diff --git a/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h
index 83d5fdcdc7..fe835881f5 100644
--- a/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h
+++ b/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h
@@ -120,7 +120,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
     int i;
     for (i = 0; i < (int)rd_len; i++) {
         if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
-        buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
+        buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte);
     }
     return i;
 }
@@ -139,7 +139,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
     int i;
     for (i = 0; i < (int)wr_len; i++) {
         if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
-        USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
+        HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]);
     }
     return i;
 }
diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt
index 5c95fddb84..90e0569f19 100644
--- a/components/soc/CMakeLists.txt
+++ b/components/soc/CMakeLists.txt
@@ -18,9 +18,13 @@ if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/include")
     list(APPEND includes "${target_folder}/include")
 endif()
 
-if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register")
-    # register headers that generated by script from CSV
-    list(APPEND includes "${target_folder}/register")
+# register headers that generated by script from CSV
+if(CONFIG_IDF_TARGET_ESP32P4)
+    list(APPEND includes "${target_folder}/register/hw_ver1")
+else()
+    if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register")
+        list(APPEND includes "${target_folder}/register")
+    endif()
 endif()
 
 if(target STREQUAL "esp32")
diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h
index e8e79a9d07..d36ecc9e29 100644
--- a/components/soc/esp32p4/include/soc/soc.h
+++ b/components/soc/esp32p4/include/soc/soc.h
@@ -224,6 +224,7 @@
 #define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
 
 // Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START_REV2    0x4ffbcfc0
 #define SOC_ROM_STACK_START         0x4ff3cfc0
 #define SOC_ROM_STACK_SIZE          0x2000
 
diff --git a/components/soc/esp32p4/register/soc/adc_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/adc_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/adc_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/adc_reg.h
diff --git a/components/soc/esp32p4/register/soc/adc_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/adc_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/adc_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/adc_struct.h
diff --git a/components/soc/esp32p4/register/soc/aes_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/aes_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/aes_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/aes_reg.h
diff --git a/components/soc/esp32p4/register/soc/aes_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/aes_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/aes_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/aes_struct.h
diff --git a/components/soc/esp32p4/register/soc/ahb_dma_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/ahb_dma_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/ahb_dma_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/ahb_dma_reg.h
diff --git a/components/soc/esp32p4/register/soc/ahb_dma_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/ahb_dma_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/ahb_dma_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/ahb_dma_struct.h
diff --git a/components/soc/esp32p4/register/soc/assist_debug_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/assist_debug_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/assist_debug_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/assist_debug_reg.h
diff --git a/components/soc/esp32p4/register/soc/assist_debug_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/assist_debug_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/assist_debug_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/assist_debug_struct.h
diff --git a/components/soc/esp32p4/register/soc/axi_dma_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/axi_dma_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/axi_dma_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/axi_dma_reg.h
diff --git a/components/soc/esp32p4/register/soc/axi_dma_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/axi_dma_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/axi_dma_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/axi_dma_struct.h
diff --git a/components/soc/esp32p4/register/soc/bitscrambler_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/bitscrambler_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/bitscrambler_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/bitscrambler_reg.h
diff --git a/components/soc/esp32p4/register/soc/bitscrambler_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/bitscrambler_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/bitscrambler_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/bitscrambler_struct.h
diff --git a/components/soc/esp32p4/register/soc/cache_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/cache_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/cache_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/cache_reg.h
diff --git a/components/soc/esp32p4/register/soc/cache_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/cache_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/cache_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/cache_struct.h
diff --git a/components/soc/esp32p4/register/soc/dma2d_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/dma2d_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/dma2d_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/dma2d_reg.h
diff --git a/components/soc/esp32p4/register/soc/dma2d_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/dma2d_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h
diff --git a/components/soc/esp32p4/register/soc/dma_pms_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/dma_pms_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/dma_pms_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/dma_pms_reg.h
diff --git a/components/soc/esp32p4/register/soc/dma_pms_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/dma_pms_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/dma_pms_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/dma_pms_struct.h
diff --git a/components/soc/esp32p4/register/soc/ds_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/ds_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/ds_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/ds_reg.h
diff --git a/components/soc/esp32p4/register/soc/ds_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/ds_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/ds_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/ds_struct.h
diff --git a/components/soc/esp32p4/register/soc/dw_gdma_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/dw_gdma_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/dw_gdma_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/dw_gdma_reg.h
diff --git a/components/soc/esp32p4/register/soc/dw_gdma_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/dw_gdma_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/dw_gdma_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/dw_gdma_struct.h
diff --git a/components/soc/esp32p4/register/soc/ecc_mult_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/ecc_mult_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/ecc_mult_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/ecc_mult_reg.h
diff --git a/components/soc/esp32p4/register/soc/ecc_mult_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/ecc_mult_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/ecc_mult_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/ecc_mult_struct.h
diff --git a/components/soc/esp32p4/register/soc/ecdsa_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/ecdsa_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/ecdsa_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/ecdsa_reg.h
diff --git a/components/soc/esp32p4/register/soc/ecdsa_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/ecdsa_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/ecdsa_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/ecdsa_struct.h
diff --git a/components/soc/esp32p4/register/soc/efuse_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/efuse_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/efuse_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/efuse_reg.h
diff --git a/components/soc/esp32p4/register/soc/efuse_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/efuse_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/efuse_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/efuse_struct.h
diff --git a/components/soc/esp32p4/register/soc/emac_dma_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/emac_dma_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/emac_dma_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/emac_dma_struct.h
diff --git a/components/soc/esp32p4/register/soc/emac_mac_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/emac_mac_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/emac_mac_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/emac_mac_struct.h
diff --git a/components/soc/esp32p4/register/soc/emac_ptp_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/emac_ptp_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/emac_ptp_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/emac_ptp_struct.h
diff --git a/components/soc/esp32p4/register/soc/gpio_ext_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/gpio_ext_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/gpio_ext_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/gpio_ext_reg.h
diff --git a/components/soc/esp32p4/register/soc/gpio_ext_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/gpio_ext_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/gpio_ext_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/gpio_ext_struct.h
diff --git a/components/soc/esp32p4/register/soc/gpio_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/gpio_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/gpio_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/gpio_reg.h
diff --git a/components/soc/esp32p4/register/soc/gpio_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/gpio_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/gpio_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/gpio_struct.h
diff --git a/components/soc/esp32p4/register/soc/h264_dma_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/h264_dma_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/h264_dma_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/h264_dma_reg.h
diff --git a/components/soc/esp32p4/register/soc/h264_dma_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/h264_dma_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/h264_dma_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/h264_dma_struct.h
diff --git a/components/soc/esp32p4/register/soc/h264_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/h264_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/h264_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/h264_reg.h
diff --git a/components/soc/esp32p4/register/soc/h264_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/h264_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/h264_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/h264_struct.h
diff --git a/components/soc/esp32p4/register/soc/hmac_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/hmac_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/hmac_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/hmac_reg.h
diff --git a/components/soc/esp32p4/register/soc/hmac_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/hmac_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/hmac_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/hmac_struct.h
diff --git a/components/soc/esp32p4/register/soc/hp2lp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/hp2lp_peri_pms_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/hp2lp_peri_pms_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/hp2lp_peri_pms_reg.h
diff --git a/components/soc/esp32p4/register/soc/hp2lp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/hp2lp_peri_pms_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/hp2lp_peri_pms_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/hp2lp_peri_pms_struct.h
diff --git a/components/soc/esp32p4/register/soc/hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/hp_peri_pms_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/hp_peri_pms_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/hp_peri_pms_reg.h
diff --git a/components/soc/esp32p4/register/soc/hp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/hp_peri_pms_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/hp_peri_pms_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/hp_peri_pms_struct.h
diff --git a/components/soc/esp32p4/register/soc/hp_sys_clkrst_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/hp_sys_clkrst_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/hp_sys_clkrst_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/hp_sys_clkrst_reg.h
diff --git a/components/soc/esp32p4/register/soc/hp_sys_clkrst_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/hp_sys_clkrst_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/hp_sys_clkrst_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/hp_sys_clkrst_struct.h
diff --git a/components/soc/esp32p4/register/soc/hp_system_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/hp_system_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/hp_system_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/hp_system_reg.h
diff --git a/components/soc/esp32p4/register/soc/hp_system_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/hp_system_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/hp_system_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/hp_system_struct.h
diff --git a/components/soc/esp32p4/register/soc/huk_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/huk_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/huk_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/huk_reg.h
diff --git a/components/soc/esp32p4/register/soc/huk_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/huk_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/huk_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/huk_struct.h
diff --git a/components/soc/esp32p4/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/i2c_ana_mst_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_reg.h
diff --git a/components/soc/esp32p4/register/soc/i2c_ana_mst_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/i2c_ana_mst_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_struct.h
diff --git a/components/soc/esp32p4/register/soc/i2c_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/i2c_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/i2c_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/i2c_reg.h
diff --git a/components/soc/esp32p4/register/soc/i2c_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/i2c_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/i2c_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/i2c_struct.h
diff --git a/components/soc/esp32p4/register/soc/i2s_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/i2s_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h
diff --git a/components/soc/esp32p4/register/soc/i2s_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/i2s_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/i2s_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/i2s_struct.h
diff --git a/components/soc/esp32p4/register/soc/i3c_mst_mem_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/i3c_mst_mem_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/i3c_mst_mem_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/i3c_mst_mem_reg.h
diff --git a/components/soc/esp32p4/register/soc/i3c_mst_mem_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/i3c_mst_mem_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/i3c_mst_mem_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/i3c_mst_mem_struct.h
diff --git a/components/soc/esp32p4/register/soc/i3c_mst_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/i3c_mst_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/i3c_mst_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/i3c_mst_reg.h
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rename to components/soc/esp32p4/register/hw_ver1/soc/mipi_csi_host_struct.h
diff --git a/components/soc/esp32p4/register/soc/mipi_dsi_bridge_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/mipi_dsi_bridge_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/mipi_dsi_bridge_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/mipi_dsi_bridge_reg.h
diff --git a/components/soc/esp32p4/register/soc/mipi_dsi_bridge_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/mipi_dsi_bridge_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/mipi_dsi_bridge_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/mipi_dsi_bridge_struct.h
diff --git a/components/soc/esp32p4/register/soc/mipi_dsi_host_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/mipi_dsi_host_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/mipi_dsi_host_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/mipi_dsi_host_reg.h
diff --git a/components/soc/esp32p4/register/soc/mipi_dsi_host_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/mipi_dsi_host_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/mipi_dsi_host_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/mipi_dsi_host_struct.h
diff --git a/components/soc/esp32p4/register/soc/parl_io_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/parl_io_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/parl_io_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/parl_io_reg.h
diff --git a/components/soc/esp32p4/register/soc/parl_io_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/parl_io_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/parl_io_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/parl_io_struct.h
diff --git a/components/soc/esp32p4/register/soc/pau_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/pau_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/pau_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/pau_reg.h
diff --git a/components/soc/esp32p4/register/soc/pau_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/pau_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/pau_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/pau_struct.h
diff --git a/components/soc/esp32p4/register/soc/pcnt_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/pcnt_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/pcnt_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/pcnt_reg.h
diff --git a/components/soc/esp32p4/register/soc/pcnt_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/pcnt_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/pcnt_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/pcnt_struct.h
diff --git a/components/soc/esp32p4/register/soc/pmu_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/pmu_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/pmu_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/pmu_reg.h
diff --git a/components/soc/esp32p4/register/soc/pmu_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/pmu_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/pmu_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/pmu_struct.h
diff --git a/components/soc/esp32p4/register/soc/ppa_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/ppa_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/ppa_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/ppa_reg.h
diff --git a/components/soc/esp32p4/register/soc/ppa_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/ppa_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/ppa_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/ppa_struct.h
diff --git a/components/soc/esp32p4/register/soc/pvt_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/pvt_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/pvt_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/pvt_reg.h
diff --git a/components/soc/esp32p4/register/soc/pvt_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/pvt_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/pvt_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/pvt_struct.h
diff --git a/components/soc/esp32p4/register/soc/reg_base.h b/components/soc/esp32p4/register/hw_ver1/soc/reg_base.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/reg_base.h
rename to components/soc/esp32p4/register/hw_ver1/soc/reg_base.h
diff --git a/components/soc/esp32p4/register/soc/rmt_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/rmt_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/rmt_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/rmt_reg.h
diff --git a/components/soc/esp32p4/register/soc/rmt_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/rmt_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/rmt_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/rmt_struct.h
diff --git a/components/soc/esp32p4/register/soc/rsa_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/rsa_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/rsa_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/rsa_reg.h
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similarity index 100%
rename from components/soc/esp32p4/register/soc/rsa_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/rsa_struct.h
diff --git a/components/soc/esp32p4/register/soc/rtclockcali_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/rtclockcali_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/rtclockcali_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/rtclockcali_reg.h
diff --git a/components/soc/esp32p4/register/soc/rtclockcali_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/rtclockcali_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/rtclockcali_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/rtclockcali_struct.h
diff --git a/components/soc/esp32p4/register/soc/sdmmc_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/sdmmc_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/sdmmc_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/sdmmc_reg.h
diff --git a/components/soc/esp32p4/register/soc/sdmmc_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/sdmmc_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/sdmmc_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/sdmmc_struct.h
diff --git a/components/soc/esp32p4/register/soc/sha_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/sha_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/sha_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/sha_reg.h
diff --git a/components/soc/esp32p4/register/soc/sha_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/sha_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/sha_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/sha_struct.h
diff --git a/components/soc/esp32p4/register/soc/soc_etm_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/soc_etm_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/soc_etm_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/soc_etm_reg.h
diff --git a/components/soc/esp32p4/register/soc/soc_etm_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/soc_etm_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/soc_etm_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/soc_etm_struct.h
diff --git a/components/soc/esp32p4/register/soc/spi1_mem_c_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/spi1_mem_c_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/spi1_mem_c_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/spi1_mem_c_reg.h
diff --git a/components/soc/esp32p4/register/soc/spi1_mem_c_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/spi1_mem_c_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/spi1_mem_c_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/spi1_mem_c_struct.h
diff --git a/components/soc/esp32p4/register/soc/spi1_mem_s_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/spi1_mem_s_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/spi1_mem_s_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/spi1_mem_s_reg.h
diff --git a/components/soc/esp32p4/register/soc/spi1_mem_s_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/spi1_mem_s_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/spi1_mem_s_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/spi1_mem_s_struct.h
diff --git a/components/soc/esp32p4/register/soc/spi_mem_c_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/spi_mem_c_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/spi_mem_c_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/spi_mem_c_reg.h
diff --git a/components/soc/esp32p4/register/soc/spi_mem_c_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/spi_mem_c_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/spi_mem_c_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/spi_mem_c_struct.h
diff --git a/components/soc/esp32p4/register/soc/spi_mem_s_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/spi_mem_s_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/spi_mem_s_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/spi_mem_s_reg.h
diff --git a/components/soc/esp32p4/register/soc/spi_mem_s_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/spi_mem_s_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/spi_mem_s_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/spi_mem_s_struct.h
diff --git a/components/soc/esp32p4/register/soc/spi_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/spi_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/spi_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/spi_reg.h
diff --git a/components/soc/esp32p4/register/soc/spi_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/spi_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/spi_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/spi_struct.h
diff --git a/components/soc/esp32p4/register/soc/systimer_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/systimer_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/systimer_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/systimer_reg.h
diff --git a/components/soc/esp32p4/register/soc/systimer_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/systimer_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/systimer_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/systimer_struct.h
diff --git a/components/soc/esp32p4/register/soc/tcm_monitor_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/tcm_monitor_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/tcm_monitor_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/tcm_monitor_reg.h
diff --git a/components/soc/esp32p4/register/soc/tcm_monitor_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/tcm_monitor_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/tcm_monitor_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/tcm_monitor_struct.h
diff --git a/components/soc/esp32p4/register/soc/timer_group_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/timer_group_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/timer_group_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/timer_group_reg.h
diff --git a/components/soc/esp32p4/register/soc/timer_group_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/timer_group_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/timer_group_struct.h
diff --git a/components/soc/esp32p4/register/soc/touch_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/touch_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/touch_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/touch_reg.h
diff --git a/components/soc/esp32p4/register/soc/touch_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/touch_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/touch_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/touch_struct.h
diff --git a/components/soc/esp32p4/register/soc/trace_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/trace_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/trace_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/trace_reg.h
diff --git a/components/soc/esp32p4/register/soc/trace_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/trace_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/trace_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/trace_struct.h
diff --git a/components/soc/esp32p4/register/soc/tsens_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/tsens_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/tsens_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/tsens_reg.h
diff --git a/components/soc/esp32p4/register/soc/tsens_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/tsens_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/tsens_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/tsens_struct.h
diff --git a/components/soc/esp32p4/register/soc/twai_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/twai_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/twai_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/twai_reg.h
diff --git a/components/soc/esp32p4/register/soc/twai_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/twai_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/twai_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/twai_struct.h
diff --git a/components/soc/esp32p4/register/soc/uart_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/uart_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/uart_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/uart_reg.h
diff --git a/components/soc/esp32p4/register/soc/uart_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/uart_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/uart_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/uart_struct.h
diff --git a/components/soc/esp32p4/register/soc/uhci_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/uhci_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/uhci_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/uhci_reg.h
diff --git a/components/soc/esp32p4/register/soc/uhci_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/uhci_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/uhci_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/uhci_struct.h
diff --git a/components/soc/esp32p4/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/usb_serial_jtag_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/usb_serial_jtag_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/usb_serial_jtag_reg.h
diff --git a/components/soc/esp32p4/register/soc/usb_serial_jtag_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/usb_serial_jtag_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/usb_serial_jtag_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/usb_serial_jtag_struct.h
diff --git a/components/soc/esp32p4/register/soc/usb_utmi_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/usb_utmi_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/usb_utmi_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/usb_utmi_struct.h
diff --git a/components/soc/esp32p4/register/soc/usb_wrap_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/usb_wrap_reg.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/usb_wrap_reg.h
rename to components/soc/esp32p4/register/hw_ver1/soc/usb_wrap_reg.h
diff --git a/components/soc/esp32p4/register/soc/usb_wrap_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/usb_wrap_struct.h
similarity index 100%
rename from components/soc/esp32p4/register/soc/usb_wrap_struct.h
rename to components/soc/esp32p4/register/hw_ver1/soc/usb_wrap_struct.h
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/adc_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/adc_eco5_reg.h
new file mode 100644
index 0000000000..2315ba5af2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/adc_eco5_reg.h
@@ -0,0 +1,787 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ADC_CTRL_REG_REG register
+ *  Register
+ */
+#define ADC_CTRL_REG_REG (DR_REG_ADC_BASE + 0x0)
+/** ADC_START_FORCE : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_START_FORCE    (BIT(0))
+#define ADC_START_FORCE_M  (ADC_START_FORCE_V << ADC_START_FORCE_S)
+#define ADC_START_FORCE_V  0x00000001U
+#define ADC_START_FORCE_S  0
+/** ADC_START : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_START    (BIT(1))
+#define ADC_START_M  (ADC_START_V << ADC_START_S)
+#define ADC_START_V  0x00000001U
+#define ADC_START_S  1
+/** ADC_WORK_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  0: single mode, 1: double mode, 2: alternate mode
+ */
+#define ADC_WORK_MODE    0x00000003U
+#define ADC_WORK_MODE_M  (ADC_WORK_MODE_V << ADC_WORK_MODE_S)
+#define ADC_WORK_MODE_V  0x00000003U
+#define ADC_WORK_MODE_S  2
+/** ADC_SAR_SEL : R/W; bitpos: [4]; default: 0;
+ *  0: SAR1, 1: SAR2, only work for single SAR mode
+ */
+#define ADC_SAR_SEL    (BIT(4))
+#define ADC_SAR_SEL_M  (ADC_SAR_SEL_V << ADC_SAR_SEL_S)
+#define ADC_SAR_SEL_V  0x00000001U
+#define ADC_SAR_SEL_S  4
+/** ADC_SAR_CLK_GATED : R/W; bitpos: [5]; default: 1;
+ *  need_des
+ */
+#define ADC_SAR_CLK_GATED    (BIT(5))
+#define ADC_SAR_CLK_GATED_M  (ADC_SAR_CLK_GATED_V << ADC_SAR_CLK_GATED_S)
+#define ADC_SAR_CLK_GATED_V  0x00000001U
+#define ADC_SAR_CLK_GATED_S  5
+/** ADC_SAR_CLK_DIV : R/W; bitpos: [13:6]; default: 4;
+ *  SAR clock divider
+ */
+#define ADC_SAR_CLK_DIV    0x000000FFU
+#define ADC_SAR_CLK_DIV_M  (ADC_SAR_CLK_DIV_V << ADC_SAR_CLK_DIV_S)
+#define ADC_SAR_CLK_DIV_V  0x000000FFU
+#define ADC_SAR_CLK_DIV_S  6
+/** ADC_SAR1_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define ADC_SAR1_PATT_LEN    0x0000000FU
+#define ADC_SAR1_PATT_LEN_M  (ADC_SAR1_PATT_LEN_V << ADC_SAR1_PATT_LEN_S)
+#define ADC_SAR1_PATT_LEN_V  0x0000000FU
+#define ADC_SAR1_PATT_LEN_S  14
+/** ADC_SAR2_PATT_LEN : R/W; bitpos: [21:18]; default: 15;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define ADC_SAR2_PATT_LEN    0x0000000FU
+#define ADC_SAR2_PATT_LEN_M  (ADC_SAR2_PATT_LEN_V << ADC_SAR2_PATT_LEN_S)
+#define ADC_SAR2_PATT_LEN_V  0x0000000FU
+#define ADC_SAR2_PATT_LEN_S  18
+/** ADC_SAR1_PATT_P_CLEAR : R/W; bitpos: [22]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC1 CTRL
+ */
+#define ADC_SAR1_PATT_P_CLEAR    (BIT(22))
+#define ADC_SAR1_PATT_P_CLEAR_M  (ADC_SAR1_PATT_P_CLEAR_V << ADC_SAR1_PATT_P_CLEAR_S)
+#define ADC_SAR1_PATT_P_CLEAR_V  0x00000001U
+#define ADC_SAR1_PATT_P_CLEAR_S  22
+/** ADC_SAR2_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC2 CTRL
+ */
+#define ADC_SAR2_PATT_P_CLEAR    (BIT(23))
+#define ADC_SAR2_PATT_P_CLEAR_M  (ADC_SAR2_PATT_P_CLEAR_V << ADC_SAR2_PATT_P_CLEAR_S)
+#define ADC_SAR2_PATT_P_CLEAR_V  0x00000001U
+#define ADC_SAR2_PATT_P_CLEAR_S  23
+/** ADC_DATA_SAR_SEL : R/W; bitpos: [24]; default: 0;
+ *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+ *  resolution should not be larger than 11 bits.
+ */
+#define ADC_DATA_SAR_SEL    (BIT(24))
+#define ADC_DATA_SAR_SEL_M  (ADC_DATA_SAR_SEL_V << ADC_DATA_SAR_SEL_S)
+#define ADC_DATA_SAR_SEL_V  0x00000001U
+#define ADC_DATA_SAR_SEL_S  24
+/** ADC_DATA_TO_I2S : R/W; bitpos: [25]; default: 0;
+ *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+ */
+#define ADC_DATA_TO_I2S    (BIT(25))
+#define ADC_DATA_TO_I2S_M  (ADC_DATA_TO_I2S_V << ADC_DATA_TO_I2S_S)
+#define ADC_DATA_TO_I2S_V  0x00000001U
+#define ADC_DATA_TO_I2S_S  25
+/** ADC_XPD_SAR1_FORCE : R/W; bitpos: [27:26]; default: 0;
+ *  force option to xpd sar1 blocks
+ */
+#define ADC_XPD_SAR1_FORCE    0x00000003U
+#define ADC_XPD_SAR1_FORCE_M  (ADC_XPD_SAR1_FORCE_V << ADC_XPD_SAR1_FORCE_S)
+#define ADC_XPD_SAR1_FORCE_V  0x00000003U
+#define ADC_XPD_SAR1_FORCE_S  26
+/** ADC_XPD_SAR2_FORCE : R/W; bitpos: [29:28]; default: 0;
+ *  force option to xpd sar2 blocks
+ */
+#define ADC_XPD_SAR2_FORCE    0x00000003U
+#define ADC_XPD_SAR2_FORCE_M  (ADC_XPD_SAR2_FORCE_V << ADC_XPD_SAR2_FORCE_S)
+#define ADC_XPD_SAR2_FORCE_V  0x00000003U
+#define ADC_XPD_SAR2_FORCE_S  28
+/** ADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
+ *  wait arbit signal stable after sar_done
+ */
+#define ADC_WAIT_ARB_CYCLE    0x00000003U
+#define ADC_WAIT_ARB_CYCLE_M  (ADC_WAIT_ARB_CYCLE_V << ADC_WAIT_ARB_CYCLE_S)
+#define ADC_WAIT_ARB_CYCLE_V  0x00000003U
+#define ADC_WAIT_ARB_CYCLE_S  30
+
+/** ADC_CTRL2_REG register
+ *  Register
+ */
+#define ADC_CTRL2_REG (DR_REG_ADC_BASE + 0x4)
+/** ADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_MEAS_NUM_LIMIT    (BIT(0))
+#define ADC_MEAS_NUM_LIMIT_M  (ADC_MEAS_NUM_LIMIT_V << ADC_MEAS_NUM_LIMIT_S)
+#define ADC_MEAS_NUM_LIMIT_V  0x00000001U
+#define ADC_MEAS_NUM_LIMIT_S  0
+/** ADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
+ *  max conversion number
+ */
+#define ADC_MAX_MEAS_NUM    0x000000FFU
+#define ADC_MAX_MEAS_NUM_M  (ADC_MAX_MEAS_NUM_V << ADC_MAX_MEAS_NUM_S)
+#define ADC_MAX_MEAS_NUM_V  0x000000FFU
+#define ADC_MAX_MEAS_NUM_S  1
+/** ADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
+ *  1: data to DIG ADC1 CTRL is inverted, otherwise not
+ */
+#define ADC_SAR1_INV    (BIT(9))
+#define ADC_SAR1_INV_M  (ADC_SAR1_INV_V << ADC_SAR1_INV_S)
+#define ADC_SAR1_INV_V  0x00000001U
+#define ADC_SAR1_INV_S  9
+/** ADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
+ *  1: data to DIG ADC2 CTRL is inverted, otherwise not
+ */
+#define ADC_SAR2_INV    (BIT(10))
+#define ADC_SAR2_INV_M  (ADC_SAR2_INV_V << ADC_SAR2_INV_S)
+#define ADC_SAR2_INV_V  0x00000001U
+#define ADC_SAR2_INV_S  10
+/** ADC_TIMER_SEL : R/W; bitpos: [11]; default: 0;
+ *  1: select saradc timer 0: i2s_ws trigger
+ */
+#define ADC_TIMER_SEL    (BIT(11))
+#define ADC_TIMER_SEL_M  (ADC_TIMER_SEL_V << ADC_TIMER_SEL_S)
+#define ADC_TIMER_SEL_V  0x00000001U
+#define ADC_TIMER_SEL_S  11
+/** ADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
+ *  to set saradc timer target
+ */
+#define ADC_TIMER_TARGET    0x00000FFFU
+#define ADC_TIMER_TARGET_M  (ADC_TIMER_TARGET_V << ADC_TIMER_TARGET_S)
+#define ADC_TIMER_TARGET_V  0x00000FFFU
+#define ADC_TIMER_TARGET_S  12
+/** ADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
+ *  to enable saradc timer trigger
+ */
+#define ADC_TIMER_EN    (BIT(24))
+#define ADC_TIMER_EN_M  (ADC_TIMER_EN_V << ADC_TIMER_EN_S)
+#define ADC_TIMER_EN_V  0x00000001U
+#define ADC_TIMER_EN_S  24
+
+/** ADC_FILTER_CTRL1_REG register
+ *  Register
+ */
+#define ADC_FILTER_CTRL1_REG (DR_REG_ADC_BASE + 0x8)
+/** ADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
+ *  need_des
+ */
+#define ADC_FILTER_FACTOR1    0x00000007U
+#define ADC_FILTER_FACTOR1_M  (ADC_FILTER_FACTOR1_V << ADC_FILTER_FACTOR1_S)
+#define ADC_FILTER_FACTOR1_V  0x00000007U
+#define ADC_FILTER_FACTOR1_S  26
+/** ADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
+ *  need_des
+ */
+#define ADC_FILTER_FACTOR0    0x00000007U
+#define ADC_FILTER_FACTOR0_M  (ADC_FILTER_FACTOR0_V << ADC_FILTER_FACTOR0_S)
+#define ADC_FILTER_FACTOR0_V  0x00000007U
+#define ADC_FILTER_FACTOR0_S  29
+
+/** ADC_SAR1_PATT_TAB1_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x18)
+/** ADC_SAR1_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
+ *  item 0 ~ 3 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB1    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB1_M  (ADC_SAR1_PATT_TAB1_V << ADC_SAR1_PATT_TAB1_S)
+#define ADC_SAR1_PATT_TAB1_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB1_S  0
+
+/** ADC_SAR1_PATT_TAB2_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x1c)
+/** ADC_SAR1_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 4 ~ 7 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB2    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB2_M  (ADC_SAR1_PATT_TAB2_V << ADC_SAR1_PATT_TAB2_S)
+#define ADC_SAR1_PATT_TAB2_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB2_S  0
+
+/** ADC_SAR1_PATT_TAB3_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x20)
+/** ADC_SAR1_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 8 ~ 11 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB3    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB3_M  (ADC_SAR1_PATT_TAB3_V << ADC_SAR1_PATT_TAB3_S)
+#define ADC_SAR1_PATT_TAB3_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB3_S  0
+
+/** ADC_SAR1_PATT_TAB4_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x24)
+/** ADC_SAR1_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 12 ~ 15 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB4    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB4_M  (ADC_SAR1_PATT_TAB4_V << ADC_SAR1_PATT_TAB4_S)
+#define ADC_SAR1_PATT_TAB4_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB4_S  0
+
+/** ADC_SAR2_PATT_TAB1_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x28)
+/** ADC_SAR2_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
+ *  item 0 ~ 3 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB1    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB1_M  (ADC_SAR2_PATT_TAB1_V << ADC_SAR2_PATT_TAB1_S)
+#define ADC_SAR2_PATT_TAB1_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB1_S  0
+
+/** ADC_SAR2_PATT_TAB2_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x2c)
+/** ADC_SAR2_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 4 ~ 7 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB2    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB2_M  (ADC_SAR2_PATT_TAB2_V << ADC_SAR2_PATT_TAB2_S)
+#define ADC_SAR2_PATT_TAB2_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB2_S  0
+
+/** ADC_SAR2_PATT_TAB3_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x30)
+/** ADC_SAR2_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 8 ~ 11 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB3    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB3_M  (ADC_SAR2_PATT_TAB3_V << ADC_SAR2_PATT_TAB3_S)
+#define ADC_SAR2_PATT_TAB3_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB3_S  0
+
+/** ADC_SAR2_PATT_TAB4_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x34)
+/** ADC_SAR2_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 12 ~ 15 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB4    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB4_M  (ADC_SAR2_PATT_TAB4_V << ADC_SAR2_PATT_TAB4_S)
+#define ADC_SAR2_PATT_TAB4_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB4_S  0
+
+/** ADC_ARB_CTRL_REG register
+ *  Register
+ */
+#define ADC_ARB_CTRL_REG (DR_REG_ADC_BASE + 0x38)
+/** ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
+ *  adc2 arbiter force to enableapb controller
+ */
+#define ADC_ARB_APB_FORCE    (BIT(2))
+#define ADC_ARB_APB_FORCE_M  (ADC_ARB_APB_FORCE_V << ADC_ARB_APB_FORCE_S)
+#define ADC_ARB_APB_FORCE_V  0x00000001U
+#define ADC_ARB_APB_FORCE_S  2
+/** ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
+ *  adc2 arbiter force to enable rtc controller
+ */
+#define ADC_ARB_RTC_FORCE    (BIT(3))
+#define ADC_ARB_RTC_FORCE_M  (ADC_ARB_RTC_FORCE_V << ADC_ARB_RTC_FORCE_S)
+#define ADC_ARB_RTC_FORCE_V  0x00000001U
+#define ADC_ARB_RTC_FORCE_S  3
+/** ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
+ *  adc2 arbiter force to enable wifi controller
+ */
+#define ADC_ARB_WIFI_FORCE    (BIT(4))
+#define ADC_ARB_WIFI_FORCE_M  (ADC_ARB_WIFI_FORCE_V << ADC_ARB_WIFI_FORCE_S)
+#define ADC_ARB_WIFI_FORCE_V  0x00000001U
+#define ADC_ARB_WIFI_FORCE_S  4
+/** ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
+ *  adc2 arbiter force grant
+ */
+#define ADC_ARB_GRANT_FORCE    (BIT(5))
+#define ADC_ARB_GRANT_FORCE_M  (ADC_ARB_GRANT_FORCE_V << ADC_ARB_GRANT_FORCE_S)
+#define ADC_ARB_GRANT_FORCE_V  0x00000001U
+#define ADC_ARB_GRANT_FORCE_S  5
+/** ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
+ *  Set adc2 arbiterapb priority
+ */
+#define ADC_ARB_APB_PRIORITY    0x00000003U
+#define ADC_ARB_APB_PRIORITY_M  (ADC_ARB_APB_PRIORITY_V << ADC_ARB_APB_PRIORITY_S)
+#define ADC_ARB_APB_PRIORITY_V  0x00000003U
+#define ADC_ARB_APB_PRIORITY_S  6
+/** ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
+ *  Set adc2 arbiter rtc priority
+ */
+#define ADC_ARB_RTC_PRIORITY    0x00000003U
+#define ADC_ARB_RTC_PRIORITY_M  (ADC_ARB_RTC_PRIORITY_V << ADC_ARB_RTC_PRIORITY_S)
+#define ADC_ARB_RTC_PRIORITY_V  0x00000003U
+#define ADC_ARB_RTC_PRIORITY_S  8
+/** ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
+ *  Set adc2 arbiter wifi priority
+ */
+#define ADC_ARB_WIFI_PRIORITY    0x00000003U
+#define ADC_ARB_WIFI_PRIORITY_M  (ADC_ARB_WIFI_PRIORITY_V << ADC_ARB_WIFI_PRIORITY_S)
+#define ADC_ARB_WIFI_PRIORITY_V  0x00000003U
+#define ADC_ARB_WIFI_PRIORITY_S  10
+/** ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
+ *  adc2 arbiter uses fixed priority
+ */
+#define ADC_ARB_FIX_PRIORITY    (BIT(12))
+#define ADC_ARB_FIX_PRIORITY_M  (ADC_ARB_FIX_PRIORITY_V << ADC_ARB_FIX_PRIORITY_S)
+#define ADC_ARB_FIX_PRIORITY_V  0x00000001U
+#define ADC_ARB_FIX_PRIORITY_S  12
+
+/** ADC_FILTER_CTRL0_REG register
+ *  Register
+ */
+#define ADC_FILTER_CTRL0_REG (DR_REG_ADC_BASE + 0x3c)
+/** ADC_FILTER_CHANNEL1 : R/W; bitpos: [18:14]; default: 13;
+ *  need_des
+ */
+#define ADC_FILTER_CHANNEL1    0x0000001FU
+#define ADC_FILTER_CHANNEL1_M  (ADC_FILTER_CHANNEL1_V << ADC_FILTER_CHANNEL1_S)
+#define ADC_FILTER_CHANNEL1_V  0x0000001FU
+#define ADC_FILTER_CHANNEL1_S  14
+/** ADC_FILTER_CHANNEL0 : R/W; bitpos: [23:19]; default: 13;
+ *  apb_adc1_filter_factor
+ */
+#define ADC_FILTER_CHANNEL0    0x0000001FU
+#define ADC_FILTER_CHANNEL0_M  (ADC_FILTER_CHANNEL0_V << ADC_FILTER_CHANNEL0_S)
+#define ADC_FILTER_CHANNEL0_V  0x0000001FU
+#define ADC_FILTER_CHANNEL0_S  19
+/** ADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc1_filter
+ */
+#define ADC_FILTER_RESET    (BIT(31))
+#define ADC_FILTER_RESET_M  (ADC_FILTER_RESET_V << ADC_FILTER_RESET_S)
+#define ADC_FILTER_RESET_V  0x00000001U
+#define ADC_FILTER_RESET_S  31
+
+/** ADC_SAR1_DATA_STATUS_REG register
+ *  Register
+ */
+#define ADC_SAR1_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x40)
+/** ADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DATA    0x0001FFFFU
+#define ADC_APB_SARADC1_DATA_M  (ADC_APB_SARADC1_DATA_V << ADC_APB_SARADC1_DATA_S)
+#define ADC_APB_SARADC1_DATA_V  0x0001FFFFU
+#define ADC_APB_SARADC1_DATA_S  0
+
+/** ADC_THRES0_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES0_CTRL_REG (DR_REG_ADC_BASE + 0x44)
+/** ADC_THRES0_CHANNEL : R/W; bitpos: [4:0]; default: 13;
+ *  need_des
+ */
+#define ADC_THRES0_CHANNEL    0x0000001FU
+#define ADC_THRES0_CHANNEL_M  (ADC_THRES0_CHANNEL_V << ADC_THRES0_CHANNEL_S)
+#define ADC_THRES0_CHANNEL_V  0x0000001FU
+#define ADC_THRES0_CHANNEL_S  0
+/** ADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES0_HIGH    0x00001FFFU
+#define ADC_THRES0_HIGH_M  (ADC_THRES0_HIGH_V << ADC_THRES0_HIGH_S)
+#define ADC_THRES0_HIGH_V  0x00001FFFU
+#define ADC_THRES0_HIGH_S  5
+/** ADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES0_LOW    0x00001FFFU
+#define ADC_THRES0_LOW_M  (ADC_THRES0_LOW_V << ADC_THRES0_LOW_S)
+#define ADC_THRES0_LOW_V  0x00001FFFU
+#define ADC_THRES0_LOW_S  18
+
+/** ADC_THRES1_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES1_CTRL_REG (DR_REG_ADC_BASE + 0x48)
+/** ADC_THRES1_CHANNEL : R/W; bitpos: [4:0]; default: 13;
+ *  need_des
+ */
+#define ADC_THRES1_CHANNEL    0x0000001FU
+#define ADC_THRES1_CHANNEL_M  (ADC_THRES1_CHANNEL_V << ADC_THRES1_CHANNEL_S)
+#define ADC_THRES1_CHANNEL_V  0x0000001FU
+#define ADC_THRES1_CHANNEL_S  0
+/** ADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES1_HIGH    0x00001FFFU
+#define ADC_THRES1_HIGH_M  (ADC_THRES1_HIGH_V << ADC_THRES1_HIGH_S)
+#define ADC_THRES1_HIGH_V  0x00001FFFU
+#define ADC_THRES1_HIGH_S  5
+/** ADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES1_LOW    0x00001FFFU
+#define ADC_THRES1_LOW_M  (ADC_THRES1_LOW_V << ADC_THRES1_LOW_S)
+#define ADC_THRES1_LOW_V  0x00001FFFU
+#define ADC_THRES1_LOW_S  18
+
+/** ADC_THRES_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES_CTRL_REG (DR_REG_ADC_BASE + 0x4c)
+/** ADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES_ALL_EN    (BIT(27))
+#define ADC_THRES_ALL_EN_M  (ADC_THRES_ALL_EN_V << ADC_THRES_ALL_EN_S)
+#define ADC_THRES_ALL_EN_V  0x00000001U
+#define ADC_THRES_ALL_EN_S  27
+/** ADC_THRES3_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES3_EN    (BIT(28))
+#define ADC_THRES3_EN_M  (ADC_THRES3_EN_V << ADC_THRES3_EN_S)
+#define ADC_THRES3_EN_V  0x00000001U
+#define ADC_THRES3_EN_S  28
+/** ADC_THRES2_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES2_EN    (BIT(29))
+#define ADC_THRES2_EN_M  (ADC_THRES2_EN_V << ADC_THRES2_EN_S)
+#define ADC_THRES2_EN_V  0x00000001U
+#define ADC_THRES2_EN_S  29
+/** ADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_EN    (BIT(30))
+#define ADC_THRES1_EN_M  (ADC_THRES1_EN_V << ADC_THRES1_EN_S)
+#define ADC_THRES1_EN_V  0x00000001U
+#define ADC_THRES1_EN_S  30
+/** ADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_EN    (BIT(31))
+#define ADC_THRES0_EN_M  (ADC_THRES0_EN_V << ADC_THRES0_EN_S)
+#define ADC_THRES0_EN_V  0x00000001U
+#define ADC_THRES0_EN_S  31
+
+/** ADC_INT_ENA_REG register
+ *  Register
+ */
+#define ADC_INT_ENA_REG (DR_REG_ADC_BASE + 0x50)
+/** ADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_ENA    (BIT(26))
+#define ADC_THRES1_LOW_INT_ENA_M  (ADC_THRES1_LOW_INT_ENA_V << ADC_THRES1_LOW_INT_ENA_S)
+#define ADC_THRES1_LOW_INT_ENA_V  0x00000001U
+#define ADC_THRES1_LOW_INT_ENA_S  26
+/** ADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_ENA    (BIT(27))
+#define ADC_THRES0_LOW_INT_ENA_M  (ADC_THRES0_LOW_INT_ENA_V << ADC_THRES0_LOW_INT_ENA_S)
+#define ADC_THRES0_LOW_INT_ENA_V  0x00000001U
+#define ADC_THRES0_LOW_INT_ENA_S  27
+/** ADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_ENA    (BIT(28))
+#define ADC_THRES1_HIGH_INT_ENA_M  (ADC_THRES1_HIGH_INT_ENA_V << ADC_THRES1_HIGH_INT_ENA_S)
+#define ADC_THRES1_HIGH_INT_ENA_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_ENA_S  28
+/** ADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_ENA    (BIT(29))
+#define ADC_THRES0_HIGH_INT_ENA_M  (ADC_THRES0_HIGH_INT_ENA_V << ADC_THRES0_HIGH_INT_ENA_S)
+#define ADC_THRES0_HIGH_INT_ENA_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_ENA_S  29
+/** ADC_SAR2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_ENA    (BIT(30))
+#define ADC_SAR2_DONE_INT_ENA_M  (ADC_SAR2_DONE_INT_ENA_V << ADC_SAR2_DONE_INT_ENA_S)
+#define ADC_SAR2_DONE_INT_ENA_V  0x00000001U
+#define ADC_SAR2_DONE_INT_ENA_S  30
+/** ADC_SAR1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_ENA    (BIT(31))
+#define ADC_SAR1_DONE_INT_ENA_M  (ADC_SAR1_DONE_INT_ENA_V << ADC_SAR1_DONE_INT_ENA_S)
+#define ADC_SAR1_DONE_INT_ENA_V  0x00000001U
+#define ADC_SAR1_DONE_INT_ENA_S  31
+
+/** ADC_INT_RAW_REG register
+ *  Register
+ */
+#define ADC_INT_RAW_REG (DR_REG_ADC_BASE + 0x54)
+/** ADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_RAW    (BIT(26))
+#define ADC_THRES1_LOW_INT_RAW_M  (ADC_THRES1_LOW_INT_RAW_V << ADC_THRES1_LOW_INT_RAW_S)
+#define ADC_THRES1_LOW_INT_RAW_V  0x00000001U
+#define ADC_THRES1_LOW_INT_RAW_S  26
+/** ADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_RAW    (BIT(27))
+#define ADC_THRES0_LOW_INT_RAW_M  (ADC_THRES0_LOW_INT_RAW_V << ADC_THRES0_LOW_INT_RAW_S)
+#define ADC_THRES0_LOW_INT_RAW_V  0x00000001U
+#define ADC_THRES0_LOW_INT_RAW_S  27
+/** ADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_RAW    (BIT(28))
+#define ADC_THRES1_HIGH_INT_RAW_M  (ADC_THRES1_HIGH_INT_RAW_V << ADC_THRES1_HIGH_INT_RAW_S)
+#define ADC_THRES1_HIGH_INT_RAW_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_RAW_S  28
+/** ADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_RAW    (BIT(29))
+#define ADC_THRES0_HIGH_INT_RAW_M  (ADC_THRES0_HIGH_INT_RAW_V << ADC_THRES0_HIGH_INT_RAW_S)
+#define ADC_THRES0_HIGH_INT_RAW_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_RAW_S  29
+/** ADC_SAR2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_RAW    (BIT(30))
+#define ADC_SAR2_DONE_INT_RAW_M  (ADC_SAR2_DONE_INT_RAW_V << ADC_SAR2_DONE_INT_RAW_S)
+#define ADC_SAR2_DONE_INT_RAW_V  0x00000001U
+#define ADC_SAR2_DONE_INT_RAW_S  30
+/** ADC_SAR1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_RAW    (BIT(31))
+#define ADC_SAR1_DONE_INT_RAW_M  (ADC_SAR1_DONE_INT_RAW_V << ADC_SAR1_DONE_INT_RAW_S)
+#define ADC_SAR1_DONE_INT_RAW_V  0x00000001U
+#define ADC_SAR1_DONE_INT_RAW_S  31
+
+/** ADC_INT_ST_REG register
+ *  Register
+ */
+#define ADC_INT_ST_REG (DR_REG_ADC_BASE + 0x58)
+/** ADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_ST    (BIT(26))
+#define ADC_THRES1_LOW_INT_ST_M  (ADC_THRES1_LOW_INT_ST_V << ADC_THRES1_LOW_INT_ST_S)
+#define ADC_THRES1_LOW_INT_ST_V  0x00000001U
+#define ADC_THRES1_LOW_INT_ST_S  26
+/** ADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_ST    (BIT(27))
+#define ADC_THRES0_LOW_INT_ST_M  (ADC_THRES0_LOW_INT_ST_V << ADC_THRES0_LOW_INT_ST_S)
+#define ADC_THRES0_LOW_INT_ST_V  0x00000001U
+#define ADC_THRES0_LOW_INT_ST_S  27
+/** ADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_ST    (BIT(28))
+#define ADC_THRES1_HIGH_INT_ST_M  (ADC_THRES1_HIGH_INT_ST_V << ADC_THRES1_HIGH_INT_ST_S)
+#define ADC_THRES1_HIGH_INT_ST_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_ST_S  28
+/** ADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_ST    (BIT(29))
+#define ADC_THRES0_HIGH_INT_ST_M  (ADC_THRES0_HIGH_INT_ST_V << ADC_THRES0_HIGH_INT_ST_S)
+#define ADC_THRES0_HIGH_INT_ST_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_ST_S  29
+/** ADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DONE_INT_ST    (BIT(30))
+#define ADC_APB_SARADC2_DONE_INT_ST_M  (ADC_APB_SARADC2_DONE_INT_ST_V << ADC_APB_SARADC2_DONE_INT_ST_S)
+#define ADC_APB_SARADC2_DONE_INT_ST_V  0x00000001U
+#define ADC_APB_SARADC2_DONE_INT_ST_S  30
+/** ADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DONE_INT_ST    (BIT(31))
+#define ADC_APB_SARADC1_DONE_INT_ST_M  (ADC_APB_SARADC1_DONE_INT_ST_V << ADC_APB_SARADC1_DONE_INT_ST_S)
+#define ADC_APB_SARADC1_DONE_INT_ST_V  0x00000001U
+#define ADC_APB_SARADC1_DONE_INT_ST_S  31
+
+/** ADC_INT_CLR_REG register
+ *  Register
+ */
+#define ADC_INT_CLR_REG (DR_REG_ADC_BASE + 0x5c)
+/** ADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_CLR    (BIT(26))
+#define ADC_THRES1_LOW_INT_CLR_M  (ADC_THRES1_LOW_INT_CLR_V << ADC_THRES1_LOW_INT_CLR_S)
+#define ADC_THRES1_LOW_INT_CLR_V  0x00000001U
+#define ADC_THRES1_LOW_INT_CLR_S  26
+/** ADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_CLR    (BIT(27))
+#define ADC_THRES0_LOW_INT_CLR_M  (ADC_THRES0_LOW_INT_CLR_V << ADC_THRES0_LOW_INT_CLR_S)
+#define ADC_THRES0_LOW_INT_CLR_V  0x00000001U
+#define ADC_THRES0_LOW_INT_CLR_S  27
+/** ADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_CLR    (BIT(28))
+#define ADC_THRES1_HIGH_INT_CLR_M  (ADC_THRES1_HIGH_INT_CLR_V << ADC_THRES1_HIGH_INT_CLR_S)
+#define ADC_THRES1_HIGH_INT_CLR_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_CLR_S  28
+/** ADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_CLR    (BIT(29))
+#define ADC_THRES0_HIGH_INT_CLR_M  (ADC_THRES0_HIGH_INT_CLR_V << ADC_THRES0_HIGH_INT_CLR_S)
+#define ADC_THRES0_HIGH_INT_CLR_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_CLR_S  29
+/** ADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DONE_INT_CLR    (BIT(30))
+#define ADC_APB_SARADC2_DONE_INT_CLR_M  (ADC_APB_SARADC2_DONE_INT_CLR_V << ADC_APB_SARADC2_DONE_INT_CLR_S)
+#define ADC_APB_SARADC2_DONE_INT_CLR_V  0x00000001U
+#define ADC_APB_SARADC2_DONE_INT_CLR_S  30
+/** ADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DONE_INT_CLR    (BIT(31))
+#define ADC_APB_SARADC1_DONE_INT_CLR_M  (ADC_APB_SARADC1_DONE_INT_CLR_V << ADC_APB_SARADC1_DONE_INT_CLR_S)
+#define ADC_APB_SARADC1_DONE_INT_CLR_V  0x00000001U
+#define ADC_APB_SARADC1_DONE_INT_CLR_S  31
+
+/** ADC_DMA_CONF_REG register
+ *  Register
+ */
+#define ADC_DMA_CONF_REG (DR_REG_ADC_BASE + 0x60)
+/** ADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
+ *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+ */
+#define ADC_APB_ADC_EOF_NUM    0x0000FFFFU
+#define ADC_APB_ADC_EOF_NUM_M  (ADC_APB_ADC_EOF_NUM_V << ADC_APB_ADC_EOF_NUM_S)
+#define ADC_APB_ADC_EOF_NUM_V  0x0000FFFFU
+#define ADC_APB_ADC_EOF_NUM_S  0
+/** ADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
+ *  reset_apb_adc_state
+ */
+#define ADC_APB_ADC_RESET_FSM    (BIT(30))
+#define ADC_APB_ADC_RESET_FSM_M  (ADC_APB_ADC_RESET_FSM_V << ADC_APB_ADC_RESET_FSM_S)
+#define ADC_APB_ADC_RESET_FSM_V  0x00000001U
+#define ADC_APB_ADC_RESET_FSM_S  30
+/** ADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc use spi_dma
+ */
+#define ADC_APB_ADC_TRANS    (BIT(31))
+#define ADC_APB_ADC_TRANS_M  (ADC_APB_ADC_TRANS_V << ADC_APB_ADC_TRANS_S)
+#define ADC_APB_ADC_TRANS_V  0x00000001U
+#define ADC_APB_ADC_TRANS_S  31
+
+/** ADC_SAR2_DATA_STATUS_REG register
+ *  Register
+ */
+#define ADC_SAR2_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x64)
+/** ADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DATA    0x0001FFFFU
+#define ADC_APB_SARADC2_DATA_M  (ADC_APB_SARADC2_DATA_V << ADC_APB_SARADC2_DATA_S)
+#define ADC_APB_SARADC2_DATA_V  0x0001FFFFU
+#define ADC_APB_SARADC2_DATA_S  0
+
+/** ADC_CALI_REG register
+ *  Register
+ */
+#define ADC_CALI_REG (DR_REG_ADC_BASE + 0x68)
+/** ADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
+ *  need_des
+ */
+#define ADC_CALI_CFG    0x0001FFFFU
+#define ADC_CALI_CFG_M  (ADC_CALI_CFG_V << ADC_CALI_CFG_S)
+#define ADC_CALI_CFG_V  0x0001FFFFU
+#define ADC_CALI_CFG_S  0
+
+/** ADC_RND_ECO_LOW_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_LOW_REG (DR_REG_ADC_BASE + 0x6c)
+/** ADC_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  rnd eco low
+ */
+#define ADC_RND_ECO_LOW    0xFFFFFFFFU
+#define ADC_RND_ECO_LOW_M  (ADC_RND_ECO_LOW_V << ADC_RND_ECO_LOW_S)
+#define ADC_RND_ECO_LOW_V  0xFFFFFFFFU
+#define ADC_RND_ECO_LOW_S  0
+
+/** ADC_RND_ECO_HIGH_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_HIGH_REG (DR_REG_ADC_BASE + 0x70)
+/** ADC_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  rnd eco high
+ */
+#define ADC_RND_ECO_HIGH    0xFFFFFFFFU
+#define ADC_RND_ECO_HIGH_M  (ADC_RND_ECO_HIGH_V << ADC_RND_ECO_HIGH_S)
+#define ADC_RND_ECO_HIGH_V  0xFFFFFFFFU
+#define ADC_RND_ECO_HIGH_S  0
+
+/** ADC_RND_ECO_CS_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_CS_REG (DR_REG_ADC_BASE + 0x74)
+/** ADC_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_RND_ECO_EN    (BIT(0))
+#define ADC_RND_ECO_EN_M  (ADC_RND_ECO_EN_V << ADC_RND_ECO_EN_S)
+#define ADC_RND_ECO_EN_V  0x00000001U
+#define ADC_RND_ECO_EN_S  0
+/** ADC_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_RND_ECO_RESULT    (BIT(1))
+#define ADC_RND_ECO_RESULT_M  (ADC_RND_ECO_RESULT_V << ADC_RND_ECO_RESULT_S)
+#define ADC_RND_ECO_RESULT_V  0x00000001U
+#define ADC_RND_ECO_RESULT_S  1
+
+/** ADC_CTRL_DATE_REG register
+ *  Register
+ */
+#define ADC_CTRL_DATE_REG (DR_REG_ADC_BASE + 0x3fc)
+/** ADC_CTRL_DATE : R/W; bitpos: [30:0]; default: 35725920;
+ *  need_des
+ */
+#define ADC_CTRL_DATE    0x7FFFFFFFU
+#define ADC_CTRL_DATE_M  (ADC_CTRL_DATE_V << ADC_CTRL_DATE_S)
+#define ADC_CTRL_DATE_V  0x7FFFFFFFU
+#define ADC_CTRL_DATE_S  0
+/** ADC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_CLK_EN    (BIT(31))
+#define ADC_CLK_EN_M  (ADC_CLK_EN_V << ADC_CLK_EN_S)
+#define ADC_CLK_EN_V  0x00000001U
+#define ADC_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/adc_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/adc_eco5_struct.h
new file mode 100644
index 0000000000..873db7857c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/adc_eco5_struct.h
@@ -0,0 +1,695 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configure Register */
+/** Type of ctrl_reg register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** start_force : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t start_force:1;
+        /** start : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t start:1;
+        /** work_mode : R/W; bitpos: [3:2]; default: 0;
+         *  0: single mode, 1: double mode, 2: alternate mode
+         */
+        uint32_t work_mode:2;
+        /** sar_sel : R/W; bitpos: [4]; default: 0;
+         *  0: SAR1, 1: SAR2, only work for single SAR mode
+         */
+        uint32_t sar_sel:1;
+        /** sar_clk_gated : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t sar_clk_gated:1;
+        /** sar_clk_div : R/W; bitpos: [13:6]; default: 4;
+         *  SAR clock divider
+         */
+        uint32_t sar_clk_div:8;
+        /** sar1_patt_len : R/W; bitpos: [17:14]; default: 15;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t sar1_patt_len:4;
+        /** sar2_patt_len : R/W; bitpos: [21:18]; default: 15;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t sar2_patt_len:4;
+        /** sar1_patt_p_clear : R/W; bitpos: [22]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC1 CTRL
+         */
+        uint32_t sar1_patt_p_clear:1;
+        /** sar2_patt_p_clear : R/W; bitpos: [23]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC2 CTRL
+         */
+        uint32_t sar2_patt_p_clear:1;
+        /** data_sar_sel : R/W; bitpos: [24]; default: 0;
+         *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+         *  resolution should not be larger than 11 bits.
+         */
+        uint32_t data_sar_sel:1;
+        /** data_to_i2s : R/W; bitpos: [25]; default: 0;
+         *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+         */
+        uint32_t data_to_i2s:1;
+        /** xpd_sar1_force : R/W; bitpos: [27:26]; default: 0;
+         *  force option to xpd sar1 blocks
+         */
+        uint32_t xpd_sar1_force:2;
+        /** xpd_sar2_force : R/W; bitpos: [29:28]; default: 0;
+         *  force option to xpd sar2 blocks
+         */
+        uint32_t xpd_sar2_force:2;
+        /** wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
+         *  wait arbit signal stable after sar_done
+         */
+        uint32_t wait_arb_cycle:2;
+    };
+    uint32_t val;
+} adc_ctrl_reg_reg_t;
+
+/** Type of ctrl2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** meas_num_limit : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t meas_num_limit:1;
+        /** max_meas_num : R/W; bitpos: [8:1]; default: 255;
+         *  max conversion number
+         */
+        uint32_t max_meas_num:8;
+        /** sar1_inv : R/W; bitpos: [9]; default: 0;
+         *  1: data to DIG ADC1 CTRL is inverted, otherwise not
+         */
+        uint32_t sar1_inv:1;
+        /** sar2_inv : R/W; bitpos: [10]; default: 0;
+         *  1: data to DIG ADC2 CTRL is inverted, otherwise not
+         */
+        uint32_t sar2_inv:1;
+        /** timer_sel : R/W; bitpos: [11]; default: 0;
+         *  1: select saradc timer 0: i2s_ws trigger
+         */
+        uint32_t timer_sel:1;
+        /** timer_target : R/W; bitpos: [23:12]; default: 10;
+         *  to set saradc timer target
+         */
+        uint32_t timer_target:12;
+        /** timer_en : R/W; bitpos: [24]; default: 0;
+         *  to enable saradc timer trigger
+         */
+        uint32_t timer_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} adc_ctrl2_reg_t;
+
+/** Type of filter_ctrl1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** filter_factor1 : R/W; bitpos: [28:26]; default: 0;
+         *  need_des
+         */
+        uint32_t filter_factor1:3;
+        /** filter_factor0 : R/W; bitpos: [31:29]; default: 0;
+         *  need_des
+         */
+        uint32_t filter_factor0:3;
+    };
+    uint32_t val;
+} adc_filter_ctrl1_reg_t;
+
+/** Type of sar1_patt_tab1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab1 : R/W; bitpos: [23:0]; default: 0;
+         *  item 0 ~ 3 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab1_reg_t;
+
+/** Type of sar1_patt_tab2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 4 ~ 7 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab2:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab2_reg_t;
+
+/** Type of sar1_patt_tab3 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 8 ~ 11 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab3:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab3_reg_t;
+
+/** Type of sar1_patt_tab4 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 12 ~ 15 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab4:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab4_reg_t;
+
+/** Type of sar2_patt_tab1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab1 : R/W; bitpos: [23:0]; default: 0;
+         *  item 0 ~ 3 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab1_reg_t;
+
+/** Type of sar2_patt_tab2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 4 ~ 7 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab2:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab2_reg_t;
+
+/** Type of sar2_patt_tab3 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 8 ~ 11 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab3:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab3_reg_t;
+
+/** Type of sar2_patt_tab4 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 12 ~ 15 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab4:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab4_reg_t;
+
+/** Type of arb_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** arb_apb_force : R/W; bitpos: [2]; default: 0;
+         *  adc2 arbiter force to enableapb controller
+         */
+        uint32_t arb_apb_force:1;
+        /** arb_rtc_force : R/W; bitpos: [3]; default: 0;
+         *  adc2 arbiter force to enable rtc controller
+         */
+        uint32_t arb_rtc_force:1;
+        /** arb_wifi_force : R/W; bitpos: [4]; default: 0;
+         *  adc2 arbiter force to enable wifi controller
+         */
+        uint32_t arb_wifi_force:1;
+        /** arb_grant_force : R/W; bitpos: [5]; default: 0;
+         *  adc2 arbiter force grant
+         */
+        uint32_t arb_grant_force:1;
+        /** arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
+         *  Set adc2 arbiterapb priority
+         */
+        uint32_t arb_apb_priority:2;
+        /** arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
+         *  Set adc2 arbiter rtc priority
+         */
+        uint32_t arb_rtc_priority:2;
+        /** arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
+         *  Set adc2 arbiter wifi priority
+         */
+        uint32_t arb_wifi_priority:2;
+        /** arb_fix_priority : R/W; bitpos: [12]; default: 0;
+         *  adc2 arbiter uses fixed priority
+         */
+        uint32_t arb_fix_priority:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} adc_arb_ctrl_reg_t;
+
+/** Type of filter_ctrl0 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** filter_channel1 : R/W; bitpos: [18:14]; default: 13;
+         *  need_des
+         */
+        uint32_t filter_channel1:5;
+        /** filter_channel0 : R/W; bitpos: [23:19]; default: 13;
+         *  apb_adc1_filter_factor
+         */
+        uint32_t filter_channel0:5;
+        uint32_t reserved_24:7;
+        /** filter_reset : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc1_filter
+         */
+        uint32_t filter_reset:1;
+    };
+    uint32_t val;
+} adc_filter_ctrl0_reg_t;
+
+/** Type of sar1_data_status register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_data:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_sar1_data_status_reg_t;
+
+/** Type of thres0_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres0_channel : R/W; bitpos: [4:0]; default: 13;
+         *  need_des
+         */
+        uint32_t thres0_channel:5;
+        /** thres0_high : R/W; bitpos: [17:5]; default: 8191;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres0_high:13;
+        /** thres0_low : R/W; bitpos: [30:18]; default: 0;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres0_low:13;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} adc_thres0_ctrl_reg_t;
+
+/** Type of thres1_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres1_channel : R/W; bitpos: [4:0]; default: 13;
+         *  need_des
+         */
+        uint32_t thres1_channel:5;
+        /** thres1_high : R/W; bitpos: [17:5]; default: 8191;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres1_high:13;
+        /** thres1_low : R/W; bitpos: [30:18]; default: 0;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres1_low:13;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} adc_thres1_ctrl_reg_t;
+
+/** Type of thres_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** thres_all_en : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres_all_en:1;
+        /** thres3_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres3_en:1;
+        /** thres2_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres2_en:1;
+        /** thres1_en : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_en:1;
+        /** thres0_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_en:1;
+    };
+    uint32_t val;
+} adc_thres_ctrl_reg_t;
+
+/** Type of int_ena register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_ena:1;
+        /** thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_ena:1;
+        /** thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_ena:1;
+        /** thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_ena:1;
+        /** sar2_done_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_ena:1;
+        /** sar1_done_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_ena:1;
+    };
+    uint32_t val;
+} adc_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_raw:1;
+        /** thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_raw:1;
+        /** thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_raw:1;
+        /** thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_raw:1;
+        /** sar2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_raw:1;
+        /** sar1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_raw:1;
+    };
+    uint32_t val;
+} adc_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_st : RO; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_st:1;
+        /** thres0_low_int_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_st:1;
+        /** thres1_high_int_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_st:1;
+        /** thres0_high_int_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_st:1;
+        /** apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_done_int_st:1;
+        /** apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_done_int_st:1;
+    };
+    uint32_t val;
+} adc_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_clr : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_clr:1;
+        /** thres0_low_int_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_clr:1;
+        /** thres1_high_int_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_clr:1;
+        /** thres0_high_int_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_clr:1;
+        /** apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_done_int_clr:1;
+        /** apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_done_int_clr:1;
+    };
+    uint32_t val;
+} adc_int_clr_reg_t;
+
+/** Type of dma_conf register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
+         *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+         */
+        uint32_t apb_adc_eof_num:16;
+        uint32_t reserved_16:14;
+        /** apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
+         *  reset_apb_adc_state
+         */
+        uint32_t apb_adc_reset_fsm:1;
+        /** apb_adc_trans : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc use spi_dma
+         */
+        uint32_t apb_adc_trans:1;
+    };
+    uint32_t val;
+} adc_dma_conf_reg_t;
+
+/** Type of sar2_data_status register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_data:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_sar2_data_status_reg_t;
+
+/** Type of cali register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** cali_cfg : R/W; bitpos: [16:0]; default: 32768;
+         *  need_des
+         */
+        uint32_t cali_cfg:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_cali_reg_t;
+
+/** Type of rnd_eco_low register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rnd eco low
+         */
+        uint32_t rnd_eco_low:32;
+    };
+    uint32_t val;
+} adc_rnd_eco_low_reg_t;
+
+/** Type of rnd_eco_high register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rnd eco high
+         */
+        uint32_t rnd_eco_high:32;
+    };
+    uint32_t val;
+} adc_rnd_eco_high_reg_t;
+
+/** Type of rnd_eco_cs register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t rnd_eco_en:1;
+        /** rnd_eco_result : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t rnd_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} adc_rnd_eco_cs_reg_t;
+
+/** Type of ctrl_date register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** ctrl_date : R/W; bitpos: [30:0]; default: 35725920;
+         *  need_des
+         */
+        uint32_t ctrl_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} adc_ctrl_date_reg_t;
+
+
+typedef struct {
+    volatile adc_ctrl_reg_reg_t ctrl_reg;
+    volatile adc_ctrl2_reg_t ctrl2;
+    volatile adc_filter_ctrl1_reg_t filter_ctrl1;
+    uint32_t reserved_00c[3];
+    volatile adc_sar1_patt_tab1_reg_t sar1_patt_tab1;
+    volatile adc_sar1_patt_tab2_reg_t sar1_patt_tab2;
+    volatile adc_sar1_patt_tab3_reg_t sar1_patt_tab3;
+    volatile adc_sar1_patt_tab4_reg_t sar1_patt_tab4;
+    volatile adc_sar2_patt_tab1_reg_t sar2_patt_tab1;
+    volatile adc_sar2_patt_tab2_reg_t sar2_patt_tab2;
+    volatile adc_sar2_patt_tab3_reg_t sar2_patt_tab3;
+    volatile adc_sar2_patt_tab4_reg_t sar2_patt_tab4;
+    volatile adc_arb_ctrl_reg_t arb_ctrl;
+    volatile adc_filter_ctrl0_reg_t filter_ctrl0;
+    volatile adc_sar1_data_status_reg_t sar1_data_status;
+    volatile adc_thres0_ctrl_reg_t thres0_ctrl;
+    volatile adc_thres1_ctrl_reg_t thres1_ctrl;
+    volatile adc_thres_ctrl_reg_t thres_ctrl;
+    volatile adc_int_ena_reg_t int_ena;
+    volatile adc_int_raw_reg_t int_raw;
+    volatile adc_int_st_reg_t int_st;
+    volatile adc_int_clr_reg_t int_clr;
+    volatile adc_dma_conf_reg_t dma_conf;
+    volatile adc_sar2_data_status_reg_t sar2_data_status;
+    volatile adc_cali_reg_t cali;
+    volatile adc_rnd_eco_low_reg_t rnd_eco_low;
+    volatile adc_rnd_eco_high_reg_t rnd_eco_high;
+    volatile adc_rnd_eco_cs_reg_t rnd_eco_cs;
+    uint32_t reserved_078[225];
+    volatile adc_ctrl_date_reg_t ctrl_date;
+} adc_dev_t;
+
+extern adc_dev_t ADC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/adc_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/adc_reg.h
new file mode 100644
index 0000000000..2e58050bf7
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/adc_reg.h
@@ -0,0 +1,809 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13426
+
+/** ADC_CTRL_REG_REG register
+ *  Register
+ */
+#define ADC_CTRL_REG_REG (DR_REG_ADC_BASE + 0x0)
+/** ADC_START_FORCE : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_START_FORCE    (BIT(0))
+#define ADC_START_FORCE_M  (ADC_START_FORCE_V << ADC_START_FORCE_S)
+#define ADC_START_FORCE_V  0x00000001U
+#define ADC_START_FORCE_S  0
+/** ADC_START : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_START    (BIT(1))
+#define ADC_START_M  (ADC_START_V << ADC_START_S)
+#define ADC_START_V  0x00000001U
+#define ADC_START_S  1
+/** ADC_WORK_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  0: single mode, 1: double mode, 2: alternate mode
+ */
+#define ADC_WORK_MODE    0x00000003U
+#define ADC_WORK_MODE_M  (ADC_WORK_MODE_V << ADC_WORK_MODE_S)
+#define ADC_WORK_MODE_V  0x00000003U
+#define ADC_WORK_MODE_S  2
+/** ADC_SAR_SEL : R/W; bitpos: [4]; default: 0;
+ *  0: SAR1, 1: SAR2, only work for single SAR mode
+ */
+#define ADC_SAR_SEL    (BIT(4))
+#define ADC_SAR_SEL_M  (ADC_SAR_SEL_V << ADC_SAR_SEL_S)
+#define ADC_SAR_SEL_V  0x00000001U
+#define ADC_SAR_SEL_S  4
+/** ADC_SAR_CLK_GATED : R/W; bitpos: [5]; default: 1;
+ *  need_des
+ */
+#define ADC_SAR_CLK_GATED    (BIT(5))
+#define ADC_SAR_CLK_GATED_M  (ADC_SAR_CLK_GATED_V << ADC_SAR_CLK_GATED_S)
+#define ADC_SAR_CLK_GATED_V  0x00000001U
+#define ADC_SAR_CLK_GATED_S  5
+/** ADC_SAR_CLK_DIV : R/W; bitpos: [13:6]; default: 4;
+ *  SAR clock divider
+ */
+#define ADC_SAR_CLK_DIV    0x000000FFU
+#define ADC_SAR_CLK_DIV_M  (ADC_SAR_CLK_DIV_V << ADC_SAR_CLK_DIV_S)
+#define ADC_SAR_CLK_DIV_V  0x000000FFU
+#define ADC_SAR_CLK_DIV_S  6
+/** ADC_SAR1_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define ADC_SAR1_PATT_LEN    0x0000000FU
+#define ADC_SAR1_PATT_LEN_M  (ADC_SAR1_PATT_LEN_V << ADC_SAR1_PATT_LEN_S)
+#define ADC_SAR1_PATT_LEN_V  0x0000000FU
+#define ADC_SAR1_PATT_LEN_S  14
+/** ADC_SAR2_PATT_LEN : R/W; bitpos: [21:18]; default: 15;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define ADC_SAR2_PATT_LEN    0x0000000FU
+#define ADC_SAR2_PATT_LEN_M  (ADC_SAR2_PATT_LEN_V << ADC_SAR2_PATT_LEN_S)
+#define ADC_SAR2_PATT_LEN_V  0x0000000FU
+#define ADC_SAR2_PATT_LEN_S  18
+/** ADC_SAR1_PATT_P_CLEAR : R/W; bitpos: [22]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC1 CTRL
+ */
+#define ADC_SAR1_PATT_P_CLEAR    (BIT(22))
+#define ADC_SAR1_PATT_P_CLEAR_M  (ADC_SAR1_PATT_P_CLEAR_V << ADC_SAR1_PATT_P_CLEAR_S)
+#define ADC_SAR1_PATT_P_CLEAR_V  0x00000001U
+#define ADC_SAR1_PATT_P_CLEAR_S  22
+/** ADC_SAR2_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC2 CTRL
+ */
+#define ADC_SAR2_PATT_P_CLEAR    (BIT(23))
+#define ADC_SAR2_PATT_P_CLEAR_M  (ADC_SAR2_PATT_P_CLEAR_V << ADC_SAR2_PATT_P_CLEAR_S)
+#define ADC_SAR2_PATT_P_CLEAR_V  0x00000001U
+#define ADC_SAR2_PATT_P_CLEAR_S  23
+/** ADC_DATA_SAR_SEL : R/W; bitpos: [24]; default: 0;
+ *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+ *  resolution should not be larger than 11 bits.
+ */
+#define ADC_DATA_SAR_SEL    (BIT(24))
+#define ADC_DATA_SAR_SEL_M  (ADC_DATA_SAR_SEL_V << ADC_DATA_SAR_SEL_S)
+#define ADC_DATA_SAR_SEL_V  0x00000001U
+#define ADC_DATA_SAR_SEL_S  24
+/** ADC_DATA_TO_I2S : R/W; bitpos: [25]; default: 0;
+ *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+ */
+#define ADC_DATA_TO_I2S    (BIT(25))
+#define ADC_DATA_TO_I2S_M  (ADC_DATA_TO_I2S_V << ADC_DATA_TO_I2S_S)
+#define ADC_DATA_TO_I2S_V  0x00000001U
+#define ADC_DATA_TO_I2S_S  25
+/** ADC_XPD_SAR1_FORCE : R/W; bitpos: [27:26]; default: 0;
+ *  force option to xpd sar1 blocks
+ */
+#define ADC_XPD_SAR1_FORCE    0x00000003U
+#define ADC_XPD_SAR1_FORCE_M  (ADC_XPD_SAR1_FORCE_V << ADC_XPD_SAR1_FORCE_S)
+#define ADC_XPD_SAR1_FORCE_V  0x00000003U
+#define ADC_XPD_SAR1_FORCE_S  26
+/** ADC_XPD_SAR2_FORCE : R/W; bitpos: [29:28]; default: 0;
+ *  force option to xpd sar2 blocks
+ */
+#define ADC_XPD_SAR2_FORCE    0x00000003U
+#define ADC_XPD_SAR2_FORCE_M  (ADC_XPD_SAR2_FORCE_V << ADC_XPD_SAR2_FORCE_S)
+#define ADC_XPD_SAR2_FORCE_V  0x00000003U
+#define ADC_XPD_SAR2_FORCE_S  28
+/** ADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
+ *  wait arbit signal stable after sar_done
+ */
+#define ADC_WAIT_ARB_CYCLE    0x00000003U
+#define ADC_WAIT_ARB_CYCLE_M  (ADC_WAIT_ARB_CYCLE_V << ADC_WAIT_ARB_CYCLE_S)
+#define ADC_WAIT_ARB_CYCLE_V  0x00000003U
+#define ADC_WAIT_ARB_CYCLE_S  30
+
+/** ADC_CTRL2_REG register
+ *  Register
+ */
+#define ADC_CTRL2_REG (DR_REG_ADC_BASE + 0x4)
+/** ADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_MEAS_NUM_LIMIT    (BIT(0))
+#define ADC_MEAS_NUM_LIMIT_M  (ADC_MEAS_NUM_LIMIT_V << ADC_MEAS_NUM_LIMIT_S)
+#define ADC_MEAS_NUM_LIMIT_V  0x00000001U
+#define ADC_MEAS_NUM_LIMIT_S  0
+/** ADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
+ *  max conversion number
+ */
+#define ADC_MAX_MEAS_NUM    0x000000FFU
+#define ADC_MAX_MEAS_NUM_M  (ADC_MAX_MEAS_NUM_V << ADC_MAX_MEAS_NUM_S)
+#define ADC_MAX_MEAS_NUM_V  0x000000FFU
+#define ADC_MAX_MEAS_NUM_S  1
+/** ADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
+ *  1: data to DIG ADC1 CTRL is inverted, otherwise not
+ */
+#define ADC_SAR1_INV    (BIT(9))
+#define ADC_SAR1_INV_M  (ADC_SAR1_INV_V << ADC_SAR1_INV_S)
+#define ADC_SAR1_INV_V  0x00000001U
+#define ADC_SAR1_INV_S  9
+/** ADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
+ *  1: data to DIG ADC2 CTRL is inverted, otherwise not
+ */
+#define ADC_SAR2_INV    (BIT(10))
+#define ADC_SAR2_INV_M  (ADC_SAR2_INV_V << ADC_SAR2_INV_S)
+#define ADC_SAR2_INV_V  0x00000001U
+#define ADC_SAR2_INV_S  10
+/** ADC_TIMER_SEL : R/W; bitpos: [11]; default: 0;
+ *  1: select saradc timer 0: i2s_ws trigger
+ */
+#define ADC_TIMER_SEL    (BIT(11))
+#define ADC_TIMER_SEL_M  (ADC_TIMER_SEL_V << ADC_TIMER_SEL_S)
+#define ADC_TIMER_SEL_V  0x00000001U
+#define ADC_TIMER_SEL_S  11
+/** ADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
+ *  to set saradc timer target
+ */
+#define ADC_TIMER_TARGET    0x00000FFFU
+#define ADC_TIMER_TARGET_M  (ADC_TIMER_TARGET_V << ADC_TIMER_TARGET_S)
+#define ADC_TIMER_TARGET_V  0x00000FFFU
+#define ADC_TIMER_TARGET_S  12
+/** ADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
+ *  to enable saradc timer trigger
+ */
+#define ADC_TIMER_EN    (BIT(24))
+#define ADC_TIMER_EN_M  (ADC_TIMER_EN_V << ADC_TIMER_EN_S)
+#define ADC_TIMER_EN_V  0x00000001U
+#define ADC_TIMER_EN_S  24
+
+/** ADC_FILTER_CTRL1_REG register
+ *  Register
+ */
+#define ADC_FILTER_CTRL1_REG (DR_REG_ADC_BASE + 0x8)
+/** ADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
+ *  need_des
+ */
+#define ADC_FILTER_FACTOR1    0x00000007U
+#define ADC_FILTER_FACTOR1_M  (ADC_FILTER_FACTOR1_V << ADC_FILTER_FACTOR1_S)
+#define ADC_FILTER_FACTOR1_V  0x00000007U
+#define ADC_FILTER_FACTOR1_S  26
+/** ADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
+ *  need_des
+ */
+#define ADC_FILTER_FACTOR0    0x00000007U
+#define ADC_FILTER_FACTOR0_M  (ADC_FILTER_FACTOR0_V << ADC_FILTER_FACTOR0_S)
+#define ADC_FILTER_FACTOR0_V  0x00000007U
+#define ADC_FILTER_FACTOR0_S  29
+
+#define ADC_FSM_WAIT_REG          (DR_REG_ADC_BASE + 0xC)
+/* ADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
+/*description: need_des.*/
+#define ADC_STANDBY_WAIT    0x000000FF
+#define ADC_STANDBY_WAIT_M  ((ADC_STANDBY_WAIT_V)<<(ADC_STANDBY_WAIT_S))
+#define ADC_STANDBY_WAIT_V  0xFF
+#define ADC_STANDBY_WAIT_S  16
+/* ADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
+/*description: need_des.*/
+#define ADC_RSTB_WAIT    0x000000FF
+#define ADC_RSTB_WAIT_M  ((ADC_RSTB_WAIT_V)<<(ADC_RSTB_WAIT_S))
+#define ADC_RSTB_WAIT_V  0xFF
+#define ADC_RSTB_WAIT_S  8
+/* ADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
+/*description: need_des.*/
+#define ADC_XPD_WAIT    0x000000FF
+#define ADC_XPD_WAIT_M  ((ADC_XPD_WAIT_V)<<(ADC_XPD_WAIT_S))
+#define ADC_XPD_WAIT_V  0xFF
+#define ADC_XPD_WAIT_S  0
+
+/** ADC_SAR1_PATT_TAB1_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x18)
+/** ADC_SAR1_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
+ *  item 0 ~ 3 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB1    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB1_M  (ADC_SAR1_PATT_TAB1_V << ADC_SAR1_PATT_TAB1_S)
+#define ADC_SAR1_PATT_TAB1_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB1_S  0
+
+/** ADC_SAR1_PATT_TAB2_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x1c)
+/** ADC_SAR1_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 4 ~ 7 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB2    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB2_M  (ADC_SAR1_PATT_TAB2_V << ADC_SAR1_PATT_TAB2_S)
+#define ADC_SAR1_PATT_TAB2_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB2_S  0
+
+/** ADC_SAR1_PATT_TAB3_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x20)
+/** ADC_SAR1_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 8 ~ 11 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB3    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB3_M  (ADC_SAR1_PATT_TAB3_V << ADC_SAR1_PATT_TAB3_S)
+#define ADC_SAR1_PATT_TAB3_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB3_S  0
+
+/** ADC_SAR1_PATT_TAB4_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x24)
+/** ADC_SAR1_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 12 ~ 15 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB4    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB4_M  (ADC_SAR1_PATT_TAB4_V << ADC_SAR1_PATT_TAB4_S)
+#define ADC_SAR1_PATT_TAB4_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB4_S  0
+
+/** ADC_SAR2_PATT_TAB1_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x28)
+/** ADC_SAR2_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
+ *  item 0 ~ 3 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB1    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB1_M  (ADC_SAR2_PATT_TAB1_V << ADC_SAR2_PATT_TAB1_S)
+#define ADC_SAR2_PATT_TAB1_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB1_S  0
+
+/** ADC_SAR2_PATT_TAB2_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x2c)
+/** ADC_SAR2_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 4 ~ 7 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB2    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB2_M  (ADC_SAR2_PATT_TAB2_V << ADC_SAR2_PATT_TAB2_S)
+#define ADC_SAR2_PATT_TAB2_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB2_S  0
+
+/** ADC_SAR2_PATT_TAB3_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x30)
+/** ADC_SAR2_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 8 ~ 11 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB3    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB3_M  (ADC_SAR2_PATT_TAB3_V << ADC_SAR2_PATT_TAB3_S)
+#define ADC_SAR2_PATT_TAB3_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB3_S  0
+
+/** ADC_SAR2_PATT_TAB4_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x34)
+/** ADC_SAR2_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 12 ~ 15 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB4    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB4_M  (ADC_SAR2_PATT_TAB4_V << ADC_SAR2_PATT_TAB4_S)
+#define ADC_SAR2_PATT_TAB4_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB4_S  0
+
+/** ADC_ARB_CTRL_REG register
+ *  Register
+ */
+#define ADC_ARB_CTRL_REG (DR_REG_ADC_BASE + 0x38)
+/** ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
+ *  adc2 arbiter force to enableapb controller
+ */
+#define ADC_ARB_APB_FORCE    (BIT(2))
+#define ADC_ARB_APB_FORCE_M  (ADC_ARB_APB_FORCE_V << ADC_ARB_APB_FORCE_S)
+#define ADC_ARB_APB_FORCE_V  0x00000001U
+#define ADC_ARB_APB_FORCE_S  2
+/** ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
+ *  adc2 arbiter force to enable rtc controller
+ */
+#define ADC_ARB_RTC_FORCE    (BIT(3))
+#define ADC_ARB_RTC_FORCE_M  (ADC_ARB_RTC_FORCE_V << ADC_ARB_RTC_FORCE_S)
+#define ADC_ARB_RTC_FORCE_V  0x00000001U
+#define ADC_ARB_RTC_FORCE_S  3
+/** ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
+ *  adc2 arbiter force to enable wifi controller
+ */
+#define ADC_ARB_WIFI_FORCE    (BIT(4))
+#define ADC_ARB_WIFI_FORCE_M  (ADC_ARB_WIFI_FORCE_V << ADC_ARB_WIFI_FORCE_S)
+#define ADC_ARB_WIFI_FORCE_V  0x00000001U
+#define ADC_ARB_WIFI_FORCE_S  4
+/** ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
+ *  adc2 arbiter force grant
+ */
+#define ADC_ARB_GRANT_FORCE    (BIT(5))
+#define ADC_ARB_GRANT_FORCE_M  (ADC_ARB_GRANT_FORCE_V << ADC_ARB_GRANT_FORCE_S)
+#define ADC_ARB_GRANT_FORCE_V  0x00000001U
+#define ADC_ARB_GRANT_FORCE_S  5
+/** ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
+ *  Set adc2 arbiterapb priority
+ */
+#define ADC_ARB_APB_PRIORITY    0x00000003U
+#define ADC_ARB_APB_PRIORITY_M  (ADC_ARB_APB_PRIORITY_V << ADC_ARB_APB_PRIORITY_S)
+#define ADC_ARB_APB_PRIORITY_V  0x00000003U
+#define ADC_ARB_APB_PRIORITY_S  6
+/** ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
+ *  Set adc2 arbiter rtc priority
+ */
+#define ADC_ARB_RTC_PRIORITY    0x00000003U
+#define ADC_ARB_RTC_PRIORITY_M  (ADC_ARB_RTC_PRIORITY_V << ADC_ARB_RTC_PRIORITY_S)
+#define ADC_ARB_RTC_PRIORITY_V  0x00000003U
+#define ADC_ARB_RTC_PRIORITY_S  8
+/** ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
+ *  Set adc2 arbiter wifi priority
+ */
+#define ADC_ARB_WIFI_PRIORITY    0x00000003U
+#define ADC_ARB_WIFI_PRIORITY_M  (ADC_ARB_WIFI_PRIORITY_V << ADC_ARB_WIFI_PRIORITY_S)
+#define ADC_ARB_WIFI_PRIORITY_V  0x00000003U
+#define ADC_ARB_WIFI_PRIORITY_S  10
+/** ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
+ *  adc2 arbiter uses fixed priority
+ */
+#define ADC_ARB_FIX_PRIORITY    (BIT(12))
+#define ADC_ARB_FIX_PRIORITY_M  (ADC_ARB_FIX_PRIORITY_V << ADC_ARB_FIX_PRIORITY_S)
+#define ADC_ARB_FIX_PRIORITY_V  0x00000001U
+#define ADC_ARB_FIX_PRIORITY_S  12
+
+/** ADC_FILTER_CTRL0_REG register
+ *  Register
+ */
+#define ADC_FILTER_CTRL0_REG (DR_REG_ADC_BASE + 0x3c)
+/** ADC_FILTER_CHANNEL1 : R/W; bitpos: [18:14]; default: 13;
+ *  need_des
+ */
+#define ADC_FILTER_CHANNEL1    0x0000001FU
+#define ADC_FILTER_CHANNEL1_M  (ADC_FILTER_CHANNEL1_V << ADC_FILTER_CHANNEL1_S)
+#define ADC_FILTER_CHANNEL1_V  0x0000001FU
+#define ADC_FILTER_CHANNEL1_S  14
+/** ADC_FILTER_CHANNEL0 : R/W; bitpos: [23:19]; default: 13;
+ *  apb_adc1_filter_factor
+ */
+#define ADC_FILTER_CHANNEL0    0x0000001FU
+#define ADC_FILTER_CHANNEL0_M  (ADC_FILTER_CHANNEL0_V << ADC_FILTER_CHANNEL0_S)
+#define ADC_FILTER_CHANNEL0_V  0x0000001FU
+#define ADC_FILTER_CHANNEL0_S  19
+/** ADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc1_filter
+ */
+#define ADC_FILTER_RESET    (BIT(31))
+#define ADC_FILTER_RESET_M  (ADC_FILTER_RESET_V << ADC_FILTER_RESET_S)
+#define ADC_FILTER_RESET_V  0x00000001U
+#define ADC_FILTER_RESET_S  31
+
+/** ADC_SAR1_DATA_STATUS_REG register
+ *  Register
+ */
+#define ADC_SAR1_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x40)
+/** ADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DATA    0x0001FFFFU
+#define ADC_APB_SARADC1_DATA_M  (ADC_APB_SARADC1_DATA_V << ADC_APB_SARADC1_DATA_S)
+#define ADC_APB_SARADC1_DATA_V  0x0001FFFFU
+#define ADC_APB_SARADC1_DATA_S  0
+
+/** ADC_THRES0_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES0_CTRL_REG (DR_REG_ADC_BASE + 0x44)
+/** ADC_THRES0_CHANNEL : R/W; bitpos: [4:0]; default: 13;
+ *  need_des
+ */
+#define ADC_THRES0_CHANNEL    0x0000001FU
+#define ADC_THRES0_CHANNEL_M  (ADC_THRES0_CHANNEL_V << ADC_THRES0_CHANNEL_S)
+#define ADC_THRES0_CHANNEL_V  0x0000001FU
+#define ADC_THRES0_CHANNEL_S  0
+/** ADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES0_HIGH    0x00001FFFU
+#define ADC_THRES0_HIGH_M  (ADC_THRES0_HIGH_V << ADC_THRES0_HIGH_S)
+#define ADC_THRES0_HIGH_V  0x00001FFFU
+#define ADC_THRES0_HIGH_S  5
+/** ADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES0_LOW    0x00001FFFU
+#define ADC_THRES0_LOW_M  (ADC_THRES0_LOW_V << ADC_THRES0_LOW_S)
+#define ADC_THRES0_LOW_V  0x00001FFFU
+#define ADC_THRES0_LOW_S  18
+
+/** ADC_THRES1_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES1_CTRL_REG (DR_REG_ADC_BASE + 0x48)
+/** ADC_THRES1_CHANNEL : R/W; bitpos: [4:0]; default: 13;
+ *  need_des
+ */
+#define ADC_THRES1_CHANNEL    0x0000001FU
+#define ADC_THRES1_CHANNEL_M  (ADC_THRES1_CHANNEL_V << ADC_THRES1_CHANNEL_S)
+#define ADC_THRES1_CHANNEL_V  0x0000001FU
+#define ADC_THRES1_CHANNEL_S  0
+/** ADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES1_HIGH    0x00001FFFU
+#define ADC_THRES1_HIGH_M  (ADC_THRES1_HIGH_V << ADC_THRES1_HIGH_S)
+#define ADC_THRES1_HIGH_V  0x00001FFFU
+#define ADC_THRES1_HIGH_S  5
+/** ADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES1_LOW    0x00001FFFU
+#define ADC_THRES1_LOW_M  (ADC_THRES1_LOW_V << ADC_THRES1_LOW_S)
+#define ADC_THRES1_LOW_V  0x00001FFFU
+#define ADC_THRES1_LOW_S  18
+
+/** ADC_THRES_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES_CTRL_REG (DR_REG_ADC_BASE + 0x4c)
+/** ADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES_ALL_EN    (BIT(27))
+#define ADC_THRES_ALL_EN_M  (ADC_THRES_ALL_EN_V << ADC_THRES_ALL_EN_S)
+#define ADC_THRES_ALL_EN_V  0x00000001U
+#define ADC_THRES_ALL_EN_S  27
+/** ADC_THRES3_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES3_EN    (BIT(28))
+#define ADC_THRES3_EN_M  (ADC_THRES3_EN_V << ADC_THRES3_EN_S)
+#define ADC_THRES3_EN_V  0x00000001U
+#define ADC_THRES3_EN_S  28
+/** ADC_THRES2_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES2_EN    (BIT(29))
+#define ADC_THRES2_EN_M  (ADC_THRES2_EN_V << ADC_THRES2_EN_S)
+#define ADC_THRES2_EN_V  0x00000001U
+#define ADC_THRES2_EN_S  29
+/** ADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_EN    (BIT(30))
+#define ADC_THRES1_EN_M  (ADC_THRES1_EN_V << ADC_THRES1_EN_S)
+#define ADC_THRES1_EN_V  0x00000001U
+#define ADC_THRES1_EN_S  30
+/** ADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_EN    (BIT(31))
+#define ADC_THRES0_EN_M  (ADC_THRES0_EN_V << ADC_THRES0_EN_S)
+#define ADC_THRES0_EN_V  0x00000001U
+#define ADC_THRES0_EN_S  31
+
+/** ADC_INT_ENA_REG register
+ *  Register
+ */
+#define ADC_INT_ENA_REG (DR_REG_ADC_BASE + 0x50)
+/** ADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_ENA    (BIT(26))
+#define ADC_THRES1_LOW_INT_ENA_M  (ADC_THRES1_LOW_INT_ENA_V << ADC_THRES1_LOW_INT_ENA_S)
+#define ADC_THRES1_LOW_INT_ENA_V  0x00000001U
+#define ADC_THRES1_LOW_INT_ENA_S  26
+/** ADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_ENA    (BIT(27))
+#define ADC_THRES0_LOW_INT_ENA_M  (ADC_THRES0_LOW_INT_ENA_V << ADC_THRES0_LOW_INT_ENA_S)
+#define ADC_THRES0_LOW_INT_ENA_V  0x00000001U
+#define ADC_THRES0_LOW_INT_ENA_S  27
+/** ADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_ENA    (BIT(28))
+#define ADC_THRES1_HIGH_INT_ENA_M  (ADC_THRES1_HIGH_INT_ENA_V << ADC_THRES1_HIGH_INT_ENA_S)
+#define ADC_THRES1_HIGH_INT_ENA_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_ENA_S  28
+/** ADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_ENA    (BIT(29))
+#define ADC_THRES0_HIGH_INT_ENA_M  (ADC_THRES0_HIGH_INT_ENA_V << ADC_THRES0_HIGH_INT_ENA_S)
+#define ADC_THRES0_HIGH_INT_ENA_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_ENA_S  29
+/** ADC_SAR2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_ENA    (BIT(30))
+#define ADC_SAR2_DONE_INT_ENA_M  (ADC_SAR2_DONE_INT_ENA_V << ADC_SAR2_DONE_INT_ENA_S)
+#define ADC_SAR2_DONE_INT_ENA_V  0x00000001U
+#define ADC_SAR2_DONE_INT_ENA_S  30
+/** ADC_SAR1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_ENA    (BIT(31))
+#define ADC_SAR1_DONE_INT_ENA_M  (ADC_SAR1_DONE_INT_ENA_V << ADC_SAR1_DONE_INT_ENA_S)
+#define ADC_SAR1_DONE_INT_ENA_V  0x00000001U
+#define ADC_SAR1_DONE_INT_ENA_S  31
+
+/** ADC_INT_RAW_REG register
+ *  Register
+ */
+#define ADC_INT_RAW_REG (DR_REG_ADC_BASE + 0x54)
+/** ADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_RAW    (BIT(26))
+#define ADC_THRES1_LOW_INT_RAW_M  (ADC_THRES1_LOW_INT_RAW_V << ADC_THRES1_LOW_INT_RAW_S)
+#define ADC_THRES1_LOW_INT_RAW_V  0x00000001U
+#define ADC_THRES1_LOW_INT_RAW_S  26
+/** ADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_RAW    (BIT(27))
+#define ADC_THRES0_LOW_INT_RAW_M  (ADC_THRES0_LOW_INT_RAW_V << ADC_THRES0_LOW_INT_RAW_S)
+#define ADC_THRES0_LOW_INT_RAW_V  0x00000001U
+#define ADC_THRES0_LOW_INT_RAW_S  27
+/** ADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_RAW    (BIT(28))
+#define ADC_THRES1_HIGH_INT_RAW_M  (ADC_THRES1_HIGH_INT_RAW_V << ADC_THRES1_HIGH_INT_RAW_S)
+#define ADC_THRES1_HIGH_INT_RAW_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_RAW_S  28
+/** ADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_RAW    (BIT(29))
+#define ADC_THRES0_HIGH_INT_RAW_M  (ADC_THRES0_HIGH_INT_RAW_V << ADC_THRES0_HIGH_INT_RAW_S)
+#define ADC_THRES0_HIGH_INT_RAW_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_RAW_S  29
+/** ADC_SAR2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_RAW    (BIT(30))
+#define ADC_SAR2_DONE_INT_RAW_M  (ADC_SAR2_DONE_INT_RAW_V << ADC_SAR2_DONE_INT_RAW_S)
+#define ADC_SAR2_DONE_INT_RAW_V  0x00000001U
+#define ADC_SAR2_DONE_INT_RAW_S  30
+/** ADC_SAR1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_RAW    (BIT(31))
+#define ADC_SAR1_DONE_INT_RAW_M  (ADC_SAR1_DONE_INT_RAW_V << ADC_SAR1_DONE_INT_RAW_S)
+#define ADC_SAR1_DONE_INT_RAW_V  0x00000001U
+#define ADC_SAR1_DONE_INT_RAW_S  31
+
+/** ADC_INT_ST_REG register
+ *  Register
+ */
+#define ADC_INT_ST_REG (DR_REG_ADC_BASE + 0x58)
+/** ADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_ST    (BIT(26))
+#define ADC_THRES1_LOW_INT_ST_M  (ADC_THRES1_LOW_INT_ST_V << ADC_THRES1_LOW_INT_ST_S)
+#define ADC_THRES1_LOW_INT_ST_V  0x00000001U
+#define ADC_THRES1_LOW_INT_ST_S  26
+/** ADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_ST    (BIT(27))
+#define ADC_THRES0_LOW_INT_ST_M  (ADC_THRES0_LOW_INT_ST_V << ADC_THRES0_LOW_INT_ST_S)
+#define ADC_THRES0_LOW_INT_ST_V  0x00000001U
+#define ADC_THRES0_LOW_INT_ST_S  27
+/** ADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_ST    (BIT(28))
+#define ADC_THRES1_HIGH_INT_ST_M  (ADC_THRES1_HIGH_INT_ST_V << ADC_THRES1_HIGH_INT_ST_S)
+#define ADC_THRES1_HIGH_INT_ST_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_ST_S  28
+/** ADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_ST    (BIT(29))
+#define ADC_THRES0_HIGH_INT_ST_M  (ADC_THRES0_HIGH_INT_ST_V << ADC_THRES0_HIGH_INT_ST_S)
+#define ADC_THRES0_HIGH_INT_ST_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_ST_S  29
+/** ADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DONE_INT_ST    (BIT(30))
+#define ADC_APB_SARADC2_DONE_INT_ST_M  (ADC_APB_SARADC2_DONE_INT_ST_V << ADC_APB_SARADC2_DONE_INT_ST_S)
+#define ADC_APB_SARADC2_DONE_INT_ST_V  0x00000001U
+#define ADC_APB_SARADC2_DONE_INT_ST_S  30
+/** ADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DONE_INT_ST    (BIT(31))
+#define ADC_APB_SARADC1_DONE_INT_ST_M  (ADC_APB_SARADC1_DONE_INT_ST_V << ADC_APB_SARADC1_DONE_INT_ST_S)
+#define ADC_APB_SARADC1_DONE_INT_ST_V  0x00000001U
+#define ADC_APB_SARADC1_DONE_INT_ST_S  31
+
+/** ADC_INT_CLR_REG register
+ *  Register
+ */
+#define ADC_INT_CLR_REG (DR_REG_ADC_BASE + 0x5c)
+/** ADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_CLR    (BIT(26))
+#define ADC_THRES1_LOW_INT_CLR_M  (ADC_THRES1_LOW_INT_CLR_V << ADC_THRES1_LOW_INT_CLR_S)
+#define ADC_THRES1_LOW_INT_CLR_V  0x00000001U
+#define ADC_THRES1_LOW_INT_CLR_S  26
+/** ADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_CLR    (BIT(27))
+#define ADC_THRES0_LOW_INT_CLR_M  (ADC_THRES0_LOW_INT_CLR_V << ADC_THRES0_LOW_INT_CLR_S)
+#define ADC_THRES0_LOW_INT_CLR_V  0x00000001U
+#define ADC_THRES0_LOW_INT_CLR_S  27
+/** ADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_CLR    (BIT(28))
+#define ADC_THRES1_HIGH_INT_CLR_M  (ADC_THRES1_HIGH_INT_CLR_V << ADC_THRES1_HIGH_INT_CLR_S)
+#define ADC_THRES1_HIGH_INT_CLR_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_CLR_S  28
+/** ADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_CLR    (BIT(29))
+#define ADC_THRES0_HIGH_INT_CLR_M  (ADC_THRES0_HIGH_INT_CLR_V << ADC_THRES0_HIGH_INT_CLR_S)
+#define ADC_THRES0_HIGH_INT_CLR_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_CLR_S  29
+/** ADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DONE_INT_CLR    (BIT(30))
+#define ADC_APB_SARADC2_DONE_INT_CLR_M  (ADC_APB_SARADC2_DONE_INT_CLR_V << ADC_APB_SARADC2_DONE_INT_CLR_S)
+#define ADC_APB_SARADC2_DONE_INT_CLR_V  0x00000001U
+#define ADC_APB_SARADC2_DONE_INT_CLR_S  30
+/** ADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DONE_INT_CLR    (BIT(31))
+#define ADC_APB_SARADC1_DONE_INT_CLR_M  (ADC_APB_SARADC1_DONE_INT_CLR_V << ADC_APB_SARADC1_DONE_INT_CLR_S)
+#define ADC_APB_SARADC1_DONE_INT_CLR_V  0x00000001U
+#define ADC_APB_SARADC1_DONE_INT_CLR_S  31
+
+/** ADC_DMA_CONF_REG register
+ *  Register
+ */
+#define ADC_DMA_CONF_REG (DR_REG_ADC_BASE + 0x60)
+/** ADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
+ *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+ */
+#define ADC_APB_ADC_EOF_NUM    0x0000FFFFU
+#define ADC_APB_ADC_EOF_NUM_M  (ADC_APB_ADC_EOF_NUM_V << ADC_APB_ADC_EOF_NUM_S)
+#define ADC_APB_ADC_EOF_NUM_V  0x0000FFFFU
+#define ADC_APB_ADC_EOF_NUM_S  0
+/** ADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
+ *  reset_apb_adc_state
+ */
+#define ADC_APB_ADC_RESET_FSM    (BIT(30))
+#define ADC_APB_ADC_RESET_FSM_M  (ADC_APB_ADC_RESET_FSM_V << ADC_APB_ADC_RESET_FSM_S)
+#define ADC_APB_ADC_RESET_FSM_V  0x00000001U
+#define ADC_APB_ADC_RESET_FSM_S  30
+/** ADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc use spi_dma
+ */
+#define ADC_APB_ADC_TRANS    (BIT(31))
+#define ADC_APB_ADC_TRANS_M  (ADC_APB_ADC_TRANS_V << ADC_APB_ADC_TRANS_S)
+#define ADC_APB_ADC_TRANS_V  0x00000001U
+#define ADC_APB_ADC_TRANS_S  31
+
+/** ADC_SAR2_DATA_STATUS_REG register
+ *  Register
+ */
+#define ADC_SAR2_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x64)
+/** ADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DATA    0x0001FFFFU
+#define ADC_APB_SARADC2_DATA_M  (ADC_APB_SARADC2_DATA_V << ADC_APB_SARADC2_DATA_S)
+#define ADC_APB_SARADC2_DATA_V  0x0001FFFFU
+#define ADC_APB_SARADC2_DATA_S  0
+
+/** ADC_CALI_REG register
+ *  Register
+ */
+#define ADC_CALI_REG (DR_REG_ADC_BASE + 0x68)
+/** ADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
+ *  need_des
+ */
+#define ADC_CALI_CFG    0x0001FFFFU
+#define ADC_CALI_CFG_M  (ADC_CALI_CFG_V << ADC_CALI_CFG_S)
+#define ADC_CALI_CFG_V  0x0001FFFFU
+#define ADC_CALI_CFG_S  0
+
+/** ADC_RND_ECO_LOW_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_LOW_REG (DR_REG_ADC_BASE + 0x6c)
+/** ADC_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  rnd eco low
+ */
+#define ADC_RND_ECO_LOW    0xFFFFFFFFU
+#define ADC_RND_ECO_LOW_M  (ADC_RND_ECO_LOW_V << ADC_RND_ECO_LOW_S)
+#define ADC_RND_ECO_LOW_V  0xFFFFFFFFU
+#define ADC_RND_ECO_LOW_S  0
+
+/** ADC_RND_ECO_HIGH_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_HIGH_REG (DR_REG_ADC_BASE + 0x70)
+/** ADC_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  rnd eco high
+ */
+#define ADC_RND_ECO_HIGH    0xFFFFFFFFU
+#define ADC_RND_ECO_HIGH_M  (ADC_RND_ECO_HIGH_V << ADC_RND_ECO_HIGH_S)
+#define ADC_RND_ECO_HIGH_V  0xFFFFFFFFU
+#define ADC_RND_ECO_HIGH_S  0
+
+/** ADC_RND_ECO_CS_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_CS_REG (DR_REG_ADC_BASE + 0x74)
+/** ADC_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_RND_ECO_EN    (BIT(0))
+#define ADC_RND_ECO_EN_M  (ADC_RND_ECO_EN_V << ADC_RND_ECO_EN_S)
+#define ADC_RND_ECO_EN_V  0x00000001U
+#define ADC_RND_ECO_EN_S  0
+/** ADC_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_RND_ECO_RESULT    (BIT(1))
+#define ADC_RND_ECO_RESULT_M  (ADC_RND_ECO_RESULT_V << ADC_RND_ECO_RESULT_S)
+#define ADC_RND_ECO_RESULT_V  0x00000001U
+#define ADC_RND_ECO_RESULT_S  1
+
+/** ADC_CTRL_DATE_REG register
+ *  Register
+ */
+#define ADC_CTRL_DATE_REG (DR_REG_ADC_BASE + 0x3fc)
+/** ADC_CTRL_DATE : R/W; bitpos: [30:0]; default: 35725920;
+ *  need_des
+ */
+#define ADC_CTRL_DATE    0x7FFFFFFFU
+#define ADC_CTRL_DATE_M  (ADC_CTRL_DATE_V << ADC_CTRL_DATE_S)
+#define ADC_CTRL_DATE_V  0x7FFFFFFFU
+#define ADC_CTRL_DATE_S  0
+/** ADC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_CLK_EN    (BIT(31))
+#define ADC_CLK_EN_M  (ADC_CLK_EN_V << ADC_CLK_EN_S)
+#define ADC_CLK_EN_V  0x00000001U
+#define ADC_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/adc_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/adc_struct.h
new file mode 100644
index 0000000000..1103ce9498
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/adc_struct.h
@@ -0,0 +1,621 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13426
+
+/** Group: Configure Register */
+/** Type of ctrl_reg register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** start_force : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t start_force:1;
+        /** start : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t start:1;
+        /** work_mode : R/W; bitpos: [3:2]; default: 0;
+         *  0: single mode, 1: double mode, 2: alternate mode
+         */
+        uint32_t work_mode:2;
+        /** sar_sel : R/W; bitpos: [4]; default: 0;
+         *  0: SAR1, 1: SAR2, only work for single SAR mode
+         */
+        uint32_t sar_sel:1;
+        /** sar_clk_gated : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t sar_clk_gated:1;
+        /** sar_clk_div : R/W; bitpos: [13:6]; default: 4;
+         *  SAR clock divider
+         */
+        uint32_t sar_clk_div:8;
+        /** sar1_patt_len : R/W; bitpos: [17:14]; default: 15;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t sar1_patt_len:4;
+        /** sar2_patt_len : R/W; bitpos: [21:18]; default: 15;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t sar2_patt_len:4;
+        /** sar1_patt_p_clear : R/W; bitpos: [22]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC1 CTRL
+         */
+        uint32_t sar1_patt_p_clear:1;
+        /** sar2_patt_p_clear : R/W; bitpos: [23]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC2 CTRL
+         */
+        uint32_t sar2_patt_p_clear:1;
+        /** data_sar_sel : R/W; bitpos: [24]; default: 0;
+         *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+         *  resolution should not be larger than 11 bits.
+         */
+        uint32_t data_sar_sel:1;
+        /** data_to_i2s : R/W; bitpos: [25]; default: 0;
+         *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+         */
+        uint32_t data_to_i2s:1;
+        /** xpd_sar1_force : R/W; bitpos: [27:26]; default: 0;
+         *  force option to xpd sar1 blocks
+         */
+        uint32_t xpd_sar1_force:2;
+        /** xpd_sar2_force : R/W; bitpos: [29:28]; default: 0;
+         *  force option to xpd sar2 blocks
+         */
+        uint32_t xpd_sar2_force:2;
+        /** wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
+         *  wait arbit signal stable after sar_done
+         */
+        uint32_t wait_arb_cycle:2;
+    };
+    uint32_t val;
+} adc_ctrl_reg_reg_t;
+
+/** Type of ctrl2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** meas_num_limit : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t meas_num_limit:1;
+        /** max_meas_num : R/W; bitpos: [8:1]; default: 255;
+         *  max conversion number
+         */
+        uint32_t max_meas_num:8;
+        /** sar1_inv : R/W; bitpos: [9]; default: 0;
+         *  1: data to DIG ADC1 CTRL is inverted, otherwise not
+         */
+        uint32_t sar1_inv:1;
+        /** sar2_inv : R/W; bitpos: [10]; default: 0;
+         *  1: data to DIG ADC2 CTRL is inverted, otherwise not
+         */
+        uint32_t sar2_inv:1;
+        /** timer_sel : R/W; bitpos: [11]; default: 0;
+         *  1: select saradc timer 0: i2s_ws trigger
+         */
+        uint32_t timer_sel:1;
+        /** timer_target : R/W; bitpos: [23:12]; default: 10;
+         *  to set saradc timer target
+         */
+        uint32_t timer_target:12;
+        /** timer_en : R/W; bitpos: [24]; default: 0;
+         *  to enable saradc timer trigger
+         */
+        uint32_t timer_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} adc_ctrl2_reg_t;
+
+/** Type of filter_ctrl1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** filter_factor1 : R/W; bitpos: [28:26]; default: 0;
+         *  need_des
+         */
+        uint32_t filter_factor1:3;
+        /** filter_factor0 : R/W; bitpos: [31:29]; default: 0;
+         *  need_des
+         */
+        uint32_t filter_factor0:3;
+    };
+    uint32_t val;
+} adc_filter_ctrl1_reg_t;
+
+/** Type of filter_ctrl1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t xpd_wait:8;
+        uint32_t rstb_wait:8;
+        uint32_t standby_wait:8;
+        uint32_t reserved24:8;
+    };
+    uint32_t val;
+} adc_fsm_wait_reg_t;
+
+/** Type of sar1_patt_tab register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab : R/W; bitpos: [23:0]; default: 0;
+         *  item 0 ~ 3 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab_reg_t;
+
+/** Type of sar2_patt_tab1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab : R/W; bitpos: [23:0]; default: 0;
+         *  item 0 ~ 3 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab_reg_t;
+
+/** Type of arb_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** arb_apb_force : R/W; bitpos: [2]; default: 0;
+         *  adc2 arbiter force to enableapb controller
+         */
+        uint32_t arb_apb_force:1;
+        /** arb_rtc_force : R/W; bitpos: [3]; default: 0;
+         *  adc2 arbiter force to enable rtc controller
+         */
+        uint32_t arb_rtc_force:1;
+        /** arb_wifi_force : R/W; bitpos: [4]; default: 0;
+         *  adc2 arbiter force to enable wifi controller
+         */
+        uint32_t arb_wifi_force:1;
+        /** arb_grant_force : R/W; bitpos: [5]; default: 0;
+         *  adc2 arbiter force grant
+         */
+        uint32_t arb_grant_force:1;
+        /** arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
+         *  Set adc2 arbiterapb priority
+         */
+        uint32_t arb_apb_priority:2;
+        /** arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
+         *  Set adc2 arbiter rtc priority
+         */
+        uint32_t arb_rtc_priority:2;
+        /** arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
+         *  Set adc2 arbiter wifi priority
+         */
+        uint32_t arb_wifi_priority:2;
+        /** arb_fix_priority : R/W; bitpos: [12]; default: 0;
+         *  adc2 arbiter uses fixed priority
+         */
+        uint32_t arb_fix_priority:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} adc_arb_ctrl_reg_t;
+
+/** Type of filter_ctrl0 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** filter_channel1 : R/W; bitpos: [18:14]; default: 13;
+         *  need_des
+         */
+        uint32_t filter_channel1:5;
+        /** filter_channel0 : R/W; bitpos: [23:19]; default: 13;
+         *  apb_adc1_filter_factor
+         */
+        uint32_t filter_channel0:5;
+        uint32_t reserved_24:7;
+        /** filter_reset : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc1_filter
+         */
+        uint32_t filter_reset:1;
+    };
+    uint32_t val;
+} adc_filter_ctrl0_reg_t;
+
+/** Type of sar1_data_status register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_data:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_sar1_data_status_reg_t;
+
+/** Type of thres0_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres0_channel : R/W; bitpos: [4:0]; default: 13;
+         *  need_des
+         */
+        uint32_t thres0_channel:5;
+        /** thres0_high : R/W; bitpos: [17:5]; default: 8191;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres0_high:13;
+        /** thres0_low : R/W; bitpos: [30:18]; default: 0;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres0_low:13;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} adc_thres0_ctrl_reg_t;
+
+/** Type of thres1_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres1_channel : R/W; bitpos: [4:0]; default: 13;
+         *  need_des
+         */
+        uint32_t thres1_channel:5;
+        /** thres1_high : R/W; bitpos: [17:5]; default: 8191;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres1_high:13;
+        /** thres1_low : R/W; bitpos: [30:18]; default: 0;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres1_low:13;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} adc_thres1_ctrl_reg_t;
+
+/** Type of thres_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** thres_all_en : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres_all_en:1;
+        /** thres3_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres3_en:1;
+        /** thres2_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres2_en:1;
+        /** thres1_en : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_en:1;
+        /** thres0_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_en:1;
+    };
+    uint32_t val;
+} adc_thres_ctrl_reg_t;
+
+/** Type of int_ena register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_ena:1;
+        /** thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_ena:1;
+        /** thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_ena:1;
+        /** thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_ena:1;
+        /** sar2_done_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_ena:1;
+        /** sar1_done_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_ena:1;
+    };
+    uint32_t val;
+} adc_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_raw:1;
+        /** thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_raw:1;
+        /** thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_raw:1;
+        /** thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_raw:1;
+        /** sar2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_raw:1;
+        /** sar1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_raw:1;
+    };
+    uint32_t val;
+} adc_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_st : RO; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_st:1;
+        /** thres0_low_int_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_st:1;
+        /** thres1_high_int_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_st:1;
+        /** thres0_high_int_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_st:1;
+        /** apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_done_int_st:1;
+        /** apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_done_int_st:1;
+    };
+    uint32_t val;
+} adc_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_clr : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_clr:1;
+        /** thres0_low_int_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_clr:1;
+        /** thres1_high_int_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_clr:1;
+        /** thres0_high_int_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_clr:1;
+        /** apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_done_int_clr:1;
+        /** apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_done_int_clr:1;
+    };
+    uint32_t val;
+} adc_int_clr_reg_t;
+
+/** Type of dma_conf register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
+         *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+         */
+        uint32_t apb_adc_eof_num:16;
+        uint32_t reserved_16:14;
+        /** apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
+         *  reset_apb_adc_state
+         */
+        uint32_t apb_adc_reset_fsm:1;
+        /** apb_adc_trans : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc use spi_dma
+         */
+        uint32_t apb_adc_trans:1;
+    };
+    uint32_t val;
+} adc_dma_conf_reg_t;
+
+/** Type of sar2_data_status register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_data:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_sar2_data_status_reg_t;
+
+/** Type of cali register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** cali_cfg : R/W; bitpos: [16:0]; default: 32768;
+         *  need_des
+         */
+        uint32_t cali_cfg:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_cali_reg_t;
+
+/** Type of rnd_eco_low register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rnd eco low
+         */
+        uint32_t rnd_eco_low:32;
+    };
+    uint32_t val;
+} adc_rnd_eco_low_reg_t;
+
+/** Type of rnd_eco_high register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rnd eco high
+         */
+        uint32_t rnd_eco_high:32;
+    };
+    uint32_t val;
+} adc_rnd_eco_high_reg_t;
+
+/** Type of rnd_eco_cs register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t rnd_eco_en:1;
+        /** rnd_eco_result : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t rnd_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} adc_rnd_eco_cs_reg_t;
+
+/** Type of ctrl_date register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** ctrl_date : R/W; bitpos: [30:0]; default: 35725920;
+         *  need_des
+         */
+        uint32_t ctrl_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} adc_ctrl_date_reg_t;
+
+
+typedef struct {
+    volatile adc_ctrl_reg_reg_t ctrl_reg;
+    volatile adc_ctrl2_reg_t ctrl2;
+    volatile adc_filter_ctrl1_reg_t filter_ctrl1;
+    volatile adc_fsm_wait_reg_t fsm_wait;
+    uint32_t reserved_00c[2];
+    volatile adc_sar1_patt_tab_reg_t sar1_patt_tab[4];
+    volatile adc_sar2_patt_tab_reg_t sar2_patt_tab[4];
+    volatile adc_arb_ctrl_reg_t arb_ctrl;
+    volatile adc_filter_ctrl0_reg_t filter_ctrl0;
+    volatile adc_sar1_data_status_reg_t sar1_data_status;
+    volatile adc_thres0_ctrl_reg_t thres0_ctrl;
+    volatile adc_thres1_ctrl_reg_t thres1_ctrl;
+    volatile adc_thres_ctrl_reg_t thres_ctrl;
+    volatile adc_int_ena_reg_t int_ena;
+    volatile adc_int_raw_reg_t int_raw;
+    volatile adc_int_st_reg_t int_st;
+    volatile adc_int_clr_reg_t int_clr;
+    volatile adc_dma_conf_reg_t dma_conf;
+    volatile adc_sar2_data_status_reg_t sar2_data_status;
+    volatile adc_cali_reg_t cali;
+    volatile adc_rnd_eco_low_reg_t rnd_eco_low;
+    volatile adc_rnd_eco_high_reg_t rnd_eco_high;
+    volatile adc_rnd_eco_cs_reg_t rnd_eco_cs;
+    uint32_t reserved_078[225];
+    volatile adc_ctrl_date_reg_t ctrl_date;
+} adc_dev_t;
+
+extern adc_dev_t ADC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/aes_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/aes_eco5_reg.h
new file mode 100644
index 0000000000..5d8b0b9a53
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/aes_eco5_reg.h
@@ -0,0 +1,462 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AES_KEY_0_REG register
+ *  AES key data register 0
+ */
+#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_1_REG register
+ *  AES key data register 1
+ */
+#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_2_REG register
+ *  AES key data register 2
+ */
+#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_3_REG register
+ *  AES key data register 3
+ */
+#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_4_REG register
+ *  AES key data register 4
+ */
+#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_5_REG register
+ *  AES key data register 5
+ */
+#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_6_REG register
+ *  AES key data register 6
+ */
+#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_7_REG register
+ *  AES key data register 7
+ */
+#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_TEXT_IN_0_REG register
+ *  Source text data register 0
+ */
+#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_1_REG register
+ *  Source text data register 1
+ */
+#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_2_REG register
+ *  Source text data register 2
+ */
+#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_3_REG register
+ *  Source text data register 3
+ */
+#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_OUT_0_REG register
+ *  Result text data register 0
+ */
+#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_1_REG register
+ *  Result text data register 1
+ */
+#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_2_REG register
+ *  Result text data register 2
+ */
+#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_3_REG register
+ *  Result text data register 3
+ */
+#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_MODE_REG register
+ *  Defines key length and encryption / decryption
+ */
+#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
+/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the key length and encryption / decryption of the AES accelerator.
+ *  0: AES-128 encryption
+ *  1: AES-192 encryption
+ *  2: AES-256 encryption
+ *  3: Reserved
+ *  4: AES-128 decryption
+ *  5: AES-192 decryption
+ *  6: AES-256 decryption
+ *  7: Reserved
+ */
+#define AES_MODE    0x00000007U
+#define AES_MODE_M  (AES_MODE_V << AES_MODE_S)
+#define AES_MODE_V  0x00000007U
+#define AES_MODE_S  0
+
+/** AES_TRIGGER_REG register
+ *  Operation start controlling register
+ */
+#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
+/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to start AES operation.
+ *  0: No effect
+ *  1: Start
+ */
+#define AES_TRIGGER    (BIT(0))
+#define AES_TRIGGER_M  (AES_TRIGGER_V << AES_TRIGGER_S)
+#define AES_TRIGGER_V  0x00000001U
+#define AES_TRIGGER_S  0
+
+/** AES_STATE_REG register
+ *  Operation status register
+ */
+#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
+/** AES_STATE : RO; bitpos: [1:0]; default: 0;
+ *  Represents the working status of the AES accelerator.
+ *  In Typical AES working mode:
+ *  0: IDLE
+ *  1: WORK
+ *  2: No effect
+ *  3: No effect
+ *  In DMA-AES working mode:
+ *  0: IDLE
+ *  1: WORK
+ *  2: DONE
+ *  3: No effect
+ */
+#define AES_STATE    0x00000003U
+#define AES_STATE_M  (AES_STATE_V << AES_STATE_S)
+#define AES_STATE_V  0x00000003U
+#define AES_STATE_S  0
+
+/** AES_IV_MEM register
+ *  The memory that stores initialization vector
+ */
+#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
+#define AES_IV_MEM_SIZE_BYTES 16
+
+/** AES_H_MEM register
+ *  The memory that stores GCM hash subkey
+ */
+#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
+#define AES_H_MEM_SIZE_BYTES 16
+
+/** AES_J0_MEM register
+ *  The memory that stores J0
+ */
+#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
+#define AES_J0_MEM_SIZE_BYTES 16
+
+/** AES_T0_MEM register
+ *  The memory that stores T0
+ */
+#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
+#define AES_T0_MEM_SIZE_BYTES 16
+
+/** AES_DMA_ENABLE_REG register
+ *  Selects the working mode of the AES accelerator
+ */
+#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
+/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Configures the working mode of the AES accelerator.
+ *  0: Typical AES
+ *  1: DMA-AES
+ */
+#define AES_DMA_ENABLE    (BIT(0))
+#define AES_DMA_ENABLE_M  (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
+#define AES_DMA_ENABLE_V  0x00000001U
+#define AES_DMA_ENABLE_S  0
+
+/** AES_BLOCK_MODE_REG register
+ *  Defines the block cipher mode
+ */
+#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
+/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the block cipher mode of the AES accelerator operating under the DMA-AES
+ *  working mode.
+ *  0: ECB (Electronic Code Block)
+ *  1: CBC (Cipher Block Chaining)
+ *  2: OFB (Output FeedBack)
+ *  3: CTR (Counter)
+ *  4: CFB8 (8-bit Cipher FeedBack)
+ *  5: CFB128 (128-bit Cipher FeedBack)
+ *  6: GCM
+ *  7: Reserved
+ */
+#define AES_BLOCK_MODE    0x00000007U
+#define AES_BLOCK_MODE_M  (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
+#define AES_BLOCK_MODE_V  0x00000007U
+#define AES_BLOCK_MODE_S  0
+
+/** AES_BLOCK_NUM_REG register
+ *  Block number configuration register
+ */
+#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
+/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
+ *  Represents the Block Number of plaintext or ciphertext when the AES accelerator
+ *  operates under the DMA-AES working mode. For details, see Section . "
+ */
+#define AES_BLOCK_NUM    0xFFFFFFFFU
+#define AES_BLOCK_NUM_M  (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
+#define AES_BLOCK_NUM_V  0xFFFFFFFFU
+#define AES_BLOCK_NUM_S  0
+
+/** AES_INC_SEL_REG register
+ *  Standard incrementing function register
+ */
+#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
+/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures the Standard Incrementing Function for CTR block operation.
+ *  0: INC_32
+ *  1: INC_128
+ */
+#define AES_INC_SEL    (BIT(0))
+#define AES_INC_SEL_M  (AES_INC_SEL_V << AES_INC_SEL_S)
+#define AES_INC_SEL_V  0x00000001U
+#define AES_INC_SEL_S  0
+
+/** AES_INT_CLEAR_REG register
+ *  DMA-AES interrupt clear register
+ */
+#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
+/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear AES interrupt.
+ *  0: No effect
+ *  1: Clear
+ */
+#define AES_INT_CLEAR    (BIT(0))
+#define AES_INT_CLEAR_M  (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
+#define AES_INT_CLEAR_V  0x00000001U
+#define AES_INT_CLEAR_S  0
+
+/** AES_INT_ENA_REG register
+ *  DMA-AES interrupt enable register
+ */
+#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
+/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable AES interrupt.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AES_INT_ENA    (BIT(0))
+#define AES_INT_ENA_M  (AES_INT_ENA_V << AES_INT_ENA_S)
+#define AES_INT_ENA_V  0x00000001U
+#define AES_INT_ENA_S  0
+
+/** AES_DATE_REG register
+ *  AES version control register
+ */
+#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
+/** AES_DATE : R/W; bitpos: [27:0]; default: 36774000;
+ *  This bits stores the version information of AES.
+ */
+#define AES_DATE    0x0FFFFFFFU
+#define AES_DATE_M  (AES_DATE_V << AES_DATE_S)
+#define AES_DATE_V  0x0FFFFFFFU
+#define AES_DATE_S  0
+
+/** AES_DMA_EXIT_REG register
+ *  Operation exit controlling register
+ */
+#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
+/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to exit AES operation.
+ *  0: No effect
+ *  1: Exit
+ *  Only valid for DMA-AES operation.
+ */
+#define AES_DMA_EXIT    (BIT(0))
+#define AES_DMA_EXIT_M  (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
+#define AES_DMA_EXIT_V  0x00000001U
+#define AES_DMA_EXIT_S  0
+
+/** AES_RX_RESET_REG register
+ *  AES-DMA reset rx-fifo register
+ */
+#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
+/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset rx_fifo under dma_aes working mode.
+ */
+#define AES_RX_RESET    (BIT(0))
+#define AES_RX_RESET_M  (AES_RX_RESET_V << AES_RX_RESET_S)
+#define AES_RX_RESET_V  0x00000001U
+#define AES_RX_RESET_S  0
+
+/** AES_TX_RESET_REG register
+ *  AES-DMA reset tx-fifo register
+ */
+#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
+/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset tx_fifo under dma_aes working mode.
+ */
+#define AES_TX_RESET    (BIT(0))
+#define AES_TX_RESET_M  (AES_TX_RESET_V << AES_TX_RESET_S)
+#define AES_TX_RESET_V  0x00000001U
+#define AES_TX_RESET_S  0
+
+/** AES_PSEUDO_REG register
+ *  AES PSEUDO function configure register
+ */
+#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
+/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
+ *  This bit decides whether the pseudo round function is enable or not.
+ */
+#define AES_PSEUDO_EN    (BIT(0))
+#define AES_PSEUDO_EN_M  (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
+#define AES_PSEUDO_EN_V  0x00000001U
+#define AES_PSEUDO_EN_S  0
+/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
+ *  Those bits decides the basic number of pseudo round number.
+ */
+#define AES_PSEUDO_BASE    0x0000000FU
+#define AES_PSEUDO_BASE_M  (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
+#define AES_PSEUDO_BASE_V  0x0000000FU
+#define AES_PSEUDO_BASE_S  1
+/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
+ *  Those bits decides the increment number of pseudo round number
+ */
+#define AES_PSEUDO_INC    0x00000003U
+#define AES_PSEUDO_INC_M  (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
+#define AES_PSEUDO_INC_V  0x00000003U
+#define AES_PSEUDO_INC_S  5
+/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
+ *  Those bits decides the update frequency of the pseudo-key.
+ */
+#define AES_PSEUDO_RNG_CNT    0x00000007U
+#define AES_PSEUDO_RNG_CNT_M  (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
+#define AES_PSEUDO_RNG_CNT_V  0x00000007U
+#define AES_PSEUDO_RNG_CNT_S  7
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/aes_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/aes_reg.h
new file mode 100644
index 0000000000..741786dbf1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/aes_reg.h
@@ -0,0 +1,417 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AES_KEY_0_REG register
+ *  Key material key_0 configure register
+ */
+#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_1_REG register
+ *  Key material key_1 configure register
+ */
+#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
+/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_1 that is a part of key material.
+ */
+#define AES_KEY_1    0xFFFFFFFFU
+#define AES_KEY_1_M  (AES_KEY_1_V << AES_KEY_1_S)
+#define AES_KEY_1_V  0xFFFFFFFFU
+#define AES_KEY_1_S  0
+
+/** AES_KEY_2_REG register
+ *  Key material key_2 configure register
+ */
+#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
+/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_2 that is a part of key material.
+ */
+#define AES_KEY_2    0xFFFFFFFFU
+#define AES_KEY_2_M  (AES_KEY_2_V << AES_KEY_2_S)
+#define AES_KEY_2_V  0xFFFFFFFFU
+#define AES_KEY_2_S  0
+
+/** AES_KEY_3_REG register
+ *  Key material key_3 configure register
+ */
+#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
+/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_3 that is a part of key material.
+ */
+#define AES_KEY_3    0xFFFFFFFFU
+#define AES_KEY_3_M  (AES_KEY_3_V << AES_KEY_3_S)
+#define AES_KEY_3_V  0xFFFFFFFFU
+#define AES_KEY_3_S  0
+
+/** AES_KEY_4_REG register
+ *  Key material key_4 configure register
+ */
+#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
+/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_4 that is a part of key material.
+ */
+#define AES_KEY_4    0xFFFFFFFFU
+#define AES_KEY_4_M  (AES_KEY_4_V << AES_KEY_4_S)
+#define AES_KEY_4_V  0xFFFFFFFFU
+#define AES_KEY_4_S  0
+
+/** AES_KEY_5_REG register
+ *  Key material key_5 configure register
+ */
+#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
+/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_5 that is a part of key material.
+ */
+#define AES_KEY_5    0xFFFFFFFFU
+#define AES_KEY_5_M  (AES_KEY_5_V << AES_KEY_5_S)
+#define AES_KEY_5_V  0xFFFFFFFFU
+#define AES_KEY_5_S  0
+
+/** AES_KEY_6_REG register
+ *  Key material key_6 configure register
+ */
+#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
+/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_6 that is a part of key material.
+ */
+#define AES_KEY_6    0xFFFFFFFFU
+#define AES_KEY_6_M  (AES_KEY_6_V << AES_KEY_6_S)
+#define AES_KEY_6_V  0xFFFFFFFFU
+#define AES_KEY_6_S  0
+
+/** AES_KEY_7_REG register
+ *  Key material key_7 configure register
+ */
+#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
+/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_7 that is a part of key material.
+ */
+#define AES_KEY_7    0xFFFFFFFFU
+#define AES_KEY_7_M  (AES_KEY_7_V << AES_KEY_7_S)
+#define AES_KEY_7_V  0xFFFFFFFFU
+#define AES_KEY_7_S  0
+
+/** AES_TEXT_IN_0_REG register
+ *  source text material text_in_0 configure register
+ */
+#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_1_REG register
+ *  source text material text_in_1 configure register
+ */
+#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
+/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_1 that is a part of source text material.
+ */
+#define AES_TEXT_IN_1    0xFFFFFFFFU
+#define AES_TEXT_IN_1_M  (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S)
+#define AES_TEXT_IN_1_V  0xFFFFFFFFU
+#define AES_TEXT_IN_1_S  0
+
+/** AES_TEXT_IN_2_REG register
+ *  source text material text_in_2 configure register
+ */
+#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
+/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_2 that is a part of source text material.
+ */
+#define AES_TEXT_IN_2    0xFFFFFFFFU
+#define AES_TEXT_IN_2_M  (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S)
+#define AES_TEXT_IN_2_V  0xFFFFFFFFU
+#define AES_TEXT_IN_2_S  0
+
+/** AES_TEXT_IN_3_REG register
+ *  source text material text_in_3 configure register
+ */
+#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
+/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_3 that is a part of source text material.
+ */
+#define AES_TEXT_IN_3    0xFFFFFFFFU
+#define AES_TEXT_IN_3_M  (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S)
+#define AES_TEXT_IN_3_V  0xFFFFFFFFU
+#define AES_TEXT_IN_3_S  0
+
+/** AES_TEXT_OUT_0_REG register
+ *  result text material text_out_0 configure register
+ */
+#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_1_REG register
+ *  result text material text_out_1 configure register
+ */
+#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
+/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_1 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_1    0xFFFFFFFFU
+#define AES_TEXT_OUT_1_M  (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S)
+#define AES_TEXT_OUT_1_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_1_S  0
+
+/** AES_TEXT_OUT_2_REG register
+ *  result text material text_out_2 configure register
+ */
+#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
+/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_2 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_2    0xFFFFFFFFU
+#define AES_TEXT_OUT_2_M  (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S)
+#define AES_TEXT_OUT_2_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_2_S  0
+
+/** AES_TEXT_OUT_3_REG register
+ *  result text material text_out_3 configure register
+ */
+#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
+/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_3 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_3    0xFFFFFFFFU
+#define AES_TEXT_OUT_3_M  (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S)
+#define AES_TEXT_OUT_3_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_3_S  0
+
+/** AES_MODE_REG register
+ *  AES Mode register
+ */
+#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
+/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
+ *  Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
+ */
+#define AES_MODE    0x00000007U
+#define AES_MODE_M  (AES_MODE_V << AES_MODE_S)
+#define AES_MODE_V  0x00000007U
+#define AES_MODE_S  0
+
+/** AES_ENDIAN_REG register
+ *  AES Endian configure register
+ */
+#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44)
+/** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0;
+ *  endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out
+ *  endian or out_stream endian
+ */
+#define AES_ENDIAN    0x0000003FU
+#define AES_ENDIAN_M  (AES_ENDIAN_V << AES_ENDIAN_S)
+#define AES_ENDIAN_V  0x0000003FU
+#define AES_ENDIAN_S  0
+
+/** AES_TRIGGER_REG register
+ *  AES trigger register
+ */
+#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
+/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Set this bit to start AES calculation.
+ */
+#define AES_TRIGGER    (BIT(0))
+#define AES_TRIGGER_M  (AES_TRIGGER_V << AES_TRIGGER_S)
+#define AES_TRIGGER_V  0x00000001U
+#define AES_TRIGGER_S  0
+
+/** AES_STATE_REG register
+ *  AES state register
+ */
+#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
+/** AES_STATE : RO; bitpos: [1:0]; default: 0;
+ *  Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
+ *  idle, 1: busy, 2: calculation_done.
+ */
+#define AES_STATE    0x00000003U
+#define AES_STATE_M  (AES_STATE_V << AES_STATE_S)
+#define AES_STATE_V  0x00000003U
+#define AES_STATE_S  0
+
+/** AES_IV_MEM register
+ *  The memory that stores initialization vector
+ */
+#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
+#define AES_IV_MEM_SIZE_BYTES 16
+
+/** AES_H_MEM register
+ *  The memory that stores GCM hash subkey
+ */
+#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
+#define AES_H_MEM_SIZE_BYTES 16
+
+/** AES_J0_MEM register
+ *  The memory that stores J0
+ */
+#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
+#define AES_J0_MEM_SIZE_BYTES 16
+
+/** AES_T0_MEM register
+ *  The memory that stores T0
+ */
+#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
+#define AES_T0_MEM_SIZE_BYTES 16
+
+/** AES_DMA_ENABLE_REG register
+ *  DMA-AES working mode register
+ */
+#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
+/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
+ */
+#define AES_DMA_ENABLE    (BIT(0))
+#define AES_DMA_ENABLE_M  (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
+#define AES_DMA_ENABLE_V  0x00000001U
+#define AES_DMA_ENABLE_S  0
+
+/** AES_BLOCK_MODE_REG register
+ *  AES cipher block mode register
+ */
+#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
+/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
+ *  0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
+ */
+#define AES_BLOCK_MODE    0x00000007U
+#define AES_BLOCK_MODE_M  (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
+#define AES_BLOCK_MODE_V  0x00000007U
+#define AES_BLOCK_MODE_S  0
+
+/** AES_BLOCK_NUM_REG register
+ *  AES block number register
+ */
+#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
+/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits stores the number of Plaintext/ciphertext block.
+ */
+#define AES_BLOCK_NUM    0xFFFFFFFFU
+#define AES_BLOCK_NUM_M  (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
+#define AES_BLOCK_NUM_V  0xFFFFFFFFU
+#define AES_BLOCK_NUM_S  0
+
+/** AES_INC_SEL_REG register
+ *  Standard incrementing function configure register
+ */
+#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
+/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
+ *  This bit decides the standard incrementing function. 0: INC32. 1: INC128.
+ */
+#define AES_INC_SEL    (BIT(0))
+#define AES_INC_SEL_M  (AES_INC_SEL_V << AES_INC_SEL_S)
+#define AES_INC_SEL_V  0x00000001U
+#define AES_INC_SEL_S  0
+
+/** AES_AAD_BLOCK_NUM_REG register
+ *  Additional Authential Data block number register
+ */
+#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0)
+/** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits stores the number of AAD block.
+ */
+#define AES_AAD_BLOCK_NUM    0xFFFFFFFFU
+#define AES_AAD_BLOCK_NUM_M  (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S)
+#define AES_AAD_BLOCK_NUM_V  0xFFFFFFFFU
+#define AES_AAD_BLOCK_NUM_S  0
+
+/** AES_REMAINDER_BIT_NUM_REG register
+ *  AES remainder bit number register
+ */
+#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4)
+/** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0;
+ *  Those bits stores the number of remainder bit.
+ */
+#define AES_REMAINDER_BIT_NUM    0x0000007FU
+#define AES_REMAINDER_BIT_NUM_M  (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S)
+#define AES_REMAINDER_BIT_NUM_V  0x0000007FU
+#define AES_REMAINDER_BIT_NUM_S  0
+
+/** AES_CONTINUE_REG register
+ *  AES continue register
+ */
+#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8)
+/** AES_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to continue GCM operation.
+ */
+#define AES_CONTINUE    (BIT(0))
+#define AES_CONTINUE_M  (AES_CONTINUE_V << AES_CONTINUE_S)
+#define AES_CONTINUE_V  0x00000001U
+#define AES_CONTINUE_S  0
+
+/** AES_INT_CLEAR_REG register
+ *  AES Interrupt clear register
+ */
+#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
+/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the AES interrupt.
+ */
+#define AES_INT_CLEAR    (BIT(0))
+#define AES_INT_CLEAR_M  (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
+#define AES_INT_CLEAR_V  0x00000001U
+#define AES_INT_CLEAR_S  0
+
+/** AES_INT_ENA_REG register
+ *  AES Interrupt enable register
+ */
+#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
+/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
+ */
+#define AES_INT_ENA    (BIT(0))
+#define AES_INT_ENA_M  (AES_INT_ENA_V << AES_INT_ENA_S)
+#define AES_INT_ENA_V  0x00000001U
+#define AES_INT_ENA_S  0
+
+/** AES_DATE_REG register
+ *  AES version control register
+ */
+#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
+/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936;
+ *  This bits stores the version information of AES.
+ */
+#define AES_DATE    0x3FFFFFFFU
+#define AES_DATE_M  (AES_DATE_V << AES_DATE_S)
+#define AES_DATE_V  0x3FFFFFFFU
+#define AES_DATE_S  0
+
+/** AES_DMA_EXIT_REG register
+ *  AES-DMA exit config
+ */
+#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
+/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
+ *  Set this register to leave calculation done stage. Recommend to use it after
+ *  software finishes reading DMA's output buffer.
+ */
+#define AES_DMA_EXIT    (BIT(0))
+#define AES_DMA_EXIT_M  (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
+#define AES_DMA_EXIT_V  0x00000001U
+#define AES_DMA_EXIT_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/aes_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/aes_struct.h
new file mode 100644
index 0000000000..3065c238f2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/aes_struct.h
@@ -0,0 +1,354 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Key Registers */
+/** Type of key_n register
+ *  AES key data register n
+ */
+typedef union {
+    struct {
+        /** key_0 : R/W; bitpos: [31:0]; default: 0;
+         *  This bits stores key_0 that is a part of key material.
+         */
+        uint32_t key_0:32;
+    };
+    uint32_t val;
+} aes_key_n_reg_t;
+
+
+/** Group: TEXT_IN Registers */
+/** Type of text_in_n register
+ *  Source text data register n
+ */
+typedef union {
+    struct {
+        /** text_in_0 : R/W; bitpos: [31:0]; default: 0;
+         *  This bits stores text_in_0 that is a part of source text material.
+         */
+        uint32_t text_in_0:32;
+    };
+    uint32_t val;
+} aes_text_in_n_reg_t;
+
+
+/** Group: TEXT_OUT Registers */
+/** Type of text_out_n register
+ *  Result text data register n
+ */
+typedef union {
+    struct {
+        /** text_out_0 : R/W; bitpos: [31:0]; default: 0;
+         *  This bits stores text_out_0 that is a part of result text material.
+         */
+        uint32_t text_out_0:32;
+    };
+    uint32_t val;
+} aes_text_out_n_reg_t;
+
+
+/** Group: Control / Configuration Registers */
+/** Type of mode register
+ *  Defines key length and encryption / decryption
+ */
+typedef union {
+    struct {
+        /** mode : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the key length and encryption / decryption of the AES accelerator.
+         *  0: AES-128 encryption
+         *  1: AES-192 encryption
+         *  2: AES-256 encryption
+         *  3: Reserved
+         *  4: AES-128 decryption
+         *  5: AES-192 decryption
+         *  6: AES-256 decryption
+         *  7: Reserved
+         */
+        uint32_t mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} aes_mode_reg_t;
+
+/** Type of trigger register
+ *  Operation start controlling register
+ */
+typedef union {
+    struct {
+        /** trigger : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to start AES operation.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t trigger:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_trigger_reg_t;
+
+/** Type of dma_enable register
+ *  Selects the working mode of the AES accelerator
+ */
+typedef union {
+    struct {
+        /** dma_enable : R/W; bitpos: [0]; default: 0;
+         *  Configures the working mode of the AES accelerator.
+         *  0: Typical AES
+         *  1: DMA-AES
+         */
+        uint32_t dma_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_dma_enable_reg_t;
+
+/** Type of block_mode register
+ *  Defines the block cipher mode
+ */
+typedef union {
+    struct {
+        /** block_mode : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the block cipher mode of the AES accelerator operating under the DMA-AES
+         *  working mode.
+         *  0: ECB (Electronic Code Block)
+         *  1: CBC (Cipher Block Chaining)
+         *  2: OFB (Output FeedBack)
+         *  3: CTR (Counter)
+         *  4: CFB8 (8-bit Cipher FeedBack)
+         *  5: CFB128 (128-bit Cipher FeedBack)
+         *  6: GCM
+         *  7: Reserved
+         */
+        uint32_t block_mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} aes_block_mode_reg_t;
+
+/** Type of block_num register
+ *  Block number configuration register
+ */
+typedef union {
+    struct {
+        /** block_num : R/W; bitpos: [31:0]; default: 0;
+         *  Represents the Block Number of plaintext or ciphertext when the AES accelerator
+         *  operates under the DMA-AES working mode. For details, see Section . "
+         */
+        uint32_t block_num:32;
+    };
+    uint32_t val;
+} aes_block_num_reg_t;
+
+/** Type of inc_sel register
+ *  Standard incrementing function register
+ */
+typedef union {
+    struct {
+        /** inc_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures the Standard Incrementing Function for CTR block operation.
+         *  0: INC_32
+         *  1: INC_128
+         */
+        uint32_t inc_sel:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_inc_sel_reg_t;
+
+/** Type of dma_exit register
+ *  Operation exit controlling register
+ */
+typedef union {
+    struct {
+        /** dma_exit : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to exit AES operation.
+         *  0: No effect
+         *  1: Exit
+         *  Only valid for DMA-AES operation.
+         */
+        uint32_t dma_exit:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_dma_exit_reg_t;
+
+/** Type of rx_reset register
+ *  AES-DMA reset rx-fifo register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset rx_fifo under dma_aes working mode.
+         */
+        uint32_t rx_reset:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_rx_reset_reg_t;
+
+/** Type of tx_reset register
+ *  AES-DMA reset tx-fifo register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset tx_fifo under dma_aes working mode.
+         */
+        uint32_t tx_reset:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_tx_reset_reg_t;
+
+
+/** Group: Configuration register */
+/** Type of pseudo register
+ *  AES PSEUDO function configure register
+ */
+typedef union {
+    struct {
+        /** pseudo_en : R/W; bitpos: [0]; default: 0;
+         *  This bit decides whether the pseudo round function is enable or not.
+         */
+        uint32_t pseudo_en:1;
+        /** pseudo_base : R/W; bitpos: [4:1]; default: 2;
+         *  Those bits decides the basic number of pseudo round number.
+         */
+        uint32_t pseudo_base:4;
+        /** pseudo_inc : R/W; bitpos: [6:5]; default: 2;
+         *  Those bits decides the increment number of pseudo round number
+         */
+        uint32_t pseudo_inc:2;
+        /** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7;
+         *  Those bits decides the update frequency of the pseudo-key.
+         */
+        uint32_t pseudo_rng_cnt:3;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} aes_pseudo_reg_t;
+
+
+/** Group: Status Register */
+/** Type of state register
+ *  Operation status register
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [1:0]; default: 0;
+         *  Represents the working status of the AES accelerator.
+         *  In Typical AES working mode:
+         *  0: IDLE
+         *  1: WORK
+         *  2: No effect
+         *  3: No effect
+         *  In DMA-AES working mode:
+         *  0: IDLE
+         *  1: WORK
+         *  2: DONE
+         *  3: No effect
+         */
+        uint32_t state:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} aes_state_reg_t;
+
+
+/** Group: memory type */
+
+/** Group: Interrupt Registers */
+/** Type of int_clear register
+ *  DMA-AES interrupt clear register
+ */
+typedef union {
+    struct {
+        /** int_clear : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear AES interrupt.
+         *  0: No effect
+         *  1: Clear
+         */
+        uint32_t int_clear:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_int_clear_reg_t;
+
+/** Type of int_ena register
+ *  DMA-AES interrupt enable register
+ */
+typedef union {
+    struct {
+        /** int_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable AES interrupt.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_int_ena_reg_t;
+
+
+/** Group: Version control register */
+/** Type of date register
+ *  AES version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36774000;
+         *  This bits stores the version information of AES.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} aes_date_reg_t;
+
+
+typedef struct {
+    volatile aes_key_n_reg_t key_n[8];
+    volatile aes_text_in_n_reg_t text_in_n[4];
+    volatile aes_text_out_n_reg_t text_out_n[4];
+    volatile aes_mode_reg_t mode;
+    uint32_t reserved_044;
+    volatile aes_trigger_reg_t trigger;
+    volatile aes_state_reg_t state;
+    volatile uint32_t iv[4];
+    volatile uint32_t h[4];
+    volatile uint32_t j0[4];
+    volatile uint32_t t0[4];
+    volatile aes_dma_enable_reg_t dma_enable;
+    volatile aes_block_mode_reg_t block_mode;
+    volatile aes_block_num_reg_t block_num;
+    volatile aes_inc_sel_reg_t inc_sel;
+    uint32_t reserved_0a0[3];
+    volatile aes_int_clear_reg_t int_clear;
+    volatile aes_int_ena_reg_t int_ena;
+    volatile aes_date_reg_t date;
+    volatile aes_dma_exit_reg_t dma_exit;
+    uint32_t reserved_0bc;
+    volatile aes_rx_reset_reg_t rx_reset;
+    volatile aes_tx_reset_reg_t tx_reset;
+    uint32_t reserved_0c8[2];
+    volatile aes_pseudo_reg_t pseudo;
+} aes_dev_t;
+
+extern aes_dev_t AES;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(aes_dev_t) == 0xd4, "Invalid size of aes_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_eco5_struct.h
new file mode 100644
index 0000000000..43769ae0ee
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_eco5_struct.h
@@ -0,0 +1,3866 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt Registers */
+/** Type of in_int_raw_ch0 register
+ *  Raw interrupt status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT
+         */
+        uint32_t in_done_ch0_int_raw:1;
+        /** in_suc_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT
+         */
+        uint32_t in_suc_eof_ch0_int_raw:1;
+        /** in_err_eof_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT
+         */
+        uint32_t in_err_eof_ch0_int_raw:1;
+        /** in_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT
+         */
+        uint32_t in_dscr_err_ch0_int_raw:1;
+        /** in_dscr_empty_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+         */
+        uint32_t in_dscr_empty_ch0_int_raw:1;
+        /** infifo_ovf_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT
+         */
+        uint32_t infifo_ovf_ch0_int_raw:1;
+        /** infifo_udf_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT
+         */
+        uint32_t infifo_udf_ch0_int_raw:1;
+        /** in_ahbinf_resp_err_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch0_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_raw_ch0_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of in_int_st_ch0 register
+ *  Masked interrupt status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT
+         */
+        uint32_t in_done_ch0_int_st:1;
+        /** in_suc_eof_ch0_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT
+         */
+        uint32_t in_suc_eof_ch0_int_st:1;
+        /** in_err_eof_ch0_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT
+         */
+        uint32_t in_err_eof_ch0_int_st:1;
+        /** in_dscr_err_ch0_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT
+         */
+        uint32_t in_dscr_err_ch0_int_st:1;
+        /** in_dscr_empty_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+         */
+        uint32_t in_dscr_empty_ch0_int_st:1;
+        /** infifo_ovf_ch0_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT
+         */
+        uint32_t infifo_ovf_ch0_int_st:1;
+        /** infifo_udf_ch0_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT
+         */
+        uint32_t infifo_udf_ch0_int_st:1;
+        /** in_ahbinf_resp_err_ch0_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch0_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_st_ch0_reg_t;
+
+/** Type of in_int_ena_ch0 register
+ *  Interrupt enable bits of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DONE_CH0_INT
+         */
+        uint32_t in_done_ch0_int_ena:1;
+        /** in_suc_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT
+         */
+        uint32_t in_suc_eof_ch0_int_ena:1;
+        /** in_err_eof_ch0_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT
+         */
+        uint32_t in_err_eof_ch0_int_ena:1;
+        /** in_dscr_err_ch0_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT
+         */
+        uint32_t in_dscr_err_ch0_int_ena:1;
+        /** in_dscr_empty_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+         */
+        uint32_t in_dscr_empty_ch0_int_ena:1;
+        /** infifo_ovf_ch0_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT
+         */
+        uint32_t infifo_ovf_ch0_int_ena:1;
+        /** infifo_udf_ch0_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT
+         */
+        uint32_t infifo_udf_ch0_int_ena:1;
+        /** in_ahbinf_resp_err_ch0_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch0_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_ena_ch0_reg_t;
+
+/** Type of in_int_clr_ch0 register
+ *  Interrupt clear bits of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DONE_CH0_INT
+         */
+        uint32_t in_done_ch0_int_clr:1;
+        /** in_suc_eof_ch0_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT
+         */
+        uint32_t in_suc_eof_ch0_int_clr:1;
+        /** in_err_eof_ch0_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT
+         */
+        uint32_t in_err_eof_ch0_int_clr:1;
+        /** in_dscr_err_ch0_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT
+         */
+        uint32_t in_dscr_err_ch0_int_clr:1;
+        /** in_dscr_empty_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+         */
+        uint32_t in_dscr_empty_ch0_int_clr:1;
+        /** infifo_ovf_ch0_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT
+         */
+        uint32_t infifo_ovf_ch0_int_clr:1;
+        /** infifo_udf_ch0_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT
+         */
+        uint32_t infifo_udf_ch0_int_clr:1;
+        /** in_ahbinf_resp_err_ch0_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch0_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_clr_ch0_reg_t;
+
+/** Type of in_int_raw_ch1 register
+ *  Raw interrupt status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT
+         */
+        uint32_t in_done_ch1_int_raw:1;
+        /** in_suc_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT
+         */
+        uint32_t in_suc_eof_ch1_int_raw:1;
+        /** in_err_eof_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT
+         */
+        uint32_t in_err_eof_ch1_int_raw:1;
+        /** in_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT
+         */
+        uint32_t in_dscr_err_ch1_int_raw:1;
+        /** in_dscr_empty_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+         */
+        uint32_t in_dscr_empty_ch1_int_raw:1;
+        /** infifo_ovf_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT
+         */
+        uint32_t infifo_ovf_ch1_int_raw:1;
+        /** infifo_udf_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT
+         */
+        uint32_t infifo_udf_ch1_int_raw:1;
+        /** in_ahbinf_resp_err_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch1_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_raw_ch1_reg_t;
+
+/** Type of in_int_st_ch1 register
+ *  Masked interrupt status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT
+         */
+        uint32_t in_done_ch1_int_st:1;
+        /** in_suc_eof_ch1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT
+         */
+        uint32_t in_suc_eof_ch1_int_st:1;
+        /** in_err_eof_ch1_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT
+         */
+        uint32_t in_err_eof_ch1_int_st:1;
+        /** in_dscr_err_ch1_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT
+         */
+        uint32_t in_dscr_err_ch1_int_st:1;
+        /** in_dscr_empty_ch1_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+         */
+        uint32_t in_dscr_empty_ch1_int_st:1;
+        /** infifo_ovf_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT
+         */
+        uint32_t infifo_ovf_ch1_int_st:1;
+        /** infifo_udf_ch1_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT
+         */
+        uint32_t infifo_udf_ch1_int_st:1;
+        /** in_ahbinf_resp_err_ch1_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch1_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_st_ch1_reg_t;
+
+/** Type of in_int_ena_ch1 register
+ *  Interrupt enable bits of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DONE_CH1_INT
+         */
+        uint32_t in_done_ch1_int_ena:1;
+        /** in_suc_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT
+         */
+        uint32_t in_suc_eof_ch1_int_ena:1;
+        /** in_err_eof_ch1_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT
+         */
+        uint32_t in_err_eof_ch1_int_ena:1;
+        /** in_dscr_err_ch1_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT
+         */
+        uint32_t in_dscr_err_ch1_int_ena:1;
+        /** in_dscr_empty_ch1_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+         */
+        uint32_t in_dscr_empty_ch1_int_ena:1;
+        /** infifo_ovf_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT
+         */
+        uint32_t infifo_ovf_ch1_int_ena:1;
+        /** infifo_udf_ch1_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT
+         */
+        uint32_t infifo_udf_ch1_int_ena:1;
+        /** in_ahbinf_resp_err_ch1_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch1_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_ena_ch1_reg_t;
+
+/** Type of in_int_clr_ch1 register
+ *  Interrupt clear bits of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DONE_CH1_INT
+         */
+        uint32_t in_done_ch1_int_clr:1;
+        /** in_suc_eof_ch1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT
+         */
+        uint32_t in_suc_eof_ch1_int_clr:1;
+        /** in_err_eof_ch1_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT
+         */
+        uint32_t in_err_eof_ch1_int_clr:1;
+        /** in_dscr_err_ch1_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT
+         */
+        uint32_t in_dscr_err_ch1_int_clr:1;
+        /** in_dscr_empty_ch1_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+         */
+        uint32_t in_dscr_empty_ch1_int_clr:1;
+        /** infifo_ovf_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT
+         */
+        uint32_t infifo_ovf_ch1_int_clr:1;
+        /** infifo_udf_ch1_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT
+         */
+        uint32_t infifo_udf_ch1_int_clr:1;
+        /** in_ahbinf_resp_err_ch1_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch1_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_clr_ch1_reg_t;
+
+/** Type of in_int_raw_ch2 register
+ *  Raw interrupt status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT
+         */
+        uint32_t in_done_ch2_int_raw:1;
+        /** in_suc_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT
+         */
+        uint32_t in_suc_eof_ch2_int_raw:1;
+        /** in_err_eof_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT
+         */
+        uint32_t in_err_eof_ch2_int_raw:1;
+        /** in_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT
+         */
+        uint32_t in_dscr_err_ch2_int_raw:1;
+        /** in_dscr_empty_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+         */
+        uint32_t in_dscr_empty_ch2_int_raw:1;
+        /** infifo_ovf_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT
+         */
+        uint32_t infifo_ovf_ch2_int_raw:1;
+        /** infifo_udf_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT
+         */
+        uint32_t infifo_udf_ch2_int_raw:1;
+        /** in_ahbinf_resp_err_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch2_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_raw_ch2_reg_t;
+
+/** Type of in_int_st_ch2 register
+ *  Masked interrupt status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT
+         */
+        uint32_t in_done_ch2_int_st:1;
+        /** in_suc_eof_ch2_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT
+         */
+        uint32_t in_suc_eof_ch2_int_st:1;
+        /** in_err_eof_ch2_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT
+         */
+        uint32_t in_err_eof_ch2_int_st:1;
+        /** in_dscr_err_ch2_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT
+         */
+        uint32_t in_dscr_err_ch2_int_st:1;
+        /** in_dscr_empty_ch2_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+         */
+        uint32_t in_dscr_empty_ch2_int_st:1;
+        /** infifo_ovf_ch2_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT
+         */
+        uint32_t infifo_ovf_ch2_int_st:1;
+        /** infifo_udf_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT
+         */
+        uint32_t infifo_udf_ch2_int_st:1;
+        /** in_ahbinf_resp_err_ch2_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch2_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_st_ch2_reg_t;
+
+/** Type of in_int_ena_ch2 register
+ *  Interrupt enable bits of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DONE_CH2_INT
+         */
+        uint32_t in_done_ch2_int_ena:1;
+        /** in_suc_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT
+         */
+        uint32_t in_suc_eof_ch2_int_ena:1;
+        /** in_err_eof_ch2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT
+         */
+        uint32_t in_err_eof_ch2_int_ena:1;
+        /** in_dscr_err_ch2_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT
+         */
+        uint32_t in_dscr_err_ch2_int_ena:1;
+        /** in_dscr_empty_ch2_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+         */
+        uint32_t in_dscr_empty_ch2_int_ena:1;
+        /** infifo_ovf_ch2_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT
+         */
+        uint32_t infifo_ovf_ch2_int_ena:1;
+        /** infifo_udf_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT
+         */
+        uint32_t infifo_udf_ch2_int_ena:1;
+        /** in_ahbinf_resp_err_ch2_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch2_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_ena_ch2_reg_t;
+
+/** Type of in_int_clr_ch2 register
+ *  Interrupt clear bits of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DONE_CH2_INT
+         */
+        uint32_t in_done_ch2_int_clr:1;
+        /** in_suc_eof_ch2_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT
+         */
+        uint32_t in_suc_eof_ch2_int_clr:1;
+        /** in_err_eof_ch2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT
+         */
+        uint32_t in_err_eof_ch2_int_clr:1;
+        /** in_dscr_err_ch2_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT
+         */
+        uint32_t in_dscr_err_ch2_int_clr:1;
+        /** in_dscr_empty_ch2_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+         */
+        uint32_t in_dscr_empty_ch2_int_clr:1;
+        /** infifo_ovf_ch2_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT
+         */
+        uint32_t infifo_ovf_ch2_int_clr:1;
+        /** infifo_udf_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT
+         */
+        uint32_t infifo_udf_ch2_int_clr:1;
+        /** in_ahbinf_resp_err_ch2_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch2_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_clr_ch2_reg_t;
+
+/** Type of out_int_raw_ch0 register
+ *  //Raw interrupt status of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT
+         */
+        uint32_t out_done_ch0_int_raw:1;
+        /** out_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT
+         */
+        uint32_t out_eof_ch0_int_raw:1;
+        /** out_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT
+         */
+        uint32_t out_dscr_err_ch0_int_raw:1;
+        /** out_total_eof_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+         */
+        uint32_t out_total_eof_ch0_int_raw:1;
+        /** outfifo_ovf_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT
+         */
+        uint32_t outfifo_ovf_ch0_int_raw:1;
+        /** outfifo_udf_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT
+         */
+        uint32_t outfifo_udf_ch0_int_raw:1;
+        /** out_ahbinf_resp_err_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch0_int_raw:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_raw_ch0_reg_t;
+
+/** Type of out_int_st_ch0 register
+ *  Masked interrupt status of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT
+         */
+        uint32_t out_done_ch0_int_st:1;
+        /** out_eof_ch0_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT
+         */
+        uint32_t out_eof_ch0_int_st:1;
+        /** out_dscr_err_ch0_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT
+         */
+        uint32_t out_dscr_err_ch0_int_st:1;
+        /** out_total_eof_ch0_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+         */
+        uint32_t out_total_eof_ch0_int_st:1;
+        /** outfifo_ovf_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT
+         */
+        uint32_t outfifo_ovf_ch0_int_st:1;
+        /** outfifo_udf_ch0_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT
+         */
+        uint32_t outfifo_udf_ch0_int_st:1;
+        /** out_ahbinf_resp_err_ch0_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch0_int_st:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_st_ch0_reg_t;
+
+/** Type of out_int_ena_ch0 register
+ *  Interrupt enable bits of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT
+         */
+        uint32_t out_done_ch0_int_ena:1;
+        /** out_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT
+         */
+        uint32_t out_eof_ch0_int_ena:1;
+        /** out_dscr_err_ch0_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT
+         */
+        uint32_t out_dscr_err_ch0_int_ena:1;
+        /** out_total_eof_ch0_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+         */
+        uint32_t out_total_eof_ch0_int_ena:1;
+        /** outfifo_ovf_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT
+         */
+        uint32_t outfifo_ovf_ch0_int_ena:1;
+        /** outfifo_udf_ch0_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT
+         */
+        uint32_t outfifo_udf_ch0_int_ena:1;
+        /** out_ahbinf_resp_err_ch0_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch0_int_ena:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_ena_ch0_reg_t;
+
+/** Type of out_int_clr_ch0 register
+ *  Interrupt clear bits of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT
+         */
+        uint32_t out_done_ch0_int_clr:1;
+        /** out_eof_ch0_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT
+         */
+        uint32_t out_eof_ch0_int_clr:1;
+        /** out_dscr_err_ch0_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT
+         */
+        uint32_t out_dscr_err_ch0_int_clr:1;
+        /** out_total_eof_ch0_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+         */
+        uint32_t out_total_eof_ch0_int_clr:1;
+        /** outfifo_ovf_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT
+         */
+        uint32_t outfifo_ovf_ch0_int_clr:1;
+        /** outfifo_udf_ch0_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT
+         */
+        uint32_t outfifo_udf_ch0_int_clr:1;
+        /** out_ahbinf_resp_err_ch0_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch0_int_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_clr_ch0_reg_t;
+
+/** Type of out_int_raw_ch1 register
+ *  //Raw interrupt status of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT
+         */
+        uint32_t out_done_ch1_int_raw:1;
+        /** out_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT
+         */
+        uint32_t out_eof_ch1_int_raw:1;
+        /** out_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT
+         */
+        uint32_t out_dscr_err_ch1_int_raw:1;
+        /** out_total_eof_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+         */
+        uint32_t out_total_eof_ch1_int_raw:1;
+        /** outfifo_ovf_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT
+         */
+        uint32_t outfifo_ovf_ch1_int_raw:1;
+        /** outfifo_udf_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT
+         */
+        uint32_t outfifo_udf_ch1_int_raw:1;
+        /** out_ahbinf_resp_err_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch1_int_raw:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_raw_ch1_reg_t;
+
+/** Type of out_int_st_ch1 register
+ *  Masked interrupt status of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT
+         */
+        uint32_t out_done_ch1_int_st:1;
+        /** out_eof_ch1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT
+         */
+        uint32_t out_eof_ch1_int_st:1;
+        /** out_dscr_err_ch1_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT
+         */
+        uint32_t out_dscr_err_ch1_int_st:1;
+        /** out_total_eof_ch1_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+         */
+        uint32_t out_total_eof_ch1_int_st:1;
+        /** outfifo_ovf_ch1_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT
+         */
+        uint32_t outfifo_ovf_ch1_int_st:1;
+        /** outfifo_udf_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT
+         */
+        uint32_t outfifo_udf_ch1_int_st:1;
+        /** out_ahbinf_resp_err_ch1_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch1_int_st:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_st_ch1_reg_t;
+
+/** Type of out_int_ena_ch1 register
+ *  Interrupt enable bits of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT
+         */
+        uint32_t out_done_ch1_int_ena:1;
+        /** out_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT
+         */
+        uint32_t out_eof_ch1_int_ena:1;
+        /** out_dscr_err_ch1_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT
+         */
+        uint32_t out_dscr_err_ch1_int_ena:1;
+        /** out_total_eof_ch1_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+         */
+        uint32_t out_total_eof_ch1_int_ena:1;
+        /** outfifo_ovf_ch1_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT
+         */
+        uint32_t outfifo_ovf_ch1_int_ena:1;
+        /** outfifo_udf_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT
+         */
+        uint32_t outfifo_udf_ch1_int_ena:1;
+        /** out_ahbinf_resp_err_ch1_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch1_int_ena:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_ena_ch1_reg_t;
+
+/** Type of out_int_clr_ch1 register
+ *  Interrupt clear bits of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT
+         */
+        uint32_t out_done_ch1_int_clr:1;
+        /** out_eof_ch1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT
+         */
+        uint32_t out_eof_ch1_int_clr:1;
+        /** out_dscr_err_ch1_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT
+         */
+        uint32_t out_dscr_err_ch1_int_clr:1;
+        /** out_total_eof_ch1_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+         */
+        uint32_t out_total_eof_ch1_int_clr:1;
+        /** outfifo_ovf_ch1_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT
+         */
+        uint32_t outfifo_ovf_ch1_int_clr:1;
+        /** outfifo_udf_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT
+         */
+        uint32_t outfifo_udf_ch1_int_clr:1;
+        /** out_ahbinf_resp_err_ch1_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch1_int_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_clr_ch1_reg_t;
+
+/** Type of out_int_raw_ch2 register
+ *  //Raw interrupt status of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT
+         */
+        uint32_t out_done_ch2_int_raw:1;
+        /** out_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT
+         */
+        uint32_t out_eof_ch2_int_raw:1;
+        /** out_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT
+         */
+        uint32_t out_dscr_err_ch2_int_raw:1;
+        /** out_total_eof_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+         */
+        uint32_t out_total_eof_ch2_int_raw:1;
+        /** outfifo_ovf_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT
+         */
+        uint32_t outfifo_ovf_ch2_int_raw:1;
+        /** outfifo_udf_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT
+         */
+        uint32_t outfifo_udf_ch2_int_raw:1;
+        /** out_ahbinf_resp_err_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch2_int_raw:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_raw_ch2_reg_t;
+
+/** Type of out_int_st_ch2 register
+ *  Masked interrupt status of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT
+         */
+        uint32_t out_done_ch2_int_st:1;
+        /** out_eof_ch2_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT
+         */
+        uint32_t out_eof_ch2_int_st:1;
+        /** out_dscr_err_ch2_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT
+         */
+        uint32_t out_dscr_err_ch2_int_st:1;
+        /** out_total_eof_ch2_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+         */
+        uint32_t out_total_eof_ch2_int_st:1;
+        /** outfifo_ovf_ch2_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT
+         */
+        uint32_t outfifo_ovf_ch2_int_st:1;
+        /** outfifo_udf_ch2_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT
+         */
+        uint32_t outfifo_udf_ch2_int_st:1;
+        /** out_ahbinf_resp_err_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch2_int_st:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_st_ch2_reg_t;
+
+/** Type of out_int_ena_ch2 register
+ *  Interrupt enable bits of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT
+         */
+        uint32_t out_done_ch2_int_ena:1;
+        /** out_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT
+         */
+        uint32_t out_eof_ch2_int_ena:1;
+        /** out_dscr_err_ch2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT
+         */
+        uint32_t out_dscr_err_ch2_int_ena:1;
+        /** out_total_eof_ch2_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+         */
+        uint32_t out_total_eof_ch2_int_ena:1;
+        /** outfifo_ovf_ch2_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT
+         */
+        uint32_t outfifo_ovf_ch2_int_ena:1;
+        /** outfifo_udf_ch2_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT
+         */
+        uint32_t outfifo_udf_ch2_int_ena:1;
+        /** out_ahbinf_resp_err_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch2_int_ena:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_ena_ch2_reg_t;
+
+/** Type of out_int_clr_ch2 register
+ *  Interrupt clear bits of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT
+         */
+        uint32_t out_done_ch2_int_clr:1;
+        /** out_eof_ch2_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT
+         */
+        uint32_t out_eof_ch2_int_clr:1;
+        /** out_dscr_err_ch2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT
+         */
+        uint32_t out_dscr_err_ch2_int_clr:1;
+        /** out_total_eof_ch2_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+         */
+        uint32_t out_total_eof_ch2_int_clr:1;
+        /** outfifo_ovf_ch2_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT
+         */
+        uint32_t outfifo_ovf_ch2_int_clr:1;
+        /** outfifo_udf_ch2_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT
+         */
+        uint32_t outfifo_udf_ch2_int_clr:1;
+        /** out_ahbinf_resp_err_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch2_int_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_clr_ch2_reg_t;
+
+/** Type of ahb_test register
+ *  only for test
+ */
+typedef union {
+    struct {
+        /** ahb_testmode : R/W; bitpos: [2:0]; default: 0;
+         *  reserved
+         */
+        uint32_t ahb_testmode:3;
+        uint32_t reserved_3:1;
+        /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
+         *  reserved
+         */
+        uint32_t ahb_testaddr:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_ahb_test_reg_t;
+
+/** Type of misc_conf register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0;
+         *  Write 1 and then 0 to reset the internal AHB FSM
+         */
+        uint32_t ahbm_rst_inter:1;
+        uint32_t reserved_1:1;
+        /** arb_pri_dis : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to disable the fixed-priority channel arbitration.
+         *  0: Enable
+         *  1: Disable
+         */
+        uint32_t arb_pri_dis:1;
+        /** clk_en : R/W; bitpos: [3]; default: 0;
+         *  Configures clock gating.
+         *  0: Support clock only when the application writes registers.
+         *  1: Always force the clock on for registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_misc_conf_reg_t;
+
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 2425376;
+         *  Version control register
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} ahb_dma_date_reg_t;
+
+/** Type of in_conf0_ch0 register
+ *  Configuration register 0 of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_rst_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer.
+         */
+        uint32_t in_rst_ch0:1;
+        /** in_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_ch0:1;
+        /** indscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable INCR burst transfer for RX channel 0 to read
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t indscr_burst_en_ch0:1;
+        /** in_data_burst_en_ch0 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 0 receiving data
+         *  when accessing internal SRAM.
+         */
+        uint32_t in_data_burst_en_ch0:1;
+        /** mem_trans_en_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable memory-to-memory data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t mem_trans_en_ch0:1;
+        /** in_etm_en_ch0 : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable ETM control for RX channel0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_etm_en_ch0:1;
+        /** in_data_burst_mode_sel_ch0 : R/W; bitpos: [7:6]; default: 1;
+         *  Configures max burst size for Rx channel0.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t in_data_burst_mode_sel_ch0:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_conf0_ch0_reg_t;
+
+/** Type of in_conf1_ch0 register
+ *  Configuration register 1 of RX channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** in_check_owner_ch0 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for RX channel 0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_check_owner_ch0:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_conf1_ch0_reg_t;
+
+/** Type of infifo_status_ch0 register
+ *  Receive FIFO status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_full_ch0 : RO; bitpos: [0]; default: 1;
+         *  Represents whether L1 RX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t infifo_full_ch0:1;
+        /** infifo_empty_ch0 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 RX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t infifo_empty_ch0:1;
+        uint32_t reserved_2:6;
+        /** infifo_cnt_ch0 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 RX FIFO for RX channel 0
+         */
+        uint32_t infifo_cnt_ch0:7;
+        uint32_t reserved_15:8;
+        /** in_remain_under_1b_ch0 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_ch0:1;
+        /** in_remain_under_2b_ch0 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_ch0:1;
+        /** in_remain_under_3b_ch0 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_ch0:1;
+        /** in_remain_under_4b_ch0 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_ch0:1;
+        /** in_buf_hungry_ch0 : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_ch0:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ahb_dma_infifo_status_ch0_reg_t;
+
+/** Type of in_pop_ch0 register
+ *  Receive FIFO status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch0 : RO; bitpos: [11:0]; default: 2048;
+         *  Represents the data popped from AHB_DMA FIFO.
+         */
+        uint32_t infifo_rdata_ch0:12;
+        /** infifo_pop_ch0 : WT; bitpos: [12]; default: 0;
+         *  Configures whether to pop data from AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Pop
+         */
+        uint32_t infifo_pop_ch0:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_pop_ch0_reg_t;
+
+/** Type of in_link_ch0 register
+ *  Receive FIFO status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_ch0 : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to return to current receive descriptor's address when there are
+         *  some errors in current receiving data.
+         *  0: Not return
+         *  1: Return
+         *  .
+         */
+        uint32_t inlink_auto_ret_ch0:1;
+        /** inlink_stop_ch0 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to stop AHB_DMA's RX channel 0 from receiving data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t inlink_stop_ch0:1;
+        /** inlink_start_ch0 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to enable AHB_DMA's RX channel 0 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t inlink_start_ch0:1;
+        /** inlink_restart_ch0 : WT; bitpos: [3]; default: 0;
+         *  Configures whether to restart RX channel 0 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t inlink_restart_ch0:1;
+        /** inlink_park_ch0 : RO; bitpos: [4]; default: 1;
+         *  Represents the status of the receive descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t inlink_park_ch0:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} ahb_dma_in_link_ch0_reg_t;
+
+/** Type of in_state_ch0 register
+ *  Receive status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0;
+         *  reserved
+         */
+        uint32_t inlink_dscr_addr_ch0:18;
+        /** in_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_ch0:2;
+        /** in_state_ch0 : RO; bitpos: [22:20]; default: 0;
+         *  Represents the address of the lower 18 bits of the next receive descriptor to be
+         *  processed.
+         */
+        uint32_t in_state_ch0:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_in_state_ch0_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch0 register
+ *  Receive descriptor address when EOF occurs on RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_suc_eof_des_addr_ch0_reg_t;
+
+/** Type of in_err_eof_des_addr_ch0 register
+ *  Receive descriptor address when errors occur of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when there are some errors in the
+         *  currently received data.
+         */
+        uint32_t in_err_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_err_eof_des_addr_ch0_reg_t;
+
+/** Type of in_dscr_ch0 register
+ *  Current receive descriptor address of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next receive descriptor x+1 pointed by the current
+         *  receive descriptor that has already been fetched.
+         */
+        uint32_t inlink_dscr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_ch0_reg_t;
+
+/** Type of in_dscr_bf0_ch0 register
+ *  The last receive descriptor address of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current receive descriptor x that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf0_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf0_ch0_reg_t;
+
+/** Type of in_dscr_bf1_ch0 register
+ *  The second-to-last receive descriptor address of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous receive descriptor x-1 that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf1_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf1_ch0_reg_t;
+
+/** Type of in_peri_ch0 register
+ *  Priority register of RX channel 0
+ */
+typedef union {
+    struct {
+        /** rx_pri_ch0 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of RX channel 0.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t rx_pri_ch0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_ch0_reg_t;
+
+/** Type of in_peri_sel_ch0 register
+ *  Peripheral selection register of RX channel 0
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_ch0 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to RX channel 0.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_in_sel_ch0:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_sel_ch0_reg_t;
+
+/** Type of out_conf0_ch0 register
+ *  Configuration register 0 of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_rst_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.
+         *  0: Release reset
+         *  1: Reset
+         */
+        uint32_t out_rst_ch0:1;
+        /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch0:1;
+        /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable automatic outlink write-back when all the data in TX
+         *  FIFO has been transmitted.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_auto_wrback_ch0:1;
+        /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1;
+         *  Configures when to generate EOF flag.
+         *  0: EOF flag for TX channel 0 is generated when data to be transmitted has been
+         *  pushed into FIFO in AHB_DMA.
+         *  1: EOF flag for TX channel 0 is generated when data to be transmitted has been
+         *  popped from FIFO in AHB_DMA.
+         */
+        uint32_t out_eof_mode_ch0:1;
+        /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable INCR burst transfer for TX channel 0 reading
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outdscr_burst_en_ch0:1;
+        /** out_data_burst_en_ch0 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to 1 to enable INCR4 burst transfer for Tx channel 0 transmitting data
+         *  when accessing internal SRAM.
+         */
+        uint32_t out_data_burst_en_ch0:1;
+        /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to enable ETM control for TX channel 0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_etm_en_ch0:1;
+        uint32_t reserved_7:1;
+        /** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 1;
+         *  Configures max burst size for TX channel0.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t out_data_burst_mode_sel_ch0:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_conf0_ch0_reg_t;
+
+/** Type of out_conf1_ch0 register
+ *  Configuration register 1 of TX channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** out_check_owner_ch0 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for TX channel 0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_check_owner_ch0:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_out_conf1_ch0_reg_t;
+
+/** Type of outfifo_status_ch0 register
+ *  Receive FIFO status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_full_ch0 : RO; bitpos: [0]; default: 0;
+         *  Represents whether L1 TX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t outfifo_full_ch0:1;
+        /** outfifo_empty_ch0 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 TX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t outfifo_empty_ch0:1;
+        uint32_t reserved_2:6;
+        /** outfifo_cnt_ch0 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 TX FIFO for TX channel 0
+         */
+        uint32_t outfifo_cnt_ch0:7;
+        uint32_t reserved_15:8;
+        /** out_remain_under_1b_ch0 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_ch0:1;
+        /** out_remain_under_2b_ch0 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_ch0:1;
+        /** out_remain_under_3b_ch0 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_ch0:1;
+        /** out_remain_under_4b_ch0 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_ch0:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} ahb_dma_outfifo_status_ch0_reg_t;
+
+/** Type of out_push_ch0 register
+ *  Push control register of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch0 : R/W; bitpos: [8:0]; default: 0;
+         *  Configures whether to push data into AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Push
+         */
+        uint32_t outfifo_wdata_ch0:9;
+        /** outfifo_push_ch0 : WT; bitpos: [9]; default: 0;
+         *  Configures the data that need to be pushed into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_push_ch0:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_push_ch0_reg_t;
+
+/** Type of out_link_ch0 register
+ *  Push control register of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_stop_ch0 : WT; bitpos: [0]; default: 0;
+         *  Configures whether to stop AHB_DMA's TX channel 0 from transmitting data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t outlink_stop_ch0:1;
+        /** outlink_start_ch0 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to enable AHB_DMA's TX channel 0 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outlink_start_ch0:1;
+        /** outlink_restart_ch0 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to restart TX channel 0 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t outlink_restart_ch0:1;
+        /** outlink_park_ch0 : RO; bitpos: [3]; default: 1;
+         *  Represents the status of the transmit descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t outlink_park_ch0:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_link_ch0_reg_t;
+
+/** Type of out_state_ch0 register
+ *  Transmit status of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0;
+         *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+         *  processed.
+         */
+        uint32_t outlink_dscr_addr_ch0:18;
+        /** out_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_ch0:2;
+        /** out_state_ch0 : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_ch0:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_out_state_ch0_reg_t;
+
+/** Type of out_eof_des_addr_ch0 register
+ *  Transmit descriptor address when EOF occurs on TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_des_addr_ch0_reg_t;
+
+/** Type of out_eof_bfr_des_addr_ch0 register
+ *  The last transmit descriptor address when EOF occurs on TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor before the last transmit
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_bfr_des_addr_ch0_reg_t;
+
+/** Type of out_dscr_ch0 register
+ *  Current transmit descriptor address of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next transmit descriptor y+1 pointed by the current
+         *  transmit descriptor that has already been fetched.
+         */
+        uint32_t outlink_dscr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_ch0_reg_t;
+
+/** Type of out_dscr_bf0_ch0 register
+ *  The last transmit descriptor address of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current transmit descriptor y that has already been
+         *  fetched.
+         */
+        uint32_t outlink_dscr_bf0_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf0_ch0_reg_t;
+
+/** Type of out_dscr_bf1_ch0 register
+ *  The second-to-last transmit descriptor address of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous transmit descriptor y-1 that has already
+         *  been fetched.
+         */
+        uint32_t outlink_dscr_bf1_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf1_ch0_reg_t;
+
+/** Type of out_peri_ch0 register
+ *  Priority register of TX channel 0
+ */
+typedef union {
+    struct {
+        /** tx_pri_ch0 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of TX channel 0.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t tx_pri_ch0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_ch0_reg_t;
+
+/** Type of out_peri_sel_ch0 register
+ *  Peripheral selection register of TX channel 0
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_ch0 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to TX channel 0.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_out_sel_ch0:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_sel_ch0_reg_t;
+
+/** Type of in_conf0_ch1 register
+ *  Configuration register 0 of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_rst_ch1 : R/W; bitpos: [0]; default: 0;
+         *  Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer.
+         */
+        uint32_t in_rst_ch1:1;
+        /** in_loop_test_ch1 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_ch1:1;
+        /** indscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable INCR burst transfer for RX channel 1 to read
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t indscr_burst_en_ch1:1;
+        /** in_data_burst_en_ch1 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 1 receiving data
+         *  when accessing internal SRAM.
+         */
+        uint32_t in_data_burst_en_ch1:1;
+        /** mem_trans_en_ch1 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable memory-to-memory data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t mem_trans_en_ch1:1;
+        /** in_etm_en_ch1 : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable ETM control for RX channel1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_etm_en_ch1:1;
+        /** in_data_burst_mode_sel_ch1 : R/W; bitpos: [7:6]; default: 1;
+         *  Configures max burst size for Rx channel1.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t in_data_burst_mode_sel_ch1:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_conf0_ch1_reg_t;
+
+/** Type of in_conf1_ch1 register
+ *  Configuration register 1 of RX channel 1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** in_check_owner_ch1 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for RX channel 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_check_owner_ch1:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_conf1_ch1_reg_t;
+
+/** Type of infifo_status_ch1 register
+ *  Receive FIFO status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** infifo_full_ch1 : RO; bitpos: [0]; default: 1;
+         *  Represents whether L1 RX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t infifo_full_ch1:1;
+        /** infifo_empty_ch1 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 RX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t infifo_empty_ch1:1;
+        uint32_t reserved_2:6;
+        /** infifo_cnt_ch1 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 RX FIFO for RX channel 1
+         */
+        uint32_t infifo_cnt_ch1:7;
+        uint32_t reserved_15:8;
+        /** in_remain_under_1b_ch1 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_ch1:1;
+        /** in_remain_under_2b_ch1 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_ch1:1;
+        /** in_remain_under_3b_ch1 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_ch1:1;
+        /** in_remain_under_4b_ch1 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_ch1:1;
+        /** in_buf_hungry_ch1 : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_ch1:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ahb_dma_infifo_status_ch1_reg_t;
+
+/** Type of in_pop_ch1 register
+ *  Receive FIFO status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch1 : RO; bitpos: [11:0]; default: 2048;
+         *  Represents the data popped from AHB_DMA FIFO.
+         */
+        uint32_t infifo_rdata_ch1:12;
+        /** infifo_pop_ch1 : WT; bitpos: [12]; default: 0;
+         *  Configures whether to pop data from AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Pop
+         */
+        uint32_t infifo_pop_ch1:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_pop_ch1_reg_t;
+
+/** Type of in_link_ch1 register
+ *  Receive FIFO status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_ch1 : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to return to current receive descriptor's address when there are
+         *  some errors in current receiving data.
+         *  0: Not return
+         *  1: Return
+         *  .
+         */
+        uint32_t inlink_auto_ret_ch1:1;
+        /** inlink_stop_ch1 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to stop AHB_DMA's RX channel 1 from receiving data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t inlink_stop_ch1:1;
+        /** inlink_start_ch1 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to enable AHB_DMA's RX channel 1 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t inlink_start_ch1:1;
+        /** inlink_restart_ch1 : WT; bitpos: [3]; default: 0;
+         *  Configures whether to restart RX channel 1 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t inlink_restart_ch1:1;
+        /** inlink_park_ch1 : RO; bitpos: [4]; default: 1;
+         *  Represents the status of the receive descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t inlink_park_ch1:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} ahb_dma_in_link_ch1_reg_t;
+
+/** Type of in_state_ch1 register
+ *  Receive status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0;
+         *  reserved
+         */
+        uint32_t inlink_dscr_addr_ch1:18;
+        /** in_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_ch1:2;
+        /** in_state_ch1 : RO; bitpos: [22:20]; default: 0;
+         *  Represents the address of the lower 18 bits of the next receive descriptor to be
+         *  processed.
+         */
+        uint32_t in_state_ch1:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_in_state_ch1_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch1 register
+ *  Receive descriptor address when EOF occurs on RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_suc_eof_des_addr_ch1_reg_t;
+
+/** Type of in_err_eof_des_addr_ch1 register
+ *  Receive descriptor address when errors occur of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when there are some errors in the
+         *  currently received data.
+         */
+        uint32_t in_err_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_err_eof_des_addr_ch1_reg_t;
+
+/** Type of in_dscr_ch1 register
+ *  Current receive descriptor address of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next receive descriptor x+1 pointed by the current
+         *  receive descriptor that has already been fetched.
+         */
+        uint32_t inlink_dscr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_ch1_reg_t;
+
+/** Type of in_dscr_bf0_ch1 register
+ *  The last receive descriptor address of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current receive descriptor x that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf0_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf0_ch1_reg_t;
+
+/** Type of in_dscr_bf1_ch1 register
+ *  The second-to-last receive descriptor address of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous receive descriptor x-1 that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf1_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf1_ch1_reg_t;
+
+/** Type of in_peri_ch1 register
+ *  Priority register of RX channel 1
+ */
+typedef union {
+    struct {
+        /** rx_pri_ch1 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of RX channel 1.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t rx_pri_ch1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_ch1_reg_t;
+
+/** Type of in_peri_sel_ch1 register
+ *  Peripheral selection register of RX channel 1
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_ch1 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to RX channel 1.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_in_sel_ch1:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_sel_ch1_reg_t;
+
+/** Type of out_conf0_ch1 register
+ *  Configuration register 0 of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_rst_ch1 : R/W; bitpos: [0]; default: 0;
+         *  Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer.
+         *  0: Release reset
+         *  1: Reset
+         */
+        uint32_t out_rst_ch1:1;
+        /** out_loop_test_ch1 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch1:1;
+        /** out_auto_wrback_ch1 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable automatic outlink write-back when all the data in TX
+         *  FIFO has been transmitted.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_auto_wrback_ch1:1;
+        /** out_eof_mode_ch1 : R/W; bitpos: [3]; default: 1;
+         *  Configures when to generate EOF flag.
+         *  0: EOF flag for TX channel 1 is generated when data to be transmitted has been
+         *  pushed into FIFO in AHB_DMA.
+         *  1: EOF flag for TX channel 1 is generated when data to be transmitted has been
+         *  popped from FIFO in AHB_DMA.
+         */
+        uint32_t out_eof_mode_ch1:1;
+        /** outdscr_burst_en_ch1 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable INCR burst transfer for TX channel 1 reading
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outdscr_burst_en_ch1:1;
+        /** out_data_burst_en_ch1 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data
+         *  when accessing internal SRAM.
+         */
+        uint32_t out_data_burst_en_ch1:1;
+        /** out_etm_en_ch1 : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to enable ETM control for TX channel 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_etm_en_ch1:1;
+        uint32_t reserved_7:1;
+        /** out_data_burst_mode_sel_ch1 : R/W; bitpos: [9:8]; default: 1;
+         *  Configures max burst size for TX channel1.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t out_data_burst_mode_sel_ch1:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_conf0_ch1_reg_t;
+
+/** Type of out_conf1_ch1 register
+ *  Configuration register 1 of TX channel 1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** out_check_owner_ch1 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for TX channel 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_check_owner_ch1:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_out_conf1_ch1_reg_t;
+
+/** Type of outfifo_status_ch1 register
+ *  Receive FIFO status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** outfifo_full_ch1 : RO; bitpos: [0]; default: 0;
+         *  Represents whether L1 TX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t outfifo_full_ch1:1;
+        /** outfifo_empty_ch1 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 TX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t outfifo_empty_ch1:1;
+        uint32_t reserved_2:6;
+        /** outfifo_cnt_ch1 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 TX FIFO for TX channel 1
+         */
+        uint32_t outfifo_cnt_ch1:7;
+        uint32_t reserved_15:8;
+        /** out_remain_under_1b_ch1 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_ch1:1;
+        /** out_remain_under_2b_ch1 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_ch1:1;
+        /** out_remain_under_3b_ch1 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_ch1:1;
+        /** out_remain_under_4b_ch1 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_ch1:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} ahb_dma_outfifo_status_ch1_reg_t;
+
+/** Type of out_push_ch1 register
+ *  Push control register of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch1 : R/W; bitpos: [8:0]; default: 0;
+         *  Configures whether to push data into AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Push
+         */
+        uint32_t outfifo_wdata_ch1:9;
+        /** outfifo_push_ch1 : WT; bitpos: [9]; default: 0;
+         *  Configures the data that need to be pushed into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_push_ch1:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_push_ch1_reg_t;
+
+/** Type of out_link_ch1 register
+ *  Push control register of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_stop_ch1 : WT; bitpos: [0]; default: 0;
+         *  Configures whether to stop AHB_DMA's TX channel 1 from transmitting data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t outlink_stop_ch1:1;
+        /** outlink_start_ch1 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to enable AHB_DMA's TX channel 1 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outlink_start_ch1:1;
+        /** outlink_restart_ch1 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to restart TX channel 1 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t outlink_restart_ch1:1;
+        /** outlink_park_ch1 : RO; bitpos: [3]; default: 1;
+         *  Represents the status of the transmit descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t outlink_park_ch1:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_link_ch1_reg_t;
+
+/** Type of out_state_ch1 register
+ *  Transmit status of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0;
+         *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+         *  processed.
+         */
+        uint32_t outlink_dscr_addr_ch1:18;
+        /** out_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_ch1:2;
+        /** out_state_ch1 : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_ch1:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_out_state_ch1_reg_t;
+
+/** Type of out_eof_des_addr_ch1 register
+ *  Transmit descriptor address when EOF occurs on TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_des_addr_ch1_reg_t;
+
+/** Type of out_eof_bfr_des_addr_ch1 register
+ *  The last transmit descriptor address when EOF occurs on TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor before the last transmit
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_bfr_des_addr_ch1_reg_t;
+
+/** Type of out_dscr_ch1 register
+ *  Current transmit descriptor address of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next transmit descriptor y+1 pointed by the current
+         *  transmit descriptor that has already been fetched.
+         */
+        uint32_t outlink_dscr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_ch1_reg_t;
+
+/** Type of out_dscr_bf0_ch1 register
+ *  The last transmit descriptor address of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current transmit descriptor y that has already been
+         *  fetched.
+         */
+        uint32_t outlink_dscr_bf0_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf0_ch1_reg_t;
+
+/** Type of out_dscr_bf1_ch1 register
+ *  The second-to-last transmit descriptor address of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous transmit descriptor y-1 that has already
+         *  been fetched.
+         */
+        uint32_t outlink_dscr_bf1_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf1_ch1_reg_t;
+
+/** Type of out_peri_ch1 register
+ *  Priority register of TX channel 1
+ */
+typedef union {
+    struct {
+        /** tx_pri_ch1 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of TX channel 1.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t tx_pri_ch1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_ch1_reg_t;
+
+/** Type of out_peri_sel_ch1 register
+ *  Peripheral selection register of TX channel 1
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_ch1 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to TX channel 1.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_out_sel_ch1:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_sel_ch1_reg_t;
+
+/** Type of in_conf0_ch2 register
+ *  Configuration register 0 of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_rst_ch2 : R/W; bitpos: [0]; default: 0;
+         *  Write 1 and then 0 to reset AHB_DMA channel 2 RX FSM and RX FIFO pointer.
+         */
+        uint32_t in_rst_ch2:1;
+        /** in_loop_test_ch2 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_ch2:1;
+        /** indscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable INCR burst transfer for RX channel 2 to read
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t indscr_burst_en_ch2:1;
+        /** in_data_burst_en_ch2 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 2 receiving data
+         *  when accessing internal SRAM.
+         */
+        uint32_t in_data_burst_en_ch2:1;
+        /** mem_trans_en_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable memory-to-memory data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t mem_trans_en_ch2:1;
+        /** in_etm_en_ch2 : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable ETM control for RX channel2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_etm_en_ch2:1;
+        /** in_data_burst_mode_sel_ch2 : R/W; bitpos: [7:6]; default: 1;
+         *  Configures max burst size for Rx channel2.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t in_data_burst_mode_sel_ch2:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_conf0_ch2_reg_t;
+
+/** Type of in_conf1_ch2 register
+ *  Configuration register 1 of RX channel 2
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** in_check_owner_ch2 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for RX channel 2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_check_owner_ch2:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_conf1_ch2_reg_t;
+
+/** Type of infifo_status_ch2 register
+ *  Receive FIFO status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** infifo_full_ch2 : RO; bitpos: [0]; default: 1;
+         *  Represents whether L1 RX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t infifo_full_ch2:1;
+        /** infifo_empty_ch2 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 RX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t infifo_empty_ch2:1;
+        uint32_t reserved_2:6;
+        /** infifo_cnt_ch2 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 RX FIFO for RX channel 2
+         */
+        uint32_t infifo_cnt_ch2:7;
+        uint32_t reserved_15:8;
+        /** in_remain_under_1b_ch2 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_ch2:1;
+        /** in_remain_under_2b_ch2 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_ch2:1;
+        /** in_remain_under_3b_ch2 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_ch2:1;
+        /** in_remain_under_4b_ch2 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_ch2:1;
+        /** in_buf_hungry_ch2 : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_ch2:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ahb_dma_infifo_status_ch2_reg_t;
+
+/** Type of in_pop_ch2 register
+ *  Receive FIFO status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch2 : RO; bitpos: [11:0]; default: 2048;
+         *  Represents the data popped from AHB_DMA FIFO.
+         */
+        uint32_t infifo_rdata_ch2:12;
+        /** infifo_pop_ch2 : WT; bitpos: [12]; default: 0;
+         *  Configures whether to pop data from AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Pop
+         */
+        uint32_t infifo_pop_ch2:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_pop_ch2_reg_t;
+
+/** Type of in_link_ch2 register
+ *  Receive FIFO status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_ch2 : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to return to current receive descriptor's address when there are
+         *  some errors in current receiving data.
+         *  0: Not return
+         *  1: Return
+         *  .
+         */
+        uint32_t inlink_auto_ret_ch2:1;
+        /** inlink_stop_ch2 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to stop AHB_DMA's RX channel 2 from receiving data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t inlink_stop_ch2:1;
+        /** inlink_start_ch2 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to enable AHB_DMA's RX channel 2 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t inlink_start_ch2:1;
+        /** inlink_restart_ch2 : WT; bitpos: [3]; default: 0;
+         *  Configures whether to restart RX channel 2 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t inlink_restart_ch2:1;
+        /** inlink_park_ch2 : RO; bitpos: [4]; default: 1;
+         *  Represents the status of the receive descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t inlink_park_ch2:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} ahb_dma_in_link_ch2_reg_t;
+
+/** Type of in_state_ch2 register
+ *  Receive status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0;
+         *  reserved
+         */
+        uint32_t inlink_dscr_addr_ch2:18;
+        /** in_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_ch2:2;
+        /** in_state_ch2 : RO; bitpos: [22:20]; default: 0;
+         *  Represents the address of the lower 18 bits of the next receive descriptor to be
+         *  processed.
+         */
+        uint32_t in_state_ch2:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_in_state_ch2_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch2 register
+ *  Receive descriptor address when EOF occurs on RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_suc_eof_des_addr_ch2_reg_t;
+
+/** Type of in_err_eof_des_addr_ch2 register
+ *  Receive descriptor address when errors occur of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when there are some errors in the
+         *  currently received data.
+         */
+        uint32_t in_err_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_err_eof_des_addr_ch2_reg_t;
+
+/** Type of in_dscr_ch2 register
+ *  Current receive descriptor address of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next receive descriptor x+1 pointed by the current
+         *  receive descriptor that has already been fetched.
+         */
+        uint32_t inlink_dscr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_ch2_reg_t;
+
+/** Type of in_dscr_bf0_ch2 register
+ *  The last receive descriptor address of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current receive descriptor x that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf0_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf0_ch2_reg_t;
+
+/** Type of in_dscr_bf1_ch2 register
+ *  The second-to-last receive descriptor address of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous receive descriptor x-1 that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf1_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf1_ch2_reg_t;
+
+/** Type of in_peri_ch2 register
+ *  Priority register of RX channel 2
+ */
+typedef union {
+    struct {
+        /** rx_pri_ch2 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of RX channel 2.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t rx_pri_ch2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_ch2_reg_t;
+
+/** Type of in_peri_sel_ch2 register
+ *  Peripheral selection register of RX channel 2
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_ch2 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to RX channel 2.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_in_sel_ch2:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_sel_ch2_reg_t;
+
+/** Type of out_conf0_ch2 register
+ *  Configuration register 0 of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_rst_ch2 : R/W; bitpos: [0]; default: 0;
+         *  Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer.
+         *  0: Release reset
+         *  1: Reset
+         */
+        uint32_t out_rst_ch2:1;
+        /** out_loop_test_ch2 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch2:1;
+        /** out_auto_wrback_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable automatic outlink write-back when all the data in TX
+         *  FIFO has been transmitted.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_auto_wrback_ch2:1;
+        /** out_eof_mode_ch2 : R/W; bitpos: [3]; default: 1;
+         *  Configures when to generate EOF flag.
+         *  0: EOF flag for TX channel 2 is generated when data to be transmitted has been
+         *  pushed into FIFO in AHB_DMA.
+         *  1: EOF flag for TX channel 2 is generated when data to be transmitted has been
+         *  popped from FIFO in AHB_DMA.
+         */
+        uint32_t out_eof_mode_ch2:1;
+        /** outdscr_burst_en_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable INCR burst transfer for TX channel 2 reading
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outdscr_burst_en_ch2:1;
+        /** out_data_burst_en_ch2 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data
+         *  when accessing internal SRAM.
+         */
+        uint32_t out_data_burst_en_ch2:1;
+        /** out_etm_en_ch2 : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to enable ETM control for TX channel 2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_etm_en_ch2:1;
+        uint32_t reserved_7:1;
+        /** out_data_burst_mode_sel_ch2 : R/W; bitpos: [9:8]; default: 1;
+         *  Configures max burst size for TX channel2.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t out_data_burst_mode_sel_ch2:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_conf0_ch2_reg_t;
+
+/** Type of out_conf1_ch2 register
+ *  Configuration register 1 of TX channel 2
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** out_check_owner_ch2 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for TX channel 2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_check_owner_ch2:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_out_conf1_ch2_reg_t;
+
+/** Type of outfifo_status_ch2 register
+ *  Receive FIFO status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** outfifo_full_ch2 : RO; bitpos: [0]; default: 0;
+         *  Represents whether L1 TX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t outfifo_full_ch2:1;
+        /** outfifo_empty_ch2 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 TX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t outfifo_empty_ch2:1;
+        uint32_t reserved_2:6;
+        /** outfifo_cnt_ch2 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 TX FIFO for TX channel 2
+         */
+        uint32_t outfifo_cnt_ch2:7;
+        uint32_t reserved_15:8;
+        /** out_remain_under_1b_ch2 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_ch2:1;
+        /** out_remain_under_2b_ch2 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_ch2:1;
+        /** out_remain_under_3b_ch2 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_ch2:1;
+        /** out_remain_under_4b_ch2 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_ch2:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} ahb_dma_outfifo_status_ch2_reg_t;
+
+/** Type of out_push_ch2 register
+ *  Push control register of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch2 : R/W; bitpos: [8:0]; default: 0;
+         *  Configures whether to push data into AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Push
+         */
+        uint32_t outfifo_wdata_ch2:9;
+        /** outfifo_push_ch2 : WT; bitpos: [9]; default: 0;
+         *  Configures the data that need to be pushed into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_push_ch2:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_push_ch2_reg_t;
+
+/** Type of out_link_ch2 register
+ *  Push control register of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_stop_ch2 : WT; bitpos: [0]; default: 0;
+         *  Configures whether to stop AHB_DMA's TX channel 2 from transmitting data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t outlink_stop_ch2:1;
+        /** outlink_start_ch2 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to enable AHB_DMA's TX channel 2 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outlink_start_ch2:1;
+        /** outlink_restart_ch2 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to restart TX channel 2 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t outlink_restart_ch2:1;
+        /** outlink_park_ch2 : RO; bitpos: [3]; default: 1;
+         *  Represents the status of the transmit descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t outlink_park_ch2:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_link_ch2_reg_t;
+
+/** Type of out_state_ch2 register
+ *  Transmit status of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0;
+         *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+         *  processed.
+         */
+        uint32_t outlink_dscr_addr_ch2:18;
+        /** out_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_ch2:2;
+        /** out_state_ch2 : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_ch2:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_out_state_ch2_reg_t;
+
+/** Type of out_eof_des_addr_ch2 register
+ *  Transmit descriptor address when EOF occurs on TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_des_addr_ch2_reg_t;
+
+/** Type of out_eof_bfr_des_addr_ch2 register
+ *  The last transmit descriptor address when EOF occurs on TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor before the last transmit
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_bfr_des_addr_ch2_reg_t;
+
+/** Type of out_dscr_ch2 register
+ *  Current transmit descriptor address of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next transmit descriptor y+1 pointed by the current
+         *  transmit descriptor that has already been fetched.
+         */
+        uint32_t outlink_dscr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_ch2_reg_t;
+
+/** Type of out_dscr_bf0_ch2 register
+ *  The last transmit descriptor address of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current transmit descriptor y that has already been
+         *  fetched.
+         */
+        uint32_t outlink_dscr_bf0_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf0_ch2_reg_t;
+
+/** Type of out_dscr_bf1_ch2 register
+ *  The second-to-last transmit descriptor address of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous transmit descriptor y-1 that has already
+         *  been fetched.
+         */
+        uint32_t outlink_dscr_bf1_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf1_ch2_reg_t;
+
+/** Type of out_peri_ch2 register
+ *  Priority register of TX channel 2
+ */
+typedef union {
+    struct {
+        /** tx_pri_ch2 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of TX channel 2.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t tx_pri_ch2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_ch2_reg_t;
+
+/** Type of out_peri_sel_ch2 register
+ *  Peripheral selection register of TX channel 2
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_ch2 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to TX channel 2.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_out_sel_ch2:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_sel_ch2_reg_t;
+
+/** Type of tx_ch_arb_weight_ch0 register
+ *  TX channel 0 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of TX channel0
+         */
+        uint32_t tx_arb_weight_value_ch0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_tx_ch_arb_weight_ch0_reg_t;
+
+/** Type of tx_arb_weight_opt_dir_ch0 register
+ *  TX channel 0 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_arb_weight_opt_dis_ch0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t;
+
+/** Type of tx_ch_arb_weight_ch1 register
+ *  TX channel 1 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of TX channel1
+         */
+        uint32_t tx_arb_weight_value_ch1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_tx_ch_arb_weight_ch1_reg_t;
+
+/** Type of tx_arb_weight_opt_dir_ch1 register
+ *  TX channel 1 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_arb_weight_opt_dis_ch1:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t;
+
+/** Type of tx_ch_arb_weight_ch2 register
+ *  TX channel 2 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_value_ch2 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of TX channel2
+         */
+        uint32_t tx_arb_weight_value_ch2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_tx_ch_arb_weight_ch2_reg_t;
+
+/** Type of tx_arb_weight_opt_dir_ch2 register
+ *  TX channel 2 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_opt_dis_ch2 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_arb_weight_opt_dis_ch2:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_tx_arb_weight_opt_dir_ch2_reg_t;
+
+/** Type of rx_ch_arb_weight_ch0 register
+ *  RX channel 0 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of RX channel0
+         */
+        uint32_t rx_arb_weight_value_ch0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_rx_ch_arb_weight_ch0_reg_t;
+
+/** Type of rx_arb_weight_opt_dir_ch0 register
+ *  RX channel 0 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_arb_weight_opt_dis_ch0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t;
+
+/** Type of rx_ch_arb_weight_ch1 register
+ *  RX channel 1 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of RX channel1
+         */
+        uint32_t rx_arb_weight_value_ch1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_rx_ch_arb_weight_ch1_reg_t;
+
+/** Type of rx_arb_weight_opt_dir_ch1 register
+ *  RX channel 1 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_arb_weight_opt_dis_ch1:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t;
+
+/** Type of in_link_addr_ch0 register
+ *  Link list descriptor address configuration of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address
+         */
+        uint32_t inlink_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_link_addr_ch0_reg_t;
+
+/** Type of in_link_addr_ch1 register
+ *  Link list descriptor address configuration of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address
+         */
+        uint32_t inlink_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_link_addr_ch1_reg_t;
+
+/** Type of in_link_addr_ch2 register
+ *  Link list descriptor address configuration of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address
+         */
+        uint32_t inlink_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_link_addr_ch2_reg_t;
+
+/** Type of out_link_addr_ch0 register
+ *  Link list descriptor address configuration of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address.
+         */
+        uint32_t outlink_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_link_addr_ch0_reg_t;
+
+/** Type of out_link_addr_ch1 register
+ *  Link list descriptor address configuration of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address.
+         */
+        uint32_t outlink_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_link_addr_ch1_reg_t;
+
+/** Type of out_link_addr_ch2 register
+ *  Link list descriptor address configuration of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address.
+         */
+        uint32_t outlink_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_link_addr_ch2_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  Accessible address space start address configuration register
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Accessible address space start address configuration register
+         */
+        uint32_t access_intr_mem_start_addr:32;
+    };
+    uint32_t val;
+} ahb_dma_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  Accessible address space end address configuration register
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the end address of accessible address space.
+         */
+        uint32_t access_intr_mem_end_addr:32;
+    };
+    uint32_t val;
+} ahb_dma_intr_mem_end_addr_reg_t;
+
+/** Type of arb_timeout register
+ *  TX arbitration timeout configuration register
+ */
+typedef union {
+    struct {
+        /** arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the time slot. Measurement unit: AHB bus clock cycle.
+         */
+        uint32_t arb_timeout_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_reg_t;
+
+/** Type of weight_en register
+ *  TX weight arbitration enable register
+ */
+typedef union {
+    struct {
+        /** weight_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable weight arbitration.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t weight_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_reg_t;
+
+/** Type of module_clk_en register
+ *  Module clock force on register
+ */
+typedef union {
+    struct {
+        /** ahb_apb_sync_clk_en : R/W; bitpos: [2:0]; default: 7;
+         *  Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n:
+         *  0 : Not force on ahb_apb_sync n clock
+         *  1 : Force on ahb_apb_sync n clock
+         */
+        uint32_t ahb_apb_sync_clk_en:3;
+        /** out_dscr_clk_en : R/W; bitpos: [5:3]; default: 7;
+         *  Configures whether to force on out_dscr 2~0 module clock. For bit n:
+         *  0 : Not force on out_dscr n clock
+         *  1 : Force on out_dscr n clock
+         */
+        uint32_t out_dscr_clk_en:3;
+        /** out_ctrl_clk_en : R/W; bitpos: [8:6]; default: 7;
+         *  Configures whether to force on out_ctrl 2~0 module clock. For bit n:
+         *  0 : Not force on out_ctrl n clock
+         *  1 : Force on out_ctrl n clock
+         */
+        uint32_t out_ctrl_clk_en:3;
+        /** in_dscr_clk_en : R/W; bitpos: [11:9]; default: 7;
+         *  Configures whether to force on in_dscr 2~0 module clock. For bit n:
+         *  0 : Not force on in_dscr n clock
+         *  1 : Force on in_dscr n clock
+         */
+        uint32_t in_dscr_clk_en:3;
+        /** in_ctrl_clk_en : R/W; bitpos: [14:12]; default: 7;
+         *  Configures whether to force on in_ctrl 2~0 module clock. For bit n:
+         *  0 : Not force on in_ctrl n clock
+         *  1 : Force on in_ctrl n clock
+         */
+        uint32_t in_ctrl_clk_en:3;
+        uint32_t reserved_15:12;
+        /** cmd_arb_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether to force on cmd_arb module clock.
+         *  0 : Not force on cmd_arb clock
+         *  1 : Force on cmd_arb clock
+         */
+        uint32_t cmd_arb_clk_en:1;
+        /** ahbinf_clk_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether to force on ahbinf module clock.
+         *  0 : Not force on ahbinf clock
+         *  1 : Force on ahbinf clock
+         */
+        uint32_t ahbinf_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} ahb_dma_module_clk_en_reg_t;
+
+/** Type of ahbinf_resp_err_status0 register
+ *  AHB response error status 0 register
+ */
+typedef union {
+    struct {
+        /** ahbinf_resp_err_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the AHB response error.
+         */
+        uint32_t ahbinf_resp_err_addr:32;
+    };
+    uint32_t val;
+} ahb_dma_ahbinf_resp_err_status0_reg_t;
+
+/** Type of ahbinf_resp_err_status1 register
+ *  AHB response error status 1 register
+ */
+typedef union {
+    struct {
+        /** ahbinf_resp_err_wr : RO; bitpos: [0]; default: 0;
+         *  Represents the AHB response error is write request.
+         */
+        uint32_t ahbinf_resp_err_wr:1;
+        /** ahbinf_resp_err_id : RO; bitpos: [4:1]; default: 15;
+         *  Represents the AHB response error request id.
+         */
+        uint32_t ahbinf_resp_err_id:4;
+        /** ahbinf_resp_err_ch_id : RO; bitpos: [7:5]; default: 0;
+         *  Represents the AHB response error request channel id.bit[2]=1:TX channel.
+         *  bit[2]=0:RX channel.
+         */
+        uint32_t ahbinf_resp_err_ch_id:3;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_ahbinf_resp_err_status1_reg_t;
+
+/** Type of in_done_des_addr_ch0 register
+ *  RX_done Inlink descriptor address of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the inlink descriptor when  this descriptor is completed .
+         */
+        uint32_t in_done_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_done_des_addr_ch0_reg_t;
+
+/** Type of out_done_des_addr_ch0 register
+ *  TX done outlink descriptor address of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the outlink descriptor when this descriptor is completed.
+         */
+        uint32_t out_done_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_done_des_addr_ch0_reg_t;
+
+/** Type of in_done_des_addr_ch1 register
+ *  RX_done Inlink descriptor address of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the inlink descriptor when  this descriptor is completed .
+         */
+        uint32_t in_done_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_done_des_addr_ch1_reg_t;
+
+/** Type of out_done_des_addr_ch1 register
+ *  TX done outlink descriptor address of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the outlink descriptor when this descriptor is completed.
+         */
+        uint32_t out_done_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_done_des_addr_ch1_reg_t;
+
+/** Type of in_done_des_addr_ch2 register
+ *  RX_done Inlink descriptor address of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_done_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the inlink descriptor when  this descriptor is completed .
+         */
+        uint32_t in_done_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_done_des_addr_ch2_reg_t;
+
+/** Type of out_done_des_addr_ch2 register
+ *  TX done outlink descriptor address of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_done_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the outlink descriptor when this descriptor is completed.
+         */
+        uint32_t out_done_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_done_des_addr_ch2_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of out_crc_init_data_chn register
+ *  This register is used to config chn crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of tx crc initial value
+         */
+        uint32_t out_crc_init_data_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_init_data_chn_reg_t;
+
+/** Type of tx_crc_width_chn register
+ *  This register is used to confiig tx chn crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_width_chn:2;
+        /** tx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_lautch_flga_chn:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_width_chn_reg_t;
+
+/** Type of out_crc_clear_chn register
+ *  This register is used to clear chn crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of tx crc result
+         */
+        uint32_t out_crc_clear_chn_reg:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_clear_chn_reg_t;
+
+/** Type of out_crc_final_result_chn register
+ *  This register is used to store chn crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of tx
+         */
+        uint32_t out_crc_final_result_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_final_result_chn_reg_t;
+
+/** Type of tx_crc_en_wr_data_chn register
+ *  This resister is used to config chn crc en for every bit
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable tx ch0 crc 32bit on/off
+         */
+        uint32_t tx_crc_en_wr_data_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_en_addr_chn register
+ *  This register is used to config chn crc en addr
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_en_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_en_addr_chn_reg_t;
+
+/** Type of tx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_wr_data_chn:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_data_en_addr_chn_reg_t;
+
+/** Type of in_crc_init_data_chn register
+ *  This register is used to config chn crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of rx crc initial value
+         */
+        uint32_t in_crc_init_data_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_init_data_chn_reg_t;
+
+/** Type of rx_crc_width_chn register
+ *  This register is used to confiig rx chn crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_width_chn:2;
+        /** rx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_lautch_flga_chn:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_width_chn_reg_t;
+
+/** Type of in_crc_clear_chn register
+ *  This register is used to clear chn crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of rx crc result
+         */
+        uint32_t in_crc_clear_chn_reg:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_clear_chn_reg_t;
+
+/** Type of in_crc_final_result_chn register
+ *  This register is used to store chn crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of rx
+         */
+        uint32_t in_crc_final_result_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_final_result_chn_reg_t;
+
+/** Type of rx_crc_en_wr_data_chn register
+ *  This resister is used to config chn crc en for every bit
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable rx ch0 crc 32bit on/off
+         */
+        uint32_t rx_crc_en_wr_data_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_en_addr_chn register
+ *  This register is used to config chn crc en addr
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_en_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_en_addr_chn_reg_t;
+
+/** Type of rx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_wr_data_chn:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_data_en_addr_chn_reg_t;
+
+/** Type of rx_ch_arb_weigh_chn register
+ *  RX channel 2 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of RX channeln
+         */
+        uint32_t rx_ch_arb_weigh_chn:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_rx_ch_arb_weigh_chn_reg_t;
+
+/** Type of rx_arb_weigh_opt_dir_chn register
+ *  RX channel 2 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_arb_weigh_opt_dir_chn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t;
+
+/** Type of arb_timeout_tx register
+ *  TX arbitration timeout configuration register
+ */
+typedef union {
+    struct {
+        /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the time slot for TX. Measurement unit: AHB bus clock cycle.
+         */
+        uint32_t arb_timeout_tx:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_tx_reg_t;
+
+/** Type of arb_timeout_rx register
+ *  RX arbitration timeout configuration register
+ */
+typedef union {
+    struct {
+        /** arb_timeout_rx : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the time slot for RX. Measurement unit: AHB bus clock cycle.
+         */
+        uint32_t arb_timeout_rx:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_rx_reg_t;
+
+/** Type of weight_en_tx register
+ *  TX weight arbitration enable register
+ */
+typedef union {
+    struct {
+        /** weight_en_tx : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable weight arbitration for TX.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t weight_en_tx:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_tx_reg_t;
+
+/** Type of weight_en_rx register
+ *  RX weight arbitration enable register
+ */
+typedef union {
+    struct {
+        /** weight_en_rx : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable weight arbitration for RX.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t weight_en_rx:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_rx_reg_t;
+
+
+typedef struct {
+    volatile ahb_dma_in_int_raw_ch0_reg_t in_int_raw_ch0;
+    volatile ahb_dma_in_int_st_ch0_reg_t in_int_st_ch0;
+    volatile ahb_dma_in_int_ena_ch0_reg_t in_int_ena_ch0;
+    volatile ahb_dma_in_int_clr_ch0_reg_t in_int_clr_ch0;
+    volatile ahb_dma_in_int_raw_ch1_reg_t in_int_raw_ch1;
+    volatile ahb_dma_in_int_st_ch1_reg_t in_int_st_ch1;
+    volatile ahb_dma_in_int_ena_ch1_reg_t in_int_ena_ch1;
+    volatile ahb_dma_in_int_clr_ch1_reg_t in_int_clr_ch1;
+    volatile ahb_dma_in_int_raw_ch2_reg_t in_int_raw_ch2;
+    volatile ahb_dma_in_int_st_ch2_reg_t in_int_st_ch2;
+    volatile ahb_dma_in_int_ena_ch2_reg_t in_int_ena_ch2;
+    volatile ahb_dma_in_int_clr_ch2_reg_t in_int_clr_ch2;
+    volatile ahb_dma_out_int_raw_ch0_reg_t out_int_raw_ch0;
+    volatile ahb_dma_out_int_st_ch0_reg_t out_int_st_ch0;
+    volatile ahb_dma_out_int_ena_ch0_reg_t out_int_ena_ch0;
+    volatile ahb_dma_out_int_clr_ch0_reg_t out_int_clr_ch0;
+    volatile ahb_dma_out_int_raw_ch1_reg_t out_int_raw_ch1;
+    volatile ahb_dma_out_int_st_ch1_reg_t out_int_st_ch1;
+    volatile ahb_dma_out_int_ena_ch1_reg_t out_int_ena_ch1;
+    volatile ahb_dma_out_int_clr_ch1_reg_t out_int_clr_ch1;
+    volatile ahb_dma_out_int_raw_ch2_reg_t out_int_raw_ch2;
+    volatile ahb_dma_out_int_st_ch2_reg_t out_int_st_ch2;
+    volatile ahb_dma_out_int_ena_ch2_reg_t out_int_ena_ch2;
+    volatile ahb_dma_out_int_clr_ch2_reg_t out_int_clr_ch2;
+    volatile ahb_dma_ahb_test_reg_t ahb_test;
+    volatile ahb_dma_misc_conf_reg_t misc_conf;
+    volatile ahb_dma_date_reg_t date;
+    uint32_t reserved_06c;
+    volatile ahb_dma_in_conf0_ch0_reg_t in_conf0_ch0;
+    volatile ahb_dma_in_conf1_ch0_reg_t in_conf1_ch0;
+    volatile ahb_dma_infifo_status_ch0_reg_t infifo_status_ch0;
+    volatile ahb_dma_in_pop_ch0_reg_t in_pop_ch0;
+    volatile ahb_dma_in_link_ch0_reg_t in_link_ch0;
+    volatile ahb_dma_in_state_ch0_reg_t in_state_ch0;
+    volatile ahb_dma_in_suc_eof_des_addr_ch0_reg_t in_suc_eof_des_addr_ch0;
+    volatile ahb_dma_in_err_eof_des_addr_ch0_reg_t in_err_eof_des_addr_ch0;
+    volatile ahb_dma_in_dscr_ch0_reg_t in_dscr_ch0;
+    volatile ahb_dma_in_dscr_bf0_ch0_reg_t in_dscr_bf0_ch0;
+    volatile ahb_dma_in_dscr_bf1_ch0_reg_t in_dscr_bf1_ch0;
+    volatile ahb_dma_in_peri_ch0_reg_t in_peri_ch0;
+    volatile ahb_dma_in_peri_sel_ch0_reg_t in_peri_sel_ch0;
+    uint32_t reserved_0a4[11];
+    volatile ahb_dma_out_conf0_ch0_reg_t out_conf0_ch0;
+    volatile ahb_dma_out_conf1_ch0_reg_t out_conf1_ch0;
+    volatile ahb_dma_outfifo_status_ch0_reg_t outfifo_status_ch0;
+    volatile ahb_dma_out_push_ch0_reg_t out_push_ch0;
+    volatile ahb_dma_out_link_ch0_reg_t out_link_ch0;
+    volatile ahb_dma_out_state_ch0_reg_t out_state_ch0;
+    volatile ahb_dma_out_eof_des_addr_ch0_reg_t out_eof_des_addr_ch0;
+    volatile ahb_dma_out_eof_bfr_des_addr_ch0_reg_t out_eof_bfr_des_addr_ch0;
+    volatile ahb_dma_out_dscr_ch0_reg_t out_dscr_ch0;
+    volatile ahb_dma_out_dscr_bf0_ch0_reg_t out_dscr_bf0_ch0;
+    volatile ahb_dma_out_dscr_bf1_ch0_reg_t out_dscr_bf1_ch0;
+    volatile ahb_dma_out_peri_ch0_reg_t out_peri_ch0;
+    volatile ahb_dma_out_peri_sel_ch0_reg_t out_peri_sel_ch0;
+    uint32_t reserved_104[11];
+    volatile ahb_dma_in_conf0_ch1_reg_t in_conf0_ch1;
+    volatile ahb_dma_in_conf1_ch1_reg_t in_conf1_ch1;
+    volatile ahb_dma_infifo_status_ch1_reg_t infifo_status_ch1;
+    volatile ahb_dma_in_pop_ch1_reg_t in_pop_ch1;
+    volatile ahb_dma_in_link_ch1_reg_t in_link_ch1;
+    volatile ahb_dma_in_state_ch1_reg_t in_state_ch1;
+    volatile ahb_dma_in_suc_eof_des_addr_ch1_reg_t in_suc_eof_des_addr_ch1;
+    volatile ahb_dma_in_err_eof_des_addr_ch1_reg_t in_err_eof_des_addr_ch1;
+    volatile ahb_dma_in_dscr_ch1_reg_t in_dscr_ch1;
+    volatile ahb_dma_in_dscr_bf0_ch1_reg_t in_dscr_bf0_ch1;
+    volatile ahb_dma_in_dscr_bf1_ch1_reg_t in_dscr_bf1_ch1;
+    volatile ahb_dma_in_peri_ch1_reg_t in_peri_ch1;
+    volatile ahb_dma_in_peri_sel_ch1_reg_t in_peri_sel_ch1;
+    uint32_t reserved_164[11];
+    volatile ahb_dma_out_conf0_ch1_reg_t out_conf0_ch1;
+    volatile ahb_dma_out_conf1_ch1_reg_t out_conf1_ch1;
+    volatile ahb_dma_outfifo_status_ch1_reg_t outfifo_status_ch1;
+    volatile ahb_dma_out_push_ch1_reg_t out_push_ch1;
+    volatile ahb_dma_out_link_ch1_reg_t out_link_ch1;
+    volatile ahb_dma_out_state_ch1_reg_t out_state_ch1;
+    volatile ahb_dma_out_eof_des_addr_ch1_reg_t out_eof_des_addr_ch1;
+    volatile ahb_dma_out_eof_bfr_des_addr_ch1_reg_t out_eof_bfr_des_addr_ch1;
+    volatile ahb_dma_out_dscr_ch1_reg_t out_dscr_ch1;
+    volatile ahb_dma_out_dscr_bf0_ch1_reg_t out_dscr_bf0_ch1;
+    volatile ahb_dma_out_dscr_bf1_ch1_reg_t out_dscr_bf1_ch1;
+    volatile ahb_dma_out_peri_ch1_reg_t out_peri_ch1;
+    volatile ahb_dma_out_peri_sel_ch1_reg_t out_peri_sel_ch1;
+    uint32_t reserved_1c4[11];
+    volatile ahb_dma_in_conf0_ch2_reg_t in_conf0_ch2;
+    volatile ahb_dma_in_conf1_ch2_reg_t in_conf1_ch2;
+    volatile ahb_dma_infifo_status_ch2_reg_t infifo_status_ch2;
+    volatile ahb_dma_in_pop_ch2_reg_t in_pop_ch2;
+    volatile ahb_dma_in_link_ch2_reg_t in_link_ch2;
+    volatile ahb_dma_in_state_ch2_reg_t in_state_ch2;
+    volatile ahb_dma_in_suc_eof_des_addr_ch2_reg_t in_suc_eof_des_addr_ch2;
+    volatile ahb_dma_in_err_eof_des_addr_ch2_reg_t in_err_eof_des_addr_ch2;
+    volatile ahb_dma_in_dscr_ch2_reg_t in_dscr_ch2;
+    volatile ahb_dma_in_dscr_bf0_ch2_reg_t in_dscr_bf0_ch2;
+    volatile ahb_dma_in_dscr_bf1_ch2_reg_t in_dscr_bf1_ch2;
+    volatile ahb_dma_in_peri_ch2_reg_t in_peri_ch2;
+    volatile ahb_dma_in_peri_sel_ch2_reg_t in_peri_sel_ch2;
+    uint32_t reserved_224[11];
+    volatile ahb_dma_out_conf0_ch2_reg_t out_conf0_ch2;
+    volatile ahb_dma_out_conf1_ch2_reg_t out_conf1_ch2;
+    volatile ahb_dma_outfifo_status_ch2_reg_t outfifo_status_ch2;
+    volatile ahb_dma_out_push_ch2_reg_t out_push_ch2;
+    volatile ahb_dma_out_link_ch2_reg_t out_link_ch2;
+    volatile ahb_dma_out_state_ch2_reg_t out_state_ch2;
+    volatile ahb_dma_out_eof_des_addr_ch2_reg_t out_eof_des_addr_ch2;
+    volatile ahb_dma_out_eof_bfr_des_addr_ch2_reg_t out_eof_bfr_des_addr_ch2;
+    volatile ahb_dma_out_dscr_ch2_reg_t out_dscr_ch2;
+    volatile ahb_dma_out_dscr_bf0_ch2_reg_t out_dscr_bf0_ch2;
+    volatile ahb_dma_out_dscr_bf1_ch2_reg_t out_dscr_bf1_ch2;
+    volatile ahb_dma_out_peri_ch2_reg_t out_peri_ch2;
+    volatile ahb_dma_out_peri_sel_ch2_reg_t out_peri_sel_ch2;
+    uint32_t reserved_284[14];
+    volatile ahb_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch0;
+    volatile ahb_dma_tx_crc_width_chn_reg_t tx_crc_width_ch0;
+    volatile ahb_dma_out_crc_clear_chn_reg_t out_crc_clear_ch0;
+    volatile ahb_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch0;
+    volatile ahb_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch0;
+    volatile ahb_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch0;
+    volatile ahb_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch0;
+    volatile ahb_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch0;
+    volatile ahb_dma_tx_ch_arb_weight_ch0_reg_t tx_ch_arb_weight_ch0;
+    volatile ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t tx_arb_weight_opt_dir_ch0;
+    volatile ahb_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch1;
+    volatile ahb_dma_tx_crc_width_chn_reg_t tx_crc_width_ch1;
+    volatile ahb_dma_out_crc_clear_chn_reg_t out_crc_clear_ch1;
+    volatile ahb_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch1;
+    volatile ahb_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch1;
+    volatile ahb_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch1;
+    volatile ahb_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch1;
+    volatile ahb_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch1;
+    volatile ahb_dma_tx_ch_arb_weight_ch1_reg_t tx_ch_arb_weight_ch1;
+    volatile ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t tx_arb_weight_opt_dir_ch1;
+    volatile ahb_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch2;
+    volatile ahb_dma_tx_crc_width_chn_reg_t tx_crc_width_ch2;
+    volatile ahb_dma_out_crc_clear_chn_reg_t out_crc_clear_ch2;
+    volatile ahb_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch2;
+    volatile ahb_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch2;
+    volatile ahb_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch2;
+    volatile ahb_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch2;
+    volatile ahb_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch2;
+    volatile ahb_dma_tx_ch_arb_weight_ch2_reg_t tx_ch_arb_weight_ch2;
+    volatile ahb_dma_tx_arb_weight_opt_dir_ch2_reg_t tx_arb_weight_opt_dir_ch2;
+    volatile ahb_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch0;
+    volatile ahb_dma_rx_crc_width_chn_reg_t rx_crc_width_ch0;
+    volatile ahb_dma_in_crc_clear_chn_reg_t in_crc_clear_ch0;
+    volatile ahb_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch0;
+    volatile ahb_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch0;
+    volatile ahb_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch0;
+    volatile ahb_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch0;
+    volatile ahb_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch0;
+    volatile ahb_dma_rx_ch_arb_weight_ch0_reg_t rx_ch_arb_weight_ch0;
+    volatile ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t rx_arb_weight_opt_dir_ch0;
+    volatile ahb_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch1;
+    volatile ahb_dma_rx_crc_width_chn_reg_t rx_crc_width_ch1;
+    volatile ahb_dma_in_crc_clear_chn_reg_t in_crc_clear_ch1;
+    volatile ahb_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch1;
+    volatile ahb_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch1;
+    volatile ahb_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch1;
+    volatile ahb_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch1;
+    volatile ahb_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch1;
+    volatile ahb_dma_rx_ch_arb_weight_ch1_reg_t rx_ch_arb_weight_ch1;
+    volatile ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t rx_arb_weight_opt_dir_ch1;
+    volatile ahb_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch2;
+    volatile ahb_dma_rx_crc_width_chn_reg_t rx_crc_width_ch2;
+    volatile ahb_dma_in_crc_clear_chn_reg_t in_crc_clear_ch2;
+    volatile ahb_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch2;
+    volatile ahb_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch2;
+    volatile ahb_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch2;
+    volatile ahb_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch2;
+    volatile ahb_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch2;
+    volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch2;
+    volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch2;
+    volatile ahb_dma_in_link_addr_ch0_reg_t in_link_addr_ch0;
+    volatile ahb_dma_in_link_addr_ch1_reg_t in_link_addr_ch1;
+    volatile ahb_dma_in_link_addr_ch2_reg_t in_link_addr_ch2;
+    volatile ahb_dma_out_link_addr_ch0_reg_t out_link_addr_ch0;
+    volatile ahb_dma_out_link_addr_ch1_reg_t out_link_addr_ch1;
+    volatile ahb_dma_out_link_addr_ch2_reg_t out_link_addr_ch2;
+    volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx;
+    volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx;
+    volatile ahb_dma_weight_en_tx_reg_t weight_en_tx;
+    volatile ahb_dma_weight_en_rx_reg_t weight_en_rx;
+    volatile ahb_dma_arb_timeout_reg_t arb_timeout;
+    uint32_t reserved_3e0[8];
+    volatile ahb_dma_weight_en_reg_t weight_en;
+    volatile ahb_dma_module_clk_en_reg_t module_clk_en;
+    volatile ahb_dma_ahbinf_resp_err_status0_reg_t ahbinf_resp_err_status0;
+    volatile ahb_dma_ahbinf_resp_err_status1_reg_t ahbinf_resp_err_status1;
+    volatile ahb_dma_in_done_des_addr_ch0_reg_t in_done_des_addr_ch0;
+    volatile ahb_dma_out_done_des_addr_ch0_reg_t out_done_des_addr_ch0;
+    volatile ahb_dma_in_done_des_addr_ch1_reg_t in_done_des_addr_ch1;
+    volatile ahb_dma_out_done_des_addr_ch1_reg_t out_done_des_addr_ch1;
+    volatile ahb_dma_in_done_des_addr_ch2_reg_t in_done_des_addr_ch2;
+    volatile ahb_dma_out_done_des_addr_ch2_reg_t out_done_des_addr_ch2;
+} ahb_dma_dev_t;
+
+extern ahb_dma_dev_t AHB_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ahb_dma_dev_t) == 0x428, "Invalid size of ahb_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_reg.h
new file mode 100644
index 0000000000..8fcba6d907
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_reg.h
@@ -0,0 +1,4654 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AHB_DMA_IN_INT_RAW_CH0_REG register
+ *  Raw interrupt status of RX channel 0
+ */
+#define AHB_DMA_IN_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x0)
+/** AHB_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_RAW_M  (AHB_DMA_IN_DONE_CH0_INT_RAW_V << AHB_DMA_IN_DONE_CH0_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH0_REG register
+ *  Masked interrupt status of RX channel 0
+ */
+#define AHB_DMA_IN_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x4)
+/** AHB_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_ST_M  (AHB_DMA_IN_DONE_CH0_INT_ST_V << AHB_DMA_IN_DONE_CH0_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH0_INT_ST_V << AHB_DMA_INFIFO_OVF_CH0_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH0_INT_ST_V << AHB_DMA_INFIFO_UDF_CH0_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of RX channel 0
+ */
+#define AHB_DMA_IN_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8)
+/** AHB_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH0_INT
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_ENA_M  (AHB_DMA_IN_DONE_CH0_INT_ENA_V << AHB_DMA_IN_DONE_CH0_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of RX channel 0
+ */
+#define AHB_DMA_IN_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xc)
+/** AHB_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH0_INT
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_CLR_M  (AHB_DMA_IN_DONE_CH0_INT_CLR_V << AHB_DMA_IN_DONE_CH0_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S  7
+
+/** AHB_DMA_IN_INT_RAW_CH1_REG register
+ *  Raw interrupt status of RX channel 1
+ */
+#define AHB_DMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x10)
+/** AHB_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_RAW_M  (AHB_DMA_IN_DONE_CH1_INT_RAW_V << AHB_DMA_IN_DONE_CH1_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH1_REG register
+ *  Masked interrupt status of RX channel 1
+ */
+#define AHB_DMA_IN_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14)
+/** AHB_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_ST_M  (AHB_DMA_IN_DONE_CH1_INT_ST_V << AHB_DMA_IN_DONE_CH1_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH1_INT_ST_V << AHB_DMA_INFIFO_OVF_CH1_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH1_INT_ST_V << AHB_DMA_INFIFO_UDF_CH1_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of RX channel 1
+ */
+#define AHB_DMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x18)
+/** AHB_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH1_INT
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_ENA_M  (AHB_DMA_IN_DONE_CH1_INT_ENA_V << AHB_DMA_IN_DONE_CH1_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of RX channel 1
+ */
+#define AHB_DMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c)
+/** AHB_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH1_INT
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_CLR_M  (AHB_DMA_IN_DONE_CH1_INT_CLR_V << AHB_DMA_IN_DONE_CH1_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S  7
+
+/** AHB_DMA_IN_INT_RAW_CH2_REG register
+ *  Raw interrupt status of RX channel 2
+ */
+#define AHB_DMA_IN_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20)
+/** AHB_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_RAW_M  (AHB_DMA_IN_DONE_CH2_INT_RAW_V << AHB_DMA_IN_DONE_CH2_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH2_REG register
+ *  Masked interrupt status of RX channel 2
+ */
+#define AHB_DMA_IN_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x24)
+/** AHB_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_ST_M  (AHB_DMA_IN_DONE_CH2_INT_ST_V << AHB_DMA_IN_DONE_CH2_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH2_INT_ST_V << AHB_DMA_INFIFO_OVF_CH2_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH2_INT_ST_V << AHB_DMA_INFIFO_UDF_CH2_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of RX channel 2
+ */
+#define AHB_DMA_IN_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x28)
+/** AHB_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH2_INT
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_ENA_M  (AHB_DMA_IN_DONE_CH2_INT_ENA_V << AHB_DMA_IN_DONE_CH2_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of RX channel 2
+ */
+#define AHB_DMA_IN_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x2c)
+/** AHB_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH2_INT
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_CLR_M  (AHB_DMA_IN_DONE_CH2_INT_CLR_V << AHB_DMA_IN_DONE_CH2_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S  7
+
+/** AHB_DMA_OUT_INT_RAW_CH0_REG register
+ *  //Raw interrupt status of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x30)
+/** AHB_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW_M  (AHB_DMA_OUT_DONE_CH0_INT_RAW_V << AHB_DMA_OUT_DONE_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW_M  (AHB_DMA_OUT_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x34)
+/** AHB_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_ST_M  (AHB_DMA_OUT_DONE_CH0_INT_ST_V << AHB_DMA_OUT_DONE_CH0_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_ST_M  (AHB_DMA_OUT_EOF_CH0_INT_ST_V << AHB_DMA_OUT_EOF_CH0_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x38)
+/** AHB_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA_M  (AHB_DMA_OUT_DONE_CH0_INT_ENA_V << AHB_DMA_OUT_DONE_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA_M  (AHB_DMA_OUT_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3c)
+/** AHB_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR_M  (AHB_DMA_OUT_DONE_CH0_INT_CLR_V << AHB_DMA_OUT_DONE_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR_M  (AHB_DMA_OUT_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S  6
+
+/** AHB_DMA_OUT_INT_RAW_CH1_REG register
+ *  //Raw interrupt status of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x40)
+/** AHB_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW_M  (AHB_DMA_OUT_DONE_CH1_INT_RAW_V << AHB_DMA_OUT_DONE_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW_M  (AHB_DMA_OUT_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt status of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x44)
+/** AHB_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_ST_M  (AHB_DMA_OUT_DONE_CH1_INT_ST_V << AHB_DMA_OUT_DONE_CH1_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_ST_M  (AHB_DMA_OUT_EOF_CH1_INT_ST_V << AHB_DMA_OUT_EOF_CH1_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x48)
+/** AHB_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA_M  (AHB_DMA_OUT_DONE_CH1_INT_ENA_V << AHB_DMA_OUT_DONE_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA_M  (AHB_DMA_OUT_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x4c)
+/** AHB_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR_M  (AHB_DMA_OUT_DONE_CH1_INT_CLR_V << AHB_DMA_OUT_DONE_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR_M  (AHB_DMA_OUT_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S  6
+
+/** AHB_DMA_OUT_INT_RAW_CH2_REG register
+ *  //Raw interrupt status of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x50)
+/** AHB_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW_M  (AHB_DMA_OUT_DONE_CH2_INT_RAW_V << AHB_DMA_OUT_DONE_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW_M  (AHB_DMA_OUT_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt status of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x54)
+/** AHB_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_ST_M  (AHB_DMA_OUT_DONE_CH2_INT_ST_V << AHB_DMA_OUT_DONE_CH2_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_ST_M  (AHB_DMA_OUT_EOF_CH2_INT_ST_V << AHB_DMA_OUT_EOF_CH2_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x58)
+/** AHB_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA_M  (AHB_DMA_OUT_DONE_CH2_INT_ENA_V << AHB_DMA_OUT_DONE_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA_M  (AHB_DMA_OUT_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x5c)
+/** AHB_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR_M  (AHB_DMA_OUT_DONE_CH2_INT_CLR_V << AHB_DMA_OUT_DONE_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR_M  (AHB_DMA_OUT_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S  6
+
+/** AHB_DMA_AHB_TEST_REG register
+ *  only for test
+ */
+#define AHB_DMA_AHB_TEST_REG (DR_REG_AHB_DMA_BASE + 0x60)
+/** AHB_DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_AHB_TESTMODE    0x00000007U
+#define AHB_DMA_AHB_TESTMODE_M  (AHB_DMA_AHB_TESTMODE_V << AHB_DMA_AHB_TESTMODE_S)
+#define AHB_DMA_AHB_TESTMODE_V  0x00000007U
+#define AHB_DMA_AHB_TESTMODE_S  0
+/** AHB_DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_AHB_TESTADDR    0x00000003U
+#define AHB_DMA_AHB_TESTADDR_M  (AHB_DMA_AHB_TESTADDR_V << AHB_DMA_AHB_TESTADDR_S)
+#define AHB_DMA_AHB_TESTADDR_V  0x00000003U
+#define AHB_DMA_AHB_TESTADDR_S  4
+
+/** AHB_DMA_MISC_CONF_REG register
+ *  reserved
+ */
+#define AHB_DMA_MISC_CONF_REG (DR_REG_AHB_DMA_BASE + 0x64)
+/** AHB_DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset the internal AHB FSM
+ */
+#define AHB_DMA_AHBM_RST_INTER    (BIT(0))
+#define AHB_DMA_AHBM_RST_INTER_M  (AHB_DMA_AHBM_RST_INTER_V << AHB_DMA_AHBM_RST_INTER_S)
+#define AHB_DMA_AHBM_RST_INTER_V  0x00000001U
+#define AHB_DMA_AHBM_RST_INTER_S  0
+/** AHB_DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to disable the fixed-priority channel arbitration.
+ *  0: Enable
+ *  1: Disable
+ */
+#define AHB_DMA_ARB_PRI_DIS    (BIT(2))
+#define AHB_DMA_ARB_PRI_DIS_M  (AHB_DMA_ARB_PRI_DIS_V << AHB_DMA_ARB_PRI_DIS_S)
+#define AHB_DMA_ARB_PRI_DIS_V  0x00000001U
+#define AHB_DMA_ARB_PRI_DIS_S  2
+/** AHB_DMA_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures clock gating.
+ *  0: Support clock only when the application writes registers.
+ *  1: Always force the clock on for registers.
+ */
+#define AHB_DMA_CLK_EN    (BIT(3))
+#define AHB_DMA_CLK_EN_M  (AHB_DMA_CLK_EN_V << AHB_DMA_CLK_EN_S)
+#define AHB_DMA_CLK_EN_V  0x00000001U
+#define AHB_DMA_CLK_EN_S  3
+
+/** AHB_DMA_DATE_REG register
+ *  Version control register
+ */
+#define AHB_DMA_DATE_REG (DR_REG_AHB_DMA_BASE + 0x68)
+/** AHB_DMA_DATE : R/W; bitpos: [31:0]; default: 2425376;
+ *  Version control register
+ */
+#define AHB_DMA_DATE    0xFFFFFFFFU
+#define AHB_DMA_DATE_M  (AHB_DMA_DATE_V << AHB_DMA_DATE_S)
+#define AHB_DMA_DATE_V  0xFFFFFFFFU
+#define AHB_DMA_DATE_S  0
+
+/** AHB_DMA_IN_CONF0_CH0_REG register
+ *  Configuration register 0 of RX channel 0
+ */
+#define AHB_DMA_IN_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x70)
+/** AHB_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH0    (BIT(0))
+#define AHB_DMA_IN_RST_CH0_M  (AHB_DMA_IN_RST_CH0_V << AHB_DMA_IN_RST_CH0_S)
+#define AHB_DMA_IN_RST_CH0_V  0x00000001U
+#define AHB_DMA_IN_RST_CH0_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH0    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH0_M  (AHB_DMA_IN_LOOP_TEST_CH0_V << AHB_DMA_IN_LOOP_TEST_CH0_S)
+#define AHB_DMA_IN_LOOP_TEST_CH0_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH0_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 0 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH0    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH0_M  (AHB_DMA_INDSCR_BURST_EN_CH0_V << AHB_DMA_INDSCR_BURST_EN_CH0_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH0_S  2
+/** AHB_DMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 0 receiving data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_IN_DATA_BURST_EN_CH0    (BIT(3))
+#define AHB_DMA_IN_DATA_BURST_EN_CH0_M  (AHB_DMA_IN_DATA_BURST_EN_CH0_V << AHB_DMA_IN_DATA_BURST_EN_CH0_S)
+#define AHB_DMA_IN_DATA_BURST_EN_CH0_V  0x00000001U
+#define AHB_DMA_IN_DATA_BURST_EN_CH0_S  3
+/** AHB_DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH0    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH0_M  (AHB_DMA_MEM_TRANS_EN_CH0_V << AHB_DMA_MEM_TRANS_EN_CH0_S)
+#define AHB_DMA_MEM_TRANS_EN_CH0_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH0_S  4
+/** AHB_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH0    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH0_M  (AHB_DMA_IN_ETM_EN_CH0_V << AHB_DMA_IN_ETM_EN_CH0_S)
+#define AHB_DMA_IN_ETM_EN_CH0_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH0_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 1;
+ *  Configures max burst size for Rx channel0.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S  6
+
+/** AHB_DMA_IN_CONF1_CH0_REG register
+ *  Configuration register 1 of RX channel 0
+ */
+#define AHB_DMA_IN_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x74)
+/** AHB_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH0    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH0_M  (AHB_DMA_IN_CHECK_OWNER_CH0_V << AHB_DMA_IN_CHECK_OWNER_CH0_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH0_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH0_REG register
+ *  Receive FIFO status of RX channel 0
+ */
+#define AHB_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x78)
+/** AHB_DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH0    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH0_M  (AHB_DMA_INFIFO_FULL_CH0_V << AHB_DMA_INFIFO_FULL_CH0_S)
+#define AHB_DMA_INFIFO_FULL_CH0_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH0_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH0    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH0_M  (AHB_DMA_INFIFO_EMPTY_CH0_V << AHB_DMA_INFIFO_EMPTY_CH0_S)
+#define AHB_DMA_INFIFO_EMPTY_CH0_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH0_S  1
+/** AHB_DMA_INFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 0
+ */
+#define AHB_DMA_INFIFO_CNT_CH0    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH0_M  (AHB_DMA_INFIFO_CNT_CH0_V << AHB_DMA_INFIFO_CNT_CH0_S)
+#define AHB_DMA_INFIFO_CNT_CH0_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH0_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH0    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH0_M  (AHB_DMA_IN_BUF_HUNGRY_CH0_V << AHB_DMA_IN_BUF_HUNGRY_CH0_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH0_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH0_S  27
+
+/** AHB_DMA_IN_POP_CH0_REG register
+ *  Receive FIFO status of RX channel 0
+ */
+#define AHB_DMA_IN_POP_CH0_REG (DR_REG_AHB_DMA_BASE + 0x7c)
+/** AHB_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH0    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH0_M  (AHB_DMA_INFIFO_RDATA_CH0_V << AHB_DMA_INFIFO_RDATA_CH0_S)
+#define AHB_DMA_INFIFO_RDATA_CH0_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH0_S  0
+/** AHB_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH0    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH0_M  (AHB_DMA_INFIFO_POP_CH0_V << AHB_DMA_INFIFO_POP_CH0_S)
+#define AHB_DMA_INFIFO_POP_CH0_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH0_S  12
+
+/** AHB_DMA_IN_LINK_CH0_REG register
+ *  Receive FIFO status of RX channel 0
+ */
+#define AHB_DMA_IN_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0x80)
+/** AHB_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ *  .
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH0    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH0_M  (AHB_DMA_INLINK_AUTO_RET_CH0_V << AHB_DMA_INLINK_AUTO_RET_CH0_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH0_S  0
+/** AHB_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 0 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH0    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH0_M  (AHB_DMA_INLINK_STOP_CH0_V << AHB_DMA_INLINK_STOP_CH0_S)
+#define AHB_DMA_INLINK_STOP_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH0_S  1
+/** AHB_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 0 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH0    (BIT(2))
+#define AHB_DMA_INLINK_START_CH0_M  (AHB_DMA_INLINK_START_CH0_V << AHB_DMA_INLINK_START_CH0_S)
+#define AHB_DMA_INLINK_START_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH0_S  2
+/** AHB_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 0 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH0    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH0_M  (AHB_DMA_INLINK_RESTART_CH0_V << AHB_DMA_INLINK_RESTART_CH0_S)
+#define AHB_DMA_INLINK_RESTART_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH0_S  3
+/** AHB_DMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH0    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH0_M  (AHB_DMA_INLINK_PARK_CH0_V << AHB_DMA_INLINK_PARK_CH0_S)
+#define AHB_DMA_INLINK_PARK_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH0_S  4
+
+/** AHB_DMA_IN_STATE_CH0_REG register
+ *  Receive status of RX channel 0
+ */
+#define AHB_DMA_IN_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0x84)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0_M  (AHB_DMA_INLINK_DSCR_ADDR_CH0_V << AHB_DMA_INLINK_DSCR_ADDR_CH0_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH0    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH0_M  (AHB_DMA_IN_DSCR_STATE_CH0_V << AHB_DMA_IN_DSCR_STATE_CH0_S)
+#define AHB_DMA_IN_DSCR_STATE_CH0_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH0_S  18
+/** AHB_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_IN_STATE_CH0    0x00000007U
+#define AHB_DMA_IN_STATE_CH0_M  (AHB_DMA_IN_STATE_CH0_V << AHB_DMA_IN_STATE_CH0_S)
+#define AHB_DMA_IN_STATE_CH0_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH0_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 0
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x88)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Receive descriptor address when errors occur of RX channel 0
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8c)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_DSCR_CH0_REG register
+ *  Current receive descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x90)
+/** AHB_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH0_M  (AHB_DMA_INLINK_DSCR_CH0_V << AHB_DMA_INLINK_DSCR_CH0_S)
+#define AHB_DMA_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH0_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH0_REG register
+ *  The last receive descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x94)
+/** AHB_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH0_M  (AHB_DMA_INLINK_DSCR_BF0_CH0_V << AHB_DMA_INLINK_DSCR_BF0_CH0_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH0_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH0_REG register
+ *  The second-to-last receive descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x98)
+/** AHB_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH0_M  (AHB_DMA_INLINK_DSCR_BF1_CH0_V << AHB_DMA_INLINK_DSCR_BF1_CH0_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH0_S  0
+
+/** AHB_DMA_IN_PRI_CH0_REG register
+ *  Priority register of RX channel 0
+ */
+#define AHB_DMA_IN_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x9c)
+/** AHB_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 0.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_RX_PRI_CH0    0x0000000FU
+#define AHB_DMA_RX_PRI_CH0_M  (AHB_DMA_RX_PRI_CH0_V << AHB_DMA_RX_PRI_CH0_S)
+#define AHB_DMA_RX_PRI_CH0_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH0_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH0_REG register
+ *  Peripheral selection register of RX channel 0
+ */
+#define AHB_DMA_IN_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0xa0)
+/** AHB_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 0.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_IN_SEL_CH0    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH0_M  (AHB_DMA_PERI_IN_SEL_CH0_V << AHB_DMA_PERI_IN_SEL_CH0_S)
+#define AHB_DMA_PERI_IN_SEL_CH0_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH0_S  0
+
+/** AHB_DMA_OUT_CONF0_CH0_REG register
+ *  Configuration register 0 of TX channel 0
+ */
+#define AHB_DMA_OUT_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd0)
+/** AHB_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH0    (BIT(0))
+#define AHB_DMA_OUT_RST_CH0_M  (AHB_DMA_OUT_RST_CH0_V << AHB_DMA_OUT_RST_CH0_S)
+#define AHB_DMA_OUT_RST_CH0_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH0_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH0    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH0_M  (AHB_DMA_OUT_LOOP_TEST_CH0_V << AHB_DMA_OUT_LOOP_TEST_CH0_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH0_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0_M  (AHB_DMA_OUT_AUTO_WRBACK_CH0_V << AHB_DMA_OUT_AUTO_WRBACK_CH0_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 0 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 0 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH0    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH0_M  (AHB_DMA_OUT_EOF_MODE_CH0_V << AHB_DMA_OUT_EOF_MODE_CH0_S)
+#define AHB_DMA_OUT_EOF_MODE_CH0_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH0_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 0 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0_M  (AHB_DMA_OUTDSCR_BURST_EN_CH0_V << AHB_DMA_OUTDSCR_BURST_EN_CH0_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0_S  4
+/** AHB_DMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to 1 to enable INCR4 burst transfer for Tx channel 0 transmitting data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_OUT_DATA_BURST_EN_CH0    (BIT(5))
+#define AHB_DMA_OUT_DATA_BURST_EN_CH0_M  (AHB_DMA_OUT_DATA_BURST_EN_CH0_V << AHB_DMA_OUT_DATA_BURST_EN_CH0_S)
+#define AHB_DMA_OUT_DATA_BURST_EN_CH0_V  0x00000001U
+#define AHB_DMA_OUT_DATA_BURST_EN_CH0_S  5
+/** AHB_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH0    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH0_M  (AHB_DMA_OUT_ETM_EN_CH0_V << AHB_DMA_OUT_ETM_EN_CH0_S)
+#define AHB_DMA_OUT_ETM_EN_CH0_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH0_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 1;
+ *  Configures max burst size for TX channel0.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S  8
+
+/** AHB_DMA_OUT_CONF1_CH0_REG register
+ *  Configuration register 1 of TX channel 0
+ */
+#define AHB_DMA_OUT_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd4)
+/** AHB_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH0    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH0_M  (AHB_DMA_OUT_CHECK_OWNER_CH0_V << AHB_DMA_OUT_CHECK_OWNER_CH0_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH0_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH0_REG register
+ *  Receive FIFO status of RX channel 0
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd8)
+/** AHB_DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH0    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH0_M  (AHB_DMA_OUTFIFO_FULL_CH0_V << AHB_DMA_OUTFIFO_FULL_CH0_S)
+#define AHB_DMA_OUTFIFO_FULL_CH0_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH0_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH0    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH0_M  (AHB_DMA_OUTFIFO_EMPTY_CH0_V << AHB_DMA_OUTFIFO_EMPTY_CH0_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH0_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH0_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 0
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH0    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH0_M  (AHB_DMA_OUTFIFO_CNT_CH0_V << AHB_DMA_OUTFIFO_CNT_CH0_S)
+#define AHB_DMA_OUTFIFO_CNT_CH0_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH0_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S  26
+
+/** AHB_DMA_OUT_PUSH_CH0_REG register
+ *  Push control register of TX channel 0
+ */
+#define AHB_DMA_OUT_PUSH_CH0_REG (DR_REG_AHB_DMA_BASE + 0xdc)
+/** AHB_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH0    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH0_M  (AHB_DMA_OUTFIFO_WDATA_CH0_V << AHB_DMA_OUTFIFO_WDATA_CH0_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH0_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH0_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH0    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH0_M  (AHB_DMA_OUTFIFO_PUSH_CH0_V << AHB_DMA_OUTFIFO_PUSH_CH0_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH0_S  9
+
+/** AHB_DMA_OUT_LINK_CH0_REG register
+ *  Push control register of TX channel 0
+ */
+#define AHB_DMA_OUT_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe0)
+/** AHB_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 0 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH0    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH0_M  (AHB_DMA_OUTLINK_STOP_CH0_V << AHB_DMA_OUTLINK_STOP_CH0_S)
+#define AHB_DMA_OUTLINK_STOP_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH0_S  0
+/** AHB_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 0 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH0    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH0_M  (AHB_DMA_OUTLINK_START_CH0_V << AHB_DMA_OUTLINK_START_CH0_S)
+#define AHB_DMA_OUTLINK_START_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH0_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 0 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH0    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH0_M  (AHB_DMA_OUTLINK_RESTART_CH0_V << AHB_DMA_OUTLINK_RESTART_CH0_S)
+#define AHB_DMA_OUTLINK_RESTART_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH0_S  2
+/** AHB_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH0    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH0_M  (AHB_DMA_OUTLINK_PARK_CH0_V << AHB_DMA_OUTLINK_PARK_CH0_S)
+#define AHB_DMA_OUTLINK_PARK_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH0_S  3
+
+/** AHB_DMA_OUT_STATE_CH0_REG register
+ *  Transmit status of TX channel 0
+ */
+#define AHB_DMA_OUT_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe4)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH0    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH0_M  (AHB_DMA_OUT_DSCR_STATE_CH0_V << AHB_DMA_OUT_DSCR_STATE_CH0_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH0_S  18
+/** AHB_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH0    0x00000007U
+#define AHB_DMA_OUT_STATE_CH0_M  (AHB_DMA_OUT_STATE_CH0_V << AHB_DMA_OUT_STATE_CH0_S)
+#define AHB_DMA_OUT_STATE_CH0_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH0_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 0
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe8)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH0_V << AHB_DMA_OUT_EOF_DES_ADDR_CH0_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 0
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xec)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_DSCR_CH0_REG register
+ *  Current transmit descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf0)
+/** AHB_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH0_M  (AHB_DMA_OUTLINK_DSCR_CH0_V << AHB_DMA_OUTLINK_DSCR_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH0_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH0_REG register
+ *  The last transmit descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf4)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH0_V << AHB_DMA_OUTLINK_DSCR_BF0_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH0_REG register
+ *  The second-to-last transmit descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf8)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH0_V << AHB_DMA_OUTLINK_DSCR_BF1_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** AHB_DMA_OUT_PRI_CH0_REG register
+ *  Priority register of TX channel 0
+ */
+#define AHB_DMA_OUT_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0xfc)
+/** AHB_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 0.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_TX_PRI_CH0    0x0000000FU
+#define AHB_DMA_TX_PRI_CH0_M  (AHB_DMA_TX_PRI_CH0_V << AHB_DMA_TX_PRI_CH0_S)
+#define AHB_DMA_TX_PRI_CH0_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH0_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH0_REG register
+ *  Peripheral selection register of TX channel 0
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0x100)
+/** AHB_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 0.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH0    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH0_M  (AHB_DMA_PERI_OUT_SEL_CH0_V << AHB_DMA_PERI_OUT_SEL_CH0_S)
+#define AHB_DMA_PERI_OUT_SEL_CH0_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH0_S  0
+
+/** AHB_DMA_IN_CONF0_CH1_REG register
+ *  Configuration register 0 of RX channel 1
+ */
+#define AHB_DMA_IN_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x130)
+/** AHB_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH1    (BIT(0))
+#define AHB_DMA_IN_RST_CH1_M  (AHB_DMA_IN_RST_CH1_V << AHB_DMA_IN_RST_CH1_S)
+#define AHB_DMA_IN_RST_CH1_V  0x00000001U
+#define AHB_DMA_IN_RST_CH1_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH1    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH1_M  (AHB_DMA_IN_LOOP_TEST_CH1_V << AHB_DMA_IN_LOOP_TEST_CH1_S)
+#define AHB_DMA_IN_LOOP_TEST_CH1_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH1_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 1 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH1    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH1_M  (AHB_DMA_INDSCR_BURST_EN_CH1_V << AHB_DMA_INDSCR_BURST_EN_CH1_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH1_S  2
+/** AHB_DMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 1 receiving data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_IN_DATA_BURST_EN_CH1    (BIT(3))
+#define AHB_DMA_IN_DATA_BURST_EN_CH1_M  (AHB_DMA_IN_DATA_BURST_EN_CH1_V << AHB_DMA_IN_DATA_BURST_EN_CH1_S)
+#define AHB_DMA_IN_DATA_BURST_EN_CH1_V  0x00000001U
+#define AHB_DMA_IN_DATA_BURST_EN_CH1_S  3
+/** AHB_DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH1    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH1_M  (AHB_DMA_MEM_TRANS_EN_CH1_V << AHB_DMA_MEM_TRANS_EN_CH1_S)
+#define AHB_DMA_MEM_TRANS_EN_CH1_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH1_S  4
+/** AHB_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH1    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH1_M  (AHB_DMA_IN_ETM_EN_CH1_V << AHB_DMA_IN_ETM_EN_CH1_S)
+#define AHB_DMA_IN_ETM_EN_CH1_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH1_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 1;
+ *  Configures max burst size for Rx channel1.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S  6
+
+/** AHB_DMA_IN_CONF1_CH1_REG register
+ *  Configuration register 1 of RX channel 1
+ */
+#define AHB_DMA_IN_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x134)
+/** AHB_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH1    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH1_M  (AHB_DMA_IN_CHECK_OWNER_CH1_V << AHB_DMA_IN_CHECK_OWNER_CH1_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH1_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH1_REG register
+ *  Receive FIFO status of RX channel 1
+ */
+#define AHB_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x138)
+/** AHB_DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH1    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH1_M  (AHB_DMA_INFIFO_FULL_CH1_V << AHB_DMA_INFIFO_FULL_CH1_S)
+#define AHB_DMA_INFIFO_FULL_CH1_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH1_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH1    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH1_M  (AHB_DMA_INFIFO_EMPTY_CH1_V << AHB_DMA_INFIFO_EMPTY_CH1_S)
+#define AHB_DMA_INFIFO_EMPTY_CH1_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH1_S  1
+/** AHB_DMA_INFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 1
+ */
+#define AHB_DMA_INFIFO_CNT_CH1    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH1_M  (AHB_DMA_INFIFO_CNT_CH1_V << AHB_DMA_INFIFO_CNT_CH1_S)
+#define AHB_DMA_INFIFO_CNT_CH1_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH1_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH1    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH1_M  (AHB_DMA_IN_BUF_HUNGRY_CH1_V << AHB_DMA_IN_BUF_HUNGRY_CH1_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH1_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH1_S  27
+
+/** AHB_DMA_IN_POP_CH1_REG register
+ *  Receive FIFO status of RX channel 1
+ */
+#define AHB_DMA_IN_POP_CH1_REG (DR_REG_AHB_DMA_BASE + 0x13c)
+/** AHB_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH1    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH1_M  (AHB_DMA_INFIFO_RDATA_CH1_V << AHB_DMA_INFIFO_RDATA_CH1_S)
+#define AHB_DMA_INFIFO_RDATA_CH1_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH1_S  0
+/** AHB_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH1    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH1_M  (AHB_DMA_INFIFO_POP_CH1_V << AHB_DMA_INFIFO_POP_CH1_S)
+#define AHB_DMA_INFIFO_POP_CH1_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH1_S  12
+
+/** AHB_DMA_IN_LINK_CH1_REG register
+ *  Receive FIFO status of RX channel 1
+ */
+#define AHB_DMA_IN_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x140)
+/** AHB_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ *  .
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH1    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH1_M  (AHB_DMA_INLINK_AUTO_RET_CH1_V << AHB_DMA_INLINK_AUTO_RET_CH1_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH1_S  0
+/** AHB_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 1 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH1    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH1_M  (AHB_DMA_INLINK_STOP_CH1_V << AHB_DMA_INLINK_STOP_CH1_S)
+#define AHB_DMA_INLINK_STOP_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH1_S  1
+/** AHB_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 1 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH1    (BIT(2))
+#define AHB_DMA_INLINK_START_CH1_M  (AHB_DMA_INLINK_START_CH1_V << AHB_DMA_INLINK_START_CH1_S)
+#define AHB_DMA_INLINK_START_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH1_S  2
+/** AHB_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 1 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH1    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH1_M  (AHB_DMA_INLINK_RESTART_CH1_V << AHB_DMA_INLINK_RESTART_CH1_S)
+#define AHB_DMA_INLINK_RESTART_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH1_S  3
+/** AHB_DMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH1    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH1_M  (AHB_DMA_INLINK_PARK_CH1_V << AHB_DMA_INLINK_PARK_CH1_S)
+#define AHB_DMA_INLINK_PARK_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH1_S  4
+
+/** AHB_DMA_IN_STATE_CH1_REG register
+ *  Receive status of RX channel 1
+ */
+#define AHB_DMA_IN_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x144)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1_M  (AHB_DMA_INLINK_DSCR_ADDR_CH1_V << AHB_DMA_INLINK_DSCR_ADDR_CH1_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH1    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH1_M  (AHB_DMA_IN_DSCR_STATE_CH1_V << AHB_DMA_IN_DSCR_STATE_CH1_S)
+#define AHB_DMA_IN_DSCR_STATE_CH1_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH1_S  18
+/** AHB_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_IN_STATE_CH1    0x00000007U
+#define AHB_DMA_IN_STATE_CH1_M  (AHB_DMA_IN_STATE_CH1_V << AHB_DMA_IN_STATE_CH1_S)
+#define AHB_DMA_IN_STATE_CH1_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH1_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 1
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x148)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Receive descriptor address when errors occur of RX channel 1
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14c)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_DSCR_CH1_REG register
+ *  Current receive descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x150)
+/** AHB_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH1_M  (AHB_DMA_INLINK_DSCR_CH1_V << AHB_DMA_INLINK_DSCR_CH1_S)
+#define AHB_DMA_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH1_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH1_REG register
+ *  The last receive descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x154)
+/** AHB_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH1_M  (AHB_DMA_INLINK_DSCR_BF0_CH1_V << AHB_DMA_INLINK_DSCR_BF0_CH1_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH1_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH1_REG register
+ *  The second-to-last receive descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x158)
+/** AHB_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH1_M  (AHB_DMA_INLINK_DSCR_BF1_CH1_V << AHB_DMA_INLINK_DSCR_BF1_CH1_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH1_S  0
+
+/** AHB_DMA_IN_PRI_CH1_REG register
+ *  Priority register of RX channel 1
+ */
+#define AHB_DMA_IN_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c)
+/** AHB_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 1.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_RX_PRI_CH1    0x0000000FU
+#define AHB_DMA_RX_PRI_CH1_M  (AHB_DMA_RX_PRI_CH1_V << AHB_DMA_RX_PRI_CH1_S)
+#define AHB_DMA_RX_PRI_CH1_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH1_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH1_REG register
+ *  Peripheral selection register of RX channel 1
+ */
+#define AHB_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x160)
+/** AHB_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 1.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_IN_SEL_CH1    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH1_M  (AHB_DMA_PERI_IN_SEL_CH1_V << AHB_DMA_PERI_IN_SEL_CH1_S)
+#define AHB_DMA_PERI_IN_SEL_CH1_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH1_S  0
+
+/** AHB_DMA_OUT_CONF0_CH1_REG register
+ *  Configuration register 0 of TX channel 1
+ */
+#define AHB_DMA_OUT_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x190)
+/** AHB_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH1    (BIT(0))
+#define AHB_DMA_OUT_RST_CH1_M  (AHB_DMA_OUT_RST_CH1_V << AHB_DMA_OUT_RST_CH1_S)
+#define AHB_DMA_OUT_RST_CH1_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH1_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH1    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH1_M  (AHB_DMA_OUT_LOOP_TEST_CH1_V << AHB_DMA_OUT_LOOP_TEST_CH1_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH1_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1_M  (AHB_DMA_OUT_AUTO_WRBACK_CH1_V << AHB_DMA_OUT_AUTO_WRBACK_CH1_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 1 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 1 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH1    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH1_M  (AHB_DMA_OUT_EOF_MODE_CH1_V << AHB_DMA_OUT_EOF_MODE_CH1_S)
+#define AHB_DMA_OUT_EOF_MODE_CH1_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH1_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 1 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1_M  (AHB_DMA_OUTDSCR_BURST_EN_CH1_V << AHB_DMA_OUTDSCR_BURST_EN_CH1_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1_S  4
+/** AHB_DMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_OUT_DATA_BURST_EN_CH1    (BIT(5))
+#define AHB_DMA_OUT_DATA_BURST_EN_CH1_M  (AHB_DMA_OUT_DATA_BURST_EN_CH1_V << AHB_DMA_OUT_DATA_BURST_EN_CH1_S)
+#define AHB_DMA_OUT_DATA_BURST_EN_CH1_V  0x00000001U
+#define AHB_DMA_OUT_DATA_BURST_EN_CH1_S  5
+/** AHB_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH1    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH1_M  (AHB_DMA_OUT_ETM_EN_CH1_V << AHB_DMA_OUT_ETM_EN_CH1_S)
+#define AHB_DMA_OUT_ETM_EN_CH1_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH1_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 1;
+ *  Configures max burst size for TX channel1.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S  8
+
+/** AHB_DMA_OUT_CONF1_CH1_REG register
+ *  Configuration register 1 of TX channel 1
+ */
+#define AHB_DMA_OUT_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x194)
+/** AHB_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH1    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH1_M  (AHB_DMA_OUT_CHECK_OWNER_CH1_V << AHB_DMA_OUT_CHECK_OWNER_CH1_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH1_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH1_REG register
+ *  Receive FIFO status of RX channel 1
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x198)
+/** AHB_DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH1    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH1_M  (AHB_DMA_OUTFIFO_FULL_CH1_V << AHB_DMA_OUTFIFO_FULL_CH1_S)
+#define AHB_DMA_OUTFIFO_FULL_CH1_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH1_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH1    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH1_M  (AHB_DMA_OUTFIFO_EMPTY_CH1_V << AHB_DMA_OUTFIFO_EMPTY_CH1_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH1_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH1_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 1
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH1    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH1_M  (AHB_DMA_OUTFIFO_CNT_CH1_V << AHB_DMA_OUTFIFO_CNT_CH1_S)
+#define AHB_DMA_OUTFIFO_CNT_CH1_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH1_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S  26
+
+/** AHB_DMA_OUT_PUSH_CH1_REG register
+ *  Push control register of TX channel 1
+ */
+#define AHB_DMA_OUT_PUSH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x19c)
+/** AHB_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH1    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH1_M  (AHB_DMA_OUTFIFO_WDATA_CH1_V << AHB_DMA_OUTFIFO_WDATA_CH1_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH1_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH1_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH1    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH1_M  (AHB_DMA_OUTFIFO_PUSH_CH1_V << AHB_DMA_OUTFIFO_PUSH_CH1_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH1_S  9
+
+/** AHB_DMA_OUT_LINK_CH1_REG register
+ *  Push control register of TX channel 1
+ */
+#define AHB_DMA_OUT_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a0)
+/** AHB_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 1 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH1    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH1_M  (AHB_DMA_OUTLINK_STOP_CH1_V << AHB_DMA_OUTLINK_STOP_CH1_S)
+#define AHB_DMA_OUTLINK_STOP_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH1_S  0
+/** AHB_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 1 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH1    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH1_M  (AHB_DMA_OUTLINK_START_CH1_V << AHB_DMA_OUTLINK_START_CH1_S)
+#define AHB_DMA_OUTLINK_START_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH1_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 1 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH1    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH1_M  (AHB_DMA_OUTLINK_RESTART_CH1_V << AHB_DMA_OUTLINK_RESTART_CH1_S)
+#define AHB_DMA_OUTLINK_RESTART_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH1_S  2
+/** AHB_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH1    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH1_M  (AHB_DMA_OUTLINK_PARK_CH1_V << AHB_DMA_OUTLINK_PARK_CH1_S)
+#define AHB_DMA_OUTLINK_PARK_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH1_S  3
+
+/** AHB_DMA_OUT_STATE_CH1_REG register
+ *  Transmit status of TX channel 1
+ */
+#define AHB_DMA_OUT_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a4)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH1    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH1_M  (AHB_DMA_OUT_DSCR_STATE_CH1_V << AHB_DMA_OUT_DSCR_STATE_CH1_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH1_S  18
+/** AHB_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH1    0x00000007U
+#define AHB_DMA_OUT_STATE_CH1_M  (AHB_DMA_OUT_STATE_CH1_V << AHB_DMA_OUT_STATE_CH1_S)
+#define AHB_DMA_OUT_STATE_CH1_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH1_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 1
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a8)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH1_V << AHB_DMA_OUT_EOF_DES_ADDR_CH1_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 1
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1ac)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_DSCR_CH1_REG register
+ *  Current transmit descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b0)
+/** AHB_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH1_M  (AHB_DMA_OUTLINK_DSCR_CH1_V << AHB_DMA_OUTLINK_DSCR_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH1_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH1_REG register
+ *  The last transmit descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b4)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH1_V << AHB_DMA_OUTLINK_DSCR_BF0_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH1_REG register
+ *  The second-to-last transmit descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b8)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH1_V << AHB_DMA_OUTLINK_DSCR_BF1_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** AHB_DMA_OUT_PRI_CH1_REG register
+ *  Priority register of TX channel 1
+ */
+#define AHB_DMA_OUT_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc)
+/** AHB_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 1.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_TX_PRI_CH1    0x0000000FU
+#define AHB_DMA_TX_PRI_CH1_M  (AHB_DMA_TX_PRI_CH1_V << AHB_DMA_TX_PRI_CH1_S)
+#define AHB_DMA_TX_PRI_CH1_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH1_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH1_REG register
+ *  Peripheral selection register of TX channel 1
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c0)
+/** AHB_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 1.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH1    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH1_M  (AHB_DMA_PERI_OUT_SEL_CH1_V << AHB_DMA_PERI_OUT_SEL_CH1_S)
+#define AHB_DMA_PERI_OUT_SEL_CH1_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH1_S  0
+
+/** AHB_DMA_IN_CONF0_CH2_REG register
+ *  Configuration register 0 of RX channel 2
+ */
+#define AHB_DMA_IN_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f0)
+/** AHB_DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 2 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH2    (BIT(0))
+#define AHB_DMA_IN_RST_CH2_M  (AHB_DMA_IN_RST_CH2_V << AHB_DMA_IN_RST_CH2_S)
+#define AHB_DMA_IN_RST_CH2_V  0x00000001U
+#define AHB_DMA_IN_RST_CH2_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH2    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH2_M  (AHB_DMA_IN_LOOP_TEST_CH2_V << AHB_DMA_IN_LOOP_TEST_CH2_S)
+#define AHB_DMA_IN_LOOP_TEST_CH2_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH2_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 2 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH2    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH2_M  (AHB_DMA_INDSCR_BURST_EN_CH2_V << AHB_DMA_INDSCR_BURST_EN_CH2_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH2_S  2
+/** AHB_DMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 2 receiving data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_IN_DATA_BURST_EN_CH2    (BIT(3))
+#define AHB_DMA_IN_DATA_BURST_EN_CH2_M  (AHB_DMA_IN_DATA_BURST_EN_CH2_V << AHB_DMA_IN_DATA_BURST_EN_CH2_S)
+#define AHB_DMA_IN_DATA_BURST_EN_CH2_V  0x00000001U
+#define AHB_DMA_IN_DATA_BURST_EN_CH2_S  3
+/** AHB_DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH2    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH2_M  (AHB_DMA_MEM_TRANS_EN_CH2_V << AHB_DMA_MEM_TRANS_EN_CH2_S)
+#define AHB_DMA_MEM_TRANS_EN_CH2_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH2_S  4
+/** AHB_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH2    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH2_M  (AHB_DMA_IN_ETM_EN_CH2_V << AHB_DMA_IN_ETM_EN_CH2_S)
+#define AHB_DMA_IN_ETM_EN_CH2_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH2_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [7:6]; default: 1;
+ *  Configures max burst size for Rx channel2.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S  6
+
+/** AHB_DMA_IN_CONF1_CH2_REG register
+ *  Configuration register 1 of RX channel 2
+ */
+#define AHB_DMA_IN_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f4)
+/** AHB_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH2    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH2_M  (AHB_DMA_IN_CHECK_OWNER_CH2_V << AHB_DMA_IN_CHECK_OWNER_CH2_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH2_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH2_REG register
+ *  Receive FIFO status of RX channel 2
+ */
+#define AHB_DMA_INFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f8)
+/** AHB_DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH2    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH2_M  (AHB_DMA_INFIFO_FULL_CH2_V << AHB_DMA_INFIFO_FULL_CH2_S)
+#define AHB_DMA_INFIFO_FULL_CH2_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH2_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH2    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH2_M  (AHB_DMA_INFIFO_EMPTY_CH2_V << AHB_DMA_INFIFO_EMPTY_CH2_S)
+#define AHB_DMA_INFIFO_EMPTY_CH2_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH2_S  1
+/** AHB_DMA_INFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 2
+ */
+#define AHB_DMA_INFIFO_CNT_CH2    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH2_M  (AHB_DMA_INFIFO_CNT_CH2_V << AHB_DMA_INFIFO_CNT_CH2_S)
+#define AHB_DMA_INFIFO_CNT_CH2_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH2_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH2    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH2_M  (AHB_DMA_IN_BUF_HUNGRY_CH2_V << AHB_DMA_IN_BUF_HUNGRY_CH2_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH2_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH2_S  27
+
+/** AHB_DMA_IN_POP_CH2_REG register
+ *  Receive FIFO status of RX channel 2
+ */
+#define AHB_DMA_IN_POP_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1fc)
+/** AHB_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH2    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH2_M  (AHB_DMA_INFIFO_RDATA_CH2_V << AHB_DMA_INFIFO_RDATA_CH2_S)
+#define AHB_DMA_INFIFO_RDATA_CH2_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH2_S  0
+/** AHB_DMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH2    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH2_M  (AHB_DMA_INFIFO_POP_CH2_V << AHB_DMA_INFIFO_POP_CH2_S)
+#define AHB_DMA_INFIFO_POP_CH2_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH2_S  12
+
+/** AHB_DMA_IN_LINK_CH2_REG register
+ *  Receive FIFO status of RX channel 2
+ */
+#define AHB_DMA_IN_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x200)
+/** AHB_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ *  .
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH2    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH2_M  (AHB_DMA_INLINK_AUTO_RET_CH2_V << AHB_DMA_INLINK_AUTO_RET_CH2_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH2_S  0
+/** AHB_DMA_INLINK_STOP_CH2 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 2 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH2    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH2_M  (AHB_DMA_INLINK_STOP_CH2_V << AHB_DMA_INLINK_STOP_CH2_S)
+#define AHB_DMA_INLINK_STOP_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH2_S  1
+/** AHB_DMA_INLINK_START_CH2 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 2 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH2    (BIT(2))
+#define AHB_DMA_INLINK_START_CH2_M  (AHB_DMA_INLINK_START_CH2_V << AHB_DMA_INLINK_START_CH2_S)
+#define AHB_DMA_INLINK_START_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH2_S  2
+/** AHB_DMA_INLINK_RESTART_CH2 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 2 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH2    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH2_M  (AHB_DMA_INLINK_RESTART_CH2_V << AHB_DMA_INLINK_RESTART_CH2_S)
+#define AHB_DMA_INLINK_RESTART_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH2_S  3
+/** AHB_DMA_INLINK_PARK_CH2 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH2    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH2_M  (AHB_DMA_INLINK_PARK_CH2_V << AHB_DMA_INLINK_PARK_CH2_S)
+#define AHB_DMA_INLINK_PARK_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH2_S  4
+
+/** AHB_DMA_IN_STATE_CH2_REG register
+ *  Receive status of RX channel 2
+ */
+#define AHB_DMA_IN_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x204)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2_M  (AHB_DMA_INLINK_DSCR_ADDR_CH2_V << AHB_DMA_INLINK_DSCR_ADDR_CH2_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH2    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH2_M  (AHB_DMA_IN_DSCR_STATE_CH2_V << AHB_DMA_IN_DSCR_STATE_CH2_S)
+#define AHB_DMA_IN_DSCR_STATE_CH2_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH2_S  18
+/** AHB_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_IN_STATE_CH2    0x00000007U
+#define AHB_DMA_IN_STATE_CH2_M  (AHB_DMA_IN_STATE_CH2_V << AHB_DMA_IN_STATE_CH2_S)
+#define AHB_DMA_IN_STATE_CH2_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH2_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 2
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x208)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  Receive descriptor address when errors occur of RX channel 2
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20c)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_IN_DSCR_CH2_REG register
+ *  Current receive descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x210)
+/** AHB_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH2_M  (AHB_DMA_INLINK_DSCR_CH2_V << AHB_DMA_INLINK_DSCR_CH2_S)
+#define AHB_DMA_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH2_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH2_REG register
+ *  The last receive descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x214)
+/** AHB_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH2_M  (AHB_DMA_INLINK_DSCR_BF0_CH2_V << AHB_DMA_INLINK_DSCR_BF0_CH2_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH2_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH2_REG register
+ *  The second-to-last receive descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x218)
+/** AHB_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH2_M  (AHB_DMA_INLINK_DSCR_BF1_CH2_V << AHB_DMA_INLINK_DSCR_BF1_CH2_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH2_S  0
+
+/** AHB_DMA_IN_PRI_CH2_REG register
+ *  Priority register of RX channel 2
+ */
+#define AHB_DMA_IN_PRI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x21c)
+/** AHB_DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 2.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_RX_PRI_CH2    0x0000000FU
+#define AHB_DMA_RX_PRI_CH2_M  (AHB_DMA_RX_PRI_CH2_V << AHB_DMA_RX_PRI_CH2_S)
+#define AHB_DMA_RX_PRI_CH2_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH2_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH2_REG register
+ *  Peripheral selection register of RX channel 2
+ */
+#define AHB_DMA_IN_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x220)
+/** AHB_DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 2.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_IN_SEL_CH2    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH2_M  (AHB_DMA_PERI_IN_SEL_CH2_V << AHB_DMA_PERI_IN_SEL_CH2_S)
+#define AHB_DMA_PERI_IN_SEL_CH2_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH2_S  0
+
+/** AHB_DMA_OUT_CONF0_CH2_REG register
+ *  Configuration register 0 of TX channel 2
+ */
+#define AHB_DMA_OUT_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x250)
+/** AHB_DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH2    (BIT(0))
+#define AHB_DMA_OUT_RST_CH2_M  (AHB_DMA_OUT_RST_CH2_V << AHB_DMA_OUT_RST_CH2_S)
+#define AHB_DMA_OUT_RST_CH2_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH2_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH2    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH2_M  (AHB_DMA_OUT_LOOP_TEST_CH2_V << AHB_DMA_OUT_LOOP_TEST_CH2_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH2_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2_M  (AHB_DMA_OUT_AUTO_WRBACK_CH2_V << AHB_DMA_OUT_AUTO_WRBACK_CH2_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 2 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 2 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH2    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH2_M  (AHB_DMA_OUT_EOF_MODE_CH2_V << AHB_DMA_OUT_EOF_MODE_CH2_S)
+#define AHB_DMA_OUT_EOF_MODE_CH2_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH2_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 2 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2_M  (AHB_DMA_OUTDSCR_BURST_EN_CH2_V << AHB_DMA_OUTDSCR_BURST_EN_CH2_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2_S  4
+/** AHB_DMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_OUT_DATA_BURST_EN_CH2    (BIT(5))
+#define AHB_DMA_OUT_DATA_BURST_EN_CH2_M  (AHB_DMA_OUT_DATA_BURST_EN_CH2_V << AHB_DMA_OUT_DATA_BURST_EN_CH2_S)
+#define AHB_DMA_OUT_DATA_BURST_EN_CH2_V  0x00000001U
+#define AHB_DMA_OUT_DATA_BURST_EN_CH2_S  5
+/** AHB_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH2    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH2_M  (AHB_DMA_OUT_ETM_EN_CH2_V << AHB_DMA_OUT_ETM_EN_CH2_S)
+#define AHB_DMA_OUT_ETM_EN_CH2_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH2_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [9:8]; default: 1;
+ *  Configures max burst size for TX channel2.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S  8
+
+/** AHB_DMA_OUT_CONF1_CH2_REG register
+ *  Configuration register 1 of TX channel 2
+ */
+#define AHB_DMA_OUT_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x254)
+/** AHB_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH2    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH2_M  (AHB_DMA_OUT_CHECK_OWNER_CH2_V << AHB_DMA_OUT_CHECK_OWNER_CH2_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH2_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH2_REG register
+ *  Receive FIFO status of RX channel 2
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x258)
+/** AHB_DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH2    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH2_M  (AHB_DMA_OUTFIFO_FULL_CH2_V << AHB_DMA_OUTFIFO_FULL_CH2_S)
+#define AHB_DMA_OUTFIFO_FULL_CH2_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH2_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH2    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH2_M  (AHB_DMA_OUTFIFO_EMPTY_CH2_V << AHB_DMA_OUTFIFO_EMPTY_CH2_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH2_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH2_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 2
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH2    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH2_M  (AHB_DMA_OUTFIFO_CNT_CH2_V << AHB_DMA_OUTFIFO_CNT_CH2_S)
+#define AHB_DMA_OUTFIFO_CNT_CH2_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH2_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S  26
+
+/** AHB_DMA_OUT_PUSH_CH2_REG register
+ *  Push control register of TX channel 2
+ */
+#define AHB_DMA_OUT_PUSH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x25c)
+/** AHB_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH2    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH2_M  (AHB_DMA_OUTFIFO_WDATA_CH2_V << AHB_DMA_OUTFIFO_WDATA_CH2_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH2_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH2_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH2    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH2_M  (AHB_DMA_OUTFIFO_PUSH_CH2_V << AHB_DMA_OUTFIFO_PUSH_CH2_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH2_S  9
+
+/** AHB_DMA_OUT_LINK_CH2_REG register
+ *  Push control register of TX channel 2
+ */
+#define AHB_DMA_OUT_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x260)
+/** AHB_DMA_OUTLINK_STOP_CH2 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 2 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH2    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH2_M  (AHB_DMA_OUTLINK_STOP_CH2_V << AHB_DMA_OUTLINK_STOP_CH2_S)
+#define AHB_DMA_OUTLINK_STOP_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH2_S  0
+/** AHB_DMA_OUTLINK_START_CH2 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 2 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH2    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH2_M  (AHB_DMA_OUTLINK_START_CH2_V << AHB_DMA_OUTLINK_START_CH2_S)
+#define AHB_DMA_OUTLINK_START_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH2_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH2 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 2 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH2    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH2_M  (AHB_DMA_OUTLINK_RESTART_CH2_V << AHB_DMA_OUTLINK_RESTART_CH2_S)
+#define AHB_DMA_OUTLINK_RESTART_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH2_S  2
+/** AHB_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH2    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH2_M  (AHB_DMA_OUTLINK_PARK_CH2_V << AHB_DMA_OUTLINK_PARK_CH2_S)
+#define AHB_DMA_OUTLINK_PARK_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH2_S  3
+
+/** AHB_DMA_OUT_STATE_CH2_REG register
+ *  Transmit status of TX channel 2
+ */
+#define AHB_DMA_OUT_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x264)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH2_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH2    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH2_M  (AHB_DMA_OUT_DSCR_STATE_CH2_V << AHB_DMA_OUT_DSCR_STATE_CH2_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH2_S  18
+/** AHB_DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH2    0x00000007U
+#define AHB_DMA_OUT_STATE_CH2_M  (AHB_DMA_OUT_STATE_CH2_V << AHB_DMA_OUT_STATE_CH2_S)
+#define AHB_DMA_OUT_STATE_CH2_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH2_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 2
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x268)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH2_V << AHB_DMA_OUT_EOF_DES_ADDR_CH2_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 2
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x26c)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_DSCR_CH2_REG register
+ *  Current transmit descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x270)
+/** AHB_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH2_M  (AHB_DMA_OUTLINK_DSCR_CH2_V << AHB_DMA_OUTLINK_DSCR_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH2_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH2_REG register
+ *  The last transmit descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x274)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH2_V << AHB_DMA_OUTLINK_DSCR_BF0_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH2_REG register
+ *  The second-to-last transmit descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x278)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH2_V << AHB_DMA_OUTLINK_DSCR_BF1_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** AHB_DMA_OUT_PRI_CH2_REG register
+ *  Priority register of TX channel 2
+ */
+#define AHB_DMA_OUT_PRI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x27c)
+/** AHB_DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 2.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_TX_PRI_CH2    0x0000000FU
+#define AHB_DMA_TX_PRI_CH2_M  (AHB_DMA_TX_PRI_CH2_V << AHB_DMA_TX_PRI_CH2_S)
+#define AHB_DMA_TX_PRI_CH2_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH2_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH2_REG register
+ *  Peripheral selection register of TX channel 2
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x280)
+/** AHB_DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 2.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH2    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH2_M  (AHB_DMA_PERI_OUT_SEL_CH2_V << AHB_DMA_PERI_OUT_SEL_CH2_S)
+#define AHB_DMA_PERI_OUT_SEL_CH2_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH2_S  0
+
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH0_REG register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2bc)
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH0_M  (AHB_DMA_OUT_CRC_INIT_DATA_CH0_V << AHB_DMA_OUT_CRC_INIT_DATA_CH0_S)
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH0_S  0
+
+/** AHB_DMA_TX_CRC_WIDTH_CH0_REG register
+ *  This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2c0)
+/** AHB_DMA_TX_CRC_WIDTH_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH0    0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH0_M  (AHB_DMA_TX_CRC_WIDTH_CH0_V << AHB_DMA_TX_CRC_WIDTH_CH0_S)
+#define AHB_DMA_TX_CRC_WIDTH_CH0_V  0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH0_S  0
+/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0    (BIT(2))
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_M  (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_S)
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_V  0x00000001U
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_S  2
+
+/** AHB_DMA_OUT_CRC_CLEAR_CH0_REG register
+ *  This register is used to clear ch0 crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2c4)
+/** AHB_DMA_OUT_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH0    (BIT(0))
+#define AHB_DMA_OUT_CRC_CLEAR_CH0_M  (AHB_DMA_OUT_CRC_CLEAR_CH0_V << AHB_DMA_OUT_CRC_CLEAR_CH0_S)
+#define AHB_DMA_OUT_CRC_CLEAR_CH0_V  0x00000001U
+#define AHB_DMA_OUT_CRC_CLEAR_CH0_S  0
+
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_REG register
+ *  This register is used to store ch0 crc result
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2c8)
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_M  (AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_V << AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_S)
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_S  0
+
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH0_REG register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2cc)
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH0    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH0_M  (AHB_DMA_TX_CRC_EN_WR_DATA_CH0_V << AHB_DMA_TX_CRC_EN_WR_DATA_CH0_S)
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH0_S  0
+
+/** AHB_DMA_TX_CRC_EN_ADDR_CH0_REG register
+ *  This register is used to config ch0 crc en addr
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2d0)
+/** AHB_DMA_TX_CRC_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH0_M  (AHB_DMA_TX_CRC_EN_ADDR_CH0_V << AHB_DMA_TX_CRC_EN_ADDR_CH0_S)
+#define AHB_DMA_TX_CRC_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH0_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2d4)
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0    0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_M  (AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_V << AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_S)
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_V  0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2d8)
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_M  (AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_V << AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_S)
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG register
+ *  TX channel 0 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2dc)
+/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel0
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0    0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_M  (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S)
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V  0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S  0
+
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG register
+ *  TX channel 0 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0)
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_M  (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S  0
+
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH1_REG register
+ *  This register is used to config ch1 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2e4)
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH1_M  (AHB_DMA_OUT_CRC_INIT_DATA_CH1_V << AHB_DMA_OUT_CRC_INIT_DATA_CH1_S)
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH1_S  0
+
+/** AHB_DMA_TX_CRC_WIDTH_CH1_REG register
+ *  This register is used to confiig tx ch1 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2e8)
+/** AHB_DMA_TX_CRC_WIDTH_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH1    0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH1_M  (AHB_DMA_TX_CRC_WIDTH_CH1_V << AHB_DMA_TX_CRC_WIDTH_CH1_S)
+#define AHB_DMA_TX_CRC_WIDTH_CH1_V  0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH1_S  0
+/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1    (BIT(2))
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_M  (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_S)
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_V  0x00000001U
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_S  2
+
+/** AHB_DMA_OUT_CRC_CLEAR_CH1_REG register
+ *  This register is used to clear ch1 crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2ec)
+/** AHB_DMA_OUT_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH1    (BIT(0))
+#define AHB_DMA_OUT_CRC_CLEAR_CH1_M  (AHB_DMA_OUT_CRC_CLEAR_CH1_V << AHB_DMA_OUT_CRC_CLEAR_CH1_S)
+#define AHB_DMA_OUT_CRC_CLEAR_CH1_V  0x00000001U
+#define AHB_DMA_OUT_CRC_CLEAR_CH1_S  0
+
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_REG register
+ *  This register is used to store ch1 crc result
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2f0)
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_M  (AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_V << AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_S)
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_S  0
+
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH1_REG register
+ *  This resister is used to config ch1 crc en for every bit
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2f4)
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH1    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH1_M  (AHB_DMA_TX_CRC_EN_WR_DATA_CH1_V << AHB_DMA_TX_CRC_EN_WR_DATA_CH1_S)
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH1_S  0
+
+/** AHB_DMA_TX_CRC_EN_ADDR_CH1_REG register
+ *  This register is used to config ch1 crc en addr
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2f8)
+/** AHB_DMA_TX_CRC_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH1_M  (AHB_DMA_TX_CRC_EN_ADDR_CH1_V << AHB_DMA_TX_CRC_EN_ADDR_CH1_S)
+#define AHB_DMA_TX_CRC_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH1_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2fc)
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1    0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_M  (AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_V << AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_S)
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_V  0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x300)
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_M  (AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_V << AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_S)
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG register
+ *  TX channel 1 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x304)
+/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel1
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1    0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_M  (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S)
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V  0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S  0
+
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG register
+ *  TX channel 1 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308)
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_M  (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S  0
+
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH2_REG register
+ *  This register is used to config ch2 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x30c)
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH2_M  (AHB_DMA_OUT_CRC_INIT_DATA_CH2_V << AHB_DMA_OUT_CRC_INIT_DATA_CH2_S)
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH2_S  0
+
+/** AHB_DMA_TX_CRC_WIDTH_CH2_REG register
+ *  This register is used to confiig tx ch2 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x310)
+/** AHB_DMA_TX_CRC_WIDTH_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH2    0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH2_M  (AHB_DMA_TX_CRC_WIDTH_CH2_V << AHB_DMA_TX_CRC_WIDTH_CH2_S)
+#define AHB_DMA_TX_CRC_WIDTH_CH2_V  0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH2_S  0
+/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2    (BIT(2))
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_M  (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_S)
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_V  0x00000001U
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_S  2
+
+/** AHB_DMA_OUT_CRC_CLEAR_CH2_REG register
+ *  This register is used to clear ch2 crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x314)
+/** AHB_DMA_OUT_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH2    (BIT(0))
+#define AHB_DMA_OUT_CRC_CLEAR_CH2_M  (AHB_DMA_OUT_CRC_CLEAR_CH2_V << AHB_DMA_OUT_CRC_CLEAR_CH2_S)
+#define AHB_DMA_OUT_CRC_CLEAR_CH2_V  0x00000001U
+#define AHB_DMA_OUT_CRC_CLEAR_CH2_S  0
+
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_REG register
+ *  This register is used to store ch2 crc result
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_REG (DR_REG_AHB_DMA_BASE + 0x318)
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_M  (AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_V << AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_S)
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_S  0
+
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH2_REG register
+ *  This resister is used to config ch2 crc en for every bit
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x31c)
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH2    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH2_M  (AHB_DMA_TX_CRC_EN_WR_DATA_CH2_V << AHB_DMA_TX_CRC_EN_WR_DATA_CH2_S)
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH2_S  0
+
+/** AHB_DMA_TX_CRC_EN_ADDR_CH2_REG register
+ *  This register is used to config ch2 crc en addr
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x320)
+/** AHB_DMA_TX_CRC_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH2_M  (AHB_DMA_TX_CRC_EN_ADDR_CH2_V << AHB_DMA_TX_CRC_EN_ADDR_CH2_S)
+#define AHB_DMA_TX_CRC_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH2_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x324)
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2    0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_M  (AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_V << AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_S)
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_V  0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x328)
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_M  (AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_V << AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_S)
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG register
+ *  TX channel 2 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x32c)
+/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel2
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2    0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_M  (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_S)
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_V  0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_S  0
+
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH2_REG register
+ *  TX channel 2 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x330)
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_M  (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_S  0
+
+/** AHB_DMA_IN_CRC_INIT_DATA_CH0_REG register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x334)
+/** AHB_DMA_IN_CRC_INIT_DATA_CH0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH0_M  (AHB_DMA_IN_CRC_INIT_DATA_CH0_V << AHB_DMA_IN_CRC_INIT_DATA_CH0_S)
+#define AHB_DMA_IN_CRC_INIT_DATA_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH0_S  0
+
+/** AHB_DMA_RX_CRC_WIDTH_CH0_REG register
+ *  This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x338)
+/** AHB_DMA_RX_CRC_WIDTH_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH0    0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH0_M  (AHB_DMA_RX_CRC_WIDTH_CH0_V << AHB_DMA_RX_CRC_WIDTH_CH0_S)
+#define AHB_DMA_RX_CRC_WIDTH_CH0_V  0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH0_S  0
+/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0    (BIT(2))
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_M  (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_S)
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_V  0x00000001U
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_S  2
+
+/** AHB_DMA_IN_CRC_CLEAR_CH0_REG register
+ *  This register is used to clear ch0 crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x33c)
+/** AHB_DMA_IN_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH0    (BIT(0))
+#define AHB_DMA_IN_CRC_CLEAR_CH0_M  (AHB_DMA_IN_CRC_CLEAR_CH0_V << AHB_DMA_IN_CRC_CLEAR_CH0_S)
+#define AHB_DMA_IN_CRC_CLEAR_CH0_V  0x00000001U
+#define AHB_DMA_IN_CRC_CLEAR_CH0_S  0
+
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH0_REG register
+ *  This register is used to store ch0 crc result
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x340)
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH0_M  (AHB_DMA_IN_CRC_FINAL_RESULT_CH0_V << AHB_DMA_IN_CRC_FINAL_RESULT_CH0_S)
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH0_S  0
+
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH0_REG register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x344)
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH0    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH0_M  (AHB_DMA_RX_CRC_EN_WR_DATA_CH0_V << AHB_DMA_RX_CRC_EN_WR_DATA_CH0_S)
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH0_S  0
+
+/** AHB_DMA_RX_CRC_EN_ADDR_CH0_REG register
+ *  This register is used to config ch0 crc en addr
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x348)
+/** AHB_DMA_RX_CRC_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH0_M  (AHB_DMA_RX_CRC_EN_ADDR_CH0_V << AHB_DMA_RX_CRC_EN_ADDR_CH0_S)
+#define AHB_DMA_RX_CRC_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH0_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x34c)
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0    0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_M  (AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_V << AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_S)
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_V  0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x350)
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_M  (AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_V << AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_S)
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG register
+ *  RX channel 0 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x354)
+/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel0
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0    0x0000000FU
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_M  (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S)
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V  0x0000000FU
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S  0
+
+/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG register
+ *  RX channel 0 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358)
+/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_M  (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S  0
+
+/** AHB_DMA_IN_CRC_INIT_DATA_CH1_REG register
+ *  This register is used to config ch1 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x35c)
+/** AHB_DMA_IN_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH1_M  (AHB_DMA_IN_CRC_INIT_DATA_CH1_V << AHB_DMA_IN_CRC_INIT_DATA_CH1_S)
+#define AHB_DMA_IN_CRC_INIT_DATA_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH1_S  0
+
+/** AHB_DMA_RX_CRC_WIDTH_CH1_REG register
+ *  This register is used to confiig rx ch1 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x360)
+/** AHB_DMA_RX_CRC_WIDTH_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH1    0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH1_M  (AHB_DMA_RX_CRC_WIDTH_CH1_V << AHB_DMA_RX_CRC_WIDTH_CH1_S)
+#define AHB_DMA_RX_CRC_WIDTH_CH1_V  0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH1_S  0
+/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1    (BIT(2))
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_M  (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_S)
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_V  0x00000001U
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_S  2
+
+/** AHB_DMA_IN_CRC_CLEAR_CH1_REG register
+ *  This register is used to clear ch1 crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x364)
+/** AHB_DMA_IN_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH1    (BIT(0))
+#define AHB_DMA_IN_CRC_CLEAR_CH1_M  (AHB_DMA_IN_CRC_CLEAR_CH1_V << AHB_DMA_IN_CRC_CLEAR_CH1_S)
+#define AHB_DMA_IN_CRC_CLEAR_CH1_V  0x00000001U
+#define AHB_DMA_IN_CRC_CLEAR_CH1_S  0
+
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH1_REG register
+ *  This register is used to store ch1 crc result
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x368)
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH1_M  (AHB_DMA_IN_CRC_FINAL_RESULT_CH1_V << AHB_DMA_IN_CRC_FINAL_RESULT_CH1_S)
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH1_S  0
+
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH1_REG register
+ *  This resister is used to config ch1 crc en for every bit
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x36c)
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH1    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH1_M  (AHB_DMA_RX_CRC_EN_WR_DATA_CH1_V << AHB_DMA_RX_CRC_EN_WR_DATA_CH1_S)
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH1_S  0
+
+/** AHB_DMA_RX_CRC_EN_ADDR_CH1_REG register
+ *  This register is used to config ch1 crc en addr
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x370)
+/** AHB_DMA_RX_CRC_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH1_M  (AHB_DMA_RX_CRC_EN_ADDR_CH1_V << AHB_DMA_RX_CRC_EN_ADDR_CH1_S)
+#define AHB_DMA_RX_CRC_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH1_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x374)
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1    0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_M  (AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_V << AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_S)
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_V  0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x378)
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_M  (AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_V << AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_S)
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG register
+ *  RX channel 1 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x37c)
+/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel1
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1    0x0000000FU
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_M  (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S)
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V  0x0000000FU
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S  0
+
+/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG register
+ *  RX channel 1 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380)
+/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_M  (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S  0
+
+/** AHB_DMA_IN_CRC_INIT_DATA_CH2_REG register
+ *  This register is used to config ch2 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x384)
+/** AHB_DMA_IN_CRC_INIT_DATA_CH2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH2_M  (AHB_DMA_IN_CRC_INIT_DATA_CH2_V << AHB_DMA_IN_CRC_INIT_DATA_CH2_S)
+#define AHB_DMA_IN_CRC_INIT_DATA_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH2_S  0
+
+/** AHB_DMA_RX_CRC_WIDTH_CH2_REG register
+ *  This register is used to confiig rx ch2 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x388)
+/** AHB_DMA_RX_CRC_WIDTH_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH2    0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH2_M  (AHB_DMA_RX_CRC_WIDTH_CH2_V << AHB_DMA_RX_CRC_WIDTH_CH2_S)
+#define AHB_DMA_RX_CRC_WIDTH_CH2_V  0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH2_S  0
+/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2    (BIT(2))
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_M  (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_S)
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_V  0x00000001U
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_S  2
+
+/** AHB_DMA_IN_CRC_CLEAR_CH2_REG register
+ *  This register is used to clear ch2 crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x38c)
+/** AHB_DMA_IN_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH2    (BIT(0))
+#define AHB_DMA_IN_CRC_CLEAR_CH2_M  (AHB_DMA_IN_CRC_CLEAR_CH2_V << AHB_DMA_IN_CRC_CLEAR_CH2_S)
+#define AHB_DMA_IN_CRC_CLEAR_CH2_V  0x00000001U
+#define AHB_DMA_IN_CRC_CLEAR_CH2_S  0
+
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH2_REG register
+ *  This register is used to store ch2 crc result
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH2_REG (DR_REG_AHB_DMA_BASE + 0x390)
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH2_M  (AHB_DMA_IN_CRC_FINAL_RESULT_CH2_V << AHB_DMA_IN_CRC_FINAL_RESULT_CH2_S)
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH2_S  0
+
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH2_REG register
+ *  This resister is used to config ch2 crc en for every bit
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x394)
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH2    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH2_M  (AHB_DMA_RX_CRC_EN_WR_DATA_CH2_V << AHB_DMA_RX_CRC_EN_WR_DATA_CH2_S)
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH2_S  0
+
+/** AHB_DMA_RX_CRC_EN_ADDR_CH2_REG register
+ *  This register is used to config ch2 crc en addr
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x398)
+/** AHB_DMA_RX_CRC_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH2_M  (AHB_DMA_RX_CRC_EN_ADDR_CH2_V << AHB_DMA_RX_CRC_EN_ADDR_CH2_S)
+#define AHB_DMA_RX_CRC_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH2_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x39c)
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2    0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_M  (AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_V << AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_S)
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_V  0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a0)
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_M  (AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_V << AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_S)
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG register
+ *  RX channel 2 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a4)
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel2
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2    0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_M  (AHB_DMA_RX_CH_ARB_WEIGH_CH2_V << AHB_DMA_RX_CH_ARB_WEIGH_CH2_S)
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_V  0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_S  0
+
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG register
+ *  RX channel 2 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a8)
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M  (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S)
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S  0
+
+/** AHB_DMA_IN_LINK_ADDR_CH0_REG register
+ *  Link list descriptor address configuration of RX channel 0
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3ac)
+/** AHB_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address
+ */
+#define AHB_DMA_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH0_M  (AHB_DMA_INLINK_ADDR_CH0_V << AHB_DMA_INLINK_ADDR_CH0_S)
+#define AHB_DMA_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_LINK_ADDR_CH1_REG register
+ *  Link list descriptor address configuration of RX channel 1
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3b0)
+/** AHB_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address
+ */
+#define AHB_DMA_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH1_M  (AHB_DMA_INLINK_ADDR_CH1_V << AHB_DMA_INLINK_ADDR_CH1_S)
+#define AHB_DMA_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_LINK_ADDR_CH2_REG register
+ *  Link list descriptor address configuration of RX channel 2
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3b4)
+/** AHB_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address
+ */
+#define AHB_DMA_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH2_M  (AHB_DMA_INLINK_ADDR_CH2_V << AHB_DMA_INLINK_ADDR_CH2_S)
+#define AHB_DMA_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_LINK_ADDR_CH0_REG register
+ *  Link list descriptor address configuration of TX channel 0
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3b8)
+/** AHB_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH0_M  (AHB_DMA_OUTLINK_ADDR_CH0_V << AHB_DMA_OUTLINK_ADDR_CH0_S)
+#define AHB_DMA_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_LINK_ADDR_CH1_REG register
+ *  Link list descriptor address configuration of TX channel 1
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3bc)
+/** AHB_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH1_M  (AHB_DMA_OUTLINK_ADDR_CH1_V << AHB_DMA_OUTLINK_ADDR_CH1_S)
+#define AHB_DMA_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_LINK_ADDR_CH2_REG register
+ *  Link list descriptor address configuration of TX channel 2
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3c0)
+/** AHB_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH2_M  (AHB_DMA_OUTLINK_ADDR_CH2_V << AHB_DMA_OUTLINK_ADDR_CH2_S)
+#define AHB_DMA_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH2_S  0
+
+/** AHB_DMA_INTR_MEM_START_ADDR_REG register
+ *  Accessible address space start address configuration register
+ */
+#define AHB_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c4)
+/** AHB_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Accessible address space start address configuration register
+ */
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_M  (AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S)
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** AHB_DMA_INTR_MEM_END_ADDR_REG register
+ *  Accessible address space end address configuration register
+ */
+#define AHB_DMA_INTR_MEM_END_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c8)
+/** AHB_DMA_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the end address of accessible address space.
+ */
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_M  (AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S)
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** AHB_DMA_ARB_TIMEOUT_TX_REG register
+ *  TX arbitration timeout configuration register
+ */
+#define AHB_DMA_ARB_TIMEOUT_TX_REG (DR_REG_AHB_DMA_BASE + 0x3cc)
+/** AHB_DMA_ARB_TIMEOUT_TX : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the time slot for TX. Measurement unit: AHB bus clock cycle.
+ */
+#define AHB_DMA_ARB_TIMEOUT_TX    0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_TX_M  (AHB_DMA_ARB_TIMEOUT_TX_V << AHB_DMA_ARB_TIMEOUT_TX_S)
+#define AHB_DMA_ARB_TIMEOUT_TX_V  0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_TX_S  0
+
+/** AHB_DMA_ARB_TIMEOUT_RX_REG register
+ *  RX arbitration timeout configuration register
+ */
+#define AHB_DMA_ARB_TIMEOUT_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d0)
+/** AHB_DMA_ARB_TIMEOUT_RX : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the time slot for RX. Measurement unit: AHB bus clock cycle.
+ */
+#define AHB_DMA_ARB_TIMEOUT_RX    0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_RX_M  (AHB_DMA_ARB_TIMEOUT_RX_V << AHB_DMA_ARB_TIMEOUT_RX_S)
+#define AHB_DMA_ARB_TIMEOUT_RX_V  0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_RX_S  0
+
+/** AHB_DMA_WEIGHT_EN_TX_REG register
+ *  TX weight arbitration enable register
+ */
+#define AHB_DMA_WEIGHT_EN_TX_REG (DR_REG_AHB_DMA_BASE + 0x3d4)
+/** AHB_DMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable weight arbitration for TX.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_WEIGHT_EN_TX    (BIT(0))
+#define AHB_DMA_WEIGHT_EN_TX_M  (AHB_DMA_WEIGHT_EN_TX_V << AHB_DMA_WEIGHT_EN_TX_S)
+#define AHB_DMA_WEIGHT_EN_TX_V  0x00000001U
+#define AHB_DMA_WEIGHT_EN_TX_S  0
+
+/** AHB_DMA_WEIGHT_EN_RX_REG register
+ *  RX weight arbitration enable register
+ */
+#define AHB_DMA_WEIGHT_EN_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d8)
+/** AHB_DMA_WEIGHT_EN_RX : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable weight arbitration for RX.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_WEIGHT_EN_RX    (BIT(0))
+#define AHB_DMA_WEIGHT_EN_RX_M  (AHB_DMA_WEIGHT_EN_RX_V << AHB_DMA_WEIGHT_EN_RX_S)
+#define AHB_DMA_WEIGHT_EN_RX_V  0x00000001U
+#define AHB_DMA_WEIGHT_EN_RX_S  0
+
+/** AHB_DMA_ARB_TIMEOUT_REG register
+ *  TX arbitration timeout configuration register
+ */
+#define AHB_DMA_ARB_TIMEOUT_REG (DR_REG_AHB_DMA_BASE + 0x3dc)
+/** AHB_DMA_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the time slot. Measurement unit: AHB bus clock cycle.
+ */
+#define AHB_DMA_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_NUM_M  (AHB_DMA_ARB_TIMEOUT_NUM_V << AHB_DMA_ARB_TIMEOUT_NUM_S)
+#define AHB_DMA_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_NUM_S  0
+
+/** AHB_DMA_WEIGHT_EN_REG register
+ *  TX weight arbitration enable register
+ */
+#define AHB_DMA_WEIGHT_EN_REG (DR_REG_AHB_DMA_BASE + 0x400)
+/** AHB_DMA_WEIGHT_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable weight arbitration.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_WEIGHT_EN    (BIT(0))
+#define AHB_DMA_WEIGHT_EN_M  (AHB_DMA_WEIGHT_EN_V << AHB_DMA_WEIGHT_EN_S)
+#define AHB_DMA_WEIGHT_EN_V  0x00000001U
+#define AHB_DMA_WEIGHT_EN_S  0
+
+/** AHB_DMA_MODULE_CLK_EN_REG register
+ *  Module clock force on register
+ */
+#define AHB_DMA_MODULE_CLK_EN_REG (DR_REG_AHB_DMA_BASE + 0x404)
+/** AHB_DMA_AHB_APB_SYNC_CLK_EN : R/W; bitpos: [2:0]; default: 7;
+ *  Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n:
+ *  0 : Not force on ahb_apb_sync n clock
+ *  1 : Force on ahb_apb_sync n clock
+ */
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN    0x00000007U
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN_M  (AHB_DMA_AHB_APB_SYNC_CLK_EN_V << AHB_DMA_AHB_APB_SYNC_CLK_EN_S)
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN_V  0x00000007U
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN_S  0
+/** AHB_DMA_OUT_DSCR_CLK_EN : R/W; bitpos: [5:3]; default: 7;
+ *  Configures whether to force on out_dscr 2~0 module clock. For bit n:
+ *  0 : Not force on out_dscr n clock
+ *  1 : Force on out_dscr n clock
+ */
+#define AHB_DMA_OUT_DSCR_CLK_EN    0x00000007U
+#define AHB_DMA_OUT_DSCR_CLK_EN_M  (AHB_DMA_OUT_DSCR_CLK_EN_V << AHB_DMA_OUT_DSCR_CLK_EN_S)
+#define AHB_DMA_OUT_DSCR_CLK_EN_V  0x00000007U
+#define AHB_DMA_OUT_DSCR_CLK_EN_S  3
+/** AHB_DMA_OUT_CTRL_CLK_EN : R/W; bitpos: [8:6]; default: 7;
+ *  Configures whether to force on out_ctrl 2~0 module clock. For bit n:
+ *  0 : Not force on out_ctrl n clock
+ *  1 : Force on out_ctrl n clock
+ */
+#define AHB_DMA_OUT_CTRL_CLK_EN    0x00000007U
+#define AHB_DMA_OUT_CTRL_CLK_EN_M  (AHB_DMA_OUT_CTRL_CLK_EN_V << AHB_DMA_OUT_CTRL_CLK_EN_S)
+#define AHB_DMA_OUT_CTRL_CLK_EN_V  0x00000007U
+#define AHB_DMA_OUT_CTRL_CLK_EN_S  6
+/** AHB_DMA_IN_DSCR_CLK_EN : R/W; bitpos: [11:9]; default: 7;
+ *  Configures whether to force on in_dscr 2~0 module clock. For bit n:
+ *  0 : Not force on in_dscr n clock
+ *  1 : Force on in_dscr n clock
+ */
+#define AHB_DMA_IN_DSCR_CLK_EN    0x00000007U
+#define AHB_DMA_IN_DSCR_CLK_EN_M  (AHB_DMA_IN_DSCR_CLK_EN_V << AHB_DMA_IN_DSCR_CLK_EN_S)
+#define AHB_DMA_IN_DSCR_CLK_EN_V  0x00000007U
+#define AHB_DMA_IN_DSCR_CLK_EN_S  9
+/** AHB_DMA_IN_CTRL_CLK_EN : R/W; bitpos: [14:12]; default: 7;
+ *  Configures whether to force on in_ctrl 2~0 module clock. For bit n:
+ *  0 : Not force on in_ctrl n clock
+ *  1 : Force on in_ctrl n clock
+ */
+#define AHB_DMA_IN_CTRL_CLK_EN    0x00000007U
+#define AHB_DMA_IN_CTRL_CLK_EN_M  (AHB_DMA_IN_CTRL_CLK_EN_V << AHB_DMA_IN_CTRL_CLK_EN_S)
+#define AHB_DMA_IN_CTRL_CLK_EN_V  0x00000007U
+#define AHB_DMA_IN_CTRL_CLK_EN_S  12
+/** AHB_DMA_CMD_ARB_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether to force on cmd_arb module clock.
+ *  0 : Not force on cmd_arb clock
+ *  1 : Force on cmd_arb clock
+ */
+#define AHB_DMA_CMD_ARB_CLK_EN    (BIT(27))
+#define AHB_DMA_CMD_ARB_CLK_EN_M  (AHB_DMA_CMD_ARB_CLK_EN_V << AHB_DMA_CMD_ARB_CLK_EN_S)
+#define AHB_DMA_CMD_ARB_CLK_EN_V  0x00000001U
+#define AHB_DMA_CMD_ARB_CLK_EN_S  27
+/** AHB_DMA_AHBINF_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether to force on ahbinf module clock.
+ *  0 : Not force on ahbinf clock
+ *  1 : Force on ahbinf clock
+ */
+#define AHB_DMA_AHBINF_CLK_EN    (BIT(28))
+#define AHB_DMA_AHBINF_CLK_EN_M  (AHB_DMA_AHBINF_CLK_EN_V << AHB_DMA_AHBINF_CLK_EN_S)
+#define AHB_DMA_AHBINF_CLK_EN_V  0x00000001U
+#define AHB_DMA_AHBINF_CLK_EN_S  28
+
+/** AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG register
+ *  AHB response error status 0 register
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG (DR_REG_AHB_DMA_BASE + 0x408)
+/** AHB_DMA_AHBINF_RESP_ERR_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the AHB response error.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR    0xFFFFFFFFU
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR_M  (AHB_DMA_AHBINF_RESP_ERR_ADDR_V << AHB_DMA_AHBINF_RESP_ERR_ADDR_S)
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR_V  0xFFFFFFFFU
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR_S  0
+
+/** AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG register
+ *  AHB response error status 1 register
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG (DR_REG_AHB_DMA_BASE + 0x40c)
+/** AHB_DMA_AHBINF_RESP_ERR_WR : RO; bitpos: [0]; default: 0;
+ *  Represents the AHB response error is write request.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_WR    (BIT(0))
+#define AHB_DMA_AHBINF_RESP_ERR_WR_M  (AHB_DMA_AHBINF_RESP_ERR_WR_V << AHB_DMA_AHBINF_RESP_ERR_WR_S)
+#define AHB_DMA_AHBINF_RESP_ERR_WR_V  0x00000001U
+#define AHB_DMA_AHBINF_RESP_ERR_WR_S  0
+/** AHB_DMA_AHBINF_RESP_ERR_ID : RO; bitpos: [4:1]; default: 15;
+ *  Represents the AHB response error request id.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_ID    0x0000000FU
+#define AHB_DMA_AHBINF_RESP_ERR_ID_M  (AHB_DMA_AHBINF_RESP_ERR_ID_V << AHB_DMA_AHBINF_RESP_ERR_ID_S)
+#define AHB_DMA_AHBINF_RESP_ERR_ID_V  0x0000000FU
+#define AHB_DMA_AHBINF_RESP_ERR_ID_S  1
+/** AHB_DMA_AHBINF_RESP_ERR_CH_ID : RO; bitpos: [7:5]; default: 0;
+ *  Represents the AHB response error request channel id.bit[2]=1:TX channel.
+ *  bit[2]=0:RX channel.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID    0x00000007U
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_M  (AHB_DMA_AHBINF_RESP_ERR_CH_ID_V << AHB_DMA_AHBINF_RESP_ERR_CH_ID_S)
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_V  0x00000007U
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_S  5
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH0_REG register
+ *  RX_done Inlink descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x410)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_M  (AHB_DMA_IN_DONE_DES_ADDR_CH0_V << AHB_DMA_IN_DONE_DES_ADDR_CH0_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG register
+ *  TX done outlink descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x414)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH0_V << AHB_DMA_OUT_DONE_DES_ADDR_CH0_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH1_REG register
+ *  RX_done Inlink descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x418)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_M  (AHB_DMA_IN_DONE_DES_ADDR_CH1_V << AHB_DMA_IN_DONE_DES_ADDR_CH1_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG register
+ *  TX done outlink descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x41c)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH1_V << AHB_DMA_OUT_DONE_DES_ADDR_CH1_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH2_REG register
+ *  RX_done Inlink descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x420)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_M  (AHB_DMA_IN_DONE_DES_ADDR_CH2_V << AHB_DMA_IN_DONE_DES_ADDR_CH2_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG register
+ *  TX done outlink descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x424)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH2_V << AHB_DMA_OUT_DONE_DES_ADDR_CH2_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_struct.h
new file mode 100644
index 0000000000..eb66f78455
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_struct.h
@@ -0,0 +1,1411 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt Registers */
+/** Type of in_int_raw_chn register
+ *  Raw status interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw: 1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+         *  turns to high level when the last data pointed by one inlink descriptor has been
+         *  received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw: 1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when data error is detected only in the
+         *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+         *  interrupt is reserved.
+         */
+        uint32_t in_err_eof_chn_int_raw: 1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+         *  including owner error and the second and third word error of inlink descriptor for
+         *  Rx channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw: 1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+         *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+         */
+        uint32_t in_dscr_empty_chn_int_raw: 1;
+        /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_ovf_chn_int_raw: 1;
+        /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_udf_chn_int_raw: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} ahb_dma_in_int_raw_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st: 1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st: 1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st: 1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st: 1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st: 1;
+        /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_chn_int_st: 1;
+        /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_chn_int_st: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} ahb_dma_in_int_st_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena: 1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena: 1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena: 1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena: 1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena: 1;
+        /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_chn_int_ena: 1;
+        /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_chn_int_ena: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} ahb_dma_in_int_ena_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr: 1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr: 1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr: 1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr: 1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr: 1;
+        /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_chn_int_clr: 1;
+        /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_chn_int_clr: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} ahb_dma_in_int_clr_chn_reg_t;
+
+/** Type of out_int_raw_chn register
+ *  Raw status interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_chn_int_raw: 1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_chn_int_raw: 1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+         *  including owner error and the second and third word error of outlink descriptor for
+         *  Tx channel 0.
+         */
+        uint32_t out_dscr_err_chn_int_raw: 1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_chn_int_raw: 1;
+        /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
+         *  overflow.
+         */
+        uint32_t outfifo_ovf_chn_int_raw: 1;
+        /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
+         *  underflow.
+         */
+        uint32_t outfifo_udf_chn_int_raw: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_out_int_raw_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st: 1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st: 1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st: 1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st: 1;
+        /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_chn_int_st: 1;
+        /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_chn_int_st: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_out_int_st_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena: 1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena: 1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena: 1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena: 1;
+        /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_chn_int_ena: 1;
+        /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_chn_int_ena: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_out_int_ena_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr: 1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr: 1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr: 1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr: 1;
+        /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_chn_int_clr: 1;
+        /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_chn_int_clr: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_out_int_clr_chn_reg_t;
+
+/** Group: Debug Registers */
+/** Type of ahb_test register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** ahb_testmode : R/W; bitpos: [2:0]; default: 0;
+         *  reserved
+         */
+        uint32_t ahb_testmode: 3;
+        uint32_t reserved_3: 1;
+        /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
+         *  reserved
+         */
+        uint32_t ahb_testaddr: 2;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_ahb_test_reg_t;
+
+/** Group: Configuration Registers */
+/** Type of misc_conf register
+ *  MISC register
+ */
+typedef union {
+    struct {
+        /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0;
+         *  Set this bit then clear this bit to reset the internal ahb FSM.
+         */
+        uint32_t ahbm_rst_inter: 1;
+        uint32_t reserved_1: 1;
+        /** arb_pri_dis : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to disable priority arbitration function.
+         */
+        uint32_t arb_pri_dis: 1;
+        /** clk_en : R/W; bitpos: [3]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_misc_conf_reg_t;
+
+/** Type of in_conf0_chn register
+ *  Configure 0 register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer.
+         */
+        uint32_t in_rst_chn: 1;
+        /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn: 1;
+        /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t indscr_burst_en_chn: 1;
+        /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
+         *  when accessing internal SRAM.
+         */
+        uint32_t in_data_burst_en_chn: 1;
+        /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+         *  AHB_DMA.
+         */
+        uint32_t mem_trans_en_chn: 1;
+        /** in_etm_en_chn : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+         *  task.
+         */
+        uint32_t in_etm_en_chn: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_in_conf0_chn_reg_t;
+
+/** Type of in_conf1_chn register
+ *  Configure 1 register of Rx channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} ahb_dma_in_conf1_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Pop control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
+         *  This register stores the data popping from AHB_DMA FIFO.
+         */
+        uint32_t infifo_rdata_chn: 12;
+        /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
+         *  Set this bit to pop data from AHB_DMA FIFO.
+         */
+        uint32_t infifo_pop_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} ahb_dma_in_pop_chn_reg_t;
+
+/** Type of in_link_chn register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_chn: 1;
+        /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn: 1;
+        /** inlink_start_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn: 1;
+        /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn: 1;
+        /** inlink_park_chn : RO; bitpos: [4]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} ahb_dma_in_link_chn_reg_t;
+
+/** Type of out_conf1_chn register
+ *  Configure 1 register of Tx channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} ahb_dma_out_conf1_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Push control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
+         *  This register stores the data that need to be pushed into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_wdata_chn: 9;
+        /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
+         *  Set this bit to push data into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_push_chn: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} ahb_dma_out_push_chn_reg_t;
+
+/** Type of out_link_chn register
+ *  Link descriptor configure and control register of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn: 1;
+        /** outlink_start_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn: 1;
+        /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn: 1;
+        /** outlink_park_chn : RO; bitpos: [3]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_out_link_chn_reg_t;
+
+/** Type of out_conf0_chn register
+ *  Configure 0 register of Tx channel 1
+ */
+typedef union {
+    struct {
+        /** out_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_chn: 1;
+        /** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_chn: 1;
+        /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_chn: 1;
+        /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is
+         *  generated when data need to transmit has been popped from FIFO in AHB_DMA
+         */
+        uint32_t out_eof_mode_chn: 1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_chn: 1;
+        /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data
+         *  when accessing internal SRAM.
+         */
+        uint32_t out_data_burst_en_chn: 1;
+        /** out_etm_en_chn : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_chn: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} ahb_dma_out_conf0_chn_reg_t;
+
+/** Type of out_crc_init_data_chn register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of tx crc initial value
+         */
+        uint32_t out_crc_init_data_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_init_data_chn_reg_t;
+
+/** Type of tx_crc_width_chn register
+ *  This register is used to config tx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_width_chn: 2;
+        /** tx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_latch_flag_chn: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_width_chn_reg_t;
+
+/** Type of out_crc_clear_chn register
+ *  This register is used to clear ch0 crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of tx crc result
+         */
+        uint32_t out_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_clear_chn_reg_t;
+
+/** Type of out_crc_final_result_chn register
+ *  This register is used to store ch0 crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of tx
+         */
+        uint32_t out_crc_final_result_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_final_result_chn_reg_t;
+
+/** Type of tx_crc_en_wr_data_chn register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable tx ch0 crc 32bit on/off
+         */
+        uint32_t tx_crc_en_wr_data_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_en_addr_chn register
+ *  This register is used to config ch0 crc en addr
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_en_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_en_addr_chn_reg_t;
+
+/** Type of tx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_wr_data_chn: 8;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_data_en_addr_chn_reg_t;
+
+/** Type of tx_ch_arb_weigh_chn register
+ *  This register is used to config ch0 arbiter weigh
+ */
+typedef union {
+    struct {
+        /** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_ch_arb_weigh_chn: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_tx_ch_arb_weigh_chn_reg_t;
+
+/** Type of tx_arb_weigh_opt_dir_chn register
+ *  This register is used to config off or on weigh optimization
+ */
+typedef union {
+    struct {
+        /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t;
+
+/** Type of in_crc_init_data_chn register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of rx crc initial value
+         */
+        uint32_t in_crc_init_data_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_init_data_chn_reg_t;
+
+/** Type of rx_crc_width_chn register
+ *  This register is used to config rx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_width_chn: 2;
+        /** rx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_latch_flag_chn: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_width_chn_reg_t;
+
+/** Type of in_crc_clear_chn register
+ *  This register is used to clear ch0 crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of rx crc result
+         */
+        uint32_t in_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_clear_chn_reg_t;
+
+/** Type of in_crc_final_result_chn register
+ *  This register is used to store ch0 crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of rx
+         */
+        uint32_t in_crc_final_result_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_final_result_chn_reg_t;
+
+/** Type of rx_crc_en_wr_data_chn register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable rx ch0 crc 32bit on/off
+         */
+        uint32_t rx_crc_en_wr_data_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_en_addr_chn register
+ *  This register is used to config ch0 crc en addr
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_en_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_en_addr_chn_reg_t;
+
+/** Type of rx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_wr_data_chn: 8;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_data_en_addr_chn_reg_t;
+
+/** Type of rx_ch_arb_weigh_chn register
+ *  This register is used to config ch0 arbiter weigh
+ */
+typedef union {
+    struct {
+        /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_ch_arb_weigh_chn: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_rx_ch_arb_weigh_chn_reg_t;
+
+/** Type of rx_arb_weigh_opt_dir_chn register
+ *  This register is used to config off or on weigh optimization
+ */
+typedef union {
+    struct {
+        /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t;
+
+/** Type of in_link_addr_chn register
+ *  Link descriptor configure of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 32 least significant bits of the first inlink descriptor's
+         *  address.
+         */
+        uint32_t inlink_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_link_addr_chn_reg_t;
+
+/** Type of out_link_addr_chn register
+ *  Link descriptor configure of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 32 least significant bits of the first outlink
+         *  descriptor's address.
+         */
+        uint32_t outlink_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_link_addr_chn_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr: 32;
+    };
+    uint32_t val;
+} ahb_dma_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr: 32;
+    };
+    uint32_t val;
+} ahb_dma_intr_mem_end_addr_reg_t;
+
+/** Type of arb_timeout_tx register
+ *  This retister is used to config arbiter time slice for tx dir
+ */
+typedef union {
+    struct {
+        /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to config arbiter time out value
+         */
+        uint32_t arb_timeout_tx: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_tx_reg_t;
+
+/** Type of arb_timeout_rx register
+ *  This retister is used to config arbiter time slice for rx dir
+ */
+typedef union {
+    struct {
+        /** arb_timeout_rx : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to config arbiter time out value
+         */
+        uint32_t arb_timeout_rx: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_rx_reg_t;
+
+/** Type of weight_en_tx register
+ *  This register is used to config arbiter weigh function to on or off for tx dir
+ */
+typedef union {
+    struct {
+        /** weight_en_tx : R/W; bitpos: [0]; default: 0;
+         *  This register is used to config arbiter weight function  off/on
+         */
+        uint32_t weight_en_tx: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_tx_reg_t;
+
+/** Type of weight_en_rx register
+ *  This register is used to config arbiter weigh function to on or off for rx dir
+ */
+typedef union {
+    struct {
+        /** weight_en_rx : R/W; bitpos: [0]; default: 0;
+         *  This register is used to config arbiter weight function  off/on
+         */
+        uint32_t weight_en_rx: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_rx_reg_t;
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36712768;
+         *  register version.
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} ahb_dma_date_reg_t;
+
+/** Group: Status Registers */
+/** Type of infifo_status_chn register
+ *  Receive FIFO status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_full_chn : RO; bitpos: [0]; default: 1;
+         *  L1 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_full_chn: 1;
+        /** infifo_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L1 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_empty_chn: 1;
+        /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_cnt_chn: 6;
+        uint32_t reserved_8: 15;
+        /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn: 1;
+        /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn: 1;
+        /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn: 1;
+        /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn: 1;
+        /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_chn: 1;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} ahb_dma_infifo_status_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Receive status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn: 18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn: 2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn: 3;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} ahb_dma_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Inlink descriptor address when EOF occurs of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Inlink descriptor address when errors occur of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data. Only used when peripheral is UHCI0.
+         */
+        uint32_t in_err_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Current inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current inlink descriptor x.
+         */
+        uint32_t inlink_dscr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  The last inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  The second-to-last inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf1_chn_reg_t;
+
+/** Type of outfifo_status_chn register
+ *  Transmit FIFO status of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_full_chn : RO; bitpos: [0]; default: 0;
+         *  L1 Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_chn: 1;
+        /** outfifo_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L1 Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_chn: 1;
+        /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_chn: 6;
+        uint32_t reserved_8: 15;
+        /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn: 1;
+        /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn: 1;
+        /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn: 1;
+        /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn: 1;
+        uint32_t reserved_27: 5;
+    };
+    uint32_t val;
+} ahb_dma_outfifo_status_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Transmit status of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn: 18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_chn: 2;
+        /** out_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_chn: 3;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} ahb_dma_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Outlink descriptor address when EOF occurs of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_eof_bfr_des_addr_chn register
+ *  The last outlink descriptor address when EOF occurs of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor before the last outlink
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_bfr_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Current inlink descriptor address of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current outlink descriptor y.
+         */
+        uint32_t outlink_dscr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  The last inlink descriptor address of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  The second-to-last inlink descriptor address of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor x-2.
+         */
+        uint32_t outlink_dscr_bf1_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf1_chn_reg_t;
+
+/** Group: Priority Registers */
+/** Type of in_pri_chn register
+ *  Priority register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+         */
+        uint32_t rx_pri_chn: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_in_pri_chn_reg_t;
+
+/** Type of out_pri_chn register
+ *  Priority register of Tx channel 0.
+ */
+typedef union {
+    struct {
+        /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Tx channel 0. The larger of the value the higher of the priority.
+         */
+        uint32_t tx_pri_chn: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_out_pri_chn_reg_t;
+
+/** Group: Peripheral Select Registers */
+/** Type of in_peri_sel_chn register
+ *  Peripheral selection of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2:
+         *  UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10:
+         *  RMT,11~15: Dummy
+         */
+        uint32_t peri_in_sel_chn: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_sel_chn_reg_t;
+
+/** Type of out_peri_sel_chn register
+ *  Peripheral selection of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2:
+         *  UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10:
+         *  RMT,11~15: Dummy
+         */
+        uint32_t peri_out_sel_chn: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_sel_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_in_int_raw_chn_reg_t raw;
+    volatile ahb_dma_in_int_st_chn_reg_t st;
+    volatile ahb_dma_in_int_ena_chn_reg_t ena;
+    volatile ahb_dma_in_int_clr_chn_reg_t clr;
+} ahb_dma_in_int_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_out_int_raw_chn_reg_t raw;
+    volatile ahb_dma_out_int_st_chn_reg_t st;
+    volatile ahb_dma_out_int_ena_chn_reg_t ena;
+    volatile ahb_dma_out_int_clr_chn_reg_t clr;
+} ahb_dma_out_int_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_in_conf0_chn_reg_t in_conf0;
+    volatile ahb_dma_in_conf1_chn_reg_t in_conf1;
+    volatile ahb_dma_infifo_status_chn_reg_t infifo_status;
+    volatile ahb_dma_in_pop_chn_reg_t in_pop;
+    volatile ahb_dma_in_link_chn_reg_t in_link;
+    volatile ahb_dma_in_state_chn_reg_t in_state;
+    volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
+    volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
+    volatile ahb_dma_in_dscr_chn_reg_t in_dscr;
+    volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
+    volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
+    volatile ahb_dma_in_pri_chn_reg_t in_pri;
+    volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel;
+} ahb_dma_in_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_out_conf0_chn_reg_t out_conf0;
+    volatile ahb_dma_out_conf1_chn_reg_t out_conf1;
+    volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status;
+    volatile ahb_dma_out_push_chn_reg_t out_push;
+    volatile ahb_dma_out_link_chn_reg_t out_link;
+    volatile ahb_dma_out_state_chn_reg_t out_state;
+    volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
+    volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
+    volatile ahb_dma_out_dscr_chn_reg_t out_dscr;
+    volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
+    volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
+    volatile ahb_dma_out_pri_chn_reg_t out_pri;
+    volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel;
+} ahb_dma_out_chn_reg_t;
+
+typedef struct {
+    ahb_dma_in_crc_init_data_chn_reg_t crc_init_data;
+    ahb_dma_rx_crc_width_chn_reg_t crc_width;
+    ahb_dma_in_crc_clear_chn_reg_t crc_clear;
+    ahb_dma_in_crc_final_result_chn_reg_t crc_final_result;
+    ahb_dma_rx_crc_en_wr_data_chn_reg_t crc_en_wr_data;
+    ahb_dma_rx_crc_en_addr_chn_reg_t crc_en_addr;
+    ahb_dma_rx_crc_data_en_wr_data_chn_reg_t crc_data_en_wr_data;
+    ahb_dma_rx_crc_data_en_addr_chn_reg_t crc_data_en_addr;
+    ahb_dma_rx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
+    ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
+} ahb_dma_in_crc_arb_chn_reg_t;
+
+typedef struct {
+    ahb_dma_out_crc_init_data_chn_reg_t crc_init_data;
+    ahb_dma_tx_crc_width_chn_reg_t crc_width;
+    ahb_dma_out_crc_clear_chn_reg_t crc_clear;
+    ahb_dma_out_crc_final_result_chn_reg_t crc_final_result;
+    ahb_dma_tx_crc_en_wr_data_chn_reg_t crc_en_wr_data;
+    ahb_dma_tx_crc_en_addr_chn_reg_t crc_en_addr;
+    ahb_dma_tx_crc_data_en_wr_data_chn_reg_t crc_data_en_wr_data;
+    ahb_dma_tx_crc_data_en_addr_chn_reg_t crc_data_en_addr;
+    ahb_dma_tx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
+    ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
+} ahb_dma_out_crc_arb_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_in_chn_reg_t in;
+    uint32_t reserved_in[11];
+    volatile ahb_dma_out_chn_reg_t out;
+    uint32_t reserved_out[11];
+} ahb_dma_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_in_int_chn_reg_t in_intr[3];
+    volatile ahb_dma_out_int_chn_reg_t out_intr[3];
+    volatile ahb_dma_ahb_test_reg_t ahb_test;
+    volatile ahb_dma_misc_conf_reg_t misc_conf;
+    volatile ahb_dma_date_reg_t date;
+    uint32_t reserved_06c;
+    volatile ahb_dma_chn_reg_t channel[3];
+    uint32_t reserved_2b0[3];
+    volatile ahb_dma_out_crc_arb_chn_reg_t out_crc_arb[3];
+    volatile ahb_dma_in_crc_arb_chn_reg_t in_crc_arb[3];
+    volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr[3];
+    volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr[3];
+    volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx;
+    volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx;
+    volatile ahb_dma_weight_en_tx_reg_t weight_en_tx;
+    volatile ahb_dma_weight_en_rx_reg_t weight_en_rx;
+} ahb_dma_dev_t;
+
+extern ahb_dma_dev_t AHB_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ahb_dma_dev_t) == 0x3DC, "Invalid size of ahb_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/assist_debug_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/assist_debug_reg.h
new file mode 100644
index 0000000000..3cbd5c7c89
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/assist_debug_reg.h
@@ -0,0 +1,1399 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
+ *  core0 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
+
+/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
+ *  core0 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
+
+/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
+ *  core0 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
+
+/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
+ *  core0 monitor interrupt clr register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
+ *  core0 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 dram0 region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
+ *  core0 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 dram0 region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
+ *  core0 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 dram0 region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
+ *  core0 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 dram0 region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
+ *  core0 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 PIF region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
+ *  core0 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 PIF region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
+ *  core0 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 PIF region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
+ *  core0 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 PIF region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
+ *  core0 area pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
+/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  the stackpointer when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
+ *  core0 area sp status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
+/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  the PC when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
+ *  stack min value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
+/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  core0 sp region configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
+ *  stack max value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
+/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  core0 sp pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
+ *  stack monitor pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
+/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the PC when trigger stack monitor.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
+ *  record enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
+/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable record PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  recorded PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  recorded sp
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_iram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_iram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register2
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
+ *  reg_core_0_dram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  1
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register3
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
+ *  exception monitor status register4
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
+ *  exception monitor status register5
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
+ *  reg_core_0_dram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  1
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
+
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  cpu's lastpc before exception
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  cpu debug mode status, 1 means cpu enter debug mode.
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  cpu debug_module active status
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CORE_1_INTR_ENA_REG register
+ *  core1 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x80)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S  9
+
+/** ASSIST_DEBUG_CORE_1_INTR_RAW_REG register
+ *  core1 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x84)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S  9
+
+/** ASSIST_DEBUG_CORE_1_INTR_RLS_REG register
+ *  core1 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x88)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S  9
+
+/** ASSIST_DEBUG_CORE_1_INTR_CLR_REG register
+ *  core1 monitor interrupt clr register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8c)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S  9
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG register
+ *  core1 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x90)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 dram0 region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG register
+ *  core1 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 dram0 region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG register
+ *  core1 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x98)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 dram0 region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG register
+ *  core1 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x9c)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 dram0 region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG register
+ *  core1 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa0)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 PIF region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG register
+ *  core1 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa4)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 PIF region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG register
+ *  core1 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa8)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 PIF region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG register
+ *  core1 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xac)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 PIF region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PC_REG register
+ *  core1 area pc status register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb0)
+/** ASSIST_DEBUG_CORE_1_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  the stackpointer when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PC_M  (ASSIST_DEBUG_CORE_1_AREA_PC_V << ASSIST_DEBUG_CORE_1_AREA_PC_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PC_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_SP_REG register
+ *  core1 area sp status register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb4)
+/** ASSIST_DEBUG_CORE_1_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  the PC when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_SP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_SP_M  (ASSIST_DEBUG_CORE_1_AREA_SP_V << ASSIST_DEBUG_CORE_1_AREA_SP_S)
+#define ASSIST_DEBUG_CORE_1_AREA_SP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_SP_S  0
+
+/** ASSIST_DEBUG_CORE_1_SP_MIN_REG register
+ *  stack min value
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb8)
+/** ASSIST_DEBUG_CORE_1_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  core1 sp region configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MIN_M  (ASSIST_DEBUG_CORE_1_SP_MIN_V << ASSIST_DEBUG_CORE_1_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_1_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_SP_MAX_REG register
+ *  stack max value
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xbc)
+/** ASSIST_DEBUG_CORE_1_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  core1 sp pc status register
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MAX_M  (ASSIST_DEBUG_CORE_1_SP_MAX_V << ASSIST_DEBUG_CORE_1_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_1_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_SP_PC_REG register
+ *  stack monitor pc status register
+ */
+#define ASSIST_DEBUG_CORE_1_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc0)
+/** ASSIST_DEBUG_CORE_1_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the PC when trigger stack monitor.
+ */
+#define ASSIST_DEBUG_CORE_1_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_PC_M  (ASSIST_DEBUG_CORE_1_SP_PC_V << ASSIST_DEBUG_CORE_1_SP_PC_S)
+#define ASSIST_DEBUG_CORE_1_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_1_RCD_EN_REG register
+ *  record enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc4)
+/** ASSIST_DEBUG_CORE_1_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable record PC
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_1_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_1_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc8)
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  recorded PC
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0xcc)
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  recorded sp
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd0)
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_iram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  reg_core_1_iram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S  24
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
+ *  reg_core_1_iram0_recording_loadstore_0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S  25
+
+/** ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd4)
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_iram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  reg_core_1_iram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S  24
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
+ *  reg_core_1_iram0_recording_loadstore_1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S  25
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register2
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd8)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
+ *  reg_core_1_dram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S  0
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_1_dram0_recording_byteen_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S  1
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register3
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0xdc)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_dram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S  0
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG register
+ *  exception monitor status register4
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe0)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_1_dram0_recording_pc_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S  0
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG register
+ *  exception monitor status register5
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe4)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
+ *  reg_core_1_dram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S  0
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_1_dram0_recording_byteen_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S  1
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe8)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_dram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S  0
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0xec)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_1_dram0_recording_pc_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S  0
+
+/** ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0xf0)
+/** ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  cpu's lastpc before exception
+ */
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_1_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0xf4)
+/** ASSIST_DEBUG_CORE_1_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  cpu debug mode status, 1 means cpu enter debug mode.
+ */
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_1_DEBUG_MODE_V << ASSIST_DEBUG_CORE_1_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  cpu debug_module active status
+ */
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_0
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_1
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
+
+/** ASSIST_DEBUG_CLOCK_GATE_REG register
+ *  clock register
+ */
+#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108)
+/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 force on the clock gate
+ */
+#define ASSIST_DEBUG_CLK_EN    (BIT(0))
+#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
+#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
+#define ASSIST_DEBUG_CLK_EN_S  0
+
+/** ASSIST_DEBUG_DATE_REG register
+ *  version register
+ */
+#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
+/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
+ *  version register
+ */
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE    0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/assist_debug_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/assist_debug_struct.h
new file mode 100644
index 0000000000..3f040390f7
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/assist_debug_struct.h
@@ -0,0 +1,1318 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: monitor configuration registers */
+/** Type of core_0_intr_ena register
+ *  core0 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor enable
+         */
+        uint32_t core_0_area_dram0_0_rd_ena:1;
+        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor enable
+         */
+        uint32_t core_0_area_dram0_0_wr_ena:1;
+        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor enable
+         */
+        uint32_t core_0_area_dram0_1_rd_ena:1;
+        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor enable
+         */
+        uint32_t core_0_area_dram0_1_wr_ena:1;
+        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor enable
+         */
+        uint32_t core_0_area_pif_0_rd_ena:1;
+        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor enable
+         */
+        uint32_t core_0_area_pif_0_wr_ena:1;
+        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor enable
+         */
+        uint32_t core_0_area_pif_1_rd_ena:1;
+        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor enable
+         */
+        uint32_t core_0_area_pif_1_wr_ena:1;
+        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor enable
+         */
+        uint32_t core_0_sp_spill_min_ena:1;
+        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor enable
+         */
+        uint32_t core_0_sp_spill_max_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_ena_reg_t;
+
+/** Type of core_0_area_dram0_0_min register
+ *  core0 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 dram0 region0 start addr
+         */
+        uint32_t core_0_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_min_reg_t;
+
+/** Type of core_0_area_dram0_0_max register
+ *  core0 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 dram0 region0 end addr
+         */
+        uint32_t core_0_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_max_reg_t;
+
+/** Type of core_0_area_dram0_1_min register
+ *  core0 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 dram0 region1 start addr
+         */
+        uint32_t core_0_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_min_reg_t;
+
+/** Type of core_0_area_dram0_1_max register
+ *  core0 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 dram0 region1 end addr
+         */
+        uint32_t core_0_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_max_reg_t;
+
+/** Type of core_0_area_pif_0_min register
+ *  core0 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 PIF region0 start addr
+         */
+        uint32_t core_0_area_pif_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_min_reg_t;
+
+/** Type of core_0_area_pif_0_max register
+ *  core0 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 PIF region0 end addr
+         */
+        uint32_t core_0_area_pif_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_max_reg_t;
+
+/** Type of core_0_area_pif_1_min register
+ *  core0 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 PIF region1 start addr
+         */
+        uint32_t core_0_area_pif_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_min_reg_t;
+
+/** Type of core_0_area_pif_1_max register
+ *  core0 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 PIF region1 end addr
+         */
+        uint32_t core_0_area_pif_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_max_reg_t;
+
+/** Type of core_0_area_pc register
+ *  core0 area pc status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  the stackpointer when first touch region monitor interrupt
+         */
+        uint32_t core_0_area_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pc_reg_t;
+
+/** Type of core_0_area_sp register
+ *  core0 area sp status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  the PC when first touch region monitor interrupt
+         */
+        uint32_t core_0_area_sp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_sp_reg_t;
+
+/** Type of core_0_sp_min register
+ *  stack min value
+ */
+typedef union {
+    struct {
+        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  core0 sp region configuration register
+         */
+        uint32_t core_0_sp_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_min_reg_t;
+
+/** Type of core_0_sp_max register
+ *  stack max value
+ */
+typedef union {
+    struct {
+        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  core0 sp pc status register
+         */
+        uint32_t core_0_sp_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_max_reg_t;
+
+/** Type of core_0_sp_pc register
+ *  stack monitor pc status register
+ */
+typedef union {
+    struct {
+        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the PC when trigger stack monitor.
+         */
+        uint32_t core_0_sp_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_pc_reg_t;
+
+/** Type of core_1_intr_ena register
+ *  core1 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor enable
+         */
+        uint32_t core_1_area_dram0_0_rd_ena:1;
+        /** core_1_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor enable
+         */
+        uint32_t core_1_area_dram0_0_wr_ena:1;
+        /** core_1_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor enable
+         */
+        uint32_t core_1_area_dram0_1_rd_ena:1;
+        /** core_1_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor enable
+         */
+        uint32_t core_1_area_dram0_1_wr_ena:1;
+        /** core_1_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor enable
+         */
+        uint32_t core_1_area_pif_0_rd_ena:1;
+        /** core_1_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor enable
+         */
+        uint32_t core_1_area_pif_0_wr_ena:1;
+        /** core_1_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor enable
+         */
+        uint32_t core_1_area_pif_1_rd_ena:1;
+        /** core_1_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor enable
+         */
+        uint32_t core_1_area_pif_1_wr_ena:1;
+        /** core_1_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor enable
+         */
+        uint32_t core_1_sp_spill_min_ena:1;
+        /** core_1_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor enable
+         */
+        uint32_t core_1_sp_spill_max_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_ena_reg_t;
+
+/** Type of core_1_area_dram0_0_min register
+ *  core1 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 dram0 region0 start addr
+         */
+        uint32_t core_1_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_0_min_reg_t;
+
+/** Type of core_1_area_dram0_0_max register
+ *  core1 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 dram0 region0 end addr
+         */
+        uint32_t core_1_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_0_max_reg_t;
+
+/** Type of core_1_area_dram0_1_min register
+ *  core1 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 dram0 region1 start addr
+         */
+        uint32_t core_1_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_1_min_reg_t;
+
+/** Type of core_1_area_dram0_1_max register
+ *  core1 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 dram0 region1 end addr
+         */
+        uint32_t core_1_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_1_max_reg_t;
+
+/** Type of core_1_area_pif_0_min register
+ *  core1 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 PIF region0 start addr
+         */
+        uint32_t core_1_area_pif_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_0_min_reg_t;
+
+/** Type of core_1_area_pif_0_max register
+ *  core1 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 PIF region0 end addr
+         */
+        uint32_t core_1_area_pif_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_0_max_reg_t;
+
+/** Type of core_1_area_pif_1_min register
+ *  core1 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 PIF region1 start addr
+         */
+        uint32_t core_1_area_pif_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_1_min_reg_t;
+
+/** Type of core_1_area_pif_1_max register
+ *  core1 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 PIF region1 end addr
+         */
+        uint32_t core_1_area_pif_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_1_max_reg_t;
+
+/** Type of core_1_area_pc register
+ *  core1 area pc status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  the stackpointer when first touch region monitor interrupt
+         */
+        uint32_t core_1_area_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pc_reg_t;
+
+/** Type of core_1_area_sp register
+ *  core1 area sp status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  the PC when first touch region monitor interrupt
+         */
+        uint32_t core_1_area_sp:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_sp_reg_t;
+
+/** Type of core_1_sp_min register
+ *  stack min value
+ */
+typedef union {
+    struct {
+        /** core_1_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  core1 sp region configuration register
+         */
+        uint32_t core_1_sp_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_sp_min_reg_t;
+
+/** Type of core_1_sp_max register
+ *  stack max value
+ */
+typedef union {
+    struct {
+        /** core_1_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  core1 sp pc status register
+         */
+        uint32_t core_1_sp_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_sp_max_reg_t;
+
+/** Type of core_1_sp_pc register
+ *  stack monitor pc status register
+ */
+typedef union {
+    struct {
+        /** core_1_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the PC when trigger stack monitor.
+         */
+        uint32_t core_1_sp_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_sp_pc_reg_t;
+
+
+/** Group: interrupt configuration register */
+/** Type of core_0_intr_raw register
+ *  core0 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_0_rd_raw:1;
+        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_0_wr_raw:1;
+        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_1_rd_raw:1;
+        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_1_wr_raw:1;
+        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt status
+         */
+        uint32_t core_0_area_pif_0_rd_raw:1;
+        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt status
+         */
+        uint32_t core_0_area_pif_0_wr_raw:1;
+        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt status
+         */
+        uint32_t core_0_area_pif_1_rd_raw:1;
+        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt status
+         */
+        uint32_t core_0_area_pif_1_wr_raw:1;
+        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt status
+         */
+        uint32_t core_0_sp_spill_min_raw:1;
+        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt status
+         */
+        uint32_t core_0_sp_spill_max_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_raw_reg_t;
+
+/** Type of core_0_intr_rls register
+ *  core0 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_rd_rls:1;
+        /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_wr_rls:1;
+        /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_rd_rls:1;
+        /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_wr_rls:1;
+        /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_rd_rls:1;
+        /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_wr_rls:1;
+        /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_rd_rls:1;
+        /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_wr_rls:1;
+        /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_min_rls:1;
+        /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_max_rls:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_rls_reg_t;
+
+/** Type of core_0_intr_clr register
+ *  core0 monitor interrupt clr register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_0_rd_clr:1;
+        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_0_wr_clr:1;
+        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_1_rd_clr:1;
+        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_1_wr_clr:1;
+        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_0_rd_clr:1;
+        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_0_wr_clr:1;
+        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_1_rd_clr:1;
+        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_1_wr_clr:1;
+        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt clr
+         */
+        uint32_t core_0_sp_spill_min_clr:1;
+        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt clr
+         */
+        uint32_t core_0_sp_spill_max_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_clr_reg_t;
+
+/** Type of core_1_intr_raw register
+ *  core1 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_0_rd_raw:1;
+        /** core_1_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_0_wr_raw:1;
+        /** core_1_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_1_rd_raw:1;
+        /** core_1_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_1_wr_raw:1;
+        /** core_1_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor interrupt status
+         */
+        uint32_t core_1_area_pif_0_rd_raw:1;
+        /** core_1_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor interrupt status
+         */
+        uint32_t core_1_area_pif_0_wr_raw:1;
+        /** core_1_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor interrupt status
+         */
+        uint32_t core_1_area_pif_1_rd_raw:1;
+        /** core_1_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor interrupt status
+         */
+        uint32_t core_1_area_pif_1_wr_raw:1;
+        /** core_1_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor interrupt status
+         */
+        uint32_t core_1_sp_spill_min_raw:1;
+        /** core_1_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor interrupt status
+         */
+        uint32_t core_1_sp_spill_max_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_raw_reg_t;
+
+/** Type of core_1_intr_rls register
+ *  core1 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_0_rd_rls:1;
+        /** core_1_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_0_wr_rls:1;
+        /** core_1_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_1_rd_rls:1;
+        /** core_1_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_1_wr_rls:1;
+        /** core_1_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_0_rd_rls:1;
+        /** core_1_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_0_wr_rls:1;
+        /** core_1_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_1_rd_rls:1;
+        /** core_1_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_1_wr_rls:1;
+        /** core_1_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_1_sp_spill_min_rls:1;
+        /** core_1_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_1_sp_spill_max_rls:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_rls_reg_t;
+
+/** Type of core_1_intr_clr register
+ *  core1 monitor interrupt clr register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_0_rd_clr:1;
+        /** core_1_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_0_wr_clr:1;
+        /** core_1_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_1_rd_clr:1;
+        /** core_1_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_1_wr_clr:1;
+        /** core_1_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_0_rd_clr:1;
+        /** core_1_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_0_wr_clr:1;
+        /** core_1_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_1_rd_clr:1;
+        /** core_1_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_1_wr_clr:1;
+        /** core_1_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor interrupt clr
+         */
+        uint32_t core_1_sp_spill_min_clr:1;
+        /** core_1_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor interrupt clr
+         */
+        uint32_t core_1_sp_spill_max_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_clr_reg_t;
+
+
+/** Group: pc recording configuration register */
+/** Type of core_0_rcd_en register
+ *  record enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable record PC
+         */
+        uint32_t core_0_rcd_recorden:1;
+        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+         */
+        uint32_t core_0_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_en_reg_t;
+
+/** Type of core_1_rcd_en register
+ *  record enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable record PC
+         */
+        uint32_t core_1_rcd_recorden:1;
+        /** core_1_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+         */
+        uint32_t core_1_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_1_rcd_en_reg_t;
+
+
+/** Group: pc recording status register */
+/** Type of core_0_rcd_pdebugpc register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  recorded PC
+         */
+        uint32_t core_0_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugpc_reg_t;
+
+/** Type of core_0_rcd_pdebugsp register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  recorded sp
+         */
+        uint32_t core_0_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugsp_reg_t;
+
+/** Type of core_1_rcd_pdebugpc register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  recorded PC
+         */
+        uint32_t core_1_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_rcd_pdebugpc_reg_t;
+
+/** Type of core_1_rcd_pdebugsp register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  recorded sp
+         */
+        uint32_t core_1_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_rcd_pdebugsp_reg_t;
+
+
+/** Group: exception monitor register */
+/** Type of core_0_iram0_exception_monitor_0 register
+ *  exception monitor status register0
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_0
+         */
+        uint32_t core_0_iram0_recording_addr_0:24;
+        /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_iram0_recording_wr_0
+         */
+        uint32_t core_0_iram0_recording_wr_0:1;
+        /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_0
+         */
+        uint32_t core_0_iram0_recording_loadstore_0:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_iram0_exception_monitor_1 register
+ *  exception monitor status register1
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_1
+         */
+        uint32_t core_0_iram0_recording_addr_1:24;
+        /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_iram0_recording_wr_1
+         */
+        uint32_t core_0_iram0_recording_wr_1:1;
+        /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_1
+         */
+        uint32_t core_0_iram0_recording_loadstore_1:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_0 register
+ *  exception monitor status register2
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
+         *  reg_core_0_dram0_recording_wr_0
+         */
+        uint32_t core_0_dram0_recording_wr_0:1;
+        /** core_0_dram0_recording_byteen_0 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_0
+         */
+        uint32_t core_0_dram0_recording_byteen_0:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_1 register
+ *  exception monitor status register3
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_0
+         */
+        uint32_t core_0_dram0_recording_addr_0:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_2 register
+ *  exception monitor status register4
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_0
+         */
+        uint32_t core_0_dram0_recording_pc_0:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_3 register
+ *  exception monitor status register5
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
+         *  reg_core_0_dram0_recording_wr_1
+         */
+        uint32_t core_0_dram0_recording_wr_1:1;
+        /** core_0_dram0_recording_byteen_1 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_1
+         */
+        uint32_t core_0_dram0_recording_byteen_1:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_4 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_1
+         */
+        uint32_t core_0_dram0_recording_addr_1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_4_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_5 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_1
+         */
+        uint32_t core_0_dram0_recording_pc_1:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_5_reg_t;
+
+/** Type of core_1_iram0_exception_monitor_0 register
+ *  exception monitor status register0
+ */
+typedef union {
+    struct {
+        /** core_1_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_iram0_recording_addr_0
+         */
+        uint32_t core_1_iram0_recording_addr_0:24;
+        /** core_1_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
+         *  reg_core_1_iram0_recording_wr_0
+         */
+        uint32_t core_1_iram0_recording_wr_0:1;
+        /** core_1_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
+         *  reg_core_1_iram0_recording_loadstore_0
+         */
+        uint32_t core_1_iram0_recording_loadstore_0:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_1_iram0_exception_monitor_0_reg_t;
+
+/** Type of core_1_iram0_exception_monitor_1 register
+ *  exception monitor status register1
+ */
+typedef union {
+    struct {
+        /** core_1_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_iram0_recording_addr_1
+         */
+        uint32_t core_1_iram0_recording_addr_1:24;
+        /** core_1_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
+         *  reg_core_1_iram0_recording_wr_1
+         */
+        uint32_t core_1_iram0_recording_wr_1:1;
+        /** core_1_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
+         *  reg_core_1_iram0_recording_loadstore_1
+         */
+        uint32_t core_1_iram0_recording_loadstore_1:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_1_iram0_exception_monitor_1_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_0 register
+ *  exception monitor status register2
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
+         *  reg_core_1_dram0_recording_wr_0
+         */
+        uint32_t core_1_dram0_recording_wr_0:1;
+        /** core_1_dram0_recording_byteen_0 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_1_dram0_recording_byteen_0
+         */
+        uint32_t core_1_dram0_recording_byteen_0:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_1 register
+ *  exception monitor status register3
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_dram0_recording_addr_0
+         */
+        uint32_t core_1_dram0_recording_addr_0:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_1_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_2 register
+ *  exception monitor status register4
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_1_dram0_recording_pc_0
+         */
+        uint32_t core_1_dram0_recording_pc_0:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_2_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_3 register
+ *  exception monitor status register5
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
+         *  reg_core_1_dram0_recording_wr_1
+         */
+        uint32_t core_1_dram0_recording_wr_1:1;
+        /** core_1_dram0_recording_byteen_1 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_1_dram0_recording_byteen_1
+         */
+        uint32_t core_1_dram0_recording_byteen_1:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_3_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_4 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_dram0_recording_addr_1
+         */
+        uint32_t core_1_dram0_recording_addr_1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_4_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_5 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_1_dram0_recording_pc_1
+         */
+        uint32_t core_1_dram0_recording_pc_1:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_5_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_0 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_0
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_1 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_1
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_1:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
+
+
+/** Group: cpu status registers */
+/** Type of core_0_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  cpu's lastpc before exception
+         */
+        uint32_t core_0_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_lastpc_before_exception_reg_t;
+
+/** Type of core_0_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
+         *  cpu debug mode status, 1 means cpu enter debug mode.
+         */
+        uint32_t core_0_debug_mode:1;
+        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  cpu debug_module active status
+         */
+        uint32_t core_0_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_debug_mode_reg_t;
+
+/** Type of core_1_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_1_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  cpu's lastpc before exception
+         */
+        uint32_t core_1_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_lastpc_before_exception_reg_t;
+
+/** Type of core_1_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_1_debug_mode : RO; bitpos: [0]; default: 0;
+         *  cpu debug mode status, 1 means cpu enter debug mode.
+         */
+        uint32_t core_1_debug_mode:1;
+        /** core_1_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  cpu debug_module active status
+         */
+        uint32_t core_1_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_1_debug_mode_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of clock_gate register
+ *  clock register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 force on the clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} assist_debug_clock_gate_reg_t;
+
+/** Type of date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
+         *  version register
+         */
+        uint32_t assist_debug_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} assist_debug_date_reg_t;
+
+
+typedef struct {
+    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
+    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
+    volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
+    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
+    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
+    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
+    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
+    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
+    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
+    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
+    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
+    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
+    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
+    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
+    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
+    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
+    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
+    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
+    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
+    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
+    volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
+    volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
+    volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
+    volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
+    volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4;
+    volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5;
+    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
+    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
+    uint32_t reserved_078[2];
+    volatile assist_debug_core_1_intr_ena_reg_t core_1_intr_ena;
+    volatile assist_debug_core_1_intr_raw_reg_t core_1_intr_raw;
+    volatile assist_debug_core_1_intr_rls_reg_t core_1_intr_rls;
+    volatile assist_debug_core_1_intr_clr_reg_t core_1_intr_clr;
+    volatile assist_debug_core_1_area_dram0_0_min_reg_t core_1_area_dram0_0_min;
+    volatile assist_debug_core_1_area_dram0_0_max_reg_t core_1_area_dram0_0_max;
+    volatile assist_debug_core_1_area_dram0_1_min_reg_t core_1_area_dram0_1_min;
+    volatile assist_debug_core_1_area_dram0_1_max_reg_t core_1_area_dram0_1_max;
+    volatile assist_debug_core_1_area_pif_0_min_reg_t core_1_area_pif_0_min;
+    volatile assist_debug_core_1_area_pif_0_max_reg_t core_1_area_pif_0_max;
+    volatile assist_debug_core_1_area_pif_1_min_reg_t core_1_area_pif_1_min;
+    volatile assist_debug_core_1_area_pif_1_max_reg_t core_1_area_pif_1_max;
+    volatile assist_debug_core_1_area_pc_reg_t core_1_area_pc;
+    volatile assist_debug_core_1_area_sp_reg_t core_1_area_sp;
+    volatile assist_debug_core_1_sp_min_reg_t core_1_sp_min;
+    volatile assist_debug_core_1_sp_max_reg_t core_1_sp_max;
+    volatile assist_debug_core_1_sp_pc_reg_t core_1_sp_pc;
+    volatile assist_debug_core_1_rcd_en_reg_t core_1_rcd_en;
+    volatile assist_debug_core_1_rcd_pdebugpc_reg_t core_1_rcd_pdebugpc;
+    volatile assist_debug_core_1_rcd_pdebugsp_reg_t core_1_rcd_pdebugsp;
+    volatile assist_debug_core_1_iram0_exception_monitor_0_reg_t core_1_iram0_exception_monitor_0;
+    volatile assist_debug_core_1_iram0_exception_monitor_1_reg_t core_1_iram0_exception_monitor_1;
+    volatile assist_debug_core_1_dram0_exception_monitor_0_reg_t core_1_dram0_exception_monitor_0;
+    volatile assist_debug_core_1_dram0_exception_monitor_1_reg_t core_1_dram0_exception_monitor_1;
+    volatile assist_debug_core_1_dram0_exception_monitor_2_reg_t core_1_dram0_exception_monitor_2;
+    volatile assist_debug_core_1_dram0_exception_monitor_3_reg_t core_1_dram0_exception_monitor_3;
+    volatile assist_debug_core_1_dram0_exception_monitor_4_reg_t core_1_dram0_exception_monitor_4;
+    volatile assist_debug_core_1_dram0_exception_monitor_5_reg_t core_1_dram0_exception_monitor_5;
+    volatile assist_debug_core_1_lastpc_before_exception_reg_t core_1_lastpc_before_exception;
+    volatile assist_debug_core_1_debug_mode_reg_t core_1_debug_mode;
+    uint32_t reserved_0f8[2];
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
+    volatile assist_debug_clock_gate_reg_t clock_gate;
+    uint32_t reserved_10c[188];
+    volatile assist_debug_date_reg_t date;
+} assist_debug_dev_t;
+
+extern assist_debug_dev_t ASSIST_DEBUG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/axi_dma_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/axi_dma_eco5_struct.h
new file mode 100644
index 0000000000..0abf169209
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/axi_dma_eco5_struct.h
@@ -0,0 +1,2021 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt Registers */
+/** Type of in_int_raw_chn register
+ *  Raw status interrupt of channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw:1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+         *  turns to high level when the last data pointed by one inlink descriptor has been
+         *  received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw:1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when data error is detected only in the
+         *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+         *  interrupt is reserved.
+         */
+        uint32_t in_err_eof_chn_int_raw:1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+         *  including owner error and the second and third word error of inlink descriptor for
+         *  Rx channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw:1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+         *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+         */
+        uint32_t in_dscr_empty_chn_int_raw:1;
+        /** infifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l1_ovf_chn_int_raw:1;
+        /** infifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l1_udf_chn_int_raw:1;
+        /** infifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l2_ovf_chn_int_raw:1;
+        /** infifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l2_udf_chn_int_raw:1;
+        /** infifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l3_ovf_chn_int_raw:1;
+        /** infifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l3_udf_chn_int_raw:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_in_int_raw_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt of channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st:1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st:1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st:1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st:1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st:1;
+        /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_chn_int_st:1;
+        /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_chn_int_st:1;
+        /** infifo_l1_ovf_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_st:1;
+        /** infifo_l1_udf_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_st:1;
+        /** infifo_l3_ovf_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_st:1;
+        /** infifo_l3_udf_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_st:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_in_int_st_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena:1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena:1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena:1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena:1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena:1;
+        /** infifo_l1_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_ena:1;
+        /** infifo_l1_udf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_ena:1;
+        /** infifo_l2_ovf_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_ena:1;
+        /** infifo_l2_udf_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_ena:1;
+        /** infifo_l3_ovf_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_ena:1;
+        /** infifo_l3_udf_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_ena:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_in_int_ena_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr:1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr:1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr:1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr:1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr:1;
+        /** infifo_l1_ovf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_clr:1;
+        /** infifo_l1_udf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_clr:1;
+        /** infifo_l2_ovf_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_clr:1;
+        /** infifo_l2_udf_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_clr:1;
+        /** infifo_l3_ovf_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_clr:1;
+        /** infifo_l3_udf_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_clr:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_in_int_clr_chn_reg_t;
+
+/** Type of out_int_raw_chn register
+ *  Raw status interrupt of channeln
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel0.
+         */
+        uint32_t out_done_chn_int_raw:1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel0.
+         */
+        uint32_t out_eof_chn_int_raw:1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+         *  including owner error and the second and third word error of outlink descriptor for
+         *  Tx channel0.
+         */
+        uint32_t out_dscr_err_chn_int_raw:1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel0.
+         */
+        uint32_t out_total_eof_chn_int_raw:1;
+        /** outfifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_raw:1;
+        /** outfifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l1_udf_chn_int_raw:1;
+        /** outfifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_raw:1;
+        /** outfifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l2_udf_chn_int_raw:1;
+        /** outfifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_raw:1;
+        /** outfifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l3_udf_chn_int_raw:1;
+        /** out_link_switch_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+         *  channel0.
+         */
+        uint32_t out_link_switch_chn_int_raw:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_int_raw_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt of channeln
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st:1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st:1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st:1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st:1;
+        /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_chn_int_st:1;
+        /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_chn_int_st:1;
+        /** outfifo_l1_ovf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_st:1;
+        /** outfifo_l1_udf_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_st:1;
+        /** outfifo_l3_ovf_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_st:1;
+        /** outfifo_l3_udf_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_st:1;
+        /** out_link_switch_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+         */
+        uint32_t out_link_switch_chn_int_st:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_int_st_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of channeln
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena:1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena:1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena:1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena:1;
+        /** outfifo_l1_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_ena:1;
+        /** outfifo_l1_udf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_ena:1;
+        /** outfifo_l2_ovf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_ena:1;
+        /** outfifo_l2_udf_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_ena:1;
+        /** outfifo_l3_ovf_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_ena:1;
+        /** outfifo_l3_udf_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_ena:1;
+        /** out_link_switch_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+         */
+        uint32_t out_link_switch_chn_int_ena:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_int_ena_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of channeln
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr:1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr:1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr:1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr:1;
+        /** outfifo_l1_ovf_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_clr:1;
+        /** outfifo_l1_udf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_clr:1;
+        /** outfifo_l2_ovf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_clr:1;
+        /** outfifo_l2_udf_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_clr:1;
+        /** outfifo_l3_ovf_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_clr:1;
+        /** outfifo_l3_udf_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_clr:1;
+        /** out_link_switch_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+         */
+        uint32_t out_link_switch_chn_int_clr:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_int_clr_chn_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of in_conf0_chn register
+ *  Configure 0 register of Rx channel n
+ */
+typedef union {
+    struct {
+        /** in_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+         */
+        uint32_t in_rst_chn:1;
+        /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn:1;
+        /** mem_trans_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+         *  AXI_DMA.
+         */
+        uint32_t mem_trans_en_chn:1;
+        /** in_etm_en_chn : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+         *  task.
+         */
+        uint32_t in_etm_en_chn:1;
+        /** in_burst_size_sel_chn : R/W; bitpos: [6:4]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t in_burst_size_sel_chn:3;
+        /** in_cmd_disable_chn : R/W; bitpos: [7]; default: 0;
+         *  1:mean disable cmd of this ch0
+         */
+        uint32_t in_cmd_disable_chn:1;
+        /** in_ecc_aec_en_chn : R/W; bitpos: [8]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t in_ecc_aec_en_chn:1;
+        /** indscr_burst_en_chn : R/W; bitpos: [9]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t indscr_burst_en_chn:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_dma_in_conf0_chn_reg_t;
+
+/** Type of in_conf1_chn register
+ *  Configure 1 register of Rx channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_dma_in_conf1_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Pop control register of Rx channel n
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
+         *  This register stores the data popping from AXI_DMA FIFO.
+         */
+        uint32_t infifo_rdata_chn:12;
+        /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
+         *  Set this bit to pop data from AXI_DMA FIFO.
+         */
+        uint32_t infifo_pop_chn:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_dma_in_pop_chn_reg_t;
+
+/** Type of in_link1_chn register
+ *  Link descriptor configure and control register of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_chn:1;
+        /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn:1;
+        /** inlink_start_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn:1;
+        /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn:1;
+        /** inlink_park_chn : RO; bitpos: [4]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} axi_dma_in_link1_chn_reg_t;
+
+/** Type of in_link2_chn register
+ *  Link descriptor configure and control register of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 20 least significant bits of the first inlink descriptor's
+         *  address.
+         */
+        uint32_t inlink_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_link2_chn_reg_t;
+
+/** Type of in_crc_init_data_chn register
+ *  This register is used to config chn crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of rx crc initial value
+         */
+        uint32_t in_crc_init_data_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_crc_init_data_chn_reg_t;
+
+/** Type of rx_crc_width_chn register
+ *  This register is used to confiig rx chn crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_width_chn:2;
+        /** rx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_lautch_flga_chn:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_width_chn_reg_t;
+
+/** Type of in_crc_clear_chn register
+ *  This register is used to clear chn crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of rx crc result
+         */
+        uint32_t in_crc_clear_chn_reg:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_dma_in_crc_clear_chn_reg_t;
+
+/** Type of in_crc_final_result_chn register
+ *  This register is used to store chn crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of rx
+         */
+        uint32_t in_crc_final_result_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_crc_final_result_chn_reg_t;
+
+/** Type of rx_crc_en_addr_chn register
+ *  This register is used to config chn crc en addr
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_en_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_en_addr_chn_reg_t;
+
+/** Type of rx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_wr_data_chn:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_data_en_addr_chn_reg_t;
+
+/** Type of out_conf0_ch0 register
+ *  Configure 0 register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** out_rst_ch0 : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_ch0:1;
+        /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch0:1;
+        /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_ch0:1;
+        /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is
+         *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+         */
+        uint32_t out_eof_mode_ch0:1;
+        /** out_etm_en_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_ch0:1;
+        /** out_burst_size_sel_ch0 : R/W; bitpos: [7:5]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t out_burst_size_sel_ch0:3;
+        /** out_cmd_disable_ch0 : R/W; bitpos: [8]; default: 0;
+         *  1:mean disable cmd of this ch0
+         */
+        uint32_t out_cmd_disable_ch0:1;
+        /** out_ecc_aec_en_ch0 : R/W; bitpos: [9]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t out_ecc_aec_en_ch0:1;
+        /** outdscr_burst_en_ch0 : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch0:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_conf0_ch0_reg_t;
+
+/** Type of out_conf1_chn register
+ *  Configure 1 register of Tx channeln
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_dma_out_conf1_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Push control register of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
+         *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+         */
+        uint32_t outfifo_wdata_chn:9;
+        /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
+         *  Set this bit to push data into AXI_DMA FIFO.
+         */
+        uint32_t outfifo_push_chn:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_dma_out_push_chn_reg_t;
+
+/** Type of out_link1_chn register
+ *  Link descriptor configure and control register of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn:1;
+        /** outlink_start_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn:1;
+        /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn:1;
+        /** outlink_park_chn : RO; bitpos: [3]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_dma_out_link1_chn_reg_t;
+
+/** Type of out_link2_chn register
+ *  Link descriptor configure and control register of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 32 least significant bits of the first outlink
+         *  descriptor's address.
+         */
+        uint32_t outlink_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_link2_chn_reg_t;
+
+/** Type of out_crc_init_data_chn register
+ *  This register is used to config chn crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of tx crc initial value
+         */
+        uint32_t out_crc_init_data_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_crc_init_data_chn_reg_t;
+
+/** Type of tx_crc_width_chn register
+ *  This register is used to confiig tx chn crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_width_chn:2;
+        /** tx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_lautch_flga_chn:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_width_chn_reg_t;
+
+/** Type of out_crc_clear_chn register
+ *  This register is used to clear chn crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of tx crc result
+         */
+        uint32_t out_crc_clear_chn_reg:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_dma_out_crc_clear_chn_reg_t;
+
+/** Type of out_crc_final_result_chn register
+ *  This register is used to store chn crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of tx
+         */
+        uint32_t out_crc_final_result_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_crc_final_result_chn_reg_t;
+
+/** Type of tx_crc_en_wr_data_chn register
+ *  This resister is used to config chn crc en for every bit
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable tx ch0 crc 32bit on/off
+         */
+        uint32_t tx_crc_en_wr_data_chn:32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_en_addr_chn register
+ *  This register is used to config chn crc en addr
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_en_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_en_addr_chn_reg_t;
+
+/** Type of tx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_wr_data_chn:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_data_en_addr_chn_reg_t;
+
+/** Type of out_conf0_ch1 register
+ *  Configure 0 register of Tx channel1
+ */
+typedef union {
+    struct {
+        /** out_rst_ch1 : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_ch1:1;
+        /** out_loop_test_ch1 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch1:1;
+        /** out_auto_wrback_ch1 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_ch1:1;
+        /** out_eof_mode_ch1 : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is
+         *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+         */
+        uint32_t out_eof_mode_ch1:1;
+        /** out_etm_en_ch1 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_ch1:1;
+        /** out_burst_size_sel_ch1 : R/W; bitpos: [7:5]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t out_burst_size_sel_ch1:3;
+        /** out_cmd_disable_ch1 : R/W; bitpos: [8]; default: 0;
+         *  1:mean disable cmd of this ch1
+         */
+        uint32_t out_cmd_disable_ch1:1;
+        /** out_ecc_aec_en_ch1 : R/W; bitpos: [9]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t out_ecc_aec_en_ch1:1;
+        /** outdscr_burst_en_ch1 : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch1:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_conf0_ch1_reg_t;
+
+/** Type of out_conf0_ch2 register
+ *  Configure 0 register of Tx channel2
+ */
+typedef union {
+    struct {
+        /** out_rst_ch2 : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_ch2:1;
+        /** out_loop_test_ch2 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch2:1;
+        /** out_auto_wrback_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_ch2:1;
+        /** out_eof_mode_ch2 : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is
+         *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+         */
+        uint32_t out_eof_mode_ch2:1;
+        /** out_etm_en_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_ch2:1;
+        /** out_burst_size_sel_ch2 : R/W; bitpos: [7:5]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t out_burst_size_sel_ch2:3;
+        /** out_cmd_disable_ch2 : R/W; bitpos: [8]; default: 0;
+         *  1:mean disable cmd of this ch2
+         */
+        uint32_t out_cmd_disable_ch2:1;
+        /** out_ecc_aec_en_ch2 : R/W; bitpos: [9]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t out_ecc_aec_en_ch2:1;
+        /** outdscr_burst_en_ch2 : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch2:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_conf0_ch2_reg_t;
+
+/** Type of arb_timeout register
+ *  This retister is used to config arbiter time slice
+ */
+typedef union {
+    struct {
+        /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to config tx arbiter time out value
+         */
+        uint32_t arb_timeout_tx:16;
+        /** arb_timeout_rx : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to config rx arbiter time out value
+         */
+        uint32_t arb_timeout_rx:16;
+    };
+    uint32_t val;
+} axi_dma_arb_timeout_reg_t;
+
+/** Type of weight_en register
+ *  This register is used to config arbiter weight function to on or off
+ */
+typedef union {
+    struct {
+        /** weight_en_tx : R/W; bitpos: [0]; default: 0;
+         *  This register is used to config tx arbiter weight function  off/on
+         */
+        uint32_t weight_en_tx:1;
+        /** weight_en_rx : R/W; bitpos: [1]; default: 0;
+         *  This register is used to config rx arbiter weight function  off/on
+         */
+        uint32_t weight_en_rx:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_dma_weight_en_reg_t;
+
+/** Type of in_mem_conf register
+ *  Mem power configure register of Rx channel
+ */
+typedef union {
+    struct {
+        /** in_mem_clk_force_en : R/W; bitpos: [0]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+         *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+         */
+        uint32_t in_mem_clk_force_en:1;
+        /** in_mem_force_pu : R/W; bitpos: [1]; default: 0;
+         *  Force power up ram
+         */
+        uint32_t in_mem_force_pu:1;
+        /** in_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Force power down ram
+         */
+        uint32_t in_mem_force_pd:1;
+        /** out_mem_clk_force_en : R/W; bitpos: [3]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+         *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+         */
+        uint32_t out_mem_clk_force_en:1;
+        /** out_mem_force_pu : R/W; bitpos: [4]; default: 0;
+         *  Force power up ram
+         */
+        uint32_t out_mem_force_pu:1;
+        /** out_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  Force power down ram
+         */
+        uint32_t out_mem_force_pd:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_dma_in_mem_conf_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr:32;
+    };
+    uint32_t val;
+} axi_dma_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr:32;
+    };
+    uint32_t val;
+} axi_dma_intr_mem_end_addr_reg_t;
+
+/** Type of extr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_extr_mem_start_addr:32;
+    };
+    uint32_t val;
+} axi_dma_extr_mem_start_addr_reg_t;
+
+/** Type of extr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_extr_mem_end_addr:32;
+    };
+    uint32_t val;
+} axi_dma_extr_mem_end_addr_reg_t;
+
+/** Type of in_reset_avail_chn register
+ *  The rx channel n reset valid_flag register.
+ */
+typedef union {
+    struct {
+        /** in_reset_avail_chn : RO; bitpos: [0]; default: 1;
+         *  rx chan0 reset valid reg.
+         */
+        uint32_t in_reset_avail_chn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_dma_in_reset_avail_chn_reg_t;
+
+/** Type of out_reset_avail_chn register
+ *  The tx channel n reset valid_flag register.
+ */
+typedef union {
+    struct {
+        /** out_reset_avail_chn : RO; bitpos: [0]; default: 1;
+         *  tx chan0 reset valid reg.
+         */
+        uint32_t out_reset_avail_chn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_dma_out_reset_avail_chn_reg_t;
+
+/** Type of misc_conf register
+ *  MISC register
+ */
+typedef union {
+    struct {
+        /** axim_rst_wr_inter : R/W; bitpos: [0]; default: 0;
+         *  Set this bit then clear this bit to reset the internal axi_wr FSM.
+         */
+        uint32_t axim_rst_wr_inter:1;
+        /** axim_rst_rd_inter : R/W; bitpos: [1]; default: 0;
+         *  Set this bit then clear this bit to reset the internal axi_rd FSM.
+         */
+        uint32_t axim_rst_rd_inter:1;
+        uint32_t reserved_2:1;
+        /** arb_pri_dis : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to disable priority arbitration function.
+         */
+        uint32_t arb_pri_dis:1;
+        /** clk_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} axi_dma_misc_conf_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of infifo_status_chn register
+ *  Receive FIFO status of Rx channel n
+ */
+typedef union {
+    struct {
+        /** infifo_l3_full_chn : RO; bitpos: [0]; default: 1;
+         *  L3 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_full_chn:1;
+        /** infifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L3 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_empty_chn:1;
+        /** infifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_l3_cnt_chn:6;
+        /** infifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
+         *  L3 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_udf_chn:1;
+        /** infifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
+         *  L3 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_ovf_chn:1;
+        /** infifo_l1_full_chn : RO; bitpos: [10]; default: 0;
+         *  L1 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_full_chn:1;
+        /** infifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
+         *  L1 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_empty_chn:1;
+        /** infifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
+         *  L1 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_udf_chn:1;
+        /** infifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
+         *  L1 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_ovf_chn:1;
+        /** infifo_l2_full_chn : RO; bitpos: [14]; default: 0;
+         *  L2 Rx RAM full signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_full_chn:1;
+        /** infifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
+         *  L2 Rx RAM empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_empty_chn:1;
+        /** infifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
+         *  L2 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_udf_chn:1;
+        /** infifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
+         *  L2 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_ovf_chn:1;
+        uint32_t reserved_18:5;
+        /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn:1;
+        /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn:1;
+        /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn:1;
+        /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn:1;
+        /** in_remain_under_5b_chn : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_5b_chn:1;
+        /** in_remain_under_6b_chn : RO; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_6b_chn:1;
+        /** in_remain_under_7b_chn : RO; bitpos: [29]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_7b_chn:1;
+        /** in_remain_under_8b_chn : RO; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_8b_chn:1;
+        /** in_buf_hungry_chn : RO; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_chn:1;
+    };
+    uint32_t val;
+} axi_dma_infifo_status_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Receive status of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn:18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn:2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} axi_dma_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Inlink descriptor address when EOF occurs of Rx channel n
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Inlink descriptor address when errors occur of Rx channel n
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data. Only used when peripheral is UHCI0.
+         */
+        uint32_t in_err_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Current inlink descriptor address of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current inlink descriptor x.
+         */
+        uint32_t inlink_dscr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  The last inlink descriptor address of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  The second-to-last inlink descriptor address of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_bf1_chn_reg_t;
+
+/** Type of outfifo_status_chn register
+ *  Transmit FIFO status of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outfifo_l3_full_chn : RO; bitpos: [0]; default: 0;
+         *  L3 Tx FIFO full signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_full_chn:1;
+        /** outfifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L3 Tx FIFO empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_empty_chn:1;
+        /** outfifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+         */
+        uint32_t outfifo_l3_cnt_chn:6;
+        /** outfifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
+         *  L3 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_udf_chn:1;
+        /** outfifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
+         *  L3 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_ovf_chn:1;
+        /** outfifo_l1_full_chn : RO; bitpos: [10]; default: 0;
+         *  L1 Tx FIFO full signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_full_chn:1;
+        /** outfifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
+         *  L1 Tx FIFO empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_empty_chn:1;
+        /** outfifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
+         *  L1 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_udf_chn:1;
+        /** outfifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
+         *  L1 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_ovf_chn:1;
+        /** outfifo_l2_full_chn : RO; bitpos: [14]; default: 0;
+         *  L2 Tx RAM full signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_full_chn:1;
+        /** outfifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
+         *  L2 Tx RAM empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_empty_chn:1;
+        /** outfifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
+         *  L2 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_udf_chn:1;
+        /** outfifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
+         *  L2 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_ovf_chn:1;
+        uint32_t reserved_18:5;
+        /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn:1;
+        /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn:1;
+        /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn:1;
+        /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn:1;
+        /** out_remain_under_5b_chn : RO; bitpos: [27]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_5b_chn:1;
+        /** out_remain_under_6b_chn : RO; bitpos: [28]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_6b_chn:1;
+        /** out_remain_under_7b_chn : RO; bitpos: [29]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_7b_chn:1;
+        /** out_remain_under_8b_chn : RO; bitpos: [30]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_8b_chn:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} axi_dma_outfifo_status_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Transmit status of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn:18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_chn:2;
+        /** out_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_chn:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} axi_dma_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Outlink descriptor address when EOF occurs of Tx channeln
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_eof_bfr_des_addr_chn register
+ *  The last outlink descriptor address when EOF occurs of Tx channeln
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor before the last outlink
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_eof_bfr_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Current outlink descriptor address of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current outlink descriptor y.
+         */
+        uint32_t outlink_dscr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  The last outlink descriptor address of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  The second-to-last outlink descriptor address of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor x-2.
+         */
+        uint32_t outlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_bf1_chn_reg_t;
+
+/** Type of wresp_cnt register
+ *  AXI wr response cnt register.
+ */
+typedef union {
+    struct {
+        /** wresp_cnt : RO; bitpos: [3:0]; default: 0;
+         *  axi wr response cnt reg.
+         */
+        uint32_t wresp_cnt:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_dma_wresp_cnt_reg_t;
+
+/** Type of rresp_cnt register
+ *  AXI wr response cnt register.
+ */
+typedef union {
+    struct {
+        /** rresp_cnt : RO; bitpos: [3:0]; default: 0;
+         *  axi rd response cnt reg.
+         */
+        uint32_t rresp_cnt:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_dma_rresp_cnt_reg_t;
+
+/** Type of infifo_status1_chn register
+ *  Receive FIFO status of Rx channel n
+ */
+typedef union {
+    struct {
+        /** l1infifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+         */
+        uint32_t l1infifo_cnt_chn:6;
+        /** l2infifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
+         *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+         */
+        uint32_t l2infifo_cnt_chn:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_dma_infifo_status1_chn_reg_t;
+
+/** Type of outfifo_status1_chn register
+ *  Receive FIFO status of Tx channel n
+ */
+typedef union {
+    struct {
+        /** l1outfifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+         */
+        uint32_t l1outfifo_cnt_chn:6;
+        /** l2outfifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
+         *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+         */
+        uint32_t l2outfifo_cnt_chn:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_dma_outfifo_status1_chn_reg_t;
+
+/** Type of link_switch_state register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** link_switch_state_ch0 : R/W; bitpos: [0]; default: 0;
+         *  The register that confirm ch dscr switch success
+         */
+        uint32_t link_switch_state_ch0:1;
+        /** link_switch_state_ch1 : R/W; bitpos: [1]; default: 0;
+         *  The register that confirm ch dscr switch success
+         */
+        uint32_t link_switch_state_ch1:1;
+        /** link_switch_state_ch2 : R/W; bitpos: [2]; default: 0;
+         *  The register that confirm ch dscr switch success
+         */
+        uint32_t link_switch_state_ch2:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_dma_link_switch_state_reg_t;
+
+
+/** Group: Priority Registers */
+/** Type of in_pri_chn register
+ *  Priority register of Rx channel n
+ */
+typedef union {
+    struct {
+        /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+         */
+        uint32_t rx_pri_chn:4;
+        /** rx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
+         *  The weight of Rx channel 0
+         */
+        uint32_t rx_ch_arb_weigh_chn:4;
+        /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
+         *  0: mean not optimization weight function ,1: mean optimization
+         */
+        uint32_t rx_arb_weigh_opt_dir_chn:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} axi_dma_in_pri_chn_reg_t;
+
+/** Type of out_pri_chn register
+ *  Priority register of Tx channeln.
+ */
+typedef union {
+    struct {
+        /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Tx channel0. The larger of the value the higher of the priority.
+         */
+        uint32_t tx_pri_chn:4;
+        /** tx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
+         *  The weight of Tx channel0
+         */
+        uint32_t tx_ch_arb_weigh_chn:4;
+        /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
+         *  0: mean not optimization weight function ,1: mean optimization
+         */
+        uint32_t tx_arb_weigh_opt_dir_chn:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} axi_dma_out_pri_chn_reg_t;
+
+
+/** Group: Peripheral Select Registers */
+/** Type of in_peri_sel_chn register
+ *  Peripheral selection of Rx channel n
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+         *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+         */
+        uint32_t peri_in_sel_chn:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_dma_in_peri_sel_chn_reg_t;
+
+/** Type of out_peri_sel_chn register
+ *  Peripheral selection of Tx channeln
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+         *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+         */
+        uint32_t peri_out_sel_chn:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_dma_out_peri_sel_chn_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of rx_crc_en_wr_data_chn register
+ *  This resister is used to config chn crc en for every bit
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable rx ch0 crc 32bit on/off
+         */
+        uint32_t rx_crc_en_wr_data_chn:32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_en_wr_data_chn_reg_t;
+
+
+/** Group: Debug Registers */
+/** Type of rdn_result register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_dma_rdn_result_reg_t;
+
+/** Type of rdn_eco_high register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} axi_dma_rdn_eco_high_reg_t;
+
+/** Type of rdn_eco_low register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} axi_dma_rdn_eco_low_reg_t;
+
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36712768;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} axi_dma_date_reg_t;
+
+
+typedef struct {
+    volatile axi_dma_in_int_raw_chn_reg_t in_int_raw_ch0;
+    volatile axi_dma_in_int_st_chn_reg_t in_int_st_ch0;
+    volatile axi_dma_in_int_ena_chn_reg_t in_int_ena_ch0;
+    volatile axi_dma_in_int_clr_chn_reg_t in_int_clr_ch0;
+    volatile axi_dma_in_conf0_chn_reg_t in_conf0_ch0;
+    volatile axi_dma_in_conf1_chn_reg_t in_conf1_ch0;
+    volatile axi_dma_infifo_status_chn_reg_t infifo_status_ch0;
+    volatile axi_dma_in_pop_chn_reg_t in_pop_ch0;
+    volatile axi_dma_in_link1_chn_reg_t in_link1_ch0;
+    volatile axi_dma_in_link2_chn_reg_t in_link2_ch0;
+    volatile axi_dma_in_state_chn_reg_t in_state_ch0;
+    volatile axi_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0;
+    volatile axi_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0;
+    volatile axi_dma_in_dscr_chn_reg_t in_dscr_ch0;
+    volatile axi_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0;
+    volatile axi_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0;
+    volatile axi_dma_in_pri_chn_reg_t in_pri_ch0;
+    volatile axi_dma_in_peri_sel_chn_reg_t in_peri_sel_ch0;
+    volatile axi_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch0;
+    volatile axi_dma_rx_crc_width_chn_reg_t rx_crc_width_ch0;
+    volatile axi_dma_in_crc_clear_chn_reg_t in_crc_clear_ch0;
+    volatile axi_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch0;
+    volatile axi_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch0;
+    volatile axi_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch0;
+    volatile axi_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch0;
+    volatile axi_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch0;
+    volatile axi_dma_in_int_raw_chn_reg_t in_int_raw_ch1;
+    volatile axi_dma_in_int_st_chn_reg_t in_int_st_ch1;
+    volatile axi_dma_in_int_ena_chn_reg_t in_int_ena_ch1;
+    volatile axi_dma_in_int_clr_chn_reg_t in_int_clr_ch1;
+    volatile axi_dma_in_conf0_chn_reg_t in_conf0_ch1;
+    volatile axi_dma_in_conf1_chn_reg_t in_conf1_ch1;
+    volatile axi_dma_infifo_status_chn_reg_t infifo_status_ch1;
+    volatile axi_dma_in_pop_chn_reg_t in_pop_ch1;
+    volatile axi_dma_in_link1_chn_reg_t in_link1_ch1;
+    volatile axi_dma_in_link2_chn_reg_t in_link2_ch1;
+    volatile axi_dma_in_state_chn_reg_t in_state_ch1;
+    volatile axi_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1;
+    volatile axi_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1;
+    volatile axi_dma_in_dscr_chn_reg_t in_dscr_ch1;
+    volatile axi_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1;
+    volatile axi_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1;
+    volatile axi_dma_in_pri_chn_reg_t in_pri_ch1;
+    volatile axi_dma_in_peri_sel_chn_reg_t in_peri_sel_ch1;
+    volatile axi_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch1;
+    volatile axi_dma_rx_crc_width_chn_reg_t rx_crc_width_ch1;
+    volatile axi_dma_in_crc_clear_chn_reg_t in_crc_clear_ch1;
+    volatile axi_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch1;
+    volatile axi_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch1;
+    volatile axi_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch1;
+    volatile axi_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch1;
+    volatile axi_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch1;
+    volatile axi_dma_in_int_raw_chn_reg_t in_int_raw_ch2;
+    volatile axi_dma_in_int_st_chn_reg_t in_int_st_ch2;
+    volatile axi_dma_in_int_ena_chn_reg_t in_int_ena_ch2;
+    volatile axi_dma_in_int_clr_chn_reg_t in_int_clr_ch2;
+    volatile axi_dma_in_conf0_chn_reg_t in_conf0_ch2;
+    volatile axi_dma_in_conf1_chn_reg_t in_conf1_ch2;
+    volatile axi_dma_infifo_status_chn_reg_t infifo_status_ch2;
+    volatile axi_dma_in_pop_chn_reg_t in_pop_ch2;
+    volatile axi_dma_in_link1_chn_reg_t in_link1_ch2;
+    volatile axi_dma_in_link2_chn_reg_t in_link2_ch2;
+    volatile axi_dma_in_state_chn_reg_t in_state_ch2;
+    volatile axi_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2;
+    volatile axi_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2;
+    volatile axi_dma_in_dscr_chn_reg_t in_dscr_ch2;
+    volatile axi_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2;
+    volatile axi_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2;
+    volatile axi_dma_in_pri_chn_reg_t in_pri_ch2;
+    volatile axi_dma_in_peri_sel_chn_reg_t in_peri_sel_ch2;
+    volatile axi_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch2;
+    volatile axi_dma_rx_crc_width_chn_reg_t rx_crc_width_ch2;
+    volatile axi_dma_in_crc_clear_chn_reg_t in_crc_clear_ch2;
+    volatile axi_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch2;
+    volatile axi_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch2;
+    volatile axi_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch2;
+    volatile axi_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch2;
+    volatile axi_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch2;
+    volatile axi_dma_out_int_raw_chn_reg_t out_int_raw_ch0;
+    volatile axi_dma_out_int_st_chn_reg_t out_int_st_ch0;
+    volatile axi_dma_out_int_ena_chn_reg_t out_int_ena_ch0;
+    volatile axi_dma_out_int_clr_chn_reg_t out_int_clr_ch0;
+    volatile axi_dma_out_conf0_ch0_reg_t out_conf0_ch0;
+    volatile axi_dma_out_conf1_chn_reg_t out_conf1_ch0;
+    volatile axi_dma_outfifo_status_chn_reg_t outfifo_status_ch0;
+    volatile axi_dma_out_push_chn_reg_t out_push_ch0;
+    volatile axi_dma_out_link1_chn_reg_t out_link1_ch0;
+    volatile axi_dma_out_link2_chn_reg_t out_link2_ch0;
+    volatile axi_dma_out_state_chn_reg_t out_state_ch0;
+    volatile axi_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0;
+    volatile axi_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0;
+    volatile axi_dma_out_dscr_chn_reg_t out_dscr_ch0;
+    volatile axi_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0;
+    volatile axi_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0;
+    volatile axi_dma_out_pri_chn_reg_t out_pri_ch0;
+    volatile axi_dma_out_peri_sel_chn_reg_t out_peri_sel_ch0;
+    volatile axi_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch0;
+    volatile axi_dma_tx_crc_width_chn_reg_t tx_crc_width_ch0;
+    volatile axi_dma_out_crc_clear_chn_reg_t out_crc_clear_ch0;
+    volatile axi_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch0;
+    volatile axi_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch0;
+    volatile axi_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch0;
+    volatile axi_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch0;
+    volatile axi_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch0;
+    volatile axi_dma_out_int_raw_chn_reg_t out_int_raw_ch1;
+    volatile axi_dma_out_int_st_chn_reg_t out_int_st_ch1;
+    volatile axi_dma_out_int_ena_chn_reg_t out_int_ena_ch1;
+    volatile axi_dma_out_int_clr_chn_reg_t out_int_clr_ch1;
+    volatile axi_dma_out_conf0_ch1_reg_t out_conf0_ch1;
+    volatile axi_dma_out_conf1_chn_reg_t out_conf1_ch1;
+    volatile axi_dma_outfifo_status_chn_reg_t outfifo_status_ch1;
+    volatile axi_dma_out_push_chn_reg_t out_push_ch1;
+    volatile axi_dma_out_link1_chn_reg_t out_link1_ch1;
+    volatile axi_dma_out_link2_chn_reg_t out_link2_ch1;
+    volatile axi_dma_out_state_chn_reg_t out_state_ch1;
+    volatile axi_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1;
+    volatile axi_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1;
+    volatile axi_dma_out_dscr_chn_reg_t out_dscr_ch1;
+    volatile axi_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1;
+    volatile axi_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1;
+    volatile axi_dma_out_pri_chn_reg_t out_pri_ch1;
+    volatile axi_dma_out_peri_sel_chn_reg_t out_peri_sel_ch1;
+    volatile axi_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch1;
+    volatile axi_dma_tx_crc_width_chn_reg_t tx_crc_width_ch1;
+    volatile axi_dma_out_crc_clear_chn_reg_t out_crc_clear_ch1;
+    volatile axi_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch1;
+    volatile axi_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch1;
+    volatile axi_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch1;
+    volatile axi_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch1;
+    volatile axi_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch1;
+    volatile axi_dma_out_int_raw_chn_reg_t out_int_raw_ch2;
+    volatile axi_dma_out_int_st_chn_reg_t out_int_st_ch2;
+    volatile axi_dma_out_int_ena_chn_reg_t out_int_ena_ch2;
+    volatile axi_dma_out_int_clr_chn_reg_t out_int_clr_ch2;
+    volatile axi_dma_out_conf0_ch2_reg_t out_conf0_ch2;
+    volatile axi_dma_out_conf1_chn_reg_t out_conf1_ch2;
+    volatile axi_dma_outfifo_status_chn_reg_t outfifo_status_ch2;
+    volatile axi_dma_out_push_chn_reg_t out_push_ch2;
+    volatile axi_dma_out_link1_chn_reg_t out_link1_ch2;
+    volatile axi_dma_out_link2_chn_reg_t out_link2_ch2;
+    volatile axi_dma_out_state_chn_reg_t out_state_ch2;
+    volatile axi_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2;
+    volatile axi_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2;
+    volatile axi_dma_out_dscr_chn_reg_t out_dscr_ch2;
+    volatile axi_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2;
+    volatile axi_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2;
+    volatile axi_dma_out_pri_chn_reg_t out_pri_ch2;
+    volatile axi_dma_out_peri_sel_chn_reg_t out_peri_sel_ch2;
+    volatile axi_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch2;
+    volatile axi_dma_tx_crc_width_chn_reg_t tx_crc_width_ch2;
+    volatile axi_dma_out_crc_clear_chn_reg_t out_crc_clear_ch2;
+    volatile axi_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch2;
+    volatile axi_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch2;
+    volatile axi_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch2;
+    volatile axi_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch2;
+    volatile axi_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch2;
+    volatile axi_dma_arb_timeout_reg_t arb_timeout;
+    volatile axi_dma_weight_en_reg_t weight_en;
+    volatile axi_dma_in_mem_conf_reg_t in_mem_conf;
+    volatile axi_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile axi_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile axi_dma_extr_mem_start_addr_reg_t extr_mem_start_addr;
+    volatile axi_dma_extr_mem_end_addr_reg_t extr_mem_end_addr;
+    volatile axi_dma_in_reset_avail_chn_reg_t in_reset_avail_chn[3];
+    volatile axi_dma_out_reset_avail_chn_reg_t out_reset_avail_chn[3];
+    uint32_t reserved_2a4;
+    volatile axi_dma_misc_conf_reg_t misc_conf;
+    volatile axi_dma_rdn_result_reg_t rdn_result;
+    volatile axi_dma_rdn_eco_high_reg_t rdn_eco_high;
+    volatile axi_dma_rdn_eco_low_reg_t rdn_eco_low;
+    volatile axi_dma_wresp_cnt_reg_t wresp_cnt;
+    volatile axi_dma_rresp_cnt_reg_t rresp_cnt;
+    volatile axi_dma_infifo_status1_chn_reg_t infifo_status1_chn[3];
+    volatile axi_dma_outfifo_status1_chn_reg_t outfifo_status1_chn[3];
+    volatile axi_dma_date_reg_t date;
+    volatile axi_dma_link_switch_state_reg_t link_switch_state;
+} axi_dma_dev_t;
+
+extern axi_dma_dev_t AXI_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(axi_dma_dev_t) == 0x2e0, "Invalid size of axi_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/axi_dma_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/axi_dma_reg.h
new file mode 100644
index 0000000000..5d0e1fb808
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/axi_dma_reg.h
@@ -0,0 +1,5757 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AXI_DMA_IN_INT_RAW_CH0_REG register
+ *  Raw status interrupt of channel 0
+ */
+#define AXI_DMA_IN_INT_RAW_CH0_REG (DR_REG_AXI_DMA_BASE + 0x0)
+/** AXI_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_RAW_M  (AXI_DMA_IN_DONE_CH0_INT_RAW_V << AXI_DMA_IN_DONE_CH0_INT_RAW_S)
+#define AXI_DMA_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_RAW_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+ *  turns to high level when the last data pointed by one inlink descriptor has been
+ *  received and no data error is detected for Rx channel 0.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when data error is detected only in the
+ *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+ *  interrupt is reserved.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+ *  including owner error and the second and third word error of inlink descriptor for
+ *  Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+ *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_S  10
+
+/** AXI_DMA_IN_INT_ST_CH0_REG register
+ *  Masked interrupt of channel 0
+ */
+#define AXI_DMA_IN_INT_ST_CH0_REG (DR_REG_AXI_DMA_BASE + 0x4)
+/** AXI_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_ST    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_ST_M  (AXI_DMA_IN_DONE_CH0_INT_ST_V << AXI_DMA_IN_DONE_CH0_INT_ST_S)
+#define AXI_DMA_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_ST_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_ST_V << AXI_DMA_IN_SUC_EOF_CH0_INT_ST_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_ST_V << AXI_DMA_IN_ERR_EOF_CH0_INT_ST_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S  4
+/** AXI_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST    (BIT(5))
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST_M  (AXI_DMA_INFIFO_OVF_CH0_INT_ST_V << AXI_DMA_INFIFO_OVF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST_S  5
+/** AXI_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST    (BIT(6))
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST_M  (AXI_DMA_INFIFO_UDF_CH0_INT_ST_V << AXI_DMA_INFIFO_UDF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST_S  6
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST    (BIT(7))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_S  7
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST    (BIT(8))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_S  10
+
+/** AXI_DMA_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of channel 0
+ */
+#define AXI_DMA_IN_INT_ENA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x8)
+/** AXI_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_ENA_M  (AXI_DMA_IN_DONE_CH0_INT_ENA_V << AXI_DMA_IN_DONE_CH0_INT_ENA_S)
+#define AXI_DMA_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_ENA_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_S  10
+
+/** AXI_DMA_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of channel 0
+ */
+#define AXI_DMA_IN_INT_CLR_CH0_REG (DR_REG_AXI_DMA_BASE + 0xc)
+/** AXI_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_CLR_M  (AXI_DMA_IN_DONE_CH0_INT_CLR_V << AXI_DMA_IN_DONE_CH0_INT_CLR_S)
+#define AXI_DMA_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_CLR_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_S  10
+
+/** AXI_DMA_IN_CONF0_CH0_REG register
+ *  Configure 0 register of Rx channel 0
+ */
+#define AXI_DMA_IN_CONF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x10)
+/** AXI_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+#define AXI_DMA_IN_RST_CH0    (BIT(0))
+#define AXI_DMA_IN_RST_CH0_M  (AXI_DMA_IN_RST_CH0_V << AXI_DMA_IN_RST_CH0_S)
+#define AXI_DMA_IN_RST_CH0_V  0x00000001U
+#define AXI_DMA_IN_RST_CH0_S  0
+/** AXI_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_LOOP_TEST_CH0    (BIT(1))
+#define AXI_DMA_IN_LOOP_TEST_CH0_M  (AXI_DMA_IN_LOOP_TEST_CH0_V << AXI_DMA_IN_LOOP_TEST_CH0_S)
+#define AXI_DMA_IN_LOOP_TEST_CH0_V  0x00000001U
+#define AXI_DMA_IN_LOOP_TEST_CH0_S  1
+/** AXI_DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+ *  AXI_DMA.
+ */
+#define AXI_DMA_MEM_TRANS_EN_CH0    (BIT(2))
+#define AXI_DMA_MEM_TRANS_EN_CH0_M  (AXI_DMA_MEM_TRANS_EN_CH0_V << AXI_DMA_MEM_TRANS_EN_CH0_S)
+#define AXI_DMA_MEM_TRANS_EN_CH0_V  0x00000001U
+#define AXI_DMA_MEM_TRANS_EN_CH0_S  2
+/** AXI_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_IN_ETM_EN_CH0    (BIT(3))
+#define AXI_DMA_IN_ETM_EN_CH0_M  (AXI_DMA_IN_ETM_EN_CH0_V << AXI_DMA_IN_ETM_EN_CH0_S)
+#define AXI_DMA_IN_ETM_EN_CH0_V  0x00000001U
+#define AXI_DMA_IN_ETM_EN_CH0_S  3
+/** AXI_DMA_IN_BURST_SIZE_SEL_CH0 : R/W; bitpos: [6:4]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0    0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0_M  (AXI_DMA_IN_BURST_SIZE_SEL_CH0_V << AXI_DMA_IN_BURST_SIZE_SEL_CH0_S)
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0_V  0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0_S  4
+/** AXI_DMA_IN_CMD_DISABLE_CH0 : R/W; bitpos: [7]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_IN_CMD_DISABLE_CH0    (BIT(7))
+#define AXI_DMA_IN_CMD_DISABLE_CH0_M  (AXI_DMA_IN_CMD_DISABLE_CH0_V << AXI_DMA_IN_CMD_DISABLE_CH0_S)
+#define AXI_DMA_IN_CMD_DISABLE_CH0_V  0x00000001U
+#define AXI_DMA_IN_CMD_DISABLE_CH0_S  7
+/** AXI_DMA_IN_ECC_AEC_EN_CH0 : R/W; bitpos: [8]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_IN_ECC_AEC_EN_CH0    (BIT(8))
+#define AXI_DMA_IN_ECC_AEC_EN_CH0_M  (AXI_DMA_IN_ECC_AEC_EN_CH0_V << AXI_DMA_IN_ECC_AEC_EN_CH0_S)
+#define AXI_DMA_IN_ECC_AEC_EN_CH0_V  0x00000001U
+#define AXI_DMA_IN_ECC_AEC_EN_CH0_S  8
+/** AXI_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_INDSCR_BURST_EN_CH0    (BIT(9))
+#define AXI_DMA_INDSCR_BURST_EN_CH0_M  (AXI_DMA_INDSCR_BURST_EN_CH0_V << AXI_DMA_INDSCR_BURST_EN_CH0_S)
+#define AXI_DMA_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define AXI_DMA_INDSCR_BURST_EN_CH0_S  9
+
+/** AXI_DMA_IN_CONF1_CH0_REG register
+ *  Configure 1 register of Rx channel 0
+ */
+#define AXI_DMA_IN_CONF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x14)
+/** AXI_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_IN_CHECK_OWNER_CH0    (BIT(12))
+#define AXI_DMA_IN_CHECK_OWNER_CH0_M  (AXI_DMA_IN_CHECK_OWNER_CH0_V << AXI_DMA_IN_CHECK_OWNER_CH0_S)
+#define AXI_DMA_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define AXI_DMA_IN_CHECK_OWNER_CH0_S  12
+
+/** AXI_DMA_INFIFO_STATUS_CH0_REG register
+ *  Receive FIFO status of Rx channel 0
+ */
+#define AXI_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AXI_DMA_BASE + 0x18)
+/** AXI_DMA_INFIFO_L3_FULL_CH0 : RO; bitpos: [0]; default: 1;
+ *  L3 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_FULL_CH0    (BIT(0))
+#define AXI_DMA_INFIFO_L3_FULL_CH0_M  (AXI_DMA_INFIFO_L3_FULL_CH0_V << AXI_DMA_INFIFO_L3_FULL_CH0_S)
+#define AXI_DMA_INFIFO_L3_FULL_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_FULL_CH0_S  0
+/** AXI_DMA_INFIFO_L3_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  L3 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0    (BIT(1))
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0_M  (AXI_DMA_INFIFO_L3_EMPTY_CH0_V << AXI_DMA_INFIFO_L3_EMPTY_CH0_S)
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0_S  1
+/** AXI_DMA_INFIFO_L3_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_CNT_CH0    0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH0_M  (AXI_DMA_INFIFO_L3_CNT_CH0_V << AXI_DMA_INFIFO_L3_CNT_CH0_S)
+#define AXI_DMA_INFIFO_L3_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH0_S  2
+/** AXI_DMA_INFIFO_L3_UDF_CH0 : RO; bitpos: [8]; default: 0;
+ *  L3 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0    (BIT(8))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_M  (AXI_DMA_INFIFO_L3_UDF_CH0_V << AXI_DMA_INFIFO_L3_UDF_CH0_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0 : RO; bitpos: [9]; default: 0;
+ *  L3 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_M  (AXI_DMA_INFIFO_L3_OVF_CH0_V << AXI_DMA_INFIFO_L3_OVF_CH0_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_S  9
+/** AXI_DMA_INFIFO_L1_FULL_CH0 : RO; bitpos: [10]; default: 0;
+ *  L1 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_FULL_CH0    (BIT(10))
+#define AXI_DMA_INFIFO_L1_FULL_CH0_M  (AXI_DMA_INFIFO_L1_FULL_CH0_V << AXI_DMA_INFIFO_L1_FULL_CH0_S)
+#define AXI_DMA_INFIFO_L1_FULL_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_FULL_CH0_S  10
+/** AXI_DMA_INFIFO_L1_EMPTY_CH0 : RO; bitpos: [11]; default: 1;
+ *  L1 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0    (BIT(11))
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0_M  (AXI_DMA_INFIFO_L1_EMPTY_CH0_V << AXI_DMA_INFIFO_L1_EMPTY_CH0_S)
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0_S  11
+/** AXI_DMA_INFIFO_L1_UDF_CH0 : RO; bitpos: [12]; default: 0;
+ *  L1 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0    (BIT(12))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_M  (AXI_DMA_INFIFO_L1_UDF_CH0_V << AXI_DMA_INFIFO_L1_UDF_CH0_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_S  12
+/** AXI_DMA_INFIFO_L1_OVF_CH0 : RO; bitpos: [13]; default: 0;
+ *  L1 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0    (BIT(13))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_M  (AXI_DMA_INFIFO_L1_OVF_CH0_V << AXI_DMA_INFIFO_L1_OVF_CH0_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_S  13
+/** AXI_DMA_INFIFO_L2_FULL_CH0 : RO; bitpos: [14]; default: 0;
+ *  L2 Rx RAM full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_FULL_CH0    (BIT(14))
+#define AXI_DMA_INFIFO_L2_FULL_CH0_M  (AXI_DMA_INFIFO_L2_FULL_CH0_V << AXI_DMA_INFIFO_L2_FULL_CH0_S)
+#define AXI_DMA_INFIFO_L2_FULL_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_FULL_CH0_S  14
+/** AXI_DMA_INFIFO_L2_EMPTY_CH0 : RO; bitpos: [15]; default: 1;
+ *  L2 Rx RAM empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0    (BIT(15))
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0_M  (AXI_DMA_INFIFO_L2_EMPTY_CH0_V << AXI_DMA_INFIFO_L2_EMPTY_CH0_S)
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0_S  15
+/** AXI_DMA_INFIFO_L2_UDF_CH0 : RO; bitpos: [16]; default: 0;
+ *  L2 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0    (BIT(16))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_M  (AXI_DMA_INFIFO_L2_UDF_CH0_V << AXI_DMA_INFIFO_L2_UDF_CH0_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_S  16
+/** AXI_DMA_INFIFO_L2_OVF_CH0 : RO; bitpos: [17]; default: 0;
+ *  L2 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0    (BIT(17))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_M  (AXI_DMA_INFIFO_L2_OVF_CH0_V << AXI_DMA_INFIFO_L2_OVF_CH0_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_S  17
+/** AXI_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_1B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_1B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0_S  23
+/** AXI_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_2B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_2B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0_S  24
+/** AXI_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_3B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_3B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0_S  25
+/** AXI_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_4B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_4B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0_S  26
+/** AXI_DMA_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0    (BIT(27))
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_5B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_5B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0_S  27
+/** AXI_DMA_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0    (BIT(28))
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_6B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_6B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0_S  28
+/** AXI_DMA_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0    (BIT(29))
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_7B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_7B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0_S  29
+/** AXI_DMA_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0    (BIT(30))
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_8B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_8B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0_S  30
+/** AXI_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_BUF_HUNGRY_CH0    (BIT(31))
+#define AXI_DMA_IN_BUF_HUNGRY_CH0_M  (AXI_DMA_IN_BUF_HUNGRY_CH0_V << AXI_DMA_IN_BUF_HUNGRY_CH0_S)
+#define AXI_DMA_IN_BUF_HUNGRY_CH0_V  0x00000001U
+#define AXI_DMA_IN_BUF_HUNGRY_CH0_S  31
+
+/** AXI_DMA_IN_POP_CH0_REG register
+ *  Pop control register of Rx channel 0
+ */
+#define AXI_DMA_IN_POP_CH0_REG (DR_REG_AXI_DMA_BASE + 0x1c)
+/** AXI_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048;
+ *  This register stores the data popping from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_RDATA_CH0    0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH0_M  (AXI_DMA_INFIFO_RDATA_CH0_V << AXI_DMA_INFIFO_RDATA_CH0_S)
+#define AXI_DMA_INFIFO_RDATA_CH0_V  0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH0_S  0
+/** AXI_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0;
+ *  Set this bit to pop data from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_POP_CH0    (BIT(12))
+#define AXI_DMA_INFIFO_POP_CH0_M  (AXI_DMA_INFIFO_POP_CH0_V << AXI_DMA_INFIFO_POP_CH0_S)
+#define AXI_DMA_INFIFO_POP_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_POP_CH0_S  12
+
+/** AXI_DMA_IN_LINK1_CH0_REG register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+#define AXI_DMA_IN_LINK1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x20)
+/** AXI_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address when there are some
+ *  errors in current receiving data.
+ */
+#define AXI_DMA_INLINK_AUTO_RET_CH0    (BIT(0))
+#define AXI_DMA_INLINK_AUTO_RET_CH0_M  (AXI_DMA_INLINK_AUTO_RET_CH0_V << AXI_DMA_INLINK_AUTO_RET_CH0_S)
+#define AXI_DMA_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_AUTO_RET_CH0_S  0
+/** AXI_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_STOP_CH0    (BIT(1))
+#define AXI_DMA_INLINK_STOP_CH0_M  (AXI_DMA_INLINK_STOP_CH0_V << AXI_DMA_INLINK_STOP_CH0_S)
+#define AXI_DMA_INLINK_STOP_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_STOP_CH0_S  1
+/** AXI_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_START_CH0    (BIT(2))
+#define AXI_DMA_INLINK_START_CH0_M  (AXI_DMA_INLINK_START_CH0_V << AXI_DMA_INLINK_START_CH0_S)
+#define AXI_DMA_INLINK_START_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_START_CH0_S  2
+/** AXI_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define AXI_DMA_INLINK_RESTART_CH0    (BIT(3))
+#define AXI_DMA_INLINK_RESTART_CH0_M  (AXI_DMA_INLINK_RESTART_CH0_V << AXI_DMA_INLINK_RESTART_CH0_S)
+#define AXI_DMA_INLINK_RESTART_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_RESTART_CH0_S  3
+/** AXI_DMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define AXI_DMA_INLINK_PARK_CH0    (BIT(4))
+#define AXI_DMA_INLINK_PARK_CH0_M  (AXI_DMA_INLINK_PARK_CH0_V << AXI_DMA_INLINK_PARK_CH0_S)
+#define AXI_DMA_INLINK_PARK_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_PARK_CH0_S  4
+
+/** AXI_DMA_IN_LINK2_CH0_REG register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+#define AXI_DMA_IN_LINK2_CH0_REG (DR_REG_AXI_DMA_BASE + 0x24)
+/** AXI_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first inlink descriptor's
+ *  address.
+ */
+#define AXI_DMA_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH0_M  (AXI_DMA_INLINK_ADDR_CH0_V << AXI_DMA_INLINK_ADDR_CH0_S)
+#define AXI_DMA_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_STATE_CH0_REG register
+ *  Receive status of Rx channel 0
+ */
+#define AXI_DMA_IN_STATE_CH0_REG (DR_REG_AXI_DMA_BASE + 0x28)
+/** AXI_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0_M  (AXI_DMA_INLINK_DSCR_ADDR_CH0_V << AXI_DMA_INLINK_DSCR_ADDR_CH0_S)
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0_S  0
+/** AXI_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_DSCR_STATE_CH0    0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH0_M  (AXI_DMA_IN_DSCR_STATE_CH0_V << AXI_DMA_IN_DSCR_STATE_CH0_S)
+#define AXI_DMA_IN_DSCR_STATE_CH0_V  0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH0_S  18
+/** AXI_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_STATE_CH0    0x00000007U
+#define AXI_DMA_IN_STATE_CH0_M  (AXI_DMA_IN_STATE_CH0_V << AXI_DMA_IN_STATE_CH0_S)
+#define AXI_DMA_IN_STATE_CH0_V  0x00000007U
+#define AXI_DMA_IN_STATE_CH0_S  20
+
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Inlink descriptor address when EOF occurs of Rx channel 0
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x2c)
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_M  (AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_V << AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Inlink descriptor address when errors occur of Rx channel 0
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x30)
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_M  (AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_DSCR_CH0_REG register
+ *  Current inlink descriptor address of Rx channel 0
+ */
+#define AXI_DMA_IN_DSCR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x34)
+/** AXI_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current inlink descriptor x.
+ */
+#define AXI_DMA_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH0_M  (AXI_DMA_INLINK_DSCR_CH0_V << AXI_DMA_INLINK_DSCR_CH0_S)
+#define AXI_DMA_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH0_S  0
+
+/** AXI_DMA_IN_DSCR_BF0_CH0_REG register
+ *  The last inlink descriptor address of Rx channel 0
+ */
+#define AXI_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x38)
+/** AXI_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor x-1.
+ */
+#define AXI_DMA_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH0_M  (AXI_DMA_INLINK_DSCR_BF0_CH0_V << AXI_DMA_INLINK_DSCR_BF0_CH0_S)
+#define AXI_DMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH0_S  0
+
+/** AXI_DMA_IN_DSCR_BF1_CH0_REG register
+ *  The second-to-last inlink descriptor address of Rx channel 0
+ */
+#define AXI_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x3c)
+/** AXI_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define AXI_DMA_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH0_M  (AXI_DMA_INLINK_DSCR_BF1_CH0_V << AXI_DMA_INLINK_DSCR_BF1_CH0_S)
+#define AXI_DMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH0_S  0
+
+/** AXI_DMA_IN_PRI_CH0_REG register
+ *  Priority register of Rx channel 0
+ */
+#define AXI_DMA_IN_PRI_CH0_REG (DR_REG_AXI_DMA_BASE + 0x40)
+/** AXI_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_RX_PRI_CH0    0x0000000FU
+#define AXI_DMA_RX_PRI_CH0_M  (AXI_DMA_RX_PRI_CH0_V << AXI_DMA_RX_PRI_CH0_S)
+#define AXI_DMA_RX_PRI_CH0_V  0x0000000FU
+#define AXI_DMA_RX_PRI_CH0_S  0
+/** AXI_DMA_RX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Rx channel 0
+ */
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0    0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0_M  (AXI_DMA_RX_CH_ARB_WEIGH_CH0_V << AXI_DMA_RX_CH_ARB_WEIGH_CH0_S)
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0_V  0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0_S  4
+/** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0    (BIT(8))
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S)
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V  0x00000001U
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S  8
+
+/** AXI_DMA_IN_PERI_SEL_CH0_REG register
+ *  Peripheral selection of Rx channel 0
+ */
+#define AXI_DMA_IN_PERI_SEL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x44)
+/** AXI_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_IN_SEL_CH0    0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH0_M  (AXI_DMA_PERI_IN_SEL_CH0_V << AXI_DMA_PERI_IN_SEL_CH0_S)
+#define AXI_DMA_PERI_IN_SEL_CH0_V  0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH0_S  0
+
+/** AXI_DMA_IN_CRC_INIT_DATA_CH0_REG register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x48)
+/** AXI_DMA_IN_CRC_INIT_DATA_CH0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_M  (AXI_DMA_IN_CRC_INIT_DATA_CH0_V << AXI_DMA_IN_CRC_INIT_DATA_CH0_S)
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_S  0
+
+/** AXI_DMA_RX_CRC_WIDTH_CH0_REG register
+ *  This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH0_REG (DR_REG_AXI_DMA_BASE + 0x4c)
+/** AXI_DMA_RX_CRC_WIDTH_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH0    0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH0_M  (AXI_DMA_RX_CRC_WIDTH_CH0_V << AXI_DMA_RX_CRC_WIDTH_CH0_S)
+#define AXI_DMA_RX_CRC_WIDTH_CH0_V  0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH0_S  0
+/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0    (BIT(2))
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_M  (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_S)
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_V  0x00000001U
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_S  2
+
+/** AXI_DMA_IN_CRC_CLEAR_CH0_REG register
+ *  This register is used to clear ch0 crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x50)
+/** AXI_DMA_IN_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH0    (BIT(0))
+#define AXI_DMA_IN_CRC_CLEAR_CH0_M  (AXI_DMA_IN_CRC_CLEAR_CH0_V << AXI_DMA_IN_CRC_CLEAR_CH0_S)
+#define AXI_DMA_IN_CRC_CLEAR_CH0_V  0x00000001U
+#define AXI_DMA_IN_CRC_CLEAR_CH0_S  0
+
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH0_REG register
+ *  This register is used to store ch0 crc result
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_REG (DR_REG_AXI_DMA_BASE + 0x54)
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_M  (AXI_DMA_IN_CRC_FINAL_RESULT_CH0_V << AXI_DMA_IN_CRC_FINAL_RESULT_CH0_S)
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_S  0
+
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH0_REG register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x58)
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_M  (AXI_DMA_RX_CRC_EN_WR_DATA_CH0_V << AXI_DMA_RX_CRC_EN_WR_DATA_CH0_S)
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_RX_CRC_EN_ADDR_CH0_REG register
+ *  This register is used to config ch0 crc en addr
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x5c)
+/** AXI_DMA_RX_CRC_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_M  (AXI_DMA_RX_CRC_EN_ADDR_CH0_V << AXI_DMA_RX_CRC_EN_ADDR_CH0_S)
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x60)
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0    0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_M  (AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_V << AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_S)
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_V  0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x64)
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_M  (AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_V << AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_S)
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_INT_RAW_CH1_REG register
+ *  Raw status interrupt of channel 1
+ */
+#define AXI_DMA_IN_INT_RAW_CH1_REG (DR_REG_AXI_DMA_BASE + 0x68)
+/** AXI_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_RAW_M  (AXI_DMA_IN_DONE_CH1_INT_RAW_V << AXI_DMA_IN_DONE_CH1_INT_RAW_S)
+#define AXI_DMA_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_RAW_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+ *  turns to high level when the last data pointed by one inlink descriptor has been
+ *  received and no data error is detected for Rx channel 0.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when data error is detected only in the
+ *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+ *  interrupt is reserved.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+ *  including owner error and the second and third word error of inlink descriptor for
+ *  Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+ *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_S  10
+
+/** AXI_DMA_IN_INT_ST_CH1_REG register
+ *  Masked interrupt of channel 1
+ */
+#define AXI_DMA_IN_INT_ST_CH1_REG (DR_REG_AXI_DMA_BASE + 0x6c)
+/** AXI_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_ST    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_ST_M  (AXI_DMA_IN_DONE_CH1_INT_ST_V << AXI_DMA_IN_DONE_CH1_INT_ST_S)
+#define AXI_DMA_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_ST_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_ST_V << AXI_DMA_IN_SUC_EOF_CH1_INT_ST_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_ST_V << AXI_DMA_IN_ERR_EOF_CH1_INT_ST_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S  4
+/** AXI_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST    (BIT(5))
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST_M  (AXI_DMA_INFIFO_OVF_CH1_INT_ST_V << AXI_DMA_INFIFO_OVF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST_S  5
+/** AXI_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST    (BIT(6))
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST_M  (AXI_DMA_INFIFO_UDF_CH1_INT_ST_V << AXI_DMA_INFIFO_UDF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST_S  6
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST    (BIT(7))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_S  7
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST    (BIT(8))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_S  10
+
+/** AXI_DMA_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of channel 1
+ */
+#define AXI_DMA_IN_INT_ENA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x70)
+/** AXI_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_ENA_M  (AXI_DMA_IN_DONE_CH1_INT_ENA_V << AXI_DMA_IN_DONE_CH1_INT_ENA_S)
+#define AXI_DMA_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_ENA_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_S  10
+
+/** AXI_DMA_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of channel 1
+ */
+#define AXI_DMA_IN_INT_CLR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x74)
+/** AXI_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_CLR_M  (AXI_DMA_IN_DONE_CH1_INT_CLR_V << AXI_DMA_IN_DONE_CH1_INT_CLR_S)
+#define AXI_DMA_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_CLR_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_S  10
+
+/** AXI_DMA_IN_CONF0_CH1_REG register
+ *  Configure 0 register of Rx channel 1
+ */
+#define AXI_DMA_IN_CONF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0x78)
+/** AXI_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+#define AXI_DMA_IN_RST_CH1    (BIT(0))
+#define AXI_DMA_IN_RST_CH1_M  (AXI_DMA_IN_RST_CH1_V << AXI_DMA_IN_RST_CH1_S)
+#define AXI_DMA_IN_RST_CH1_V  0x00000001U
+#define AXI_DMA_IN_RST_CH1_S  0
+/** AXI_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_LOOP_TEST_CH1    (BIT(1))
+#define AXI_DMA_IN_LOOP_TEST_CH1_M  (AXI_DMA_IN_LOOP_TEST_CH1_V << AXI_DMA_IN_LOOP_TEST_CH1_S)
+#define AXI_DMA_IN_LOOP_TEST_CH1_V  0x00000001U
+#define AXI_DMA_IN_LOOP_TEST_CH1_S  1
+/** AXI_DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+ *  AXI_DMA.
+ */
+#define AXI_DMA_MEM_TRANS_EN_CH1    (BIT(2))
+#define AXI_DMA_MEM_TRANS_EN_CH1_M  (AXI_DMA_MEM_TRANS_EN_CH1_V << AXI_DMA_MEM_TRANS_EN_CH1_S)
+#define AXI_DMA_MEM_TRANS_EN_CH1_V  0x00000001U
+#define AXI_DMA_MEM_TRANS_EN_CH1_S  2
+/** AXI_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_IN_ETM_EN_CH1    (BIT(3))
+#define AXI_DMA_IN_ETM_EN_CH1_M  (AXI_DMA_IN_ETM_EN_CH1_V << AXI_DMA_IN_ETM_EN_CH1_S)
+#define AXI_DMA_IN_ETM_EN_CH1_V  0x00000001U
+#define AXI_DMA_IN_ETM_EN_CH1_S  3
+/** AXI_DMA_IN_BURST_SIZE_SEL_CH1 : R/W; bitpos: [6:4]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1    0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1_M  (AXI_DMA_IN_BURST_SIZE_SEL_CH1_V << AXI_DMA_IN_BURST_SIZE_SEL_CH1_S)
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1_V  0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1_S  4
+/** AXI_DMA_IN_CMD_DISABLE_CH1 : R/W; bitpos: [7]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_IN_CMD_DISABLE_CH1    (BIT(7))
+#define AXI_DMA_IN_CMD_DISABLE_CH1_M  (AXI_DMA_IN_CMD_DISABLE_CH1_V << AXI_DMA_IN_CMD_DISABLE_CH1_S)
+#define AXI_DMA_IN_CMD_DISABLE_CH1_V  0x00000001U
+#define AXI_DMA_IN_CMD_DISABLE_CH1_S  7
+/** AXI_DMA_IN_ECC_AEC_EN_CH1 : R/W; bitpos: [8]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_IN_ECC_AEC_EN_CH1    (BIT(8))
+#define AXI_DMA_IN_ECC_AEC_EN_CH1_M  (AXI_DMA_IN_ECC_AEC_EN_CH1_V << AXI_DMA_IN_ECC_AEC_EN_CH1_S)
+#define AXI_DMA_IN_ECC_AEC_EN_CH1_V  0x00000001U
+#define AXI_DMA_IN_ECC_AEC_EN_CH1_S  8
+/** AXI_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_INDSCR_BURST_EN_CH1    (BIT(9))
+#define AXI_DMA_INDSCR_BURST_EN_CH1_M  (AXI_DMA_INDSCR_BURST_EN_CH1_V << AXI_DMA_INDSCR_BURST_EN_CH1_S)
+#define AXI_DMA_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define AXI_DMA_INDSCR_BURST_EN_CH1_S  9
+
+/** AXI_DMA_IN_CONF1_CH1_REG register
+ *  Configure 1 register of Rx channel 1
+ */
+#define AXI_DMA_IN_CONF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x7c)
+/** AXI_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_IN_CHECK_OWNER_CH1    (BIT(12))
+#define AXI_DMA_IN_CHECK_OWNER_CH1_M  (AXI_DMA_IN_CHECK_OWNER_CH1_V << AXI_DMA_IN_CHECK_OWNER_CH1_S)
+#define AXI_DMA_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define AXI_DMA_IN_CHECK_OWNER_CH1_S  12
+
+/** AXI_DMA_INFIFO_STATUS_CH1_REG register
+ *  Receive FIFO status of Rx channel 1
+ */
+#define AXI_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AXI_DMA_BASE + 0x80)
+/** AXI_DMA_INFIFO_L3_FULL_CH1 : RO; bitpos: [0]; default: 1;
+ *  L3 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_FULL_CH1    (BIT(0))
+#define AXI_DMA_INFIFO_L3_FULL_CH1_M  (AXI_DMA_INFIFO_L3_FULL_CH1_V << AXI_DMA_INFIFO_L3_FULL_CH1_S)
+#define AXI_DMA_INFIFO_L3_FULL_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_FULL_CH1_S  0
+/** AXI_DMA_INFIFO_L3_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  L3 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1    (BIT(1))
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1_M  (AXI_DMA_INFIFO_L3_EMPTY_CH1_V << AXI_DMA_INFIFO_L3_EMPTY_CH1_S)
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1_S  1
+/** AXI_DMA_INFIFO_L3_CNT_CH1 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_CNT_CH1    0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH1_M  (AXI_DMA_INFIFO_L3_CNT_CH1_V << AXI_DMA_INFIFO_L3_CNT_CH1_S)
+#define AXI_DMA_INFIFO_L3_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH1_S  2
+/** AXI_DMA_INFIFO_L3_UDF_CH1 : RO; bitpos: [8]; default: 0;
+ *  L3 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1    (BIT(8))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_M  (AXI_DMA_INFIFO_L3_UDF_CH1_V << AXI_DMA_INFIFO_L3_UDF_CH1_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1 : RO; bitpos: [9]; default: 0;
+ *  L3 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_M  (AXI_DMA_INFIFO_L3_OVF_CH1_V << AXI_DMA_INFIFO_L3_OVF_CH1_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_S  9
+/** AXI_DMA_INFIFO_L1_FULL_CH1 : RO; bitpos: [10]; default: 0;
+ *  L1 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_FULL_CH1    (BIT(10))
+#define AXI_DMA_INFIFO_L1_FULL_CH1_M  (AXI_DMA_INFIFO_L1_FULL_CH1_V << AXI_DMA_INFIFO_L1_FULL_CH1_S)
+#define AXI_DMA_INFIFO_L1_FULL_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_FULL_CH1_S  10
+/** AXI_DMA_INFIFO_L1_EMPTY_CH1 : RO; bitpos: [11]; default: 1;
+ *  L1 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1    (BIT(11))
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1_M  (AXI_DMA_INFIFO_L1_EMPTY_CH1_V << AXI_DMA_INFIFO_L1_EMPTY_CH1_S)
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1_S  11
+/** AXI_DMA_INFIFO_L1_UDF_CH1 : RO; bitpos: [12]; default: 0;
+ *  L1 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1    (BIT(12))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_M  (AXI_DMA_INFIFO_L1_UDF_CH1_V << AXI_DMA_INFIFO_L1_UDF_CH1_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_S  12
+/** AXI_DMA_INFIFO_L1_OVF_CH1 : RO; bitpos: [13]; default: 0;
+ *  L1 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1    (BIT(13))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_M  (AXI_DMA_INFIFO_L1_OVF_CH1_V << AXI_DMA_INFIFO_L1_OVF_CH1_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_S  13
+/** AXI_DMA_INFIFO_L2_FULL_CH1 : RO; bitpos: [14]; default: 0;
+ *  L2 Rx RAM full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_FULL_CH1    (BIT(14))
+#define AXI_DMA_INFIFO_L2_FULL_CH1_M  (AXI_DMA_INFIFO_L2_FULL_CH1_V << AXI_DMA_INFIFO_L2_FULL_CH1_S)
+#define AXI_DMA_INFIFO_L2_FULL_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_FULL_CH1_S  14
+/** AXI_DMA_INFIFO_L2_EMPTY_CH1 : RO; bitpos: [15]; default: 1;
+ *  L2 Rx RAM empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1    (BIT(15))
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1_M  (AXI_DMA_INFIFO_L2_EMPTY_CH1_V << AXI_DMA_INFIFO_L2_EMPTY_CH1_S)
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1_S  15
+/** AXI_DMA_INFIFO_L2_UDF_CH1 : RO; bitpos: [16]; default: 0;
+ *  L2 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1    (BIT(16))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_M  (AXI_DMA_INFIFO_L2_UDF_CH1_V << AXI_DMA_INFIFO_L2_UDF_CH1_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_S  16
+/** AXI_DMA_INFIFO_L2_OVF_CH1 : RO; bitpos: [17]; default: 0;
+ *  L2 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1    (BIT(17))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_M  (AXI_DMA_INFIFO_L2_OVF_CH1_V << AXI_DMA_INFIFO_L2_OVF_CH1_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_S  17
+/** AXI_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_1B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_1B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1_S  23
+/** AXI_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_2B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_2B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1_S  24
+/** AXI_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_3B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_3B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1_S  25
+/** AXI_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_4B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_4B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1_S  26
+/** AXI_DMA_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1    (BIT(27))
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_5B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_5B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1_S  27
+/** AXI_DMA_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1    (BIT(28))
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_6B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_6B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1_S  28
+/** AXI_DMA_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1    (BIT(29))
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_7B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_7B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1_S  29
+/** AXI_DMA_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1    (BIT(30))
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_8B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_8B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1_S  30
+/** AXI_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_BUF_HUNGRY_CH1    (BIT(31))
+#define AXI_DMA_IN_BUF_HUNGRY_CH1_M  (AXI_DMA_IN_BUF_HUNGRY_CH1_V << AXI_DMA_IN_BUF_HUNGRY_CH1_S)
+#define AXI_DMA_IN_BUF_HUNGRY_CH1_V  0x00000001U
+#define AXI_DMA_IN_BUF_HUNGRY_CH1_S  31
+
+/** AXI_DMA_IN_POP_CH1_REG register
+ *  Pop control register of Rx channel 1
+ */
+#define AXI_DMA_IN_POP_CH1_REG (DR_REG_AXI_DMA_BASE + 0x84)
+/** AXI_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048;
+ *  This register stores the data popping from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_RDATA_CH1    0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH1_M  (AXI_DMA_INFIFO_RDATA_CH1_V << AXI_DMA_INFIFO_RDATA_CH1_S)
+#define AXI_DMA_INFIFO_RDATA_CH1_V  0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH1_S  0
+/** AXI_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0;
+ *  Set this bit to pop data from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_POP_CH1    (BIT(12))
+#define AXI_DMA_INFIFO_POP_CH1_M  (AXI_DMA_INFIFO_POP_CH1_V << AXI_DMA_INFIFO_POP_CH1_S)
+#define AXI_DMA_INFIFO_POP_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_POP_CH1_S  12
+
+/** AXI_DMA_IN_LINK1_CH1_REG register
+ *  Link descriptor configure and control register of Rx channel 1
+ */
+#define AXI_DMA_IN_LINK1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x88)
+/** AXI_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address when there are some
+ *  errors in current receiving data.
+ */
+#define AXI_DMA_INLINK_AUTO_RET_CH1    (BIT(0))
+#define AXI_DMA_INLINK_AUTO_RET_CH1_M  (AXI_DMA_INLINK_AUTO_RET_CH1_V << AXI_DMA_INLINK_AUTO_RET_CH1_S)
+#define AXI_DMA_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_AUTO_RET_CH1_S  0
+/** AXI_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_STOP_CH1    (BIT(1))
+#define AXI_DMA_INLINK_STOP_CH1_M  (AXI_DMA_INLINK_STOP_CH1_V << AXI_DMA_INLINK_STOP_CH1_S)
+#define AXI_DMA_INLINK_STOP_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_STOP_CH1_S  1
+/** AXI_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_START_CH1    (BIT(2))
+#define AXI_DMA_INLINK_START_CH1_M  (AXI_DMA_INLINK_START_CH1_V << AXI_DMA_INLINK_START_CH1_S)
+#define AXI_DMA_INLINK_START_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_START_CH1_S  2
+/** AXI_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define AXI_DMA_INLINK_RESTART_CH1    (BIT(3))
+#define AXI_DMA_INLINK_RESTART_CH1_M  (AXI_DMA_INLINK_RESTART_CH1_V << AXI_DMA_INLINK_RESTART_CH1_S)
+#define AXI_DMA_INLINK_RESTART_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_RESTART_CH1_S  3
+/** AXI_DMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define AXI_DMA_INLINK_PARK_CH1    (BIT(4))
+#define AXI_DMA_INLINK_PARK_CH1_M  (AXI_DMA_INLINK_PARK_CH1_V << AXI_DMA_INLINK_PARK_CH1_S)
+#define AXI_DMA_INLINK_PARK_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_PARK_CH1_S  4
+
+/** AXI_DMA_IN_LINK2_CH1_REG register
+ *  Link descriptor configure and control register of Rx channel 1
+ */
+#define AXI_DMA_IN_LINK2_CH1_REG (DR_REG_AXI_DMA_BASE + 0x8c)
+/** AXI_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first inlink descriptor's
+ *  address.
+ */
+#define AXI_DMA_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH1_M  (AXI_DMA_INLINK_ADDR_CH1_V << AXI_DMA_INLINK_ADDR_CH1_S)
+#define AXI_DMA_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_STATE_CH1_REG register
+ *  Receive status of Rx channel 1
+ */
+#define AXI_DMA_IN_STATE_CH1_REG (DR_REG_AXI_DMA_BASE + 0x90)
+/** AXI_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1_M  (AXI_DMA_INLINK_DSCR_ADDR_CH1_V << AXI_DMA_INLINK_DSCR_ADDR_CH1_S)
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1_S  0
+/** AXI_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_DSCR_STATE_CH1    0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH1_M  (AXI_DMA_IN_DSCR_STATE_CH1_V << AXI_DMA_IN_DSCR_STATE_CH1_S)
+#define AXI_DMA_IN_DSCR_STATE_CH1_V  0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH1_S  18
+/** AXI_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_STATE_CH1    0x00000007U
+#define AXI_DMA_IN_STATE_CH1_M  (AXI_DMA_IN_STATE_CH1_V << AXI_DMA_IN_STATE_CH1_S)
+#define AXI_DMA_IN_STATE_CH1_V  0x00000007U
+#define AXI_DMA_IN_STATE_CH1_S  20
+
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Inlink descriptor address when EOF occurs of Rx channel 1
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x94)
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_M  (AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_V << AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Inlink descriptor address when errors occur of Rx channel 1
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x98)
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_M  (AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_DSCR_CH1_REG register
+ *  Current inlink descriptor address of Rx channel 1
+ */
+#define AXI_DMA_IN_DSCR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x9c)
+/** AXI_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current inlink descriptor x.
+ */
+#define AXI_DMA_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH1_M  (AXI_DMA_INLINK_DSCR_CH1_V << AXI_DMA_INLINK_DSCR_CH1_S)
+#define AXI_DMA_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH1_S  0
+
+/** AXI_DMA_IN_DSCR_BF0_CH1_REG register
+ *  The last inlink descriptor address of Rx channel 1
+ */
+#define AXI_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0xa0)
+/** AXI_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor x-1.
+ */
+#define AXI_DMA_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH1_M  (AXI_DMA_INLINK_DSCR_BF0_CH1_V << AXI_DMA_INLINK_DSCR_BF0_CH1_S)
+#define AXI_DMA_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH1_S  0
+
+/** AXI_DMA_IN_DSCR_BF1_CH1_REG register
+ *  The second-to-last inlink descriptor address of Rx channel 1
+ */
+#define AXI_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0xa4)
+/** AXI_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define AXI_DMA_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH1_M  (AXI_DMA_INLINK_DSCR_BF1_CH1_V << AXI_DMA_INLINK_DSCR_BF1_CH1_S)
+#define AXI_DMA_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH1_S  0
+
+/** AXI_DMA_IN_PRI_CH1_REG register
+ *  Priority register of Rx channel 1
+ */
+#define AXI_DMA_IN_PRI_CH1_REG (DR_REG_AXI_DMA_BASE + 0xa8)
+/** AXI_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_RX_PRI_CH1    0x0000000FU
+#define AXI_DMA_RX_PRI_CH1_M  (AXI_DMA_RX_PRI_CH1_V << AXI_DMA_RX_PRI_CH1_S)
+#define AXI_DMA_RX_PRI_CH1_V  0x0000000FU
+#define AXI_DMA_RX_PRI_CH1_S  0
+/** AXI_DMA_RX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Rx channel 0
+ */
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1    0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1_M  (AXI_DMA_RX_CH_ARB_WEIGH_CH1_V << AXI_DMA_RX_CH_ARB_WEIGH_CH1_S)
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1_V  0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1_S  4
+/** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1    (BIT(8))
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S)
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V  0x00000001U
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S  8
+
+/** AXI_DMA_IN_PERI_SEL_CH1_REG register
+ *  Peripheral selection of Rx channel 1
+ */
+#define AXI_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AXI_DMA_BASE + 0xac)
+/** AXI_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_IN_SEL_CH1    0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH1_M  (AXI_DMA_PERI_IN_SEL_CH1_V << AXI_DMA_PERI_IN_SEL_CH1_S)
+#define AXI_DMA_PERI_IN_SEL_CH1_V  0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH1_S  0
+
+/** AXI_DMA_IN_CRC_INIT_DATA_CH1_REG register
+ *  This register is used to config ch1 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0xb0)
+/** AXI_DMA_IN_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_M  (AXI_DMA_IN_CRC_INIT_DATA_CH1_V << AXI_DMA_IN_CRC_INIT_DATA_CH1_S)
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_S  0
+
+/** AXI_DMA_RX_CRC_WIDTH_CH1_REG register
+ *  This register is used to confiig rx ch1 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH1_REG (DR_REG_AXI_DMA_BASE + 0xb4)
+/** AXI_DMA_RX_CRC_WIDTH_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH1    0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH1_M  (AXI_DMA_RX_CRC_WIDTH_CH1_V << AXI_DMA_RX_CRC_WIDTH_CH1_S)
+#define AXI_DMA_RX_CRC_WIDTH_CH1_V  0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH1_S  0
+/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1    (BIT(2))
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_M  (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_S)
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_V  0x00000001U
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_S  2
+
+/** AXI_DMA_IN_CRC_CLEAR_CH1_REG register
+ *  This register is used to clear ch1 crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH1_REG (DR_REG_AXI_DMA_BASE + 0xb8)
+/** AXI_DMA_IN_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH1    (BIT(0))
+#define AXI_DMA_IN_CRC_CLEAR_CH1_M  (AXI_DMA_IN_CRC_CLEAR_CH1_V << AXI_DMA_IN_CRC_CLEAR_CH1_S)
+#define AXI_DMA_IN_CRC_CLEAR_CH1_V  0x00000001U
+#define AXI_DMA_IN_CRC_CLEAR_CH1_S  0
+
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH1_REG register
+ *  This register is used to store ch1 crc result
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_REG (DR_REG_AXI_DMA_BASE + 0xbc)
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_M  (AXI_DMA_IN_CRC_FINAL_RESULT_CH1_V << AXI_DMA_IN_CRC_FINAL_RESULT_CH1_S)
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_S  0
+
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH1_REG register
+ *  This resister is used to config ch1 crc en for every bit
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0xc0)
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_M  (AXI_DMA_RX_CRC_EN_WR_DATA_CH1_V << AXI_DMA_RX_CRC_EN_WR_DATA_CH1_S)
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_RX_CRC_EN_ADDR_CH1_REG register
+ *  This register is used to config ch1 crc en addr
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0xc4)
+/** AXI_DMA_RX_CRC_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_M  (AXI_DMA_RX_CRC_EN_ADDR_CH1_V << AXI_DMA_RX_CRC_EN_ADDR_CH1_S)
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0xc8)
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1    0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_M  (AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_V << AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_S)
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_V  0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0xcc)
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_M  (AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_V << AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_S)
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_INT_RAW_CH2_REG register
+ *  Raw status interrupt of channel 2
+ */
+#define AXI_DMA_IN_INT_RAW_CH2_REG (DR_REG_AXI_DMA_BASE + 0xd0)
+/** AXI_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_RAW_M  (AXI_DMA_IN_DONE_CH2_INT_RAW_V << AXI_DMA_IN_DONE_CH2_INT_RAW_S)
+#define AXI_DMA_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_RAW_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+ *  turns to high level when the last data pointed by one inlink descriptor has been
+ *  received and no data error is detected for Rx channel 0.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_V << AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when data error is detected only in the
+ *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+ *  interrupt is reserved.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_V << AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+ *  including owner error and the second and third word error of inlink descriptor for
+ *  Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+ *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_S  10
+
+/** AXI_DMA_IN_INT_ST_CH2_REG register
+ *  Masked interrupt of channel 2
+ */
+#define AXI_DMA_IN_INT_ST_CH2_REG (DR_REG_AXI_DMA_BASE + 0xd4)
+/** AXI_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_ST    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_ST_M  (AXI_DMA_IN_DONE_CH2_INT_ST_V << AXI_DMA_IN_DONE_CH2_INT_ST_S)
+#define AXI_DMA_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_ST_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_ST_V << AXI_DMA_IN_SUC_EOF_CH2_INT_ST_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_ST_V << AXI_DMA_IN_ERR_EOF_CH2_INT_ST_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S  4
+/** AXI_DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST    (BIT(5))
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST_M  (AXI_DMA_INFIFO_OVF_CH2_INT_ST_V << AXI_DMA_INFIFO_OVF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST_S  5
+/** AXI_DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST    (BIT(6))
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST_M  (AXI_DMA_INFIFO_UDF_CH2_INT_ST_V << AXI_DMA_INFIFO_UDF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST_S  6
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST    (BIT(7))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_S  7
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST    (BIT(8))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_S  10
+
+/** AXI_DMA_IN_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of channel 2
+ */
+#define AXI_DMA_IN_INT_ENA_CH2_REG (DR_REG_AXI_DMA_BASE + 0xd8)
+/** AXI_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_ENA_M  (AXI_DMA_IN_DONE_CH2_INT_ENA_V << AXI_DMA_IN_DONE_CH2_INT_ENA_S)
+#define AXI_DMA_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_ENA_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_V << AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_V << AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_S  10
+
+/** AXI_DMA_IN_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of channel 2
+ */
+#define AXI_DMA_IN_INT_CLR_CH2_REG (DR_REG_AXI_DMA_BASE + 0xdc)
+/** AXI_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_CLR_M  (AXI_DMA_IN_DONE_CH2_INT_CLR_V << AXI_DMA_IN_DONE_CH2_INT_CLR_S)
+#define AXI_DMA_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_CLR_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_V << AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_V << AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_S  10
+
+/** AXI_DMA_IN_CONF0_CH2_REG register
+ *  Configure 0 register of Rx channel 2
+ */
+#define AXI_DMA_IN_CONF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0xe0)
+/** AXI_DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+#define AXI_DMA_IN_RST_CH2    (BIT(0))
+#define AXI_DMA_IN_RST_CH2_M  (AXI_DMA_IN_RST_CH2_V << AXI_DMA_IN_RST_CH2_S)
+#define AXI_DMA_IN_RST_CH2_V  0x00000001U
+#define AXI_DMA_IN_RST_CH2_S  0
+/** AXI_DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_LOOP_TEST_CH2    (BIT(1))
+#define AXI_DMA_IN_LOOP_TEST_CH2_M  (AXI_DMA_IN_LOOP_TEST_CH2_V << AXI_DMA_IN_LOOP_TEST_CH2_S)
+#define AXI_DMA_IN_LOOP_TEST_CH2_V  0x00000001U
+#define AXI_DMA_IN_LOOP_TEST_CH2_S  1
+/** AXI_DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+ *  AXI_DMA.
+ */
+#define AXI_DMA_MEM_TRANS_EN_CH2    (BIT(2))
+#define AXI_DMA_MEM_TRANS_EN_CH2_M  (AXI_DMA_MEM_TRANS_EN_CH2_V << AXI_DMA_MEM_TRANS_EN_CH2_S)
+#define AXI_DMA_MEM_TRANS_EN_CH2_V  0x00000001U
+#define AXI_DMA_MEM_TRANS_EN_CH2_S  2
+/** AXI_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_IN_ETM_EN_CH2    (BIT(3))
+#define AXI_DMA_IN_ETM_EN_CH2_M  (AXI_DMA_IN_ETM_EN_CH2_V << AXI_DMA_IN_ETM_EN_CH2_S)
+#define AXI_DMA_IN_ETM_EN_CH2_V  0x00000001U
+#define AXI_DMA_IN_ETM_EN_CH2_S  3
+/** AXI_DMA_IN_BURST_SIZE_SEL_CH2 : R/W; bitpos: [6:4]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2    0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2_M  (AXI_DMA_IN_BURST_SIZE_SEL_CH2_V << AXI_DMA_IN_BURST_SIZE_SEL_CH2_S)
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2_V  0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2_S  4
+/** AXI_DMA_IN_CMD_DISABLE_CH2 : R/W; bitpos: [7]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_IN_CMD_DISABLE_CH2    (BIT(7))
+#define AXI_DMA_IN_CMD_DISABLE_CH2_M  (AXI_DMA_IN_CMD_DISABLE_CH2_V << AXI_DMA_IN_CMD_DISABLE_CH2_S)
+#define AXI_DMA_IN_CMD_DISABLE_CH2_V  0x00000001U
+#define AXI_DMA_IN_CMD_DISABLE_CH2_S  7
+/** AXI_DMA_IN_ECC_AEC_EN_CH2 : R/W; bitpos: [8]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_IN_ECC_AEC_EN_CH2    (BIT(8))
+#define AXI_DMA_IN_ECC_AEC_EN_CH2_M  (AXI_DMA_IN_ECC_AEC_EN_CH2_V << AXI_DMA_IN_ECC_AEC_EN_CH2_S)
+#define AXI_DMA_IN_ECC_AEC_EN_CH2_V  0x00000001U
+#define AXI_DMA_IN_ECC_AEC_EN_CH2_S  8
+/** AXI_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_INDSCR_BURST_EN_CH2    (BIT(9))
+#define AXI_DMA_INDSCR_BURST_EN_CH2_M  (AXI_DMA_INDSCR_BURST_EN_CH2_V << AXI_DMA_INDSCR_BURST_EN_CH2_S)
+#define AXI_DMA_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define AXI_DMA_INDSCR_BURST_EN_CH2_S  9
+
+/** AXI_DMA_IN_CONF1_CH2_REG register
+ *  Configure 1 register of Rx channel 2
+ */
+#define AXI_DMA_IN_CONF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0xe4)
+/** AXI_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_IN_CHECK_OWNER_CH2    (BIT(12))
+#define AXI_DMA_IN_CHECK_OWNER_CH2_M  (AXI_DMA_IN_CHECK_OWNER_CH2_V << AXI_DMA_IN_CHECK_OWNER_CH2_S)
+#define AXI_DMA_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define AXI_DMA_IN_CHECK_OWNER_CH2_S  12
+
+/** AXI_DMA_INFIFO_STATUS_CH2_REG register
+ *  Receive FIFO status of Rx channel 2
+ */
+#define AXI_DMA_INFIFO_STATUS_CH2_REG (DR_REG_AXI_DMA_BASE + 0xe8)
+/** AXI_DMA_INFIFO_L3_FULL_CH2 : RO; bitpos: [0]; default: 1;
+ *  L3 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_FULL_CH2    (BIT(0))
+#define AXI_DMA_INFIFO_L3_FULL_CH2_M  (AXI_DMA_INFIFO_L3_FULL_CH2_V << AXI_DMA_INFIFO_L3_FULL_CH2_S)
+#define AXI_DMA_INFIFO_L3_FULL_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_FULL_CH2_S  0
+/** AXI_DMA_INFIFO_L3_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  L3 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2    (BIT(1))
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2_M  (AXI_DMA_INFIFO_L3_EMPTY_CH2_V << AXI_DMA_INFIFO_L3_EMPTY_CH2_S)
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2_S  1
+/** AXI_DMA_INFIFO_L3_CNT_CH2 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_CNT_CH2    0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH2_M  (AXI_DMA_INFIFO_L3_CNT_CH2_V << AXI_DMA_INFIFO_L3_CNT_CH2_S)
+#define AXI_DMA_INFIFO_L3_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH2_S  2
+/** AXI_DMA_INFIFO_L3_UDF_CH2 : RO; bitpos: [8]; default: 0;
+ *  L3 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2    (BIT(8))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_M  (AXI_DMA_INFIFO_L3_UDF_CH2_V << AXI_DMA_INFIFO_L3_UDF_CH2_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2 : RO; bitpos: [9]; default: 0;
+ *  L3 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_M  (AXI_DMA_INFIFO_L3_OVF_CH2_V << AXI_DMA_INFIFO_L3_OVF_CH2_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_S  9
+/** AXI_DMA_INFIFO_L1_FULL_CH2 : RO; bitpos: [10]; default: 0;
+ *  L1 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_FULL_CH2    (BIT(10))
+#define AXI_DMA_INFIFO_L1_FULL_CH2_M  (AXI_DMA_INFIFO_L1_FULL_CH2_V << AXI_DMA_INFIFO_L1_FULL_CH2_S)
+#define AXI_DMA_INFIFO_L1_FULL_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_FULL_CH2_S  10
+/** AXI_DMA_INFIFO_L1_EMPTY_CH2 : RO; bitpos: [11]; default: 1;
+ *  L1 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2    (BIT(11))
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2_M  (AXI_DMA_INFIFO_L1_EMPTY_CH2_V << AXI_DMA_INFIFO_L1_EMPTY_CH2_S)
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2_S  11
+/** AXI_DMA_INFIFO_L1_UDF_CH2 : RO; bitpos: [12]; default: 0;
+ *  L1 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2    (BIT(12))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_M  (AXI_DMA_INFIFO_L1_UDF_CH2_V << AXI_DMA_INFIFO_L1_UDF_CH2_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_S  12
+/** AXI_DMA_INFIFO_L1_OVF_CH2 : RO; bitpos: [13]; default: 0;
+ *  L1 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2    (BIT(13))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_M  (AXI_DMA_INFIFO_L1_OVF_CH2_V << AXI_DMA_INFIFO_L1_OVF_CH2_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_S  13
+/** AXI_DMA_INFIFO_L2_FULL_CH2 : RO; bitpos: [14]; default: 0;
+ *  L2 Rx RAM full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_FULL_CH2    (BIT(14))
+#define AXI_DMA_INFIFO_L2_FULL_CH2_M  (AXI_DMA_INFIFO_L2_FULL_CH2_V << AXI_DMA_INFIFO_L2_FULL_CH2_S)
+#define AXI_DMA_INFIFO_L2_FULL_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_FULL_CH2_S  14
+/** AXI_DMA_INFIFO_L2_EMPTY_CH2 : RO; bitpos: [15]; default: 1;
+ *  L2 Rx RAM empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2    (BIT(15))
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2_M  (AXI_DMA_INFIFO_L2_EMPTY_CH2_V << AXI_DMA_INFIFO_L2_EMPTY_CH2_S)
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2_S  15
+/** AXI_DMA_INFIFO_L2_UDF_CH2 : RO; bitpos: [16]; default: 0;
+ *  L2 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2    (BIT(16))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_M  (AXI_DMA_INFIFO_L2_UDF_CH2_V << AXI_DMA_INFIFO_L2_UDF_CH2_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_S  16
+/** AXI_DMA_INFIFO_L2_OVF_CH2 : RO; bitpos: [17]; default: 0;
+ *  L2 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2    (BIT(17))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_M  (AXI_DMA_INFIFO_L2_OVF_CH2_V << AXI_DMA_INFIFO_L2_OVF_CH2_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_S  17
+/** AXI_DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_1B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_1B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2_S  23
+/** AXI_DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_2B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_2B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2_S  24
+/** AXI_DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_3B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_3B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2_S  25
+/** AXI_DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_4B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_4B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2_S  26
+/** AXI_DMA_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2    (BIT(27))
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_5B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_5B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2_S  27
+/** AXI_DMA_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2    (BIT(28))
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_6B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_6B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2_S  28
+/** AXI_DMA_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2    (BIT(29))
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_7B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_7B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2_S  29
+/** AXI_DMA_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2    (BIT(30))
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_8B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_8B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2_S  30
+/** AXI_DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_BUF_HUNGRY_CH2    (BIT(31))
+#define AXI_DMA_IN_BUF_HUNGRY_CH2_M  (AXI_DMA_IN_BUF_HUNGRY_CH2_V << AXI_DMA_IN_BUF_HUNGRY_CH2_S)
+#define AXI_DMA_IN_BUF_HUNGRY_CH2_V  0x00000001U
+#define AXI_DMA_IN_BUF_HUNGRY_CH2_S  31
+
+/** AXI_DMA_IN_POP_CH2_REG register
+ *  Pop control register of Rx channel 2
+ */
+#define AXI_DMA_IN_POP_CH2_REG (DR_REG_AXI_DMA_BASE + 0xec)
+/** AXI_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048;
+ *  This register stores the data popping from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_RDATA_CH2    0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH2_M  (AXI_DMA_INFIFO_RDATA_CH2_V << AXI_DMA_INFIFO_RDATA_CH2_S)
+#define AXI_DMA_INFIFO_RDATA_CH2_V  0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH2_S  0
+/** AXI_DMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0;
+ *  Set this bit to pop data from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_POP_CH2    (BIT(12))
+#define AXI_DMA_INFIFO_POP_CH2_M  (AXI_DMA_INFIFO_POP_CH2_V << AXI_DMA_INFIFO_POP_CH2_S)
+#define AXI_DMA_INFIFO_POP_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_POP_CH2_S  12
+
+/** AXI_DMA_IN_LINK1_CH2_REG register
+ *  Link descriptor configure and control register of Rx channel 2
+ */
+#define AXI_DMA_IN_LINK1_CH2_REG (DR_REG_AXI_DMA_BASE + 0xf0)
+/** AXI_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address when there are some
+ *  errors in current receiving data.
+ */
+#define AXI_DMA_INLINK_AUTO_RET_CH2    (BIT(0))
+#define AXI_DMA_INLINK_AUTO_RET_CH2_M  (AXI_DMA_INLINK_AUTO_RET_CH2_V << AXI_DMA_INLINK_AUTO_RET_CH2_S)
+#define AXI_DMA_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_AUTO_RET_CH2_S  0
+/** AXI_DMA_INLINK_STOP_CH2 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_STOP_CH2    (BIT(1))
+#define AXI_DMA_INLINK_STOP_CH2_M  (AXI_DMA_INLINK_STOP_CH2_V << AXI_DMA_INLINK_STOP_CH2_S)
+#define AXI_DMA_INLINK_STOP_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_STOP_CH2_S  1
+/** AXI_DMA_INLINK_START_CH2 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_START_CH2    (BIT(2))
+#define AXI_DMA_INLINK_START_CH2_M  (AXI_DMA_INLINK_START_CH2_V << AXI_DMA_INLINK_START_CH2_S)
+#define AXI_DMA_INLINK_START_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_START_CH2_S  2
+/** AXI_DMA_INLINK_RESTART_CH2 : WT; bitpos: [3]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define AXI_DMA_INLINK_RESTART_CH2    (BIT(3))
+#define AXI_DMA_INLINK_RESTART_CH2_M  (AXI_DMA_INLINK_RESTART_CH2_V << AXI_DMA_INLINK_RESTART_CH2_S)
+#define AXI_DMA_INLINK_RESTART_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_RESTART_CH2_S  3
+/** AXI_DMA_INLINK_PARK_CH2 : RO; bitpos: [4]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define AXI_DMA_INLINK_PARK_CH2    (BIT(4))
+#define AXI_DMA_INLINK_PARK_CH2_M  (AXI_DMA_INLINK_PARK_CH2_V << AXI_DMA_INLINK_PARK_CH2_S)
+#define AXI_DMA_INLINK_PARK_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_PARK_CH2_S  4
+
+/** AXI_DMA_IN_LINK2_CH2_REG register
+ *  Link descriptor configure and control register of Rx channel 2
+ */
+#define AXI_DMA_IN_LINK2_CH2_REG (DR_REG_AXI_DMA_BASE + 0xf4)
+/** AXI_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first inlink descriptor's
+ *  address.
+ */
+#define AXI_DMA_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH2_M  (AXI_DMA_INLINK_ADDR_CH2_V << AXI_DMA_INLINK_ADDR_CH2_S)
+#define AXI_DMA_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH2_S  0
+
+/** AXI_DMA_IN_STATE_CH2_REG register
+ *  Receive status of Rx channel 2
+ */
+#define AXI_DMA_IN_STATE_CH2_REG (DR_REG_AXI_DMA_BASE + 0xf8)
+/** AXI_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2_M  (AXI_DMA_INLINK_DSCR_ADDR_CH2_V << AXI_DMA_INLINK_DSCR_ADDR_CH2_S)
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2_S  0
+/** AXI_DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_DSCR_STATE_CH2    0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH2_M  (AXI_DMA_IN_DSCR_STATE_CH2_V << AXI_DMA_IN_DSCR_STATE_CH2_S)
+#define AXI_DMA_IN_DSCR_STATE_CH2_V  0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH2_S  18
+/** AXI_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_STATE_CH2    0x00000007U
+#define AXI_DMA_IN_STATE_CH2_M  (AXI_DMA_IN_STATE_CH2_V << AXI_DMA_IN_STATE_CH2_S)
+#define AXI_DMA_IN_STATE_CH2_V  0x00000007U
+#define AXI_DMA_IN_STATE_CH2_S  20
+
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  Inlink descriptor address when EOF occurs of Rx channel 2
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0xfc)
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_M  (AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_V << AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  Inlink descriptor address when errors occur of Rx channel 2
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x100)
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_M  (AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_V << AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_IN_DSCR_CH2_REG register
+ *  Current inlink descriptor address of Rx channel 2
+ */
+#define AXI_DMA_IN_DSCR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x104)
+/** AXI_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current inlink descriptor x.
+ */
+#define AXI_DMA_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH2_M  (AXI_DMA_INLINK_DSCR_CH2_V << AXI_DMA_INLINK_DSCR_CH2_S)
+#define AXI_DMA_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH2_S  0
+
+/** AXI_DMA_IN_DSCR_BF0_CH2_REG register
+ *  The last inlink descriptor address of Rx channel 2
+ */
+#define AXI_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0x108)
+/** AXI_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor x-1.
+ */
+#define AXI_DMA_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH2_M  (AXI_DMA_INLINK_DSCR_BF0_CH2_V << AXI_DMA_INLINK_DSCR_BF0_CH2_S)
+#define AXI_DMA_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH2_S  0
+
+/** AXI_DMA_IN_DSCR_BF1_CH2_REG register
+ *  The second-to-last inlink descriptor address of Rx channel 2
+ */
+#define AXI_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x10c)
+/** AXI_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define AXI_DMA_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH2_M  (AXI_DMA_INLINK_DSCR_BF1_CH2_V << AXI_DMA_INLINK_DSCR_BF1_CH2_S)
+#define AXI_DMA_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH2_S  0
+
+/** AXI_DMA_IN_PRI_CH2_REG register
+ *  Priority register of Rx channel 2
+ */
+#define AXI_DMA_IN_PRI_CH2_REG (DR_REG_AXI_DMA_BASE + 0x110)
+/** AXI_DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_RX_PRI_CH2    0x0000000FU
+#define AXI_DMA_RX_PRI_CH2_M  (AXI_DMA_RX_PRI_CH2_V << AXI_DMA_RX_PRI_CH2_S)
+#define AXI_DMA_RX_PRI_CH2_V  0x0000000FU
+#define AXI_DMA_RX_PRI_CH2_S  0
+/** AXI_DMA_RX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Rx channel 0
+ */
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2    0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2_M  (AXI_DMA_RX_CH_ARB_WEIGH_CH2_V << AXI_DMA_RX_CH_ARB_WEIGH_CH2_S)
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2_V  0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2_S  4
+/** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2    (BIT(8))
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S)
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V  0x00000001U
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S  8
+
+/** AXI_DMA_IN_PERI_SEL_CH2_REG register
+ *  Peripheral selection of Rx channel 2
+ */
+#define AXI_DMA_IN_PERI_SEL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x114)
+/** AXI_DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_IN_SEL_CH2    0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH2_M  (AXI_DMA_PERI_IN_SEL_CH2_V << AXI_DMA_PERI_IN_SEL_CH2_S)
+#define AXI_DMA_PERI_IN_SEL_CH2_V  0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH2_S  0
+
+/** AXI_DMA_IN_CRC_INIT_DATA_CH2_REG register
+ *  This register is used to config ch2 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x118)
+/** AXI_DMA_IN_CRC_INIT_DATA_CH2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_M  (AXI_DMA_IN_CRC_INIT_DATA_CH2_V << AXI_DMA_IN_CRC_INIT_DATA_CH2_S)
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_S  0
+
+/** AXI_DMA_RX_CRC_WIDTH_CH2_REG register
+ *  This register is used to confiig rx ch2 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH2_REG (DR_REG_AXI_DMA_BASE + 0x11c)
+/** AXI_DMA_RX_CRC_WIDTH_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH2    0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH2_M  (AXI_DMA_RX_CRC_WIDTH_CH2_V << AXI_DMA_RX_CRC_WIDTH_CH2_S)
+#define AXI_DMA_RX_CRC_WIDTH_CH2_V  0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH2_S  0
+/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2    (BIT(2))
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_M  (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_S)
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_V  0x00000001U
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_S  2
+
+/** AXI_DMA_IN_CRC_CLEAR_CH2_REG register
+ *  This register is used to clear ch2 crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x120)
+/** AXI_DMA_IN_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH2    (BIT(0))
+#define AXI_DMA_IN_CRC_CLEAR_CH2_M  (AXI_DMA_IN_CRC_CLEAR_CH2_V << AXI_DMA_IN_CRC_CLEAR_CH2_S)
+#define AXI_DMA_IN_CRC_CLEAR_CH2_V  0x00000001U
+#define AXI_DMA_IN_CRC_CLEAR_CH2_S  0
+
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH2_REG register
+ *  This register is used to store ch2 crc result
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_REG (DR_REG_AXI_DMA_BASE + 0x124)
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_M  (AXI_DMA_IN_CRC_FINAL_RESULT_CH2_V << AXI_DMA_IN_CRC_FINAL_RESULT_CH2_S)
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_S  0
+
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH2_REG register
+ *  This resister is used to config ch2 crc en for every bit
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x128)
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_M  (AXI_DMA_RX_CRC_EN_WR_DATA_CH2_V << AXI_DMA_RX_CRC_EN_WR_DATA_CH2_S)
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_RX_CRC_EN_ADDR_CH2_REG register
+ *  This register is used to config ch2 crc en addr
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x12c)
+/** AXI_DMA_RX_CRC_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_M  (AXI_DMA_RX_CRC_EN_ADDR_CH2_V << AXI_DMA_RX_CRC_EN_ADDR_CH2_S)
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x130)
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2    0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_M  (AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_V << AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_S)
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_V  0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x134)
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_M  (AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_V << AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_S)
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_INT_RAW_CH0_REG register
+ *  Raw status interrupt of channel0
+ */
+#define AXI_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AXI_DMA_BASE + 0x138)
+/** AXI_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel0.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW_M  (AXI_DMA_OUT_DONE_CH0_INT_RAW_V << AXI_DMA_OUT_DONE_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel0.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW_M  (AXI_DMA_OUT_EOF_CH0_INT_RAW_V << AXI_DMA_OUT_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+ *  including owner error and the second and third word error of outlink descriptor for
+ *  Tx channel0.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_S  10
+
+/** AXI_DMA_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt of channel0
+ */
+#define AXI_DMA_OUT_INT_ST_CH0_REG (DR_REG_AXI_DMA_BASE + 0x13c)
+/** AXI_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_ST_M  (AXI_DMA_OUT_DONE_CH0_INT_ST_V << AXI_DMA_OUT_DONE_CH0_INT_ST_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_ST_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_ST_M  (AXI_DMA_OUT_EOF_CH0_INT_ST_V << AXI_DMA_OUT_EOF_CH0_INT_ST_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_ST_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** AXI_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST    (BIT(4))
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_S  4
+/** AXI_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST    (BIT(5))
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_S  5
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST    (BIT(6))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_S  6
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST    (BIT(7))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_S  10
+
+/** AXI_DMA_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of channel0
+ */
+#define AXI_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x140)
+/** AXI_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA_M  (AXI_DMA_OUT_DONE_CH0_INT_ENA_V << AXI_DMA_OUT_DONE_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA_M  (AXI_DMA_OUT_EOF_CH0_INT_ENA_V << AXI_DMA_OUT_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_S  10
+
+/** AXI_DMA_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of channel0
+ */
+#define AXI_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x144)
+/** AXI_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR_M  (AXI_DMA_OUT_DONE_CH0_INT_CLR_V << AXI_DMA_OUT_DONE_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR_M  (AXI_DMA_OUT_EOF_CH0_INT_CLR_V << AXI_DMA_OUT_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_S  10
+
+/** AXI_DMA_OUT_CONF0_CH0_REG register
+ *  Configure 0 register of Tx channel0
+ */
+#define AXI_DMA_OUT_CONF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x148)
+/** AXI_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer.
+ */
+#define AXI_DMA_OUT_RST_CH0    (BIT(0))
+#define AXI_DMA_OUT_RST_CH0_M  (AXI_DMA_OUT_RST_CH0_V << AXI_DMA_OUT_RST_CH0_S)
+#define AXI_DMA_OUT_RST_CH0_V  0x00000001U
+#define AXI_DMA_OUT_RST_CH0_S  0
+/** AXI_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_LOOP_TEST_CH0    (BIT(1))
+#define AXI_DMA_OUT_LOOP_TEST_CH0_M  (AXI_DMA_OUT_LOOP_TEST_CH0_V << AXI_DMA_OUT_LOOP_TEST_CH0_S)
+#define AXI_DMA_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define AXI_DMA_OUT_LOOP_TEST_CH0_S  1
+/** AXI_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+ *  has been transmitted.
+ */
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0    (BIT(2))
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0_M  (AXI_DMA_OUT_AUTO_WRBACK_CH0_V << AXI_DMA_OUT_AUTO_WRBACK_CH0_S)
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0_S  2
+/** AXI_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1;
+ *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is
+ *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+ */
+#define AXI_DMA_OUT_EOF_MODE_CH0    (BIT(3))
+#define AXI_DMA_OUT_EOF_MODE_CH0_M  (AXI_DMA_OUT_EOF_MODE_CH0_V << AXI_DMA_OUT_EOF_MODE_CH0_S)
+#define AXI_DMA_OUT_EOF_MODE_CH0_V  0x00000001U
+#define AXI_DMA_OUT_EOF_MODE_CH0_S  3
+/** AXI_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_OUT_ETM_EN_CH0    (BIT(4))
+#define AXI_DMA_OUT_ETM_EN_CH0_M  (AXI_DMA_OUT_ETM_EN_CH0_V << AXI_DMA_OUT_ETM_EN_CH0_S)
+#define AXI_DMA_OUT_ETM_EN_CH0_V  0x00000001U
+#define AXI_DMA_OUT_ETM_EN_CH0_S  4
+/** AXI_DMA_OUT_BURST_SIZE_SEL_CH0 : R/W; bitpos: [7:5]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0    0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0_M  (AXI_DMA_OUT_BURST_SIZE_SEL_CH0_V << AXI_DMA_OUT_BURST_SIZE_SEL_CH0_S)
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0_V  0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0_S  5
+/** AXI_DMA_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [8]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_OUT_CMD_DISABLE_CH0    (BIT(8))
+#define AXI_DMA_OUT_CMD_DISABLE_CH0_M  (AXI_DMA_OUT_CMD_DISABLE_CH0_V << AXI_DMA_OUT_CMD_DISABLE_CH0_S)
+#define AXI_DMA_OUT_CMD_DISABLE_CH0_V  0x00000001U
+#define AXI_DMA_OUT_CMD_DISABLE_CH0_S  8
+/** AXI_DMA_OUT_ECC_AEC_EN_CH0 : R/W; bitpos: [9]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0    (BIT(9))
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0_M  (AXI_DMA_OUT_ECC_AEC_EN_CH0_V << AXI_DMA_OUT_ECC_AEC_EN_CH0_S)
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0_V  0x00000001U
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0_S  9
+/** AXI_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0    (BIT(10))
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0_M  (AXI_DMA_OUTDSCR_BURST_EN_CH0_V << AXI_DMA_OUTDSCR_BURST_EN_CH0_S)
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0_S  10
+
+/** AXI_DMA_OUT_CONF1_CH0_REG register
+ *  Configure 1 register of Tx channel0
+ */
+#define AXI_DMA_OUT_CONF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x14c)
+/** AXI_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_OUT_CHECK_OWNER_CH0    (BIT(12))
+#define AXI_DMA_OUT_CHECK_OWNER_CH0_M  (AXI_DMA_OUT_CHECK_OWNER_CH0_V << AXI_DMA_OUT_CHECK_OWNER_CH0_S)
+#define AXI_DMA_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define AXI_DMA_OUT_CHECK_OWNER_CH0_S  12
+
+/** AXI_DMA_OUTFIFO_STATUS_CH0_REG register
+ *  Transmit FIFO status of Tx channel0
+ */
+#define AXI_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AXI_DMA_BASE + 0x150)
+/** AXI_DMA_OUTFIFO_L3_FULL_CH0 : RO; bitpos: [0]; default: 0;
+ *  L3 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0    (BIT(0))
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0_M  (AXI_DMA_OUTFIFO_L3_FULL_CH0_V << AXI_DMA_OUTFIFO_L3_FULL_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0_S  0
+/** AXI_DMA_OUTFIFO_L3_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  L3 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0    (BIT(1))
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0_M  (AXI_DMA_OUTFIFO_L3_EMPTY_CH0_V << AXI_DMA_OUTFIFO_L3_EMPTY_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0_S  1
+/** AXI_DMA_OUTFIFO_L3_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0    0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0_M  (AXI_DMA_OUTFIFO_L3_CNT_CH0_V << AXI_DMA_OUTFIFO_L3_CNT_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0_S  2
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0 : RO; bitpos: [8]; default: 0;
+ *  L3 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_S  8
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0 : RO; bitpos: [9]; default: 0;
+ *  L3 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_S  9
+/** AXI_DMA_OUTFIFO_L1_FULL_CH0 : RO; bitpos: [10]; default: 0;
+ *  L1 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0    (BIT(10))
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0_M  (AXI_DMA_OUTFIFO_L1_FULL_CH0_V << AXI_DMA_OUTFIFO_L1_FULL_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0_S  10
+/** AXI_DMA_OUTFIFO_L1_EMPTY_CH0 : RO; bitpos: [11]; default: 1;
+ *  L1 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0    (BIT(11))
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0_M  (AXI_DMA_OUTFIFO_L1_EMPTY_CH0_V << AXI_DMA_OUTFIFO_L1_EMPTY_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0_S  11
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0 : RO; bitpos: [12]; default: 0;
+ *  L1 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0    (BIT(12))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_S  12
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0 : RO; bitpos: [13]; default: 0;
+ *  L1 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0    (BIT(13))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_S  13
+/** AXI_DMA_OUTFIFO_L2_FULL_CH0 : RO; bitpos: [14]; default: 0;
+ *  L2 Tx RAM full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0    (BIT(14))
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0_M  (AXI_DMA_OUTFIFO_L2_FULL_CH0_V << AXI_DMA_OUTFIFO_L2_FULL_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0_S  14
+/** AXI_DMA_OUTFIFO_L2_EMPTY_CH0 : RO; bitpos: [15]; default: 1;
+ *  L2 Tx RAM empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0    (BIT(15))
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0_M  (AXI_DMA_OUTFIFO_L2_EMPTY_CH0_V << AXI_DMA_OUTFIFO_L2_EMPTY_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0_S  15
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0 : RO; bitpos: [16]; default: 0;
+ *  L2 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0    (BIT(16))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_S  16
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0 : RO; bitpos: [17]; default: 0;
+ *  L2 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0    (BIT(17))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_S  17
+/** AXI_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_S  23
+/** AXI_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_S  24
+/** AXI_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_S  25
+/** AXI_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_S  26
+/** AXI_DMA_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [27]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0    (BIT(27))
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_S  27
+/** AXI_DMA_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0    (BIT(28))
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_S  28
+/** AXI_DMA_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0    (BIT(29))
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_S  29
+/** AXI_DMA_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0    (BIT(30))
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_S  30
+
+/** AXI_DMA_OUT_PUSH_CH0_REG register
+ *  Push control register of Tx channel0
+ */
+#define AXI_DMA_OUT_PUSH_CH0_REG (DR_REG_AXI_DMA_BASE + 0x154)
+/** AXI_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0;
+ *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_WDATA_CH0    0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH0_M  (AXI_DMA_OUTFIFO_WDATA_CH0_V << AXI_DMA_OUTFIFO_WDATA_CH0_S)
+#define AXI_DMA_OUTFIFO_WDATA_CH0_V  0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH0_S  0
+/** AXI_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0;
+ *  Set this bit to push data into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_PUSH_CH0    (BIT(9))
+#define AXI_DMA_OUTFIFO_PUSH_CH0_M  (AXI_DMA_OUTFIFO_PUSH_CH0_V << AXI_DMA_OUTFIFO_PUSH_CH0_S)
+#define AXI_DMA_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_PUSH_CH0_S  9
+
+/** AXI_DMA_OUT_LINK1_CH0_REG register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+#define AXI_DMA_OUT_LINK1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x158)
+/** AXI_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_STOP_CH0    (BIT(0))
+#define AXI_DMA_OUTLINK_STOP_CH0_M  (AXI_DMA_OUTLINK_STOP_CH0_V << AXI_DMA_OUTLINK_STOP_CH0_S)
+#define AXI_DMA_OUTLINK_STOP_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_STOP_CH0_S  0
+/** AXI_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_START_CH0    (BIT(1))
+#define AXI_DMA_OUTLINK_START_CH0_M  (AXI_DMA_OUTLINK_START_CH0_V << AXI_DMA_OUTLINK_START_CH0_S)
+#define AXI_DMA_OUTLINK_START_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_START_CH0_S  1
+/** AXI_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define AXI_DMA_OUTLINK_RESTART_CH0    (BIT(2))
+#define AXI_DMA_OUTLINK_RESTART_CH0_M  (AXI_DMA_OUTLINK_RESTART_CH0_V << AXI_DMA_OUTLINK_RESTART_CH0_S)
+#define AXI_DMA_OUTLINK_RESTART_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_RESTART_CH0_S  2
+/** AXI_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define AXI_DMA_OUTLINK_PARK_CH0    (BIT(3))
+#define AXI_DMA_OUTLINK_PARK_CH0_M  (AXI_DMA_OUTLINK_PARK_CH0_V << AXI_DMA_OUTLINK_PARK_CH0_S)
+#define AXI_DMA_OUTLINK_PARK_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_PARK_CH0_S  3
+
+/** AXI_DMA_OUT_LINK2_CH0_REG register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+#define AXI_DMA_OUT_LINK2_CH0_REG (DR_REG_AXI_DMA_BASE + 0x15c)
+/** AXI_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 32 least significant bits of the first outlink
+ *  descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH0_M  (AXI_DMA_OUTLINK_ADDR_CH0_V << AXI_DMA_OUTLINK_ADDR_CH0_S)
+#define AXI_DMA_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_STATE_CH0_REG register
+ *  Transmit status of Tx channel0
+ */
+#define AXI_DMA_OUT_STATE_CH0_REG (DR_REG_AXI_DMA_BASE + 0x160)
+/** AXI_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0_M  (AXI_DMA_OUTLINK_DSCR_ADDR_CH0_V << AXI_DMA_OUTLINK_DSCR_ADDR_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0_S  0
+/** AXI_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_DSCR_STATE_CH0    0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH0_M  (AXI_DMA_OUT_DSCR_STATE_CH0_V << AXI_DMA_OUT_DSCR_STATE_CH0_S)
+#define AXI_DMA_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH0_S  18
+/** AXI_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_STATE_CH0    0x00000007U
+#define AXI_DMA_OUT_STATE_CH0_M  (AXI_DMA_OUT_STATE_CH0_V << AXI_DMA_OUT_STATE_CH0_S)
+#define AXI_DMA_OUT_STATE_CH0_V  0x00000007U
+#define AXI_DMA_OUT_STATE_CH0_S  20
+
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Outlink descriptor address when EOF occurs of Tx channel0
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x164)
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_M  (AXI_DMA_OUT_EOF_DES_ADDR_CH0_V << AXI_DMA_OUT_EOF_DES_ADDR_CH0_S)
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register
+ *  The last outlink descriptor address when EOF occurs of Tx channel0
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x168)
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor before the last outlink
+ *  descriptor.
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_M  (AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S)
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_DSCR_CH0_REG register
+ *  Current outlink descriptor address of Tx channel0
+ */
+#define AXI_DMA_OUT_DSCR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x16c)
+/** AXI_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current outlink descriptor y.
+ */
+#define AXI_DMA_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH0_M  (AXI_DMA_OUTLINK_DSCR_CH0_V << AXI_DMA_OUTLINK_DSCR_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH0_S  0
+
+/** AXI_DMA_OUT_DSCR_BF0_CH0_REG register
+ *  The last outlink descriptor address of Tx channel0
+ */
+#define AXI_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x170)
+/** AXI_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor y-1.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0_M  (AXI_DMA_OUTLINK_DSCR_BF0_CH0_V << AXI_DMA_OUTLINK_DSCR_BF0_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** AXI_DMA_OUT_DSCR_BF1_CH0_REG register
+ *  The second-to-last outlink descriptor address of Tx channel0
+ */
+#define AXI_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x174)
+/** AXI_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor x-2.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0_M  (AXI_DMA_OUTLINK_DSCR_BF1_CH0_V << AXI_DMA_OUTLINK_DSCR_BF1_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** AXI_DMA_OUT_PRI_CH0_REG register
+ *  Priority register of Tx channel0.
+ */
+#define AXI_DMA_OUT_PRI_CH0_REG (DR_REG_AXI_DMA_BASE + 0x178)
+/** AXI_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Tx channel0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_TX_PRI_CH0    0x0000000FU
+#define AXI_DMA_TX_PRI_CH0_M  (AXI_DMA_TX_PRI_CH0_V << AXI_DMA_TX_PRI_CH0_S)
+#define AXI_DMA_TX_PRI_CH0_V  0x0000000FU
+#define AXI_DMA_TX_PRI_CH0_S  0
+/** AXI_DMA_TX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Tx channel0
+ */
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0    0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0_M  (AXI_DMA_TX_CH_ARB_WEIGH_CH0_V << AXI_DMA_TX_CH_ARB_WEIGH_CH0_S)
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0_V  0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0_S  4
+/** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0    (BIT(8))
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S)
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V  0x00000001U
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S  8
+
+/** AXI_DMA_OUT_PERI_SEL_CH0_REG register
+ *  Peripheral selection of Tx channel0
+ */
+#define AXI_DMA_OUT_PERI_SEL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x17c)
+/** AXI_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_OUT_SEL_CH0    0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH0_M  (AXI_DMA_PERI_OUT_SEL_CH0_V << AXI_DMA_PERI_OUT_SEL_CH0_S)
+#define AXI_DMA_PERI_OUT_SEL_CH0_V  0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH0_S  0
+
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH0_REG register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x180)
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_M  (AXI_DMA_OUT_CRC_INIT_DATA_CH0_V << AXI_DMA_OUT_CRC_INIT_DATA_CH0_S)
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_S  0
+
+/** AXI_DMA_TX_CRC_WIDTH_CH0_REG register
+ *  This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH0_REG (DR_REG_AXI_DMA_BASE + 0x184)
+/** AXI_DMA_TX_CRC_WIDTH_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH0    0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH0_M  (AXI_DMA_TX_CRC_WIDTH_CH0_V << AXI_DMA_TX_CRC_WIDTH_CH0_S)
+#define AXI_DMA_TX_CRC_WIDTH_CH0_V  0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH0_S  0
+/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0    (BIT(2))
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_M  (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_S)
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_V  0x00000001U
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_S  2
+
+/** AXI_DMA_OUT_CRC_CLEAR_CH0_REG register
+ *  This register is used to clear ch0 crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x188)
+/** AXI_DMA_OUT_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH0    (BIT(0))
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_M  (AXI_DMA_OUT_CRC_CLEAR_CH0_V << AXI_DMA_OUT_CRC_CLEAR_CH0_S)
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_V  0x00000001U
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_S  0
+
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_REG register
+ *  This register is used to store ch0 crc result
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_REG (DR_REG_AXI_DMA_BASE + 0x18c)
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_M  (AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_V << AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_S)
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_S  0
+
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH0_REG register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x190)
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_M  (AXI_DMA_TX_CRC_EN_WR_DATA_CH0_V << AXI_DMA_TX_CRC_EN_WR_DATA_CH0_S)
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_TX_CRC_EN_ADDR_CH0_REG register
+ *  This register is used to config ch0 crc en addr
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x194)
+/** AXI_DMA_TX_CRC_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_M  (AXI_DMA_TX_CRC_EN_ADDR_CH0_V << AXI_DMA_TX_CRC_EN_ADDR_CH0_S)
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x198)
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0    0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_M  (AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_V << AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_S)
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_V  0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x19c)
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_M  (AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_V << AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_S)
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_INT_RAW_CH1_REG register
+ *  Raw status interrupt of channel1
+ */
+#define AXI_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1a0)
+/** AXI_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel0.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW_M  (AXI_DMA_OUT_DONE_CH1_INT_RAW_V << AXI_DMA_OUT_DONE_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel0.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW_M  (AXI_DMA_OUT_EOF_CH1_INT_RAW_V << AXI_DMA_OUT_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+ *  including owner error and the second and third word error of outlink descriptor for
+ *  Tx channel0.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_S  10
+
+/** AXI_DMA_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt of channel1
+ */
+#define AXI_DMA_OUT_INT_ST_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1a4)
+/** AXI_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_ST_M  (AXI_DMA_OUT_DONE_CH1_INT_ST_V << AXI_DMA_OUT_DONE_CH1_INT_ST_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_ST_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_ST_M  (AXI_DMA_OUT_EOF_CH1_INT_ST_V << AXI_DMA_OUT_EOF_CH1_INT_ST_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_ST_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** AXI_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST    (BIT(4))
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_S  4
+/** AXI_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST    (BIT(5))
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_S  5
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST    (BIT(6))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_S  6
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST    (BIT(7))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_S  10
+
+/** AXI_DMA_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of channel1
+ */
+#define AXI_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1a8)
+/** AXI_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA_M  (AXI_DMA_OUT_DONE_CH1_INT_ENA_V << AXI_DMA_OUT_DONE_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA_M  (AXI_DMA_OUT_EOF_CH1_INT_ENA_V << AXI_DMA_OUT_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_S  10
+
+/** AXI_DMA_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of channel1
+ */
+#define AXI_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1ac)
+/** AXI_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR_M  (AXI_DMA_OUT_DONE_CH1_INT_CLR_V << AXI_DMA_OUT_DONE_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR_M  (AXI_DMA_OUT_EOF_CH1_INT_CLR_V << AXI_DMA_OUT_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_S  10
+
+/** AXI_DMA_OUT_CONF0_CH1_REG register
+ *  Configure 0 register of Tx channel1
+ */
+#define AXI_DMA_OUT_CONF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1b0)
+/** AXI_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer.
+ */
+#define AXI_DMA_OUT_RST_CH1    (BIT(0))
+#define AXI_DMA_OUT_RST_CH1_M  (AXI_DMA_OUT_RST_CH1_V << AXI_DMA_OUT_RST_CH1_S)
+#define AXI_DMA_OUT_RST_CH1_V  0x00000001U
+#define AXI_DMA_OUT_RST_CH1_S  0
+/** AXI_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_LOOP_TEST_CH1    (BIT(1))
+#define AXI_DMA_OUT_LOOP_TEST_CH1_M  (AXI_DMA_OUT_LOOP_TEST_CH1_V << AXI_DMA_OUT_LOOP_TEST_CH1_S)
+#define AXI_DMA_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define AXI_DMA_OUT_LOOP_TEST_CH1_S  1
+/** AXI_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+ *  has been transmitted.
+ */
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1    (BIT(2))
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1_M  (AXI_DMA_OUT_AUTO_WRBACK_CH1_V << AXI_DMA_OUT_AUTO_WRBACK_CH1_S)
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1_S  2
+/** AXI_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1;
+ *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is
+ *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+ */
+#define AXI_DMA_OUT_EOF_MODE_CH1    (BIT(3))
+#define AXI_DMA_OUT_EOF_MODE_CH1_M  (AXI_DMA_OUT_EOF_MODE_CH1_V << AXI_DMA_OUT_EOF_MODE_CH1_S)
+#define AXI_DMA_OUT_EOF_MODE_CH1_V  0x00000001U
+#define AXI_DMA_OUT_EOF_MODE_CH1_S  3
+/** AXI_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_OUT_ETM_EN_CH1    (BIT(4))
+#define AXI_DMA_OUT_ETM_EN_CH1_M  (AXI_DMA_OUT_ETM_EN_CH1_V << AXI_DMA_OUT_ETM_EN_CH1_S)
+#define AXI_DMA_OUT_ETM_EN_CH1_V  0x00000001U
+#define AXI_DMA_OUT_ETM_EN_CH1_S  4
+/** AXI_DMA_OUT_BURST_SIZE_SEL_CH1 : R/W; bitpos: [7:5]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1    0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1_M  (AXI_DMA_OUT_BURST_SIZE_SEL_CH1_V << AXI_DMA_OUT_BURST_SIZE_SEL_CH1_S)
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1_V  0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1_S  5
+/** AXI_DMA_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [8]; default: 0;
+ *  1:mean disable cmd of this ch1
+ */
+#define AXI_DMA_OUT_CMD_DISABLE_CH1    (BIT(8))
+#define AXI_DMA_OUT_CMD_DISABLE_CH1_M  (AXI_DMA_OUT_CMD_DISABLE_CH1_V << AXI_DMA_OUT_CMD_DISABLE_CH1_S)
+#define AXI_DMA_OUT_CMD_DISABLE_CH1_V  0x00000001U
+#define AXI_DMA_OUT_CMD_DISABLE_CH1_S  8
+/** AXI_DMA_OUT_ECC_AEC_EN_CH1 : R/W; bitpos: [9]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1    (BIT(9))
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1_M  (AXI_DMA_OUT_ECC_AEC_EN_CH1_V << AXI_DMA_OUT_ECC_AEC_EN_CH1_S)
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1_V  0x00000001U
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1_S  9
+/** AXI_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1    (BIT(10))
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1_M  (AXI_DMA_OUTDSCR_BURST_EN_CH1_V << AXI_DMA_OUTDSCR_BURST_EN_CH1_S)
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1_S  10
+
+/** AXI_DMA_OUT_CONF1_CH1_REG register
+ *  Configure 1 register of Tx channel1
+ */
+#define AXI_DMA_OUT_CONF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1b4)
+/** AXI_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_OUT_CHECK_OWNER_CH1    (BIT(12))
+#define AXI_DMA_OUT_CHECK_OWNER_CH1_M  (AXI_DMA_OUT_CHECK_OWNER_CH1_V << AXI_DMA_OUT_CHECK_OWNER_CH1_S)
+#define AXI_DMA_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define AXI_DMA_OUT_CHECK_OWNER_CH1_S  12
+
+/** AXI_DMA_OUTFIFO_STATUS_CH1_REG register
+ *  Transmit FIFO status of Tx channel1
+ */
+#define AXI_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1b8)
+/** AXI_DMA_OUTFIFO_L3_FULL_CH1 : RO; bitpos: [0]; default: 0;
+ *  L3 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1    (BIT(0))
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1_M  (AXI_DMA_OUTFIFO_L3_FULL_CH1_V << AXI_DMA_OUTFIFO_L3_FULL_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1_S  0
+/** AXI_DMA_OUTFIFO_L3_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  L3 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1    (BIT(1))
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1_M  (AXI_DMA_OUTFIFO_L3_EMPTY_CH1_V << AXI_DMA_OUTFIFO_L3_EMPTY_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1_S  1
+/** AXI_DMA_OUTFIFO_L3_CNT_CH1 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1    0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1_M  (AXI_DMA_OUTFIFO_L3_CNT_CH1_V << AXI_DMA_OUTFIFO_L3_CNT_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1_S  2
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1 : RO; bitpos: [8]; default: 0;
+ *  L3 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_S  8
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1 : RO; bitpos: [9]; default: 0;
+ *  L3 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_S  9
+/** AXI_DMA_OUTFIFO_L1_FULL_CH1 : RO; bitpos: [10]; default: 0;
+ *  L1 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1    (BIT(10))
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1_M  (AXI_DMA_OUTFIFO_L1_FULL_CH1_V << AXI_DMA_OUTFIFO_L1_FULL_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1_S  10
+/** AXI_DMA_OUTFIFO_L1_EMPTY_CH1 : RO; bitpos: [11]; default: 1;
+ *  L1 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1    (BIT(11))
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1_M  (AXI_DMA_OUTFIFO_L1_EMPTY_CH1_V << AXI_DMA_OUTFIFO_L1_EMPTY_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1_S  11
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1 : RO; bitpos: [12]; default: 0;
+ *  L1 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1    (BIT(12))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_S  12
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1 : RO; bitpos: [13]; default: 0;
+ *  L1 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1    (BIT(13))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_S  13
+/** AXI_DMA_OUTFIFO_L2_FULL_CH1 : RO; bitpos: [14]; default: 0;
+ *  L2 Tx RAM full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1    (BIT(14))
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1_M  (AXI_DMA_OUTFIFO_L2_FULL_CH1_V << AXI_DMA_OUTFIFO_L2_FULL_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1_S  14
+/** AXI_DMA_OUTFIFO_L2_EMPTY_CH1 : RO; bitpos: [15]; default: 1;
+ *  L2 Tx RAM empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1    (BIT(15))
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1_M  (AXI_DMA_OUTFIFO_L2_EMPTY_CH1_V << AXI_DMA_OUTFIFO_L2_EMPTY_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1_S  15
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1 : RO; bitpos: [16]; default: 0;
+ *  L2 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1    (BIT(16))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_S  16
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1 : RO; bitpos: [17]; default: 0;
+ *  L2 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1    (BIT(17))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_S  17
+/** AXI_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_S  23
+/** AXI_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_S  24
+/** AXI_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_S  25
+/** AXI_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_S  26
+/** AXI_DMA_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [27]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1    (BIT(27))
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_S  27
+/** AXI_DMA_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1    (BIT(28))
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_S  28
+/** AXI_DMA_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1    (BIT(29))
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_S  29
+/** AXI_DMA_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1    (BIT(30))
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_S  30
+
+/** AXI_DMA_OUT_PUSH_CH1_REG register
+ *  Push control register of Tx channel1
+ */
+#define AXI_DMA_OUT_PUSH_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1bc)
+/** AXI_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0;
+ *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_WDATA_CH1    0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH1_M  (AXI_DMA_OUTFIFO_WDATA_CH1_V << AXI_DMA_OUTFIFO_WDATA_CH1_S)
+#define AXI_DMA_OUTFIFO_WDATA_CH1_V  0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH1_S  0
+/** AXI_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0;
+ *  Set this bit to push data into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_PUSH_CH1    (BIT(9))
+#define AXI_DMA_OUTFIFO_PUSH_CH1_M  (AXI_DMA_OUTFIFO_PUSH_CH1_V << AXI_DMA_OUTFIFO_PUSH_CH1_S)
+#define AXI_DMA_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_PUSH_CH1_S  9
+
+/** AXI_DMA_OUT_LINK1_CH1_REG register
+ *  Link descriptor configure and control register of Tx channel1
+ */
+#define AXI_DMA_OUT_LINK1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1c0)
+/** AXI_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_STOP_CH1    (BIT(0))
+#define AXI_DMA_OUTLINK_STOP_CH1_M  (AXI_DMA_OUTLINK_STOP_CH1_V << AXI_DMA_OUTLINK_STOP_CH1_S)
+#define AXI_DMA_OUTLINK_STOP_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_STOP_CH1_S  0
+/** AXI_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_START_CH1    (BIT(1))
+#define AXI_DMA_OUTLINK_START_CH1_M  (AXI_DMA_OUTLINK_START_CH1_V << AXI_DMA_OUTLINK_START_CH1_S)
+#define AXI_DMA_OUTLINK_START_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_START_CH1_S  1
+/** AXI_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define AXI_DMA_OUTLINK_RESTART_CH1    (BIT(2))
+#define AXI_DMA_OUTLINK_RESTART_CH1_M  (AXI_DMA_OUTLINK_RESTART_CH1_V << AXI_DMA_OUTLINK_RESTART_CH1_S)
+#define AXI_DMA_OUTLINK_RESTART_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_RESTART_CH1_S  2
+/** AXI_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define AXI_DMA_OUTLINK_PARK_CH1    (BIT(3))
+#define AXI_DMA_OUTLINK_PARK_CH1_M  (AXI_DMA_OUTLINK_PARK_CH1_V << AXI_DMA_OUTLINK_PARK_CH1_S)
+#define AXI_DMA_OUTLINK_PARK_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_PARK_CH1_S  3
+
+/** AXI_DMA_OUT_LINK2_CH1_REG register
+ *  Link descriptor configure and control register of Tx channel1
+ */
+#define AXI_DMA_OUT_LINK2_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1c4)
+/** AXI_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 32 least significant bits of the first outlink
+ *  descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH1_M  (AXI_DMA_OUTLINK_ADDR_CH1_V << AXI_DMA_OUTLINK_ADDR_CH1_S)
+#define AXI_DMA_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_STATE_CH1_REG register
+ *  Transmit status of Tx channel1
+ */
+#define AXI_DMA_OUT_STATE_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1c8)
+/** AXI_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1_M  (AXI_DMA_OUTLINK_DSCR_ADDR_CH1_V << AXI_DMA_OUTLINK_DSCR_ADDR_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1_S  0
+/** AXI_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_DSCR_STATE_CH1    0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH1_M  (AXI_DMA_OUT_DSCR_STATE_CH1_V << AXI_DMA_OUT_DSCR_STATE_CH1_S)
+#define AXI_DMA_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH1_S  18
+/** AXI_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_STATE_CH1    0x00000007U
+#define AXI_DMA_OUT_STATE_CH1_M  (AXI_DMA_OUT_STATE_CH1_V << AXI_DMA_OUT_STATE_CH1_S)
+#define AXI_DMA_OUT_STATE_CH1_V  0x00000007U
+#define AXI_DMA_OUT_STATE_CH1_S  20
+
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Outlink descriptor address when EOF occurs of Tx channel1
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1cc)
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_M  (AXI_DMA_OUT_EOF_DES_ADDR_CH1_V << AXI_DMA_OUT_EOF_DES_ADDR_CH1_S)
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register
+ *  The last outlink descriptor address when EOF occurs of Tx channel1
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1d0)
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor before the last outlink
+ *  descriptor.
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_M  (AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S)
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_DSCR_CH1_REG register
+ *  Current outlink descriptor address of Tx channel1
+ */
+#define AXI_DMA_OUT_DSCR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1d4)
+/** AXI_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current outlink descriptor y.
+ */
+#define AXI_DMA_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH1_M  (AXI_DMA_OUTLINK_DSCR_CH1_V << AXI_DMA_OUTLINK_DSCR_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH1_S  0
+
+/** AXI_DMA_OUT_DSCR_BF0_CH1_REG register
+ *  The last outlink descriptor address of Tx channel1
+ */
+#define AXI_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1d8)
+/** AXI_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor y-1.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1_M  (AXI_DMA_OUTLINK_DSCR_BF0_CH1_V << AXI_DMA_OUTLINK_DSCR_BF0_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** AXI_DMA_OUT_DSCR_BF1_CH1_REG register
+ *  The second-to-last outlink descriptor address of Tx channel1
+ */
+#define AXI_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1dc)
+/** AXI_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor x-2.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1_M  (AXI_DMA_OUTLINK_DSCR_BF1_CH1_V << AXI_DMA_OUTLINK_DSCR_BF1_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** AXI_DMA_OUT_PRI_CH1_REG register
+ *  Priority register of Tx channel1.
+ */
+#define AXI_DMA_OUT_PRI_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1e0)
+/** AXI_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Tx channel0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_TX_PRI_CH1    0x0000000FU
+#define AXI_DMA_TX_PRI_CH1_M  (AXI_DMA_TX_PRI_CH1_V << AXI_DMA_TX_PRI_CH1_S)
+#define AXI_DMA_TX_PRI_CH1_V  0x0000000FU
+#define AXI_DMA_TX_PRI_CH1_S  0
+/** AXI_DMA_TX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Tx channel0
+ */
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1    0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1_M  (AXI_DMA_TX_CH_ARB_WEIGH_CH1_V << AXI_DMA_TX_CH_ARB_WEIGH_CH1_S)
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1_V  0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1_S  4
+/** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1    (BIT(8))
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S)
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V  0x00000001U
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S  8
+
+/** AXI_DMA_OUT_PERI_SEL_CH1_REG register
+ *  Peripheral selection of Tx channel1
+ */
+#define AXI_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1e4)
+/** AXI_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_OUT_SEL_CH1    0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH1_M  (AXI_DMA_PERI_OUT_SEL_CH1_V << AXI_DMA_PERI_OUT_SEL_CH1_S)
+#define AXI_DMA_PERI_OUT_SEL_CH1_V  0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH1_S  0
+
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH1_REG register
+ *  This register is used to config ch1 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1e8)
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_M  (AXI_DMA_OUT_CRC_INIT_DATA_CH1_V << AXI_DMA_OUT_CRC_INIT_DATA_CH1_S)
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_S  0
+
+/** AXI_DMA_TX_CRC_WIDTH_CH1_REG register
+ *  This register is used to confiig tx ch1 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1ec)
+/** AXI_DMA_TX_CRC_WIDTH_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH1    0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH1_M  (AXI_DMA_TX_CRC_WIDTH_CH1_V << AXI_DMA_TX_CRC_WIDTH_CH1_S)
+#define AXI_DMA_TX_CRC_WIDTH_CH1_V  0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH1_S  0
+/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1    (BIT(2))
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_M  (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_S)
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_V  0x00000001U
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_S  2
+
+/** AXI_DMA_OUT_CRC_CLEAR_CH1_REG register
+ *  This register is used to clear ch1 crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1f0)
+/** AXI_DMA_OUT_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH1    (BIT(0))
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_M  (AXI_DMA_OUT_CRC_CLEAR_CH1_V << AXI_DMA_OUT_CRC_CLEAR_CH1_S)
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_V  0x00000001U
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_S  0
+
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_REG register
+ *  This register is used to store ch1 crc result
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1f4)
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_M  (AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_V << AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_S)
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_S  0
+
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH1_REG register
+ *  This resister is used to config ch1 crc en for every bit
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1f8)
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_M  (AXI_DMA_TX_CRC_EN_WR_DATA_CH1_V << AXI_DMA_TX_CRC_EN_WR_DATA_CH1_S)
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_TX_CRC_EN_ADDR_CH1_REG register
+ *  This register is used to config ch1 crc en addr
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1fc)
+/** AXI_DMA_TX_CRC_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_M  (AXI_DMA_TX_CRC_EN_ADDR_CH1_V << AXI_DMA_TX_CRC_EN_ADDR_CH1_S)
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x200)
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1    0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_M  (AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_V << AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_S)
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_V  0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x204)
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_M  (AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_V << AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_S)
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_INT_RAW_CH2_REG register
+ *  Raw status interrupt of channel2
+ */
+#define AXI_DMA_OUT_INT_RAW_CH2_REG (DR_REG_AXI_DMA_BASE + 0x208)
+/** AXI_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel0.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW_M  (AXI_DMA_OUT_DONE_CH2_INT_RAW_V << AXI_DMA_OUT_DONE_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel0.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW_M  (AXI_DMA_OUT_EOF_CH2_INT_RAW_V << AXI_DMA_OUT_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+ *  including owner error and the second and third word error of outlink descriptor for
+ *  Tx channel0.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_S  10
+
+/** AXI_DMA_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt of channel2
+ */
+#define AXI_DMA_OUT_INT_ST_CH2_REG (DR_REG_AXI_DMA_BASE + 0x20c)
+/** AXI_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_ST_M  (AXI_DMA_OUT_DONE_CH2_INT_ST_V << AXI_DMA_OUT_DONE_CH2_INT_ST_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_ST_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_ST_M  (AXI_DMA_OUT_EOF_CH2_INT_ST_V << AXI_DMA_OUT_EOF_CH2_INT_ST_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_ST_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** AXI_DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST    (BIT(4))
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_S  4
+/** AXI_DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST    (BIT(5))
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_S  5
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST    (BIT(6))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_S  6
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST    (BIT(7))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_S  10
+
+/** AXI_DMA_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of channel2
+ */
+#define AXI_DMA_OUT_INT_ENA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x210)
+/** AXI_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA_M  (AXI_DMA_OUT_DONE_CH2_INT_ENA_V << AXI_DMA_OUT_DONE_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA_M  (AXI_DMA_OUT_EOF_CH2_INT_ENA_V << AXI_DMA_OUT_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_S  10
+
+/** AXI_DMA_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of channel2
+ */
+#define AXI_DMA_OUT_INT_CLR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x214)
+/** AXI_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR_M  (AXI_DMA_OUT_DONE_CH2_INT_CLR_V << AXI_DMA_OUT_DONE_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR_M  (AXI_DMA_OUT_EOF_CH2_INT_CLR_V << AXI_DMA_OUT_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_S  10
+
+/** AXI_DMA_OUT_CONF0_CH2_REG register
+ *  Configure 0 register of Tx channel2
+ */
+#define AXI_DMA_OUT_CONF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0x218)
+/** AXI_DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer.
+ */
+#define AXI_DMA_OUT_RST_CH2    (BIT(0))
+#define AXI_DMA_OUT_RST_CH2_M  (AXI_DMA_OUT_RST_CH2_V << AXI_DMA_OUT_RST_CH2_S)
+#define AXI_DMA_OUT_RST_CH2_V  0x00000001U
+#define AXI_DMA_OUT_RST_CH2_S  0
+/** AXI_DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_LOOP_TEST_CH2    (BIT(1))
+#define AXI_DMA_OUT_LOOP_TEST_CH2_M  (AXI_DMA_OUT_LOOP_TEST_CH2_V << AXI_DMA_OUT_LOOP_TEST_CH2_S)
+#define AXI_DMA_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define AXI_DMA_OUT_LOOP_TEST_CH2_S  1
+/** AXI_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+ *  has been transmitted.
+ */
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2    (BIT(2))
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2_M  (AXI_DMA_OUT_AUTO_WRBACK_CH2_V << AXI_DMA_OUT_AUTO_WRBACK_CH2_S)
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2_S  2
+/** AXI_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1;
+ *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is
+ *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+ */
+#define AXI_DMA_OUT_EOF_MODE_CH2    (BIT(3))
+#define AXI_DMA_OUT_EOF_MODE_CH2_M  (AXI_DMA_OUT_EOF_MODE_CH2_V << AXI_DMA_OUT_EOF_MODE_CH2_S)
+#define AXI_DMA_OUT_EOF_MODE_CH2_V  0x00000001U
+#define AXI_DMA_OUT_EOF_MODE_CH2_S  3
+/** AXI_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_OUT_ETM_EN_CH2    (BIT(4))
+#define AXI_DMA_OUT_ETM_EN_CH2_M  (AXI_DMA_OUT_ETM_EN_CH2_V << AXI_DMA_OUT_ETM_EN_CH2_S)
+#define AXI_DMA_OUT_ETM_EN_CH2_V  0x00000001U
+#define AXI_DMA_OUT_ETM_EN_CH2_S  4
+/** AXI_DMA_OUT_BURST_SIZE_SEL_CH2 : R/W; bitpos: [7:5]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2    0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2_M  (AXI_DMA_OUT_BURST_SIZE_SEL_CH2_V << AXI_DMA_OUT_BURST_SIZE_SEL_CH2_S)
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2_V  0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2_S  5
+/** AXI_DMA_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [8]; default: 0;
+ *  1:mean disable cmd of this ch2
+ */
+#define AXI_DMA_OUT_CMD_DISABLE_CH2    (BIT(8))
+#define AXI_DMA_OUT_CMD_DISABLE_CH2_M  (AXI_DMA_OUT_CMD_DISABLE_CH2_V << AXI_DMA_OUT_CMD_DISABLE_CH2_S)
+#define AXI_DMA_OUT_CMD_DISABLE_CH2_V  0x00000001U
+#define AXI_DMA_OUT_CMD_DISABLE_CH2_S  8
+/** AXI_DMA_OUT_ECC_AEC_EN_CH2 : R/W; bitpos: [9]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2    (BIT(9))
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2_M  (AXI_DMA_OUT_ECC_AEC_EN_CH2_V << AXI_DMA_OUT_ECC_AEC_EN_CH2_S)
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2_V  0x00000001U
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2_S  9
+/** AXI_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2    (BIT(10))
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2_M  (AXI_DMA_OUTDSCR_BURST_EN_CH2_V << AXI_DMA_OUTDSCR_BURST_EN_CH2_S)
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2_S  10
+
+/** AXI_DMA_OUT_CONF1_CH2_REG register
+ *  Configure 1 register of Tx channel2
+ */
+#define AXI_DMA_OUT_CONF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x21c)
+/** AXI_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_OUT_CHECK_OWNER_CH2    (BIT(12))
+#define AXI_DMA_OUT_CHECK_OWNER_CH2_M  (AXI_DMA_OUT_CHECK_OWNER_CH2_V << AXI_DMA_OUT_CHECK_OWNER_CH2_S)
+#define AXI_DMA_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define AXI_DMA_OUT_CHECK_OWNER_CH2_S  12
+
+/** AXI_DMA_OUTFIFO_STATUS_CH2_REG register
+ *  Transmit FIFO status of Tx channel2
+ */
+#define AXI_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_AXI_DMA_BASE + 0x220)
+/** AXI_DMA_OUTFIFO_L3_FULL_CH2 : RO; bitpos: [0]; default: 0;
+ *  L3 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2    (BIT(0))
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2_M  (AXI_DMA_OUTFIFO_L3_FULL_CH2_V << AXI_DMA_OUTFIFO_L3_FULL_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2_S  0
+/** AXI_DMA_OUTFIFO_L3_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  L3 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2    (BIT(1))
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2_M  (AXI_DMA_OUTFIFO_L3_EMPTY_CH2_V << AXI_DMA_OUTFIFO_L3_EMPTY_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2_S  1
+/** AXI_DMA_OUTFIFO_L3_CNT_CH2 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2    0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2_M  (AXI_DMA_OUTFIFO_L3_CNT_CH2_V << AXI_DMA_OUTFIFO_L3_CNT_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2_S  2
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2 : RO; bitpos: [8]; default: 0;
+ *  L3 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_S  8
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2 : RO; bitpos: [9]; default: 0;
+ *  L3 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_S  9
+/** AXI_DMA_OUTFIFO_L1_FULL_CH2 : RO; bitpos: [10]; default: 0;
+ *  L1 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2    (BIT(10))
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2_M  (AXI_DMA_OUTFIFO_L1_FULL_CH2_V << AXI_DMA_OUTFIFO_L1_FULL_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2_S  10
+/** AXI_DMA_OUTFIFO_L1_EMPTY_CH2 : RO; bitpos: [11]; default: 1;
+ *  L1 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2    (BIT(11))
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2_M  (AXI_DMA_OUTFIFO_L1_EMPTY_CH2_V << AXI_DMA_OUTFIFO_L1_EMPTY_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2_S  11
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2 : RO; bitpos: [12]; default: 0;
+ *  L1 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2    (BIT(12))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_S  12
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2 : RO; bitpos: [13]; default: 0;
+ *  L1 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2    (BIT(13))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_S  13
+/** AXI_DMA_OUTFIFO_L2_FULL_CH2 : RO; bitpos: [14]; default: 0;
+ *  L2 Tx RAM full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2    (BIT(14))
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2_M  (AXI_DMA_OUTFIFO_L2_FULL_CH2_V << AXI_DMA_OUTFIFO_L2_FULL_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2_S  14
+/** AXI_DMA_OUTFIFO_L2_EMPTY_CH2 : RO; bitpos: [15]; default: 1;
+ *  L2 Tx RAM empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2    (BIT(15))
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2_M  (AXI_DMA_OUTFIFO_L2_EMPTY_CH2_V << AXI_DMA_OUTFIFO_L2_EMPTY_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2_S  15
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2 : RO; bitpos: [16]; default: 0;
+ *  L2 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2    (BIT(16))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_S  16
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2 : RO; bitpos: [17]; default: 0;
+ *  L2 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2    (BIT(17))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_S  17
+/** AXI_DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_S  23
+/** AXI_DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_S  24
+/** AXI_DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_S  25
+/** AXI_DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_S  26
+/** AXI_DMA_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [27]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2    (BIT(27))
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_S  27
+/** AXI_DMA_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2    (BIT(28))
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_S  28
+/** AXI_DMA_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2    (BIT(29))
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_S  29
+/** AXI_DMA_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2    (BIT(30))
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_S  30
+
+/** AXI_DMA_OUT_PUSH_CH2_REG register
+ *  Push control register of Tx channel2
+ */
+#define AXI_DMA_OUT_PUSH_CH2_REG (DR_REG_AXI_DMA_BASE + 0x224)
+/** AXI_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0;
+ *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_WDATA_CH2    0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH2_M  (AXI_DMA_OUTFIFO_WDATA_CH2_V << AXI_DMA_OUTFIFO_WDATA_CH2_S)
+#define AXI_DMA_OUTFIFO_WDATA_CH2_V  0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH2_S  0
+/** AXI_DMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0;
+ *  Set this bit to push data into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_PUSH_CH2    (BIT(9))
+#define AXI_DMA_OUTFIFO_PUSH_CH2_M  (AXI_DMA_OUTFIFO_PUSH_CH2_V << AXI_DMA_OUTFIFO_PUSH_CH2_S)
+#define AXI_DMA_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_PUSH_CH2_S  9
+
+/** AXI_DMA_OUT_LINK1_CH2_REG register
+ *  Link descriptor configure and control register of Tx channel2
+ */
+#define AXI_DMA_OUT_LINK1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x228)
+/** AXI_DMA_OUTLINK_STOP_CH2 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_STOP_CH2    (BIT(0))
+#define AXI_DMA_OUTLINK_STOP_CH2_M  (AXI_DMA_OUTLINK_STOP_CH2_V << AXI_DMA_OUTLINK_STOP_CH2_S)
+#define AXI_DMA_OUTLINK_STOP_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_STOP_CH2_S  0
+/** AXI_DMA_OUTLINK_START_CH2 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_START_CH2    (BIT(1))
+#define AXI_DMA_OUTLINK_START_CH2_M  (AXI_DMA_OUTLINK_START_CH2_V << AXI_DMA_OUTLINK_START_CH2_S)
+#define AXI_DMA_OUTLINK_START_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_START_CH2_S  1
+/** AXI_DMA_OUTLINK_RESTART_CH2 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define AXI_DMA_OUTLINK_RESTART_CH2    (BIT(2))
+#define AXI_DMA_OUTLINK_RESTART_CH2_M  (AXI_DMA_OUTLINK_RESTART_CH2_V << AXI_DMA_OUTLINK_RESTART_CH2_S)
+#define AXI_DMA_OUTLINK_RESTART_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_RESTART_CH2_S  2
+/** AXI_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [3]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define AXI_DMA_OUTLINK_PARK_CH2    (BIT(3))
+#define AXI_DMA_OUTLINK_PARK_CH2_M  (AXI_DMA_OUTLINK_PARK_CH2_V << AXI_DMA_OUTLINK_PARK_CH2_S)
+#define AXI_DMA_OUTLINK_PARK_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_PARK_CH2_S  3
+
+/** AXI_DMA_OUT_LINK2_CH2_REG register
+ *  Link descriptor configure and control register of Tx channel2
+ */
+#define AXI_DMA_OUT_LINK2_CH2_REG (DR_REG_AXI_DMA_BASE + 0x22c)
+/** AXI_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 32 least significant bits of the first outlink
+ *  descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH2_M  (AXI_DMA_OUTLINK_ADDR_CH2_V << AXI_DMA_OUTLINK_ADDR_CH2_S)
+#define AXI_DMA_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_STATE_CH2_REG register
+ *  Transmit status of Tx channel2
+ */
+#define AXI_DMA_OUT_STATE_CH2_REG (DR_REG_AXI_DMA_BASE + 0x230)
+/** AXI_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2_M  (AXI_DMA_OUTLINK_DSCR_ADDR_CH2_V << AXI_DMA_OUTLINK_DSCR_ADDR_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2_S  0
+/** AXI_DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_DSCR_STATE_CH2    0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH2_M  (AXI_DMA_OUT_DSCR_STATE_CH2_V << AXI_DMA_OUT_DSCR_STATE_CH2_S)
+#define AXI_DMA_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH2_S  18
+/** AXI_DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_STATE_CH2    0x00000007U
+#define AXI_DMA_OUT_STATE_CH2_M  (AXI_DMA_OUT_STATE_CH2_V << AXI_DMA_OUT_STATE_CH2_S)
+#define AXI_DMA_OUT_STATE_CH2_V  0x00000007U
+#define AXI_DMA_OUT_STATE_CH2_S  20
+
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Outlink descriptor address when EOF occurs of Tx channel2
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x234)
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_M  (AXI_DMA_OUT_EOF_DES_ADDR_CH2_V << AXI_DMA_OUT_EOF_DES_ADDR_CH2_S)
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register
+ *  The last outlink descriptor address when EOF occurs of Tx channel2
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x238)
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor before the last outlink
+ *  descriptor.
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_M  (AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S)
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_DSCR_CH2_REG register
+ *  Current outlink descriptor address of Tx channel2
+ */
+#define AXI_DMA_OUT_DSCR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x23c)
+/** AXI_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current outlink descriptor y.
+ */
+#define AXI_DMA_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH2_M  (AXI_DMA_OUTLINK_DSCR_CH2_V << AXI_DMA_OUTLINK_DSCR_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH2_S  0
+
+/** AXI_DMA_OUT_DSCR_BF0_CH2_REG register
+ *  The last outlink descriptor address of Tx channel2
+ */
+#define AXI_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0x240)
+/** AXI_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor y-1.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2_M  (AXI_DMA_OUTLINK_DSCR_BF0_CH2_V << AXI_DMA_OUTLINK_DSCR_BF0_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** AXI_DMA_OUT_DSCR_BF1_CH2_REG register
+ *  The second-to-last outlink descriptor address of Tx channel2
+ */
+#define AXI_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x244)
+/** AXI_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor x-2.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2_M  (AXI_DMA_OUTLINK_DSCR_BF1_CH2_V << AXI_DMA_OUTLINK_DSCR_BF1_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** AXI_DMA_OUT_PRI_CH2_REG register
+ *  Priority register of Tx channel2.
+ */
+#define AXI_DMA_OUT_PRI_CH2_REG (DR_REG_AXI_DMA_BASE + 0x248)
+/** AXI_DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Tx channel0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_TX_PRI_CH2    0x0000000FU
+#define AXI_DMA_TX_PRI_CH2_M  (AXI_DMA_TX_PRI_CH2_V << AXI_DMA_TX_PRI_CH2_S)
+#define AXI_DMA_TX_PRI_CH2_V  0x0000000FU
+#define AXI_DMA_TX_PRI_CH2_S  0
+/** AXI_DMA_TX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Tx channel0
+ */
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2    0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2_M  (AXI_DMA_TX_CH_ARB_WEIGH_CH2_V << AXI_DMA_TX_CH_ARB_WEIGH_CH2_S)
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2_V  0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2_S  4
+/** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2    (BIT(8))
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S)
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V  0x00000001U
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S  8
+
+/** AXI_DMA_OUT_PERI_SEL_CH2_REG register
+ *  Peripheral selection of Tx channel2
+ */
+#define AXI_DMA_OUT_PERI_SEL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x24c)
+/** AXI_DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_OUT_SEL_CH2    0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH2_M  (AXI_DMA_PERI_OUT_SEL_CH2_V << AXI_DMA_PERI_OUT_SEL_CH2_S)
+#define AXI_DMA_PERI_OUT_SEL_CH2_V  0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH2_S  0
+
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH2_REG register
+ *  This register is used to config ch2 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x250)
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_M  (AXI_DMA_OUT_CRC_INIT_DATA_CH2_V << AXI_DMA_OUT_CRC_INIT_DATA_CH2_S)
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_S  0
+
+/** AXI_DMA_TX_CRC_WIDTH_CH2_REG register
+ *  This register is used to confiig tx ch2 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH2_REG (DR_REG_AXI_DMA_BASE + 0x254)
+/** AXI_DMA_TX_CRC_WIDTH_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH2    0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH2_M  (AXI_DMA_TX_CRC_WIDTH_CH2_V << AXI_DMA_TX_CRC_WIDTH_CH2_S)
+#define AXI_DMA_TX_CRC_WIDTH_CH2_V  0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH2_S  0
+/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2    (BIT(2))
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_M  (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_S)
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_V  0x00000001U
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_S  2
+
+/** AXI_DMA_OUT_CRC_CLEAR_CH2_REG register
+ *  This register is used to clear ch2 crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x258)
+/** AXI_DMA_OUT_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH2    (BIT(0))
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_M  (AXI_DMA_OUT_CRC_CLEAR_CH2_V << AXI_DMA_OUT_CRC_CLEAR_CH2_S)
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_V  0x00000001U
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_S  0
+
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_REG register
+ *  This register is used to store ch2 crc result
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_REG (DR_REG_AXI_DMA_BASE + 0x25c)
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_M  (AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_V << AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_S)
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_S  0
+
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH2_REG register
+ *  This resister is used to config ch2 crc en for every bit
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x260)
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_M  (AXI_DMA_TX_CRC_EN_WR_DATA_CH2_V << AXI_DMA_TX_CRC_EN_WR_DATA_CH2_S)
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_TX_CRC_EN_ADDR_CH2_REG register
+ *  This register is used to config ch2 crc en addr
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x264)
+/** AXI_DMA_TX_CRC_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_M  (AXI_DMA_TX_CRC_EN_ADDR_CH2_V << AXI_DMA_TX_CRC_EN_ADDR_CH2_S)
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x268)
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2    0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_M  (AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_V << AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_S)
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_V  0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x26c)
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_M  (AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_V << AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_S)
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_ARB_TIMEOUT_REG register
+ *  This retister is used to config arbiter time slice
+ */
+#define AXI_DMA_ARB_TIMEOUT_REG (DR_REG_AXI_DMA_BASE + 0x270)
+/** AXI_DMA_ARB_TIMEOUT_TX : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to config tx arbiter time out value
+ */
+#define AXI_DMA_ARB_TIMEOUT_TX    0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_TX_M  (AXI_DMA_ARB_TIMEOUT_TX_V << AXI_DMA_ARB_TIMEOUT_TX_S)
+#define AXI_DMA_ARB_TIMEOUT_TX_V  0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_TX_S  0
+/** AXI_DMA_ARB_TIMEOUT_RX : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to config rx arbiter time out value
+ */
+#define AXI_DMA_ARB_TIMEOUT_RX    0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_RX_M  (AXI_DMA_ARB_TIMEOUT_RX_V << AXI_DMA_ARB_TIMEOUT_RX_S)
+#define AXI_DMA_ARB_TIMEOUT_RX_V  0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_RX_S  16
+
+/** AXI_DMA_WEIGHT_EN_REG register
+ *  This register is used to config arbiter weight function to on or off
+ */
+#define AXI_DMA_WEIGHT_EN_REG (DR_REG_AXI_DMA_BASE + 0x274)
+/** AXI_DMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0;
+ *  This register is used to config tx arbiter weight function  off/on
+ */
+#define AXI_DMA_WEIGHT_EN_TX    (BIT(0))
+#define AXI_DMA_WEIGHT_EN_TX_M  (AXI_DMA_WEIGHT_EN_TX_V << AXI_DMA_WEIGHT_EN_TX_S)
+#define AXI_DMA_WEIGHT_EN_TX_V  0x00000001U
+#define AXI_DMA_WEIGHT_EN_TX_S  0
+/** AXI_DMA_WEIGHT_EN_RX : R/W; bitpos: [1]; default: 0;
+ *  This register is used to config rx arbiter weight function  off/on
+ */
+#define AXI_DMA_WEIGHT_EN_RX    (BIT(1))
+#define AXI_DMA_WEIGHT_EN_RX_M  (AXI_DMA_WEIGHT_EN_RX_V << AXI_DMA_WEIGHT_EN_RX_S)
+#define AXI_DMA_WEIGHT_EN_RX_V  0x00000001U
+#define AXI_DMA_WEIGHT_EN_RX_S  1
+
+/** AXI_DMA_IN_MEM_CONF_REG register
+ *  Mem power configure register of Rx channel
+ */
+#define AXI_DMA_IN_MEM_CONF_REG (DR_REG_AXI_DMA_BASE + 0x278)
+/** AXI_DMA_IN_MEM_CLK_FORCE_EN : R/W; bitpos: [0]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+ *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+ */
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN    (BIT(0))
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN_M  (AXI_DMA_IN_MEM_CLK_FORCE_EN_V << AXI_DMA_IN_MEM_CLK_FORCE_EN_S)
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN_V  0x00000001U
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN_S  0
+/** AXI_DMA_IN_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0;
+ *  Force power up ram
+ */
+#define AXI_DMA_IN_MEM_FORCE_PU    (BIT(1))
+#define AXI_DMA_IN_MEM_FORCE_PU_M  (AXI_DMA_IN_MEM_FORCE_PU_V << AXI_DMA_IN_MEM_FORCE_PU_S)
+#define AXI_DMA_IN_MEM_FORCE_PU_V  0x00000001U
+#define AXI_DMA_IN_MEM_FORCE_PU_S  1
+/** AXI_DMA_IN_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Force power down ram
+ */
+#define AXI_DMA_IN_MEM_FORCE_PD    (BIT(2))
+#define AXI_DMA_IN_MEM_FORCE_PD_M  (AXI_DMA_IN_MEM_FORCE_PD_V << AXI_DMA_IN_MEM_FORCE_PD_S)
+#define AXI_DMA_IN_MEM_FORCE_PD_V  0x00000001U
+#define AXI_DMA_IN_MEM_FORCE_PD_S  2
+/** AXI_DMA_OUT_MEM_CLK_FORCE_EN : R/W; bitpos: [3]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+ *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+ */
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN    (BIT(3))
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN_M  (AXI_DMA_OUT_MEM_CLK_FORCE_EN_V << AXI_DMA_OUT_MEM_CLK_FORCE_EN_S)
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN_V  0x00000001U
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN_S  3
+/** AXI_DMA_OUT_MEM_FORCE_PU : R/W; bitpos: [4]; default: 0;
+ *  Force power up ram
+ */
+#define AXI_DMA_OUT_MEM_FORCE_PU    (BIT(4))
+#define AXI_DMA_OUT_MEM_FORCE_PU_M  (AXI_DMA_OUT_MEM_FORCE_PU_V << AXI_DMA_OUT_MEM_FORCE_PU_S)
+#define AXI_DMA_OUT_MEM_FORCE_PU_V  0x00000001U
+#define AXI_DMA_OUT_MEM_FORCE_PU_S  4
+/** AXI_DMA_OUT_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  Force power down ram
+ */
+#define AXI_DMA_OUT_MEM_FORCE_PD    (BIT(5))
+#define AXI_DMA_OUT_MEM_FORCE_PD_M  (AXI_DMA_OUT_MEM_FORCE_PD_V << AXI_DMA_OUT_MEM_FORCE_PD_S)
+#define AXI_DMA_OUT_MEM_FORCE_PD_V  0x00000001U
+#define AXI_DMA_OUT_MEM_FORCE_PD_S  5
+
+/** AXI_DMA_INTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x27c)
+/** AXI_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR_M  (AXI_DMA_ACCESS_INTR_MEM_START_ADDR_V << AXI_DMA_ACCESS_INTR_MEM_START_ADDR_S)
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** AXI_DMA_INTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_INTR_MEM_END_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x280)
+/** AXI_DMA_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR_M  (AXI_DMA_ACCESS_INTR_MEM_END_ADDR_V << AXI_DMA_ACCESS_INTR_MEM_END_ADDR_S)
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** AXI_DMA_EXTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_EXTR_MEM_START_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x284)
+/** AXI_DMA_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_M  (AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_V << AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_S)
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_S  0
+
+/** AXI_DMA_EXTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_EXTR_MEM_END_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x288)
+/** AXI_DMA_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_M  (AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_V << AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_S)
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_S  0
+
+/** AXI_DMA_IN_RESET_AVAIL_CH0_REG register
+ *  The rx channel 0 reset valid_flag register.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x28c)
+/** AXI_DMA_IN_RESET_AVAIL_CH0 : RO; bitpos: [0]; default: 1;
+ *  rx chan0 reset valid reg.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH0    (BIT(0))
+#define AXI_DMA_IN_RESET_AVAIL_CH0_M  (AXI_DMA_IN_RESET_AVAIL_CH0_V << AXI_DMA_IN_RESET_AVAIL_CH0_S)
+#define AXI_DMA_IN_RESET_AVAIL_CH0_V  0x00000001U
+#define AXI_DMA_IN_RESET_AVAIL_CH0_S  0
+
+/** AXI_DMA_IN_RESET_AVAIL_CH1_REG register
+ *  The rx channel 1 reset valid_flag register.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH1_REG (DR_REG_AXI_DMA_BASE + 0x290)
+/** AXI_DMA_IN_RESET_AVAIL_CH1 : RO; bitpos: [0]; default: 1;
+ *  rx chan0 reset valid reg.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH1    (BIT(0))
+#define AXI_DMA_IN_RESET_AVAIL_CH1_M  (AXI_DMA_IN_RESET_AVAIL_CH1_V << AXI_DMA_IN_RESET_AVAIL_CH1_S)
+#define AXI_DMA_IN_RESET_AVAIL_CH1_V  0x00000001U
+#define AXI_DMA_IN_RESET_AVAIL_CH1_S  0
+
+/** AXI_DMA_IN_RESET_AVAIL_CH2_REG register
+ *  The rx channel 2 reset valid_flag register.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x294)
+/** AXI_DMA_IN_RESET_AVAIL_CH2 : RO; bitpos: [0]; default: 1;
+ *  rx chan0 reset valid reg.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH2    (BIT(0))
+#define AXI_DMA_IN_RESET_AVAIL_CH2_M  (AXI_DMA_IN_RESET_AVAIL_CH2_V << AXI_DMA_IN_RESET_AVAIL_CH2_S)
+#define AXI_DMA_IN_RESET_AVAIL_CH2_V  0x00000001U
+#define AXI_DMA_IN_RESET_AVAIL_CH2_S  0
+
+/** AXI_DMA_OUT_RESET_AVAIL_CH0_REG register
+ *  The tx channel 0 reset valid_flag register.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x298)
+/** AXI_DMA_OUT_RESET_AVAIL_CH0 : RO; bitpos: [0]; default: 1;
+ *  tx chan0 reset valid reg.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH0    (BIT(0))
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_M  (AXI_DMA_OUT_RESET_AVAIL_CH0_V << AXI_DMA_OUT_RESET_AVAIL_CH0_S)
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_V  0x00000001U
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_S  0
+
+/** AXI_DMA_OUT_RESET_AVAIL_CH1_REG register
+ *  The tx channel 1 reset valid_flag register.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_REG (DR_REG_AXI_DMA_BASE + 0x29c)
+/** AXI_DMA_OUT_RESET_AVAIL_CH1 : RO; bitpos: [0]; default: 1;
+ *  tx chan0 reset valid reg.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH1    (BIT(0))
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_M  (AXI_DMA_OUT_RESET_AVAIL_CH1_V << AXI_DMA_OUT_RESET_AVAIL_CH1_S)
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_V  0x00000001U
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_S  0
+
+/** AXI_DMA_OUT_RESET_AVAIL_CH2_REG register
+ *  The tx channel 2 reset valid_flag register.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x2a0)
+/** AXI_DMA_OUT_RESET_AVAIL_CH2 : RO; bitpos: [0]; default: 1;
+ *  tx chan0 reset valid reg.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH2    (BIT(0))
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_M  (AXI_DMA_OUT_RESET_AVAIL_CH2_V << AXI_DMA_OUT_RESET_AVAIL_CH2_S)
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_V  0x00000001U
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_S  0
+
+/** AXI_DMA_MISC_CONF_REG register
+ *  MISC register
+ */
+#define AXI_DMA_MISC_CONF_REG (DR_REG_AXI_DMA_BASE + 0x2a8)
+/** AXI_DMA_AXIM_RST_WR_INTER : R/W; bitpos: [0]; default: 0;
+ *  Set this bit then clear this bit to reset the internal axi_wr FSM.
+ */
+#define AXI_DMA_AXIM_RST_WR_INTER    (BIT(0))
+#define AXI_DMA_AXIM_RST_WR_INTER_M  (AXI_DMA_AXIM_RST_WR_INTER_V << AXI_DMA_AXIM_RST_WR_INTER_S)
+#define AXI_DMA_AXIM_RST_WR_INTER_V  0x00000001U
+#define AXI_DMA_AXIM_RST_WR_INTER_S  0
+/** AXI_DMA_AXIM_RST_RD_INTER : R/W; bitpos: [1]; default: 0;
+ *  Set this bit then clear this bit to reset the internal axi_rd FSM.
+ */
+#define AXI_DMA_AXIM_RST_RD_INTER    (BIT(1))
+#define AXI_DMA_AXIM_RST_RD_INTER_M  (AXI_DMA_AXIM_RST_RD_INTER_V << AXI_DMA_AXIM_RST_RD_INTER_S)
+#define AXI_DMA_AXIM_RST_RD_INTER_V  0x00000001U
+#define AXI_DMA_AXIM_RST_RD_INTER_S  1
+/** AXI_DMA_ARB_PRI_DIS : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to disable priority arbitration function.
+ */
+#define AXI_DMA_ARB_PRI_DIS    (BIT(3))
+#define AXI_DMA_ARB_PRI_DIS_M  (AXI_DMA_ARB_PRI_DIS_V << AXI_DMA_ARB_PRI_DIS_S)
+#define AXI_DMA_ARB_PRI_DIS_V  0x00000001U
+#define AXI_DMA_ARB_PRI_DIS_S  3
+/** AXI_DMA_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define AXI_DMA_CLK_EN    (BIT(4))
+#define AXI_DMA_CLK_EN_M  (AXI_DMA_CLK_EN_V << AXI_DMA_CLK_EN_S)
+#define AXI_DMA_CLK_EN_V  0x00000001U
+#define AXI_DMA_CLK_EN_S  4
+
+/** AXI_DMA_RDN_RESULT_REG register
+ *  reserved
+ */
+#define AXI_DMA_RDN_RESULT_REG (DR_REG_AXI_DMA_BASE + 0x2ac)
+/** AXI_DMA_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RDN_ENA    (BIT(0))
+#define AXI_DMA_RDN_ENA_M  (AXI_DMA_RDN_ENA_V << AXI_DMA_RDN_ENA_S)
+#define AXI_DMA_RDN_ENA_V  0x00000001U
+#define AXI_DMA_RDN_ENA_S  0
+/** AXI_DMA_RDN_RESULT : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RDN_RESULT    (BIT(1))
+#define AXI_DMA_RDN_RESULT_M  (AXI_DMA_RDN_RESULT_V << AXI_DMA_RDN_RESULT_S)
+#define AXI_DMA_RDN_RESULT_V  0x00000001U
+#define AXI_DMA_RDN_RESULT_S  1
+
+/** AXI_DMA_RDN_ECO_HIGH_REG register
+ *  reserved
+ */
+#define AXI_DMA_RDN_ECO_HIGH_REG (DR_REG_AXI_DMA_BASE + 0x2b0)
+/** AXI_DMA_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_RDN_ECO_HIGH    0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_HIGH_M  (AXI_DMA_RDN_ECO_HIGH_V << AXI_DMA_RDN_ECO_HIGH_S)
+#define AXI_DMA_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_HIGH_S  0
+
+/** AXI_DMA_RDN_ECO_LOW_REG register
+ *  reserved
+ */
+#define AXI_DMA_RDN_ECO_LOW_REG (DR_REG_AXI_DMA_BASE + 0x2b4)
+/** AXI_DMA_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_RDN_ECO_LOW    0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_LOW_M  (AXI_DMA_RDN_ECO_LOW_V << AXI_DMA_RDN_ECO_LOW_S)
+#define AXI_DMA_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_LOW_S  0
+
+/** AXI_DMA_WRESP_CNT_REG register
+ *  AXI wr response cnt register.
+ */
+#define AXI_DMA_WRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2b8)
+/** AXI_DMA_WRESP_CNT : RO; bitpos: [3:0]; default: 0;
+ *  axi wr response cnt reg.
+ */
+#define AXI_DMA_WRESP_CNT    0x0000000FU
+#define AXI_DMA_WRESP_CNT_M  (AXI_DMA_WRESP_CNT_V << AXI_DMA_WRESP_CNT_S)
+#define AXI_DMA_WRESP_CNT_V  0x0000000FU
+#define AXI_DMA_WRESP_CNT_S  0
+
+/** AXI_DMA_RRESP_CNT_REG register
+ *  AXI wr response cnt register.
+ */
+#define AXI_DMA_RRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2bc)
+/** AXI_DMA_RRESP_CNT : RO; bitpos: [3:0]; default: 0;
+ *  axi rd response cnt reg.
+ */
+#define AXI_DMA_RRESP_CNT    0x0000000FU
+#define AXI_DMA_RRESP_CNT_M  (AXI_DMA_RRESP_CNT_V << AXI_DMA_RRESP_CNT_S)
+#define AXI_DMA_RRESP_CNT_V  0x0000000FU
+#define AXI_DMA_RRESP_CNT_S  0
+
+/** AXI_DMA_INFIFO_STATUS1_CH0_REG register
+ *  Receive FIFO status of Rx channel 0
+ */
+#define AXI_DMA_INFIFO_STATUS1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x2c0)
+/** AXI_DMA_L1INFIFO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L1INFIFO_CNT_CH0    0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH0_M  (AXI_DMA_L1INFIFO_CNT_CH0_V << AXI_DMA_L1INFIFO_CNT_CH0_S)
+#define AXI_DMA_L1INFIFO_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH0_S  0
+/** AXI_DMA_L2INFIFO_CNT_CH0 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L2INFIFO_CNT_CH0    0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH0_M  (AXI_DMA_L2INFIFO_CNT_CH0_V << AXI_DMA_L2INFIFO_CNT_CH0_S)
+#define AXI_DMA_L2INFIFO_CNT_CH0_V  0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH0_S  6
+
+/** AXI_DMA_INFIFO_STATUS1_CH1_REG register
+ *  Receive FIFO status of Rx channel 1
+ */
+#define AXI_DMA_INFIFO_STATUS1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x2c4)
+/** AXI_DMA_L1INFIFO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L1INFIFO_CNT_CH1    0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH1_M  (AXI_DMA_L1INFIFO_CNT_CH1_V << AXI_DMA_L1INFIFO_CNT_CH1_S)
+#define AXI_DMA_L1INFIFO_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH1_S  0
+/** AXI_DMA_L2INFIFO_CNT_CH1 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L2INFIFO_CNT_CH1    0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH1_M  (AXI_DMA_L2INFIFO_CNT_CH1_V << AXI_DMA_L2INFIFO_CNT_CH1_S)
+#define AXI_DMA_L2INFIFO_CNT_CH1_V  0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH1_S  6
+
+/** AXI_DMA_INFIFO_STATUS1_CH2_REG register
+ *  Receive FIFO status of Rx channel 2
+ */
+#define AXI_DMA_INFIFO_STATUS1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x2c8)
+/** AXI_DMA_L1INFIFO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L1INFIFO_CNT_CH2    0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH2_M  (AXI_DMA_L1INFIFO_CNT_CH2_V << AXI_DMA_L1INFIFO_CNT_CH2_S)
+#define AXI_DMA_L1INFIFO_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH2_S  0
+/** AXI_DMA_L2INFIFO_CNT_CH2 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L2INFIFO_CNT_CH2    0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH2_M  (AXI_DMA_L2INFIFO_CNT_CH2_V << AXI_DMA_L2INFIFO_CNT_CH2_S)
+#define AXI_DMA_L2INFIFO_CNT_CH2_V  0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH2_S  6
+
+/** AXI_DMA_OUTFIFO_STATUS1_CH0_REG register
+ *  Receive FIFO status of Tx channel 0
+ */
+#define AXI_DMA_OUTFIFO_STATUS1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x2cc)
+/** AXI_DMA_L1OUTFIFO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L1OUTFIFO_CNT_CH0    0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH0_M  (AXI_DMA_L1OUTFIFO_CNT_CH0_V << AXI_DMA_L1OUTFIFO_CNT_CH0_S)
+#define AXI_DMA_L1OUTFIFO_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH0_S  0
+/** AXI_DMA_L2OUTFIFO_CNT_CH0 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L2OUTFIFO_CNT_CH0    0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH0_M  (AXI_DMA_L2OUTFIFO_CNT_CH0_V << AXI_DMA_L2OUTFIFO_CNT_CH0_S)
+#define AXI_DMA_L2OUTFIFO_CNT_CH0_V  0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH0_S  6
+
+/** AXI_DMA_OUTFIFO_STATUS1_CH1_REG register
+ *  Receive FIFO status of Tx channel 1
+ */
+#define AXI_DMA_OUTFIFO_STATUS1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x2d0)
+/** AXI_DMA_L1OUTFIFO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L1OUTFIFO_CNT_CH1    0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH1_M  (AXI_DMA_L1OUTFIFO_CNT_CH1_V << AXI_DMA_L1OUTFIFO_CNT_CH1_S)
+#define AXI_DMA_L1OUTFIFO_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH1_S  0
+/** AXI_DMA_L2OUTFIFO_CNT_CH1 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L2OUTFIFO_CNT_CH1    0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH1_M  (AXI_DMA_L2OUTFIFO_CNT_CH1_V << AXI_DMA_L2OUTFIFO_CNT_CH1_S)
+#define AXI_DMA_L2OUTFIFO_CNT_CH1_V  0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH1_S  6
+
+/** AXI_DMA_OUTFIFO_STATUS1_CH2_REG register
+ *  Receive FIFO status of Tx channel 2
+ */
+#define AXI_DMA_OUTFIFO_STATUS1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x2d4)
+/** AXI_DMA_L1OUTFIFO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L1OUTFIFO_CNT_CH2    0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH2_M  (AXI_DMA_L1OUTFIFO_CNT_CH2_V << AXI_DMA_L1OUTFIFO_CNT_CH2_S)
+#define AXI_DMA_L1OUTFIFO_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH2_S  0
+/** AXI_DMA_L2OUTFIFO_CNT_CH2 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L2OUTFIFO_CNT_CH2    0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH2_M  (AXI_DMA_L2OUTFIFO_CNT_CH2_V << AXI_DMA_L2OUTFIFO_CNT_CH2_S)
+#define AXI_DMA_L2OUTFIFO_CNT_CH2_V  0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH2_S  6
+
+/** AXI_DMA_DATE_REG register
+ *  Version control register
+ */
+#define AXI_DMA_DATE_REG (DR_REG_AXI_DMA_BASE + 0x2d8)
+/** AXI_DMA_DATE : R/W; bitpos: [31:0]; default: 36712768;
+ *  register version.
+ */
+#define AXI_DMA_DATE    0xFFFFFFFFU
+#define AXI_DMA_DATE_M  (AXI_DMA_DATE_V << AXI_DMA_DATE_S)
+#define AXI_DMA_DATE_V  0xFFFFFFFFU
+#define AXI_DMA_DATE_S  0
+
+/** AXI_DMA_LINK_SWITCH_STATE_REG register
+ *  Version control register
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_REG (DR_REG_AXI_DMA_BASE + 0x2dc)
+/** AXI_DMA_LINK_SWITCH_STATE_CH0 : R/W; bitpos: [0]; default: 0;
+ *  The register that confirm ch dscr switch success
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_CH0    (BIT(0))
+#define AXI_DMA_LINK_SWITCH_STATE_CH0_M  (AXI_DMA_LINK_SWITCH_STATE_CH0_V << AXI_DMA_LINK_SWITCH_STATE_CH0_S)
+#define AXI_DMA_LINK_SWITCH_STATE_CH0_V  0x00000001U
+#define AXI_DMA_LINK_SWITCH_STATE_CH0_S  0
+/** AXI_DMA_LINK_SWITCH_STATE_CH1 : R/W; bitpos: [1]; default: 0;
+ *  The register that confirm ch dscr switch success
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_CH1    (BIT(1))
+#define AXI_DMA_LINK_SWITCH_STATE_CH1_M  (AXI_DMA_LINK_SWITCH_STATE_CH1_V << AXI_DMA_LINK_SWITCH_STATE_CH1_S)
+#define AXI_DMA_LINK_SWITCH_STATE_CH1_V  0x00000001U
+#define AXI_DMA_LINK_SWITCH_STATE_CH1_S  1
+/** AXI_DMA_LINK_SWITCH_STATE_CH2 : R/W; bitpos: [2]; default: 0;
+ *  The register that confirm ch dscr switch success
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_CH2    (BIT(2))
+#define AXI_DMA_LINK_SWITCH_STATE_CH2_M  (AXI_DMA_LINK_SWITCH_STATE_CH2_V << AXI_DMA_LINK_SWITCH_STATE_CH2_S)
+#define AXI_DMA_LINK_SWITCH_STATE_CH2_V  0x00000001U
+#define AXI_DMA_LINK_SWITCH_STATE_CH2_S  2
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/axi_dma_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/axi_dma_struct.h
new file mode 100644
index 0000000000..fed3f3ed39
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/axi_dma_struct.h
@@ -0,0 +1,1799 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: in */
+/** Type of in_int_raw_chn register
+ *  Raw status interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw: 1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+         *  turns to high level when the last data pointed by one inlink descriptor has been
+         *  received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw: 1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when data error is detected only in the
+         *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+         *  interrupt is reserved.
+         */
+        uint32_t in_err_eof_chn_int_raw: 1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+         *  including owner error and the second and third word error of inlink descriptor for
+         *  Rx channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw: 1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+         *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+         */
+        uint32_t in_dscr_empty_chn_int_raw: 1;
+        /** infifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l1_ovf_chn_int_raw: 1;
+        /** infifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l1_udf_chn_int_raw: 1;
+        /** infifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l2_ovf_chn_int_raw: 1;
+        /** infifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l2_udf_chn_int_raw: 1;
+        /** infifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l3_ovf_chn_int_raw: 1;
+        /** infifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l3_udf_chn_int_raw: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_raw_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st: 1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st: 1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st: 1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st: 1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st: 1;
+        /** infifo_l1_ovf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_st: 1;
+        /** infifo_l1_udf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_st: 1;
+        /** infifo_l2_ovf_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_st: 1;
+        /** infifo_l2_udf_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_st: 1;
+        /** infifo_l3_ovf_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_st: 1;
+        /** infifo_l3_udf_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_st: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_st_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena: 1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena: 1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena: 1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena: 1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena: 1;
+        /** infifo_l1_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_ena: 1;
+        /** infifo_l1_udf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_ena: 1;
+        /** infifo_l2_ovf_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_ena: 1;
+        /** infifo_l2_udf_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_ena: 1;
+        /** infifo_l3_ovf_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_ena: 1;
+        /** infifo_l3_udf_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_ena: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_ena_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr: 1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr: 1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr: 1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr: 1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr: 1;
+        /** infifo_l1_ovf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_clr: 1;
+        /** infifo_l1_udf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_clr: 1;
+        /** infifo_l2_ovf_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_clr: 1;
+        /** infifo_l2_udf_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_clr: 1;
+        /** infifo_l3_ovf_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_clr: 1;
+        /** infifo_l3_udf_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_clr: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_clr_chn_reg_t;
+
+/** Type of in_conf0_chn register
+ *  Configure 0 register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+         */
+        uint32_t in_rst_chn: 1;
+        /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn: 1;
+        /** mem_trans_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+         *  AXI_DMA.
+         */
+        uint32_t mem_trans_en_chn: 1;
+        /** in_etm_en_chn : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+         *  task.
+         */
+        uint32_t in_etm_en_chn: 1;
+        /** in_burst_size_sel_chn : R/W; bitpos: [6:4]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t in_burst_size_sel_chn: 3;
+        /** in_cmd_disable_chn : R/W; bitpos: [7]; default: 0;
+         *  1:mean disable cmd of this ch0
+         */
+        uint32_t in_cmd_disable_chn: 1;
+        /** in_ecc_aes_en_chn : R/W; bitpos: [8]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t in_ecc_aes_en_chn: 1;
+        /** indscr_burst_en_chn : R/W; bitpos: [9]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t indscr_burst_en_chn: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_in_conf0_chn_reg_t;
+
+/** Type of in_conf1_chn register
+ *  Configure 1 register of Rx channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} axi_dma_in_conf1_chn_reg_t;
+
+/** Type of infifo_status_chn register
+ *  Receive FIFO status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_l3_full_chn : RO; bitpos: [0]; default: 1;
+         *  L3 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_full_chn: 1;
+        /** infifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L3 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_empty_chn: 1;
+        /** infifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_l3_cnt_chn: 6;
+        /** infifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
+         *  L3 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_udf_chn: 1;
+        /** infifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
+         *  L3 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_ovf_chn: 1;
+        /** infifo_l1_full_chn : RO; bitpos: [10]; default: 0;
+         *  L1 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_full_chn: 1;
+        /** infifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
+         *  L1 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_empty_chn: 1;
+        /** infifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
+         *  L1 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_udf_chn: 1;
+        /** infifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
+         *  L1 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_ovf_chn: 1;
+        /** infifo_l2_full_chn : RO; bitpos: [14]; default: 0;
+         *  L2 Rx RAM full signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_full_chn: 1;
+        /** infifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
+         *  L2 Rx RAM empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_empty_chn: 1;
+        /** infifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
+         *  L2 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_udf_chn: 1;
+        /** infifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
+         *  L2 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_ovf_chn: 1;
+        uint32_t reserved_18: 5;
+        /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn: 1;
+        /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn: 1;
+        /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn: 1;
+        /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn: 1;
+        /** in_remain_under_5b_chn : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_5b_chn: 1;
+        /** in_remain_under_6b_chn : RO; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_6b_chn: 1;
+        /** in_remain_under_7b_chn : RO; bitpos: [29]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_7b_chn: 1;
+        /** in_remain_under_8b_chn : RO; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_8b_chn: 1;
+        /** in_buf_hungry_chn : RO; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_chn: 1;
+    };
+    uint32_t val;
+} axi_dma_infifo_status_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Pop control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
+         *  This register stores the data popping from AXI_DMA FIFO.
+         */
+        uint32_t infifo_rdata_chn: 12;
+        /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
+         *  Set this bit to pop data from AXI_DMA FIFO.
+         */
+        uint32_t infifo_pop_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} axi_dma_in_pop_chn_reg_t;
+
+/** Type of in_link1_chn register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_chn: 1;
+        /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn: 1;
+        /** inlink_start_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn: 1;
+        /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn: 1;
+        /** inlink_park_chn : RO; bitpos: [4]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} axi_dma_in_link1_chn_reg_t;
+
+/** Type of in_link2_chn register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 20 least significant bits of the first inlink descriptor's
+         *  address.
+         */
+        uint32_t inlink_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_link2_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Receive status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn: 18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn: 2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn: 3;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} axi_dma_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Inlink descriptor address when EOF occurs of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Inlink descriptor address when errors occur of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data. Only used when peripheral is UHCI0.
+         */
+        uint32_t in_err_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Current inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current inlink descriptor x.
+         */
+        uint32_t inlink_dscr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  The last inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  The second-to-last inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_bf1_chn_reg_t;
+
+/** Type of in_pri_chn register
+ *  Priority register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+         */
+        uint32_t rx_pri_chn: 4;
+        /** rx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
+         *  The weight of Rx channel 0
+         */
+        uint32_t rx_ch_arb_weigh_chn: 4;
+        /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
+         *  0: mean not optimization weight function ,1: mean optimization
+         */
+        uint32_t rx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_9: 23;
+    };
+    uint32_t val;
+} axi_dma_in_pri_chn_reg_t;
+
+/** Type of in_peri_sel_chn register
+ *  Peripheral selection of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+         *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+         */
+        uint32_t peri_in_sel_chn: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} axi_dma_in_peri_sel_chn_reg_t;
+
+/** Type of in_crc_init_data_chn register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of rx crc initial value
+         */
+        uint32_t in_crc_init_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_crc_init_data_chn_reg_t;
+
+/** Type of rx_crc_width_chn register
+ *  This register is used to config rx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_width_chn: 2;
+        /** rx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_latch_flag_chn: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_width_chn_reg_t;
+
+/** Type of in_crc_clear_chn register
+ *  This register is used to clear ch0 crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of rx crc result
+         */
+        uint32_t in_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_in_crc_clear_chn_reg_t;
+
+/** Type of in_crc_final_result_chn register
+ *  This register is used to store ch0 crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of rx
+         */
+        uint32_t in_crc_final_result_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_crc_final_result_chn_reg_t;
+
+/** Type of rx_crc_en_wr_data_chn register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable rx ch0 crc 32bit on/off
+         */
+        uint32_t rx_crc_en_wr_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_en_addr_chn register
+ *  This register is used to config ch0 crc en addr
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_en_addr_chn_reg_t;
+
+/** Type of rx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_wr_data_chn: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_data_en_addr_chn_reg_t;
+
+/** Group: out */
+/** Type of out_int_raw_chn register
+ *  Raw status interrupt of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel0.
+         */
+        uint32_t out_done_chn_int_raw: 1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel0.
+         */
+        uint32_t out_eof_chn_int_raw: 1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+         *  including owner error and the second and third word error of outlink descriptor for
+         *  Tx channel0.
+         */
+        uint32_t out_dscr_err_chn_int_raw: 1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel0.
+         */
+        uint32_t out_total_eof_chn_int_raw: 1;
+        /** outfifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_raw: 1;
+        /** outfifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l1_udf_chn_int_raw: 1;
+        /** outfifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_raw: 1;
+        /** outfifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l2_udf_chn_int_raw: 1;
+        /** outfifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_raw: 1;
+        /** outfifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l3_udf_chn_int_raw: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_raw_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st: 1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st: 1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st: 1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st: 1;
+        /** outfifo_l1_ovf_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_st: 1;
+        /** outfifo_l1_udf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_st: 1;
+        /** outfifo_l2_ovf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_st: 1;
+        /** outfifo_l2_udf_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_st: 1;
+        /** outfifo_l3_ovf_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_st: 1;
+        /** outfifo_l3_udf_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_st: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_st_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena: 1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena: 1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena: 1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena: 1;
+        /** outfifo_l1_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_ena: 1;
+        /** outfifo_l1_udf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_ena: 1;
+        /** outfifo_l2_ovf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_ena: 1;
+        /** outfifo_l2_udf_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_ena: 1;
+        /** outfifo_l3_ovf_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_ena: 1;
+        /** outfifo_l3_udf_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_ena: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_ena_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr: 1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr: 1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr: 1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr: 1;
+        /** outfifo_l1_ovf_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_clr: 1;
+        /** outfifo_l1_udf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_clr: 1;
+        /** outfifo_l2_ovf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_clr: 1;
+        /** outfifo_l2_udf_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_clr: 1;
+        /** outfifo_l3_ovf_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_clr: 1;
+        /** outfifo_l3_udf_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_clr: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_clr_chn_reg_t;
+
+/** Type of out_conf0_chn register
+ *  Configure 0 register of Tx channelN
+ */
+typedef union {
+    struct {
+        /** out_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_chn: 1;
+        /** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_chn: 1;
+        /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_chn: 1;
+        /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is
+         *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+         */
+        uint32_t out_eof_mode_chn: 1;
+        /** out_etm_en_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_chn: 1;
+        /** out_burst_size_sel_chn : R/W; bitpos: [7:5]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t out_burst_size_sel_chn: 3;
+        /** out_cmd_disable_chn : R/W; bitpos: [8]; default: 0;
+         *  1:mean disable cmd of this chn
+         */
+        uint32_t out_cmd_disable_chn: 1;
+        /** out_ecc_aes_en_chn : R/W; bitpos: [9]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t out_ecc_aes_en_chn: 1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_chn: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_out_conf0_chn_reg_t;
+
+/** Type of out_conf1_chn register
+ *  Configure 1 register of Tx channel0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} axi_dma_out_conf1_chn_reg_t;
+
+/** Type of outfifo_status_chn register
+ *  Transmit FIFO status of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outfifo_l3_full_chn : RO; bitpos: [0]; default: 0;
+         *  L3 Tx FIFO full signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_full_chn: 1;
+        /** outfifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L3 Tx FIFO empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_empty_chn: 1;
+        /** outfifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+         */
+        uint32_t outfifo_l3_cnt_chn: 6;
+        /** outfifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
+         *  L3 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_udf_chn: 1;
+        /** outfifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
+         *  L3 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_ovf_chn: 1;
+        /** outfifo_l1_full_chn : RO; bitpos: [10]; default: 0;
+         *  L1 Tx FIFO full signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_full_chn: 1;
+        /** outfifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
+         *  L1 Tx FIFO empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_empty_chn: 1;
+        /** outfifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
+         *  L1 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_udf_chn: 1;
+        /** outfifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
+         *  L1 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_ovf_chn: 1;
+        /** outfifo_l2_full_chn : RO; bitpos: [14]; default: 0;
+         *  L2 Tx RAM full signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_full_chn: 1;
+        /** outfifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
+         *  L2 Tx RAM empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_empty_chn: 1;
+        /** outfifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
+         *  L2 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_udf_chn: 1;
+        /** outfifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
+         *  L2 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_ovf_chn: 1;
+        uint32_t reserved_18: 5;
+        /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn: 1;
+        /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn: 1;
+        /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn: 1;
+        /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn: 1;
+        /** out_remain_under_5b_chn : RO; bitpos: [27]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_5b_chn: 1;
+        /** out_remain_under_6b_chn : RO; bitpos: [28]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_6b_chn: 1;
+        /** out_remain_under_7b_chn : RO; bitpos: [29]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_7b_chn: 1;
+        /** out_remain_under_8b_chn : RO; bitpos: [30]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_8b_chn: 1;
+        uint32_t reserved_31: 1;
+    };
+    uint32_t val;
+} axi_dma_outfifo_status_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Push control register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
+         *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+         */
+        uint32_t outfifo_wdata_chn: 9;
+        /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
+         *  Set this bit to push data into AXI_DMA FIFO.
+         */
+        uint32_t outfifo_push_chn: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_push_chn_reg_t;
+
+/** Type of out_link1_chn register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn: 1;
+        /** outlink_start_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn: 1;
+        /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn: 1;
+        /** outlink_park_chn : RO; bitpos: [3]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} axi_dma_out_link1_chn_reg_t;
+
+/** Type of out_link2_chn register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 32 least significant bits of the first outlink
+         *  descriptor's address.
+         */
+        uint32_t outlink_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_link2_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Transmit status of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn: 18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_chn: 2;
+        /** out_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_chn: 3;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} axi_dma_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Outlink descriptor address when EOF occurs of Tx channel0
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_eof_bfr_des_addr_chn register
+ *  The last outlink descriptor address when EOF occurs of Tx channel0
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor before the last outlink
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_eof_bfr_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Current outlink descriptor address of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current outlink descriptor y.
+         */
+        uint32_t outlink_dscr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  The last outlink descriptor address of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  The second-to-last outlink descriptor address of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor x-2.
+         */
+        uint32_t outlink_dscr_bf1_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_bf1_chn_reg_t;
+
+/** Type of out_pri_chn register
+ *  Priority register of Tx channel0.
+ */
+typedef union {
+    struct {
+        /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Tx channel0. The larger of the value the higher of the priority.
+         */
+        uint32_t tx_pri_chn: 4;
+        /** tx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
+         *  The weight of Tx channel0
+         */
+        uint32_t tx_ch_arb_weigh_chn: 4;
+        /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
+         *  0: mean not optimization weight function ,1: mean optimization
+         */
+        uint32_t tx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_9: 23;
+    };
+    uint32_t val;
+} axi_dma_out_pri_chn_reg_t;
+
+/** Type of out_peri_sel_chn register
+ *  Peripheral selection of Tx channel0
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+         *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+         */
+        uint32_t peri_out_sel_chn: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} axi_dma_out_peri_sel_chn_reg_t;
+
+/** Type of out_crc_init_data_chn register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of tx crc initial value
+         */
+        uint32_t out_crc_init_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_crc_init_data_chn_reg_t;
+
+/** Type of tx_crc_width_chn register
+ *  This register is used to config tx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_width_chn: 2;
+        /** tx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_latch_flag_chn: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_width_chn_reg_t;
+
+/** Type of out_crc_clear_chn register
+ *  This register is used to clear ch0 crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of tx crc result
+         */
+        uint32_t out_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_out_crc_clear_chn_reg_t;
+
+/** Type of out_crc_final_result_chn register
+ *  This register is used to store ch0 crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of tx
+         */
+        uint32_t out_crc_final_result_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_crc_final_result_chn_reg_t;
+
+/** Type of tx_crc_en_wr_data_chn register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable tx ch0 crc 32bit on/off
+         */
+        uint32_t tx_crc_en_wr_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_en_addr_chn register
+ *  This register is used to config ch0 crc en addr
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_en_addr_chn_reg_t;
+
+/** Type of tx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_wr_data_chn: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_data_en_addr_chn_reg_t;
+
+/** Group: Configuration Registers */
+/** Type of arb_timeout register
+ *  This retister is used to config arbiter time slice
+ */
+typedef union {
+    struct {
+        /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to config tx arbiter time out value
+         */
+        uint32_t arb_timeout_tx: 16;
+        /** arb_timeout_rx : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to config rx arbiter time out value
+         */
+        uint32_t arb_timeout_rx: 16;
+    };
+    uint32_t val;
+} axi_dma_arb_timeout_reg_t;
+
+/** Type of weight_en register
+ *  This register is used to config arbiter weight function to on or off
+ */
+typedef union {
+    struct {
+        /** weight_en_tx : R/W; bitpos: [0]; default: 0;
+         *  This register is used to config tx arbiter weight function  off/on
+         */
+        uint32_t weight_en_tx: 1;
+        /** weight_en_rx : R/W; bitpos: [1]; default: 0;
+         *  This register is used to config rx arbiter weight function  off/on
+         */
+        uint32_t weight_en_rx: 1;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} axi_dma_weight_en_reg_t;
+
+/** Type of in_mem_conf register
+ *  Mem power configure register of Rx channel
+ */
+typedef union {
+    struct {
+        /** in_mem_clk_force_en : R/W; bitpos: [0]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+         *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+         */
+        uint32_t in_mem_clk_force_en: 1;
+        /** in_mem_force_pu : R/W; bitpos: [1]; default: 0;
+         *  Force power up ram
+         */
+        uint32_t in_mem_force_pu: 1;
+        /** in_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Force power down ram
+         */
+        uint32_t in_mem_force_pd: 1;
+        /** out_mem_clk_force_en : R/W; bitpos: [3]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+         *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+         */
+        uint32_t out_mem_clk_force_en: 1;
+        /** out_mem_force_pu : R/W; bitpos: [4]; default: 0;
+         *  Force power up ram
+         */
+        uint32_t out_mem_force_pu: 1;
+        /** out_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  Force power down ram
+         */
+        uint32_t out_mem_force_pd: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} axi_dma_in_mem_conf_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_intr_mem_end_addr_reg_t;
+
+/** Type of extr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_extr_mem_start_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_extr_mem_start_addr_reg_t;
+
+/** Type of extr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_extr_mem_end_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_extr_mem_end_addr_reg_t;
+
+/** Type of in_reset_avail_chn register
+ *  The rx channel 0 reset valid_flag register.
+ */
+typedef union {
+    struct {
+        /** in_reset_avail_chn : RO; bitpos: [0]; default: 1;
+         *  rx chan0 reset valid reg.
+         */
+        uint32_t in_reset_avail_chn: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_in_reset_avail_chn_reg_t;
+
+/** Type of out_reset_avail_chn register
+ *  The tx channel 0 reset valid_flag register.
+ */
+typedef union {
+    struct {
+        /** out_reset_avail_chn : RO; bitpos: [0]; default: 1;
+         *  tx chan0 reset valid reg.
+         */
+        uint32_t out_reset_avail_chn: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_out_reset_avail_chn_reg_t;
+
+/** Type of misc_conf register
+ *  MISC register
+ */
+typedef union {
+    struct {
+        /** axim_rst_wr_inter : R/W; bitpos: [0]; default: 0;
+         *  Set this bit then clear this bit to reset the internal axi_wr FSM.
+         */
+        uint32_t axim_rst_wr_inter: 1;
+        /** axim_rst_rd_inter : R/W; bitpos: [1]; default: 0;
+         *  Set this bit then clear this bit to reset the internal axi_rd FSM.
+         */
+        uint32_t axim_rst_rd_inter: 1;
+        uint32_t reserved_2: 1;
+        /** arb_pri_dis : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to disable priority arbitration function.
+         */
+        uint32_t arb_pri_dis: 1;
+        /** clk_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} axi_dma_misc_conf_reg_t;
+
+/** Group: Debug Registers */
+/** Type of rdn_result register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_ena: 1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_result: 1;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} axi_dma_rdn_result_reg_t;
+
+/** Type of rdn_eco_high register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_high: 32;
+    };
+    uint32_t val;
+} axi_dma_rdn_eco_high_reg_t;
+
+/** Type of rdn_eco_low register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_low: 32;
+    };
+    uint32_t val;
+} axi_dma_rdn_eco_low_reg_t;
+
+/** Group: Status Registers */
+/** Type of wresp_cnt register
+ *  AXI wr response cnt register.
+ */
+typedef union {
+    struct {
+        /** wresp_cnt : RO; bitpos: [3:0]; default: 0;
+         *  axi wr response cnt reg.
+         */
+        uint32_t wresp_cnt: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} axi_dma_wresp_cnt_reg_t;
+
+/** Type of rresp_cnt register
+ *  AXI wr response cnt register.
+ */
+typedef union {
+    struct {
+        /** rresp_cnt : RO; bitpos: [3:0]; default: 0;
+         *  axi rd response cnt reg.
+         */
+        uint32_t rresp_cnt: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} axi_dma_rresp_cnt_reg_t;
+
+/** Type of infifo_status1_chn register
+ *  Receive FIFO status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** l1infifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+         */
+        uint32_t l1infifo_cnt_chn: 6;
+        /** l2infifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
+         *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+         */
+        uint32_t l2infifo_cnt_chn: 4;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_infifo_status1_chn_reg_t;
+
+/** Type of outfifo_status1_chn register
+ *  Receive FIFO status of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** l1outfifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+         */
+        uint32_t l1outfifo_cnt_chn: 6;
+        /** l2outfifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
+         *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+         */
+        uint32_t l2outfifo_cnt_chn: 4;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_outfifo_status1_chn_reg_t;
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36712768;
+         *  register version.
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} axi_dma_date_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_int_raw_chn_reg_t raw;
+    volatile axi_dma_in_int_st_chn_reg_t st;
+    volatile axi_dma_in_int_ena_chn_reg_t ena;
+    volatile axi_dma_in_int_clr_chn_reg_t clr;
+} axi_dma_in_int_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_conf0_chn_reg_t in_conf0;
+    volatile axi_dma_in_conf1_chn_reg_t in_conf1;
+    volatile axi_dma_infifo_status_chn_reg_t infifo_status;
+    volatile axi_dma_in_pop_chn_reg_t in_pop;
+    volatile axi_dma_in_link1_chn_reg_t in_link1;
+    volatile axi_dma_in_link2_chn_reg_t in_link2;
+    volatile axi_dma_in_state_chn_reg_t in_state;
+    volatile axi_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
+    volatile axi_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
+    volatile axi_dma_in_dscr_chn_reg_t in_dscr;
+    volatile axi_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
+    volatile axi_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
+    volatile axi_dma_in_pri_chn_reg_t in_pri;
+    volatile axi_dma_in_peri_sel_chn_reg_t in_peri_sel;
+} axi_dma_in_conf_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_crc_init_data_chn_reg_t in_crc_init_data;
+    volatile axi_dma_rx_crc_width_chn_reg_t rx_crc_width;
+    volatile axi_dma_in_crc_clear_chn_reg_t in_crc_clear;
+    volatile axi_dma_in_crc_final_result_chn_reg_t in_crc_final_result;
+    volatile axi_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data;
+    volatile axi_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr;
+    volatile axi_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data;
+    volatile axi_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr;
+} axi_dma_in_crc_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_int_chn_reg_t intr;
+    volatile axi_dma_in_conf_chn_reg_t conf;
+    volatile axi_dma_in_crc_chn_reg_t crc;
+} axi_dma_in_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_int_raw_chn_reg_t raw;
+    volatile axi_dma_out_int_st_chn_reg_t st;
+    volatile axi_dma_out_int_ena_chn_reg_t ena;
+    volatile axi_dma_out_int_clr_chn_reg_t clr;
+} axi_dma_out_int_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_conf0_chn_reg_t out_conf0;
+    volatile axi_dma_out_conf1_chn_reg_t out_conf1;
+    volatile axi_dma_outfifo_status_chn_reg_t outfifo_status;
+    volatile axi_dma_out_push_chn_reg_t out_push;
+    volatile axi_dma_out_link1_chn_reg_t out_link1;
+    volatile axi_dma_out_link2_chn_reg_t out_link2;
+    volatile axi_dma_out_state_chn_reg_t out_state;
+    volatile axi_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
+    volatile axi_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
+    volatile axi_dma_out_dscr_chn_reg_t out_dscr;
+    volatile axi_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
+    volatile axi_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
+    volatile axi_dma_out_pri_chn_reg_t out_pri;
+    volatile axi_dma_out_peri_sel_chn_reg_t out_peri_sel;
+} axi_dma_out_conf_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_crc_init_data_chn_reg_t out_crc_init_data;
+    volatile axi_dma_tx_crc_width_chn_reg_t tx_crc_width;
+    volatile axi_dma_out_crc_clear_chn_reg_t out_crc_clear;
+    volatile axi_dma_out_crc_final_result_chn_reg_t out_crc_final_result;
+    volatile axi_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data;
+    volatile axi_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr;
+    volatile axi_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data;
+    volatile axi_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr;
+} axi_dma_out_crc_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_int_chn_reg_t intr;
+    volatile axi_dma_out_conf_chn_reg_t conf;
+    volatile axi_dma_out_crc_chn_reg_t crc;
+} axi_dma_out_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_reg_t in[3];
+    volatile axi_dma_out_reg_t out[3];
+    volatile axi_dma_arb_timeout_reg_t arb_timeout;
+    volatile axi_dma_weight_en_reg_t weight_en;
+    volatile axi_dma_in_mem_conf_reg_t in_mem_conf;
+    volatile axi_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile axi_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile axi_dma_extr_mem_start_addr_reg_t extr_mem_start_addr;
+    volatile axi_dma_extr_mem_end_addr_reg_t extr_mem_end_addr;
+    volatile axi_dma_in_reset_avail_chn_reg_t in_reset_avail_chn[3];
+    volatile axi_dma_out_reset_avail_chn_reg_t out_reset_avail_chn[3];
+    uint32_t reserved_2a4;
+    volatile axi_dma_misc_conf_reg_t misc_conf;
+    volatile axi_dma_rdn_result_reg_t rdn_result;
+    volatile axi_dma_rdn_eco_high_reg_t rdn_eco_high;
+    volatile axi_dma_rdn_eco_low_reg_t rdn_eco_low;
+    volatile axi_dma_wresp_cnt_reg_t wresp_cnt;
+    volatile axi_dma_rresp_cnt_reg_t rresp_cnt;
+    volatile axi_dma_infifo_status1_chn_reg_t infifo_status1_chn[3];
+    volatile axi_dma_outfifo_status1_chn_reg_t outfifo_status1_chn[3];
+    volatile axi_dma_date_reg_t date;
+} axi_dma_dev_t;
+
+extern axi_dma_dev_t AXI_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(axi_dma_dev_t) == 0x2dc, "Invalid size of axi_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/axi_perf_mon_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/axi_perf_mon_reg.h
new file mode 100644
index 0000000000..bc1ebf8a28
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/axi_perf_mon_reg.h
@@ -0,0 +1,1858 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AXI_PERF_MON_CLK_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_CLK_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x0)
+/** AXI_PERF_MON_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  reserved
+ */
+#define AXI_PERF_MON_CLK_EN    (BIT(0))
+#define AXI_PERF_MON_CLK_EN_M  (AXI_PERF_MON_CLK_EN_V << AXI_PERF_MON_CLK_EN_S)
+#define AXI_PERF_MON_CLK_EN_V  0x00000001U
+#define AXI_PERF_MON_CLK_EN_S  0
+
+/** AXI_PERF_MON_AGENT_SELECT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_AGENT_SELECT_REG (DR_REG_AXI_PERF_MON_BASE + 0x4)
+/** AXI_PERF_MON_AGENT_SELECT : R/W; bitpos: [31:0]; default: 0;
+ *  Select Agent in slot to be monitored, 4 bits means one agent number
+ */
+#define AXI_PERF_MON_AGENT_SELECT    0xFFFFFFFFU
+#define AXI_PERF_MON_AGENT_SELECT_M  (AXI_PERF_MON_AGENT_SELECT_V << AXI_PERF_MON_AGENT_SELECT_S)
+#define AXI_PERF_MON_AGENT_SELECT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_AGENT_SELECT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x8)
+/** AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0xc)
+/** AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x10)
+/** AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x14)
+/** AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x18)
+/** AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c)
+/** AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x20)
+/** AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x24)
+/** AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x28)
+/** AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x2c)
+/** AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0x30)
+/** AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0x34)
+/** AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x38)
+/** AXI_PERF_MON_SEL_AG0_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x3c)
+/** AXI_PERF_MON_SEL_AG1_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x40)
+/** AXI_PERF_MON_SEL_AG0_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x44)
+/** AXI_PERF_MON_SEL_AG1_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x48)
+/** AXI_PERF_MON_SEL_AG0_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x4c)
+/** AXI_PERF_MON_SEL_AG1_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x50)
+/** AXI_PERF_MON_SEL_AG0_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x54)
+/** AXI_PERF_MON_SEL_AG1_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x58)
+/** AXI_PERF_MON_SEL_AG0_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x5c)
+/** AXI_PERF_MON_SEL_AG1_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x60)
+/** AXI_PERF_MON_SEL_AG0_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x64)
+/** AXI_PERF_MON_SEL_AG1_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x68)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x6c)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x70)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x74)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x78)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x7c)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x80)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x84)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x88)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x8c)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x90)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x94)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x98)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x9c)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0xa0)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0xa4)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0xa8)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0xac)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0xb0)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0xb4)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0xb8)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0xbc)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0xc0)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0xc4)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0xc8)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0xcc)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0xd0)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0xd4)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0xd8)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0xdc)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0xe0)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0xe4)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0xe8)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0xec)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0xf0)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0xf4)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0xf8)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0xfc)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x100)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x104)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x108)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x10c)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x110)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x114)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x118)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x11c)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x120)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x124)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x128)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x12c)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x130)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x134)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x138)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x13c)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x140)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x144)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x148)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x14c)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x150)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x154)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x158)
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x15c)
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x160)
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x164)
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG_RD_ADDR_REGION_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_RD_ADDR_REGION_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x168)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL : R/W; bitpos: [5:3]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_S  3
+
+/** AXI_PERF_MON_SEL_AG_WR_ADDR_REGION_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_WR_ADDR_REGION_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x16c)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL : R/W; bitpos: [5:3]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_S  3
+
+/** AXI_PERF_MON_SEL_AG_ADDR_FILTER_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_ADDR_FILTER_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x170)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN : R/W; bitpos: [1]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_S  1
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN : R/W; bitpos: [2]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN    (BIT(2))
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN : R/W; bitpos: [3]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_S  3
+
+/** AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x174)
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN : WT; bitpos: [0]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_S  0
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN : WT; bitpos: [1]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_S  1
+
+/** AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_CLR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_CLR_REG (DR_REG_AXI_PERF_MON_BASE + 0x178)
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR : WT; bitpos: [0]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_S  0
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR : WT; bitpos: [1]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_S  1
+
+/** AXI_PERF_MON_SEL_AG_INS_BANDW_TEST_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INS_BANDW_TEST_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x17c)
+/** AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN : R/W; bitpos: [1]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_S  1
+/** AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN : R/W; bitpos: [2]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN    (BIT(2))
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN : R/W; bitpos: [3]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_S  3
+
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x180)
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x184)
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG0_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x188)
+/** AXI_PERF_MON_SEL_AG0_RD_ID_MASK : R/W; bitpos: [7:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG0_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG0_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_ID_MASK : R/W; bitpos: [15:8]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG0_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG0_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK_S  8
+
+/** AXI_PERF_MON_SEL_AG1_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x18c)
+/** AXI_PERF_MON_SEL_AG1_RD_ID_MASK : R/W; bitpos: [7:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG1_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG1_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_ID_MASK : R/W; bitpos: [15:8]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG1_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG1_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK_S  8
+
+/** AXI_PERF_MON_SEL_AG0_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x190)
+/** AXI_PERF_MON_SEL_AG0_RD_ID_FILTER : R/W; bitpos: [7:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_ID_FILTER : R/W; bitpos: [15:8]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_S  8
+
+/** AXI_PERF_MON_SEL_AG1_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x194)
+/** AXI_PERF_MON_SEL_AG1_RD_ID_FILTER : R/W; bitpos: [7:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_ID_FILTER : R/W; bitpos: [15:8]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_S  8
+
+/** AXI_PERF_MON_SEL_AG_BANDW_TEST_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_BANDW_TEST_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x198)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN : R/W; bitpos: [1]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_S  1
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN    (BIT(2))
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN : R/W; bitpos: [3]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_S  3
+
+/** AXI_PERF_MON_SEL_AG_BANDW_TEST_STOP_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_BANDW_TEST_STOP_REG (DR_REG_AXI_PERF_MON_BASE + 0x19c)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP : R/W; bitpos: [1]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP    (BIT(1))
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_S  1
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP    (BIT(2))
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP : R/W; bitpos: [3]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_S  3
+
+/** AXI_PERF_MON_SEL_AG0_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x1a0)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG1_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x1a4)
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x1a8)
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x1ac)
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x1b0)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x1b4)
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x1b8)
+/** AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x1bc)
+/** AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG_INT_RAW_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_RAW_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c0)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [0];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [1];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  1
+
+/** AXI_PERF_MON_SEL_AG_INT_ST_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_ST_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c4)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_S  1
+
+/** AXI_PERF_MON_SEL_AG_INT_ENA_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_ENA_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c8)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  1
+
+/** AXI_PERF_MON_SEL_AG_INT_CLR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_CLR_REG (DR_REG_AXI_PERF_MON_BASE + 0x1cc)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/axi_perf_mon_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/axi_perf_mon_struct.h
new file mode 100644
index 0000000000..eceee2b302
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/axi_perf_mon_struct.h
@@ -0,0 +1,1995 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of clk_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  reserved
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_perf_mon_clk_en_reg_t;
+
+/** Type of sel_ag0_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range0_cnt_high:16;
+        /** sel_ag0_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range0_reg_t;
+
+/** Type of sel_ag1_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range0_cnt_high:16;
+        /** sel_ag1_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range0_reg_t;
+
+/** Type of sel_ag0_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range1_cnt_high:16;
+        /** sel_ag0_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range1_reg_t;
+
+/** Type of sel_ag1_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range1_cnt_high:16;
+        /** sel_ag1_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range1_reg_t;
+
+/** Type of sel_ag0_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range2_cnt_high:16;
+        /** sel_ag0_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range2_reg_t;
+
+/** Type of sel_ag1_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range2_cnt_high:16;
+        /** sel_ag1_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range2_reg_t;
+
+/** Type of sel_ag0_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range3_cnt_high:16;
+        /** sel_ag0_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range3_reg_t;
+
+/** Type of sel_ag1_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range3_cnt_high:16;
+        /** sel_ag1_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range3_reg_t;
+
+/** Type of sel_ag0_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range4_cnt_high:16;
+        /** sel_ag0_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range4_reg_t;
+
+/** Type of sel_ag1_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range4_cnt_high:16;
+        /** sel_ag1_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range4_reg_t;
+
+/** Type of sel_ag0_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range5_cnt_high:16;
+        /** sel_ag0_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range5_reg_t;
+
+/** Type of sel_ag1_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range5_cnt_high:16;
+        /** sel_ag1_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range5_reg_t;
+
+/** Type of sel_ag0_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag1_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag0_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag1_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag0_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag1_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag0_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag1_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag0_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag1_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag0_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag1_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag0_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag1_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag0_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag1_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag0_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag1_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag0_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag1_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag0_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag1_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag0_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag1_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag0_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag0_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_select1_reg_t;
+
+/** Type of sel_ag1_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag1_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_select1_reg_t;
+
+/** Type of sel_ag0_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag0_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_select2_reg_t;
+
+/** Type of sel_ag1_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag1_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_select2_reg_t;
+
+/** Type of sel_ag_rd_addr_region_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_region_sel : R/W; bitpos: [2:0]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag0_rd_addr_region_sel:3;
+        /** sel_ag1_rd_addr_region_sel : R/W; bitpos: [5:3]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag1_rd_addr_region_sel:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_rd_addr_region_sel_reg_t;
+
+/** Type of sel_ag_wr_addr_region_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_region_sel : R/W; bitpos: [2:0]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag0_wr_addr_region_sel:3;
+        /** sel_ag1_wr_addr_region_sel : R/W; bitpos: [5:3]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag1_wr_addr_region_sel:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_wr_addr_region_sel_reg_t;
+
+/** Type of sel_ag_addr_filter_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter_en : R/W; bitpos: [0]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag0_rd_addr_filter_en:1;
+        /** sel_ag1_rd_addr_filter_en : R/W; bitpos: [1]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag1_rd_addr_filter_en:1;
+        /** sel_ag0_wr_addr_filter_en : R/W; bitpos: [2]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag0_wr_addr_filter_en:1;
+        /** sel_ag1_wr_addr_filter_en : R/W; bitpos: [3]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag1_wr_addr_filter_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_addr_filter_en_reg_t;
+
+/** Type of sel_ag_sw_record_stop_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_sw_record_stop_en : WT; bitpos: [0]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag0_sw_record_stop_en:1;
+        /** sel_ag1_sw_record_stop_en : WT; bitpos: [1]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag1_sw_record_stop_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_sw_record_stop_en_reg_t;
+
+/** Type of sel_ag_sw_record_stop_clr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_sw_record_stop_clr : WT; bitpos: [0]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag0_sw_record_stop_clr:1;
+        /** sel_ag1_sw_record_stop_clr : WT; bitpos: [1]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag1_sw_record_stop_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_sw_record_stop_clr_reg_t;
+
+/** Type of sel_ag_ins_bandw_test_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_ins_bandw_test_en : R/W; bitpos: [0]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_rd_ins_bandw_test_en:1;
+        /** sel_ag0_wr_ins_bandw_test_en : R/W; bitpos: [1]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_wr_ins_bandw_test_en:1;
+        /** sel_ag1_rd_ins_bandw_test_en : R/W; bitpos: [2]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_rd_ins_bandw_test_en:1;
+        /** sel_ag1_wr_ins_bandw_test_en : R/W; bitpos: [3]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_wr_ins_bandw_test_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_ins_bandw_test_en_reg_t;
+
+/** Type of sel_ag0_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag0_sw_record_stop_rd_data_limit:16;
+        /** sel_ag0_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag0_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag1_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag1_sw_record_stop_rd_data_limit:16;
+        /** sel_ag1_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag1_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag0_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_id_mask : R/W; bitpos: [7:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag0_rd_id_mask:8;
+        /** sel_ag0_wr_id_mask : R/W; bitpos: [15:8]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag0_wr_id_mask:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_id_mask_reg_t;
+
+/** Type of sel_ag1_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_id_mask : R/W; bitpos: [7:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag1_rd_id_mask:8;
+        /** sel_ag1_wr_id_mask : R/W; bitpos: [15:8]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag1_wr_id_mask:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_id_mask_reg_t;
+
+/** Type of sel_ag0_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_id_filter : R/W; bitpos: [7:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag0_rd_id_filter:8;
+        /** sel_ag0_wr_id_filter : R/W; bitpos: [15:8]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag0_wr_id_filter:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_id_filter_reg_t;
+
+/** Type of sel_ag1_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_id_filter : R/W; bitpos: [7:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag1_rd_id_filter:8;
+        /** sel_ag1_wr_id_filter : R/W; bitpos: [15:8]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag1_wr_id_filter:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_id_filter_reg_t;
+
+/** Type of sel_ag_bandw_test_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_test_en : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag0_rd_bandw_test_en:1;
+        /** sel_ag0_wr_bandw_test_en : R/W; bitpos: [1]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_wr_bandw_test_en:1;
+        /** sel_ag1_rd_bandw_test_en : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag1_rd_bandw_test_en:1;
+        /** sel_ag1_wr_bandw_test_en : R/W; bitpos: [3]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_wr_bandw_test_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_bandw_test_en_reg_t;
+
+/** Type of sel_ag_bandw_test_stop register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_test_stop : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag0_rd_bandw_test_stop:1;
+        /** sel_ag0_wr_bandw_test_stop : R/W; bitpos: [1]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_wr_bandw_test_stop:1;
+        /** sel_ag1_rd_bandw_test_stop : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag1_rd_bandw_test_stop:1;
+        /** sel_ag1_wr_bandw_test_stop : R/W; bitpos: [3]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_wr_bandw_test_stop:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_bandw_test_stop_reg_t;
+
+/** Type of sel_ag0_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag0_rd_bandw_trigger_en_sel:4;
+        /** sel_ag0_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag0_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag0_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag0_wr_bandw_trigger_en_sel:4;
+        /** sel_ag0_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag0_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag1_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag1_rd_bandw_trigger_en_sel:4;
+        /** sel_ag1_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag1_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag1_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag1_wr_bandw_trigger_en_sel:4;
+        /** sel_ag1_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag1_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag0_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag0_rd_ins_bandw_time_thr:16;
+        /** sel_ag0_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag0_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_time_thr_reg_t;
+
+/** Type of sel_ag1_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag1_rd_ins_bandw_time_thr:16;
+        /** sel_ag1_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag1_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_time_thr_reg_t;
+
+
+/** Group: Peripheral Select Registers */
+/** Type of agent_select register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** agent_select : R/W; bitpos: [31:0]; default: 0;
+         *  Select Agent in slot to be monitored, 4 bits means one agent number
+         */
+        uint32_t agent_select:32;
+    };
+    uint32_t val;
+} axi_perf_mon_agent_select_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of sel_ag0_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter0_reg_t;
+
+/** Type of sel_ag1_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter0_reg_t;
+
+/** Type of sel_ag0_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter1_reg_t;
+
+/** Type of sel_ag1_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter1_reg_t;
+
+/** Type of sel_ag0_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter2_reg_t;
+
+/** Type of sel_ag1_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter2_reg_t;
+
+/** Type of sel_ag0_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter3_reg_t;
+
+/** Type of sel_ag1_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter3_reg_t;
+
+/** Type of sel_ag0_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter4_reg_t;
+
+/** Type of sel_ag1_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter4_reg_t;
+
+/** Type of sel_ag0_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter5_reg_t;
+
+/** Type of sel_ag1_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter5_reg_t;
+
+/** Type of sel_ag0_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range0_reg_t;
+
+/** Type of sel_ag1_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range0_reg_t;
+
+/** Type of sel_ag0_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range1_reg_t;
+
+/** Type of sel_ag1_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range1_reg_t;
+
+/** Type of sel_ag0_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range2_reg_t;
+
+/** Type of sel_ag1_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range2_reg_t;
+
+/** Type of sel_ag0_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range3_reg_t;
+
+/** Type of sel_ag1_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range3_reg_t;
+
+/** Type of sel_ag0_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range4_reg_t;
+
+/** Type of sel_ag1_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range4_reg_t;
+
+/** Type of sel_ag0_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range5_reg_t;
+
+/** Type of sel_ag1_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range5_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag0_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag0_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag0_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag0_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag1_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag1_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag1_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag1_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag0_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag0_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag0_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag0_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag1_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag1_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag1_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag1_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of sel_ag_int_raw register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_raw:1;
+        /** sel_ag1_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_raw_reg_t;
+
+/** Type of sel_ag_int_st register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_st:1;
+        /** sel_ag1_record_cnt_under_limit_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_st_reg_t;
+
+/** Type of sel_ag_int_ena register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_ena:1;
+        /** sel_ag1_record_cnt_under_limit_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_ena_reg_t;
+
+/** Type of sel_ag_int_clr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_clr:1;
+        /** sel_ag1_record_cnt_under_limit_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_clr_reg_t;
+
+
+typedef struct {
+    volatile axi_perf_mon_clk_en_reg_t clk_en;
+    volatile axi_perf_mon_agent_select_reg_t agent_select;
+    volatile axi_perf_mon_sel_ag0_counter0_reg_t sel_ag0_counter0;
+    volatile axi_perf_mon_sel_ag1_counter0_reg_t sel_ag1_counter0;
+    volatile axi_perf_mon_sel_ag0_counter1_reg_t sel_ag0_counter1;
+    volatile axi_perf_mon_sel_ag1_counter1_reg_t sel_ag1_counter1;
+    volatile axi_perf_mon_sel_ag0_counter2_reg_t sel_ag0_counter2;
+    volatile axi_perf_mon_sel_ag1_counter2_reg_t sel_ag1_counter2;
+    volatile axi_perf_mon_sel_ag0_counter3_reg_t sel_ag0_counter3;
+    volatile axi_perf_mon_sel_ag1_counter3_reg_t sel_ag1_counter3;
+    volatile axi_perf_mon_sel_ag0_counter4_reg_t sel_ag0_counter4;
+    volatile axi_perf_mon_sel_ag1_counter4_reg_t sel_ag1_counter4;
+    volatile axi_perf_mon_sel_ag0_counter5_reg_t sel_ag0_counter5;
+    volatile axi_perf_mon_sel_ag1_counter5_reg_t sel_ag1_counter5;
+    volatile axi_perf_mon_sel_ag0_range0_reg_t sel_ag0_range0;
+    volatile axi_perf_mon_sel_ag1_range0_reg_t sel_ag1_range0;
+    volatile axi_perf_mon_sel_ag0_range1_reg_t sel_ag0_range1;
+    volatile axi_perf_mon_sel_ag1_range1_reg_t sel_ag1_range1;
+    volatile axi_perf_mon_sel_ag0_range2_reg_t sel_ag0_range2;
+    volatile axi_perf_mon_sel_ag1_range2_reg_t sel_ag1_range2;
+    volatile axi_perf_mon_sel_ag0_range3_reg_t sel_ag0_range3;
+    volatile axi_perf_mon_sel_ag1_range3_reg_t sel_ag1_range3;
+    volatile axi_perf_mon_sel_ag0_range4_reg_t sel_ag0_range4;
+    volatile axi_perf_mon_sel_ag1_range4_reg_t sel_ag1_range4;
+    volatile axi_perf_mon_sel_ag0_range5_reg_t sel_ag0_range5;
+    volatile axi_perf_mon_sel_ag1_range5_reg_t sel_ag1_range5;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record0_reg_t sel_ag0_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record0_reg_t sel_ag1_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record1_reg_t sel_ag0_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record1_reg_t sel_ag1_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record2_reg_t sel_ag0_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record2_reg_t sel_ag1_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record3_reg_t sel_ag0_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record3_reg_t sel_ag1_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record0_reg_t sel_ag0_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record0_reg_t sel_ag1_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record1_reg_t sel_ag0_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record1_reg_t sel_ag1_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record2_reg_t sel_ag0_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record2_reg_t sel_ag1_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record3_reg_t sel_ag0_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record3_reg_t sel_ag1_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data0_reg_t sel_ag0_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data0_reg_t sel_ag1_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data1_reg_t sel_ag0_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data1_reg_t sel_ag1_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data2_reg_t sel_ag0_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data2_reg_t sel_ag1_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data3_reg_t sel_ag0_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data3_reg_t sel_ag1_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag0_metric_range0_reg_t sel_ag0_metric_range0;
+    volatile axi_perf_mon_sel_ag1_metric_range0_reg_t sel_ag1_metric_range0;
+    volatile axi_perf_mon_sel_ag0_metric_range1_reg_t sel_ag0_metric_range1;
+    volatile axi_perf_mon_sel_ag1_metric_range1_reg_t sel_ag1_metric_range1;
+    volatile axi_perf_mon_sel_ag0_metric_range2_reg_t sel_ag0_metric_range2;
+    volatile axi_perf_mon_sel_ag1_metric_range2_reg_t sel_ag1_metric_range2;
+    volatile axi_perf_mon_sel_ag0_metric_range3_reg_t sel_ag0_metric_range3;
+    volatile axi_perf_mon_sel_ag1_metric_range3_reg_t sel_ag1_metric_range3;
+    volatile axi_perf_mon_sel_ag0_metric_range4_reg_t sel_ag0_metric_range4;
+    volatile axi_perf_mon_sel_ag1_metric_range4_reg_t sel_ag1_metric_range4;
+    volatile axi_perf_mon_sel_ag0_metric_range5_reg_t sel_ag0_metric_range5;
+    volatile axi_perf_mon_sel_ag1_metric_range5_reg_t sel_ag1_metric_range5;
+    volatile axi_perf_mon_sel_ag0_rd_addr_mask0_reg_t sel_ag0_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag1_rd_addr_mask0_reg_t sel_ag1_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag0_rd_addr_mask1_reg_t sel_ag0_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag1_rd_addr_mask1_reg_t sel_ag1_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag0_rd_addr_mask2_reg_t sel_ag0_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag1_rd_addr_mask2_reg_t sel_ag1_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag0_wr_addr_mask0_reg_t sel_ag0_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag1_wr_addr_mask0_reg_t sel_ag1_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag0_wr_addr_mask1_reg_t sel_ag0_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag1_wr_addr_mask1_reg_t sel_ag1_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag0_wr_addr_mask2_reg_t sel_ag0_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag1_wr_addr_mask2_reg_t sel_ag1_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag0_rd_addr_filter0_reg_t sel_ag0_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag1_rd_addr_filter0_reg_t sel_ag1_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag0_rd_addr_filter1_reg_t sel_ag0_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag1_rd_addr_filter1_reg_t sel_ag1_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag0_rd_addr_filter2_reg_t sel_ag0_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag1_rd_addr_filter2_reg_t sel_ag1_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag0_wr_addr_filter0_reg_t sel_ag0_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag1_wr_addr_filter0_reg_t sel_ag1_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag0_wr_addr_filter1_reg_t sel_ag0_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag1_wr_addr_filter1_reg_t sel_ag1_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag0_wr_addr_filter2_reg_t sel_ag0_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag1_wr_addr_filter2_reg_t sel_ag1_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag0_metric_select1_reg_t sel_ag0_metric_select1;
+    volatile axi_perf_mon_sel_ag1_metric_select1_reg_t sel_ag1_metric_select1;
+    volatile axi_perf_mon_sel_ag0_metric_select2_reg_t sel_ag0_metric_select2;
+    volatile axi_perf_mon_sel_ag1_metric_select2_reg_t sel_ag1_metric_select2;
+    volatile axi_perf_mon_sel_ag_rd_addr_region_sel_reg_t sel_ag_rd_addr_region_sel;
+    volatile axi_perf_mon_sel_ag_wr_addr_region_sel_reg_t sel_ag_wr_addr_region_sel;
+    volatile axi_perf_mon_sel_ag_addr_filter_en_reg_t sel_ag_addr_filter_en;
+    volatile axi_perf_mon_sel_ag_sw_record_stop_en_reg_t sel_ag_sw_record_stop_en;
+    volatile axi_perf_mon_sel_ag_sw_record_stop_clr_reg_t sel_ag_sw_record_stop_clr;
+    volatile axi_perf_mon_sel_ag_ins_bandw_test_en_reg_t sel_ag_ins_bandw_test_en;
+    volatile axi_perf_mon_sel_ag0_sw_record_stop_data_limit_reg_t sel_ag0_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag1_sw_record_stop_data_limit_reg_t sel_ag1_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag0_id_mask_reg_t sel_ag0_id_mask;
+    volatile axi_perf_mon_sel_ag1_id_mask_reg_t sel_ag1_id_mask;
+    volatile axi_perf_mon_sel_ag0_id_filter_reg_t sel_ag0_id_filter;
+    volatile axi_perf_mon_sel_ag1_id_filter_reg_t sel_ag1_id_filter;
+    volatile axi_perf_mon_sel_ag_bandw_test_en_reg_t sel_ag_bandw_test_en;
+    volatile axi_perf_mon_sel_ag_bandw_test_stop_reg_t sel_ag_bandw_test_stop;
+    volatile axi_perf_mon_sel_ag0_bandw_trigger_in_sel_reg_t sel_ag0_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag1_bandw_trigger_in_sel_reg_t sel_ag1_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag0_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag0_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag1_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag1_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag0_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag0_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag1_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag1_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_time_thr_reg_t sel_ag0_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_time_thr_reg_t sel_ag1_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag_int_raw_reg_t sel_ag_int_raw;
+    volatile axi_perf_mon_sel_ag_int_st_reg_t sel_ag_int_st;
+    volatile axi_perf_mon_sel_ag_int_ena_reg_t sel_ag_int_ena;
+    volatile axi_perf_mon_sel_ag_int_clr_reg_t sel_ag_int_clr;
+} axi_perf_mon_dev_t;
+
+extern axi_perf_mon_dev_t AXI_PERF_MON;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(axi_perf_mon_dev_t) == 0x1d0, "Invalid size of axi_perf_mon_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_eco5_struct.h
new file mode 100644
index 0000000000..904de77a89
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_eco5_struct.h
@@ -0,0 +1,437 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of tx_inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t tx_inst_idx:3;
+        /** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t tx_inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_tx_inst_cfg0_reg_t;
+
+/** Type of tx_inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_inst : R/W; bitpos: [31:0]; default: 4;
+         *  write this bits to update instruction which specified by
+         *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
+         *  BITSCRAMBLER_TX_INST_CFG0_REG
+         */
+        uint32_t tx_inst:32;
+    };
+    uint32_t val;
+} bitscrambler_tx_inst_cfg1_reg_t;
+
+/** Type of rx_inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t rx_inst_idx:3;
+        /** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t rx_inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_rx_inst_cfg0_reg_t;
+
+/** Type of rx_inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_inst : R/W; bitpos: [31:0]; default: 12;
+         *  write this bits to update instruction which specified by
+         *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
+         *  BITSCRAMBLER_RX_INST_CFG0_REG
+         */
+        uint32_t rx_inst:32;
+    };
+    uint32_t val;
+} bitscrambler_rx_inst_cfg1_reg_t;
+
+/** Type of tx_lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on
+         *  reg_bitscrambler_tx_lut_mode
+         */
+        uint32_t tx_lut_idx:11;
+        /** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t tx_lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_tx_lut_cfg0_reg_t;
+
+/** Type of tx_lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_lut : R/W; bitpos: [31:0]; default: 20;
+         *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
+         *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
+         */
+        uint32_t tx_lut:32;
+    };
+    uint32_t val;
+} bitscrambler_tx_lut_cfg1_reg_t;
+
+/** Type of rx_lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on
+         *  reg_bitscrambler_rx_lut_mode
+         */
+        uint32_t rx_lut_idx:11;
+        /** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t rx_lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_rx_lut_cfg0_reg_t;
+
+/** Type of rx_lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_lut : R/W; bitpos: [31:0]; default: 28;
+         *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
+         *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
+         */
+        uint32_t rx_lut:32;
+    };
+    uint32_t val;
+} bitscrambler_rx_lut_cfg1_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of tx_tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t tx_tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_tx_tailing_bits_reg_t;
+
+/** Type of rx_tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t rx_tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_rx_tailing_bits_reg_t;
+
+/** Type of tx_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler tx
+         */
+        uint32_t tx_ena:1;
+        /** tx_pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler tx core
+         */
+        uint32_t tx_pause:1;
+        /** tx_halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler tx core
+         */
+        uint32_t tx_halt:1;
+        /** tx_eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
+         *  counter by write peripheral buffer
+         */
+        uint32_t tx_eof_mode:1;
+        /** tx_cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t tx_cond_mode:1;
+        /** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t tx_fetch_mode:1;
+        /** tx_halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t tx_halt_mode:1;
+        /** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t tx_rd_dummy:1;
+        /** tx_fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler tx fifo
+         */
+        uint32_t tx_fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_tx_ctrl_reg_t;
+
+/** Type of rx_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler rx
+         */
+        uint32_t rx_ena:1;
+        /** rx_pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler rx core
+         */
+        uint32_t rx_pause:1;
+        /** rx_halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler rx core
+         */
+        uint32_t rx_halt:1;
+        /** rx_eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
+         *  buffer, 0 counter by write dma fifo
+         */
+        uint32_t rx_eof_mode:1;
+        /** rx_cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t rx_cond_mode:1;
+        /** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t rx_fetch_mode:1;
+        /** rx_halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t rx_halt_mode:1;
+        /** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t rx_rd_dummy:1;
+        /** rx_fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler rx fifo
+         */
+        uint32_t rx_fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_rx_ctrl_reg_t;
+
+/** Type of sys register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** loop_mode : R/W; bitpos: [0]; default: 0;
+         *  write this bit to set the bitscrambler tx loop back to DMA rx
+         */
+        uint32_t loop_mode:1;
+        uint32_t reserved_1:30;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} bitscrambler_sys_reg_t;
+
+
+/** Group: Status registers */
+/** Type of tx_state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** tx_in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler tx core in halt mode
+         */
+        uint32_t tx_in_idle:1;
+        /** tx_in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler tx core in run mode
+         */
+        uint32_t tx_in_run:1;
+        /** tx_in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler tx core in wait mode to wait write back done
+         */
+        uint32_t tx_in_wait:1;
+        /** tx_in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler tx core in pause mode
+         */
+        uint32_t tx_in_pause:1;
+        /** tx_fifo_empty : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler tx fifo in empty state
+         */
+        uint32_t tx_fifo_empty:1;
+        uint32_t reserved_5:11;
+        /** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler tx core when get EOF
+         */
+        uint32_t tx_eof_get_cnt:14;
+        /** tx_eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler tx core
+         */
+        uint32_t tx_eof_overload:1;
+        /** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_tx_eof_overload and
+         *  reg_bitscrambler_tx_eof_get_cnt registers
+         */
+        uint32_t tx_eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_tx_state_reg_t;
+
+/** Type of rx_state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** rx_in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler rx core in halt mode
+         */
+        uint32_t rx_in_idle:1;
+        /** rx_in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler rx core in run mode
+         */
+        uint32_t rx_in_run:1;
+        /** rx_in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler rx core in wait mode to wait write back done
+         */
+        uint32_t rx_in_wait:1;
+        /** rx_in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler rx core in pause mode
+         */
+        uint32_t rx_in_pause:1;
+        /** rx_fifo_full : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler rx fifo in full state
+         */
+        uint32_t rx_fifo_full:1;
+        uint32_t reserved_5:11;
+        /** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler rx core when get EOF
+         */
+        uint32_t rx_eof_get_cnt:14;
+        /** rx_eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler rx core
+         */
+        uint32_t rx_eof_overload:1;
+        /** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_rx_eof_overload and
+         *  reg_bitscrambler_rx_eof_get_cnt registers
+         */
+        uint32_t rx_eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_rx_state_reg_t;
+
+
+/** Group: Version register */
+/** Type of version register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
+         *  Reserved
+         */
+        uint32_t bitscrambler_ver:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} bitscrambler_version_reg_t;
+
+
+typedef struct {
+    volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
+    volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
+    volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
+    volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
+    volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
+    volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
+    volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
+    volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
+    volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
+    volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
+    volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
+    volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
+    volatile bitscrambler_tx_state_reg_t tx_state;
+    volatile bitscrambler_rx_state_reg_t rx_state;
+    uint32_t reserved_038[48];
+    volatile bitscrambler_sys_reg_t sys;
+    volatile bitscrambler_version_reg_t version;
+} bitscrambler_dev_t;
+
+extern bitscrambler_dev_t BITSCRAMBLER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_reg.h
new file mode 100644
index 0000000000..5bee86a8b5
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_reg.h
@@ -0,0 +1,481 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** BITSCRAMBLER_TX_INST_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0)
+/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
+ *  write this bits to specify the one of 8 instruction
+ */
+#define BITSCRAMBLER_TX_INST_IDX    0x00000007U
+#define BITSCRAMBLER_TX_INST_IDX_M  (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S)
+#define BITSCRAMBLER_TX_INST_IDX_V  0x00000007U
+#define BITSCRAMBLER_TX_INST_IDX_S  0
+/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0;
+ *  write this bits to specify the bit position of 257 bit instruction which in units
+ *  of 32 bits
+ */
+#define BITSCRAMBLER_TX_INST_POS    0x0000000FU
+#define BITSCRAMBLER_TX_INST_POS_M  (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S)
+#define BITSCRAMBLER_TX_INST_POS_V  0x0000000FU
+#define BITSCRAMBLER_TX_INST_POS_S  3
+
+/** BITSCRAMBLER_TX_INST_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4)
+/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4;
+ *  write this bits to update instruction which specified by
+ *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
+ *  BITSCRAMBLER_TX_INST_CFG0_REG
+ */
+#define BITSCRAMBLER_TX_INST    0xFFFFFFFFU
+#define BITSCRAMBLER_TX_INST_M  (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S)
+#define BITSCRAMBLER_TX_INST_V  0xFFFFFFFFU
+#define BITSCRAMBLER_TX_INST_S  0
+
+/** BITSCRAMBLER_RX_INST_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8)
+/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
+ *  write this bits to specify the one of 8 instruction
+ */
+#define BITSCRAMBLER_RX_INST_IDX    0x00000007U
+#define BITSCRAMBLER_RX_INST_IDX_M  (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S)
+#define BITSCRAMBLER_RX_INST_IDX_V  0x00000007U
+#define BITSCRAMBLER_RX_INST_IDX_S  0
+/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0;
+ *  write this bits to specify the bit position of 257 bit instruction which in units
+ *  of 32 bits
+ */
+#define BITSCRAMBLER_RX_INST_POS    0x0000000FU
+#define BITSCRAMBLER_RX_INST_POS_M  (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S)
+#define BITSCRAMBLER_RX_INST_POS_V  0x0000000FU
+#define BITSCRAMBLER_RX_INST_POS_S  3
+
+/** BITSCRAMBLER_RX_INST_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc)
+/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12;
+ *  write this bits to update instruction which specified by
+ *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
+ *  BITSCRAMBLER_RX_INST_CFG0_REG
+ */
+#define BITSCRAMBLER_RX_INST    0xFFFFFFFFU
+#define BITSCRAMBLER_RX_INST_M  (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S)
+#define BITSCRAMBLER_RX_INST_V  0xFFFFFFFFU
+#define BITSCRAMBLER_RX_INST_S  0
+
+/** BITSCRAMBLER_TX_LUT_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10)
+/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
+ *  write this bits to specify the bytes position of LUT RAM based on
+ *  reg_bitscrambler_tx_lut_mode
+ */
+#define BITSCRAMBLER_TX_LUT_IDX    0x000007FFU
+#define BITSCRAMBLER_TX_LUT_IDX_M  (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S)
+#define BITSCRAMBLER_TX_LUT_IDX_V  0x000007FFU
+#define BITSCRAMBLER_TX_LUT_IDX_S  0
+/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+ *  bytes
+ */
+#define BITSCRAMBLER_TX_LUT_MODE    0x00000003U
+#define BITSCRAMBLER_TX_LUT_MODE_M  (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S)
+#define BITSCRAMBLER_TX_LUT_MODE_V  0x00000003U
+#define BITSCRAMBLER_TX_LUT_MODE_S  11
+
+/** BITSCRAMBLER_TX_LUT_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14)
+/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20;
+ *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
+ *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
+ */
+#define BITSCRAMBLER_TX_LUT    0xFFFFFFFFU
+#define BITSCRAMBLER_TX_LUT_M  (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S)
+#define BITSCRAMBLER_TX_LUT_V  0xFFFFFFFFU
+#define BITSCRAMBLER_TX_LUT_S  0
+
+/** BITSCRAMBLER_RX_LUT_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18)
+/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
+ *  write this bits to specify the bytes position of LUT RAM based on
+ *  reg_bitscrambler_rx_lut_mode
+ */
+#define BITSCRAMBLER_RX_LUT_IDX    0x000007FFU
+#define BITSCRAMBLER_RX_LUT_IDX_M  (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S)
+#define BITSCRAMBLER_RX_LUT_IDX_V  0x000007FFU
+#define BITSCRAMBLER_RX_LUT_IDX_S  0
+/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+ *  bytes
+ */
+#define BITSCRAMBLER_RX_LUT_MODE    0x00000003U
+#define BITSCRAMBLER_RX_LUT_MODE_M  (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S)
+#define BITSCRAMBLER_RX_LUT_MODE_V  0x00000003U
+#define BITSCRAMBLER_RX_LUT_MODE_S  11
+
+/** BITSCRAMBLER_RX_LUT_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c)
+/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28;
+ *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
+ *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
+ */
+#define BITSCRAMBLER_RX_LUT    0xFFFFFFFFU
+#define BITSCRAMBLER_RX_LUT_M  (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S)
+#define BITSCRAMBLER_RX_LUT_V  0xFFFFFFFFU
+#define BITSCRAMBLER_RX_LUT_S  0
+
+/** BITSCRAMBLER_TX_TAILING_BITS_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20)
+/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
+ *  write this bits to specify the extra data bit length after getting EOF
+ */
+#define BITSCRAMBLER_TX_TAILING_BITS    0x0000FFFFU
+#define BITSCRAMBLER_TX_TAILING_BITS_M  (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S)
+#define BITSCRAMBLER_TX_TAILING_BITS_V  0x0000FFFFU
+#define BITSCRAMBLER_TX_TAILING_BITS_S  0
+
+/** BITSCRAMBLER_RX_TAILING_BITS_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24)
+/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
+ *  write this bits to specify the extra data bit length after getting EOF
+ */
+#define BITSCRAMBLER_RX_TAILING_BITS    0x0000FFFFU
+#define BITSCRAMBLER_RX_TAILING_BITS_M  (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S)
+#define BITSCRAMBLER_RX_TAILING_BITS_V  0x0000FFFFU
+#define BITSCRAMBLER_RX_TAILING_BITS_S  0
+
+/** BITSCRAMBLER_TX_CTRL_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28)
+/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0;
+ *  write this bit to enable the bitscrambler tx
+ */
+#define BITSCRAMBLER_TX_ENA    (BIT(0))
+#define BITSCRAMBLER_TX_ENA_M  (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S)
+#define BITSCRAMBLER_TX_ENA_V  0x00000001U
+#define BITSCRAMBLER_TX_ENA_S  0
+/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0;
+ *  write this bit to pause the bitscrambler tx core
+ */
+#define BITSCRAMBLER_TX_PAUSE    (BIT(1))
+#define BITSCRAMBLER_TX_PAUSE_M  (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S)
+#define BITSCRAMBLER_TX_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_TX_PAUSE_S  1
+/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1;
+ *  write this bit to halt the bitscrambler tx core
+ */
+#define BITSCRAMBLER_TX_HALT    (BIT(2))
+#define BITSCRAMBLER_TX_HALT_M  (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S)
+#define BITSCRAMBLER_TX_HALT_V  0x00000001U
+#define BITSCRAMBLER_TX_HALT_S  2
+/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0;
+ *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+ *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
+ *  counter by write peripheral buffer
+ */
+#define BITSCRAMBLER_TX_EOF_MODE    (BIT(3))
+#define BITSCRAMBLER_TX_EOF_MODE_M  (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S)
+#define BITSCRAMBLER_TX_EOF_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_EOF_MODE_S  3
+/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0;
+ *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+ *  core, 0: use the little than operator to get the condition, 1: use not equal
+ *  operator to get the condition
+ */
+#define BITSCRAMBLER_TX_COND_MODE    (BIT(4))
+#define BITSCRAMBLER_TX_COND_MODE_M  (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S)
+#define BITSCRAMBLER_TX_COND_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_COND_MODE_S  4
+/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
+ *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+ *  by reset, 1: fetch by instructions
+ */
+#define BITSCRAMBLER_TX_FETCH_MODE    (BIT(5))
+#define BITSCRAMBLER_TX_FETCH_MODE_M  (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
+#define BITSCRAMBLER_TX_FETCH_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_FETCH_MODE_S  5
+/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0;
+ *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
+ *  wait write data back done, , 1: ignore write data back
+ */
+#define BITSCRAMBLER_TX_HALT_MODE    (BIT(6))
+#define BITSCRAMBLER_TX_HALT_MODE_M  (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S)
+#define BITSCRAMBLER_TX_HALT_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_HALT_MODE_S  6
+/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
+ *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+ *  wait read data, 1: ignore read data
+ */
+#define BITSCRAMBLER_TX_RD_DUMMY    (BIT(7))
+#define BITSCRAMBLER_TX_RD_DUMMY_M  (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S)
+#define BITSCRAMBLER_TX_RD_DUMMY_V  0x00000001U
+#define BITSCRAMBLER_TX_RD_DUMMY_S  7
+/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0;
+ *  write this bit to reset the bitscrambler tx fifo
+ */
+#define BITSCRAMBLER_TX_FIFO_RST    (BIT(8))
+#define BITSCRAMBLER_TX_FIFO_RST_M  (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S)
+#define BITSCRAMBLER_TX_FIFO_RST_V  0x00000001U
+#define BITSCRAMBLER_TX_FIFO_RST_S  8
+
+/** BITSCRAMBLER_RX_CTRL_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c)
+/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0;
+ *  write this bit to enable the bitscrambler rx
+ */
+#define BITSCRAMBLER_RX_ENA    (BIT(0))
+#define BITSCRAMBLER_RX_ENA_M  (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S)
+#define BITSCRAMBLER_RX_ENA_V  0x00000001U
+#define BITSCRAMBLER_RX_ENA_S  0
+/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0;
+ *  write this bit to pause the bitscrambler rx core
+ */
+#define BITSCRAMBLER_RX_PAUSE    (BIT(1))
+#define BITSCRAMBLER_RX_PAUSE_M  (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S)
+#define BITSCRAMBLER_RX_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_RX_PAUSE_S  1
+/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1;
+ *  write this bit to halt the bitscrambler rx core
+ */
+#define BITSCRAMBLER_RX_HALT    (BIT(2))
+#define BITSCRAMBLER_RX_HALT_M  (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S)
+#define BITSCRAMBLER_RX_HALT_V  0x00000001U
+#define BITSCRAMBLER_RX_HALT_S  2
+/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0;
+ *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
+ *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
+ *  buffer, 0 counter by write dma fifo
+ */
+#define BITSCRAMBLER_RX_EOF_MODE    (BIT(3))
+#define BITSCRAMBLER_RX_EOF_MODE_M  (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S)
+#define BITSCRAMBLER_RX_EOF_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_EOF_MODE_S  3
+/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0;
+ *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
+ *  core, 0: use the little than operator to get the condition, 1: use not equal
+ *  operator to get the condition
+ */
+#define BITSCRAMBLER_RX_COND_MODE    (BIT(4))
+#define BITSCRAMBLER_RX_COND_MODE_M  (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S)
+#define BITSCRAMBLER_RX_COND_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_COND_MODE_S  4
+/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
+ *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
+ *  by reset, 1: fetch by instructions
+ */
+#define BITSCRAMBLER_RX_FETCH_MODE    (BIT(5))
+#define BITSCRAMBLER_RX_FETCH_MODE_M  (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
+#define BITSCRAMBLER_RX_FETCH_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_FETCH_MODE_S  5
+/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0;
+ *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
+ *  wait write data back done, , 1: ignore write data back
+ */
+#define BITSCRAMBLER_RX_HALT_MODE    (BIT(6))
+#define BITSCRAMBLER_RX_HALT_MODE_M  (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S)
+#define BITSCRAMBLER_RX_HALT_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_HALT_MODE_S  6
+/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
+ *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
+ *  wait read data, 1: ignore read data
+ */
+#define BITSCRAMBLER_RX_RD_DUMMY    (BIT(7))
+#define BITSCRAMBLER_RX_RD_DUMMY_M  (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S)
+#define BITSCRAMBLER_RX_RD_DUMMY_V  0x00000001U
+#define BITSCRAMBLER_RX_RD_DUMMY_S  7
+/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0;
+ *  write this bit to reset the bitscrambler rx fifo
+ */
+#define BITSCRAMBLER_RX_FIFO_RST    (BIT(8))
+#define BITSCRAMBLER_RX_FIFO_RST_M  (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S)
+#define BITSCRAMBLER_RX_FIFO_RST_V  0x00000001U
+#define BITSCRAMBLER_RX_FIFO_RST_S  8
+
+/** BITSCRAMBLER_TX_STATE_REG register
+ *  Status registers
+ */
+#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30)
+/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1;
+ *  represents the bitscrambler tx core in halt mode
+ */
+#define BITSCRAMBLER_TX_IN_IDLE    (BIT(0))
+#define BITSCRAMBLER_TX_IN_IDLE_M  (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S)
+#define BITSCRAMBLER_TX_IN_IDLE_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_IDLE_S  0
+/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0;
+ *  represents the bitscrambler tx core in run mode
+ */
+#define BITSCRAMBLER_TX_IN_RUN    (BIT(1))
+#define BITSCRAMBLER_TX_IN_RUN_M  (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S)
+#define BITSCRAMBLER_TX_IN_RUN_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_RUN_S  1
+/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0;
+ *  represents the bitscrambler tx core in wait mode to wait write back done
+ */
+#define BITSCRAMBLER_TX_IN_WAIT    (BIT(2))
+#define BITSCRAMBLER_TX_IN_WAIT_M  (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S)
+#define BITSCRAMBLER_TX_IN_WAIT_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_WAIT_S  2
+/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0;
+ *  represents the bitscrambler tx core in pause mode
+ */
+#define BITSCRAMBLER_TX_IN_PAUSE    (BIT(3))
+#define BITSCRAMBLER_TX_IN_PAUSE_M  (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S)
+#define BITSCRAMBLER_TX_IN_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_PAUSE_S  3
+/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 0;
+ *  represents the bitscrambler tx fifo in empty state
+ */
+#define BITSCRAMBLER_TX_FIFO_EMPTY    (BIT(4))
+#define BITSCRAMBLER_TX_FIFO_EMPTY_M  (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S)
+#define BITSCRAMBLER_TX_FIFO_EMPTY_V  0x00000001U
+#define BITSCRAMBLER_TX_FIFO_EMPTY_S  4
+/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
+ *  represents the bytes numbers of bitscrambler tx core when get EOF
+ */
+#define BITSCRAMBLER_TX_EOF_GET_CNT    0x00003FFFU
+#define BITSCRAMBLER_TX_EOF_GET_CNT_M  (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S)
+#define BITSCRAMBLER_TX_EOF_GET_CNT_V  0x00003FFFU
+#define BITSCRAMBLER_TX_EOF_GET_CNT_S  16
+/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
+ *  represents the some EOFs will be lost for bitscrambler tx core
+ */
+#define BITSCRAMBLER_TX_EOF_OVERLOAD    (BIT(30))
+#define BITSCRAMBLER_TX_EOF_OVERLOAD_M  (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S)
+#define BITSCRAMBLER_TX_EOF_OVERLOAD_V  0x00000001U
+#define BITSCRAMBLER_TX_EOF_OVERLOAD_S  30
+/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
+ *  write this bit to clear reg_bitscrambler_tx_eof_overload and
+ *  reg_bitscrambler_tx_eof_get_cnt registers
+ */
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR    (BIT(31))
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M  (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S)
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V  0x00000001U
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S  31
+
+/** BITSCRAMBLER_RX_STATE_REG register
+ *  Status registers
+ */
+#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34)
+/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1;
+ *  represents the bitscrambler rx core in halt mode
+ */
+#define BITSCRAMBLER_RX_IN_IDLE    (BIT(0))
+#define BITSCRAMBLER_RX_IN_IDLE_M  (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S)
+#define BITSCRAMBLER_RX_IN_IDLE_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_IDLE_S  0
+/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0;
+ *  represents the bitscrambler rx core in run mode
+ */
+#define BITSCRAMBLER_RX_IN_RUN    (BIT(1))
+#define BITSCRAMBLER_RX_IN_RUN_M  (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S)
+#define BITSCRAMBLER_RX_IN_RUN_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_RUN_S  1
+/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0;
+ *  represents the bitscrambler rx core in wait mode to wait write back done
+ */
+#define BITSCRAMBLER_RX_IN_WAIT    (BIT(2))
+#define BITSCRAMBLER_RX_IN_WAIT_M  (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S)
+#define BITSCRAMBLER_RX_IN_WAIT_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_WAIT_S  2
+/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0;
+ *  represents the bitscrambler rx core in pause mode
+ */
+#define BITSCRAMBLER_RX_IN_PAUSE    (BIT(3))
+#define BITSCRAMBLER_RX_IN_PAUSE_M  (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S)
+#define BITSCRAMBLER_RX_IN_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_PAUSE_S  3
+/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0;
+ *  represents the bitscrambler rx fifo in full state
+ */
+#define BITSCRAMBLER_RX_FIFO_FULL    (BIT(4))
+#define BITSCRAMBLER_RX_FIFO_FULL_M  (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S)
+#define BITSCRAMBLER_RX_FIFO_FULL_V  0x00000001U
+#define BITSCRAMBLER_RX_FIFO_FULL_S  4
+/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
+ *  represents the bytes numbers of bitscrambler rx core when get EOF
+ */
+#define BITSCRAMBLER_RX_EOF_GET_CNT    0x00003FFFU
+#define BITSCRAMBLER_RX_EOF_GET_CNT_M  (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S)
+#define BITSCRAMBLER_RX_EOF_GET_CNT_V  0x00003FFFU
+#define BITSCRAMBLER_RX_EOF_GET_CNT_S  16
+/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
+ *  represents the some EOFs will be lost for bitscrambler rx core
+ */
+#define BITSCRAMBLER_RX_EOF_OVERLOAD    (BIT(30))
+#define BITSCRAMBLER_RX_EOF_OVERLOAD_M  (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S)
+#define BITSCRAMBLER_RX_EOF_OVERLOAD_V  0x00000001U
+#define BITSCRAMBLER_RX_EOF_OVERLOAD_S  30
+/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
+ *  write this bit to clear reg_bitscrambler_rx_eof_overload and
+ *  reg_bitscrambler_rx_eof_get_cnt registers
+ */
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR    (BIT(31))
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M  (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S)
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V  0x00000001U
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S  31
+
+/** BITSCRAMBLER_SYS_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8)
+/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0;
+ *  write this bit to set the bitscrambler tx loop back to DMA rx
+ */
+#define BITSCRAMBLER_LOOP_MODE    (BIT(0))
+#define BITSCRAMBLER_LOOP_MODE_M  (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S)
+#define BITSCRAMBLER_LOOP_MODE_V  0x00000001U
+#define BITSCRAMBLER_LOOP_MODE_S  0
+/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define BITSCRAMBLER_CLK_EN    (BIT(31))
+#define BITSCRAMBLER_CLK_EN_M  (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S)
+#define BITSCRAMBLER_CLK_EN_V  0x00000001U
+#define BITSCRAMBLER_CLK_EN_S  31
+
+/** BITSCRAMBLER_VERSION_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc)
+/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 36713024;
+ *  Reserved
+ */
+#define BITSCRAMBLER_BITSCRAMBLER_VER    0x0FFFFFFFU
+#define BITSCRAMBLER_BITSCRAMBLER_VER_M  (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S)
+#define BITSCRAMBLER_BITSCRAMBLER_VER_V  0x0FFFFFFFU
+#define BITSCRAMBLER_BITSCRAMBLER_VER_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_struct.h
new file mode 100644
index 0000000000..4701ecccf0
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_struct.h
@@ -0,0 +1,612 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of tx_inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t tx_inst_idx:3;
+        /** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t tx_inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_tx_inst_cfg0_reg_t;
+
+/** Type of tx_inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_inst : R/W; bitpos: [31:0]; default: 4;
+         *  write this bits to update instruction which specified by
+         *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
+         *  BITSCRAMBLER_TX_INST_CFG0_REG
+         */
+        uint32_t tx_inst:32;
+    };
+    uint32_t val;
+} bitscrambler_tx_inst_cfg1_reg_t;
+
+/** Type of rx_inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t rx_inst_idx:3;
+        /** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t rx_inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_rx_inst_cfg0_reg_t;
+
+/** Type of rx_inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_inst : R/W; bitpos: [31:0]; default: 12;
+         *  write this bits to update instruction which specified by
+         *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
+         *  BITSCRAMBLER_RX_INST_CFG0_REG
+         */
+        uint32_t rx_inst:32;
+    };
+    uint32_t val;
+} bitscrambler_rx_inst_cfg1_reg_t;
+
+/** Type of tx_lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on
+         *  reg_bitscrambler_tx_lut_mode
+         */
+        uint32_t tx_lut_idx:11;
+        /** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t tx_lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_tx_lut_cfg0_reg_t;
+
+/** Type of tx_lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_lut : R/W; bitpos: [31:0]; default: 20;
+         *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
+         *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
+         */
+        uint32_t tx_lut:32;
+    };
+    uint32_t val;
+} bitscrambler_tx_lut_cfg1_reg_t;
+
+/** Type of rx_lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on
+         *  reg_bitscrambler_rx_lut_mode
+         */
+        uint32_t rx_lut_idx:11;
+        /** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t rx_lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_rx_lut_cfg0_reg_t;
+
+/** Type of rx_lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_lut : R/W; bitpos: [31:0]; default: 28;
+         *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
+         *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
+         */
+        uint32_t rx_lut:32;
+    };
+    uint32_t val;
+} bitscrambler_rx_lut_cfg1_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of tx_tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t tx_tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_tx_tailing_bits_reg_t;
+
+/** Type of rx_tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t rx_tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_rx_tailing_bits_reg_t;
+
+/** Type of tx_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler tx
+         */
+        uint32_t tx_ena:1;
+        /** tx_pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler tx core
+         */
+        uint32_t tx_pause:1;
+        /** tx_halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler tx core
+         */
+        uint32_t tx_halt:1;
+        /** tx_eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
+         *  counter by write peripheral buffer
+         */
+        uint32_t tx_eof_mode:1;
+        /** tx_cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t tx_cond_mode:1;
+        /** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t tx_fetch_mode:1;
+        /** tx_halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t tx_halt_mode:1;
+        /** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t tx_rd_dummy:1;
+        /** tx_fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler tx fifo
+         */
+        uint32_t tx_fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_tx_ctrl_reg_t;
+
+/** Type of rx_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler rx
+         */
+        uint32_t rx_ena:1;
+        /** rx_pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler rx core
+         */
+        uint32_t rx_pause:1;
+        /** rx_halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler rx core
+         */
+        uint32_t rx_halt:1;
+        /** rx_eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
+         *  buffer, 0 counter by write dma fifo
+         */
+        uint32_t rx_eof_mode:1;
+        /** rx_cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t rx_cond_mode:1;
+        /** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t rx_fetch_mode:1;
+        /** rx_halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t rx_halt_mode:1;
+        /** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t rx_rd_dummy:1;
+        /** rx_fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler rx fifo
+         */
+        uint32_t rx_fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_rx_ctrl_reg_t;
+
+/** Type of sys register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** loop_mode : R/W; bitpos: [0]; default: 0;
+         *  write this bit to set the bitscrambler tx loop back to DMA rx
+         */
+        uint32_t loop_mode:1;
+        uint32_t reserved_1:30;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} bitscrambler_sys_reg_t;
+
+
+/** Group: Status registers */
+/** Type of tx_state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** tx_in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler tx core in halt mode
+         */
+        uint32_t tx_in_idle:1;
+        /** tx_in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler tx core in run mode
+         */
+        uint32_t tx_in_run:1;
+        /** tx_in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler tx core in wait mode to wait write back done
+         */
+        uint32_t tx_in_wait:1;
+        /** tx_in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler tx core in pause mode
+         */
+        uint32_t tx_in_pause:1;
+        /** tx_fifo_empty : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler tx fifo in empty state
+         */
+        uint32_t tx_fifo_empty:1;
+        uint32_t reserved_5:11;
+        /** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler tx core when get EOF
+         */
+        uint32_t tx_eof_get_cnt:14;
+        /** tx_eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler tx core
+         */
+        uint32_t tx_eof_overload:1;
+        /** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_tx_eof_overload and
+         *  reg_bitscrambler_tx_eof_get_cnt registers
+         */
+        uint32_t tx_eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_tx_state_reg_t;
+
+/** Type of rx_state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** rx_in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler rx core in halt mode
+         */
+        uint32_t rx_in_idle:1;
+        /** rx_in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler rx core in run mode
+         */
+        uint32_t rx_in_run:1;
+        /** rx_in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler rx core in wait mode to wait write back done
+         */
+        uint32_t rx_in_wait:1;
+        /** rx_in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler rx core in pause mode
+         */
+        uint32_t rx_in_pause:1;
+        /** rx_fifo_full : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler rx fifo in full state
+         */
+        uint32_t rx_fifo_full:1;
+        uint32_t reserved_5:11;
+        /** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler rx core when get EOF
+         */
+        uint32_t rx_eof_get_cnt:14;
+        /** rx_eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler rx core
+         */
+        uint32_t rx_eof_overload:1;
+        /** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_rx_eof_overload and
+         *  reg_bitscrambler_rx_eof_get_cnt registers
+         */
+        uint32_t rx_eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_rx_state_reg_t;
+
+
+/** Group: Version register */
+/** Type of version register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
+         *  Reserved
+         */
+        uint32_t bitscrambler_ver:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} bitscrambler_version_reg_t;
+
+///////////////////// TX and RX registers are exactly the same //////////////////////////////////
+// The following registers are used for both TX and RX, so we can use the same struct for both //
+/////////////////////////////////////////////////////////////////////////////////////////////////
+
+/** Type of inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t inst_idx:3;
+        /** inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_inst_cfg0_reg_t;
+
+/** Type of inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** inst : R/W; bitpos: [31:0]; default: 4;
+         *  write this bits to update instruction, Read this bits to get instruction.
+         */
+        uint32_t inst:32;
+    };
+    uint32_t val;
+} bitscrambler_inst_cfg1_reg_t;
+
+/** Type of lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on lut_mode
+         */
+        uint32_t lut_idx:11;
+        /** lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_lut_cfg0_reg_t;
+
+/** Type of lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** lut : R/W; bitpos: [31:0]; default: 20;
+         *  write this bits to update LUT, Read this bits to get LUT
+         */
+        uint32_t lut:32;
+    };
+    uint32_t val;
+} bitscrambler_lut_cfg1_reg_t;
+
+/** Type of tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_tailing_bits_reg_t;
+
+/** Type of ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler tx
+         */
+        uint32_t ena:1;
+        /** pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler tx core
+         */
+        uint32_t pause:1;
+        /** halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler tx core
+         */
+        uint32_t halt:1;
+        /** eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_tailing_bits, 0: counter by read dma fifo, 0
+         *  counter by write peripheral buffer
+         */
+        uint32_t eof_mode:1;
+        /** cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t cond_mode:1;
+        /** fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t fetch_mode:1;
+        /** halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler tx core halt mode when halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t halt_mode:1;
+        /** rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t rd_dummy:1;
+        /** fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler tx fifo
+         */
+        uint32_t fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_ctrl_reg_t;
+
+/** Group: Status registers */
+/** Type of state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler tx core in halt mode
+         */
+        uint32_t in_idle:1;
+        /** in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler tx core in run mode
+         */
+        uint32_t in_run:1;
+        /** in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler tx core in wait mode to wait write back done
+         */
+        uint32_t in_wait:1;
+        /** in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler tx core in pause mode
+         */
+        uint32_t in_pause:1;
+        /** fifo_empty : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler tx fifo in empty state
+         */
+        uint32_t fifo_empty:1;
+        uint32_t reserved_5:11;
+        /** eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler tx core when get EOF
+         */
+        uint32_t eof_get_cnt:14;
+        /** eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler tx core
+         */
+        uint32_t eof_overload:1;
+        /** eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_eof_overload and
+         *  reg_bitscrambler_eof_get_cnt registers
+         */
+        uint32_t eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_state_reg_t;
+
+typedef struct {
+    volatile struct {
+        bitscrambler_inst_cfg0_reg_t cfg0;
+        bitscrambler_inst_cfg1_reg_t cfg1;
+    } inst_cfg[2];
+    volatile struct {
+        bitscrambler_lut_cfg0_reg_t cfg0;
+        bitscrambler_lut_cfg1_reg_t cfg1;
+    } lut_cfg[2];
+    volatile bitscrambler_tailing_bits_reg_t tail_bits[2];
+    volatile bitscrambler_ctrl_reg_t ctrl[2];
+    volatile bitscrambler_state_reg_t state[2];
+    uint32_t reserved_038[48];
+    volatile bitscrambler_sys_reg_t sys;
+    volatile bitscrambler_version_reg_t version;
+} bitscrambler_dev_t;
+
+extern bitscrambler_dev_t BITSCRAMBLER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/cache_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/cache_reg.h
new file mode 100644
index 0000000000..a99a74bbcb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/cache_reg.h
@@ -0,0 +1,6343 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CACHE_L1_ICACHE_CTRL_REG register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0)
+/** CACHE_L1_ICACHE_SHUT_IBUS0 : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS0    (BIT(0))
+#define CACHE_L1_ICACHE_SHUT_IBUS0_M  (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS0_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS0_S  0
+/** CACHE_L1_ICACHE_SHUT_IBUS1 : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS1    (BIT(1))
+#define CACHE_L1_ICACHE_SHUT_IBUS1_M  (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS1_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS1_S  1
+/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS2    (BIT(2))
+#define CACHE_L1_ICACHE_SHUT_IBUS2_M  (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS2_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS2_S  2
+/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS3    (BIT(3))
+#define CACHE_L1_ICACHE_SHUT_IBUS3_M  (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS3_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS3_S  3
+
+/** CACHE_L1_DCACHE_CTRL_REG register
+ *  L1 data Cache(L1-DCache) control register
+ */
+#define CACHE_L1_DCACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
+/** CACHE_L1_DCACHE_SHUT_DBUS0 : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS0    (BIT(0))
+#define CACHE_L1_DCACHE_SHUT_DBUS0_M  (CACHE_L1_DCACHE_SHUT_DBUS0_V << CACHE_L1_DCACHE_SHUT_DBUS0_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS0_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS0_S  0
+/** CACHE_L1_DCACHE_SHUT_DBUS1 : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS1    (BIT(1))
+#define CACHE_L1_DCACHE_SHUT_DBUS1_M  (CACHE_L1_DCACHE_SHUT_DBUS1_V << CACHE_L1_DCACHE_SHUT_DBUS1_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS1_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS1_S  1
+/** CACHE_L1_DCACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS2    (BIT(2))
+#define CACHE_L1_DCACHE_SHUT_DBUS2_M  (CACHE_L1_DCACHE_SHUT_DBUS2_V << CACHE_L1_DCACHE_SHUT_DBUS2_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS2_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS2_S  2
+/** CACHE_L1_DCACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS3    (BIT(3))
+#define CACHE_L1_DCACHE_SHUT_DBUS3_M  (CACHE_L1_DCACHE_SHUT_DBUS3_V << CACHE_L1_DCACHE_SHUT_DBUS3_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS3_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS3_S  3
+/** CACHE_L1_DCACHE_SHUT_DMA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L1_DCACHE_SHUT_DMA_M  (CACHE_L1_DCACHE_SHUT_DMA_V << CACHE_L1_DCACHE_SHUT_DMA_S)
+#define CACHE_L1_DCACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DMA_S  4
+
+/** CACHE_L1_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8)
+/** CACHE_BYPASS_L1_ICACHE0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_ICACHE0_EN    (BIT(0))
+#define CACHE_BYPASS_L1_ICACHE0_EN_M  (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S)
+#define CACHE_BYPASS_L1_ICACHE0_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE0_EN_S  0
+/** CACHE_BYPASS_L1_ICACHE1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_ICACHE1_EN    (BIT(1))
+#define CACHE_BYPASS_L1_ICACHE1_EN_M  (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S)
+#define CACHE_BYPASS_L1_ICACHE1_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE1_EN_S  1
+/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_BYPASS_L1_ICACHE2_EN    (BIT(2))
+#define CACHE_BYPASS_L1_ICACHE2_EN_M  (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S)
+#define CACHE_BYPASS_L1_ICACHE2_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE2_EN_S  2
+/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_BYPASS_L1_ICACHE3_EN    (BIT(3))
+#define CACHE_BYPASS_L1_ICACHE3_EN_M  (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S)
+#define CACHE_BYPASS_L1_ICACHE3_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE3_EN_S  3
+/** CACHE_BYPASS_L1_DCACHE_EN : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_DCACHE_EN    (BIT(4))
+#define CACHE_BYPASS_L1_DCACHE_EN_M  (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S)
+#define CACHE_BYPASS_L1_DCACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_DCACHE_EN_S  4
+
+/** CACHE_L1_CACHE_ATOMIC_CONF_REG register
+ *  L1 Cache atomic feature configure register
+ */
+#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc)
+/** CACHE_L1_DCACHE_ATOMIC_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable atomic feature on L1-DCache when multiple cores access
+ *  L1-DCache.  1: disable, 1: enable.
+ */
+#define CACHE_L1_DCACHE_ATOMIC_EN    (BIT(0))
+#define CACHE_L1_DCACHE_ATOMIC_EN_M  (CACHE_L1_DCACHE_ATOMIC_EN_V << CACHE_L1_DCACHE_ATOMIC_EN_S)
+#define CACHE_L1_DCACHE_ATOMIC_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_ATOMIC_EN_S  0
+
+/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10)
+/** CACHE_L1_ICACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_ICACHE_CACHESIZE_256_M  (CACHE_L1_ICACHE_CACHESIZE_256_V << CACHE_L1_ICACHE_CACHESIZE_256_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256_S  0
+/** CACHE_L1_ICACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_ICACHE_CACHESIZE_512_M  (CACHE_L1_ICACHE_CACHESIZE_512_V << CACHE_L1_ICACHE_CACHESIZE_512_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512_S  1
+/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_ICACHE_CACHESIZE_1K_M  (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_ICACHE_CACHESIZE_2K_M  (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_ICACHE_CACHESIZE_4K_M  (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_ICACHE_CACHESIZE_8K_M  (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 1;
+ *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_ICACHE_CACHESIZE_16K_M  (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_ICACHE_CACHESIZE_32K_M  (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_ICACHE_CACHESIZE_64K_M  (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_ICACHE_CACHESIZE_128K_M  (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_ICACHE_CACHESIZE_256K_M  (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_ICACHE_CACHESIZE_512K_M  (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_M  (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14)
+/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_M  (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_M  (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_M  (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_M  (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_M  (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_M  (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_DCACHE_CACHESIZE_CONF_REG register
+ *  L1 data Cache CacheSize mode configure register
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18)
+/** CACHE_L1_DCACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_DCACHE_CACHESIZE_256_M  (CACHE_L1_DCACHE_CACHESIZE_256_V << CACHE_L1_DCACHE_CACHESIZE_256_S)
+#define CACHE_L1_DCACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_256_S  0
+/** CACHE_L1_DCACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_DCACHE_CACHESIZE_512_M  (CACHE_L1_DCACHE_CACHESIZE_512_V << CACHE_L1_DCACHE_CACHESIZE_512_S)
+#define CACHE_L1_DCACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_512_S  1
+/** CACHE_L1_DCACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_DCACHE_CACHESIZE_1K_M  (CACHE_L1_DCACHE_CACHESIZE_1K_V << CACHE_L1_DCACHE_CACHESIZE_1K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_DCACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_DCACHE_CACHESIZE_2K_M  (CACHE_L1_DCACHE_CACHESIZE_2K_V << CACHE_L1_DCACHE_CACHESIZE_2K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_DCACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_DCACHE_CACHESIZE_4K_M  (CACHE_L1_DCACHE_CACHESIZE_4K_V << CACHE_L1_DCACHE_CACHESIZE_4K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_DCACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_DCACHE_CACHESIZE_8K_M  (CACHE_L1_DCACHE_CACHESIZE_8K_V << CACHE_L1_DCACHE_CACHESIZE_8K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_DCACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_DCACHE_CACHESIZE_16K_M  (CACHE_L1_DCACHE_CACHESIZE_16K_V << CACHE_L1_DCACHE_CACHESIZE_16K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_DCACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_DCACHE_CACHESIZE_32K_M  (CACHE_L1_DCACHE_CACHESIZE_32K_V << CACHE_L1_DCACHE_CACHESIZE_32K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_DCACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 1;
+ *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_DCACHE_CACHESIZE_64K_M  (CACHE_L1_DCACHE_CACHESIZE_64K_V << CACHE_L1_DCACHE_CACHESIZE_64K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_DCACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_DCACHE_CACHESIZE_128K_M  (CACHE_L1_DCACHE_CACHESIZE_128K_V << CACHE_L1_DCACHE_CACHESIZE_128K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_DCACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_DCACHE_CACHESIZE_256K_M  (CACHE_L1_DCACHE_CACHESIZE_256K_V << CACHE_L1_DCACHE_CACHESIZE_256K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_DCACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_DCACHE_CACHESIZE_512K_M  (CACHE_L1_DCACHE_CACHESIZE_512K_V << CACHE_L1_DCACHE_CACHESIZE_512K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_DCACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_M  (CACHE_L1_DCACHE_CACHESIZE_1024K_V << CACHE_L1_DCACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_DCACHE_BLOCKSIZE_CONF_REG register
+ *  L1 data Cache BlockSize mode configure register
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c)
+/** CACHE_L1_DCACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_M  (CACHE_L1_DCACHE_BLOCKSIZE_8_V << CACHE_L1_DCACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_DCACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_M  (CACHE_L1_DCACHE_BLOCKSIZE_16_V << CACHE_L1_DCACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_DCACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_M  (CACHE_L1_DCACHE_BLOCKSIZE_32_V << CACHE_L1_DCACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_DCACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_M  (CACHE_L1_DCACHE_BLOCKSIZE_64_V << CACHE_L1_DCACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_DCACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_M  (CACHE_L1_DCACHE_BLOCKSIZE_128_V << CACHE_L1_DCACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_DCACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_M  (CACHE_L1_DCACHE_BLOCKSIZE_256_V << CACHE_L1_DCACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20)
+/** CACHE_L1_ICACHE0_WRAP : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+ */
+#define CACHE_L1_ICACHE0_WRAP    (BIT(0))
+#define CACHE_L1_ICACHE0_WRAP_M  (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S)
+#define CACHE_L1_ICACHE0_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE0_WRAP_S  0
+/** CACHE_L1_ICACHE1_WRAP : R/W; bitpos: [1]; default: 0;
+ *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+ */
+#define CACHE_L1_ICACHE1_WRAP    (BIT(1))
+#define CACHE_L1_ICACHE1_WRAP_M  (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S)
+#define CACHE_L1_ICACHE1_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE1_WRAP_S  1
+/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_WRAP    (BIT(2))
+#define CACHE_L1_ICACHE2_WRAP_M  (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S)
+#define CACHE_L1_ICACHE2_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE2_WRAP_S  2
+/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_WRAP    (BIT(3))
+#define CACHE_L1_ICACHE3_WRAP_M  (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S)
+#define CACHE_L1_ICACHE3_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE3_WRAP_S  3
+/** CACHE_L1_DCACHE_WRAP : R/W; bitpos: [4]; default: 0;
+ *  Set this bit as 1 to enable L1-DCache wrap around mode.
+ */
+#define CACHE_L1_DCACHE_WRAP    (BIT(4))
+#define CACHE_L1_DCACHE_WRAP_M  (CACHE_L1_DCACHE_WRAP_V << CACHE_L1_DCACHE_WRAP_S)
+#define CACHE_L1_DCACHE_WRAP_V  0x00000001U
+#define CACHE_L1_DCACHE_WRAP_S  4
+
+/** CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG register
+ *  Cache tag memory power control register
+ */
+#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24)
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S  0
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD    (BIT(1))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S  1
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU    (BIT(2))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S  2
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON    (BIT(4))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S  4
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD    (BIT(5))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S  5
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU : R/W; bitpos: [6]; default: 1;
+ *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU    (BIT(6))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S  6
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON    (BIT(8))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S  8
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD    (BIT(9))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S  9
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU    (BIT(10))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S  10
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON    (BIT(12))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S  12
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD    (BIT(13))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S  13
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU    (BIT(14))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S  14
+/** CACHE_L1_DCACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to close clock gating of  L1-DCache tag memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON    (BIT(16))
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_S  16
+/** CACHE_L1_DCACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD    (BIT(17))
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_S  17
+/** CACHE_L1_DCACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU    (BIT(18))
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_S  18
+
+/** CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG register
+ *  Cache data memory power control register
+ */
+#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28)
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON    (BIT(0))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S  0
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD    (BIT(1))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S  1
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU    (BIT(2))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S  2
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON    (BIT(4))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S  4
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD    (BIT(5))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S  5
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU : R/W; bitpos: [6]; default: 1;
+ *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU    (BIT(6))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S  6
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON    (BIT(8))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S  8
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD    (BIT(9))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S  9
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU    (BIT(10))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S  10
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON    (BIT(12))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S  12
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD    (BIT(13))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S  13
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU    (BIT(14))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S  14
+/** CACHE_L1_DCACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to close clock gating of  L1-DCache data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON    (BIT(16))
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_S  16
+/** CACHE_L1_DCACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD    (BIT(17))
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_S  17
+/** CACHE_L1_DCACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU    (BIT(18))
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_S  18
+
+/** CACHE_L1_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2c)
+/** CACHE_L1_ICACHE0_FREEZE_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_FREEZE_EN_M  (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S)
+#define CACHE_L1_ICACHE0_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_EN_S  0
+/** CACHE_L1_ICACHE0_FREEZE_MODE : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_MODE    (BIT(1))
+#define CACHE_L1_ICACHE0_FREEZE_MODE_M  (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE0_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_MODE_S  1
+/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_DONE    (BIT(2))
+#define CACHE_L1_ICACHE0_FREEZE_DONE_M  (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE0_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_DONE_S  2
+/** CACHE_L1_ICACHE1_FREEZE_EN : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_FREEZE_EN_M  (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S)
+#define CACHE_L1_ICACHE1_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_EN_S  4
+/** CACHE_L1_ICACHE1_FREEZE_MODE : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_MODE    (BIT(5))
+#define CACHE_L1_ICACHE1_FREEZE_MODE_M  (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE1_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_MODE_S  5
+/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_DONE    (BIT(6))
+#define CACHE_L1_ICACHE1_FREEZE_DONE_M  (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE1_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_DONE_S  6
+/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_FREEZE_EN_M  (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S)
+#define CACHE_L1_ICACHE2_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_EN_S  8
+/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_MODE    (BIT(9))
+#define CACHE_L1_ICACHE2_FREEZE_MODE_M  (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE2_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_MODE_S  9
+/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_DONE    (BIT(10))
+#define CACHE_L1_ICACHE2_FREEZE_DONE_M  (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE2_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_DONE_S  10
+/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_FREEZE_EN_M  (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S)
+#define CACHE_L1_ICACHE3_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_EN_S  12
+/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_MODE    (BIT(13))
+#define CACHE_L1_ICACHE3_FREEZE_MODE_M  (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE3_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_MODE_S  13
+/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_DONE    (BIT(14))
+#define CACHE_L1_ICACHE3_FREEZE_DONE_M  (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE3_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_DONE_S  14
+/** CACHE_L1_DCACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0;
+ *  The bit is used to enable freeze operation on L1-DCache. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_DCACHE_FREEZE_EN    (BIT(16))
+#define CACHE_L1_DCACHE_FREEZE_EN_M  (CACHE_L1_DCACHE_FREEZE_EN_V << CACHE_L1_DCACHE_FREEZE_EN_S)
+#define CACHE_L1_DCACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_EN_S  16
+/** CACHE_L1_DCACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_DCACHE_FREEZE_MODE    (BIT(17))
+#define CACHE_L1_DCACHE_FREEZE_MODE_M  (CACHE_L1_DCACHE_FREEZE_MODE_V << CACHE_L1_DCACHE_FREEZE_MODE_S)
+#define CACHE_L1_DCACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_MODE_S  17
+/** CACHE_L1_DCACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-DCache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_DCACHE_FREEZE_DONE    (BIT(18))
+#define CACHE_L1_DCACHE_FREEZE_DONE_M  (CACHE_L1_DCACHE_FREEZE_DONE_V << CACHE_L1_DCACHE_FREEZE_DONE_S)
+#define CACHE_L1_DCACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_DONE_S  18
+
+/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30)
+/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : R/W; bitpos: [1]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+ *  1: enable.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : R/W; bitpos: [5]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+ *  1: enable.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S  13
+/** CACHE_L1_DCACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_M  (CACHE_L1_DCACHE_DATA_MEM_RD_EN_V << CACHE_L1_DCACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_S  16
+/** CACHE_L1_DCACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
+ *  The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_M  (CACHE_L1_DCACHE_DATA_MEM_WR_EN_V << CACHE_L1_DCACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_S  17
+
+/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34)
+/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : R/W; bitpos: [1]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : R/W; bitpos: [5]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S  13
+/** CACHE_L1_DCACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_M  (CACHE_L1_DCACHE_TAG_MEM_RD_EN_V << CACHE_L1_DCACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_S  16
+/** CACHE_L1_DCACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
+ *  The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_M  (CACHE_L1_DCACHE_TAG_MEM_WR_EN_V << CACHE_L1_DCACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_S  17
+
+/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x38)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE0_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 prelock.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_M  (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x3c)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache0, which should be used together with
+ *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x40)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache0, which should be used together with
+ *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x44)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x48)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE1_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 prelock.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_M  (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x4c)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache1, which should be used together with
+ *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x50)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache1, which should be used together with
+ *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x54)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x58)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 prelock.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_M  (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x5c)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache2, which should be used together with
+ *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x60)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache2, which should be used together with
+ *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x64)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x68)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 prelock.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_M  (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x6c)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache3, which should be used together with
+ *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x70)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache3, which should be used together with
+ *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x74)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_DCACHE_PRELOCK_CONF_REG register
+ *  L1 data Cache prelock configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_EN_V << CACHE_L1_DCACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_EN_V << CACHE_L1_DCACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_DCACHE_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 dcache prelock.
+ */
+#define CACHE_L1_DCACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_PRELOCK_RGID_M  (CACHE_L1_DCACHE_PRELOCK_RGID_V << CACHE_L1_DCACHE_PRELOCK_RGID_S)
+#define CACHE_L1_DCACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L1 data Cache prelock section0 address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7c)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-DCache, which should be used together with
+ *  L1_DCACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L1 data Cache prelock section1 address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80)
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-DCache, which should be used together with
+ *  L1_DCACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register
+ *  L1 data Cache prelock section size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_LOCK_CTRL_REG register
+ *  Lock-class (manual lock) operation control register
+ */
+#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88)
+/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+ *  operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive,
+ *  that is, those bits can not be set to 1 at the same time. (2) lock operation can be
+ *  applied on LL1-ICache, L1-DCache and L2-Cache.
+ */
+#define CACHE_LOCK_ENA    (BIT(0))
+#define CACHE_LOCK_ENA_M  (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S)
+#define CACHE_LOCK_ENA_V  0x00000001U
+#define CACHE_LOCK_ENA_S  0
+/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  The bit is used to enable unlock operation. It will be cleared by hardware after
+ *  unlock operation done. Note that (1) this bit and lock_ena bit are mutually
+ *  exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock
+ *  operation can be applied on L1-ICache, L1-DCache and L2-Cache.
+ */
+#define CACHE_UNLOCK_ENA    (BIT(1))
+#define CACHE_UNLOCK_ENA_M  (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S)
+#define CACHE_UNLOCK_ENA_V  0x00000001U
+#define CACHE_UNLOCK_ENA_S  1
+/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
+ *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+ *  not finished. 1: finished.
+ */
+#define CACHE_LOCK_DONE    (BIT(2))
+#define CACHE_LOCK_DONE_M  (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S)
+#define CACHE_LOCK_DONE_V  0x00000001U
+#define CACHE_LOCK_DONE_S  2
+/** CACHE_LOCK_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of cache lock/unlock.
+ */
+#define CACHE_LOCK_RGID    0x0000000FU
+#define CACHE_LOCK_RGID_M  (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S)
+#define CACHE_LOCK_RGID_V  0x0000000FU
+#define CACHE_LOCK_RGID_S  3
+
+/** CACHE_LOCK_MAP_REG register
+ *  Lock (manual lock) map configure register
+ */
+#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8c)
+/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Those bits are used to indicate which caches in the two-level cache structure will
+ *  apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]:
+ *  L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
+ */
+#define CACHE_LOCK_MAP    0x0000003FU
+#define CACHE_LOCK_MAP_M  (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S)
+#define CACHE_LOCK_MAP_V  0x0000003FU
+#define CACHE_LOCK_MAP_S  0
+
+/** CACHE_LOCK_ADDR_REG register
+ *  Lock (manual lock) address configure register
+ */
+#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90)
+/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the lock/unlock
+ *  operation, which should be used together with CACHE_LOCK_SIZE_REG
+ */
+#define CACHE_LOCK_ADDR    0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_M  (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S)
+#define CACHE_LOCK_ADDR_V  0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_S  0
+
+/** CACHE_LOCK_SIZE_REG register
+ *  Lock (manual lock) size configure register
+ */
+#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94)
+/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  Those bits are used to configure the size of the lock/unlock operation, which
+ *  should be used together with CACHE_LOCK_ADDR_REG
+ */
+#define CACHE_LOCK_SIZE    0x0000FFFFU
+#define CACHE_LOCK_SIZE_M  (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S)
+#define CACHE_LOCK_SIZE_V  0x0000FFFFU
+#define CACHE_LOCK_SIZE_S  0
+
+/** CACHE_SYNC_CTRL_REG register
+ *  Sync-class operation control register
+ */
+#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98)
+/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1;
+ *  The bit is used to enable invalidate operation. It will be cleared by hardware
+ *  after invalidate operation done. Note that this bit and the other sync-bits
+ *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+ *  is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_INVALIDATE_ENA    (BIT(0))
+#define CACHE_INVALIDATE_ENA_M  (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S)
+#define CACHE_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_INVALIDATE_ENA_S  0
+/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  The bit is used to enable clean operation. It will be cleared by hardware after
+ *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+ *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+ *  bits can not be set to 1 at the same time.
+ */
+#define CACHE_CLEAN_ENA    (BIT(1))
+#define CACHE_CLEAN_ENA_M  (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S)
+#define CACHE_CLEAN_ENA_V  0x00000001U
+#define CACHE_CLEAN_ENA_S  1
+/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0;
+ *  The bit is used to enable writeback operation. It will be cleared by hardware after
+ *  writeback operation done. Note that this bit and the other sync-bits
+ *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+ *  is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_WRITEBACK_ENA    (BIT(2))
+#define CACHE_WRITEBACK_ENA_M  (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S)
+#define CACHE_WRITEBACK_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_ENA_S  2
+/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0;
+ *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+ *  hardware after writeback-invalidate operation done. Note that this bit and the
+ *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+ *  that is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
+#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S)
+#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
+/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0;
+ *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+ *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+ */
+#define CACHE_SYNC_DONE    (BIT(4))
+#define CACHE_SYNC_DONE_M  (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S)
+#define CACHE_SYNC_DONE_V  0x00000001U
+#define CACHE_SYNC_DONE_S  4
+/** CACHE_SYNC_RGID : R/W; bitpos: [8:5]; default: 0;
+ *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+ *  writeback, writeback_invalidate)
+ */
+#define CACHE_SYNC_RGID    0x0000000FU
+#define CACHE_SYNC_RGID_M  (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S)
+#define CACHE_SYNC_RGID_V  0x0000000FU
+#define CACHE_SYNC_RGID_S  5
+
+/** CACHE_SYNC_MAP_REG register
+ *  Sync map configure register
+ */
+#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9c)
+/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 31;
+ *  Those bits are used to indicate which caches in the two-level cache structure will
+ *  apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]:
+ *  L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
+ */
+#define CACHE_SYNC_MAP    0x0000003FU
+#define CACHE_SYNC_MAP_M  (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S)
+#define CACHE_SYNC_MAP_V  0x0000003FU
+#define CACHE_SYNC_MAP_S  0
+
+/** CACHE_SYNC_ADDR_REG register
+ *  Sync address configure register
+ */
+#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa0)
+/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the sync operation,
+ *  which should be used together with CACHE_SYNC_SIZE_REG
+ */
+#define CACHE_SYNC_ADDR    0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_M  (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S)
+#define CACHE_SYNC_ADDR_V  0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_S  0
+
+/** CACHE_SYNC_SIZE_REG register
+ *  Sync size configure register
+ */
+#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa4)
+/** CACHE_SYNC_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the sync operation, which should be
+ *  used together with CACHE_SYNC_ADDR_REG
+ */
+#define CACHE_SYNC_SIZE    0x0FFFFFFFU
+#define CACHE_SYNC_SIZE_M  (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S)
+#define CACHE_SYNC_SIZE_V  0x0FFFFFFFU
+#define CACHE_SYNC_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa8)
+/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_M  (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_M  (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M  (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 preload.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_M  (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE0_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l1 icache0 preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE0_PRELOAD_MODE_M  (CACHE_L1_ICACHE0_PRELOAD_MODE_V << CACHE_L1_ICACHE0_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xac)
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M  (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb0)
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M  (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb4)
+/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_M  (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_M  (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M  (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 preload.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_M  (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE1_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l1 icache1 preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE1_PRELOAD_MODE_M  (CACHE_L1_ICACHE1_PRELOAD_MODE_V << CACHE_L1_ICACHE1_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb8)
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M  (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xbc)
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M  (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc0)
+/** CACHE_L1_ICACHE2_PRELOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_M  (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_M  (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M  (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 preload.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_M  (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE2_PRELOAD_MODE : HRO; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l1 icache2 preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE2_PRELOAD_MODE_M  (CACHE_L1_ICACHE2_PRELOAD_MODE_V << CACHE_L1_ICACHE2_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc4)
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M  (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc8)
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M  (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xcc)
+/** CACHE_L1_ICACHE3_PRELOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_M  (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_M  (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M  (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 preload.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_M  (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE3_PRELOAD_MODE : HRO; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l1 icache3 preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE3_PRELOAD_MODE_M  (CACHE_L1_ICACHE3_PRELOAD_MODE_V << CACHE_L1_ICACHE3_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd0)
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M  (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd4)
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M  (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_DCACHE_PRELOAD_CTRL_REG register
+ *  L1 data Cache  preload-operation control register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd8)
+/** CACHE_L1_DCACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-DCache. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_DCACHE_PRELOAD_ENA_M  (CACHE_L1_DCACHE_PRELOAD_ENA_V << CACHE_L1_DCACHE_PRELOAD_ENA_S)
+#define CACHE_L1_DCACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_ENA_S  0
+/** CACHE_L1_DCACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_DCACHE_PRELOAD_DONE_M  (CACHE_L1_DCACHE_PRELOAD_DONE_V << CACHE_L1_DCACHE_PRELOAD_DONE_S)
+#define CACHE_L1_DCACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_DONE_S  1
+/** CACHE_L1_DCACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_M  (CACHE_L1_DCACHE_PRELOAD_ORDER_V << CACHE_L1_DCACHE_PRELOAD_ORDER_S)
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_S  2
+/** CACHE_L1_DCACHE_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 dcache preload.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_PRELOAD_RGID_M  (CACHE_L1_DCACHE_PRELOAD_RGID_V << CACHE_L1_DCACHE_PRELOAD_RGID_S)
+#define CACHE_L1_DCACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_PRELOAD_RGID_S  3
+/** CACHE_L1_DCACHE_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l1 dcache preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_DCACHE_PRELOAD_MODE_M  (CACHE_L1_DCACHE_PRELOAD_MODE_V << CACHE_L1_DCACHE_PRELOAD_MODE_S)
+#define CACHE_L1_DCACHE_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_MODE_S  7
+
+/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
+ *  L1 data Cache  preload address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xdc)
+/** CACHE_L1_DCACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on L1-DCache,
+ *  which should be used together with L1_DCACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_M  (CACHE_L1_DCACHE_PRELOAD_ADDR_V << CACHE_L1_DCACHE_PRELOAD_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register
+ *  L1 data Cache  preload size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe0)
+/** CACHE_L1_DCACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_M  (CACHE_L1_DCACHE_PRELOAD_SIZE_V << CACHE_L1_DCACHE_PRELOAD_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe4)
+/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : R/W; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 autoload.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe8)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xec)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xf0)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf4)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf8)
+/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : R/W; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 autoload.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xfc)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x100)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x104)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x108)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x10c)
+/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 autoload.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x110)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x114)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x118)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x11c)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x120)
+/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 autoload.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x124)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x128)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x12c)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x130)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_CTRL_REG register
+ *  L1 data Cache autoload-operation control register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134)
+/** CACHE_L1_DCACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-DCache.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L1_DCACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-DCache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_M  (CACHE_L1_DCACHE_AUTOLOAD_DONE_V << CACHE_L1_DCACHE_AUTOLOAD_DONE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L1_DCACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-DCache. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_M  (CACHE_L1_DCACHE_AUTOLOAD_ORDER_V << CACHE_L1_DCACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-DCache.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA : R/W; bitpos: [10]; default: 0;
+ *  The bit is used to enable the third section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable the fourth section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L1_DCACHE_AUTOLOAD_RGID : R/W; bitpos: [15:12]; default: 0;
+ *  The bit is used to set  the gid of l1 dcache autoload.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_M  (CACHE_L1_DCACHE_AUTOLOAD_RGID_V << CACHE_L1_DCACHE_AUTOLOAD_RGID_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 data Cache autoload section 0 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 data Cache autoload section 0 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13c)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L1 data Cache autoload section 2 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x148)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the third section for
+ *  autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L1 data Cache autoload section 2 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x14c)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the third section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x150)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the fourth section
+ *  for autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x154)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the fourth section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158)
+/** CACHE_L1_IBUS0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ENA_M  (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ENA_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ENA_M  (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ENA_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ENA_M  (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ENA_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ENA_M  (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ENA_S  3
+/** CACHE_L1_DBUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_ENA    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_ENA_M  (CACHE_L1_DBUS0_OVF_INT_ENA_V << CACHE_L1_DBUS0_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_ENA_S  4
+/** CACHE_L1_DBUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_ENA    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_ENA_M  (CACHE_L1_DBUS1_OVF_INT_ENA_V << CACHE_L1_DBUS1_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_ENA_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ENA_M  (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ENA_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ENA_M  (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ENA_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15c)
+/** CACHE_L1_IBUS0_OVF_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+ *  to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_CLR    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_CLR_M  (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_CLR_S  0
+/** CACHE_L1_IBUS1_OVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+ *  to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_CLR    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_CLR_M  (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_CLR_S  1
+/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_CLR    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_CLR_M  (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_CLR_S  2
+/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_CLR    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_CLR_M  (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_CLR_S  3
+/** CACHE_L1_DBUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_CLR    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_CLR_M  (CACHE_L1_DBUS0_OVF_INT_CLR_V << CACHE_L1_DBUS0_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_CLR_S  4
+/** CACHE_L1_DBUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_CLR    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_CLR_M  (CACHE_L1_DBUS1_OVF_INT_CLR_V << CACHE_L1_DBUS1_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_CLR_S  5
+/** CACHE_L1_DBUS2_OVF_INT_CLR : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_CLR    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_CLR_M  (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_CLR_S  6
+/** CACHE_L1_DBUS3_OVF_INT_CLR : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_CLR    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_CLR_M  (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_CLR_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160)
+/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+ *  due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_RAW    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_RAW_M  (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_RAW_S  0
+/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+ *  due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_RAW    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_RAW_M  (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_RAW_S  1
+/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+ *  due to bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_OVF_INT_RAW    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_RAW_M  (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_RAW_S  2
+/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+ *  due to bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_OVF_INT_RAW    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_RAW_M  (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_RAW_S  3
+/** CACHE_L1_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_RAW    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_RAW_M  (CACHE_L1_DBUS0_OVF_INT_RAW_V << CACHE_L1_DBUS0_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_RAW_S  4
+/** CACHE_L1_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_RAW    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_RAW_M  (CACHE_L1_DBUS1_OVF_INT_RAW_V << CACHE_L1_DBUS1_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_RAW_S  5
+/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_OVF_INT_RAW    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_RAW_M  (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_RAW_S  6
+/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_OVF_INT_RAW    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_RAW_M  (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_RAW_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164)
+/** CACHE_L1_IBUS0_OVF_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ST    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ST_M  (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S)
+#define CACHE_L1_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ST_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ST    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ST_M  (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S)
+#define CACHE_L1_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ST_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ST    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ST_M  (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S)
+#define CACHE_L1_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ST_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ST    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ST_M  (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S)
+#define CACHE_L1_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ST_S  3
+/** CACHE_L1_DBUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_ST    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_ST_M  (CACHE_L1_DBUS0_OVF_INT_ST_V << CACHE_L1_DBUS0_OVF_INT_ST_S)
+#define CACHE_L1_DBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_ST_S  4
+/** CACHE_L1_DBUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_ST    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_ST_M  (CACHE_L1_DBUS1_OVF_INT_ST_V << CACHE_L1_DBUS1_OVF_INT_ST_S)
+#define CACHE_L1_DBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_ST_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ST : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ST    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ST_M  (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S)
+#define CACHE_L1_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ST_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ST : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ST    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ST_M  (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S)
+#define CACHE_L1_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ST_S  7
+
+/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register
+ *  Cache Access Fail Configuration register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x168)
+/** CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to configure l1 icache0 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE    (BIT(0))
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S  0
+/** CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to configure l1 icache1 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE    (BIT(1))
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S  1
+/** CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure l1 icache2 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE    (BIT(2))
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S  2
+/** CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE : R/W; bitpos: [3]; default: 0;
+ *  The bit is used to configure l1 icache3 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE    (BIT(3))
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S  3
+/** CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to configure l1 dcache access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE    (BIT(4))
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x16c)
+/** CACHE_L1_ICACHE0_FAIL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M  (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M  (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M  (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M  (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_ENA    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_M  (CACHE_L1_DCACHE_FAIL_INT_ENA_V << CACHE_L1_DCACHE_FAIL_INT_ENA_S)
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x170)
+/** CACHE_L1_ICACHE0_FAIL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M  (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M  (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M  (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M  (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_M  (CACHE_L1_DCACHE_FAIL_INT_CLR_V << CACHE_L1_DCACHE_FAIL_INT_CLR_S)
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x174)
+/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M  (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M  (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M  (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M  (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_RAW    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_M  (CACHE_L1_DCACHE_FAIL_INT_RAW_V << CACHE_L1_DCACHE_FAIL_INT_RAW_S)
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x178)
+/** CACHE_L1_ICACHE0_FAIL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_M  (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_M  (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_M  (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_M  (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+ *  to cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_ST    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_ST_M  (CACHE_L1_DCACHE_FAIL_INT_ST_V << CACHE_L1_DCACHE_FAIL_INT_ST_S)
+#define CACHE_L1_DCACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_ST_S  4
+
+/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x17c)
+/** CACHE_L1_IBUS0_CNT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable ibus0 counter in L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CNT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_CNT_ENA_M  (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S)
+#define CACHE_L1_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_ENA_S  0
+/** CACHE_L1_IBUS1_CNT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable ibus1 counter in L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CNT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_CNT_ENA_M  (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S)
+#define CACHE_L1_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_ENA_S  1
+/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_CNT_ENA_M  (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S)
+#define CACHE_L1_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_ENA_S  2
+/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_CNT_ENA_M  (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S)
+#define CACHE_L1_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_ENA_S  3
+/** CACHE_L1_DBUS0_CNT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable dbus0 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS0_CNT_ENA    (BIT(4))
+#define CACHE_L1_DBUS0_CNT_ENA_M  (CACHE_L1_DBUS0_CNT_ENA_V << CACHE_L1_DBUS0_CNT_ENA_S)
+#define CACHE_L1_DBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS0_CNT_ENA_S  4
+/** CACHE_L1_DBUS1_CNT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable dbus1 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS1_CNT_ENA    (BIT(5))
+#define CACHE_L1_DBUS1_CNT_ENA_M  (CACHE_L1_DBUS1_CNT_ENA_V << CACHE_L1_DBUS1_CNT_ENA_S)
+#define CACHE_L1_DBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS1_CNT_ENA_S  5
+/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_CNT_ENA_M  (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S)
+#define CACHE_L1_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_ENA_S  6
+/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_CNT_ENA_M  (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S)
+#define CACHE_L1_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_ENA_S  7
+/** CACHE_L1_IBUS0_CNT_CLR : WT; bitpos: [16]; default: 0;
+ *  The bit is used to clear ibus0 counter in L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CNT_CLR    (BIT(16))
+#define CACHE_L1_IBUS0_CNT_CLR_M  (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S)
+#define CACHE_L1_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_CLR_S  16
+/** CACHE_L1_IBUS1_CNT_CLR : WT; bitpos: [17]; default: 0;
+ *  The bit is used to clear ibus1 counter in L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CNT_CLR    (BIT(17))
+#define CACHE_L1_IBUS1_CNT_CLR_M  (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S)
+#define CACHE_L1_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_CLR_S  17
+/** CACHE_L1_IBUS2_CNT_CLR : HRO; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_CLR    (BIT(18))
+#define CACHE_L1_IBUS2_CNT_CLR_M  (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S)
+#define CACHE_L1_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_CLR_S  18
+/** CACHE_L1_IBUS3_CNT_CLR : HRO; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_CLR    (BIT(19))
+#define CACHE_L1_IBUS3_CNT_CLR_M  (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S)
+#define CACHE_L1_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_CLR_S  19
+/** CACHE_L1_DBUS0_CNT_CLR : WT; bitpos: [20]; default: 0;
+ *  The bit is used to clear dbus0 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS0_CNT_CLR    (BIT(20))
+#define CACHE_L1_DBUS0_CNT_CLR_M  (CACHE_L1_DBUS0_CNT_CLR_V << CACHE_L1_DBUS0_CNT_CLR_S)
+#define CACHE_L1_DBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS0_CNT_CLR_S  20
+/** CACHE_L1_DBUS1_CNT_CLR : WT; bitpos: [21]; default: 0;
+ *  The bit is used to clear dbus1 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS1_CNT_CLR    (BIT(21))
+#define CACHE_L1_DBUS1_CNT_CLR_M  (CACHE_L1_DBUS1_CNT_CLR_V << CACHE_L1_DBUS1_CNT_CLR_S)
+#define CACHE_L1_DBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS1_CNT_CLR_S  21
+/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_CLR    (BIT(22))
+#define CACHE_L1_DBUS2_CNT_CLR_M  (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S)
+#define CACHE_L1_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_CLR_S  22
+/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_CLR    (BIT(23))
+#define CACHE_L1_DBUS3_CNT_CLR_M  (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S)
+#define CACHE_L1_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_CLR_S  23
+
+/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x180)
+/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_M  (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S)
+#define CACHE_L1_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x184)
+/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_M  (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S)
+#define CACHE_L1_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x188)
+/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_M  (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x18c)
+/** CACHE_L1_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS0_NXTLVL_RD_CNT_V << CACHE_L1_IBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x190)
+/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_M  (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S)
+#define CACHE_L1_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x194)
+/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_M  (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S)
+#define CACHE_L1_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x198)
+/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_M  (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x19c)
+/** CACHE_L1_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS1_NXTLVL_RD_CNT_V << CACHE_L1_IBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1a0)
+/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_M  (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S)
+#define CACHE_L1_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a4)
+/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_M  (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S)
+#define CACHE_L1_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a8)
+/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_M  (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1ac)
+/** CACHE_L1_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS2_NXTLVL_RD_CNT_V << CACHE_L1_IBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1b0)
+/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_M  (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S)
+#define CACHE_L1_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b4)
+/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_M  (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S)
+#define CACHE_L1_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b8)
+/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_M  (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1bc)
+/** CACHE_L1_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS3_NXTLVL_RD_CNT_V << CACHE_L1_IBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_HIT_CNT_REG register
+ *  L1-DCache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1c0)
+/** CACHE_L1_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_HIT_CNT_M  (CACHE_L1_DBUS0_HIT_CNT_V << CACHE_L1_DBUS0_HIT_CNT_S)
+#define CACHE_L1_DBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_MISS_CNT_REG register
+ *  L1-DCache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c4)
+/** CACHE_L1_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_MISS_CNT_M  (CACHE_L1_DBUS0_MISS_CNT_V << CACHE_L1_DBUS0_MISS_CNT_S)
+#define CACHE_L1_DBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c8)
+/** CACHE_L1_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_CONFLICT_CNT_M  (CACHE_L1_DBUS0_CONFLICT_CNT_V << CACHE_L1_DBUS0_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1cc)
+/** CACHE_L1_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS0_NXTLVL_RD_CNT_V << CACHE_L1_DBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus0 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1d0)
+/** CACHE_L1_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS0_NXTLVL_WR_CNT_V << CACHE_L1_DBUS0_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_HIT_CNT_REG register
+ *  L1-DCache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d4)
+/** CACHE_L1_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_HIT_CNT_M  (CACHE_L1_DBUS1_HIT_CNT_V << CACHE_L1_DBUS1_HIT_CNT_S)
+#define CACHE_L1_DBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_MISS_CNT_REG register
+ *  L1-DCache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d8)
+/** CACHE_L1_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_MISS_CNT_M  (CACHE_L1_DBUS1_MISS_CNT_V << CACHE_L1_DBUS1_MISS_CNT_S)
+#define CACHE_L1_DBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1dc)
+/** CACHE_L1_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_CONFLICT_CNT_M  (CACHE_L1_DBUS1_CONFLICT_CNT_V << CACHE_L1_DBUS1_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1e0)
+/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus1 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e4)
+/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1e8)
+/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_M  (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S)
+#define CACHE_L1_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1ec)
+/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_M  (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S)
+#define CACHE_L1_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1f0)
+/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_M  (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1f4)
+/** CACHE_L1_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS2_NXTLVL_RD_CNT_V << CACHE_L1_DBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus2 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1f8)
+/** CACHE_L1_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS2_NXTLVL_WR_CNT_V << CACHE_L1_DBUS2_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1fc)
+/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_M  (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S)
+#define CACHE_L1_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x200)
+/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_M  (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S)
+#define CACHE_L1_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x204)
+/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_M  (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x208)
+/** CACHE_L1_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS3_NXTLVL_RD_CNT_V << CACHE_L1_DBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus3 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x20c)
+/** CACHE_L1_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS3_NXTLVL_WR_CNT_V << CACHE_L1_DBUS3_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x210)
+/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_M  (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S)
+#define CACHE_L1_ICACHE0_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_S  0
+/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_M  (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE0_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x214)
+/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_M  (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE0_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x218)
+/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_M  (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S)
+#define CACHE_L1_ICACHE1_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_S  0
+/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_M  (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE1_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x21c)
+/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_M  (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE1_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x220)
+/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_M  (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S)
+#define CACHE_L1_ICACHE2_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_S  0
+/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_M  (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE2_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x224)
+/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_M  (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE2_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x228)
+/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_M  (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S)
+#define CACHE_L1_ICACHE3_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_S  0
+/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_M  (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE3_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x22c)
+/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_M  (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE3_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_S  0
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L1-DCache Access Fail ID/attribution information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x230)
+/** CACHE_L1_DCACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ID_M  (CACHE_L1_DCACHE_FAIL_ID_V << CACHE_L1_DCACHE_FAIL_ID_S)
+#define CACHE_L1_DCACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ID_S  0
+/** CACHE_L1_DCACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ATTR_M  (CACHE_L1_DCACHE_FAIL_ATTR_V << CACHE_L1_DCACHE_FAIL_ATTR_S)
+#define CACHE_L1_DCACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ATTR_S  16
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register
+ *  L1-DCache Access Fail Address information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x234)
+/** CACHE_L1_DCACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_FAIL_ADDR_M  (CACHE_L1_DCACHE_FAIL_ADDR_V << CACHE_L1_DCACHE_FAIL_ADDR_S)
+#define CACHE_L1_DCACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_FAIL_ADDR_S  0
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x238)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of L1-DCache preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_M  (CACHE_L1_DCACHE_PLD_DONE_INT_ENA_V << CACHE_L1_DCACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_S  4
+/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The bit is used to enable interrupt of Cache sync-operation done.
+ */
+#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ENA_M  (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S)
+#define CACHE_SYNC_DONE_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ENA_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_M  (CACHE_L1_DCACHE_PLD_ERR_INT_ENA_V << CACHE_L1_DCACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_S  11
+/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ENA_M  (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S)
+#define CACHE_SYNC_ERR_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ENA_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x23c)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-DCache
+ *  preload-operation is done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_M  (CACHE_L1_DCACHE_PLD_DONE_INT_CLR_V << CACHE_L1_DCACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_S  4
+/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+ *  done.
+ */
+#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
+#define CACHE_SYNC_DONE_INT_CLR_M  (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S)
+#define CACHE_SYNC_DONE_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_CLR_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The bit is used to clear interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_M  (CACHE_L1_DCACHE_PLD_ERR_INT_CLR_V << CACHE_L1_DCACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_S  11
+/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The bit is used to clear interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
+#define CACHE_SYNC_ERR_INT_CLR_M  (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S)
+#define CACHE_SYNC_ERR_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_CLR_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x240)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation is
+ *  done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_M  (CACHE_L1_DCACHE_PLD_DONE_INT_RAW_V << CACHE_L1_DCACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_S  4
+/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
+#define CACHE_SYNC_DONE_INT_RAW_M  (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S)
+#define CACHE_SYNC_DONE_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_RAW_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_M  (CACHE_L1_DCACHE_PLD_ERR_INT_RAW_V << CACHE_L1_DCACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_S  11
+/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+ *  occurs.
+ */
+#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
+#define CACHE_SYNC_ERR_INT_RAW_M  (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S)
+#define CACHE_SYNC_ERR_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_RAW_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x244)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-DCache
+ *  preload-operation is done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_M  (CACHE_L1_DCACHE_PLD_DONE_INT_ST_V << CACHE_L1_DCACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_S  4
+/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when Cache
+ *  sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ST_M  (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S)
+#define CACHE_SYNC_DONE_INT_ST_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ST_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : RO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : RO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_M  (CACHE_L1_DCACHE_PLD_ERR_INT_ST_V << CACHE_L1_DCACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_S  11
+/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The bit indicates the status of the interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ST_M  (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S)
+#define CACHE_SYNC_ERR_INT_ST_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ST_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x248)
+/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M  (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S  0
+/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M  (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S  2
+/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M  (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S  4
+/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M  (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S  6
+/** CACHE_L1_DCACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_M  (CACHE_L1_DCACHE_PLD_ERR_CODE_V << CACHE_L1_DCACHE_PLD_ERR_CODE_S)
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_S  8
+/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0;
+ *  The values 0-2 are available which means sync map, command conflict and size are
+ *  error in Cache System.
+ */
+#define CACHE_SYNC_ERR_CODE    0x00000003U
+#define CACHE_SYNC_ERR_CODE_M  (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S)
+#define CACHE_SYNC_ERR_CODE_V  0x00000003U
+#define CACHE_SYNC_ERR_CODE_S  12
+
+/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c)
+/** CACHE_L1_ICACHE0_SYNC_RST : R/W; bitpos: [0]; default: 0;
+ *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE0_SYNC_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_SYNC_RST_M  (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S)
+#define CACHE_L1_ICACHE0_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_SYNC_RST_S  0
+/** CACHE_L1_ICACHE1_SYNC_RST : R/W; bitpos: [1]; default: 0;
+ *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE1_SYNC_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_SYNC_RST_M  (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S)
+#define CACHE_L1_ICACHE1_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_SYNC_RST_S  1
+/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_SYNC_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_SYNC_RST_M  (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S)
+#define CACHE_L1_ICACHE2_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_SYNC_RST_S  2
+/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_SYNC_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_SYNC_RST_M  (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S)
+#define CACHE_L1_ICACHE3_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_SYNC_RST_S  3
+/** CACHE_L1_DCACHE_SYNC_RST : R/W; bitpos: [4]; default: 0;
+ *  set this bit to reset sync-logic inside L1-DCache. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_DCACHE_SYNC_RST    (BIT(4))
+#define CACHE_L1_DCACHE_SYNC_RST_M  (CACHE_L1_DCACHE_SYNC_RST_V << CACHE_L1_DCACHE_SYNC_RST_S)
+#define CACHE_L1_DCACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L1_DCACHE_SYNC_RST_S  4
+
+/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x250)
+/** CACHE_L1_ICACHE0_PLD_RST : R/W; bitpos: [0]; default: 0;
+ *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_RST_M  (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S)
+#define CACHE_L1_ICACHE0_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_RST_S  0
+/** CACHE_L1_ICACHE1_PLD_RST : R/W; bitpos: [1]; default: 0;
+ *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_RST_M  (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S)
+#define CACHE_L1_ICACHE1_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_RST_S  1
+/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_RST_M  (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S)
+#define CACHE_L1_ICACHE2_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_RST_S  2
+/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_RST_M  (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S)
+#define CACHE_L1_ICACHE3_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_RST_S  3
+/** CACHE_L1_DCACHE_PLD_RST : R/W; bitpos: [4]; default: 0;
+ *  set this bit to reset preload-logic inside L1-DCache. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_RST    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_RST_M  (CACHE_L1_DCACHE_PLD_RST_V << CACHE_L1_DCACHE_PLD_RST_S)
+#define CACHE_L1_DCACHE_PLD_RST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_RST_S  4
+
+/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x254)
+/** CACHE_L1_ICACHE0_ALD_BUF_CLR : R/W; bitpos: [0]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+ *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+ *  works in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M  (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S  0
+/** CACHE_L1_ICACHE1_ALD_BUF_CLR : R/W; bitpos: [1]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+ *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+ *  works in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M  (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S  1
+/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M  (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S  2
+/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M  (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S  3
+/** CACHE_L1_DCACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-DCache. If this bit is active,
+ *  autoload will not work in L1-DCache. This bit should not be active when autoload
+ *  works in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_ALD_BUF_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_M  (CACHE_L1_DCACHE_ALD_BUF_CLR_V << CACHE_L1_DCACHE_ALD_BUF_CLR_S)
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_S  4
+
+/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x258)
+/** CACHE_L1_ICACHE0_UNALLOC_CLR : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
+/** CACHE_L1_ICACHE1_UNALLOC_CLR : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_S  1
+/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_UNALLOC_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_M  (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_S  2
+/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_UNALLOC_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_M  (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
+/** CACHE_L1_DCACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 dcache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_DCACHE_UNALLOC_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_UNALLOC_CLR_M  (CACHE_L1_DCACHE_UNALLOC_CLR_V << CACHE_L1_DCACHE_UNALLOC_CLR_S)
+#define CACHE_L1_DCACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_UNALLOC_CLR_S  4
+
+/** CACHE_L1_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x25c)
+/** CACHE_L1_ICACHE0_TAG_OBJECT : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_TAG_OBJECT    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_OBJECT_M  (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE0_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_OBJECT_S  0
+/** CACHE_L1_ICACHE1_TAG_OBJECT : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_TAG_OBJECT    (BIT(1))
+#define CACHE_L1_ICACHE1_TAG_OBJECT_M  (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE1_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_OBJECT_S  1
+/** CACHE_L1_ICACHE2_TAG_OBJECT : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_OBJECT    (BIT(2))
+#define CACHE_L1_ICACHE2_TAG_OBJECT_M  (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE2_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_OBJECT_S  2
+/** CACHE_L1_ICACHE3_TAG_OBJECT : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_OBJECT    (BIT(3))
+#define CACHE_L1_ICACHE3_TAG_OBJECT_M  (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE3_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_OBJECT_S  3
+/** CACHE_L1_DCACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to set L1-DCache tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_DCACHE_TAG_OBJECT    (BIT(4))
+#define CACHE_L1_DCACHE_TAG_OBJECT_M  (CACHE_L1_DCACHE_TAG_OBJECT_V << CACHE_L1_DCACHE_TAG_OBJECT_S)
+#define CACHE_L1_DCACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_OBJECT_S  4
+/** CACHE_L1_ICACHE0_MEM_OBJECT : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+ *  with the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_MEM_OBJECT    (BIT(6))
+#define CACHE_L1_ICACHE0_MEM_OBJECT_M  (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE0_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_MEM_OBJECT_S  6
+/** CACHE_L1_ICACHE1_MEM_OBJECT : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+ *  with the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_MEM_OBJECT    (BIT(7))
+#define CACHE_L1_ICACHE1_MEM_OBJECT_M  (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE1_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_MEM_OBJECT_S  7
+/** CACHE_L1_ICACHE2_MEM_OBJECT : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_MEM_OBJECT    (BIT(8))
+#define CACHE_L1_ICACHE2_MEM_OBJECT_M  (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE2_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_MEM_OBJECT_S  8
+/** CACHE_L1_ICACHE3_MEM_OBJECT : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_MEM_OBJECT    (BIT(9))
+#define CACHE_L1_ICACHE3_MEM_OBJECT_M  (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE3_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_MEM_OBJECT_S  9
+/** CACHE_L1_DCACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to set L1-DCache data memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_DCACHE_MEM_OBJECT    (BIT(10))
+#define CACHE_L1_DCACHE_MEM_OBJECT_M  (CACHE_L1_DCACHE_MEM_OBJECT_V << CACHE_L1_DCACHE_MEM_OBJECT_S)
+#define CACHE_L1_DCACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_DCACHE_MEM_OBJECT_S  10
+
+/** CACHE_L1_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x260)
+/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
+ *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+ *  way1, 2: way2, 3: way3, ?, 7: way7.
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_M  (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S)
+#define CACHE_L1_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L1_CACHE_VADDR_REG register
+ *  Cache Vaddr register
+ */
+#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x264)
+/** CACHE_L1_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
+ *  Those bits stores the virtual address which will decide where inside the specified
+ *  tag memory object will be accessed.
+ */
+#define CACHE_L1_CACHE_VADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_VADDR_M  (CACHE_L1_CACHE_VADDR_V << CACHE_L1_CACHE_VADDR_S)
+#define CACHE_L1_CACHE_VADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_VADDR_S  0
+
+/** CACHE_L1_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x268)
+/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 616;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_M  (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S)
+#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_L2_CACHE_CTRL_REG register
+ *  L2 Cache(L2-Cache) control register
+ */
+#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x270)
+/** CACHE_L2_CACHE_SHUT_DMA : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L2_CACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L2_CACHE_SHUT_DMA_M  (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S)
+#define CACHE_L2_CACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L2_CACHE_SHUT_DMA_S  4
+
+/** CACHE_L2_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x274)
+/** CACHE_BYPASS_L2_CACHE_EN : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L2_CACHE_EN    (BIT(5))
+#define CACHE_BYPASS_L2_CACHE_EN_M  (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S)
+#define CACHE_BYPASS_L2_CACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L2_CACHE_EN_S  5
+
+/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register
+ *  L2 Cache CacheSize mode configure register
+ */
+#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x278)
+/** CACHE_L2_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L2_CACHE_CACHESIZE_256_M  (CACHE_L2_CACHE_CACHESIZE_256_V << CACHE_L2_CACHE_CACHESIZE_256_S)
+#define CACHE_L2_CACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256_S  0
+/** CACHE_L2_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L2_CACHE_CACHESIZE_512_M  (CACHE_L2_CACHE_CACHESIZE_512_V << CACHE_L2_CACHE_CACHESIZE_512_S)
+#define CACHE_L2_CACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512_S  1
+/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L2_CACHE_CACHESIZE_1K_M  (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1K_S  2
+/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L2_CACHE_CACHESIZE_2K_M  (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S)
+#define CACHE_L2_CACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_2K_S  3
+/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L2_CACHE_CACHESIZE_4K_M  (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S)
+#define CACHE_L2_CACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_4K_S  4
+/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L2_CACHE_CACHESIZE_8K_M  (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S)
+#define CACHE_L2_CACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_8K_S  5
+/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L2_CACHE_CACHESIZE_16K_M  (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S)
+#define CACHE_L2_CACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_16K_S  6
+/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L2_CACHE_CACHESIZE_32K_M  (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S)
+#define CACHE_L2_CACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_32K_S  7
+/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L2_CACHE_CACHESIZE_64K_M  (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S)
+#define CACHE_L2_CACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_64K_S  8
+/** CACHE_L2_CACHE_CACHESIZE_128K : R/W; bitpos: [9]; default: 1;
+ *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L2_CACHE_CACHESIZE_128K_M  (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S)
+#define CACHE_L2_CACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_128K_S  9
+/** CACHE_L2_CACHE_CACHESIZE_256K : R/W; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L2_CACHE_CACHESIZE_256K_M  (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S)
+#define CACHE_L2_CACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256K_S  10
+/** CACHE_L2_CACHE_CACHESIZE_512K : R/W; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L2_CACHE_CACHESIZE_512K_M  (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S)
+#define CACHE_L2_CACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512K_S  11
+/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L2_CACHE_CACHESIZE_1024K_M  (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register
+ *  L2 Cache BlockSize mode configure register
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x27c)
+/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L2_CACHE_BLOCKSIZE_8_M  (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_8_S  0
+/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L2_CACHE_BLOCKSIZE_16_M  (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_16_S  1
+/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L2_CACHE_BLOCKSIZE_32_M  (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_32_S  2
+/** CACHE_L2_CACHE_BLOCKSIZE_64 : R/W; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L2_CACHE_BLOCKSIZE_64_M  (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_64_S  3
+/** CACHE_L2_CACHE_BLOCKSIZE_128 : R/W; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L2_CACHE_BLOCKSIZE_128_M  (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_128_S  4
+/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L2_CACHE_BLOCKSIZE_256_M  (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x280)
+/** CACHE_L2_CACHE_WRAP : R/W; bitpos: [5]; default: 0;
+ *  Set this bit as 1 to enable L2-Cache wrap around mode.
+ */
+#define CACHE_L2_CACHE_WRAP    (BIT(5))
+#define CACHE_L2_CACHE_WRAP_M  (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S)
+#define CACHE_L2_CACHE_WRAP_V  0x00000001U
+#define CACHE_L2_CACHE_WRAP_S  5
+
+/** CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG register
+ *  Cache tag memory power control register
+ */
+#define CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x284)
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON    (BIT(20))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S  20
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [21]; default: 0;
+ *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD    (BIT(21))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S  21
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [22]; default: 1;
+ *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU    (BIT(22))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S  22
+
+/** CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG register
+ *  Cache data memory power control register
+ */
+#define CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x288)
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON    (BIT(20))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S  20
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [21]; default: 0;
+ *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD    (BIT(21))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S  21
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [22]; default: 1;
+ *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU    (BIT(22))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S  22
+
+/** CACHE_L2_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x28c)
+/** CACHE_L2_CACHE_FREEZE_EN : R/W; bitpos: [20]; default: 0;
+ *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+ *  software.
+ */
+#define CACHE_L2_CACHE_FREEZE_EN    (BIT(20))
+#define CACHE_L2_CACHE_FREEZE_EN_M  (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S)
+#define CACHE_L2_CACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_EN_S  20
+/** CACHE_L2_CACHE_FREEZE_MODE : R/W; bitpos: [21]; default: 0;
+ *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L2_CACHE_FREEZE_MODE    (BIT(21))
+#define CACHE_L2_CACHE_FREEZE_MODE_M  (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S)
+#define CACHE_L2_CACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_MODE_S  21
+/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_FREEZE_DONE    (BIT(22))
+#define CACHE_L2_CACHE_FREEZE_DONE_M  (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S)
+#define CACHE_L2_CACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_DONE_S  22
+
+/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x290)
+/** CACHE_L2_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M  (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [21]; default: 1;
+ *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M  (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x294)
+/** CACHE_L2_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M  (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [21]; default: 1;
+ *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M  (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_PRELOCK_CONF_REG register
+ *  L2 Cache prelock configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x298)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L2-Cache.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L2-Cache.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L2_CACHE_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l2 cache prelock.
+ */
+#define CACHE_L2_CACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_M  (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S)
+#define CACHE_L2_CACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L2 Cache prelock section0 address configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x29c)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L2-Cache, which should be used together with
+ *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L2 Cache prelock section1 address configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2a0)
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L2-Cache, which should be used together with
+ *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register
+ *  L2 Cache prelock section size configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x2a4)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [15:0]; default: 65535;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [31:16]; default: 65535;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register
+ *  L2 Cache preload-operation control register
+ */
+#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a8)
+/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_PRELOAD_ENA_M  (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S)
+#define CACHE_L2_CACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ENA_S  0
+/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_PRELOAD_DONE_M  (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S)
+#define CACHE_L2_CACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_DONE_S  1
+/** CACHE_L2_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_PRELOAD_ORDER_M  (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S)
+#define CACHE_L2_CACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ORDER_S  2
+/** CACHE_L2_CACHE_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l2 cache preload.
+ */
+#define CACHE_L2_CACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_M  (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S)
+#define CACHE_L2_CACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_S  3
+/** CACHE_L2_CACHE_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l2 cache preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L2_CACHE_PRELOAD_MODE    (BIT(7))
+#define CACHE_L2_CACHE_PRELOAD_MODE_M  (CACHE_L2_CACHE_PRELOAD_MODE_V << CACHE_L2_CACHE_PRELOAD_MODE_S)
+#define CACHE_L2_CACHE_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_MODE_S  7
+
+/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register
+ *  L2 Cache preload address configure register
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x2ac)
+/** CACHE_L2_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on L2-Cache,
+ *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_M  (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S)
+#define CACHE_L2_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register
+ *  L2 Cache preload size configure register
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x2b0)
+/** CACHE_L2_CACHE_PRELOAD_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_M  (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S)
+#define CACHE_L2_CACHE_PRELOAD_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register
+ *  L2 Cache autoload-operation control register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2b4)
+/** CACHE_L2_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_M  (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L2_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M  (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+ *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : R/W; bitpos: [10]; default: 0;
+ *  The bit is used to enable the third section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L2_CACHE_AUTOLOAD_RGID : R/W; bitpos: [15:12]; default: 0;
+ *  The bit is used to set  the gid of l2 cache autoload.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_M  (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S)
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L2 Cache autoload section 0 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2b8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L2 Cache autoload section 0 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2bc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L2 Cache autoload section 1 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2c0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L2 Cache autoload section 1 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2c4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L2 Cache autoload section 2 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2c8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the third section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L2 Cache autoload section 2 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2cc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the third section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L2 Cache autoload section 3 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2d0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the fourth section
+ *  for autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L2 Cache autoload section 3 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2d4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the fourth section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d8)
+/** CACHE_L2_IBUS0_OVF_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ENA_M  (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ENA_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ENA_M  (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ENA_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ENA_M  (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ENA_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ENA_M  (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ENA_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ENA_M  (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ENA_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ENA_M  (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ENA_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ENA_M  (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ENA_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ENA_M  (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ENA_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2dc)
+/** CACHE_L2_IBUS0_OVF_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_CLR    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_CLR_M  (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_CLR_S  8
+/** CACHE_L2_IBUS1_OVF_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_CLR    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_CLR_M  (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_CLR_S  9
+/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_CLR    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_CLR_M  (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_CLR_S  10
+/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_CLR    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_CLR_M  (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_CLR_S  11
+/** CACHE_L2_DBUS0_OVF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_CLR    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_CLR_M  (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_CLR_S  12
+/** CACHE_L2_DBUS1_OVF_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_CLR    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_CLR_M  (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_CLR_S  13
+/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_CLR    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_CLR_M  (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_CLR_S  14
+/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_CLR    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_CLR_M  (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_CLR_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2e0)
+/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-ICache0.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_RAW    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_RAW_M  (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_RAW_S  8
+/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-ICache1.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_RAW    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_RAW_M  (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_RAW_S  9
+/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-ICache2.
+ */
+#define CACHE_L2_IBUS2_OVF_INT_RAW    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_RAW_M  (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_RAW_S  10
+/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-ICache3.
+ */
+#define CACHE_L2_IBUS3_OVF_INT_RAW    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_RAW_M  (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_RAW_S  11
+/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_RAW    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_RAW_M  (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_RAW_S  12
+/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_RAW    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_RAW_M  (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_RAW_S  13
+/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS2_OVF_INT_RAW    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_RAW_M  (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_RAW_S  14
+/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS3_OVF_INT_RAW    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_RAW_M  (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_RAW_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2e4)
+/** CACHE_L2_IBUS0_OVF_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ST    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ST_M  (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S)
+#define CACHE_L2_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ST_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ST    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ST_M  (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S)
+#define CACHE_L2_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ST_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ST    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ST_M  (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S)
+#define CACHE_L2_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ST_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ST    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ST_M  (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S)
+#define CACHE_L2_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ST_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ST    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ST_M  (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S)
+#define CACHE_L2_DBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ST_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ST    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ST_M  (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S)
+#define CACHE_L2_DBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ST_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ST    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ST_M  (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S)
+#define CACHE_L2_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ST_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ST    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ST_M  (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S)
+#define CACHE_L2_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ST_S  15
+
+/** CACHE_L2_CACHE_ACS_FAIL_CTRL_REG register
+ *  Cache Access Fail Configuration register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x2e8)
+/** CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to configure l2 cache access fail check mode. 0: the access fail is
+ *  not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE    (BIT(0))
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2ec)
+/** CACHE_L2_CACHE_FAIL_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+ *  l1 cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ENA_M  (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S)
+#define CACHE_L2_CACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ENA_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2f0)
+/** CACHE_L2_CACHE_FAIL_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+ *  cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_CLR_M  (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S)
+#define CACHE_L2_CACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_CLR_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2f4)
+/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_RAW_M  (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S)
+#define CACHE_L2_CACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_RAW_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2f8)
+/** CACHE_L2_CACHE_FAIL_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+ *  to l1 cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ST_M  (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S)
+#define CACHE_L2_CACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ST_S  5
+
+/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2fc)
+/** CACHE_L2_IBUS0_CNT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable ibus0 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS0_CNT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_CNT_ENA_M  (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S)
+#define CACHE_L2_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_ENA_S  8
+/** CACHE_L2_IBUS1_CNT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable ibus1 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS1_CNT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_CNT_ENA_M  (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S)
+#define CACHE_L2_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_ENA_S  9
+/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_CNT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_CNT_ENA_M  (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S)
+#define CACHE_L2_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_ENA_S  10
+/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_CNT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_CNT_ENA_M  (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S)
+#define CACHE_L2_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_ENA_S  11
+/** CACHE_L2_DBUS0_CNT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The bit is used to enable dbus0 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS0_CNT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_CNT_ENA_M  (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S)
+#define CACHE_L2_DBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_ENA_S  12
+/** CACHE_L2_DBUS1_CNT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable dbus1 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS1_CNT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_CNT_ENA_M  (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S)
+#define CACHE_L2_DBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_ENA_S  13
+/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_CNT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_CNT_ENA_M  (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S)
+#define CACHE_L2_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_ENA_S  14
+/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_CNT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_CNT_ENA_M  (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S)
+#define CACHE_L2_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_ENA_S  15
+/** CACHE_L2_IBUS0_CNT_CLR : WT; bitpos: [24]; default: 0;
+ *  The bit is used to clear ibus0 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS0_CNT_CLR    (BIT(24))
+#define CACHE_L2_IBUS0_CNT_CLR_M  (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S)
+#define CACHE_L2_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_CLR_S  24
+/** CACHE_L2_IBUS1_CNT_CLR : WT; bitpos: [25]; default: 0;
+ *  The bit is used to clear ibus1 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS1_CNT_CLR    (BIT(25))
+#define CACHE_L2_IBUS1_CNT_CLR_M  (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S)
+#define CACHE_L2_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_CLR_S  25
+/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_CNT_CLR    (BIT(26))
+#define CACHE_L2_IBUS2_CNT_CLR_M  (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S)
+#define CACHE_L2_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_CLR_S  26
+/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_CNT_CLR    (BIT(27))
+#define CACHE_L2_IBUS3_CNT_CLR_M  (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S)
+#define CACHE_L2_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_CLR_S  27
+/** CACHE_L2_DBUS0_CNT_CLR : WT; bitpos: [28]; default: 0;
+ *  The bit is used to clear dbus0 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS0_CNT_CLR    (BIT(28))
+#define CACHE_L2_DBUS0_CNT_CLR_M  (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S)
+#define CACHE_L2_DBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_CLR_S  28
+/** CACHE_L2_DBUS1_CNT_CLR : WT; bitpos: [29]; default: 0;
+ *  The bit is used to clear dbus1 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS1_CNT_CLR    (BIT(29))
+#define CACHE_L2_DBUS1_CNT_CLR_M  (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S)
+#define CACHE_L2_DBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_CLR_S  29
+/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_CNT_CLR    (BIT(30))
+#define CACHE_L2_DBUS2_CNT_CLR_M  (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S)
+#define CACHE_L2_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_CLR_S  30
+/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_CNT_CLR    (BIT(31))
+#define CACHE_L2_DBUS3_CNT_CLR_M  (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S)
+#define CACHE_L2_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_CLR_S  31
+
+/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x300)
+/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_M  (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S)
+#define CACHE_L2_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x304)
+/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_M  (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S)
+#define CACHE_L2_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x308)
+/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache0 accesses
+ *  L2-Cache due to bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_M  (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x30c)
+/** CACHE_L2_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS0_NXTLVL_RD_CNT_V << CACHE_L2_IBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x310)
+/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_M  (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S)
+#define CACHE_L2_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x314)
+/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_M  (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S)
+#define CACHE_L2_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x318)
+/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache1 accesses
+ *  L2-Cache due to bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_M  (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x31c)
+/** CACHE_L2_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS1_NXTLVL_RD_CNT_V << CACHE_L2_IBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x320)
+/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_M  (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S)
+#define CACHE_L2_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x324)
+/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_M  (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S)
+#define CACHE_L2_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x328)
+/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache2 accesses
+ *  L2-Cache due to bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_M  (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x32c)
+/** CACHE_L2_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS2_NXTLVL_RD_CNT_V << CACHE_L2_IBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x330)
+/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_M  (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S)
+#define CACHE_L2_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x334)
+/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_M  (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S)
+#define CACHE_L2_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x338)
+/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache3 accesses
+ *  L2-Cache due to bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_M  (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x33c)
+/** CACHE_L2_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS3_NXTLVL_RD_CNT_V << CACHE_L2_IBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x340)
+/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_M  (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S)
+#define CACHE_L2_DBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x344)
+/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_M  (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S)
+#define CACHE_L2_DBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x348)
+/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_M  (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x34c)
+/** CACHE_L2_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS0_NXTLVL_RD_CNT_V << CACHE_L2_DBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus0 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x350)
+/** CACHE_L2_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS0_NXTLVL_WR_CNT_V << CACHE_L2_DBUS0_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x354)
+/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_M  (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S)
+#define CACHE_L2_DBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x358)
+/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_M  (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S)
+#define CACHE_L2_DBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x35c)
+/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_M  (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x360)
+/** CACHE_L2_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS1_NXTLVL_RD_CNT_V << CACHE_L2_DBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus1 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x364)
+/** CACHE_L2_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS1_NXTLVL_WR_CNT_V << CACHE_L2_DBUS1_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x368)
+/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_M  (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S)
+#define CACHE_L2_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x36c)
+/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_M  (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S)
+#define CACHE_L2_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x370)
+/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_M  (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x374)
+/** CACHE_L2_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS2_NXTLVL_RD_CNT_V << CACHE_L2_DBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus2 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x378)
+/** CACHE_L2_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS2_NXTLVL_WR_CNT_V << CACHE_L2_DBUS2_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x37c)
+/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_M  (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S)
+#define CACHE_L2_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x380)
+/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_M  (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S)
+#define CACHE_L2_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x384)
+/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_M  (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x388)
+/** CACHE_L2_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS3_NXTLVL_RD_CNT_V << CACHE_L2_DBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus3 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x38c)
+/** CACHE_L2_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS3_NXTLVL_WR_CNT_V << CACHE_L2_DBUS3_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x390)
+/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_M  (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S)
+#define CACHE_L2_CACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_S  0
+/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+ *  due to cache accessing L1-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_M  (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S)
+#define CACHE_L2_CACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_S  16
+
+/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register
+ *  L2-Cache Access Fail Address information register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x394)
+/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_M  (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S)
+#define CACHE_L2_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_S  0
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x398)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x39c)
+/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+ *  is done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x3a0)
+/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+ *  done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+ *  occurs.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x3a4)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+ *  preload-operation is done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M  (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M  (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x3a8)
+/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L2-Cache.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_M  (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S)
+#define CACHE_L2_CACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_S  10
+
+/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3ac)
+/** CACHE_L2_CACHE_SYNC_RST : R/W; bitpos: [5]; default: 0;
+ *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L2_CACHE_SYNC_RST    (BIT(5))
+#define CACHE_L2_CACHE_SYNC_RST_M  (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S)
+#define CACHE_L2_CACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L2_CACHE_SYNC_RST_S  5
+
+/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3b0)
+/** CACHE_L2_CACHE_PLD_RST : R/W; bitpos: [5]; default: 0;
+ *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L2_CACHE_PLD_RST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_RST_M  (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S)
+#define CACHE_L2_CACHE_PLD_RST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_RST_S  5
+
+/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x3b4)
+/** CACHE_L2_CACHE_ALD_BUF_CLR : R/W; bitpos: [5]; default: 0;
+ *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+ *  autoload will not work in L2-Cache. This bit should not be active when autoload
+ *  works in L2-Cache.
+ */
+#define CACHE_L2_CACHE_ALD_BUF_CLR    (BIT(5))
+#define CACHE_L2_CACHE_ALD_BUF_CLR_M  (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S)
+#define CACHE_L2_CACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_ALD_BUF_CLR_S  5
+
+/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b8)
+/** CACHE_L2_CACHE_UNALLOC_CLR : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l2 icache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
+#define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)
+#define CACHE_L2_CACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_UNALLOC_CLR_S  5
+
+/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register
+ *  L2 cache access attribute control register
+ */
+#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x3bc)
+/** CACHE_L2_CACHE_ACCESS_FORCE_CC : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+ *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+ *  non-cacheable.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC    (BIT(0))
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M  (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S  0
+/** CACHE_L2_CACHE_ACCESS_FORCE_WB : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+ *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+ *  write-through.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB    (BIT(1))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M  (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S  1
+/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  write-miss-allocate and write-miss-no-allocate.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA    (BIT(2))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S  2
+/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : R/W; bitpos: [3]; default: 1;
+ *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  read-miss-allocate and read-miss-no-allocate.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA    (BIT(3))
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S  3
+
+/** CACHE_L2_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x3c0)
+/** CACHE_L2_CACHE_TAG_OBJECT : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L2_CACHE_TAG_OBJECT    (BIT(5))
+#define CACHE_L2_CACHE_TAG_OBJECT_M  (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S)
+#define CACHE_L2_CACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_OBJECT_S  5
+/** CACHE_L2_CACHE_MEM_OBJECT : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L2_CACHE_MEM_OBJECT    (BIT(11))
+#define CACHE_L2_CACHE_MEM_OBJECT_M  (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S)
+#define CACHE_L2_CACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_MEM_OBJECT_S  11
+
+/** CACHE_L2_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x3c4)
+/** CACHE_L2_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
+ *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+ *  way1, 2: way2, 3: way3, ?, 7: way7.
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_M  (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S)
+#define CACHE_L2_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L2_CACHE_VADDR_REG register
+ *  Cache Vaddr register
+ */
+#define CACHE_L2_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x3c8)
+/** CACHE_L2_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
+ *  Those bits stores the virtual address which will decide where inside the specified
+ *  tag memory object will be accessed.
+ */
+#define CACHE_L2_CACHE_VADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_VADDR_M  (CACHE_L2_CACHE_VADDR_V << CACHE_L2_CACHE_VADDR_S)
+#define CACHE_L2_CACHE_VADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_VADDR_S  0
+
+/** CACHE_L2_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3cc)
+/** CACHE_L2_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 972;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_M  (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S)
+#define CACHE_L2_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3d4)
+/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable clock gate when access all registers in this module.
+ */
+#define CACHE_CLK_EN    (BIT(0))
+#define CACHE_CLK_EN_M  (CACHE_CLK_EN_V << CACHE_CLK_EN_S)
+#define CACHE_CLK_EN_V  0x00000001U
+#define CACHE_CLK_EN_S  0
+
+/** CACHE_DATE_REG register
+ *  Version control register
+ */
+#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
+/** CACHE_DATE : R/W; bitpos: [27:0]; default: 38810192;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define CACHE_DATE    0x0FFFFFFFU
+#define CACHE_DATE_M  (CACHE_DATE_V << CACHE_DATE_S)
+#define CACHE_DATE_V  0x0FFFFFFFU
+#define CACHE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/cache_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/cache_struct.h
new file mode 100644
index 0000000000..771b04eeee
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/cache_struct.h
@@ -0,0 +1,5840 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of l1_icache_ctrl register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+typedef union {
+    struct {
+        /** l1_icache_shut_ibus0 : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus0:1;
+        /** l1_icache_shut_ibus1 : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus1:1;
+        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus2:1;
+        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus3:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cache_l1_icache_ctrl_reg_t;
+
+/** Type of l1_dcache_ctrl register
+ *  L1 data Cache(L1-DCache) control register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_shut_dbus0 : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable
+         */
+        uint32_t l1_dcache_shut_dbus0:1;
+        /** l1_dcache_shut_dbus1 : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable
+         */
+        uint32_t l1_dcache_shut_dbus1:1;
+        /** l1_dcache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dcache_shut_dbus2:1;
+        /** l1_dcache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dcache_shut_dbus3:1;
+        /** l1_dcache_shut_dma : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable
+         */
+        uint32_t l1_dcache_shut_dma:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_dcache_ctrl_reg_t;
+
+/** Type of l2_cache_ctrl register
+ *  L2 Cache(L2-Cache) control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** l2_cache_shut_dma : R/W; bitpos: [4]; default: 1;
+         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+         */
+        uint32_t l2_cache_shut_dma:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l2_cache_ctrl_reg_t;
+
+
+/** Group: Bypass Cache Control and configuration registers */
+/** Type of l1_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        /** bypass_l1_icache0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache0_en:1;
+        /** bypass_l1_icache1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache1_en:1;
+        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache2_en:1;
+        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache3_en:1;
+        /** bypass_l1_dcache_en : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_dcache_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_bypass_cache_conf_reg_t;
+
+/** Type of l2_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** bypass_l2_cache_en : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l2_cache_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_bypass_cache_conf_reg_t;
+
+
+/** Group: Cache Atomic Control and configuration registers */
+/** Type of l1_cache_atomic_conf register
+ *  L1 Cache atomic feature configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_atomic_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable atomic feature on L1-DCache when multiple cores access
+         *  L1-DCache.  1: disable, 1: enable.
+         */
+        uint32_t l1_dcache_atomic_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_l1_cache_atomic_conf_reg_t;
+
+
+/** Group: Cache Mode Control and configuration registers */
+/** Type of l1_icache_cachesize_conf register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_256:1;
+        /** l1_icache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_512:1;
+        /** l1_icache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1k:1;
+        /** l1_icache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2k:1;
+        /** l1_icache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4k:1;
+        /** l1_icache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_8k:1;
+        /** l1_icache_cachesize_16k : HRO; bitpos: [6]; default: 1;
+         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_16k:1;
+        /** l1_icache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_32k:1;
+        /** l1_icache_cachesize_64k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_64k:1;
+        /** l1_icache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_128k:1;
+        /** l1_icache_cachesize_256k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_256k:1;
+        /** l1_icache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_512k:1;
+        /** l1_icache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_icache_cachesize_conf_reg_t;
+
+/** Type of l1_icache_blocksize_conf register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_8:1;
+        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_16:1;
+        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_32:1;
+        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 1;
+         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_64:1;
+        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_128:1;
+        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache_blocksize_conf_reg_t;
+
+/** Type of l1_dcache_cachesize_conf register
+ *  L1 data Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_256:1;
+        /** l1_dcache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_512:1;
+        /** l1_dcache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_1k:1;
+        /** l1_dcache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_2k:1;
+        /** l1_dcache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_4k:1;
+        /** l1_dcache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_8k:1;
+        /** l1_dcache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_16k:1;
+        /** l1_dcache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_32k:1;
+        /** l1_dcache_cachesize_64k : HRO; bitpos: [8]; default: 1;
+         *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_64k:1;
+        /** l1_dcache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_128k:1;
+        /** l1_dcache_cachesize_256k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_256k:1;
+        /** l1_dcache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_512k:1;
+        /** l1_dcache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_dcache_cachesize_conf_reg_t;
+
+/** Type of l1_dcache_blocksize_conf register
+ *  L1 data Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_8:1;
+        /** l1_dcache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_16:1;
+        /** l1_dcache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_32:1;
+        /** l1_dcache_blocksize_64 : HRO; bitpos: [3]; default: 1;
+         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_64:1;
+        /** l1_dcache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_128:1;
+        /** l1_dcache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_dcache_blocksize_conf_reg_t;
+
+/** Type of l2_cache_cachesize_conf register
+ *  L2 Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_256:1;
+        /** l2_cache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_512:1;
+        /** l2_cache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1k:1;
+        /** l2_cache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2k:1;
+        /** l2_cache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4k:1;
+        /** l2_cache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_8k:1;
+        /** l2_cache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_16k:1;
+        /** l2_cache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_32k:1;
+        /** l2_cache_cachesize_64k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_64k:1;
+        /** l2_cache_cachesize_128k : R/W; bitpos: [9]; default: 1;
+         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_128k:1;
+        /** l2_cache_cachesize_256k : R/W; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_256k:1;
+        /** l2_cache_cachesize_512k : R/W; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_512k:1;
+        /** l2_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_cachesize_conf_reg_t;
+
+/** Type of l2_cache_blocksize_conf register
+ *  L2 Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_8:1;
+        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_16:1;
+        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_32:1;
+        /** l2_cache_blocksize_64 : R/W; bitpos: [3]; default: 1;
+         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_64:1;
+        /** l2_cache_blocksize_128 : R/W; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_128:1;
+        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_blocksize_conf_reg_t;
+
+
+/** Group: Wrap Mode Control and configuration registers */
+/** Type of l1_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_wrap : R/W; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+         */
+        uint32_t l1_icache0_wrap:1;
+        /** l1_icache1_wrap : R/W; bitpos: [1]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+         */
+        uint32_t l1_icache1_wrap:1;
+        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_wrap:1;
+        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_wrap:1;
+        /** l1_dcache_wrap : R/W; bitpos: [4]; default: 0;
+         *  Set this bit as 1 to enable L1-DCache wrap around mode.
+         */
+        uint32_t l1_dcache_wrap:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_wrap_around_ctrl_reg_t;
+
+/** Type of l2_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_wrap : R/W; bitpos: [5]; default: 0;
+         *  Set this bit as 1 to enable L2-Cache wrap around mode.
+         */
+        uint32_t l2_cache_wrap:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_wrap_around_ctrl_reg_t;
+
+
+/** Group: Cache Tag Memory Power Control registers */
+/** Type of l1_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_force_on : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_tag_mem_force_on:1;
+        /** l1_icache0_tag_mem_force_pd : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_tag_mem_force_pd:1;
+        /** l1_icache0_tag_mem_force_pu : R/W; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_tag_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_tag_mem_force_on : R/W; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_tag_mem_force_on:1;
+        /** l1_icache1_tag_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_tag_mem_force_pd:1;
+        /** l1_icache1_tag_mem_force_pu : R/W; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_tag_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_on:1;
+        /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pd:1;
+        /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_on:1;
+        /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pd:1;
+        /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_dcache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-DCache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l1_dcache_tag_mem_force_on:1;
+        /** l1_dcache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_dcache_tag_mem_force_pd:1;
+        /** l1_dcache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_dcache_tag_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_tag_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_force_on : R/W; bitpos: [20]; default: 1;
+         *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_tag_mem_force_on:1;
+        /** l2_cache_tag_mem_force_pd : R/W; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+         */
+        uint32_t l2_cache_tag_mem_force_pd:1;
+        /** l2_cache_tag_mem_force_pu : R/W; bitpos: [22]; default: 1;
+         *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_tag_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_tag_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Power Control registers */
+/** Type of l1_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_force_on : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_data_mem_force_on:1;
+        /** l1_icache0_data_mem_force_pd : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_data_mem_force_pd:1;
+        /** l1_icache0_data_mem_force_pu : R/W; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_data_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_data_mem_force_on : R/W; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_data_mem_force_on:1;
+        /** l1_icache1_data_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_data_mem_force_pd:1;
+        /** l1_icache1_data_mem_force_pu : R/W; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_data_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_on:1;
+        /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pd:1;
+        /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_on:1;
+        /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pd:1;
+        /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_dcache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-DCache data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_dcache_data_mem_force_on:1;
+        /** l1_dcache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_dcache_data_mem_force_pd:1;
+        /** l1_dcache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_dcache_data_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_data_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_force_on : R/W; bitpos: [20]; default: 1;
+         *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_data_mem_force_on:1;
+        /** l2_cache_data_mem_force_pd : R/W; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l2_cache_data_mem_force_pd:1;
+        /** l2_cache_data_mem_force_pu : R/W; bitpos: [22]; default: 1;
+         *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_data_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_data_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Freeze Control registers */
+/** Type of l1_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_freeze_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache0_freeze_en:1;
+        /** l1_icache0_freeze_mode : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache0_freeze_mode:1;
+        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_freeze_done:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_freeze_en : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache1_freeze_en:1;
+        /** l1_icache1_freeze_mode : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache1_freeze_mode:1;
+        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_freeze_done:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_en:1;
+        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_mode:1;
+        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_done:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_en:1;
+        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_mode:1;
+        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_done:1;
+        uint32_t reserved_15:1;
+        /** l1_dcache_freeze_en : R/W; bitpos: [16]; default: 0;
+         *  The bit is used to enable freeze operation on L1-DCache. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_dcache_freeze_en:1;
+        /** l1_dcache_freeze_mode : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_dcache_freeze_mode:1;
+        /** l1_dcache_freeze_done : RO; bitpos: [18]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-DCache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_dcache_freeze_done:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_freeze_ctrl_reg_t;
+
+/** Type of l2_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_freeze_en : R/W; bitpos: [20]; default: 0;
+         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l2_cache_freeze_en:1;
+        /** l2_cache_freeze_mode : R/W; bitpos: [21]; default: 0;
+         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l2_cache_freeze_mode:1;
+        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_freeze_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_freeze_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Access Control and Configuration registers */
+/** Type of l1_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_rd_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_data_mem_rd_en:1;
+        /** l1_icache0_data_mem_wr_en : R/W; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache0_data_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_data_mem_rd_en : R/W; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_data_mem_rd_en:1;
+        /** l1_icache1_data_mem_wr_en : R/W; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache1_data_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_rd_en:1;
+        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_rd_en:1;
+        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_dcache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_dcache_data_mem_rd_en:1;
+        /** l1_dcache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_dcache_data_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} cache_l1_cache_data_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_rd_en : R/W; bitpos: [20]; default: 1;
+         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_rd_en:1;
+        /** l2_cache_data_mem_wr_en : R/W; bitpos: [21]; default: 1;
+         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} cache_l2_cache_data_mem_acs_conf_reg_t;
+
+
+/** Group: Cache Tag Memory Access Control and Configuration registers */
+/** Type of l1_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_rd_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_rd_en:1;
+        /** l1_icache0_tag_mem_wr_en : R/W; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_tag_mem_rd_en : R/W; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_rd_en:1;
+        /** l1_icache1_tag_mem_wr_en : R/W; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_rd_en:1;
+        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_rd_en:1;
+        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_dcache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_dcache_tag_mem_rd_en:1;
+        /** l1_dcache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_dcache_tag_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} cache_l1_cache_tag_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_rd_en : R/W; bitpos: [20]; default: 1;
+         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_rd_en:1;
+        /** l2_cache_tag_mem_wr_en : R/W; bitpos: [21]; default: 1;
+         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} cache_l2_cache_tag_mem_acs_conf_reg_t;
+
+
+/** Group: Prelock Control and configuration registers */
+/** Type of l1_icache0_prelock_conf register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct0_en:1;
+        /** l1_icache0_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct1_en:1;
+        /** l1_icache0_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 prelock.
+         */
+        uint32_t l1_icache0_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_conf_reg_t;
+
+/** Type of l1_icache0_prelock_sct0_addr register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct1_addr register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct_size register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache0_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct_size_reg_t;
+
+/** Type of l1_icache1_prelock_conf register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct0_en:1;
+        /** l1_icache1_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct1_en:1;
+        /** l1_icache1_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 prelock.
+         */
+        uint32_t l1_icache1_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_conf_reg_t;
+
+/** Type of l1_icache1_prelock_sct0_addr register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct1_addr register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct_size register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache1_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct_size_reg_t;
+
+/** Type of l1_icache2_prelock_conf register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct0_en:1;
+        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct1_en:1;
+        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 prelock.
+         */
+        uint32_t l1_icache2_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_conf_reg_t;
+
+/** Type of l1_icache2_prelock_sct0_addr register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct1_addr register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct_size register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct_size_reg_t;
+
+/** Type of l1_icache3_prelock_conf register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct0_en:1;
+        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct1_en:1;
+        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 prelock.
+         */
+        uint32_t l1_icache3_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_conf_reg_t;
+
+/** Type of l1_icache3_prelock_sct0_addr register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct1_addr register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct_size register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct_size_reg_t;
+
+/** Type of l1_dcache_prelock_conf register
+ *  L1 data Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-DCache.
+         */
+        uint32_t l1_dcache_prelock_sct0_en:1;
+        /** l1_dcache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-DCache.
+         */
+        uint32_t l1_dcache_prelock_sct1_en:1;
+        /** l1_dcache_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 dcache prelock.
+         */
+        uint32_t l1_dcache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_conf_reg_t;
+
+/** Type of l1_dcache_prelock_sct0_addr register
+ *  L1 data Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-DCache, which should be used together with
+         *  L1_DCACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_dcache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct0_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct1_addr register
+ *  L1 data Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-DCache, which should be used together with
+         *  L1_DCACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_dcache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct1_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct_size register
+ *  L1 data Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_dcache_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_dcache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_dcache_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct_size_reg_t;
+
+/** Type of l2_cache_prelock_conf register
+ *  L2 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct0_en:1;
+        /** l2_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct1_en:1;
+        /** l2_cache_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l2 cache prelock.
+         */
+        uint32_t l2_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_conf_reg_t;
+
+/** Type of l2_cache_prelock_sct0_addr register
+ *  L2 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct1_addr register
+ *  L2 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct1_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct_size register
+ *  L2 Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_size : R/W; bitpos: [15:0]; default: 65535;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct0_size:16;
+        /** l2_cache_prelock_sct1_size : R/W; bitpos: [31:16]; default: 65535;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct1_size:16;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct_size_reg_t;
+
+
+/** Group: Lock Control and configuration registers */
+/** Type of lock_ctrl register
+ *  Lock-class (manual lock) operation control register
+ */
+typedef union {
+    struct {
+        /** lock_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+         *  operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive,
+         *  that is, those bits can not be set to 1 at the same time. (2) lock operation can be
+         *  applied on LL1-ICache, L1-DCache and L2-Cache.
+         */
+        uint32_t lock_ena:1;
+        /** unlock_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable unlock operation. It will be cleared by hardware after
+         *  unlock operation done. Note that (1) this bit and lock_ena bit are mutually
+         *  exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock
+         *  operation can be applied on L1-ICache, L1-DCache and L2-Cache.
+         */
+        uint32_t unlock_ena:1;
+        /** lock_done : RO; bitpos: [2]; default: 1;
+         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+         *  not finished. 1: finished.
+         */
+        uint32_t lock_done:1;
+        /** lock_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of cache lock/unlock.
+         */
+        uint32_t lock_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_lock_ctrl_reg_t;
+
+/** Type of lock_map register
+ *  Lock (manual lock) map configure register
+ */
+typedef union {
+    struct {
+        /** lock_map : R/W; bitpos: [5:0]; default: 0;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]:
+         *  L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
+         */
+        uint32_t lock_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_lock_map_reg_t;
+
+/** Type of lock_addr register
+ *  Lock (manual lock) address configure register
+ */
+typedef union {
+    struct {
+        /** lock_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the lock/unlock
+         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
+         */
+        uint32_t lock_addr:32;
+    };
+    uint32_t val;
+} cache_lock_addr_reg_t;
+
+/** Type of lock_size register
+ *  Lock (manual lock) size configure register
+ */
+typedef union {
+    struct {
+        /** lock_size : R/W; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the lock/unlock operation, which
+         *  should be used together with CACHE_LOCK_ADDR_REG
+         */
+        uint32_t lock_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_lock_size_reg_t;
+
+
+/** Group: Sync Control and configuration registers */
+/** Type of sync_ctrl register
+ *  Sync-class operation control register
+ */
+typedef union {
+    struct {
+        /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
+         *  The bit is used to enable invalidate operation. It will be cleared by hardware
+         *  after invalidate operation done. Note that this bit and the other sync-bits
+         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t invalidate_ena:1;
+        /** clean_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable clean operation. It will be cleared by hardware after
+         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+         *  bits can not be set to 1 at the same time.
+         */
+        uint32_t clean_ena:1;
+        /** writeback_ena : R/W/SC; bitpos: [2]; default: 0;
+         *  The bit is used to enable writeback operation. It will be cleared by hardware after
+         *  writeback operation done. Note that this bit and the other sync-bits
+         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t writeback_ena:1;
+        /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
+         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+         *  hardware after writeback-invalidate operation done. Note that this bit and the
+         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+         *  that is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t writeback_invalidate_ena:1;
+        /** sync_done : RO; bitpos: [4]; default: 0;
+         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+         */
+        uint32_t sync_done:1;
+        /** sync_rgid : R/W; bitpos: [8:5]; default: 0;
+         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+         *  writeback, writeback_invalidate)
+         */
+        uint32_t sync_rgid:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} cache_sync_ctrl_reg_t;
+
+/** Type of sync_map register
+ *  Sync map configure register
+ */
+typedef union {
+    struct {
+        /** sync_map : R/W; bitpos: [5:0]; default: 31;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]:
+         *  L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
+         */
+        uint32_t sync_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_sync_map_reg_t;
+
+/** Type of sync_addr register
+ *  Sync address configure register
+ */
+typedef union {
+    struct {
+        /** sync_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the sync operation,
+         *  which should be used together with CACHE_SYNC_SIZE_REG
+         */
+        uint32_t sync_addr:32;
+    };
+    uint32_t val;
+} cache_sync_addr_reg_t;
+
+/** Type of sync_size register
+ *  Sync size configure register
+ */
+typedef union {
+    struct {
+        /** sync_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the sync operation, which should be
+         *  used together with CACHE_SYNC_ADDR_REG
+         */
+        uint32_t sync_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_sync_size_reg_t;
+
+
+/** Group: Preload Control and configuration registers */
+/** Type of l1_icache0_preload_ctrl register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache0_preload_ena:1;
+        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache0_preload_done:1;
+        /** l1_icache0_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache0_preload_order:1;
+        /** l1_icache0_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 preload.
+         */
+        uint32_t l1_icache0_preload_rgid:4;
+        /** l1_icache0_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l1 icache0 preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l1_icache0_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_ctrl_reg_t;
+
+/** Type of l1_icache0_preload_addr register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache0_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_addr_reg_t;
+
+/** Type of l1_icache0_preload_size register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache0_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_size_reg_t;
+
+/** Type of l1_icache1_preload_ctrl register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache1_preload_ena:1;
+        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache1_preload_done:1;
+        /** l1_icache1_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache1_preload_order:1;
+        /** l1_icache1_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 preload.
+         */
+        uint32_t l1_icache1_preload_rgid:4;
+        /** l1_icache1_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l1 icache1 preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l1_icache1_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_ctrl_reg_t;
+
+/** Type of l1_icache1_preload_addr register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache1_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_addr_reg_t;
+
+/** Type of l1_icache1_preload_size register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache1_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_size_reg_t;
+
+/** Type of l1_icache2_preload_ctrl register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache2_preload_ena:1;
+        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache2_preload_done:1;
+        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache2_preload_order:1;
+        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 preload.
+         */
+        uint32_t l1_icache2_preload_rgid:4;
+        /** l1_icache2_preload_mode : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l1 icache2 preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l1_icache2_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_ctrl_reg_t;
+
+/** Type of l1_icache2_preload_addr register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache2_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_addr_reg_t;
+
+/** Type of l1_icache2_preload_size register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache2_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_size_reg_t;
+
+/** Type of l1_icache3_preload_ctrl register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache3_preload_ena:1;
+        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache3_preload_done:1;
+        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache3_preload_order:1;
+        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 preload.
+         */
+        uint32_t l1_icache3_preload_rgid:4;
+        /** l1_icache3_preload_mode : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l1 icache3 preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l1_icache3_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_ctrl_reg_t;
+
+/** Type of l1_icache3_preload_addr register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache3_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_addr_reg_t;
+
+/** Type of l1_icache3_preload_size register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache3_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_size_reg_t;
+
+/** Type of l1_dcache_preload_ctrl register
+ *  L1 data Cache  preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-DCache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_dcache_preload_ena:1;
+        /** l1_dcache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_dcache_preload_done:1;
+        /** l1_dcache_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_dcache_preload_order:1;
+        /** l1_dcache_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 dcache preload.
+         */
+        uint32_t l1_dcache_preload_rgid:4;
+        /** l1_dcache_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l1 dcache preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l1_dcache_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_ctrl_reg_t;
+
+/** Type of l1_dcache_preload_addr register
+ *  L1 data Cache  preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L1-DCache,
+         *  which should be used together with L1_DCACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_dcache_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_addr_reg_t;
+
+/** Type of l1_dcache_preload_size register
+ *  L1 data Cache  preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_dcache_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_size_reg_t;
+
+/** Type of l2_cache_preload_ctrl register
+ *  L2 Cache preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l2_cache_preload_ena:1;
+        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l2_cache_preload_done:1;
+        /** l2_cache_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l2_cache_preload_order:1;
+        /** l2_cache_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l2 cache preload.
+         */
+        uint32_t l2_cache_preload_rgid:4;
+        /** l2_cache_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l2 cache preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l2_cache_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_ctrl_reg_t;
+
+/** Type of l2_cache_preload_addr register
+ *  L2 Cache preload address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L2-Cache,
+         *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l2_cache_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_addr_reg_t;
+
+/** Type of l2_cache_preload_size register
+ *  L2 Cache preload size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_size : R/W; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l2_cache_preload_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_size_reg_t;
+
+
+/** Group: Autoload Control and configuration registers */
+/** Type of l1_icache0_autoload_ctrl register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache0_autoload_ena:1;
+        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_autoload_done:1;
+        /** l1_icache0_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache0_autoload_order:1;
+        /** l1_icache0_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache0_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache0_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct0_ena:1;
+        /** l1_icache0_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct1_ena:1;
+        /** l1_icache0_autoload_rgid : R/W; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 autoload.
+         */
+        uint32_t l1_icache0_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_ctrl_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_addr register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_size register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_addr register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_size register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache1_autoload_ctrl register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache1_autoload_ena:1;
+        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_autoload_done:1;
+        /** l1_icache1_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache1_autoload_order:1;
+        /** l1_icache1_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache1_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache1_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct0_ena:1;
+        /** l1_icache1_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct1_ena:1;
+        /** l1_icache1_autoload_rgid : R/W; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 autoload.
+         */
+        uint32_t l1_icache1_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_ctrl_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_addr register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_size register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_addr register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_size register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache2_autoload_ctrl register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache2_autoload_ena:1;
+        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache2_autoload_done:1;
+        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache2_autoload_order:1;
+        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache2_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct0_ena:1;
+        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct1_ena:1;
+        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 autoload.
+         */
+        uint32_t l1_icache2_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_ctrl_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_addr register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_size register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_addr register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_size register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache3_autoload_ctrl register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache3_autoload_ena:1;
+        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache3_autoload_done:1;
+        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache3_autoload_order:1;
+        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache3_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct0_ena:1;
+        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct1_ena:1;
+        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 autoload.
+         */
+        uint32_t l1_icache3_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_ctrl_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_addr register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_size register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_addr register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_size register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct1_size_reg_t;
+
+/** Type of l1_dcache_autoload_ctrl register
+ *  L1 data Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-DCache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_dcache_autoload_ena:1;
+        /** l1_dcache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-DCache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_dcache_autoload_done:1;
+        /** l1_dcache_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-DCache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_dcache_autoload_order:1;
+        /** l1_dcache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-DCache.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_dcache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_dcache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-DCache.
+         */
+        uint32_t l1_dcache_autoload_sct0_ena:1;
+        /** l1_dcache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-DCache.
+         */
+        uint32_t l1_dcache_autoload_sct1_ena:1;
+        /** l1_dcache_autoload_sct2_ena : R/W; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L1-DCache.
+         */
+        uint32_t l1_dcache_autoload_sct2_ena:1;
+        /** l1_dcache_autoload_sct3_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L1-DCache.
+         */
+        uint32_t l1_dcache_autoload_sct3_ena:1;
+        /** l1_dcache_autoload_rgid : R/W; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l1 dcache autoload.
+         */
+        uint32_t l1_dcache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_ctrl_reg_t;
+
+/** Type of l1_dcache_autoload_sct0_addr register
+ *  L1 data Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct0_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct0_size register
+ *  L1 data Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct0_size_reg_t;
+
+/** Type of l1_dcache_autoload_sct1_addr register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct1_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct1_size register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct1_size_reg_t;
+
+/** Type of l1_dcache_autoload_sct2_addr register
+ *  L1 data Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct2_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct2_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct2_size register
+ *  L1 data Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct2_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct2_size_reg_t;
+
+/** Type of l1_dcache_autoload_sct3_addr register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct3_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct3_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct3_size register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct3_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct3_size_reg_t;
+
+/** Type of l2_cache_autoload_ctrl register
+ *  L2 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l2_cache_autoload_ena:1;
+        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_autoload_done:1;
+        /** l2_cache_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l2_cache_autoload_order:1;
+        /** l2_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l2_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l2_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct0_ena:1;
+        /** l2_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct1_ena:1;
+        /** l2_cache_autoload_sct2_ena : R/W; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct2_ena:1;
+        /** l2_cache_autoload_sct3_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct3_ena:1;
+        /** l2_cache_autoload_rgid : R/W; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l2 cache autoload.
+         */
+        uint32_t l2_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_sct0_addr register
+ *  L2 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct0_size register
+ *  L2 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct0_size_reg_t;
+
+/** Type of l2_cache_autoload_sct1_addr register
+ *  L2 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct1_size register
+ *  L2 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct1_size_reg_t;
+
+/** Type of l2_cache_autoload_sct2_addr register
+ *  L2 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct2_size register
+ *  L2 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct2_size_reg_t;
+
+/** Type of l2_cache_autoload_sct3_addr register
+ *  L2 Cache autoload section 3 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct3_size register
+ *  L2 Cache autoload section 3 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct3_size_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of l1_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_ena:1;
+        /** l1_ibus1_ovf_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_ena:1;
+        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_ena:1;
+        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_ena:1;
+        /** l1_dbus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_ena:1;
+        /** l1_dbus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_ena:1;
+        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_ena:1;
+        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_clr : WT; bitpos: [0]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+         *  to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_clr:1;
+        /** l1_ibus1_ovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+         *  to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_clr:1;
+        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_clr:1;
+        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_clr:1;
+        /** l1_dbus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_clr:1;
+        /** l1_dbus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_clr:1;
+        /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_clr:1;
+        /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+         *  due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_raw:1;
+        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+         *  due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_raw:1;
+        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+         *  due to bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_ovf_int_raw:1;
+        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+         *  due to bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_ovf_int_raw:1;
+        /** l1_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_raw:1;
+        /** l1_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_raw:1;
+        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_ovf_int_raw:1;
+        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_ovf_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_st : RO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_st:1;
+        /** l1_ibus1_ovf_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_st:1;
+        /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_st:1;
+        /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_st:1;
+        /** l1_dbus0_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_st:1;
+        /** l1_dbus1_ovf_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_st:1;
+        /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_st:1;
+        /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l1_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_ena:1;
+        /** l1_icache1_fail_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_ena:1;
+        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_ena:1;
+        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_ena:1;
+        /** l1_dcache_fail_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l1_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_clr : WT; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_clr:1;
+        /** l1_icache1_fail_int_clr : WT; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_clr:1;
+        /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_clr:1;
+        /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_clr:1;
+        /** l1_dcache_fail_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l1_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_raw:1;
+        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_raw:1;
+        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+         */
+        uint32_t l1_icache2_fail_int_raw:1;
+        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+         */
+        uint32_t l1_icache3_fail_int_raw:1;
+        /** l1_dcache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l1_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_st : RO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_int_st:1;
+        /** l1_icache1_fail_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_int_st:1;
+        /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_st:1;
+        /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_st:1;
+        /** l1_dcache_fail_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+         *  to cpu accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_st_reg_t;
+
+/** Type of sync_l1_cache_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache0_pld_done_int_ena:1;
+        /** l1_icache1_pld_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache1_pld_done_int_ena:1;
+        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_ena:1;
+        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_ena:1;
+        /** l1_dcache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of L1-DCache preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_dcache_pld_done_int_ena:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation done.
+         */
+        uint32_t sync_done_int_ena:1;
+        /** l1_icache0_pld_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_ena:1;
+        /** l1_icache1_pld_err_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_ena:1;
+        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_ena:1;
+        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_ena:1;
+        /** l1_dcache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable interrupt of L1-DCache preload-operation error.
+         */
+        uint32_t l1_dcache_pld_err_int_ena:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_sync_l1_cache_preload_int_ena_reg_t;
+
+/** Type of sync_l1_cache_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_clr:1;
+        /** l1_icache1_pld_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_clr:1;
+        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_clr:1;
+        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_clr:1;
+        /** l1_dcache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-DCache
+         *  preload-operation is done.
+         */
+        uint32_t l1_dcache_pld_done_int_clr:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_clr : WT; bitpos: [6]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+         *  done.
+         */
+        uint32_t sync_done_int_clr:1;
+        /** l1_icache0_pld_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_clr:1;
+        /** l1_icache1_pld_err_int_clr : WT; bitpos: [8]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_clr:1;
+        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_clr:1;
+        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_clr:1;
+        /** l1_dcache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
+         *  The bit is used to clear interrupt of L1-DCache preload-operation error.
+         */
+        uint32_t l1_dcache_pld_err_int_clr:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_sync_l1_cache_preload_int_clr_reg_t;
+
+/** Type of sync_l1_cache_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache0_pld_done_int_raw:1;
+        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache1_pld_done_int_raw:1;
+        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_raw:1;
+        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_raw:1;
+        /** l1_dcache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation is
+         *  done.
+         */
+        uint32_t l1_dcache_pld_done_int_raw:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+         */
+        uint32_t sync_done_int_raw:1;
+        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache0_pld_err_int_raw:1;
+        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache1_pld_err_int_raw:1;
+        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_raw:1;
+        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_raw:1;
+        /** l1_dcache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_dcache_pld_err_int_raw:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+         *  occurs.
+         */
+        uint32_t sync_err_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_sync_l1_cache_preload_int_raw_reg_t;
+
+/** Type of sync_l1_cache_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_st:1;
+        /** l1_icache1_pld_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_st:1;
+        /** l1_icache2_pld_done_int_st : RO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_st:1;
+        /** l1_icache3_pld_done_int_st : RO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_st:1;
+        /** l1_dcache_pld_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-DCache
+         *  preload-operation is done.
+         */
+        uint32_t l1_dcache_pld_done_int_st:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_st : RO; bitpos: [6]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when Cache
+         *  sync-operation is done.
+         */
+        uint32_t sync_done_int_st:1;
+        /** l1_icache0_pld_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_st:1;
+        /** l1_icache1_pld_err_int_st : RO; bitpos: [8]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_st:1;
+        /** l1_icache2_pld_err_int_st : RO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_st:1;
+        /** l1_icache3_pld_err_int_st : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_st:1;
+        /** l1_dcache_pld_err_int_st : RO; bitpos: [11]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-DCache preload-operation error.
+         */
+        uint32_t l1_dcache_pld_err_int_st:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the status of the interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_sync_l1_cache_preload_int_st_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_ena:1;
+        /** l2_ibus1_ovf_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_ena:1;
+        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_ena:1;
+        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_ena:1;
+        /** l2_dbus0_ovf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_ena:1;
+        /** l2_dbus1_ovf_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_ena:1;
+        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_ena:1;
+        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_clr : WT; bitpos: [8]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_clr:1;
+        /** l2_ibus1_ovf_int_clr : WT; bitpos: [9]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_clr:1;
+        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_clr:1;
+        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_clr:1;
+        /** l2_dbus0_ovf_int_clr : WT; bitpos: [12]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_clr:1;
+        /** l2_dbus1_ovf_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_clr:1;
+        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_clr:1;
+        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-ICache0.
+         */
+        uint32_t l2_ibus0_ovf_int_raw:1;
+        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-ICache1.
+         */
+        uint32_t l2_ibus1_ovf_int_raw:1;
+        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-ICache2.
+         */
+        uint32_t l2_ibus2_ovf_int_raw:1;
+        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-ICache3.
+         */
+        uint32_t l2_ibus3_ovf_int_raw:1;
+        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-DCache.
+         */
+        uint32_t l2_dbus0_ovf_int_raw:1;
+        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-DCache.
+         */
+        uint32_t l2_dbus1_ovf_int_raw:1;
+        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-DCache.
+         */
+        uint32_t l2_dbus2_ovf_int_raw:1;
+        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-DCache.
+         */
+        uint32_t l2_dbus3_ovf_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_st : RO; bitpos: [8]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_st:1;
+        /** l2_ibus1_ovf_int_st : RO; bitpos: [9]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_st:1;
+        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_st:1;
+        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_st:1;
+        /** l2_dbus0_ovf_int_st : RO; bitpos: [12]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_st:1;
+        /** l2_dbus1_ovf_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_st:1;
+        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_st:1;
+        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l2_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+         *  l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l2_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+         *  cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l2_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l2_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+         *  to l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_st_reg_t;
+
+/** Type of l2_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+         */
+        uint32_t l2_cache_pld_done_int_ena:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l2_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l2_cache_pld_done_int_clr:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_clr : WT; bitpos: [12]; default: 0;
+         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l2_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l2_cache_pld_done_int_raw:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_err_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l2_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l2_cache_pld_done_int_st:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_st : RO; bitpos: [12]; default: 0;
+         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_st_reg_t;
+
+
+/** Group: Cache Access Fail Configuration register */
+/** Type of l1_cache_acs_fail_ctrl register
+ *  Cache Access Fail Configuration register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_acs_fail_check_mode : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to configure l1 icache0 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache0_acs_fail_check_mode:1;
+        /** l1_icache1_acs_fail_check_mode : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to configure l1 icache1 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache1_acs_fail_check_mode:1;
+        /** l1_icache2_acs_fail_check_mode : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure l1 icache2 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache2_acs_fail_check_mode:1;
+        /** l1_icache3_acs_fail_check_mode : R/W; bitpos: [3]; default: 0;
+         *  The bit is used to configure l1 icache3 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache3_acs_fail_check_mode:1;
+        /** l1_dcache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to configure l1 dcache access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_dcache_acs_fail_check_mode:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_ctrl_reg_t;
+
+/** Type of l2_cache_acs_fail_ctrl register
+ *  Cache Access Fail Configuration register
+ */
+typedef union {
+    struct {
+        /** l2_cache_acs_fail_check_mode : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to configure l2 cache access fail check mode. 0: the access fail is
+         *  not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l2_cache_acs_fail_check_mode:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_ctrl_reg_t;
+
+
+/** Group: Access Statistics registers */
+/** Type of l1_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_cnt_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_ena:1;
+        /** l1_ibus1_cnt_ena : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_ena:1;
+        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_ena:1;
+        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_ena:1;
+        /** l1_dbus0_cnt_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_dbus0_cnt_ena:1;
+        /** l1_dbus1_cnt_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_dbus1_cnt_ena:1;
+        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_ena:1;
+        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_ena:1;
+        uint32_t reserved_8:8;
+        /** l1_ibus0_cnt_clr : WT; bitpos: [16]; default: 0;
+         *  The bit is used to clear ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_clr:1;
+        /** l1_ibus1_cnt_clr : WT; bitpos: [17]; default: 0;
+         *  The bit is used to clear ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_clr:1;
+        /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_clr:1;
+        /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_clr:1;
+        /** l1_dbus0_cnt_clr : WT; bitpos: [20]; default: 0;
+         *  The bit is used to clear dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_dbus0_cnt_clr:1;
+        /** l1_dbus1_cnt_clr : WT; bitpos: [21]; default: 0;
+         *  The bit is used to clear dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_dbus1_cnt_clr:1;
+        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_clr:1;
+        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_clr:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l1_ibus0_acs_hit_cnt register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_miss_cnt register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_conflict_cnt register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l1_ibus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_hit_cnt register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_miss_cnt register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_conflict_cnt register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l1_ibus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_hit_cnt register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_miss_cnt register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_conflict_cnt register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l1_ibus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_hit_cnt register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_miss_cnt register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_conflict_cnt register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l1_ibus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_hit_cnt register
+ *  L1-DCache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_miss_cnt register
+ *  L1-DCache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_conflict_cnt register
+ *  L1-DCache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l1_dbus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus0 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_hit_cnt register
+ *  L1-DCache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_miss_cnt register
+ *  L1-DCache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_conflict_cnt register
+ *  L1-DCache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l1_dbus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus1 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_hit_cnt register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_miss_cnt register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_conflict_cnt register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l1_dbus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus2 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_hit_cnt register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_miss_cnt register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_conflict_cnt register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l1_dbus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus3 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_cnt_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_ena:1;
+        /** l2_ibus1_cnt_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_ena:1;
+        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_ena:1;
+        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_ena:1;
+        /** l2_dbus0_cnt_ena : R/W; bitpos: [12]; default: 0;
+         *  The bit is used to enable dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_ena:1;
+        /** l2_dbus1_cnt_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_ena:1;
+        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_ena:1;
+        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_ena:1;
+        uint32_t reserved_16:8;
+        /** l2_ibus0_cnt_clr : WT; bitpos: [24]; default: 0;
+         *  The bit is used to clear ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_clr:1;
+        /** l2_ibus1_cnt_clr : WT; bitpos: [25]; default: 0;
+         *  The bit is used to clear ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_clr:1;
+        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_clr:1;
+        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_clr:1;
+        /** l2_dbus0_cnt_clr : WT; bitpos: [28]; default: 0;
+         *  The bit is used to clear dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_clr:1;
+        /** l2_dbus1_cnt_clr : WT; bitpos: [29]; default: 0;
+         *  The bit is used to clear dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_clr:1;
+        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_clr:1;
+        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_clr:1;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l2_ibus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache0 accesses
+         *  L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache1 accesses
+         *  L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache2 accesses
+         *  L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache3 accesses
+         *  L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus0 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus1 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus2 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus3 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t;
+
+
+/** Group: Access Fail Debug registers */
+/** Type of l1_icache0_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_id:16;
+        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache0_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache0_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_acs_fail_addr_reg_t;
+
+/** Type of l1_icache1_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_id:16;
+        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache1_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache1_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_acs_fail_addr_reg_t;
+
+/** Type of l1_icache2_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_id:16;
+        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache2_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache2_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_acs_fail_addr_reg_t;
+
+/** Type of l1_icache3_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_id:16;
+        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache3_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache3_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_acs_fail_addr_reg_t;
+
+/** Type of l1_dcache_acs_fail_id_attr register
+ *  L1-DCache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_id:16;
+        /** l1_dcache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_dcache_acs_fail_id_attr_reg_t;
+
+/** Type of l1_dcache_acs_fail_addr register
+ *  L1-DCache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_acs_fail_addr_reg_t;
+
+/** Type of l2_cache_acs_fail_id_attr register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_id:16;
+        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+         *  due to cache accessing L1-Cache.
+         */
+        uint32_t l2_cache_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l2_cache_acs_fail_addr register
+ *  L2-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_addr_reg_t;
+
+
+/** Group: Operation Exception registers */
+/** Type of sync_l1_cache_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache0.
+         */
+        uint32_t l1_icache0_pld_err_code:2;
+        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache1.
+         */
+        uint32_t l1_icache1_pld_err_code:2;
+        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_code:2;
+        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_code:2;
+        /** l1_dcache_pld_err_code : RO; bitpos: [9:8]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-DCache.
+         */
+        uint32_t l1_dcache_pld_err_code:2;
+        uint32_t reserved_10:2;
+        /** sync_err_code : RO; bitpos: [13:12]; default: 0;
+         *  The values 0-2 are available which means sync map, command conflict and size are
+         *  error in Cache System.
+         */
+        uint32_t sync_err_code:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_sync_l1_cache_preload_exception_reg_t;
+
+/** Type of l2_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L2-Cache.
+         */
+        uint32_t l2_cache_pld_err_code:2;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_exception_reg_t;
+
+
+/** Group: Sync Reset control and configuration registers */
+/** Type of l1_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_sync_rst : R/W; bitpos: [0]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache0_sync_rst:1;
+        /** l1_icache1_sync_rst : R/W; bitpos: [1]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache1_sync_rst:1;
+        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_sync_rst:1;
+        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_sync_rst:1;
+        /** l1_dcache_sync_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset sync-logic inside L1-DCache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_dcache_sync_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_rst_ctrl_reg_t;
+
+/** Type of l2_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_sync_rst : R/W; bitpos: [5]; default: 0;
+         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l2_cache_sync_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_rst_ctrl_reg_t;
+
+
+/** Group: Preload Reset control and configuration registers */
+/** Type of l1_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_rst : R/W; bitpos: [0]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache0_pld_rst:1;
+        /** l1_icache1_pld_rst : R/W; bitpos: [1]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache1_pld_rst:1;
+        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_rst:1;
+        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_rst:1;
+        /** l1_dcache_pld_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset preload-logic inside L1-DCache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_dcache_pld_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_preload_rst_ctrl_reg_t;
+
+/** Type of l2_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_rst : R/W; bitpos: [5]; default: 0;
+         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_rst_ctrl_reg_t;
+
+
+/** Group: Autoload buffer clear control and configuration registers */
+/** Type of l1_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_ald_buf_clr : R/W; bitpos: [0]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+         *  works in L1-ICache0.
+         */
+        uint32_t l1_icache0_ald_buf_clr:1;
+        /** l1_icache1_ald_buf_clr : R/W; bitpos: [1]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+         *  works in L1-ICache1.
+         */
+        uint32_t l1_icache1_ald_buf_clr:1;
+        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_ald_buf_clr:1;
+        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_ald_buf_clr:1;
+        /** l1_dcache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-DCache. If this bit is active,
+         *  autoload will not work in L1-DCache. This bit should not be active when autoload
+         *  works in L1-DCache.
+         */
+        uint32_t l1_dcache_ald_buf_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_buf_clr_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_ald_buf_clr : R/W; bitpos: [5]; default: 0;
+         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+         *  autoload will not work in L2-Cache. This bit should not be active when autoload
+         *  works in L2-Cache.
+         */
+        uint32_t l2_cache_ald_buf_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_buf_clr_ctrl_reg_t;
+
+
+/** Group: Unallocate request buffer clear registers */
+/** Type of l1_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        /** l1_icache0_unalloc_clr : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache0_unalloc_clr:1;
+        /** l1_icache1_unalloc_clr : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache1_unalloc_clr:1;
+        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_unalloc_clr:1;
+        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_unalloc_clr:1;
+        /** l1_dcache_unalloc_clr : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 dcache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_dcache_unalloc_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_unallocate_buffer_clear_reg_t;
+
+/** Type of l2_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_unalloc_clr : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l2 icache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l2_cache_unalloc_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_unallocate_buffer_clear_reg_t;
+
+
+/** Group: Tag and Data Memory Access Control and configuration register */
+/** Type of l1_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_object : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache0_tag_object:1;
+        /** l1_icache1_tag_object : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache1_tag_object:1;
+        /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_object:1;
+        /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_object:1;
+        /** l1_dcache_tag_object : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to set L1-DCache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_dcache_tag_object:1;
+        uint32_t reserved_5:1;
+        /** l1_icache0_mem_object : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache0_mem_object:1;
+        /** l1_icache1_mem_object : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache1_mem_object:1;
+        /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_mem_object:1;
+        /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_mem_object:1;
+        /** l1_dcache_mem_object : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to set L1-DCache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_dcache_mem_object:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} cache_l1_cache_object_ctrl_reg_t;
+
+/** Type of l1_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l1_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cache_l1_cache_way_object_reg_t;
+
+/** Type of l1_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l1_cache_vaddr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_vaddr_reg_t;
+
+/** Type of l1_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 616;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l1_cache_debug_bus:32;
+    };
+    uint32_t val;
+} cache_l1_cache_debug_bus_reg_t;
+
+/** Type of l2_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_tag_object : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_tag_object:1;
+        uint32_t reserved_6:5;
+        /** l2_cache_mem_object : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_mem_object:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l2_cache_object_ctrl_reg_t;
+
+/** Type of l2_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l2_cache_way_object : R/W; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l2_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cache_l2_cache_way_object_reg_t;
+
+/** Type of l2_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l2_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l2_cache_vaddr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_vaddr_reg_t;
+
+/** Type of l2_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l2_cache_debug_bus : R/W; bitpos: [31:0]; default: 972;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l2_cache_debug_bus:32;
+    };
+    uint32_t val;
+} cache_l2_cache_debug_bus_reg_t;
+
+
+/** Group: L2 cache access attribute control register */
+/** Type of l2_cache_access_attr_ctrl register
+ *  L2 cache access attribute control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_access_force_cc : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+         *  non-cacheable.
+         */
+        uint32_t l2_cache_access_force_cc:1;
+        /** l2_cache_access_force_wb : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+         *  write-through.
+         */
+        uint32_t l2_cache_access_force_wb:1;
+        /** l2_cache_access_force_wma : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  write-miss-allocate and write-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_wma:1;
+        /** l2_cache_access_force_rma : R/W; bitpos: [3]; default: 1;
+         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  read-miss-allocate and read-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_rma:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cache_l2_cache_access_attr_ctrl_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38810192;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_date_reg_t;
+
+
+typedef struct {
+    volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl;
+    volatile cache_l1_dcache_ctrl_reg_t l1_dcache_ctrl;
+    volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
+    volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
+    volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
+    volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
+    volatile cache_l1_dcache_cachesize_conf_reg_t l1_dcache_cachesize_conf;
+    volatile cache_l1_dcache_blocksize_conf_reg_t l1_dcache_blocksize_conf;
+    volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
+    volatile cache_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
+    volatile cache_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
+    volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
+    volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
+    volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
+    volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
+    volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
+    volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
+    volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
+    volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
+    volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
+    volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
+    volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
+    volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
+    volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
+    volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
+    volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
+    volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
+    volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
+    volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
+    volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
+    volatile cache_l1_dcache_prelock_conf_reg_t l1_dcache_prelock_conf;
+    volatile cache_l1_dcache_prelock_sct0_addr_reg_t l1_dcache_prelock_sct0_addr;
+    volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
+    volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
+    volatile cache_lock_ctrl_reg_t lock_ctrl;
+    volatile cache_lock_map_reg_t lock_map;
+    volatile cache_lock_addr_reg_t lock_addr;
+    volatile cache_lock_size_reg_t lock_size;
+    volatile cache_sync_ctrl_reg_t sync_ctrl;
+    volatile cache_sync_map_reg_t sync_map;
+    volatile cache_sync_addr_reg_t sync_addr;
+    volatile cache_sync_size_reg_t sync_size;
+    volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
+    volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
+    volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
+    volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
+    volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
+    volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
+    volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
+    volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
+    volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
+    volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
+    volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
+    volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
+    volatile cache_l1_dcache_preload_ctrl_reg_t l1_dcache_preload_ctrl;
+    volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
+    volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
+    volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
+    volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
+    volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
+    volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
+    volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
+    volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
+    volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
+    volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
+    volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
+    volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
+    volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
+    volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
+    volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
+    volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
+    volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
+    volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
+    volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
+    volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
+    volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
+    volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
+    volatile cache_l1_dcache_autoload_ctrl_reg_t l1_dcache_autoload_ctrl;
+    volatile cache_l1_dcache_autoload_sct0_addr_reg_t l1_dcache_autoload_sct0_addr;
+    volatile cache_l1_dcache_autoload_sct0_size_reg_t l1_dcache_autoload_sct0_size;
+    volatile cache_l1_dcache_autoload_sct1_addr_reg_t l1_dcache_autoload_sct1_addr;
+    volatile cache_l1_dcache_autoload_sct1_size_reg_t l1_dcache_autoload_sct1_size;
+    volatile cache_l1_dcache_autoload_sct2_addr_reg_t l1_dcache_autoload_sct2_addr;
+    volatile cache_l1_dcache_autoload_sct2_size_reg_t l1_dcache_autoload_sct2_size;
+    volatile cache_l1_dcache_autoload_sct3_addr_reg_t l1_dcache_autoload_sct3_addr;
+    volatile cache_l1_dcache_autoload_sct3_size_reg_t l1_dcache_autoload_sct3_size;
+    volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
+    volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
+    volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
+    volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
+    volatile cache_l1_cache_acs_fail_ctrl_reg_t l1_cache_acs_fail_ctrl;
+    volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
+    volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
+    volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
+    volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
+    volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
+    volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
+    volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
+    volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
+    volatile cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t l1_ibus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
+    volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
+    volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
+    volatile cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t l1_ibus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
+    volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
+    volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
+    volatile cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t l1_ibus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
+    volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
+    volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
+    volatile cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t l1_ibus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus0_acs_hit_cnt_reg_t l1_dbus0_acs_hit_cnt;
+    volatile cache_l1_dbus0_acs_miss_cnt_reg_t l1_dbus0_acs_miss_cnt;
+    volatile cache_l1_dbus0_acs_conflict_cnt_reg_t l1_dbus0_acs_conflict_cnt;
+    volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus1_acs_hit_cnt_reg_t l1_dbus1_acs_hit_cnt;
+    volatile cache_l1_dbus1_acs_miss_cnt_reg_t l1_dbus1_acs_miss_cnt;
+    volatile cache_l1_dbus1_acs_conflict_cnt_reg_t l1_dbus1_acs_conflict_cnt;
+    volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
+    volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
+    volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
+    volatile cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t l1_dbus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t l1_dbus2_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
+    volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
+    volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
+    volatile cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t l1_dbus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t l1_dbus3_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
+    volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
+    volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
+    volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
+    volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
+    volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
+    volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
+    volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
+    volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr;
+    volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
+    volatile cache_sync_l1_cache_preload_int_ena_reg_t sync_l1_cache_preload_int_ena;
+    volatile cache_sync_l1_cache_preload_int_clr_reg_t sync_l1_cache_preload_int_clr;
+    volatile cache_sync_l1_cache_preload_int_raw_reg_t sync_l1_cache_preload_int_raw;
+    volatile cache_sync_l1_cache_preload_int_st_reg_t sync_l1_cache_preload_int_st;
+    volatile cache_sync_l1_cache_preload_exception_reg_t sync_l1_cache_preload_exception;
+    volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
+    volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
+    volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
+    volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
+    volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
+    volatile cache_l1_cache_way_object_reg_t l1_cache_way_object;
+    volatile cache_l1_cache_vaddr_reg_t l1_cache_vaddr;
+    volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
+    uint32_t reserved_26c;
+    volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl;
+    volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
+    volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
+    volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
+    volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
+    volatile cache_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl;
+    volatile cache_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl;
+    volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
+    volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
+    volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
+    volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
+    volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
+    volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
+    volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
+    volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
+    volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
+    volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size;
+    volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
+    volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
+    volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
+    volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
+    volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
+    volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
+    volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
+    volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
+    volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
+    volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
+    volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
+    volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
+    volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
+    volatile cache_l2_cache_acs_fail_ctrl_reg_t l2_cache_acs_fail_ctrl;
+    volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
+    volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
+    volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
+    volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
+    volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
+    volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
+    volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
+    volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
+    volatile cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t l2_ibus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
+    volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
+    volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
+    volatile cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t l2_ibus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
+    volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
+    volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
+    volatile cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t l2_ibus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
+    volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
+    volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
+    volatile cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t l2_ibus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
+    volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
+    volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
+    volatile cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t l2_dbus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t l2_dbus0_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
+    volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
+    volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
+    volatile cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t l2_dbus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t l2_dbus1_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
+    volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
+    volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
+    volatile cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t l2_dbus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t l2_dbus2_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
+    volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
+    volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
+    volatile cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t l2_dbus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t l2_dbus3_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
+    volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
+    volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
+    volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
+    volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
+    volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
+    volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
+    volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
+    volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
+    volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
+    volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
+    volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
+    volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
+    volatile cache_l2_cache_way_object_reg_t l2_cache_way_object;
+    volatile cache_l2_cache_vaddr_reg_t l2_cache_vaddr;
+    volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
+    uint32_t reserved_3d0;
+    volatile cache_clock_gate_reg_t clock_gate;
+    uint32_t reserved_3d8[9];
+    volatile cache_date_reg_t date;
+} cache_dev_t;
+
+extern cache_dev_t CACHE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h
new file mode 100644
index 0000000000..3077ad0e45
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h
@@ -0,0 +1,7537 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DMA2D_OUT_CONF0_CH0_REG register
+ *  Configures the tx direction of channel 0
+ */
+#define DMA2D_OUT_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x0)
+/** DMA2D_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH0    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH0_M  (DMA2D_OUT_AUTO_WRBACK_CH0_V << DMA2D_OUT_AUTO_WRBACK_CH0_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH0_S  0
+/** DMA2D_OUT_EOF_MODE_CH0 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH0    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH0_M  (DMA2D_OUT_EOF_MODE_CH0_V << DMA2D_OUT_EOF_MODE_CH0_S)
+#define DMA2D_OUT_EOF_MODE_CH0_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH0_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH0    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH0_M  (DMA2D_OUTDSCR_BURST_EN_CH0_V << DMA2D_OUTDSCR_BURST_EN_CH0_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH0_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH0    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH0_M  (DMA2D_OUT_ECC_AES_EN_CH0_V << DMA2D_OUT_ECC_AES_EN_CH0_S)
+#define DMA2D_OUT_ECC_AES_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH0_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH0    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH0_M  (DMA2D_OUT_CHECK_OWNER_CH0_V << DMA2D_OUT_CHECK_OWNER_CH0_S)
+#define DMA2D_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH0_S  4
+/** DMA2D_OUT_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH0    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH0_M  (DMA2D_OUT_LOOP_TEST_CH0_V << DMA2D_OUT_LOOP_TEST_CH0_S)
+#define DMA2D_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH0_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH0_V << DMA2D_OUT_MEM_BURST_LENGTH_CH0_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH0    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_M  (DMA2D_OUT_DSCR_PORT_EN_CH0_V << DMA2D_OUT_DSCR_PORT_EN_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_M  (DMA2D_OUT_PAGE_BOUND_EN_CH0_V << DMA2D_OUT_PAGE_BOUND_EN_CH0_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_S  12
+/** DMA2D_OUT_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH0    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH0_M  (DMA2D_OUT_REORDER_EN_CH0_V << DMA2D_OUT_REORDER_EN_CH0_S)
+#define DMA2D_OUT_REORDER_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH0_S  16
+/** DMA2D_OUT_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH0    (BIT(24))
+#define DMA2D_OUT_RST_CH0_M  (DMA2D_OUT_RST_CH0_V << DMA2D_OUT_RST_CH0_S)
+#define DMA2D_OUT_RST_CH0_V  0x00000001U
+#define DMA2D_OUT_RST_CH0_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH0    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH0_M  (DMA2D_OUT_CMD_DISABLE_CH0_V << DMA2D_OUT_CMD_DISABLE_CH0_S)
+#define DMA2D_OUT_CMD_DISABLE_CH0_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH0_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** DMA2D_OUT_INT_RAW_CH0_REG register
+ *  Raw interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x4)
+/** DMA2D_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_RAW_M  (DMA2D_OUT_DONE_CH0_INT_RAW_V << DMA2D_OUT_DONE_CH0_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_RAW_M  (DMA2D_OUT_EOF_CH0_INT_RAW_V << DMA2D_OUT_EOF_CH0_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x8)
+/** DMA2D_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_ENA_M  (DMA2D_OUT_DONE_CH0_INT_ENA_V << DMA2D_OUT_DONE_CH0_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_ENA_M  (DMA2D_OUT_EOF_CH0_INT_ENA_V << DMA2D_OUT_EOF_CH0_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0xc)
+/** DMA2D_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_ST_M  (DMA2D_OUT_DONE_CH0_INT_ST_V << DMA2D_OUT_DONE_CH0_INT_ST_S)
+#define DMA2D_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_ST_M  (DMA2D_OUT_EOF_CH0_INT_ST_V << DMA2D_OUT_EOF_CH0_INT_ST_S)
+#define DMA2D_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x10)
+/** DMA2D_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_CLR_M  (DMA2D_OUT_DONE_CH0_INT_CLR_V << DMA2D_OUT_DONE_CH0_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_CLR_M  (DMA2D_OUT_EOF_CH0_INT_CLR_V << DMA2D_OUT_EOF_CH0_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH0_REG register
+ *  Represents the status of the tx fifo of channel 0
+ */
+#define DMA2D_OUTFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x14)
+/** DMA2D_OUTFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH0    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH0_M  (DMA2D_OUTFIFO_FULL_L2_CH0_V << DMA2D_OUTFIFO_FULL_L2_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH0_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_M  (DMA2D_OUTFIFO_EMPTY_L2_CH0_V << DMA2D_OUTFIFO_EMPTY_L2_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH0    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH0_M  (DMA2D_OUTFIFO_CNT_L2_CH0_V << DMA2D_OUTFIFO_CNT_L2_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH0_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH0_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH0_V << DMA2D_OUT_REMAIN_UNDER_1B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH0_V << DMA2D_OUT_REMAIN_UNDER_2B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH0_V << DMA2D_OUT_REMAIN_UNDER_3B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH0_V << DMA2D_OUT_REMAIN_UNDER_4B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH0_V << DMA2D_OUT_REMAIN_UNDER_5B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH0_V << DMA2D_OUT_REMAIN_UNDER_6B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH0_V << DMA2D_OUT_REMAIN_UNDER_7B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH0_V << DMA2D_OUT_REMAIN_UNDER_8B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH0    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH0_M  (DMA2D_OUTFIFO_FULL_L1_CH0_V << DMA2D_OUTFIFO_FULL_L1_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH0_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_M  (DMA2D_OUTFIFO_EMPTY_L1_CH0_V << DMA2D_OUTFIFO_EMPTY_L1_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH0    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH0_M  (DMA2D_OUTFIFO_CNT_L1_CH0_V << DMA2D_OUTFIFO_CNT_L1_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH0_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH0_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH0    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH0_M  (DMA2D_OUTFIFO_FULL_L3_CH0_V << DMA2D_OUTFIFO_FULL_L3_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH0_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_M  (DMA2D_OUTFIFO_EMPTY_L3_CH0_V << DMA2D_OUTFIFO_EMPTY_L3_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH0    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH0_M  (DMA2D_OUTFIFO_CNT_L3_CH0_V << DMA2D_OUTFIFO_CNT_L3_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH0_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH0_S  24
+
+/** DMA2D_OUT_PUSH_CH0_REG register
+ *  Configures the tx fifo of channel 0
+ */
+#define DMA2D_OUT_PUSH_CH0_REG (DR_REG_DMA2D_BASE + 0x18)
+/** DMA2D_OUTFIFO_WDATA_CH0 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH0    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH0_M  (DMA2D_OUTFIFO_WDATA_CH0_V << DMA2D_OUTFIFO_WDATA_CH0_S)
+#define DMA2D_OUTFIFO_WDATA_CH0_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH0_S  0
+/** DMA2D_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH0    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH0_M  (DMA2D_OUTFIFO_PUSH_CH0_V << DMA2D_OUTFIFO_PUSH_CH0_S)
+#define DMA2D_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH0_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH0_REG register
+ *  Configures the tx descriptor operations of channel 0
+ */
+#define DMA2D_OUT_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x1c)
+/** DMA2D_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH0    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH0_M  (DMA2D_OUTLINK_STOP_CH0_V << DMA2D_OUTLINK_STOP_CH0_S)
+#define DMA2D_OUTLINK_STOP_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH0_S  20
+/** DMA2D_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH0    (BIT(21))
+#define DMA2D_OUTLINK_START_CH0_M  (DMA2D_OUTLINK_START_CH0_V << DMA2D_OUTLINK_START_CH0_S)
+#define DMA2D_OUTLINK_START_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH0_S  21
+/** DMA2D_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH0    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH0_M  (DMA2D_OUTLINK_RESTART_CH0_V << DMA2D_OUTLINK_RESTART_CH0_S)
+#define DMA2D_OUTLINK_RESTART_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH0_S  22
+/** DMA2D_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH0    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH0_M  (DMA2D_OUTLINK_PARK_CH0_V << DMA2D_OUTLINK_PARK_CH0_S)
+#define DMA2D_OUTLINK_PARK_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH0_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH0_REG register
+ *  Configures the tx descriptor address of channel 0
+ */
+#define DMA2D_OUT_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x20)
+/** DMA2D_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH0_M  (DMA2D_OUTLINK_ADDR_CH0_V << DMA2D_OUTLINK_ADDR_CH0_S)
+#define DMA2D_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH0_S  0
+
+/** DMA2D_OUT_STATE_CH0_REG register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+#define DMA2D_OUT_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x24)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_M  (DMA2D_OUTLINK_DSCR_ADDR_CH0_V << DMA2D_OUTLINK_DSCR_ADDR_CH0_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_S  0
+/** DMA2D_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH0    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH0_M  (DMA2D_OUT_DSCR_STATE_CH0_V << DMA2D_OUT_DSCR_STATE_CH0_S)
+#define DMA2D_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH0_S  18
+/** DMA2D_OUT_STATE_CH0 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH0    0x0000000FU
+#define DMA2D_OUT_STATE_CH0_M  (DMA2D_OUT_STATE_CH0_V << DMA2D_OUT_STATE_CH0_S)
+#define DMA2D_OUT_STATE_CH0_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH0_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH0 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH0    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH0_M  (DMA2D_OUT_RESET_AVAIL_CH0_V << DMA2D_OUT_RESET_AVAIL_CH0_S)
+#define DMA2D_OUT_RESET_AVAIL_CH0_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH0_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x28)
+/** DMA2D_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_M  (DMA2D_OUT_EOF_DES_ADDR_CH0_V << DMA2D_OUT_EOF_DES_ADDR_CH0_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_OUT_DSCR_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x2c)
+/** DMA2D_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH0_M  (DMA2D_OUTLINK_DSCR_CH0_V << DMA2D_OUTLINK_DSCR_CH0_S)
+#define DMA2D_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH0_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x30)
+/** DMA2D_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_M  (DMA2D_OUTLINK_DSCR_BF0_CH0_V << DMA2D_OUTLINK_DSCR_BF0_CH0_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x34)
+/** DMA2D_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_M  (DMA2D_OUTLINK_DSCR_BF1_CH0_V << DMA2D_OUTLINK_DSCR_BF1_CH0_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH0_REG register
+ *  Configures the tx peripheral of channel 0
+ */
+#define DMA2D_OUT_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x38)
+/** DMA2D_OUT_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH0    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH0_M  (DMA2D_OUT_PERI_SEL_CH0_V << DMA2D_OUT_PERI_SEL_CH0_S)
+#define DMA2D_OUT_PERI_SEL_CH0_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH0_S  0
+
+/** DMA2D_OUT_ARB_CH0_REG register
+ *  Configures the tx arbiter of channel 0
+ */
+#define DMA2D_OUT_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x3c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH0    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH0_M  (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH0_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH0_S  4
+/** DMA2D_OUT_ARB_PRIORITY_H_CH0 : R/W; bitpos: [7:6]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_H_CH0    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH0_M  (DMA2D_OUT_ARB_PRIORITY_H_CH0_V << DMA2D_OUT_ARB_PRIORITY_H_CH0_S)
+#define DMA2D_OUT_ARB_PRIORITY_H_CH0_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH0_S  6
+
+/** DMA2D_OUT_RO_STATUS_CH0_REG register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+#define DMA2D_OUT_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x40)
+/** DMA2D_OUTFIFO_RO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH0    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH0_M  (DMA2D_OUTFIFO_RO_CNT_CH0_V << DMA2D_OUTFIFO_RO_CNT_CH0_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH0_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH0_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH0 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH0    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH0_M  (DMA2D_OUT_RO_WR_STATE_CH0_V << DMA2D_OUT_RO_WR_STATE_CH0_S)
+#define DMA2D_OUT_RO_WR_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH0_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH0 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH0    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH0_M  (DMA2D_OUT_RO_RD_STATE_CH0_V << DMA2D_OUT_RO_RD_STATE_CH0_S)
+#define DMA2D_OUT_RO_RD_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH0_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH0 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH0    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH0_M  (DMA2D_OUT_PIXEL_BYTE_CH0_V << DMA2D_OUT_PIXEL_BYTE_CH0_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH0_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH0_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH0 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH0_V << DMA2D_OUT_BURST_BLOCK_NUM_CH0_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_S  14
+
+/** DMA2D_OUT_RO_PD_CONF_CH0_REG register
+ *  Configures the tx reorder memory of channel 0
+ */
+#define DMA2D_OUT_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x44)
+/** DMA2D_OUT_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_M  (DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S)
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S  4
+/** DMA2D_OUT_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_M  (DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S)
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S  5
+/** DMA2D_OUT_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_M  (DMA2D_OUT_RO_RAM_CLK_FO_CH0_V << DMA2D_OUT_RO_RAM_CLK_FO_CH0_S)
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_S  6
+
+/** DMA2D_OUT_COLOR_CONVERT_CH0_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x48)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH0_V << DMA2D_OUT_COLOR_INPUT_SEL_CH0_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH0_REG register
+ *  Configures the tx scramble of channel 0
+ */
+#define DMA2D_OUT_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x4c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x50)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_M  (DMA2D_OUT_COLOR_PARAM_H0_CH0_V << DMA2D_OUT_COLOR_PARAM_H0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x54)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_M  (DMA2D_OUT_COLOR_PARAM_H1_CH0_V << DMA2D_OUT_COLOR_PARAM_H1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x58)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_M  (DMA2D_OUT_COLOR_PARAM_M0_CH0_V << DMA2D_OUT_COLOR_PARAM_M0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x5c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_M  (DMA2D_OUT_COLOR_PARAM_M1_CH0_V << DMA2D_OUT_COLOR_PARAM_M1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x60)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_M  (DMA2D_OUT_COLOR_PARAM_L0_CH0_V << DMA2D_OUT_COLOR_PARAM_L0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x64)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_M  (DMA2D_OUT_COLOR_PARAM_L1_CH0_V << DMA2D_OUT_COLOR_PARAM_L1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH0_REG register
+ *  Configures the tx etm of channel 0
+ */
+#define DMA2D_OUT_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x68)
+/** DMA2D_OUT_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH0    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH0_M  (DMA2D_OUT_ETM_EN_CH0_V << DMA2D_OUT_ETM_EN_CH0_S)
+#define DMA2D_OUT_ETM_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH0_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH0    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_M  (DMA2D_OUT_ETM_LOOP_EN_CH0_V << DMA2D_OUT_ETM_LOOP_EN_CH0_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_M  (DMA2D_OUT_DSCR_TASK_MAK_CH0_V << DMA2D_OUT_DSCR_TASK_MAK_CH0_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH0_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH0_REG (DR_REG_DMA2D_BASE + 0x6c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH0 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH0 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S  14
+
+/** DMA2D_OUT_CONF0_CH1_REG register
+ *  Configures the tx direction of channel 1
+ */
+#define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100)
+/** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH1    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH1_M  (DMA2D_OUT_AUTO_WRBACK_CH1_V << DMA2D_OUT_AUTO_WRBACK_CH1_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH1_S  0
+/** DMA2D_OUT_EOF_MODE_CH1 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH1    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH1_M  (DMA2D_OUT_EOF_MODE_CH1_V << DMA2D_OUT_EOF_MODE_CH1_S)
+#define DMA2D_OUT_EOF_MODE_CH1_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH1_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH1    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH1_M  (DMA2D_OUTDSCR_BURST_EN_CH1_V << DMA2D_OUTDSCR_BURST_EN_CH1_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH1_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH1    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH1_M  (DMA2D_OUT_ECC_AES_EN_CH1_V << DMA2D_OUT_ECC_AES_EN_CH1_S)
+#define DMA2D_OUT_ECC_AES_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH1_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH1    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH1_M  (DMA2D_OUT_CHECK_OWNER_CH1_V << DMA2D_OUT_CHECK_OWNER_CH1_S)
+#define DMA2D_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH1_S  4
+/** DMA2D_OUT_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH1    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH1_M  (DMA2D_OUT_LOOP_TEST_CH1_V << DMA2D_OUT_LOOP_TEST_CH1_S)
+#define DMA2D_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH1_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH1_V << DMA2D_OUT_MEM_BURST_LENGTH_CH1_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH1    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_M  (DMA2D_OUT_DSCR_PORT_EN_CH1_V << DMA2D_OUT_DSCR_PORT_EN_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_M  (DMA2D_OUT_PAGE_BOUND_EN_CH1_V << DMA2D_OUT_PAGE_BOUND_EN_CH1_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_S  12
+/** DMA2D_OUT_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH1    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH1_M  (DMA2D_OUT_REORDER_EN_CH1_V << DMA2D_OUT_REORDER_EN_CH1_S)
+#define DMA2D_OUT_REORDER_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH1_S  16
+/** DMA2D_OUT_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH1    (BIT(24))
+#define DMA2D_OUT_RST_CH1_M  (DMA2D_OUT_RST_CH1_V << DMA2D_OUT_RST_CH1_S)
+#define DMA2D_OUT_RST_CH1_V  0x00000001U
+#define DMA2D_OUT_RST_CH1_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH1    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH1_M  (DMA2D_OUT_CMD_DISABLE_CH1_V << DMA2D_OUT_CMD_DISABLE_CH1_S)
+#define DMA2D_OUT_CMD_DISABLE_CH1_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH1_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** DMA2D_OUT_INT_RAW_CH1_REG register
+ *  Raw interrupt status of TX channel 1
+ */
+#define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104)
+/** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_RAW_M  (DMA2D_OUT_DONE_CH1_INT_RAW_V << DMA2D_OUT_DONE_CH1_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_RAW_M  (DMA2D_OUT_EOF_CH1_INT_RAW_V << DMA2D_OUT_EOF_CH1_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of TX channel 1
+ */
+#define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108)
+/** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_ENA_M  (DMA2D_OUT_DONE_CH1_INT_ENA_V << DMA2D_OUT_DONE_CH1_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_ENA_M  (DMA2D_OUT_EOF_CH1_INT_ENA_V << DMA2D_OUT_EOF_CH1_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt status of TX channel 1
+ */
+#define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c)
+/** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_ST_M  (DMA2D_OUT_DONE_CH1_INT_ST_V << DMA2D_OUT_DONE_CH1_INT_ST_S)
+#define DMA2D_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_ST_M  (DMA2D_OUT_EOF_CH1_INT_ST_V << DMA2D_OUT_EOF_CH1_INT_ST_S)
+#define DMA2D_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of TX channel 1
+ */
+#define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110)
+/** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_CLR_M  (DMA2D_OUT_DONE_CH1_INT_CLR_V << DMA2D_OUT_DONE_CH1_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_CLR_M  (DMA2D_OUT_EOF_CH1_INT_CLR_V << DMA2D_OUT_EOF_CH1_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH1_REG register
+ *  Represents the status of the tx fifo of channel 1
+ */
+#define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114)
+/** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH1    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH1_M  (DMA2D_OUTFIFO_FULL_L2_CH1_V << DMA2D_OUTFIFO_FULL_L2_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH1_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_M  (DMA2D_OUTFIFO_EMPTY_L2_CH1_V << DMA2D_OUTFIFO_EMPTY_L2_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH1    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH1_M  (DMA2D_OUTFIFO_CNT_L2_CH1_V << DMA2D_OUTFIFO_CNT_L2_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH1_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH1_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH1_V << DMA2D_OUT_REMAIN_UNDER_1B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH1_V << DMA2D_OUT_REMAIN_UNDER_2B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH1_V << DMA2D_OUT_REMAIN_UNDER_3B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH1_V << DMA2D_OUT_REMAIN_UNDER_4B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH1_V << DMA2D_OUT_REMAIN_UNDER_5B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH1_V << DMA2D_OUT_REMAIN_UNDER_6B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH1_V << DMA2D_OUT_REMAIN_UNDER_7B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH1_V << DMA2D_OUT_REMAIN_UNDER_8B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH1    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH1_M  (DMA2D_OUTFIFO_FULL_L1_CH1_V << DMA2D_OUTFIFO_FULL_L1_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH1_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_M  (DMA2D_OUTFIFO_EMPTY_L1_CH1_V << DMA2D_OUTFIFO_EMPTY_L1_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH1    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH1_M  (DMA2D_OUTFIFO_CNT_L1_CH1_V << DMA2D_OUTFIFO_CNT_L1_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH1_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH1_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH1    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH1_M  (DMA2D_OUTFIFO_FULL_L3_CH1_V << DMA2D_OUTFIFO_FULL_L3_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH1_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_M  (DMA2D_OUTFIFO_EMPTY_L3_CH1_V << DMA2D_OUTFIFO_EMPTY_L3_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH1    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH1_M  (DMA2D_OUTFIFO_CNT_L3_CH1_V << DMA2D_OUTFIFO_CNT_L3_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH1_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH1_S  24
+
+/** DMA2D_OUT_PUSH_CH1_REG register
+ *  Configures the tx fifo of channel 1
+ */
+#define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118)
+/** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH1    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH1_M  (DMA2D_OUTFIFO_WDATA_CH1_V << DMA2D_OUTFIFO_WDATA_CH1_S)
+#define DMA2D_OUTFIFO_WDATA_CH1_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH1_S  0
+/** DMA2D_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH1    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH1_M  (DMA2D_OUTFIFO_PUSH_CH1_V << DMA2D_OUTFIFO_PUSH_CH1_S)
+#define DMA2D_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH1_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH1_REG register
+ *  Configures the tx descriptor operations of channel 1
+ */
+#define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c)
+/** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH1    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH1_M  (DMA2D_OUTLINK_STOP_CH1_V << DMA2D_OUTLINK_STOP_CH1_S)
+#define DMA2D_OUTLINK_STOP_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH1_S  20
+/** DMA2D_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH1    (BIT(21))
+#define DMA2D_OUTLINK_START_CH1_M  (DMA2D_OUTLINK_START_CH1_V << DMA2D_OUTLINK_START_CH1_S)
+#define DMA2D_OUTLINK_START_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH1_S  21
+/** DMA2D_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH1    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH1_M  (DMA2D_OUTLINK_RESTART_CH1_V << DMA2D_OUTLINK_RESTART_CH1_S)
+#define DMA2D_OUTLINK_RESTART_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH1_S  22
+/** DMA2D_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH1    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH1_M  (DMA2D_OUTLINK_PARK_CH1_V << DMA2D_OUTLINK_PARK_CH1_S)
+#define DMA2D_OUTLINK_PARK_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH1_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH1_REG register
+ *  Configures the tx descriptor address of channel 1
+ */
+#define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120)
+/** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH1_M  (DMA2D_OUTLINK_ADDR_CH1_V << DMA2D_OUTLINK_ADDR_CH1_S)
+#define DMA2D_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH1_S  0
+
+/** DMA2D_OUT_STATE_CH1_REG register
+ *  Represents the working status of the tx descriptor of channel 1
+ */
+#define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_M  (DMA2D_OUTLINK_DSCR_ADDR_CH1_V << DMA2D_OUTLINK_DSCR_ADDR_CH1_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_S  0
+/** DMA2D_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH1    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH1_M  (DMA2D_OUT_DSCR_STATE_CH1_V << DMA2D_OUT_DSCR_STATE_CH1_S)
+#define DMA2D_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH1_S  18
+/** DMA2D_OUT_STATE_CH1 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH1    0x0000000FU
+#define DMA2D_OUT_STATE_CH1_M  (DMA2D_OUT_STATE_CH1_V << DMA2D_OUT_STATE_CH1_S)
+#define DMA2D_OUT_STATE_CH1_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH1_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH1 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH1    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH1_M  (DMA2D_OUT_RESET_AVAIL_CH1_V << DMA2D_OUT_RESET_AVAIL_CH1_S)
+#define DMA2D_OUT_RESET_AVAIL_CH1_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH1_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128)
+/** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_M  (DMA2D_OUT_EOF_DES_ADDR_CH1_V << DMA2D_OUT_EOF_DES_ADDR_CH1_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_OUT_DSCR_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c)
+/** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH1_M  (DMA2D_OUTLINK_DSCR_CH1_V << DMA2D_OUTLINK_DSCR_CH1_S)
+#define DMA2D_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH1_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130)
+/** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_M  (DMA2D_OUTLINK_DSCR_BF0_CH1_V << DMA2D_OUTLINK_DSCR_BF0_CH1_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134)
+/** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_M  (DMA2D_OUTLINK_DSCR_BF1_CH1_V << DMA2D_OUTLINK_DSCR_BF1_CH1_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH1_REG register
+ *  Configures the tx peripheral of channel 1
+ */
+#define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138)
+/** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH1    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH1_M  (DMA2D_OUT_PERI_SEL_CH1_V << DMA2D_OUT_PERI_SEL_CH1_S)
+#define DMA2D_OUT_PERI_SEL_CH1_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH1_S  0
+
+/** DMA2D_OUT_ARB_CH1_REG register
+ *  Configures the tx arbiter of channel 1
+ */
+#define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH1    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH1_M  (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH1_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH1_S  4
+/** DMA2D_OUT_ARB_PRIORITY_H_CH1 : R/W; bitpos: [7:6]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_H_CH1    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH1_M  (DMA2D_OUT_ARB_PRIORITY_H_CH1_V << DMA2D_OUT_ARB_PRIORITY_H_CH1_S)
+#define DMA2D_OUT_ARB_PRIORITY_H_CH1_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH1_S  6
+
+/** DMA2D_OUT_RO_STATUS_CH1_REG register
+ *  Represents the status of the tx reorder module of channel 1
+ */
+#define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140)
+/** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH1    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH1_M  (DMA2D_OUTFIFO_RO_CNT_CH1_V << DMA2D_OUTFIFO_RO_CNT_CH1_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH1_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH1_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH1 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH1    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH1_M  (DMA2D_OUT_RO_WR_STATE_CH1_V << DMA2D_OUT_RO_WR_STATE_CH1_S)
+#define DMA2D_OUT_RO_WR_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH1_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH1 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH1    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH1_M  (DMA2D_OUT_RO_RD_STATE_CH1_V << DMA2D_OUT_RO_RD_STATE_CH1_S)
+#define DMA2D_OUT_RO_RD_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH1_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH1 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH1    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH1_M  (DMA2D_OUT_PIXEL_BYTE_CH1_V << DMA2D_OUT_PIXEL_BYTE_CH1_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH1_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH1_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH1 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH1_V << DMA2D_OUT_BURST_BLOCK_NUM_CH1_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH1_REG register
+ *  Configures the tx color convert of channel 1
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH1_V << DMA2D_OUT_COLOR_INPUT_SEL_CH1_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH1_REG register
+ *  Configures the tx scramble of channel 1
+ */
+#define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_M  (DMA2D_OUT_COLOR_PARAM_H0_CH1_V << DMA2D_OUT_COLOR_PARAM_H0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_M  (DMA2D_OUT_COLOR_PARAM_H1_CH1_V << DMA2D_OUT_COLOR_PARAM_H1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_M  (DMA2D_OUT_COLOR_PARAM_M0_CH1_V << DMA2D_OUT_COLOR_PARAM_M0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_M  (DMA2D_OUT_COLOR_PARAM_M1_CH1_V << DMA2D_OUT_COLOR_PARAM_M1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_M  (DMA2D_OUT_COLOR_PARAM_L0_CH1_V << DMA2D_OUT_COLOR_PARAM_L0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_M  (DMA2D_OUT_COLOR_PARAM_L1_CH1_V << DMA2D_OUT_COLOR_PARAM_L1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH1_REG register
+ *  Configures the tx etm of channel 1
+ */
+#define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168)
+/** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH1    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH1_M  (DMA2D_OUT_ETM_EN_CH1_V << DMA2D_OUT_ETM_EN_CH1_S)
+#define DMA2D_OUT_ETM_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH1_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH1    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_M  (DMA2D_OUT_ETM_LOOP_EN_CH1_V << DMA2D_OUT_ETM_LOOP_EN_CH1_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_M  (DMA2D_OUT_DSCR_TASK_MAK_CH1_V << DMA2D_OUT_DSCR_TASK_MAK_CH1_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH1_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH1_REG (DR_REG_DMA2D_BASE + 0x16c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH1 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH1 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S  14
+
+/** DMA2D_OUT_CONF0_CH2_REG register
+ *  Configures the tx direction of channel 2
+ */
+#define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200)
+/** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH2    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH2_M  (DMA2D_OUT_AUTO_WRBACK_CH2_V << DMA2D_OUT_AUTO_WRBACK_CH2_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH2_S  0
+/** DMA2D_OUT_EOF_MODE_CH2 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH2    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH2_M  (DMA2D_OUT_EOF_MODE_CH2_V << DMA2D_OUT_EOF_MODE_CH2_S)
+#define DMA2D_OUT_EOF_MODE_CH2_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH2_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH2    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH2_M  (DMA2D_OUTDSCR_BURST_EN_CH2_V << DMA2D_OUTDSCR_BURST_EN_CH2_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH2_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH2    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH2_M  (DMA2D_OUT_ECC_AES_EN_CH2_V << DMA2D_OUT_ECC_AES_EN_CH2_S)
+#define DMA2D_OUT_ECC_AES_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH2_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH2    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH2_M  (DMA2D_OUT_CHECK_OWNER_CH2_V << DMA2D_OUT_CHECK_OWNER_CH2_S)
+#define DMA2D_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH2_S  4
+/** DMA2D_OUT_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH2    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH2_M  (DMA2D_OUT_LOOP_TEST_CH2_V << DMA2D_OUT_LOOP_TEST_CH2_S)
+#define DMA2D_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH2_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH2_V << DMA2D_OUT_MEM_BURST_LENGTH_CH2_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH2    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_M  (DMA2D_OUT_DSCR_PORT_EN_CH2_V << DMA2D_OUT_DSCR_PORT_EN_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_M  (DMA2D_OUT_PAGE_BOUND_EN_CH2_V << DMA2D_OUT_PAGE_BOUND_EN_CH2_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_S  12
+/** DMA2D_OUT_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH2    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH2_M  (DMA2D_OUT_REORDER_EN_CH2_V << DMA2D_OUT_REORDER_EN_CH2_S)
+#define DMA2D_OUT_REORDER_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH2_S  16
+/** DMA2D_OUT_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH2    (BIT(24))
+#define DMA2D_OUT_RST_CH2_M  (DMA2D_OUT_RST_CH2_V << DMA2D_OUT_RST_CH2_S)
+#define DMA2D_OUT_RST_CH2_V  0x00000001U
+#define DMA2D_OUT_RST_CH2_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH2    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH2_M  (DMA2D_OUT_CMD_DISABLE_CH2_V << DMA2D_OUT_CMD_DISABLE_CH2_S)
+#define DMA2D_OUT_CMD_DISABLE_CH2_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH2_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** DMA2D_OUT_INT_RAW_CH2_REG register
+ *  Raw interrupt status of TX channel 2
+ */
+#define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204)
+/** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_RAW_M  (DMA2D_OUT_DONE_CH2_INT_RAW_V << DMA2D_OUT_DONE_CH2_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_RAW_M  (DMA2D_OUT_EOF_CH2_INT_RAW_V << DMA2D_OUT_EOF_CH2_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of TX channel 2
+ */
+#define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208)
+/** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_ENA_M  (DMA2D_OUT_DONE_CH2_INT_ENA_V << DMA2D_OUT_DONE_CH2_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_ENA_M  (DMA2D_OUT_EOF_CH2_INT_ENA_V << DMA2D_OUT_EOF_CH2_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt status of TX channel 2
+ */
+#define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c)
+/** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_ST_M  (DMA2D_OUT_DONE_CH2_INT_ST_V << DMA2D_OUT_DONE_CH2_INT_ST_S)
+#define DMA2D_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_ST_M  (DMA2D_OUT_EOF_CH2_INT_ST_V << DMA2D_OUT_EOF_CH2_INT_ST_S)
+#define DMA2D_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of TX channel 2
+ */
+#define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210)
+/** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_CLR_M  (DMA2D_OUT_DONE_CH2_INT_CLR_V << DMA2D_OUT_DONE_CH2_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_CLR_M  (DMA2D_OUT_EOF_CH2_INT_CLR_V << DMA2D_OUT_EOF_CH2_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH2_REG register
+ *  Represents the status of the tx fifo of channel 2
+ */
+#define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214)
+/** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH2    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH2_M  (DMA2D_OUTFIFO_FULL_L2_CH2_V << DMA2D_OUTFIFO_FULL_L2_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH2_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_M  (DMA2D_OUTFIFO_EMPTY_L2_CH2_V << DMA2D_OUTFIFO_EMPTY_L2_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH2    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH2_M  (DMA2D_OUTFIFO_CNT_L2_CH2_V << DMA2D_OUTFIFO_CNT_L2_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH2_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH2_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH2_V << DMA2D_OUT_REMAIN_UNDER_1B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH2_V << DMA2D_OUT_REMAIN_UNDER_2B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH2_V << DMA2D_OUT_REMAIN_UNDER_3B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH2_V << DMA2D_OUT_REMAIN_UNDER_4B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH2_V << DMA2D_OUT_REMAIN_UNDER_5B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH2_V << DMA2D_OUT_REMAIN_UNDER_6B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH2_V << DMA2D_OUT_REMAIN_UNDER_7B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH2_V << DMA2D_OUT_REMAIN_UNDER_8B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH2    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH2_M  (DMA2D_OUTFIFO_FULL_L1_CH2_V << DMA2D_OUTFIFO_FULL_L1_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH2_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_M  (DMA2D_OUTFIFO_EMPTY_L1_CH2_V << DMA2D_OUTFIFO_EMPTY_L1_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH2    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH2_M  (DMA2D_OUTFIFO_CNT_L1_CH2_V << DMA2D_OUTFIFO_CNT_L1_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH2_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH2_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH2    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH2_M  (DMA2D_OUTFIFO_FULL_L3_CH2_V << DMA2D_OUTFIFO_FULL_L3_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH2_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_M  (DMA2D_OUTFIFO_EMPTY_L3_CH2_V << DMA2D_OUTFIFO_EMPTY_L3_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH2    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH2_M  (DMA2D_OUTFIFO_CNT_L3_CH2_V << DMA2D_OUTFIFO_CNT_L3_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH2_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH2_S  24
+
+/** DMA2D_OUT_PUSH_CH2_REG register
+ *  Configures the tx fifo of channel 2
+ */
+#define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218)
+/** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH2    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH2_M  (DMA2D_OUTFIFO_WDATA_CH2_V << DMA2D_OUTFIFO_WDATA_CH2_S)
+#define DMA2D_OUTFIFO_WDATA_CH2_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH2_S  0
+/** DMA2D_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH2    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH2_M  (DMA2D_OUTFIFO_PUSH_CH2_V << DMA2D_OUTFIFO_PUSH_CH2_S)
+#define DMA2D_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH2_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH2_REG register
+ *  Configures the tx descriptor operations of channel 2
+ */
+#define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c)
+/** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH2    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH2_M  (DMA2D_OUTLINK_STOP_CH2_V << DMA2D_OUTLINK_STOP_CH2_S)
+#define DMA2D_OUTLINK_STOP_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH2_S  20
+/** DMA2D_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH2    (BIT(21))
+#define DMA2D_OUTLINK_START_CH2_M  (DMA2D_OUTLINK_START_CH2_V << DMA2D_OUTLINK_START_CH2_S)
+#define DMA2D_OUTLINK_START_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH2_S  21
+/** DMA2D_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH2    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH2_M  (DMA2D_OUTLINK_RESTART_CH2_V << DMA2D_OUTLINK_RESTART_CH2_S)
+#define DMA2D_OUTLINK_RESTART_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH2_S  22
+/** DMA2D_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH2    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH2_M  (DMA2D_OUTLINK_PARK_CH2_V << DMA2D_OUTLINK_PARK_CH2_S)
+#define DMA2D_OUTLINK_PARK_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH2_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH2_REG register
+ *  Configures the tx descriptor address of channel 2
+ */
+#define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220)
+/** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH2_M  (DMA2D_OUTLINK_ADDR_CH2_V << DMA2D_OUTLINK_ADDR_CH2_S)
+#define DMA2D_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH2_S  0
+
+/** DMA2D_OUT_STATE_CH2_REG register
+ *  Represents the working status of the tx descriptor of channel 2
+ */
+#define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_M  (DMA2D_OUTLINK_DSCR_ADDR_CH2_V << DMA2D_OUTLINK_DSCR_ADDR_CH2_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_S  0
+/** DMA2D_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH2    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH2_M  (DMA2D_OUT_DSCR_STATE_CH2_V << DMA2D_OUT_DSCR_STATE_CH2_S)
+#define DMA2D_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH2_S  18
+/** DMA2D_OUT_STATE_CH2 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH2    0x0000000FU
+#define DMA2D_OUT_STATE_CH2_M  (DMA2D_OUT_STATE_CH2_V << DMA2D_OUT_STATE_CH2_S)
+#define DMA2D_OUT_STATE_CH2_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH2_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH2 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH2    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH2_M  (DMA2D_OUT_RESET_AVAIL_CH2_V << DMA2D_OUT_RESET_AVAIL_CH2_S)
+#define DMA2D_OUT_RESET_AVAIL_CH2_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH2_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228)
+/** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_M  (DMA2D_OUT_EOF_DES_ADDR_CH2_V << DMA2D_OUT_EOF_DES_ADDR_CH2_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_OUT_DSCR_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c)
+/** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH2_M  (DMA2D_OUTLINK_DSCR_CH2_V << DMA2D_OUTLINK_DSCR_CH2_S)
+#define DMA2D_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH2_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230)
+/** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_M  (DMA2D_OUTLINK_DSCR_BF0_CH2_V << DMA2D_OUTLINK_DSCR_BF0_CH2_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234)
+/** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_M  (DMA2D_OUTLINK_DSCR_BF1_CH2_V << DMA2D_OUTLINK_DSCR_BF1_CH2_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH2_REG register
+ *  Configures the tx peripheral of channel 2
+ */
+#define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238)
+/** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH2    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH2_M  (DMA2D_OUT_PERI_SEL_CH2_V << DMA2D_OUT_PERI_SEL_CH2_S)
+#define DMA2D_OUT_PERI_SEL_CH2_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH2_S  0
+
+/** DMA2D_OUT_ARB_CH2_REG register
+ *  Configures the tx arbiter of channel 2
+ */
+#define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH2    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH2_M  (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH2_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH2_S  4
+/** DMA2D_OUT_ARB_PRIORITY_H_CH2 : R/W; bitpos: [7:6]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_H_CH2    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH2_M  (DMA2D_OUT_ARB_PRIORITY_H_CH2_V << DMA2D_OUT_ARB_PRIORITY_H_CH2_S)
+#define DMA2D_OUT_ARB_PRIORITY_H_CH2_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH2_S  6
+
+/** DMA2D_OUT_RO_STATUS_CH2_REG register
+ *  Represents the status of the tx reorder module of channel 2
+ */
+#define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240)
+/** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH2    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH2_M  (DMA2D_OUTFIFO_RO_CNT_CH2_V << DMA2D_OUTFIFO_RO_CNT_CH2_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH2_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH2_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH2 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH2    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH2_M  (DMA2D_OUT_RO_WR_STATE_CH2_V << DMA2D_OUT_RO_WR_STATE_CH2_S)
+#define DMA2D_OUT_RO_WR_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH2_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH2 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH2    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH2_M  (DMA2D_OUT_RO_RD_STATE_CH2_V << DMA2D_OUT_RO_RD_STATE_CH2_S)
+#define DMA2D_OUT_RO_RD_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH2_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH2 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH2    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH2_M  (DMA2D_OUT_PIXEL_BYTE_CH2_V << DMA2D_OUT_PIXEL_BYTE_CH2_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH2_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH2_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH2 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH2_V << DMA2D_OUT_BURST_BLOCK_NUM_CH2_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH2_REG register
+ *  Configures the tx color convert of channel 2
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH2_V << DMA2D_OUT_COLOR_INPUT_SEL_CH2_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH2_REG register
+ *  Configures the tx scramble of channel 2
+ */
+#define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_M  (DMA2D_OUT_COLOR_PARAM_H0_CH2_V << DMA2D_OUT_COLOR_PARAM_H0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_M  (DMA2D_OUT_COLOR_PARAM_H1_CH2_V << DMA2D_OUT_COLOR_PARAM_H1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_M  (DMA2D_OUT_COLOR_PARAM_M0_CH2_V << DMA2D_OUT_COLOR_PARAM_M0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_M  (DMA2D_OUT_COLOR_PARAM_M1_CH2_V << DMA2D_OUT_COLOR_PARAM_M1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_M  (DMA2D_OUT_COLOR_PARAM_L0_CH2_V << DMA2D_OUT_COLOR_PARAM_L0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_M  (DMA2D_OUT_COLOR_PARAM_L1_CH2_V << DMA2D_OUT_COLOR_PARAM_L1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH2_REG register
+ *  Configures the tx etm of channel 2
+ */
+#define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268)
+/** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH2    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH2_M  (DMA2D_OUT_ETM_EN_CH2_V << DMA2D_OUT_ETM_EN_CH2_S)
+#define DMA2D_OUT_ETM_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH2_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH2    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_M  (DMA2D_OUT_ETM_LOOP_EN_CH2_V << DMA2D_OUT_ETM_LOOP_EN_CH2_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_M  (DMA2D_OUT_DSCR_TASK_MAK_CH2_V << DMA2D_OUT_DSCR_TASK_MAK_CH2_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH2_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH2_REG (DR_REG_DMA2D_BASE + 0x26c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH2 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH2 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S  14
+
+/** DMA2D_OUT_CONF0_CH3_REG register
+ *  Configures the tx direction of channel 3
+ */
+#define DMA2D_OUT_CONF0_CH3_REG (DR_REG_DMA2D_BASE + 0x300)
+/** DMA2D_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH3    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH3_M  (DMA2D_OUT_AUTO_WRBACK_CH3_V << DMA2D_OUT_AUTO_WRBACK_CH3_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH3_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH3_S  0
+/** DMA2D_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH3    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH3_M  (DMA2D_OUT_EOF_MODE_CH3_V << DMA2D_OUT_EOF_MODE_CH3_S)
+#define DMA2D_OUT_EOF_MODE_CH3_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH3_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH3    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH3_M  (DMA2D_OUTDSCR_BURST_EN_CH3_V << DMA2D_OUTDSCR_BURST_EN_CH3_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH3_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH3_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH3    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH3_M  (DMA2D_OUT_ECC_AES_EN_CH3_V << DMA2D_OUT_ECC_AES_EN_CH3_S)
+#define DMA2D_OUT_ECC_AES_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH3_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH3    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH3_M  (DMA2D_OUT_CHECK_OWNER_CH3_V << DMA2D_OUT_CHECK_OWNER_CH3_S)
+#define DMA2D_OUT_CHECK_OWNER_CH3_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH3_S  4
+/** DMA2D_OUT_LOOP_TEST_CH3 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH3    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH3_M  (DMA2D_OUT_LOOP_TEST_CH3_V << DMA2D_OUT_LOOP_TEST_CH3_S)
+#define DMA2D_OUT_LOOP_TEST_CH3_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH3_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH3_V << DMA2D_OUT_MEM_BURST_LENGTH_CH3_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH3 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH3    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH3_M  (DMA2D_OUT_DSCR_PORT_EN_CH3_V << DMA2D_OUT_DSCR_PORT_EN_CH3_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH3_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3_M  (DMA2D_OUT_PAGE_BOUND_EN_CH3_V << DMA2D_OUT_PAGE_BOUND_EN_CH3_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3_S  12
+/** DMA2D_OUT_REORDER_EN_CH3 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH3    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH3_M  (DMA2D_OUT_REORDER_EN_CH3_V << DMA2D_OUT_REORDER_EN_CH3_S)
+#define DMA2D_OUT_REORDER_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH3_S  16
+/** DMA2D_OUT_RST_CH3 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH3    (BIT(24))
+#define DMA2D_OUT_RST_CH3_M  (DMA2D_OUT_RST_CH3_V << DMA2D_OUT_RST_CH3_S)
+#define DMA2D_OUT_RST_CH3_V  0x00000001U
+#define DMA2D_OUT_RST_CH3_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH3    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH3_M  (DMA2D_OUT_CMD_DISABLE_CH3_V << DMA2D_OUT_CMD_DISABLE_CH3_S)
+#define DMA2D_OUT_CMD_DISABLE_CH3_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH3_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S  26
+
+/** DMA2D_OUT_INT_RAW_CH3_REG register
+ *  Raw interrupt status of TX channel 3
+ */
+#define DMA2D_OUT_INT_RAW_CH3_REG (DR_REG_DMA2D_BASE + 0x304)
+/** DMA2D_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_RAW_M  (DMA2D_OUT_DONE_CH3_INT_RAW_V << DMA2D_OUT_DONE_CH3_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_RAW_M  (DMA2D_OUT_EOF_CH3_INT_RAW_V << DMA2D_OUT_EOF_CH3_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH3_REG register
+ *  Interrupt enable bits of TX channel 3
+ */
+#define DMA2D_OUT_INT_ENA_CH3_REG (DR_REG_DMA2D_BASE + 0x308)
+/** DMA2D_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_ENA_M  (DMA2D_OUT_DONE_CH3_INT_ENA_V << DMA2D_OUT_DONE_CH3_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_ENA_M  (DMA2D_OUT_EOF_CH3_INT_ENA_V << DMA2D_OUT_EOF_CH3_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH3_REG register
+ *  Masked interrupt status of TX channel 3
+ */
+#define DMA2D_OUT_INT_ST_CH3_REG (DR_REG_DMA2D_BASE + 0x30c)
+/** DMA2D_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_ST_M  (DMA2D_OUT_DONE_CH3_INT_ST_V << DMA2D_OUT_DONE_CH3_INT_ST_S)
+#define DMA2D_OUT_DONE_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_ST_M  (DMA2D_OUT_EOF_CH3_INT_ST_V << DMA2D_OUT_EOF_CH3_INT_ST_S)
+#define DMA2D_OUT_EOF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH3_REG register
+ *  Interrupt clear bits of TX channel 3
+ */
+#define DMA2D_OUT_INT_CLR_CH3_REG (DR_REG_DMA2D_BASE + 0x310)
+/** DMA2D_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_CLR_M  (DMA2D_OUT_DONE_CH3_INT_CLR_V << DMA2D_OUT_DONE_CH3_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_CLR_M  (DMA2D_OUT_EOF_CH3_INT_CLR_V << DMA2D_OUT_EOF_CH3_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH3_REG register
+ *  Represents the status of the tx fifo of channel 3
+ */
+#define DMA2D_OUTFIFO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x314)
+/** DMA2D_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH3    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH3_M  (DMA2D_OUTFIFO_FULL_L2_CH3_V << DMA2D_OUTFIFO_FULL_L2_CH3_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH3_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3_M  (DMA2D_OUTFIFO_EMPTY_L2_CH3_V << DMA2D_OUTFIFO_EMPTY_L2_CH3_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH3    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH3_M  (DMA2D_OUTFIFO_CNT_L2_CH3_V << DMA2D_OUTFIFO_CNT_L2_CH3_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH3_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH3_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH3 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH3_V << DMA2D_OUT_REMAIN_UNDER_1B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH3 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH3_V << DMA2D_OUT_REMAIN_UNDER_2B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH3 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH3_V << DMA2D_OUT_REMAIN_UNDER_3B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH3 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH3_V << DMA2D_OUT_REMAIN_UNDER_4B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH3 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH3_V << DMA2D_OUT_REMAIN_UNDER_5B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH3 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH3_V << DMA2D_OUT_REMAIN_UNDER_6B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH3 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH3_V << DMA2D_OUT_REMAIN_UNDER_7B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH3 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH3_V << DMA2D_OUT_REMAIN_UNDER_8B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH3    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH3_M  (DMA2D_OUTFIFO_FULL_L1_CH3_V << DMA2D_OUTFIFO_FULL_L1_CH3_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH3_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3_M  (DMA2D_OUTFIFO_EMPTY_L1_CH3_V << DMA2D_OUTFIFO_EMPTY_L1_CH3_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH3    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH3_M  (DMA2D_OUTFIFO_CNT_L1_CH3_V << DMA2D_OUTFIFO_CNT_L1_CH3_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH3_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH3_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH3    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH3_M  (DMA2D_OUTFIFO_FULL_L3_CH3_V << DMA2D_OUTFIFO_FULL_L3_CH3_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH3_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3_M  (DMA2D_OUTFIFO_EMPTY_L3_CH3_V << DMA2D_OUTFIFO_EMPTY_L3_CH3_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH3    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH3_M  (DMA2D_OUTFIFO_CNT_L3_CH3_V << DMA2D_OUTFIFO_CNT_L3_CH3_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH3_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH3_S  24
+
+/** DMA2D_OUT_PUSH_CH3_REG register
+ *  Configures the tx fifo of channel 3
+ */
+#define DMA2D_OUT_PUSH_CH3_REG (DR_REG_DMA2D_BASE + 0x318)
+/** DMA2D_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH3    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH3_M  (DMA2D_OUTFIFO_WDATA_CH3_V << DMA2D_OUTFIFO_WDATA_CH3_S)
+#define DMA2D_OUTFIFO_WDATA_CH3_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH3_S  0
+/** DMA2D_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH3    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH3_M  (DMA2D_OUTFIFO_PUSH_CH3_V << DMA2D_OUTFIFO_PUSH_CH3_S)
+#define DMA2D_OUTFIFO_PUSH_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH3_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH3_REG register
+ *  Configures the tx descriptor operations of channel 3
+ */
+#define DMA2D_OUT_LINK_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x31c)
+/** DMA2D_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH3    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH3_M  (DMA2D_OUTLINK_STOP_CH3_V << DMA2D_OUTLINK_STOP_CH3_S)
+#define DMA2D_OUTLINK_STOP_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH3_S  20
+/** DMA2D_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH3    (BIT(21))
+#define DMA2D_OUTLINK_START_CH3_M  (DMA2D_OUTLINK_START_CH3_V << DMA2D_OUTLINK_START_CH3_S)
+#define DMA2D_OUTLINK_START_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH3_S  21
+/** DMA2D_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH3    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH3_M  (DMA2D_OUTLINK_RESTART_CH3_V << DMA2D_OUTLINK_RESTART_CH3_S)
+#define DMA2D_OUTLINK_RESTART_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH3_S  22
+/** DMA2D_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH3    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH3_M  (DMA2D_OUTLINK_PARK_CH3_V << DMA2D_OUTLINK_PARK_CH3_S)
+#define DMA2D_OUTLINK_PARK_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH3_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH3_REG register
+ *  Configures the tx descriptor address of channel 3
+ */
+#define DMA2D_OUT_LINK_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x320)
+/** DMA2D_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH3_M  (DMA2D_OUTLINK_ADDR_CH3_V << DMA2D_OUTLINK_ADDR_CH3_S)
+#define DMA2D_OUTLINK_ADDR_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH3_S  0
+
+/** DMA2D_OUT_STATE_CH3_REG register
+ *  Represents the working status of the tx descriptor of channel 3
+ */
+#define DMA2D_OUT_STATE_CH3_REG (DR_REG_DMA2D_BASE + 0x324)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3_M  (DMA2D_OUTLINK_DSCR_ADDR_CH3_V << DMA2D_OUTLINK_DSCR_ADDR_CH3_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3_S  0
+/** DMA2D_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH3    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH3_M  (DMA2D_OUT_DSCR_STATE_CH3_V << DMA2D_OUT_DSCR_STATE_CH3_S)
+#define DMA2D_OUT_DSCR_STATE_CH3_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH3_S  18
+/** DMA2D_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH3    0x0000000FU
+#define DMA2D_OUT_STATE_CH3_M  (DMA2D_OUT_STATE_CH3_V << DMA2D_OUT_STATE_CH3_S)
+#define DMA2D_OUT_STATE_CH3_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH3_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH3 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH3    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH3_M  (DMA2D_OUT_RESET_AVAIL_CH3_V << DMA2D_OUT_RESET_AVAIL_CH3_S)
+#define DMA2D_OUT_RESET_AVAIL_CH3_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH3_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x328)
+/** DMA2D_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_M  (DMA2D_OUT_EOF_DES_ADDR_CH3_V << DMA2D_OUT_EOF_DES_ADDR_CH3_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_S  0
+
+/** DMA2D_OUT_DSCR_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_DSCR_CH3_REG (DR_REG_DMA2D_BASE + 0x32c)
+/** DMA2D_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH3_M  (DMA2D_OUTLINK_DSCR_CH3_V << DMA2D_OUTLINK_DSCR_CH3_S)
+#define DMA2D_OUTLINK_DSCR_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH3_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_DSCR_BF0_CH3_REG (DR_REG_DMA2D_BASE + 0x330)
+/** DMA2D_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH3_M  (DMA2D_OUTLINK_DSCR_BF0_CH3_V << DMA2D_OUTLINK_DSCR_BF0_CH3_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH3_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_DSCR_BF1_CH3_REG (DR_REG_DMA2D_BASE + 0x334)
+/** DMA2D_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH3_M  (DMA2D_OUTLINK_DSCR_BF1_CH3_V << DMA2D_OUTLINK_DSCR_BF1_CH3_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH3_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH3_REG register
+ *  Configures the tx peripheral of channel 3
+ */
+#define DMA2D_OUT_PERI_SEL_CH3_REG (DR_REG_DMA2D_BASE + 0x338)
+/** DMA2D_OUT_PERI_SEL_CH3 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH3    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH3_M  (DMA2D_OUT_PERI_SEL_CH3_V << DMA2D_OUT_PERI_SEL_CH3_S)
+#define DMA2D_OUT_PERI_SEL_CH3_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH3_S  0
+
+/** DMA2D_OUT_ARB_CH3_REG register
+ *  Configures the tx arbiter of channel 3
+ */
+#define DMA2D_OUT_ARB_CH3_REG (DR_REG_DMA2D_BASE + 0x33c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH3_V << DMA2D_OUT_ARB_TOKEN_NUM_CH3_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH3    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH3_M  (DMA2D_OUT_ARB_PRIORITY_CH3_V << DMA2D_OUT_ARB_PRIORITY_CH3_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH3_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH3_S  4
+/** DMA2D_OUT_ARB_PRIORITY_H_CH3 : R/W; bitpos: [7:6]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_H_CH3    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH3_M  (DMA2D_OUT_ARB_PRIORITY_H_CH3_V << DMA2D_OUT_ARB_PRIORITY_H_CH3_S)
+#define DMA2D_OUT_ARB_PRIORITY_H_CH3_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH3_S  6
+
+/** DMA2D_OUT_RO_STATUS_CH3_REG register
+ *  Represents the status of the tx reorder module of channel 3
+ */
+#define DMA2D_OUT_RO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x340)
+/** DMA2D_OUTFIFO_RO_CNT_CH3 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH3    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH3_M  (DMA2D_OUTFIFO_RO_CNT_CH3_V << DMA2D_OUTFIFO_RO_CNT_CH3_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH3_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH3_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH3 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH3    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH3_M  (DMA2D_OUT_RO_WR_STATE_CH3_V << DMA2D_OUT_RO_WR_STATE_CH3_S)
+#define DMA2D_OUT_RO_WR_STATE_CH3_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH3_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH3 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH3    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH3_M  (DMA2D_OUT_RO_RD_STATE_CH3_V << DMA2D_OUT_RO_RD_STATE_CH3_S)
+#define DMA2D_OUT_RO_RD_STATE_CH3_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH3_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH3 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH3    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH3_M  (DMA2D_OUT_PIXEL_BYTE_CH3_V << DMA2D_OUT_PIXEL_BYTE_CH3_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH3_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH3_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH3 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH3_V << DMA2D_OUT_BURST_BLOCK_NUM_CH3_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH3_REG register
+ *  Configures the tx color convert of channel 3
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH3_REG (DR_REG_DMA2D_BASE + 0x348)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH3 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH3_V << DMA2D_OUT_COLOR_INPUT_SEL_CH3_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH3_REG register
+ *  Configures the tx scramble of channel 3
+ */
+#define DMA2D_OUT_SCRAMBLE_CH3_REG (DR_REG_DMA2D_BASE + 0x34c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH3_REG (DR_REG_DMA2D_BASE + 0x350)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH3 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3_M  (DMA2D_OUT_COLOR_PARAM_H0_CH3_V << DMA2D_OUT_COLOR_PARAM_H0_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH3_REG (DR_REG_DMA2D_BASE + 0x354)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH3 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3_M  (DMA2D_OUT_COLOR_PARAM_H1_CH3_V << DMA2D_OUT_COLOR_PARAM_H1_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH3_REG (DR_REG_DMA2D_BASE + 0x358)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH3 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3_M  (DMA2D_OUT_COLOR_PARAM_M0_CH3_V << DMA2D_OUT_COLOR_PARAM_M0_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH3_REG (DR_REG_DMA2D_BASE + 0x35c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH3 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3_M  (DMA2D_OUT_COLOR_PARAM_M1_CH3_V << DMA2D_OUT_COLOR_PARAM_M1_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH3_REG (DR_REG_DMA2D_BASE + 0x360)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH3 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3_M  (DMA2D_OUT_COLOR_PARAM_L0_CH3_V << DMA2D_OUT_COLOR_PARAM_L0_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH3_REG (DR_REG_DMA2D_BASE + 0x364)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH3 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3_M  (DMA2D_OUT_COLOR_PARAM_L1_CH3_V << DMA2D_OUT_COLOR_PARAM_L1_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH3_REG register
+ *  Configures the tx etm of channel 3
+ */
+#define DMA2D_OUT_ETM_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x368)
+/** DMA2D_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH3    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH3_M  (DMA2D_OUT_ETM_EN_CH3_V << DMA2D_OUT_ETM_EN_CH3_S)
+#define DMA2D_OUT_ETM_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH3_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH3    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH3_M  (DMA2D_OUT_ETM_LOOP_EN_CH3_V << DMA2D_OUT_ETM_LOOP_EN_CH3_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH3_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3_M  (DMA2D_OUT_DSCR_TASK_MAK_CH3_V << DMA2D_OUT_DSCR_TASK_MAK_CH3_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH3_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH3_REG (DR_REG_DMA2D_BASE + 0x36c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH3 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH3 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S  14
+
+/** DMA2D_IN_CONF0_CH0_REG register
+ *  Configures the rx direction of channel 0
+ */
+#define DMA2D_IN_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x500)
+/** DMA2D_IN_MEM_TRANS_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH0    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH0_M  (DMA2D_IN_MEM_TRANS_EN_CH0_V << DMA2D_IN_MEM_TRANS_EN_CH0_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH0_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH0_S  0
+/** DMA2D_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH0    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH0_M  (DMA2D_INDSCR_BURST_EN_CH0_V << DMA2D_INDSCR_BURST_EN_CH0_S)
+#define DMA2D_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH0_S  2
+/** DMA2D_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH0    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH0_M  (DMA2D_IN_ECC_AES_EN_CH0_V << DMA2D_IN_ECC_AES_EN_CH0_S)
+#define DMA2D_IN_ECC_AES_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH0_S  3
+/** DMA2D_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH0    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH0_M  (DMA2D_IN_CHECK_OWNER_CH0_V << DMA2D_IN_CHECK_OWNER_CH0_S)
+#define DMA2D_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH0_S  4
+/** DMA2D_IN_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH0    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH0_M  (DMA2D_IN_LOOP_TEST_CH0_V << DMA2D_IN_LOOP_TEST_CH0_S)
+#define DMA2D_IN_LOOP_TEST_CH0_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH0_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_M  (DMA2D_IN_MEM_BURST_LENGTH_CH0_V << DMA2D_IN_MEM_BURST_LENGTH_CH0_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH0    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH0_M  (DMA2D_IN_DSCR_PORT_EN_CH0_V << DMA2D_IN_DSCR_PORT_EN_CH0_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH0_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH0_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH0    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_M  (DMA2D_IN_PAGE_BOUND_EN_CH0_V << DMA2D_IN_PAGE_BOUND_EN_CH0_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_S  12
+/** DMA2D_IN_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH0    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH0_M  (DMA2D_IN_REORDER_EN_CH0_V << DMA2D_IN_REORDER_EN_CH0_S)
+#define DMA2D_IN_REORDER_EN_CH0_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH0_S  16
+/** DMA2D_IN_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH0    (BIT(24))
+#define DMA2D_IN_RST_CH0_M  (DMA2D_IN_RST_CH0_V << DMA2D_IN_RST_CH0_S)
+#define DMA2D_IN_RST_CH0_V  0x00000001U
+#define DMA2D_IN_RST_CH0_S  24
+/** DMA2D_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH0    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH0_M  (DMA2D_IN_CMD_DISABLE_CH0_V << DMA2D_IN_CMD_DISABLE_CH0_S)
+#define DMA2D_IN_CMD_DISABLE_CH0_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH0_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** DMA2D_IN_INT_RAW_CH0_REG register
+ *  Raw interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x504)
+/** DMA2D_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_RAW_M  (DMA2D_IN_DONE_CH0_INT_RAW_V << DMA2D_IN_DONE_CH0_INT_RAW_S)
+#define DMA2D_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH0_INT_RAW_V << DMA2D_IN_SUC_EOF_CH0_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH0_INT_RAW_V << DMA2D_IN_ERR_EOF_CH0_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of RX channel 0
+ */
+#define DMA2D_IN_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x508)
+/** DMA2D_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_ENA_M  (DMA2D_IN_DONE_CH0_INT_ENA_V << DMA2D_IN_DONE_CH0_INT_ENA_S)
+#define DMA2D_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH0_INT_ENA_V << DMA2D_IN_SUC_EOF_CH0_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH0_INT_ENA_V << DMA2D_IN_ERR_EOF_CH0_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH0_REG register
+ *  Masked interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0x50c)
+/** DMA2D_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_ST_M  (DMA2D_IN_DONE_CH0_INT_ST_V << DMA2D_IN_DONE_CH0_INT_ST_S)
+#define DMA2D_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_M  (DMA2D_IN_SUC_EOF_CH0_INT_ST_V << DMA2D_IN_SUC_EOF_CH0_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_M  (DMA2D_IN_ERR_EOF_CH0_INT_ST_V << DMA2D_IN_ERR_EOF_CH0_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH0_INT_ST_V << DMA2D_IN_DSCR_ERR_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of RX channel 0
+ */
+#define DMA2D_IN_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x510)
+/** DMA2D_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_CLR_M  (DMA2D_IN_DONE_CH0_INT_CLR_V << DMA2D_IN_DONE_CH0_INT_CLR_S)
+#define DMA2D_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH0_INT_CLR_V << DMA2D_IN_SUC_EOF_CH0_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH0_INT_CLR_V << DMA2D_IN_ERR_EOF_CH0_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH0_REG register
+ *  Represents the status of the rx fifo of channel 0
+ */
+#define DMA2D_INFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x514)
+/** DMA2D_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH0    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH0_M  (DMA2D_INFIFO_FULL_L2_CH0_V << DMA2D_INFIFO_FULL_L2_CH0_S)
+#define DMA2D_INFIFO_FULL_L2_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH0_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH0    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH0_M  (DMA2D_INFIFO_EMPTY_L2_CH0_V << DMA2D_INFIFO_EMPTY_L2_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH0_S  1
+/** DMA2D_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH0    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH0_M  (DMA2D_INFIFO_CNT_L2_CH0_V << DMA2D_INFIFO_CNT_L2_CH0_S)
+#define DMA2D_INFIFO_CNT_L2_CH0_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH0_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_M  (DMA2D_IN_REMAIN_UNDER_1B_CH0_V << DMA2D_IN_REMAIN_UNDER_1B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_M  (DMA2D_IN_REMAIN_UNDER_2B_CH0_V << DMA2D_IN_REMAIN_UNDER_2B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_M  (DMA2D_IN_REMAIN_UNDER_3B_CH0_V << DMA2D_IN_REMAIN_UNDER_3B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_M  (DMA2D_IN_REMAIN_UNDER_4B_CH0_V << DMA2D_IN_REMAIN_UNDER_4B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_M  (DMA2D_IN_REMAIN_UNDER_5B_CH0_V << DMA2D_IN_REMAIN_UNDER_5B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_M  (DMA2D_IN_REMAIN_UNDER_6B_CH0_V << DMA2D_IN_REMAIN_UNDER_6B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_M  (DMA2D_IN_REMAIN_UNDER_7B_CH0_V << DMA2D_IN_REMAIN_UNDER_7B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_M  (DMA2D_IN_REMAIN_UNDER_8B_CH0_V << DMA2D_IN_REMAIN_UNDER_8B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_S  14
+/** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH0    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH0_M  (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S)
+#define DMA2D_INFIFO_FULL_L1_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH0_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH0    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH0_M  (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH0_S  16
+/** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH0    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH0_M  (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S)
+#define DMA2D_INFIFO_CNT_L1_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH0_S  17
+/** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH0    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH0_M  (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S)
+#define DMA2D_INFIFO_FULL_L3_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH0_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH0    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH0_M  (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH0_S  23
+/** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH0    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH0_M  (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S)
+#define DMA2D_INFIFO_CNT_L3_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH0_S  24
+
+/** DMA2D_IN_POP_CH0_REG register
+ *  Configures the rx fifo of channel 0
+ */
+#define DMA2D_IN_POP_CH0_REG (DR_REG_DMA2D_BASE + 0x518)
+/** DMA2D_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH0    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH0_M  (DMA2D_INFIFO_RDATA_CH0_V << DMA2D_INFIFO_RDATA_CH0_S)
+#define DMA2D_INFIFO_RDATA_CH0_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH0_S  0
+/** DMA2D_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH0    (BIT(11))
+#define DMA2D_INFIFO_POP_CH0_M  (DMA2D_INFIFO_POP_CH0_V << DMA2D_INFIFO_POP_CH0_S)
+#define DMA2D_INFIFO_POP_CH0_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH0_S  11
+
+/** DMA2D_IN_LINK_CONF_CH0_REG register
+ *  Configures the rx descriptor operations of channel 0
+ */
+#define DMA2D_IN_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x51c)
+/** DMA2D_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH0    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH0_M  (DMA2D_INLINK_AUTO_RET_CH0_V << DMA2D_INLINK_AUTO_RET_CH0_S)
+#define DMA2D_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH0_S  20
+/** DMA2D_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH0    (BIT(21))
+#define DMA2D_INLINK_STOP_CH0_M  (DMA2D_INLINK_STOP_CH0_V << DMA2D_INLINK_STOP_CH0_S)
+#define DMA2D_INLINK_STOP_CH0_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH0_S  21
+/** DMA2D_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH0    (BIT(22))
+#define DMA2D_INLINK_START_CH0_M  (DMA2D_INLINK_START_CH0_V << DMA2D_INLINK_START_CH0_S)
+#define DMA2D_INLINK_START_CH0_V  0x00000001U
+#define DMA2D_INLINK_START_CH0_S  22
+/** DMA2D_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH0    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH0_M  (DMA2D_INLINK_RESTART_CH0_V << DMA2D_INLINK_RESTART_CH0_S)
+#define DMA2D_INLINK_RESTART_CH0_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH0_S  23
+/** DMA2D_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH0    (BIT(24))
+#define DMA2D_INLINK_PARK_CH0_M  (DMA2D_INLINK_PARK_CH0_V << DMA2D_INLINK_PARK_CH0_S)
+#define DMA2D_INLINK_PARK_CH0_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH0_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH0_REG register
+ *  Configures the rx descriptor address of channel 0
+ */
+#define DMA2D_IN_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x520)
+/** DMA2D_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH0_M  (DMA2D_INLINK_ADDR_CH0_V << DMA2D_INLINK_ADDR_CH0_S)
+#define DMA2D_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH0_S  0
+
+/** DMA2D_IN_STATE_CH0_REG register
+ *  Represents the working status of the rx descriptor of channel 0
+ */
+#define DMA2D_IN_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x524)
+/** DMA2D_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH0_M  (DMA2D_INLINK_DSCR_ADDR_CH0_V << DMA2D_INLINK_DSCR_ADDR_CH0_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH0_S  0
+/** DMA2D_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH0    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH0_M  (DMA2D_IN_DSCR_STATE_CH0_V << DMA2D_IN_DSCR_STATE_CH0_S)
+#define DMA2D_IN_DSCR_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH0_S  18
+/** DMA2D_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH0    0x00000007U
+#define DMA2D_IN_STATE_CH0_M  (DMA2D_IN_STATE_CH0_V << DMA2D_IN_STATE_CH0_S)
+#define DMA2D_IN_STATE_CH0_V  0x00000007U
+#define DMA2D_IN_STATE_CH0_S  20
+/** DMA2D_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH0    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH0_M  (DMA2D_IN_RESET_AVAIL_CH0_V << DMA2D_IN_RESET_AVAIL_CH0_S)
+#define DMA2D_IN_RESET_AVAIL_CH0_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH0_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x528)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x52c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_IN_DSCR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x530)
+/** DMA2D_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH0_M  (DMA2D_INLINK_DSCR_CH0_V << DMA2D_INLINK_DSCR_CH0_S)
+#define DMA2D_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH0_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x534)
+/** DMA2D_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH0_M  (DMA2D_INLINK_DSCR_BF0_CH0_V << DMA2D_INLINK_DSCR_BF0_CH0_S)
+#define DMA2D_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH0_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x538)
+/** DMA2D_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH0_M  (DMA2D_INLINK_DSCR_BF1_CH0_V << DMA2D_INLINK_DSCR_BF1_CH0_S)
+#define DMA2D_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH0_S  0
+
+/** DMA2D_IN_PERI_SEL_CH0_REG register
+ *  Configures the rx peripheral of channel 0
+ */
+#define DMA2D_IN_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x53c)
+/** DMA2D_IN_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH0    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH0_M  (DMA2D_IN_PERI_SEL_CH0_V << DMA2D_IN_PERI_SEL_CH0_S)
+#define DMA2D_IN_PERI_SEL_CH0_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH0_S  0
+
+/** DMA2D_IN_ARB_CH0_REG register
+ *  Configures the rx arbiter of channel 0
+ */
+#define DMA2D_IN_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x540)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_M  (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH0    (BIT(4))
+#define DMA2D_IN_ARB_PRIORITY_CH0_M  (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S)
+#define DMA2D_IN_ARB_PRIORITY_CH0_V  0x00000001U
+#define DMA2D_IN_ARB_PRIORITY_CH0_S  4
+/** DMA2D_IN_ARB_PRIORITY_H_CH0 : R/W; bitpos: [7:5]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_H_CH0    0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH0_M  (DMA2D_IN_ARB_PRIORITY_H_CH0_V << DMA2D_IN_ARB_PRIORITY_H_CH0_S)
+#define DMA2D_IN_ARB_PRIORITY_H_CH0_V  0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH0_S  5
+
+/** DMA2D_IN_RO_STATUS_CH0_REG register
+ *  Represents the status of the rx reorder module of channel 0
+ */
+#define DMA2D_IN_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x544)
+/** DMA2D_INFIFO_RO_CNT_CH0 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH0    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH0_M  (DMA2D_INFIFO_RO_CNT_CH0_V << DMA2D_INFIFO_RO_CNT_CH0_S)
+#define DMA2D_INFIFO_RO_CNT_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH0_S  0
+/** DMA2D_IN_RO_WR_STATE_CH0 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH0    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH0_M  (DMA2D_IN_RO_WR_STATE_CH0_V << DMA2D_IN_RO_WR_STATE_CH0_S)
+#define DMA2D_IN_RO_WR_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH0_S  5
+/** DMA2D_IN_RO_RD_STATE_CH0 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH0    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH0_M  (DMA2D_IN_RO_RD_STATE_CH0_V << DMA2D_IN_RO_RD_STATE_CH0_S)
+#define DMA2D_IN_RO_RD_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH0_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH0 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH0    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH0_M  (DMA2D_IN_PIXEL_BYTE_CH0_V << DMA2D_IN_PIXEL_BYTE_CH0_S)
+#define DMA2D_IN_PIXEL_BYTE_CH0_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH0_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH0 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_M  (DMA2D_IN_BURST_BLOCK_NUM_CH0_V << DMA2D_IN_BURST_BLOCK_NUM_CH0_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_S  13
+
+/** DMA2D_IN_RO_PD_CONF_CH0_REG register
+ *  Configures the rx reorder memory of channel 0
+ */
+#define DMA2D_IN_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x548)
+/** DMA2D_IN_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_M  (DMA2D_IN_RO_RAM_FORCE_PD_CH0_V << DMA2D_IN_RO_RAM_FORCE_PD_CH0_S)
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_S  4
+/** DMA2D_IN_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_M  (DMA2D_IN_RO_RAM_FORCE_PU_CH0_V << DMA2D_IN_RO_RAM_FORCE_PU_CH0_S)
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_S  5
+/** DMA2D_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_M  (DMA2D_IN_RO_RAM_CLK_FO_CH0_V << DMA2D_IN_RO_RAM_CLK_FO_CH0_S)
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_S  6
+
+/** DMA2D_IN_COLOR_CONVERT_CH0_REG register
+ *  Configures the Rx color convert of channel 0
+ */
+#define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c)
+/** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  output directly     2: YUV444 to YUV422    3: YUV444 to YUV420
+ */
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0    0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M  (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S)
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V  0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S  0
+/** DMA2D_IN_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0    (BIT(2))
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_M  (DMA2D_IN_COLOR_3B_PROC_EN_CH0_V << DMA2D_IN_COLOR_3B_PROC_EN_CH0_S)
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_V  0x00000001U
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_S  2
+/** DMA2D_IN_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+ *  1: YUV422      2: YUV444/420      7: disable color space convert
+ */
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0    0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_M  (DMA2D_IN_COLOR_INPUT_SEL_CH0_V << DMA2D_IN_COLOR_INPUT_SEL_CH0_S)
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_V  0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_S  3
+
+/** DMA2D_IN_SCRAMBLE_CH0_REG register
+ *  Configures the rx scramble of channel 0
+ */
+#define DMA2D_IN_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x550)
+/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_M  (DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S)
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S  0
+/** DMA2D_IN_SCRAMBLE_SEL_POST_CH0 : R/W; bitpos: [5:3]; default: 0;
+ *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+ *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_M  (DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S)
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S  3
+
+/** DMA2D_IN_COLOR_PARAM0_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x554)
+/** DMA2D_IN_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_M  (DMA2D_IN_COLOR_PARAM_H0_CH0_V << DMA2D_IN_COLOR_PARAM_H0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM1_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x558)
+/** DMA2D_IN_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_M  (DMA2D_IN_COLOR_PARAM_H1_CH0_V << DMA2D_IN_COLOR_PARAM_H1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM2_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x55c)
+/** DMA2D_IN_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_M  (DMA2D_IN_COLOR_PARAM_M0_CH0_V << DMA2D_IN_COLOR_PARAM_M0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM3_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x560)
+/** DMA2D_IN_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_M  (DMA2D_IN_COLOR_PARAM_M1_CH0_V << DMA2D_IN_COLOR_PARAM_M1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM4_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x564)
+/** DMA2D_IN_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_M  (DMA2D_IN_COLOR_PARAM_L0_CH0_V << DMA2D_IN_COLOR_PARAM_L0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM5_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x568)
+/** DMA2D_IN_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_M  (DMA2D_IN_COLOR_PARAM_L1_CH0_V << DMA2D_IN_COLOR_PARAM_L1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_S  0
+
+/** DMA2D_IN_ETM_CONF_CH0_REG register
+ *  Configures the rx etm of channel 0
+ */
+#define DMA2D_IN_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x56c)
+/** DMA2D_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH0    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH0_M  (DMA2D_IN_ETM_EN_CH0_V << DMA2D_IN_ETM_EN_CH0_S)
+#define DMA2D_IN_ETM_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH0_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH0    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH0_M  (DMA2D_IN_ETM_LOOP_EN_CH0_V << DMA2D_IN_ETM_LOOP_EN_CH0_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH0_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH0    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_M  (DMA2D_IN_DSCR_TASK_MAK_CH0_V << DMA2D_IN_DSCR_TASK_MAK_CH0_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_S  2
+
+/** DMA2D_IN_CONF0_CH1_REG register
+ *  Configures the rx direction of channel 1
+ */
+#define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600)
+/** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH1    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH1_M  (DMA2D_IN_MEM_TRANS_EN_CH1_V << DMA2D_IN_MEM_TRANS_EN_CH1_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH1_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH1_S  0
+/** DMA2D_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH1    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH1_M  (DMA2D_INDSCR_BURST_EN_CH1_V << DMA2D_INDSCR_BURST_EN_CH1_S)
+#define DMA2D_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH1_S  2
+/** DMA2D_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH1    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH1_M  (DMA2D_IN_ECC_AES_EN_CH1_V << DMA2D_IN_ECC_AES_EN_CH1_S)
+#define DMA2D_IN_ECC_AES_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH1_S  3
+/** DMA2D_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH1    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH1_M  (DMA2D_IN_CHECK_OWNER_CH1_V << DMA2D_IN_CHECK_OWNER_CH1_S)
+#define DMA2D_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH1_S  4
+/** DMA2D_IN_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH1    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH1_M  (DMA2D_IN_LOOP_TEST_CH1_V << DMA2D_IN_LOOP_TEST_CH1_S)
+#define DMA2D_IN_LOOP_TEST_CH1_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH1_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_M  (DMA2D_IN_MEM_BURST_LENGTH_CH1_V << DMA2D_IN_MEM_BURST_LENGTH_CH1_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH1    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH1_M  (DMA2D_IN_DSCR_PORT_EN_CH1_V << DMA2D_IN_DSCR_PORT_EN_CH1_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH1_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH1_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH1    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_M  (DMA2D_IN_PAGE_BOUND_EN_CH1_V << DMA2D_IN_PAGE_BOUND_EN_CH1_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_S  12
+/** DMA2D_IN_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH1    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH1_M  (DMA2D_IN_REORDER_EN_CH1_V << DMA2D_IN_REORDER_EN_CH1_S)
+#define DMA2D_IN_REORDER_EN_CH1_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH1_S  16
+/** DMA2D_IN_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH1    (BIT(24))
+#define DMA2D_IN_RST_CH1_M  (DMA2D_IN_RST_CH1_V << DMA2D_IN_RST_CH1_S)
+#define DMA2D_IN_RST_CH1_V  0x00000001U
+#define DMA2D_IN_RST_CH1_S  24
+/** DMA2D_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH1    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH1_M  (DMA2D_IN_CMD_DISABLE_CH1_V << DMA2D_IN_CMD_DISABLE_CH1_S)
+#define DMA2D_IN_CMD_DISABLE_CH1_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH1_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** DMA2D_IN_INT_RAW_CH1_REG register
+ *  Raw interrupt status of RX channel 1
+ */
+#define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604)
+/** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_RAW_M  (DMA2D_IN_DONE_CH1_INT_RAW_V << DMA2D_IN_DONE_CH1_INT_RAW_S)
+#define DMA2D_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH1_INT_RAW_V << DMA2D_IN_SUC_EOF_CH1_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH1_INT_RAW_V << DMA2D_IN_ERR_EOF_CH1_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of RX channel 1
+ */
+#define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608)
+/** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_ENA_M  (DMA2D_IN_DONE_CH1_INT_ENA_V << DMA2D_IN_DONE_CH1_INT_ENA_S)
+#define DMA2D_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH1_INT_ENA_V << DMA2D_IN_SUC_EOF_CH1_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH1_INT_ENA_V << DMA2D_IN_ERR_EOF_CH1_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH1_REG register
+ *  Masked interrupt status of RX channel 1
+ */
+#define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c)
+/** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_ST_M  (DMA2D_IN_DONE_CH1_INT_ST_V << DMA2D_IN_DONE_CH1_INT_ST_S)
+#define DMA2D_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_M  (DMA2D_IN_SUC_EOF_CH1_INT_ST_V << DMA2D_IN_SUC_EOF_CH1_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_M  (DMA2D_IN_ERR_EOF_CH1_INT_ST_V << DMA2D_IN_ERR_EOF_CH1_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH1_INT_ST_V << DMA2D_IN_DSCR_ERR_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of RX channel 1
+ */
+#define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610)
+/** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_CLR_M  (DMA2D_IN_DONE_CH1_INT_CLR_V << DMA2D_IN_DONE_CH1_INT_CLR_S)
+#define DMA2D_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH1_INT_CLR_V << DMA2D_IN_SUC_EOF_CH1_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH1_INT_CLR_V << DMA2D_IN_ERR_EOF_CH1_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH1_REG register
+ *  Represents the status of the rx fifo of channel 1
+ */
+#define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614)
+/** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH1    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH1_M  (DMA2D_INFIFO_FULL_L2_CH1_V << DMA2D_INFIFO_FULL_L2_CH1_S)
+#define DMA2D_INFIFO_FULL_L2_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH1_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH1    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH1_M  (DMA2D_INFIFO_EMPTY_L2_CH1_V << DMA2D_INFIFO_EMPTY_L2_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH1_S  1
+/** DMA2D_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH1    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH1_M  (DMA2D_INFIFO_CNT_L2_CH1_V << DMA2D_INFIFO_CNT_L2_CH1_S)
+#define DMA2D_INFIFO_CNT_L2_CH1_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH1_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_M  (DMA2D_IN_REMAIN_UNDER_1B_CH1_V << DMA2D_IN_REMAIN_UNDER_1B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_M  (DMA2D_IN_REMAIN_UNDER_2B_CH1_V << DMA2D_IN_REMAIN_UNDER_2B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_M  (DMA2D_IN_REMAIN_UNDER_3B_CH1_V << DMA2D_IN_REMAIN_UNDER_3B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_M  (DMA2D_IN_REMAIN_UNDER_4B_CH1_V << DMA2D_IN_REMAIN_UNDER_4B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_M  (DMA2D_IN_REMAIN_UNDER_5B_CH1_V << DMA2D_IN_REMAIN_UNDER_5B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_M  (DMA2D_IN_REMAIN_UNDER_6B_CH1_V << DMA2D_IN_REMAIN_UNDER_6B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_M  (DMA2D_IN_REMAIN_UNDER_7B_CH1_V << DMA2D_IN_REMAIN_UNDER_7B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_M  (DMA2D_IN_REMAIN_UNDER_8B_CH1_V << DMA2D_IN_REMAIN_UNDER_8B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_S  14
+/** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH1    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH1_M  (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S)
+#define DMA2D_INFIFO_FULL_L1_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH1_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH1    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH1_M  (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH1_S  16
+/** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH1    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH1_M  (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S)
+#define DMA2D_INFIFO_CNT_L1_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH1_S  17
+/** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH1    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH1_M  (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S)
+#define DMA2D_INFIFO_FULL_L3_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH1_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH1    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH1_M  (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH1_S  23
+/** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH1    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH1_M  (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S)
+#define DMA2D_INFIFO_CNT_L3_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH1_S  24
+
+/** DMA2D_IN_POP_CH1_REG register
+ *  Configures the rx fifo of channel 1
+ */
+#define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618)
+/** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH1    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH1_M  (DMA2D_INFIFO_RDATA_CH1_V << DMA2D_INFIFO_RDATA_CH1_S)
+#define DMA2D_INFIFO_RDATA_CH1_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH1_S  0
+/** DMA2D_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH1    (BIT(11))
+#define DMA2D_INFIFO_POP_CH1_M  (DMA2D_INFIFO_POP_CH1_V << DMA2D_INFIFO_POP_CH1_S)
+#define DMA2D_INFIFO_POP_CH1_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH1_S  11
+
+/** DMA2D_IN_LINK_CONF_CH1_REG register
+ *  Configures the rx descriptor operations of channel 1
+ */
+#define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c)
+/** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH1    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH1_M  (DMA2D_INLINK_AUTO_RET_CH1_V << DMA2D_INLINK_AUTO_RET_CH1_S)
+#define DMA2D_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH1_S  20
+/** DMA2D_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH1    (BIT(21))
+#define DMA2D_INLINK_STOP_CH1_M  (DMA2D_INLINK_STOP_CH1_V << DMA2D_INLINK_STOP_CH1_S)
+#define DMA2D_INLINK_STOP_CH1_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH1_S  21
+/** DMA2D_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH1    (BIT(22))
+#define DMA2D_INLINK_START_CH1_M  (DMA2D_INLINK_START_CH1_V << DMA2D_INLINK_START_CH1_S)
+#define DMA2D_INLINK_START_CH1_V  0x00000001U
+#define DMA2D_INLINK_START_CH1_S  22
+/** DMA2D_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH1    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH1_M  (DMA2D_INLINK_RESTART_CH1_V << DMA2D_INLINK_RESTART_CH1_S)
+#define DMA2D_INLINK_RESTART_CH1_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH1_S  23
+/** DMA2D_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH1    (BIT(24))
+#define DMA2D_INLINK_PARK_CH1_M  (DMA2D_INLINK_PARK_CH1_V << DMA2D_INLINK_PARK_CH1_S)
+#define DMA2D_INLINK_PARK_CH1_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH1_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH1_REG register
+ *  Configures the rx descriptor address of channel 1
+ */
+#define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620)
+/** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH1_M  (DMA2D_INLINK_ADDR_CH1_V << DMA2D_INLINK_ADDR_CH1_S)
+#define DMA2D_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH1_S  0
+
+/** DMA2D_IN_STATE_CH1_REG register
+ *  Represents the working status of the rx descriptor of channel 1
+ */
+#define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624)
+/** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH1_M  (DMA2D_INLINK_DSCR_ADDR_CH1_V << DMA2D_INLINK_DSCR_ADDR_CH1_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH1_S  0
+/** DMA2D_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH1    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH1_M  (DMA2D_IN_DSCR_STATE_CH1_V << DMA2D_IN_DSCR_STATE_CH1_S)
+#define DMA2D_IN_DSCR_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH1_S  18
+/** DMA2D_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH1    0x00000007U
+#define DMA2D_IN_STATE_CH1_M  (DMA2D_IN_STATE_CH1_V << DMA2D_IN_STATE_CH1_S)
+#define DMA2D_IN_STATE_CH1_V  0x00000007U
+#define DMA2D_IN_STATE_CH1_S  20
+/** DMA2D_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH1    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH1_M  (DMA2D_IN_RESET_AVAIL_CH1_V << DMA2D_IN_RESET_AVAIL_CH1_S)
+#define DMA2D_IN_RESET_AVAIL_CH1_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH1_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_IN_DSCR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630)
+/** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH1_M  (DMA2D_INLINK_DSCR_CH1_V << DMA2D_INLINK_DSCR_CH1_S)
+#define DMA2D_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH1_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634)
+/** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH1_M  (DMA2D_INLINK_DSCR_BF0_CH1_V << DMA2D_INLINK_DSCR_BF0_CH1_S)
+#define DMA2D_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH1_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638)
+/** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH1_M  (DMA2D_INLINK_DSCR_BF1_CH1_V << DMA2D_INLINK_DSCR_BF1_CH1_S)
+#define DMA2D_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH1_S  0
+
+/** DMA2D_IN_PERI_SEL_CH1_REG register
+ *  Configures the rx peripheral of channel 1
+ */
+#define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c)
+/** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH1    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH1_M  (DMA2D_IN_PERI_SEL_CH1_V << DMA2D_IN_PERI_SEL_CH1_S)
+#define DMA2D_IN_PERI_SEL_CH1_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH1_S  0
+
+/** DMA2D_IN_ARB_CH1_REG register
+ *  Configures the rx arbiter of channel 1
+ */
+#define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_M  (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH1    (BIT(4))
+#define DMA2D_IN_ARB_PRIORITY_CH1_M  (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S)
+#define DMA2D_IN_ARB_PRIORITY_CH1_V  0x00000001U
+#define DMA2D_IN_ARB_PRIORITY_CH1_S  4
+/** DMA2D_IN_ARB_PRIORITY_H_CH1 : R/W; bitpos: [7:5]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_H_CH1    0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH1_M  (DMA2D_IN_ARB_PRIORITY_H_CH1_V << DMA2D_IN_ARB_PRIORITY_H_CH1_S)
+#define DMA2D_IN_ARB_PRIORITY_H_CH1_V  0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH1_S  5
+
+/** DMA2D_IN_RO_STATUS_CH1_REG register
+ *  Represents the status of the rx reorder module of channel 1
+ */
+#define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644)
+/** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH1    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH1_M  (DMA2D_INFIFO_RO_CNT_CH1_V << DMA2D_INFIFO_RO_CNT_CH1_S)
+#define DMA2D_INFIFO_RO_CNT_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH1_S  0
+/** DMA2D_IN_RO_WR_STATE_CH1 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH1    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH1_M  (DMA2D_IN_RO_WR_STATE_CH1_V << DMA2D_IN_RO_WR_STATE_CH1_S)
+#define DMA2D_IN_RO_WR_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH1_S  5
+/** DMA2D_IN_RO_RD_STATE_CH1 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH1    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH1_M  (DMA2D_IN_RO_RD_STATE_CH1_V << DMA2D_IN_RO_RD_STATE_CH1_S)
+#define DMA2D_IN_RO_RD_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH1_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH1 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH1    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH1_M  (DMA2D_IN_PIXEL_BYTE_CH1_V << DMA2D_IN_PIXEL_BYTE_CH1_S)
+#define DMA2D_IN_PIXEL_BYTE_CH1_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH1_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH1 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_M  (DMA2D_IN_BURST_BLOCK_NUM_CH1_V << DMA2D_IN_BURST_BLOCK_NUM_CH1_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_S  13
+
+/** DMA2D_IN_RO_PD_CONF_CH1_REG register
+ *  Configures the rx reorder memory of channel 1
+ */
+#define DMA2D_IN_RO_PD_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x648)
+/** DMA2D_IN_RO_RAM_FORCE_PD_CH1 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH1    (BIT(4))
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_M  (DMA2D_IN_RO_RAM_FORCE_PD_CH1_V << DMA2D_IN_RO_RAM_FORCE_PD_CH1_S)
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_S  4
+/** DMA2D_IN_RO_RAM_FORCE_PU_CH1 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH1    (BIT(5))
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_M  (DMA2D_IN_RO_RAM_FORCE_PU_CH1_V << DMA2D_IN_RO_RAM_FORCE_PU_CH1_S)
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_S  5
+/** DMA2D_IN_RO_RAM_CLK_FO_CH1 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_IN_RO_RAM_CLK_FO_CH1    (BIT(6))
+#define DMA2D_IN_RO_RAM_CLK_FO_CH1_M  (DMA2D_IN_RO_RAM_CLK_FO_CH1_V << DMA2D_IN_RO_RAM_CLK_FO_CH1_S)
+#define DMA2D_IN_RO_RAM_CLK_FO_CH1_V  0x00000001U
+#define DMA2D_IN_RO_RAM_CLK_FO_CH1_S  6
+
+/** DMA2D_IN_COLOR_CONVERT_CH1_REG register
+ *  Configures the Rx color convert of channel 1
+ */
+#define DMA2D_IN_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x64c)
+/** DMA2D_IN_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  output directly     2: YUV444 to YUV422    3: YUV444 to YUV420
+ */
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1    0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_M  (DMA2D_IN_COLOR_OUTPUT_SEL_CH1_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH1_S)
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_V  0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_S  0
+/** DMA2D_IN_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH1    (BIT(2))
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_M  (DMA2D_IN_COLOR_3B_PROC_EN_CH1_V << DMA2D_IN_COLOR_3B_PROC_EN_CH1_S)
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_V  0x00000001U
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_S  2
+/** DMA2D_IN_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+ *  1: YUV422      2: YUV444/420      7: disable color space convert
+ */
+#define DMA2D_IN_COLOR_INPUT_SEL_CH1    0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH1_M  (DMA2D_IN_COLOR_INPUT_SEL_CH1_V << DMA2D_IN_COLOR_INPUT_SEL_CH1_S)
+#define DMA2D_IN_COLOR_INPUT_SEL_CH1_V  0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH1_S  3
+
+/** DMA2D_IN_SCRAMBLE_CH1_REG register
+ *  Configures the rx scramble of channel 1
+ */
+#define DMA2D_IN_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x650)
+/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_M  (DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_S)
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_S  0
+/** DMA2D_IN_SCRAMBLE_SEL_POST_CH1 : R/W; bitpos: [5:3]; default: 0;
+ *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+ *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_M  (DMA2D_IN_SCRAMBLE_SEL_POST_CH1_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH1_S)
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_S  3
+
+/** DMA2D_IN_COLOR_PARAM0_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x654)
+/** DMA2D_IN_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H0_CH1    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH1_M  (DMA2D_IN_COLOR_PARAM_H0_CH1_V << DMA2D_IN_COLOR_PARAM_H0_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_H0_CH1_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH1_S  0
+
+/** DMA2D_IN_COLOR_PARAM1_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x658)
+/** DMA2D_IN_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H1_CH1    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH1_M  (DMA2D_IN_COLOR_PARAM_H1_CH1_V << DMA2D_IN_COLOR_PARAM_H1_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_H1_CH1_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH1_S  0
+
+/** DMA2D_IN_COLOR_PARAM2_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x65c)
+/** DMA2D_IN_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M0_CH1    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH1_M  (DMA2D_IN_COLOR_PARAM_M0_CH1_V << DMA2D_IN_COLOR_PARAM_M0_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_M0_CH1_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH1_S  0
+
+/** DMA2D_IN_COLOR_PARAM3_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x660)
+/** DMA2D_IN_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M1_CH1    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH1_M  (DMA2D_IN_COLOR_PARAM_M1_CH1_V << DMA2D_IN_COLOR_PARAM_M1_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_M1_CH1_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH1_S  0
+
+/** DMA2D_IN_COLOR_PARAM4_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x664)
+/** DMA2D_IN_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L0_CH1    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH1_M  (DMA2D_IN_COLOR_PARAM_L0_CH1_V << DMA2D_IN_COLOR_PARAM_L0_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_L0_CH1_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH1_S  0
+
+/** DMA2D_IN_COLOR_PARAM5_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x668)
+/** DMA2D_IN_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L1_CH1    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH1_M  (DMA2D_IN_COLOR_PARAM_L1_CH1_V << DMA2D_IN_COLOR_PARAM_L1_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_L1_CH1_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH1_S  0
+
+/** DMA2D_IN_ETM_CONF_CH1_REG register
+ *  Configures the rx etm of channel 1
+ */
+#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x66c)
+/** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH1    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH1_M  (DMA2D_IN_ETM_EN_CH1_V << DMA2D_IN_ETM_EN_CH1_S)
+#define DMA2D_IN_ETM_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH1_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH1    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH1_M  (DMA2D_IN_ETM_LOOP_EN_CH1_V << DMA2D_IN_ETM_LOOP_EN_CH1_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH1_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH1    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_M  (DMA2D_IN_DSCR_TASK_MAK_CH1_V << DMA2D_IN_DSCR_TASK_MAK_CH1_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_S  2
+
+/** DMA2D_IN_CONF0_CH2_REG register
+ *  Configures the rx direction of channel 2
+ */
+#define DMA2D_IN_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x700)
+/** DMA2D_IN_MEM_TRANS_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH2    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH2_M  (DMA2D_IN_MEM_TRANS_EN_CH2_V << DMA2D_IN_MEM_TRANS_EN_CH2_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH2_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH2_S  0
+/** DMA2D_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH2    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH2_M  (DMA2D_INDSCR_BURST_EN_CH2_V << DMA2D_INDSCR_BURST_EN_CH2_S)
+#define DMA2D_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH2_S  2
+/** DMA2D_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH2    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH2_M  (DMA2D_IN_ECC_AES_EN_CH2_V << DMA2D_IN_ECC_AES_EN_CH2_S)
+#define DMA2D_IN_ECC_AES_EN_CH2_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH2_S  3
+/** DMA2D_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH2    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH2_M  (DMA2D_IN_CHECK_OWNER_CH2_V << DMA2D_IN_CHECK_OWNER_CH2_S)
+#define DMA2D_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH2_S  4
+/** DMA2D_IN_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH2    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH2_M  (DMA2D_IN_LOOP_TEST_CH2_V << DMA2D_IN_LOOP_TEST_CH2_S)
+#define DMA2D_IN_LOOP_TEST_CH2_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH2_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2_M  (DMA2D_IN_MEM_BURST_LENGTH_CH2_V << DMA2D_IN_MEM_BURST_LENGTH_CH2_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH2    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH2_M  (DMA2D_IN_DSCR_PORT_EN_CH2_V << DMA2D_IN_DSCR_PORT_EN_CH2_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH2_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH2_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH2    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH2_M  (DMA2D_IN_PAGE_BOUND_EN_CH2_V << DMA2D_IN_PAGE_BOUND_EN_CH2_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH2_S  12
+/** DMA2D_IN_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH2    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH2_M  (DMA2D_IN_REORDER_EN_CH2_V << DMA2D_IN_REORDER_EN_CH2_S)
+#define DMA2D_IN_REORDER_EN_CH2_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH2_S  16
+/** DMA2D_IN_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH2    (BIT(24))
+#define DMA2D_IN_RST_CH2_M  (DMA2D_IN_RST_CH2_V << DMA2D_IN_RST_CH2_S)
+#define DMA2D_IN_RST_CH2_V  0x00000001U
+#define DMA2D_IN_RST_CH2_S  24
+/** DMA2D_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH2    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH2_M  (DMA2D_IN_CMD_DISABLE_CH2_V << DMA2D_IN_CMD_DISABLE_CH2_S)
+#define DMA2D_IN_CMD_DISABLE_CH2_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH2_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** DMA2D_IN_INT_RAW_CH2_REG register
+ *  Raw interrupt status of RX channel 2
+ */
+#define DMA2D_IN_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x704)
+/** DMA2D_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_RAW_M  (DMA2D_IN_DONE_CH2_INT_RAW_V << DMA2D_IN_DONE_CH2_INT_RAW_S)
+#define DMA2D_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH2_INT_RAW_V << DMA2D_IN_SUC_EOF_CH2_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH2_INT_RAW_V << DMA2D_IN_ERR_EOF_CH2_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of RX channel 2
+ */
+#define DMA2D_IN_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x708)
+/** DMA2D_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_ENA_M  (DMA2D_IN_DONE_CH2_INT_ENA_V << DMA2D_IN_DONE_CH2_INT_ENA_S)
+#define DMA2D_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH2_INT_ENA_V << DMA2D_IN_SUC_EOF_CH2_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH2_INT_ENA_V << DMA2D_IN_ERR_EOF_CH2_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH2_REG register
+ *  Masked interrupt status of RX channel 2
+ */
+#define DMA2D_IN_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x70c)
+/** DMA2D_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH2_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_ST_M  (DMA2D_IN_DONE_CH2_INT_ST_V << DMA2D_IN_DONE_CH2_INT_ST_S)
+#define DMA2D_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST_M  (DMA2D_IN_SUC_EOF_CH2_INT_ST_V << DMA2D_IN_SUC_EOF_CH2_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST_M  (DMA2D_IN_ERR_EOF_CH2_INT_ST_V << DMA2D_IN_ERR_EOF_CH2_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH2_INT_ST_V << DMA2D_IN_DSCR_ERR_CH2_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of RX channel 2
+ */
+#define DMA2D_IN_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x710)
+/** DMA2D_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_CLR_M  (DMA2D_IN_DONE_CH2_INT_CLR_V << DMA2D_IN_DONE_CH2_INT_CLR_S)
+#define DMA2D_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH2_INT_CLR_V << DMA2D_IN_SUC_EOF_CH2_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH2_INT_CLR_V << DMA2D_IN_ERR_EOF_CH2_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH2_REG register
+ *  Represents the status of the rx fifo of channel 2
+ */
+#define DMA2D_INFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x714)
+/** DMA2D_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH2    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH2_M  (DMA2D_INFIFO_FULL_L2_CH2_V << DMA2D_INFIFO_FULL_L2_CH2_S)
+#define DMA2D_INFIFO_FULL_L2_CH2_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH2_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH2    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH2_M  (DMA2D_INFIFO_EMPTY_L2_CH2_V << DMA2D_INFIFO_EMPTY_L2_CH2_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH2_S  1
+/** DMA2D_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH2    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH2_M  (DMA2D_INFIFO_CNT_L2_CH2_V << DMA2D_INFIFO_CNT_L2_CH2_S)
+#define DMA2D_INFIFO_CNT_L2_CH2_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH2_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2_M  (DMA2D_IN_REMAIN_UNDER_1B_CH2_V << DMA2D_IN_REMAIN_UNDER_1B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2_M  (DMA2D_IN_REMAIN_UNDER_2B_CH2_V << DMA2D_IN_REMAIN_UNDER_2B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2_M  (DMA2D_IN_REMAIN_UNDER_3B_CH2_V << DMA2D_IN_REMAIN_UNDER_3B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2_M  (DMA2D_IN_REMAIN_UNDER_4B_CH2_V << DMA2D_IN_REMAIN_UNDER_4B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2_M  (DMA2D_IN_REMAIN_UNDER_5B_CH2_V << DMA2D_IN_REMAIN_UNDER_5B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2_M  (DMA2D_IN_REMAIN_UNDER_6B_CH2_V << DMA2D_IN_REMAIN_UNDER_6B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2_M  (DMA2D_IN_REMAIN_UNDER_7B_CH2_V << DMA2D_IN_REMAIN_UNDER_7B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2_M  (DMA2D_IN_REMAIN_UNDER_8B_CH2_V << DMA2D_IN_REMAIN_UNDER_8B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2_S  14
+/** DMA2D_INFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH2    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH2_M  (DMA2D_INFIFO_FULL_L1_CH2_V << DMA2D_INFIFO_FULL_L1_CH2_S)
+#define DMA2D_INFIFO_FULL_L1_CH2_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH2_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH2    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH2_M  (DMA2D_INFIFO_EMPTY_L1_CH2_V << DMA2D_INFIFO_EMPTY_L1_CH2_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH2_S  16
+/** DMA2D_INFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH2    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH2_M  (DMA2D_INFIFO_CNT_L1_CH2_V << DMA2D_INFIFO_CNT_L1_CH2_S)
+#define DMA2D_INFIFO_CNT_L1_CH2_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH2_S  17
+/** DMA2D_INFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH2    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH2_M  (DMA2D_INFIFO_FULL_L3_CH2_V << DMA2D_INFIFO_FULL_L3_CH2_S)
+#define DMA2D_INFIFO_FULL_L3_CH2_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH2_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH2    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH2_M  (DMA2D_INFIFO_EMPTY_L3_CH2_V << DMA2D_INFIFO_EMPTY_L3_CH2_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH2_S  23
+/** DMA2D_INFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH2    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH2_M  (DMA2D_INFIFO_CNT_L3_CH2_V << DMA2D_INFIFO_CNT_L3_CH2_S)
+#define DMA2D_INFIFO_CNT_L3_CH2_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH2_S  24
+
+/** DMA2D_IN_POP_CH2_REG register
+ *  Configures the rx fifo of channel 2
+ */
+#define DMA2D_IN_POP_CH2_REG (DR_REG_DMA2D_BASE + 0x718)
+/** DMA2D_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH2    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH2_M  (DMA2D_INFIFO_RDATA_CH2_V << DMA2D_INFIFO_RDATA_CH2_S)
+#define DMA2D_INFIFO_RDATA_CH2_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH2_S  0
+/** DMA2D_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH2    (BIT(11))
+#define DMA2D_INFIFO_POP_CH2_M  (DMA2D_INFIFO_POP_CH2_V << DMA2D_INFIFO_POP_CH2_S)
+#define DMA2D_INFIFO_POP_CH2_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH2_S  11
+
+/** DMA2D_IN_LINK_CONF_CH2_REG register
+ *  Configures the rx descriptor operations of channel 2
+ */
+#define DMA2D_IN_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x71c)
+/** DMA2D_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH2    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH2_M  (DMA2D_INLINK_AUTO_RET_CH2_V << DMA2D_INLINK_AUTO_RET_CH2_S)
+#define DMA2D_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH2_S  20
+/** DMA2D_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH2    (BIT(21))
+#define DMA2D_INLINK_STOP_CH2_M  (DMA2D_INLINK_STOP_CH2_V << DMA2D_INLINK_STOP_CH2_S)
+#define DMA2D_INLINK_STOP_CH2_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH2_S  21
+/** DMA2D_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH2    (BIT(22))
+#define DMA2D_INLINK_START_CH2_M  (DMA2D_INLINK_START_CH2_V << DMA2D_INLINK_START_CH2_S)
+#define DMA2D_INLINK_START_CH2_V  0x00000001U
+#define DMA2D_INLINK_START_CH2_S  22
+/** DMA2D_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH2    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH2_M  (DMA2D_INLINK_RESTART_CH2_V << DMA2D_INLINK_RESTART_CH2_S)
+#define DMA2D_INLINK_RESTART_CH2_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH2_S  23
+/** DMA2D_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH2    (BIT(24))
+#define DMA2D_INLINK_PARK_CH2_M  (DMA2D_INLINK_PARK_CH2_V << DMA2D_INLINK_PARK_CH2_S)
+#define DMA2D_INLINK_PARK_CH2_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH2_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH2_REG register
+ *  Configures the rx descriptor address of channel 2
+ */
+#define DMA2D_IN_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x720)
+/** DMA2D_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH2_M  (DMA2D_INLINK_ADDR_CH2_V << DMA2D_INLINK_ADDR_CH2_S)
+#define DMA2D_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH2_S  0
+
+/** DMA2D_IN_STATE_CH2_REG register
+ *  Represents the working status of the rx descriptor of channel 2
+ */
+#define DMA2D_IN_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x724)
+/** DMA2D_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH2_M  (DMA2D_INLINK_DSCR_ADDR_CH2_V << DMA2D_INLINK_DSCR_ADDR_CH2_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH2_S  0
+/** DMA2D_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH2    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH2_M  (DMA2D_IN_DSCR_STATE_CH2_V << DMA2D_IN_DSCR_STATE_CH2_S)
+#define DMA2D_IN_DSCR_STATE_CH2_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH2_S  18
+/** DMA2D_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH2    0x00000007U
+#define DMA2D_IN_STATE_CH2_M  (DMA2D_IN_STATE_CH2_V << DMA2D_IN_STATE_CH2_S)
+#define DMA2D_IN_STATE_CH2_V  0x00000007U
+#define DMA2D_IN_STATE_CH2_S  20
+/** DMA2D_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH2    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH2_M  (DMA2D_IN_RESET_AVAIL_CH2_V << DMA2D_IN_RESET_AVAIL_CH2_S)
+#define DMA2D_IN_RESET_AVAIL_CH2_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH2_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x728)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x72c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_IN_DSCR_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x730)
+/** DMA2D_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH2_M  (DMA2D_INLINK_DSCR_CH2_V << DMA2D_INLINK_DSCR_CH2_S)
+#define DMA2D_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH2_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x734)
+/** DMA2D_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH2_M  (DMA2D_INLINK_DSCR_BF0_CH2_V << DMA2D_INLINK_DSCR_BF0_CH2_S)
+#define DMA2D_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH2_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x738)
+/** DMA2D_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH2_M  (DMA2D_INLINK_DSCR_BF1_CH2_V << DMA2D_INLINK_DSCR_BF1_CH2_S)
+#define DMA2D_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH2_S  0
+
+/** DMA2D_IN_PERI_SEL_CH2_REG register
+ *  Configures the rx peripheral of channel 2
+ */
+#define DMA2D_IN_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x73c)
+/** DMA2D_IN_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH2    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH2_M  (DMA2D_IN_PERI_SEL_CH2_V << DMA2D_IN_PERI_SEL_CH2_S)
+#define DMA2D_IN_PERI_SEL_CH2_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH2_S  0
+
+/** DMA2D_IN_ARB_CH2_REG register
+ *  Configures the rx arbiter of channel 2
+ */
+#define DMA2D_IN_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x740)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2_M  (DMA2D_IN_ARB_TOKEN_NUM_CH2_V << DMA2D_IN_ARB_TOKEN_NUM_CH2_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH2    (BIT(4))
+#define DMA2D_IN_ARB_PRIORITY_CH2_M  (DMA2D_IN_ARB_PRIORITY_CH2_V << DMA2D_IN_ARB_PRIORITY_CH2_S)
+#define DMA2D_IN_ARB_PRIORITY_CH2_V  0x00000001U
+#define DMA2D_IN_ARB_PRIORITY_CH2_S  4
+/** DMA2D_IN_ARB_PRIORITY_H_CH2 : R/W; bitpos: [7:5]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_H_CH2    0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH2_M  (DMA2D_IN_ARB_PRIORITY_H_CH2_V << DMA2D_IN_ARB_PRIORITY_H_CH2_S)
+#define DMA2D_IN_ARB_PRIORITY_H_CH2_V  0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH2_S  5
+
+/** DMA2D_IN_RO_STATUS_CH2_REG register
+ *  Represents the status of the rx reorder module of channel 2
+ */
+#define DMA2D_IN_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x744)
+/** DMA2D_INFIFO_RO_CNT_CH2 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH2    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH2_M  (DMA2D_INFIFO_RO_CNT_CH2_V << DMA2D_INFIFO_RO_CNT_CH2_S)
+#define DMA2D_INFIFO_RO_CNT_CH2_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH2_S  0
+/** DMA2D_IN_RO_WR_STATE_CH2 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH2    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH2_M  (DMA2D_IN_RO_WR_STATE_CH2_V << DMA2D_IN_RO_WR_STATE_CH2_S)
+#define DMA2D_IN_RO_WR_STATE_CH2_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH2_S  5
+/** DMA2D_IN_RO_RD_STATE_CH2 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH2    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH2_M  (DMA2D_IN_RO_RD_STATE_CH2_V << DMA2D_IN_RO_RD_STATE_CH2_S)
+#define DMA2D_IN_RO_RD_STATE_CH2_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH2_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH2 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH2    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH2_M  (DMA2D_IN_PIXEL_BYTE_CH2_V << DMA2D_IN_PIXEL_BYTE_CH2_S)
+#define DMA2D_IN_PIXEL_BYTE_CH2_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH2_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH2 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2_M  (DMA2D_IN_BURST_BLOCK_NUM_CH2_V << DMA2D_IN_BURST_BLOCK_NUM_CH2_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2_S  13
+
+/** DMA2D_IN_RO_PD_CONF_CH2_REG register
+ *  Configures the rx reorder memory of channel 2
+ */
+#define DMA2D_IN_RO_PD_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x748)
+/** DMA2D_IN_RO_RAM_FORCE_PD_CH2 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH2    (BIT(4))
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_M  (DMA2D_IN_RO_RAM_FORCE_PD_CH2_V << DMA2D_IN_RO_RAM_FORCE_PD_CH2_S)
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_S  4
+/** DMA2D_IN_RO_RAM_FORCE_PU_CH2 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH2    (BIT(5))
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_M  (DMA2D_IN_RO_RAM_FORCE_PU_CH2_V << DMA2D_IN_RO_RAM_FORCE_PU_CH2_S)
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_S  5
+/** DMA2D_IN_RO_RAM_CLK_FO_CH2 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_IN_RO_RAM_CLK_FO_CH2    (BIT(6))
+#define DMA2D_IN_RO_RAM_CLK_FO_CH2_M  (DMA2D_IN_RO_RAM_CLK_FO_CH2_V << DMA2D_IN_RO_RAM_CLK_FO_CH2_S)
+#define DMA2D_IN_RO_RAM_CLK_FO_CH2_V  0x00000001U
+#define DMA2D_IN_RO_RAM_CLK_FO_CH2_S  6
+
+/** DMA2D_IN_COLOR_CONVERT_CH2_REG register
+ *  Configures the Rx color convert of channel 2
+ */
+#define DMA2D_IN_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x74c)
+/** DMA2D_IN_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  output directly     2: YUV444 to YUV422    3: YUV444 to YUV420
+ */
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2    0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_M  (DMA2D_IN_COLOR_OUTPUT_SEL_CH2_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH2_S)
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_V  0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_S  0
+/** DMA2D_IN_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH2    (BIT(2))
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_M  (DMA2D_IN_COLOR_3B_PROC_EN_CH2_V << DMA2D_IN_COLOR_3B_PROC_EN_CH2_S)
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_V  0x00000001U
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_S  2
+/** DMA2D_IN_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+ *  1: YUV422      2: YUV444/420      7: disable color space convert
+ */
+#define DMA2D_IN_COLOR_INPUT_SEL_CH2    0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH2_M  (DMA2D_IN_COLOR_INPUT_SEL_CH2_V << DMA2D_IN_COLOR_INPUT_SEL_CH2_S)
+#define DMA2D_IN_COLOR_INPUT_SEL_CH2_V  0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH2_S  3
+
+/** DMA2D_IN_SCRAMBLE_CH2_REG register
+ *  Configures the rx scramble of channel 2
+ */
+#define DMA2D_IN_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x750)
+/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_M  (DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_S)
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_S  0
+/** DMA2D_IN_SCRAMBLE_SEL_POST_CH2 : R/W; bitpos: [5:3]; default: 0;
+ *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+ *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_M  (DMA2D_IN_SCRAMBLE_SEL_POST_CH2_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH2_S)
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_S  3
+
+/** DMA2D_IN_COLOR_PARAM0_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x754)
+/** DMA2D_IN_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H0_CH2    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH2_M  (DMA2D_IN_COLOR_PARAM_H0_CH2_V << DMA2D_IN_COLOR_PARAM_H0_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_H0_CH2_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH2_S  0
+
+/** DMA2D_IN_COLOR_PARAM1_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x758)
+/** DMA2D_IN_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H1_CH2    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH2_M  (DMA2D_IN_COLOR_PARAM_H1_CH2_V << DMA2D_IN_COLOR_PARAM_H1_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_H1_CH2_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH2_S  0
+
+/** DMA2D_IN_COLOR_PARAM2_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x75c)
+/** DMA2D_IN_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M0_CH2    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH2_M  (DMA2D_IN_COLOR_PARAM_M0_CH2_V << DMA2D_IN_COLOR_PARAM_M0_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_M0_CH2_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH2_S  0
+
+/** DMA2D_IN_COLOR_PARAM3_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x760)
+/** DMA2D_IN_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M1_CH2    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH2_M  (DMA2D_IN_COLOR_PARAM_M1_CH2_V << DMA2D_IN_COLOR_PARAM_M1_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_M1_CH2_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH2_S  0
+
+/** DMA2D_IN_COLOR_PARAM4_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x764)
+/** DMA2D_IN_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L0_CH2    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH2_M  (DMA2D_IN_COLOR_PARAM_L0_CH2_V << DMA2D_IN_COLOR_PARAM_L0_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_L0_CH2_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH2_S  0
+
+/** DMA2D_IN_COLOR_PARAM5_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x768)
+/** DMA2D_IN_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L1_CH2    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH2_M  (DMA2D_IN_COLOR_PARAM_L1_CH2_V << DMA2D_IN_COLOR_PARAM_L1_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_L1_CH2_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH2_S  0
+
+/** DMA2D_IN_ETM_CONF_CH2_REG register
+ *  Configures the rx etm of channel 2
+ */
+#define DMA2D_IN_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x76c)
+/** DMA2D_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH2    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH2_M  (DMA2D_IN_ETM_EN_CH2_V << DMA2D_IN_ETM_EN_CH2_S)
+#define DMA2D_IN_ETM_EN_CH2_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH2_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH2    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH2_M  (DMA2D_IN_ETM_LOOP_EN_CH2_V << DMA2D_IN_ETM_LOOP_EN_CH2_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH2_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH2_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH2    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH2_M  (DMA2D_IN_DSCR_TASK_MAK_CH2_V << DMA2D_IN_DSCR_TASK_MAK_CH2_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH2_S  2
+
+/** DMA2D_AXI_ERR_REG register
+ *  Represents the status of th axi bus
+ */
+#define DMA2D_AXI_ERR_REG (DR_REG_DMA2D_BASE + 0xa00)
+/** DMA2D_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0;
+ *  AXI read id err cnt
+ */
+#define DMA2D_RID_ERR_CNT    0x0000000FU
+#define DMA2D_RID_ERR_CNT_M  (DMA2D_RID_ERR_CNT_V << DMA2D_RID_ERR_CNT_S)
+#define DMA2D_RID_ERR_CNT_V  0x0000000FU
+#define DMA2D_RID_ERR_CNT_S  0
+/** DMA2D_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0;
+ *  AXI read resp err cnt
+ */
+#define DMA2D_RRESP_ERR_CNT    0x0000000FU
+#define DMA2D_RRESP_ERR_CNT_M  (DMA2D_RRESP_ERR_CNT_V << DMA2D_RRESP_ERR_CNT_S)
+#define DMA2D_RRESP_ERR_CNT_V  0x0000000FU
+#define DMA2D_RRESP_ERR_CNT_S  4
+/** DMA2D_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0;
+ *  AXI write resp err cnt
+ */
+#define DMA2D_WRESP_ERR_CNT    0x0000000FU
+#define DMA2D_WRESP_ERR_CNT_M  (DMA2D_WRESP_ERR_CNT_V << DMA2D_WRESP_ERR_CNT_S)
+#define DMA2D_WRESP_ERR_CNT_V  0x0000000FU
+#define DMA2D_WRESP_ERR_CNT_S  8
+/** DMA2D_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0;
+ *  AXI read cmd fifo remain cmd count
+ */
+#define DMA2D_RD_FIFO_CNT    0x00000007U
+#define DMA2D_RD_FIFO_CNT_M  (DMA2D_RD_FIFO_CNT_V << DMA2D_RD_FIFO_CNT_S)
+#define DMA2D_RD_FIFO_CNT_V  0x00000007U
+#define DMA2D_RD_FIFO_CNT_S  12
+/** DMA2D_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0;
+ *  AXI read backup cmd fifo remain cmd count
+ */
+#define DMA2D_RD_BAK_FIFO_CNT    0x0000000FU
+#define DMA2D_RD_BAK_FIFO_CNT_M  (DMA2D_RD_BAK_FIFO_CNT_V << DMA2D_RD_BAK_FIFO_CNT_S)
+#define DMA2D_RD_BAK_FIFO_CNT_V  0x0000000FU
+#define DMA2D_RD_BAK_FIFO_CNT_S  15
+/** DMA2D_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0;
+ *  AXI write cmd fifo remain cmd count
+ */
+#define DMA2D_WR_FIFO_CNT    0x00000007U
+#define DMA2D_WR_FIFO_CNT_M  (DMA2D_WR_FIFO_CNT_V << DMA2D_WR_FIFO_CNT_S)
+#define DMA2D_WR_FIFO_CNT_V  0x00000007U
+#define DMA2D_WR_FIFO_CNT_S  19
+/** DMA2D_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0;
+ *  AXI write backup cmd fifo remain cmd count
+ */
+#define DMA2D_WR_BAK_FIFO_CNT    0x0000000FU
+#define DMA2D_WR_BAK_FIFO_CNT_M  (DMA2D_WR_BAK_FIFO_CNT_V << DMA2D_WR_BAK_FIFO_CNT_S)
+#define DMA2D_WR_BAK_FIFO_CNT_V  0x0000000FU
+#define DMA2D_WR_BAK_FIFO_CNT_S  22
+
+/** DMA2D_RST_CONF_REG register
+ *  Configures the reset of axi
+ */
+#define DMA2D_RST_CONF_REG (DR_REG_DMA2D_BASE + 0xa04)
+/** DMA2D_AXIM_RD_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+ */
+#define DMA2D_AXIM_RD_RST    (BIT(0))
+#define DMA2D_AXIM_RD_RST_M  (DMA2D_AXIM_RD_RST_V << DMA2D_AXIM_RD_RST_S)
+#define DMA2D_AXIM_RD_RST_V  0x00000001U
+#define DMA2D_AXIM_RD_RST_S  0
+/** DMA2D_AXIM_WR_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+ */
+#define DMA2D_AXIM_WR_RST    (BIT(1))
+#define DMA2D_AXIM_WR_RST_M  (DMA2D_AXIM_WR_RST_V << DMA2D_AXIM_WR_RST_S)
+#define DMA2D_AXIM_WR_RST_V  0x00000001U
+#define DMA2D_AXIM_WR_RST_S  1
+/** DMA2D_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define DMA2D_CLK_EN    (BIT(2))
+#define DMA2D_CLK_EN_M  (DMA2D_CLK_EN_V << DMA2D_CLK_EN_S)
+#define DMA2D_CLK_EN_V  0x00000001U
+#define DMA2D_CLK_EN_S  2
+
+/** DMA2D_INTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define DMA2D_INTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa08)
+/** DMA2D_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_M  (DMA2D_ACCESS_INTR_MEM_START_ADDR_V << DMA2D_ACCESS_INTR_MEM_START_ADDR_S)
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** DMA2D_INTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space.
+ */
+#define DMA2D_INTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa0c)
+/** DMA2D_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_M  (DMA2D_ACCESS_INTR_MEM_END_ADDR_V << DMA2D_ACCESS_INTR_MEM_END_ADDR_S)
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** DMA2D_EXTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define DMA2D_EXTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa10)
+/** DMA2D_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_M  (DMA2D_ACCESS_EXTR_MEM_START_ADDR_V << DMA2D_ACCESS_EXTR_MEM_START_ADDR_S)
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_S  0
+
+/** DMA2D_EXTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space.
+ */
+#define DMA2D_EXTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa14)
+/** DMA2D_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_M  (DMA2D_ACCESS_EXTR_MEM_END_ADDR_V << DMA2D_ACCESS_EXTR_MEM_END_ADDR_S)
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_S  0
+
+/** DMA2D_OUT_ARB_CONFIG_REG register
+ *  Configures the tx arbiter
+ */
+#define DMA2D_OUT_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa18)
+/** DMA2D_OUT_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define DMA2D_OUT_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_M  (DMA2D_OUT_ARB_TIMEOUT_NUM_V << DMA2D_OUT_ARB_TIMEOUT_NUM_S)
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_S  0
+/** DMA2D_OUT_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_WEIGHT_EN    (BIT(16))
+#define DMA2D_OUT_WEIGHT_EN_M  (DMA2D_OUT_WEIGHT_EN_V << DMA2D_OUT_WEIGHT_EN_S)
+#define DMA2D_OUT_WEIGHT_EN_V  0x00000001U
+#define DMA2D_OUT_WEIGHT_EN_S  16
+
+/** DMA2D_IN_ARB_CONFIG_REG register
+ *  Configures the rx arbiter
+ */
+#define DMA2D_IN_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa1c)
+/** DMA2D_IN_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define DMA2D_IN_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define DMA2D_IN_ARB_TIMEOUT_NUM_M  (DMA2D_IN_ARB_TIMEOUT_NUM_V << DMA2D_IN_ARB_TIMEOUT_NUM_S)
+#define DMA2D_IN_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define DMA2D_IN_ARB_TIMEOUT_NUM_S  0
+/** DMA2D_IN_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_WEIGHT_EN    (BIT(16))
+#define DMA2D_IN_WEIGHT_EN_M  (DMA2D_IN_WEIGHT_EN_V << DMA2D_IN_WEIGHT_EN_S)
+#define DMA2D_IN_WEIGHT_EN_V  0x00000001U
+#define DMA2D_IN_WEIGHT_EN_S  16
+
+/** DMA2D_RDN_RESULT_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_RESULT_REG (DR_REG_DMA2D_BASE + 0xa20)
+/** DMA2D_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define DMA2D_RDN_ENA    (BIT(0))
+#define DMA2D_RDN_ENA_M  (DMA2D_RDN_ENA_V << DMA2D_RDN_ENA_S)
+#define DMA2D_RDN_ENA_V  0x00000001U
+#define DMA2D_RDN_ENA_S  0
+/** DMA2D_RDN_RESULT : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define DMA2D_RDN_RESULT    (BIT(1))
+#define DMA2D_RDN_RESULT_M  (DMA2D_RDN_RESULT_V << DMA2D_RDN_RESULT_S)
+#define DMA2D_RDN_RESULT_V  0x00000001U
+#define DMA2D_RDN_RESULT_S  1
+
+/** DMA2D_RDN_ECO_HIGH_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_ECO_HIGH_REG (DR_REG_DMA2D_BASE + 0xa24)
+/** DMA2D_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_RDN_ECO_HIGH    0xFFFFFFFFU
+#define DMA2D_RDN_ECO_HIGH_M  (DMA2D_RDN_ECO_HIGH_V << DMA2D_RDN_ECO_HIGH_S)
+#define DMA2D_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define DMA2D_RDN_ECO_HIGH_S  0
+
+/** DMA2D_RDN_ECO_LOW_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_ECO_LOW_REG (DR_REG_DMA2D_BASE + 0xa28)
+/** DMA2D_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_RDN_ECO_LOW    0xFFFFFFFFU
+#define DMA2D_RDN_ECO_LOW_M  (DMA2D_RDN_ECO_LOW_V << DMA2D_RDN_ECO_LOW_S)
+#define DMA2D_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define DMA2D_RDN_ECO_LOW_S  0
+
+/** DMA2D_DATE_REG register
+ *  register version.
+ */
+#define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c)
+/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 37822864;
+ *  register version.
+ */
+#define DMA2D_DATE    0xFFFFFFFFU
+#define DMA2D_DATE_M  (DMA2D_DATE_V << DMA2D_DATE_S)
+#define DMA2D_DATE_V  0xFFFFFFFFU
+#define DMA2D_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h
new file mode 100644
index 0000000000..d637f6ecab
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h
@@ -0,0 +1,2085 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of out_conf0_chn register
+ *  Configures the tx direction of channel n
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_chn : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_chn:1;
+        /** out_eof_mode_chn : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_chn:1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_chn:1;
+        /** out_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_chn:1;
+        /** out_check_owner_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn:1;
+        /** out_loop_test_chn : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_chn:1;
+        /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_chn:3;
+        /** out_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0;
+         *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+         *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+         *  descriptor
+         */
+        uint32_t out_macro_block_size_chn:2;
+        /** out_dscr_port_en_chn : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to 1 to obtain descriptor from IP port
+         */
+        uint32_t out_dscr_port_en_chn:1;
+        /** out_page_bound_en_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_chn:1;
+        uint32_t reserved_13:3;
+        /** out_reorder_en_chn : R/W; bitpos: [16]; default: 0;
+         *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t out_reorder_en_chn:1;
+        uint32_t reserved_17:7;
+        /** out_rst_chn : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_chn:1;
+        /** out_cmd_disable_chn : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_chn:1;
+        /** out_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} dma2d_out_conf0_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Configures the tx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_chn:10;
+        /** outfifo_push_chn : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_chn:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dma2d_out_push_chn_reg_t;
+
+/** Type of out_link_conf_chn register
+ *  Configures the tx descriptor operations of channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_chn : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn:1;
+        /** outlink_start_chn : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn:1;
+        /** outlink_restart_chn : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn:1;
+        /** outlink_park_chn : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dma2d_out_link_conf_chn_reg_t;
+
+/** Type of out_link_addr_chn register
+ *  Configures the tx descriptor address of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_link_addr_chn_reg_t;
+
+/** Type of out_arb_chn register
+ *  Configures the tx arbiter of channel n
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_chn:4;
+        /** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t out_arb_priority_chn:2;
+        /** out_arb_priority_h_chn : R/W; bitpos: [7:6]; default: 0;
+         *  Set the priority of channel
+         */
+        uint32_t out_arb_priority_h_chn:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dma2d_out_arb_chn_reg_t;
+
+/** Type of out_ro_pd_conf_chn register
+ *  Configures the tx reorder memory of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** out_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0;
+         *  dma reorder ram power down
+         */
+        uint32_t out_ro_ram_force_pd_chn:1;
+        /** out_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1;
+         *  dma reorder ram power up
+         */
+        uint32_t out_ro_ram_force_pu_chn:1;
+        /** out_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t out_ro_ram_clk_fo_chn:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dma2d_out_ro_pd_conf_chn_reg_t;
+
+/** Type of out_color_convert_chn register
+ *  Configures the tx color convert of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+         *  YUV444 to YUV422     2: output directly
+         */
+        uint32_t out_color_output_sel_chn:2;
+        /** out_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Enable generic color convert module between color input & color output, need to
+         *  configure parameter.
+         */
+        uint32_t out_color_3b_proc_en_chn:1;
+        /** out_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7;
+         *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+         *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+         *  disable color space convert
+         */
+        uint32_t out_color_input_sel_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_out_color_convert_chn_reg_t;
+
+/** Type of out_scramble_chn register
+ *  Configures the tx scramble of channel n
+ */
+typedef union {
+    struct {
+        /** out_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0;
+         *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+         *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t out_scramble_sel_pre_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_out_scramble_chn_reg_t;
+
+/** Type of out_color_param0_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298;
+         *  Set first 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_h0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_out_color_param0_chn_reg_t;
+
+/** Type of out_color_param1_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121;
+         *  Set last 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_h1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_color_param1_chn_reg_t;
+
+/** Type of out_color_param2_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050;
+         *  Set first 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_m0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_out_color_param2_chn_reg_t;
+
+/** Type of out_color_param3_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784;
+         *  Set last 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_m1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_color_param3_chn_reg_t;
+
+/** Type of out_color_param4_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682;
+         *  Set first 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_l0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_out_color_param4_chn_reg_t;
+
+/** Type of out_color_param5_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392;
+         *  Set last 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_l1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_color_param5_chn_reg_t;
+
+/** Type of out_etm_conf_chn register
+ *  Configures the tx etm of channel n
+ */
+typedef union {
+    struct {
+        /** out_etm_en_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the enable of the etm function, 1 is enable.
+         */
+        uint32_t out_etm_en_chn:1;
+        /** out_etm_loop_en_chn : R/W; bitpos: [1]; default: 0;
+         *  Configures the enable of the descriptors loop etm function, 1 is enable.
+         */
+        uint32_t out_etm_loop_en_chn:1;
+        /** out_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1;
+         *  Configures the maximum number of cacheable descriptors.
+         */
+        uint32_t out_dscr_task_mak_chn:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dma2d_out_etm_conf_chn_reg_t;
+
+/** Type of out_dscr_port_blk_chn register
+ *  Configures the tx block size in dscr port mode
+ */
+typedef union {
+    struct {
+        /** out_dscr_port_blk_h_chn : R/W; bitpos: [13:0]; default: 18;
+         *  Set the vertical height of tx block size in dscr port mode
+         */
+        uint32_t out_dscr_port_blk_h_chn:14;
+        /** out_dscr_port_blk_v_chn : R/W; bitpos: [27:14]; default: 18;
+         *  Set the horizontal width of tx block size in dscr port mode
+         */
+        uint32_t out_dscr_port_blk_v_chn:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_dscr_port_blk_chn_reg_t;
+
+/** Type of in_conf0_chn register
+ *  Configures the rx direction of channel n
+ */
+typedef union {
+    struct {
+        /** in_mem_trans_en_chn : R/W; bitpos: [0]; default: 0;
+         *  enable memory trans of the same channel
+         */
+        uint32_t in_mem_trans_en_chn:1;
+        uint32_t reserved_1:1;
+        /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_chn:1;
+        /** in_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_chn:1;
+        /** in_check_owner_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn:1;
+        /** in_loop_test_chn : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn:1;
+        /** in_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_chn:3;
+        /** in_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0;
+         *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+         *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+         *  descriptor
+         */
+        uint32_t in_macro_block_size_chn:2;
+        /** in_dscr_port_en_chn : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to 1 to obtain descriptor from IP port
+         */
+        uint32_t in_dscr_port_en_chn:1;
+        /** in_page_bound_en_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_chn:1;
+        uint32_t reserved_13:3;
+        /** in_reorder_en_chn : R/W; bitpos: [16]; default: 0;
+         *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t in_reorder_en_chn:1;
+        uint32_t reserved_17:7;
+        /** in_rst_chn : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_chn:1;
+        /** in_cmd_disable_chn : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_chn:1;
+        /** in_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} dma2d_in_conf0_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Configures the rx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_chn:11;
+        /** infifo_pop_chn : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_chn:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dma2d_in_pop_chn_reg_t;
+
+/** Type of in_link_conf_chn register
+ *  Configures the rx descriptor operations of channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_chn:1;
+        /** inlink_stop_chn : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn:1;
+        /** inlink_start_chn : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn:1;
+        /** inlink_restart_chn : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn:1;
+        /** inlink_park_chn : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dma2d_in_link_conf_chn_reg_t;
+
+/** Type of in_link_addr_chn register
+ *  Configures the rx descriptor address of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_link_addr_chn_reg_t;
+
+/** Type of in_arb_chn register
+ *  Configures the rx arbiter of channel n
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_chn:4;
+        /** in_arb_priority_chn : R/W; bitpos: [4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t in_arb_priority_chn:1;
+        /** in_arb_priority_h_chn : R/W; bitpos: [7:5]; default: 0;
+         *  Set the priority of channel
+         */
+        uint32_t in_arb_priority_h_chn:3;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dma2d_in_arb_chn_reg_t;
+
+/** Type of in_ro_pd_conf_chn register
+ *  Configures the rx reorder memory of channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** in_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0;
+         *  dma reorder ram power down
+         */
+        uint32_t in_ro_ram_force_pd_chn:1;
+        /** in_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1;
+         *  dma reorder ram power up
+         */
+        uint32_t in_ro_ram_force_pu_chn:1;
+        /** in_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t in_ro_ram_clk_fo_chn:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dma2d_in_ro_pd_conf_chn_reg_t;
+
+/** Type of in_color_convert_chn register
+ *  Configures the Rx color convert of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+         *  output directly     2: YUV444 to YUV422    3: YUV444 to YUV420
+         */
+        uint32_t in_color_output_sel_chn:2;
+        /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Enable generic color convert module between color input & color output, need to
+         *  configure parameter.
+         */
+        uint32_t in_color_3b_proc_en_chn:1;
+        /** in_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7;
+         *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+         *  1: YUV422      2: YUV444/420      7: disable color space convert
+         */
+        uint32_t in_color_input_sel_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_in_color_convert_chn_reg_t;
+
+/** Type of in_scramble_chn register
+ *  Configures the rx scramble of channel n
+ */
+typedef union {
+    struct {
+        /** in_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0;
+         *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+         *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t in_scramble_sel_pre_chn:3;
+        /** in_scramble_sel_post_chn : R/W; bitpos: [5:3]; default: 0;
+         *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+         *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t in_scramble_sel_post_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_in_scramble_chn_reg_t;
+
+/** Type of in_color_param0_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298;
+         *  Set first 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_h0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_in_color_param0_chn_reg_t;
+
+/** Type of in_color_param1_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121;
+         *  Set last 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_h1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_in_color_param1_chn_reg_t;
+
+/** Type of in_color_param2_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050;
+         *  Set first 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_m0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_in_color_param2_chn_reg_t;
+
+/** Type of in_color_param3_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784;
+         *  Set last 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_m1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_in_color_param3_chn_reg_t;
+
+/** Type of in_color_param4_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682;
+         *  Set first 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_l0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_in_color_param4_chn_reg_t;
+
+/** Type of in_color_param5_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392;
+         *  Set last 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_l1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_in_color_param5_chn_reg_t;
+
+/** Type of in_etm_conf_chn register
+ *  Configures the rx etm of channel n
+ */
+typedef union {
+    struct {
+        /** in_etm_en_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the enable of the etm function, 1 is enable.
+         */
+        uint32_t in_etm_en_chn:1;
+        /** in_etm_loop_en_chn : R/W; bitpos: [1]; default: 0;
+         *  Configures the enable of the descriptors loop etm function, 1 is enable.
+         */
+        uint32_t in_etm_loop_en_chn:1;
+        /** in_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1;
+         *  Configures the maximum number of cacheable descriptors.
+         */
+        uint32_t in_dscr_task_mak_chn:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dma2d_in_etm_conf_chn_reg_t;
+
+/** Type of rst_conf register
+ *  Configures the reset of axi
+ */
+typedef union {
+    struct {
+        /** axim_rd_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+         */
+        uint32_t axim_rd_rst:1;
+        /** axim_wr_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+         */
+        uint32_t axim_wr_rst:1;
+        /** clk_en : R/W; bitpos: [2]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_rst_conf_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr:32;
+    };
+    uint32_t val;
+} dma2d_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr:32;
+    };
+    uint32_t val;
+} dma2d_intr_mem_end_addr_reg_t;
+
+/** Type of extr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_extr_mem_start_addr:32;
+    };
+    uint32_t val;
+} dma2d_extr_mem_start_addr_reg_t;
+
+/** Type of extr_mem_end_addr register
+ *  The end address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_extr_mem_end_addr:32;
+    };
+    uint32_t val;
+} dma2d_extr_mem_end_addr_reg_t;
+
+/** Type of out_arb_config register
+ *  Configures the tx arbiter
+ */
+typedef union {
+    struct {
+        /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t out_arb_timeout_num:16;
+        /** out_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t out_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_out_arb_config_reg_t;
+
+/** Type of in_arb_config register
+ *  Configures the rx arbiter
+ */
+typedef union {
+    struct {
+        /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t in_arb_timeout_num:16;
+        /** in_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t in_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_in_arb_config_reg_t;
+
+/** Type of rdn_result register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dma2d_rdn_result_reg_t;
+
+/** Type of rdn_eco_high register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} dma2d_rdn_eco_high_reg_t;
+
+/** Type of rdn_eco_low register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} dma2d_rdn_eco_low_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of out_int_raw_chn register
+ *  Raw interrupt status of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_chn_int_raw:1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_chn_int_raw:1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_chn_int_raw:1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_chn_int_raw:1;
+        /** outfifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_raw:1;
+        /** outfifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_chn_int_raw:1;
+        /** outfifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_raw:1;
+        /** outfifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_chn_int_raw:1;
+        /** outfifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_raw:1;
+        /** outfifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l3_chn_int_raw:1;
+        /** outfifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_raw:1;
+        /** outfifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+         */
+        uint32_t outfifo_ro_udf_chn_int_raw:1;
+        /** out_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_raw_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena:1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena:1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena:1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena:1;
+        /** outfifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_ena:1;
+        /** outfifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_ena:1;
+        /** outfifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_ena:1;
+        /** outfifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_ena:1;
+        /** outfifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_ena:1;
+        /** outfifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_ena:1;
+        /** outfifo_ro_ovf_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_ena:1;
+        /** outfifo_ro_udf_chn_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_ena:1;
+        /** out_dscr_task_ovf_chn_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_ena_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt status of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st:1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st:1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st:1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st:1;
+        /** outfifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_st:1;
+        /** outfifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_st:1;
+        /** outfifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_st:1;
+        /** outfifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_st:1;
+        /** outfifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_st:1;
+        /** outfifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_st:1;
+        /** outfifo_ro_ovf_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_st:1;
+        /** outfifo_ro_udf_chn_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_st:1;
+        /** out_dscr_task_ovf_chn_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_st_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr:1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr:1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr:1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr:1;
+        /** outfifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_clr:1;
+        /** outfifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_clr:1;
+        /** outfifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_clr:1;
+        /** outfifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_clr:1;
+        /** outfifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_clr:1;
+        /** outfifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_clr:1;
+        /** outfifo_ro_ovf_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_clr:1;
+        /** outfifo_ro_udf_chn_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_clr:1;
+        /** out_dscr_task_ovf_chn_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_clr_chn_reg_t;
+
+/** Type of in_int_raw_chn register
+ *  Raw interrupt status of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw:1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw:1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_chn_int_raw:1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw:1;
+        /** infifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_chn_int_raw:1;
+        /** infifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_chn_int_raw:1;
+        /** infifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_chn_int_raw:1;
+        /** infifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_chn_int_raw:1;
+        /** infifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l3_chn_int_raw:1;
+        /** infifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l3_chn_int_raw:1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_chn_int_raw:1;
+        /** infifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+         */
+        uint32_t infifo_ro_ovf_chn_int_raw:1;
+        /** infifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+         */
+        uint32_t infifo_ro_udf_chn_int_raw:1;
+        /** in_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_raw_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena:1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena:1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena:1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena:1;
+        /** infifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_ena:1;
+        /** infifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_ena:1;
+        /** infifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_ena:1;
+        /** infifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_ena:1;
+        /** infifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_ena:1;
+        /** infifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_ena:1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena:1;
+        /** infifo_ro_ovf_chn_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_ena:1;
+        /** infifo_ro_udf_chn_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_ena:1;
+        /** in_dscr_task_ovf_chn_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_ena_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt status of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st:1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st:1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st:1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st:1;
+        /** infifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_st:1;
+        /** infifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_st:1;
+        /** infifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_st:1;
+        /** infifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_st:1;
+        /** infifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_st:1;
+        /** infifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_st:1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st:1;
+        /** infifo_ro_ovf_chn_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_st:1;
+        /** infifo_ro_udf_chn_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_st:1;
+        /** in_dscr_task_ovf_chn_int_st : RO; bitpos: [13]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_st_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr:1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr:1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr:1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr:1;
+        /** infifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_clr:1;
+        /** infifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_clr:1;
+        /** infifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_clr:1;
+        /** infifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_clr:1;
+        /** infifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_clr:1;
+        /** infifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_clr:1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr:1;
+        /** infifo_ro_ovf_chn_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_clr:1;
+        /** infifo_ro_udf_chn_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_clr:1;
+        /** in_dscr_task_ovf_chn_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_clr_chn_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of outfifo_status_chn register
+ *  Represents the status of the tx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l2_chn:1;
+        /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l2_chn:1;
+        /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l2_chn:4;
+        uint32_t reserved_6:1;
+        /** out_remain_under_1b_chn : RO; bitpos: [7]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn:1;
+        /** out_remain_under_2b_chn : RO; bitpos: [8]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn:1;
+        /** out_remain_under_3b_chn : RO; bitpos: [9]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn:1;
+        /** out_remain_under_4b_chn : RO; bitpos: [10]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn:1;
+        /** out_remain_under_5b_chn : RO; bitpos: [11]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_5b_chn:1;
+        /** out_remain_under_6b_chn : RO; bitpos: [12]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_6b_chn:1;
+        /** out_remain_under_7b_chn : RO; bitpos: [13]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_7b_chn:1;
+        /** out_remain_under_8b_chn : RO; bitpos: [14]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_8b_chn:1;
+        /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l1_chn:1;
+        /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l1_chn:1;
+        /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l1_chn:5;
+        /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l3_chn:1;
+        /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l3_chn:1;
+        /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l3_chn:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dma2d_outfifo_status_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Represents the working status of the tx descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn:18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_chn:2;
+        /** out_state_chn : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_chn:4;
+        /** out_reset_avail_chn : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dma2d_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_bf1_chn_reg_t;
+
+/** Type of out_ro_status_chn register
+ *  Represents the status of the tx reorder module of channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_ro_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in color convert Tx FIFO for
+         *  channel 0.
+         */
+        uint32_t outfifo_ro_cnt_chn:6;
+        /** out_ro_wr_state_chn : RO; bitpos: [7:6]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t out_ro_wr_state_chn:2;
+        /** out_ro_rd_state_chn : RO; bitpos: [9:8]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t out_ro_rd_state_chn:2;
+        /** out_pixel_byte_chn : RO; bitpos: [13:10]; default: 0;
+         *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t out_pixel_byte_chn:4;
+        /** out_burst_block_num_chn : RO; bitpos: [17:14]; default: 0;
+         *  the number of macro blocks contained in a burst of data at TX channel
+         */
+        uint32_t out_burst_block_num_chn:4;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dma2d_out_ro_status_chn_reg_t;
+
+/** Type of infifo_status_chn register
+ *  Represents the status of the rx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_chn:1;
+        /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_chn:1;
+        /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_chn:4;
+        uint32_t reserved_6:1;
+        /** in_remain_under_1b_chn : RO; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn:1;
+        /** in_remain_under_2b_chn : RO; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn:1;
+        /** in_remain_under_3b_chn : RO; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn:1;
+        /** in_remain_under_4b_chn : RO; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn:1;
+        /** in_remain_under_5b_chn : RO; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_5b_chn:1;
+        /** in_remain_under_6b_chn : RO; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_6b_chn:1;
+        /** in_remain_under_7b_chn : RO; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_7b_chn:1;
+        /** in_remain_under_8b_chn : RO; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_8b_chn:1;
+        /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0;
+         *  Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_full_l1_chn:1;
+        /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
+         *  Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_empty_l1_chn:1;
+        /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_cnt_l1_chn:5;
+        /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0;
+         *  Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_full_l3_chn:1;
+        /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
+         *  Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_empty_l3_chn:1;
+        /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_cnt_l3_chn:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dma2d_infifo_status_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Represents the working status of the rx descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn:18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn:2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn:3;
+        /** in_reset_avail_chn : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_chn:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dma2d_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_bf1_chn_reg_t;
+
+/** Type of in_ro_status_chn register
+ *  Represents the status of the rx reorder module of channel n
+ */
+typedef union {
+    struct {
+        /** infifo_ro_cnt_chn : RO; bitpos: [4:0]; default: 0;
+         *  The register stores the byte number of the data in color convert Rx FIFO for
+         *  channel 0.
+         */
+        uint32_t infifo_ro_cnt_chn:5;
+        /** in_ro_wr_state_chn : RO; bitpos: [6:5]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t in_ro_wr_state_chn:2;
+        /** in_ro_rd_state_chn : RO; bitpos: [8:7]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t in_ro_rd_state_chn:2;
+        /** in_pixel_byte_chn : RO; bitpos: [12:9]; default: 0;
+         *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t in_pixel_byte_chn:4;
+        /** in_burst_block_num_chn : RO; bitpos: [16:13]; default: 0;
+         *  the number of macro blocks contained in a burst of data at RX channel
+         */
+        uint32_t in_burst_block_num_chn:4;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_in_ro_status_chn_reg_t;
+
+/** Type of axi_err register
+ *  Represents the status of th axi bus
+ */
+typedef union {
+    struct {
+        /** rid_err_cnt : RO; bitpos: [3:0]; default: 0;
+         *  AXI read id err cnt
+         */
+        uint32_t rid_err_cnt:4;
+        /** rresp_err_cnt : RO; bitpos: [7:4]; default: 0;
+         *  AXI read resp err cnt
+         */
+        uint32_t rresp_err_cnt:4;
+        /** wresp_err_cnt : RO; bitpos: [11:8]; default: 0;
+         *  AXI write resp err cnt
+         */
+        uint32_t wresp_err_cnt:4;
+        /** rd_fifo_cnt : RO; bitpos: [14:12]; default: 0;
+         *  AXI read cmd fifo remain cmd count
+         */
+        uint32_t rd_fifo_cnt:3;
+        /** rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0;
+         *  AXI read backup cmd fifo remain cmd count
+         */
+        uint32_t rd_bak_fifo_cnt:4;
+        /** wr_fifo_cnt : RO; bitpos: [21:19]; default: 0;
+         *  AXI write cmd fifo remain cmd count
+         */
+        uint32_t wr_fifo_cnt:3;
+        /** wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0;
+         *  AXI write backup cmd fifo remain cmd count
+         */
+        uint32_t wr_bak_fifo_cnt:4;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} dma2d_axi_err_reg_t;
+
+/** Type of date register
+ *  register version.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 37822864;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} dma2d_date_reg_t;
+
+
+/** Group: Peripheral Select Registers */
+/** Type of out_peri_sel_chn register
+ *  Configures the tx peripheral of channel n
+ */
+typedef union {
+    struct {
+        /** out_peri_sel_chn : R/W; bitpos: [2:0]; default: 7;
+         *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+         *  display-1     2: display-2     3: display-3      7: no choose
+         */
+        uint32_t out_peri_sel_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_out_peri_sel_chn_reg_t;
+
+/** Type of in_peri_sel_chn register
+ *  Configures the rx peripheral of channel n
+ */
+typedef union {
+    struct {
+        /** in_peri_sel_chn : R/W; bitpos: [2:0]; default: 7;
+         *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+         *  display-1     2: display-2        7: no choose
+         */
+        uint32_t in_peri_sel_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_in_peri_sel_chn_reg_t;
+
+
+typedef struct {
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch0;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch0;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch0;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch0;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch0;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch0;
+    volatile dma2d_out_push_chn_reg_t out_push_ch0;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch0;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch0;
+    volatile dma2d_out_state_chn_reg_t out_state_ch0;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch0;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch0;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch0;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch0;
+    volatile dma2d_out_ro_pd_conf_chn_reg_t out_ro_pd_conf_ch0;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch0;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch0;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch0;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch0;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch0;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch0;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch0;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch0;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch0;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch0;
+    uint32_t reserved_070[36];
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch1;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch1;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch1;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch1;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch1;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch1;
+    volatile dma2d_out_push_chn_reg_t out_push_ch1;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch1;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch1;
+    volatile dma2d_out_state_chn_reg_t out_state_ch1;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch1;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch1;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch1;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch1;
+    uint32_t reserved_144;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch1;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch1;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch1;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch1;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch1;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch1;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch1;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch1;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch1;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch1;
+    uint32_t reserved_170[36];
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch2;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch2;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch2;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch2;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch2;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch2;
+    volatile dma2d_out_push_chn_reg_t out_push_ch2;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch2;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch2;
+    volatile dma2d_out_state_chn_reg_t out_state_ch2;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch2;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch2;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch2;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch2;
+    uint32_t reserved_244;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch2;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch2;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch2;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch2;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch2;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch2;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch2;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch2;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch2;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch2;
+    uint32_t reserved_270[36];
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch3;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch3;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch3;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch3;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch3;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch3;
+    volatile dma2d_out_push_chn_reg_t out_push_ch3;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch3;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch3;
+    volatile dma2d_out_state_chn_reg_t out_state_ch3;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch3;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch3;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch3;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch3;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch3;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch3;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch3;
+    uint32_t reserved_344;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch3;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch3;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch3;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch3;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch3;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch3;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch3;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch3;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch3;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch3;
+    uint32_t reserved_370[100];
+    volatile dma2d_in_conf0_chn_reg_t in_conf0_ch0;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch0;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch0;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st_ch0;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch0;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status_ch0;
+    volatile dma2d_in_pop_chn_reg_t in_pop_ch0;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch0;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch0;
+    volatile dma2d_in_state_chn_reg_t in_state_ch0;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr_ch0;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch0;
+    volatile dma2d_in_arb_chn_reg_t in_arb_ch0;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch0;
+    volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch0;
+    volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch0;
+    volatile dma2d_in_scramble_chn_reg_t in_scramble_ch0;
+    volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch0;
+    volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch0;
+    volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch0;
+    volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch0;
+    volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch0;
+    volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch0;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch0;
+    uint32_t reserved_570[36];
+    volatile dma2d_in_conf0_chn_reg_t in_conf0_ch1;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch1;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch1;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st_ch1;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch1;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status_ch1;
+    volatile dma2d_in_pop_chn_reg_t in_pop_ch1;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch1;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch1;
+    volatile dma2d_in_state_chn_reg_t in_state_ch1;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr_ch1;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch1;
+    volatile dma2d_in_arb_chn_reg_t in_arb_ch1;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch1;
+    volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch1;
+    volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch1;
+    volatile dma2d_in_scramble_chn_reg_t in_scramble_ch1;
+    volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch1;
+    volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch1;
+    volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch1;
+    volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch1;
+    volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch1;
+    volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch1;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch1;
+    uint32_t reserved_670[36];
+    volatile dma2d_in_conf0_chn_reg_t in_conf0_ch2;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch2;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch2;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st_ch2;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch2;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status_ch2;
+    volatile dma2d_in_pop_chn_reg_t in_pop_ch2;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch2;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch2;
+    volatile dma2d_in_state_chn_reg_t in_state_ch2;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr_ch2;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch2;
+    volatile dma2d_in_arb_chn_reg_t in_arb_ch2;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch2;
+    volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch2;
+    volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch2;
+    volatile dma2d_in_scramble_chn_reg_t in_scramble_ch2;
+    volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch2;
+    volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch2;
+    volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch2;
+    volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch2;
+    volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch2;
+    volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch2;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch2;
+    uint32_t reserved_770[164];
+    volatile dma2d_axi_err_reg_t axi_err;
+    volatile dma2d_rst_conf_reg_t rst_conf;
+    volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile dma2d_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile dma2d_extr_mem_start_addr_reg_t extr_mem_start_addr;
+    volatile dma2d_extr_mem_end_addr_reg_t extr_mem_end_addr;
+    volatile dma2d_out_arb_config_reg_t out_arb_config;
+    volatile dma2d_in_arb_config_reg_t in_arb_config;
+    volatile dma2d_rdn_result_reg_t rdn_result;
+    volatile dma2d_rdn_eco_high_reg_t rdn_eco_high;
+    volatile dma2d_rdn_eco_low_reg_t rdn_eco_low;
+    volatile dma2d_date_reg_t date;
+} dma2d_dev_t;
+
+extern dma2d_dev_t DMA2D;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dma2d_dev_t) == 0xa30, "Invalid size of dma2d_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h
new file mode 100644
index 0000000000..b16c0654e9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h
@@ -0,0 +1,5270 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13427
+
+/** DMA2D_OUT_CONF0_CH0_REG register
+ *  Configures the tx direction of channel 0
+ */
+#define DMA2D_OUT_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x0)
+/** DMA2D_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH0    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH0_M  (DMA2D_OUT_AUTO_WRBACK_CH0_V << DMA2D_OUT_AUTO_WRBACK_CH0_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH0_S  0
+/** DMA2D_OUT_EOF_MODE_CH0 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH0    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH0_M  (DMA2D_OUT_EOF_MODE_CH0_V << DMA2D_OUT_EOF_MODE_CH0_S)
+#define DMA2D_OUT_EOF_MODE_CH0_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH0_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH0    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH0_M  (DMA2D_OUTDSCR_BURST_EN_CH0_V << DMA2D_OUTDSCR_BURST_EN_CH0_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH0_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH0    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH0_M  (DMA2D_OUT_ECC_AES_EN_CH0_V << DMA2D_OUT_ECC_AES_EN_CH0_S)
+#define DMA2D_OUT_ECC_AES_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH0_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH0    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH0_M  (DMA2D_OUT_CHECK_OWNER_CH0_V << DMA2D_OUT_CHECK_OWNER_CH0_S)
+#define DMA2D_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH0_S  4
+/** DMA2D_OUT_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH0    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH0_M  (DMA2D_OUT_LOOP_TEST_CH0_V << DMA2D_OUT_LOOP_TEST_CH0_S)
+#define DMA2D_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH0_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH0_V << DMA2D_OUT_MEM_BURST_LENGTH_CH0_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH0    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_M  (DMA2D_OUT_DSCR_PORT_EN_CH0_V << DMA2D_OUT_DSCR_PORT_EN_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_M  (DMA2D_OUT_PAGE_BOUND_EN_CH0_V << DMA2D_OUT_PAGE_BOUND_EN_CH0_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_S  12
+/** DMA2D_OUT_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH0    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH0_M  (DMA2D_OUT_REORDER_EN_CH0_V << DMA2D_OUT_REORDER_EN_CH0_S)
+#define DMA2D_OUT_REORDER_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH0_S  16
+/** DMA2D_OUT_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH0    (BIT(24))
+#define DMA2D_OUT_RST_CH0_M  (DMA2D_OUT_RST_CH0_V << DMA2D_OUT_RST_CH0_S)
+#define DMA2D_OUT_RST_CH0_V  0x00000001U
+#define DMA2D_OUT_RST_CH0_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH0    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH0_M  (DMA2D_OUT_CMD_DISABLE_CH0_V << DMA2D_OUT_CMD_DISABLE_CH0_S)
+#define DMA2D_OUT_CMD_DISABLE_CH0_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH0_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** DMA2D_OUT_INT_RAW_CH0_REG register
+ *  Raw interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x4)
+/** DMA2D_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_RAW_M  (DMA2D_OUT_DONE_CH0_INT_RAW_V << DMA2D_OUT_DONE_CH0_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_RAW_M  (DMA2D_OUT_EOF_CH0_INT_RAW_V << DMA2D_OUT_EOF_CH0_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x8)
+/** DMA2D_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_ENA_M  (DMA2D_OUT_DONE_CH0_INT_ENA_V << DMA2D_OUT_DONE_CH0_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_ENA_M  (DMA2D_OUT_EOF_CH0_INT_ENA_V << DMA2D_OUT_EOF_CH0_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0xc)
+/** DMA2D_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_ST_M  (DMA2D_OUT_DONE_CH0_INT_ST_V << DMA2D_OUT_DONE_CH0_INT_ST_S)
+#define DMA2D_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_ST_M  (DMA2D_OUT_EOF_CH0_INT_ST_V << DMA2D_OUT_EOF_CH0_INT_ST_S)
+#define DMA2D_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x10)
+/** DMA2D_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_CLR_M  (DMA2D_OUT_DONE_CH0_INT_CLR_V << DMA2D_OUT_DONE_CH0_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_CLR_M  (DMA2D_OUT_EOF_CH0_INT_CLR_V << DMA2D_OUT_EOF_CH0_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH0_REG register
+ *  Represents the status of the tx fifo of channel 0
+ */
+#define DMA2D_OUTFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x14)
+/** DMA2D_OUTFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH0    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH0_M  (DMA2D_OUTFIFO_FULL_L2_CH0_V << DMA2D_OUTFIFO_FULL_L2_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH0_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_M  (DMA2D_OUTFIFO_EMPTY_L2_CH0_V << DMA2D_OUTFIFO_EMPTY_L2_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH0    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH0_M  (DMA2D_OUTFIFO_CNT_L2_CH0_V << DMA2D_OUTFIFO_CNT_L2_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH0_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH0_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH0_V << DMA2D_OUT_REMAIN_UNDER_1B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH0_V << DMA2D_OUT_REMAIN_UNDER_2B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH0_V << DMA2D_OUT_REMAIN_UNDER_3B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH0_V << DMA2D_OUT_REMAIN_UNDER_4B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH0_V << DMA2D_OUT_REMAIN_UNDER_5B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH0_V << DMA2D_OUT_REMAIN_UNDER_6B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH0_V << DMA2D_OUT_REMAIN_UNDER_7B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH0_V << DMA2D_OUT_REMAIN_UNDER_8B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH0    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH0_M  (DMA2D_OUTFIFO_FULL_L1_CH0_V << DMA2D_OUTFIFO_FULL_L1_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH0_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_M  (DMA2D_OUTFIFO_EMPTY_L1_CH0_V << DMA2D_OUTFIFO_EMPTY_L1_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH0    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH0_M  (DMA2D_OUTFIFO_CNT_L1_CH0_V << DMA2D_OUTFIFO_CNT_L1_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH0_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH0_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH0    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH0_M  (DMA2D_OUTFIFO_FULL_L3_CH0_V << DMA2D_OUTFIFO_FULL_L3_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH0_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_M  (DMA2D_OUTFIFO_EMPTY_L3_CH0_V << DMA2D_OUTFIFO_EMPTY_L3_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH0    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH0_M  (DMA2D_OUTFIFO_CNT_L3_CH0_V << DMA2D_OUTFIFO_CNT_L3_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH0_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH0_S  24
+
+/** DMA2D_OUT_PUSH_CH0_REG register
+ *  Configures the tx fifo of channel 0
+ */
+#define DMA2D_OUT_PUSH_CH0_REG (DR_REG_DMA2D_BASE + 0x18)
+/** DMA2D_OUTFIFO_WDATA_CH0 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH0    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH0_M  (DMA2D_OUTFIFO_WDATA_CH0_V << DMA2D_OUTFIFO_WDATA_CH0_S)
+#define DMA2D_OUTFIFO_WDATA_CH0_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH0_S  0
+/** DMA2D_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH0    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH0_M  (DMA2D_OUTFIFO_PUSH_CH0_V << DMA2D_OUTFIFO_PUSH_CH0_S)
+#define DMA2D_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH0_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH0_REG register
+ *  Configures the tx descriptor operations of channel 0
+ */
+#define DMA2D_OUT_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x1c)
+/** DMA2D_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH0    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH0_M  (DMA2D_OUTLINK_STOP_CH0_V << DMA2D_OUTLINK_STOP_CH0_S)
+#define DMA2D_OUTLINK_STOP_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH0_S  20
+/** DMA2D_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH0    (BIT(21))
+#define DMA2D_OUTLINK_START_CH0_M  (DMA2D_OUTLINK_START_CH0_V << DMA2D_OUTLINK_START_CH0_S)
+#define DMA2D_OUTLINK_START_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH0_S  21
+/** DMA2D_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH0    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH0_M  (DMA2D_OUTLINK_RESTART_CH0_V << DMA2D_OUTLINK_RESTART_CH0_S)
+#define DMA2D_OUTLINK_RESTART_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH0_S  22
+/** DMA2D_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH0    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH0_M  (DMA2D_OUTLINK_PARK_CH0_V << DMA2D_OUTLINK_PARK_CH0_S)
+#define DMA2D_OUTLINK_PARK_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH0_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH0_REG register
+ *  Configures the tx descriptor address of channel 0
+ */
+#define DMA2D_OUT_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x20)
+/** DMA2D_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH0_M  (DMA2D_OUTLINK_ADDR_CH0_V << DMA2D_OUTLINK_ADDR_CH0_S)
+#define DMA2D_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH0_S  0
+
+/** DMA2D_OUT_STATE_CH0_REG register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+#define DMA2D_OUT_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x24)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_M  (DMA2D_OUTLINK_DSCR_ADDR_CH0_V << DMA2D_OUTLINK_DSCR_ADDR_CH0_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_S  0
+/** DMA2D_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH0    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH0_M  (DMA2D_OUT_DSCR_STATE_CH0_V << DMA2D_OUT_DSCR_STATE_CH0_S)
+#define DMA2D_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH0_S  18
+/** DMA2D_OUT_STATE_CH0 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH0    0x0000000FU
+#define DMA2D_OUT_STATE_CH0_M  (DMA2D_OUT_STATE_CH0_V << DMA2D_OUT_STATE_CH0_S)
+#define DMA2D_OUT_STATE_CH0_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH0_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH0 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH0    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH0_M  (DMA2D_OUT_RESET_AVAIL_CH0_V << DMA2D_OUT_RESET_AVAIL_CH0_S)
+#define DMA2D_OUT_RESET_AVAIL_CH0_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH0_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x28)
+/** DMA2D_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_M  (DMA2D_OUT_EOF_DES_ADDR_CH0_V << DMA2D_OUT_EOF_DES_ADDR_CH0_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_OUT_DSCR_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x2c)
+/** DMA2D_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH0_M  (DMA2D_OUTLINK_DSCR_CH0_V << DMA2D_OUTLINK_DSCR_CH0_S)
+#define DMA2D_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH0_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x30)
+/** DMA2D_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_M  (DMA2D_OUTLINK_DSCR_BF0_CH0_V << DMA2D_OUTLINK_DSCR_BF0_CH0_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x34)
+/** DMA2D_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_M  (DMA2D_OUTLINK_DSCR_BF1_CH0_V << DMA2D_OUTLINK_DSCR_BF1_CH0_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH0_REG register
+ *  Configures the tx peripheral of channel 0
+ */
+#define DMA2D_OUT_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x38)
+/** DMA2D_OUT_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH0    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH0_M  (DMA2D_OUT_PERI_SEL_CH0_V << DMA2D_OUT_PERI_SEL_CH0_S)
+#define DMA2D_OUT_PERI_SEL_CH0_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH0_S  0
+
+/** DMA2D_OUT_ARB_CH0_REG register
+ *  Configures the tx arbiter of channel 0
+ */
+#define DMA2D_OUT_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x3c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH0    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH0_M  (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH0_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH0_S  4
+
+/** DMA2D_OUT_RO_STATUS_CH0_REG register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+#define DMA2D_OUT_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x40)
+/** DMA2D_OUTFIFO_RO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH0    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH0_M  (DMA2D_OUTFIFO_RO_CNT_CH0_V << DMA2D_OUTFIFO_RO_CNT_CH0_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH0_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH0_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH0 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH0    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH0_M  (DMA2D_OUT_RO_WR_STATE_CH0_V << DMA2D_OUT_RO_WR_STATE_CH0_S)
+#define DMA2D_OUT_RO_WR_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH0_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH0 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH0    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH0_M  (DMA2D_OUT_RO_RD_STATE_CH0_V << DMA2D_OUT_RO_RD_STATE_CH0_S)
+#define DMA2D_OUT_RO_RD_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH0_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH0 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH0    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH0_M  (DMA2D_OUT_PIXEL_BYTE_CH0_V << DMA2D_OUT_PIXEL_BYTE_CH0_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH0_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH0_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH0 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH0_V << DMA2D_OUT_BURST_BLOCK_NUM_CH0_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_S  14
+
+/** DMA2D_OUT_RO_PD_CONF_CH0_REG register
+ *  Configures the tx reorder memory of channel 0
+ */
+#define DMA2D_OUT_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x44)
+/** DMA2D_OUT_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_M  (DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S)
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S  4
+/** DMA2D_OUT_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_M  (DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S)
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S  5
+/** DMA2D_OUT_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_M  (DMA2D_OUT_RO_RAM_CLK_FO_CH0_V << DMA2D_OUT_RO_RAM_CLK_FO_CH0_S)
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_S  6
+
+/** DMA2D_OUT_COLOR_CONVERT_CH0_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x48)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH0_V << DMA2D_OUT_COLOR_INPUT_SEL_CH0_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH0_REG register
+ *  Configures the tx scramble of channel 0
+ */
+#define DMA2D_OUT_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x4c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x50)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_M  (DMA2D_OUT_COLOR_PARAM_H0_CH0_V << DMA2D_OUT_COLOR_PARAM_H0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x54)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_M  (DMA2D_OUT_COLOR_PARAM_H1_CH0_V << DMA2D_OUT_COLOR_PARAM_H1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x58)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_M  (DMA2D_OUT_COLOR_PARAM_M0_CH0_V << DMA2D_OUT_COLOR_PARAM_M0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x5c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_M  (DMA2D_OUT_COLOR_PARAM_M1_CH0_V << DMA2D_OUT_COLOR_PARAM_M1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x60)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_M  (DMA2D_OUT_COLOR_PARAM_L0_CH0_V << DMA2D_OUT_COLOR_PARAM_L0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x64)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_M  (DMA2D_OUT_COLOR_PARAM_L1_CH0_V << DMA2D_OUT_COLOR_PARAM_L1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH0_REG register
+ *  Configures the tx etm of channel 0
+ */
+#define DMA2D_OUT_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x68)
+/** DMA2D_OUT_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH0    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH0_M  (DMA2D_OUT_ETM_EN_CH0_V << DMA2D_OUT_ETM_EN_CH0_S)
+#define DMA2D_OUT_ETM_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH0_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH0    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_M  (DMA2D_OUT_ETM_LOOP_EN_CH0_V << DMA2D_OUT_ETM_LOOP_EN_CH0_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_M  (DMA2D_OUT_DSCR_TASK_MAK_CH0_V << DMA2D_OUT_DSCR_TASK_MAK_CH0_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH0_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH0_REG (DR_REG_DMA2D_BASE + 0x6c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH0 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH0 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S  14
+
+/** DMA2D_OUT_CONF0_CH1_REG register
+ *  Configures the tx direction of channel 0
+ */
+#define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100)
+/** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH1    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH1_M  (DMA2D_OUT_AUTO_WRBACK_CH1_V << DMA2D_OUT_AUTO_WRBACK_CH1_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH1_S  0
+/** DMA2D_OUT_EOF_MODE_CH1 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH1    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH1_M  (DMA2D_OUT_EOF_MODE_CH1_V << DMA2D_OUT_EOF_MODE_CH1_S)
+#define DMA2D_OUT_EOF_MODE_CH1_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH1_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH1    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH1_M  (DMA2D_OUTDSCR_BURST_EN_CH1_V << DMA2D_OUTDSCR_BURST_EN_CH1_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH1_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH1    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH1_M  (DMA2D_OUT_ECC_AES_EN_CH1_V << DMA2D_OUT_ECC_AES_EN_CH1_S)
+#define DMA2D_OUT_ECC_AES_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH1_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH1    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH1_M  (DMA2D_OUT_CHECK_OWNER_CH1_V << DMA2D_OUT_CHECK_OWNER_CH1_S)
+#define DMA2D_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH1_S  4
+/** DMA2D_OUT_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH1    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH1_M  (DMA2D_OUT_LOOP_TEST_CH1_V << DMA2D_OUT_LOOP_TEST_CH1_S)
+#define DMA2D_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH1_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH1_V << DMA2D_OUT_MEM_BURST_LENGTH_CH1_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH1    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_M  (DMA2D_OUT_DSCR_PORT_EN_CH1_V << DMA2D_OUT_DSCR_PORT_EN_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_M  (DMA2D_OUT_PAGE_BOUND_EN_CH1_V << DMA2D_OUT_PAGE_BOUND_EN_CH1_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_S  12
+/** DMA2D_OUT_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH1    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH1_M  (DMA2D_OUT_REORDER_EN_CH1_V << DMA2D_OUT_REORDER_EN_CH1_S)
+#define DMA2D_OUT_REORDER_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH1_S  16
+/** DMA2D_OUT_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH1    (BIT(24))
+#define DMA2D_OUT_RST_CH1_M  (DMA2D_OUT_RST_CH1_V << DMA2D_OUT_RST_CH1_S)
+#define DMA2D_OUT_RST_CH1_V  0x00000001U
+#define DMA2D_OUT_RST_CH1_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH1    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH1_M  (DMA2D_OUT_CMD_DISABLE_CH1_V << DMA2D_OUT_CMD_DISABLE_CH1_S)
+#define DMA2D_OUT_CMD_DISABLE_CH1_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH1_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** DMA2D_OUT_INT_RAW_CH1_REG register
+ *  Raw interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104)
+/** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_RAW_M  (DMA2D_OUT_DONE_CH1_INT_RAW_V << DMA2D_OUT_DONE_CH1_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_RAW_M  (DMA2D_OUT_EOF_CH1_INT_RAW_V << DMA2D_OUT_EOF_CH1_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108)
+/** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_ENA_M  (DMA2D_OUT_DONE_CH1_INT_ENA_V << DMA2D_OUT_DONE_CH1_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_ENA_M  (DMA2D_OUT_EOF_CH1_INT_ENA_V << DMA2D_OUT_EOF_CH1_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c)
+/** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_ST_M  (DMA2D_OUT_DONE_CH1_INT_ST_V << DMA2D_OUT_DONE_CH1_INT_ST_S)
+#define DMA2D_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_ST_M  (DMA2D_OUT_EOF_CH1_INT_ST_V << DMA2D_OUT_EOF_CH1_INT_ST_S)
+#define DMA2D_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110)
+/** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_CLR_M  (DMA2D_OUT_DONE_CH1_INT_CLR_V << DMA2D_OUT_DONE_CH1_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_CLR_M  (DMA2D_OUT_EOF_CH1_INT_CLR_V << DMA2D_OUT_EOF_CH1_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH1_REG register
+ *  Represents the status of the tx fifo of channel 0
+ */
+#define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114)
+/** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH1    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH1_M  (DMA2D_OUTFIFO_FULL_L2_CH1_V << DMA2D_OUTFIFO_FULL_L2_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH1_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_M  (DMA2D_OUTFIFO_EMPTY_L2_CH1_V << DMA2D_OUTFIFO_EMPTY_L2_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH1    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH1_M  (DMA2D_OUTFIFO_CNT_L2_CH1_V << DMA2D_OUTFIFO_CNT_L2_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH1_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH1_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH1_V << DMA2D_OUT_REMAIN_UNDER_1B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH1_V << DMA2D_OUT_REMAIN_UNDER_2B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH1_V << DMA2D_OUT_REMAIN_UNDER_3B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH1_V << DMA2D_OUT_REMAIN_UNDER_4B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH1_V << DMA2D_OUT_REMAIN_UNDER_5B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH1_V << DMA2D_OUT_REMAIN_UNDER_6B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH1_V << DMA2D_OUT_REMAIN_UNDER_7B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH1_V << DMA2D_OUT_REMAIN_UNDER_8B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH1    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH1_M  (DMA2D_OUTFIFO_FULL_L1_CH1_V << DMA2D_OUTFIFO_FULL_L1_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH1_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_M  (DMA2D_OUTFIFO_EMPTY_L1_CH1_V << DMA2D_OUTFIFO_EMPTY_L1_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH1    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH1_M  (DMA2D_OUTFIFO_CNT_L1_CH1_V << DMA2D_OUTFIFO_CNT_L1_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH1_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH1_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH1    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH1_M  (DMA2D_OUTFIFO_FULL_L3_CH1_V << DMA2D_OUTFIFO_FULL_L3_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH1_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_M  (DMA2D_OUTFIFO_EMPTY_L3_CH1_V << DMA2D_OUTFIFO_EMPTY_L3_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH1    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH1_M  (DMA2D_OUTFIFO_CNT_L3_CH1_V << DMA2D_OUTFIFO_CNT_L3_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH1_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH1_S  24
+
+/** DMA2D_OUT_PUSH_CH1_REG register
+ *  Configures the tx fifo of channel 0
+ */
+#define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118)
+/** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH1    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH1_M  (DMA2D_OUTFIFO_WDATA_CH1_V << DMA2D_OUTFIFO_WDATA_CH1_S)
+#define DMA2D_OUTFIFO_WDATA_CH1_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH1_S  0
+/** DMA2D_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH1    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH1_M  (DMA2D_OUTFIFO_PUSH_CH1_V << DMA2D_OUTFIFO_PUSH_CH1_S)
+#define DMA2D_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH1_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH1_REG register
+ *  Configures the tx descriptor operations of channel 0
+ */
+#define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c)
+/** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH1    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH1_M  (DMA2D_OUTLINK_STOP_CH1_V << DMA2D_OUTLINK_STOP_CH1_S)
+#define DMA2D_OUTLINK_STOP_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH1_S  20
+/** DMA2D_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH1    (BIT(21))
+#define DMA2D_OUTLINK_START_CH1_M  (DMA2D_OUTLINK_START_CH1_V << DMA2D_OUTLINK_START_CH1_S)
+#define DMA2D_OUTLINK_START_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH1_S  21
+/** DMA2D_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH1    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH1_M  (DMA2D_OUTLINK_RESTART_CH1_V << DMA2D_OUTLINK_RESTART_CH1_S)
+#define DMA2D_OUTLINK_RESTART_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH1_S  22
+/** DMA2D_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH1    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH1_M  (DMA2D_OUTLINK_PARK_CH1_V << DMA2D_OUTLINK_PARK_CH1_S)
+#define DMA2D_OUTLINK_PARK_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH1_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH1_REG register
+ *  Configures the tx descriptor address of channel 0
+ */
+#define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120)
+/** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH1_M  (DMA2D_OUTLINK_ADDR_CH1_V << DMA2D_OUTLINK_ADDR_CH1_S)
+#define DMA2D_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH1_S  0
+
+/** DMA2D_OUT_STATE_CH1_REG register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+#define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_M  (DMA2D_OUTLINK_DSCR_ADDR_CH1_V << DMA2D_OUTLINK_DSCR_ADDR_CH1_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_S  0
+/** DMA2D_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH1    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH1_M  (DMA2D_OUT_DSCR_STATE_CH1_V << DMA2D_OUT_DSCR_STATE_CH1_S)
+#define DMA2D_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH1_S  18
+/** DMA2D_OUT_STATE_CH1 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH1    0x0000000FU
+#define DMA2D_OUT_STATE_CH1_M  (DMA2D_OUT_STATE_CH1_V << DMA2D_OUT_STATE_CH1_S)
+#define DMA2D_OUT_STATE_CH1_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH1_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH1 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH1    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH1_M  (DMA2D_OUT_RESET_AVAIL_CH1_V << DMA2D_OUT_RESET_AVAIL_CH1_S)
+#define DMA2D_OUT_RESET_AVAIL_CH1_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH1_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128)
+/** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_M  (DMA2D_OUT_EOF_DES_ADDR_CH1_V << DMA2D_OUT_EOF_DES_ADDR_CH1_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_OUT_DSCR_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c)
+/** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH1_M  (DMA2D_OUTLINK_DSCR_CH1_V << DMA2D_OUTLINK_DSCR_CH1_S)
+#define DMA2D_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH1_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130)
+/** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_M  (DMA2D_OUTLINK_DSCR_BF0_CH1_V << DMA2D_OUTLINK_DSCR_BF0_CH1_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134)
+/** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_M  (DMA2D_OUTLINK_DSCR_BF1_CH1_V << DMA2D_OUTLINK_DSCR_BF1_CH1_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH1_REG register
+ *  Configures the tx peripheral of channel 0
+ */
+#define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138)
+/** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH1    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH1_M  (DMA2D_OUT_PERI_SEL_CH1_V << DMA2D_OUT_PERI_SEL_CH1_S)
+#define DMA2D_OUT_PERI_SEL_CH1_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH1_S  0
+
+/** DMA2D_OUT_ARB_CH1_REG register
+ *  Configures the tx arbiter of channel 0
+ */
+#define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH1    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH1_M  (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH1_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH1_S  4
+
+/** DMA2D_OUT_RO_STATUS_CH1_REG register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+#define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140)
+/** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH1    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH1_M  (DMA2D_OUTFIFO_RO_CNT_CH1_V << DMA2D_OUTFIFO_RO_CNT_CH1_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH1_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH1_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH1 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH1    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH1_M  (DMA2D_OUT_RO_WR_STATE_CH1_V << DMA2D_OUT_RO_WR_STATE_CH1_S)
+#define DMA2D_OUT_RO_WR_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH1_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH1 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH1    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH1_M  (DMA2D_OUT_RO_RD_STATE_CH1_V << DMA2D_OUT_RO_RD_STATE_CH1_S)
+#define DMA2D_OUT_RO_RD_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH1_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH1 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH1    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH1_M  (DMA2D_OUT_PIXEL_BYTE_CH1_V << DMA2D_OUT_PIXEL_BYTE_CH1_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH1_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH1_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH1 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH1_V << DMA2D_OUT_BURST_BLOCK_NUM_CH1_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH1_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH1_V << DMA2D_OUT_COLOR_INPUT_SEL_CH1_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH1_REG register
+ *  Configures the tx scramble of channel 0
+ */
+#define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_M  (DMA2D_OUT_COLOR_PARAM_H0_CH1_V << DMA2D_OUT_COLOR_PARAM_H0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_M  (DMA2D_OUT_COLOR_PARAM_H1_CH1_V << DMA2D_OUT_COLOR_PARAM_H1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_M  (DMA2D_OUT_COLOR_PARAM_M0_CH1_V << DMA2D_OUT_COLOR_PARAM_M0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_M  (DMA2D_OUT_COLOR_PARAM_M1_CH1_V << DMA2D_OUT_COLOR_PARAM_M1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_M  (DMA2D_OUT_COLOR_PARAM_L0_CH1_V << DMA2D_OUT_COLOR_PARAM_L0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_M  (DMA2D_OUT_COLOR_PARAM_L1_CH1_V << DMA2D_OUT_COLOR_PARAM_L1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH1_REG register
+ *  Configures the tx etm of channel 0
+ */
+#define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168)
+/** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH1    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH1_M  (DMA2D_OUT_ETM_EN_CH1_V << DMA2D_OUT_ETM_EN_CH1_S)
+#define DMA2D_OUT_ETM_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH1_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH1    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_M  (DMA2D_OUT_ETM_LOOP_EN_CH1_V << DMA2D_OUT_ETM_LOOP_EN_CH1_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_M  (DMA2D_OUT_DSCR_TASK_MAK_CH1_V << DMA2D_OUT_DSCR_TASK_MAK_CH1_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH1_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH1_REG (DR_REG_DMA2D_BASE + 0x16c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH1 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH1 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S  14
+
+/** DMA2D_OUT_CONF0_CH2_REG register
+ *  Configures the tx direction of channel 0
+ */
+#define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200)
+/** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH2    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH2_M  (DMA2D_OUT_AUTO_WRBACK_CH2_V << DMA2D_OUT_AUTO_WRBACK_CH2_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH2_S  0
+/** DMA2D_OUT_EOF_MODE_CH2 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH2    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH2_M  (DMA2D_OUT_EOF_MODE_CH2_V << DMA2D_OUT_EOF_MODE_CH2_S)
+#define DMA2D_OUT_EOF_MODE_CH2_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH2_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH2    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH2_M  (DMA2D_OUTDSCR_BURST_EN_CH2_V << DMA2D_OUTDSCR_BURST_EN_CH2_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH2_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH2    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH2_M  (DMA2D_OUT_ECC_AES_EN_CH2_V << DMA2D_OUT_ECC_AES_EN_CH2_S)
+#define DMA2D_OUT_ECC_AES_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH2_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH2    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH2_M  (DMA2D_OUT_CHECK_OWNER_CH2_V << DMA2D_OUT_CHECK_OWNER_CH2_S)
+#define DMA2D_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH2_S  4
+/** DMA2D_OUT_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH2    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH2_M  (DMA2D_OUT_LOOP_TEST_CH2_V << DMA2D_OUT_LOOP_TEST_CH2_S)
+#define DMA2D_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH2_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH2_V << DMA2D_OUT_MEM_BURST_LENGTH_CH2_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH2    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_M  (DMA2D_OUT_DSCR_PORT_EN_CH2_V << DMA2D_OUT_DSCR_PORT_EN_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_M  (DMA2D_OUT_PAGE_BOUND_EN_CH2_V << DMA2D_OUT_PAGE_BOUND_EN_CH2_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_S  12
+/** DMA2D_OUT_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH2    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH2_M  (DMA2D_OUT_REORDER_EN_CH2_V << DMA2D_OUT_REORDER_EN_CH2_S)
+#define DMA2D_OUT_REORDER_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH2_S  16
+/** DMA2D_OUT_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH2    (BIT(24))
+#define DMA2D_OUT_RST_CH2_M  (DMA2D_OUT_RST_CH2_V << DMA2D_OUT_RST_CH2_S)
+#define DMA2D_OUT_RST_CH2_V  0x00000001U
+#define DMA2D_OUT_RST_CH2_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH2    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH2_M  (DMA2D_OUT_CMD_DISABLE_CH2_V << DMA2D_OUT_CMD_DISABLE_CH2_S)
+#define DMA2D_OUT_CMD_DISABLE_CH2_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH2_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** DMA2D_OUT_INT_RAW_CH2_REG register
+ *  Raw interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204)
+/** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_RAW_M  (DMA2D_OUT_DONE_CH2_INT_RAW_V << DMA2D_OUT_DONE_CH2_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_RAW_M  (DMA2D_OUT_EOF_CH2_INT_RAW_V << DMA2D_OUT_EOF_CH2_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208)
+/** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_ENA_M  (DMA2D_OUT_DONE_CH2_INT_ENA_V << DMA2D_OUT_DONE_CH2_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_ENA_M  (DMA2D_OUT_EOF_CH2_INT_ENA_V << DMA2D_OUT_EOF_CH2_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c)
+/** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_ST_M  (DMA2D_OUT_DONE_CH2_INT_ST_V << DMA2D_OUT_DONE_CH2_INT_ST_S)
+#define DMA2D_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_ST_M  (DMA2D_OUT_EOF_CH2_INT_ST_V << DMA2D_OUT_EOF_CH2_INT_ST_S)
+#define DMA2D_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210)
+/** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_CLR_M  (DMA2D_OUT_DONE_CH2_INT_CLR_V << DMA2D_OUT_DONE_CH2_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_CLR_M  (DMA2D_OUT_EOF_CH2_INT_CLR_V << DMA2D_OUT_EOF_CH2_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH2_REG register
+ *  Represents the status of the tx fifo of channel 0
+ */
+#define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214)
+/** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH2    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH2_M  (DMA2D_OUTFIFO_FULL_L2_CH2_V << DMA2D_OUTFIFO_FULL_L2_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH2_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_M  (DMA2D_OUTFIFO_EMPTY_L2_CH2_V << DMA2D_OUTFIFO_EMPTY_L2_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH2    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH2_M  (DMA2D_OUTFIFO_CNT_L2_CH2_V << DMA2D_OUTFIFO_CNT_L2_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH2_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH2_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH2_V << DMA2D_OUT_REMAIN_UNDER_1B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH2_V << DMA2D_OUT_REMAIN_UNDER_2B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH2_V << DMA2D_OUT_REMAIN_UNDER_3B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH2_V << DMA2D_OUT_REMAIN_UNDER_4B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH2_V << DMA2D_OUT_REMAIN_UNDER_5B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH2_V << DMA2D_OUT_REMAIN_UNDER_6B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH2_V << DMA2D_OUT_REMAIN_UNDER_7B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH2_V << DMA2D_OUT_REMAIN_UNDER_8B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH2    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH2_M  (DMA2D_OUTFIFO_FULL_L1_CH2_V << DMA2D_OUTFIFO_FULL_L1_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH2_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_M  (DMA2D_OUTFIFO_EMPTY_L1_CH2_V << DMA2D_OUTFIFO_EMPTY_L1_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH2    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH2_M  (DMA2D_OUTFIFO_CNT_L1_CH2_V << DMA2D_OUTFIFO_CNT_L1_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH2_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH2_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH2    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH2_M  (DMA2D_OUTFIFO_FULL_L3_CH2_V << DMA2D_OUTFIFO_FULL_L3_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH2_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_M  (DMA2D_OUTFIFO_EMPTY_L3_CH2_V << DMA2D_OUTFIFO_EMPTY_L3_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH2    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH2_M  (DMA2D_OUTFIFO_CNT_L3_CH2_V << DMA2D_OUTFIFO_CNT_L3_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH2_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH2_S  24
+
+/** DMA2D_OUT_PUSH_CH2_REG register
+ *  Configures the tx fifo of channel 0
+ */
+#define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218)
+/** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH2    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH2_M  (DMA2D_OUTFIFO_WDATA_CH2_V << DMA2D_OUTFIFO_WDATA_CH2_S)
+#define DMA2D_OUTFIFO_WDATA_CH2_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH2_S  0
+/** DMA2D_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH2    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH2_M  (DMA2D_OUTFIFO_PUSH_CH2_V << DMA2D_OUTFIFO_PUSH_CH2_S)
+#define DMA2D_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH2_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH2_REG register
+ *  Configures the tx descriptor operations of channel 0
+ */
+#define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c)
+/** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH2    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH2_M  (DMA2D_OUTLINK_STOP_CH2_V << DMA2D_OUTLINK_STOP_CH2_S)
+#define DMA2D_OUTLINK_STOP_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH2_S  20
+/** DMA2D_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH2    (BIT(21))
+#define DMA2D_OUTLINK_START_CH2_M  (DMA2D_OUTLINK_START_CH2_V << DMA2D_OUTLINK_START_CH2_S)
+#define DMA2D_OUTLINK_START_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH2_S  21
+/** DMA2D_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH2    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH2_M  (DMA2D_OUTLINK_RESTART_CH2_V << DMA2D_OUTLINK_RESTART_CH2_S)
+#define DMA2D_OUTLINK_RESTART_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH2_S  22
+/** DMA2D_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH2    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH2_M  (DMA2D_OUTLINK_PARK_CH2_V << DMA2D_OUTLINK_PARK_CH2_S)
+#define DMA2D_OUTLINK_PARK_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH2_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH2_REG register
+ *  Configures the tx descriptor address of channel 0
+ */
+#define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220)
+/** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH2_M  (DMA2D_OUTLINK_ADDR_CH2_V << DMA2D_OUTLINK_ADDR_CH2_S)
+#define DMA2D_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH2_S  0
+
+/** DMA2D_OUT_STATE_CH2_REG register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+#define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_M  (DMA2D_OUTLINK_DSCR_ADDR_CH2_V << DMA2D_OUTLINK_DSCR_ADDR_CH2_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_S  0
+/** DMA2D_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH2    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH2_M  (DMA2D_OUT_DSCR_STATE_CH2_V << DMA2D_OUT_DSCR_STATE_CH2_S)
+#define DMA2D_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH2_S  18
+/** DMA2D_OUT_STATE_CH2 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH2    0x0000000FU
+#define DMA2D_OUT_STATE_CH2_M  (DMA2D_OUT_STATE_CH2_V << DMA2D_OUT_STATE_CH2_S)
+#define DMA2D_OUT_STATE_CH2_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH2_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH2 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH2    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH2_M  (DMA2D_OUT_RESET_AVAIL_CH2_V << DMA2D_OUT_RESET_AVAIL_CH2_S)
+#define DMA2D_OUT_RESET_AVAIL_CH2_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH2_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228)
+/** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_M  (DMA2D_OUT_EOF_DES_ADDR_CH2_V << DMA2D_OUT_EOF_DES_ADDR_CH2_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_OUT_DSCR_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c)
+/** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH2_M  (DMA2D_OUTLINK_DSCR_CH2_V << DMA2D_OUTLINK_DSCR_CH2_S)
+#define DMA2D_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH2_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230)
+/** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_M  (DMA2D_OUTLINK_DSCR_BF0_CH2_V << DMA2D_OUTLINK_DSCR_BF0_CH2_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234)
+/** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_M  (DMA2D_OUTLINK_DSCR_BF1_CH2_V << DMA2D_OUTLINK_DSCR_BF1_CH2_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH2_REG register
+ *  Configures the tx peripheral of channel 0
+ */
+#define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238)
+/** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH2    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH2_M  (DMA2D_OUT_PERI_SEL_CH2_V << DMA2D_OUT_PERI_SEL_CH2_S)
+#define DMA2D_OUT_PERI_SEL_CH2_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH2_S  0
+
+/** DMA2D_OUT_ARB_CH2_REG register
+ *  Configures the tx arbiter of channel 0
+ */
+#define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH2    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH2_M  (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH2_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH2_S  4
+
+/** DMA2D_OUT_RO_STATUS_CH2_REG register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+#define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240)
+/** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH2    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH2_M  (DMA2D_OUTFIFO_RO_CNT_CH2_V << DMA2D_OUTFIFO_RO_CNT_CH2_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH2_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH2_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH2 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH2    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH2_M  (DMA2D_OUT_RO_WR_STATE_CH2_V << DMA2D_OUT_RO_WR_STATE_CH2_S)
+#define DMA2D_OUT_RO_WR_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH2_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH2 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH2    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH2_M  (DMA2D_OUT_RO_RD_STATE_CH2_V << DMA2D_OUT_RO_RD_STATE_CH2_S)
+#define DMA2D_OUT_RO_RD_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH2_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH2 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH2    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH2_M  (DMA2D_OUT_PIXEL_BYTE_CH2_V << DMA2D_OUT_PIXEL_BYTE_CH2_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH2_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH2_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH2 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH2_V << DMA2D_OUT_BURST_BLOCK_NUM_CH2_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH2_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH2_V << DMA2D_OUT_COLOR_INPUT_SEL_CH2_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH2_REG register
+ *  Configures the tx scramble of channel 0
+ */
+#define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_M  (DMA2D_OUT_COLOR_PARAM_H0_CH2_V << DMA2D_OUT_COLOR_PARAM_H0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_M  (DMA2D_OUT_COLOR_PARAM_H1_CH2_V << DMA2D_OUT_COLOR_PARAM_H1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_M  (DMA2D_OUT_COLOR_PARAM_M0_CH2_V << DMA2D_OUT_COLOR_PARAM_M0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_M  (DMA2D_OUT_COLOR_PARAM_M1_CH2_V << DMA2D_OUT_COLOR_PARAM_M1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_M  (DMA2D_OUT_COLOR_PARAM_L0_CH2_V << DMA2D_OUT_COLOR_PARAM_L0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_M  (DMA2D_OUT_COLOR_PARAM_L1_CH2_V << DMA2D_OUT_COLOR_PARAM_L1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH2_REG register
+ *  Configures the tx etm of channel 0
+ */
+#define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268)
+/** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH2    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH2_M  (DMA2D_OUT_ETM_EN_CH2_V << DMA2D_OUT_ETM_EN_CH2_S)
+#define DMA2D_OUT_ETM_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH2_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH2    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_M  (DMA2D_OUT_ETM_LOOP_EN_CH2_V << DMA2D_OUT_ETM_LOOP_EN_CH2_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_M  (DMA2D_OUT_DSCR_TASK_MAK_CH2_V << DMA2D_OUT_DSCR_TASK_MAK_CH2_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH2_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH2_REG (DR_REG_DMA2D_BASE + 0x26c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH2 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH2 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S  14
+
+/** DMA2D_IN_CONF0_CH0_REG register
+ *  Configures the rx direction of channel 0
+ */
+#define DMA2D_IN_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x500)
+/** DMA2D_IN_MEM_TRANS_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH0    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH0_M  (DMA2D_IN_MEM_TRANS_EN_CH0_V << DMA2D_IN_MEM_TRANS_EN_CH0_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH0_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH0_S  0
+/** DMA2D_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH0    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH0_M  (DMA2D_INDSCR_BURST_EN_CH0_V << DMA2D_INDSCR_BURST_EN_CH0_S)
+#define DMA2D_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH0_S  2
+/** DMA2D_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH0    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH0_M  (DMA2D_IN_ECC_AES_EN_CH0_V << DMA2D_IN_ECC_AES_EN_CH0_S)
+#define DMA2D_IN_ECC_AES_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH0_S  3
+/** DMA2D_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH0    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH0_M  (DMA2D_IN_CHECK_OWNER_CH0_V << DMA2D_IN_CHECK_OWNER_CH0_S)
+#define DMA2D_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH0_S  4
+/** DMA2D_IN_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH0    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH0_M  (DMA2D_IN_LOOP_TEST_CH0_V << DMA2D_IN_LOOP_TEST_CH0_S)
+#define DMA2D_IN_LOOP_TEST_CH0_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH0_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_M  (DMA2D_IN_MEM_BURST_LENGTH_CH0_V << DMA2D_IN_MEM_BURST_LENGTH_CH0_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH0    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH0_M  (DMA2D_IN_DSCR_PORT_EN_CH0_V << DMA2D_IN_DSCR_PORT_EN_CH0_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH0_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH0_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH0    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_M  (DMA2D_IN_PAGE_BOUND_EN_CH0_V << DMA2D_IN_PAGE_BOUND_EN_CH0_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_S  12
+/** DMA2D_IN_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH0    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH0_M  (DMA2D_IN_REORDER_EN_CH0_V << DMA2D_IN_REORDER_EN_CH0_S)
+#define DMA2D_IN_REORDER_EN_CH0_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH0_S  16
+/** DMA2D_IN_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH0    (BIT(24))
+#define DMA2D_IN_RST_CH0_M  (DMA2D_IN_RST_CH0_V << DMA2D_IN_RST_CH0_S)
+#define DMA2D_IN_RST_CH0_V  0x00000001U
+#define DMA2D_IN_RST_CH0_S  24
+/** DMA2D_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH0    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH0_M  (DMA2D_IN_CMD_DISABLE_CH0_V << DMA2D_IN_CMD_DISABLE_CH0_S)
+#define DMA2D_IN_CMD_DISABLE_CH0_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH0_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** DMA2D_IN_INT_RAW_CH0_REG register
+ *  Raw interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x504)
+/** DMA2D_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_RAW_M  (DMA2D_IN_DONE_CH0_INT_RAW_V << DMA2D_IN_DONE_CH0_INT_RAW_S)
+#define DMA2D_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH0_INT_RAW_V << DMA2D_IN_SUC_EOF_CH0_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH0_INT_RAW_V << DMA2D_IN_ERR_EOF_CH0_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of RX channel 0
+ */
+#define DMA2D_IN_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x508)
+/** DMA2D_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_ENA_M  (DMA2D_IN_DONE_CH0_INT_ENA_V << DMA2D_IN_DONE_CH0_INT_ENA_S)
+#define DMA2D_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH0_INT_ENA_V << DMA2D_IN_SUC_EOF_CH0_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH0_INT_ENA_V << DMA2D_IN_ERR_EOF_CH0_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH0_REG register
+ *  Masked interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0x50c)
+/** DMA2D_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_ST_M  (DMA2D_IN_DONE_CH0_INT_ST_V << DMA2D_IN_DONE_CH0_INT_ST_S)
+#define DMA2D_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_M  (DMA2D_IN_SUC_EOF_CH0_INT_ST_V << DMA2D_IN_SUC_EOF_CH0_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_M  (DMA2D_IN_ERR_EOF_CH0_INT_ST_V << DMA2D_IN_ERR_EOF_CH0_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH0_INT_ST_V << DMA2D_IN_DSCR_ERR_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of RX channel 0
+ */
+#define DMA2D_IN_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x510)
+/** DMA2D_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_CLR_M  (DMA2D_IN_DONE_CH0_INT_CLR_V << DMA2D_IN_DONE_CH0_INT_CLR_S)
+#define DMA2D_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH0_INT_CLR_V << DMA2D_IN_SUC_EOF_CH0_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH0_INT_CLR_V << DMA2D_IN_ERR_EOF_CH0_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH0_REG register
+ *  Represents the status of the rx fifo of channel 0
+ */
+#define DMA2D_INFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x514)
+/** DMA2D_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH0    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH0_M  (DMA2D_INFIFO_FULL_L2_CH0_V << DMA2D_INFIFO_FULL_L2_CH0_S)
+#define DMA2D_INFIFO_FULL_L2_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH0_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH0    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH0_M  (DMA2D_INFIFO_EMPTY_L2_CH0_V << DMA2D_INFIFO_EMPTY_L2_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH0_S  1
+/** DMA2D_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH0    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH0_M  (DMA2D_INFIFO_CNT_L2_CH0_V << DMA2D_INFIFO_CNT_L2_CH0_S)
+#define DMA2D_INFIFO_CNT_L2_CH0_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH0_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_M  (DMA2D_IN_REMAIN_UNDER_1B_CH0_V << DMA2D_IN_REMAIN_UNDER_1B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_M  (DMA2D_IN_REMAIN_UNDER_2B_CH0_V << DMA2D_IN_REMAIN_UNDER_2B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_M  (DMA2D_IN_REMAIN_UNDER_3B_CH0_V << DMA2D_IN_REMAIN_UNDER_3B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_M  (DMA2D_IN_REMAIN_UNDER_4B_CH0_V << DMA2D_IN_REMAIN_UNDER_4B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_M  (DMA2D_IN_REMAIN_UNDER_5B_CH0_V << DMA2D_IN_REMAIN_UNDER_5B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_M  (DMA2D_IN_REMAIN_UNDER_6B_CH0_V << DMA2D_IN_REMAIN_UNDER_6B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_M  (DMA2D_IN_REMAIN_UNDER_7B_CH0_V << DMA2D_IN_REMAIN_UNDER_7B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_M  (DMA2D_IN_REMAIN_UNDER_8B_CH0_V << DMA2D_IN_REMAIN_UNDER_8B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_S  14
+/** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH0    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH0_M  (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S)
+#define DMA2D_INFIFO_FULL_L1_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH0_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH0    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH0_M  (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH0_S  16
+/** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH0    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH0_M  (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S)
+#define DMA2D_INFIFO_CNT_L1_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH0_S  17
+/** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH0    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH0_M  (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S)
+#define DMA2D_INFIFO_FULL_L3_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH0_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH0    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH0_M  (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH0_S  23
+/** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH0    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH0_M  (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S)
+#define DMA2D_INFIFO_CNT_L3_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH0_S  24
+
+/** DMA2D_IN_POP_CH0_REG register
+ *  Configures the rx fifo of channel 0
+ */
+#define DMA2D_IN_POP_CH0_REG (DR_REG_DMA2D_BASE + 0x518)
+/** DMA2D_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH0    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH0_M  (DMA2D_INFIFO_RDATA_CH0_V << DMA2D_INFIFO_RDATA_CH0_S)
+#define DMA2D_INFIFO_RDATA_CH0_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH0_S  0
+/** DMA2D_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH0    (BIT(11))
+#define DMA2D_INFIFO_POP_CH0_M  (DMA2D_INFIFO_POP_CH0_V << DMA2D_INFIFO_POP_CH0_S)
+#define DMA2D_INFIFO_POP_CH0_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH0_S  11
+
+/** DMA2D_IN_LINK_CONF_CH0_REG register
+ *  Configures the rx descriptor operations of channel 0
+ */
+#define DMA2D_IN_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x51c)
+/** DMA2D_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1;
+ *  Configure the value of the owner field written back to the inlink descriptor.
+ *  1: Write back 1. 0: Write back 0.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH0    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH0_M  (DMA2D_INLINK_AUTO_RET_CH0_V << DMA2D_INLINK_AUTO_RET_CH0_S)
+#define DMA2D_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH0_S  20
+/** DMA2D_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH0    (BIT(21))
+#define DMA2D_INLINK_STOP_CH0_M  (DMA2D_INLINK_STOP_CH0_V << DMA2D_INLINK_STOP_CH0_S)
+#define DMA2D_INLINK_STOP_CH0_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH0_S  21
+/** DMA2D_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH0    (BIT(22))
+#define DMA2D_INLINK_START_CH0_M  (DMA2D_INLINK_START_CH0_V << DMA2D_INLINK_START_CH0_S)
+#define DMA2D_INLINK_START_CH0_V  0x00000001U
+#define DMA2D_INLINK_START_CH0_S  22
+/** DMA2D_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH0    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH0_M  (DMA2D_INLINK_RESTART_CH0_V << DMA2D_INLINK_RESTART_CH0_S)
+#define DMA2D_INLINK_RESTART_CH0_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH0_S  23
+/** DMA2D_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH0    (BIT(24))
+#define DMA2D_INLINK_PARK_CH0_M  (DMA2D_INLINK_PARK_CH0_V << DMA2D_INLINK_PARK_CH0_S)
+#define DMA2D_INLINK_PARK_CH0_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH0_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH0_REG register
+ *  Configures the rx descriptor address of channel 0
+ */
+#define DMA2D_IN_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x520)
+/** DMA2D_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH0_M  (DMA2D_INLINK_ADDR_CH0_V << DMA2D_INLINK_ADDR_CH0_S)
+#define DMA2D_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH0_S  0
+
+/** DMA2D_IN_STATE_CH0_REG register
+ *  Represents the working status of the rx descriptor of channel 0
+ */
+#define DMA2D_IN_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x524)
+/** DMA2D_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH0_M  (DMA2D_INLINK_DSCR_ADDR_CH0_V << DMA2D_INLINK_DSCR_ADDR_CH0_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH0_S  0
+/** DMA2D_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH0    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH0_M  (DMA2D_IN_DSCR_STATE_CH0_V << DMA2D_IN_DSCR_STATE_CH0_S)
+#define DMA2D_IN_DSCR_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH0_S  18
+/** DMA2D_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH0    0x00000007U
+#define DMA2D_IN_STATE_CH0_M  (DMA2D_IN_STATE_CH0_V << DMA2D_IN_STATE_CH0_S)
+#define DMA2D_IN_STATE_CH0_V  0x00000007U
+#define DMA2D_IN_STATE_CH0_S  20
+/** DMA2D_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH0    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH0_M  (DMA2D_IN_RESET_AVAIL_CH0_V << DMA2D_IN_RESET_AVAIL_CH0_S)
+#define DMA2D_IN_RESET_AVAIL_CH0_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH0_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x528)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x52c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_IN_DSCR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x530)
+/** DMA2D_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH0_M  (DMA2D_INLINK_DSCR_CH0_V << DMA2D_INLINK_DSCR_CH0_S)
+#define DMA2D_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH0_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x534)
+/** DMA2D_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH0_M  (DMA2D_INLINK_DSCR_BF0_CH0_V << DMA2D_INLINK_DSCR_BF0_CH0_S)
+#define DMA2D_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH0_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x538)
+/** DMA2D_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH0_M  (DMA2D_INLINK_DSCR_BF1_CH0_V << DMA2D_INLINK_DSCR_BF1_CH0_S)
+#define DMA2D_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH0_S  0
+
+/** DMA2D_IN_PERI_SEL_CH0_REG register
+ *  Configures the rx peripheral of channel 0
+ */
+#define DMA2D_IN_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x53c)
+/** DMA2D_IN_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH0    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH0_M  (DMA2D_IN_PERI_SEL_CH0_V << DMA2D_IN_PERI_SEL_CH0_S)
+#define DMA2D_IN_PERI_SEL_CH0_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH0_S  0
+
+/** DMA2D_IN_ARB_CH0_REG register
+ *  Configures the rx arbiter of channel 0
+ */
+#define DMA2D_IN_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x540)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_M  (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH0    (BIT(4))
+#define DMA2D_IN_ARB_PRIORITY_CH0_M  (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S)
+#define DMA2D_IN_ARB_PRIORITY_CH0_V  0x00000001U
+#define DMA2D_IN_ARB_PRIORITY_CH0_S  4
+
+/** DMA2D_IN_RO_STATUS_CH0_REG register
+ *  Represents the status of the rx reorder module of channel 0
+ */
+#define DMA2D_IN_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x544)
+/** DMA2D_INFIFO_RO_CNT_CH0 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH0    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH0_M  (DMA2D_INFIFO_RO_CNT_CH0_V << DMA2D_INFIFO_RO_CNT_CH0_S)
+#define DMA2D_INFIFO_RO_CNT_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH0_S  0
+/** DMA2D_IN_RO_WR_STATE_CH0 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH0    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH0_M  (DMA2D_IN_RO_WR_STATE_CH0_V << DMA2D_IN_RO_WR_STATE_CH0_S)
+#define DMA2D_IN_RO_WR_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH0_S  5
+/** DMA2D_IN_RO_RD_STATE_CH0 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH0    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH0_M  (DMA2D_IN_RO_RD_STATE_CH0_V << DMA2D_IN_RO_RD_STATE_CH0_S)
+#define DMA2D_IN_RO_RD_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH0_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH0 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH0    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH0_M  (DMA2D_IN_PIXEL_BYTE_CH0_V << DMA2D_IN_PIXEL_BYTE_CH0_S)
+#define DMA2D_IN_PIXEL_BYTE_CH0_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH0_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH0 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_M  (DMA2D_IN_BURST_BLOCK_NUM_CH0_V << DMA2D_IN_BURST_BLOCK_NUM_CH0_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_S  13
+
+/** DMA2D_IN_RO_PD_CONF_CH0_REG register
+ *  Configures the rx reorder memory of channel 0
+ */
+#define DMA2D_IN_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x548)
+/** DMA2D_IN_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_M  (DMA2D_IN_RO_RAM_FORCE_PD_CH0_V << DMA2D_IN_RO_RAM_FORCE_PD_CH0_S)
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_S  4
+/** DMA2D_IN_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_M  (DMA2D_IN_RO_RAM_FORCE_PU_CH0_V << DMA2D_IN_RO_RAM_FORCE_PU_CH0_S)
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_S  5
+/** DMA2D_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_M  (DMA2D_IN_RO_RAM_CLK_FO_CH0_V << DMA2D_IN_RO_RAM_CLK_FO_CH0_S)
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_S  6
+
+/** DMA2D_IN_COLOR_CONVERT_CH0_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c)
+/** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  output directly
+ */
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0    0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M  (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S)
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V  0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S  0
+/** DMA2D_IN_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0    (BIT(2))
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_M  (DMA2D_IN_COLOR_3B_PROC_EN_CH0_V << DMA2D_IN_COLOR_3B_PROC_EN_CH0_S)
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_V  0x00000001U
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_S  2
+/** DMA2D_IN_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+ *  1: YUV422      2: YUV444/420      7: disable color space convert
+ */
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0    0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_M  (DMA2D_IN_COLOR_INPUT_SEL_CH0_V << DMA2D_IN_COLOR_INPUT_SEL_CH0_S)
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_V  0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_S  3
+
+/** DMA2D_IN_SCRAMBLE_CH0_REG register
+ *  Configures the rx scramble of channel 0
+ */
+#define DMA2D_IN_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x550)
+/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_M  (DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S)
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S  0
+/** DMA2D_IN_SCRAMBLE_SEL_POST_CH0 : R/W; bitpos: [5:3]; default: 0;
+ *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+ *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_M  (DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S)
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S  3
+
+/** DMA2D_IN_COLOR_PARAM0_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x554)
+/** DMA2D_IN_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_M  (DMA2D_IN_COLOR_PARAM_H0_CH0_V << DMA2D_IN_COLOR_PARAM_H0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM1_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x558)
+/** DMA2D_IN_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_M  (DMA2D_IN_COLOR_PARAM_H1_CH0_V << DMA2D_IN_COLOR_PARAM_H1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM2_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x55c)
+/** DMA2D_IN_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_M  (DMA2D_IN_COLOR_PARAM_M0_CH0_V << DMA2D_IN_COLOR_PARAM_M0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM3_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x560)
+/** DMA2D_IN_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_M  (DMA2D_IN_COLOR_PARAM_M1_CH0_V << DMA2D_IN_COLOR_PARAM_M1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM4_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x564)
+/** DMA2D_IN_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_M  (DMA2D_IN_COLOR_PARAM_L0_CH0_V << DMA2D_IN_COLOR_PARAM_L0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM5_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x568)
+/** DMA2D_IN_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_M  (DMA2D_IN_COLOR_PARAM_L1_CH0_V << DMA2D_IN_COLOR_PARAM_L1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_S  0
+
+/** DMA2D_IN_ETM_CONF_CH0_REG register
+ *  Configures the rx etm of channel 0
+ */
+#define DMA2D_IN_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x56c)
+/** DMA2D_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH0    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH0_M  (DMA2D_IN_ETM_EN_CH0_V << DMA2D_IN_ETM_EN_CH0_S)
+#define DMA2D_IN_ETM_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH0_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH0    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH0_M  (DMA2D_IN_ETM_LOOP_EN_CH0_V << DMA2D_IN_ETM_LOOP_EN_CH0_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH0_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH0    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_M  (DMA2D_IN_DSCR_TASK_MAK_CH0_V << DMA2D_IN_DSCR_TASK_MAK_CH0_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_S  2
+
+/** DMA2D_IN_CONF0_CH1_REG register
+ *  Configures the rx direction of channel 0
+ */
+#define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600)
+/** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH1    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH1_M  (DMA2D_IN_MEM_TRANS_EN_CH1_V << DMA2D_IN_MEM_TRANS_EN_CH1_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH1_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH1_S  0
+/** DMA2D_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH1    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH1_M  (DMA2D_INDSCR_BURST_EN_CH1_V << DMA2D_INDSCR_BURST_EN_CH1_S)
+#define DMA2D_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH1_S  2
+/** DMA2D_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH1    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH1_M  (DMA2D_IN_ECC_AES_EN_CH1_V << DMA2D_IN_ECC_AES_EN_CH1_S)
+#define DMA2D_IN_ECC_AES_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH1_S  3
+/** DMA2D_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH1    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH1_M  (DMA2D_IN_CHECK_OWNER_CH1_V << DMA2D_IN_CHECK_OWNER_CH1_S)
+#define DMA2D_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH1_S  4
+/** DMA2D_IN_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH1    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH1_M  (DMA2D_IN_LOOP_TEST_CH1_V << DMA2D_IN_LOOP_TEST_CH1_S)
+#define DMA2D_IN_LOOP_TEST_CH1_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH1_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_M  (DMA2D_IN_MEM_BURST_LENGTH_CH1_V << DMA2D_IN_MEM_BURST_LENGTH_CH1_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH1    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH1_M  (DMA2D_IN_DSCR_PORT_EN_CH1_V << DMA2D_IN_DSCR_PORT_EN_CH1_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH1_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH1_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH1    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_M  (DMA2D_IN_PAGE_BOUND_EN_CH1_V << DMA2D_IN_PAGE_BOUND_EN_CH1_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_S  12
+/** DMA2D_IN_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH1    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH1_M  (DMA2D_IN_REORDER_EN_CH1_V << DMA2D_IN_REORDER_EN_CH1_S)
+#define DMA2D_IN_REORDER_EN_CH1_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH1_S  16
+/** DMA2D_IN_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH1    (BIT(24))
+#define DMA2D_IN_RST_CH1_M  (DMA2D_IN_RST_CH1_V << DMA2D_IN_RST_CH1_S)
+#define DMA2D_IN_RST_CH1_V  0x00000001U
+#define DMA2D_IN_RST_CH1_S  24
+/** DMA2D_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH1    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH1_M  (DMA2D_IN_CMD_DISABLE_CH1_V << DMA2D_IN_CMD_DISABLE_CH1_S)
+#define DMA2D_IN_CMD_DISABLE_CH1_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH1_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** DMA2D_IN_INT_RAW_CH1_REG register
+ *  Raw interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604)
+/** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_RAW_M  (DMA2D_IN_DONE_CH1_INT_RAW_V << DMA2D_IN_DONE_CH1_INT_RAW_S)
+#define DMA2D_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH1_INT_RAW_V << DMA2D_IN_SUC_EOF_CH1_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH1_INT_RAW_V << DMA2D_IN_ERR_EOF_CH1_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of RX channel 0
+ */
+#define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608)
+/** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_ENA_M  (DMA2D_IN_DONE_CH1_INT_ENA_V << DMA2D_IN_DONE_CH1_INT_ENA_S)
+#define DMA2D_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH1_INT_ENA_V << DMA2D_IN_SUC_EOF_CH1_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH1_INT_ENA_V << DMA2D_IN_ERR_EOF_CH1_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH1_REG register
+ *  Masked interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c)
+/** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_ST_M  (DMA2D_IN_DONE_CH1_INT_ST_V << DMA2D_IN_DONE_CH1_INT_ST_S)
+#define DMA2D_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_M  (DMA2D_IN_SUC_EOF_CH1_INT_ST_V << DMA2D_IN_SUC_EOF_CH1_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_M  (DMA2D_IN_ERR_EOF_CH1_INT_ST_V << DMA2D_IN_ERR_EOF_CH1_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH1_INT_ST_V << DMA2D_IN_DSCR_ERR_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of RX channel 0
+ */
+#define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610)
+/** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_CLR_M  (DMA2D_IN_DONE_CH1_INT_CLR_V << DMA2D_IN_DONE_CH1_INT_CLR_S)
+#define DMA2D_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH1_INT_CLR_V << DMA2D_IN_SUC_EOF_CH1_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH1_INT_CLR_V << DMA2D_IN_ERR_EOF_CH1_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH1_REG register
+ *  Represents the status of the rx fifo of channel 0
+ */
+#define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614)
+/** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH1    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH1_M  (DMA2D_INFIFO_FULL_L2_CH1_V << DMA2D_INFIFO_FULL_L2_CH1_S)
+#define DMA2D_INFIFO_FULL_L2_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH1_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH1    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH1_M  (DMA2D_INFIFO_EMPTY_L2_CH1_V << DMA2D_INFIFO_EMPTY_L2_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH1_S  1
+/** DMA2D_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH1    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH1_M  (DMA2D_INFIFO_CNT_L2_CH1_V << DMA2D_INFIFO_CNT_L2_CH1_S)
+#define DMA2D_INFIFO_CNT_L2_CH1_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH1_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_M  (DMA2D_IN_REMAIN_UNDER_1B_CH1_V << DMA2D_IN_REMAIN_UNDER_1B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_M  (DMA2D_IN_REMAIN_UNDER_2B_CH1_V << DMA2D_IN_REMAIN_UNDER_2B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_M  (DMA2D_IN_REMAIN_UNDER_3B_CH1_V << DMA2D_IN_REMAIN_UNDER_3B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_M  (DMA2D_IN_REMAIN_UNDER_4B_CH1_V << DMA2D_IN_REMAIN_UNDER_4B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_M  (DMA2D_IN_REMAIN_UNDER_5B_CH1_V << DMA2D_IN_REMAIN_UNDER_5B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_M  (DMA2D_IN_REMAIN_UNDER_6B_CH1_V << DMA2D_IN_REMAIN_UNDER_6B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_M  (DMA2D_IN_REMAIN_UNDER_7B_CH1_V << DMA2D_IN_REMAIN_UNDER_7B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_M  (DMA2D_IN_REMAIN_UNDER_8B_CH1_V << DMA2D_IN_REMAIN_UNDER_8B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_S  14
+/** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH1    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH1_M  (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S)
+#define DMA2D_INFIFO_FULL_L1_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH1_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH1    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH1_M  (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH1_S  16
+/** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH1    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH1_M  (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S)
+#define DMA2D_INFIFO_CNT_L1_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH1_S  17
+/** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH1    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH1_M  (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S)
+#define DMA2D_INFIFO_FULL_L3_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH1_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH1    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH1_M  (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH1_S  23
+/** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH1    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH1_M  (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S)
+#define DMA2D_INFIFO_CNT_L3_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH1_S  24
+
+/** DMA2D_IN_POP_CH1_REG register
+ *  Configures the rx fifo of channel 0
+ */
+#define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618)
+/** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH1    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH1_M  (DMA2D_INFIFO_RDATA_CH1_V << DMA2D_INFIFO_RDATA_CH1_S)
+#define DMA2D_INFIFO_RDATA_CH1_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH1_S  0
+/** DMA2D_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH1    (BIT(11))
+#define DMA2D_INFIFO_POP_CH1_M  (DMA2D_INFIFO_POP_CH1_V << DMA2D_INFIFO_POP_CH1_S)
+#define DMA2D_INFIFO_POP_CH1_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH1_S  11
+
+/** DMA2D_IN_LINK_CONF_CH1_REG register
+ *  Configures the rx descriptor operations of channel 0
+ */
+#define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c)
+/** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1;
+ *  Configure the value of the owner field written back to the inlink descriptor.
+ *  1: Write back 1. 0: Write back 0.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH1    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH1_M  (DMA2D_INLINK_AUTO_RET_CH1_V << DMA2D_INLINK_AUTO_RET_CH1_S)
+#define DMA2D_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH1_S  20
+/** DMA2D_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH1    (BIT(21))
+#define DMA2D_INLINK_STOP_CH1_M  (DMA2D_INLINK_STOP_CH1_V << DMA2D_INLINK_STOP_CH1_S)
+#define DMA2D_INLINK_STOP_CH1_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH1_S  21
+/** DMA2D_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH1    (BIT(22))
+#define DMA2D_INLINK_START_CH1_M  (DMA2D_INLINK_START_CH1_V << DMA2D_INLINK_START_CH1_S)
+#define DMA2D_INLINK_START_CH1_V  0x00000001U
+#define DMA2D_INLINK_START_CH1_S  22
+/** DMA2D_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH1    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH1_M  (DMA2D_INLINK_RESTART_CH1_V << DMA2D_INLINK_RESTART_CH1_S)
+#define DMA2D_INLINK_RESTART_CH1_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH1_S  23
+/** DMA2D_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH1    (BIT(24))
+#define DMA2D_INLINK_PARK_CH1_M  (DMA2D_INLINK_PARK_CH1_V << DMA2D_INLINK_PARK_CH1_S)
+#define DMA2D_INLINK_PARK_CH1_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH1_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH1_REG register
+ *  Configures the rx descriptor address of channel 0
+ */
+#define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620)
+/** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH1_M  (DMA2D_INLINK_ADDR_CH1_V << DMA2D_INLINK_ADDR_CH1_S)
+#define DMA2D_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH1_S  0
+
+/** DMA2D_IN_STATE_CH1_REG register
+ *  Represents the working status of the rx descriptor of channel 0
+ */
+#define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624)
+/** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH1_M  (DMA2D_INLINK_DSCR_ADDR_CH1_V << DMA2D_INLINK_DSCR_ADDR_CH1_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH1_S  0
+/** DMA2D_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH1    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH1_M  (DMA2D_IN_DSCR_STATE_CH1_V << DMA2D_IN_DSCR_STATE_CH1_S)
+#define DMA2D_IN_DSCR_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH1_S  18
+/** DMA2D_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH1    0x00000007U
+#define DMA2D_IN_STATE_CH1_M  (DMA2D_IN_STATE_CH1_V << DMA2D_IN_STATE_CH1_S)
+#define DMA2D_IN_STATE_CH1_V  0x00000007U
+#define DMA2D_IN_STATE_CH1_S  20
+/** DMA2D_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH1    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH1_M  (DMA2D_IN_RESET_AVAIL_CH1_V << DMA2D_IN_RESET_AVAIL_CH1_S)
+#define DMA2D_IN_RESET_AVAIL_CH1_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH1_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_IN_DSCR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630)
+/** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH1_M  (DMA2D_INLINK_DSCR_CH1_V << DMA2D_INLINK_DSCR_CH1_S)
+#define DMA2D_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH1_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634)
+/** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH1_M  (DMA2D_INLINK_DSCR_BF0_CH1_V << DMA2D_INLINK_DSCR_BF0_CH1_S)
+#define DMA2D_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH1_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638)
+/** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH1_M  (DMA2D_INLINK_DSCR_BF1_CH1_V << DMA2D_INLINK_DSCR_BF1_CH1_S)
+#define DMA2D_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH1_S  0
+
+/** DMA2D_IN_PERI_SEL_CH1_REG register
+ *  Configures the rx peripheral of channel 0
+ */
+#define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c)
+/** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH1    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH1_M  (DMA2D_IN_PERI_SEL_CH1_V << DMA2D_IN_PERI_SEL_CH1_S)
+#define DMA2D_IN_PERI_SEL_CH1_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH1_S  0
+
+/** DMA2D_IN_ARB_CH1_REG register
+ *  Configures the rx arbiter of channel 0
+ */
+#define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_M  (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH1    (BIT(4))
+#define DMA2D_IN_ARB_PRIORITY_CH1_M  (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S)
+#define DMA2D_IN_ARB_PRIORITY_CH1_V  0x00000001U
+#define DMA2D_IN_ARB_PRIORITY_CH1_S  4
+
+/** DMA2D_IN_RO_STATUS_CH1_REG register
+ *  Represents the status of the rx reorder module of channel 0
+ */
+#define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644)
+/** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH1    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH1_M  (DMA2D_INFIFO_RO_CNT_CH1_V << DMA2D_INFIFO_RO_CNT_CH1_S)
+#define DMA2D_INFIFO_RO_CNT_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH1_S  0
+/** DMA2D_IN_RO_WR_STATE_CH1 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH1    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH1_M  (DMA2D_IN_RO_WR_STATE_CH1_V << DMA2D_IN_RO_WR_STATE_CH1_S)
+#define DMA2D_IN_RO_WR_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH1_S  5
+/** DMA2D_IN_RO_RD_STATE_CH1 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH1    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH1_M  (DMA2D_IN_RO_RD_STATE_CH1_V << DMA2D_IN_RO_RD_STATE_CH1_S)
+#define DMA2D_IN_RO_RD_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH1_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH1 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH1    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH1_M  (DMA2D_IN_PIXEL_BYTE_CH1_V << DMA2D_IN_PIXEL_BYTE_CH1_S)
+#define DMA2D_IN_PIXEL_BYTE_CH1_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH1_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH1 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_M  (DMA2D_IN_BURST_BLOCK_NUM_CH1_V << DMA2D_IN_BURST_BLOCK_NUM_CH1_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_S  13
+
+/** DMA2D_IN_ETM_CONF_CH1_REG register
+ *  Configures the rx etm of channel 0
+ */
+#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x648)
+/** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH1    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH1_M  (DMA2D_IN_ETM_EN_CH1_V << DMA2D_IN_ETM_EN_CH1_S)
+#define DMA2D_IN_ETM_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH1_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH1    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH1_M  (DMA2D_IN_ETM_LOOP_EN_CH1_V << DMA2D_IN_ETM_LOOP_EN_CH1_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH1_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH1    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_M  (DMA2D_IN_DSCR_TASK_MAK_CH1_V << DMA2D_IN_DSCR_TASK_MAK_CH1_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_S  2
+
+/** DMA2D_AXI_ERR_REG register
+ *  Represents the status of th axi bus
+ */
+#define DMA2D_AXI_ERR_REG (DR_REG_DMA2D_BASE + 0xa00)
+/** DMA2D_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0;
+ *  AXI read id err cnt
+ */
+#define DMA2D_RID_ERR_CNT    0x0000000FU
+#define DMA2D_RID_ERR_CNT_M  (DMA2D_RID_ERR_CNT_V << DMA2D_RID_ERR_CNT_S)
+#define DMA2D_RID_ERR_CNT_V  0x0000000FU
+#define DMA2D_RID_ERR_CNT_S  0
+/** DMA2D_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0;
+ *  AXI read resp err cnt
+ */
+#define DMA2D_RRESP_ERR_CNT    0x0000000FU
+#define DMA2D_RRESP_ERR_CNT_M  (DMA2D_RRESP_ERR_CNT_V << DMA2D_RRESP_ERR_CNT_S)
+#define DMA2D_RRESP_ERR_CNT_V  0x0000000FU
+#define DMA2D_RRESP_ERR_CNT_S  4
+/** DMA2D_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0;
+ *  AXI write resp err cnt
+ */
+#define DMA2D_WRESP_ERR_CNT    0x0000000FU
+#define DMA2D_WRESP_ERR_CNT_M  (DMA2D_WRESP_ERR_CNT_V << DMA2D_WRESP_ERR_CNT_S)
+#define DMA2D_WRESP_ERR_CNT_V  0x0000000FU
+#define DMA2D_WRESP_ERR_CNT_S  8
+/** DMA2D_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0;
+ *  AXI read cmd fifo remain cmd count
+ */
+#define DMA2D_RD_FIFO_CNT    0x00000007U
+#define DMA2D_RD_FIFO_CNT_M  (DMA2D_RD_FIFO_CNT_V << DMA2D_RD_FIFO_CNT_S)
+#define DMA2D_RD_FIFO_CNT_V  0x00000007U
+#define DMA2D_RD_FIFO_CNT_S  12
+/** DMA2D_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0;
+ *  AXI read backup cmd fifo remain cmd count
+ */
+#define DMA2D_RD_BAK_FIFO_CNT    0x0000000FU
+#define DMA2D_RD_BAK_FIFO_CNT_M  (DMA2D_RD_BAK_FIFO_CNT_V << DMA2D_RD_BAK_FIFO_CNT_S)
+#define DMA2D_RD_BAK_FIFO_CNT_V  0x0000000FU
+#define DMA2D_RD_BAK_FIFO_CNT_S  15
+/** DMA2D_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0;
+ *  AXI write cmd fifo remain cmd count
+ */
+#define DMA2D_WR_FIFO_CNT    0x00000007U
+#define DMA2D_WR_FIFO_CNT_M  (DMA2D_WR_FIFO_CNT_V << DMA2D_WR_FIFO_CNT_S)
+#define DMA2D_WR_FIFO_CNT_V  0x00000007U
+#define DMA2D_WR_FIFO_CNT_S  19
+/** DMA2D_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0;
+ *  AXI write backup cmd fifo remain cmd count
+ */
+#define DMA2D_WR_BAK_FIFO_CNT    0x0000000FU
+#define DMA2D_WR_BAK_FIFO_CNT_M  (DMA2D_WR_BAK_FIFO_CNT_V << DMA2D_WR_BAK_FIFO_CNT_S)
+#define DMA2D_WR_BAK_FIFO_CNT_V  0x0000000FU
+#define DMA2D_WR_BAK_FIFO_CNT_S  22
+
+/** DMA2D_RST_CONF_REG register
+ *  Configures the reset of axi
+ */
+#define DMA2D_RST_CONF_REG (DR_REG_DMA2D_BASE + 0xa04)
+/** DMA2D_AXIM_RD_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+ */
+#define DMA2D_AXIM_RD_RST    (BIT(0))
+#define DMA2D_AXIM_RD_RST_M  (DMA2D_AXIM_RD_RST_V << DMA2D_AXIM_RD_RST_S)
+#define DMA2D_AXIM_RD_RST_V  0x00000001U
+#define DMA2D_AXIM_RD_RST_S  0
+/** DMA2D_AXIM_WR_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+ */
+#define DMA2D_AXIM_WR_RST    (BIT(1))
+#define DMA2D_AXIM_WR_RST_M  (DMA2D_AXIM_WR_RST_V << DMA2D_AXIM_WR_RST_S)
+#define DMA2D_AXIM_WR_RST_V  0x00000001U
+#define DMA2D_AXIM_WR_RST_S  1
+/** DMA2D_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define DMA2D_CLK_EN    (BIT(2))
+#define DMA2D_CLK_EN_M  (DMA2D_CLK_EN_V << DMA2D_CLK_EN_S)
+#define DMA2D_CLK_EN_V  0x00000001U
+#define DMA2D_CLK_EN_S  2
+
+/** DMA2D_INTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define DMA2D_INTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa08)
+/** DMA2D_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_M  (DMA2D_ACCESS_INTR_MEM_START_ADDR_V << DMA2D_ACCESS_INTR_MEM_START_ADDR_S)
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** DMA2D_INTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space.
+ */
+#define DMA2D_INTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa0c)
+/** DMA2D_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_M  (DMA2D_ACCESS_INTR_MEM_END_ADDR_V << DMA2D_ACCESS_INTR_MEM_END_ADDR_S)
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** DMA2D_EXTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define DMA2D_EXTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa10)
+/** DMA2D_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_M  (DMA2D_ACCESS_EXTR_MEM_START_ADDR_V << DMA2D_ACCESS_EXTR_MEM_START_ADDR_S)
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_S  0
+
+/** DMA2D_EXTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space.
+ */
+#define DMA2D_EXTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa14)
+/** DMA2D_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_M  (DMA2D_ACCESS_EXTR_MEM_END_ADDR_V << DMA2D_ACCESS_EXTR_MEM_END_ADDR_S)
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_S  0
+
+/** DMA2D_OUT_ARB_CONFIG_REG register
+ *  Configures the tx arbiter
+ */
+#define DMA2D_OUT_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa18)
+/** DMA2D_OUT_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define DMA2D_OUT_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_M  (DMA2D_OUT_ARB_TIMEOUT_NUM_V << DMA2D_OUT_ARB_TIMEOUT_NUM_S)
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_S  0
+/** DMA2D_OUT_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_WEIGHT_EN    (BIT(16))
+#define DMA2D_OUT_WEIGHT_EN_M  (DMA2D_OUT_WEIGHT_EN_V << DMA2D_OUT_WEIGHT_EN_S)
+#define DMA2D_OUT_WEIGHT_EN_V  0x00000001U
+#define DMA2D_OUT_WEIGHT_EN_S  16
+
+/** DMA2D_IN_ARB_CONFIG_REG register
+ *  Configures the rx arbiter
+ */
+#define DMA2D_IN_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa1c)
+/** DMA2D_IN_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define DMA2D_IN_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define DMA2D_IN_ARB_TIMEOUT_NUM_M  (DMA2D_IN_ARB_TIMEOUT_NUM_V << DMA2D_IN_ARB_TIMEOUT_NUM_S)
+#define DMA2D_IN_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define DMA2D_IN_ARB_TIMEOUT_NUM_S  0
+/** DMA2D_IN_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_WEIGHT_EN    (BIT(16))
+#define DMA2D_IN_WEIGHT_EN_M  (DMA2D_IN_WEIGHT_EN_V << DMA2D_IN_WEIGHT_EN_S)
+#define DMA2D_IN_WEIGHT_EN_V  0x00000001U
+#define DMA2D_IN_WEIGHT_EN_S  16
+
+/** DMA2D_RDN_RESULT_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_RESULT_REG (DR_REG_DMA2D_BASE + 0xa20)
+/** DMA2D_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define DMA2D_RDN_ENA    (BIT(0))
+#define DMA2D_RDN_ENA_M  (DMA2D_RDN_ENA_V << DMA2D_RDN_ENA_S)
+#define DMA2D_RDN_ENA_V  0x00000001U
+#define DMA2D_RDN_ENA_S  0
+/** DMA2D_RDN_RESULT : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define DMA2D_RDN_RESULT    (BIT(1))
+#define DMA2D_RDN_RESULT_M  (DMA2D_RDN_RESULT_V << DMA2D_RDN_RESULT_S)
+#define DMA2D_RDN_RESULT_V  0x00000001U
+#define DMA2D_RDN_RESULT_S  1
+
+/** DMA2D_RDN_ECO_HIGH_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_ECO_HIGH_REG (DR_REG_DMA2D_BASE + 0xa24)
+/** DMA2D_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_RDN_ECO_HIGH    0xFFFFFFFFU
+#define DMA2D_RDN_ECO_HIGH_M  (DMA2D_RDN_ECO_HIGH_V << DMA2D_RDN_ECO_HIGH_S)
+#define DMA2D_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define DMA2D_RDN_ECO_HIGH_S  0
+
+/** DMA2D_RDN_ECO_LOW_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_ECO_LOW_REG (DR_REG_DMA2D_BASE + 0xa28)
+/** DMA2D_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_RDN_ECO_LOW    0xFFFFFFFFU
+#define DMA2D_RDN_ECO_LOW_M  (DMA2D_RDN_ECO_LOW_V << DMA2D_RDN_ECO_LOW_S)
+#define DMA2D_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define DMA2D_RDN_ECO_LOW_S  0
+
+/** DMA2D_DATE_REG register
+ *  register version.
+ */
+#define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c)
+/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 36716816;
+ *  register version.
+ */
+#define DMA2D_DATE    0xFFFFFFFFU
+#define DMA2D_DATE_M  (DMA2D_DATE_V << DMA2D_DATE_S)
+#define DMA2D_DATE_V  0xFFFFFFFFU
+#define DMA2D_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h
new file mode 100644
index 0000000000..30fef532db
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h
@@ -0,0 +1,1827 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13427
+
+/** Group: out */
+/** Type of out_conf0_chn register
+ *  Configures the tx direction of channel 0
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_chn : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_chn:1;
+        /** out_eof_mode_chn : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_chn:1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_chn:1;
+        /** out_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_chn:1;
+        /** out_check_owner_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn:1;
+        /** out_loop_test_chn : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_chn:1;
+        /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_chn:3;
+        /** out_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0;
+         *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+         *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+         *  descriptor
+         */
+        uint32_t out_macro_block_size_chn:2;
+        /** out_dscr_port_en_chn : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to 1 to obtain descriptor from IP port
+         */
+        uint32_t out_dscr_port_en_chn:1;
+        /** out_page_bound_en_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_chn:1;
+        uint32_t reserved_13:3;
+        /** out_reorder_en_chn : R/W; bitpos: [16]; default: 0;
+         *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t out_reorder_en_chn:1;
+        uint32_t reserved_17:7;
+        /** out_rst_chn : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_chn:1;
+        /** out_cmd_disable_chn : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_chn:1;
+        /** out_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} dma2d_out_conf0_chn_reg_t;
+
+/** Type of out_int_raw_chn register
+ *  Raw interrupt status of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_chn_int_raw:1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_chn_int_raw:1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_chn_int_raw:1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_chn_int_raw:1;
+        /** outfifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_raw:1;
+        /** outfifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_chn_int_raw:1;
+        /** outfifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_raw:1;
+        /** outfifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_chn_int_raw:1;
+        /** outfifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_raw:1;
+        /** outfifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l3_chn_int_raw:1;
+        /** outfifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_raw:1;
+        /** outfifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+         */
+        uint32_t outfifo_ro_udf_chn_int_raw:1;
+        /** out_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_raw_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena:1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena:1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena:1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena:1;
+        /** outfifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_ena:1;
+        /** outfifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_ena:1;
+        /** outfifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_ena:1;
+        /** outfifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_ena:1;
+        /** outfifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_ena:1;
+        /** outfifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_ena:1;
+        /** outfifo_ro_ovf_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_ena:1;
+        /** outfifo_ro_udf_chn_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_ena:1;
+        /** out_dscr_task_ovf_chn_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_ena_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt status of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st:1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st:1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st:1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st:1;
+        /** outfifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_st:1;
+        /** outfifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_st:1;
+        /** outfifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_st:1;
+        /** outfifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_st:1;
+        /** outfifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_st:1;
+        /** outfifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_st:1;
+        /** outfifo_ro_ovf_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_st:1;
+        /** outfifo_ro_udf_chn_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_st:1;
+        /** out_dscr_task_ovf_chn_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_st_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr:1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr:1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr:1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr:1;
+        /** outfifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_clr:1;
+        /** outfifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_clr:1;
+        /** outfifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_clr:1;
+        /** outfifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_clr:1;
+        /** outfifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_clr:1;
+        /** outfifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_clr:1;
+        /** outfifo_ro_ovf_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_clr:1;
+        /** outfifo_ro_udf_chn_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_clr:1;
+        /** out_dscr_task_ovf_chn_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_clr_chn_reg_t;
+
+/** Type of outfifo_status_chn register
+ *  Represents the status of the tx fifo of channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l2_chn:1;
+        /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l2_chn:1;
+        /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l2_chn:4;
+        uint32_t reserved_6:1;
+        /** out_remain_under_1b_chn : RO; bitpos: [7]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn:1;
+        /** out_remain_under_2b_chn : RO; bitpos: [8]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn:1;
+        /** out_remain_under_3b_chn : RO; bitpos: [9]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn:1;
+        /** out_remain_under_4b_chn : RO; bitpos: [10]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn:1;
+        /** out_remain_under_5b_chn : RO; bitpos: [11]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_5b_chn:1;
+        /** out_remain_under_6b_chn : RO; bitpos: [12]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_6b_chn:1;
+        /** out_remain_under_7b_chn : RO; bitpos: [13]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_7b_chn:1;
+        /** out_remain_under_8b_chn : RO; bitpos: [14]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_8b_chn:1;
+        /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l1_chn:1;
+        /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l1_chn:1;
+        /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l1_chn:5;
+        /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l3_chn:1;
+        /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l3_chn:1;
+        /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l3_chn:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dma2d_outfifo_status_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Configures the tx fifo of channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_chn:10;
+        /** outfifo_push_chn : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_chn:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dma2d_out_push_chn_reg_t;
+
+/** Type of out_link_conf_chn register
+ *  Configures the tx descriptor operations of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_chn : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn:1;
+        /** outlink_start_chn : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn:1;
+        /** outlink_restart_chn : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn:1;
+        /** outlink_park_chn : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dma2d_out_link_conf_chn_reg_t;
+
+/** Type of out_link_addr_chn register
+ *  Configures the tx descriptor address of channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_link_addr_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn:18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_chn:2;
+        /** out_state_chn : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_chn:4;
+        /** out_reset_avail_chn : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dma2d_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_bf1_chn_reg_t;
+
+/** Type of out_peri_sel_chn register
+ *  Configures the tx peripheral of channel 0
+ */
+typedef union {
+    struct {
+        /** out_peri_sel_chn : R/W; bitpos: [2:0]; default: 7;
+         *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+         *  display-1     2: display-2     3: display-3      7: no choose
+         */
+        uint32_t out_peri_sel_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_out_peri_sel_chn_reg_t;
+
+/** Type of out_arb_chn register
+ *  Configures the tx arbiter of channel 0
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_chn:4;
+        /** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t out_arb_priority_chn:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_out_arb_chn_reg_t;
+
+/** Type of out_ro_status_chn register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_ro_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in color convert Tx FIFO for
+         *  channel 0.
+         */
+        uint32_t outfifo_ro_cnt_chn:6;
+        /** out_ro_wr_state_chn : RO; bitpos: [7:6]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t out_ro_wr_state_chn:2;
+        /** out_ro_rd_state_chn : RO; bitpos: [9:8]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t out_ro_rd_state_chn:2;
+        /** out_pixel_byte_chn : RO; bitpos: [13:10]; default: 0;
+         *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t out_pixel_byte_chn:4;
+        /** out_burst_block_num_chn : RO; bitpos: [17:14]; default: 0;
+         *  the number of macro blocks contained in a burst of data at TX channel
+         */
+        uint32_t out_burst_block_num_chn:4;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dma2d_out_ro_status_chn_reg_t;
+
+/** Type of out_ro_pd_conf_chn register
+ *  Configures the tx reorder memory of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** out_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0;
+         *  dma reorder ram power down
+         */
+        uint32_t out_ro_ram_force_pd_chn:1;
+        /** out_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1;
+         *  dma reorder ram power up
+         */
+        uint32_t out_ro_ram_force_pu_chn:1;
+        /** out_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t out_ro_ram_clk_fo_chn:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dma2d_out_ro_pd_conf_chn_reg_t;
+
+/** Type of out_color_convert_chn register
+ *  Configures the tx color convert of channel 0
+ */
+typedef union {
+    struct {
+        /** out_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+         *  YUV444 to YUV422     2: output directly
+         */
+        uint32_t out_color_output_sel_chn:2;
+        /** out_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Enable generic color convert module between color input & color output, need to
+         *  configure parameter.
+         */
+        uint32_t out_color_3b_proc_en_chn:1;
+        /** out_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7;
+         *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+         *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+         *  disable color space convert
+         */
+        uint32_t out_color_input_sel_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_out_color_convert_chn_reg_t;
+
+/** Type of out_scramble_chn register
+ *  Configures the tx scramble of channel 0
+ */
+typedef union {
+    struct {
+        /** out_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0;
+         *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+         *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t out_scramble_sel_pre_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_out_scramble_chn_reg_t;
+
+/** Type of out_etm_conf_chn register
+ *  Configures the tx etm of channel 0
+ */
+typedef union {
+    struct {
+        /** out_etm_en_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the enable of the etm function, 1 is enable.
+         */
+        uint32_t out_etm_en_chn:1;
+        /** out_etm_loop_en_chn : R/W; bitpos: [1]; default: 0;
+         *  Configures the enable of the descriptors loop etm function, 1 is enable.
+         */
+        uint32_t out_etm_loop_en_chn:1;
+        /** out_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1;
+         *  Configures the maximum number of cacheable descriptors.
+         */
+        uint32_t out_dscr_task_mak_chn:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dma2d_out_etm_conf_chn_reg_t;
+
+/** Type of out_dscr_port_blk_chn register
+ *  Configures the tx block size in dscr port mode
+ */
+typedef union {
+    struct {
+        /** out_dscr_port_blk_h_chn : R/W; bitpos: [13:0]; default: 18;
+         *  Set the horizontal width of tx block size in dscr port mode
+         */
+        uint32_t out_dscr_port_blk_h_chn:14;
+        /** out_dscr_port_blk_v_chn : R/W; bitpos: [27:14]; default: 18;
+         *  Set the vertical height of tx block size in dscr port mode
+         */
+        uint32_t out_dscr_port_blk_v_chn:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_dscr_port_blk_chn_reg_t;
+
+
+/** Group: in */
+/** Type of in_conf0_chn register
+ *  Configures the rx direction of channel 0
+ */
+typedef union {
+    struct {
+        /** in_mem_trans_en_chn : R/W; bitpos: [0]; default: 0;
+         *  enable memory trans of the same channel
+         */
+        uint32_t in_mem_trans_en_chn:1;
+        uint32_t reserved_1:1;
+        /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_chn:1;
+        /** in_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_chn:1;
+        /** in_check_owner_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn:1;
+        /** in_loop_test_chn : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn:1;
+        /** in_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_chn:3;
+        /** in_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0;
+         *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+         *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+         *  descriptor
+         */
+        uint32_t in_macro_block_size_chn:2;
+        /** in_dscr_port_en_chn : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to 1 to obtain descriptor from IP port
+         */
+        uint32_t in_dscr_port_en_chn:1;
+        /** in_page_bound_en_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_chn:1;
+        uint32_t reserved_13:3;
+        /** in_reorder_en_chn : R/W; bitpos: [16]; default: 0;
+         *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t in_reorder_en_chn:1;
+        uint32_t reserved_17:7;
+        /** in_rst_chn : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_chn:1;
+        /** in_cmd_disable_chn : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_chn:1;
+        /** in_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} dma2d_in_conf0_chn_reg_t;
+
+/** Type of in_int_raw_chn register
+ *  Raw interrupt status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw:1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw:1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_chn_int_raw:1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw:1;
+        /** infifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_chn_int_raw:1;
+        /** infifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_chn_int_raw:1;
+        /** infifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_chn_int_raw:1;
+        /** infifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_chn_int_raw:1;
+        /** infifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l3_chn_int_raw:1;
+        /** infifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l3_chn_int_raw:1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_chn_int_raw:1;
+        /** infifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+         */
+        uint32_t infifo_ro_ovf_chn_int_raw:1;
+        /** infifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+         */
+        uint32_t infifo_ro_udf_chn_int_raw:1;
+        /** in_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_raw_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena:1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena:1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena:1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena:1;
+        /** infifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_ena:1;
+        /** infifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_ena:1;
+        /** infifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_ena:1;
+        /** infifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_ena:1;
+        /** infifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_ena:1;
+        /** infifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_ena:1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena:1;
+        /** infifo_ro_ovf_chn_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_ena:1;
+        /** infifo_ro_udf_chn_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_ena:1;
+        /** in_dscr_task_ovf_chn_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_ena_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st:1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st:1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st:1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st:1;
+        /** infifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_st:1;
+        /** infifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_st:1;
+        /** infifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_st:1;
+        /** infifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_st:1;
+        /** infifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_st:1;
+        /** infifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_st:1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st:1;
+        /** infifo_ro_ovf_chn_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_st:1;
+        /** infifo_ro_udf_chn_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_st:1;
+        /** in_dscr_task_ovf_chn_int_st : RO; bitpos: [13]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_st_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr:1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr:1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr:1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr:1;
+        /** infifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_clr:1;
+        /** infifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_clr:1;
+        /** infifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_clr:1;
+        /** infifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_clr:1;
+        /** infifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_clr:1;
+        /** infifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_clr:1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr:1;
+        /** infifo_ro_ovf_chn_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_clr:1;
+        /** infifo_ro_udf_chn_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_clr:1;
+        /** in_dscr_task_ovf_chn_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_clr_chn_reg_t;
+
+/** Type of infifo_status_chn register
+ *  Represents the status of the rx fifo of channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_chn:1;
+        /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_chn:1;
+        /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_chn:4;
+        uint32_t reserved_6:1;
+        /** in_remain_under_1b_chn : RO; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn:1;
+        /** in_remain_under_2b_chn : RO; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn:1;
+        /** in_remain_under_3b_chn : RO; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn:1;
+        /** in_remain_under_4b_chn : RO; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn:1;
+        /** in_remain_under_5b_chn : RO; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_5b_chn:1;
+        /** in_remain_under_6b_chn : RO; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_6b_chn:1;
+        /** in_remain_under_7b_chn : RO; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_7b_chn:1;
+        /** in_remain_under_8b_chn : RO; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_8b_chn:1;
+        /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t infifo_full_l1_chn:1;
+        /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t infifo_empty_l1_chn:1;
+        /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t infifo_cnt_l1_chn:5;
+        /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t infifo_full_l3_chn:1;
+        /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t infifo_empty_l3_chn:1;
+        /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t infifo_cnt_l3_chn:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dma2d_infifo_status_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Configures the rx fifo of channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_chn:11;
+        /** infifo_pop_chn : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_chn:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dma2d_in_pop_chn_reg_t;
+
+/** Type of in_link_conf_chn register
+ *  Configures the rx descriptor operations of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1;
+         *  Configure the value of the owner field written back to the inlink descriptor.
+         *  1: Write back 1. 0: Write back 0.
+         */
+        uint32_t inlink_auto_ret_chn:1;
+        /** inlink_stop_chn : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn:1;
+        /** inlink_start_chn : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn:1;
+        /** inlink_restart_chn : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn:1;
+        /** inlink_park_chn : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dma2d_in_link_conf_chn_reg_t;
+
+/** Type of in_link_addr_chn register
+ *  Configures the rx descriptor address of channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_link_addr_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Represents the working status of the rx descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn:18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn:2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn:3;
+        /** in_reset_avail_chn : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_chn:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dma2d_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_bf1_chn_reg_t;
+
+/** Type of in_peri_sel_chn register
+ *  Configures the rx peripheral of channel 0
+ */
+typedef union {
+    struct {
+        /** in_peri_sel_chn : R/W; bitpos: [2:0]; default: 7;
+         *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+         *  display-1     2: display-2        7: no choose
+         */
+        uint32_t in_peri_sel_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_in_peri_sel_chn_reg_t;
+
+/** Type of in_arb_chn register
+ *  Configures the rx arbiter of channel 0
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_chn:4;
+        /** in_arb_priority_chn : R/W; bitpos: [4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t in_arb_priority_chn:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} dma2d_in_arb_chn_reg_t;
+
+/** Type of in_ro_status_chn register
+ *  Represents the status of the rx reorder module of channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_ro_cnt_chn : RO; bitpos: [4:0]; default: 0;
+         *  The register stores the byte number of the data in color convert Rx FIFO for
+         *  channel 0.
+         */
+        uint32_t infifo_ro_cnt_chn:5;
+        /** in_ro_wr_state_chn : RO; bitpos: [6:5]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t in_ro_wr_state_chn:2;
+        /** in_ro_rd_state_chn : RO; bitpos: [8:7]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t in_ro_rd_state_chn:2;
+        /** in_pixel_byte_chn : RO; bitpos: [12:9]; default: 0;
+         *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t in_pixel_byte_chn:4;
+        /** in_burst_block_num_chn : RO; bitpos: [16:13]; default: 0;
+         *  the number of macro blocks contained in a burst of data at RX channel
+         */
+        uint32_t in_burst_block_num_chn:4;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_in_ro_status_chn_reg_t;
+
+/** Type of in_ro_pd_conf_chn register
+ *  Configures the rx reorder memory of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** in_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0;
+         *  dma reorder ram power down
+         */
+        uint32_t in_ro_ram_force_pd_chn:1;
+        /** in_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1;
+         *  dma reorder ram power up
+         */
+        uint32_t in_ro_ram_force_pu_chn:1;
+        /** in_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t in_ro_ram_clk_fo_chn:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dma2d_in_ro_pd_conf_chn_reg_t;
+
+/** Type of in_color_convert_chn register
+ *  Configures the tx color convert of channel 0
+ */
+typedef union {
+    struct {
+        /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+         *  output directly
+         */
+        uint32_t in_color_output_sel_chn:2;
+        /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Enable generic color convert module between color input & color output, need to
+         *  configure parameter.
+         */
+        uint32_t in_color_3b_proc_en_chn:1;
+        /** in_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7;
+         *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+         *  1: YUV422      2: YUV444/420      7: disable color space convert
+         */
+        uint32_t in_color_input_sel_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_in_color_convert_chn_reg_t;
+
+/** Type of in_scramble_chn register
+ *  Configures the rx scramble of channel 0
+ */
+typedef union {
+    struct {
+        /** in_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0;
+         *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+         *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t in_scramble_sel_pre_chn:3;
+        /** in_scramble_sel_post_chn : R/W; bitpos: [5:3]; default: 0;
+         *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+         *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t in_scramble_sel_post_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_in_scramble_chn_reg_t;
+
+/** Type of in_etm_conf_chn register
+ *  Configures the rx etm of channel 0
+ */
+typedef union {
+    struct {
+        /** in_etm_en_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the enable of the etm function, 1 is enable.
+         */
+        uint32_t in_etm_en_chn:1;
+        /** in_etm_loop_en_chn : R/W; bitpos: [1]; default: 0;
+         *  Configures the enable of the descriptors loop etm function, 1 is enable.
+         */
+        uint32_t in_etm_loop_en_chn:1;
+        /** in_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1;
+         *  Configures the maximum number of cacheable descriptors.
+         */
+        uint32_t in_dscr_task_mak_chn:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dma2d_in_etm_conf_chn_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of axi_err register
+ *  Represents the status of th axi bus
+ */
+typedef union {
+    struct {
+        /** rid_err_cnt : RO; bitpos: [3:0]; default: 0;
+         *  AXI read id err cnt
+         */
+        uint32_t rid_err_cnt:4;
+        /** rresp_err_cnt : RO; bitpos: [7:4]; default: 0;
+         *  AXI read resp err cnt
+         */
+        uint32_t rresp_err_cnt:4;
+        /** wresp_err_cnt : RO; bitpos: [11:8]; default: 0;
+         *  AXI write resp err cnt
+         */
+        uint32_t wresp_err_cnt:4;
+        /** rd_fifo_cnt : RO; bitpos: [14:12]; default: 0;
+         *  AXI read cmd fifo remain cmd count
+         */
+        uint32_t rd_fifo_cnt:3;
+        /** rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0;
+         *  AXI read backup cmd fifo remain cmd count
+         */
+        uint32_t rd_bak_fifo_cnt:4;
+        /** wr_fifo_cnt : RO; bitpos: [21:19]; default: 0;
+         *  AXI write cmd fifo remain cmd count
+         */
+        uint32_t wr_fifo_cnt:3;
+        /** wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0;
+         *  AXI write backup cmd fifo remain cmd count
+         */
+        uint32_t wr_bak_fifo_cnt:4;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} dma2d_axi_err_reg_t;
+
+/** Type of date register
+ *  register version.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36716816;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} dma2d_date_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of rst_conf register
+ *  Configures the reset of axi
+ */
+typedef union {
+    struct {
+        /** axim_rd_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+         */
+        uint32_t axim_rd_rst:1;
+        /** axim_wr_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+         */
+        uint32_t axim_wr_rst:1;
+        /** clk_en : R/W; bitpos: [2]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_rst_conf_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944 (0x30100000);
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr:32;
+    };
+    uint32_t val;
+} dma2d_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103 (0x8FFFFFFF);
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr:32;
+    };
+    uint32_t val;
+} dma2d_intr_mem_end_addr_reg_t;
+
+/** Type of extr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944 (0x30100000);
+         *  The start address of accessible address space.
+         */
+        uint32_t access_extr_mem_start_addr:32;
+    };
+    uint32_t val;
+} dma2d_extr_mem_start_addr_reg_t;
+
+/** Type of extr_mem_end_addr register
+ *  The end address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103 (0x8FFFFFFF);
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_extr_mem_end_addr:32;
+    };
+    uint32_t val;
+} dma2d_extr_mem_end_addr_reg_t;
+
+/** Type of out_arb_config register
+ *  Configures the tx arbiter
+ */
+typedef union {
+    struct {
+        /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t out_arb_timeout_num:16;
+        /** out_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t out_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_out_arb_config_reg_t;
+
+/** Type of in_arb_config register
+ *  Configures the rx arbiter
+ */
+typedef union {
+    struct {
+        /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t in_arb_timeout_num:16;
+        /** in_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t in_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_in_arb_config_reg_t;
+
+/** Type of rdn_result register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dma2d_rdn_result_reg_t;
+
+/** Type of rdn_eco_high register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} dma2d_rdn_eco_high_reg_t;
+
+/** Type of rdn_eco_low register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} dma2d_rdn_eco_low_reg_t;
+
+
+/** Type of in/out_color_param_h/m/l_chn register
+ *  Configures the rx/tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        struct {
+            /** a: R/W; bitpos: [9:0]; default: h:298, m:298, l:298
+             * Set the first parameter of the most/medium/least significant byte of pending 3 bytes
+             */
+            uint32_t a                             :    10;
+            /** b: R/W; bitpos: [20:10]; default: h:0, in_m:1948, l:516
+             * Set the second parameter of the most/medium/least significant byte of pending 3 bytes
+             */
+            uint32_t b                             :    11;
+            uint32_t reserved21                    :    11;
+        };
+        struct {
+            /** c: R/W; bitpos: [41:32]; default: h:409, m:816, l:0
+             * Set the third parameter of the most/medium/least significant byte of pending 3 bytes
+             */
+            uint32_t c                             :    10;
+            /** d: R/W; bitpos: [59:42]; default: h:205238, m:34707, l:191308
+             * Set the fourth parameter of the most/medium/least significant byte of pending 3 bytes
+             */
+            uint32_t d                             :    18;
+            uint32_t reserved60                    :    4;
+        };
+    };
+    uint32_t val[2];
+} dma2d_color_param_reg_t;
+
+typedef struct {
+    volatile dma2d_color_param_reg_t param_h;
+    volatile dma2d_color_param_reg_t param_m;
+    volatile dma2d_color_param_reg_t param_l;
+} dma2d_color_param_group_chn_reg_t;
+
+typedef struct {
+    volatile dma2d_out_conf0_chn_reg_t out_conf0;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status;
+    volatile dma2d_out_push_chn_reg_t out_push;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr;
+    volatile dma2d_out_state_chn_reg_t out_state;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel;
+    volatile dma2d_out_arb_chn_reg_t out_arb;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status;
+    volatile dma2d_out_ro_pd_conf_chn_reg_t out_ro_pd_conf;  /* only exist on channel0 */
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble;
+    volatile dma2d_color_param_group_chn_reg_t out_color_param_group;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk;
+    uint32_t reserved_out[36];
+} dma2d_out_chn_reg_t;
+
+typedef struct {
+    volatile dma2d_in_conf0_chn_reg_t in_conf0;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status;
+    volatile dma2d_in_pop_chn_reg_t in_pop;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr;
+    volatile dma2d_in_state_chn_reg_t in_state;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
+    volatile dma2d_in_arb_chn_reg_t in_arb;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
+    volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf;
+    volatile dma2d_in_color_convert_chn_reg_t in_color_convert;
+    volatile dma2d_in_scramble_chn_reg_t in_scramble;
+    volatile dma2d_color_param_group_chn_reg_t in_color_param_group;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
+    uint32_t reserved_570[36];
+} dma2d_in_ch0_reg_t;
+
+typedef struct {
+    volatile dma2d_in_conf0_chn_reg_t in_conf0;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status;
+    volatile dma2d_in_pop_chn_reg_t in_pop;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr;
+    volatile dma2d_in_state_chn_reg_t in_state;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
+    volatile dma2d_in_arb_chn_reg_t in_arb;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
+    uint32_t reserved_64c[45];
+} dma2d_in_ch1_reg_t;
+
+typedef struct dma2d_dev_t {
+    volatile dma2d_out_chn_reg_t out_channel[3];
+    uint32_t reserved_300[128];
+    volatile dma2d_in_ch0_reg_t in_channel0;
+    volatile dma2d_in_ch1_reg_t in_channel1;
+    uint32_t reserved_700[192];
+    volatile dma2d_axi_err_reg_t axi_err;
+    volatile dma2d_rst_conf_reg_t rst_conf;
+    volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile dma2d_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile dma2d_extr_mem_start_addr_reg_t extr_mem_start_addr;
+    volatile dma2d_extr_mem_end_addr_reg_t extr_mem_end_addr;
+    volatile dma2d_out_arb_config_reg_t out_arb_config;
+    volatile dma2d_in_arb_config_reg_t in_arb_config;
+    volatile dma2d_rdn_result_reg_t rdn_result;
+    volatile dma2d_rdn_eco_high_reg_t rdn_eco_high;
+    volatile dma2d_rdn_eco_low_reg_t rdn_eco_low;
+    volatile dma2d_date_reg_t date;
+} dma2d_dev_t;
+
+extern dma2d_dev_t DMA2D;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dma2d_dev_t) == 0xa30, "Invalid size of dma2d_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_eco5_reg.h
new file mode 100644
index 0000000000..9bb8b75dbb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_eco5_reg.h
@@ -0,0 +1,1576 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_DMA_DATE_REG register
+ *  NA
+ */
+#define TEE_DMA_DATE_REG (DR_REG_TEE_DMA_BASE + 0x0)
+/** TEE_DMA_TEE_DATE : R/W; bitpos: [31:0]; default: 539165460;
+ *  NA
+ */
+#define TEE_DMA_TEE_DATE    0xFFFFFFFFU
+#define TEE_DMA_TEE_DATE_M  (TEE_DMA_TEE_DATE_V << TEE_DMA_TEE_DATE_S)
+#define TEE_DMA_TEE_DATE_V  0xFFFFFFFFU
+#define TEE_DMA_TEE_DATE_S  0
+
+/** TEE_DMA_CLK_EN_REG register
+ *  NA
+ */
+#define TEE_DMA_CLK_EN_REG (DR_REG_TEE_DMA_BASE + 0x4)
+/** TEE_DMA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_DMA_CLK_EN    (BIT(0))
+#define TEE_DMA_CLK_EN_M  (TEE_DMA_CLK_EN_V << TEE_DMA_CLK_EN_S)
+#define TEE_DMA_CLK_EN_V  0x00000001U
+#define TEE_DMA_CLK_EN_S  0
+
+/** TEE_DMA_REGION0_LOW_REG register
+ *  Region0 address low register.
+ */
+#define TEE_DMA_REGION0_LOW_REG (DR_REG_TEE_DMA_BASE + 0x8)
+/** TEE_DMA_REGION0_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region0 address low.
+ */
+#define TEE_DMA_REGION0_LOW    0x000FFFFFU
+#define TEE_DMA_REGION0_LOW_M  (TEE_DMA_REGION0_LOW_V << TEE_DMA_REGION0_LOW_S)
+#define TEE_DMA_REGION0_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION0_LOW_S  12
+
+/** TEE_DMA_REGION0_HIGH_REG register
+ *  Region0 address high register.
+ */
+#define TEE_DMA_REGION0_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xc)
+/** TEE_DMA_REGION0_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region0 address high.
+ */
+#define TEE_DMA_REGION0_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION0_HIGH_M  (TEE_DMA_REGION0_HIGH_V << TEE_DMA_REGION0_HIGH_S)
+#define TEE_DMA_REGION0_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION0_HIGH_S  12
+
+/** TEE_DMA_REGION1_LOW_REG register
+ *  Region1 address low register.
+ */
+#define TEE_DMA_REGION1_LOW_REG (DR_REG_TEE_DMA_BASE + 0x10)
+/** TEE_DMA_REGION1_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region1 address low.
+ */
+#define TEE_DMA_REGION1_LOW    0x000FFFFFU
+#define TEE_DMA_REGION1_LOW_M  (TEE_DMA_REGION1_LOW_V << TEE_DMA_REGION1_LOW_S)
+#define TEE_DMA_REGION1_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION1_LOW_S  12
+
+/** TEE_DMA_REGION1_HIGH_REG register
+ *  Region1 address high register.
+ */
+#define TEE_DMA_REGION1_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x14)
+/** TEE_DMA_REGION1_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region1 address high.
+ */
+#define TEE_DMA_REGION1_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION1_HIGH_M  (TEE_DMA_REGION1_HIGH_V << TEE_DMA_REGION1_HIGH_S)
+#define TEE_DMA_REGION1_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION1_HIGH_S  12
+
+/** TEE_DMA_REGION2_LOW_REG register
+ *  Region2 address low register.
+ */
+#define TEE_DMA_REGION2_LOW_REG (DR_REG_TEE_DMA_BASE + 0x18)
+/** TEE_DMA_REGION2_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region2 address low.
+ */
+#define TEE_DMA_REGION2_LOW    0x000FFFFFU
+#define TEE_DMA_REGION2_LOW_M  (TEE_DMA_REGION2_LOW_V << TEE_DMA_REGION2_LOW_S)
+#define TEE_DMA_REGION2_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION2_LOW_S  12
+
+/** TEE_DMA_REGION2_HIGH_REG register
+ *  Region2 address high register.
+ */
+#define TEE_DMA_REGION2_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x1c)
+/** TEE_DMA_REGION2_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region2 address high.
+ */
+#define TEE_DMA_REGION2_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION2_HIGH_M  (TEE_DMA_REGION2_HIGH_V << TEE_DMA_REGION2_HIGH_S)
+#define TEE_DMA_REGION2_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION2_HIGH_S  12
+
+/** TEE_DMA_REGION3_LOW_REG register
+ *  Region3 address low register.
+ */
+#define TEE_DMA_REGION3_LOW_REG (DR_REG_TEE_DMA_BASE + 0x20)
+/** TEE_DMA_REGION3_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region3 address low.
+ */
+#define TEE_DMA_REGION3_LOW    0x000FFFFFU
+#define TEE_DMA_REGION3_LOW_M  (TEE_DMA_REGION3_LOW_V << TEE_DMA_REGION3_LOW_S)
+#define TEE_DMA_REGION3_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION3_LOW_S  12
+
+/** TEE_DMA_REGION3_HIGH_REG register
+ *  Region3 address high register.
+ */
+#define TEE_DMA_REGION3_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x24)
+/** TEE_DMA_REGION3_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region3 address high.
+ */
+#define TEE_DMA_REGION3_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION3_HIGH_M  (TEE_DMA_REGION3_HIGH_V << TEE_DMA_REGION3_HIGH_S)
+#define TEE_DMA_REGION3_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION3_HIGH_S  12
+
+/** TEE_DMA_REGION4_LOW_REG register
+ *  Region4 address low register.
+ */
+#define TEE_DMA_REGION4_LOW_REG (DR_REG_TEE_DMA_BASE + 0x28)
+/** TEE_DMA_REGION4_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region4 address low.
+ */
+#define TEE_DMA_REGION4_LOW    0x000FFFFFU
+#define TEE_DMA_REGION4_LOW_M  (TEE_DMA_REGION4_LOW_V << TEE_DMA_REGION4_LOW_S)
+#define TEE_DMA_REGION4_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION4_LOW_S  12
+
+/** TEE_DMA_REGION4_HIGH_REG register
+ *  Region4 address high register.
+ */
+#define TEE_DMA_REGION4_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x2c)
+/** TEE_DMA_REGION4_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region4 address high.
+ */
+#define TEE_DMA_REGION4_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION4_HIGH_M  (TEE_DMA_REGION4_HIGH_V << TEE_DMA_REGION4_HIGH_S)
+#define TEE_DMA_REGION4_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION4_HIGH_S  12
+
+/** TEE_DMA_REGION5_LOW_REG register
+ *  Region5 address low register.
+ */
+#define TEE_DMA_REGION5_LOW_REG (DR_REG_TEE_DMA_BASE + 0x30)
+/** TEE_DMA_REGION5_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region5 address low.
+ */
+#define TEE_DMA_REGION5_LOW    0x000FFFFFU
+#define TEE_DMA_REGION5_LOW_M  (TEE_DMA_REGION5_LOW_V << TEE_DMA_REGION5_LOW_S)
+#define TEE_DMA_REGION5_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION5_LOW_S  12
+
+/** TEE_DMA_REGION5_HIGH_REG register
+ *  Region5 address high register.
+ */
+#define TEE_DMA_REGION5_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x34)
+/** TEE_DMA_REGION5_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region5 address high.
+ */
+#define TEE_DMA_REGION5_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION5_HIGH_M  (TEE_DMA_REGION5_HIGH_V << TEE_DMA_REGION5_HIGH_S)
+#define TEE_DMA_REGION5_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION5_HIGH_S  12
+
+/** TEE_DMA_REGION6_LOW_REG register
+ *  Region6 address low register.
+ */
+#define TEE_DMA_REGION6_LOW_REG (DR_REG_TEE_DMA_BASE + 0x38)
+/** TEE_DMA_REGION6_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region6 address low.
+ */
+#define TEE_DMA_REGION6_LOW    0x000FFFFFU
+#define TEE_DMA_REGION6_LOW_M  (TEE_DMA_REGION6_LOW_V << TEE_DMA_REGION6_LOW_S)
+#define TEE_DMA_REGION6_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION6_LOW_S  12
+
+/** TEE_DMA_REGION6_HIGH_REG register
+ *  Region6 address high register.
+ */
+#define TEE_DMA_REGION6_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x3c)
+/** TEE_DMA_REGION6_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region6 address high.
+ */
+#define TEE_DMA_REGION6_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION6_HIGH_M  (TEE_DMA_REGION6_HIGH_V << TEE_DMA_REGION6_HIGH_S)
+#define TEE_DMA_REGION6_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION6_HIGH_S  12
+
+/** TEE_DMA_REGION7_LOW_REG register
+ *  Region7 address low register.
+ */
+#define TEE_DMA_REGION7_LOW_REG (DR_REG_TEE_DMA_BASE + 0x40)
+/** TEE_DMA_REGION7_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region7 address low.
+ */
+#define TEE_DMA_REGION7_LOW    0x000FFFFFU
+#define TEE_DMA_REGION7_LOW_M  (TEE_DMA_REGION7_LOW_V << TEE_DMA_REGION7_LOW_S)
+#define TEE_DMA_REGION7_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION7_LOW_S  12
+
+/** TEE_DMA_REGION7_HIGH_REG register
+ *  Region7 address high register.
+ */
+#define TEE_DMA_REGION7_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x44)
+/** TEE_DMA_REGION7_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region7 address high.
+ */
+#define TEE_DMA_REGION7_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION7_HIGH_M  (TEE_DMA_REGION7_HIGH_V << TEE_DMA_REGION7_HIGH_S)
+#define TEE_DMA_REGION7_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION7_HIGH_S  12
+
+/** TEE_DMA_REGION8_LOW_REG register
+ *  Region8 address low register.
+ */
+#define TEE_DMA_REGION8_LOW_REG (DR_REG_TEE_DMA_BASE + 0x48)
+/** TEE_DMA_REGION8_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region8 address low.
+ */
+#define TEE_DMA_REGION8_LOW    0x000FFFFFU
+#define TEE_DMA_REGION8_LOW_M  (TEE_DMA_REGION8_LOW_V << TEE_DMA_REGION8_LOW_S)
+#define TEE_DMA_REGION8_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION8_LOW_S  12
+
+/** TEE_DMA_REGION8_HIGH_REG register
+ *  Region8 address high register.
+ */
+#define TEE_DMA_REGION8_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x4c)
+/** TEE_DMA_REGION8_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region8 address high.
+ */
+#define TEE_DMA_REGION8_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION8_HIGH_M  (TEE_DMA_REGION8_HIGH_V << TEE_DMA_REGION8_HIGH_S)
+#define TEE_DMA_REGION8_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION8_HIGH_S  12
+
+/** TEE_DMA_REGION9_LOW_REG register
+ *  Region9 address low register.
+ */
+#define TEE_DMA_REGION9_LOW_REG (DR_REG_TEE_DMA_BASE + 0x50)
+/** TEE_DMA_REGION9_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region9 address low.
+ */
+#define TEE_DMA_REGION9_LOW    0x000FFFFFU
+#define TEE_DMA_REGION9_LOW_M  (TEE_DMA_REGION9_LOW_V << TEE_DMA_REGION9_LOW_S)
+#define TEE_DMA_REGION9_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION9_LOW_S  12
+
+/** TEE_DMA_REGION9_HIGH_REG register
+ *  Region9 address high register.
+ */
+#define TEE_DMA_REGION9_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x54)
+/** TEE_DMA_REGION9_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region9 address high.
+ */
+#define TEE_DMA_REGION9_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION9_HIGH_M  (TEE_DMA_REGION9_HIGH_V << TEE_DMA_REGION9_HIGH_S)
+#define TEE_DMA_REGION9_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION9_HIGH_S  12
+
+/** TEE_DMA_REGION10_LOW_REG register
+ *  Region10 address low register.
+ */
+#define TEE_DMA_REGION10_LOW_REG (DR_REG_TEE_DMA_BASE + 0x58)
+/** TEE_DMA_REGION10_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region10 address low.
+ */
+#define TEE_DMA_REGION10_LOW    0x000FFFFFU
+#define TEE_DMA_REGION10_LOW_M  (TEE_DMA_REGION10_LOW_V << TEE_DMA_REGION10_LOW_S)
+#define TEE_DMA_REGION10_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION10_LOW_S  12
+
+/** TEE_DMA_REGION10_HIGH_REG register
+ *  Region10 address high register.
+ */
+#define TEE_DMA_REGION10_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x5c)
+/** TEE_DMA_REGION10_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region10 address high.
+ */
+#define TEE_DMA_REGION10_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION10_HIGH_M  (TEE_DMA_REGION10_HIGH_V << TEE_DMA_REGION10_HIGH_S)
+#define TEE_DMA_REGION10_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION10_HIGH_S  12
+
+/** TEE_DMA_REGION11_LOW_REG register
+ *  Region11 address low register.
+ */
+#define TEE_DMA_REGION11_LOW_REG (DR_REG_TEE_DMA_BASE + 0x60)
+/** TEE_DMA_REGION11_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region11 address low.
+ */
+#define TEE_DMA_REGION11_LOW    0x000FFFFFU
+#define TEE_DMA_REGION11_LOW_M  (TEE_DMA_REGION11_LOW_V << TEE_DMA_REGION11_LOW_S)
+#define TEE_DMA_REGION11_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION11_LOW_S  12
+
+/** TEE_DMA_REGION11_HIGH_REG register
+ *  Region11 address high register.
+ */
+#define TEE_DMA_REGION11_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x64)
+/** TEE_DMA_REGION11_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region11 address high.
+ */
+#define TEE_DMA_REGION11_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION11_HIGH_M  (TEE_DMA_REGION11_HIGH_V << TEE_DMA_REGION11_HIGH_S)
+#define TEE_DMA_REGION11_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION11_HIGH_S  12
+
+/** TEE_DMA_REGION12_LOW_REG register
+ *  Region12 address low register.
+ */
+#define TEE_DMA_REGION12_LOW_REG (DR_REG_TEE_DMA_BASE + 0x68)
+/** TEE_DMA_REGION12_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region12 address low.
+ */
+#define TEE_DMA_REGION12_LOW    0x000FFFFFU
+#define TEE_DMA_REGION12_LOW_M  (TEE_DMA_REGION12_LOW_V << TEE_DMA_REGION12_LOW_S)
+#define TEE_DMA_REGION12_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION12_LOW_S  12
+
+/** TEE_DMA_REGION12_HIGH_REG register
+ *  Region12 address high register.
+ */
+#define TEE_DMA_REGION12_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x6c)
+/** TEE_DMA_REGION12_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region12 address high.
+ */
+#define TEE_DMA_REGION12_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION12_HIGH_M  (TEE_DMA_REGION12_HIGH_V << TEE_DMA_REGION12_HIGH_S)
+#define TEE_DMA_REGION12_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION12_HIGH_S  12
+
+/** TEE_DMA_REGION13_LOW_REG register
+ *  Region13 address low register.
+ */
+#define TEE_DMA_REGION13_LOW_REG (DR_REG_TEE_DMA_BASE + 0x70)
+/** TEE_DMA_REGION13_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region13 address low.
+ */
+#define TEE_DMA_REGION13_LOW    0x000FFFFFU
+#define TEE_DMA_REGION13_LOW_M  (TEE_DMA_REGION13_LOW_V << TEE_DMA_REGION13_LOW_S)
+#define TEE_DMA_REGION13_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION13_LOW_S  12
+
+/** TEE_DMA_REGION13_HIGH_REG register
+ *  Region13 address high register.
+ */
+#define TEE_DMA_REGION13_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x74)
+/** TEE_DMA_REGION13_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region13 address high.
+ */
+#define TEE_DMA_REGION13_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION13_HIGH_M  (TEE_DMA_REGION13_HIGH_V << TEE_DMA_REGION13_HIGH_S)
+#define TEE_DMA_REGION13_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION13_HIGH_S  12
+
+/** TEE_DMA_REGION14_LOW_REG register
+ *  Region14 address low register.
+ */
+#define TEE_DMA_REGION14_LOW_REG (DR_REG_TEE_DMA_BASE + 0x78)
+/** TEE_DMA_REGION14_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region14 address low.
+ */
+#define TEE_DMA_REGION14_LOW    0x000FFFFFU
+#define TEE_DMA_REGION14_LOW_M  (TEE_DMA_REGION14_LOW_V << TEE_DMA_REGION14_LOW_S)
+#define TEE_DMA_REGION14_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION14_LOW_S  12
+
+/** TEE_DMA_REGION14_HIGH_REG register
+ *  Region14 address high register.
+ */
+#define TEE_DMA_REGION14_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x7c)
+/** TEE_DMA_REGION14_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region14 address high.
+ */
+#define TEE_DMA_REGION14_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION14_HIGH_M  (TEE_DMA_REGION14_HIGH_V << TEE_DMA_REGION14_HIGH_S)
+#define TEE_DMA_REGION14_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION14_HIGH_S  12
+
+/** TEE_DMA_REGION15_LOW_REG register
+ *  Region15 address low register.
+ */
+#define TEE_DMA_REGION15_LOW_REG (DR_REG_TEE_DMA_BASE + 0x80)
+/** TEE_DMA_REGION15_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region15 address low.
+ */
+#define TEE_DMA_REGION15_LOW    0x000FFFFFU
+#define TEE_DMA_REGION15_LOW_M  (TEE_DMA_REGION15_LOW_V << TEE_DMA_REGION15_LOW_S)
+#define TEE_DMA_REGION15_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION15_LOW_S  12
+
+/** TEE_DMA_REGION15_HIGH_REG register
+ *  Region15 address high register.
+ */
+#define TEE_DMA_REGION15_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x84)
+/** TEE_DMA_REGION15_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region15 address high.
+ */
+#define TEE_DMA_REGION15_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION15_HIGH_M  (TEE_DMA_REGION15_HIGH_V << TEE_DMA_REGION15_HIGH_S)
+#define TEE_DMA_REGION15_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION15_HIGH_S  12
+
+/** TEE_DMA_REGION16_LOW_REG register
+ *  Region16 address low register.
+ */
+#define TEE_DMA_REGION16_LOW_REG (DR_REG_TEE_DMA_BASE + 0x88)
+/** TEE_DMA_REGION16_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region16 address low.
+ */
+#define TEE_DMA_REGION16_LOW    0x000FFFFFU
+#define TEE_DMA_REGION16_LOW_M  (TEE_DMA_REGION16_LOW_V << TEE_DMA_REGION16_LOW_S)
+#define TEE_DMA_REGION16_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION16_LOW_S  12
+
+/** TEE_DMA_REGION16_HIGH_REG register
+ *  Region16 address high register.
+ */
+#define TEE_DMA_REGION16_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x8c)
+/** TEE_DMA_REGION16_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region16 address high.
+ */
+#define TEE_DMA_REGION16_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION16_HIGH_M  (TEE_DMA_REGION16_HIGH_V << TEE_DMA_REGION16_HIGH_S)
+#define TEE_DMA_REGION16_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION16_HIGH_S  12
+
+/** TEE_DMA_REGION17_LOW_REG register
+ *  Region17 address low register.
+ */
+#define TEE_DMA_REGION17_LOW_REG (DR_REG_TEE_DMA_BASE + 0x90)
+/** TEE_DMA_REGION17_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region17 address low.
+ */
+#define TEE_DMA_REGION17_LOW    0x000FFFFFU
+#define TEE_DMA_REGION17_LOW_M  (TEE_DMA_REGION17_LOW_V << TEE_DMA_REGION17_LOW_S)
+#define TEE_DMA_REGION17_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION17_LOW_S  12
+
+/** TEE_DMA_REGION17_HIGH_REG register
+ *  Region17 address high register.
+ */
+#define TEE_DMA_REGION17_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x94)
+/** TEE_DMA_REGION17_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region17 address high.
+ */
+#define TEE_DMA_REGION17_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION17_HIGH_M  (TEE_DMA_REGION17_HIGH_V << TEE_DMA_REGION17_HIGH_S)
+#define TEE_DMA_REGION17_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION17_HIGH_S  12
+
+/** TEE_DMA_REGION18_LOW_REG register
+ *  Region18 address low register.
+ */
+#define TEE_DMA_REGION18_LOW_REG (DR_REG_TEE_DMA_BASE + 0x98)
+/** TEE_DMA_REGION18_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region18 address low.
+ */
+#define TEE_DMA_REGION18_LOW    0x000FFFFFU
+#define TEE_DMA_REGION18_LOW_M  (TEE_DMA_REGION18_LOW_V << TEE_DMA_REGION18_LOW_S)
+#define TEE_DMA_REGION18_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION18_LOW_S  12
+
+/** TEE_DMA_REGION18_HIGH_REG register
+ *  Region18 address high register.
+ */
+#define TEE_DMA_REGION18_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x9c)
+/** TEE_DMA_REGION18_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region18 address high.
+ */
+#define TEE_DMA_REGION18_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION18_HIGH_M  (TEE_DMA_REGION18_HIGH_V << TEE_DMA_REGION18_HIGH_S)
+#define TEE_DMA_REGION18_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION18_HIGH_S  12
+
+/** TEE_DMA_REGION19_LOW_REG register
+ *  Region19 address low register.
+ */
+#define TEE_DMA_REGION19_LOW_REG (DR_REG_TEE_DMA_BASE + 0xa0)
+/** TEE_DMA_REGION19_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region19 address low.
+ */
+#define TEE_DMA_REGION19_LOW    0x000FFFFFU
+#define TEE_DMA_REGION19_LOW_M  (TEE_DMA_REGION19_LOW_V << TEE_DMA_REGION19_LOW_S)
+#define TEE_DMA_REGION19_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION19_LOW_S  12
+
+/** TEE_DMA_REGION19_HIGH_REG register
+ *  Region19 address high register.
+ */
+#define TEE_DMA_REGION19_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xa4)
+/** TEE_DMA_REGION19_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region19 address high.
+ */
+#define TEE_DMA_REGION19_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION19_HIGH_M  (TEE_DMA_REGION19_HIGH_V << TEE_DMA_REGION19_HIGH_S)
+#define TEE_DMA_REGION19_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION19_HIGH_S  12
+
+/** TEE_DMA_REGION20_LOW_REG register
+ *  Region20 address low register.
+ */
+#define TEE_DMA_REGION20_LOW_REG (DR_REG_TEE_DMA_BASE + 0xa8)
+/** TEE_DMA_REGION20_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region20 address low.
+ */
+#define TEE_DMA_REGION20_LOW    0x000FFFFFU
+#define TEE_DMA_REGION20_LOW_M  (TEE_DMA_REGION20_LOW_V << TEE_DMA_REGION20_LOW_S)
+#define TEE_DMA_REGION20_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION20_LOW_S  12
+
+/** TEE_DMA_REGION20_HIGH_REG register
+ *  Region20 address high register.
+ */
+#define TEE_DMA_REGION20_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xac)
+/** TEE_DMA_REGION20_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region20 address high.
+ */
+#define TEE_DMA_REGION20_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION20_HIGH_M  (TEE_DMA_REGION20_HIGH_V << TEE_DMA_REGION20_HIGH_S)
+#define TEE_DMA_REGION20_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION20_HIGH_S  12
+
+/** TEE_DMA_REGION21_LOW_REG register
+ *  Region21 address low register.
+ */
+#define TEE_DMA_REGION21_LOW_REG (DR_REG_TEE_DMA_BASE + 0xb0)
+/** TEE_DMA_REGION21_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region21 address low.
+ */
+#define TEE_DMA_REGION21_LOW    0x000FFFFFU
+#define TEE_DMA_REGION21_LOW_M  (TEE_DMA_REGION21_LOW_V << TEE_DMA_REGION21_LOW_S)
+#define TEE_DMA_REGION21_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION21_LOW_S  12
+
+/** TEE_DMA_REGION21_HIGH_REG register
+ *  Region21 address high register.
+ */
+#define TEE_DMA_REGION21_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xb4)
+/** TEE_DMA_REGION21_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region21 address high.
+ */
+#define TEE_DMA_REGION21_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION21_HIGH_M  (TEE_DMA_REGION21_HIGH_V << TEE_DMA_REGION21_HIGH_S)
+#define TEE_DMA_REGION21_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION21_HIGH_S  12
+
+/** TEE_DMA_REGION22_LOW_REG register
+ *  Region22 address low register.
+ */
+#define TEE_DMA_REGION22_LOW_REG (DR_REG_TEE_DMA_BASE + 0xb8)
+/** TEE_DMA_REGION22_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region22 address low.
+ */
+#define TEE_DMA_REGION22_LOW    0x000FFFFFU
+#define TEE_DMA_REGION22_LOW_M  (TEE_DMA_REGION22_LOW_V << TEE_DMA_REGION22_LOW_S)
+#define TEE_DMA_REGION22_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION22_LOW_S  12
+
+/** TEE_DMA_REGION22_HIGH_REG register
+ *  Region22 address high register.
+ */
+#define TEE_DMA_REGION22_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xbc)
+/** TEE_DMA_REGION22_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region22 address high.
+ */
+#define TEE_DMA_REGION22_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION22_HIGH_M  (TEE_DMA_REGION22_HIGH_V << TEE_DMA_REGION22_HIGH_S)
+#define TEE_DMA_REGION22_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION22_HIGH_S  12
+
+/** TEE_DMA_REGION23_LOW_REG register
+ *  Region23 address low register.
+ */
+#define TEE_DMA_REGION23_LOW_REG (DR_REG_TEE_DMA_BASE + 0xc0)
+/** TEE_DMA_REGION23_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region23 address low.
+ */
+#define TEE_DMA_REGION23_LOW    0x000FFFFFU
+#define TEE_DMA_REGION23_LOW_M  (TEE_DMA_REGION23_LOW_V << TEE_DMA_REGION23_LOW_S)
+#define TEE_DMA_REGION23_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION23_LOW_S  12
+
+/** TEE_DMA_REGION23_HIGH_REG register
+ *  Region23 address high register.
+ */
+#define TEE_DMA_REGION23_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xc4)
+/** TEE_DMA_REGION23_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region23 address high.
+ */
+#define TEE_DMA_REGION23_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION23_HIGH_M  (TEE_DMA_REGION23_HIGH_V << TEE_DMA_REGION23_HIGH_S)
+#define TEE_DMA_REGION23_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION23_HIGH_S  12
+
+/** TEE_DMA_REGION24_LOW_REG register
+ *  Region24 address low register.
+ */
+#define TEE_DMA_REGION24_LOW_REG (DR_REG_TEE_DMA_BASE + 0xc8)
+/** TEE_DMA_REGION24_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region24 address low.
+ */
+#define TEE_DMA_REGION24_LOW    0x000FFFFFU
+#define TEE_DMA_REGION24_LOW_M  (TEE_DMA_REGION24_LOW_V << TEE_DMA_REGION24_LOW_S)
+#define TEE_DMA_REGION24_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION24_LOW_S  12
+
+/** TEE_DMA_REGION24_HIGH_REG register
+ *  Region24 address high register.
+ */
+#define TEE_DMA_REGION24_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xcc)
+/** TEE_DMA_REGION24_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region24 address high.
+ */
+#define TEE_DMA_REGION24_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION24_HIGH_M  (TEE_DMA_REGION24_HIGH_V << TEE_DMA_REGION24_HIGH_S)
+#define TEE_DMA_REGION24_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION24_HIGH_S  12
+
+/** TEE_DMA_REGION25_LOW_REG register
+ *  Region25 address low register.
+ */
+#define TEE_DMA_REGION25_LOW_REG (DR_REG_TEE_DMA_BASE + 0xd0)
+/** TEE_DMA_REGION25_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region25 address low.
+ */
+#define TEE_DMA_REGION25_LOW    0x000FFFFFU
+#define TEE_DMA_REGION25_LOW_M  (TEE_DMA_REGION25_LOW_V << TEE_DMA_REGION25_LOW_S)
+#define TEE_DMA_REGION25_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION25_LOW_S  12
+
+/** TEE_DMA_REGION25_HIGH_REG register
+ *  Region25 address high register.
+ */
+#define TEE_DMA_REGION25_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xd4)
+/** TEE_DMA_REGION25_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region25 address high.
+ */
+#define TEE_DMA_REGION25_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION25_HIGH_M  (TEE_DMA_REGION25_HIGH_V << TEE_DMA_REGION25_HIGH_S)
+#define TEE_DMA_REGION25_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION25_HIGH_S  12
+
+/** TEE_DMA_REGION26_LOW_REG register
+ *  Region26 address low register.
+ */
+#define TEE_DMA_REGION26_LOW_REG (DR_REG_TEE_DMA_BASE + 0xd8)
+/** TEE_DMA_REGION26_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region26 address low.
+ */
+#define TEE_DMA_REGION26_LOW    0x000FFFFFU
+#define TEE_DMA_REGION26_LOW_M  (TEE_DMA_REGION26_LOW_V << TEE_DMA_REGION26_LOW_S)
+#define TEE_DMA_REGION26_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION26_LOW_S  12
+
+/** TEE_DMA_REGION26_HIGH_REG register
+ *  Region26 address high register.
+ */
+#define TEE_DMA_REGION26_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xdc)
+/** TEE_DMA_REGION26_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region26 address high.
+ */
+#define TEE_DMA_REGION26_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION26_HIGH_M  (TEE_DMA_REGION26_HIGH_V << TEE_DMA_REGION26_HIGH_S)
+#define TEE_DMA_REGION26_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION26_HIGH_S  12
+
+/** TEE_DMA_REGION27_LOW_REG register
+ *  Region27 address low register.
+ */
+#define TEE_DMA_REGION27_LOW_REG (DR_REG_TEE_DMA_BASE + 0xe0)
+/** TEE_DMA_REGION27_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region27 address low.
+ */
+#define TEE_DMA_REGION27_LOW    0x000FFFFFU
+#define TEE_DMA_REGION27_LOW_M  (TEE_DMA_REGION27_LOW_V << TEE_DMA_REGION27_LOW_S)
+#define TEE_DMA_REGION27_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION27_LOW_S  12
+
+/** TEE_DMA_REGION27_HIGH_REG register
+ *  Region27 address high register.
+ */
+#define TEE_DMA_REGION27_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xe4)
+/** TEE_DMA_REGION27_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region27 address high.
+ */
+#define TEE_DMA_REGION27_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION27_HIGH_M  (TEE_DMA_REGION27_HIGH_V << TEE_DMA_REGION27_HIGH_S)
+#define TEE_DMA_REGION27_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION27_HIGH_S  12
+
+/** TEE_DMA_REGION28_LOW_REG register
+ *  Region28 address low register.
+ */
+#define TEE_DMA_REGION28_LOW_REG (DR_REG_TEE_DMA_BASE + 0xe8)
+/** TEE_DMA_REGION28_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region28 address low.
+ */
+#define TEE_DMA_REGION28_LOW    0x000FFFFFU
+#define TEE_DMA_REGION28_LOW_M  (TEE_DMA_REGION28_LOW_V << TEE_DMA_REGION28_LOW_S)
+#define TEE_DMA_REGION28_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION28_LOW_S  12
+
+/** TEE_DMA_REGION28_HIGH_REG register
+ *  Region28 address high register.
+ */
+#define TEE_DMA_REGION28_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xec)
+/** TEE_DMA_REGION28_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region28 address high.
+ */
+#define TEE_DMA_REGION28_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION28_HIGH_M  (TEE_DMA_REGION28_HIGH_V << TEE_DMA_REGION28_HIGH_S)
+#define TEE_DMA_REGION28_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION28_HIGH_S  12
+
+/** TEE_DMA_REGION29_LOW_REG register
+ *  Region29 address low register.
+ */
+#define TEE_DMA_REGION29_LOW_REG (DR_REG_TEE_DMA_BASE + 0xf0)
+/** TEE_DMA_REGION29_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region29 address low.
+ */
+#define TEE_DMA_REGION29_LOW    0x000FFFFFU
+#define TEE_DMA_REGION29_LOW_M  (TEE_DMA_REGION29_LOW_V << TEE_DMA_REGION29_LOW_S)
+#define TEE_DMA_REGION29_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION29_LOW_S  12
+
+/** TEE_DMA_REGION29_HIGH_REG register
+ *  Region29 address high register.
+ */
+#define TEE_DMA_REGION29_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xf4)
+/** TEE_DMA_REGION29_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region29 address high.
+ */
+#define TEE_DMA_REGION29_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION29_HIGH_M  (TEE_DMA_REGION29_HIGH_V << TEE_DMA_REGION29_HIGH_S)
+#define TEE_DMA_REGION29_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION29_HIGH_S  12
+
+/** TEE_DMA_REGION30_LOW_REG register
+ *  Region30 address low register.
+ */
+#define TEE_DMA_REGION30_LOW_REG (DR_REG_TEE_DMA_BASE + 0xf8)
+/** TEE_DMA_REGION30_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region30 address low.
+ */
+#define TEE_DMA_REGION30_LOW    0x000FFFFFU
+#define TEE_DMA_REGION30_LOW_M  (TEE_DMA_REGION30_LOW_V << TEE_DMA_REGION30_LOW_S)
+#define TEE_DMA_REGION30_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION30_LOW_S  12
+
+/** TEE_DMA_REGION30_HIGH_REG register
+ *  Region30 address high register.
+ */
+#define TEE_DMA_REGION30_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xfc)
+/** TEE_DMA_REGION30_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region30 address high.
+ */
+#define TEE_DMA_REGION30_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION30_HIGH_M  (TEE_DMA_REGION30_HIGH_V << TEE_DMA_REGION30_HIGH_S)
+#define TEE_DMA_REGION30_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION30_HIGH_S  12
+
+/** TEE_DMA_REGION31_LOW_REG register
+ *  Region31 address low register.
+ */
+#define TEE_DMA_REGION31_LOW_REG (DR_REG_TEE_DMA_BASE + 0x100)
+/** TEE_DMA_REGION31_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region31 address low.
+ */
+#define TEE_DMA_REGION31_LOW    0x000FFFFFU
+#define TEE_DMA_REGION31_LOW_M  (TEE_DMA_REGION31_LOW_V << TEE_DMA_REGION31_LOW_S)
+#define TEE_DMA_REGION31_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION31_LOW_S  12
+
+/** TEE_DMA_REGION31_HIGH_REG register
+ *  Region31 address high register.
+ */
+#define TEE_DMA_REGION31_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x104)
+/** TEE_DMA_REGION31_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region31 address high.
+ */
+#define TEE_DMA_REGION31_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION31_HIGH_M  (TEE_DMA_REGION31_HIGH_V << TEE_DMA_REGION31_HIGH_S)
+#define TEE_DMA_REGION31_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION31_HIGH_S  12
+
+/** TEE_DMA_GMDA_CH0_R_PMS_REG register
+ *  GDMA ch0 read permission control registers.
+ */
+#define TEE_DMA_GMDA_CH0_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x108)
+/** TEE_DMA_GDMA_CH0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch0 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH0_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH0_R_PMS_M  (TEE_DMA_GDMA_CH0_R_PMS_V << TEE_DMA_GDMA_CH0_R_PMS_S)
+#define TEE_DMA_GDMA_CH0_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH0_R_PMS_S  0
+
+/** TEE_DMA_GMDA_CH0_W_PMS_REG register
+ *  GDMA ch0 write permission control registers.
+ */
+#define TEE_DMA_GMDA_CH0_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x10c)
+/** TEE_DMA_GDMA_CH0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch0 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH0_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH0_W_PMS_M  (TEE_DMA_GDMA_CH0_W_PMS_V << TEE_DMA_GDMA_CH0_W_PMS_S)
+#define TEE_DMA_GDMA_CH0_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH0_W_PMS_S  0
+
+/** TEE_DMA_GMDA_CH1_R_PMS_REG register
+ *  GDMA ch1 read permission control registers.
+ */
+#define TEE_DMA_GMDA_CH1_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x110)
+/** TEE_DMA_GDMA_CH1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch1 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH1_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH1_R_PMS_M  (TEE_DMA_GDMA_CH1_R_PMS_V << TEE_DMA_GDMA_CH1_R_PMS_S)
+#define TEE_DMA_GDMA_CH1_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH1_R_PMS_S  0
+
+/** TEE_DMA_GMDA_CH1_W_PMS_REG register
+ *  GDMA ch1 write permission control registers.
+ */
+#define TEE_DMA_GMDA_CH1_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x114)
+/** TEE_DMA_GDMA_CH1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch1 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH1_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH1_W_PMS_M  (TEE_DMA_GDMA_CH1_W_PMS_V << TEE_DMA_GDMA_CH1_W_PMS_S)
+#define TEE_DMA_GDMA_CH1_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH1_W_PMS_S  0
+
+/** TEE_DMA_GMDA_CH2_R_PMS_REG register
+ *  GDMA ch2 read permission control registers.
+ */
+#define TEE_DMA_GMDA_CH2_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x118)
+/** TEE_DMA_GDMA_CH2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch2 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH2_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH2_R_PMS_M  (TEE_DMA_GDMA_CH2_R_PMS_V << TEE_DMA_GDMA_CH2_R_PMS_S)
+#define TEE_DMA_GDMA_CH2_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH2_R_PMS_S  0
+
+/** TEE_DMA_GMDA_CH2_W_PMS_REG register
+ *  GDMA ch2 write permission control registers.
+ */
+#define TEE_DMA_GMDA_CH2_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x11c)
+/** TEE_DMA_GDMA_CH2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch2 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH2_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH2_W_PMS_M  (TEE_DMA_GDMA_CH2_W_PMS_V << TEE_DMA_GDMA_CH2_W_PMS_S)
+#define TEE_DMA_GDMA_CH2_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH2_W_PMS_S  0
+
+/** TEE_DMA_GMDA_CH3_R_PMS_REG register
+ *  GDMA ch3 read permission control registers.
+ */
+#define TEE_DMA_GMDA_CH3_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x120)
+/** TEE_DMA_GDMA_CH3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch3 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH3_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH3_R_PMS_M  (TEE_DMA_GDMA_CH3_R_PMS_V << TEE_DMA_GDMA_CH3_R_PMS_S)
+#define TEE_DMA_GDMA_CH3_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH3_R_PMS_S  0
+
+/** TEE_DMA_GMDA_CH3_W_PMS_REG register
+ *  GDMA ch3 write permission control registers.
+ */
+#define TEE_DMA_GMDA_CH3_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x124)
+/** TEE_DMA_GDMA_CH3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch3 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH3_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH3_W_PMS_M  (TEE_DMA_GDMA_CH3_W_PMS_V << TEE_DMA_GDMA_CH3_W_PMS_S)
+#define TEE_DMA_GDMA_CH3_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH3_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_ADC_R_PMS_REG register
+ *  AHB PDMA adc read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_ADC_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x128)
+/** TEE_DMA_AHB_PDMA_ADC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA adc read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_ADC_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_ADC_R_PMS_M  (TEE_DMA_AHB_PDMA_ADC_R_PMS_V << TEE_DMA_AHB_PDMA_ADC_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_ADC_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_ADC_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_ADC_W_PMS_REG register
+ *  AHB PDMA adc write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_ADC_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x12c)
+/** TEE_DMA_AHB_PDMA_ADC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA adc write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_ADC_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_ADC_W_PMS_M  (TEE_DMA_AHB_PDMA_ADC_W_PMS_V << TEE_DMA_AHB_PDMA_ADC_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_ADC_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_ADC_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S0_R_PMS_REG register
+ *  AHB PDMA i2s0 read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x130)
+/** TEE_DMA_AHB_PDMA_I2S0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s0 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S0_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_M  (TEE_DMA_AHB_PDMA_I2S0_R_PMS_V << TEE_DMA_AHB_PDMA_I2S0_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S0_W_PMS_REG register
+ *  AHB PDMA i2s0 write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x134)
+/** TEE_DMA_AHB_PDMA_I2S0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s0 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S0_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_M  (TEE_DMA_AHB_PDMA_I2S0_W_PMS_V << TEE_DMA_AHB_PDMA_I2S0_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S1_R_PMS_REG register
+ *  AHB PDMA i2s1 read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x138)
+/** TEE_DMA_AHB_PDMA_I2S1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s1 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S1_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_M  (TEE_DMA_AHB_PDMA_I2S1_R_PMS_V << TEE_DMA_AHB_PDMA_I2S1_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S1_W_PMS_REG register
+ *  AHB PDMA i2s1 write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x13c)
+/** TEE_DMA_AHB_PDMA_I2S1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s1 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S1_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_M  (TEE_DMA_AHB_PDMA_I2S1_W_PMS_V << TEE_DMA_AHB_PDMA_I2S1_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S2_R_PMS_REG register
+ *  AHB PDMA i2s2 read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x140)
+/** TEE_DMA_AHB_PDMA_I2S2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s2 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S2_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_M  (TEE_DMA_AHB_PDMA_I2S2_R_PMS_V << TEE_DMA_AHB_PDMA_I2S2_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S2_W_PMS_REG register
+ *  AHB PDMA i2s2 write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x144)
+/** TEE_DMA_AHB_PDMA_I2S2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s2 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S2_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_M  (TEE_DMA_AHB_PDMA_I2S2_W_PMS_V << TEE_DMA_AHB_PDMA_I2S2_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_REG register
+ *  AHB PDMA i3s mst read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x148)
+/** TEE_DMA_AHB_PDMA_I3C_MST_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i3c mst read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_M  (TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_V << TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_REG register
+ *  AHB PDMA i3c mst  write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x14c)
+/** TEE_DMA_AHB_PDMA_I3C_MST_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i3c mst  write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_M  (TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_V << TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_UHCI0_R_PMS_REG register
+ *  AHB PDMA uhci0 read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x150)
+/** TEE_DMA_AHB_PDMA_UHCI0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA uhci0 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_M  (TEE_DMA_AHB_PDMA_UHCI0_R_PMS_V << TEE_DMA_AHB_PDMA_UHCI0_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_UHCI0_W_PMS_REG register
+ *  AHB PDMA uhci0 write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x154)
+/** TEE_DMA_AHB_PDMA_UHCI0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA uhci0 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_M  (TEE_DMA_AHB_PDMA_UHCI0_W_PMS_V << TEE_DMA_AHB_PDMA_UHCI0_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_RMT_R_PMS_REG register
+ *  AHB PDMA rmt read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_RMT_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x158)
+/** TEE_DMA_AHB_PDMA_RMT_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA rmt read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_RMT_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_RMT_R_PMS_M  (TEE_DMA_AHB_PDMA_RMT_R_PMS_V << TEE_DMA_AHB_PDMA_RMT_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_RMT_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_RMT_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_RMT_W_PMS_REG register
+ *  AHB PDMA rmt write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_RMT_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x170)
+/** TEE_DMA_AHB_PDMA_RMT_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA rmt write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_RMT_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_RMT_W_PMS_M  (TEE_DMA_AHB_PDMA_RMT_W_PMS_V << TEE_DMA_AHB_PDMA_RMT_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_RMT_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_RMT_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_REG register
+ *  AXI PDMA lcdcam read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x174)
+/** TEE_DMA_AXI_PDMA_LCDCAM_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA lcdcam read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_M  (TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_V << TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_REG register
+ *  AXI PDMA lcdcam write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x178)
+/** TEE_DMA_AXI_PDMA_LCDCAM_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA lcdcam write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_M  (TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_V << TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_REG register
+ *  AXI PDMA gpspi2 read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x17c)
+/** TEE_DMA_AXI_PDMA_GPSPI2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA gpspi2 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_M  (TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_V << TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_REG register
+ *  AXI PDMA gpspi2 write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x180)
+/** TEE_DMA_AXI_PDMA_GPSPI2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA gpspi2 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_M  (TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_V << TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_REG register
+ *  AXI PDMA gpspi3 read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x184)
+/** TEE_DMA_AXI_PDMA_GPSPI3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA gpspi3 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_M  (TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_V << TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_REG register
+ *  AXI PDMA gpspi3 write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x188)
+/** TEE_DMA_AXI_PDMA_GPSPI3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA gpspi3 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_M  (TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_V << TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_PARLIO_R_PMS_REG register
+ *  AXI PDMA parl io read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x18c)
+/** TEE_DMA_AXI_PDMA_PARLIO_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA parl io read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_M  (TEE_DMA_AXI_PDMA_PARLIO_R_PMS_V << TEE_DMA_AXI_PDMA_PARLIO_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_PARLIO_W_PMS_REG register
+ *  AXI PDMA parl io write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x190)
+/** TEE_DMA_AXI_PDMA_PARLIO_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA parl io write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_M  (TEE_DMA_AXI_PDMA_PARLIO_W_PMS_V << TEE_DMA_AXI_PDMA_PARLIO_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_AES_R_PMS_REG register
+ *  AXI PDMA aes read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_AES_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x194)
+/** TEE_DMA_AXI_PDMA_AES_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA aes read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_AES_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_AES_R_PMS_M  (TEE_DMA_AXI_PDMA_AES_R_PMS_V << TEE_DMA_AXI_PDMA_AES_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_AES_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_AES_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_AES_W_PMS_REG register
+ *  AXI PDMA aes write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_AES_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x198)
+/** TEE_DMA_AXI_PDMA_AES_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA aes write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_AES_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_AES_W_PMS_M  (TEE_DMA_AXI_PDMA_AES_W_PMS_V << TEE_DMA_AXI_PDMA_AES_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_AES_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_AES_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_SHA_R_PMS_REG register
+ *  AXI PDMA sha read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_SHA_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x19c)
+/** TEE_DMA_AXI_PDMA_SHA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA sha read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_SHA_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_SHA_R_PMS_M  (TEE_DMA_AXI_PDMA_SHA_R_PMS_V << TEE_DMA_AXI_PDMA_SHA_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_SHA_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_SHA_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_SHA_W_PMS_REG register
+ *  AXI PDMA sha write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_SHA_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x1a0)
+/** TEE_DMA_AXI_PDMA_SHA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA sha write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_SHA_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_SHA_W_PMS_M  (TEE_DMA_AXI_PDMA_SHA_W_PMS_V << TEE_DMA_AXI_PDMA_SHA_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_SHA_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_SHA_W_PMS_S  0
+
+/** TEE_DMA_DMA2D_JPEG_PMS_R_REG register
+ *  DMA2D JPEG read permission control registers.
+ */
+#define TEE_DMA_DMA2D_JPEG_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1a4)
+/** TEE_DMA_DMA2D_JPEG_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D JPEG read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_JPEG_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_JPEG_R_PMS_M  (TEE_DMA_DMA2D_JPEG_R_PMS_V << TEE_DMA_DMA2D_JPEG_R_PMS_S)
+#define TEE_DMA_DMA2D_JPEG_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_JPEG_R_PMS_S  0
+
+/** TEE_DMA_DMA2D_JPEG_PMS_W_REG register
+ *  DMA2D JPEG write permission control registers.
+ */
+#define TEE_DMA_DMA2D_JPEG_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1a8)
+/** TEE_DMA_DMA2D_JPEG_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D  JPEG write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_JPEG_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_JPEG_W_PMS_M  (TEE_DMA_DMA2D_JPEG_W_PMS_V << TEE_DMA_DMA2D_JPEG_W_PMS_S)
+#define TEE_DMA_DMA2D_JPEG_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_JPEG_W_PMS_S  0
+
+/** TEE_DMA_USB_PMS_R_REG register
+ *  USB read permission control registers.
+ */
+#define TEE_DMA_USB_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1ac)
+/** TEE_DMA_USB_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  USB read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_USB_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_USB_R_PMS_M  (TEE_DMA_USB_R_PMS_V << TEE_DMA_USB_R_PMS_S)
+#define TEE_DMA_USB_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_USB_R_PMS_S  0
+
+/** TEE_DMA_USB_PMS_W_REG register
+ *  USB write permission control registers.
+ */
+#define TEE_DMA_USB_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1b0)
+/** TEE_DMA_USB_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  USB write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_USB_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_USB_W_PMS_M  (TEE_DMA_USB_W_PMS_V << TEE_DMA_USB_W_PMS_S)
+#define TEE_DMA_USB_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_USB_W_PMS_S  0
+
+/** TEE_DMA_GMAC_PMS_R_REG register
+ *  GMAC read permission control registers.
+ */
+#define TEE_DMA_GMAC_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1b4)
+/** TEE_DMA_GMAC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GMAC read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GMAC_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_GMAC_R_PMS_M  (TEE_DMA_GMAC_R_PMS_V << TEE_DMA_GMAC_R_PMS_S)
+#define TEE_DMA_GMAC_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GMAC_R_PMS_S  0
+
+/** TEE_DMA_GMAC_PMS_W_REG register
+ *  GMAC write permission control registers.
+ */
+#define TEE_DMA_GMAC_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1b8)
+/** TEE_DMA_GMAC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GMAC write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GMAC_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_GMAC_W_PMS_M  (TEE_DMA_GMAC_W_PMS_V << TEE_DMA_GMAC_W_PMS_S)
+#define TEE_DMA_GMAC_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GMAC_W_PMS_S  0
+
+/** TEE_DMA_SDMMC_PMS_R_REG register
+ *  SDMMC read permission control registers.
+ */
+#define TEE_DMA_SDMMC_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1bc)
+/** TEE_DMA_SDMMC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  SDMMC read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_SDMMC_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_SDMMC_R_PMS_M  (TEE_DMA_SDMMC_R_PMS_V << TEE_DMA_SDMMC_R_PMS_S)
+#define TEE_DMA_SDMMC_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_SDMMC_R_PMS_S  0
+
+/** TEE_DMA_SDMMC_PMS_W_REG register
+ *  SDMMC write permission control registers.
+ */
+#define TEE_DMA_SDMMC_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1c0)
+/** TEE_DMA_SDMMC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  SDMMC write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_SDMMC_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_SDMMC_W_PMS_M  (TEE_DMA_SDMMC_W_PMS_V << TEE_DMA_SDMMC_W_PMS_S)
+#define TEE_DMA_SDMMC_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_SDMMC_W_PMS_S  0
+
+/** TEE_DMA_USBOTG11_PMS_R_REG register
+ *  USBOTG11 read permission control registers.
+ */
+#define TEE_DMA_USBOTG11_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1c4)
+/** TEE_DMA_USBOTG11_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  USBOTG11 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_USBOTG11_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_USBOTG11_R_PMS_M  (TEE_DMA_USBOTG11_R_PMS_V << TEE_DMA_USBOTG11_R_PMS_S)
+#define TEE_DMA_USBOTG11_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_USBOTG11_R_PMS_S  0
+
+/** TEE_DMA_USBOTG11_PMS_W_REG register
+ *  USBOTG11 write permission control registers.
+ */
+#define TEE_DMA_USBOTG11_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1c8)
+/** TEE_DMA_USBOTG11_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  USBOTG11 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_USBOTG11_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_USBOTG11_W_PMS_M  (TEE_DMA_USBOTG11_W_PMS_V << TEE_DMA_USBOTG11_W_PMS_S)
+#define TEE_DMA_USBOTG11_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_USBOTG11_W_PMS_S  0
+
+/** TEE_DMA_TRACE0_PMS_R_REG register
+ *  TRACE0 read permission control registers.
+ */
+#define TEE_DMA_TRACE0_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1cc)
+/** TEE_DMA_TRACE0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TRACE0 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TRACE0_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_TRACE0_R_PMS_M  (TEE_DMA_TRACE0_R_PMS_V << TEE_DMA_TRACE0_R_PMS_S)
+#define TEE_DMA_TRACE0_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TRACE0_R_PMS_S  0
+
+/** TEE_DMA_TRACE0_PMS_W_REG register
+ *  TRACE0 write permission control registers.
+ */
+#define TEE_DMA_TRACE0_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1d0)
+/** TEE_DMA_TRACE0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TRACE0 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TRACE0_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_TRACE0_W_PMS_M  (TEE_DMA_TRACE0_W_PMS_V << TEE_DMA_TRACE0_W_PMS_S)
+#define TEE_DMA_TRACE0_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TRACE0_W_PMS_S  0
+
+/** TEE_DMA_TRACE1_PMS_R_REG register
+ *  TRACE1 read permission control registers.
+ */
+#define TEE_DMA_TRACE1_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1d4)
+/** TEE_DMA_TRACE1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TRACE1 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TRACE1_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_TRACE1_R_PMS_M  (TEE_DMA_TRACE1_R_PMS_V << TEE_DMA_TRACE1_R_PMS_S)
+#define TEE_DMA_TRACE1_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TRACE1_R_PMS_S  0
+
+/** TEE_DMA_TRACE1_PMS_W_REG register
+ *  TRACE1 write permission control registers.
+ */
+#define TEE_DMA_TRACE1_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1d8)
+/** TEE_DMA_TRACE1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TRACE1 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TRACE1_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_TRACE1_W_PMS_M  (TEE_DMA_TRACE1_W_PMS_V << TEE_DMA_TRACE1_W_PMS_S)
+#define TEE_DMA_TRACE1_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TRACE1_W_PMS_S  0
+
+/** TEE_DMA_L2MEM_MON_PMS_R_REG register
+ *  L2MEM MON read permission control registers.
+ */
+#define TEE_DMA_L2MEM_MON_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1dc)
+/** TEE_DMA_L2MEM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  L2MEM MON read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_L2MEM_MON_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_L2MEM_MON_R_PMS_M  (TEE_DMA_L2MEM_MON_R_PMS_V << TEE_DMA_L2MEM_MON_R_PMS_S)
+#define TEE_DMA_L2MEM_MON_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_L2MEM_MON_R_PMS_S  0
+
+/** TEE_DMA_L2MEM_MON_PMS_W_REG register
+ *  L2MEM MON write permission control registers.
+ */
+#define TEE_DMA_L2MEM_MON_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1e0)
+/** TEE_DMA_L2MEM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  L2MEM MON write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_L2MEM_MON_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_L2MEM_MON_W_PMS_M  (TEE_DMA_L2MEM_MON_W_PMS_V << TEE_DMA_L2MEM_MON_W_PMS_S)
+#define TEE_DMA_L2MEM_MON_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_L2MEM_MON_W_PMS_S  0
+
+/** TEE_DMA_TCM_MON_PMS_R_REG register
+ *  TCM MON read permission control registers.
+ */
+#define TEE_DMA_TCM_MON_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1e4)
+/** TEE_DMA_TCM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TCM MON read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TCM_MON_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_TCM_MON_R_PMS_M  (TEE_DMA_TCM_MON_R_PMS_V << TEE_DMA_TCM_MON_R_PMS_S)
+#define TEE_DMA_TCM_MON_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TCM_MON_R_PMS_S  0
+
+/** TEE_DMA_TCM_MON_PMS_W_REG register
+ *  TCM MON write permission control registers.
+ */
+#define TEE_DMA_TCM_MON_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1e8)
+/** TEE_DMA_TCM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TCM MON write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TCM_MON_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_TCM_MON_W_PMS_M  (TEE_DMA_TCM_MON_W_PMS_V << TEE_DMA_TCM_MON_W_PMS_S)
+#define TEE_DMA_TCM_MON_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TCM_MON_W_PMS_S  0
+
+/** TEE_DMA_REGDMA_PMS_R_REG register
+ *  REGDMA read permission control registers.
+ */
+#define TEE_DMA_REGDMA_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1ec)
+/** TEE_DMA_REGDMA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  REGDMA read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_REGDMA_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_REGDMA_R_PMS_M  (TEE_DMA_REGDMA_R_PMS_V << TEE_DMA_REGDMA_R_PMS_S)
+#define TEE_DMA_REGDMA_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_REGDMA_R_PMS_S  0
+
+/** TEE_DMA_REGDMA_PMS_W_REG register
+ *  REGDMA write permission control registers.
+ */
+#define TEE_DMA_REGDMA_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1f0)
+/** TEE_DMA_REGDMA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  REGDMA write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_REGDMA_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_REGDMA_W_PMS_M  (TEE_DMA_REGDMA_W_PMS_V << TEE_DMA_REGDMA_W_PMS_S)
+#define TEE_DMA_REGDMA_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_REGDMA_W_PMS_S  0
+
+/** TEE_DMA_H264_PMS_R_REG register
+ *  H264 read permission control registers.
+ */
+#define TEE_DMA_H264_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1fc)
+/** TEE_DMA_H264_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  H264 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_H264_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_H264_R_PMS_M  (TEE_DMA_H264_R_PMS_V << TEE_DMA_H264_R_PMS_S)
+#define TEE_DMA_H264_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_H264_R_PMS_S  0
+
+/** TEE_DMA_H264_PMS_W_REG register
+ *  H264 write permission control registers.
+ */
+#define TEE_DMA_H264_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x200)
+/** TEE_DMA_H264_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  H264 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_H264_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_H264_W_PMS_M  (TEE_DMA_H264_W_PMS_V << TEE_DMA_H264_W_PMS_S)
+#define TEE_DMA_H264_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_H264_W_PMS_S  0
+
+/** TEE_DMA_DMA2D_PPA_PMS_R_REG register
+ *  DMA2D PPA read permission control registers.
+ */
+#define TEE_DMA_DMA2D_PPA_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x204)
+/** TEE_DMA_DMA2D_PPA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D PPA  read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_PPA_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_PPA_R_PMS_M  (TEE_DMA_DMA2D_PPA_R_PMS_V << TEE_DMA_DMA2D_PPA_R_PMS_S)
+#define TEE_DMA_DMA2D_PPA_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_PPA_R_PMS_S  0
+
+/** TEE_DMA_DMA2D_PPA_PMS_W_REG register
+ *  DMA2D PPA  write permission control registers.
+ */
+#define TEE_DMA_DMA2D_PPA_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x208)
+/** TEE_DMA_DMA2D_PPA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D  PPA write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_PPA_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_PPA_W_PMS_M  (TEE_DMA_DMA2D_PPA_W_PMS_V << TEE_DMA_DMA2D_PPA_W_PMS_S)
+#define TEE_DMA_DMA2D_PPA_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_PPA_W_PMS_S  0
+
+/** TEE_DMA_DMA2D_DUMMY_PMS_R_REG register
+ *  DMA2D dummy read permission control registers.
+ */
+#define TEE_DMA_DMA2D_DUMMY_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x20c)
+/** TEE_DMA_DMA2D_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D dummy  read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_DUMMY_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_DUMMY_R_PMS_M  (TEE_DMA_DMA2D_DUMMY_R_PMS_V << TEE_DMA_DMA2D_DUMMY_R_PMS_S)
+#define TEE_DMA_DMA2D_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_DUMMY_R_PMS_S  0
+
+/** TEE_DMA_DMA2D_DUMMY_PMS_W_REG register
+ *  DMA2D dummy  write permission control registers.
+ */
+#define TEE_DMA_DMA2D_DUMMY_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x210)
+/** TEE_DMA_DMA2D_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D dummy  write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_DUMMY_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_DUMMY_W_PMS_M  (TEE_DMA_DMA2D_DUMMY_W_PMS_V << TEE_DMA_DMA2D_DUMMY_W_PMS_S)
+#define TEE_DMA_DMA2D_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_DUMMY_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_DUMMY_R_PMS_REG register
+ *  AHB PDMA dummy read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x214)
+/** TEE_DMA_AHB_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA dummy read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_M  (TEE_DMA_AHB_PDMA_DUMMY_R_PMS_V << TEE_DMA_AHB_PDMA_DUMMY_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_DUMMY_W_PMS_REG register
+ *  AHB PDMA dummy write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x218)
+/** TEE_DMA_AHB_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA dummy write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_M  (TEE_DMA_AHB_PDMA_DUMMY_W_PMS_V << TEE_DMA_AHB_PDMA_DUMMY_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_DUMMY_R_PMS_REG register
+ *  AXI PDMA dummy read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x21c)
+/** TEE_DMA_AXI_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA dummy read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_M  (TEE_DMA_AXI_PDMA_DUMMY_R_PMS_V << TEE_DMA_AXI_PDMA_DUMMY_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_DUMMY_W_PMS_REG register
+ *  AXI PDMA dummy write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x220)
+/** TEE_DMA_AXI_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA dummy write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_M  (TEE_DMA_AXI_PDMA_DUMMY_W_PMS_V << TEE_DMA_AXI_PDMA_DUMMY_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_reg.h
new file mode 100644
index 0000000000..c07d10067a
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_reg.h
@@ -0,0 +1,1740 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMS_DMA_DATE_REG register
+ *  Version control register
+ */
+#define PMS_DMA_DATE_REG (DR_REG_DMA_PMS_BASE + 0x0)
+/** PMS_DMA_DATE : R/W; bitpos: [31:0]; default: 539165460;
+ *  Version control register.
+ */
+#define PMS_DMA_DATE    0xFFFFFFFFU
+#define PMS_DMA_DATE_M  (PMS_DMA_DATE_V << PMS_DMA_DATE_S)
+#define PMS_DMA_DATE_V  0xFFFFFFFFU
+#define PMS_DMA_DATE_S  0
+
+/** PMS_DMA_CLK_EN_REG register
+ *  Clock gating register
+ */
+#define PMS_DMA_CLK_EN_REG (DR_REG_DMA_PMS_BASE + 0x4)
+/** PMS_DMA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating.
+ *  1: Keep the clock always on.
+ */
+#define PMS_DMA_CLK_EN    (BIT(0))
+#define PMS_DMA_CLK_EN_M  (PMS_DMA_CLK_EN_V << PMS_DMA_CLK_EN_S)
+#define PMS_DMA_CLK_EN_V  0x00000001U
+#define PMS_DMA_CLK_EN_S  0
+
+/** PMS_DMA_REGION0_LOW_REG register
+ *  Region0 start address configuration register
+ */
+#define PMS_DMA_REGION0_LOW_REG (DR_REG_DMA_PMS_BASE + 0x8)
+/** PMS_DMA_REGION0_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region0.
+ */
+#define PMS_DMA_REGION0_LOW    0x000FFFFFU
+#define PMS_DMA_REGION0_LOW_M  (PMS_DMA_REGION0_LOW_V << PMS_DMA_REGION0_LOW_S)
+#define PMS_DMA_REGION0_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION0_LOW_S  12
+
+/** PMS_DMA_REGION0_HIGH_REG register
+ *  Region0 end address configuration register
+ */
+#define PMS_DMA_REGION0_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xc)
+/** PMS_DMA_REGION0_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region0.
+ */
+#define PMS_DMA_REGION0_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION0_HIGH_M  (PMS_DMA_REGION0_HIGH_V << PMS_DMA_REGION0_HIGH_S)
+#define PMS_DMA_REGION0_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION0_HIGH_S  12
+
+/** PMS_DMA_REGION1_LOW_REG register
+ *  Region1 start address configuration register
+ */
+#define PMS_DMA_REGION1_LOW_REG (DR_REG_DMA_PMS_BASE + 0x10)
+/** PMS_DMA_REGION1_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region1.
+ */
+#define PMS_DMA_REGION1_LOW    0x000FFFFFU
+#define PMS_DMA_REGION1_LOW_M  (PMS_DMA_REGION1_LOW_V << PMS_DMA_REGION1_LOW_S)
+#define PMS_DMA_REGION1_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION1_LOW_S  12
+
+/** PMS_DMA_REGION1_HIGH_REG register
+ *  Region1 end address configuration register
+ */
+#define PMS_DMA_REGION1_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x14)
+/** PMS_DMA_REGION1_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region1.
+ */
+#define PMS_DMA_REGION1_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION1_HIGH_M  (PMS_DMA_REGION1_HIGH_V << PMS_DMA_REGION1_HIGH_S)
+#define PMS_DMA_REGION1_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION1_HIGH_S  12
+
+/** PMS_DMA_REGION2_LOW_REG register
+ *  Region2 start address configuration register
+ */
+#define PMS_DMA_REGION2_LOW_REG (DR_REG_DMA_PMS_BASE + 0x18)
+/** PMS_DMA_REGION2_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region2.
+ */
+#define PMS_DMA_REGION2_LOW    0x000FFFFFU
+#define PMS_DMA_REGION2_LOW_M  (PMS_DMA_REGION2_LOW_V << PMS_DMA_REGION2_LOW_S)
+#define PMS_DMA_REGION2_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION2_LOW_S  12
+
+/** PMS_DMA_REGION2_HIGH_REG register
+ *  Region2 end address configuration register
+ */
+#define PMS_DMA_REGION2_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x1c)
+/** PMS_DMA_REGION2_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region2.
+ */
+#define PMS_DMA_REGION2_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION2_HIGH_M  (PMS_DMA_REGION2_HIGH_V << PMS_DMA_REGION2_HIGH_S)
+#define PMS_DMA_REGION2_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION2_HIGH_S  12
+
+/** PMS_DMA_REGION3_LOW_REG register
+ *  Region3 start address configuration register
+ */
+#define PMS_DMA_REGION3_LOW_REG (DR_REG_DMA_PMS_BASE + 0x20)
+/** PMS_DMA_REGION3_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region3.
+ */
+#define PMS_DMA_REGION3_LOW    0x000FFFFFU
+#define PMS_DMA_REGION3_LOW_M  (PMS_DMA_REGION3_LOW_V << PMS_DMA_REGION3_LOW_S)
+#define PMS_DMA_REGION3_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION3_LOW_S  12
+
+/** PMS_DMA_REGION3_HIGH_REG register
+ *  Region3 end address configuration register
+ */
+#define PMS_DMA_REGION3_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x24)
+/** PMS_DMA_REGION3_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region3.
+ */
+#define PMS_DMA_REGION3_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION3_HIGH_M  (PMS_DMA_REGION3_HIGH_V << PMS_DMA_REGION3_HIGH_S)
+#define PMS_DMA_REGION3_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION3_HIGH_S  12
+
+/** PMS_DMA_REGION4_LOW_REG register
+ *  Region4 start address configuration register
+ */
+#define PMS_DMA_REGION4_LOW_REG (DR_REG_DMA_PMS_BASE + 0x28)
+/** PMS_DMA_REGION4_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region4.
+ */
+#define PMS_DMA_REGION4_LOW    0x000FFFFFU
+#define PMS_DMA_REGION4_LOW_M  (PMS_DMA_REGION4_LOW_V << PMS_DMA_REGION4_LOW_S)
+#define PMS_DMA_REGION4_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION4_LOW_S  12
+
+/** PMS_DMA_REGION4_HIGH_REG register
+ *  Region4 end address configuration register
+ */
+#define PMS_DMA_REGION4_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x2c)
+/** PMS_DMA_REGION4_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region4.
+ */
+#define PMS_DMA_REGION4_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION4_HIGH_M  (PMS_DMA_REGION4_HIGH_V << PMS_DMA_REGION4_HIGH_S)
+#define PMS_DMA_REGION4_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION4_HIGH_S  12
+
+/** PMS_DMA_REGION5_LOW_REG register
+ *  Region5 start address configuration register
+ */
+#define PMS_DMA_REGION5_LOW_REG (DR_REG_DMA_PMS_BASE + 0x30)
+/** PMS_DMA_REGION5_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region5.
+ */
+#define PMS_DMA_REGION5_LOW    0x000FFFFFU
+#define PMS_DMA_REGION5_LOW_M  (PMS_DMA_REGION5_LOW_V << PMS_DMA_REGION5_LOW_S)
+#define PMS_DMA_REGION5_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION5_LOW_S  12
+
+/** PMS_DMA_REGION5_HIGH_REG register
+ *  Region5 end address configuration register
+ */
+#define PMS_DMA_REGION5_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x34)
+/** PMS_DMA_REGION5_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region5.
+ */
+#define PMS_DMA_REGION5_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION5_HIGH_M  (PMS_DMA_REGION5_HIGH_V << PMS_DMA_REGION5_HIGH_S)
+#define PMS_DMA_REGION5_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION5_HIGH_S  12
+
+/** PMS_DMA_REGION6_LOW_REG register
+ *  Region6 start address configuration register
+ */
+#define PMS_DMA_REGION6_LOW_REG (DR_REG_DMA_PMS_BASE + 0x38)
+/** PMS_DMA_REGION6_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region6.
+ */
+#define PMS_DMA_REGION6_LOW    0x000FFFFFU
+#define PMS_DMA_REGION6_LOW_M  (PMS_DMA_REGION6_LOW_V << PMS_DMA_REGION6_LOW_S)
+#define PMS_DMA_REGION6_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION6_LOW_S  12
+
+/** PMS_DMA_REGION6_HIGH_REG register
+ *  Region6 end address configuration register
+ */
+#define PMS_DMA_REGION6_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x3c)
+/** PMS_DMA_REGION6_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region6.
+ */
+#define PMS_DMA_REGION6_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION6_HIGH_M  (PMS_DMA_REGION6_HIGH_V << PMS_DMA_REGION6_HIGH_S)
+#define PMS_DMA_REGION6_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION6_HIGH_S  12
+
+/** PMS_DMA_REGION7_LOW_REG register
+ *  Region7 start address configuration register
+ */
+#define PMS_DMA_REGION7_LOW_REG (DR_REG_DMA_PMS_BASE + 0x40)
+/** PMS_DMA_REGION7_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region7.
+ */
+#define PMS_DMA_REGION7_LOW    0x000FFFFFU
+#define PMS_DMA_REGION7_LOW_M  (PMS_DMA_REGION7_LOW_V << PMS_DMA_REGION7_LOW_S)
+#define PMS_DMA_REGION7_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION7_LOW_S  12
+
+/** PMS_DMA_REGION7_HIGH_REG register
+ *  Region7 end address configuration register
+ */
+#define PMS_DMA_REGION7_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x44)
+/** PMS_DMA_REGION7_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region7.
+ */
+#define PMS_DMA_REGION7_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION7_HIGH_M  (PMS_DMA_REGION7_HIGH_V << PMS_DMA_REGION7_HIGH_S)
+#define PMS_DMA_REGION7_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION7_HIGH_S  12
+
+/** PMS_DMA_REGION8_LOW_REG register
+ *  Region8 start address configuration register
+ */
+#define PMS_DMA_REGION8_LOW_REG (DR_REG_DMA_PMS_BASE + 0x48)
+/** PMS_DMA_REGION8_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region8.
+ */
+#define PMS_DMA_REGION8_LOW    0x000FFFFFU
+#define PMS_DMA_REGION8_LOW_M  (PMS_DMA_REGION8_LOW_V << PMS_DMA_REGION8_LOW_S)
+#define PMS_DMA_REGION8_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION8_LOW_S  12
+
+/** PMS_DMA_REGION8_HIGH_REG register
+ *  Region8 end address configuration register
+ */
+#define PMS_DMA_REGION8_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x4c)
+/** PMS_DMA_REGION8_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region8.
+ */
+#define PMS_DMA_REGION8_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION8_HIGH_M  (PMS_DMA_REGION8_HIGH_V << PMS_DMA_REGION8_HIGH_S)
+#define PMS_DMA_REGION8_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION8_HIGH_S  12
+
+/** PMS_DMA_REGION9_LOW_REG register
+ *  Region9 start address configuration register
+ */
+#define PMS_DMA_REGION9_LOW_REG (DR_REG_DMA_PMS_BASE + 0x50)
+/** PMS_DMA_REGION9_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region9.
+ */
+#define PMS_DMA_REGION9_LOW    0x000FFFFFU
+#define PMS_DMA_REGION9_LOW_M  (PMS_DMA_REGION9_LOW_V << PMS_DMA_REGION9_LOW_S)
+#define PMS_DMA_REGION9_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION9_LOW_S  12
+
+/** PMS_DMA_REGION9_HIGH_REG register
+ *  Region9 end address configuration register
+ */
+#define PMS_DMA_REGION9_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x54)
+/** PMS_DMA_REGION9_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region9.
+ */
+#define PMS_DMA_REGION9_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION9_HIGH_M  (PMS_DMA_REGION9_HIGH_V << PMS_DMA_REGION9_HIGH_S)
+#define PMS_DMA_REGION9_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION9_HIGH_S  12
+
+/** PMS_DMA_REGION10_LOW_REG register
+ *  Region10 start address configuration register
+ */
+#define PMS_DMA_REGION10_LOW_REG (DR_REG_DMA_PMS_BASE + 0x58)
+/** PMS_DMA_REGION10_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region10.
+ */
+#define PMS_DMA_REGION10_LOW    0x000FFFFFU
+#define PMS_DMA_REGION10_LOW_M  (PMS_DMA_REGION10_LOW_V << PMS_DMA_REGION10_LOW_S)
+#define PMS_DMA_REGION10_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION10_LOW_S  12
+
+/** PMS_DMA_REGION10_HIGH_REG register
+ *  Region10 end address configuration register
+ */
+#define PMS_DMA_REGION10_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x5c)
+/** PMS_DMA_REGION10_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region10.
+ */
+#define PMS_DMA_REGION10_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION10_HIGH_M  (PMS_DMA_REGION10_HIGH_V << PMS_DMA_REGION10_HIGH_S)
+#define PMS_DMA_REGION10_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION10_HIGH_S  12
+
+/** PMS_DMA_REGION11_LOW_REG register
+ *  Region11 start address configuration register
+ */
+#define PMS_DMA_REGION11_LOW_REG (DR_REG_DMA_PMS_BASE + 0x60)
+/** PMS_DMA_REGION11_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region11.
+ */
+#define PMS_DMA_REGION11_LOW    0x000FFFFFU
+#define PMS_DMA_REGION11_LOW_M  (PMS_DMA_REGION11_LOW_V << PMS_DMA_REGION11_LOW_S)
+#define PMS_DMA_REGION11_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION11_LOW_S  12
+
+/** PMS_DMA_REGION11_HIGH_REG register
+ *  Region11 end address configuration register
+ */
+#define PMS_DMA_REGION11_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x64)
+/** PMS_DMA_REGION11_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region11.
+ */
+#define PMS_DMA_REGION11_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION11_HIGH_M  (PMS_DMA_REGION11_HIGH_V << PMS_DMA_REGION11_HIGH_S)
+#define PMS_DMA_REGION11_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION11_HIGH_S  12
+
+/** PMS_DMA_REGION12_LOW_REG register
+ *  Region12 start address configuration register
+ */
+#define PMS_DMA_REGION12_LOW_REG (DR_REG_DMA_PMS_BASE + 0x68)
+/** PMS_DMA_REGION12_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region12.
+ */
+#define PMS_DMA_REGION12_LOW    0x000FFFFFU
+#define PMS_DMA_REGION12_LOW_M  (PMS_DMA_REGION12_LOW_V << PMS_DMA_REGION12_LOW_S)
+#define PMS_DMA_REGION12_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION12_LOW_S  12
+
+/** PMS_DMA_REGION12_HIGH_REG register
+ *  Region12 end address configuration register
+ */
+#define PMS_DMA_REGION12_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x6c)
+/** PMS_DMA_REGION12_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region12.
+ */
+#define PMS_DMA_REGION12_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION12_HIGH_M  (PMS_DMA_REGION12_HIGH_V << PMS_DMA_REGION12_HIGH_S)
+#define PMS_DMA_REGION12_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION12_HIGH_S  12
+
+/** PMS_DMA_REGION13_LOW_REG register
+ *  Region13 start address configuration register
+ */
+#define PMS_DMA_REGION13_LOW_REG (DR_REG_DMA_PMS_BASE + 0x70)
+/** PMS_DMA_REGION13_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region13.
+ */
+#define PMS_DMA_REGION13_LOW    0x000FFFFFU
+#define PMS_DMA_REGION13_LOW_M  (PMS_DMA_REGION13_LOW_V << PMS_DMA_REGION13_LOW_S)
+#define PMS_DMA_REGION13_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION13_LOW_S  12
+
+/** PMS_DMA_REGION13_HIGH_REG register
+ *  Region13 end address configuration register
+ */
+#define PMS_DMA_REGION13_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x74)
+/** PMS_DMA_REGION13_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region13.
+ */
+#define PMS_DMA_REGION13_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION13_HIGH_M  (PMS_DMA_REGION13_HIGH_V << PMS_DMA_REGION13_HIGH_S)
+#define PMS_DMA_REGION13_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION13_HIGH_S  12
+
+/** PMS_DMA_REGION14_LOW_REG register
+ *  Region14 start address configuration register
+ */
+#define PMS_DMA_REGION14_LOW_REG (DR_REG_DMA_PMS_BASE + 0x78)
+/** PMS_DMA_REGION14_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region14.
+ */
+#define PMS_DMA_REGION14_LOW    0x000FFFFFU
+#define PMS_DMA_REGION14_LOW_M  (PMS_DMA_REGION14_LOW_V << PMS_DMA_REGION14_LOW_S)
+#define PMS_DMA_REGION14_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION14_LOW_S  12
+
+/** PMS_DMA_REGION14_HIGH_REG register
+ *  Region14 end address configuration register
+ */
+#define PMS_DMA_REGION14_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x7c)
+/** PMS_DMA_REGION14_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region14.
+ */
+#define PMS_DMA_REGION14_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION14_HIGH_M  (PMS_DMA_REGION14_HIGH_V << PMS_DMA_REGION14_HIGH_S)
+#define PMS_DMA_REGION14_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION14_HIGH_S  12
+
+/** PMS_DMA_REGION15_LOW_REG register
+ *  Region15 start address configuration register
+ */
+#define PMS_DMA_REGION15_LOW_REG (DR_REG_DMA_PMS_BASE + 0x80)
+/** PMS_DMA_REGION15_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region15.
+ */
+#define PMS_DMA_REGION15_LOW    0x000FFFFFU
+#define PMS_DMA_REGION15_LOW_M  (PMS_DMA_REGION15_LOW_V << PMS_DMA_REGION15_LOW_S)
+#define PMS_DMA_REGION15_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION15_LOW_S  12
+
+/** PMS_DMA_REGION15_HIGH_REG register
+ *  Region15 end address configuration register
+ */
+#define PMS_DMA_REGION15_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x84)
+/** PMS_DMA_REGION15_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region15.
+ */
+#define PMS_DMA_REGION15_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION15_HIGH_M  (PMS_DMA_REGION15_HIGH_V << PMS_DMA_REGION15_HIGH_S)
+#define PMS_DMA_REGION15_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION15_HIGH_S  12
+
+/** PMS_DMA_REGION16_LOW_REG register
+ *  Region16 start address configuration register
+ */
+#define PMS_DMA_REGION16_LOW_REG (DR_REG_DMA_PMS_BASE + 0x88)
+/** PMS_DMA_REGION16_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region16.
+ */
+#define PMS_DMA_REGION16_LOW    0x000FFFFFU
+#define PMS_DMA_REGION16_LOW_M  (PMS_DMA_REGION16_LOW_V << PMS_DMA_REGION16_LOW_S)
+#define PMS_DMA_REGION16_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION16_LOW_S  12
+
+/** PMS_DMA_REGION16_HIGH_REG register
+ *  Region16 end address configuration register
+ */
+#define PMS_DMA_REGION16_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x8c)
+/** PMS_DMA_REGION16_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region16.
+ */
+#define PMS_DMA_REGION16_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION16_HIGH_M  (PMS_DMA_REGION16_HIGH_V << PMS_DMA_REGION16_HIGH_S)
+#define PMS_DMA_REGION16_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION16_HIGH_S  12
+
+/** PMS_DMA_REGION17_LOW_REG register
+ *  Region17 start address configuration register
+ */
+#define PMS_DMA_REGION17_LOW_REG (DR_REG_DMA_PMS_BASE + 0x90)
+/** PMS_DMA_REGION17_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region17.
+ */
+#define PMS_DMA_REGION17_LOW    0x000FFFFFU
+#define PMS_DMA_REGION17_LOW_M  (PMS_DMA_REGION17_LOW_V << PMS_DMA_REGION17_LOW_S)
+#define PMS_DMA_REGION17_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION17_LOW_S  12
+
+/** PMS_DMA_REGION17_HIGH_REG register
+ *  Region17 end address configuration register
+ */
+#define PMS_DMA_REGION17_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x94)
+/** PMS_DMA_REGION17_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region17.
+ */
+#define PMS_DMA_REGION17_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION17_HIGH_M  (PMS_DMA_REGION17_HIGH_V << PMS_DMA_REGION17_HIGH_S)
+#define PMS_DMA_REGION17_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION17_HIGH_S  12
+
+/** PMS_DMA_REGION18_LOW_REG register
+ *  Region18 start address configuration register
+ */
+#define PMS_DMA_REGION18_LOW_REG (DR_REG_DMA_PMS_BASE + 0x98)
+/** PMS_DMA_REGION18_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region18.
+ */
+#define PMS_DMA_REGION18_LOW    0x000FFFFFU
+#define PMS_DMA_REGION18_LOW_M  (PMS_DMA_REGION18_LOW_V << PMS_DMA_REGION18_LOW_S)
+#define PMS_DMA_REGION18_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION18_LOW_S  12
+
+/** PMS_DMA_REGION18_HIGH_REG register
+ *  Region18 end address configuration register
+ */
+#define PMS_DMA_REGION18_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x9c)
+/** PMS_DMA_REGION18_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region18.
+ */
+#define PMS_DMA_REGION18_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION18_HIGH_M  (PMS_DMA_REGION18_HIGH_V << PMS_DMA_REGION18_HIGH_S)
+#define PMS_DMA_REGION18_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION18_HIGH_S  12
+
+/** PMS_DMA_REGION19_LOW_REG register
+ *  Region19 start address configuration register
+ */
+#define PMS_DMA_REGION19_LOW_REG (DR_REG_DMA_PMS_BASE + 0xa0)
+/** PMS_DMA_REGION19_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region19.
+ */
+#define PMS_DMA_REGION19_LOW    0x000FFFFFU
+#define PMS_DMA_REGION19_LOW_M  (PMS_DMA_REGION19_LOW_V << PMS_DMA_REGION19_LOW_S)
+#define PMS_DMA_REGION19_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION19_LOW_S  12
+
+/** PMS_DMA_REGION19_HIGH_REG register
+ *  Region19 end address configuration register
+ */
+#define PMS_DMA_REGION19_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xa4)
+/** PMS_DMA_REGION19_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region19.
+ */
+#define PMS_DMA_REGION19_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION19_HIGH_M  (PMS_DMA_REGION19_HIGH_V << PMS_DMA_REGION19_HIGH_S)
+#define PMS_DMA_REGION19_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION19_HIGH_S  12
+
+/** PMS_DMA_REGION20_LOW_REG register
+ *  Region20 start address configuration register
+ */
+#define PMS_DMA_REGION20_LOW_REG (DR_REG_DMA_PMS_BASE + 0xa8)
+/** PMS_DMA_REGION20_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region20.
+ */
+#define PMS_DMA_REGION20_LOW    0x000FFFFFU
+#define PMS_DMA_REGION20_LOW_M  (PMS_DMA_REGION20_LOW_V << PMS_DMA_REGION20_LOW_S)
+#define PMS_DMA_REGION20_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION20_LOW_S  12
+
+/** PMS_DMA_REGION20_HIGH_REG register
+ *  Region20 end address configuration register
+ */
+#define PMS_DMA_REGION20_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xac)
+/** PMS_DMA_REGION20_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region20.
+ */
+#define PMS_DMA_REGION20_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION20_HIGH_M  (PMS_DMA_REGION20_HIGH_V << PMS_DMA_REGION20_HIGH_S)
+#define PMS_DMA_REGION20_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION20_HIGH_S  12
+
+/** PMS_DMA_REGION21_LOW_REG register
+ *  Region21 start address configuration register
+ */
+#define PMS_DMA_REGION21_LOW_REG (DR_REG_DMA_PMS_BASE + 0xb0)
+/** PMS_DMA_REGION21_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region21.
+ */
+#define PMS_DMA_REGION21_LOW    0x000FFFFFU
+#define PMS_DMA_REGION21_LOW_M  (PMS_DMA_REGION21_LOW_V << PMS_DMA_REGION21_LOW_S)
+#define PMS_DMA_REGION21_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION21_LOW_S  12
+
+/** PMS_DMA_REGION21_HIGH_REG register
+ *  Region21 end address configuration register
+ */
+#define PMS_DMA_REGION21_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xb4)
+/** PMS_DMA_REGION21_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region21.
+ */
+#define PMS_DMA_REGION21_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION21_HIGH_M  (PMS_DMA_REGION21_HIGH_V << PMS_DMA_REGION21_HIGH_S)
+#define PMS_DMA_REGION21_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION21_HIGH_S  12
+
+/** PMS_DMA_REGION22_LOW_REG register
+ *  Region22 start address configuration register
+ */
+#define PMS_DMA_REGION22_LOW_REG (DR_REG_DMA_PMS_BASE + 0xb8)
+/** PMS_DMA_REGION22_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region22.
+ */
+#define PMS_DMA_REGION22_LOW    0x000FFFFFU
+#define PMS_DMA_REGION22_LOW_M  (PMS_DMA_REGION22_LOW_V << PMS_DMA_REGION22_LOW_S)
+#define PMS_DMA_REGION22_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION22_LOW_S  12
+
+/** PMS_DMA_REGION22_HIGH_REG register
+ *  Region22 end address configuration register
+ */
+#define PMS_DMA_REGION22_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xbc)
+/** PMS_DMA_REGION22_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region22.
+ */
+#define PMS_DMA_REGION22_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION22_HIGH_M  (PMS_DMA_REGION22_HIGH_V << PMS_DMA_REGION22_HIGH_S)
+#define PMS_DMA_REGION22_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION22_HIGH_S  12
+
+/** PMS_DMA_REGION23_LOW_REG register
+ *  Region23 start address configuration register
+ */
+#define PMS_DMA_REGION23_LOW_REG (DR_REG_DMA_PMS_BASE + 0xc0)
+/** PMS_DMA_REGION23_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region23.
+ */
+#define PMS_DMA_REGION23_LOW    0x000FFFFFU
+#define PMS_DMA_REGION23_LOW_M  (PMS_DMA_REGION23_LOW_V << PMS_DMA_REGION23_LOW_S)
+#define PMS_DMA_REGION23_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION23_LOW_S  12
+
+/** PMS_DMA_REGION23_HIGH_REG register
+ *  Region23 end address configuration register
+ */
+#define PMS_DMA_REGION23_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xc4)
+/** PMS_DMA_REGION23_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region23.
+ */
+#define PMS_DMA_REGION23_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION23_HIGH_M  (PMS_DMA_REGION23_HIGH_V << PMS_DMA_REGION23_HIGH_S)
+#define PMS_DMA_REGION23_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION23_HIGH_S  12
+
+/** PMS_DMA_REGION24_LOW_REG register
+ *  Region24 start address configuration register
+ */
+#define PMS_DMA_REGION24_LOW_REG (DR_REG_DMA_PMS_BASE + 0xc8)
+/** PMS_DMA_REGION24_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region24.
+ */
+#define PMS_DMA_REGION24_LOW    0x000FFFFFU
+#define PMS_DMA_REGION24_LOW_M  (PMS_DMA_REGION24_LOW_V << PMS_DMA_REGION24_LOW_S)
+#define PMS_DMA_REGION24_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION24_LOW_S  12
+
+/** PMS_DMA_REGION24_HIGH_REG register
+ *  Region24 end address configuration register
+ */
+#define PMS_DMA_REGION24_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xcc)
+/** PMS_DMA_REGION24_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region24.
+ */
+#define PMS_DMA_REGION24_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION24_HIGH_M  (PMS_DMA_REGION24_HIGH_V << PMS_DMA_REGION24_HIGH_S)
+#define PMS_DMA_REGION24_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION24_HIGH_S  12
+
+/** PMS_DMA_REGION25_LOW_REG register
+ *  Region25 start address configuration register
+ */
+#define PMS_DMA_REGION25_LOW_REG (DR_REG_DMA_PMS_BASE + 0xd0)
+/** PMS_DMA_REGION25_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region25.
+ */
+#define PMS_DMA_REGION25_LOW    0x000FFFFFU
+#define PMS_DMA_REGION25_LOW_M  (PMS_DMA_REGION25_LOW_V << PMS_DMA_REGION25_LOW_S)
+#define PMS_DMA_REGION25_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION25_LOW_S  12
+
+/** PMS_DMA_REGION25_HIGH_REG register
+ *  Region25 end address configuration register
+ */
+#define PMS_DMA_REGION25_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xd4)
+/** PMS_DMA_REGION25_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region25.
+ */
+#define PMS_DMA_REGION25_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION25_HIGH_M  (PMS_DMA_REGION25_HIGH_V << PMS_DMA_REGION25_HIGH_S)
+#define PMS_DMA_REGION25_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION25_HIGH_S  12
+
+/** PMS_DMA_REGION26_LOW_REG register
+ *  Region26 start address configuration register
+ */
+#define PMS_DMA_REGION26_LOW_REG (DR_REG_DMA_PMS_BASE + 0xd8)
+/** PMS_DMA_REGION26_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region26.
+ */
+#define PMS_DMA_REGION26_LOW    0x000FFFFFU
+#define PMS_DMA_REGION26_LOW_M  (PMS_DMA_REGION26_LOW_V << PMS_DMA_REGION26_LOW_S)
+#define PMS_DMA_REGION26_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION26_LOW_S  12
+
+/** PMS_DMA_REGION26_HIGH_REG register
+ *  Region26 end address configuration register
+ */
+#define PMS_DMA_REGION26_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xdc)
+/** PMS_DMA_REGION26_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region26.
+ */
+#define PMS_DMA_REGION26_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION26_HIGH_M  (PMS_DMA_REGION26_HIGH_V << PMS_DMA_REGION26_HIGH_S)
+#define PMS_DMA_REGION26_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION26_HIGH_S  12
+
+/** PMS_DMA_REGION27_LOW_REG register
+ *  Region27 start address configuration register
+ */
+#define PMS_DMA_REGION27_LOW_REG (DR_REG_DMA_PMS_BASE + 0xe0)
+/** PMS_DMA_REGION27_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region27.
+ */
+#define PMS_DMA_REGION27_LOW    0x000FFFFFU
+#define PMS_DMA_REGION27_LOW_M  (PMS_DMA_REGION27_LOW_V << PMS_DMA_REGION27_LOW_S)
+#define PMS_DMA_REGION27_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION27_LOW_S  12
+
+/** PMS_DMA_REGION27_HIGH_REG register
+ *  Region27 end address configuration register
+ */
+#define PMS_DMA_REGION27_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xe4)
+/** PMS_DMA_REGION27_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region27.
+ */
+#define PMS_DMA_REGION27_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION27_HIGH_M  (PMS_DMA_REGION27_HIGH_V << PMS_DMA_REGION27_HIGH_S)
+#define PMS_DMA_REGION27_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION27_HIGH_S  12
+
+/** PMS_DMA_REGION28_LOW_REG register
+ *  Region28 start address configuration register
+ */
+#define PMS_DMA_REGION28_LOW_REG (DR_REG_DMA_PMS_BASE + 0xe8)
+/** PMS_DMA_REGION28_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region28.
+ */
+#define PMS_DMA_REGION28_LOW    0x000FFFFFU
+#define PMS_DMA_REGION28_LOW_M  (PMS_DMA_REGION28_LOW_V << PMS_DMA_REGION28_LOW_S)
+#define PMS_DMA_REGION28_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION28_LOW_S  12
+
+/** PMS_DMA_REGION28_HIGH_REG register
+ *  Region28 end address configuration register
+ */
+#define PMS_DMA_REGION28_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xec)
+/** PMS_DMA_REGION28_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region28.
+ */
+#define PMS_DMA_REGION28_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION28_HIGH_M  (PMS_DMA_REGION28_HIGH_V << PMS_DMA_REGION28_HIGH_S)
+#define PMS_DMA_REGION28_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION28_HIGH_S  12
+
+/** PMS_DMA_REGION29_LOW_REG register
+ *  Region29 start address configuration register
+ */
+#define PMS_DMA_REGION29_LOW_REG (DR_REG_DMA_PMS_BASE + 0xf0)
+/** PMS_DMA_REGION29_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region29.
+ */
+#define PMS_DMA_REGION29_LOW    0x000FFFFFU
+#define PMS_DMA_REGION29_LOW_M  (PMS_DMA_REGION29_LOW_V << PMS_DMA_REGION29_LOW_S)
+#define PMS_DMA_REGION29_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION29_LOW_S  12
+
+/** PMS_DMA_REGION29_HIGH_REG register
+ *  Region29 end address configuration register
+ */
+#define PMS_DMA_REGION29_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xf4)
+/** PMS_DMA_REGION29_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region29.
+ */
+#define PMS_DMA_REGION29_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION29_HIGH_M  (PMS_DMA_REGION29_HIGH_V << PMS_DMA_REGION29_HIGH_S)
+#define PMS_DMA_REGION29_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION29_HIGH_S  12
+
+/** PMS_DMA_REGION30_LOW_REG register
+ *  Region30 start address configuration register
+ */
+#define PMS_DMA_REGION30_LOW_REG (DR_REG_DMA_PMS_BASE + 0xf8)
+/** PMS_DMA_REGION30_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region30.
+ */
+#define PMS_DMA_REGION30_LOW    0x000FFFFFU
+#define PMS_DMA_REGION30_LOW_M  (PMS_DMA_REGION30_LOW_V << PMS_DMA_REGION30_LOW_S)
+#define PMS_DMA_REGION30_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION30_LOW_S  12
+
+/** PMS_DMA_REGION30_HIGH_REG register
+ *  Region30 end address configuration register
+ */
+#define PMS_DMA_REGION30_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xfc)
+/** PMS_DMA_REGION30_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region30.
+ */
+#define PMS_DMA_REGION30_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION30_HIGH_M  (PMS_DMA_REGION30_HIGH_V << PMS_DMA_REGION30_HIGH_S)
+#define PMS_DMA_REGION30_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION30_HIGH_S  12
+
+/** PMS_DMA_REGION31_LOW_REG register
+ *  Region31 start address configuration register
+ */
+#define PMS_DMA_REGION31_LOW_REG (DR_REG_DMA_PMS_BASE + 0x100)
+/** PMS_DMA_REGION31_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region31.
+ */
+#define PMS_DMA_REGION31_LOW    0x000FFFFFU
+#define PMS_DMA_REGION31_LOW_M  (PMS_DMA_REGION31_LOW_V << PMS_DMA_REGION31_LOW_S)
+#define PMS_DMA_REGION31_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION31_LOW_S  12
+
+/** PMS_DMA_REGION31_HIGH_REG register
+ *  Region31 end address configuration register
+ */
+#define PMS_DMA_REGION31_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x104)
+/** PMS_DMA_REGION31_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region31.
+ */
+#define PMS_DMA_REGION31_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION31_HIGH_M  (PMS_DMA_REGION31_HIGH_V << PMS_DMA_REGION31_HIGH_S)
+#define PMS_DMA_REGION31_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION31_HIGH_S  12
+
+/** PMS_DMA_GDMA_CH0_R_PMS_REG register
+ *  GDMA ch0 read permission control register
+ */
+#define PMS_DMA_GDMA_CH0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x108)
+/** PMS_DMA_GDMA_CH0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch0 to read 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_GDMA_CH0_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH0_R_PMS_M  (PMS_DMA_GDMA_CH0_R_PMS_V << PMS_DMA_GDMA_CH0_R_PMS_S)
+#define PMS_DMA_GDMA_CH0_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH0_R_PMS_S  0
+
+/** PMS_DMA_GDMA_CH0_W_PMS_REG register
+ *  GDMA ch0 write permission control register
+ */
+#define PMS_DMA_GDMA_CH0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x10c)
+/** PMS_DMA_GDMA_CH0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch0 to write 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_GDMA_CH0_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH0_W_PMS_M  (PMS_DMA_GDMA_CH0_W_PMS_V << PMS_DMA_GDMA_CH0_W_PMS_S)
+#define PMS_DMA_GDMA_CH0_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH0_W_PMS_S  0
+
+/** PMS_DMA_GDMA_CH1_R_PMS_REG register
+ *  GDMA ch1 read permission control register
+ */
+#define PMS_DMA_GDMA_CH1_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x110)
+/** PMS_DMA_GDMA_CH1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch1 to read 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_GDMA_CH1_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH1_R_PMS_M  (PMS_DMA_GDMA_CH1_R_PMS_V << PMS_DMA_GDMA_CH1_R_PMS_S)
+#define PMS_DMA_GDMA_CH1_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH1_R_PMS_S  0
+
+/** PMS_DMA_GDMA_CH1_W_PMS_REG register
+ *  GDMA ch1 write permission control register
+ */
+#define PMS_DMA_GDMA_CH1_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x114)
+/** PMS_DMA_GDMA_CH1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch1 to write 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_GDMA_CH1_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH1_W_PMS_M  (PMS_DMA_GDMA_CH1_W_PMS_V << PMS_DMA_GDMA_CH1_W_PMS_S)
+#define PMS_DMA_GDMA_CH1_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH1_W_PMS_S  0
+
+/** PMS_DMA_GDMA_CH2_R_PMS_REG register
+ *  GDMA ch2 read permission control register
+ */
+#define PMS_DMA_GDMA_CH2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x118)
+/** PMS_DMA_GDMA_CH2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch2 to read 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_GDMA_CH2_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH2_R_PMS_M  (PMS_DMA_GDMA_CH2_R_PMS_V << PMS_DMA_GDMA_CH2_R_PMS_S)
+#define PMS_DMA_GDMA_CH2_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH2_R_PMS_S  0
+
+/** PMS_DMA_GDMA_CH2_W_PMS_REG register
+ *  GDMA ch2 write permission control register
+ */
+#define PMS_DMA_GDMA_CH2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x11c)
+/** PMS_DMA_GDMA_CH2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch2 to write 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_GDMA_CH2_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH2_W_PMS_M  (PMS_DMA_GDMA_CH2_W_PMS_V << PMS_DMA_GDMA_CH2_W_PMS_S)
+#define PMS_DMA_GDMA_CH2_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH2_W_PMS_S  0
+
+/** PMS_DMA_GDMA_CH3_R_PMS_REG register
+ *  GDMA ch3 read permission control register
+ */
+#define PMS_DMA_GDMA_CH3_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x120)
+/** PMS_DMA_GDMA_CH3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch3 to read 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_GDMA_CH3_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH3_R_PMS_M  (PMS_DMA_GDMA_CH3_R_PMS_V << PMS_DMA_GDMA_CH3_R_PMS_S)
+#define PMS_DMA_GDMA_CH3_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH3_R_PMS_S  0
+
+/** PMS_DMA_GDMA_CH3_W_PMS_REG register
+ *  GDMA ch3 write permission control register
+ */
+#define PMS_DMA_GDMA_CH3_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x124)
+/** PMS_DMA_GDMA_CH3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch3 to write 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_GDMA_CH3_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH3_W_PMS_M  (PMS_DMA_GDMA_CH3_W_PMS_V << PMS_DMA_GDMA_CH3_W_PMS_S)
+#define PMS_DMA_GDMA_CH3_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH3_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_ADC_R_PMS_REG register
+ *  GDMA-AHB ADC read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x128)
+/** PMS_DMA_AHB_PDMA_ADC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by ADC. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS_M  (PMS_DMA_AHB_PDMA_ADC_R_PMS_V << PMS_DMA_AHB_PDMA_ADC_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_ADC_W_PMS_REG register
+ *  GDMA-AHB ADC write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x12c)
+/** PMS_DMA_AHB_PDMA_ADC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by ADC. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS_M  (PMS_DMA_AHB_PDMA_ADC_W_PMS_V << PMS_DMA_AHB_PDMA_ADC_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S0_R_PMS_REG register
+ *  GDMA-AHB I2S0 read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x130)
+/** PMS_DMA_AHB_PDMA_I2S0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by I2S0. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_M  (PMS_DMA_AHB_PDMA_I2S0_R_PMS_V << PMS_DMA_AHB_PDMA_I2S0_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S0_W_PMS_REG register
+ *  GDMA-AHB I2S0 write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x134)
+/** PMS_DMA_AHB_PDMA_I2S0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by I2S0. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_M  (PMS_DMA_AHB_PDMA_I2S0_W_PMS_V << PMS_DMA_AHB_PDMA_I2S0_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S1_R_PMS_REG register
+ *  GDMA-AHB I2S1 read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x138)
+/** PMS_DMA_AHB_PDMA_I2S1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by I2S1. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_M  (PMS_DMA_AHB_PDMA_I2S1_R_PMS_V << PMS_DMA_AHB_PDMA_I2S1_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S1_W_PMS_REG register
+ *  GDMA-AHB I2S1 write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x13c)
+/** PMS_DMA_AHB_PDMA_I2S1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by I2S1. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_M  (PMS_DMA_AHB_PDMA_I2S1_W_PMS_V << PMS_DMA_AHB_PDMA_I2S1_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S2_R_PMS_REG register
+ *  GDMA-AHB I2S2 read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x140)
+/** PMS_DMA_AHB_PDMA_I2S2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by I2S2. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_M  (PMS_DMA_AHB_PDMA_I2S2_R_PMS_V << PMS_DMA_AHB_PDMA_I2S2_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S2_W_PMS_REG register
+ *  GDMA-AHB I2S2 write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x144)
+/** PMS_DMA_AHB_PDMA_I2S2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by I2S2. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_M  (PMS_DMA_AHB_PDMA_I2S2_W_PMS_V << PMS_DMA_AHB_PDMA_I2S2_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_REG register
+ *  GDMA-AHB I3C MST read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x148)
+/** PMS_DMA_AHB_PDMA_I3C_MST_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by I3C  master.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_M  (PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_V << PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_REG register
+ *  GDMA-AHB I3C MST write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x14c)
+/** PMS_DMA_AHB_PDMA_I3C_MST_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by I3C  master.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_M  (PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_V << PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_UHCI0_R_PMS_REG register
+ *  GDMA-AHB UHCI read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x150)
+/** PMS_DMA_AHB_PDMA_UHCI0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by UHCI. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_M  (PMS_DMA_AHB_PDMA_UHCI0_R_PMS_V << PMS_DMA_AHB_PDMA_UHCI0_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_UHCI0_W_PMS_REG register
+ *  GDMA-AHB UHCI write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x154)
+/** PMS_DMA_AHB_PDMA_UHCI0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by UHCI. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_M  (PMS_DMA_AHB_PDMA_UHCI0_W_PMS_V << PMS_DMA_AHB_PDMA_UHCI0_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_RMT_R_PMS_REG register
+ *  GDMA-AHB RMT read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x158)
+/** PMS_DMA_AHB_PDMA_RMT_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by RMT. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS_M  (PMS_DMA_AHB_PDMA_RMT_R_PMS_V << PMS_DMA_AHB_PDMA_RMT_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_RMT_W_PMS_REG register
+ *  GDMA-AHB RMT write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x170)
+/** PMS_DMA_AHB_PDMA_RMT_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by RMT. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS_M  (PMS_DMA_AHB_PDMA_RMT_W_PMS_V << PMS_DMA_AHB_PDMA_RMT_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_REG register
+ *  GDMA-AXI LCD_CAM read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x174)
+/** PMS_DMA_AXI_PDMA_LCDCAM_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by LCD_CAM. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_M  (PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_V << PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_REG register
+ *  GDMA-AXI LCD_CAM write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x178)
+/** PMS_DMA_AXI_PDMA_LCDCAM_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by LCD_CAM. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_M  (PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_V << PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_REG register
+ *  GDMA-AXI GPSPI2 read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x17c)
+/** PMS_DMA_AXI_PDMA_GPSPI2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by GP-SPI2. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_M  (PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_V << PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_REG register
+ *  GDMA-AXI GPSPI2 write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x180)
+/** PMS_DMA_AXI_PDMA_GPSPI2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by GP-SPI2. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_M  (PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_V << PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_REG register
+ *  GDMA-AXI GPSPI3 read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x184)
+/** PMS_DMA_AXI_PDMA_GPSPI3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by GP-SPI3. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_M  (PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_V << PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_REG register
+ *  AXI PDMA GPSPI3 write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x188)
+/** PMS_DMA_AXI_PDMA_GPSPI3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by GP-SPI3. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_M  (PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_V << PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_PARLIO_R_PMS_REG register
+ *  GDMA-AXI PARLIO read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x18c)
+/** PMS_DMA_AXI_PDMA_PARLIO_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by PARLIO
+ *  (Parallel IO Controller). Bit 0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_M  (PMS_DMA_AXI_PDMA_PARLIO_R_PMS_V << PMS_DMA_AXI_PDMA_PARLIO_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_PARLIO_W_PMS_REG register
+ *  GDMA-AXI PARLIO write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x190)
+/** PMS_DMA_AXI_PDMA_PARLIO_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by PARLIO. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_M  (PMS_DMA_AXI_PDMA_PARLIO_W_PMS_V << PMS_DMA_AXI_PDMA_PARLIO_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_AES_R_PMS_REG register
+ *  GDMA-AXI AES read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_AES_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x194)
+/** PMS_DMA_AXI_PDMA_AES_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by AES. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_AES_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_AES_R_PMS_M  (PMS_DMA_AXI_PDMA_AES_R_PMS_V << PMS_DMA_AXI_PDMA_AES_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_AES_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_AES_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_AES_W_PMS_REG register
+ *  GDMA-AXI AES write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_AES_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x198)
+/** PMS_DMA_AXI_PDMA_AES_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by AES. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_AES_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_AES_W_PMS_M  (PMS_DMA_AXI_PDMA_AES_W_PMS_V << PMS_DMA_AXI_PDMA_AES_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_AES_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_AES_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_SHA_R_PMS_REG register
+ *  GDMA-AXI SHA read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x19c)
+/** PMS_DMA_AXI_PDMA_SHA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by SHA. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS_M  (PMS_DMA_AXI_PDMA_SHA_R_PMS_V << PMS_DMA_AXI_PDMA_SHA_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_SHA_W_PMS_REG register
+ *  GDMA-AXI SHA write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x1a0)
+/** PMS_DMA_AXI_PDMA_SHA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by SHA. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS_M  (PMS_DMA_AXI_PDMA_SHA_W_PMS_V << PMS_DMA_AXI_PDMA_SHA_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS_S  0
+
+/** PMS_DMA_DMA2D_JPEG_PMS_R_REG register
+ *  2D-DMA JPEG read permission control register
+ */
+#define PMS_DMA_DMA2D_JPEG_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1a4)
+/** PMS_DMA_DMA2D_JPEG_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to read 32 address ranges requested by JPEG. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_DMA2D_JPEG_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_JPEG_R_PMS_M  (PMS_DMA_DMA2D_JPEG_R_PMS_V << PMS_DMA_DMA2D_JPEG_R_PMS_S)
+#define PMS_DMA_DMA2D_JPEG_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_JPEG_R_PMS_S  0
+
+/** PMS_DMA_DMA2D_JPEG_PMS_W_REG register
+ *  2D-DMA JPEG write permission control register
+ */
+#define PMS_DMA_DMA2D_JPEG_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1a8)
+/** PMS_DMA_DMA2D_JPEG_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to write 32 address ranges requested by JPEG. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_DMA2D_JPEG_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_JPEG_W_PMS_M  (PMS_DMA_DMA2D_JPEG_W_PMS_V << PMS_DMA_DMA2D_JPEG_W_PMS_S)
+#define PMS_DMA_DMA2D_JPEG_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_JPEG_W_PMS_S  0
+
+/** PMS_DMA_USB_PMS_R_REG register
+ *  High-speed USB 2.0 OTG read permission control register
+ */
+#define PMS_DMA_USB_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1ac)
+/** PMS_DMA_USB_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for high-speed USB 2.0 OTG to access 32 address ranges.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_USB_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_USB_R_PMS_M  (PMS_DMA_USB_R_PMS_V << PMS_DMA_USB_R_PMS_S)
+#define PMS_DMA_USB_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_USB_R_PMS_S  0
+
+/** PMS_DMA_USB_PMS_W_REG register
+ *  High-speed USB 2.0 OTG write permission control register
+ */
+#define PMS_DMA_USB_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1b0)
+/** PMS_DMA_USB_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for high-speed USB 2.0 OTG to access 32 address ranges.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_USB_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_USB_W_PMS_M  (PMS_DMA_USB_W_PMS_V << PMS_DMA_USB_W_PMS_S)
+#define PMS_DMA_USB_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_USB_W_PMS_S  0
+
+/** PMS_DMA_GMAC_PMS_R_REG register
+ *  EMAC read permission control register
+ */
+#define PMS_DMA_GMAC_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1b4)
+/** PMS_DMA_GMAC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for EMAC to access 32 address ranges. Bit 0 corresponds
+ *  to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_GMAC_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_GMAC_R_PMS_M  (PMS_DMA_GMAC_R_PMS_V << PMS_DMA_GMAC_R_PMS_S)
+#define PMS_DMA_GMAC_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GMAC_R_PMS_S  0
+
+/** PMS_DMA_GMAC_PMS_W_REG register
+ *  EMAC write permission control register
+ */
+#define PMS_DMA_GMAC_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1b8)
+/** PMS_DMA_GMAC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for EMAC to access 32 address ranges. Bit 0 corresponds
+ *  to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_GMAC_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_GMAC_W_PMS_M  (PMS_DMA_GMAC_W_PMS_V << PMS_DMA_GMAC_W_PMS_S)
+#define PMS_DMA_GMAC_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GMAC_W_PMS_S  0
+
+/** PMS_DMA_SDMMC_PMS_R_REG register
+ *  SDMMC read permission control register
+ */
+#define PMS_DMA_SDMMC_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1bc)
+/** PMS_DMA_SDMMC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for SDMMC to access 32 address ranges. Bit 0 corresponds
+ *  to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_SDMMC_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_SDMMC_R_PMS_M  (PMS_DMA_SDMMC_R_PMS_V << PMS_DMA_SDMMC_R_PMS_S)
+#define PMS_DMA_SDMMC_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_SDMMC_R_PMS_S  0
+
+/** PMS_DMA_SDMMC_PMS_W_REG register
+ *  SDMMC write permission control register
+ */
+#define PMS_DMA_SDMMC_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1c0)
+/** PMS_DMA_SDMMC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for SDMMC to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_SDMMC_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_SDMMC_W_PMS_M  (PMS_DMA_SDMMC_W_PMS_V << PMS_DMA_SDMMC_W_PMS_S)
+#define PMS_DMA_SDMMC_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_SDMMC_W_PMS_S  0
+
+/** PMS_DMA_USBOTG11_PMS_R_REG register
+ *  Full-speed USB 2.0 OTG full-speed read permission control register
+ */
+#define PMS_DMA_USBOTG11_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1c4)
+/** PMS_DMA_USBOTG11_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for full-speed USB 2.0 OTG to access 32 address ranges.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_USBOTG11_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_USBOTG11_R_PMS_M  (PMS_DMA_USBOTG11_R_PMS_V << PMS_DMA_USBOTG11_R_PMS_S)
+#define PMS_DMA_USBOTG11_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_USBOTG11_R_PMS_S  0
+
+/** PMS_DMA_USBOTG11_PMS_W_REG register
+ *  Full-speed USB 2.0 OTG full-speed write permission control register
+ */
+#define PMS_DMA_USBOTG11_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1c8)
+/** PMS_DMA_USBOTG11_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for full-speed USB 2.0 OTG to access 32 address ranges.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_USBOTG11_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_USBOTG11_W_PMS_M  (PMS_DMA_USBOTG11_W_PMS_V << PMS_DMA_USBOTG11_W_PMS_S)
+#define PMS_DMA_USBOTG11_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_USBOTG11_W_PMS_S  0
+
+/** PMS_DMA_TRACE0_PMS_R_REG register
+ *  TRACE0 read permission control register
+ */
+#define PMS_DMA_TRACE0_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1cc)
+/** PMS_DMA_TRACE0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for TRACE0 to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_TRACE0_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_TRACE0_R_PMS_M  (PMS_DMA_TRACE0_R_PMS_V << PMS_DMA_TRACE0_R_PMS_S)
+#define PMS_DMA_TRACE0_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_TRACE0_R_PMS_S  0
+
+/** PMS_DMA_TRACE0_PMS_W_REG register
+ *  TRACE0 write permission control register
+ */
+#define PMS_DMA_TRACE0_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1d0)
+/** PMS_DMA_TRACE0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for TRACE0 to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_TRACE0_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_TRACE0_W_PMS_M  (PMS_DMA_TRACE0_W_PMS_V << PMS_DMA_TRACE0_W_PMS_S)
+#define PMS_DMA_TRACE0_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_TRACE0_W_PMS_S  0
+
+/** PMS_DMA_TRACE1_PMS_R_REG register
+ *  TRACE1 read permission control register
+ */
+#define PMS_DMA_TRACE1_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1d4)
+/** PMS_DMA_TRACE1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for TRACE1 to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_TRACE1_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_TRACE1_R_PMS_M  (PMS_DMA_TRACE1_R_PMS_V << PMS_DMA_TRACE1_R_PMS_S)
+#define PMS_DMA_TRACE1_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_TRACE1_R_PMS_S  0
+
+/** PMS_DMA_TRACE1_PMS_W_REG register
+ *  TRACE1 write permission control register
+ */
+#define PMS_DMA_TRACE1_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1d8)
+/** PMS_DMA_TRACE1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for TRACE1 to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_TRACE1_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_TRACE1_W_PMS_M  (PMS_DMA_TRACE1_W_PMS_V << PMS_DMA_TRACE1_W_PMS_S)
+#define PMS_DMA_TRACE1_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_TRACE1_W_PMS_S  0
+
+/** PMS_DMA_L2MEM_MON_PMS_R_REG register
+ *  L2MEM Monitor read permission control register
+ */
+#define PMS_DMA_L2MEM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1dc)
+/** PMS_DMA_L2MEM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for L2MEM MON. Each bit corresponds to a region. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_L2MEM_MON_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_L2MEM_MON_R_PMS_M  (PMS_DMA_L2MEM_MON_R_PMS_V << PMS_DMA_L2MEM_MON_R_PMS_S)
+#define PMS_DMA_L2MEM_MON_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_L2MEM_MON_R_PMS_S  0
+
+/** PMS_DMA_L2MEM_MON_PMS_W_REG register
+ *  L2MEM Monitor write permission control register
+ */
+#define PMS_DMA_L2MEM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e0)
+/** PMS_DMA_L2MEM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for L2MEM monitor to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_L2MEM_MON_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_L2MEM_MON_W_PMS_M  (PMS_DMA_L2MEM_MON_W_PMS_V << PMS_DMA_L2MEM_MON_W_PMS_S)
+#define PMS_DMA_L2MEM_MON_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_L2MEM_MON_W_PMS_S  0
+
+/** PMS_DMA_SPM_MON_PMS_R_REG register
+ *  SPM Monitor read permission control register
+ */
+#define PMS_DMA_SPM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1e4)
+/** PMS_DMA_SPM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for SPM MON. Each bit corresponds to a region. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_SPM_MON_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_SPM_MON_R_PMS_M  (PMS_DMA_SPM_MON_R_PMS_V << PMS_DMA_SPM_MON_R_PMS_S)
+#define PMS_DMA_SPM_MON_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_SPM_MON_R_PMS_S  0
+
+/** PMS_DMA_SPM_MON_PMS_W_REG register
+ *  SPM Monitor write permission control register
+ */
+#define PMS_DMA_SPM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e8)
+/** PMS_DMA_SPM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for SPM monitor to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_SPM_MON_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_SPM_MON_W_PMS_M  (PMS_DMA_SPM_MON_W_PMS_V << PMS_DMA_SPM_MON_W_PMS_S)
+#define PMS_DMA_SPM_MON_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_SPM_MON_W_PMS_S  0
+
+/** PMS_DMA_H264_PMS_R_REG register
+ *  H264 DMA read permission control register
+ */
+#define PMS_DMA_H264_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1fc)
+/** PMS_DMA_H264_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for H264 DMA to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_H264_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_H264_R_PMS_M  (PMS_DMA_H264_R_PMS_V << PMS_DMA_H264_R_PMS_S)
+#define PMS_DMA_H264_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_H264_R_PMS_S  0
+
+/** PMS_DMA_H264_PMS_W_REG register
+ *  H264 DMA write permission control register
+ */
+#define PMS_DMA_H264_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x200)
+/** PMS_DMA_H264_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for H264 DMA to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_H264_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_H264_W_PMS_M  (PMS_DMA_H264_W_PMS_V << PMS_DMA_H264_W_PMS_S)
+#define PMS_DMA_H264_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_H264_W_PMS_S  0
+
+/** PMS_DMA_DMA2D_PPA_PMS_R_REG register
+ *  2D-DMA PPA read permission control register
+ */
+#define PMS_DMA_DMA2D_PPA_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x204)
+/** PMS_DMA_DMA2D_PPA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to read 32 address ranges requested by PPA
+ *  (Pixel-Processing Accelerator). Bit 0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_DMA2D_PPA_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_PPA_R_PMS_M  (PMS_DMA_DMA2D_PPA_R_PMS_V << PMS_DMA_DMA2D_PPA_R_PMS_S)
+#define PMS_DMA_DMA2D_PPA_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_PPA_R_PMS_S  0
+
+/** PMS_DMA_DMA2D_PPA_PMS_W_REG register
+ *  2D-DMA PPA write permission control register
+ */
+#define PMS_DMA_DMA2D_PPA_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x208)
+/** PMS_DMA_DMA2D_PPA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to write 32 address ranges requested by PPA. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_DMA2D_PPA_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_PPA_W_PMS_M  (PMS_DMA_DMA2D_PPA_W_PMS_V << PMS_DMA_DMA2D_PPA_W_PMS_S)
+#define PMS_DMA_DMA2D_PPA_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_PPA_W_PMS_S  0
+
+/** PMS_DMA_DMA2D_DUMMY_PMS_R_REG register
+ *  2D-DMA dummy read permission control register
+ */
+#define PMS_DMA_DMA2D_DUMMY_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x20c)
+/** PMS_DMA_DMA2D_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to read 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_DMA2D_DUMMY_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_DUMMY_R_PMS_M  (PMS_DMA_DMA2D_DUMMY_R_PMS_V << PMS_DMA_DMA2D_DUMMY_R_PMS_S)
+#define PMS_DMA_DMA2D_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_DUMMY_R_PMS_S  0
+
+/** PMS_DMA_DMA2D_DUMMY_PMS_W_REG register
+ *  2D-DMA dummy write permission control register
+ */
+#define PMS_DMA_DMA2D_DUMMY_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x210)
+/** PMS_DMA_DMA2D_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to write 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_DMA2D_DUMMY_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_DUMMY_W_PMS_M  (PMS_DMA_DMA2D_DUMMY_W_PMS_V << PMS_DMA_DMA2D_DUMMY_W_PMS_S)
+#define PMS_DMA_DMA2D_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_DUMMY_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_DUMMY_R_PMS_REG register
+ *  GDMA-AHB dummy read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x214)
+/** PMS_DMA_AHB_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_M  (PMS_DMA_AHB_PDMA_DUMMY_R_PMS_V << PMS_DMA_AHB_PDMA_DUMMY_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_DUMMY_W_PMS_REG register
+ *  GDMA-AHB dummy write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x218)
+/** PMS_DMA_AHB_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_M  (PMS_DMA_AHB_PDMA_DUMMY_W_PMS_V << PMS_DMA_AHB_PDMA_DUMMY_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_DUMMY_R_PMS_REG register
+ *  GDMA-AXI dummy read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x21c)
+/** PMS_DMA_AXI_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_M  (PMS_DMA_AXI_PDMA_DUMMY_R_PMS_V << PMS_DMA_AXI_PDMA_DUMMY_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_DUMMY_W_PMS_REG register
+ *  GDMA-AXI dummy write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x220)
+/** PMS_DMA_AXI_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_M  (PMS_DMA_AXI_PDMA_DUMMY_W_PMS_V << PMS_DMA_AXI_PDMA_DUMMY_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_struct.h
new file mode 100644
index 0000000000..4ccb8898e6
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/dma_pms_struct.h
@@ -0,0 +1,1919 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Tee version register. */
+/** Type of date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tee_date : R/W; bitpos: [31:0]; default: 539165460;
+         *  NA
+         */
+        uint32_t tee_date:32;
+    };
+    uint32_t val;
+} tee_dma_date_reg_t;
+
+
+/** Group: Tee regbank clock gating control register. */
+/** Type of clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_dma_clk_en_reg_t;
+
+
+/** Group: Tee region configuration registers. */
+/** Type of region0_low register
+ *  Region0 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region0_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region0 address low.
+         */
+        uint32_t region0_low:20;
+    };
+    uint32_t val;
+} tee_dma_region0_low_reg_t;
+
+/** Type of region0_high register
+ *  Region0 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region0_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region0 address high.
+         */
+        uint32_t region0_high:20;
+    };
+    uint32_t val;
+} tee_dma_region0_high_reg_t;
+
+/** Type of region1_low register
+ *  Region1 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region1_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region1 address low.
+         */
+        uint32_t region1_low:20;
+    };
+    uint32_t val;
+} tee_dma_region1_low_reg_t;
+
+/** Type of region1_high register
+ *  Region1 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region1_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region1 address high.
+         */
+        uint32_t region1_high:20;
+    };
+    uint32_t val;
+} tee_dma_region1_high_reg_t;
+
+/** Type of region2_low register
+ *  Region2 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region2_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region2 address low.
+         */
+        uint32_t region2_low:20;
+    };
+    uint32_t val;
+} tee_dma_region2_low_reg_t;
+
+/** Type of region2_high register
+ *  Region2 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region2_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region2 address high.
+         */
+        uint32_t region2_high:20;
+    };
+    uint32_t val;
+} tee_dma_region2_high_reg_t;
+
+/** Type of region3_low register
+ *  Region3 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region3_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region3 address low.
+         */
+        uint32_t region3_low:20;
+    };
+    uint32_t val;
+} tee_dma_region3_low_reg_t;
+
+/** Type of region3_high register
+ *  Region3 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region3_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region3 address high.
+         */
+        uint32_t region3_high:20;
+    };
+    uint32_t val;
+} tee_dma_region3_high_reg_t;
+
+/** Type of region4_low register
+ *  Region4 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region4_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region4 address low.
+         */
+        uint32_t region4_low:20;
+    };
+    uint32_t val;
+} tee_dma_region4_low_reg_t;
+
+/** Type of region4_high register
+ *  Region4 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region4_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region4 address high.
+         */
+        uint32_t region4_high:20;
+    };
+    uint32_t val;
+} tee_dma_region4_high_reg_t;
+
+/** Type of region5_low register
+ *  Region5 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region5_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region5 address low.
+         */
+        uint32_t region5_low:20;
+    };
+    uint32_t val;
+} tee_dma_region5_low_reg_t;
+
+/** Type of region5_high register
+ *  Region5 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region5_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region5 address high.
+         */
+        uint32_t region5_high:20;
+    };
+    uint32_t val;
+} tee_dma_region5_high_reg_t;
+
+/** Type of region6_low register
+ *  Region6 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region6_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region6 address low.
+         */
+        uint32_t region6_low:20;
+    };
+    uint32_t val;
+} tee_dma_region6_low_reg_t;
+
+/** Type of region6_high register
+ *  Region6 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region6_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region6 address high.
+         */
+        uint32_t region6_high:20;
+    };
+    uint32_t val;
+} tee_dma_region6_high_reg_t;
+
+/** Type of region7_low register
+ *  Region7 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region7_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region7 address low.
+         */
+        uint32_t region7_low:20;
+    };
+    uint32_t val;
+} tee_dma_region7_low_reg_t;
+
+/** Type of region7_high register
+ *  Region7 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region7_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region7 address high.
+         */
+        uint32_t region7_high:20;
+    };
+    uint32_t val;
+} tee_dma_region7_high_reg_t;
+
+/** Type of region8_low register
+ *  Region8 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region8_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region8 address low.
+         */
+        uint32_t region8_low:20;
+    };
+    uint32_t val;
+} tee_dma_region8_low_reg_t;
+
+/** Type of region8_high register
+ *  Region8 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region8_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region8 address high.
+         */
+        uint32_t region8_high:20;
+    };
+    uint32_t val;
+} tee_dma_region8_high_reg_t;
+
+/** Type of region9_low register
+ *  Region9 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region9_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region9 address low.
+         */
+        uint32_t region9_low:20;
+    };
+    uint32_t val;
+} tee_dma_region9_low_reg_t;
+
+/** Type of region9_high register
+ *  Region9 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region9_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region9 address high.
+         */
+        uint32_t region9_high:20;
+    };
+    uint32_t val;
+} tee_dma_region9_high_reg_t;
+
+/** Type of region10_low register
+ *  Region10 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region10_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region10 address low.
+         */
+        uint32_t region10_low:20;
+    };
+    uint32_t val;
+} tee_dma_region10_low_reg_t;
+
+/** Type of region10_high register
+ *  Region10 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region10_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region10 address high.
+         */
+        uint32_t region10_high:20;
+    };
+    uint32_t val;
+} tee_dma_region10_high_reg_t;
+
+/** Type of region11_low register
+ *  Region11 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region11_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region11 address low.
+         */
+        uint32_t region11_low:20;
+    };
+    uint32_t val;
+} tee_dma_region11_low_reg_t;
+
+/** Type of region11_high register
+ *  Region11 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region11_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region11 address high.
+         */
+        uint32_t region11_high:20;
+    };
+    uint32_t val;
+} tee_dma_region11_high_reg_t;
+
+/** Type of region12_low register
+ *  Region12 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region12_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region12 address low.
+         */
+        uint32_t region12_low:20;
+    };
+    uint32_t val;
+} tee_dma_region12_low_reg_t;
+
+/** Type of region12_high register
+ *  Region12 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region12_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region12 address high.
+         */
+        uint32_t region12_high:20;
+    };
+    uint32_t val;
+} tee_dma_region12_high_reg_t;
+
+/** Type of region13_low register
+ *  Region13 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region13_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region13 address low.
+         */
+        uint32_t region13_low:20;
+    };
+    uint32_t val;
+} tee_dma_region13_low_reg_t;
+
+/** Type of region13_high register
+ *  Region13 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region13_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region13 address high.
+         */
+        uint32_t region13_high:20;
+    };
+    uint32_t val;
+} tee_dma_region13_high_reg_t;
+
+/** Type of region14_low register
+ *  Region14 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region14_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region14 address low.
+         */
+        uint32_t region14_low:20;
+    };
+    uint32_t val;
+} tee_dma_region14_low_reg_t;
+
+/** Type of region14_high register
+ *  Region14 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region14_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region14 address high.
+         */
+        uint32_t region14_high:20;
+    };
+    uint32_t val;
+} tee_dma_region14_high_reg_t;
+
+/** Type of region15_low register
+ *  Region15 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region15_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region15 address low.
+         */
+        uint32_t region15_low:20;
+    };
+    uint32_t val;
+} tee_dma_region15_low_reg_t;
+
+/** Type of region15_high register
+ *  Region15 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region15_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region15 address high.
+         */
+        uint32_t region15_high:20;
+    };
+    uint32_t val;
+} tee_dma_region15_high_reg_t;
+
+/** Type of region16_low register
+ *  Region16 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region16_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region16 address low.
+         */
+        uint32_t region16_low:20;
+    };
+    uint32_t val;
+} tee_dma_region16_low_reg_t;
+
+/** Type of region16_high register
+ *  Region16 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region16_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region16 address high.
+         */
+        uint32_t region16_high:20;
+    };
+    uint32_t val;
+} tee_dma_region16_high_reg_t;
+
+/** Type of region17_low register
+ *  Region17 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region17_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region17 address low.
+         */
+        uint32_t region17_low:20;
+    };
+    uint32_t val;
+} tee_dma_region17_low_reg_t;
+
+/** Type of region17_high register
+ *  Region17 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region17_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region17 address high.
+         */
+        uint32_t region17_high:20;
+    };
+    uint32_t val;
+} tee_dma_region17_high_reg_t;
+
+/** Type of region18_low register
+ *  Region18 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region18_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region18 address low.
+         */
+        uint32_t region18_low:20;
+    };
+    uint32_t val;
+} tee_dma_region18_low_reg_t;
+
+/** Type of region18_high register
+ *  Region18 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region18_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region18 address high.
+         */
+        uint32_t region18_high:20;
+    };
+    uint32_t val;
+} tee_dma_region18_high_reg_t;
+
+/** Type of region19_low register
+ *  Region19 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region19_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region19 address low.
+         */
+        uint32_t region19_low:20;
+    };
+    uint32_t val;
+} tee_dma_region19_low_reg_t;
+
+/** Type of region19_high register
+ *  Region19 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region19_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region19 address high.
+         */
+        uint32_t region19_high:20;
+    };
+    uint32_t val;
+} tee_dma_region19_high_reg_t;
+
+/** Type of region20_low register
+ *  Region20 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region20_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region20 address low.
+         */
+        uint32_t region20_low:20;
+    };
+    uint32_t val;
+} tee_dma_region20_low_reg_t;
+
+/** Type of region20_high register
+ *  Region20 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region20_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region20 address high.
+         */
+        uint32_t region20_high:20;
+    };
+    uint32_t val;
+} tee_dma_region20_high_reg_t;
+
+/** Type of region21_low register
+ *  Region21 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region21_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region21 address low.
+         */
+        uint32_t region21_low:20;
+    };
+    uint32_t val;
+} tee_dma_region21_low_reg_t;
+
+/** Type of region21_high register
+ *  Region21 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region21_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region21 address high.
+         */
+        uint32_t region21_high:20;
+    };
+    uint32_t val;
+} tee_dma_region21_high_reg_t;
+
+/** Type of region22_low register
+ *  Region22 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region22_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region22 address low.
+         */
+        uint32_t region22_low:20;
+    };
+    uint32_t val;
+} tee_dma_region22_low_reg_t;
+
+/** Type of region22_high register
+ *  Region22 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region22_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region22 address high.
+         */
+        uint32_t region22_high:20;
+    };
+    uint32_t val;
+} tee_dma_region22_high_reg_t;
+
+/** Type of region23_low register
+ *  Region23 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region23_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region23 address low.
+         */
+        uint32_t region23_low:20;
+    };
+    uint32_t val;
+} tee_dma_region23_low_reg_t;
+
+/** Type of region23_high register
+ *  Region23 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region23_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region23 address high.
+         */
+        uint32_t region23_high:20;
+    };
+    uint32_t val;
+} tee_dma_region23_high_reg_t;
+
+/** Type of region24_low register
+ *  Region24 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region24_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region24 address low.
+         */
+        uint32_t region24_low:20;
+    };
+    uint32_t val;
+} tee_dma_region24_low_reg_t;
+
+/** Type of region24_high register
+ *  Region24 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region24_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region24 address high.
+         */
+        uint32_t region24_high:20;
+    };
+    uint32_t val;
+} tee_dma_region24_high_reg_t;
+
+/** Type of region25_low register
+ *  Region25 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region25_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region25 address low.
+         */
+        uint32_t region25_low:20;
+    };
+    uint32_t val;
+} tee_dma_region25_low_reg_t;
+
+/** Type of region25_high register
+ *  Region25 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region25_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region25 address high.
+         */
+        uint32_t region25_high:20;
+    };
+    uint32_t val;
+} tee_dma_region25_high_reg_t;
+
+/** Type of region26_low register
+ *  Region26 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region26_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region26 address low.
+         */
+        uint32_t region26_low:20;
+    };
+    uint32_t val;
+} tee_dma_region26_low_reg_t;
+
+/** Type of region26_high register
+ *  Region26 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region26_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region26 address high.
+         */
+        uint32_t region26_high:20;
+    };
+    uint32_t val;
+} tee_dma_region26_high_reg_t;
+
+/** Type of region27_low register
+ *  Region27 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region27_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region27 address low.
+         */
+        uint32_t region27_low:20;
+    };
+    uint32_t val;
+} tee_dma_region27_low_reg_t;
+
+/** Type of region27_high register
+ *  Region27 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region27_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region27 address high.
+         */
+        uint32_t region27_high:20;
+    };
+    uint32_t val;
+} tee_dma_region27_high_reg_t;
+
+/** Type of region28_low register
+ *  Region28 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region28_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region28 address low.
+         */
+        uint32_t region28_low:20;
+    };
+    uint32_t val;
+} tee_dma_region28_low_reg_t;
+
+/** Type of region28_high register
+ *  Region28 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region28_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region28 address high.
+         */
+        uint32_t region28_high:20;
+    };
+    uint32_t val;
+} tee_dma_region28_high_reg_t;
+
+/** Type of region29_low register
+ *  Region29 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region29_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region29 address low.
+         */
+        uint32_t region29_low:20;
+    };
+    uint32_t val;
+} tee_dma_region29_low_reg_t;
+
+/** Type of region29_high register
+ *  Region29 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region29_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region29 address high.
+         */
+        uint32_t region29_high:20;
+    };
+    uint32_t val;
+} tee_dma_region29_high_reg_t;
+
+/** Type of region30_low register
+ *  Region30 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region30_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region30 address low.
+         */
+        uint32_t region30_low:20;
+    };
+    uint32_t val;
+} tee_dma_region30_low_reg_t;
+
+/** Type of region30_high register
+ *  Region30 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region30_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region30 address high.
+         */
+        uint32_t region30_high:20;
+    };
+    uint32_t val;
+} tee_dma_region30_high_reg_t;
+
+/** Type of region31_low register
+ *  Region31 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region31_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region31 address low.
+         */
+        uint32_t region31_low:20;
+    };
+    uint32_t val;
+} tee_dma_region31_low_reg_t;
+
+/** Type of region31_high register
+ *  Region31 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region31_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region31 address high.
+         */
+        uint32_t region31_high:20;
+    };
+    uint32_t val;
+} tee_dma_region31_high_reg_t;
+
+
+/** Group: Tee permission control registers. */
+/** Type of gmda_ch0_r_pms register
+ *  GDMA ch0 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch0_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch0 read permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch0_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch0_r_pms_reg_t;
+
+/** Type of gmda_ch0_w_pms register
+ *  GDMA ch0 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch0_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch0 write permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch0_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch0_w_pms_reg_t;
+
+/** Type of gmda_ch1_r_pms register
+ *  GDMA ch1 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch1_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch1 read permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch1_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch1_r_pms_reg_t;
+
+/** Type of gmda_ch1_w_pms register
+ *  GDMA ch1 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch1_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch1 write permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch1_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch1_w_pms_reg_t;
+
+/** Type of gmda_ch2_r_pms register
+ *  GDMA ch2 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch2_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch2 read permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch2_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch2_r_pms_reg_t;
+
+/** Type of gmda_ch2_w_pms register
+ *  GDMA ch2 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch2_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch2 write permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch2_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch2_w_pms_reg_t;
+
+/** Type of gmda_ch3_r_pms register
+ *  GDMA ch3 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch3_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch3 read permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch3_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch3_r_pms_reg_t;
+
+/** Type of gmda_ch3_w_pms register
+ *  GDMA ch3 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch3_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch3 write permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch3_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch3_w_pms_reg_t;
+
+/** Type of ahb_pdma_adc_r_pms register
+ *  AHB PDMA adc read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_adc_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA adc read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_adc_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_adc_r_pms_reg_t;
+
+/** Type of ahb_pdma_adc_w_pms register
+ *  AHB PDMA adc write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_adc_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA adc write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_adc_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_adc_w_pms_reg_t;
+
+/** Type of ahb_pdma_i2s0_r_pms register
+ *  AHB PDMA i2s0 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s0_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s0 read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s0_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s0_r_pms_reg_t;
+
+/** Type of ahb_pdma_i2s0_w_pms register
+ *  AHB PDMA i2s0 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s0_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s0 write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s0_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s0_w_pms_reg_t;
+
+/** Type of ahb_pdma_i2s1_r_pms register
+ *  AHB PDMA i2s1 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s1_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s1 read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s1_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s1_r_pms_reg_t;
+
+/** Type of ahb_pdma_i2s1_w_pms register
+ *  AHB PDMA i2s1 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s1_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s1 write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s1_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s1_w_pms_reg_t;
+
+/** Type of ahb_pdma_i2s2_r_pms register
+ *  AHB PDMA i2s2 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s2_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s2 read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s2_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s2_r_pms_reg_t;
+
+/** Type of ahb_pdma_i2s2_w_pms register
+ *  AHB PDMA i2s2 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s2_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s2 write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s2_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s2_w_pms_reg_t;
+
+/** Type of ahb_pdma_i3c_mst_r_pms register
+ *  AHB PDMA i3s mst read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i3c_mst_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i3c mst read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i3c_mst_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i3c_mst_r_pms_reg_t;
+
+/** Type of ahb_pdma_i3c_mst_w_pms register
+ *  AHB PDMA i3c mst  write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i3c_mst_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i3c mst  write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i3c_mst_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i3c_mst_w_pms_reg_t;
+
+/** Type of ahb_pdma_uhci0_r_pms register
+ *  AHB PDMA uhci0 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_uhci0_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA uhci0 read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_uhci0_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_uhci0_r_pms_reg_t;
+
+/** Type of ahb_pdma_uhci0_w_pms register
+ *  AHB PDMA uhci0 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_uhci0_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA uhci0 write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_uhci0_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_uhci0_w_pms_reg_t;
+
+/** Type of ahb_pdma_rmt_r_pms register
+ *  AHB PDMA rmt read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_rmt_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA rmt read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_rmt_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_rmt_r_pms_reg_t;
+
+/** Type of ahb_pdma_rmt_w_pms register
+ *  AHB PDMA rmt write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_rmt_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA rmt write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_rmt_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_rmt_w_pms_reg_t;
+
+/** Type of axi_pdma_lcdcam_r_pms register
+ *  AXI PDMA lcdcam read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_lcdcam_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA lcdcam read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_lcdcam_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_lcdcam_r_pms_reg_t;
+
+/** Type of axi_pdma_lcdcam_w_pms register
+ *  AXI PDMA lcdcam write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_lcdcam_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA lcdcam write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_lcdcam_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_lcdcam_w_pms_reg_t;
+
+/** Type of axi_pdma_gpspi2_r_pms register
+ *  AXI PDMA gpspi2 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_gpspi2_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA gpspi2 read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_gpspi2_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_gpspi2_r_pms_reg_t;
+
+/** Type of axi_pdma_gpspi2_w_pms register
+ *  AXI PDMA gpspi2 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_gpspi2_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA gpspi2 write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_gpspi2_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_gpspi2_w_pms_reg_t;
+
+/** Type of axi_pdma_gpspi3_r_pms register
+ *  AXI PDMA gpspi3 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_gpspi3_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA gpspi3 read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_gpspi3_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_gpspi3_r_pms_reg_t;
+
+/** Type of axi_pdma_gpspi3_w_pms register
+ *  AXI PDMA gpspi3 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_gpspi3_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA gpspi3 write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_gpspi3_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_gpspi3_w_pms_reg_t;
+
+/** Type of axi_pdma_parlio_r_pms register
+ *  AXI PDMA parl io read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_parlio_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA parl io read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_parlio_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_parlio_r_pms_reg_t;
+
+/** Type of axi_pdma_parlio_w_pms register
+ *  AXI PDMA parl io write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_parlio_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA parl io write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_parlio_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_parlio_w_pms_reg_t;
+
+/** Type of axi_pdma_aes_r_pms register
+ *  AXI PDMA aes read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_aes_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA aes read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_aes_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_aes_r_pms_reg_t;
+
+/** Type of axi_pdma_aes_w_pms register
+ *  AXI PDMA aes write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_aes_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA aes write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_aes_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_aes_w_pms_reg_t;
+
+/** Type of axi_pdma_sha_r_pms register
+ *  AXI PDMA sha read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_sha_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA sha read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_sha_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_sha_r_pms_reg_t;
+
+/** Type of axi_pdma_sha_w_pms register
+ *  AXI PDMA sha write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_sha_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA sha write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_sha_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_sha_w_pms_reg_t;
+
+/** Type of dma2d_jpeg_pms_r register
+ *  DMA2D JPEG read permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_jpeg_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D JPEG read permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_jpeg_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_jpeg_pms_r_reg_t;
+
+/** Type of dma2d_jpeg_pms_w register
+ *  DMA2D JPEG write permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_jpeg_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D  JPEG write permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_jpeg_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_jpeg_pms_w_reg_t;
+
+/** Type of usb_pms_r register
+ *  USB read permission control registers.
+ */
+typedef union {
+    struct {
+        /** usb_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  USB read permission control, each bit corresponds to a region.
+         */
+        uint32_t usb_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_usb_pms_r_reg_t;
+
+/** Type of usb_pms_w register
+ *  USB write permission control registers.
+ */
+typedef union {
+    struct {
+        /** usb_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  USB write permission control, each bit corresponds to a region.
+         */
+        uint32_t usb_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_usb_pms_w_reg_t;
+
+/** Type of gmac_pms_r register
+ *  GMAC read permission control registers.
+ */
+typedef union {
+    struct {
+        /** gmac_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GMAC read permission control, each bit corresponds to a region.
+         */
+        uint32_t gmac_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmac_pms_r_reg_t;
+
+/** Type of gmac_pms_w register
+ *  GMAC write permission control registers.
+ */
+typedef union {
+    struct {
+        /** gmac_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GMAC write permission control, each bit corresponds to a region.
+         */
+        uint32_t gmac_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmac_pms_w_reg_t;
+
+/** Type of sdmmc_pms_r register
+ *  SDMMC read permission control registers.
+ */
+typedef union {
+    struct {
+        /** sdmmc_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  SDMMC read permission control, each bit corresponds to a region.
+         */
+        uint32_t sdmmc_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_sdmmc_pms_r_reg_t;
+
+/** Type of sdmmc_pms_w register
+ *  SDMMC write permission control registers.
+ */
+typedef union {
+    struct {
+        /** sdmmc_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  SDMMC write permission control, each bit corresponds to a region.
+         */
+        uint32_t sdmmc_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_sdmmc_pms_w_reg_t;
+
+/** Type of usbotg11_pms_r register
+ *  USBOTG11 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** usbotg11_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  USBOTG11 read permission control, each bit corresponds to a region.
+         */
+        uint32_t usbotg11_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_usbotg11_pms_r_reg_t;
+
+/** Type of usbotg11_pms_w register
+ *  USBOTG11 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** usbotg11_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  USBOTG11 write permission control, each bit corresponds to a region.
+         */
+        uint32_t usbotg11_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_usbotg11_pms_w_reg_t;
+
+/** Type of trace0_pms_r register
+ *  TRACE0 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** trace0_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TRACE0 read permission control, each bit corresponds to a region.
+         */
+        uint32_t trace0_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_trace0_pms_r_reg_t;
+
+/** Type of trace0_pms_w register
+ *  TRACE0 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** trace0_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TRACE0 write permission control, each bit corresponds to a region.
+         */
+        uint32_t trace0_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_trace0_pms_w_reg_t;
+
+/** Type of trace1_pms_r register
+ *  TRACE1 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** trace1_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TRACE1 read permission control, each bit corresponds to a region.
+         */
+        uint32_t trace1_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_trace1_pms_r_reg_t;
+
+/** Type of trace1_pms_w register
+ *  TRACE1 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** trace1_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TRACE1 write permission control, each bit corresponds to a region.
+         */
+        uint32_t trace1_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_trace1_pms_w_reg_t;
+
+/** Type of l2mem_mon_pms_r register
+ *  L2MEM MON read permission control registers.
+ */
+typedef union {
+    struct {
+        /** l2mem_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  L2MEM MON read permission control, each bit corresponds to a region.
+         */
+        uint32_t l2mem_mon_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_l2mem_mon_pms_r_reg_t;
+
+/** Type of l2mem_mon_pms_w register
+ *  L2MEM MON write permission control registers.
+ */
+typedef union {
+    struct {
+        /** l2mem_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  L2MEM MON write permission control, each bit corresponds to a region.
+         */
+        uint32_t l2mem_mon_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_l2mem_mon_pms_w_reg_t;
+
+/** Type of tcm_mon_pms_r register
+ *  TCM MON read permission control registers.
+ */
+typedef union {
+    struct {
+        /** tcm_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TCM MON read permission control, each bit corresponds to a region.
+         */
+        uint32_t tcm_mon_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_tcm_mon_pms_r_reg_t;
+
+/** Type of tcm_mon_pms_w register
+ *  TCM MON write permission control registers.
+ */
+typedef union {
+    struct {
+        /** tcm_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TCM MON write permission control, each bit corresponds to a region.
+         */
+        uint32_t tcm_mon_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_tcm_mon_pms_w_reg_t;
+
+/** Type of regdma_pms_r register
+ *  REGDMA read permission control registers.
+ */
+typedef union {
+    struct {
+        /** regdma_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  REGDMA read permission control, each bit corresponds to a region.
+         */
+        uint32_t regdma_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_regdma_pms_r_reg_t;
+
+/** Type of regdma_pms_w register
+ *  REGDMA write permission control registers.
+ */
+typedef union {
+    struct {
+        /** regdma_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  REGDMA write permission control, each bit corresponds to a region.
+         */
+        uint32_t regdma_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_regdma_pms_w_reg_t;
+
+/** Type of h264_pms_r register
+ *  H264 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** h264_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  H264 read permission control, each bit corresponds to a region.
+         */
+        uint32_t h264_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_h264_pms_r_reg_t;
+
+/** Type of h264_pms_w register
+ *  H264 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** h264_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  H264 write permission control, each bit corresponds to a region.
+         */
+        uint32_t h264_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_h264_pms_w_reg_t;
+
+/** Type of dma2d_ppa_pms_r register
+ *  DMA2D PPA read permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_ppa_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D PPA  read permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_ppa_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_ppa_pms_r_reg_t;
+
+/** Type of dma2d_ppa_pms_w register
+ *  DMA2D PPA  write permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_ppa_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D  PPA write permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_ppa_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_ppa_pms_w_reg_t;
+
+/** Type of dma2d_dummy_pms_r register
+ *  DMA2D dummy read permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_dummy_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D dummy  read permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_dummy_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_dummy_pms_r_reg_t;
+
+/** Type of dma2d_dummy_pms_w register
+ *  DMA2D dummy  write permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_dummy_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D dummy  write permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_dummy_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_dummy_pms_w_reg_t;
+
+/** Type of ahb_pdma_dummy_r_pms register
+ *  AHB PDMA dummy read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_dummy_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA dummy read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_dummy_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_dummy_r_pms_reg_t;
+
+/** Type of ahb_pdma_dummy_w_pms register
+ *  AHB PDMA dummy write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_dummy_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA dummy write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_dummy_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_dummy_w_pms_reg_t;
+
+/** Type of axi_pdma_dummy_r_pms register
+ *  AXI PDMA dummy read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_dummy_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA dummy read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_dummy_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_dummy_r_pms_reg_t;
+
+/** Type of axi_pdma_dummy_w_pms register
+ *  AXI PDMA dummy write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_dummy_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA dummy write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_dummy_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_dummy_w_pms_reg_t;
+
+
+typedef struct {
+    volatile tee_dma_date_reg_t date;
+    volatile tee_dma_clk_en_reg_t clk_en;
+    volatile tee_dma_region0_low_reg_t region0_low;
+    volatile tee_dma_region0_high_reg_t region0_high;
+    volatile tee_dma_region1_low_reg_t region1_low;
+    volatile tee_dma_region1_high_reg_t region1_high;
+    volatile tee_dma_region2_low_reg_t region2_low;
+    volatile tee_dma_region2_high_reg_t region2_high;
+    volatile tee_dma_region3_low_reg_t region3_low;
+    volatile tee_dma_region3_high_reg_t region3_high;
+    volatile tee_dma_region4_low_reg_t region4_low;
+    volatile tee_dma_region4_high_reg_t region4_high;
+    volatile tee_dma_region5_low_reg_t region5_low;
+    volatile tee_dma_region5_high_reg_t region5_high;
+    volatile tee_dma_region6_low_reg_t region6_low;
+    volatile tee_dma_region6_high_reg_t region6_high;
+    volatile tee_dma_region7_low_reg_t region7_low;
+    volatile tee_dma_region7_high_reg_t region7_high;
+    volatile tee_dma_region8_low_reg_t region8_low;
+    volatile tee_dma_region8_high_reg_t region8_high;
+    volatile tee_dma_region9_low_reg_t region9_low;
+    volatile tee_dma_region9_high_reg_t region9_high;
+    volatile tee_dma_region10_low_reg_t region10_low;
+    volatile tee_dma_region10_high_reg_t region10_high;
+    volatile tee_dma_region11_low_reg_t region11_low;
+    volatile tee_dma_region11_high_reg_t region11_high;
+    volatile tee_dma_region12_low_reg_t region12_low;
+    volatile tee_dma_region12_high_reg_t region12_high;
+    volatile tee_dma_region13_low_reg_t region13_low;
+    volatile tee_dma_region13_high_reg_t region13_high;
+    volatile tee_dma_region14_low_reg_t region14_low;
+    volatile tee_dma_region14_high_reg_t region14_high;
+    volatile tee_dma_region15_low_reg_t region15_low;
+    volatile tee_dma_region15_high_reg_t region15_high;
+    volatile tee_dma_region16_low_reg_t region16_low;
+    volatile tee_dma_region16_high_reg_t region16_high;
+    volatile tee_dma_region17_low_reg_t region17_low;
+    volatile tee_dma_region17_high_reg_t region17_high;
+    volatile tee_dma_region18_low_reg_t region18_low;
+    volatile tee_dma_region18_high_reg_t region18_high;
+    volatile tee_dma_region19_low_reg_t region19_low;
+    volatile tee_dma_region19_high_reg_t region19_high;
+    volatile tee_dma_region20_low_reg_t region20_low;
+    volatile tee_dma_region20_high_reg_t region20_high;
+    volatile tee_dma_region21_low_reg_t region21_low;
+    volatile tee_dma_region21_high_reg_t region21_high;
+    volatile tee_dma_region22_low_reg_t region22_low;
+    volatile tee_dma_region22_high_reg_t region22_high;
+    volatile tee_dma_region23_low_reg_t region23_low;
+    volatile tee_dma_region23_high_reg_t region23_high;
+    volatile tee_dma_region24_low_reg_t region24_low;
+    volatile tee_dma_region24_high_reg_t region24_high;
+    volatile tee_dma_region25_low_reg_t region25_low;
+    volatile tee_dma_region25_high_reg_t region25_high;
+    volatile tee_dma_region26_low_reg_t region26_low;
+    volatile tee_dma_region26_high_reg_t region26_high;
+    volatile tee_dma_region27_low_reg_t region27_low;
+    volatile tee_dma_region27_high_reg_t region27_high;
+    volatile tee_dma_region28_low_reg_t region28_low;
+    volatile tee_dma_region28_high_reg_t region28_high;
+    volatile tee_dma_region29_low_reg_t region29_low;
+    volatile tee_dma_region29_high_reg_t region29_high;
+    volatile tee_dma_region30_low_reg_t region30_low;
+    volatile tee_dma_region30_high_reg_t region30_high;
+    volatile tee_dma_region31_low_reg_t region31_low;
+    volatile tee_dma_region31_high_reg_t region31_high;
+    volatile tee_dma_gmda_ch0_r_pms_reg_t gmda_ch0_r_pms;
+    volatile tee_dma_gmda_ch0_w_pms_reg_t gmda_ch0_w_pms;
+    volatile tee_dma_gmda_ch1_r_pms_reg_t gmda_ch1_r_pms;
+    volatile tee_dma_gmda_ch1_w_pms_reg_t gmda_ch1_w_pms;
+    volatile tee_dma_gmda_ch2_r_pms_reg_t gmda_ch2_r_pms;
+    volatile tee_dma_gmda_ch2_w_pms_reg_t gmda_ch2_w_pms;
+    volatile tee_dma_gmda_ch3_r_pms_reg_t gmda_ch3_r_pms;
+    volatile tee_dma_gmda_ch3_w_pms_reg_t gmda_ch3_w_pms;
+    volatile tee_dma_ahb_pdma_adc_r_pms_reg_t ahb_pdma_adc_r_pms;
+    volatile tee_dma_ahb_pdma_adc_w_pms_reg_t ahb_pdma_adc_w_pms;
+    volatile tee_dma_ahb_pdma_i2s0_r_pms_reg_t ahb_pdma_i2s0_r_pms;
+    volatile tee_dma_ahb_pdma_i2s0_w_pms_reg_t ahb_pdma_i2s0_w_pms;
+    volatile tee_dma_ahb_pdma_i2s1_r_pms_reg_t ahb_pdma_i2s1_r_pms;
+    volatile tee_dma_ahb_pdma_i2s1_w_pms_reg_t ahb_pdma_i2s1_w_pms;
+    volatile tee_dma_ahb_pdma_i2s2_r_pms_reg_t ahb_pdma_i2s2_r_pms;
+    volatile tee_dma_ahb_pdma_i2s2_w_pms_reg_t ahb_pdma_i2s2_w_pms;
+    volatile tee_dma_ahb_pdma_i3c_mst_r_pms_reg_t ahb_pdma_i3c_mst_r_pms;
+    volatile tee_dma_ahb_pdma_i3c_mst_w_pms_reg_t ahb_pdma_i3c_mst_w_pms;
+    volatile tee_dma_ahb_pdma_uhci0_r_pms_reg_t ahb_pdma_uhci0_r_pms;
+    volatile tee_dma_ahb_pdma_uhci0_w_pms_reg_t ahb_pdma_uhci0_w_pms;
+    volatile tee_dma_ahb_pdma_rmt_r_pms_reg_t ahb_pdma_rmt_r_pms;
+    uint32_t reserved_15c[5];
+    volatile tee_dma_ahb_pdma_rmt_w_pms_reg_t ahb_pdma_rmt_w_pms;
+    volatile tee_dma_axi_pdma_lcdcam_r_pms_reg_t axi_pdma_lcdcam_r_pms;
+    volatile tee_dma_axi_pdma_lcdcam_w_pms_reg_t axi_pdma_lcdcam_w_pms;
+    volatile tee_dma_axi_pdma_gpspi2_r_pms_reg_t axi_pdma_gpspi2_r_pms;
+    volatile tee_dma_axi_pdma_gpspi2_w_pms_reg_t axi_pdma_gpspi2_w_pms;
+    volatile tee_dma_axi_pdma_gpspi3_r_pms_reg_t axi_pdma_gpspi3_r_pms;
+    volatile tee_dma_axi_pdma_gpspi3_w_pms_reg_t axi_pdma_gpspi3_w_pms;
+    volatile tee_dma_axi_pdma_parlio_r_pms_reg_t axi_pdma_parlio_r_pms;
+    volatile tee_dma_axi_pdma_parlio_w_pms_reg_t axi_pdma_parlio_w_pms;
+    volatile tee_dma_axi_pdma_aes_r_pms_reg_t axi_pdma_aes_r_pms;
+    volatile tee_dma_axi_pdma_aes_w_pms_reg_t axi_pdma_aes_w_pms;
+    volatile tee_dma_axi_pdma_sha_r_pms_reg_t axi_pdma_sha_r_pms;
+    volatile tee_dma_axi_pdma_sha_w_pms_reg_t axi_pdma_sha_w_pms;
+    volatile tee_dma_dma2d_jpeg_pms_r_reg_t dma2d_jpeg_pms_r;
+    volatile tee_dma_dma2d_jpeg_pms_w_reg_t dma2d_jpeg_pms_w;
+    volatile tee_dma_usb_pms_r_reg_t usb_pms_r;
+    volatile tee_dma_usb_pms_w_reg_t usb_pms_w;
+    volatile tee_dma_gmac_pms_r_reg_t gmac_pms_r;
+    volatile tee_dma_gmac_pms_w_reg_t gmac_pms_w;
+    volatile tee_dma_sdmmc_pms_r_reg_t sdmmc_pms_r;
+    volatile tee_dma_sdmmc_pms_w_reg_t sdmmc_pms_w;
+    volatile tee_dma_usbotg11_pms_r_reg_t usbotg11_pms_r;
+    volatile tee_dma_usbotg11_pms_w_reg_t usbotg11_pms_w;
+    volatile tee_dma_trace0_pms_r_reg_t trace0_pms_r;
+    volatile tee_dma_trace0_pms_w_reg_t trace0_pms_w;
+    volatile tee_dma_trace1_pms_r_reg_t trace1_pms_r;
+    volatile tee_dma_trace1_pms_w_reg_t trace1_pms_w;
+    volatile tee_dma_l2mem_mon_pms_r_reg_t l2mem_mon_pms_r;
+    volatile tee_dma_l2mem_mon_pms_w_reg_t l2mem_mon_pms_w;
+    volatile tee_dma_tcm_mon_pms_r_reg_t tcm_mon_pms_r;
+    volatile tee_dma_tcm_mon_pms_w_reg_t tcm_mon_pms_w;
+    volatile tee_dma_regdma_pms_r_reg_t regdma_pms_r;
+    volatile tee_dma_regdma_pms_w_reg_t regdma_pms_w;
+    uint32_t reserved_1f4[2];
+    volatile tee_dma_h264_pms_r_reg_t h264_pms_r;
+    volatile tee_dma_h264_pms_w_reg_t h264_pms_w;
+    volatile tee_dma_dma2d_ppa_pms_r_reg_t dma2d_ppa_pms_r;
+    volatile tee_dma_dma2d_ppa_pms_w_reg_t dma2d_ppa_pms_w;
+    volatile tee_dma_dma2d_dummy_pms_r_reg_t dma2d_dummy_pms_r;
+    volatile tee_dma_dma2d_dummy_pms_w_reg_t dma2d_dummy_pms_w;
+    volatile tee_dma_ahb_pdma_dummy_r_pms_reg_t ahb_pdma_dummy_r_pms;
+    volatile tee_dma_ahb_pdma_dummy_w_pms_reg_t ahb_pdma_dummy_w_pms;
+    volatile tee_dma_axi_pdma_dummy_r_pms_reg_t axi_pdma_dummy_r_pms;
+    volatile tee_dma_axi_pdma_dummy_w_pms_reg_t axi_pdma_dummy_w_pms;
+} tee_dma_dev_t;
+
+extern tee_dma_dev_t DMA_PMS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dma_dev_t) == 0x224, "Invalid size of tee_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ds_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ds_reg.h
new file mode 100644
index 0000000000..fd6797f0fa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ds_reg.h
@@ -0,0 +1,176 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DS_Y_MEM register
+ *  memory that stores Y
+ */
+#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
+#define DS_Y_MEM_SIZE_BYTES 512
+
+/** DS_M_MEM register
+ *  memory that stores M
+ */
+#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
+#define DS_M_MEM_SIZE_BYTES 512
+
+/** DS_RB_MEM register
+ *  memory that stores Rb
+ */
+#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
+#define DS_RB_MEM_SIZE_BYTES 512
+
+/** DS_BOX_MEM register
+ *  memory that stores BOX
+ */
+#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
+#define DS_BOX_MEM_SIZE_BYTES 48
+
+/** DS_IV_MEM register
+ *  memory that stores IV
+ */
+#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
+#define DS_IV_MEM_SIZE_BYTES 16
+
+/** DS_X_MEM register
+ *  memory that stores X
+ */
+#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
+#define DS_X_MEM_SIZE_BYTES 512
+
+/** DS_Z_MEM register
+ *  memory that stores Z
+ */
+#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
+#define DS_Z_MEM_SIZE_BYTES 512
+
+/** DS_SET_START_REG register
+ *  Activates the DS module
+ */
+#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
+/** DS_SET_START : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to activate the DS peripheral.
+ *  0: Invalid
+ *  1: Activate the DS peripheral
+ */
+#define DS_SET_START    (BIT(0))
+#define DS_SET_START_M  (DS_SET_START_V << DS_SET_START_S)
+#define DS_SET_START_V  0x00000001U
+#define DS_SET_START_S  0
+
+/** DS_SET_CONTINUE_REG register
+ *  DS continue control register
+ */
+#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
+/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  set this bit to continue DS operation.
+ */
+#define DS_SET_CONTINUE    (BIT(0))
+#define DS_SET_CONTINUE_M  (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
+#define DS_SET_CONTINUE_V  0x00000001U
+#define DS_SET_CONTINUE_S  0
+
+/** DS_SET_FINISH_REG register
+ *  Ends DS operation
+ */
+#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
+/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to end DS operation.
+ *  0: Invalid
+ *  1: End DS operation
+ */
+#define DS_SET_FINISH    (BIT(0))
+#define DS_SET_FINISH_M  (DS_SET_FINISH_V << DS_SET_FINISH_S)
+#define DS_SET_FINISH_V  0x00000001U
+#define DS_SET_FINISH_S  0
+
+/** DS_QUERY_BUSY_REG register
+ *  Status of the DS module
+ */
+#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
+/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the DS module is idle.
+ *  0: The DS module is idle
+ *  1: The DS module is busy
+ */
+#define DS_QUERY_BUSY    (BIT(0))
+#define DS_QUERY_BUSY_M  (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
+#define DS_QUERY_BUSY_V  0x00000001U
+#define DS_QUERY_BUSY_S  0
+
+/** DS_QUERY_KEY_WRONG_REG register
+ *  Checks the reason why \begin{math}DS_KEY\end{math} is not ready
+ */
+#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
+/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
+ *  Represents the specific problem with HMAC initialization.
+ *  0: HMAC is not called
+ *  1-15: HMAC was activated, but the DS peripheral did not successfully receive the
+ *  \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)
+ */
+#define DS_QUERY_KEY_WRONG    0x0000000FU
+#define DS_QUERY_KEY_WRONG_M  (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
+#define DS_QUERY_KEY_WRONG_V  0x0000000FU
+#define DS_QUERY_KEY_WRONG_S  0
+
+/** DS_QUERY_CHECK_REG register
+ *  Queries DS check result
+ */
+#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
+/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the MD check passes.
+ *  0: The MD check passes
+ *  1: The MD check fails
+ */
+#define DS_MD_ERROR    (BIT(0))
+#define DS_MD_ERROR_M  (DS_MD_ERROR_V << DS_MD_ERROR_S)
+#define DS_MD_ERROR_V  0x00000001U
+#define DS_MD_ERROR_S  0
+/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not the padding check passes.
+ *  0: The padding check passes
+ *  1: The padding check fails
+ */
+#define DS_PADDING_BAD    (BIT(1))
+#define DS_PADDING_BAD_M  (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
+#define DS_PADDING_BAD_V  0x00000001U
+#define DS_PADDING_BAD_S  1
+
+/** DS_KEY_SOURCE_REG register
+ *  DS configure key source register
+ */
+#define DS_KEY_SOURCE_REG (DR_REG_DS_BASE + 0xe18)
+/** DS_KEY_SOURCE : R/W; bitpos: [0]; default: 0;
+ *  digital signature key source bit.
+ *  1'b0: key is from hmac.
+ *  1'b1: key is from key manager.
+ */
+#define DS_KEY_SOURCE    (BIT(0))
+#define DS_KEY_SOURCE_M  (DS_KEY_SOURCE_V << DS_KEY_SOURCE_S)
+#define DS_KEY_SOURCE_V  0x00000001U
+#define DS_KEY_SOURCE_S  0
+
+/** DS_DATE_REG register
+ *  DS version control register
+ */
+#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
+/** DS_DATE : R/W; bitpos: [29:0]; default: 539166977;
+ *  ds version information
+ */
+#define DS_DATE    0x3FFFFFFFU
+#define DS_DATE_M  (DS_DATE_V << DS_DATE_S)
+#define DS_DATE_V  0x3FFFFFFFU
+#define DS_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ds_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ds_struct.h
new file mode 100644
index 0000000000..317f867a4c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ds_struct.h
@@ -0,0 +1,181 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: memory type */
+
+/** Group: Control/Status registers */
+/** Type of set_start register
+ *  Activates the DS module
+ */
+typedef union {
+    struct {
+        /** set_start : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to activate the DS peripheral.
+         *  0: Invalid
+         *  1: Activate the DS peripheral
+         */
+        uint32_t set_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_set_start_reg_t;
+
+/** Type of set_continue register
+ *  DS continue control register
+ */
+typedef union {
+    struct {
+        /** set_continue : WT; bitpos: [0]; default: 0;
+         *  set this bit to continue DS operation.
+         */
+        uint32_t set_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_set_continue_reg_t;
+
+/** Type of set_finish register
+ *  Ends DS operation
+ */
+typedef union {
+    struct {
+        /** set_finish : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to end DS operation.
+         *  0: Invalid
+         *  1: End DS operation
+         */
+        uint32_t set_finish:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_set_finish_reg_t;
+
+/** Type of query_busy register
+ *  Status of the DS module
+ */
+typedef union {
+    struct {
+        /** query_busy : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the DS module is idle.
+         *  0: The DS module is idle
+         *  1: The DS module is busy
+         */
+        uint32_t query_busy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_query_busy_reg_t;
+
+/** Type of query_key_wrong register
+ *  Checks the reason why \begin{math}DS_KEY\end{math} is not ready
+ */
+typedef union {
+    struct {
+        /** query_key_wrong : RO; bitpos: [3:0]; default: 0;
+         *  Represents the specific problem with HMAC initialization.
+         *  0: HMAC is not called
+         *  1-15: HMAC was activated, but the DS peripheral did not successfully receive the
+         *  \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)
+         */
+        uint32_t query_key_wrong:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ds_query_key_wrong_reg_t;
+
+/** Type of query_check register
+ *  Queries DS check result
+ */
+typedef union {
+    struct {
+        /** md_error : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the MD check passes.
+         *  0: The MD check passes
+         *  1: The MD check fails
+         */
+        uint32_t md_error:1;
+        /** padding_bad : RO; bitpos: [1]; default: 0;
+         *  Represents whether or not the padding check passes.
+         *  0: The padding check passes
+         *  1: The padding check fails
+         */
+        uint32_t padding_bad:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ds_query_check_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of key_source register
+ *  DS configure key source register
+ */
+typedef union {
+    struct {
+        /** key_source : R/W; bitpos: [0]; default: 0;
+         *  digital signature key source bit.
+         *  1'b0: key is from hmac.
+         *  1'b1: key is from key manager.
+         */
+        uint32_t key_source:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_key_source_reg_t;
+
+
+/** Group: version control register */
+/** Type of date register
+ *  DS version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [29:0]; default: 539166977;
+         *  ds version information
+         */
+        uint32_t date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} ds_date_reg_t;
+
+
+typedef struct {
+    volatile uint32_t y[128];
+    volatile uint32_t m[128];
+    volatile uint32_t rb[128];
+    volatile uint32_t box[12];
+    volatile uint32_t iv[4];
+    uint32_t reserved_640[112];
+    volatile uint32_t x[128];
+    volatile uint32_t z[128];
+    uint32_t reserved_c00[128];
+    volatile ds_set_start_reg_t set_start;
+    volatile ds_set_continue_reg_t set_continue;
+    volatile ds_set_finish_reg_t set_finish;
+    volatile ds_query_busy_reg_t query_busy;
+    volatile ds_query_key_wrong_reg_t query_key_wrong;
+    volatile ds_query_check_reg_t query_check;
+    volatile ds_key_source_reg_t key_source;
+    uint32_t reserved_e1c;
+    volatile ds_date_reg_t date;
+} ds_dev_t;
+
+extern ds_dev_t DS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_eco5_struct.h
new file mode 100644
index 0000000000..c030f0e037
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_eco5_struct.h
@@ -0,0 +1,5184 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Version Register */
+/** Type of id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_id : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_id:32;
+    };
+    uint32_t val;
+} dmac_id0_reg_t;
+
+/** Type of compver0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_compver : RO; bitpos: [31:0]; default: 842018858;
+         *  NA
+         */
+        uint32_t dmac_compver:32;
+    };
+    uint32_t val;
+} dmac_compver0_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_en:1;
+        /** int_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t int_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dmac_cfg0_reg_t;
+
+/** Type of chen0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_en:1;
+        /** ch2_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_en:1;
+        /** ch3_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_en:1;
+        /** ch4_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_en:1;
+        uint32_t reserved_4:4;
+        /** ch1_en_we : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_en_we:1;
+        /** ch2_en_we : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_en_we:1;
+        /** ch3_en_we : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_en_we:1;
+        /** ch4_en_we : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_en_we:1;
+        uint32_t reserved_12:4;
+        /** ch1_susp : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_susp:1;
+        /** ch2_susp : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_susp:1;
+        /** ch3_susp : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_susp:1;
+        /** ch4_susp : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_susp:1;
+        uint32_t reserved_20:4;
+        /** ch1_susp_we : WO; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_susp_we:1;
+        /** ch2_susp_we : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_susp_we:1;
+        /** ch3_susp_we : WO; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_susp_we:1;
+        /** ch4_susp_we : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_susp_we:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dmac_chen0_reg_t;
+
+/** Type of chen1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_abort : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_abort:1;
+        /** ch2_abort : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_abort:1;
+        /** ch3_abort : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_abort:1;
+        /** ch4_abort : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_abort:1;
+        uint32_t reserved_4:4;
+        /** ch1_abort_we : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_abort_we:1;
+        /** ch2_abort_we : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_abort_we:1;
+        /** ch3_abort_we : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_abort_we:1;
+        /** ch4_abort_we : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_abort_we:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dmac_chen1_reg_t;
+
+/** Type of reset0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_rst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_rst:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dmac_reset0_reg_t;
+
+/** Type of lowpower_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gbl_cslp_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t gbl_cslp_en:1;
+        /** chnl_cslp_en : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t chnl_cslp_en:1;
+        /** sbiu_cslp_en : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t sbiu_cslp_en:1;
+        /** mxif_cslp_en : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t mxif_cslp_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_lowpower_cfg0_reg_t;
+
+/** Type of lowpower_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** glch_lpdly : R/W; bitpos: [7:0]; default: 64;
+         *  NA
+         */
+        uint32_t glch_lpdly:8;
+        /** sbiu_lpdly : R/W; bitpos: [15:8]; default: 64;
+         *  NA
+         */
+        uint32_t sbiu_lpdly:8;
+        /** mxif_lpdly : R/W; bitpos: [23:16]; default: 64;
+         *  NA
+         */
+        uint32_t mxif_lpdly:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dmac_lowpower_cfg1_reg_t;
+
+/** Type of ch1_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sar0:32;
+    };
+    uint32_t val;
+} dmac_ch1_sar0_reg_t;
+
+/** Type of ch1_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sar1:32;
+    };
+    uint32_t val;
+} dmac_ch1_sar1_reg_t;
+
+/** Type of ch1_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dar0:32;
+    };
+    uint32_t val;
+} dmac_ch1_dar0_reg_t;
+
+/** Type of ch1_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dar1:32;
+    };
+    uint32_t val;
+} dmac_ch1_dar1_reg_t;
+
+/** Type of ch1_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_block_ts:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch1_block_ts0_reg_t;
+
+/** Type of ch1_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sms:1;
+        uint32_t reserved_1:1;
+        /** ch1_dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dms:1;
+        uint32_t reserved_3:1;
+        /** ch1_sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sinc:1;
+        uint32_t reserved_5:1;
+        /** ch1_dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dinc:1;
+        uint32_t reserved_7:1;
+        /** ch1_src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t ch1_src_tr_width:3;
+        /** ch1_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t ch1_dst_tr_width:3;
+        /** ch1_src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_msize:4;
+        /** ch1_dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_msize:4;
+        /** ch1_ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ar_cache:4;
+        /** ch1_aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_aw_cache:4;
+        /** ch1_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_nonposted_lastwrite_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch1_ctl0_reg_t;
+
+/** Type of ch1_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ar_prot:3;
+        /** ch1_aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_aw_prot:3;
+        /** ch1_arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_arlen_en:1;
+        /** ch1_arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_arlen:8;
+        /** ch1_awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_awlen_en:1;
+        /** ch1_awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_awlen:8;
+        /** ch1_src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_stat_en:1;
+        /** ch1_dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_stat_en:1;
+        /** ch1_ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ioc_blktfr:1;
+        uint32_t reserved_27:3;
+        /** ch1_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_shadowreg_or_lli_last:1;
+        /** ch1_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_shadowreg_or_lli_valid:1;
+    };
+    uint32_t val;
+} dmac_ch1_ctl1_reg_t;
+
+/** Type of ch1_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_multblk_type:2;
+        /** ch1_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_multblk_type:2;
+        uint32_t reserved_4:14;
+        /** ch1_rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_rd_uid:4;
+        uint32_t reserved_22:3;
+        /** ch1_wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_wr_uid:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dmac_ch1_cfg0_reg_t;
+
+/** Type of ch1_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t ch1_tt_fc:3;
+        /** ch1_hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_hs_sel_src:1;
+        /** ch1_hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_hs_sel_dst:1;
+        /** ch1_src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_hwhs_pol:1;
+        /** ch1_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_hwhs_pol:1;
+        /** ch1_src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_per:2;
+        uint32_t reserved_9:3;
+        /** ch1_dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_per:2;
+        uint32_t reserved_14:3;
+        /** ch1_ch_prior : R/W; bitpos: [19:17]; default: 3;
+         *  NA
+         */
+        uint32_t ch1_ch_prior:3;
+        /** ch1_lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lock_ch:1;
+        /** ch1_lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lock_ch_l:2;
+        /** ch1_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_osr_lmt:4;
+        /** ch1_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_osr_lmt:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch1_cfg1_reg_t;
+
+/** Type of ch1_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lms:1;
+        uint32_t reserved_1:5;
+        /** ch1_loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_loc0:26;
+    };
+    uint32_t val;
+} dmac_ch1_llp0_reg_t;
+
+/** Type of ch1_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_loc1:32;
+    };
+    uint32_t val;
+} dmac_ch1_llp1_reg_t;
+
+/** Type of ch1_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_req_src:1;
+        /** ch1_swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_req_src_we:1;
+        /** ch1_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_sglreq_src:1;
+        /** ch1_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_sglreq_src_we:1;
+        /** ch1_swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_lst_src:1;
+        /** ch1_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_lst_src_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch1_swhssrc0_reg_t;
+
+/** Type of ch1_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_req_dst:1;
+        /** ch1_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_req_dst_we:1;
+        /** ch1_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_sglreq_dst:1;
+        /** ch1_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_sglreq_dst_we:1;
+        /** ch1_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_lst_dst:1;
+        /** ch1_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_lst_dst_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch1_swhsdst0_reg_t;
+
+/** Type of ch1_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_blk_tfr_resumereq:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dmac_ch1_blk_tfr_resumereq0_reg_t;
+
+/** Type of ch1_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_axi_read_id_suffix:1;
+        uint32_t reserved_1:15;
+        /** ch1_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_axi_write_id_suffix:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dmac_ch1_axi_id0_reg_t;
+
+/** Type of ch1_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_axi_awqos:4;
+        /** ch1_axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_axi_arqos:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dmac_ch1_axi_qos0_reg_t;
+
+/** Type of ch2_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sar0:32;
+    };
+    uint32_t val;
+} dmac_ch2_sar0_reg_t;
+
+/** Type of ch2_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sar1:32;
+    };
+    uint32_t val;
+} dmac_ch2_sar1_reg_t;
+
+/** Type of ch2_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dar0:32;
+    };
+    uint32_t val;
+} dmac_ch2_dar0_reg_t;
+
+/** Type of ch2_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dar1:32;
+    };
+    uint32_t val;
+} dmac_ch2_dar1_reg_t;
+
+/** Type of ch2_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_block_ts:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch2_block_ts0_reg_t;
+
+/** Type of ch2_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sms:1;
+        uint32_t reserved_1:1;
+        /** ch2_dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dms:1;
+        uint32_t reserved_3:1;
+        /** ch2_sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sinc:1;
+        uint32_t reserved_5:1;
+        /** ch2_dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dinc:1;
+        uint32_t reserved_7:1;
+        /** ch2_src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t ch2_src_tr_width:3;
+        /** ch2_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t ch2_dst_tr_width:3;
+        /** ch2_src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_msize:4;
+        /** ch2_dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_msize:4;
+        /** ch2_ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ar_cache:4;
+        /** ch2_aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_aw_cache:4;
+        /** ch2_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_nonposted_lastwrite_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch2_ctl0_reg_t;
+
+/** Type of ch2_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ar_prot:3;
+        /** ch2_aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_aw_prot:3;
+        /** ch2_arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_arlen_en:1;
+        /** ch2_arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_arlen:8;
+        /** ch2_awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_awlen_en:1;
+        /** ch2_awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_awlen:8;
+        /** ch2_src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_stat_en:1;
+        /** ch2_dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_stat_en:1;
+        /** ch2_ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ioc_blktfr:1;
+        uint32_t reserved_27:3;
+        /** ch2_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_shadowreg_or_lli_last:1;
+        /** ch2_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_shadowreg_or_lli_valid:1;
+    };
+    uint32_t val;
+} dmac_ch2_ctl1_reg_t;
+
+/** Type of ch2_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_multblk_type:2;
+        /** ch2_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_multblk_type:2;
+        uint32_t reserved_4:14;
+        /** ch2_rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_rd_uid:4;
+        uint32_t reserved_22:3;
+        /** ch2_wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_wr_uid:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dmac_ch2_cfg0_reg_t;
+
+/** Type of ch2_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t ch2_tt_fc:3;
+        /** ch2_hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_hs_sel_src:1;
+        /** ch2_hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_hs_sel_dst:1;
+        /** ch2_src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_hwhs_pol:1;
+        /** ch2_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_hwhs_pol:1;
+        /** ch2_src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_per:2;
+        uint32_t reserved_9:3;
+        /** ch2_dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_per:2;
+        uint32_t reserved_14:3;
+        /** ch2_ch_prior : R/W; bitpos: [19:17]; default: 2;
+         *  NA
+         */
+        uint32_t ch2_ch_prior:3;
+        /** ch2_lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lock_ch:1;
+        /** ch2_lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lock_ch_l:2;
+        /** ch2_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_osr_lmt:4;
+        /** ch2_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_osr_lmt:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch2_cfg1_reg_t;
+
+/** Type of ch2_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lms:1;
+        uint32_t reserved_1:5;
+        /** ch2_loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_loc0:26;
+    };
+    uint32_t val;
+} dmac_ch2_llp0_reg_t;
+
+/** Type of ch2_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_loc1:32;
+    };
+    uint32_t val;
+} dmac_ch2_llp1_reg_t;
+
+/** Type of ch2_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_req_src:1;
+        /** ch2_swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_req_src_we:1;
+        /** ch2_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_sglreq_src:1;
+        /** ch2_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_sglreq_src_we:1;
+        /** ch2_swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_lst_src:1;
+        /** ch2_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_lst_src_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch2_swhssrc0_reg_t;
+
+/** Type of ch2_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_req_dst:1;
+        /** ch2_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_req_dst_we:1;
+        /** ch2_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_sglreq_dst:1;
+        /** ch2_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_sglreq_dst_we:1;
+        /** ch2_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_lst_dst:1;
+        /** ch2_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_lst_dst_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch2_swhsdst0_reg_t;
+
+/** Type of ch2_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_blk_tfr_resumereq:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dmac_ch2_blk_tfr_resumereq0_reg_t;
+
+/** Type of ch2_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_axi_read_id_suffix:1;
+        uint32_t reserved_1:15;
+        /** ch2_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_axi_write_id_suffix:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dmac_ch2_axi_id0_reg_t;
+
+/** Type of ch2_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_axi_awqos:4;
+        /** ch2_axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_axi_arqos:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dmac_ch2_axi_qos0_reg_t;
+
+/** Type of ch3_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sar0:32;
+    };
+    uint32_t val;
+} dmac_ch3_sar0_reg_t;
+
+/** Type of ch3_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sar1:32;
+    };
+    uint32_t val;
+} dmac_ch3_sar1_reg_t;
+
+/** Type of ch3_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dar0:32;
+    };
+    uint32_t val;
+} dmac_ch3_dar0_reg_t;
+
+/** Type of ch3_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dar1:32;
+    };
+    uint32_t val;
+} dmac_ch3_dar1_reg_t;
+
+/** Type of ch3_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_block_ts:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch3_block_ts0_reg_t;
+
+/** Type of ch3_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sms:1;
+        uint32_t reserved_1:1;
+        /** ch3_dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dms:1;
+        uint32_t reserved_3:1;
+        /** ch3_sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sinc:1;
+        uint32_t reserved_5:1;
+        /** ch3_dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dinc:1;
+        uint32_t reserved_7:1;
+        /** ch3_src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t ch3_src_tr_width:3;
+        /** ch3_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t ch3_dst_tr_width:3;
+        /** ch3_src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_msize:4;
+        /** ch3_dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_msize:4;
+        /** ch3_ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ar_cache:4;
+        /** ch3_aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_aw_cache:4;
+        /** ch3_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_nonposted_lastwrite_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch3_ctl0_reg_t;
+
+/** Type of ch3_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ar_prot:3;
+        /** ch3_aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_aw_prot:3;
+        /** ch3_arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_arlen_en:1;
+        /** ch3_arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_arlen:8;
+        /** ch3_awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_awlen_en:1;
+        /** ch3_awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_awlen:8;
+        /** ch3_src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_stat_en:1;
+        /** ch3_dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_stat_en:1;
+        /** ch3_ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ioc_blktfr:1;
+        uint32_t reserved_27:3;
+        /** ch3_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_shadowreg_or_lli_last:1;
+        /** ch3_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_shadowreg_or_lli_valid:1;
+    };
+    uint32_t val;
+} dmac_ch3_ctl1_reg_t;
+
+/** Type of ch3_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_multblk_type:2;
+        /** ch3_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_multblk_type:2;
+        uint32_t reserved_4:14;
+        /** ch3_rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_rd_uid:4;
+        uint32_t reserved_22:3;
+        /** ch3_wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_wr_uid:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dmac_ch3_cfg0_reg_t;
+
+/** Type of ch3_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t ch3_tt_fc:3;
+        /** ch3_hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_hs_sel_src:1;
+        /** ch3_hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_hs_sel_dst:1;
+        /** ch3_src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_hwhs_pol:1;
+        /** ch3_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_hwhs_pol:1;
+        /** ch3_src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_per:2;
+        uint32_t reserved_9:3;
+        /** ch3_dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_per:2;
+        uint32_t reserved_14:3;
+        /** ch3_ch_prior : R/W; bitpos: [19:17]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_ch_prior:3;
+        /** ch3_lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lock_ch:1;
+        /** ch3_lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lock_ch_l:2;
+        /** ch3_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_osr_lmt:4;
+        /** ch3_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_osr_lmt:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch3_cfg1_reg_t;
+
+/** Type of ch3_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lms:1;
+        uint32_t reserved_1:5;
+        /** ch3_loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_loc0:26;
+    };
+    uint32_t val;
+} dmac_ch3_llp0_reg_t;
+
+/** Type of ch3_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_loc1:32;
+    };
+    uint32_t val;
+} dmac_ch3_llp1_reg_t;
+
+/** Type of ch3_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_req_src:1;
+        /** ch3_swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_req_src_we:1;
+        /** ch3_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_sglreq_src:1;
+        /** ch3_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_sglreq_src_we:1;
+        /** ch3_swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_lst_src:1;
+        /** ch3_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_lst_src_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch3_swhssrc0_reg_t;
+
+/** Type of ch3_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_req_dst:1;
+        /** ch3_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_req_dst_we:1;
+        /** ch3_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_sglreq_dst:1;
+        /** ch3_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_sglreq_dst_we:1;
+        /** ch3_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_lst_dst:1;
+        /** ch3_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_lst_dst_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch3_swhsdst0_reg_t;
+
+/** Type of ch3_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_blk_tfr_resumereq:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dmac_ch3_blk_tfr_resumereq0_reg_t;
+
+/** Type of ch3_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_axi_read_id_suffix:1;
+        uint32_t reserved_1:15;
+        /** ch3_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_axi_write_id_suffix:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dmac_ch3_axi_id0_reg_t;
+
+/** Type of ch3_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_axi_awqos:4;
+        /** ch3_axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_axi_arqos:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dmac_ch3_axi_qos0_reg_t;
+
+/** Type of ch4_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sar0:32;
+    };
+    uint32_t val;
+} dmac_ch4_sar0_reg_t;
+
+/** Type of ch4_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sar1:32;
+    };
+    uint32_t val;
+} dmac_ch4_sar1_reg_t;
+
+/** Type of ch4_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dar0:32;
+    };
+    uint32_t val;
+} dmac_ch4_dar0_reg_t;
+
+/** Type of ch4_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dar1:32;
+    };
+    uint32_t val;
+} dmac_ch4_dar1_reg_t;
+
+/** Type of ch4_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_block_ts:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch4_block_ts0_reg_t;
+
+/** Type of ch4_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sms:1;
+        uint32_t reserved_1:1;
+        /** ch4_dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dms:1;
+        uint32_t reserved_3:1;
+        /** ch4_sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sinc:1;
+        uint32_t reserved_5:1;
+        /** ch4_dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dinc:1;
+        uint32_t reserved_7:1;
+        /** ch4_src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t ch4_src_tr_width:3;
+        /** ch4_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t ch4_dst_tr_width:3;
+        /** ch4_src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_msize:4;
+        /** ch4_dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_msize:4;
+        /** ch4_ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ar_cache:4;
+        /** ch4_aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_aw_cache:4;
+        /** ch4_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_nonposted_lastwrite_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch4_ctl0_reg_t;
+
+/** Type of ch4_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ar_prot:3;
+        /** ch4_aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_aw_prot:3;
+        /** ch4_arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_arlen_en:1;
+        /** ch4_arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_arlen:8;
+        /** ch4_awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_awlen_en:1;
+        /** ch4_awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_awlen:8;
+        /** ch4_src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_stat_en:1;
+        /** ch4_dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_stat_en:1;
+        /** ch4_ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ioc_blktfr:1;
+        uint32_t reserved_27:3;
+        /** ch4_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_shadowreg_or_lli_last:1;
+        /** ch4_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_shadowreg_or_lli_valid:1;
+    };
+    uint32_t val;
+} dmac_ch4_ctl1_reg_t;
+
+/** Type of ch4_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_multblk_type:2;
+        /** ch4_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_multblk_type:2;
+        uint32_t reserved_4:14;
+        /** ch4_rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_rd_uid:4;
+        uint32_t reserved_22:3;
+        /** ch4_wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_wr_uid:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dmac_ch4_cfg0_reg_t;
+
+/** Type of ch4_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t ch4_tt_fc:3;
+        /** ch4_hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_hs_sel_src:1;
+        /** ch4_hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_hs_sel_dst:1;
+        /** ch4_src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_hwhs_pol:1;
+        /** ch4_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_hwhs_pol:1;
+        /** ch4_src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_per:2;
+        uint32_t reserved_9:3;
+        /** ch4_dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_per:2;
+        uint32_t reserved_14:3;
+        /** ch4_ch_prior : R/W; bitpos: [19:17]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_prior:3;
+        /** ch4_lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lock_ch:1;
+        /** ch4_lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lock_ch_l:2;
+        /** ch4_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_osr_lmt:4;
+        /** ch4_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_osr_lmt:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch4_cfg1_reg_t;
+
+/** Type of ch4_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lms:1;
+        uint32_t reserved_1:5;
+        /** ch4_loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_loc0:26;
+    };
+    uint32_t val;
+} dmac_ch4_llp0_reg_t;
+
+/** Type of ch4_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_loc1:32;
+    };
+    uint32_t val;
+} dmac_ch4_llp1_reg_t;
+
+/** Type of ch4_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_req_src:1;
+        /** ch4_swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_req_src_we:1;
+        /** ch4_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_sglreq_src:1;
+        /** ch4_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_sglreq_src_we:1;
+        /** ch4_swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_lst_src:1;
+        /** ch4_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_lst_src_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch4_swhssrc0_reg_t;
+
+/** Type of ch4_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_req_dst:1;
+        /** ch4_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_req_dst_we:1;
+        /** ch4_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_sglreq_dst:1;
+        /** ch4_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_sglreq_dst_we:1;
+        /** ch4_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_lst_dst:1;
+        /** ch4_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_lst_dst_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch4_swhsdst0_reg_t;
+
+/** Type of ch4_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_blk_tfr_resumereq:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dmac_ch4_blk_tfr_resumereq0_reg_t;
+
+/** Type of ch4_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_axi_read_id_suffix:1;
+        uint32_t reserved_1:15;
+        /** ch4_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_axi_write_id_suffix:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dmac_ch4_axi_id0_reg_t;
+
+/** Type of ch4_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_axi_awqos:4;
+        /** ch4_axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_axi_arqos:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dmac_ch4_axi_qos0_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_intstat:1;
+        /** ch2_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_intstat:1;
+        /** ch3_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_intstat:1;
+        /** ch4_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_intstat:1;
+        uint32_t reserved_4:12;
+        /** commonreg_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t commonreg_intstat:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dmac_intstatus0_reg_t;
+
+/** Type of commonreg_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_slvif_commonreg_dec_err_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_dec_err_intstat:1;
+        /** clear_slvif_commonreg_wr2ro_err_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wr2ro_err_intstat:1;
+        /** clear_slvif_commonreg_rd2wo_err_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_rd2wo_err_intstat:1;
+        /** clear_slvif_commonreg_wronhold_err_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wronhold_err_intstat:1;
+        uint32_t reserved_4:3;
+        /** clear_slvif_commonreg_wrparity_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wrparity_err_intstat:1;
+        /** clear_slvif_undefinedreg_dec_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_undefinedreg_dec_err_intstat:1;
+        /** clear_mxif1_rch0_eccprot_correrr_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch0_eccprot_correrr_intstat:1;
+        /** clear_mxif1_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch0_eccprot_uncorrerr_intstat:1;
+        /** clear_mxif1_rch1_eccprot_correrr_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch1_eccprot_correrr_intstat:1;
+        /** clear_mxif1_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch1_eccprot_uncorrerr_intstat:1;
+        /** clear_mxif1_bch_eccprot_correrr_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_bch_eccprot_correrr_intstat:1;
+        /** clear_mxif1_bch_eccprot_uncorrerr_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_bch_eccprot_uncorrerr_intstat:1;
+        /** clear_mxif2_rch0_eccprot_correrr_intstat : WO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch0_eccprot_correrr_intstat:1;
+        /** clear_mxif2_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch0_eccprot_uncorrerr_intstat:1;
+        /** clear_mxif2_rch1_eccprot_correrr_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch1_eccprot_correrr_intstat:1;
+        /** clear_mxif2_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch1_eccprot_uncorrerr_intstat:1;
+        /** clear_mxif2_bch_eccprot_correrr_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_bch_eccprot_correrr_intstat:1;
+        /** clear_mxif2_bch_eccprot_uncorrerr_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_bch_eccprot_uncorrerr_intstat:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dmac_commonreg_intclear0_reg_t;
+
+/** Type of commonreg_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_slvif_commonreg_dec_err_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_dec_err_intstat:1;
+        /** enable_slvif_commonreg_wr2ro_err_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wr2ro_err_intstat:1;
+        /** enable_slvif_commonreg_rd2wo_err_intstat : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_rd2wo_err_intstat:1;
+        /** enable_slvif_commonreg_wronhold_err_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wronhold_err_intstat:1;
+        uint32_t reserved_4:3;
+        /** enable_slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wrparity_err_intstat:1;
+        /** enable_slvif_undefinedreg_dec_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_undefinedreg_dec_err_intstat:1;
+        /** enable_mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_correrr_intstat:1;
+        /** enable_mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intstat:1;
+        /** enable_mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_correrr_intstat:1;
+        /** enable_mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intstat:1;
+        /** enable_mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_correrr_intstat:1;
+        /** enable_mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intstat:1;
+        /** enable_mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_correrr_intstat:1;
+        /** enable_mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intstat:1;
+        /** enable_mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_correrr_intstat:1;
+        /** enable_mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intstat:1;
+        /** enable_mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_correrr_intstat:1;
+        /** enable_mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intstat:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dmac_commonreg_intstatus_enable0_reg_t;
+
+/** Type of commonreg_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_slvif_commonreg_dec_err_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_dec_err_intsignal:1;
+        /** enable_slvif_commonreg_wr2ro_err_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wr2ro_err_intsignal:1;
+        /** enable_slvif_commonreg_rd2wo_err_intsignal : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_rd2wo_err_intsignal:1;
+        /** enable_slvif_commonreg_wronhold_err_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wronhold_err_intsignal:1;
+        uint32_t reserved_4:3;
+        /** enable_slvif_commonreg_wrparity_err_intsignal : RO; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wrparity_err_intsignal:1;
+        /** enable_slvif_undefinedreg_dec_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_undefinedreg_dec_err_intsignal:1;
+        /** enable_mxif1_rch0_eccprot_correrr_intsignal : RO; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_correrr_intsignal:1;
+        /** enable_mxif1_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intsignal:1;
+        /** enable_mxif1_rch1_eccprot_correrr_intsignal : RO; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_correrr_intsignal:1;
+        /** enable_mxif1_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intsignal:1;
+        /** enable_mxif1_bch_eccprot_correrr_intsignal : RO; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_correrr_intsignal:1;
+        /** enable_mxif1_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intsignal:1;
+        /** enable_mxif2_rch0_eccprot_correrr_intsignal : RO; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_correrr_intsignal:1;
+        /** enable_mxif2_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intsignal:1;
+        /** enable_mxif2_rch1_eccprot_correrr_intsignal : RO; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_correrr_intsignal:1;
+        /** enable_mxif2_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intsignal:1;
+        /** enable_mxif2_bch_eccprot_correrr_intsignal : RO; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_correrr_intsignal:1;
+        /** enable_mxif2_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intsignal:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dmac_commonreg_intsignal_enable0_reg_t;
+
+/** Type of commonreg_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** slvif_commonreg_dec_err_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_dec_err_intstat:1;
+        /** slvif_commonreg_wr2ro_err_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wr2ro_err_intstat:1;
+        /** slvif_commonreg_rd2wo_err_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_rd2wo_err_intstat:1;
+        /** slvif_commonreg_wronhold_err_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wronhold_err_intstat:1;
+        uint32_t reserved_4:3;
+        /** slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wrparity_err_intstat:1;
+        /** slvif_undefinedreg_dec_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_undefinedreg_dec_err_intstat:1;
+        /** mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch0_eccprot_correrr_intstat:1;
+        /** mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch0_eccprot_uncorrerr_intstat:1;
+        /** mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch1_eccprot_correrr_intstat:1;
+        /** mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch1_eccprot_uncorrerr_intstat:1;
+        /** mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_bch_eccprot_correrr_intstat:1;
+        /** mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_bch_eccprot_uncorrerr_intstat:1;
+        /** mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch0_eccprot_correrr_intstat:1;
+        /** mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch0_eccprot_uncorrerr_intstat:1;
+        /** mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch1_eccprot_correrr_intstat:1;
+        /** mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch1_eccprot_uncorrerr_intstat:1;
+        /** mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_bch_eccprot_correrr_intstat:1;
+        /** mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_bch_eccprot_uncorrerr_intstat:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dmac_commonreg_intstatus0_reg_t;
+
+/** Type of ch1_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_block_tfr_done_intstat:1;
+        /** ch1_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch1_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_transcomp_intstat:1;
+        /** ch1_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_transcomp_intstat:1;
+        /** ch1_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_dec_err_intstat:1;
+        /** ch1_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_dec_err_intstat:1;
+        /** ch1_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_slv_err_intstat:1;
+        /** ch1_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_slv_err_intstat:1;
+        /** ch1_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_rd_dec_err_intstat:1;
+        /** ch1_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_wr_dec_err_intstat:1;
+        /** ch1_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_rd_slv_err_intstat:1;
+        /** ch1_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_wr_slv_err_intstat:1;
+        /** ch1_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch1_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch1_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_dec_err_intstat:1;
+        /** ch1_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wr2ro_err_intstat:1;
+        /** ch1_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_rd2rwo_err_intstat:1;
+        /** ch1_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wronchen_err_intstat:1;
+        /** ch1_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch1_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch1_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch1_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_lock_cleared_intstat:1;
+        /** ch1_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_src_suspended_intstat:1;
+        /** ch1_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_suspended_intstat:1;
+        /** ch1_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_disabled_intstat:1;
+        /** ch1_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch1_intstatus_enable0_reg_t;
+
+/** Type of ch1_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_chmem_correrr_intstat:1;
+        /** ch1_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch1_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch1_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch1_intstatus_enable1_reg_t;
+
+/** Type of ch1_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_block_tfr_done_intstat:1;
+        /** ch1_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch1_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_transcomp_intstat:1;
+        /** ch1_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_transcomp_intstat:1;
+        /** ch1_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_dec_err_intstat:1;
+        /** ch1_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_dec_err_intstat:1;
+        /** ch1_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_slv_err_intstat:1;
+        /** ch1_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_slv_err_intstat:1;
+        /** ch1_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lli_rd_dec_err_intstat:1;
+        /** ch1_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lli_wr_dec_err_intstat:1;
+        /** ch1_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lli_rd_slv_err_intstat:1;
+        /** ch1_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lli_wr_slv_err_intstat:1;
+        /** ch1_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch1_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch1_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_dec_err_intstat:1;
+        /** ch1_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_wr2ro_err_intstat:1;
+        /** ch1_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_rd2rwo_err_intstat:1;
+        /** ch1_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_wronchen_err_intstat:1;
+        /** ch1_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch1_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch1_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch1_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ch_lock_cleared_intstat:1;
+        /** ch1_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ch_src_suspended_intstat:1;
+        /** ch1_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ch_suspended_intstat:1;
+        /** ch1_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ch_disabled_intstat:1;
+        /** ch1_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch1_intstatus0_reg_t;
+
+/** Type of ch1_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ecc_prot_chmem_correrr_intstat:1;
+        /** ch1_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch1_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch1_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch1_intstatus1_reg_t;
+
+/** Type of ch1_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_block_tfr_done_intsignal:1;
+        /** ch1_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dma_tfr_done_intsignal:1;
+        uint32_t reserved_2:1;
+        /** ch1_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_transcomp_intsignal:1;
+        /** ch1_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_transcomp_intsignal:1;
+        /** ch1_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_dec_err_intsignal:1;
+        /** ch1_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_dec_err_intsignal:1;
+        /** ch1_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_slv_err_intsignal:1;
+        /** ch1_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_slv_err_intsignal:1;
+        /** ch1_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_rd_dec_err_intsignal:1;
+        /** ch1_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_wr_dec_err_intsignal:1;
+        /** ch1_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_rd_slv_err_intsignal:1;
+        /** ch1_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_wr_slv_err_intsignal:1;
+        /** ch1_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_shadowreg_or_lli_invalid_err_intsignal:1;
+        /** ch1_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_multiblktype_err_intsignal:1;
+        uint32_t reserved_15:1;
+        /** ch1_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_dec_err_intsignal:1;
+        /** ch1_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wr2ro_err_intsignal:1;
+        /** ch1_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_rd2rwo_err_intsignal:1;
+        /** ch1_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wronchen_err_intsignal:1;
+        /** ch1_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
+        /** ch1_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wronhold_err_intsignal:1;
+        uint32_t reserved_22:3;
+        /** ch1_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wrparity_err_intsignal:1;
+        uint32_t reserved_26:1;
+        /** ch1_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_lock_cleared_intsignal:1;
+        /** ch1_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_src_suspended_intsignal:1;
+        /** ch1_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_suspended_intsignal:1;
+        /** ch1_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_disabled_intsignal:1;
+        /** ch1_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_aborted_intsignal:1;
+    };
+    uint32_t val;
+} dmac_ch1_intsignal_enable0_reg_t;
+
+/** Type of ch1_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_chmem_correrr_intsignal:1;
+        /** ch1_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
+        /** ch1_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_uidmem_correrr_intsignal:1;
+        /** ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch1_intsignal_enable1_reg_t;
+
+/** Type of ch1_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_block_tfr_done_intstat:1;
+        /** ch1_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch1_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_src_transcomp_intstat:1;
+        /** ch1_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_dst_transcomp_intstat:1;
+        /** ch1_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_src_dec_err_intstat:1;
+        /** ch1_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_dst_dec_err_intstat:1;
+        /** ch1_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_src_slv_err_intstat:1;
+        /** ch1_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_dst_slv_err_intstat:1;
+        /** ch1_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_lli_rd_dec_err_intstat:1;
+        /** ch1_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_lli_wr_dec_err_intstat:1;
+        /** ch1_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_lli_rd_slv_err_intstat:1;
+        /** ch1_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_lli_wr_slv_err_intstat:1;
+        /** ch1_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch1_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch1_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_dec_err_intstat:1;
+        /** ch1_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_wr2ro_err_intstat:1;
+        /** ch1_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_rd2rwo_err_intstat:1;
+        /** ch1_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_wronchen_err_intstat:1;
+        /** ch1_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch1_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch1_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch1_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ch_lock_cleared_intstat:1;
+        /** ch1_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ch_src_suspended_intstat:1;
+        /** ch1_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ch_suspended_intstat:1;
+        /** ch1_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ch_disabled_intstat:1;
+        /** ch1_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch1_intclear0_reg_t;
+
+/** Type of ch1_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ecc_prot_chmem_correrr_intstat:1;
+        /** ch1_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch1_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch1_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch1_intclear1_reg_t;
+
+/** Type of ch2_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_block_tfr_done_intstat:1;
+        /** ch2_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch2_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_transcomp_intstat:1;
+        /** ch2_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_transcomp_intstat:1;
+        /** ch2_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_dec_err_intstat:1;
+        /** ch2_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_dec_err_intstat:1;
+        /** ch2_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_slv_err_intstat:1;
+        /** ch2_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_slv_err_intstat:1;
+        /** ch2_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_rd_dec_err_intstat:1;
+        /** ch2_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_wr_dec_err_intstat:1;
+        /** ch2_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_rd_slv_err_intstat:1;
+        /** ch2_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_wr_slv_err_intstat:1;
+        /** ch2_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch2_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch2_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_dec_err_intstat:1;
+        /** ch2_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wr2ro_err_intstat:1;
+        /** ch2_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_rd2rwo_err_intstat:1;
+        /** ch2_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wronchen_err_intstat:1;
+        /** ch2_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch2_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch2_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch2_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_lock_cleared_intstat:1;
+        /** ch2_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_src_suspended_intstat:1;
+        /** ch2_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_suspended_intstat:1;
+        /** ch2_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_disabled_intstat:1;
+        /** ch2_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch2_intstatus_enable0_reg_t;
+
+/** Type of ch2_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_chmem_correrr_intstat:1;
+        /** ch2_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch2_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch2_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch2_intstatus_enable1_reg_t;
+
+/** Type of ch2_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_block_tfr_done_intstat:1;
+        /** ch2_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch2_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_transcomp_intstat:1;
+        /** ch2_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_transcomp_intstat:1;
+        /** ch2_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_dec_err_intstat:1;
+        /** ch2_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_dec_err_intstat:1;
+        /** ch2_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_slv_err_intstat:1;
+        /** ch2_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_slv_err_intstat:1;
+        /** ch2_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lli_rd_dec_err_intstat:1;
+        /** ch2_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lli_wr_dec_err_intstat:1;
+        /** ch2_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lli_rd_slv_err_intstat:1;
+        /** ch2_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lli_wr_slv_err_intstat:1;
+        /** ch2_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch2_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch2_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_dec_err_intstat:1;
+        /** ch2_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_wr2ro_err_intstat:1;
+        /** ch2_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_rd2rwo_err_intstat:1;
+        /** ch2_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_wronchen_err_intstat:1;
+        /** ch2_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch2_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch2_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch2_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ch_lock_cleared_intstat:1;
+        /** ch2_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ch_src_suspended_intstat:1;
+        /** ch2_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ch_suspended_intstat:1;
+        /** ch2_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ch_disabled_intstat:1;
+        /** ch2_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch2_intstatus0_reg_t;
+
+/** Type of ch2_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ecc_prot_chmem_correrr_intstat:1;
+        /** ch2_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch2_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch2_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch2_intstatus1_reg_t;
+
+/** Type of ch2_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_block_tfr_done_intsignal:1;
+        /** ch2_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dma_tfr_done_intsignal:1;
+        uint32_t reserved_2:1;
+        /** ch2_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_transcomp_intsignal:1;
+        /** ch2_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_transcomp_intsignal:1;
+        /** ch2_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_dec_err_intsignal:1;
+        /** ch2_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_dec_err_intsignal:1;
+        /** ch2_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_slv_err_intsignal:1;
+        /** ch2_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_slv_err_intsignal:1;
+        /** ch2_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_rd_dec_err_intsignal:1;
+        /** ch2_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_wr_dec_err_intsignal:1;
+        /** ch2_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_rd_slv_err_intsignal:1;
+        /** ch2_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_wr_slv_err_intsignal:1;
+        /** ch2_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_shadowreg_or_lli_invalid_err_intsignal:1;
+        /** ch2_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_multiblktype_err_intsignal:1;
+        uint32_t reserved_15:1;
+        /** ch2_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_dec_err_intsignal:1;
+        /** ch2_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wr2ro_err_intsignal:1;
+        /** ch2_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_rd2rwo_err_intsignal:1;
+        /** ch2_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wronchen_err_intsignal:1;
+        /** ch2_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
+        /** ch2_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wronhold_err_intsignal:1;
+        uint32_t reserved_22:3;
+        /** ch2_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wrparity_err_intsignal:1;
+        uint32_t reserved_26:1;
+        /** ch2_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_lock_cleared_intsignal:1;
+        /** ch2_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_src_suspended_intsignal:1;
+        /** ch2_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_suspended_intsignal:1;
+        /** ch2_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_disabled_intsignal:1;
+        /** ch2_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_aborted_intsignal:1;
+    };
+    uint32_t val;
+} dmac_ch2_intsignal_enable0_reg_t;
+
+/** Type of ch2_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_chmem_correrr_intsignal:1;
+        /** ch2_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
+        /** ch2_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_uidmem_correrr_intsignal:1;
+        /** ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch2_intsignal_enable1_reg_t;
+
+/** Type of ch2_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_block_tfr_done_intstat:1;
+        /** ch2_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch2_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_src_transcomp_intstat:1;
+        /** ch2_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_dst_transcomp_intstat:1;
+        /** ch2_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_src_dec_err_intstat:1;
+        /** ch2_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_dst_dec_err_intstat:1;
+        /** ch2_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_src_slv_err_intstat:1;
+        /** ch2_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_dst_slv_err_intstat:1;
+        /** ch2_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_lli_rd_dec_err_intstat:1;
+        /** ch2_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_lli_wr_dec_err_intstat:1;
+        /** ch2_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_lli_rd_slv_err_intstat:1;
+        /** ch2_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_lli_wr_slv_err_intstat:1;
+        /** ch2_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch2_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch2_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_dec_err_intstat:1;
+        /** ch2_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_wr2ro_err_intstat:1;
+        /** ch2_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_rd2rwo_err_intstat:1;
+        /** ch2_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_wronchen_err_intstat:1;
+        /** ch2_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch2_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch2_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch2_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ch_lock_cleared_intstat:1;
+        /** ch2_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ch_src_suspended_intstat:1;
+        /** ch2_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ch_suspended_intstat:1;
+        /** ch2_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ch_disabled_intstat:1;
+        /** ch2_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch2_intclear0_reg_t;
+
+/** Type of ch2_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ecc_prot_chmem_correrr_intstat:1;
+        /** ch2_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch2_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch2_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch2_intclear1_reg_t;
+
+/** Type of ch3_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_block_tfr_done_intstat:1;
+        /** ch3_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch3_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_transcomp_intstat:1;
+        /** ch3_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_transcomp_intstat:1;
+        /** ch3_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_dec_err_intstat:1;
+        /** ch3_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_dec_err_intstat:1;
+        /** ch3_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_slv_err_intstat:1;
+        /** ch3_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_slv_err_intstat:1;
+        /** ch3_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_rd_dec_err_intstat:1;
+        /** ch3_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_wr_dec_err_intstat:1;
+        /** ch3_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_rd_slv_err_intstat:1;
+        /** ch3_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_wr_slv_err_intstat:1;
+        /** ch3_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch3_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch3_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_dec_err_intstat:1;
+        /** ch3_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wr2ro_err_intstat:1;
+        /** ch3_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_rd2rwo_err_intstat:1;
+        /** ch3_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wronchen_err_intstat:1;
+        /** ch3_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch3_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch3_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch3_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_lock_cleared_intstat:1;
+        /** ch3_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_src_suspended_intstat:1;
+        /** ch3_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_suspended_intstat:1;
+        /** ch3_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_disabled_intstat:1;
+        /** ch3_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch3_intstatus_enable0_reg_t;
+
+/** Type of ch3_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_chmem_correrr_intstat:1;
+        /** ch3_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch3_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch3_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch3_intstatus_enable1_reg_t;
+
+/** Type of ch3_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_block_tfr_done_intstat:1;
+        /** ch3_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch3_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_transcomp_intstat:1;
+        /** ch3_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_transcomp_intstat:1;
+        /** ch3_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_dec_err_intstat:1;
+        /** ch3_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_dec_err_intstat:1;
+        /** ch3_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_slv_err_intstat:1;
+        /** ch3_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_slv_err_intstat:1;
+        /** ch3_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lli_rd_dec_err_intstat:1;
+        /** ch3_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lli_wr_dec_err_intstat:1;
+        /** ch3_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lli_rd_slv_err_intstat:1;
+        /** ch3_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lli_wr_slv_err_intstat:1;
+        /** ch3_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch3_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch3_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_dec_err_intstat:1;
+        /** ch3_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_wr2ro_err_intstat:1;
+        /** ch3_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_rd2rwo_err_intstat:1;
+        /** ch3_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_wronchen_err_intstat:1;
+        /** ch3_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch3_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch3_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch3_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ch_lock_cleared_intstat:1;
+        /** ch3_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ch_src_suspended_intstat:1;
+        /** ch3_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ch_suspended_intstat:1;
+        /** ch3_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ch_disabled_intstat:1;
+        /** ch3_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch3_intstatus0_reg_t;
+
+/** Type of ch3_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ecc_prot_chmem_correrr_intstat:1;
+        /** ch3_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch3_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch3_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch3_intstatus1_reg_t;
+
+/** Type of ch3_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_block_tfr_done_intsignal:1;
+        /** ch3_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dma_tfr_done_intsignal:1;
+        uint32_t reserved_2:1;
+        /** ch3_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_transcomp_intsignal:1;
+        /** ch3_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_transcomp_intsignal:1;
+        /** ch3_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_dec_err_intsignal:1;
+        /** ch3_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_dec_err_intsignal:1;
+        /** ch3_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_slv_err_intsignal:1;
+        /** ch3_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_slv_err_intsignal:1;
+        /** ch3_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_rd_dec_err_intsignal:1;
+        /** ch3_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_wr_dec_err_intsignal:1;
+        /** ch3_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_rd_slv_err_intsignal:1;
+        /** ch3_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_wr_slv_err_intsignal:1;
+        /** ch3_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_shadowreg_or_lli_invalid_err_intsignal:1;
+        /** ch3_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_multiblktype_err_intsignal:1;
+        uint32_t reserved_15:1;
+        /** ch3_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_dec_err_intsignal:1;
+        /** ch3_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wr2ro_err_intsignal:1;
+        /** ch3_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_rd2rwo_err_intsignal:1;
+        /** ch3_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wronchen_err_intsignal:1;
+        /** ch3_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
+        /** ch3_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wronhold_err_intsignal:1;
+        uint32_t reserved_22:3;
+        /** ch3_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wrparity_err_intsignal:1;
+        uint32_t reserved_26:1;
+        /** ch3_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_lock_cleared_intsignal:1;
+        /** ch3_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_src_suspended_intsignal:1;
+        /** ch3_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_suspended_intsignal:1;
+        /** ch3_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_disabled_intsignal:1;
+        /** ch3_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_aborted_intsignal:1;
+    };
+    uint32_t val;
+} dmac_ch3_intsignal_enable0_reg_t;
+
+/** Type of ch3_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_chmem_correrr_intsignal:1;
+        /** ch3_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
+        /** ch3_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_uidmem_correrr_intsignal:1;
+        /** ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch3_intsignal_enable1_reg_t;
+
+/** Type of ch3_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_block_tfr_done_intstat:1;
+        /** ch3_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch3_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_src_transcomp_intstat:1;
+        /** ch3_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_dst_transcomp_intstat:1;
+        /** ch3_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_src_dec_err_intstat:1;
+        /** ch3_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_dst_dec_err_intstat:1;
+        /** ch3_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_src_slv_err_intstat:1;
+        /** ch3_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_dst_slv_err_intstat:1;
+        /** ch3_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_lli_rd_dec_err_intstat:1;
+        /** ch3_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_lli_wr_dec_err_intstat:1;
+        /** ch3_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_lli_rd_slv_err_intstat:1;
+        /** ch3_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_lli_wr_slv_err_intstat:1;
+        /** ch3_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch3_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch3_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_dec_err_intstat:1;
+        /** ch3_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_wr2ro_err_intstat:1;
+        /** ch3_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_rd2rwo_err_intstat:1;
+        /** ch3_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_wronchen_err_intstat:1;
+        /** ch3_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch3_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch3_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch3_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ch_lock_cleared_intstat:1;
+        /** ch3_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ch_src_suspended_intstat:1;
+        /** ch3_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ch_suspended_intstat:1;
+        /** ch3_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ch_disabled_intstat:1;
+        /** ch3_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch3_intclear0_reg_t;
+
+/** Type of ch3_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ecc_prot_chmem_correrr_intstat:1;
+        /** ch3_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch3_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch3_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch3_intclear1_reg_t;
+
+/** Type of ch4_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_block_tfr_done_intstat:1;
+        /** ch4_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch4_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_transcomp_intstat:1;
+        /** ch4_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_transcomp_intstat:1;
+        /** ch4_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_dec_err_intstat:1;
+        /** ch4_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_dec_err_intstat:1;
+        /** ch4_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_slv_err_intstat:1;
+        /** ch4_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_slv_err_intstat:1;
+        /** ch4_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_rd_dec_err_intstat:1;
+        /** ch4_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_wr_dec_err_intstat:1;
+        /** ch4_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_rd_slv_err_intstat:1;
+        /** ch4_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_wr_slv_err_intstat:1;
+        /** ch4_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch4_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch4_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_dec_err_intstat:1;
+        /** ch4_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wr2ro_err_intstat:1;
+        /** ch4_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_rd2rwo_err_intstat:1;
+        /** ch4_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wronchen_err_intstat:1;
+        /** ch4_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch4_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch4_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch4_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_lock_cleared_intstat:1;
+        /** ch4_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_src_suspended_intstat:1;
+        /** ch4_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_suspended_intstat:1;
+        /** ch4_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_disabled_intstat:1;
+        /** ch4_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch4_intstatus_enable0_reg_t;
+
+/** Type of ch4_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_chmem_correrr_intstat:1;
+        /** ch4_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch4_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch4_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch4_intstatus_enable1_reg_t;
+
+/** Type of ch4_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_block_tfr_done_intstat:1;
+        /** ch4_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch4_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_transcomp_intstat:1;
+        /** ch4_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_transcomp_intstat:1;
+        /** ch4_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_dec_err_intstat:1;
+        /** ch4_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_dec_err_intstat:1;
+        /** ch4_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_slv_err_intstat:1;
+        /** ch4_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_slv_err_intstat:1;
+        /** ch4_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lli_rd_dec_err_intstat:1;
+        /** ch4_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lli_wr_dec_err_intstat:1;
+        /** ch4_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lli_rd_slv_err_intstat:1;
+        /** ch4_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lli_wr_slv_err_intstat:1;
+        /** ch4_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch4_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch4_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_dec_err_intstat:1;
+        /** ch4_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_wr2ro_err_intstat:1;
+        /** ch4_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_rd2rwo_err_intstat:1;
+        /** ch4_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_wronchen_err_intstat:1;
+        /** ch4_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch4_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch4_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch4_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_lock_cleared_intstat:1;
+        /** ch4_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_src_suspended_intstat:1;
+        /** ch4_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_suspended_intstat:1;
+        /** ch4_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_disabled_intstat:1;
+        /** ch4_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch4_intstatus0_reg_t;
+
+/** Type of ch4_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ecc_prot_chmem_correrr_intstat:1;
+        /** ch4_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch4_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch4_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch4_intstatus1_reg_t;
+
+/** Type of ch4_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_block_tfr_done_intsignal:1;
+        /** ch4_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dma_tfr_done_intsignal:1;
+        uint32_t reserved_2:1;
+        /** ch4_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_transcomp_intsignal:1;
+        /** ch4_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_transcomp_intsignal:1;
+        /** ch4_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_dec_err_intsignal:1;
+        /** ch4_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_dec_err_intsignal:1;
+        /** ch4_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_slv_err_intsignal:1;
+        /** ch4_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_slv_err_intsignal:1;
+        /** ch4_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_rd_dec_err_intsignal:1;
+        /** ch4_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_wr_dec_err_intsignal:1;
+        /** ch4_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_rd_slv_err_intsignal:1;
+        /** ch4_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_wr_slv_err_intsignal:1;
+        /** ch4_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_shadowreg_or_lli_invalid_err_intsignal:1;
+        /** ch4_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_multiblktype_err_intsignal:1;
+        uint32_t reserved_15:1;
+        /** ch4_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_dec_err_intsignal:1;
+        /** ch4_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wr2ro_err_intsignal:1;
+        /** ch4_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_rd2rwo_err_intsignal:1;
+        /** ch4_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wronchen_err_intsignal:1;
+        /** ch4_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
+        /** ch4_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wronhold_err_intsignal:1;
+        uint32_t reserved_22:3;
+        /** ch4_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wrparity_err_intsignal:1;
+        uint32_t reserved_26:1;
+        /** ch4_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_lock_cleared_intsignal:1;
+        /** ch4_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_src_suspended_intsignal:1;
+        /** ch4_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_suspended_intsignal:1;
+        /** ch4_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_disabled_intsignal:1;
+        /** ch4_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_aborted_intsignal:1;
+    };
+    uint32_t val;
+} dmac_ch4_intsignal_enable0_reg_t;
+
+/** Type of ch4_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_chmem_correrr_intsignal:1;
+        /** ch4_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
+        /** ch4_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_uidmem_correrr_intsignal:1;
+        /** ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch4_intsignal_enable1_reg_t;
+
+/** Type of ch4_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_block_tfr_done_intstat:1;
+        /** ch4_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch4_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_src_transcomp_intstat:1;
+        /** ch4_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_dst_transcomp_intstat:1;
+        /** ch4_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_src_dec_err_intstat:1;
+        /** ch4_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_dst_dec_err_intstat:1;
+        /** ch4_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_src_slv_err_intstat:1;
+        /** ch4_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_dst_slv_err_intstat:1;
+        /** ch4_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_lli_rd_dec_err_intstat:1;
+        /** ch4_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_lli_wr_dec_err_intstat:1;
+        /** ch4_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_lli_rd_slv_err_intstat:1;
+        /** ch4_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_lli_wr_slv_err_intstat:1;
+        /** ch4_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch4_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch4_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_dec_err_intstat:1;
+        /** ch4_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_wr2ro_err_intstat:1;
+        /** ch4_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_rd2rwo_err_intstat:1;
+        /** ch4_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_wronchen_err_intstat:1;
+        /** ch4_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch4_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch4_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch4_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ch_lock_cleared_intstat:1;
+        /** ch4_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ch_src_suspended_intstat:1;
+        /** ch4_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ch_suspended_intstat:1;
+        /** ch4_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ch_disabled_intstat:1;
+        /** ch4_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch4_intclear0_reg_t;
+
+/** Type of ch4_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ecc_prot_chmem_correrr_intstat:1;
+        /** ch4_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch4_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch4_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch4_intclear1_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of ch1_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_cmpltd_blk_tfr_size:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch1_status0_reg_t;
+
+/** Type of ch1_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_data_left_in_fifo:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dmac_ch1_status1_reg_t;
+
+/** Type of ch1_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sstat:32;
+    };
+    uint32_t val;
+} dmac_ch1_sstat0_reg_t;
+
+/** Type of ch1_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dstat:32;
+    };
+    uint32_t val;
+} dmac_ch1_dstat0_reg_t;
+
+/** Type of ch1_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch1_sstatar0_reg_t;
+
+/** Type of ch1_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch1_sstatar1_reg_t;
+
+/** Type of ch1_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch1_dstatar0_reg_t;
+
+/** Type of ch1_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch1_dstatar1_reg_t;
+
+/** Type of ch2_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_cmpltd_blk_tfr_size:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch2_status0_reg_t;
+
+/** Type of ch2_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_data_left_in_fifo:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dmac_ch2_status1_reg_t;
+
+/** Type of ch2_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sstat:32;
+    };
+    uint32_t val;
+} dmac_ch2_sstat0_reg_t;
+
+/** Type of ch2_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dstat:32;
+    };
+    uint32_t val;
+} dmac_ch2_dstat0_reg_t;
+
+/** Type of ch2_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch2_sstatar0_reg_t;
+
+/** Type of ch2_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch2_sstatar1_reg_t;
+
+/** Type of ch2_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch2_dstatar0_reg_t;
+
+/** Type of ch2_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch2_dstatar1_reg_t;
+
+/** Type of ch3_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_cmpltd_blk_tfr_size:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch3_status0_reg_t;
+
+/** Type of ch3_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_data_left_in_fifo:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dmac_ch3_status1_reg_t;
+
+/** Type of ch3_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sstat:32;
+    };
+    uint32_t val;
+} dmac_ch3_sstat0_reg_t;
+
+/** Type of ch3_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dstat:32;
+    };
+    uint32_t val;
+} dmac_ch3_dstat0_reg_t;
+
+/** Type of ch3_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch3_sstatar0_reg_t;
+
+/** Type of ch3_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch3_sstatar1_reg_t;
+
+/** Type of ch3_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch3_dstatar0_reg_t;
+
+/** Type of ch3_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch3_dstatar1_reg_t;
+
+/** Type of ch4_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_cmpltd_blk_tfr_size:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch4_status0_reg_t;
+
+/** Type of ch4_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_data_left_in_fifo:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dmac_ch4_status1_reg_t;
+
+/** Type of ch4_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sstat:32;
+    };
+    uint32_t val;
+} dmac_ch4_sstat0_reg_t;
+
+/** Type of ch4_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dstat:32;
+    };
+    uint32_t val;
+} dmac_ch4_dstat0_reg_t;
+
+/** Type of ch4_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch4_sstatar0_reg_t;
+
+/** Type of ch4_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch4_sstatar1_reg_t;
+
+/** Type of ch4_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch4_dstatar0_reg_t;
+
+/** Type of ch4_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch4_dstatar1_reg_t;
+
+
+typedef struct {
+    volatile dmac_id0_reg_t id0;
+    uint32_t reserved_004;
+    volatile dmac_compver0_reg_t compver0;
+    uint32_t reserved_00c;
+    volatile dmac_cfg0_reg_t cfg0;
+    uint32_t reserved_014;
+    volatile dmac_chen0_reg_t chen0;
+    volatile dmac_chen1_reg_t chen1;
+    uint32_t reserved_020[4];
+    volatile dmac_intstatus0_reg_t intstatus0;
+    uint32_t reserved_034;
+    volatile dmac_commonreg_intclear0_reg_t commonreg_intclear0;
+    uint32_t reserved_03c;
+    volatile dmac_commonreg_intstatus_enable0_reg_t commonreg_intstatus_enable0;
+    uint32_t reserved_044;
+    volatile dmac_commonreg_intsignal_enable0_reg_t commonreg_intsignal_enable0;
+    uint32_t reserved_04c;
+    volatile dmac_commonreg_intstatus0_reg_t commonreg_intstatus0;
+    uint32_t reserved_054;
+    volatile dmac_reset0_reg_t reset0;
+    uint32_t reserved_05c;
+    volatile dmac_lowpower_cfg0_reg_t lowpower_cfg0;
+    volatile dmac_lowpower_cfg1_reg_t lowpower_cfg1;
+    uint32_t reserved_068[38];
+    volatile dmac_ch1_sar0_reg_t ch1_sar0;
+    volatile dmac_ch1_sar1_reg_t ch1_sar1;
+    volatile dmac_ch1_dar0_reg_t ch1_dar0;
+    volatile dmac_ch1_dar1_reg_t ch1_dar1;
+    volatile dmac_ch1_block_ts0_reg_t ch1_block_ts0;
+    uint32_t reserved_114;
+    volatile dmac_ch1_ctl0_reg_t ch1_ctl0;
+    volatile dmac_ch1_ctl1_reg_t ch1_ctl1;
+    volatile dmac_ch1_cfg0_reg_t ch1_cfg0;
+    volatile dmac_ch1_cfg1_reg_t ch1_cfg1;
+    volatile dmac_ch1_llp0_reg_t ch1_llp0;
+    volatile dmac_ch1_llp1_reg_t ch1_llp1;
+    volatile dmac_ch1_status0_reg_t ch1_status0;
+    volatile dmac_ch1_status1_reg_t ch1_status1;
+    volatile dmac_ch1_swhssrc0_reg_t ch1_swhssrc0;
+    uint32_t reserved_13c;
+    volatile dmac_ch1_swhsdst0_reg_t ch1_swhsdst0;
+    uint32_t reserved_144;
+    volatile dmac_ch1_blk_tfr_resumereq0_reg_t ch1_blk_tfr_resumereq0;
+    uint32_t reserved_14c;
+    volatile dmac_ch1_axi_id0_reg_t ch1_axi_id0;
+    uint32_t reserved_154;
+    volatile dmac_ch1_axi_qos0_reg_t ch1_axi_qos0;
+    uint32_t reserved_15c;
+    volatile dmac_ch1_sstat0_reg_t ch1_sstat0;
+    uint32_t reserved_164;
+    volatile dmac_ch1_dstat0_reg_t ch1_dstat0;
+    uint32_t reserved_16c;
+    volatile dmac_ch1_sstatar0_reg_t ch1_sstatar0;
+    volatile dmac_ch1_sstatar1_reg_t ch1_sstatar1;
+    volatile dmac_ch1_dstatar0_reg_t ch1_dstatar0;
+    volatile dmac_ch1_dstatar1_reg_t ch1_dstatar1;
+    volatile dmac_ch1_intstatus_enable0_reg_t ch1_intstatus_enable0;
+    volatile dmac_ch1_intstatus_enable1_reg_t ch1_intstatus_enable1;
+    volatile dmac_ch1_intstatus0_reg_t ch1_intstatus0;
+    volatile dmac_ch1_intstatus1_reg_t ch1_intstatus1;
+    volatile dmac_ch1_intsignal_enable0_reg_t ch1_intsignal_enable0;
+    volatile dmac_ch1_intsignal_enable1_reg_t ch1_intsignal_enable1;
+    volatile dmac_ch1_intclear0_reg_t ch1_intclear0;
+    volatile dmac_ch1_intclear1_reg_t ch1_intclear1;
+    uint32_t reserved_1a0[24];
+    volatile dmac_ch2_sar0_reg_t ch2_sar0;
+    volatile dmac_ch2_sar1_reg_t ch2_sar1;
+    volatile dmac_ch2_dar0_reg_t ch2_dar0;
+    volatile dmac_ch2_dar1_reg_t ch2_dar1;
+    volatile dmac_ch2_block_ts0_reg_t ch2_block_ts0;
+    uint32_t reserved_214;
+    volatile dmac_ch2_ctl0_reg_t ch2_ctl0;
+    volatile dmac_ch2_ctl1_reg_t ch2_ctl1;
+    volatile dmac_ch2_cfg0_reg_t ch2_cfg0;
+    volatile dmac_ch2_cfg1_reg_t ch2_cfg1;
+    volatile dmac_ch2_llp0_reg_t ch2_llp0;
+    volatile dmac_ch2_llp1_reg_t ch2_llp1;
+    volatile dmac_ch2_status0_reg_t ch2_status0;
+    volatile dmac_ch2_status1_reg_t ch2_status1;
+    volatile dmac_ch2_swhssrc0_reg_t ch2_swhssrc0;
+    uint32_t reserved_23c;
+    volatile dmac_ch2_swhsdst0_reg_t ch2_swhsdst0;
+    uint32_t reserved_244;
+    volatile dmac_ch2_blk_tfr_resumereq0_reg_t ch2_blk_tfr_resumereq0;
+    uint32_t reserved_24c;
+    volatile dmac_ch2_axi_id0_reg_t ch2_axi_id0;
+    uint32_t reserved_254;
+    volatile dmac_ch2_axi_qos0_reg_t ch2_axi_qos0;
+    uint32_t reserved_25c;
+    volatile dmac_ch2_sstat0_reg_t ch2_sstat0;
+    uint32_t reserved_264;
+    volatile dmac_ch2_dstat0_reg_t ch2_dstat0;
+    uint32_t reserved_26c;
+    volatile dmac_ch2_sstatar0_reg_t ch2_sstatar0;
+    volatile dmac_ch2_sstatar1_reg_t ch2_sstatar1;
+    volatile dmac_ch2_dstatar0_reg_t ch2_dstatar0;
+    volatile dmac_ch2_dstatar1_reg_t ch2_dstatar1;
+    volatile dmac_ch2_intstatus_enable0_reg_t ch2_intstatus_enable0;
+    volatile dmac_ch2_intstatus_enable1_reg_t ch2_intstatus_enable1;
+    volatile dmac_ch2_intstatus0_reg_t ch2_intstatus0;
+    volatile dmac_ch2_intstatus1_reg_t ch2_intstatus1;
+    volatile dmac_ch2_intsignal_enable0_reg_t ch2_intsignal_enable0;
+    volatile dmac_ch2_intsignal_enable1_reg_t ch2_intsignal_enable1;
+    volatile dmac_ch2_intclear0_reg_t ch2_intclear0;
+    volatile dmac_ch2_intclear1_reg_t ch2_intclear1;
+    uint32_t reserved_2a0[24];
+    volatile dmac_ch3_sar0_reg_t ch3_sar0;
+    volatile dmac_ch3_sar1_reg_t ch3_sar1;
+    volatile dmac_ch3_dar0_reg_t ch3_dar0;
+    volatile dmac_ch3_dar1_reg_t ch3_dar1;
+    volatile dmac_ch3_block_ts0_reg_t ch3_block_ts0;
+    uint32_t reserved_314;
+    volatile dmac_ch3_ctl0_reg_t ch3_ctl0;
+    volatile dmac_ch3_ctl1_reg_t ch3_ctl1;
+    volatile dmac_ch3_cfg0_reg_t ch3_cfg0;
+    volatile dmac_ch3_cfg1_reg_t ch3_cfg1;
+    volatile dmac_ch3_llp0_reg_t ch3_llp0;
+    volatile dmac_ch3_llp1_reg_t ch3_llp1;
+    volatile dmac_ch3_status0_reg_t ch3_status0;
+    volatile dmac_ch3_status1_reg_t ch3_status1;
+    volatile dmac_ch3_swhssrc0_reg_t ch3_swhssrc0;
+    uint32_t reserved_33c;
+    volatile dmac_ch3_swhsdst0_reg_t ch3_swhsdst0;
+    uint32_t reserved_344;
+    volatile dmac_ch3_blk_tfr_resumereq0_reg_t ch3_blk_tfr_resumereq0;
+    uint32_t reserved_34c;
+    volatile dmac_ch3_axi_id0_reg_t ch3_axi_id0;
+    uint32_t reserved_354;
+    volatile dmac_ch3_axi_qos0_reg_t ch3_axi_qos0;
+    uint32_t reserved_35c;
+    volatile dmac_ch3_sstat0_reg_t ch3_sstat0;
+    uint32_t reserved_364;
+    volatile dmac_ch3_dstat0_reg_t ch3_dstat0;
+    uint32_t reserved_36c;
+    volatile dmac_ch3_sstatar0_reg_t ch3_sstatar0;
+    volatile dmac_ch3_sstatar1_reg_t ch3_sstatar1;
+    volatile dmac_ch3_dstatar0_reg_t ch3_dstatar0;
+    volatile dmac_ch3_dstatar1_reg_t ch3_dstatar1;
+    volatile dmac_ch3_intstatus_enable0_reg_t ch3_intstatus_enable0;
+    volatile dmac_ch3_intstatus_enable1_reg_t ch3_intstatus_enable1;
+    volatile dmac_ch3_intstatus0_reg_t ch3_intstatus0;
+    volatile dmac_ch3_intstatus1_reg_t ch3_intstatus1;
+    volatile dmac_ch3_intsignal_enable0_reg_t ch3_intsignal_enable0;
+    volatile dmac_ch3_intsignal_enable1_reg_t ch3_intsignal_enable1;
+    volatile dmac_ch3_intclear0_reg_t ch3_intclear0;
+    volatile dmac_ch3_intclear1_reg_t ch3_intclear1;
+    uint32_t reserved_3a0[24];
+    volatile dmac_ch4_sar0_reg_t ch4_sar0;
+    volatile dmac_ch4_sar1_reg_t ch4_sar1;
+    volatile dmac_ch4_dar0_reg_t ch4_dar0;
+    volatile dmac_ch4_dar1_reg_t ch4_dar1;
+    volatile dmac_ch4_block_ts0_reg_t ch4_block_ts0;
+    uint32_t reserved_414;
+    volatile dmac_ch4_ctl0_reg_t ch4_ctl0;
+    volatile dmac_ch4_ctl1_reg_t ch4_ctl1;
+    volatile dmac_ch4_cfg0_reg_t ch4_cfg0;
+    volatile dmac_ch4_cfg1_reg_t ch4_cfg1;
+    volatile dmac_ch4_llp0_reg_t ch4_llp0;
+    volatile dmac_ch4_llp1_reg_t ch4_llp1;
+    volatile dmac_ch4_status0_reg_t ch4_status0;
+    volatile dmac_ch4_status1_reg_t ch4_status1;
+    volatile dmac_ch4_swhssrc0_reg_t ch4_swhssrc0;
+    uint32_t reserved_43c;
+    volatile dmac_ch4_swhsdst0_reg_t ch4_swhsdst0;
+    uint32_t reserved_444;
+    volatile dmac_ch4_blk_tfr_resumereq0_reg_t ch4_blk_tfr_resumereq0;
+    uint32_t reserved_44c;
+    volatile dmac_ch4_axi_id0_reg_t ch4_axi_id0;
+    uint32_t reserved_454;
+    volatile dmac_ch4_axi_qos0_reg_t ch4_axi_qos0;
+    uint32_t reserved_45c;
+    volatile dmac_ch4_sstat0_reg_t ch4_sstat0;
+    uint32_t reserved_464;
+    volatile dmac_ch4_dstat0_reg_t ch4_dstat0;
+    uint32_t reserved_46c;
+    volatile dmac_ch4_sstatar0_reg_t ch4_sstatar0;
+    volatile dmac_ch4_sstatar1_reg_t ch4_sstatar1;
+    volatile dmac_ch4_dstatar0_reg_t ch4_dstatar0;
+    volatile dmac_ch4_dstatar1_reg_t ch4_dstatar1;
+    volatile dmac_ch4_intstatus_enable0_reg_t ch4_intstatus_enable0;
+    volatile dmac_ch4_intstatus_enable1_reg_t ch4_intstatus_enable1;
+    volatile dmac_ch4_intstatus0_reg_t ch4_intstatus0;
+    volatile dmac_ch4_intstatus1_reg_t ch4_intstatus1;
+    volatile dmac_ch4_intsignal_enable0_reg_t ch4_intsignal_enable0;
+    volatile dmac_ch4_intsignal_enable1_reg_t ch4_intsignal_enable1;
+    volatile dmac_ch4_intclear0_reg_t ch4_intclear0;
+    volatile dmac_ch4_intclear1_reg_t ch4_intclear1;
+} dmac_dev_t;
+
+extern dmac_dev_t GDMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dmac_dev_t) == 0x4a0, "Invalid size of dmac_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_reg.h
new file mode 100644
index 0000000000..6aa7a720ed
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_reg.h
@@ -0,0 +1,6880 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DMAC_ID0_REG register
+ *  NA
+ */
+#define DMAC_ID0_REG (DR_REG_DMAC_BASE + 0x0)
+/** DMAC_DMAC_ID : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_DMAC_ID    0xFFFFFFFFU
+#define DMAC_DMAC_ID_M  (DMAC_DMAC_ID_V << DMAC_DMAC_ID_S)
+#define DMAC_DMAC_ID_V  0xFFFFFFFFU
+#define DMAC_DMAC_ID_S  0
+
+/** DMAC_COMPVER0_REG register
+ *  NA
+ */
+#define DMAC_COMPVER0_REG (DR_REG_DMAC_BASE + 0x8)
+/** DMAC_DMAC_COMPVER : RO; bitpos: [31:0]; default: 842018858;
+ *  NA
+ */
+#define DMAC_DMAC_COMPVER    0xFFFFFFFFU
+#define DMAC_DMAC_COMPVER_M  (DMAC_DMAC_COMPVER_V << DMAC_DMAC_COMPVER_S)
+#define DMAC_DMAC_COMPVER_V  0xFFFFFFFFU
+#define DMAC_DMAC_COMPVER_S  0
+
+/** DMAC_CFG0_REG register
+ *  NA
+ */
+#define DMAC_CFG0_REG (DR_REG_DMAC_BASE + 0x10)
+/** DMAC_DMAC_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_DMAC_EN    (BIT(0))
+#define DMAC_DMAC_EN_M  (DMAC_DMAC_EN_V << DMAC_DMAC_EN_S)
+#define DMAC_DMAC_EN_V  0x00000001U
+#define DMAC_DMAC_EN_S  0
+/** DMAC_INT_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_INT_EN    (BIT(1))
+#define DMAC_INT_EN_M  (DMAC_INT_EN_V << DMAC_INT_EN_S)
+#define DMAC_INT_EN_V  0x00000001U
+#define DMAC_INT_EN_S  1
+
+/** DMAC_CHEN0_REG register
+ *  NA
+ */
+#define DMAC_CHEN0_REG (DR_REG_DMAC_BASE + 0x18)
+/** DMAC_CH1_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_EN    (BIT(0))
+#define DMAC_CH1_EN_M  (DMAC_CH1_EN_V << DMAC_CH1_EN_S)
+#define DMAC_CH1_EN_V  0x00000001U
+#define DMAC_CH1_EN_S  0
+/** DMAC_CH2_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_EN    (BIT(1))
+#define DMAC_CH2_EN_M  (DMAC_CH2_EN_V << DMAC_CH2_EN_S)
+#define DMAC_CH2_EN_V  0x00000001U
+#define DMAC_CH2_EN_S  1
+/** DMAC_CH3_EN : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_EN    (BIT(2))
+#define DMAC_CH3_EN_M  (DMAC_CH3_EN_V << DMAC_CH3_EN_S)
+#define DMAC_CH3_EN_V  0x00000001U
+#define DMAC_CH3_EN_S  2
+/** DMAC_CH4_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_EN    (BIT(3))
+#define DMAC_CH4_EN_M  (DMAC_CH4_EN_V << DMAC_CH4_EN_S)
+#define DMAC_CH4_EN_V  0x00000001U
+#define DMAC_CH4_EN_S  3
+/** DMAC_CH1_EN_WE : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_EN_WE    (BIT(8))
+#define DMAC_CH1_EN_WE_M  (DMAC_CH1_EN_WE_V << DMAC_CH1_EN_WE_S)
+#define DMAC_CH1_EN_WE_V  0x00000001U
+#define DMAC_CH1_EN_WE_S  8
+/** DMAC_CH2_EN_WE : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_EN_WE    (BIT(9))
+#define DMAC_CH2_EN_WE_M  (DMAC_CH2_EN_WE_V << DMAC_CH2_EN_WE_S)
+#define DMAC_CH2_EN_WE_V  0x00000001U
+#define DMAC_CH2_EN_WE_S  9
+/** DMAC_CH3_EN_WE : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_EN_WE    (BIT(10))
+#define DMAC_CH3_EN_WE_M  (DMAC_CH3_EN_WE_V << DMAC_CH3_EN_WE_S)
+#define DMAC_CH3_EN_WE_V  0x00000001U
+#define DMAC_CH3_EN_WE_S  10
+/** DMAC_CH4_EN_WE : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_EN_WE    (BIT(11))
+#define DMAC_CH4_EN_WE_M  (DMAC_CH4_EN_WE_V << DMAC_CH4_EN_WE_S)
+#define DMAC_CH4_EN_WE_V  0x00000001U
+#define DMAC_CH4_EN_WE_S  11
+/** DMAC_CH1_SUSP : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SUSP    (BIT(16))
+#define DMAC_CH1_SUSP_M  (DMAC_CH1_SUSP_V << DMAC_CH1_SUSP_S)
+#define DMAC_CH1_SUSP_V  0x00000001U
+#define DMAC_CH1_SUSP_S  16
+/** DMAC_CH2_SUSP : R/W; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SUSP    (BIT(17))
+#define DMAC_CH2_SUSP_M  (DMAC_CH2_SUSP_V << DMAC_CH2_SUSP_S)
+#define DMAC_CH2_SUSP_V  0x00000001U
+#define DMAC_CH2_SUSP_S  17
+/** DMAC_CH3_SUSP : R/W; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SUSP    (BIT(18))
+#define DMAC_CH3_SUSP_M  (DMAC_CH3_SUSP_V << DMAC_CH3_SUSP_S)
+#define DMAC_CH3_SUSP_V  0x00000001U
+#define DMAC_CH3_SUSP_S  18
+/** DMAC_CH4_SUSP : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SUSP    (BIT(19))
+#define DMAC_CH4_SUSP_M  (DMAC_CH4_SUSP_V << DMAC_CH4_SUSP_S)
+#define DMAC_CH4_SUSP_V  0x00000001U
+#define DMAC_CH4_SUSP_S  19
+/** DMAC_CH1_SUSP_WE : WO; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SUSP_WE    (BIT(24))
+#define DMAC_CH1_SUSP_WE_M  (DMAC_CH1_SUSP_WE_V << DMAC_CH1_SUSP_WE_S)
+#define DMAC_CH1_SUSP_WE_V  0x00000001U
+#define DMAC_CH1_SUSP_WE_S  24
+/** DMAC_CH2_SUSP_WE : WO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SUSP_WE    (BIT(25))
+#define DMAC_CH2_SUSP_WE_M  (DMAC_CH2_SUSP_WE_V << DMAC_CH2_SUSP_WE_S)
+#define DMAC_CH2_SUSP_WE_V  0x00000001U
+#define DMAC_CH2_SUSP_WE_S  25
+/** DMAC_CH3_SUSP_WE : WO; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SUSP_WE    (BIT(26))
+#define DMAC_CH3_SUSP_WE_M  (DMAC_CH3_SUSP_WE_V << DMAC_CH3_SUSP_WE_S)
+#define DMAC_CH3_SUSP_WE_V  0x00000001U
+#define DMAC_CH3_SUSP_WE_S  26
+/** DMAC_CH4_SUSP_WE : WO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SUSP_WE    (BIT(27))
+#define DMAC_CH4_SUSP_WE_M  (DMAC_CH4_SUSP_WE_V << DMAC_CH4_SUSP_WE_S)
+#define DMAC_CH4_SUSP_WE_V  0x00000001U
+#define DMAC_CH4_SUSP_WE_S  27
+
+/** DMAC_CHEN1_REG register
+ *  NA
+ */
+#define DMAC_CHEN1_REG (DR_REG_DMAC_BASE + 0x1c)
+/** DMAC_CH1_ABORT : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ABORT    (BIT(0))
+#define DMAC_CH1_ABORT_M  (DMAC_CH1_ABORT_V << DMAC_CH1_ABORT_S)
+#define DMAC_CH1_ABORT_V  0x00000001U
+#define DMAC_CH1_ABORT_S  0
+/** DMAC_CH2_ABORT : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ABORT    (BIT(1))
+#define DMAC_CH2_ABORT_M  (DMAC_CH2_ABORT_V << DMAC_CH2_ABORT_S)
+#define DMAC_CH2_ABORT_V  0x00000001U
+#define DMAC_CH2_ABORT_S  1
+/** DMAC_CH3_ABORT : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ABORT    (BIT(2))
+#define DMAC_CH3_ABORT_M  (DMAC_CH3_ABORT_V << DMAC_CH3_ABORT_S)
+#define DMAC_CH3_ABORT_V  0x00000001U
+#define DMAC_CH3_ABORT_S  2
+/** DMAC_CH4_ABORT : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ABORT    (BIT(3))
+#define DMAC_CH4_ABORT_M  (DMAC_CH4_ABORT_V << DMAC_CH4_ABORT_S)
+#define DMAC_CH4_ABORT_V  0x00000001U
+#define DMAC_CH4_ABORT_S  3
+/** DMAC_CH1_ABORT_WE : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ABORT_WE    (BIT(8))
+#define DMAC_CH1_ABORT_WE_M  (DMAC_CH1_ABORT_WE_V << DMAC_CH1_ABORT_WE_S)
+#define DMAC_CH1_ABORT_WE_V  0x00000001U
+#define DMAC_CH1_ABORT_WE_S  8
+/** DMAC_CH2_ABORT_WE : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ABORT_WE    (BIT(9))
+#define DMAC_CH2_ABORT_WE_M  (DMAC_CH2_ABORT_WE_V << DMAC_CH2_ABORT_WE_S)
+#define DMAC_CH2_ABORT_WE_V  0x00000001U
+#define DMAC_CH2_ABORT_WE_S  9
+/** DMAC_CH3_ABORT_WE : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ABORT_WE    (BIT(10))
+#define DMAC_CH3_ABORT_WE_M  (DMAC_CH3_ABORT_WE_V << DMAC_CH3_ABORT_WE_S)
+#define DMAC_CH3_ABORT_WE_V  0x00000001U
+#define DMAC_CH3_ABORT_WE_S  10
+/** DMAC_CH4_ABORT_WE : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ABORT_WE    (BIT(11))
+#define DMAC_CH4_ABORT_WE_M  (DMAC_CH4_ABORT_WE_V << DMAC_CH4_ABORT_WE_S)
+#define DMAC_CH4_ABORT_WE_V  0x00000001U
+#define DMAC_CH4_ABORT_WE_S  11
+
+/** DMAC_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x30)
+/** DMAC_CH1_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_INTSTAT    (BIT(0))
+#define DMAC_CH1_INTSTAT_M  (DMAC_CH1_INTSTAT_V << DMAC_CH1_INTSTAT_S)
+#define DMAC_CH1_INTSTAT_V  0x00000001U
+#define DMAC_CH1_INTSTAT_S  0
+/** DMAC_CH2_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_INTSTAT    (BIT(1))
+#define DMAC_CH2_INTSTAT_M  (DMAC_CH2_INTSTAT_V << DMAC_CH2_INTSTAT_S)
+#define DMAC_CH2_INTSTAT_V  0x00000001U
+#define DMAC_CH2_INTSTAT_S  1
+/** DMAC_CH3_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_INTSTAT    (BIT(2))
+#define DMAC_CH3_INTSTAT_M  (DMAC_CH3_INTSTAT_V << DMAC_CH3_INTSTAT_S)
+#define DMAC_CH3_INTSTAT_V  0x00000001U
+#define DMAC_CH3_INTSTAT_S  2
+/** DMAC_CH4_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_INTSTAT    (BIT(3))
+#define DMAC_CH4_INTSTAT_M  (DMAC_CH4_INTSTAT_V << DMAC_CH4_INTSTAT_S)
+#define DMAC_CH4_INTSTAT_V  0x00000001U
+#define DMAC_CH4_INTSTAT_S  3
+/** DMAC_COMMONREG_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_COMMONREG_INTSTAT    (BIT(16))
+#define DMAC_COMMONREG_INTSTAT_M  (DMAC_COMMONREG_INTSTAT_V << DMAC_COMMONREG_INTSTAT_S)
+#define DMAC_COMMONREG_INTSTAT_V  0x00000001U
+#define DMAC_COMMONREG_INTSTAT_S  16
+
+/** DMAC_COMMONREG_INTCLEAR0_REG register
+ *  NA
+ */
+#define DMAC_COMMONREG_INTCLEAR0_REG (DR_REG_DMAC_BASE + 0x38)
+/** DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT    (BIT(0))
+#define DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S  0
+/** DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT    (BIT(1))
+#define DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S  1
+/** DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT : WO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT    (BIT(2))
+#define DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S  2
+/** DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT    (BIT(3))
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S  3
+/** DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT : WO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT    (BIT(7))
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S  7
+/** DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT    (BIT(8))
+#define DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S  8
+/** DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(9))
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S  9
+/** DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(10))
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  10
+/** DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(11))
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S  11
+/** DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(12))
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  12
+/** DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(13))
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S  13
+/** DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(14))
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S  14
+/** DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(15))
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S  15
+/** DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(16))
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  16
+/** DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(17))
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S  17
+/** DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(18))
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  18
+/** DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(19))
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S  19
+/** DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(20))
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S  20
+
+/** DMAC_COMMONREG_INTSTATUS_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_COMMONREG_INTSTATUS_ENABLE0_REG (DR_REG_DMAC_BASE + 0x40)
+/** DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT    (BIT(0))
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S  0
+/** DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT    (BIT(1))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S  1
+/** DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT    (BIT(2))
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S  2
+/** DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT    (BIT(3))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S  3
+/** DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT : RO; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT    (BIT(7))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S  7
+/** DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT    (BIT(8))
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S  8
+/** DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(9))
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S  9
+/** DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(10))
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  10
+/** DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(11))
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S  11
+/** DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(12))
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  12
+/** DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(13))
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S  13
+/** DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(14))
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S  14
+/** DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(15))
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S  15
+/** DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(16))
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  16
+/** DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(17))
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S  17
+/** DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(18))
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  18
+/** DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(19))
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S  19
+/** DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(20))
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S  20
+
+/** DMAC_COMMONREG_INTSIGNAL_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_COMMONREG_INTSIGNAL_ENABLE0_REG (DR_REG_DMAC_BASE + 0x48)
+/** DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL    (BIT(0))
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_S  0
+/** DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL    (BIT(1))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_S  1
+/** DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL    (BIT(2))
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_S  2
+/** DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL    (BIT(3))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_S  3
+/** DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL : RO; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL    (BIT(7))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_S  7
+/** DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL    (BIT(8))
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_S  8
+/** DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL    (BIT(9))
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_S  9
+/** DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(10))
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_S  10
+/** DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL    (BIT(11))
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_S  11
+/** DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(12))
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_S  12
+/** DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL    (BIT(13))
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_S  13
+/** DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(14))
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_S  14
+/** DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL    (BIT(15))
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_S  15
+/** DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(16))
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_S  16
+/** DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL    (BIT(17))
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_S  17
+/** DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(18))
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_S  18
+/** DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL    (BIT(19))
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_S  19
+/** DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(20))
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_S  20
+
+/** DMAC_COMMONREG_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_COMMONREG_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x50)
+/** DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT    (BIT(0))
+#define DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT_M  (DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V << DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S)
+#define DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S  0
+/** DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT    (BIT(1))
+#define DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_M  (DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V << DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S)
+#define DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S  1
+/** DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT    (BIT(2))
+#define DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_M  (DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V << DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S)
+#define DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S  2
+/** DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT    (BIT(3))
+#define DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_M  (DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V << DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S  3
+/** DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT    (BIT(7))
+#define DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_M  (DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V << DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S  7
+/** DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT    (BIT(8))
+#define DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_M  (DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V << DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S)
+#define DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S  8
+/** DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(9))
+#define DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S  9
+/** DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(10))
+#define DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  10
+/** DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(11))
+#define DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S  11
+/** DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(12))
+#define DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  12
+/** DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(13))
+#define DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S  13
+/** DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(14))
+#define DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S  14
+/** DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(15))
+#define DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S  15
+/** DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(16))
+#define DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  16
+/** DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(17))
+#define DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S  17
+/** DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(18))
+#define DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  18
+/** DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(19))
+#define DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S  19
+/** DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(20))
+#define DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S  20
+
+/** DMAC_RESET0_REG register
+ *  NA
+ */
+#define DMAC_RESET0_REG (DR_REG_DMAC_BASE + 0x58)
+/** DMAC_DMAC_RST : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_DMAC_RST    (BIT(0))
+#define DMAC_DMAC_RST_M  (DMAC_DMAC_RST_V << DMAC_DMAC_RST_S)
+#define DMAC_DMAC_RST_V  0x00000001U
+#define DMAC_DMAC_RST_S  0
+
+/** DMAC_LOWPOWER_CFG0_REG register
+ *  NA
+ */
+#define DMAC_LOWPOWER_CFG0_REG (DR_REG_DMAC_BASE + 0x60)
+/** DMAC_GBL_CSLP_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_GBL_CSLP_EN    (BIT(0))
+#define DMAC_GBL_CSLP_EN_M  (DMAC_GBL_CSLP_EN_V << DMAC_GBL_CSLP_EN_S)
+#define DMAC_GBL_CSLP_EN_V  0x00000001U
+#define DMAC_GBL_CSLP_EN_S  0
+/** DMAC_CHNL_CSLP_EN : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CHNL_CSLP_EN    (BIT(1))
+#define DMAC_CHNL_CSLP_EN_M  (DMAC_CHNL_CSLP_EN_V << DMAC_CHNL_CSLP_EN_S)
+#define DMAC_CHNL_CSLP_EN_V  0x00000001U
+#define DMAC_CHNL_CSLP_EN_S  1
+/** DMAC_SBIU_CSLP_EN : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_SBIU_CSLP_EN    (BIT(2))
+#define DMAC_SBIU_CSLP_EN_M  (DMAC_SBIU_CSLP_EN_V << DMAC_SBIU_CSLP_EN_S)
+#define DMAC_SBIU_CSLP_EN_V  0x00000001U
+#define DMAC_SBIU_CSLP_EN_S  2
+/** DMAC_MXIF_CSLP_EN : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_MXIF_CSLP_EN    (BIT(3))
+#define DMAC_MXIF_CSLP_EN_M  (DMAC_MXIF_CSLP_EN_V << DMAC_MXIF_CSLP_EN_S)
+#define DMAC_MXIF_CSLP_EN_V  0x00000001U
+#define DMAC_MXIF_CSLP_EN_S  3
+
+/** DMAC_LOWPOWER_CFG1_REG register
+ *  NA
+ */
+#define DMAC_LOWPOWER_CFG1_REG (DR_REG_DMAC_BASE + 0x64)
+/** DMAC_GLCH_LPDLY : R/W; bitpos: [7:0]; default: 64;
+ *  NA
+ */
+#define DMAC_GLCH_LPDLY    0x000000FFU
+#define DMAC_GLCH_LPDLY_M  (DMAC_GLCH_LPDLY_V << DMAC_GLCH_LPDLY_S)
+#define DMAC_GLCH_LPDLY_V  0x000000FFU
+#define DMAC_GLCH_LPDLY_S  0
+/** DMAC_SBIU_LPDLY : R/W; bitpos: [15:8]; default: 64;
+ *  NA
+ */
+#define DMAC_SBIU_LPDLY    0x000000FFU
+#define DMAC_SBIU_LPDLY_M  (DMAC_SBIU_LPDLY_V << DMAC_SBIU_LPDLY_S)
+#define DMAC_SBIU_LPDLY_V  0x000000FFU
+#define DMAC_SBIU_LPDLY_S  8
+/** DMAC_MXIF_LPDLY : R/W; bitpos: [23:16]; default: 64;
+ *  NA
+ */
+#define DMAC_MXIF_LPDLY    0x000000FFU
+#define DMAC_MXIF_LPDLY_M  (DMAC_MXIF_LPDLY_V << DMAC_MXIF_LPDLY_S)
+#define DMAC_MXIF_LPDLY_V  0x000000FFU
+#define DMAC_MXIF_LPDLY_S  16
+
+/** DMAC_CH1_SAR0_REG register
+ *  NA
+ */
+#define DMAC_CH1_SAR0_REG (DR_REG_DMAC_BASE + 0x100)
+/** DMAC_CH1_SAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SAR0    0xFFFFFFFFU
+#define DMAC_CH1_SAR0_M  (DMAC_CH1_SAR0_V << DMAC_CH1_SAR0_S)
+#define DMAC_CH1_SAR0_V  0xFFFFFFFFU
+#define DMAC_CH1_SAR0_S  0
+
+/** DMAC_CH1_SAR1_REG register
+ *  NA
+ */
+#define DMAC_CH1_SAR1_REG (DR_REG_DMAC_BASE + 0x104)
+/** DMAC_CH1_SAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SAR1    0xFFFFFFFFU
+#define DMAC_CH1_SAR1_M  (DMAC_CH1_SAR1_V << DMAC_CH1_SAR1_S)
+#define DMAC_CH1_SAR1_V  0xFFFFFFFFU
+#define DMAC_CH1_SAR1_S  0
+
+/** DMAC_CH1_DAR0_REG register
+ *  NA
+ */
+#define DMAC_CH1_DAR0_REG (DR_REG_DMAC_BASE + 0x108)
+/** DMAC_CH1_DAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DAR0    0xFFFFFFFFU
+#define DMAC_CH1_DAR0_M  (DMAC_CH1_DAR0_V << DMAC_CH1_DAR0_S)
+#define DMAC_CH1_DAR0_V  0xFFFFFFFFU
+#define DMAC_CH1_DAR0_S  0
+
+/** DMAC_CH1_DAR1_REG register
+ *  NA
+ */
+#define DMAC_CH1_DAR1_REG (DR_REG_DMAC_BASE + 0x10c)
+/** DMAC_CH1_DAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DAR1    0xFFFFFFFFU
+#define DMAC_CH1_DAR1_M  (DMAC_CH1_DAR1_V << DMAC_CH1_DAR1_S)
+#define DMAC_CH1_DAR1_V  0xFFFFFFFFU
+#define DMAC_CH1_DAR1_S  0
+
+/** DMAC_CH1_BLOCK_TS0_REG register
+ *  NA
+ */
+#define DMAC_CH1_BLOCK_TS0_REG (DR_REG_DMAC_BASE + 0x110)
+/** DMAC_CH1_BLOCK_TS : R/W; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_BLOCK_TS    0x003FFFFFU
+#define DMAC_CH1_BLOCK_TS_M  (DMAC_CH1_BLOCK_TS_V << DMAC_CH1_BLOCK_TS_S)
+#define DMAC_CH1_BLOCK_TS_V  0x003FFFFFU
+#define DMAC_CH1_BLOCK_TS_S  0
+
+/** DMAC_CH1_CTL0_REG register
+ *  NA
+ */
+#define DMAC_CH1_CTL0_REG (DR_REG_DMAC_BASE + 0x118)
+/** DMAC_CH1_SMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SMS    (BIT(0))
+#define DMAC_CH1_SMS_M  (DMAC_CH1_SMS_V << DMAC_CH1_SMS_S)
+#define DMAC_CH1_SMS_V  0x00000001U
+#define DMAC_CH1_SMS_S  0
+/** DMAC_CH1_DMS : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DMS    (BIT(2))
+#define DMAC_CH1_DMS_M  (DMAC_CH1_DMS_V << DMAC_CH1_DMS_S)
+#define DMAC_CH1_DMS_V  0x00000001U
+#define DMAC_CH1_DMS_S  2
+/** DMAC_CH1_SINC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SINC    (BIT(4))
+#define DMAC_CH1_SINC_M  (DMAC_CH1_SINC_V << DMAC_CH1_SINC_S)
+#define DMAC_CH1_SINC_V  0x00000001U
+#define DMAC_CH1_SINC_S  4
+/** DMAC_CH1_DINC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DINC    (BIT(6))
+#define DMAC_CH1_DINC_M  (DMAC_CH1_DINC_V << DMAC_CH1_DINC_S)
+#define DMAC_CH1_DINC_V  0x00000001U
+#define DMAC_CH1_DINC_S  6
+/** DMAC_CH1_SRC_TR_WIDTH : R/W; bitpos: [10:8]; default: 2;
+ *  NA
+ */
+#define DMAC_CH1_SRC_TR_WIDTH    0x00000007U
+#define DMAC_CH1_SRC_TR_WIDTH_M  (DMAC_CH1_SRC_TR_WIDTH_V << DMAC_CH1_SRC_TR_WIDTH_S)
+#define DMAC_CH1_SRC_TR_WIDTH_V  0x00000007U
+#define DMAC_CH1_SRC_TR_WIDTH_S  8
+/** DMAC_CH1_DST_TR_WIDTH : R/W; bitpos: [13:11]; default: 2;
+ *  NA
+ */
+#define DMAC_CH1_DST_TR_WIDTH    0x00000007U
+#define DMAC_CH1_DST_TR_WIDTH_M  (DMAC_CH1_DST_TR_WIDTH_V << DMAC_CH1_DST_TR_WIDTH_S)
+#define DMAC_CH1_DST_TR_WIDTH_V  0x00000007U
+#define DMAC_CH1_DST_TR_WIDTH_S  11
+/** DMAC_CH1_SRC_MSIZE : R/W; bitpos: [17:14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_MSIZE    0x0000000FU
+#define DMAC_CH1_SRC_MSIZE_M  (DMAC_CH1_SRC_MSIZE_V << DMAC_CH1_SRC_MSIZE_S)
+#define DMAC_CH1_SRC_MSIZE_V  0x0000000FU
+#define DMAC_CH1_SRC_MSIZE_S  14
+/** DMAC_CH1_DST_MSIZE : R/W; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_MSIZE    0x0000000FU
+#define DMAC_CH1_DST_MSIZE_M  (DMAC_CH1_DST_MSIZE_V << DMAC_CH1_DST_MSIZE_S)
+#define DMAC_CH1_DST_MSIZE_V  0x0000000FU
+#define DMAC_CH1_DST_MSIZE_S  18
+/** DMAC_CH1_AR_CACHE : R/W; bitpos: [25:22]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AR_CACHE    0x0000000FU
+#define DMAC_CH1_AR_CACHE_M  (DMAC_CH1_AR_CACHE_V << DMAC_CH1_AR_CACHE_S)
+#define DMAC_CH1_AR_CACHE_V  0x0000000FU
+#define DMAC_CH1_AR_CACHE_S  22
+/** DMAC_CH1_AW_CACHE : R/W; bitpos: [29:26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AW_CACHE    0x0000000FU
+#define DMAC_CH1_AW_CACHE_M  (DMAC_CH1_AW_CACHE_V << DMAC_CH1_AW_CACHE_S)
+#define DMAC_CH1_AW_CACHE_V  0x0000000FU
+#define DMAC_CH1_AW_CACHE_S  26
+/** DMAC_CH1_NONPOSTED_LASTWRITE_EN : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_NONPOSTED_LASTWRITE_EN    (BIT(30))
+#define DMAC_CH1_NONPOSTED_LASTWRITE_EN_M  (DMAC_CH1_NONPOSTED_LASTWRITE_EN_V << DMAC_CH1_NONPOSTED_LASTWRITE_EN_S)
+#define DMAC_CH1_NONPOSTED_LASTWRITE_EN_V  0x00000001U
+#define DMAC_CH1_NONPOSTED_LASTWRITE_EN_S  30
+
+/** DMAC_CH1_CTL1_REG register
+ *  NA
+ */
+#define DMAC_CH1_CTL1_REG (DR_REG_DMAC_BASE + 0x11c)
+/** DMAC_CH1_AR_PROT : R/W; bitpos: [2:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AR_PROT    0x00000007U
+#define DMAC_CH1_AR_PROT_M  (DMAC_CH1_AR_PROT_V << DMAC_CH1_AR_PROT_S)
+#define DMAC_CH1_AR_PROT_V  0x00000007U
+#define DMAC_CH1_AR_PROT_S  0
+/** DMAC_CH1_AW_PROT : R/W; bitpos: [5:3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AW_PROT    0x00000007U
+#define DMAC_CH1_AW_PROT_M  (DMAC_CH1_AW_PROT_V << DMAC_CH1_AW_PROT_S)
+#define DMAC_CH1_AW_PROT_V  0x00000007U
+#define DMAC_CH1_AW_PROT_S  3
+/** DMAC_CH1_ARLEN_EN : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ARLEN_EN    (BIT(6))
+#define DMAC_CH1_ARLEN_EN_M  (DMAC_CH1_ARLEN_EN_V << DMAC_CH1_ARLEN_EN_S)
+#define DMAC_CH1_ARLEN_EN_V  0x00000001U
+#define DMAC_CH1_ARLEN_EN_S  6
+/** DMAC_CH1_ARLEN : R/W; bitpos: [14:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ARLEN    0x000000FFU
+#define DMAC_CH1_ARLEN_M  (DMAC_CH1_ARLEN_V << DMAC_CH1_ARLEN_S)
+#define DMAC_CH1_ARLEN_V  0x000000FFU
+#define DMAC_CH1_ARLEN_S  7
+/** DMAC_CH1_AWLEN_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AWLEN_EN    (BIT(15))
+#define DMAC_CH1_AWLEN_EN_M  (DMAC_CH1_AWLEN_EN_V << DMAC_CH1_AWLEN_EN_S)
+#define DMAC_CH1_AWLEN_EN_V  0x00000001U
+#define DMAC_CH1_AWLEN_EN_S  15
+/** DMAC_CH1_AWLEN : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AWLEN    0x000000FFU
+#define DMAC_CH1_AWLEN_M  (DMAC_CH1_AWLEN_V << DMAC_CH1_AWLEN_S)
+#define DMAC_CH1_AWLEN_V  0x000000FFU
+#define DMAC_CH1_AWLEN_S  16
+/** DMAC_CH1_SRC_STAT_EN : R/W; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_STAT_EN    (BIT(24))
+#define DMAC_CH1_SRC_STAT_EN_M  (DMAC_CH1_SRC_STAT_EN_V << DMAC_CH1_SRC_STAT_EN_S)
+#define DMAC_CH1_SRC_STAT_EN_V  0x00000001U
+#define DMAC_CH1_SRC_STAT_EN_S  24
+/** DMAC_CH1_DST_STAT_EN : R/W; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_STAT_EN    (BIT(25))
+#define DMAC_CH1_DST_STAT_EN_M  (DMAC_CH1_DST_STAT_EN_V << DMAC_CH1_DST_STAT_EN_S)
+#define DMAC_CH1_DST_STAT_EN_V  0x00000001U
+#define DMAC_CH1_DST_STAT_EN_S  25
+/** DMAC_CH1_IOC_BLKTFR : R/W; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_IOC_BLKTFR    (BIT(26))
+#define DMAC_CH1_IOC_BLKTFR_M  (DMAC_CH1_IOC_BLKTFR_V << DMAC_CH1_IOC_BLKTFR_S)
+#define DMAC_CH1_IOC_BLKTFR_V  0x00000001U
+#define DMAC_CH1_IOC_BLKTFR_S  26
+/** DMAC_CH1_SHADOWREG_OR_LLI_LAST : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SHADOWREG_OR_LLI_LAST    (BIT(30))
+#define DMAC_CH1_SHADOWREG_OR_LLI_LAST_M  (DMAC_CH1_SHADOWREG_OR_LLI_LAST_V << DMAC_CH1_SHADOWREG_OR_LLI_LAST_S)
+#define DMAC_CH1_SHADOWREG_OR_LLI_LAST_V  0x00000001U
+#define DMAC_CH1_SHADOWREG_OR_LLI_LAST_S  30
+/** DMAC_CH1_SHADOWREG_OR_LLI_VALID : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SHADOWREG_OR_LLI_VALID    (BIT(31))
+#define DMAC_CH1_SHADOWREG_OR_LLI_VALID_M  (DMAC_CH1_SHADOWREG_OR_LLI_VALID_V << DMAC_CH1_SHADOWREG_OR_LLI_VALID_S)
+#define DMAC_CH1_SHADOWREG_OR_LLI_VALID_V  0x00000001U
+#define DMAC_CH1_SHADOWREG_OR_LLI_VALID_S  31
+
+/** DMAC_CH1_CFG0_REG register
+ *  NA
+ */
+#define DMAC_CH1_CFG0_REG (DR_REG_DMAC_BASE + 0x120)
+/** DMAC_CH1_SRC_MULTBLK_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH1_SRC_MULTBLK_TYPE_M  (DMAC_CH1_SRC_MULTBLK_TYPE_V << DMAC_CH1_SRC_MULTBLK_TYPE_S)
+#define DMAC_CH1_SRC_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH1_SRC_MULTBLK_TYPE_S  0
+/** DMAC_CH1_DST_MULTBLK_TYPE : R/W; bitpos: [3:2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH1_DST_MULTBLK_TYPE_M  (DMAC_CH1_DST_MULTBLK_TYPE_V << DMAC_CH1_DST_MULTBLK_TYPE_S)
+#define DMAC_CH1_DST_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH1_DST_MULTBLK_TYPE_S  2
+/** DMAC_CH1_RD_UID : RO; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_RD_UID    0x0000000FU
+#define DMAC_CH1_RD_UID_M  (DMAC_CH1_RD_UID_V << DMAC_CH1_RD_UID_S)
+#define DMAC_CH1_RD_UID_V  0x0000000FU
+#define DMAC_CH1_RD_UID_S  18
+/** DMAC_CH1_WR_UID : RO; bitpos: [28:25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_WR_UID    0x0000000FU
+#define DMAC_CH1_WR_UID_M  (DMAC_CH1_WR_UID_V << DMAC_CH1_WR_UID_S)
+#define DMAC_CH1_WR_UID_V  0x0000000FU
+#define DMAC_CH1_WR_UID_S  25
+
+/** DMAC_CH1_CFG1_REG register
+ *  NA
+ */
+#define DMAC_CH1_CFG1_REG (DR_REG_DMAC_BASE + 0x124)
+/** DMAC_CH1_TT_FC : R/W; bitpos: [2:0]; default: 3;
+ *  NA
+ */
+#define DMAC_CH1_TT_FC    0x00000007U
+#define DMAC_CH1_TT_FC_M  (DMAC_CH1_TT_FC_V << DMAC_CH1_TT_FC_S)
+#define DMAC_CH1_TT_FC_V  0x00000007U
+#define DMAC_CH1_TT_FC_S  0
+/** DMAC_CH1_HS_SEL_SRC : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_HS_SEL_SRC    (BIT(3))
+#define DMAC_CH1_HS_SEL_SRC_M  (DMAC_CH1_HS_SEL_SRC_V << DMAC_CH1_HS_SEL_SRC_S)
+#define DMAC_CH1_HS_SEL_SRC_V  0x00000001U
+#define DMAC_CH1_HS_SEL_SRC_S  3
+/** DMAC_CH1_HS_SEL_DST : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_HS_SEL_DST    (BIT(4))
+#define DMAC_CH1_HS_SEL_DST_M  (DMAC_CH1_HS_SEL_DST_V << DMAC_CH1_HS_SEL_DST_S)
+#define DMAC_CH1_HS_SEL_DST_V  0x00000001U
+#define DMAC_CH1_HS_SEL_DST_S  4
+/** DMAC_CH1_SRC_HWHS_POL : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_HWHS_POL    (BIT(5))
+#define DMAC_CH1_SRC_HWHS_POL_M  (DMAC_CH1_SRC_HWHS_POL_V << DMAC_CH1_SRC_HWHS_POL_S)
+#define DMAC_CH1_SRC_HWHS_POL_V  0x00000001U
+#define DMAC_CH1_SRC_HWHS_POL_S  5
+/** DMAC_CH1_DST_HWHS_POL : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_HWHS_POL    (BIT(6))
+#define DMAC_CH1_DST_HWHS_POL_M  (DMAC_CH1_DST_HWHS_POL_V << DMAC_CH1_DST_HWHS_POL_S)
+#define DMAC_CH1_DST_HWHS_POL_V  0x00000001U
+#define DMAC_CH1_DST_HWHS_POL_S  6
+/** DMAC_CH1_SRC_PER : R/W; bitpos: [8:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_PER    0x00000003U
+#define DMAC_CH1_SRC_PER_M  (DMAC_CH1_SRC_PER_V << DMAC_CH1_SRC_PER_S)
+#define DMAC_CH1_SRC_PER_V  0x00000003U
+#define DMAC_CH1_SRC_PER_S  7
+/** DMAC_CH1_DST_PER : R/W; bitpos: [13:12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_PER    0x00000003U
+#define DMAC_CH1_DST_PER_M  (DMAC_CH1_DST_PER_V << DMAC_CH1_DST_PER_S)
+#define DMAC_CH1_DST_PER_V  0x00000003U
+#define DMAC_CH1_DST_PER_S  12
+/** DMAC_CH1_CH_PRIOR : R/W; bitpos: [19:17]; default: 3;
+ *  NA
+ */
+#define DMAC_CH1_CH_PRIOR    0x00000007U
+#define DMAC_CH1_CH_PRIOR_M  (DMAC_CH1_CH_PRIOR_V << DMAC_CH1_CH_PRIOR_S)
+#define DMAC_CH1_CH_PRIOR_V  0x00000007U
+#define DMAC_CH1_CH_PRIOR_S  17
+/** DMAC_CH1_LOCK_CH : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LOCK_CH    (BIT(20))
+#define DMAC_CH1_LOCK_CH_M  (DMAC_CH1_LOCK_CH_V << DMAC_CH1_LOCK_CH_S)
+#define DMAC_CH1_LOCK_CH_V  0x00000001U
+#define DMAC_CH1_LOCK_CH_S  20
+/** DMAC_CH1_LOCK_CH_L : RO; bitpos: [22:21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LOCK_CH_L    0x00000003U
+#define DMAC_CH1_LOCK_CH_L_M  (DMAC_CH1_LOCK_CH_L_V << DMAC_CH1_LOCK_CH_L_S)
+#define DMAC_CH1_LOCK_CH_L_V  0x00000003U
+#define DMAC_CH1_LOCK_CH_L_S  21
+/** DMAC_CH1_SRC_OSR_LMT : R/W; bitpos: [26:23]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_OSR_LMT    0x0000000FU
+#define DMAC_CH1_SRC_OSR_LMT_M  (DMAC_CH1_SRC_OSR_LMT_V << DMAC_CH1_SRC_OSR_LMT_S)
+#define DMAC_CH1_SRC_OSR_LMT_V  0x0000000FU
+#define DMAC_CH1_SRC_OSR_LMT_S  23
+/** DMAC_CH1_DST_OSR_LMT : R/W; bitpos: [30:27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_OSR_LMT    0x0000000FU
+#define DMAC_CH1_DST_OSR_LMT_M  (DMAC_CH1_DST_OSR_LMT_V << DMAC_CH1_DST_OSR_LMT_S)
+#define DMAC_CH1_DST_OSR_LMT_V  0x0000000FU
+#define DMAC_CH1_DST_OSR_LMT_S  27
+
+/** DMAC_CH1_LLP0_REG register
+ *  NA
+ */
+#define DMAC_CH1_LLP0_REG (DR_REG_DMAC_BASE + 0x128)
+/** DMAC_CH1_LMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LMS    (BIT(0))
+#define DMAC_CH1_LMS_M  (DMAC_CH1_LMS_V << DMAC_CH1_LMS_S)
+#define DMAC_CH1_LMS_V  0x00000001U
+#define DMAC_CH1_LMS_S  0
+/** DMAC_CH1_LOC0 : R/W; bitpos: [31:6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LOC0    0x03FFFFFFU
+#define DMAC_CH1_LOC0_M  (DMAC_CH1_LOC0_V << DMAC_CH1_LOC0_S)
+#define DMAC_CH1_LOC0_V  0x03FFFFFFU
+#define DMAC_CH1_LOC0_S  6
+
+/** DMAC_CH1_LLP1_REG register
+ *  NA
+ */
+#define DMAC_CH1_LLP1_REG (DR_REG_DMAC_BASE + 0x12c)
+/** DMAC_CH1_LOC1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LOC1    0xFFFFFFFFU
+#define DMAC_CH1_LOC1_M  (DMAC_CH1_LOC1_V << DMAC_CH1_LOC1_S)
+#define DMAC_CH1_LOC1_V  0xFFFFFFFFU
+#define DMAC_CH1_LOC1_S  0
+
+/** DMAC_CH1_STATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH1_STATUS0_REG (DR_REG_DMAC_BASE + 0x130)
+/** DMAC_CH1_CMPLTD_BLK_TFR_SIZE : RO; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CMPLTD_BLK_TFR_SIZE    0x003FFFFFU
+#define DMAC_CH1_CMPLTD_BLK_TFR_SIZE_M  (DMAC_CH1_CMPLTD_BLK_TFR_SIZE_V << DMAC_CH1_CMPLTD_BLK_TFR_SIZE_S)
+#define DMAC_CH1_CMPLTD_BLK_TFR_SIZE_V  0x003FFFFFU
+#define DMAC_CH1_CMPLTD_BLK_TFR_SIZE_S  0
+
+/** DMAC_CH1_STATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH1_STATUS1_REG (DR_REG_DMAC_BASE + 0x134)
+/** DMAC_CH1_DATA_LEFT_IN_FIFO : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DATA_LEFT_IN_FIFO    0x00007FFFU
+#define DMAC_CH1_DATA_LEFT_IN_FIFO_M  (DMAC_CH1_DATA_LEFT_IN_FIFO_V << DMAC_CH1_DATA_LEFT_IN_FIFO_S)
+#define DMAC_CH1_DATA_LEFT_IN_FIFO_V  0x00007FFFU
+#define DMAC_CH1_DATA_LEFT_IN_FIFO_S  0
+
+/** DMAC_CH1_SWHSSRC0_REG register
+ *  NA
+ */
+#define DMAC_CH1_SWHSSRC0_REG (DR_REG_DMAC_BASE + 0x138)
+/** DMAC_CH1_SWHS_REQ_SRC : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_REQ_SRC    (BIT(0))
+#define DMAC_CH1_SWHS_REQ_SRC_M  (DMAC_CH1_SWHS_REQ_SRC_V << DMAC_CH1_SWHS_REQ_SRC_S)
+#define DMAC_CH1_SWHS_REQ_SRC_V  0x00000001U
+#define DMAC_CH1_SWHS_REQ_SRC_S  0
+/** DMAC_CH1_SWHS_REQ_SRC_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_REQ_SRC_WE    (BIT(1))
+#define DMAC_CH1_SWHS_REQ_SRC_WE_M  (DMAC_CH1_SWHS_REQ_SRC_WE_V << DMAC_CH1_SWHS_REQ_SRC_WE_S)
+#define DMAC_CH1_SWHS_REQ_SRC_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_REQ_SRC_WE_S  1
+/** DMAC_CH1_SWHS_SGLREQ_SRC : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_SGLREQ_SRC    (BIT(2))
+#define DMAC_CH1_SWHS_SGLREQ_SRC_M  (DMAC_CH1_SWHS_SGLREQ_SRC_V << DMAC_CH1_SWHS_SGLREQ_SRC_S)
+#define DMAC_CH1_SWHS_SGLREQ_SRC_V  0x00000001U
+#define DMAC_CH1_SWHS_SGLREQ_SRC_S  2
+/** DMAC_CH1_SWHS_SGLREQ_SRC_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_SGLREQ_SRC_WE    (BIT(3))
+#define DMAC_CH1_SWHS_SGLREQ_SRC_WE_M  (DMAC_CH1_SWHS_SGLREQ_SRC_WE_V << DMAC_CH1_SWHS_SGLREQ_SRC_WE_S)
+#define DMAC_CH1_SWHS_SGLREQ_SRC_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_SGLREQ_SRC_WE_S  3
+/** DMAC_CH1_SWHS_LST_SRC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_LST_SRC    (BIT(4))
+#define DMAC_CH1_SWHS_LST_SRC_M  (DMAC_CH1_SWHS_LST_SRC_V << DMAC_CH1_SWHS_LST_SRC_S)
+#define DMAC_CH1_SWHS_LST_SRC_V  0x00000001U
+#define DMAC_CH1_SWHS_LST_SRC_S  4
+/** DMAC_CH1_SWHS_LST_SRC_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_LST_SRC_WE    (BIT(5))
+#define DMAC_CH1_SWHS_LST_SRC_WE_M  (DMAC_CH1_SWHS_LST_SRC_WE_V << DMAC_CH1_SWHS_LST_SRC_WE_S)
+#define DMAC_CH1_SWHS_LST_SRC_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_LST_SRC_WE_S  5
+
+/** DMAC_CH1_SWHSDST0_REG register
+ *  NA
+ */
+#define DMAC_CH1_SWHSDST0_REG (DR_REG_DMAC_BASE + 0x140)
+/** DMAC_CH1_SWHS_REQ_DST : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_REQ_DST    (BIT(0))
+#define DMAC_CH1_SWHS_REQ_DST_M  (DMAC_CH1_SWHS_REQ_DST_V << DMAC_CH1_SWHS_REQ_DST_S)
+#define DMAC_CH1_SWHS_REQ_DST_V  0x00000001U
+#define DMAC_CH1_SWHS_REQ_DST_S  0
+/** DMAC_CH1_SWHS_REQ_DST_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_REQ_DST_WE    (BIT(1))
+#define DMAC_CH1_SWHS_REQ_DST_WE_M  (DMAC_CH1_SWHS_REQ_DST_WE_V << DMAC_CH1_SWHS_REQ_DST_WE_S)
+#define DMAC_CH1_SWHS_REQ_DST_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_REQ_DST_WE_S  1
+/** DMAC_CH1_SWHS_SGLREQ_DST : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_SGLREQ_DST    (BIT(2))
+#define DMAC_CH1_SWHS_SGLREQ_DST_M  (DMAC_CH1_SWHS_SGLREQ_DST_V << DMAC_CH1_SWHS_SGLREQ_DST_S)
+#define DMAC_CH1_SWHS_SGLREQ_DST_V  0x00000001U
+#define DMAC_CH1_SWHS_SGLREQ_DST_S  2
+/** DMAC_CH1_SWHS_SGLREQ_DST_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_SGLREQ_DST_WE    (BIT(3))
+#define DMAC_CH1_SWHS_SGLREQ_DST_WE_M  (DMAC_CH1_SWHS_SGLREQ_DST_WE_V << DMAC_CH1_SWHS_SGLREQ_DST_WE_S)
+#define DMAC_CH1_SWHS_SGLREQ_DST_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_SGLREQ_DST_WE_S  3
+/** DMAC_CH1_SWHS_LST_DST : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_LST_DST    (BIT(4))
+#define DMAC_CH1_SWHS_LST_DST_M  (DMAC_CH1_SWHS_LST_DST_V << DMAC_CH1_SWHS_LST_DST_S)
+#define DMAC_CH1_SWHS_LST_DST_V  0x00000001U
+#define DMAC_CH1_SWHS_LST_DST_S  4
+/** DMAC_CH1_SWHS_LST_DST_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_LST_DST_WE    (BIT(5))
+#define DMAC_CH1_SWHS_LST_DST_WE_M  (DMAC_CH1_SWHS_LST_DST_WE_V << DMAC_CH1_SWHS_LST_DST_WE_S)
+#define DMAC_CH1_SWHS_LST_DST_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_LST_DST_WE_S  5
+
+/** DMAC_CH1_BLK_TFR_RESUMEREQ0_REG register
+ *  NA
+ */
+#define DMAC_CH1_BLK_TFR_RESUMEREQ0_REG (DR_REG_DMAC_BASE + 0x148)
+/** DMAC_CH1_BLK_TFR_RESUMEREQ : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_BLK_TFR_RESUMEREQ    (BIT(0))
+#define DMAC_CH1_BLK_TFR_RESUMEREQ_M  (DMAC_CH1_BLK_TFR_RESUMEREQ_V << DMAC_CH1_BLK_TFR_RESUMEREQ_S)
+#define DMAC_CH1_BLK_TFR_RESUMEREQ_V  0x00000001U
+#define DMAC_CH1_BLK_TFR_RESUMEREQ_S  0
+
+/** DMAC_CH1_AXI_ID0_REG register
+ *  NA
+ */
+#define DMAC_CH1_AXI_ID0_REG (DR_REG_DMAC_BASE + 0x150)
+/** DMAC_CH1_AXI_READ_ID_SUFFIX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AXI_READ_ID_SUFFIX    (BIT(0))
+#define DMAC_CH1_AXI_READ_ID_SUFFIX_M  (DMAC_CH1_AXI_READ_ID_SUFFIX_V << DMAC_CH1_AXI_READ_ID_SUFFIX_S)
+#define DMAC_CH1_AXI_READ_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH1_AXI_READ_ID_SUFFIX_S  0
+/** DMAC_CH1_AXI_WRITE_ID_SUFFIX : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AXI_WRITE_ID_SUFFIX    (BIT(16))
+#define DMAC_CH1_AXI_WRITE_ID_SUFFIX_M  (DMAC_CH1_AXI_WRITE_ID_SUFFIX_V << DMAC_CH1_AXI_WRITE_ID_SUFFIX_S)
+#define DMAC_CH1_AXI_WRITE_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH1_AXI_WRITE_ID_SUFFIX_S  16
+
+/** DMAC_CH1_AXI_QOS0_REG register
+ *  NA
+ */
+#define DMAC_CH1_AXI_QOS0_REG (DR_REG_DMAC_BASE + 0x158)
+/** DMAC_CH1_AXI_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AXI_AWQOS    0x0000000FU
+#define DMAC_CH1_AXI_AWQOS_M  (DMAC_CH1_AXI_AWQOS_V << DMAC_CH1_AXI_AWQOS_S)
+#define DMAC_CH1_AXI_AWQOS_V  0x0000000FU
+#define DMAC_CH1_AXI_AWQOS_S  0
+/** DMAC_CH1_AXI_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AXI_ARQOS    0x0000000FU
+#define DMAC_CH1_AXI_ARQOS_M  (DMAC_CH1_AXI_ARQOS_V << DMAC_CH1_AXI_ARQOS_S)
+#define DMAC_CH1_AXI_ARQOS_V  0x0000000FU
+#define DMAC_CH1_AXI_ARQOS_S  4
+
+/** DMAC_CH1_SSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH1_SSTAT0_REG (DR_REG_DMAC_BASE + 0x160)
+/** DMAC_CH1_SSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SSTAT    0xFFFFFFFFU
+#define DMAC_CH1_SSTAT_M  (DMAC_CH1_SSTAT_V << DMAC_CH1_SSTAT_S)
+#define DMAC_CH1_SSTAT_V  0xFFFFFFFFU
+#define DMAC_CH1_SSTAT_S  0
+
+/** DMAC_CH1_DSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH1_DSTAT0_REG (DR_REG_DMAC_BASE + 0x168)
+/** DMAC_CH1_DSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DSTAT    0xFFFFFFFFU
+#define DMAC_CH1_DSTAT_M  (DMAC_CH1_DSTAT_V << DMAC_CH1_DSTAT_S)
+#define DMAC_CH1_DSTAT_V  0xFFFFFFFFU
+#define DMAC_CH1_DSTAT_S  0
+
+/** DMAC_CH1_SSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH1_SSTATAR0_REG (DR_REG_DMAC_BASE + 0x170)
+/** DMAC_CH1_SSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SSTATAR0    0xFFFFFFFFU
+#define DMAC_CH1_SSTATAR0_M  (DMAC_CH1_SSTATAR0_V << DMAC_CH1_SSTATAR0_S)
+#define DMAC_CH1_SSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH1_SSTATAR0_S  0
+
+/** DMAC_CH1_SSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH1_SSTATAR1_REG (DR_REG_DMAC_BASE + 0x174)
+/** DMAC_CH1_SSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SSTATAR1    0xFFFFFFFFU
+#define DMAC_CH1_SSTATAR1_M  (DMAC_CH1_SSTATAR1_V << DMAC_CH1_SSTATAR1_S)
+#define DMAC_CH1_SSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH1_SSTATAR1_S  0
+
+/** DMAC_CH1_DSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH1_DSTATAR0_REG (DR_REG_DMAC_BASE + 0x178)
+/** DMAC_CH1_DSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DSTATAR0    0xFFFFFFFFU
+#define DMAC_CH1_DSTATAR0_M  (DMAC_CH1_DSTATAR0_V << DMAC_CH1_DSTATAR0_S)
+#define DMAC_CH1_DSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH1_DSTATAR0_S  0
+
+/** DMAC_CH1_DSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH1_DSTATAR1_REG (DR_REG_DMAC_BASE + 0x17c)
+/** DMAC_CH1_DSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DSTATAR1    0xFFFFFFFFU
+#define DMAC_CH1_DSTATAR1_M  (DMAC_CH1_DSTATAR1_V << DMAC_CH1_DSTATAR1_S)
+#define DMAC_CH1_DSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH1_DSTATAR1_S  0
+
+/** DMAC_CH1_INTSTATUS_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSTATUS_ENABLE0_REG (DR_REG_DMAC_BASE + 0x180)
+/** DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_V << DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_V << DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT_V << DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT_V << DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : R/W; bitpos: [13]; default:
+ *  1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT_M  (DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT_V << DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT_M  (DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT_V << DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT_M  (DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT_V << DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH1_INTSTATUS_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSTATUS_ENABLE1_REG (DR_REG_DMAC_BASE + 0x184)
+/** DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH1_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x188)
+/** DMAC_CH1_BLOCK_TFR_DONE_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH1_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH1_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH1_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH1_DMA_TFR_DONE_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH1_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH1_DMA_TFR_DONE_INTSTAT_V << DMAC_CH1_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH1_SRC_TRANSCOMP_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH1_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH1_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH1_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH1_DST_TRANSCOMP_INTSTAT : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH1_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH1_DST_TRANSCOMP_INTSTAT_V << DMAC_CH1_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH1_SRC_DEC_ERR_INTSTAT : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH1_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH1_SRC_DEC_ERR_INTSTAT_V << DMAC_CH1_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH1_DST_DEC_ERR_INTSTAT : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH1_DST_DEC_ERR_INTSTAT_M  (DMAC_CH1_DST_DEC_ERR_INTSTAT_V << DMAC_CH1_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH1_SRC_SLV_ERR_INTSTAT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH1_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH1_SRC_SLV_ERR_INTSTAT_V << DMAC_CH1_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH1_DST_SLV_ERR_INTSTAT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH1_DST_SLV_ERR_INTSTAT_M  (DMAC_CH1_DST_SLV_ERR_INTSTAT_V << DMAC_CH1_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH1_SLVIF_DEC_ERR_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH1_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH1_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH1_CH_LOCK_CLEARED_INTSTAT : RO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH1_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH1_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH1_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH1_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT : RO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH1_CH_SUSPENDED_INTSTAT : RO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH1_CH_SUSPENDED_INTSTAT_M  (DMAC_CH1_CH_SUSPENDED_INTSTAT_V << DMAC_CH1_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH1_CH_DISABLED_INTSTAT : RO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH1_CH_DISABLED_INTSTAT_M  (DMAC_CH1_CH_DISABLED_INTSTAT_V << DMAC_CH1_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH1_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH1_CH_ABORTED_INTSTAT : RO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH1_CH_ABORTED_INTSTAT_M  (DMAC_CH1_CH_ABORTED_INTSTAT_V << DMAC_CH1_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH1_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH1_INTSTATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSTATUS1_REG (DR_REG_DMAC_BASE + 0x18c)
+/** DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH1_INTSIGNAL_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSIGNAL_ENABLE0_REG (DR_REG_DMAC_BASE + 0x190)
+/** DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL    (BIT(0))
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_M  (DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V << DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S  0
+/** DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL    (BIT(1))
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_M  (DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_V << DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_S  1
+/** DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL    (BIT(3))
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_M  (DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V << DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S  3
+/** DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL    (BIT(4))
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_M  (DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_V << DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_S  4
+/** DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL    (BIT(5))
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_S  5
+/** DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL    (BIT(6))
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_S  6
+/** DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL    (BIT(7))
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_S  7
+/** DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL    (BIT(8))
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_S  8
+/** DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL    (BIT(9))
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S  9
+/** DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL    (BIT(10))
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S  10
+/** DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL    (BIT(11))
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S  11
+/** DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL    (BIT(12))
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S  12
+/** DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL : R/W; bitpos: [13];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL    (BIT(13))
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S  13
+/** DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL    (BIT(14))
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S  14
+/** DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL    (BIT(16))
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S  16
+/** DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL    (BIT(17))
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S  17
+/** DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL    (BIT(18))
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S  18
+/** DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL    (BIT(19))
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S  19
+/** DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL    (BIT(20))
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S  20
+/** DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL    (BIT(21))
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S  21
+/** DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL    (BIT(25))
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S  25
+/** DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL    (BIT(27))
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_M  (DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V << DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S  27
+/** DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL    (BIT(28))
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_M  (DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V << DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S  28
+/** DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL    (BIT(29))
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_M  (DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_V << DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_S  29
+/** DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL    (BIT(30))
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL_M  (DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL_V << DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL_S  30
+/** DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL    (BIT(31))
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL_M  (DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL_V << DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL_S  31
+
+/** DMAC_CH1_INTSIGNAL_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSIGNAL_ENABLE1_REG (DR_REG_DMAC_BASE + 0x194)
+/** DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL    (BIT(0))
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V << DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S  0
+/** DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL    (BIT(1))
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S  1
+/** DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL    (BIT(2))
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V << DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S  2
+/** DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL    (BIT(3))
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S  3
+
+/** DMAC_CH1_INTCLEAR0_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTCLEAR0_REG (DR_REG_DMAC_BASE + 0x198)
+/** DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_V << DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT : WO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_V << DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT : WO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT_V << DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT : WO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT_V << DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : WO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : WO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT : WO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT : WO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT : WO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT : WO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : WO; bitpos: [20]; default:
+ *  0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT : WO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT : WO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT : WO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT : WO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT : WO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT_M  (DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT_V << DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT : WO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT_M  (DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT_V << DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT : WO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT_M  (DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT_V << DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH1_INTCLEAR1_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTCLEAR1_REG (DR_REG_DMAC_BASE + 0x19c)
+/** DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT : WO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH2_SAR0_REG register
+ *  NA
+ */
+#define DMAC_CH2_SAR0_REG (DR_REG_DMAC_BASE + 0x200)
+/** DMAC_CH2_SAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SAR0    0xFFFFFFFFU
+#define DMAC_CH2_SAR0_M  (DMAC_CH2_SAR0_V << DMAC_CH2_SAR0_S)
+#define DMAC_CH2_SAR0_V  0xFFFFFFFFU
+#define DMAC_CH2_SAR0_S  0
+
+/** DMAC_CH2_SAR1_REG register
+ *  NA
+ */
+#define DMAC_CH2_SAR1_REG (DR_REG_DMAC_BASE + 0x204)
+/** DMAC_CH2_SAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SAR1    0xFFFFFFFFU
+#define DMAC_CH2_SAR1_M  (DMAC_CH2_SAR1_V << DMAC_CH2_SAR1_S)
+#define DMAC_CH2_SAR1_V  0xFFFFFFFFU
+#define DMAC_CH2_SAR1_S  0
+
+/** DMAC_CH2_DAR0_REG register
+ *  NA
+ */
+#define DMAC_CH2_DAR0_REG (DR_REG_DMAC_BASE + 0x208)
+/** DMAC_CH2_DAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DAR0    0xFFFFFFFFU
+#define DMAC_CH2_DAR0_M  (DMAC_CH2_DAR0_V << DMAC_CH2_DAR0_S)
+#define DMAC_CH2_DAR0_V  0xFFFFFFFFU
+#define DMAC_CH2_DAR0_S  0
+
+/** DMAC_CH2_DAR1_REG register
+ *  NA
+ */
+#define DMAC_CH2_DAR1_REG (DR_REG_DMAC_BASE + 0x20c)
+/** DMAC_CH2_DAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DAR1    0xFFFFFFFFU
+#define DMAC_CH2_DAR1_M  (DMAC_CH2_DAR1_V << DMAC_CH2_DAR1_S)
+#define DMAC_CH2_DAR1_V  0xFFFFFFFFU
+#define DMAC_CH2_DAR1_S  0
+
+/** DMAC_CH2_BLOCK_TS0_REG register
+ *  NA
+ */
+#define DMAC_CH2_BLOCK_TS0_REG (DR_REG_DMAC_BASE + 0x210)
+/** DMAC_CH2_BLOCK_TS : R/W; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_BLOCK_TS    0x003FFFFFU
+#define DMAC_CH2_BLOCK_TS_M  (DMAC_CH2_BLOCK_TS_V << DMAC_CH2_BLOCK_TS_S)
+#define DMAC_CH2_BLOCK_TS_V  0x003FFFFFU
+#define DMAC_CH2_BLOCK_TS_S  0
+
+/** DMAC_CH2_CTL0_REG register
+ *  NA
+ */
+#define DMAC_CH2_CTL0_REG (DR_REG_DMAC_BASE + 0x218)
+/** DMAC_CH2_SMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SMS    (BIT(0))
+#define DMAC_CH2_SMS_M  (DMAC_CH2_SMS_V << DMAC_CH2_SMS_S)
+#define DMAC_CH2_SMS_V  0x00000001U
+#define DMAC_CH2_SMS_S  0
+/** DMAC_CH2_DMS : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DMS    (BIT(2))
+#define DMAC_CH2_DMS_M  (DMAC_CH2_DMS_V << DMAC_CH2_DMS_S)
+#define DMAC_CH2_DMS_V  0x00000001U
+#define DMAC_CH2_DMS_S  2
+/** DMAC_CH2_SINC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SINC    (BIT(4))
+#define DMAC_CH2_SINC_M  (DMAC_CH2_SINC_V << DMAC_CH2_SINC_S)
+#define DMAC_CH2_SINC_V  0x00000001U
+#define DMAC_CH2_SINC_S  4
+/** DMAC_CH2_DINC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DINC    (BIT(6))
+#define DMAC_CH2_DINC_M  (DMAC_CH2_DINC_V << DMAC_CH2_DINC_S)
+#define DMAC_CH2_DINC_V  0x00000001U
+#define DMAC_CH2_DINC_S  6
+/** DMAC_CH2_SRC_TR_WIDTH : R/W; bitpos: [10:8]; default: 2;
+ *  NA
+ */
+#define DMAC_CH2_SRC_TR_WIDTH    0x00000007U
+#define DMAC_CH2_SRC_TR_WIDTH_M  (DMAC_CH2_SRC_TR_WIDTH_V << DMAC_CH2_SRC_TR_WIDTH_S)
+#define DMAC_CH2_SRC_TR_WIDTH_V  0x00000007U
+#define DMAC_CH2_SRC_TR_WIDTH_S  8
+/** DMAC_CH2_DST_TR_WIDTH : R/W; bitpos: [13:11]; default: 2;
+ *  NA
+ */
+#define DMAC_CH2_DST_TR_WIDTH    0x00000007U
+#define DMAC_CH2_DST_TR_WIDTH_M  (DMAC_CH2_DST_TR_WIDTH_V << DMAC_CH2_DST_TR_WIDTH_S)
+#define DMAC_CH2_DST_TR_WIDTH_V  0x00000007U
+#define DMAC_CH2_DST_TR_WIDTH_S  11
+/** DMAC_CH2_SRC_MSIZE : R/W; bitpos: [17:14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_MSIZE    0x0000000FU
+#define DMAC_CH2_SRC_MSIZE_M  (DMAC_CH2_SRC_MSIZE_V << DMAC_CH2_SRC_MSIZE_S)
+#define DMAC_CH2_SRC_MSIZE_V  0x0000000FU
+#define DMAC_CH2_SRC_MSIZE_S  14
+/** DMAC_CH2_DST_MSIZE : R/W; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_MSIZE    0x0000000FU
+#define DMAC_CH2_DST_MSIZE_M  (DMAC_CH2_DST_MSIZE_V << DMAC_CH2_DST_MSIZE_S)
+#define DMAC_CH2_DST_MSIZE_V  0x0000000FU
+#define DMAC_CH2_DST_MSIZE_S  18
+/** DMAC_CH2_AR_CACHE : R/W; bitpos: [25:22]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AR_CACHE    0x0000000FU
+#define DMAC_CH2_AR_CACHE_M  (DMAC_CH2_AR_CACHE_V << DMAC_CH2_AR_CACHE_S)
+#define DMAC_CH2_AR_CACHE_V  0x0000000FU
+#define DMAC_CH2_AR_CACHE_S  22
+/** DMAC_CH2_AW_CACHE : R/W; bitpos: [29:26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AW_CACHE    0x0000000FU
+#define DMAC_CH2_AW_CACHE_M  (DMAC_CH2_AW_CACHE_V << DMAC_CH2_AW_CACHE_S)
+#define DMAC_CH2_AW_CACHE_V  0x0000000FU
+#define DMAC_CH2_AW_CACHE_S  26
+/** DMAC_CH2_NONPOSTED_LASTWRITE_EN : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_NONPOSTED_LASTWRITE_EN    (BIT(30))
+#define DMAC_CH2_NONPOSTED_LASTWRITE_EN_M  (DMAC_CH2_NONPOSTED_LASTWRITE_EN_V << DMAC_CH2_NONPOSTED_LASTWRITE_EN_S)
+#define DMAC_CH2_NONPOSTED_LASTWRITE_EN_V  0x00000001U
+#define DMAC_CH2_NONPOSTED_LASTWRITE_EN_S  30
+
+/** DMAC_CH2_CTL1_REG register
+ *  NA
+ */
+#define DMAC_CH2_CTL1_REG (DR_REG_DMAC_BASE + 0x21c)
+/** DMAC_CH2_AR_PROT : R/W; bitpos: [2:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AR_PROT    0x00000007U
+#define DMAC_CH2_AR_PROT_M  (DMAC_CH2_AR_PROT_V << DMAC_CH2_AR_PROT_S)
+#define DMAC_CH2_AR_PROT_V  0x00000007U
+#define DMAC_CH2_AR_PROT_S  0
+/** DMAC_CH2_AW_PROT : R/W; bitpos: [5:3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AW_PROT    0x00000007U
+#define DMAC_CH2_AW_PROT_M  (DMAC_CH2_AW_PROT_V << DMAC_CH2_AW_PROT_S)
+#define DMAC_CH2_AW_PROT_V  0x00000007U
+#define DMAC_CH2_AW_PROT_S  3
+/** DMAC_CH2_ARLEN_EN : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ARLEN_EN    (BIT(6))
+#define DMAC_CH2_ARLEN_EN_M  (DMAC_CH2_ARLEN_EN_V << DMAC_CH2_ARLEN_EN_S)
+#define DMAC_CH2_ARLEN_EN_V  0x00000001U
+#define DMAC_CH2_ARLEN_EN_S  6
+/** DMAC_CH2_ARLEN : R/W; bitpos: [14:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ARLEN    0x000000FFU
+#define DMAC_CH2_ARLEN_M  (DMAC_CH2_ARLEN_V << DMAC_CH2_ARLEN_S)
+#define DMAC_CH2_ARLEN_V  0x000000FFU
+#define DMAC_CH2_ARLEN_S  7
+/** DMAC_CH2_AWLEN_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AWLEN_EN    (BIT(15))
+#define DMAC_CH2_AWLEN_EN_M  (DMAC_CH2_AWLEN_EN_V << DMAC_CH2_AWLEN_EN_S)
+#define DMAC_CH2_AWLEN_EN_V  0x00000001U
+#define DMAC_CH2_AWLEN_EN_S  15
+/** DMAC_CH2_AWLEN : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AWLEN    0x000000FFU
+#define DMAC_CH2_AWLEN_M  (DMAC_CH2_AWLEN_V << DMAC_CH2_AWLEN_S)
+#define DMAC_CH2_AWLEN_V  0x000000FFU
+#define DMAC_CH2_AWLEN_S  16
+/** DMAC_CH2_SRC_STAT_EN : R/W; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_STAT_EN    (BIT(24))
+#define DMAC_CH2_SRC_STAT_EN_M  (DMAC_CH2_SRC_STAT_EN_V << DMAC_CH2_SRC_STAT_EN_S)
+#define DMAC_CH2_SRC_STAT_EN_V  0x00000001U
+#define DMAC_CH2_SRC_STAT_EN_S  24
+/** DMAC_CH2_DST_STAT_EN : R/W; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_STAT_EN    (BIT(25))
+#define DMAC_CH2_DST_STAT_EN_M  (DMAC_CH2_DST_STAT_EN_V << DMAC_CH2_DST_STAT_EN_S)
+#define DMAC_CH2_DST_STAT_EN_V  0x00000001U
+#define DMAC_CH2_DST_STAT_EN_S  25
+/** DMAC_CH2_IOC_BLKTFR : R/W; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_IOC_BLKTFR    (BIT(26))
+#define DMAC_CH2_IOC_BLKTFR_M  (DMAC_CH2_IOC_BLKTFR_V << DMAC_CH2_IOC_BLKTFR_S)
+#define DMAC_CH2_IOC_BLKTFR_V  0x00000001U
+#define DMAC_CH2_IOC_BLKTFR_S  26
+/** DMAC_CH2_SHADOWREG_OR_LLI_LAST : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SHADOWREG_OR_LLI_LAST    (BIT(30))
+#define DMAC_CH2_SHADOWREG_OR_LLI_LAST_M  (DMAC_CH2_SHADOWREG_OR_LLI_LAST_V << DMAC_CH2_SHADOWREG_OR_LLI_LAST_S)
+#define DMAC_CH2_SHADOWREG_OR_LLI_LAST_V  0x00000001U
+#define DMAC_CH2_SHADOWREG_OR_LLI_LAST_S  30
+/** DMAC_CH2_SHADOWREG_OR_LLI_VALID : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SHADOWREG_OR_LLI_VALID    (BIT(31))
+#define DMAC_CH2_SHADOWREG_OR_LLI_VALID_M  (DMAC_CH2_SHADOWREG_OR_LLI_VALID_V << DMAC_CH2_SHADOWREG_OR_LLI_VALID_S)
+#define DMAC_CH2_SHADOWREG_OR_LLI_VALID_V  0x00000001U
+#define DMAC_CH2_SHADOWREG_OR_LLI_VALID_S  31
+
+/** DMAC_CH2_CFG0_REG register
+ *  NA
+ */
+#define DMAC_CH2_CFG0_REG (DR_REG_DMAC_BASE + 0x220)
+/** DMAC_CH2_SRC_MULTBLK_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH2_SRC_MULTBLK_TYPE_M  (DMAC_CH2_SRC_MULTBLK_TYPE_V << DMAC_CH2_SRC_MULTBLK_TYPE_S)
+#define DMAC_CH2_SRC_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH2_SRC_MULTBLK_TYPE_S  0
+/** DMAC_CH2_DST_MULTBLK_TYPE : R/W; bitpos: [3:2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH2_DST_MULTBLK_TYPE_M  (DMAC_CH2_DST_MULTBLK_TYPE_V << DMAC_CH2_DST_MULTBLK_TYPE_S)
+#define DMAC_CH2_DST_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH2_DST_MULTBLK_TYPE_S  2
+/** DMAC_CH2_RD_UID : RO; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_RD_UID    0x0000000FU
+#define DMAC_CH2_RD_UID_M  (DMAC_CH2_RD_UID_V << DMAC_CH2_RD_UID_S)
+#define DMAC_CH2_RD_UID_V  0x0000000FU
+#define DMAC_CH2_RD_UID_S  18
+/** DMAC_CH2_WR_UID : RO; bitpos: [28:25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_WR_UID    0x0000000FU
+#define DMAC_CH2_WR_UID_M  (DMAC_CH2_WR_UID_V << DMAC_CH2_WR_UID_S)
+#define DMAC_CH2_WR_UID_V  0x0000000FU
+#define DMAC_CH2_WR_UID_S  25
+
+/** DMAC_CH2_CFG1_REG register
+ *  NA
+ */
+#define DMAC_CH2_CFG1_REG (DR_REG_DMAC_BASE + 0x224)
+/** DMAC_CH2_TT_FC : R/W; bitpos: [2:0]; default: 3;
+ *  NA
+ */
+#define DMAC_CH2_TT_FC    0x00000007U
+#define DMAC_CH2_TT_FC_M  (DMAC_CH2_TT_FC_V << DMAC_CH2_TT_FC_S)
+#define DMAC_CH2_TT_FC_V  0x00000007U
+#define DMAC_CH2_TT_FC_S  0
+/** DMAC_CH2_HS_SEL_SRC : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_HS_SEL_SRC    (BIT(3))
+#define DMAC_CH2_HS_SEL_SRC_M  (DMAC_CH2_HS_SEL_SRC_V << DMAC_CH2_HS_SEL_SRC_S)
+#define DMAC_CH2_HS_SEL_SRC_V  0x00000001U
+#define DMAC_CH2_HS_SEL_SRC_S  3
+/** DMAC_CH2_HS_SEL_DST : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_HS_SEL_DST    (BIT(4))
+#define DMAC_CH2_HS_SEL_DST_M  (DMAC_CH2_HS_SEL_DST_V << DMAC_CH2_HS_SEL_DST_S)
+#define DMAC_CH2_HS_SEL_DST_V  0x00000001U
+#define DMAC_CH2_HS_SEL_DST_S  4
+/** DMAC_CH2_SRC_HWHS_POL : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_HWHS_POL    (BIT(5))
+#define DMAC_CH2_SRC_HWHS_POL_M  (DMAC_CH2_SRC_HWHS_POL_V << DMAC_CH2_SRC_HWHS_POL_S)
+#define DMAC_CH2_SRC_HWHS_POL_V  0x00000001U
+#define DMAC_CH2_SRC_HWHS_POL_S  5
+/** DMAC_CH2_DST_HWHS_POL : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_HWHS_POL    (BIT(6))
+#define DMAC_CH2_DST_HWHS_POL_M  (DMAC_CH2_DST_HWHS_POL_V << DMAC_CH2_DST_HWHS_POL_S)
+#define DMAC_CH2_DST_HWHS_POL_V  0x00000001U
+#define DMAC_CH2_DST_HWHS_POL_S  6
+/** DMAC_CH2_SRC_PER : R/W; bitpos: [8:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_PER    0x00000003U
+#define DMAC_CH2_SRC_PER_M  (DMAC_CH2_SRC_PER_V << DMAC_CH2_SRC_PER_S)
+#define DMAC_CH2_SRC_PER_V  0x00000003U
+#define DMAC_CH2_SRC_PER_S  7
+/** DMAC_CH2_DST_PER : R/W; bitpos: [13:12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_PER    0x00000003U
+#define DMAC_CH2_DST_PER_M  (DMAC_CH2_DST_PER_V << DMAC_CH2_DST_PER_S)
+#define DMAC_CH2_DST_PER_V  0x00000003U
+#define DMAC_CH2_DST_PER_S  12
+/** DMAC_CH2_CH_PRIOR : R/W; bitpos: [19:17]; default: 2;
+ *  NA
+ */
+#define DMAC_CH2_CH_PRIOR    0x00000007U
+#define DMAC_CH2_CH_PRIOR_M  (DMAC_CH2_CH_PRIOR_V << DMAC_CH2_CH_PRIOR_S)
+#define DMAC_CH2_CH_PRIOR_V  0x00000007U
+#define DMAC_CH2_CH_PRIOR_S  17
+/** DMAC_CH2_LOCK_CH : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LOCK_CH    (BIT(20))
+#define DMAC_CH2_LOCK_CH_M  (DMAC_CH2_LOCK_CH_V << DMAC_CH2_LOCK_CH_S)
+#define DMAC_CH2_LOCK_CH_V  0x00000001U
+#define DMAC_CH2_LOCK_CH_S  20
+/** DMAC_CH2_LOCK_CH_L : RO; bitpos: [22:21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LOCK_CH_L    0x00000003U
+#define DMAC_CH2_LOCK_CH_L_M  (DMAC_CH2_LOCK_CH_L_V << DMAC_CH2_LOCK_CH_L_S)
+#define DMAC_CH2_LOCK_CH_L_V  0x00000003U
+#define DMAC_CH2_LOCK_CH_L_S  21
+/** DMAC_CH2_SRC_OSR_LMT : R/W; bitpos: [26:23]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_OSR_LMT    0x0000000FU
+#define DMAC_CH2_SRC_OSR_LMT_M  (DMAC_CH2_SRC_OSR_LMT_V << DMAC_CH2_SRC_OSR_LMT_S)
+#define DMAC_CH2_SRC_OSR_LMT_V  0x0000000FU
+#define DMAC_CH2_SRC_OSR_LMT_S  23
+/** DMAC_CH2_DST_OSR_LMT : R/W; bitpos: [30:27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_OSR_LMT    0x0000000FU
+#define DMAC_CH2_DST_OSR_LMT_M  (DMAC_CH2_DST_OSR_LMT_V << DMAC_CH2_DST_OSR_LMT_S)
+#define DMAC_CH2_DST_OSR_LMT_V  0x0000000FU
+#define DMAC_CH2_DST_OSR_LMT_S  27
+
+/** DMAC_CH2_LLP0_REG register
+ *  NA
+ */
+#define DMAC_CH2_LLP0_REG (DR_REG_DMAC_BASE + 0x228)
+/** DMAC_CH2_LMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LMS    (BIT(0))
+#define DMAC_CH2_LMS_M  (DMAC_CH2_LMS_V << DMAC_CH2_LMS_S)
+#define DMAC_CH2_LMS_V  0x00000001U
+#define DMAC_CH2_LMS_S  0
+/** DMAC_CH2_LOC0 : R/W; bitpos: [31:6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LOC0    0x03FFFFFFU
+#define DMAC_CH2_LOC0_M  (DMAC_CH2_LOC0_V << DMAC_CH2_LOC0_S)
+#define DMAC_CH2_LOC0_V  0x03FFFFFFU
+#define DMAC_CH2_LOC0_S  6
+
+/** DMAC_CH2_LLP1_REG register
+ *  NA
+ */
+#define DMAC_CH2_LLP1_REG (DR_REG_DMAC_BASE + 0x22c)
+/** DMAC_CH2_LOC1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LOC1    0xFFFFFFFFU
+#define DMAC_CH2_LOC1_M  (DMAC_CH2_LOC1_V << DMAC_CH2_LOC1_S)
+#define DMAC_CH2_LOC1_V  0xFFFFFFFFU
+#define DMAC_CH2_LOC1_S  0
+
+/** DMAC_CH2_STATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH2_STATUS0_REG (DR_REG_DMAC_BASE + 0x230)
+/** DMAC_CH2_CMPLTD_BLK_TFR_SIZE : RO; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CMPLTD_BLK_TFR_SIZE    0x003FFFFFU
+#define DMAC_CH2_CMPLTD_BLK_TFR_SIZE_M  (DMAC_CH2_CMPLTD_BLK_TFR_SIZE_V << DMAC_CH2_CMPLTD_BLK_TFR_SIZE_S)
+#define DMAC_CH2_CMPLTD_BLK_TFR_SIZE_V  0x003FFFFFU
+#define DMAC_CH2_CMPLTD_BLK_TFR_SIZE_S  0
+
+/** DMAC_CH2_STATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH2_STATUS1_REG (DR_REG_DMAC_BASE + 0x234)
+/** DMAC_CH2_DATA_LEFT_IN_FIFO : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DATA_LEFT_IN_FIFO    0x00007FFFU
+#define DMAC_CH2_DATA_LEFT_IN_FIFO_M  (DMAC_CH2_DATA_LEFT_IN_FIFO_V << DMAC_CH2_DATA_LEFT_IN_FIFO_S)
+#define DMAC_CH2_DATA_LEFT_IN_FIFO_V  0x00007FFFU
+#define DMAC_CH2_DATA_LEFT_IN_FIFO_S  0
+
+/** DMAC_CH2_SWHSSRC0_REG register
+ *  NA
+ */
+#define DMAC_CH2_SWHSSRC0_REG (DR_REG_DMAC_BASE + 0x238)
+/** DMAC_CH2_SWHS_REQ_SRC : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_REQ_SRC    (BIT(0))
+#define DMAC_CH2_SWHS_REQ_SRC_M  (DMAC_CH2_SWHS_REQ_SRC_V << DMAC_CH2_SWHS_REQ_SRC_S)
+#define DMAC_CH2_SWHS_REQ_SRC_V  0x00000001U
+#define DMAC_CH2_SWHS_REQ_SRC_S  0
+/** DMAC_CH2_SWHS_REQ_SRC_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_REQ_SRC_WE    (BIT(1))
+#define DMAC_CH2_SWHS_REQ_SRC_WE_M  (DMAC_CH2_SWHS_REQ_SRC_WE_V << DMAC_CH2_SWHS_REQ_SRC_WE_S)
+#define DMAC_CH2_SWHS_REQ_SRC_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_REQ_SRC_WE_S  1
+/** DMAC_CH2_SWHS_SGLREQ_SRC : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_SGLREQ_SRC    (BIT(2))
+#define DMAC_CH2_SWHS_SGLREQ_SRC_M  (DMAC_CH2_SWHS_SGLREQ_SRC_V << DMAC_CH2_SWHS_SGLREQ_SRC_S)
+#define DMAC_CH2_SWHS_SGLREQ_SRC_V  0x00000001U
+#define DMAC_CH2_SWHS_SGLREQ_SRC_S  2
+/** DMAC_CH2_SWHS_SGLREQ_SRC_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_SGLREQ_SRC_WE    (BIT(3))
+#define DMAC_CH2_SWHS_SGLREQ_SRC_WE_M  (DMAC_CH2_SWHS_SGLREQ_SRC_WE_V << DMAC_CH2_SWHS_SGLREQ_SRC_WE_S)
+#define DMAC_CH2_SWHS_SGLREQ_SRC_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_SGLREQ_SRC_WE_S  3
+/** DMAC_CH2_SWHS_LST_SRC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_LST_SRC    (BIT(4))
+#define DMAC_CH2_SWHS_LST_SRC_M  (DMAC_CH2_SWHS_LST_SRC_V << DMAC_CH2_SWHS_LST_SRC_S)
+#define DMAC_CH2_SWHS_LST_SRC_V  0x00000001U
+#define DMAC_CH2_SWHS_LST_SRC_S  4
+/** DMAC_CH2_SWHS_LST_SRC_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_LST_SRC_WE    (BIT(5))
+#define DMAC_CH2_SWHS_LST_SRC_WE_M  (DMAC_CH2_SWHS_LST_SRC_WE_V << DMAC_CH2_SWHS_LST_SRC_WE_S)
+#define DMAC_CH2_SWHS_LST_SRC_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_LST_SRC_WE_S  5
+
+/** DMAC_CH2_SWHSDST0_REG register
+ *  NA
+ */
+#define DMAC_CH2_SWHSDST0_REG (DR_REG_DMAC_BASE + 0x240)
+/** DMAC_CH2_SWHS_REQ_DST : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_REQ_DST    (BIT(0))
+#define DMAC_CH2_SWHS_REQ_DST_M  (DMAC_CH2_SWHS_REQ_DST_V << DMAC_CH2_SWHS_REQ_DST_S)
+#define DMAC_CH2_SWHS_REQ_DST_V  0x00000001U
+#define DMAC_CH2_SWHS_REQ_DST_S  0
+/** DMAC_CH2_SWHS_REQ_DST_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_REQ_DST_WE    (BIT(1))
+#define DMAC_CH2_SWHS_REQ_DST_WE_M  (DMAC_CH2_SWHS_REQ_DST_WE_V << DMAC_CH2_SWHS_REQ_DST_WE_S)
+#define DMAC_CH2_SWHS_REQ_DST_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_REQ_DST_WE_S  1
+/** DMAC_CH2_SWHS_SGLREQ_DST : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_SGLREQ_DST    (BIT(2))
+#define DMAC_CH2_SWHS_SGLREQ_DST_M  (DMAC_CH2_SWHS_SGLREQ_DST_V << DMAC_CH2_SWHS_SGLREQ_DST_S)
+#define DMAC_CH2_SWHS_SGLREQ_DST_V  0x00000001U
+#define DMAC_CH2_SWHS_SGLREQ_DST_S  2
+/** DMAC_CH2_SWHS_SGLREQ_DST_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_SGLREQ_DST_WE    (BIT(3))
+#define DMAC_CH2_SWHS_SGLREQ_DST_WE_M  (DMAC_CH2_SWHS_SGLREQ_DST_WE_V << DMAC_CH2_SWHS_SGLREQ_DST_WE_S)
+#define DMAC_CH2_SWHS_SGLREQ_DST_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_SGLREQ_DST_WE_S  3
+/** DMAC_CH2_SWHS_LST_DST : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_LST_DST    (BIT(4))
+#define DMAC_CH2_SWHS_LST_DST_M  (DMAC_CH2_SWHS_LST_DST_V << DMAC_CH2_SWHS_LST_DST_S)
+#define DMAC_CH2_SWHS_LST_DST_V  0x00000001U
+#define DMAC_CH2_SWHS_LST_DST_S  4
+/** DMAC_CH2_SWHS_LST_DST_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_LST_DST_WE    (BIT(5))
+#define DMAC_CH2_SWHS_LST_DST_WE_M  (DMAC_CH2_SWHS_LST_DST_WE_V << DMAC_CH2_SWHS_LST_DST_WE_S)
+#define DMAC_CH2_SWHS_LST_DST_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_LST_DST_WE_S  5
+
+/** DMAC_CH2_BLK_TFR_RESUMEREQ0_REG register
+ *  NA
+ */
+#define DMAC_CH2_BLK_TFR_RESUMEREQ0_REG (DR_REG_DMAC_BASE + 0x248)
+/** DMAC_CH2_BLK_TFR_RESUMEREQ : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_BLK_TFR_RESUMEREQ    (BIT(0))
+#define DMAC_CH2_BLK_TFR_RESUMEREQ_M  (DMAC_CH2_BLK_TFR_RESUMEREQ_V << DMAC_CH2_BLK_TFR_RESUMEREQ_S)
+#define DMAC_CH2_BLK_TFR_RESUMEREQ_V  0x00000001U
+#define DMAC_CH2_BLK_TFR_RESUMEREQ_S  0
+
+/** DMAC_CH2_AXI_ID0_REG register
+ *  NA
+ */
+#define DMAC_CH2_AXI_ID0_REG (DR_REG_DMAC_BASE + 0x250)
+/** DMAC_CH2_AXI_READ_ID_SUFFIX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AXI_READ_ID_SUFFIX    (BIT(0))
+#define DMAC_CH2_AXI_READ_ID_SUFFIX_M  (DMAC_CH2_AXI_READ_ID_SUFFIX_V << DMAC_CH2_AXI_READ_ID_SUFFIX_S)
+#define DMAC_CH2_AXI_READ_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH2_AXI_READ_ID_SUFFIX_S  0
+/** DMAC_CH2_AXI_WRITE_ID_SUFFIX : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AXI_WRITE_ID_SUFFIX    (BIT(16))
+#define DMAC_CH2_AXI_WRITE_ID_SUFFIX_M  (DMAC_CH2_AXI_WRITE_ID_SUFFIX_V << DMAC_CH2_AXI_WRITE_ID_SUFFIX_S)
+#define DMAC_CH2_AXI_WRITE_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH2_AXI_WRITE_ID_SUFFIX_S  16
+
+/** DMAC_CH2_AXI_QOS0_REG register
+ *  NA
+ */
+#define DMAC_CH2_AXI_QOS0_REG (DR_REG_DMAC_BASE + 0x258)
+/** DMAC_CH2_AXI_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AXI_AWQOS    0x0000000FU
+#define DMAC_CH2_AXI_AWQOS_M  (DMAC_CH2_AXI_AWQOS_V << DMAC_CH2_AXI_AWQOS_S)
+#define DMAC_CH2_AXI_AWQOS_V  0x0000000FU
+#define DMAC_CH2_AXI_AWQOS_S  0
+/** DMAC_CH2_AXI_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AXI_ARQOS    0x0000000FU
+#define DMAC_CH2_AXI_ARQOS_M  (DMAC_CH2_AXI_ARQOS_V << DMAC_CH2_AXI_ARQOS_S)
+#define DMAC_CH2_AXI_ARQOS_V  0x0000000FU
+#define DMAC_CH2_AXI_ARQOS_S  4
+
+/** DMAC_CH2_SSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH2_SSTAT0_REG (DR_REG_DMAC_BASE + 0x260)
+/** DMAC_CH2_SSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SSTAT    0xFFFFFFFFU
+#define DMAC_CH2_SSTAT_M  (DMAC_CH2_SSTAT_V << DMAC_CH2_SSTAT_S)
+#define DMAC_CH2_SSTAT_V  0xFFFFFFFFU
+#define DMAC_CH2_SSTAT_S  0
+
+/** DMAC_CH2_DSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH2_DSTAT0_REG (DR_REG_DMAC_BASE + 0x268)
+/** DMAC_CH2_DSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DSTAT    0xFFFFFFFFU
+#define DMAC_CH2_DSTAT_M  (DMAC_CH2_DSTAT_V << DMAC_CH2_DSTAT_S)
+#define DMAC_CH2_DSTAT_V  0xFFFFFFFFU
+#define DMAC_CH2_DSTAT_S  0
+
+/** DMAC_CH2_SSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH2_SSTATAR0_REG (DR_REG_DMAC_BASE + 0x270)
+/** DMAC_CH2_SSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SSTATAR0    0xFFFFFFFFU
+#define DMAC_CH2_SSTATAR0_M  (DMAC_CH2_SSTATAR0_V << DMAC_CH2_SSTATAR0_S)
+#define DMAC_CH2_SSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH2_SSTATAR0_S  0
+
+/** DMAC_CH2_SSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH2_SSTATAR1_REG (DR_REG_DMAC_BASE + 0x274)
+/** DMAC_CH2_SSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SSTATAR1    0xFFFFFFFFU
+#define DMAC_CH2_SSTATAR1_M  (DMAC_CH2_SSTATAR1_V << DMAC_CH2_SSTATAR1_S)
+#define DMAC_CH2_SSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH2_SSTATAR1_S  0
+
+/** DMAC_CH2_DSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH2_DSTATAR0_REG (DR_REG_DMAC_BASE + 0x278)
+/** DMAC_CH2_DSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DSTATAR0    0xFFFFFFFFU
+#define DMAC_CH2_DSTATAR0_M  (DMAC_CH2_DSTATAR0_V << DMAC_CH2_DSTATAR0_S)
+#define DMAC_CH2_DSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH2_DSTATAR0_S  0
+
+/** DMAC_CH2_DSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH2_DSTATAR1_REG (DR_REG_DMAC_BASE + 0x27c)
+/** DMAC_CH2_DSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DSTATAR1    0xFFFFFFFFU
+#define DMAC_CH2_DSTATAR1_M  (DMAC_CH2_DSTATAR1_V << DMAC_CH2_DSTATAR1_S)
+#define DMAC_CH2_DSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH2_DSTATAR1_S  0
+
+/** DMAC_CH2_INTSTATUS_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSTATUS_ENABLE0_REG (DR_REG_DMAC_BASE + 0x280)
+/** DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_V << DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_V << DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT_V << DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT_V << DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : R/W; bitpos: [13]; default:
+ *  1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT_M  (DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT_V << DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT_M  (DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT_V << DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT_M  (DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT_V << DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH2_INTSTATUS_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSTATUS_ENABLE1_REG (DR_REG_DMAC_BASE + 0x284)
+/** DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH2_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x288)
+/** DMAC_CH2_BLOCK_TFR_DONE_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH2_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH2_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH2_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH2_DMA_TFR_DONE_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH2_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH2_DMA_TFR_DONE_INTSTAT_V << DMAC_CH2_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH2_SRC_TRANSCOMP_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH2_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH2_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH2_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH2_DST_TRANSCOMP_INTSTAT : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH2_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH2_DST_TRANSCOMP_INTSTAT_V << DMAC_CH2_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH2_SRC_DEC_ERR_INTSTAT : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH2_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH2_SRC_DEC_ERR_INTSTAT_V << DMAC_CH2_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH2_DST_DEC_ERR_INTSTAT : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH2_DST_DEC_ERR_INTSTAT_M  (DMAC_CH2_DST_DEC_ERR_INTSTAT_V << DMAC_CH2_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH2_SRC_SLV_ERR_INTSTAT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH2_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH2_SRC_SLV_ERR_INTSTAT_V << DMAC_CH2_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH2_DST_SLV_ERR_INTSTAT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH2_DST_SLV_ERR_INTSTAT_M  (DMAC_CH2_DST_SLV_ERR_INTSTAT_V << DMAC_CH2_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH2_SLVIF_DEC_ERR_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH2_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH2_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH2_CH_LOCK_CLEARED_INTSTAT : RO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH2_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH2_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH2_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH2_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT : RO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH2_CH_SUSPENDED_INTSTAT : RO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH2_CH_SUSPENDED_INTSTAT_M  (DMAC_CH2_CH_SUSPENDED_INTSTAT_V << DMAC_CH2_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH2_CH_DISABLED_INTSTAT : RO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH2_CH_DISABLED_INTSTAT_M  (DMAC_CH2_CH_DISABLED_INTSTAT_V << DMAC_CH2_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH2_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH2_CH_ABORTED_INTSTAT : RO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH2_CH_ABORTED_INTSTAT_M  (DMAC_CH2_CH_ABORTED_INTSTAT_V << DMAC_CH2_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH2_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH2_INTSTATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSTATUS1_REG (DR_REG_DMAC_BASE + 0x28c)
+/** DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH2_INTSIGNAL_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSIGNAL_ENABLE0_REG (DR_REG_DMAC_BASE + 0x290)
+/** DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL    (BIT(0))
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_M  (DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V << DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S  0
+/** DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL    (BIT(1))
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_M  (DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_V << DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_S  1
+/** DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL    (BIT(3))
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_M  (DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V << DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S  3
+/** DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL    (BIT(4))
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_M  (DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_V << DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_S  4
+/** DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL    (BIT(5))
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_S  5
+/** DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL    (BIT(6))
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_S  6
+/** DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL    (BIT(7))
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_S  7
+/** DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL    (BIT(8))
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_S  8
+/** DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL    (BIT(9))
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S  9
+/** DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL    (BIT(10))
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S  10
+/** DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL    (BIT(11))
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S  11
+/** DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL    (BIT(12))
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S  12
+/** DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL : R/W; bitpos: [13];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL    (BIT(13))
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S  13
+/** DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL    (BIT(14))
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S  14
+/** DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL    (BIT(16))
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S  16
+/** DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL    (BIT(17))
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S  17
+/** DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL    (BIT(18))
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S  18
+/** DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL    (BIT(19))
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S  19
+/** DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL    (BIT(20))
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S  20
+/** DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL    (BIT(21))
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S  21
+/** DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL    (BIT(25))
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S  25
+/** DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL    (BIT(27))
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_M  (DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V << DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S  27
+/** DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL    (BIT(28))
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_M  (DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V << DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S  28
+/** DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL    (BIT(29))
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_M  (DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_V << DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_S  29
+/** DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL    (BIT(30))
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL_M  (DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL_V << DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL_S  30
+/** DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL    (BIT(31))
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL_M  (DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL_V << DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL_S  31
+
+/** DMAC_CH2_INTSIGNAL_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSIGNAL_ENABLE1_REG (DR_REG_DMAC_BASE + 0x294)
+/** DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL    (BIT(0))
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V << DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S  0
+/** DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL    (BIT(1))
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S  1
+/** DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL    (BIT(2))
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V << DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S  2
+/** DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL    (BIT(3))
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S  3
+
+/** DMAC_CH2_INTCLEAR0_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTCLEAR0_REG (DR_REG_DMAC_BASE + 0x298)
+/** DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_V << DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT : WO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_V << DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT : WO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT_V << DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT : WO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT_V << DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : WO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : WO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT : WO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT : WO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT : WO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT : WO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : WO; bitpos: [20]; default:
+ *  0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT : WO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT : WO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT : WO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT : WO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT : WO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT_M  (DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT_V << DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT : WO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT_M  (DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT_V << DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT : WO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT_M  (DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT_V << DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH2_INTCLEAR1_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTCLEAR1_REG (DR_REG_DMAC_BASE + 0x29c)
+/** DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT : WO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH3_SAR0_REG register
+ *  NA
+ */
+#define DMAC_CH3_SAR0_REG (DR_REG_DMAC_BASE + 0x300)
+/** DMAC_CH3_SAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SAR0    0xFFFFFFFFU
+#define DMAC_CH3_SAR0_M  (DMAC_CH3_SAR0_V << DMAC_CH3_SAR0_S)
+#define DMAC_CH3_SAR0_V  0xFFFFFFFFU
+#define DMAC_CH3_SAR0_S  0
+
+/** DMAC_CH3_SAR1_REG register
+ *  NA
+ */
+#define DMAC_CH3_SAR1_REG (DR_REG_DMAC_BASE + 0x304)
+/** DMAC_CH3_SAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SAR1    0xFFFFFFFFU
+#define DMAC_CH3_SAR1_M  (DMAC_CH3_SAR1_V << DMAC_CH3_SAR1_S)
+#define DMAC_CH3_SAR1_V  0xFFFFFFFFU
+#define DMAC_CH3_SAR1_S  0
+
+/** DMAC_CH3_DAR0_REG register
+ *  NA
+ */
+#define DMAC_CH3_DAR0_REG (DR_REG_DMAC_BASE + 0x308)
+/** DMAC_CH3_DAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DAR0    0xFFFFFFFFU
+#define DMAC_CH3_DAR0_M  (DMAC_CH3_DAR0_V << DMAC_CH3_DAR0_S)
+#define DMAC_CH3_DAR0_V  0xFFFFFFFFU
+#define DMAC_CH3_DAR0_S  0
+
+/** DMAC_CH3_DAR1_REG register
+ *  NA
+ */
+#define DMAC_CH3_DAR1_REG (DR_REG_DMAC_BASE + 0x30c)
+/** DMAC_CH3_DAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DAR1    0xFFFFFFFFU
+#define DMAC_CH3_DAR1_M  (DMAC_CH3_DAR1_V << DMAC_CH3_DAR1_S)
+#define DMAC_CH3_DAR1_V  0xFFFFFFFFU
+#define DMAC_CH3_DAR1_S  0
+
+/** DMAC_CH3_BLOCK_TS0_REG register
+ *  NA
+ */
+#define DMAC_CH3_BLOCK_TS0_REG (DR_REG_DMAC_BASE + 0x310)
+/** DMAC_CH3_BLOCK_TS : R/W; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_BLOCK_TS    0x003FFFFFU
+#define DMAC_CH3_BLOCK_TS_M  (DMAC_CH3_BLOCK_TS_V << DMAC_CH3_BLOCK_TS_S)
+#define DMAC_CH3_BLOCK_TS_V  0x003FFFFFU
+#define DMAC_CH3_BLOCK_TS_S  0
+
+/** DMAC_CH3_CTL0_REG register
+ *  NA
+ */
+#define DMAC_CH3_CTL0_REG (DR_REG_DMAC_BASE + 0x318)
+/** DMAC_CH3_SMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SMS    (BIT(0))
+#define DMAC_CH3_SMS_M  (DMAC_CH3_SMS_V << DMAC_CH3_SMS_S)
+#define DMAC_CH3_SMS_V  0x00000001U
+#define DMAC_CH3_SMS_S  0
+/** DMAC_CH3_DMS : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DMS    (BIT(2))
+#define DMAC_CH3_DMS_M  (DMAC_CH3_DMS_V << DMAC_CH3_DMS_S)
+#define DMAC_CH3_DMS_V  0x00000001U
+#define DMAC_CH3_DMS_S  2
+/** DMAC_CH3_SINC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SINC    (BIT(4))
+#define DMAC_CH3_SINC_M  (DMAC_CH3_SINC_V << DMAC_CH3_SINC_S)
+#define DMAC_CH3_SINC_V  0x00000001U
+#define DMAC_CH3_SINC_S  4
+/** DMAC_CH3_DINC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DINC    (BIT(6))
+#define DMAC_CH3_DINC_M  (DMAC_CH3_DINC_V << DMAC_CH3_DINC_S)
+#define DMAC_CH3_DINC_V  0x00000001U
+#define DMAC_CH3_DINC_S  6
+/** DMAC_CH3_SRC_TR_WIDTH : R/W; bitpos: [10:8]; default: 2;
+ *  NA
+ */
+#define DMAC_CH3_SRC_TR_WIDTH    0x00000007U
+#define DMAC_CH3_SRC_TR_WIDTH_M  (DMAC_CH3_SRC_TR_WIDTH_V << DMAC_CH3_SRC_TR_WIDTH_S)
+#define DMAC_CH3_SRC_TR_WIDTH_V  0x00000007U
+#define DMAC_CH3_SRC_TR_WIDTH_S  8
+/** DMAC_CH3_DST_TR_WIDTH : R/W; bitpos: [13:11]; default: 2;
+ *  NA
+ */
+#define DMAC_CH3_DST_TR_WIDTH    0x00000007U
+#define DMAC_CH3_DST_TR_WIDTH_M  (DMAC_CH3_DST_TR_WIDTH_V << DMAC_CH3_DST_TR_WIDTH_S)
+#define DMAC_CH3_DST_TR_WIDTH_V  0x00000007U
+#define DMAC_CH3_DST_TR_WIDTH_S  11
+/** DMAC_CH3_SRC_MSIZE : R/W; bitpos: [17:14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_MSIZE    0x0000000FU
+#define DMAC_CH3_SRC_MSIZE_M  (DMAC_CH3_SRC_MSIZE_V << DMAC_CH3_SRC_MSIZE_S)
+#define DMAC_CH3_SRC_MSIZE_V  0x0000000FU
+#define DMAC_CH3_SRC_MSIZE_S  14
+/** DMAC_CH3_DST_MSIZE : R/W; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_MSIZE    0x0000000FU
+#define DMAC_CH3_DST_MSIZE_M  (DMAC_CH3_DST_MSIZE_V << DMAC_CH3_DST_MSIZE_S)
+#define DMAC_CH3_DST_MSIZE_V  0x0000000FU
+#define DMAC_CH3_DST_MSIZE_S  18
+/** DMAC_CH3_AR_CACHE : R/W; bitpos: [25:22]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AR_CACHE    0x0000000FU
+#define DMAC_CH3_AR_CACHE_M  (DMAC_CH3_AR_CACHE_V << DMAC_CH3_AR_CACHE_S)
+#define DMAC_CH3_AR_CACHE_V  0x0000000FU
+#define DMAC_CH3_AR_CACHE_S  22
+/** DMAC_CH3_AW_CACHE : R/W; bitpos: [29:26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AW_CACHE    0x0000000FU
+#define DMAC_CH3_AW_CACHE_M  (DMAC_CH3_AW_CACHE_V << DMAC_CH3_AW_CACHE_S)
+#define DMAC_CH3_AW_CACHE_V  0x0000000FU
+#define DMAC_CH3_AW_CACHE_S  26
+/** DMAC_CH3_NONPOSTED_LASTWRITE_EN : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_NONPOSTED_LASTWRITE_EN    (BIT(30))
+#define DMAC_CH3_NONPOSTED_LASTWRITE_EN_M  (DMAC_CH3_NONPOSTED_LASTWRITE_EN_V << DMAC_CH3_NONPOSTED_LASTWRITE_EN_S)
+#define DMAC_CH3_NONPOSTED_LASTWRITE_EN_V  0x00000001U
+#define DMAC_CH3_NONPOSTED_LASTWRITE_EN_S  30
+
+/** DMAC_CH3_CTL1_REG register
+ *  NA
+ */
+#define DMAC_CH3_CTL1_REG (DR_REG_DMAC_BASE + 0x31c)
+/** DMAC_CH3_AR_PROT : R/W; bitpos: [2:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AR_PROT    0x00000007U
+#define DMAC_CH3_AR_PROT_M  (DMAC_CH3_AR_PROT_V << DMAC_CH3_AR_PROT_S)
+#define DMAC_CH3_AR_PROT_V  0x00000007U
+#define DMAC_CH3_AR_PROT_S  0
+/** DMAC_CH3_AW_PROT : R/W; bitpos: [5:3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AW_PROT    0x00000007U
+#define DMAC_CH3_AW_PROT_M  (DMAC_CH3_AW_PROT_V << DMAC_CH3_AW_PROT_S)
+#define DMAC_CH3_AW_PROT_V  0x00000007U
+#define DMAC_CH3_AW_PROT_S  3
+/** DMAC_CH3_ARLEN_EN : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ARLEN_EN    (BIT(6))
+#define DMAC_CH3_ARLEN_EN_M  (DMAC_CH3_ARLEN_EN_V << DMAC_CH3_ARLEN_EN_S)
+#define DMAC_CH3_ARLEN_EN_V  0x00000001U
+#define DMAC_CH3_ARLEN_EN_S  6
+/** DMAC_CH3_ARLEN : R/W; bitpos: [14:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ARLEN    0x000000FFU
+#define DMAC_CH3_ARLEN_M  (DMAC_CH3_ARLEN_V << DMAC_CH3_ARLEN_S)
+#define DMAC_CH3_ARLEN_V  0x000000FFU
+#define DMAC_CH3_ARLEN_S  7
+/** DMAC_CH3_AWLEN_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AWLEN_EN    (BIT(15))
+#define DMAC_CH3_AWLEN_EN_M  (DMAC_CH3_AWLEN_EN_V << DMAC_CH3_AWLEN_EN_S)
+#define DMAC_CH3_AWLEN_EN_V  0x00000001U
+#define DMAC_CH3_AWLEN_EN_S  15
+/** DMAC_CH3_AWLEN : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AWLEN    0x000000FFU
+#define DMAC_CH3_AWLEN_M  (DMAC_CH3_AWLEN_V << DMAC_CH3_AWLEN_S)
+#define DMAC_CH3_AWLEN_V  0x000000FFU
+#define DMAC_CH3_AWLEN_S  16
+/** DMAC_CH3_SRC_STAT_EN : R/W; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_STAT_EN    (BIT(24))
+#define DMAC_CH3_SRC_STAT_EN_M  (DMAC_CH3_SRC_STAT_EN_V << DMAC_CH3_SRC_STAT_EN_S)
+#define DMAC_CH3_SRC_STAT_EN_V  0x00000001U
+#define DMAC_CH3_SRC_STAT_EN_S  24
+/** DMAC_CH3_DST_STAT_EN : R/W; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_STAT_EN    (BIT(25))
+#define DMAC_CH3_DST_STAT_EN_M  (DMAC_CH3_DST_STAT_EN_V << DMAC_CH3_DST_STAT_EN_S)
+#define DMAC_CH3_DST_STAT_EN_V  0x00000001U
+#define DMAC_CH3_DST_STAT_EN_S  25
+/** DMAC_CH3_IOC_BLKTFR : R/W; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_IOC_BLKTFR    (BIT(26))
+#define DMAC_CH3_IOC_BLKTFR_M  (DMAC_CH3_IOC_BLKTFR_V << DMAC_CH3_IOC_BLKTFR_S)
+#define DMAC_CH3_IOC_BLKTFR_V  0x00000001U
+#define DMAC_CH3_IOC_BLKTFR_S  26
+/** DMAC_CH3_SHADOWREG_OR_LLI_LAST : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SHADOWREG_OR_LLI_LAST    (BIT(30))
+#define DMAC_CH3_SHADOWREG_OR_LLI_LAST_M  (DMAC_CH3_SHADOWREG_OR_LLI_LAST_V << DMAC_CH3_SHADOWREG_OR_LLI_LAST_S)
+#define DMAC_CH3_SHADOWREG_OR_LLI_LAST_V  0x00000001U
+#define DMAC_CH3_SHADOWREG_OR_LLI_LAST_S  30
+/** DMAC_CH3_SHADOWREG_OR_LLI_VALID : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SHADOWREG_OR_LLI_VALID    (BIT(31))
+#define DMAC_CH3_SHADOWREG_OR_LLI_VALID_M  (DMAC_CH3_SHADOWREG_OR_LLI_VALID_V << DMAC_CH3_SHADOWREG_OR_LLI_VALID_S)
+#define DMAC_CH3_SHADOWREG_OR_LLI_VALID_V  0x00000001U
+#define DMAC_CH3_SHADOWREG_OR_LLI_VALID_S  31
+
+/** DMAC_CH3_CFG0_REG register
+ *  NA
+ */
+#define DMAC_CH3_CFG0_REG (DR_REG_DMAC_BASE + 0x320)
+/** DMAC_CH3_SRC_MULTBLK_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH3_SRC_MULTBLK_TYPE_M  (DMAC_CH3_SRC_MULTBLK_TYPE_V << DMAC_CH3_SRC_MULTBLK_TYPE_S)
+#define DMAC_CH3_SRC_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH3_SRC_MULTBLK_TYPE_S  0
+/** DMAC_CH3_DST_MULTBLK_TYPE : R/W; bitpos: [3:2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH3_DST_MULTBLK_TYPE_M  (DMAC_CH3_DST_MULTBLK_TYPE_V << DMAC_CH3_DST_MULTBLK_TYPE_S)
+#define DMAC_CH3_DST_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH3_DST_MULTBLK_TYPE_S  2
+/** DMAC_CH3_RD_UID : RO; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_RD_UID    0x0000000FU
+#define DMAC_CH3_RD_UID_M  (DMAC_CH3_RD_UID_V << DMAC_CH3_RD_UID_S)
+#define DMAC_CH3_RD_UID_V  0x0000000FU
+#define DMAC_CH3_RD_UID_S  18
+/** DMAC_CH3_WR_UID : RO; bitpos: [28:25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_WR_UID    0x0000000FU
+#define DMAC_CH3_WR_UID_M  (DMAC_CH3_WR_UID_V << DMAC_CH3_WR_UID_S)
+#define DMAC_CH3_WR_UID_V  0x0000000FU
+#define DMAC_CH3_WR_UID_S  25
+
+/** DMAC_CH3_CFG1_REG register
+ *  NA
+ */
+#define DMAC_CH3_CFG1_REG (DR_REG_DMAC_BASE + 0x324)
+/** DMAC_CH3_TT_FC : R/W; bitpos: [2:0]; default: 3;
+ *  NA
+ */
+#define DMAC_CH3_TT_FC    0x00000007U
+#define DMAC_CH3_TT_FC_M  (DMAC_CH3_TT_FC_V << DMAC_CH3_TT_FC_S)
+#define DMAC_CH3_TT_FC_V  0x00000007U
+#define DMAC_CH3_TT_FC_S  0
+/** DMAC_CH3_HS_SEL_SRC : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_HS_SEL_SRC    (BIT(3))
+#define DMAC_CH3_HS_SEL_SRC_M  (DMAC_CH3_HS_SEL_SRC_V << DMAC_CH3_HS_SEL_SRC_S)
+#define DMAC_CH3_HS_SEL_SRC_V  0x00000001U
+#define DMAC_CH3_HS_SEL_SRC_S  3
+/** DMAC_CH3_HS_SEL_DST : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_HS_SEL_DST    (BIT(4))
+#define DMAC_CH3_HS_SEL_DST_M  (DMAC_CH3_HS_SEL_DST_V << DMAC_CH3_HS_SEL_DST_S)
+#define DMAC_CH3_HS_SEL_DST_V  0x00000001U
+#define DMAC_CH3_HS_SEL_DST_S  4
+/** DMAC_CH3_SRC_HWHS_POL : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_HWHS_POL    (BIT(5))
+#define DMAC_CH3_SRC_HWHS_POL_M  (DMAC_CH3_SRC_HWHS_POL_V << DMAC_CH3_SRC_HWHS_POL_S)
+#define DMAC_CH3_SRC_HWHS_POL_V  0x00000001U
+#define DMAC_CH3_SRC_HWHS_POL_S  5
+/** DMAC_CH3_DST_HWHS_POL : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_HWHS_POL    (BIT(6))
+#define DMAC_CH3_DST_HWHS_POL_M  (DMAC_CH3_DST_HWHS_POL_V << DMAC_CH3_DST_HWHS_POL_S)
+#define DMAC_CH3_DST_HWHS_POL_V  0x00000001U
+#define DMAC_CH3_DST_HWHS_POL_S  6
+/** DMAC_CH3_SRC_PER : R/W; bitpos: [8:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_PER    0x00000003U
+#define DMAC_CH3_SRC_PER_M  (DMAC_CH3_SRC_PER_V << DMAC_CH3_SRC_PER_S)
+#define DMAC_CH3_SRC_PER_V  0x00000003U
+#define DMAC_CH3_SRC_PER_S  7
+/** DMAC_CH3_DST_PER : R/W; bitpos: [13:12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_PER    0x00000003U
+#define DMAC_CH3_DST_PER_M  (DMAC_CH3_DST_PER_V << DMAC_CH3_DST_PER_S)
+#define DMAC_CH3_DST_PER_V  0x00000003U
+#define DMAC_CH3_DST_PER_S  12
+/** DMAC_CH3_CH_PRIOR : R/W; bitpos: [19:17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_CH_PRIOR    0x00000007U
+#define DMAC_CH3_CH_PRIOR_M  (DMAC_CH3_CH_PRIOR_V << DMAC_CH3_CH_PRIOR_S)
+#define DMAC_CH3_CH_PRIOR_V  0x00000007U
+#define DMAC_CH3_CH_PRIOR_S  17
+/** DMAC_CH3_LOCK_CH : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LOCK_CH    (BIT(20))
+#define DMAC_CH3_LOCK_CH_M  (DMAC_CH3_LOCK_CH_V << DMAC_CH3_LOCK_CH_S)
+#define DMAC_CH3_LOCK_CH_V  0x00000001U
+#define DMAC_CH3_LOCK_CH_S  20
+/** DMAC_CH3_LOCK_CH_L : RO; bitpos: [22:21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LOCK_CH_L    0x00000003U
+#define DMAC_CH3_LOCK_CH_L_M  (DMAC_CH3_LOCK_CH_L_V << DMAC_CH3_LOCK_CH_L_S)
+#define DMAC_CH3_LOCK_CH_L_V  0x00000003U
+#define DMAC_CH3_LOCK_CH_L_S  21
+/** DMAC_CH3_SRC_OSR_LMT : R/W; bitpos: [26:23]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_OSR_LMT    0x0000000FU
+#define DMAC_CH3_SRC_OSR_LMT_M  (DMAC_CH3_SRC_OSR_LMT_V << DMAC_CH3_SRC_OSR_LMT_S)
+#define DMAC_CH3_SRC_OSR_LMT_V  0x0000000FU
+#define DMAC_CH3_SRC_OSR_LMT_S  23
+/** DMAC_CH3_DST_OSR_LMT : R/W; bitpos: [30:27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_OSR_LMT    0x0000000FU
+#define DMAC_CH3_DST_OSR_LMT_M  (DMAC_CH3_DST_OSR_LMT_V << DMAC_CH3_DST_OSR_LMT_S)
+#define DMAC_CH3_DST_OSR_LMT_V  0x0000000FU
+#define DMAC_CH3_DST_OSR_LMT_S  27
+
+/** DMAC_CH3_LLP0_REG register
+ *  NA
+ */
+#define DMAC_CH3_LLP0_REG (DR_REG_DMAC_BASE + 0x328)
+/** DMAC_CH3_LMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LMS    (BIT(0))
+#define DMAC_CH3_LMS_M  (DMAC_CH3_LMS_V << DMAC_CH3_LMS_S)
+#define DMAC_CH3_LMS_V  0x00000001U
+#define DMAC_CH3_LMS_S  0
+/** DMAC_CH3_LOC0 : R/W; bitpos: [31:6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LOC0    0x03FFFFFFU
+#define DMAC_CH3_LOC0_M  (DMAC_CH3_LOC0_V << DMAC_CH3_LOC0_S)
+#define DMAC_CH3_LOC0_V  0x03FFFFFFU
+#define DMAC_CH3_LOC0_S  6
+
+/** DMAC_CH3_LLP1_REG register
+ *  NA
+ */
+#define DMAC_CH3_LLP1_REG (DR_REG_DMAC_BASE + 0x32c)
+/** DMAC_CH3_LOC1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LOC1    0xFFFFFFFFU
+#define DMAC_CH3_LOC1_M  (DMAC_CH3_LOC1_V << DMAC_CH3_LOC1_S)
+#define DMAC_CH3_LOC1_V  0xFFFFFFFFU
+#define DMAC_CH3_LOC1_S  0
+
+/** DMAC_CH3_STATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH3_STATUS0_REG (DR_REG_DMAC_BASE + 0x330)
+/** DMAC_CH3_CMPLTD_BLK_TFR_SIZE : RO; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CMPLTD_BLK_TFR_SIZE    0x003FFFFFU
+#define DMAC_CH3_CMPLTD_BLK_TFR_SIZE_M  (DMAC_CH3_CMPLTD_BLK_TFR_SIZE_V << DMAC_CH3_CMPLTD_BLK_TFR_SIZE_S)
+#define DMAC_CH3_CMPLTD_BLK_TFR_SIZE_V  0x003FFFFFU
+#define DMAC_CH3_CMPLTD_BLK_TFR_SIZE_S  0
+
+/** DMAC_CH3_STATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH3_STATUS1_REG (DR_REG_DMAC_BASE + 0x334)
+/** DMAC_CH3_DATA_LEFT_IN_FIFO : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DATA_LEFT_IN_FIFO    0x00007FFFU
+#define DMAC_CH3_DATA_LEFT_IN_FIFO_M  (DMAC_CH3_DATA_LEFT_IN_FIFO_V << DMAC_CH3_DATA_LEFT_IN_FIFO_S)
+#define DMAC_CH3_DATA_LEFT_IN_FIFO_V  0x00007FFFU
+#define DMAC_CH3_DATA_LEFT_IN_FIFO_S  0
+
+/** DMAC_CH3_SWHSSRC0_REG register
+ *  NA
+ */
+#define DMAC_CH3_SWHSSRC0_REG (DR_REG_DMAC_BASE + 0x338)
+/** DMAC_CH3_SWHS_REQ_SRC : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_REQ_SRC    (BIT(0))
+#define DMAC_CH3_SWHS_REQ_SRC_M  (DMAC_CH3_SWHS_REQ_SRC_V << DMAC_CH3_SWHS_REQ_SRC_S)
+#define DMAC_CH3_SWHS_REQ_SRC_V  0x00000001U
+#define DMAC_CH3_SWHS_REQ_SRC_S  0
+/** DMAC_CH3_SWHS_REQ_SRC_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_REQ_SRC_WE    (BIT(1))
+#define DMAC_CH3_SWHS_REQ_SRC_WE_M  (DMAC_CH3_SWHS_REQ_SRC_WE_V << DMAC_CH3_SWHS_REQ_SRC_WE_S)
+#define DMAC_CH3_SWHS_REQ_SRC_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_REQ_SRC_WE_S  1
+/** DMAC_CH3_SWHS_SGLREQ_SRC : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_SGLREQ_SRC    (BIT(2))
+#define DMAC_CH3_SWHS_SGLREQ_SRC_M  (DMAC_CH3_SWHS_SGLREQ_SRC_V << DMAC_CH3_SWHS_SGLREQ_SRC_S)
+#define DMAC_CH3_SWHS_SGLREQ_SRC_V  0x00000001U
+#define DMAC_CH3_SWHS_SGLREQ_SRC_S  2
+/** DMAC_CH3_SWHS_SGLREQ_SRC_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_SGLREQ_SRC_WE    (BIT(3))
+#define DMAC_CH3_SWHS_SGLREQ_SRC_WE_M  (DMAC_CH3_SWHS_SGLREQ_SRC_WE_V << DMAC_CH3_SWHS_SGLREQ_SRC_WE_S)
+#define DMAC_CH3_SWHS_SGLREQ_SRC_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_SGLREQ_SRC_WE_S  3
+/** DMAC_CH3_SWHS_LST_SRC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_LST_SRC    (BIT(4))
+#define DMAC_CH3_SWHS_LST_SRC_M  (DMAC_CH3_SWHS_LST_SRC_V << DMAC_CH3_SWHS_LST_SRC_S)
+#define DMAC_CH3_SWHS_LST_SRC_V  0x00000001U
+#define DMAC_CH3_SWHS_LST_SRC_S  4
+/** DMAC_CH3_SWHS_LST_SRC_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_LST_SRC_WE    (BIT(5))
+#define DMAC_CH3_SWHS_LST_SRC_WE_M  (DMAC_CH3_SWHS_LST_SRC_WE_V << DMAC_CH3_SWHS_LST_SRC_WE_S)
+#define DMAC_CH3_SWHS_LST_SRC_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_LST_SRC_WE_S  5
+
+/** DMAC_CH3_SWHSDST0_REG register
+ *  NA
+ */
+#define DMAC_CH3_SWHSDST0_REG (DR_REG_DMAC_BASE + 0x340)
+/** DMAC_CH3_SWHS_REQ_DST : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_REQ_DST    (BIT(0))
+#define DMAC_CH3_SWHS_REQ_DST_M  (DMAC_CH3_SWHS_REQ_DST_V << DMAC_CH3_SWHS_REQ_DST_S)
+#define DMAC_CH3_SWHS_REQ_DST_V  0x00000001U
+#define DMAC_CH3_SWHS_REQ_DST_S  0
+/** DMAC_CH3_SWHS_REQ_DST_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_REQ_DST_WE    (BIT(1))
+#define DMAC_CH3_SWHS_REQ_DST_WE_M  (DMAC_CH3_SWHS_REQ_DST_WE_V << DMAC_CH3_SWHS_REQ_DST_WE_S)
+#define DMAC_CH3_SWHS_REQ_DST_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_REQ_DST_WE_S  1
+/** DMAC_CH3_SWHS_SGLREQ_DST : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_SGLREQ_DST    (BIT(2))
+#define DMAC_CH3_SWHS_SGLREQ_DST_M  (DMAC_CH3_SWHS_SGLREQ_DST_V << DMAC_CH3_SWHS_SGLREQ_DST_S)
+#define DMAC_CH3_SWHS_SGLREQ_DST_V  0x00000001U
+#define DMAC_CH3_SWHS_SGLREQ_DST_S  2
+/** DMAC_CH3_SWHS_SGLREQ_DST_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_SGLREQ_DST_WE    (BIT(3))
+#define DMAC_CH3_SWHS_SGLREQ_DST_WE_M  (DMAC_CH3_SWHS_SGLREQ_DST_WE_V << DMAC_CH3_SWHS_SGLREQ_DST_WE_S)
+#define DMAC_CH3_SWHS_SGLREQ_DST_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_SGLREQ_DST_WE_S  3
+/** DMAC_CH3_SWHS_LST_DST : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_LST_DST    (BIT(4))
+#define DMAC_CH3_SWHS_LST_DST_M  (DMAC_CH3_SWHS_LST_DST_V << DMAC_CH3_SWHS_LST_DST_S)
+#define DMAC_CH3_SWHS_LST_DST_V  0x00000001U
+#define DMAC_CH3_SWHS_LST_DST_S  4
+/** DMAC_CH3_SWHS_LST_DST_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_LST_DST_WE    (BIT(5))
+#define DMAC_CH3_SWHS_LST_DST_WE_M  (DMAC_CH3_SWHS_LST_DST_WE_V << DMAC_CH3_SWHS_LST_DST_WE_S)
+#define DMAC_CH3_SWHS_LST_DST_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_LST_DST_WE_S  5
+
+/** DMAC_CH3_BLK_TFR_RESUMEREQ0_REG register
+ *  NA
+ */
+#define DMAC_CH3_BLK_TFR_RESUMEREQ0_REG (DR_REG_DMAC_BASE + 0x348)
+/** DMAC_CH3_BLK_TFR_RESUMEREQ : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_BLK_TFR_RESUMEREQ    (BIT(0))
+#define DMAC_CH3_BLK_TFR_RESUMEREQ_M  (DMAC_CH3_BLK_TFR_RESUMEREQ_V << DMAC_CH3_BLK_TFR_RESUMEREQ_S)
+#define DMAC_CH3_BLK_TFR_RESUMEREQ_V  0x00000001U
+#define DMAC_CH3_BLK_TFR_RESUMEREQ_S  0
+
+/** DMAC_CH3_AXI_ID0_REG register
+ *  NA
+ */
+#define DMAC_CH3_AXI_ID0_REG (DR_REG_DMAC_BASE + 0x350)
+/** DMAC_CH3_AXI_READ_ID_SUFFIX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AXI_READ_ID_SUFFIX    (BIT(0))
+#define DMAC_CH3_AXI_READ_ID_SUFFIX_M  (DMAC_CH3_AXI_READ_ID_SUFFIX_V << DMAC_CH3_AXI_READ_ID_SUFFIX_S)
+#define DMAC_CH3_AXI_READ_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH3_AXI_READ_ID_SUFFIX_S  0
+/** DMAC_CH3_AXI_WRITE_ID_SUFFIX : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AXI_WRITE_ID_SUFFIX    (BIT(16))
+#define DMAC_CH3_AXI_WRITE_ID_SUFFIX_M  (DMAC_CH3_AXI_WRITE_ID_SUFFIX_V << DMAC_CH3_AXI_WRITE_ID_SUFFIX_S)
+#define DMAC_CH3_AXI_WRITE_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH3_AXI_WRITE_ID_SUFFIX_S  16
+
+/** DMAC_CH3_AXI_QOS0_REG register
+ *  NA
+ */
+#define DMAC_CH3_AXI_QOS0_REG (DR_REG_DMAC_BASE + 0x358)
+/** DMAC_CH3_AXI_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AXI_AWQOS    0x0000000FU
+#define DMAC_CH3_AXI_AWQOS_M  (DMAC_CH3_AXI_AWQOS_V << DMAC_CH3_AXI_AWQOS_S)
+#define DMAC_CH3_AXI_AWQOS_V  0x0000000FU
+#define DMAC_CH3_AXI_AWQOS_S  0
+/** DMAC_CH3_AXI_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AXI_ARQOS    0x0000000FU
+#define DMAC_CH3_AXI_ARQOS_M  (DMAC_CH3_AXI_ARQOS_V << DMAC_CH3_AXI_ARQOS_S)
+#define DMAC_CH3_AXI_ARQOS_V  0x0000000FU
+#define DMAC_CH3_AXI_ARQOS_S  4
+
+/** DMAC_CH3_SSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH3_SSTAT0_REG (DR_REG_DMAC_BASE + 0x360)
+/** DMAC_CH3_SSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SSTAT    0xFFFFFFFFU
+#define DMAC_CH3_SSTAT_M  (DMAC_CH3_SSTAT_V << DMAC_CH3_SSTAT_S)
+#define DMAC_CH3_SSTAT_V  0xFFFFFFFFU
+#define DMAC_CH3_SSTAT_S  0
+
+/** DMAC_CH3_DSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH3_DSTAT0_REG (DR_REG_DMAC_BASE + 0x368)
+/** DMAC_CH3_DSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DSTAT    0xFFFFFFFFU
+#define DMAC_CH3_DSTAT_M  (DMAC_CH3_DSTAT_V << DMAC_CH3_DSTAT_S)
+#define DMAC_CH3_DSTAT_V  0xFFFFFFFFU
+#define DMAC_CH3_DSTAT_S  0
+
+/** DMAC_CH3_SSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH3_SSTATAR0_REG (DR_REG_DMAC_BASE + 0x370)
+/** DMAC_CH3_SSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SSTATAR0    0xFFFFFFFFU
+#define DMAC_CH3_SSTATAR0_M  (DMAC_CH3_SSTATAR0_V << DMAC_CH3_SSTATAR0_S)
+#define DMAC_CH3_SSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH3_SSTATAR0_S  0
+
+/** DMAC_CH3_SSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH3_SSTATAR1_REG (DR_REG_DMAC_BASE + 0x374)
+/** DMAC_CH3_SSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SSTATAR1    0xFFFFFFFFU
+#define DMAC_CH3_SSTATAR1_M  (DMAC_CH3_SSTATAR1_V << DMAC_CH3_SSTATAR1_S)
+#define DMAC_CH3_SSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH3_SSTATAR1_S  0
+
+/** DMAC_CH3_DSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH3_DSTATAR0_REG (DR_REG_DMAC_BASE + 0x378)
+/** DMAC_CH3_DSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DSTATAR0    0xFFFFFFFFU
+#define DMAC_CH3_DSTATAR0_M  (DMAC_CH3_DSTATAR0_V << DMAC_CH3_DSTATAR0_S)
+#define DMAC_CH3_DSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH3_DSTATAR0_S  0
+
+/** DMAC_CH3_DSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH3_DSTATAR1_REG (DR_REG_DMAC_BASE + 0x37c)
+/** DMAC_CH3_DSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DSTATAR1    0xFFFFFFFFU
+#define DMAC_CH3_DSTATAR1_M  (DMAC_CH3_DSTATAR1_V << DMAC_CH3_DSTATAR1_S)
+#define DMAC_CH3_DSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH3_DSTATAR1_S  0
+
+/** DMAC_CH3_INTSTATUS_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSTATUS_ENABLE0_REG (DR_REG_DMAC_BASE + 0x380)
+/** DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_V << DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_V << DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT_V << DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT_V << DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : R/W; bitpos: [13]; default:
+ *  1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT_M  (DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT_V << DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT_M  (DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT_V << DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT_M  (DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT_V << DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH3_INTSTATUS_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSTATUS_ENABLE1_REG (DR_REG_DMAC_BASE + 0x384)
+/** DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH3_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x388)
+/** DMAC_CH3_BLOCK_TFR_DONE_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH3_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH3_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH3_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH3_DMA_TFR_DONE_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH3_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH3_DMA_TFR_DONE_INTSTAT_V << DMAC_CH3_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH3_SRC_TRANSCOMP_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH3_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH3_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH3_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH3_DST_TRANSCOMP_INTSTAT : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH3_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH3_DST_TRANSCOMP_INTSTAT_V << DMAC_CH3_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH3_SRC_DEC_ERR_INTSTAT : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH3_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH3_SRC_DEC_ERR_INTSTAT_V << DMAC_CH3_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH3_DST_DEC_ERR_INTSTAT : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH3_DST_DEC_ERR_INTSTAT_M  (DMAC_CH3_DST_DEC_ERR_INTSTAT_V << DMAC_CH3_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH3_SRC_SLV_ERR_INTSTAT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH3_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH3_SRC_SLV_ERR_INTSTAT_V << DMAC_CH3_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH3_DST_SLV_ERR_INTSTAT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH3_DST_SLV_ERR_INTSTAT_M  (DMAC_CH3_DST_SLV_ERR_INTSTAT_V << DMAC_CH3_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH3_SLVIF_DEC_ERR_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH3_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH3_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH3_CH_LOCK_CLEARED_INTSTAT : RO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH3_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH3_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH3_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH3_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT : RO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH3_CH_SUSPENDED_INTSTAT : RO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH3_CH_SUSPENDED_INTSTAT_M  (DMAC_CH3_CH_SUSPENDED_INTSTAT_V << DMAC_CH3_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH3_CH_DISABLED_INTSTAT : RO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH3_CH_DISABLED_INTSTAT_M  (DMAC_CH3_CH_DISABLED_INTSTAT_V << DMAC_CH3_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH3_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH3_CH_ABORTED_INTSTAT : RO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH3_CH_ABORTED_INTSTAT_M  (DMAC_CH3_CH_ABORTED_INTSTAT_V << DMAC_CH3_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH3_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH3_INTSTATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSTATUS1_REG (DR_REG_DMAC_BASE + 0x38c)
+/** DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH3_INTSIGNAL_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSIGNAL_ENABLE0_REG (DR_REG_DMAC_BASE + 0x390)
+/** DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL    (BIT(0))
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_M  (DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V << DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S  0
+/** DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL    (BIT(1))
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_M  (DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_V << DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_S  1
+/** DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL    (BIT(3))
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_M  (DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V << DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S  3
+/** DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL    (BIT(4))
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_M  (DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_V << DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_S  4
+/** DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL    (BIT(5))
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_S  5
+/** DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL    (BIT(6))
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_S  6
+/** DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL    (BIT(7))
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_S  7
+/** DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL    (BIT(8))
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_S  8
+/** DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL    (BIT(9))
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S  9
+/** DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL    (BIT(10))
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S  10
+/** DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL    (BIT(11))
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S  11
+/** DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL    (BIT(12))
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S  12
+/** DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL : R/W; bitpos: [13];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL    (BIT(13))
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S  13
+/** DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL    (BIT(14))
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S  14
+/** DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL    (BIT(16))
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S  16
+/** DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL    (BIT(17))
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S  17
+/** DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL    (BIT(18))
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S  18
+/** DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL    (BIT(19))
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S  19
+/** DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL    (BIT(20))
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S  20
+/** DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL    (BIT(21))
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S  21
+/** DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL    (BIT(25))
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S  25
+/** DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL    (BIT(27))
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_M  (DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V << DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S  27
+/** DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL    (BIT(28))
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_M  (DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V << DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S  28
+/** DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL    (BIT(29))
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_M  (DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_V << DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_S  29
+/** DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL    (BIT(30))
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL_M  (DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL_V << DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL_S  30
+/** DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL    (BIT(31))
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL_M  (DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL_V << DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL_S  31
+
+/** DMAC_CH3_INTSIGNAL_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSIGNAL_ENABLE1_REG (DR_REG_DMAC_BASE + 0x394)
+/** DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL    (BIT(0))
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V << DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S  0
+/** DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL    (BIT(1))
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S  1
+/** DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL    (BIT(2))
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V << DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S  2
+/** DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL    (BIT(3))
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S  3
+
+/** DMAC_CH3_INTCLEAR0_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTCLEAR0_REG (DR_REG_DMAC_BASE + 0x398)
+/** DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_V << DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT : WO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_V << DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT : WO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT_V << DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT : WO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT_V << DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : WO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : WO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT : WO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT : WO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT : WO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT : WO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : WO; bitpos: [20]; default:
+ *  0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT : WO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT : WO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT : WO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT : WO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT : WO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT_M  (DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT_V << DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT : WO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT_M  (DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT_V << DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT : WO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT_M  (DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT_V << DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH3_INTCLEAR1_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTCLEAR1_REG (DR_REG_DMAC_BASE + 0x39c)
+/** DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT : WO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH4_SAR0_REG register
+ *  NA
+ */
+#define DMAC_CH4_SAR0_REG (DR_REG_DMAC_BASE + 0x400)
+/** DMAC_CH4_SAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SAR0    0xFFFFFFFFU
+#define DMAC_CH4_SAR0_M  (DMAC_CH4_SAR0_V << DMAC_CH4_SAR0_S)
+#define DMAC_CH4_SAR0_V  0xFFFFFFFFU
+#define DMAC_CH4_SAR0_S  0
+
+/** DMAC_CH4_SAR1_REG register
+ *  NA
+ */
+#define DMAC_CH4_SAR1_REG (DR_REG_DMAC_BASE + 0x404)
+/** DMAC_CH4_SAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SAR1    0xFFFFFFFFU
+#define DMAC_CH4_SAR1_M  (DMAC_CH4_SAR1_V << DMAC_CH4_SAR1_S)
+#define DMAC_CH4_SAR1_V  0xFFFFFFFFU
+#define DMAC_CH4_SAR1_S  0
+
+/** DMAC_CH4_DAR0_REG register
+ *  NA
+ */
+#define DMAC_CH4_DAR0_REG (DR_REG_DMAC_BASE + 0x408)
+/** DMAC_CH4_DAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DAR0    0xFFFFFFFFU
+#define DMAC_CH4_DAR0_M  (DMAC_CH4_DAR0_V << DMAC_CH4_DAR0_S)
+#define DMAC_CH4_DAR0_V  0xFFFFFFFFU
+#define DMAC_CH4_DAR0_S  0
+
+/** DMAC_CH4_DAR1_REG register
+ *  NA
+ */
+#define DMAC_CH4_DAR1_REG (DR_REG_DMAC_BASE + 0x40c)
+/** DMAC_CH4_DAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DAR1    0xFFFFFFFFU
+#define DMAC_CH4_DAR1_M  (DMAC_CH4_DAR1_V << DMAC_CH4_DAR1_S)
+#define DMAC_CH4_DAR1_V  0xFFFFFFFFU
+#define DMAC_CH4_DAR1_S  0
+
+/** DMAC_CH4_BLOCK_TS0_REG register
+ *  NA
+ */
+#define DMAC_CH4_BLOCK_TS0_REG (DR_REG_DMAC_BASE + 0x410)
+/** DMAC_CH4_BLOCK_TS : R/W; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_BLOCK_TS    0x003FFFFFU
+#define DMAC_CH4_BLOCK_TS_M  (DMAC_CH4_BLOCK_TS_V << DMAC_CH4_BLOCK_TS_S)
+#define DMAC_CH4_BLOCK_TS_V  0x003FFFFFU
+#define DMAC_CH4_BLOCK_TS_S  0
+
+/** DMAC_CH4_CTL0_REG register
+ *  NA
+ */
+#define DMAC_CH4_CTL0_REG (DR_REG_DMAC_BASE + 0x418)
+/** DMAC_CH4_SMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SMS    (BIT(0))
+#define DMAC_CH4_SMS_M  (DMAC_CH4_SMS_V << DMAC_CH4_SMS_S)
+#define DMAC_CH4_SMS_V  0x00000001U
+#define DMAC_CH4_SMS_S  0
+/** DMAC_CH4_DMS : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DMS    (BIT(2))
+#define DMAC_CH4_DMS_M  (DMAC_CH4_DMS_V << DMAC_CH4_DMS_S)
+#define DMAC_CH4_DMS_V  0x00000001U
+#define DMAC_CH4_DMS_S  2
+/** DMAC_CH4_SINC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SINC    (BIT(4))
+#define DMAC_CH4_SINC_M  (DMAC_CH4_SINC_V << DMAC_CH4_SINC_S)
+#define DMAC_CH4_SINC_V  0x00000001U
+#define DMAC_CH4_SINC_S  4
+/** DMAC_CH4_DINC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DINC    (BIT(6))
+#define DMAC_CH4_DINC_M  (DMAC_CH4_DINC_V << DMAC_CH4_DINC_S)
+#define DMAC_CH4_DINC_V  0x00000001U
+#define DMAC_CH4_DINC_S  6
+/** DMAC_CH4_SRC_TR_WIDTH : R/W; bitpos: [10:8]; default: 2;
+ *  NA
+ */
+#define DMAC_CH4_SRC_TR_WIDTH    0x00000007U
+#define DMAC_CH4_SRC_TR_WIDTH_M  (DMAC_CH4_SRC_TR_WIDTH_V << DMAC_CH4_SRC_TR_WIDTH_S)
+#define DMAC_CH4_SRC_TR_WIDTH_V  0x00000007U
+#define DMAC_CH4_SRC_TR_WIDTH_S  8
+/** DMAC_CH4_DST_TR_WIDTH : R/W; bitpos: [13:11]; default: 2;
+ *  NA
+ */
+#define DMAC_CH4_DST_TR_WIDTH    0x00000007U
+#define DMAC_CH4_DST_TR_WIDTH_M  (DMAC_CH4_DST_TR_WIDTH_V << DMAC_CH4_DST_TR_WIDTH_S)
+#define DMAC_CH4_DST_TR_WIDTH_V  0x00000007U
+#define DMAC_CH4_DST_TR_WIDTH_S  11
+/** DMAC_CH4_SRC_MSIZE : R/W; bitpos: [17:14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_MSIZE    0x0000000FU
+#define DMAC_CH4_SRC_MSIZE_M  (DMAC_CH4_SRC_MSIZE_V << DMAC_CH4_SRC_MSIZE_S)
+#define DMAC_CH4_SRC_MSIZE_V  0x0000000FU
+#define DMAC_CH4_SRC_MSIZE_S  14
+/** DMAC_CH4_DST_MSIZE : R/W; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_MSIZE    0x0000000FU
+#define DMAC_CH4_DST_MSIZE_M  (DMAC_CH4_DST_MSIZE_V << DMAC_CH4_DST_MSIZE_S)
+#define DMAC_CH4_DST_MSIZE_V  0x0000000FU
+#define DMAC_CH4_DST_MSIZE_S  18
+/** DMAC_CH4_AR_CACHE : R/W; bitpos: [25:22]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AR_CACHE    0x0000000FU
+#define DMAC_CH4_AR_CACHE_M  (DMAC_CH4_AR_CACHE_V << DMAC_CH4_AR_CACHE_S)
+#define DMAC_CH4_AR_CACHE_V  0x0000000FU
+#define DMAC_CH4_AR_CACHE_S  22
+/** DMAC_CH4_AW_CACHE : R/W; bitpos: [29:26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AW_CACHE    0x0000000FU
+#define DMAC_CH4_AW_CACHE_M  (DMAC_CH4_AW_CACHE_V << DMAC_CH4_AW_CACHE_S)
+#define DMAC_CH4_AW_CACHE_V  0x0000000FU
+#define DMAC_CH4_AW_CACHE_S  26
+/** DMAC_CH4_NONPOSTED_LASTWRITE_EN : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_NONPOSTED_LASTWRITE_EN    (BIT(30))
+#define DMAC_CH4_NONPOSTED_LASTWRITE_EN_M  (DMAC_CH4_NONPOSTED_LASTWRITE_EN_V << DMAC_CH4_NONPOSTED_LASTWRITE_EN_S)
+#define DMAC_CH4_NONPOSTED_LASTWRITE_EN_V  0x00000001U
+#define DMAC_CH4_NONPOSTED_LASTWRITE_EN_S  30
+
+/** DMAC_CH4_CTL1_REG register
+ *  NA
+ */
+#define DMAC_CH4_CTL1_REG (DR_REG_DMAC_BASE + 0x41c)
+/** DMAC_CH4_AR_PROT : R/W; bitpos: [2:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AR_PROT    0x00000007U
+#define DMAC_CH4_AR_PROT_M  (DMAC_CH4_AR_PROT_V << DMAC_CH4_AR_PROT_S)
+#define DMAC_CH4_AR_PROT_V  0x00000007U
+#define DMAC_CH4_AR_PROT_S  0
+/** DMAC_CH4_AW_PROT : R/W; bitpos: [5:3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AW_PROT    0x00000007U
+#define DMAC_CH4_AW_PROT_M  (DMAC_CH4_AW_PROT_V << DMAC_CH4_AW_PROT_S)
+#define DMAC_CH4_AW_PROT_V  0x00000007U
+#define DMAC_CH4_AW_PROT_S  3
+/** DMAC_CH4_ARLEN_EN : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ARLEN_EN    (BIT(6))
+#define DMAC_CH4_ARLEN_EN_M  (DMAC_CH4_ARLEN_EN_V << DMAC_CH4_ARLEN_EN_S)
+#define DMAC_CH4_ARLEN_EN_V  0x00000001U
+#define DMAC_CH4_ARLEN_EN_S  6
+/** DMAC_CH4_ARLEN : R/W; bitpos: [14:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ARLEN    0x000000FFU
+#define DMAC_CH4_ARLEN_M  (DMAC_CH4_ARLEN_V << DMAC_CH4_ARLEN_S)
+#define DMAC_CH4_ARLEN_V  0x000000FFU
+#define DMAC_CH4_ARLEN_S  7
+/** DMAC_CH4_AWLEN_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AWLEN_EN    (BIT(15))
+#define DMAC_CH4_AWLEN_EN_M  (DMAC_CH4_AWLEN_EN_V << DMAC_CH4_AWLEN_EN_S)
+#define DMAC_CH4_AWLEN_EN_V  0x00000001U
+#define DMAC_CH4_AWLEN_EN_S  15
+/** DMAC_CH4_AWLEN : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AWLEN    0x000000FFU
+#define DMAC_CH4_AWLEN_M  (DMAC_CH4_AWLEN_V << DMAC_CH4_AWLEN_S)
+#define DMAC_CH4_AWLEN_V  0x000000FFU
+#define DMAC_CH4_AWLEN_S  16
+/** DMAC_CH4_SRC_STAT_EN : R/W; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_STAT_EN    (BIT(24))
+#define DMAC_CH4_SRC_STAT_EN_M  (DMAC_CH4_SRC_STAT_EN_V << DMAC_CH4_SRC_STAT_EN_S)
+#define DMAC_CH4_SRC_STAT_EN_V  0x00000001U
+#define DMAC_CH4_SRC_STAT_EN_S  24
+/** DMAC_CH4_DST_STAT_EN : R/W; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_STAT_EN    (BIT(25))
+#define DMAC_CH4_DST_STAT_EN_M  (DMAC_CH4_DST_STAT_EN_V << DMAC_CH4_DST_STAT_EN_S)
+#define DMAC_CH4_DST_STAT_EN_V  0x00000001U
+#define DMAC_CH4_DST_STAT_EN_S  25
+/** DMAC_CH4_IOC_BLKTFR : R/W; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_IOC_BLKTFR    (BIT(26))
+#define DMAC_CH4_IOC_BLKTFR_M  (DMAC_CH4_IOC_BLKTFR_V << DMAC_CH4_IOC_BLKTFR_S)
+#define DMAC_CH4_IOC_BLKTFR_V  0x00000001U
+#define DMAC_CH4_IOC_BLKTFR_S  26
+/** DMAC_CH4_SHADOWREG_OR_LLI_LAST : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SHADOWREG_OR_LLI_LAST    (BIT(30))
+#define DMAC_CH4_SHADOWREG_OR_LLI_LAST_M  (DMAC_CH4_SHADOWREG_OR_LLI_LAST_V << DMAC_CH4_SHADOWREG_OR_LLI_LAST_S)
+#define DMAC_CH4_SHADOWREG_OR_LLI_LAST_V  0x00000001U
+#define DMAC_CH4_SHADOWREG_OR_LLI_LAST_S  30
+/** DMAC_CH4_SHADOWREG_OR_LLI_VALID : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SHADOWREG_OR_LLI_VALID    (BIT(31))
+#define DMAC_CH4_SHADOWREG_OR_LLI_VALID_M  (DMAC_CH4_SHADOWREG_OR_LLI_VALID_V << DMAC_CH4_SHADOWREG_OR_LLI_VALID_S)
+#define DMAC_CH4_SHADOWREG_OR_LLI_VALID_V  0x00000001U
+#define DMAC_CH4_SHADOWREG_OR_LLI_VALID_S  31
+
+/** DMAC_CH4_CFG0_REG register
+ *  NA
+ */
+#define DMAC_CH4_CFG0_REG (DR_REG_DMAC_BASE + 0x420)
+/** DMAC_CH4_SRC_MULTBLK_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH4_SRC_MULTBLK_TYPE_M  (DMAC_CH4_SRC_MULTBLK_TYPE_V << DMAC_CH4_SRC_MULTBLK_TYPE_S)
+#define DMAC_CH4_SRC_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH4_SRC_MULTBLK_TYPE_S  0
+/** DMAC_CH4_DST_MULTBLK_TYPE : R/W; bitpos: [3:2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH4_DST_MULTBLK_TYPE_M  (DMAC_CH4_DST_MULTBLK_TYPE_V << DMAC_CH4_DST_MULTBLK_TYPE_S)
+#define DMAC_CH4_DST_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH4_DST_MULTBLK_TYPE_S  2
+/** DMAC_CH4_RD_UID : RO; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_RD_UID    0x0000000FU
+#define DMAC_CH4_RD_UID_M  (DMAC_CH4_RD_UID_V << DMAC_CH4_RD_UID_S)
+#define DMAC_CH4_RD_UID_V  0x0000000FU
+#define DMAC_CH4_RD_UID_S  18
+/** DMAC_CH4_WR_UID : RO; bitpos: [28:25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_WR_UID    0x0000000FU
+#define DMAC_CH4_WR_UID_M  (DMAC_CH4_WR_UID_V << DMAC_CH4_WR_UID_S)
+#define DMAC_CH4_WR_UID_V  0x0000000FU
+#define DMAC_CH4_WR_UID_S  25
+
+/** DMAC_CH4_CFG1_REG register
+ *  NA
+ */
+#define DMAC_CH4_CFG1_REG (DR_REG_DMAC_BASE + 0x424)
+/** DMAC_CH4_TT_FC : R/W; bitpos: [2:0]; default: 3;
+ *  NA
+ */
+#define DMAC_CH4_TT_FC    0x00000007U
+#define DMAC_CH4_TT_FC_M  (DMAC_CH4_TT_FC_V << DMAC_CH4_TT_FC_S)
+#define DMAC_CH4_TT_FC_V  0x00000007U
+#define DMAC_CH4_TT_FC_S  0
+/** DMAC_CH4_HS_SEL_SRC : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_HS_SEL_SRC    (BIT(3))
+#define DMAC_CH4_HS_SEL_SRC_M  (DMAC_CH4_HS_SEL_SRC_V << DMAC_CH4_HS_SEL_SRC_S)
+#define DMAC_CH4_HS_SEL_SRC_V  0x00000001U
+#define DMAC_CH4_HS_SEL_SRC_S  3
+/** DMAC_CH4_HS_SEL_DST : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_HS_SEL_DST    (BIT(4))
+#define DMAC_CH4_HS_SEL_DST_M  (DMAC_CH4_HS_SEL_DST_V << DMAC_CH4_HS_SEL_DST_S)
+#define DMAC_CH4_HS_SEL_DST_V  0x00000001U
+#define DMAC_CH4_HS_SEL_DST_S  4
+/** DMAC_CH4_SRC_HWHS_POL : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_HWHS_POL    (BIT(5))
+#define DMAC_CH4_SRC_HWHS_POL_M  (DMAC_CH4_SRC_HWHS_POL_V << DMAC_CH4_SRC_HWHS_POL_S)
+#define DMAC_CH4_SRC_HWHS_POL_V  0x00000001U
+#define DMAC_CH4_SRC_HWHS_POL_S  5
+/** DMAC_CH4_DST_HWHS_POL : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_HWHS_POL    (BIT(6))
+#define DMAC_CH4_DST_HWHS_POL_M  (DMAC_CH4_DST_HWHS_POL_V << DMAC_CH4_DST_HWHS_POL_S)
+#define DMAC_CH4_DST_HWHS_POL_V  0x00000001U
+#define DMAC_CH4_DST_HWHS_POL_S  6
+/** DMAC_CH4_SRC_PER : R/W; bitpos: [8:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_PER    0x00000003U
+#define DMAC_CH4_SRC_PER_M  (DMAC_CH4_SRC_PER_V << DMAC_CH4_SRC_PER_S)
+#define DMAC_CH4_SRC_PER_V  0x00000003U
+#define DMAC_CH4_SRC_PER_S  7
+/** DMAC_CH4_DST_PER : R/W; bitpos: [13:12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_PER    0x00000003U
+#define DMAC_CH4_DST_PER_M  (DMAC_CH4_DST_PER_V << DMAC_CH4_DST_PER_S)
+#define DMAC_CH4_DST_PER_V  0x00000003U
+#define DMAC_CH4_DST_PER_S  12
+/** DMAC_CH4_CH_PRIOR : R/W; bitpos: [19:17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_PRIOR    0x00000007U
+#define DMAC_CH4_CH_PRIOR_M  (DMAC_CH4_CH_PRIOR_V << DMAC_CH4_CH_PRIOR_S)
+#define DMAC_CH4_CH_PRIOR_V  0x00000007U
+#define DMAC_CH4_CH_PRIOR_S  17
+/** DMAC_CH4_LOCK_CH : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LOCK_CH    (BIT(20))
+#define DMAC_CH4_LOCK_CH_M  (DMAC_CH4_LOCK_CH_V << DMAC_CH4_LOCK_CH_S)
+#define DMAC_CH4_LOCK_CH_V  0x00000001U
+#define DMAC_CH4_LOCK_CH_S  20
+/** DMAC_CH4_LOCK_CH_L : RO; bitpos: [22:21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LOCK_CH_L    0x00000003U
+#define DMAC_CH4_LOCK_CH_L_M  (DMAC_CH4_LOCK_CH_L_V << DMAC_CH4_LOCK_CH_L_S)
+#define DMAC_CH4_LOCK_CH_L_V  0x00000003U
+#define DMAC_CH4_LOCK_CH_L_S  21
+/** DMAC_CH4_SRC_OSR_LMT : R/W; bitpos: [26:23]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_OSR_LMT    0x0000000FU
+#define DMAC_CH4_SRC_OSR_LMT_M  (DMAC_CH4_SRC_OSR_LMT_V << DMAC_CH4_SRC_OSR_LMT_S)
+#define DMAC_CH4_SRC_OSR_LMT_V  0x0000000FU
+#define DMAC_CH4_SRC_OSR_LMT_S  23
+/** DMAC_CH4_DST_OSR_LMT : R/W; bitpos: [30:27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_OSR_LMT    0x0000000FU
+#define DMAC_CH4_DST_OSR_LMT_M  (DMAC_CH4_DST_OSR_LMT_V << DMAC_CH4_DST_OSR_LMT_S)
+#define DMAC_CH4_DST_OSR_LMT_V  0x0000000FU
+#define DMAC_CH4_DST_OSR_LMT_S  27
+
+/** DMAC_CH4_LLP0_REG register
+ *  NA
+ */
+#define DMAC_CH4_LLP0_REG (DR_REG_DMAC_BASE + 0x428)
+/** DMAC_CH4_LMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LMS    (BIT(0))
+#define DMAC_CH4_LMS_M  (DMAC_CH4_LMS_V << DMAC_CH4_LMS_S)
+#define DMAC_CH4_LMS_V  0x00000001U
+#define DMAC_CH4_LMS_S  0
+/** DMAC_CH4_LOC0 : R/W; bitpos: [31:6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LOC0    0x03FFFFFFU
+#define DMAC_CH4_LOC0_M  (DMAC_CH4_LOC0_V << DMAC_CH4_LOC0_S)
+#define DMAC_CH4_LOC0_V  0x03FFFFFFU
+#define DMAC_CH4_LOC0_S  6
+
+/** DMAC_CH4_LLP1_REG register
+ *  NA
+ */
+#define DMAC_CH4_LLP1_REG (DR_REG_DMAC_BASE + 0x42c)
+/** DMAC_CH4_LOC1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LOC1    0xFFFFFFFFU
+#define DMAC_CH4_LOC1_M  (DMAC_CH4_LOC1_V << DMAC_CH4_LOC1_S)
+#define DMAC_CH4_LOC1_V  0xFFFFFFFFU
+#define DMAC_CH4_LOC1_S  0
+
+/** DMAC_CH4_STATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH4_STATUS0_REG (DR_REG_DMAC_BASE + 0x430)
+/** DMAC_CH4_CMPLTD_BLK_TFR_SIZE : RO; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CMPLTD_BLK_TFR_SIZE    0x003FFFFFU
+#define DMAC_CH4_CMPLTD_BLK_TFR_SIZE_M  (DMAC_CH4_CMPLTD_BLK_TFR_SIZE_V << DMAC_CH4_CMPLTD_BLK_TFR_SIZE_S)
+#define DMAC_CH4_CMPLTD_BLK_TFR_SIZE_V  0x003FFFFFU
+#define DMAC_CH4_CMPLTD_BLK_TFR_SIZE_S  0
+
+/** DMAC_CH4_STATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH4_STATUS1_REG (DR_REG_DMAC_BASE + 0x434)
+/** DMAC_CH4_DATA_LEFT_IN_FIFO : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DATA_LEFT_IN_FIFO    0x00007FFFU
+#define DMAC_CH4_DATA_LEFT_IN_FIFO_M  (DMAC_CH4_DATA_LEFT_IN_FIFO_V << DMAC_CH4_DATA_LEFT_IN_FIFO_S)
+#define DMAC_CH4_DATA_LEFT_IN_FIFO_V  0x00007FFFU
+#define DMAC_CH4_DATA_LEFT_IN_FIFO_S  0
+
+/** DMAC_CH4_SWHSSRC0_REG register
+ *  NA
+ */
+#define DMAC_CH4_SWHSSRC0_REG (DR_REG_DMAC_BASE + 0x438)
+/** DMAC_CH4_SWHS_REQ_SRC : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_REQ_SRC    (BIT(0))
+#define DMAC_CH4_SWHS_REQ_SRC_M  (DMAC_CH4_SWHS_REQ_SRC_V << DMAC_CH4_SWHS_REQ_SRC_S)
+#define DMAC_CH4_SWHS_REQ_SRC_V  0x00000001U
+#define DMAC_CH4_SWHS_REQ_SRC_S  0
+/** DMAC_CH4_SWHS_REQ_SRC_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_REQ_SRC_WE    (BIT(1))
+#define DMAC_CH4_SWHS_REQ_SRC_WE_M  (DMAC_CH4_SWHS_REQ_SRC_WE_V << DMAC_CH4_SWHS_REQ_SRC_WE_S)
+#define DMAC_CH4_SWHS_REQ_SRC_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_REQ_SRC_WE_S  1
+/** DMAC_CH4_SWHS_SGLREQ_SRC : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_SGLREQ_SRC    (BIT(2))
+#define DMAC_CH4_SWHS_SGLREQ_SRC_M  (DMAC_CH4_SWHS_SGLREQ_SRC_V << DMAC_CH4_SWHS_SGLREQ_SRC_S)
+#define DMAC_CH4_SWHS_SGLREQ_SRC_V  0x00000001U
+#define DMAC_CH4_SWHS_SGLREQ_SRC_S  2
+/** DMAC_CH4_SWHS_SGLREQ_SRC_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_SGLREQ_SRC_WE    (BIT(3))
+#define DMAC_CH4_SWHS_SGLREQ_SRC_WE_M  (DMAC_CH4_SWHS_SGLREQ_SRC_WE_V << DMAC_CH4_SWHS_SGLREQ_SRC_WE_S)
+#define DMAC_CH4_SWHS_SGLREQ_SRC_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_SGLREQ_SRC_WE_S  3
+/** DMAC_CH4_SWHS_LST_SRC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_LST_SRC    (BIT(4))
+#define DMAC_CH4_SWHS_LST_SRC_M  (DMAC_CH4_SWHS_LST_SRC_V << DMAC_CH4_SWHS_LST_SRC_S)
+#define DMAC_CH4_SWHS_LST_SRC_V  0x00000001U
+#define DMAC_CH4_SWHS_LST_SRC_S  4
+/** DMAC_CH4_SWHS_LST_SRC_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_LST_SRC_WE    (BIT(5))
+#define DMAC_CH4_SWHS_LST_SRC_WE_M  (DMAC_CH4_SWHS_LST_SRC_WE_V << DMAC_CH4_SWHS_LST_SRC_WE_S)
+#define DMAC_CH4_SWHS_LST_SRC_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_LST_SRC_WE_S  5
+
+/** DMAC_CH4_SWHSDST0_REG register
+ *  NA
+ */
+#define DMAC_CH4_SWHSDST0_REG (DR_REG_DMAC_BASE + 0x440)
+/** DMAC_CH4_SWHS_REQ_DST : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_REQ_DST    (BIT(0))
+#define DMAC_CH4_SWHS_REQ_DST_M  (DMAC_CH4_SWHS_REQ_DST_V << DMAC_CH4_SWHS_REQ_DST_S)
+#define DMAC_CH4_SWHS_REQ_DST_V  0x00000001U
+#define DMAC_CH4_SWHS_REQ_DST_S  0
+/** DMAC_CH4_SWHS_REQ_DST_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_REQ_DST_WE    (BIT(1))
+#define DMAC_CH4_SWHS_REQ_DST_WE_M  (DMAC_CH4_SWHS_REQ_DST_WE_V << DMAC_CH4_SWHS_REQ_DST_WE_S)
+#define DMAC_CH4_SWHS_REQ_DST_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_REQ_DST_WE_S  1
+/** DMAC_CH4_SWHS_SGLREQ_DST : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_SGLREQ_DST    (BIT(2))
+#define DMAC_CH4_SWHS_SGLREQ_DST_M  (DMAC_CH4_SWHS_SGLREQ_DST_V << DMAC_CH4_SWHS_SGLREQ_DST_S)
+#define DMAC_CH4_SWHS_SGLREQ_DST_V  0x00000001U
+#define DMAC_CH4_SWHS_SGLREQ_DST_S  2
+/** DMAC_CH4_SWHS_SGLREQ_DST_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_SGLREQ_DST_WE    (BIT(3))
+#define DMAC_CH4_SWHS_SGLREQ_DST_WE_M  (DMAC_CH4_SWHS_SGLREQ_DST_WE_V << DMAC_CH4_SWHS_SGLREQ_DST_WE_S)
+#define DMAC_CH4_SWHS_SGLREQ_DST_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_SGLREQ_DST_WE_S  3
+/** DMAC_CH4_SWHS_LST_DST : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_LST_DST    (BIT(4))
+#define DMAC_CH4_SWHS_LST_DST_M  (DMAC_CH4_SWHS_LST_DST_V << DMAC_CH4_SWHS_LST_DST_S)
+#define DMAC_CH4_SWHS_LST_DST_V  0x00000001U
+#define DMAC_CH4_SWHS_LST_DST_S  4
+/** DMAC_CH4_SWHS_LST_DST_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_LST_DST_WE    (BIT(5))
+#define DMAC_CH4_SWHS_LST_DST_WE_M  (DMAC_CH4_SWHS_LST_DST_WE_V << DMAC_CH4_SWHS_LST_DST_WE_S)
+#define DMAC_CH4_SWHS_LST_DST_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_LST_DST_WE_S  5
+
+/** DMAC_CH4_BLK_TFR_RESUMEREQ0_REG register
+ *  NA
+ */
+#define DMAC_CH4_BLK_TFR_RESUMEREQ0_REG (DR_REG_DMAC_BASE + 0x448)
+/** DMAC_CH4_BLK_TFR_RESUMEREQ : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_BLK_TFR_RESUMEREQ    (BIT(0))
+#define DMAC_CH4_BLK_TFR_RESUMEREQ_M  (DMAC_CH4_BLK_TFR_RESUMEREQ_V << DMAC_CH4_BLK_TFR_RESUMEREQ_S)
+#define DMAC_CH4_BLK_TFR_RESUMEREQ_V  0x00000001U
+#define DMAC_CH4_BLK_TFR_RESUMEREQ_S  0
+
+/** DMAC_CH4_AXI_ID0_REG register
+ *  NA
+ */
+#define DMAC_CH4_AXI_ID0_REG (DR_REG_DMAC_BASE + 0x450)
+/** DMAC_CH4_AXI_READ_ID_SUFFIX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AXI_READ_ID_SUFFIX    (BIT(0))
+#define DMAC_CH4_AXI_READ_ID_SUFFIX_M  (DMAC_CH4_AXI_READ_ID_SUFFIX_V << DMAC_CH4_AXI_READ_ID_SUFFIX_S)
+#define DMAC_CH4_AXI_READ_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH4_AXI_READ_ID_SUFFIX_S  0
+/** DMAC_CH4_AXI_WRITE_ID_SUFFIX : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AXI_WRITE_ID_SUFFIX    (BIT(16))
+#define DMAC_CH4_AXI_WRITE_ID_SUFFIX_M  (DMAC_CH4_AXI_WRITE_ID_SUFFIX_V << DMAC_CH4_AXI_WRITE_ID_SUFFIX_S)
+#define DMAC_CH4_AXI_WRITE_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH4_AXI_WRITE_ID_SUFFIX_S  16
+
+/** DMAC_CH4_AXI_QOS0_REG register
+ *  NA
+ */
+#define DMAC_CH4_AXI_QOS0_REG (DR_REG_DMAC_BASE + 0x458)
+/** DMAC_CH4_AXI_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AXI_AWQOS    0x0000000FU
+#define DMAC_CH4_AXI_AWQOS_M  (DMAC_CH4_AXI_AWQOS_V << DMAC_CH4_AXI_AWQOS_S)
+#define DMAC_CH4_AXI_AWQOS_V  0x0000000FU
+#define DMAC_CH4_AXI_AWQOS_S  0
+/** DMAC_CH4_AXI_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AXI_ARQOS    0x0000000FU
+#define DMAC_CH4_AXI_ARQOS_M  (DMAC_CH4_AXI_ARQOS_V << DMAC_CH4_AXI_ARQOS_S)
+#define DMAC_CH4_AXI_ARQOS_V  0x0000000FU
+#define DMAC_CH4_AXI_ARQOS_S  4
+
+/** DMAC_CH4_SSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH4_SSTAT0_REG (DR_REG_DMAC_BASE + 0x460)
+/** DMAC_CH4_SSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SSTAT    0xFFFFFFFFU
+#define DMAC_CH4_SSTAT_M  (DMAC_CH4_SSTAT_V << DMAC_CH4_SSTAT_S)
+#define DMAC_CH4_SSTAT_V  0xFFFFFFFFU
+#define DMAC_CH4_SSTAT_S  0
+
+/** DMAC_CH4_DSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH4_DSTAT0_REG (DR_REG_DMAC_BASE + 0x468)
+/** DMAC_CH4_DSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DSTAT    0xFFFFFFFFU
+#define DMAC_CH4_DSTAT_M  (DMAC_CH4_DSTAT_V << DMAC_CH4_DSTAT_S)
+#define DMAC_CH4_DSTAT_V  0xFFFFFFFFU
+#define DMAC_CH4_DSTAT_S  0
+
+/** DMAC_CH4_SSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH4_SSTATAR0_REG (DR_REG_DMAC_BASE + 0x470)
+/** DMAC_CH4_SSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SSTATAR0    0xFFFFFFFFU
+#define DMAC_CH4_SSTATAR0_M  (DMAC_CH4_SSTATAR0_V << DMAC_CH4_SSTATAR0_S)
+#define DMAC_CH4_SSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH4_SSTATAR0_S  0
+
+/** DMAC_CH4_SSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH4_SSTATAR1_REG (DR_REG_DMAC_BASE + 0x474)
+/** DMAC_CH4_SSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SSTATAR1    0xFFFFFFFFU
+#define DMAC_CH4_SSTATAR1_M  (DMAC_CH4_SSTATAR1_V << DMAC_CH4_SSTATAR1_S)
+#define DMAC_CH4_SSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH4_SSTATAR1_S  0
+
+/** DMAC_CH4_DSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH4_DSTATAR0_REG (DR_REG_DMAC_BASE + 0x478)
+/** DMAC_CH4_DSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DSTATAR0    0xFFFFFFFFU
+#define DMAC_CH4_DSTATAR0_M  (DMAC_CH4_DSTATAR0_V << DMAC_CH4_DSTATAR0_S)
+#define DMAC_CH4_DSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH4_DSTATAR0_S  0
+
+/** DMAC_CH4_DSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH4_DSTATAR1_REG (DR_REG_DMAC_BASE + 0x47c)
+/** DMAC_CH4_DSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DSTATAR1    0xFFFFFFFFU
+#define DMAC_CH4_DSTATAR1_M  (DMAC_CH4_DSTATAR1_V << DMAC_CH4_DSTATAR1_S)
+#define DMAC_CH4_DSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH4_DSTATAR1_S  0
+
+/** DMAC_CH4_INTSTATUS_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSTATUS_ENABLE0_REG (DR_REG_DMAC_BASE + 0x480)
+/** DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_V << DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_V << DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT_V << DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT_V << DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : R/W; bitpos: [13]; default:
+ *  1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT_M  (DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT_V << DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT_M  (DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT_V << DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT_M  (DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT_V << DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH4_INTSTATUS_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSTATUS_ENABLE1_REG (DR_REG_DMAC_BASE + 0x484)
+/** DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH4_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x488)
+/** DMAC_CH4_BLOCK_TFR_DONE_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH4_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH4_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH4_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH4_DMA_TFR_DONE_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH4_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH4_DMA_TFR_DONE_INTSTAT_V << DMAC_CH4_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH4_SRC_TRANSCOMP_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH4_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH4_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH4_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH4_DST_TRANSCOMP_INTSTAT : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH4_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH4_DST_TRANSCOMP_INTSTAT_V << DMAC_CH4_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH4_SRC_DEC_ERR_INTSTAT : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH4_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH4_SRC_DEC_ERR_INTSTAT_V << DMAC_CH4_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH4_DST_DEC_ERR_INTSTAT : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH4_DST_DEC_ERR_INTSTAT_M  (DMAC_CH4_DST_DEC_ERR_INTSTAT_V << DMAC_CH4_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH4_SRC_SLV_ERR_INTSTAT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH4_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH4_SRC_SLV_ERR_INTSTAT_V << DMAC_CH4_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH4_DST_SLV_ERR_INTSTAT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH4_DST_SLV_ERR_INTSTAT_M  (DMAC_CH4_DST_SLV_ERR_INTSTAT_V << DMAC_CH4_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH4_SLVIF_DEC_ERR_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH4_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH4_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH4_CH_LOCK_CLEARED_INTSTAT : RO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH4_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH4_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH4_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH4_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT : RO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH4_CH_SUSPENDED_INTSTAT : RO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH4_CH_SUSPENDED_INTSTAT_M  (DMAC_CH4_CH_SUSPENDED_INTSTAT_V << DMAC_CH4_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH4_CH_DISABLED_INTSTAT : RO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH4_CH_DISABLED_INTSTAT_M  (DMAC_CH4_CH_DISABLED_INTSTAT_V << DMAC_CH4_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH4_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH4_CH_ABORTED_INTSTAT : RO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH4_CH_ABORTED_INTSTAT_M  (DMAC_CH4_CH_ABORTED_INTSTAT_V << DMAC_CH4_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH4_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH4_INTSTATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSTATUS1_REG (DR_REG_DMAC_BASE + 0x48c)
+/** DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH4_INTSIGNAL_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSIGNAL_ENABLE0_REG (DR_REG_DMAC_BASE + 0x490)
+/** DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL    (BIT(0))
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_M  (DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V << DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S  0
+/** DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL    (BIT(1))
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_M  (DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_V << DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_S  1
+/** DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL    (BIT(3))
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_M  (DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V << DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S  3
+/** DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL    (BIT(4))
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_M  (DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_V << DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_S  4
+/** DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL    (BIT(5))
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_S  5
+/** DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL    (BIT(6))
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_S  6
+/** DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL    (BIT(7))
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_S  7
+/** DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL    (BIT(8))
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_S  8
+/** DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL    (BIT(9))
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S  9
+/** DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL    (BIT(10))
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S  10
+/** DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL    (BIT(11))
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S  11
+/** DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL    (BIT(12))
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S  12
+/** DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL : R/W; bitpos: [13];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL    (BIT(13))
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S  13
+/** DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL    (BIT(14))
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S  14
+/** DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL    (BIT(16))
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S  16
+/** DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL    (BIT(17))
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S  17
+/** DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL    (BIT(18))
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S  18
+/** DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL    (BIT(19))
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S  19
+/** DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL    (BIT(20))
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S  20
+/** DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL    (BIT(21))
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S  21
+/** DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL    (BIT(25))
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S  25
+/** DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL    (BIT(27))
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_M  (DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V << DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S  27
+/** DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL    (BIT(28))
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_M  (DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V << DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S  28
+/** DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL    (BIT(29))
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_M  (DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_V << DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_S  29
+/** DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL    (BIT(30))
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL_M  (DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL_V << DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL_S  30
+/** DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL    (BIT(31))
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL_M  (DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL_V << DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL_S  31
+
+/** DMAC_CH4_INTSIGNAL_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSIGNAL_ENABLE1_REG (DR_REG_DMAC_BASE + 0x494)
+/** DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL    (BIT(0))
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V << DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S  0
+/** DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL    (BIT(1))
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S  1
+/** DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL    (BIT(2))
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V << DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S  2
+/** DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL    (BIT(3))
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S  3
+
+/** DMAC_CH4_INTCLEAR0_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTCLEAR0_REG (DR_REG_DMAC_BASE + 0x498)
+/** DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_V << DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT : WO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_V << DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT : WO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT_V << DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT : WO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT_V << DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : WO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : WO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT : WO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT : WO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT : WO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT : WO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : WO; bitpos: [20]; default:
+ *  0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT : WO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT : WO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT : WO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT : WO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT : WO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT_M  (DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT_V << DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT : WO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT_M  (DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT_V << DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT : WO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT_M  (DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT_V << DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH4_INTCLEAR1_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTCLEAR1_REG (DR_REG_DMAC_BASE + 0x49c)
+/** DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT : WO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_struct.h
new file mode 100644
index 0000000000..a751e25fc7
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_struct.h
@@ -0,0 +1,1782 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13429
+
+/** Group: Version Register */
+/** Type of id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_id : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_id: 32;
+    };
+    uint32_t val;
+} dmac_id0_reg_t;
+
+/** Type of compver0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_compver : RO; bitpos: [31:0]; default: 842018858;
+         *  NA
+         */
+        uint32_t dmac_compver: 32;
+    };
+    uint32_t val;
+} dmac_compver0_reg_t;
+
+/** Group: Configuration Registers */
+/** Type of cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_en: 1;
+        /** int_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t int_en: 1;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} dmac_cfg0_reg_t;
+
+/** Type of chen0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_en: 1;
+        /** ch2_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_en: 1;
+        /** ch3_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_en: 1;
+        /** ch4_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_en: 1;
+        uint32_t reserved_4: 4;
+        /** ch1_en_we : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_en_we: 1;
+        /** ch2_en_we : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_en_we: 1;
+        /** ch3_en_we : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_en_we: 1;
+        /** ch4_en_we : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_en_we: 1;
+        uint32_t reserved_12: 4;
+        /** ch1_susp : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_susp: 1;
+        /** ch2_susp : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_susp: 1;
+        /** ch3_susp : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_susp: 1;
+        /** ch4_susp : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_susp: 1;
+        uint32_t reserved_20: 4;
+        /** ch1_susp_we : WO; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_susp_we: 1;
+        /** ch2_susp_we : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_susp_we: 1;
+        /** ch3_susp_we : WO; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_susp_we: 1;
+        /** ch4_susp_we : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_susp_we: 1;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} dmac_chen0_reg_t;
+
+/** Type of chen1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_abort : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_abort: 1;
+        /** ch2_abort : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_abort: 1;
+        /** ch3_abort : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_abort: 1;
+        /** ch4_abort : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_abort: 1;
+        uint32_t reserved_4: 4;
+        /** ch1_abort_we : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_abort_we: 1;
+        /** ch2_abort_we : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_abort_we: 1;
+        /** ch3_abort_we : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_abort_we: 1;
+        /** ch4_abort_we : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_abort_we: 1;
+        uint32_t reserved_12: 20;
+    };
+    uint32_t val;
+} dmac_chen1_reg_t;
+
+/** Type of reset0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_rst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_rst: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} dmac_reset0_reg_t;
+
+/** Type of lowpower_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gbl_cslp_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t gbl_cslp_en: 1;
+        /** chnl_cslp_en : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t chnl_cslp_en: 1;
+        /** sbiu_cslp_en : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t sbiu_cslp_en: 1;
+        /** mxif_cslp_en : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t mxif_cslp_en: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_lowpower_cfg0_reg_t;
+
+/** Type of lowpower_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** glch_lpdly : R/W; bitpos: [7:0]; default: 64;
+         *  NA
+         */
+        uint32_t glch_lpdly: 8;
+        /** sbiu_lpdly : R/W; bitpos: [15:8]; default: 64;
+         *  NA
+         */
+        uint32_t sbiu_lpdly: 8;
+        /** mxif_lpdly : R/W; bitpos: [23:16]; default: 64;
+         *  NA
+         */
+        uint32_t mxif_lpdly: 8;
+        uint32_t reserved_24: 8;
+    };
+    uint32_t val;
+} dmac_lowpower_cfg1_reg_t;
+
+/** Type of chn_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_sar0_reg_t;
+
+/** Type of chn_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_sar1_reg_t;
+
+/** Type of chn_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_dar0_reg_t;
+
+/** Type of chn_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_dar1_reg_t;
+
+/** Type of chn_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t block_ts: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} dmac_chn_block_ts0_reg_t;
+
+/** Type of chn_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t sms: 1;
+        uint32_t reserved_1: 1;
+        /** dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t dms: 1;
+        uint32_t reserved_3: 1;
+        /** sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t sinc: 1;
+        uint32_t reserved_5: 1;
+        /** dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t dinc: 1;
+        uint32_t reserved_7: 1;
+        /** src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t src_tr_width: 3;
+        /** dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t dst_tr_width: 3;
+        /** src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t src_msize: 4;
+        /** dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t dst_msize: 4;
+        /** ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ar_cache: 4;
+        /** aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t aw_cache: 4;
+        /** nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t nonposted_lastwrite_en: 1;
+        uint32_t reserved_31: 1;
+    };
+    uint32_t val;
+} dmac_chn_ctl0_reg_t;
+
+/** Type of chn_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ar_prot: 3;
+        /** aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t aw_prot: 3;
+        /** arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t arlen_en: 1;
+        /** arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t arlen: 8;
+        /** awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t awlen_en: 1;
+        /** awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t awlen: 8;
+        /** src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t src_stat_en: 1;
+        /** dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t dst_stat_en: 1;
+        /** ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ioc_blktfr: 1;
+        uint32_t reserved_27: 3;
+        /** shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t shadowreg_or_lli_last: 1;
+        /** shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t shadowreg_or_lli_valid: 1;
+    };
+    uint32_t val;
+} dmac_chn_ctl1_reg_t;
+
+/** Type of chn_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t src_multblk_type: 2;
+        /** dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t dst_multblk_type: 2;
+        uint32_t reserved_4: 14;
+        /** rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t rd_uid: 4;
+        uint32_t reserved_22: 3;
+        /** wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t wr_uid: 4;
+        uint32_t reserved_29: 3;
+    };
+    uint32_t val;
+} dmac_chn_cfg0_reg_t;
+
+/** Type of chn_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t tt_fc: 3;
+        /** hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t hs_sel_src: 1;
+        /** hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t hs_sel_dst: 1;
+        /** src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t src_hwhs_pol: 1;
+        /** dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t dst_hwhs_pol: 1;
+        /** src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t src_per: 2;
+        uint32_t reserved_9: 3;
+        /** dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t dst_per: 2;
+        uint32_t reserved_14: 3;
+        /** ch_prior : R/W; bitpos: [19:17]; default: 3;
+         *  NA
+         */
+        uint32_t ch_prior: 3;
+        /** lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t lock_ch: 1;
+        /** lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t lock_ch_l: 2;
+        /** src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t src_osr_lmt: 4;
+        /** dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t dst_osr_lmt: 4;
+        uint32_t reserved_31: 1;
+    };
+    uint32_t val;
+} dmac_chn_cfg1_reg_t;
+
+/** Type of chn_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t lms: 1;
+        uint32_t reserved_1: 5;
+        /** loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t loc0: 26;
+    };
+    uint32_t val;
+} dmac_chn_llp0_reg_t;
+
+/** Type of chn_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t loc1: 32;
+    };
+    uint32_t val;
+} dmac_chn_llp1_reg_t;
+
+/** Type of chn_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_src: 1;
+        /** swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_src_we: 1;
+        /** swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_src: 1;
+        /** swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_src_we: 1;
+        /** swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_src: 1;
+        /** swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_src_we: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} dmac_chn_swhssrc0_reg_t;
+
+/** Type of chn_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_dst: 1;
+        /** swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_dst_we: 1;
+        /** swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_dst: 1;
+        /** swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_dst_we: 1;
+        /** swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_dst: 1;
+        /** swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_dst_we: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} dmac_chn_swhsdst0_reg_t;
+
+/** Type of chn_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t blk_tfr_resumereq: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} dmac_chn_blk_tfr_resumereq0_reg_t;
+
+/** Type of chn_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t axi_read_id_suffix: 1;
+        uint32_t reserved_1: 15;
+        /** axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t axi_write_id_suffix: 1;
+        uint32_t reserved_17: 15;
+    };
+    uint32_t val;
+} dmac_chn_axi_id0_reg_t;
+
+/** Type of chn_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t axi_awqos: 4;
+        /** axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t axi_arqos: 4;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} dmac_chn_axi_qos0_reg_t;
+
+/** Group: Interrupt Registers */
+/** Type of intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_intstat: 1;
+        /** ch2_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_intstat: 1;
+        /** ch3_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_intstat: 1;
+        /** ch4_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_intstat: 1;
+        uint32_t reserved_4: 12;
+        /** commonreg_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t commonreg_intstat: 1;
+        uint32_t reserved_17: 15;
+    };
+    uint32_t val;
+} dmac_intstatus0_reg_t;
+
+/** Type of commonreg_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_slvif_commonreg_dec_err_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_dec_err_intstat: 1;
+        /** clear_slvif_commonreg_wr2ro_err_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wr2ro_err_intstat: 1;
+        /** clear_slvif_commonreg_rd2wo_err_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_rd2wo_err_intstat: 1;
+        /** clear_slvif_commonreg_wronhold_err_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wronhold_err_intstat: 1;
+        uint32_t reserved_4: 3;
+        /** clear_slvif_commonreg_wrparity_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wrparity_err_intstat: 1;
+        /** clear_slvif_undefinedreg_dec_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_undefinedreg_dec_err_intstat: 1;
+        /** clear_mxif1_rch0_eccprot_correrr_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch0_eccprot_correrr_intstat: 1;
+        /** clear_mxif1_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch0_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif1_rch1_eccprot_correrr_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch1_eccprot_correrr_intstat: 1;
+        /** clear_mxif1_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch1_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif1_bch_eccprot_correrr_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_bch_eccprot_correrr_intstat: 1;
+        /** clear_mxif1_bch_eccprot_uncorrerr_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_bch_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif2_rch0_eccprot_correrr_intstat : WO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch0_eccprot_correrr_intstat: 1;
+        /** clear_mxif2_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch0_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif2_rch1_eccprot_correrr_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch1_eccprot_correrr_intstat: 1;
+        /** clear_mxif2_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch1_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif2_bch_eccprot_correrr_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_bch_eccprot_correrr_intstat: 1;
+        /** clear_mxif2_bch_eccprot_uncorrerr_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_bch_eccprot_uncorrerr_intstat: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intclear0_reg_t;
+
+/** Type of commonreg_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_slvif_commonreg_dec_err_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_dec_err_intstat: 1;
+        /** enable_slvif_commonreg_wr2ro_err_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wr2ro_err_intstat: 1;
+        /** enable_slvif_commonreg_rd2wo_err_intstat : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_rd2wo_err_intstat: 1;
+        /** enable_slvif_commonreg_wronhold_err_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wronhold_err_intstat: 1;
+        uint32_t reserved_4: 3;
+        /** enable_slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wrparity_err_intstat: 1;
+        /** enable_slvif_undefinedreg_dec_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_undefinedreg_dec_err_intstat: 1;
+        /** enable_mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_correrr_intstat: 1;
+        /** enable_mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_correrr_intstat: 1;
+        /** enable_mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_correrr_intstat: 1;
+        /** enable_mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_correrr_intstat: 1;
+        /** enable_mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_correrr_intstat: 1;
+        /** enable_mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_correrr_intstat: 1;
+        /** enable_mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intstat: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intstatus_enable0_reg_t;
+
+/** Type of commonreg_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_slvif_commonreg_dec_err_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_dec_err_intsignal: 1;
+        /** enable_slvif_commonreg_wr2ro_err_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wr2ro_err_intsignal: 1;
+        /** enable_slvif_commonreg_rd2wo_err_intsignal : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_rd2wo_err_intsignal: 1;
+        /** enable_slvif_commonreg_wronhold_err_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wronhold_err_intsignal: 1;
+        uint32_t reserved_4: 3;
+        /** enable_slvif_commonreg_wrparity_err_intsignal : RO; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wrparity_err_intsignal: 1;
+        /** enable_slvif_undefinedreg_dec_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_undefinedreg_dec_err_intsignal: 1;
+        /** enable_mxif1_rch0_eccprot_correrr_intsignal : RO; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_correrr_intsignal: 1;
+        /** enable_mxif1_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif1_rch1_eccprot_correrr_intsignal : RO; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_correrr_intsignal: 1;
+        /** enable_mxif1_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif1_bch_eccprot_correrr_intsignal : RO; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_correrr_intsignal: 1;
+        /** enable_mxif1_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif2_rch0_eccprot_correrr_intsignal : RO; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_correrr_intsignal: 1;
+        /** enable_mxif2_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif2_rch1_eccprot_correrr_intsignal : RO; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_correrr_intsignal: 1;
+        /** enable_mxif2_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif2_bch_eccprot_correrr_intsignal : RO; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_correrr_intsignal: 1;
+        /** enable_mxif2_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intsignal: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intsignal_enable0_reg_t;
+
+/** Type of commonreg_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** slvif_commonreg_dec_err_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_dec_err_intstat: 1;
+        /** slvif_commonreg_wr2ro_err_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wr2ro_err_intstat: 1;
+        /** slvif_commonreg_rd2wo_err_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_rd2wo_err_intstat: 1;
+        /** slvif_commonreg_wronhold_err_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wronhold_err_intstat: 1;
+        uint32_t reserved_4: 3;
+        /** slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wrparity_err_intstat: 1;
+        /** slvif_undefinedreg_dec_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_undefinedreg_dec_err_intstat: 1;
+        /** mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch0_eccprot_correrr_intstat: 1;
+        /** mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch0_eccprot_uncorrerr_intstat: 1;
+        /** mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch1_eccprot_correrr_intstat: 1;
+        /** mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch1_eccprot_uncorrerr_intstat: 1;
+        /** mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_bch_eccprot_correrr_intstat: 1;
+        /** mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_bch_eccprot_uncorrerr_intstat: 1;
+        /** mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch0_eccprot_correrr_intstat: 1;
+        /** mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch0_eccprot_uncorrerr_intstat: 1;
+        /** mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch1_eccprot_correrr_intstat: 1;
+        /** mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch1_eccprot_uncorrerr_intstat: 1;
+        /** mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_bch_eccprot_correrr_intstat: 1;
+        /** mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_bch_eccprot_uncorrerr_intstat: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intstatus0_reg_t;
+
+/** Type of chn_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_block_tfr_done_intstat: 1;
+        /** enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dma_tfr_done_intstat: 1;
+        uint32_t reserved_2: 1;
+        /** enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_transcomp_intstat: 1;
+        /** enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_transcomp_intstat: 1;
+        /** enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_dec_err_intstat: 1;
+        /** enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_dec_err_intstat: 1;
+        /** enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_slv_err_intstat: 1;
+        /** enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_slv_err_intstat: 1;
+        /** enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_dec_err_intstat: 1;
+        /** enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_dec_err_intstat: 1;
+        /** enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_slv_err_intstat: 1;
+        /** enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_slv_err_intstat: 1;
+        /** enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_shadowreg_or_lli_invalid_err_intstat: 1;
+        /** enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_multiblktype_err_intstat: 1;
+        uint32_t reserved_15: 1;
+        /** enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_dec_err_intstat: 1;
+        /** enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wr2ro_err_intstat: 1;
+        /** enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_rd2rwo_err_intstat: 1;
+        /** enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronchen_err_intstat: 1;
+        /** enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_shadowreg_wron_valid_err_intstat: 1;
+        /** enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronhold_err_intstat: 1;
+        uint32_t reserved_22: 3;
+        /** enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wrparity_err_intstat: 1;
+        uint32_t reserved_26: 1;
+        /** enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_lock_cleared_intstat: 1;
+        /** enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_src_suspended_intstat: 1;
+        /** enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_suspended_intstat: 1;
+        /** enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_disabled_intstat: 1;
+        /** enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_aborted_intstat: 1;
+    };
+    uint32_t val;
+} dmac_chn_intstatus_enable0_reg_t;
+
+/** Type of chn_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_correrr_intstat: 1;
+        /** enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_uncorrerr_intstat: 1;
+        /** enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_correrr_intstat: 1;
+        /** enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_uncorrerr_intstat: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intstatus_enable1_reg_t;
+
+/** Type of chn_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t block_tfr_done_intstat: 1;
+        /** dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t dma_tfr_done_intstat: 1;
+        uint32_t reserved_2: 1;
+        /** src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t src_transcomp_intstat: 1;
+        /** dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t dst_transcomp_intstat: 1;
+        /** src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t src_dec_err_intstat: 1;
+        /** dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t dst_dec_err_intstat: 1;
+        /** src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t src_slv_err_intstat: 1;
+        /** dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t dst_slv_err_intstat: 1;
+        /** lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t lli_rd_dec_err_intstat: 1;
+        /** lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t lli_wr_dec_err_intstat: 1;
+        /** lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t lli_rd_slv_err_intstat: 1;
+        /** lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t lli_wr_slv_err_intstat: 1;
+        /** shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t shadowreg_or_lli_invalid_err_intstat: 1;
+        /** slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_multiblktype_err_intstat: 1;
+        uint32_t reserved_15: 1;
+        /** slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_dec_err_intstat: 1;
+        /** slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wr2ro_err_intstat: 1;
+        /** slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_rd2rwo_err_intstat: 1;
+        /** slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wronchen_err_intstat: 1;
+        /** slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_shadowreg_wron_valid_err_intstat: 1;
+        /** slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wronhold_err_intstat: 1;
+        uint32_t reserved_22: 3;
+        /** slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wrparity_err_intstat: 1;
+        uint32_t reserved_26: 1;
+        /** ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch_lock_cleared_intstat: 1;
+        /** ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch_src_suspended_intstat: 1;
+        /** ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch_suspended_intstat: 1;
+        /** ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch_disabled_intstat: 1;
+        /** ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch_aborted_intstat: 1;
+    };
+    uint32_t val;
+} dmac_chn_intstatus0_reg_t;
+
+/** Type of chn_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_chmem_correrr_intstat: 1;
+        /** ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_chmem_uncorrerr_intstat: 1;
+        /** ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_uidmem_correrr_intstat: 1;
+        /** ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_uidmem_uncorrerr_intstat: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intstatus1_reg_t;
+
+/** Type of chn_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_block_tfr_done_intsignal: 1;
+        /** enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dma_tfr_done_intsignal: 1;
+        uint32_t reserved_2: 1;
+        /** enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_transcomp_intsignal: 1;
+        /** enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_transcomp_intsignal: 1;
+        /** enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_dec_err_intsignal: 1;
+        /** enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_dec_err_intsignal: 1;
+        /** enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_slv_err_intsignal: 1;
+        /** enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_slv_err_intsignal: 1;
+        /** enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_dec_err_intsignal: 1;
+        /** enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_dec_err_intsignal: 1;
+        /** enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_slv_err_intsignal: 1;
+        /** enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_slv_err_intsignal: 1;
+        /** enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_shadowreg_or_lli_invalid_err_intsignal: 1;
+        /** enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_multiblktype_err_intsignal: 1;
+        uint32_t reserved_15: 1;
+        /** enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_dec_err_intsignal: 1;
+        /** enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wr2ro_err_intsignal: 1;
+        /** enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_rd2rwo_err_intsignal: 1;
+        /** enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronchen_err_intsignal: 1;
+        /** enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_shadowreg_wron_valid_err_intsignal: 1;
+        /** enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronhold_err_intsignal: 1;
+        uint32_t reserved_22: 3;
+        /** enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wrparity_err_intsignal: 1;
+        uint32_t reserved_26: 1;
+        /** enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_lock_cleared_intsignal: 1;
+        /** enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_src_suspended_intsignal: 1;
+        /** enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_suspended_intsignal: 1;
+        /** enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_disabled_intsignal: 1;
+        /** enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_aborted_intsignal: 1;
+    };
+    uint32_t val;
+} dmac_chn_intsignal_enable0_reg_t;
+
+/** Type of chn_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_correrr_intsignal: 1;
+        /** enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_uncorrerr_intsignal: 1;
+        /** enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_correrr_intsignal: 1;
+        /** enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_uncorrerr_intsignal: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intsignal_enable1_reg_t;
+
+/** Type of chn_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_block_tfr_done_intstat: 1;
+        /** clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dma_tfr_done_intstat: 1;
+        uint32_t reserved_2: 1;
+        /** clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_src_transcomp_intstat: 1;
+        /** clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dst_transcomp_intstat: 1;
+        /** clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t clear_src_dec_err_intstat: 1;
+        /** clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dst_dec_err_intstat: 1;
+        /** clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t clear_src_slv_err_intstat: 1;
+        /** clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dst_slv_err_intstat: 1;
+        /** clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_rd_dec_err_intstat: 1;
+        /** clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_wr_dec_err_intstat: 1;
+        /** clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_rd_slv_err_intstat: 1;
+        /** clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_wr_slv_err_intstat: 1;
+        /** clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t clear_shadowreg_or_lli_invalid_err_intstat: 1;
+        /** clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_multiblktype_err_intstat: 1;
+        uint32_t reserved_15: 1;
+        /** clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_dec_err_intstat: 1;
+        /** clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wr2ro_err_intstat: 1;
+        /** clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_rd2rwo_err_intstat: 1;
+        /** clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wronchen_err_intstat: 1;
+        /** clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_shadowreg_wron_valid_err_intstat: 1;
+        /** clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wronhold_err_intstat: 1;
+        uint32_t reserved_22: 3;
+        /** clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wrparity_err_intstat: 1;
+        uint32_t reserved_26: 1;
+        /** clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_lock_cleared_intstat: 1;
+        /** clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_src_suspended_intstat: 1;
+        /** clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_suspended_intstat: 1;
+        /** clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_disabled_intstat: 1;
+        /** clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_aborted_intstat: 1;
+    };
+    uint32_t val;
+} dmac_chn_intclear0_reg_t;
+
+/** Type of chn_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_chmem_correrr_intstat: 1;
+        /** clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_chmem_uncorrerr_intstat: 1;
+        /** clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_uidmem_correrr_intstat: 1;
+        /** clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_uidmem_uncorrerr_intstat: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intclear1_reg_t;
+
+/** Group: Status Registers */
+/** Type of chn_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t cmpltd_blk_tfr_size: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} dmac_chn_status0_reg_t;
+
+/** Type of chn_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t data_left_in_fifo: 15;
+        uint32_t reserved_15: 17;
+    };
+    uint32_t val;
+} dmac_chn_status1_reg_t;
+
+/** Type of chn_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sstat: 32;
+    };
+    uint32_t val;
+} dmac_chn_sstat0_reg_t;
+
+/** Type of chn_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dstat: 32;
+    };
+    uint32_t val;
+} dmac_chn_dstat0_reg_t;
+
+/** Type of chn_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sstatar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_sstatar0_reg_t;
+
+/** Type of chn_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sstatar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_sstatar1_reg_t;
+
+/** Type of chn_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dstatar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_dstatar0_reg_t;
+
+/** Type of chn_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dstatar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_dstatar1_reg_t;
+
+typedef struct {
+    volatile dmac_chn_sar0_reg_t sar0;
+    volatile dmac_chn_sar1_reg_t sar1;
+    volatile dmac_chn_dar0_reg_t dar0;
+    volatile dmac_chn_dar1_reg_t dar1;
+    volatile dmac_chn_block_ts0_reg_t block_ts0;
+    uint32_t reserved_114;
+    volatile dmac_chn_ctl0_reg_t ctl0;
+    volatile dmac_chn_ctl1_reg_t ctl1;
+    volatile dmac_chn_cfg0_reg_t cfg0;
+    volatile dmac_chn_cfg1_reg_t cfg1;
+    volatile dmac_chn_llp0_reg_t llp0;
+    volatile dmac_chn_llp1_reg_t llp1;
+    volatile dmac_chn_status0_reg_t status0;
+    volatile dmac_chn_status1_reg_t status1;
+    volatile dmac_chn_swhssrc0_reg_t swhssrc0;
+    uint32_t reserved_13c;
+    volatile dmac_chn_swhsdst0_reg_t swhsdst0;
+    uint32_t reserved_144;
+    volatile dmac_chn_blk_tfr_resumereq0_reg_t blk_tfr_resumereq0;
+    uint32_t reserved_14c;
+    volatile dmac_chn_axi_id0_reg_t axi_id0;
+    uint32_t reserved_154;
+    volatile dmac_chn_axi_qos0_reg_t axi_qos0;
+    uint32_t reserved_15c;
+    volatile dmac_chn_sstat0_reg_t sstat0;
+    uint32_t reserved_164;
+    volatile dmac_chn_dstat0_reg_t dstat0;
+    uint32_t reserved_16c;
+    volatile dmac_chn_sstatar0_reg_t sstatar0;
+    volatile dmac_chn_sstatar1_reg_t sstatar1;
+    volatile dmac_chn_dstatar0_reg_t dstatar0;
+    volatile dmac_chn_dstatar1_reg_t dstatar1;
+    volatile dmac_chn_intstatus_enable0_reg_t int_st_ena0;
+    volatile dmac_chn_intstatus_enable1_reg_t int_st_ena1;
+    volatile dmac_chn_intstatus0_reg_t int_st0;
+    volatile dmac_chn_intstatus1_reg_t int_st1;
+    volatile dmac_chn_intsignal_enable0_reg_t int_sig_ena0;
+    volatile dmac_chn_intsignal_enable1_reg_t int_sig_ena1;
+    volatile dmac_chn_intclear0_reg_t int_clr0;
+    volatile dmac_chn_intclear1_reg_t int_clr1;
+    uint32_t reserved_1a0[24];
+} dmac_channel_reg_t;
+
+typedef struct dw_gdma_dev_t {
+    volatile dmac_id0_reg_t id0;
+    uint32_t reserved_004;
+    volatile dmac_compver0_reg_t compver0;
+    uint32_t reserved_00c;
+    volatile dmac_cfg0_reg_t cfg0;
+    uint32_t reserved_014;
+    volatile dmac_chen0_reg_t chen0;
+    volatile dmac_chen1_reg_t chen1;
+    uint32_t reserved_020[4];
+    volatile dmac_intstatus0_reg_t int_st0;
+    uint32_t reserved_034;
+    volatile dmac_commonreg_intclear0_reg_t common_int_clr0;
+    uint32_t reserved_03c;
+    volatile dmac_commonreg_intstatus_enable0_reg_t common_int_st_ena0;
+    uint32_t reserved_044;
+    volatile dmac_commonreg_intsignal_enable0_reg_t common_int_sig_ena0;
+    uint32_t reserved_04c;
+    volatile dmac_commonreg_intstatus0_reg_t common_int_st0;
+    uint32_t reserved_054;
+    volatile dmac_reset0_reg_t reset0;
+    uint32_t reserved_05c;
+    volatile dmac_lowpower_cfg0_reg_t lowpower_cfg0;
+    volatile dmac_lowpower_cfg1_reg_t lowpower_cfg1;
+    uint32_t reserved_068[38];
+    volatile dmac_channel_reg_t ch[4];
+} dw_gdma_dev_t;
+
+extern dw_gdma_dev_t DW_GDMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dw_gdma_dev_t) == 0x500, "Invalid size of dw_gdma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ecc_mult_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ecc_mult_reg.h
new file mode 100644
index 0000000000..ac87d7b65a
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ecc_mult_reg.h
@@ -0,0 +1,210 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECC_MULT_INT_RAW_REG register
+ *  ECC raw interrupt status register
+ */
+#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
+/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
+#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_RAW_S  0
+
+/** ECC_MULT_INT_ST_REG register
+ *  ECC masked interrupt status register
+ */
+#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
+/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
+#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ST_S  0
+
+/** ECC_MULT_INT_ENA_REG register
+ *  ECC interrupt enable register
+ */
+#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
+/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
+#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ENA_S  0
+
+/** ECC_MULT_INT_CLR_REG register
+ *  ECC interrupt clear register
+ */
+#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
+/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
+#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_CLR_S  0
+
+/** ECC_MULT_CONF_REG register
+ *  ECC configuration register
+ */
+#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
+/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures whether to start calculation of ECC Accelerator. This bit will be
+ *  self-cleared after the calculation is done.
+ *  0: No effect
+ *  1: Start calculation of ECC Accelerator
+ */
+#define ECC_MULT_START    (BIT(0))
+#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
+#define ECC_MULT_START_V  0x00000001U
+#define ECC_MULT_START_S  0
+/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
+ *  Configures whether to reset ECC Accelerator.
+ *  0: No effect
+ *  1: Reset
+ */
+#define ECC_MULT_RESET    (BIT(1))
+#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
+#define ECC_MULT_RESET_V  0x00000001U
+#define ECC_MULT_RESET_S  1
+/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the key length mode bit of ECC Accelerator.
+ *  0: P-192
+ *  1: P-256
+ *  2: P-384
+ *  3: Reserved.
+ */
+#define ECC_MULT_KEY_LENGTH    0x00000003U
+#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
+#define ECC_MULT_KEY_LENGTH_V  0x00000003U
+#define ECC_MULT_KEY_LENGTH_S  2
+/** ECC_MULT_MOD_BASE : R/W; bitpos: [4]; default: 0;
+ *  Configures the mod base of mod operation, only valid in work_mode 8-11.
+ *  0: n(order of curve)
+ *  1: p(mod base of curve)
+ */
+#define ECC_MULT_MOD_BASE    (BIT(4))
+#define ECC_MULT_MOD_BASE_M  (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
+#define ECC_MULT_MOD_BASE_V  0x00000001U
+#define ECC_MULT_MOD_BASE_S  4
+/** ECC_MULT_WORK_MODE : R/W; bitpos: [8:5]; default: 0;
+ *  Configures the work mode of ECC Accelerator.
+ *  0: Point Multi mode
+ *  1: Reserved
+ *  2: Point Verif mode
+ *  3: Point Verif + Multi mode
+ *  4: Jacobian Point Multi mode
+ *  5: Reserved
+ *  6: Jacobian Point Verif mode
+ *  7: Point Verif + Jacobian Point Multi mode
+ *  8: Mod Add mode
+ *  9. Mod Sub mode
+ *  10: Mod Multi mode
+ *  11: Mod Div mode
+ */
+#define ECC_MULT_WORK_MODE    0x0000000FU
+#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
+#define ECC_MULT_WORK_MODE_V  0x0000000FU
+#define ECC_MULT_WORK_MODE_S  5
+/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [9]; default: 0;
+ *  Configures the security mode of ECC Accelerator.
+ *  0: no secure function enabled.
+ *  1: enable constant-time calculation in all point multiplication modes.
+ */
+#define ECC_MULT_SECURITY_MODE    (BIT(9))
+#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
+#define ECC_MULT_SECURITY_MODE_V  0x00000001U
+#define ECC_MULT_SECURITY_MODE_S  9
+/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
+ *  Represents the verification result of ECC Accelerator, valid only when calculation
+ *  is done.
+ */
+#define ECC_MULT_VERIFICATION_RESULT    (BIT(29))
+#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
+#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
+#define ECC_MULT_VERIFICATION_RESULT_S  29
+/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Configures whether to force on register clock gate.
+ *  0: No effect
+ *  1: Force on
+ */
+#define ECC_MULT_CLK_EN    (BIT(30))
+#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
+#define ECC_MULT_CLK_EN_V  0x00000001U
+#define ECC_MULT_CLK_EN_S  30
+/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  Configures whether to force on ECC memory clock gate.
+ *  0: No effect
+ *  1: Force on
+ */
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON    (BIT(31))
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M  (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V  0x00000001U
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S  31
+
+/** ECC_MULT_DATE_REG register
+ *  Version control register
+ */
+#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
+/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37781792;
+ *  ECC mult version control register
+ */
+#define ECC_MULT_DATE    0x0FFFFFFFU
+#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
+#define ECC_MULT_DATE_V  0x0FFFFFFFU
+#define ECC_MULT_DATE_S  0
+
+/** ECC_MULT_K_MEM register
+ *  The memory that stores k.
+ */
+#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
+#define ECC_MULT_K_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_PX_MEM register
+ *  The memory that stores Px.
+ */
+#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x130)
+#define ECC_MULT_PX_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_PY_MEM register
+ *  The memory that stores Py.
+ */
+#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x160)
+#define ECC_MULT_PY_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_QX_MEM register
+ *  The memory that stores Qx.
+ */
+#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x190)
+#define ECC_MULT_QX_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_QY_MEM register
+ *  The memory that stores Qy.
+ */
+#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x1c0)
+#define ECC_MULT_QY_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_QZ_MEM register
+ *  The memory that stores Qz.
+ */
+#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1f0)
+#define ECC_MULT_QZ_MEM_SIZE_BYTES 48
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ecc_mult_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ecc_mult_struct.h
new file mode 100644
index 0000000000..8cb5a65ee6
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ecc_mult_struct.h
@@ -0,0 +1,192 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECC raw interrupt status register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECC masked interrupt status register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECC interrupt enable register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECC interrupt clear register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of conf register
+ *  ECC configuration register
+ */
+typedef union {
+    struct {
+        /** start : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether to start calculation of ECC Accelerator. This bit will be
+         *  self-cleared after the calculation is done.
+         *  0: No effect
+         *  1: Start calculation of ECC Accelerator
+         */
+        uint32_t start:1;
+        /** reset : WT; bitpos: [1]; default: 0;
+         *  Configures whether to reset ECC Accelerator.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t reset:1;
+        /** key_length : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the key length mode bit of ECC Accelerator.
+         *  0: P-192
+         *  1: P-256
+         *  2: P-384
+         *  3: Reserved.
+         */
+        uint32_t key_length:2;
+        /** mod_base : R/W; bitpos: [4]; default: 0;
+         *  Configures the mod base of mod operation, only valid in work_mode 8-11.
+         *  0: n(order of curve)
+         *  1: p(mod base of curve)
+         */
+        uint32_t mod_base:1;
+        /** work_mode : R/W; bitpos: [8:5]; default: 0;
+         *  Configures the work mode of ECC Accelerator.
+         *  0: Point Multi mode
+         *  1: Reserved
+         *  2: Point Verif mode
+         *  3: Point Verif + Multi mode
+         *  4: Jacobian Point Multi mode
+         *  5: Reserved
+         *  6: Jacobian Point Verif mode
+         *  7: Point Verif + Jacobian Point Multi mode
+         *  8: Mod Add mode
+         *  9. Mod Sub mode
+         *  10: Mod Multi mode
+         *  11: Mod Div mode
+         */
+        uint32_t work_mode:4;
+        /** security_mode : R/W; bitpos: [9]; default: 0;
+         *  Configures the security mode of ECC Accelerator.
+         *  0: no secure function enabled.
+         *  1: enable constant-time calculation in all point multiplication modes.
+         */
+        uint32_t security_mode:1;
+        uint32_t reserved_10:19;
+        /** verification_result : RO/SS; bitpos: [29]; default: 0;
+         *  Represents the verification result of ECC Accelerator, valid only when calculation
+         *  is done.
+         */
+        uint32_t verification_result:1;
+        /** clk_en : R/W; bitpos: [30]; default: 0;
+         *  Configures whether to force on register clock gate.
+         *  0: No effect
+         *  1: Force on
+         */
+        uint32_t clk_en:1;
+        /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
+         *  Configures whether to force on ECC memory clock gate.
+         *  0: No effect
+         *  1: Force on
+         */
+        uint32_t mem_clock_gate_force_on:1;
+    };
+    uint32_t val;
+} ecc_mult_conf_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37781792;
+         *  ECC mult version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecc_mult_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile ecc_mult_int_raw_reg_t int_raw;
+    volatile ecc_mult_int_st_reg_t int_st;
+    volatile ecc_mult_int_ena_reg_t int_ena;
+    volatile ecc_mult_int_clr_reg_t int_clr;
+    volatile ecc_mult_conf_reg_t conf;
+    uint32_t reserved_020[55];
+    volatile ecc_mult_date_reg_t date;
+    volatile uint32_t k[12];
+    volatile uint32_t px[12];
+    volatile uint32_t py[12];
+    volatile uint32_t qx[12];
+    volatile uint32_t qy[12];
+    volatile uint32_t qz[12];
+} ecc_mult_dev_t;
+
+extern ecc_mult_dev_t ECC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecc_mult_dev_t) == 0x220, "Invalid size of ecc_mult_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ecdsa_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ecdsa_eco5_reg.h
new file mode 100644
index 0000000000..179698edbb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ecdsa_eco5_reg.h
@@ -0,0 +1,359 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECDSA_CONF_REG register
+ *  ECDSA configure register
+ */
+#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
+/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+ *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+ */
+#define ECDSA_WORK_MODE    0x00000003U
+#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
+#define ECDSA_WORK_MODE_V  0x00000003U
+#define ECDSA_WORK_MODE_S  0
+/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0;
+ *  The ecc curve select bit of ECDSA Accelerator.  0: P-192. 1: P-256. 2: P-384.
+ */
+#define ECDSA_ECC_CURVE    0x00000003U
+#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
+#define ECDSA_ECC_CURVE_V  0x00000003U
+#define ECDSA_ECC_CURVE_S  2
+/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0;
+ *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+ *  written by software.
+ */
+#define ECDSA_SOFTWARE_SET_K    (BIT(4))
+#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
+#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_K_S  4
+/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0;
+ *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+ *  software.
+ */
+#define ECDSA_SOFTWARE_SET_Z    (BIT(5))
+#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
+#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_Z_S  5
+/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0;
+ *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+ *  deterministic derivation algorithm.
+ */
+#define ECDSA_DETERMINISTIC_K    (BIT(6))
+#define ECDSA_DETERMINISTIC_K_M  (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
+#define ECDSA_DETERMINISTIC_K_V  0x00000001U
+#define ECDSA_DETERMINISTIC_K_S  6
+
+/** ECDSA_CLK_REG register
+ *  ECDSA clock gate register
+ */
+#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
+/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
+#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
+#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
+#define ECDSA_CLK_GATE_FORCE_ON_S  0
+
+/** ECDSA_INT_RAW_REG register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
+/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_RAW    (BIT(0))
+#define ECDSA_PREP_DONE_INT_RAW_M  (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
+#define ECDSA_PREP_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_RAW_S  0
+/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_RAW    (BIT(1))
+#define ECDSA_PROC_DONE_INT_RAW_M  (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
+#define ECDSA_PROC_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_RAW_S  1
+/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_RAW    (BIT(2))
+#define ECDSA_POST_DONE_INT_RAW_M  (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
+#define ECDSA_POST_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_POST_DONE_INT_RAW_S  2
+/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
+#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_RAW_S  3
+
+/** ECDSA_INT_ST_REG register
+ *  ECDSA interrupt status register.
+ */
+#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
+/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_ST    (BIT(0))
+#define ECDSA_PREP_DONE_INT_ST_M  (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
+#define ECDSA_PREP_DONE_INT_ST_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_ST_S  0
+/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_ST    (BIT(1))
+#define ECDSA_PROC_DONE_INT_ST_M  (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
+#define ECDSA_PROC_DONE_INT_ST_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_ST_S  1
+/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_ST    (BIT(2))
+#define ECDSA_POST_DONE_INT_ST_M  (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
+#define ECDSA_POST_DONE_INT_ST_V  0x00000001U
+#define ECDSA_POST_DONE_INT_ST_S  2
+/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ST    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
+#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ST_S  3
+
+/** ECDSA_INT_ENA_REG register
+ *  ECDSA interrupt enable register.
+ */
+#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
+/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_ENA    (BIT(0))
+#define ECDSA_PREP_DONE_INT_ENA_M  (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
+#define ECDSA_PREP_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_ENA_S  0
+/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_ENA    (BIT(1))
+#define ECDSA_PROC_DONE_INT_ENA_M  (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
+#define ECDSA_PROC_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_ENA_S  1
+/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_ENA    (BIT(2))
+#define ECDSA_POST_DONE_INT_ENA_M  (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
+#define ECDSA_POST_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_POST_DONE_INT_ENA_S  2
+/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
+#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ENA_S  3
+
+/** ECDSA_INT_CLR_REG register
+ *  ECDSA interrupt clear register.
+ */
+#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
+/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_CLR    (BIT(0))
+#define ECDSA_PREP_DONE_INT_CLR_M  (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
+#define ECDSA_PREP_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_CLR_S  0
+/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_CLR    (BIT(1))
+#define ECDSA_PROC_DONE_INT_CLR_M  (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
+#define ECDSA_PROC_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_CLR_S  1
+/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_CLR    (BIT(2))
+#define ECDSA_POST_DONE_INT_CLR_M  (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
+#define ECDSA_POST_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_POST_DONE_INT_CLR_S  2
+/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
+#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_CLR_S  3
+
+/** ECDSA_START_REG register
+ *  ECDSA start register
+ */
+#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
+/** ECDSA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+ *  after configuration.
+ */
+#define ECDSA_START    (BIT(0))
+#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
+#define ECDSA_START_V  0x00000001U
+#define ECDSA_START_S  0
+/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_LOAD_DONE    (BIT(1))
+#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
+#define ECDSA_LOAD_DONE_V  0x00000001U
+#define ECDSA_LOAD_DONE_S  1
+/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
+ *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_GET_DONE    (BIT(2))
+#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
+#define ECDSA_GET_DONE_V  0x00000001U
+#define ECDSA_GET_DONE_S  2
+
+/** ECDSA_STATE_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
+/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
+ *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+ *  state.
+ */
+#define ECDSA_BUSY    0x00000003U
+#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
+#define ECDSA_BUSY_V  0x00000003U
+#define ECDSA_BUSY_S  0
+
+/** ECDSA_RESULT_REG register
+ *  ECDSA result register
+ */
+#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
+/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+ *  done.
+ */
+#define ECDSA_OPERATION_RESULT    (BIT(0))
+#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
+#define ECDSA_OPERATION_RESULT_V  0x00000001U
+#define ECDSA_OPERATION_RESULT_S  0
+
+/** ECDSA_DATE_REG register
+ *  Version control register
+ */
+#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
+/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984;
+ *  ECDSA version control register
+ */
+#define ECDSA_DATE    0x0FFFFFFFU
+#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
+#define ECDSA_DATE_V  0x0FFFFFFFU
+#define ECDSA_DATE_S  0
+
+/** ECDSA_SHA_MODE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
+/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
+ *  SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 7: invalid.
+ */
+#define ECDSA_SHA_MODE    0x00000007U
+#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
+#define ECDSA_SHA_MODE_V  0x00000007U
+#define ECDSA_SHA_MODE_S  0
+
+/** ECDSA_SHA_START_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
+/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_START    (BIT(0))
+#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
+#define ECDSA_SHA_START_V  0x00000001U
+#define ECDSA_SHA_START_S  0
+
+/** ECDSA_SHA_CONTINUE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
+/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_CONTINUE    (BIT(0))
+#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
+#define ECDSA_SHA_CONTINUE_V  0x00000001U
+#define ECDSA_SHA_CONTINUE_S  0
+
+/** ECDSA_SHA_BUSY_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
+/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
+ *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+ *  calculation. 0: SHA is idle.
+ */
+#define ECDSA_SHA_BUSY    (BIT(0))
+#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
+#define ECDSA_SHA_BUSY_V  0x00000001U
+#define ECDSA_SHA_BUSY_S  0
+
+/** ECDSA_MESSAGE_MEM register
+ *  The memory that stores message.
+ */
+#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
+#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64
+
+/** ECDSA_R_MEM register
+ *  The memory that stores r.
+ */
+#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0)
+#define ECDSA_R_MEM_SIZE_BYTES 48
+
+/** ECDSA_S_MEM register
+ *  The memory that stores s.
+ */
+#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410)
+#define ECDSA_S_MEM_SIZE_BYTES 48
+
+/** ECDSA_Z_MEM register
+ *  The memory that stores software written z.
+ */
+#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440)
+#define ECDSA_Z_MEM_SIZE_BYTES 48
+
+/** ECDSA_QAX_MEM register
+ *  The memory that stores x coordinates of QA or software written k.
+ */
+#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470)
+#define ECDSA_QAX_MEM_SIZE_BYTES 48
+
+/** ECDSA_QAY_MEM register
+ *  The memory that stores y coordinates of QA.
+ */
+#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0)
+#define ECDSA_QAY_MEM_SIZE_BYTES 48
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ecdsa_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ecdsa_reg.h
new file mode 100644
index 0000000000..59b58185f8
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ecdsa_reg.h
@@ -0,0 +1,318 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECDSA_CONF_REG register
+ *  ECDSA configure register
+ */
+#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
+/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+ *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+ */
+#define ECDSA_WORK_MODE    0x00000003U
+#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
+#define ECDSA_WORK_MODE_V  0x00000003U
+#define ECDSA_WORK_MODE_S  0
+/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
+ *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
+ */
+#define ECDSA_ECC_CURVE    (BIT(2))
+#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
+#define ECDSA_ECC_CURVE_V  0x00000001U
+#define ECDSA_ECC_CURVE_S  2
+/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
+ *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+ *  written by software.
+ */
+#define ECDSA_SOFTWARE_SET_K    (BIT(3))
+#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
+#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_K_S  3
+/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
+ *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+ *  software.
+ */
+#define ECDSA_SOFTWARE_SET_Z    (BIT(4))
+#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
+#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_Z_S  4
+/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
+ *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+ *  deterministic derivation algorithm.
+ */
+#define ECDSA_DETERMINISTIC_K    (BIT(5))
+#define ECDSA_DETERMINISTIC_K_M  (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
+#define ECDSA_DETERMINISTIC_K_V  0x00000001U
+#define ECDSA_DETERMINISTIC_K_S  5
+/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
+ *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
+ */
+#define ECDSA_DETERMINISTIC_LOOP    0x0000FFFFU
+#define ECDSA_DETERMINISTIC_LOOP_M  (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
+#define ECDSA_DETERMINISTIC_LOOP_V  0x0000FFFFU
+#define ECDSA_DETERMINISTIC_LOOP_S  6
+
+/** ECDSA_CLK_REG register
+ *  ECDSA clock gate register
+ */
+#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
+/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
+#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
+#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
+#define ECDSA_CLK_GATE_FORCE_ON_S  0
+
+/** ECDSA_INT_RAW_REG register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
+/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_RAW    (BIT(0))
+#define ECDSA_CALC_DONE_INT_RAW_M  (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
+#define ECDSA_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_RAW_S  0
+/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
+#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_RAW_S  1
+
+/** ECDSA_INT_ST_REG register
+ *  ECDSA interrupt status register.
+ */
+#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
+/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_ST    (BIT(0))
+#define ECDSA_CALC_DONE_INT_ST_M  (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
+#define ECDSA_CALC_DONE_INT_ST_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_ST_S  0
+/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ST    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
+#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ST_S  1
+
+/** ECDSA_INT_ENA_REG register
+ *  ECDSA interrupt enable register.
+ */
+#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
+/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_ENA    (BIT(0))
+#define ECDSA_CALC_DONE_INT_ENA_M  (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
+#define ECDSA_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_ENA_S  0
+/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
+#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ENA_S  1
+
+/** ECDSA_INT_CLR_REG register
+ *  ECDSA interrupt clear register.
+ */
+#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
+/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_CLR    (BIT(0))
+#define ECDSA_CALC_DONE_INT_CLR_M  (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
+#define ECDSA_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_CLR_S  0
+/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
+#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_CLR_S  1
+
+/** ECDSA_START_REG register
+ *  ECDSA start register
+ */
+#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
+/** ECDSA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+ *  after configuration.
+ */
+#define ECDSA_START    (BIT(0))
+#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
+#define ECDSA_START_V  0x00000001U
+#define ECDSA_START_S  0
+/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_LOAD_DONE    (BIT(1))
+#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
+#define ECDSA_LOAD_DONE_V  0x00000001U
+#define ECDSA_LOAD_DONE_S  1
+/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
+ *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_GET_DONE    (BIT(2))
+#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
+#define ECDSA_GET_DONE_V  0x00000001U
+#define ECDSA_GET_DONE_S  2
+
+/** ECDSA_STATE_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
+/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
+ *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+ *  state.
+ */
+#define ECDSA_BUSY    0x00000003U
+#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
+#define ECDSA_BUSY_V  0x00000003U
+#define ECDSA_BUSY_S  0
+
+/** ECDSA_RESULT_REG register
+ *  ECDSA result register
+ */
+#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
+/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+ *  done.
+ */
+#define ECDSA_OPERATION_RESULT    (BIT(0))
+#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
+#define ECDSA_OPERATION_RESULT_V  0x00000001U
+#define ECDSA_OPERATION_RESULT_S  0
+/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
+ *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
+ *  curve order, then actually taken k = k mod n.
+ */
+#define ECDSA_K_VALUE_WARNING    (BIT(1))
+#define ECDSA_K_VALUE_WARNING_M  (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
+#define ECDSA_K_VALUE_WARNING_V  0x00000001U
+#define ECDSA_K_VALUE_WARNING_S  1
+
+/** ECDSA_DATE_REG register
+ *  Version control register
+ */
+#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
+/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
+ *  ECDSA version control register
+ */
+#define ECDSA_DATE    0x0FFFFFFFU
+#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
+#define ECDSA_DATE_V  0x0FFFFFFFU
+#define ECDSA_DATE_S  0
+
+/** ECDSA_SHA_MODE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
+/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
+ *  Others: invalid.
+ */
+#define ECDSA_SHA_MODE    0x00000007U
+#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
+#define ECDSA_SHA_MODE_V  0x00000007U
+#define ECDSA_SHA_MODE_S  0
+
+/** ECDSA_SHA_START_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
+/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_START    (BIT(0))
+#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
+#define ECDSA_SHA_START_V  0x00000001U
+#define ECDSA_SHA_START_S  0
+
+/** ECDSA_SHA_CONTINUE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
+/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_CONTINUE    (BIT(0))
+#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
+#define ECDSA_SHA_CONTINUE_V  0x00000001U
+#define ECDSA_SHA_CONTINUE_S  0
+
+/** ECDSA_SHA_BUSY_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
+/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
+ *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+ *  calculation. 0: SHA is idle.
+ */
+#define ECDSA_SHA_BUSY    (BIT(0))
+#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
+#define ECDSA_SHA_BUSY_V  0x00000001U
+#define ECDSA_SHA_BUSY_S  0
+
+/** ECDSA_MESSAGE_MEM register
+ *  The memory that stores message.
+ */
+#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
+#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
+
+/** ECDSA_R_MEM register
+ *  The memory that stores r.
+ */
+#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
+#define ECDSA_R_MEM_SIZE_BYTES 32
+
+/** ECDSA_S_MEM register
+ *  The memory that stores s.
+ */
+#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
+#define ECDSA_S_MEM_SIZE_BYTES 32
+
+/** ECDSA_Z_MEM register
+ *  The memory that stores software written z.
+ */
+#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
+#define ECDSA_Z_MEM_SIZE_BYTES 32
+
+/** ECDSA_QAX_MEM register
+ *  The memory that stores x coordinates of QA or software written k.
+ */
+#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
+#define ECDSA_QAX_MEM_SIZE_BYTES 32
+
+/** ECDSA_QAY_MEM register
+ *  The memory that stores y coordinates of QA.
+ */
+#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
+#define ECDSA_QAY_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ecdsa_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ecdsa_struct.h
new file mode 100644
index 0000000000..5f820a7ee2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ecdsa_struct.h
@@ -0,0 +1,347 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Data Memory */
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  ECDSA configure register
+ */
+typedef union {
+    struct {
+        /** work_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+         *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+         */
+        uint32_t work_mode:2;
+        /** ecc_curve : R/W; bitpos: [3:2]; default: 0;
+         *  The ecc curve select bit of ECDSA Accelerator.  0: P-192. 1: P-256. 2: P-384.
+         */
+        uint32_t ecc_curve:2;
+        /** software_set_k : R/W; bitpos: [4]; default: 0;
+         *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+         *  written by software.
+         */
+        uint32_t software_set_k:1;
+        /** software_set_z : R/W; bitpos: [5]; default: 0;
+         *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+         *  software.
+         */
+        uint32_t software_set_z:1;
+        /** deterministic_k : R/W; bitpos: [6]; default: 0;
+         *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+         *  deterministic derivation algorithm.
+         */
+        uint32_t deterministic_k:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ecdsa_conf_reg_t;
+
+/** Type of start register
+ *  ECDSA start register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+         *  after configuration.
+         */
+        uint32_t start:1;
+        /** load_done : WT; bitpos: [1]; default: 0;
+         *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t load_done:1;
+        /** get_done : WT; bitpos: [2]; default: 0;
+         *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t get_done:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_start_reg_t;
+
+
+/** Group: Clock and reset registers */
+/** Type of clk register
+ *  ECDSA clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_gate_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_raw:1;
+        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_raw:1;
+        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_raw:1;
+        /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECDSA interrupt status register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_st:1;
+        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_st:1;
+        /** post_done_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_st:1;
+        /** sha_release_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECDSA interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_ena:1;
+        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_ena:1;
+        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_ena:1;
+        /** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECDSA interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_clr:1;
+        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_clr:1;
+        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_clr:1;
+        /** sha_release_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_clr_reg_t;
+
+
+/** Group: Status registers */
+/** Type of state register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** busy : RO; bitpos: [1:0]; default: 0;
+         *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+         *  state.
+         */
+        uint32_t busy:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of result register
+ *  ECDSA result register
+ */
+typedef union {
+    struct {
+        /** operation_result : RO/SS; bitpos: [0]; default: 0;
+         *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+         *  done.
+         */
+        uint32_t operation_result:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_result_reg_t;
+
+
+/** Group: SHA register */
+/** Type of sha_mode register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_mode : R/W; bitpos: [2:0]; default: 0;
+         *  The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
+         *  SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 7: invalid.
+         */
+        uint32_t sha_mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_sha_mode_reg_t;
+
+/** Type of sha_start register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_start_reg_t;
+
+/** Type of sha_continue register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_continue : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_continue_reg_t;
+
+/** Type of sha_busy register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** sha_busy : RO; bitpos: [0]; default: 0;
+         *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+         *  calculation. 0: SHA is idle.
+         */
+        uint32_t sha_busy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_busy_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37785984;
+         *  ECDSA version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecdsa_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile ecdsa_conf_reg_t conf;
+    volatile ecdsa_clk_reg_t clk;
+    volatile ecdsa_int_raw_reg_t int_raw;
+    volatile ecdsa_int_st_reg_t int_st;
+    volatile ecdsa_int_ena_reg_t int_ena;
+    volatile ecdsa_int_clr_reg_t int_clr;
+    volatile ecdsa_start_reg_t start;
+    volatile ecdsa_state_reg_t state;
+    volatile ecdsa_result_reg_t result;
+    uint32_t reserved_028[53];
+    volatile ecdsa_date_reg_t date;
+    uint32_t reserved_100[64];
+    volatile ecdsa_sha_mode_reg_t sha_mode;
+    uint32_t reserved_204[3];
+    volatile ecdsa_sha_start_reg_t sha_start;
+    volatile ecdsa_sha_continue_reg_t sha_continue;
+    volatile ecdsa_sha_busy_reg_t sha_busy;
+    uint32_t reserved_21c[25];
+    volatile uint32_t message[16];
+    uint32_t reserved_2c0[72];
+    volatile uint32_t r[12];
+    volatile uint32_t s[12];
+    volatile uint32_t z[12];
+    volatile uint32_t qax[12];
+    volatile uint32_t qay[12];
+} ecdsa_dev_t;
+
+extern ecdsa_dev_t ECDSA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/efuse_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/efuse_eco5_struct.h
new file mode 100644
index 0000000000..e24109ae08
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/efuse_eco5_struct.h
@@ -0,0 +1,3689 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: program_data registers */
+/** Type of pgm_datan register
+ *  Represents pgm_datan
+ */
+typedef union {
+    struct {
+        /** pgm_data_n : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the nth 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_n:32;
+    };
+    uint32_t val;
+} efuse_pgm_datan_reg_t;
+
+/** Type of pgm_check_valuen register
+ *  Represents pgm_check_valuen
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the nth RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_n:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_valuen_reg_t;
+
+
+/** Group: block0 registers */
+/** Type of rd_wr_dis register
+ *  Represents rd_wr_dis
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled.  For
+         *  mapping between the bits of this field and the eFuse memory bits, please refer to
+         *  Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.
+         *  1: Disabled
+         *  0: Enabled
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+         *  enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t rd_dis:7;
+        /** recovery_bootloader_flash_sector_0_1 : RO; bitpos: [8:7]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_0_1:2;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  Set this bit to disable function of usb switch to jtag in module of usb device.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** recovery_bootloader_flash_sector_2_2 : RO; bitpos: [10]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_2_2:1;
+        uint32_t reserved_11:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Set this bit to disable the function that forces chip into download mode.
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
+         *  boot_mode_download.
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Set this bit to disable TWAI function.
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0.
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Set this bit to disable flash manual encrypt function (except in SPI boot mode).
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** recovery_bootloader_flash_sector_3_6 : RO; bitpos: [24:21]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_3_6:4;
+        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
+         *  0: intphy(gpio24/25) <---> usb_device
+         *  1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device
+         *  1: intphy(24/25) <---> usb_otg11.
+         */
+        uint32_t usb_phy_sel:1;
+        /** huk_gen_state : RO; bitpos: [30:26]; default: 0;
+         *  Set the bits to control validation of HUK generate mode. Odd of 1 is invalid, even
+         *  of 1 is valid.
+         */
+        uint32_t huk_gen_state:5;
+        /** recovery_bootloader_flash_sector_7_7 : RO; bitpos: [31]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_7_7:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** recovery_bootloader_flash_sector_8_10 : RO; bitpos: [2:0]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_8_10:3;
+        /** recovery_bootloader_flash_sector_11_11 : RO; bitpos: [3]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_11_11:1;
+        /** km_rnd_switch_cycle : RO; bitpos: [4]; default: 0;
+         *  Set the bits to control key manager random number switch cycle. 0: control by
+         *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+         */
+        uint32_t km_rnd_switch_cycle:1;
+        /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0;
+         *  EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field:
+         *  {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to
+         *  control whether corresponding key can only be deployed once. 1 is true, 0 is false.
+         *  bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+         */
+        uint32_t km_deploy_only_once:4;
+        /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0;
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form
+         *  one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H,
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether
+         *  corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda,
+         *  bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+         */
+        uint32_t force_use_key_manager_key:4;
+        /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable software written init key, and force use efuse_init_key.
+         */
+        uint32_t force_disable_sw_init_key:1;
+        /** km_xts_key_length_256 : RO; bitpos: [14]; default: 0;
+         *  Set this bit to config flash encryption xts-512 key, else use xts-256 key when
+         *  using the key manager
+         */
+        uint32_t km_xts_key_length_256:1;
+        /** ecc_force_const_time : RO; bitpos: [15]; default: 0;
+         *  Set this bit to permanently turn on ECC const-time mode.
+         */
+        uint32_t ecc_force_const_time:1;
+        uint32_t reserved_16:1;
+        /** wdt_delay_sel : RO; bitpos: [17]; default: 0;
+         *  Select lp wdt timeout threshold at startup = initial timeout value * (2 ^
+         *  (EFUSE_WDT_DELAY_SEL + 1))
+         */
+        uint32_t wdt_delay_sel:1;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+         *  number of 1: disable.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Set this bit to enable revoking first secure boot key.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Set this bit to enable revoking second secure boot key.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Set this bit to enable revoking third secure boot key.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
+         *  Configures the clock random divide mode to determine the dpa secure level
+         */
+        uint32_t sec_dpa_level:2;
+        uint32_t reserved_18:1;
+        /** xts_dpa_clk_enable : RO; bitpos: [19]; default: 0;
+         *  Sets this bit to enable xts clock anti-dpa attack function.
+         */
+        uint32_t xts_dpa_clk_enable:1;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Set this bit to enable secure boot.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Set this bit to enable revoking aggressive secure boot.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** km_deploy_only_once_h : RO; bitpos: [22]; default: 0;
+         *  EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field:
+         *  {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to
+         *  control whether corresponding key can only be deployed once. 1 is true, 0 is false.
+         *  bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+         */
+        uint32_t km_deploy_only_once_h:1;
+        /** force_use_key_manager_key_h : RO; bitpos: [23]; default: 0;
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form
+         *  one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H,
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether
+         *  corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda,
+         *  bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+         */
+        uint32_t force_use_key_manager_key_h:1;
+        uint32_t reserved_24:2;
+        /** flash_ecc_en : RO; bitpos: [26]; default: 0;
+         *  Set this bit to enable ECC for flash boot.
+         */
+        uint32_t flash_ecc_en:1;
+        /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0;
+         *  Set this bit to disable download via USB-OTG.
+         */
+        uint32_t dis_usb_otg_download_mode:1;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Configures flash waiting time after power-up, in unit of ms. When the value less
+         *  than 15, the waiting time is the configurable value. Otherwise, the waiting time is
+         *  30.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Set this bit to disable direct boot mode
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Set this bit to disable USB-Serial-JTAG print during rom boot.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** lock_km_key : RO; bitpos: [3]; default: 0;
+         *  set this bit to lock the key manager key after deploy
+         */
+        uint32_t lock_km_key:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Set this bit to disable the USB-Serial-JTAG download function.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Set this bit to enable security download mode.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Set the type of UART printing, 00: force enable printing, 01: enable printing when
+         *  GPIO8 is reset at low level, 10: enable printing when GPIO8 is reset at high level,
+         *  11: force disable printing
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [8]; default: 0;
+         *  Set this bit to force ROM code to send a resume command during SPI boot.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [24:9]; default: 0;
+         *  Secure version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
+         *  Represents whether secure boot do fast verification on wake is disabled. 0: enabled
+         *  1: disabled
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** hys_en_pad : RO; bitpos: [26]; default: 0;
+         *  Set bits to enable hysteresis function of PAD0~27
+         */
+        uint32_t hys_en_pad:1;
+        /** key_purpose_0_h : RO; bitpos: [27]; default: 0;
+         *  Purpose of Key0. The 5-th bit.
+         */
+        uint32_t key_purpose_0_h:1;
+        /** key_purpose_1_h : RO; bitpos: [28]; default: 0;
+         *  Purpose of Key1. The 5-th bit.
+         */
+        uint32_t key_purpose_1_h:1;
+        /** key_purpose_2_h : RO; bitpos: [29]; default: 0;
+         *  Purpose of Key2. The 5-th bit.
+         */
+        uint32_t key_purpose_2_h:1;
+        /** key_purpose_3_h : RO; bitpos: [30]; default: 0;
+         *  Purpose of Key3. The 5-th bit.
+         */
+        uint32_t key_purpose_3_h:1;
+        /** key_purpose_4_h : RO; bitpos: [31]; default: 0;
+         *  Purpose of Key4. The 5-th bit.
+         */
+        uint32_t key_purpose_4_h:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
+         *  Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0
+         */
+        uint32_t pxa0_tieh_sel_0:2;
+        /** pvt_glitch_en : RO; bitpos: [2]; default: 0;
+         *  Represents whether to enable PVT power glitch monitor function.
+         *  1:Enable.
+         *  0:Disable
+         */
+        uint32_t pvt_glitch_en:1;
+        uint32_t reserved_3:1;
+        /** key_purpose_5_h : RO; bitpos: [4]; default: 0;
+         *  Purpose of Key5. The 5-th bit.
+         */
+        uint32_t key_purpose_5_h:1;
+        uint32_t reserved_5:2;
+        /** km_disable_deploy_mode_h : RO; bitpos: [7]; default: 0;
+         *  EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one
+         *  field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set
+         *  each bit to control whether corresponding key's deploy mode of new value deployment
+         *  is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds,
+         *  bit4:psram
+         */
+        uint32_t km_disable_deploy_mode_h:1;
+        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
+         *  EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one
+         *  field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set
+         *  each bit to control whether corresponding key's deploy mode of new value deployment
+         *  is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds,
+         *  bit4:psram
+         */
+        uint32_t km_disable_deploy_mode:4;
+        uint32_t reserved_12:4;
+        /** xts_dpa_pseudo_level : RO; bitpos: [17:16]; default: 0;
+         *  Sets this bit to control the xts pseudo-round anti-dpa attack function. 0:
+         *  controlled by register. 1-3: the higher the value is, the more pseudo-rounds are
+         *  inserted to the xts-aes calculation
+         */
+        uint32_t xts_dpa_pseudo_level:2;
+        /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
+         *  HP system power source select. 0:LDO  1: DCDC
+         */
+        uint32_t hp_pwr_src_sel:1;
+        /** secure_boot_sha384_en : RO; bitpos: [19]; default: 0;
+         *  Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable
+         */
+        uint32_t secure_boot_sha384_en:1;
+        /** dis_wdt : RO; bitpos: [20]; default: 0;
+         *  Set this bit to disable watch dog.
+         */
+        uint32_t dis_wdt:1;
+        /** dis_swd : RO; bitpos: [21]; default: 0;
+         *  Set bit to disable super-watchdog
+         */
+        uint32_t dis_swd:1;
+        /** pvt_glitch_mode : RO; bitpos: [23:22]; default: 0;
+         *  Use to configure glitch mode
+         */
+        uint32_t pvt_glitch_mode:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+
+/** Group: block1 registers */
+/** Type of rd_mac_sys0 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents MAC address. Low 32-bit.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys0_reg_t;
+
+/** Type of rd_mac_sys1 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Represents MAC address. High 16-bit.
+         */
+        uint32_t mac_1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys1_reg_t;
+
+/** Type of rd_mac_sys3 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:18;
+        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
+         *  Represents the first 14-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_0:14;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys3_reg_t;
+
+/** Type of rd_mac_sys4 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the second 32-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_1:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys4_reg_t;
+
+/** Type of rd_mac_sys5 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the third 32-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_2:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys5_reg_t;
+
+
+/** Group: block2 registers */
+/** Type of rd_sys_part1_datan register
+ *  Represents rd_sys_part1_datan
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of first part of system data.
+         */
+        uint32_t sys_data_part1_n:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_datan_reg_t;
+
+
+/** Group: block3 registers */
+/** Type of rd_usr_datan register
+ *  Represents rd_usr_datan
+ */
+typedef union {
+    struct {
+        /** usr_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_datan_reg_t;
+
+
+/** Group: block4 registers */
+/** Type of rd_key0_datan register
+ *  Represents rd_key0_datan
+ */
+typedef union {
+    struct {
+        /** key0_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_datan_reg_t;
+
+
+/** Group: block5 registers */
+/** Type of rd_key1_datan register
+ *  Represents rd_key1_datan
+ */
+typedef union {
+    struct {
+        /** key1_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_datan_reg_t;
+
+
+/** Group: block6 registers */
+/** Type of rd_key2_datan register
+ *  Represents rd_key2_datan
+ */
+typedef union {
+    struct {
+        /** key2_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_datan_reg_t;
+
+
+/** Group: block7 registers */
+/** Type of rd_key3_datan register
+ *  Represents rd_key3_datan
+ */
+typedef union {
+    struct {
+        /** key3_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_datan_reg_t;
+
+
+/** Group: block8 registers */
+/** Type of rd_key4_datan register
+ *  Represents rd_key4_datan
+ */
+typedef union {
+    struct {
+        /** key4_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_datan_reg_t;
+
+
+/** Group: block9 registers */
+/** Type of rd_key5_datan register
+ *  Represents rd_key5_datan
+ */
+typedef union {
+    struct {
+        /** key5_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_datan_reg_t;
+
+
+/** Group: block10 registers */
+/** Type of rd_sys_part2_data0 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the first 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the first 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the second 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the third 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the fourth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the fifth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** usb_device_exchg_pins : RO; bitpos: [4]; default: 0;
+         *  Enable usb device exchange pins of D+ and D-.
+         */
+        uint32_t usb_device_exchg_pins:1;
+        /** usb_otg11_exchg_pins : RO; bitpos: [5]; default: 0;
+         *  Enable usb otg11 exchange pins of D+ and D-.
+         */
+        uint32_t usb_otg11_exchg_pins:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+
+/** Group: block0 error report registers */
+/** Type of rd_repeat_data_err0 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Represents the programming error of EFUSE_RD_DIS
+         */
+        uint32_t rd_dis_err:7;
+        /** recovery_bootloader_flash_sector_0_1_err : RO; bitpos: [8:7]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1
+         */
+        uint32_t recovery_bootloader_flash_sector_0_1_err:2;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_JTAG
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** recovery_bootloader_flash_sector_2_2_err : RO; bitpos: [10]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2
+         */
+        uint32_t recovery_bootloader_flash_sector_2_2_err:1;
+        uint32_t reserved_11:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
+         *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_TWAI
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_PAD_JTAG
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** recovery_bootloader_flash_sector_3_6_err : RO; bitpos: [24:21]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6
+         */
+        uint32_t recovery_bootloader_flash_sector_3_6_err:4;
+        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
+         *  Represents the programming error of EFUSE_USB_PHY_SEL
+         */
+        uint32_t usb_phy_sel_err:1;
+        /** huk_gen_state_err : RO; bitpos: [30:26]; default: 0;
+         *  Represents the programming error of EFUSE_HUK_GEN_STATE
+         */
+        uint32_t huk_gen_state_err:5;
+        /** recovery_bootloader_flash_sector_7_7_err : RO; bitpos: [31]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7
+         */
+        uint32_t recovery_bootloader_flash_sector_7_7_err:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err0_reg_t;
+
+/** Type of rd_repeat_data_err1 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** recovery_bootloader_flash_sector_8_10_err : RO; bitpos: [2:0]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10
+         */
+        uint32_t recovery_bootloader_flash_sector_8_10_err:3;
+        /** recovery_bootloader_flash_sector_11_11_err : RO; bitpos: [3]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11
+         */
+        uint32_t recovery_bootloader_flash_sector_11_11_err:1;
+        /** km_rnd_switch_cycle_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
+         */
+        uint32_t km_rnd_switch_cycle_err:1;
+        /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
+         */
+        uint32_t km_deploy_only_once_err:4;
+        /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
+         */
+        uint32_t force_use_key_manager_key_err:4;
+        /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
+         */
+        uint32_t force_disable_sw_init_key_err:1;
+        /** km_xts_key_length_256_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
+         */
+        uint32_t km_xts_key_length_256_err:1;
+        /** ecc_force_const_time_err : RO; bitpos: [15]; default: 0;
+         *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
+         */
+        uint32_t ecc_force_const_time_err:1;
+        uint32_t reserved_16:1;
+        /** wdt_delay_sel_err : RO; bitpos: [17]; default: 0;
+         *  Represents the programming error of EFUSE_WDT_DELAY_SEL
+         */
+        uint32_t wdt_delay_sel_err:1;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_0
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_1
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err1_reg_t;
+
+/** Type of rd_repeat_data_err2 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_2
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_3
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_4
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_5
+         */
+        uint32_t key_purpose_5_err:4;
+        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
+         */
+        uint32_t sec_dpa_level_err:2;
+        uint32_t reserved_18:1;
+        /** xts_dpa_clk_enable_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
+         */
+        uint32_t xts_dpa_clk_enable_err:1;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_EN
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        /** km_deploy_only_once_h_err : RO; bitpos: [22]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE_H
+         */
+        uint32_t km_deploy_only_once_h_err:1;
+        /** force_use_key_manager_key_h_err : RO; bitpos: [23]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY_H
+         */
+        uint32_t force_use_key_manager_key_h_err:1;
+        uint32_t reserved_24:2;
+        /** flash_ecc_en_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_FLASH_ECC_EN
+         */
+        uint32_t flash_ecc_en_err:1;
+        /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_OTG_DOWNLOAD_MODE
+         */
+        uint32_t dis_usb_otg_download_mode_err:1;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  Represents the programming error of EFUSE_FLASH_TPUW
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err2_reg_t;
+
+/** Type of rd_repeat_data_err3 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
+         */
+        uint32_t dis_usb_serial_jtag_rom_print_err:1;
+        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
+         *  Represents the programming error of EFUSE_LOCK_KM_KEY
+         */
+        uint32_t lock_km_key_err:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_VERSION
+         */
+        uint32_t secure_version_err:16;
+        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
+         */
+        uint32_t secure_boot_disable_fast_wake_err:1;
+        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_HYS_EN_PAD
+         */
+        uint32_t hys_en_pad_err:1;
+        /** key_purpose_0_h_err : RO; bitpos: [27]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_0_H
+         */
+        uint32_t key_purpose_0_h_err:1;
+        /** key_purpose_1_h_err : RO; bitpos: [28]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_1_H
+         */
+        uint32_t key_purpose_1_h_err:1;
+        /** key_purpose_2_h_err : RO; bitpos: [29]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_2_H
+         */
+        uint32_t key_purpose_2_h_err:1;
+        /** key_purpose_3_h_err : RO; bitpos: [30]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_3_H
+         */
+        uint32_t key_purpose_3_h_err:1;
+        /** key_purpose_4_h_err : RO; bitpos: [31]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_4_H
+         */
+        uint32_t key_purpose_4_h_err:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err3_reg_t;
+
+/** Type of rd_repeat_data_err4 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
+         *  Represents the programming error of 0PXA_TIEH_SEL_0
+         */
+        uint32_t pxa0_tieh_sel_0_err:2;
+        /** pvt_glitch_en_err : RO; bitpos: [2]; default: 0;
+         *  Represents the programming error of EFUSE_PVT_GLITCH_EN
+         */
+        uint32_t pvt_glitch_en_err:1;
+        uint32_t reserved_3:1;
+        /** key_purpose_5_h_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_5_H
+         */
+        uint32_t key_purpose_5_h_err:1;
+        uint32_t reserved_5:2;
+        /** km_disable_deploy_mode_h_err : RO; bitpos: [7]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE_H
+         */
+        uint32_t km_disable_deploy_mode_h_err:1;
+        /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
+         */
+        uint32_t km_disable_deploy_mode_err:4;
+        uint32_t reserved_12:4;
+        /** xts_dpa_pseudo_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
+         */
+        uint32_t xts_dpa_pseudo_level_err:2;
+        /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0;
+         *  Represents the programming error of EFUSE_HP_PWR_SRC_SEL
+         */
+        uint32_t hp_pwr_src_sel_err:1;
+        /** secure_boot_sha384_en_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN
+         */
+        uint32_t secure_boot_sha384_en_err:1;
+        /** dis_wdt_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_WDT
+         */
+        uint32_t dis_wdt_err:1;
+        /** dis_swd_err : RO; bitpos: [21]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_SWD
+         */
+        uint32_t dis_swd_err:1;
+        /** pvt_glitch_mode_err : RO; bitpos: [23:22]; default: 0;
+         *  Represents the programming error of EFUSE_PVT_GLITCH_MODE
+         */
+        uint32_t pvt_glitch_mode_err:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err4_reg_t;
+
+
+/** Group: EFUSE ECDSA Configure Registers */
+/** Type of ecdsa register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** cfg_ecdsa_p192_blk : R/W; bitpos: [3:0]; default: 0;
+         *  Configures which block to use for ECDSA P192 key output.
+         */
+        uint32_t cfg_ecdsa_p192_blk:4;
+        /** cfg_ecdsa_p256_blk : R/W; bitpos: [7:4]; default: 0;
+         *  Configures which block to use for ECDSA P256 key output.
+         */
+        uint32_t cfg_ecdsa_p256_blk:4;
+        /** cfg_ecdsa_p384_l_blk : R/W; bitpos: [11:8]; default: 0;
+         *  Configures which block to use for ECDSA P384 key low part output.
+         */
+        uint32_t cfg_ecdsa_p384_l_blk:4;
+        /** cfg_ecdsa_p384_h_blk : R/W; bitpos: [15:12]; default: 0;
+         *  Configures which block to use for ECDSA P256 key high part output.
+         */
+        uint32_t cfg_ecdsa_p384_h_blk:4;
+        /** cur_ecdsa_p192_blk : RO; bitpos: [19:16]; default: 0;
+         *  Represents which block is used for ECDSA P192 key output.
+         */
+        uint32_t cur_ecdsa_p192_blk:4;
+        /** cur_ecdsa_p256_blk : RO; bitpos: [23:20]; default: 0;
+         *  Represents which block is used for ECDSA P256 key output.
+         */
+        uint32_t cur_ecdsa_p256_blk:4;
+        /** cur_ecdsa_p384_l_blk : RO; bitpos: [27:24]; default: 0;
+         *  Represents which block is used for ECDSA P384 key low part output.
+         */
+        uint32_t cur_ecdsa_p384_l_blk:4;
+        /** cur_ecdsa_p384_h_blk : RO; bitpos: [31:28]; default: 0;
+         *  Represents which block is used for ECDSA P384 key high part output.
+         */
+        uint32_t cur_ecdsa_p384_h_blk:4;
+    };
+    uint32_t val;
+} efuse_ecdsa_reg_t;
+
+
+/** Group: RS block error report registers */
+/** Type of rd_rs_data_err0 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_mac_sys
+         */
+        uint32_t rd_mac_sys_err_num:3;
+        /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_mac_sys is reliable
+         *  1: Means that programming rd_mac_sys failed and the number of error bytes is over 6.
+         */
+        uint32_t rd_mac_sys_fail:1;
+        /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_sys_part1_data
+         */
+        uint32_t rd_sys_part1_data_err_num:3;
+        /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_sys_part1_data is reliable
+         *  1: Means that programming rd_sys_part1_data failed and the number of error bytes is
+         *  over 6.
+         */
+        uint32_t rd_sys_part1_data_fail:1;
+        /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_usr_data
+         */
+        uint32_t rd_usr_data_err_num:3;
+        /** rd_usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_usr_data is reliable
+         *  1: Means that programming rd_usr_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_usr_data_fail:1;
+        /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key0_data
+         */
+        uint32_t rd_key0_data_err_num:3;
+        /** rd_key0_data_fail : RO; bitpos: [15]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key0_data is reliable
+         *  1: Means that programming rd_key0_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key0_data_fail:1;
+        /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key1_data
+         */
+        uint32_t rd_key1_data_err_num:3;
+        /** rd_key1_data_fail : RO; bitpos: [19]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key1_data is reliable
+         *  1: Means that programming rd_key1_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key1_data_fail:1;
+        /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key2_data
+         */
+        uint32_t rd_key2_data_err_num:3;
+        /** rd_key2_data_fail : RO; bitpos: [23]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key2_data is reliable
+         *  1: Means that programming rd_key2_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key2_data_fail:1;
+        /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key3_data
+         */
+        uint32_t rd_key3_data_err_num:3;
+        /** rd_key3_data_fail : RO; bitpos: [27]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key3_data is reliable
+         *  1: Means that programming rd_key3_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key3_data_fail:1;
+        /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key4_data
+         */
+        uint32_t rd_key4_data_err_num:3;
+        /** rd_key4_data_fail : RO; bitpos: [31]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key4_data is reliable
+         *  1: Means that programming rd_key4_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key4_data_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err0_reg_t;
+
+/** Type of rd_rs_data_err1 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key5_data
+         */
+        uint32_t rd_key5_data_err_num:3;
+        /** rd_key5_data_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key5_data is reliable
+         *  1: Means that programming rd_key5_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key5_data_fail:1;
+        /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_sys_part2_data
+         */
+        uint32_t rd_sys_part2_data_err_num:3;
+        /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_sys_part2_data is reliable
+         *  1: Means that programming rd_sys_part2_data failed and the number of error bytes is
+         *  over 6.
+         */
+        uint32_t rd_sys_part2_data_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err1_reg_t;
+
+
+/** Group: ******** Registers */
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to force enable eFuse register configuration clock signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+         */
+        uint32_t op_code:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        uint32_t reserved_4:6;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
+         *  Configures the waiting time of reading eFuse memory.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 160;
+         *  Configures the active programming time.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to bypass reed solomon correction step.
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures block number of programming twice operation.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Set this bit to update multi-bit register signals.
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: EFUSE Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38805904;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
+/** Type of apb2otp_wr_dis register
+ *  eFuse apb2otp block0 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 write disable data.
+         */
+        uint32_t apb2otp_block0_wr_dis:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_wr_dis_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
+/** Type of apb2otp_blk0_backup1_w1 register
+ *  eFuse apb2otp block0 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word1 data.
+         */
+        uint32_t apb2otp_block0_backup1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
+/** Type of apb2otp_blk0_backup1_w2 register
+ *  eFuse apb2otp block0 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word2 data.
+         */
+        uint32_t apb2otp_block0_backup1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
+/** Type of apb2otp_blk0_backup1_w3 register
+ *  eFuse apb2otp block0 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word3 data.
+         */
+        uint32_t apb2otp_block0_backup1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
+/** Type of apb2otp_blk0_backup1_w4 register
+ *  eFuse apb2otp block0 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word4 data.
+         */
+        uint32_t apb2otp_block0_backup1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
+/** Type of apb2otp_blk0_backup1_w5 register
+ *  eFuse apb2otp block0 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word5 data.
+         */
+        uint32_t apb2otp_block0_backup1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
+/** Type of apb2otp_blk0_backup2_w1 register
+ *  eFuse apb2otp block0 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word1 data.
+         */
+        uint32_t apb2otp_block0_backup2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
+/** Type of apb2otp_blk0_backup2_w2 register
+ *  eFuse apb2otp block0 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word2 data.
+         */
+        uint32_t apb2otp_block0_backup2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
+/** Type of apb2otp_blk0_backup2_w3 register
+ *  eFuse apb2otp block0 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word3 data.
+         */
+        uint32_t apb2otp_block0_backup2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
+/** Type of apb2otp_blk0_backup2_w4 register
+ *  eFuse apb2otp block0 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word4 data.
+         */
+        uint32_t apb2otp_block0_backup2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
+/** Type of apb2otp_blk0_backup2_w5 register
+ *  eFuse apb2otp block0 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word5 data.
+         */
+        uint32_t apb2otp_block0_backup2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
+/** Type of apb2otp_blk0_backup3_w1 register
+ *  eFuse apb2otp block0 data register12.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word1 data.
+         */
+        uint32_t apb2otp_block0_backup3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
+/** Type of apb2otp_blk0_backup3_w2 register
+ *  eFuse apb2otp block0 data register13.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word2 data.
+         */
+        uint32_t apb2otp_block0_backup3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
+/** Type of apb2otp_blk0_backup3_w3 register
+ *  eFuse apb2otp block0 data register14.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word3 data.
+         */
+        uint32_t apb2otp_block0_backup3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
+/** Type of apb2otp_blk0_backup3_w4 register
+ *  eFuse apb2otp block0 data register15.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word4 data.
+         */
+        uint32_t apb2otp_block0_backup3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
+/** Type of apb2otp_blk0_backup3_w5 register
+ *  eFuse apb2otp block0 data register16.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word5 data.
+         */
+        uint32_t apb2otp_block0_backup3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
+/** Type of apb2otp_blk0_backup4_w1 register
+ *  eFuse apb2otp block0 data register17.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word1 data.
+         */
+        uint32_t apb2otp_block0_backup4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
+/** Type of apb2otp_blk0_backup4_w2 register
+ *  eFuse apb2otp block0 data register18.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word2 data.
+         */
+        uint32_t apb2otp_block0_backup4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
+/** Type of apb2otp_blk0_backup4_w3 register
+ *  eFuse apb2otp block0 data register19.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word3 data.
+         */
+        uint32_t apb2otp_block0_backup4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
+/** Type of apb2otp_blk0_backup4_w4 register
+ *  eFuse apb2otp block0 data register20.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word4 data.
+         */
+        uint32_t apb2otp_block0_backup4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
+/** Type of apb2otp_blk0_backup4_w5 register
+ *  eFuse apb2otp block0 data register21.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word5 data.
+         */
+        uint32_t apb2otp_block0_backup4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word1 Data */
+/** Type of apb2otp_blk1_w1 register
+ *  eFuse apb2otp block1 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word1 data.
+         */
+        uint32_t apb2otp_block1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word2 Data */
+/** Type of apb2otp_blk1_w2 register
+ *  eFuse apb2otp block1 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word2 data.
+         */
+        uint32_t apb2otp_block1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word3 Data */
+/** Type of apb2otp_blk1_w3 register
+ *  eFuse apb2otp block1 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word3 data.
+         */
+        uint32_t apb2otp_block1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word4 Data */
+/** Type of apb2otp_blk1_w4 register
+ *  eFuse apb2otp block1 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word4 data.
+         */
+        uint32_t apb2otp_block1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word5 Data */
+/** Type of apb2otp_blk1_w5 register
+ *  eFuse apb2otp block1 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word5 data.
+         */
+        uint32_t apb2otp_block1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word6 Data */
+/** Type of apb2otp_blk1_w6 register
+ *  eFuse apb2otp block1 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word6 data.
+         */
+        uint32_t apb2otp_block1_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word7 Data */
+/** Type of apb2otp_blk1_w7 register
+ *  eFuse apb2otp block1 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word7 data.
+         */
+        uint32_t apb2otp_block1_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word8 Data */
+/** Type of apb2otp_blk1_w8 register
+ *  eFuse apb2otp block1 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word8 data.
+         */
+        uint32_t apb2otp_block1_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word9 Data */
+/** Type of apb2otp_blk1_w9 register
+ *  eFuse apb2otp block1 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word9 data.
+         */
+        uint32_t apb2otp_block1_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word1 Data */
+/** Type of apb2otp_blk2_w1 register
+ *  eFuse apb2otp block2 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word1 data.
+         */
+        uint32_t apb2otp_block2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word2 Data */
+/** Type of apb2otp_blk2_w2 register
+ *  eFuse apb2otp block2 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word2 data.
+         */
+        uint32_t apb2otp_block2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word3 Data */
+/** Type of apb2otp_blk2_w3 register
+ *  eFuse apb2otp block2 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word3 data.
+         */
+        uint32_t apb2otp_block2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word4 Data */
+/** Type of apb2otp_blk2_w4 register
+ *  eFuse apb2otp block2 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word4 data.
+         */
+        uint32_t apb2otp_block2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word5 Data */
+/** Type of apb2otp_blk2_w5 register
+ *  eFuse apb2otp block2 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word5 data.
+         */
+        uint32_t apb2otp_block2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word6 Data */
+/** Type of apb2otp_blk2_w6 register
+ *  eFuse apb2otp block2 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word6 data.
+         */
+        uint32_t apb2otp_block2_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word7 Data */
+/** Type of apb2otp_blk2_w7 register
+ *  eFuse apb2otp block2 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word7 data.
+         */
+        uint32_t apb2otp_block2_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word8 Data */
+/** Type of apb2otp_blk2_w8 register
+ *  eFuse apb2otp block2 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word8 data.
+         */
+        uint32_t apb2otp_block2_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word9 Data */
+/** Type of apb2otp_blk2_w9 register
+ *  eFuse apb2otp block2 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word9 data.
+         */
+        uint32_t apb2otp_block2_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word10 Data */
+/** Type of apb2otp_blk2_w10 register
+ *  eFuse apb2otp block2 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word10 data.
+         */
+        uint32_t apb2otp_block2_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word11 Data */
+/** Type of apb2otp_blk2_w11 register
+ *  eFuse apb2otp block2 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word11 data.
+         */
+        uint32_t apb2otp_block2_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w11_reg_t;
+
+/** Type of apb2otp_blk10_w11 register
+ *  eFuse apb2otp block10 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word11 data.
+         */
+        uint32_t apb2otp_block10_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word1 Data */
+/** Type of apb2otp_blk3_w1 register
+ *  eFuse apb2otp block3 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word1 data.
+         */
+        uint32_t apb2otp_block3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word2 Data */
+/** Type of apb2otp_blk3_w2 register
+ *  eFuse apb2otp block3 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word2 data.
+         */
+        uint32_t apb2otp_block3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word3 Data */
+/** Type of apb2otp_blk3_w3 register
+ *  eFuse apb2otp block3 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word3 data.
+         */
+        uint32_t apb2otp_block3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word4 Data */
+/** Type of apb2otp_blk3_w4 register
+ *  eFuse apb2otp block3 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word4 data.
+         */
+        uint32_t apb2otp_block3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word5 Data */
+/** Type of apb2otp_blk3_w5 register
+ *  eFuse apb2otp block3 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word5 data.
+         */
+        uint32_t apb2otp_block3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word6 Data */
+/** Type of apb2otp_blk3_w6 register
+ *  eFuse apb2otp block3 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word6 data.
+         */
+        uint32_t apb2otp_block3_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word7 Data */
+/** Type of apb2otp_blk3_w7 register
+ *  eFuse apb2otp block3 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word7 data.
+         */
+        uint32_t apb2otp_block3_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word8 Data */
+/** Type of apb2otp_blk3_w8 register
+ *  eFuse apb2otp block3 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word8 data.
+         */
+        uint32_t apb2otp_block3_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word9 Data */
+/** Type of apb2otp_blk3_w9 register
+ *  eFuse apb2otp block3 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word9 data.
+         */
+        uint32_t apb2otp_block3_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word10 Data */
+/** Type of apb2otp_blk3_w10 register
+ *  eFuse apb2otp block3 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word10 data.
+         */
+        uint32_t apb2otp_block3_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word11 Data */
+/** Type of apb2otp_blk3_w11 register
+ *  eFuse apb2otp block3 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word11 data.
+         */
+        uint32_t apb2otp_block3_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word1 Data */
+/** Type of apb2otp_blk4_w1 register
+ *  eFuse apb2otp block4 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word1 data.
+         */
+        uint32_t apb2otp_block4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word2 Data */
+/** Type of apb2otp_blk4_w2 register
+ *  eFuse apb2otp block4 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word2 data.
+         */
+        uint32_t apb2otp_block4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word3 Data */
+/** Type of apb2otp_blk4_w3 register
+ *  eFuse apb2otp block4 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word3 data.
+         */
+        uint32_t apb2otp_block4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word4 Data */
+/** Type of apb2otp_blk4_w4 register
+ *  eFuse apb2otp block4 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word4 data.
+         */
+        uint32_t apb2otp_block4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word5 Data */
+/** Type of apb2otp_blk4_w5 register
+ *  eFuse apb2otp block4 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word5 data.
+         */
+        uint32_t apb2otp_block4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word6 Data */
+/** Type of apb2otp_blk4_w6 register
+ *  eFuse apb2otp block4 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word6 data.
+         */
+        uint32_t apb2otp_block4_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word7 Data */
+/** Type of apb2otp_blk4_w7 register
+ *  eFuse apb2otp block4 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word7 data.
+         */
+        uint32_t apb2otp_block4_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word8 Data */
+/** Type of apb2otp_blk4_w8 register
+ *  eFuse apb2otp block4 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word8 data.
+         */
+        uint32_t apb2otp_block4_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word9 Data */
+/** Type of apb2otp_blk4_w9 register
+ *  eFuse apb2otp block4 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word9 data.
+         */
+        uint32_t apb2otp_block4_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word10 Data */
+/** Type of apb2otp_blk4_w10 register
+ *  eFuse apb2otp block4 data registe10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word10 data.
+         */
+        uint32_t apb2otp_block4_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word11 Data */
+/** Type of apb2otp_blk4_w11 register
+ *  eFuse apb2otp block4 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word11 data.
+         */
+        uint32_t apb2otp_block4_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word1 Data */
+/** Type of apb2otp_blk5_w1 register
+ *  eFuse apb2otp block5 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word1 data.
+         */
+        uint32_t apb2otp_block5_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word2 Data */
+/** Type of apb2otp_blk5_w2 register
+ *  eFuse apb2otp block5 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word2 data.
+         */
+        uint32_t apb2otp_block5_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word3 Data */
+/** Type of apb2otp_blk5_w3 register
+ *  eFuse apb2otp block5 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word3 data.
+         */
+        uint32_t apb2otp_block5_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word4 Data */
+/** Type of apb2otp_blk5_w4 register
+ *  eFuse apb2otp block5 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word4 data.
+         */
+        uint32_t apb2otp_block5_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word5 Data */
+/** Type of apb2otp_blk5_w5 register
+ *  eFuse apb2otp block5 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word5 data.
+         */
+        uint32_t apb2otp_block5_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word6 Data */
+/** Type of apb2otp_blk5_w6 register
+ *  eFuse apb2otp block5 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word6 data.
+         */
+        uint32_t apb2otp_block5_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word7 Data */
+/** Type of apb2otp_blk5_w7 register
+ *  eFuse apb2otp block5 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word7 data.
+         */
+        uint32_t apb2otp_block5_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word8 Data */
+/** Type of apb2otp_blk5_w8 register
+ *  eFuse apb2otp block5 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word8 data.
+         */
+        uint32_t apb2otp_block5_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word9 Data */
+/** Type of apb2otp_blk5_w9 register
+ *  eFuse apb2otp block5 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word9 data.
+         */
+        uint32_t apb2otp_block5_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word10 Data */
+/** Type of apb2otp_blk5_w10 register
+ *  eFuse apb2otp block5 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word10 data.
+         */
+        uint32_t apb2otp_block5_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word11 Data */
+/** Type of apb2otp_blk5_w11 register
+ *  eFuse apb2otp block5 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word11 data.
+         */
+        uint32_t apb2otp_block5_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word1 Data */
+/** Type of apb2otp_blk6_w1 register
+ *  eFuse apb2otp block6 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word1 data.
+         */
+        uint32_t apb2otp_block6_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word2 Data */
+/** Type of apb2otp_blk6_w2 register
+ *  eFuse apb2otp block6 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word2 data.
+         */
+        uint32_t apb2otp_block6_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word3 Data */
+/** Type of apb2otp_blk6_w3 register
+ *  eFuse apb2otp block6 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word3 data.
+         */
+        uint32_t apb2otp_block6_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word4 Data */
+/** Type of apb2otp_blk6_w4 register
+ *  eFuse apb2otp block6 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word4 data.
+         */
+        uint32_t apb2otp_block6_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word5 Data */
+/** Type of apb2otp_blk6_w5 register
+ *  eFuse apb2otp block6 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word5 data.
+         */
+        uint32_t apb2otp_block6_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word6 Data */
+/** Type of apb2otp_blk6_w6 register
+ *  eFuse apb2otp block6 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word6 data.
+         */
+        uint32_t apb2otp_block6_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word7 Data */
+/** Type of apb2otp_blk6_w7 register
+ *  eFuse apb2otp block6 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word7 data.
+         */
+        uint32_t apb2otp_block6_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word8 Data */
+/** Type of apb2otp_blk6_w8 register
+ *  eFuse apb2otp block6 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word8 data.
+         */
+        uint32_t apb2otp_block6_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word9 Data */
+/** Type of apb2otp_blk6_w9 register
+ *  eFuse apb2otp block6 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word9 data.
+         */
+        uint32_t apb2otp_block6_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word10 Data */
+/** Type of apb2otp_blk6_w10 register
+ *  eFuse apb2otp block6 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word10 data.
+         */
+        uint32_t apb2otp_block6_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word11 Data */
+/** Type of apb2otp_blk6_w11 register
+ *  eFuse apb2otp block6 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word11 data.
+         */
+        uint32_t apb2otp_block6_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word1 Data */
+/** Type of apb2otp_blk7_w1 register
+ *  eFuse apb2otp block7 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word1 data.
+         */
+        uint32_t apb2otp_block7_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word2 Data */
+/** Type of apb2otp_blk7_w2 register
+ *  eFuse apb2otp block7 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word2 data.
+         */
+        uint32_t apb2otp_block7_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word3 Data */
+/** Type of apb2otp_blk7_w3 register
+ *  eFuse apb2otp block7 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word3 data.
+         */
+        uint32_t apb2otp_block7_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word4 Data */
+/** Type of apb2otp_blk7_w4 register
+ *  eFuse apb2otp block7 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word4 data.
+         */
+        uint32_t apb2otp_block7_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word5 Data */
+/** Type of apb2otp_blk7_w5 register
+ *  eFuse apb2otp block7 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word5 data.
+         */
+        uint32_t apb2otp_block7_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word6 Data */
+/** Type of apb2otp_blk7_w6 register
+ *  eFuse apb2otp block7 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word6 data.
+         */
+        uint32_t apb2otp_block7_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word7 Data */
+/** Type of apb2otp_blk7_w7 register
+ *  eFuse apb2otp block7 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word7 data.
+         */
+        uint32_t apb2otp_block7_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word8 Data */
+/** Type of apb2otp_blk7_w8 register
+ *  eFuse apb2otp block7 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word8 data.
+         */
+        uint32_t apb2otp_block7_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word9 Data */
+/** Type of apb2otp_blk7_w9 register
+ *  eFuse apb2otp block7 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word9 data.
+         */
+        uint32_t apb2otp_block7_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word10 Data */
+/** Type of apb2otp_blk7_w10 register
+ *  eFuse apb2otp block7 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word10 data.
+         */
+        uint32_t apb2otp_block7_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word11 Data */
+/** Type of apb2otp_blk7_w11 register
+ *  eFuse apb2otp block7 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word11 data.
+         */
+        uint32_t apb2otp_block7_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word1 Data */
+/** Type of apb2otp_blk8_w1 register
+ *  eFuse apb2otp block8 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word1 data.
+         */
+        uint32_t apb2otp_block8_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word2 Data */
+/** Type of apb2otp_blk8_w2 register
+ *  eFuse apb2otp block8 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word2 data.
+         */
+        uint32_t apb2otp_block8_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word3 Data */
+/** Type of apb2otp_blk8_w3 register
+ *  eFuse apb2otp block8 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word3 data.
+         */
+        uint32_t apb2otp_block8_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word4 Data */
+/** Type of apb2otp_blk8_w4 register
+ *  eFuse apb2otp block8 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word4 data.
+         */
+        uint32_t apb2otp_block8_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word5 Data */
+/** Type of apb2otp_blk8_w5 register
+ *  eFuse apb2otp block8 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word5 data.
+         */
+        uint32_t apb2otp_block8_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word6 Data */
+/** Type of apb2otp_blk8_w6 register
+ *  eFuse apb2otp block8 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word6 data.
+         */
+        uint32_t apb2otp_block8_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word7 Data */
+/** Type of apb2otp_blk8_w7 register
+ *  eFuse apb2otp block8 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word7 data.
+         */
+        uint32_t apb2otp_block8_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word8 Data */
+/** Type of apb2otp_blk8_w8 register
+ *  eFuse apb2otp block8 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word8 data.
+         */
+        uint32_t apb2otp_block8_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word9 Data */
+/** Type of apb2otp_blk8_w9 register
+ *  eFuse apb2otp block8 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word9 data.
+         */
+        uint32_t apb2otp_block8_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word10 Data */
+/** Type of apb2otp_blk8_w10 register
+ *  eFuse apb2otp block8 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word10 data.
+         */
+        uint32_t apb2otp_block8_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word11 Data */
+/** Type of apb2otp_blk8_w11 register
+ *  eFuse apb2otp block8 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word11 data.
+         */
+        uint32_t apb2otp_block8_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word1 Data */
+/** Type of apb2otp_blk9_w1 register
+ *  eFuse apb2otp block9 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word1 data.
+         */
+        uint32_t apb2otp_block9_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word2 Data */
+/** Type of apb2otp_blk9_w2 register
+ *  eFuse apb2otp block9 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word2 data.
+         */
+        uint32_t apb2otp_block9_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word3 Data */
+/** Type of apb2otp_blk9_w3 register
+ *  eFuse apb2otp block9 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word3 data.
+         */
+        uint32_t apb2otp_block9_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word4 Data */
+/** Type of apb2otp_blk9_w4 register
+ *  eFuse apb2otp block9 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word4 data.
+         */
+        uint32_t apb2otp_block9_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word5 Data */
+/** Type of apb2otp_blk9_w5 register
+ *  eFuse apb2otp block9 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word5 data.
+         */
+        uint32_t apb2otp_block9_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word6 Data */
+/** Type of apb2otp_blk9_w6 register
+ *  eFuse apb2otp block9 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word6 data.
+         */
+        uint32_t apb2otp_block9_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word7 Data */
+/** Type of apb2otp_blk9_w7 register
+ *  eFuse apb2otp block9 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word7 data.
+         */
+        uint32_t apb2otp_block9_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word8 Data */
+/** Type of apb2otp_blk9_w8 register
+ *  eFuse apb2otp block9 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word8 data.
+         */
+        uint32_t apb2otp_block9_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word9 Data */
+/** Type of apb2otp_blk9_w9 register
+ *  eFuse apb2otp block9 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word9 data.
+         */
+        uint32_t apb2otp_block9_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word10 Data */
+/** Type of apb2otp_blk9_w10 register
+ *  eFuse apb2otp block9 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word10 data.
+         */
+        uint32_t apb2otp_block9_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word11 Data */
+/** Type of apb2otp_blk9_w11 register
+ *  eFuse apb2otp block9 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word11 data.
+         */
+        uint32_t apb2otp_block9_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word1 Data */
+/** Type of apb2otp_blk10_w1 register
+ *  eFuse apb2otp block10 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word1 data.
+         */
+        uint32_t apb2otp_block10_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word2 Data */
+/** Type of apb2otp_blk10_w2 register
+ *  eFuse apb2otp block10 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word2 data.
+         */
+        uint32_t apb2otp_block10_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word3 Data */
+/** Type of apb2otp_blk10_w3 register
+ *  eFuse apb2otp block10 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word3 data.
+         */
+        uint32_t apb2otp_block10_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word4 Data */
+/** Type of apb2otp_blk10_w4 register
+ *  eFuse apb2otp block10 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word4 data.
+         */
+        uint32_t apb2otp_block10_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word5 Data */
+/** Type of apb2otp_blk10_w5 register
+ *  eFuse apb2otp block10 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word5 data.
+         */
+        uint32_t apb2otp_block10_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word6 Data */
+/** Type of apb2otp_blk10_w6 register
+ *  eFuse apb2otp block10 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word6 data.
+         */
+        uint32_t apb2otp_block10_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word7 Data */
+/** Type of apb2otp_blk10_w7 register
+ *  eFuse apb2otp block10 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word7 data.
+         */
+        uint32_t apb2otp_block10_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word8 Data */
+/** Type of apb2otp_blk10_w8 register
+ *  eFuse apb2otp block10 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word8 data.
+         */
+        uint32_t apb2otp_block10_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word9 Data */
+/** Type of apb2otp_blk10_w9 register
+ *  eFuse apb2otp block10 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word9 data.
+         */
+        uint32_t apb2otp_block10_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word10 Data */
+/** Type of apb2otp_blk10_w10 register
+ *  eFuse apb2otp block10 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word10 data.
+         */
+        uint32_t apb2otp_block19_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Function Enable Signal */
+/** Type of apb2otp_en register
+ *  eFuse apb2otp enable configuration register.
+ */
+typedef union {
+    struct {
+        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
+         *  Apb2otp mode enable signal.
+         */
+        uint32_t apb2otp_apb2otp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} efuse_apb2otp_en_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_datan_reg_t pgm_datan[8];
+    volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3];
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0;
+    volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1;
+    uint32_t reserved_04c;
+    volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
+    volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
+    volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
+    volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8];
+    volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8];
+    volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8];
+    volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8];
+    volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8];
+    volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8];
+    volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8];
+    volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8];
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    uint32_t reserved_174;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0;
+    volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1;
+    volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2;
+    volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3;
+    volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4;
+    uint32_t reserved_190[8];
+    volatile efuse_ecdsa_reg_t ecdsa;
+    uint32_t reserved_1b4[3];
+    volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0;
+    volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+    volatile efuse_date_reg_t date;
+    uint32_t reserved_200[384];
+    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
+    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
+    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
+    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
+    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
+    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
+    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
+    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
+    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
+    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
+    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
+    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
+    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
+    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
+    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
+    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
+    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
+    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
+    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
+    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
+    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
+    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
+    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
+    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
+    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
+    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
+    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
+    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
+    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
+    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
+    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
+    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
+    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
+    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
+    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
+    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
+    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
+    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
+    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
+    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
+    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
+    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
+    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
+    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
+    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
+    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
+    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
+    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
+    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
+    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
+    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
+    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
+    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
+    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
+    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
+    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
+    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
+    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
+    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
+    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
+    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
+    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
+    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
+    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
+    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
+    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
+    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
+    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
+    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
+    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
+    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
+    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
+    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
+    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
+    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
+    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
+    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
+    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
+    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
+    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
+    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
+    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
+    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
+    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
+    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
+    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
+    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
+    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
+    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
+    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
+    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
+    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
+    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
+    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
+    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
+    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
+    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
+    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
+    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
+    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
+    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
+    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
+    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
+    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
+    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
+    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
+    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
+    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
+    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
+    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
+    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
+    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
+    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
+    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
+    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
+    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
+    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
+    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
+    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
+    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
+    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
+    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
+    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
+    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
+    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
+    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
+    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
+    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
+    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
+    uint32_t reserved_a04;
+    volatile efuse_apb2otp_en_reg_t apb2otp_en;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h
new file mode 100644
index 0000000000..e0a0a82e4e
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h
@@ -0,0 +1,4655 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/efuse_defs.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13421
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Register 0 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Register 1 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Register 2 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Register 3 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 3rd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Register 4 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Register 5 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Register 6 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Register 7 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS_REG register
+ *  BLOCK0 data register 0.
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Represents whether programming of individual eFuse memory bit is disabled or
+ *  enabled. 1: Disabled. 0 Enabled.
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  BLOCK0 data register 1.
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [7]; default: 0;
+ *  Enable usb device exchange pins of D+ and D-.
+ */
+#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(7))
+#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S)
+#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_DEVICE_EXCHG_PINS_S  7
+/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [8]; default: 0;
+ *  Enable usb otg11 exchange pins of D+ and D-.
+ */
+#define EFUSE_USB_OTG11_EXCHG_PINS    (BIT(8))
+#define EFUSE_USB_OTG11_EXCHG_PINS_M  (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S)
+#define EFUSE_USB_OTG11_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_OTG11_EXCHG_PINS_S  8
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
+ *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  9
+/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0;
+ *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_POWERGLITCH_EN    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
+#define EFUSE_POWERGLITCH_EN_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
+ *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  Represents whether the function that forces chip into download mode is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
+ *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
+ *  boot_mode_download.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
+ *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+ *  is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+ *  enabled.
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+ *  enabled.
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+ *  mode). 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
+ */
+#define EFUSE_USB_DEVICE_DREFH    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_M  (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S)
+#define EFUSE_USB_DEVICE_DREFH_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_S  21
+/** EFUSE_USB_OTG11_DREFH : RO; bitpos: [24:23]; default: 0;
+ *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+ */
+#define EFUSE_USB_OTG11_DREFH    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_M  (EFUSE_USB_OTG11_DREFH_V << EFUSE_USB_OTG11_DREFH_S)
+#define EFUSE_USB_OTG11_DREFH_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_S  23
+/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
+ *  TBD
+ */
+#define EFUSE_USB_PHY_SEL    (BIT(25))
+#define EFUSE_USB_PHY_SEL_M  (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S)
+#define EFUSE_USB_PHY_SEL_V  0x00000001U
+#define EFUSE_USB_PHY_SEL_S  25
+/** EFUSE_KM_HUK_GEN_STATE_LOW : RO; bitpos: [31:26]; default: 0;
+ *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+ *  of 1 is valid.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_LOW    0x0000003FU
+#define EFUSE_KM_HUK_GEN_STATE_LOW_M  (EFUSE_KM_HUK_GEN_STATE_LOW_V << EFUSE_KM_HUK_GEN_STATE_LOW_S)
+#define EFUSE_KM_HUK_GEN_STATE_LOW_V  0x0000003FU
+#define EFUSE_KM_HUK_GEN_STATE_LOW_S  26
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  BLOCK0 data register 2.
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_KM_HUK_GEN_STATE_HIGH : RO; bitpos: [2:0]; default: 0;
+ *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+ *  of 1 is valid.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_HIGH    0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_V << EFUSE_KM_HUK_GEN_STATE_HIGH_S)
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_V  0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_S  0
+/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4:3]; default: 0;
+ *  Set bits to control key manager random number switch cycle. 0: control by register.
+ *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_S  3
+/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [8:5]; default: 0;
+ *  Set each bit to control whether corresponding key can only be deployed once. 1 is
+ *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  5
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [12:9]; default: 0;
+ *  Set each bit to control whether corresponding key must come from key manager.. 1 is
+ *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  9
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [13]; default: 0;
+ *  Set this bit to disable software written init key, and force use efuse_init_key.
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  13
+/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0;
+ *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
+ */
+#define EFUSE_XTS_KEY_LENGTH_256    (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
+#define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
+#define EFUSE_XTS_KEY_LENGTH_256_S  14
+/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_79    (BIT(15))
+#define EFUSE_RD_RESERVE_0_79_M  (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S)
+#define EFUSE_RD_RESERVE_0_79_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_79_S  15
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+ *  selected. 0: not selected.
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+ *  1: enabled. Even number of 1: disabled.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ *  Represents the purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  24
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ *  Represents the purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  28
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  BLOCK0 data register 3.
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ *  Represents the purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_S  0
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ *  Represents the purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  4
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ *  Represents the purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  8
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ *  Represents the purpose of Key5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  12
+/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents the spa secure level by configuring the clock random divide mode.
+ */
+#define EFUSE_SEC_DPA_LEVEL    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
+#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_S  16
+/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0;
+ *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
+ *  0: not force used.
+ */
+#define EFUSE_ECDSA_ENABLE_SOFT_K    (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_M  (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S)
+#define EFUSE_ECDSA_ENABLE_SOFT_K_V  0x00000001U
+#define EFUSE_ECDSA_ENABLE_SOFT_K_S  18
+/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
+ *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
+#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_S  19
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_118    (BIT(22))
+#define EFUSE_RD_RESERVE_0_118_M  (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S)
+#define EFUSE_RD_RESERVE_0_118_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_118_S  22
+/** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0;
+ *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
+ */
+#define EFUSE_FLASH_TYPE    (BIT(23))
+#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
+#define EFUSE_FLASH_TYPE_V  0x00000001U
+#define EFUSE_FLASH_TYPE_S  23
+/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [25:24]; default: 0;
+ *  Set flash page size.
+ */
+#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
+#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_S  24
+/** EFUSE_FLASH_ECC_EN : RO; bitpos: [26]; default: 0;
+ *  Set this bit to enable ecc for flash boot.
+ */
+#define EFUSE_FLASH_ECC_EN    (BIT(26))
+#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
+#define EFUSE_FLASH_ECC_EN_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_S  26
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [27]; default: 0;
+ *  Set this bit to disable download via USB-OTG.
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  27
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  Represents the flash waiting time after power-up, in unit of ms. When the value
+ *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+ *  is 2 times the programmed value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  BLOCK0 data register 4.
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
+ *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
+ *  0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0;
+ *  TBD
+ */
+#define EFUSE_LOCK_KM_KEY    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
+#define EFUSE_LOCK_KM_KEY_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+ *  disabled.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ *  Represents the type of UART printing. 00: force enable printing. 01: enable
+ *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+ *  at high level. 11: force disable printing.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
+ *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+ *  forced. 0:not forced.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  8
+/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
+ *  Represents the version used by ESP-IDF anti-rollback feature.
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
+ *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
+/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0;
+ *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
+ *  enabled. 0:disabled.
+ */
+#define EFUSE_HYS_EN_PAD    (BIT(26))
+#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
+#define EFUSE_HYS_EN_PAD_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_S  26
+/** EFUSE_DCDC_VSET : RO; bitpos: [31:27]; default: 0;
+ *  Set the dcdc voltage default.
+ */
+#define EFUSE_DCDC_VSET    0x0000001FU
+#define EFUSE_DCDC_VSET_M  (EFUSE_DCDC_VSET_V << EFUSE_DCDC_VSET_S)
+#define EFUSE_DCDC_VSET_V  0x0000001FU
+#define EFUSE_DCDC_VSET_S  27
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  BLOCK0 data register 5.
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_PXA0_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
+ *  TBD
+ */
+#define EFUSE_PXA0_TIEH_SEL_0    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_M  (EFUSE_PXA0_TIEH_SEL_0_V << EFUSE_PXA0_TIEH_SEL_0_S)
+#define EFUSE_PXA0_TIEH_SEL_0_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_S  0
+/** EFUSE_PXA0_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_PXA0_TIEH_SEL_1    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_M  (EFUSE_PXA0_TIEH_SEL_1_V << EFUSE_PXA0_TIEH_SEL_1_S)
+#define EFUSE_PXA0_TIEH_SEL_1_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_S  2
+/** EFUSE_PXA0_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_PXA0_TIEH_SEL_2    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_M  (EFUSE_PXA0_TIEH_SEL_2_V << EFUSE_PXA0_TIEH_SEL_2_S)
+#define EFUSE_PXA0_TIEH_SEL_2_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_S  4
+/** EFUSE_PXA0_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_PXA0_TIEH_SEL_3    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_M  (EFUSE_PXA0_TIEH_SEL_3_V << EFUSE_PXA0_TIEH_SEL_3_S)
+#define EFUSE_PXA0_TIEH_SEL_3_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_S  6
+/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
+/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0;
+ *  Represents the usb device single-end input low threshold; 0.8 V to 1.04 V with step
+ *  of 80 mV
+ */
+#define EFUSE_USB_DEVICE_DREFL    0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_M  (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S)
+#define EFUSE_USB_DEVICE_DREFL_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_S  12
+/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0;
+ *  Represents the usb otg11 single-end input low threshold; 0.8 V to 1.04 V with step
+ *  of 80 mV
+ */
+#define EFUSE_USB_OTG11_DREFL    0x00000003U
+#define EFUSE_USB_OTG11_DREFL_M  (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S)
+#define EFUSE_USB_OTG11_DREFL_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFL_S  14
+/** EFUSE_RD_RESERVE_0_176 : RW; bitpos: [17:16]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_176    0x00000003U
+#define EFUSE_RD_RESERVE_0_176_M  (EFUSE_RD_RESERVE_0_176_V << EFUSE_RD_RESERVE_0_176_S)
+#define EFUSE_RD_RESERVE_0_176_V  0x00000003U
+#define EFUSE_RD_RESERVE_0_176_S  16
+/** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0;
+ *  HP system power source select. 0:LDO. 1: DCDC.
+ */
+#define EFUSE_HP_PWR_SRC_SEL    (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_M  (EFUSE_HP_PWR_SRC_SEL_V << EFUSE_HP_PWR_SRC_SEL_S)
+#define EFUSE_HP_PWR_SRC_SEL_V  0x00000001U
+#define EFUSE_HP_PWR_SRC_SEL_S  18
+/** EFUSE_DCDC_VSET_EN : RO; bitpos: [19]; default: 0;
+ *  Select dcdc vset use efuse_dcdc_vset.
+ */
+#define EFUSE_DCDC_VSET_EN    (BIT(19))
+#define EFUSE_DCDC_VSET_EN_M  (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S)
+#define EFUSE_DCDC_VSET_EN_V  0x00000001U
+#define EFUSE_DCDC_VSET_EN_S  19
+/** EFUSE_DIS_WDT : RO; bitpos: [20]; default: 0;
+ *  Set this bit to disable watch dog.
+ */
+#define EFUSE_DIS_WDT    (BIT(20))
+#define EFUSE_DIS_WDT_M  (EFUSE_DIS_WDT_V << EFUSE_DIS_WDT_S)
+#define EFUSE_DIS_WDT_V  0x00000001U
+#define EFUSE_DIS_WDT_S  20
+/** EFUSE_DIS_SWD : RO; bitpos: [21]; default: 0;
+ *  Set this bit to disable super-watchdog.
+ */
+#define EFUSE_DIS_SWD    (BIT(21))
+#define EFUSE_DIS_SWD_M  (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S)
+#define EFUSE_DIS_SWD_V  0x00000001U
+#define EFUSE_DIS_SWD_S  21
+/** EFUSE_RD_RESERVE_0_182 : RW; bitpos: [31:22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_182    0x000003FFU
+#define EFUSE_RD_RESERVE_0_182_M  (EFUSE_RD_RESERVE_0_182_V << EFUSE_RD_RESERVE_0_182_S)
+#define EFUSE_RD_RESERVE_0_182_V  0x000003FFU
+#define EFUSE_RD_RESERVE_0_182_S  22
+
+/** EFUSE_RD_MAC_SYS_0_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the low 32 bits of MAC address.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SYS_1_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Stores the high 16 bits of MAC address.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_RESERVED_1_16 : RO; bitpos: [31:16]; default: 0;
+ *  Stores the extended bits of MAC address.
+ */
+#define EFUSE_RESERVED_1_16    0x0000FFFFU
+#define EFUSE_RESERVED_1_16_M  (EFUSE_RESERVED_1_16_V << EFUSE_RESERVED_1_16_S)
+#define EFUSE_RESERVED_1_16_V  0x0000FFFFU
+#define EFUSE_RESERVED_1_16_S  16
+
+/** EFUSE_RD_MAC_SYS_2_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
+ *  Minor chip version
+ */
+#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
+#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_S  0
+/** EFUSE_WAFER_VERSION_MAJOR_LO : R; bitpos: [5:4]; default: 0;
+ *  Major chip version (lower 2 bits)
+ */
+#define EFUSE_WAFER_VERSION_MAJOR_LO    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_LO_M  (EFUSE_WAFER_VERSION_MAJOR_LO_V << EFUSE_WAFER_VERSION_MAJOR_LO_S)
+#define EFUSE_WAFER_VERSION_MAJOR_LO_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_LO_S  4
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
+ *  Disables check of wafer version major
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(6))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  6
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
+ *  BLK_VERSION_MINOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  8
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
+ *  BLK_VERSION_MAJOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  11
+/** EFUSE_PSRAM_CAP : R; bitpos: [15:13]; default: 0;
+ *  PSRAM capacity
+ */
+#define EFUSE_PSRAM_CAP    0x00000007U
+#define EFUSE_PSRAM_CAP_M  (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
+#define EFUSE_PSRAM_CAP_V  0x00000007U
+#define EFUSE_PSRAM_CAP_S  13
+/** EFUSE_TEMP : R; bitpos: [17:16]; default: 0;
+ *  Operating temperature of the ESP chip
+ */
+#define EFUSE_TEMP    0x00000003U
+#define EFUSE_TEMP_M  (EFUSE_TEMP_V << EFUSE_TEMP_S)
+#define EFUSE_TEMP_V  0x00000003U
+#define EFUSE_TEMP_S  16
+/** EFUSE_PSRAM_VENDOR : R; bitpos: [19:18]; default: 0;
+ *  PSRAM vendor
+ */
+#define EFUSE_PSRAM_VENDOR    0x00000003U
+#define EFUSE_PSRAM_VENDOR_M  (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
+#define EFUSE_PSRAM_VENDOR_V  0x00000003U
+#define EFUSE_PSRAM_VENDOR_S  18
+/** EFUSE_PKG_VERSION : R; bitpos: [22:20]; default: 0;
+ *  Package version
+ */
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  20
+/** EFUSE_WAFER_VERSION_MAJOR_HI : R; bitpos: [23]; default: 0;
+ *  Major chip version (MSB)
+ */
+#define EFUSE_WAFER_VERSION_MAJOR_HI    (BIT(23))
+#define EFUSE_WAFER_VERSION_MAJOR_HI_M  (EFUSE_WAFER_VERSION_MAJOR_HI_V << EFUSE_WAFER_VERSION_MAJOR_HI_S)
+#define EFUSE_WAFER_VERSION_MAJOR_HI_V  0x00000001U
+#define EFUSE_WAFER_VERSION_MAJOR_HI_S  23
+/** EFUSE_LDO_VO1_DREF : R; bitpos: [27:24]; default: 0;
+ *  Output VO1 parameter
+ */
+#define EFUSE_LDO_VO1_DREF    0x0000000FU
+#define EFUSE_LDO_VO1_DREF_M  (EFUSE_LDO_VO1_DREF_V << EFUSE_LDO_VO1_DREF_S)
+#define EFUSE_LDO_VO1_DREF_V  0x0000000FU
+#define EFUSE_LDO_VO1_DREF_S  24
+/** EFUSE_LDO_VO2_DREF : R; bitpos: [31:28]; default: 0;
+ *  Output VO2 parameter
+ */
+#define EFUSE_LDO_VO2_DREF    0x0000000FU
+#define EFUSE_LDO_VO2_DREF_M  (EFUSE_LDO_VO2_DREF_V << EFUSE_LDO_VO2_DREF_S)
+#define EFUSE_LDO_VO2_DREF_V  0x0000000FU
+#define EFUSE_LDO_VO2_DREF_S  28
+
+/** EFUSE_RD_MAC_SYS_3_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_LDO_VO1_MUL : R; bitpos: [2:0]; default: 0;
+ *  Output VO1 parameter
+ */
+#define EFUSE_LDO_VO1_MUL    0x00000007U
+#define EFUSE_LDO_VO1_MUL_M  (EFUSE_LDO_VO1_MUL_V << EFUSE_LDO_VO1_MUL_S)
+#define EFUSE_LDO_VO1_MUL_V  0x00000007U
+#define EFUSE_LDO_VO1_MUL_S  0
+/** EFUSE_LDO_VO2_MUL : R; bitpos: [5:3]; default: 0;
+ *  Output VO2 parameter
+ */
+#define EFUSE_LDO_VO2_MUL    0x00000007U
+#define EFUSE_LDO_VO2_MUL_M  (EFUSE_LDO_VO2_MUL_V << EFUSE_LDO_VO2_MUL_S)
+#define EFUSE_LDO_VO2_MUL_V  0x00000007U
+#define EFUSE_LDO_VO2_MUL_S  3
+/** EFUSE_LDO_VO3_K : R; bitpos: [13:6]; default: 0;
+ *  Output VO3 calibration parameter
+ */
+#define EFUSE_LDO_VO3_K    0x000000FFU
+#define EFUSE_LDO_VO3_K_M  (EFUSE_LDO_VO3_K_V << EFUSE_LDO_VO3_K_S)
+#define EFUSE_LDO_VO3_K_V  0x000000FFU
+#define EFUSE_LDO_VO3_K_S  6
+/** EFUSE_LDO_VO3_VOS : R; bitpos: [19:14]; default: 0;
+ *  Output VO3 calibration parameter
+ */
+#define EFUSE_LDO_VO3_VOS    0x0000003FU
+#define EFUSE_LDO_VO3_VOS_M  (EFUSE_LDO_VO3_VOS_V << EFUSE_LDO_VO3_VOS_S)
+#define EFUSE_LDO_VO3_VOS_V  0x0000003FU
+#define EFUSE_LDO_VO3_VOS_S  14
+/** EFUSE_LDO_VO3_C : R; bitpos: [25:20]; default: 0;
+ *  Output VO3 calibration parameter
+ */
+#define EFUSE_LDO_VO3_C    0x0000003FU
+#define EFUSE_LDO_VO3_C_M  (EFUSE_LDO_VO3_C_V << EFUSE_LDO_VO3_C_S)
+#define EFUSE_LDO_VO3_C_V  0x0000003FU
+#define EFUSE_LDO_VO3_C_S  20
+/** EFUSE_LDO_VO4_K : R; bitpos: [31:26]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_K    0x0000003FU
+#define EFUSE_LDO_VO4_K_M  (EFUSE_LDO_VO4_K_V << EFUSE_LDO_VO4_K_S)
+#define EFUSE_LDO_VO4_K_V  0x0000003FU
+#define EFUSE_LDO_VO4_K_S  26
+
+/** EFUSE_RD_MAC_SYS_4_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_LDO_VO4_K_1 : R; bitpos: [1:0]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_K_1    0x00000003U
+#define EFUSE_LDO_VO4_K_1_M  (EFUSE_LDO_VO4_K_1_V << EFUSE_LDO_VO4_K_1_S)
+#define EFUSE_LDO_VO4_K_1_V  0x00000003U
+#define EFUSE_LDO_VO4_K_1_S  0
+/** EFUSE_LDO_VO4_VOS : R; bitpos: [7:2]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_VOS    0x0000003FU
+#define EFUSE_LDO_VO4_VOS_M  (EFUSE_LDO_VO4_VOS_V << EFUSE_LDO_VO4_VOS_S)
+#define EFUSE_LDO_VO4_VOS_V  0x0000003FU
+#define EFUSE_LDO_VO4_VOS_S  2
+/** EFUSE_LDO_VO4_C : R; bitpos: [13:8]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_C    0x0000003FU
+#define EFUSE_LDO_VO4_C_M  (EFUSE_LDO_VO4_C_V << EFUSE_LDO_VO4_C_S)
+#define EFUSE_LDO_VO4_C_V  0x0000003FU
+#define EFUSE_LDO_VO4_C_S  8
+/** EFUSE_RESERVED_1_142 : R; bitpos: [15:14]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_142    0x00000003U
+#define EFUSE_RESERVED_1_142_M  (EFUSE_RESERVED_1_142_V << EFUSE_RESERVED_1_142_S)
+#define EFUSE_RESERVED_1_142_V  0x00000003U
+#define EFUSE_RESERVED_1_142_S  14
+/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [19:16]; default: 0;
+ *  Active HP DBIAS of fixed voltage
+ */
+#define EFUSE_ACTIVE_HP_DBIAS    0x0000000FU
+#define EFUSE_ACTIVE_HP_DBIAS_M  (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
+#define EFUSE_ACTIVE_HP_DBIAS_V  0x0000000FU
+#define EFUSE_ACTIVE_HP_DBIAS_S  16
+/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [23:20]; default: 0;
+ *  Active LP DBIAS of fixed voltage
+ */
+#define EFUSE_ACTIVE_LP_DBIAS    0x0000000FU
+#define EFUSE_ACTIVE_LP_DBIAS_M  (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
+#define EFUSE_ACTIVE_LP_DBIAS_V  0x0000000FU
+#define EFUSE_ACTIVE_LP_DBIAS_S  20
+/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [27:24]; default: 0;
+ *  LSLP HP DBIAS of fixed voltage
+ */
+#define EFUSE_LSLP_HP_DBIAS    0x0000000FU
+#define EFUSE_LSLP_HP_DBIAS_M  (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
+#define EFUSE_LSLP_HP_DBIAS_V  0x0000000FU
+#define EFUSE_LSLP_HP_DBIAS_S  24
+/** EFUSE_DSLP_DBG : R; bitpos: [31:28]; default: 0;
+ *  DSLP BDG of fixed voltage
+ */
+#define EFUSE_DSLP_DBG    0x0000000FU
+#define EFUSE_DSLP_DBG_M  (EFUSE_DSLP_DBG_V << EFUSE_DSLP_DBG_S)
+#define EFUSE_DSLP_DBG_V  0x0000000FU
+#define EFUSE_DSLP_DBG_S  28
+
+/** EFUSE_RD_MAC_SYS_5_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [4:0]; default: 0;
+ *  DSLP LP DBIAS of fixed voltage
+ */
+#define EFUSE_DSLP_LP_DBIAS    0x0000001FU
+#define EFUSE_DSLP_LP_DBIAS_M  (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
+#define EFUSE_DSLP_LP_DBIAS_V  0x0000001FU
+#define EFUSE_DSLP_LP_DBIAS_S  0
+/** EFUSE_LP_DCDC_DBIAS_VOL_GAP : R; bitpos: [9:5]; default: 0;
+ *  DBIAS gap between LP and DCDC
+ */
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP    0x0000001FU
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_M  (EFUSE_LP_DCDC_DBIAS_VOL_GAP_V << EFUSE_LP_DCDC_DBIAS_VOL_GAP_S)
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_V  0x0000001FU
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_S  5
+/** EFUSE_RESERVED_1_170 : R; bitpos: [31:10]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_170    0x003FFFFFU
+#define EFUSE_RESERVED_1_170_M  (EFUSE_RESERVED_1_170_V << EFUSE_RESERVED_1_170_S)
+#define EFUSE_RESERVED_1_170_V  0x003FFFFFU
+#define EFUSE_RESERVED_1_170_S  10
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [9:0]; default: 0;
+ *  Average initcode of ADC1 atten0
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S  0
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [19:10]; default: 0;
+ *  Average initcode of ADC1 atten1
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S  10
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [29:20]; default: 0;
+ *  Average initcode of ADC1 atten2
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S  20
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [31:30]; default: 0;
+ *  Average initcode of ADC1 atten3
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3    0x00000003U
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V  0x00000003U
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S  30
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
+ *  Average initcode of ADC1 atten3
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1    0x000000FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V  0x000000FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S  0
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN0 : R; bitpos: [17:8]; default: 0;
+ *  Average initcode of ADC2 atten0
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN0_V << EFUSE_ADC2_AVE_INITCODE_ATTEN0_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_S  8
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN1 : R; bitpos: [27:18]; default: 0;
+ *  Average initcode of ADC2 atten1
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1    0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN1_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_S  18
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN2 : R; bitpos: [31:28]; default: 0;
+ *  Average initcode of ADC2 atten2
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2    0x0000000FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN2_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_V  0x0000000FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_S  28
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 : R; bitpos: [5:0]; default: 0;
+ *  Average initcode of ADC2 atten2
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1    0x0000003FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V  0x0000003FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S  0
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN3 : R; bitpos: [15:6]; default: 0;
+ *  Average initcode of ADC2 atten3
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3    0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN3_V << EFUSE_ADC2_AVE_INITCODE_ATTEN3_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_S  6
+/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [25:16]; default: 0;
+ *  HI_DOUT of ADC1 atten0
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_S  16
+/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [31:26]; default: 0;
+ *  HI_DOUT of ADC1 atten1
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN1    0x0000003FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_V  0x0000003FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_S  26
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_ADC1_HI_DOUT_ATTEN1_1 : R; bitpos: [3:0]; default: 0;
+ *  HI_DOUT of ADC1 atten1
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1    0x0000000FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_V  0x0000000FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_S  0
+/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [13:4]; default: 0;
+ *  HI_DOUT of ADC1 atten2
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_M  (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_S  4
+/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [23:14]; default: 0;
+ *  HI_DOUT of ADC1 atten3
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN3    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_S  14
+/** EFUSE_RESERVED_2_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_248    0x000000FFU
+#define EFUSE_RESERVED_2_248_M  (EFUSE_RESERVED_2_248_V << EFUSE_RESERVED_2_248_S)
+#define EFUSE_RESERVED_2_248_V  0x000000FFU
+#define EFUSE_RESERVED_2_248_S  24
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_192    0x000000FFU
+#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
+#define EFUSE_RESERVED_3_192_V  0x000000FFU
+#define EFUSE_RESERVED_3_192_S  0
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_S  8
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_248    0x000000FFU
+#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
+#define EFUSE_RESERVED_3_248_V  0x000000FFU
+#define EFUSE_RESERVED_3_248_S  24
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_S  0
+
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_S  0
+
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_S  0
+
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_S  0
+
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_S  0
+
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_S  0
+
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_S  0
+
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_ADC2_HI_DOUT_ATTEN0 : R; bitpos: [9:0]; default: 0;
+ *  HI_DOUT of ADC2 atten0
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN0    0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN0_M  (EFUSE_ADC2_HI_DOUT_ATTEN0_V << EFUSE_ADC2_HI_DOUT_ATTEN0_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN0_S  0
+/** EFUSE_ADC2_HI_DOUT_ATTEN1 : R; bitpos: [19:10]; default: 0;
+ *  HI_DOUT of ADC2 atten1
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN1    0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN1_M  (EFUSE_ADC2_HI_DOUT_ATTEN1_V << EFUSE_ADC2_HI_DOUT_ATTEN1_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN1_S  10
+/** EFUSE_ADC2_HI_DOUT_ATTEN2 : R; bitpos: [29:20]; default: 0;
+ *  HI_DOUT of ADC2 atten2
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN2    0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN2_M  (EFUSE_ADC2_HI_DOUT_ATTEN2_V << EFUSE_ADC2_HI_DOUT_ATTEN2_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN2_S  20
+/** EFUSE_ADC2_HI_DOUT_ATTEN3 : R; bitpos: [31:30]; default: 0;
+ *  HI_DOUT of ADC2 atten3
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN3    0x00000003U
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_M  (EFUSE_ADC2_HI_DOUT_ATTEN3_V << EFUSE_ADC2_HI_DOUT_ATTEN3_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_V  0x00000003U
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_S  30
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_ADC2_HI_DOUT_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
+ *  HI_DOUT of ADC2 atten3
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1    0x000000FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_M  (EFUSE_ADC2_HI_DOUT_ATTEN3_1_V << EFUSE_ADC2_HI_DOUT_ATTEN3_1_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_V  0x000000FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_S  0
+/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
+ *  Gap between ADC1_ch0 and average initcode
+ */
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S  8
+/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
+ *  Gap between ADC1_ch1 and average initcode
+ */
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S  12
+/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
+ *  Gap between ADC1_ch2 and average initcode
+ */
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S  16
+/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
+ *  Gap between ADC1_ch3 and average initcode
+ */
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S  20
+/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
+ *  Gap between ADC1_ch4 and average initcode
+ */
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S  24
+/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
+ *  Gap between ADC1_ch5 and average initcode
+ */
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S  28
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+/** EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF : R; bitpos: [3:0]; default: 0;
+ *  Gap between ADC1_ch6 and average initcode
+ */
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S  0
+/** EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF : R; bitpos: [7:4]; default: 0;
+ *  Gap between ADC1_ch7 and average initcode
+ */
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S  4
+/** EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
+ *  Gap between ADC2_ch0 and average initcode
+ */
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S  8
+/** EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
+ *  Gap between ADC2_ch1 and average initcode
+ */
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S  12
+/** EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
+ *  Gap between ADC2_ch2 and average initcode
+ */
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S  16
+/** EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
+ *  Gap between ADC2_ch3 and average initcode
+ */
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S  20
+/** EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
+ *  Gap between ADC2_ch4 and average initcode
+ */
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S  24
+/** EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
+ *  Gap between ADC2_ch5 and average initcode
+ */
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S  28
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
+ *  Temperature calibration data
+ */
+#define EFUSE_TEMPERATURE_SENSOR    0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_M  (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
+#define EFUSE_TEMPERATURE_SENSOR_V  0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_S  0
+/** EFUSE_RESERVED_10_105 : R; bitpos: [31:9]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_10_105    0x007FFFFFU
+#define EFUSE_RESERVED_10_105_M  (EFUSE_RESERVED_10_105_V << EFUSE_RESERVED_10_105_S)
+#define EFUSE_RESERVED_10_105_V  0x007FFFFFU
+#define EFUSE_RESERVED_10_105_S  9
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+/** EFUSE_RD_REPEAT_ERR0_REG register
+ *  Programming error record register 0 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  Indicates a programming error of RD_DIS.
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO; bitpos: [7]; default: 0;
+ *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
+ */
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR    (BIT(7))
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S)
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S  7
+/** EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
+ */
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR    (BIT(8))
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S)
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S  8
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
+ *  Indicates a programming error of DIS_USB_JTAG.
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0;
+ *  Indicates a programming error of POWERGLITCH_EN.
+ */
+#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
+#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_ERR_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
+/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
+ *  Indicates a programming error of DIS_TWAI.
+ */
+#define EFUSE_DIS_TWAI_ERR    (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
+#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
+#define EFUSE_DIS_TWAI_ERR_S  14
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
+ *  Indicates a programming error of JTAG_SEL_ENABLE.
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  Indicates a programming error of SOFT_DIS_JTAG.
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of DIS_PAD_JTAG.
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DEVICE_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  Indicates a programming error of USB_DEVICE_DREFH.
+ */
+#define EFUSE_USB_DEVICE_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_ERR_M  (EFUSE_USB_DEVICE_DREFH_ERR_V << EFUSE_USB_DEVICE_DREFH_ERR_S)
+#define EFUSE_USB_DEVICE_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_ERR_S  21
+/** EFUSE_USB_OTG11_DREFH_ERR : RO; bitpos: [24:23]; default: 0;
+ *  Indicates a programming error of USB_OTG11_DREFH.
+ */
+#define EFUSE_USB_OTG11_DREFH_ERR    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_ERR_M  (EFUSE_USB_OTG11_DREFH_ERR_V << EFUSE_USB_OTG11_DREFH_ERR_S)
+#define EFUSE_USB_OTG11_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_ERR_S  23
+/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of USB_PHY_SEL.
+ */
+#define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
+#define EFUSE_USB_PHY_SEL_ERR_M  (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S)
+#define EFUSE_USB_PHY_SEL_ERR_V  0x00000001U
+#define EFUSE_USB_PHY_SEL_ERR_S  25
+/** EFUSE_HUK_GEN_STATE_LOW_ERR : RO; bitpos: [31:26]; default: 0;
+ *  Indicates a programming error of HUK_GEN_STATE_LOW.
+ */
+#define EFUSE_HUK_GEN_STATE_LOW_ERR    0x0000003FU
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_M  (EFUSE_HUK_GEN_STATE_LOW_ERR_V << EFUSE_HUK_GEN_STATE_LOW_ERR_S)
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_V  0x0000003FU
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_S  26
+
+/** EFUSE_RD_REPEAT_ERR1_REG register
+ *  Programming error record register 1 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO; bitpos: [2:0]; default: 0;
+ *  Indicates a programming error of HUK_GEN_STATE_HIGH.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR    0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V << EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S)
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V  0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S  0
+/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4:3]; default: 0;
+ *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  3
+/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [8:5]; default: 0;
+ *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  5
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [12:9]; default: 0;
+ *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  9
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  13
+/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0;
+ *  Indicates a programming error of XTS_KEY_LENGTH_256.
+ */
+#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S)
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  14
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of WDT_DELAY_SEL.
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_0.
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_1.
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR2_REG register
+ *  Programming error record register 2 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_2.
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_3.
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_4.
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_5.
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of SEC_DPA_LEVEL.
+ */
+#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
+#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
+/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0;
+ *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
+ */
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR    (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M  (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S)
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V  0x00000001U
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S  18
+/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of CRYPT_DPA_ENABLE.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_EN.
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [23]; default: 0;
+ *  Indicates a programming error of FLASH_TYPE.
+ */
+#define EFUSE_FLASH_TYPE_ERR    (BIT(23))
+#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
+#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
+#define EFUSE_FLASH_TYPE_ERR_S  23
+/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [25:24]; default: 0;
+ *  Indicates a programming error of FLASH_PAGE_SIZE.
+ */
+#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
+#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_S  24
+/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [26]; default: 0;
+ *  Indicates a programming error of FLASH_ECC_EN.
+ */
+#define EFUSE_FLASH_ECC_EN_ERR    (BIT(26))
+#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
+#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_ERR_S  26
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [27]; default: 0;
+ *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR    (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S  27
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of FLASH_TPUW.
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR3_REG register
+ *  Programming error record register 3 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  Indicates a programming error of DIS_DIRECT_BOOT.
+ */
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
+/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0;
+ *  TBD
+ */
+#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
+#define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_ERR_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Indicates a programming error of UART_PRINT_CONTROL.
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of FORCE_SEND_RESUME.
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
+ *  Indicates a programming error of SECURE VERSION.
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
+/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0;
+ *  Indicates a programming error of HYS_EN_PAD.
+ */
+#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
+#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
+#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_ERR_S  26
+/** EFUSE_DCDC_VSET_ERR : RO; bitpos: [31:27]; default: 0;
+ *  Indicates a programming error of DCDC_VSET.
+ */
+#define EFUSE_DCDC_VSET_ERR    0x0000001FU
+#define EFUSE_DCDC_VSET_ERR_M  (EFUSE_DCDC_VSET_ERR_V << EFUSE_DCDC_VSET_ERR_S)
+#define EFUSE_DCDC_VSET_ERR_V  0x0000001FU
+#define EFUSE_DCDC_VSET_ERR_S  27
+
+/** EFUSE_RD_REPEAT_ERR4_REG register
+ *  Programming error record register 4 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
+/** EFUSE_PXA0_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_0.
+ */
+#define EFUSE_PXA0_TIEH_SEL_0_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_M  (EFUSE_PXA0_TIEH_SEL_0_ERR_V << EFUSE_PXA0_TIEH_SEL_0_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_S  0
+/** EFUSE_PXA0_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_1.
+ */
+#define EFUSE_PXA0_TIEH_SEL_1_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_M  (EFUSE_PXA0_TIEH_SEL_1_ERR_V << EFUSE_PXA0_TIEH_SEL_1_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_S  2
+/** EFUSE_PXA0_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_2.
+ */
+#define EFUSE_PXA0_TIEH_SEL_2_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_M  (EFUSE_PXA0_TIEH_SEL_2_ERR_V << EFUSE_PXA0_TIEH_SEL_2_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_S  4
+/** EFUSE_PXA0_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_3.
+ */
+#define EFUSE_PXA0_TIEH_SEL_3_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_M  (EFUSE_PXA0_TIEH_SEL_3_ERR_V << EFUSE_PXA0_TIEH_SEL_3_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_S  6
+/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  8
+/** EFUSE_USB_DEVICE_DREFL_ERR : RO; bitpos: [13:12]; default: 0;
+ *  Indicates a programming error of USB_DEVICE_DREFL.
+ */
+#define EFUSE_USB_DEVICE_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_ERR_M  (EFUSE_USB_DEVICE_DREFL_ERR_V << EFUSE_USB_DEVICE_DREFL_ERR_S)
+#define EFUSE_USB_DEVICE_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_ERR_S  12
+/** EFUSE_USB_OTG11_DREFL_ERR : RO; bitpos: [15:14]; default: 0;
+ *  Indicates a programming error of USB_OTG11_DREFL.
+ */
+#define EFUSE_USB_OTG11_DREFL_ERR    0x00000003U
+#define EFUSE_USB_OTG11_DREFL_ERR_M  (EFUSE_USB_OTG11_DREFL_ERR_V << EFUSE_USB_OTG11_DREFL_ERR_S)
+#define EFUSE_USB_OTG11_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFL_ERR_S  14
+/** EFUSE_HP_PWR_SRC_SEL_ERR : RO; bitpos: [18]; default: 0;
+ *  Indicates a programming error of HP_PWR_SRC_SEL.
+ */
+#define EFUSE_HP_PWR_SRC_SEL_ERR    (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_ERR_M  (EFUSE_HP_PWR_SRC_SEL_ERR_V << EFUSE_HP_PWR_SRC_SEL_ERR_S)
+#define EFUSE_HP_PWR_SRC_SEL_ERR_V  0x00000001U
+#define EFUSE_HP_PWR_SRC_SEL_ERR_S  18
+/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of DCDC_VSET_EN.
+ */
+#define EFUSE_DCDC_VSET_EN_ERR    (BIT(19))
+#define EFUSE_DCDC_VSET_EN_ERR_M  (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S)
+#define EFUSE_DCDC_VSET_EN_ERR_V  0x00000001U
+#define EFUSE_DCDC_VSET_EN_ERR_S  19
+/** EFUSE_DIS_WDT_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of DIS_WDT.
+ */
+#define EFUSE_DIS_WDT_ERR    (BIT(20))
+#define EFUSE_DIS_WDT_ERR_M  (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S)
+#define EFUSE_DIS_WDT_ERR_V  0x00000001U
+#define EFUSE_DIS_WDT_ERR_S  20
+/** EFUSE_DIS_SWD_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of DIS_SWD.
+ */
+#define EFUSE_DIS_SWD_ERR    (BIT(21))
+#define EFUSE_DIS_SWD_ERR_M  (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S)
+#define EFUSE_DIS_SWD_ERR_V  0x00000001U
+#define EFUSE_DIS_SWD_ERR_S  21
+
+/** EFUSE_RD_RS_ERR0_REG register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
+/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_MAC_SYS_ERR_NUM    0x00000007U
+#define EFUSE_MAC_SYS_ERR_NUM_M  (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S)
+#define EFUSE_MAC_SYS_ERR_NUM_V  0x00000007U
+#define EFUSE_MAC_SYS_ERR_NUM_S  0
+/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_MAC_SYS_FAIL    (BIT(3))
+#define EFUSE_MAC_SYS_FAIL_M  (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S)
+#define EFUSE_MAC_SYS_FAIL_V  0x00000001U
+#define EFUSE_MAC_SYS_FAIL_S  3
+/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART1_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART1_ERR_NUM_M  (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S)
+#define EFUSE_SYS_PART1_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART1_ERR_NUM_S  4
+/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART1_FAIL    (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
+#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART1_FAIL_S  7
+/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
+#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  0: Means no failure and that the user data is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
+#define EFUSE_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_USR_DATA_FAIL_S  11
+/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY0_ERR_NUM    0x00000007U
+#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
+#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY0_ERR_NUM_S  12
+/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
+ *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+ *  key0 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY0_FAIL    (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
+#define EFUSE_KEY0_FAIL_V  0x00000001U
+#define EFUSE_KEY0_FAIL_S  15
+/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY1_ERR_NUM    0x00000007U
+#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
+#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY1_ERR_NUM_S  16
+/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
+ *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+ *  key1 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY1_FAIL    (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
+#define EFUSE_KEY1_FAIL_V  0x00000001U
+#define EFUSE_KEY1_FAIL_S  19
+/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY2_ERR_NUM    0x00000007U
+#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
+#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY2_ERR_NUM_S  20
+/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
+ *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+ *  key2 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY2_FAIL    (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
+#define EFUSE_KEY2_FAIL_V  0x00000001U
+#define EFUSE_KEY2_FAIL_S  23
+/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY3_ERR_NUM    0x00000007U
+#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
+#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY3_ERR_NUM_S  24
+/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
+ *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+ *  key3 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY3_FAIL    (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
+#define EFUSE_KEY3_FAIL_V  0x00000001U
+#define EFUSE_KEY3_FAIL_S  27
+/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY4_ERR_NUM    0x00000007U
+#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
+#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY4_ERR_NUM_S  28
+/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
+ *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+ *  key4 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY4_FAIL    (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
+#define EFUSE_KEY4_FAIL_V  0x00000001U
+#define EFUSE_KEY4_FAIL_S  31
+
+/** EFUSE_RD_RS_ERR1_REG register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
+/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY5_ERR_NUM    0x00000007U
+#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
+#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY5_ERR_NUM_S  0
+/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+ *  key5 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY5_FAIL    (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
+#define EFUSE_KEY5_FAIL_V  0x00000001U
+#define EFUSE_KEY5_FAIL_S  3
+/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART2_FAIL    (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
+#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART2_FAIL_S  7
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to force enable eFuse register configuration clock signal.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
+ *  Configures which block to use for ECDSA key output.
+ */
+#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
+#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_S  16
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
+ *  Indicates the number of block valid bit.
+ */
+#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
+ *  Indicates which block is used for ECDSA key output.
+ */
+#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
+#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_S  20
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the read hold time.
+ */
+#define EFUSE_THR_A    0x000000FFU
+#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
+#define EFUSE_THR_A_V  0x000000FFU
+#define EFUSE_THR_A_S  0
+/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
+ *  Configures the read time.
+ */
+#define EFUSE_TRD    0x000000FFU
+#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
+#define EFUSE_TRD_V  0x000000FFU
+#define EFUSE_TRD_S  8
+/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
+ *  Configures the read setup time.
+ */
+#define EFUSE_TSUR_A    0x000000FFU
+#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
+#define EFUSE_TSUR_A_V  0x000000FFU
+#define EFUSE_TSUR_A_S  16
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15;
+ *  Configures the waiting time of reading eFuse memory.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
+/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the programming setup time.
+ */
+#define EFUSE_TSUP_A    0x000000FFU
+#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
+#define EFUSE_TSUP_A_V  0x000000FFU
+#define EFUSE_TSUP_A_S  0
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
+ *  Configures the programming hold time.
+ */
+#define EFUSE_THP_A    0x000000FFU
+#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
+#define EFUSE_THP_A_V  0x000000FFU
+#define EFUSE_THP_A_S  24
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160;
+ *  Configures the active programming time.
+ */
+#define EFUSE_TPGM    0x0000FFFFU
+#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
+#define EFUSE_TPGM_V  0x0000FFFFU
+#define EFUSE_TPGM_S  16
+
+/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
+/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to bypass reed solomon correction step.
+ */
+#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
+#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
+#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
+#define EFUSE_BYPASS_RS_CORRECTION_S  0
+/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
+ *  Configures block number of programming twice operation.
+ */
+#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
+#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_S  1
+/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
+ *  Set this bit to update multi-bit register signals.
+ */
+#define EFUSE_UPDATE    (BIT(12))
+#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
+#define EFUSE_UPDATE_V  0x00000001U
+#define EFUSE_UPDATE_S  12
+/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
+ *  Configures the inactive programming time.
+ */
+#define EFUSE_TPGM_INACTIVE    0x000000FFU
+#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
+#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
+#define EFUSE_TPGM_INACTIVE_S  13
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 36720720;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+/** EFUSE_APB2OTP_WR_DIS_REG register
+ *  eFuse apb2otp block0 data register1.
+ */
+#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x800)
+/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 write disable data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S)
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register
+ *  eFuse apb2otp block0 data register2.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x804)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register
+ *  eFuse apb2otp block0 data register3.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x808)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register
+ *  eFuse apb2otp block0 data register4.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x80c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register
+ *  eFuse apb2otp block0 data register5.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x810)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register
+ *  eFuse apb2otp block0 data register6.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x814)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register
+ *  eFuse apb2otp block0 data register7.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x818)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register
+ *  eFuse apb2otp block0 data register8.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x81c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register
+ *  eFuse apb2otp block0 data register9.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x820)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register
+ *  eFuse apb2otp block0 data register10.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x824)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register
+ *  eFuse apb2otp block0 data register11.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x828)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register
+ *  eFuse apb2otp block0 data register12.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x82c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register
+ *  eFuse apb2otp block0 data register13.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x830)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register
+ *  eFuse apb2otp block0 data register14.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x834)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register
+ *  eFuse apb2otp block0 data register15.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x838)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register
+ *  eFuse apb2otp block0 data register16.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x83c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register
+ *  eFuse apb2otp block0 data register17.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x840)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register
+ *  eFuse apb2otp block0 data register18.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x844)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register
+ *  eFuse apb2otp block0 data register19.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x848)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register
+ *  eFuse apb2otp block0 data register20.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x84c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register
+ *  eFuse apb2otp block0 data register21.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x850)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
+
+/** EFUSE_APB2OTP_BLK1_W1_REG register
+ *  eFuse apb2otp block1 data register1.
+ */
+#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x854)
+/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_M  (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S)
+#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_S  0
+
+/** EFUSE_APB2OTP_BLK1_W2_REG register
+ *  eFuse apb2otp block1 data register2.
+ */
+#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x858)
+/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_M  (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S)
+#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_S  0
+
+/** EFUSE_APB2OTP_BLK1_W3_REG register
+ *  eFuse apb2otp block1 data register3.
+ */
+#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x85c)
+/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_M  (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S)
+#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_S  0
+
+/** EFUSE_APB2OTP_BLK1_W4_REG register
+ *  eFuse apb2otp block1 data register4.
+ */
+#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x860)
+/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_M  (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S)
+#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_S  0
+
+/** EFUSE_APB2OTP_BLK1_W5_REG register
+ *  eFuse apb2otp block1 data register5.
+ */
+#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x864)
+/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_M  (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S)
+#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_S  0
+
+/** EFUSE_APB2OTP_BLK1_W6_REG register
+ *  eFuse apb2otp block1 data register6.
+ */
+#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x868)
+/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_M  (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S)
+#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_S  0
+
+/** EFUSE_APB2OTP_BLK1_W7_REG register
+ *  eFuse apb2otp block1 data register7.
+ */
+#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x86c)
+/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_M  (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S)
+#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_S  0
+
+/** EFUSE_APB2OTP_BLK1_W8_REG register
+ *  eFuse apb2otp block1 data register8.
+ */
+#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x870)
+/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_M  (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S)
+#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_S  0
+
+/** EFUSE_APB2OTP_BLK1_W9_REG register
+ *  eFuse apb2otp block1 data register9.
+ */
+#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x874)
+/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_M  (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S)
+#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_S  0
+
+/** EFUSE_APB2OTP_BLK2_W1_REG register
+ *  eFuse apb2otp block2 data register1.
+ */
+#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x878)
+/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_M  (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S)
+#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_S  0
+
+/** EFUSE_APB2OTP_BLK2_W2_REG register
+ *  eFuse apb2otp block2 data register2.
+ */
+#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x87c)
+/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_M  (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S)
+#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_S  0
+
+/** EFUSE_APB2OTP_BLK2_W3_REG register
+ *  eFuse apb2otp block2 data register3.
+ */
+#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x880)
+/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_M  (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S)
+#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_S  0
+
+/** EFUSE_APB2OTP_BLK2_W4_REG register
+ *  eFuse apb2otp block2 data register4.
+ */
+#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x884)
+/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_M  (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S)
+#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_S  0
+
+/** EFUSE_APB2OTP_BLK2_W5_REG register
+ *  eFuse apb2otp block2 data register5.
+ */
+#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x888)
+/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_M  (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S)
+#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_S  0
+
+/** EFUSE_APB2OTP_BLK2_W6_REG register
+ *  eFuse apb2otp block2 data register6.
+ */
+#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x88c)
+/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_M  (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S)
+#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_S  0
+
+/** EFUSE_APB2OTP_BLK2_W7_REG register
+ *  eFuse apb2otp block2 data register7.
+ */
+#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x890)
+/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_M  (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S)
+#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_S  0
+
+/** EFUSE_APB2OTP_BLK2_W8_REG register
+ *  eFuse apb2otp block2 data register8.
+ */
+#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x894)
+/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_M  (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S)
+#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_S  0
+
+/** EFUSE_APB2OTP_BLK2_W9_REG register
+ *  eFuse apb2otp block2 data register9.
+ */
+#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x898)
+/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_M  (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S)
+#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_S  0
+
+/** EFUSE_APB2OTP_BLK2_W10_REG register
+ *  eFuse apb2otp block2 data register10.
+ */
+#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x89c)
+/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_M  (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S)
+#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_S  0
+
+/** EFUSE_APB2OTP_BLK2_W11_REG register
+ *  eFuse apb2otp block2 data register11.
+ */
+#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x8a0)
+/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_M  (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S)
+#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_S  0
+
+/** EFUSE_APB2OTP_BLK3_W1_REG register
+ *  eFuse apb2otp block3 data register1.
+ */
+#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x8a4)
+/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_M  (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S)
+#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_S  0
+
+/** EFUSE_APB2OTP_BLK3_W2_REG register
+ *  eFuse apb2otp block3 data register2.
+ */
+#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x8a8)
+/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_M  (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S)
+#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_S  0
+
+/** EFUSE_APB2OTP_BLK3_W3_REG register
+ *  eFuse apb2otp block3 data register3.
+ */
+#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x8ac)
+/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_M  (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S)
+#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_S  0
+
+/** EFUSE_APB2OTP_BLK3_W4_REG register
+ *  eFuse apb2otp block3 data register4.
+ */
+#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x8b0)
+/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_M  (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S)
+#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_S  0
+
+/** EFUSE_APB2OTP_BLK3_W5_REG register
+ *  eFuse apb2otp block3 data register5.
+ */
+#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x8b4)
+/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_M  (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S)
+#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_S  0
+
+/** EFUSE_APB2OTP_BLK3_W6_REG register
+ *  eFuse apb2otp block3 data register6.
+ */
+#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x8b8)
+/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_M  (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S)
+#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_S  0
+
+/** EFUSE_APB2OTP_BLK3_W7_REG register
+ *  eFuse apb2otp block3 data register7.
+ */
+#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x8bc)
+/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_M  (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S)
+#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_S  0
+
+/** EFUSE_APB2OTP_BLK3_W8_REG register
+ *  eFuse apb2otp block3 data register8.
+ */
+#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x8c0)
+/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_M  (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S)
+#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_S  0
+
+/** EFUSE_APB2OTP_BLK3_W9_REG register
+ *  eFuse apb2otp block3 data register9.
+ */
+#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x8c4)
+/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_M  (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S)
+#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_S  0
+
+/** EFUSE_APB2OTP_BLK3_W10_REG register
+ *  eFuse apb2otp block3 data register10.
+ */
+#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x8c8)
+/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_M  (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S)
+#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_S  0
+
+/** EFUSE_APB2OTP_BLK3_W11_REG register
+ *  eFuse apb2otp block3 data register11.
+ */
+#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x8cc)
+/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_M  (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S)
+#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_S  0
+
+/** EFUSE_APB2OTP_BLK4_W1_REG register
+ *  eFuse apb2otp block4 data register1.
+ */
+#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x8d0)
+/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_M  (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S)
+#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_S  0
+
+/** EFUSE_APB2OTP_BLK4_W2_REG register
+ *  eFuse apb2otp block4 data register2.
+ */
+#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x8d4)
+/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_M  (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S)
+#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_S  0
+
+/** EFUSE_APB2OTP_BLK4_W3_REG register
+ *  eFuse apb2otp block4 data register3.
+ */
+#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x8d8)
+/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_M  (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S)
+#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_S  0
+
+/** EFUSE_APB2OTP_BLK4_W4_REG register
+ *  eFuse apb2otp block4 data register4.
+ */
+#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x8dc)
+/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_M  (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S)
+#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_S  0
+
+/** EFUSE_APB2OTP_BLK4_W5_REG register
+ *  eFuse apb2otp block4 data register5.
+ */
+#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x8e0)
+/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_M  (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S)
+#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_S  0
+
+/** EFUSE_APB2OTP_BLK4_W6_REG register
+ *  eFuse apb2otp block4 data register6.
+ */
+#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x8e4)
+/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_M  (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S)
+#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_S  0
+
+/** EFUSE_APB2OTP_BLK4_W7_REG register
+ *  eFuse apb2otp block4 data register7.
+ */
+#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x8e8)
+/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_M  (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S)
+#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_S  0
+
+/** EFUSE_APB2OTP_BLK4_W8_REG register
+ *  eFuse apb2otp block4 data register8.
+ */
+#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x8ec)
+/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_M  (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S)
+#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_S  0
+
+/** EFUSE_APB2OTP_BLK4_W9_REG register
+ *  eFuse apb2otp block4 data register9.
+ */
+#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x8f0)
+/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_M  (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S)
+#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_S  0
+
+/** EFUSE_APB2OTP_BLK4_W10_REG register
+ *  eFuse apb2otp block4 data registe10.
+ */
+#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x8f4)
+/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_M  (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S)
+#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_S  0
+
+/** EFUSE_APB2OTP_BLK4_W11_REG register
+ *  eFuse apb2otp block4 data register11.
+ */
+#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x8f8)
+/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_M  (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S)
+#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_S  0
+
+/** EFUSE_APB2OTP_BLK5_W1_REG register
+ *  eFuse apb2otp block5 data register1.
+ */
+#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x8fc)
+/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_M  (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S)
+#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_S  0
+
+/** EFUSE_APB2OTP_BLK5_W2_REG register
+ *  eFuse apb2otp block5 data register2.
+ */
+#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x900)
+/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_M  (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S)
+#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_S  0
+
+/** EFUSE_APB2OTP_BLK5_W3_REG register
+ *  eFuse apb2otp block5 data register3.
+ */
+#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x904)
+/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_M  (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S)
+#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_S  0
+
+/** EFUSE_APB2OTP_BLK5_W4_REG register
+ *  eFuse apb2otp block5 data register4.
+ */
+#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x908)
+/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_M  (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S)
+#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_S  0
+
+/** EFUSE_APB2OTP_BLK5_W5_REG register
+ *  eFuse apb2otp block5 data register5.
+ */
+#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x90c)
+/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_M  (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S)
+#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_S  0
+
+/** EFUSE_APB2OTP_BLK5_W6_REG register
+ *  eFuse apb2otp block5 data register6.
+ */
+#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x910)
+/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_M  (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S)
+#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_S  0
+
+/** EFUSE_APB2OTP_BLK5_W7_REG register
+ *  eFuse apb2otp block5 data register7.
+ */
+#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x914)
+/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_M  (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S)
+#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_S  0
+
+/** EFUSE_APB2OTP_BLK5_W8_REG register
+ *  eFuse apb2otp block5 data register8.
+ */
+#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x918)
+/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_M  (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S)
+#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_S  0
+
+/** EFUSE_APB2OTP_BLK5_W9_REG register
+ *  eFuse apb2otp block5 data register9.
+ */
+#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x91c)
+/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_M  (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S)
+#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_S  0
+
+/** EFUSE_APB2OTP_BLK5_W10_REG register
+ *  eFuse apb2otp block5 data register10.
+ */
+#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x920)
+/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_M  (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S)
+#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_S  0
+
+/** EFUSE_APB2OTP_BLK5_W11_REG register
+ *  eFuse apb2otp block5 data register11.
+ */
+#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x924)
+/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_M  (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S)
+#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_S  0
+
+/** EFUSE_APB2OTP_BLK6_W1_REG register
+ *  eFuse apb2otp block6 data register1.
+ */
+#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x928)
+/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_M  (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S)
+#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_S  0
+
+/** EFUSE_APB2OTP_BLK6_W2_REG register
+ *  eFuse apb2otp block6 data register2.
+ */
+#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x92c)
+/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_M  (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S)
+#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_S  0
+
+/** EFUSE_APB2OTP_BLK6_W3_REG register
+ *  eFuse apb2otp block6 data register3.
+ */
+#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x930)
+/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_M  (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S)
+#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_S  0
+
+/** EFUSE_APB2OTP_BLK6_W4_REG register
+ *  eFuse apb2otp block6 data register4.
+ */
+#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x934)
+/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_M  (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S)
+#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_S  0
+
+/** EFUSE_APB2OTP_BLK6_W5_REG register
+ *  eFuse apb2otp block6 data register5.
+ */
+#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x938)
+/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_M  (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S)
+#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_S  0
+
+/** EFUSE_APB2OTP_BLK6_W6_REG register
+ *  eFuse apb2otp block6 data register6.
+ */
+#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x93c)
+/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_M  (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S)
+#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_S  0
+
+/** EFUSE_APB2OTP_BLK6_W7_REG register
+ *  eFuse apb2otp block6 data register7.
+ */
+#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x940)
+/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_M  (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S)
+#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_S  0
+
+/** EFUSE_APB2OTP_BLK6_W8_REG register
+ *  eFuse apb2otp block6 data register8.
+ */
+#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x944)
+/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_M  (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S)
+#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_S  0
+
+/** EFUSE_APB2OTP_BLK6_W9_REG register
+ *  eFuse apb2otp block6 data register9.
+ */
+#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x948)
+/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_M  (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S)
+#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_S  0
+
+/** EFUSE_APB2OTP_BLK6_W10_REG register
+ *  eFuse apb2otp block6 data register10.
+ */
+#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x94c)
+/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_M  (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S)
+#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_S  0
+
+/** EFUSE_APB2OTP_BLK6_W11_REG register
+ *  eFuse apb2otp block6 data register11.
+ */
+#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x950)
+/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_M  (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S)
+#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_S  0
+
+/** EFUSE_APB2OTP_BLK7_W1_REG register
+ *  eFuse apb2otp block7 data register1.
+ */
+#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x954)
+/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_M  (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S)
+#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_S  0
+
+/** EFUSE_APB2OTP_BLK7_W2_REG register
+ *  eFuse apb2otp block7 data register2.
+ */
+#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x958)
+/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_M  (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S)
+#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_S  0
+
+/** EFUSE_APB2OTP_BLK7_W3_REG register
+ *  eFuse apb2otp block7 data register3.
+ */
+#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x95c)
+/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_M  (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S)
+#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_S  0
+
+/** EFUSE_APB2OTP_BLK7_W4_REG register
+ *  eFuse apb2otp block7 data register4.
+ */
+#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x960)
+/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_M  (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S)
+#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_S  0
+
+/** EFUSE_APB2OTP_BLK7_W5_REG register
+ *  eFuse apb2otp block7 data register5.
+ */
+#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x964)
+/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_M  (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S)
+#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_S  0
+
+/** EFUSE_APB2OTP_BLK7_W6_REG register
+ *  eFuse apb2otp block7 data register6.
+ */
+#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x968)
+/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_M  (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S)
+#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_S  0
+
+/** EFUSE_APB2OTP_BLK7_W7_REG register
+ *  eFuse apb2otp block7 data register7.
+ */
+#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x96c)
+/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_M  (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S)
+#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_S  0
+
+/** EFUSE_APB2OTP_BLK7_W8_REG register
+ *  eFuse apb2otp block7 data register8.
+ */
+#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x970)
+/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_M  (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S)
+#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_S  0
+
+/** EFUSE_APB2OTP_BLK7_W9_REG register
+ *  eFuse apb2otp block7 data register9.
+ */
+#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x974)
+/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_M  (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S)
+#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_S  0
+
+/** EFUSE_APB2OTP_BLK7_W10_REG register
+ *  eFuse apb2otp block7 data register10.
+ */
+#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x978)
+/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_M  (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S)
+#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_S  0
+
+/** EFUSE_APB2OTP_BLK7_W11_REG register
+ *  eFuse apb2otp block7 data register11.
+ */
+#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x97c)
+/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_M  (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S)
+#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_S  0
+
+/** EFUSE_APB2OTP_BLK8_W1_REG register
+ *  eFuse apb2otp block8 data register1.
+ */
+#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x980)
+/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_M  (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S)
+#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_S  0
+
+/** EFUSE_APB2OTP_BLK8_W2_REG register
+ *  eFuse apb2otp block8 data register2.
+ */
+#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x984)
+/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_M  (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S)
+#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_S  0
+
+/** EFUSE_APB2OTP_BLK8_W3_REG register
+ *  eFuse apb2otp block8 data register3.
+ */
+#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x988)
+/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_M  (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S)
+#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_S  0
+
+/** EFUSE_APB2OTP_BLK8_W4_REG register
+ *  eFuse apb2otp block8 data register4.
+ */
+#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x98c)
+/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_M  (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S)
+#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_S  0
+
+/** EFUSE_APB2OTP_BLK8_W5_REG register
+ *  eFuse apb2otp block8 data register5.
+ */
+#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x990)
+/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_M  (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S)
+#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_S  0
+
+/** EFUSE_APB2OTP_BLK8_W6_REG register
+ *  eFuse apb2otp block8 data register6.
+ */
+#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x994)
+/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_M  (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S)
+#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_S  0
+
+/** EFUSE_APB2OTP_BLK8_W7_REG register
+ *  eFuse apb2otp block8 data register7.
+ */
+#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x998)
+/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_M  (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S)
+#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_S  0
+
+/** EFUSE_APB2OTP_BLK8_W8_REG register
+ *  eFuse apb2otp block8 data register8.
+ */
+#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x99c)
+/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_M  (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S)
+#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_S  0
+
+/** EFUSE_APB2OTP_BLK8_W9_REG register
+ *  eFuse apb2otp block8 data register9.
+ */
+#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x9a0)
+/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_M  (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S)
+#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_S  0
+
+/** EFUSE_APB2OTP_BLK8_W10_REG register
+ *  eFuse apb2otp block8 data register10.
+ */
+#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x9a4)
+/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_M  (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S)
+#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_S  0
+
+/** EFUSE_APB2OTP_BLK8_W11_REG register
+ *  eFuse apb2otp block8 data register11.
+ */
+#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x9a8)
+/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_M  (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S)
+#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_S  0
+
+/** EFUSE_APB2OTP_BLK9_W1_REG register
+ *  eFuse apb2otp block9 data register1.
+ */
+#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x9ac)
+/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_M  (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S)
+#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_S  0
+
+/** EFUSE_APB2OTP_BLK9_W2_REG register
+ *  eFuse apb2otp block9 data register2.
+ */
+#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x9b0)
+/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_M  (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S)
+#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_S  0
+
+/** EFUSE_APB2OTP_BLK9_W3_REG register
+ *  eFuse apb2otp block9 data register3.
+ */
+#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x9b4)
+/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_M  (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S)
+#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_S  0
+
+/** EFUSE_APB2OTP_BLK9_W4_REG register
+ *  eFuse apb2otp block9 data register4.
+ */
+#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x9b8)
+/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_M  (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S)
+#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_S  0
+
+/** EFUSE_APB2OTP_BLK9_W5_REG register
+ *  eFuse apb2otp block9 data register5.
+ */
+#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x9bc)
+/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_M  (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S)
+#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_S  0
+
+/** EFUSE_APB2OTP_BLK9_W6_REG register
+ *  eFuse apb2otp block9 data register6.
+ */
+#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x9c0)
+/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_M  (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S)
+#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_S  0
+
+/** EFUSE_APB2OTP_BLK9_W7_REG register
+ *  eFuse apb2otp block9 data register7.
+ */
+#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x9c4)
+/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_M  (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S)
+#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_S  0
+
+/** EFUSE_APB2OTP_BLK9_W8_REG register
+ *  eFuse apb2otp block9 data register8.
+ */
+#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x9c8)
+/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_M  (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S)
+#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_S  0
+
+/** EFUSE_APB2OTP_BLK9_W9_REG register
+ *  eFuse apb2otp block9 data register9.
+ */
+#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x9cc)
+/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_M  (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S)
+#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_S  0
+
+/** EFUSE_APB2OTP_BLK9_W10_REG register
+ *  eFuse apb2otp block9 data register10.
+ */
+#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x9d0)
+/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_M  (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S)
+#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_S  0
+
+/** EFUSE_APB2OTP_BLK9_W11_REG register
+ *  eFuse apb2otp block9 data register11.
+ */
+#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x9d4)
+/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_M  (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S)
+#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_S  0
+
+/** EFUSE_APB2OTP_BLK10_W1_REG register
+ *  eFuse apb2otp block10 data register1.
+ */
+#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x9d8)
+/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_M  (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S)
+#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_S  0
+
+/** EFUSE_APB2OTP_BLK10_W2_REG register
+ *  eFuse apb2otp block10 data register2.
+ */
+#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x9dc)
+/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_M  (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S)
+#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_S  0
+
+/** EFUSE_APB2OTP_BLK10_W3_REG register
+ *  eFuse apb2otp block10 data register3.
+ */
+#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x9e0)
+/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_M  (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S)
+#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_S  0
+
+/** EFUSE_APB2OTP_BLK10_W4_REG register
+ *  eFuse apb2otp block10 data register4.
+ */
+#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x9e4)
+/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_M  (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S)
+#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_S  0
+
+/** EFUSE_APB2OTP_BLK10_W5_REG register
+ *  eFuse apb2otp block10 data register5.
+ */
+#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x9e8)
+/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_M  (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S)
+#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_S  0
+
+/** EFUSE_APB2OTP_BLK10_W6_REG register
+ *  eFuse apb2otp block10 data register6.
+ */
+#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x9ec)
+/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_M  (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S)
+#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_S  0
+
+/** EFUSE_APB2OTP_BLK10_W7_REG register
+ *  eFuse apb2otp block10 data register7.
+ */
+#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x9f0)
+/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_M  (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S)
+#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_S  0
+
+/** EFUSE_APB2OTP_BLK10_W8_REG register
+ *  eFuse apb2otp block10 data register8.
+ */
+#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x9f4)
+/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_M  (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S)
+#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_S  0
+
+/** EFUSE_APB2OTP_BLK10_W9_REG register
+ *  eFuse apb2otp block10 data register9.
+ */
+#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x9f8)
+/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_M  (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S)
+#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_S  0
+
+/** EFUSE_APB2OTP_BLK10_W10_REG register
+ *  eFuse apb2otp block10 data register10.
+ */
+#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x9fc)
+/** EFUSE_APB2OTP_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK19_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK19_W10_M  (EFUSE_APB2OTP_BLOCK19_W10_V << EFUSE_APB2OTP_BLOCK19_W10_S)
+#define EFUSE_APB2OTP_BLOCK19_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK19_W10_S  0
+
+/** EFUSE_APB2OTP_BLK10_W11_REG register
+ *  eFuse apb2otp block10 data register11.
+ */
+#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0xa00)
+/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_M  (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S)
+#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_S  0
+
+/** EFUSE_APB2OTP_EN_REG register
+ *  eFuse apb2otp enable configuration register.
+ */
+#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0xa08)
+/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
+ *  Apb2otp mode enable signal.
+ */
+#define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
+#define EFUSE_APB2OTP_APB2OTP_EN_M  (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S)
+#define EFUSE_APB2OTP_APB2OTP_EN_V  0x00000001U
+#define EFUSE_APB2OTP_APB2OTP_EN_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h
new file mode 100644
index 0000000000..b153ab070f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h
@@ -0,0 +1,4737 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13421
+
+/** Group: PGM Data Register */
+/** Type of pgm_data0 register
+ *  Register 0 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Register 1 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Register 2 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Register 3 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 3rd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Register 4 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 4th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Register 5 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 5th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Register 6 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 6th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Register 7 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 7th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+/** Type of pgm_check_value0 register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: ******** Registers */
+/** Type of rd_wr_dis register
+ *  BLOCK0 data register 0.
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled or
+         *  enabled. 1: Disabled. 0 Enabled.
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  BLOCK0 data register 1.
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t rd_dis:7;
+        /** usb_device_exchg_pins : RO; bitpos: [7]; default: 0;
+         *  Enable usb device exchange pins of D+ and D-.
+         */
+        uint32_t usb_device_exchg_pins:1;
+        /** usb_otg11_exchg_pins : RO; bitpos: [8]; default: 0;
+         *  Enable usb otg11 exchange pins of D+ and D-.
+         */
+        uint32_t usb_otg11_exchg_pins:1;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** powerglitch_en : RO; bitpos: [10]; default: 0;
+         *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+         */
+        uint32_t powerglitch_en:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
+         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Represents whether the function that forces chip into download mode is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
+         *  boot_mode_download.
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+         *  is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+         *  enabled.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+         *  enabled.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+         *  mode). 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** usb_device_drefh : RO; bitpos: [22:21]; default: 0;
+         *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
+         */
+        uint32_t usb_device_drefh:2;
+        /** usb_otg11_drefh : RO; bitpos: [24:23]; default: 0;
+         *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+         */
+        uint32_t usb_otg11_drefh:2;
+        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
+         *  TBD
+         */
+        uint32_t usb_phy_sel:1;
+        /** km_huk_gen_state_low : RO; bitpos: [31:26]; default: 0;
+         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+         *  of 1 is valid.
+         */
+        uint32_t km_huk_gen_state_low:6;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  BLOCK0 data register 2.
+ */
+typedef union {
+    struct {
+        /** km_huk_gen_state_high : RO; bitpos: [2:0]; default: 0;
+         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+         *  of 1 is valid.
+         */
+        uint32_t km_huk_gen_state_high:3;
+        /** km_rnd_switch_cycle : RO; bitpos: [4:3]; default: 0;
+         *  Set bits to control key manager random number switch cycle. 0: control by register.
+         *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
+         */
+        uint32_t km_rnd_switch_cycle:2;
+        /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0;
+         *  Set each bit to control whether corresponding key can only be deployed once. 1 is
+         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+         */
+        uint32_t km_deploy_only_once:4;
+        /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0;
+         *  Set each bit to control whether corresponding key must come from key manager.. 1 is
+         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+         */
+        uint32_t force_use_key_manager_key:4;
+        /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable software written init key, and force use efuse_init_key.
+         */
+        uint32_t force_disable_sw_init_key:1;
+        /** xts_key_length_256 : RO; bitpos: [14]; default: 0;
+         *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
+         */
+        uint32_t xts_key_length_256:1;
+        /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_79:1;
+        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
+         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+         *  selected. 0: not selected.
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+         *  1: enabled. Even number of 1: disabled.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Represents the purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Represents the purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  BLOCK0 data register 3.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Represents the purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Represents the purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Represents the purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Represents the purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
+         *  Represents the spa secure level by configuring the clock random divide mode.
+         */
+        uint32_t sec_dpa_level:2;
+        /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0;
+         *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
+         *  0: not force used.
+         */
+        uint32_t ecdsa_enable_soft_k:1;
+        /** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
+         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+         */
+        uint32_t crypt_dpa_enable:1;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** rd_reserve_0_118 : RW; bitpos: [22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_118:1;
+        /** flash_type : RO; bitpos: [23]; default: 0;
+         *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
+         */
+        uint32_t flash_type:1;
+        /** flash_page_size : RO; bitpos: [25:24]; default: 0;
+         *  Set flash page size.
+         */
+        uint32_t flash_page_size:2;
+        /** flash_ecc_en : RO; bitpos: [26]; default: 0;
+         *  Set this bit to enable ecc for flash boot.
+         */
+        uint32_t flash_ecc_en:1;
+        /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0;
+         *  Set this bit to disable download via USB-OTG.
+         */
+        uint32_t dis_usb_otg_download_mode:1;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Represents the flash waiting time after power-up, in unit of ms. When the value
+         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+         *  is 2 times the programmed value.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  BLOCK0 data register 4.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
+         *  0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** lock_km_key : RO; bitpos: [3]; default: 0;
+         *  TBD
+         */
+        uint32_t lock_km_key:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+         *  disabled.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Represents the type of UART printing. 00: force enable printing. 01: enable
+         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+         *  at high level. 11: force disable printing.
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [8]; default: 0;
+         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+         *  forced. 0:not forced.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [24:9]; default: 0;
+         *  Represents the version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
+         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** hys_en_pad : RO; bitpos: [26]; default: 0;
+         *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
+         *  enabled. 0:disabled.
+         */
+        uint32_t hys_en_pad:1;
+        /** dcdc_vset : RO; bitpos: [31:27]; default: 0;
+         *  Set the dcdc voltage default.
+         */
+        uint32_t dcdc_vset:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  BLOCK0 data register 5.
+ */
+typedef union {
+    struct {
+        /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
+         *  TBD
+         */
+        uint32_t pxa0_tieh_sel_0:2;
+        /** pxa0_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
+         *  TBD.
+         */
+        uint32_t pxa0_tieh_sel_1:2;
+        /** pxa0_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
+         *  TBD.
+         */
+        uint32_t pxa0_tieh_sel_2:2;
+        /** pxa0_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
+         *  TBD.
+         */
+        uint32_t pxa0_tieh_sel_3:2;
+        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
+         *  TBD.
+         */
+        uint32_t km_disable_deploy_mode:4;
+        /** usb_device_drefl : RO; bitpos: [13:12]; default: 0;
+         *  Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step
+         *  of 80 mV.
+         */
+        uint32_t usb_device_drefl:2;
+        /** usb_otg11_drefl : RO; bitpos: [15:14]; default: 0;
+         *  Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step
+         *  of 80 mV.
+         */
+        uint32_t usb_otg11_drefl:2;
+        /** rd_reserve_0_176 : RW; bitpos: [17:16]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_176:2;
+        /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
+         *  HP system power source select. 0:LDO. 1: DCDC.
+         */
+        uint32_t hp_pwr_src_sel:1;
+        /** dcdc_vset_en : RO; bitpos: [19]; default: 0;
+         *  Select dcdc vset use efuse_dcdc_vset.
+         */
+        uint32_t dcdc_vset_en:1;
+        /** dis_wdt : RO; bitpos: [20]; default: 0;
+         *  Set this bit to disable watch dog.
+         */
+        uint32_t dis_wdt:1;
+        /** dis_swd : RO; bitpos: [21]; default: 0;
+         *  Set this bit to disable super-watchdog.
+         */
+        uint32_t dis_swd:1;
+        /** rd_reserve_0_182 : RW; bitpos: [31:22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_182:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+/** Type of rd_mac_sys_0 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the low 32 bits of MAC address.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_0_reg_t;
+
+/** Type of rd_mac_sys_1 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Stores the high 16 bits of MAC address.
+         */
+        uint32_t mac_1:16;
+        /** reserved_1_16 : RO; bitpos: [31:16]; default: 0;
+         *  Stores the extended bits of MAC address.
+         */
+        uint32_t reserved_1_16:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_1_reg_t;
+
+/** Type of rd_mac_sys_2 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** wafer_version_minor : R; bitpos: [3:0]; default: 0;
+         *  Minor chip version
+         */
+        uint32_t wafer_version_minor:4;
+        /** wafer_version_major_lo : R; bitpos: [5:4]; default: 0;
+         *  Major chip version (lower 2 bits)
+         */
+        uint32_t wafer_version_major_lo:2;
+        /** disable_wafer_version_major : R; bitpos: [6]; default: 0;
+         *  Disables check of wafer version major
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** blk_version_minor : R; bitpos: [10:8]; default: 0;
+         *  BLK_VERSION_MINOR of BLOCK2
+         */
+        uint32_t blk_version_minor:3;
+        /** blk_version_major : R; bitpos: [12:11]; default: 0;
+         *  BLK_VERSION_MAJOR of BLOCK2
+         */
+        uint32_t blk_version_major:2;
+        /** psram_cap : R; bitpos: [15:13]; default: 0;
+         *  PSRAM capacity
+         */
+        uint32_t psram_cap:3;
+        /** temp : R; bitpos: [17:16]; default: 0;
+         *  Operating temperature of the ESP chip
+         */
+        uint32_t temp:2;
+        /** psram_vendor : R; bitpos: [19:18]; default: 0;
+         *  PSRAM vendor
+         */
+        uint32_t psram_vendor:2;
+        /** pkg_version : R; bitpos: [22:20]; default: 0;
+         *  Package version
+         */
+        uint32_t pkg_version:3;
+        /** wafer_version_major_hi : R; bitpos: [23]; default: 0;
+         *  Major chip version (MSB)
+         */
+        uint32_t wafer_version_major_hi:1;
+        /** ldo_vo1_dref : R; bitpos: [27:24]; default: 0;
+         *  Output VO1 parameter
+         */
+        uint32_t ldo_vo1_dref:4;
+        /** ldo_vo2_dref : R; bitpos: [31:28]; default: 0;
+         *  Output VO2 parameter
+         */
+        uint32_t ldo_vo2_dref:4;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_2_reg_t;
+
+/** Type of rd_mac_sys_3 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** ldo_vo1_mul : R; bitpos: [2:0]; default: 0;
+         *  Output VO1 parameter
+         */
+        uint32_t ldo_vo1_mul:3;
+        /** ldo_vo2_mul : R; bitpos: [5:3]; default: 0;
+         *  Output VO2 parameter
+         */
+        uint32_t ldo_vo2_mul:3;
+        /** ldo_vo3_k : R; bitpos: [13:6]; default: 0;
+         *  Output VO3 calibration parameter
+         */
+        uint32_t ldo_vo3_k:8;
+        /** ldo_vo3_vos : R; bitpos: [19:14]; default: 0;
+         *  Output VO3 calibration parameter
+         */
+        uint32_t ldo_vo3_vos:6;
+        /** ldo_vo3_c : R; bitpos: [25:20]; default: 0;
+         *  Output VO3 calibration parameter
+         */
+        uint32_t ldo_vo3_c:6;
+        /** ldo_vo4_k : R; bitpos: [31:26]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_k:6;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_3_reg_t;
+
+/** Type of rd_mac_sys_4 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** ldo_vo4_k_1 : R; bitpos: [1:0]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_k_1:2;
+        /** ldo_vo4_vos : R; bitpos: [7:2]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_vos:6;
+        /** ldo_vo4_c : R; bitpos: [13:8]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_c:6;
+        /** reserved_1_142 : R; bitpos: [15:14]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_142:2;
+        /** active_hp_dbias : R; bitpos: [19:16]; default: 0;
+         *  Active HP DBIAS of fixed voltage
+         */
+        uint32_t active_hp_dbias:4;
+        /** active_lp_dbias : R; bitpos: [23:20]; default: 0;
+         *  Active LP DBIAS of fixed voltage
+         */
+        uint32_t active_lp_dbias:4;
+        /** lslp_hp_dbias : R; bitpos: [27:24]; default: 0;
+         *  LSLP HP DBIAS of fixed voltage
+         */
+        uint32_t lslp_hp_dbias:4;
+        /** dslp_dbg : R; bitpos: [31:28]; default: 0;
+         *  DSLP BDG of fixed voltage
+         */
+        uint32_t dslp_dbg:4;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_4_reg_t;
+
+/** Type of rd_mac_sys_5 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** dslp_lp_dbias : R; bitpos: [4:0]; default: 0;
+         *  DSLP LP DBIAS of fixed voltage
+         */
+        uint32_t dslp_lp_dbias:5;
+        /** lp_dcdc_dbias_vol_gap : R; bitpos: [9:5]; default: 0;
+         *  DBIAS gap between LP and DCDC
+         */
+        uint32_t lp_dcdc_dbias_vol_gap:5;
+        /** reserved_1_170 : R; bitpos: [31:10]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_170:22;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_5_reg_t;
+
+/** Type of rd_sys_part1_data0 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_ave_initcode_atten0 : R; bitpos: [9:0]; default: 0;
+         *  Average initcode of ADC1 atten0
+         */
+        uint32_t adc1_ave_initcode_atten0:10;
+        /** adc1_ave_initcode_atten1 : R; bitpos: [19:10]; default: 0;
+         *  Average initcode of ADC1 atten1
+         */
+        uint32_t adc1_ave_initcode_atten1:10;
+        /** adc1_ave_initcode_atten2 : R; bitpos: [29:20]; default: 0;
+         *  Average initcode of ADC1 atten2
+         */
+        uint32_t adc1_ave_initcode_atten2:10;
+        /** adc1_ave_initcode_atten3 : R; bitpos: [31:30]; default: 0;
+         *  Average initcode of ADC1 atten3
+         */
+        uint32_t adc1_ave_initcode_atten3:2;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_ave_initcode_atten3_1 : R; bitpos: [7:0]; default: 0;
+         *  Average initcode of ADC1 atten3
+         */
+        uint32_t adc1_ave_initcode_atten3_1:8;
+        /** adc2_ave_initcode_atten0 : R; bitpos: [17:8]; default: 0;
+         *  Average initcode of ADC2 atten0
+         */
+        uint32_t adc2_ave_initcode_atten0:10;
+        /** adc2_ave_initcode_atten1 : R; bitpos: [27:18]; default: 0;
+         *  Average initcode of ADC2 atten1
+         */
+        uint32_t adc2_ave_initcode_atten1:10;
+        /** adc2_ave_initcode_atten2 : R; bitpos: [31:28]; default: 0;
+         *  Average initcode of ADC2 atten2
+         */
+        uint32_t adc2_ave_initcode_atten2:4;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc2_ave_initcode_atten2_1 : R; bitpos: [5:0]; default: 0;
+         *  Average initcode of ADC2 atten2
+         */
+        uint32_t adc2_ave_initcode_atten2_1:6;
+        /** adc2_ave_initcode_atten3 : R; bitpos: [15:6]; default: 0;
+         *  Average initcode of ADC2 atten3
+         */
+        uint32_t adc2_ave_initcode_atten3:10;
+        /** adc1_hi_dout_atten0 : R; bitpos: [25:16]; default: 0;
+         *  HI_DOUT of ADC1 atten0
+         */
+        uint32_t adc1_hi_dout_atten0:10;
+        /** adc1_hi_dout_atten1 : R; bitpos: [31:26]; default: 0;
+         *  HI_DOUT of ADC1 atten1
+         */
+        uint32_t adc1_hi_dout_atten1:6;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_hi_dout_atten1_1 : R; bitpos: [3:0]; default: 0;
+         *  HI_DOUT of ADC1 atten1
+         */
+        uint32_t adc1_hi_dout_atten1_1:4;
+        /** adc1_hi_dout_atten2 : R; bitpos: [13:4]; default: 0;
+         *  HI_DOUT of ADC1 atten2
+         */
+        uint32_t adc1_hi_dout_atten2:10;
+        /** adc1_hi_dout_atten3 : R; bitpos: [23:14]; default: 0;
+         *  HI_DOUT of ADC1 atten3
+         */
+        uint32_t adc1_hi_dout_atten3:10;
+        /** reserved_2_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_248:8;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+/** Type of rd_usr_data0 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_192:8;
+        /** custom_mac : R; bitpos: [31:8]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac:24;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac_1:24;
+        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_248:8;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+/** Type of rd_key0_data0 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+/** Type of rd_key1_data0 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+/** Type of rd_key2_data0 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+/** Type of rd_key3_data0 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+/** Type of rd_key4_data0 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+/** Type of rd_key5_data0 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+/** Type of rd_sys_part2_data0 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** adc2_hi_dout_atten0 : R; bitpos: [9:0]; default: 0;
+         *  HI_DOUT of ADC2 atten0
+         */
+        uint32_t adc2_hi_dout_atten0:10;
+        /** adc2_hi_dout_atten1 : R; bitpos: [19:10]; default: 0;
+         *  HI_DOUT of ADC2 atten1
+         */
+        uint32_t adc2_hi_dout_atten1:10;
+        /** adc2_hi_dout_atten2 : R; bitpos: [29:20]; default: 0;
+         *  HI_DOUT of ADC2 atten2
+         */
+        uint32_t adc2_hi_dout_atten2:10;
+        /** adc2_hi_dout_atten3 : R; bitpos: [31:30]; default: 0;
+         *  HI_DOUT of ADC2 atten3
+         */
+        uint32_t adc2_hi_dout_atten3:2;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** adc2_hi_dout_atten3_1 : R; bitpos: [7:0]; default: 0;
+         *  HI_DOUT of ADC2 atten3
+         */
+        uint32_t adc2_hi_dout_atten3_1:8;
+        /** adc1_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
+         *  Gap between ADC1_ch0 and average initcode
+         */
+        uint32_t adc1_ch0_atten0_initcode_diff:4;
+        /** adc1_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
+         *  Gap between ADC1_ch1 and average initcode
+         */
+        uint32_t adc1_ch1_atten0_initcode_diff:4;
+        /** adc1_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
+         *  Gap between ADC1_ch2 and average initcode
+         */
+        uint32_t adc1_ch2_atten0_initcode_diff:4;
+        /** adc1_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
+         *  Gap between ADC1_ch3 and average initcode
+         */
+        uint32_t adc1_ch3_atten0_initcode_diff:4;
+        /** adc1_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
+         *  Gap between ADC1_ch4 and average initcode
+         */
+        uint32_t adc1_ch4_atten0_initcode_diff:4;
+        /** adc1_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
+         *  Gap between ADC1_ch5 and average initcode
+         */
+        uint32_t adc1_ch5_atten0_initcode_diff:4;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_ch6_atten0_initcode_diff : R; bitpos: [3:0]; default: 0;
+         *  Gap between ADC1_ch6 and average initcode
+         */
+        uint32_t adc1_ch6_atten0_initcode_diff:4;
+        /** adc1_ch7_atten0_initcode_diff : R; bitpos: [7:4]; default: 0;
+         *  Gap between ADC1_ch7 and average initcode
+         */
+        uint32_t adc1_ch7_atten0_initcode_diff:4;
+        /** adc2_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
+         *  Gap between ADC2_ch0 and average initcode
+         */
+        uint32_t adc2_ch0_atten0_initcode_diff:4;
+        /** adc2_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
+         *  Gap between ADC2_ch1 and average initcode
+         */
+        uint32_t adc2_ch1_atten0_initcode_diff:4;
+        /** adc2_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
+         *  Gap between ADC2_ch2 and average initcode
+         */
+        uint32_t adc2_ch2_atten0_initcode_diff:4;
+        /** adc2_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
+         *  Gap between ADC2_ch3 and average initcode
+         */
+        uint32_t adc2_ch3_atten0_initcode_diff:4;
+        /** adc2_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
+         *  Gap between ADC2_ch4 and average initcode
+         */
+        uint32_t adc2_ch4_atten0_initcode_diff:4;
+        /** adc2_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
+         *  Gap between ADC2_ch5 and average initcode
+         */
+        uint32_t adc2_ch5_atten0_initcode_diff:4;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** temperature_sensor : R; bitpos: [8:0]; default: 0;
+         *  Temperature calibration data
+         */
+        uint32_t temperature_sensor:9;
+        /** reserved_10_105 : R; bitpos: [31:9]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_10_105:23;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+/** Type of rd_repeat_err0 register
+ *  Programming error record register 0 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Indicates a programming error of RD_DIS.
+         */
+        uint32_t rd_dis_err:7;
+        /** dis_usb_device_exchg_pins_err : RO; bitpos: [7]; default: 0;
+         *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
+         */
+        uint32_t dis_usb_device_exchg_pins_err:1;
+        /** dis_usb_otg11_exchg_pins_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
+         */
+        uint32_t dis_usb_otg11_exchg_pins_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  Indicates a programming error of DIS_USB_JTAG.
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** powerglitch_en_err : RO; bitpos: [10]; default: 0;
+         *  Indicates a programming error of POWERGLITCH_EN.
+         */
+        uint32_t powerglitch_en_err:1;
+        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+         */
+        uint32_t dis_usb_serial_jtag_err:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  Indicates a programming error of DIS_TWAI.
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  Indicates a programming error of JTAG_SEL_ENABLE.
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  Indicates a programming error of SOFT_DIS_JTAG.
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of DIS_PAD_JTAG.
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** usb_device_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  Indicates a programming error of USB_DEVICE_DREFH.
+         */
+        uint32_t usb_device_drefh_err:2;
+        /** usb_otg11_drefh_err : RO; bitpos: [24:23]; default: 0;
+         *  Indicates a programming error of USB_OTG11_DREFH.
+         */
+        uint32_t usb_otg11_drefh_err:2;
+        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of USB_PHY_SEL.
+         */
+        uint32_t usb_phy_sel_err:1;
+        /** huk_gen_state_low_err : RO; bitpos: [31:26]; default: 0;
+         *  Indicates a programming error of HUK_GEN_STATE_LOW.
+         */
+        uint32_t huk_gen_state_low_err:6;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err0_reg_t;
+
+/** Type of rd_repeat_err1 register
+ *  Programming error record register 1 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** km_huk_gen_state_high_err : RO; bitpos: [2:0]; default: 0;
+         *  Indicates a programming error of HUK_GEN_STATE_HIGH.
+         */
+        uint32_t km_huk_gen_state_high_err:3;
+        /** km_rnd_switch_cycle_err : RO; bitpos: [4:3]; default: 0;
+         *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
+         */
+        uint32_t km_rnd_switch_cycle_err:2;
+        /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0;
+         *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
+         */
+        uint32_t km_deploy_only_once_err:4;
+        /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0;
+         *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
+         */
+        uint32_t force_use_key_manager_key_err:4;
+        /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
+         */
+        uint32_t force_disable_sw_init_key_err:1;
+        /** xts_key_length_256_err : RO; bitpos: [14]; default: 0;
+         *  Indicates a programming error of XTS_KEY_LENGTH_256.
+         */
+        uint32_t xts_key_length_256_err:1;
+        uint32_t reserved_15:1;
+        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of WDT_DELAY_SEL.
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_0.
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_1.
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err1_reg_t;
+
+/** Type of rd_repeat_err2 register
+ *  Programming error record register 2 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_2.
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_3.
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_4.
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_5.
+         */
+        uint32_t key_purpose_5_err:4;
+        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of SEC_DPA_LEVEL.
+         */
+        uint32_t sec_dpa_level_err:2;
+        /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0;
+         *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
+         */
+        uint32_t ecdsa_enable_soft_k_err:1;
+        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of CRYPT_DPA_ENABLE.
+         */
+        uint32_t crypt_dpa_enable_err:1;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_EN.
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        uint32_t reserved_22:1;
+        /** flash_type_err : RO; bitpos: [23]; default: 0;
+         *  Indicates a programming error of FLASH_TYPE.
+         */
+        uint32_t flash_type_err:1;
+        /** flash_page_size_err : RO; bitpos: [25:24]; default: 0;
+         *  Indicates a programming error of FLASH_PAGE_SIZE.
+         */
+        uint32_t flash_page_size_err:2;
+        /** flash_ecc_en_err : RO; bitpos: [26]; default: 0;
+         *  Indicates a programming error of FLASH_ECC_EN.
+         */
+        uint32_t flash_ecc_en_err:1;
+        /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0;
+         *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_otg_download_mode_err:1;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of FLASH_TPUW.
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err2_reg_t;
+
+/** Type of rd_repeat_err3 register
+ *  Programming error record register 3 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
+         *  Indicates a programming error of DIS_DIRECT_BOOT.
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print_err:1;
+        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
+         *  TBD
+         */
+        uint32_t lock_km_key_err:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  Indicates a programming error of UART_PRINT_CONTROL.
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of FORCE_SEND_RESUME.
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
+         *  Indicates a programming error of SECURE VERSION.
+         */
+        uint32_t secure_version_err:16;
+        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+         */
+        uint32_t secure_boot_disable_fast_wake_err:1;
+        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
+         *  Indicates a programming error of HYS_EN_PAD.
+         */
+        uint32_t hys_en_pad_err:1;
+        /** dcdc_vset_err : RO; bitpos: [31:27]; default: 0;
+         *  Indicates a programming error of DCDC_VSET.
+         */
+        uint32_t dcdc_vset_err:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err3_reg_t;
+
+/** Type of rd_repeat_err4 register
+ *  Programming error record register 4 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_0.
+         */
+        uint32_t pxa0_tieh_sel_0_err:2;
+        /** pxa0_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_1.
+         */
+        uint32_t pxa0_tieh_sel_1_err:2;
+        /** pxa0_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_2.
+         */
+        uint32_t pxa0_tieh_sel_2_err:2;
+        /** pxa0_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_3.
+         */
+        uint32_t pxa0_tieh_sel_3_err:2;
+        /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
+         *  TBD.
+         */
+        uint32_t km_disable_deploy_mode_err:4;
+        /** usb_device_drefl_err : RO; bitpos: [13:12]; default: 0;
+         *  Indicates a programming error of USB_DEVICE_DREFL.
+         */
+        uint32_t usb_device_drefl_err:2;
+        /** usb_otg11_drefl_err : RO; bitpos: [15:14]; default: 0;
+         *  Indicates a programming error of USB_OTG11_DREFL.
+         */
+        uint32_t usb_otg11_drefl_err:2;
+        uint32_t reserved_16:2;
+        /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0;
+         *  Indicates a programming error of HP_PWR_SRC_SEL.
+         */
+        uint32_t hp_pwr_src_sel_err:1;
+        /** dcdc_vset_en_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of DCDC_VSET_EN.
+         */
+        uint32_t dcdc_vset_en_err:1;
+        /** dis_wdt_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of DIS_WDT.
+         */
+        uint32_t dis_wdt_err:1;
+        /** dis_swd_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of DIS_SWD.
+         */
+        uint32_t dis_swd_err:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err4_reg_t;
+
+/** Type of rd_rs_err0 register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t mac_sys_err_num:3;
+        /** mac_sys_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t mac_sys_fail:1;
+        /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part1_err_num:3;
+        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part1_fail:1;
+        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t usr_data_err_num:3;
+        /** usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  0: Means no failure and that the user data is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t usr_data_fail:1;
+        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key0_err_num:3;
+        /** key0_fail : RO; bitpos: [15]; default: 0;
+         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+         *  key0 failed and the number of error bytes is over 6.
+         */
+        uint32_t key0_fail:1;
+        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key1_err_num:3;
+        /** key1_fail : RO; bitpos: [19]; default: 0;
+         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+         *  key1 failed and the number of error bytes is over 6.
+         */
+        uint32_t key1_fail:1;
+        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key2_err_num:3;
+        /** key2_fail : RO; bitpos: [23]; default: 0;
+         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+         *  key2 failed and the number of error bytes is over 6.
+         */
+        uint32_t key2_fail:1;
+        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key3_err_num:3;
+        /** key3_fail : RO; bitpos: [27]; default: 0;
+         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+         *  key3 failed and the number of error bytes is over 6.
+         */
+        uint32_t key3_fail:1;
+        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key4_err_num:3;
+        /** key4_fail : RO; bitpos: [31]; default: 0;
+         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+         *  key4 failed and the number of error bytes is over 6.
+         */
+        uint32_t key4_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_err0_reg_t;
+
+/** Type of rd_rs_err1 register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key5_err_num:3;
+        /** key5_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+         *  key5 failed and the number of error bytes is over 6.
+         */
+        uint32_t key5_fail:1;
+        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part2_err_num:3;
+        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part2_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_err1_reg_t;
+
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to force enable eFuse register configuration clock signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+         */
+        uint32_t op_code:16;
+        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
+         *  Configures which block to use for ECDSA key output.
+         */
+        uint32_t cfg_ecdsa_blk:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
+         *  Indicates which block is used for ECDSA key output.
+         */
+        uint32_t cur_ecdsa_blk:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
+         *  Configures the waiting time of reading eFuse memory.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 160;
+         *  Configures the active programming time.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to bypass reed solomon correction step.
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures block number of programming twice operation.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Set this bit to update multi-bit register signals.
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: EFUSE Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36720720;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
+/** Type of apb2otp_wr_dis register
+ *  eFuse apb2otp block0 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 write disable data.
+         */
+        uint32_t apb2otp_block0_wr_dis:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_wr_dis_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
+/** Type of apb2otp_blk0_backup1_w1 register
+ *  eFuse apb2otp block0 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word1 data.
+         */
+        uint32_t apb2otp_block0_backup1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
+/** Type of apb2otp_blk0_backup1_w2 register
+ *  eFuse apb2otp block0 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word2 data.
+         */
+        uint32_t apb2otp_block0_backup1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
+/** Type of apb2otp_blk0_backup1_w3 register
+ *  eFuse apb2otp block0 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word3 data.
+         */
+        uint32_t apb2otp_block0_backup1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
+/** Type of apb2otp_blk0_backup1_w4 register
+ *  eFuse apb2otp block0 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word4 data.
+         */
+        uint32_t apb2otp_block0_backup1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
+/** Type of apb2otp_blk0_backup1_w5 register
+ *  eFuse apb2otp block0 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word5 data.
+         */
+        uint32_t apb2otp_block0_backup1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
+/** Type of apb2otp_blk0_backup2_w1 register
+ *  eFuse apb2otp block0 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word1 data.
+         */
+        uint32_t apb2otp_block0_backup2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
+/** Type of apb2otp_blk0_backup2_w2 register
+ *  eFuse apb2otp block0 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word2 data.
+         */
+        uint32_t apb2otp_block0_backup2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
+/** Type of apb2otp_blk0_backup2_w3 register
+ *  eFuse apb2otp block0 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word3 data.
+         */
+        uint32_t apb2otp_block0_backup2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
+/** Type of apb2otp_blk0_backup2_w4 register
+ *  eFuse apb2otp block0 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word4 data.
+         */
+        uint32_t apb2otp_block0_backup2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
+/** Type of apb2otp_blk0_backup2_w5 register
+ *  eFuse apb2otp block0 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word5 data.
+         */
+        uint32_t apb2otp_block0_backup2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
+/** Type of apb2otp_blk0_backup3_w1 register
+ *  eFuse apb2otp block0 data register12.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word1 data.
+         */
+        uint32_t apb2otp_block0_backup3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
+/** Type of apb2otp_blk0_backup3_w2 register
+ *  eFuse apb2otp block0 data register13.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word2 data.
+         */
+        uint32_t apb2otp_block0_backup3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
+/** Type of apb2otp_blk0_backup3_w3 register
+ *  eFuse apb2otp block0 data register14.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word3 data.
+         */
+        uint32_t apb2otp_block0_backup3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
+/** Type of apb2otp_blk0_backup3_w4 register
+ *  eFuse apb2otp block0 data register15.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word4 data.
+         */
+        uint32_t apb2otp_block0_backup3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
+/** Type of apb2otp_blk0_backup3_w5 register
+ *  eFuse apb2otp block0 data register16.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word5 data.
+         */
+        uint32_t apb2otp_block0_backup3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
+/** Type of apb2otp_blk0_backup4_w1 register
+ *  eFuse apb2otp block0 data register17.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word1 data.
+         */
+        uint32_t apb2otp_block0_backup4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
+/** Type of apb2otp_blk0_backup4_w2 register
+ *  eFuse apb2otp block0 data register18.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word2 data.
+         */
+        uint32_t apb2otp_block0_backup4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
+/** Type of apb2otp_blk0_backup4_w3 register
+ *  eFuse apb2otp block0 data register19.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word3 data.
+         */
+        uint32_t apb2otp_block0_backup4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
+/** Type of apb2otp_blk0_backup4_w4 register
+ *  eFuse apb2otp block0 data register20.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word4 data.
+         */
+        uint32_t apb2otp_block0_backup4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
+/** Type of apb2otp_blk0_backup4_w5 register
+ *  eFuse apb2otp block0 data register21.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word5 data.
+         */
+        uint32_t apb2otp_block0_backup4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word1 Data */
+/** Type of apb2otp_blk1_w1 register
+ *  eFuse apb2otp block1 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word1 data.
+         */
+        uint32_t apb2otp_block1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word2 Data */
+/** Type of apb2otp_blk1_w2 register
+ *  eFuse apb2otp block1 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word2 data.
+         */
+        uint32_t apb2otp_block1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word3 Data */
+/** Type of apb2otp_blk1_w3 register
+ *  eFuse apb2otp block1 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word3 data.
+         */
+        uint32_t apb2otp_block1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word4 Data */
+/** Type of apb2otp_blk1_w4 register
+ *  eFuse apb2otp block1 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word4 data.
+         */
+        uint32_t apb2otp_block1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word5 Data */
+/** Type of apb2otp_blk1_w5 register
+ *  eFuse apb2otp block1 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word5 data.
+         */
+        uint32_t apb2otp_block1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word6 Data */
+/** Type of apb2otp_blk1_w6 register
+ *  eFuse apb2otp block1 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word6 data.
+         */
+        uint32_t apb2otp_block1_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word7 Data */
+/** Type of apb2otp_blk1_w7 register
+ *  eFuse apb2otp block1 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word7 data.
+         */
+        uint32_t apb2otp_block1_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word8 Data */
+/** Type of apb2otp_blk1_w8 register
+ *  eFuse apb2otp block1 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word8 data.
+         */
+        uint32_t apb2otp_block1_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word9 Data */
+/** Type of apb2otp_blk1_w9 register
+ *  eFuse apb2otp block1 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word9 data.
+         */
+        uint32_t apb2otp_block1_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word1 Data */
+/** Type of apb2otp_blk2_w1 register
+ *  eFuse apb2otp block2 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word1 data.
+         */
+        uint32_t apb2otp_block2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word2 Data */
+/** Type of apb2otp_blk2_w2 register
+ *  eFuse apb2otp block2 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word2 data.
+         */
+        uint32_t apb2otp_block2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word3 Data */
+/** Type of apb2otp_blk2_w3 register
+ *  eFuse apb2otp block2 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word3 data.
+         */
+        uint32_t apb2otp_block2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word4 Data */
+/** Type of apb2otp_blk2_w4 register
+ *  eFuse apb2otp block2 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word4 data.
+         */
+        uint32_t apb2otp_block2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word5 Data */
+/** Type of apb2otp_blk2_w5 register
+ *  eFuse apb2otp block2 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word5 data.
+         */
+        uint32_t apb2otp_block2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word6 Data */
+/** Type of apb2otp_blk2_w6 register
+ *  eFuse apb2otp block2 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word6 data.
+         */
+        uint32_t apb2otp_block2_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word7 Data */
+/** Type of apb2otp_blk2_w7 register
+ *  eFuse apb2otp block2 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word7 data.
+         */
+        uint32_t apb2otp_block2_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word8 Data */
+/** Type of apb2otp_blk2_w8 register
+ *  eFuse apb2otp block2 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word8 data.
+         */
+        uint32_t apb2otp_block2_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word9 Data */
+/** Type of apb2otp_blk2_w9 register
+ *  eFuse apb2otp block2 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word9 data.
+         */
+        uint32_t apb2otp_block2_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word10 Data */
+/** Type of apb2otp_blk2_w10 register
+ *  eFuse apb2otp block2 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word10 data.
+         */
+        uint32_t apb2otp_block2_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word11 Data */
+/** Type of apb2otp_blk2_w11 register
+ *  eFuse apb2otp block2 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word11 data.
+         */
+        uint32_t apb2otp_block2_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w11_reg_t;
+
+/** Type of apb2otp_blk10_w11 register
+ *  eFuse apb2otp block10 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word11 data.
+         */
+        uint32_t apb2otp_block10_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word1 Data */
+/** Type of apb2otp_blk3_w1 register
+ *  eFuse apb2otp block3 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word1 data.
+         */
+        uint32_t apb2otp_block3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word2 Data */
+/** Type of apb2otp_blk3_w2 register
+ *  eFuse apb2otp block3 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word2 data.
+         */
+        uint32_t apb2otp_block3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word3 Data */
+/** Type of apb2otp_blk3_w3 register
+ *  eFuse apb2otp block3 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word3 data.
+         */
+        uint32_t apb2otp_block3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word4 Data */
+/** Type of apb2otp_blk3_w4 register
+ *  eFuse apb2otp block3 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word4 data.
+         */
+        uint32_t apb2otp_block3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word5 Data */
+/** Type of apb2otp_blk3_w5 register
+ *  eFuse apb2otp block3 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word5 data.
+         */
+        uint32_t apb2otp_block3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word6 Data */
+/** Type of apb2otp_blk3_w6 register
+ *  eFuse apb2otp block3 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word6 data.
+         */
+        uint32_t apb2otp_block3_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word7 Data */
+/** Type of apb2otp_blk3_w7 register
+ *  eFuse apb2otp block3 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word7 data.
+         */
+        uint32_t apb2otp_block3_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word8 Data */
+/** Type of apb2otp_blk3_w8 register
+ *  eFuse apb2otp block3 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word8 data.
+         */
+        uint32_t apb2otp_block3_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word9 Data */
+/** Type of apb2otp_blk3_w9 register
+ *  eFuse apb2otp block3 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word9 data.
+         */
+        uint32_t apb2otp_block3_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word10 Data */
+/** Type of apb2otp_blk3_w10 register
+ *  eFuse apb2otp block3 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word10 data.
+         */
+        uint32_t apb2otp_block3_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word11 Data */
+/** Type of apb2otp_blk3_w11 register
+ *  eFuse apb2otp block3 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word11 data.
+         */
+        uint32_t apb2otp_block3_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word1 Data */
+/** Type of apb2otp_blk4_w1 register
+ *  eFuse apb2otp block4 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word1 data.
+         */
+        uint32_t apb2otp_block4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word2 Data */
+/** Type of apb2otp_blk4_w2 register
+ *  eFuse apb2otp block4 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word2 data.
+         */
+        uint32_t apb2otp_block4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word3 Data */
+/** Type of apb2otp_blk4_w3 register
+ *  eFuse apb2otp block4 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word3 data.
+         */
+        uint32_t apb2otp_block4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word4 Data */
+/** Type of apb2otp_blk4_w4 register
+ *  eFuse apb2otp block4 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word4 data.
+         */
+        uint32_t apb2otp_block4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word5 Data */
+/** Type of apb2otp_blk4_w5 register
+ *  eFuse apb2otp block4 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word5 data.
+         */
+        uint32_t apb2otp_block4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word6 Data */
+/** Type of apb2otp_blk4_w6 register
+ *  eFuse apb2otp block4 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word6 data.
+         */
+        uint32_t apb2otp_block4_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word7 Data */
+/** Type of apb2otp_blk4_w7 register
+ *  eFuse apb2otp block4 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word7 data.
+         */
+        uint32_t apb2otp_block4_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word8 Data */
+/** Type of apb2otp_blk4_w8 register
+ *  eFuse apb2otp block4 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word8 data.
+         */
+        uint32_t apb2otp_block4_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word9 Data */
+/** Type of apb2otp_blk4_w9 register
+ *  eFuse apb2otp block4 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word9 data.
+         */
+        uint32_t apb2otp_block4_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word10 Data */
+/** Type of apb2otp_blk4_w10 register
+ *  eFuse apb2otp block4 data registe10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word10 data.
+         */
+        uint32_t apb2otp_block4_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word11 Data */
+/** Type of apb2otp_blk4_w11 register
+ *  eFuse apb2otp block4 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word11 data.
+         */
+        uint32_t apb2otp_block4_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word1 Data */
+/** Type of apb2otp_blk5_w1 register
+ *  eFuse apb2otp block5 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word1 data.
+         */
+        uint32_t apb2otp_block5_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word2 Data */
+/** Type of apb2otp_blk5_w2 register
+ *  eFuse apb2otp block5 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word2 data.
+         */
+        uint32_t apb2otp_block5_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word3 Data */
+/** Type of apb2otp_blk5_w3 register
+ *  eFuse apb2otp block5 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word3 data.
+         */
+        uint32_t apb2otp_block5_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word4 Data */
+/** Type of apb2otp_blk5_w4 register
+ *  eFuse apb2otp block5 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word4 data.
+         */
+        uint32_t apb2otp_block5_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word5 Data */
+/** Type of apb2otp_blk5_w5 register
+ *  eFuse apb2otp block5 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word5 data.
+         */
+        uint32_t apb2otp_block5_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word6 Data */
+/** Type of apb2otp_blk5_w6 register
+ *  eFuse apb2otp block5 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word6 data.
+         */
+        uint32_t apb2otp_block5_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word7 Data */
+/** Type of apb2otp_blk5_w7 register
+ *  eFuse apb2otp block5 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word7 data.
+         */
+        uint32_t apb2otp_block5_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word8 Data */
+/** Type of apb2otp_blk5_w8 register
+ *  eFuse apb2otp block5 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word8 data.
+         */
+        uint32_t apb2otp_block5_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word9 Data */
+/** Type of apb2otp_blk5_w9 register
+ *  eFuse apb2otp block5 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word9 data.
+         */
+        uint32_t apb2otp_block5_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word10 Data */
+/** Type of apb2otp_blk5_w10 register
+ *  eFuse apb2otp block5 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word10 data.
+         */
+        uint32_t apb2otp_block5_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word11 Data */
+/** Type of apb2otp_blk5_w11 register
+ *  eFuse apb2otp block5 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word11 data.
+         */
+        uint32_t apb2otp_block5_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word1 Data */
+/** Type of apb2otp_blk6_w1 register
+ *  eFuse apb2otp block6 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word1 data.
+         */
+        uint32_t apb2otp_block6_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word2 Data */
+/** Type of apb2otp_blk6_w2 register
+ *  eFuse apb2otp block6 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word2 data.
+         */
+        uint32_t apb2otp_block6_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word3 Data */
+/** Type of apb2otp_blk6_w3 register
+ *  eFuse apb2otp block6 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word3 data.
+         */
+        uint32_t apb2otp_block6_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word4 Data */
+/** Type of apb2otp_blk6_w4 register
+ *  eFuse apb2otp block6 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word4 data.
+         */
+        uint32_t apb2otp_block6_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word5 Data */
+/** Type of apb2otp_blk6_w5 register
+ *  eFuse apb2otp block6 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word5 data.
+         */
+        uint32_t apb2otp_block6_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word6 Data */
+/** Type of apb2otp_blk6_w6 register
+ *  eFuse apb2otp block6 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word6 data.
+         */
+        uint32_t apb2otp_block6_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word7 Data */
+/** Type of apb2otp_blk6_w7 register
+ *  eFuse apb2otp block6 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word7 data.
+         */
+        uint32_t apb2otp_block6_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word8 Data */
+/** Type of apb2otp_blk6_w8 register
+ *  eFuse apb2otp block6 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word8 data.
+         */
+        uint32_t apb2otp_block6_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word9 Data */
+/** Type of apb2otp_blk6_w9 register
+ *  eFuse apb2otp block6 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word9 data.
+         */
+        uint32_t apb2otp_block6_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word10 Data */
+/** Type of apb2otp_blk6_w10 register
+ *  eFuse apb2otp block6 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word10 data.
+         */
+        uint32_t apb2otp_block6_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word11 Data */
+/** Type of apb2otp_blk6_w11 register
+ *  eFuse apb2otp block6 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word11 data.
+         */
+        uint32_t apb2otp_block6_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word1 Data */
+/** Type of apb2otp_blk7_w1 register
+ *  eFuse apb2otp block7 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word1 data.
+         */
+        uint32_t apb2otp_block7_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word2 Data */
+/** Type of apb2otp_blk7_w2 register
+ *  eFuse apb2otp block7 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word2 data.
+         */
+        uint32_t apb2otp_block7_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word3 Data */
+/** Type of apb2otp_blk7_w3 register
+ *  eFuse apb2otp block7 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word3 data.
+         */
+        uint32_t apb2otp_block7_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word4 Data */
+/** Type of apb2otp_blk7_w4 register
+ *  eFuse apb2otp block7 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word4 data.
+         */
+        uint32_t apb2otp_block7_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word5 Data */
+/** Type of apb2otp_blk7_w5 register
+ *  eFuse apb2otp block7 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word5 data.
+         */
+        uint32_t apb2otp_block7_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word6 Data */
+/** Type of apb2otp_blk7_w6 register
+ *  eFuse apb2otp block7 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word6 data.
+         */
+        uint32_t apb2otp_block7_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word7 Data */
+/** Type of apb2otp_blk7_w7 register
+ *  eFuse apb2otp block7 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word7 data.
+         */
+        uint32_t apb2otp_block7_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word8 Data */
+/** Type of apb2otp_blk7_w8 register
+ *  eFuse apb2otp block7 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word8 data.
+         */
+        uint32_t apb2otp_block7_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word9 Data */
+/** Type of apb2otp_blk7_w9 register
+ *  eFuse apb2otp block7 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word9 data.
+         */
+        uint32_t apb2otp_block7_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word10 Data */
+/** Type of apb2otp_blk7_w10 register
+ *  eFuse apb2otp block7 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word10 data.
+         */
+        uint32_t apb2otp_block7_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word11 Data */
+/** Type of apb2otp_blk7_w11 register
+ *  eFuse apb2otp block7 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word11 data.
+         */
+        uint32_t apb2otp_block7_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word1 Data */
+/** Type of apb2otp_blk8_w1 register
+ *  eFuse apb2otp block8 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word1 data.
+         */
+        uint32_t apb2otp_block8_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word2 Data */
+/** Type of apb2otp_blk8_w2 register
+ *  eFuse apb2otp block8 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word2 data.
+         */
+        uint32_t apb2otp_block8_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word3 Data */
+/** Type of apb2otp_blk8_w3 register
+ *  eFuse apb2otp block8 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word3 data.
+         */
+        uint32_t apb2otp_block8_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word4 Data */
+/** Type of apb2otp_blk8_w4 register
+ *  eFuse apb2otp block8 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word4 data.
+         */
+        uint32_t apb2otp_block8_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word5 Data */
+/** Type of apb2otp_blk8_w5 register
+ *  eFuse apb2otp block8 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word5 data.
+         */
+        uint32_t apb2otp_block8_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word6 Data */
+/** Type of apb2otp_blk8_w6 register
+ *  eFuse apb2otp block8 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word6 data.
+         */
+        uint32_t apb2otp_block8_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word7 Data */
+/** Type of apb2otp_blk8_w7 register
+ *  eFuse apb2otp block8 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word7 data.
+         */
+        uint32_t apb2otp_block8_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word8 Data */
+/** Type of apb2otp_blk8_w8 register
+ *  eFuse apb2otp block8 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word8 data.
+         */
+        uint32_t apb2otp_block8_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word9 Data */
+/** Type of apb2otp_blk8_w9 register
+ *  eFuse apb2otp block8 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word9 data.
+         */
+        uint32_t apb2otp_block8_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word10 Data */
+/** Type of apb2otp_blk8_w10 register
+ *  eFuse apb2otp block8 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word10 data.
+         */
+        uint32_t apb2otp_block8_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word11 Data */
+/** Type of apb2otp_blk8_w11 register
+ *  eFuse apb2otp block8 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word11 data.
+         */
+        uint32_t apb2otp_block8_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word1 Data */
+/** Type of apb2otp_blk9_w1 register
+ *  eFuse apb2otp block9 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word1 data.
+         */
+        uint32_t apb2otp_block9_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word2 Data */
+/** Type of apb2otp_blk9_w2 register
+ *  eFuse apb2otp block9 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word2 data.
+         */
+        uint32_t apb2otp_block9_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word3 Data */
+/** Type of apb2otp_blk9_w3 register
+ *  eFuse apb2otp block9 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word3 data.
+         */
+        uint32_t apb2otp_block9_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word4 Data */
+/** Type of apb2otp_blk9_w4 register
+ *  eFuse apb2otp block9 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word4 data.
+         */
+        uint32_t apb2otp_block9_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word5 Data */
+/** Type of apb2otp_blk9_w5 register
+ *  eFuse apb2otp block9 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word5 data.
+         */
+        uint32_t apb2otp_block9_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word6 Data */
+/** Type of apb2otp_blk9_w6 register
+ *  eFuse apb2otp block9 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word6 data.
+         */
+        uint32_t apb2otp_block9_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word7 Data */
+/** Type of apb2otp_blk9_w7 register
+ *  eFuse apb2otp block9 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word7 data.
+         */
+        uint32_t apb2otp_block9_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word8 Data */
+/** Type of apb2otp_blk9_w8 register
+ *  eFuse apb2otp block9 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word8 data.
+         */
+        uint32_t apb2otp_block9_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word9 Data */
+/** Type of apb2otp_blk9_w9 register
+ *  eFuse apb2otp block9 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word9 data.
+         */
+        uint32_t apb2otp_block9_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word10 Data */
+/** Type of apb2otp_blk9_w10 register
+ *  eFuse apb2otp block9 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word10 data.
+         */
+        uint32_t apb2otp_block9_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word11 Data */
+/** Type of apb2otp_blk9_w11 register
+ *  eFuse apb2otp block9 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word11 data.
+         */
+        uint32_t apb2otp_block9_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word1 Data */
+/** Type of apb2otp_blk10_w1 register
+ *  eFuse apb2otp block10 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word1 data.
+         */
+        uint32_t apb2otp_block10_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word2 Data */
+/** Type of apb2otp_blk10_w2 register
+ *  eFuse apb2otp block10 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word2 data.
+         */
+        uint32_t apb2otp_block10_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word3 Data */
+/** Type of apb2otp_blk10_w3 register
+ *  eFuse apb2otp block10 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word3 data.
+         */
+        uint32_t apb2otp_block10_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word4 Data */
+/** Type of apb2otp_blk10_w4 register
+ *  eFuse apb2otp block10 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word4 data.
+         */
+        uint32_t apb2otp_block10_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word5 Data */
+/** Type of apb2otp_blk10_w5 register
+ *  eFuse apb2otp block10 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word5 data.
+         */
+        uint32_t apb2otp_block10_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word6 Data */
+/** Type of apb2otp_blk10_w6 register
+ *  eFuse apb2otp block10 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word6 data.
+         */
+        uint32_t apb2otp_block10_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word7 Data */
+/** Type of apb2otp_blk10_w7 register
+ *  eFuse apb2otp block10 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word7 data.
+         */
+        uint32_t apb2otp_block10_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word8 Data */
+/** Type of apb2otp_blk10_w8 register
+ *  eFuse apb2otp block10 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word8 data.
+         */
+        uint32_t apb2otp_block10_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word9 Data */
+/** Type of apb2otp_blk10_w9 register
+ *  eFuse apb2otp block10 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word9 data.
+         */
+        uint32_t apb2otp_block10_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word10 Data */
+/** Type of apb2otp_blk10_w10 register
+ *  eFuse apb2otp block10 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word10 data.
+         */
+        uint32_t apb2otp_block19_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Function Enable Signal */
+/** Type of apb2otp_en register
+ *  eFuse apb2otp enable configuration register.
+ */
+typedef union {
+    struct {
+        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
+         *  Apb2otp mode enable signal.
+         */
+        uint32_t apb2otp_apb2otp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} efuse_apb2otp_en_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0;
+    volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1;
+    volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2;
+    volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3;
+    volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4;
+    volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
+    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
+    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
+    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
+    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
+    uint32_t reserved_190[12];
+    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
+    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+    volatile efuse_date_reg_t date;
+    uint32_t reserved_200[384];
+    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
+    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
+    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
+    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
+    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
+    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
+    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
+    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
+    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
+    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
+    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
+    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
+    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
+    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
+    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
+    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
+    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
+    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
+    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
+    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
+    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
+    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
+    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
+    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
+    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
+    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
+    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
+    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
+    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
+    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
+    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
+    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
+    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
+    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
+    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
+    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
+    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
+    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
+    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
+    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
+    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
+    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
+    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
+    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
+    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
+    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
+    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
+    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
+    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
+    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
+    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
+    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
+    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
+    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
+    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
+    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
+    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
+    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
+    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
+    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
+    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
+    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
+    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
+    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
+    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
+    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
+    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
+    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
+    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
+    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
+    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
+    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
+    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
+    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
+    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
+    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
+    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
+    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
+    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
+    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
+    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
+    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
+    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
+    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
+    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
+    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
+    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
+    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
+    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
+    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
+    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
+    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
+    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
+    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
+    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
+    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
+    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
+    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
+    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
+    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
+    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
+    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
+    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
+    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
+    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
+    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
+    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
+    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
+    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
+    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
+    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
+    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
+    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
+    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
+    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
+    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
+    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
+    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
+    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
+    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
+    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
+    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
+    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
+    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
+    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
+    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
+    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
+    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
+    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
+    uint32_t reserved_a04;
+    volatile efuse_apb2otp_en_reg_t apb2otp_en;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/emac_dma_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/emac_dma_struct.h
new file mode 100644
index 0000000000..5607737825
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/emac_dma_struct.h
@@ -0,0 +1,154 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+
+typedef struct emac_dma_dev_s {
+    volatile union {
+        struct {
+            uint32_t sw_rst : 1;         /*When this bit is set  the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC  you should read a zero (0) value in this bit.*/
+            uint32_t dma_arb_sch : 1;    /*This bit specifies the arbitration scheme between the transmit and receive paths.1'b0: weighted round-robin with RX:TX or TX:RX  priority specified in PR (bit[15:14]). 1'b1 Fixed priority (Rx priority to Tx).*/
+            uint32_t desc_skip_len : 5;  /*This bit specifies the number of Word to skip between two unchained descriptors.The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL(DESC_SKIP_LEN) value is equal to zero  the descriptor table is taken as contiguous by the DMA in Ring mode.*/
+            uint32_t alt_desc_size : 1;  /*When set  the size of the alternate descriptor increases to 32 bytes.*/
+            uint32_t prog_burst_len : 6; /*These bits indicate the maximum number of beats to be transferred in one DMA transaction. If the number of beats to be transferred is more than 32  then perform the following steps: 1. Set the PBLx8 mode  2. Set the PBL(PROG_BURST_LEN).*/
+            uint32_t pri_ratio : 2;      /*These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx represented by each bit:  2'b00 -- 1: 1    2'b01 -- 2: 0    2'b10 -- 3: 1    2'b11 -- 4: 1*/
+            uint32_t fixed_burst : 1;    /*This bit controls whether the AHB master interface performs fixed burst transfers or not. When set  the AHB interface uses only SINGLE  INCR4  INCR8  or INCR16 during start of the normal burst transfers. When reset  the AHB interface uses SINGLE and INCR burst transfer Operations.*/
+            uint32_t rx_dma_pbl : 6;     /*This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst transfer on the host bus. You can program RPBL with values of 1  2  4  8  16  and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL) is set high.*/
+            uint32_t use_sep_pbl : 1;    /*When set high  this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When reset to low  the PBL value in Bits[13:8] is applicable for both DMA engines.*/
+            uint32_t pblx8_mode : 1;     /*When set high  this bit multiplies the programmed PBL value (Bits[22:17] and Bits[13:8]) eight times. Therefore  the DMA transfers the data in 8  16  32  64  128  and 256 beats depending on the PBL value.*/
+            uint32_t dmaaddralibea : 1;  /*When this bit is set high and the FIXED_BURST bit is 1  the AHB interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0  the first burst (accessing the start address of data buffer) is not aligned  but subsequent bursts are aligned to the address.*/
+            uint32_t dmamixedburst : 1;  /*When this bit is set high and the FIXED_BURST bit is low  the AHB master interface starts all bursts of a length more than 16 with INCR (undefined burst)  whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less.*/
+            uint32_t reserved27 : 1;
+            uint32_t reserved28 : 2;
+            uint32_t reserved30 : 1;
+            uint32_t reserved31 : 1;
+        };
+        uint32_t val;
+    } dmabusmode;
+    uint32_t dmatxpolldemand; /*When these bits are written with any value  the DMA reads the current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host)  the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available  the transmission resumes.*/
+    uint32_t dmarxpolldemand; /*When these bits are written with any value  the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host)  the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available  the Rx DMA returns to the active state.*/
+    uint32_t dmarxbaseaddr;   /*This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.*/
+    uint32_t dmatxbaseaddr;   /*This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore  these LSB bits are read-only.*/
+    volatile union {
+        struct {
+            uint32_t trans_int : 1;         /*This bit indicates that the frame transmission is complete. When transmission is complete  Bit[31] (OWN) of TDES0 is reset  and the specific frame status information is updated in the Descriptor.*/
+            uint32_t trans_proc_stop : 1;   /*This bit is set when the transmission is stopped.*/
+            uint32_t trans_buf_unavail : 1; /*This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors  the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand Command.*/
+            uint32_t trans_jabber_to : 1;   /*This bit indicates that the Transmit Jabber Timer expired  which happens when the frame size exceeds 2 048 (10 240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs  the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.*/
+            uint32_t recv_ovflow : 1;       /*This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application  the overflow status is set in RDES0[11].*/
+            uint32_t trans_undflow : 1;     /*This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.*/
+            uint32_t recv_int : 1;          /*This bit indicates that the frame reception is complete. When reception is complete  the Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor  and the specific frame status information is updated in the descriptor. The reception remains in the Running state.*/
+            uint32_t recv_buf_unavail : 1;  /*This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors  the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued  the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA.*/
+            uint32_t recv_proc_stop : 1;    /*This bit is asserted when the Receive Process enters the Stopped state.*/
+            uint32_t recv_wdt_to : 1;       /*When set  this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout.*/
+            uint32_t early_trans_int : 1;   /*This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO.*/
+            uint32_t reserved11 : 2;
+            uint32_t fatal_bus_err_int : 1; /*This bit indicates that a bus error occurred  as described in Bits [25:23]. When this bit is set  the corresponding DMA engine disables all of its bus accesses.*/
+            uint32_t early_recv_int : 1;    /*This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whichever occurs earlier).*/
+            uint32_t abn_int_summ : 1;      /*Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Interrupt Enable Register:   Bit[1]: Transmit Process Stopped.  Bit[3]: Transmit Jabber Timeout.  Bit[4]: Receive FIFO Overflow.  Bit[5]: Transmit Underflow.  Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped.  Bit[9]: Receive Watchdog Timeout.  Bit[10]: Early Transmit Interrupt.  Bit[13]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes AIS to be set  is cleared.*/
+            uint32_t norm_int_summ : 1;     /*Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Interrupt Enable Register:  Bit[0]: Transmit Interrupt.  Bit[2]: Transmit Buffer Unavailable.  Bit[6]: Receive Interrupt.  Bit[14]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set  is cleared.*/
+            uint32_t recv_proc_state : 3;   /*This field indicates the Receive DMA FSM state. This field does not generate an interrupt.  3'b000: Stopped. Reset or Stop Receive Command issued.  3'b001: Running. Fetching Receive Transfer Descriptor.  3'b010: Reserved for future use.  3'b011: Running. Waiting for RX packets.  3'b100: Suspended. Receive Descriptor Unavailable.  3'b101: Running. Closing Receive Descriptor.  3'b110: TIME_STAMP write state.  3'b111: Running. Transferring the TX packets data from receive buffer to host memory.*/
+            uint32_t trans_proc_state : 3;  /*This field indicates the Transmit DMA FSM state. This field does not generate an interrupt.  3'b000: Stopped. Reset or Stop Transmit Command issued.  3'b001: Running. Fetching Transmit Transfer Descriptor.  3'b010: Reserved for future use.  3'b011: Running. Waiting for TX packets.  3'b100: Suspended. Receive Descriptor Unavailable.  3'b101: Running. Closing Transmit Descriptor.  3'b110: TIME_STAMP write state.  3'b111: Running. Transferring the TX packets data from transmit buffer to host memory.*/
+            uint32_t error_bits : 3;        /*This field indicates the type of error that caused a Bus Error  for example  error response on the AHB interface. This field is valid only when Bit[13] (FBI) is set. This field does not generate an interrupt.  3'b000: Error during Rx DMA Write Data Transfer.  3'b011: Error during Tx DMA Read Data Transfer.  3'b100: Error during Rx DMA Descriptor Write Access.  3'b101: Error during Tx DMA Descriptor Write Access.  3'b110: Error during Rx DMA Descriptor Read Access.  3'b111: Error during Tx DMA Descriptor Read Access.*/
+            uint32_t reserved26 : 1;
+            uint32_t reserved27 : 1;
+            uint32_t pmt_int : 1;    /*This bit indicates an interrupt event in the PMT module of the ETH_MAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0.*/
+            uint32_t ts_tri_int : 1; /*This bit indicates an interrupt event in the Timestamp Generator block of the ETH_MAC.The software must read the corresponding registers in the ETH_MAC to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0.*/
+            uint32_t reserved30 : 1;
+            uint32_t reserved31 : 1;
+        };
+        uint32_t val;
+    } dmastatus;
+    volatile union {
+        struct {
+            uint32_t reserved0 : 1;
+            uint32_t start_stop_rx : 1;    /*When this bit is set  the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared  the Rx DMA operation is stopped after the transfer of the current frame.*/
+            uint32_t opt_second_frame : 1; /*When this bit is set  it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained.*/
+            uint32_t rx_thresh_ctrl : 2;   /*These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. 2'b00: 64， 2'b01: 32， 2'b10: 96， 2'b11: 128 .*/
+            uint32_t drop_gfrm : 1;        /*When set  the MAC drops the received giant frames in the Rx FIFO  that is frames that are larger than the computed giant frame limit.*/
+            uint32_t fwd_under_gf : 1;     /*When set  the Rx FIFO forwards Undersized frames (that is  frames with no Error and length less than 64 bytes) including pad-bytes and CRC.*/
+            uint32_t fwd_err_frame : 1;    /*When this bit is reset  the Rx FIFO drops frames with error status (CRC error collision error   giant frame  watchdog timeout  or overflow).*/
+            uint32_t reserved8 : 1;
+            uint32_t reserved9 : 2;
+            uint32_t reserved11 : 2;
+            uint32_t start_stop_transmission_command : 1; /*When this bit is set  transmission is placed in the Running state  and the DMA checks the Transmit List at the current position for a frame to be transmitted.When this bit is reset  the transmission process is placed in the Stopped state after completing the transmission of the current frame.*/
+            uint32_t tx_thresh_ctrl : 3;                  /*These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition  full frames with a length less than the threshold are also transmitted. These bits are used only when Tx_Str_fwd is reset. 3'b000: 64  3'b001: 128   3'b010: 192   3'b011: 256  3'b100: 40  3'b101: 32  3'b110: 24  3'b111: 16 .*/
+            uint32_t reserved17 : 3;
+            uint32_t flush_tx_fifo : 1; /*When this bit is set  the transmit FIFO controller logic is reset to its default values  and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete.*/
+            uint32_t tx_str_fwd : 1;    /*When this bit is set  transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set  the Tx_Thresh_Ctrl values specified in Tx_Thresh_Ctrl are ignored.*/
+            uint32_t reserved22 : 1;
+            uint32_t reserved23 : 1;
+            uint32_t dis_flush_recv_frames : 1;   /*When this bit is set  the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers.*/
+            uint32_t rx_store_forward : 1;        /*When this bit is set  the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it.*/
+            uint32_t dis_drop_tcpip_err_fram : 1; /*When this bit is set  the MAC does not drop the frames which only have errors detected by the Receive Checksum engine.When this bit is reset  all error frames are dropped if the Fwd_Err_Frame bit is reset.*/
+            uint32_t reserved27 : 5;
+        };
+        uint32_t val;
+    } dmaoperation_mode;
+    volatile union {
+        struct {
+            uint32_t dmain_tie : 1;  /*When this bit is set with Normal Interrupt Summary Enable (Bit[16])  the Transmit Interrupt is enabled. When this bit is reset  the Transmit Interrupt is disabled.*/
+            uint32_t dmain_tse : 1;  /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Transmission Stopped Interrupt is enabled. When this bit is reset  the Transmission Stopped Interrupt is disabled.*/
+            uint32_t dmain_tbue : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit 16)  the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset  the Transmit Buffer Unavailable Interrupt is Disabled.*/
+            uint32_t dmain_tjte : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset  the Transmit Jabber Timeout Interrupt is disabled.*/
+            uint32_t dmain_oie : 1;  /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Receive Overflow Interrupt is enabled. When this bit is reset  the Overflow Interrupt is disabled.*/
+            uint32_t dmain_uie : 1;  /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Transmit Underflow Interrupt is enabled. When this bit is reset  the Underflow Interrupt is disabled.*/
+            uint32_t dmain_rie : 1;  /*When this bit is set with Normal Interrupt Summary Enable (Bit[16])  the Receive Interrupt is enabled. When this bit is reset  the Receive Interrupt is disabled.*/
+            uint32_t dmain_rbue : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset  the Receive Buffer Unavailable Interrupt is disabled.*/
+            uint32_t dmain_rse : 1;  /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Receive Stopped Interrupt is enabled. When this bit is reset  the Receive Stopped Interrupt is disabled.*/
+            uint32_t dmain_rwte : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset  the Receive Watchdog Timeout Interrupt is disabled.*/
+            uint32_t dmain_etie : 1; /*When this bit is set with an Abnormal Interrupt Summary Enable (Bit[15])  the Early Transmit Interrupt is enabled. When this bit is reset  the Early Transmit Interrupt is disabled.*/
+            uint32_t reserved11 : 2;
+            uint32_t dmain_fbee : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Fatal Bus Error Interrupt is enabled. When this bit is reset  the Fatal Bus Error Enable Interrupt is disabled.*/
+            uint32_t dmain_erie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16])  the Early Receive Interrupt is enabled. When this bit is reset  the Early Receive Interrupt is disabled.*/
+            uint32_t dmain_aise : 1; /*When this bit is set  abnormal interrupt summary is enabled. When this bit is reset the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status Register:  Bit[1]: Transmit Process Stopped.  Bit[3]: Transmit Jabber Timeout.  Bit[4]: Receive Overflow.  Bit[5]: Transmit Underflow.  Bit[7]: Receive Buffer Unavailable.  Bit[8]: Receive Process Stopped.  Bit[9]: Receive Watchdog Timeout.  Bit[10]: Early Transmit Interrupt.  Bit[13]: Fatal Bus Error.*/
+            uint32_t dmain_nise : 1; /*When this bit is set  normal interrupt summary is enabled. When this bit is reset  normal interrupt summary is disabled. This bit enables the following interrupts in Status Register:  Bit[0]: Transmit Interrupt.  Bit[2]: Transmit Buffer Unavailable.  Bit[6]: Receive Interrupt.  Bit[14]: Early Receive Interrupt.*/
+            uint32_t reserved17 : 15;
+        };
+        uint32_t val;
+    } dmain_en;
+    volatile union {
+        struct {
+            uint32_t missed_fc : 16;    /*This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read.*/
+            uint32_t overflow_bmfc : 1; /*This bit is set every time Missed Frame Counter (Bits[15:0]) overflows that is  the DMA discards an incoming frame because of the Host Receive  Buffer being unavailable with the missed frame counter at maximum value. In such a scenario  the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
+            uint32_t overflow_fc : 11;  /*This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read.*/
+            uint32_t overflow_bfoc : 1; /*This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows  that is  the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario  the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
+            uint32_t reserved29 : 3;
+        };
+        uint32_t val;
+    } dmamissedfr;
+    volatile union {
+        struct {
+            uint32_t riwtc : 8; /*This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out  the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame.*/
+            uint32_t reserved8 : 24;
+        };
+        uint32_t val;
+    } dmarintwdtimer;
+    uint32_t reserved_28;
+    uint32_t reserved_2c;
+    uint32_t reserved_30;
+    uint32_t reserved_34;
+    uint32_t reserved_38;
+    uint32_t reserved_3c;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t dmatxcurrdesc;     /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
+    uint32_t dmarxcurrdesc;     /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
+    uint32_t dmatxcurraddr_buf; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
+    uint32_t dmarxcurraddr_buf; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
+} emac_dma_dev_t;
+
+extern emac_dma_dev_t EMAC_DMA;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/emac_mac_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/emac_mac_struct.h
new file mode 100644
index 0000000000..a316295a2e
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/emac_mac_struct.h
@@ -0,0 +1,258 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+typedef struct {
+    volatile union {
+        struct {
+            uint32_t mac_address_hi : 16; /*This field contains the upper 16 bits  Bits[47:32] of the eighth 6-byte MAC Address.*/
+            uint32_t reserved16 : 8;
+            uint32_t mask_byte_control : 6; /*These bits are mask control bits for comparison of each of the EMAC_ADDR bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of EMAC_ADDR registers. Each bit controls the masking of the bytes as follows:  Bit[29]: EMAC_ADDR High [15:8].  Bit[28]: EMAC_ADDR High [7:0].  Bit[27]: EMAC_ADDR Low [31:24].  Bit[24]: EMAC_ADDR Low [7:0]. You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
+            uint32_t source_address : 1;    /*When this bit is set  the EMAC_ADDR[47:0] is used to compare with the SA fields of the received frame. When this bit is reset  the EMAC_ADDR[47:0] is used to compare with the DA fields of the received frame.*/
+            uint32_t address_enable : 1;    /*When this bit is set  the address filter module uses the eighth MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering.*/
+        };
+        uint32_t val;
+    } emacaddrhigh;
+    uint32_t emacaddrlow; /*This field contains the lower 32 bits of the eighth 6-byte MAC address.The content of this field is undefined  so the register needs to be configured after the initialization Process.*/
+} emac_mac_addr_t;
+
+typedef struct emac_mac_dev_s {
+    volatile union {
+        struct {
+            uint32_t pltf : 2;          /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/
+            uint32_t rx : 1;            /*When this bit is set  the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset  the MAC receive state machine is disabled after the completion of the reception of the current frame  and does not receive any further frames from the MII.*/
+            uint32_t tx : 1;            /*When this bit is set  the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset  the MAC transmit state machine is disabled after the completion of the transmission of the current frame  and does not transmit any further frames.*/
+            uint32_t deferralcheck : 1; /*Deferral Check.*/
+            uint32_t backofflimit : 2;  /*The Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode.  00: k= min (n  10).  01: k = min (n  8).  10: k = min (n  4).  11: k = min (n  1)  n = retransmission attempt. The random integer r takes the value in the Range 0 ~ 2000.*/
+            uint32_t padcrcstrip : 1;   /*When this bit is set  the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1 536 bytes. All received frames with length field greater than or equal to 1 536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset  the MAC passes all incoming frames  without modifying them to the Host.*/
+            uint32_t reserved8 : 1;
+            uint32_t retry : 1;         /*When this bit is set  the MAC attempts only one transmission. When a collision occurs on the MII interface  the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset  the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex Mode.*/
+            uint32_t rxipcoffload : 1;  /*When this bit is set  the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset  this function is disabled.*/
+            uint32_t duplex : 1;        /*When this bit is set  the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is read only with default value of 1'b1 in the full-duplex-mode.*/
+            uint32_t loopback : 1;      /*When this bit is set  the MAC operates in the loopback mode MII. The MII Receive clock input (CLK_RX) is required for the loopback to work properly  because the transmit clock is not looped-back internally.*/
+            uint32_t rxown : 1;         /*When this bit is set  the MAC disables the reception of frames when the TX_EN is asserted in the half-duplex mode. When this bit is reset  the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full duplex mode.*/
+            uint32_t fespeed : 1;       /*This bit selects the speed in the MII  RMII interface. 0: 10 Mbps. 1: 100 Mbps.*/
+            uint32_t mii : 1;           /*This bit selects the Ethernet line speed. It should be set to 1 for 10 or 100 Mbps operations.In 10 or 100 Mbps operations  this bit  along with FES(EMACFESPEED) bit  it selects the exact linespeed. In the 10/100 Mbps-only operations  the bit is always 1.*/
+            uint32_t disablecrs : 1;    /*When set high  this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low  the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions.*/
+            uint32_t interframegap : 3; /*These bits control the minimum IFG between frames during transmission.  3'b000: 96 bit times.  3'b001: 88 bit times.  3'b010: 80 bit times.  3'b111: 40 bit times. In the half-duplex mode  the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered.*/
+            uint32_t jumboframe : 1;    /*When this bit is set  the MAC allows Jumbo frames of 9 018 bytes (9 022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.*/
+            uint32_t reserved21 : 1;
+            uint32_t jabber : 1;   /*When this bit is set  the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset  the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data (10 240 if JE is set high) during Transmission.*/
+            uint32_t watchdog : 1; /*When this bit is set  the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16 383 bytes. When this bit is reset  the MAC does not allow a receive frame which more than 2 048 bytes (10 240 if JE is set high) or the value programmed in Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog limit number of bytes.*/
+            uint32_t reserved24 : 1;
+            uint32_t reserved25 : 1;
+            uint32_t reserved26 : 1;
+            uint32_t ass2kp : 1; /*When set  the MAC considers all frames  with up to 2 000 bytes length  as normal packets.When Bit[20] (JE) is not set  the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit[20] (JE) is not set  the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit[20] is set  setting this bit has no effect on Giant Frame status.*/
+            uint32_t sairc : 3;  /*This field controls the source address insertion or replacement for all transmitted frames.Bit[30] specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]:  2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation.  2'b10: If Bit[30] is set to 0  the MAC inserts the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC inserts the content of the MAC Address 1 registers in the SA field of all transmitted frames.  2'b11: If Bit[30] is set to 0  the MAC replaces the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1  the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames.*/
+            uint32_t reserved31 : 1;
+        };
+        uint32_t val;
+    } gmacconfig;
+    volatile union {
+        struct {
+            uint32_t pmode : 1; /*When this bit is set  the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set.*/
+            uint32_t reserved1 : 1;
+            uint32_t reserved2 : 1;
+            uint32_t daif : 1; /*When this bit is set  the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset  normal filtering of frames is performed.*/
+            uint32_t pam : 1;  /*When set  this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.*/
+            uint32_t dbf : 1;  /*When this bit is set  the AFM(Address Filtering Module) module blocks all incoming broadcast frames. In addition  it overrides all other filter settings. When this bit is reset  the AFM module passes all received broadcast Frames.*/
+            uint32_t pcf : 2;  /*These bits control the forwarding of all control frames (including unicast and multicast Pause frames).   2'b00: MAC filters all control frames from reaching the application.  2'b01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter.  2'b10: MAC forwards all control frames to application even if they fail the Address Filter.  2'b11: MAC forwards control frames that pass the Address Filter.The following conditions should be true for the Pause frames processing:  Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register (Flow Control Register) to 1.  Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set.  Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.*/
+            uint32_t saif : 1; /*When this bit is set  the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset  frames whose SA does not match the SA registers are marked as failing the SA Address filter.*/
+            uint32_t safe : 1; /*When this bit is set  the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails  the MAC drops the frame. When this bit is reset  the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison.*/
+            uint32_t reserved10 : 1;
+            uint32_t reserved11 : 5;
+            uint32_t reserved16 : 1;
+            uint32_t reserved17 : 3;
+            uint32_t reserved20 : 1;
+            uint32_t reserved21 : 1;
+            uint32_t reserved22 : 9;
+            uint32_t receive_all : 1; /*When this bit is set  the MAC Receiver module passes all received frames  irrespective of whether they pass the address filter or not  to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter.*/
+        };
+        uint32_t val;
+    } gmacff;
+    uint32_t reserved_1008;
+    uint32_t reserved_100c;
+    volatile union {
+        struct {
+            uint32_t miibusy : 1;   /*This bit should read logic 0 before writing to PHY Addr Register and PHY data Register.During a PHY register access  the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation  the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed  there is no change in the functionality of this bit even when the PHY is not Present.*/
+            uint32_t miiwrite : 1;  /*When set  this bit indicates to the PHY that this is a Write operation using the MII Data register. If this bit is not set  it indicates that this is a Read operation  that is  placing the data in the MII Data register.*/
+            uint32_t miicsrclk : 4; /*CSR clock range: 1.0 MHz ~ 2.5 MHz.  4'b0000: When the APB clock frequency is 80 MHz  the MDC clock frequency is APB CLK/42  4'b0011: When the APB clock frequency is 40 MHz  the MDC clock frequency is APB CLK/26.*/
+            uint32_t miireg : 5;    /*These bits select the desired MII register in the selected PHY device.*/
+            uint32_t miidev : 5;    /*This field indicates which of the 32 possible PHY devices are being accessed.*/
+            uint32_t reserved16 : 16;
+        };
+        uint32_t val;
+    } emacgmiiaddr;
+    volatile union {
+        struct {
+            uint32_t mii_data : 16; /*This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation.*/
+            uint32_t reserved16 : 16;
+        };
+        uint32_t val;
+    } emacmiidata;
+    volatile union {
+        struct {
+            uint32_t fcbba : 1; /*This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode  this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame  the Application must set this bit to 1'b1. During a transfer of the Control Frame  this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission  the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode  when this bit is set (and TFCE is set)  then backpressure is asserted by the MAC. During backpressure  when the MAC receives a new frame  the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode  the BPA(backpressure activate) is automatically disabled.*/
+            uint32_t tfce : 1;  /*In the full-duplex mode  when this bit is set  the MAC enables the flow control operation to transmit Pause frames. When this bit is reset  the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode  when this bit is set the MAC enables the backpressure operation. When this bit is reset  the backpressure feature is Disabled.*/
+            uint32_t rfce : 1;  /*When this bit is set  the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset  the decode function of the Pause frame is disabled.*/
+            uint32_t upfd : 1;  /*A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set  the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the EMACADDR0 High Register and EMACADDR0 Low Register. When this bit is reset  the MAC only detects Pause frames with unique multicast address.*/
+            uint32_t plt : 2;   /*This field configures the threshold of the Pause timer automatic retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example  if PT = 100H (256 slot-times)  and PLT = 01  then a second Pause frame is automatically transmitted at 228 (256-28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values:   2'b00: The threshold is Pause time minus 4 slot times (PT-4 slot times).  2'b01: The threshold is Pause time minus 28 slot times (PT-28 slot times).  2'b10: The threshold is Pause time minus 144 slot times (PT-144 slot times).  2'b11: The threshold is Pause time minus 256 slot times (PT-256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface.*/
+            uint32_t reserved6 : 1;
+            uint32_t dzpq : 1; /*When this bit is set  it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer. When this bit is reset  normal operation with automatic Zero-Quanta Pause frame generation is enabled.*/
+            uint32_t reserved8 : 8;
+            uint32_t pause_time : 16; /*This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.*/
+        };
+        uint32_t val;
+    } gmacfc;
+    uint32_t reserved_101c;
+    uint32_t reserved_1020;
+    volatile union {
+        struct {
+            uint32_t macrpes : 1;  /*When high  this bit indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state.*/
+            uint32_t macrffcs : 2; /*When high  this field indicates the active state of the FIFO Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller.*/
+            uint32_t reserved3 : 1;
+            uint32_t mtlrfwcas : 1; /*When high  this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO.*/
+            uint32_t mtlrfrcs : 2;  /*This field gives the state of the Rx FIFO read Controller: 2'b00: IDLE state.2'b01: Reading frame data.2'b10: Reading frame status (or timestamp).2'b11: Flushing the frame data and status.*/
+            uint32_t reserved7 : 1;
+            uint32_t mtlrffls : 2; /*This field gives the status of the fill-level of the Rx FIFO:   2'b00: Rx FIFO Empty.  2'b01: Rx FIFO fill-level below flow-control deactivate threshold.  2'b10: Rx FIFO fill-level above flow-control activate threshold.  2'b11: Rx FIFO Full.*/
+            uint32_t reserved10 : 6;
+            uint32_t mactpes : 1;  /*When high  this bit indicates that the MAC MII transmit protocol engine is actively transmitting data and is not in the IDLE state.*/
+            uint32_t mactfcs : 2;  /*This field indicates the state of the MAC Transmit Frame Controller module:   2'b00: IDLE state.  2'b01: Waiting for status of previous frame or IFG or backoff period to be over.  2'b10: Generating and transmitting a Pause frame (in the full-duplex mode).  2'b11: Transferring input frame for transmission.*/
+            uint32_t mactp : 1;    /*When high  this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-mode) and hence does not schedule any frame for transmission.*/
+            uint32_t mtltfrcs : 2; /*This field indicates the state of the Tx FIFO Read Controller:   2'b00: IDLE state.  2'b01: READ state (transferring data to the MAC transmitter).  2'b10: Waiting for TxStatus from the MAC transmitter.  2'b11: Writing the received TxStatus or flushing the Tx FIFO.*/
+            uint32_t mtltfwcs : 1; /*When high  this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO.*/
+            uint32_t reserved23 : 1;
+            uint32_t mtltfnes : 1; /*When high  this bit indicates that the MTL Tx FIFO is not empty and some data is left for Transmission.*/
+            uint32_t mtltsffs : 1; /*When high  this bit indicates that the MTL TxStatus FIFO is full. Therefore  the MTL cannot accept any more frames for transmission.*/
+            uint32_t reserved26 : 6;
+        };
+        uint32_t val;
+    } emacdebug;
+    uint32_t pmt_rwuffr; /*The MSB (31st bit) must be zero.Bit j[30:0] is the byte mask. If Bit 1/2/3/4 (byte number) of the byte mask is set  the CRC block processes the Filter 1/2/3/4 Offset + j of the incoming packet(PWKPTR is 0/1/2/3).RWKPTR is 0:Filter 0 Byte Mask .RWKPTR is 1:Filter 1 Byte Mask RWKPTR is 2:Filter 2 Byte Mask RWKPTR is 3:Filter 3 Byte Mask RWKPTR is 4:Bit 3/11/19/27 specifies the address type  defining the destination address type of the pattern.When the bit is set  the pattern applies to only multicast packets*/
+    volatile union {
+        struct {
+            uint32_t pwrdwn : 1;   /*When set  the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame.This bit must only be set when MGKPKTEN  GLBLUCAST  or RWKPKTEN bit is set high.*/
+            uint32_t mgkpkten : 1; /*When set  enables generation of a power management event because of magic packet reception.*/
+            uint32_t rwkpkten : 1; /*When set  enables generation of a power management event because of remote wake-up frame reception*/
+            uint32_t reserved3 : 2;
+            uint32_t mgkprcvd : 1; /*When set  this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register.*/
+            uint32_t rwkprcvd : 1; /*When set  this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register.*/
+            uint32_t reserved7 : 2;
+            uint32_t glblucast : 1; /*When set  enables any unicast packet filtered by the MAC (DAFilter) address recognition to be a remote wake-up frame.*/
+            uint32_t reserved10 : 14;
+            uint32_t rwkptr : 5; /*The maximum value of the pointer is 7  the detail information please refer to PMT_RWUFFR.*/
+            uint32_t reserved29 : 2;
+            uint32_t rwkfiltrst : 1; /*When this bit is set  it resets the RWKPTR register to 3’b000.*/
+        };
+        uint32_t val;
+    } pmt_csr;
+    volatile union {
+        struct {
+            uint32_t tlpien : 1; /*When set  this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register.*/
+            uint32_t tlpiex : 1; /*When set  this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI_TW_Timer has expired.This bit is cleared by a read into this register.*/
+            uint32_t rlpien : 1; /*When set  this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register.*/
+            uint32_t rlpiex : 1; /*When set  this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface  exited the LPI state  and resumed the normal reception. This bit is cleared by a read into this register.*/
+            uint32_t reserved4 : 4;
+            uint32_t tlpist : 1; /*When set  this bit indicates that the MAC is transmitting the LPI pattern on the MII interface.*/
+            uint32_t rlpist : 1; /*When set  this bit indicates that the MAC is receiving the LPI pattern on the MII interface.*/
+            uint32_t reserved10 : 6;
+            uint32_t lpien : 1; /*When set  this bit instructs the MAC Transmitter to enter the LPI state. When reset  this bit instructs the MAC to exit the LPI state and resume normal transmission.This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.*/
+            uint32_t pls : 1;   /*This bit indicates the link status of the PHY.When set  the link is considered to be okay (up) and when reset  the link is considered to be down.*/
+            uint32_t reserved18 : 1;
+            uint32_t lpitxa : 1; /*This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side.If the LPITXA and LPIEN bits are set to 1  the MAC enters the LPI mode only after all outstanding frames and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame.When this bit is 0  the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.*/
+            uint32_t reserved20 : 12;
+        };
+        uint32_t val;
+    } gmaclpi_crs;
+    volatile union {
+        struct {
+            uint32_t lpi_tw_timer : 16; /*This field specifies the minimum time (in microseconds) for which the MAC waits  after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer.*/
+            uint32_t lpi_ls_timer : 10; /*This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI_LS_Timer reaches the programmed terminal count. The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard.*/
+            uint32_t reserved26 : 6;
+        };
+        uint32_t val;
+    } gmaclpitimerscontrol;
+    volatile union {
+        struct {
+            uint32_t reserved0 : 1;
+            uint32_t reserved1 : 1;
+            uint32_t reserved2 : 1;
+            uint32_t pmtints : 1; /*This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bit[5] and Bit[6] in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. This bit is valid only when you select the optional PMT module during core configuration.*/
+            uint32_t reserved4 : 1;
+            uint32_t reserved5 : 1;
+            uint32_t reserved6 : 1;
+            uint32_t reserved7 : 1;
+            uint32_t reserved8 : 1;
+            uint32_t reserved9 : 1;
+            uint32_t lpiis : 1; /*When the Energy Efficient Ethernet feature is enabled  this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit[0] of Register (LPI Control and Status Register).*/
+            uint32_t reserved11 : 1;
+            uint32_t reserved12 : 20;
+        };
+        uint32_t val;
+    } emacints;
+    volatile union {
+        struct {
+            uint32_t reserved0 : 1;
+            uint32_t reserved1 : 1;
+            uint32_t reserved2 : 1;
+            uint32_t pmtintmask : 1; /*When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Interrupt Status Register.*/
+            uint32_t reserved4 : 5;
+            uint32_t tsintmask : 1; /*When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Interrupt Status Register. */
+            uint32_t lpiintmask : 1; /*When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Interrupt Status Register.*/
+            uint32_t reserved11 : 21;
+        };
+        uint32_t val;
+    } emacintmask;
+    volatile union {
+        struct {
+            uint32_t address0_hi : 16; /*This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
+            uint32_t reserved16 : 15;
+            uint32_t address_enable0 : 1; /*This bit is always set to 1.*/
+        };
+        uint32_t val;
+    } emacaddr0high;
+    uint32_t emacaddr0low; /*This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
+    emac_mac_addr_t emacaddr[15];    /*Offset: 0x40-0xC0. MAC Address1-15 registers. Each MAC address register contains the high and low 32-bit fields for MAC addresses 1-15.*/
+    uint32_t reserved_10c4; // AN control register
+    uint32_t reserved_10c8;
+    uint32_t reserved_10cc;
+    uint32_t reserved_10d0;
+    uint32_t reserved_10d4;
+    volatile union {
+        struct {
+            uint32_t link_mode : 1;  /*This bit indicates the current mode of operation of the link:   1'b0: Half-duplex mode.  1'b1: Full-duplex mode.*/
+            uint32_t link_speed : 2; /*This bit indicates the current speed of the link:   2'b00: 2.5 MHz.  2'b01: 25 MHz.  2'b10: 125 MHz.*/
+            uint32_t reserved3 : 1;
+            uint32_t jabber_timeout : 1; /*This bit indicates whether there is jabber timeout error (1'b1) in the received Frame.*/
+            uint32_t reserved5 : 1;
+            uint32_t reserved6 : 10;
+            uint32_t reserved16 : 1;
+            uint32_t reserved17 : 15;
+        };
+        uint32_t val;
+    } emaccstatus;
+    volatile union {
+        struct {
+            uint32_t wdogto : 14; /*When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG is reset  this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field  such frame is terminated and declared as an error frame.*/
+            uint32_t reserved14 : 2;
+            uint32_t pwdogen : 1; /*When this bit is set and Bit[23] (WD) of EMACCONFIG_REG is reset  the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared  the watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in EMACCONFIG_REG.*/
+            uint32_t reserved17 : 15;
+        };
+        uint32_t val;
+    } emacwdogto;
+} emac_mac_dev_t;
+
+extern emac_mac_dev_t EMAC_MAC;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/emac_ptp_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/emac_ptp_struct.h
new file mode 100644
index 0000000000..ca04887a21
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/emac_ptp_struct.h
@@ -0,0 +1,268 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct emac_ptp_dev_s {
+    volatile union {
+        struct {
+            uint32_t en_timestamp : 1;                /* Timestamp Enable */
+            uint32_t ts_fine_coarse_update : 1;       /* Timestamp Fine or Coarse Update */
+            uint32_t ts_initialize : 1;               /* Timestamp Initialize */
+            uint32_t ts_update : 1;                   /* Timestamp Update */
+            uint32_t en_ts_int_trig : 1;              /* Timestamp Interrupt Trigger Enable */
+            uint32_t addend_reg_update : 1;           /* Addend Reg Update */
+            uint32_t reserved1 : 2;                   /* Reserved */
+            uint32_t en_ts4all : 1;                   /* Enable Timestamp for All Frames */
+            uint32_t ts_digit_bin_roll_ctrl : 1;      /* Timestamp Digital or Binary Rollover Control */
+            uint32_t en_ptp_pkg_proc_ver2_fmt : 1;    /* Enable PTP packet Processing for Version 2 Format */
+            uint32_t en_proc_ptp_ether_frm : 1;       /* Enable Processing of PTP over Ethernet Frames */
+            uint32_t en_proc_ptp_ipv6_udp : 1;        /* Enable Processing of PTP Frames Sent over IPv6-UDP */
+            uint32_t en_proc_ptp_ipv4_udp : 1;        /* Enable Processing of PTP Frames Sent over IPv4-UDP */
+            uint32_t en_ts_snap_event_msg : 1;        /* Enable Timestamp Snapshot for Event Messages */
+            uint32_t en_snap_msg_relevant_master : 1; /* Enable Snapshot for Messages Relevant to Master */
+            uint32_t sel_snap_type : 2;               /* Select PTP packets for Taking Snapshots */
+            uint32_t en_mac_addr_filter : 1;          /* Enable MAC address for PTP Frame Filtering */
+            uint32_t reserved2 : 5;                   /* Reserved */
+            uint32_t aux_snap_fifo_clear : 1;         /* Auxiliary Snapshot FIFO Clear */
+            uint32_t en_aux_snap0 : 1;                /* Auxiliary Snapshot 0 Enable */
+            uint32_t en_aux_snap1 : 1;                /* Auxiliary Snapshot 1 Enable */
+            uint32_t en_aux_snap2 : 1;                /* Auxiliary Snapshot 2 Enable */
+            uint32_t en_aux_snap3 : 1;                /* Auxiliary Snapshot 3 Enable */
+            uint32_t reserved3 : 3;                   /* Reserved */
+        };
+        uint32_t val;
+    } timestamp_ctrl;
+    volatile union {
+        struct {
+            uint32_t sub_second_incre_value : 8; /* Sub-second Increment Value */
+            uint32_t reserved : 24;              /* Reserved */
+        };
+        uint32_t val;
+    } sub_sec_incre;
+    volatile union {
+        struct {
+            uint32_t ts_second : 32; /* Timestamp Second */
+        };
+        uint32_t val;
+    } sys_seconds;
+    volatile union {
+        struct {
+            uint32_t ts_sub_seconds : 31; /* Timestamp Sub Seconds */
+            uint32_t reserved: 1;         /* Reserved */
+        };
+        uint32_t val;
+    } sys_nanosec;
+    volatile union {
+        struct {
+            uint32_t ts_second : 32; /* Timestamp Second */
+        };
+        uint32_t val;
+    } sys_seconds_update;
+    volatile union {
+        struct {
+            uint32_t ts_sub_seconds : 31; /* Timestamp Sub Seconds */
+            uint32_t add_sub : 1;         /* Add or Subtract Time */
+        };
+        uint32_t val;
+    } sys_nanosec_update;
+    volatile union {
+        struct {
+            uint32_t ts_addend_val: 32; /* Timestamp Addend Register */
+        };
+        uint32_t val;
+    } timestamp_addend;
+    volatile union {
+        struct {
+            uint32_t tgt_time_second_val : 32; /* Target Time Seconds Register */
+        };
+        uint32_t val;
+    } tgt_seconds;
+    volatile union {
+        struct {
+            uint32_t tgt_ts_low_reg : 31;   /* Target Timestamp Low Register */
+            uint32_t tgt_time_reg_busy : 1; /* Target Time Register Busy */
+        };
+        uint32_t val;
+    } tgt_nanosec;
+    volatile union {
+        struct {
+            uint32_t ts_higher_word : 16; /* Timestamp Higher Word Register */
+            uint32_t reserved : 16;       /* Reserved */
+        };
+        uint32_t val;
+    } sys_seconds_high;
+    volatile union {
+        struct {
+            uint32_t ts_secons_ovf : 1;             /* Timestamp Seconds Overflow */
+            uint32_t ts_tgt_time_reach : 1;         /* Timestamp Target Time Reached */
+            uint32_t aux_ts_trig_snap : 1;          /* Auxiliary Timestamp Trigger Snapshot */
+            uint32_t ts_tgt_time_err : 1;           /* Timestamp Target Time Error */
+            uint32_t ts_tgt_time_reach_pps1 : 1;    /* Timestamp Target Time Reached for Target Time PPS1 */
+            uint32_t ts_tgt_time_err1 : 1;          /* Timestamp Target Time Error */
+            uint32_t ts_tgt_time_reach_pps2 : 1;    /* Timestamp Target Time Reached for Target Time PPS2 */
+            uint32_t ts_tgt_time_err2 : 1;          /* Timestamp Target Time Error */
+            uint32_t ts_tgt_time_reach_pps3 : 1;    /* Timestamp Target Time Reached for Target Time PPS3 */
+            uint32_t ts_tgt_time_err3 : 1;          /* Timestamp Target Time Error */
+            uint32_t reserved1 : 6;                 /* Reserved */
+            uint32_t aux_ts_snap_trig_identify : 4; /* Auxiliary Timestamp Snapshot Trigger Identifier */
+            uint32_t reserved2 : 4;                 /* Reserved */
+            uint32_t aux_tx_snap_trig_miss : 1;     /* Auxiliary Timestamp Snapshot Trigger Missed */
+            uint32_t aux_ts_snap_num : 5;           /* Number of Auxiliary Timestamp Snapshots */
+            uint32_t reserved : 2;                  /* Reserved */
+        };
+        uint32_t val;
+    } status;
+    volatile union {
+        struct {
+            uint32_t pps_cmd0 : 4;      /* Flexible PPS0 Output Control */
+            uint32_t en_pps0 : 1;       /* Flexible PPS Output Mode Enable */
+            uint32_t tgt_mode_sel0 : 2; /* Target Time Register Mode for PPS0 Output */
+            uint32_t reserved1 : 1;     /* Reserved */
+            uint32_t pps_cmd1 : 3;      /* Flexible PPS1 Output Control */
+            uint32_t reserved2 : 2;     /* Reserved */
+            uint32_t tgt_mode_sel1 : 2; /* Target Time Register Mode for PPS1 Output */
+            uint32_t reserved3 : 1;     /* Reserved */
+            uint32_t pps_cmd2 : 3;      /* Flexible PPS2 Output Control */
+            uint32_t reserved4 : 2;     /* Reserved */
+            uint32_t tgt_mode_sel2 : 2; /* Target Time Register Mode for PPS2 Output */
+            uint32_t reserved5 : 1;     /* Reserved */
+            uint32_t pps_cmd3 : 3;      /* Flexible PPS3 Output Control */
+            uint32_t reserved6 : 2;     /* Reserved */
+            uint32_t tgt_mode_sel3 : 2; /* Target Time Register Mode for PPS3 Output */
+            uint32_t reserved7 : 1;     /* Reserved */
+        };
+        uint32_t val;
+    } pps_ctrl;
+    volatile union {
+        struct {
+            uint32_t aux_ts_low : 31; /* Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. */
+            uint32_t reserved : 1;    /* Reserved */
+        };
+        uint32_t val;
+    } aux_nanosec;
+    volatile union {
+        struct {
+            uint32_t aux_tx_high : 32; /* Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. */
+        };
+        uint32_t val;
+    } aux_seconds;
+    volatile union {
+        struct {
+            uint32_t av_ethertype_val : 16;       /* AV EtherType Value */
+            uint32_t ac_queue_pri : 3;            /* AV Priority for Queuing */
+            uint32_t en_queue_non_av_pkt : 1;     /* VLAN Tagged Non-AV Packets Queueing Enable */
+            uint32_t dis_av_chann : 1;            /* AV Channel Disable */
+            uint32_t queue_av_ctrl_pkt_chann : 2; /* Channel for Queuing the AV Control Packets */
+            uint32_t reserved1 : 1;               /* Reserved */
+            uint32_t queue_ptp_pkt_chann : 2;     /* Channel for Queuing the PTP Packets */
+            uint32_t reserved2 : 6;               /* Reserved */
+        };
+        uint32_t val;
+    } av_mac_ctrl;
+    uint32_t reserved1[9]; /* Reserved */
+    volatile union {
+        struct {
+            uint32_t pps0_interval : 32; /* PPS0 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps0_interval;
+    volatile union {
+        struct {
+            uint32_t pps0_width : 32; /* PPS0 Output Signal Width */
+        };
+        uint32_t val;
+    } pps0_width;
+    uint32_t reserved2[6]; /* Reserved */
+    volatile union {
+        struct {
+            uint32_t pps1_tgt_seconds : 32; /* PPS1 Target Time Seconds Register */
+        };
+        uint32_t val;
+    } pps1_tgt_seconds;
+    volatile union {
+        struct {
+            uint32_t pps1_tgt_nanosec : 31;  /* Target Time Low for PPS1 Register */
+            uint32_t pps1_tgt_time_busy : 1; /* PPS1 Target Time Register Busy */
+        };
+        uint32_t val;
+    } pps1_tgt_nanosec;
+    volatile union {
+        struct {
+            uint32_t pps1_interval : 32; /* PPS1 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps1_interval;
+    volatile union {
+        struct {
+            uint32_t pps1_width : 32; /* PPS1 Output Signal Width */
+        };
+        uint32_t val;
+    } pps1_width;
+    uint32_t reserved3[4]; /* Reserved */
+    volatile union {
+        struct {
+            uint32_t pps2_tgt_seconds : 32; /* PPS2 Target Time Seconds Register */
+        };
+        uint32_t val;
+    } pps2_tgt_seconds;
+    volatile union {
+        struct {
+            uint32_t pps2_tgt_nanosec : 31;  /* Target Time Low for PPS2 Register */
+            uint32_t pps2_tgt_time_busy : 1; /* PPS2 Target Time Register Busy */
+        };
+        uint32_t val;
+    } pps2_tgt_nanosec;
+    volatile union {
+        struct {
+            uint32_t pps2_interval : 32; /* PPS2 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps2_interval;
+    volatile union {
+        struct {
+            uint32_t pps2_width : 32; /* PPS2 Output Signal Width */
+        };
+        uint32_t val;
+    } pps2_width;
+    uint32_t reserved4[4]; /* Reserved */
+    volatile union {
+        struct {
+            uint32_t pps3_tgt_seconds : 32; /* PPS3 Target Time Seconds Register */
+        };
+        uint32_t val;
+    } pps3_tgt_seconds;
+    volatile union {
+        struct {
+            uint32_t pps3_tgt_nanosec : 31;  /* Target Time Low for PPS3 Register */
+            uint32_t pps3_tgt_time_busy : 1; /* PPS3 Target Time Register Busy */
+        };
+        uint32_t val;
+    } pps3_tgt_nanosec;
+    volatile union {
+        struct {
+            uint32_t pps3_interval : 32; /* PPS3 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps3_interval;
+    volatile union {
+        struct {
+            uint32_t pps3_width : 32; /* PPS3 Output Signal Width */
+        };
+        uint32_t val;
+    } pps3_width;
+} emac_ptp_dev_t;
+
+extern emac_ptp_dev_t EMAC_PTP;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/emac_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/emac_reg.h
new file mode 100644
index 0000000000..9bde27bca0
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/emac_reg.h
@@ -0,0 +1,7239 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EMAC_MACCONFIGURATION_REG register
+ *  This is the operation mode register for the MAC
+ */
+#define EMAC_MACCONFIGURATION_REG (DR_REG_EMAC_BASE + 0x0)
+/** EMAC_PRELEN : R/W; bitpos: [1:0]; default: 0;
+ *  Preamble Length for Transmit frames These bits control the number of preamble bytes
+ *  that are added to the beginning of every Transmit frame The preamble reduction
+ *  occurs only when the MAC is operating in the fullduplex mode 2'b00: 7 bytes of
+ *  preamble 2'b01: 5 bytes of preamble 2'b10: 3 bytes of preamble 2'b11: Reserved
+ */
+#define EMAC_PRELEN    0x00000003U
+#define EMAC_PRELEN_M  (EMAC_PRELEN_V << EMAC_PRELEN_S)
+#define EMAC_PRELEN_V  0x00000003U
+#define EMAC_PRELEN_S  0
+/** EMAC_RE : R/W; bitpos: [2]; default: 0;
+ *  Receiver Enable When this bit is set, the receiver state machine of the MAC is
+ *  enabled for receiving frames from the GMII or MII When this bit is reset, the MAC
+ *  receive state machine is disabled after the completion of the reception of the
+ *  current frame, and does not receive any further frames from the GMII or MII
+ */
+#define EMAC_RE    (BIT(2))
+#define EMAC_RE_M  (EMAC_RE_V << EMAC_RE_S)
+#define EMAC_RE_V  0x00000001U
+#define EMAC_RE_S  2
+/** EMAC_TE : R/W; bitpos: [3]; default: 0;
+ *  Transmitter Enable When this bit is set, the transmit state machine of the MAC is
+ *  enabled for transmission on the GMII or MII When this bit is reset, the MAC
+ *  transmit state machine is disabled after the completion of the transmission of the
+ *  current frame, and does not transmit any further frames
+ */
+#define EMAC_TE    (BIT(3))
+#define EMAC_TE_M  (EMAC_TE_V << EMAC_TE_S)
+#define EMAC_TE_V  0x00000001U
+#define EMAC_TE_S  3
+/** EMAC_DC : R/W; bitpos: [4]; default: 0;
+ *  Deferral Check When this bit is set, the deferral check function is enabled in the
+ *  MAC The MAC issues a Frame Abort status, along with the excessive deferral error
+ *  bit set in the transmit frame status, when the transmit state machine is deferred
+ *  for more than 24,288 bit times in the 10 or 100 Mbps mode If the MAC is configured
+ *  for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps
+ *  mode, the threshold for deferral is 155,680 bits times Deferral begins when the
+ *  transmitter is ready to transmit, but it is prevented because of an active carrier
+ *  sense signal _CRS_ on GMII or MII The defer time is not cumulative For example, if
+ *  the transmitter defers for 10,000 bit times because the CRS signal is active and
+ *  then the CRS signal becomes inactive, the transmitter transmits and collision
+ *  happens Because of collision, the transmitter needs to back off and then defer
+ *  again after back off completion In such a scenario, the deferral timer is reset to
+ *  0 and it is restarted When this bit is reset, the deferral check function is
+ *  disabled and the MAC defers until the CRS signal goes inactive This bit is
+ *  applicable only in the halfduplex mode and is reserved _RO_ in the fullduplexonly
+ *  configuration
+ */
+#define EMAC_DC    (BIT(4))
+#define EMAC_DC_M  (EMAC_DC_V << EMAC_DC_S)
+#define EMAC_DC_V  0x00000001U
+#define EMAC_DC_S  4
+/** EMAC_BL : R/W; bitpos: [6:5]; default: 0;
+ *  BackOff Limit The BackOff limit determines the random integer number _r_ of slot
+ *  time delays _4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps_ for
+ *  which the MAC waits before rescheduling a transmission attempt during retries after
+ *  a collision This bit is applicable only in the halfduplex mode and is reserved _RO_
+ *  in the fullduplexonly configuration 00: k= min _n, 10_ 01: k = min _n, 8_ 10: k =
+ *  min _n, 4_ 11: k = min _n, 1_ where n = retransmission attempt The random integer r
+ *  takes the value in the range 0 ≤ r < 2k
+ */
+#define EMAC_BL    0x00000003U
+#define EMAC_BL_M  (EMAC_BL_V << EMAC_BL_S)
+#define EMAC_BL_V  0x00000003U
+#define EMAC_BL_S  5
+/** EMAC_ACS : R/W; bitpos: [7]; default: 0;
+ *  Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS
+ *  field on the incoming frames only if the value of the length field is less than
+ *  1,536 bytes All received frames with length field greater than or equal to 1,536
+ *  bytes are passed to the application without stripping the Pad or FCS field When
+ *  this bit is reset, the MAC passes all incoming frames, without modifying them, to
+ *  the Host Note: For information about how the settings of Bit 25 _CST_ and this bit
+ *  impact the frame length, see Table 632
+ */
+#define EMAC_ACS    (BIT(7))
+#define EMAC_ACS_M  (EMAC_ACS_V << EMAC_ACS_S)
+#define EMAC_ACS_V  0x00000001U
+#define EMAC_ACS_S  7
+/** EMAC_LUD : R/W; bitpos: [8]; default: 0;
+ *  Link Up or Down This bit indicates whether the link is up or down during the
+ *  transmission of configuration in the RGMII, SGMII, or SMII interface: 0: Link Down
+ *  1: Link Up This bit is reserved _RO with default value_ and is enabled when the
+ *  RGMII, SGMII, or SMII interface is enabled during core configuration
+ */
+#define EMAC_LUD    (BIT(8))
+#define EMAC_LUD_M  (EMAC_LUD_V << EMAC_LUD_S)
+#define EMAC_LUD_V  0x00000001U
+#define EMAC_LUD_S  8
+/** EMAC_DR : R/W; bitpos: [9]; default: 0;
+ *  Disable Retry When this bit is set, the MAC attempts only one transmission When a
+ *  collision occurs on the GMII or MII interface, the MAC ignores the current frame
+ *  transmission and reports a Frame Abort with excessive collision error in the
+ *  transmit frame status When this bit is reset, the MAC attempts retries based on the
+ *  settings of the BL field _Bits [6:5]_ This bit is applicable only in the halfduplex
+ *  mode and is reserved _RO with default value_ in the fullduplexonly configuration
+ */
+#define EMAC_DR    (BIT(9))
+#define EMAC_DR_M  (EMAC_DR_V << EMAC_DR_S)
+#define EMAC_DR_V  0x00000001U
+#define EMAC_DR_S  9
+/** EMAC_IPC : R/W; bitpos: [10]; default: 0;
+ *  Checksum Offload When this bit is set, the MAC calculates the 16bit one’s
+ *  complement of the one’s complement sum of all received Ethernet frame payloads It
+ *  also checks whether the IPv4 Header checksum _assumed to be bytes 2526 or 2930
+ *  _VLAN tagged_ of the received Ethernet frame_ is correct for the received frame and
+ *  gives the status in the receive status word The MAC also appends the 16bit checksum
+ *  calculated for the IP header datagram payload _bytes after the IPv4 header_ and
+ *  appends it to the Ethernet frame transferred to the application _when Type 2 COE is
+ *  deselected_ When this bit is reset, this function is disabled When Type 2 COE is
+ *  selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or
+ *  IPv6 TCP, UDP, or ICMP payload checksum checking When this bit is reset, the COE
+ *  function in the receiver is disabled and the corresponding PCE and IP HCE status
+ *  bits _see Table 310 on page 138_ are always cleared If the IP Checksum Offload
+ *  feature is not enabled during core configuration, this bit is reserved _RO with
+ *  default value_
+ */
+#define EMAC_IPC    (BIT(10))
+#define EMAC_IPC_M  (EMAC_IPC_V << EMAC_IPC_S)
+#define EMAC_IPC_V  0x00000001U
+#define EMAC_IPC_S  10
+/** EMAC_DM : R/W; bitpos: [11]; default: 0;
+ *  Duplex Mode When this bit is set, the MAC operates in the fullduplex mode where it
+ *  can transmit and receive simultaneously This bit is RO with default value of 1'b1
+ *  in the fullduplexonly configuration
+ */
+#define EMAC_DM    (BIT(11))
+#define EMAC_DM_M  (EMAC_DM_V << EMAC_DM_S)
+#define EMAC_DM_V  0x00000001U
+#define EMAC_DM_S  11
+/** EMAC_LM : R/W; bitpos: [12]; default: 0;
+ *  Loopback Mode When this bit is set, the MAC operates in the loopback mode at GMII
+ *  or MII The _G_MII Receive clock input _clk_rx_i_ is required for the loopback to
+ *  work properly, because the Transmit clock is not loopedback internally
+ */
+#define EMAC_LM    (BIT(12))
+#define EMAC_LM_M  (EMAC_LM_V << EMAC_LM_S)
+#define EMAC_LM_V  0x00000001U
+#define EMAC_LM_S  12
+/** EMAC_DO : R/W; bitpos: [13]; default: 0;
+ *  Disable Receive Own When this bit is set, the MAC disables the reception of frames
+ *  when the phy_txen_o is asserted in the halfduplex mode When this bit is reset, the
+ *  MAC receives all packets that are given by the PHY while transmitting This bit is
+ *  not applicable if the MAC is operating in the fullduplex mode This bit is reserved
+ *  _RO with default value_ if the MAC is configured for the fullduplexonly operation
+ */
+#define EMAC_DO    (BIT(13))
+#define EMAC_DO_M  (EMAC_DO_V << EMAC_DO_S)
+#define EMAC_DO_V  0x00000001U
+#define EMAC_DO_S  13
+/** EMAC_FES : R/W; bitpos: [14]; default: 0;
+ *  Speed This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII
+ *  interface: 0: 10 Mbps 1: 100 Mbps This bit is reserved _RO_ by default and is
+ *  enabled only when the parameter SPEED_SELECT = Enabled This bit generates link
+ *  speed encoding when Bit 24 _TC_ is set in the RGMII, SMII, or SGMII mode This bit
+ *  is always enabled for RGMII, SGMII, SMII, or RevMII interface In configurations
+ *  with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output
+ *  signal _mac_speed_o[0]_ to reflect the value of this bit in the mac_speed_o signal
+ *  In configurations with RMII, MII, or GMII interface, you can optionally drive this
+ *  bit as an output signal _mac_speed_o[0]_ to reflect its value in the mac_speed_o
+ *  signal
+ */
+#define EMAC_FES    (BIT(14))
+#define EMAC_FES_M  (EMAC_FES_V << EMAC_FES_S)
+#define EMAC_FES_V  0x00000001U
+#define EMAC_FES_S  14
+/** EMAC_PS : R/W; bitpos: [15]; default: 0;
+ *  Port Select This bit selects the Ethernet line speed 0: For 1000 Mbps operations 1:
+ *  For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with
+ *  FES bit, selects the exact line speed In the 10/100 Mbpsonly _always 1_ or 1000
+ *  Mbpsonly _always 0_ configurations, this bit is readonly with the appropriate value
+ *  In default 10/100/1000 Mbps configuration, this bit is R_W The mac_portselect_o or
+ *  mac_speed_o[1] signal reflects the value of this bit
+ */
+#define EMAC_PS    (BIT(15))
+#define EMAC_PS_M  (EMAC_PS_V << EMAC_PS_S)
+#define EMAC_PS_V  0x00000001U
+#define EMAC_PS_S  15
+/** EMAC_DCRS : R/W; bitpos: [16]; default: 0;
+ *  Disable Carrier Sense During Transmission When set high, this bit makes the MAC
+ *  transmitter ignore the _G_MII CRS signal during frame transmission in the
+ *  halfduplex mode This request results in no errors generated because of Loss of
+ *  Carrier or No Carrier during such transmission When this bit is low, the MAC
+ *  transmitter generates such errors because of Carrier Sense and can even abort the
+ *  transmissions This bit is reserved _and RO_ in the fullduplexonly configurations
+ */
+#define EMAC_DCRS    (BIT(16))
+#define EMAC_DCRS_M  (EMAC_DCRS_V << EMAC_DCRS_S)
+#define EMAC_DCRS_V  0x00000001U
+#define EMAC_DCRS_S  16
+/** EMAC_IFG : R/W; bitpos: [19:17]; default: 0;
+ *  InterFrame Gap These bits control the minimum IFG between frames during
+ *  transmission 000: 96 bit times 001: 88 bit times 010: 80 bit times  111: 40 bit
+ *  times In the halfduplex mode, the minimum IFG can be configured only for 64 bit
+ *  times _IFG = 100_ Lower values are not considered In the 1000Mbps mode, the minimum
+ *  IFG supported is 64 bit times _and above_ in the EMACCORE configuration and 80 bit
+ *  times _and above_ in other configurations When a JAM pattern is being transmitted
+ *  because of backpressure activation, the MAC does not consider the minimum IFG
+ */
+#define EMAC_IFG    0x00000007U
+#define EMAC_IFG_M  (EMAC_IFG_V << EMAC_IFG_S)
+#define EMAC_IFG_V  0x00000007U
+#define EMAC_IFG_S  17
+/** EMAC_JE : R/W; bitpos: [20]; default: 0;
+ *  Jumbo Frame Enable When this bit is set, the MAC allows Jumbo frames of 9,018 bytes
+ *  _9,022 bytes for VLAN tagged frames_ without reporting a giant frame error in the
+ *  receive frame status
+ */
+#define EMAC_JE    (BIT(20))
+#define EMAC_JE_M  (EMAC_JE_V << EMAC_JE_S)
+#define EMAC_JE_V  0x00000001U
+#define EMAC_JE_S  20
+/** EMAC_BE : R/W; bitpos: [21]; default: 0;
+ *  Frame Burst Enable When this bit is set, the MAC allows frame bursting during
+ *  transmission in the GMII halfduplex mode This bit is reserved _and RO_ in the
+ *  10/100 Mbps only or fullduplexonly configurations
+ */
+#define EMAC_BE    (BIT(21))
+#define EMAC_BE_M  (EMAC_BE_V << EMAC_BE_S)
+#define EMAC_BE_V  0x00000001U
+#define EMAC_BE_S  21
+/** EMAC_JD : R/W; bitpos: [22]; default: 0;
+ *  Jabber Disable When this bit is set, the MAC disables the jabber timer on the
+ *  transmitter The MAC can transfer frames of up to 16,383 bytes When this bit is
+ *  reset, the MAC cuts off the transmitter if the application sends out more than
+ *  2,048 bytes of data _10,240 if JE is set high_ during transmission
+ */
+#define EMAC_JD    (BIT(22))
+#define EMAC_JD_M  (EMAC_JD_V << EMAC_JD_S)
+#define EMAC_JD_V  0x00000001U
+#define EMAC_JD_S  22
+/** EMAC_WD : R/W; bitpos: [23]; default: 0;
+ *  Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the
+ *  receiver The MAC can receive frames of up to 16,383 bytes When this bit is reset,
+ *  the MAC does not allow a receive frame which more than 2,048 bytes _10,240 if JE is
+ *  set high_ or the value programmed in Register 55 _Watchdog Timeout Register_ The
+ *  MAC cuts off any bytes received after the watchdog limit number of bytes
+ */
+#define EMAC_WD    (BIT(23))
+#define EMAC_WD_M  (EMAC_WD_V << EMAC_WD_S)
+#define EMAC_WD_V  0x00000001U
+#define EMAC_WD_S  23
+/** EMAC_TC : R/W; bitpos: [24]; default: 0;
+ *  Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the
+ *  transmission of duplex mode, link speed, and link up or down information to the PHY
+ *  in the RGMII, SMII, or SGMII port When this bit is reset, no such information is
+ *  driven to the PHY This bit is reserved _and RO_ if the RGMII, SMII, or SGMII PHY
+ *  port is not selected during core configuration The details of this feature are
+ *  explained in the following sections: “Reduced Gigabit Media Independent Interface”
+ *  on page 249 “Serial Media Independent Interface” on page 245 “Serial Gigabit Media
+ *  Independent Interface” on page 257
+ */
+#define EMAC_TC    (BIT(24))
+#define EMAC_TC_M  (EMAC_TC_V << EMAC_TC_S)
+#define EMAC_TC_V  0x00000001U
+#define EMAC_TC_S  24
+/** EMAC_CST : R/W; bitpos: [25]; default: 0;
+ *  CRC Stripping for Type Frames When this bit is set, the last 4 bytes _FCS_ of all
+ *  frames of Ether type _Length/Type field greater than or equal to 1,536_ are
+ *  stripped and dropped before forwarding the frame to the application This function
+ *  is not valid when the IP Checksum Engine _Type 1_ is enabled in the MAC receiver
+ *  This function is valid when Type 2 Checksum Offload Engine is enabled Note: For
+ *  information about how the settings of Bit 7 _ACS_ and this bit impact the frame
+ *  length, see Table 632
+ */
+#define EMAC_CST    (BIT(25))
+#define EMAC_CST_M  (EMAC_CST_V << EMAC_CST_S)
+#define EMAC_CST_V  0x00000001U
+#define EMAC_CST_S  25
+/** EMAC_SFTERR : R/W; bitpos: [26]; default: 0;
+ *  SMII Force Transmit Error When set, this bit indicates to the PHY to force a
+ *  transmit error in the SMII frame being transmitted This bit is reserved if the SMII
+ *  PHY port is not selected during core configuration
+ */
+#define EMAC_SFTERR    (BIT(26))
+#define EMAC_SFTERR_M  (EMAC_SFTERR_V << EMAC_SFTERR_S)
+#define EMAC_SFTERR_V  0x00000001U
+#define EMAC_SFTERR_S  26
+/** EMAC_TWOKPE : R/W; bitpos: [27]; default: 0;
+ *  IEEE 8023as Support for 2K Packets When set, the MAC considers all frames, with up
+ *  to 2,000 bytes length, as normal packets When Bit 20 _JE_ is not set, the MAC
+ *  considers all received frames of size more than 2K bytes as Giant frames When this
+ *  bit is reset and Bit 20 _JE_ is not set, the MAC considers all received frames of
+ *  size more than 1,518 bytes _1,522 bytes for tagged_ as Giant frames When Bit 20 is
+ *  set, setting this bit has no effect on Giant Frame status For more information
+ *  about how the setting of this bit and Bit 20 impact the Giant frame status, see
+ *  Table 631
+ */
+#define EMAC_TWOKPE    (BIT(27))
+#define EMAC_TWOKPE_M  (EMAC_TWOKPE_V << EMAC_TWOKPE_S)
+#define EMAC_TWOKPE_V  0x00000001U
+#define EMAC_TWOKPE_S  27
+/** EMAC_SARC : R/W; bitpos: [30:28]; default: 0;
+ *  Source Address Insertion or Replacement Control This field controls the source
+ *  address insertion or replacement for all transmitted frames Bit 30 specifies which
+ *  MAC Address register _0 or 1_ is used for source address insertion or replacement
+ *  based on the values of Bits [29:28]: 2'b0x: The input signals mti_sa_ctrl_i and
+ *  ati_sa_ctrl_i control the SA field generation 2'b10: 	If Bit 30 is set to 0, the
+ *  MAC inserts the content of the MAC Address 0 registers _registers 16 and 17_ in the
+ *  SA field of all transmitted frames 	If Bit 30 is set to 1 and the Enable MAC
+ *  Address Register 1 option is selected during core configuration, the MAC inserts
+ *  the content of the MAC Address 1 registers _registers 18 and 19_ in the SA field of
+ *  all transmitted frames 2'b11: 	If Bit 30 is set to 0, the MAC replaces the content
+ *  of the MAC Address 0 registers _registers 16 and 17_ in the SA field of all
+ *  transmitted frames 	If Bit 30 is set to 1 and the Enable MAC Address Register 1
+ *  option is selected during core configuration, the MAC replaces the content of the
+ *  MAC Address 1 registers _registers 18 and 19_ in the SA field of all transmitted
+ *  frames Note: Changes to this field take effect only on the start of a frame If you
+ *  write this register field when a frame is being transmitted, only the subsequent
+ *  frame can use the updated value, that is, the current frame does not use the
+ *  updated value These bits are reserved and RO when the Enable SA, VLAN, and CRC
+ *  Insertion on TX feature is not selected during core configuration
+ */
+#define EMAC_SARC    0x00000007U
+#define EMAC_SARC_M  (EMAC_SARC_V << EMAC_SARC_S)
+#define EMAC_SARC_V  0x00000007U
+#define EMAC_SARC_S  28
+
+/** EMAC_MACFRAMEFILTER_REG register
+ *  Contains the frame filtering controls
+ */
+#define EMAC_MACFRAMEFILTER_REG (DR_REG_EMAC_BASE + 0x4)
+/** EMAC_PROMISCUOUS_MODE : R/W; bitpos: [0]; default: 0;
+ *  Promiscuous Mode When this bit is set, the Address Filter module passes all
+ *  incoming frames irrespective of the destination or source address The SA or DA
+ *  Filter Fails status bits of the Receive Status Word are always cleared when PR is
+ *  set
+ */
+#define EMAC_PROMISCUOUS_MODE    (BIT(0))
+#define EMAC_PROMISCUOUS_MODE_M  (EMAC_PROMISCUOUS_MODE_V << EMAC_PROMISCUOUS_MODE_S)
+#define EMAC_PROMISCUOUS_MODE_V  0x00000001U
+#define EMAC_PROMISCUOUS_MODE_S  0
+/** EMAC_HUC : R/W; bitpos: [1]; default: 0;
+ *  Hash Unicast When set, the MAC performs destination address filtering of unicast
+ *  frames according to the hash table When reset, the MAC performs a perfect
+ *  destination address filtering for unicast frames, that is, it compares the DA field
+ *  with the values programmed in DA registers If Hash Filter is not selected during
+ *  core configuration, this bit is reserved _and RO_
+ */
+#define EMAC_HUC    (BIT(1))
+#define EMAC_HUC_M  (EMAC_HUC_V << EMAC_HUC_S)
+#define EMAC_HUC_V  0x00000001U
+#define EMAC_HUC_S  1
+/** EMAC_HMC : R/W; bitpos: [2]; default: 0;
+ *  Hash Multicast When set, the MAC performs destination address filtering of received
+ *  multicast frames according to the hash table When reset, the MAC performs a perfect
+ *  destination address filtering for multicast frames, that is, it compares the DA
+ *  field with the values programmed in DA registers If Hash Filter is not selected
+ *  during core configuration, this bit is reserved _and RO_
+ */
+#define EMAC_HMC    (BIT(2))
+#define EMAC_HMC_M  (EMAC_HMC_V << EMAC_HMC_S)
+#define EMAC_HMC_V  0x00000001U
+#define EMAC_HMC_S  2
+/** EMAC_DAIF : R/W; bitpos: [3]; default: 0;
+ *  DA Inverse Filtering When this bit is set, the Address Check block operates in
+ *  inverse filtering mode for the DA address comparison for both unicast and multicast
+ *  frames When reset, normal filtering of frames is performed
+ */
+#define EMAC_DAIF    (BIT(3))
+#define EMAC_DAIF_M  (EMAC_DAIF_V << EMAC_DAIF_S)
+#define EMAC_DAIF_V  0x00000001U
+#define EMAC_DAIF_S  3
+/** EMAC_PM : R/W; bitpos: [4]; default: 0;
+ *  Pass All Multicast When set, this bit indicates that all received frames with a
+ *  multicast destination address _first bit in the destination address field is '1'_
+ *  are passed When reset, filtering of multicast frame depends on HMC bit
+ */
+#define EMAC_PM    (BIT(4))
+#define EMAC_PM_M  (EMAC_PM_V << EMAC_PM_S)
+#define EMAC_PM_V  0x00000001U
+#define EMAC_PM_S  4
+/** EMAC_DBF : R/W; bitpos: [5]; default: 0;
+ *  Disable Broadcast Frames When this bit is set, the AFM module blocks all incoming
+ *  broadcast frames In addition, it overrides all other filter settings When this bit
+ *  is reset, the AFM module passes all received broadcast frames
+ */
+#define EMAC_DBF    (BIT(5))
+#define EMAC_DBF_M  (EMAC_DBF_V << EMAC_DBF_S)
+#define EMAC_DBF_V  0x00000001U
+#define EMAC_DBF_S  5
+/** EMAC_PCF : R/W; bitpos: [7:6]; default: 0;
+ *  Pass Control Frames These bits control the forwarding of all control frames
+ *  _including unicast and multicast Pause frames_ 00: MAC filters all control frames
+ *  from reaching the application 01: MAC forwards all control frames except Pause
+ *  frames to application even if they fail the Address filter 10: MAC forwards all
+ *  control frames to application even if they fail the Address Filter 11: MAC forwards
+ *  control frames that pass the Address Filter The following conditions should be true
+ *  for the Pause frames processing: Condition 1 : The MAC is in the fullduplex mode
+ *  and flow control is enabled by setting Bit 2 _RFE_ of Register 6 _Flow Control
+ *  Register_ to 1 Condition 2 : The destination address _DA_ of the received frame
+ *  matches the special multicast address or the MAC Address 0 when Bit 3 _UP_ of the
+ *  Register 6 _Flow Control Register_ is set Condition 3: The Type field of the
+ *  received frame is 0x8808 and the OPCODE field is 0x0001 Note: This field should be
+ *  set to 01 only when the Condition 1 is true, that is, the MAC is programmed to
+ *  operate in the fullduplex mode and the RFE bit is enabled Otherwise, the Pause
+ *  frame filtering may be inconsistent When Condition 1 is false, the Pause frames are
+ *  considered as generic control frames Therefore, to pass all control frames
+ *  _including Pause frames_ when the fullduplex mode and flow control is not enabled,
+ *  you should set the PCF field to 10 or 11 _as required by the application_
+ */
+#define EMAC_PCF    0x00000003U
+#define EMAC_PCF_M  (EMAC_PCF_V << EMAC_PCF_S)
+#define EMAC_PCF_V  0x00000003U
+#define EMAC_PCF_S  6
+/** EMAC_SAIF : R/W; bitpos: [8]; default: 0;
+ *  SA Inverse Filtering When this bit is set, the Address Check block operates in
+ *  inverse filtering mode for the SA address comparison The frames whose SA matches
+ *  the SA registers are marked as failing the SA Address filter When this bit is
+ *  reset, frames whose SA does not match the SA registers are marked as failing the SA
+ *  Address filter
+ */
+#define EMAC_SAIF    (BIT(8))
+#define EMAC_SAIF_M  (EMAC_SAIF_V << EMAC_SAIF_S)
+#define EMAC_SAIF_V  0x00000001U
+#define EMAC_SAIF_S  8
+/** EMAC_SAF : R/W; bitpos: [9]; default: 0;
+ *  Source Address Filter Enable When this bit is set, the MAC compares the SA field of
+ *  the received frames with the values programmed in the enabled SA registers If the
+ *  comparison fails, the MAC drops the frame When this bit is reset, the MAC forwards
+ *  the received frame to the application with updated SAF bit of the Rx Status
+ *  depending on the SA address comparison Note: According to the IEEE specification,
+ *  Bit 47 of the SA is reserved and set to 0 However, in DWC_EMAC, the MAC compares
+ *  all 48 bits The software driver should take this into consideration while
+ *  programming the MAC address registers for SA
+ */
+#define EMAC_SAF    (BIT(9))
+#define EMAC_SAF_M  (EMAC_SAF_V << EMAC_SAF_S)
+#define EMAC_SAF_V  0x00000001U
+#define EMAC_SAF_S  9
+/** EMAC_HPF : R/W; bitpos: [10]; default: 0;
+ *  Hash or Perfect Filter When this bit is set, it configures the address filter to
+ *  pass a frame if it matches either the perfect filtering or the hash filtering as
+ *  set by the HMC or HUC bits When this bit is low and the HUC or HMC bit is set, the
+ *  frame is passed only if it matches the Hash filter This bit is reserved _and RO_ if
+ *  the Hash filter is not selected during core configuration
+ */
+#define EMAC_HPF    (BIT(10))
+#define EMAC_HPF_M  (EMAC_HPF_V << EMAC_HPF_S)
+#define EMAC_HPF_V  0x00000001U
+#define EMAC_HPF_S  10
+/** EMAC_VTFE : R/W; bitpos: [16]; default: 0;
+ *  VLAN Tag Filter Enable When set, this bit enables the MAC to drop VLAN tagged
+ *  frames that do not match the VLAN Tag comparison When reset, the MAC forwards all
+ *  frames irrespective of the match status of the VLAN Tag
+ */
+#define EMAC_VTFE    (BIT(16))
+#define EMAC_VTFE_M  (EMAC_VTFE_V << EMAC_VTFE_S)
+#define EMAC_VTFE_V  0x00000001U
+#define EMAC_VTFE_S  16
+/** EMAC_IPFE : R/W; bitpos: [20]; default: 0;
+ *  Layer 3 and Layer 4 Filter Enable When set, this bit enables the MAC to drop frames
+ *  that do not match the enabled Layer 3 and Layer 4 filters If Layer 3 or Layer 4
+ *  filters are not enabled for matching, this bit does not have any effect When reset,
+ *  the MAC forwards all frames irrespective of the match status of the Layer 3 and
+ *  Layer 4 fields If the Layer 3 and Layer 4 Filtering feature is not selected during
+ *  core configuration, this bit is reserved _RO with default value_
+ */
+#define EMAC_IPFE    (BIT(20))
+#define EMAC_IPFE_M  (EMAC_IPFE_V << EMAC_IPFE_S)
+#define EMAC_IPFE_V  0x00000001U
+#define EMAC_IPFE_S  20
+/** EMAC_DNTU : R/W; bitpos: [21]; default: 0;
+ *  Drop nonTCP/UDP over IP Frames When set, this bit enables the MAC to drop the
+ *  nonTCP or UDP over IP frames The MAC forward only those frames that are processed
+ *  by the Layer 4 filter When reset, this bit enables the MAC to forward all nonTCP or
+ *  UDP over IP frames If the Layer 3 and Layer 4 Filtering feature is not selected
+ *  during core configuration, this bit is reserved _RO with default value_
+ */
+#define EMAC_DNTU    (BIT(21))
+#define EMAC_DNTU_M  (EMAC_DNTU_V << EMAC_DNTU_S)
+#define EMAC_DNTU_V  0x00000001U
+#define EMAC_DNTU_S  21
+/** EMAC_RA : R/W; bitpos: [31]; default: 0;
+ *  Receive All When this bit is set, the MAC Receiver module passes all received
+ *  frames, irrespective of whether they pass the address filter or not, to the
+ *  Application The result of the SA or DA filtering is updated _pass or fail_ in the
+ *  corresponding bits in the Receive Status Word When this bit is reset, the Receiver
+ *  module passes only those frames to the Application that pass the SA or DA address
+ *  filter
+ */
+#define EMAC_RA    (BIT(31))
+#define EMAC_RA_M  (EMAC_RA_V << EMAC_RA_S)
+#define EMAC_RA_V  0x00000001U
+#define EMAC_RA_S  31
+
+/** EMAC_HASHTABLEHIGH_REG register
+ *  Contains the higher 32 bits of the Multicast Hash table This register is present
+ *  only when you select the 64bit Hash filter function in coreConsultant _See Table 79_
+ */
+#define EMAC_HASHTABLEHIGH_REG (DR_REG_EMAC_BASE + 0x8)
+/** EMAC_HTH : R/W; bitpos: [31:0]; default: 0;
+ *  Hash Table High This field contains the upper 32 bits of the Hash table
+ */
+#define EMAC_HTH    0xFFFFFFFFU
+#define EMAC_HTH_M  (EMAC_HTH_V << EMAC_HTH_S)
+#define EMAC_HTH_V  0xFFFFFFFFU
+#define EMAC_HTH_S  0
+
+/** EMAC_HASHTABLELOW_REG register
+ *  Contains the lower 32 bits of the Multicast Hash table This register is present
+ *  only when you select the Hash filter function in coreConsultant _See Table 79_
+ */
+#define EMAC_HASHTABLELOW_REG (DR_REG_EMAC_BASE + 0xc)
+/** EMAC_HTL : R/W; bitpos: [31:0]; default: 0;
+ *  Hash Table Low This field contains the lower 32 bits of the Hash table
+ */
+#define EMAC_HTL    0xFFFFFFFFU
+#define EMAC_HTL_M  (EMAC_HTL_V << EMAC_HTL_S)
+#define EMAC_HTL_V  0xFFFFFFFFU
+#define EMAC_HTL_S  0
+
+/** EMAC_GMIIADDRESS_REG register
+ *  Controls the management cycles to an external PHY This register is present only
+ *  when you select the Station Management _MDIO_ feature in coreConsultant _See Table
+ *  726_
+ */
+#define EMAC_GMIIADDRESS_REG (DR_REG_EMAC_BASE + 0x10)
+/** EMAC_GB : R/W1S; bitpos: [0]; default: 0;
+ *  GMII Busy This bit should read logic 0 before writing to Register 4 and Register 5
+ *  During a PHY or RevMII register access, the software sets this bit to 1’b1 to
+ *  indicate that a Read or Write access is in progress Register 5 is invalid until
+ *  this bit is cleared by the MAC Therefore, Register 5 _GMII Data_ should be kept
+ *  valid until the MAC clears this bit during a PHY Write operation Similarly for a
+ *  read operation, the contents of Register 5 are not valid until this bit is cleared
+ *  The subsequent read or write operation should happen only after the previous
+ *  operation is complete Because there is no acknowledgment from the PHY to MAC after
+ *  a read or write operation is completed, there is no change in the functionality of
+ *  this bit even when the PHY is not present
+ */
+#define EMAC_GB    (BIT(0))
+#define EMAC_GB_M  (EMAC_GB_V << EMAC_GB_S)
+#define EMAC_GB_V  0x00000001U
+#define EMAC_GB_S  0
+/** EMAC_GW : R/W; bitpos: [1]; default: 0;
+ *  GMII Write When set, this bit indicates to the PHY or RevMII that this is a Write
+ *  operation using the GMII Data register If this bit is not set, it indicates that
+ *  this is a Read operation, that is, placing the data in the GMII Data register
+ */
+#define EMAC_GW    (BIT(1))
+#define EMAC_GW_M  (EMAC_GW_V << EMAC_GW_S)
+#define EMAC_GW_V  0x00000001U
+#define EMAC_GW_S  1
+/** EMAC_CR : R/W; bitpos: [5:2]; default: 0;
+ *  CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC
+ *  clock according to the CSR clock frequency used in your design The CSR clock
+ *  corresponding to different EMAC configurations is given in Table 92 on page 564 The
+ *  suggested range of CSR clock frequency applicable for each value _when Bit[5] = 0_
+ *  ensures that the MDC clock is approximately between the frequency range 10 MHz25
+ *  MHz 0000: The CSR clock frequency is 60100 MHz and the MDC clock frequency is CSR
+ *  clock/42 0001: The CSR clock frequency is 100150 MHz and the MDC clock frequency is
+ *  CSR clock/62 0010: The CSR clock frequency is 2035 MHz and the MDC clock frequency
+ *  is CSR clock/16 0011: The CSR clock frequency is 3560 MHz and the MDC clock
+ *  frequency is CSR clock/26 0100: The CSR clock frequency is 150250 MHz and the MDC
+ *  clock frequency is CSR clock/102 0101: The CSR clock frequency is 250300 MHz and
+ *  the MDC clock is CSR clock/124 0110, 0111: Reserved When Bit 5 is set, you can
+ *  achieve higher frequency of the MDC clock than the frequency limit of 25 MHz
+ *  _specified in the IEEE Std 8023_ and program a clock divider of lower value For
+ *  example, when CSR clock is of 100 MHz frequency and you program these bits as 1010,
+ *  then the resultant MDC clock is of 125 MHz which is outside the limit of IEEE 8023
+ *  specified range Program the following values only if the interfacing chips support
+ *  faster MDC clocks 1000: CSR clock/4 1001: CSR clock/6 1010: CSR clock/8 1011: CSR
+ *  clock/10 1100: CSR clock/12 1101: CSR clock/14 1110: CSR clock/16 1111: CSR
+ *  clock/18 These bits are not used for accessing RevMII These bits are readonly if
+ *  the RevMII interface is selected as single PHY interface
+ */
+#define EMAC_CR    0x0000000FU
+#define EMAC_CR_M  (EMAC_CR_V << EMAC_CR_S)
+#define EMAC_CR_V  0x0000000FU
+#define EMAC_CR_S  2
+/** EMAC_GR : R/W; bitpos: [10:6]; default: 0;
+ *  GMII Register These bits select the desired GMII register in the selected PHY
+ *  device For RevMII, these bits select the desired CSR register in the RevMII
+ *  Registers set
+ */
+#define EMAC_GR    0x0000001FU
+#define EMAC_GR_M  (EMAC_GR_V << EMAC_GR_S)
+#define EMAC_GR_V  0x0000001FU
+#define EMAC_GR_S  6
+/** EMAC_PA : R/W; bitpos: [15:11]; default: 0;
+ *  Physical Layer Address This field indicates which of the 32 possible PHY devices
+ *  are being accessed For RevMII, this field gives the PHY Address of the RevMII module
+ */
+#define EMAC_PA    0x0000001FU
+#define EMAC_PA_M  (EMAC_PA_V << EMAC_PA_S)
+#define EMAC_PA_V  0x0000001FU
+#define EMAC_PA_S  11
+
+/** EMAC_GMIIDATA_REG register
+ *  Contains the data to be written to or read from the PHY register This register is
+ *  present only when you select the Station Management _MDIO_ feature in
+ *  coreConsultant _See Table 726_
+ */
+#define EMAC_GMIIDATA_REG (DR_REG_EMAC_BASE + 0x14)
+/** EMAC_GD : R/W; bitpos: [15:0]; default: 0;
+ *  GMII Data This field contains the 16bit data value read from the PHY or RevMII
+ *  after a Management Read operation or the 16bit data value to be written to the PHY
+ *  or RevMII before a Management Write operation
+ */
+#define EMAC_GD    0x0000FFFFU
+#define EMAC_GD_M  (EMAC_GD_V << EMAC_GD_S)
+#define EMAC_GD_V  0x0000FFFFU
+#define EMAC_GD_S  0
+
+/** EMAC_FLOWCONTROL_REG register
+ *  Controls the generation of control frames
+ */
+#define EMAC_FLOWCONTROL_REG (DR_REG_EMAC_BASE + 0x18)
+/** EMAC_FCB_BPA : R/W1S; bitpos: [0]; default: 0;
+ *  Flow Control Busy or Backpressure Activate This bit initiates a Pause frame in the
+ *  fullduplex mode and activates the backpressure function in the halfduplex mode if
+ *  the TFE bit is set In the fullduplex mode, this bit should be read as 1'b0 before
+ *  writing to the Flow Control register To initiate a Pause frame, the Application
+ *  must set this bit to 1'b1 During a transfer of the Control Frame, this bit
+ *  continues to be set to signify that a frame transmission is in progress After the
+ *  completion of Pause frame transmission, the MAC resets this bit to 1'b0 The Flow
+ *  Control register should not be written to until this bit is cleared In the
+ *  halfduplex mode, when this bit is set _and TFE is set_, then backpressure is
+ *  asserted by the MAC During backpressure, when the MAC receives a new frame, the
+ *  transmitter starts sending a JAM pattern resulting in a collision This control
+ *  register bit is logically ORed with the mti_flowctrl_i input signal for the
+ *  backpressure function When the MAC is configured for the fullduplex mode, the BPA
+ *  is automatically disabled
+ */
+#define EMAC_FCB_BPA    (BIT(0))
+#define EMAC_FCB_BPA_M  (EMAC_FCB_BPA_V << EMAC_FCB_BPA_S)
+#define EMAC_FCB_BPA_V  0x00000001U
+#define EMAC_FCB_BPA_S  0
+/** EMAC_TFE : R/W; bitpos: [1]; default: 0;
+ *  Transmit Flow Control Enable In the fullduplex mode, when this bit is set, the MAC
+ *  enables the flow control operation to transmit Pause frames When this bit is reset,
+ *  the flow control operation in the MAC is disabled, and the MAC does not transmit
+ *  any Pause frames In the halfduplex mode, when this bit is set, the MAC enables the
+ *  backpressure operation When this bit is reset, the backpressure feature is disabled
+ */
+#define EMAC_TFE    (BIT(1))
+#define EMAC_TFE_M  (EMAC_TFE_V << EMAC_TFE_S)
+#define EMAC_TFE_V  0x00000001U
+#define EMAC_TFE_S  1
+/** EMAC_RECEIVE_FLOW_CTRL_E : R/W; bitpos: [2]; default: 0;
+ *  Receive Flow Control Enable When this bit is set, the MAC decodes the received
+ *  Pause frame and disables its transmitter for a specified _Pause_ time When this bit
+ *  is reset, the decode function of the Pause frame is disabled
+ */
+#define EMAC_RECEIVE_FLOW_CTRL_E    (BIT(2))
+#define EMAC_RECEIVE_FLOW_CTRL_E_M  (EMAC_RECEIVE_FLOW_CTRL_E_V << EMAC_RECEIVE_FLOW_CTRL_E_S)
+#define EMAC_RECEIVE_FLOW_CTRL_E_V  0x00000001U
+#define EMAC_RECEIVE_FLOW_CTRL_E_S  2
+/** EMAC_UP : R/W; bitpos: [3]; default: 0;
+ *  Unicast Pause Frame Detect A pause frame is processed when it has the unique
+ *  multicast address specified in the IEEE Std 8023 When this bit is set, the MAC can
+ *  also detect Pause frames with unicast address of the station This unicast address
+ *  should be as specified in the MAC Address0 High Register and MAC Address0 Low
+ *  Register When this bit is reset, the MAC only detects Pause frames with unique
+ *  multicast address Note: The MAC does not process a Pause frame if the multicast
+ *  address of received frame is different from the unique multicast address
+ */
+#define EMAC_UP    (BIT(3))
+#define EMAC_UP_M  (EMAC_UP_V << EMAC_UP_S)
+#define EMAC_UP_V  0x00000001U
+#define EMAC_UP_S  3
+/** EMAC_PLT : R/W; bitpos: [5:4]; default: 0;
+ *  Pause Low Threshold This field configures the threshold of the Pause timer at which
+ *  the input flow control signal mti_flowctrl_i _or sbd_flowctrl_i_ is checked for
+ *  automatic retransmission of the Pause frame The threshold values should be always
+ *  less than the Pause Time configured in Bits[31:16] For example, if PT = 100H _256
+ *  slottimes_, and PLT = 01, then a second Pause frame is automatically transmitted if
+ *  the mti_flowctrl_i signal is asserted at 228 _256  28_ slot times after the first
+ *  Pause frame is transmitted The following list provides the threshold values for
+ *  different values: 00: The threshold is Pause time minus 4 slot times _PT  4 slot
+ *  times_ 01: The threshold is Pause time minus 28 slot times _PT  28 slot times_ 10:
+ *  The threshold is Pause time minus 144 slot times _PT  144 slot times_ 11: The
+ *  threshold is Pause time minus 256 slot times _PT  256 slot times_ The slot time is
+ *  defined as the time taken to transmit 512 bits _64 bytes_ on the GMII or MII
+ *  interface
+ */
+#define EMAC_PLT    0x00000003U
+#define EMAC_PLT_M  (EMAC_PLT_V << EMAC_PLT_S)
+#define EMAC_PLT_V  0x00000003U
+#define EMAC_PLT_S  4
+/** EMAC_DZPQ : R/W; bitpos: [7]; default: 0;
+ *  Disable ZeroQuanta Pause When this bit is set, it disables the automatic generation
+ *  of the ZeroQuanta Pause frames on the deassertion of the flowcontrol signal from
+ *  the FIFO layer _MTL or external sideband flow control signal
+ *  sbd_flowctrl_i/mti_flowctrl_i_ When this bit is reset, normal operation with
+ *  automatic ZeroQuanta Pause frame generation is enabled
+ */
+#define EMAC_DZPQ    (BIT(7))
+#define EMAC_DZPQ_M  (EMAC_DZPQ_V << EMAC_DZPQ_S)
+#define EMAC_DZPQ_V  0x00000001U
+#define EMAC_DZPQ_S  7
+/** EMAC_PT : R/W; bitpos: [31:16]; default: 0;
+ *  Pause Time This field holds the value to be used in the Pause Time field in the
+ *  transmit control frame If the Pause Time bits is configured to be
+ *  doublesynchronized to the _G_MII clock domain, then consecutive writes to this
+ *  register should be performed only after at least four clock cycles in the
+ *  destination clock domain
+ */
+#define EMAC_PT    0x0000FFFFU
+#define EMAC_PT_M  (EMAC_PT_V << EMAC_PT_S)
+#define EMAC_PT_V  0x0000FFFFU
+#define EMAC_PT_S  16
+
+/** EMAC_VLANTAG_REG register
+ *  Identifies IEEE 8021Q VLAN type frames
+ */
+#define EMAC_VLANTAG_REG (DR_REG_EMAC_BASE + 0x1c)
+/** EMAC_VL : R/W; bitpos: [15:0]; default: 0;
+ *  VLAN Tag Identifier for Receive Frames This field contains the 8021Q VLAN tag to
+ *  identify the VLAN frames and is compared to the 15th and 16th bytes of the frames
+ *  being received for VLAN frames The following list describes the bits of this field:
+ *  Bits [15:13]: User Priority Bit 12: Canonical Format Indicator _CFI_ or Drop
+ *  Eligible Indicator _DEI_ Bits[11:0]: VLAN tag’s VLAN Identifier _VID_ field When
+ *  the ETV bit is set, only the VID _Bits[11:0]_ is used for comparison If VL
+ *  _VL[11:0] if ETV is set_ is all zeros, the MAC does not check the fifteenth and
+ *  16th bytes for VLAN tag comparison, and declares all frames with a Type field value
+ *  of 0x8100 or 0x88a8 as VLAN frames
+ */
+#define EMAC_VL    0x0000FFFFU
+#define EMAC_VL_M  (EMAC_VL_V << EMAC_VL_S)
+#define EMAC_VL_V  0x0000FFFFU
+#define EMAC_VL_S  0
+/** EMAC_ETV : R/W; bitpos: [16]; default: 0;
+ *  Enable 12-Bit VLAN Tag Comparison
+ */
+#define EMAC_ETV    (BIT(16))
+#define EMAC_ETV_M  (EMAC_ETV_V << EMAC_ETV_S)
+#define EMAC_ETV_V  0x00000001U
+#define EMAC_ETV_S  16
+/** EMAC_VTIM : R/W; bitpos: [17]; default: 0;
+ *  VLAN Tag Inverse Match Enable When set, this bit enables the VLAN Tag inverse
+ *  matching The frames that do not have matching VLAN Tag are marked as matched When
+ *  reset, this bit enables the VLAN Tag perfect matching The frames with matched VLAN
+ *  Tag are marked as matched
+ */
+#define EMAC_VTIM    (BIT(17))
+#define EMAC_VTIM_M  (EMAC_VTIM_V << EMAC_VTIM_S)
+#define EMAC_VTIM_V  0x00000001U
+#define EMAC_VTIM_S  17
+/** EMAC_ESVL : R/W; bitpos: [18]; default: 0;
+ *  Enable SVLAN When this bit is set, the MAC transmitter and receiver also consider
+ *  the SVLAN _Type = 0x88A8_ frames as valid VLAN tagged frames
+ */
+#define EMAC_ESVL    (BIT(18))
+#define EMAC_ESVL_M  (EMAC_ESVL_V << EMAC_ESVL_S)
+#define EMAC_ESVL_V  0x00000001U
+#define EMAC_ESVL_S  18
+/** EMAC_VTHM : R/W; bitpos: [19]; default: 0;
+ *  VLAN Tag Hash Table Match Enable When set, the most significant four bits of the
+ *  VLAN tag’s CRC are used to index the content of Register 354 _VLAN Hash Table
+ *  Register_ A value of 1 in the VLAN Hash Table register, corresponding to the index,
+ *  indicates that the frame matched the VLAN hash table When Bit 16 _ETV_ is set, the
+ *  CRC of the 12bit VLAN Identifier _VID_ is used for comparison whereas when ETV is
+ *  reset, the CRC of the 16bit VLAN tag is used for comparison When reset, the VLAN
+ *  Hash Match operation is not performed If the VLAN Hash feature is not enabled
+ *  during core configuration, this bit is reserved _RO with default value_
+ */
+#define EMAC_VTHM    (BIT(19))
+#define EMAC_VTHM_M  (EMAC_VTHM_V << EMAC_VTHM_S)
+#define EMAC_VTHM_V  0x00000001U
+#define EMAC_VTHM_S  19
+
+/** EMAC_VERSION_REG register
+ *  Identifies the version of the Core
+ */
+#define EMAC_VERSION_REG (DR_REG_EMAC_BASE + 0x20)
+/** EMAC_SNPSVER : RO; bitpos: [7:0]; default: 55;
+ *  Synopsysdefined Version _37_
+ */
+#define EMAC_SNPSVER    0x000000FFU
+#define EMAC_SNPSVER_M  (EMAC_SNPSVER_V << EMAC_SNPSVER_S)
+#define EMAC_SNPSVER_V  0x000000FFU
+#define EMAC_SNPSVER_S  0
+/** EMAC_USERVER : RO; bitpos: [15:8]; default: 0;
+ *  Userdefined Version _configured with coreConsultant_
+ */
+#define EMAC_USERVER    0x000000FFU
+#define EMAC_USERVER_M  (EMAC_USERVER_V << EMAC_USERVER_S)
+#define EMAC_USERVER_V  0x000000FFU
+#define EMAC_USERVER_S  8
+
+/** EMAC_DEBUG_REG register
+ *  Gives the status of various internal blocks for debugging
+ */
+#define EMAC_DEBUG_REG (DR_REG_EMAC_BASE + 0x24)
+/** EMAC_RPESTS : RO; bitpos: [0]; default: 0;
+ *  MAC GMII or MII Receive Protocol Engine Status When high, this bit indicates that
+ *  the MAC GMII or MII receive protocol engine is actively receiving data and not in
+ *  IDLE state
+ */
+#define EMAC_RPESTS    (BIT(0))
+#define EMAC_RPESTS_M  (EMAC_RPESTS_V << EMAC_RPESTS_S)
+#define EMAC_RPESTS_V  0x00000001U
+#define EMAC_RPESTS_S  0
+/** EMAC_RFCFCSTS : RO; bitpos: [2:1]; default: 0;
+ *  MAC Receive Frame FIFO Controller Status When high, this field indicates the active
+ *  state of the small FIFO Read and Write controllers of the MAC Receive Frame
+ *  Controller Module RFCFCSTS[1] represents the status of small FIFO Read controller
+ *  RFCFCSTS[0] represents the status of small FIFO Write controller
+ */
+#define EMAC_RFCFCSTS    0x00000003U
+#define EMAC_RFCFCSTS_M  (EMAC_RFCFCSTS_V << EMAC_RFCFCSTS_S)
+#define EMAC_RFCFCSTS_V  0x00000003U
+#define EMAC_RFCFCSTS_S  1
+/** EMAC_RWCSTS : RO; bitpos: [4]; default: 0;
+ *  MTL Rx FIFO Write Controller Active Status When high, this bit indicates that the
+ *  MTL Rx FIFO Write Controller is active and is transferring a received frame to the
+ *  FIFO
+ */
+#define EMAC_RWCSTS    (BIT(4))
+#define EMAC_RWCSTS_M  (EMAC_RWCSTS_V << EMAC_RWCSTS_S)
+#define EMAC_RWCSTS_V  0x00000001U
+#define EMAC_RWCSTS_S  4
+/** EMAC_RRCSTS : RO; bitpos: [6:5]; default: 0;
+ *  MTL RxFIFO Read Controller State This field gives the state of the Rx FIFO read
+ *  Controller: 00: IDLE state 01: Reading frame data 10: Reading frame status _or
+ *  timestamp_ 11: Flushing the frame data and status
+ */
+#define EMAC_RRCSTS    0x00000003U
+#define EMAC_RRCSTS_M  (EMAC_RRCSTS_V << EMAC_RRCSTS_S)
+#define EMAC_RRCSTS_V  0x00000003U
+#define EMAC_RRCSTS_S  5
+/** EMAC_RXFSTS : RO; bitpos: [9:8]; default: 0;
+ *  MTL RxFIFO FillLevel Status This field gives the status of the filllevel of the Rx
+ *  FIFO: 00: Rx FIFO Empty 01: Rx FIFO filllevel below flowcontrol deactivate
+ *  threshold 10: Rx FIFO filllevel above flowcontrol activate threshold 11: Rx FIFO
+ *  Full
+ */
+#define EMAC_RXFSTS    0x00000003U
+#define EMAC_RXFSTS_M  (EMAC_RXFSTS_V << EMAC_RXFSTS_S)
+#define EMAC_RXFSTS_V  0x00000003U
+#define EMAC_RXFSTS_S  8
+/** EMAC_TPESTS : RO; bitpos: [16]; default: 0;
+ *  MAC GMII or MII Transmit Protocol Engine Status When high, this bit indicates that
+ *  the MAC GMII or MII transmit protocol engine is actively transmitting data and is
+ *  not in the IDLE state
+ */
+#define EMAC_TPESTS    (BIT(16))
+#define EMAC_TPESTS_M  (EMAC_TPESTS_V << EMAC_TPESTS_S)
+#define EMAC_TPESTS_V  0x00000001U
+#define EMAC_TPESTS_S  16
+/** EMAC_TFCSTS : RO; bitpos: [18:17]; default: 0;
+ *  MAC Transmit Frame Controller Status This field indicates the state of the MAC
+ *  Transmit Frame Controller module: 00: IDLE state 01: Waiting for status of previous
+ *  frame or IFG or backoff period to be over 10: Generating and transmitting a Pause
+ *  frame _in the fullduplex mode_ 11: Transferring input frame for transmission
+ */
+#define EMAC_TFCSTS    0x00000003U
+#define EMAC_TFCSTS_M  (EMAC_TFCSTS_V << EMAC_TFCSTS_S)
+#define EMAC_TFCSTS_V  0x00000003U
+#define EMAC_TFCSTS_S  17
+/** EMAC_TXPAUSED : RO; bitpos: [19]; default: 0;
+ *  MAC Transmitter in Pause When high, this bit indicates that the MAC transmitter is
+ *  in the Pause condition _in the fullduplexonly mode_ and hence does not schedule any
+ *  frame for transmission
+ */
+#define EMAC_TXPAUSED    (BIT(19))
+#define EMAC_TXPAUSED_M  (EMAC_TXPAUSED_V << EMAC_TXPAUSED_S)
+#define EMAC_TXPAUSED_V  0x00000001U
+#define EMAC_TXPAUSED_S  19
+/** EMAC_TRCSTS : RO; bitpos: [21:20]; default: 0;
+ *  MTL Tx FIFO Read Controller Status This field indicates the state of the Tx FIFO
+ *  Read Controller: 00: IDLE state 01: READ state _transferring data to the MAC
+ *  transmitter_ 10: Waiting for TxStatus from the MAC transmitter 11: Writing the
+ *  received TxStatus or flushing the Tx FIFO
+ */
+#define EMAC_TRCSTS    0x00000003U
+#define EMAC_TRCSTS_M  (EMAC_TRCSTS_V << EMAC_TRCSTS_S)
+#define EMAC_TRCSTS_V  0x00000003U
+#define EMAC_TRCSTS_S  20
+/** EMAC_TWCSTS : RO; bitpos: [22]; default: 0;
+ *  MTL Tx FIFO Write Controller Status When high, this bit indicates that the MTL Tx
+ *  FIFO Write Controller is active and is transferring data to the Tx FIFO
+ */
+#define EMAC_TWCSTS    (BIT(22))
+#define EMAC_TWCSTS_M  (EMAC_TWCSTS_V << EMAC_TWCSTS_S)
+#define EMAC_TWCSTS_V  0x00000001U
+#define EMAC_TWCSTS_S  22
+/** EMAC_TXFSTS : RO; bitpos: [24]; default: 0;
+ *  MTL Tx FIFO Not Empty Status When high, this bit indicates that the MTL Tx FIFO is
+ *  not empty and some data is left for transmission
+ */
+#define EMAC_TXFSTS    (BIT(24))
+#define EMAC_TXFSTS_M  (EMAC_TXFSTS_V << EMAC_TXFSTS_S)
+#define EMAC_TXFSTS_V  0x00000001U
+#define EMAC_TXFSTS_S  24
+/** EMAC_TXSTSFSTS : RO; bitpos: [25]; default: 0;
+ *  MTL TxStatus FIFO Full Status When high, this bit indicates that the MTL TxStatus
+ *  FIFO is full Therefore, the MTL cannot accept any more frames for transmission This
+ *  bit is reserved in the EMACAHB and EMACDMA configurations
+ */
+#define EMAC_TXSTSFSTS    (BIT(25))
+#define EMAC_TXSTSFSTS_M  (EMAC_TXSTSFSTS_V << EMAC_TXSTSFSTS_S)
+#define EMAC_TXSTSFSTS_V  0x00000001U
+#define EMAC_TXSTSFSTS_S  25
+
+/** EMAC_REMOTEWAKEUPFRAMEFILTER_REG register
+ *  Remote Wake-Up Frame Filter Register
+ */
+#define EMAC_REMOTEWAKEUPFRAMEFILTER_REG (DR_REG_EMAC_BASE + 0x28)
+/** EMAC_WKUPFRM_FILTER : R/W; bitpos: [31:0]; default: 0;
+ *  This is the address through which the application writes or reads the remote
+ *  wake-up frame filter registers.The reg_wkupfrm_filter register is a pointer to
+ *  eight reg_wkupfrm_filter registers.The reg_wkupfrm_filter register is loaded by
+ *  sequentially loading the eight register values.Eight sequential writes to this
+ *  address(0x0028)write all reg_wkupfrm_filter registers.Similarly, eight sequential
+ *  reads from this address(0x0028) read all reg_wkupfrm_filter registers.
+ *  This register is present only when you select the PMT module Remote Wake-Up feature
+ *  in coreConsultant.
+ */
+#define EMAC_WKUPFRM_FILTER    0xFFFFFFFFU
+#define EMAC_WKUPFRM_FILTER_M  (EMAC_WKUPFRM_FILTER_V << EMAC_WKUPFRM_FILTER_S)
+#define EMAC_WKUPFRM_FILTER_V  0xFFFFFFFFU
+#define EMAC_WKUPFRM_FILTER_S  0
+
+/** EMAC_PMTCONTROLANDSTATUS_REG register
+ *  PMT Control and Status Register. This register is present only when you select the
+ *  PMT module in coreConsultant.
+ */
+#define EMAC_PMTCONTROLANDSTATUS_REG (DR_REG_EMAC_BASE + 0x2c)
+/** EMAC_PWRDWN : R/W1S; bitpos: [0]; default: 0;
+ *  Power Down
+ *  When set, the MAC receiver drops all received frames until it receives the expected
+ *  magic packet or remote wake-up frame. This bit is then self-cleared and the
+ *  power-down mode is disabled. The Software can also clear this bit before the
+ *  expected magic packet or remote wake-up frame is received. The frames, received by
+ *  MAC after this bit is cleared, are forwarded to the application. This bit must only
+ *  be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable
+ *  bit is set high.
+ */
+#define EMAC_PWRDWN    (BIT(0))
+#define EMAC_PWRDWN_M  (EMAC_PWRDWN_V << EMAC_PWRDWN_S)
+#define EMAC_PWRDWN_V  0x00000001U
+#define EMAC_PWRDWN_S  0
+/** EMAC_MGKPKTEN : R/W; bitpos: [1]; default: 0;
+ *  Magic Packet Enable
+ *  When set, enables generation of a power management event because of magic packet
+ *  reception.
+ */
+#define EMAC_MGKPKTEN    (BIT(1))
+#define EMAC_MGKPKTEN_M  (EMAC_MGKPKTEN_V << EMAC_MGKPKTEN_S)
+#define EMAC_MGKPKTEN_V  0x00000001U
+#define EMAC_MGKPKTEN_S  1
+/** EMAC_RWKPKTEN : R/W; bitpos: [2]; default: 0;
+ *  Remote Wake-Up Frame Enable
+ *  When set, enables generation of a power management event because of remote wake-up
+ *  frame reception.
+ */
+#define EMAC_RWKPKTEN    (BIT(2))
+#define EMAC_RWKPKTEN_M  (EMAC_RWKPKTEN_V << EMAC_RWKPKTEN_S)
+#define EMAC_RWKPKTEN_V  0x00000001U
+#define EMAC_RWKPKTEN_S  2
+/** EMAC_MGKPRCVD : R/W; bitpos: [5]; default: 0;
+ *  Magic Packet Received
+ *  When set,this bit indicates that the power management event is generated because of
+ *  the reception of a magic packet. This bit is cleared by Read into this register.
+ */
+#define EMAC_MGKPRCVD    (BIT(5))
+#define EMAC_MGKPRCVD_M  (EMAC_MGKPRCVD_V << EMAC_MGKPRCVD_S)
+#define EMAC_MGKPRCVD_V  0x00000001U
+#define EMAC_MGKPRCVD_S  5
+/** EMAC_RWKPRCVD : R/W; bitpos: [6]; default: 0;
+ *  Remote Wake-Up Frame Received
+ *  When set, this bit indicates the power management event is generated because of the
+ *  reception of a remote wake-up frame. This bit is cleared by a Read into this
+ *  register.
+ */
+#define EMAC_RWKPRCVD    (BIT(6))
+#define EMAC_RWKPRCVD_M  (EMAC_RWKPRCVD_V << EMAC_RWKPRCVD_S)
+#define EMAC_RWKPRCVD_V  0x00000001U
+#define EMAC_RWKPRCVD_S  6
+/** EMAC_GLBLUCAST : R/W; bitpos: [9]; default: 0;
+ *  Global Unicast.
+ *  When set, enables any unicast packet filtered by the MAX(DAF) address recognition
+ *  to be a remote wake-up frame.
+ */
+#define EMAC_GLBLUCAST    (BIT(9))
+#define EMAC_GLBLUCAST_M  (EMAC_GLBLUCAST_V << EMAC_GLBLUCAST_S)
+#define EMAC_GLBLUCAST_V  0x00000001U
+#define EMAC_GLBLUCAST_S  9
+/** EMAC_RWKPTR : RO; bitpos: [28:24]; default: 0;
+ *  Remote Wake-up FIFO Pointer.
+ *  This field gives the current value(0 to 31) of the Remote Wake-up Frame filter
+ *  register pointer. When the value of this pointer is erual to 7, 15, 23 or 31, the
+ *  contents of the Remote Wake-up Frame Filter Register are transferred to the
+ *  clk_rx_i domain when a write occurs to that register.
+ *  The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the
+ *  number of Remote Wakeup Filters selected during configuration.
+ */
+#define EMAC_RWKPTR    0x0000001FU
+#define EMAC_RWKPTR_M  (EMAC_RWKPTR_V << EMAC_RWKPTR_S)
+#define EMAC_RWKPTR_V  0x0000001FU
+#define EMAC_RWKPTR_S  24
+/** EMAC_RWKFILTRST : R/W1S; bitpos: [31]; default: 0;
+ *  Remote Wake-Up Frame Filter Register Pointer Reset.
+ *  When this bit is set, it resets the remote wake-up frame filter register pointer to
+ *  3'b000. It is automatically cleared after 1 clock cycle.
+ */
+#define EMAC_RWKFILTRST    (BIT(31))
+#define EMAC_RWKFILTRST_M  (EMAC_RWKFILTRST_V << EMAC_RWKFILTRST_S)
+#define EMAC_RWKFILTRST_V  0x00000001U
+#define EMAC_RWKFILTRST_S  31
+
+/** EMAC_LPICONTROLANDSTATUS_REG register
+ *  Controls the Low Power Idle _LPI_ operations and provides the LPI status of the
+ *  core This register is present only when you select the Energy Efficient Ethernet
+ *  feature in coreConsultant
+ */
+#define EMAC_LPICONTROLANDSTATUS_REG (DR_REG_EMAC_BASE + 0x30)
+/** EMAC_TLPIEN : R/W; bitpos: [0]; default: 0;
+ *  Transmit LPI Entry When set, this bit indicates that the MAC Transmitter has
+ *  entered the LPI state because of the setting of the LPIEN bit This bit is cleared
+ *  by a read into this register
+ */
+#define EMAC_TLPIEN    (BIT(0))
+#define EMAC_TLPIEN_M  (EMAC_TLPIEN_V << EMAC_TLPIEN_S)
+#define EMAC_TLPIEN_V  0x00000001U
+#define EMAC_TLPIEN_S  0
+/** EMAC_TLPIEX : R/W; bitpos: [1]; default: 0;
+ *  Transmit LPI Exit When set, this bit indicates that the MAC transmitter has exited
+ *  the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has
+ *  expired This bit is cleared by a read into this register
+ */
+#define EMAC_TLPIEX    (BIT(1))
+#define EMAC_TLPIEX_M  (EMAC_TLPIEX_V << EMAC_TLPIEX_S)
+#define EMAC_TLPIEX_V  0x00000001U
+#define EMAC_TLPIEX_S  1
+/** EMAC_RLPIEN : R/W; bitpos: [2]; default: 0;
+ *  Receive LPI Entry When set, this bit indicates that the MAC Receiver has received
+ *  an LPI pattern and entered the LPI state This bit is cleared by a read into this
+ *  register Note: This bit may not get set if the MAC stops receiving the LPI pattern
+ *  for a very short duration, such as, less than 3 clock cycles of CSR clock
+ */
+#define EMAC_RLPIEN    (BIT(2))
+#define EMAC_RLPIEN_M  (EMAC_RLPIEN_V << EMAC_RLPIEN_S)
+#define EMAC_RLPIEN_V  0x00000001U
+#define EMAC_RLPIEN_S  2
+/** EMAC_RLPIEX : R/W; bitpos: [3]; default: 0;
+ *  Receive LPI Exit When set, this bit indicates that the MAC Receiver has stopped
+ *  receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and
+ *  resumed the normal reception This bit is cleared by a read into this register Note:
+ *  This bit may not get set if the MAC stops receiving the LPI pattern for a very
+ *  short duration, such as, less than 3 clock cycles of CSR clock
+ */
+#define EMAC_RLPIEX    (BIT(3))
+#define EMAC_RLPIEX_M  (EMAC_RLPIEX_V << EMAC_RLPIEX_S)
+#define EMAC_RLPIEX_V  0x00000001U
+#define EMAC_RLPIEX_S  3
+/** EMAC_TLPIST : RO; bitpos: [8]; default: 0;
+ *  Transmit LPI State When set, this bit indicates that the MAC is transmitting the
+ *  LPI pattern on the GMII or MII interface
+ */
+#define EMAC_TLPIST    (BIT(8))
+#define EMAC_TLPIST_M  (EMAC_TLPIST_V << EMAC_TLPIST_S)
+#define EMAC_TLPIST_V  0x00000001U
+#define EMAC_TLPIST_S  8
+/** EMAC_RLPIST : RO; bitpos: [9]; default: 0;
+ *  Receive LPI State When set, this bit indicates that the MAC is receiving the LPI
+ *  pattern on the GMII or MII interface
+ */
+#define EMAC_RLPIST    (BIT(9))
+#define EMAC_RLPIST_M  (EMAC_RLPIST_V << EMAC_RLPIST_S)
+#define EMAC_RLPIST_V  0x00000001U
+#define EMAC_RLPIST_S  9
+/** EMAC_LPIEN : R/W; bitpos: [16]; default: 0;
+ *  LPI Enable When set, this bit instructs the MAC Transmitter to enter the LPI state
+ *  When reset, this bit instructs the MAC to exit the LPI state and resume normal
+ *  transmission This bit is cleared when the LPITXA bit is set and the MAC exits the
+ *  LPI state because of the arrival of a new packet for transmission
+ */
+#define EMAC_LPIEN    (BIT(16))
+#define EMAC_LPIEN_M  (EMAC_LPIEN_V << EMAC_LPIEN_S)
+#define EMAC_LPIEN_V  0x00000001U
+#define EMAC_LPIEN_S  16
+/** EMAC_PLS : R/W; bitpos: [17]; default: 0;
+ *  PHY Link Status This bit indicates the link status of the PHY The MAC Transmitter
+ *  asserts the LPI pattern only when the link status is up _okay_ at least for the
+ *  time indicated by the LPI LS TIMER When set, the link is considered to be okay _up_
+ *  and when reset, the link is considered to be down
+ */
+#define EMAC_PLS    (BIT(17))
+#define EMAC_PLS_M  (EMAC_PLS_V << EMAC_PLS_S)
+#define EMAC_PLS_V  0x00000001U
+#define EMAC_PLS_S  17
+/** EMAC_PLSEN : R/W; bitpos: [18]; default: 0;
+ *  PHY Link Status Enable This bit enables the link status received on the RGMII,
+ *  SGMII, or SMII receive paths to be used for activating the LPI LS TIMER When set,
+ *  the MAC uses the linkstatus bits of Register 54 _SGMII/RGMII/SMII Control and
+ *  Status Register_ and Bit 17 _PLS_ for the LPI LS Timer trigger When cleared, the
+ *  MAC ignores the linkstatus bits of Register 54 and takes only the PLS bit This bit
+ *  is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface
+ */
+#define EMAC_PLSEN    (BIT(18))
+#define EMAC_PLSEN_M  (EMAC_PLSEN_V << EMAC_PLSEN_S)
+#define EMAC_PLSEN_V  0x00000001U
+#define EMAC_PLSEN_S  18
+/** EMAC_LPITXA : R/W; bitpos: [19]; default: 0;
+ *  LPI TX Automate This bit controls the behavior of the MAC when it is entering or
+ *  coming out of the LPI mode on the transmit side This bit is not functional in the
+ *  EMAC CORE configuration in which the Tx clock gating is done during the LPI mode If
+ *  the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all
+ *  outstanding frames _in the core_ and pending frames _in the application interface_
+ *  have been transmitted The MAC comes out of the LPI mode when the application sends
+ *  any frame for transmission or the application issues a TX FIFO Flush command In
+ *  addition, the MAC automatically clears the LPIEN bit when it exits the LPI state If
+ *  TX FIFO Flush is set in Bit 20 of Register 6 _Operation Mode Register_, when the
+ *  MAC is in the LPI mode, the MAC exits the LPI mode When this bit is 0, the LPIEN
+ *  bit directly controls behavior of the MAC when it is entering or coming out of the
+ *  LPI mode
+ */
+#define EMAC_LPITXA    (BIT(19))
+#define EMAC_LPITXA_M  (EMAC_LPITXA_V << EMAC_LPITXA_S)
+#define EMAC_LPITXA_V  0x00000001U
+#define EMAC_LPITXA_S  19
+
+/** EMAC_LPITIMERSCONTROL_REG register
+ *  Controls the timeout values in LPI states This register is present only when you
+ *  select the Energy Efficient Ethernet feature in coreConsultant
+ */
+#define EMAC_LPITIMERSCONTROL_REG (DR_REG_EMAC_BASE + 0x34)
+/** EMAC_TWT : R/W; bitpos: [15:0]; default: 0;
+ *  LPI TW TIMER This field specifies the minimum time _in microseconds_ for which the
+ *  MAC waits after it stops transmitting the LPI pattern to the PHY and before it
+ *  resumes the normal transmission The TLPIEX status bit is set after the expiry of
+ *  this timer
+ */
+#define EMAC_TWT    0x0000FFFFU
+#define EMAC_TWT_M  (EMAC_TWT_V << EMAC_TWT_S)
+#define EMAC_TWT_V  0x0000FFFFU
+#define EMAC_TWT_S  0
+/** EMAC_LST : R/W; bitpos: [25:16]; default: 1000;
+ *  LPI LS TIMER This field specifies the minimum time _in milliseconds_ for which the
+ *  link status from the PHY should be up _OKAY_ before the LPI pattern can be
+ *  transmitted to the PHY The MAC does not transmit the LPI pattern even when the
+ *  LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count The
+ *  default value of the LPI LS Timer is 1000 _1 sec_ as defined in the IEEE standard
+ */
+#define EMAC_LST    0x000003FFU
+#define EMAC_LST_M  (EMAC_LST_V << EMAC_LST_S)
+#define EMAC_LST_V  0x000003FFU
+#define EMAC_LST_S  16
+
+/** EMAC_INTERRUPTSTATUS_REG register
+ *  Contains the interrupt status
+ */
+#define EMAC_INTERRUPTSTATUS_REG (DR_REG_EMAC_BASE + 0x38)
+/** EMAC_RGSMIIIS : RO; bitpos: [0]; default: 0;
+ *  RGMII or SMII Interrupt Status This bit is set because of any change in value of
+ *  the Link Status of RGMII or SMII interface _Bit 3 in Register 54 _SGMII/RGMII/SMII
+ *  Control and Status Register__ This bit is cleared when you perform a read operation
+ *  on the SGMII/RGMII/SMII Control and Status Register This bit is valid only when you
+ *  select the optional RGMII or SMII PHY interface during core configuration and
+ *  operation
+ */
+#define EMAC_RGSMIIIS    (BIT(0))
+#define EMAC_RGSMIIIS_M  (EMAC_RGSMIIIS_V << EMAC_RGSMIIIS_S)
+#define EMAC_RGSMIIIS_V  0x00000001U
+#define EMAC_RGSMIIIS_S  0
+/** EMAC_PCSLCHGIS : RO; bitpos: [1]; default: 0;
+ *  PCS Link Status Changed This bit is set because of any change in Link Status in the
+ *  TBI, RTBI, or SGMII PHY interface _Bit 2 in Register 49 _AN Status Register__ This
+ *  bit is cleared when you perform a read operation on the AN Status register This bit
+ *  is valid only when you select the optional TBI, RTBI, or SGMII PHY interface during
+ *  core configuration and operation
+ */
+#define EMAC_PCSLCHGIS    (BIT(1))
+#define EMAC_PCSLCHGIS_M  (EMAC_PCSLCHGIS_V << EMAC_PCSLCHGIS_S)
+#define EMAC_PCSLCHGIS_V  0x00000001U
+#define EMAC_PCSLCHGIS_S  1
+/** EMAC_PCSANCIS : RO; bitpos: [2]; default: 0;
+ *  PCS AutoNegotiation Complete This bit is set when the Autonegotiation is completed
+ *  in the TBI, RTBI, or SGMII PHY interface _Bit 5 in Register 49 _AN Status
+ *  Register__ This bit is cleared when you perform a read operation to the AN Status
+ *  register This bit is valid only when you select the optional TBI, RTBI, or SGMII
+ *  PHY interface during core configuration and operation
+ */
+#define EMAC_PCSANCIS    (BIT(2))
+#define EMAC_PCSANCIS_M  (EMAC_PCSANCIS_V << EMAC_PCSANCIS_S)
+#define EMAC_PCSANCIS_V  0x00000001U
+#define EMAC_PCSANCIS_S  2
+/** EMAC_PMTIS : RO; bitpos: [3]; default: 0;
+ *  PMT Interrupt Status This bit is set when a magic packet or remote wakeup frame is
+ *  received in the powerdown mode _see Bits 5 and 6 in the PMT Control and Status
+ *  Register_ This bit is cleared when both Bits[6:5] are cleared because of a read
+ *  operation to the PMT Control and Status register This bit is valid only when you
+ *  select the optional PMT module during core configuration
+ */
+#define EMAC_PMTIS    (BIT(3))
+#define EMAC_PMTIS_M  (EMAC_PMTIS_V << EMAC_PMTIS_S)
+#define EMAC_PMTIS_V  0x00000001U
+#define EMAC_PMTIS_S  3
+/** EMAC_MMCIS : RO; bitpos: [4]; default: 0;
+ *  MMC Interrupt Status This bit is set high when any of the Bits [7:5] is set high
+ *  and cleared only when all of these bits are low This bit is valid only when you
+ *  select the optional MMC module during core configuration
+ */
+#define EMAC_MMCIS    (BIT(4))
+#define EMAC_MMCIS_M  (EMAC_MMCIS_V << EMAC_MMCIS_S)
+#define EMAC_MMCIS_V  0x00000001U
+#define EMAC_MMCIS_S  4
+/** EMAC_MMCRXIS : RO; bitpos: [5]; default: 0;
+ *  MMC Receive Interrupt Status This bit is set high when an interrupt is generated in
+ *  the MMC Receive Interrupt Register This bit is cleared when all the bits in this
+ *  interrupt register are cleared This bit is valid only when you select the optional
+ *  MMC module during core configuration
+ */
+#define EMAC_MMCRXIS    (BIT(5))
+#define EMAC_MMCRXIS_M  (EMAC_MMCRXIS_V << EMAC_MMCRXIS_S)
+#define EMAC_MMCRXIS_V  0x00000001U
+#define EMAC_MMCRXIS_S  5
+/** EMAC_MMCTXIS : RO; bitpos: [6]; default: 0;
+ *  MMC Transmit Interrupt Status This bit is set high when an interrupt is generated
+ *  in the MMC Transmit Interrupt Register This bit is cleared when all the bits in
+ *  this interrupt register are cleared This bit is valid only when you select the
+ *  optional MMC module during core configuration
+ */
+#define EMAC_MMCTXIS    (BIT(6))
+#define EMAC_MMCTXIS_M  (EMAC_MMCTXIS_V << EMAC_MMCTXIS_S)
+#define EMAC_MMCTXIS_V  0x00000001U
+#define EMAC_MMCTXIS_S  6
+/** EMAC_MMCRXIPIS : RO; bitpos: [7]; default: 0;
+ *  MMC Receive Checksum Offload Interrupt Status This bit is set high when an
+ *  interrupt is generated in the MMC Receive Checksum Offload Interrupt Register This
+ *  bit is cleared when all the bits in this interrupt register are cleared This bit is
+ *  valid only when you select the optional MMC module and Checksum Offload Engine
+ *  _Type 2_ during core configuration
+ */
+#define EMAC_MMCRXIPIS    (BIT(7))
+#define EMAC_MMCRXIPIS_M  (EMAC_MMCRXIPIS_V << EMAC_MMCRXIPIS_S)
+#define EMAC_MMCRXIPIS_V  0x00000001U
+#define EMAC_MMCRXIPIS_S  7
+/** EMAC_TSIS : RO; bitpos: [9]; default: 0;
+ *  Timestamp Interrupt Status When the Advanced Timestamp feature is enabled, this bit
+ *  is set when R_SS_RC any of the following conditions is true: The system time value
+ *  equals or exceeds the value specified in the Target Time High and Low registers
+ *  There is an overflow in the seconds register The Auxiliary snapshot trigger is
+ *  asserted This bit is cleared on reading Bit 0 of Register 458 _Timestamp Status
+ *  Register_ If default Timestamping is enabled, when set, this bit indicates that the
+ *  system time value is equal to or exceeds the value specified in the Target Time
+ *  registers In this mode, this bit is cleared after the completion of the read of
+ *  this bit In all other modes, this bit is reserved
+ */
+#define EMAC_TSIS    (BIT(9))
+#define EMAC_TSIS_M  (EMAC_TSIS_V << EMAC_TSIS_S)
+#define EMAC_TSIS_V  0x00000001U
+#define EMAC_TSIS_S  9
+/** EMAC_LPIIS : RO; bitpos: [10]; default: 0;
+ *  LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled, this
+ *  bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver This
+ *  bit is cleared on reading Bit 0 of Register 12 _LPI Control and Status Register_ In
+ *  all other modes, this bit is reserved
+ */
+#define EMAC_LPIIS    (BIT(10))
+#define EMAC_LPIIS_M  (EMAC_LPIIS_V << EMAC_LPIIS_S)
+#define EMAC_LPIIS_V  0x00000001U
+#define EMAC_LPIIS_S  10
+/** EMAC_GPIIS : RO; bitpos: [11]; default: 0;
+ *  GPI Interrupt Status When the GPIO feature is enabled, this bit is set when any
+ *  active event _LL or LH_ occurs on the GPIS field _Bits [3:0]_ of Register 56
+ *  _General Purpose IO Register_ and the corresponding GPIE bit is enabled This bit is
+ *  cleared on reading lane 0 _GPIS_ of Register 56 _General Purpose IO Register_ When
+ *  the GPIO feature is not enabled, this bit is reserved
+ */
+#define EMAC_GPIIS    (BIT(11))
+#define EMAC_GPIIS_M  (EMAC_GPIIS_V << EMAC_GPIIS_S)
+#define EMAC_GPIIS_V  0x00000001U
+#define EMAC_GPIIS_S  11
+
+/** EMAC_INTERRUPTMASK_REG register
+ *  Contains the masks for generating the interrupts
+ */
+#define EMAC_INTERRUPTMASK_REG (DR_REG_EMAC_BASE + 0x3c)
+/** EMAC_RGSMIIIM : R/W; bitpos: [0]; default: 0;
+ *  RGMII or SMII Interrupt Mask When set, this bit disables the assertion of the
+ *  interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit
+ *  in Register 14 _Interrupt Status Register_
+ */
+#define EMAC_RGSMIIIM    (BIT(0))
+#define EMAC_RGSMIIIM_M  (EMAC_RGSMIIIM_V << EMAC_RGSMIIIM_S)
+#define EMAC_RGSMIIIM_V  0x00000001U
+#define EMAC_RGSMIIIM_S  0
+/** EMAC_PCSLCHGIM : R/W; bitpos: [1]; default: 0;
+ *  PCS Link Status Interrupt Mask When set, this bit disables the assertion of the
+ *  interrupt signal because of the setting of the PCS Linkstatus changed bit in
+ *  Register 14 _Interrupt Status Register_
+ */
+#define EMAC_PCSLCHGIM    (BIT(1))
+#define EMAC_PCSLCHGIM_M  (EMAC_PCSLCHGIM_V << EMAC_PCSLCHGIM_S)
+#define EMAC_PCSLCHGIM_V  0x00000001U
+#define EMAC_PCSLCHGIM_S  1
+/** EMAC_PCSANCIM : R/W; bitpos: [2]; default: 0;
+ *  PCS AN Completion Interrupt Mask When set, this bit disables the assertion of the
+ *  interrupt signal because of the setting of PCS Autonegotiation complete bit in
+ *  Register 14 _Interrupt Status Register_
+ */
+#define EMAC_PCSANCIM    (BIT(2))
+#define EMAC_PCSANCIM_M  (EMAC_PCSANCIM_V << EMAC_PCSANCIM_S)
+#define EMAC_PCSANCIM_V  0x00000001U
+#define EMAC_PCSANCIM_S  2
+/** EMAC_PMTIM : R/W; bitpos: [3]; default: 0;
+ *  PMT Interrupt Mask When set, this bit disables the assertion of the interrupt
+ *  signal because of the setting of PMT Interrupt Status bit in Register 14 _Interrupt
+ *  Status Register_
+ */
+#define EMAC_PMTIM    (BIT(3))
+#define EMAC_PMTIM_M  (EMAC_PMTIM_V << EMAC_PMTIM_S)
+#define EMAC_PMTIM_V  0x00000001U
+#define EMAC_PMTIM_S  3
+/** EMAC_TSIM : R/W; bitpos: [9]; default: 0;
+ *  Timestamp Interrupt Mask When set, this bit disables the assertion of the interrupt
+ *  signal because of the setting of Timestamp Interrupt Status bit in Register 14
+ *  _Interrupt Status Register_ This bit is valid only when IEEE1588 timestamping is
+ *  enabled In all other modes, this bit is reserved
+ */
+#define EMAC_TSIM    (BIT(9))
+#define EMAC_TSIM_M  (EMAC_TSIM_V << EMAC_TSIM_S)
+#define EMAC_TSIM_V  0x00000001U
+#define EMAC_TSIM_S  9
+/** EMAC_LPIIM : R/W; bitpos: [10]; default: 0;
+ *  LPI Interrupt Mask When set, this bit disables the assertion of the interrupt
+ *  signal because of the setting of the LPI Interrupt Status bit in Register 14
+ *  _Interrupt Status Register_ This bit is valid only when you select the Energy
+ *  Efficient Ethernet feature during core configuration In all other modes, this bit
+ *  is reserved
+ */
+#define EMAC_LPIIM    (BIT(10))
+#define EMAC_LPIIM_M  (EMAC_LPIIM_V << EMAC_LPIIM_S)
+#define EMAC_LPIIM_V  0x00000001U
+#define EMAC_LPIIM_S  10
+
+/** EMAC_MACADDRESS0HIGH_REG register
+ *  Contains the higher 16 bits of the first MAC address
+ */
+#define EMAC_MACADDRESS0HIGH_REG (DR_REG_EMAC_BASE + 0x40)
+/** EMAC_ADDRHI_0 : R/W; bitpos: [15:0]; default: 65535;
+ *  MAC Address0 [47:32] This field contains the upper 16 bits _47:32_ of the first
+ *  6byte MAC address The MAC uses this field for filtering the received frames and
+ *  inserting the MAC address in the Transmit Flow Control _Pause_ Frames
+ */
+#define EMAC_ADDRHI_0    0x0000FFFFU
+#define EMAC_ADDRHI_0_M  (EMAC_ADDRHI_0_V << EMAC_ADDRHI_0_S)
+#define EMAC_ADDRHI_0_V  0x0000FFFFU
+#define EMAC_ADDRHI_0_S  0
+/** EMAC_AE_0 : RO; bitpos: [31]; default: 1;
+ *  Address Enable This bit is always set to 1
+ */
+#define EMAC_AE_0    (BIT(31))
+#define EMAC_AE_0_M  (EMAC_AE_0_V << EMAC_AE_0_S)
+#define EMAC_AE_0_V  0x00000001U
+#define EMAC_AE_0_S  31
+
+/** EMAC_MACADDRESS0LOW_REG register
+ *  Contains the lower 32 bits of the first MAC address
+ */
+#define EMAC_MACADDRESS0LOW_REG (DR_REG_EMAC_BASE + 0x44)
+/** EMAC_ADDRLO_0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  MAC Address0 [31:0] This field contains the lower 32 bits of the first 6byte MAC
+ *  address This is used by the MAC for filtering the received frames and inserting the
+ *  MAC address in the Transmit Flow Control _Pause_ Frames
+ */
+#define EMAC_ADDRLO_0    0xFFFFFFFFU
+#define EMAC_ADDRLO_0_M  (EMAC_ADDRLO_0_V << EMAC_ADDRLO_0_S)
+#define EMAC_ADDRLO_0_V  0xFFFFFFFFU
+#define EMAC_ADDRLO_0_S  0
+
+/** EMAC_MACADDRESS1HIGH_REG register
+ *  Contains the higher 16 bits of the second MAC address This register is present only
+ *  when Enable MAC Address1 is selected in coreConsultant _See Table 78_
+ */
+#define EMAC_MACADDRESS1HIGH_REG (DR_REG_EMAC_BASE + 0x48)
+/** EMAC_ADDRHI_1 : R/W; bitpos: [15:0]; default: 65535;
+ *  MAC Address1 [47:32] This field contains the upper 16 bits _47:32_ of the second
+ *  6byte MAC address
+ */
+#define EMAC_ADDRHI_1    0x0000FFFFU
+#define EMAC_ADDRHI_1_M  (EMAC_ADDRHI_1_V << EMAC_ADDRHI_1_S)
+#define EMAC_ADDRHI_1_V  0x0000FFFFU
+#define EMAC_ADDRHI_1_S  0
+/** EMAC_MBC_1 : R/W; bitpos: [29:24]; default: 0;
+ *  Mask Byte Control These bits are mask control bits for comparison of each of the
+ *  MAC Address bytes When set high, the MAC does not compare the corresponding byte of
+ *  received DA or SA with the contents of MAC Address1 registers Each bit controls the
+ *  masking of the bytes as follows: Bit 29: Register 18[15:8] Bit 28: Register 18[7:0]
+ *  Bit 27: Register 19[31:24]  Bit 24: Register 19[7:0] You can filter a group of
+ *  addresses _known as group address filtering_ by masking one or more bytes of the
+ *  address
+ */
+#define EMAC_MBC_1    0x0000003FU
+#define EMAC_MBC_1_M  (EMAC_MBC_1_V << EMAC_MBC_1_S)
+#define EMAC_MBC_1_V  0x0000003FU
+#define EMAC_MBC_1_S  24
+/** EMAC_SA_1 : R/W; bitpos: [30]; default: 0;
+ *  Source Address When this bit is set, the MAC Address1[47:0] is used to compare with
+ *  the SA fields of the received frame When this bit is reset, the MAC Address1[47:0]
+ *  is used to compare with the DA fields of the received frame
+ */
+#define EMAC_SA_1    (BIT(30))
+#define EMAC_SA_1_M  (EMAC_SA_1_V << EMAC_SA_1_S)
+#define EMAC_SA_1_V  0x00000001U
+#define EMAC_SA_1_S  30
+/** EMAC_AE_1 : R/W; bitpos: [31]; default: 0;
+ *  Address Enable
+ */
+#define EMAC_AE_1    (BIT(31))
+#define EMAC_AE_1_M  (EMAC_AE_1_V << EMAC_AE_1_S)
+#define EMAC_AE_1_V  0x00000001U
+#define EMAC_AE_1_S  31
+
+/** EMAC_MACADDRESS1LOW_REG register
+ *  Contains the lower 32 bits of the second MAC address This register is present only
+ *  when Enable MAC Address1 is selected in coreConsultant _See Table 78_
+ */
+#define EMAC_MACADDRESS1LOW_REG (DR_REG_EMAC_BASE + 0x4c)
+/** EMAC_ADDRLO_1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  MAC Address1 [31:0] This field contains the lower 32 bits of the second 6byte MAC
+ *  address The content of this field is undefined until loaded by the Application
+ *  after the initialization process
+ */
+#define EMAC_ADDRLO_1    0xFFFFFFFFU
+#define EMAC_ADDRLO_1_M  (EMAC_ADDRLO_1_V << EMAC_ADDRLO_1_S)
+#define EMAC_ADDRLO_1_V  0xFFFFFFFFU
+#define EMAC_ADDRLO_1_S  0
+
+/** EMAC_MACADDRESS2HIGH_REG register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS2HIGH_REG (DR_REG_EMAC_BASE + 0x50)
+/** EMAC_ADDRHI_2 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address2 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRHI_2    0x0000FFFFU
+#define EMAC_ADDRHI_2_M  (EMAC_ADDRHI_2_V << EMAC_ADDRHI_2_S)
+#define EMAC_ADDRHI_2_V  0x0000FFFFU
+#define EMAC_ADDRHI_2_S  0
+/** EMAC_MBC_2 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address2 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_MBC_2    0x0000003FU
+#define EMAC_MBC_2_M  (EMAC_MBC_2_V << EMAC_MBC_2_S)
+#define EMAC_MBC_2_V  0x0000003FU
+#define EMAC_MBC_2_S  24
+/** EMAC_SA_2 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address2 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_SA_2    (BIT(30))
+#define EMAC_SA_2_M  (EMAC_SA_2_V << EMAC_SA_2_S)
+#define EMAC_SA_2_V  0x00000001U
+#define EMAC_SA_2_S  30
+/** EMAC_AE_2 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address2 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_AE_2    (BIT(31))
+#define EMAC_AE_2_M  (EMAC_AE_2_V << EMAC_AE_2_S)
+#define EMAC_AE_2_V  0x00000001U
+#define EMAC_AE_2_S  31
+
+/** EMAC_MACADDRESS2LOW_REG register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS2LOW_REG (DR_REG_EMAC_BASE + 0x54)
+/** EMAC_ADDRLO_2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address2 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRLO_2    0xFFFFFFFFU
+#define EMAC_ADDRLO_2_M  (EMAC_ADDRLO_2_V << EMAC_ADDRLO_2_S)
+#define EMAC_ADDRLO_2_V  0xFFFFFFFFU
+#define EMAC_ADDRLO_2_S  0
+
+/** EMAC_MACADDRESS3HIGH_REG
+ *  register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS3HIGH_REG (DR_REG_EMAC_BASE + 0x58)
+/** EMAC_ADDRHI_3 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address3 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRHI_3    0x0000FFFFU
+#define EMAC_ADDRHI_3_M  (EMAC_ADDRHI_3_V << EMAC_ADDRHI_3_S)
+#define EMAC_ADDRHI_3_V  0x0000FFFFU
+#define EMAC_ADDRHI_3_S  0
+/** EMAC_MBC_3 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address3 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_MBC_3    0x0000003FU
+#define EMAC_MBC_3_M  (EMAC_MBC_3_V << EMAC_MBC_3_S)
+#define EMAC_MBC_3_V  0x0000003FU
+#define EMAC_MBC_3_S  24
+/** EMAC_SA_3 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address3 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_SA_3    (BIT(30))
+#define EMAC_SA_3_M  (EMAC_SA_3_V << EMAC_SA_3_S)
+#define EMAC_SA_3_V  0x00000001U
+#define EMAC_SA_3_S  30
+/** EMAC_AE_3 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address3 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_AE_3    (BIT(31))
+#define EMAC_AE_3_M  (EMAC_AE_3_V << EMAC_AE_3_S)
+#define EMAC_AE_3_V  0x00000001U
+#define EMAC_AE_3_S  31
+
+/** EMAC_MACADDRESS3LOW_REG register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS3LOW_REG (DR_REG_EMAC_BASE + 0x5c)
+/** EMAC_ADDRLO_3 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address3 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRLO_3    0xFFFFFFFFU
+#define EMAC_ADDRLO_3_M  (EMAC_ADDRLO_3_V << EMAC_ADDRLO_3_S)
+#define EMAC_ADDRLO_3_V  0xFFFFFFFFU
+#define EMAC_ADDRLO_3_S  0
+
+/** EMAC_MACADDRESS4HIGH_REG register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS4HIGH_REG (DR_REG_EMAC_BASE + 0x60)
+/** EMAC_ADDRHI_4 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address4 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRHI_4    0x0000FFFFU
+#define EMAC_ADDRHI_4_M  (EMAC_ADDRHI_4_V << EMAC_ADDRHI_4_S)
+#define EMAC_ADDRHI_4_V  0x0000FFFFU
+#define EMAC_ADDRHI_4_S  0
+/** EMAC_MBC_4 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address4 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_MBC_4    0x0000003FU
+#define EMAC_MBC_4_M  (EMAC_MBC_4_V << EMAC_MBC_4_S)
+#define EMAC_MBC_4_V  0x0000003FU
+#define EMAC_MBC_4_S  24
+/** EMAC_SA_4 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address4 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_SA_4    (BIT(30))
+#define EMAC_SA_4_M  (EMAC_SA_4_V << EMAC_SA_4_S)
+#define EMAC_SA_4_V  0x00000001U
+#define EMAC_SA_4_S  30
+/** EMAC_AE_4 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address4 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_AE_4    (BIT(31))
+#define EMAC_AE_4_M  (EMAC_AE_4_V << EMAC_AE_4_S)
+#define EMAC_AE_4_V  0x00000001U
+#define EMAC_AE_4_S  31
+
+/** EMAC_MACADDRESS4LOW_REG register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS4LOW_REG (DR_REG_EMAC_BASE + 0x64)
+/** EMAC_ADDRLO_4 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address4 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRLO_4    0xFFFFFFFFU
+#define EMAC_ADDRLO_4_M  (EMAC_ADDRLO_4_V << EMAC_ADDRLO_4_S)
+#define EMAC_ADDRLO_4_V  0xFFFFFFFFU
+#define EMAC_ADDRLO_4_S  0
+
+/** EMAC_MACADDRESS5HIGH_REG register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS5HIGH_REG (DR_REG_EMAC_BASE + 0x68)
+/** EMAC_ADDRHI_5 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address5 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRHI_5    0x0000FFFFU
+#define EMAC_ADDRHI_5_M  (EMAC_ADDRHI_5_V << EMAC_ADDRHI_5_S)
+#define EMAC_ADDRHI_5_V  0x0000FFFFU
+#define EMAC_ADDRHI_5_S  0
+/** EMAC_MBC_5 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address5 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_MBC_5    0x0000003FU
+#define EMAC_MBC_5_M  (EMAC_MBC_5_V << EMAC_MBC_5_S)
+#define EMAC_MBC_5_V  0x0000003FU
+#define EMAC_MBC_5_S  24
+/** EMAC_SA_5 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address5 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_SA_5    (BIT(30))
+#define EMAC_SA_5_M  (EMAC_SA_5_V << EMAC_SA_5_S)
+#define EMAC_SA_5_V  0x00000001U
+#define EMAC_SA_5_S  30
+/** EMAC_AE_5 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address5 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_AE_5    (BIT(31))
+#define EMAC_AE_5_M  (EMAC_AE_5_V << EMAC_AE_5_S)
+#define EMAC_AE_5_V  0x00000001U
+#define EMAC_AE_5_S  31
+
+/** EMAC_MACADDRESS5LOW_REG register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS5LOW_REG (DR_REG_EMAC_BASE + 0x6c)
+/** EMAC_ADDRLO_5 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address5 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRLO_5    0xFFFFFFFFU
+#define EMAC_ADDRLO_5_M  (EMAC_ADDRLO_5_V << EMAC_ADDRLO_5_S)
+#define EMAC_ADDRLO_5_V  0xFFFFFFFFU
+#define EMAC_ADDRLO_5_S  0
+
+/** EMAC_MACADDRESS6HIGH_REG
+ *  register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS6HIGH_REG (DR_REG_EMAC_BASE + 0x70)
+/** EMAC_ADDRHI_6 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address6 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRHI_6    0x0000FFFFU
+#define EMAC_ADDRHI_6_M  (EMAC_ADDRHI_6_V << EMAC_ADDRHI_6_S)
+#define EMAC_ADDRHI_6_V  0x0000FFFFU
+#define EMAC_ADDRHI_6_S  0
+/** EMAC_MBC_6 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address6 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_MBC_6    0x0000003FU
+#define EMAC_MBC_6_M  (EMAC_MBC_6_V << EMAC_MBC_6_S)
+#define EMAC_MBC_6_V  0x0000003FU
+#define EMAC_MBC_6_S  24
+/** EMAC_SA_6 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address6 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_SA_6    (BIT(30))
+#define EMAC_SA_6_M  (EMAC_SA_6_V << EMAC_SA_6_S)
+#define EMAC_SA_6_V  0x00000001U
+#define EMAC_SA_6_S  30
+/** EMAC_AE_6 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address6 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_AE_6    (BIT(31))
+#define EMAC_AE_6_M  (EMAC_AE_6_V << EMAC_AE_6_S)
+#define EMAC_AE_6_V  0x00000001U
+#define EMAC_AE_6_S  31
+
+/** EMAC_MACADDRESS6LOW_REG register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS6LOW_REG (DR_REG_EMAC_BASE + 0x74)
+/** EMAC_ADDRLO_6 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address6 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRLO_6    0xFFFFFFFFU
+#define EMAC_ADDRLO_6_M  (EMAC_ADDRLO_6_V << EMAC_ADDRLO_6_S)
+#define EMAC_ADDRLO_6_V  0xFFFFFFFFU
+#define EMAC_ADDRLO_6_S  0
+
+/** EMAC_MACADDRESS7HIGH_REG
+ *  register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS7HIGH_REG (DR_REG_EMAC_BASE + 0x78)
+/** EMAC_ADDRHI_7 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address7 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRHI_7    0x0000FFFFU
+#define EMAC_ADDRHI_7_M  (EMAC_ADDRHI_7_V << EMAC_ADDRHI_7_S)
+#define EMAC_ADDRHI_7_V  0x0000FFFFU
+#define EMAC_ADDRHI_7_S  0
+/** EMAC_MBC_7 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address7 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_MBC_7    0x0000003FU
+#define EMAC_MBC_7_M  (EMAC_MBC_7_V << EMAC_MBC_7_S)
+#define EMAC_MBC_7_V  0x0000003FU
+#define EMAC_MBC_7_S  24
+/** EMAC_SA_7 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address7 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_SA_7    (BIT(30))
+#define EMAC_SA_7_M  (EMAC_SA_7_V << EMAC_SA_7_S)
+#define EMAC_SA_7_V  0x00000001U
+#define EMAC_SA_7_S  30
+/** EMAC_AE_7 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address7 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_AE_7    (BIT(31))
+#define EMAC_AE_7_M  (EMAC_AE_7_V << EMAC_AE_7_S)
+#define EMAC_AE_7_V  0x00000001U
+#define EMAC_AE_7_S  31
+
+/** EMAC_MACADDRESS7LOW_REG register
+ *  Reserved
+ */
+#define EMAC_MACADDRESS7LOW_REG (DR_REG_EMAC_BASE + 0x7c)
+/** EMAC_ADDRLO_7 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address7 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define EMAC_ADDRLO_7    0xFFFFFFFFU
+#define EMAC_ADDRLO_7_M  (EMAC_ADDRLO_7_V << EMAC_ADDRLO_7_S)
+#define EMAC_ADDRLO_7_V  0xFFFFFFFFU
+#define EMAC_ADDRLO_7_S  0
+
+/** EMAC_ANCONTROL_REG register
+ *  Enables and/or restarts autonegotiation This register also enables the Physical
+ *  Coding Sublayer _PCS_ loopback This register is present only when you select the
+ *  TBI, RTBI, or SGMII interface in coreConsultant
+ */
+#define EMAC_ANCONTROL_REG (DR_REG_EMAC_BASE + 0xc0)
+/** EMAC_RAN : R/W1S; bitpos: [9]; default: 0;
+ *  Restart AutoNegotiation When set, this bit causes autonegotiation to restart if Bit
+ *  12 _ANE_ is set This bit is selfclearing after autonegotiation starts This bit
+ *  should be cleared for normal operation
+ */
+#define EMAC_RAN    (BIT(9))
+#define EMAC_RAN_M  (EMAC_RAN_V << EMAC_RAN_S)
+#define EMAC_RAN_V  0x00000001U
+#define EMAC_RAN_S  9
+/** EMAC_ANE : R/W; bitpos: [12]; default: 0;
+ *  AutoNegotiation Enable When set, this bit enables the MAC to perform
+ *  autonegotiation with the link partner Clearing this bit disables the autonegotiation
+ */
+#define EMAC_ANE    (BIT(12))
+#define EMAC_ANE_M  (EMAC_ANE_V << EMAC_ANE_S)
+#define EMAC_ANE_V  0x00000001U
+#define EMAC_ANE_S  12
+/** EMAC_ELE : R/W; bitpos: [14]; default: 0;
+ *  External Loopback Enable When set, this bit causes the PHY to loopback the transmit
+ *  data into the receive path The pcs_ewrap_o signal is asserted high when this bit is
+ *  set
+ */
+#define EMAC_ELE    (BIT(14))
+#define EMAC_ELE_M  (EMAC_ELE_V << EMAC_ELE_S)
+#define EMAC_ELE_V  0x00000001U
+#define EMAC_ELE_S  14
+/** EMAC_ECD : R/W; bitpos: [16]; default: 0;
+ *  Enable Comma Detect When set, this bit enables the PHY for comma detection and word
+ *  resynchronization This bit controls the pcs_en_cdet_o signal on the TBI, RTBI, or
+ *  SGMII interface
+ */
+#define EMAC_ECD    (BIT(16))
+#define EMAC_ECD_M  (EMAC_ECD_V << EMAC_ECD_S)
+#define EMAC_ECD_V  0x00000001U
+#define EMAC_ECD_S  16
+/** EMAC_LR : R/W; bitpos: [17]; default: 0;
+ *  Lock to Reference When set, this bit enables the PHY to lock its PLL to the 125 MHz
+ *  reference clock This bit controls the pcs_lck_ref_o signal on the TBI, RTBI, or
+ *  SGMII interface
+ */
+#define EMAC_LR    (BIT(17))
+#define EMAC_LR_M  (EMAC_LR_V << EMAC_LR_S)
+#define EMAC_LR_V  0x00000001U
+#define EMAC_LR_S  17
+/** EMAC_SGMRAL : R/W; bitpos: [18]; default: 0;
+ *  SGMII RAL Control When set, this bit forces the SGMII RAL block to operate in the
+ *  speed configured in the Speed and Port Select bits of the MAC Configuration
+ *  register This is useful when the SGMII interface is used in a direct MAC to MAC
+ *  connection _without a PHY_ and any MAC must reconfigure the speed When reset, the
+ *  SGMII RAL block operates according to the link speed status received on SGMII _from
+ *  the PHY_ This bit is reserved _and RO_ if the SGMII PHY interface is not selected
+ *  during core configuration
+ */
+#define EMAC_SGMRAL    (BIT(18))
+#define EMAC_SGMRAL_M  (EMAC_SGMRAL_V << EMAC_SGMRAL_S)
+#define EMAC_SGMRAL_V  0x00000001U
+#define EMAC_SGMRAL_S  18
+
+/** EMAC_ANSTATUS_REG register
+ *  Indicates the link and autonegotiation status This register is present only when
+ *  you select the TBI, RTBI, or SGMII interface in coreConsultant
+ */
+#define EMAC_ANSTATUS_REG (DR_REG_EMAC_BASE + 0xc4)
+/** EMAC_LS : RO; bitpos: [2]; default: 0;
+ *  Link Status This bit indicates whether the data channel _link_ is up or down For
+ *  the TBI, RTBI or SGMII interfaces, if ANEG is going on, data cannot be transferred
+ *  across the link and hence the link is given as down
+ */
+#define EMAC_LS    (BIT(2))
+#define EMAC_LS_M  (EMAC_LS_V << EMAC_LS_S)
+#define EMAC_LS_V  0x00000001U
+#define EMAC_LS_S  2
+/** EMAC_ANA : RO; bitpos: [3]; default: 1;
+ *  AutoNegotiation Ability This bit is always high because the MAC supports auto
+ *  negotiation
+ */
+#define EMAC_ANA    (BIT(3))
+#define EMAC_ANA_M  (EMAC_ANA_V << EMAC_ANA_S)
+#define EMAC_ANA_V  0x00000001U
+#define EMAC_ANA_S  3
+/** EMAC_ANC : RO; bitpos: [5]; default: 0;
+ *  AutoNegotiation Complete When set, this bit indicates that the autonegotiation
+ *  process is complete This bit is cleared when autonegotiation is reinitiated
+ */
+#define EMAC_ANC    (BIT(5))
+#define EMAC_ANC_M  (EMAC_ANC_V << EMAC_ANC_S)
+#define EMAC_ANC_V  0x00000001U
+#define EMAC_ANC_S  5
+/** EMAC_ES : RO; bitpos: [8]; default: 1;
+ *  Extended Status This bit is tied to high if the TBI or RTBI interface is selected
+ *  during core configuration indicating that the MAC supports extended status
+ *  information in Register 53 _TBI Extended  Status Register_ This bit is tied to low
+ *  if the SGMII interface is selected and the TBI or RTBI interface is not selected
+ *  during core configuration indicating that Register 53 is not present
+ */
+#define EMAC_ES    (BIT(8))
+#define EMAC_ES_M  (EMAC_ES_V << EMAC_ES_S)
+#define EMAC_ES_V  0x00000001U
+#define EMAC_ES_S  8
+
+/** EMAC_AUTONEGOTIATIONADVERTISEMENT_REG register
+ *  This register is configured before autonegotiation begins It contains the
+ *  advertised ability of the MAC This register is present only when you select the TBI
+ *  or RTBI interface in coreConsultant
+ */
+#define EMAC_AUTONEGOTIATIONADVERTISEMENT_REG (DR_REG_EMAC_BASE + 0xc8)
+/** EMAC_FD : R/W; bitpos: [5]; default: 1;
+ *  FullDuplex When set high, this bit indicates that the MAC supports the fullduplex
+ *  mode
+ */
+#define EMAC_FD    (BIT(5))
+#define EMAC_FD_M  (EMAC_FD_V << EMAC_FD_S)
+#define EMAC_FD_V  0x00000001U
+#define EMAC_FD_S  5
+/** EMAC_HD : R/W; bitpos: [6]; default: 1;
+ *  HalfDuplex When set high, this bit indicates that the MAC supports the halfduplex
+ *  mode This bit is always low _and RO_ when the MAC is configured for the
+ *  fullduplexonly mode
+ */
+#define EMAC_HD    (BIT(6))
+#define EMAC_HD_M  (EMAC_HD_V << EMAC_HD_S)
+#define EMAC_HD_V  0x00000001U
+#define EMAC_HD_S  6
+/** EMAC_PSE : R/W; bitpos: [8:7]; default: 3;
+ *  Pause Encoding These bits provide an encoding for the Pause bits, indicating that
+ *  the MAC is capable of configuring the Pause function as defined in IEEE 8023x The
+ *  encoding of these bits is defined in IEEE 8023z, Section 37214
+ */
+#define EMAC_PSE    0x00000003U
+#define EMAC_PSE_M  (EMAC_PSE_V << EMAC_PSE_S)
+#define EMAC_PSE_V  0x00000003U
+#define EMAC_PSE_S  7
+/** EMAC_RFE : R/W; bitpos: [13:12]; default: 0;
+ *  Remote Fault Encoding These bits provide a remote fault encoding, indicating to a
+ *  link partner that a fault or error condition has occurred The encoding of these
+ *  bits is defined in IEEE 8023z, Section 37215
+ */
+#define EMAC_RFE    0x00000003U
+#define EMAC_RFE_M  (EMAC_RFE_V << EMAC_RFE_S)
+#define EMAC_RFE_V  0x00000003U
+#define EMAC_RFE_S  12
+/** EMAC_NP : RO; bitpos: [15]; default: 0;
+ *  Next Page Support This bit is always low because the MAC does not support the next
+ *  page
+ */
+#define EMAC_NP    (BIT(15))
+#define EMAC_NP_M  (EMAC_NP_V << EMAC_NP_S)
+#define EMAC_NP_V  0x00000001U
+#define EMAC_NP_S  15
+
+/** EMAC_AUTONEGOTIATIONLINKPARTNERABILITY_REG register
+ *  Contains the advertised ability of the link partner Its value is valid after
+ *  successful completion of autonegotiation or when a new base page has been received
+ *  _indicated in the AutoNegotiation Expansion Register_ This register is present only
+ *  when you select the TBI or RTBI interface in coreConsultant
+ */
+#define EMAC_AUTONEGOTIATIONLINKPARTNERABILITY_REG (DR_REG_EMAC_BASE + 0xcc)
+/** EMAC_FD_ABILITY : RO; bitpos: [5]; default: 0;
+ *  FullDuplex When set, this bit indicates that the link partner has the ability to
+ *  operate in the full duplex mode When cleared, this bit indicates that the link
+ *  partner does not have the ability to operate in the fullduplex mode
+ */
+#define EMAC_FD_ABILITY    (BIT(5))
+#define EMAC_FD_ABILITY_M  (EMAC_FD_ABILITY_V << EMAC_FD_ABILITY_S)
+#define EMAC_FD_ABILITY_V  0x00000001U
+#define EMAC_FD_ABILITY_S  5
+/** EMAC_HD_ABILITY : RO; bitpos: [6]; default: 0;
+ *  HalfDuplex When set, this bit indicates that the link partner has the ability to
+ *  operate in the halfduplex mode When cleared, this bit indicates that the link
+ *  partner does not have the ability to operate in the halfduplex mode
+ */
+#define EMAC_HD_ABILITY    (BIT(6))
+#define EMAC_HD_ABILITY_M  (EMAC_HD_ABILITY_V << EMAC_HD_ABILITY_S)
+#define EMAC_HD_ABILITY_V  0x00000001U
+#define EMAC_HD_ABILITY_S  6
+/** EMAC_PSE_ABILITY : RO; bitpos: [8:7]; default: 0;
+ *  Pause Encoding These bits provide an encoding for the Pause bits, indicating that
+ *  the link partner's capability of configuring the Pause function as defined in the
+ *  IEEE 8023x specification The encoding of these bits is defined in IEEE 8023z,
+ *  Section 37214
+ */
+#define EMAC_PSE_ABILITY    0x00000003U
+#define EMAC_PSE_ABILITY_M  (EMAC_PSE_ABILITY_V << EMAC_PSE_ABILITY_S)
+#define EMAC_PSE_ABILITY_V  0x00000003U
+#define EMAC_PSE_ABILITY_S  7
+/** EMAC_RFE_ABILITY : RO; bitpos: [13:12]; default: 0;
+ *  Remote Fault Encoding These bits provide a remote fault encoding, indicating a
+ *  fault or error condition of the link partner The encoding of these bits is defined
+ *  in IEEE 8023z, Section 37215
+ */
+#define EMAC_RFE_ABILITY    0x00000003U
+#define EMAC_RFE_ABILITY_M  (EMAC_RFE_ABILITY_V << EMAC_RFE_ABILITY_S)
+#define EMAC_RFE_ABILITY_V  0x00000003U
+#define EMAC_RFE_ABILITY_S  12
+/** EMAC_ACK : RO; bitpos: [14]; default: 0;
+ *  Acknowledge When set, the autonegotiation function uses this bit to indicate that
+ *  the link partner has successfully received the base page of the MAC When cleared,
+ *  it indicates that the link partner did not successfully receive the base page of
+ *  the MAC
+ */
+#define EMAC_ACK    (BIT(14))
+#define EMAC_ACK_M  (EMAC_ACK_V << EMAC_ACK_S)
+#define EMAC_ACK_V  0x00000001U
+#define EMAC_ACK_S  14
+/** EMAC_NO : RO; bitpos: [15]; default: 0;
+ *  Next Page Support When set, this bit indicates that more next page information is
+ *  available When cleared, this bit indicates that next page exchange is not desired
+ */
+#define EMAC_NO    (BIT(15))
+#define EMAC_NO_M  (EMAC_NO_V << EMAC_NO_S)
+#define EMAC_NO_V  0x00000001U
+#define EMAC_NO_S  15
+
+/** EMAC_AUTONEGOTIATIONEXPANSION_REG register
+ *  Indicates whether a new base page has been received from the link partner This
+ *  register is present only when you select the TBI or RTBI interface in coreConsultant
+ */
+#define EMAC_AUTONEGOTIATIONEXPANSION_REG (DR_REG_EMAC_BASE + 0xd0)
+/** EMAC_NPR : RO; bitpos: [1]; default: 0;
+ *  New Page Received When set, this bit indicates that the MAC has received a new page
+ *  This bit is cleared when read
+ */
+#define EMAC_NPR    (BIT(1))
+#define EMAC_NPR_M  (EMAC_NPR_V << EMAC_NPR_S)
+#define EMAC_NPR_V  0x00000001U
+#define EMAC_NPR_S  1
+/** EMAC_NPA : RO; bitpos: [2]; default: 0;
+ *  Next Page Ability This bit is always low because the MAC does not support the next
+ *  page function
+ */
+#define EMAC_NPA    (BIT(2))
+#define EMAC_NPA_M  (EMAC_NPA_V << EMAC_NPA_S)
+#define EMAC_NPA_V  0x00000001U
+#define EMAC_NPA_S  2
+
+/** EMAC_TBIEXTENDEDSTATUS_REG register
+ *  Indicates all modes of operation of the MAC This register is present only when you
+ *  select the TBI or RTBI interface in coreConsultant
+ */
+#define EMAC_TBIEXTENDEDSTATUS_REG (DR_REG_EMAC_BASE + 0xd4)
+/** EMAC_GHD : RO; bitpos: [14]; default: 1;
+ *  1000BASEX HalfDuplex Capable This bit indicates that the MAC is able to perform the
+ *  halfduplex and 1000BASEX operations This bit is always low when the MAC is
+ *  configured for the fullduplexonly operation during core configuration
+ */
+#define EMAC_GHD    (BIT(14))
+#define EMAC_GHD_M  (EMAC_GHD_V << EMAC_GHD_S)
+#define EMAC_GHD_V  0x00000001U
+#define EMAC_GHD_S  14
+/** EMAC_GFD : RO; bitpos: [15]; default: 1;
+ *  1000BASEX FullDuplex Capable This bit indicates that the MAC is able to perform the
+ *  fullduplex and 1000BASEX operations
+ */
+#define EMAC_GFD    (BIT(15))
+#define EMAC_GFD_M  (EMAC_GFD_V << EMAC_GFD_S)
+#define EMAC_GFD_V  0x00000001U
+#define EMAC_GFD_S  15
+
+/** EMAC_SGMII_RGMII_SMIICONTROLANDSTATUS_REG register
+ *  Indicates the status signals received from the PHY through the SGMII, RGMII, or
+ *  SMII interface This register is present only when you select the SGMII, RGMII, or
+ *  SMII interface in coreConsultant
+ */
+#define EMAC_SGMII_RGMII_SMIICONTROLANDSTATUS_REG (DR_REG_EMAC_BASE + 0xd8)
+/** EMAC_LNKMOD : RO; bitpos: [0]; default: 0;
+ *  Link Mode This bit indicates the current mode of operation of the link: 1’b0:
+ *  Halfduplex mode 1’b1: Fullduplex mode
+ */
+#define EMAC_LNKMOD    (BIT(0))
+#define EMAC_LNKMOD_M  (EMAC_LNKMOD_V << EMAC_LNKMOD_S)
+#define EMAC_LNKMOD_V  0x00000001U
+#define EMAC_LNKMOD_S  0
+/** EMAC_LNKSPEED : RO; bitpos: [2:1]; default: 2;
+ *  Link Speed
+ */
+#define EMAC_LNKSPEED    0x00000003U
+#define EMAC_LNKSPEED_M  (EMAC_LNKSPEED_V << EMAC_LNKSPEED_S)
+#define EMAC_LNKSPEED_V  0x00000003U
+#define EMAC_LNKSPEED_S  1
+/** EMAC_LNKSTS : RO; bitpos: [3]; default: 0;
+ *  Link Status This bit indicates whether the link between the local PHY and the
+ *  remote PHY is up or down It gives the status of the link between the SGMII of MAC
+ *  and the SGMII of the local PHY The status bits are received from the local PHY
+ *  during ANEG between he MAC and PHY on the SGMII link
+ */
+#define EMAC_LNKSTS    (BIT(3))
+#define EMAC_LNKSTS_M  (EMAC_LNKSTS_V << EMAC_LNKSTS_S)
+#define EMAC_LNKSTS_V  0x00000001U
+#define EMAC_LNKSTS_S  3
+/** EMAC_JABTO : RO; bitpos: [4]; default: 0;
+ *  Jabber Timeout This bit indicates whether there is jabber timeout error _1'b1_ in
+ *  the received frame This bit is reserved when the MAC is configured for the SGMII or
+ *  RGMII PHY interface
+ */
+#define EMAC_JABTO    (BIT(4))
+#define EMAC_JABTO_M  (EMAC_JABTO_V << EMAC_JABTO_S)
+#define EMAC_JABTO_V  0x00000001U
+#define EMAC_JABTO_S  4
+/** EMAC_FALSCARDET : RO; bitpos: [5]; default: 0;
+ *  False Carrier Detected This bit indicates whether the SMII PHY detected false
+ *  carrier _1'b1_ This bit is reserved when the MAC is configured for the SGMII or
+ *  RGMII PHY interface
+ */
+#define EMAC_FALSCARDET    (BIT(5))
+#define EMAC_FALSCARDET_M  (EMAC_FALSCARDET_V << EMAC_FALSCARDET_S)
+#define EMAC_FALSCARDET_V  0x00000001U
+#define EMAC_FALSCARDET_S  5
+/** EMAC_SMIDRXS : R/W; bitpos: [16]; default: 0;
+ *  Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the
+ *  first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal When
+ *  reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal
+ *  If the SMII PHY Interface with source synchronous mode is selected during core
+ *  configuration, this bit is reserved _RO with default value_
+ */
+#define EMAC_SMIDRXS    (BIT(16))
+#define EMAC_SMIDRXS_M  (EMAC_SMIDRXS_V << EMAC_SMIDRXS_S)
+#define EMAC_SMIDRXS_V  0x00000001U
+#define EMAC_SMIDRXS_S  16
+
+/** EMAC_WATCHDOGTIMEOUT_REG register
+ *  Controls the watchdog timeout for received frames
+ */
+#define EMAC_WATCHDOGTIMEOUT_REG (DR_REG_EMAC_BASE + 0xdc)
+/** EMAC_WTO : R/W; bitpos: [13:0]; default: 0;
+ *  Watchdog Timeout When Bit 16 _PWE_ is set and Bit 23 _WD_ of Register 0 _MAC
+ *  Configuration Register_ is reset, this field is used as watchdog timeout for a
+ *  received frame If the length of a received frame exceeds the value of this field,
+ *  such frame is terminated and declared as an error frame Note: When Bit 16 _PWE_ is
+ *  set, the value in this field should be more than 1,522 _0x05F2_ Otherwise, the IEEE
+ *  Std 8023specified valid tagged frames are declared as error frames and are dropped
+ */
+#define EMAC_WTO    0x00003FFFU
+#define EMAC_WTO_M  (EMAC_WTO_V << EMAC_WTO_S)
+#define EMAC_WTO_V  0x00003FFFU
+#define EMAC_WTO_S  0
+/** EMAC_PWE : R/W; bitpos: [16]; default: 0;
+ *  Programmable Watchdog Enable When this bit is set and Bit 23 _WD_ of Register 0
+ *  _MAC Configuration Register_ is reset, the WTO field _Bits[13:0]_ is used as
+ *  watchdog timeout for a received frame When this bit is cleared, the watchdog
+ *  timeout for a received frame is controlled by the setting of Bit 23 _WD_ and Bit 20
+ *  _JE_ in Register 0 _MAC Configuration Register_
+ */
+#define EMAC_PWE    (BIT(16))
+#define EMAC_PWE_M  (EMAC_PWE_V << EMAC_PWE_S)
+#define EMAC_PWE_V  0x00000001U
+#define EMAC_PWE_S  16
+
+/** EMAC_GENERALPURPOSEIO_REG register
+ *  Provides the control to drive up to 4 bits of output ports _GPO_ and also provides
+ *  the status of up to 4 input ports _GPIS_
+ */
+#define EMAC_GENERALPURPOSEIO_REG (DR_REG_EMAC_BASE + 0xe0)
+/** EMAC_GPIS : R/W; bitpos: [3:0]; default: 0;
+ *  General Purpose Input Status This field gives the status of the signals connected
+ *  to the gpi_i input ports This field is of the following types based on the setting
+ *  of the corresponding GPIT field of this register: Latchedlow _LL_: This field is
+ *  cleared when the corresponding gpi_i input becomes low This field remains low until
+ *  the host reads this field After this, this field reflects the current value of the
+ *  gpi_i input Latchedhigh _LH_: This field is set when the corresponding gpi_i input
+ *  becomes high This field remains high until the host reads this field After this,
+ *  this field reflects the current value of the gpi_i input The number of bits
+ *  available in this field depend on the GP Input Signal Width option Other bits are
+ *  not used _reserved and always reset_
+ */
+#define EMAC_GPIS    0x0000000FU
+#define EMAC_GPIS_M  (EMAC_GPIS_V << EMAC_GPIS_S)
+#define EMAC_GPIS_V  0x0000000FU
+#define EMAC_GPIS_S  0
+/** EMAC_GPO : R/W; bitpos: [11:8]; default: 0;
+ *  General Purpose Output When this bit is set, it directly drives the gpo_o output
+ *  ports When this bit is reset, it does not directly drive the gpo_o output ports The
+ *  number of bits available in this field depend on the GP Output Signal Width option
+ *  Other bits are not used _reserved and always reset_
+ */
+#define EMAC_GPO    0x0000000FU
+#define EMAC_GPO_M  (EMAC_GPO_V << EMAC_GPO_S)
+#define EMAC_GPO_V  0x0000000FU
+#define EMAC_GPO_S  8
+/** EMAC_GPIE : R/W; bitpos: [19:16]; default: 0;
+ *  GPI Interrupt Enable When this bit is set and the programmed event _LL or LH_
+ *  occurs on the corresponding GPIS bit, Bit 11 _GPIIS_ of Register 14 _Interrupt
+ *  Status Register_ is set Accordingly, the interrupt is generated on the mci_intr_o
+ *  or sbd_intr_o The GPIIS bit is cleared when the host reads the Bits[7:0] of this
+ *  register When reset, Bit 11 _GPIIS_ of Register 14 _Interrupt Status Register_ is
+ *  not set when any event occurs on the corresponding GPIS bits The number of bits
+ *  available in this field depend on the GP Input Signal Width option Other bits are
+ *  not used _reserved and always reset_
+ */
+#define EMAC_GPIE    0x0000000FU
+#define EMAC_GPIE_M  (EMAC_GPIE_V << EMAC_GPIE_S)
+#define EMAC_GPIE_V  0x0000000FU
+#define EMAC_GPIE_S  16
+/** EMAC_GPIT : R/W; bitpos: [27:24]; default: 0;
+ *  GPI Type When set, this bit indicates that the corresponding GPIS is of latchedlow
+ *  _LL_ type When reset, this bit indicates that the corresponding GPIS is of
+ *  latchedhigh _LH_ type The number of bits available in this field depend on the GP
+ *  Input Signal Width option Other bits are not used _reserved and always reset_
+ */
+#define EMAC_GPIT    0x0000000FU
+#define EMAC_GPIT_M  (EMAC_GPIT_V << EMAC_GPIT_S)
+#define EMAC_GPIT_V  0x0000000FU
+#define EMAC_GPIT_S  24
+
+/** EMAC_LAYER3ANDLAYER4CONTROLREGISTER0_REG register
+ *  Controls the operations of the Layer 3 and Layer 4 frame filtering
+ */
+#define EMAC_LAYER3ANDLAYER4CONTROLREGISTER0_REG (DR_REG_EMAC_BASE + 0x400)
+/** EMAC_L3PEN0 : R/W; bitpos: [0]; default: 0;
+ *  Layer 3 Protocol Enable When set, this bit indicates that the Layer 3 IP Source or
+ *  Destination Address matching is enabled for the IPv6 frames When reset, this bit
+ *  indicates that the Layer 3 IP Source or Destination Address matching is enabled for
+ *  the IPv4 frames The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit
+ *  is set high
+ */
+#define EMAC_L3PEN0    (BIT(0))
+#define EMAC_L3PEN0_M  (EMAC_L3PEN0_V << EMAC_L3PEN0_S)
+#define EMAC_L3PEN0_V  0x00000001U
+#define EMAC_L3PEN0_S  0
+/** EMAC_L3SAM0 : R/W; bitpos: [2]; default: 0;
+ *  Layer 3 IP SA Match Enable When set, this bit indicates that the Layer 3 IP Source
+ *  Address field is enabled for matching When reset, the MAC ignores the Layer 3 IP
+ *  Source Address field for matching Note: When Bit 0 _L3PEN0_ is set, you should set
+ *  either this bit or Bit 4 _L3DAM0_ because either IPv6 SA or DA can be checked for
+ *  filtering
+ */
+#define EMAC_L3SAM0    (BIT(2))
+#define EMAC_L3SAM0_M  (EMAC_L3SAM0_V << EMAC_L3SAM0_S)
+#define EMAC_L3SAM0_V  0x00000001U
+#define EMAC_L3SAM0_S  2
+/** EMAC_L3SAIM0 : R/W; bitpos: [3]; default: 0;
+ *  Layer 3 IP SA Inverse Match Enable When set, this bit indicates that the Layer 3 IP
+ *  Source Address field is enabled for inverse matching When reset, this bit indicates
+ *  that the Layer 3 IP Source Address field is enabled for perfect matching This bit
+ *  is valid and applicable only when Bit 2 _L3SAM0_ is set high
+ */
+#define EMAC_L3SAIM0    (BIT(3))
+#define EMAC_L3SAIM0_M  (EMAC_L3SAIM0_V << EMAC_L3SAIM0_S)
+#define EMAC_L3SAIM0_V  0x00000001U
+#define EMAC_L3SAIM0_S  3
+/** EMAC_L3DAM0 : R/W; bitpos: [4]; default: 0;
+ *  Layer 3 IP DA Match Enable When set, this bit indicates that Layer 3 IP Destination
+ *  Address field is enabled for matching When reset, the MAC ignores the Layer 3 IP
+ *  Destination Address field for matching Note: When Bit 0 _L3PEN0_ is set, you should
+ *  set either this bit or Bit 2 _L3SAM0_ because either IPv6 DA or SA can be checked
+ *  for filtering
+ */
+#define EMAC_L3DAM0    (BIT(4))
+#define EMAC_L3DAM0_M  (EMAC_L3DAM0_V << EMAC_L3DAM0_S)
+#define EMAC_L3DAM0_V  0x00000001U
+#define EMAC_L3DAM0_S  4
+/** EMAC_L3DAIM0 : R/W; bitpos: [5]; default: 0;
+ *  Layer 3 IP DA Inverse Match Enable When set, this bit indicates that the Layer 3 IP
+ *  Destination Address field is enabled for inverse matching When reset, this bit
+ *  indicates that the Layer 3 IP Destination Address field is enabled for perfect
+ *  matching This bit is valid and applicable only when Bit 4 _L3DAM0_ is set high
+ */
+#define EMAC_L3DAIM0    (BIT(5))
+#define EMAC_L3DAIM0_M  (EMAC_L3DAIM0_V << EMAC_L3DAIM0_S)
+#define EMAC_L3DAIM0_V  0x00000001U
+#define EMAC_L3DAIM0_S  5
+/** EMAC_L3HSBM0 : R/W; bitpos: [10:6]; default: 0;
+ *  Layer 3 IP SA Higher Bits Match IPv4 Frames: This field contains the number of
+ *  lower bits of IP Source Address that are masked for matching in the IPv4 frames The
+ *  following list describes the values of this field: 0: No bits are masked 1: LSb[0]
+ *  is masked 2: Two LSbs [1:0] are masked  31: All bits except MSb are masked IPv6
+ *  Frames: This field contains Bits [4:0] of the field that indicates the number of
+ *  higher bits of IP Source or Destination Address matched in the IPv6 frames This
+ *  field is valid and applicable only if L3DAM0 or L3SAM0 is set high
+ */
+#define EMAC_L3HSBM0    0x0000001FU
+#define EMAC_L3HSBM0_M  (EMAC_L3HSBM0_V << EMAC_L3HSBM0_S)
+#define EMAC_L3HSBM0_V  0x0000001FU
+#define EMAC_L3HSBM0_S  6
+/** EMAC_L3HDBM0 : R/W; bitpos: [15:11]; default: 0;
+ *  Layer 3 IP DA Higher Bits Match IPv4 Frames: This field contains the number of
+ *  higher bits of IP Destination Address that are matched in the IPv4 frames The
+ *  following list describes the values of this field: 0: No bits are masked 1: LSb[0]
+ *  is masked 2: Two LSbs [1:0] are masked  31: All bits except MSb are masked IPv6
+ *  Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which
+ *  indicate the number of lower bits of IP Source or Destination Address that are
+ *  masked in the IPv6 frames The following list describes the concatenated values of
+ *  the L3HDBM0[1:0] and L3HSBM0 bits: 0: No bits are masked 1: LSb[0] is masked 2: Two
+ *  LSbs [1:0] are masked … 127: All bits except MSb are masked This field is valid and
+ *  applicable only if L3DAM0 or L3SAM0 is set high
+ */
+#define EMAC_L3HDBM0    0x0000001FU
+#define EMAC_L3HDBM0_M  (EMAC_L3HDBM0_V << EMAC_L3HDBM0_S)
+#define EMAC_L3HDBM0_V  0x0000001FU
+#define EMAC_L3HDBM0_S  11
+/** EMAC_L4PEN0 : R/W; bitpos: [16]; default: 0;
+ *  Layer 4 Protocol Enable When set, this bit indicates that the Source and
+ *  Destination Port number fields for UDP frames are used for matching When reset,
+ *  this bit indicates that the Source and Destination Port number fields for TCP
+ *  frames are used for matching The Layer 4 matching is done only when either L4SPM0
+ *  or L4DPM0 bit is set high
+ */
+#define EMAC_L4PEN0    (BIT(16))
+#define EMAC_L4PEN0_M  (EMAC_L4PEN0_V << EMAC_L4PEN0_S)
+#define EMAC_L4PEN0_V  0x00000001U
+#define EMAC_L4PEN0_S  16
+/** EMAC_L4SPM0 : R/W; bitpos: [18]; default: 0;
+ *  Layer 4 Source Port Match Enable When set, this bit indicates that the Layer 4
+ *  Source Port number field is enabled for matching When reset, the MAC ignores the
+ *  Layer 4 Source Port number field for matching
+ */
+#define EMAC_L4SPM0    (BIT(18))
+#define EMAC_L4SPM0_M  (EMAC_L4SPM0_V << EMAC_L4SPM0_S)
+#define EMAC_L4SPM0_V  0x00000001U
+#define EMAC_L4SPM0_S  18
+/** EMAC_L4SPIM0 : R/W; bitpos: [19]; default: 0;
+ *  Layer 4 Source Port Inverse Match Enable When set, this bit indicates that the
+ *  Layer 4 Source Port number field is enabled for inverse matching When reset, this
+ *  bit indicates that the Layer 4 Source Port number field is enabled for perfect
+ *  matching This bit is valid and applicable only when Bit 18 _L4SPM0_ is set high
+ */
+#define EMAC_L4SPIM0    (BIT(19))
+#define EMAC_L4SPIM0_M  (EMAC_L4SPIM0_V << EMAC_L4SPIM0_S)
+#define EMAC_L4SPIM0_V  0x00000001U
+#define EMAC_L4SPIM0_S  19
+/** EMAC_L4DPM0 : R/W; bitpos: [20]; default: 0;
+ *  Layer 4 Destination Port Match Enable When set, this bit indicates that the Layer 4
+ *  Destination Port number field is enabled for matching When reset, the MAC ignores
+ *  the Layer 4 Destination Port number field for matching
+ */
+#define EMAC_L4DPM0    (BIT(20))
+#define EMAC_L4DPM0_M  (EMAC_L4DPM0_V << EMAC_L4DPM0_S)
+#define EMAC_L4DPM0_V  0x00000001U
+#define EMAC_L4DPM0_S  20
+/** EMAC_L4DPIM0 : R/W; bitpos: [21]; default: 0;
+ *  Layer 4 Destination Port Inverse Match Enable When set, this bit indicates that the
+ *  Layer 4 Destination Port number field is enabled for inverse matching When reset,
+ *  this bit indicates that the Layer 4 Destination Port number field is enabled for
+ *  perfect matching This bit is valid and applicable only when Bit 20 _L4DPM0_ is set
+ *  high
+ */
+#define EMAC_L4DPIM0    (BIT(21))
+#define EMAC_L4DPIM0_M  (EMAC_L4DPIM0_V << EMAC_L4DPIM0_S)
+#define EMAC_L4DPIM0_V  0x00000001U
+#define EMAC_L4DPIM0_S  21
+
+/** EMAC_LAYER4ADDRESSREGISTER0_REG register
+ *  Layer 4 Port number field It contains the 16bit Source and Destination Port numbers
+ *  of the TCP or UDP frame
+ */
+#define EMAC_LAYER4ADDRESSREGISTER0_REG (DR_REG_EMAC_BASE + 0x404)
+/** EMAC_L4SP0 : R/W; bitpos: [15:0]; default: 0;
+ *  Layer 4 Source Port Number Field When Bit 16 _L4PEN0_ is reset and Bit 20 _L4DPM0_
+ *  is set in Register 256 _Layer 3 and Layer 4 Control Register 0_, this field
+ *  contains the value to be matched with the TCP Source Port Number field in the IPv4
+ *  or IPv6 frames When Bit 16 _L4PEN0_ and Bit 20 _L4DPM0_ are set in Register 256
+ *  _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+ *  matched with the UDP Source Port Number field in the IPv4 or IPv6 frames
+ */
+#define EMAC_L4SP0    0x0000FFFFU
+#define EMAC_L4SP0_M  (EMAC_L4SP0_V << EMAC_L4SP0_S)
+#define EMAC_L4SP0_V  0x0000FFFFU
+#define EMAC_L4SP0_S  0
+/** EMAC_L4DP0 : R/W; bitpos: [31:16]; default: 0;
+ *  Layer 4 Destination Port Number Field When Bit 16 _L4PEN0_ is reset and Bit 20
+ *  _L4DPM0_ is set in Register 256 _Layer 3 and Layer 4 Control Register 0_, this
+ *  field contains the value to be matched with the TCP Destination Port Number field
+ *  in the IPv4 or IPv6 frames When Bit 16 _L4PEN0_ and Bit 20 _L4DPM0_ are set in
+ *  Register 256 _Layer 3 and Layer 4 Control Register 0_, this field contains the
+ *  value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6
+ *  frames
+ */
+#define EMAC_L4DP0    0x0000FFFFU
+#define EMAC_L4DP0_M  (EMAC_L4DP0_V << EMAC_L4DP0_S)
+#define EMAC_L4DP0_V  0x0000FFFFU
+#define EMAC_L4DP0_S  16
+
+/** EMAC_LAYER3ADDRESS0REGISTER0_REG register
+ *  Layer 3 Address field For IPv4 frames, it contains the 32bit IP Source Address
+ *  field For IPv6 frames, it contains Bits [31:0] of the 128bit IP Source Address or
+ *  Destination Address field
+ */
+#define EMAC_LAYER3ADDRESS0REGISTER0_REG (DR_REG_EMAC_BASE + 0x410)
+/** EMAC_L3A00 : R/W; bitpos: [31:0]; default: 0;
+ *  Layer 3 Address 0 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+ *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+ *  matched with Bits [31:0] of the IP Source Address field in the IPv6 frames When Bit
+ *  0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4 Control
+ *  Register 0_, this field contains the value to be matched with Bits [31:0] of the IP
+ *  Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset and Bit 2
+ *  _L3SAM0_ is set in Register 256 _Layer 3 and Layer 4 Control Register 0_, this
+ *  field contains the value to be matched with the IP Source Address field in the IPv4
+ *  frames
+ */
+#define EMAC_L3A00    0xFFFFFFFFU
+#define EMAC_L3A00_M  (EMAC_L3A00_V << EMAC_L3A00_S)
+#define EMAC_L3A00_V  0xFFFFFFFFU
+#define EMAC_L3A00_S  0
+
+/** EMAC_LAYER3ADDRESS1REGISTER0_REG register
+ *  Layer 3 Address 1 field For IPv4 frames, it contains the 32bit IP Destination
+ *  Address field For IPv6 frames, it contains Bits [63:32] of the 128bit IP Source
+ *  Address or Destination Address field
+ */
+#define EMAC_LAYER3ADDRESS1REGISTER0_REG (DR_REG_EMAC_BASE + 0x414)
+/** EMAC_L3A10 : R/W; bitpos: [31:0]; default: 0;
+ *  Layer 3 Address 1 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+ *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+ *  matched with Bits [63:32] of the IP Source Address field in the IPv6 frames When
+ *  Bit 0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4
+ *  Control Register 0_, this field contains the value to be matched with Bits [63:32]
+ *  of the IP Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset
+ *  and Bit 4 _L3DAM0_ is set in Register 256 _Layer 3 and Layer 4 Control Register 0_,
+ *  this field contains the value to be matched with the IP Destination Address field
+ *  in the IPv4 frames
+ */
+#define EMAC_L3A10    0xFFFFFFFFU
+#define EMAC_L3A10_M  (EMAC_L3A10_V << EMAC_L3A10_S)
+#define EMAC_L3A10_V  0xFFFFFFFFU
+#define EMAC_L3A10_S  0
+
+/** EMAC_LAYER3ADDRESS2REGISTER0_REG register
+ *  Layer 3 Address 2 field This register is reserved for IPv4 frames For IPv6 frames,
+ *  it contains Bits [95:64] of the 128bit IP Source Address or Destination Address
+ *  field
+ */
+#define EMAC_LAYER3ADDRESS2REGISTER0_REG (DR_REG_EMAC_BASE + 0x418)
+/** EMAC_L3A20 : R/W; bitpos: [31:0]; default: 0;
+ *  Layer 3 Address 2 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+ *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+ *  matched with Bits [95:64] of the IP Source Address field in the IPv6 frames When
+ *  Bit 0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4
+ *  Control Register 0_, this field contains value to be matched with Bits [95:64] of
+ *  the IP Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset in
+ *  Register 256 _Layer 3 and Layer 4 Control Register 0_, this register is not used
+ */
+#define EMAC_L3A20    0xFFFFFFFFU
+#define EMAC_L3A20_M  (EMAC_L3A20_V << EMAC_L3A20_S)
+#define EMAC_L3A20_V  0xFFFFFFFFU
+#define EMAC_L3A20_S  0
+
+/** EMAC_LAYER3ADDRESS3REGISTER0_REG register
+ *  Layer 3 Address 3 field This register is reserved for IPv4 frames For IPv6 frames,
+ *  it contains Bits [127:96] of the 128bit IP Source Address or Destination Address
+ *  field
+ */
+#define EMAC_LAYER3ADDRESS3REGISTER0_REG (DR_REG_EMAC_BASE + 0x41c)
+/** EMAC_L3A30 : R/W; bitpos: [31:0]; default: 0;
+ *  Layer 3 Address 3 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+ *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+ *  matched with Bits [127:96] of the IP Source Address field in the IPv6 frames When
+ *  Bit 0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4
+ *  Control Register 0_, this field contains the value to be matched with Bits [127:96]
+ *  of the IP Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset
+ *  in Register 256 _Layer 3 and Layer 4 Control Register 0_, this register is not used
+ */
+#define EMAC_L3A30    0xFFFFFFFFU
+#define EMAC_L3A30_M  (EMAC_L3A30_V << EMAC_L3A30_S)
+#define EMAC_L3A30_V  0xFFFFFFFFU
+#define EMAC_L3A30_S  0
+
+/** EMAC_HASHTABLEREGISTER0_REG register
+ *  This register contains the first 32 bits of the hash table when the width of the
+ *  Hash table is 128 bits or 256 bits
+ */
+#define EMAC_HASHTABLEREGISTER0_REG (DR_REG_EMAC_BASE + 0x500)
+/** EMAC_HT31T0 : R/W; bitpos: [31:0]; default: 0;
+ *  First 32 bits of Hash Table This field contains the first 32 Bits _31:0_ of the
+ *  Hash table Note Registers 321 through 327 are similar to Register 320 _Hash Table
+ *  Register 0_ Registers 324 through 327 are present only when you select the 256bit
+ *  Hash table during core configuration
+ */
+#define EMAC_HT31T0    0xFFFFFFFFU
+#define EMAC_HT31T0_M  (EMAC_HT31T0_V << EMAC_HT31T0_S)
+#define EMAC_HT31T0_V  0xFFFFFFFFU
+#define EMAC_HT31T0_S  0
+
+/** EMAC_VLANTAGINCLUSIONORREPLACEMENT_REG register
+ *  This register contains the VLAN tag for insertion into or replacement in the
+ *  transmit frames
+ */
+#define EMAC_VLANTAGINCLUSIONORREPLACEMENT_REG (DR_REG_EMAC_BASE + 0x584)
+/** EMAC_VLT : R/W; bitpos: [15:0]; default: 0;
+ *  VLAN Tag for Transmit Frames This field contains the value of the VLAN tag to be
+ *  inserted or replaced The value must only be changed when the transmit lines are
+ *  inactive or during the initialization phase Bits[15:13] are the User Priority, Bit
+ *  12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field
+ */
+#define EMAC_VLT    0x0000FFFFU
+#define EMAC_VLT_M  (EMAC_VLT_V << EMAC_VLT_S)
+#define EMAC_VLT_V  0x0000FFFFU
+#define EMAC_VLT_S  0
+/** EMAC_VLC : R/W; bitpos: [17:16]; default: 0;
+ *  VLAN Tag Control in Transmit Frames 2’b00: No VLAN tag deletion, insertion, or
+ *  replacement 2’b01: VLAN tag deletion The MAC removes the VLAN type _bytes 13 and
+ *  14_ and VLAN tag _bytes 15 and 16_ of all transmitted frames with VLAN tags 2’b10:
+ *  VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after
+ *  inserting the Type value _0x8100/0x88a8_ in bytes 13 and 14 This operation is
+ *  performed on all transmitted frames, irrespective of whether they already have a
+ *  VLAN tag 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all
+ *  VLANtype transmitted frames _Bytes 13 and 14 are 0x8100/0x88a8_ Note: Changes to
+ *  this field take effect only on the start of a frame If you write this register
+ *  field when a frame is being transmitted, only the subsequent frame can use the
+ *  updated value, that is, the current frame does not use the updated value
+ */
+#define EMAC_VLC    0x00000003U
+#define EMAC_VLC_M  (EMAC_VLC_V << EMAC_VLC_S)
+#define EMAC_VLC_V  0x00000003U
+#define EMAC_VLC_S  16
+/** EMAC_VLP : R/W; bitpos: [18]; default: 0;
+ *  VLAN Priority Control When this bit is set, the control Bits [17:16] are used for
+ *  VLAN deletion, insertion, or replacement When this bit is reset, the
+ *  mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored
+ */
+#define EMAC_VLP    (BIT(18))
+#define EMAC_VLP_M  (EMAC_VLP_V << EMAC_VLP_S)
+#define EMAC_VLP_V  0x00000001U
+#define EMAC_VLP_S  18
+/** EMAC_CSVL : R/W; bitpos: [19]; default: 0;
+ *  CVLAN or SVLAN When this bit is set, SVLAN type _0x88A8_ is inserted or replaced in
+ *  the 13th and 14th bytes of transmitted frames When this bit is reset, CVLAN type
+ *  _0x8100_ is inserted or replaced in the transmitted frames
+ */
+#define EMAC_CSVL    (BIT(19))
+#define EMAC_CSVL_M  (EMAC_CSVL_V << EMAC_CSVL_S)
+#define EMAC_CSVL_V  0x00000001U
+#define EMAC_CSVL_S  19
+
+/** EMAC_VLANHASHTABLE_REG register
+ *  This register contains the VLAN hash table
+ */
+#define EMAC_VLANHASHTABLE_REG (DR_REG_EMAC_BASE + 0x588)
+/** EMAC_VLHT : R/W; bitpos: [15:0]; default: 0;
+ *  VLAN Hash Table This field contains the 16bit VLAN Hash Table
+ */
+#define EMAC_VLHT    0x0000FFFFU
+#define EMAC_VLHT_M  (EMAC_VLHT_V << EMAC_VLHT_S)
+#define EMAC_VLHT_V  0x0000FFFFU
+#define EMAC_VLHT_S  0
+
+/** EMAC_TIMESTAMPCONTROL_REG register
+ *  Controls the timestamp generation and update logic This register is present only
+ *  when IEEE1588 timestamping is enabled during coreConsultant configuration
+ */
+#define EMAC_TIMESTAMPCONTROL_REG (DR_REG_EMAC_BASE + 0x700)
+/** EMAC_TSENA : R/W; bitpos: [0]; default: 0;
+ *  Timestamp Enable When set, the timestamp is added for the transmit and receive
+ *  frames When disabled, timestamp is not added for the transmit and receive frames
+ *  and the Timestamp Generator is also suspended You need to initialize the Timestamp
+ *  _system time_ after enabling this mode On the receive side, the MAC processes the
+ *  1588 frames only if this bit is set
+ */
+#define EMAC_TSENA    (BIT(0))
+#define EMAC_TSENA_M  (EMAC_TSENA_V << EMAC_TSENA_S)
+#define EMAC_TSENA_V  0x00000001U
+#define EMAC_TSENA_S  0
+/** EMAC_TSCFUPDT : R/W; bitpos: [1]; default: 0;
+ *  Timestamp Fine or Coarse Update When set, this bit indicates that the system times
+ *  update should be done using the fine update method When reset, it indicates the
+ *  system timestamp update should be done using the Coarse method
+ */
+#define EMAC_TSCFUPDT    (BIT(1))
+#define EMAC_TSCFUPDT_M  (EMAC_TSCFUPDT_V << EMAC_TSCFUPDT_S)
+#define EMAC_TSCFUPDT_V  0x00000001U
+#define EMAC_TSCFUPDT_S  1
+/** EMAC_TSINIT : R/W1S; bitpos: [2]; default: 0;
+ *  Timestamp Initialize When set, the system time is initialized _overwritten_ with
+ *  the value specified in the Register 452 _System Time  Seconds Update Register_ and
+ *  Register 453 _System Time  Nanoseconds Update Register_ This bit should be read
+ *  zero before updating it This bit is reset when the initialization is complete The
+ *  “Timestamp Higher Word” register _if enabled during core configuration_ can only be
+ *  initialized
+ */
+#define EMAC_TSINIT    (BIT(2))
+#define EMAC_TSINIT_M  (EMAC_TSINIT_V << EMAC_TSINIT_S)
+#define EMAC_TSINIT_V  0x00000001U
+#define EMAC_TSINIT_S  2
+/** EMAC_TSUPDT : R/W1S; bitpos: [3]; default: 0;
+ *  Timestamp Update When set, the system time is updated _added or subtracted_ with
+ *  the value specified in Register 452 _System Time  Seconds Update Register_ and
+ *  Register 453 _System Time  Nanoseconds Update Register_ This bit should be read
+ *  zero before updating it This bit is reset when the update is completed in hardware
+ *  The “Timestamp Higher Word” register _if enabled during core configuration_ is not
+ *  updated
+ */
+#define EMAC_TSUPDT    (BIT(3))
+#define EMAC_TSUPDT_M  (EMAC_TSUPDT_V << EMAC_TSUPDT_S)
+#define EMAC_TSUPDT_V  0x00000001U
+#define EMAC_TSUPDT_S  3
+/** EMAC_TSTRIG : R/W1S; bitpos: [4]; default: 0;
+ *  Timestamp Interrupt Trigger Enable When set, the timestamp interrupt is generated
+ *  when the System Time becomes greater than the value written in the Target Time
+ *  register This bit is reset after the generation of the Timestamp Trigger Interrupt
+ */
+#define EMAC_TSTRIG    (BIT(4))
+#define EMAC_TSTRIG_M  (EMAC_TSTRIG_V << EMAC_TSTRIG_S)
+#define EMAC_TSTRIG_V  0x00000001U
+#define EMAC_TSTRIG_S  4
+/** EMAC_TSADDREG : R/W1S; bitpos: [5]; default: 0;
+ *  Addend Reg Update When set, the content of the Timestamp Addend register is updated
+ *  in the PTP block for fine correction This is cleared when the update is completed
+ *  This register bit should be zero before setting it
+ */
+#define EMAC_TSADDREG    (BIT(5))
+#define EMAC_TSADDREG_M  (EMAC_TSADDREG_V << EMAC_TSADDREG_S)
+#define EMAC_TSADDREG_V  0x00000001U
+#define EMAC_TSADDREG_S  5
+/** EMAC_TSENALL : R/W; bitpos: [8]; default: 0;
+ *  Enable Timestamp for All Frames When set, the timestamp snapshot is enabled for all
+ *  frames received by the MAC
+ */
+#define EMAC_TSENALL    (BIT(8))
+#define EMAC_TSENALL_M  (EMAC_TSENALL_V << EMAC_TSENALL_S)
+#define EMAC_TSENALL_V  0x00000001U
+#define EMAC_TSENALL_S  8
+/** EMAC_TSCTRLSSR : R/W; bitpos: [9]; default: 0;
+ *  Timestamp Digital or Binary Rollover Control When set, the Timestamp Low register
+ *  rolls over after 0x3B9A_C9FF value _that is, 1 nanosecond accuracy_ and increments
+ *  the timestamp _High_ seconds When reset, the rollover value of subsecond register
+ *  is 0x7FFF_FFFF The subsecond increment has to be programmed correctly depending on
+ *  the PTP reference clock frequency and the value of this bit
+ */
+#define EMAC_TSCTRLSSR    (BIT(9))
+#define EMAC_TSCTRLSSR_M  (EMAC_TSCTRLSSR_V << EMAC_TSCTRLSSR_S)
+#define EMAC_TSCTRLSSR_V  0x00000001U
+#define EMAC_TSCTRLSSR_S  9
+/** EMAC_TSVER2ENA : R/W; bitpos: [10]; default: 0;
+ *  Enable PTP packet Processing for Version 2 Format When set, the PTP packets are
+ *  processed using the 1588 version 2 format Otherwise, the PTP packets are processed
+ *  using the version 1 format The IEEE 1588 Version 1 and Version 2 format are
+ *  described in “PTP Processing and Control” on page 155
+ */
+#define EMAC_TSVER2ENA    (BIT(10))
+#define EMAC_TSVER2ENA_M  (EMAC_TSVER2ENA_V << EMAC_TSVER2ENA_S)
+#define EMAC_TSVER2ENA_V  0x00000001U
+#define EMAC_TSVER2ENA_S  10
+/** EMAC_TSIPENA : R/W; bitpos: [11]; default: 0;
+ *  Enable Processing of PTP over Ethernet Frames When set, the MAC receiver processes
+ *  the PTP packets encapsulated directly in the Ethernet frames When this bit is
+ *  clear, the MAC ignores the PTP over Ethernet packets
+ */
+#define EMAC_TSIPENA    (BIT(11))
+#define EMAC_TSIPENA_M  (EMAC_TSIPENA_V << EMAC_TSIPENA_S)
+#define EMAC_TSIPENA_V  0x00000001U
+#define EMAC_TSIPENA_S  11
+/** EMAC_TSIPV6ENA : R/W; bitpos: [12]; default: 0;
+ *  Enable Processing of PTP Frames Sent over IPv6UDP When set, the MAC receiver
+ *  processes PTP packets encapsulated in UDP over IPv6 packets When this bit is clear,
+ *  the MAC ignores the PTP transported over UDPIPv6 packets
+ */
+#define EMAC_TSIPV6ENA    (BIT(12))
+#define EMAC_TSIPV6ENA_M  (EMAC_TSIPV6ENA_V << EMAC_TSIPV6ENA_S)
+#define EMAC_TSIPV6ENA_V  0x00000001U
+#define EMAC_TSIPV6ENA_S  12
+/** EMAC_TSIPV4ENA : R/W; bitpos: [13]; default: 1;
+ *  Enable Processing of PTP Frames Sent over IPv4UDP When set, the MAC receiver
+ *  processes the PTP packets encapsulated in UDP over IPv4 packets When this bit is
+ *  clear, the MAC ignores the PTP transported over UDPIPv4 packets This bit is set by
+ *  default
+ */
+#define EMAC_TSIPV4ENA    (BIT(13))
+#define EMAC_TSIPV4ENA_M  (EMAC_TSIPV4ENA_V << EMAC_TSIPV4ENA_S)
+#define EMAC_TSIPV4ENA_V  0x00000001U
+#define EMAC_TSIPV4ENA_S  13
+/** EMAC_TSEVNTENA : R/W; bitpos: [14]; default: 0;
+ *  Enable Timestamp Snapshot for Event Messages When set, the timestamp snapshot is
+ *  taken only for event messages _SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp_ When
+ *  reset, the snapshot is taken for all messages except Announce, Management, and
+ *  Signaling For more information about the timestamp snapshots, see Table 670 on page
+ *  462
+ */
+#define EMAC_TSEVNTENA    (BIT(14))
+#define EMAC_TSEVNTENA_M  (EMAC_TSEVNTENA_V << EMAC_TSEVNTENA_S)
+#define EMAC_TSEVNTENA_V  0x00000001U
+#define EMAC_TSEVNTENA_S  14
+/** EMAC_TSMSTRENA : R/W; bitpos: [15]; default: 0;
+ *  Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken
+ *  only for the messages relevant to the master node Otherwise, the snapshot is taken
+ *  for the messages relevant to the slave node
+ */
+#define EMAC_TSMSTRENA    (BIT(15))
+#define EMAC_TSMSTRENA_M  (EMAC_TSMSTRENA_V << EMAC_TSMSTRENA_S)
+#define EMAC_TSMSTRENA_V  0x00000001U
+#define EMAC_TSMSTRENA_S  15
+/** EMAC_SNAPTYPSEL : R/W; bitpos: [17:16]; default: 0;
+ *  Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide
+ *  the set of PTP packet types for which snapshot needs to be taken The encoding is
+ *  given in Table 670 on page 462
+ */
+#define EMAC_SNAPTYPSEL    0x00000003U
+#define EMAC_SNAPTYPSEL_M  (EMAC_SNAPTYPSEL_V << EMAC_SNAPTYPSEL_S)
+#define EMAC_SNAPTYPSEL_V  0x00000003U
+#define EMAC_SNAPTYPSEL_S  16
+/** EMAC_TSENMACADDR : R/W; bitpos: [18]; default: 0;
+ *  Enable MAC address for PTP Frame Filtering When set, the DA MAC address _that
+ *  matches any MAC Address register_ is used to filter the PTP frames when PTP is
+ *  directly sent over Ethernet
+ */
+#define EMAC_TSENMACADDR    (BIT(18))
+#define EMAC_TSENMACADDR_M  (EMAC_TSENMACADDR_V << EMAC_TSENMACADDR_S)
+#define EMAC_TSENMACADDR_V  0x00000001U
+#define EMAC_TSENMACADDR_S  18
+/** EMAC_ATSFC : R/W1S; bitpos: [24]; default: 0;
+ *  Auxiliary Snapshot FIFO Clear When set, it resets the pointers of the Auxiliary
+ *  Snapshot FIFO This bit is cleared when the pointers are reset and the FIFO is empty
+ *  When this bit is high, auxiliary snapshots get stored in the FIFO This bit is
+ *  reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during
+ *  core configuration
+ */
+#define EMAC_ATSFC    (BIT(24))
+#define EMAC_ATSFC_M  (EMAC_ATSFC_V << EMAC_ATSFC_S)
+#define EMAC_ATSFC_V  0x00000001U
+#define EMAC_ATSFC_S  24
+/** EMAC_ATSEN0 : R/W; bitpos: [25]; default: 0;
+ *  Auxiliary Snapshot 0 Enable This field controls capturing the Auxiliary Snapshot
+ *  Trigger 0 When this bit is set, the Auxiliary snapshot of event on
+ *  ptp_aux_trig_i[0] input is enabled When this bit is reset, the events on this input
+ *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+ *  is not selected during core configuration
+ */
+#define EMAC_ATSEN0    (BIT(25))
+#define EMAC_ATSEN0_M  (EMAC_ATSEN0_V << EMAC_ATSEN0_S)
+#define EMAC_ATSEN0_V  0x00000001U
+#define EMAC_ATSEN0_S  25
+/** EMAC_ATSEN1 : R/W; bitpos: [26]; default: 0;
+ *  Auxiliary Snapshot 1 Enable This field controls capturing the Auxiliary Snapshot
+ *  Trigger 1 When this bit is set, the Auxiliary snapshot of event on
+ *  ptp_aux_trig_i[1] input is enabled When this bit is reset, the events on this input
+ *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+ *  is not selected during core configuration or the selected number in the Number of
+ *  IEEE 1588 Auxiliary Snapshot Inputs option is less than two
+ */
+#define EMAC_ATSEN1    (BIT(26))
+#define EMAC_ATSEN1_M  (EMAC_ATSEN1_V << EMAC_ATSEN1_S)
+#define EMAC_ATSEN1_V  0x00000001U
+#define EMAC_ATSEN1_S  26
+/** EMAC_ATSEN2 : R/W; bitpos: [27]; default: 0;
+ *  Auxiliary Snapshot 2 Enable This field controls capturing the Auxiliary Snapshot
+ *  Trigger 2 When this bit is set, the Auxiliary snapshot of event on
+ *  ptp_aux_trig_i[2] input is enabled When this bit is reset, the events on this input
+ *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+ *  is not selected during core configuration or the selected number in the Number of
+ *  IEEE 1588 Auxiliary Snapshot Inputs option is less than three
+ */
+#define EMAC_ATSEN2    (BIT(27))
+#define EMAC_ATSEN2_M  (EMAC_ATSEN2_V << EMAC_ATSEN2_S)
+#define EMAC_ATSEN2_V  0x00000001U
+#define EMAC_ATSEN2_S  27
+/** EMAC_ATSEN3 : R/W; bitpos: [28]; default: 0;
+ *  Auxiliary Snapshot 3 Enable This field controls capturing the Auxiliary Snapshot
+ *  Trigger 3 When this bit is set, the Auxiliary snapshot of event on
+ *  ptp_aux_trig_i[3] input is enabled When this bit is reset, the events on this input
+ *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+ *  is not selected during core configuration or the selected number in the Number of
+ *  IEEE 1588 Auxiliary Snapshot Inputs option is less than four
+ */
+#define EMAC_ATSEN3    (BIT(28))
+#define EMAC_ATSEN3_M  (EMAC_ATSEN3_V << EMAC_ATSEN3_S)
+#define EMAC_ATSEN3_V  0x00000001U
+#define EMAC_ATSEN3_S  28
+
+/** EMAC_SUBSECONDINCREMENT_REG register
+ *  Contains the 8bit value by which the SubSecond register is incremented This
+ *  register is present only when IEEE1588 timestamping is enabled without an external
+ *  timestamp input
+ */
+#define EMAC_SUBSECONDINCREMENT_REG (DR_REG_EMAC_BASE + 0x704)
+/** EMAC_SSINC : R/W; bitpos: [7:0]; default: 0;
+ *  Subsecond Increment Value The value programmed in this field is accumulated every
+ *  clock cycle _of clk_ptp_i_ with the contents of the subsecond register For example,
+ *  when PTP clock is 50 MHz _period is 20 ns_, you should program 20 _0x14_ when the
+ *  System Time Nanoseconds register has an accuracy of 1 ns [Bit 9 _TSCTRLSSR_ is set
+ *  in Register 448 _Timestamp Control Register_] When TSCTRLSSR is clear, the
+ *  Nanoseconds register has a resolution of ~0465ns In this case, you should program a
+ *  value of 43 _0x2B_ that is derived by 20ns/0465
+ */
+#define EMAC_SSINC    0x000000FFU
+#define EMAC_SSINC_M  (EMAC_SSINC_V << EMAC_SSINC_S)
+#define EMAC_SSINC_V  0x000000FFU
+#define EMAC_SSINC_S  0
+
+/** EMAC_SYSTEMTIMESECONDS_REG register
+ *  Contains the lower 32 bits of the seconds field of the system time This register is
+ *  present only when IEEE1588 timestamping is enabled without an external timestamp
+ *  input
+ */
+#define EMAC_SYSTEMTIMESECONDS_REG (DR_REG_EMAC_BASE + 0x708)
+/** EMAC_TSS_RO : RO; bitpos: [31:0]; default: 0;
+ *  Timestamp Second The value in this field indicates the current value in seconds of
+ *  the System Time maintained by the MAC
+ */
+#define EMAC_TSS_RO    0xFFFFFFFFU
+#define EMAC_TSS_RO_M  (EMAC_TSS_RO_V << EMAC_TSS_RO_S)
+#define EMAC_TSS_RO_V  0xFFFFFFFFU
+#define EMAC_TSS_RO_S  0
+
+/** EMAC_SYSTEMTIMENANOSECONDS_REG register
+ *  Contains 32 bits of the nanoseconds field of the system time This register is only
+ *  present when IEEE1588 timestamping is enabled without an external timestamp input
+ */
+#define EMAC_SYSTEMTIMENANOSECONDS_REG (DR_REG_EMAC_BASE + 0x70c)
+/** EMAC_TSSS_RO : RO; bitpos: [30:0]; default: 0;
+ *  Timestamp Sub Seconds The value in this field has the sub second representation of
+ *  time, with an accuracy of 046 ns When Bit 9 _TSCTRLSSR_ is set in Register 448
+ *  _Timestamp Control Register_, each bit represents 1 ns and the maximum value is
+ *  0x3B9A_C9FF, after which it rollsover to zero
+ */
+#define EMAC_TSSS_RO    0x7FFFFFFFU
+#define EMAC_TSSS_RO_M  (EMAC_TSSS_RO_V << EMAC_TSSS_RO_S)
+#define EMAC_TSSS_RO_V  0x7FFFFFFFU
+#define EMAC_TSSS_RO_S  0
+
+/** EMAC_SYSTEMTIMESECONDSUPDATE_REG register
+ *  Contains the lower 32 bits of the seconds field to be written to, added to, or
+ *  subtracted from the System Time value This register is only present when IEEE1588
+ *  timestamping is enabled without an external timestamp input
+ */
+#define EMAC_SYSTEMTIMESECONDSUPDATE_REG (DR_REG_EMAC_BASE + 0x710)
+/** EMAC_TSS : R/W; bitpos: [31:0]; default: 0;
+ *  TIMESTAMP SECOND THE VALUE IN THIS FIELD INDICATES THE TIME IN SECONDS TO BE
+ *  INITIALIZED OR ADDED TO THE SYSTEM TIME
+ */
+#define EMAC_TSS    0xFFFFFFFFU
+#define EMAC_TSS_M  (EMAC_TSS_V << EMAC_TSS_S)
+#define EMAC_TSS_V  0xFFFFFFFFU
+#define EMAC_TSS_S  0
+
+/** EMAC_SYSTEMTIMENANOSECONDSUPDATE_REG register
+ *  Contains 32 bits of the nanoseconds field to be written to, added to, or subtracted
+ *  from the System Time value This register is only present when IEEE1588 timestamping
+ *  is enabled without an external timestamp input
+ */
+#define EMAC_SYSTEMTIMENANOSECONDSUPDATE_REG (DR_REG_EMAC_BASE + 0x714)
+/** EMAC_TSSS : R/W; bitpos: [30:0]; default: 0;
+ *  Timestamp Sub Seconds The value in this field has the sub second representation of
+ *  time, with an accuracy of 046 ns When Bit 9 _TSCTRLSSR_ is set in Register 448
+ *  _Timestamp Control Register_, each bit represents 1 ns and the programmed value
+ *  should not exceed 0x3B9A_C9FF
+ */
+#define EMAC_TSSS    0x7FFFFFFFU
+#define EMAC_TSSS_M  (EMAC_TSSS_V << EMAC_TSSS_S)
+#define EMAC_TSSS_V  0x7FFFFFFFU
+#define EMAC_TSSS_S  0
+/** EMAC_ADDSUB : R/W; bitpos: [31]; default: 0;
+ *  Add or Subtract Time When this bit is set, the time value is subtracted with the
+ *  contents of the update register When this bit is reset, the time value is added
+ *  with the contents of the update register
+ */
+#define EMAC_ADDSUB    (BIT(31))
+#define EMAC_ADDSUB_M  (EMAC_ADDSUB_V << EMAC_ADDSUB_S)
+#define EMAC_ADDSUB_V  0x00000001U
+#define EMAC_ADDSUB_S  31
+
+/** EMAC_TIMESTAMPADDEND_REG register
+ *  This register is used by the software to readjust the clock frequency linearly to
+ *  match the master clock frequency This register is only present when IEEE1588
+ *  timestamping is enabled without an external timestamp input
+ */
+#define EMAC_TIMESTAMPADDEND_REG (DR_REG_EMAC_BASE + 0x718)
+/** EMAC_TSAR : R/W; bitpos: [31:0]; default: 0;
+ *  Timestamp Addend Register This field indicates the 32bit time value to be added to
+ *  the Accumulator register to achieve time synchronization
+ */
+#define EMAC_TSAR    0xFFFFFFFFU
+#define EMAC_TSAR_M  (EMAC_TSAR_V << EMAC_TSAR_S)
+#define EMAC_TSAR_V  0xFFFFFFFFU
+#define EMAC_TSAR_S  0
+
+/** EMAC_TARGETTIMESECONDS_REG register
+ *  Contains the higher 32 bits of time to be compared with the system time for
+ *  interrupt event generation or to start the PPS signal output generation This
+ *  register is present only when IEEE1588 timestamping is enabled without an external
+ *  timestamp input
+ */
+#define EMAC_TARGETTIMESECONDS_REG (DR_REG_EMAC_BASE + 0x71c)
+/** EMAC_TSTR : R/W; bitpos: [31:0]; default: 0;
+ *  Target Time Seconds Register This register stores the time in seconds When the
+ *  timestamp value matches or exceeds both Target Timestamp registers, then based on
+ *  Bits [6:5] of Register 459 _PPS Control Register_, the MAC starts or stops the PPS
+ *  signal output and generates an interrupt _if enabled_
+ */
+#define EMAC_TSTR    0xFFFFFFFFU
+#define EMAC_TSTR_M  (EMAC_TSTR_V << EMAC_TSTR_S)
+#define EMAC_TSTR_V  0xFFFFFFFFU
+#define EMAC_TSTR_S  0
+
+/** EMAC_TARGETTIMENANOSECONDS_REG register
+ *  Contains the lower 32 bits of time to be compared with the system time for
+ *  interrupt event generation or to start the PPS signal output generation This
+ *  register is present only when IEEE1588 timestamping is enabled without an external
+ *  timestamp input
+ */
+#define EMAC_TARGETTIMENANOSECONDS_REG (DR_REG_EMAC_BASE + 0x720)
+/** EMAC_TTSLO : R/W; bitpos: [30:0]; default: 0;
+ *  Target Timestamp Low Register This register stores the time in _signed_ nanoseconds
+ *  When the value of the timestamp matches the both Target Timestamp registers, then
+ *  based on the TRGTMODSEL0 field _Bits [6:5]_ in Register 459 _PPS Control Register_,
+ *  the MAC starts or stops the PPS signal output and generates an interrupt _if
+ *  enabled_ This value should not exceed 0x3B9A_C9FF when Bit 9 _TSCTRLSSR_ is set in
+ *  Register 448 _Timestamp Control Register_ The actual start or stop time of the PPS
+ *  signal output may have an error margin up to one unit of subsecond increment value
+ */
+#define EMAC_TTSLO    0x7FFFFFFFU
+#define EMAC_TTSLO_M  (EMAC_TTSLO_V << EMAC_TTSLO_S)
+#define EMAC_TTSLO_V  0x7FFFFFFFU
+#define EMAC_TTSLO_S  0
+/** EMAC_TRGTBUSY : R/W1S; bitpos: [31]; default: 0;
+ *  Target Time Register Busy The MAC sets this bit when the PPSCMD field _Bit [3:0]_
+ *  in Register 459 _PPS Control Register_ is programmed to 010 or 011 Programming the
+ *  PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time
+ *  Registers to the PTP clock domain The MAC clears this bit after synchronizing the
+ *  Target Time Registers to the PTP clock domain The application must not update the
+ *  Target Time Registers when this bit is read as 1 Otherwise, the synchronization of
+ *  the previous programmed time gets corrupted This bit is reserved when the Enable
+ *  Flexible PulsePerSecond Output feature is not selected
+ */
+#define EMAC_TRGTBUSY    (BIT(31))
+#define EMAC_TRGTBUSY_M  (EMAC_TRGTBUSY_V << EMAC_TRGTBUSY_S)
+#define EMAC_TRGTBUSY_V  0x00000001U
+#define EMAC_TRGTBUSY_S  31
+
+/** EMAC_SYSTEMTIMEHIGHERWORDSECONDS_REG register
+ *  Contains the most significant 16bits of the timestamp seconds value This register
+ *  is optional and can be selected using the parameter mentioned in “IEEE 1588
+ *  Timestamp Block” on page 492
+ */
+#define EMAC_SYSTEMTIMEHIGHERWORDSECONDS_REG (DR_REG_EMAC_BASE + 0x724)
+/** EMAC_TSHWR : R/W; bitpos: [15:0]; default: 0;
+ *  Timestamp Higher Word Register This field contains the most significant 16bits of
+ *  the timestamp seconds value This register is optional and can be selected using the
+ *  Enable IEEE 1588 Higher Word Register option during core configuration The register
+ *  is directly written to initialize the value This register is incremented when there
+ *  is an overflow from the 32bits of the System Time  Seconds register
+ */
+#define EMAC_TSHWR    0x0000FFFFU
+#define EMAC_TSHWR_M  (EMAC_TSHWR_V << EMAC_TSHWR_S)
+#define EMAC_TSHWR_V  0x0000FFFFU
+#define EMAC_TSHWR_S  0
+
+/** EMAC_TIMESTAMPSTATUS_REG register
+ *  Contains the PTP status This register is available only when the advanced IEEE 1588
+ *  timestamp feature is selected
+ */
+#define EMAC_TIMESTAMPSTATUS_REG (DR_REG_EMAC_BASE + 0x728)
+/** EMAC_TSSOVF : R/W; bitpos: [0]; default: 0;
+ *  Timestamp Seconds Overflow When set, this bit indicates that the seconds value of
+ *  the timestamp _when supporting version 2 format_ has overflowed beyond 32’hFFFF_FFFF
+ */
+#define EMAC_TSSOVF    (BIT(0))
+#define EMAC_TSSOVF_M  (EMAC_TSSOVF_V << EMAC_TSSOVF_S)
+#define EMAC_TSSOVF_V  0x00000001U
+#define EMAC_TSSOVF_S  0
+/** EMAC_TSTARGT : R/W; bitpos: [1]; default: 0;
+ *  Timestamp Target Time Reached When set, this bit indicates that the value of system
+ *  time is greater than or equal to the value specified in the Register 455 _Target
+ *  Time Seconds Register_ and Register 456 _Target Time Nanoseconds Register_
+ */
+#define EMAC_TSTARGT    (BIT(1))
+#define EMAC_TSTARGT_M  (EMAC_TSTARGT_V << EMAC_TSTARGT_S)
+#define EMAC_TSTARGT_V  0x00000001U
+#define EMAC_TSTARGT_S  1
+/** EMAC_AUXTSTRIG : R/W; bitpos: [2]; default: 0;
+ *  Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary
+ *  snapshot is written to the FIFO This bit is valid only if the Enable IEEE 1588
+ *  Auxiliary Snapshot feature is selected
+ */
+#define EMAC_AUXTSTRIG    (BIT(2))
+#define EMAC_AUXTSTRIG_M  (EMAC_AUXTSTRIG_V << EMAC_AUXTSTRIG_S)
+#define EMAC_AUXTSTRIG_V  0x00000001U
+#define EMAC_AUXTSTRIG_S  2
+/** EMAC_TSTRGTERR : R/W; bitpos: [3]; default: 0;
+ *  Timestamp Target Time Error This bit is set when the target time, being programmed
+ *  in Register 455 and Register 456, is already elapsed This bit is cleared when read
+ *  by the application
+ */
+#define EMAC_TSTRGTERR    (BIT(3))
+#define EMAC_TSTRGTERR_M  (EMAC_TSTRGTERR_V << EMAC_TSTRGTERR_S)
+#define EMAC_TSTRGTERR_V  0x00000001U
+#define EMAC_TSTRGTERR_S  3
+/** EMAC_TSTARGT1 : R/W; bitpos: [4]; default: 0;
+ *  Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates
+ *  that the value of system time is greater than or equal to the value specified in
+ *  Register 480 _PPS1 Target Time High Register_ and Register 481 _PPS1 Target Time
+ *  Low Register_
+ */
+#define EMAC_TSTARGT1    (BIT(4))
+#define EMAC_TSTARGT1_M  (EMAC_TSTARGT1_V << EMAC_TSTARGT1_S)
+#define EMAC_TSTARGT1_V  0x00000001U
+#define EMAC_TSTARGT1_S  4
+/** EMAC_TSTRGTERR1 : R/W; bitpos: [5]; default: 0;
+ *  Timestamp Target Time Error This bit is set when the target time, being programmed
+ *  in Register 480 and Register 481, is already elapsed This bit is cleared when read
+ *  by the application
+ */
+#define EMAC_TSTRGTERR1    (BIT(5))
+#define EMAC_TSTRGTERR1_M  (EMAC_TSTRGTERR1_V << EMAC_TSTRGTERR1_S)
+#define EMAC_TSTRGTERR1_V  0x00000001U
+#define EMAC_TSTRGTERR1_S  5
+/** EMAC_TSTARGT2 : R/W; bitpos: [6]; default: 0;
+ *  Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates
+ *  that the value of system time is greater than or equal to the value specified in
+ *  Register 488 _PPS2 Target Time High Register_ and Register 489 _PPS2 Target Time
+ *  Low Register_
+ */
+#define EMAC_TSTARGT2    (BIT(6))
+#define EMAC_TSTARGT2_M  (EMAC_TSTARGT2_V << EMAC_TSTARGT2_S)
+#define EMAC_TSTARGT2_V  0x00000001U
+#define EMAC_TSTARGT2_S  6
+/** EMAC_TSTRGTERR2 : R/W; bitpos: [7]; default: 0;
+ *  Timestamp Target Time Error This bit is set when the target time, being programmed
+ *  in Register 488 and Register 489, is already elapsed This bit is cleared when read
+ *  by the application
+ */
+#define EMAC_TSTRGTERR2    (BIT(7))
+#define EMAC_TSTRGTERR2_M  (EMAC_TSTRGTERR2_V << EMAC_TSTRGTERR2_S)
+#define EMAC_TSTRGTERR2_V  0x00000001U
+#define EMAC_TSTRGTERR2_S  7
+/** EMAC_TSTARGT3 : R/W; bitpos: [8]; default: 0;
+ *  Timestamp Target Time Reached for Target Time PPS3 When set, this bit indicates
+ *  that the value of system time is greater than or equal to the value specified in
+ *  Register 496 _PPS3 Target Time High Register_ and Register 497 _PPS3 Target Time
+ *  Low Register_
+ */
+#define EMAC_TSTARGT3    (BIT(8))
+#define EMAC_TSTARGT3_M  (EMAC_TSTARGT3_V << EMAC_TSTARGT3_S)
+#define EMAC_TSTARGT3_V  0x00000001U
+#define EMAC_TSTARGT3_S  8
+/** EMAC_TSTRGTERR3 : R/W; bitpos: [9]; default: 0;
+ *  Timestamp Target Time Error This bit is set when the target time, being programmed
+ *  in Register 496 and Register 497, is already elapsed This bit is cleared when read
+ *  by the application
+ */
+#define EMAC_TSTRGTERR3    (BIT(9))
+#define EMAC_TSTRGTERR3_M  (EMAC_TSTRGTERR3_V << EMAC_TSTRGTERR3_S)
+#define EMAC_TSTRGTERR3_V  0x00000001U
+#define EMAC_TSTRGTERR3_S  9
+/** EMAC_ATSSTN : R/W; bitpos: [19:16]; default: 0;
+ *  Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary
+ *  trigger inputs for which the timestamp available in the Auxiliary Snapshot Register
+ *  is applicable When more than one bit is set at the same time, it means that
+ *  corresponding auxiliary triggers were sampled at the same clock These bits are
+ *  applicable only if the number of Auxiliary snapshots is more than one One bit is
+ *  assigned for each trigger as shown in the following list: Bit 16: Auxiliary trigger
+ *  0 Bit 17: Auxiliary trigger 1 Bit 18: Auxiliary trigger 2 Bit 19: Auxiliary trigger
+ *  3 The software can read this register to find the triggers that are set when the
+ *  timestamp is taken
+ */
+#define EMAC_ATSSTN    0x0000000FU
+#define EMAC_ATSSTN_M  (EMAC_ATSSTN_V << EMAC_ATSSTN_S)
+#define EMAC_ATSSTN_V  0x0000000FU
+#define EMAC_ATSSTN_S  16
+/** EMAC_ATSSTM : RO; bitpos: [24]; default: 0;
+ *  Auxiliary Timestamp Snapshot Trigger Missed
+ */
+#define EMAC_ATSSTM    (BIT(24))
+#define EMAC_ATSSTM_M  (EMAC_ATSSTM_V << EMAC_ATSSTM_S)
+#define EMAC_ATSSTM_V  0x00000001U
+#define EMAC_ATSSTM_S  24
+/** EMAC_ATSNS : RO; bitpos: [29:25]; default: 0;
+ *  Number of Auxiliary Timestamp Snapshots This field indicates the number of
+ *  Snapshots available in the FIFO A value equal to the selected depth of FIFO _4, 8,
+ *  or 16_ indicates that the Auxiliary Snapshot FIFO is full These bits are cleared
+ *  _to 00000_ when the Auxiliary snapshot FIFO clear bit is set This bit is valid only
+ *  if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration
+ */
+#define EMAC_ATSNS    0x0000001FU
+#define EMAC_ATSNS_M  (EMAC_ATSNS_V << EMAC_ATSNS_S)
+#define EMAC_ATSNS_V  0x0000001FU
+#define EMAC_ATSNS_S  25
+
+/** EMAC_PPSCONTROL_REG register
+ *  This register is used to control the interval of the PPS signal output This
+ *  register is available only when the advanced IEEE 1588 timestamp feature is selected
+ */
+#define EMAC_PPSCONTROL_REG (DR_REG_EMAC_BASE + 0x72c)
+/** EMAC_PPSCTRL0 : R/W1S; bitpos: [3:0]; default: 0;
+ *  PPSCTRL0: PPS0 Output Frequency Control This field controls the frequency of the
+ *  PPS0 output _ptp_pps_o[0]_ signal The default value of PPSCTRL is 0000, and the PPS
+ *  output is 1 pulse _of width clk_ptp_i_ every second For other values of PPSCTRL,
+ *  the PPS output becomes a generated clock of following frequencies: 0001: The binary
+ *  rollover is 2 Hz, and the digital rollover is 1 Hz 0010: The binary rollover is 4
+ *  Hz, and the digital rollover is 2 Hz 0011: The binary rollover is 8 Hz, and the
+ *  digital rollover is 4 Hz 0100: The binary rollover is 16 Hz, and the digital
+ *  rollover is 8 Hz  1111: The binary rollover is 32768 KHz, and the digital rollover
+ *  is 16384 KHz Note: In the binary rollover mode, the PPS output _ptp_pps_o_ has a
+ *  duty cycle of 50 percent with these frequencies In the digital rollover mode, the
+ *  PPS output frequency is an average number The actual clock is of different
+ *  frequency that gets synchronized every second For example: When PPSCTRL = 0001, the
+ *  PPS _1 Hz_ has a low period of 537 ms and a high period of 463 ms When PPSCTRL =
+ *  0010, the PPS _2 Hz_ is a sequence of: 	One clock of 50 percent duty cycle and 537
+ *  ms period 	Second clock of 463 ms period _268 ms low and 195 ms high_ When PPSCTRL
+ *  = 0011, the PPS _4 Hz_ is a sequence of: 	Three clocks of 50 percent duty cycle and
+ *  268 ms period 	Fourth clock of 195 ms period _134 ms low and 61 ms high_ This
+ *  behavior is because of the nonlinear toggling of bits in the digital rollover mode
+ *  in Register 451 _System Time  Nanoseconds Register_ / PPSCMD0: Flexible PPS0 Output
+ *  _ptp_pps_o[0]_ Control Programming these bits with a nonzero value instructs the
+ *  MAC to initiate an event When the command is transferred or synchronized to the PTP
+ *  clock domain, these bits get cleared automatically The Software should ensure that
+ *  these bits are programmed only when they are “allzero” The following list describes
+ *  the values of PPSCMD0: 0000: No Command 0001: START Single Pulse This command
+ *  generates single pulse rising at the start point defined in Target Time Registers
+ *  _register 455 and 456_ and of a duration defined in the PPS0 Width Register 0010:
+ *  START Pulse Train This command generates the train of pulses rising at the start
+ *  point defined in the Target Time Registers and of a duration defined in the PPS0
+ *  Width Register and repeated at interval defined in the PPS Interval Register By
+ *  default, the PPS pulse train is freerunning unless stopped by 'STOP Pulse train at
+ *  time' or 'STOP Pulse Train immediately' commands 0011: Cancel START This command
+ *  cancels the START Single Pulse and START Pulse Train commands if the system time
+ *  has not crossed the programmed start time 0100: STOP Pulse train at time This
+ *  command stops the train of pulses initiated by the START Pulse Train command
+ *  _PPSCMD = 0010_ after the time programmed in the Target Time registers elapses
+ *  0101: STOP Pulse Train immediately This command immediately stops the train of
+ *  pulses initiated by the START Pulse Train command _PPSCMD = 0010_ 0110: Cancel STOP
+ *  Pulse train This command cancels the STOP pulse train at time command if the
+ *  programmed stop time has not elapsed The PPS pulse train becomes freerunning on the
+ *  successful execution of this command 01111111: Reserved
+ */
+#define EMAC_PPSCTRL0    0x0000000FU
+#define EMAC_PPSCTRL0_M  (EMAC_PPSCTRL0_V << EMAC_PPSCTRL0_S)
+#define EMAC_PPSCTRL0_V  0x0000000FU
+#define EMAC_PPSCTRL0_S  0
+/** EMAC_PPSEN0 : R/W; bitpos: [4]; default: 0;
+ *  Flexible PPS Output Mode Enable When set low, Bits [3:0] function as PPSCTRL
+ *  _backward compatible_ When set high, Bits[3:0] function as PPSCMD
+ */
+#define EMAC_PPSEN0    (BIT(4))
+#define EMAC_PPSEN0_M  (EMAC_PPSEN0_V << EMAC_PPSEN0_S)
+#define EMAC_PPSEN0_V  0x00000001U
+#define EMAC_PPSEN0_S  4
+/** EMAC_TRGTMODSEL0 : R/W; bitpos: [6:5]; default: 0;
+ *  Target Time Register Mode for PPS0 Output This field indicates the Target Time
+ *  registers _register 455 and 456_ mode for PPS0 output signal: 00: Indicates that
+ *  the Target Time registers are programmed only for generating the interrupt event
+ *  01: Reserved 10: Indicates that the Target Time registers are programmed for
+ *  generating the interrupt event and starting or stopping the generation of the PPS0
+ *  output signal 11: Indicates that the Target Time registers are programmed only for
+ *  starting or stopping the generation of the PPS0 output signal No interrupt is
+ *  asserted
+ */
+#define EMAC_TRGTMODSEL0    0x00000003U
+#define EMAC_TRGTMODSEL0_M  (EMAC_TRGTMODSEL0_V << EMAC_TRGTMODSEL0_S)
+#define EMAC_TRGTMODSEL0_V  0x00000003U
+#define EMAC_TRGTMODSEL0_S  5
+/** EMAC_PPSCMD1 : R/W1S; bitpos: [10:8]; default: 0;
+ *  Flexible PPS1 Output Control This field controls the flexible PPS1 output
+ *  _ptp_pps_o[1]_ signal This field is similar to PPSCMD0[2:0] in functionality
+ */
+#define EMAC_PPSCMD1    0x00000007U
+#define EMAC_PPSCMD1_M  (EMAC_PPSCMD1_V << EMAC_PPSCMD1_S)
+#define EMAC_PPSCMD1_V  0x00000007U
+#define EMAC_PPSCMD1_S  8
+/** EMAC_TRGTMODSEL1 : R/W; bitpos: [14:13]; default: 0;
+ *  Target Time Register Mode for PPS1 Output This field indicates the Target Time
+ *  registers _register 480 and 481_ mode for PPS1 output signal This field is similar
+ *  to the TRGTMODSEL0 field
+ */
+#define EMAC_TRGTMODSEL1    0x00000003U
+#define EMAC_TRGTMODSEL1_M  (EMAC_TRGTMODSEL1_V << EMAC_TRGTMODSEL1_S)
+#define EMAC_TRGTMODSEL1_V  0x00000003U
+#define EMAC_TRGTMODSEL1_S  13
+/** EMAC_PPSCMD2 : R/W1S; bitpos: [18:16]; default: 0;
+ *  Flexible PPS2 Output Control This field controls the flexible PPS2 output
+ *  _ptp_pps_o[2]_ signal This field is similar to PPSCMD0[2:0] in functionality
+ */
+#define EMAC_PPSCMD2    0x00000007U
+#define EMAC_PPSCMD2_M  (EMAC_PPSCMD2_V << EMAC_PPSCMD2_S)
+#define EMAC_PPSCMD2_V  0x00000007U
+#define EMAC_PPSCMD2_S  16
+/** EMAC_TRGTMODSEL2 : R/W; bitpos: [22:21]; default: 0;
+ *  Target Time Register Mode for PPS2 Output This field indicates the Target Time
+ *  registers _register 488 and 489_ mode for PPS2 output signal This field is similar
+ *  to the TRGTMODSEL0 field
+ */
+#define EMAC_TRGTMODSEL2    0x00000003U
+#define EMAC_TRGTMODSEL2_M  (EMAC_TRGTMODSEL2_V << EMAC_TRGTMODSEL2_S)
+#define EMAC_TRGTMODSEL2_V  0x00000003U
+#define EMAC_TRGTMODSEL2_S  21
+/** EMAC_PPSCMD3 : R/W1S; bitpos: [26:24]; default: 0;
+ *  Flexible PPS3 Output Control This field controls the flexible PPS3 output
+ *  _ptp_pps_o[3]_ signal This field is similar to PPSCMD0[2:0] in functionality
+ */
+#define EMAC_PPSCMD3    0x00000007U
+#define EMAC_PPSCMD3_M  (EMAC_PPSCMD3_V << EMAC_PPSCMD3_S)
+#define EMAC_PPSCMD3_V  0x00000007U
+#define EMAC_PPSCMD3_S  24
+/** EMAC_TRGTMODSEL3 : R/W; bitpos: [30:29]; default: 0;
+ *  Target Time Register Mode for PPS3 Output This field indicates the Target Time
+ *  registers _register 496 and 497_ mode for PPS3 output signal This field is similar
+ *  to the TRGTMODSEL0 field
+ */
+#define EMAC_TRGTMODSEL3    0x00000003U
+#define EMAC_TRGTMODSEL3_M  (EMAC_TRGTMODSEL3_V << EMAC_TRGTMODSEL3_S)
+#define EMAC_TRGTMODSEL3_V  0x00000003U
+#define EMAC_TRGTMODSEL3_S  29
+
+/** EMAC_AUXILIARYTIMESTAMPNANOSECONDS_REG register
+ *  Contains the lower 32 bits _nanoseconds field_ of the auxiliary timestamp register
+ */
+#define EMAC_AUXILIARYTIMESTAMPNANOSECONDS_REG (DR_REG_EMAC_BASE + 0x730)
+/** EMAC_AUXTSLO : RO; bitpos: [30:0]; default: 0;
+ *  Contains the lower 31 bits _nanoseconds field_ of the auxiliary timestamp
+ */
+#define EMAC_AUXTSLO    0x7FFFFFFFU
+#define EMAC_AUXTSLO_M  (EMAC_AUXTSLO_V << EMAC_AUXTSLO_S)
+#define EMAC_AUXTSLO_V  0x7FFFFFFFU
+#define EMAC_AUXTSLO_S  0
+
+/** EMAC_AUXILIARYTIMESTAMPSECONDS_REG register
+ *  Contains the lower 32 bits of the Seconds field of the auxiliary timestamp register
+ */
+#define EMAC_AUXILIARYTIMESTAMPSECONDS_REG (DR_REG_EMAC_BASE + 0x734)
+/** EMAC_AUXTSHI : RO; bitpos: [31:0]; default: 0;
+ *  Contains the lower 32 bits of the Seconds field of the auxiliary timestamp
+ */
+#define EMAC_AUXTSHI    0xFFFFFFFFU
+#define EMAC_AUXTSHI_M  (EMAC_AUXTSHI_V << EMAC_AUXTSHI_S)
+#define EMAC_AUXTSHI_V  0xFFFFFFFFU
+#define EMAC_AUXTSHI_S  0
+
+/** EMAC_AVMACCONTROL_REG register
+ *  Controls the AV traffic and queue management in the MAC Receiver This register is
+ *  present only when you select the AV feature in coreConsultant
+ */
+#define EMAC_AVMACCONTROL_REG (DR_REG_EMAC_BASE + 0x738)
+/** EMAC_AVT : R/W; bitpos: [15:0]; default: 0;
+ *  AV EtherType Value This field contains the value that is compared with the
+ *  EtherType field of the incoming _tagged or untagged_ Ethernet frame to detect an AV
+ *  packet
+ */
+#define EMAC_AVT    0x0000FFFFU
+#define EMAC_AVT_M  (EMAC_AVT_V << EMAC_AVT_S)
+#define EMAC_AVT_V  0x0000FFFFU
+#define EMAC_AVT_S  0
+/** EMAC_AVP : R/W; bitpos: [18:16]; default: 0;
+ *  AV Priority for Queuing The value programmed in these bits control the receive
+ *  channel _0, 1, or 2_ to which an AV packet with a given priority must be queued If
+ *  only Channel 1 receive path is enabled, the AV packets with priority value greater
+ *  than or equal to the programmed value are queued on Channel 1 and all other packets
+ *  are queued on Channel 0 If Channel 2 receive path is also enabled, the AV packets
+ *  with priority value greater than or equal to the programmed value are queued on
+ *  Channel 2 The AV packets with value less than the programmed value on Channel 1 and
+ *  all other packets are queued on Channel 0 These bits are applicable only if at
+ *  least one additional receive channel is selected in the AV mode
+ */
+#define EMAC_AVP    0x00000007U
+#define EMAC_AVP_M  (EMAC_AVP_V << EMAC_AVP_S)
+#define EMAC_AVP_V  0x00000007U
+#define EMAC_AVP_S  16
+/** EMAC_VQE : R/W; bitpos: [19]; default: 0;
+ *  VLAN Tagged NonAV Packets Queueing Enable When this bit is set, the MAC also queues
+ *  nonAV VLAN tagged packets into the available channels according to the value of the
+ *  AVP bits This bit is reserved and readonly if Channel 1 and Channel 2 Receive paths
+ *  are not selected during core configuration
+ */
+#define EMAC_VQE    (BIT(19))
+#define EMAC_VQE_M  (EMAC_VQE_V << EMAC_VQE_S)
+#define EMAC_VQE_V  0x00000001U
+#define EMAC_VQE_S  19
+/** EMAC_AVCD : R/W; bitpos: [20]; default: 0;
+ *  AV Channel Disable When this bit is set, the MAC forwards all packets to the
+ *  default Channel 0 and the values programmed in the AVP, AVCH, and PTPCH fields are
+ *  ignored This bit is reserved and readonly if Channel 1 or Channel 2 receive paths
+ *  are not selected during core configuration
+ */
+#define EMAC_AVCD    (BIT(20))
+#define EMAC_AVCD_M  (EMAC_AVCD_V << EMAC_AVCD_S)
+#define EMAC_AVCD_V  0x00000001U
+#define EMAC_AVCD_S  20
+/** EMAC_AVCH : R/W; bitpos: [22:21]; default: 0;
+ *  Channel for Queuing the AV Control Packets This field specifies the channel on
+ *  which the received untagged AV control packets are queued 00: Channel 0 01: Channel
+ *  1 10: Channel 2 11: Reserved These bits are reserved if the receive paths of
+ *  Channel 1 or Channel 2 are not enabled
+ */
+#define EMAC_AVCH    0x00000003U
+#define EMAC_AVCH_M  (EMAC_AVCH_V << EMAC_AVCH_S)
+#define EMAC_AVCH_V  0x00000003U
+#define EMAC_AVCH_S  21
+/** EMAC_PTPCH : R/W; bitpos: [25:24]; default: 0;
+ *  Channel for Queuing the PTP Packets This field specifies the channel on which the
+ *  untagged PTP packets, sent over the Ethernet payload and not over IPv4 or IPv6, are
+ *  queued 00: Channel 0 01: Channel 1 10: Channel 2 11: Reserved These bits are
+ *  reserved if the receive paths of Channel 1 or Channel 2 are not enabled
+ */
+#define EMAC_PTPCH    0x00000003U
+#define EMAC_PTPCH_M  (EMAC_PTPCH_V << EMAC_PTPCH_S)
+#define EMAC_PTPCH_V  0x00000003U
+#define EMAC_PTPCH_S  24
+
+/** EMAC_PPS0INTERVAL_REG register
+ *  Contains the number of units of subsecond increment value between the rising edges
+ *  of PPS0 signal output This register is available only when the flexible PPS feature
+ *  is selected
+ */
+#define EMAC_PPS0INTERVAL_REG (DR_REG_EMAC_BASE + 0x760)
+/** EMAC_PPSINT : R/W; bitpos: [31:0]; default: 0;
+ *  PPS0 Output Signal Interval These bits store the interval between the rising edges
+ *  of PPS0 signal output in terms of units of subsecond increment value You need to
+ *  program one value less than the required interval For example, if the PTP reference
+ *  clock is 50 MHz _period of 20ns_, and desired interval between rising edges of PPS0
+ *  signal output is 100ns _that is, five units of subsecond increment value_, then you
+ *  should program value 4 _5  1_ in this register
+ */
+#define EMAC_PPSINT    0xFFFFFFFFU
+#define EMAC_PPSINT_M  (EMAC_PPSINT_V << EMAC_PPSINT_S)
+#define EMAC_PPSINT_V  0xFFFFFFFFU
+#define EMAC_PPSINT_S  0
+
+/** EMAC_PPS0WIDTH_REG register
+ *  Contains the number of units of subsecond increment value between the rising and
+ *  corresponding falling edges of PPS0 signal output This register is available only
+ *  when the flexible PPS feature is selected
+ */
+#define EMAC_PPS0WIDTH_REG (DR_REG_EMAC_BASE + 0x764)
+/** EMAC_PPSWIDTH : R/W; bitpos: [31:0]; default: 0;
+ *  PPS0 Output Signal Width These bits store the width between the rising edge and
+ *  corresponding falling edge of the PPS0 signal output in terms of units of subsecond
+ *  increment value You need to program one value less than the required interval For
+ *  example, if PTP reference clock is 50 MHz _period of 20ns_, and desired width
+ *  between the rising and corresponding falling edges of PPS0 signal output is 80ns
+ *  _that is, four units of subsecond increment value_, then you should program value 3
+ *  _4  1_ in this register Note: The value programmed in this register must be lesser
+ *  than the value programmed in Register 472 _PPS0 Interval Register_
+ */
+#define EMAC_PPSWIDTH    0xFFFFFFFFU
+#define EMAC_PPSWIDTH_M  (EMAC_PPSWIDTH_V << EMAC_PPSWIDTH_S)
+#define EMAC_PPSWIDTH_V  0xFFFFFFFFU
+#define EMAC_PPSWIDTH_S  0
+
+/** EMAC_PPS1TARGETTIMESECONDS_REG register
+ *  Contains the higher 32 bits of time to be compared with the system time to generate
+ *  the interrupt event or to start generating the PPS1 output signal This register is
+ *  present only when IEEE1588 timestamping is enabled without an external timestamp
+ *  input and at least one additional PPS output is selected
+ */
+#define EMAC_PPS1TARGETTIMESECONDS_REG (DR_REG_EMAC_BASE + 0x780)
+/** EMAC_TSTRH1 : R/W; bitpos: [31:0]; default: 0;
+ *  PPS1 Target Time Seconds Register This register stores the time in seconds When the
+ *  timestamp value matches or exceeds both Target Timestamp registers, then based on
+ *  Bits [14:13], TRGTMODSEL1, of Register 459 _PPS Control Register_, the MAC starts
+ *  or stops the PPS signal output and generates an interrupt _if enabled_
+ */
+#define EMAC_TSTRH1    0xFFFFFFFFU
+#define EMAC_TSTRH1_M  (EMAC_TSTRH1_V << EMAC_TSTRH1_S)
+#define EMAC_TSTRH1_V  0xFFFFFFFFU
+#define EMAC_TSTRH1_S  0
+
+/** EMAC_PPS1TARGETTIMENANOSECONDS_REG register
+ *  Contains the lower 32 bits of time to be compared with the system time to generate
+ *  the interrupt event or to start generating the PPS1 output signal This register is
+ *  present only when IEEE1588 timestamping is enabled without an external timestamp
+ *  input and at least one additional PPS output is selected
+ */
+#define EMAC_PPS1TARGETTIMENANOSECONDS_REG (DR_REG_EMAC_BASE + 0x784)
+/** EMAC_TTSL1 : R/W; bitpos: [30:0]; default: 0;
+ *  Target Time Low for PPS1 Register This register stores the time in _signed_
+ *  nanoseconds When the value of the timestamp matches the both Target Timestamp
+ *  registers, then based on the TRGTMODSEL1 field _Bits [14:13]_ in Register 459 _PPS
+ *  Control Register_, the MAC starts or stops the PPS signal output and generates an
+ *  interrupt _if enabled_ This value should not exceed 0x3B9A_C9FF when Bit 9
+ *  _TSCTRLSSR_ is set in Register 448 _Timestamp Control Register_ The actual start or
+ *  stop time of the PPS signal output may have an error margin up to one unit of
+ *  subsecond increment value
+ */
+#define EMAC_TTSL1    0x7FFFFFFFU
+#define EMAC_TTSL1_M  (EMAC_TTSL1_V << EMAC_TTSL1_S)
+#define EMAC_TTSL1_V  0x7FFFFFFFU
+#define EMAC_TTSL1_S  0
+/** EMAC_TRGTBUSY1 : R/W1S; bitpos: [31]; default: 0;
+ *  PPS1 Target Time Register Busy The MAC sets this bit when the PPSCMD1 field _Bits
+ *  [10:8]_ in Register 459 _PPS Control Register_ is programmed to 010 or 011
+ *  Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the
+ *  Target Time Registers to the PTP clock domain The MAC clears this bit after
+ *  synchronizing the Target Time Registers to the PTP clock domain The application
+ *  must not update the Target Time Registers when this bit is read as 1 Otherwise, the
+ *  synchronization of the previous programmed time gets corrupted
+ */
+#define EMAC_TRGTBUSY1    (BIT(31))
+#define EMAC_TRGTBUSY1_M  (EMAC_TRGTBUSY1_V << EMAC_TRGTBUSY1_S)
+#define EMAC_TRGTBUSY1_V  0x00000001U
+#define EMAC_TRGTBUSY1_S  31
+
+/** EMAC_MACADDRESS32HIGH_REG register
+ *  Contains the higher 16 bits of the 33rd MAC address This register is present only
+ *  when Enable Additional 32 MAC Address Registers is selected in coreConsultant _See
+ *  Table 78_
+ */
+#define EMAC_MACADDRESS32HIGH_REG (DR_REG_EMAC_BASE + 0x880)
+/** EMAC_ADDRHI : R/W; bitpos: [15:0]; default: 65535;
+ *  MAC Address32 [47:32] This field contains the upper 16 bits _47:32_ of the 33rd
+ *  6byte MAC address
+ */
+#define EMAC_ADDRHI    0x0000FFFFU
+#define EMAC_ADDRHI_M  (EMAC_ADDRHI_V << EMAC_ADDRHI_S)
+#define EMAC_ADDRHI_V  0x0000FFFFU
+#define EMAC_ADDRHI_S  0
+/** EMAC_AE : R/W; bitpos: [31]; default: 0;
+ *  Address Enable When this bit is set, the Address filter module uses the 33rd MAC
+ *  address for perfect filtering When reset, the address filter module ignores the
+ *  address for filtering
+ */
+#define EMAC_AE    (BIT(31))
+#define EMAC_AE_M  (EMAC_AE_V << EMAC_AE_S)
+#define EMAC_AE_V  0x00000001U
+#define EMAC_AE_S  31
+
+/** EMAC_BUSMODE_REG register
+ *  Controls the Host Interface Mode
+ */
+#define EMAC_BUSMODE_REG (DR_REG_EMAC_BASE + 0x1000)
+/** EMAC_SWR : R/W1S_SC; bitpos: [0]; default: 1;
+ *  Software Reset When this bit is set, the MAC DMA Controller resets the logic and
+ *  all internal registers of the MAC It is cleared automatically after the reset
+ *  operation is complete in all of the DWC_EMAC clock domains Before reprogramming any
+ *  register of the DWC_EMAC, you should read a zero _0_ value in this bit Note: The
+ *  Software reset function is driven only by this bit Bit 0 of Register 64 _Channel 1
+ *  Bus Mode Register_ or Register 128 _Channel 2 Bus Mode Register_ has no impact on
+ *  the Software reset function The reset operation is completed only when all resets
+ *  in all active clock domains are deasserted Therefore, it is essential that all PHY
+ *  inputs clocks _applicable for the selected PHY interface_ are present for the
+ *  software reset completion The time to complete the software reset operation depends
+ *  on the frequency of the slowest active clock
+ */
+#define EMAC_SWR    (BIT(0))
+#define EMAC_SWR_M  (EMAC_SWR_V << EMAC_SWR_S)
+#define EMAC_SWR_V  0x00000001U
+#define EMAC_SWR_S  0
+/** EMAC_DA : R/W; bitpos: [1]; default: 0;
+ *  DMA Arbitration Scheme This bit specifies the arbitration scheme between the
+ *  transmit and receive paths of Channel 0 0: Weighted roundrobin with Rx:Tx or Tx:Rx
+ *  The priority between the paths is according to the priority specified in Bits
+ *  [15:14] _PR_ and priority weights specified in Bit 27 _TXPR_ 1: Fixed priority The
+ *  transmit path has priority over receive path when Bit 27 _TXPR_ is set Otherwise,
+ *  receive path has priority over the transmit path In the EMACAXI configuration,
+ *  these bits are reserved and are readonly _RO_ For more information about the
+ *  priority scheme between the transmit and receive paths, see Table 412 in “DMA
+ *  Arbiter Functions” on page 167
+ */
+#define EMAC_DA    (BIT(1))
+#define EMAC_DA_M  (EMAC_DA_V << EMAC_DA_S)
+#define EMAC_DA_V  0x00000001U
+#define EMAC_DA_S  1
+/** EMAC_DSL : R/W; bitpos: [6:2]; default: 0;
+ *  Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword
+ *  _depending on the 32bit, 64bit, or 128bit bus_ to skip between two unchained
+ *  descriptors The address skipping starts from the end of current descriptor to the
+ *  start of next descriptor When the DSL value is equal to zero, the descriptor table
+ *  is taken as contiguous by the DMA in Ring mode
+ */
+#define EMAC_DSL    0x0000001FU
+#define EMAC_DSL_M  (EMAC_DSL_V << EMAC_DSL_S)
+#define EMAC_DSL_V  0x0000001FU
+#define EMAC_DSL_S  2
+/** EMAC_ATDS : R/W; bitpos: [7]; default: 0;
+ *  Alternate Descriptor Size When set, the size of the alternate descriptor _described
+ *  in “Alternate or Enhanced Descriptors” on page 545_ increases to 32 bytes _8
+ *  DWORDS_ This is required when the Advanced Timestamp feature or the IPC Full
+ *  Checksum Offload Engine _Type 2_ is enabled in the receiver The enhanced descriptor
+ *  is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine
+ *  _Type 2_ features are not enabled In such case, you can use the 16 bytes descriptor
+ *  to save 4 bytes of memory This bit is present only when you select the Alternate
+ *  Descriptor feature and any one of the following features during core configuration:
+ *  Advanced Timestamp feature IPC Full Checksum Offload Engine _Type 2_ feature
+ *  Otherwise, this bit is reserved and is readonly When reset, the descriptor size
+ *  reverts back to 4 DWORDs _16 bytes_ This bit preserves the backward compatibility
+ *  for the descriptor size In versions prior to 350a, the descriptor size is 16 bytes
+ *  for both normal and enhanced descriptors In version 350a, descriptor size is
+ *  increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum
+ *  Offload Engine _Type 2_ features
+ */
+#define EMAC_ATDS    (BIT(7))
+#define EMAC_ATDS_M  (EMAC_ATDS_V << EMAC_ATDS_S)
+#define EMAC_ATDS_V  0x00000001U
+#define EMAC_ATDS_S  7
+/** EMAC_PBL : R/W; bitpos: [13:8]; default: 1;
+ *  Programmable Burst Length These bits indicate the maximum number of beats to be
+ *  transferred in one DMA transaction This is the maximum value that is used in a
+ *  single block Read or Write The DMA always attempts to burst as specified in PBL
+ *  each time it starts a Burst transfer on the host bus PBL can be programmed with
+ *  permissible values of 1, 2, 4, 8, 16, and 32 Any other value results in undefined
+ *  behavior When USP is set high, this PBL value is applicable only for Tx DMA
+ *  transactions If the number of beats to be transferred is more than 32, then perform
+ *  the following steps: 1 Set the PBLx8 mode 2 Set the PBL For example, if the maximum
+ *  number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL
+ *  to 8 The PBL values have the following limitation: The maximum number of possible
+ *  beats _PBL_ is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and
+ *  the data bus width on the DMA The FIFO has a constraint that the maximum beat
+ *  supported is half the depth of the FIFO, except when specified For different data
+ *  bus widths and FIFO sizes, the valid PBL range _including x8 mode_ is provided in
+ *  Table 66 on page 382
+ */
+#define EMAC_PBL    0x0000003FU
+#define EMAC_PBL_M  (EMAC_PBL_V << EMAC_PBL_S)
+#define EMAC_PBL_V  0x0000003FU
+#define EMAC_PBL_S  8
+/** EMAC_PR : R/W; bitpos: [15:14]; default: 0;
+ *  Priority Ratio These bits control the priority ratio in the weighted roundrobin
+ *  arbitration between the Rx DMA and Tx DMA These bits are valid only when Bit 1 _DA_
+ *  is reset The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 _TXPR_ is
+ *  reset or set 00: The Priority Ratio is 1:1 01: The Priority Ratio is 2:1 10: The
+ *  Priority Ratio is 3:1 11: The Priority Ratio is 4:1 In the EMACAXI configuration,
+ *  these bits are reserved and readonly _RO_ For more information about the priority
+ *  scheme between the transmit and receive paths, see Table 412 in “DMA Arbiter
+ *  Functions” on page 167
+ */
+#define EMAC_PR    0x00000003U
+#define EMAC_PR_M  (EMAC_PR_V << EMAC_PR_S)
+#define EMAC_PR_V  0x00000003U
+#define EMAC_PR_S  14
+/** EMAC_FB : R/W; bitpos: [16]; default: 0;
+ *  Fixed Burst This bit controls whether the AHB or AXI master interface performs
+ *  fixed burst transfers or not When set, the AHB interface uses only SINGLE, INCR4,
+ *  INCR8, or INCR16 during start of the normal burst transfers When reset, the AHB or
+ *  AXI interface uses SINGLE and INCR burst transfer operations For more information,
+ *  see Bit 0 _UNDEF_ of the AXI Bus Mode register in the EMACAXI configuration
+ */
+#define EMAC_FB    (BIT(16))
+#define EMAC_FB_M  (EMAC_FB_V << EMAC_FB_S)
+#define EMAC_FB_V  0x00000001U
+#define EMAC_FB_S  16
+/** EMAC_RPBL : R/W; bitpos: [22:17]; default: 1;
+ *  Rx DMA PBL This field indicates the maximum number of beats to be transferred in
+ *  one Rx DMA transaction This is the maximum value that is used in a single block
+ *  Read or Write The Rx DMA always attempts to burst as specified in the RPBL bit each
+ *  time it starts a Burst transfer on the host bus You can program RPBL with values of
+ *  1, 2, 4, 8, 16, and 32 Any other value results in undefined behavior This field is
+ *  valid and applicable only when USP is set high
+ */
+#define EMAC_RPBL    0x0000003FU
+#define EMAC_RPBL_M  (EMAC_RPBL_V << EMAC_RPBL_S)
+#define EMAC_RPBL_V  0x0000003FU
+#define EMAC_RPBL_S  17
+/** EMAC_USP : R/W; bitpos: [23]; default: 0;
+ *  Use Separate PBL When set high, this bit configures the Rx DMA to use the value
+ *  configured in Bits [22:17] as PBL The PBL value in Bits [13:8] is applicable only
+ *  to the Tx DMA operations When reset to low, the PBL value in Bits [13:8] is
+ *  applicable for both DMA engines
+ */
+#define EMAC_USP    (BIT(23))
+#define EMAC_USP_M  (EMAC_USP_V << EMAC_USP_S)
+#define EMAC_USP_V  0x00000001U
+#define EMAC_USP_S  23
+/** EMAC_PBLX8 : R/W; bitpos: [24]; default: 0;
+ *  PBLx8 Mode When set high, this bit multiplies the programmed PBL value _Bits
+ *  [22:17] and Bits[13:8]_ eight times Therefore, the DMA transfers the data in 8, 16,
+ *  32, 64, 128, and 256 beats depending on the PBL value Note: This bit function is
+ *  not backward compatible Before release 350a, this bit was 4xPBL
+ */
+#define EMAC_PBLX8    (BIT(24))
+#define EMAC_PBLX8_M  (EMAC_PBLX8_V << EMAC_PBLX8_S)
+#define EMAC_PBLX8_V  0x00000001U
+#define EMAC_PBLX8_S  24
+/** EMAC_AAL : R/W; bitpos: [25]; default: 0;
+ *  AddressAligned Beats When this bit is set high and the FB bit is equal to 1, the
+ *  AHB or AXI interface generates all bursts aligned to the start address LS bits If
+ *  the FB bit is equal to 0, the first burst _accessing the start address of data
+ *  buffer_ is not aligned, but subsequent bursts are aligned to the address This bit
+ *  is valid only in the EMACAHB and EMACAXI configurations and is reserved _RO with
+ *  default value 0_ in all other configurations
+ */
+#define EMAC_AAL    (BIT(25))
+#define EMAC_AAL_M  (EMAC_AAL_V << EMAC_AAL_S)
+#define EMAC_AAL_V  0x00000001U
+#define EMAC_AAL_S  25
+/** EMAC_MB : R/W; bitpos: [26]; default: 0;
+ *  Mixed Burst When this bit is set high and the FB bit is low, the AHB master
+ *  interface starts all bursts of length more than 16 with INCR _undefined burst_,
+ *  whereas it reverts to fixed burst transfers _INCRx and SINGLE_ for burst length of
+ *  16 and less This bit is valid only in the EMACAHB configuration and reserved in all
+ *  other configuration
+ */
+#define EMAC_MB    (BIT(26))
+#define EMAC_MB_M  (EMAC_MB_V << EMAC_MB_S)
+#define EMAC_MB_V  0x00000001U
+#define EMAC_MB_S  26
+/** EMAC_TXPR : R/W; bitpos: [27]; default: 0;
+ *  Transmit Priority When set, this bit indicates that the transmit DMA has higher
+ *  priority than the receive DMA during arbitration for the systemside bus In the
+ *  EMACAXI configuration, this bit is reserved and readonly _RO_ For more information
+ *  about the priority scheme between the transmit and receive paths, see Table 412 in
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define EMAC_TXPR    (BIT(27))
+#define EMAC_TXPR_M  (EMAC_TXPR_V << EMAC_TXPR_S)
+#define EMAC_TXPR_V  0x00000001U
+#define EMAC_TXPR_S  27
+/** EMAC_PRWG : R/W; bitpos: [29:28]; default: 0;
+ *  Channel Priority Weights This field sets the priority weights for Channel 0 during
+ *  the roundrobin arbitration between the DMA channels for the system bus 00: The
+ *  priority weight is 1 01: The priority weight is 2 10: The priority weight is 3 11:
+ *  The priority weight is 4 This field is present in all DWC_EMAC configurations
+ *  except EMACAXI when you select the AV feature Otherwise, this field is reserved and
+ *  readonly _RO_ For more information about the priority weights of DMA channels, see
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define EMAC_PRWG    0x00000003U
+#define EMAC_PRWG_M  (EMAC_PRWG_V << EMAC_PRWG_S)
+#define EMAC_PRWG_V  0x00000003U
+#define EMAC_PRWG_S  28
+/** EMAC_RIB : R/W; bitpos: [31]; default: 0;
+ *  Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT
+ *  _Retry, Split, or Losing bus grant_, the AHB master interface rebuilds the pending
+ *  beats of any burst transfer initiated with INCRx The AHB master interface rebuilds
+ *  the beats with a combination of specified bursts with INCRx and SINGLE By default,
+ *  the AHB master interface rebuilds pending beats of an EBT with an unspecified
+ *  _INCR_ burst This bit is valid only in the EMACAHB configuration It is reserved in
+ *  all other configuration
+ */
+#define EMAC_RIB    (BIT(31))
+#define EMAC_RIB_M  (EMAC_RIB_V << EMAC_RIB_S)
+#define EMAC_RIB_V  0x00000001U
+#define EMAC_RIB_S  31
+
+/** EMAC_TRANSMITPOLLDEMAND_REG register
+ *  Used by the host to instruct the DMA to poll the Transmit Descriptor list
+ */
+#define EMAC_TRANSMITPOLLDEMAND_REG (DR_REG_EMAC_BASE + 0x1004)
+/** EMAC_TPD : RO; bitpos: [31:0]; default: 0;
+ *  Transmit Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 18 _Current Host Transmit Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  transmission returns to the Suspend state and Bit 2 _TU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the transmission resumes
+ */
+#define EMAC_TPD    0xFFFFFFFFU
+#define EMAC_TPD_M  (EMAC_TPD_V << EMAC_TPD_S)
+#define EMAC_TPD_V  0xFFFFFFFFU
+#define EMAC_TPD_S  0
+
+/** EMAC_RECEIVEPOLLDEMAND_REG register
+ *  Used by the host to instruct the DMA to poll the Receive Descriptor list
+ */
+#define EMAC_RECEIVEPOLLDEMAND_REG (DR_REG_EMAC_BASE + 0x1008)
+/** EMAC_RPD : RO; bitpos: [31:0]; default: 0;
+ *  Receive Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 19 _Current Host Receive Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  reception returns to the Suspended state and Bit 7 _RU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the Rx DMA returns to the
+ *  active state
+ */
+#define EMAC_RPD    0xFFFFFFFFU
+#define EMAC_RPD_M  (EMAC_RPD_V << EMAC_RPD_S)
+#define EMAC_RPD_V  0xFFFFFFFFU
+#define EMAC_RPD_S  0
+
+/** EMAC_RECEIVEDESCRIPTORLISTADDRESS_REG register
+ *  Points the DMA to the start of the Receive Descriptor list
+ */
+#define EMAC_RECEIVEDESCRIPTORLISTADDRESS_REG (DR_REG_EMAC_BASE + 0x100c)
+/** EMAC_RDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Receive List This field contains the base address of the first descriptor
+ *  in the Receive Descriptor list The LSB bits _1:0, 2:0, or 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and internally taken as allzero by the DMA Therefore,
+ *  these LSB bits are readonly _RO_
+ */
+#define EMAC_RDESLA    0xFFFFFFFFU
+#define EMAC_RDESLA_M  (EMAC_RDESLA_V << EMAC_RDESLA_S)
+#define EMAC_RDESLA_V  0xFFFFFFFFU
+#define EMAC_RDESLA_S  0
+
+/** EMAC_TRANSMITDESCRIPTORLISTADDRESS_REG register
+ *  Points the DMA to the start of the Transmit Descriptor list
+ */
+#define EMAC_TRANSMITDESCRIPTORLISTADDRESS_REG (DR_REG_EMAC_BASE + 0x1010)
+/** EMAC_TDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Transmit List This field contains the base address of the first descriptor
+ *  in the Transmit Descriptor list The LSB bits _1:0, 2:0, 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and are internally taken as allzero by the DMA
+ *  Therefore, these LSB bits are readonly _RO_
+ */
+#define EMAC_TDESLA    0xFFFFFFFFU
+#define EMAC_TDESLA_M  (EMAC_TDESLA_V << EMAC_TDESLA_S)
+#define EMAC_TDESLA_V  0xFFFFFFFFU
+#define EMAC_TDESLA_S  0
+
+/** EMAC_STATUS_REG register
+ *  The Software driver _application_ reads this register during interrupt service
+ *  routine or polling to determine the status of the DMA
+ */
+#define EMAC_STATUS_REG (DR_REG_EMAC_BASE + 0x1014)
+/** EMAC_TI : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt This bit indicates that the frame transmission is complete When
+ *  transmission is complete, Bit 31 _OWN_ of TDES0 is reset, and the specific frame
+ *  status information is updated in the descriptor
+ */
+#define EMAC_TI    (BIT(0))
+#define EMAC_TI_M  (EMAC_TI_V << EMAC_TI_S)
+#define EMAC_TI_V  0x00000001U
+#define EMAC_TI_S  0
+/** EMAC_TPS : R/W; bitpos: [1]; default: 0;
+ *  Transmit Process Stopped This bit is set when the transmission is stopped
+ */
+#define EMAC_TPS    (BIT(1))
+#define EMAC_TPS_M  (EMAC_TPS_V << EMAC_TPS_S)
+#define EMAC_TPS_V  0x00000001U
+#define EMAC_TPS_S  1
+/** EMAC_TU : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Transmit List and the DMA cannot acquire it Transmission is
+ *  suspended Bits[22:20] explain the Transmit Process state transitions To resume
+ *  processing Transmit descriptors, the host should change the ownership of the
+ *  descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command
+ */
+#define EMAC_TU    (BIT(2))
+#define EMAC_TU_M  (EMAC_TU_V << EMAC_TU_S)
+#define EMAC_TU_V  0x00000001U
+#define EMAC_TU_S  2
+/** EMAC_TJT : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired,
+ *  which happens when the frame size exceeds 2,048 _10,240 bytes when the Jumbo frame
+ *  is enabled_ When the Jabber Timeout occurs, the transmission process is aborted and
+ *  placed in the Stopped state This causes the Transmit Jabber Timeout TDES0[14] flag
+ *  to assert
+ */
+#define EMAC_TJT    (BIT(3))
+#define EMAC_TJT_M  (EMAC_TJT_V << EMAC_TJT_S)
+#define EMAC_TJT_V  0x00000001U
+#define EMAC_TJT_S  3
+/** EMAC_OVF : R/W; bitpos: [4]; default: 0;
+ *  Receive Overflow This bit indicates that the Receive Buffer had an Overflow during
+ *  frame reception If the partial frame is transferred to the application, the
+ *  overflow status is set in RDES0[11]
+ */
+#define EMAC_OVF    (BIT(4))
+#define EMAC_OVF_M  (EMAC_OVF_V << EMAC_OVF_S)
+#define EMAC_OVF_V  0x00000001U
+#define EMAC_OVF_S  4
+/** EMAC_UNF : R/W; bitpos: [5]; default: 0;
+ *  Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow
+ *  during frame transmission Transmission is suspended and an Underflow Error TDES0[1]
+ *  is set
+ */
+#define EMAC_UNF    (BIT(5))
+#define EMAC_UNF_M  (EMAC_UNF_V << EMAC_UNF_S)
+#define EMAC_UNF_V  0x00000001U
+#define EMAC_UNF_S  5
+/** EMAC_RI : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt This bit indicates that the frame reception is complete When
+ *  reception is complete, the Bit 31 of RDES1 _Disable Interrupt on Completion_ is
+ *  reset in the last Descriptor, and the specific frame status information is updated
+ *  in the descriptor The reception remains in the Running state
+ */
+#define EMAC_RI    (BIT(6))
+#define EMAC_RI_M  (EMAC_RI_V << EMAC_RI_S)
+#define EMAC_RI_V  0x00000001U
+#define EMAC_RI_S  6
+/** EMAC_RU : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Receive List and the DMA cannot acquire it The Receive Process is
+ *  suspended To resume processing Receive descriptors, the host should change the
+ *  ownership of the descriptor and issue a Receive Poll Demand command If no Receive
+ *  Poll Demand is issued, the Receive Process resumes when the next recognized
+ *  incoming frame is received This bit is set only when the previous Receive
+ *  Descriptor is owned by the DMA
+ */
+#define EMAC_RU    (BIT(7))
+#define EMAC_RU_M  (EMAC_RU_V << EMAC_RU_S)
+#define EMAC_RU_V  0x00000001U
+#define EMAC_RU_S  7
+/** EMAC_RPS : R/W; bitpos: [8]; default: 0;
+ *  Receive Process Stopped This bit is asserted when the Receive Process enters the
+ *  Stopped state
+ */
+#define EMAC_RPS    (BIT(8))
+#define EMAC_RPS_M  (EMAC_RPS_V << EMAC_RPS_S)
+#define EMAC_RPS_V  0x00000001U
+#define EMAC_RPS_S  8
+/** EMAC_RWT : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog
+ *  Timer expired while receiving the current frame and the current frame is truncated
+ *  after the watchdog timeout
+ */
+#define EMAC_RWT    (BIT(9))
+#define EMAC_RWT_M  (EMAC_RWT_V << EMAC_RWT_S)
+#define EMAC_RWT_V  0x00000001U
+#define EMAC_RWT_S  9
+/** EMAC_ETI : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt This bit indicates that the frame to be transmitted is
+ *  fully transferred to the MTL Transmit FIFO
+ */
+#define EMAC_ETI    (BIT(10))
+#define EMAC_ETI_M  (EMAC_ETI_V << EMAC_ETI_S)
+#define EMAC_ETI_V  0x00000001U
+#define EMAC_ETI_S  10
+/** EMAC_FBI : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as
+ *  described in Bits [25:23] When this bit is set, the corresponding DMA engine
+ *  disables all of its bus accesses 12:11		Reserved	00	RO
+ */
+#define EMAC_FBI    (BIT(13))
+#define EMAC_FBI_M  (EMAC_FBI_V << EMAC_FBI_S)
+#define EMAC_FBI_V  0x00000001U
+#define EMAC_FBI_S  13
+/** EMAC_ERI : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt This bit indicates that the DMA filled the first data
+ *  buffer of the packet This bit is cleared when the software writes 1 to this bit or
+ *  Bit 6 _RI_ of this register is set _whichever occurs earlier_
+ */
+#define EMAC_ERI    (BIT(14))
+#define EMAC_ERI_M  (EMAC_ERI_V << EMAC_ERI_S)
+#define EMAC_ERI_V  0x00000001U
+#define EMAC_ERI_S  14
+/** EMAC_AIS : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR
+ *  of the following when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[1]: Transmit Process Stopped Register 5[3]:
+ *  Transmit Jabber Timeout Register 5[4]: Receive FIFO Overflow Register 5[5]:
+ *  Transmit Underflow Register 5[7]: Receive Buffer Unavailable Register 5[8]: Receive
+ *  Process Stopped Register 5[9]: Receive Watchdog Timeout Register 5[10]: Early
+ *  Transmit Interrupt Register 5[13]: Fatal Bus Error Only unmasked bits affect the
+ *  Abnormal Interrupt Summary bit This is a sticky bit and must be cleared _by writing
+ *  1 to this bit_ each time a corresponding bit, which causes AIS to be set, is cleared
+ */
+#define EMAC_AIS    (BIT(15))
+#define EMAC_AIS_M  (EMAC_AIS_V << EMAC_AIS_S)
+#define EMAC_AIS_V  0x00000001U
+#define EMAC_AIS_S  15
+/** EMAC_NIS : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of
+ *  the following bits when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[0]: Transmit Interrupt Register 5[2]:
+ *  Transmit Buffer Unavailable Register 5[6]: Receive Interrupt Register 5[14]: Early
+ *  Receive Interrupt Only unmasked bits _interrupts for which interrupt enable is set
+ *  in Register 7_ affect the Normal Interrupt Summary bit This is a sticky bit and
+ *  must be cleared _by writing 1 to this bit_ each time a corresponding bit, which
+ *  causes NIS to be set, is cleared
+ */
+#define EMAC_NIS    (BIT(16))
+#define EMAC_NIS_M  (EMAC_NIS_V << EMAC_NIS_S)
+#define EMAC_NIS_V  0x00000001U
+#define EMAC_NIS_S  16
+/** EMAC_RS : RO; bitpos: [19:17]; default: 0;
+ *  Receive Process State This field indicates the Receive DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Receive Command
+ *  issued 3’b001: Running: Fetching Receive Transfer Descriptor 3’b010: Reserved for
+ *  future use 3’b011: Running: Waiting for receive packet 3’b100: Suspended: Receive
+ *  Descriptor Unavailable 3’b101: Running: Closing Receive Descriptor 3’b110:
+ *  TIME_STAMP write state 3’b111: Running: Transferring the receive packet data from
+ *  receive buffer to host memory
+ */
+#define EMAC_RS    0x00000007U
+#define EMAC_RS_M  (EMAC_RS_V << EMAC_RS_S)
+#define EMAC_RS_V  0x00000007U
+#define EMAC_RS_S  17
+/** EMAC_TS : RO; bitpos: [22:20]; default: 0;
+ *  Transmit Process State This field indicates the Transmit DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Transmit Command
+ *  issued 3’b001: Running: Fetching Transmit Transfer Descriptor 3’b010: Running:
+ *  Waiting for status 3’b011: Running: Reading Data from host memory buffer and
+ *  queuing it to transmit buffer _Tx FIFO_ 3’b100: TIME_STAMP write state 3’b101:
+ *  Reserved for future use 3’b110: Suspended: Transmit Descriptor Unavailable or
+ *  Transmit Buffer Underflow 3’b111: Running: Closing Transmit Descriptor
+ */
+#define EMAC_TS    0x00000007U
+#define EMAC_TS_M  (EMAC_TS_V << EMAC_TS_S)
+#define EMAC_TS_V  0x00000007U
+#define EMAC_TS_S  20
+/** EMAC_EB : RO; bitpos: [25:23]; default: 0;
+ *  Error Bits This field indicates the type of error that caused a Bus Error, for
+ *  example, error response on the AHB or AXI interface This field is valid only when
+ *  Bit 13 _FBI_ is set This field does not generate an interrupt 0 0 0: Error during
+ *  Rx DMA Write Data Transfer 0 1 1: Error during Tx DMA Read Data Transfer 1 0 0:
+ *  Error during Rx DMA Descriptor Write Access 1 0 1: Error during Tx DMA Descriptor
+ *  Write Access 1 1 0: Error during Rx DMA Descriptor Read Access 1 1 1: Error during
+ *  Tx DMA Descriptor Read Access Note: 001 and 010 are reserved
+ */
+#define EMAC_EB    0x00000007U
+#define EMAC_EB_M  (EMAC_EB_V << EMAC_EB_S)
+#define EMAC_EB_V  0x00000007U
+#define EMAC_EB_S  23
+/** EMAC_GLI : RO; bitpos: [26]; default: 0;
+ *  EMAC Line Interface Interrupt When set, this bit reflects any of the following
+ *  interrupt events in the DWC_EMAC interfaces _if present and enabled in your
+ *  configuration_: PCS _TBI, RTBI, or SGMII_: Link change or autonegotiation complete
+ *  event SMII or RGMII: Link change event General Purpose Input Status _GPIS_: Any LL
+ *  or LH event on the gpi_i input ports To identify the exact cause of the interrupt,
+ *  the software must first read Bit 11 and Bits[2:0] of Register 14 _Interrupt Status
+ *  Register_ and then to clear the source of interrupt _which also clears the GLI
+ *  interrupt_, read any of the following corresponding registers: PCS _TBI, RTBI, or
+ *  SGMII_: Register 49 _AN Status Register_ SMII or RGMII: Register 54
+ *  _SGMII/RGMII/SMII Control and Status Register_ General Purpose Input _GPI_:
+ *  Register 56 _General Purpose IO Register_ The interrupt signal from the DWC_EMAC
+ *  subsystem _sbd_intr_o_ is high when this bit is high
+ */
+#define EMAC_GLI    (BIT(26))
+#define EMAC_GLI_M  (EMAC_GLI_V << EMAC_GLI_S)
+#define EMAC_GLI_V  0x00000001U
+#define EMAC_GLI_S  26
+/** EMAC_GMI : RO; bitpos: [27]; default: 0;
+ *  EMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the
+ *  DWC_EMAC The software must read the corresponding registers in the DWC_EMAC to get
+ *  the exact cause of the interrupt and clear the source of interrupt to make this bit
+ *  as 1’b0 The interrupt signal from the DWC_EMAC subsystem _sbd_intr_o_ is high when
+ *  this bit is high This bit is applicable only when the MAC Management Counters _MMC_
+ *  are enabled Otherwise, this bit is reserved
+ */
+#define EMAC_GMI    (BIT(27))
+#define EMAC_GMI_M  (EMAC_GMI_V << EMAC_GMI_S)
+#define EMAC_GMI_V  0x00000001U
+#define EMAC_GMI_S  27
+/** EMAC_GPI : RO; bitpos: [28]; default: 0;
+ *  EMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the
+ *  DWC_EMAC The software must read the PMT Control and Status Register in the MAC to
+ *  get the exact cause of interrupt and clear its source to reset this bit to 1’b0 The
+ *  interrupt signal from the DWC_EMAC subsystem _sbd_intr_o_ is high when this bit is
+ *  high This bit is applicable only when the Power Management feature is enabled
+ *  Otherwise, this bit is reserved Note: The GPI and pmt_intr_o interrupts are
+ *  generated in different clock domains
+ */
+#define EMAC_GPI    (BIT(28))
+#define EMAC_GPI_M  (EMAC_GPI_V << EMAC_GPI_S)
+#define EMAC_GPI_V  0x00000001U
+#define EMAC_GPI_S  28
+/** EMAC_TTI : RO; bitpos: [29]; default: 0;
+ *  Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp
+ *  Generator block of the DWC_EMAC The software must read the corresponding registers
+ *  in the DWC_EMAC to get the exact cause of the interrupt and clear its source to
+ *  reset this bit to 1'b0 When this bit is high, the interrupt signal from the
+ *  DWC_EMAC subsystem _sbd_intr_o_ is high This bit is applicable only when the IEEE
+ *  1588 Timestamp feature is enabled Otherwise, this bit is reserved
+ */
+#define EMAC_TTI    (BIT(29))
+#define EMAC_TTI_M  (EMAC_TTI_V << EMAC_TTI_S)
+#define EMAC_TTI_V  0x00000001U
+#define EMAC_TTI_S  29
+/** EMAC_GLPII_GTMSI : RO; bitpos: [30]; default: 0;
+ *  GLPII: EMAC LPI Interrupt This bit indicates an interrupt event in the LPI logic of
+ *  the MAC To reset this bit to 1'b0, the software must read the corresponding
+ *  registers in the DWC_EMAC to get the exact cause of the interrupt and clear its
+ *  source Note: GLPII status is given only in Channel 0 DMA register and is applicable
+ *  only when the Energy Efficient Ethernet feature is enabled Otherwise, this bit is
+ *  reserved When this bit is high, the interrupt signal from the MAC _sbd_intr_o_ is
+ *  high
+ */
+#define EMAC_GLPII_GTMSI    (BIT(30))
+#define EMAC_GLPII_GTMSI_M  (EMAC_GLPII_GTMSI_V << EMAC_GLPII_GTMSI_S)
+#define EMAC_GLPII_GTMSI_V  0x00000001U
+#define EMAC_GLPII_GTMSI_S  30
+
+/** EMAC_OPERATIONMODE_REG register
+ *  Establishes the Receive and Transmit operating modes and command Note: This
+ *  register is valid and present in the EMACMTL configuration
+ */
+#define EMAC_OPERATIONMODE_REG (DR_REG_EMAC_BASE + 0x1018)
+/** EMAC_SR : R/W; bitpos: [1]; default: 0;
+ *  Start or Stop Receive When this bit is set, the Receive process is placed in the
+ *  Running state The DMA attempts to acquire the descriptor from the Receive list and
+ *  processes the incoming frames The descriptor acquisition is attempted from the
+ *  current position in the list, which is the address set by the Register 3 _Receive
+ *  Descriptor List Address Register_ or the position retained when the Receive process
+ *  was previously stopped If the DMA does not own the descriptor, reception is
+ *  suspended and Bit 7 _Receive Buffer Unavailable_ of Register 5 _Status Register_ is
+ *  set The Start Receive command is effective only when the reception has stopped If
+ *  the command is issued before setting Register 3 _Receive Descriptor List Address
+ *  Register_, the DMA behavior is unpredictable When this bit is cleared, the Rx DMA
+ *  operation is stopped after the transfer of the current frame The next descriptor
+ *  position in the Receive list is saved and becomes the current position after the
+ *  Receive process is restarted The Stop Receive command is effective only when the
+ *  Receive process is in either the Running _waiting for receive packet_ or in the
+ *  Suspended state Note: For information about how to pause the transmission, see
+ *  “Stopping and Starting Transmission” on page 715
+ */
+#define EMAC_SR    (BIT(1))
+#define EMAC_SR_M  (EMAC_SR_V << EMAC_SR_S)
+#define EMAC_SR_V  0x00000001U
+#define EMAC_SR_S  1
+/** EMAC_OSF : R/W; bitpos: [2]; default: 0;
+ *  Operate on Second Frame When this bit is set, it instructs the DMA to process the
+ *  second frame of the Transmit data even before the status for the first frame is
+ *  obtained
+ */
+#define EMAC_OSF    (BIT(2))
+#define EMAC_OSF_M  (EMAC_OSF_V << EMAC_OSF_S)
+#define EMAC_OSF_V  0x00000001U
+#define EMAC_OSF_S  2
+/** EMAC_RTC : R/W; bitpos: [4:3]; default: 0;
+ *  Receive Threshold Control These two bits control the threshold level of the MTL
+ *  Receive FIFO Transfer _request_ to DMA starts when the frame size within the MTL
+ *  Receive FIFO is larger than the threshold In addition, full frames with length less
+ *  than the threshold are automatically transferred The value of 11 is not applicable
+ *  if the configured Receive FIFO size is 128 bytes These bits are valid only when the
+ *  RSF bit is zero, and are ignored when the RSF bit is set to 1 00: 64 01: 32 10: 96
+ *  11: 128
+ */
+#define EMAC_RTC    0x00000003U
+#define EMAC_RTC_M  (EMAC_RTC_V << EMAC_RTC_S)
+#define EMAC_RTC_V  0x00000003U
+#define EMAC_RTC_S  3
+/** EMAC_DGF : R/W; bitpos: [5]; default: 0;
+ *  Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO,
+ *  that is, frames that are larger than the computed giant frame limit When reset, the
+ *  MAC does not drop the giant frames in the Rx FIFO Note: This bit is available in
+ *  the following configurations in which the giant frame status is not provided in Rx
+ *  status and giant frames are not dropped by default: Configurations in which IP
+ *  Checksum Offload _Type 1_ is selected in Rx Configurations in which the IPC Full
+ *  Checksum Offload Engine _Type 2_ is selected in Rx with normal descriptor format
+ *  Configurations in which the Advanced Timestamp feature is selected In all other
+ *  configurations, this bit is not used _reserved and always reset_
+ */
+#define EMAC_DGF    (BIT(5))
+#define EMAC_DGF_M  (EMAC_DGF_V << EMAC_DGF_S)
+#define EMAC_DGF_V  0x00000001U
+#define EMAC_DGF_S  5
+/** EMAC_FUF : R/W; bitpos: [6]; default: 0;
+ *  Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames
+ *  _that is, frames with no Error and length less than 64 bytes_ including padbytes
+ *  and CRC When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a
+ *  frame is already transferred because of the lower value of Receive Threshold, for
+ *  example, RTC = 01
+ */
+#define EMAC_FUF    (BIT(6))
+#define EMAC_FUF_M  (EMAC_FUF_V << EMAC_FUF_S)
+#define EMAC_FUF_V  0x00000001U
+#define EMAC_FUF_S  6
+/** EMAC_FEF : R/W; bitpos: [7]; default: 0;
+ *  Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error
+ *  status _CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or
+ *  overflow_ However, if the start byte _write_ pointer of a frame is already
+ *  transferred to the read controller side _in Threshold mode_, then the frame is not
+ *  dropped In the EMACMTL configuration in which the Frame Length FIFO is also enabled
+ *  during core configuration, the Rx FIFO drops the error frames if that frame's start
+ *  byte is not transferred _output_ on the ARI bus When the FEF bit is set, all frames
+ *  except runt error frames are forwarded to the DMA If the Bit 25 _RSF_ is set and
+ *  the Rx FIFO overflows when a partial frame is written, then the frame is dropped
+ *  irrespective of the FEF bit setting However, if the Bit 25 _RSF_ is reset and the
+ *  Rx FIFO overflows when a partial frame is written, then a partial frame may be
+ *  forwarded to the DMA Note: When FEF bit is reset, the giant frames are dropped if
+ *  the giant frame status is given in Rx Status _in Table 86 or Table 823_ in the
+ *  following configurations: The IP checksum engine _Type 1_ and full checksum offload
+ *  engine _Type 2_ are not selected The advanced timestamp feature is not selected but
+ *  the extended status is selected The extended status is available with the following
+ *  features: 	L3L4 filter in EMACCORE or EMACMTL configurations 	Full checksum offload
+ *  engine _Type 2_ with enhanced descriptor format in the EMACDMA, EMACAHB, or EMACAXI
+ *  configurations
+ */
+#define EMAC_FEF    (BIT(7))
+#define EMAC_FEF_M  (EMAC_FEF_V << EMAC_FEF_S)
+#define EMAC_FEF_V  0x00000001U
+#define EMAC_FEF_S  7
+/** EMAC_EFC : R/W; bitpos: [8]; default: 0;
+ *  Enable HW Flow Control When this bit is set, the flow control signal operation
+ *  based on the filllevel of Rx FIFO is enabled When reset, the flow control operation
+ *  is disabled This bit is not used _reserved and always reset_ when the Rx FIFO is
+ *  less than 4 KB
+ */
+#define EMAC_EFC    (BIT(8))
+#define EMAC_EFC_M  (EMAC_EFC_V << EMAC_EFC_S)
+#define EMAC_EFC_V  0x00000001U
+#define EMAC_EFC_S  8
+/** EMAC_RFA : R/W; bitpos: [10:9]; default: 0;
+ *  Threshold for Activating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Fill level of Rx FIFO_ at which the flow control is
+ *  activated 00: Full minus 1 KB, that is, FULL—1KB 01: Full minus 2 KB, that is,
+ *  FULL—2KB 10: Full minus 3 KB, that is, FULL—3KB 11: Full minus 4 KB, that is,
+ *  FULL—4KB These values are applicable only to Rx FIFOs of 4 KB or more and when Bit
+ *  8 _EFC_ is set high If the Rx FIFO is 8 KB or more, an additional Bit _RFA_2_ is
+ *  used for more threshold levels as described in Bit 23 These bits are reserved and
+ *  readonly when the depth of Rx FIFO is less than 4 KB Note: When FIFO size is
+ *  exactly 4 KB, although the DWC_EMAC allows you to program the value of these bits
+ *  to 11, the software should not program these bits to 2'b11 The value 2'b11 means
+ *  flow control on FIFO empty condition
+ */
+#define EMAC_RFA    0x00000003U
+#define EMAC_RFA_M  (EMAC_RFA_V << EMAC_RFA_S)
+#define EMAC_RFA_V  0x00000003U
+#define EMAC_RFA_S  9
+/** EMAC_RFD : R/W; bitpos: [12:11]; default: 0;
+ *  Threshold for Deactivating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Filllevel of Rx FIFO_ at which the flow control is
+ *  deasserted after activation 00: Full minus 1 KB, that is, FULL — 1 KB 01: Full
+ *  minus 2 KB, that is, FULL — 2 KB 10: Full minus 3 KB, that is, FULL — 3 KB 11: Full
+ *  minus 4 KB, that is, FULL — 4 KB The deassertion is effective only after flow
+ *  control is asserted If the Rx FIFO is 8 KB or more, an additional Bit _RFD_2_ is
+ *  used for more threshold levels as described in Bit 22 These bits are reserved and
+ *  readonly when the Rx FIFO depth is less than 4 KB Note: For proper flow control,
+ *  the value programmed in the “RFD_2, RFD” fields should be equal to or more than the
+ *  value programmed in the “RFA_2, RFA” fields
+ */
+#define EMAC_RFD    0x00000003U
+#define EMAC_RFD_M  (EMAC_RFD_V << EMAC_RFD_S)
+#define EMAC_RFD_V  0x00000003U
+#define EMAC_RFD_S  11
+/** EMAC_ST : R/W; bitpos: [13]; default: 0;
+ *  Start or Stop Transmission Command When this bit is set, transmission is placed in
+ *  the Running state, and the DMA checks the Transmit List at the current position for
+ *  a frame to be transmitted Descriptor acquisition is attempted either from the
+ *  current position in the list, which is the Transmit List Base Address set by
+ *  Register 4 _Transmit Descriptor List Address Register_, or from the position
+ *  retained when transmission was stopped previously If the DMA does not own the
+ *  current descriptor, transmission enters the Suspended state and Bit 2 _Transmit
+ *  Buffer Unavailable_ of Register 5 _Status Register_ is set The Start Transmission
+ *  command is effective only when transmission is stopped If the command is issued
+ *  before setting Register 4 _Transmit Descriptor List Address Register_, then the DMA
+ *  behavior is unpredictable When this bit is reset, the transmission process is
+ *  placed in the Stopped state after completing the transmission of the current frame
+ *  The Next Descriptor position in the Transmit List is saved, and it becomes the
+ *  current position when transmission is restarted To change the list address, you
+ *  need to program Register 4 _Transmit Descriptor List Address Register_ with a new
+ *  value when this bit is reset The new value is considered when this bit is set again
+ *  The stop transmission command is effective only when the transmission of the
+ *  current frame is complete or the transmission is in the Suspended state Note: For
+ *  information about how to pause the transmission, see “Stopping and Starting
+ *  Transmission” on page 715
+ */
+#define EMAC_ST    (BIT(13))
+#define EMAC_ST_M  (EMAC_ST_V << EMAC_ST_S)
+#define EMAC_ST_V  0x00000001U
+#define EMAC_ST_S  13
+/** EMAC_TTC : R/W; bitpos: [16:14]; default: 0;
+ *  Transmit Threshold Control These bits control the threshold level of the MTL
+ *  Transmit FIFO Transmission starts when the frame size within the MTL Transmit FIFO
+ *  is larger than the threshold In addition, full frames with a length less than the
+ *  threshold are also transmitted These bits are used only when Bit 21 _TSF_ is reset
+ *  000: 64 001: 128 010: 192 011: 256 100: 40 101: 32 110: 24 111: 16
+ */
+#define EMAC_TTC    0x00000007U
+#define EMAC_TTC_M  (EMAC_TTC_V << EMAC_TTC_S)
+#define EMAC_TTC_V  0x00000007U
+#define EMAC_TTC_S  14
+/** EMAC_FTF : R/W1S; bitpos: [20]; default: 0;
+ *  Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is
+ *  reset to its default values and thus all data in the Tx FIFO is lost or flushed
+ *  This bit is cleared internally when the flushing operation is complete The
+ *  Operation Mode register should not be written to until this bit is cleared The data
+ *  which is already accepted by the MAC transmitter is not flushed It is scheduled for
+ *  transmission and results in underflow and runt frame transmission Note: The flush
+ *  operation is complete only when the Tx FIFO is emptied of its contents and all the
+ *  pending Transmit Status of the transmitted frames are accepted by the host In order
+ *  to complete this flush operation, the PHY transmit clock _clk_tx_i_ is required to
+ *  be active 19:17		Reserved 	000	RO
+ */
+#define EMAC_FTF    (BIT(20))
+#define EMAC_FTF_M  (EMAC_FTF_V << EMAC_FTF_S)
+#define EMAC_FTF_V  0x00000001U
+#define EMAC_FTF_S  20
+/** EMAC_TSF : R/W; bitpos: [21]; default: 0;
+ *  Transmit Store and Forward When this bit is set, transmission starts when a full
+ *  frame resides in the MTL Transmit FIFO When this bit is set, the TTC values
+ *  specified in Bits [16:14] are ignored This bit should be changed only when the
+ *  transmission is stopped
+ */
+#define EMAC_TSF    (BIT(21))
+#define EMAC_TSF_M  (EMAC_TSF_V << EMAC_TSF_S)
+#define EMAC_TSF_V  0x00000001U
+#define EMAC_TSF_S  21
+/** EMAC_RFD_2 : R/W; bitpos: [22]; default: 0;
+ *  MSB of Threshold for Deactivating Flow Control If the DWC_EMAC is configured for Rx
+ *  FIFO size of 8 KB or more, this bit _when set_ provides additional threshold levels
+ *  for deactivating the flow control in both halfduplex and fullduplex modes This bit
+ *  _as Most Significant Bit_ along with the RFD _Bits [12:11]_ gives the following
+ *  thresholds for deactivating flow control: 100: Full minus 5 KB, that is, FULL — 5
+ *  KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that is, FULL —
+ *  7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB or less deep
+ */
+#define EMAC_RFD_2    (BIT(22))
+#define EMAC_RFD_2_M  (EMAC_RFD_2_V << EMAC_RFD_2_S)
+#define EMAC_RFD_2_V  0x00000001U
+#define EMAC_RFD_2_S  22
+/** EMAC_RFA_2 : R/W; bitpos: [23]; default: 0;
+ *  MSB of Threshold for Activating Flow Control If the DWC_EMAC is configured for an
+ *  Rx FIFO size of 8 KB or more, this bit _when set_ provides additional threshold
+ *  levels for activating the flow control in both half duplex and fullduplex modes
+ *  This bit _as Most Significant Bit_, along with the RFA _Bits [10:9]_, gives the
+ *  following thresholds for activating flow control: 100: Full minus 5 KB, that is,
+ *  FULL — 5 KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that
+ *  is, FULL — 7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB
+ *  or less deep
+ */
+#define EMAC_RFA_2    (BIT(23))
+#define EMAC_RFA_2_M  (EMAC_RFA_2_V << EMAC_RFA_2_S)
+#define EMAC_RFA_2_V  0x00000001U
+#define EMAC_RFA_2_S  23
+/** EMAC_DFF : R/W; bitpos: [24]; default: 0;
+ *  Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush
+ *  any frames because of the unavailability of receive descriptors or buffers as it
+ *  does normally when this bit is reset _See “Receive Process Suspended” on page 83_
+ *  This bit is reserved _and RO_ in the EMACMTL configuration
+ */
+#define EMAC_DFF    (BIT(24))
+#define EMAC_DFF_M  (EMAC_DFF_V << EMAC_DFF_S)
+#define EMAC_DFF_V  0x00000001U
+#define EMAC_DFF_S  24
+/** EMAC_RSF : R/W; bitpos: [25]; default: 0;
+ *  Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx
+ *  FIFO only after the complete frame has been written to it, ignoring the RTC bits
+ *  When this bit is reset, the Rx FIFO operates in the cutthrough mode, subject to the
+ *  threshold specified by the RTC bits
+ */
+#define EMAC_RSF    (BIT(25))
+#define EMAC_RSF_M  (EMAC_RSF_V << EMAC_RSF_S)
+#define EMAC_RSF_V  0x00000001U
+#define EMAC_RSF_S  25
+/** EMAC_DT : R/W; bitpos: [26]; default: 0;
+ *  Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does
+ *  not drop the frames which only have errors detected by the Receive Checksum Offload
+ *  engine Such frames do not have any errors _including FCS error_ in the Ethernet
+ *  frame received by the MAC but have errors only in the encapsulated payload When
+ *  this bit is reset, all error frames are dropped if the FEF bit is reset If the IPC
+ *  Full Checksum Offload Engine _Type 2_ is disabled, this bit is reserved _RO with
+ *  value 1'b0_
+ */
+#define EMAC_DT    (BIT(26))
+#define EMAC_DT_M  (EMAC_DT_V << EMAC_DT_S)
+#define EMAC_DT_V  0x00000001U
+#define EMAC_DT_S  26
+
+/** EMAC_INTERRUPTENABLE_REG register
+ *  Enables the interrupts reported by the Status Register
+ */
+#define EMAC_INTERRUPTENABLE_REG (DR_REG_EMAC_BASE + 0x101c)
+/** EMAC_TIE : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Transmit Interrupt is enabled When this bit is reset, the Transmit
+ *  Interrupt is disabled The sbd_intr_o interrupt is generated as shown in Figure 61
+ *  It is asserted only when the TTI, GPI, GMI, GLI, or GLPII bit of the DMA Status
+ *  register is asserted, or when the NIS or AIS Status bit is asserted and the
+ *  corresponding Interrupt Enable bits _NIE or AIE_ are enabled
+ */
+#define EMAC_TIE    (BIT(0))
+#define EMAC_TIE_M  (EMAC_TIE_V << EMAC_TIE_S)
+#define EMAC_TIE_V  0x00000001U
+#define EMAC_TIE_S  0
+/** EMAC_TSE : R/W; bitpos: [1]; default: 0;
+ *  Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Transmission Stopped Interrupt is enabled When this bit is reset, the
+ *  Transmission Stopped Interrupt is disabled
+ */
+#define EMAC_TSE    (BIT(1))
+#define EMAC_TSE_M  (EMAC_TSE_V << EMAC_TSE_S)
+#define EMAC_TSE_V  0x00000001U
+#define EMAC_TSE_S  1
+/** EMAC_TUE : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt
+ *  Summary Enable _Bit 16_, the Transmit Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled
+ */
+#define EMAC_TUE    (BIT(2))
+#define EMAC_TUE_M  (EMAC_TUE_V << EMAC_TUE_S)
+#define EMAC_TUE_V  0x00000001U
+#define EMAC_TUE_S  2
+/** EMAC_TJE : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Jabber Timeout Interrupt is enabled When this bit is
+ *  reset, the Transmit Jabber Timeout Interrupt is disabled
+ */
+#define EMAC_TJE    (BIT(3))
+#define EMAC_TJE_M  (EMAC_TJE_V << EMAC_TJE_S)
+#define EMAC_TJE_V  0x00000001U
+#define EMAC_TJE_S  3
+/** EMAC_OVE : R/W; bitpos: [4]; default: 0;
+ *  Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Receive Overflow Interrupt is enabled When this bit is reset,
+ *  the Overflow Interrupt is disabled
+ */
+#define EMAC_OVE    (BIT(4))
+#define EMAC_OVE_M  (EMAC_OVE_V << EMAC_OVE_S)
+#define EMAC_OVE_V  0x00000001U
+#define EMAC_OVE_S  4
+/** EMAC_UNE : R/W; bitpos: [5]; default: 0;
+ *  Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Underflow Interrupt is enabled When this bit is
+ *  reset, the Underflow Interrupt is disabled
+ */
+#define EMAC_UNE    (BIT(5))
+#define EMAC_UNE_M  (EMAC_UNE_V << EMAC_UNE_S)
+#define EMAC_UNE_V  0x00000001U
+#define EMAC_UNE_S  5
+/** EMAC_RIE : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Receive Interrupt is enabled When this bit is reset, the Receive
+ *  Interrupt is disabled
+ */
+#define EMAC_RIE    (BIT(6))
+#define EMAC_RIE_M  (EMAC_RIE_V << EMAC_RIE_S)
+#define EMAC_RIE_V  0x00000001U
+#define EMAC_RIE_S  6
+/** EMAC_RUE : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Receive Buffer Unavailable Interrupt is disabled
+ */
+#define EMAC_RUE    (BIT(7))
+#define EMAC_RUE_M  (EMAC_RUE_V << EMAC_RUE_S)
+#define EMAC_RUE_V  0x00000001U
+#define EMAC_RUE_S  7
+/** EMAC_RSE : R/W; bitpos: [8]; default: 0;
+ *  Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Receive Stopped Interrupt is enabled When this bit is reset, the
+ *  Receive Stopped Interrupt is disabled
+ */
+#define EMAC_RSE    (BIT(8))
+#define EMAC_RSE_M  (EMAC_RSE_V << EMAC_RSE_S)
+#define EMAC_RSE_V  0x00000001U
+#define EMAC_RSE_S  8
+/** EMAC_RWE : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Watchdog Timeout Interrupt is enabled When
+ *  this bit is reset, the Receive Watchdog Timeout Interrupt is disabled
+ */
+#define EMAC_RWE    (BIT(9))
+#define EMAC_RWE_M  (EMAC_RWE_V << EMAC_RWE_S)
+#define EMAC_RWE_V  0x00000001U
+#define EMAC_RWE_S  9
+/** EMAC_ETE : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Early Transmit Interrupt is enabled When this bit is
+ *  reset, the Early Transmit Interrupt is disabled
+ */
+#define EMAC_ETE    (BIT(10))
+#define EMAC_ETE_M  (EMAC_ETE_V << EMAC_ETE_S)
+#define EMAC_ETE_V  0x00000001U
+#define EMAC_ETE_S  10
+/** EMAC_FBE : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Fatal Bus Error Interrupt is enabled When this bit is reset, the
+ *  Fatal Bus Error Enable Interrupt is disabled 12:11		Reserved	00	RO
+ */
+#define EMAC_FBE    (BIT(13))
+#define EMAC_FBE_M  (EMAC_FBE_V << EMAC_FBE_S)
+#define EMAC_FBE_V  0x00000001U
+#define EMAC_FBE_S  13
+/** EMAC_ERE : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary
+ *  Enable _Bit 16_, the Early Receive Interrupt is enabled When this bit is reset, the
+ *  Early Receive Interrupt is disabled
+ */
+#define EMAC_ERE    (BIT(14))
+#define EMAC_ERE_M  (EMAC_ERE_V << EMAC_ERE_S)
+#define EMAC_ERE_V  0x00000001U
+#define EMAC_ERE_S  14
+/** EMAC_AIE : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary
+ *  is enabled When this bit is reset, the abnormal interrupt summary is disabled This
+ *  bit enables the following interrupts in Register 5 _Status Register_: Register
+ *  5[1]: Transmit Process Stopped Register 5[3]: Transmit Jabber Timeout Register
+ *  5[4]: Receive Overflow Register 5[5]: Transmit Underflow Register 5[7]: Receive
+ *  Buffer Unavailable Register 5[8]: Receive Process Stopped Register 5[9]: Receive
+ *  Watchdog Timeout Register 5[10]: Early Transmit Interrupt Register 5[13]: Fatal Bus
+ *  Error
+ */
+#define EMAC_AIE    (BIT(15))
+#define EMAC_AIE_M  (EMAC_AIE_V << EMAC_AIE_S)
+#define EMAC_AIE_V  0x00000001U
+#define EMAC_AIE_S  15
+/** EMAC_NIE : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is
+ *  enabled When this bit is reset, normal interrupt summary is disabled This bit
+ *  enables the following interrupts in Register 5 _Status Register_: Register 5[0]:
+ *  Transmit Interrupt Register 5[2]: Transmit Buffer Unavailable Register 5[6]:
+ *  Receive Interrupt Register 5[14]: Early Receive Interrupt
+ */
+#define EMAC_NIE    (BIT(16))
+#define EMAC_NIE_M  (EMAC_NIE_V << EMAC_NIE_S)
+#define EMAC_NIE_V  0x00000001U
+#define EMAC_NIE_S  16
+
+/** EMAC_MISSEDFRAMEANDBUFFEROVERFLOWCOUNTER_REG register
+ *  Contains the counters for discarded frames because no host Receive Descriptor was
+ *  available or because of Receive FIFO Overflow
+ */
+#define EMAC_MISSEDFRAMEANDBUFFEROVERFLOWCOUNTER_REG (DR_REG_EMAC_BASE + 0x1020)
+/** EMAC_MISFRMCNT : R/W; bitpos: [15:0]; default: 0;
+ *  Missed Frame Counter This field indicates the number of frames missed by the
+ *  controller because of the Host Receive Buffer being unavailable This counter is
+ *  incremented each time the DMA discards an incoming frame The counter is cleared
+ *  when this register is read with mci_be_i[0] at 1’b1
+ */
+#define EMAC_MISFRMCNT    0x0000FFFFU
+#define EMAC_MISFRMCNT_M  (EMAC_MISFRMCNT_V << EMAC_MISFRMCNT_S)
+#define EMAC_MISFRMCNT_V  0x0000FFFFU
+#define EMAC_MISFRMCNT_S  0
+/** EMAC_MISCNTOVF : R/W; bitpos: [16]; default: 0;
+ *  Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame
+ *  Counter _Bits[15:0]_ overflows, that is, the DMA discards an incoming frame because
+ *  of the Host Receive Buffer being unavailable with the missed frame counter at
+ *  maximum value In such a scenario, the Missed frame counter is reset to allzeros and
+ *  this bit indicates that the rollover happened
+ */
+#define EMAC_MISCNTOVF    (BIT(16))
+#define EMAC_MISCNTOVF_M  (EMAC_MISCNTOVF_V << EMAC_MISCNTOVF_S)
+#define EMAC_MISCNTOVF_V  0x00000001U
+#define EMAC_MISCNTOVF_S  16
+/** EMAC_OVFFRMCNT : R/W; bitpos: [27:17]; default: 0;
+ *  Overflow Frame Counter This field indicates the number of frames missed by the
+ *  application This counter is incremented each time the MTL FIFO overflows The
+ *  counter is cleared when this register is read with mci_be_i[2] at 1’b1
+ */
+#define EMAC_OVFFRMCNT    0x000007FFU
+#define EMAC_OVFFRMCNT_M  (EMAC_OVFFRMCNT_V << EMAC_OVFFRMCNT_S)
+#define EMAC_OVFFRMCNT_V  0x000007FFU
+#define EMAC_OVFFRMCNT_S  17
+/** EMAC_OVFCNTOVF : R/W; bitpos: [28]; default: 0;
+ *  Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow
+ *  Frame Counter _Bits[27:17]_ overflows, that is, the Rx FIFO overflows with the
+ *  overflow frame counter at maximum value In such a scenario, the overflow frame
+ *  counter is reset to allzeros and this bit indicates that the rollover happened
+ */
+#define EMAC_OVFCNTOVF    (BIT(28))
+#define EMAC_OVFCNTOVF_M  (EMAC_OVFCNTOVF_V << EMAC_OVFCNTOVF_S)
+#define EMAC_OVFCNTOVF_V  0x00000001U
+#define EMAC_OVFCNTOVF_S  28
+
+/** EMAC_RECEIVEINTERRUPTWATCHDOGTIMER_REG register
+ *  Watchdog timeout for Receive Interrupt _RI_ from DMA
+ */
+#define EMAC_RECEIVEINTERRUPTWATCHDOGTIMER_REG (DR_REG_EMAC_BASE + 0x1024)
+/** EMAC_RIWT : R/W; bitpos: [7:0]; default: 0;
+ *  RI Watchdog Timer Count This bit indicates the number of system clock cycles
+ *  multiplied by 256 for which the watchdog timer is set The watchdog timer gets
+ *  triggered with the programmed value after the Rx DMA completes the transfer of a
+ *  frame for which the RI status bit is not set because of the setting in the
+ *  corresponding descriptor RDES1[31] When the watchdog timer runs out, the RI bit is
+ *  set and the timer is stopped The watchdog timer is reset when the RI bit is set
+ *  high because of automatic setting of RI as per RDES1[31] of any received frame
+ */
+#define EMAC_RIWT    0x000000FFU
+#define EMAC_RIWT_M  (EMAC_RIWT_V << EMAC_RIWT_S)
+#define EMAC_RIWT_V  0x000000FFU
+#define EMAC_RIWT_S  0
+
+/** EMAC_AXIBUSMODE_REG register
+ *  Controls AXI master behavior _mainly controls burst splitting and number of
+ *  outstanding requests_
+ */
+#define EMAC_AXIBUSMODE_REG (DR_REG_EMAC_BASE + 0x1028)
+/** EMAC_UNDEF : RO; bitpos: [0]; default: 1;
+ *  AXI Undefined Burst Length This bit is readonly bit and indicates the complement
+ *  _invert_ value of Bit 16 _FB_ in Register 0 _Bus Mode Register_ When this bit is
+ *  set to 1, the EMACAXI is allowed to perform any burst length equal to or below the
+ *  maximum allowed burst length programmed in Bits[7:3] When this bit is set to 0, the
+ *  EMACAXI is allowed to perform only fixed burst lengths as indicated by BLEN256,
+ *  BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1 If UNDEF
+ *  is set and none of the BLEN bits is set, then EMACAXI is allowed to perform a burst
+ *  length of 16
+ */
+#define EMAC_UNDEF    (BIT(0))
+#define EMAC_UNDEF_M  (EMAC_UNDEF_V << EMAC_UNDEF_S)
+#define EMAC_UNDEF_V  0x00000001U
+#define EMAC_UNDEF_S  0
+/** EMAC_BLEN4 : R/W; bitpos: [1]; default: 0;
+ *  AXI Burst Length 4 When this bit is set to 1, the EMACAXI is allowed to select a
+ *  burst length of 4 on the AXI master interface Setting this bit has no effect when
+ *  UNDEF is set to 1
+ */
+#define EMAC_BLEN4    (BIT(1))
+#define EMAC_BLEN4_M  (EMAC_BLEN4_V << EMAC_BLEN4_S)
+#define EMAC_BLEN4_V  0x00000001U
+#define EMAC_BLEN4_S  1
+/** EMAC_BLEN8 : R/W; bitpos: [2]; default: 0;
+ *  AXI Burst Length 8 When this bit is set to 1, the EMACAXI is allowed to select a
+ *  burst length of 8 on the AXI master interface Setting this bit has no effect when
+ *  UNDEF is set to 1
+ */
+#define EMAC_BLEN8    (BIT(2))
+#define EMAC_BLEN8_M  (EMAC_BLEN8_V << EMAC_BLEN8_S)
+#define EMAC_BLEN8_V  0x00000001U
+#define EMAC_BLEN8_S  2
+/** EMAC_BLEN16 : R/W; bitpos: [3]; default: 0;
+ *  AXI Burst Length 16 When this bit is set to 1 or UNDEF is set to 1, the EMACAXI is
+ *  allowed to select a burst length of 16 on the AXI master interface
+ */
+#define EMAC_BLEN16    (BIT(3))
+#define EMAC_BLEN16_M  (EMAC_BLEN16_V << EMAC_BLEN16_S)
+#define EMAC_BLEN16_V  0x00000001U
+#define EMAC_BLEN16_S  3
+/** EMAC_BLEN32 : R/W; bitpos: [4]; default: 0;
+ *  AXI Burst Length 32 When this bit is set to 1, the EMACAXI is allowed to select a
+ *  burst length of 32 on the AXI master interface This bit is present only when the
+ *  configuration parameter AXI_BL is set to 32 or more Otherwise, this bit is reserved
+ *  and is readonly _RO_
+ */
+#define EMAC_BLEN32    (BIT(4))
+#define EMAC_BLEN32_M  (EMAC_BLEN32_V << EMAC_BLEN32_S)
+#define EMAC_BLEN32_V  0x00000001U
+#define EMAC_BLEN32_S  4
+/** EMAC_BLEN64 : R/W; bitpos: [5]; default: 0;
+ *  AXI Burst Length 64 When this bit is set to 1, the EMACAXI is allowed to select a
+ *  burst length of 64 on the AXI master interface This bit is present only when the
+ *  configuration parameter AXI_BL is set to 64 or more Otherwise, this bit is reserved
+ *  and is readonly _RO_
+ */
+#define EMAC_BLEN64    (BIT(5))
+#define EMAC_BLEN64_M  (EMAC_BLEN64_V << EMAC_BLEN64_S)
+#define EMAC_BLEN64_V  0x00000001U
+#define EMAC_BLEN64_S  5
+/** EMAC_BLEN128 : R/W; bitpos: [6]; default: 0;
+ *  AXI Burst Length 128 When this bit is set to 1, the EMACAXI is allowed to select a
+ *  burst length of 128 on the AXI master interface This bit is present only when the
+ *  configuration parameter AXI_BL is set to 128 or more Otherwise, this bit is
+ *  reserved and is readonly _RO_
+ */
+#define EMAC_BLEN128    (BIT(6))
+#define EMAC_BLEN128_M  (EMAC_BLEN128_V << EMAC_BLEN128_S)
+#define EMAC_BLEN128_V  0x00000001U
+#define EMAC_BLEN128_S  6
+/** EMAC_BLEN256 : R/W; bitpos: [7]; default: 0;
+ *  AXI Burst Length 256 When this bit is set to 1, the EMACAXI is allowed to select a
+ *  burst length of 256 on the AXI master interface This bit is present only when the
+ *  configuration parameter AXI_BL is set to 256 Otherwise, this bit is reserved and is
+ *  readonly _RO_
+ */
+#define EMAC_BLEN256    (BIT(7))
+#define EMAC_BLEN256_M  (EMAC_BLEN256_V << EMAC_BLEN256_S)
+#define EMAC_BLEN256_V  0x00000001U
+#define EMAC_BLEN256_S  7
+/** EMAC_AXI_AAL : RO; bitpos: [12]; default: 0;
+ *  AddressAligned Beats This bit is readonly bit and reflects the Bit 25 _AAL_ of
+ *  Register 0 _Bus Mode Register_ When this bit is set to 1, the EMACAXI performs
+ *  addressaligned burst transfers on both read and write channels 11:8		Reserved	0H	RO
+ */
+#define EMAC_AXI_AAL    (BIT(12))
+#define EMAC_AXI_AAL_M  (EMAC_AXI_AAL_V << EMAC_AXI_AAL_S)
+#define EMAC_AXI_AAL_V  0x00000001U
+#define EMAC_AXI_AAL_S  12
+/** EMAC_ONEKBBE : R/W; bitpos: [13]; default: 0;
+ *  1 KB Boundary Crossing Enable for the EMACAXI Master When set, the EMACAXI master
+ *  performs burst transfers that do not cross 1 KB boundary When reset, the EMACAXI
+ *  master performs burst transfers that do not cross 4 KB boundary
+ */
+#define EMAC_ONEKBBE    (BIT(13))
+#define EMAC_ONEKBBE_M  (EMAC_ONEKBBE_V << EMAC_ONEKBBE_S)
+#define EMAC_ONEKBBE_V  0x00000001U
+#define EMAC_ONEKBBE_S  13
+/** EMAC_RD_OSR_LMT : R/W; bitpos: [19:16]; default: 1;
+ *  AXI Maximum Read Outstanding Request Limit This value limits the maximum
+ *  outstanding request on the AXI read interface Maximum outstanding requests =
+ *  RD_OSR_LMT+1 Note: Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4 Bit 19 is
+ *  reserved if AXI_GM_MAX_RD_REQUESTS != 16 15:14		Reserved	00	RO
+ */
+#define EMAC_RD_OSR_LMT    0x0000000FU
+#define EMAC_RD_OSR_LMT_M  (EMAC_RD_OSR_LMT_V << EMAC_RD_OSR_LMT_S)
+#define EMAC_RD_OSR_LMT_V  0x0000000FU
+#define EMAC_RD_OSR_LMT_S  16
+/** EMAC_WR_OSR_LMT : R/W; bitpos: [23:20]; default: 1;
+ *  AXI Maximum Write Outstanding Request Limit This value limits the maximum
+ *  outstanding request on the AXI write interface Maximum outstanding requests =
+ *  WR_OSR_LMT+1 Note: Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4 Bit 23 bit is
+ *  reserved if AXI_GM_MAX_WR_REQUESTS != 16
+ */
+#define EMAC_WR_OSR_LMT    0x0000000FU
+#define EMAC_WR_OSR_LMT_M  (EMAC_WR_OSR_LMT_V << EMAC_WR_OSR_LMT_S)
+#define EMAC_WR_OSR_LMT_V  0x0000000FU
+#define EMAC_WR_OSR_LMT_S  20
+/** EMAC_LPI_XIT_FRM : R/W; bitpos: [30]; default: 0;
+ *  Unlock on Magic Packet or Remote WakeUp Frame When set to 1, this bit enables the
+ *  EMACAXI to come out of the LPI mode only when the magic packet or remote wakeup
+ *  frame is received When set to 0, this bit enables the EMACAXI to come out of LPI
+ *  mode when any frame is received 29:24		Reserved	00H	RO
+ */
+#define EMAC_LPI_XIT_FRM    (BIT(30))
+#define EMAC_LPI_XIT_FRM_M  (EMAC_LPI_XIT_FRM_V << EMAC_LPI_XIT_FRM_S)
+#define EMAC_LPI_XIT_FRM_V  0x00000001U
+#define EMAC_LPI_XIT_FRM_S  30
+/** EMAC_EN_LPI : R/W; bitpos: [31]; default: 0;
+ *  Enable Low Power Interface _LPI_ When set to 1, this bit enables the LPI mode
+ *  supported by the EMACAXI configuration and accepts the LPI request from the AXI
+ *  System Clock controller When set to 0, this bit disables the LPI mode and always
+ *  denies the LPI request from the AXI System Clock controller
+ */
+#define EMAC_EN_LPI    (BIT(31))
+#define EMAC_EN_LPI_M  (EMAC_EN_LPI_V << EMAC_EN_LPI_S)
+#define EMAC_EN_LPI_V  0x00000001U
+#define EMAC_EN_LPI_S  31
+
+/** EMAC_AHBORAXISTATUS_REG register
+ *  Gives the idle status of the AHB master interface in the EMACAHB configuration
+ *  Gives the idle status of the AXI master's read or write channel in the EMACAXI
+ *  configuration
+ */
+#define EMAC_AHBORAXISTATUS_REG (DR_REG_EMAC_BASE + 0x102c)
+/** EMAC_AXWHSTS : RO; bitpos: [0]; default: 0;
+ *  AXI Master Write Channel or AHB Master Status When high, it indicates that AXI
+ *  master's write channel is active and transferring data in the EMACAXI configuration
+ *  In the EMACAHB configuration, it indicates that the AHB master interface FSMs are
+ *  in the nonidle state
+ */
+#define EMAC_AXWHSTS    (BIT(0))
+#define EMAC_AXWHSTS_M  (EMAC_AXWHSTS_V << EMAC_AXWHSTS_S)
+#define EMAC_AXWHSTS_V  0x00000001U
+#define EMAC_AXWHSTS_S  0
+/** EMAC_AXIRDSTS : RO; bitpos: [1]; default: 0;
+ *  AXI Master Read Channel Status When high, it indicates that AXI master's read
+ *  channel is active and transferring data
+ */
+#define EMAC_AXIRDSTS    (BIT(1))
+#define EMAC_AXIRDSTS_M  (EMAC_AXIRDSTS_V << EMAC_AXIRDSTS_S)
+#define EMAC_AXIRDSTS_V  0x00000001U
+#define EMAC_AXIRDSTS_S  1
+
+/** EMAC_CURRENTHOSTTRANSMITDESCRIPTOR_REG register
+ *  Points to the start of current Transmit Descriptor read by the DMA
+ */
+#define EMAC_CURRENTHOSTTRANSMITDESCRIPTOR_REG (DR_REG_EMAC_BASE + 0x1048)
+/** EMAC_CURTDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Descriptor Address Pointer
+ */
+#define EMAC_CURTDESAPTR    0xFFFFFFFFU
+#define EMAC_CURTDESAPTR_M  (EMAC_CURTDESAPTR_V << EMAC_CURTDESAPTR_S)
+#define EMAC_CURTDESAPTR_V  0xFFFFFFFFU
+#define EMAC_CURTDESAPTR_S  0
+
+/** EMAC_CURRENTHOSTRECEIVEDESCRIPTOR_REG register
+ *  Points to the start of current Receive Descriptor read by the DMA
+ */
+#define EMAC_CURRENTHOSTRECEIVEDESCRIPTOR_REG (DR_REG_EMAC_BASE + 0x104c)
+/** EMAC_CURRDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Descriptor Address Pointer
+ */
+#define EMAC_CURRDESAPTR    0xFFFFFFFFU
+#define EMAC_CURRDESAPTR_M  (EMAC_CURRDESAPTR_V << EMAC_CURRDESAPTR_S)
+#define EMAC_CURRDESAPTR_V  0xFFFFFFFFU
+#define EMAC_CURRDESAPTR_S  0
+
+/** EMAC_CURRENTHOSTTRANSMITBUFFERADDRESS_REG register
+ *  Points to the current Transmit Buffer address read by the DMA
+ */
+#define EMAC_CURRENTHOSTTRANSMITBUFFERADDRESS_REG (DR_REG_EMAC_BASE + 0x1050)
+/** EMAC_CURTBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Buffer Address Pointer
+ */
+#define EMAC_CURTBUFAPTR    0xFFFFFFFFU
+#define EMAC_CURTBUFAPTR_M  (EMAC_CURTBUFAPTR_V << EMAC_CURTBUFAPTR_S)
+#define EMAC_CURTBUFAPTR_V  0xFFFFFFFFU
+#define EMAC_CURTBUFAPTR_S  0
+
+/** EMAC_CURRENTHOSTRECEIVEBUFFERADDRESS_REG register
+ *  Points to the current Receive Buffer address read by the DMA
+ */
+#define EMAC_CURRENTHOSTRECEIVEBUFFERADDRESS_REG (DR_REG_EMAC_BASE + 0x1054)
+/** EMAC_CURRBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Buffer Address Pointer
+ */
+#define EMAC_CURRBUFAPTR    0xFFFFFFFFU
+#define EMAC_CURRBUFAPTR_M  (EMAC_CURRBUFAPTR_V << EMAC_CURRBUFAPTR_S)
+#define EMAC_CURRBUFAPTR_V  0xFFFFFFFFU
+#define EMAC_CURRBUFAPTR_S  0
+
+/** EMAC_HWFEATURE_REG register
+ *  Indicates the presence of the optional features of the core
+ */
+#define EMAC_HWFEATURE_REG (DR_REG_EMAC_BASE + 0x1058)
+/** EMAC_MIISEL : RO; bitpos: [0]; default: 0;
+ *  10 or 100 Mbps support
+ */
+#define EMAC_MIISEL    (BIT(0))
+#define EMAC_MIISEL_M  (EMAC_MIISEL_V << EMAC_MIISEL_S)
+#define EMAC_MIISEL_V  0x00000001U
+#define EMAC_MIISEL_S  0
+/** EMAC_GMIISEL : RO; bitpos: [1]; default: 0;
+ *  1000 Mbps support
+ */
+#define EMAC_GMIISEL    (BIT(1))
+#define EMAC_GMIISEL_M  (EMAC_GMIISEL_V << EMAC_GMIISEL_S)
+#define EMAC_GMIISEL_V  0x00000001U
+#define EMAC_GMIISEL_S  1
+/** EMAC_HDSEL : RO; bitpos: [2]; default: 0;
+ *  Halfduplex support
+ */
+#define EMAC_HDSEL    (BIT(2))
+#define EMAC_HDSEL_M  (EMAC_HDSEL_V << EMAC_HDSEL_S)
+#define EMAC_HDSEL_V  0x00000001U
+#define EMAC_HDSEL_S  2
+/** EMAC_EXTHASHEN : RO; bitpos: [3]; default: 0;
+ *  Expanded DA Hash filter
+ */
+#define EMAC_EXTHASHEN    (BIT(3))
+#define EMAC_EXTHASHEN_M  (EMAC_EXTHASHEN_V << EMAC_EXTHASHEN_S)
+#define EMAC_EXTHASHEN_V  0x00000001U
+#define EMAC_EXTHASHEN_S  3
+/** EMAC_HASHSEL : RO; bitpos: [4]; default: 0;
+ *  HASH filter
+ */
+#define EMAC_HASHSEL    (BIT(4))
+#define EMAC_HASHSEL_M  (EMAC_HASHSEL_V << EMAC_HASHSEL_S)
+#define EMAC_HASHSEL_V  0x00000001U
+#define EMAC_HASHSEL_S  4
+/** EMAC_ADDMACADRSEL : RO; bitpos: [5]; default: 0;
+ *  Multiple MAC Address registers
+ */
+#define EMAC_ADDMACADRSEL    (BIT(5))
+#define EMAC_ADDMACADRSEL_M  (EMAC_ADDMACADRSEL_V << EMAC_ADDMACADRSEL_S)
+#define EMAC_ADDMACADRSEL_V  0x00000001U
+#define EMAC_ADDMACADRSEL_S  5
+/** EMAC_PCSSEL : RO; bitpos: [6]; default: 0;
+ *  PCS registers _TBI, SGMII, or RTBI PHY interface_
+ */
+#define EMAC_PCSSEL    (BIT(6))
+#define EMAC_PCSSEL_M  (EMAC_PCSSEL_V << EMAC_PCSSEL_S)
+#define EMAC_PCSSEL_V  0x00000001U
+#define EMAC_PCSSEL_S  6
+/** EMAC_L3L4FLTREN : RO; bitpos: [7]; default: 0;
+ *  Layer 3 and Layer 4 feature
+ */
+#define EMAC_L3L4FLTREN    (BIT(7))
+#define EMAC_L3L4FLTREN_M  (EMAC_L3L4FLTREN_V << EMAC_L3L4FLTREN_S)
+#define EMAC_L3L4FLTREN_V  0x00000001U
+#define EMAC_L3L4FLTREN_S  7
+/** EMAC_SMASEL : RO; bitpos: [8]; default: 0;
+ *  SMA _MDIO_ Interface
+ */
+#define EMAC_SMASEL    (BIT(8))
+#define EMAC_SMASEL_M  (EMAC_SMASEL_V << EMAC_SMASEL_S)
+#define EMAC_SMASEL_V  0x00000001U
+#define EMAC_SMASEL_S  8
+/** EMAC_RWKSEL : RO; bitpos: [9]; default: 0;
+ *  PMT remote wakeup frame
+ */
+#define EMAC_RWKSEL    (BIT(9))
+#define EMAC_RWKSEL_M  (EMAC_RWKSEL_V << EMAC_RWKSEL_S)
+#define EMAC_RWKSEL_V  0x00000001U
+#define EMAC_RWKSEL_S  9
+/** EMAC_MGKSEL : RO; bitpos: [10]; default: 0;
+ *  PMT magic packet
+ */
+#define EMAC_MGKSEL    (BIT(10))
+#define EMAC_MGKSEL_M  (EMAC_MGKSEL_V << EMAC_MGKSEL_S)
+#define EMAC_MGKSEL_V  0x00000001U
+#define EMAC_MGKSEL_S  10
+/** EMAC_MMCSEL : RO; bitpos: [11]; default: 0;
+ *  RMON module
+ */
+#define EMAC_MMCSEL    (BIT(11))
+#define EMAC_MMCSEL_M  (EMAC_MMCSEL_V << EMAC_MMCSEL_S)
+#define EMAC_MMCSEL_V  0x00000001U
+#define EMAC_MMCSEL_S  11
+/** EMAC_TSVER1SEL : RO; bitpos: [12]; default: 0;
+ *  Only IEEE 15882002 timestamp
+ */
+#define EMAC_TSVER1SEL    (BIT(12))
+#define EMAC_TSVER1SEL_M  (EMAC_TSVER1SEL_V << EMAC_TSVER1SEL_S)
+#define EMAC_TSVER1SEL_V  0x00000001U
+#define EMAC_TSVER1SEL_S  12
+/** EMAC_TSVER2SEL : RO; bitpos: [13]; default: 0;
+ *  IEEE 15882008 Advanced timestamp
+ */
+#define EMAC_TSVER2SEL    (BIT(13))
+#define EMAC_TSVER2SEL_M  (EMAC_TSVER2SEL_V << EMAC_TSVER2SEL_S)
+#define EMAC_TSVER2SEL_V  0x00000001U
+#define EMAC_TSVER2SEL_S  13
+/** EMAC_EEESEL : RO; bitpos: [14]; default: 0;
+ *  Energy Efficient Ethernet
+ */
+#define EMAC_EEESEL    (BIT(14))
+#define EMAC_EEESEL_M  (EMAC_EEESEL_V << EMAC_EEESEL_S)
+#define EMAC_EEESEL_V  0x00000001U
+#define EMAC_EEESEL_S  14
+/** EMAC_AVSEL : RO; bitpos: [15]; default: 0;
+ *  AV feature
+ */
+#define EMAC_AVSEL    (BIT(15))
+#define EMAC_AVSEL_M  (EMAC_AVSEL_V << EMAC_AVSEL_S)
+#define EMAC_AVSEL_V  0x00000001U
+#define EMAC_AVSEL_S  15
+/** EMAC_TXCOESEL : RO; bitpos: [16]; default: 0;
+ *  Checksum Offload in Tx
+ */
+#define EMAC_TXCOESEL    (BIT(16))
+#define EMAC_TXCOESEL_M  (EMAC_TXCOESEL_V << EMAC_TXCOESEL_S)
+#define EMAC_TXCOESEL_V  0x00000001U
+#define EMAC_TXCOESEL_S  16
+/** EMAC_RXTYP1COE : RO; bitpos: [17]; default: 0;
+ *  IP Checksum Offload _Type 1_ in Rx Note: If IPCHKSUM_EN = Enabled and
+ *  IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1
+ */
+#define EMAC_RXTYP1COE    (BIT(17))
+#define EMAC_RXTYP1COE_M  (EMAC_RXTYP1COE_V << EMAC_RXTYP1COE_S)
+#define EMAC_RXTYP1COE_V  0x00000001U
+#define EMAC_RXTYP1COE_S  17
+/** EMAC_RXTYP2COE : RO; bitpos: [18]; default: 0;
+ *  IP Checksum Offload _Type 2_ in Rx
+ */
+#define EMAC_RXTYP2COE    (BIT(18))
+#define EMAC_RXTYP2COE_M  (EMAC_RXTYP2COE_V << EMAC_RXTYP2COE_S)
+#define EMAC_RXTYP2COE_V  0x00000001U
+#define EMAC_RXTYP2COE_S  18
+/** EMAC_RXFIFOSIZE : RO; bitpos: [19]; default: 0;
+ *  Rx FIFO > 2,048 Bytes
+ */
+#define EMAC_RXFIFOSIZE    (BIT(19))
+#define EMAC_RXFIFOSIZE_M  (EMAC_RXFIFOSIZE_V << EMAC_RXFIFOSIZE_S)
+#define EMAC_RXFIFOSIZE_V  0x00000001U
+#define EMAC_RXFIFOSIZE_S  19
+/** EMAC_RXCHCNT : RO; bitpos: [21:20]; default: 0;
+ *  Number of additional Rx Channels
+ */
+#define EMAC_RXCHCNT    0x00000003U
+#define EMAC_RXCHCNT_M  (EMAC_RXCHCNT_V << EMAC_RXCHCNT_S)
+#define EMAC_RXCHCNT_V  0x00000003U
+#define EMAC_RXCHCNT_S  20
+/** EMAC_TXCHCNT : RO; bitpos: [23:22]; default: 0;
+ *  Number of additional Tx Channels
+ */
+#define EMAC_TXCHCNT    0x00000003U
+#define EMAC_TXCHCNT_M  (EMAC_TXCHCNT_V << EMAC_TXCHCNT_S)
+#define EMAC_TXCHCNT_V  0x00000003U
+#define EMAC_TXCHCNT_S  22
+/** EMAC_ENHDESSEL : RO; bitpos: [24]; default: 0;
+ *  Alternate _Enhanced Descriptor_
+ */
+#define EMAC_ENHDESSEL    (BIT(24))
+#define EMAC_ENHDESSEL_M  (EMAC_ENHDESSEL_V << EMAC_ENHDESSEL_S)
+#define EMAC_ENHDESSEL_V  0x00000001U
+#define EMAC_ENHDESSEL_S  24
+/** EMAC_INTTSEN : RO; bitpos: [25]; default: 0;
+ *  Timestamping with Internal System Time
+ */
+#define EMAC_INTTSEN    (BIT(25))
+#define EMAC_INTTSEN_M  (EMAC_INTTSEN_V << EMAC_INTTSEN_S)
+#define EMAC_INTTSEN_V  0x00000001U
+#define EMAC_INTTSEN_S  25
+/** EMAC_FLEXIPPSEN : RO; bitpos: [26]; default: 0;
+ *  Flexible PulsePerSecond Output
+ */
+#define EMAC_FLEXIPPSEN    (BIT(26))
+#define EMAC_FLEXIPPSEN_M  (EMAC_FLEXIPPSEN_V << EMAC_FLEXIPPSEN_S)
+#define EMAC_FLEXIPPSEN_V  0x00000001U
+#define EMAC_FLEXIPPSEN_S  26
+/** EMAC_SAVLANINS : RO; bitpos: [27]; default: 0;
+ *  Source Address or VLAN Insertion
+ */
+#define EMAC_SAVLANINS    (BIT(27))
+#define EMAC_SAVLANINS_M  (EMAC_SAVLANINS_V << EMAC_SAVLANINS_S)
+#define EMAC_SAVLANINS_V  0x00000001U
+#define EMAC_SAVLANINS_S  27
+/** EMAC_ACTPHYIF : RO; bitpos: [30:28]; default: 0;
+ *  Active or selected PHY interface When you have multiple PHY interfaces in your
+ *  configuration, this field indicates the sampled value of phy_intf_sel_i during
+ *  reset deassertion 000: GMII or MII 001: RGMII 010: SGMII 011: TBI 100: RMII 101:
+ *  RTBI 110: SMII 111: RevMII All Others: Reserved
+ */
+#define EMAC_ACTPHYIF    0x00000007U
+#define EMAC_ACTPHYIF_M  (EMAC_ACTPHYIF_V << EMAC_ACTPHYIF_S)
+#define EMAC_ACTPHYIF_V  0x00000007U
+#define EMAC_ACTPHYIF_S  28
+
+/** EMAC_CHANNEL1BUSMODE_REG register
+ *  Controls the Host Interface mode for Channel 1
+ */
+#define EMAC_CHANNEL1BUSMODE_REG (DR_REG_EMAC_BASE + 0x1100)
+/** EMAC_CH1_SWR : R/W1S; bitpos: [0]; default: 1;
+ *  Software Reset When this bit is set, the MAC DMA Controller resets the logic and
+ *  all internal registers of the MAC It is cleared automatically after the reset
+ *  operation is complete in all of the DWC_EMAC clock domains Before reprogramming any
+ *  register of the DWC_EMAC, you should read a zero _0_ value in this bit Note: The
+ *  Software reset function is driven only by this bit Bit 0 of Register 64 _Channel 1
+ *  Bus Mode Register_ or Register 128 _Channel 2 Bus Mode Register_ has no impact on
+ *  the Software reset function The reset operation is completed only when all resets
+ *  in all active clock domains are deasserted Therefore, it is essential that all PHY
+ *  inputs clocks _applicable for the selected PHY interface_ are present for the
+ *  software reset completion The time to complete the software reset operation depends
+ *  on the frequency of the slowest active clock
+ */
+#define EMAC_CH1_SWR    (BIT(0))
+#define EMAC_CH1_SWR_M  (EMAC_CH1_SWR_V << EMAC_CH1_SWR_S)
+#define EMAC_CH1_SWR_V  0x00000001U
+#define EMAC_CH1_SWR_S  0
+/** EMAC_CH1_DA : R/W; bitpos: [1]; default: 0;
+ *  DMA Arbitration Scheme This bit specifies the arbitration scheme between the
+ *  transmit and receive paths of Channel 1 0: Weighted roundrobin with Rx:Tx or Tx:Rx
+ *  The priority between the paths is according to the priority specified in Bits
+ *  [15:14] _PR_ and priority weights specified in Bit 27 _TXPR_ 1: Fixed priority The
+ *  transmit path has priority over receive path when Bit 27 _TXPR_ is set Otherwise,
+ *  receive path has priority over the transmit path In the EMACAXI configuration,
+ *  these bits are reserved and are readonly _RO_ For more information about the
+ *  priority scheme between the transmit and receive paths, see Table 412 in “DMA
+ *  Arbiter Functions” on page 167
+ */
+#define EMAC_CH1_DA    (BIT(1))
+#define EMAC_CH1_DA_M  (EMAC_CH1_DA_V << EMAC_CH1_DA_S)
+#define EMAC_CH1_DA_V  0x00000001U
+#define EMAC_CH1_DA_S  1
+/** EMAC_CH1_DSL : R/W; bitpos: [6:2]; default: 0;
+ *  Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword
+ *  _depending on the 32bit, 64bit, or 128bit bus_ to skip between two unchained
+ *  descriptors The address skipping starts from the end of current descriptor to the
+ *  start of next descriptor When the DSL value is equal to zero, the descriptor table
+ *  is taken as contiguous by the DMA in Ring mode
+ */
+#define EMAC_CH1_DSL    0x0000001FU
+#define EMAC_CH1_DSL_M  (EMAC_CH1_DSL_V << EMAC_CH1_DSL_S)
+#define EMAC_CH1_DSL_V  0x0000001FU
+#define EMAC_CH1_DSL_S  2
+/** EMAC_CH1_ATDS : R/W; bitpos: [7]; default: 0;
+ *  Alternate Descriptor Size When set, the size of the alternate descriptor _described
+ *  in “Alternate or Enhanced Descriptors” on page 545_ increases to 32 bytes _8
+ *  DWORDS_ This is required when the Advanced Timestamp feature or the IPC Full
+ *  Checksum Offload Engine _Type 2_ is enabled in the receiver The enhanced descriptor
+ *  is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine
+ *  _Type 2_ features are not enabled In such case, you can use the 16 bytes descriptor
+ *  to save 4 bytes of memory This bit is present only when you select the Alternate
+ *  Descriptor feature and any one of the following features during core configuration:
+ *  Advanced Timestamp feature IPC Full Checksum Offload Engine _Type 2_ feature
+ *  Otherwise, this bit is reserved and is readonly When reset, the descriptor size
+ *  reverts back to 4 DWORDs _16 bytes_ This bit preserves the backward compatibility
+ *  for the descriptor size In versions prior to 350a, the descriptor size is 16 bytes
+ *  for both normal and enhanced descriptors In version 350a, descriptor size is
+ *  increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum
+ *  Offload Engine _Type 2_ features
+ */
+#define EMAC_CH1_ATDS    (BIT(7))
+#define EMAC_CH1_ATDS_M  (EMAC_CH1_ATDS_V << EMAC_CH1_ATDS_S)
+#define EMAC_CH1_ATDS_V  0x00000001U
+#define EMAC_CH1_ATDS_S  7
+/** EMAC_CH1_PBL : R/W; bitpos: [13:8]; default: 1;
+ *  Programmable Burst Length These bits indicate the maximum number of beats to be
+ *  transferred in one DMA transaction This is the maximum value that is used in a
+ *  single block Read or Write The DMA always attempts to burst as specified in PBL
+ *  each time it starts a Burst transfer on the host bus PBL can be programmed with
+ *  permissible values of 1, 2, 4, 8, 16, and 32 Any other value results in undefined
+ *  behavior When USP is set high, this PBL value is applicable only for Tx DMA
+ *  transactions If the number of beats to be transferred is more than 32, then perform
+ *  the following steps: 1 Set the PBLx8 mode 2 Set the PBL For example, if the maximum
+ *  number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL
+ *  to 8 The PBL values have the following limitation: The maximum number of possible
+ *  beats _PBL_ is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and
+ *  the data bus width on the DMA The FIFO has a constraint that the maximum beat
+ *  supported is half the depth of the FIFO, except when specified For different data
+ *  bus widths and FIFO sizes, the valid PBL range _including x8 mode_ is provided in
+ *  Table 66 on page 382
+ */
+#define EMAC_CH1_PBL    0x0000003FU
+#define EMAC_CH1_PBL_M  (EMAC_CH1_PBL_V << EMAC_CH1_PBL_S)
+#define EMAC_CH1_PBL_V  0x0000003FU
+#define EMAC_CH1_PBL_S  8
+/** EMAC_CH1_PR : R/W; bitpos: [15:14]; default: 0;
+ *  Priority Ratio These bits control the priority ratio in the weighted roundrobin
+ *  arbitration between the Rx DMA and Tx DMA These bits are valid only when Bit 1 _DA_
+ *  is reset The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 _TXPR_ is
+ *  reset or set 00: The Priority Ratio is 1:1 01: The Priority Ratio is 2:1 10: The
+ *  Priority Ratio is 3:1 11: The Priority Ratio is 4:1 In the EMACAXI configuration,
+ *  these bits are reserved and readonly _RO_ For more information about the priority
+ *  scheme between the transmit and receive paths, see Table 412 in “DMA Arbiter
+ *  Functions” on page 167
+ */
+#define EMAC_CH1_PR    0x00000003U
+#define EMAC_CH1_PR_M  (EMAC_CH1_PR_V << EMAC_CH1_PR_S)
+#define EMAC_CH1_PR_V  0x00000003U
+#define EMAC_CH1_PR_S  14
+/** EMAC_CH1_FB : R/W; bitpos: [16]; default: 0;
+ *  Fixed Burst This bit controls whether the AHB or AXI master interface performs
+ *  fixed burst transfers or not When set, the AHB interface uses only SINGLE, INCR4,
+ *  INCR8, or INCR16 during start of the normal burst transfers When reset, the AHB or
+ *  AXI interface uses SINGLE and INCR burst transfer operations For more information,
+ *  see Bit 0 _UNDEF_ of the AXI Bus Mode register in the EMACAXI configuration
+ */
+#define EMAC_CH1_FB    (BIT(16))
+#define EMAC_CH1_FB_M  (EMAC_CH1_FB_V << EMAC_CH1_FB_S)
+#define EMAC_CH1_FB_V  0x00000001U
+#define EMAC_CH1_FB_S  16
+/** EMAC_CH1_RPBL : R/W; bitpos: [22:17]; default: 1;
+ *  Rx DMA PBL This field indicates the maximum number of beats to be transferred in
+ *  one Rx DMA transaction This is the maximum value that is used in a single block
+ *  Read or Write The Rx DMA always attempts to burst as specified in the RPBL bit each
+ *  time it starts a Burst transfer on the host bus You can program RPBL with values of
+ *  1, 2, 4, 8, 16, and 32 Any other value results in undefined behavior This field is
+ *  valid and applicable only when USP is set high
+ */
+#define EMAC_CH1_RPBL    0x0000003FU
+#define EMAC_CH1_RPBL_M  (EMAC_CH1_RPBL_V << EMAC_CH1_RPBL_S)
+#define EMAC_CH1_RPBL_V  0x0000003FU
+#define EMAC_CH1_RPBL_S  17
+/** EMAC_CH1_USP : R/W; bitpos: [23]; default: 0;
+ *  Use Separate PBL When set high, this bit configures the Rx DMA to use the value
+ *  configured in Bits [22:17] as PBL The PBL value in Bits [13:8] is applicable only
+ *  to the Tx DMA operations When reset to low, the PBL value in Bits [13:8] is
+ *  applicable for both DMA engines
+ */
+#define EMAC_CH1_USP    (BIT(23))
+#define EMAC_CH1_USP_M  (EMAC_CH1_USP_V << EMAC_CH1_USP_S)
+#define EMAC_CH1_USP_V  0x00000001U
+#define EMAC_CH1_USP_S  23
+/** EMAC_CH1_PBLX8 : R/W; bitpos: [24]; default: 0;
+ *  PBLx8 Mode When set high, this bit multiplies the programmed PBL value _Bits
+ *  [22:17] and Bits[13:8]_ eight times Therefore, the DMA transfers the data in 8, 16,
+ *  32, 64, 128, and 256 beats depending on the PBL value Note: This bit function is
+ *  not backward compatible Before release 350a, this bit was 4xPBL
+ */
+#define EMAC_CH1_PBLX8    (BIT(24))
+#define EMAC_CH1_PBLX8_M  (EMAC_CH1_PBLX8_V << EMAC_CH1_PBLX8_S)
+#define EMAC_CH1_PBLX8_V  0x00000001U
+#define EMAC_CH1_PBLX8_S  24
+/** EMAC_CH1_AAL : R/W; bitpos: [25]; default: 0;
+ *  AddressAligned Beats When this bit is set high and the FB bit is equal to 1, the
+ *  AHB or AXI interface generates all bursts aligned to the start address LS bits If
+ *  the FB bit is equal to 0, the first burst _accessing the start address of data
+ *  buffer_ is not aligned, but subsequent bursts are aligned to the address This bit
+ *  is valid only in the EMACAHB and EMACAXI configurations and is reserved _RO with
+ *  default value 0_ in all other configurations
+ */
+#define EMAC_CH1_AAL    (BIT(25))
+#define EMAC_CH1_AAL_M  (EMAC_CH1_AAL_V << EMAC_CH1_AAL_S)
+#define EMAC_CH1_AAL_V  0x00000001U
+#define EMAC_CH1_AAL_S  25
+/** EMAC_CH1_MB : R/W; bitpos: [26]; default: 0;
+ *  Mixed Burst When this bit is set high and the FB bit is low, the AHB master
+ *  interface starts all bursts of length more than 16 with INCR _undefined burst_,
+ *  whereas it reverts to fixed burst transfers _INCRx and SINGLE_ for burst length of
+ *  16 and less This bit is valid only in the EMACAHB configuration and reserved in all
+ *  other configuration
+ */
+#define EMAC_CH1_MB    (BIT(26))
+#define EMAC_CH1_MB_M  (EMAC_CH1_MB_V << EMAC_CH1_MB_S)
+#define EMAC_CH1_MB_V  0x00000001U
+#define EMAC_CH1_MB_S  26
+/** EMAC_CH1_TXPR : R/W; bitpos: [27]; default: 0;
+ *  Transmit Priority When set, this bit indicates that the transmit DMA has higher
+ *  priority than the receive DMA during arbitration for the systemside bus In the
+ *  EMACAXI configuration, this bit is reserved and readonly _RO_ For more information
+ *  about the priority scheme between the transmit and receive paths, see Table 412 in
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define EMAC_CH1_TXPR    (BIT(27))
+#define EMAC_CH1_TXPR_M  (EMAC_CH1_TXPR_V << EMAC_CH1_TXPR_S)
+#define EMAC_CH1_TXPR_V  0x00000001U
+#define EMAC_CH1_TXPR_S  27
+/** EMAC_CH1_PRWG : R/W; bitpos: [29:28]; default: 0;
+ *  Channel Priority Weights This field sets the priority weights for Channel 1 during
+ *  the roundrobin arbitration between the DMA channels for the system bus 00: The
+ *  priority weight is 1 01: The priority weight is 2 10: The priority weight is 3 11:
+ *  The priority weight is 4 This field is present in all DWC_EMAC configurations
+ *  except EMACAXI when you select the AV feature Otherwise, this field is reserved and
+ *  readonly _RO_ For more information about the priority weights of DMA channels, see
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define EMAC_CH1_PRWG    0x00000003U
+#define EMAC_CH1_PRWG_M  (EMAC_CH1_PRWG_V << EMAC_CH1_PRWG_S)
+#define EMAC_CH1_PRWG_V  0x00000003U
+#define EMAC_CH1_PRWG_S  28
+/** EMAC_CH1_RIB : R/W; bitpos: [31]; default: 0;
+ *  Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT
+ *  _Retry, Split, or Losing bus grant_, the AHB master interface rebuilds the pending
+ *  beats of any burst transfer initiated with INCRx The AHB master interface rebuilds
+ *  the beats with a combination of specified bursts with INCRx and SINGLE By default,
+ *  the AHB master interface rebuilds pending beats of an EBT with an unspecified
+ *  _INCR_ burst This bit is valid only in the EMACAHB configuration It is reserved in
+ *  all other configuration
+ */
+#define EMAC_CH1_RIB    (BIT(31))
+#define EMAC_CH1_RIB_M  (EMAC_CH1_RIB_V << EMAC_CH1_RIB_S)
+#define EMAC_CH1_RIB_V  0x00000001U
+#define EMAC_CH1_RIB_S  31
+
+/** EMAC_CHANNEL1TRANSMITPOLLDEMAND_REG register
+ *  Used by the host to instruct the DMA to poll the Transmit Descriptor list
+ */
+#define EMAC_CHANNEL1TRANSMITPOLLDEMAND_REG (DR_REG_EMAC_BASE + 0x1104)
+/** EMAC_CH1_TPD : RO; bitpos: [31:0]; default: 0;
+ *  Transmit Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 18 _Current Host Transmit Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  transmission returns to the Suspend state and Bit 2 _TU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the transmission resumes
+ */
+#define EMAC_CH1_TPD    0xFFFFFFFFU
+#define EMAC_CH1_TPD_M  (EMAC_CH1_TPD_V << EMAC_CH1_TPD_S)
+#define EMAC_CH1_TPD_V  0xFFFFFFFFU
+#define EMAC_CH1_TPD_S  0
+
+/** EMAC_CHANNEL1RECEIVEPOLLDEMAND_REG register
+ *  Used by the Host to instruct the DMA to poll the Receive Descriptor list
+ */
+#define EMAC_CHANNEL1RECEIVEPOLLDEMAND_REG (DR_REG_EMAC_BASE + 0x1108)
+/** EMAC_CH1_RPD : RO; bitpos: [31:0]; default: 0;
+ *  Receive Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 19 _Current Host Receive Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  reception returns to the Suspended state and Bit 7 _RU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the Rx DMA returns to the
+ *  active state
+ */
+#define EMAC_CH1_RPD    0xFFFFFFFFU
+#define EMAC_CH1_RPD_M  (EMAC_CH1_RPD_V << EMAC_CH1_RPD_S)
+#define EMAC_CH1_RPD_V  0xFFFFFFFFU
+#define EMAC_CH1_RPD_S  0
+
+/** EMAC_CHANNEL1RECEIVEDESCRIPTORLISTADDRESS_REG register
+ *  Points the DMA to the start of the Receive Descriptor list
+ */
+#define EMAC_CHANNEL1RECEIVEDESCRIPTORLISTADDRESS_REG (DR_REG_EMAC_BASE + 0x110c)
+/** EMAC_CH1_RDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Receive List This field contains the base address of the first descriptor
+ *  in the Receive Descriptor list The LSB bits _1:0, 2:0, or 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and internally taken as allzero by the DMA Therefore,
+ *  these LSB bits are readonly _RO_
+ */
+#define EMAC_CH1_RDESLA    0xFFFFFFFFU
+#define EMAC_CH1_RDESLA_M  (EMAC_CH1_RDESLA_V << EMAC_CH1_RDESLA_S)
+#define EMAC_CH1_RDESLA_V  0xFFFFFFFFU
+#define EMAC_CH1_RDESLA_S  0
+
+/** EMAC_CHANNEL1TRANSMITDESCRIPTORLISTADDRESS_REG register
+ *  Points the DMA to the start of the Transmit Descriptor list
+ */
+#define EMAC_CHANNEL1TRANSMITDESCRIPTORLISTADDRESS_REG (DR_REG_EMAC_BASE + 0x1110)
+/** EMAC_CH1_TDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Transmit List This field contains the base address of the first descriptor
+ *  in the Transmit Descriptor list The LSB bits _1:0, 2:0, 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and are internally taken as allzero by the DMA
+ *  Therefore, these LSB bits are readonly _RO_
+ */
+#define EMAC_CH1_TDESLA    0xFFFFFFFFU
+#define EMAC_CH1_TDESLA_M  (EMAC_CH1_TDESLA_V << EMAC_CH1_TDESLA_S)
+#define EMAC_CH1_TDESLA_V  0xFFFFFFFFU
+#define EMAC_CH1_TDESLA_S  0
+
+/** EMAC_CHANNEL1STATUS_REG register
+ *  The Software driver _application_ reads this register during interrupt service
+ *  routine or polling to determine the status of the DMA Bits 29:26 are reserved for
+ *  the Channel 1 Status Register
+ */
+#define EMAC_CHANNEL1STATUS_REG (DR_REG_EMAC_BASE + 0x1114)
+/** EMAC_CH1_TI : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt This bit indicates that the frame transmission is complete When
+ *  transmission is complete, Bit 31 _OWN_ of TDES0 is reset, and the specific frame
+ *  status information is updated in the descriptor
+ */
+#define EMAC_CH1_TI    (BIT(0))
+#define EMAC_CH1_TI_M  (EMAC_CH1_TI_V << EMAC_CH1_TI_S)
+#define EMAC_CH1_TI_V  0x00000001U
+#define EMAC_CH1_TI_S  0
+/** EMAC_CH1_TPS : R/W; bitpos: [1]; default: 0;
+ *  Transmit Process Stopped This bit is set when the transmission is stopped
+ */
+#define EMAC_CH1_TPS    (BIT(1))
+#define EMAC_CH1_TPS_M  (EMAC_CH1_TPS_V << EMAC_CH1_TPS_S)
+#define EMAC_CH1_TPS_V  0x00000001U
+#define EMAC_CH1_TPS_S  1
+/** EMAC_CH1_TU : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Transmit List and the DMA cannot acquire it Transmission is
+ *  suspended Bits[22:20] explain the Transmit Process state transitions To resume
+ *  processing Transmit descriptors, the host should change the ownership of the
+ *  descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command
+ */
+#define EMAC_CH1_TU    (BIT(2))
+#define EMAC_CH1_TU_M  (EMAC_CH1_TU_V << EMAC_CH1_TU_S)
+#define EMAC_CH1_TU_V  0x00000001U
+#define EMAC_CH1_TU_S  2
+/** EMAC_CH1_TJT : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired,
+ *  which happens when the frame size exceeds 2,048 _10,240 bytes when the Jumbo frame
+ *  is enabled_ When the Jabber Timeout occurs, the transmission process is aborted and
+ *  placed in the Stopped state This causes the Transmit Jabber Timeout TDES0[14] flag
+ *  to assert
+ */
+#define EMAC_CH1_TJT    (BIT(3))
+#define EMAC_CH1_TJT_M  (EMAC_CH1_TJT_V << EMAC_CH1_TJT_S)
+#define EMAC_CH1_TJT_V  0x00000001U
+#define EMAC_CH1_TJT_S  3
+/** EMAC_CH1_OVF : R/W; bitpos: [4]; default: 0;
+ *  Receive Overflow This bit indicates that the Receive Buffer had an Overflow during
+ *  frame reception If the partial frame is transferred to the application, the
+ *  overflow status is set in RDES0[11]
+ */
+#define EMAC_CH1_OVF    (BIT(4))
+#define EMAC_CH1_OVF_M  (EMAC_CH1_OVF_V << EMAC_CH1_OVF_S)
+#define EMAC_CH1_OVF_V  0x00000001U
+#define EMAC_CH1_OVF_S  4
+/** EMAC_CH1_UNF : R/W; bitpos: [5]; default: 0;
+ *  Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow
+ *  during frame transmission Transmission is suspended and an Underflow Error TDES0[1]
+ *  is set
+ */
+#define EMAC_CH1_UNF    (BIT(5))
+#define EMAC_CH1_UNF_M  (EMAC_CH1_UNF_V << EMAC_CH1_UNF_S)
+#define EMAC_CH1_UNF_V  0x00000001U
+#define EMAC_CH1_UNF_S  5
+/** EMAC_CH1_RI : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt This bit indicates that the frame reception is complete When
+ *  reception is complete, the Bit 31 of RDES1 _Disable Interrupt on Completion_ is
+ *  reset in the last Descriptor, and the specific frame status information is updated
+ *  in the descriptor The reception remains in the Running state
+ */
+#define EMAC_CH1_RI    (BIT(6))
+#define EMAC_CH1_RI_M  (EMAC_CH1_RI_V << EMAC_CH1_RI_S)
+#define EMAC_CH1_RI_V  0x00000001U
+#define EMAC_CH1_RI_S  6
+/** EMAC_CH1_RU : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Receive List and the DMA cannot acquire it The Receive Process is
+ *  suspended To resume processing Receive descriptors, the host should change the
+ *  ownership of the descriptor and issue a Receive Poll Demand command If no Receive
+ *  Poll Demand is issued, the Receive Process resumes when the next recognized
+ *  incoming frame is received This bit is set only when the previous Receive
+ *  Descriptor is owned by the DMA
+ */
+#define EMAC_CH1_RU    (BIT(7))
+#define EMAC_CH1_RU_M  (EMAC_CH1_RU_V << EMAC_CH1_RU_S)
+#define EMAC_CH1_RU_V  0x00000001U
+#define EMAC_CH1_RU_S  7
+/** EMAC_CH1_RPS : R/W; bitpos: [8]; default: 0;
+ *  Receive Process Stopped This bit is asserted when the Receive Process enters the
+ *  Stopped state
+ */
+#define EMAC_CH1_RPS    (BIT(8))
+#define EMAC_CH1_RPS_M  (EMAC_CH1_RPS_V << EMAC_CH1_RPS_S)
+#define EMAC_CH1_RPS_V  0x00000001U
+#define EMAC_CH1_RPS_S  8
+/** EMAC_CH1_RWT : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog
+ *  Timer expired while receiving the current frame and the current frame is truncated
+ *  after the watchdog timeout
+ */
+#define EMAC_CH1_RWT    (BIT(9))
+#define EMAC_CH1_RWT_M  (EMAC_CH1_RWT_V << EMAC_CH1_RWT_S)
+#define EMAC_CH1_RWT_V  0x00000001U
+#define EMAC_CH1_RWT_S  9
+/** EMAC_CH1_ETI : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt This bit indicates that the frame to be transmitted is
+ *  fully transferred to the MTL Transmit FIFO
+ */
+#define EMAC_CH1_ETI    (BIT(10))
+#define EMAC_CH1_ETI_M  (EMAC_CH1_ETI_V << EMAC_CH1_ETI_S)
+#define EMAC_CH1_ETI_V  0x00000001U
+#define EMAC_CH1_ETI_S  10
+/** EMAC_CH1_FBI : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as
+ *  described in Bits [25:23] When this bit is set, the corresponding DMA engine
+ *  disables all of its bus accesses 12:11		Reserved	00	RO
+ */
+#define EMAC_CH1_FBI    (BIT(13))
+#define EMAC_CH1_FBI_M  (EMAC_CH1_FBI_V << EMAC_CH1_FBI_S)
+#define EMAC_CH1_FBI_V  0x00000001U
+#define EMAC_CH1_FBI_S  13
+/** EMAC_CH1_ERI : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt This bit indicates that the DMA filled the first data
+ *  buffer of the packet This bit is cleared when the software writes 1 to this bit or
+ *  Bit 6 _RI_ of this register is set _whichever occurs earlier_
+ */
+#define EMAC_CH1_ERI    (BIT(14))
+#define EMAC_CH1_ERI_M  (EMAC_CH1_ERI_V << EMAC_CH1_ERI_S)
+#define EMAC_CH1_ERI_V  0x00000001U
+#define EMAC_CH1_ERI_S  14
+/** EMAC_CH1_AIS : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR
+ *  of the following when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[1]: Transmit Process Stopped Register 5[3]:
+ *  Transmit Jabber Timeout Register 5[4]: Receive FIFO Overflow Register 5[5]:
+ *  Transmit Underflow Register 5[7]: Receive Buffer Unavailable Register 5[8]: Receive
+ *  Process Stopped Register 5[9]: Receive Watchdog Timeout Register 5[10]: Early
+ *  Transmit Interrupt Register 5[13]: Fatal Bus Error Only unmasked bits affect the
+ *  Abnormal Interrupt Summary bit This is a sticky bit and must be cleared _by writing
+ *  1 to this bit_ each time a corresponding bit, which causes AIS to be set, is cleared
+ */
+#define EMAC_CH1_AIS    (BIT(15))
+#define EMAC_CH1_AIS_M  (EMAC_CH1_AIS_V << EMAC_CH1_AIS_S)
+#define EMAC_CH1_AIS_V  0x00000001U
+#define EMAC_CH1_AIS_S  15
+/** EMAC_CH1_NIS : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of
+ *  the following bits when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[0]: Transmit Interrupt Register 5[2]:
+ *  Transmit Buffer Unavailable Register 5[6]: Receive Interrupt Register 5[14]: Early
+ *  Receive Interrupt Only unmasked bits _interrupts for which interrupt enable is set
+ *  in Register 7_ affect the Normal Interrupt Summary bit This is a sticky bit and
+ *  must be cleared _by writing 1 to this bit_ each time a corresponding bit, which
+ *  causes NIS to be set, is cleared
+ */
+#define EMAC_CH1_NIS    (BIT(16))
+#define EMAC_CH1_NIS_M  (EMAC_CH1_NIS_V << EMAC_CH1_NIS_S)
+#define EMAC_CH1_NIS_V  0x00000001U
+#define EMAC_CH1_NIS_S  16
+/** EMAC_CH1_RS : RO; bitpos: [19:17]; default: 0;
+ *  Receive Process State This field indicates the Receive DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Receive Command
+ *  issued 3’b001: Running: Fetching Receive Transfer Descriptor 3’b010: Reserved for
+ *  future use 3’b011: Running: Waiting for receive packet 3’b100: Suspended: Receive
+ *  Descriptor Unavailable 3’b101: Running: Closing Receive Descriptor 3’b110:
+ *  TIME_STAMP write state 3’b111: Running: Transferring the receive packet data from
+ *  receive buffer to host memory
+ */
+#define EMAC_CH1_RS    0x00000007U
+#define EMAC_CH1_RS_M  (EMAC_CH1_RS_V << EMAC_CH1_RS_S)
+#define EMAC_CH1_RS_V  0x00000007U
+#define EMAC_CH1_RS_S  17
+/** EMAC_CH1_TS : RO; bitpos: [22:20]; default: 0;
+ *  Transmit Process State This field indicates the Transmit DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Transmit Command
+ *  issued 3’b001: Running: Fetching Transmit Transfer Descriptor 3’b010: Running:
+ *  Waiting for status 3’b011: Running: Reading Data from host memory buffer and
+ *  queuing it to transmit buffer _Tx FIFO_ 3’b100: TIME_STAMP write state 3’b101:
+ *  Reserved for future use 3’b110: Suspended: Transmit Descriptor Unavailable or
+ *  Transmit Buffer Underflow 3’b111: Running: Closing Transmit Descriptor
+ */
+#define EMAC_CH1_TS    0x00000007U
+#define EMAC_CH1_TS_M  (EMAC_CH1_TS_V << EMAC_CH1_TS_S)
+#define EMAC_CH1_TS_V  0x00000007U
+#define EMAC_CH1_TS_S  20
+/** EMAC_CH1_EB : RO; bitpos: [25:23]; default: 0;
+ *  Error Bits This field indicates the type of error that caused a Bus Error, for
+ *  example, error response on the AHB or AXI interface This field is valid only when
+ *  Bit 13 _FBI_ is set This field does not generate an interrupt 0 0 0: Error during
+ *  Rx DMA Write Data Transfer 0 1 1: Error during Tx DMA Read Data Transfer 1 0 0:
+ *  Error during Rx DMA Descriptor Write Access 1 0 1: Error during Tx DMA Descriptor
+ *  Write Access 1 1 0: Error during Rx DMA Descriptor Read Access 1 1 1: Error during
+ *  Tx DMA Descriptor Read Access Note: 001 and 010 are reserved
+ */
+#define EMAC_CH1_EB    0x00000007U
+#define EMAC_CH1_EB_M  (EMAC_CH1_EB_V << EMAC_CH1_EB_S)
+#define EMAC_CH1_EB_V  0x00000007U
+#define EMAC_CH1_EB_S  23
+/** EMAC_CH1_GLI : RO; bitpos: [26]; default: 0;
+ *  EMAC Line Interface Interrupt When set, this bit reflects any of the following
+ *  interrupt events in the DWC_EMAC interfaces _if present and enabled in your
+ *  configuration_: PCS _TBI, RTBI, or SGMII_: Link change or autonegotiation complete
+ *  event SMII or RGMII: Link change event General Purpose Input Status _GPIS_: Any LL
+ *  or LH event on the gpi_i input ports To identify the exact cause of the interrupt,
+ *  the software must first read Bit 11 and Bits[2:0] of Register 14 _Interrupt Status
+ *  Register_ and then to clear the source of interrupt _which also clears the GLI
+ *  interrupt_, read any of the following corresponding registers: PCS _TBI, RTBI, or
+ *  SGMII_: Register 49 _AN Status Register_ SMII or RGMII: Register 54
+ *  _SGMII/RGMII/SMII Control and Status Register_ General Purpose Input _GPI_:
+ *  Register 56 _General Purpose IO Register_ The interrupt signal from the DWC_EMAC
+ *  subsystem _sbd_intr_o_ is high when this bit is high
+ */
+#define EMAC_CH1_GLI    (BIT(26))
+#define EMAC_CH1_GLI_M  (EMAC_CH1_GLI_V << EMAC_CH1_GLI_S)
+#define EMAC_CH1_GLI_V  0x00000001U
+#define EMAC_CH1_GLI_S  26
+/** EMAC_CH1_GMI : RO; bitpos: [27]; default: 0;
+ *  EMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the
+ *  DWC_EMAC The software must read the corresponding registers in the DWC_EMAC to get
+ *  the exact cause of the interrupt and clear the source of interrupt to make this bit
+ *  as 1’b0 The interrupt signal from the DWC_EMAC subsystem _sbd_intr_o_ is high when
+ *  this bit is high This bit is applicable only when the MAC Management Counters _MMC_
+ *  are enabled Otherwise, this bit is reserved
+ */
+#define EMAC_CH1_GMI    (BIT(27))
+#define EMAC_CH1_GMI_M  (EMAC_CH1_GMI_V << EMAC_CH1_GMI_S)
+#define EMAC_CH1_GMI_V  0x00000001U
+#define EMAC_CH1_GMI_S  27
+/** EMAC_CH1_GPI : RO; bitpos: [28]; default: 0;
+ *  EMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the
+ *  DWC_EMAC The software must read the PMT Control and Status Register in the MAC to
+ *  get the exact cause of interrupt and clear its source to reset this bit to 1’b0 The
+ *  interrupt signal from the DWC_EMAC subsystem _sbd_intr_o_ is high when this bit is
+ *  high This bit is applicable only when the Power Management feature is enabled
+ *  Otherwise, this bit is reserved Note: The GPI and pmt_intr_o interrupts are
+ *  generated in different clock domains
+ */
+#define EMAC_CH1_GPI    (BIT(28))
+#define EMAC_CH1_GPI_M  (EMAC_CH1_GPI_V << EMAC_CH1_GPI_S)
+#define EMAC_CH1_GPI_V  0x00000001U
+#define EMAC_CH1_GPI_S  28
+/** EMAC_CH1_TTI : RO; bitpos: [29]; default: 0;
+ *  Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp
+ *  Generator block of the DWC_EMAC The software must read the corresponding registers
+ *  in the DWC_EMAC to get the exact cause of the interrupt and clear its source to
+ *  reset this bit to 1'b0 When this bit is high, the interrupt signal from the
+ *  DWC_EMAC subsystem _sbd_intr_o_ is high This bit is applicable only when the IEEE
+ *  1588 Timestamp feature is enabled Otherwise, this bit is reserved
+ */
+#define EMAC_CH1_TTI    (BIT(29))
+#define EMAC_CH1_TTI_M  (EMAC_CH1_TTI_V << EMAC_CH1_TTI_S)
+#define EMAC_CH1_TTI_V  0x00000001U
+#define EMAC_CH1_TTI_S  29
+/** EMAC_CH1_GLPII_GTMSI : RO; bitpos: [30]; default: 0;
+ *  GTMSI: EMAC TMS Interrupt _for Channel 1 and Channel 2_ This bit indicates an
+ *  interrupt event in the traffic manager and scheduler logic of DWC_EMAC To reset
+ *  this bit, the software must read the corresponding registers _Channel Status
+ *  Register_ to get the exact cause of the interrupt and clear its source Note: GTMSI
+ *  status is given only in Channel 1 and Channel 2 DMA register when the AV feature is
+ *  enabled and corresponding additional transmit channels are present Otherwise, this
+ *  bit is reserved When this bit is high, the interrupt signal from the MAC
+ *  _sbd_intr_o_ is high
+ */
+#define EMAC_CH1_GLPII_GTMSI    (BIT(30))
+#define EMAC_CH1_GLPII_GTMSI_M  (EMAC_CH1_GLPII_GTMSI_V << EMAC_CH1_GLPII_GTMSI_S)
+#define EMAC_CH1_GLPII_GTMSI_V  0x00000001U
+#define EMAC_CH1_GLPII_GTMSI_S  30
+
+/** EMAC_CHANNEL1OPERATIONMODE_REG register
+ *  Establishes the Receive and Transmit operating modes and command
+ */
+#define EMAC_CHANNEL1OPERATIONMODE_REG (DR_REG_EMAC_BASE + 0x1118)
+/** EMAC_CH1_SR : R/W; bitpos: [1]; default: 0;
+ *  Start or Stop Receive When this bit is set, the Receive process is placed in the
+ *  Running state The DMA attempts to acquire the descriptor from the Receive list and
+ *  processes the incoming frames The descriptor acquisition is attempted from the
+ *  current position in the list, which is the address set by the Register 3 _Receive
+ *  Descriptor List Address Register_ or the position retained when the Receive process
+ *  was previously stopped If the DMA does not own the descriptor, reception is
+ *  suspended and Bit 7 _Receive Buffer Unavailable_ of Register 5 _Status Register_ is
+ *  set The Start Receive command is effective only when the reception has stopped If
+ *  the command is issued before setting Register 3 _Receive Descriptor List Address
+ *  Register_, the DMA behavior is unpredictable When this bit is cleared, the Rx DMA
+ *  operation is stopped after the transfer of the current frame The next descriptor
+ *  position in the Receive list is saved and becomes the current position after the
+ *  Receive process is restarted The Stop Receive command is effective only when the
+ *  Receive process is in either the Running _waiting for receive packet_ or in the
+ *  Suspended state Note: For information about how to pause the transmission, see
+ *  “Stopping and Starting Transmission” on page 715
+ */
+#define EMAC_CH1_SR    (BIT(1))
+#define EMAC_CH1_SR_M  (EMAC_CH1_SR_V << EMAC_CH1_SR_S)
+#define EMAC_CH1_SR_V  0x00000001U
+#define EMAC_CH1_SR_S  1
+/** EMAC_CH1_OSF : R/W; bitpos: [2]; default: 0;
+ *  Operate on Second Frame When this bit is set, it instructs the DMA to process the
+ *  second frame of the Transmit data even before the status for the first frame is
+ *  obtained
+ */
+#define EMAC_CH1_OSF    (BIT(2))
+#define EMAC_CH1_OSF_M  (EMAC_CH1_OSF_V << EMAC_CH1_OSF_S)
+#define EMAC_CH1_OSF_V  0x00000001U
+#define EMAC_CH1_OSF_S  2
+/** EMAC_CH1_RTC : R/W; bitpos: [4:3]; default: 0;
+ *  Receive Threshold Control These two bits control the threshold level of the MTL
+ *  Receive FIFO Transfer _request_ to DMA starts when the frame size within the MTL
+ *  Receive FIFO is larger than the threshold In addition, full frames with length less
+ *  than the threshold are automatically transferred The value of 11 is not applicable
+ *  if the configured Receive FIFO size is 128 bytes These bits are valid only when the
+ *  RSF bit is zero, and are ignored when the RSF bit is set to 1 00: 64 01: 32 10: 96
+ *  11: 128
+ */
+#define EMAC_CH1_RTC    0x00000003U
+#define EMAC_CH1_RTC_M  (EMAC_CH1_RTC_V << EMAC_CH1_RTC_S)
+#define EMAC_CH1_RTC_V  0x00000003U
+#define EMAC_CH1_RTC_S  3
+/** EMAC_CH1_DGF : R/W; bitpos: [5]; default: 0;
+ *  Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO,
+ *  that is, frames that are larger than the computed giant frame limit When reset, the
+ *  MAC does not drop the giant frames in the Rx FIFO Note: This bit is available in
+ *  the following configurations in which the giant frame status is not provided in Rx
+ *  status and giant frames are not dropped by default: Configurations in which IP
+ *  Checksum Offload _Type 1_ is selected in Rx Configurations in which the IPC Full
+ *  Checksum Offload Engine _Type 2_ is selected in Rx with normal descriptor format
+ *  Configurations in which the Advanced Timestamp feature is selected In all other
+ *  configurations, this bit is not used _reserved and always reset_
+ */
+#define EMAC_CH1_DGF    (BIT(5))
+#define EMAC_CH1_DGF_M  (EMAC_CH1_DGF_V << EMAC_CH1_DGF_S)
+#define EMAC_CH1_DGF_V  0x00000001U
+#define EMAC_CH1_DGF_S  5
+/** EMAC_CH1_FUF : R/W; bitpos: [6]; default: 0;
+ *  Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames
+ *  _that is, frames with no Error and length less than 64 bytes_ including padbytes
+ *  and CRC When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a
+ *  frame is already transferred because of the lower value of Receive Threshold, for
+ *  example, RTC = 01
+ */
+#define EMAC_CH1_FUF    (BIT(6))
+#define EMAC_CH1_FUF_M  (EMAC_CH1_FUF_V << EMAC_CH1_FUF_S)
+#define EMAC_CH1_FUF_V  0x00000001U
+#define EMAC_CH1_FUF_S  6
+/** EMAC_CH1_FEF : R/W; bitpos: [7]; default: 0;
+ *  Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error
+ *  status _CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or
+ *  overflow_ However, if the start byte _write_ pointer of a frame is already
+ *  transferred to the read controller side _in Threshold mode_, then the frame is not
+ *  dropped In the EMACMTL configuration in which the Frame Length FIFO is also enabled
+ *  during core configuration, the Rx FIFO drops the error frames if that frame's start
+ *  byte is not transferred _output_ on the ARI bus When the FEF bit is set, all frames
+ *  except runt error frames are forwarded to the DMA If the Bit 25 _RSF_ is set and
+ *  the Rx FIFO overflows when a partial frame is written, then the frame is dropped
+ *  irrespective of the FEF bit setting However, if the Bit 25 _RSF_ is reset and the
+ *  Rx FIFO overflows when a partial frame is written, then a partial frame may be
+ *  forwarded to the DMA Note: When FEF bit is reset, the giant frames are dropped if
+ *  the giant frame status is given in Rx Status _in Table 86 or Table 823_ in the
+ *  following configurations: The IP checksum engine _Type 1_ and full checksum offload
+ *  engine _Type 2_ are not selected The advanced timestamp feature is not selected but
+ *  the extended status is selected The extended status is available with the following
+ *  features: 	L3L4 filter in EMACCORE or EMACMTL configurations 	Full checksum offload
+ *  engine _Type 2_ with enhanced descriptor format in the EMACDMA, EMACAHB, or EMACAXI
+ *  configurations
+ */
+#define EMAC_CH1_FEF    (BIT(7))
+#define EMAC_CH1_FEF_M  (EMAC_CH1_FEF_V << EMAC_CH1_FEF_S)
+#define EMAC_CH1_FEF_V  0x00000001U
+#define EMAC_CH1_FEF_S  7
+/** EMAC_CH1_EFC : R/W; bitpos: [8]; default: 0;
+ *  Enable HW Flow Control When this bit is set, the flow control signal operation
+ *  based on the filllevel of Rx FIFO is enabled When reset, the flow control operation
+ *  is disabled This bit is not used _reserved and always reset_ when the Rx FIFO is
+ *  less than 4 KB
+ */
+#define EMAC_CH1_EFC    (BIT(8))
+#define EMAC_CH1_EFC_M  (EMAC_CH1_EFC_V << EMAC_CH1_EFC_S)
+#define EMAC_CH1_EFC_V  0x00000001U
+#define EMAC_CH1_EFC_S  8
+/** EMAC_CH1_RFA : R/W; bitpos: [10:9]; default: 0;
+ *  Threshold for Activating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Fill level of Rx FIFO_ at which the flow control is
+ *  activated 00: Full minus 1 KB, that is, FULL—1KB 01: Full minus 2 KB, that is,
+ *  FULL—2KB 10: Full minus 3 KB, that is, FULL—3KB 11: Full minus 4 KB, that is,
+ *  FULL—4KB These values are applicable only to Rx FIFOs of 4 KB or more and when Bit
+ *  8 _EFC_ is set high If the Rx FIFO is 8 KB or more, an additional Bit _RFA_2_ is
+ *  used for more threshold levels as described in Bit 23 These bits are reserved and
+ *  readonly when the depth of Rx FIFO is less than 4 KB Note: When FIFO size is
+ *  exactly 4 KB, although the DWC_EMAC allows you to program the value of these bits
+ *  to 11, the software should not program these bits to 2'b11 The value 2'b11 means
+ *  flow control on FIFO empty condition
+ */
+#define EMAC_CH1_RFA    0x00000003U
+#define EMAC_CH1_RFA_M  (EMAC_CH1_RFA_V << EMAC_CH1_RFA_S)
+#define EMAC_CH1_RFA_V  0x00000003U
+#define EMAC_CH1_RFA_S  9
+/** EMAC_CH1_RFD : R/W; bitpos: [12:11]; default: 0;
+ *  Threshold for Deactivating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Filllevel of Rx FIFO_ at which the flow control is
+ *  deasserted after activation 00: Full minus 1 KB, that is, FULL — 1 KB 01: Full
+ *  minus 2 KB, that is, FULL — 2 KB 10: Full minus 3 KB, that is, FULL — 3 KB 11: Full
+ *  minus 4 KB, that is, FULL — 4 KB The deassertion is effective only after flow
+ *  control is asserted If the Rx FIFO is 8 KB or more, an additional Bit _RFD_2_ is
+ *  used for more threshold levels as described in Bit 22 These bits are reserved and
+ *  readonly when the Rx FIFO depth is less than 4 KB Note: For proper flow control,
+ *  the value programmed in the “RFD_2, RFD” fields should be equal to or more than the
+ *  value programmed in the “RFA_2, RFA” fields
+ */
+#define EMAC_CH1_RFD    0x00000003U
+#define EMAC_CH1_RFD_M  (EMAC_CH1_RFD_V << EMAC_CH1_RFD_S)
+#define EMAC_CH1_RFD_V  0x00000003U
+#define EMAC_CH1_RFD_S  11
+/** EMAC_CH1_ST : R/W; bitpos: [13]; default: 0;
+ *  Start or Stop Transmission Command When this bit is set, transmission is placed in
+ *  the Running state, and the DMA checks the Transmit List at the current position for
+ *  a frame to be transmitted Descriptor acquisition is attempted either from the
+ *  current position in the list, which is the Transmit List Base Address set by
+ *  Register 4 _Transmit Descriptor List Address Register_, or from the position
+ *  retained when transmission was stopped previously If the DMA does not own the
+ *  current descriptor, transmission enters the Suspended state and Bit 2 _Transmit
+ *  Buffer Unavailable_ of Register 5 _Status Register_ is set The Start Transmission
+ *  command is effective only when transmission is stopped If the command is issued
+ *  before setting Register 4 _Transmit Descriptor List Address Register_, then the DMA
+ *  behavior is unpredictable When this bit is reset, the transmission process is
+ *  placed in the Stopped state after completing the transmission of the current frame
+ *  The Next Descriptor position in the Transmit List is saved, and it becomes the
+ *  current position when transmission is restarted To change the list address, you
+ *  need to program Register 4 _Transmit Descriptor List Address Register_ with a new
+ *  value when this bit is reset The new value is considered when this bit is set again
+ *  The stop transmission command is effective only when the transmission of the
+ *  current frame is complete or the transmission is in the Suspended state Note: For
+ *  information about how to pause the transmission, see “Stopping and Starting
+ *  Transmission” on page 715
+ */
+#define EMAC_CH1_ST    (BIT(13))
+#define EMAC_CH1_ST_M  (EMAC_CH1_ST_V << EMAC_CH1_ST_S)
+#define EMAC_CH1_ST_V  0x00000001U
+#define EMAC_CH1_ST_S  13
+/** EMAC_CH1_TTC : R/W; bitpos: [16:14]; default: 0;
+ *  Transmit Threshold Control These bits control the threshold level of the MTL
+ *  Transmit FIFO Transmission starts when the frame size within the MTL Transmit FIFO
+ *  is larger than the threshold In addition, full frames with a length less than the
+ *  threshold are also transmitted These bits are used only when Bit 21 _TSF_ is reset
+ *  000: 64 001: 128 010: 192 011: 256 100: 40 101: 32 110: 24 111: 16
+ */
+#define EMAC_CH1_TTC    0x00000007U
+#define EMAC_CH1_TTC_M  (EMAC_CH1_TTC_V << EMAC_CH1_TTC_S)
+#define EMAC_CH1_TTC_V  0x00000007U
+#define EMAC_CH1_TTC_S  14
+/** EMAC_CH1_FTF : R/W1S; bitpos: [20]; default: 0;
+ *  Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is
+ *  reset to its default values and thus all data in the Tx FIFO is lost or flushed
+ *  This bit is cleared internally when the flushing operation is complete The
+ *  Operation Mode register should not be written to until this bit is cleared The data
+ *  which is already accepted by the MAC transmitter is not flushed It is scheduled for
+ *  transmission and results in underflow and runt frame transmission Note: The flush
+ *  operation is complete only when the Tx FIFO is emptied of its contents and all the
+ *  pending Transmit Status of the transmitted frames are accepted by the host In order
+ *  to complete this flush operation, the PHY transmit clock _clk_tx_i_ is required to
+ *  be active 19:17		Reserved 	000	RO
+ */
+#define EMAC_CH1_FTF    (BIT(20))
+#define EMAC_CH1_FTF_M  (EMAC_CH1_FTF_V << EMAC_CH1_FTF_S)
+#define EMAC_CH1_FTF_V  0x00000001U
+#define EMAC_CH1_FTF_S  20
+/** EMAC_CH1_TSF : R/W; bitpos: [21]; default: 0;
+ *  Transmit Store and Forward When this bit is set, transmission starts when a full
+ *  frame resides in the MTL Transmit FIFO When this bit is set, the TTC values
+ *  specified in Bits [16:14] are ignored This bit should be changed only when the
+ *  transmission is stopped
+ */
+#define EMAC_CH1_TSF    (BIT(21))
+#define EMAC_CH1_TSF_M  (EMAC_CH1_TSF_V << EMAC_CH1_TSF_S)
+#define EMAC_CH1_TSF_V  0x00000001U
+#define EMAC_CH1_TSF_S  21
+/** EMAC_CH1_RFD_2 : R/W; bitpos: [22]; default: 0;
+ *  MSB of Threshold for Deactivating Flow Control If the DWC_EMAC is configured for Rx
+ *  FIFO size of 8 KB or more, this bit _when set_ provides additional threshold levels
+ *  for deactivating the flow control in both halfduplex and fullduplex modes This bit
+ *  _as Most Significant Bit_ along with the RFD _Bits [12:11]_ gives the following
+ *  thresholds for deactivating flow control: 100: Full minus 5 KB, that is, FULL — 5
+ *  KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that is, FULL —
+ *  7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB or less deep
+ */
+#define EMAC_CH1_RFD_2    (BIT(22))
+#define EMAC_CH1_RFD_2_M  (EMAC_CH1_RFD_2_V << EMAC_CH1_RFD_2_S)
+#define EMAC_CH1_RFD_2_V  0x00000001U
+#define EMAC_CH1_RFD_2_S  22
+/** EMAC_CH1_RFA_2 : R/W; bitpos: [23]; default: 0;
+ *  MSB of Threshold for Activating Flow Control If the DWC_EMAC is configured for an
+ *  Rx FIFO size of 8 KB or more, this bit _when set_ provides additional threshold
+ *  levels for activating the flow control in both half duplex and fullduplex modes
+ *  This bit _as Most Significant Bit_, along with the RFA _Bits [10:9]_, gives the
+ *  following thresholds for activating flow control: 100: Full minus 5 KB, that is,
+ *  FULL — 5 KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that
+ *  is, FULL — 7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB
+ *  or less deep
+ */
+#define EMAC_CH1_RFA_2    (BIT(23))
+#define EMAC_CH1_RFA_2_M  (EMAC_CH1_RFA_2_V << EMAC_CH1_RFA_2_S)
+#define EMAC_CH1_RFA_2_V  0x00000001U
+#define EMAC_CH1_RFA_2_S  23
+/** EMAC_CH1_DFF : R/W; bitpos: [24]; default: 0;
+ *  Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush
+ *  any frames because of the unavailability of receive descriptors or buffers as it
+ *  does normally when this bit is reset _See “Receive Process Suspended” on page 83_
+ *  This bit is reserved _and RO_ in the EMACMTL configuration
+ */
+#define EMAC_CH1_DFF    (BIT(24))
+#define EMAC_CH1_DFF_M  (EMAC_CH1_DFF_V << EMAC_CH1_DFF_S)
+#define EMAC_CH1_DFF_V  0x00000001U
+#define EMAC_CH1_DFF_S  24
+/** EMAC_CH1_RSF : R/W; bitpos: [25]; default: 0;
+ *  Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx
+ *  FIFO only after the complete frame has been written to it, ignoring the RTC bits
+ *  When this bit is reset, the Rx FIFO operates in the cutthrough mode, subject to the
+ *  threshold specified by the RTC bits
+ */
+#define EMAC_CH1_RSF    (BIT(25))
+#define EMAC_CH1_RSF_M  (EMAC_CH1_RSF_V << EMAC_CH1_RSF_S)
+#define EMAC_CH1_RSF_V  0x00000001U
+#define EMAC_CH1_RSF_S  25
+/** EMAC_CH1_DT : R/W; bitpos: [26]; default: 0;
+ *  Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does
+ *  not drop the frames which only have errors detected by the Receive Checksum Offload
+ *  engine Such frames do not have any errors _including FCS error_ in the Ethernet
+ *  frame received by the MAC but have errors only in the encapsulated payload When
+ *  this bit is reset, all error frames are dropped if the FEF bit is reset If the IPC
+ *  Full Checksum Offload Engine _Type 2_ is disabled, this bit is reserved _RO with
+ *  value 1'b0_
+ */
+#define EMAC_CH1_DT    (BIT(26))
+#define EMAC_CH1_DT_M  (EMAC_CH1_DT_V << EMAC_CH1_DT_S)
+#define EMAC_CH1_DT_V  0x00000001U
+#define EMAC_CH1_DT_S  26
+
+/** EMAC_CHANNEL1INTERRUPTENABLE_REG register
+ *  Enables the interrupts reported by the Status Register
+ */
+#define EMAC_CHANNEL1INTERRUPTENABLE_REG (DR_REG_EMAC_BASE + 0x111c)
+/** EMAC_CH1_TIE : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Transmit Interrupt is enabled When this bit is reset, the Transmit
+ *  Interrupt is disabled The sbd_intr_o interrupt is generated as shown in Figure 61
+ *  It is asserted only when the TTI, GPI, GMI, GLI, or GLPII bit of the DMA Status
+ *  register is asserted, or when the NIS or AIS Status bit is asserted and the
+ *  corresponding Interrupt Enable bits _NIE or AIE_ are enabled
+ */
+#define EMAC_CH1_TIE    (BIT(0))
+#define EMAC_CH1_TIE_M  (EMAC_CH1_TIE_V << EMAC_CH1_TIE_S)
+#define EMAC_CH1_TIE_V  0x00000001U
+#define EMAC_CH1_TIE_S  0
+/** EMAC_CH1_TSE : R/W; bitpos: [1]; default: 0;
+ *  Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Transmission Stopped Interrupt is enabled When this bit is reset, the
+ *  Transmission Stopped Interrupt is disabled
+ */
+#define EMAC_CH1_TSE    (BIT(1))
+#define EMAC_CH1_TSE_M  (EMAC_CH1_TSE_V << EMAC_CH1_TSE_S)
+#define EMAC_CH1_TSE_V  0x00000001U
+#define EMAC_CH1_TSE_S  1
+/** EMAC_CH1_TUE : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt
+ *  Summary Enable _Bit 16_, the Transmit Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled
+ */
+#define EMAC_CH1_TUE    (BIT(2))
+#define EMAC_CH1_TUE_M  (EMAC_CH1_TUE_V << EMAC_CH1_TUE_S)
+#define EMAC_CH1_TUE_V  0x00000001U
+#define EMAC_CH1_TUE_S  2
+/** EMAC_CH1_TJE : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Jabber Timeout Interrupt is enabled When this bit is
+ *  reset, the Transmit Jabber Timeout Interrupt is disabled
+ */
+#define EMAC_CH1_TJE    (BIT(3))
+#define EMAC_CH1_TJE_M  (EMAC_CH1_TJE_V << EMAC_CH1_TJE_S)
+#define EMAC_CH1_TJE_V  0x00000001U
+#define EMAC_CH1_TJE_S  3
+/** EMAC_CH1_OVE : R/W; bitpos: [4]; default: 0;
+ *  Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Receive Overflow Interrupt is enabled When this bit is reset,
+ *  the Overflow Interrupt is disabled
+ */
+#define EMAC_CH1_OVE    (BIT(4))
+#define EMAC_CH1_OVE_M  (EMAC_CH1_OVE_V << EMAC_CH1_OVE_S)
+#define EMAC_CH1_OVE_V  0x00000001U
+#define EMAC_CH1_OVE_S  4
+/** EMAC_CH1_UNE : R/W; bitpos: [5]; default: 0;
+ *  Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Underflow Interrupt is enabled When this bit is
+ *  reset, the Underflow Interrupt is disabled
+ */
+#define EMAC_CH1_UNE    (BIT(5))
+#define EMAC_CH1_UNE_M  (EMAC_CH1_UNE_V << EMAC_CH1_UNE_S)
+#define EMAC_CH1_UNE_V  0x00000001U
+#define EMAC_CH1_UNE_S  5
+/** EMAC_CH1_RIE : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Receive Interrupt is enabled When this bit is reset, the Receive
+ *  Interrupt is disabled
+ */
+#define EMAC_CH1_RIE    (BIT(6))
+#define EMAC_CH1_RIE_M  (EMAC_CH1_RIE_V << EMAC_CH1_RIE_S)
+#define EMAC_CH1_RIE_V  0x00000001U
+#define EMAC_CH1_RIE_S  6
+/** EMAC_CH1_RUE : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Receive Buffer Unavailable Interrupt is disabled
+ */
+#define EMAC_CH1_RUE    (BIT(7))
+#define EMAC_CH1_RUE_M  (EMAC_CH1_RUE_V << EMAC_CH1_RUE_S)
+#define EMAC_CH1_RUE_V  0x00000001U
+#define EMAC_CH1_RUE_S  7
+/** EMAC_CH1_RSE : R/W; bitpos: [8]; default: 0;
+ *  Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Receive Stopped Interrupt is enabled When this bit is reset, the
+ *  Receive Stopped Interrupt is disabled
+ */
+#define EMAC_CH1_RSE    (BIT(8))
+#define EMAC_CH1_RSE_M  (EMAC_CH1_RSE_V << EMAC_CH1_RSE_S)
+#define EMAC_CH1_RSE_V  0x00000001U
+#define EMAC_CH1_RSE_S  8
+/** EMAC_CH1_RWE : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Watchdog Timeout Interrupt is enabled When
+ *  this bit is reset, the Receive Watchdog Timeout Interrupt is disabled
+ */
+#define EMAC_CH1_RWE    (BIT(9))
+#define EMAC_CH1_RWE_M  (EMAC_CH1_RWE_V << EMAC_CH1_RWE_S)
+#define EMAC_CH1_RWE_V  0x00000001U
+#define EMAC_CH1_RWE_S  9
+/** EMAC_CH1_ETE : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Early Transmit Interrupt is enabled When this bit is
+ *  reset, the Early Transmit Interrupt is disabled
+ */
+#define EMAC_CH1_ETE    (BIT(10))
+#define EMAC_CH1_ETE_M  (EMAC_CH1_ETE_V << EMAC_CH1_ETE_S)
+#define EMAC_CH1_ETE_V  0x00000001U
+#define EMAC_CH1_ETE_S  10
+/** EMAC_CH1_FBE : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Fatal Bus Error Interrupt is enabled When this bit is reset, the
+ *  Fatal Bus Error Enable Interrupt is disabled 12:11		Reserved	00	RO
+ */
+#define EMAC_CH1_FBE    (BIT(13))
+#define EMAC_CH1_FBE_M  (EMAC_CH1_FBE_V << EMAC_CH1_FBE_S)
+#define EMAC_CH1_FBE_V  0x00000001U
+#define EMAC_CH1_FBE_S  13
+/** EMAC_CH1_ERE : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary
+ *  Enable _Bit 16_, the Early Receive Interrupt is enabled When this bit is reset, the
+ *  Early Receive Interrupt is disabled
+ */
+#define EMAC_CH1_ERE    (BIT(14))
+#define EMAC_CH1_ERE_M  (EMAC_CH1_ERE_V << EMAC_CH1_ERE_S)
+#define EMAC_CH1_ERE_V  0x00000001U
+#define EMAC_CH1_ERE_S  14
+/** EMAC_CH1_AIE : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary
+ *  is enabled When this bit is reset, the abnormal interrupt summary is disabled This
+ *  bit enables the following interrupts in Register 5 _Status Register_: Register
+ *  5[1]: Transmit Process Stopped Register 5[3]: Transmit Jabber Timeout Register
+ *  5[4]: Receive Overflow Register 5[5]: Transmit Underflow Register 5[7]: Receive
+ *  Buffer Unavailable Register 5[8]: Receive Process Stopped Register 5[9]: Receive
+ *  Watchdog Timeout Register 5[10]: Early Transmit Interrupt Register 5[13]: Fatal Bus
+ *  Error
+ */
+#define EMAC_CH1_AIE    (BIT(15))
+#define EMAC_CH1_AIE_M  (EMAC_CH1_AIE_V << EMAC_CH1_AIE_S)
+#define EMAC_CH1_AIE_V  0x00000001U
+#define EMAC_CH1_AIE_S  15
+/** EMAC_CH1_NIE : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is
+ *  enabled When this bit is reset, normal interrupt summary is disabled This bit
+ *  enables the following interrupts in Register 5 _Status Register_: Register 5[0]:
+ *  Transmit Interrupt Register 5[2]: Transmit Buffer Unavailable Register 5[6]:
+ *  Receive Interrupt Register 5[14]: Early Receive Interrupt
+ */
+#define EMAC_CH1_NIE    (BIT(16))
+#define EMAC_CH1_NIE_M  (EMAC_CH1_NIE_V << EMAC_CH1_NIE_S)
+#define EMAC_CH1_NIE_V  0x00000001U
+#define EMAC_CH1_NIE_S  16
+
+/** EMAC_CHANNEL1MISSEDFRAMEANDBUFFEROVERFLOWCOUNTER_REG register
+ *  Contains the counters for discarded frames because no host Receive Descriptor was
+ *  available, and discarded frames because of Receive FIFO Overflow
+ */
+#define EMAC_CHANNEL1MISSEDFRAMEANDBUFFEROVERFLOWCOUNTER_REG (DR_REG_EMAC_BASE + 0x1120)
+/** EMAC_CH1_MISFRMCNT : R/W; bitpos: [15:0]; default: 0;
+ *  Missed Frame Counter This field indicates the number of frames missed by the
+ *  controller because of the Host Receive Buffer being unavailable This counter is
+ *  incremented each time the DMA discards an incoming frame The counter is cleared
+ *  when this register is read with mci_be_i[0] at 1’b1
+ */
+#define EMAC_CH1_MISFRMCNT    0x0000FFFFU
+#define EMAC_CH1_MISFRMCNT_M  (EMAC_CH1_MISFRMCNT_V << EMAC_CH1_MISFRMCNT_S)
+#define EMAC_CH1_MISFRMCNT_V  0x0000FFFFU
+#define EMAC_CH1_MISFRMCNT_S  0
+/** EMAC_CH1_MISCNTOVF : R/W; bitpos: [16]; default: 0;
+ *  Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame
+ *  Counter _Bits[15:0]_ overflows, that is, the DMA discards an incoming frame because
+ *  of the Host Receive Buffer being unavailable with the missed frame counter at
+ *  maximum value In such a scenario, the Missed frame counter is reset to allzeros and
+ *  this bit indicates that the rollover happened
+ */
+#define EMAC_CH1_MISCNTOVF    (BIT(16))
+#define EMAC_CH1_MISCNTOVF_M  (EMAC_CH1_MISCNTOVF_V << EMAC_CH1_MISCNTOVF_S)
+#define EMAC_CH1_MISCNTOVF_V  0x00000001U
+#define EMAC_CH1_MISCNTOVF_S  16
+/** EMAC_CH1_OVFFRMCNT : R/W; bitpos: [27:17]; default: 0;
+ *  Overflow Frame Counter This field indicates the number of frames missed by the
+ *  application This counter is incremented each time the MTL FIFO overflows The
+ *  counter is cleared when this register is read with mci_be_i[2] at 1’b1
+ */
+#define EMAC_CH1_OVFFRMCNT    0x000007FFU
+#define EMAC_CH1_OVFFRMCNT_M  (EMAC_CH1_OVFFRMCNT_V << EMAC_CH1_OVFFRMCNT_S)
+#define EMAC_CH1_OVFFRMCNT_V  0x000007FFU
+#define EMAC_CH1_OVFFRMCNT_S  17
+/** EMAC_CH1_OVFCNTOVF : R/W; bitpos: [28]; default: 0;
+ *  Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow
+ *  Frame Counter _Bits[27:17]_ overflows, that is, the Rx FIFO overflows with the
+ *  overflow frame counter at maximum value In such a scenario, the overflow frame
+ *  counter is reset to allzeros and this bit indicates that the rollover happened
+ */
+#define EMAC_CH1_OVFCNTOVF    (BIT(28))
+#define EMAC_CH1_OVFCNTOVF_M  (EMAC_CH1_OVFCNTOVF_V << EMAC_CH1_OVFCNTOVF_S)
+#define EMAC_CH1_OVFCNTOVF_V  0x00000001U
+#define EMAC_CH1_OVFCNTOVF_S  28
+
+/** EMAC_CHANNEL1RECEIVEINTERRUPTWATCHDOGTIMER_REG register
+ *  Watchdog timeout for Receive Interrupt _RI_ from DMA
+ */
+#define EMAC_CHANNEL1RECEIVEINTERRUPTWATCHDOGTIMER_REG (DR_REG_EMAC_BASE + 0x1124)
+/** EMAC_CH1_RIWT : R/W; bitpos: [7:0]; default: 0;
+ *  RI Watchdog Timer Count This bit indicates the number of system clock cycles
+ *  multiplied by 256 for which the watchdog timer is set The watchdog timer gets
+ *  triggered with the programmed value after the Rx DMA completes the transfer of a
+ *  frame for which the RI status bit is not set because of the setting in the
+ *  corresponding descriptor RDES1[31] When the watchdog timer runs out, the RI bit is
+ *  set and the timer is stopped The watchdog timer is reset when the RI bit is set
+ *  high because of automatic setting of RI as per RDES1[31] of any received frame
+ */
+#define EMAC_CH1_RIWT    0x000000FFU
+#define EMAC_CH1_RIWT_M  (EMAC_CH1_RIWT_V << EMAC_CH1_RIWT_S)
+#define EMAC_CH1_RIWT_V  0x000000FFU
+#define EMAC_CH1_RIWT_S  0
+
+/** EMAC_CHANNEL1SLOTFUNCTIONCONTROLANDSTATUS_REG register
+ *  Contains the control bits for slot function and its status for Channel 1 transmit
+ *  path
+ */
+#define EMAC_CHANNEL1SLOTFUNCTIONCONTROLANDSTATUS_REG (DR_REG_EMAC_BASE + 0x1130)
+/** EMAC_ESC : R/W; bitpos: [0]; default: 0;
+ *  Enable Slot Comparison When set, this bit enables the checking of the slot numbers,
+ *  programmed in the transmit descriptor, with the current reference given in Bits
+ *  [19:16] The DMA fetches the data from the corresponding buffer only when the slot
+ *  number is equal to the reference slot number or is ahead of the reference slot
+ *  number by one slot When reset, this bit disables the checking of the slot numbers
+ *  The DMA fetches the data immediately after the descriptor is processed
+ */
+#define EMAC_ESC    (BIT(0))
+#define EMAC_ESC_M  (EMAC_ESC_V << EMAC_ESC_S)
+#define EMAC_ESC_V  0x00000001U
+#define EMAC_ESC_S  0
+/** EMAC_ASC : R/W; bitpos: [1]; default: 0;
+ *  Advance Slot Check When set, this bit enables the DMA to fetch the data from the
+ *  buffer when the slot number _SLOTNUM_ programmed in the transmit descriptor is:
+ *  equal to the reference slot number given in Bits [19:16] or ahead of the reference
+ *  slot number by up to two slots This bit is applicable only when Bit 0 _ESC_ is set
+ */
+#define EMAC_ASC    (BIT(1))
+#define EMAC_ASC_M  (EMAC_ASC_V << EMAC_ASC_S)
+#define EMAC_ASC_V  0x00000001U
+#define EMAC_ASC_S  1
+/** EMAC_RSN : RO; bitpos: [19:16]; default: 0;
+ *  Reference Slot Number This field gives the current value of the reference slot
+ *  number in DMA used for comparison checking
+ */
+#define EMAC_RSN    0x0000000FU
+#define EMAC_RSN_M  (EMAC_RSN_V << EMAC_RSN_S)
+#define EMAC_RSN_V  0x0000000FU
+#define EMAC_RSN_S  16
+
+/** EMAC_CHANNEL1CURRENTHOSTTRANSMITDESCRIPTOR_REG register
+ *  Points to the start of current Transmit Descriptor read by the DMA
+ */
+#define EMAC_CHANNEL1CURRENTHOSTTRANSMITDESCRIPTOR_REG (DR_REG_EMAC_BASE + 0x1148)
+/** EMAC_CH1_CURTDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Descriptor Address Pointer
+ */
+#define EMAC_CH1_CURTDESAPTR    0xFFFFFFFFU
+#define EMAC_CH1_CURTDESAPTR_M  (EMAC_CH1_CURTDESAPTR_V << EMAC_CH1_CURTDESAPTR_S)
+#define EMAC_CH1_CURTDESAPTR_V  0xFFFFFFFFU
+#define EMAC_CH1_CURTDESAPTR_S  0
+
+/** EMAC_CHANNEL1CURRENTHOSTRECEIVEDESCRIPTOR_REG register
+ *  Points to the start of current Receive Descriptor read by the DMA
+ */
+#define EMAC_CHANNEL1CURRENTHOSTRECEIVEDESCRIPTOR_REG (DR_REG_EMAC_BASE + 0x114c)
+/** EMAC_CH1_CURRDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Descriptor Address Pointer
+ */
+#define EMAC_CH1_CURRDESAPTR    0xFFFFFFFFU
+#define EMAC_CH1_CURRDESAPTR_M  (EMAC_CH1_CURRDESAPTR_V << EMAC_CH1_CURRDESAPTR_S)
+#define EMAC_CH1_CURRDESAPTR_V  0xFFFFFFFFU
+#define EMAC_CH1_CURRDESAPTR_S  0
+
+/** EMAC_CHANNEL1CURRENTHOSTTRANSMITBUFFERADDRESS_REG register
+ *  Points to the current Transmit Buffer address read by the DMA
+ */
+#define EMAC_CHANNEL1CURRENTHOSTTRANSMITBUFFERADDRESS_REG (DR_REG_EMAC_BASE + 0x1150)
+/** EMAC_CH1_CURTBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Buffer Address Pointer
+ */
+#define EMAC_CH1_CURTBUFAPTR    0xFFFFFFFFU
+#define EMAC_CH1_CURTBUFAPTR_M  (EMAC_CH1_CURTBUFAPTR_V << EMAC_CH1_CURTBUFAPTR_S)
+#define EMAC_CH1_CURTBUFAPTR_V  0xFFFFFFFFU
+#define EMAC_CH1_CURTBUFAPTR_S  0
+
+/** EMAC_CHANNEL1CURRENTHOSTRECEIVEBUFFERADDRESS_REG register
+ *  Points to the current Receive Buffer address read by the DMA
+ */
+#define EMAC_CHANNEL1CURRENTHOSTRECEIVEBUFFERADDRESS_REG (DR_REG_EMAC_BASE + 0x1154)
+/** EMAC_CH1_CURRBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Buffer Address Pointer
+ */
+#define EMAC_CH1_CURRBUFAPTR    0xFFFFFFFFU
+#define EMAC_CH1_CURRBUFAPTR_M  (EMAC_CH1_CURRBUFAPTR_V << EMAC_CH1_CURRBUFAPTR_S)
+#define EMAC_CH1_CURRBUFAPTR_V  0xFFFFFFFFU
+#define EMAC_CH1_CURRBUFAPTR_S  0
+
+/** EMAC_CHANNEL1CBSCONTROL_REG register
+ *  Controls the Channel 1 credit shaping operation on the transmit path
+ */
+#define EMAC_CHANNEL1CBSCONTROL_REG (DR_REG_EMAC_BASE + 0x1160)
+/** EMAC_CH1_CBSD : R/W; bitpos: [0]; default: 0;
+ *  CreditBased Shaper Disable When set, the MAC disables the creditbased shaper
+ *  algorithm for Channel 1 traffic and makes the traffic management algorithm to
+ *  strict priority for Channel 1 over Channel 0 When reset, the creditbased shaper
+ *  algorithm schedules the traffic in Channel 1 for transmission
+ */
+#define EMAC_CH1_CBSD    (BIT(0))
+#define EMAC_CH1_CBSD_M  (EMAC_CH1_CBSD_V << EMAC_CH1_CBSD_S)
+#define EMAC_CH1_CBSD_V  0x00000001U
+#define EMAC_CH1_CBSD_S  0
+/** EMAC_CH1_CC : R/W; bitpos: [1]; default: 0;
+ *  Credit Control When reset, the accumulated credit parameter in the creditbased
+ *  shaper algorithm logic is set to zero when there is positive credit and no frame to
+ *  transmit in Channel 1 When there is no frame waiting in Channel 1 and other channel
+ *  is transmitting, no credit is accumulated When set, the accumulated credit
+ *  parameter in the creditbased shaper algorithm logic is not reset to zero when there
+ *  is positive credit and no frame to transmit in Channel 1 The credit accumulates
+ *  even when there is no frame waiting in Channel 1 and another channel is transmitting
+ */
+#define EMAC_CH1_CC    (BIT(1))
+#define EMAC_CH1_CC_M  (EMAC_CH1_CC_V << EMAC_CH1_CC_S)
+#define EMAC_CH1_CC_V  0x00000001U
+#define EMAC_CH1_CC_S  1
+/** EMAC_CH1_SLC : R/W; bitpos: [6:4]; default: 0;
+ *  Slot Count The software can program the number of slots _of duration 125 microsec_
+ *  over which the average transmitted bits per slot _provided in the CBS Status
+ *  register_ need to be computed for Channel 1 when the creditbased shaper algorithm
+ *  is enabled The encoding is as follows: 3'b000: 1 Slot 3'b001: 2 Slots 3'b010: 4
+ *  Slots 3'b011: 8 Slots 3'b100: 16 Slots 3'b1013'b111: Reserved
+ */
+#define EMAC_CH1_SLC    0x00000007U
+#define EMAC_CH1_SLC_M  (EMAC_CH1_SLC_V << EMAC_CH1_SLC_S)
+#define EMAC_CH1_SLC_V  0x00000007U
+#define EMAC_CH1_SLC_S  4
+/** EMAC_CH1_ABPSSIE : R/W; bitpos: [17]; default: 0;
+ *  Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts an
+ *  interrupt _sbd_intr_o or mci_intr_o_ when the average bits per slot status is
+ *  updated _Bit 17 _ABSU_ in Register 89_ for Channel 1 When this bit is cleared,
+ *  interrupt is not asserted for such an event
+ */
+#define EMAC_CH1_ABPSSIE    (BIT(17))
+#define EMAC_CH1_ABPSSIE_M  (EMAC_CH1_ABPSSIE_V << EMAC_CH1_ABPSSIE_S)
+#define EMAC_CH1_ABPSSIE_V  0x00000001U
+#define EMAC_CH1_ABPSSIE_S  17
+
+/** EMAC_CHANNEL1CBSSTATUS_REG register
+ *  Provides the average traffic transmitted in Channel 1
+ */
+#define EMAC_CHANNEL1CBSSTATUS_REG (DR_REG_EMAC_BASE + 0x1164)
+/** EMAC_CH1_ABS : RO; bitpos: [16:0]; default: 0;
+ *  Average Bits per Slot This field contains the average transmitted bits per slot
+ *  This field is computed over programmed number of slots _SLC bits in the CBS Control
+ *  Register_ for Channel 1 traffic The maximum value is 0x30D4 for 100 Mbps and
+ *  0x1E848 for 1000 Mbps
+ */
+#define EMAC_CH1_ABS    0x0001FFFFU
+#define EMAC_CH1_ABS_M  (EMAC_CH1_ABS_V << EMAC_CH1_ABS_S)
+#define EMAC_CH1_ABS_V  0x0001FFFFU
+#define EMAC_CH1_ABS_S  0
+/** EMAC_CH1_ABSU : RO; bitpos: [17]; default: 0;
+ *  ABS Updated When set, this bit indicates that the MAC has updated the ABS value
+ *  This bit is cleared when the application reads the ABS value
+ */
+#define EMAC_CH1_ABSU    (BIT(17))
+#define EMAC_CH1_ABSU_M  (EMAC_CH1_ABSU_V << EMAC_CH1_ABSU_S)
+#define EMAC_CH1_ABSU_V  0x00000001U
+#define EMAC_CH1_ABSU_S  17
+
+/** EMAC_CHANNEL1IDLESLOPECREDIT_REG register
+ *  Contains the idleSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 1
+ */
+#define EMAC_CHANNEL1IDLESLOPECREDIT_REG (DR_REG_EMAC_BASE + 0x1168)
+/** EMAC_CH1_ISC : R/W; bitpos: [13:0]; default: 0;
+ *  idleSlopeCredit This field contains the idleSlopeCredit value required for the
+ *  creditbased shaper algorithm for Channel 1 This is the rate of change of credit in
+ *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+ *  credit is increasing The software should program this field with computed credit in
+ *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+ *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode
+ */
+#define EMAC_CH1_ISC    0x00003FFFU
+#define EMAC_CH1_ISC_M  (EMAC_CH1_ISC_V << EMAC_CH1_ISC_S)
+#define EMAC_CH1_ISC_V  0x00003FFFU
+#define EMAC_CH1_ISC_S  0
+
+/** EMAC_CHANNEL1SENDSLOPECREDIT_REG register
+ *  Contains the sendSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 1
+ */
+#define EMAC_CHANNEL1SENDSLOPECREDIT_REG (DR_REG_EMAC_BASE + 0x116c)
+/** EMAC_CH1_SSC : R/W; bitpos: [13:0]; default: 0;
+ *  sendSlopeCredit This field contains the sendSlopeCredit value required for
+ *  creditbased shaper algorithm for Channel 1 This is the rate of change of credit in
+ *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+ *  credit is decreasing The software should program this field with computed credit in
+ *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+ *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode This field should be
+ *  programmed with absolute sendSlopeCredit value The creditbased shaper logic
+ *  subtracts it from the accumulated credit when Channel 1 is selected for transmission
+ */
+#define EMAC_CH1_SSC    0x00003FFFU
+#define EMAC_CH1_SSC_M  (EMAC_CH1_SSC_V << EMAC_CH1_SSC_S)
+#define EMAC_CH1_SSC_V  0x00003FFFU
+#define EMAC_CH1_SSC_S  0
+
+/** EMAC_CHANNEL1HICREDIT_REG register
+ *  Contains the hiCredit value required for the creditbased shaper algorithm for
+ *  Channel 1
+ */
+#define EMAC_CHANNEL1HICREDIT_REG (DR_REG_EMAC_BASE + 0x1170)
+/** EMAC_CH1_HC : R/W; bitpos: [28:0]; default: 0;
+ *  hiCredit This field contains the hiCredit value required for the creditbased shaper
+ *  algorithm for Channel 1 This is the maximum value that can be accumulated in the
+ *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+ *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+ *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+ *  0x0800_0000
+ */
+#define EMAC_CH1_HC    0x1FFFFFFFU
+#define EMAC_CH1_HC_M  (EMAC_CH1_HC_V << EMAC_CH1_HC_S)
+#define EMAC_CH1_HC_V  0x1FFFFFFFU
+#define EMAC_CH1_HC_S  0
+
+/** EMAC_CHANNEL1LOCREDIT_REG register
+ *  Contains the loCredit value required for the creditbased shaper algorithm for
+ *  Channel 1
+ */
+#define EMAC_CHANNEL1LOCREDIT_REG (DR_REG_EMAC_BASE + 0x1174)
+/** EMAC_CH1_LC : R/W; bitpos: [28:0]; default: 536870911;
+ *  loCredit This field contains the loCredit value required for the creditbased shaper
+ *  algorithm for Channel 1 This is the minimum value that can be accumulated in the
+ *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+ *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+ *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+ *  0x0800_0000 The programmed value is 2's complement _negative number_, that is,
+ *  0xF800_0000
+ */
+#define EMAC_CH1_LC    0x1FFFFFFFU
+#define EMAC_CH1_LC_M  (EMAC_CH1_LC_V << EMAC_CH1_LC_S)
+#define EMAC_CH1_LC_V  0x1FFFFFFFU
+#define EMAC_CH1_LC_S  0
+
+/** EMAC_CHANNEL2BUSMODE_REG register
+ *  Controls the Host Interface mode for Channel 2
+ */
+#define EMAC_CHANNEL2BUSMODE_REG (DR_REG_EMAC_BASE + 0x1200)
+/** EMAC_CH2_SWR : R/W; bitpos: [0]; default: 1;
+ *  Software Reset When this bit is set, the MAC DMA Controller resets the logic and
+ *  all internal registers of the MAC It is cleared automatically after the reset
+ *  operation is complete in all of the DWC_EMAC clock domains Before reprogramming any
+ *  register of the DWC_EMAC, you should read a zero _0_ value in this bit Note: The
+ *  Software reset function is driven only by this bit Bit 0 of Register 64 _Channel 1
+ *  Bus Mode Register_ or Register 128 _Channel 2 Bus Mode Register_ has no impact on
+ *  the Software reset function The reset operation is completed only when all resets
+ *  in all active clock domains are deasserted Therefore, it is essential that all PHY
+ *  inputs clocks _applicable for the selected PHY interface_ are present for the
+ *  software reset completion The time to complete the software reset operation depends
+ *  on the frequency of the slowest active clock
+ */
+#define EMAC_CH2_SWR    (BIT(0))
+#define EMAC_CH2_SWR_M  (EMAC_CH2_SWR_V << EMAC_CH2_SWR_S)
+#define EMAC_CH2_SWR_V  0x00000001U
+#define EMAC_CH2_SWR_S  0
+/** EMAC_CH2_DA : R/W; bitpos: [1]; default: 0;
+ *  DMA Arbitration Scheme This bit specifies the arbitration scheme between the
+ *  transmit and receive paths of Channel 2 0: Weighted roundrobin with Rx:Tx or Tx:Rx
+ *  The priority between the paths is according to the priority specified in Bits
+ *  [15:14] _PR_ and priority weights specified in Bit 27 _TXPR_ 1: Fixed priority The
+ *  transmit path has priority over receive path when Bit 27 _TXPR_ is set Otherwise,
+ *  receive path has priority over the transmit path In the EMACAXI configuration,
+ *  these bits are reserved and are readonly _RO_ For more information about the
+ *  priority scheme between the transmit and receive paths, see Table 412 in “DMA
+ *  Arbiter Functions” on page 167
+ */
+#define EMAC_CH2_DA    (BIT(1))
+#define EMAC_CH2_DA_M  (EMAC_CH2_DA_V << EMAC_CH2_DA_S)
+#define EMAC_CH2_DA_V  0x00000001U
+#define EMAC_CH2_DA_S  1
+/** EMAC_CH2_DSL : R/W; bitpos: [6:2]; default: 0;
+ *  Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword
+ *  _depending on the 32bit, 64bit, or 128bit bus_ to skip between two unchained
+ *  descriptors The address skipping starts from the end of current descriptor to the
+ *  start of next descriptor When the DSL value is equal to zero, the descriptor table
+ *  is taken as contiguous by the DMA in Ring mode
+ */
+#define EMAC_CH2_DSL    0x0000001FU
+#define EMAC_CH2_DSL_M  (EMAC_CH2_DSL_V << EMAC_CH2_DSL_S)
+#define EMAC_CH2_DSL_V  0x0000001FU
+#define EMAC_CH2_DSL_S  2
+/** EMAC_CH2_ATDS : R/W; bitpos: [7]; default: 0;
+ *  Alternate Descriptor Size When set, the size of the alternate descriptor _described
+ *  in “Alternate or Enhanced Descriptors” on page 545_ increases to 32 bytes _8
+ *  DWORDS_ This is required when the Advanced Timestamp feature or the IPC Full
+ *  Checksum Offload Engine _Type 2_ is enabled in the receiver The enhanced descriptor
+ *  is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine
+ *  _Type 2_ features are not enabled In such case, you can use the 16 bytes descriptor
+ *  to save 4 bytes of memory This bit is present only when you select the Alternate
+ *  Descriptor feature and any one of the following features during core configuration:
+ *  Advanced Timestamp feature IPC Full Checksum Offload Engine _Type 2_ feature
+ *  Otherwise, this bit is reserved and is readonly When reset, the descriptor size
+ *  reverts back to 4 DWORDs _16 bytes_ This bit preserves the backward compatibility
+ *  for the descriptor size In versions prior to 350a, the descriptor size is 16 bytes
+ *  for both normal and enhanced descriptors In version 350a, descriptor size is
+ *  increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum
+ *  Offload Engine _Type 2_ features
+ */
+#define EMAC_CH2_ATDS    (BIT(7))
+#define EMAC_CH2_ATDS_M  (EMAC_CH2_ATDS_V << EMAC_CH2_ATDS_S)
+#define EMAC_CH2_ATDS_V  0x00000001U
+#define EMAC_CH2_ATDS_S  7
+/** EMAC_CH2_PBL : R/W; bitpos: [13:8]; default: 1;
+ *  Programmable Burst Length These bits indicate the maximum number of beats to be
+ *  transferred in one DMA transaction This is the maximum value that is used in a
+ *  single block Read or Write The DMA always attempts to burst as specified in PBL
+ *  each time it starts a Burst transfer on the host bus PBL can be programmed with
+ *  permissible values of 1, 2, 4, 8, 16, and 32 Any other value results in undefined
+ *  behavior When USP is set high, this PBL value is applicable only for Tx DMA
+ *  transactions If the number of beats to be transferred is more than 32, then perform
+ *  the following steps: 1 Set the PBLx8 mode 2 Set the PBL For example, if the maximum
+ *  number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL
+ *  to 8 The PBL values have the following limitation: The maximum number of possible
+ *  beats _PBL_ is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and
+ *  the data bus width on the DMA The FIFO has a constraint that the maximum beat
+ *  supported is half the depth of the FIFO, except when specified For different data
+ *  bus widths and FIFO sizes, the valid PBL range _including x8 mode_ is provided in
+ *  Table 66 on page 382
+ */
+#define EMAC_CH2_PBL    0x0000003FU
+#define EMAC_CH2_PBL_M  (EMAC_CH2_PBL_V << EMAC_CH2_PBL_S)
+#define EMAC_CH2_PBL_V  0x0000003FU
+#define EMAC_CH2_PBL_S  8
+/** EMAC_CH2_PR : R/W; bitpos: [15:14]; default: 0;
+ *  Priority Ratio These bits control the priority ratio in the weighted roundrobin
+ *  arbitration between the Rx DMA and Tx DMA These bits are valid only when Bit 1 _DA_
+ *  is reset The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 _TXPR_ is
+ *  reset or set 00: The Priority Ratio is 1:1 01: The Priority Ratio is 2:1 10: The
+ *  Priority Ratio is 3:1 11: The Priority Ratio is 4:1 In the EMACAXI configuration,
+ *  these bits are reserved and readonly _RO_ For more information about the priority
+ *  scheme between the transmit and receive paths, see Table 412 in “DMA Arbiter
+ *  Functions” on page 167
+ */
+#define EMAC_CH2_PR    0x00000003U
+#define EMAC_CH2_PR_M  (EMAC_CH2_PR_V << EMAC_CH2_PR_S)
+#define EMAC_CH2_PR_V  0x00000003U
+#define EMAC_CH2_PR_S  14
+/** EMAC_CH2_FB : R/W; bitpos: [16]; default: 0;
+ *  Fixed Burst This bit controls whether the AHB or AXI master interface performs
+ *  fixed burst transfers or not When set, the AHB interface uses only SINGLE, INCR4,
+ *  INCR8, or INCR16 during start of the normal burst transfers When reset, the AHB or
+ *  AXI interface uses SINGLE and INCR burst transfer operations For more information,
+ *  see Bit 0 _UNDEF_ of the AXI Bus Mode register in the EMACAXI configuration
+ */
+#define EMAC_CH2_FB    (BIT(16))
+#define EMAC_CH2_FB_M  (EMAC_CH2_FB_V << EMAC_CH2_FB_S)
+#define EMAC_CH2_FB_V  0x00000001U
+#define EMAC_CH2_FB_S  16
+/** EMAC_CH2_RPBL : R/W; bitpos: [22:17]; default: 1;
+ *  Rx DMA PBL This field indicates the maximum number of beats to be transferred in
+ *  one Rx DMA transaction This is the maximum value that is used in a single block
+ *  Read or Write The Rx DMA always attempts to burst as specified in the RPBL bit each
+ *  time it starts a Burst transfer on the host bus You can program RPBL with values of
+ *  1, 2, 4, 8, 16, and 32 Any other value results in undefined behavior This field is
+ *  valid and applicable only when USP is set high
+ */
+#define EMAC_CH2_RPBL    0x0000003FU
+#define EMAC_CH2_RPBL_M  (EMAC_CH2_RPBL_V << EMAC_CH2_RPBL_S)
+#define EMAC_CH2_RPBL_V  0x0000003FU
+#define EMAC_CH2_RPBL_S  17
+/** EMAC_CH2_USP : R/W; bitpos: [23]; default: 0;
+ *  Use Separate PBL When set high, this bit configures the Rx DMA to use the value
+ *  configured in Bits [22:17] as PBL The PBL value in Bits [13:8] is applicable only
+ *  to the Tx DMA operations When reset to low, the PBL value in Bits [13:8] is
+ *  applicable for both DMA engines
+ */
+#define EMAC_CH2_USP    (BIT(23))
+#define EMAC_CH2_USP_M  (EMAC_CH2_USP_V << EMAC_CH2_USP_S)
+#define EMAC_CH2_USP_V  0x00000001U
+#define EMAC_CH2_USP_S  23
+/** EMAC_CH2_PBLX8 : R/W; bitpos: [24]; default: 0;
+ *  PBLx8 Mode When set high, this bit multiplies the programmed PBL value _Bits
+ *  [22:17] and Bits[13:8]_ eight times Therefore, the DMA transfers the data in 8, 16,
+ *  32, 64, 128, and 256 beats depending on the PBL value Note: This bit function is
+ *  not backward compatible Before release 350a, this bit was 4xPBL
+ */
+#define EMAC_CH2_PBLX8    (BIT(24))
+#define EMAC_CH2_PBLX8_M  (EMAC_CH2_PBLX8_V << EMAC_CH2_PBLX8_S)
+#define EMAC_CH2_PBLX8_V  0x00000001U
+#define EMAC_CH2_PBLX8_S  24
+/** EMAC_CH2_AAL : R/W; bitpos: [25]; default: 0;
+ *  AddressAligned Beats When this bit is set high and the FB bit is equal to 1, the
+ *  AHB or AXI interface generates all bursts aligned to the start address LS bits If
+ *  the FB bit is equal to 0, the first burst _accessing the start address of data
+ *  buffer_ is not aligned, but subsequent bursts are aligned to the address This bit
+ *  is valid only in the EMACAHB and EMACAXI configurations and is reserved _RO with
+ *  default value 0_ in all other configurations
+ */
+#define EMAC_CH2_AAL    (BIT(25))
+#define EMAC_CH2_AAL_M  (EMAC_CH2_AAL_V << EMAC_CH2_AAL_S)
+#define EMAC_CH2_AAL_V  0x00000001U
+#define EMAC_CH2_AAL_S  25
+/** EMAC_CH2_MB : R/W; bitpos: [26]; default: 0;
+ *  Mixed Burst When this bit is set high and the FB bit is low, the AHB master
+ *  interface starts all bursts of length more than 16 with INCR _undefined burst_,
+ *  whereas it reverts to fixed burst transfers _INCRx and SINGLE_ for burst length of
+ *  16 and less This bit is valid only in the EMACAHB configuration and reserved in all
+ *  other configuration
+ */
+#define EMAC_CH2_MB    (BIT(26))
+#define EMAC_CH2_MB_M  (EMAC_CH2_MB_V << EMAC_CH2_MB_S)
+#define EMAC_CH2_MB_V  0x00000001U
+#define EMAC_CH2_MB_S  26
+/** EMAC_CH2_TXPR : R/W; bitpos: [27]; default: 0;
+ *  Transmit Priority When set, this bit indicates that the transmit DMA has higher
+ *  priority than the receive DMA during arbitration for the systemside bus In the
+ *  EMACAXI configuration, this bit is reserved and readonly _RO_ For more information
+ *  about the priority scheme between the transmit and receive paths, see Table 412 in
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define EMAC_CH2_TXPR    (BIT(27))
+#define EMAC_CH2_TXPR_M  (EMAC_CH2_TXPR_V << EMAC_CH2_TXPR_S)
+#define EMAC_CH2_TXPR_V  0x00000001U
+#define EMAC_CH2_TXPR_S  27
+/** EMAC_CH2_PRWG : R/W; bitpos: [29:28]; default: 0;
+ *  Channel Priority Weights This field sets the priority weights for Channel 2 during
+ *  the roundrobin arbitration between the DMA channels for the system bus 00: The
+ *  priority weight is 1 01: The priority weight is 2 10: The priority weight is 3 11:
+ *  The priority weight is 4 This field is present in all DWC_EMAC configurations
+ *  except EMACAXI when you select the AV feature Otherwise, this field is reserved and
+ *  readonly _RO_ For more information about the priority weights of DMA channels, see
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define EMAC_CH2_PRWG    0x00000003U
+#define EMAC_CH2_PRWG_M  (EMAC_CH2_PRWG_V << EMAC_CH2_PRWG_S)
+#define EMAC_CH2_PRWG_V  0x00000003U
+#define EMAC_CH2_PRWG_S  28
+/** EMAC_CH2_RIB : R/W; bitpos: [31]; default: 0;
+ *  Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT
+ *  _Retry, Split, or Losing bus grant_, the AHB master interface rebuilds the pending
+ *  beats of any burst transfer initiated with INCRx The AHB master interface rebuilds
+ *  the beats with a combination of specified bursts with INCRx and SINGLE By default,
+ *  the AHB master interface rebuilds pending beats of an EBT with an unspecified
+ *  _INCR_ burst This bit is valid only in the EMACAHB configuration It is reserved in
+ *  all other configuration
+ */
+#define EMAC_CH2_RIB    (BIT(31))
+#define EMAC_CH2_RIB_M  (EMAC_CH2_RIB_V << EMAC_CH2_RIB_S)
+#define EMAC_CH2_RIB_V  0x00000001U
+#define EMAC_CH2_RIB_S  31
+
+/** EMAC_CHANNEL2TRANSMITPOLLDEMAND_REG register
+ *  Used by the host to instruct the DMA to poll the Transmit Descriptor list
+ */
+#define EMAC_CHANNEL2TRANSMITPOLLDEMAND_REG (DR_REG_EMAC_BASE + 0x1204)
+/** EMAC_CH2_TPD : RO; bitpos: [31:0]; default: 0;
+ *  Transmit Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 18 _Current Host Transmit Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  transmission returns to the Suspend state and Bit 2 _TU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the transmission resumes
+ */
+#define EMAC_CH2_TPD    0xFFFFFFFFU
+#define EMAC_CH2_TPD_M  (EMAC_CH2_TPD_V << EMAC_CH2_TPD_S)
+#define EMAC_CH2_TPD_V  0xFFFFFFFFU
+#define EMAC_CH2_TPD_S  0
+
+/** EMAC_CHANNEL2RECEIVEPOLLDEMAND_REG register
+ *  Used by the Host to instruct the DMA to poll the Receive Descriptor list
+ */
+#define EMAC_CHANNEL2RECEIVEPOLLDEMAND_REG (DR_REG_EMAC_BASE + 0x1208)
+/** EMAC_CH2_RPD : RO; bitpos: [31:0]; default: 0;
+ *  Receive Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 19 _Current Host Receive Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  reception returns to the Suspended state and Bit 7 _RU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the Rx DMA returns to the
+ *  active state
+ */
+#define EMAC_CH2_RPD    0xFFFFFFFFU
+#define EMAC_CH2_RPD_M  (EMAC_CH2_RPD_V << EMAC_CH2_RPD_S)
+#define EMAC_CH2_RPD_V  0xFFFFFFFFU
+#define EMAC_CH2_RPD_S  0
+
+/** EMAC_CHANNEL2RECEIVEDESCRIPTORLISTADDRESS_REG register
+ *  Points the DMA to the start of the Receive Descriptor list
+ */
+#define EMAC_CHANNEL2RECEIVEDESCRIPTORLISTADDRESS_REG (DR_REG_EMAC_BASE + 0x120c)
+/** EMAC_CH2_RDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Receive List This field contains the base address of the first descriptor
+ *  in the Receive Descriptor list The LSB bits _1:0, 2:0, or 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and internally taken as allzero by the DMA Therefore,
+ *  these LSB bits are readonly _RO_
+ */
+#define EMAC_CH2_RDESLA    0xFFFFFFFFU
+#define EMAC_CH2_RDESLA_M  (EMAC_CH2_RDESLA_V << EMAC_CH2_RDESLA_S)
+#define EMAC_CH2_RDESLA_V  0xFFFFFFFFU
+#define EMAC_CH2_RDESLA_S  0
+
+/** EMAC_CHANNEL2TRANSMITDESCRIPTORLISTADDRESS_REG register
+ *  Points the DMA to the start of the Transmit Descriptor List
+ */
+#define EMAC_CHANNEL2TRANSMITDESCRIPTORLISTADDRESS_REG (DR_REG_EMAC_BASE + 0x1210)
+/** EMAC_CH2_TDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Transmit List This field contains the base address of the first descriptor
+ *  in the Transmit Descriptor list The LSB bits _1:0, 2:0, 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and are internally taken as allzero by the DMA
+ *  Therefore, these LSB bits are readonly _RO_
+ */
+#define EMAC_CH2_TDESLA    0xFFFFFFFFU
+#define EMAC_CH2_TDESLA_M  (EMAC_CH2_TDESLA_V << EMAC_CH2_TDESLA_S)
+#define EMAC_CH2_TDESLA_V  0xFFFFFFFFU
+#define EMAC_CH2_TDESLA_S  0
+
+/** EMAC_CHANNEL2STATUS_REG register
+ *  The software driver _application_ reads this register during interrupt service
+ *  routine or polling to determine the status of the DMA Bits [29:26] are reserved for
+ *  the Channel 2 Status Register
+ */
+#define EMAC_CHANNEL2STATUS_REG (DR_REG_EMAC_BASE + 0x1214)
+/** EMAC_CH2_TI : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt This bit indicates that the frame transmission is complete When
+ *  transmission is complete, Bit 31 _OWN_ of TDES0 is reset, and the specific frame
+ *  status information is updated in the descriptor
+ */
+#define EMAC_CH2_TI    (BIT(0))
+#define EMAC_CH2_TI_M  (EMAC_CH2_TI_V << EMAC_CH2_TI_S)
+#define EMAC_CH2_TI_V  0x00000001U
+#define EMAC_CH2_TI_S  0
+/** EMAC_CH2_TPS : R/W; bitpos: [1]; default: 0;
+ *  Transmit Process Stopped This bit is set when the transmission is stopped
+ */
+#define EMAC_CH2_TPS    (BIT(1))
+#define EMAC_CH2_TPS_M  (EMAC_CH2_TPS_V << EMAC_CH2_TPS_S)
+#define EMAC_CH2_TPS_V  0x00000001U
+#define EMAC_CH2_TPS_S  1
+/** EMAC_CH2_TU : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Transmit List and the DMA cannot acquire it Transmission is
+ *  suspended Bits[22:20] explain the Transmit Process state transitions To resume
+ *  processing Transmit descriptors, the host should change the ownership of the
+ *  descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command
+ */
+#define EMAC_CH2_TU    (BIT(2))
+#define EMAC_CH2_TU_M  (EMAC_CH2_TU_V << EMAC_CH2_TU_S)
+#define EMAC_CH2_TU_V  0x00000001U
+#define EMAC_CH2_TU_S  2
+/** EMAC_CH2_TJT : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired,
+ *  which happens when the frame size exceeds 2,048 _10,240 bytes when the Jumbo frame
+ *  is enabled_ When the Jabber Timeout occurs, the transmission process is aborted and
+ *  placed in the Stopped state This causes the Transmit Jabber Timeout TDES0[14] flag
+ *  to assert
+ */
+#define EMAC_CH2_TJT    (BIT(3))
+#define EMAC_CH2_TJT_M  (EMAC_CH2_TJT_V << EMAC_CH2_TJT_S)
+#define EMAC_CH2_TJT_V  0x00000001U
+#define EMAC_CH2_TJT_S  3
+/** EMAC_CH2_OVF : R/W; bitpos: [4]; default: 0;
+ *  Receive Overflow This bit indicates that the Receive Buffer had an Overflow during
+ *  frame reception If the partial frame is transferred to the application, the
+ *  overflow status is set in RDES0[11]
+ */
+#define EMAC_CH2_OVF    (BIT(4))
+#define EMAC_CH2_OVF_M  (EMAC_CH2_OVF_V << EMAC_CH2_OVF_S)
+#define EMAC_CH2_OVF_V  0x00000001U
+#define EMAC_CH2_OVF_S  4
+/** EMAC_CH2_UNF : R/W; bitpos: [5]; default: 0;
+ *  Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow
+ *  during frame transmission Transmission is suspended and an Underflow Error TDES0[1]
+ *  is set
+ */
+#define EMAC_CH2_UNF    (BIT(5))
+#define EMAC_CH2_UNF_M  (EMAC_CH2_UNF_V << EMAC_CH2_UNF_S)
+#define EMAC_CH2_UNF_V  0x00000001U
+#define EMAC_CH2_UNF_S  5
+/** EMAC_CH2_RI : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt This bit indicates that the frame reception is complete When
+ *  reception is complete, the Bit 31 of RDES1 _Disable Interrupt on Completion_ is
+ *  reset in the last Descriptor, and the specific frame status information is updated
+ *  in the descriptor The reception remains in the Running state
+ */
+#define EMAC_CH2_RI    (BIT(6))
+#define EMAC_CH2_RI_M  (EMAC_CH2_RI_V << EMAC_CH2_RI_S)
+#define EMAC_CH2_RI_V  0x00000001U
+#define EMAC_CH2_RI_S  6
+/** EMAC_CH2_RU : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Receive List and the DMA cannot acquire it The Receive Process is
+ *  suspended To resume processing Receive descriptors, the host should change the
+ *  ownership of the descriptor and issue a Receive Poll Demand command If no Receive
+ *  Poll Demand is issued, the Receive Process resumes when the next recognized
+ *  incoming frame is received This bit is set only when the previous Receive
+ *  Descriptor is owned by the DMA
+ */
+#define EMAC_CH2_RU    (BIT(7))
+#define EMAC_CH2_RU_M  (EMAC_CH2_RU_V << EMAC_CH2_RU_S)
+#define EMAC_CH2_RU_V  0x00000001U
+#define EMAC_CH2_RU_S  7
+/** EMAC_CH2_RPS : R/W; bitpos: [8]; default: 0;
+ *  Receive Process Stopped This bit is asserted when the Receive Process enters the
+ *  Stopped state
+ */
+#define EMAC_CH2_RPS    (BIT(8))
+#define EMAC_CH2_RPS_M  (EMAC_CH2_RPS_V << EMAC_CH2_RPS_S)
+#define EMAC_CH2_RPS_V  0x00000001U
+#define EMAC_CH2_RPS_S  8
+/** EMAC_CH2_RWT : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog
+ *  Timer expired while receiving the current frame and the current frame is truncated
+ *  after the watchdog timeout
+ */
+#define EMAC_CH2_RWT    (BIT(9))
+#define EMAC_CH2_RWT_M  (EMAC_CH2_RWT_V << EMAC_CH2_RWT_S)
+#define EMAC_CH2_RWT_V  0x00000001U
+#define EMAC_CH2_RWT_S  9
+/** EMAC_CH2_ETI : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt This bit indicates that the frame to be transmitted is
+ *  fully transferred to the MTL Transmit FIFO
+ */
+#define EMAC_CH2_ETI    (BIT(10))
+#define EMAC_CH2_ETI_M  (EMAC_CH2_ETI_V << EMAC_CH2_ETI_S)
+#define EMAC_CH2_ETI_V  0x00000001U
+#define EMAC_CH2_ETI_S  10
+/** EMAC_CH2_FBI : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as
+ *  described in Bits [25:23] When this bit is set, the corresponding DMA engine
+ *  disables all of its bus accesses 12:11		Reserved	00	RO
+ */
+#define EMAC_CH2_FBI    (BIT(13))
+#define EMAC_CH2_FBI_M  (EMAC_CH2_FBI_V << EMAC_CH2_FBI_S)
+#define EMAC_CH2_FBI_V  0x00000001U
+#define EMAC_CH2_FBI_S  13
+/** EMAC_CH2_ERI : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt This bit indicates that the DMA filled the first data
+ *  buffer of the packet This bit is cleared when the software writes 1 to this bit or
+ *  Bit 6 _RI_ of this register is set _whichever occurs earlier_
+ */
+#define EMAC_CH2_ERI    (BIT(14))
+#define EMAC_CH2_ERI_M  (EMAC_CH2_ERI_V << EMAC_CH2_ERI_S)
+#define EMAC_CH2_ERI_V  0x00000001U
+#define EMAC_CH2_ERI_S  14
+/** EMAC_CH2_AIS : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR
+ *  of the following when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[1]: Transmit Process Stopped Register 5[3]:
+ *  Transmit Jabber Timeout Register 5[4]: Receive FIFO Overflow Register 5[5]:
+ *  Transmit Underflow Register 5[7]: Receive Buffer Unavailable Register 5[8]: Receive
+ *  Process Stopped Register 5[9]: Receive Watchdog Timeout Register 5[10]: Early
+ *  Transmit Interrupt Register 5[13]: Fatal Bus Error Only unmasked bits affect the
+ *  Abnormal Interrupt Summary bit This is a sticky bit and must be cleared _by writing
+ *  1 to this bit_ each time a corresponding bit, which causes AIS to be set, is cleared
+ */
+#define EMAC_CH2_AIS    (BIT(15))
+#define EMAC_CH2_AIS_M  (EMAC_CH2_AIS_V << EMAC_CH2_AIS_S)
+#define EMAC_CH2_AIS_V  0x00000001U
+#define EMAC_CH2_AIS_S  15
+/** EMAC_CH2_NIS : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of
+ *  the following bits when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[0]: Transmit Interrupt Register 5[2]:
+ *  Transmit Buffer Unavailable Register 5[6]: Receive Interrupt Register 5[14]: Early
+ *  Receive Interrupt Only unmasked bits _interrupts for which interrupt enable is set
+ *  in Register 7_ affect the Normal Interrupt Summary bit This is a sticky bit and
+ *  must be cleared _by writing 1 to this bit_ each time a corresponding bit, which
+ *  causes NIS to be set, is cleared
+ */
+#define EMAC_CH2_NIS    (BIT(16))
+#define EMAC_CH2_NIS_M  (EMAC_CH2_NIS_V << EMAC_CH2_NIS_S)
+#define EMAC_CH2_NIS_V  0x00000001U
+#define EMAC_CH2_NIS_S  16
+/** EMAC_CH2_RS : RO; bitpos: [19:17]; default: 0;
+ *  Receive Process State This field indicates the Receive DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Receive Command
+ *  issued 3’b001: Running: Fetching Receive Transfer Descriptor 3’b010: Reserved for
+ *  future use 3’b011: Running: Waiting for receive packet 3’b100: Suspended: Receive
+ *  Descriptor Unavailable 3’b101: Running: Closing Receive Descriptor 3’b110:
+ *  TIME_STAMP write state 3’b111: Running: Transferring the receive packet data from
+ *  receive buffer to host memory
+ */
+#define EMAC_CH2_RS    0x00000007U
+#define EMAC_CH2_RS_M  (EMAC_CH2_RS_V << EMAC_CH2_RS_S)
+#define EMAC_CH2_RS_V  0x00000007U
+#define EMAC_CH2_RS_S  17
+/** EMAC_CH2_TS : RO; bitpos: [22:20]; default: 0;
+ *  Transmit Process State This field indicates the Transmit DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Transmit Command
+ *  issued 3’b001: Running: Fetching Transmit Transfer Descriptor 3’b010: Running:
+ *  Waiting for status 3’b011: Running: Reading Data from host memory buffer and
+ *  queuing it to transmit buffer _Tx FIFO_ 3’b100: TIME_STAMP write state 3’b101:
+ *  Reserved for future use 3’b110: Suspended: Transmit Descriptor Unavailable or
+ *  Transmit Buffer Underflow 3’b111: Running: Closing Transmit Descriptor
+ */
+#define EMAC_CH2_TS    0x00000007U
+#define EMAC_CH2_TS_M  (EMAC_CH2_TS_V << EMAC_CH2_TS_S)
+#define EMAC_CH2_TS_V  0x00000007U
+#define EMAC_CH2_TS_S  20
+/** EMAC_CH2_EB : RO; bitpos: [25:23]; default: 0;
+ *  Error Bits This field indicates the type of error that caused a Bus Error, for
+ *  example, error response on the AHB or AXI interface This field is valid only when
+ *  Bit 13 _FBI_ is set This field does not generate an interrupt 0 0 0: Error during
+ *  Rx DMA Write Data Transfer 0 1 1: Error during Tx DMA Read Data Transfer 1 0 0:
+ *  Error during Rx DMA Descriptor Write Access 1 0 1: Error during Tx DMA Descriptor
+ *  Write Access 1 1 0: Error during Rx DMA Descriptor Read Access 1 1 1: Error during
+ *  Tx DMA Descriptor Read Access Note: 001 and 010 are reserved
+ */
+#define EMAC_CH2_EB    0x00000007U
+#define EMAC_CH2_EB_M  (EMAC_CH2_EB_V << EMAC_CH2_EB_S)
+#define EMAC_CH2_EB_V  0x00000007U
+#define EMAC_CH2_EB_S  23
+/** EMAC_CH2_GLI : RO; bitpos: [26]; default: 0;
+ *  EMAC Line Interface Interrupt When set, this bit reflects any of the following
+ *  interrupt events in the DWC_EMAC interfaces _if present and enabled in your
+ *  configuration_: PCS _TBI, RTBI, or SGMII_: Link change or autonegotiation complete
+ *  event SMII or RGMII: Link change event General Purpose Input Status _GPIS_: Any LL
+ *  or LH event on the gpi_i input ports To identify the exact cause of the interrupt,
+ *  the software must first read Bit 11 and Bits[2:0] of Register 14 _Interrupt Status
+ *  Register_ and then to clear the source of interrupt _which also clears the GLI
+ *  interrupt_, read any of the following corresponding registers: PCS _TBI, RTBI, or
+ *  SGMII_: Register 49 _AN Status Register_ SMII or RGMII: Register 54
+ *  _SGMII/RGMII/SMII Control and Status Register_ General Purpose Input _GPI_:
+ *  Register 56 _General Purpose IO Register_ The interrupt signal from the DWC_EMAC
+ *  subsystem _sbd_intr_o_ is high when this bit is high
+ */
+#define EMAC_CH2_GLI    (BIT(26))
+#define EMAC_CH2_GLI_M  (EMAC_CH2_GLI_V << EMAC_CH2_GLI_S)
+#define EMAC_CH2_GLI_V  0x00000001U
+#define EMAC_CH2_GLI_S  26
+/** EMAC_CH2_GMI : RO; bitpos: [27]; default: 0;
+ *  EMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the
+ *  DWC_EMAC The software must read the corresponding registers in the DWC_EMAC to get
+ *  the exact cause of the interrupt and clear the source of interrupt to make this bit
+ *  as 1’b0 The interrupt signal from the DWC_EMAC subsystem _sbd_intr_o_ is high when
+ *  this bit is high This bit is applicable only when the MAC Management Counters _MMC_
+ *  are enabled Otherwise, this bit is reserved
+ */
+#define EMAC_CH2_GMI    (BIT(27))
+#define EMAC_CH2_GMI_M  (EMAC_CH2_GMI_V << EMAC_CH2_GMI_S)
+#define EMAC_CH2_GMI_V  0x00000001U
+#define EMAC_CH2_GMI_S  27
+/** EMAC_CH2_GPI : RO; bitpos: [28]; default: 0;
+ *  EMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the
+ *  DWC_EMAC The software must read the PMT Control and Status Register in the MAC to
+ *  get the exact cause of interrupt and clear its source to reset this bit to 1’b0 The
+ *  interrupt signal from the DWC_EMAC subsystem _sbd_intr_o_ is high when this bit is
+ *  high This bit is applicable only when the Power Management feature is enabled
+ *  Otherwise, this bit is reserved Note: The GPI and pmt_intr_o interrupts are
+ *  generated in different clock domains
+ */
+#define EMAC_CH2_GPI    (BIT(28))
+#define EMAC_CH2_GPI_M  (EMAC_CH2_GPI_V << EMAC_CH2_GPI_S)
+#define EMAC_CH2_GPI_V  0x00000001U
+#define EMAC_CH2_GPI_S  28
+/** EMAC_CH2_TTI : RO; bitpos: [29]; default: 0;
+ *  Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp
+ *  Generator block of the DWC_EMAC The software must read the corresponding registers
+ *  in the DWC_EMAC to get the exact cause of the interrupt and clear its source to
+ *  reset this bit to 1'b0 When this bit is high, the interrupt signal from the
+ *  DWC_EMAC subsystem _sbd_intr_o_ is high This bit is applicable only when the IEEE
+ *  1588 Timestamp feature is enabled Otherwise, this bit is reserved
+ */
+#define EMAC_CH2_TTI    (BIT(29))
+#define EMAC_CH2_TTI_M  (EMAC_CH2_TTI_V << EMAC_CH2_TTI_S)
+#define EMAC_CH2_TTI_V  0x00000001U
+#define EMAC_CH2_TTI_S  29
+/** EMAC_CH2_GLPII_GTMSI : RO; bitpos: [30]; default: 0;
+ *  GTMSI: EMAC TMS Interrupt _for Channel 1 and Channel 2_ This bit indicates an
+ *  interrupt event in the traffic manager and scheduler logic of DWC_EMAC To reset
+ *  this bit, the software must read the corresponding registers _Channel Status
+ *  Register_ to get the exact cause of the interrupt and clear its source Note: GTMSI
+ *  status is given only in Channel 1 and Channel 2 DMA register when the AV feature is
+ *  enabled and corresponding additional transmit channels are present Otherwise, this
+ *  bit is reserved When this bit is high, the interrupt signal from the MAC
+ *  _sbd_intr_o_ is high
+ */
+#define EMAC_CH2_GLPII_GTMSI    (BIT(30))
+#define EMAC_CH2_GLPII_GTMSI_M  (EMAC_CH2_GLPII_GTMSI_V << EMAC_CH2_GLPII_GTMSI_S)
+#define EMAC_CH2_GLPII_GTMSI_V  0x00000001U
+#define EMAC_CH2_GLPII_GTMSI_S  30
+
+/** EMAC_CHANNEL2OPERATIONMODE_REG register
+ *  Establishes the Receive and Transmit operating modes and command
+ */
+#define EMAC_CHANNEL2OPERATIONMODE_REG (DR_REG_EMAC_BASE + 0x1218)
+/** EMAC_CH2_SR : R/W; bitpos: [1]; default: 0;
+ *  Start or Stop Receive When this bit is set, the Receive process is placed in the
+ *  Running state The DMA attempts to acquire the descriptor from the Receive list and
+ *  processes the incoming frames The descriptor acquisition is attempted from the
+ *  current position in the list, which is the address set by the Register 3 _Receive
+ *  Descriptor List Address Register_ or the position retained when the Receive process
+ *  was previously stopped If the DMA does not own the descriptor, reception is
+ *  suspended and Bit 7 _Receive Buffer Unavailable_ of Register 5 _Status Register_ is
+ *  set The Start Receive command is effective only when the reception has stopped If
+ *  the command is issued before setting Register 3 _Receive Descriptor List Address
+ *  Register_, the DMA behavior is unpredictable When this bit is cleared, the Rx DMA
+ *  operation is stopped after the transfer of the current frame The next descriptor
+ *  position in the Receive list is saved and becomes the current position after the
+ *  Receive process is restarted The Stop Receive command is effective only when the
+ *  Receive process is in either the Running _waiting for receive packet_ or in the
+ *  Suspended state Note: For information about how to pause the transmission, see
+ *  “Stopping and Starting Transmission” on page 715
+ */
+#define EMAC_CH2_SR    (BIT(1))
+#define EMAC_CH2_SR_M  (EMAC_CH2_SR_V << EMAC_CH2_SR_S)
+#define EMAC_CH2_SR_V  0x00000001U
+#define EMAC_CH2_SR_S  1
+/** EMAC_CH2_OSF : R/W; bitpos: [2]; default: 0;
+ *  Operate on Second Frame When this bit is set, it instructs the DMA to process the
+ *  second frame of the Transmit data even before the status for the first frame is
+ *  obtained
+ */
+#define EMAC_CH2_OSF    (BIT(2))
+#define EMAC_CH2_OSF_M  (EMAC_CH2_OSF_V << EMAC_CH2_OSF_S)
+#define EMAC_CH2_OSF_V  0x00000001U
+#define EMAC_CH2_OSF_S  2
+/** EMAC_CH2_RTC : R/W; bitpos: [4:3]; default: 0;
+ *  Receive Threshold Control These two bits control the threshold level of the MTL
+ *  Receive FIFO Transfer _request_ to DMA starts when the frame size within the MTL
+ *  Receive FIFO is larger than the threshold In addition, full frames with length less
+ *  than the threshold are automatically transferred The value of 11 is not applicable
+ *  if the configured Receive FIFO size is 128 bytes These bits are valid only when the
+ *  RSF bit is zero, and are ignored when the RSF bit is set to 1 00: 64 01: 32 10: 96
+ *  11: 128
+ */
+#define EMAC_CH2_RTC    0x00000003U
+#define EMAC_CH2_RTC_M  (EMAC_CH2_RTC_V << EMAC_CH2_RTC_S)
+#define EMAC_CH2_RTC_V  0x00000003U
+#define EMAC_CH2_RTC_S  3
+/** EMAC_CH2_DGF : R/W; bitpos: [5]; default: 0;
+ *  Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO,
+ *  that is, frames that are larger than the computed giant frame limit When reset, the
+ *  MAC does not drop the giant frames in the Rx FIFO Note: This bit is available in
+ *  the following configurations in which the giant frame status is not provided in Rx
+ *  status and giant frames are not dropped by default: Configurations in which IP
+ *  Checksum Offload _Type 1_ is selected in Rx Configurations in which the IPC Full
+ *  Checksum Offload Engine _Type 2_ is selected in Rx with normal descriptor format
+ *  Configurations in which the Advanced Timestamp feature is selected In all other
+ *  configurations, this bit is not used _reserved and always reset_
+ */
+#define EMAC_CH2_DGF    (BIT(5))
+#define EMAC_CH2_DGF_M  (EMAC_CH2_DGF_V << EMAC_CH2_DGF_S)
+#define EMAC_CH2_DGF_V  0x00000001U
+#define EMAC_CH2_DGF_S  5
+/** EMAC_CH2_FUF : R/W; bitpos: [6]; default: 0;
+ *  Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames
+ *  _that is, frames with no Error and length less than 64 bytes_ including padbytes
+ *  and CRC When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a
+ *  frame is already transferred because of the lower value of Receive Threshold, for
+ *  example, RTC = 01
+ */
+#define EMAC_CH2_FUF    (BIT(6))
+#define EMAC_CH2_FUF_M  (EMAC_CH2_FUF_V << EMAC_CH2_FUF_S)
+#define EMAC_CH2_FUF_V  0x00000001U
+#define EMAC_CH2_FUF_S  6
+/** EMAC_CH2_FEF : R/W; bitpos: [7]; default: 0;
+ *  Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error
+ *  status _CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or
+ *  overflow_ However, if the start byte _write_ pointer of a frame is already
+ *  transferred to the read controller side _in Threshold mode_, then the frame is not
+ *  dropped In the EMACMTL configuration in which the Frame Length FIFO is also enabled
+ *  during core configuration, the Rx FIFO drops the error frames if that frame's start
+ *  byte is not transferred _output_ on the ARI bus When the FEF bit is set, all frames
+ *  except runt error frames are forwarded to the DMA If the Bit 25 _RSF_ is set and
+ *  the Rx FIFO overflows when a partial frame is written, then the frame is dropped
+ *  irrespective of the FEF bit setting However, if the Bit 25 _RSF_ is reset and the
+ *  Rx FIFO overflows when a partial frame is written, then a partial frame may be
+ *  forwarded to the DMA Note: When FEF bit is reset, the giant frames are dropped if
+ *  the giant frame status is given in Rx Status _in Table 86 or Table 823_ in the
+ *  following configurations: The IP checksum engine _Type 1_ and full checksum offload
+ *  engine _Type 2_ are not selected The advanced timestamp feature is not selected but
+ *  the extended status is selected The extended status is available with the following
+ *  features: 	L3L4 filter in EMACCORE or EMACMTL configurations 	Full checksum offload
+ *  engine _Type 2_ with enhanced descriptor format in the EMACDMA, EMACAHB, or EMACAXI
+ *  configurations
+ */
+#define EMAC_CH2_FEF    (BIT(7))
+#define EMAC_CH2_FEF_M  (EMAC_CH2_FEF_V << EMAC_CH2_FEF_S)
+#define EMAC_CH2_FEF_V  0x00000001U
+#define EMAC_CH2_FEF_S  7
+/** EMAC_CH2_EFC : R/W; bitpos: [8]; default: 0;
+ *  Enable HW Flow Control When this bit is set, the flow control signal operation
+ *  based on the filllevel of Rx FIFO is enabled When reset, the flow control operation
+ *  is disabled This bit is not used _reserved and always reset_ when the Rx FIFO is
+ *  less than 4 KB
+ */
+#define EMAC_CH2_EFC    (BIT(8))
+#define EMAC_CH2_EFC_M  (EMAC_CH2_EFC_V << EMAC_CH2_EFC_S)
+#define EMAC_CH2_EFC_V  0x00000001U
+#define EMAC_CH2_EFC_S  8
+/** EMAC_CH2_RFA : R/W; bitpos: [10:9]; default: 0;
+ *  Threshold for Activating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Fill level of Rx FIFO_ at which the flow control is
+ *  activated 00: Full minus 1 KB, that is, FULL—1KB 01: Full minus 2 KB, that is,
+ *  FULL—2KB 10: Full minus 3 KB, that is, FULL—3KB 11: Full minus 4 KB, that is,
+ *  FULL—4KB These values are applicable only to Rx FIFOs of 4 KB or more and when Bit
+ *  8 _EFC_ is set high If the Rx FIFO is 8 KB or more, an additional Bit _RFA_2_ is
+ *  used for more threshold levels as described in Bit 23 These bits are reserved and
+ *  readonly when the depth of Rx FIFO is less than 4 KB Note: When FIFO size is
+ *  exactly 4 KB, although the DWC_EMAC allows you to program the value of these bits
+ *  to 11, the software should not program these bits to 2'b11 The value 2'b11 means
+ *  flow control on FIFO empty condition
+ */
+#define EMAC_CH2_RFA    0x00000003U
+#define EMAC_CH2_RFA_M  (EMAC_CH2_RFA_V << EMAC_CH2_RFA_S)
+#define EMAC_CH2_RFA_V  0x00000003U
+#define EMAC_CH2_RFA_S  9
+/** EMAC_CH2_RFD : R/W; bitpos: [12:11]; default: 0;
+ *  Threshold for Deactivating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Filllevel of Rx FIFO_ at which the flow control is
+ *  deasserted after activation 00: Full minus 1 KB, that is, FULL — 1 KB 01: Full
+ *  minus 2 KB, that is, FULL — 2 KB 10: Full minus 3 KB, that is, FULL — 3 KB 11: Full
+ *  minus 4 KB, that is, FULL — 4 KB The deassertion is effective only after flow
+ *  control is asserted If the Rx FIFO is 8 KB or more, an additional Bit _RFD_2_ is
+ *  used for more threshold levels as described in Bit 22 These bits are reserved and
+ *  readonly when the Rx FIFO depth is less than 4 KB Note: For proper flow control,
+ *  the value programmed in the “RFD_2, RFD” fields should be equal to or more than the
+ *  value programmed in the “RFA_2, RFA” fields
+ */
+#define EMAC_CH2_RFD    0x00000003U
+#define EMAC_CH2_RFD_M  (EMAC_CH2_RFD_V << EMAC_CH2_RFD_S)
+#define EMAC_CH2_RFD_V  0x00000003U
+#define EMAC_CH2_RFD_S  11
+/** EMAC_CH2_ST : R/W; bitpos: [13]; default: 0;
+ *  Start or Stop Transmission Command When this bit is set, transmission is placed in
+ *  the Running state, and the DMA checks the Transmit List at the current position for
+ *  a frame to be transmitted Descriptor acquisition is attempted either from the
+ *  current position in the list, which is the Transmit List Base Address set by
+ *  Register 4 _Transmit Descriptor List Address Register_, or from the position
+ *  retained when transmission was stopped previously If the DMA does not own the
+ *  current descriptor, transmission enters the Suspended state and Bit 2 _Transmit
+ *  Buffer Unavailable_ of Register 5 _Status Register_ is set The Start Transmission
+ *  command is effective only when transmission is stopped If the command is issued
+ *  before setting Register 4 _Transmit Descriptor List Address Register_, then the DMA
+ *  behavior is unpredictable When this bit is reset, the transmission process is
+ *  placed in the Stopped state after completing the transmission of the current frame
+ *  The Next Descriptor position in the Transmit List is saved, and it becomes the
+ *  current position when transmission is restarted To change the list address, you
+ *  need to program Register 4 _Transmit Descriptor List Address Register_ with a new
+ *  value when this bit is reset The new value is considered when this bit is set again
+ *  The stop transmission command is effective only when the transmission of the
+ *  current frame is complete or the transmission is in the Suspended state Note: For
+ *  information about how to pause the transmission, see “Stopping and Starting
+ *  Transmission” on page 715
+ */
+#define EMAC_CH2_ST    (BIT(13))
+#define EMAC_CH2_ST_M  (EMAC_CH2_ST_V << EMAC_CH2_ST_S)
+#define EMAC_CH2_ST_V  0x00000001U
+#define EMAC_CH2_ST_S  13
+/** EMAC_CH2_TTC : R/W; bitpos: [16:14]; default: 0;
+ *  Transmit Threshold Control These bits control the threshold level of the MTL
+ *  Transmit FIFO Transmission starts when the frame size within the MTL Transmit FIFO
+ *  is larger than the threshold In addition, full frames with a length less than the
+ *  threshold are also transmitted These bits are used only when Bit 21 _TSF_ is reset
+ *  000: 64 001: 128 010: 192 011: 256 100: 40 101: 32 110: 24 111: 16
+ */
+#define EMAC_CH2_TTC    0x00000007U
+#define EMAC_CH2_TTC_M  (EMAC_CH2_TTC_V << EMAC_CH2_TTC_S)
+#define EMAC_CH2_TTC_V  0x00000007U
+#define EMAC_CH2_TTC_S  14
+/** EMAC_CH2_FTF : R/W; bitpos: [20]; default: 0;
+ *  Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is
+ *  reset to its default values and thus all data in the Tx FIFO is lost or flushed
+ *  This bit is cleared internally when the flushing operation is complete The
+ *  Operation Mode register should not be written to until this bit is cleared The data
+ *  which is already accepted by the MAC transmitter is not flushed It is scheduled for
+ *  transmission and results in underflow and runt frame transmission Note: The flush
+ *  operation is complete only when the Tx FIFO is emptied of its contents and all the
+ *  pending Transmit Status of the transmitted frames are accepted by the host In order
+ *  to complete this flush operation, the PHY transmit clock _clk_tx_i_ is required to
+ *  be active 19:17		Reserved 	000	RO
+ */
+#define EMAC_CH2_FTF    (BIT(20))
+#define EMAC_CH2_FTF_M  (EMAC_CH2_FTF_V << EMAC_CH2_FTF_S)
+#define EMAC_CH2_FTF_V  0x00000001U
+#define EMAC_CH2_FTF_S  20
+/** EMAC_CH2_TSF : R/W; bitpos: [21]; default: 0;
+ *  Transmit Store and Forward When this bit is set, transmission starts when a full
+ *  frame resides in the MTL Transmit FIFO When this bit is set, the TTC values
+ *  specified in Bits [16:14] are ignored This bit should be changed only when the
+ *  transmission is stopped
+ */
+#define EMAC_CH2_TSF    (BIT(21))
+#define EMAC_CH2_TSF_M  (EMAC_CH2_TSF_V << EMAC_CH2_TSF_S)
+#define EMAC_CH2_TSF_V  0x00000001U
+#define EMAC_CH2_TSF_S  21
+/** EMAC_CH2_RFD_2 : R/W; bitpos: [22]; default: 0;
+ *  MSB of Threshold for Deactivating Flow Control If the DWC_EMAC is configured for Rx
+ *  FIFO size of 8 KB or more, this bit _when set_ provides additional threshold levels
+ *  for deactivating the flow control in both halfduplex and fullduplex modes This bit
+ *  _as Most Significant Bit_ along with the RFD _Bits [12:11]_ gives the following
+ *  thresholds for deactivating flow control: 100: Full minus 5 KB, that is, FULL — 5
+ *  KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that is, FULL —
+ *  7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB or less deep
+ */
+#define EMAC_CH2_RFD_2    (BIT(22))
+#define EMAC_CH2_RFD_2_M  (EMAC_CH2_RFD_2_V << EMAC_CH2_RFD_2_S)
+#define EMAC_CH2_RFD_2_V  0x00000001U
+#define EMAC_CH2_RFD_2_S  22
+/** EMAC_CH2_RFA_2 : R/W; bitpos: [23]; default: 0;
+ *  MSB of Threshold for Activating Flow Control If the DWC_EMAC is configured for an
+ *  Rx FIFO size of 8 KB or more, this bit _when set_ provides additional threshold
+ *  levels for activating the flow control in both half duplex and fullduplex modes
+ *  This bit _as Most Significant Bit_, along with the RFA _Bits [10:9]_, gives the
+ *  following thresholds for activating flow control: 100: Full minus 5 KB, that is,
+ *  FULL — 5 KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that
+ *  is, FULL — 7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB
+ *  or less deep
+ */
+#define EMAC_CH2_RFA_2    (BIT(23))
+#define EMAC_CH2_RFA_2_M  (EMAC_CH2_RFA_2_V << EMAC_CH2_RFA_2_S)
+#define EMAC_CH2_RFA_2_V  0x00000001U
+#define EMAC_CH2_RFA_2_S  23
+/** EMAC_CH2_DFF : R/W; bitpos: [24]; default: 0;
+ *  Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush
+ *  any frames because of the unavailability of receive descriptors or buffers as it
+ *  does normally when this bit is reset _See “Receive Process Suspended” on page 83_
+ *  This bit is reserved _and RO_ in the EMACMTL configuration
+ */
+#define EMAC_CH2_DFF    (BIT(24))
+#define EMAC_CH2_DFF_M  (EMAC_CH2_DFF_V << EMAC_CH2_DFF_S)
+#define EMAC_CH2_DFF_V  0x00000001U
+#define EMAC_CH2_DFF_S  24
+/** EMAC_CH2_RSF : R/W; bitpos: [25]; default: 0;
+ *  Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx
+ *  FIFO only after the complete frame has been written to it, ignoring the RTC bits
+ *  When this bit is reset, the Rx FIFO operates in the cutthrough mode, subject to the
+ *  threshold specified by the RTC bits
+ */
+#define EMAC_CH2_RSF    (BIT(25))
+#define EMAC_CH2_RSF_M  (EMAC_CH2_RSF_V << EMAC_CH2_RSF_S)
+#define EMAC_CH2_RSF_V  0x00000001U
+#define EMAC_CH2_RSF_S  25
+/** EMAC_CH2_DT : R/W; bitpos: [26]; default: 0;
+ *  Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does
+ *  not drop the frames which only have errors detected by the Receive Checksum Offload
+ *  engine Such frames do not have any errors _including FCS error_ in the Ethernet
+ *  frame received by the MAC but have errors only in the encapsulated payload When
+ *  this bit is reset, all error frames are dropped if the FEF bit is reset If the IPC
+ *  Full Checksum Offload Engine _Type 2_ is disabled, this bit is reserved _RO with
+ *  value 1'b0_
+ */
+#define EMAC_CH2_DT    (BIT(26))
+#define EMAC_CH2_DT_M  (EMAC_CH2_DT_V << EMAC_CH2_DT_S)
+#define EMAC_CH2_DT_V  0x00000001U
+#define EMAC_CH2_DT_S  26
+
+/** EMAC_CHANNEL2INTERRUPTENABLE_REG register
+ *  Enables the interrupts reported by the Status Register
+ */
+#define EMAC_CHANNEL2INTERRUPTENABLE_REG (DR_REG_EMAC_BASE + 0x121c)
+/** EMAC_CH2_TIE : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Transmit Interrupt is enabled When this bit is reset, the Transmit
+ *  Interrupt is disabled The sbd_intr_o interrupt is generated as shown in Figure 61
+ *  It is asserted only when the TTI, GPI, GMI, GLI, or GLPII bit of the DMA Status
+ *  register is asserted, or when the NIS or AIS Status bit is asserted and the
+ *  corresponding Interrupt Enable bits _NIE or AIE_ are enabled
+ */
+#define EMAC_CH2_TIE    (BIT(0))
+#define EMAC_CH2_TIE_M  (EMAC_CH2_TIE_V << EMAC_CH2_TIE_S)
+#define EMAC_CH2_TIE_V  0x00000001U
+#define EMAC_CH2_TIE_S  0
+/** EMAC_CH2_TSE : R/W; bitpos: [1]; default: 0;
+ *  Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Transmission Stopped Interrupt is enabled When this bit is reset, the
+ *  Transmission Stopped Interrupt is disabled
+ */
+#define EMAC_CH2_TSE    (BIT(1))
+#define EMAC_CH2_TSE_M  (EMAC_CH2_TSE_V << EMAC_CH2_TSE_S)
+#define EMAC_CH2_TSE_V  0x00000001U
+#define EMAC_CH2_TSE_S  1
+/** EMAC_CH2_TUE : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt
+ *  Summary Enable _Bit 16_, the Transmit Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled
+ */
+#define EMAC_CH2_TUE    (BIT(2))
+#define EMAC_CH2_TUE_M  (EMAC_CH2_TUE_V << EMAC_CH2_TUE_S)
+#define EMAC_CH2_TUE_V  0x00000001U
+#define EMAC_CH2_TUE_S  2
+/** EMAC_CH2_TJE : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Jabber Timeout Interrupt is enabled When this bit is
+ *  reset, the Transmit Jabber Timeout Interrupt is disabled
+ */
+#define EMAC_CH2_TJE    (BIT(3))
+#define EMAC_CH2_TJE_M  (EMAC_CH2_TJE_V << EMAC_CH2_TJE_S)
+#define EMAC_CH2_TJE_V  0x00000001U
+#define EMAC_CH2_TJE_S  3
+/** EMAC_CH2_OVE : R/W; bitpos: [4]; default: 0;
+ *  Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Receive Overflow Interrupt is enabled When this bit is reset,
+ *  the Overflow Interrupt is disabled
+ */
+#define EMAC_CH2_OVE    (BIT(4))
+#define EMAC_CH2_OVE_M  (EMAC_CH2_OVE_V << EMAC_CH2_OVE_S)
+#define EMAC_CH2_OVE_V  0x00000001U
+#define EMAC_CH2_OVE_S  4
+/** EMAC_CH2_UNE : R/W; bitpos: [5]; default: 0;
+ *  Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Underflow Interrupt is enabled When this bit is
+ *  reset, the Underflow Interrupt is disabled
+ */
+#define EMAC_CH2_UNE    (BIT(5))
+#define EMAC_CH2_UNE_M  (EMAC_CH2_UNE_V << EMAC_CH2_UNE_S)
+#define EMAC_CH2_UNE_V  0x00000001U
+#define EMAC_CH2_UNE_S  5
+/** EMAC_CH2_RIE : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Receive Interrupt is enabled When this bit is reset, the Receive
+ *  Interrupt is disabled
+ */
+#define EMAC_CH2_RIE    (BIT(6))
+#define EMAC_CH2_RIE_M  (EMAC_CH2_RIE_V << EMAC_CH2_RIE_S)
+#define EMAC_CH2_RIE_V  0x00000001U
+#define EMAC_CH2_RIE_S  6
+/** EMAC_CH2_RUE : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Receive Buffer Unavailable Interrupt is disabled
+ */
+#define EMAC_CH2_RUE    (BIT(7))
+#define EMAC_CH2_RUE_M  (EMAC_CH2_RUE_V << EMAC_CH2_RUE_S)
+#define EMAC_CH2_RUE_V  0x00000001U
+#define EMAC_CH2_RUE_S  7
+/** EMAC_CH2_RSE : R/W; bitpos: [8]; default: 0;
+ *  Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Receive Stopped Interrupt is enabled When this bit is reset, the
+ *  Receive Stopped Interrupt is disabled
+ */
+#define EMAC_CH2_RSE    (BIT(8))
+#define EMAC_CH2_RSE_M  (EMAC_CH2_RSE_V << EMAC_CH2_RSE_S)
+#define EMAC_CH2_RSE_V  0x00000001U
+#define EMAC_CH2_RSE_S  8
+/** EMAC_CH2_RWE : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Watchdog Timeout Interrupt is enabled When
+ *  this bit is reset, the Receive Watchdog Timeout Interrupt is disabled
+ */
+#define EMAC_CH2_RWE    (BIT(9))
+#define EMAC_CH2_RWE_M  (EMAC_CH2_RWE_V << EMAC_CH2_RWE_S)
+#define EMAC_CH2_RWE_V  0x00000001U
+#define EMAC_CH2_RWE_S  9
+/** EMAC_CH2_ETE : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Early Transmit Interrupt is enabled When this bit is
+ *  reset, the Early Transmit Interrupt is disabled
+ */
+#define EMAC_CH2_ETE    (BIT(10))
+#define EMAC_CH2_ETE_M  (EMAC_CH2_ETE_V << EMAC_CH2_ETE_S)
+#define EMAC_CH2_ETE_V  0x00000001U
+#define EMAC_CH2_ETE_S  10
+/** EMAC_CH2_FBE : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Fatal Bus Error Interrupt is enabled When this bit is reset, the
+ *  Fatal Bus Error Enable Interrupt is disabled 12:11		Reserved	00	RO
+ */
+#define EMAC_CH2_FBE    (BIT(13))
+#define EMAC_CH2_FBE_M  (EMAC_CH2_FBE_V << EMAC_CH2_FBE_S)
+#define EMAC_CH2_FBE_V  0x00000001U
+#define EMAC_CH2_FBE_S  13
+/** EMAC_CH2_ERE : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary
+ *  Enable _Bit 16_, the Early Receive Interrupt is enabled When this bit is reset, the
+ *  Early Receive Interrupt is disabled
+ */
+#define EMAC_CH2_ERE    (BIT(14))
+#define EMAC_CH2_ERE_M  (EMAC_CH2_ERE_V << EMAC_CH2_ERE_S)
+#define EMAC_CH2_ERE_V  0x00000001U
+#define EMAC_CH2_ERE_S  14
+/** EMAC_CH2_AIE : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary
+ *  is enabled When this bit is reset, the abnormal interrupt summary is disabled This
+ *  bit enables the following interrupts in Register 5 _Status Register_: Register
+ *  5[1]: Transmit Process Stopped Register 5[3]: Transmit Jabber Timeout Register
+ *  5[4]: Receive Overflow Register 5[5]: Transmit Underflow Register 5[7]: Receive
+ *  Buffer Unavailable Register 5[8]: Receive Process Stopped Register 5[9]: Receive
+ *  Watchdog Timeout Register 5[10]: Early Transmit Interrupt Register 5[13]: Fatal Bus
+ *  Error
+ */
+#define EMAC_CH2_AIE    (BIT(15))
+#define EMAC_CH2_AIE_M  (EMAC_CH2_AIE_V << EMAC_CH2_AIE_S)
+#define EMAC_CH2_AIE_V  0x00000001U
+#define EMAC_CH2_AIE_S  15
+/** EMAC_CH2_NIE : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is
+ *  enabled When this bit is reset, normal interrupt summary is disabled This bit
+ *  enables the following interrupts in Register 5 _Status Register_: Register 5[0]:
+ *  Transmit Interrupt Register 5[2]: Transmit Buffer Unavailable Register 5[6]:
+ *  Receive Interrupt Register 5[14]: Early Receive Interrupt
+ */
+#define EMAC_CH2_NIE    (BIT(16))
+#define EMAC_CH2_NIE_M  (EMAC_CH2_NIE_V << EMAC_CH2_NIE_S)
+#define EMAC_CH2_NIE_V  0x00000001U
+#define EMAC_CH2_NIE_S  16
+
+/** EMAC_CHANNEL2MISSEDFRAMEANDBUFFEROVERFLOWCOUNTER_REG register
+ *  Contains the counters for discarded frames because no host Receive Descriptor was
+ *  available or because of Receive FIFO Overflow
+ */
+#define EMAC_CHANNEL2MISSEDFRAMEANDBUFFEROVERFLOWCOUNTER_REG (DR_REG_EMAC_BASE + 0x1220)
+/** EMAC_CH2_MISFRMCNT : R/W; bitpos: [15:0]; default: 0;
+ *  Missed Frame Counter This field indicates the number of frames missed by the
+ *  controller because of the Host Receive Buffer being unavailable This counter is
+ *  incremented each time the DMA discards an incoming frame The counter is cleared
+ *  when this register is read with mci_be_i[0] at 1’b1
+ */
+#define EMAC_CH2_MISFRMCNT    0x0000FFFFU
+#define EMAC_CH2_MISFRMCNT_M  (EMAC_CH2_MISFRMCNT_V << EMAC_CH2_MISFRMCNT_S)
+#define EMAC_CH2_MISFRMCNT_V  0x0000FFFFU
+#define EMAC_CH2_MISFRMCNT_S  0
+/** EMAC_CH2_MISCNTOVF : R/W; bitpos: [16]; default: 0;
+ *  Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame
+ *  Counter _Bits[15:0]_ overflows, that is, the DMA discards an incoming frame because
+ *  of the Host Receive Buffer being unavailable with the missed frame counter at
+ *  maximum value In such a scenario, the Missed frame counter is reset to allzeros and
+ *  this bit indicates that the rollover happened
+ */
+#define EMAC_CH2_MISCNTOVF    (BIT(16))
+#define EMAC_CH2_MISCNTOVF_M  (EMAC_CH2_MISCNTOVF_V << EMAC_CH2_MISCNTOVF_S)
+#define EMAC_CH2_MISCNTOVF_V  0x00000001U
+#define EMAC_CH2_MISCNTOVF_S  16
+/** EMAC_CH2_OVFFRMCNT : R/W; bitpos: [27:17]; default: 0;
+ *  Overflow Frame Counter This field indicates the number of frames missed by the
+ *  application This counter is incremented each time the MTL FIFO overflows The
+ *  counter is cleared when this register is read with mci_be_i[2] at 1’b1
+ */
+#define EMAC_CH2_OVFFRMCNT    0x000007FFU
+#define EMAC_CH2_OVFFRMCNT_M  (EMAC_CH2_OVFFRMCNT_V << EMAC_CH2_OVFFRMCNT_S)
+#define EMAC_CH2_OVFFRMCNT_V  0x000007FFU
+#define EMAC_CH2_OVFFRMCNT_S  17
+/** EMAC_CH2_OVFCNTOVF : R/W; bitpos: [28]; default: 0;
+ *  Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow
+ *  Frame Counter _Bits[27:17]_ overflows, that is, the Rx FIFO overflows with the
+ *  overflow frame counter at maximum value In such a scenario, the overflow frame
+ *  counter is reset to allzeros and this bit indicates that the rollover happened
+ */
+#define EMAC_CH2_OVFCNTOVF    (BIT(28))
+#define EMAC_CH2_OVFCNTOVF_M  (EMAC_CH2_OVFCNTOVF_V << EMAC_CH2_OVFCNTOVF_S)
+#define EMAC_CH2_OVFCNTOVF_V  0x00000001U
+#define EMAC_CH2_OVFCNTOVF_S  28
+
+/** EMAC_CHANNEL2RECEIVEINTERRUPTWATCHDOGTIMER_REG register
+ *  Watchdog timeout for Receive Interrupt _RI_ from DMA
+ */
+#define EMAC_CHANNEL2RECEIVEINTERRUPTWATCHDOGTIMER_REG (DR_REG_EMAC_BASE + 0x1224)
+/** EMAC_CH2_RIWT : R/W; bitpos: [7:0]; default: 0;
+ *  RI Watchdog Timer Count This bit indicates the number of system clock cycles
+ *  multiplied by 256 for which the watchdog timer is set The watchdog timer gets
+ *  triggered with the programmed value after the Rx DMA completes the transfer of a
+ *  frame for which the RI status bit is not set because of the setting in the
+ *  corresponding descriptor RDES1[31] When the watchdog timer runs out, the RI bit is
+ *  set and the timer is stopped The watchdog timer is reset when the RI bit is set
+ *  high because of automatic setting of RI as per RDES1[31] of any received frame
+ */
+#define EMAC_CH2_RIWT    0x000000FFU
+#define EMAC_CH2_RIWT_M  (EMAC_CH2_RIWT_V << EMAC_CH2_RIWT_S)
+#define EMAC_CH2_RIWT_V  0x000000FFU
+#define EMAC_CH2_RIWT_S  0
+
+/** EMAC_CHANNEL2CURRENTHOSTTRANSMITDESCRIPTOR_REG register
+ *  Points to the start of current Transmit Descriptor read by the DMA
+ */
+#define EMAC_CHANNEL2CURRENTHOSTTRANSMITDESCRIPTOR_REG (DR_REG_EMAC_BASE + 0x1248)
+/** EMAC_CH2_CURTDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Descriptor Address Pointer
+ */
+#define EMAC_CH2_CURTDESAPTR    0xFFFFFFFFU
+#define EMAC_CH2_CURTDESAPTR_M  (EMAC_CH2_CURTDESAPTR_V << EMAC_CH2_CURTDESAPTR_S)
+#define EMAC_CH2_CURTDESAPTR_V  0xFFFFFFFFU
+#define EMAC_CH2_CURTDESAPTR_S  0
+
+/** EMAC_CHANNEL2CURRENTHOSTRECEIVEDESCRIPTOR_REG register
+ *  Points to the start of current Receive Descriptor read by the DMA
+ */
+#define EMAC_CHANNEL2CURRENTHOSTRECEIVEDESCRIPTOR_REG (DR_REG_EMAC_BASE + 0x124c)
+/** EMAC_CH2_CURRDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Descriptor Address Pointer
+ */
+#define EMAC_CH2_CURRDESAPTR    0xFFFFFFFFU
+#define EMAC_CH2_CURRDESAPTR_M  (EMAC_CH2_CURRDESAPTR_V << EMAC_CH2_CURRDESAPTR_S)
+#define EMAC_CH2_CURRDESAPTR_V  0xFFFFFFFFU
+#define EMAC_CH2_CURRDESAPTR_S  0
+
+/** EMAC_CHANNEL2CURRENTHOSTTRANSMITBUFFERADDRESS_REG register
+ *  Points to the current Transmit Buffer address read by the DMA
+ */
+#define EMAC_CHANNEL2CURRENTHOSTTRANSMITBUFFERADDRESS_REG (DR_REG_EMAC_BASE + 0x1250)
+/** EMAC_CH2_CURTBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Buffer Address Pointer
+ */
+#define EMAC_CH2_CURTBUFAPTR    0xFFFFFFFFU
+#define EMAC_CH2_CURTBUFAPTR_M  (EMAC_CH2_CURTBUFAPTR_V << EMAC_CH2_CURTBUFAPTR_S)
+#define EMAC_CH2_CURTBUFAPTR_V  0xFFFFFFFFU
+#define EMAC_CH2_CURTBUFAPTR_S  0
+
+/** EMAC_CHANNEL2CURRENTHOSTRECEIVEBUFFERADDRESS_REG register
+ *  Points to the current Receive Buffer address read by the DMA
+ */
+#define EMAC_CHANNEL2CURRENTHOSTRECEIVEBUFFERADDRESS_REG (DR_REG_EMAC_BASE + 0x1254)
+/** EMAC_CH2_CURRBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Buffer Address Pointer
+ */
+#define EMAC_CH2_CURRBUFAPTR    0xFFFFFFFFU
+#define EMAC_CH2_CURRBUFAPTR_M  (EMAC_CH2_CURRBUFAPTR_V << EMAC_CH2_CURRBUFAPTR_S)
+#define EMAC_CH2_CURRBUFAPTR_V  0xFFFFFFFFU
+#define EMAC_CH2_CURRBUFAPTR_S  0
+
+/** EMAC_CHANNEL2CBSCONTROL_REG register
+ *  Controls the Channel 2 credit shaping operation on the transmit path
+ */
+#define EMAC_CHANNEL2CBSCONTROL_REG (DR_REG_EMAC_BASE + 0x1260)
+/** EMAC_CH2_CBSD : R/W; bitpos: [0]; default: 0;
+ *  CreditBased Shaper Disable When set, the MAC disables the creditbased shaper
+ *  algorithm for Channel 2 traffic and makes the traffic management algorithm to
+ *  strict priority for Channel 2 over Channel 0 When reset, the creditbased shaper
+ *  algorithm schedules the traffic in Channel 2 for transmission
+ */
+#define EMAC_CH2_CBSD    (BIT(0))
+#define EMAC_CH2_CBSD_M  (EMAC_CH2_CBSD_V << EMAC_CH2_CBSD_S)
+#define EMAC_CH2_CBSD_V  0x00000001U
+#define EMAC_CH2_CBSD_S  0
+/** EMAC_CH2_CC : R/W; bitpos: [1]; default: 0;
+ *  Credit Control When reset, the accumulated credit parameter in the creditbased
+ *  shaper algorithm logic is set to zero when there is positive credit and no frame to
+ *  transmit in Channel 2 When there is no frame waiting in Channel 2 and other channel
+ *  is transmitting, no credit is accumulated When set, the accumulated credit
+ *  parameter in the creditbased shaper algorithm logic is not reset to zero when there
+ *  is positive credit and no frame to transmit in Channel 2 The credit accumulates
+ *  even when there is no frame waiting in Channel 2 and another channel is transmitting
+ */
+#define EMAC_CH2_CC    (BIT(1))
+#define EMAC_CH2_CC_M  (EMAC_CH2_CC_V << EMAC_CH2_CC_S)
+#define EMAC_CH2_CC_V  0x00000001U
+#define EMAC_CH2_CC_S  1
+/** EMAC_CH2_SLC : R/W; bitpos: [6:4]; default: 0;
+ *  Slot Count The software can program the number of slots _of duration 125 microsec_
+ *  over which the average transmitted bits per slot _provided in the CBS Status
+ *  register_ need to be computed for Channel 2 when the creditbased shaper algorithm
+ *  is enabled The encoding is as follows: 3'b000: 1 Slot 3'b001: 2 Slots 3'b010: 4
+ *  Slots 3'b011: 8 Slots 3'b100: 16 Slots 3'b1013'b111: Reserved
+ */
+#define EMAC_CH2_SLC    0x00000007U
+#define EMAC_CH2_SLC_M  (EMAC_CH2_SLC_V << EMAC_CH2_SLC_S)
+#define EMAC_CH2_SLC_V  0x00000007U
+#define EMAC_CH2_SLC_S  4
+/** EMAC_CH2_ABPSSIE : R/W; bitpos: [17]; default: 0;
+ *  Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts an
+ *  interrupt _sbd_intr_o or mci_intr_o_ when the average bits per slot status is
+ *  updated _Bit 17 _ABSU_ in Register 153_ for Channel 2 When this bit is cleared,
+ *  interrupt is not asserted for such an event
+ */
+#define EMAC_CH2_ABPSSIE    (BIT(17))
+#define EMAC_CH2_ABPSSIE_M  (EMAC_CH2_ABPSSIE_V << EMAC_CH2_ABPSSIE_S)
+#define EMAC_CH2_ABPSSIE_V  0x00000001U
+#define EMAC_CH2_ABPSSIE_S  17
+
+/** EMAC_CHANNEL2CBSSTATUS_REG register
+ *  Provides the average traffic transmitted in Channel 2
+ */
+#define EMAC_CHANNEL2CBSSTATUS_REG (DR_REG_EMAC_BASE + 0x1264)
+/** EMAC_CH2_ABS : RO; bitpos: [16:0]; default: 0;
+ *  Average Bits per Slot This field contains the average transmitted bits per slot
+ *  This field is computed over programmed number of slots _SLC bits in the CBS Control
+ *  Register_ for Channel 2 traffic The maximum value is 0x30D4 for 100 Mbps and
+ *  0x1E848 for 1000 Mbps
+ */
+#define EMAC_CH2_ABS    0x0001FFFFU
+#define EMAC_CH2_ABS_M  (EMAC_CH2_ABS_V << EMAC_CH2_ABS_S)
+#define EMAC_CH2_ABS_V  0x0001FFFFU
+#define EMAC_CH2_ABS_S  0
+/** EMAC_CH2_ABSU : RO; bitpos: [17]; default: 0;
+ *  ABS Updated When set, this bit indicates that the MAC has updated the ABS value
+ *  This bit is cleared when the application reads the ABS value
+ */
+#define EMAC_CH2_ABSU    (BIT(17))
+#define EMAC_CH2_ABSU_M  (EMAC_CH2_ABSU_V << EMAC_CH2_ABSU_S)
+#define EMAC_CH2_ABSU_V  0x00000001U
+#define EMAC_CH2_ABSU_S  17
+
+/** EMAC_CHANNEL2IDLESLOPECREDIT_REG register
+ *  Contains the idleSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 2
+ */
+#define EMAC_CHANNEL2IDLESLOPECREDIT_REG (DR_REG_EMAC_BASE + 0x1268)
+/** EMAC_CH2_ISC : R/W; bitpos: [13:0]; default: 0;
+ *  idleSlopeCredit This field contains the idleSlopeCredit value required for the
+ *  creditbased shaper algorithm for Channel 2 This is the rate of change of credit in
+ *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+ *  credit is increasing The software should program this field with computed credit in
+ *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+ *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode
+ */
+#define EMAC_CH2_ISC    0x00003FFFU
+#define EMAC_CH2_ISC_M  (EMAC_CH2_ISC_V << EMAC_CH2_ISC_S)
+#define EMAC_CH2_ISC_V  0x00003FFFU
+#define EMAC_CH2_ISC_S  0
+
+/** EMAC_CHANNEL2SENDSLOPECREDIT_REG register
+ *  Contains the sendSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 2
+ */
+#define EMAC_CHANNEL2SENDSLOPECREDIT_REG (DR_REG_EMAC_BASE + 0x126c)
+/** EMAC_CH2_SSC : R/W; bitpos: [13:0]; default: 0;
+ *  sendSlopeCredit This field contains the sendSlopeCredit value required for
+ *  creditbased shaper algorithm for Channel 2 This is the rate of change of credit in
+ *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+ *  credit is decreasing The software should program this field with computed credit in
+ *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+ *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode This field should be
+ *  programmed with absolute sendSlopeCredit value The creditbased shaper logic
+ *  subtracts it from the accumulated credit when Channel 2 is selected for transmission
+ */
+#define EMAC_CH2_SSC    0x00003FFFU
+#define EMAC_CH2_SSC_M  (EMAC_CH2_SSC_V << EMAC_CH2_SSC_S)
+#define EMAC_CH2_SSC_V  0x00003FFFU
+#define EMAC_CH2_SSC_S  0
+
+/** EMAC_CHANNEL2HICREDIT_REG register
+ *  Contains the hiCredit value required for the creditbased shaper algorithm for
+ *  Channel 2
+ */
+#define EMAC_CHANNEL2HICREDIT_REG (DR_REG_EMAC_BASE + 0x1270)
+/** EMAC_CH2_HC : R/W; bitpos: [28:0]; default: 0;
+ *  hiCredit This field contains the hiCredit value required for the creditbased shaper
+ *  algorithm for Channel 2 This is the maximum value that can be accumulated in the
+ *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+ *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+ *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+ *  0x0800_0000
+ */
+#define EMAC_CH2_HC    0x1FFFFFFFU
+#define EMAC_CH2_HC_M  (EMAC_CH2_HC_V << EMAC_CH2_HC_S)
+#define EMAC_CH2_HC_V  0x1FFFFFFFU
+#define EMAC_CH2_HC_S  0
+
+/** EMAC_CHANNEL2LOCREDIT_REG register
+ *  Contains the loCredit value required for the creditbased shaper algorithm for
+ *  Channel 2
+ */
+#define EMAC_CHANNEL2LOCREDIT_REG (DR_REG_EMAC_BASE + 0x1274)
+/** EMAC_CH2_LC : R/W; bitpos: [28:0]; default: 536870911;
+ *  loCredit This field contains the loCredit value required for the creditbased shaper
+ *  algorithm for Channel 2 This is the minimum value that can be accumulated in the
+ *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+ *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+ *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+ *  0x0800_0000 The programmed value is 2's complement _negative number_, that is,
+ *  0xF800_0000
+ */
+#define EMAC_CH2_LC    0x1FFFFFFFU
+#define EMAC_CH2_LC_M  (EMAC_CH2_LC_V << EMAC_CH2_LC_S)
+#define EMAC_CH2_LC_V  0x1FFFFFFFU
+#define EMAC_CH2_LC_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h
new file mode 100644
index 0000000000..a3b88516fa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h
@@ -0,0 +1,772 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: SDM Configure Registers */
+/** Type of sigmadeltan register
+ *  Duty Cycle Configure Register of SDMn
+ */
+typedef union {
+    struct {
+        /** sdn_in : R/W; bitpos: [7:0]; default: 0;
+         *  This field is used to configure the duty cycle of sigma delta modulation output.
+         */
+        uint32_t sdn_in:8;
+        /** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
+         *  This field is used to set a divider value to divide APB clock.
+         */
+        uint32_t sdn_prescale:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpiosd_sigmadeltan_reg_t;
+
+/** Type of sigmadelta_misc register
+ *  MISC Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** function_clk_en : R/W; bitpos: [30]; default: 0;
+         *  Clock enable bit of sigma delta modulation.
+         */
+        uint32_t function_clk_en:1;
+        /** spi_swap : R/W; bitpos: [31]; default: 0;
+         *  Reserved.
+         */
+        uint32_t spi_swap:1;
+    };
+    uint32_t val;
+} gpiosd_sigmadelta_misc_reg_t;
+
+
+/** Group: Glitch filter Configure Registers */
+/** Type of glitch_filter_chn register
+ *  Glitch Filter Configure Register of Channeln
+ */
+typedef union {
+    struct {
+        /** filter_ch0_en : R/W; bitpos: [0]; default: 0;
+         *  Glitch Filter channel enable bit.
+         */
+        uint32_t filter_ch0_en:1;
+        /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
+         *  Glitch Filter input io number.
+         */
+        uint32_t filter_ch0_input_io_num:6;
+        /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
+         *  Glitch Filter window threshold.
+         */
+        uint32_t filter_ch0_window_thres:6;
+        /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
+         *  Glitch Filter window width.
+         */
+        uint32_t filter_ch0_window_width:6;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} gpiosd_glitch_filter_chn_reg_t;
+
+
+/** Group: Etm Configure Registers */
+/** Type of etm_event_chn_cfg register
+ *  Etm Config register of Channeln
+ */
+typedef union {
+    struct {
+        /** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
+         *  Etm event channel select gpio.
+         */
+        uint32_t etm_ch0_event_sel:6;
+        uint32_t reserved_6:1;
+        /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
+         *  Etm event send enable bit.
+         */
+        uint32_t etm_ch0_event_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpiosd_etm_event_chn_cfg_reg_t;
+
+/** Type of etm_task_p0_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio0_en:1;
+        /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio0_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio1_en:1;
+        /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio1_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio2_en:1;
+        /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio2_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio3_en:1;
+        /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio3_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p0_cfg_reg_t;
+
+/** Type of etm_task_p1_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio4_en:1;
+        /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio4_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio5_en:1;
+        /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio5_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio6_en:1;
+        /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio6_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio7_en:1;
+        /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio7_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p1_cfg_reg_t;
+
+/** Type of etm_task_p2_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio8_en:1;
+        /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio8_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio9_en:1;
+        /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio9_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio10_en:1;
+        /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio10_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio11_en:1;
+        /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio11_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p2_cfg_reg_t;
+
+/** Type of etm_task_p3_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio12_en:1;
+        /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio12_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio13_en:1;
+        /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio13_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio14_en:1;
+        /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio14_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio15_en:1;
+        /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio15_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p3_cfg_reg_t;
+
+/** Type of etm_task_p4_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio16_en:1;
+        /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio16_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio17_en:1;
+        /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio17_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio18_en:1;
+        /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio18_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio19_en:1;
+        /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio19_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p4_cfg_reg_t;
+
+/** Type of etm_task_p5_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio20_en:1;
+        /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio20_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio21_en:1;
+        /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio21_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio22_en:1;
+        /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio22_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio23_en:1;
+        /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio23_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p5_cfg_reg_t;
+
+/** Type of etm_task_p6_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio24_en:1;
+        /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio24_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio25_en:1;
+        /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio25_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio26_en:1;
+        /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio26_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio27_en:1;
+        /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio27_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p6_cfg_reg_t;
+
+/** Type of etm_task_p7_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio28_en:1;
+        /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio28_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio29_en:1;
+        /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio29_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio30_en:1;
+        /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio30_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio31_en:1;
+        /** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio31_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p7_cfg_reg_t;
+
+/** Type of etm_task_p8_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio32_en:1;
+        /** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio32_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio33_en:1;
+        /** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio33_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio34_en:1;
+        /** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio34_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio35_en:1;
+        /** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio35_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p8_cfg_reg_t;
+
+/** Type of etm_task_p9_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio36_en:1;
+        /** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio36_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio37_en:1;
+        /** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio37_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio38_en:1;
+        /** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio38_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio39_en:1;
+        /** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio39_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p9_cfg_reg_t;
+
+/** Type of etm_task_p10_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio40_en:1;
+        /** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio40_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio41_en:1;
+        /** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio41_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio42_en:1;
+        /** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio42_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio43_en:1;
+        /** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio43_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p10_cfg_reg_t;
+
+/** Type of etm_task_p11_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio44_en:1;
+        /** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio44_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio45_en:1;
+        /** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio45_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio46_en:1;
+        /** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio46_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio47_en:1;
+        /** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio47_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p11_cfg_reg_t;
+
+/** Type of etm_task_p12_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio48_en:1;
+        /** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio48_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio49_en:1;
+        /** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio49_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio50_en:1;
+        /** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio50_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio51_en:1;
+        /** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio51_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p12_cfg_reg_t;
+
+/** Type of etm_task_p13_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio52_en:1;
+        /** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio52_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio53_en:1;
+        /** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio53_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio54_en:1;
+        /** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio54_sel:3;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p13_cfg_reg_t;
+
+
+/** Group: Version Register */
+/** Type of version register
+ *  Version Control Register
+ */
+typedef union {
+    struct {
+        /** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952;
+         *  Version control register.
+         */
+        uint32_t gpio_sd_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_version_reg_t;
+
+
+typedef struct {
+    volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8];
+    uint32_t reserved_020;
+    volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc;
+    uint32_t reserved_028[2];
+    volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8];
+    uint32_t reserved_050[4];
+    volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
+    uint32_t reserved_080[8];
+    volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
+    volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
+    volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
+    volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
+    volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
+    volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
+    volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
+    volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
+    volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
+    volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
+    volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
+    volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
+    volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
+    volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
+    uint32_t reserved_0d8[9];
+    volatile gpiosd_version_reg_t version;
+} gpiosd_dev_t;
+
+extern gpiosd_dev_t GPIO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_reg.h
new file mode 100644
index 0000000000..ce4b476a72
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_reg.h
@@ -0,0 +1,1455 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIOSD_SIGMADELTA0_REG register
+ *  Duty Cycle Configure Register of SDM0
+ */
+#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIOSD_BASE + 0x0)
+/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD0_IN    0x000000FFU
+#define GPIO_EXT_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
+#define GPIO_EXT_SD0_IN_V  0x000000FFU
+#define GPIO_EXT_SD0_IN_S  0
+/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD0_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
+#define GPIO_EXT_SD0_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD0_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA1_REG register
+ *  Duty Cycle Configure Register of SDM1
+ */
+#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIOSD_BASE + 0x4)
+/** GPIOSD_SD1_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD1_IN    0x000000FFU
+#define GPIO_EXT_SD1_IN_M  (GPIOSD_SD1_IN_V << GPIOSD_SD1_IN_S)
+#define GPIO_EXT_SD1_IN_V  0x000000FFU
+#define GPIO_EXT_SD1_IN_S  0
+/** GPIOSD_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD1_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD1_PRESCALE_M  (GPIOSD_SD1_PRESCALE_V << GPIOSD_SD1_PRESCALE_S)
+#define GPIO_EXT_SD1_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD1_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA2_REG register
+ *  Duty Cycle Configure Register of SDM2
+ */
+#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIOSD_BASE + 0x8)
+/** GPIOSD_SD2_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD2_IN    0x000000FFU
+#define GPIO_EXT_SD2_IN_M  (GPIOSD_SD2_IN_V << GPIOSD_SD2_IN_S)
+#define GPIO_EXT_SD2_IN_V  0x000000FFU
+#define GPIO_EXT_SD2_IN_S  0
+/** GPIOSD_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD2_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD2_PRESCALE_M  (GPIOSD_SD2_PRESCALE_V << GPIOSD_SD2_PRESCALE_S)
+#define GPIO_EXT_SD2_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD2_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA3_REG register
+ *  Duty Cycle Configure Register of SDM3
+ */
+#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIOSD_BASE + 0xc)
+/** GPIOSD_SD3_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD3_IN    0x000000FFU
+#define GPIO_EXT_SD3_IN_M  (GPIOSD_SD3_IN_V << GPIOSD_SD3_IN_S)
+#define GPIO_EXT_SD3_IN_V  0x000000FFU
+#define GPIO_EXT_SD3_IN_S  0
+/** GPIOSD_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD3_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD3_PRESCALE_M  (GPIOSD_SD3_PRESCALE_V << GPIOSD_SD3_PRESCALE_S)
+#define GPIO_EXT_SD3_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD3_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA4_REG register
+ *  Duty Cycle Configure Register of SDM4
+ */
+#define GPIO_EXT_SIGMADELTA4_REG (DR_REG_GPIOSD_BASE + 0x10)
+/** GPIOSD_SD4_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD4_IN    0x000000FFU
+#define GPIO_EXT_SD4_IN_M  (GPIOSD_SD4_IN_V << GPIOSD_SD4_IN_S)
+#define GPIO_EXT_SD4_IN_V  0x000000FFU
+#define GPIO_EXT_SD4_IN_S  0
+/** GPIOSD_SD4_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD4_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD4_PRESCALE_M  (GPIOSD_SD4_PRESCALE_V << GPIOSD_SD4_PRESCALE_S)
+#define GPIO_EXT_SD4_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD4_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA5_REG register
+ *  Duty Cycle Configure Register of SDM5
+ */
+#define GPIO_EXT_SIGMADELTA5_REG (DR_REG_GPIOSD_BASE + 0x14)
+/** GPIOSD_SD5_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD5_IN    0x000000FFU
+#define GPIO_EXT_SD5_IN_M  (GPIOSD_SD5_IN_V << GPIOSD_SD5_IN_S)
+#define GPIO_EXT_SD5_IN_V  0x000000FFU
+#define GPIO_EXT_SD5_IN_S  0
+/** GPIOSD_SD5_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD5_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD5_PRESCALE_M  (GPIOSD_SD5_PRESCALE_V << GPIOSD_SD5_PRESCALE_S)
+#define GPIO_EXT_SD5_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD5_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA6_REG register
+ *  Duty Cycle Configure Register of SDM6
+ */
+#define GPIO_EXT_SIGMADELTA6_REG (DR_REG_GPIOSD_BASE + 0x18)
+/** GPIOSD_SD6_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD6_IN    0x000000FFU
+#define GPIO_EXT_SD6_IN_M  (GPIOSD_SD6_IN_V << GPIOSD_SD6_IN_S)
+#define GPIO_EXT_SD6_IN_V  0x000000FFU
+#define GPIO_EXT_SD6_IN_S  0
+/** GPIOSD_SD6_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD6_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD6_PRESCALE_M  (GPIOSD_SD6_PRESCALE_V << GPIOSD_SD6_PRESCALE_S)
+#define GPIO_EXT_SD6_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD6_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA7_REG register
+ *  Duty Cycle Configure Register of SDM7
+ */
+#define GPIO_EXT_SIGMADELTA7_REG (DR_REG_GPIOSD_BASE + 0x1c)
+/** GPIOSD_SD7_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD7_IN    0x000000FFU
+#define GPIO_EXT_SD7_IN_M  (GPIOSD_SD7_IN_V << GPIOSD_SD7_IN_S)
+#define GPIO_EXT_SD7_IN_V  0x000000FFU
+#define GPIO_EXT_SD7_IN_S  0
+/** GPIOSD_SD7_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD7_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD7_PRESCALE_M  (GPIOSD_SD7_PRESCALE_V << GPIOSD_SD7_PRESCALE_S)
+#define GPIO_EXT_SD7_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD7_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA_MISC_REG register
+ *  MISC Register
+ */
+#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIOSD_BASE + 0x24)
+/** GPIOSD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Clock enable bit of sigma delta modulation.
+ */
+#define GPIO_EXT_FUNCTION_CLK_EN    (BIT(30))
+#define GPIO_EXT_FUNCTION_CLK_EN_M  (GPIOSD_FUNCTION_CLK_EN_V << GPIOSD_FUNCTION_CLK_EN_S)
+#define GPIO_EXT_FUNCTION_CLK_EN_V  0x00000001U
+#define GPIO_EXT_FUNCTION_CLK_EN_S  30
+/** GPIOSD_SPI_SWAP : R/W; bitpos: [31]; default: 0;
+ *  Reserved.
+ */
+#define GPIO_EXT_SPI_SWAP    (BIT(31))
+#define GPIO_EXT_SPI_SWAP_M  (GPIOSD_SPI_SWAP_V << GPIOSD_SPI_SWAP_S)
+#define GPIO_EXT_SPI_SWAP_V  0x00000001U
+#define GPIO_EXT_SPI_SWAP_S  31
+
+/** GPIOSD_GLITCH_FILTER_CH0_REG register
+ *  Glitch Filter Configure Register of Channel0
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIOSD_BASE + 0x30)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH1_REG register
+ *  Glitch Filter Configure Register of Channel1
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIOSD_BASE + 0x34)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH2_REG register
+ *  Glitch Filter Configure Register of Channel2
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIOSD_BASE + 0x38)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH3_REG register
+ *  Glitch Filter Configure Register of Channel3
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIOSD_BASE + 0x3c)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH4_REG register
+ *  Glitch Filter Configure Register of Channel4
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIOSD_BASE + 0x40)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH5_REG register
+ *  Glitch Filter Configure Register of Channel5
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIOSD_BASE + 0x44)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH6_REG register
+ *  Glitch Filter Configure Register of Channel6
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIOSD_BASE + 0x48)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH7_REG register
+ *  Glitch Filter Configure Register of Channel7
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIOSD_BASE + 0x4c)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_ETM_EVENT_CH0_CFG_REG register
+ *  Etm Config register of Channel0
+ */
+#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIOSD_BASE + 0x60)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH1_CFG_REG register
+ *  Etm Config register of Channel1
+ */
+#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIOSD_BASE + 0x64)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH2_CFG_REG register
+ *  Etm Config register of Channel2
+ */
+#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIOSD_BASE + 0x68)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH3_CFG_REG register
+ *  Etm Config register of Channel3
+ */
+#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIOSD_BASE + 0x6c)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH4_CFG_REG register
+ *  Etm Config register of Channel4
+ */
+#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIOSD_BASE + 0x70)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH5_CFG_REG register
+ *  Etm Config register of Channel5
+ */
+#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIOSD_BASE + 0x74)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH6_CFG_REG register
+ *  Etm Config register of Channel6
+ */
+#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIOSD_BASE + 0x78)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH7_CFG_REG register
+ *  Etm Config register of Channel7
+ */
+#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIOSD_BASE + 0x7c)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_TASK_P0_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIOSD_BASE + 0xa0)
+/** GPIOSD_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO0_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO0_EN_M  (GPIOSD_ETM_TASK_GPIO0_EN_V << GPIOSD_ETM_TASK_GPIO0_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO0_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO0_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL_M  (GPIOSD_ETM_TASK_GPIO0_SEL_V << GPIOSD_ETM_TASK_GPIO0_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO1_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO1_EN_M  (GPIOSD_ETM_TASK_GPIO1_EN_V << GPIOSD_ETM_TASK_GPIO1_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO1_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO1_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL_M  (GPIOSD_ETM_TASK_GPIO1_SEL_V << GPIOSD_ETM_TASK_GPIO1_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO2_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO2_EN_M  (GPIOSD_ETM_TASK_GPIO2_EN_V << GPIOSD_ETM_TASK_GPIO2_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO2_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO2_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL_M  (GPIOSD_ETM_TASK_GPIO2_SEL_V << GPIOSD_ETM_TASK_GPIO2_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO3_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO3_EN_M  (GPIOSD_ETM_TASK_GPIO3_EN_V << GPIOSD_ETM_TASK_GPIO3_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO3_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO3_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL_M  (GPIOSD_ETM_TASK_GPIO3_SEL_V << GPIOSD_ETM_TASK_GPIO3_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P1_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIOSD_BASE + 0xa4)
+/** GPIOSD_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO4_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO4_EN_M  (GPIOSD_ETM_TASK_GPIO4_EN_V << GPIOSD_ETM_TASK_GPIO4_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO4_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO4_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL_M  (GPIOSD_ETM_TASK_GPIO4_SEL_V << GPIOSD_ETM_TASK_GPIO4_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO5_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO5_EN_M  (GPIOSD_ETM_TASK_GPIO5_EN_V << GPIOSD_ETM_TASK_GPIO5_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO5_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO5_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL_M  (GPIOSD_ETM_TASK_GPIO5_SEL_V << GPIOSD_ETM_TASK_GPIO5_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO6_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO6_EN_M  (GPIOSD_ETM_TASK_GPIO6_EN_V << GPIOSD_ETM_TASK_GPIO6_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO6_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO6_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL_M  (GPIOSD_ETM_TASK_GPIO6_SEL_V << GPIOSD_ETM_TASK_GPIO6_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO7_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO7_EN_M  (GPIOSD_ETM_TASK_GPIO7_EN_V << GPIOSD_ETM_TASK_GPIO7_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO7_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO7_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL_M  (GPIOSD_ETM_TASK_GPIO7_SEL_V << GPIOSD_ETM_TASK_GPIO7_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P2_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIOSD_BASE + 0xa8)
+/** GPIOSD_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO8_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO8_EN_M  (GPIOSD_ETM_TASK_GPIO8_EN_V << GPIOSD_ETM_TASK_GPIO8_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO8_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO8_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL_M  (GPIOSD_ETM_TASK_GPIO8_SEL_V << GPIOSD_ETM_TASK_GPIO8_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO9_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO9_EN_M  (GPIOSD_ETM_TASK_GPIO9_EN_V << GPIOSD_ETM_TASK_GPIO9_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO9_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO9_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL_M  (GPIOSD_ETM_TASK_GPIO9_SEL_V << GPIOSD_ETM_TASK_GPIO9_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO10_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO10_EN_M  (GPIOSD_ETM_TASK_GPIO10_EN_V << GPIOSD_ETM_TASK_GPIO10_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO10_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO10_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL_M  (GPIOSD_ETM_TASK_GPIO10_SEL_V << GPIOSD_ETM_TASK_GPIO10_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO11_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO11_EN_M  (GPIOSD_ETM_TASK_GPIO11_EN_V << GPIOSD_ETM_TASK_GPIO11_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO11_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO11_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL_M  (GPIOSD_ETM_TASK_GPIO11_SEL_V << GPIOSD_ETM_TASK_GPIO11_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P3_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIOSD_BASE + 0xac)
+/** GPIOSD_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO12_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO12_EN_M  (GPIOSD_ETM_TASK_GPIO12_EN_V << GPIOSD_ETM_TASK_GPIO12_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO12_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO12_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL_M  (GPIOSD_ETM_TASK_GPIO12_SEL_V << GPIOSD_ETM_TASK_GPIO12_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO13_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO13_EN_M  (GPIOSD_ETM_TASK_GPIO13_EN_V << GPIOSD_ETM_TASK_GPIO13_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO13_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO13_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL_M  (GPIOSD_ETM_TASK_GPIO13_SEL_V << GPIOSD_ETM_TASK_GPIO13_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO14_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO14_EN_M  (GPIOSD_ETM_TASK_GPIO14_EN_V << GPIOSD_ETM_TASK_GPIO14_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO14_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO14_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL_M  (GPIOSD_ETM_TASK_GPIO14_SEL_V << GPIOSD_ETM_TASK_GPIO14_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO15_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO15_EN_M  (GPIOSD_ETM_TASK_GPIO15_EN_V << GPIOSD_ETM_TASK_GPIO15_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO15_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO15_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL_M  (GPIOSD_ETM_TASK_GPIO15_SEL_V << GPIOSD_ETM_TASK_GPIO15_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P4_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIOSD_BASE + 0xb0)
+/** GPIOSD_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO16_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO16_EN_M  (GPIOSD_ETM_TASK_GPIO16_EN_V << GPIOSD_ETM_TASK_GPIO16_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO16_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO16_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL_M  (GPIOSD_ETM_TASK_GPIO16_SEL_V << GPIOSD_ETM_TASK_GPIO16_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO17_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO17_EN_M  (GPIOSD_ETM_TASK_GPIO17_EN_V << GPIOSD_ETM_TASK_GPIO17_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO17_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO17_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL_M  (GPIOSD_ETM_TASK_GPIO17_SEL_V << GPIOSD_ETM_TASK_GPIO17_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO18_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO18_EN_M  (GPIOSD_ETM_TASK_GPIO18_EN_V << GPIOSD_ETM_TASK_GPIO18_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO18_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO18_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL_M  (GPIOSD_ETM_TASK_GPIO18_SEL_V << GPIOSD_ETM_TASK_GPIO18_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO19_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO19_EN_M  (GPIOSD_ETM_TASK_GPIO19_EN_V << GPIOSD_ETM_TASK_GPIO19_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO19_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO19_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL_M  (GPIOSD_ETM_TASK_GPIO19_SEL_V << GPIOSD_ETM_TASK_GPIO19_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P5_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIOSD_BASE + 0xb4)
+/** GPIOSD_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO20_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO20_EN_M  (GPIOSD_ETM_TASK_GPIO20_EN_V << GPIOSD_ETM_TASK_GPIO20_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO20_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO20_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL_M  (GPIOSD_ETM_TASK_GPIO20_SEL_V << GPIOSD_ETM_TASK_GPIO20_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO21_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO21_EN_M  (GPIOSD_ETM_TASK_GPIO21_EN_V << GPIOSD_ETM_TASK_GPIO21_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO21_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO21_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL_M  (GPIOSD_ETM_TASK_GPIO21_SEL_V << GPIOSD_ETM_TASK_GPIO21_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO22_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO22_EN_M  (GPIOSD_ETM_TASK_GPIO22_EN_V << GPIOSD_ETM_TASK_GPIO22_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO22_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO22_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL_M  (GPIOSD_ETM_TASK_GPIO22_SEL_V << GPIOSD_ETM_TASK_GPIO22_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO23_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO23_EN_M  (GPIOSD_ETM_TASK_GPIO23_EN_V << GPIOSD_ETM_TASK_GPIO23_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO23_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO23_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL_M  (GPIOSD_ETM_TASK_GPIO23_SEL_V << GPIOSD_ETM_TASK_GPIO23_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P6_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P6_CFG_REG (DR_REG_GPIOSD_BASE + 0xb8)
+/** GPIOSD_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO24_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO24_EN_M  (GPIOSD_ETM_TASK_GPIO24_EN_V << GPIOSD_ETM_TASK_GPIO24_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO24_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO24_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL_M  (GPIOSD_ETM_TASK_GPIO24_SEL_V << GPIOSD_ETM_TASK_GPIO24_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO25_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO25_EN_M  (GPIOSD_ETM_TASK_GPIO25_EN_V << GPIOSD_ETM_TASK_GPIO25_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO25_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO25_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL_M  (GPIOSD_ETM_TASK_GPIO25_SEL_V << GPIOSD_ETM_TASK_GPIO25_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO26_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO26_EN_M  (GPIOSD_ETM_TASK_GPIO26_EN_V << GPIOSD_ETM_TASK_GPIO26_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO26_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO26_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL_M  (GPIOSD_ETM_TASK_GPIO26_SEL_V << GPIOSD_ETM_TASK_GPIO26_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO27_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO27_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO27_EN_M  (GPIOSD_ETM_TASK_GPIO27_EN_V << GPIOSD_ETM_TASK_GPIO27_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO27_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO27_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO27_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL_M  (GPIOSD_ETM_TASK_GPIO27_SEL_V << GPIOSD_ETM_TASK_GPIO27_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P7_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P7_CFG_REG (DR_REG_GPIOSD_BASE + 0xbc)
+/** GPIOSD_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO28_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO28_EN_M  (GPIOSD_ETM_TASK_GPIO28_EN_V << GPIOSD_ETM_TASK_GPIO28_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO28_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO28_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO28_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL_M  (GPIOSD_ETM_TASK_GPIO28_SEL_V << GPIOSD_ETM_TASK_GPIO28_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO29_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO29_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO29_EN_M  (GPIOSD_ETM_TASK_GPIO29_EN_V << GPIOSD_ETM_TASK_GPIO29_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO29_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO29_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO29_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL_M  (GPIOSD_ETM_TASK_GPIO29_SEL_V << GPIOSD_ETM_TASK_GPIO29_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO30_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO30_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO30_EN_M  (GPIOSD_ETM_TASK_GPIO30_EN_V << GPIOSD_ETM_TASK_GPIO30_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO30_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO30_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO30_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL_M  (GPIOSD_ETM_TASK_GPIO30_SEL_V << GPIOSD_ETM_TASK_GPIO30_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO31_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO31_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO31_EN_M  (GPIOSD_ETM_TASK_GPIO31_EN_V << GPIOSD_ETM_TASK_GPIO31_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO31_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO31_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO31_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL_M  (GPIOSD_ETM_TASK_GPIO31_SEL_V << GPIOSD_ETM_TASK_GPIO31_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P8_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P8_CFG_REG (DR_REG_GPIOSD_BASE + 0xc0)
+/** GPIOSD_ETM_TASK_GPIO32_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO32_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO32_EN_M  (GPIOSD_ETM_TASK_GPIO32_EN_V << GPIOSD_ETM_TASK_GPIO32_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO32_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO32_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO32_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL_M  (GPIOSD_ETM_TASK_GPIO32_SEL_V << GPIOSD_ETM_TASK_GPIO32_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO33_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO33_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO33_EN_M  (GPIOSD_ETM_TASK_GPIO33_EN_V << GPIOSD_ETM_TASK_GPIO33_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO33_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO33_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO33_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL_M  (GPIOSD_ETM_TASK_GPIO33_SEL_V << GPIOSD_ETM_TASK_GPIO33_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO34_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO34_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO34_EN_M  (GPIOSD_ETM_TASK_GPIO34_EN_V << GPIOSD_ETM_TASK_GPIO34_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO34_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO34_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO34_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL_M  (GPIOSD_ETM_TASK_GPIO34_SEL_V << GPIOSD_ETM_TASK_GPIO34_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO35_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO35_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO35_EN_M  (GPIOSD_ETM_TASK_GPIO35_EN_V << GPIOSD_ETM_TASK_GPIO35_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO35_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO35_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO35_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL_M  (GPIOSD_ETM_TASK_GPIO35_SEL_V << GPIOSD_ETM_TASK_GPIO35_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P9_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P9_CFG_REG (DR_REG_GPIOSD_BASE + 0xc4)
+/** GPIOSD_ETM_TASK_GPIO36_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO36_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO36_EN_M  (GPIOSD_ETM_TASK_GPIO36_EN_V << GPIOSD_ETM_TASK_GPIO36_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO36_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO36_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO36_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL_M  (GPIOSD_ETM_TASK_GPIO36_SEL_V << GPIOSD_ETM_TASK_GPIO36_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO37_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO37_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO37_EN_M  (GPIOSD_ETM_TASK_GPIO37_EN_V << GPIOSD_ETM_TASK_GPIO37_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO37_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO37_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO37_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL_M  (GPIOSD_ETM_TASK_GPIO37_SEL_V << GPIOSD_ETM_TASK_GPIO37_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO38_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO38_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO38_EN_M  (GPIOSD_ETM_TASK_GPIO38_EN_V << GPIOSD_ETM_TASK_GPIO38_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO38_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO38_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO38_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL_M  (GPIOSD_ETM_TASK_GPIO38_SEL_V << GPIOSD_ETM_TASK_GPIO38_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO39_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO39_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO39_EN_M  (GPIOSD_ETM_TASK_GPIO39_EN_V << GPIOSD_ETM_TASK_GPIO39_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO39_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO39_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO39_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL_M  (GPIOSD_ETM_TASK_GPIO39_SEL_V << GPIOSD_ETM_TASK_GPIO39_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P10_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P10_CFG_REG (DR_REG_GPIOSD_BASE + 0xc8)
+/** GPIOSD_ETM_TASK_GPIO40_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO40_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO40_EN_M  (GPIOSD_ETM_TASK_GPIO40_EN_V << GPIOSD_ETM_TASK_GPIO40_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO40_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO40_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO40_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL_M  (GPIOSD_ETM_TASK_GPIO40_SEL_V << GPIOSD_ETM_TASK_GPIO40_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO41_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO41_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO41_EN_M  (GPIOSD_ETM_TASK_GPIO41_EN_V << GPIOSD_ETM_TASK_GPIO41_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO41_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO41_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO41_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL_M  (GPIOSD_ETM_TASK_GPIO41_SEL_V << GPIOSD_ETM_TASK_GPIO41_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO42_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO42_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO42_EN_M  (GPIOSD_ETM_TASK_GPIO42_EN_V << GPIOSD_ETM_TASK_GPIO42_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO42_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO42_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO42_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL_M  (GPIOSD_ETM_TASK_GPIO42_SEL_V << GPIOSD_ETM_TASK_GPIO42_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO43_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO43_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO43_EN_M  (GPIOSD_ETM_TASK_GPIO43_EN_V << GPIOSD_ETM_TASK_GPIO43_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO43_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO43_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO43_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL_M  (GPIOSD_ETM_TASK_GPIO43_SEL_V << GPIOSD_ETM_TASK_GPIO43_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P11_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P11_CFG_REG (DR_REG_GPIOSD_BASE + 0xcc)
+/** GPIOSD_ETM_TASK_GPIO44_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO44_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO44_EN_M  (GPIOSD_ETM_TASK_GPIO44_EN_V << GPIOSD_ETM_TASK_GPIO44_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO44_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO44_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO44_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL_M  (GPIOSD_ETM_TASK_GPIO44_SEL_V << GPIOSD_ETM_TASK_GPIO44_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO45_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO45_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO45_EN_M  (GPIOSD_ETM_TASK_GPIO45_EN_V << GPIOSD_ETM_TASK_GPIO45_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO45_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO45_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO45_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL_M  (GPIOSD_ETM_TASK_GPIO45_SEL_V << GPIOSD_ETM_TASK_GPIO45_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO46_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO46_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO46_EN_M  (GPIOSD_ETM_TASK_GPIO46_EN_V << GPIOSD_ETM_TASK_GPIO46_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO46_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO46_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO46_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL_M  (GPIOSD_ETM_TASK_GPIO46_SEL_V << GPIOSD_ETM_TASK_GPIO46_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO47_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO47_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO47_EN_M  (GPIOSD_ETM_TASK_GPIO47_EN_V << GPIOSD_ETM_TASK_GPIO47_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO47_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO47_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO47_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL_M  (GPIOSD_ETM_TASK_GPIO47_SEL_V << GPIOSD_ETM_TASK_GPIO47_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P12_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P12_CFG_REG (DR_REG_GPIOSD_BASE + 0xd0)
+/** GPIOSD_ETM_TASK_GPIO48_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO48_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO48_EN_M  (GPIOSD_ETM_TASK_GPIO48_EN_V << GPIOSD_ETM_TASK_GPIO48_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO48_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO48_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO48_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL_M  (GPIOSD_ETM_TASK_GPIO48_SEL_V << GPIOSD_ETM_TASK_GPIO48_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO49_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO49_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO49_EN_M  (GPIOSD_ETM_TASK_GPIO49_EN_V << GPIOSD_ETM_TASK_GPIO49_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO49_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO49_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO49_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL_M  (GPIOSD_ETM_TASK_GPIO49_SEL_V << GPIOSD_ETM_TASK_GPIO49_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO50_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO50_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO50_EN_M  (GPIOSD_ETM_TASK_GPIO50_EN_V << GPIOSD_ETM_TASK_GPIO50_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO50_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO50_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO50_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL_M  (GPIOSD_ETM_TASK_GPIO50_SEL_V << GPIOSD_ETM_TASK_GPIO50_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO51_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO51_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO51_EN_M  (GPIOSD_ETM_TASK_GPIO51_EN_V << GPIOSD_ETM_TASK_GPIO51_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO51_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO51_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO51_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL_M  (GPIOSD_ETM_TASK_GPIO51_SEL_V << GPIOSD_ETM_TASK_GPIO51_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P13_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P13_CFG_REG (DR_REG_GPIOSD_BASE + 0xd4)
+/** GPIOSD_ETM_TASK_GPIO52_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO52_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO52_EN_M  (GPIOSD_ETM_TASK_GPIO52_EN_V << GPIOSD_ETM_TASK_GPIO52_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO52_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO52_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO52_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL_M  (GPIOSD_ETM_TASK_GPIO52_SEL_V << GPIOSD_ETM_TASK_GPIO52_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO53_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO53_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO53_EN_M  (GPIOSD_ETM_TASK_GPIO53_EN_V << GPIOSD_ETM_TASK_GPIO53_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO53_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO53_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO53_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL_M  (GPIOSD_ETM_TASK_GPIO53_SEL_V << GPIOSD_ETM_TASK_GPIO53_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO54_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO54_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO54_EN_M  (GPIOSD_ETM_TASK_GPIO54_EN_V << GPIOSD_ETM_TASK_GPIO54_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO54_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO54_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO54_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL_M  (GPIOSD_ETM_TASK_GPIO54_SEL_V << GPIOSD_ETM_TASK_GPIO54_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL_S  17
+
+/** GPIOSD_VERSION_REG register
+ *  Version Control Register
+ */
+#define GPIO_EXT_VERSION_REG (DR_REG_GPIOSD_BASE + 0xfc)
+/** GPIOSD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35663952;
+ *  Version control register.
+ */
+#define GPIO_EXT_GPIO_SD_DATE    0x0FFFFFFFU
+#define GPIO_EXT_GPIO_SD_DATE_M  (GPIOSD_GPIO_SD_DATE_V << GPIOSD_GPIO_SD_DATE_S)
+#define GPIO_EXT_GPIO_SD_DATE_V  0x0FFFFFFFU
+#define GPIO_EXT_GPIO_SD_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_struct.h
new file mode 100644
index 0000000000..617c6be66c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_struct.h
@@ -0,0 +1,194 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: SDM Configure Registers */
+/** Type of sigmadeltan register
+ *  Duty Cycle Configure Register of SDMn
+ */
+typedef union {
+    struct {
+        /** duty : R/W; bitpos: [7:0]; default: 0;
+         *  This field is used to configure the duty cycle of sigma delta modulation output.
+         */
+        uint32_t duty: 8;
+        /** prescale : R/W; bitpos: [15:8]; default: 255;
+         *  This field is used to set a divider value to divide APB clock.
+         */
+        uint32_t prescale: 8;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} gpio_sigmadelta_chn_reg_t;
+
+/** Type of sigmadelta_misc register
+ *  MISC Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 30;
+        /** function_clk_en : R/W; bitpos: [30]; default: 0;
+         *  Clock enable bit of sigma delta modulation.
+         */
+        uint32_t function_clk_en: 1;
+        /** spi_swap : R/W; bitpos: [31]; default: 0;
+         *  Reserved.
+         */
+        uint32_t spi_swap: 1;
+    };
+    uint32_t val;
+} gpio_sigmadelta_misc_reg_t;
+
+/** Group: Glitch filter Configure Registers */
+/** Type of glitch_filter_chn register
+ *  Glitch Filter Configure Register of Channeln
+ */
+typedef union {
+    struct {
+        /** filter_chn_en : R/W; bitpos: [0]; default: 0;
+         *  Glitch Filter channel enable bit.
+         */
+        uint32_t filter_chn_en: 1;
+        /** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0;
+         *  Glitch Filter input io number.
+         */
+        uint32_t filter_chn_input_io_num: 6;
+        /** filter_chn_window_thres : R/W; bitpos: [12:7]; default: 0;
+         *  Glitch Filter window threshold.
+         */
+        uint32_t filter_chn_window_thres: 6;
+        /** filter_chn_window_width : R/W; bitpos: [18:13]; default: 0;
+         *  Glitch Filter window width.
+         */
+        uint32_t filter_chn_window_width: 6;
+        uint32_t reserved_19: 13;
+    };
+    uint32_t val;
+} gpio_glitch_filter_chn_reg_t;
+
+/** Group: Etm Configure Registers */
+/** Type of etm_event_chn_cfg register
+ *  Etm Config register of Channeln
+ */
+typedef union {
+    struct {
+        /** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0;
+         *  Etm event channel select gpio.
+         */
+        uint32_t etm_chn_event_sel: 6;
+        uint32_t reserved_6: 1;
+        /** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
+         *  Etm event send enable bit.
+         */
+        uint32_t etm_chn_event_en: 1;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} gpio_etm_event_chn_cfg_reg_t;
+
+/** Type of etm_task_p0_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio0_en: 1;
+        /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio0_sel: 3;
+        uint32_t reserved_4: 4;
+        /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio1_en: 1;
+        /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio1_sel: 3;
+        uint32_t reserved_12: 4;
+        /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio2_en: 1;
+        /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio2_sel: 3;
+        uint32_t reserved_20: 4;
+        /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio3_en: 1;
+        /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio3_sel: 3;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} gpio_etm_task_pn_cfg_reg_t;
+
+/** Group: Version Register */
+/** Type of version register
+ *  Version Control Register
+ */
+typedef union {
+    struct {
+        /** gpio_ext_date : R/W; bitpos: [27:0]; default: 35663952;
+         *  Version control register.
+         */
+        uint32_t gpio_ext_date: 28;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} gpio_ext_version_reg_t;
+
+typedef struct gpio_sd_dev_t {
+    volatile gpio_sigmadelta_chn_reg_t channel[8];
+    uint32_t reserved_020;
+    volatile gpio_sigmadelta_misc_reg_t misc;
+} gpio_sd_dev_t;
+
+typedef struct gpio_glitch_filter_dev_t {
+    volatile gpio_glitch_filter_chn_reg_t glitch_filter_chn[8];
+} gpio_glitch_filter_dev_t;
+
+typedef struct gpio_etm_dev_t {
+    volatile gpio_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
+    uint32_t reserved_080[8];
+    volatile gpio_etm_task_pn_cfg_reg_t etm_task_pn_cfg[14];
+} gpio_etm_dev_t;
+
+typedef struct {
+    volatile gpio_sd_dev_t sigma_delta;
+    uint32_t reserved_028[2];
+    volatile gpio_glitch_filter_dev_t glitch_filter;
+    uint32_t reserved_050[4];
+    volatile gpio_etm_dev_t etm;
+    uint32_t reserved_0d8[9];
+    volatile gpio_ext_version_reg_t version;
+} gpio_ext_dev_t;
+
+extern gpio_sd_dev_t SDM;
+extern gpio_glitch_filter_dev_t GLITCH_FILTER;
+extern gpio_etm_dev_t GPIO_ETM;
+extern gpio_ext_dev_t GPIO_EXT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_reg.h
new file mode 100644
index 0000000000..af324fea51
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/gpio_reg.h
@@ -0,0 +1,12163 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO_BT_SELECT_REG register
+ *  GPIO bit select register
+ */
+#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0)
+/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0;
+ *  GPIO bit select register
+ */
+#define GPIO_BT_SEL    0xFFFFFFFFU
+#define GPIO_BT_SEL_M  (GPIO_BT_SEL_V << GPIO_BT_SEL_S)
+#define GPIO_BT_SEL_V  0xFFFFFFFFU
+#define GPIO_BT_SEL_S  0
+
+/** GPIO_OUT_REG register
+ *  GPIO output register for GPIO0-31
+ */
+#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
+/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0;
+ *  GPIO output register for GPIO0-31
+ */
+#define GPIO_OUT_DATA_ORIG    0xFFFFFFFFU
+#define GPIO_OUT_DATA_ORIG_M  (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S)
+#define GPIO_OUT_DATA_ORIG_V  0xFFFFFFFFU
+#define GPIO_OUT_DATA_ORIG_S  0
+
+/** GPIO_OUT_W1TS_REG register
+ *  GPIO output set register for GPIO0-31
+ */
+#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8)
+/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output set register for GPIO0-31
+ */
+#define GPIO_OUT_W1TS    0xFFFFFFFFU
+#define GPIO_OUT_W1TS_M  (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S)
+#define GPIO_OUT_W1TS_V  0xFFFFFFFFU
+#define GPIO_OUT_W1TS_S  0
+
+/** GPIO_OUT_W1TC_REG register
+ *  GPIO output clear register for GPIO0-31
+ */
+#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc)
+/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output clear register for GPIO0-31
+ */
+#define GPIO_OUT_W1TC    0xFFFFFFFFU
+#define GPIO_OUT_W1TC_M  (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S)
+#define GPIO_OUT_W1TC_V  0xFFFFFFFFU
+#define GPIO_OUT_W1TC_S  0
+
+/** GPIO_OUT1_REG register
+ *  GPIO output register for GPIO32-56
+ */
+#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10)
+/** GPIO_OUT1_DATA_ORIG : R/W/SC/WTC; bitpos: [24:0]; default: 0;
+ *  GPIO output register for GPIO32-56
+ */
+#define GPIO_OUT1_DATA_ORIG    0x01FFFFFFU
+#define GPIO_OUT1_DATA_ORIG_M  (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S)
+#define GPIO_OUT1_DATA_ORIG_V  0x01FFFFFFU
+#define GPIO_OUT1_DATA_ORIG_S  0
+
+/** GPIO_OUT1_W1TS_REG register
+ *  GPIO output set register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14)
+/** GPIO_OUT1_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output set register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TS    0x01FFFFFFU
+#define GPIO_OUT1_W1TS_M  (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S)
+#define GPIO_OUT1_W1TS_V  0x01FFFFFFU
+#define GPIO_OUT1_W1TS_S  0
+
+/** GPIO_OUT1_W1TC_REG register
+ *  GPIO output clear register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18)
+/** GPIO_OUT1_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output clear register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TC    0x01FFFFFFU
+#define GPIO_OUT1_W1TC_M  (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S)
+#define GPIO_OUT1_W1TC_V  0x01FFFFFFU
+#define GPIO_OUT1_W1TC_S  0
+
+/** GPIO_ENABLE_REG register
+ *  GPIO output enable register for GPIO0-31
+ */
+#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20)
+/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0;
+ *  GPIO output enable register for GPIO0-31
+ */
+#define GPIO_ENABLE_DATA    0xFFFFFFFFU
+#define GPIO_ENABLE_DATA_M  (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S)
+#define GPIO_ENABLE_DATA_V  0xFFFFFFFFU
+#define GPIO_ENABLE_DATA_S  0
+
+/** GPIO_ENABLE_W1TS_REG register
+ *  GPIO output enable set register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24)
+/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output enable set register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TS    0xFFFFFFFFU
+#define GPIO_ENABLE_W1TS_M  (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S)
+#define GPIO_ENABLE_W1TS_V  0xFFFFFFFFU
+#define GPIO_ENABLE_W1TS_S  0
+
+/** GPIO_ENABLE_W1TC_REG register
+ *  GPIO output enable clear register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28)
+/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output enable clear register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TC    0xFFFFFFFFU
+#define GPIO_ENABLE_W1TC_M  (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S)
+#define GPIO_ENABLE_W1TC_V  0xFFFFFFFFU
+#define GPIO_ENABLE_W1TC_S  0
+
+/** GPIO_ENABLE1_REG register
+ *  GPIO output enable register for GPIO32-56
+ */
+#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2c)
+/** GPIO_ENABLE1_DATA : R/W/WTC; bitpos: [24:0]; default: 0;
+ *  GPIO output enable register for GPIO32-56
+ */
+#define GPIO_ENABLE1_DATA    0x01FFFFFFU
+#define GPIO_ENABLE1_DATA_M  (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S)
+#define GPIO_ENABLE1_DATA_V  0x01FFFFFFU
+#define GPIO_ENABLE1_DATA_S  0
+
+/** GPIO_ENABLE1_W1TS_REG register
+ *  GPIO output enable set register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30)
+/** GPIO_ENABLE1_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output enable set register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TS    0x01FFFFFFU
+#define GPIO_ENABLE1_W1TS_M  (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S)
+#define GPIO_ENABLE1_W1TS_V  0x01FFFFFFU
+#define GPIO_ENABLE1_W1TS_S  0
+
+/** GPIO_ENABLE1_W1TC_REG register
+ *  GPIO output enable clear register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34)
+/** GPIO_ENABLE1_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output enable clear register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TC    0x01FFFFFFU
+#define GPIO_ENABLE1_W1TC_M  (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S)
+#define GPIO_ENABLE1_W1TC_V  0x01FFFFFFU
+#define GPIO_ENABLE1_W1TC_S  0
+
+/** GPIO_STRAP_REG register
+ *  pad strapping register
+ */
+#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38)
+/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
+ *  pad strapping register
+ */
+#define GPIO_STRAPPING    0x0000FFFFU
+#define GPIO_STRAPPING_M  (GPIO_STRAPPING_V << GPIO_STRAPPING_S)
+#define GPIO_STRAPPING_V  0x0000FFFFU
+#define GPIO_STRAPPING_S  0
+
+/** GPIO_IN_REG register
+ *  GPIO input register for GPIO0-31
+ */
+#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c)
+/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0;
+ *  GPIO input register for GPIO0-31
+ */
+#define GPIO_IN_DATA_NEXT    0xFFFFFFFFU
+#define GPIO_IN_DATA_NEXT_M  (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S)
+#define GPIO_IN_DATA_NEXT_V  0xFFFFFFFFU
+#define GPIO_IN_DATA_NEXT_S  0
+
+/** GPIO_IN1_REG register
+ *  GPIO input register for GPIO32-56
+ */
+#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40)
+/** GPIO_IN1_DATA_NEXT : RO; bitpos: [24:0]; default: 0;
+ *  GPIO input register for GPIO32-56
+ */
+#define GPIO_IN1_DATA_NEXT    0x01FFFFFFU
+#define GPIO_IN1_DATA_NEXT_M  (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S)
+#define GPIO_IN1_DATA_NEXT_V  0x01FFFFFFU
+#define GPIO_IN1_DATA_NEXT_S  0
+
+/** GPIO_STATUS_REG register
+ *  GPIO interrupt status register for GPIO0-31
+ */
+#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44)
+/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt status register for GPIO0-31
+ */
+#define GPIO_STATUS_INTERRUPT    0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_M  (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S)
+#define GPIO_STATUS_INTERRUPT_V  0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_S  0
+
+/** GPIO_STATUS_W1TS_REG register
+ *  GPIO interrupt status set register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48)
+/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt status set register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TS    0xFFFFFFFFU
+#define GPIO_STATUS_W1TS_M  (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S)
+#define GPIO_STATUS_W1TS_V  0xFFFFFFFFU
+#define GPIO_STATUS_W1TS_S  0
+
+/** GPIO_STATUS_W1TC_REG register
+ *  GPIO interrupt status clear register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c)
+/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt status clear register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TC    0xFFFFFFFFU
+#define GPIO_STATUS_W1TC_M  (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S)
+#define GPIO_STATUS_W1TC_V  0xFFFFFFFFU
+#define GPIO_STATUS_W1TC_S  0
+
+/** GPIO_STATUS1_REG register
+ *  GPIO interrupt status register for GPIO32-56
+ */
+#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50)
+/** GPIO_STATUS1_INTERRUPT : R/W/WTC; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status register for GPIO32-56
+ */
+#define GPIO_STATUS1_INTERRUPT    0x01FFFFFFU
+#define GPIO_STATUS1_INTERRUPT_M  (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S)
+#define GPIO_STATUS1_INTERRUPT_V  0x01FFFFFFU
+#define GPIO_STATUS1_INTERRUPT_S  0
+
+/** GPIO_STATUS1_W1TS_REG register
+ *  GPIO interrupt status set register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54)
+/** GPIO_STATUS1_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status set register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TS    0x01FFFFFFU
+#define GPIO_STATUS1_W1TS_M  (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S)
+#define GPIO_STATUS1_W1TS_V  0x01FFFFFFU
+#define GPIO_STATUS1_W1TS_S  0
+
+/** GPIO_STATUS1_W1TC_REG register
+ *  GPIO interrupt status clear register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58)
+/** GPIO_STATUS1_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status clear register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TC    0x01FFFFFFU
+#define GPIO_STATUS1_W1TC_M  (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S)
+#define GPIO_STATUS1_W1TC_V  0x01FFFFFFU
+#define GPIO_STATUS1_W1TC_S  0
+
+/** GPIO_INTR_0_REG register
+ *  GPIO interrupt 0 status register for GPIO0-31
+ */
+#define GPIO_INTR_0_REG (DR_REG_GPIO_BASE + 0x5c)
+/** GPIO_INT_0 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 0 status register for GPIO0-31
+ */
+#define GPIO_INT_0    0xFFFFFFFFU
+#define GPIO_INT_0_M  (GPIO_INT_0_V << GPIO_INT_0_S)
+#define GPIO_INT_0_V  0xFFFFFFFFU
+#define GPIO_INT_0_S  0
+
+/** GPIO_INTR1_0_REG register
+ *  GPIO interrupt 0 status register for GPIO32-56
+ */
+#define GPIO_INTR1_0_REG (DR_REG_GPIO_BASE + 0x60)
+/** GPIO_INT1_0 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 0 status register for GPIO32-56
+ */
+#define GPIO_INT1_0    0x01FFFFFFU
+#define GPIO_INT1_0_M  (GPIO_INT1_0_V << GPIO_INT1_0_S)
+#define GPIO_INT1_0_V  0x01FFFFFFU
+#define GPIO_INT1_0_S  0
+
+/** GPIO_INTR_1_REG register
+ *  GPIO interrupt 1 status register for GPIO0-31
+ */
+#define GPIO_INTR_1_REG (DR_REG_GPIO_BASE + 0x64)
+/** GPIO_INT_1 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 1 status register for GPIO0-31
+ */
+#define GPIO_INT_1    0xFFFFFFFFU
+#define GPIO_INT_1_M  (GPIO_INT_1_V << GPIO_INT_1_S)
+#define GPIO_INT_1_V  0xFFFFFFFFU
+#define GPIO_INT_1_S  0
+
+/** GPIO_INTR1_1_REG register
+ *  GPIO interrupt 1 status register for GPIO32-56
+ */
+#define GPIO_INTR1_1_REG (DR_REG_GPIO_BASE + 0x68)
+/** GPIO_INT1_1 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 1 status register for GPIO32-56
+ */
+#define GPIO_INT1_1    0x01FFFFFFU
+#define GPIO_INT1_1_M  (GPIO_INT1_1_V << GPIO_INT1_1_S)
+#define GPIO_INT1_1_V  0x01FFFFFFU
+#define GPIO_INT1_1_S  0
+
+/** GPIO_STATUS_NEXT_REG register
+ *  GPIO interrupt source register for GPIO0-31
+ */
+#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x6c)
+/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt source register for GPIO0-31
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT    0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_M  (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S)
+#define GPIO_STATUS_INTERRUPT_NEXT_V  0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+/** GPIO_STATUS_NEXT1_REG register
+ *  GPIO interrupt source register for GPIO32-56
+ */
+#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x70)
+/** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt source register for GPIO32-56
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT1    0x01FFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT1_M  (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S)
+#define GPIO_STATUS_INTERRUPT_NEXT1_V  0x01FFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT1_S  0
+
+/** GPIO_PIN0_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74)
+/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN0_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_M  (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S)
+#define GPIO_PIN0_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_S  0
+/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M  (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S)
+#define GPIO_PIN0_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN0_PAD_DRIVER_S  2
+/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN0_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_M  (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S)
+#define GPIO_PIN0_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_S  3
+/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN0_INT_TYPE    0x00000007U
+#define GPIO_PIN0_INT_TYPE_M  (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S)
+#define GPIO_PIN0_INT_TYPE_V  0x00000007U
+#define GPIO_PIN0_INT_TYPE_S  7
+/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M  (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S)
+#define GPIO_PIN0_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN0_WAKEUP_ENABLE_S  10
+/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN0_CONFIG    0x00000003U
+#define GPIO_PIN0_CONFIG_M  (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S)
+#define GPIO_PIN0_CONFIG_V  0x00000003U
+#define GPIO_PIN0_CONFIG_S  11
+/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN0_INT_ENA    0x0000001FU
+#define GPIO_PIN0_INT_ENA_M  (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S)
+#define GPIO_PIN0_INT_ENA_V  0x0000001FU
+#define GPIO_PIN0_INT_ENA_S  13
+
+/** GPIO_PIN1_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78)
+/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN1_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_M  (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S)
+#define GPIO_PIN1_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_S  0
+/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M  (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S)
+#define GPIO_PIN1_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN1_PAD_DRIVER_S  2
+/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN1_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_M  (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S)
+#define GPIO_PIN1_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_S  3
+/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN1_INT_TYPE    0x00000007U
+#define GPIO_PIN1_INT_TYPE_M  (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S)
+#define GPIO_PIN1_INT_TYPE_V  0x00000007U
+#define GPIO_PIN1_INT_TYPE_S  7
+/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M  (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S)
+#define GPIO_PIN1_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN1_WAKEUP_ENABLE_S  10
+/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN1_CONFIG    0x00000003U
+#define GPIO_PIN1_CONFIG_M  (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S)
+#define GPIO_PIN1_CONFIG_V  0x00000003U
+#define GPIO_PIN1_CONFIG_S  11
+/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN1_INT_ENA    0x0000001FU
+#define GPIO_PIN1_INT_ENA_M  (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S)
+#define GPIO_PIN1_INT_ENA_V  0x0000001FU
+#define GPIO_PIN1_INT_ENA_S  13
+
+/** GPIO_PIN2_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c)
+/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN2_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_M  (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S)
+#define GPIO_PIN2_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_S  0
+/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M  (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S)
+#define GPIO_PIN2_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN2_PAD_DRIVER_S  2
+/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN2_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_M  (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S)
+#define GPIO_PIN2_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_S  3
+/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN2_INT_TYPE    0x00000007U
+#define GPIO_PIN2_INT_TYPE_M  (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S)
+#define GPIO_PIN2_INT_TYPE_V  0x00000007U
+#define GPIO_PIN2_INT_TYPE_S  7
+/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M  (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S)
+#define GPIO_PIN2_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN2_WAKEUP_ENABLE_S  10
+/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN2_CONFIG    0x00000003U
+#define GPIO_PIN2_CONFIG_M  (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S)
+#define GPIO_PIN2_CONFIG_V  0x00000003U
+#define GPIO_PIN2_CONFIG_S  11
+/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN2_INT_ENA    0x0000001FU
+#define GPIO_PIN2_INT_ENA_M  (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S)
+#define GPIO_PIN2_INT_ENA_V  0x0000001FU
+#define GPIO_PIN2_INT_ENA_S  13
+
+/** GPIO_PIN3_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80)
+/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN3_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_M  (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S)
+#define GPIO_PIN3_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_S  0
+/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M  (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S)
+#define GPIO_PIN3_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN3_PAD_DRIVER_S  2
+/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN3_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_M  (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S)
+#define GPIO_PIN3_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_S  3
+/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN3_INT_TYPE    0x00000007U
+#define GPIO_PIN3_INT_TYPE_M  (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S)
+#define GPIO_PIN3_INT_TYPE_V  0x00000007U
+#define GPIO_PIN3_INT_TYPE_S  7
+/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M  (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S)
+#define GPIO_PIN3_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN3_WAKEUP_ENABLE_S  10
+/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN3_CONFIG    0x00000003U
+#define GPIO_PIN3_CONFIG_M  (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S)
+#define GPIO_PIN3_CONFIG_V  0x00000003U
+#define GPIO_PIN3_CONFIG_S  11
+/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN3_INT_ENA    0x0000001FU
+#define GPIO_PIN3_INT_ENA_M  (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S)
+#define GPIO_PIN3_INT_ENA_V  0x0000001FU
+#define GPIO_PIN3_INT_ENA_S  13
+
+/** GPIO_PIN4_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84)
+/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN4_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_M  (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S)
+#define GPIO_PIN4_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_S  0
+/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M  (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S)
+#define GPIO_PIN4_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN4_PAD_DRIVER_S  2
+/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN4_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_M  (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S)
+#define GPIO_PIN4_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_S  3
+/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN4_INT_TYPE    0x00000007U
+#define GPIO_PIN4_INT_TYPE_M  (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S)
+#define GPIO_PIN4_INT_TYPE_V  0x00000007U
+#define GPIO_PIN4_INT_TYPE_S  7
+/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M  (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S)
+#define GPIO_PIN4_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN4_WAKEUP_ENABLE_S  10
+/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN4_CONFIG    0x00000003U
+#define GPIO_PIN4_CONFIG_M  (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S)
+#define GPIO_PIN4_CONFIG_V  0x00000003U
+#define GPIO_PIN4_CONFIG_S  11
+/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN4_INT_ENA    0x0000001FU
+#define GPIO_PIN4_INT_ENA_M  (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S)
+#define GPIO_PIN4_INT_ENA_V  0x0000001FU
+#define GPIO_PIN4_INT_ENA_S  13
+
+/** GPIO_PIN5_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88)
+/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN5_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_M  (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S)
+#define GPIO_PIN5_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_S  0
+/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M  (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S)
+#define GPIO_PIN5_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN5_PAD_DRIVER_S  2
+/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN5_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_M  (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S)
+#define GPIO_PIN5_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_S  3
+/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN5_INT_TYPE    0x00000007U
+#define GPIO_PIN5_INT_TYPE_M  (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S)
+#define GPIO_PIN5_INT_TYPE_V  0x00000007U
+#define GPIO_PIN5_INT_TYPE_S  7
+/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M  (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S)
+#define GPIO_PIN5_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN5_WAKEUP_ENABLE_S  10
+/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN5_CONFIG    0x00000003U
+#define GPIO_PIN5_CONFIG_M  (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S)
+#define GPIO_PIN5_CONFIG_V  0x00000003U
+#define GPIO_PIN5_CONFIG_S  11
+/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN5_INT_ENA    0x0000001FU
+#define GPIO_PIN5_INT_ENA_M  (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S)
+#define GPIO_PIN5_INT_ENA_V  0x0000001FU
+#define GPIO_PIN5_INT_ENA_S  13
+
+/** GPIO_PIN6_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c)
+/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN6_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_M  (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S)
+#define GPIO_PIN6_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_S  0
+/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M  (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S)
+#define GPIO_PIN6_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN6_PAD_DRIVER_S  2
+/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN6_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_M  (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S)
+#define GPIO_PIN6_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_S  3
+/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN6_INT_TYPE    0x00000007U
+#define GPIO_PIN6_INT_TYPE_M  (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S)
+#define GPIO_PIN6_INT_TYPE_V  0x00000007U
+#define GPIO_PIN6_INT_TYPE_S  7
+/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M  (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S)
+#define GPIO_PIN6_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN6_WAKEUP_ENABLE_S  10
+/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN6_CONFIG    0x00000003U
+#define GPIO_PIN6_CONFIG_M  (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S)
+#define GPIO_PIN6_CONFIG_V  0x00000003U
+#define GPIO_PIN6_CONFIG_S  11
+/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN6_INT_ENA    0x0000001FU
+#define GPIO_PIN6_INT_ENA_M  (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S)
+#define GPIO_PIN6_INT_ENA_V  0x0000001FU
+#define GPIO_PIN6_INT_ENA_S  13
+
+/** GPIO_PIN7_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90)
+/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN7_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_M  (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S)
+#define GPIO_PIN7_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_S  0
+/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M  (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S)
+#define GPIO_PIN7_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN7_PAD_DRIVER_S  2
+/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN7_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_M  (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S)
+#define GPIO_PIN7_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_S  3
+/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN7_INT_TYPE    0x00000007U
+#define GPIO_PIN7_INT_TYPE_M  (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S)
+#define GPIO_PIN7_INT_TYPE_V  0x00000007U
+#define GPIO_PIN7_INT_TYPE_S  7
+/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M  (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S)
+#define GPIO_PIN7_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN7_WAKEUP_ENABLE_S  10
+/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN7_CONFIG    0x00000003U
+#define GPIO_PIN7_CONFIG_M  (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S)
+#define GPIO_PIN7_CONFIG_V  0x00000003U
+#define GPIO_PIN7_CONFIG_S  11
+/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN7_INT_ENA    0x0000001FU
+#define GPIO_PIN7_INT_ENA_M  (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S)
+#define GPIO_PIN7_INT_ENA_V  0x0000001FU
+#define GPIO_PIN7_INT_ENA_S  13
+
+/** GPIO_PIN8_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94)
+/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN8_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_M  (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S)
+#define GPIO_PIN8_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_S  0
+/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M  (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S)
+#define GPIO_PIN8_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN8_PAD_DRIVER_S  2
+/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN8_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_M  (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S)
+#define GPIO_PIN8_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_S  3
+/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN8_INT_TYPE    0x00000007U
+#define GPIO_PIN8_INT_TYPE_M  (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S)
+#define GPIO_PIN8_INT_TYPE_V  0x00000007U
+#define GPIO_PIN8_INT_TYPE_S  7
+/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M  (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S)
+#define GPIO_PIN8_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN8_WAKEUP_ENABLE_S  10
+/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN8_CONFIG    0x00000003U
+#define GPIO_PIN8_CONFIG_M  (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S)
+#define GPIO_PIN8_CONFIG_V  0x00000003U
+#define GPIO_PIN8_CONFIG_S  11
+/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN8_INT_ENA    0x0000001FU
+#define GPIO_PIN8_INT_ENA_M  (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S)
+#define GPIO_PIN8_INT_ENA_V  0x0000001FU
+#define GPIO_PIN8_INT_ENA_S  13
+
+/** GPIO_PIN9_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98)
+/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN9_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_M  (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S)
+#define GPIO_PIN9_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_S  0
+/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M  (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S)
+#define GPIO_PIN9_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN9_PAD_DRIVER_S  2
+/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN9_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_M  (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S)
+#define GPIO_PIN9_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_S  3
+/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN9_INT_TYPE    0x00000007U
+#define GPIO_PIN9_INT_TYPE_M  (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S)
+#define GPIO_PIN9_INT_TYPE_V  0x00000007U
+#define GPIO_PIN9_INT_TYPE_S  7
+/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M  (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S)
+#define GPIO_PIN9_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN9_WAKEUP_ENABLE_S  10
+/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN9_CONFIG    0x00000003U
+#define GPIO_PIN9_CONFIG_M  (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S)
+#define GPIO_PIN9_CONFIG_V  0x00000003U
+#define GPIO_PIN9_CONFIG_S  11
+/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN9_INT_ENA    0x0000001FU
+#define GPIO_PIN9_INT_ENA_M  (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S)
+#define GPIO_PIN9_INT_ENA_V  0x0000001FU
+#define GPIO_PIN9_INT_ENA_S  13
+
+/** GPIO_PIN10_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c)
+/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN10_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_M  (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S)
+#define GPIO_PIN10_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_S  0
+/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M  (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S)
+#define GPIO_PIN10_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN10_PAD_DRIVER_S  2
+/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN10_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_M  (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S)
+#define GPIO_PIN10_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_S  3
+/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN10_INT_TYPE    0x00000007U
+#define GPIO_PIN10_INT_TYPE_M  (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S)
+#define GPIO_PIN10_INT_TYPE_V  0x00000007U
+#define GPIO_PIN10_INT_TYPE_S  7
+/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M  (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S)
+#define GPIO_PIN10_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN10_WAKEUP_ENABLE_S  10
+/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN10_CONFIG    0x00000003U
+#define GPIO_PIN10_CONFIG_M  (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S)
+#define GPIO_PIN10_CONFIG_V  0x00000003U
+#define GPIO_PIN10_CONFIG_S  11
+/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN10_INT_ENA    0x0000001FU
+#define GPIO_PIN10_INT_ENA_M  (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S)
+#define GPIO_PIN10_INT_ENA_V  0x0000001FU
+#define GPIO_PIN10_INT_ENA_S  13
+
+/** GPIO_PIN11_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0)
+/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN11_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_M  (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S)
+#define GPIO_PIN11_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_S  0
+/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M  (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S)
+#define GPIO_PIN11_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN11_PAD_DRIVER_S  2
+/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN11_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_M  (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S)
+#define GPIO_PIN11_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_S  3
+/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN11_INT_TYPE    0x00000007U
+#define GPIO_PIN11_INT_TYPE_M  (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S)
+#define GPIO_PIN11_INT_TYPE_V  0x00000007U
+#define GPIO_PIN11_INT_TYPE_S  7
+/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M  (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S)
+#define GPIO_PIN11_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN11_WAKEUP_ENABLE_S  10
+/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN11_CONFIG    0x00000003U
+#define GPIO_PIN11_CONFIG_M  (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S)
+#define GPIO_PIN11_CONFIG_V  0x00000003U
+#define GPIO_PIN11_CONFIG_S  11
+/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN11_INT_ENA    0x0000001FU
+#define GPIO_PIN11_INT_ENA_M  (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S)
+#define GPIO_PIN11_INT_ENA_V  0x0000001FU
+#define GPIO_PIN11_INT_ENA_S  13
+
+/** GPIO_PIN12_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4)
+/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN12_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_M  (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S)
+#define GPIO_PIN12_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_S  0
+/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M  (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S)
+#define GPIO_PIN12_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN12_PAD_DRIVER_S  2
+/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN12_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_M  (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S)
+#define GPIO_PIN12_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_S  3
+/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN12_INT_TYPE    0x00000007U
+#define GPIO_PIN12_INT_TYPE_M  (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S)
+#define GPIO_PIN12_INT_TYPE_V  0x00000007U
+#define GPIO_PIN12_INT_TYPE_S  7
+/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M  (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S)
+#define GPIO_PIN12_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN12_WAKEUP_ENABLE_S  10
+/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN12_CONFIG    0x00000003U
+#define GPIO_PIN12_CONFIG_M  (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S)
+#define GPIO_PIN12_CONFIG_V  0x00000003U
+#define GPIO_PIN12_CONFIG_S  11
+/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN12_INT_ENA    0x0000001FU
+#define GPIO_PIN12_INT_ENA_M  (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S)
+#define GPIO_PIN12_INT_ENA_V  0x0000001FU
+#define GPIO_PIN12_INT_ENA_S  13
+
+/** GPIO_PIN13_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8)
+/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN13_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_M  (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S)
+#define GPIO_PIN13_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_S  0
+/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M  (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S)
+#define GPIO_PIN13_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN13_PAD_DRIVER_S  2
+/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN13_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_M  (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S)
+#define GPIO_PIN13_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_S  3
+/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN13_INT_TYPE    0x00000007U
+#define GPIO_PIN13_INT_TYPE_M  (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S)
+#define GPIO_PIN13_INT_TYPE_V  0x00000007U
+#define GPIO_PIN13_INT_TYPE_S  7
+/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M  (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S)
+#define GPIO_PIN13_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN13_WAKEUP_ENABLE_S  10
+/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN13_CONFIG    0x00000003U
+#define GPIO_PIN13_CONFIG_M  (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S)
+#define GPIO_PIN13_CONFIG_V  0x00000003U
+#define GPIO_PIN13_CONFIG_S  11
+/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN13_INT_ENA    0x0000001FU
+#define GPIO_PIN13_INT_ENA_M  (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S)
+#define GPIO_PIN13_INT_ENA_V  0x0000001FU
+#define GPIO_PIN13_INT_ENA_S  13
+
+/** GPIO_PIN14_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac)
+/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN14_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_M  (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S)
+#define GPIO_PIN14_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_S  0
+/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M  (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S)
+#define GPIO_PIN14_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN14_PAD_DRIVER_S  2
+/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN14_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_M  (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S)
+#define GPIO_PIN14_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_S  3
+/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN14_INT_TYPE    0x00000007U
+#define GPIO_PIN14_INT_TYPE_M  (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S)
+#define GPIO_PIN14_INT_TYPE_V  0x00000007U
+#define GPIO_PIN14_INT_TYPE_S  7
+/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M  (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S)
+#define GPIO_PIN14_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN14_WAKEUP_ENABLE_S  10
+/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN14_CONFIG    0x00000003U
+#define GPIO_PIN14_CONFIG_M  (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S)
+#define GPIO_PIN14_CONFIG_V  0x00000003U
+#define GPIO_PIN14_CONFIG_S  11
+/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN14_INT_ENA    0x0000001FU
+#define GPIO_PIN14_INT_ENA_M  (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S)
+#define GPIO_PIN14_INT_ENA_V  0x0000001FU
+#define GPIO_PIN14_INT_ENA_S  13
+
+/** GPIO_PIN15_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0)
+/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN15_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_M  (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S)
+#define GPIO_PIN15_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_S  0
+/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M  (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S)
+#define GPIO_PIN15_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN15_PAD_DRIVER_S  2
+/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN15_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_M  (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S)
+#define GPIO_PIN15_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_S  3
+/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN15_INT_TYPE    0x00000007U
+#define GPIO_PIN15_INT_TYPE_M  (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S)
+#define GPIO_PIN15_INT_TYPE_V  0x00000007U
+#define GPIO_PIN15_INT_TYPE_S  7
+/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M  (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S)
+#define GPIO_PIN15_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN15_WAKEUP_ENABLE_S  10
+/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN15_CONFIG    0x00000003U
+#define GPIO_PIN15_CONFIG_M  (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S)
+#define GPIO_PIN15_CONFIG_V  0x00000003U
+#define GPIO_PIN15_CONFIG_S  11
+/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN15_INT_ENA    0x0000001FU
+#define GPIO_PIN15_INT_ENA_M  (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S)
+#define GPIO_PIN15_INT_ENA_V  0x0000001FU
+#define GPIO_PIN15_INT_ENA_S  13
+
+/** GPIO_PIN16_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4)
+/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN16_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_M  (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S)
+#define GPIO_PIN16_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_S  0
+/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M  (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S)
+#define GPIO_PIN16_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN16_PAD_DRIVER_S  2
+/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN16_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_M  (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S)
+#define GPIO_PIN16_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_S  3
+/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN16_INT_TYPE    0x00000007U
+#define GPIO_PIN16_INT_TYPE_M  (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S)
+#define GPIO_PIN16_INT_TYPE_V  0x00000007U
+#define GPIO_PIN16_INT_TYPE_S  7
+/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M  (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S)
+#define GPIO_PIN16_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN16_WAKEUP_ENABLE_S  10
+/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN16_CONFIG    0x00000003U
+#define GPIO_PIN16_CONFIG_M  (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S)
+#define GPIO_PIN16_CONFIG_V  0x00000003U
+#define GPIO_PIN16_CONFIG_S  11
+/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN16_INT_ENA    0x0000001FU
+#define GPIO_PIN16_INT_ENA_M  (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S)
+#define GPIO_PIN16_INT_ENA_V  0x0000001FU
+#define GPIO_PIN16_INT_ENA_S  13
+
+/** GPIO_PIN17_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8)
+/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN17_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_M  (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S)
+#define GPIO_PIN17_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_S  0
+/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M  (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S)
+#define GPIO_PIN17_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN17_PAD_DRIVER_S  2
+/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN17_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_M  (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S)
+#define GPIO_PIN17_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_S  3
+/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN17_INT_TYPE    0x00000007U
+#define GPIO_PIN17_INT_TYPE_M  (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S)
+#define GPIO_PIN17_INT_TYPE_V  0x00000007U
+#define GPIO_PIN17_INT_TYPE_S  7
+/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M  (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S)
+#define GPIO_PIN17_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN17_WAKEUP_ENABLE_S  10
+/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN17_CONFIG    0x00000003U
+#define GPIO_PIN17_CONFIG_M  (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S)
+#define GPIO_PIN17_CONFIG_V  0x00000003U
+#define GPIO_PIN17_CONFIG_S  11
+/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN17_INT_ENA    0x0000001FU
+#define GPIO_PIN17_INT_ENA_M  (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S)
+#define GPIO_PIN17_INT_ENA_V  0x0000001FU
+#define GPIO_PIN17_INT_ENA_S  13
+
+/** GPIO_PIN18_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc)
+/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN18_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_M  (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S)
+#define GPIO_PIN18_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_S  0
+/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M  (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S)
+#define GPIO_PIN18_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN18_PAD_DRIVER_S  2
+/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN18_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_M  (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S)
+#define GPIO_PIN18_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_S  3
+/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN18_INT_TYPE    0x00000007U
+#define GPIO_PIN18_INT_TYPE_M  (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S)
+#define GPIO_PIN18_INT_TYPE_V  0x00000007U
+#define GPIO_PIN18_INT_TYPE_S  7
+/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M  (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S)
+#define GPIO_PIN18_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN18_WAKEUP_ENABLE_S  10
+/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN18_CONFIG    0x00000003U
+#define GPIO_PIN18_CONFIG_M  (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S)
+#define GPIO_PIN18_CONFIG_V  0x00000003U
+#define GPIO_PIN18_CONFIG_S  11
+/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN18_INT_ENA    0x0000001FU
+#define GPIO_PIN18_INT_ENA_M  (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S)
+#define GPIO_PIN18_INT_ENA_V  0x0000001FU
+#define GPIO_PIN18_INT_ENA_S  13
+
+/** GPIO_PIN19_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0)
+/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN19_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_M  (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S)
+#define GPIO_PIN19_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_S  0
+/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M  (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S)
+#define GPIO_PIN19_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN19_PAD_DRIVER_S  2
+/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN19_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_M  (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S)
+#define GPIO_PIN19_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_S  3
+/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN19_INT_TYPE    0x00000007U
+#define GPIO_PIN19_INT_TYPE_M  (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S)
+#define GPIO_PIN19_INT_TYPE_V  0x00000007U
+#define GPIO_PIN19_INT_TYPE_S  7
+/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M  (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S)
+#define GPIO_PIN19_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN19_WAKEUP_ENABLE_S  10
+/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN19_CONFIG    0x00000003U
+#define GPIO_PIN19_CONFIG_M  (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S)
+#define GPIO_PIN19_CONFIG_V  0x00000003U
+#define GPIO_PIN19_CONFIG_S  11
+/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN19_INT_ENA    0x0000001FU
+#define GPIO_PIN19_INT_ENA_M  (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S)
+#define GPIO_PIN19_INT_ENA_V  0x0000001FU
+#define GPIO_PIN19_INT_ENA_S  13
+
+/** GPIO_PIN20_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4)
+/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN20_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_M  (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S)
+#define GPIO_PIN20_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_S  0
+/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M  (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S)
+#define GPIO_PIN20_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN20_PAD_DRIVER_S  2
+/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN20_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_M  (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S)
+#define GPIO_PIN20_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_S  3
+/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN20_INT_TYPE    0x00000007U
+#define GPIO_PIN20_INT_TYPE_M  (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S)
+#define GPIO_PIN20_INT_TYPE_V  0x00000007U
+#define GPIO_PIN20_INT_TYPE_S  7
+/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M  (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S)
+#define GPIO_PIN20_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN20_WAKEUP_ENABLE_S  10
+/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN20_CONFIG    0x00000003U
+#define GPIO_PIN20_CONFIG_M  (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S)
+#define GPIO_PIN20_CONFIG_V  0x00000003U
+#define GPIO_PIN20_CONFIG_S  11
+/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN20_INT_ENA    0x0000001FU
+#define GPIO_PIN20_INT_ENA_M  (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S)
+#define GPIO_PIN20_INT_ENA_V  0x0000001FU
+#define GPIO_PIN20_INT_ENA_S  13
+
+/** GPIO_PIN21_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8)
+/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN21_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_M  (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S)
+#define GPIO_PIN21_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_S  0
+/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M  (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S)
+#define GPIO_PIN21_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN21_PAD_DRIVER_S  2
+/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN21_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_M  (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S)
+#define GPIO_PIN21_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_S  3
+/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN21_INT_TYPE    0x00000007U
+#define GPIO_PIN21_INT_TYPE_M  (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S)
+#define GPIO_PIN21_INT_TYPE_V  0x00000007U
+#define GPIO_PIN21_INT_TYPE_S  7
+/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M  (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S)
+#define GPIO_PIN21_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN21_WAKEUP_ENABLE_S  10
+/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN21_CONFIG    0x00000003U
+#define GPIO_PIN21_CONFIG_M  (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S)
+#define GPIO_PIN21_CONFIG_V  0x00000003U
+#define GPIO_PIN21_CONFIG_S  11
+/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN21_INT_ENA    0x0000001FU
+#define GPIO_PIN21_INT_ENA_M  (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S)
+#define GPIO_PIN21_INT_ENA_V  0x0000001FU
+#define GPIO_PIN21_INT_ENA_S  13
+
+/** GPIO_PIN22_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc)
+/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN22_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_M  (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
+#define GPIO_PIN22_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_S  0
+/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN22_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M  (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
+#define GPIO_PIN22_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN22_PAD_DRIVER_S  2
+/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN22_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_M  (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
+#define GPIO_PIN22_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_S  3
+/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN22_INT_TYPE    0x00000007U
+#define GPIO_PIN22_INT_TYPE_M  (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
+#define GPIO_PIN22_INT_TYPE_V  0x00000007U
+#define GPIO_PIN22_INT_TYPE_S  7
+/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN22_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M  (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
+#define GPIO_PIN22_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN22_WAKEUP_ENABLE_S  10
+/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN22_CONFIG    0x00000003U
+#define GPIO_PIN22_CONFIG_M  (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S)
+#define GPIO_PIN22_CONFIG_V  0x00000003U
+#define GPIO_PIN22_CONFIG_S  11
+/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN22_INT_ENA    0x0000001FU
+#define GPIO_PIN22_INT_ENA_M  (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
+#define GPIO_PIN22_INT_ENA_V  0x0000001FU
+#define GPIO_PIN22_INT_ENA_S  13
+
+/** GPIO_PIN23_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0)
+/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN23_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_M  (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
+#define GPIO_PIN23_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_S  0
+/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN23_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M  (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
+#define GPIO_PIN23_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN23_PAD_DRIVER_S  2
+/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN23_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_M  (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
+#define GPIO_PIN23_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_S  3
+/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN23_INT_TYPE    0x00000007U
+#define GPIO_PIN23_INT_TYPE_M  (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
+#define GPIO_PIN23_INT_TYPE_V  0x00000007U
+#define GPIO_PIN23_INT_TYPE_S  7
+/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN23_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M  (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
+#define GPIO_PIN23_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN23_WAKEUP_ENABLE_S  10
+/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN23_CONFIG    0x00000003U
+#define GPIO_PIN23_CONFIG_M  (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S)
+#define GPIO_PIN23_CONFIG_V  0x00000003U
+#define GPIO_PIN23_CONFIG_S  11
+/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN23_INT_ENA    0x0000001FU
+#define GPIO_PIN23_INT_ENA_M  (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
+#define GPIO_PIN23_INT_ENA_V  0x0000001FU
+#define GPIO_PIN23_INT_ENA_S  13
+
+/** GPIO_PIN24_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4)
+/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN24_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_M  (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
+#define GPIO_PIN24_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_S  0
+/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN24_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M  (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
+#define GPIO_PIN24_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN24_PAD_DRIVER_S  2
+/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN24_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_M  (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
+#define GPIO_PIN24_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_S  3
+/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN24_INT_TYPE    0x00000007U
+#define GPIO_PIN24_INT_TYPE_M  (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
+#define GPIO_PIN24_INT_TYPE_V  0x00000007U
+#define GPIO_PIN24_INT_TYPE_S  7
+/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN24_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M  (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
+#define GPIO_PIN24_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN24_WAKEUP_ENABLE_S  10
+/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN24_CONFIG    0x00000003U
+#define GPIO_PIN24_CONFIG_M  (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S)
+#define GPIO_PIN24_CONFIG_V  0x00000003U
+#define GPIO_PIN24_CONFIG_S  11
+/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN24_INT_ENA    0x0000001FU
+#define GPIO_PIN24_INT_ENA_M  (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
+#define GPIO_PIN24_INT_ENA_V  0x0000001FU
+#define GPIO_PIN24_INT_ENA_S  13
+
+/** GPIO_PIN25_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8)
+/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN25_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN25_SYNC2_BYPASS_M  (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S)
+#define GPIO_PIN25_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN25_SYNC2_BYPASS_S  0
+/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN25_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_M  (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S)
+#define GPIO_PIN25_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN25_PAD_DRIVER_S  2
+/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN25_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN25_SYNC1_BYPASS_M  (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S)
+#define GPIO_PIN25_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN25_SYNC1_BYPASS_S  3
+/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN25_INT_TYPE    0x00000007U
+#define GPIO_PIN25_INT_TYPE_M  (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S)
+#define GPIO_PIN25_INT_TYPE_V  0x00000007U
+#define GPIO_PIN25_INT_TYPE_S  7
+/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN25_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_M  (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S)
+#define GPIO_PIN25_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN25_WAKEUP_ENABLE_S  10
+/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN25_CONFIG    0x00000003U
+#define GPIO_PIN25_CONFIG_M  (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S)
+#define GPIO_PIN25_CONFIG_V  0x00000003U
+#define GPIO_PIN25_CONFIG_S  11
+/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN25_INT_ENA    0x0000001FU
+#define GPIO_PIN25_INT_ENA_M  (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S)
+#define GPIO_PIN25_INT_ENA_V  0x0000001FU
+#define GPIO_PIN25_INT_ENA_S  13
+
+/** GPIO_PIN26_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc)
+/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN26_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN26_SYNC2_BYPASS_M  (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S)
+#define GPIO_PIN26_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN26_SYNC2_BYPASS_S  0
+/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN26_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN26_PAD_DRIVER_M  (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S)
+#define GPIO_PIN26_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN26_PAD_DRIVER_S  2
+/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN26_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN26_SYNC1_BYPASS_M  (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S)
+#define GPIO_PIN26_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN26_SYNC1_BYPASS_S  3
+/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN26_INT_TYPE    0x00000007U
+#define GPIO_PIN26_INT_TYPE_M  (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S)
+#define GPIO_PIN26_INT_TYPE_V  0x00000007U
+#define GPIO_PIN26_INT_TYPE_S  7
+/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN26_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN26_WAKEUP_ENABLE_M  (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S)
+#define GPIO_PIN26_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN26_WAKEUP_ENABLE_S  10
+/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN26_CONFIG    0x00000003U
+#define GPIO_PIN26_CONFIG_M  (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S)
+#define GPIO_PIN26_CONFIG_V  0x00000003U
+#define GPIO_PIN26_CONFIG_S  11
+/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN26_INT_ENA    0x0000001FU
+#define GPIO_PIN26_INT_ENA_M  (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S)
+#define GPIO_PIN26_INT_ENA_V  0x0000001FU
+#define GPIO_PIN26_INT_ENA_S  13
+
+/** GPIO_PIN27_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0)
+/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN27_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN27_SYNC2_BYPASS_M  (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S)
+#define GPIO_PIN27_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN27_SYNC2_BYPASS_S  0
+/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN27_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN27_PAD_DRIVER_M  (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S)
+#define GPIO_PIN27_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN27_PAD_DRIVER_S  2
+/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN27_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN27_SYNC1_BYPASS_M  (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S)
+#define GPIO_PIN27_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN27_SYNC1_BYPASS_S  3
+/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN27_INT_TYPE    0x00000007U
+#define GPIO_PIN27_INT_TYPE_M  (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S)
+#define GPIO_PIN27_INT_TYPE_V  0x00000007U
+#define GPIO_PIN27_INT_TYPE_S  7
+/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN27_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN27_WAKEUP_ENABLE_M  (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S)
+#define GPIO_PIN27_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN27_WAKEUP_ENABLE_S  10
+/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN27_CONFIG    0x00000003U
+#define GPIO_PIN27_CONFIG_M  (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S)
+#define GPIO_PIN27_CONFIG_V  0x00000003U
+#define GPIO_PIN27_CONFIG_S  11
+/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN27_INT_ENA    0x0000001FU
+#define GPIO_PIN27_INT_ENA_M  (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S)
+#define GPIO_PIN27_INT_ENA_V  0x0000001FU
+#define GPIO_PIN27_INT_ENA_S  13
+
+/** GPIO_PIN28_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4)
+/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN28_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN28_SYNC2_BYPASS_M  (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S)
+#define GPIO_PIN28_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN28_SYNC2_BYPASS_S  0
+/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN28_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN28_PAD_DRIVER_M  (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S)
+#define GPIO_PIN28_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN28_PAD_DRIVER_S  2
+/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN28_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN28_SYNC1_BYPASS_M  (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S)
+#define GPIO_PIN28_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN28_SYNC1_BYPASS_S  3
+/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN28_INT_TYPE    0x00000007U
+#define GPIO_PIN28_INT_TYPE_M  (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S)
+#define GPIO_PIN28_INT_TYPE_V  0x00000007U
+#define GPIO_PIN28_INT_TYPE_S  7
+/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN28_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN28_WAKEUP_ENABLE_M  (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S)
+#define GPIO_PIN28_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN28_WAKEUP_ENABLE_S  10
+/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN28_CONFIG    0x00000003U
+#define GPIO_PIN28_CONFIG_M  (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S)
+#define GPIO_PIN28_CONFIG_V  0x00000003U
+#define GPIO_PIN28_CONFIG_S  11
+/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN28_INT_ENA    0x0000001FU
+#define GPIO_PIN28_INT_ENA_M  (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S)
+#define GPIO_PIN28_INT_ENA_V  0x0000001FU
+#define GPIO_PIN28_INT_ENA_S  13
+
+/** GPIO_PIN29_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8)
+/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN29_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN29_SYNC2_BYPASS_M  (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S)
+#define GPIO_PIN29_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN29_SYNC2_BYPASS_S  0
+/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN29_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN29_PAD_DRIVER_M  (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S)
+#define GPIO_PIN29_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN29_PAD_DRIVER_S  2
+/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN29_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN29_SYNC1_BYPASS_M  (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S)
+#define GPIO_PIN29_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN29_SYNC1_BYPASS_S  3
+/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN29_INT_TYPE    0x00000007U
+#define GPIO_PIN29_INT_TYPE_M  (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S)
+#define GPIO_PIN29_INT_TYPE_V  0x00000007U
+#define GPIO_PIN29_INT_TYPE_S  7
+/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN29_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN29_WAKEUP_ENABLE_M  (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S)
+#define GPIO_PIN29_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN29_WAKEUP_ENABLE_S  10
+/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN29_CONFIG    0x00000003U
+#define GPIO_PIN29_CONFIG_M  (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S)
+#define GPIO_PIN29_CONFIG_V  0x00000003U
+#define GPIO_PIN29_CONFIG_S  11
+/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN29_INT_ENA    0x0000001FU
+#define GPIO_PIN29_INT_ENA_M  (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S)
+#define GPIO_PIN29_INT_ENA_V  0x0000001FU
+#define GPIO_PIN29_INT_ENA_S  13
+
+/** GPIO_PIN30_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec)
+/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN30_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN30_SYNC2_BYPASS_M  (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S)
+#define GPIO_PIN30_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN30_SYNC2_BYPASS_S  0
+/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN30_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN30_PAD_DRIVER_M  (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S)
+#define GPIO_PIN30_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN30_PAD_DRIVER_S  2
+/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN30_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN30_SYNC1_BYPASS_M  (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S)
+#define GPIO_PIN30_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN30_SYNC1_BYPASS_S  3
+/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN30_INT_TYPE    0x00000007U
+#define GPIO_PIN30_INT_TYPE_M  (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S)
+#define GPIO_PIN30_INT_TYPE_V  0x00000007U
+#define GPIO_PIN30_INT_TYPE_S  7
+/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN30_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN30_WAKEUP_ENABLE_M  (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S)
+#define GPIO_PIN30_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN30_WAKEUP_ENABLE_S  10
+/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN30_CONFIG    0x00000003U
+#define GPIO_PIN30_CONFIG_M  (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S)
+#define GPIO_PIN30_CONFIG_V  0x00000003U
+#define GPIO_PIN30_CONFIG_S  11
+/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN30_INT_ENA    0x0000001FU
+#define GPIO_PIN30_INT_ENA_M  (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S)
+#define GPIO_PIN30_INT_ENA_V  0x0000001FU
+#define GPIO_PIN30_INT_ENA_S  13
+
+/** GPIO_PIN31_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0)
+/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN31_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN31_SYNC2_BYPASS_M  (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S)
+#define GPIO_PIN31_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN31_SYNC2_BYPASS_S  0
+/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN31_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN31_PAD_DRIVER_M  (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S)
+#define GPIO_PIN31_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN31_PAD_DRIVER_S  2
+/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN31_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN31_SYNC1_BYPASS_M  (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S)
+#define GPIO_PIN31_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN31_SYNC1_BYPASS_S  3
+/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN31_INT_TYPE    0x00000007U
+#define GPIO_PIN31_INT_TYPE_M  (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S)
+#define GPIO_PIN31_INT_TYPE_V  0x00000007U
+#define GPIO_PIN31_INT_TYPE_S  7
+/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN31_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN31_WAKEUP_ENABLE_M  (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S)
+#define GPIO_PIN31_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN31_WAKEUP_ENABLE_S  10
+/** GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN31_CONFIG    0x00000003U
+#define GPIO_PIN31_CONFIG_M  (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S)
+#define GPIO_PIN31_CONFIG_V  0x00000003U
+#define GPIO_PIN31_CONFIG_S  11
+/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN31_INT_ENA    0x0000001FU
+#define GPIO_PIN31_INT_ENA_M  (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S)
+#define GPIO_PIN31_INT_ENA_V  0x0000001FU
+#define GPIO_PIN31_INT_ENA_S  13
+
+/** GPIO_PIN32_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xf4)
+/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN32_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN32_SYNC2_BYPASS_M  (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S)
+#define GPIO_PIN32_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN32_SYNC2_BYPASS_S  0
+/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN32_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN32_PAD_DRIVER_M  (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S)
+#define GPIO_PIN32_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN32_PAD_DRIVER_S  2
+/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN32_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN32_SYNC1_BYPASS_M  (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S)
+#define GPIO_PIN32_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN32_SYNC1_BYPASS_S  3
+/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN32_INT_TYPE    0x00000007U
+#define GPIO_PIN32_INT_TYPE_M  (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S)
+#define GPIO_PIN32_INT_TYPE_V  0x00000007U
+#define GPIO_PIN32_INT_TYPE_S  7
+/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN32_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN32_WAKEUP_ENABLE_M  (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S)
+#define GPIO_PIN32_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN32_WAKEUP_ENABLE_S  10
+/** GPIO_PIN32_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN32_CONFIG    0x00000003U
+#define GPIO_PIN32_CONFIG_M  (GPIO_PIN32_CONFIG_V << GPIO_PIN32_CONFIG_S)
+#define GPIO_PIN32_CONFIG_V  0x00000003U
+#define GPIO_PIN32_CONFIG_S  11
+/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN32_INT_ENA    0x0000001FU
+#define GPIO_PIN32_INT_ENA_M  (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S)
+#define GPIO_PIN32_INT_ENA_V  0x0000001FU
+#define GPIO_PIN32_INT_ENA_S  13
+
+/** GPIO_PIN33_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xf8)
+/** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN33_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN33_SYNC2_BYPASS_M  (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S)
+#define GPIO_PIN33_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN33_SYNC2_BYPASS_S  0
+/** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN33_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN33_PAD_DRIVER_M  (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S)
+#define GPIO_PIN33_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN33_PAD_DRIVER_S  2
+/** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN33_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN33_SYNC1_BYPASS_M  (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S)
+#define GPIO_PIN33_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN33_SYNC1_BYPASS_S  3
+/** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN33_INT_TYPE    0x00000007U
+#define GPIO_PIN33_INT_TYPE_M  (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S)
+#define GPIO_PIN33_INT_TYPE_V  0x00000007U
+#define GPIO_PIN33_INT_TYPE_S  7
+/** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN33_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN33_WAKEUP_ENABLE_M  (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S)
+#define GPIO_PIN33_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN33_WAKEUP_ENABLE_S  10
+/** GPIO_PIN33_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN33_CONFIG    0x00000003U
+#define GPIO_PIN33_CONFIG_M  (GPIO_PIN33_CONFIG_V << GPIO_PIN33_CONFIG_S)
+#define GPIO_PIN33_CONFIG_V  0x00000003U
+#define GPIO_PIN33_CONFIG_S  11
+/** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN33_INT_ENA    0x0000001FU
+#define GPIO_PIN33_INT_ENA_M  (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S)
+#define GPIO_PIN33_INT_ENA_V  0x0000001FU
+#define GPIO_PIN33_INT_ENA_S  13
+
+/** GPIO_PIN34_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xfc)
+/** GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN34_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN34_SYNC2_BYPASS_M  (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S)
+#define GPIO_PIN34_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN34_SYNC2_BYPASS_S  0
+/** GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN34_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN34_PAD_DRIVER_M  (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S)
+#define GPIO_PIN34_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN34_PAD_DRIVER_S  2
+/** GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN34_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN34_SYNC1_BYPASS_M  (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S)
+#define GPIO_PIN34_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN34_SYNC1_BYPASS_S  3
+/** GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN34_INT_TYPE    0x00000007U
+#define GPIO_PIN34_INT_TYPE_M  (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S)
+#define GPIO_PIN34_INT_TYPE_V  0x00000007U
+#define GPIO_PIN34_INT_TYPE_S  7
+/** GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN34_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN34_WAKEUP_ENABLE_M  (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S)
+#define GPIO_PIN34_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN34_WAKEUP_ENABLE_S  10
+/** GPIO_PIN34_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN34_CONFIG    0x00000003U
+#define GPIO_PIN34_CONFIG_M  (GPIO_PIN34_CONFIG_V << GPIO_PIN34_CONFIG_S)
+#define GPIO_PIN34_CONFIG_V  0x00000003U
+#define GPIO_PIN34_CONFIG_S  11
+/** GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN34_INT_ENA    0x0000001FU
+#define GPIO_PIN34_INT_ENA_M  (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S)
+#define GPIO_PIN34_INT_ENA_V  0x0000001FU
+#define GPIO_PIN34_INT_ENA_S  13
+
+/** GPIO_PIN35_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100)
+/** GPIO_PIN35_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN35_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN35_SYNC2_BYPASS_M  (GPIO_PIN35_SYNC2_BYPASS_V << GPIO_PIN35_SYNC2_BYPASS_S)
+#define GPIO_PIN35_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN35_SYNC2_BYPASS_S  0
+/** GPIO_PIN35_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN35_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN35_PAD_DRIVER_M  (GPIO_PIN35_PAD_DRIVER_V << GPIO_PIN35_PAD_DRIVER_S)
+#define GPIO_PIN35_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN35_PAD_DRIVER_S  2
+/** GPIO_PIN35_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN35_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN35_SYNC1_BYPASS_M  (GPIO_PIN35_SYNC1_BYPASS_V << GPIO_PIN35_SYNC1_BYPASS_S)
+#define GPIO_PIN35_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN35_SYNC1_BYPASS_S  3
+/** GPIO_PIN35_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN35_INT_TYPE    0x00000007U
+#define GPIO_PIN35_INT_TYPE_M  (GPIO_PIN35_INT_TYPE_V << GPIO_PIN35_INT_TYPE_S)
+#define GPIO_PIN35_INT_TYPE_V  0x00000007U
+#define GPIO_PIN35_INT_TYPE_S  7
+/** GPIO_PIN35_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN35_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN35_WAKEUP_ENABLE_M  (GPIO_PIN35_WAKEUP_ENABLE_V << GPIO_PIN35_WAKEUP_ENABLE_S)
+#define GPIO_PIN35_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN35_WAKEUP_ENABLE_S  10
+/** GPIO_PIN35_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN35_CONFIG    0x00000003U
+#define GPIO_PIN35_CONFIG_M  (GPIO_PIN35_CONFIG_V << GPIO_PIN35_CONFIG_S)
+#define GPIO_PIN35_CONFIG_V  0x00000003U
+#define GPIO_PIN35_CONFIG_S  11
+/** GPIO_PIN35_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN35_INT_ENA    0x0000001FU
+#define GPIO_PIN35_INT_ENA_M  (GPIO_PIN35_INT_ENA_V << GPIO_PIN35_INT_ENA_S)
+#define GPIO_PIN35_INT_ENA_V  0x0000001FU
+#define GPIO_PIN35_INT_ENA_S  13
+
+/** GPIO_PIN36_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104)
+/** GPIO_PIN36_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN36_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN36_SYNC2_BYPASS_M  (GPIO_PIN36_SYNC2_BYPASS_V << GPIO_PIN36_SYNC2_BYPASS_S)
+#define GPIO_PIN36_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN36_SYNC2_BYPASS_S  0
+/** GPIO_PIN36_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN36_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN36_PAD_DRIVER_M  (GPIO_PIN36_PAD_DRIVER_V << GPIO_PIN36_PAD_DRIVER_S)
+#define GPIO_PIN36_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN36_PAD_DRIVER_S  2
+/** GPIO_PIN36_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN36_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN36_SYNC1_BYPASS_M  (GPIO_PIN36_SYNC1_BYPASS_V << GPIO_PIN36_SYNC1_BYPASS_S)
+#define GPIO_PIN36_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN36_SYNC1_BYPASS_S  3
+/** GPIO_PIN36_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN36_INT_TYPE    0x00000007U
+#define GPIO_PIN36_INT_TYPE_M  (GPIO_PIN36_INT_TYPE_V << GPIO_PIN36_INT_TYPE_S)
+#define GPIO_PIN36_INT_TYPE_V  0x00000007U
+#define GPIO_PIN36_INT_TYPE_S  7
+/** GPIO_PIN36_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN36_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN36_WAKEUP_ENABLE_M  (GPIO_PIN36_WAKEUP_ENABLE_V << GPIO_PIN36_WAKEUP_ENABLE_S)
+#define GPIO_PIN36_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN36_WAKEUP_ENABLE_S  10
+/** GPIO_PIN36_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN36_CONFIG    0x00000003U
+#define GPIO_PIN36_CONFIG_M  (GPIO_PIN36_CONFIG_V << GPIO_PIN36_CONFIG_S)
+#define GPIO_PIN36_CONFIG_V  0x00000003U
+#define GPIO_PIN36_CONFIG_S  11
+/** GPIO_PIN36_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN36_INT_ENA    0x0000001FU
+#define GPIO_PIN36_INT_ENA_M  (GPIO_PIN36_INT_ENA_V << GPIO_PIN36_INT_ENA_S)
+#define GPIO_PIN36_INT_ENA_V  0x0000001FU
+#define GPIO_PIN36_INT_ENA_S  13
+
+/** GPIO_PIN37_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108)
+/** GPIO_PIN37_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN37_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN37_SYNC2_BYPASS_M  (GPIO_PIN37_SYNC2_BYPASS_V << GPIO_PIN37_SYNC2_BYPASS_S)
+#define GPIO_PIN37_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN37_SYNC2_BYPASS_S  0
+/** GPIO_PIN37_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN37_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN37_PAD_DRIVER_M  (GPIO_PIN37_PAD_DRIVER_V << GPIO_PIN37_PAD_DRIVER_S)
+#define GPIO_PIN37_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN37_PAD_DRIVER_S  2
+/** GPIO_PIN37_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN37_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN37_SYNC1_BYPASS_M  (GPIO_PIN37_SYNC1_BYPASS_V << GPIO_PIN37_SYNC1_BYPASS_S)
+#define GPIO_PIN37_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN37_SYNC1_BYPASS_S  3
+/** GPIO_PIN37_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN37_INT_TYPE    0x00000007U
+#define GPIO_PIN37_INT_TYPE_M  (GPIO_PIN37_INT_TYPE_V << GPIO_PIN37_INT_TYPE_S)
+#define GPIO_PIN37_INT_TYPE_V  0x00000007U
+#define GPIO_PIN37_INT_TYPE_S  7
+/** GPIO_PIN37_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN37_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN37_WAKEUP_ENABLE_M  (GPIO_PIN37_WAKEUP_ENABLE_V << GPIO_PIN37_WAKEUP_ENABLE_S)
+#define GPIO_PIN37_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN37_WAKEUP_ENABLE_S  10
+/** GPIO_PIN37_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN37_CONFIG    0x00000003U
+#define GPIO_PIN37_CONFIG_M  (GPIO_PIN37_CONFIG_V << GPIO_PIN37_CONFIG_S)
+#define GPIO_PIN37_CONFIG_V  0x00000003U
+#define GPIO_PIN37_CONFIG_S  11
+/** GPIO_PIN37_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN37_INT_ENA    0x0000001FU
+#define GPIO_PIN37_INT_ENA_M  (GPIO_PIN37_INT_ENA_V << GPIO_PIN37_INT_ENA_S)
+#define GPIO_PIN37_INT_ENA_V  0x0000001FU
+#define GPIO_PIN37_INT_ENA_S  13
+
+/** GPIO_PIN38_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10c)
+/** GPIO_PIN38_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN38_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN38_SYNC2_BYPASS_M  (GPIO_PIN38_SYNC2_BYPASS_V << GPIO_PIN38_SYNC2_BYPASS_S)
+#define GPIO_PIN38_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN38_SYNC2_BYPASS_S  0
+/** GPIO_PIN38_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN38_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN38_PAD_DRIVER_M  (GPIO_PIN38_PAD_DRIVER_V << GPIO_PIN38_PAD_DRIVER_S)
+#define GPIO_PIN38_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN38_PAD_DRIVER_S  2
+/** GPIO_PIN38_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN38_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN38_SYNC1_BYPASS_M  (GPIO_PIN38_SYNC1_BYPASS_V << GPIO_PIN38_SYNC1_BYPASS_S)
+#define GPIO_PIN38_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN38_SYNC1_BYPASS_S  3
+/** GPIO_PIN38_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN38_INT_TYPE    0x00000007U
+#define GPIO_PIN38_INT_TYPE_M  (GPIO_PIN38_INT_TYPE_V << GPIO_PIN38_INT_TYPE_S)
+#define GPIO_PIN38_INT_TYPE_V  0x00000007U
+#define GPIO_PIN38_INT_TYPE_S  7
+/** GPIO_PIN38_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN38_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN38_WAKEUP_ENABLE_M  (GPIO_PIN38_WAKEUP_ENABLE_V << GPIO_PIN38_WAKEUP_ENABLE_S)
+#define GPIO_PIN38_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN38_WAKEUP_ENABLE_S  10
+/** GPIO_PIN38_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN38_CONFIG    0x00000003U
+#define GPIO_PIN38_CONFIG_M  (GPIO_PIN38_CONFIG_V << GPIO_PIN38_CONFIG_S)
+#define GPIO_PIN38_CONFIG_V  0x00000003U
+#define GPIO_PIN38_CONFIG_S  11
+/** GPIO_PIN38_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN38_INT_ENA    0x0000001FU
+#define GPIO_PIN38_INT_ENA_M  (GPIO_PIN38_INT_ENA_V << GPIO_PIN38_INT_ENA_S)
+#define GPIO_PIN38_INT_ENA_V  0x0000001FU
+#define GPIO_PIN38_INT_ENA_S  13
+
+/** GPIO_PIN39_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110)
+/** GPIO_PIN39_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN39_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN39_SYNC2_BYPASS_M  (GPIO_PIN39_SYNC2_BYPASS_V << GPIO_PIN39_SYNC2_BYPASS_S)
+#define GPIO_PIN39_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN39_SYNC2_BYPASS_S  0
+/** GPIO_PIN39_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN39_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN39_PAD_DRIVER_M  (GPIO_PIN39_PAD_DRIVER_V << GPIO_PIN39_PAD_DRIVER_S)
+#define GPIO_PIN39_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN39_PAD_DRIVER_S  2
+/** GPIO_PIN39_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN39_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN39_SYNC1_BYPASS_M  (GPIO_PIN39_SYNC1_BYPASS_V << GPIO_PIN39_SYNC1_BYPASS_S)
+#define GPIO_PIN39_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN39_SYNC1_BYPASS_S  3
+/** GPIO_PIN39_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN39_INT_TYPE    0x00000007U
+#define GPIO_PIN39_INT_TYPE_M  (GPIO_PIN39_INT_TYPE_V << GPIO_PIN39_INT_TYPE_S)
+#define GPIO_PIN39_INT_TYPE_V  0x00000007U
+#define GPIO_PIN39_INT_TYPE_S  7
+/** GPIO_PIN39_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN39_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN39_WAKEUP_ENABLE_M  (GPIO_PIN39_WAKEUP_ENABLE_V << GPIO_PIN39_WAKEUP_ENABLE_S)
+#define GPIO_PIN39_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN39_WAKEUP_ENABLE_S  10
+/** GPIO_PIN39_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN39_CONFIG    0x00000003U
+#define GPIO_PIN39_CONFIG_M  (GPIO_PIN39_CONFIG_V << GPIO_PIN39_CONFIG_S)
+#define GPIO_PIN39_CONFIG_V  0x00000003U
+#define GPIO_PIN39_CONFIG_S  11
+/** GPIO_PIN39_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN39_INT_ENA    0x0000001FU
+#define GPIO_PIN39_INT_ENA_M  (GPIO_PIN39_INT_ENA_V << GPIO_PIN39_INT_ENA_S)
+#define GPIO_PIN39_INT_ENA_V  0x0000001FU
+#define GPIO_PIN39_INT_ENA_S  13
+
+/** GPIO_PIN40_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114)
+/** GPIO_PIN40_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN40_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN40_SYNC2_BYPASS_M  (GPIO_PIN40_SYNC2_BYPASS_V << GPIO_PIN40_SYNC2_BYPASS_S)
+#define GPIO_PIN40_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN40_SYNC2_BYPASS_S  0
+/** GPIO_PIN40_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN40_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN40_PAD_DRIVER_M  (GPIO_PIN40_PAD_DRIVER_V << GPIO_PIN40_PAD_DRIVER_S)
+#define GPIO_PIN40_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN40_PAD_DRIVER_S  2
+/** GPIO_PIN40_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN40_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN40_SYNC1_BYPASS_M  (GPIO_PIN40_SYNC1_BYPASS_V << GPIO_PIN40_SYNC1_BYPASS_S)
+#define GPIO_PIN40_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN40_SYNC1_BYPASS_S  3
+/** GPIO_PIN40_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN40_INT_TYPE    0x00000007U
+#define GPIO_PIN40_INT_TYPE_M  (GPIO_PIN40_INT_TYPE_V << GPIO_PIN40_INT_TYPE_S)
+#define GPIO_PIN40_INT_TYPE_V  0x00000007U
+#define GPIO_PIN40_INT_TYPE_S  7
+/** GPIO_PIN40_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN40_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN40_WAKEUP_ENABLE_M  (GPIO_PIN40_WAKEUP_ENABLE_V << GPIO_PIN40_WAKEUP_ENABLE_S)
+#define GPIO_PIN40_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN40_WAKEUP_ENABLE_S  10
+/** GPIO_PIN40_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN40_CONFIG    0x00000003U
+#define GPIO_PIN40_CONFIG_M  (GPIO_PIN40_CONFIG_V << GPIO_PIN40_CONFIG_S)
+#define GPIO_PIN40_CONFIG_V  0x00000003U
+#define GPIO_PIN40_CONFIG_S  11
+/** GPIO_PIN40_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN40_INT_ENA    0x0000001FU
+#define GPIO_PIN40_INT_ENA_M  (GPIO_PIN40_INT_ENA_V << GPIO_PIN40_INT_ENA_S)
+#define GPIO_PIN40_INT_ENA_V  0x0000001FU
+#define GPIO_PIN40_INT_ENA_S  13
+
+/** GPIO_PIN41_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118)
+/** GPIO_PIN41_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN41_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN41_SYNC2_BYPASS_M  (GPIO_PIN41_SYNC2_BYPASS_V << GPIO_PIN41_SYNC2_BYPASS_S)
+#define GPIO_PIN41_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN41_SYNC2_BYPASS_S  0
+/** GPIO_PIN41_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN41_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN41_PAD_DRIVER_M  (GPIO_PIN41_PAD_DRIVER_V << GPIO_PIN41_PAD_DRIVER_S)
+#define GPIO_PIN41_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN41_PAD_DRIVER_S  2
+/** GPIO_PIN41_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN41_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN41_SYNC1_BYPASS_M  (GPIO_PIN41_SYNC1_BYPASS_V << GPIO_PIN41_SYNC1_BYPASS_S)
+#define GPIO_PIN41_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN41_SYNC1_BYPASS_S  3
+/** GPIO_PIN41_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN41_INT_TYPE    0x00000007U
+#define GPIO_PIN41_INT_TYPE_M  (GPIO_PIN41_INT_TYPE_V << GPIO_PIN41_INT_TYPE_S)
+#define GPIO_PIN41_INT_TYPE_V  0x00000007U
+#define GPIO_PIN41_INT_TYPE_S  7
+/** GPIO_PIN41_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN41_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN41_WAKEUP_ENABLE_M  (GPIO_PIN41_WAKEUP_ENABLE_V << GPIO_PIN41_WAKEUP_ENABLE_S)
+#define GPIO_PIN41_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN41_WAKEUP_ENABLE_S  10
+/** GPIO_PIN41_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN41_CONFIG    0x00000003U
+#define GPIO_PIN41_CONFIG_M  (GPIO_PIN41_CONFIG_V << GPIO_PIN41_CONFIG_S)
+#define GPIO_PIN41_CONFIG_V  0x00000003U
+#define GPIO_PIN41_CONFIG_S  11
+/** GPIO_PIN41_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN41_INT_ENA    0x0000001FU
+#define GPIO_PIN41_INT_ENA_M  (GPIO_PIN41_INT_ENA_V << GPIO_PIN41_INT_ENA_S)
+#define GPIO_PIN41_INT_ENA_V  0x0000001FU
+#define GPIO_PIN41_INT_ENA_S  13
+
+/** GPIO_PIN42_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11c)
+/** GPIO_PIN42_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN42_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN42_SYNC2_BYPASS_M  (GPIO_PIN42_SYNC2_BYPASS_V << GPIO_PIN42_SYNC2_BYPASS_S)
+#define GPIO_PIN42_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN42_SYNC2_BYPASS_S  0
+/** GPIO_PIN42_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN42_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN42_PAD_DRIVER_M  (GPIO_PIN42_PAD_DRIVER_V << GPIO_PIN42_PAD_DRIVER_S)
+#define GPIO_PIN42_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN42_PAD_DRIVER_S  2
+/** GPIO_PIN42_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN42_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN42_SYNC1_BYPASS_M  (GPIO_PIN42_SYNC1_BYPASS_V << GPIO_PIN42_SYNC1_BYPASS_S)
+#define GPIO_PIN42_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN42_SYNC1_BYPASS_S  3
+/** GPIO_PIN42_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN42_INT_TYPE    0x00000007U
+#define GPIO_PIN42_INT_TYPE_M  (GPIO_PIN42_INT_TYPE_V << GPIO_PIN42_INT_TYPE_S)
+#define GPIO_PIN42_INT_TYPE_V  0x00000007U
+#define GPIO_PIN42_INT_TYPE_S  7
+/** GPIO_PIN42_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN42_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN42_WAKEUP_ENABLE_M  (GPIO_PIN42_WAKEUP_ENABLE_V << GPIO_PIN42_WAKEUP_ENABLE_S)
+#define GPIO_PIN42_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN42_WAKEUP_ENABLE_S  10
+/** GPIO_PIN42_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN42_CONFIG    0x00000003U
+#define GPIO_PIN42_CONFIG_M  (GPIO_PIN42_CONFIG_V << GPIO_PIN42_CONFIG_S)
+#define GPIO_PIN42_CONFIG_V  0x00000003U
+#define GPIO_PIN42_CONFIG_S  11
+/** GPIO_PIN42_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN42_INT_ENA    0x0000001FU
+#define GPIO_PIN42_INT_ENA_M  (GPIO_PIN42_INT_ENA_V << GPIO_PIN42_INT_ENA_S)
+#define GPIO_PIN42_INT_ENA_V  0x0000001FU
+#define GPIO_PIN42_INT_ENA_S  13
+
+/** GPIO_PIN43_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120)
+/** GPIO_PIN43_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN43_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN43_SYNC2_BYPASS_M  (GPIO_PIN43_SYNC2_BYPASS_V << GPIO_PIN43_SYNC2_BYPASS_S)
+#define GPIO_PIN43_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN43_SYNC2_BYPASS_S  0
+/** GPIO_PIN43_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN43_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN43_PAD_DRIVER_M  (GPIO_PIN43_PAD_DRIVER_V << GPIO_PIN43_PAD_DRIVER_S)
+#define GPIO_PIN43_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN43_PAD_DRIVER_S  2
+/** GPIO_PIN43_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN43_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN43_SYNC1_BYPASS_M  (GPIO_PIN43_SYNC1_BYPASS_V << GPIO_PIN43_SYNC1_BYPASS_S)
+#define GPIO_PIN43_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN43_SYNC1_BYPASS_S  3
+/** GPIO_PIN43_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN43_INT_TYPE    0x00000007U
+#define GPIO_PIN43_INT_TYPE_M  (GPIO_PIN43_INT_TYPE_V << GPIO_PIN43_INT_TYPE_S)
+#define GPIO_PIN43_INT_TYPE_V  0x00000007U
+#define GPIO_PIN43_INT_TYPE_S  7
+/** GPIO_PIN43_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN43_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN43_WAKEUP_ENABLE_M  (GPIO_PIN43_WAKEUP_ENABLE_V << GPIO_PIN43_WAKEUP_ENABLE_S)
+#define GPIO_PIN43_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN43_WAKEUP_ENABLE_S  10
+/** GPIO_PIN43_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN43_CONFIG    0x00000003U
+#define GPIO_PIN43_CONFIG_M  (GPIO_PIN43_CONFIG_V << GPIO_PIN43_CONFIG_S)
+#define GPIO_PIN43_CONFIG_V  0x00000003U
+#define GPIO_PIN43_CONFIG_S  11
+/** GPIO_PIN43_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN43_INT_ENA    0x0000001FU
+#define GPIO_PIN43_INT_ENA_M  (GPIO_PIN43_INT_ENA_V << GPIO_PIN43_INT_ENA_S)
+#define GPIO_PIN43_INT_ENA_V  0x0000001FU
+#define GPIO_PIN43_INT_ENA_S  13
+
+/** GPIO_PIN44_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124)
+/** GPIO_PIN44_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN44_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN44_SYNC2_BYPASS_M  (GPIO_PIN44_SYNC2_BYPASS_V << GPIO_PIN44_SYNC2_BYPASS_S)
+#define GPIO_PIN44_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN44_SYNC2_BYPASS_S  0
+/** GPIO_PIN44_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN44_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN44_PAD_DRIVER_M  (GPIO_PIN44_PAD_DRIVER_V << GPIO_PIN44_PAD_DRIVER_S)
+#define GPIO_PIN44_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN44_PAD_DRIVER_S  2
+/** GPIO_PIN44_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN44_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN44_SYNC1_BYPASS_M  (GPIO_PIN44_SYNC1_BYPASS_V << GPIO_PIN44_SYNC1_BYPASS_S)
+#define GPIO_PIN44_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN44_SYNC1_BYPASS_S  3
+/** GPIO_PIN44_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN44_INT_TYPE    0x00000007U
+#define GPIO_PIN44_INT_TYPE_M  (GPIO_PIN44_INT_TYPE_V << GPIO_PIN44_INT_TYPE_S)
+#define GPIO_PIN44_INT_TYPE_V  0x00000007U
+#define GPIO_PIN44_INT_TYPE_S  7
+/** GPIO_PIN44_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN44_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN44_WAKEUP_ENABLE_M  (GPIO_PIN44_WAKEUP_ENABLE_V << GPIO_PIN44_WAKEUP_ENABLE_S)
+#define GPIO_PIN44_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN44_WAKEUP_ENABLE_S  10
+/** GPIO_PIN44_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN44_CONFIG    0x00000003U
+#define GPIO_PIN44_CONFIG_M  (GPIO_PIN44_CONFIG_V << GPIO_PIN44_CONFIG_S)
+#define GPIO_PIN44_CONFIG_V  0x00000003U
+#define GPIO_PIN44_CONFIG_S  11
+/** GPIO_PIN44_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN44_INT_ENA    0x0000001FU
+#define GPIO_PIN44_INT_ENA_M  (GPIO_PIN44_INT_ENA_V << GPIO_PIN44_INT_ENA_S)
+#define GPIO_PIN44_INT_ENA_V  0x0000001FU
+#define GPIO_PIN44_INT_ENA_S  13
+
+/** GPIO_PIN45_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN45_REG (DR_REG_GPIO_BASE + 0x128)
+/** GPIO_PIN45_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN45_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN45_SYNC2_BYPASS_M  (GPIO_PIN45_SYNC2_BYPASS_V << GPIO_PIN45_SYNC2_BYPASS_S)
+#define GPIO_PIN45_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN45_SYNC2_BYPASS_S  0
+/** GPIO_PIN45_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN45_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN45_PAD_DRIVER_M  (GPIO_PIN45_PAD_DRIVER_V << GPIO_PIN45_PAD_DRIVER_S)
+#define GPIO_PIN45_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN45_PAD_DRIVER_S  2
+/** GPIO_PIN45_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN45_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN45_SYNC1_BYPASS_M  (GPIO_PIN45_SYNC1_BYPASS_V << GPIO_PIN45_SYNC1_BYPASS_S)
+#define GPIO_PIN45_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN45_SYNC1_BYPASS_S  3
+/** GPIO_PIN45_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN45_INT_TYPE    0x00000007U
+#define GPIO_PIN45_INT_TYPE_M  (GPIO_PIN45_INT_TYPE_V << GPIO_PIN45_INT_TYPE_S)
+#define GPIO_PIN45_INT_TYPE_V  0x00000007U
+#define GPIO_PIN45_INT_TYPE_S  7
+/** GPIO_PIN45_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN45_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN45_WAKEUP_ENABLE_M  (GPIO_PIN45_WAKEUP_ENABLE_V << GPIO_PIN45_WAKEUP_ENABLE_S)
+#define GPIO_PIN45_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN45_WAKEUP_ENABLE_S  10
+/** GPIO_PIN45_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN45_CONFIG    0x00000003U
+#define GPIO_PIN45_CONFIG_M  (GPIO_PIN45_CONFIG_V << GPIO_PIN45_CONFIG_S)
+#define GPIO_PIN45_CONFIG_V  0x00000003U
+#define GPIO_PIN45_CONFIG_S  11
+/** GPIO_PIN45_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN45_INT_ENA    0x0000001FU
+#define GPIO_PIN45_INT_ENA_M  (GPIO_PIN45_INT_ENA_V << GPIO_PIN45_INT_ENA_S)
+#define GPIO_PIN45_INT_ENA_V  0x0000001FU
+#define GPIO_PIN45_INT_ENA_S  13
+
+/** GPIO_PIN46_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN46_REG (DR_REG_GPIO_BASE + 0x12c)
+/** GPIO_PIN46_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN46_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN46_SYNC2_BYPASS_M  (GPIO_PIN46_SYNC2_BYPASS_V << GPIO_PIN46_SYNC2_BYPASS_S)
+#define GPIO_PIN46_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN46_SYNC2_BYPASS_S  0
+/** GPIO_PIN46_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN46_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN46_PAD_DRIVER_M  (GPIO_PIN46_PAD_DRIVER_V << GPIO_PIN46_PAD_DRIVER_S)
+#define GPIO_PIN46_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN46_PAD_DRIVER_S  2
+/** GPIO_PIN46_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN46_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN46_SYNC1_BYPASS_M  (GPIO_PIN46_SYNC1_BYPASS_V << GPIO_PIN46_SYNC1_BYPASS_S)
+#define GPIO_PIN46_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN46_SYNC1_BYPASS_S  3
+/** GPIO_PIN46_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN46_INT_TYPE    0x00000007U
+#define GPIO_PIN46_INT_TYPE_M  (GPIO_PIN46_INT_TYPE_V << GPIO_PIN46_INT_TYPE_S)
+#define GPIO_PIN46_INT_TYPE_V  0x00000007U
+#define GPIO_PIN46_INT_TYPE_S  7
+/** GPIO_PIN46_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN46_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN46_WAKEUP_ENABLE_M  (GPIO_PIN46_WAKEUP_ENABLE_V << GPIO_PIN46_WAKEUP_ENABLE_S)
+#define GPIO_PIN46_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN46_WAKEUP_ENABLE_S  10
+/** GPIO_PIN46_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN46_CONFIG    0x00000003U
+#define GPIO_PIN46_CONFIG_M  (GPIO_PIN46_CONFIG_V << GPIO_PIN46_CONFIG_S)
+#define GPIO_PIN46_CONFIG_V  0x00000003U
+#define GPIO_PIN46_CONFIG_S  11
+/** GPIO_PIN46_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN46_INT_ENA    0x0000001FU
+#define GPIO_PIN46_INT_ENA_M  (GPIO_PIN46_INT_ENA_V << GPIO_PIN46_INT_ENA_S)
+#define GPIO_PIN46_INT_ENA_V  0x0000001FU
+#define GPIO_PIN46_INT_ENA_S  13
+
+/** GPIO_PIN47_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN47_REG (DR_REG_GPIO_BASE + 0x130)
+/** GPIO_PIN47_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN47_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN47_SYNC2_BYPASS_M  (GPIO_PIN47_SYNC2_BYPASS_V << GPIO_PIN47_SYNC2_BYPASS_S)
+#define GPIO_PIN47_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN47_SYNC2_BYPASS_S  0
+/** GPIO_PIN47_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN47_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN47_PAD_DRIVER_M  (GPIO_PIN47_PAD_DRIVER_V << GPIO_PIN47_PAD_DRIVER_S)
+#define GPIO_PIN47_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN47_PAD_DRIVER_S  2
+/** GPIO_PIN47_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN47_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN47_SYNC1_BYPASS_M  (GPIO_PIN47_SYNC1_BYPASS_V << GPIO_PIN47_SYNC1_BYPASS_S)
+#define GPIO_PIN47_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN47_SYNC1_BYPASS_S  3
+/** GPIO_PIN47_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN47_INT_TYPE    0x00000007U
+#define GPIO_PIN47_INT_TYPE_M  (GPIO_PIN47_INT_TYPE_V << GPIO_PIN47_INT_TYPE_S)
+#define GPIO_PIN47_INT_TYPE_V  0x00000007U
+#define GPIO_PIN47_INT_TYPE_S  7
+/** GPIO_PIN47_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN47_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN47_WAKEUP_ENABLE_M  (GPIO_PIN47_WAKEUP_ENABLE_V << GPIO_PIN47_WAKEUP_ENABLE_S)
+#define GPIO_PIN47_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN47_WAKEUP_ENABLE_S  10
+/** GPIO_PIN47_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN47_CONFIG    0x00000003U
+#define GPIO_PIN47_CONFIG_M  (GPIO_PIN47_CONFIG_V << GPIO_PIN47_CONFIG_S)
+#define GPIO_PIN47_CONFIG_V  0x00000003U
+#define GPIO_PIN47_CONFIG_S  11
+/** GPIO_PIN47_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN47_INT_ENA    0x0000001FU
+#define GPIO_PIN47_INT_ENA_M  (GPIO_PIN47_INT_ENA_V << GPIO_PIN47_INT_ENA_S)
+#define GPIO_PIN47_INT_ENA_V  0x0000001FU
+#define GPIO_PIN47_INT_ENA_S  13
+
+/** GPIO_PIN48_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN48_REG (DR_REG_GPIO_BASE + 0x134)
+/** GPIO_PIN48_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN48_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN48_SYNC2_BYPASS_M  (GPIO_PIN48_SYNC2_BYPASS_V << GPIO_PIN48_SYNC2_BYPASS_S)
+#define GPIO_PIN48_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN48_SYNC2_BYPASS_S  0
+/** GPIO_PIN48_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN48_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN48_PAD_DRIVER_M  (GPIO_PIN48_PAD_DRIVER_V << GPIO_PIN48_PAD_DRIVER_S)
+#define GPIO_PIN48_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN48_PAD_DRIVER_S  2
+/** GPIO_PIN48_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN48_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN48_SYNC1_BYPASS_M  (GPIO_PIN48_SYNC1_BYPASS_V << GPIO_PIN48_SYNC1_BYPASS_S)
+#define GPIO_PIN48_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN48_SYNC1_BYPASS_S  3
+/** GPIO_PIN48_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN48_INT_TYPE    0x00000007U
+#define GPIO_PIN48_INT_TYPE_M  (GPIO_PIN48_INT_TYPE_V << GPIO_PIN48_INT_TYPE_S)
+#define GPIO_PIN48_INT_TYPE_V  0x00000007U
+#define GPIO_PIN48_INT_TYPE_S  7
+/** GPIO_PIN48_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN48_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN48_WAKEUP_ENABLE_M  (GPIO_PIN48_WAKEUP_ENABLE_V << GPIO_PIN48_WAKEUP_ENABLE_S)
+#define GPIO_PIN48_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN48_WAKEUP_ENABLE_S  10
+/** GPIO_PIN48_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN48_CONFIG    0x00000003U
+#define GPIO_PIN48_CONFIG_M  (GPIO_PIN48_CONFIG_V << GPIO_PIN48_CONFIG_S)
+#define GPIO_PIN48_CONFIG_V  0x00000003U
+#define GPIO_PIN48_CONFIG_S  11
+/** GPIO_PIN48_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN48_INT_ENA    0x0000001FU
+#define GPIO_PIN48_INT_ENA_M  (GPIO_PIN48_INT_ENA_V << GPIO_PIN48_INT_ENA_S)
+#define GPIO_PIN48_INT_ENA_V  0x0000001FU
+#define GPIO_PIN48_INT_ENA_S  13
+
+/** GPIO_PIN49_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN49_REG (DR_REG_GPIO_BASE + 0x138)
+/** GPIO_PIN49_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN49_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN49_SYNC2_BYPASS_M  (GPIO_PIN49_SYNC2_BYPASS_V << GPIO_PIN49_SYNC2_BYPASS_S)
+#define GPIO_PIN49_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN49_SYNC2_BYPASS_S  0
+/** GPIO_PIN49_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN49_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN49_PAD_DRIVER_M  (GPIO_PIN49_PAD_DRIVER_V << GPIO_PIN49_PAD_DRIVER_S)
+#define GPIO_PIN49_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN49_PAD_DRIVER_S  2
+/** GPIO_PIN49_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN49_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN49_SYNC1_BYPASS_M  (GPIO_PIN49_SYNC1_BYPASS_V << GPIO_PIN49_SYNC1_BYPASS_S)
+#define GPIO_PIN49_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN49_SYNC1_BYPASS_S  3
+/** GPIO_PIN49_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN49_INT_TYPE    0x00000007U
+#define GPIO_PIN49_INT_TYPE_M  (GPIO_PIN49_INT_TYPE_V << GPIO_PIN49_INT_TYPE_S)
+#define GPIO_PIN49_INT_TYPE_V  0x00000007U
+#define GPIO_PIN49_INT_TYPE_S  7
+/** GPIO_PIN49_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN49_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN49_WAKEUP_ENABLE_M  (GPIO_PIN49_WAKEUP_ENABLE_V << GPIO_PIN49_WAKEUP_ENABLE_S)
+#define GPIO_PIN49_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN49_WAKEUP_ENABLE_S  10
+/** GPIO_PIN49_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN49_CONFIG    0x00000003U
+#define GPIO_PIN49_CONFIG_M  (GPIO_PIN49_CONFIG_V << GPIO_PIN49_CONFIG_S)
+#define GPIO_PIN49_CONFIG_V  0x00000003U
+#define GPIO_PIN49_CONFIG_S  11
+/** GPIO_PIN49_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN49_INT_ENA    0x0000001FU
+#define GPIO_PIN49_INT_ENA_M  (GPIO_PIN49_INT_ENA_V << GPIO_PIN49_INT_ENA_S)
+#define GPIO_PIN49_INT_ENA_V  0x0000001FU
+#define GPIO_PIN49_INT_ENA_S  13
+
+/** GPIO_PIN50_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN50_REG (DR_REG_GPIO_BASE + 0x13c)
+/** GPIO_PIN50_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN50_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN50_SYNC2_BYPASS_M  (GPIO_PIN50_SYNC2_BYPASS_V << GPIO_PIN50_SYNC2_BYPASS_S)
+#define GPIO_PIN50_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN50_SYNC2_BYPASS_S  0
+/** GPIO_PIN50_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN50_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN50_PAD_DRIVER_M  (GPIO_PIN50_PAD_DRIVER_V << GPIO_PIN50_PAD_DRIVER_S)
+#define GPIO_PIN50_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN50_PAD_DRIVER_S  2
+/** GPIO_PIN50_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN50_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN50_SYNC1_BYPASS_M  (GPIO_PIN50_SYNC1_BYPASS_V << GPIO_PIN50_SYNC1_BYPASS_S)
+#define GPIO_PIN50_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN50_SYNC1_BYPASS_S  3
+/** GPIO_PIN50_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN50_INT_TYPE    0x00000007U
+#define GPIO_PIN50_INT_TYPE_M  (GPIO_PIN50_INT_TYPE_V << GPIO_PIN50_INT_TYPE_S)
+#define GPIO_PIN50_INT_TYPE_V  0x00000007U
+#define GPIO_PIN50_INT_TYPE_S  7
+/** GPIO_PIN50_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN50_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN50_WAKEUP_ENABLE_M  (GPIO_PIN50_WAKEUP_ENABLE_V << GPIO_PIN50_WAKEUP_ENABLE_S)
+#define GPIO_PIN50_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN50_WAKEUP_ENABLE_S  10
+/** GPIO_PIN50_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN50_CONFIG    0x00000003U
+#define GPIO_PIN50_CONFIG_M  (GPIO_PIN50_CONFIG_V << GPIO_PIN50_CONFIG_S)
+#define GPIO_PIN50_CONFIG_V  0x00000003U
+#define GPIO_PIN50_CONFIG_S  11
+/** GPIO_PIN50_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN50_INT_ENA    0x0000001FU
+#define GPIO_PIN50_INT_ENA_M  (GPIO_PIN50_INT_ENA_V << GPIO_PIN50_INT_ENA_S)
+#define GPIO_PIN50_INT_ENA_V  0x0000001FU
+#define GPIO_PIN50_INT_ENA_S  13
+
+/** GPIO_PIN51_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN51_REG (DR_REG_GPIO_BASE + 0x140)
+/** GPIO_PIN51_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN51_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN51_SYNC2_BYPASS_M  (GPIO_PIN51_SYNC2_BYPASS_V << GPIO_PIN51_SYNC2_BYPASS_S)
+#define GPIO_PIN51_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN51_SYNC2_BYPASS_S  0
+/** GPIO_PIN51_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN51_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN51_PAD_DRIVER_M  (GPIO_PIN51_PAD_DRIVER_V << GPIO_PIN51_PAD_DRIVER_S)
+#define GPIO_PIN51_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN51_PAD_DRIVER_S  2
+/** GPIO_PIN51_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN51_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN51_SYNC1_BYPASS_M  (GPIO_PIN51_SYNC1_BYPASS_V << GPIO_PIN51_SYNC1_BYPASS_S)
+#define GPIO_PIN51_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN51_SYNC1_BYPASS_S  3
+/** GPIO_PIN51_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN51_INT_TYPE    0x00000007U
+#define GPIO_PIN51_INT_TYPE_M  (GPIO_PIN51_INT_TYPE_V << GPIO_PIN51_INT_TYPE_S)
+#define GPIO_PIN51_INT_TYPE_V  0x00000007U
+#define GPIO_PIN51_INT_TYPE_S  7
+/** GPIO_PIN51_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN51_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN51_WAKEUP_ENABLE_M  (GPIO_PIN51_WAKEUP_ENABLE_V << GPIO_PIN51_WAKEUP_ENABLE_S)
+#define GPIO_PIN51_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN51_WAKEUP_ENABLE_S  10
+/** GPIO_PIN51_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN51_CONFIG    0x00000003U
+#define GPIO_PIN51_CONFIG_M  (GPIO_PIN51_CONFIG_V << GPIO_PIN51_CONFIG_S)
+#define GPIO_PIN51_CONFIG_V  0x00000003U
+#define GPIO_PIN51_CONFIG_S  11
+/** GPIO_PIN51_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN51_INT_ENA    0x0000001FU
+#define GPIO_PIN51_INT_ENA_M  (GPIO_PIN51_INT_ENA_V << GPIO_PIN51_INT_ENA_S)
+#define GPIO_PIN51_INT_ENA_V  0x0000001FU
+#define GPIO_PIN51_INT_ENA_S  13
+
+/** GPIO_PIN52_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN52_REG (DR_REG_GPIO_BASE + 0x144)
+/** GPIO_PIN52_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN52_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN52_SYNC2_BYPASS_M  (GPIO_PIN52_SYNC2_BYPASS_V << GPIO_PIN52_SYNC2_BYPASS_S)
+#define GPIO_PIN52_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN52_SYNC2_BYPASS_S  0
+/** GPIO_PIN52_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN52_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN52_PAD_DRIVER_M  (GPIO_PIN52_PAD_DRIVER_V << GPIO_PIN52_PAD_DRIVER_S)
+#define GPIO_PIN52_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN52_PAD_DRIVER_S  2
+/** GPIO_PIN52_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN52_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN52_SYNC1_BYPASS_M  (GPIO_PIN52_SYNC1_BYPASS_V << GPIO_PIN52_SYNC1_BYPASS_S)
+#define GPIO_PIN52_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN52_SYNC1_BYPASS_S  3
+/** GPIO_PIN52_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN52_INT_TYPE    0x00000007U
+#define GPIO_PIN52_INT_TYPE_M  (GPIO_PIN52_INT_TYPE_V << GPIO_PIN52_INT_TYPE_S)
+#define GPIO_PIN52_INT_TYPE_V  0x00000007U
+#define GPIO_PIN52_INT_TYPE_S  7
+/** GPIO_PIN52_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN52_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN52_WAKEUP_ENABLE_M  (GPIO_PIN52_WAKEUP_ENABLE_V << GPIO_PIN52_WAKEUP_ENABLE_S)
+#define GPIO_PIN52_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN52_WAKEUP_ENABLE_S  10
+/** GPIO_PIN52_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN52_CONFIG    0x00000003U
+#define GPIO_PIN52_CONFIG_M  (GPIO_PIN52_CONFIG_V << GPIO_PIN52_CONFIG_S)
+#define GPIO_PIN52_CONFIG_V  0x00000003U
+#define GPIO_PIN52_CONFIG_S  11
+/** GPIO_PIN52_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN52_INT_ENA    0x0000001FU
+#define GPIO_PIN52_INT_ENA_M  (GPIO_PIN52_INT_ENA_V << GPIO_PIN52_INT_ENA_S)
+#define GPIO_PIN52_INT_ENA_V  0x0000001FU
+#define GPIO_PIN52_INT_ENA_S  13
+
+/** GPIO_PIN53_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN53_REG (DR_REG_GPIO_BASE + 0x148)
+/** GPIO_PIN53_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN53_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN53_SYNC2_BYPASS_M  (GPIO_PIN53_SYNC2_BYPASS_V << GPIO_PIN53_SYNC2_BYPASS_S)
+#define GPIO_PIN53_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN53_SYNC2_BYPASS_S  0
+/** GPIO_PIN53_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN53_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN53_PAD_DRIVER_M  (GPIO_PIN53_PAD_DRIVER_V << GPIO_PIN53_PAD_DRIVER_S)
+#define GPIO_PIN53_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN53_PAD_DRIVER_S  2
+/** GPIO_PIN53_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN53_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN53_SYNC1_BYPASS_M  (GPIO_PIN53_SYNC1_BYPASS_V << GPIO_PIN53_SYNC1_BYPASS_S)
+#define GPIO_PIN53_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN53_SYNC1_BYPASS_S  3
+/** GPIO_PIN53_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN53_INT_TYPE    0x00000007U
+#define GPIO_PIN53_INT_TYPE_M  (GPIO_PIN53_INT_TYPE_V << GPIO_PIN53_INT_TYPE_S)
+#define GPIO_PIN53_INT_TYPE_V  0x00000007U
+#define GPIO_PIN53_INT_TYPE_S  7
+/** GPIO_PIN53_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN53_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN53_WAKEUP_ENABLE_M  (GPIO_PIN53_WAKEUP_ENABLE_V << GPIO_PIN53_WAKEUP_ENABLE_S)
+#define GPIO_PIN53_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN53_WAKEUP_ENABLE_S  10
+/** GPIO_PIN53_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN53_CONFIG    0x00000003U
+#define GPIO_PIN53_CONFIG_M  (GPIO_PIN53_CONFIG_V << GPIO_PIN53_CONFIG_S)
+#define GPIO_PIN53_CONFIG_V  0x00000003U
+#define GPIO_PIN53_CONFIG_S  11
+/** GPIO_PIN53_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN53_INT_ENA    0x0000001FU
+#define GPIO_PIN53_INT_ENA_M  (GPIO_PIN53_INT_ENA_V << GPIO_PIN53_INT_ENA_S)
+#define GPIO_PIN53_INT_ENA_V  0x0000001FU
+#define GPIO_PIN53_INT_ENA_S  13
+
+/** GPIO_PIN54_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN54_REG (DR_REG_GPIO_BASE + 0x14c)
+/** GPIO_PIN54_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN54_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN54_SYNC2_BYPASS_M  (GPIO_PIN54_SYNC2_BYPASS_V << GPIO_PIN54_SYNC2_BYPASS_S)
+#define GPIO_PIN54_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN54_SYNC2_BYPASS_S  0
+/** GPIO_PIN54_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN54_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN54_PAD_DRIVER_M  (GPIO_PIN54_PAD_DRIVER_V << GPIO_PIN54_PAD_DRIVER_S)
+#define GPIO_PIN54_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN54_PAD_DRIVER_S  2
+/** GPIO_PIN54_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN54_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN54_SYNC1_BYPASS_M  (GPIO_PIN54_SYNC1_BYPASS_V << GPIO_PIN54_SYNC1_BYPASS_S)
+#define GPIO_PIN54_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN54_SYNC1_BYPASS_S  3
+/** GPIO_PIN54_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN54_INT_TYPE    0x00000007U
+#define GPIO_PIN54_INT_TYPE_M  (GPIO_PIN54_INT_TYPE_V << GPIO_PIN54_INT_TYPE_S)
+#define GPIO_PIN54_INT_TYPE_V  0x00000007U
+#define GPIO_PIN54_INT_TYPE_S  7
+/** GPIO_PIN54_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN54_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN54_WAKEUP_ENABLE_M  (GPIO_PIN54_WAKEUP_ENABLE_V << GPIO_PIN54_WAKEUP_ENABLE_S)
+#define GPIO_PIN54_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN54_WAKEUP_ENABLE_S  10
+/** GPIO_PIN54_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN54_CONFIG    0x00000003U
+#define GPIO_PIN54_CONFIG_M  (GPIO_PIN54_CONFIG_V << GPIO_PIN54_CONFIG_S)
+#define GPIO_PIN54_CONFIG_V  0x00000003U
+#define GPIO_PIN54_CONFIG_S  11
+/** GPIO_PIN54_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN54_INT_ENA    0x0000001FU
+#define GPIO_PIN54_INT_ENA_M  (GPIO_PIN54_INT_ENA_V << GPIO_PIN54_INT_ENA_S)
+#define GPIO_PIN54_INT_ENA_V  0x0000001FU
+#define GPIO_PIN54_INT_ENA_S  13
+
+/** GPIO_PIN55_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN55_REG (DR_REG_GPIO_BASE + 0x150)
+/** GPIO_PIN55_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN55_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN55_SYNC2_BYPASS_M  (GPIO_PIN55_SYNC2_BYPASS_V << GPIO_PIN55_SYNC2_BYPASS_S)
+#define GPIO_PIN55_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN55_SYNC2_BYPASS_S  0
+/** GPIO_PIN55_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN55_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN55_PAD_DRIVER_M  (GPIO_PIN55_PAD_DRIVER_V << GPIO_PIN55_PAD_DRIVER_S)
+#define GPIO_PIN55_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN55_PAD_DRIVER_S  2
+/** GPIO_PIN55_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN55_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN55_SYNC1_BYPASS_M  (GPIO_PIN55_SYNC1_BYPASS_V << GPIO_PIN55_SYNC1_BYPASS_S)
+#define GPIO_PIN55_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN55_SYNC1_BYPASS_S  3
+/** GPIO_PIN55_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN55_INT_TYPE    0x00000007U
+#define GPIO_PIN55_INT_TYPE_M  (GPIO_PIN55_INT_TYPE_V << GPIO_PIN55_INT_TYPE_S)
+#define GPIO_PIN55_INT_TYPE_V  0x00000007U
+#define GPIO_PIN55_INT_TYPE_S  7
+/** GPIO_PIN55_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN55_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN55_WAKEUP_ENABLE_M  (GPIO_PIN55_WAKEUP_ENABLE_V << GPIO_PIN55_WAKEUP_ENABLE_S)
+#define GPIO_PIN55_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN55_WAKEUP_ENABLE_S  10
+/** GPIO_PIN55_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN55_CONFIG    0x00000003U
+#define GPIO_PIN55_CONFIG_M  (GPIO_PIN55_CONFIG_V << GPIO_PIN55_CONFIG_S)
+#define GPIO_PIN55_CONFIG_V  0x00000003U
+#define GPIO_PIN55_CONFIG_S  11
+/** GPIO_PIN55_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN55_INT_ENA    0x0000001FU
+#define GPIO_PIN55_INT_ENA_M  (GPIO_PIN55_INT_ENA_V << GPIO_PIN55_INT_ENA_S)
+#define GPIO_PIN55_INT_ENA_V  0x0000001FU
+#define GPIO_PIN55_INT_ENA_S  13
+
+/** GPIO_PIN56_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN56_REG (DR_REG_GPIO_BASE + 0x154)
+/** GPIO_PIN56_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN56_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN56_SYNC2_BYPASS_M  (GPIO_PIN56_SYNC2_BYPASS_V << GPIO_PIN56_SYNC2_BYPASS_S)
+#define GPIO_PIN56_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN56_SYNC2_BYPASS_S  0
+/** GPIO_PIN56_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN56_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN56_PAD_DRIVER_M  (GPIO_PIN56_PAD_DRIVER_V << GPIO_PIN56_PAD_DRIVER_S)
+#define GPIO_PIN56_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN56_PAD_DRIVER_S  2
+/** GPIO_PIN56_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN56_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN56_SYNC1_BYPASS_M  (GPIO_PIN56_SYNC1_BYPASS_V << GPIO_PIN56_SYNC1_BYPASS_S)
+#define GPIO_PIN56_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN56_SYNC1_BYPASS_S  3
+/** GPIO_PIN56_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN56_INT_TYPE    0x00000007U
+#define GPIO_PIN56_INT_TYPE_M  (GPIO_PIN56_INT_TYPE_V << GPIO_PIN56_INT_TYPE_S)
+#define GPIO_PIN56_INT_TYPE_V  0x00000007U
+#define GPIO_PIN56_INT_TYPE_S  7
+/** GPIO_PIN56_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN56_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN56_WAKEUP_ENABLE_M  (GPIO_PIN56_WAKEUP_ENABLE_V << GPIO_PIN56_WAKEUP_ENABLE_S)
+#define GPIO_PIN56_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN56_WAKEUP_ENABLE_S  10
+/** GPIO_PIN56_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN56_CONFIG    0x00000003U
+#define GPIO_PIN56_CONFIG_M  (GPIO_PIN56_CONFIG_V << GPIO_PIN56_CONFIG_S)
+#define GPIO_PIN56_CONFIG_V  0x00000003U
+#define GPIO_PIN56_CONFIG_S  11
+/** GPIO_PIN56_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN56_INT_ENA    0x0000001FU
+#define GPIO_PIN56_INT_ENA_M  (GPIO_PIN56_INT_ENA_V << GPIO_PIN56_INT_ENA_S)
+#define GPIO_PIN56_INT_ENA_V  0x0000001FU
+#define GPIO_PIN56_INT_ENA_S  13
+
+/** GPIO_FUNC1_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c)
+/** GPIO_FUNC1_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC1_IN_SEL    0x0000003FU
+#define GPIO_FUNC1_IN_SEL_M  (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S)
+#define GPIO_FUNC1_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC1_IN_SEL_S  0
+/** GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC1_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC1_IN_INV_SEL_M  (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S)
+#define GPIO_FUNC1_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_IN_INV_SEL_S  6
+/** GPIO_SIG1_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG1_IN_SEL    (BIT(7))
+#define GPIO_SIG1_IN_SEL_M  (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S)
+#define GPIO_SIG1_IN_SEL_V  0x00000001U
+#define GPIO_SIG1_IN_SEL_S  7
+
+/** GPIO_FUNC2_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160)
+/** GPIO_FUNC2_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC2_IN_SEL    0x0000003FU
+#define GPIO_FUNC2_IN_SEL_M  (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S)
+#define GPIO_FUNC2_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC2_IN_SEL_S  0
+/** GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC2_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC2_IN_INV_SEL_M  (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S)
+#define GPIO_FUNC2_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_IN_INV_SEL_S  6
+/** GPIO_SIG2_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG2_IN_SEL    (BIT(7))
+#define GPIO_SIG2_IN_SEL_M  (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S)
+#define GPIO_SIG2_IN_SEL_V  0x00000001U
+#define GPIO_SIG2_IN_SEL_S  7
+
+/** GPIO_FUNC3_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164)
+/** GPIO_FUNC3_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC3_IN_SEL    0x0000003FU
+#define GPIO_FUNC3_IN_SEL_M  (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S)
+#define GPIO_FUNC3_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC3_IN_SEL_S  0
+/** GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC3_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC3_IN_INV_SEL_M  (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S)
+#define GPIO_FUNC3_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_IN_INV_SEL_S  6
+/** GPIO_SIG3_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG3_IN_SEL    (BIT(7))
+#define GPIO_SIG3_IN_SEL_M  (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S)
+#define GPIO_SIG3_IN_SEL_V  0x00000001U
+#define GPIO_SIG3_IN_SEL_S  7
+
+/** GPIO_FUNC4_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168)
+/** GPIO_FUNC4_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC4_IN_SEL    0x0000003FU
+#define GPIO_FUNC4_IN_SEL_M  (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S)
+#define GPIO_FUNC4_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC4_IN_SEL_S  0
+/** GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC4_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC4_IN_INV_SEL_M  (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S)
+#define GPIO_FUNC4_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_IN_INV_SEL_S  6
+/** GPIO_SIG4_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG4_IN_SEL    (BIT(7))
+#define GPIO_SIG4_IN_SEL_M  (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S)
+#define GPIO_SIG4_IN_SEL_V  0x00000001U
+#define GPIO_SIG4_IN_SEL_S  7
+
+/** GPIO_FUNC5_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c)
+/** GPIO_FUNC5_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC5_IN_SEL    0x0000003FU
+#define GPIO_FUNC5_IN_SEL_M  (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S)
+#define GPIO_FUNC5_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC5_IN_SEL_S  0
+/** GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC5_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC5_IN_INV_SEL_M  (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S)
+#define GPIO_FUNC5_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_IN_INV_SEL_S  6
+/** GPIO_SIG5_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG5_IN_SEL    (BIT(7))
+#define GPIO_SIG5_IN_SEL_M  (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S)
+#define GPIO_SIG5_IN_SEL_V  0x00000001U
+#define GPIO_SIG5_IN_SEL_S  7
+
+/** GPIO_FUNC6_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170)
+/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC6_IN_SEL    0x0000003FU
+#define GPIO_FUNC6_IN_SEL_M  (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S)
+#define GPIO_FUNC6_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC6_IN_SEL_S  0
+/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC6_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC6_IN_INV_SEL_M  (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S)
+#define GPIO_FUNC6_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_IN_INV_SEL_S  6
+/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG6_IN_SEL    (BIT(7))
+#define GPIO_SIG6_IN_SEL_M  (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S)
+#define GPIO_SIG6_IN_SEL_V  0x00000001U
+#define GPIO_SIG6_IN_SEL_S  7
+
+/** GPIO_FUNC7_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174)
+/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC7_IN_SEL    0x0000003FU
+#define GPIO_FUNC7_IN_SEL_M  (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S)
+#define GPIO_FUNC7_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC7_IN_SEL_S  0
+/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC7_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC7_IN_INV_SEL_M  (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S)
+#define GPIO_FUNC7_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_IN_INV_SEL_S  6
+/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG7_IN_SEL    (BIT(7))
+#define GPIO_SIG7_IN_SEL_M  (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S)
+#define GPIO_SIG7_IN_SEL_V  0x00000001U
+#define GPIO_SIG7_IN_SEL_S  7
+
+/** GPIO_FUNC8_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178)
+/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC8_IN_SEL    0x0000003FU
+#define GPIO_FUNC8_IN_SEL_M  (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S)
+#define GPIO_FUNC8_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC8_IN_SEL_S  0
+/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC8_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC8_IN_INV_SEL_M  (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S)
+#define GPIO_FUNC8_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_IN_INV_SEL_S  6
+/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG8_IN_SEL    (BIT(7))
+#define GPIO_SIG8_IN_SEL_M  (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S)
+#define GPIO_SIG8_IN_SEL_V  0x00000001U
+#define GPIO_SIG8_IN_SEL_S  7
+
+/** GPIO_FUNC9_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c)
+/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC9_IN_SEL    0x0000003FU
+#define GPIO_FUNC9_IN_SEL_M  (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S)
+#define GPIO_FUNC9_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC9_IN_SEL_S  0
+/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC9_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC9_IN_INV_SEL_M  (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S)
+#define GPIO_FUNC9_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_IN_INV_SEL_S  6
+/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG9_IN_SEL    (BIT(7))
+#define GPIO_SIG9_IN_SEL_M  (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S)
+#define GPIO_SIG9_IN_SEL_V  0x00000001U
+#define GPIO_SIG9_IN_SEL_S  7
+
+/** GPIO_FUNC10_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180)
+/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC10_IN_SEL    0x0000003FU
+#define GPIO_FUNC10_IN_SEL_M  (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S)
+#define GPIO_FUNC10_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC10_IN_SEL_S  0
+/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC10_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC10_IN_INV_SEL_M  (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S)
+#define GPIO_FUNC10_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_IN_INV_SEL_S  6
+/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG10_IN_SEL    (BIT(7))
+#define GPIO_SIG10_IN_SEL_M  (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S)
+#define GPIO_SIG10_IN_SEL_V  0x00000001U
+#define GPIO_SIG10_IN_SEL_S  7
+
+/** GPIO_FUNC11_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184)
+/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC11_IN_SEL    0x0000003FU
+#define GPIO_FUNC11_IN_SEL_M  (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S)
+#define GPIO_FUNC11_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC11_IN_SEL_S  0
+/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC11_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC11_IN_INV_SEL_M  (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S)
+#define GPIO_FUNC11_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_IN_INV_SEL_S  6
+/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG11_IN_SEL    (BIT(7))
+#define GPIO_SIG11_IN_SEL_M  (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S)
+#define GPIO_SIG11_IN_SEL_V  0x00000001U
+#define GPIO_SIG11_IN_SEL_S  7
+
+/** GPIO_FUNC12_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188)
+/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC12_IN_SEL    0x0000003FU
+#define GPIO_FUNC12_IN_SEL_M  (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S)
+#define GPIO_FUNC12_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC12_IN_SEL_S  0
+/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC12_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC12_IN_INV_SEL_M  (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S)
+#define GPIO_FUNC12_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_IN_INV_SEL_S  6
+/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG12_IN_SEL    (BIT(7))
+#define GPIO_SIG12_IN_SEL_M  (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S)
+#define GPIO_SIG12_IN_SEL_V  0x00000001U
+#define GPIO_SIG12_IN_SEL_S  7
+
+/** GPIO_FUNC13_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c)
+/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC13_IN_SEL    0x0000003FU
+#define GPIO_FUNC13_IN_SEL_M  (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S)
+#define GPIO_FUNC13_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC13_IN_SEL_S  0
+/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC13_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC13_IN_INV_SEL_M  (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S)
+#define GPIO_FUNC13_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_IN_INV_SEL_S  6
+/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG13_IN_SEL    (BIT(7))
+#define GPIO_SIG13_IN_SEL_M  (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S)
+#define GPIO_SIG13_IN_SEL_V  0x00000001U
+#define GPIO_SIG13_IN_SEL_S  7
+
+/** GPIO_FUNC14_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190)
+/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC14_IN_SEL    0x0000003FU
+#define GPIO_FUNC14_IN_SEL_M  (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S)
+#define GPIO_FUNC14_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC14_IN_SEL_S  0
+/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC14_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC14_IN_INV_SEL_M  (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S)
+#define GPIO_FUNC14_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_IN_INV_SEL_S  6
+/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG14_IN_SEL    (BIT(7))
+#define GPIO_SIG14_IN_SEL_M  (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S)
+#define GPIO_SIG14_IN_SEL_V  0x00000001U
+#define GPIO_SIG14_IN_SEL_S  7
+
+/** GPIO_FUNC15_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194)
+/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC15_IN_SEL    0x0000003FU
+#define GPIO_FUNC15_IN_SEL_M  (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S)
+#define GPIO_FUNC15_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC15_IN_SEL_S  0
+/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC15_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC15_IN_INV_SEL_M  (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S)
+#define GPIO_FUNC15_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_IN_INV_SEL_S  6
+/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG15_IN_SEL    (BIT(7))
+#define GPIO_SIG15_IN_SEL_M  (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S)
+#define GPIO_SIG15_IN_SEL_V  0x00000001U
+#define GPIO_SIG15_IN_SEL_S  7
+
+/** GPIO_FUNC16_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198)
+/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC16_IN_SEL    0x0000003FU
+#define GPIO_FUNC16_IN_SEL_M  (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S)
+#define GPIO_FUNC16_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC16_IN_SEL_S  0
+/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC16_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC16_IN_INV_SEL_M  (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S)
+#define GPIO_FUNC16_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_IN_INV_SEL_S  6
+/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG16_IN_SEL    (BIT(7))
+#define GPIO_SIG16_IN_SEL_M  (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S)
+#define GPIO_SIG16_IN_SEL_V  0x00000001U
+#define GPIO_SIG16_IN_SEL_S  7
+
+/** GPIO_FUNC17_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c)
+/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC17_IN_SEL    0x0000003FU
+#define GPIO_FUNC17_IN_SEL_M  (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S)
+#define GPIO_FUNC17_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC17_IN_SEL_S  0
+/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC17_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC17_IN_INV_SEL_M  (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S)
+#define GPIO_FUNC17_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_IN_INV_SEL_S  6
+/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG17_IN_SEL    (BIT(7))
+#define GPIO_SIG17_IN_SEL_M  (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S)
+#define GPIO_SIG17_IN_SEL_V  0x00000001U
+#define GPIO_SIG17_IN_SEL_S  7
+
+/** GPIO_FUNC18_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0)
+/** GPIO_FUNC18_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC18_IN_SEL    0x0000003FU
+#define GPIO_FUNC18_IN_SEL_M  (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S)
+#define GPIO_FUNC18_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC18_IN_SEL_S  0
+/** GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC18_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC18_IN_INV_SEL_M  (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S)
+#define GPIO_FUNC18_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_IN_INV_SEL_S  6
+/** GPIO_SIG18_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG18_IN_SEL    (BIT(7))
+#define GPIO_SIG18_IN_SEL_M  (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S)
+#define GPIO_SIG18_IN_SEL_V  0x00000001U
+#define GPIO_SIG18_IN_SEL_S  7
+
+/** GPIO_FUNC19_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4)
+/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC19_IN_SEL    0x0000003FU
+#define GPIO_FUNC19_IN_SEL_M  (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S)
+#define GPIO_FUNC19_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC19_IN_SEL_S  0
+/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC19_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC19_IN_INV_SEL_M  (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S)
+#define GPIO_FUNC19_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_IN_INV_SEL_S  6
+/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG19_IN_SEL    (BIT(7))
+#define GPIO_SIG19_IN_SEL_M  (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S)
+#define GPIO_SIG19_IN_SEL_V  0x00000001U
+#define GPIO_SIG19_IN_SEL_S  7
+
+/** GPIO_FUNC20_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8)
+/** GPIO_FUNC20_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC20_IN_SEL    0x0000003FU
+#define GPIO_FUNC20_IN_SEL_M  (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S)
+#define GPIO_FUNC20_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC20_IN_SEL_S  0
+/** GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC20_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC20_IN_INV_SEL_M  (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S)
+#define GPIO_FUNC20_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_IN_INV_SEL_S  6
+/** GPIO_SIG20_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG20_IN_SEL    (BIT(7))
+#define GPIO_SIG20_IN_SEL_M  (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S)
+#define GPIO_SIG20_IN_SEL_V  0x00000001U
+#define GPIO_SIG20_IN_SEL_S  7
+
+/** GPIO_FUNC21_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac)
+/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC21_IN_SEL    0x0000003FU
+#define GPIO_FUNC21_IN_SEL_M  (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S)
+#define GPIO_FUNC21_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC21_IN_SEL_S  0
+/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC21_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC21_IN_INV_SEL_M  (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S)
+#define GPIO_FUNC21_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_IN_INV_SEL_S  6
+/** GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG21_IN_SEL    (BIT(7))
+#define GPIO_SIG21_IN_SEL_M  (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S)
+#define GPIO_SIG21_IN_SEL_V  0x00000001U
+#define GPIO_SIG21_IN_SEL_S  7
+
+/** GPIO_FUNC22_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0)
+/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC22_IN_SEL    0x0000003FU
+#define GPIO_FUNC22_IN_SEL_M  (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S)
+#define GPIO_FUNC22_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC22_IN_SEL_S  0
+/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC22_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC22_IN_INV_SEL_M  (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S)
+#define GPIO_FUNC22_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_IN_INV_SEL_S  6
+/** GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG22_IN_SEL    (BIT(7))
+#define GPIO_SIG22_IN_SEL_M  (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S)
+#define GPIO_SIG22_IN_SEL_V  0x00000001U
+#define GPIO_SIG22_IN_SEL_S  7
+
+/** GPIO_FUNC23_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4)
+/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC23_IN_SEL    0x0000003FU
+#define GPIO_FUNC23_IN_SEL_M  (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S)
+#define GPIO_FUNC23_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC23_IN_SEL_S  0
+/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC23_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC23_IN_INV_SEL_M  (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S)
+#define GPIO_FUNC23_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_IN_INV_SEL_S  6
+/** GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG23_IN_SEL    (BIT(7))
+#define GPIO_SIG23_IN_SEL_M  (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S)
+#define GPIO_SIG23_IN_SEL_V  0x00000001U
+#define GPIO_SIG23_IN_SEL_S  7
+
+/** GPIO_FUNC24_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8)
+/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC24_IN_SEL    0x0000003FU
+#define GPIO_FUNC24_IN_SEL_M  (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S)
+#define GPIO_FUNC24_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC24_IN_SEL_S  0
+/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC24_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC24_IN_INV_SEL_M  (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S)
+#define GPIO_FUNC24_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_IN_INV_SEL_S  6
+/** GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG24_IN_SEL    (BIT(7))
+#define GPIO_SIG24_IN_SEL_M  (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S)
+#define GPIO_SIG24_IN_SEL_V  0x00000001U
+#define GPIO_SIG24_IN_SEL_S  7
+
+/** GPIO_FUNC25_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc)
+/** GPIO_FUNC25_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC25_IN_SEL    0x0000003FU
+#define GPIO_FUNC25_IN_SEL_M  (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S)
+#define GPIO_FUNC25_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC25_IN_SEL_S  0
+/** GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC25_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC25_IN_INV_SEL_M  (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S)
+#define GPIO_FUNC25_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_IN_INV_SEL_S  6
+/** GPIO_SIG25_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG25_IN_SEL    (BIT(7))
+#define GPIO_SIG25_IN_SEL_M  (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S)
+#define GPIO_SIG25_IN_SEL_V  0x00000001U
+#define GPIO_SIG25_IN_SEL_S  7
+
+/** GPIO_FUNC26_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0)
+/** GPIO_FUNC26_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC26_IN_SEL    0x0000003FU
+#define GPIO_FUNC26_IN_SEL_M  (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S)
+#define GPIO_FUNC26_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC26_IN_SEL_S  0
+/** GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC26_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC26_IN_INV_SEL_M  (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S)
+#define GPIO_FUNC26_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_IN_INV_SEL_S  6
+/** GPIO_SIG26_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG26_IN_SEL    (BIT(7))
+#define GPIO_SIG26_IN_SEL_M  (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S)
+#define GPIO_SIG26_IN_SEL_V  0x00000001U
+#define GPIO_SIG26_IN_SEL_S  7
+
+/** GPIO_FUNC27_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4)
+/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC27_IN_SEL    0x0000003FU
+#define GPIO_FUNC27_IN_SEL_M  (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S)
+#define GPIO_FUNC27_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC27_IN_SEL_S  0
+/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC27_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC27_IN_INV_SEL_M  (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S)
+#define GPIO_FUNC27_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_IN_INV_SEL_S  6
+/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG27_IN_SEL    (BIT(7))
+#define GPIO_SIG27_IN_SEL_M  (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S)
+#define GPIO_SIG27_IN_SEL_V  0x00000001U
+#define GPIO_SIG27_IN_SEL_S  7
+
+/** GPIO_FUNC28_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8)
+/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC28_IN_SEL    0x0000003FU
+#define GPIO_FUNC28_IN_SEL_M  (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S)
+#define GPIO_FUNC28_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC28_IN_SEL_S  0
+/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC28_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC28_IN_INV_SEL_M  (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S)
+#define GPIO_FUNC28_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_IN_INV_SEL_S  6
+/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG28_IN_SEL    (BIT(7))
+#define GPIO_SIG28_IN_SEL_M  (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S)
+#define GPIO_SIG28_IN_SEL_V  0x00000001U
+#define GPIO_SIG28_IN_SEL_S  7
+
+/** GPIO_FUNC29_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc)
+/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC29_IN_SEL    0x0000003FU
+#define GPIO_FUNC29_IN_SEL_M  (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S)
+#define GPIO_FUNC29_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC29_IN_SEL_S  0
+/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC29_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC29_IN_INV_SEL_M  (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S)
+#define GPIO_FUNC29_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_IN_INV_SEL_S  6
+/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG29_IN_SEL    (BIT(7))
+#define GPIO_SIG29_IN_SEL_M  (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S)
+#define GPIO_SIG29_IN_SEL_V  0x00000001U
+#define GPIO_SIG29_IN_SEL_S  7
+
+/** GPIO_FUNC30_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0)
+/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC30_IN_SEL    0x0000003FU
+#define GPIO_FUNC30_IN_SEL_M  (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S)
+#define GPIO_FUNC30_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC30_IN_SEL_S  0
+/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC30_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC30_IN_INV_SEL_M  (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S)
+#define GPIO_FUNC30_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_IN_INV_SEL_S  6
+/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG30_IN_SEL    (BIT(7))
+#define GPIO_SIG30_IN_SEL_M  (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S)
+#define GPIO_SIG30_IN_SEL_V  0x00000001U
+#define GPIO_SIG30_IN_SEL_S  7
+
+/** GPIO_FUNC31_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4)
+/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC31_IN_SEL    0x0000003FU
+#define GPIO_FUNC31_IN_SEL_M  (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S)
+#define GPIO_FUNC31_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC31_IN_SEL_S  0
+/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC31_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC31_IN_INV_SEL_M  (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S)
+#define GPIO_FUNC31_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_IN_INV_SEL_S  6
+/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG31_IN_SEL    (BIT(7))
+#define GPIO_SIG31_IN_SEL_M  (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S)
+#define GPIO_SIG31_IN_SEL_V  0x00000001U
+#define GPIO_SIG31_IN_SEL_S  7
+
+/** GPIO_FUNC32_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8)
+/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC32_IN_SEL    0x0000003FU
+#define GPIO_FUNC32_IN_SEL_M  (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S)
+#define GPIO_FUNC32_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC32_IN_SEL_S  0
+/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC32_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC32_IN_INV_SEL_M  (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S)
+#define GPIO_FUNC32_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_IN_INV_SEL_S  6
+/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG32_IN_SEL    (BIT(7))
+#define GPIO_SIG32_IN_SEL_M  (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S)
+#define GPIO_SIG32_IN_SEL_V  0x00000001U
+#define GPIO_SIG32_IN_SEL_S  7
+
+/** GPIO_FUNC33_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc)
+/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC33_IN_SEL    0x0000003FU
+#define GPIO_FUNC33_IN_SEL_M  (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S)
+#define GPIO_FUNC33_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC33_IN_SEL_S  0
+/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC33_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC33_IN_INV_SEL_M  (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S)
+#define GPIO_FUNC33_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_IN_INV_SEL_S  6
+/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG33_IN_SEL    (BIT(7))
+#define GPIO_SIG33_IN_SEL_M  (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S)
+#define GPIO_SIG33_IN_SEL_V  0x00000001U
+#define GPIO_SIG33_IN_SEL_S  7
+
+/** GPIO_FUNC34_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0)
+/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC34_IN_SEL    0x0000003FU
+#define GPIO_FUNC34_IN_SEL_M  (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S)
+#define GPIO_FUNC34_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC34_IN_SEL_S  0
+/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC34_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC34_IN_INV_SEL_M  (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S)
+#define GPIO_FUNC34_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_IN_INV_SEL_S  6
+/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG34_IN_SEL    (BIT(7))
+#define GPIO_SIG34_IN_SEL_M  (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S)
+#define GPIO_SIG34_IN_SEL_V  0x00000001U
+#define GPIO_SIG34_IN_SEL_S  7
+
+/** GPIO_FUNC35_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4)
+/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC35_IN_SEL    0x0000003FU
+#define GPIO_FUNC35_IN_SEL_M  (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S)
+#define GPIO_FUNC35_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC35_IN_SEL_S  0
+/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC35_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC35_IN_INV_SEL_M  (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S)
+#define GPIO_FUNC35_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_IN_INV_SEL_S  6
+/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG35_IN_SEL    (BIT(7))
+#define GPIO_SIG35_IN_SEL_M  (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S)
+#define GPIO_SIG35_IN_SEL_V  0x00000001U
+#define GPIO_SIG35_IN_SEL_S  7
+
+/** GPIO_FUNC36_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8)
+/** GPIO_FUNC36_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC36_IN_SEL    0x0000003FU
+#define GPIO_FUNC36_IN_SEL_M  (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S)
+#define GPIO_FUNC36_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC36_IN_SEL_S  0
+/** GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC36_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC36_IN_INV_SEL_M  (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S)
+#define GPIO_FUNC36_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_IN_INV_SEL_S  6
+/** GPIO_SIG36_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG36_IN_SEL    (BIT(7))
+#define GPIO_SIG36_IN_SEL_M  (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S)
+#define GPIO_SIG36_IN_SEL_V  0x00000001U
+#define GPIO_SIG36_IN_SEL_S  7
+
+/** GPIO_FUNC37_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec)
+/** GPIO_FUNC37_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC37_IN_SEL    0x0000003FU
+#define GPIO_FUNC37_IN_SEL_M  (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S)
+#define GPIO_FUNC37_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC37_IN_SEL_S  0
+/** GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC37_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC37_IN_INV_SEL_M  (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S)
+#define GPIO_FUNC37_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_IN_INV_SEL_S  6
+/** GPIO_SIG37_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG37_IN_SEL    (BIT(7))
+#define GPIO_SIG37_IN_SEL_M  (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S)
+#define GPIO_SIG37_IN_SEL_V  0x00000001U
+#define GPIO_SIG37_IN_SEL_S  7
+
+/** GPIO_FUNC38_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0)
+/** GPIO_FUNC38_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC38_IN_SEL    0x0000003FU
+#define GPIO_FUNC38_IN_SEL_M  (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S)
+#define GPIO_FUNC38_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC38_IN_SEL_S  0
+/** GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC38_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC38_IN_INV_SEL_M  (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S)
+#define GPIO_FUNC38_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_IN_INV_SEL_S  6
+/** GPIO_SIG38_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG38_IN_SEL    (BIT(7))
+#define GPIO_SIG38_IN_SEL_M  (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S)
+#define GPIO_SIG38_IN_SEL_V  0x00000001U
+#define GPIO_SIG38_IN_SEL_S  7
+
+/** GPIO_FUNC39_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4)
+/** GPIO_FUNC39_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC39_IN_SEL    0x0000003FU
+#define GPIO_FUNC39_IN_SEL_M  (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S)
+#define GPIO_FUNC39_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC39_IN_SEL_S  0
+/** GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC39_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC39_IN_INV_SEL_M  (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S)
+#define GPIO_FUNC39_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_IN_INV_SEL_S  6
+/** GPIO_SIG39_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG39_IN_SEL    (BIT(7))
+#define GPIO_SIG39_IN_SEL_M  (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S)
+#define GPIO_SIG39_IN_SEL_V  0x00000001U
+#define GPIO_SIG39_IN_SEL_S  7
+
+/** GPIO_FUNC40_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8)
+/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC40_IN_SEL    0x0000003FU
+#define GPIO_FUNC40_IN_SEL_M  (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S)
+#define GPIO_FUNC40_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC40_IN_SEL_S  0
+/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC40_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC40_IN_INV_SEL_M  (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S)
+#define GPIO_FUNC40_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_IN_INV_SEL_S  6
+/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG40_IN_SEL    (BIT(7))
+#define GPIO_SIG40_IN_SEL_M  (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S)
+#define GPIO_SIG40_IN_SEL_V  0x00000001U
+#define GPIO_SIG40_IN_SEL_S  7
+
+/** GPIO_FUNC41_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc)
+/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC41_IN_SEL    0x0000003FU
+#define GPIO_FUNC41_IN_SEL_M  (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S)
+#define GPIO_FUNC41_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC41_IN_SEL_S  0
+/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC41_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC41_IN_INV_SEL_M  (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S)
+#define GPIO_FUNC41_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_IN_INV_SEL_S  6
+/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG41_IN_SEL    (BIT(7))
+#define GPIO_SIG41_IN_SEL_M  (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S)
+#define GPIO_SIG41_IN_SEL_V  0x00000001U
+#define GPIO_SIG41_IN_SEL_S  7
+
+/** GPIO_FUNC42_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200)
+/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC42_IN_SEL    0x0000003FU
+#define GPIO_FUNC42_IN_SEL_M  (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S)
+#define GPIO_FUNC42_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC42_IN_SEL_S  0
+/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC42_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC42_IN_INV_SEL_M  (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S)
+#define GPIO_FUNC42_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_IN_INV_SEL_S  6
+/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG42_IN_SEL    (BIT(7))
+#define GPIO_SIG42_IN_SEL_M  (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S)
+#define GPIO_SIG42_IN_SEL_V  0x00000001U
+#define GPIO_SIG42_IN_SEL_S  7
+
+/** GPIO_FUNC43_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204)
+/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC43_IN_SEL    0x0000003FU
+#define GPIO_FUNC43_IN_SEL_M  (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S)
+#define GPIO_FUNC43_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC43_IN_SEL_S  0
+/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC43_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC43_IN_INV_SEL_M  (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S)
+#define GPIO_FUNC43_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_IN_INV_SEL_S  6
+/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG43_IN_SEL    (BIT(7))
+#define GPIO_SIG43_IN_SEL_M  (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S)
+#define GPIO_SIG43_IN_SEL_V  0x00000001U
+#define GPIO_SIG43_IN_SEL_S  7
+
+/** GPIO_FUNC44_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208)
+/** GPIO_FUNC44_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC44_IN_SEL    0x0000003FU
+#define GPIO_FUNC44_IN_SEL_M  (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S)
+#define GPIO_FUNC44_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC44_IN_SEL_S  0
+/** GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC44_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC44_IN_INV_SEL_M  (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S)
+#define GPIO_FUNC44_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_IN_INV_SEL_S  6
+/** GPIO_SIG44_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG44_IN_SEL    (BIT(7))
+#define GPIO_SIG44_IN_SEL_M  (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S)
+#define GPIO_SIG44_IN_SEL_V  0x00000001U
+#define GPIO_SIG44_IN_SEL_S  7
+
+/** GPIO_FUNC45_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c)
+/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC45_IN_SEL    0x0000003FU
+#define GPIO_FUNC45_IN_SEL_M  (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S)
+#define GPIO_FUNC45_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC45_IN_SEL_S  0
+/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC45_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC45_IN_INV_SEL_M  (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S)
+#define GPIO_FUNC45_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_IN_INV_SEL_S  6
+/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG45_IN_SEL    (BIT(7))
+#define GPIO_SIG45_IN_SEL_M  (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S)
+#define GPIO_SIG45_IN_SEL_V  0x00000001U
+#define GPIO_SIG45_IN_SEL_S  7
+
+/** GPIO_FUNC47_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214)
+/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC47_IN_SEL    0x0000003FU
+#define GPIO_FUNC47_IN_SEL_M  (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S)
+#define GPIO_FUNC47_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC47_IN_SEL_S  0
+/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC47_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC47_IN_INV_SEL_M  (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S)
+#define GPIO_FUNC47_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_IN_INV_SEL_S  6
+/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG47_IN_SEL    (BIT(7))
+#define GPIO_SIG47_IN_SEL_M  (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S)
+#define GPIO_SIG47_IN_SEL_V  0x00000001U
+#define GPIO_SIG47_IN_SEL_S  7
+
+/** GPIO_FUNC48_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218)
+/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC48_IN_SEL    0x0000003FU
+#define GPIO_FUNC48_IN_SEL_M  (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S)
+#define GPIO_FUNC48_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC48_IN_SEL_S  0
+/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC48_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC48_IN_INV_SEL_M  (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S)
+#define GPIO_FUNC48_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_IN_INV_SEL_S  6
+/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG48_IN_SEL    (BIT(7))
+#define GPIO_SIG48_IN_SEL_M  (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S)
+#define GPIO_SIG48_IN_SEL_V  0x00000001U
+#define GPIO_SIG48_IN_SEL_S  7
+
+/** GPIO_FUNC49_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c)
+/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC49_IN_SEL    0x0000003FU
+#define GPIO_FUNC49_IN_SEL_M  (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S)
+#define GPIO_FUNC49_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC49_IN_SEL_S  0
+/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC49_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC49_IN_INV_SEL_M  (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S)
+#define GPIO_FUNC49_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_IN_INV_SEL_S  6
+/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG49_IN_SEL    (BIT(7))
+#define GPIO_SIG49_IN_SEL_M  (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S)
+#define GPIO_SIG49_IN_SEL_V  0x00000001U
+#define GPIO_SIG49_IN_SEL_S  7
+
+/** GPIO_FUNC50_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220)
+/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC50_IN_SEL    0x0000003FU
+#define GPIO_FUNC50_IN_SEL_M  (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S)
+#define GPIO_FUNC50_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC50_IN_SEL_S  0
+/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC50_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC50_IN_INV_SEL_M  (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S)
+#define GPIO_FUNC50_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_IN_INV_SEL_S  6
+/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG50_IN_SEL    (BIT(7))
+#define GPIO_SIG50_IN_SEL_M  (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S)
+#define GPIO_SIG50_IN_SEL_V  0x00000001U
+#define GPIO_SIG50_IN_SEL_S  7
+
+/** GPIO_FUNC51_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224)
+/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC51_IN_SEL    0x0000003FU
+#define GPIO_FUNC51_IN_SEL_M  (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S)
+#define GPIO_FUNC51_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC51_IN_SEL_S  0
+/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC51_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC51_IN_INV_SEL_M  (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S)
+#define GPIO_FUNC51_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_IN_INV_SEL_S  6
+/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG51_IN_SEL    (BIT(7))
+#define GPIO_SIG51_IN_SEL_M  (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S)
+#define GPIO_SIG51_IN_SEL_V  0x00000001U
+#define GPIO_SIG51_IN_SEL_S  7
+
+/** GPIO_FUNC52_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228)
+/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC52_IN_SEL    0x0000003FU
+#define GPIO_FUNC52_IN_SEL_M  (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S)
+#define GPIO_FUNC52_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC52_IN_SEL_S  0
+/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC52_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC52_IN_INV_SEL_M  (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S)
+#define GPIO_FUNC52_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_IN_INV_SEL_S  6
+/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG52_IN_SEL    (BIT(7))
+#define GPIO_SIG52_IN_SEL_M  (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S)
+#define GPIO_SIG52_IN_SEL_V  0x00000001U
+#define GPIO_SIG52_IN_SEL_S  7
+
+/** GPIO_FUNC53_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c)
+/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC53_IN_SEL    0x0000003FU
+#define GPIO_FUNC53_IN_SEL_M  (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S)
+#define GPIO_FUNC53_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC53_IN_SEL_S  0
+/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC53_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC53_IN_INV_SEL_M  (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S)
+#define GPIO_FUNC53_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_IN_INV_SEL_S  6
+/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG53_IN_SEL    (BIT(7))
+#define GPIO_SIG53_IN_SEL_M  (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S)
+#define GPIO_SIG53_IN_SEL_V  0x00000001U
+#define GPIO_SIG53_IN_SEL_S  7
+
+/** GPIO_FUNC54_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230)
+/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC54_IN_SEL    0x0000003FU
+#define GPIO_FUNC54_IN_SEL_M  (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S)
+#define GPIO_FUNC54_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC54_IN_SEL_S  0
+/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC54_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC54_IN_INV_SEL_M  (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S)
+#define GPIO_FUNC54_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_IN_INV_SEL_S  6
+/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG54_IN_SEL    (BIT(7))
+#define GPIO_SIG54_IN_SEL_M  (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S)
+#define GPIO_SIG54_IN_SEL_V  0x00000001U
+#define GPIO_SIG54_IN_SEL_S  7
+
+/** GPIO_FUNC55_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234)
+/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC55_IN_SEL    0x0000003FU
+#define GPIO_FUNC55_IN_SEL_M  (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S)
+#define GPIO_FUNC55_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC55_IN_SEL_S  0
+/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC55_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC55_IN_INV_SEL_M  (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S)
+#define GPIO_FUNC55_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_IN_INV_SEL_S  6
+/** GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG55_IN_SEL    (BIT(7))
+#define GPIO_SIG55_IN_SEL_M  (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S)
+#define GPIO_SIG55_IN_SEL_V  0x00000001U
+#define GPIO_SIG55_IN_SEL_S  7
+
+/** GPIO_FUNC56_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238)
+/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC56_IN_SEL    0x0000003FU
+#define GPIO_FUNC56_IN_SEL_M  (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S)
+#define GPIO_FUNC56_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC56_IN_SEL_S  0
+/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC56_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC56_IN_INV_SEL_M  (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S)
+#define GPIO_FUNC56_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_IN_INV_SEL_S  6
+/** GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG56_IN_SEL    (BIT(7))
+#define GPIO_SIG56_IN_SEL_M  (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S)
+#define GPIO_SIG56_IN_SEL_V  0x00000001U
+#define GPIO_SIG56_IN_SEL_S  7
+
+/** GPIO_FUNC57_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c)
+/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC57_IN_SEL    0x0000003FU
+#define GPIO_FUNC57_IN_SEL_M  (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S)
+#define GPIO_FUNC57_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC57_IN_SEL_S  0
+/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC57_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC57_IN_INV_SEL_M  (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S)
+#define GPIO_FUNC57_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC57_IN_INV_SEL_S  6
+/** GPIO_SIG57_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG57_IN_SEL    (BIT(7))
+#define GPIO_SIG57_IN_SEL_M  (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S)
+#define GPIO_SIG57_IN_SEL_V  0x00000001U
+#define GPIO_SIG57_IN_SEL_S  7
+
+/** GPIO_FUNC58_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240)
+/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC58_IN_SEL    0x0000003FU
+#define GPIO_FUNC58_IN_SEL_M  (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S)
+#define GPIO_FUNC58_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC58_IN_SEL_S  0
+/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC58_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC58_IN_INV_SEL_M  (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S)
+#define GPIO_FUNC58_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC58_IN_INV_SEL_S  6
+/** GPIO_SIG58_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG58_IN_SEL    (BIT(7))
+#define GPIO_SIG58_IN_SEL_M  (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S)
+#define GPIO_SIG58_IN_SEL_V  0x00000001U
+#define GPIO_SIG58_IN_SEL_S  7
+
+/** GPIO_FUNC59_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244)
+/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC59_IN_SEL    0x0000003FU
+#define GPIO_FUNC59_IN_SEL_M  (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S)
+#define GPIO_FUNC59_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC59_IN_SEL_S  0
+/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC59_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC59_IN_INV_SEL_M  (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S)
+#define GPIO_FUNC59_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC59_IN_INV_SEL_S  6
+/** GPIO_SIG59_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG59_IN_SEL    (BIT(7))
+#define GPIO_SIG59_IN_SEL_M  (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S)
+#define GPIO_SIG59_IN_SEL_V  0x00000001U
+#define GPIO_SIG59_IN_SEL_S  7
+
+/** GPIO_FUNC60_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248)
+/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC60_IN_SEL    0x0000003FU
+#define GPIO_FUNC60_IN_SEL_M  (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S)
+#define GPIO_FUNC60_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC60_IN_SEL_S  0
+/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC60_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC60_IN_INV_SEL_M  (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S)
+#define GPIO_FUNC60_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC60_IN_INV_SEL_S  6
+/** GPIO_SIG60_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG60_IN_SEL    (BIT(7))
+#define GPIO_SIG60_IN_SEL_M  (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S)
+#define GPIO_SIG60_IN_SEL_V  0x00000001U
+#define GPIO_SIG60_IN_SEL_S  7
+
+/** GPIO_FUNC61_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c)
+/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC61_IN_SEL    0x0000003FU
+#define GPIO_FUNC61_IN_SEL_M  (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S)
+#define GPIO_FUNC61_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC61_IN_SEL_S  0
+/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC61_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC61_IN_INV_SEL_M  (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S)
+#define GPIO_FUNC61_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC61_IN_INV_SEL_S  6
+/** GPIO_SIG61_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG61_IN_SEL    (BIT(7))
+#define GPIO_SIG61_IN_SEL_M  (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S)
+#define GPIO_SIG61_IN_SEL_V  0x00000001U
+#define GPIO_SIG61_IN_SEL_S  7
+
+/** GPIO_FUNC62_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250)
+/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC62_IN_SEL    0x0000003FU
+#define GPIO_FUNC62_IN_SEL_M  (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S)
+#define GPIO_FUNC62_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC62_IN_SEL_S  0
+/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC62_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC62_IN_INV_SEL_M  (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S)
+#define GPIO_FUNC62_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC62_IN_INV_SEL_S  6
+/** GPIO_SIG62_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG62_IN_SEL    (BIT(7))
+#define GPIO_SIG62_IN_SEL_M  (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S)
+#define GPIO_SIG62_IN_SEL_V  0x00000001U
+#define GPIO_SIG62_IN_SEL_S  7
+
+/** GPIO_FUNC63_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254)
+/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC63_IN_SEL    0x0000003FU
+#define GPIO_FUNC63_IN_SEL_M  (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S)
+#define GPIO_FUNC63_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC63_IN_SEL_S  0
+/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC63_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC63_IN_INV_SEL_M  (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S)
+#define GPIO_FUNC63_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC63_IN_INV_SEL_S  6
+/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG63_IN_SEL    (BIT(7))
+#define GPIO_SIG63_IN_SEL_M  (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S)
+#define GPIO_SIG63_IN_SEL_V  0x00000001U
+#define GPIO_SIG63_IN_SEL_S  7
+
+/** GPIO_FUNC64_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258)
+/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC64_IN_SEL    0x0000003FU
+#define GPIO_FUNC64_IN_SEL_M  (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S)
+#define GPIO_FUNC64_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC64_IN_SEL_S  0
+/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC64_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC64_IN_INV_SEL_M  (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S)
+#define GPIO_FUNC64_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC64_IN_INV_SEL_S  6
+/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG64_IN_SEL    (BIT(7))
+#define GPIO_SIG64_IN_SEL_M  (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S)
+#define GPIO_SIG64_IN_SEL_V  0x00000001U
+#define GPIO_SIG64_IN_SEL_S  7
+
+/** GPIO_FUNC65_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c)
+/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC65_IN_SEL    0x0000003FU
+#define GPIO_FUNC65_IN_SEL_M  (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S)
+#define GPIO_FUNC65_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC65_IN_SEL_S  0
+/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC65_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC65_IN_INV_SEL_M  (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S)
+#define GPIO_FUNC65_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC65_IN_INV_SEL_S  6
+/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG65_IN_SEL    (BIT(7))
+#define GPIO_SIG65_IN_SEL_M  (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S)
+#define GPIO_SIG65_IN_SEL_V  0x00000001U
+#define GPIO_SIG65_IN_SEL_S  7
+
+/** GPIO_FUNC66_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260)
+/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC66_IN_SEL    0x0000003FU
+#define GPIO_FUNC66_IN_SEL_M  (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S)
+#define GPIO_FUNC66_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC66_IN_SEL_S  0
+/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC66_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC66_IN_INV_SEL_M  (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S)
+#define GPIO_FUNC66_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC66_IN_INV_SEL_S  6
+/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG66_IN_SEL    (BIT(7))
+#define GPIO_SIG66_IN_SEL_M  (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S)
+#define GPIO_SIG66_IN_SEL_V  0x00000001U
+#define GPIO_SIG66_IN_SEL_S  7
+
+/** GPIO_FUNC68_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268)
+/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC68_IN_SEL    0x0000003FU
+#define GPIO_FUNC68_IN_SEL_M  (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S)
+#define GPIO_FUNC68_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC68_IN_SEL_S  0
+/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC68_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC68_IN_INV_SEL_M  (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S)
+#define GPIO_FUNC68_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC68_IN_INV_SEL_S  6
+/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG68_IN_SEL    (BIT(7))
+#define GPIO_SIG68_IN_SEL_M  (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S)
+#define GPIO_SIG68_IN_SEL_V  0x00000001U
+#define GPIO_SIG68_IN_SEL_S  7
+
+/** GPIO_FUNC69_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c)
+/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC69_IN_SEL    0x0000003FU
+#define GPIO_FUNC69_IN_SEL_M  (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S)
+#define GPIO_FUNC69_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC69_IN_SEL_S  0
+/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC69_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC69_IN_INV_SEL_M  (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S)
+#define GPIO_FUNC69_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC69_IN_INV_SEL_S  6
+/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG69_IN_SEL    (BIT(7))
+#define GPIO_SIG69_IN_SEL_M  (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S)
+#define GPIO_SIG69_IN_SEL_V  0x00000001U
+#define GPIO_SIG69_IN_SEL_S  7
+
+/** GPIO_FUNC70_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270)
+/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC70_IN_SEL    0x0000003FU
+#define GPIO_FUNC70_IN_SEL_M  (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S)
+#define GPIO_FUNC70_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC70_IN_SEL_S  0
+/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC70_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC70_IN_INV_SEL_M  (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S)
+#define GPIO_FUNC70_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC70_IN_INV_SEL_S  6
+/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG70_IN_SEL    (BIT(7))
+#define GPIO_SIG70_IN_SEL_M  (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S)
+#define GPIO_SIG70_IN_SEL_V  0x00000001U
+#define GPIO_SIG70_IN_SEL_S  7
+
+/** GPIO_FUNC71_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274)
+/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC71_IN_SEL    0x0000003FU
+#define GPIO_FUNC71_IN_SEL_M  (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S)
+#define GPIO_FUNC71_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC71_IN_SEL_S  0
+/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC71_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC71_IN_INV_SEL_M  (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S)
+#define GPIO_FUNC71_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC71_IN_INV_SEL_S  6
+/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG71_IN_SEL    (BIT(7))
+#define GPIO_SIG71_IN_SEL_M  (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S)
+#define GPIO_SIG71_IN_SEL_V  0x00000001U
+#define GPIO_SIG71_IN_SEL_S  7
+
+/** GPIO_FUNC74_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280)
+/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC74_IN_SEL    0x0000003FU
+#define GPIO_FUNC74_IN_SEL_M  (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S)
+#define GPIO_FUNC74_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC74_IN_SEL_S  0
+/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC74_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC74_IN_INV_SEL_M  (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S)
+#define GPIO_FUNC74_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC74_IN_INV_SEL_S  6
+/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG74_IN_SEL    (BIT(7))
+#define GPIO_SIG74_IN_SEL_M  (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S)
+#define GPIO_SIG74_IN_SEL_V  0x00000001U
+#define GPIO_SIG74_IN_SEL_S  7
+
+/** GPIO_FUNC75_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284)
+/** GPIO_FUNC75_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC75_IN_SEL    0x0000003FU
+#define GPIO_FUNC75_IN_SEL_M  (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S)
+#define GPIO_FUNC75_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC75_IN_SEL_S  0
+/** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC75_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC75_IN_INV_SEL_M  (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S)
+#define GPIO_FUNC75_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC75_IN_INV_SEL_S  6
+/** GPIO_SIG75_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG75_IN_SEL    (BIT(7))
+#define GPIO_SIG75_IN_SEL_M  (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S)
+#define GPIO_SIG75_IN_SEL_V  0x00000001U
+#define GPIO_SIG75_IN_SEL_S  7
+
+/** GPIO_FUNC76_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288)
+/** GPIO_FUNC76_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC76_IN_SEL    0x0000003FU
+#define GPIO_FUNC76_IN_SEL_M  (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S)
+#define GPIO_FUNC76_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC76_IN_SEL_S  0
+/** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC76_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC76_IN_INV_SEL_M  (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S)
+#define GPIO_FUNC76_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC76_IN_INV_SEL_S  6
+/** GPIO_SIG76_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG76_IN_SEL    (BIT(7))
+#define GPIO_SIG76_IN_SEL_M  (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S)
+#define GPIO_SIG76_IN_SEL_V  0x00000001U
+#define GPIO_SIG76_IN_SEL_S  7
+
+/** GPIO_FUNC77_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c)
+/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC77_IN_SEL    0x0000003FU
+#define GPIO_FUNC77_IN_SEL_M  (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S)
+#define GPIO_FUNC77_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC77_IN_SEL_S  0
+/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC77_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC77_IN_INV_SEL_M  (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S)
+#define GPIO_FUNC77_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC77_IN_INV_SEL_S  6
+/** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG77_IN_SEL    (BIT(7))
+#define GPIO_SIG77_IN_SEL_M  (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S)
+#define GPIO_SIG77_IN_SEL_V  0x00000001U
+#define GPIO_SIG77_IN_SEL_S  7
+
+/** GPIO_FUNC78_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290)
+/** GPIO_FUNC78_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC78_IN_SEL    0x0000003FU
+#define GPIO_FUNC78_IN_SEL_M  (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S)
+#define GPIO_FUNC78_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC78_IN_SEL_S  0
+/** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC78_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC78_IN_INV_SEL_M  (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S)
+#define GPIO_FUNC78_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC78_IN_INV_SEL_S  6
+/** GPIO_SIG78_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG78_IN_SEL    (BIT(7))
+#define GPIO_SIG78_IN_SEL_M  (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S)
+#define GPIO_SIG78_IN_SEL_V  0x00000001U
+#define GPIO_SIG78_IN_SEL_S  7
+
+/** GPIO_FUNC80_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298)
+/** GPIO_FUNC80_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC80_IN_SEL    0x0000003FU
+#define GPIO_FUNC80_IN_SEL_M  (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S)
+#define GPIO_FUNC80_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC80_IN_SEL_S  0
+/** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC80_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC80_IN_INV_SEL_M  (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S)
+#define GPIO_FUNC80_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC80_IN_INV_SEL_S  6
+/** GPIO_SIG80_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG80_IN_SEL    (BIT(7))
+#define GPIO_SIG80_IN_SEL_M  (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S)
+#define GPIO_SIG80_IN_SEL_V  0x00000001U
+#define GPIO_SIG80_IN_SEL_S  7
+
+/** GPIO_FUNC83_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4)
+/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC83_IN_SEL    0x0000003FU
+#define GPIO_FUNC83_IN_SEL_M  (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S)
+#define GPIO_FUNC83_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC83_IN_SEL_S  0
+/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC83_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC83_IN_INV_SEL_M  (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S)
+#define GPIO_FUNC83_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC83_IN_INV_SEL_S  6
+/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG83_IN_SEL    (BIT(7))
+#define GPIO_SIG83_IN_SEL_M  (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S)
+#define GPIO_SIG83_IN_SEL_V  0x00000001U
+#define GPIO_SIG83_IN_SEL_S  7
+
+/** GPIO_FUNC86_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0)
+/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC86_IN_SEL    0x0000003FU
+#define GPIO_FUNC86_IN_SEL_M  (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S)
+#define GPIO_FUNC86_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC86_IN_SEL_S  0
+/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC86_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC86_IN_INV_SEL_M  (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S)
+#define GPIO_FUNC86_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC86_IN_INV_SEL_S  6
+/** GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG86_IN_SEL    (BIT(7))
+#define GPIO_SIG86_IN_SEL_M  (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S)
+#define GPIO_SIG86_IN_SEL_V  0x00000001U
+#define GPIO_SIG86_IN_SEL_S  7
+
+/** GPIO_FUNC89_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc)
+/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC89_IN_SEL    0x0000003FU
+#define GPIO_FUNC89_IN_SEL_M  (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S)
+#define GPIO_FUNC89_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC89_IN_SEL_S  0
+/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC89_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC89_IN_INV_SEL_M  (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S)
+#define GPIO_FUNC89_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC89_IN_INV_SEL_S  6
+/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG89_IN_SEL    (BIT(7))
+#define GPIO_SIG89_IN_SEL_M  (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S)
+#define GPIO_SIG89_IN_SEL_V  0x00000001U
+#define GPIO_SIG89_IN_SEL_S  7
+
+/** GPIO_FUNC90_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0)
+/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC90_IN_SEL    0x0000003FU
+#define GPIO_FUNC90_IN_SEL_M  (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S)
+#define GPIO_FUNC90_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC90_IN_SEL_S  0
+/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC90_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC90_IN_INV_SEL_M  (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S)
+#define GPIO_FUNC90_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC90_IN_INV_SEL_S  6
+/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG90_IN_SEL    (BIT(7))
+#define GPIO_SIG90_IN_SEL_M  (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S)
+#define GPIO_SIG90_IN_SEL_V  0x00000001U
+#define GPIO_SIG90_IN_SEL_S  7
+
+/** GPIO_FUNC91_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4)
+/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC91_IN_SEL    0x0000003FU
+#define GPIO_FUNC91_IN_SEL_M  (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S)
+#define GPIO_FUNC91_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC91_IN_SEL_S  0
+/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC91_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC91_IN_INV_SEL_M  (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S)
+#define GPIO_FUNC91_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC91_IN_INV_SEL_S  6
+/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG91_IN_SEL    (BIT(7))
+#define GPIO_SIG91_IN_SEL_M  (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S)
+#define GPIO_SIG91_IN_SEL_V  0x00000001U
+#define GPIO_SIG91_IN_SEL_S  7
+
+/** GPIO_FUNC92_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8)
+/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC92_IN_SEL    0x0000003FU
+#define GPIO_FUNC92_IN_SEL_M  (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S)
+#define GPIO_FUNC92_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC92_IN_SEL_S  0
+/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC92_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC92_IN_INV_SEL_M  (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S)
+#define GPIO_FUNC92_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC92_IN_INV_SEL_S  6
+/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG92_IN_SEL    (BIT(7))
+#define GPIO_SIG92_IN_SEL_M  (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S)
+#define GPIO_SIG92_IN_SEL_V  0x00000001U
+#define GPIO_SIG92_IN_SEL_S  7
+
+/** GPIO_FUNC93_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc)
+/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC93_IN_SEL    0x0000003FU
+#define GPIO_FUNC93_IN_SEL_M  (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S)
+#define GPIO_FUNC93_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC93_IN_SEL_S  0
+/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC93_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC93_IN_INV_SEL_M  (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S)
+#define GPIO_FUNC93_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC93_IN_INV_SEL_S  6
+/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG93_IN_SEL    (BIT(7))
+#define GPIO_SIG93_IN_SEL_M  (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S)
+#define GPIO_SIG93_IN_SEL_V  0x00000001U
+#define GPIO_SIG93_IN_SEL_S  7
+
+/** GPIO_FUNC94_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0)
+/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC94_IN_SEL    0x0000003FU
+#define GPIO_FUNC94_IN_SEL_M  (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S)
+#define GPIO_FUNC94_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC94_IN_SEL_S  0
+/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC94_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC94_IN_INV_SEL_M  (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S)
+#define GPIO_FUNC94_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC94_IN_INV_SEL_S  6
+/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG94_IN_SEL    (BIT(7))
+#define GPIO_SIG94_IN_SEL_M  (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S)
+#define GPIO_SIG94_IN_SEL_V  0x00000001U
+#define GPIO_SIG94_IN_SEL_S  7
+
+/** GPIO_FUNC95_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4)
+/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC95_IN_SEL    0x0000003FU
+#define GPIO_FUNC95_IN_SEL_M  (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S)
+#define GPIO_FUNC95_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC95_IN_SEL_S  0
+/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC95_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC95_IN_INV_SEL_M  (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S)
+#define GPIO_FUNC95_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC95_IN_INV_SEL_S  6
+/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG95_IN_SEL    (BIT(7))
+#define GPIO_SIG95_IN_SEL_M  (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S)
+#define GPIO_SIG95_IN_SEL_V  0x00000001U
+#define GPIO_SIG95_IN_SEL_S  7
+
+/** GPIO_FUNC96_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8)
+/** GPIO_FUNC96_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC96_IN_SEL    0x0000003FU
+#define GPIO_FUNC96_IN_SEL_M  (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S)
+#define GPIO_FUNC96_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC96_IN_SEL_S  0
+/** GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC96_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC96_IN_INV_SEL_M  (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S)
+#define GPIO_FUNC96_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC96_IN_INV_SEL_S  6
+/** GPIO_SIG96_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG96_IN_SEL    (BIT(7))
+#define GPIO_SIG96_IN_SEL_M  (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S)
+#define GPIO_SIG96_IN_SEL_V  0x00000001U
+#define GPIO_SIG96_IN_SEL_S  7
+
+/** GPIO_FUNC97_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc)
+/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC97_IN_SEL    0x0000003FU
+#define GPIO_FUNC97_IN_SEL_M  (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S)
+#define GPIO_FUNC97_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC97_IN_SEL_S  0
+/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC97_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC97_IN_INV_SEL_M  (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S)
+#define GPIO_FUNC97_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC97_IN_INV_SEL_S  6
+/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG97_IN_SEL    (BIT(7))
+#define GPIO_SIG97_IN_SEL_M  (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S)
+#define GPIO_SIG97_IN_SEL_V  0x00000001U
+#define GPIO_SIG97_IN_SEL_S  7
+
+/** GPIO_FUNC98_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0)
+/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC98_IN_SEL    0x0000003FU
+#define GPIO_FUNC98_IN_SEL_M  (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S)
+#define GPIO_FUNC98_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC98_IN_SEL_S  0
+/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC98_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC98_IN_INV_SEL_M  (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S)
+#define GPIO_FUNC98_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC98_IN_INV_SEL_S  6
+/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG98_IN_SEL    (BIT(7))
+#define GPIO_SIG98_IN_SEL_M  (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S)
+#define GPIO_SIG98_IN_SEL_V  0x00000001U
+#define GPIO_SIG98_IN_SEL_S  7
+
+/** GPIO_FUNC99_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4)
+/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC99_IN_SEL    0x0000003FU
+#define GPIO_FUNC99_IN_SEL_M  (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S)
+#define GPIO_FUNC99_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC99_IN_SEL_S  0
+/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC99_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC99_IN_INV_SEL_M  (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S)
+#define GPIO_FUNC99_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC99_IN_INV_SEL_S  6
+/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG99_IN_SEL    (BIT(7))
+#define GPIO_SIG99_IN_SEL_M  (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S)
+#define GPIO_SIG99_IN_SEL_V  0x00000001U
+#define GPIO_SIG99_IN_SEL_S  7
+
+/** GPIO_FUNC100_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8)
+/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC100_IN_SEL    0x0000003FU
+#define GPIO_FUNC100_IN_SEL_M  (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S)
+#define GPIO_FUNC100_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC100_IN_SEL_S  0
+/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC100_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC100_IN_INV_SEL_M  (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S)
+#define GPIO_FUNC100_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC100_IN_INV_SEL_S  6
+/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG100_IN_SEL    (BIT(7))
+#define GPIO_SIG100_IN_SEL_M  (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S)
+#define GPIO_SIG100_IN_SEL_V  0x00000001U
+#define GPIO_SIG100_IN_SEL_S  7
+
+/** GPIO_FUNC101_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec)
+/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC101_IN_SEL    0x0000003FU
+#define GPIO_FUNC101_IN_SEL_M  (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S)
+#define GPIO_FUNC101_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC101_IN_SEL_S  0
+/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC101_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC101_IN_INV_SEL_M  (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S)
+#define GPIO_FUNC101_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC101_IN_INV_SEL_S  6
+/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG101_IN_SEL    (BIT(7))
+#define GPIO_SIG101_IN_SEL_M  (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S)
+#define GPIO_SIG101_IN_SEL_V  0x00000001U
+#define GPIO_SIG101_IN_SEL_S  7
+
+/** GPIO_FUNC102_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0)
+/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC102_IN_SEL    0x0000003FU
+#define GPIO_FUNC102_IN_SEL_M  (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S)
+#define GPIO_FUNC102_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC102_IN_SEL_S  0
+/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC102_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC102_IN_INV_SEL_M  (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S)
+#define GPIO_FUNC102_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC102_IN_INV_SEL_S  6
+/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG102_IN_SEL    (BIT(7))
+#define GPIO_SIG102_IN_SEL_M  (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S)
+#define GPIO_SIG102_IN_SEL_V  0x00000001U
+#define GPIO_SIG102_IN_SEL_S  7
+
+/** GPIO_FUNC103_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4)
+/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC103_IN_SEL    0x0000003FU
+#define GPIO_FUNC103_IN_SEL_M  (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S)
+#define GPIO_FUNC103_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC103_IN_SEL_S  0
+/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC103_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC103_IN_INV_SEL_M  (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S)
+#define GPIO_FUNC103_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC103_IN_INV_SEL_S  6
+/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG103_IN_SEL    (BIT(7))
+#define GPIO_SIG103_IN_SEL_M  (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S)
+#define GPIO_SIG103_IN_SEL_V  0x00000001U
+#define GPIO_SIG103_IN_SEL_S  7
+
+/** GPIO_FUNC104_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8)
+/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC104_IN_SEL    0x0000003FU
+#define GPIO_FUNC104_IN_SEL_M  (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S)
+#define GPIO_FUNC104_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC104_IN_SEL_S  0
+/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC104_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC104_IN_INV_SEL_M  (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S)
+#define GPIO_FUNC104_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC104_IN_INV_SEL_S  6
+/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG104_IN_SEL    (BIT(7))
+#define GPIO_SIG104_IN_SEL_M  (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S)
+#define GPIO_SIG104_IN_SEL_V  0x00000001U
+#define GPIO_SIG104_IN_SEL_S  7
+
+/** GPIO_FUNC105_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc)
+/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC105_IN_SEL    0x0000003FU
+#define GPIO_FUNC105_IN_SEL_M  (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S)
+#define GPIO_FUNC105_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC105_IN_SEL_S  0
+/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC105_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC105_IN_INV_SEL_M  (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S)
+#define GPIO_FUNC105_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC105_IN_INV_SEL_S  6
+/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG105_IN_SEL    (BIT(7))
+#define GPIO_SIG105_IN_SEL_M  (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S)
+#define GPIO_SIG105_IN_SEL_V  0x00000001U
+#define GPIO_SIG105_IN_SEL_S  7
+
+/** GPIO_FUNC106_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300)
+/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC106_IN_SEL    0x0000003FU
+#define GPIO_FUNC106_IN_SEL_M  (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S)
+#define GPIO_FUNC106_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC106_IN_SEL_S  0
+/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC106_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC106_IN_INV_SEL_M  (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S)
+#define GPIO_FUNC106_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC106_IN_INV_SEL_S  6
+/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG106_IN_SEL    (BIT(7))
+#define GPIO_SIG106_IN_SEL_M  (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S)
+#define GPIO_SIG106_IN_SEL_V  0x00000001U
+#define GPIO_SIG106_IN_SEL_S  7
+
+/** GPIO_FUNC107_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304)
+/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC107_IN_SEL    0x0000003FU
+#define GPIO_FUNC107_IN_SEL_M  (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S)
+#define GPIO_FUNC107_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC107_IN_SEL_S  0
+/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC107_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC107_IN_INV_SEL_M  (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S)
+#define GPIO_FUNC107_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC107_IN_INV_SEL_S  6
+/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG107_IN_SEL    (BIT(7))
+#define GPIO_SIG107_IN_SEL_M  (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S)
+#define GPIO_SIG107_IN_SEL_V  0x00000001U
+#define GPIO_SIG107_IN_SEL_S  7
+
+/** GPIO_FUNC108_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308)
+/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC108_IN_SEL    0x0000003FU
+#define GPIO_FUNC108_IN_SEL_M  (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S)
+#define GPIO_FUNC108_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC108_IN_SEL_S  0
+/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC108_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC108_IN_INV_SEL_M  (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S)
+#define GPIO_FUNC108_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC108_IN_INV_SEL_S  6
+/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG108_IN_SEL    (BIT(7))
+#define GPIO_SIG108_IN_SEL_M  (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S)
+#define GPIO_SIG108_IN_SEL_V  0x00000001U
+#define GPIO_SIG108_IN_SEL_S  7
+
+/** GPIO_FUNC109_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c)
+/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC109_IN_SEL    0x0000003FU
+#define GPIO_FUNC109_IN_SEL_M  (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S)
+#define GPIO_FUNC109_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC109_IN_SEL_S  0
+/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC109_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC109_IN_INV_SEL_M  (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S)
+#define GPIO_FUNC109_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC109_IN_INV_SEL_S  6
+/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG109_IN_SEL    (BIT(7))
+#define GPIO_SIG109_IN_SEL_M  (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S)
+#define GPIO_SIG109_IN_SEL_V  0x00000001U
+#define GPIO_SIG109_IN_SEL_S  7
+
+/** GPIO_FUNC110_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310)
+/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC110_IN_SEL    0x0000003FU
+#define GPIO_FUNC110_IN_SEL_M  (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S)
+#define GPIO_FUNC110_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC110_IN_SEL_S  0
+/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC110_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC110_IN_INV_SEL_M  (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S)
+#define GPIO_FUNC110_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC110_IN_INV_SEL_S  6
+/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG110_IN_SEL    (BIT(7))
+#define GPIO_SIG110_IN_SEL_M  (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S)
+#define GPIO_SIG110_IN_SEL_V  0x00000001U
+#define GPIO_SIG110_IN_SEL_S  7
+
+/** GPIO_FUNC111_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314)
+/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC111_IN_SEL    0x0000003FU
+#define GPIO_FUNC111_IN_SEL_M  (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S)
+#define GPIO_FUNC111_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC111_IN_SEL_S  0
+/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC111_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC111_IN_INV_SEL_M  (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S)
+#define GPIO_FUNC111_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC111_IN_INV_SEL_S  6
+/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG111_IN_SEL    (BIT(7))
+#define GPIO_SIG111_IN_SEL_M  (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S)
+#define GPIO_SIG111_IN_SEL_V  0x00000001U
+#define GPIO_SIG111_IN_SEL_S  7
+
+/** GPIO_FUNC112_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318)
+/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC112_IN_SEL    0x0000003FU
+#define GPIO_FUNC112_IN_SEL_M  (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S)
+#define GPIO_FUNC112_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC112_IN_SEL_S  0
+/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC112_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC112_IN_INV_SEL_M  (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S)
+#define GPIO_FUNC112_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC112_IN_INV_SEL_S  6
+/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG112_IN_SEL    (BIT(7))
+#define GPIO_SIG112_IN_SEL_M  (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S)
+#define GPIO_SIG112_IN_SEL_V  0x00000001U
+#define GPIO_SIG112_IN_SEL_S  7
+
+/** GPIO_FUNC113_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c)
+/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC113_IN_SEL    0x0000003FU
+#define GPIO_FUNC113_IN_SEL_M  (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S)
+#define GPIO_FUNC113_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC113_IN_SEL_S  0
+/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC113_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC113_IN_INV_SEL_M  (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S)
+#define GPIO_FUNC113_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC113_IN_INV_SEL_S  6
+/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG113_IN_SEL    (BIT(7))
+#define GPIO_SIG113_IN_SEL_M  (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S)
+#define GPIO_SIG113_IN_SEL_V  0x00000001U
+#define GPIO_SIG113_IN_SEL_S  7
+
+/** GPIO_FUNC114_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320)
+/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC114_IN_SEL    0x0000003FU
+#define GPIO_FUNC114_IN_SEL_M  (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S)
+#define GPIO_FUNC114_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC114_IN_SEL_S  0
+/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC114_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC114_IN_INV_SEL_M  (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S)
+#define GPIO_FUNC114_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC114_IN_INV_SEL_S  6
+/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG114_IN_SEL    (BIT(7))
+#define GPIO_SIG114_IN_SEL_M  (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S)
+#define GPIO_SIG114_IN_SEL_V  0x00000001U
+#define GPIO_SIG114_IN_SEL_S  7
+
+/** GPIO_FUNC117_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c)
+/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC117_IN_SEL    0x0000003FU
+#define GPIO_FUNC117_IN_SEL_M  (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S)
+#define GPIO_FUNC117_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC117_IN_SEL_S  0
+/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC117_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC117_IN_INV_SEL_M  (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S)
+#define GPIO_FUNC117_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC117_IN_INV_SEL_S  6
+/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG117_IN_SEL    (BIT(7))
+#define GPIO_SIG117_IN_SEL_M  (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S)
+#define GPIO_SIG117_IN_SEL_V  0x00000001U
+#define GPIO_SIG117_IN_SEL_S  7
+
+/** GPIO_FUNC118_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330)
+/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC118_IN_SEL    0x0000003FU
+#define GPIO_FUNC118_IN_SEL_M  (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S)
+#define GPIO_FUNC118_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC118_IN_SEL_S  0
+/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC118_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC118_IN_INV_SEL_M  (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S)
+#define GPIO_FUNC118_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC118_IN_INV_SEL_S  6
+/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG118_IN_SEL    (BIT(7))
+#define GPIO_SIG118_IN_SEL_M  (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S)
+#define GPIO_SIG118_IN_SEL_V  0x00000001U
+#define GPIO_SIG118_IN_SEL_S  7
+
+/** GPIO_FUNC126_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350)
+/** GPIO_FUNC126_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC126_IN_SEL    0x0000003FU
+#define GPIO_FUNC126_IN_SEL_M  (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S)
+#define GPIO_FUNC126_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC126_IN_SEL_S  0
+/** GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC126_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC126_IN_INV_SEL_M  (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S)
+#define GPIO_FUNC126_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC126_IN_INV_SEL_S  6
+/** GPIO_SIG126_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG126_IN_SEL    (BIT(7))
+#define GPIO_SIG126_IN_SEL_M  (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S)
+#define GPIO_SIG126_IN_SEL_V  0x00000001U
+#define GPIO_SIG126_IN_SEL_S  7
+
+/** GPIO_FUNC127_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354)
+/** GPIO_FUNC127_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC127_IN_SEL    0x0000003FU
+#define GPIO_FUNC127_IN_SEL_M  (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S)
+#define GPIO_FUNC127_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC127_IN_SEL_S  0
+/** GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC127_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC127_IN_INV_SEL_M  (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S)
+#define GPIO_FUNC127_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC127_IN_INV_SEL_S  6
+/** GPIO_SIG127_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG127_IN_SEL    (BIT(7))
+#define GPIO_SIG127_IN_SEL_M  (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S)
+#define GPIO_SIG127_IN_SEL_V  0x00000001U
+#define GPIO_SIG127_IN_SEL_S  7
+
+/** GPIO_FUNC128_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358)
+/** GPIO_FUNC128_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC128_IN_SEL    0x0000003FU
+#define GPIO_FUNC128_IN_SEL_M  (GPIO_FUNC128_IN_SEL_V << GPIO_FUNC128_IN_SEL_S)
+#define GPIO_FUNC128_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC128_IN_SEL_S  0
+/** GPIO_FUNC128_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC128_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC128_IN_INV_SEL_M  (GPIO_FUNC128_IN_INV_SEL_V << GPIO_FUNC128_IN_INV_SEL_S)
+#define GPIO_FUNC128_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC128_IN_INV_SEL_S  6
+/** GPIO_SIG128_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG128_IN_SEL    (BIT(7))
+#define GPIO_SIG128_IN_SEL_M  (GPIO_SIG128_IN_SEL_V << GPIO_SIG128_IN_SEL_S)
+#define GPIO_SIG128_IN_SEL_V  0x00000001U
+#define GPIO_SIG128_IN_SEL_S  7
+
+/** GPIO_FUNC129_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35c)
+/** GPIO_FUNC129_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC129_IN_SEL    0x0000003FU
+#define GPIO_FUNC129_IN_SEL_M  (GPIO_FUNC129_IN_SEL_V << GPIO_FUNC129_IN_SEL_S)
+#define GPIO_FUNC129_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC129_IN_SEL_S  0
+/** GPIO_FUNC129_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC129_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC129_IN_INV_SEL_M  (GPIO_FUNC129_IN_INV_SEL_V << GPIO_FUNC129_IN_INV_SEL_S)
+#define GPIO_FUNC129_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC129_IN_INV_SEL_S  6
+/** GPIO_SIG129_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG129_IN_SEL    (BIT(7))
+#define GPIO_SIG129_IN_SEL_M  (GPIO_SIG129_IN_SEL_V << GPIO_SIG129_IN_SEL_S)
+#define GPIO_SIG129_IN_SEL_V  0x00000001U
+#define GPIO_SIG129_IN_SEL_S  7
+
+/** GPIO_FUNC130_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360)
+/** GPIO_FUNC130_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC130_IN_SEL    0x0000003FU
+#define GPIO_FUNC130_IN_SEL_M  (GPIO_FUNC130_IN_SEL_V << GPIO_FUNC130_IN_SEL_S)
+#define GPIO_FUNC130_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC130_IN_SEL_S  0
+/** GPIO_FUNC130_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC130_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC130_IN_INV_SEL_M  (GPIO_FUNC130_IN_INV_SEL_V << GPIO_FUNC130_IN_INV_SEL_S)
+#define GPIO_FUNC130_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC130_IN_INV_SEL_S  6
+/** GPIO_SIG130_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG130_IN_SEL    (BIT(7))
+#define GPIO_SIG130_IN_SEL_M  (GPIO_SIG130_IN_SEL_V << GPIO_SIG130_IN_SEL_S)
+#define GPIO_SIG130_IN_SEL_V  0x00000001U
+#define GPIO_SIG130_IN_SEL_S  7
+
+/** GPIO_FUNC131_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x364)
+/** GPIO_FUNC131_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC131_IN_SEL    0x0000003FU
+#define GPIO_FUNC131_IN_SEL_M  (GPIO_FUNC131_IN_SEL_V << GPIO_FUNC131_IN_SEL_S)
+#define GPIO_FUNC131_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC131_IN_SEL_S  0
+/** GPIO_FUNC131_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC131_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC131_IN_INV_SEL_M  (GPIO_FUNC131_IN_INV_SEL_V << GPIO_FUNC131_IN_INV_SEL_S)
+#define GPIO_FUNC131_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC131_IN_INV_SEL_S  6
+/** GPIO_SIG131_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG131_IN_SEL    (BIT(7))
+#define GPIO_SIG131_IN_SEL_M  (GPIO_SIG131_IN_SEL_V << GPIO_SIG131_IN_SEL_S)
+#define GPIO_SIG131_IN_SEL_V  0x00000001U
+#define GPIO_SIG131_IN_SEL_S  7
+
+/** GPIO_FUNC132_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368)
+/** GPIO_FUNC132_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC132_IN_SEL    0x0000003FU
+#define GPIO_FUNC132_IN_SEL_M  (GPIO_FUNC132_IN_SEL_V << GPIO_FUNC132_IN_SEL_S)
+#define GPIO_FUNC132_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC132_IN_SEL_S  0
+/** GPIO_FUNC132_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC132_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC132_IN_INV_SEL_M  (GPIO_FUNC132_IN_INV_SEL_V << GPIO_FUNC132_IN_INV_SEL_S)
+#define GPIO_FUNC132_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC132_IN_INV_SEL_S  6
+/** GPIO_SIG132_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG132_IN_SEL    (BIT(7))
+#define GPIO_SIG132_IN_SEL_M  (GPIO_SIG132_IN_SEL_V << GPIO_SIG132_IN_SEL_S)
+#define GPIO_SIG132_IN_SEL_V  0x00000001U
+#define GPIO_SIG132_IN_SEL_S  7
+
+/** GPIO_FUNC133_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c)
+/** GPIO_FUNC133_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC133_IN_SEL    0x0000003FU
+#define GPIO_FUNC133_IN_SEL_M  (GPIO_FUNC133_IN_SEL_V << GPIO_FUNC133_IN_SEL_S)
+#define GPIO_FUNC133_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC133_IN_SEL_S  0
+/** GPIO_FUNC133_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC133_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC133_IN_INV_SEL_M  (GPIO_FUNC133_IN_INV_SEL_V << GPIO_FUNC133_IN_INV_SEL_S)
+#define GPIO_FUNC133_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC133_IN_INV_SEL_S  6
+/** GPIO_SIG133_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG133_IN_SEL    (BIT(7))
+#define GPIO_SIG133_IN_SEL_M  (GPIO_SIG133_IN_SEL_V << GPIO_SIG133_IN_SEL_S)
+#define GPIO_SIG133_IN_SEL_V  0x00000001U
+#define GPIO_SIG133_IN_SEL_S  7
+
+/** GPIO_FUNC134_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370)
+/** GPIO_FUNC134_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC134_IN_SEL    0x0000003FU
+#define GPIO_FUNC134_IN_SEL_M  (GPIO_FUNC134_IN_SEL_V << GPIO_FUNC134_IN_SEL_S)
+#define GPIO_FUNC134_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC134_IN_SEL_S  0
+/** GPIO_FUNC134_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC134_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC134_IN_INV_SEL_M  (GPIO_FUNC134_IN_INV_SEL_V << GPIO_FUNC134_IN_INV_SEL_S)
+#define GPIO_FUNC134_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC134_IN_INV_SEL_S  6
+/** GPIO_SIG134_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG134_IN_SEL    (BIT(7))
+#define GPIO_SIG134_IN_SEL_M  (GPIO_SIG134_IN_SEL_V << GPIO_SIG134_IN_SEL_S)
+#define GPIO_SIG134_IN_SEL_V  0x00000001U
+#define GPIO_SIG134_IN_SEL_S  7
+
+/** GPIO_FUNC135_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x374)
+/** GPIO_FUNC135_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC135_IN_SEL    0x0000003FU
+#define GPIO_FUNC135_IN_SEL_M  (GPIO_FUNC135_IN_SEL_V << GPIO_FUNC135_IN_SEL_S)
+#define GPIO_FUNC135_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC135_IN_SEL_S  0
+/** GPIO_FUNC135_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC135_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC135_IN_INV_SEL_M  (GPIO_FUNC135_IN_INV_SEL_V << GPIO_FUNC135_IN_INV_SEL_S)
+#define GPIO_FUNC135_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC135_IN_INV_SEL_S  6
+/** GPIO_SIG135_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG135_IN_SEL    (BIT(7))
+#define GPIO_SIG135_IN_SEL_M  (GPIO_SIG135_IN_SEL_V << GPIO_SIG135_IN_SEL_S)
+#define GPIO_SIG135_IN_SEL_V  0x00000001U
+#define GPIO_SIG135_IN_SEL_S  7
+
+/** GPIO_FUNC136_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378)
+/** GPIO_FUNC136_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC136_IN_SEL    0x0000003FU
+#define GPIO_FUNC136_IN_SEL_M  (GPIO_FUNC136_IN_SEL_V << GPIO_FUNC136_IN_SEL_S)
+#define GPIO_FUNC136_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC136_IN_SEL_S  0
+/** GPIO_FUNC136_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC136_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC136_IN_INV_SEL_M  (GPIO_FUNC136_IN_INV_SEL_V << GPIO_FUNC136_IN_INV_SEL_S)
+#define GPIO_FUNC136_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC136_IN_INV_SEL_S  6
+/** GPIO_SIG136_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG136_IN_SEL    (BIT(7))
+#define GPIO_SIG136_IN_SEL_M  (GPIO_SIG136_IN_SEL_V << GPIO_SIG136_IN_SEL_S)
+#define GPIO_SIG136_IN_SEL_V  0x00000001U
+#define GPIO_SIG136_IN_SEL_S  7
+
+/** GPIO_FUNC137_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c)
+/** GPIO_FUNC137_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC137_IN_SEL    0x0000003FU
+#define GPIO_FUNC137_IN_SEL_M  (GPIO_FUNC137_IN_SEL_V << GPIO_FUNC137_IN_SEL_S)
+#define GPIO_FUNC137_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC137_IN_SEL_S  0
+/** GPIO_FUNC137_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC137_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC137_IN_INV_SEL_M  (GPIO_FUNC137_IN_INV_SEL_V << GPIO_FUNC137_IN_INV_SEL_S)
+#define GPIO_FUNC137_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC137_IN_INV_SEL_S  6
+/** GPIO_SIG137_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG137_IN_SEL    (BIT(7))
+#define GPIO_SIG137_IN_SEL_M  (GPIO_SIG137_IN_SEL_V << GPIO_SIG137_IN_SEL_S)
+#define GPIO_SIG137_IN_SEL_V  0x00000001U
+#define GPIO_SIG137_IN_SEL_S  7
+
+/** GPIO_FUNC140_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x388)
+/** GPIO_FUNC140_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC140_IN_SEL    0x0000003FU
+#define GPIO_FUNC140_IN_SEL_M  (GPIO_FUNC140_IN_SEL_V << GPIO_FUNC140_IN_SEL_S)
+#define GPIO_FUNC140_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC140_IN_SEL_S  0
+/** GPIO_FUNC140_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC140_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC140_IN_INV_SEL_M  (GPIO_FUNC140_IN_INV_SEL_V << GPIO_FUNC140_IN_INV_SEL_S)
+#define GPIO_FUNC140_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC140_IN_INV_SEL_S  6
+/** GPIO_SIG140_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG140_IN_SEL    (BIT(7))
+#define GPIO_SIG140_IN_SEL_M  (GPIO_SIG140_IN_SEL_V << GPIO_SIG140_IN_SEL_S)
+#define GPIO_SIG140_IN_SEL_V  0x00000001U
+#define GPIO_SIG140_IN_SEL_S  7
+
+/** GPIO_FUNC141_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c)
+/** GPIO_FUNC141_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC141_IN_SEL    0x0000003FU
+#define GPIO_FUNC141_IN_SEL_M  (GPIO_FUNC141_IN_SEL_V << GPIO_FUNC141_IN_SEL_S)
+#define GPIO_FUNC141_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC141_IN_SEL_S  0
+/** GPIO_FUNC141_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC141_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC141_IN_INV_SEL_M  (GPIO_FUNC141_IN_INV_SEL_V << GPIO_FUNC141_IN_INV_SEL_S)
+#define GPIO_FUNC141_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC141_IN_INV_SEL_S  6
+/** GPIO_SIG141_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG141_IN_SEL    (BIT(7))
+#define GPIO_SIG141_IN_SEL_M  (GPIO_SIG141_IN_SEL_V << GPIO_SIG141_IN_SEL_S)
+#define GPIO_SIG141_IN_SEL_V  0x00000001U
+#define GPIO_SIG141_IN_SEL_S  7
+
+/** GPIO_FUNC142_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390)
+/** GPIO_FUNC142_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC142_IN_SEL    0x0000003FU
+#define GPIO_FUNC142_IN_SEL_M  (GPIO_FUNC142_IN_SEL_V << GPIO_FUNC142_IN_SEL_S)
+#define GPIO_FUNC142_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC142_IN_SEL_S  0
+/** GPIO_FUNC142_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC142_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC142_IN_INV_SEL_M  (GPIO_FUNC142_IN_INV_SEL_V << GPIO_FUNC142_IN_INV_SEL_S)
+#define GPIO_FUNC142_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC142_IN_INV_SEL_S  6
+/** GPIO_SIG142_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG142_IN_SEL    (BIT(7))
+#define GPIO_SIG142_IN_SEL_M  (GPIO_SIG142_IN_SEL_V << GPIO_SIG142_IN_SEL_S)
+#define GPIO_SIG142_IN_SEL_V  0x00000001U
+#define GPIO_SIG142_IN_SEL_S  7
+
+/** GPIO_FUNC143_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x394)
+/** GPIO_FUNC143_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC143_IN_SEL    0x0000003FU
+#define GPIO_FUNC143_IN_SEL_M  (GPIO_FUNC143_IN_SEL_V << GPIO_FUNC143_IN_SEL_S)
+#define GPIO_FUNC143_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC143_IN_SEL_S  0
+/** GPIO_FUNC143_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC143_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC143_IN_INV_SEL_M  (GPIO_FUNC143_IN_INV_SEL_V << GPIO_FUNC143_IN_INV_SEL_S)
+#define GPIO_FUNC143_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC143_IN_INV_SEL_S  6
+/** GPIO_SIG143_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG143_IN_SEL    (BIT(7))
+#define GPIO_SIG143_IN_SEL_M  (GPIO_SIG143_IN_SEL_V << GPIO_SIG143_IN_SEL_S)
+#define GPIO_SIG143_IN_SEL_V  0x00000001U
+#define GPIO_SIG143_IN_SEL_S  7
+
+/** GPIO_FUNC144_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x398)
+/** GPIO_FUNC144_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC144_IN_SEL    0x0000003FU
+#define GPIO_FUNC144_IN_SEL_M  (GPIO_FUNC144_IN_SEL_V << GPIO_FUNC144_IN_SEL_S)
+#define GPIO_FUNC144_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC144_IN_SEL_S  0
+/** GPIO_FUNC144_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC144_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC144_IN_INV_SEL_M  (GPIO_FUNC144_IN_INV_SEL_V << GPIO_FUNC144_IN_INV_SEL_S)
+#define GPIO_FUNC144_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC144_IN_INV_SEL_S  6
+/** GPIO_SIG144_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG144_IN_SEL    (BIT(7))
+#define GPIO_SIG144_IN_SEL_M  (GPIO_SIG144_IN_SEL_V << GPIO_SIG144_IN_SEL_S)
+#define GPIO_SIG144_IN_SEL_V  0x00000001U
+#define GPIO_SIG144_IN_SEL_S  7
+
+/** GPIO_FUNC145_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x39c)
+/** GPIO_FUNC145_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC145_IN_SEL    0x0000003FU
+#define GPIO_FUNC145_IN_SEL_M  (GPIO_FUNC145_IN_SEL_V << GPIO_FUNC145_IN_SEL_S)
+#define GPIO_FUNC145_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC145_IN_SEL_S  0
+/** GPIO_FUNC145_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC145_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC145_IN_INV_SEL_M  (GPIO_FUNC145_IN_INV_SEL_V << GPIO_FUNC145_IN_INV_SEL_S)
+#define GPIO_FUNC145_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC145_IN_INV_SEL_S  6
+/** GPIO_SIG145_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG145_IN_SEL    (BIT(7))
+#define GPIO_SIG145_IN_SEL_M  (GPIO_SIG145_IN_SEL_V << GPIO_SIG145_IN_SEL_S)
+#define GPIO_SIG145_IN_SEL_V  0x00000001U
+#define GPIO_SIG145_IN_SEL_S  7
+
+/** GPIO_FUNC146_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a0)
+/** GPIO_FUNC146_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC146_IN_SEL    0x0000003FU
+#define GPIO_FUNC146_IN_SEL_M  (GPIO_FUNC146_IN_SEL_V << GPIO_FUNC146_IN_SEL_S)
+#define GPIO_FUNC146_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC146_IN_SEL_S  0
+/** GPIO_FUNC146_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC146_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC146_IN_INV_SEL_M  (GPIO_FUNC146_IN_INV_SEL_V << GPIO_FUNC146_IN_INV_SEL_S)
+#define GPIO_FUNC146_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC146_IN_INV_SEL_S  6
+/** GPIO_SIG146_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG146_IN_SEL    (BIT(7))
+#define GPIO_SIG146_IN_SEL_M  (GPIO_SIG146_IN_SEL_V << GPIO_SIG146_IN_SEL_S)
+#define GPIO_SIG146_IN_SEL_V  0x00000001U
+#define GPIO_SIG146_IN_SEL_S  7
+
+/** GPIO_FUNC147_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a4)
+/** GPIO_FUNC147_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC147_IN_SEL    0x0000003FU
+#define GPIO_FUNC147_IN_SEL_M  (GPIO_FUNC147_IN_SEL_V << GPIO_FUNC147_IN_SEL_S)
+#define GPIO_FUNC147_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC147_IN_SEL_S  0
+/** GPIO_FUNC147_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC147_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC147_IN_INV_SEL_M  (GPIO_FUNC147_IN_INV_SEL_V << GPIO_FUNC147_IN_INV_SEL_S)
+#define GPIO_FUNC147_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC147_IN_INV_SEL_S  6
+/** GPIO_SIG147_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG147_IN_SEL    (BIT(7))
+#define GPIO_SIG147_IN_SEL_M  (GPIO_SIG147_IN_SEL_V << GPIO_SIG147_IN_SEL_S)
+#define GPIO_SIG147_IN_SEL_V  0x00000001U
+#define GPIO_SIG147_IN_SEL_S  7
+
+/** GPIO_FUNC148_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a8)
+/** GPIO_FUNC148_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC148_IN_SEL    0x0000003FU
+#define GPIO_FUNC148_IN_SEL_M  (GPIO_FUNC148_IN_SEL_V << GPIO_FUNC148_IN_SEL_S)
+#define GPIO_FUNC148_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC148_IN_SEL_S  0
+/** GPIO_FUNC148_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC148_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC148_IN_INV_SEL_M  (GPIO_FUNC148_IN_INV_SEL_V << GPIO_FUNC148_IN_INV_SEL_S)
+#define GPIO_FUNC148_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC148_IN_INV_SEL_S  6
+/** GPIO_SIG148_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG148_IN_SEL    (BIT(7))
+#define GPIO_SIG148_IN_SEL_M  (GPIO_SIG148_IN_SEL_V << GPIO_SIG148_IN_SEL_S)
+#define GPIO_SIG148_IN_SEL_V  0x00000001U
+#define GPIO_SIG148_IN_SEL_S  7
+
+/** GPIO_FUNC149_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ac)
+/** GPIO_FUNC149_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC149_IN_SEL    0x0000003FU
+#define GPIO_FUNC149_IN_SEL_M  (GPIO_FUNC149_IN_SEL_V << GPIO_FUNC149_IN_SEL_S)
+#define GPIO_FUNC149_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC149_IN_SEL_S  0
+/** GPIO_FUNC149_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC149_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC149_IN_INV_SEL_M  (GPIO_FUNC149_IN_INV_SEL_V << GPIO_FUNC149_IN_INV_SEL_S)
+#define GPIO_FUNC149_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC149_IN_INV_SEL_S  6
+/** GPIO_SIG149_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG149_IN_SEL    (BIT(7))
+#define GPIO_SIG149_IN_SEL_M  (GPIO_SIG149_IN_SEL_V << GPIO_SIG149_IN_SEL_S)
+#define GPIO_SIG149_IN_SEL_V  0x00000001U
+#define GPIO_SIG149_IN_SEL_S  7
+
+/** GPIO_FUNC150_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b0)
+/** GPIO_FUNC150_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC150_IN_SEL    0x0000003FU
+#define GPIO_FUNC150_IN_SEL_M  (GPIO_FUNC150_IN_SEL_V << GPIO_FUNC150_IN_SEL_S)
+#define GPIO_FUNC150_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC150_IN_SEL_S  0
+/** GPIO_FUNC150_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC150_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC150_IN_INV_SEL_M  (GPIO_FUNC150_IN_INV_SEL_V << GPIO_FUNC150_IN_INV_SEL_S)
+#define GPIO_FUNC150_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC150_IN_INV_SEL_S  6
+/** GPIO_SIG150_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG150_IN_SEL    (BIT(7))
+#define GPIO_SIG150_IN_SEL_M  (GPIO_SIG150_IN_SEL_V << GPIO_SIG150_IN_SEL_S)
+#define GPIO_SIG150_IN_SEL_V  0x00000001U
+#define GPIO_SIG150_IN_SEL_S  7
+
+/** GPIO_FUNC151_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b4)
+/** GPIO_FUNC151_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC151_IN_SEL    0x0000003FU
+#define GPIO_FUNC151_IN_SEL_M  (GPIO_FUNC151_IN_SEL_V << GPIO_FUNC151_IN_SEL_S)
+#define GPIO_FUNC151_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC151_IN_SEL_S  0
+/** GPIO_FUNC151_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC151_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC151_IN_INV_SEL_M  (GPIO_FUNC151_IN_INV_SEL_V << GPIO_FUNC151_IN_INV_SEL_S)
+#define GPIO_FUNC151_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC151_IN_INV_SEL_S  6
+/** GPIO_SIG151_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG151_IN_SEL    (BIT(7))
+#define GPIO_SIG151_IN_SEL_M  (GPIO_SIG151_IN_SEL_V << GPIO_SIG151_IN_SEL_S)
+#define GPIO_SIG151_IN_SEL_V  0x00000001U
+#define GPIO_SIG151_IN_SEL_S  7
+
+/** GPIO_FUNC152_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b8)
+/** GPIO_FUNC152_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC152_IN_SEL    0x0000003FU
+#define GPIO_FUNC152_IN_SEL_M  (GPIO_FUNC152_IN_SEL_V << GPIO_FUNC152_IN_SEL_S)
+#define GPIO_FUNC152_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC152_IN_SEL_S  0
+/** GPIO_FUNC152_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC152_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC152_IN_INV_SEL_M  (GPIO_FUNC152_IN_INV_SEL_V << GPIO_FUNC152_IN_INV_SEL_S)
+#define GPIO_FUNC152_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC152_IN_INV_SEL_S  6
+/** GPIO_SIG152_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG152_IN_SEL    (BIT(7))
+#define GPIO_SIG152_IN_SEL_M  (GPIO_SIG152_IN_SEL_V << GPIO_SIG152_IN_SEL_S)
+#define GPIO_SIG152_IN_SEL_V  0x00000001U
+#define GPIO_SIG152_IN_SEL_S  7
+
+/** GPIO_FUNC153_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3bc)
+/** GPIO_FUNC153_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC153_IN_SEL    0x0000003FU
+#define GPIO_FUNC153_IN_SEL_M  (GPIO_FUNC153_IN_SEL_V << GPIO_FUNC153_IN_SEL_S)
+#define GPIO_FUNC153_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC153_IN_SEL_S  0
+/** GPIO_FUNC153_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC153_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC153_IN_INV_SEL_M  (GPIO_FUNC153_IN_INV_SEL_V << GPIO_FUNC153_IN_INV_SEL_S)
+#define GPIO_FUNC153_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC153_IN_INV_SEL_S  6
+/** GPIO_SIG153_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG153_IN_SEL    (BIT(7))
+#define GPIO_SIG153_IN_SEL_M  (GPIO_SIG153_IN_SEL_V << GPIO_SIG153_IN_SEL_S)
+#define GPIO_SIG153_IN_SEL_V  0x00000001U
+#define GPIO_SIG153_IN_SEL_S  7
+
+/** GPIO_FUNC154_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c0)
+/** GPIO_FUNC154_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC154_IN_SEL    0x0000003FU
+#define GPIO_FUNC154_IN_SEL_M  (GPIO_FUNC154_IN_SEL_V << GPIO_FUNC154_IN_SEL_S)
+#define GPIO_FUNC154_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC154_IN_SEL_S  0
+/** GPIO_FUNC154_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC154_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC154_IN_INV_SEL_M  (GPIO_FUNC154_IN_INV_SEL_V << GPIO_FUNC154_IN_INV_SEL_S)
+#define GPIO_FUNC154_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC154_IN_INV_SEL_S  6
+/** GPIO_SIG154_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG154_IN_SEL    (BIT(7))
+#define GPIO_SIG154_IN_SEL_M  (GPIO_SIG154_IN_SEL_V << GPIO_SIG154_IN_SEL_S)
+#define GPIO_SIG154_IN_SEL_V  0x00000001U
+#define GPIO_SIG154_IN_SEL_S  7
+
+/** GPIO_FUNC155_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4)
+/** GPIO_FUNC155_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC155_IN_SEL    0x0000003FU
+#define GPIO_FUNC155_IN_SEL_M  (GPIO_FUNC155_IN_SEL_V << GPIO_FUNC155_IN_SEL_S)
+#define GPIO_FUNC155_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC155_IN_SEL_S  0
+/** GPIO_FUNC155_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC155_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC155_IN_INV_SEL_M  (GPIO_FUNC155_IN_INV_SEL_V << GPIO_FUNC155_IN_INV_SEL_S)
+#define GPIO_FUNC155_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC155_IN_INV_SEL_S  6
+/** GPIO_SIG155_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG155_IN_SEL    (BIT(7))
+#define GPIO_SIG155_IN_SEL_M  (GPIO_SIG155_IN_SEL_V << GPIO_SIG155_IN_SEL_S)
+#define GPIO_SIG155_IN_SEL_V  0x00000001U
+#define GPIO_SIG155_IN_SEL_S  7
+
+/** GPIO_FUNC156_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8)
+/** GPIO_FUNC156_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC156_IN_SEL    0x0000003FU
+#define GPIO_FUNC156_IN_SEL_M  (GPIO_FUNC156_IN_SEL_V << GPIO_FUNC156_IN_SEL_S)
+#define GPIO_FUNC156_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC156_IN_SEL_S  0
+/** GPIO_FUNC156_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC156_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC156_IN_INV_SEL_M  (GPIO_FUNC156_IN_INV_SEL_V << GPIO_FUNC156_IN_INV_SEL_S)
+#define GPIO_FUNC156_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC156_IN_INV_SEL_S  6
+/** GPIO_SIG156_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG156_IN_SEL    (BIT(7))
+#define GPIO_SIG156_IN_SEL_M  (GPIO_SIG156_IN_SEL_V << GPIO_SIG156_IN_SEL_S)
+#define GPIO_SIG156_IN_SEL_V  0x00000001U
+#define GPIO_SIG156_IN_SEL_S  7
+
+/** GPIO_FUNC158_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0)
+/** GPIO_FUNC158_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC158_IN_SEL    0x0000003FU
+#define GPIO_FUNC158_IN_SEL_M  (GPIO_FUNC158_IN_SEL_V << GPIO_FUNC158_IN_SEL_S)
+#define GPIO_FUNC158_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC158_IN_SEL_S  0
+/** GPIO_FUNC158_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC158_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC158_IN_INV_SEL_M  (GPIO_FUNC158_IN_INV_SEL_V << GPIO_FUNC158_IN_INV_SEL_S)
+#define GPIO_FUNC158_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC158_IN_INV_SEL_S  6
+/** GPIO_SIG158_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG158_IN_SEL    (BIT(7))
+#define GPIO_SIG158_IN_SEL_M  (GPIO_SIG158_IN_SEL_V << GPIO_SIG158_IN_SEL_S)
+#define GPIO_SIG158_IN_SEL_V  0x00000001U
+#define GPIO_SIG158_IN_SEL_S  7
+
+/** GPIO_FUNC159_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4)
+/** GPIO_FUNC159_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC159_IN_SEL    0x0000003FU
+#define GPIO_FUNC159_IN_SEL_M  (GPIO_FUNC159_IN_SEL_V << GPIO_FUNC159_IN_SEL_S)
+#define GPIO_FUNC159_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC159_IN_SEL_S  0
+/** GPIO_FUNC159_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC159_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC159_IN_INV_SEL_M  (GPIO_FUNC159_IN_INV_SEL_V << GPIO_FUNC159_IN_INV_SEL_S)
+#define GPIO_FUNC159_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC159_IN_INV_SEL_S  6
+/** GPIO_SIG159_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG159_IN_SEL    (BIT(7))
+#define GPIO_SIG159_IN_SEL_M  (GPIO_SIG159_IN_SEL_V << GPIO_SIG159_IN_SEL_S)
+#define GPIO_SIG159_IN_SEL_V  0x00000001U
+#define GPIO_SIG159_IN_SEL_S  7
+
+/** GPIO_FUNC160_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8)
+/** GPIO_FUNC160_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC160_IN_SEL    0x0000003FU
+#define GPIO_FUNC160_IN_SEL_M  (GPIO_FUNC160_IN_SEL_V << GPIO_FUNC160_IN_SEL_S)
+#define GPIO_FUNC160_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC160_IN_SEL_S  0
+/** GPIO_FUNC160_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC160_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC160_IN_INV_SEL_M  (GPIO_FUNC160_IN_INV_SEL_V << GPIO_FUNC160_IN_INV_SEL_S)
+#define GPIO_FUNC160_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC160_IN_INV_SEL_S  6
+/** GPIO_SIG160_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG160_IN_SEL    (BIT(7))
+#define GPIO_SIG160_IN_SEL_M  (GPIO_SIG160_IN_SEL_V << GPIO_SIG160_IN_SEL_S)
+#define GPIO_SIG160_IN_SEL_V  0x00000001U
+#define GPIO_SIG160_IN_SEL_S  7
+
+/** GPIO_FUNC161_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc)
+/** GPIO_FUNC161_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC161_IN_SEL    0x0000003FU
+#define GPIO_FUNC161_IN_SEL_M  (GPIO_FUNC161_IN_SEL_V << GPIO_FUNC161_IN_SEL_S)
+#define GPIO_FUNC161_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC161_IN_SEL_S  0
+/** GPIO_FUNC161_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC161_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC161_IN_INV_SEL_M  (GPIO_FUNC161_IN_INV_SEL_V << GPIO_FUNC161_IN_INV_SEL_S)
+#define GPIO_FUNC161_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC161_IN_INV_SEL_S  6
+/** GPIO_SIG161_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG161_IN_SEL    (BIT(7))
+#define GPIO_SIG161_IN_SEL_M  (GPIO_SIG161_IN_SEL_V << GPIO_SIG161_IN_SEL_S)
+#define GPIO_SIG161_IN_SEL_V  0x00000001U
+#define GPIO_SIG161_IN_SEL_S  7
+
+/** GPIO_FUNC162_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e0)
+/** GPIO_FUNC162_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC162_IN_SEL    0x0000003FU
+#define GPIO_FUNC162_IN_SEL_M  (GPIO_FUNC162_IN_SEL_V << GPIO_FUNC162_IN_SEL_S)
+#define GPIO_FUNC162_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC162_IN_SEL_S  0
+/** GPIO_FUNC162_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC162_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC162_IN_INV_SEL_M  (GPIO_FUNC162_IN_INV_SEL_V << GPIO_FUNC162_IN_INV_SEL_S)
+#define GPIO_FUNC162_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC162_IN_INV_SEL_S  6
+/** GPIO_SIG162_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG162_IN_SEL    (BIT(7))
+#define GPIO_SIG162_IN_SEL_M  (GPIO_SIG162_IN_SEL_V << GPIO_SIG162_IN_SEL_S)
+#define GPIO_SIG162_IN_SEL_V  0x00000001U
+#define GPIO_SIG162_IN_SEL_S  7
+
+/** GPIO_FUNC163_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4)
+/** GPIO_FUNC163_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC163_IN_SEL    0x0000003FU
+#define GPIO_FUNC163_IN_SEL_M  (GPIO_FUNC163_IN_SEL_V << GPIO_FUNC163_IN_SEL_S)
+#define GPIO_FUNC163_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC163_IN_SEL_S  0
+/** GPIO_FUNC163_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC163_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC163_IN_INV_SEL_M  (GPIO_FUNC163_IN_INV_SEL_V << GPIO_FUNC163_IN_INV_SEL_S)
+#define GPIO_FUNC163_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC163_IN_INV_SEL_S  6
+/** GPIO_SIG163_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG163_IN_SEL    (BIT(7))
+#define GPIO_SIG163_IN_SEL_M  (GPIO_SIG163_IN_SEL_V << GPIO_SIG163_IN_SEL_S)
+#define GPIO_SIG163_IN_SEL_V  0x00000001U
+#define GPIO_SIG163_IN_SEL_S  7
+
+/** GPIO_FUNC164_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8)
+/** GPIO_FUNC164_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC164_IN_SEL    0x0000003FU
+#define GPIO_FUNC164_IN_SEL_M  (GPIO_FUNC164_IN_SEL_V << GPIO_FUNC164_IN_SEL_S)
+#define GPIO_FUNC164_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC164_IN_SEL_S  0
+/** GPIO_FUNC164_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC164_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC164_IN_INV_SEL_M  (GPIO_FUNC164_IN_INV_SEL_V << GPIO_FUNC164_IN_INV_SEL_S)
+#define GPIO_FUNC164_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC164_IN_INV_SEL_S  6
+/** GPIO_SIG164_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG164_IN_SEL    (BIT(7))
+#define GPIO_SIG164_IN_SEL_M  (GPIO_SIG164_IN_SEL_V << GPIO_SIG164_IN_SEL_S)
+#define GPIO_SIG164_IN_SEL_V  0x00000001U
+#define GPIO_SIG164_IN_SEL_S  7
+
+/** GPIO_FUNC165_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec)
+/** GPIO_FUNC165_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC165_IN_SEL    0x0000003FU
+#define GPIO_FUNC165_IN_SEL_M  (GPIO_FUNC165_IN_SEL_V << GPIO_FUNC165_IN_SEL_S)
+#define GPIO_FUNC165_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC165_IN_SEL_S  0
+/** GPIO_FUNC165_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC165_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC165_IN_INV_SEL_M  (GPIO_FUNC165_IN_INV_SEL_V << GPIO_FUNC165_IN_INV_SEL_S)
+#define GPIO_FUNC165_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC165_IN_INV_SEL_S  6
+/** GPIO_SIG165_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG165_IN_SEL    (BIT(7))
+#define GPIO_SIG165_IN_SEL_M  (GPIO_SIG165_IN_SEL_V << GPIO_SIG165_IN_SEL_S)
+#define GPIO_SIG165_IN_SEL_V  0x00000001U
+#define GPIO_SIG165_IN_SEL_S  7
+
+/** GPIO_FUNC166_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f0)
+/** GPIO_FUNC166_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC166_IN_SEL    0x0000003FU
+#define GPIO_FUNC166_IN_SEL_M  (GPIO_FUNC166_IN_SEL_V << GPIO_FUNC166_IN_SEL_S)
+#define GPIO_FUNC166_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC166_IN_SEL_S  0
+/** GPIO_FUNC166_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC166_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC166_IN_INV_SEL_M  (GPIO_FUNC166_IN_INV_SEL_V << GPIO_FUNC166_IN_INV_SEL_S)
+#define GPIO_FUNC166_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC166_IN_INV_SEL_S  6
+/** GPIO_SIG166_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG166_IN_SEL    (BIT(7))
+#define GPIO_SIG166_IN_SEL_M  (GPIO_SIG166_IN_SEL_V << GPIO_SIG166_IN_SEL_S)
+#define GPIO_SIG166_IN_SEL_V  0x00000001U
+#define GPIO_SIG166_IN_SEL_S  7
+
+/** GPIO_FUNC167_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f4)
+/** GPIO_FUNC167_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC167_IN_SEL    0x0000003FU
+#define GPIO_FUNC167_IN_SEL_M  (GPIO_FUNC167_IN_SEL_V << GPIO_FUNC167_IN_SEL_S)
+#define GPIO_FUNC167_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC167_IN_SEL_S  0
+/** GPIO_FUNC167_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC167_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC167_IN_INV_SEL_M  (GPIO_FUNC167_IN_INV_SEL_V << GPIO_FUNC167_IN_INV_SEL_S)
+#define GPIO_FUNC167_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC167_IN_INV_SEL_S  6
+/** GPIO_SIG167_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG167_IN_SEL    (BIT(7))
+#define GPIO_SIG167_IN_SEL_M  (GPIO_SIG167_IN_SEL_V << GPIO_SIG167_IN_SEL_S)
+#define GPIO_SIG167_IN_SEL_V  0x00000001U
+#define GPIO_SIG167_IN_SEL_S  7
+
+/** GPIO_FUNC168_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f8)
+/** GPIO_FUNC168_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC168_IN_SEL    0x0000003FU
+#define GPIO_FUNC168_IN_SEL_M  (GPIO_FUNC168_IN_SEL_V << GPIO_FUNC168_IN_SEL_S)
+#define GPIO_FUNC168_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC168_IN_SEL_S  0
+/** GPIO_FUNC168_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC168_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC168_IN_INV_SEL_M  (GPIO_FUNC168_IN_INV_SEL_V << GPIO_FUNC168_IN_INV_SEL_S)
+#define GPIO_FUNC168_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC168_IN_INV_SEL_S  6
+/** GPIO_SIG168_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG168_IN_SEL    (BIT(7))
+#define GPIO_SIG168_IN_SEL_M  (GPIO_SIG168_IN_SEL_V << GPIO_SIG168_IN_SEL_S)
+#define GPIO_SIG168_IN_SEL_V  0x00000001U
+#define GPIO_SIG168_IN_SEL_S  7
+
+/** GPIO_FUNC169_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc)
+/** GPIO_FUNC169_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC169_IN_SEL    0x0000003FU
+#define GPIO_FUNC169_IN_SEL_M  (GPIO_FUNC169_IN_SEL_V << GPIO_FUNC169_IN_SEL_S)
+#define GPIO_FUNC169_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC169_IN_SEL_S  0
+/** GPIO_FUNC169_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC169_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC169_IN_INV_SEL_M  (GPIO_FUNC169_IN_INV_SEL_V << GPIO_FUNC169_IN_INV_SEL_S)
+#define GPIO_FUNC169_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC169_IN_INV_SEL_S  6
+/** GPIO_SIG169_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG169_IN_SEL    (BIT(7))
+#define GPIO_SIG169_IN_SEL_M  (GPIO_SIG169_IN_SEL_V << GPIO_SIG169_IN_SEL_S)
+#define GPIO_SIG169_IN_SEL_V  0x00000001U
+#define GPIO_SIG169_IN_SEL_S  7
+
+/** GPIO_FUNC170_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x400)
+/** GPIO_FUNC170_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC170_IN_SEL    0x0000003FU
+#define GPIO_FUNC170_IN_SEL_M  (GPIO_FUNC170_IN_SEL_V << GPIO_FUNC170_IN_SEL_S)
+#define GPIO_FUNC170_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC170_IN_SEL_S  0
+/** GPIO_FUNC170_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC170_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC170_IN_INV_SEL_M  (GPIO_FUNC170_IN_INV_SEL_V << GPIO_FUNC170_IN_INV_SEL_S)
+#define GPIO_FUNC170_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC170_IN_INV_SEL_S  6
+/** GPIO_SIG170_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG170_IN_SEL    (BIT(7))
+#define GPIO_SIG170_IN_SEL_M  (GPIO_SIG170_IN_SEL_V << GPIO_SIG170_IN_SEL_S)
+#define GPIO_SIG170_IN_SEL_V  0x00000001U
+#define GPIO_SIG170_IN_SEL_S  7
+
+/** GPIO_FUNC171_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x404)
+/** GPIO_FUNC171_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC171_IN_SEL    0x0000003FU
+#define GPIO_FUNC171_IN_SEL_M  (GPIO_FUNC171_IN_SEL_V << GPIO_FUNC171_IN_SEL_S)
+#define GPIO_FUNC171_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC171_IN_SEL_S  0
+/** GPIO_FUNC171_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC171_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC171_IN_INV_SEL_M  (GPIO_FUNC171_IN_INV_SEL_V << GPIO_FUNC171_IN_INV_SEL_S)
+#define GPIO_FUNC171_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC171_IN_INV_SEL_S  6
+/** GPIO_SIG171_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG171_IN_SEL    (BIT(7))
+#define GPIO_SIG171_IN_SEL_M  (GPIO_SIG171_IN_SEL_V << GPIO_SIG171_IN_SEL_S)
+#define GPIO_SIG171_IN_SEL_V  0x00000001U
+#define GPIO_SIG171_IN_SEL_S  7
+
+/** GPIO_FUNC172_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x408)
+/** GPIO_FUNC172_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC172_IN_SEL    0x0000003FU
+#define GPIO_FUNC172_IN_SEL_M  (GPIO_FUNC172_IN_SEL_V << GPIO_FUNC172_IN_SEL_S)
+#define GPIO_FUNC172_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC172_IN_SEL_S  0
+/** GPIO_FUNC172_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC172_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC172_IN_INV_SEL_M  (GPIO_FUNC172_IN_INV_SEL_V << GPIO_FUNC172_IN_INV_SEL_S)
+#define GPIO_FUNC172_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC172_IN_INV_SEL_S  6
+/** GPIO_SIG172_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG172_IN_SEL    (BIT(7))
+#define GPIO_SIG172_IN_SEL_M  (GPIO_SIG172_IN_SEL_V << GPIO_SIG172_IN_SEL_S)
+#define GPIO_SIG172_IN_SEL_V  0x00000001U
+#define GPIO_SIG172_IN_SEL_S  7
+
+/** GPIO_FUNC173_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c)
+/** GPIO_FUNC173_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC173_IN_SEL    0x0000003FU
+#define GPIO_FUNC173_IN_SEL_M  (GPIO_FUNC173_IN_SEL_V << GPIO_FUNC173_IN_SEL_S)
+#define GPIO_FUNC173_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC173_IN_SEL_S  0
+/** GPIO_FUNC173_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC173_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC173_IN_INV_SEL_M  (GPIO_FUNC173_IN_INV_SEL_V << GPIO_FUNC173_IN_INV_SEL_S)
+#define GPIO_FUNC173_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC173_IN_INV_SEL_S  6
+/** GPIO_SIG173_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG173_IN_SEL    (BIT(7))
+#define GPIO_SIG173_IN_SEL_M  (GPIO_SIG173_IN_SEL_V << GPIO_SIG173_IN_SEL_S)
+#define GPIO_SIG173_IN_SEL_V  0x00000001U
+#define GPIO_SIG173_IN_SEL_S  7
+
+/** GPIO_FUNC174_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410)
+/** GPIO_FUNC174_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC174_IN_SEL    0x0000003FU
+#define GPIO_FUNC174_IN_SEL_M  (GPIO_FUNC174_IN_SEL_V << GPIO_FUNC174_IN_SEL_S)
+#define GPIO_FUNC174_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC174_IN_SEL_S  0
+/** GPIO_FUNC174_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC174_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC174_IN_INV_SEL_M  (GPIO_FUNC174_IN_INV_SEL_V << GPIO_FUNC174_IN_INV_SEL_S)
+#define GPIO_FUNC174_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC174_IN_INV_SEL_S  6
+/** GPIO_SIG174_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG174_IN_SEL    (BIT(7))
+#define GPIO_SIG174_IN_SEL_M  (GPIO_SIG174_IN_SEL_V << GPIO_SIG174_IN_SEL_S)
+#define GPIO_SIG174_IN_SEL_V  0x00000001U
+#define GPIO_SIG174_IN_SEL_S  7
+
+/** GPIO_FUNC175_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x414)
+/** GPIO_FUNC175_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC175_IN_SEL    0x0000003FU
+#define GPIO_FUNC175_IN_SEL_M  (GPIO_FUNC175_IN_SEL_V << GPIO_FUNC175_IN_SEL_S)
+#define GPIO_FUNC175_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC175_IN_SEL_S  0
+/** GPIO_FUNC175_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC175_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC175_IN_INV_SEL_M  (GPIO_FUNC175_IN_INV_SEL_V << GPIO_FUNC175_IN_INV_SEL_S)
+#define GPIO_FUNC175_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC175_IN_INV_SEL_S  6
+/** GPIO_SIG175_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG175_IN_SEL    (BIT(7))
+#define GPIO_SIG175_IN_SEL_M  (GPIO_SIG175_IN_SEL_V << GPIO_SIG175_IN_SEL_S)
+#define GPIO_SIG175_IN_SEL_V  0x00000001U
+#define GPIO_SIG175_IN_SEL_S  7
+
+/** GPIO_FUNC176_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x418)
+/** GPIO_FUNC176_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC176_IN_SEL    0x0000003FU
+#define GPIO_FUNC176_IN_SEL_M  (GPIO_FUNC176_IN_SEL_V << GPIO_FUNC176_IN_SEL_S)
+#define GPIO_FUNC176_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC176_IN_SEL_S  0
+/** GPIO_FUNC176_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC176_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC176_IN_INV_SEL_M  (GPIO_FUNC176_IN_INV_SEL_V << GPIO_FUNC176_IN_INV_SEL_S)
+#define GPIO_FUNC176_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC176_IN_INV_SEL_S  6
+/** GPIO_SIG176_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG176_IN_SEL    (BIT(7))
+#define GPIO_SIG176_IN_SEL_M  (GPIO_SIG176_IN_SEL_V << GPIO_SIG176_IN_SEL_S)
+#define GPIO_SIG176_IN_SEL_V  0x00000001U
+#define GPIO_SIG176_IN_SEL_S  7
+
+/** GPIO_FUNC177_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c)
+/** GPIO_FUNC177_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC177_IN_SEL    0x0000003FU
+#define GPIO_FUNC177_IN_SEL_M  (GPIO_FUNC177_IN_SEL_V << GPIO_FUNC177_IN_SEL_S)
+#define GPIO_FUNC177_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC177_IN_SEL_S  0
+/** GPIO_FUNC177_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC177_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC177_IN_INV_SEL_M  (GPIO_FUNC177_IN_INV_SEL_V << GPIO_FUNC177_IN_INV_SEL_S)
+#define GPIO_FUNC177_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC177_IN_INV_SEL_S  6
+/** GPIO_SIG177_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG177_IN_SEL    (BIT(7))
+#define GPIO_SIG177_IN_SEL_M  (GPIO_SIG177_IN_SEL_V << GPIO_SIG177_IN_SEL_S)
+#define GPIO_SIG177_IN_SEL_V  0x00000001U
+#define GPIO_SIG177_IN_SEL_S  7
+
+/** GPIO_FUNC178_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420)
+/** GPIO_FUNC178_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC178_IN_SEL    0x0000003FU
+#define GPIO_FUNC178_IN_SEL_M  (GPIO_FUNC178_IN_SEL_V << GPIO_FUNC178_IN_SEL_S)
+#define GPIO_FUNC178_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC178_IN_SEL_S  0
+/** GPIO_FUNC178_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC178_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC178_IN_INV_SEL_M  (GPIO_FUNC178_IN_INV_SEL_V << GPIO_FUNC178_IN_INV_SEL_S)
+#define GPIO_FUNC178_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC178_IN_INV_SEL_S  6
+/** GPIO_SIG178_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG178_IN_SEL    (BIT(7))
+#define GPIO_SIG178_IN_SEL_M  (GPIO_SIG178_IN_SEL_V << GPIO_SIG178_IN_SEL_S)
+#define GPIO_SIG178_IN_SEL_V  0x00000001U
+#define GPIO_SIG178_IN_SEL_S  7
+
+/** GPIO_FUNC179_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x424)
+/** GPIO_FUNC179_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC179_IN_SEL    0x0000003FU
+#define GPIO_FUNC179_IN_SEL_M  (GPIO_FUNC179_IN_SEL_V << GPIO_FUNC179_IN_SEL_S)
+#define GPIO_FUNC179_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC179_IN_SEL_S  0
+/** GPIO_FUNC179_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC179_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC179_IN_INV_SEL_M  (GPIO_FUNC179_IN_INV_SEL_V << GPIO_FUNC179_IN_INV_SEL_S)
+#define GPIO_FUNC179_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC179_IN_INV_SEL_S  6
+/** GPIO_SIG179_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG179_IN_SEL    (BIT(7))
+#define GPIO_SIG179_IN_SEL_M  (GPIO_SIG179_IN_SEL_V << GPIO_SIG179_IN_SEL_S)
+#define GPIO_SIG179_IN_SEL_V  0x00000001U
+#define GPIO_SIG179_IN_SEL_S  7
+
+/** GPIO_FUNC180_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x428)
+/** GPIO_FUNC180_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC180_IN_SEL    0x0000003FU
+#define GPIO_FUNC180_IN_SEL_M  (GPIO_FUNC180_IN_SEL_V << GPIO_FUNC180_IN_SEL_S)
+#define GPIO_FUNC180_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC180_IN_SEL_S  0
+/** GPIO_FUNC180_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC180_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC180_IN_INV_SEL_M  (GPIO_FUNC180_IN_INV_SEL_V << GPIO_FUNC180_IN_INV_SEL_S)
+#define GPIO_FUNC180_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC180_IN_INV_SEL_S  6
+/** GPIO_SIG180_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG180_IN_SEL    (BIT(7))
+#define GPIO_SIG180_IN_SEL_M  (GPIO_SIG180_IN_SEL_V << GPIO_SIG180_IN_SEL_S)
+#define GPIO_SIG180_IN_SEL_V  0x00000001U
+#define GPIO_SIG180_IN_SEL_S  7
+
+/** GPIO_FUNC181_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x42c)
+/** GPIO_FUNC181_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC181_IN_SEL    0x0000003FU
+#define GPIO_FUNC181_IN_SEL_M  (GPIO_FUNC181_IN_SEL_V << GPIO_FUNC181_IN_SEL_S)
+#define GPIO_FUNC181_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC181_IN_SEL_S  0
+/** GPIO_FUNC181_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC181_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC181_IN_INV_SEL_M  (GPIO_FUNC181_IN_INV_SEL_V << GPIO_FUNC181_IN_INV_SEL_S)
+#define GPIO_FUNC181_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC181_IN_INV_SEL_S  6
+/** GPIO_SIG181_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG181_IN_SEL    (BIT(7))
+#define GPIO_SIG181_IN_SEL_M  (GPIO_SIG181_IN_SEL_V << GPIO_SIG181_IN_SEL_S)
+#define GPIO_SIG181_IN_SEL_V  0x00000001U
+#define GPIO_SIG181_IN_SEL_S  7
+
+/** GPIO_FUNC182_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x430)
+/** GPIO_FUNC182_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC182_IN_SEL    0x0000003FU
+#define GPIO_FUNC182_IN_SEL_M  (GPIO_FUNC182_IN_SEL_V << GPIO_FUNC182_IN_SEL_S)
+#define GPIO_FUNC182_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC182_IN_SEL_S  0
+/** GPIO_FUNC182_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC182_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC182_IN_INV_SEL_M  (GPIO_FUNC182_IN_INV_SEL_V << GPIO_FUNC182_IN_INV_SEL_S)
+#define GPIO_FUNC182_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC182_IN_INV_SEL_S  6
+/** GPIO_SIG182_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG182_IN_SEL    (BIT(7))
+#define GPIO_SIG182_IN_SEL_M  (GPIO_SIG182_IN_SEL_V << GPIO_SIG182_IN_SEL_S)
+#define GPIO_SIG182_IN_SEL_V  0x00000001U
+#define GPIO_SIG182_IN_SEL_S  7
+
+/** GPIO_FUNC183_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x434)
+/** GPIO_FUNC183_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC183_IN_SEL    0x0000003FU
+#define GPIO_FUNC183_IN_SEL_M  (GPIO_FUNC183_IN_SEL_V << GPIO_FUNC183_IN_SEL_S)
+#define GPIO_FUNC183_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC183_IN_SEL_S  0
+/** GPIO_FUNC183_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC183_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC183_IN_INV_SEL_M  (GPIO_FUNC183_IN_INV_SEL_V << GPIO_FUNC183_IN_INV_SEL_S)
+#define GPIO_FUNC183_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC183_IN_INV_SEL_S  6
+/** GPIO_SIG183_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG183_IN_SEL    (BIT(7))
+#define GPIO_SIG183_IN_SEL_M  (GPIO_SIG183_IN_SEL_V << GPIO_SIG183_IN_SEL_S)
+#define GPIO_SIG183_IN_SEL_V  0x00000001U
+#define GPIO_SIG183_IN_SEL_S  7
+
+/** GPIO_FUNC184_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x438)
+/** GPIO_FUNC184_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC184_IN_SEL    0x0000003FU
+#define GPIO_FUNC184_IN_SEL_M  (GPIO_FUNC184_IN_SEL_V << GPIO_FUNC184_IN_SEL_S)
+#define GPIO_FUNC184_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC184_IN_SEL_S  0
+/** GPIO_FUNC184_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC184_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC184_IN_INV_SEL_M  (GPIO_FUNC184_IN_INV_SEL_V << GPIO_FUNC184_IN_INV_SEL_S)
+#define GPIO_FUNC184_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC184_IN_INV_SEL_S  6
+/** GPIO_SIG184_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG184_IN_SEL    (BIT(7))
+#define GPIO_SIG184_IN_SEL_M  (GPIO_SIG184_IN_SEL_V << GPIO_SIG184_IN_SEL_S)
+#define GPIO_SIG184_IN_SEL_V  0x00000001U
+#define GPIO_SIG184_IN_SEL_S  7
+
+/** GPIO_FUNC185_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x43c)
+/** GPIO_FUNC185_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC185_IN_SEL    0x0000003FU
+#define GPIO_FUNC185_IN_SEL_M  (GPIO_FUNC185_IN_SEL_V << GPIO_FUNC185_IN_SEL_S)
+#define GPIO_FUNC185_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC185_IN_SEL_S  0
+/** GPIO_FUNC185_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC185_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC185_IN_INV_SEL_M  (GPIO_FUNC185_IN_INV_SEL_V << GPIO_FUNC185_IN_INV_SEL_S)
+#define GPIO_FUNC185_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC185_IN_INV_SEL_S  6
+/** GPIO_SIG185_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG185_IN_SEL    (BIT(7))
+#define GPIO_SIG185_IN_SEL_M  (GPIO_SIG185_IN_SEL_V << GPIO_SIG185_IN_SEL_S)
+#define GPIO_SIG185_IN_SEL_V  0x00000001U
+#define GPIO_SIG185_IN_SEL_S  7
+
+/** GPIO_FUNC186_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x440)
+/** GPIO_FUNC186_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC186_IN_SEL    0x0000003FU
+#define GPIO_FUNC186_IN_SEL_M  (GPIO_FUNC186_IN_SEL_V << GPIO_FUNC186_IN_SEL_S)
+#define GPIO_FUNC186_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC186_IN_SEL_S  0
+/** GPIO_FUNC186_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC186_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC186_IN_INV_SEL_M  (GPIO_FUNC186_IN_INV_SEL_V << GPIO_FUNC186_IN_INV_SEL_S)
+#define GPIO_FUNC186_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC186_IN_INV_SEL_S  6
+/** GPIO_SIG186_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG186_IN_SEL    (BIT(7))
+#define GPIO_SIG186_IN_SEL_M  (GPIO_SIG186_IN_SEL_V << GPIO_SIG186_IN_SEL_S)
+#define GPIO_SIG186_IN_SEL_V  0x00000001U
+#define GPIO_SIG186_IN_SEL_S  7
+
+/** GPIO_FUNC187_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x444)
+/** GPIO_FUNC187_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC187_IN_SEL    0x0000003FU
+#define GPIO_FUNC187_IN_SEL_M  (GPIO_FUNC187_IN_SEL_V << GPIO_FUNC187_IN_SEL_S)
+#define GPIO_FUNC187_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC187_IN_SEL_S  0
+/** GPIO_FUNC187_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC187_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC187_IN_INV_SEL_M  (GPIO_FUNC187_IN_INV_SEL_V << GPIO_FUNC187_IN_INV_SEL_S)
+#define GPIO_FUNC187_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC187_IN_INV_SEL_S  6
+/** GPIO_SIG187_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG187_IN_SEL    (BIT(7))
+#define GPIO_SIG187_IN_SEL_M  (GPIO_SIG187_IN_SEL_V << GPIO_SIG187_IN_SEL_S)
+#define GPIO_SIG187_IN_SEL_V  0x00000001U
+#define GPIO_SIG187_IN_SEL_S  7
+
+/** GPIO_FUNC188_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448)
+/** GPIO_FUNC188_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC188_IN_SEL    0x0000003FU
+#define GPIO_FUNC188_IN_SEL_M  (GPIO_FUNC188_IN_SEL_V << GPIO_FUNC188_IN_SEL_S)
+#define GPIO_FUNC188_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC188_IN_SEL_S  0
+/** GPIO_FUNC188_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC188_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC188_IN_INV_SEL_M  (GPIO_FUNC188_IN_INV_SEL_V << GPIO_FUNC188_IN_INV_SEL_S)
+#define GPIO_FUNC188_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC188_IN_INV_SEL_S  6
+/** GPIO_SIG188_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG188_IN_SEL    (BIT(7))
+#define GPIO_SIG188_IN_SEL_M  (GPIO_SIG188_IN_SEL_V << GPIO_SIG188_IN_SEL_S)
+#define GPIO_SIG188_IN_SEL_V  0x00000001U
+#define GPIO_SIG188_IN_SEL_S  7
+
+/** GPIO_FUNC189_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c)
+/** GPIO_FUNC189_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC189_IN_SEL    0x0000003FU
+#define GPIO_FUNC189_IN_SEL_M  (GPIO_FUNC189_IN_SEL_V << GPIO_FUNC189_IN_SEL_S)
+#define GPIO_FUNC189_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC189_IN_SEL_S  0
+/** GPIO_FUNC189_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC189_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC189_IN_INV_SEL_M  (GPIO_FUNC189_IN_INV_SEL_V << GPIO_FUNC189_IN_INV_SEL_S)
+#define GPIO_FUNC189_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC189_IN_INV_SEL_S  6
+/** GPIO_SIG189_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG189_IN_SEL    (BIT(7))
+#define GPIO_SIG189_IN_SEL_M  (GPIO_SIG189_IN_SEL_V << GPIO_SIG189_IN_SEL_S)
+#define GPIO_SIG189_IN_SEL_V  0x00000001U
+#define GPIO_SIG189_IN_SEL_S  7
+
+/** GPIO_FUNC190_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450)
+/** GPIO_FUNC190_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC190_IN_SEL    0x0000003FU
+#define GPIO_FUNC190_IN_SEL_M  (GPIO_FUNC190_IN_SEL_V << GPIO_FUNC190_IN_SEL_S)
+#define GPIO_FUNC190_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC190_IN_SEL_S  0
+/** GPIO_FUNC190_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC190_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC190_IN_INV_SEL_M  (GPIO_FUNC190_IN_INV_SEL_V << GPIO_FUNC190_IN_INV_SEL_S)
+#define GPIO_FUNC190_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC190_IN_INV_SEL_S  6
+/** GPIO_SIG190_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG190_IN_SEL    (BIT(7))
+#define GPIO_SIG190_IN_SEL_M  (GPIO_SIG190_IN_SEL_V << GPIO_SIG190_IN_SEL_S)
+#define GPIO_SIG190_IN_SEL_V  0x00000001U
+#define GPIO_SIG190_IN_SEL_S  7
+
+/** GPIO_FUNC191_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454)
+/** GPIO_FUNC191_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC191_IN_SEL    0x0000003FU
+#define GPIO_FUNC191_IN_SEL_M  (GPIO_FUNC191_IN_SEL_V << GPIO_FUNC191_IN_SEL_S)
+#define GPIO_FUNC191_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC191_IN_SEL_S  0
+/** GPIO_FUNC191_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC191_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC191_IN_INV_SEL_M  (GPIO_FUNC191_IN_INV_SEL_V << GPIO_FUNC191_IN_INV_SEL_S)
+#define GPIO_FUNC191_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC191_IN_INV_SEL_S  6
+/** GPIO_SIG191_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG191_IN_SEL    (BIT(7))
+#define GPIO_SIG191_IN_SEL_M  (GPIO_SIG191_IN_SEL_V << GPIO_SIG191_IN_SEL_S)
+#define GPIO_SIG191_IN_SEL_V  0x00000001U
+#define GPIO_SIG191_IN_SEL_S  7
+
+/** GPIO_FUNC192_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458)
+/** GPIO_FUNC192_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC192_IN_SEL    0x0000003FU
+#define GPIO_FUNC192_IN_SEL_M  (GPIO_FUNC192_IN_SEL_V << GPIO_FUNC192_IN_SEL_S)
+#define GPIO_FUNC192_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC192_IN_SEL_S  0
+/** GPIO_FUNC192_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC192_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC192_IN_INV_SEL_M  (GPIO_FUNC192_IN_INV_SEL_V << GPIO_FUNC192_IN_INV_SEL_S)
+#define GPIO_FUNC192_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC192_IN_INV_SEL_S  6
+/** GPIO_SIG192_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG192_IN_SEL    (BIT(7))
+#define GPIO_SIG192_IN_SEL_M  (GPIO_SIG192_IN_SEL_V << GPIO_SIG192_IN_SEL_S)
+#define GPIO_SIG192_IN_SEL_V  0x00000001U
+#define GPIO_SIG192_IN_SEL_S  7
+
+/** GPIO_FUNC193_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c)
+/** GPIO_FUNC193_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC193_IN_SEL    0x0000003FU
+#define GPIO_FUNC193_IN_SEL_M  (GPIO_FUNC193_IN_SEL_V << GPIO_FUNC193_IN_SEL_S)
+#define GPIO_FUNC193_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC193_IN_SEL_S  0
+/** GPIO_FUNC193_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC193_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC193_IN_INV_SEL_M  (GPIO_FUNC193_IN_INV_SEL_V << GPIO_FUNC193_IN_INV_SEL_S)
+#define GPIO_FUNC193_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC193_IN_INV_SEL_S  6
+/** GPIO_SIG193_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG193_IN_SEL    (BIT(7))
+#define GPIO_SIG193_IN_SEL_M  (GPIO_SIG193_IN_SEL_V << GPIO_SIG193_IN_SEL_S)
+#define GPIO_SIG193_IN_SEL_V  0x00000001U
+#define GPIO_SIG193_IN_SEL_S  7
+
+/** GPIO_FUNC194_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460)
+/** GPIO_FUNC194_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC194_IN_SEL    0x0000003FU
+#define GPIO_FUNC194_IN_SEL_M  (GPIO_FUNC194_IN_SEL_V << GPIO_FUNC194_IN_SEL_S)
+#define GPIO_FUNC194_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC194_IN_SEL_S  0
+/** GPIO_FUNC194_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC194_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC194_IN_INV_SEL_M  (GPIO_FUNC194_IN_INV_SEL_V << GPIO_FUNC194_IN_INV_SEL_S)
+#define GPIO_FUNC194_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC194_IN_INV_SEL_S  6
+/** GPIO_SIG194_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG194_IN_SEL    (BIT(7))
+#define GPIO_SIG194_IN_SEL_M  (GPIO_SIG194_IN_SEL_V << GPIO_SIG194_IN_SEL_S)
+#define GPIO_SIG194_IN_SEL_V  0x00000001U
+#define GPIO_SIG194_IN_SEL_S  7
+
+/** GPIO_FUNC195_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464)
+/** GPIO_FUNC195_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC195_IN_SEL    0x0000003FU
+#define GPIO_FUNC195_IN_SEL_M  (GPIO_FUNC195_IN_SEL_V << GPIO_FUNC195_IN_SEL_S)
+#define GPIO_FUNC195_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC195_IN_SEL_S  0
+/** GPIO_FUNC195_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC195_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC195_IN_INV_SEL_M  (GPIO_FUNC195_IN_INV_SEL_V << GPIO_FUNC195_IN_INV_SEL_S)
+#define GPIO_FUNC195_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC195_IN_INV_SEL_S  6
+/** GPIO_SIG195_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG195_IN_SEL    (BIT(7))
+#define GPIO_SIG195_IN_SEL_M  (GPIO_SIG195_IN_SEL_V << GPIO_SIG195_IN_SEL_S)
+#define GPIO_SIG195_IN_SEL_V  0x00000001U
+#define GPIO_SIG195_IN_SEL_S  7
+
+/** GPIO_FUNC196_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x468)
+/** GPIO_FUNC196_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC196_IN_SEL    0x0000003FU
+#define GPIO_FUNC196_IN_SEL_M  (GPIO_FUNC196_IN_SEL_V << GPIO_FUNC196_IN_SEL_S)
+#define GPIO_FUNC196_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC196_IN_SEL_S  0
+/** GPIO_FUNC196_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC196_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC196_IN_INV_SEL_M  (GPIO_FUNC196_IN_INV_SEL_V << GPIO_FUNC196_IN_INV_SEL_S)
+#define GPIO_FUNC196_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC196_IN_INV_SEL_S  6
+/** GPIO_SIG196_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG196_IN_SEL    (BIT(7))
+#define GPIO_SIG196_IN_SEL_M  (GPIO_SIG196_IN_SEL_V << GPIO_SIG196_IN_SEL_S)
+#define GPIO_SIG196_IN_SEL_V  0x00000001U
+#define GPIO_SIG196_IN_SEL_S  7
+
+/** GPIO_FUNC197_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x46c)
+/** GPIO_FUNC197_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC197_IN_SEL    0x0000003FU
+#define GPIO_FUNC197_IN_SEL_M  (GPIO_FUNC197_IN_SEL_V << GPIO_FUNC197_IN_SEL_S)
+#define GPIO_FUNC197_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC197_IN_SEL_S  0
+/** GPIO_FUNC197_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC197_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC197_IN_INV_SEL_M  (GPIO_FUNC197_IN_INV_SEL_V << GPIO_FUNC197_IN_INV_SEL_S)
+#define GPIO_FUNC197_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC197_IN_INV_SEL_S  6
+/** GPIO_SIG197_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG197_IN_SEL    (BIT(7))
+#define GPIO_SIG197_IN_SEL_M  (GPIO_SIG197_IN_SEL_V << GPIO_SIG197_IN_SEL_S)
+#define GPIO_SIG197_IN_SEL_V  0x00000001U
+#define GPIO_SIG197_IN_SEL_S  7
+
+/** GPIO_FUNC198_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x470)
+/** GPIO_FUNC198_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC198_IN_SEL    0x0000003FU
+#define GPIO_FUNC198_IN_SEL_M  (GPIO_FUNC198_IN_SEL_V << GPIO_FUNC198_IN_SEL_S)
+#define GPIO_FUNC198_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC198_IN_SEL_S  0
+/** GPIO_FUNC198_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC198_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC198_IN_INV_SEL_M  (GPIO_FUNC198_IN_INV_SEL_V << GPIO_FUNC198_IN_INV_SEL_S)
+#define GPIO_FUNC198_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC198_IN_INV_SEL_S  6
+/** GPIO_SIG198_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG198_IN_SEL    (BIT(7))
+#define GPIO_SIG198_IN_SEL_M  (GPIO_SIG198_IN_SEL_V << GPIO_SIG198_IN_SEL_S)
+#define GPIO_SIG198_IN_SEL_V  0x00000001U
+#define GPIO_SIG198_IN_SEL_S  7
+
+/** GPIO_FUNC199_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x474)
+/** GPIO_FUNC199_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC199_IN_SEL    0x0000003FU
+#define GPIO_FUNC199_IN_SEL_M  (GPIO_FUNC199_IN_SEL_V << GPIO_FUNC199_IN_SEL_S)
+#define GPIO_FUNC199_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC199_IN_SEL_S  0
+/** GPIO_FUNC199_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC199_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC199_IN_INV_SEL_M  (GPIO_FUNC199_IN_INV_SEL_V << GPIO_FUNC199_IN_INV_SEL_S)
+#define GPIO_FUNC199_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC199_IN_INV_SEL_S  6
+/** GPIO_SIG199_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG199_IN_SEL    (BIT(7))
+#define GPIO_SIG199_IN_SEL_M  (GPIO_SIG199_IN_SEL_V << GPIO_SIG199_IN_SEL_S)
+#define GPIO_SIG199_IN_SEL_V  0x00000001U
+#define GPIO_SIG199_IN_SEL_S  7
+
+/** GPIO_FUNC200_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x478)
+/** GPIO_FUNC200_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC200_IN_SEL    0x0000003FU
+#define GPIO_FUNC200_IN_SEL_M  (GPIO_FUNC200_IN_SEL_V << GPIO_FUNC200_IN_SEL_S)
+#define GPIO_FUNC200_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC200_IN_SEL_S  0
+/** GPIO_FUNC200_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC200_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC200_IN_INV_SEL_M  (GPIO_FUNC200_IN_INV_SEL_V << GPIO_FUNC200_IN_INV_SEL_S)
+#define GPIO_FUNC200_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC200_IN_INV_SEL_S  6
+/** GPIO_SIG200_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG200_IN_SEL    (BIT(7))
+#define GPIO_SIG200_IN_SEL_M  (GPIO_SIG200_IN_SEL_V << GPIO_SIG200_IN_SEL_S)
+#define GPIO_SIG200_IN_SEL_V  0x00000001U
+#define GPIO_SIG200_IN_SEL_S  7
+
+/** GPIO_FUNC201_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x47c)
+/** GPIO_FUNC201_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC201_IN_SEL    0x0000003FU
+#define GPIO_FUNC201_IN_SEL_M  (GPIO_FUNC201_IN_SEL_V << GPIO_FUNC201_IN_SEL_S)
+#define GPIO_FUNC201_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC201_IN_SEL_S  0
+/** GPIO_FUNC201_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC201_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC201_IN_INV_SEL_M  (GPIO_FUNC201_IN_INV_SEL_V << GPIO_FUNC201_IN_INV_SEL_S)
+#define GPIO_FUNC201_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC201_IN_INV_SEL_S  6
+/** GPIO_SIG201_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG201_IN_SEL    (BIT(7))
+#define GPIO_SIG201_IN_SEL_M  (GPIO_SIG201_IN_SEL_V << GPIO_SIG201_IN_SEL_S)
+#define GPIO_SIG201_IN_SEL_V  0x00000001U
+#define GPIO_SIG201_IN_SEL_S  7
+
+/** GPIO_FUNC202_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x480)
+/** GPIO_FUNC202_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC202_IN_SEL    0x0000003FU
+#define GPIO_FUNC202_IN_SEL_M  (GPIO_FUNC202_IN_SEL_V << GPIO_FUNC202_IN_SEL_S)
+#define GPIO_FUNC202_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC202_IN_SEL_S  0
+/** GPIO_FUNC202_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC202_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC202_IN_INV_SEL_M  (GPIO_FUNC202_IN_INV_SEL_V << GPIO_FUNC202_IN_INV_SEL_S)
+#define GPIO_FUNC202_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC202_IN_INV_SEL_S  6
+/** GPIO_SIG202_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG202_IN_SEL    (BIT(7))
+#define GPIO_SIG202_IN_SEL_M  (GPIO_SIG202_IN_SEL_V << GPIO_SIG202_IN_SEL_S)
+#define GPIO_SIG202_IN_SEL_V  0x00000001U
+#define GPIO_SIG202_IN_SEL_S  7
+
+/** GPIO_FUNC203_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x484)
+/** GPIO_FUNC203_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC203_IN_SEL    0x0000003FU
+#define GPIO_FUNC203_IN_SEL_M  (GPIO_FUNC203_IN_SEL_V << GPIO_FUNC203_IN_SEL_S)
+#define GPIO_FUNC203_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC203_IN_SEL_S  0
+/** GPIO_FUNC203_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC203_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC203_IN_INV_SEL_M  (GPIO_FUNC203_IN_INV_SEL_V << GPIO_FUNC203_IN_INV_SEL_S)
+#define GPIO_FUNC203_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC203_IN_INV_SEL_S  6
+/** GPIO_SIG203_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG203_IN_SEL    (BIT(7))
+#define GPIO_SIG203_IN_SEL_M  (GPIO_SIG203_IN_SEL_V << GPIO_SIG203_IN_SEL_S)
+#define GPIO_SIG203_IN_SEL_V  0x00000001U
+#define GPIO_SIG203_IN_SEL_S  7
+
+/** GPIO_FUNC214_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b0)
+/** GPIO_FUNC214_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC214_IN_SEL    0x0000003FU
+#define GPIO_FUNC214_IN_SEL_M  (GPIO_FUNC214_IN_SEL_V << GPIO_FUNC214_IN_SEL_S)
+#define GPIO_FUNC214_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC214_IN_SEL_S  0
+/** GPIO_FUNC214_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC214_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC214_IN_INV_SEL_M  (GPIO_FUNC214_IN_INV_SEL_V << GPIO_FUNC214_IN_INV_SEL_S)
+#define GPIO_FUNC214_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC214_IN_INV_SEL_S  6
+/** GPIO_SIG214_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG214_IN_SEL    (BIT(7))
+#define GPIO_SIG214_IN_SEL_M  (GPIO_SIG214_IN_SEL_V << GPIO_SIG214_IN_SEL_S)
+#define GPIO_SIG214_IN_SEL_V  0x00000001U
+#define GPIO_SIG214_IN_SEL_S  7
+
+/** GPIO_FUNC215_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b4)
+/** GPIO_FUNC215_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC215_IN_SEL    0x0000003FU
+#define GPIO_FUNC215_IN_SEL_M  (GPIO_FUNC215_IN_SEL_V << GPIO_FUNC215_IN_SEL_S)
+#define GPIO_FUNC215_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC215_IN_SEL_S  0
+/** GPIO_FUNC215_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC215_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC215_IN_INV_SEL_M  (GPIO_FUNC215_IN_INV_SEL_V << GPIO_FUNC215_IN_INV_SEL_S)
+#define GPIO_FUNC215_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC215_IN_INV_SEL_S  6
+/** GPIO_SIG215_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG215_IN_SEL    (BIT(7))
+#define GPIO_SIG215_IN_SEL_M  (GPIO_SIG215_IN_SEL_V << GPIO_SIG215_IN_SEL_S)
+#define GPIO_SIG215_IN_SEL_V  0x00000001U
+#define GPIO_SIG215_IN_SEL_S  7
+
+/** GPIO_FUNC216_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b8)
+/** GPIO_FUNC216_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC216_IN_SEL    0x0000003FU
+#define GPIO_FUNC216_IN_SEL_M  (GPIO_FUNC216_IN_SEL_V << GPIO_FUNC216_IN_SEL_S)
+#define GPIO_FUNC216_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC216_IN_SEL_S  0
+/** GPIO_FUNC216_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC216_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC216_IN_INV_SEL_M  (GPIO_FUNC216_IN_INV_SEL_V << GPIO_FUNC216_IN_INV_SEL_S)
+#define GPIO_FUNC216_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC216_IN_INV_SEL_S  6
+/** GPIO_SIG216_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG216_IN_SEL    (BIT(7))
+#define GPIO_SIG216_IN_SEL_M  (GPIO_SIG216_IN_SEL_V << GPIO_SIG216_IN_SEL_S)
+#define GPIO_SIG216_IN_SEL_V  0x00000001U
+#define GPIO_SIG216_IN_SEL_S  7
+
+/** GPIO_FUNC217_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4bc)
+/** GPIO_FUNC217_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC217_IN_SEL    0x0000003FU
+#define GPIO_FUNC217_IN_SEL_M  (GPIO_FUNC217_IN_SEL_V << GPIO_FUNC217_IN_SEL_S)
+#define GPIO_FUNC217_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC217_IN_SEL_S  0
+/** GPIO_FUNC217_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC217_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC217_IN_INV_SEL_M  (GPIO_FUNC217_IN_INV_SEL_V << GPIO_FUNC217_IN_INV_SEL_S)
+#define GPIO_FUNC217_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC217_IN_INV_SEL_S  6
+/** GPIO_SIG217_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG217_IN_SEL    (BIT(7))
+#define GPIO_SIG217_IN_SEL_M  (GPIO_SIG217_IN_SEL_V << GPIO_SIG217_IN_SEL_S)
+#define GPIO_SIG217_IN_SEL_V  0x00000001U
+#define GPIO_SIG217_IN_SEL_S  7
+
+/** GPIO_FUNC218_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c0)
+/** GPIO_FUNC218_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC218_IN_SEL    0x0000003FU
+#define GPIO_FUNC218_IN_SEL_M  (GPIO_FUNC218_IN_SEL_V << GPIO_FUNC218_IN_SEL_S)
+#define GPIO_FUNC218_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC218_IN_SEL_S  0
+/** GPIO_FUNC218_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC218_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC218_IN_INV_SEL_M  (GPIO_FUNC218_IN_INV_SEL_V << GPIO_FUNC218_IN_INV_SEL_S)
+#define GPIO_FUNC218_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC218_IN_INV_SEL_S  6
+/** GPIO_SIG218_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG218_IN_SEL    (BIT(7))
+#define GPIO_SIG218_IN_SEL_M  (GPIO_SIG218_IN_SEL_V << GPIO_SIG218_IN_SEL_S)
+#define GPIO_SIG218_IN_SEL_V  0x00000001U
+#define GPIO_SIG218_IN_SEL_S  7
+
+/** GPIO_FUNC219_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c4)
+/** GPIO_FUNC219_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC219_IN_SEL    0x0000003FU
+#define GPIO_FUNC219_IN_SEL_M  (GPIO_FUNC219_IN_SEL_V << GPIO_FUNC219_IN_SEL_S)
+#define GPIO_FUNC219_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC219_IN_SEL_S  0
+/** GPIO_FUNC219_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC219_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC219_IN_INV_SEL_M  (GPIO_FUNC219_IN_INV_SEL_V << GPIO_FUNC219_IN_INV_SEL_S)
+#define GPIO_FUNC219_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC219_IN_INV_SEL_S  6
+/** GPIO_SIG219_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG219_IN_SEL    (BIT(7))
+#define GPIO_SIG219_IN_SEL_M  (GPIO_SIG219_IN_SEL_V << GPIO_SIG219_IN_SEL_S)
+#define GPIO_SIG219_IN_SEL_V  0x00000001U
+#define GPIO_SIG219_IN_SEL_S  7
+
+/** GPIO_FUNC220_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c8)
+/** GPIO_FUNC220_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC220_IN_SEL    0x0000003FU
+#define GPIO_FUNC220_IN_SEL_M  (GPIO_FUNC220_IN_SEL_V << GPIO_FUNC220_IN_SEL_S)
+#define GPIO_FUNC220_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC220_IN_SEL_S  0
+/** GPIO_FUNC220_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC220_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC220_IN_INV_SEL_M  (GPIO_FUNC220_IN_INV_SEL_V << GPIO_FUNC220_IN_INV_SEL_S)
+#define GPIO_FUNC220_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC220_IN_INV_SEL_S  6
+/** GPIO_SIG220_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG220_IN_SEL    (BIT(7))
+#define GPIO_SIG220_IN_SEL_M  (GPIO_SIG220_IN_SEL_V << GPIO_SIG220_IN_SEL_S)
+#define GPIO_SIG220_IN_SEL_V  0x00000001U
+#define GPIO_SIG220_IN_SEL_S  7
+
+/** GPIO_FUNC221_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4cc)
+/** GPIO_FUNC221_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC221_IN_SEL    0x0000003FU
+#define GPIO_FUNC221_IN_SEL_M  (GPIO_FUNC221_IN_SEL_V << GPIO_FUNC221_IN_SEL_S)
+#define GPIO_FUNC221_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC221_IN_SEL_S  0
+/** GPIO_FUNC221_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC221_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC221_IN_INV_SEL_M  (GPIO_FUNC221_IN_INV_SEL_V << GPIO_FUNC221_IN_INV_SEL_S)
+#define GPIO_FUNC221_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC221_IN_INV_SEL_S  6
+/** GPIO_SIG221_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG221_IN_SEL    (BIT(7))
+#define GPIO_SIG221_IN_SEL_M  (GPIO_SIG221_IN_SEL_V << GPIO_SIG221_IN_SEL_S)
+#define GPIO_SIG221_IN_SEL_V  0x00000001U
+#define GPIO_SIG221_IN_SEL_S  7
+
+/** GPIO_FUNC222_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d0)
+/** GPIO_FUNC222_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC222_IN_SEL    0x0000003FU
+#define GPIO_FUNC222_IN_SEL_M  (GPIO_FUNC222_IN_SEL_V << GPIO_FUNC222_IN_SEL_S)
+#define GPIO_FUNC222_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC222_IN_SEL_S  0
+/** GPIO_FUNC222_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC222_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC222_IN_INV_SEL_M  (GPIO_FUNC222_IN_INV_SEL_V << GPIO_FUNC222_IN_INV_SEL_S)
+#define GPIO_FUNC222_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC222_IN_INV_SEL_S  6
+/** GPIO_SIG222_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG222_IN_SEL    (BIT(7))
+#define GPIO_SIG222_IN_SEL_M  (GPIO_SIG222_IN_SEL_V << GPIO_SIG222_IN_SEL_S)
+#define GPIO_SIG222_IN_SEL_V  0x00000001U
+#define GPIO_SIG222_IN_SEL_S  7
+
+/** GPIO_FUNC223_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d4)
+/** GPIO_FUNC223_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC223_IN_SEL    0x0000003FU
+#define GPIO_FUNC223_IN_SEL_M  (GPIO_FUNC223_IN_SEL_V << GPIO_FUNC223_IN_SEL_S)
+#define GPIO_FUNC223_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC223_IN_SEL_S  0
+/** GPIO_FUNC223_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC223_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC223_IN_INV_SEL_M  (GPIO_FUNC223_IN_INV_SEL_V << GPIO_FUNC223_IN_INV_SEL_S)
+#define GPIO_FUNC223_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC223_IN_INV_SEL_S  6
+/** GPIO_SIG223_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG223_IN_SEL    (BIT(7))
+#define GPIO_SIG223_IN_SEL_M  (GPIO_SIG223_IN_SEL_V << GPIO_SIG223_IN_SEL_S)
+#define GPIO_SIG223_IN_SEL_V  0x00000001U
+#define GPIO_SIG223_IN_SEL_S  7
+
+/** GPIO_FUNC224_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d8)
+/** GPIO_FUNC224_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC224_IN_SEL    0x0000003FU
+#define GPIO_FUNC224_IN_SEL_M  (GPIO_FUNC224_IN_SEL_V << GPIO_FUNC224_IN_SEL_S)
+#define GPIO_FUNC224_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC224_IN_SEL_S  0
+/** GPIO_FUNC224_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC224_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC224_IN_INV_SEL_M  (GPIO_FUNC224_IN_INV_SEL_V << GPIO_FUNC224_IN_INV_SEL_S)
+#define GPIO_FUNC224_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC224_IN_INV_SEL_S  6
+/** GPIO_SIG224_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG224_IN_SEL    (BIT(7))
+#define GPIO_SIG224_IN_SEL_M  (GPIO_SIG224_IN_SEL_V << GPIO_SIG224_IN_SEL_S)
+#define GPIO_SIG224_IN_SEL_V  0x00000001U
+#define GPIO_SIG224_IN_SEL_S  7
+
+/** GPIO_FUNC225_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4dc)
+/** GPIO_FUNC225_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC225_IN_SEL    0x0000003FU
+#define GPIO_FUNC225_IN_SEL_M  (GPIO_FUNC225_IN_SEL_V << GPIO_FUNC225_IN_SEL_S)
+#define GPIO_FUNC225_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC225_IN_SEL_S  0
+/** GPIO_FUNC225_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC225_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC225_IN_INV_SEL_M  (GPIO_FUNC225_IN_INV_SEL_V << GPIO_FUNC225_IN_INV_SEL_S)
+#define GPIO_FUNC225_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC225_IN_INV_SEL_S  6
+/** GPIO_SIG225_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG225_IN_SEL    (BIT(7))
+#define GPIO_SIG225_IN_SEL_M  (GPIO_SIG225_IN_SEL_V << GPIO_SIG225_IN_SEL_S)
+#define GPIO_SIG225_IN_SEL_V  0x00000001U
+#define GPIO_SIG225_IN_SEL_S  7
+
+/** GPIO_FUNC226_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e0)
+/** GPIO_FUNC226_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC226_IN_SEL    0x0000003FU
+#define GPIO_FUNC226_IN_SEL_M  (GPIO_FUNC226_IN_SEL_V << GPIO_FUNC226_IN_SEL_S)
+#define GPIO_FUNC226_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC226_IN_SEL_S  0
+/** GPIO_FUNC226_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC226_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC226_IN_INV_SEL_M  (GPIO_FUNC226_IN_INV_SEL_V << GPIO_FUNC226_IN_INV_SEL_S)
+#define GPIO_FUNC226_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC226_IN_INV_SEL_S  6
+/** GPIO_SIG226_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG226_IN_SEL    (BIT(7))
+#define GPIO_SIG226_IN_SEL_M  (GPIO_SIG226_IN_SEL_V << GPIO_SIG226_IN_SEL_S)
+#define GPIO_SIG226_IN_SEL_V  0x00000001U
+#define GPIO_SIG226_IN_SEL_S  7
+
+/** GPIO_FUNC227_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e4)
+/** GPIO_FUNC227_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC227_IN_SEL    0x0000003FU
+#define GPIO_FUNC227_IN_SEL_M  (GPIO_FUNC227_IN_SEL_V << GPIO_FUNC227_IN_SEL_S)
+#define GPIO_FUNC227_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC227_IN_SEL_S  0
+/** GPIO_FUNC227_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC227_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC227_IN_INV_SEL_M  (GPIO_FUNC227_IN_INV_SEL_V << GPIO_FUNC227_IN_INV_SEL_S)
+#define GPIO_FUNC227_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC227_IN_INV_SEL_S  6
+/** GPIO_SIG227_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG227_IN_SEL    (BIT(7))
+#define GPIO_SIG227_IN_SEL_M  (GPIO_SIG227_IN_SEL_V << GPIO_SIG227_IN_SEL_S)
+#define GPIO_SIG227_IN_SEL_V  0x00000001U
+#define GPIO_SIG227_IN_SEL_S  7
+
+/** GPIO_FUNC228_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e8)
+/** GPIO_FUNC228_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC228_IN_SEL    0x0000003FU
+#define GPIO_FUNC228_IN_SEL_M  (GPIO_FUNC228_IN_SEL_V << GPIO_FUNC228_IN_SEL_S)
+#define GPIO_FUNC228_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC228_IN_SEL_S  0
+/** GPIO_FUNC228_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC228_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC228_IN_INV_SEL_M  (GPIO_FUNC228_IN_INV_SEL_V << GPIO_FUNC228_IN_INV_SEL_S)
+#define GPIO_FUNC228_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC228_IN_INV_SEL_S  6
+/** GPIO_SIG228_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG228_IN_SEL    (BIT(7))
+#define GPIO_SIG228_IN_SEL_M  (GPIO_SIG228_IN_SEL_V << GPIO_SIG228_IN_SEL_S)
+#define GPIO_SIG228_IN_SEL_V  0x00000001U
+#define GPIO_SIG228_IN_SEL_S  7
+
+/** GPIO_FUNC229_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ec)
+/** GPIO_FUNC229_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC229_IN_SEL    0x0000003FU
+#define GPIO_FUNC229_IN_SEL_M  (GPIO_FUNC229_IN_SEL_V << GPIO_FUNC229_IN_SEL_S)
+#define GPIO_FUNC229_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC229_IN_SEL_S  0
+/** GPIO_FUNC229_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC229_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC229_IN_INV_SEL_M  (GPIO_FUNC229_IN_INV_SEL_V << GPIO_FUNC229_IN_INV_SEL_S)
+#define GPIO_FUNC229_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC229_IN_INV_SEL_S  6
+/** GPIO_SIG229_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG229_IN_SEL    (BIT(7))
+#define GPIO_SIG229_IN_SEL_M  (GPIO_SIG229_IN_SEL_V << GPIO_SIG229_IN_SEL_S)
+#define GPIO_SIG229_IN_SEL_V  0x00000001U
+#define GPIO_SIG229_IN_SEL_S  7
+
+/** GPIO_FUNC230_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f0)
+/** GPIO_FUNC230_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC230_IN_SEL    0x0000003FU
+#define GPIO_FUNC230_IN_SEL_M  (GPIO_FUNC230_IN_SEL_V << GPIO_FUNC230_IN_SEL_S)
+#define GPIO_FUNC230_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC230_IN_SEL_S  0
+/** GPIO_FUNC230_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC230_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC230_IN_INV_SEL_M  (GPIO_FUNC230_IN_INV_SEL_V << GPIO_FUNC230_IN_INV_SEL_S)
+#define GPIO_FUNC230_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC230_IN_INV_SEL_S  6
+/** GPIO_SIG230_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG230_IN_SEL    (BIT(7))
+#define GPIO_SIG230_IN_SEL_M  (GPIO_SIG230_IN_SEL_V << GPIO_SIG230_IN_SEL_S)
+#define GPIO_SIG230_IN_SEL_V  0x00000001U
+#define GPIO_SIG230_IN_SEL_S  7
+
+/** GPIO_FUNC231_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f4)
+/** GPIO_FUNC231_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC231_IN_SEL    0x0000003FU
+#define GPIO_FUNC231_IN_SEL_M  (GPIO_FUNC231_IN_SEL_V << GPIO_FUNC231_IN_SEL_S)
+#define GPIO_FUNC231_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC231_IN_SEL_S  0
+/** GPIO_FUNC231_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC231_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC231_IN_INV_SEL_M  (GPIO_FUNC231_IN_INV_SEL_V << GPIO_FUNC231_IN_INV_SEL_S)
+#define GPIO_FUNC231_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC231_IN_INV_SEL_S  6
+/** GPIO_SIG231_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG231_IN_SEL    (BIT(7))
+#define GPIO_SIG231_IN_SEL_M  (GPIO_SIG231_IN_SEL_V << GPIO_SIG231_IN_SEL_S)
+#define GPIO_SIG231_IN_SEL_V  0x00000001U
+#define GPIO_SIG231_IN_SEL_S  7
+
+/** GPIO_FUNC232_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f8)
+/** GPIO_FUNC232_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC232_IN_SEL    0x0000003FU
+#define GPIO_FUNC232_IN_SEL_M  (GPIO_FUNC232_IN_SEL_V << GPIO_FUNC232_IN_SEL_S)
+#define GPIO_FUNC232_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC232_IN_SEL_S  0
+/** GPIO_FUNC232_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC232_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC232_IN_INV_SEL_M  (GPIO_FUNC232_IN_INV_SEL_V << GPIO_FUNC232_IN_INV_SEL_S)
+#define GPIO_FUNC232_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC232_IN_INV_SEL_S  6
+/** GPIO_SIG232_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG232_IN_SEL    (BIT(7))
+#define GPIO_SIG232_IN_SEL_M  (GPIO_SIG232_IN_SEL_V << GPIO_SIG232_IN_SEL_S)
+#define GPIO_SIG232_IN_SEL_V  0x00000001U
+#define GPIO_SIG232_IN_SEL_S  7
+
+/** GPIO_FUNC233_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4fc)
+/** GPIO_FUNC233_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC233_IN_SEL    0x0000003FU
+#define GPIO_FUNC233_IN_SEL_M  (GPIO_FUNC233_IN_SEL_V << GPIO_FUNC233_IN_SEL_S)
+#define GPIO_FUNC233_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC233_IN_SEL_S  0
+/** GPIO_FUNC233_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC233_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC233_IN_INV_SEL_M  (GPIO_FUNC233_IN_INV_SEL_V << GPIO_FUNC233_IN_INV_SEL_S)
+#define GPIO_FUNC233_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC233_IN_INV_SEL_S  6
+/** GPIO_SIG233_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG233_IN_SEL    (BIT(7))
+#define GPIO_SIG233_IN_SEL_M  (GPIO_SIG233_IN_SEL_V << GPIO_SIG233_IN_SEL_S)
+#define GPIO_SIG233_IN_SEL_V  0x00000001U
+#define GPIO_SIG233_IN_SEL_S  7
+
+/** GPIO_FUNC234_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x500)
+/** GPIO_FUNC234_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC234_IN_SEL    0x0000003FU
+#define GPIO_FUNC234_IN_SEL_M  (GPIO_FUNC234_IN_SEL_V << GPIO_FUNC234_IN_SEL_S)
+#define GPIO_FUNC234_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC234_IN_SEL_S  0
+/** GPIO_FUNC234_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC234_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC234_IN_INV_SEL_M  (GPIO_FUNC234_IN_INV_SEL_V << GPIO_FUNC234_IN_INV_SEL_S)
+#define GPIO_FUNC234_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC234_IN_INV_SEL_S  6
+/** GPIO_SIG234_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG234_IN_SEL    (BIT(7))
+#define GPIO_SIG234_IN_SEL_M  (GPIO_SIG234_IN_SEL_V << GPIO_SIG234_IN_SEL_S)
+#define GPIO_SIG234_IN_SEL_V  0x00000001U
+#define GPIO_SIG234_IN_SEL_S  7
+
+/** GPIO_FUNC235_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x504)
+/** GPIO_FUNC235_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC235_IN_SEL    0x0000003FU
+#define GPIO_FUNC235_IN_SEL_M  (GPIO_FUNC235_IN_SEL_V << GPIO_FUNC235_IN_SEL_S)
+#define GPIO_FUNC235_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC235_IN_SEL_S  0
+/** GPIO_FUNC235_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC235_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC235_IN_INV_SEL_M  (GPIO_FUNC235_IN_INV_SEL_V << GPIO_FUNC235_IN_INV_SEL_S)
+#define GPIO_FUNC235_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC235_IN_INV_SEL_S  6
+/** GPIO_SIG235_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG235_IN_SEL    (BIT(7))
+#define GPIO_SIG235_IN_SEL_M  (GPIO_SIG235_IN_SEL_V << GPIO_SIG235_IN_SEL_S)
+#define GPIO_SIG235_IN_SEL_V  0x00000001U
+#define GPIO_SIG235_IN_SEL_S  7
+
+/** GPIO_FUNC236_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x508)
+/** GPIO_FUNC236_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC236_IN_SEL    0x0000003FU
+#define GPIO_FUNC236_IN_SEL_M  (GPIO_FUNC236_IN_SEL_V << GPIO_FUNC236_IN_SEL_S)
+#define GPIO_FUNC236_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC236_IN_SEL_S  0
+/** GPIO_FUNC236_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC236_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC236_IN_INV_SEL_M  (GPIO_FUNC236_IN_INV_SEL_V << GPIO_FUNC236_IN_INV_SEL_S)
+#define GPIO_FUNC236_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC236_IN_INV_SEL_S  6
+/** GPIO_SIG236_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG236_IN_SEL    (BIT(7))
+#define GPIO_SIG236_IN_SEL_M  (GPIO_SIG236_IN_SEL_V << GPIO_SIG236_IN_SEL_S)
+#define GPIO_SIG236_IN_SEL_V  0x00000001U
+#define GPIO_SIG236_IN_SEL_S  7
+
+/** GPIO_FUNC237_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x50c)
+/** GPIO_FUNC237_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC237_IN_SEL    0x0000003FU
+#define GPIO_FUNC237_IN_SEL_M  (GPIO_FUNC237_IN_SEL_V << GPIO_FUNC237_IN_SEL_S)
+#define GPIO_FUNC237_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC237_IN_SEL_S  0
+/** GPIO_FUNC237_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC237_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC237_IN_INV_SEL_M  (GPIO_FUNC237_IN_INV_SEL_V << GPIO_FUNC237_IN_INV_SEL_S)
+#define GPIO_FUNC237_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC237_IN_INV_SEL_S  6
+/** GPIO_SIG237_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG237_IN_SEL    (BIT(7))
+#define GPIO_SIG237_IN_SEL_M  (GPIO_SIG237_IN_SEL_V << GPIO_SIG237_IN_SEL_S)
+#define GPIO_SIG237_IN_SEL_V  0x00000001U
+#define GPIO_SIG237_IN_SEL_S  7
+
+/** GPIO_FUNC238_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x510)
+/** GPIO_FUNC238_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC238_IN_SEL    0x0000003FU
+#define GPIO_FUNC238_IN_SEL_M  (GPIO_FUNC238_IN_SEL_V << GPIO_FUNC238_IN_SEL_S)
+#define GPIO_FUNC238_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC238_IN_SEL_S  0
+/** GPIO_FUNC238_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC238_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC238_IN_INV_SEL_M  (GPIO_FUNC238_IN_INV_SEL_V << GPIO_FUNC238_IN_INV_SEL_S)
+#define GPIO_FUNC238_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC238_IN_INV_SEL_S  6
+/** GPIO_SIG238_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG238_IN_SEL    (BIT(7))
+#define GPIO_SIG238_IN_SEL_M  (GPIO_SIG238_IN_SEL_V << GPIO_SIG238_IN_SEL_S)
+#define GPIO_SIG238_IN_SEL_V  0x00000001U
+#define GPIO_SIG238_IN_SEL_S  7
+
+/** GPIO_FUNC239_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x514)
+/** GPIO_FUNC239_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC239_IN_SEL    0x0000003FU
+#define GPIO_FUNC239_IN_SEL_M  (GPIO_FUNC239_IN_SEL_V << GPIO_FUNC239_IN_SEL_S)
+#define GPIO_FUNC239_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC239_IN_SEL_S  0
+/** GPIO_FUNC239_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC239_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC239_IN_INV_SEL_M  (GPIO_FUNC239_IN_INV_SEL_V << GPIO_FUNC239_IN_INV_SEL_S)
+#define GPIO_FUNC239_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC239_IN_INV_SEL_S  6
+/** GPIO_SIG239_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG239_IN_SEL    (BIT(7))
+#define GPIO_SIG239_IN_SEL_M  (GPIO_SIG239_IN_SEL_V << GPIO_SIG239_IN_SEL_S)
+#define GPIO_SIG239_IN_SEL_V  0x00000001U
+#define GPIO_SIG239_IN_SEL_S  7
+
+/** GPIO_FUNC240_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x518)
+/** GPIO_FUNC240_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC240_IN_SEL    0x0000003FU
+#define GPIO_FUNC240_IN_SEL_M  (GPIO_FUNC240_IN_SEL_V << GPIO_FUNC240_IN_SEL_S)
+#define GPIO_FUNC240_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC240_IN_SEL_S  0
+/** GPIO_FUNC240_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC240_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC240_IN_INV_SEL_M  (GPIO_FUNC240_IN_INV_SEL_V << GPIO_FUNC240_IN_INV_SEL_S)
+#define GPIO_FUNC240_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC240_IN_INV_SEL_S  6
+/** GPIO_SIG240_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG240_IN_SEL    (BIT(7))
+#define GPIO_SIG240_IN_SEL_M  (GPIO_SIG240_IN_SEL_V << GPIO_SIG240_IN_SEL_S)
+#define GPIO_SIG240_IN_SEL_V  0x00000001U
+#define GPIO_SIG240_IN_SEL_S  7
+
+/** GPIO_FUNC241_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x51c)
+/** GPIO_FUNC241_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC241_IN_SEL    0x0000003FU
+#define GPIO_FUNC241_IN_SEL_M  (GPIO_FUNC241_IN_SEL_V << GPIO_FUNC241_IN_SEL_S)
+#define GPIO_FUNC241_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC241_IN_SEL_S  0
+/** GPIO_FUNC241_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC241_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC241_IN_INV_SEL_M  (GPIO_FUNC241_IN_INV_SEL_V << GPIO_FUNC241_IN_INV_SEL_S)
+#define GPIO_FUNC241_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC241_IN_INV_SEL_S  6
+/** GPIO_SIG241_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG241_IN_SEL    (BIT(7))
+#define GPIO_SIG241_IN_SEL_M  (GPIO_SIG241_IN_SEL_V << GPIO_SIG241_IN_SEL_S)
+#define GPIO_SIG241_IN_SEL_V  0x00000001U
+#define GPIO_SIG241_IN_SEL_S  7
+
+/** GPIO_FUNC242_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x520)
+/** GPIO_FUNC242_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC242_IN_SEL    0x0000003FU
+#define GPIO_FUNC242_IN_SEL_M  (GPIO_FUNC242_IN_SEL_V << GPIO_FUNC242_IN_SEL_S)
+#define GPIO_FUNC242_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC242_IN_SEL_S  0
+/** GPIO_FUNC242_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC242_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC242_IN_INV_SEL_M  (GPIO_FUNC242_IN_INV_SEL_V << GPIO_FUNC242_IN_INV_SEL_S)
+#define GPIO_FUNC242_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC242_IN_INV_SEL_S  6
+/** GPIO_SIG242_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG242_IN_SEL    (BIT(7))
+#define GPIO_SIG242_IN_SEL_M  (GPIO_SIG242_IN_SEL_V << GPIO_SIG242_IN_SEL_S)
+#define GPIO_SIG242_IN_SEL_V  0x00000001U
+#define GPIO_SIG242_IN_SEL_S  7
+
+/** GPIO_FUNC243_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x524)
+/** GPIO_FUNC243_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC243_IN_SEL    0x0000003FU
+#define GPIO_FUNC243_IN_SEL_M  (GPIO_FUNC243_IN_SEL_V << GPIO_FUNC243_IN_SEL_S)
+#define GPIO_FUNC243_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC243_IN_SEL_S  0
+/** GPIO_FUNC243_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC243_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC243_IN_INV_SEL_M  (GPIO_FUNC243_IN_INV_SEL_V << GPIO_FUNC243_IN_INV_SEL_S)
+#define GPIO_FUNC243_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC243_IN_INV_SEL_S  6
+/** GPIO_SIG243_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG243_IN_SEL    (BIT(7))
+#define GPIO_SIG243_IN_SEL_M  (GPIO_SIG243_IN_SEL_V << GPIO_SIG243_IN_SEL_S)
+#define GPIO_SIG243_IN_SEL_V  0x00000001U
+#define GPIO_SIG243_IN_SEL_S  7
+
+/** GPIO_FUNC244_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x528)
+/** GPIO_FUNC244_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC244_IN_SEL    0x0000003FU
+#define GPIO_FUNC244_IN_SEL_M  (GPIO_FUNC244_IN_SEL_V << GPIO_FUNC244_IN_SEL_S)
+#define GPIO_FUNC244_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC244_IN_SEL_S  0
+/** GPIO_FUNC244_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC244_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC244_IN_INV_SEL_M  (GPIO_FUNC244_IN_INV_SEL_V << GPIO_FUNC244_IN_INV_SEL_S)
+#define GPIO_FUNC244_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC244_IN_INV_SEL_S  6
+/** GPIO_SIG244_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG244_IN_SEL    (BIT(7))
+#define GPIO_SIG244_IN_SEL_M  (GPIO_SIG244_IN_SEL_V << GPIO_SIG244_IN_SEL_S)
+#define GPIO_SIG244_IN_SEL_V  0x00000001U
+#define GPIO_SIG244_IN_SEL_S  7
+
+/** GPIO_FUNC245_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x52c)
+/** GPIO_FUNC245_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC245_IN_SEL    0x0000003FU
+#define GPIO_FUNC245_IN_SEL_M  (GPIO_FUNC245_IN_SEL_V << GPIO_FUNC245_IN_SEL_S)
+#define GPIO_FUNC245_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC245_IN_SEL_S  0
+/** GPIO_FUNC245_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC245_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC245_IN_INV_SEL_M  (GPIO_FUNC245_IN_INV_SEL_V << GPIO_FUNC245_IN_INV_SEL_S)
+#define GPIO_FUNC245_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC245_IN_INV_SEL_S  6
+/** GPIO_SIG245_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG245_IN_SEL    (BIT(7))
+#define GPIO_SIG245_IN_SEL_M  (GPIO_SIG245_IN_SEL_V << GPIO_SIG245_IN_SEL_S)
+#define GPIO_SIG245_IN_SEL_V  0x00000001U
+#define GPIO_SIG245_IN_SEL_S  7
+
+/** GPIO_FUNC246_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x530)
+/** GPIO_FUNC246_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC246_IN_SEL    0x0000003FU
+#define GPIO_FUNC246_IN_SEL_M  (GPIO_FUNC246_IN_SEL_V << GPIO_FUNC246_IN_SEL_S)
+#define GPIO_FUNC246_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC246_IN_SEL_S  0
+/** GPIO_FUNC246_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC246_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC246_IN_INV_SEL_M  (GPIO_FUNC246_IN_INV_SEL_V << GPIO_FUNC246_IN_INV_SEL_S)
+#define GPIO_FUNC246_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC246_IN_INV_SEL_S  6
+/** GPIO_SIG246_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG246_IN_SEL    (BIT(7))
+#define GPIO_SIG246_IN_SEL_M  (GPIO_SIG246_IN_SEL_V << GPIO_SIG246_IN_SEL_S)
+#define GPIO_SIG246_IN_SEL_V  0x00000001U
+#define GPIO_SIG246_IN_SEL_S  7
+
+/** GPIO_FUNC247_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x534)
+/** GPIO_FUNC247_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC247_IN_SEL    0x0000003FU
+#define GPIO_FUNC247_IN_SEL_M  (GPIO_FUNC247_IN_SEL_V << GPIO_FUNC247_IN_SEL_S)
+#define GPIO_FUNC247_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC247_IN_SEL_S  0
+/** GPIO_FUNC247_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC247_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC247_IN_INV_SEL_M  (GPIO_FUNC247_IN_INV_SEL_V << GPIO_FUNC247_IN_INV_SEL_S)
+#define GPIO_FUNC247_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC247_IN_INV_SEL_S  6
+/** GPIO_SIG247_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG247_IN_SEL    (BIT(7))
+#define GPIO_SIG247_IN_SEL_M  (GPIO_SIG247_IN_SEL_V << GPIO_SIG247_IN_SEL_S)
+#define GPIO_SIG247_IN_SEL_V  0x00000001U
+#define GPIO_SIG247_IN_SEL_S  7
+
+/** GPIO_FUNC248_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x538)
+/** GPIO_FUNC248_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC248_IN_SEL    0x0000003FU
+#define GPIO_FUNC248_IN_SEL_M  (GPIO_FUNC248_IN_SEL_V << GPIO_FUNC248_IN_SEL_S)
+#define GPIO_FUNC248_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC248_IN_SEL_S  0
+/** GPIO_FUNC248_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC248_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC248_IN_INV_SEL_M  (GPIO_FUNC248_IN_INV_SEL_V << GPIO_FUNC248_IN_INV_SEL_S)
+#define GPIO_FUNC248_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC248_IN_INV_SEL_S  6
+/** GPIO_SIG248_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG248_IN_SEL    (BIT(7))
+#define GPIO_SIG248_IN_SEL_M  (GPIO_SIG248_IN_SEL_V << GPIO_SIG248_IN_SEL_S)
+#define GPIO_SIG248_IN_SEL_V  0x00000001U
+#define GPIO_SIG248_IN_SEL_S  7
+
+/** GPIO_FUNC249_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x53c)
+/** GPIO_FUNC249_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC249_IN_SEL    0x0000003FU
+#define GPIO_FUNC249_IN_SEL_M  (GPIO_FUNC249_IN_SEL_V << GPIO_FUNC249_IN_SEL_S)
+#define GPIO_FUNC249_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC249_IN_SEL_S  0
+/** GPIO_FUNC249_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC249_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC249_IN_INV_SEL_M  (GPIO_FUNC249_IN_INV_SEL_V << GPIO_FUNC249_IN_INV_SEL_S)
+#define GPIO_FUNC249_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC249_IN_INV_SEL_S  6
+/** GPIO_SIG249_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG249_IN_SEL    (BIT(7))
+#define GPIO_SIG249_IN_SEL_M  (GPIO_SIG249_IN_SEL_V << GPIO_SIG249_IN_SEL_S)
+#define GPIO_SIG249_IN_SEL_V  0x00000001U
+#define GPIO_SIG249_IN_SEL_S  7
+
+/** GPIO_FUNC250_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x540)
+/** GPIO_FUNC250_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC250_IN_SEL    0x0000003FU
+#define GPIO_FUNC250_IN_SEL_M  (GPIO_FUNC250_IN_SEL_V << GPIO_FUNC250_IN_SEL_S)
+#define GPIO_FUNC250_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC250_IN_SEL_S  0
+/** GPIO_FUNC250_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC250_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC250_IN_INV_SEL_M  (GPIO_FUNC250_IN_INV_SEL_V << GPIO_FUNC250_IN_INV_SEL_S)
+#define GPIO_FUNC250_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC250_IN_INV_SEL_S  6
+/** GPIO_SIG250_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG250_IN_SEL    (BIT(7))
+#define GPIO_SIG250_IN_SEL_M  (GPIO_SIG250_IN_SEL_V << GPIO_SIG250_IN_SEL_S)
+#define GPIO_SIG250_IN_SEL_V  0x00000001U
+#define GPIO_SIG250_IN_SEL_S  7
+
+/** GPIO_FUNC251_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x544)
+/** GPIO_FUNC251_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC251_IN_SEL    0x0000003FU
+#define GPIO_FUNC251_IN_SEL_M  (GPIO_FUNC251_IN_SEL_V << GPIO_FUNC251_IN_SEL_S)
+#define GPIO_FUNC251_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC251_IN_SEL_S  0
+/** GPIO_FUNC251_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC251_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC251_IN_INV_SEL_M  (GPIO_FUNC251_IN_INV_SEL_V << GPIO_FUNC251_IN_INV_SEL_S)
+#define GPIO_FUNC251_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC251_IN_INV_SEL_S  6
+/** GPIO_SIG251_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG251_IN_SEL    (BIT(7))
+#define GPIO_SIG251_IN_SEL_M  (GPIO_SIG251_IN_SEL_V << GPIO_SIG251_IN_SEL_S)
+#define GPIO_SIG251_IN_SEL_V  0x00000001U
+#define GPIO_SIG251_IN_SEL_S  7
+
+/** GPIO_FUNC252_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x548)
+/** GPIO_FUNC252_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC252_IN_SEL    0x0000003FU
+#define GPIO_FUNC252_IN_SEL_M  (GPIO_FUNC252_IN_SEL_V << GPIO_FUNC252_IN_SEL_S)
+#define GPIO_FUNC252_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC252_IN_SEL_S  0
+/** GPIO_FUNC252_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC252_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC252_IN_INV_SEL_M  (GPIO_FUNC252_IN_INV_SEL_V << GPIO_FUNC252_IN_INV_SEL_S)
+#define GPIO_FUNC252_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC252_IN_INV_SEL_S  6
+/** GPIO_SIG252_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG252_IN_SEL    (BIT(7))
+#define GPIO_SIG252_IN_SEL_M  (GPIO_SIG252_IN_SEL_V << GPIO_SIG252_IN_SEL_S)
+#define GPIO_SIG252_IN_SEL_V  0x00000001U
+#define GPIO_SIG252_IN_SEL_S  7
+
+/** GPIO_FUNC253_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x54c)
+/** GPIO_FUNC253_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC253_IN_SEL    0x0000003FU
+#define GPIO_FUNC253_IN_SEL_M  (GPIO_FUNC253_IN_SEL_V << GPIO_FUNC253_IN_SEL_S)
+#define GPIO_FUNC253_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC253_IN_SEL_S  0
+/** GPIO_FUNC253_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC253_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC253_IN_INV_SEL_M  (GPIO_FUNC253_IN_INV_SEL_V << GPIO_FUNC253_IN_INV_SEL_S)
+#define GPIO_FUNC253_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC253_IN_INV_SEL_S  6
+/** GPIO_SIG253_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG253_IN_SEL    (BIT(7))
+#define GPIO_SIG253_IN_SEL_M  (GPIO_SIG253_IN_SEL_V << GPIO_SIG253_IN_SEL_S)
+#define GPIO_SIG253_IN_SEL_V  0x00000001U
+#define GPIO_SIG253_IN_SEL_S  7
+
+/** GPIO_FUNC254_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x550)
+/** GPIO_FUNC254_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC254_IN_SEL    0x0000003FU
+#define GPIO_FUNC254_IN_SEL_M  (GPIO_FUNC254_IN_SEL_V << GPIO_FUNC254_IN_SEL_S)
+#define GPIO_FUNC254_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC254_IN_SEL_S  0
+/** GPIO_FUNC254_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC254_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC254_IN_INV_SEL_M  (GPIO_FUNC254_IN_INV_SEL_V << GPIO_FUNC254_IN_INV_SEL_S)
+#define GPIO_FUNC254_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC254_IN_INV_SEL_S  6
+/** GPIO_SIG254_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG254_IN_SEL    (BIT(7))
+#define GPIO_SIG254_IN_SEL_M  (GPIO_SIG254_IN_SEL_V << GPIO_SIG254_IN_SEL_S)
+#define GPIO_SIG254_IN_SEL_V  0x00000001U
+#define GPIO_SIG254_IN_SEL_S  7
+
+/** GPIO_FUNC255_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554)
+/** GPIO_FUNC255_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC255_IN_SEL    0x0000003FU
+#define GPIO_FUNC255_IN_SEL_M  (GPIO_FUNC255_IN_SEL_V << GPIO_FUNC255_IN_SEL_S)
+#define GPIO_FUNC255_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC255_IN_SEL_S  0
+/** GPIO_FUNC255_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC255_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC255_IN_INV_SEL_M  (GPIO_FUNC255_IN_INV_SEL_V << GPIO_FUNC255_IN_INV_SEL_S)
+#define GPIO_FUNC255_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC255_IN_INV_SEL_S  6
+/** GPIO_SIG255_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG255_IN_SEL    (BIT(7))
+#define GPIO_SIG255_IN_SEL_M  (GPIO_SIG255_IN_SEL_V << GPIO_SIG255_IN_SEL_S)
+#define GPIO_SIG255_IN_SEL_V  0x00000001U
+#define GPIO_SIG255_IN_SEL_S  7
+
+/** GPIO_FUNC0_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558)
+/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC0_OUT_SEL    0x000001FFU
+#define GPIO_FUNC0_OUT_SEL_M  (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S)
+#define GPIO_FUNC0_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC0_OUT_SEL_S  0
+/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC0_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_M  (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S)
+#define GPIO_FUNC0_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OUT_INV_SEL_S  9
+/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC0_OEN_SEL    (BIT(10))
+#define GPIO_FUNC0_OEN_SEL_M  (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S)
+#define GPIO_FUNC0_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC0_OEN_SEL_S  10
+/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC0_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC0_OEN_INV_SEL_M  (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S)
+#define GPIO_FUNC0_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC1_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c)
+/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC1_OUT_SEL    0x000001FFU
+#define GPIO_FUNC1_OUT_SEL_M  (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S)
+#define GPIO_FUNC1_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC1_OUT_SEL_S  0
+/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC1_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_M  (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S)
+#define GPIO_FUNC1_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OUT_INV_SEL_S  9
+/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC1_OEN_SEL    (BIT(10))
+#define GPIO_FUNC1_OEN_SEL_M  (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S)
+#define GPIO_FUNC1_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC1_OEN_SEL_S  10
+/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC1_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC1_OEN_INV_SEL_M  (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S)
+#define GPIO_FUNC1_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC2_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560)
+/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC2_OUT_SEL    0x000001FFU
+#define GPIO_FUNC2_OUT_SEL_M  (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S)
+#define GPIO_FUNC2_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC2_OUT_SEL_S  0
+/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC2_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_M  (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S)
+#define GPIO_FUNC2_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OUT_INV_SEL_S  9
+/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC2_OEN_SEL    (BIT(10))
+#define GPIO_FUNC2_OEN_SEL_M  (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S)
+#define GPIO_FUNC2_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC2_OEN_SEL_S  10
+/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC2_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC2_OEN_INV_SEL_M  (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S)
+#define GPIO_FUNC2_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC3_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564)
+/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC3_OUT_SEL    0x000001FFU
+#define GPIO_FUNC3_OUT_SEL_M  (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S)
+#define GPIO_FUNC3_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC3_OUT_SEL_S  0
+/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC3_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_M  (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S)
+#define GPIO_FUNC3_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OUT_INV_SEL_S  9
+/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC3_OEN_SEL    (BIT(10))
+#define GPIO_FUNC3_OEN_SEL_M  (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S)
+#define GPIO_FUNC3_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC3_OEN_SEL_S  10
+/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC3_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC3_OEN_INV_SEL_M  (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S)
+#define GPIO_FUNC3_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC4_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568)
+/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC4_OUT_SEL    0x000001FFU
+#define GPIO_FUNC4_OUT_SEL_M  (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S)
+#define GPIO_FUNC4_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC4_OUT_SEL_S  0
+/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC4_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_M  (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S)
+#define GPIO_FUNC4_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OUT_INV_SEL_S  9
+/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC4_OEN_SEL    (BIT(10))
+#define GPIO_FUNC4_OEN_SEL_M  (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S)
+#define GPIO_FUNC4_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC4_OEN_SEL_S  10
+/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC4_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC4_OEN_INV_SEL_M  (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S)
+#define GPIO_FUNC4_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC5_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c)
+/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC5_OUT_SEL    0x000001FFU
+#define GPIO_FUNC5_OUT_SEL_M  (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S)
+#define GPIO_FUNC5_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC5_OUT_SEL_S  0
+/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC5_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_M  (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S)
+#define GPIO_FUNC5_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OUT_INV_SEL_S  9
+/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC5_OEN_SEL    (BIT(10))
+#define GPIO_FUNC5_OEN_SEL_M  (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S)
+#define GPIO_FUNC5_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC5_OEN_SEL_S  10
+/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC5_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC5_OEN_INV_SEL_M  (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S)
+#define GPIO_FUNC5_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC6_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570)
+/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC6_OUT_SEL    0x000001FFU
+#define GPIO_FUNC6_OUT_SEL_M  (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S)
+#define GPIO_FUNC6_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC6_OUT_SEL_S  0
+/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC6_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_M  (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S)
+#define GPIO_FUNC6_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OUT_INV_SEL_S  9
+/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC6_OEN_SEL    (BIT(10))
+#define GPIO_FUNC6_OEN_SEL_M  (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S)
+#define GPIO_FUNC6_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC6_OEN_SEL_S  10
+/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC6_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC6_OEN_INV_SEL_M  (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S)
+#define GPIO_FUNC6_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC7_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574)
+/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC7_OUT_SEL    0x000001FFU
+#define GPIO_FUNC7_OUT_SEL_M  (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S)
+#define GPIO_FUNC7_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC7_OUT_SEL_S  0
+/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC7_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_M  (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S)
+#define GPIO_FUNC7_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OUT_INV_SEL_S  9
+/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC7_OEN_SEL    (BIT(10))
+#define GPIO_FUNC7_OEN_SEL_M  (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S)
+#define GPIO_FUNC7_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC7_OEN_SEL_S  10
+/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC7_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC7_OEN_INV_SEL_M  (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S)
+#define GPIO_FUNC7_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC8_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578)
+/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC8_OUT_SEL    0x000001FFU
+#define GPIO_FUNC8_OUT_SEL_M  (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S)
+#define GPIO_FUNC8_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC8_OUT_SEL_S  0
+/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC8_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_M  (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S)
+#define GPIO_FUNC8_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OUT_INV_SEL_S  9
+/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC8_OEN_SEL    (BIT(10))
+#define GPIO_FUNC8_OEN_SEL_M  (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S)
+#define GPIO_FUNC8_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC8_OEN_SEL_S  10
+/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC8_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC8_OEN_INV_SEL_M  (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S)
+#define GPIO_FUNC8_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC9_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c)
+/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC9_OUT_SEL    0x000001FFU
+#define GPIO_FUNC9_OUT_SEL_M  (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S)
+#define GPIO_FUNC9_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC9_OUT_SEL_S  0
+/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC9_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_M  (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S)
+#define GPIO_FUNC9_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OUT_INV_SEL_S  9
+/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC9_OEN_SEL    (BIT(10))
+#define GPIO_FUNC9_OEN_SEL_M  (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S)
+#define GPIO_FUNC9_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC9_OEN_SEL_S  10
+/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC9_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC9_OEN_INV_SEL_M  (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S)
+#define GPIO_FUNC9_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC10_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580)
+/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC10_OUT_SEL    0x000001FFU
+#define GPIO_FUNC10_OUT_SEL_M  (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S)
+#define GPIO_FUNC10_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC10_OUT_SEL_S  0
+/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC10_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_M  (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S)
+#define GPIO_FUNC10_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OUT_INV_SEL_S  9
+/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC10_OEN_SEL    (BIT(10))
+#define GPIO_FUNC10_OEN_SEL_M  (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S)
+#define GPIO_FUNC10_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC10_OEN_SEL_S  10
+/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC10_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC10_OEN_INV_SEL_M  (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S)
+#define GPIO_FUNC10_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC11_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584)
+/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC11_OUT_SEL    0x000001FFU
+#define GPIO_FUNC11_OUT_SEL_M  (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S)
+#define GPIO_FUNC11_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC11_OUT_SEL_S  0
+/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC11_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_M  (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S)
+#define GPIO_FUNC11_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OUT_INV_SEL_S  9
+/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC11_OEN_SEL    (BIT(10))
+#define GPIO_FUNC11_OEN_SEL_M  (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S)
+#define GPIO_FUNC11_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC11_OEN_SEL_S  10
+/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC11_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC11_OEN_INV_SEL_M  (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S)
+#define GPIO_FUNC11_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC12_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588)
+/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC12_OUT_SEL    0x000001FFU
+#define GPIO_FUNC12_OUT_SEL_M  (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S)
+#define GPIO_FUNC12_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC12_OUT_SEL_S  0
+/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC12_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_M  (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S)
+#define GPIO_FUNC12_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OUT_INV_SEL_S  9
+/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC12_OEN_SEL    (BIT(10))
+#define GPIO_FUNC12_OEN_SEL_M  (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S)
+#define GPIO_FUNC12_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC12_OEN_SEL_S  10
+/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC12_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC12_OEN_INV_SEL_M  (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S)
+#define GPIO_FUNC12_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC13_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c)
+/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC13_OUT_SEL    0x000001FFU
+#define GPIO_FUNC13_OUT_SEL_M  (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S)
+#define GPIO_FUNC13_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC13_OUT_SEL_S  0
+/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC13_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_M  (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S)
+#define GPIO_FUNC13_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OUT_INV_SEL_S  9
+/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC13_OEN_SEL    (BIT(10))
+#define GPIO_FUNC13_OEN_SEL_M  (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S)
+#define GPIO_FUNC13_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC13_OEN_SEL_S  10
+/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC13_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC13_OEN_INV_SEL_M  (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S)
+#define GPIO_FUNC13_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC14_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590)
+/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC14_OUT_SEL    0x000001FFU
+#define GPIO_FUNC14_OUT_SEL_M  (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S)
+#define GPIO_FUNC14_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC14_OUT_SEL_S  0
+/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC14_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_M  (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S)
+#define GPIO_FUNC14_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OUT_INV_SEL_S  9
+/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC14_OEN_SEL    (BIT(10))
+#define GPIO_FUNC14_OEN_SEL_M  (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S)
+#define GPIO_FUNC14_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC14_OEN_SEL_S  10
+/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC14_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC14_OEN_INV_SEL_M  (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S)
+#define GPIO_FUNC14_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC15_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594)
+/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC15_OUT_SEL    0x000001FFU
+#define GPIO_FUNC15_OUT_SEL_M  (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S)
+#define GPIO_FUNC15_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC15_OUT_SEL_S  0
+/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC15_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_M  (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S)
+#define GPIO_FUNC15_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OUT_INV_SEL_S  9
+/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC15_OEN_SEL    (BIT(10))
+#define GPIO_FUNC15_OEN_SEL_M  (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S)
+#define GPIO_FUNC15_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC15_OEN_SEL_S  10
+/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC15_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC15_OEN_INV_SEL_M  (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S)
+#define GPIO_FUNC15_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC16_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598)
+/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC16_OUT_SEL    0x000001FFU
+#define GPIO_FUNC16_OUT_SEL_M  (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S)
+#define GPIO_FUNC16_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC16_OUT_SEL_S  0
+/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC16_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_M  (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S)
+#define GPIO_FUNC16_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OUT_INV_SEL_S  9
+/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC16_OEN_SEL    (BIT(10))
+#define GPIO_FUNC16_OEN_SEL_M  (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S)
+#define GPIO_FUNC16_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC16_OEN_SEL_S  10
+/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC16_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC16_OEN_INV_SEL_M  (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S)
+#define GPIO_FUNC16_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC17_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c)
+/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC17_OUT_SEL    0x000001FFU
+#define GPIO_FUNC17_OUT_SEL_M  (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S)
+#define GPIO_FUNC17_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC17_OUT_SEL_S  0
+/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC17_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_M  (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S)
+#define GPIO_FUNC17_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OUT_INV_SEL_S  9
+/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC17_OEN_SEL    (BIT(10))
+#define GPIO_FUNC17_OEN_SEL_M  (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S)
+#define GPIO_FUNC17_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC17_OEN_SEL_S  10
+/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC17_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC17_OEN_INV_SEL_M  (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S)
+#define GPIO_FUNC17_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC18_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0)
+/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC18_OUT_SEL    0x000001FFU
+#define GPIO_FUNC18_OUT_SEL_M  (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S)
+#define GPIO_FUNC18_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC18_OUT_SEL_S  0
+/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC18_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_M  (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S)
+#define GPIO_FUNC18_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OUT_INV_SEL_S  9
+/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC18_OEN_SEL    (BIT(10))
+#define GPIO_FUNC18_OEN_SEL_M  (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S)
+#define GPIO_FUNC18_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC18_OEN_SEL_S  10
+/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC18_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC18_OEN_INV_SEL_M  (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S)
+#define GPIO_FUNC18_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC19_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4)
+/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC19_OUT_SEL    0x000001FFU
+#define GPIO_FUNC19_OUT_SEL_M  (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S)
+#define GPIO_FUNC19_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC19_OUT_SEL_S  0
+/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC19_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_M  (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S)
+#define GPIO_FUNC19_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OUT_INV_SEL_S  9
+/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC19_OEN_SEL    (BIT(10))
+#define GPIO_FUNC19_OEN_SEL_M  (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S)
+#define GPIO_FUNC19_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC19_OEN_SEL_S  10
+/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC19_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC19_OEN_INV_SEL_M  (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S)
+#define GPIO_FUNC19_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC20_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8)
+/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC20_OUT_SEL    0x000001FFU
+#define GPIO_FUNC20_OUT_SEL_M  (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S)
+#define GPIO_FUNC20_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC20_OUT_SEL_S  0
+/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC20_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_M  (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S)
+#define GPIO_FUNC20_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OUT_INV_SEL_S  9
+/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC20_OEN_SEL    (BIT(10))
+#define GPIO_FUNC20_OEN_SEL_M  (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S)
+#define GPIO_FUNC20_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC20_OEN_SEL_S  10
+/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC20_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC20_OEN_INV_SEL_M  (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S)
+#define GPIO_FUNC20_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC21_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac)
+/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC21_OUT_SEL    0x000001FFU
+#define GPIO_FUNC21_OUT_SEL_M  (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S)
+#define GPIO_FUNC21_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC21_OUT_SEL_S  0
+/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC21_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_M  (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S)
+#define GPIO_FUNC21_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OUT_INV_SEL_S  9
+/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC21_OEN_SEL    (BIT(10))
+#define GPIO_FUNC21_OEN_SEL_M  (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S)
+#define GPIO_FUNC21_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC21_OEN_SEL_S  10
+/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC21_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC21_OEN_INV_SEL_M  (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S)
+#define GPIO_FUNC21_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC22_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0)
+/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC22_OUT_SEL    0x000001FFU
+#define GPIO_FUNC22_OUT_SEL_M  (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
+#define GPIO_FUNC22_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC22_OUT_SEL_S  0
+/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC22_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_M  (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
+#define GPIO_FUNC22_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OUT_INV_SEL_S  9
+/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC22_OEN_SEL    (BIT(10))
+#define GPIO_FUNC22_OEN_SEL_M  (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S)
+#define GPIO_FUNC22_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC22_OEN_SEL_S  10
+/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC22_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC22_OEN_INV_SEL_M  (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S)
+#define GPIO_FUNC22_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC23_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4)
+/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC23_OUT_SEL    0x000001FFU
+#define GPIO_FUNC23_OUT_SEL_M  (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
+#define GPIO_FUNC23_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC23_OUT_SEL_S  0
+/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC23_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_M  (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
+#define GPIO_FUNC23_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OUT_INV_SEL_S  9
+/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC23_OEN_SEL    (BIT(10))
+#define GPIO_FUNC23_OEN_SEL_M  (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S)
+#define GPIO_FUNC23_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC23_OEN_SEL_S  10
+/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC23_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC23_OEN_INV_SEL_M  (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S)
+#define GPIO_FUNC23_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC24_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8)
+/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC24_OUT_SEL    0x000001FFU
+#define GPIO_FUNC24_OUT_SEL_M  (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
+#define GPIO_FUNC24_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC24_OUT_SEL_S  0
+/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC24_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_M  (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
+#define GPIO_FUNC24_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OUT_INV_SEL_S  9
+/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC24_OEN_SEL    (BIT(10))
+#define GPIO_FUNC24_OEN_SEL_M  (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S)
+#define GPIO_FUNC24_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC24_OEN_SEL_S  10
+/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC24_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC24_OEN_INV_SEL_M  (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S)
+#define GPIO_FUNC24_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC25_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc)
+/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC25_OUT_SEL    0x000001FFU
+#define GPIO_FUNC25_OUT_SEL_M  (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S)
+#define GPIO_FUNC25_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC25_OUT_SEL_S  0
+/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC25_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC25_OUT_INV_SEL_M  (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S)
+#define GPIO_FUNC25_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_OUT_INV_SEL_S  9
+/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC25_OEN_SEL    (BIT(10))
+#define GPIO_FUNC25_OEN_SEL_M  (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S)
+#define GPIO_FUNC25_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC25_OEN_SEL_S  10
+/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC25_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC25_OEN_INV_SEL_M  (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S)
+#define GPIO_FUNC25_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC26_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0)
+/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC26_OUT_SEL    0x000001FFU
+#define GPIO_FUNC26_OUT_SEL_M  (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S)
+#define GPIO_FUNC26_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC26_OUT_SEL_S  0
+/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC26_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC26_OUT_INV_SEL_M  (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S)
+#define GPIO_FUNC26_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_OUT_INV_SEL_S  9
+/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC26_OEN_SEL    (BIT(10))
+#define GPIO_FUNC26_OEN_SEL_M  (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S)
+#define GPIO_FUNC26_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC26_OEN_SEL_S  10
+/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC26_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC26_OEN_INV_SEL_M  (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S)
+#define GPIO_FUNC26_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC27_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4)
+/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC27_OUT_SEL    0x000001FFU
+#define GPIO_FUNC27_OUT_SEL_M  (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S)
+#define GPIO_FUNC27_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC27_OUT_SEL_S  0
+/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC27_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC27_OUT_INV_SEL_M  (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S)
+#define GPIO_FUNC27_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_OUT_INV_SEL_S  9
+/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC27_OEN_SEL    (BIT(10))
+#define GPIO_FUNC27_OEN_SEL_M  (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S)
+#define GPIO_FUNC27_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC27_OEN_SEL_S  10
+/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC27_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC27_OEN_INV_SEL_M  (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S)
+#define GPIO_FUNC27_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC28_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8)
+/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC28_OUT_SEL    0x000001FFU
+#define GPIO_FUNC28_OUT_SEL_M  (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S)
+#define GPIO_FUNC28_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC28_OUT_SEL_S  0
+/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC28_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC28_OUT_INV_SEL_M  (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S)
+#define GPIO_FUNC28_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_OUT_INV_SEL_S  9
+/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC28_OEN_SEL    (BIT(10))
+#define GPIO_FUNC28_OEN_SEL_M  (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S)
+#define GPIO_FUNC28_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC28_OEN_SEL_S  10
+/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC28_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC28_OEN_INV_SEL_M  (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S)
+#define GPIO_FUNC28_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC29_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc)
+/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC29_OUT_SEL    0x000001FFU
+#define GPIO_FUNC29_OUT_SEL_M  (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S)
+#define GPIO_FUNC29_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC29_OUT_SEL_S  0
+/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC29_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC29_OUT_INV_SEL_M  (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S)
+#define GPIO_FUNC29_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_OUT_INV_SEL_S  9
+/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC29_OEN_SEL    (BIT(10))
+#define GPIO_FUNC29_OEN_SEL_M  (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S)
+#define GPIO_FUNC29_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC29_OEN_SEL_S  10
+/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC29_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC29_OEN_INV_SEL_M  (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S)
+#define GPIO_FUNC29_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC30_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0)
+/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC30_OUT_SEL    0x000001FFU
+#define GPIO_FUNC30_OUT_SEL_M  (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S)
+#define GPIO_FUNC30_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC30_OUT_SEL_S  0
+/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC30_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC30_OUT_INV_SEL_M  (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S)
+#define GPIO_FUNC30_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_OUT_INV_SEL_S  9
+/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC30_OEN_SEL    (BIT(10))
+#define GPIO_FUNC30_OEN_SEL_M  (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S)
+#define GPIO_FUNC30_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC30_OEN_SEL_S  10
+/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC30_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC30_OEN_INV_SEL_M  (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S)
+#define GPIO_FUNC30_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC31_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4)
+/** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC31_OUT_SEL    0x000001FFU
+#define GPIO_FUNC31_OUT_SEL_M  (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S)
+#define GPIO_FUNC31_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC31_OUT_SEL_S  0
+/** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC31_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC31_OUT_INV_SEL_M  (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S)
+#define GPIO_FUNC31_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_OUT_INV_SEL_S  9
+/** GPIO_FUNC31_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC31_OEN_SEL    (BIT(10))
+#define GPIO_FUNC31_OEN_SEL_M  (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S)
+#define GPIO_FUNC31_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC31_OEN_SEL_S  10
+/** GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC31_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC31_OEN_INV_SEL_M  (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S)
+#define GPIO_FUNC31_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC32_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8)
+/** GPIO_FUNC32_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC32_OUT_SEL    0x000001FFU
+#define GPIO_FUNC32_OUT_SEL_M  (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S)
+#define GPIO_FUNC32_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC32_OUT_SEL_S  0
+/** GPIO_FUNC32_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC32_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC32_OUT_INV_SEL_M  (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S)
+#define GPIO_FUNC32_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_OUT_INV_SEL_S  9
+/** GPIO_FUNC32_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC32_OEN_SEL    (BIT(10))
+#define GPIO_FUNC32_OEN_SEL_M  (GPIO_FUNC32_OEN_SEL_V << GPIO_FUNC32_OEN_SEL_S)
+#define GPIO_FUNC32_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC32_OEN_SEL_S  10
+/** GPIO_FUNC32_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC32_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC32_OEN_INV_SEL_M  (GPIO_FUNC32_OEN_INV_SEL_V << GPIO_FUNC32_OEN_INV_SEL_S)
+#define GPIO_FUNC32_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC33_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc)
+/** GPIO_FUNC33_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC33_OUT_SEL    0x000001FFU
+#define GPIO_FUNC33_OUT_SEL_M  (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S)
+#define GPIO_FUNC33_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC33_OUT_SEL_S  0
+/** GPIO_FUNC33_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC33_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC33_OUT_INV_SEL_M  (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S)
+#define GPIO_FUNC33_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_OUT_INV_SEL_S  9
+/** GPIO_FUNC33_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC33_OEN_SEL    (BIT(10))
+#define GPIO_FUNC33_OEN_SEL_M  (GPIO_FUNC33_OEN_SEL_V << GPIO_FUNC33_OEN_SEL_S)
+#define GPIO_FUNC33_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC33_OEN_SEL_S  10
+/** GPIO_FUNC33_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC33_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC33_OEN_INV_SEL_M  (GPIO_FUNC33_OEN_INV_SEL_V << GPIO_FUNC33_OEN_INV_SEL_S)
+#define GPIO_FUNC33_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC34_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e0)
+/** GPIO_FUNC34_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC34_OUT_SEL    0x000001FFU
+#define GPIO_FUNC34_OUT_SEL_M  (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S)
+#define GPIO_FUNC34_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC34_OUT_SEL_S  0
+/** GPIO_FUNC34_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC34_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC34_OUT_INV_SEL_M  (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S)
+#define GPIO_FUNC34_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_OUT_INV_SEL_S  9
+/** GPIO_FUNC34_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC34_OEN_SEL    (BIT(10))
+#define GPIO_FUNC34_OEN_SEL_M  (GPIO_FUNC34_OEN_SEL_V << GPIO_FUNC34_OEN_SEL_S)
+#define GPIO_FUNC34_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC34_OEN_SEL_S  10
+/** GPIO_FUNC34_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC34_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC34_OEN_INV_SEL_M  (GPIO_FUNC34_OEN_INV_SEL_V << GPIO_FUNC34_OEN_INV_SEL_S)
+#define GPIO_FUNC34_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC35_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e4)
+/** GPIO_FUNC35_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC35_OUT_SEL    0x000001FFU
+#define GPIO_FUNC35_OUT_SEL_M  (GPIO_FUNC35_OUT_SEL_V << GPIO_FUNC35_OUT_SEL_S)
+#define GPIO_FUNC35_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC35_OUT_SEL_S  0
+/** GPIO_FUNC35_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC35_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC35_OUT_INV_SEL_M  (GPIO_FUNC35_OUT_INV_SEL_V << GPIO_FUNC35_OUT_INV_SEL_S)
+#define GPIO_FUNC35_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_OUT_INV_SEL_S  9
+/** GPIO_FUNC35_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC35_OEN_SEL    (BIT(10))
+#define GPIO_FUNC35_OEN_SEL_M  (GPIO_FUNC35_OEN_SEL_V << GPIO_FUNC35_OEN_SEL_S)
+#define GPIO_FUNC35_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC35_OEN_SEL_S  10
+/** GPIO_FUNC35_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC35_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC35_OEN_INV_SEL_M  (GPIO_FUNC35_OEN_INV_SEL_V << GPIO_FUNC35_OEN_INV_SEL_S)
+#define GPIO_FUNC35_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC36_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e8)
+/** GPIO_FUNC36_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC36_OUT_SEL    0x000001FFU
+#define GPIO_FUNC36_OUT_SEL_M  (GPIO_FUNC36_OUT_SEL_V << GPIO_FUNC36_OUT_SEL_S)
+#define GPIO_FUNC36_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC36_OUT_SEL_S  0
+/** GPIO_FUNC36_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC36_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC36_OUT_INV_SEL_M  (GPIO_FUNC36_OUT_INV_SEL_V << GPIO_FUNC36_OUT_INV_SEL_S)
+#define GPIO_FUNC36_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_OUT_INV_SEL_S  9
+/** GPIO_FUNC36_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC36_OEN_SEL    (BIT(10))
+#define GPIO_FUNC36_OEN_SEL_M  (GPIO_FUNC36_OEN_SEL_V << GPIO_FUNC36_OEN_SEL_S)
+#define GPIO_FUNC36_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC36_OEN_SEL_S  10
+/** GPIO_FUNC36_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC36_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC36_OEN_INV_SEL_M  (GPIO_FUNC36_OEN_INV_SEL_V << GPIO_FUNC36_OEN_INV_SEL_S)
+#define GPIO_FUNC36_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC37_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ec)
+/** GPIO_FUNC37_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC37_OUT_SEL    0x000001FFU
+#define GPIO_FUNC37_OUT_SEL_M  (GPIO_FUNC37_OUT_SEL_V << GPIO_FUNC37_OUT_SEL_S)
+#define GPIO_FUNC37_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC37_OUT_SEL_S  0
+/** GPIO_FUNC37_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC37_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC37_OUT_INV_SEL_M  (GPIO_FUNC37_OUT_INV_SEL_V << GPIO_FUNC37_OUT_INV_SEL_S)
+#define GPIO_FUNC37_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_OUT_INV_SEL_S  9
+/** GPIO_FUNC37_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC37_OEN_SEL    (BIT(10))
+#define GPIO_FUNC37_OEN_SEL_M  (GPIO_FUNC37_OEN_SEL_V << GPIO_FUNC37_OEN_SEL_S)
+#define GPIO_FUNC37_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC37_OEN_SEL_S  10
+/** GPIO_FUNC37_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC37_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC37_OEN_INV_SEL_M  (GPIO_FUNC37_OEN_INV_SEL_V << GPIO_FUNC37_OEN_INV_SEL_S)
+#define GPIO_FUNC37_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC38_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f0)
+/** GPIO_FUNC38_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC38_OUT_SEL    0x000001FFU
+#define GPIO_FUNC38_OUT_SEL_M  (GPIO_FUNC38_OUT_SEL_V << GPIO_FUNC38_OUT_SEL_S)
+#define GPIO_FUNC38_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC38_OUT_SEL_S  0
+/** GPIO_FUNC38_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC38_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC38_OUT_INV_SEL_M  (GPIO_FUNC38_OUT_INV_SEL_V << GPIO_FUNC38_OUT_INV_SEL_S)
+#define GPIO_FUNC38_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_OUT_INV_SEL_S  9
+/** GPIO_FUNC38_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC38_OEN_SEL    (BIT(10))
+#define GPIO_FUNC38_OEN_SEL_M  (GPIO_FUNC38_OEN_SEL_V << GPIO_FUNC38_OEN_SEL_S)
+#define GPIO_FUNC38_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC38_OEN_SEL_S  10
+/** GPIO_FUNC38_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC38_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC38_OEN_INV_SEL_M  (GPIO_FUNC38_OEN_INV_SEL_V << GPIO_FUNC38_OEN_INV_SEL_S)
+#define GPIO_FUNC38_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC39_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f4)
+/** GPIO_FUNC39_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC39_OUT_SEL    0x000001FFU
+#define GPIO_FUNC39_OUT_SEL_M  (GPIO_FUNC39_OUT_SEL_V << GPIO_FUNC39_OUT_SEL_S)
+#define GPIO_FUNC39_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC39_OUT_SEL_S  0
+/** GPIO_FUNC39_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC39_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC39_OUT_INV_SEL_M  (GPIO_FUNC39_OUT_INV_SEL_V << GPIO_FUNC39_OUT_INV_SEL_S)
+#define GPIO_FUNC39_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_OUT_INV_SEL_S  9
+/** GPIO_FUNC39_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC39_OEN_SEL    (BIT(10))
+#define GPIO_FUNC39_OEN_SEL_M  (GPIO_FUNC39_OEN_SEL_V << GPIO_FUNC39_OEN_SEL_S)
+#define GPIO_FUNC39_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC39_OEN_SEL_S  10
+/** GPIO_FUNC39_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC39_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC39_OEN_INV_SEL_M  (GPIO_FUNC39_OEN_INV_SEL_V << GPIO_FUNC39_OEN_INV_SEL_S)
+#define GPIO_FUNC39_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC40_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f8)
+/** GPIO_FUNC40_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC40_OUT_SEL    0x000001FFU
+#define GPIO_FUNC40_OUT_SEL_M  (GPIO_FUNC40_OUT_SEL_V << GPIO_FUNC40_OUT_SEL_S)
+#define GPIO_FUNC40_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC40_OUT_SEL_S  0
+/** GPIO_FUNC40_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC40_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC40_OUT_INV_SEL_M  (GPIO_FUNC40_OUT_INV_SEL_V << GPIO_FUNC40_OUT_INV_SEL_S)
+#define GPIO_FUNC40_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_OUT_INV_SEL_S  9
+/** GPIO_FUNC40_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC40_OEN_SEL    (BIT(10))
+#define GPIO_FUNC40_OEN_SEL_M  (GPIO_FUNC40_OEN_SEL_V << GPIO_FUNC40_OEN_SEL_S)
+#define GPIO_FUNC40_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC40_OEN_SEL_S  10
+/** GPIO_FUNC40_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC40_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC40_OEN_INV_SEL_M  (GPIO_FUNC40_OEN_INV_SEL_V << GPIO_FUNC40_OEN_INV_SEL_S)
+#define GPIO_FUNC40_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC41_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5fc)
+/** GPIO_FUNC41_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC41_OUT_SEL    0x000001FFU
+#define GPIO_FUNC41_OUT_SEL_M  (GPIO_FUNC41_OUT_SEL_V << GPIO_FUNC41_OUT_SEL_S)
+#define GPIO_FUNC41_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC41_OUT_SEL_S  0
+/** GPIO_FUNC41_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC41_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC41_OUT_INV_SEL_M  (GPIO_FUNC41_OUT_INV_SEL_V << GPIO_FUNC41_OUT_INV_SEL_S)
+#define GPIO_FUNC41_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_OUT_INV_SEL_S  9
+/** GPIO_FUNC41_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC41_OEN_SEL    (BIT(10))
+#define GPIO_FUNC41_OEN_SEL_M  (GPIO_FUNC41_OEN_SEL_V << GPIO_FUNC41_OEN_SEL_S)
+#define GPIO_FUNC41_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC41_OEN_SEL_S  10
+/** GPIO_FUNC41_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC41_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC41_OEN_INV_SEL_M  (GPIO_FUNC41_OEN_INV_SEL_V << GPIO_FUNC41_OEN_INV_SEL_S)
+#define GPIO_FUNC41_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC42_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600)
+/** GPIO_FUNC42_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC42_OUT_SEL    0x000001FFU
+#define GPIO_FUNC42_OUT_SEL_M  (GPIO_FUNC42_OUT_SEL_V << GPIO_FUNC42_OUT_SEL_S)
+#define GPIO_FUNC42_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC42_OUT_SEL_S  0
+/** GPIO_FUNC42_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC42_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC42_OUT_INV_SEL_M  (GPIO_FUNC42_OUT_INV_SEL_V << GPIO_FUNC42_OUT_INV_SEL_S)
+#define GPIO_FUNC42_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_OUT_INV_SEL_S  9
+/** GPIO_FUNC42_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC42_OEN_SEL    (BIT(10))
+#define GPIO_FUNC42_OEN_SEL_M  (GPIO_FUNC42_OEN_SEL_V << GPIO_FUNC42_OEN_SEL_S)
+#define GPIO_FUNC42_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC42_OEN_SEL_S  10
+/** GPIO_FUNC42_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC42_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC42_OEN_INV_SEL_M  (GPIO_FUNC42_OEN_INV_SEL_V << GPIO_FUNC42_OEN_INV_SEL_S)
+#define GPIO_FUNC42_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC43_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604)
+/** GPIO_FUNC43_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC43_OUT_SEL    0x000001FFU
+#define GPIO_FUNC43_OUT_SEL_M  (GPIO_FUNC43_OUT_SEL_V << GPIO_FUNC43_OUT_SEL_S)
+#define GPIO_FUNC43_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC43_OUT_SEL_S  0
+/** GPIO_FUNC43_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC43_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC43_OUT_INV_SEL_M  (GPIO_FUNC43_OUT_INV_SEL_V << GPIO_FUNC43_OUT_INV_SEL_S)
+#define GPIO_FUNC43_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_OUT_INV_SEL_S  9
+/** GPIO_FUNC43_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC43_OEN_SEL    (BIT(10))
+#define GPIO_FUNC43_OEN_SEL_M  (GPIO_FUNC43_OEN_SEL_V << GPIO_FUNC43_OEN_SEL_S)
+#define GPIO_FUNC43_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC43_OEN_SEL_S  10
+/** GPIO_FUNC43_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC43_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC43_OEN_INV_SEL_M  (GPIO_FUNC43_OEN_INV_SEL_V << GPIO_FUNC43_OEN_INV_SEL_S)
+#define GPIO_FUNC43_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC44_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x608)
+/** GPIO_FUNC44_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC44_OUT_SEL    0x000001FFU
+#define GPIO_FUNC44_OUT_SEL_M  (GPIO_FUNC44_OUT_SEL_V << GPIO_FUNC44_OUT_SEL_S)
+#define GPIO_FUNC44_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC44_OUT_SEL_S  0
+/** GPIO_FUNC44_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC44_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC44_OUT_INV_SEL_M  (GPIO_FUNC44_OUT_INV_SEL_V << GPIO_FUNC44_OUT_INV_SEL_S)
+#define GPIO_FUNC44_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_OUT_INV_SEL_S  9
+/** GPIO_FUNC44_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC44_OEN_SEL    (BIT(10))
+#define GPIO_FUNC44_OEN_SEL_M  (GPIO_FUNC44_OEN_SEL_V << GPIO_FUNC44_OEN_SEL_S)
+#define GPIO_FUNC44_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC44_OEN_SEL_S  10
+/** GPIO_FUNC44_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC44_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC44_OEN_INV_SEL_M  (GPIO_FUNC44_OEN_INV_SEL_V << GPIO_FUNC44_OEN_INV_SEL_S)
+#define GPIO_FUNC44_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC45_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC45_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x60c)
+/** GPIO_FUNC45_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC45_OUT_SEL    0x000001FFU
+#define GPIO_FUNC45_OUT_SEL_M  (GPIO_FUNC45_OUT_SEL_V << GPIO_FUNC45_OUT_SEL_S)
+#define GPIO_FUNC45_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC45_OUT_SEL_S  0
+/** GPIO_FUNC45_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC45_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC45_OUT_INV_SEL_M  (GPIO_FUNC45_OUT_INV_SEL_V << GPIO_FUNC45_OUT_INV_SEL_S)
+#define GPIO_FUNC45_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_OUT_INV_SEL_S  9
+/** GPIO_FUNC45_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC45_OEN_SEL    (BIT(10))
+#define GPIO_FUNC45_OEN_SEL_M  (GPIO_FUNC45_OEN_SEL_V << GPIO_FUNC45_OEN_SEL_S)
+#define GPIO_FUNC45_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC45_OEN_SEL_S  10
+/** GPIO_FUNC45_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC45_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC45_OEN_INV_SEL_M  (GPIO_FUNC45_OEN_INV_SEL_V << GPIO_FUNC45_OEN_INV_SEL_S)
+#define GPIO_FUNC45_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC46_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC46_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x610)
+/** GPIO_FUNC46_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC46_OUT_SEL    0x000001FFU
+#define GPIO_FUNC46_OUT_SEL_M  (GPIO_FUNC46_OUT_SEL_V << GPIO_FUNC46_OUT_SEL_S)
+#define GPIO_FUNC46_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC46_OUT_SEL_S  0
+/** GPIO_FUNC46_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC46_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC46_OUT_INV_SEL_M  (GPIO_FUNC46_OUT_INV_SEL_V << GPIO_FUNC46_OUT_INV_SEL_S)
+#define GPIO_FUNC46_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC46_OUT_INV_SEL_S  9
+/** GPIO_FUNC46_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC46_OEN_SEL    (BIT(10))
+#define GPIO_FUNC46_OEN_SEL_M  (GPIO_FUNC46_OEN_SEL_V << GPIO_FUNC46_OEN_SEL_S)
+#define GPIO_FUNC46_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC46_OEN_SEL_S  10
+/** GPIO_FUNC46_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC46_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC46_OEN_INV_SEL_M  (GPIO_FUNC46_OEN_INV_SEL_V << GPIO_FUNC46_OEN_INV_SEL_S)
+#define GPIO_FUNC46_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC46_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC47_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC47_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x614)
+/** GPIO_FUNC47_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC47_OUT_SEL    0x000001FFU
+#define GPIO_FUNC47_OUT_SEL_M  (GPIO_FUNC47_OUT_SEL_V << GPIO_FUNC47_OUT_SEL_S)
+#define GPIO_FUNC47_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC47_OUT_SEL_S  0
+/** GPIO_FUNC47_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC47_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC47_OUT_INV_SEL_M  (GPIO_FUNC47_OUT_INV_SEL_V << GPIO_FUNC47_OUT_INV_SEL_S)
+#define GPIO_FUNC47_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_OUT_INV_SEL_S  9
+/** GPIO_FUNC47_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC47_OEN_SEL    (BIT(10))
+#define GPIO_FUNC47_OEN_SEL_M  (GPIO_FUNC47_OEN_SEL_V << GPIO_FUNC47_OEN_SEL_S)
+#define GPIO_FUNC47_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC47_OEN_SEL_S  10
+/** GPIO_FUNC47_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC47_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC47_OEN_INV_SEL_M  (GPIO_FUNC47_OEN_INV_SEL_V << GPIO_FUNC47_OEN_INV_SEL_S)
+#define GPIO_FUNC47_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC48_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC48_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x618)
+/** GPIO_FUNC48_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC48_OUT_SEL    0x000001FFU
+#define GPIO_FUNC48_OUT_SEL_M  (GPIO_FUNC48_OUT_SEL_V << GPIO_FUNC48_OUT_SEL_S)
+#define GPIO_FUNC48_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC48_OUT_SEL_S  0
+/** GPIO_FUNC48_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC48_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC48_OUT_INV_SEL_M  (GPIO_FUNC48_OUT_INV_SEL_V << GPIO_FUNC48_OUT_INV_SEL_S)
+#define GPIO_FUNC48_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_OUT_INV_SEL_S  9
+/** GPIO_FUNC48_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC48_OEN_SEL    (BIT(10))
+#define GPIO_FUNC48_OEN_SEL_M  (GPIO_FUNC48_OEN_SEL_V << GPIO_FUNC48_OEN_SEL_S)
+#define GPIO_FUNC48_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC48_OEN_SEL_S  10
+/** GPIO_FUNC48_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC48_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC48_OEN_INV_SEL_M  (GPIO_FUNC48_OEN_INV_SEL_V << GPIO_FUNC48_OEN_INV_SEL_S)
+#define GPIO_FUNC48_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC49_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC49_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x61c)
+/** GPIO_FUNC49_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC49_OUT_SEL    0x000001FFU
+#define GPIO_FUNC49_OUT_SEL_M  (GPIO_FUNC49_OUT_SEL_V << GPIO_FUNC49_OUT_SEL_S)
+#define GPIO_FUNC49_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC49_OUT_SEL_S  0
+/** GPIO_FUNC49_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC49_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC49_OUT_INV_SEL_M  (GPIO_FUNC49_OUT_INV_SEL_V << GPIO_FUNC49_OUT_INV_SEL_S)
+#define GPIO_FUNC49_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_OUT_INV_SEL_S  9
+/** GPIO_FUNC49_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC49_OEN_SEL    (BIT(10))
+#define GPIO_FUNC49_OEN_SEL_M  (GPIO_FUNC49_OEN_SEL_V << GPIO_FUNC49_OEN_SEL_S)
+#define GPIO_FUNC49_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC49_OEN_SEL_S  10
+/** GPIO_FUNC49_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC49_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC49_OEN_INV_SEL_M  (GPIO_FUNC49_OEN_INV_SEL_V << GPIO_FUNC49_OEN_INV_SEL_S)
+#define GPIO_FUNC49_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC50_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC50_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x620)
+/** GPIO_FUNC50_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC50_OUT_SEL    0x000001FFU
+#define GPIO_FUNC50_OUT_SEL_M  (GPIO_FUNC50_OUT_SEL_V << GPIO_FUNC50_OUT_SEL_S)
+#define GPIO_FUNC50_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC50_OUT_SEL_S  0
+/** GPIO_FUNC50_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC50_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC50_OUT_INV_SEL_M  (GPIO_FUNC50_OUT_INV_SEL_V << GPIO_FUNC50_OUT_INV_SEL_S)
+#define GPIO_FUNC50_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_OUT_INV_SEL_S  9
+/** GPIO_FUNC50_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC50_OEN_SEL    (BIT(10))
+#define GPIO_FUNC50_OEN_SEL_M  (GPIO_FUNC50_OEN_SEL_V << GPIO_FUNC50_OEN_SEL_S)
+#define GPIO_FUNC50_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC50_OEN_SEL_S  10
+/** GPIO_FUNC50_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC50_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC50_OEN_INV_SEL_M  (GPIO_FUNC50_OEN_INV_SEL_V << GPIO_FUNC50_OEN_INV_SEL_S)
+#define GPIO_FUNC50_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC51_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC51_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x624)
+/** GPIO_FUNC51_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC51_OUT_SEL    0x000001FFU
+#define GPIO_FUNC51_OUT_SEL_M  (GPIO_FUNC51_OUT_SEL_V << GPIO_FUNC51_OUT_SEL_S)
+#define GPIO_FUNC51_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC51_OUT_SEL_S  0
+/** GPIO_FUNC51_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC51_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC51_OUT_INV_SEL_M  (GPIO_FUNC51_OUT_INV_SEL_V << GPIO_FUNC51_OUT_INV_SEL_S)
+#define GPIO_FUNC51_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_OUT_INV_SEL_S  9
+/** GPIO_FUNC51_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC51_OEN_SEL    (BIT(10))
+#define GPIO_FUNC51_OEN_SEL_M  (GPIO_FUNC51_OEN_SEL_V << GPIO_FUNC51_OEN_SEL_S)
+#define GPIO_FUNC51_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC51_OEN_SEL_S  10
+/** GPIO_FUNC51_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC51_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC51_OEN_INV_SEL_M  (GPIO_FUNC51_OEN_INV_SEL_V << GPIO_FUNC51_OEN_INV_SEL_S)
+#define GPIO_FUNC51_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC52_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC52_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x628)
+/** GPIO_FUNC52_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC52_OUT_SEL    0x000001FFU
+#define GPIO_FUNC52_OUT_SEL_M  (GPIO_FUNC52_OUT_SEL_V << GPIO_FUNC52_OUT_SEL_S)
+#define GPIO_FUNC52_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC52_OUT_SEL_S  0
+/** GPIO_FUNC52_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC52_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC52_OUT_INV_SEL_M  (GPIO_FUNC52_OUT_INV_SEL_V << GPIO_FUNC52_OUT_INV_SEL_S)
+#define GPIO_FUNC52_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_OUT_INV_SEL_S  9
+/** GPIO_FUNC52_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC52_OEN_SEL    (BIT(10))
+#define GPIO_FUNC52_OEN_SEL_M  (GPIO_FUNC52_OEN_SEL_V << GPIO_FUNC52_OEN_SEL_S)
+#define GPIO_FUNC52_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC52_OEN_SEL_S  10
+/** GPIO_FUNC52_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC52_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC52_OEN_INV_SEL_M  (GPIO_FUNC52_OEN_INV_SEL_V << GPIO_FUNC52_OEN_INV_SEL_S)
+#define GPIO_FUNC52_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC53_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC53_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x62c)
+/** GPIO_FUNC53_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC53_OUT_SEL    0x000001FFU
+#define GPIO_FUNC53_OUT_SEL_M  (GPIO_FUNC53_OUT_SEL_V << GPIO_FUNC53_OUT_SEL_S)
+#define GPIO_FUNC53_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC53_OUT_SEL_S  0
+/** GPIO_FUNC53_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC53_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC53_OUT_INV_SEL_M  (GPIO_FUNC53_OUT_INV_SEL_V << GPIO_FUNC53_OUT_INV_SEL_S)
+#define GPIO_FUNC53_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_OUT_INV_SEL_S  9
+/** GPIO_FUNC53_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC53_OEN_SEL    (BIT(10))
+#define GPIO_FUNC53_OEN_SEL_M  (GPIO_FUNC53_OEN_SEL_V << GPIO_FUNC53_OEN_SEL_S)
+#define GPIO_FUNC53_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC53_OEN_SEL_S  10
+/** GPIO_FUNC53_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC53_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC53_OEN_INV_SEL_M  (GPIO_FUNC53_OEN_INV_SEL_V << GPIO_FUNC53_OEN_INV_SEL_S)
+#define GPIO_FUNC53_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC54_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC54_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x630)
+/** GPIO_FUNC54_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC54_OUT_SEL    0x000001FFU
+#define GPIO_FUNC54_OUT_SEL_M  (GPIO_FUNC54_OUT_SEL_V << GPIO_FUNC54_OUT_SEL_S)
+#define GPIO_FUNC54_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC54_OUT_SEL_S  0
+/** GPIO_FUNC54_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC54_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC54_OUT_INV_SEL_M  (GPIO_FUNC54_OUT_INV_SEL_V << GPIO_FUNC54_OUT_INV_SEL_S)
+#define GPIO_FUNC54_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_OUT_INV_SEL_S  9
+/** GPIO_FUNC54_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC54_OEN_SEL    (BIT(10))
+#define GPIO_FUNC54_OEN_SEL_M  (GPIO_FUNC54_OEN_SEL_V << GPIO_FUNC54_OEN_SEL_S)
+#define GPIO_FUNC54_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC54_OEN_SEL_S  10
+/** GPIO_FUNC54_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC54_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC54_OEN_INV_SEL_M  (GPIO_FUNC54_OEN_INV_SEL_V << GPIO_FUNC54_OEN_INV_SEL_S)
+#define GPIO_FUNC54_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC55_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC55_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x634)
+/** GPIO_FUNC55_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC55_OUT_SEL    0x000001FFU
+#define GPIO_FUNC55_OUT_SEL_M  (GPIO_FUNC55_OUT_SEL_V << GPIO_FUNC55_OUT_SEL_S)
+#define GPIO_FUNC55_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC55_OUT_SEL_S  0
+/** GPIO_FUNC55_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC55_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC55_OUT_INV_SEL_M  (GPIO_FUNC55_OUT_INV_SEL_V << GPIO_FUNC55_OUT_INV_SEL_S)
+#define GPIO_FUNC55_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_OUT_INV_SEL_S  9
+/** GPIO_FUNC55_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC55_OEN_SEL    (BIT(10))
+#define GPIO_FUNC55_OEN_SEL_M  (GPIO_FUNC55_OEN_SEL_V << GPIO_FUNC55_OEN_SEL_S)
+#define GPIO_FUNC55_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC55_OEN_SEL_S  10
+/** GPIO_FUNC55_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC55_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC55_OEN_INV_SEL_M  (GPIO_FUNC55_OEN_INV_SEL_V << GPIO_FUNC55_OEN_INV_SEL_S)
+#define GPIO_FUNC55_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC56_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC56_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x638)
+/** GPIO_FUNC56_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC56_OUT_SEL    0x000001FFU
+#define GPIO_FUNC56_OUT_SEL_M  (GPIO_FUNC56_OUT_SEL_V << GPIO_FUNC56_OUT_SEL_S)
+#define GPIO_FUNC56_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC56_OUT_SEL_S  0
+/** GPIO_FUNC56_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC56_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC56_OUT_INV_SEL_M  (GPIO_FUNC56_OUT_INV_SEL_V << GPIO_FUNC56_OUT_INV_SEL_S)
+#define GPIO_FUNC56_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_OUT_INV_SEL_S  9
+/** GPIO_FUNC56_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC56_OEN_SEL    (BIT(10))
+#define GPIO_FUNC56_OEN_SEL_M  (GPIO_FUNC56_OEN_SEL_V << GPIO_FUNC56_OEN_SEL_S)
+#define GPIO_FUNC56_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC56_OEN_SEL_S  10
+/** GPIO_FUNC56_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC56_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC56_OEN_INV_SEL_M  (GPIO_FUNC56_OEN_INV_SEL_V << GPIO_FUNC56_OEN_INV_SEL_S)
+#define GPIO_FUNC56_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_OEN_INV_SEL_S  11
+
+/** GPIO_INTR_2_REG register
+ *  GPIO interrupt 2 status register for GPIO0-31
+ */
+#define GPIO_INTR_2_REG (DR_REG_GPIO_BASE + 0x63c)
+/** GPIO_INT_2 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 2 status register for GPIO0-31
+ */
+#define GPIO_INT_2    0xFFFFFFFFU
+#define GPIO_INT_2_M  (GPIO_INT_2_V << GPIO_INT_2_S)
+#define GPIO_INT_2_V  0xFFFFFFFFU
+#define GPIO_INT_2_S  0
+
+/** GPIO_INTR1_2_REG register
+ *  GPIO interrupt 2 status register for GPIO32-56
+ */
+#define GPIO_INTR1_2_REG (DR_REG_GPIO_BASE + 0x640)
+/** GPIO_INT1_2 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 2 status register for GPIO32-56
+ */
+#define GPIO_INT1_2    0x01FFFFFFU
+#define GPIO_INT1_2_M  (GPIO_INT1_2_V << GPIO_INT1_2_S)
+#define GPIO_INT1_2_V  0x01FFFFFFU
+#define GPIO_INT1_2_S  0
+
+/** GPIO_INTR_3_REG register
+ *  GPIO interrupt 3 status register for GPIO0-31
+ */
+#define GPIO_INTR_3_REG (DR_REG_GPIO_BASE + 0x644)
+/** GPIO_INT_3 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 3 status register for GPIO0-31
+ */
+#define GPIO_INT_3    0xFFFFFFFFU
+#define GPIO_INT_3_M  (GPIO_INT_3_V << GPIO_INT_3_S)
+#define GPIO_INT_3_V  0xFFFFFFFFU
+#define GPIO_INT_3_S  0
+
+/** GPIO_INTR1_3_REG register
+ *  GPIO interrupt 3 status register for GPIO32-56
+ */
+#define GPIO_INTR1_3_REG (DR_REG_GPIO_BASE + 0x648)
+/** GPIO_INT1_3 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 3 status register for GPIO32-56
+ */
+#define GPIO_INT1_3    0x01FFFFFFU
+#define GPIO_INT1_3_M  (GPIO_INT1_3_V << GPIO_INT1_3_S)
+#define GPIO_INT1_3_V  0x01FFFFFFU
+#define GPIO_INT1_3_S  0
+
+/** GPIO_CLOCK_GATE_REG register
+ *  GPIO clock gate register
+ */
+#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x64c)
+/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  set this bit to enable GPIO clock gate
+ */
+#define GPIO_CLK_EN    (BIT(0))
+#define GPIO_CLK_EN_M  (GPIO_CLK_EN_V << GPIO_CLK_EN_S)
+#define GPIO_CLK_EN_V  0x00000001U
+#define GPIO_CLK_EN_S  0
+
+/** GPIO_INT_RAW_REG register
+ *  analog comparator interrupt raw
+ */
+#define GPIO_INT_RAW_REG (DR_REG_GPIO_BASE + 0x700)
+/** GPIO_COMP0_NEG_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  analog comparator pos edge interrupt raw
+ */
+#define GPIO_COMP0_NEG_INT_RAW    (BIT(0))
+#define GPIO_COMP0_NEG_INT_RAW_M  (GPIO_COMP0_NEG_INT_RAW_V << GPIO_COMP0_NEG_INT_RAW_S)
+#define GPIO_COMP0_NEG_INT_RAW_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_RAW_S  0
+/** GPIO_COMP0_POS_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  analog comparator neg edge interrupt raw
+ */
+#define GPIO_COMP0_POS_INT_RAW    (BIT(1))
+#define GPIO_COMP0_POS_INT_RAW_M  (GPIO_COMP0_POS_INT_RAW_V << GPIO_COMP0_POS_INT_RAW_S)
+#define GPIO_COMP0_POS_INT_RAW_V  0x00000001U
+#define GPIO_COMP0_POS_INT_RAW_S  1
+/** GPIO_COMP0_ALL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  analog comparator neg or pos edge interrupt raw
+ */
+#define GPIO_COMP0_ALL_INT_RAW    (BIT(2))
+#define GPIO_COMP0_ALL_INT_RAW_M  (GPIO_COMP0_ALL_INT_RAW_V << GPIO_COMP0_ALL_INT_RAW_S)
+#define GPIO_COMP0_ALL_INT_RAW_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_RAW_S  2
+/** GPIO_COMP1_NEG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  analog comparator pos edge interrupt raw
+ */
+#define GPIO_COMP1_NEG_INT_RAW    (BIT(3))
+#define GPIO_COMP1_NEG_INT_RAW_M  (GPIO_COMP1_NEG_INT_RAW_V << GPIO_COMP1_NEG_INT_RAW_S)
+#define GPIO_COMP1_NEG_INT_RAW_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_RAW_S  3
+/** GPIO_COMP1_POS_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  analog comparator neg edge interrupt raw
+ */
+#define GPIO_COMP1_POS_INT_RAW    (BIT(4))
+#define GPIO_COMP1_POS_INT_RAW_M  (GPIO_COMP1_POS_INT_RAW_V << GPIO_COMP1_POS_INT_RAW_S)
+#define GPIO_COMP1_POS_INT_RAW_V  0x00000001U
+#define GPIO_COMP1_POS_INT_RAW_S  4
+/** GPIO_COMP1_ALL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  analog comparator neg or pos edge interrupt raw
+ */
+#define GPIO_COMP1_ALL_INT_RAW    (BIT(5))
+#define GPIO_COMP1_ALL_INT_RAW_M  (GPIO_COMP1_ALL_INT_RAW_V << GPIO_COMP1_ALL_INT_RAW_S)
+#define GPIO_COMP1_ALL_INT_RAW_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_RAW_S  5
+/** GPIO_BISTOK_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  pad bistok interrupt raw
+ */
+#define GPIO_BISTOK_INT_RAW    (BIT(6))
+#define GPIO_BISTOK_INT_RAW_M  (GPIO_BISTOK_INT_RAW_V << GPIO_BISTOK_INT_RAW_S)
+#define GPIO_BISTOK_INT_RAW_V  0x00000001U
+#define GPIO_BISTOK_INT_RAW_S  6
+/** GPIO_BISTFAIL_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  pad bistfail interrupt raw
+ */
+#define GPIO_BISTFAIL_INT_RAW    (BIT(7))
+#define GPIO_BISTFAIL_INT_RAW_M  (GPIO_BISTFAIL_INT_RAW_V << GPIO_BISTFAIL_INT_RAW_S)
+#define GPIO_BISTFAIL_INT_RAW_V  0x00000001U
+#define GPIO_BISTFAIL_INT_RAW_S  7
+
+/** GPIO_INT_ST_REG register
+ *  analog comparator interrupt status
+ */
+#define GPIO_INT_ST_REG (DR_REG_GPIO_BASE + 0x704)
+/** GPIO_COMP0_NEG_INT_ST : RO; bitpos: [0]; default: 0;
+ *  analog comparator pos edge interrupt status
+ */
+#define GPIO_COMP0_NEG_INT_ST    (BIT(0))
+#define GPIO_COMP0_NEG_INT_ST_M  (GPIO_COMP0_NEG_INT_ST_V << GPIO_COMP0_NEG_INT_ST_S)
+#define GPIO_COMP0_NEG_INT_ST_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_ST_S  0
+/** GPIO_COMP0_POS_INT_ST : RO; bitpos: [1]; default: 0;
+ *  analog comparator neg edge interrupt status
+ */
+#define GPIO_COMP0_POS_INT_ST    (BIT(1))
+#define GPIO_COMP0_POS_INT_ST_M  (GPIO_COMP0_POS_INT_ST_V << GPIO_COMP0_POS_INT_ST_S)
+#define GPIO_COMP0_POS_INT_ST_V  0x00000001U
+#define GPIO_COMP0_POS_INT_ST_S  1
+/** GPIO_COMP0_ALL_INT_ST : RO; bitpos: [2]; default: 0;
+ *  analog comparator neg or pos edge interrupt status
+ */
+#define GPIO_COMP0_ALL_INT_ST    (BIT(2))
+#define GPIO_COMP0_ALL_INT_ST_M  (GPIO_COMP0_ALL_INT_ST_V << GPIO_COMP0_ALL_INT_ST_S)
+#define GPIO_COMP0_ALL_INT_ST_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_ST_S  2
+/** GPIO_COMP1_NEG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  analog comparator pos edge interrupt status
+ */
+#define GPIO_COMP1_NEG_INT_ST    (BIT(3))
+#define GPIO_COMP1_NEG_INT_ST_M  (GPIO_COMP1_NEG_INT_ST_V << GPIO_COMP1_NEG_INT_ST_S)
+#define GPIO_COMP1_NEG_INT_ST_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_ST_S  3
+/** GPIO_COMP1_POS_INT_ST : RO; bitpos: [4]; default: 0;
+ *  analog comparator neg edge interrupt status
+ */
+#define GPIO_COMP1_POS_INT_ST    (BIT(4))
+#define GPIO_COMP1_POS_INT_ST_M  (GPIO_COMP1_POS_INT_ST_V << GPIO_COMP1_POS_INT_ST_S)
+#define GPIO_COMP1_POS_INT_ST_V  0x00000001U
+#define GPIO_COMP1_POS_INT_ST_S  4
+/** GPIO_COMP1_ALL_INT_ST : RO; bitpos: [5]; default: 0;
+ *  analog comparator neg or pos edge interrupt status
+ */
+#define GPIO_COMP1_ALL_INT_ST    (BIT(5))
+#define GPIO_COMP1_ALL_INT_ST_M  (GPIO_COMP1_ALL_INT_ST_V << GPIO_COMP1_ALL_INT_ST_S)
+#define GPIO_COMP1_ALL_INT_ST_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_ST_S  5
+/** GPIO_BISTOK_INT_ST : RO; bitpos: [6]; default: 0;
+ *  pad bistok interrupt status
+ */
+#define GPIO_BISTOK_INT_ST    (BIT(6))
+#define GPIO_BISTOK_INT_ST_M  (GPIO_BISTOK_INT_ST_V << GPIO_BISTOK_INT_ST_S)
+#define GPIO_BISTOK_INT_ST_V  0x00000001U
+#define GPIO_BISTOK_INT_ST_S  6
+/** GPIO_BISTFAIL_INT_ST : RO; bitpos: [7]; default: 0;
+ *  pad bistfail interrupt status
+ */
+#define GPIO_BISTFAIL_INT_ST    (BIT(7))
+#define GPIO_BISTFAIL_INT_ST_M  (GPIO_BISTFAIL_INT_ST_V << GPIO_BISTFAIL_INT_ST_S)
+#define GPIO_BISTFAIL_INT_ST_V  0x00000001U
+#define GPIO_BISTFAIL_INT_ST_S  7
+
+/** GPIO_INT_ENA_REG register
+ *  analog comparator interrupt enable
+ */
+#define GPIO_INT_ENA_REG (DR_REG_GPIO_BASE + 0x708)
+/** GPIO_COMP0_NEG_INT_ENA : R/W; bitpos: [0]; default: 1;
+ *  analog comparator pos edge interrupt enable
+ */
+#define GPIO_COMP0_NEG_INT_ENA    (BIT(0))
+#define GPIO_COMP0_NEG_INT_ENA_M  (GPIO_COMP0_NEG_INT_ENA_V << GPIO_COMP0_NEG_INT_ENA_S)
+#define GPIO_COMP0_NEG_INT_ENA_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_ENA_S  0
+/** GPIO_COMP0_POS_INT_ENA : R/W; bitpos: [1]; default: 1;
+ *  analog comparator neg edge interrupt enable
+ */
+#define GPIO_COMP0_POS_INT_ENA    (BIT(1))
+#define GPIO_COMP0_POS_INT_ENA_M  (GPIO_COMP0_POS_INT_ENA_V << GPIO_COMP0_POS_INT_ENA_S)
+#define GPIO_COMP0_POS_INT_ENA_V  0x00000001U
+#define GPIO_COMP0_POS_INT_ENA_S  1
+/** GPIO_COMP0_ALL_INT_ENA : R/W; bitpos: [2]; default: 1;
+ *  analog comparator neg or pos edge interrupt enable
+ */
+#define GPIO_COMP0_ALL_INT_ENA    (BIT(2))
+#define GPIO_COMP0_ALL_INT_ENA_M  (GPIO_COMP0_ALL_INT_ENA_V << GPIO_COMP0_ALL_INT_ENA_S)
+#define GPIO_COMP0_ALL_INT_ENA_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_ENA_S  2
+/** GPIO_COMP1_NEG_INT_ENA : R/W; bitpos: [3]; default: 1;
+ *  analog comparator pos edge interrupt enable
+ */
+#define GPIO_COMP1_NEG_INT_ENA    (BIT(3))
+#define GPIO_COMP1_NEG_INT_ENA_M  (GPIO_COMP1_NEG_INT_ENA_V << GPIO_COMP1_NEG_INT_ENA_S)
+#define GPIO_COMP1_NEG_INT_ENA_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_ENA_S  3
+/** GPIO_COMP1_POS_INT_ENA : R/W; bitpos: [4]; default: 1;
+ *  analog comparator neg edge interrupt enable
+ */
+#define GPIO_COMP1_POS_INT_ENA    (BIT(4))
+#define GPIO_COMP1_POS_INT_ENA_M  (GPIO_COMP1_POS_INT_ENA_V << GPIO_COMP1_POS_INT_ENA_S)
+#define GPIO_COMP1_POS_INT_ENA_V  0x00000001U
+#define GPIO_COMP1_POS_INT_ENA_S  4
+/** GPIO_COMP1_ALL_INT_ENA : R/W; bitpos: [5]; default: 1;
+ *  analog comparator neg or pos edge interrupt enable
+ */
+#define GPIO_COMP1_ALL_INT_ENA    (BIT(5))
+#define GPIO_COMP1_ALL_INT_ENA_M  (GPIO_COMP1_ALL_INT_ENA_V << GPIO_COMP1_ALL_INT_ENA_S)
+#define GPIO_COMP1_ALL_INT_ENA_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_ENA_S  5
+/** GPIO_BISTOK_INT_ENA : R/W; bitpos: [6]; default: 1;
+ *  pad bistok interrupt enable
+ */
+#define GPIO_BISTOK_INT_ENA    (BIT(6))
+#define GPIO_BISTOK_INT_ENA_M  (GPIO_BISTOK_INT_ENA_V << GPIO_BISTOK_INT_ENA_S)
+#define GPIO_BISTOK_INT_ENA_V  0x00000001U
+#define GPIO_BISTOK_INT_ENA_S  6
+/** GPIO_BISTFAIL_INT_ENA : R/W; bitpos: [7]; default: 1;
+ *  pad bistfail interrupt enable
+ */
+#define GPIO_BISTFAIL_INT_ENA    (BIT(7))
+#define GPIO_BISTFAIL_INT_ENA_M  (GPIO_BISTFAIL_INT_ENA_V << GPIO_BISTFAIL_INT_ENA_S)
+#define GPIO_BISTFAIL_INT_ENA_V  0x00000001U
+#define GPIO_BISTFAIL_INT_ENA_S  7
+
+/** GPIO_INT_CLR_REG register
+ *  analog comparator interrupt clear
+ */
+#define GPIO_INT_CLR_REG (DR_REG_GPIO_BASE + 0x70c)
+/** GPIO_COMP0_NEG_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  analog comparator pos edge interrupt clear
+ */
+#define GPIO_COMP0_NEG_INT_CLR    (BIT(0))
+#define GPIO_COMP0_NEG_INT_CLR_M  (GPIO_COMP0_NEG_INT_CLR_V << GPIO_COMP0_NEG_INT_CLR_S)
+#define GPIO_COMP0_NEG_INT_CLR_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_CLR_S  0
+/** GPIO_COMP0_POS_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  analog comparator neg edge interrupt clear
+ */
+#define GPIO_COMP0_POS_INT_CLR    (BIT(1))
+#define GPIO_COMP0_POS_INT_CLR_M  (GPIO_COMP0_POS_INT_CLR_V << GPIO_COMP0_POS_INT_CLR_S)
+#define GPIO_COMP0_POS_INT_CLR_V  0x00000001U
+#define GPIO_COMP0_POS_INT_CLR_S  1
+/** GPIO_COMP0_ALL_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  analog comparator neg or pos edge interrupt clear
+ */
+#define GPIO_COMP0_ALL_INT_CLR    (BIT(2))
+#define GPIO_COMP0_ALL_INT_CLR_M  (GPIO_COMP0_ALL_INT_CLR_V << GPIO_COMP0_ALL_INT_CLR_S)
+#define GPIO_COMP0_ALL_INT_CLR_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_CLR_S  2
+/** GPIO_COMP1_NEG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  analog comparator pos edge interrupt clear
+ */
+#define GPIO_COMP1_NEG_INT_CLR    (BIT(3))
+#define GPIO_COMP1_NEG_INT_CLR_M  (GPIO_COMP1_NEG_INT_CLR_V << GPIO_COMP1_NEG_INT_CLR_S)
+#define GPIO_COMP1_NEG_INT_CLR_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_CLR_S  3
+/** GPIO_COMP1_POS_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  analog comparator neg edge interrupt clear
+ */
+#define GPIO_COMP1_POS_INT_CLR    (BIT(4))
+#define GPIO_COMP1_POS_INT_CLR_M  (GPIO_COMP1_POS_INT_CLR_V << GPIO_COMP1_POS_INT_CLR_S)
+#define GPIO_COMP1_POS_INT_CLR_V  0x00000001U
+#define GPIO_COMP1_POS_INT_CLR_S  4
+/** GPIO_COMP1_ALL_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  analog comparator neg or pos edge interrupt clear
+ */
+#define GPIO_COMP1_ALL_INT_CLR    (BIT(5))
+#define GPIO_COMP1_ALL_INT_CLR_M  (GPIO_COMP1_ALL_INT_CLR_V << GPIO_COMP1_ALL_INT_CLR_S)
+#define GPIO_COMP1_ALL_INT_CLR_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_CLR_S  5
+/** GPIO_BISTOK_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  pad bistok interrupt enable
+ */
+#define GPIO_BISTOK_INT_CLR    (BIT(6))
+#define GPIO_BISTOK_INT_CLR_M  (GPIO_BISTOK_INT_CLR_V << GPIO_BISTOK_INT_CLR_S)
+#define GPIO_BISTOK_INT_CLR_V  0x00000001U
+#define GPIO_BISTOK_INT_CLR_S  6
+/** GPIO_BISTFAIL_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  pad bistfail interrupt enable
+ */
+#define GPIO_BISTFAIL_INT_CLR    (BIT(7))
+#define GPIO_BISTFAIL_INT_CLR_M  (GPIO_BISTFAIL_INT_CLR_V << GPIO_BISTFAIL_INT_CLR_S)
+#define GPIO_BISTFAIL_INT_CLR_V  0x00000001U
+#define GPIO_BISTFAIL_INT_CLR_S  7
+
+/** GPIO_ZERO_DET0_FILTER_CNT_REG register
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET0_FILTER_CNT_REG (DR_REG_GPIO_BASE + 0x710)
+/** GPIO_ZERO_DET0_FILTER_CNT : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET0_FILTER_CNT    0xFFFFFFFFU
+#define GPIO_ZERO_DET0_FILTER_CNT_M  (GPIO_ZERO_DET0_FILTER_CNT_V << GPIO_ZERO_DET0_FILTER_CNT_S)
+#define GPIO_ZERO_DET0_FILTER_CNT_V  0xFFFFFFFFU
+#define GPIO_ZERO_DET0_FILTER_CNT_S  0
+
+/** GPIO_ZERO_DET1_FILTER_CNT_REG register
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET1_FILTER_CNT_REG (DR_REG_GPIO_BASE + 0x714)
+/** GPIO_ZERO_DET1_FILTER_CNT : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET1_FILTER_CNT    0xFFFFFFFFU
+#define GPIO_ZERO_DET1_FILTER_CNT_M  (GPIO_ZERO_DET1_FILTER_CNT_V << GPIO_ZERO_DET1_FILTER_CNT_S)
+#define GPIO_ZERO_DET1_FILTER_CNT_V  0xFFFFFFFFU
+#define GPIO_ZERO_DET1_FILTER_CNT_S  0
+
+/** GPIO_SEND_SEQ_REG register
+ *  High speed sdio pad bist send sequence
+ */
+#define GPIO_SEND_SEQ_REG (DR_REG_GPIO_BASE + 0x718)
+/** GPIO_SEND_SEQ : R/W; bitpos: [31:0]; default: 305419896;
+ *  High speed sdio pad bist send sequence
+ */
+#define GPIO_SEND_SEQ    0xFFFFFFFFU
+#define GPIO_SEND_SEQ_M  (GPIO_SEND_SEQ_V << GPIO_SEND_SEQ_S)
+#define GPIO_SEND_SEQ_V  0xFFFFFFFFU
+#define GPIO_SEND_SEQ_S  0
+
+/** GPIO_RECIVE_SEQ_REG register
+ *  High speed sdio pad bist receive sequence
+ */
+#define GPIO_RECIVE_SEQ_REG (DR_REG_GPIO_BASE + 0x71c)
+/** GPIO_RECIVE_SEQ : RO; bitpos: [31:0]; default: 0;
+ *  High speed sdio pad bist receive sequence
+ */
+#define GPIO_RECIVE_SEQ    0xFFFFFFFFU
+#define GPIO_RECIVE_SEQ_M  (GPIO_RECIVE_SEQ_V << GPIO_RECIVE_SEQ_S)
+#define GPIO_RECIVE_SEQ_V  0xFFFFFFFFU
+#define GPIO_RECIVE_SEQ_S  0
+
+/** GPIO_BISTIN_SEL_REG register
+ *  High speed sdio pad bist in pad sel
+ */
+#define GPIO_BISTIN_SEL_REG (DR_REG_GPIO_BASE + 0x720)
+/** GPIO_BISTIN_SEL : R/W; bitpos: [3:0]; default: 15;
+ *  High speed sdio pad bist in pad sel 0:pad39, 1: pad40...
+ */
+#define GPIO_BISTIN_SEL    0x0000000FU
+#define GPIO_BISTIN_SEL_M  (GPIO_BISTIN_SEL_V << GPIO_BISTIN_SEL_S)
+#define GPIO_BISTIN_SEL_V  0x0000000FU
+#define GPIO_BISTIN_SEL_S  0
+
+/** GPIO_BIST_CTRL_REG register
+ *  High speed sdio pad bist control
+ */
+#define GPIO_BIST_CTRL_REG (DR_REG_GPIO_BASE + 0x724)
+/** GPIO_BIST_PAD_OE : R/W; bitpos: [0]; default: 1;
+ *  High speed sdio pad bist out pad oe
+ */
+#define GPIO_BIST_PAD_OE    (BIT(0))
+#define GPIO_BIST_PAD_OE_M  (GPIO_BIST_PAD_OE_V << GPIO_BIST_PAD_OE_S)
+#define GPIO_BIST_PAD_OE_V  0x00000001U
+#define GPIO_BIST_PAD_OE_S  0
+/** GPIO_BIST_START : WT; bitpos: [1]; default: 0;
+ *  High speed sdio pad bist start
+ */
+#define GPIO_BIST_START    (BIT(1))
+#define GPIO_BIST_START_M  (GPIO_BIST_START_V << GPIO_BIST_START_S)
+#define GPIO_BIST_START_V  0x00000001U
+#define GPIO_BIST_START_S  1
+/** GPIO_BIST_MODE : R/W; bitpos: [2]; default: 0;
+ *  Set 1 to enable sdio pad ddr200 bist mode
+ */
+#define GPIO_BIST_MODE    (BIT(2))
+#define GPIO_BIST_MODE_M  (GPIO_BIST_MODE_V << GPIO_BIST_MODE_S)
+#define GPIO_BIST_MODE_V  0x00000001U
+#define GPIO_BIST_MODE_S  2
+
+/** GPIO_DATE_REG register
+ *  GPIO version register
+ */
+#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x7fc)
+/** GPIO_DATE : R/W; bitpos: [27:0]; default: 2363942;
+ *  version register
+ */
+#define GPIO_DATE    0x0FFFFFFFU
+#define GPIO_DATE_M  (GPIO_DATE_V << GPIO_DATE_S)
+#define GPIO_DATE_V  0x0FFFFFFFU
+#define GPIO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h
new file mode 100644
index 0000000000..65c4a503c0
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h
@@ -0,0 +1,483 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define SD_CARD_CCLK_2_PAD_OUT_IDX               0
+#define SD_CARD_CCMD_2_PAD_IN_IDX                1
+#define SD_CARD_CCMD_2_PAD_OUT_IDX               1
+#define SD_CARD_CDATA0_2_PAD_IN_IDX              2
+#define SD_CARD_CDATA0_2_PAD_OUT_IDX             2
+#define SD_CARD_CDATA1_2_PAD_IN_IDX              3
+#define SD_CARD_CDATA1_2_PAD_OUT_IDX             3
+#define SD_CARD_CDATA2_2_PAD_IN_IDX              4
+#define SD_CARD_CDATA2_2_PAD_OUT_IDX             4
+#define SD_CARD_CDATA3_2_PAD_IN_IDX              5
+#define SD_CARD_CDATA3_2_PAD_OUT_IDX             5
+#define SD_CARD_CDATA4_2_PAD_IN_IDX              6
+#define SD_CARD_CDATA4_2_PAD_OUT_IDX             6
+#define SD_CARD_CDATA5_2_PAD_IN_IDX              7
+#define SD_CARD_CDATA5_2_PAD_OUT_IDX             7
+#define SD_CARD_CDATA6_2_PAD_IN_IDX              8
+#define SD_CARD_CDATA6_2_PAD_OUT_IDX             8
+#define SD_CARD_CDATA7_2_PAD_IN_IDX              9
+#define SD_CARD_CDATA7_2_PAD_OUT_IDX             9
+#define UART0_RXD_PAD_IN_IDX                     10
+#define UART0_TXD_PAD_OUT_IDX                    10
+#define UART0_CTS_PAD_IN_IDX                     11
+#define UART0_RTS_PAD_OUT_IDX                    11
+#define UART0_DSR_PAD_IN_IDX                     12
+#define UART0_DTR_PAD_OUT_IDX                    12
+#define UART1_RXD_PAD_IN_IDX                     13
+#define UART1_TXD_PAD_OUT_IDX                    13
+#define UART1_CTS_PAD_IN_IDX                     14
+#define UART1_RTS_PAD_OUT_IDX                    14
+#define UART1_DSR_PAD_IN_IDX                     15
+#define UART1_DTR_PAD_OUT_IDX                    15
+#define UART2_RXD_PAD_IN_IDX                     16
+#define UART2_TXD_PAD_OUT_IDX                    16
+#define UART2_CTS_PAD_IN_IDX                     17
+#define UART2_RTS_PAD_OUT_IDX                    17
+#define UART2_DSR_PAD_IN_IDX                     18
+#define UART2_DTR_PAD_OUT_IDX                    18
+#define UART3_RXD_PAD_IN_IDX                     19
+#define UART3_TXD_PAD_OUT_IDX                    19
+#define UART3_CTS_PAD_IN_IDX                     20
+#define UART3_RTS_PAD_OUT_IDX                    20
+#define UART3_DSR_PAD_IN_IDX                     21
+#define UART3_DTR_PAD_OUT_IDX                    21
+#define UART4_RXD_PAD_IN_IDX                     22
+#define UART4_TXD_PAD_OUT_IDX                    22
+#define UART4_CTS_PAD_IN_IDX                     23
+#define UART4_RTS_PAD_OUT_IDX                    23
+#define UART4_DSR_PAD_IN_IDX                     24
+#define UART4_DTR_PAD_OUT_IDX                    24
+#define I2S0_O_BCK_PAD_IN_IDX                    25
+#define I2S0_O_BCK_PAD_OUT_IDX                   25
+#define I2S0_MCLK_PAD_IN_IDX                     26
+#define I2S0_MCLK_PAD_OUT_IDX                    26
+#define I2S0_O_WS_PAD_IN_IDX                     27
+#define I2S0_O_WS_PAD_OUT_IDX                    27
+#define I2S0_I_SD_PAD_IN_IDX                     28
+#define I2S0_O_SD_PAD_OUT_IDX                    28
+#define I2S0_I_BCK_PAD_IN_IDX                    29
+#define I2S0_I_BCK_PAD_OUT_IDX                   29
+#define I2S0_I_WS_PAD_IN_IDX                     30
+#define I2S0_I_WS_PAD_OUT_IDX                    30
+#define I2S1_O_BCK_PAD_IN_IDX                    31
+#define I2S1_O_BCK_PAD_OUT_IDX                   31
+#define I2S1_MCLK_PAD_IN_IDX                     32
+#define I2S1_MCLK_PAD_OUT_IDX                    32
+#define I2S1_O_WS_PAD_IN_IDX                     33
+#define I2S1_O_WS_PAD_OUT_IDX                    33
+#define I2S1_I_SD_PAD_IN_IDX                     34
+#define I2S1_O_SD_PAD_OUT_IDX                    34
+#define I2S1_I_BCK_PAD_IN_IDX                    35
+#define I2S1_I_BCK_PAD_OUT_IDX                   35
+#define I2S1_I_WS_PAD_IN_IDX                     36
+#define I2S1_I_WS_PAD_OUT_IDX                    36
+#define I2S2_O_BCK_PAD_IN_IDX                    37
+#define I2S2_O_BCK_PAD_OUT_IDX                   37
+#define I2S2_MCLK_PAD_IN_IDX                     38
+#define I2S2_MCLK_PAD_OUT_IDX                    38
+#define I2S2_O_WS_PAD_IN_IDX                     39
+#define I2S2_O_WS_PAD_OUT_IDX                    39
+#define I2S2_I_SD_PAD_IN_IDX                     40
+#define I2S2_O_SD_PAD_OUT_IDX                    40
+#define I2S2_I_BCK_PAD_IN_IDX                    41
+#define I2S2_I_BCK_PAD_OUT_IDX                   41
+#define I2S2_I_WS_PAD_IN_IDX                     42
+#define I2S2_I_WS_PAD_OUT_IDX                    42
+#define I2S0_I_SD1_PAD_IN_IDX                    43
+#define I2S0_O_SD1_PAD_OUT_IDX                   43
+#define I2S0_I_SD2_PAD_IN_IDX                    44
+#define SPI2_DQS_PAD_OUT_IDX                     44
+#define I2S0_I_SD3_PAD_IN_IDX                    45
+#define SPI3_CS2_PAD_OUT_IDX                     45
+#define SPI3_CS1_PAD_OUT_IDX                     46
+#define SPI3_CK_PAD_IN_IDX                       47
+#define SPI3_CK_PAD_OUT_IDX                      47
+#define SPI3_Q_PAD_IN_IDX                        48
+#define SPI3_QO_PAD_OUT_IDX                      48
+#define SPI3_D_PAD_IN_IDX                        49
+#define SPI3_D_PAD_OUT_IDX                       49
+#define SPI3_HOLD_PAD_IN_IDX                     50
+#define SPI3_HOLD_PAD_OUT_IDX                    50
+#define SPI3_WP_PAD_IN_IDX                       51
+#define SPI3_WP_PAD_OUT_IDX                      51
+#define SPI3_CS_PAD_IN_IDX                       52
+#define SPI3_CS_PAD_OUT_IDX                      52
+#define SPI2_CK_PAD_IN_IDX                       53
+#define SPI2_CK_PAD_OUT_IDX                      53
+#define SPI2_Q_PAD_IN_IDX                        54
+#define SPI2_Q_PAD_OUT_IDX                       54
+#define SPI2_D_PAD_IN_IDX                        55
+#define SPI2_D_PAD_OUT_IDX                       55
+#define SPI2_HOLD_PAD_IN_IDX                     56
+#define SPI2_HOLD_PAD_OUT_IDX                    56
+#define SPI2_WP_PAD_IN_IDX                       57
+#define SPI2_WP_PAD_OUT_IDX                      57
+#define SPI2_IO4_PAD_IN_IDX                      58
+#define SPI2_IO4_PAD_OUT_IDX                     58
+#define SPI2_IO5_PAD_IN_IDX                      59
+#define SPI2_IO5_PAD_OUT_IDX                     59
+#define SPI2_IO6_PAD_IN_IDX                      60
+#define SPI2_IO6_PAD_OUT_IDX                     60
+#define SPI2_IO7_PAD_IN_IDX                      61
+#define SPI2_IO7_PAD_OUT_IDX                     61
+#define SPI2_CS_PAD_IN_IDX                       62
+#define SPI2_CS_PAD_OUT_IDX                      62
+#define PCNT_RST_PAD_IN0_IDX                     63
+#define SPI2_CS1_PAD_OUT_IDX                     63
+#define PCNT_RST_PAD_IN1_IDX                     64
+#define SPI2_CS2_PAD_OUT_IDX                     64
+#define PCNT_RST_PAD_IN2_IDX                     65
+#define SPI2_CS3_PAD_OUT_IDX                     65
+#define PCNT_RST_PAD_IN3_IDX                     66
+#define SPI2_CS4_PAD_OUT_IDX                     66
+#define SPI2_CS5_PAD_OUT_IDX                     67
+#define I2C0_SCL_PAD_IN_IDX                      68
+#define I2C0_SCL_PAD_OUT_IDX                     68
+#define I2C0_SDA_PAD_IN_IDX                      69
+#define I2C0_SDA_PAD_OUT_IDX                     69
+#define I2C1_SCL_PAD_IN_IDX                      70
+#define I2C1_SCL_PAD_OUT_IDX                     70
+#define I2C1_SDA_PAD_IN_IDX                      71
+#define I2C1_SDA_PAD_OUT_IDX                     71
+#define GPIO_SD0_OUT_IDX                         72
+#define GPIO_SD1_OUT_IDX                         73
+#define UART0_SLP_CLK_PAD_IN_IDX                 74
+#define GPIO_SD2_OUT_IDX                         74
+#define UART1_SLP_CLK_PAD_IN_IDX                 75
+#define GPIO_SD3_OUT_IDX                         75
+#define UART2_SLP_CLK_PAD_IN_IDX                 76
+#define GPIO_SD4_OUT_IDX                         76
+#define UART3_SLP_CLK_PAD_IN_IDX                 77
+#define GPIO_SD5_OUT_IDX                         77
+#define UART4_SLP_CLK_PAD_IN_IDX                 78
+#define GPIO_SD6_OUT_IDX                         78
+#define GPIO_SD7_OUT_IDX                         79
+#define TWAI0_RX_PAD_IN_IDX                      80
+#define TWAI0_TX_PAD_OUT_IDX                     80
+#define TWAI0_BUS_OFF_ON_PAD_OUT_IDX             81
+#define TWAI0_CLKOUT_PAD_OUT_IDX                 82
+#define TWAI1_RX_PAD_IN_IDX                      83
+#define TWAI1_TX_PAD_OUT_IDX                     83
+#define TWAI1_BUS_OFF_ON_PAD_OUT_IDX             84
+#define TWAI1_CLKOUT_PAD_OUT_IDX                 85
+#define TWAI2_RX_PAD_IN_IDX                      86
+#define TWAI2_TX_PAD_OUT_IDX                     86
+#define TWAI2_BUS_OFF_ON_PAD_OUT_IDX             87
+#define TWAI2_CLKOUT_PAD_OUT_IDX                 88
+#define PWM0_SYNC0_PAD_IN_IDX                    89
+#define PWM0_CH0_A_PAD_OUT_IDX                   89
+#define PWM0_SYNC1_PAD_IN_IDX                    90
+#define PWM0_CH0_B_PAD_OUT_IDX                   90
+#define PWM0_SYNC2_PAD_IN_IDX                    91
+#define PWM0_CH1_A_PAD_OUT_IDX                   91
+#define PWM0_F0_PAD_IN_IDX                       92
+#define PWM0_CH1_B_PAD_OUT_IDX                   92
+#define PWM0_F1_PAD_IN_IDX                       93
+#define PWM0_CH2_A_PAD_OUT_IDX                   93
+#define PWM0_F2_PAD_IN_IDX                       94
+#define PWM0_CH2_B_PAD_OUT_IDX                   94
+#define PWM0_CAP0_PAD_IN_IDX                     95
+#define PWM1_CH0_A_PAD_OUT_IDX                   95
+#define PWM0_CAP1_PAD_IN_IDX                     96
+#define PWM1_CH0_B_PAD_OUT_IDX                   96
+#define PWM0_CAP2_PAD_IN_IDX                     97
+#define PWM1_CH1_A_PAD_OUT_IDX                   97
+#define PWM1_SYNC0_PAD_IN_IDX                    98
+#define PWM1_CH1_B_PAD_OUT_IDX                   98
+#define PWM1_SYNC1_PAD_IN_IDX                    99
+#define PWM1_CH2_A_PAD_OUT_IDX                   99
+#define PWM1_SYNC2_PAD_IN_IDX                    100
+#define PWM1_CH2_B_PAD_OUT_IDX                   100
+#define PWM1_F0_PAD_IN_IDX                       101
+#define PWM1_F1_PAD_IN_IDX                       102
+#define PWM1_F2_PAD_IN_IDX                       103
+#define PWM1_CAP0_PAD_IN_IDX                     104
+#define PWM1_CAP1_PAD_IN_IDX                     105
+#define TWAI0_STANDBY_PAD_OUT_IDX                105
+#define PWM1_CAP2_PAD_IN_IDX                     106
+#define TWAI1_STANDBY_PAD_OUT_IDX                106
+#define GMII_MDI_PAD_IN_IDX                      107
+#define TWAI2_STANDBY_PAD_OUT_IDX                107
+#define GMAC_PHY_COL_PAD_IN_IDX                  108
+#define GMII_MDC_PAD_OUT_IDX                     108
+#define GMAC_PHY_CRS_PAD_IN_IDX                  109
+#define GMII_MDO_PAD_OUT_IDX                     109
+#define USB_OTG11_IDDIG_PAD_IN_IDX               110
+#define USB_SRP_DISCHRGVBUS_PAD_OUT_IDX          110
+#define USB_OTG11_AVALID_PAD_IN_IDX              111
+#define USB_OTG11_IDPULLUP_PAD_OUT_IDX           111
+#define USB_SRP_BVALID_PAD_IN_IDX                112
+#define USB_OTG11_DPPULLDOWN_PAD_OUT_IDX         112
+#define USB_OTG11_VBUSVALID_PAD_IN_IDX           113
+#define USB_OTG11_DMPULLDOWN_PAD_OUT_IDX         113
+#define USB_SRP_SESSEND_PAD_IN_IDX               114
+#define USB_OTG11_DRVVBUS_PAD_OUT_IDX            114
+#define USB_SRP_CHRGVBUS_PAD_OUT_IDX             115
+#define ULPI_CLK_PAD_IN_IDX                      117
+#define RNG_CHAIN_CLK_PAD_OUT_IDX                117
+#define USB_HSPHY_REFCLK_IN_IDX                  118
+#define HP_PROBE_TOP_OUT0_IDX                    118
+#define HP_PROBE_TOP_OUT1_IDX                    119
+#define HP_PROBE_TOP_OUT2_IDX                    120
+#define HP_PROBE_TOP_OUT3_IDX                    121
+#define HP_PROBE_TOP_OUT4_IDX                    122
+#define HP_PROBE_TOP_OUT5_IDX                    123
+#define HP_PROBE_TOP_OUT6_IDX                    124
+#define HP_PROBE_TOP_OUT7_IDX                    125
+#define SD_CARD_DETECT_N_1_PAD_IN_IDX            126
+#define LEDC_LS_SIG_OUT_PAD_OUT0_IDX             126
+#define SD_CARD_DETECT_N_2_PAD_IN_IDX            127
+#define LEDC_LS_SIG_OUT_PAD_OUT1_IDX             127
+#define SD_CARD_INT_N_1_PAD_IN_IDX               128
+#define LEDC_LS_SIG_OUT_PAD_OUT2_IDX             128
+#define SD_CARD_INT_N_2_PAD_IN_IDX               129
+#define LEDC_LS_SIG_OUT_PAD_OUT3_IDX             129
+#define SD_CARD_WRITE_PRT_1_PAD_IN_IDX           130
+#define LEDC_LS_SIG_OUT_PAD_OUT4_IDX             130
+#define SD_CARD_WRITE_PRT_2_PAD_IN_IDX           131
+#define LEDC_LS_SIG_OUT_PAD_OUT5_IDX             131
+#define SD_DATA_STROBE_1_PAD_IN_IDX              132
+#define LEDC_LS_SIG_OUT_PAD_OUT6_IDX             132
+#define SD_DATA_STROBE_2_PAD_IN_IDX              133
+#define LEDC_LS_SIG_OUT_PAD_OUT7_IDX             133
+#define I3C_MST_SCL_PAD_IN_IDX                   134
+#define I3C_MST_SCL_PAD_OUT_IDX                  134
+#define I3C_MST_SDA_PAD_IN_IDX                   135
+#define I3C_MST_SDA_PAD_OUT_IDX                  135
+#define I3C_SLV_SCL_PAD_IN_IDX                   136
+#define I3C_SLV_SCL_PAD_OUT_IDX                  136
+#define I3C_SLV_SDA_PAD_IN_IDX                   137
+#define I3C_SLV_SDA_PAD_OUT_IDX                  137
+#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX        138
+#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX        139
+#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX           140
+#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX          140
+#define PCNT_SIG_CH0_PAD_IN0_IDX                 141
+#define USB_JTAG_TMS_BRIDGE_PAD_OUT_IDX          141
+#define PCNT_SIG_CH0_PAD_IN1_IDX                 142
+#define USB_JTAG_TCK_BRIDGE_PAD_OUT_IDX          142
+#define PCNT_SIG_CH0_PAD_IN2_IDX                 143
+#define USB_JTAG_TRST_BRIDGE_PAD_OUT_IDX         143
+#define PCNT_SIG_CH0_PAD_IN3_IDX                 144
+#define LCD_CS_PAD_OUT_IDX                       144
+#define PCNT_SIG_CH1_PAD_IN0_IDX                 145
+#define LCD_DC_PAD_OUT_IDX                       145
+#define PCNT_SIG_CH1_PAD_IN1_IDX                 146
+#define SD_RST_N_1_PAD_OUT_IDX                   146
+#define PCNT_SIG_CH1_PAD_IN2_IDX                 147
+#define SD_RST_N_2_PAD_OUT_IDX                   147
+#define PCNT_SIG_CH1_PAD_IN3_IDX                 148
+#define SD_CCMD_OD_PULLUP_EN_N_PAD_OUT_IDX       148
+#define PCNT_CTRL_CH0_PAD_IN0_IDX                149
+#define LCD_PCLK_PAD_OUT_IDX                     149
+#define PCNT_CTRL_CH0_PAD_IN1_IDX                150
+#define CAM_CLK_PAD_OUT_IDX                      150
+#define PCNT_CTRL_CH0_PAD_IN2_IDX                151
+#define LCD_H_ENABLE_PAD_OUT_IDX                 151
+#define PCNT_CTRL_CH0_PAD_IN3_IDX                152
+#define LCD_H_SYNC_PAD_OUT_IDX                   152
+#define PCNT_CTRL_CH1_PAD_IN0_IDX                153
+#define LCD_V_SYNC_PAD_OUT_IDX                   153
+#define PCNT_CTRL_CH1_PAD_IN1_IDX                154
+#define LCD_DATA_OUT_PAD_OUT0_IDX                154
+#define PCNT_CTRL_CH1_PAD_IN2_IDX                155
+#define LCD_DATA_OUT_PAD_OUT1_IDX                155
+#define PCNT_CTRL_CH1_PAD_IN3_IDX                156
+#define LCD_DATA_OUT_PAD_OUT2_IDX                156
+#define LCD_DATA_OUT_PAD_OUT3_IDX                157
+#define CAM_PCLK_PAD_IN_IDX                      158
+#define LCD_DATA_OUT_PAD_OUT4_IDX                158
+#define CAM_H_ENABLE_PAD_IN_IDX                  159
+#define LCD_DATA_OUT_PAD_OUT5_IDX                159
+#define CAM_H_SYNC_PAD_IN_IDX                    160
+#define LCD_DATA_OUT_PAD_OUT6_IDX                160
+#define CAM_V_SYNC_PAD_IN_IDX                    161
+#define LCD_DATA_OUT_PAD_OUT7_IDX                161
+#define CAM_DATA_IN_PAD_IN0_IDX                  162
+#define LCD_DATA_OUT_PAD_OUT8_IDX                162
+#define CAM_DATA_IN_PAD_IN1_IDX                  163
+#define LCD_DATA_OUT_PAD_OUT9_IDX                163
+#define CAM_DATA_IN_PAD_IN2_IDX                  164
+#define LCD_DATA_OUT_PAD_OUT10_IDX               164
+#define CAM_DATA_IN_PAD_IN3_IDX                  165
+#define LCD_DATA_OUT_PAD_OUT11_IDX               165
+#define CAM_DATA_IN_PAD_IN4_IDX                  166
+#define LCD_DATA_OUT_PAD_OUT12_IDX               166
+#define CAM_DATA_IN_PAD_IN5_IDX                  167
+#define LCD_DATA_OUT_PAD_OUT13_IDX               167
+#define CAM_DATA_IN_PAD_IN6_IDX                  168
+#define LCD_DATA_OUT_PAD_OUT14_IDX               168
+#define CAM_DATA_IN_PAD_IN7_IDX                  169
+#define LCD_DATA_OUT_PAD_OUT15_IDX               169
+#define CAM_DATA_IN_PAD_IN8_IDX                  170
+#define LCD_DATA_OUT_PAD_OUT16_IDX               170
+#define CAM_DATA_IN_PAD_IN9_IDX                  171
+#define LCD_DATA_OUT_PAD_OUT17_IDX               171
+#define CAM_DATA_IN_PAD_IN10_IDX                 172
+#define LCD_DATA_OUT_PAD_OUT18_IDX               172
+#define CAM_DATA_IN_PAD_IN11_IDX                 173
+#define LCD_DATA_OUT_PAD_OUT19_IDX               173
+#define CAM_DATA_IN_PAD_IN12_IDX                 174
+#define LCD_DATA_OUT_PAD_OUT20_IDX               174
+#define CAM_DATA_IN_PAD_IN13_IDX                 175
+#define LCD_DATA_OUT_PAD_OUT21_IDX               175
+#define CAM_DATA_IN_PAD_IN14_IDX                 176
+#define LCD_DATA_OUT_PAD_OUT22_IDX               176
+#define CAM_DATA_IN_PAD_IN15_IDX                 177
+#define LCD_DATA_OUT_PAD_OUT23_IDX               177
+#define GMAC_PHY_RXDV_PAD_IN_IDX                 178
+#define GMAC_PHY_TXEN_PAD_OUT_IDX                178
+#define GMAC_PHY_RXD0_PAD_IN_IDX                 179
+#define GMAC_PHY_TXD0_PAD_OUT_IDX                179
+#define GMAC_PHY_RXD1_PAD_IN_IDX                 180
+#define GMAC_PHY_TXD1_PAD_OUT_IDX                180
+#define GMAC_PHY_RXD2_PAD_IN_IDX                 181
+#define GMAC_PHY_TXD2_PAD_OUT_IDX                181
+#define GMAC_PHY_RXD3_PAD_IN_IDX                 182
+#define GMAC_PHY_TXD3_PAD_OUT_IDX                182
+#define GMAC_PHY_RXER_PAD_IN_IDX                 183
+#define GMAC_PHY_TXER_PAD_OUT_IDX                183
+#define GMAC_RX_CLK_PAD_IN_IDX                   184
+#define DBG_CH0_CLK_IDX                          184
+#define GMAC_TX_CLK_PAD_IN_IDX                   185
+#define DBG_CH1_CLK_IDX                          185
+#define PARLIO_RX_CLK_PAD_IN_IDX                 186
+#define PARLIO_RX_CLK_PAD_OUT_IDX                186
+#define PARLIO_TX_CLK_PAD_IN_IDX                 187
+#define PARLIO_TX_CLK_PAD_OUT_IDX                187
+#define PARLIO_RX_DATA0_PAD_IN_IDX               188
+#define PARLIO_TX_DATA0_PAD_OUT_IDX              188
+#define PARLIO_RX_DATA1_PAD_IN_IDX               189
+#define PARLIO_TX_DATA1_PAD_OUT_IDX              189
+#define PARLIO_RX_DATA2_PAD_IN_IDX               190
+#define PARLIO_TX_DATA2_PAD_OUT_IDX              190
+#define PARLIO_RX_DATA3_PAD_IN_IDX               191
+#define PARLIO_TX_DATA3_PAD_OUT_IDX              191
+#define PARLIO_RX_DATA4_PAD_IN_IDX               192
+#define PARLIO_TX_DATA4_PAD_OUT_IDX              192
+#define PARLIO_RX_DATA5_PAD_IN_IDX               193
+#define PARLIO_TX_DATA5_PAD_OUT_IDX              193
+#define PARLIO_RX_DATA6_PAD_IN_IDX               194
+#define PARLIO_TX_DATA6_PAD_OUT_IDX              194
+#define PARLIO_RX_DATA7_PAD_IN_IDX               195
+#define PARLIO_TX_DATA7_PAD_OUT_IDX              195
+#define PARLIO_RX_DATA8_PAD_IN_IDX               196
+#define PARLIO_TX_DATA8_PAD_OUT_IDX              196
+#define PARLIO_RX_DATA9_PAD_IN_IDX               197
+#define PARLIO_TX_DATA9_PAD_OUT_IDX              197
+#define PARLIO_RX_DATA10_PAD_IN_IDX              198
+#define PARLIO_TX_DATA10_PAD_OUT_IDX             198
+#define PARLIO_RX_DATA11_PAD_IN_IDX              199
+#define PARLIO_TX_DATA11_PAD_OUT_IDX             199
+#define PARLIO_RX_DATA12_PAD_IN_IDX              200
+#define PARLIO_TX_DATA12_PAD_OUT_IDX             200
+#define PARLIO_RX_DATA13_PAD_IN_IDX              201
+#define PARLIO_TX_DATA13_PAD_OUT_IDX             201
+#define PARLIO_RX_DATA14_PAD_IN_IDX              202
+#define PARLIO_TX_DATA14_PAD_OUT_IDX             202
+#define PARLIO_RX_DATA15_PAD_IN_IDX              203
+#define PARLIO_TX_DATA15_PAD_OUT_IDX             203
+#define HP_PROBE_TOP_OUT8_IDX                    204
+#define HP_PROBE_TOP_OUT9_IDX                    205
+#define HP_PROBE_TOP_OUT10_IDX                   206
+#define HP_PROBE_TOP_OUT11_IDX                   207
+#define HP_PROBE_TOP_OUT12_IDX                   208
+#define HP_PROBE_TOP_OUT13_IDX                   209
+#define HP_PROBE_TOP_OUT14_IDX                   210
+#define HP_PROBE_TOP_OUT15_IDX                   211
+#define CONSTANT0_PAD_OUT_IDX                    212
+#define CONSTANT1_PAD_OUT_IDX                    213
+#define CORE_GPIO_IN_PAD_IN0_IDX                 214
+#define CORE_GPIO_OUT_PAD_OUT0_IDX               214
+#define CORE_GPIO_IN_PAD_IN1_IDX                 215
+#define CORE_GPIO_OUT_PAD_OUT1_IDX               215
+#define CORE_GPIO_IN_PAD_IN2_IDX                 216
+#define CORE_GPIO_OUT_PAD_OUT2_IDX               216
+#define CORE_GPIO_IN_PAD_IN3_IDX                 217
+#define CORE_GPIO_OUT_PAD_OUT3_IDX               217
+#define CORE_GPIO_IN_PAD_IN4_IDX                 218
+#define CORE_GPIO_OUT_PAD_OUT4_IDX               218
+#define CORE_GPIO_IN_PAD_IN5_IDX                 219
+#define CORE_GPIO_OUT_PAD_OUT5_IDX               219
+#define CORE_GPIO_IN_PAD_IN6_IDX                 220
+#define CORE_GPIO_OUT_PAD_OUT6_IDX               220
+#define CORE_GPIO_IN_PAD_IN7_IDX                 221
+#define CORE_GPIO_OUT_PAD_OUT7_IDX               221
+#define CORE_GPIO_IN_PAD_IN8_IDX                 222
+#define CORE_GPIO_OUT_PAD_OUT8_IDX               222
+#define CORE_GPIO_IN_PAD_IN9_IDX                 223
+#define CORE_GPIO_OUT_PAD_OUT9_IDX               223
+#define CORE_GPIO_IN_PAD_IN10_IDX                224
+#define CORE_GPIO_OUT_PAD_OUT10_IDX              224
+#define CORE_GPIO_IN_PAD_IN11_IDX                225
+#define CORE_GPIO_OUT_PAD_OUT11_IDX              225
+#define CORE_GPIO_IN_PAD_IN12_IDX                226
+#define CORE_GPIO_OUT_PAD_OUT12_IDX              226
+#define CORE_GPIO_IN_PAD_IN13_IDX                227
+#define CORE_GPIO_OUT_PAD_OUT13_IDX              227
+#define CORE_GPIO_IN_PAD_IN14_IDX                228
+#define CORE_GPIO_OUT_PAD_OUT14_IDX              228
+#define CORE_GPIO_IN_PAD_IN15_IDX                229
+#define CORE_GPIO_OUT_PAD_OUT15_IDX              229
+#define CORE_GPIO_IN_PAD_IN16_IDX                230
+#define CORE_GPIO_OUT_PAD_OUT16_IDX              230
+#define CORE_GPIO_IN_PAD_IN17_IDX                231
+#define CORE_GPIO_OUT_PAD_OUT17_IDX              231
+#define CORE_GPIO_IN_PAD_IN18_IDX                232
+#define CORE_GPIO_OUT_PAD_OUT18_IDX              232
+#define CORE_GPIO_IN_PAD_IN19_IDX                233
+#define CORE_GPIO_OUT_PAD_OUT19_IDX              233
+#define CORE_GPIO_IN_PAD_IN20_IDX                234
+#define CORE_GPIO_OUT_PAD_OUT20_IDX              234
+#define CORE_GPIO_IN_PAD_IN21_IDX                235
+#define CORE_GPIO_OUT_PAD_OUT21_IDX              235
+#define CORE_GPIO_IN_PAD_IN22_IDX                236
+#define CORE_GPIO_OUT_PAD_OUT22_IDX              236
+#define CORE_GPIO_IN_PAD_IN23_IDX                237
+#define CORE_GPIO_OUT_PAD_OUT23_IDX              237
+#define CORE_GPIO_IN_PAD_IN24_IDX                238
+#define CORE_GPIO_OUT_PAD_OUT24_IDX              238
+#define CORE_GPIO_IN_PAD_IN25_IDX                239
+#define CORE_GPIO_OUT_PAD_OUT25_IDX              239
+#define CORE_GPIO_IN_PAD_IN26_IDX                240
+#define CORE_GPIO_OUT_PAD_OUT26_IDX              240
+#define CORE_GPIO_IN_PAD_IN27_IDX                241
+#define CORE_GPIO_OUT_PAD_OUT27_IDX              241
+#define CORE_GPIO_IN_PAD_IN28_IDX                242
+#define PARLIO_TX_CS_PAD_OUT_IDX                 242
+#define CORE_GPIO_IN_PAD_IN29_IDX                243
+#define EMAC_PTP_PPS_PAD_OUT_IDX                 243
+#define CORE_GPIO_IN_PAD_IN30_IDX                244
+#define ANA_COMP0_OUT_IDX                        244
+#define CORE_GPIO_IN_PAD_IN31_IDX                245
+#define ANA_COMP1_OUT_IDX                        245
+#define RMT_SIG_PAD_IN0_IDX                      246
+#define RMT_SIG_PAD_OUT0_IDX                     246
+#define RMT_SIG_PAD_IN1_IDX                      247
+#define RMT_SIG_PAD_OUT1_IDX                     247
+#define RMT_SIG_PAD_IN2_IDX                      248
+#define RMT_SIG_PAD_OUT2_IDX                     248
+#define RMT_SIG_PAD_IN3_IDX                      249
+#define RMT_SIG_PAD_OUT3_IDX                     249
+#define SIG_IN_FUNC250_IDX                       250
+#define SIG_IN_FUNC250_IDX                       250
+#define SIG_IN_FUNC251_IDX                       251
+#define SIG_IN_FUNC251_IDX                       251
+#define SIG_IN_FUNC252_IDX                       252
+#define SIG_IN_FUNC252_IDX                       252
+#define SIG_IN_FUNC253_IDX                       253
+#define SIG_IN_FUNC253_IDX                       253
+#define SIG_IN_FUNC254_IDX                       254
+#define SIG_IN_FUNC254_IDX                       254
+#define SIG_IN_FUNC255_IDX                       255
+#define SIG_IN_FUNC255_IDX                       255
+// version date 230403
+#define SIG_GPIO_OUT_IDX                        256
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_struct.h
new file mode 100644
index 0000000000..f986157531
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/gpio_struct.h
@@ -0,0 +1,878 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration register */
+/** Type of bt_select register
+ *  GPIO bit select register
+ */
+typedef union {
+    struct {
+        /** bt_sel : R/W; bitpos: [31:0]; default: 0;
+         *  GPIO bit select register
+         */
+        uint32_t bt_sel:32;
+    };
+    uint32_t val;
+} gpio_bt_select_reg_t;
+
+/** Type of out register
+ *  GPIO output register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0;
+         *  GPIO output register for GPIO0-31
+         */
+        uint32_t out_data_orig:32;
+    };
+    uint32_t val;
+} gpio_out_reg_t;
+
+/** Type of out_w1ts register
+ *  GPIO output set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output set register for GPIO0-31
+         */
+        uint32_t out_w1ts:32;
+    };
+    uint32_t val;
+} gpio_out_w1ts_reg_t;
+
+/** Type of out_w1tc register
+ *  GPIO output clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output clear register for GPIO0-31
+         */
+        uint32_t out_w1tc:32;
+    };
+    uint32_t val;
+} gpio_out_w1tc_reg_t;
+
+/** Type of out1 register
+ *  GPIO output register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** out1_data_orig : R/W/SC/WTC; bitpos: [24:0]; default: 0;
+         *  GPIO output register for GPIO32-56
+         */
+        uint32_t out1_data_orig:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out1_reg_t;
+
+/** Type of out1_w1ts register
+ *  GPIO output set register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** out1_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output set register for GPIO32-56
+         */
+        uint32_t out1_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out1_w1ts_reg_t;
+
+/** Type of out1_w1tc register
+ *  GPIO output clear register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** out1_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output clear register for GPIO32-56
+         */
+        uint32_t out1_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out1_w1tc_reg_t;
+
+/** Type of enable register
+ *  GPIO output enable register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0;
+         *  GPIO output enable register for GPIO0-31
+         */
+        uint32_t enable_data:32;
+    };
+    uint32_t val;
+} gpio_enable_reg_t;
+
+/** Type of enable_w1ts register
+ *  GPIO output enable set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output enable set register for GPIO0-31
+         */
+        uint32_t enable_w1ts:32;
+    };
+    uint32_t val;
+} gpio_enable_w1ts_reg_t;
+
+/** Type of enable_w1tc register
+ *  GPIO output enable clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output enable clear register for GPIO0-31
+         */
+        uint32_t enable_w1tc:32;
+    };
+    uint32_t val;
+} gpio_enable_w1tc_reg_t;
+
+/** Type of enable1 register
+ *  GPIO output enable register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** enable1_data : R/W/WTC; bitpos: [24:0]; default: 0;
+         *  GPIO output enable register for GPIO32-56
+         */
+        uint32_t enable1_data:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable1_reg_t;
+
+/** Type of enable1_w1ts register
+ *  GPIO output enable set register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** enable1_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output enable set register for GPIO32-56
+         */
+        uint32_t enable1_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable1_w1ts_reg_t;
+
+/** Type of enable1_w1tc register
+ *  GPIO output enable clear register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** enable1_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output enable clear register for GPIO32-56
+         */
+        uint32_t enable1_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable1_w1tc_reg_t;
+
+/** Type of strap register
+ *  pad strapping register
+ */
+typedef union {
+    struct {
+        /** strapping : RO; bitpos: [15:0]; default: 0;
+         *  pad strapping register
+         */
+        uint32_t strapping:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpio_strap_reg_t;
+
+/** Type of in register
+ *  GPIO input register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** in_data_next : RO; bitpos: [31:0]; default: 0;
+         *  GPIO input register for GPIO0-31
+         */
+        uint32_t in_data_next:32;
+    };
+    uint32_t val;
+} gpio_in_reg_t;
+
+/** Type of in1 register
+ *  GPIO input register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** in1_data_next : RO; bitpos: [24:0]; default: 0;
+         *  GPIO input register for GPIO32-56
+         */
+        uint32_t in1_data_next:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_in1_reg_t;
+
+/** Type of status register
+ *  GPIO interrupt status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status register for GPIO0-31
+         */
+        uint32_t status_interrupt:32;
+    };
+    uint32_t val;
+} gpio_status_reg_t;
+
+/** Type of status_w1ts register
+ *  GPIO interrupt status set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status set register for GPIO0-31
+         */
+        uint32_t status_w1ts:32;
+    };
+    uint32_t val;
+} gpio_status_w1ts_reg_t;
+
+/** Type of status_w1tc register
+ *  GPIO interrupt status clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status clear register for GPIO0-31
+         */
+        uint32_t status_w1tc:32;
+    };
+    uint32_t val;
+} gpio_status_w1tc_reg_t;
+
+/** Type of status1 register
+ *  GPIO interrupt status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status1_interrupt : R/W/WTC; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status register for GPIO32-56
+         */
+        uint32_t status1_interrupt:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status1_reg_t;
+
+/** Type of status1_w1ts register
+ *  GPIO interrupt status set register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status1_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status set register for GPIO32-56
+         */
+        uint32_t status1_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status1_w1ts_reg_t;
+
+/** Type of status1_w1tc register
+ *  GPIO interrupt status clear register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status1_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status clear register for GPIO32-56
+         */
+        uint32_t status1_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status1_w1tc_reg_t;
+
+/** Type of intr_0 register
+ *  GPIO interrupt 0 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_0 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 0 status register for GPIO0-31
+         */
+        uint32_t int_0:32;
+    };
+    uint32_t val;
+} gpio_intr_0_reg_t;
+
+/** Type of intr1_0 register
+ *  GPIO interrupt 0 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_0 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 0 status register for GPIO32-56
+         */
+        uint32_t int1_0:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_0_reg_t;
+
+/** Type of intr_1 register
+ *  GPIO interrupt 1 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_1 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 1 status register for GPIO0-31
+         */
+        uint32_t int_1:32;
+    };
+    uint32_t val;
+} gpio_intr_1_reg_t;
+
+/** Type of intr1_1 register
+ *  GPIO interrupt 1 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_1 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 1 status register for GPIO32-56
+         */
+        uint32_t int1_1:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_1_reg_t;
+
+/** Type of status_next register
+ *  GPIO interrupt source register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt source register for GPIO0-31
+         */
+        uint32_t status_interrupt_next:32;
+    };
+    uint32_t val;
+} gpio_status_next_reg_t;
+
+/** Type of status_next1 register
+ *  GPIO interrupt source register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next1 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt source register for GPIO32-56
+         */
+        uint32_t status_interrupt_next1:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status_next1_reg_t;
+
+/** Type of pin register
+ *  GPIO pin configuration register
+ */
+typedef union {
+    struct {
+        /** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
+         *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t sync2_bypass:2;
+        /** pad_driver : R/W; bitpos: [2]; default: 0;
+         *  set this bit to select pad driver. 1:open-drain. 0:normal.
+         */
+        uint32_t pad_driver:1;
+        /** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
+         *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t sync1_bypass:2;
+        uint32_t reserved_5:2;
+        /** int_type : R/W; bitpos: [9:7]; default: 0;
+         *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+         *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+         *  at high level
+         */
+        uint32_t int_type:3;
+        /** wakeup_enable : R/W; bitpos: [10]; default: 0;
+         *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+         */
+        uint32_t wakeup_enable:1;
+        /** config : R/W; bitpos: [12:11]; default: 0;
+         *  reserved
+         */
+        uint32_t config:2;
+        /** int_ena : R/W; bitpos: [17:13]; default: 0;
+         *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+         *  interrupt.
+         */
+        uint32_t int_ena:5;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gpio_pin_reg_t;
+
+/** Type of func_in_sel_cfg register
+ *  GPIO input function configuration register
+ */
+typedef union {
+    struct {
+        /** in_sel : R/W; bitpos: [5:0]; default: 63;
+         *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+         *  high level. s=0x3E: set this port always low level.
+         */
+        uint32_t in_sel:6;
+        /** in_inv_sel : R/W; bitpos: [6]; default: 0;
+         *  set this bit to invert input signal. 1:invert. 0:not invert.
+         */
+        uint32_t in_inv_sel:1;
+        /** sig_in_sel : R/W; bitpos: [7]; default: 0;
+         *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+         */
+        uint32_t sig_in_sel:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_func_in_sel_cfg_reg_t;
+
+/** Type of func_out_sel_cfg register
+ *  GPIO output function select register
+ */
+typedef union {
+    struct {
+        /** out_sel : R/W/SC; bitpos: [8:0]; default: 256;
+         *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+         *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+         *  GPIO_OUT_REG[n].
+         */
+        uint32_t out_sel:9;
+        /** out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
+         *  set this bit to invert output signal.1:invert.0:not invert.
+         */
+        uint32_t out_inv_sel:1;
+        /** oen_sel : R/W; bitpos: [10]; default: 0;
+         *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+         *  enable signal.0:use peripheral output enable signal.
+         */
+        uint32_t oen_sel:1;
+        /** oen_inv_sel : R/W; bitpos: [11]; default: 0;
+         *  set this bit to invert output enable signal.1:invert.0:not invert.
+         */
+        uint32_t oen_inv_sel:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} gpio_func_out_sel_cfg_reg_t;
+
+/** Type of intr_2 register
+ *  GPIO interrupt 2 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_2 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 2 status register for GPIO0-31
+         */
+        uint32_t int_2:32;
+    };
+    uint32_t val;
+} gpio_intr_2_reg_t;
+
+/** Type of intr1_2 register
+ *  GPIO interrupt 2 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_2 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 2 status register for GPIO32-56
+         */
+        uint32_t int1_2:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_2_reg_t;
+
+/** Type of intr_3 register
+ *  GPIO interrupt 3 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_3 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 3 status register for GPIO0-31
+         */
+        uint32_t int_3:32;
+    };
+    uint32_t val;
+} gpio_intr_3_reg_t;
+
+/** Type of intr1_3 register
+ *  GPIO interrupt 3 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_3 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 3 status register for GPIO32-56
+         */
+        uint32_t int1_3:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_3_reg_t;
+
+/** Type of clock_gate register
+ *  GPIO clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  set this bit to enable GPIO clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} gpio_clock_gate_reg_t;
+
+/** Type of zero_det_filter_cnt register
+ *  GPIO analog comparator zero detect filter count
+ */
+typedef union {
+    struct {
+        /** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GPIO analog comparator zero detect filter count
+         */
+        uint32_t zero_det_filter_cnt:32;
+    };
+    uint32_t val;
+} gpio_zero_det_filter_cnt_reg_t;
+
+/** Type of send_seq register
+ *  High speed sdio pad bist send sequence
+ */
+typedef union {
+    struct {
+        /** send_seq : R/W; bitpos: [31:0]; default: 305419896;
+         *  High speed sdio pad bist send sequence
+         */
+        uint32_t send_seq:32;
+    };
+    uint32_t val;
+} gpio_send_seq_reg_t;
+
+/** Type of recive_seq register
+ *  High speed sdio pad bist receive sequence
+ */
+typedef union {
+    struct {
+        /** recive_seq : RO; bitpos: [31:0]; default: 0;
+         *  High speed sdio pad bist receive sequence
+         */
+        uint32_t recive_seq:32;
+    };
+    uint32_t val;
+} gpio_recive_seq_reg_t;
+
+/** Type of bistin_sel register
+ *  High speed sdio pad bist in pad sel
+ */
+typedef union {
+    struct {
+        /** bistin_sel : R/W; bitpos: [3:0]; default: 15;
+         *  High speed sdio pad bist in pad sel 0:pad39, 1: pad40...
+         */
+        uint32_t bistin_sel:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} gpio_bistin_sel_reg_t;
+
+/** Type of bist_ctrl register
+ *  High speed sdio pad bist control
+ */
+typedef union {
+    struct {
+        /** bist_pad_oe : R/W; bitpos: [0]; default: 1;
+         *  High speed sdio pad bist out pad oe
+         */
+        uint32_t bist_pad_oe:1;
+        /** bist_start : WT; bitpos: [1]; default: 0;
+         *  High speed sdio pad bist start
+         */
+        uint32_t bist_start:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} gpio_bist_ctrl_reg_t;
+
+/** Type of date register
+ *  GPIO version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2294787;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpio_date_reg_t;
+
+
+/** Group: GPIO INT RAW REG */
+/** Type of int_raw register
+ *  analog comparator interrupt raw
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  analog comparator pos edge interrupt raw
+         */
+        uint32_t comp0_neg_int_raw:1;
+        /** comp0_pos_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  analog comparator neg edge interrupt raw
+         */
+        uint32_t comp0_pos_int_raw:1;
+        /** comp0_all_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  analog comparator neg or pos edge interrupt raw
+         */
+        uint32_t comp0_all_int_raw:1;
+        /** comp1_neg_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  analog comparator pos edge interrupt raw
+         */
+        uint32_t comp1_neg_int_raw:1;
+        /** comp1_pos_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  analog comparator neg edge interrupt raw
+         */
+        uint32_t comp1_pos_int_raw:1;
+        /** comp1_all_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  analog comparator neg or pos edge interrupt raw
+         */
+        uint32_t comp1_all_int_raw:1;
+        /** bistok_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  pad bistok interrupt raw
+         */
+        uint32_t bistok_int_raw:1;
+        /** bistfail_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  pad bistfail interrupt raw
+         */
+        uint32_t bistfail_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_raw_reg_t;
+
+
+/** Group: GPIO INT ST REG */
+/** Type of int_st register
+ *  analog comparator interrupt status
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_st : RO; bitpos: [0]; default: 0;
+         *  analog comparator pos edge interrupt status
+         */
+        uint32_t comp0_neg_int_st:1;
+        /** comp0_pos_int_st : RO; bitpos: [1]; default: 0;
+         *  analog comparator neg edge interrupt status
+         */
+        uint32_t comp0_pos_int_st:1;
+        /** comp0_all_int_st : RO; bitpos: [2]; default: 0;
+         *  analog comparator neg or pos edge interrupt status
+         */
+        uint32_t comp0_all_int_st:1;
+        /** comp1_neg_int_st : RO; bitpos: [3]; default: 0;
+         *  analog comparator pos edge interrupt status
+         */
+        uint32_t comp1_neg_int_st:1;
+        /** comp1_pos_int_st : RO; bitpos: [4]; default: 0;
+         *  analog comparator neg edge interrupt status
+         */
+        uint32_t comp1_pos_int_st:1;
+        /** comp1_all_int_st : RO; bitpos: [5]; default: 0;
+         *  analog comparator neg or pos edge interrupt status
+         */
+        uint32_t comp1_all_int_st:1;
+        /** bistok_int_st : RO; bitpos: [6]; default: 0;
+         *  pad bistok interrupt status
+         */
+        uint32_t bistok_int_st:1;
+        /** bistfail_int_st : RO; bitpos: [7]; default: 0;
+         *  pad bistfail interrupt status
+         */
+        uint32_t bistfail_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_st_reg_t;
+
+
+/** Group: GPIO INT ENA REG */
+/** Type of int_ena register
+ *  analog comparator interrupt enable
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_ena : R/W; bitpos: [0]; default: 1;
+         *  analog comparator pos edge interrupt enable
+         */
+        uint32_t comp0_neg_int_ena:1;
+        /** comp0_pos_int_ena : R/W; bitpos: [1]; default: 1;
+         *  analog comparator neg edge interrupt enable
+         */
+        uint32_t comp0_pos_int_ena:1;
+        /** comp0_all_int_ena : R/W; bitpos: [2]; default: 1;
+         *  analog comparator neg or pos edge interrupt enable
+         */
+        uint32_t comp0_all_int_ena:1;
+        /** comp1_neg_int_ena : R/W; bitpos: [3]; default: 1;
+         *  analog comparator pos edge interrupt enable
+         */
+        uint32_t comp1_neg_int_ena:1;
+        /** comp1_pos_int_ena : R/W; bitpos: [4]; default: 1;
+         *  analog comparator neg edge interrupt enable
+         */
+        uint32_t comp1_pos_int_ena:1;
+        /** comp1_all_int_ena : R/W; bitpos: [5]; default: 1;
+         *  analog comparator neg or pos edge interrupt enable
+         */
+        uint32_t comp1_all_int_ena:1;
+        /** bistok_int_ena : R/W; bitpos: [6]; default: 1;
+         *  pad bistok interrupt enable
+         */
+        uint32_t bistok_int_ena:1;
+        /** bistfail_int_ena : R/W; bitpos: [7]; default: 1;
+         *  pad bistfail interrupt enable
+         */
+        uint32_t bistfail_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_ena_reg_t;
+
+
+/** Group: GPIO INT CLR REG */
+/** Type of int_clr register
+ *  analog comparator interrupt clear
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_clr : WT; bitpos: [0]; default: 0;
+         *  analog comparator pos edge interrupt clear
+         */
+        uint32_t comp0_neg_int_clr:1;
+        /** comp0_pos_int_clr : WT; bitpos: [1]; default: 0;
+         *  analog comparator neg edge interrupt clear
+         */
+        uint32_t comp0_pos_int_clr:1;
+        /** comp0_all_int_clr : WT; bitpos: [2]; default: 0;
+         *  analog comparator neg or pos edge interrupt clear
+         */
+        uint32_t comp0_all_int_clr:1;
+        /** comp1_neg_int_clr : WT; bitpos: [3]; default: 0;
+         *  analog comparator pos edge interrupt clear
+         */
+        uint32_t comp1_neg_int_clr:1;
+        /** comp1_pos_int_clr : WT; bitpos: [4]; default: 0;
+         *  analog comparator neg edge interrupt clear
+         */
+        uint32_t comp1_pos_int_clr:1;
+        /** comp1_all_int_clr : WT; bitpos: [5]; default: 0;
+         *  analog comparator neg or pos edge interrupt clear
+         */
+        uint32_t comp1_all_int_clr:1;
+        /** bistok_int_clr : WT; bitpos: [6]; default: 0;
+         *  pad bistok interrupt enable
+         */
+        uint32_t bistok_int_clr:1;
+        /** bistfail_int_clr : WT; bitpos: [7]; default: 0;
+         *  pad bistfail interrupt enable
+         */
+        uint32_t bistfail_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_clr_reg_t;
+
+
+typedef struct gpio_dev_t {
+    volatile gpio_bt_select_reg_t bt_select;
+    volatile gpio_out_reg_t out;
+    volatile gpio_out_w1ts_reg_t out_w1ts;
+    volatile gpio_out_w1tc_reg_t out_w1tc;
+    volatile gpio_out1_reg_t out1;
+    volatile gpio_out1_w1ts_reg_t out1_w1ts;
+    volatile gpio_out1_w1tc_reg_t out1_w1tc;
+    uint32_t reserved_01c;
+    volatile gpio_enable_reg_t enable;
+    volatile gpio_enable_w1ts_reg_t enable_w1ts;
+    volatile gpio_enable_w1tc_reg_t enable_w1tc;
+    volatile gpio_enable1_reg_t enable1;
+    volatile gpio_enable1_w1ts_reg_t enable1_w1ts;
+    volatile gpio_enable1_w1tc_reg_t enable1_w1tc;
+    volatile gpio_strap_reg_t strap;
+    volatile gpio_in_reg_t in;
+    volatile gpio_in1_reg_t in1;
+    volatile gpio_status_reg_t status;
+    volatile gpio_status_w1ts_reg_t status_w1ts;
+    volatile gpio_status_w1tc_reg_t status_w1tc;
+    volatile gpio_status1_reg_t status1;
+    volatile gpio_status1_w1ts_reg_t status1_w1ts;
+    volatile gpio_status1_w1tc_reg_t status1_w1tc;
+    volatile gpio_intr_0_reg_t intr_0;
+    volatile gpio_intr1_0_reg_t intr1_0;
+    volatile gpio_intr_1_reg_t intr_1;
+    volatile gpio_intr1_1_reg_t intr1_1;
+    volatile gpio_status_next_reg_t status_next;
+    volatile gpio_status_next1_reg_t status_next1;
+    volatile gpio_pin_reg_t pin[57];
+    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; /* func0-func255: reserved for func0, 46, 67, 72, 73, 79, 81, 82, 84, 85, 87, 88, 115, 116, 119-125, 157, 204-213 */
+    volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[57];
+    volatile gpio_intr_2_reg_t intr_2;
+    volatile gpio_intr1_2_reg_t intr1_2;
+    volatile gpio_intr_3_reg_t intr_3;
+    volatile gpio_intr1_3_reg_t intr1_3;
+    volatile gpio_clock_gate_reg_t clock_gate;
+    uint32_t reserved_650[44];
+    volatile gpio_int_raw_reg_t int_raw;
+    volatile gpio_int_st_reg_t int_st;
+    volatile gpio_int_ena_reg_t int_ena;
+    volatile gpio_int_clr_reg_t int_clr;
+    volatile gpio_zero_det_filter_cnt_reg_t zero_det_filter_cnt[2];
+    volatile gpio_send_seq_reg_t send_seq;
+    volatile gpio_recive_seq_reg_t recive_seq;
+    volatile gpio_bistin_sel_reg_t bistin_sel;
+    volatile gpio_bist_ctrl_reg_t bist_ctrl;
+    uint32_t reserved_728[53];
+    volatile gpio_date_reg_t date;
+} gpio_dev_t;
+
+extern gpio_dev_t GPIO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_dev_t) == 0x800, "Invalid size of gpio_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/h264_dma_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/h264_dma_reg.h
new file mode 100644
index 0000000000..722c24a9c7
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/h264_dma_reg.h
@@ -0,0 +1,8118 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** H264_DMA_OUT_CONF0_CH0_REG register
+ *  TX CH0 config0 register
+ */
+#define H264_DMA_OUT_CONF0_CH0_REG (DR_REG_H264_DMA_BASE + 0x0)
+/** H264_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define H264_DMA_OUT_AUTO_WRBACK_CH0    (BIT(0))
+#define H264_DMA_OUT_AUTO_WRBACK_CH0_M  (H264_DMA_OUT_AUTO_WRBACK_CH0_V << H264_DMA_OUT_AUTO_WRBACK_CH0_S)
+#define H264_DMA_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define H264_DMA_OUT_AUTO_WRBACK_CH0_S  0
+/** H264_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define H264_DMA_OUT_EOF_MODE_CH0    (BIT(1))
+#define H264_DMA_OUT_EOF_MODE_CH0_M  (H264_DMA_OUT_EOF_MODE_CH0_V << H264_DMA_OUT_EOF_MODE_CH0_S)
+#define H264_DMA_OUT_EOF_MODE_CH0_V  0x00000001U
+#define H264_DMA_OUT_EOF_MODE_CH0_S  1
+/** H264_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define H264_DMA_OUTDSCR_BURST_EN_CH0    (BIT(2))
+#define H264_DMA_OUTDSCR_BURST_EN_CH0_M  (H264_DMA_OUTDSCR_BURST_EN_CH0_V << H264_DMA_OUTDSCR_BURST_EN_CH0_S)
+#define H264_DMA_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define H264_DMA_OUTDSCR_BURST_EN_CH0_S  2
+/** H264_DMA_OUT_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_OUT_ECC_AES_EN_CH0    (BIT(3))
+#define H264_DMA_OUT_ECC_AES_EN_CH0_M  (H264_DMA_OUT_ECC_AES_EN_CH0_V << H264_DMA_OUT_ECC_AES_EN_CH0_S)
+#define H264_DMA_OUT_ECC_AES_EN_CH0_V  0x00000001U
+#define H264_DMA_OUT_ECC_AES_EN_CH0_S  3
+/** H264_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_OUT_CHECK_OWNER_CH0    (BIT(4))
+#define H264_DMA_OUT_CHECK_OWNER_CH0_M  (H264_DMA_OUT_CHECK_OWNER_CH0_V << H264_DMA_OUT_CHECK_OWNER_CH0_S)
+#define H264_DMA_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define H264_DMA_OUT_CHECK_OWNER_CH0_S  4
+/** H264_DMA_OUT_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH0    0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH0_M  (H264_DMA_OUT_MEM_BURST_LENGTH_CH0_V << H264_DMA_OUT_MEM_BURST_LENGTH_CH0_S)
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH0_S  6
+/** H264_DMA_OUT_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH0    (BIT(12))
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH0_M  (H264_DMA_OUT_PAGE_BOUND_EN_CH0_V << H264_DMA_OUT_PAGE_BOUND_EN_CH0_S)
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH0_S  12
+/** H264_DMA_OUT_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define H264_DMA_OUT_REORDER_EN_CH0    (BIT(16))
+#define H264_DMA_OUT_REORDER_EN_CH0_M  (H264_DMA_OUT_REORDER_EN_CH0_V << H264_DMA_OUT_REORDER_EN_CH0_S)
+#define H264_DMA_OUT_REORDER_EN_CH0_V  0x00000001U
+#define H264_DMA_OUT_REORDER_EN_CH0_S  16
+/** H264_DMA_OUT_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define H264_DMA_OUT_RST_CH0    (BIT(24))
+#define H264_DMA_OUT_RST_CH0_M  (H264_DMA_OUT_RST_CH0_V << H264_DMA_OUT_RST_CH0_S)
+#define H264_DMA_OUT_RST_CH0_V  0x00000001U
+#define H264_DMA_OUT_RST_CH0_S  24
+/** H264_DMA_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_OUT_CMD_DISABLE_CH0    (BIT(25))
+#define H264_DMA_OUT_CMD_DISABLE_CH0_M  (H264_DMA_OUT_CMD_DISABLE_CH0_V << H264_DMA_OUT_CMD_DISABLE_CH0_S)
+#define H264_DMA_OUT_CMD_DISABLE_CH0_V  0x00000001U
+#define H264_DMA_OUT_CMD_DISABLE_CH0_S  25
+/** H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0_M  (H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0_V << H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** H264_DMA_OUT_INT_RAW_CH0_REG register
+ *  TX CH0  interrupt raw register
+ */
+#define H264_DMA_OUT_INT_RAW_CH0_REG (DR_REG_H264_DMA_BASE + 0x4)
+/** H264_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define H264_DMA_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define H264_DMA_OUT_DONE_CH0_INT_RAW_M  (H264_DMA_OUT_DONE_CH0_INT_RAW_V << H264_DMA_OUT_DONE_CH0_INT_RAW_S)
+#define H264_DMA_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH0_INT_RAW_S  0
+/** H264_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define H264_DMA_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define H264_DMA_OUT_EOF_CH0_INT_RAW_M  (H264_DMA_OUT_EOF_CH0_INT_RAW_V << H264_DMA_OUT_EOF_CH0_INT_RAW_S)
+#define H264_DMA_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH0_INT_RAW_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V << H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S  8
+
+/** H264_DMA_OUT_INT_ENA_CH0_REG register
+ *  TX CH0  interrupt ena register
+ */
+#define H264_DMA_OUT_INT_ENA_CH0_REG (DR_REG_H264_DMA_BASE + 0x8)
+/** H264_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define H264_DMA_OUT_DONE_CH0_INT_ENA_M  (H264_DMA_OUT_DONE_CH0_INT_ENA_V << H264_DMA_OUT_DONE_CH0_INT_ENA_S)
+#define H264_DMA_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH0_INT_ENA_S  0
+/** H264_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define H264_DMA_OUT_EOF_CH0_INT_ENA_M  (H264_DMA_OUT_EOF_CH0_INT_ENA_V << H264_DMA_OUT_EOF_CH0_INT_ENA_S)
+#define H264_DMA_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH0_INT_ENA_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V << H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S  8
+
+/** H264_DMA_OUT_INT_ST_CH0_REG register
+ *  TX CH0  interrupt st register
+ */
+#define H264_DMA_OUT_INT_ST_CH0_REG (DR_REG_H264_DMA_BASE + 0xc)
+/** H264_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define H264_DMA_OUT_DONE_CH0_INT_ST_M  (H264_DMA_OUT_DONE_CH0_INT_ST_V << H264_DMA_OUT_DONE_CH0_INT_ST_S)
+#define H264_DMA_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH0_INT_ST_S  0
+/** H264_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define H264_DMA_OUT_EOF_CH0_INT_ST_M  (H264_DMA_OUT_EOF_CH0_INT_ST_V << H264_DMA_OUT_EOF_CH0_INT_ST_S)
+#define H264_DMA_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH0_INT_ST_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ST_M  (H264_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << H264_DMA_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST_V << H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST_V << H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST_V << H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST_V << H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST_V << H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST_S  8
+
+/** H264_DMA_OUT_INT_CLR_CH0_REG register
+ *  TX CH0  interrupt clr register
+ */
+#define H264_DMA_OUT_INT_CLR_CH0_REG (DR_REG_H264_DMA_BASE + 0x10)
+/** H264_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define H264_DMA_OUT_DONE_CH0_INT_CLR_M  (H264_DMA_OUT_DONE_CH0_INT_CLR_V << H264_DMA_OUT_DONE_CH0_INT_CLR_S)
+#define H264_DMA_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH0_INT_CLR_S  0
+/** H264_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define H264_DMA_OUT_EOF_CH0_INT_CLR_M  (H264_DMA_OUT_EOF_CH0_INT_CLR_V << H264_DMA_OUT_EOF_CH0_INT_CLR_S)
+#define H264_DMA_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH0_INT_CLR_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V << H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S  8
+
+/** H264_DMA_OUTFIFO_STATUS_CH0_REG register
+ *  TX CH0 outfifo status register
+ */
+#define H264_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_H264_DMA_BASE + 0x14)
+/** H264_DMA_OUTFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_FULL_L2_CH0    (BIT(0))
+#define H264_DMA_OUTFIFO_FULL_L2_CH0_M  (H264_DMA_OUTFIFO_FULL_L2_CH0_V << H264_DMA_OUTFIFO_FULL_L2_CH0_S)
+#define H264_DMA_OUTFIFO_FULL_L2_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L2_CH0_S  0
+/** H264_DMA_OUTFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH0    (BIT(1))
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH0_M  (H264_DMA_OUTFIFO_EMPTY_L2_CH0_V << H264_DMA_OUTFIFO_EMPTY_L2_CH0_S)
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH0_S  1
+/** H264_DMA_OUTFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_CNT_L2_CH0    0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH0_M  (H264_DMA_OUTFIFO_CNT_L2_CH0_V << H264_DMA_OUTFIFO_CNT_L2_CH0_S)
+#define H264_DMA_OUTFIFO_CNT_L2_CH0_V  0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH0_S  2
+/** H264_DMA_OUTFIFO_FULL_L1_CH0 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_FULL_L1_CH0    (BIT(6))
+#define H264_DMA_OUTFIFO_FULL_L1_CH0_M  (H264_DMA_OUTFIFO_FULL_L1_CH0_V << H264_DMA_OUTFIFO_FULL_L1_CH0_S)
+#define H264_DMA_OUTFIFO_FULL_L1_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L1_CH0_S  6
+/** H264_DMA_OUTFIFO_EMPTY_L1_CH0 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH0    (BIT(7))
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH0_M  (H264_DMA_OUTFIFO_EMPTY_L1_CH0_V << H264_DMA_OUTFIFO_EMPTY_L1_CH0_S)
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH0_S  7
+/** H264_DMA_OUTFIFO_CNT_L1_CH0 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_CNT_L1_CH0    0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH0_M  (H264_DMA_OUTFIFO_CNT_L1_CH0_V << H264_DMA_OUTFIFO_CNT_L1_CH0_S)
+#define H264_DMA_OUTFIFO_CNT_L1_CH0_V  0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH0_S  8
+/** H264_DMA_OUTFIFO_FULL_L3_CH0 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_FULL_L3_CH0    (BIT(16))
+#define H264_DMA_OUTFIFO_FULL_L3_CH0_M  (H264_DMA_OUTFIFO_FULL_L3_CH0_V << H264_DMA_OUTFIFO_FULL_L3_CH0_S)
+#define H264_DMA_OUTFIFO_FULL_L3_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L3_CH0_S  16
+/** H264_DMA_OUTFIFO_EMPTY_L3_CH0 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH0    (BIT(17))
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH0_M  (H264_DMA_OUTFIFO_EMPTY_L3_CH0_V << H264_DMA_OUTFIFO_EMPTY_L3_CH0_S)
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH0_S  17
+/** H264_DMA_OUTFIFO_CNT_L3_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_CNT_L3_CH0    0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH0_M  (H264_DMA_OUTFIFO_CNT_L3_CH0_V << H264_DMA_OUTFIFO_CNT_L3_CH0_S)
+#define H264_DMA_OUTFIFO_CNT_L3_CH0_V  0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH0_S  18
+
+/** H264_DMA_OUT_PUSH_CH0_REG register
+ *  TX CH0 outfifo push register
+ */
+#define H264_DMA_OUT_PUSH_CH0_REG (DR_REG_H264_DMA_BASE + 0x18)
+/** H264_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_WDATA_CH0    0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH0_M  (H264_DMA_OUTFIFO_WDATA_CH0_V << H264_DMA_OUTFIFO_WDATA_CH0_S)
+#define H264_DMA_OUTFIFO_WDATA_CH0_V  0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH0_S  0
+/** H264_DMA_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_PUSH_CH0    (BIT(10))
+#define H264_DMA_OUTFIFO_PUSH_CH0_M  (H264_DMA_OUTFIFO_PUSH_CH0_V << H264_DMA_OUTFIFO_PUSH_CH0_S)
+#define H264_DMA_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_PUSH_CH0_S  10
+
+/** H264_DMA_OUT_LINK_CONF_CH0_REG register
+ *  TX CH0 out_link dscr ctrl register
+ */
+#define H264_DMA_OUT_LINK_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x1c)
+/** H264_DMA_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_STOP_CH0    (BIT(20))
+#define H264_DMA_OUTLINK_STOP_CH0_M  (H264_DMA_OUTLINK_STOP_CH0_V << H264_DMA_OUTLINK_STOP_CH0_S)
+#define H264_DMA_OUTLINK_STOP_CH0_V  0x00000001U
+#define H264_DMA_OUTLINK_STOP_CH0_S  20
+/** H264_DMA_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_START_CH0    (BIT(21))
+#define H264_DMA_OUTLINK_START_CH0_M  (H264_DMA_OUTLINK_START_CH0_V << H264_DMA_OUTLINK_START_CH0_S)
+#define H264_DMA_OUTLINK_START_CH0_V  0x00000001U
+#define H264_DMA_OUTLINK_START_CH0_S  21
+/** H264_DMA_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define H264_DMA_OUTLINK_RESTART_CH0    (BIT(22))
+#define H264_DMA_OUTLINK_RESTART_CH0_M  (H264_DMA_OUTLINK_RESTART_CH0_V << H264_DMA_OUTLINK_RESTART_CH0_S)
+#define H264_DMA_OUTLINK_RESTART_CH0_V  0x00000001U
+#define H264_DMA_OUTLINK_RESTART_CH0_S  22
+/** H264_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define H264_DMA_OUTLINK_PARK_CH0    (BIT(23))
+#define H264_DMA_OUTLINK_PARK_CH0_M  (H264_DMA_OUTLINK_PARK_CH0_V << H264_DMA_OUTLINK_PARK_CH0_S)
+#define H264_DMA_OUTLINK_PARK_CH0_V  0x00000001U
+#define H264_DMA_OUTLINK_PARK_CH0_S  23
+
+/** H264_DMA_OUT_LINK_ADDR_CH0_REG register
+ *  TX CH0 out_link dscr addr register
+ */
+#define H264_DMA_OUT_LINK_ADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x20)
+/** H264_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH0_M  (H264_DMA_OUTLINK_ADDR_CH0_V << H264_DMA_OUTLINK_ADDR_CH0_S)
+#define H264_DMA_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH0_S  0
+
+/** H264_DMA_OUT_STATE_CH0_REG register
+ *  TX CH0 state register
+ */
+#define H264_DMA_OUT_STATE_CH0_REG (DR_REG_H264_DMA_BASE + 0x24)
+/** H264_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH0_M  (H264_DMA_OUTLINK_DSCR_ADDR_CH0_V << H264_DMA_OUTLINK_DSCR_ADDR_CH0_S)
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH0_S  0
+/** H264_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_OUT_DSCR_STATE_CH0    0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH0_M  (H264_DMA_OUT_DSCR_STATE_CH0_V << H264_DMA_OUT_DSCR_STATE_CH0_S)
+#define H264_DMA_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH0_S  18
+/** H264_DMA_OUT_STATE_CH0 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_OUT_STATE_CH0    0x0000000FU
+#define H264_DMA_OUT_STATE_CH0_M  (H264_DMA_OUT_STATE_CH0_V << H264_DMA_OUT_STATE_CH0_S)
+#define H264_DMA_OUT_STATE_CH0_V  0x0000000FU
+#define H264_DMA_OUT_STATE_CH0_S  20
+/** H264_DMA_OUT_RESET_AVAIL_CH0 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_OUT_RESET_AVAIL_CH0    (BIT(24))
+#define H264_DMA_OUT_RESET_AVAIL_CH0_M  (H264_DMA_OUT_RESET_AVAIL_CH0_V << H264_DMA_OUT_RESET_AVAIL_CH0_S)
+#define H264_DMA_OUT_RESET_AVAIL_CH0_V  0x00000001U
+#define H264_DMA_OUT_RESET_AVAIL_CH0_S  24
+
+/** H264_DMA_OUT_EOF_DES_ADDR_CH0_REG register
+ *  TX CH0 eof des addr register
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x28)
+/** H264_DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH0_M  (H264_DMA_OUT_EOF_DES_ADDR_CH0_V << H264_DMA_OUT_EOF_DES_ADDR_CH0_S)
+#define H264_DMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** H264_DMA_OUT_DSCR_CH0_REG register
+ *  TX CH0 next dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_CH0_REG (DR_REG_H264_DMA_BASE + 0x2c)
+/** H264_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define H264_DMA_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH0_M  (H264_DMA_OUTLINK_DSCR_CH0_V << H264_DMA_OUTLINK_DSCR_CH0_S)
+#define H264_DMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH0_S  0
+
+/** H264_DMA_OUT_DSCR_BF0_CH0_REG register
+ *  TX CH0 last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_H264_DMA_BASE + 0x30)
+/** H264_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH0_M  (H264_DMA_OUTLINK_DSCR_BF0_CH0_V << H264_DMA_OUTLINK_DSCR_BF0_CH0_S)
+#define H264_DMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** H264_DMA_OUT_DSCR_BF1_CH0_REG register
+ *  TX CH0 second-to-last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_H264_DMA_BASE + 0x34)
+/** H264_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH0_M  (H264_DMA_OUTLINK_DSCR_BF1_CH0_V << H264_DMA_OUTLINK_DSCR_BF1_CH0_S)
+#define H264_DMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** H264_DMA_OUT_ARB_CH0_REG register
+ *  TX CH0 arb register
+ */
+#define H264_DMA_OUT_ARB_CH0_REG (DR_REG_H264_DMA_BASE + 0x3c)
+/** H264_DMA_OUT_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH0_M  (H264_DMA_OUT_ARB_TOKEN_NUM_CH0_V << H264_DMA_OUT_ARB_TOKEN_NUM_CH0_S)
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH0_S  0
+/** H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0    0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0_M  (H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0_V << H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0_S)
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0_V  0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0_S  4
+
+/** H264_DMA_OUT_RO_STATUS_CH0_REG register
+ *  TX CH0 reorder status register
+ */
+#define H264_DMA_OUT_RO_STATUS_CH0_REG (DR_REG_H264_DMA_BASE + 0x40)
+/** H264_DMA_OUTFIFO_RO_CNT_CH0 : RO; bitpos: [1:0]; default: 0;
+ *  The register stores the 8byte number of the data in reorder Tx FIFO for channel 0.
+ */
+#define H264_DMA_OUTFIFO_RO_CNT_CH0    0x00000003U
+#define H264_DMA_OUTFIFO_RO_CNT_CH0_M  (H264_DMA_OUTFIFO_RO_CNT_CH0_V << H264_DMA_OUTFIFO_RO_CNT_CH0_S)
+#define H264_DMA_OUTFIFO_RO_CNT_CH0_V  0x00000003U
+#define H264_DMA_OUTFIFO_RO_CNT_CH0_S  0
+/** H264_DMA_OUT_RO_WR_STATE_CH0 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define H264_DMA_OUT_RO_WR_STATE_CH0    0x00000003U
+#define H264_DMA_OUT_RO_WR_STATE_CH0_M  (H264_DMA_OUT_RO_WR_STATE_CH0_V << H264_DMA_OUT_RO_WR_STATE_CH0_S)
+#define H264_DMA_OUT_RO_WR_STATE_CH0_V  0x00000003U
+#define H264_DMA_OUT_RO_WR_STATE_CH0_S  6
+/** H264_DMA_OUT_RO_RD_STATE_CH0 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define H264_DMA_OUT_RO_RD_STATE_CH0    0x00000003U
+#define H264_DMA_OUT_RO_RD_STATE_CH0_M  (H264_DMA_OUT_RO_RD_STATE_CH0_V << H264_DMA_OUT_RO_RD_STATE_CH0_S)
+#define H264_DMA_OUT_RO_RD_STATE_CH0_V  0x00000003U
+#define H264_DMA_OUT_RO_RD_STATE_CH0_S  8
+/** H264_DMA_OUT_PIXEL_BYTE_CH0 : RO; bitpos: [13:10]; default: 2;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define H264_DMA_OUT_PIXEL_BYTE_CH0    0x0000000FU
+#define H264_DMA_OUT_PIXEL_BYTE_CH0_M  (H264_DMA_OUT_PIXEL_BYTE_CH0_V << H264_DMA_OUT_PIXEL_BYTE_CH0_S)
+#define H264_DMA_OUT_PIXEL_BYTE_CH0_V  0x0000000FU
+#define H264_DMA_OUT_PIXEL_BYTE_CH0_S  10
+/** H264_DMA_OUT_BURST_BLOCK_NUM_CH0 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define H264_DMA_OUT_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define H264_DMA_OUT_BURST_BLOCK_NUM_CH0_M  (H264_DMA_OUT_BURST_BLOCK_NUM_CH0_V << H264_DMA_OUT_BURST_BLOCK_NUM_CH0_S)
+#define H264_DMA_OUT_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define H264_DMA_OUT_BURST_BLOCK_NUM_CH0_S  14
+
+/** H264_DMA_OUT_RO_PD_CONF_CH0_REG register
+ *  TX CH0 reorder power config register
+ */
+#define H264_DMA_OUT_RO_PD_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x44)
+/** H264_DMA_OUT_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define H264_DMA_OUT_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define H264_DMA_OUT_RO_RAM_FORCE_PD_CH0_M  (H264_DMA_OUT_RO_RAM_FORCE_PD_CH0_V << H264_DMA_OUT_RO_RAM_FORCE_PD_CH0_S)
+#define H264_DMA_OUT_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define H264_DMA_OUT_RO_RAM_FORCE_PD_CH0_S  4
+/** H264_DMA_OUT_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define H264_DMA_OUT_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define H264_DMA_OUT_RO_RAM_FORCE_PU_CH0_M  (H264_DMA_OUT_RO_RAM_FORCE_PU_CH0_V << H264_DMA_OUT_RO_RAM_FORCE_PU_CH0_S)
+#define H264_DMA_OUT_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define H264_DMA_OUT_RO_RAM_FORCE_PU_CH0_S  5
+/** H264_DMA_OUT_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define H264_DMA_OUT_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define H264_DMA_OUT_RO_RAM_CLK_FO_CH0_M  (H264_DMA_OUT_RO_RAM_CLK_FO_CH0_V << H264_DMA_OUT_RO_RAM_CLK_FO_CH0_S)
+#define H264_DMA_OUT_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define H264_DMA_OUT_RO_RAM_CLK_FO_CH0_S  6
+
+/** H264_DMA_OUT_MODE_ENABLE_CH0_REG register
+ *  tx CH0 mode enable register
+ */
+#define H264_DMA_OUT_MODE_ENABLE_CH0_REG (DR_REG_H264_DMA_BASE + 0x50)
+/** H264_DMA_OUT_TEST_MODE_ENABLE_CH0 : R/W; bitpos: [0]; default: 0;
+ *  tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test
+ *  mode
+ */
+#define H264_DMA_OUT_TEST_MODE_ENABLE_CH0    (BIT(0))
+#define H264_DMA_OUT_TEST_MODE_ENABLE_CH0_M  (H264_DMA_OUT_TEST_MODE_ENABLE_CH0_V << H264_DMA_OUT_TEST_MODE_ENABLE_CH0_S)
+#define H264_DMA_OUT_TEST_MODE_ENABLE_CH0_V  0x00000001U
+#define H264_DMA_OUT_TEST_MODE_ENABLE_CH0_S  0
+
+/** H264_DMA_OUT_MODE_YUV_CH0_REG register
+ *  tx CH0 test mode yuv value register
+ */
+#define H264_DMA_OUT_MODE_YUV_CH0_REG (DR_REG_H264_DMA_BASE + 0x54)
+/** H264_DMA_OUT_TEST_Y_VALUE_CH0 : R/W; bitpos: [7:0]; default: 0;
+ *  tx CH0 test mode y value
+ */
+#define H264_DMA_OUT_TEST_Y_VALUE_CH0    0x000000FFU
+#define H264_DMA_OUT_TEST_Y_VALUE_CH0_M  (H264_DMA_OUT_TEST_Y_VALUE_CH0_V << H264_DMA_OUT_TEST_Y_VALUE_CH0_S)
+#define H264_DMA_OUT_TEST_Y_VALUE_CH0_V  0x000000FFU
+#define H264_DMA_OUT_TEST_Y_VALUE_CH0_S  0
+/** H264_DMA_OUT_TEST_U_VALUE_CH0 : R/W; bitpos: [15:8]; default: 0;
+ *  tx CH0 test mode u value
+ */
+#define H264_DMA_OUT_TEST_U_VALUE_CH0    0x000000FFU
+#define H264_DMA_OUT_TEST_U_VALUE_CH0_M  (H264_DMA_OUT_TEST_U_VALUE_CH0_V << H264_DMA_OUT_TEST_U_VALUE_CH0_S)
+#define H264_DMA_OUT_TEST_U_VALUE_CH0_V  0x000000FFU
+#define H264_DMA_OUT_TEST_U_VALUE_CH0_S  8
+/** H264_DMA_OUT_TEST_V_VALUE_CH0 : R/W; bitpos: [23:16]; default: 0;
+ *  tx CH0 test mode v value
+ */
+#define H264_DMA_OUT_TEST_V_VALUE_CH0    0x000000FFU
+#define H264_DMA_OUT_TEST_V_VALUE_CH0_M  (H264_DMA_OUT_TEST_V_VALUE_CH0_V << H264_DMA_OUT_TEST_V_VALUE_CH0_S)
+#define H264_DMA_OUT_TEST_V_VALUE_CH0_V  0x000000FFU
+#define H264_DMA_OUT_TEST_V_VALUE_CH0_S  16
+
+/** H264_DMA_OUT_ETM_CONF_CH0_REG register
+ *  TX CH0 ETM config register
+ */
+#define H264_DMA_OUT_ETM_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x68)
+/** H264_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_OUT_ETM_EN_CH0    (BIT(0))
+#define H264_DMA_OUT_ETM_EN_CH0_M  (H264_DMA_OUT_ETM_EN_CH0_V << H264_DMA_OUT_ETM_EN_CH0_S)
+#define H264_DMA_OUT_ETM_EN_CH0_V  0x00000001U
+#define H264_DMA_OUT_ETM_EN_CH0_S  0
+/** H264_DMA_OUT_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_OUT_ETM_LOOP_EN_CH0    (BIT(1))
+#define H264_DMA_OUT_ETM_LOOP_EN_CH0_M  (H264_DMA_OUT_ETM_LOOP_EN_CH0_V << H264_DMA_OUT_ETM_LOOP_EN_CH0_S)
+#define H264_DMA_OUT_ETM_LOOP_EN_CH0_V  0x00000001U
+#define H264_DMA_OUT_ETM_LOOP_EN_CH0_S  1
+/** H264_DMA_OUT_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH0    0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH0_M  (H264_DMA_OUT_DSCR_TASK_MAK_CH0_V << H264_DMA_OUT_DSCR_TASK_MAK_CH0_S)
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH0_S  2
+
+/** H264_DMA_OUT_BUF_LEN_CH0_REG register
+ *  tx CH0 buf len register
+ */
+#define H264_DMA_OUT_BUF_LEN_CH0_REG (DR_REG_H264_DMA_BASE + 0x70)
+/** H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0    0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0_M  (H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0_V << H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0_S)
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0_V  0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0_S  0
+
+/** H264_DMA_OUT_FIFO_BCNT_CH0_REG register
+ *  tx CH0 fifo byte cnt register
+ */
+#define H264_DMA_OUT_FIFO_BCNT_CH0_REG (DR_REG_H264_DMA_BASE + 0x74)
+/** H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0    0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_M  (H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_V << H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_S)
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_V  0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_S  0
+
+/** H264_DMA_OUT_PUSH_BYTECNT_CH0_REG register
+ *  tx CH0 push byte cnt register
+ */
+#define H264_DMA_OUT_PUSH_BYTECNT_CH0_REG (DR_REG_H264_DMA_BASE + 0x78)
+/** H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0 : RO; bitpos: [7:0]; default: 255;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0    0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0_M  (H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0_V << H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0_S)
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0_V  0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0_S  0
+
+/** H264_DMA_OUT_XADDR_CH0_REG register
+ *  tx CH0 xaddr register
+ */
+#define H264_DMA_OUT_XADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x7c)
+/** H264_DMA_OUT_CMDFIFO_XADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH0_M  (H264_DMA_OUT_CMDFIFO_XADDR_CH0_V << H264_DMA_OUT_CMDFIFO_XADDR_CH0_S)
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH0_S  0
+
+/** H264_DMA_OUT_CONF0_CH1_REG register
+ *  TX CH1 config0 register
+ */
+#define H264_DMA_OUT_CONF0_CH1_REG (DR_REG_H264_DMA_BASE + 0x100)
+/** H264_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define H264_DMA_OUT_AUTO_WRBACK_CH1    (BIT(0))
+#define H264_DMA_OUT_AUTO_WRBACK_CH1_M  (H264_DMA_OUT_AUTO_WRBACK_CH1_V << H264_DMA_OUT_AUTO_WRBACK_CH1_S)
+#define H264_DMA_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define H264_DMA_OUT_AUTO_WRBACK_CH1_S  0
+/** H264_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define H264_DMA_OUT_EOF_MODE_CH1    (BIT(1))
+#define H264_DMA_OUT_EOF_MODE_CH1_M  (H264_DMA_OUT_EOF_MODE_CH1_V << H264_DMA_OUT_EOF_MODE_CH1_S)
+#define H264_DMA_OUT_EOF_MODE_CH1_V  0x00000001U
+#define H264_DMA_OUT_EOF_MODE_CH1_S  1
+/** H264_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define H264_DMA_OUTDSCR_BURST_EN_CH1    (BIT(2))
+#define H264_DMA_OUTDSCR_BURST_EN_CH1_M  (H264_DMA_OUTDSCR_BURST_EN_CH1_V << H264_DMA_OUTDSCR_BURST_EN_CH1_S)
+#define H264_DMA_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define H264_DMA_OUTDSCR_BURST_EN_CH1_S  2
+/** H264_DMA_OUT_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_OUT_ECC_AES_EN_CH1    (BIT(3))
+#define H264_DMA_OUT_ECC_AES_EN_CH1_M  (H264_DMA_OUT_ECC_AES_EN_CH1_V << H264_DMA_OUT_ECC_AES_EN_CH1_S)
+#define H264_DMA_OUT_ECC_AES_EN_CH1_V  0x00000001U
+#define H264_DMA_OUT_ECC_AES_EN_CH1_S  3
+/** H264_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_OUT_CHECK_OWNER_CH1    (BIT(4))
+#define H264_DMA_OUT_CHECK_OWNER_CH1_M  (H264_DMA_OUT_CHECK_OWNER_CH1_V << H264_DMA_OUT_CHECK_OWNER_CH1_S)
+#define H264_DMA_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define H264_DMA_OUT_CHECK_OWNER_CH1_S  4
+/** H264_DMA_OUT_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 64 bytes
+ */
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH1    0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH1_M  (H264_DMA_OUT_MEM_BURST_LENGTH_CH1_V << H264_DMA_OUT_MEM_BURST_LENGTH_CH1_S)
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH1_S  6
+/** H264_DMA_OUT_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH1    (BIT(12))
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH1_M  (H264_DMA_OUT_PAGE_BOUND_EN_CH1_V << H264_DMA_OUT_PAGE_BOUND_EN_CH1_S)
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH1_S  12
+/** H264_DMA_OUT_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define H264_DMA_OUT_RST_CH1    (BIT(24))
+#define H264_DMA_OUT_RST_CH1_M  (H264_DMA_OUT_RST_CH1_V << H264_DMA_OUT_RST_CH1_S)
+#define H264_DMA_OUT_RST_CH1_V  0x00000001U
+#define H264_DMA_OUT_RST_CH1_S  24
+/** H264_DMA_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_OUT_CMD_DISABLE_CH1    (BIT(25))
+#define H264_DMA_OUT_CMD_DISABLE_CH1_M  (H264_DMA_OUT_CMD_DISABLE_CH1_V << H264_DMA_OUT_CMD_DISABLE_CH1_S)
+#define H264_DMA_OUT_CMD_DISABLE_CH1_V  0x00000001U
+#define H264_DMA_OUT_CMD_DISABLE_CH1_S  25
+/** H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1_M  (H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1_V << H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** H264_DMA_OUT_INT_RAW_CH1_REG register
+ *  TX CH1  interrupt raw register
+ */
+#define H264_DMA_OUT_INT_RAW_CH1_REG (DR_REG_H264_DMA_BASE + 0x104)
+/** H264_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define H264_DMA_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define H264_DMA_OUT_DONE_CH1_INT_RAW_M  (H264_DMA_OUT_DONE_CH1_INT_RAW_V << H264_DMA_OUT_DONE_CH1_INT_RAW_S)
+#define H264_DMA_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH1_INT_RAW_S  0
+/** H264_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define H264_DMA_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define H264_DMA_OUT_EOF_CH1_INT_RAW_M  (H264_DMA_OUT_EOF_CH1_INT_RAW_V << H264_DMA_OUT_EOF_CH1_INT_RAW_S)
+#define H264_DMA_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH1_INT_RAW_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M  (H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M  (H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V << H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S  8
+
+/** H264_DMA_OUT_INT_ENA_CH1_REG register
+ *  TX CH1  interrupt ena register
+ */
+#define H264_DMA_OUT_INT_ENA_CH1_REG (DR_REG_H264_DMA_BASE + 0x108)
+/** H264_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define H264_DMA_OUT_DONE_CH1_INT_ENA_M  (H264_DMA_OUT_DONE_CH1_INT_ENA_V << H264_DMA_OUT_DONE_CH1_INT_ENA_S)
+#define H264_DMA_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH1_INT_ENA_S  0
+/** H264_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define H264_DMA_OUT_EOF_CH1_INT_ENA_M  (H264_DMA_OUT_EOF_CH1_INT_ENA_V << H264_DMA_OUT_EOF_CH1_INT_ENA_S)
+#define H264_DMA_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH1_INT_ENA_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M  (H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M  (H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V << H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S  8
+
+/** H264_DMA_OUT_INT_ST_CH1_REG register
+ *  TX CH1  interrupt st register
+ */
+#define H264_DMA_OUT_INT_ST_CH1_REG (DR_REG_H264_DMA_BASE + 0x10c)
+/** H264_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define H264_DMA_OUT_DONE_CH1_INT_ST_M  (H264_DMA_OUT_DONE_CH1_INT_ST_V << H264_DMA_OUT_DONE_CH1_INT_ST_S)
+#define H264_DMA_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH1_INT_ST_S  0
+/** H264_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define H264_DMA_OUT_EOF_CH1_INT_ST_M  (H264_DMA_OUT_EOF_CH1_INT_ST_V << H264_DMA_OUT_EOF_CH1_INT_ST_S)
+#define H264_DMA_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH1_INT_ST_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ST_M  (H264_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << H264_DMA_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M  (H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST_V << H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST_V << H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST_V << H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST_V << H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST_V << H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST_S  8
+
+/** H264_DMA_OUT_INT_CLR_CH1_REG register
+ *  TX CH1  interrupt clr register
+ */
+#define H264_DMA_OUT_INT_CLR_CH1_REG (DR_REG_H264_DMA_BASE + 0x110)
+/** H264_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define H264_DMA_OUT_DONE_CH1_INT_CLR_M  (H264_DMA_OUT_DONE_CH1_INT_CLR_V << H264_DMA_OUT_DONE_CH1_INT_CLR_S)
+#define H264_DMA_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH1_INT_CLR_S  0
+/** H264_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define H264_DMA_OUT_EOF_CH1_INT_CLR_M  (H264_DMA_OUT_EOF_CH1_INT_CLR_V << H264_DMA_OUT_EOF_CH1_INT_CLR_S)
+#define H264_DMA_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH1_INT_CLR_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M  (H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M  (H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V << H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S  8
+
+/** H264_DMA_OUTFIFO_STATUS_CH1_REG register
+ *  TX CH1 outfifo status register
+ */
+#define H264_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_H264_DMA_BASE + 0x114)
+/** H264_DMA_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_FULL_L2_CH1    (BIT(0))
+#define H264_DMA_OUTFIFO_FULL_L2_CH1_M  (H264_DMA_OUTFIFO_FULL_L2_CH1_V << H264_DMA_OUTFIFO_FULL_L2_CH1_S)
+#define H264_DMA_OUTFIFO_FULL_L2_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L2_CH1_S  0
+/** H264_DMA_OUTFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH1    (BIT(1))
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH1_M  (H264_DMA_OUTFIFO_EMPTY_L2_CH1_V << H264_DMA_OUTFIFO_EMPTY_L2_CH1_S)
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH1_S  1
+/** H264_DMA_OUTFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_CNT_L2_CH1    0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH1_M  (H264_DMA_OUTFIFO_CNT_L2_CH1_V << H264_DMA_OUTFIFO_CNT_L2_CH1_S)
+#define H264_DMA_OUTFIFO_CNT_L2_CH1_V  0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH1_S  2
+/** H264_DMA_OUTFIFO_FULL_L1_CH1 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_FULL_L1_CH1    (BIT(6))
+#define H264_DMA_OUTFIFO_FULL_L1_CH1_M  (H264_DMA_OUTFIFO_FULL_L1_CH1_V << H264_DMA_OUTFIFO_FULL_L1_CH1_S)
+#define H264_DMA_OUTFIFO_FULL_L1_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L1_CH1_S  6
+/** H264_DMA_OUTFIFO_EMPTY_L1_CH1 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH1    (BIT(7))
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH1_M  (H264_DMA_OUTFIFO_EMPTY_L1_CH1_V << H264_DMA_OUTFIFO_EMPTY_L1_CH1_S)
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH1_S  7
+/** H264_DMA_OUTFIFO_CNT_L1_CH1 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_CNT_L1_CH1    0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH1_M  (H264_DMA_OUTFIFO_CNT_L1_CH1_V << H264_DMA_OUTFIFO_CNT_L1_CH1_S)
+#define H264_DMA_OUTFIFO_CNT_L1_CH1_V  0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH1_S  8
+/** H264_DMA_OUTFIFO_FULL_L3_CH1 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_FULL_L3_CH1    (BIT(16))
+#define H264_DMA_OUTFIFO_FULL_L3_CH1_M  (H264_DMA_OUTFIFO_FULL_L3_CH1_V << H264_DMA_OUTFIFO_FULL_L3_CH1_S)
+#define H264_DMA_OUTFIFO_FULL_L3_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L3_CH1_S  16
+/** H264_DMA_OUTFIFO_EMPTY_L3_CH1 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH1    (BIT(17))
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH1_M  (H264_DMA_OUTFIFO_EMPTY_L3_CH1_V << H264_DMA_OUTFIFO_EMPTY_L3_CH1_S)
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH1_S  17
+/** H264_DMA_OUTFIFO_CNT_L3_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_CNT_L3_CH1    0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH1_M  (H264_DMA_OUTFIFO_CNT_L3_CH1_V << H264_DMA_OUTFIFO_CNT_L3_CH1_S)
+#define H264_DMA_OUTFIFO_CNT_L3_CH1_V  0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH1_S  18
+
+/** H264_DMA_OUT_PUSH_CH1_REG register
+ *  TX CH1 outfifo push register
+ */
+#define H264_DMA_OUT_PUSH_CH1_REG (DR_REG_H264_DMA_BASE + 0x118)
+/** H264_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_WDATA_CH1    0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH1_M  (H264_DMA_OUTFIFO_WDATA_CH1_V << H264_DMA_OUTFIFO_WDATA_CH1_S)
+#define H264_DMA_OUTFIFO_WDATA_CH1_V  0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH1_S  0
+/** H264_DMA_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_PUSH_CH1    (BIT(10))
+#define H264_DMA_OUTFIFO_PUSH_CH1_M  (H264_DMA_OUTFIFO_PUSH_CH1_V << H264_DMA_OUTFIFO_PUSH_CH1_S)
+#define H264_DMA_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_PUSH_CH1_S  10
+
+/** H264_DMA_OUT_LINK_CONF_CH1_REG register
+ *  TX CH1 out_link dscr ctrl register
+ */
+#define H264_DMA_OUT_LINK_CONF_CH1_REG (DR_REG_H264_DMA_BASE + 0x11c)
+/** H264_DMA_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_STOP_CH1    (BIT(20))
+#define H264_DMA_OUTLINK_STOP_CH1_M  (H264_DMA_OUTLINK_STOP_CH1_V << H264_DMA_OUTLINK_STOP_CH1_S)
+#define H264_DMA_OUTLINK_STOP_CH1_V  0x00000001U
+#define H264_DMA_OUTLINK_STOP_CH1_S  20
+/** H264_DMA_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_START_CH1    (BIT(21))
+#define H264_DMA_OUTLINK_START_CH1_M  (H264_DMA_OUTLINK_START_CH1_V << H264_DMA_OUTLINK_START_CH1_S)
+#define H264_DMA_OUTLINK_START_CH1_V  0x00000001U
+#define H264_DMA_OUTLINK_START_CH1_S  21
+/** H264_DMA_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define H264_DMA_OUTLINK_RESTART_CH1    (BIT(22))
+#define H264_DMA_OUTLINK_RESTART_CH1_M  (H264_DMA_OUTLINK_RESTART_CH1_V << H264_DMA_OUTLINK_RESTART_CH1_S)
+#define H264_DMA_OUTLINK_RESTART_CH1_V  0x00000001U
+#define H264_DMA_OUTLINK_RESTART_CH1_S  22
+/** H264_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define H264_DMA_OUTLINK_PARK_CH1    (BIT(23))
+#define H264_DMA_OUTLINK_PARK_CH1_M  (H264_DMA_OUTLINK_PARK_CH1_V << H264_DMA_OUTLINK_PARK_CH1_S)
+#define H264_DMA_OUTLINK_PARK_CH1_V  0x00000001U
+#define H264_DMA_OUTLINK_PARK_CH1_S  23
+
+/** H264_DMA_OUT_LINK_ADDR_CH1_REG register
+ *  TX CH1 out_link dscr addr register
+ */
+#define H264_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x120)
+/** H264_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH1_M  (H264_DMA_OUTLINK_ADDR_CH1_V << H264_DMA_OUTLINK_ADDR_CH1_S)
+#define H264_DMA_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH1_S  0
+
+/** H264_DMA_OUT_STATE_CH1_REG register
+ *  TX CH1 state register
+ */
+#define H264_DMA_OUT_STATE_CH1_REG (DR_REG_H264_DMA_BASE + 0x124)
+/** H264_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH1_M  (H264_DMA_OUTLINK_DSCR_ADDR_CH1_V << H264_DMA_OUTLINK_DSCR_ADDR_CH1_S)
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH1_S  0
+/** H264_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_OUT_DSCR_STATE_CH1    0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH1_M  (H264_DMA_OUT_DSCR_STATE_CH1_V << H264_DMA_OUT_DSCR_STATE_CH1_S)
+#define H264_DMA_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH1_S  18
+/** H264_DMA_OUT_STATE_CH1 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_OUT_STATE_CH1    0x0000000FU
+#define H264_DMA_OUT_STATE_CH1_M  (H264_DMA_OUT_STATE_CH1_V << H264_DMA_OUT_STATE_CH1_S)
+#define H264_DMA_OUT_STATE_CH1_V  0x0000000FU
+#define H264_DMA_OUT_STATE_CH1_S  20
+/** H264_DMA_OUT_RESET_AVAIL_CH1 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_OUT_RESET_AVAIL_CH1    (BIT(24))
+#define H264_DMA_OUT_RESET_AVAIL_CH1_M  (H264_DMA_OUT_RESET_AVAIL_CH1_V << H264_DMA_OUT_RESET_AVAIL_CH1_S)
+#define H264_DMA_OUT_RESET_AVAIL_CH1_V  0x00000001U
+#define H264_DMA_OUT_RESET_AVAIL_CH1_S  24
+
+/** H264_DMA_OUT_EOF_DES_ADDR_CH1_REG register
+ *  TX CH1 eof des addr register
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x128)
+/** H264_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH1_M  (H264_DMA_OUT_EOF_DES_ADDR_CH1_V << H264_DMA_OUT_EOF_DES_ADDR_CH1_S)
+#define H264_DMA_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** H264_DMA_OUT_DSCR_CH1_REG register
+ *  TX CH1 next dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_CH1_REG (DR_REG_H264_DMA_BASE + 0x12c)
+/** H264_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define H264_DMA_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH1_M  (H264_DMA_OUTLINK_DSCR_CH1_V << H264_DMA_OUTLINK_DSCR_CH1_S)
+#define H264_DMA_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH1_S  0
+
+/** H264_DMA_OUT_DSCR_BF0_CH1_REG register
+ *  TX CH1 last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_H264_DMA_BASE + 0x130)
+/** H264_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH1_M  (H264_DMA_OUTLINK_DSCR_BF0_CH1_V << H264_DMA_OUTLINK_DSCR_BF0_CH1_S)
+#define H264_DMA_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** H264_DMA_OUT_DSCR_BF1_CH1_REG register
+ *  TX CH1 second-to-last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_H264_DMA_BASE + 0x134)
+/** H264_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH1_M  (H264_DMA_OUTLINK_DSCR_BF1_CH1_V << H264_DMA_OUTLINK_DSCR_BF1_CH1_S)
+#define H264_DMA_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** H264_DMA_OUT_ARB_CH1_REG register
+ *  TX CH1 arb register
+ */
+#define H264_DMA_OUT_ARB_CH1_REG (DR_REG_H264_DMA_BASE + 0x13c)
+/** H264_DMA_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH1_M  (H264_DMA_OUT_ARB_TOKEN_NUM_CH1_V << H264_DMA_OUT_ARB_TOKEN_NUM_CH1_S)
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH1_S  0
+/** H264_DMA_INTER_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH1    (BIT(6))
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH1_M  (H264_DMA_INTER_OUT_ARB_PRIORITY_CH1_V << H264_DMA_INTER_OUT_ARB_PRIORITY_CH1_S)
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH1_V  0x00000001U
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH1_S  6
+
+/** H264_DMA_OUT_ETM_CONF_CH1_REG register
+ *  TX CH1 ETM config register
+ */
+#define H264_DMA_OUT_ETM_CONF_CH1_REG (DR_REG_H264_DMA_BASE + 0x168)
+/** H264_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_OUT_ETM_EN_CH1    (BIT(0))
+#define H264_DMA_OUT_ETM_EN_CH1_M  (H264_DMA_OUT_ETM_EN_CH1_V << H264_DMA_OUT_ETM_EN_CH1_S)
+#define H264_DMA_OUT_ETM_EN_CH1_V  0x00000001U
+#define H264_DMA_OUT_ETM_EN_CH1_S  0
+/** H264_DMA_OUT_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_OUT_ETM_LOOP_EN_CH1    (BIT(1))
+#define H264_DMA_OUT_ETM_LOOP_EN_CH1_M  (H264_DMA_OUT_ETM_LOOP_EN_CH1_V << H264_DMA_OUT_ETM_LOOP_EN_CH1_S)
+#define H264_DMA_OUT_ETM_LOOP_EN_CH1_V  0x00000001U
+#define H264_DMA_OUT_ETM_LOOP_EN_CH1_S  1
+/** H264_DMA_OUT_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH1    0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH1_M  (H264_DMA_OUT_DSCR_TASK_MAK_CH1_V << H264_DMA_OUT_DSCR_TASK_MAK_CH1_S)
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH1_S  2
+
+/** H264_DMA_OUT_BUF_LEN_CH1_REG register
+ *  tx CH1 buf len register
+ */
+#define H264_DMA_OUT_BUF_LEN_CH1_REG (DR_REG_H264_DMA_BASE + 0x170)
+/** H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1    0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1_M  (H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1_V << H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1_S)
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1_V  0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1_S  0
+
+/** H264_DMA_OUT_FIFO_BCNT_CH1_REG register
+ *  tx CH1 fifo byte cnt register
+ */
+#define H264_DMA_OUT_FIFO_BCNT_CH1_REG (DR_REG_H264_DMA_BASE + 0x174)
+/** H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1    0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_M  (H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_V << H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_S)
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_V  0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_S  0
+
+/** H264_DMA_OUT_PUSH_BYTECNT_CH1_REG register
+ *  tx CH1 push byte cnt register
+ */
+#define H264_DMA_OUT_PUSH_BYTECNT_CH1_REG (DR_REG_H264_DMA_BASE + 0x178)
+/** H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1 : RO; bitpos: [7:0]; default: 255;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1    0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1_M  (H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1_V << H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1_S)
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1_V  0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1_S  0
+
+/** H264_DMA_OUT_XADDR_CH1_REG register
+ *  tx CH1 xaddr register
+ */
+#define H264_DMA_OUT_XADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x17c)
+/** H264_DMA_OUT_CMDFIFO_XADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH1_M  (H264_DMA_OUT_CMDFIFO_XADDR_CH1_V << H264_DMA_OUT_CMDFIFO_XADDR_CH1_S)
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH1_S  0
+
+/** H264_DMA_OUT_CONF0_CH2_REG register
+ *  TX CH2 config0 register
+ */
+#define H264_DMA_OUT_CONF0_CH2_REG (DR_REG_H264_DMA_BASE + 0x200)
+/** H264_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define H264_DMA_OUT_AUTO_WRBACK_CH2    (BIT(0))
+#define H264_DMA_OUT_AUTO_WRBACK_CH2_M  (H264_DMA_OUT_AUTO_WRBACK_CH2_V << H264_DMA_OUT_AUTO_WRBACK_CH2_S)
+#define H264_DMA_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define H264_DMA_OUT_AUTO_WRBACK_CH2_S  0
+/** H264_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define H264_DMA_OUT_EOF_MODE_CH2    (BIT(1))
+#define H264_DMA_OUT_EOF_MODE_CH2_M  (H264_DMA_OUT_EOF_MODE_CH2_V << H264_DMA_OUT_EOF_MODE_CH2_S)
+#define H264_DMA_OUT_EOF_MODE_CH2_V  0x00000001U
+#define H264_DMA_OUT_EOF_MODE_CH2_S  1
+/** H264_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define H264_DMA_OUTDSCR_BURST_EN_CH2    (BIT(2))
+#define H264_DMA_OUTDSCR_BURST_EN_CH2_M  (H264_DMA_OUTDSCR_BURST_EN_CH2_V << H264_DMA_OUTDSCR_BURST_EN_CH2_S)
+#define H264_DMA_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define H264_DMA_OUTDSCR_BURST_EN_CH2_S  2
+/** H264_DMA_OUT_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_OUT_ECC_AES_EN_CH2    (BIT(3))
+#define H264_DMA_OUT_ECC_AES_EN_CH2_M  (H264_DMA_OUT_ECC_AES_EN_CH2_V << H264_DMA_OUT_ECC_AES_EN_CH2_S)
+#define H264_DMA_OUT_ECC_AES_EN_CH2_V  0x00000001U
+#define H264_DMA_OUT_ECC_AES_EN_CH2_S  3
+/** H264_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_OUT_CHECK_OWNER_CH2    (BIT(4))
+#define H264_DMA_OUT_CHECK_OWNER_CH2_M  (H264_DMA_OUT_CHECK_OWNER_CH2_V << H264_DMA_OUT_CHECK_OWNER_CH2_S)
+#define H264_DMA_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define H264_DMA_OUT_CHECK_OWNER_CH2_S  4
+/** H264_DMA_OUT_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 2. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH2    0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH2_M  (H264_DMA_OUT_MEM_BURST_LENGTH_CH2_V << H264_DMA_OUT_MEM_BURST_LENGTH_CH2_S)
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH2_S  6
+/** H264_DMA_OUT_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH2    (BIT(12))
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH2_M  (H264_DMA_OUT_PAGE_BOUND_EN_CH2_V << H264_DMA_OUT_PAGE_BOUND_EN_CH2_S)
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH2_S  12
+/** H264_DMA_OUT_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define H264_DMA_OUT_RST_CH2    (BIT(24))
+#define H264_DMA_OUT_RST_CH2_M  (H264_DMA_OUT_RST_CH2_V << H264_DMA_OUT_RST_CH2_S)
+#define H264_DMA_OUT_RST_CH2_V  0x00000001U
+#define H264_DMA_OUT_RST_CH2_S  24
+/** H264_DMA_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_OUT_CMD_DISABLE_CH2    (BIT(25))
+#define H264_DMA_OUT_CMD_DISABLE_CH2_M  (H264_DMA_OUT_CMD_DISABLE_CH2_V << H264_DMA_OUT_CMD_DISABLE_CH2_S)
+#define H264_DMA_OUT_CMD_DISABLE_CH2_V  0x00000001U
+#define H264_DMA_OUT_CMD_DISABLE_CH2_S  25
+/** H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2_M  (H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2_V << H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** H264_DMA_OUT_INT_RAW_CH2_REG register
+ *  TX CH2  interrupt raw register
+ */
+#define H264_DMA_OUT_INT_RAW_CH2_REG (DR_REG_H264_DMA_BASE + 0x204)
+/** H264_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define H264_DMA_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define H264_DMA_OUT_DONE_CH2_INT_RAW_M  (H264_DMA_OUT_DONE_CH2_INT_RAW_V << H264_DMA_OUT_DONE_CH2_INT_RAW_S)
+#define H264_DMA_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH2_INT_RAW_S  0
+/** H264_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define H264_DMA_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define H264_DMA_OUT_EOF_CH2_INT_RAW_M  (H264_DMA_OUT_EOF_CH2_INT_RAW_V << H264_DMA_OUT_EOF_CH2_INT_RAW_S)
+#define H264_DMA_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH2_INT_RAW_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M  (H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M  (H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V << H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S  8
+
+/** H264_DMA_OUT_INT_ENA_CH2_REG register
+ *  TX CH2  interrupt ena register
+ */
+#define H264_DMA_OUT_INT_ENA_CH2_REG (DR_REG_H264_DMA_BASE + 0x208)
+/** H264_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define H264_DMA_OUT_DONE_CH2_INT_ENA_M  (H264_DMA_OUT_DONE_CH2_INT_ENA_V << H264_DMA_OUT_DONE_CH2_INT_ENA_S)
+#define H264_DMA_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH2_INT_ENA_S  0
+/** H264_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define H264_DMA_OUT_EOF_CH2_INT_ENA_M  (H264_DMA_OUT_EOF_CH2_INT_ENA_V << H264_DMA_OUT_EOF_CH2_INT_ENA_S)
+#define H264_DMA_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH2_INT_ENA_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M  (H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M  (H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V << H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S  8
+
+/** H264_DMA_OUT_INT_ST_CH2_REG register
+ *  TX CH2  interrupt st register
+ */
+#define H264_DMA_OUT_INT_ST_CH2_REG (DR_REG_H264_DMA_BASE + 0x20c)
+/** H264_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define H264_DMA_OUT_DONE_CH2_INT_ST_M  (H264_DMA_OUT_DONE_CH2_INT_ST_V << H264_DMA_OUT_DONE_CH2_INT_ST_S)
+#define H264_DMA_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH2_INT_ST_S  0
+/** H264_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define H264_DMA_OUT_EOF_CH2_INT_ST_M  (H264_DMA_OUT_EOF_CH2_INT_ST_V << H264_DMA_OUT_EOF_CH2_INT_ST_S)
+#define H264_DMA_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH2_INT_ST_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ST_M  (H264_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << H264_DMA_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M  (H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST_V << H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST_V << H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST_V << H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST_V << H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST_V << H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST_S  8
+
+/** H264_DMA_OUT_INT_CLR_CH2_REG register
+ *  TX CH2  interrupt clr register
+ */
+#define H264_DMA_OUT_INT_CLR_CH2_REG (DR_REG_H264_DMA_BASE + 0x210)
+/** H264_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define H264_DMA_OUT_DONE_CH2_INT_CLR_M  (H264_DMA_OUT_DONE_CH2_INT_CLR_V << H264_DMA_OUT_DONE_CH2_INT_CLR_S)
+#define H264_DMA_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH2_INT_CLR_S  0
+/** H264_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define H264_DMA_OUT_EOF_CH2_INT_CLR_M  (H264_DMA_OUT_EOF_CH2_INT_CLR_V << H264_DMA_OUT_EOF_CH2_INT_CLR_S)
+#define H264_DMA_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH2_INT_CLR_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M  (H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M  (H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V << H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S  8
+
+/** H264_DMA_OUTFIFO_STATUS_CH2_REG register
+ *  TX CH2 outfifo status register
+ */
+#define H264_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_H264_DMA_BASE + 0x214)
+/** H264_DMA_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L2_CH2    (BIT(0))
+#define H264_DMA_OUTFIFO_FULL_L2_CH2_M  (H264_DMA_OUTFIFO_FULL_L2_CH2_V << H264_DMA_OUTFIFO_FULL_L2_CH2_S)
+#define H264_DMA_OUTFIFO_FULL_L2_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L2_CH2_S  0
+/** H264_DMA_OUTFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH2    (BIT(1))
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH2_M  (H264_DMA_OUTFIFO_EMPTY_L2_CH2_V << H264_DMA_OUTFIFO_EMPTY_L2_CH2_S)
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH2_S  1
+/** H264_DMA_OUTFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L2_CH2    0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH2_M  (H264_DMA_OUTFIFO_CNT_L2_CH2_V << H264_DMA_OUTFIFO_CNT_L2_CH2_S)
+#define H264_DMA_OUTFIFO_CNT_L2_CH2_V  0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH2_S  2
+/** H264_DMA_OUTFIFO_FULL_L1_CH2 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L1_CH2    (BIT(6))
+#define H264_DMA_OUTFIFO_FULL_L1_CH2_M  (H264_DMA_OUTFIFO_FULL_L1_CH2_V << H264_DMA_OUTFIFO_FULL_L1_CH2_S)
+#define H264_DMA_OUTFIFO_FULL_L1_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L1_CH2_S  6
+/** H264_DMA_OUTFIFO_EMPTY_L1_CH2 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH2    (BIT(7))
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH2_M  (H264_DMA_OUTFIFO_EMPTY_L1_CH2_V << H264_DMA_OUTFIFO_EMPTY_L1_CH2_S)
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH2_S  7
+/** H264_DMA_OUTFIFO_CNT_L1_CH2 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L1_CH2    0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH2_M  (H264_DMA_OUTFIFO_CNT_L1_CH2_V << H264_DMA_OUTFIFO_CNT_L1_CH2_S)
+#define H264_DMA_OUTFIFO_CNT_L1_CH2_V  0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH2_S  8
+/** H264_DMA_OUTFIFO_FULL_L3_CH2 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L3_CH2    (BIT(16))
+#define H264_DMA_OUTFIFO_FULL_L3_CH2_M  (H264_DMA_OUTFIFO_FULL_L3_CH2_V << H264_DMA_OUTFIFO_FULL_L3_CH2_S)
+#define H264_DMA_OUTFIFO_FULL_L3_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L3_CH2_S  16
+/** H264_DMA_OUTFIFO_EMPTY_L3_CH2 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH2    (BIT(17))
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH2_M  (H264_DMA_OUTFIFO_EMPTY_L3_CH2_V << H264_DMA_OUTFIFO_EMPTY_L3_CH2_S)
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH2_S  17
+/** H264_DMA_OUTFIFO_CNT_L3_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L3_CH2    0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH2_M  (H264_DMA_OUTFIFO_CNT_L3_CH2_V << H264_DMA_OUTFIFO_CNT_L3_CH2_S)
+#define H264_DMA_OUTFIFO_CNT_L3_CH2_V  0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH2_S  18
+
+/** H264_DMA_OUT_PUSH_CH2_REG register
+ *  TX CH2 outfifo push register
+ */
+#define H264_DMA_OUT_PUSH_CH2_REG (DR_REG_H264_DMA_BASE + 0x218)
+/** H264_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_WDATA_CH2    0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH2_M  (H264_DMA_OUTFIFO_WDATA_CH2_V << H264_DMA_OUTFIFO_WDATA_CH2_S)
+#define H264_DMA_OUTFIFO_WDATA_CH2_V  0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH2_S  0
+/** H264_DMA_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_PUSH_CH2    (BIT(10))
+#define H264_DMA_OUTFIFO_PUSH_CH2_M  (H264_DMA_OUTFIFO_PUSH_CH2_V << H264_DMA_OUTFIFO_PUSH_CH2_S)
+#define H264_DMA_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_PUSH_CH2_S  10
+
+/** H264_DMA_OUT_LINK_CONF_CH2_REG register
+ *  TX CH2 out_link dscr ctrl register
+ */
+#define H264_DMA_OUT_LINK_CONF_CH2_REG (DR_REG_H264_DMA_BASE + 0x21c)
+/** H264_DMA_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_STOP_CH2    (BIT(20))
+#define H264_DMA_OUTLINK_STOP_CH2_M  (H264_DMA_OUTLINK_STOP_CH2_V << H264_DMA_OUTLINK_STOP_CH2_S)
+#define H264_DMA_OUTLINK_STOP_CH2_V  0x00000001U
+#define H264_DMA_OUTLINK_STOP_CH2_S  20
+/** H264_DMA_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_START_CH2    (BIT(21))
+#define H264_DMA_OUTLINK_START_CH2_M  (H264_DMA_OUTLINK_START_CH2_V << H264_DMA_OUTLINK_START_CH2_S)
+#define H264_DMA_OUTLINK_START_CH2_V  0x00000001U
+#define H264_DMA_OUTLINK_START_CH2_S  21
+/** H264_DMA_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define H264_DMA_OUTLINK_RESTART_CH2    (BIT(22))
+#define H264_DMA_OUTLINK_RESTART_CH2_M  (H264_DMA_OUTLINK_RESTART_CH2_V << H264_DMA_OUTLINK_RESTART_CH2_S)
+#define H264_DMA_OUTLINK_RESTART_CH2_V  0x00000001U
+#define H264_DMA_OUTLINK_RESTART_CH2_S  22
+/** H264_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define H264_DMA_OUTLINK_PARK_CH2    (BIT(23))
+#define H264_DMA_OUTLINK_PARK_CH2_M  (H264_DMA_OUTLINK_PARK_CH2_V << H264_DMA_OUTLINK_PARK_CH2_S)
+#define H264_DMA_OUTLINK_PARK_CH2_V  0x00000001U
+#define H264_DMA_OUTLINK_PARK_CH2_S  23
+
+/** H264_DMA_OUT_LINK_ADDR_CH2_REG register
+ *  TX CH2 out_link dscr addr register
+ */
+#define H264_DMA_OUT_LINK_ADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x220)
+/** H264_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH2_M  (H264_DMA_OUTLINK_ADDR_CH2_V << H264_DMA_OUTLINK_ADDR_CH2_S)
+#define H264_DMA_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH2_S  0
+
+/** H264_DMA_OUT_STATE_CH2_REG register
+ *  TX CH2 state register
+ */
+#define H264_DMA_OUT_STATE_CH2_REG (DR_REG_H264_DMA_BASE + 0x224)
+/** H264_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH2_M  (H264_DMA_OUTLINK_DSCR_ADDR_CH2_V << H264_DMA_OUTLINK_DSCR_ADDR_CH2_S)
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH2_S  0
+/** H264_DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_OUT_DSCR_STATE_CH2    0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH2_M  (H264_DMA_OUT_DSCR_STATE_CH2_V << H264_DMA_OUT_DSCR_STATE_CH2_S)
+#define H264_DMA_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH2_S  18
+/** H264_DMA_OUT_STATE_CH2 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_OUT_STATE_CH2    0x0000000FU
+#define H264_DMA_OUT_STATE_CH2_M  (H264_DMA_OUT_STATE_CH2_V << H264_DMA_OUT_STATE_CH2_S)
+#define H264_DMA_OUT_STATE_CH2_V  0x0000000FU
+#define H264_DMA_OUT_STATE_CH2_S  20
+/** H264_DMA_OUT_RESET_AVAIL_CH2 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_OUT_RESET_AVAIL_CH2    (BIT(24))
+#define H264_DMA_OUT_RESET_AVAIL_CH2_M  (H264_DMA_OUT_RESET_AVAIL_CH2_V << H264_DMA_OUT_RESET_AVAIL_CH2_S)
+#define H264_DMA_OUT_RESET_AVAIL_CH2_V  0x00000001U
+#define H264_DMA_OUT_RESET_AVAIL_CH2_S  24
+
+/** H264_DMA_OUT_EOF_DES_ADDR_CH2_REG register
+ *  TX CH2 eof des addr register
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x228)
+/** H264_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH2_M  (H264_DMA_OUT_EOF_DES_ADDR_CH2_V << H264_DMA_OUT_EOF_DES_ADDR_CH2_S)
+#define H264_DMA_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** H264_DMA_OUT_DSCR_CH2_REG register
+ *  TX CH2 next dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_CH2_REG (DR_REG_H264_DMA_BASE + 0x22c)
+/** H264_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define H264_DMA_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH2_M  (H264_DMA_OUTLINK_DSCR_CH2_V << H264_DMA_OUTLINK_DSCR_CH2_S)
+#define H264_DMA_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH2_S  0
+
+/** H264_DMA_OUT_DSCR_BF0_CH2_REG register
+ *  TX CH2 last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_H264_DMA_BASE + 0x230)
+/** H264_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH2_M  (H264_DMA_OUTLINK_DSCR_BF0_CH2_V << H264_DMA_OUTLINK_DSCR_BF0_CH2_S)
+#define H264_DMA_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** H264_DMA_OUT_DSCR_BF1_CH2_REG register
+ *  TX CH2 second-to-last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_H264_DMA_BASE + 0x234)
+/** H264_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH2_M  (H264_DMA_OUTLINK_DSCR_BF1_CH2_V << H264_DMA_OUTLINK_DSCR_BF1_CH2_S)
+#define H264_DMA_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** H264_DMA_OUT_ARB_CH2_REG register
+ *  TX CH2 arb register
+ */
+#define H264_DMA_OUT_ARB_CH2_REG (DR_REG_H264_DMA_BASE + 0x23c)
+/** H264_DMA_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH2_M  (H264_DMA_OUT_ARB_TOKEN_NUM_CH2_V << H264_DMA_OUT_ARB_TOKEN_NUM_CH2_S)
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH2_S  0
+/** H264_DMA_INTER_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH2    (BIT(6))
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH2_M  (H264_DMA_INTER_OUT_ARB_PRIORITY_CH2_V << H264_DMA_INTER_OUT_ARB_PRIORITY_CH2_S)
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH2_V  0x00000001U
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH2_S  6
+
+/** H264_DMA_OUT_ETM_CONF_CH2_REG register
+ *  TX CH2 ETM config register
+ */
+#define H264_DMA_OUT_ETM_CONF_CH2_REG (DR_REG_H264_DMA_BASE + 0x268)
+/** H264_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_OUT_ETM_EN_CH2    (BIT(0))
+#define H264_DMA_OUT_ETM_EN_CH2_M  (H264_DMA_OUT_ETM_EN_CH2_V << H264_DMA_OUT_ETM_EN_CH2_S)
+#define H264_DMA_OUT_ETM_EN_CH2_V  0x00000001U
+#define H264_DMA_OUT_ETM_EN_CH2_S  0
+/** H264_DMA_OUT_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_OUT_ETM_LOOP_EN_CH2    (BIT(1))
+#define H264_DMA_OUT_ETM_LOOP_EN_CH2_M  (H264_DMA_OUT_ETM_LOOP_EN_CH2_V << H264_DMA_OUT_ETM_LOOP_EN_CH2_S)
+#define H264_DMA_OUT_ETM_LOOP_EN_CH2_V  0x00000001U
+#define H264_DMA_OUT_ETM_LOOP_EN_CH2_S  1
+/** H264_DMA_OUT_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH2    0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH2_M  (H264_DMA_OUT_DSCR_TASK_MAK_CH2_V << H264_DMA_OUT_DSCR_TASK_MAK_CH2_S)
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH2_S  2
+
+/** H264_DMA_OUT_BUF_LEN_CH2_REG register
+ *  tx CH2 buf len register
+ */
+#define H264_DMA_OUT_BUF_LEN_CH2_REG (DR_REG_H264_DMA_BASE + 0x270)
+/** H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2    0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2_M  (H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2_V << H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2_S)
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2_V  0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2_S  0
+
+/** H264_DMA_OUT_FIFO_BCNT_CH2_REG register
+ *  tx CH2 fifo byte cnt register
+ */
+#define H264_DMA_OUT_FIFO_BCNT_CH2_REG (DR_REG_H264_DMA_BASE + 0x274)
+/** H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2    0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_M  (H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_V << H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_S)
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_V  0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_S  0
+
+/** H264_DMA_OUT_PUSH_BYTECNT_CH2_REG register
+ *  tx CH2 push byte cnt register
+ */
+#define H264_DMA_OUT_PUSH_BYTECNT_CH2_REG (DR_REG_H264_DMA_BASE + 0x278)
+/** H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2 : RO; bitpos: [7:0]; default: 255;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2    0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2_M  (H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2_V << H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2_S)
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2_V  0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2_S  0
+
+/** H264_DMA_OUT_XADDR_CH2_REG register
+ *  tx CH2 xaddr register
+ */
+#define H264_DMA_OUT_XADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x27c)
+/** H264_DMA_OUT_CMDFIFO_XADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH2_M  (H264_DMA_OUT_CMDFIFO_XADDR_CH2_V << H264_DMA_OUT_CMDFIFO_XADDR_CH2_S)
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH2_S  0
+
+/** H264_DMA_OUT_CONF0_CH3_REG register
+ *  TX CH3 config0 register
+ */
+#define H264_DMA_OUT_CONF0_CH3_REG (DR_REG_H264_DMA_BASE + 0x300)
+/** H264_DMA_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define H264_DMA_OUT_AUTO_WRBACK_CH3    (BIT(0))
+#define H264_DMA_OUT_AUTO_WRBACK_CH3_M  (H264_DMA_OUT_AUTO_WRBACK_CH3_V << H264_DMA_OUT_AUTO_WRBACK_CH3_S)
+#define H264_DMA_OUT_AUTO_WRBACK_CH3_V  0x00000001U
+#define H264_DMA_OUT_AUTO_WRBACK_CH3_S  0
+/** H264_DMA_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define H264_DMA_OUT_EOF_MODE_CH3    (BIT(1))
+#define H264_DMA_OUT_EOF_MODE_CH3_M  (H264_DMA_OUT_EOF_MODE_CH3_V << H264_DMA_OUT_EOF_MODE_CH3_S)
+#define H264_DMA_OUT_EOF_MODE_CH3_V  0x00000001U
+#define H264_DMA_OUT_EOF_MODE_CH3_S  1
+/** H264_DMA_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define H264_DMA_OUTDSCR_BURST_EN_CH3    (BIT(2))
+#define H264_DMA_OUTDSCR_BURST_EN_CH3_M  (H264_DMA_OUTDSCR_BURST_EN_CH3_V << H264_DMA_OUTDSCR_BURST_EN_CH3_S)
+#define H264_DMA_OUTDSCR_BURST_EN_CH3_V  0x00000001U
+#define H264_DMA_OUTDSCR_BURST_EN_CH3_S  2
+/** H264_DMA_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_OUT_ECC_AES_EN_CH3    (BIT(3))
+#define H264_DMA_OUT_ECC_AES_EN_CH3_M  (H264_DMA_OUT_ECC_AES_EN_CH3_V << H264_DMA_OUT_ECC_AES_EN_CH3_S)
+#define H264_DMA_OUT_ECC_AES_EN_CH3_V  0x00000001U
+#define H264_DMA_OUT_ECC_AES_EN_CH3_S  3
+/** H264_DMA_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_OUT_CHECK_OWNER_CH3    (BIT(4))
+#define H264_DMA_OUT_CHECK_OWNER_CH3_M  (H264_DMA_OUT_CHECK_OWNER_CH3_V << H264_DMA_OUT_CHECK_OWNER_CH3_S)
+#define H264_DMA_OUT_CHECK_OWNER_CH3_V  0x00000001U
+#define H264_DMA_OUT_CHECK_OWNER_CH3_S  4
+/** H264_DMA_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 3. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH3    0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH3_M  (H264_DMA_OUT_MEM_BURST_LENGTH_CH3_V << H264_DMA_OUT_MEM_BURST_LENGTH_CH3_S)
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH3_V  0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH3_S  6
+/** H264_DMA_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH3    (BIT(12))
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH3_M  (H264_DMA_OUT_PAGE_BOUND_EN_CH3_V << H264_DMA_OUT_PAGE_BOUND_EN_CH3_S)
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH3_V  0x00000001U
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH3_S  12
+/** H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3    (BIT(26))
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3_M  (H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3_S)
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3_V  0x00000001U
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3_S  26
+
+/** H264_DMA_OUT_INT_RAW_CH3_REG register
+ *  TX CH3  interrupt raw register
+ */
+#define H264_DMA_OUT_INT_RAW_CH3_REG (DR_REG_H264_DMA_BASE + 0x304)
+/** H264_DMA_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define H264_DMA_OUT_DONE_CH3_INT_RAW    (BIT(0))
+#define H264_DMA_OUT_DONE_CH3_INT_RAW_M  (H264_DMA_OUT_DONE_CH3_INT_RAW_V << H264_DMA_OUT_DONE_CH3_INT_RAW_S)
+#define H264_DMA_OUT_DONE_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH3_INT_RAW_S  0
+/** H264_DMA_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define H264_DMA_OUT_EOF_CH3_INT_RAW    (BIT(1))
+#define H264_DMA_OUT_EOF_CH3_INT_RAW_M  (H264_DMA_OUT_EOF_CH3_INT_RAW_V << H264_DMA_OUT_EOF_CH3_INT_RAW_S)
+#define H264_DMA_OUT_EOF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH3_INT_RAW_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW_M  (H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW_V << H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_M  (H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_V << H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S  8
+
+/** H264_DMA_OUT_INT_ENA_CH3_REG register
+ *  TX CH3  interrupt ena register
+ */
+#define H264_DMA_OUT_INT_ENA_CH3_REG (DR_REG_H264_DMA_BASE + 0x308)
+/** H264_DMA_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH3_INT_ENA    (BIT(0))
+#define H264_DMA_OUT_DONE_CH3_INT_ENA_M  (H264_DMA_OUT_DONE_CH3_INT_ENA_V << H264_DMA_OUT_DONE_CH3_INT_ENA_S)
+#define H264_DMA_OUT_DONE_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH3_INT_ENA_S  0
+/** H264_DMA_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH3_INT_ENA    (BIT(1))
+#define H264_DMA_OUT_EOF_CH3_INT_ENA_M  (H264_DMA_OUT_EOF_CH3_INT_ENA_V << H264_DMA_OUT_EOF_CH3_INT_ENA_S)
+#define H264_DMA_OUT_EOF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH3_INT_ENA_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA_M  (H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA_V << H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_M  (H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_V << H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S  8
+
+/** H264_DMA_OUT_INT_ST_CH3_REG register
+ *  TX CH3  interrupt st register
+ */
+#define H264_DMA_OUT_INT_ST_CH3_REG (DR_REG_H264_DMA_BASE + 0x30c)
+/** H264_DMA_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH3_INT_ST    (BIT(0))
+#define H264_DMA_OUT_DONE_CH3_INT_ST_M  (H264_DMA_OUT_DONE_CH3_INT_ST_V << H264_DMA_OUT_DONE_CH3_INT_ST_S)
+#define H264_DMA_OUT_DONE_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH3_INT_ST_S  0
+/** H264_DMA_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH3_INT_ST    (BIT(1))
+#define H264_DMA_OUT_EOF_CH3_INT_ST_M  (H264_DMA_OUT_EOF_CH3_INT_ST_V << H264_DMA_OUT_EOF_CH3_INT_ST_S)
+#define H264_DMA_OUT_EOF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH3_INT_ST_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ST    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ST_M  (H264_DMA_OUT_DSCR_ERR_CH3_INT_ST_V << H264_DMA_OUT_DSCR_ERR_CH3_INT_ST_S)
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ST_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST_M  (H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST_V << H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST_V << H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST_V << H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST_V << H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST_V << H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST_S  8
+
+/** H264_DMA_OUT_INT_CLR_CH3_REG register
+ *  TX CH3  interrupt clr register
+ */
+#define H264_DMA_OUT_INT_CLR_CH3_REG (DR_REG_H264_DMA_BASE + 0x310)
+/** H264_DMA_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH3_INT_CLR    (BIT(0))
+#define H264_DMA_OUT_DONE_CH3_INT_CLR_M  (H264_DMA_OUT_DONE_CH3_INT_CLR_V << H264_DMA_OUT_DONE_CH3_INT_CLR_S)
+#define H264_DMA_OUT_DONE_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH3_INT_CLR_S  0
+/** H264_DMA_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH3_INT_CLR    (BIT(1))
+#define H264_DMA_OUT_EOF_CH3_INT_CLR_M  (H264_DMA_OUT_EOF_CH3_INT_CLR_V << H264_DMA_OUT_EOF_CH3_INT_CLR_S)
+#define H264_DMA_OUT_EOF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH3_INT_CLR_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR_M  (H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR_V << H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_M  (H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_V << H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S  8
+
+/** H264_DMA_OUTFIFO_STATUS_CH3_REG register
+ *  TX CH3 outfifo status register
+ */
+#define H264_DMA_OUTFIFO_STATUS_CH3_REG (DR_REG_H264_DMA_BASE + 0x314)
+/** H264_DMA_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L2_CH3    (BIT(0))
+#define H264_DMA_OUTFIFO_FULL_L2_CH3_M  (H264_DMA_OUTFIFO_FULL_L2_CH3_V << H264_DMA_OUTFIFO_FULL_L2_CH3_S)
+#define H264_DMA_OUTFIFO_FULL_L2_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L2_CH3_S  0
+/** H264_DMA_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH3    (BIT(1))
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH3_M  (H264_DMA_OUTFIFO_EMPTY_L2_CH3_V << H264_DMA_OUTFIFO_EMPTY_L2_CH3_S)
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH3_S  1
+/** H264_DMA_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L2_CH3    0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH3_M  (H264_DMA_OUTFIFO_CNT_L2_CH3_V << H264_DMA_OUTFIFO_CNT_L2_CH3_S)
+#define H264_DMA_OUTFIFO_CNT_L2_CH3_V  0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH3_S  2
+/** H264_DMA_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L1_CH3    (BIT(6))
+#define H264_DMA_OUTFIFO_FULL_L1_CH3_M  (H264_DMA_OUTFIFO_FULL_L1_CH3_V << H264_DMA_OUTFIFO_FULL_L1_CH3_S)
+#define H264_DMA_OUTFIFO_FULL_L1_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L1_CH3_S  6
+/** H264_DMA_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH3    (BIT(7))
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH3_M  (H264_DMA_OUTFIFO_EMPTY_L1_CH3_V << H264_DMA_OUTFIFO_EMPTY_L1_CH3_S)
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH3_S  7
+/** H264_DMA_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L1_CH3    0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH3_M  (H264_DMA_OUTFIFO_CNT_L1_CH3_V << H264_DMA_OUTFIFO_CNT_L1_CH3_S)
+#define H264_DMA_OUTFIFO_CNT_L1_CH3_V  0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH3_S  8
+/** H264_DMA_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L3_CH3    (BIT(16))
+#define H264_DMA_OUTFIFO_FULL_L3_CH3_M  (H264_DMA_OUTFIFO_FULL_L3_CH3_V << H264_DMA_OUTFIFO_FULL_L3_CH3_S)
+#define H264_DMA_OUTFIFO_FULL_L3_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L3_CH3_S  16
+/** H264_DMA_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH3    (BIT(17))
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH3_M  (H264_DMA_OUTFIFO_EMPTY_L3_CH3_V << H264_DMA_OUTFIFO_EMPTY_L3_CH3_S)
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH3_S  17
+/** H264_DMA_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L3_CH3    0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH3_M  (H264_DMA_OUTFIFO_CNT_L3_CH3_V << H264_DMA_OUTFIFO_CNT_L3_CH3_S)
+#define H264_DMA_OUTFIFO_CNT_L3_CH3_V  0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH3_S  18
+
+/** H264_DMA_OUT_PUSH_CH3_REG register
+ *  TX CH3 outfifo push register
+ */
+#define H264_DMA_OUT_PUSH_CH3_REG (DR_REG_H264_DMA_BASE + 0x318)
+/** H264_DMA_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_WDATA_CH3    0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH3_M  (H264_DMA_OUTFIFO_WDATA_CH3_V << H264_DMA_OUTFIFO_WDATA_CH3_S)
+#define H264_DMA_OUTFIFO_WDATA_CH3_V  0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH3_S  0
+/** H264_DMA_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_PUSH_CH3    (BIT(10))
+#define H264_DMA_OUTFIFO_PUSH_CH3_M  (H264_DMA_OUTFIFO_PUSH_CH3_V << H264_DMA_OUTFIFO_PUSH_CH3_S)
+#define H264_DMA_OUTFIFO_PUSH_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_PUSH_CH3_S  10
+
+/** H264_DMA_OUT_LINK_CONF_CH3_REG register
+ *  TX CH3 out_link dscr ctrl register
+ */
+#define H264_DMA_OUT_LINK_CONF_CH3_REG (DR_REG_H264_DMA_BASE + 0x31c)
+/** H264_DMA_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_STOP_CH3    (BIT(20))
+#define H264_DMA_OUTLINK_STOP_CH3_M  (H264_DMA_OUTLINK_STOP_CH3_V << H264_DMA_OUTLINK_STOP_CH3_S)
+#define H264_DMA_OUTLINK_STOP_CH3_V  0x00000001U
+#define H264_DMA_OUTLINK_STOP_CH3_S  20
+/** H264_DMA_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_START_CH3    (BIT(21))
+#define H264_DMA_OUTLINK_START_CH3_M  (H264_DMA_OUTLINK_START_CH3_V << H264_DMA_OUTLINK_START_CH3_S)
+#define H264_DMA_OUTLINK_START_CH3_V  0x00000001U
+#define H264_DMA_OUTLINK_START_CH3_S  21
+/** H264_DMA_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define H264_DMA_OUTLINK_RESTART_CH3    (BIT(22))
+#define H264_DMA_OUTLINK_RESTART_CH3_M  (H264_DMA_OUTLINK_RESTART_CH3_V << H264_DMA_OUTLINK_RESTART_CH3_S)
+#define H264_DMA_OUTLINK_RESTART_CH3_V  0x00000001U
+#define H264_DMA_OUTLINK_RESTART_CH3_S  22
+/** H264_DMA_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define H264_DMA_OUTLINK_PARK_CH3    (BIT(23))
+#define H264_DMA_OUTLINK_PARK_CH3_M  (H264_DMA_OUTLINK_PARK_CH3_V << H264_DMA_OUTLINK_PARK_CH3_S)
+#define H264_DMA_OUTLINK_PARK_CH3_V  0x00000001U
+#define H264_DMA_OUTLINK_PARK_CH3_S  23
+
+/** H264_DMA_OUT_LINK_ADDR_CH3_REG register
+ *  TX CH3 out_link dscr addr register
+ */
+#define H264_DMA_OUT_LINK_ADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x320)
+/** H264_DMA_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_ADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH3_M  (H264_DMA_OUTLINK_ADDR_CH3_V << H264_DMA_OUTLINK_ADDR_CH3_S)
+#define H264_DMA_OUTLINK_ADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH3_S  0
+
+/** H264_DMA_OUT_STATE_CH3_REG register
+ *  TX CH3 state register
+ */
+#define H264_DMA_OUT_STATE_CH3_REG (DR_REG_H264_DMA_BASE + 0x324)
+/** H264_DMA_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH3    0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH3_M  (H264_DMA_OUTLINK_DSCR_ADDR_CH3_V << H264_DMA_OUTLINK_DSCR_ADDR_CH3_S)
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH3_V  0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH3_S  0
+/** H264_DMA_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_OUT_DSCR_STATE_CH3    0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH3_M  (H264_DMA_OUT_DSCR_STATE_CH3_V << H264_DMA_OUT_DSCR_STATE_CH3_S)
+#define H264_DMA_OUT_DSCR_STATE_CH3_V  0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH3_S  18
+/** H264_DMA_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_OUT_STATE_CH3    0x0000000FU
+#define H264_DMA_OUT_STATE_CH3_M  (H264_DMA_OUT_STATE_CH3_V << H264_DMA_OUT_STATE_CH3_S)
+#define H264_DMA_OUT_STATE_CH3_V  0x0000000FU
+#define H264_DMA_OUT_STATE_CH3_S  20
+
+/** H264_DMA_OUT_EOF_DES_ADDR_CH3_REG register
+ *  TX CH3 eof des addr register
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x328)
+/** H264_DMA_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH3_M  (H264_DMA_OUT_EOF_DES_ADDR_CH3_V << H264_DMA_OUT_EOF_DES_ADDR_CH3_S)
+#define H264_DMA_OUT_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH3_S  0
+
+/** H264_DMA_OUT_DSCR_CH3_REG register
+ *  TX CH3 next dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_CH3_REG (DR_REG_H264_DMA_BASE + 0x32c)
+/** H264_DMA_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define H264_DMA_OUTLINK_DSCR_CH3    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH3_M  (H264_DMA_OUTLINK_DSCR_CH3_V << H264_DMA_OUTLINK_DSCR_CH3_S)
+#define H264_DMA_OUTLINK_DSCR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH3_S  0
+
+/** H264_DMA_OUT_DSCR_BF0_CH3_REG register
+ *  TX CH3 last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF0_CH3_REG (DR_REG_H264_DMA_BASE + 0x330)
+/** H264_DMA_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF0_CH3    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH3_M  (H264_DMA_OUTLINK_DSCR_BF0_CH3_V << H264_DMA_OUTLINK_DSCR_BF0_CH3_S)
+#define H264_DMA_OUTLINK_DSCR_BF0_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH3_S  0
+
+/** H264_DMA_OUT_DSCR_BF1_CH3_REG register
+ *  TX CH3 second-to-last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF1_CH3_REG (DR_REG_H264_DMA_BASE + 0x334)
+/** H264_DMA_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF1_CH3    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH3_M  (H264_DMA_OUTLINK_DSCR_BF1_CH3_V << H264_DMA_OUTLINK_DSCR_BF1_CH3_S)
+#define H264_DMA_OUTLINK_DSCR_BF1_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH3_S  0
+
+/** H264_DMA_OUT_ARB_CH3_REG register
+ *  TX CH3 arb register
+ */
+#define H264_DMA_OUT_ARB_CH3_REG (DR_REG_H264_DMA_BASE + 0x33c)
+/** H264_DMA_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH3    0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH3_M  (H264_DMA_OUT_ARB_TOKEN_NUM_CH3_V << H264_DMA_OUT_ARB_TOKEN_NUM_CH3_S)
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH3_V  0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH3_S  0
+/** H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3    0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3_M  (H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3_V << H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3_S)
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3_V  0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3_S  4
+
+/** H264_DMA_OUT_ETM_CONF_CH3_REG register
+ *  TX CH3 ETM config register
+ */
+#define H264_DMA_OUT_ETM_CONF_CH3_REG (DR_REG_H264_DMA_BASE + 0x368)
+/** H264_DMA_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_OUT_ETM_EN_CH3    (BIT(0))
+#define H264_DMA_OUT_ETM_EN_CH3_M  (H264_DMA_OUT_ETM_EN_CH3_V << H264_DMA_OUT_ETM_EN_CH3_S)
+#define H264_DMA_OUT_ETM_EN_CH3_V  0x00000001U
+#define H264_DMA_OUT_ETM_EN_CH3_S  0
+/** H264_DMA_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_OUT_ETM_LOOP_EN_CH3    (BIT(1))
+#define H264_DMA_OUT_ETM_LOOP_EN_CH3_M  (H264_DMA_OUT_ETM_LOOP_EN_CH3_V << H264_DMA_OUT_ETM_LOOP_EN_CH3_S)
+#define H264_DMA_OUT_ETM_LOOP_EN_CH3_V  0x00000001U
+#define H264_DMA_OUT_ETM_LOOP_EN_CH3_S  1
+/** H264_DMA_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH3    0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH3_M  (H264_DMA_OUT_DSCR_TASK_MAK_CH3_V << H264_DMA_OUT_DSCR_TASK_MAK_CH3_S)
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH3_V  0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH3_S  2
+
+/** H264_DMA_OUT_BUF_LEN_CH3_REG register
+ *  tx CH3 buf len register
+ */
+#define H264_DMA_OUT_BUF_LEN_CH3_REG (DR_REG_H264_DMA_BASE + 0x370)
+/** H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3    0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3_M  (H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3_V << H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3_S)
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3_V  0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3_S  0
+
+/** H264_DMA_OUT_FIFO_BCNT_CH3_REG register
+ *  tx CH3 fifo byte cnt register
+ */
+#define H264_DMA_OUT_FIFO_BCNT_CH3_REG (DR_REG_H264_DMA_BASE + 0x374)
+/** H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3    0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_M  (H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_V << H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_S)
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_V  0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_S  0
+
+/** H264_DMA_OUT_PUSH_BYTECNT_CH3_REG register
+ *  tx CH3 push byte cnt register
+ */
+#define H264_DMA_OUT_PUSH_BYTECNT_CH3_REG (DR_REG_H264_DMA_BASE + 0x378)
+/** H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3 : RO; bitpos: [7:0]; default: 63;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3    0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3_M  (H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3_V << H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3_S)
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3_V  0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3_S  0
+
+/** H264_DMA_OUT_XADDR_CH3_REG register
+ *  tx CH3 xaddr register
+ */
+#define H264_DMA_OUT_XADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x37c)
+/** H264_DMA_OUT_CMDFIFO_XADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH3_M  (H264_DMA_OUT_CMDFIFO_XADDR_CH3_V << H264_DMA_OUT_CMDFIFO_XADDR_CH3_S)
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH3_S  0
+
+/** H264_DMA_OUT_BLOCK_BUF_LEN_CH3_REG register
+ *  tx CH3 block buf len register
+ */
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH3_REG (DR_REG_H264_DMA_BASE + 0x380)
+/** H264_DMA_OUT_BLOCK_BUF_LEN_CH3 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH3    0x0FFFFFFFU
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH3_M  (H264_DMA_OUT_BLOCK_BUF_LEN_CH3_V << H264_DMA_OUT_BLOCK_BUF_LEN_CH3_S)
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH3_V  0x0FFFFFFFU
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH3_S  0
+
+/** H264_DMA_OUT_CONF0_CH4_REG register
+ *  TX CH4 config0 register
+ */
+#define H264_DMA_OUT_CONF0_CH4_REG (DR_REG_H264_DMA_BASE + 0x400)
+/** H264_DMA_OUT_AUTO_WRBACK_CH4 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define H264_DMA_OUT_AUTO_WRBACK_CH4    (BIT(0))
+#define H264_DMA_OUT_AUTO_WRBACK_CH4_M  (H264_DMA_OUT_AUTO_WRBACK_CH4_V << H264_DMA_OUT_AUTO_WRBACK_CH4_S)
+#define H264_DMA_OUT_AUTO_WRBACK_CH4_V  0x00000001U
+#define H264_DMA_OUT_AUTO_WRBACK_CH4_S  0
+/** H264_DMA_OUT_EOF_MODE_CH4 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define H264_DMA_OUT_EOF_MODE_CH4    (BIT(1))
+#define H264_DMA_OUT_EOF_MODE_CH4_M  (H264_DMA_OUT_EOF_MODE_CH4_V << H264_DMA_OUT_EOF_MODE_CH4_S)
+#define H264_DMA_OUT_EOF_MODE_CH4_V  0x00000001U
+#define H264_DMA_OUT_EOF_MODE_CH4_S  1
+/** H264_DMA_OUTDSCR_BURST_EN_CH4 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define H264_DMA_OUTDSCR_BURST_EN_CH4    (BIT(2))
+#define H264_DMA_OUTDSCR_BURST_EN_CH4_M  (H264_DMA_OUTDSCR_BURST_EN_CH4_V << H264_DMA_OUTDSCR_BURST_EN_CH4_S)
+#define H264_DMA_OUTDSCR_BURST_EN_CH4_V  0x00000001U
+#define H264_DMA_OUTDSCR_BURST_EN_CH4_S  2
+/** H264_DMA_OUT_ECC_AES_EN_CH4 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_OUT_ECC_AES_EN_CH4    (BIT(3))
+#define H264_DMA_OUT_ECC_AES_EN_CH4_M  (H264_DMA_OUT_ECC_AES_EN_CH4_V << H264_DMA_OUT_ECC_AES_EN_CH4_S)
+#define H264_DMA_OUT_ECC_AES_EN_CH4_V  0x00000001U
+#define H264_DMA_OUT_ECC_AES_EN_CH4_S  3
+/** H264_DMA_OUT_CHECK_OWNER_CH4 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_OUT_CHECK_OWNER_CH4    (BIT(4))
+#define H264_DMA_OUT_CHECK_OWNER_CH4_M  (H264_DMA_OUT_CHECK_OWNER_CH4_V << H264_DMA_OUT_CHECK_OWNER_CH4_S)
+#define H264_DMA_OUT_CHECK_OWNER_CH4_V  0x00000001U
+#define H264_DMA_OUT_CHECK_OWNER_CH4_S  4
+/** H264_DMA_OUT_MEM_BURST_LENGTH_CH4 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 4. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH4    0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH4_M  (H264_DMA_OUT_MEM_BURST_LENGTH_CH4_V << H264_DMA_OUT_MEM_BURST_LENGTH_CH4_S)
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH4_V  0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH4_S  6
+/** H264_DMA_OUT_PAGE_BOUND_EN_CH4 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH4    (BIT(12))
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH4_M  (H264_DMA_OUT_PAGE_BOUND_EN_CH4_V << H264_DMA_OUT_PAGE_BOUND_EN_CH4_S)
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH4_V  0x00000001U
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH4_S  12
+/** H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4    (BIT(26))
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4_M  (H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4_V << H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4_S)
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4_V  0x00000001U
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4_S  26
+
+/** H264_DMA_OUT_INT_RAW_CH4_REG register
+ *  TX CH4  interrupt raw register
+ */
+#define H264_DMA_OUT_INT_RAW_CH4_REG (DR_REG_H264_DMA_BASE + 0x404)
+/** H264_DMA_OUT_DONE_CH4_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define H264_DMA_OUT_DONE_CH4_INT_RAW    (BIT(0))
+#define H264_DMA_OUT_DONE_CH4_INT_RAW_M  (H264_DMA_OUT_DONE_CH4_INT_RAW_V << H264_DMA_OUT_DONE_CH4_INT_RAW_S)
+#define H264_DMA_OUT_DONE_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH4_INT_RAW_S  0
+/** H264_DMA_OUT_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define H264_DMA_OUT_EOF_CH4_INT_RAW    (BIT(1))
+#define H264_DMA_OUT_EOF_CH4_INT_RAW_M  (H264_DMA_OUT_EOF_CH4_INT_RAW_V << H264_DMA_OUT_EOF_CH4_INT_RAW_S)
+#define H264_DMA_OUT_EOF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH4_INT_RAW_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW_M  (H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW_V << H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_M  (H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_V << H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW_V << H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW_S  8
+
+/** H264_DMA_OUT_INT_ENA_CH4_REG register
+ *  TX CH4  interrupt ena register
+ */
+#define H264_DMA_OUT_INT_ENA_CH4_REG (DR_REG_H264_DMA_BASE + 0x408)
+/** H264_DMA_OUT_DONE_CH4_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH4_INT_ENA    (BIT(0))
+#define H264_DMA_OUT_DONE_CH4_INT_ENA_M  (H264_DMA_OUT_DONE_CH4_INT_ENA_V << H264_DMA_OUT_DONE_CH4_INT_ENA_S)
+#define H264_DMA_OUT_DONE_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH4_INT_ENA_S  0
+/** H264_DMA_OUT_EOF_CH4_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH4_INT_ENA    (BIT(1))
+#define H264_DMA_OUT_EOF_CH4_INT_ENA_M  (H264_DMA_OUT_EOF_CH4_INT_ENA_V << H264_DMA_OUT_EOF_CH4_INT_ENA_S)
+#define H264_DMA_OUT_EOF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH4_INT_ENA_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA_M  (H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA_V << H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_M  (H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_V << H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA_V << H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA_S  8
+
+/** H264_DMA_OUT_INT_ST_CH4_REG register
+ *  TX CH4  interrupt st register
+ */
+#define H264_DMA_OUT_INT_ST_CH4_REG (DR_REG_H264_DMA_BASE + 0x40c)
+/** H264_DMA_OUT_DONE_CH4_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH4_INT_ST    (BIT(0))
+#define H264_DMA_OUT_DONE_CH4_INT_ST_M  (H264_DMA_OUT_DONE_CH4_INT_ST_V << H264_DMA_OUT_DONE_CH4_INT_ST_S)
+#define H264_DMA_OUT_DONE_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH4_INT_ST_S  0
+/** H264_DMA_OUT_EOF_CH4_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH4_INT_ST    (BIT(1))
+#define H264_DMA_OUT_EOF_CH4_INT_ST_M  (H264_DMA_OUT_EOF_CH4_INT_ST_V << H264_DMA_OUT_EOF_CH4_INT_ST_S)
+#define H264_DMA_OUT_EOF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH4_INT_ST_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH4_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ST    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ST_M  (H264_DMA_OUT_DSCR_ERR_CH4_INT_ST_V << H264_DMA_OUT_DSCR_ERR_CH4_INT_ST_S)
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ST_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST_M  (H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST_V << H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST_V << H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST_V << H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST_V << H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST_V << H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST_V << H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST_S  8
+
+/** H264_DMA_OUT_INT_CLR_CH4_REG register
+ *  TX CH4  interrupt clr register
+ */
+#define H264_DMA_OUT_INT_CLR_CH4_REG (DR_REG_H264_DMA_BASE + 0x410)
+/** H264_DMA_OUT_DONE_CH4_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH4_INT_CLR    (BIT(0))
+#define H264_DMA_OUT_DONE_CH4_INT_CLR_M  (H264_DMA_OUT_DONE_CH4_INT_CLR_V << H264_DMA_OUT_DONE_CH4_INT_CLR_S)
+#define H264_DMA_OUT_DONE_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH4_INT_CLR_S  0
+/** H264_DMA_OUT_EOF_CH4_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH4_INT_CLR    (BIT(1))
+#define H264_DMA_OUT_EOF_CH4_INT_CLR_M  (H264_DMA_OUT_EOF_CH4_INT_CLR_V << H264_DMA_OUT_EOF_CH4_INT_CLR_S)
+#define H264_DMA_OUT_EOF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH4_INT_CLR_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR_M  (H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR_V << H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_M  (H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_V << H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR_V << H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR_S  8
+
+/** H264_DMA_OUTFIFO_STATUS_CH4_REG register
+ *  TX CH4 outfifo status register
+ */
+#define H264_DMA_OUTFIFO_STATUS_CH4_REG (DR_REG_H264_DMA_BASE + 0x414)
+/** H264_DMA_OUTFIFO_FULL_L2_CH4 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L2_CH4    (BIT(0))
+#define H264_DMA_OUTFIFO_FULL_L2_CH4_M  (H264_DMA_OUTFIFO_FULL_L2_CH4_V << H264_DMA_OUTFIFO_FULL_L2_CH4_S)
+#define H264_DMA_OUTFIFO_FULL_L2_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L2_CH4_S  0
+/** H264_DMA_OUTFIFO_EMPTY_L2_CH4 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH4    (BIT(1))
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH4_M  (H264_DMA_OUTFIFO_EMPTY_L2_CH4_V << H264_DMA_OUTFIFO_EMPTY_L2_CH4_S)
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH4_S  1
+/** H264_DMA_OUTFIFO_CNT_L2_CH4 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L2_CH4    0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH4_M  (H264_DMA_OUTFIFO_CNT_L2_CH4_V << H264_DMA_OUTFIFO_CNT_L2_CH4_S)
+#define H264_DMA_OUTFIFO_CNT_L2_CH4_V  0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH4_S  2
+/** H264_DMA_OUTFIFO_FULL_L1_CH4 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L1_CH4    (BIT(6))
+#define H264_DMA_OUTFIFO_FULL_L1_CH4_M  (H264_DMA_OUTFIFO_FULL_L1_CH4_V << H264_DMA_OUTFIFO_FULL_L1_CH4_S)
+#define H264_DMA_OUTFIFO_FULL_L1_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L1_CH4_S  6
+/** H264_DMA_OUTFIFO_EMPTY_L1_CH4 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH4    (BIT(7))
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH4_M  (H264_DMA_OUTFIFO_EMPTY_L1_CH4_V << H264_DMA_OUTFIFO_EMPTY_L1_CH4_S)
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH4_S  7
+/** H264_DMA_OUTFIFO_CNT_L1_CH4 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L1_CH4    0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH4_M  (H264_DMA_OUTFIFO_CNT_L1_CH4_V << H264_DMA_OUTFIFO_CNT_L1_CH4_S)
+#define H264_DMA_OUTFIFO_CNT_L1_CH4_V  0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH4_S  8
+/** H264_DMA_OUTFIFO_FULL_L3_CH4 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L3_CH4    (BIT(16))
+#define H264_DMA_OUTFIFO_FULL_L3_CH4_M  (H264_DMA_OUTFIFO_FULL_L3_CH4_V << H264_DMA_OUTFIFO_FULL_L3_CH4_S)
+#define H264_DMA_OUTFIFO_FULL_L3_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L3_CH4_S  16
+/** H264_DMA_OUTFIFO_EMPTY_L3_CH4 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH4    (BIT(17))
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH4_M  (H264_DMA_OUTFIFO_EMPTY_L3_CH4_V << H264_DMA_OUTFIFO_EMPTY_L3_CH4_S)
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH4_S  17
+/** H264_DMA_OUTFIFO_CNT_L3_CH4 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L3_CH4    0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH4_M  (H264_DMA_OUTFIFO_CNT_L3_CH4_V << H264_DMA_OUTFIFO_CNT_L3_CH4_S)
+#define H264_DMA_OUTFIFO_CNT_L3_CH4_V  0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH4_S  18
+
+/** H264_DMA_OUT_PUSH_CH4_REG register
+ *  TX CH4 outfifo push register
+ */
+#define H264_DMA_OUT_PUSH_CH4_REG (DR_REG_H264_DMA_BASE + 0x418)
+/** H264_DMA_OUTFIFO_WDATA_CH4 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_WDATA_CH4    0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH4_M  (H264_DMA_OUTFIFO_WDATA_CH4_V << H264_DMA_OUTFIFO_WDATA_CH4_S)
+#define H264_DMA_OUTFIFO_WDATA_CH4_V  0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH4_S  0
+/** H264_DMA_OUTFIFO_PUSH_CH4 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_PUSH_CH4    (BIT(10))
+#define H264_DMA_OUTFIFO_PUSH_CH4_M  (H264_DMA_OUTFIFO_PUSH_CH4_V << H264_DMA_OUTFIFO_PUSH_CH4_S)
+#define H264_DMA_OUTFIFO_PUSH_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_PUSH_CH4_S  10
+
+/** H264_DMA_OUT_LINK_CONF_CH4_REG register
+ *  TX CH4 out_link dscr ctrl register
+ */
+#define H264_DMA_OUT_LINK_CONF_CH4_REG (DR_REG_H264_DMA_BASE + 0x41c)
+/** H264_DMA_OUTLINK_STOP_CH4 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_STOP_CH4    (BIT(20))
+#define H264_DMA_OUTLINK_STOP_CH4_M  (H264_DMA_OUTLINK_STOP_CH4_V << H264_DMA_OUTLINK_STOP_CH4_S)
+#define H264_DMA_OUTLINK_STOP_CH4_V  0x00000001U
+#define H264_DMA_OUTLINK_STOP_CH4_S  20
+/** H264_DMA_OUTLINK_START_CH4 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_START_CH4    (BIT(21))
+#define H264_DMA_OUTLINK_START_CH4_M  (H264_DMA_OUTLINK_START_CH4_V << H264_DMA_OUTLINK_START_CH4_S)
+#define H264_DMA_OUTLINK_START_CH4_V  0x00000001U
+#define H264_DMA_OUTLINK_START_CH4_S  21
+/** H264_DMA_OUTLINK_RESTART_CH4 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define H264_DMA_OUTLINK_RESTART_CH4    (BIT(22))
+#define H264_DMA_OUTLINK_RESTART_CH4_M  (H264_DMA_OUTLINK_RESTART_CH4_V << H264_DMA_OUTLINK_RESTART_CH4_S)
+#define H264_DMA_OUTLINK_RESTART_CH4_V  0x00000001U
+#define H264_DMA_OUTLINK_RESTART_CH4_S  22
+/** H264_DMA_OUTLINK_PARK_CH4 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define H264_DMA_OUTLINK_PARK_CH4    (BIT(23))
+#define H264_DMA_OUTLINK_PARK_CH4_M  (H264_DMA_OUTLINK_PARK_CH4_V << H264_DMA_OUTLINK_PARK_CH4_S)
+#define H264_DMA_OUTLINK_PARK_CH4_V  0x00000001U
+#define H264_DMA_OUTLINK_PARK_CH4_S  23
+
+/** H264_DMA_OUT_LINK_ADDR_CH4_REG register
+ *  TX CH4 out_link dscr addr register
+ */
+#define H264_DMA_OUT_LINK_ADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x420)
+/** H264_DMA_OUTLINK_ADDR_CH4 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_ADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH4_M  (H264_DMA_OUTLINK_ADDR_CH4_V << H264_DMA_OUTLINK_ADDR_CH4_S)
+#define H264_DMA_OUTLINK_ADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH4_S  0
+
+/** H264_DMA_OUT_STATE_CH4_REG register
+ *  TX CH4 state register
+ */
+#define H264_DMA_OUT_STATE_CH4_REG (DR_REG_H264_DMA_BASE + 0x424)
+/** H264_DMA_OUTLINK_DSCR_ADDR_CH4 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH4    0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH4_M  (H264_DMA_OUTLINK_DSCR_ADDR_CH4_V << H264_DMA_OUTLINK_DSCR_ADDR_CH4_S)
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH4_V  0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH4_S  0
+/** H264_DMA_OUT_DSCR_STATE_CH4 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_OUT_DSCR_STATE_CH4    0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH4_M  (H264_DMA_OUT_DSCR_STATE_CH4_V << H264_DMA_OUT_DSCR_STATE_CH4_S)
+#define H264_DMA_OUT_DSCR_STATE_CH4_V  0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH4_S  18
+/** H264_DMA_OUT_STATE_CH4 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_OUT_STATE_CH4    0x0000000FU
+#define H264_DMA_OUT_STATE_CH4_M  (H264_DMA_OUT_STATE_CH4_V << H264_DMA_OUT_STATE_CH4_S)
+#define H264_DMA_OUT_STATE_CH4_V  0x0000000FU
+#define H264_DMA_OUT_STATE_CH4_S  20
+
+/** H264_DMA_OUT_EOF_DES_ADDR_CH4_REG register
+ *  TX CH4 eof des addr register
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x428)
+/** H264_DMA_OUT_EOF_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH4_M  (H264_DMA_OUT_EOF_DES_ADDR_CH4_V << H264_DMA_OUT_EOF_DES_ADDR_CH4_S)
+#define H264_DMA_OUT_EOF_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH4_S  0
+
+/** H264_DMA_OUT_DSCR_CH4_REG register
+ *  TX CH4 next dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_CH4_REG (DR_REG_H264_DMA_BASE + 0x42c)
+/** H264_DMA_OUTLINK_DSCR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define H264_DMA_OUTLINK_DSCR_CH4    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH4_M  (H264_DMA_OUTLINK_DSCR_CH4_V << H264_DMA_OUTLINK_DSCR_CH4_S)
+#define H264_DMA_OUTLINK_DSCR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH4_S  0
+
+/** H264_DMA_OUT_DSCR_BF0_CH4_REG register
+ *  TX CH4 last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF0_CH4_REG (DR_REG_H264_DMA_BASE + 0x430)
+/** H264_DMA_OUTLINK_DSCR_BF0_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF0_CH4    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH4_M  (H264_DMA_OUTLINK_DSCR_BF0_CH4_V << H264_DMA_OUTLINK_DSCR_BF0_CH4_S)
+#define H264_DMA_OUTLINK_DSCR_BF0_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH4_S  0
+
+/** H264_DMA_OUT_DSCR_BF1_CH4_REG register
+ *  TX CH4 second-to-last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF1_CH4_REG (DR_REG_H264_DMA_BASE + 0x434)
+/** H264_DMA_OUTLINK_DSCR_BF1_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF1_CH4    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH4_M  (H264_DMA_OUTLINK_DSCR_BF1_CH4_V << H264_DMA_OUTLINK_DSCR_BF1_CH4_S)
+#define H264_DMA_OUTLINK_DSCR_BF1_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH4_S  0
+
+/** H264_DMA_OUT_ARB_CH4_REG register
+ *  TX CH4 arb register
+ */
+#define H264_DMA_OUT_ARB_CH4_REG (DR_REG_H264_DMA_BASE + 0x43c)
+/** H264_DMA_OUT_ARB_TOKEN_NUM_CH4 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH4    0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH4_M  (H264_DMA_OUT_ARB_TOKEN_NUM_CH4_V << H264_DMA_OUT_ARB_TOKEN_NUM_CH4_S)
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH4_V  0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH4_S  0
+/** H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4    0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4_M  (H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4_V << H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4_S)
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4_V  0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4_S  4
+
+/** H264_DMA_OUT_ETM_CONF_CH4_REG register
+ *  TX CH4 ETM config register
+ */
+#define H264_DMA_OUT_ETM_CONF_CH4_REG (DR_REG_H264_DMA_BASE + 0x468)
+/** H264_DMA_OUT_ETM_EN_CH4 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_OUT_ETM_EN_CH4    (BIT(0))
+#define H264_DMA_OUT_ETM_EN_CH4_M  (H264_DMA_OUT_ETM_EN_CH4_V << H264_DMA_OUT_ETM_EN_CH4_S)
+#define H264_DMA_OUT_ETM_EN_CH4_V  0x00000001U
+#define H264_DMA_OUT_ETM_EN_CH4_S  0
+/** H264_DMA_OUT_ETM_LOOP_EN_CH4 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_OUT_ETM_LOOP_EN_CH4    (BIT(1))
+#define H264_DMA_OUT_ETM_LOOP_EN_CH4_M  (H264_DMA_OUT_ETM_LOOP_EN_CH4_V << H264_DMA_OUT_ETM_LOOP_EN_CH4_S)
+#define H264_DMA_OUT_ETM_LOOP_EN_CH4_V  0x00000001U
+#define H264_DMA_OUT_ETM_LOOP_EN_CH4_S  1
+/** H264_DMA_OUT_DSCR_TASK_MAK_CH4 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH4    0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH4_M  (H264_DMA_OUT_DSCR_TASK_MAK_CH4_V << H264_DMA_OUT_DSCR_TASK_MAK_CH4_S)
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH4_V  0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH4_S  2
+
+/** H264_DMA_OUT_BUF_LEN_CH4_REG register
+ *  tx CH4 buf len register
+ */
+#define H264_DMA_OUT_BUF_LEN_CH4_REG (DR_REG_H264_DMA_BASE + 0x470)
+/** H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4    0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4_M  (H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4_V << H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4_S)
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4_V  0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4_S  0
+
+/** H264_DMA_OUT_FIFO_BCNT_CH4_REG register
+ *  tx CH4 fifo byte cnt register
+ */
+#define H264_DMA_OUT_FIFO_BCNT_CH4_REG (DR_REG_H264_DMA_BASE + 0x474)
+/** H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4    0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_M  (H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_V << H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_S)
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_V  0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_S  0
+
+/** H264_DMA_OUT_PUSH_BYTECNT_CH4_REG register
+ *  tx CH4 push byte cnt register
+ */
+#define H264_DMA_OUT_PUSH_BYTECNT_CH4_REG (DR_REG_H264_DMA_BASE + 0x478)
+/** H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4 : RO; bitpos: [7:0]; default: 63;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4    0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4_M  (H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4_V << H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4_S)
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4_V  0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4_S  0
+
+/** H264_DMA_OUT_XADDR_CH4_REG register
+ *  tx CH4 xaddr register
+ */
+#define H264_DMA_OUT_XADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x47c)
+/** H264_DMA_OUT_CMDFIFO_XADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH4_M  (H264_DMA_OUT_CMDFIFO_XADDR_CH4_V << H264_DMA_OUT_CMDFIFO_XADDR_CH4_S)
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH4_S  0
+
+/** H264_DMA_OUT_BLOCK_BUF_LEN_CH4_REG register
+ *  tx CH4 block buf len register
+ */
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH4_REG (DR_REG_H264_DMA_BASE + 0x480)
+/** H264_DMA_OUT_BLOCK_BUF_LEN_CH4 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH4    0x0FFFFFFFU
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH4_M  (H264_DMA_OUT_BLOCK_BUF_LEN_CH4_V << H264_DMA_OUT_BLOCK_BUF_LEN_CH4_S)
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH4_V  0x0FFFFFFFU
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH4_S  0
+
+/** H264_DMA_IN_CONF0_CH0_REG register
+ *  RX CH0 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH0_REG (DR_REG_H264_DMA_BASE + 0x500)
+/** H264_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define H264_DMA_INDSCR_BURST_EN_CH0    (BIT(2))
+#define H264_DMA_INDSCR_BURST_EN_CH0_M  (H264_DMA_INDSCR_BURST_EN_CH0_V << H264_DMA_INDSCR_BURST_EN_CH0_S)
+#define H264_DMA_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define H264_DMA_INDSCR_BURST_EN_CH0_S  2
+/** H264_DMA_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH0    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH0_M  (H264_DMA_IN_ECC_AES_EN_CH0_V << H264_DMA_IN_ECC_AES_EN_CH0_S)
+#define H264_DMA_IN_ECC_AES_EN_CH0_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH0_S  3
+/** H264_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_IN_CHECK_OWNER_CH0    (BIT(4))
+#define H264_DMA_IN_CHECK_OWNER_CH0_M  (H264_DMA_IN_CHECK_OWNER_CH0_V << H264_DMA_IN_CHECK_OWNER_CH0_S)
+#define H264_DMA_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define H264_DMA_IN_CHECK_OWNER_CH0_S  4
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH0    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH0_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH0_V << H264_DMA_IN_MEM_BURST_LENGTH_CH0_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH0_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH0    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH0_M  (H264_DMA_IN_PAGE_BOUND_EN_CH0_V << H264_DMA_IN_PAGE_BOUND_EN_CH0_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH0_S  12
+/** H264_DMA_IN_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH0    (BIT(24))
+#define H264_DMA_IN_RST_CH0_M  (H264_DMA_IN_RST_CH0_V << H264_DMA_IN_RST_CH0_S)
+#define H264_DMA_IN_RST_CH0_V  0x00000001U
+#define H264_DMA_IN_RST_CH0_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH0    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH0_M  (H264_DMA_IN_CMD_DISABLE_CH0_V << H264_DMA_IN_CMD_DISABLE_CH0_S)
+#define H264_DMA_IN_CMD_DISABLE_CH0_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH0_S  25
+/** H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0_M  (H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0_V << H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** H264_DMA_IN_INT_RAW_CH0_REG register
+ *  RX CH0  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH0_REG (DR_REG_H264_DMA_BASE + 0x504)
+/** H264_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define H264_DMA_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH0_INT_RAW_M  (H264_DMA_IN_DONE_CH0_INT_RAW_V << H264_DMA_IN_DONE_CH0_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH0_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define H264_DMA_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH0_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH0_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH0_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** H264_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define H264_DMA_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH0_INT_RAW_M  (H264_DMA_IN_ERR_EOF_CH0_INT_RAW_V << H264_DMA_IN_ERR_EOF_CH0_INT_RAW_S)
+#define H264_DMA_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** H264_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_RAW_M  (H264_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << H264_DMA_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW_M  (H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW_V << H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW_M  (H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW_V << H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW_M  (H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW_S  9
+
+/** H264_DMA_IN_INT_ENA_CH0_REG register
+ *  RX CH0  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH0_REG (DR_REG_H264_DMA_BASE + 0x508)
+/** H264_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH0_INT_ENA_M  (H264_DMA_IN_DONE_CH0_INT_ENA_V << H264_DMA_IN_DONE_CH0_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH0_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH0_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH0_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** H264_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ENA_M  (H264_DMA_IN_ERR_EOF_CH0_INT_ENA_V << H264_DMA_IN_ERR_EOF_CH0_INT_ENA_S)
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** H264_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ENA_M  (H264_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << H264_DMA_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA_M  (H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA_V << H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA_M  (H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA_V << H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA_M  (H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA_S  9
+
+/** H264_DMA_IN_INT_ST_CH0_REG register
+ *  RX CH0  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH0_REG (DR_REG_H264_DMA_BASE + 0x50c)
+/** H264_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH0_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH0_INT_ST_M  (H264_DMA_IN_DONE_CH0_INT_ST_V << H264_DMA_IN_DONE_CH0_INT_ST_S)
+#define H264_DMA_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH0_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH0_INT_ST_V << H264_DMA_IN_SUC_EOF_CH0_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ST_S  1
+/** H264_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ST_M  (H264_DMA_IN_ERR_EOF_CH0_INT_ST_V << H264_DMA_IN_ERR_EOF_CH0_INT_ST_S)
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ST_S  2
+/** H264_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ST_M  (H264_DMA_IN_DSCR_ERR_CH0_INT_ST_V << H264_DMA_IN_DSCR_ERR_CH0_INT_ST_S)
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH0_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH0_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ST_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH0_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH0_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ST_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ST_M  (H264_DMA_INFIFO_OVF_L2_CH0_INT_ST_V << H264_DMA_INFIFO_OVF_L2_CH0_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ST_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ST_M  (H264_DMA_INFIFO_UDF_L2_CH0_INT_ST_V << H264_DMA_INFIFO_UDF_L2_CH0_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ST_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST_M  (H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST_V << H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST_S  9
+
+/** H264_DMA_IN_INT_CLR_CH0_REG register
+ *  RX CH0  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH0_REG (DR_REG_H264_DMA_BASE + 0x510)
+/** H264_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH0_INT_CLR_M  (H264_DMA_IN_DONE_CH0_INT_CLR_V << H264_DMA_IN_DONE_CH0_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH0_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH0_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH0_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH0_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** H264_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH0_INT_CLR_M  (H264_DMA_IN_ERR_EOF_CH0_INT_CLR_V << H264_DMA_IN_ERR_EOF_CH0_INT_CLR_S)
+#define H264_DMA_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** H264_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_CLR_M  (H264_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << H264_DMA_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR_M  (H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR_V << H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR_M  (H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR_V << H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR_M  (H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR_S  9
+
+/** H264_DMA_INFIFO_STATUS_CH0_REG register
+ *  RX CH0 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH0_REG (DR_REG_H264_DMA_BASE + 0x514)
+/** H264_DMA_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_FULL_L2_CH0    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L2_CH0_M  (H264_DMA_INFIFO_FULL_L2_CH0_V << H264_DMA_INFIFO_FULL_L2_CH0_S)
+#define H264_DMA_INFIFO_FULL_L2_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L2_CH0_S  0
+/** H264_DMA_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_EMPTY_L2_CH0    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L2_CH0_M  (H264_DMA_INFIFO_EMPTY_L2_CH0_V << H264_DMA_INFIFO_EMPTY_L2_CH0_S)
+#define H264_DMA_INFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L2_CH0_S  1
+/** H264_DMA_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define H264_DMA_INFIFO_CNT_L2_CH0    0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH0_M  (H264_DMA_INFIFO_CNT_L2_CH0_V << H264_DMA_INFIFO_CNT_L2_CH0_S)
+#define H264_DMA_INFIFO_CNT_L2_CH0_V  0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH0_S  2
+/** H264_DMA_INFIFO_FULL_L1_CH0 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH0    (BIT(6))
+#define H264_DMA_INFIFO_FULL_L1_CH0_M  (H264_DMA_INFIFO_FULL_L1_CH0_V << H264_DMA_INFIFO_FULL_L1_CH0_S)
+#define H264_DMA_INFIFO_FULL_L1_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH0_S  6
+/** H264_DMA_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH0    (BIT(7))
+#define H264_DMA_INFIFO_EMPTY_L1_CH0_M  (H264_DMA_INFIFO_EMPTY_L1_CH0_V << H264_DMA_INFIFO_EMPTY_L1_CH0_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH0_S  7
+/** H264_DMA_INFIFO_CNT_L1_CH0 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH0    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH0_M  (H264_DMA_INFIFO_CNT_L1_CH0_V << H264_DMA_INFIFO_CNT_L1_CH0_S)
+#define H264_DMA_INFIFO_CNT_L1_CH0_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH0_S  8
+/** H264_DMA_INFIFO_FULL_L3_CH0 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_FULL_L3_CH0    (BIT(16))
+#define H264_DMA_INFIFO_FULL_L3_CH0_M  (H264_DMA_INFIFO_FULL_L3_CH0_V << H264_DMA_INFIFO_FULL_L3_CH0_S)
+#define H264_DMA_INFIFO_FULL_L3_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L3_CH0_S  16
+/** H264_DMA_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_EMPTY_L3_CH0    (BIT(17))
+#define H264_DMA_INFIFO_EMPTY_L3_CH0_M  (H264_DMA_INFIFO_EMPTY_L3_CH0_V << H264_DMA_INFIFO_EMPTY_L3_CH0_S)
+#define H264_DMA_INFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L3_CH0_S  17
+/** H264_DMA_INFIFO_CNT_L3_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_CNT_L3_CH0    0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH0_M  (H264_DMA_INFIFO_CNT_L3_CH0_V << H264_DMA_INFIFO_CNT_L3_CH0_S)
+#define H264_DMA_INFIFO_CNT_L3_CH0_V  0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH0_S  18
+
+/** H264_DMA_IN_POP_CH0_REG register
+ *  RX CH0 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH0_REG (DR_REG_H264_DMA_BASE + 0x518)
+/** H264_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH0    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH0_M  (H264_DMA_INFIFO_RDATA_CH0_V << H264_DMA_INFIFO_RDATA_CH0_S)
+#define H264_DMA_INFIFO_RDATA_CH0_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH0_S  0
+/** H264_DMA_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH0    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH0_M  (H264_DMA_INFIFO_POP_CH0_V << H264_DMA_INFIFO_POP_CH0_S)
+#define H264_DMA_INFIFO_POP_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH0_S  11
+
+/** H264_DMA_IN_LINK_CONF_CH0_REG register
+ *  RX CH0 in_link dscr ctrl register
+ */
+#define H264_DMA_IN_LINK_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x51c)
+/** H264_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_INLINK_AUTO_RET_CH0    (BIT(20))
+#define H264_DMA_INLINK_AUTO_RET_CH0_M  (H264_DMA_INLINK_AUTO_RET_CH0_V << H264_DMA_INLINK_AUTO_RET_CH0_S)
+#define H264_DMA_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define H264_DMA_INLINK_AUTO_RET_CH0_S  20
+/** H264_DMA_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_STOP_CH0    (BIT(21))
+#define H264_DMA_INLINK_STOP_CH0_M  (H264_DMA_INLINK_STOP_CH0_V << H264_DMA_INLINK_STOP_CH0_S)
+#define H264_DMA_INLINK_STOP_CH0_V  0x00000001U
+#define H264_DMA_INLINK_STOP_CH0_S  21
+/** H264_DMA_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_START_CH0    (BIT(22))
+#define H264_DMA_INLINK_START_CH0_M  (H264_DMA_INLINK_START_CH0_V << H264_DMA_INLINK_START_CH0_S)
+#define H264_DMA_INLINK_START_CH0_V  0x00000001U
+#define H264_DMA_INLINK_START_CH0_S  22
+/** H264_DMA_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define H264_DMA_INLINK_RESTART_CH0    (BIT(23))
+#define H264_DMA_INLINK_RESTART_CH0_M  (H264_DMA_INLINK_RESTART_CH0_V << H264_DMA_INLINK_RESTART_CH0_S)
+#define H264_DMA_INLINK_RESTART_CH0_V  0x00000001U
+#define H264_DMA_INLINK_RESTART_CH0_S  23
+/** H264_DMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define H264_DMA_INLINK_PARK_CH0    (BIT(24))
+#define H264_DMA_INLINK_PARK_CH0_M  (H264_DMA_INLINK_PARK_CH0_V << H264_DMA_INLINK_PARK_CH0_S)
+#define H264_DMA_INLINK_PARK_CH0_V  0x00000001U
+#define H264_DMA_INLINK_PARK_CH0_S  24
+
+/** H264_DMA_IN_LINK_ADDR_CH0_REG register
+ *  RX CH0 in_link dscr addr register
+ */
+#define H264_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x520)
+/** H264_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH0_M  (H264_DMA_INLINK_ADDR_CH0_V << H264_DMA_INLINK_ADDR_CH0_S)
+#define H264_DMA_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH0_S  0
+
+/** H264_DMA_IN_STATE_CH0_REG register
+ *  RX CH0 state register
+ */
+#define H264_DMA_IN_STATE_CH0_REG (DR_REG_H264_DMA_BASE + 0x524)
+/** H264_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH0_M  (H264_DMA_INLINK_DSCR_ADDR_CH0_V << H264_DMA_INLINK_DSCR_ADDR_CH0_S)
+#define H264_DMA_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH0_S  0
+/** H264_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_IN_DSCR_STATE_CH0    0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH0_M  (H264_DMA_IN_DSCR_STATE_CH0_V << H264_DMA_IN_DSCR_STATE_CH0_S)
+#define H264_DMA_IN_DSCR_STATE_CH0_V  0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH0_S  18
+/** H264_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH0    0x00000007U
+#define H264_DMA_IN_STATE_CH0_M  (H264_DMA_IN_STATE_CH0_V << H264_DMA_IN_STATE_CH0_S)
+#define H264_DMA_IN_STATE_CH0_V  0x00000007U
+#define H264_DMA_IN_STATE_CH0_S  20
+/** H264_DMA_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH0    (BIT(23))
+#define H264_DMA_IN_RESET_AVAIL_CH0_M  (H264_DMA_IN_RESET_AVAIL_CH0_V << H264_DMA_IN_RESET_AVAIL_CH0_S)
+#define H264_DMA_IN_RESET_AVAIL_CH0_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH0_S  23
+
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  RX CH0 eof des addr register
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x528)
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_M  (H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_V << H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  RX CH0 err eof des addr register
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x52c)
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_M  (H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** H264_DMA_IN_DSCR_CH0_REG register
+ *  RX CH0 next dscr addr register
+ */
+#define H264_DMA_IN_DSCR_CH0_REG (DR_REG_H264_DMA_BASE + 0x530)
+/** H264_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define H264_DMA_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH0_M  (H264_DMA_INLINK_DSCR_CH0_V << H264_DMA_INLINK_DSCR_CH0_S)
+#define H264_DMA_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH0_S  0
+
+/** H264_DMA_IN_DSCR_BF0_CH0_REG register
+ *  RX CH0 last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_H264_DMA_BASE + 0x534)
+/** H264_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define H264_DMA_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH0_M  (H264_DMA_INLINK_DSCR_BF0_CH0_V << H264_DMA_INLINK_DSCR_BF0_CH0_S)
+#define H264_DMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH0_S  0
+
+/** H264_DMA_IN_DSCR_BF1_CH0_REG register
+ *  RX CH0 second-to-last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_H264_DMA_BASE + 0x538)
+/** H264_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define H264_DMA_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH0_M  (H264_DMA_INLINK_DSCR_BF1_CH0_V << H264_DMA_INLINK_DSCR_BF1_CH0_S)
+#define H264_DMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH0_S  0
+
+/** H264_DMA_IN_ARB_CH0_REG register
+ *  RX CH0 arb register
+ */
+#define H264_DMA_IN_ARB_CH0_REG (DR_REG_H264_DMA_BASE + 0x540)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH0_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH0_V << H264_DMA_IN_ARB_TOKEN_NUM_CH0_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH0_S  0
+/** H264_DMA_EXTER_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH0    0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH0_M  (H264_DMA_EXTER_IN_ARB_PRIORITY_CH0_V << H264_DMA_EXTER_IN_ARB_PRIORITY_CH0_S)
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH0_V  0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH0_S  4
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH0    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH0_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH0_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH0_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH0_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH0_S  6
+
+/** H264_DMA_IN_RO_PD_CONF_CH0_REG register
+ *  RX CH0 reorder power config register
+ */
+#define H264_DMA_IN_RO_PD_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x548)
+/** H264_DMA_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define H264_DMA_IN_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define H264_DMA_IN_RO_RAM_CLK_FO_CH0_M  (H264_DMA_IN_RO_RAM_CLK_FO_CH0_V << H264_DMA_IN_RO_RAM_CLK_FO_CH0_S)
+#define H264_DMA_IN_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define H264_DMA_IN_RO_RAM_CLK_FO_CH0_S  6
+
+/** H264_DMA_IN_ETM_CONF_CH0_REG register
+ *  RX CH0 ETM config register
+ */
+#define H264_DMA_IN_ETM_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x56c)
+/** H264_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_IN_ETM_EN_CH0    (BIT(0))
+#define H264_DMA_IN_ETM_EN_CH0_M  (H264_DMA_IN_ETM_EN_CH0_V << H264_DMA_IN_ETM_EN_CH0_S)
+#define H264_DMA_IN_ETM_EN_CH0_V  0x00000001U
+#define H264_DMA_IN_ETM_EN_CH0_S  0
+/** H264_DMA_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_IN_ETM_LOOP_EN_CH0    (BIT(1))
+#define H264_DMA_IN_ETM_LOOP_EN_CH0_M  (H264_DMA_IN_ETM_LOOP_EN_CH0_V << H264_DMA_IN_ETM_LOOP_EN_CH0_S)
+#define H264_DMA_IN_ETM_LOOP_EN_CH0_V  0x00000001U
+#define H264_DMA_IN_ETM_LOOP_EN_CH0_S  1
+/** H264_DMA_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_IN_DSCR_TASK_MAK_CH0    0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH0_M  (H264_DMA_IN_DSCR_TASK_MAK_CH0_V << H264_DMA_IN_DSCR_TASK_MAK_CH0_S)
+#define H264_DMA_IN_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH0_S  2
+
+/** H264_DMA_IN_FIFO_CNT_CH0_REG register
+ *  rx CH0 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH0_REG (DR_REG_H264_DMA_BASE + 0x580)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH0_REG register
+ *  rx CH0 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH0_REG (DR_REG_H264_DMA_BASE + 0x584)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0 : RO; bitpos: [7:0]; default: 7;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0_S  0
+
+/** H264_DMA_IN_XADDR_CH0_REG register
+ *  rx CH0 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x588)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH0_M  (H264_DMA_IN_CMDFIFO_XADDR_CH0_V << H264_DMA_IN_CMDFIFO_XADDR_CH0_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH0_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH0_REG register
+ *  rx CH0 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH0_REG (DR_REG_H264_DMA_BASE + 0x58c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0_S  0
+
+/** H264_DMA_IN_CONF0_CH1_REG register
+ *  RX CH1 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH1_REG (DR_REG_H264_DMA_BASE + 0x600)
+/** H264_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define H264_DMA_INDSCR_BURST_EN_CH1    (BIT(2))
+#define H264_DMA_INDSCR_BURST_EN_CH1_M  (H264_DMA_INDSCR_BURST_EN_CH1_V << H264_DMA_INDSCR_BURST_EN_CH1_S)
+#define H264_DMA_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define H264_DMA_INDSCR_BURST_EN_CH1_S  2
+/** H264_DMA_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH1    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH1_M  (H264_DMA_IN_ECC_AES_EN_CH1_V << H264_DMA_IN_ECC_AES_EN_CH1_S)
+#define H264_DMA_IN_ECC_AES_EN_CH1_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH1_S  3
+/** H264_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_IN_CHECK_OWNER_CH1    (BIT(4))
+#define H264_DMA_IN_CHECK_OWNER_CH1_M  (H264_DMA_IN_CHECK_OWNER_CH1_V << H264_DMA_IN_CHECK_OWNER_CH1_S)
+#define H264_DMA_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define H264_DMA_IN_CHECK_OWNER_CH1_S  4
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH1    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH1_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH1_V << H264_DMA_IN_MEM_BURST_LENGTH_CH1_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH1_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH1    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH1_M  (H264_DMA_IN_PAGE_BOUND_EN_CH1_V << H264_DMA_IN_PAGE_BOUND_EN_CH1_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH1_S  12
+/** H264_DMA_IN_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH1    (BIT(24))
+#define H264_DMA_IN_RST_CH1_M  (H264_DMA_IN_RST_CH1_V << H264_DMA_IN_RST_CH1_S)
+#define H264_DMA_IN_RST_CH1_V  0x00000001U
+#define H264_DMA_IN_RST_CH1_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH1    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH1_M  (H264_DMA_IN_CMD_DISABLE_CH1_V << H264_DMA_IN_CMD_DISABLE_CH1_S)
+#define H264_DMA_IN_CMD_DISABLE_CH1_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH1_S  25
+/** H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1_M  (H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1_V << H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** H264_DMA_IN_INT_RAW_CH1_REG register
+ *  RX CH1  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH1_REG (DR_REG_H264_DMA_BASE + 0x604)
+/** H264_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 1.
+ */
+#define H264_DMA_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH1_INT_RAW_M  (H264_DMA_IN_DONE_CH1_INT_RAW_V << H264_DMA_IN_DONE_CH1_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH1_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 1.
+ */
+#define H264_DMA_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH1_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH1_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH1_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** H264_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define H264_DMA_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH1_INT_RAW_M  (H264_DMA_IN_ERR_EOF_CH1_INT_RAW_V << H264_DMA_IN_ERR_EOF_CH1_INT_RAW_S)
+#define H264_DMA_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** H264_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 1.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_RAW_M  (H264_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << H264_DMA_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW_M  (H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW_V << H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW_M  (H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW_V << H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M  (H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW_M  (H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW_S  9
+
+/** H264_DMA_IN_INT_ENA_CH1_REG register
+ *  RX CH1  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH1_REG (DR_REG_H264_DMA_BASE + 0x608)
+/** H264_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH1_INT_ENA_M  (H264_DMA_IN_DONE_CH1_INT_ENA_V << H264_DMA_IN_DONE_CH1_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH1_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH1_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH1_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** H264_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ENA_M  (H264_DMA_IN_ERR_EOF_CH1_INT_ENA_V << H264_DMA_IN_ERR_EOF_CH1_INT_ENA_S)
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** H264_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ENA_M  (H264_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << H264_DMA_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA_M  (H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA_V << H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA_M  (H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA_V << H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M  (H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA_M  (H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA_S  9
+
+/** H264_DMA_IN_INT_ST_CH1_REG register
+ *  RX CH1  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH1_REG (DR_REG_H264_DMA_BASE + 0x60c)
+/** H264_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH1_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH1_INT_ST_M  (H264_DMA_IN_DONE_CH1_INT_ST_V << H264_DMA_IN_DONE_CH1_INT_ST_S)
+#define H264_DMA_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH1_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH1_INT_ST_V << H264_DMA_IN_SUC_EOF_CH1_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ST_S  1
+/** H264_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ST_M  (H264_DMA_IN_ERR_EOF_CH1_INT_ST_V << H264_DMA_IN_ERR_EOF_CH1_INT_ST_S)
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ST_S  2
+/** H264_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ST_M  (H264_DMA_IN_DSCR_ERR_CH1_INT_ST_V << H264_DMA_IN_DSCR_ERR_CH1_INT_ST_S)
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH1_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH1_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ST_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH1_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH1_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ST_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ST_M  (H264_DMA_INFIFO_OVF_L2_CH1_INT_ST_V << H264_DMA_INFIFO_OVF_L2_CH1_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ST_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ST_M  (H264_DMA_INFIFO_UDF_L2_CH1_INT_ST_V << H264_DMA_INFIFO_UDF_L2_CH1_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ST_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M  (H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST_M  (H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST_V << H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST_S  9
+
+/** H264_DMA_IN_INT_CLR_CH1_REG register
+ *  RX CH1  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH1_REG (DR_REG_H264_DMA_BASE + 0x610)
+/** H264_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH1_INT_CLR_M  (H264_DMA_IN_DONE_CH1_INT_CLR_V << H264_DMA_IN_DONE_CH1_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH1_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH1_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH1_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH1_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** H264_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH1_INT_CLR_M  (H264_DMA_IN_ERR_EOF_CH1_INT_CLR_V << H264_DMA_IN_ERR_EOF_CH1_INT_CLR_S)
+#define H264_DMA_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** H264_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_CLR_M  (H264_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << H264_DMA_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR_M  (H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR_V << H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR_M  (H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR_V << H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M  (H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR_M  (H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR_S  9
+
+/** H264_DMA_INFIFO_STATUS_CH1_REG register
+ *  RX CH1 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH1_REG (DR_REG_H264_DMA_BASE + 0x614)
+/** H264_DMA_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_FULL_L2_CH1    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L2_CH1_M  (H264_DMA_INFIFO_FULL_L2_CH1_V << H264_DMA_INFIFO_FULL_L2_CH1_S)
+#define H264_DMA_INFIFO_FULL_L2_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L2_CH1_S  0
+/** H264_DMA_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_EMPTY_L2_CH1    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L2_CH1_M  (H264_DMA_INFIFO_EMPTY_L2_CH1_V << H264_DMA_INFIFO_EMPTY_L2_CH1_S)
+#define H264_DMA_INFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L2_CH1_S  1
+/** H264_DMA_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define H264_DMA_INFIFO_CNT_L2_CH1    0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH1_M  (H264_DMA_INFIFO_CNT_L2_CH1_V << H264_DMA_INFIFO_CNT_L2_CH1_S)
+#define H264_DMA_INFIFO_CNT_L2_CH1_V  0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH1_S  2
+/** H264_DMA_INFIFO_FULL_L1_CH1 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH1    (BIT(6))
+#define H264_DMA_INFIFO_FULL_L1_CH1_M  (H264_DMA_INFIFO_FULL_L1_CH1_V << H264_DMA_INFIFO_FULL_L1_CH1_S)
+#define H264_DMA_INFIFO_FULL_L1_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH1_S  6
+/** H264_DMA_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH1    (BIT(7))
+#define H264_DMA_INFIFO_EMPTY_L1_CH1_M  (H264_DMA_INFIFO_EMPTY_L1_CH1_V << H264_DMA_INFIFO_EMPTY_L1_CH1_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH1_S  7
+/** H264_DMA_INFIFO_CNT_L1_CH1 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH1    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH1_M  (H264_DMA_INFIFO_CNT_L1_CH1_V << H264_DMA_INFIFO_CNT_L1_CH1_S)
+#define H264_DMA_INFIFO_CNT_L1_CH1_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH1_S  8
+/** H264_DMA_INFIFO_FULL_L3_CH1 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L3_CH1    (BIT(16))
+#define H264_DMA_INFIFO_FULL_L3_CH1_M  (H264_DMA_INFIFO_FULL_L3_CH1_V << H264_DMA_INFIFO_FULL_L3_CH1_S)
+#define H264_DMA_INFIFO_FULL_L3_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L3_CH1_S  16
+/** H264_DMA_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L3_CH1    (BIT(17))
+#define H264_DMA_INFIFO_EMPTY_L3_CH1_M  (H264_DMA_INFIFO_EMPTY_L3_CH1_V << H264_DMA_INFIFO_EMPTY_L3_CH1_S)
+#define H264_DMA_INFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L3_CH1_S  17
+/** H264_DMA_INFIFO_CNT_L3_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L3_CH1    0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH1_M  (H264_DMA_INFIFO_CNT_L3_CH1_V << H264_DMA_INFIFO_CNT_L3_CH1_S)
+#define H264_DMA_INFIFO_CNT_L3_CH1_V  0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH1_S  18
+
+/** H264_DMA_IN_POP_CH1_REG register
+ *  RX CH1 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH1_REG (DR_REG_H264_DMA_BASE + 0x618)
+/** H264_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH1    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH1_M  (H264_DMA_INFIFO_RDATA_CH1_V << H264_DMA_INFIFO_RDATA_CH1_S)
+#define H264_DMA_INFIFO_RDATA_CH1_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH1_S  0
+/** H264_DMA_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH1    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH1_M  (H264_DMA_INFIFO_POP_CH1_V << H264_DMA_INFIFO_POP_CH1_S)
+#define H264_DMA_INFIFO_POP_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH1_S  11
+
+/** H264_DMA_IN_LINK_CONF_CH1_REG register
+ *  RX CH1 in_link dscr ctrl register
+ */
+#define H264_DMA_IN_LINK_CONF_CH1_REG (DR_REG_H264_DMA_BASE + 0x61c)
+/** H264_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_INLINK_AUTO_RET_CH1    (BIT(20))
+#define H264_DMA_INLINK_AUTO_RET_CH1_M  (H264_DMA_INLINK_AUTO_RET_CH1_V << H264_DMA_INLINK_AUTO_RET_CH1_S)
+#define H264_DMA_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define H264_DMA_INLINK_AUTO_RET_CH1_S  20
+/** H264_DMA_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_STOP_CH1    (BIT(21))
+#define H264_DMA_INLINK_STOP_CH1_M  (H264_DMA_INLINK_STOP_CH1_V << H264_DMA_INLINK_STOP_CH1_S)
+#define H264_DMA_INLINK_STOP_CH1_V  0x00000001U
+#define H264_DMA_INLINK_STOP_CH1_S  21
+/** H264_DMA_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_START_CH1    (BIT(22))
+#define H264_DMA_INLINK_START_CH1_M  (H264_DMA_INLINK_START_CH1_V << H264_DMA_INLINK_START_CH1_S)
+#define H264_DMA_INLINK_START_CH1_V  0x00000001U
+#define H264_DMA_INLINK_START_CH1_S  22
+/** H264_DMA_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define H264_DMA_INLINK_RESTART_CH1    (BIT(23))
+#define H264_DMA_INLINK_RESTART_CH1_M  (H264_DMA_INLINK_RESTART_CH1_V << H264_DMA_INLINK_RESTART_CH1_S)
+#define H264_DMA_INLINK_RESTART_CH1_V  0x00000001U
+#define H264_DMA_INLINK_RESTART_CH1_S  23
+/** H264_DMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define H264_DMA_INLINK_PARK_CH1    (BIT(24))
+#define H264_DMA_INLINK_PARK_CH1_M  (H264_DMA_INLINK_PARK_CH1_V << H264_DMA_INLINK_PARK_CH1_S)
+#define H264_DMA_INLINK_PARK_CH1_V  0x00000001U
+#define H264_DMA_INLINK_PARK_CH1_S  24
+
+/** H264_DMA_IN_LINK_ADDR_CH1_REG register
+ *  RX CH1 in_link dscr addr register
+ */
+#define H264_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x620)
+/** H264_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH1_M  (H264_DMA_INLINK_ADDR_CH1_V << H264_DMA_INLINK_ADDR_CH1_S)
+#define H264_DMA_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH1_S  0
+
+/** H264_DMA_IN_STATE_CH1_REG register
+ *  RX CH1 state register
+ */
+#define H264_DMA_IN_STATE_CH1_REG (DR_REG_H264_DMA_BASE + 0x624)
+/** H264_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH1_M  (H264_DMA_INLINK_DSCR_ADDR_CH1_V << H264_DMA_INLINK_DSCR_ADDR_CH1_S)
+#define H264_DMA_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH1_S  0
+/** H264_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_IN_DSCR_STATE_CH1    0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH1_M  (H264_DMA_IN_DSCR_STATE_CH1_V << H264_DMA_IN_DSCR_STATE_CH1_S)
+#define H264_DMA_IN_DSCR_STATE_CH1_V  0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH1_S  18
+/** H264_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH1    0x00000007U
+#define H264_DMA_IN_STATE_CH1_M  (H264_DMA_IN_STATE_CH1_V << H264_DMA_IN_STATE_CH1_S)
+#define H264_DMA_IN_STATE_CH1_V  0x00000007U
+#define H264_DMA_IN_STATE_CH1_S  20
+/** H264_DMA_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH1    (BIT(23))
+#define H264_DMA_IN_RESET_AVAIL_CH1_M  (H264_DMA_IN_RESET_AVAIL_CH1_V << H264_DMA_IN_RESET_AVAIL_CH1_S)
+#define H264_DMA_IN_RESET_AVAIL_CH1_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH1_S  23
+
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  RX CH1 eof des addr register
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x628)
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_M  (H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_V << H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  RX CH1 err eof des addr register
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x62c)
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_M  (H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** H264_DMA_IN_DSCR_CH1_REG register
+ *  RX CH1 next dscr addr register
+ */
+#define H264_DMA_IN_DSCR_CH1_REG (DR_REG_H264_DMA_BASE + 0x630)
+/** H264_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define H264_DMA_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH1_M  (H264_DMA_INLINK_DSCR_CH1_V << H264_DMA_INLINK_DSCR_CH1_S)
+#define H264_DMA_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH1_S  0
+
+/** H264_DMA_IN_DSCR_BF0_CH1_REG register
+ *  RX CH1 last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_H264_DMA_BASE + 0x634)
+/** H264_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define H264_DMA_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH1_M  (H264_DMA_INLINK_DSCR_BF0_CH1_V << H264_DMA_INLINK_DSCR_BF0_CH1_S)
+#define H264_DMA_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH1_S  0
+
+/** H264_DMA_IN_DSCR_BF1_CH1_REG register
+ *  RX CH1 second-to-last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_H264_DMA_BASE + 0x638)
+/** H264_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define H264_DMA_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH1_M  (H264_DMA_INLINK_DSCR_BF1_CH1_V << H264_DMA_INLINK_DSCR_BF1_CH1_S)
+#define H264_DMA_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH1_S  0
+
+/** H264_DMA_IN_ARB_CH1_REG register
+ *  RX CH1 arb register
+ */
+#define H264_DMA_IN_ARB_CH1_REG (DR_REG_H264_DMA_BASE + 0x640)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH1_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH1_V << H264_DMA_IN_ARB_TOKEN_NUM_CH1_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH1_S  0
+/** H264_DMA_EXTER_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH1    0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH1_M  (H264_DMA_EXTER_IN_ARB_PRIORITY_CH1_V << H264_DMA_EXTER_IN_ARB_PRIORITY_CH1_S)
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH1_V  0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH1_S  4
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH1    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH1_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH1_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH1_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH1_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH1_S  6
+
+/** H264_DMA_IN_ETM_CONF_CH1_REG register
+ *  RX CH1 ETM config register
+ */
+#define H264_DMA_IN_ETM_CONF_CH1_REG (DR_REG_H264_DMA_BASE + 0x648)
+/** H264_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_IN_ETM_EN_CH1    (BIT(0))
+#define H264_DMA_IN_ETM_EN_CH1_M  (H264_DMA_IN_ETM_EN_CH1_V << H264_DMA_IN_ETM_EN_CH1_S)
+#define H264_DMA_IN_ETM_EN_CH1_V  0x00000001U
+#define H264_DMA_IN_ETM_EN_CH1_S  0
+/** H264_DMA_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_IN_ETM_LOOP_EN_CH1    (BIT(1))
+#define H264_DMA_IN_ETM_LOOP_EN_CH1_M  (H264_DMA_IN_ETM_LOOP_EN_CH1_V << H264_DMA_IN_ETM_LOOP_EN_CH1_S)
+#define H264_DMA_IN_ETM_LOOP_EN_CH1_V  0x00000001U
+#define H264_DMA_IN_ETM_LOOP_EN_CH1_S  1
+/** H264_DMA_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_IN_DSCR_TASK_MAK_CH1    0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH1_M  (H264_DMA_IN_DSCR_TASK_MAK_CH1_V << H264_DMA_IN_DSCR_TASK_MAK_CH1_S)
+#define H264_DMA_IN_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH1_S  2
+
+/** H264_DMA_IN_FIFO_CNT_CH1_REG register
+ *  rx CH1 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH1_REG (DR_REG_H264_DMA_BASE + 0x680)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH1_REG register
+ *  rx CH1 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH1_REG (DR_REG_H264_DMA_BASE + 0x684)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1 : RO; bitpos: [7:0]; default: 7;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1_S  0
+
+/** H264_DMA_IN_XADDR_CH1_REG register
+ *  rx CH1 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x688)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH1_M  (H264_DMA_IN_CMDFIFO_XADDR_CH1_V << H264_DMA_IN_CMDFIFO_XADDR_CH1_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH1_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH1_REG register
+ *  rx CH1 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH1_REG (DR_REG_H264_DMA_BASE + 0x68c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1_S  0
+
+/** H264_DMA_IN_CONF0_CH2_REG register
+ *  RX CH2 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH2_REG (DR_REG_H264_DMA_BASE + 0x700)
+/** H264_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define H264_DMA_INDSCR_BURST_EN_CH2    (BIT(2))
+#define H264_DMA_INDSCR_BURST_EN_CH2_M  (H264_DMA_INDSCR_BURST_EN_CH2_V << H264_DMA_INDSCR_BURST_EN_CH2_S)
+#define H264_DMA_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define H264_DMA_INDSCR_BURST_EN_CH2_S  2
+/** H264_DMA_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH2    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH2_M  (H264_DMA_IN_ECC_AES_EN_CH2_V << H264_DMA_IN_ECC_AES_EN_CH2_S)
+#define H264_DMA_IN_ECC_AES_EN_CH2_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH2_S  3
+/** H264_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_IN_CHECK_OWNER_CH2    (BIT(4))
+#define H264_DMA_IN_CHECK_OWNER_CH2_M  (H264_DMA_IN_CHECK_OWNER_CH2_V << H264_DMA_IN_CHECK_OWNER_CH2_S)
+#define H264_DMA_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define H264_DMA_IN_CHECK_OWNER_CH2_S  4
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 2. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH2    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH2_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH2_V << H264_DMA_IN_MEM_BURST_LENGTH_CH2_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH2_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH2    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH2_M  (H264_DMA_IN_PAGE_BOUND_EN_CH2_V << H264_DMA_IN_PAGE_BOUND_EN_CH2_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH2_S  12
+/** H264_DMA_IN_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH2    (BIT(24))
+#define H264_DMA_IN_RST_CH2_M  (H264_DMA_IN_RST_CH2_V << H264_DMA_IN_RST_CH2_S)
+#define H264_DMA_IN_RST_CH2_V  0x00000001U
+#define H264_DMA_IN_RST_CH2_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH2    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH2_M  (H264_DMA_IN_CMD_DISABLE_CH2_V << H264_DMA_IN_CMD_DISABLE_CH2_S)
+#define H264_DMA_IN_CMD_DISABLE_CH2_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH2_S  25
+/** H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2_M  (H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2_V << H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** H264_DMA_IN_INT_RAW_CH2_REG register
+ *  RX CH2  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH2_REG (DR_REG_H264_DMA_BASE + 0x704)
+/** H264_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 1.
+ */
+#define H264_DMA_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH2_INT_RAW_M  (H264_DMA_IN_DONE_CH2_INT_RAW_V << H264_DMA_IN_DONE_CH2_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH2_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 1.
+ */
+#define H264_DMA_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH2_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH2_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH2_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** H264_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define H264_DMA_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH2_INT_RAW_M  (H264_DMA_IN_ERR_EOF_CH2_INT_RAW_V << H264_DMA_IN_ERR_EOF_CH2_INT_RAW_S)
+#define H264_DMA_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** H264_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 1.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_RAW_M  (H264_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << H264_DMA_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW_M  (H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW_V << H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW_M  (H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW_V << H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M  (H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW_M  (H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW_S  9
+
+/** H264_DMA_IN_INT_ENA_CH2_REG register
+ *  RX CH2  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH2_REG (DR_REG_H264_DMA_BASE + 0x708)
+/** H264_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH2_INT_ENA_M  (H264_DMA_IN_DONE_CH2_INT_ENA_V << H264_DMA_IN_DONE_CH2_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH2_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH2_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH2_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** H264_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ENA_M  (H264_DMA_IN_ERR_EOF_CH2_INT_ENA_V << H264_DMA_IN_ERR_EOF_CH2_INT_ENA_S)
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** H264_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ENA_M  (H264_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << H264_DMA_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA_M  (H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA_V << H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA_M  (H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA_V << H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M  (H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA_M  (H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA_S  9
+
+/** H264_DMA_IN_INT_ST_CH2_REG register
+ *  RX CH2  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH2_REG (DR_REG_H264_DMA_BASE + 0x70c)
+/** H264_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH2_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH2_INT_ST_M  (H264_DMA_IN_DONE_CH2_INT_ST_V << H264_DMA_IN_DONE_CH2_INT_ST_S)
+#define H264_DMA_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH2_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH2_INT_ST_V << H264_DMA_IN_SUC_EOF_CH2_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ST_S  1
+/** H264_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ST_M  (H264_DMA_IN_ERR_EOF_CH2_INT_ST_V << H264_DMA_IN_ERR_EOF_CH2_INT_ST_S)
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ST_S  2
+/** H264_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ST_M  (H264_DMA_IN_DSCR_ERR_CH2_INT_ST_V << H264_DMA_IN_DSCR_ERR_CH2_INT_ST_S)
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH2_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH2_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ST_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH2_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH2_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ST_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ST_M  (H264_DMA_INFIFO_OVF_L2_CH2_INT_ST_V << H264_DMA_INFIFO_OVF_L2_CH2_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ST_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ST_M  (H264_DMA_INFIFO_UDF_L2_CH2_INT_ST_V << H264_DMA_INFIFO_UDF_L2_CH2_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ST_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M  (H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST_M  (H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST_V << H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST_S  9
+
+/** H264_DMA_IN_INT_CLR_CH2_REG register
+ *  RX CH2  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH2_REG (DR_REG_H264_DMA_BASE + 0x710)
+/** H264_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH2_INT_CLR_M  (H264_DMA_IN_DONE_CH2_INT_CLR_V << H264_DMA_IN_DONE_CH2_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH2_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH2_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH2_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH2_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** H264_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH2_INT_CLR_M  (H264_DMA_IN_ERR_EOF_CH2_INT_CLR_V << H264_DMA_IN_ERR_EOF_CH2_INT_CLR_S)
+#define H264_DMA_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** H264_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_CLR_M  (H264_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << H264_DMA_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR_M  (H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR_V << H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR_M  (H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR_V << H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M  (H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR_M  (H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR_S  9
+
+/** H264_DMA_INFIFO_STATUS_CH2_REG register
+ *  RX CH2 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH2_REG (DR_REG_H264_DMA_BASE + 0x714)
+/** H264_DMA_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_FULL_L2_CH2    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L2_CH2_M  (H264_DMA_INFIFO_FULL_L2_CH2_V << H264_DMA_INFIFO_FULL_L2_CH2_S)
+#define H264_DMA_INFIFO_FULL_L2_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L2_CH2_S  0
+/** H264_DMA_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_EMPTY_L2_CH2    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L2_CH2_M  (H264_DMA_INFIFO_EMPTY_L2_CH2_V << H264_DMA_INFIFO_EMPTY_L2_CH2_S)
+#define H264_DMA_INFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L2_CH2_S  1
+/** H264_DMA_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define H264_DMA_INFIFO_CNT_L2_CH2    0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH2_M  (H264_DMA_INFIFO_CNT_L2_CH2_V << H264_DMA_INFIFO_CNT_L2_CH2_S)
+#define H264_DMA_INFIFO_CNT_L2_CH2_V  0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH2_S  2
+/** H264_DMA_INFIFO_FULL_L1_CH2 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH2    (BIT(6))
+#define H264_DMA_INFIFO_FULL_L1_CH2_M  (H264_DMA_INFIFO_FULL_L1_CH2_V << H264_DMA_INFIFO_FULL_L1_CH2_S)
+#define H264_DMA_INFIFO_FULL_L1_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH2_S  6
+/** H264_DMA_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH2    (BIT(7))
+#define H264_DMA_INFIFO_EMPTY_L1_CH2_M  (H264_DMA_INFIFO_EMPTY_L1_CH2_V << H264_DMA_INFIFO_EMPTY_L1_CH2_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH2_S  7
+/** H264_DMA_INFIFO_CNT_L1_CH2 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH2    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH2_M  (H264_DMA_INFIFO_CNT_L1_CH2_V << H264_DMA_INFIFO_CNT_L1_CH2_S)
+#define H264_DMA_INFIFO_CNT_L1_CH2_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH2_S  8
+/** H264_DMA_INFIFO_FULL_L3_CH2 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L3_CH2    (BIT(16))
+#define H264_DMA_INFIFO_FULL_L3_CH2_M  (H264_DMA_INFIFO_FULL_L3_CH2_V << H264_DMA_INFIFO_FULL_L3_CH2_S)
+#define H264_DMA_INFIFO_FULL_L3_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L3_CH2_S  16
+/** H264_DMA_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L3_CH2    (BIT(17))
+#define H264_DMA_INFIFO_EMPTY_L3_CH2_M  (H264_DMA_INFIFO_EMPTY_L3_CH2_V << H264_DMA_INFIFO_EMPTY_L3_CH2_S)
+#define H264_DMA_INFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L3_CH2_S  17
+/** H264_DMA_INFIFO_CNT_L3_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L3_CH2    0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH2_M  (H264_DMA_INFIFO_CNT_L3_CH2_V << H264_DMA_INFIFO_CNT_L3_CH2_S)
+#define H264_DMA_INFIFO_CNT_L3_CH2_V  0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH2_S  18
+
+/** H264_DMA_IN_POP_CH2_REG register
+ *  RX CH2 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH2_REG (DR_REG_H264_DMA_BASE + 0x718)
+/** H264_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH2    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH2_M  (H264_DMA_INFIFO_RDATA_CH2_V << H264_DMA_INFIFO_RDATA_CH2_S)
+#define H264_DMA_INFIFO_RDATA_CH2_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH2_S  0
+/** H264_DMA_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH2    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH2_M  (H264_DMA_INFIFO_POP_CH2_V << H264_DMA_INFIFO_POP_CH2_S)
+#define H264_DMA_INFIFO_POP_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH2_S  11
+
+/** H264_DMA_IN_LINK_CONF_CH2_REG register
+ *  RX CH2 in_link dscr ctrl register
+ */
+#define H264_DMA_IN_LINK_CONF_CH2_REG (DR_REG_H264_DMA_BASE + 0x71c)
+/** H264_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_INLINK_AUTO_RET_CH2    (BIT(20))
+#define H264_DMA_INLINK_AUTO_RET_CH2_M  (H264_DMA_INLINK_AUTO_RET_CH2_V << H264_DMA_INLINK_AUTO_RET_CH2_S)
+#define H264_DMA_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define H264_DMA_INLINK_AUTO_RET_CH2_S  20
+/** H264_DMA_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_STOP_CH2    (BIT(21))
+#define H264_DMA_INLINK_STOP_CH2_M  (H264_DMA_INLINK_STOP_CH2_V << H264_DMA_INLINK_STOP_CH2_S)
+#define H264_DMA_INLINK_STOP_CH2_V  0x00000001U
+#define H264_DMA_INLINK_STOP_CH2_S  21
+/** H264_DMA_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_START_CH2    (BIT(22))
+#define H264_DMA_INLINK_START_CH2_M  (H264_DMA_INLINK_START_CH2_V << H264_DMA_INLINK_START_CH2_S)
+#define H264_DMA_INLINK_START_CH2_V  0x00000001U
+#define H264_DMA_INLINK_START_CH2_S  22
+/** H264_DMA_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define H264_DMA_INLINK_RESTART_CH2    (BIT(23))
+#define H264_DMA_INLINK_RESTART_CH2_M  (H264_DMA_INLINK_RESTART_CH2_V << H264_DMA_INLINK_RESTART_CH2_S)
+#define H264_DMA_INLINK_RESTART_CH2_V  0x00000001U
+#define H264_DMA_INLINK_RESTART_CH2_S  23
+/** H264_DMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define H264_DMA_INLINK_PARK_CH2    (BIT(24))
+#define H264_DMA_INLINK_PARK_CH2_M  (H264_DMA_INLINK_PARK_CH2_V << H264_DMA_INLINK_PARK_CH2_S)
+#define H264_DMA_INLINK_PARK_CH2_V  0x00000001U
+#define H264_DMA_INLINK_PARK_CH2_S  24
+
+/** H264_DMA_IN_LINK_ADDR_CH2_REG register
+ *  RX CH2 in_link dscr addr register
+ */
+#define H264_DMA_IN_LINK_ADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x720)
+/** H264_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH2_M  (H264_DMA_INLINK_ADDR_CH2_V << H264_DMA_INLINK_ADDR_CH2_S)
+#define H264_DMA_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH2_S  0
+
+/** H264_DMA_IN_STATE_CH2_REG register
+ *  RX CH2 state register
+ */
+#define H264_DMA_IN_STATE_CH2_REG (DR_REG_H264_DMA_BASE + 0x724)
+/** H264_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH2_M  (H264_DMA_INLINK_DSCR_ADDR_CH2_V << H264_DMA_INLINK_DSCR_ADDR_CH2_S)
+#define H264_DMA_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH2_S  0
+/** H264_DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_IN_DSCR_STATE_CH2    0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH2_M  (H264_DMA_IN_DSCR_STATE_CH2_V << H264_DMA_IN_DSCR_STATE_CH2_S)
+#define H264_DMA_IN_DSCR_STATE_CH2_V  0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH2_S  18
+/** H264_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH2    0x00000007U
+#define H264_DMA_IN_STATE_CH2_M  (H264_DMA_IN_STATE_CH2_V << H264_DMA_IN_STATE_CH2_S)
+#define H264_DMA_IN_STATE_CH2_V  0x00000007U
+#define H264_DMA_IN_STATE_CH2_S  20
+/** H264_DMA_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH2    (BIT(23))
+#define H264_DMA_IN_RESET_AVAIL_CH2_M  (H264_DMA_IN_RESET_AVAIL_CH2_V << H264_DMA_IN_RESET_AVAIL_CH2_S)
+#define H264_DMA_IN_RESET_AVAIL_CH2_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH2_S  23
+
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  RX CH2 eof des addr register
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x728)
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_M  (H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_V << H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  RX CH2 err eof des addr register
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x72c)
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_M  (H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_V << H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** H264_DMA_IN_DSCR_CH2_REG register
+ *  RX CH2 next dscr addr register
+ */
+#define H264_DMA_IN_DSCR_CH2_REG (DR_REG_H264_DMA_BASE + 0x730)
+/** H264_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define H264_DMA_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH2_M  (H264_DMA_INLINK_DSCR_CH2_V << H264_DMA_INLINK_DSCR_CH2_S)
+#define H264_DMA_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH2_S  0
+
+/** H264_DMA_IN_DSCR_BF0_CH2_REG register
+ *  RX CH2 last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_H264_DMA_BASE + 0x734)
+/** H264_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define H264_DMA_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH2_M  (H264_DMA_INLINK_DSCR_BF0_CH2_V << H264_DMA_INLINK_DSCR_BF0_CH2_S)
+#define H264_DMA_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH2_S  0
+
+/** H264_DMA_IN_DSCR_BF1_CH2_REG register
+ *  RX CH2 second-to-last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_H264_DMA_BASE + 0x738)
+/** H264_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define H264_DMA_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH2_M  (H264_DMA_INLINK_DSCR_BF1_CH2_V << H264_DMA_INLINK_DSCR_BF1_CH2_S)
+#define H264_DMA_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH2_S  0
+
+/** H264_DMA_IN_ARB_CH2_REG register
+ *  RX CH2 arb register
+ */
+#define H264_DMA_IN_ARB_CH2_REG (DR_REG_H264_DMA_BASE + 0x740)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH2_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH2_V << H264_DMA_IN_ARB_TOKEN_NUM_CH2_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH2_S  0
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH2    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH2_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH2_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH2_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH2_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH2_S  6
+
+/** H264_DMA_IN_ETM_CONF_CH2_REG register
+ *  RX CH2 ETM config register
+ */
+#define H264_DMA_IN_ETM_CONF_CH2_REG (DR_REG_H264_DMA_BASE + 0x748)
+/** H264_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_IN_ETM_EN_CH2    (BIT(0))
+#define H264_DMA_IN_ETM_EN_CH2_M  (H264_DMA_IN_ETM_EN_CH2_V << H264_DMA_IN_ETM_EN_CH2_S)
+#define H264_DMA_IN_ETM_EN_CH2_V  0x00000001U
+#define H264_DMA_IN_ETM_EN_CH2_S  0
+/** H264_DMA_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_IN_ETM_LOOP_EN_CH2    (BIT(1))
+#define H264_DMA_IN_ETM_LOOP_EN_CH2_M  (H264_DMA_IN_ETM_LOOP_EN_CH2_V << H264_DMA_IN_ETM_LOOP_EN_CH2_S)
+#define H264_DMA_IN_ETM_LOOP_EN_CH2_V  0x00000001U
+#define H264_DMA_IN_ETM_LOOP_EN_CH2_S  1
+/** H264_DMA_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_IN_DSCR_TASK_MAK_CH2    0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH2_M  (H264_DMA_IN_DSCR_TASK_MAK_CH2_V << H264_DMA_IN_DSCR_TASK_MAK_CH2_S)
+#define H264_DMA_IN_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH2_S  2
+
+/** H264_DMA_IN_FIFO_CNT_CH2_REG register
+ *  rx CH2 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH2_REG (DR_REG_H264_DMA_BASE + 0x780)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH2_REG register
+ *  rx CH2 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH2_REG (DR_REG_H264_DMA_BASE + 0x784)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2 : RO; bitpos: [7:0]; default: 7;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2_S  0
+
+/** H264_DMA_IN_XADDR_CH2_REG register
+ *  rx CH2 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x788)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH2_M  (H264_DMA_IN_CMDFIFO_XADDR_CH2_V << H264_DMA_IN_CMDFIFO_XADDR_CH2_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH2_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH2_REG register
+ *  rx CH2 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH2_REG (DR_REG_H264_DMA_BASE + 0x78c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2_S  0
+
+/** H264_DMA_IN_CONF0_CH3_REG register
+ *  RX CH3 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH3_REG (DR_REG_H264_DMA_BASE + 0x800)
+/** H264_DMA_INDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define H264_DMA_INDSCR_BURST_EN_CH3    (BIT(2))
+#define H264_DMA_INDSCR_BURST_EN_CH3_M  (H264_DMA_INDSCR_BURST_EN_CH3_V << H264_DMA_INDSCR_BURST_EN_CH3_S)
+#define H264_DMA_INDSCR_BURST_EN_CH3_V  0x00000001U
+#define H264_DMA_INDSCR_BURST_EN_CH3_S  2
+/** H264_DMA_IN_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH3    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH3_M  (H264_DMA_IN_ECC_AES_EN_CH3_V << H264_DMA_IN_ECC_AES_EN_CH3_S)
+#define H264_DMA_IN_ECC_AES_EN_CH3_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH3_S  3
+/** H264_DMA_IN_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_IN_CHECK_OWNER_CH3    (BIT(4))
+#define H264_DMA_IN_CHECK_OWNER_CH3_M  (H264_DMA_IN_CHECK_OWNER_CH3_V << H264_DMA_IN_CHECK_OWNER_CH3_S)
+#define H264_DMA_IN_CHECK_OWNER_CH3_V  0x00000001U
+#define H264_DMA_IN_CHECK_OWNER_CH3_S  4
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH3    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH3_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH3_V << H264_DMA_IN_MEM_BURST_LENGTH_CH3_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH3_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH3_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH3    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH3_M  (H264_DMA_IN_PAGE_BOUND_EN_CH3_V << H264_DMA_IN_PAGE_BOUND_EN_CH3_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH3_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH3_S  12
+/** H264_DMA_IN_RST_CH3 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH3    (BIT(24))
+#define H264_DMA_IN_RST_CH3_M  (H264_DMA_IN_RST_CH3_V << H264_DMA_IN_RST_CH3_S)
+#define H264_DMA_IN_RST_CH3_V  0x00000001U
+#define H264_DMA_IN_RST_CH3_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH3    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH3_M  (H264_DMA_IN_CMD_DISABLE_CH3_V << H264_DMA_IN_CMD_DISABLE_CH3_S)
+#define H264_DMA_IN_CMD_DISABLE_CH3_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH3_S  25
+/** H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3    (BIT(26))
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3_M  (H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3_V << H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3_S)
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3_V  0x00000001U
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3_S  26
+
+/** H264_DMA_IN_INT_RAW_CH3_REG register
+ *  RX CH3  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH3_REG (DR_REG_H264_DMA_BASE + 0x804)
+/** H264_DMA_IN_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 1.
+ */
+#define H264_DMA_IN_DONE_CH3_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH3_INT_RAW_M  (H264_DMA_IN_DONE_CH3_INT_RAW_V << H264_DMA_IN_DONE_CH3_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH3_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 1.
+ */
+#define H264_DMA_IN_SUC_EOF_CH3_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH3_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH3_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH3_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH3_INT_RAW_S  1
+/** H264_DMA_IN_ERR_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define H264_DMA_IN_ERR_EOF_CH3_INT_RAW    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH3_INT_RAW_M  (H264_DMA_IN_ERR_EOF_CH3_INT_RAW_V << H264_DMA_IN_ERR_EOF_CH3_INT_RAW_S)
+#define H264_DMA_IN_ERR_EOF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH3_INT_RAW_S  2
+/** H264_DMA_IN_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 1.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_RAW    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_RAW_M  (H264_DMA_IN_DSCR_ERR_CH3_INT_RAW_V << H264_DMA_IN_DSCR_ERR_CH3_INT_RAW_S)
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_RAW_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW_M  (H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW_V << H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW_M  (H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW_V << H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_M  (H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_V << H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW_M  (H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW_V << H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW_S  9
+
+/** H264_DMA_IN_INT_ENA_CH3_REG register
+ *  RX CH3  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH3_REG (DR_REG_H264_DMA_BASE + 0x808)
+/** H264_DMA_IN_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH3_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH3_INT_ENA_M  (H264_DMA_IN_DONE_CH3_INT_ENA_V << H264_DMA_IN_DONE_CH3_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH3_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH3_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH3_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ENA_S  1
+/** H264_DMA_IN_ERR_EOF_CH3_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ENA    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ENA_M  (H264_DMA_IN_ERR_EOF_CH3_INT_ENA_V << H264_DMA_IN_ERR_EOF_CH3_INT_ENA_S)
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ENA_S  2
+/** H264_DMA_IN_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ENA    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ENA_M  (H264_DMA_IN_DSCR_ERR_CH3_INT_ENA_V << H264_DMA_IN_DSCR_ERR_CH3_INT_ENA_S)
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ENA_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA_M  (H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA_V << H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA_M  (H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA_V << H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_M  (H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_V << H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA_M  (H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA_V << H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA_S  9
+
+/** H264_DMA_IN_INT_ST_CH3_REG register
+ *  RX CH3  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH3_REG (DR_REG_H264_DMA_BASE + 0x80c)
+/** H264_DMA_IN_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH3_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH3_INT_ST_M  (H264_DMA_IN_DONE_CH3_INT_ST_V << H264_DMA_IN_DONE_CH3_INT_ST_S)
+#define H264_DMA_IN_DONE_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH3_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH3_INT_ST_V << H264_DMA_IN_SUC_EOF_CH3_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ST_S  1
+/** H264_DMA_IN_ERR_EOF_CH3_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ST    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ST_M  (H264_DMA_IN_ERR_EOF_CH3_INT_ST_V << H264_DMA_IN_ERR_EOF_CH3_INT_ST_S)
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ST_S  2
+/** H264_DMA_IN_DSCR_ERR_CH3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ST    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ST_M  (H264_DMA_IN_DSCR_ERR_CH3_INT_ST_V << H264_DMA_IN_DSCR_ERR_CH3_INT_ST_S)
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ST_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ST    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH3_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH3_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ST_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ST    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH3_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH3_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ST_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ST    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ST_M  (H264_DMA_INFIFO_OVF_L2_CH3_INT_ST_V << H264_DMA_INFIFO_OVF_L2_CH3_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ST_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ST    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ST_M  (H264_DMA_INFIFO_UDF_L2_CH3_INT_ST_V << H264_DMA_INFIFO_UDF_L2_CH3_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ST_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST_M  (H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST_V << H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST_M  (H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST_V << H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST_S  9
+
+/** H264_DMA_IN_INT_CLR_CH3_REG register
+ *  RX CH3  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH3_REG (DR_REG_H264_DMA_BASE + 0x810)
+/** H264_DMA_IN_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH3_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH3_INT_CLR_M  (H264_DMA_IN_DONE_CH3_INT_CLR_V << H264_DMA_IN_DONE_CH3_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH3_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH3_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH3_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH3_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH3_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH3_INT_CLR_S  1
+/** H264_DMA_IN_ERR_EOF_CH3_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH3_INT_CLR    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH3_INT_CLR_M  (H264_DMA_IN_ERR_EOF_CH3_INT_CLR_V << H264_DMA_IN_ERR_EOF_CH3_INT_CLR_S)
+#define H264_DMA_IN_ERR_EOF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH3_INT_CLR_S  2
+/** H264_DMA_IN_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_CLR    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_CLR_M  (H264_DMA_IN_DSCR_ERR_CH3_INT_CLR_V << H264_DMA_IN_DSCR_ERR_CH3_INT_CLR_S)
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_CLR_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR_M  (H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR_V << H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR_M  (H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR_V << H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_M  (H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_V << H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR_M  (H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR_V << H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR_S  9
+
+/** H264_DMA_INFIFO_STATUS_CH3_REG register
+ *  RX CH3 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH3_REG (DR_REG_H264_DMA_BASE + 0x814)
+/** H264_DMA_INFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_FULL_L2_CH3    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L2_CH3_M  (H264_DMA_INFIFO_FULL_L2_CH3_V << H264_DMA_INFIFO_FULL_L2_CH3_S)
+#define H264_DMA_INFIFO_FULL_L2_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L2_CH3_S  0
+/** H264_DMA_INFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_EMPTY_L2_CH3    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L2_CH3_M  (H264_DMA_INFIFO_EMPTY_L2_CH3_V << H264_DMA_INFIFO_EMPTY_L2_CH3_S)
+#define H264_DMA_INFIFO_EMPTY_L2_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L2_CH3_S  1
+/** H264_DMA_INFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define H264_DMA_INFIFO_CNT_L2_CH3    0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH3_M  (H264_DMA_INFIFO_CNT_L2_CH3_V << H264_DMA_INFIFO_CNT_L2_CH3_S)
+#define H264_DMA_INFIFO_CNT_L2_CH3_V  0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH3_S  2
+/** H264_DMA_INFIFO_FULL_L1_CH3 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH3    (BIT(6))
+#define H264_DMA_INFIFO_FULL_L1_CH3_M  (H264_DMA_INFIFO_FULL_L1_CH3_V << H264_DMA_INFIFO_FULL_L1_CH3_S)
+#define H264_DMA_INFIFO_FULL_L1_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH3_S  6
+/** H264_DMA_INFIFO_EMPTY_L1_CH3 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH3    (BIT(7))
+#define H264_DMA_INFIFO_EMPTY_L1_CH3_M  (H264_DMA_INFIFO_EMPTY_L1_CH3_V << H264_DMA_INFIFO_EMPTY_L1_CH3_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH3_S  7
+/** H264_DMA_INFIFO_CNT_L1_CH3 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH3    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH3_M  (H264_DMA_INFIFO_CNT_L1_CH3_V << H264_DMA_INFIFO_CNT_L1_CH3_S)
+#define H264_DMA_INFIFO_CNT_L1_CH3_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH3_S  8
+/** H264_DMA_INFIFO_FULL_L3_CH3 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L3_CH3    (BIT(16))
+#define H264_DMA_INFIFO_FULL_L3_CH3_M  (H264_DMA_INFIFO_FULL_L3_CH3_V << H264_DMA_INFIFO_FULL_L3_CH3_S)
+#define H264_DMA_INFIFO_FULL_L3_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L3_CH3_S  16
+/** H264_DMA_INFIFO_EMPTY_L3_CH3 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L3_CH3    (BIT(17))
+#define H264_DMA_INFIFO_EMPTY_L3_CH3_M  (H264_DMA_INFIFO_EMPTY_L3_CH3_V << H264_DMA_INFIFO_EMPTY_L3_CH3_S)
+#define H264_DMA_INFIFO_EMPTY_L3_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L3_CH3_S  17
+/** H264_DMA_INFIFO_CNT_L3_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L3_CH3    0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH3_M  (H264_DMA_INFIFO_CNT_L3_CH3_V << H264_DMA_INFIFO_CNT_L3_CH3_S)
+#define H264_DMA_INFIFO_CNT_L3_CH3_V  0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH3_S  18
+
+/** H264_DMA_IN_POP_CH3_REG register
+ *  RX CH3 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH3_REG (DR_REG_H264_DMA_BASE + 0x818)
+/** H264_DMA_INFIFO_RDATA_CH3 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH3    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH3_M  (H264_DMA_INFIFO_RDATA_CH3_V << H264_DMA_INFIFO_RDATA_CH3_S)
+#define H264_DMA_INFIFO_RDATA_CH3_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH3_S  0
+/** H264_DMA_INFIFO_POP_CH3 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH3    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH3_M  (H264_DMA_INFIFO_POP_CH3_V << H264_DMA_INFIFO_POP_CH3_S)
+#define H264_DMA_INFIFO_POP_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH3_S  11
+
+/** H264_DMA_IN_LINK_CONF_CH3_REG register
+ *  RX CH3 in_link dscr ctrl register
+ */
+#define H264_DMA_IN_LINK_CONF_CH3_REG (DR_REG_H264_DMA_BASE + 0x81c)
+/** H264_DMA_INLINK_AUTO_RET_CH3 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_INLINK_AUTO_RET_CH3    (BIT(20))
+#define H264_DMA_INLINK_AUTO_RET_CH3_M  (H264_DMA_INLINK_AUTO_RET_CH3_V << H264_DMA_INLINK_AUTO_RET_CH3_S)
+#define H264_DMA_INLINK_AUTO_RET_CH3_V  0x00000001U
+#define H264_DMA_INLINK_AUTO_RET_CH3_S  20
+/** H264_DMA_INLINK_STOP_CH3 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_STOP_CH3    (BIT(21))
+#define H264_DMA_INLINK_STOP_CH3_M  (H264_DMA_INLINK_STOP_CH3_V << H264_DMA_INLINK_STOP_CH3_S)
+#define H264_DMA_INLINK_STOP_CH3_V  0x00000001U
+#define H264_DMA_INLINK_STOP_CH3_S  21
+/** H264_DMA_INLINK_START_CH3 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_START_CH3    (BIT(22))
+#define H264_DMA_INLINK_START_CH3_M  (H264_DMA_INLINK_START_CH3_V << H264_DMA_INLINK_START_CH3_S)
+#define H264_DMA_INLINK_START_CH3_V  0x00000001U
+#define H264_DMA_INLINK_START_CH3_S  22
+/** H264_DMA_INLINK_RESTART_CH3 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define H264_DMA_INLINK_RESTART_CH3    (BIT(23))
+#define H264_DMA_INLINK_RESTART_CH3_M  (H264_DMA_INLINK_RESTART_CH3_V << H264_DMA_INLINK_RESTART_CH3_S)
+#define H264_DMA_INLINK_RESTART_CH3_V  0x00000001U
+#define H264_DMA_INLINK_RESTART_CH3_S  23
+/** H264_DMA_INLINK_PARK_CH3 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define H264_DMA_INLINK_PARK_CH3    (BIT(24))
+#define H264_DMA_INLINK_PARK_CH3_M  (H264_DMA_INLINK_PARK_CH3_V << H264_DMA_INLINK_PARK_CH3_S)
+#define H264_DMA_INLINK_PARK_CH3_V  0x00000001U
+#define H264_DMA_INLINK_PARK_CH3_S  24
+
+/** H264_DMA_IN_LINK_ADDR_CH3_REG register
+ *  RX CH3 in_link dscr addr register
+ */
+#define H264_DMA_IN_LINK_ADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x820)
+/** H264_DMA_INLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_ADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH3_M  (H264_DMA_INLINK_ADDR_CH3_V << H264_DMA_INLINK_ADDR_CH3_S)
+#define H264_DMA_INLINK_ADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH3_S  0
+
+/** H264_DMA_IN_STATE_CH3_REG register
+ *  RX CH3 state register
+ */
+#define H264_DMA_IN_STATE_CH3_REG (DR_REG_H264_DMA_BASE + 0x824)
+/** H264_DMA_INLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_DSCR_ADDR_CH3    0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH3_M  (H264_DMA_INLINK_DSCR_ADDR_CH3_V << H264_DMA_INLINK_DSCR_ADDR_CH3_S)
+#define H264_DMA_INLINK_DSCR_ADDR_CH3_V  0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH3_S  0
+/** H264_DMA_IN_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_IN_DSCR_STATE_CH3    0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH3_M  (H264_DMA_IN_DSCR_STATE_CH3_V << H264_DMA_IN_DSCR_STATE_CH3_S)
+#define H264_DMA_IN_DSCR_STATE_CH3_V  0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH3_S  18
+/** H264_DMA_IN_STATE_CH3 : RO; bitpos: [22:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH3    0x00000007U
+#define H264_DMA_IN_STATE_CH3_M  (H264_DMA_IN_STATE_CH3_V << H264_DMA_IN_STATE_CH3_S)
+#define H264_DMA_IN_STATE_CH3_V  0x00000007U
+#define H264_DMA_IN_STATE_CH3_S  20
+/** H264_DMA_IN_RESET_AVAIL_CH3 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH3    (BIT(23))
+#define H264_DMA_IN_RESET_AVAIL_CH3_M  (H264_DMA_IN_RESET_AVAIL_CH3_V << H264_DMA_IN_RESET_AVAIL_CH3_S)
+#define H264_DMA_IN_RESET_AVAIL_CH3_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH3_S  23
+
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_REG register
+ *  RX CH3 eof des addr register
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x828)
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_M  (H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_V << H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_S)
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_S  0
+
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_REG register
+ *  RX CH3 err eof des addr register
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x82c)
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_M  (H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_V << H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_S)
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_S  0
+
+/** H264_DMA_IN_DSCR_CH3_REG register
+ *  RX CH3 next dscr addr register
+ */
+#define H264_DMA_IN_DSCR_CH3_REG (DR_REG_H264_DMA_BASE + 0x830)
+/** H264_DMA_INLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define H264_DMA_INLINK_DSCR_CH3    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH3_M  (H264_DMA_INLINK_DSCR_CH3_V << H264_DMA_INLINK_DSCR_CH3_S)
+#define H264_DMA_INLINK_DSCR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH3_S  0
+
+/** H264_DMA_IN_DSCR_BF0_CH3_REG register
+ *  RX CH3 last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF0_CH3_REG (DR_REG_H264_DMA_BASE + 0x834)
+/** H264_DMA_INLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define H264_DMA_INLINK_DSCR_BF0_CH3    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH3_M  (H264_DMA_INLINK_DSCR_BF0_CH3_V << H264_DMA_INLINK_DSCR_BF0_CH3_S)
+#define H264_DMA_INLINK_DSCR_BF0_CH3_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH3_S  0
+
+/** H264_DMA_IN_DSCR_BF1_CH3_REG register
+ *  RX CH3 second-to-last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF1_CH3_REG (DR_REG_H264_DMA_BASE + 0x838)
+/** H264_DMA_INLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define H264_DMA_INLINK_DSCR_BF1_CH3    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH3_M  (H264_DMA_INLINK_DSCR_BF1_CH3_V << H264_DMA_INLINK_DSCR_BF1_CH3_S)
+#define H264_DMA_INLINK_DSCR_BF1_CH3_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH3_S  0
+
+/** H264_DMA_IN_ARB_CH3_REG register
+ *  RX CH3 arb register
+ */
+#define H264_DMA_IN_ARB_CH3_REG (DR_REG_H264_DMA_BASE + 0x840)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH3    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH3_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH3_V << H264_DMA_IN_ARB_TOKEN_NUM_CH3_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH3_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH3_S  0
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH3 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH3    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH3_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH3_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH3_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH3_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH3_S  6
+
+/** H264_DMA_IN_ETM_CONF_CH3_REG register
+ *  RX CH3 ETM config register
+ */
+#define H264_DMA_IN_ETM_CONF_CH3_REG (DR_REG_H264_DMA_BASE + 0x848)
+/** H264_DMA_IN_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_IN_ETM_EN_CH3    (BIT(0))
+#define H264_DMA_IN_ETM_EN_CH3_M  (H264_DMA_IN_ETM_EN_CH3_V << H264_DMA_IN_ETM_EN_CH3_S)
+#define H264_DMA_IN_ETM_EN_CH3_V  0x00000001U
+#define H264_DMA_IN_ETM_EN_CH3_S  0
+/** H264_DMA_IN_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_IN_ETM_LOOP_EN_CH3    (BIT(1))
+#define H264_DMA_IN_ETM_LOOP_EN_CH3_M  (H264_DMA_IN_ETM_LOOP_EN_CH3_V << H264_DMA_IN_ETM_LOOP_EN_CH3_S)
+#define H264_DMA_IN_ETM_LOOP_EN_CH3_V  0x00000001U
+#define H264_DMA_IN_ETM_LOOP_EN_CH3_S  1
+/** H264_DMA_IN_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_IN_DSCR_TASK_MAK_CH3    0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH3_M  (H264_DMA_IN_DSCR_TASK_MAK_CH3_V << H264_DMA_IN_DSCR_TASK_MAK_CH3_S)
+#define H264_DMA_IN_DSCR_TASK_MAK_CH3_V  0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH3_S  2
+
+/** H264_DMA_IN_FIFO_CNT_CH3_REG register
+ *  rx CH3 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH3_REG (DR_REG_H264_DMA_BASE + 0x880)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH3_REG register
+ *  rx CH3 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH3_REG (DR_REG_H264_DMA_BASE + 0x884)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3 : RO; bitpos: [7:0]; default: 7;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3_S  0
+
+/** H264_DMA_IN_XADDR_CH3_REG register
+ *  rx CH3 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x888)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH3_M  (H264_DMA_IN_CMDFIFO_XADDR_CH3_V << H264_DMA_IN_CMDFIFO_XADDR_CH3_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH3_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH3_REG register
+ *  rx CH3 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH3_REG (DR_REG_H264_DMA_BASE + 0x88c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3_S  0
+
+/** H264_DMA_IN_CONF0_CH4_REG register
+ *  RX CH4 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH4_REG (DR_REG_H264_DMA_BASE + 0x900)
+/** H264_DMA_INDSCR_BURST_EN_CH4 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define H264_DMA_INDSCR_BURST_EN_CH4    (BIT(2))
+#define H264_DMA_INDSCR_BURST_EN_CH4_M  (H264_DMA_INDSCR_BURST_EN_CH4_V << H264_DMA_INDSCR_BURST_EN_CH4_S)
+#define H264_DMA_INDSCR_BURST_EN_CH4_V  0x00000001U
+#define H264_DMA_INDSCR_BURST_EN_CH4_S  2
+/** H264_DMA_IN_ECC_AES_EN_CH4 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH4    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH4_M  (H264_DMA_IN_ECC_AES_EN_CH4_V << H264_DMA_IN_ECC_AES_EN_CH4_S)
+#define H264_DMA_IN_ECC_AES_EN_CH4_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH4_S  3
+/** H264_DMA_IN_CHECK_OWNER_CH4 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_IN_CHECK_OWNER_CH4    (BIT(4))
+#define H264_DMA_IN_CHECK_OWNER_CH4_M  (H264_DMA_IN_CHECK_OWNER_CH4_V << H264_DMA_IN_CHECK_OWNER_CH4_S)
+#define H264_DMA_IN_CHECK_OWNER_CH4_V  0x00000001U
+#define H264_DMA_IN_CHECK_OWNER_CH4_S  4
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH4 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH4    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH4_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH4_V << H264_DMA_IN_MEM_BURST_LENGTH_CH4_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH4_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH4_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH4 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH4    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH4_M  (H264_DMA_IN_PAGE_BOUND_EN_CH4_V << H264_DMA_IN_PAGE_BOUND_EN_CH4_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH4_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH4_S  12
+/** H264_DMA_IN_RST_CH4 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH4    (BIT(24))
+#define H264_DMA_IN_RST_CH4_M  (H264_DMA_IN_RST_CH4_V << H264_DMA_IN_RST_CH4_S)
+#define H264_DMA_IN_RST_CH4_V  0x00000001U
+#define H264_DMA_IN_RST_CH4_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH4 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH4    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH4_M  (H264_DMA_IN_CMD_DISABLE_CH4_V << H264_DMA_IN_CMD_DISABLE_CH4_S)
+#define H264_DMA_IN_CMD_DISABLE_CH4_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH4_S  25
+/** H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4    (BIT(26))
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4_M  (H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4_V << H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4_S)
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4_V  0x00000001U
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4_S  26
+
+/** H264_DMA_IN_INT_RAW_CH4_REG register
+ *  RX CH4  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH4_REG (DR_REG_H264_DMA_BASE + 0x904)
+/** H264_DMA_IN_DONE_CH4_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 1.
+ */
+#define H264_DMA_IN_DONE_CH4_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH4_INT_RAW_M  (H264_DMA_IN_DONE_CH4_INT_RAW_V << H264_DMA_IN_DONE_CH4_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH4_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 1.
+ */
+#define H264_DMA_IN_SUC_EOF_CH4_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH4_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH4_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH4_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH4_INT_RAW_S  1
+/** H264_DMA_IN_ERR_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define H264_DMA_IN_ERR_EOF_CH4_INT_RAW    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH4_INT_RAW_M  (H264_DMA_IN_ERR_EOF_CH4_INT_RAW_V << H264_DMA_IN_ERR_EOF_CH4_INT_RAW_S)
+#define H264_DMA_IN_ERR_EOF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH4_INT_RAW_S  2
+/** H264_DMA_IN_DSCR_ERR_CH4_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 1.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_RAW    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_RAW_M  (H264_DMA_IN_DSCR_ERR_CH4_INT_RAW_V << H264_DMA_IN_DSCR_ERR_CH4_INT_RAW_S)
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_RAW_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW_M  (H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW_V << H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW_M  (H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW_V << H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_M  (H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_V << H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW_M  (H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW_V << H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW_S  9
+
+/** H264_DMA_IN_INT_ENA_CH4_REG register
+ *  RX CH4  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH4_REG (DR_REG_H264_DMA_BASE + 0x908)
+/** H264_DMA_IN_DONE_CH4_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH4_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH4_INT_ENA_M  (H264_DMA_IN_DONE_CH4_INT_ENA_V << H264_DMA_IN_DONE_CH4_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH4_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH4_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH4_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH4_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ENA_S  1
+/** H264_DMA_IN_ERR_EOF_CH4_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ENA    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ENA_M  (H264_DMA_IN_ERR_EOF_CH4_INT_ENA_V << H264_DMA_IN_ERR_EOF_CH4_INT_ENA_S)
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ENA_S  2
+/** H264_DMA_IN_DSCR_ERR_CH4_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ENA    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ENA_M  (H264_DMA_IN_DSCR_ERR_CH4_INT_ENA_V << H264_DMA_IN_DSCR_ERR_CH4_INT_ENA_S)
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ENA_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA_M  (H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA_V << H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA_M  (H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA_V << H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_M  (H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_V << H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA_M  (H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA_V << H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA_S  9
+
+/** H264_DMA_IN_INT_ST_CH4_REG register
+ *  RX CH4  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH4_REG (DR_REG_H264_DMA_BASE + 0x90c)
+/** H264_DMA_IN_DONE_CH4_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH4_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH4_INT_ST_M  (H264_DMA_IN_DONE_CH4_INT_ST_V << H264_DMA_IN_DONE_CH4_INT_ST_S)
+#define H264_DMA_IN_DONE_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH4_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH4_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH4_INT_ST_V << H264_DMA_IN_SUC_EOF_CH4_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ST_S  1
+/** H264_DMA_IN_ERR_EOF_CH4_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ST    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ST_M  (H264_DMA_IN_ERR_EOF_CH4_INT_ST_V << H264_DMA_IN_ERR_EOF_CH4_INT_ST_S)
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ST_S  2
+/** H264_DMA_IN_DSCR_ERR_CH4_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ST    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ST_M  (H264_DMA_IN_DSCR_ERR_CH4_INT_ST_V << H264_DMA_IN_DSCR_ERR_CH4_INT_ST_S)
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ST_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ST    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH4_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH4_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ST_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH4_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ST    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH4_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH4_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ST_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH4_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ST    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ST_M  (H264_DMA_INFIFO_OVF_L2_CH4_INT_ST_V << H264_DMA_INFIFO_OVF_L2_CH4_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ST_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH4_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ST    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ST_M  (H264_DMA_INFIFO_UDF_L2_CH4_INT_ST_V << H264_DMA_INFIFO_UDF_L2_CH4_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ST_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST_M  (H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST_V << H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST_M  (H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST_V << H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST_S  9
+
+/** H264_DMA_IN_INT_CLR_CH4_REG register
+ *  RX CH4  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH4_REG (DR_REG_H264_DMA_BASE + 0x910)
+/** H264_DMA_IN_DONE_CH4_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH4_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH4_INT_CLR_M  (H264_DMA_IN_DONE_CH4_INT_CLR_V << H264_DMA_IN_DONE_CH4_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH4_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH4_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH4_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH4_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH4_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH4_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH4_INT_CLR_S  1
+/** H264_DMA_IN_ERR_EOF_CH4_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH4_INT_CLR    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH4_INT_CLR_M  (H264_DMA_IN_ERR_EOF_CH4_INT_CLR_V << H264_DMA_IN_ERR_EOF_CH4_INT_CLR_S)
+#define H264_DMA_IN_ERR_EOF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH4_INT_CLR_S  2
+/** H264_DMA_IN_DSCR_ERR_CH4_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_CLR    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_CLR_M  (H264_DMA_IN_DSCR_ERR_CH4_INT_CLR_V << H264_DMA_IN_DSCR_ERR_CH4_INT_CLR_S)
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_CLR_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR_M  (H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR_V << H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR_M  (H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR_V << H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_M  (H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_V << H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR_M  (H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR_V << H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR_S  9
+
+/** H264_DMA_INFIFO_STATUS_CH4_REG register
+ *  RX CH4 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH4_REG (DR_REG_H264_DMA_BASE + 0x914)
+/** H264_DMA_INFIFO_FULL_L2_CH4 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_FULL_L2_CH4    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L2_CH4_M  (H264_DMA_INFIFO_FULL_L2_CH4_V << H264_DMA_INFIFO_FULL_L2_CH4_S)
+#define H264_DMA_INFIFO_FULL_L2_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L2_CH4_S  0
+/** H264_DMA_INFIFO_EMPTY_L2_CH4 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_EMPTY_L2_CH4    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L2_CH4_M  (H264_DMA_INFIFO_EMPTY_L2_CH4_V << H264_DMA_INFIFO_EMPTY_L2_CH4_S)
+#define H264_DMA_INFIFO_EMPTY_L2_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L2_CH4_S  1
+/** H264_DMA_INFIFO_CNT_L2_CH4 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define H264_DMA_INFIFO_CNT_L2_CH4    0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH4_M  (H264_DMA_INFIFO_CNT_L2_CH4_V << H264_DMA_INFIFO_CNT_L2_CH4_S)
+#define H264_DMA_INFIFO_CNT_L2_CH4_V  0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH4_S  2
+/** H264_DMA_INFIFO_FULL_L1_CH4 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH4    (BIT(6))
+#define H264_DMA_INFIFO_FULL_L1_CH4_M  (H264_DMA_INFIFO_FULL_L1_CH4_V << H264_DMA_INFIFO_FULL_L1_CH4_S)
+#define H264_DMA_INFIFO_FULL_L1_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH4_S  6
+/** H264_DMA_INFIFO_EMPTY_L1_CH4 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH4    (BIT(7))
+#define H264_DMA_INFIFO_EMPTY_L1_CH4_M  (H264_DMA_INFIFO_EMPTY_L1_CH4_V << H264_DMA_INFIFO_EMPTY_L1_CH4_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH4_S  7
+/** H264_DMA_INFIFO_CNT_L1_CH4 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH4    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH4_M  (H264_DMA_INFIFO_CNT_L1_CH4_V << H264_DMA_INFIFO_CNT_L1_CH4_S)
+#define H264_DMA_INFIFO_CNT_L1_CH4_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH4_S  8
+/** H264_DMA_INFIFO_FULL_L3_CH4 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L3_CH4    (BIT(16))
+#define H264_DMA_INFIFO_FULL_L3_CH4_M  (H264_DMA_INFIFO_FULL_L3_CH4_V << H264_DMA_INFIFO_FULL_L3_CH4_S)
+#define H264_DMA_INFIFO_FULL_L3_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L3_CH4_S  16
+/** H264_DMA_INFIFO_EMPTY_L3_CH4 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L3_CH4    (BIT(17))
+#define H264_DMA_INFIFO_EMPTY_L3_CH4_M  (H264_DMA_INFIFO_EMPTY_L3_CH4_V << H264_DMA_INFIFO_EMPTY_L3_CH4_S)
+#define H264_DMA_INFIFO_EMPTY_L3_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L3_CH4_S  17
+/** H264_DMA_INFIFO_CNT_L3_CH4 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L3_CH4    0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH4_M  (H264_DMA_INFIFO_CNT_L3_CH4_V << H264_DMA_INFIFO_CNT_L3_CH4_S)
+#define H264_DMA_INFIFO_CNT_L3_CH4_V  0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH4_S  18
+
+/** H264_DMA_IN_POP_CH4_REG register
+ *  RX CH4 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH4_REG (DR_REG_H264_DMA_BASE + 0x918)
+/** H264_DMA_INFIFO_RDATA_CH4 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH4    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH4_M  (H264_DMA_INFIFO_RDATA_CH4_V << H264_DMA_INFIFO_RDATA_CH4_S)
+#define H264_DMA_INFIFO_RDATA_CH4_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH4_S  0
+/** H264_DMA_INFIFO_POP_CH4 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH4    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH4_M  (H264_DMA_INFIFO_POP_CH4_V << H264_DMA_INFIFO_POP_CH4_S)
+#define H264_DMA_INFIFO_POP_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH4_S  11
+
+/** H264_DMA_IN_LINK_CONF_CH4_REG register
+ *  RX CH4 in_link dscr ctrl register
+ */
+#define H264_DMA_IN_LINK_CONF_CH4_REG (DR_REG_H264_DMA_BASE + 0x91c)
+/** H264_DMA_INLINK_AUTO_RET_CH4 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_INLINK_AUTO_RET_CH4    (BIT(20))
+#define H264_DMA_INLINK_AUTO_RET_CH4_M  (H264_DMA_INLINK_AUTO_RET_CH4_V << H264_DMA_INLINK_AUTO_RET_CH4_S)
+#define H264_DMA_INLINK_AUTO_RET_CH4_V  0x00000001U
+#define H264_DMA_INLINK_AUTO_RET_CH4_S  20
+/** H264_DMA_INLINK_STOP_CH4 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_STOP_CH4    (BIT(21))
+#define H264_DMA_INLINK_STOP_CH4_M  (H264_DMA_INLINK_STOP_CH4_V << H264_DMA_INLINK_STOP_CH4_S)
+#define H264_DMA_INLINK_STOP_CH4_V  0x00000001U
+#define H264_DMA_INLINK_STOP_CH4_S  21
+/** H264_DMA_INLINK_START_CH4 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_START_CH4    (BIT(22))
+#define H264_DMA_INLINK_START_CH4_M  (H264_DMA_INLINK_START_CH4_V << H264_DMA_INLINK_START_CH4_S)
+#define H264_DMA_INLINK_START_CH4_V  0x00000001U
+#define H264_DMA_INLINK_START_CH4_S  22
+/** H264_DMA_INLINK_RESTART_CH4 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define H264_DMA_INLINK_RESTART_CH4    (BIT(23))
+#define H264_DMA_INLINK_RESTART_CH4_M  (H264_DMA_INLINK_RESTART_CH4_V << H264_DMA_INLINK_RESTART_CH4_S)
+#define H264_DMA_INLINK_RESTART_CH4_V  0x00000001U
+#define H264_DMA_INLINK_RESTART_CH4_S  23
+/** H264_DMA_INLINK_PARK_CH4 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define H264_DMA_INLINK_PARK_CH4    (BIT(24))
+#define H264_DMA_INLINK_PARK_CH4_M  (H264_DMA_INLINK_PARK_CH4_V << H264_DMA_INLINK_PARK_CH4_S)
+#define H264_DMA_INLINK_PARK_CH4_V  0x00000001U
+#define H264_DMA_INLINK_PARK_CH4_S  24
+
+/** H264_DMA_IN_LINK_ADDR_CH4_REG register
+ *  RX CH4 in_link dscr addr register
+ */
+#define H264_DMA_IN_LINK_ADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x920)
+/** H264_DMA_INLINK_ADDR_CH4 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_ADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH4_M  (H264_DMA_INLINK_ADDR_CH4_V << H264_DMA_INLINK_ADDR_CH4_S)
+#define H264_DMA_INLINK_ADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH4_S  0
+
+/** H264_DMA_IN_STATE_CH4_REG register
+ *  RX CH4 state register
+ */
+#define H264_DMA_IN_STATE_CH4_REG (DR_REG_H264_DMA_BASE + 0x924)
+/** H264_DMA_INLINK_DSCR_ADDR_CH4 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_DSCR_ADDR_CH4    0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH4_M  (H264_DMA_INLINK_DSCR_ADDR_CH4_V << H264_DMA_INLINK_DSCR_ADDR_CH4_S)
+#define H264_DMA_INLINK_DSCR_ADDR_CH4_V  0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH4_S  0
+/** H264_DMA_IN_DSCR_STATE_CH4 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_IN_DSCR_STATE_CH4    0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH4_M  (H264_DMA_IN_DSCR_STATE_CH4_V << H264_DMA_IN_DSCR_STATE_CH4_S)
+#define H264_DMA_IN_DSCR_STATE_CH4_V  0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH4_S  18
+/** H264_DMA_IN_STATE_CH4 : RO; bitpos: [22:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH4    0x00000007U
+#define H264_DMA_IN_STATE_CH4_M  (H264_DMA_IN_STATE_CH4_V << H264_DMA_IN_STATE_CH4_S)
+#define H264_DMA_IN_STATE_CH4_V  0x00000007U
+#define H264_DMA_IN_STATE_CH4_S  20
+/** H264_DMA_IN_RESET_AVAIL_CH4 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH4    (BIT(23))
+#define H264_DMA_IN_RESET_AVAIL_CH4_M  (H264_DMA_IN_RESET_AVAIL_CH4_V << H264_DMA_IN_RESET_AVAIL_CH4_S)
+#define H264_DMA_IN_RESET_AVAIL_CH4_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH4_S  23
+
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_REG register
+ *  RX CH4 eof des addr register
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x928)
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_M  (H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_V << H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_S)
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_S  0
+
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_REG register
+ *  RX CH4 err eof des addr register
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x92c)
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_M  (H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_V << H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_S)
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_S  0
+
+/** H264_DMA_IN_DSCR_CH4_REG register
+ *  RX CH4 next dscr addr register
+ */
+#define H264_DMA_IN_DSCR_CH4_REG (DR_REG_H264_DMA_BASE + 0x930)
+/** H264_DMA_INLINK_DSCR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define H264_DMA_INLINK_DSCR_CH4    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH4_M  (H264_DMA_INLINK_DSCR_CH4_V << H264_DMA_INLINK_DSCR_CH4_S)
+#define H264_DMA_INLINK_DSCR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH4_S  0
+
+/** H264_DMA_IN_DSCR_BF0_CH4_REG register
+ *  RX CH4 last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF0_CH4_REG (DR_REG_H264_DMA_BASE + 0x934)
+/** H264_DMA_INLINK_DSCR_BF0_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define H264_DMA_INLINK_DSCR_BF0_CH4    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH4_M  (H264_DMA_INLINK_DSCR_BF0_CH4_V << H264_DMA_INLINK_DSCR_BF0_CH4_S)
+#define H264_DMA_INLINK_DSCR_BF0_CH4_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH4_S  0
+
+/** H264_DMA_IN_DSCR_BF1_CH4_REG register
+ *  RX CH4 second-to-last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF1_CH4_REG (DR_REG_H264_DMA_BASE + 0x938)
+/** H264_DMA_INLINK_DSCR_BF1_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define H264_DMA_INLINK_DSCR_BF1_CH4    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH4_M  (H264_DMA_INLINK_DSCR_BF1_CH4_V << H264_DMA_INLINK_DSCR_BF1_CH4_S)
+#define H264_DMA_INLINK_DSCR_BF1_CH4_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH4_S  0
+
+/** H264_DMA_IN_ARB_CH4_REG register
+ *  RX CH4 arb register
+ */
+#define H264_DMA_IN_ARB_CH4_REG (DR_REG_H264_DMA_BASE + 0x940)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH4 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH4    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH4_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH4_V << H264_DMA_IN_ARB_TOKEN_NUM_CH4_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH4_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH4_S  0
+/** H264_DMA_EXTER_IN_ARB_PRIORITY_CH4 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH4    0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH4_M  (H264_DMA_EXTER_IN_ARB_PRIORITY_CH4_V << H264_DMA_EXTER_IN_ARB_PRIORITY_CH4_S)
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH4_V  0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH4_S  4
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH4 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH4    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH4_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH4_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH4_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH4_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH4_S  6
+
+/** H264_DMA_IN_ETM_CONF_CH4_REG register
+ *  RX CH4 ETM config register
+ */
+#define H264_DMA_IN_ETM_CONF_CH4_REG (DR_REG_H264_DMA_BASE + 0x948)
+/** H264_DMA_IN_ETM_EN_CH4 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_IN_ETM_EN_CH4    (BIT(0))
+#define H264_DMA_IN_ETM_EN_CH4_M  (H264_DMA_IN_ETM_EN_CH4_V << H264_DMA_IN_ETM_EN_CH4_S)
+#define H264_DMA_IN_ETM_EN_CH4_V  0x00000001U
+#define H264_DMA_IN_ETM_EN_CH4_S  0
+/** H264_DMA_IN_ETM_LOOP_EN_CH4 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_IN_ETM_LOOP_EN_CH4    (BIT(1))
+#define H264_DMA_IN_ETM_LOOP_EN_CH4_M  (H264_DMA_IN_ETM_LOOP_EN_CH4_V << H264_DMA_IN_ETM_LOOP_EN_CH4_S)
+#define H264_DMA_IN_ETM_LOOP_EN_CH4_V  0x00000001U
+#define H264_DMA_IN_ETM_LOOP_EN_CH4_S  1
+/** H264_DMA_IN_DSCR_TASK_MAK_CH4 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_IN_DSCR_TASK_MAK_CH4    0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH4_M  (H264_DMA_IN_DSCR_TASK_MAK_CH4_V << H264_DMA_IN_DSCR_TASK_MAK_CH4_S)
+#define H264_DMA_IN_DSCR_TASK_MAK_CH4_V  0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH4_S  2
+
+/** H264_DMA_IN_FIFO_CNT_CH4_REG register
+ *  rx CH4 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH4_REG (DR_REG_H264_DMA_BASE + 0x980)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH4_REG register
+ *  rx CH4 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH4_REG (DR_REG_H264_DMA_BASE + 0x984)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4 : RO; bitpos: [7:0]; default: 7;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4_S  0
+
+/** H264_DMA_IN_XADDR_CH4_REG register
+ *  rx CH4 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x988)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH4_M  (H264_DMA_IN_CMDFIFO_XADDR_CH4_V << H264_DMA_IN_CMDFIFO_XADDR_CH4_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH4_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH4_REG register
+ *  rx CH4 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH4_REG (DR_REG_H264_DMA_BASE + 0x98c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4_S  0
+
+/** H264_DMA_IN_CONF0_CH5_REG register
+ *  RX CH5 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH5_REG (DR_REG_H264_DMA_BASE + 0xa00)
+/** H264_DMA_IN_ECC_AES_EN_CH5 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH5    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH5_M  (H264_DMA_IN_ECC_AES_EN_CH5_V << H264_DMA_IN_ECC_AES_EN_CH5_S)
+#define H264_DMA_IN_ECC_AES_EN_CH5_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH5_S  3
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH5 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH5    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH5_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH5_V << H264_DMA_IN_MEM_BURST_LENGTH_CH5_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH5_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH5_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH5 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH5    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH5_M  (H264_DMA_IN_PAGE_BOUND_EN_CH5_V << H264_DMA_IN_PAGE_BOUND_EN_CH5_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH5_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH5_S  12
+/** H264_DMA_IN_RST_CH5 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH5    (BIT(24))
+#define H264_DMA_IN_RST_CH5_M  (H264_DMA_IN_RST_CH5_V << H264_DMA_IN_RST_CH5_S)
+#define H264_DMA_IN_RST_CH5_V  0x00000001U
+#define H264_DMA_IN_RST_CH5_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH5 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH5    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH5_M  (H264_DMA_IN_CMD_DISABLE_CH5_V << H264_DMA_IN_CMD_DISABLE_CH5_S)
+#define H264_DMA_IN_CMD_DISABLE_CH5_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH5_S  25
+
+/** H264_DMA_IN_CONF1_CH5_REG register
+ *  RX CH5 config1 register
+ */
+#define H264_DMA_IN_CONF1_CH5_REG (DR_REG_H264_DMA_BASE + 0xa04)
+/** H264_DMA_BLOCK_START_ADDR_CH5 : R/W; bitpos: [31:0]; default: 0;
+ *  RX Channel 5 destination start address
+ */
+#define H264_DMA_BLOCK_START_ADDR_CH5    0xFFFFFFFFU
+#define H264_DMA_BLOCK_START_ADDR_CH5_M  (H264_DMA_BLOCK_START_ADDR_CH5_V << H264_DMA_BLOCK_START_ADDR_CH5_S)
+#define H264_DMA_BLOCK_START_ADDR_CH5_V  0xFFFFFFFFU
+#define H264_DMA_BLOCK_START_ADDR_CH5_S  0
+
+/** H264_DMA_IN_CONF2_CH5_REG register
+ *  RX CH5 config2 register
+ */
+#define H264_DMA_IN_CONF2_CH5_REG (DR_REG_H264_DMA_BASE + 0xa08)
+/** H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5 : R/W; bitpos: [15:0]; default: 30720;
+ *  The number of bytes contained in a row block 12line in RX channel 5
+ */
+#define H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5    0x0000FFFFU
+#define H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5_M  (H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5_V << H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5_S)
+#define H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5_V  0x0000FFFFU
+#define H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5_S  0
+/** H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5 : R/W; bitpos: [31:16]; default: 15360;
+ *  The number of bytes contained in a row block 4line in RX channel 5
+ */
+#define H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5    0x0000FFFFU
+#define H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5_M  (H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5_V << H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5_S)
+#define H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5_V  0x0000FFFFU
+#define H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5_S  16
+
+/** H264_DMA_IN_CONF3_CH5_REG register
+ *  RX CH5 config3 register
+ */
+#define H264_DMA_IN_CONF3_CH5_REG (DR_REG_H264_DMA_BASE + 0xa0c)
+/** H264_DMA_BLOCK_LENGTH_12LINE_CH5 : R/W; bitpos: [13:0]; default: 256;
+ *  The number of bytes contained in a block 12line
+ */
+#define H264_DMA_BLOCK_LENGTH_12LINE_CH5    0x00003FFFU
+#define H264_DMA_BLOCK_LENGTH_12LINE_CH5_M  (H264_DMA_BLOCK_LENGTH_12LINE_CH5_V << H264_DMA_BLOCK_LENGTH_12LINE_CH5_S)
+#define H264_DMA_BLOCK_LENGTH_12LINE_CH5_V  0x00003FFFU
+#define H264_DMA_BLOCK_LENGTH_12LINE_CH5_S  0
+/** H264_DMA_BLOCK_LENGTH_4LINE_CH5 : R/W; bitpos: [27:14]; default: 128;
+ *  The number of bytes contained in a block 4line
+ */
+#define H264_DMA_BLOCK_LENGTH_4LINE_CH5    0x00003FFFU
+#define H264_DMA_BLOCK_LENGTH_4LINE_CH5_M  (H264_DMA_BLOCK_LENGTH_4LINE_CH5_V << H264_DMA_BLOCK_LENGTH_4LINE_CH5_S)
+#define H264_DMA_BLOCK_LENGTH_4LINE_CH5_V  0x00003FFFU
+#define H264_DMA_BLOCK_LENGTH_4LINE_CH5_S  14
+
+/** H264_DMA_IN_INT_RAW_CH5_REG register
+ *  RX CH5  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH5_REG (DR_REG_H264_DMA_BASE + 0xa10)
+/** H264_DMA_IN_DONE_CH5_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 1.
+ */
+#define H264_DMA_IN_DONE_CH5_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH5_INT_RAW_M  (H264_DMA_IN_DONE_CH5_INT_RAW_V << H264_DMA_IN_DONE_CH5_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH5_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH5_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH5_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 1.
+ */
+#define H264_DMA_IN_SUC_EOF_CH5_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH5_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH5_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH5_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH5_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH5_INT_RAW_S  1
+/** H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW    (BIT(2))
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW_S  2
+/** H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW    (BIT(3))
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW_S  3
+/** H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW    (BIT(4))
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_M  (H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_V << H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_S)
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_V  0x00000001U
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_S  4
+
+/** H264_DMA_IN_INT_ENA_CH5_REG register
+ *  RX CH5  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH5_REG (DR_REG_H264_DMA_BASE + 0xa14)
+/** H264_DMA_IN_DONE_CH5_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH5_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH5_INT_ENA_M  (H264_DMA_IN_DONE_CH5_INT_ENA_V << H264_DMA_IN_DONE_CH5_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH5_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH5_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH5_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH5_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH5_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ENA_S  1
+/** H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA    (BIT(2))
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA_S  2
+/** H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA    (BIT(3))
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA_S  3
+/** H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA    (BIT(4))
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_M  (H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_V << H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_S)
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_V  0x00000001U
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_S  4
+
+/** H264_DMA_IN_INT_ST_CH5_REG register
+ *  RX CH5  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH5_REG (DR_REG_H264_DMA_BASE + 0xa18)
+/** H264_DMA_IN_DONE_CH5_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH5_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH5_INT_ST_M  (H264_DMA_IN_DONE_CH5_INT_ST_V << H264_DMA_IN_DONE_CH5_INT_ST_S)
+#define H264_DMA_IN_DONE_CH5_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH5_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH5_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH5_INT_ST_V << H264_DMA_IN_SUC_EOF_CH5_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ST_S  1
+/** H264_DMA_INFIFO_OVF_L1_CH5_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ST    (BIT(2))
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH5_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH5_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ST_S  2
+/** H264_DMA_INFIFO_UDF_L1_CH5_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ST    (BIT(3))
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH5_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH5_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ST_S  3
+/** H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST    (BIT(4))
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_M  (H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_V << H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_S)
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_V  0x00000001U
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_S  4
+
+/** H264_DMA_IN_INT_CLR_CH5_REG register
+ *  RX CH5  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH5_REG (DR_REG_H264_DMA_BASE + 0xa1c)
+/** H264_DMA_IN_DONE_CH5_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH5_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH5_INT_CLR_M  (H264_DMA_IN_DONE_CH5_INT_CLR_V << H264_DMA_IN_DONE_CH5_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH5_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH5_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH5_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH5_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH5_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH5_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH5_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH5_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH5_INT_CLR_S  1
+/** H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR    (BIT(2))
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR_S  2
+/** H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR    (BIT(3))
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR_S  3
+/** H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR    (BIT(4))
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_M  (H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_V << H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_S)
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_V  0x00000001U
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_S  4
+
+/** H264_DMA_INFIFO_STATUS_CH5_REG register
+ *  RX CH5 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH5_REG (DR_REG_H264_DMA_BASE + 0xa20)
+/** H264_DMA_INFIFO_FULL_L1_CH5 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH5    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L1_CH5_M  (H264_DMA_INFIFO_FULL_L1_CH5_V << H264_DMA_INFIFO_FULL_L1_CH5_S)
+#define H264_DMA_INFIFO_FULL_L1_CH5_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH5_S  0
+/** H264_DMA_INFIFO_EMPTY_L1_CH5 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH5    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L1_CH5_M  (H264_DMA_INFIFO_EMPTY_L1_CH5_V << H264_DMA_INFIFO_EMPTY_L1_CH5_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH5_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH5_S  1
+/** H264_DMA_INFIFO_CNT_L1_CH5 : RO; bitpos: [6:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH5    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH5_M  (H264_DMA_INFIFO_CNT_L1_CH5_V << H264_DMA_INFIFO_CNT_L1_CH5_S)
+#define H264_DMA_INFIFO_CNT_L1_CH5_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH5_S  2
+
+/** H264_DMA_IN_POP_CH5_REG register
+ *  RX CH5 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH5_REG (DR_REG_H264_DMA_BASE + 0xa24)
+/** H264_DMA_INFIFO_RDATA_CH5 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH5    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH5_M  (H264_DMA_INFIFO_RDATA_CH5_V << H264_DMA_INFIFO_RDATA_CH5_S)
+#define H264_DMA_INFIFO_RDATA_CH5_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH5_S  0
+/** H264_DMA_INFIFO_POP_CH5 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH5    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH5_M  (H264_DMA_INFIFO_POP_CH5_V << H264_DMA_INFIFO_POP_CH5_S)
+#define H264_DMA_INFIFO_POP_CH5_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH5_S  11
+
+/** H264_DMA_IN_STATE_CH5_REG register
+ *  RX CH5 state register
+ */
+#define H264_DMA_IN_STATE_CH5_REG (DR_REG_H264_DMA_BASE + 0xa28)
+/** H264_DMA_IN_STATE_CH5 : RO; bitpos: [2:0]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH5    0x00000007U
+#define H264_DMA_IN_STATE_CH5_M  (H264_DMA_IN_STATE_CH5_V << H264_DMA_IN_STATE_CH5_S)
+#define H264_DMA_IN_STATE_CH5_V  0x00000007U
+#define H264_DMA_IN_STATE_CH5_S  0
+/** H264_DMA_IN_RESET_AVAIL_CH5 : RO; bitpos: [3]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH5    (BIT(3))
+#define H264_DMA_IN_RESET_AVAIL_CH5_M  (H264_DMA_IN_RESET_AVAIL_CH5_V << H264_DMA_IN_RESET_AVAIL_CH5_S)
+#define H264_DMA_IN_RESET_AVAIL_CH5_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH5_S  3
+
+/** H264_DMA_IN_ARB_CH5_REG register
+ *  RX CH5 arb register
+ */
+#define H264_DMA_IN_ARB_CH5_REG (DR_REG_H264_DMA_BASE + 0xa40)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH5 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH5    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH5_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH5_V << H264_DMA_IN_ARB_TOKEN_NUM_CH5_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH5_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH5_S  0
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH5 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH5    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH5_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH5_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH5_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH5_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH5_S  6
+
+/** H264_DMA_IN_FIFO_CNT_CH5_REG register
+ *  rx CH5 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH5_REG (DR_REG_H264_DMA_BASE + 0xa80)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH5_REG register
+ *  rx CH5 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH5_REG (DR_REG_H264_DMA_BASE + 0xa84)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5 : RO; bitpos: [7:0]; default: 255;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5_S  0
+
+/** H264_DMA_IN_XADDR_CH5_REG register
+ *  rx CH5 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH5_REG (DR_REG_H264_DMA_BASE + 0xa88)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH5 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH5    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH5_M  (H264_DMA_IN_CMDFIFO_XADDR_CH5_V << H264_DMA_IN_CMDFIFO_XADDR_CH5_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH5_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH5_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH5_REG register
+ *  rx CH5 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH5_REG (DR_REG_H264_DMA_BASE + 0xa8c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5_S  0
+
+/** H264_DMA_INTER_AXI_ERR_REG register
+ *  inter memory axi err register
+ */
+#define H264_DMA_INTER_AXI_ERR_REG (DR_REG_H264_DMA_BASE + 0xb00)
+/** H264_DMA_INTER_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0;
+ *  AXI read id err cnt
+ */
+#define H264_DMA_INTER_RID_ERR_CNT    0x0000000FU
+#define H264_DMA_INTER_RID_ERR_CNT_M  (H264_DMA_INTER_RID_ERR_CNT_V << H264_DMA_INTER_RID_ERR_CNT_S)
+#define H264_DMA_INTER_RID_ERR_CNT_V  0x0000000FU
+#define H264_DMA_INTER_RID_ERR_CNT_S  0
+/** H264_DMA_INTER_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0;
+ *  AXI read resp err cnt
+ */
+#define H264_DMA_INTER_RRESP_ERR_CNT    0x0000000FU
+#define H264_DMA_INTER_RRESP_ERR_CNT_M  (H264_DMA_INTER_RRESP_ERR_CNT_V << H264_DMA_INTER_RRESP_ERR_CNT_S)
+#define H264_DMA_INTER_RRESP_ERR_CNT_V  0x0000000FU
+#define H264_DMA_INTER_RRESP_ERR_CNT_S  4
+/** H264_DMA_INTER_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0;
+ *  AXI write resp err cnt
+ */
+#define H264_DMA_INTER_WRESP_ERR_CNT    0x0000000FU
+#define H264_DMA_INTER_WRESP_ERR_CNT_M  (H264_DMA_INTER_WRESP_ERR_CNT_V << H264_DMA_INTER_WRESP_ERR_CNT_S)
+#define H264_DMA_INTER_WRESP_ERR_CNT_V  0x0000000FU
+#define H264_DMA_INTER_WRESP_ERR_CNT_S  8
+/** H264_DMA_INTER_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0;
+ *  AXI read cmd fifo remain cmd count
+ */
+#define H264_DMA_INTER_RD_FIFO_CNT    0x00000007U
+#define H264_DMA_INTER_RD_FIFO_CNT_M  (H264_DMA_INTER_RD_FIFO_CNT_V << H264_DMA_INTER_RD_FIFO_CNT_S)
+#define H264_DMA_INTER_RD_FIFO_CNT_V  0x00000007U
+#define H264_DMA_INTER_RD_FIFO_CNT_S  12
+/** H264_DMA_INTER_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0;
+ *  AXI read backup cmd fifo remain cmd count
+ */
+#define H264_DMA_INTER_RD_BAK_FIFO_CNT    0x0000000FU
+#define H264_DMA_INTER_RD_BAK_FIFO_CNT_M  (H264_DMA_INTER_RD_BAK_FIFO_CNT_V << H264_DMA_INTER_RD_BAK_FIFO_CNT_S)
+#define H264_DMA_INTER_RD_BAK_FIFO_CNT_V  0x0000000FU
+#define H264_DMA_INTER_RD_BAK_FIFO_CNT_S  15
+/** H264_DMA_INTER_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0;
+ *  AXI write cmd fifo remain cmd count
+ */
+#define H264_DMA_INTER_WR_FIFO_CNT    0x00000007U
+#define H264_DMA_INTER_WR_FIFO_CNT_M  (H264_DMA_INTER_WR_FIFO_CNT_V << H264_DMA_INTER_WR_FIFO_CNT_S)
+#define H264_DMA_INTER_WR_FIFO_CNT_V  0x00000007U
+#define H264_DMA_INTER_WR_FIFO_CNT_S  19
+/** H264_DMA_INTER_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0;
+ *  AXI write backup cmd fifo remain cmd count
+ */
+#define H264_DMA_INTER_WR_BAK_FIFO_CNT    0x0000000FU
+#define H264_DMA_INTER_WR_BAK_FIFO_CNT_M  (H264_DMA_INTER_WR_BAK_FIFO_CNT_V << H264_DMA_INTER_WR_BAK_FIFO_CNT_S)
+#define H264_DMA_INTER_WR_BAK_FIFO_CNT_V  0x0000000FU
+#define H264_DMA_INTER_WR_BAK_FIFO_CNT_S  22
+
+/** H264_DMA_EXTER_AXI_ERR_REG register
+ *  exter memory axi err register
+ */
+#define H264_DMA_EXTER_AXI_ERR_REG (DR_REG_H264_DMA_BASE + 0xb04)
+/** H264_DMA_EXTER_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0;
+ *  AXI read id err cnt
+ */
+#define H264_DMA_EXTER_RID_ERR_CNT    0x0000000FU
+#define H264_DMA_EXTER_RID_ERR_CNT_M  (H264_DMA_EXTER_RID_ERR_CNT_V << H264_DMA_EXTER_RID_ERR_CNT_S)
+#define H264_DMA_EXTER_RID_ERR_CNT_V  0x0000000FU
+#define H264_DMA_EXTER_RID_ERR_CNT_S  0
+/** H264_DMA_EXTER_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0;
+ *  AXI read resp err cnt
+ */
+#define H264_DMA_EXTER_RRESP_ERR_CNT    0x0000000FU
+#define H264_DMA_EXTER_RRESP_ERR_CNT_M  (H264_DMA_EXTER_RRESP_ERR_CNT_V << H264_DMA_EXTER_RRESP_ERR_CNT_S)
+#define H264_DMA_EXTER_RRESP_ERR_CNT_V  0x0000000FU
+#define H264_DMA_EXTER_RRESP_ERR_CNT_S  4
+/** H264_DMA_EXTER_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0;
+ *  AXI write resp err cnt
+ */
+#define H264_DMA_EXTER_WRESP_ERR_CNT    0x0000000FU
+#define H264_DMA_EXTER_WRESP_ERR_CNT_M  (H264_DMA_EXTER_WRESP_ERR_CNT_V << H264_DMA_EXTER_WRESP_ERR_CNT_S)
+#define H264_DMA_EXTER_WRESP_ERR_CNT_V  0x0000000FU
+#define H264_DMA_EXTER_WRESP_ERR_CNT_S  8
+/** H264_DMA_EXTER_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0;
+ *  AXI read cmd fifo remain cmd count
+ */
+#define H264_DMA_EXTER_RD_FIFO_CNT    0x00000007U
+#define H264_DMA_EXTER_RD_FIFO_CNT_M  (H264_DMA_EXTER_RD_FIFO_CNT_V << H264_DMA_EXTER_RD_FIFO_CNT_S)
+#define H264_DMA_EXTER_RD_FIFO_CNT_V  0x00000007U
+#define H264_DMA_EXTER_RD_FIFO_CNT_S  12
+/** H264_DMA_EXTER_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0;
+ *  AXI read backup cmd fifo remain cmd count
+ */
+#define H264_DMA_EXTER_RD_BAK_FIFO_CNT    0x0000000FU
+#define H264_DMA_EXTER_RD_BAK_FIFO_CNT_M  (H264_DMA_EXTER_RD_BAK_FIFO_CNT_V << H264_DMA_EXTER_RD_BAK_FIFO_CNT_S)
+#define H264_DMA_EXTER_RD_BAK_FIFO_CNT_V  0x0000000FU
+#define H264_DMA_EXTER_RD_BAK_FIFO_CNT_S  15
+/** H264_DMA_EXTER_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0;
+ *  AXI write cmd fifo remain cmd count
+ */
+#define H264_DMA_EXTER_WR_FIFO_CNT    0x00000007U
+#define H264_DMA_EXTER_WR_FIFO_CNT_M  (H264_DMA_EXTER_WR_FIFO_CNT_V << H264_DMA_EXTER_WR_FIFO_CNT_S)
+#define H264_DMA_EXTER_WR_FIFO_CNT_V  0x00000007U
+#define H264_DMA_EXTER_WR_FIFO_CNT_S  19
+/** H264_DMA_EXTER_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0;
+ *  AXI write backup cmd fifo remain cmd count
+ */
+#define H264_DMA_EXTER_WR_BAK_FIFO_CNT    0x0000000FU
+#define H264_DMA_EXTER_WR_BAK_FIFO_CNT_M  (H264_DMA_EXTER_WR_BAK_FIFO_CNT_V << H264_DMA_EXTER_WR_BAK_FIFO_CNT_S)
+#define H264_DMA_EXTER_WR_BAK_FIFO_CNT_V  0x0000000FU
+#define H264_DMA_EXTER_WR_BAK_FIFO_CNT_S  22
+
+/** H264_DMA_RST_CONF_REG register
+ *  axi reset config register
+ */
+#define H264_DMA_RST_CONF_REG (DR_REG_H264_DMA_BASE + 0xb08)
+/** H264_DMA_INTER_AXIM_RD_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+ */
+#define H264_DMA_INTER_AXIM_RD_RST    (BIT(0))
+#define H264_DMA_INTER_AXIM_RD_RST_M  (H264_DMA_INTER_AXIM_RD_RST_V << H264_DMA_INTER_AXIM_RD_RST_S)
+#define H264_DMA_INTER_AXIM_RD_RST_V  0x00000001U
+#define H264_DMA_INTER_AXIM_RD_RST_S  0
+/** H264_DMA_INTER_AXIM_WR_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+ */
+#define H264_DMA_INTER_AXIM_WR_RST    (BIT(1))
+#define H264_DMA_INTER_AXIM_WR_RST_M  (H264_DMA_INTER_AXIM_WR_RST_V << H264_DMA_INTER_AXIM_WR_RST_S)
+#define H264_DMA_INTER_AXIM_WR_RST_V  0x00000001U
+#define H264_DMA_INTER_AXIM_WR_RST_S  1
+/** H264_DMA_EXTER_AXIM_RD_RST : R/W; bitpos: [2]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+ */
+#define H264_DMA_EXTER_AXIM_RD_RST    (BIT(2))
+#define H264_DMA_EXTER_AXIM_RD_RST_M  (H264_DMA_EXTER_AXIM_RD_RST_V << H264_DMA_EXTER_AXIM_RD_RST_S)
+#define H264_DMA_EXTER_AXIM_RD_RST_V  0x00000001U
+#define H264_DMA_EXTER_AXIM_RD_RST_S  2
+/** H264_DMA_EXTER_AXIM_WR_RST : R/W; bitpos: [3]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+ */
+#define H264_DMA_EXTER_AXIM_WR_RST    (BIT(3))
+#define H264_DMA_EXTER_AXIM_WR_RST_M  (H264_DMA_EXTER_AXIM_WR_RST_V << H264_DMA_EXTER_AXIM_WR_RST_S)
+#define H264_DMA_EXTER_AXIM_WR_RST_V  0x00000001U
+#define H264_DMA_EXTER_AXIM_WR_RST_S  3
+/** H264_DMA_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define H264_DMA_CLK_EN    (BIT(4))
+#define H264_DMA_CLK_EN_M  (H264_DMA_CLK_EN_V << H264_DMA_CLK_EN_S)
+#define H264_DMA_CLK_EN_V  0x00000001U
+#define H264_DMA_CLK_EN_S  4
+
+/** H264_DMA_INTER_MEM_START_ADDR0_REG register
+ *  Start address of inter memory range0 register
+ */
+#define H264_DMA_INTER_MEM_START_ADDR0_REG (DR_REG_H264_DMA_BASE + 0xb0c)
+/** H264_DMA_ACCESS_INTER_MEM_START_ADDR0 : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR0    0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR0_M  (H264_DMA_ACCESS_INTER_MEM_START_ADDR0_V << H264_DMA_ACCESS_INTER_MEM_START_ADDR0_S)
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR0_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR0_S  0
+
+/** H264_DMA_INTER_MEM_END_ADDR0_REG register
+ *  end address of inter memory range0 register
+ */
+#define H264_DMA_INTER_MEM_END_ADDR0_REG (DR_REG_H264_DMA_BASE + 0xb10)
+/** H264_DMA_ACCESS_INTER_MEM_END_ADDR0 : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR0    0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR0_M  (H264_DMA_ACCESS_INTER_MEM_END_ADDR0_V << H264_DMA_ACCESS_INTER_MEM_END_ADDR0_S)
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR0_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR0_S  0
+
+/** H264_DMA_INTER_MEM_START_ADDR1_REG register
+ *  Start address of inter memory range1 register
+ */
+#define H264_DMA_INTER_MEM_START_ADDR1_REG (DR_REG_H264_DMA_BASE + 0xb14)
+/** H264_DMA_ACCESS_INTER_MEM_START_ADDR1 : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR1    0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR1_M  (H264_DMA_ACCESS_INTER_MEM_START_ADDR1_V << H264_DMA_ACCESS_INTER_MEM_START_ADDR1_S)
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR1_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR1_S  0
+
+/** H264_DMA_INTER_MEM_END_ADDR1_REG register
+ *  end address of inter memory range1 register
+ */
+#define H264_DMA_INTER_MEM_END_ADDR1_REG (DR_REG_H264_DMA_BASE + 0xb18)
+/** H264_DMA_ACCESS_INTER_MEM_END_ADDR1 : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR1    0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR1_M  (H264_DMA_ACCESS_INTER_MEM_END_ADDR1_V << H264_DMA_ACCESS_INTER_MEM_END_ADDR1_S)
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR1_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR1_S  0
+
+/** H264_DMA_EXTER_MEM_START_ADDR0_REG register
+ *  Start address of exter memory range0 register
+ */
+#define H264_DMA_EXTER_MEM_START_ADDR0_REG (DR_REG_H264_DMA_BASE + 0xb20)
+/** H264_DMA_ACCESS_EXTER_MEM_START_ADDR0 : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR0    0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR0_M  (H264_DMA_ACCESS_EXTER_MEM_START_ADDR0_V << H264_DMA_ACCESS_EXTER_MEM_START_ADDR0_S)
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR0_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR0_S  0
+
+/** H264_DMA_EXTER_MEM_END_ADDR0_REG register
+ *  end address of exter memory range0 register
+ */
+#define H264_DMA_EXTER_MEM_END_ADDR0_REG (DR_REG_H264_DMA_BASE + 0xb24)
+/** H264_DMA_ACCESS_EXTER_MEM_END_ADDR0 : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR0    0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR0_M  (H264_DMA_ACCESS_EXTER_MEM_END_ADDR0_V << H264_DMA_ACCESS_EXTER_MEM_END_ADDR0_S)
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR0_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR0_S  0
+
+/** H264_DMA_EXTER_MEM_START_ADDR1_REG register
+ *  Start address of exter memory range1 register
+ */
+#define H264_DMA_EXTER_MEM_START_ADDR1_REG (DR_REG_H264_DMA_BASE + 0xb28)
+/** H264_DMA_ACCESS_EXTER_MEM_START_ADDR1 : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR1    0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR1_M  (H264_DMA_ACCESS_EXTER_MEM_START_ADDR1_V << H264_DMA_ACCESS_EXTER_MEM_START_ADDR1_S)
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR1_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR1_S  0
+
+/** H264_DMA_EXTER_MEM_END_ADDR1_REG register
+ *  end address of exter memory range1 register
+ */
+#define H264_DMA_EXTER_MEM_END_ADDR1_REG (DR_REG_H264_DMA_BASE + 0xb2c)
+/** H264_DMA_ACCESS_EXTER_MEM_END_ADDR1 : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR1    0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR1_M  (H264_DMA_ACCESS_EXTER_MEM_END_ADDR1_V << H264_DMA_ACCESS_EXTER_MEM_END_ADDR1_S)
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR1_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR1_S  0
+
+/** H264_DMA_OUT_ARB_CONFIG_REG register
+ *  reserved
+ */
+#define H264_DMA_OUT_ARB_CONFIG_REG (DR_REG_H264_DMA_BASE + 0xb30)
+/** H264_DMA_OUT_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define H264_DMA_OUT_ARB_TIMEOUT_NUM_M  (H264_DMA_OUT_ARB_TIMEOUT_NUM_V << H264_DMA_OUT_ARB_TIMEOUT_NUM_S)
+#define H264_DMA_OUT_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define H264_DMA_OUT_ARB_TIMEOUT_NUM_S  0
+/** H264_DMA_OUT_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define H264_DMA_OUT_WEIGHT_EN    (BIT(16))
+#define H264_DMA_OUT_WEIGHT_EN_M  (H264_DMA_OUT_WEIGHT_EN_V << H264_DMA_OUT_WEIGHT_EN_S)
+#define H264_DMA_OUT_WEIGHT_EN_V  0x00000001U
+#define H264_DMA_OUT_WEIGHT_EN_S  16
+
+/** H264_DMA_IN_ARB_CONFIG_REG register
+ *  reserved
+ */
+#define H264_DMA_IN_ARB_CONFIG_REG (DR_REG_H264_DMA_BASE + 0xb34)
+/** H264_DMA_IN_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define H264_DMA_IN_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define H264_DMA_IN_ARB_TIMEOUT_NUM_M  (H264_DMA_IN_ARB_TIMEOUT_NUM_V << H264_DMA_IN_ARB_TIMEOUT_NUM_S)
+#define H264_DMA_IN_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define H264_DMA_IN_ARB_TIMEOUT_NUM_S  0
+/** H264_DMA_IN_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define H264_DMA_IN_WEIGHT_EN    (BIT(16))
+#define H264_DMA_IN_WEIGHT_EN_M  (H264_DMA_IN_WEIGHT_EN_V << H264_DMA_IN_WEIGHT_EN_S)
+#define H264_DMA_IN_WEIGHT_EN_V  0x00000001U
+#define H264_DMA_IN_WEIGHT_EN_S  16
+
+/** H264_DMA_DATE_REG register
+ *  reserved
+ */
+#define H264_DMA_DATE_REG (DR_REG_H264_DMA_BASE + 0xb3c)
+/** H264_DMA_DATE : R/W; bitpos: [31:0]; default: 539165699;
+ *  register version.
+ */
+#define H264_DMA_DATE    0xFFFFFFFFU
+#define H264_DMA_DATE_M  (H264_DMA_DATE_V << H264_DMA_DATE_S)
+#define H264_DMA_DATE_V  0xFFFFFFFFU
+#define H264_DMA_DATE_S  0
+
+/** H264_DMA_COUNTER_RST_REG register
+ *  counter reset register
+ */
+#define H264_DMA_COUNTER_RST_REG (DR_REG_H264_DMA_BASE + 0xb50)
+/** H264_DMA_RX_CH0_EXTER_COUNTER_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0 to this bit to reset rx ch0 counter.
+ */
+#define H264_DMA_RX_CH0_EXTER_COUNTER_RST    (BIT(0))
+#define H264_DMA_RX_CH0_EXTER_COUNTER_RST_M  (H264_DMA_RX_CH0_EXTER_COUNTER_RST_V << H264_DMA_RX_CH0_EXTER_COUNTER_RST_S)
+#define H264_DMA_RX_CH0_EXTER_COUNTER_RST_V  0x00000001U
+#define H264_DMA_RX_CH0_EXTER_COUNTER_RST_S  0
+/** H264_DMA_RX_CH1_EXTER_COUNTER_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0 to this bit to reset rx ch1 counter.
+ */
+#define H264_DMA_RX_CH1_EXTER_COUNTER_RST    (BIT(1))
+#define H264_DMA_RX_CH1_EXTER_COUNTER_RST_M  (H264_DMA_RX_CH1_EXTER_COUNTER_RST_V << H264_DMA_RX_CH1_EXTER_COUNTER_RST_S)
+#define H264_DMA_RX_CH1_EXTER_COUNTER_RST_V  0x00000001U
+#define H264_DMA_RX_CH1_EXTER_COUNTER_RST_S  1
+/** H264_DMA_RX_CH2_INTER_COUNTER_RST : R/W; bitpos: [2]; default: 0;
+ *  Write 1 then write 0 to this bit to reset rx ch2 counter.
+ */
+#define H264_DMA_RX_CH2_INTER_COUNTER_RST    (BIT(2))
+#define H264_DMA_RX_CH2_INTER_COUNTER_RST_M  (H264_DMA_RX_CH2_INTER_COUNTER_RST_V << H264_DMA_RX_CH2_INTER_COUNTER_RST_S)
+#define H264_DMA_RX_CH2_INTER_COUNTER_RST_V  0x00000001U
+#define H264_DMA_RX_CH2_INTER_COUNTER_RST_S  2
+/** H264_DMA_RX_CH5_INTER_COUNTER_RST : R/W; bitpos: [3]; default: 0;
+ *  Write 1 then write 0 to this bit to reset rx ch5 counter.
+ */
+#define H264_DMA_RX_CH5_INTER_COUNTER_RST    (BIT(3))
+#define H264_DMA_RX_CH5_INTER_COUNTER_RST_M  (H264_DMA_RX_CH5_INTER_COUNTER_RST_V << H264_DMA_RX_CH5_INTER_COUNTER_RST_S)
+#define H264_DMA_RX_CH5_INTER_COUNTER_RST_V  0x00000001U
+#define H264_DMA_RX_CH5_INTER_COUNTER_RST_S  3
+
+/** H264_DMA_RX_CH0_COUNTER_REG register
+ *  rx ch0 counter register
+ */
+#define H264_DMA_RX_CH0_COUNTER_REG (DR_REG_H264_DMA_BASE + 0xb54)
+/** H264_DMA_RX_CH0_CNT : RO; bitpos: [22:0]; default: 0;
+ *  rx ch0 counter register
+ */
+#define H264_DMA_RX_CH0_CNT    0x007FFFFFU
+#define H264_DMA_RX_CH0_CNT_M  (H264_DMA_RX_CH0_CNT_V << H264_DMA_RX_CH0_CNT_S)
+#define H264_DMA_RX_CH0_CNT_V  0x007FFFFFU
+#define H264_DMA_RX_CH0_CNT_S  0
+
+/** H264_DMA_RX_CH1_COUNTER_REG register
+ *  rx ch1 counter register
+ */
+#define H264_DMA_RX_CH1_COUNTER_REG (DR_REG_H264_DMA_BASE + 0xb58)
+/** H264_DMA_RX_CH1_CNT : RO; bitpos: [20:0]; default: 0;
+ *  rx ch1 counter register
+ */
+#define H264_DMA_RX_CH1_CNT    0x001FFFFFU
+#define H264_DMA_RX_CH1_CNT_M  (H264_DMA_RX_CH1_CNT_V << H264_DMA_RX_CH1_CNT_S)
+#define H264_DMA_RX_CH1_CNT_V  0x001FFFFFU
+#define H264_DMA_RX_CH1_CNT_S  0
+
+/** H264_DMA_RX_CH2_COUNTER_REG register
+ *  rx ch2 counter register
+ */
+#define H264_DMA_RX_CH2_COUNTER_REG (DR_REG_H264_DMA_BASE + 0xb5c)
+/** H264_DMA_RX_CH2_CNT : RO; bitpos: [10:0]; default: 0;
+ *  rx ch2 counter register
+ */
+#define H264_DMA_RX_CH2_CNT    0x000007FFU
+#define H264_DMA_RX_CH2_CNT_M  (H264_DMA_RX_CH2_CNT_V << H264_DMA_RX_CH2_CNT_S)
+#define H264_DMA_RX_CH2_CNT_V  0x000007FFU
+#define H264_DMA_RX_CH2_CNT_S  0
+
+/** H264_DMA_RX_CH5_COUNTER_REG register
+ *  rx ch5 counter register
+ */
+#define H264_DMA_RX_CH5_COUNTER_REG (DR_REG_H264_DMA_BASE + 0xb60)
+/** H264_DMA_RX_CH5_CNT : RO; bitpos: [16:0]; default: 0;
+ *  rx ch5 counter register
+ */
+#define H264_DMA_RX_CH5_CNT    0x0001FFFFU
+#define H264_DMA_RX_CH5_CNT_M  (H264_DMA_RX_CH5_CNT_V << H264_DMA_RX_CH5_CNT_S)
+#define H264_DMA_RX_CH5_CNT_V  0x0001FFFFU
+#define H264_DMA_RX_CH5_CNT_S  0
+
+/** H264_DMA_PBYTE_REG register
+ *  image pbyte register
+ */
+#define H264_DMA_PBYTE_REG (DR_REG_H264_DMA_BASE + 0xb64)
+/** H264_DMA_ORI_PBYTE : R/W; bitpos: [3:0]; default: 2;
+ *  configures bytes per pixel for ori img. 0: 0.5byte/pix, 1: 1byte/pix, 2:
+ *  1.5byte/pix, 3: 2byte/pix, 4: 3byte/pix
+ */
+#define H264_DMA_ORI_PBYTE    0x0000000FU
+#define H264_DMA_ORI_PBYTE_M  (H264_DMA_ORI_PBYTE_V << H264_DMA_ORI_PBYTE_S)
+#define H264_DMA_ORI_PBYTE_V  0x0000000FU
+#define H264_DMA_ORI_PBYTE_S  0
+
+/** H264_DMA_CH_DBG_EN_REG register
+ *  channel debug enable register
+ */
+#define H264_DMA_CH_DBG_EN_REG (DR_REG_H264_DMA_BASE + 0xb68)
+/** H264_DMA_OUT_CH0_DBG_EN : R/W; bitpos: [0]; default: 0;
+ *  configures whether to enable out channel 0 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_OUT_CH0_DBG_EN    (BIT(0))
+#define H264_DMA_OUT_CH0_DBG_EN_M  (H264_DMA_OUT_CH0_DBG_EN_V << H264_DMA_OUT_CH0_DBG_EN_S)
+#define H264_DMA_OUT_CH0_DBG_EN_V  0x00000001U
+#define H264_DMA_OUT_CH0_DBG_EN_S  0
+/** H264_DMA_OUT_CH1_DBG_EN : R/W; bitpos: [1]; default: 0;
+ *  configures whether to enable out channel 1 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_OUT_CH1_DBG_EN    (BIT(1))
+#define H264_DMA_OUT_CH1_DBG_EN_M  (H264_DMA_OUT_CH1_DBG_EN_V << H264_DMA_OUT_CH1_DBG_EN_S)
+#define H264_DMA_OUT_CH1_DBG_EN_V  0x00000001U
+#define H264_DMA_OUT_CH1_DBG_EN_S  1
+/** H264_DMA_OUT_CH2_DBG_EN : R/W; bitpos: [2]; default: 0;
+ *  configures whether to enable out channel 2 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_OUT_CH2_DBG_EN    (BIT(2))
+#define H264_DMA_OUT_CH2_DBG_EN_M  (H264_DMA_OUT_CH2_DBG_EN_V << H264_DMA_OUT_CH2_DBG_EN_S)
+#define H264_DMA_OUT_CH2_DBG_EN_V  0x00000001U
+#define H264_DMA_OUT_CH2_DBG_EN_S  2
+/** H264_DMA_OUT_CH3_DBG_EN : R/W; bitpos: [3]; default: 0;
+ *  configures whether to enable out channel 3 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_OUT_CH3_DBG_EN    (BIT(3))
+#define H264_DMA_OUT_CH3_DBG_EN_M  (H264_DMA_OUT_CH3_DBG_EN_V << H264_DMA_OUT_CH3_DBG_EN_S)
+#define H264_DMA_OUT_CH3_DBG_EN_V  0x00000001U
+#define H264_DMA_OUT_CH3_DBG_EN_S  3
+/** H264_DMA_OUT_CH4_DBG_EN : R/W; bitpos: [4]; default: 0;
+ *  configures whether to enable out channel 4 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_OUT_CH4_DBG_EN    (BIT(4))
+#define H264_DMA_OUT_CH4_DBG_EN_M  (H264_DMA_OUT_CH4_DBG_EN_V << H264_DMA_OUT_CH4_DBG_EN_S)
+#define H264_DMA_OUT_CH4_DBG_EN_V  0x00000001U
+#define H264_DMA_OUT_CH4_DBG_EN_S  4
+/** H264_DMA_IN_CH0_DBG_EN : R/W; bitpos: [16]; default: 0;
+ *  configures whether to enable in channel 0 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH0_DBG_EN    (BIT(16))
+#define H264_DMA_IN_CH0_DBG_EN_M  (H264_DMA_IN_CH0_DBG_EN_V << H264_DMA_IN_CH0_DBG_EN_S)
+#define H264_DMA_IN_CH0_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH0_DBG_EN_S  16
+/** H264_DMA_IN_CH1_DBG_EN : R/W; bitpos: [17]; default: 0;
+ *  configures whether to enable in channel 1 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH1_DBG_EN    (BIT(17))
+#define H264_DMA_IN_CH1_DBG_EN_M  (H264_DMA_IN_CH1_DBG_EN_V << H264_DMA_IN_CH1_DBG_EN_S)
+#define H264_DMA_IN_CH1_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH1_DBG_EN_S  17
+/** H264_DMA_IN_CH2_DBG_EN : R/W; bitpos: [18]; default: 0;
+ *  configures whether to enable in channel 2 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH2_DBG_EN    (BIT(18))
+#define H264_DMA_IN_CH2_DBG_EN_M  (H264_DMA_IN_CH2_DBG_EN_V << H264_DMA_IN_CH2_DBG_EN_S)
+#define H264_DMA_IN_CH2_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH2_DBG_EN_S  18
+/** H264_DMA_IN_CH3_DBG_EN : R/W; bitpos: [19]; default: 0;
+ *  configures whether to enable in channel 3 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH3_DBG_EN    (BIT(19))
+#define H264_DMA_IN_CH3_DBG_EN_M  (H264_DMA_IN_CH3_DBG_EN_V << H264_DMA_IN_CH3_DBG_EN_S)
+#define H264_DMA_IN_CH3_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH3_DBG_EN_S  19
+/** H264_DMA_IN_CH4_DBG_EN : R/W; bitpos: [20]; default: 0;
+ *  configures whether to enable in channel 4 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH4_DBG_EN    (BIT(20))
+#define H264_DMA_IN_CH4_DBG_EN_M  (H264_DMA_IN_CH4_DBG_EN_V << H264_DMA_IN_CH4_DBG_EN_S)
+#define H264_DMA_IN_CH4_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH4_DBG_EN_S  20
+/** H264_DMA_IN_CH5_DBG_EN : R/W; bitpos: [21]; default: 0;
+ *  configures whether to enable in channel 5 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH5_DBG_EN    (BIT(21))
+#define H264_DMA_IN_CH5_DBG_EN_M  (H264_DMA_IN_CH5_DBG_EN_V << H264_DMA_IN_CH5_DBG_EN_S)
+#define H264_DMA_IN_CH5_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH5_DBG_EN_S  21
+
+/** H264_DMA_OUT_CH0_DBG_DATA_L_REG register
+ *  out channel 0 debug data register
+ */
+#define H264_DMA_OUT_CH0_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb6c)
+/** H264_DMA_OUT_CH0_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 0 debug data bit 31-0
+ */
+#define H264_DMA_OUT_CH0_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_OUT_CH0_DBG_DATA_L_M  (H264_DMA_OUT_CH0_DBG_DATA_L_V << H264_DMA_OUT_CH0_DBG_DATA_L_S)
+#define H264_DMA_OUT_CH0_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH0_DBG_DATA_L_S  0
+
+/** H264_DMA_OUT_CH0_DBG_DATA_H_REG register
+ *  out channel 0 debug data register
+ */
+#define H264_DMA_OUT_CH0_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb70)
+/** H264_DMA_OUT_CH0_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 0 debug data bit 63-32
+ */
+#define H264_DMA_OUT_CH0_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_OUT_CH0_DBG_DATA_H_M  (H264_DMA_OUT_CH0_DBG_DATA_H_V << H264_DMA_OUT_CH0_DBG_DATA_H_S)
+#define H264_DMA_OUT_CH0_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH0_DBG_DATA_H_S  0
+
+/** H264_DMA_OUT_CH1_DBG_DATA_L_REG register
+ *  out channel 1 debug data register
+ */
+#define H264_DMA_OUT_CH1_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb74)
+/** H264_DMA_OUT_CH1_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 1 debug data bit 31-0
+ */
+#define H264_DMA_OUT_CH1_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_OUT_CH1_DBG_DATA_L_M  (H264_DMA_OUT_CH1_DBG_DATA_L_V << H264_DMA_OUT_CH1_DBG_DATA_L_S)
+#define H264_DMA_OUT_CH1_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH1_DBG_DATA_L_S  0
+
+/** H264_DMA_OUT_CH1_DBG_DATA_H_REG register
+ *  out channel 1 debug data register
+ */
+#define H264_DMA_OUT_CH1_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb78)
+/** H264_DMA_OUT_CH1_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 1 debug data bit 63-32
+ */
+#define H264_DMA_OUT_CH1_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_OUT_CH1_DBG_DATA_H_M  (H264_DMA_OUT_CH1_DBG_DATA_H_V << H264_DMA_OUT_CH1_DBG_DATA_H_S)
+#define H264_DMA_OUT_CH1_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH1_DBG_DATA_H_S  0
+
+/** H264_DMA_OUT_CH2_DBG_DATA_L_REG register
+ *  out channel 2 debug data register
+ */
+#define H264_DMA_OUT_CH2_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb7c)
+/** H264_DMA_OUT_CH2_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 2 debug data bit 31-0
+ */
+#define H264_DMA_OUT_CH2_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_OUT_CH2_DBG_DATA_L_M  (H264_DMA_OUT_CH2_DBG_DATA_L_V << H264_DMA_OUT_CH2_DBG_DATA_L_S)
+#define H264_DMA_OUT_CH2_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH2_DBG_DATA_L_S  0
+
+/** H264_DMA_OUT_CH2_DBG_DATA_H_REG register
+ *  out channel 2 debug data register
+ */
+#define H264_DMA_OUT_CH2_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb80)
+/** H264_DMA_OUT_CH2_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 2 debug data bit 63-32
+ */
+#define H264_DMA_OUT_CH2_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_OUT_CH2_DBG_DATA_H_M  (H264_DMA_OUT_CH2_DBG_DATA_H_V << H264_DMA_OUT_CH2_DBG_DATA_H_S)
+#define H264_DMA_OUT_CH2_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH2_DBG_DATA_H_S  0
+
+/** H264_DMA_OUT_CH3_DBG_DATA_L_REG register
+ *  out channel 3 debug data register
+ */
+#define H264_DMA_OUT_CH3_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb84)
+/** H264_DMA_OUT_CH3_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 3 debug data bit 31-0
+ */
+#define H264_DMA_OUT_CH3_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_OUT_CH3_DBG_DATA_L_M  (H264_DMA_OUT_CH3_DBG_DATA_L_V << H264_DMA_OUT_CH3_DBG_DATA_L_S)
+#define H264_DMA_OUT_CH3_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH3_DBG_DATA_L_S  0
+
+/** H264_DMA_OUT_CH3_DBG_DATA_H_REG register
+ *  out channel 3 debug data register
+ */
+#define H264_DMA_OUT_CH3_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb88)
+/** H264_DMA_OUT_CH3_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 3 debug data bit 63-32
+ */
+#define H264_DMA_OUT_CH3_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_OUT_CH3_DBG_DATA_H_M  (H264_DMA_OUT_CH3_DBG_DATA_H_V << H264_DMA_OUT_CH3_DBG_DATA_H_S)
+#define H264_DMA_OUT_CH3_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH3_DBG_DATA_H_S  0
+
+/** H264_DMA_OUT_CH4_DBG_DATA_L_REG register
+ *  out channel 4 debug data register
+ */
+#define H264_DMA_OUT_CH4_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb8c)
+/** H264_DMA_OUT_CH4_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 4 debug data bit 31-0
+ */
+#define H264_DMA_OUT_CH4_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_OUT_CH4_DBG_DATA_L_M  (H264_DMA_OUT_CH4_DBG_DATA_L_V << H264_DMA_OUT_CH4_DBG_DATA_L_S)
+#define H264_DMA_OUT_CH4_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH4_DBG_DATA_L_S  0
+
+/** H264_DMA_OUT_CH4_DBG_DATA_H_REG register
+ *  out channel 4 debug data register
+ */
+#define H264_DMA_OUT_CH4_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb90)
+/** H264_DMA_OUT_CH4_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 4 debug data bit 63-32
+ */
+#define H264_DMA_OUT_CH4_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_OUT_CH4_DBG_DATA_H_M  (H264_DMA_OUT_CH4_DBG_DATA_H_V << H264_DMA_OUT_CH4_DBG_DATA_H_S)
+#define H264_DMA_OUT_CH4_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH4_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH0_DBG_DATA_L_REG register
+ *  in channel 0 debug data register
+ */
+#define H264_DMA_IN_CH0_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb94)
+/** H264_DMA_IN_CH0_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 0 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH0_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH0_DBG_DATA_L_M  (H264_DMA_IN_CH0_DBG_DATA_L_V << H264_DMA_IN_CH0_DBG_DATA_L_S)
+#define H264_DMA_IN_CH0_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH0_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH0_DBG_DATA_H_REG register
+ *  in channel 0 debug data register
+ */
+#define H264_DMA_IN_CH0_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb98)
+/** H264_DMA_IN_CH0_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 0 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH0_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH0_DBG_DATA_H_M  (H264_DMA_IN_CH0_DBG_DATA_H_V << H264_DMA_IN_CH0_DBG_DATA_H_S)
+#define H264_DMA_IN_CH0_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH0_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH1_DBG_DATA_L_REG register
+ *  in channel 1 debug data register
+ */
+#define H264_DMA_IN_CH1_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb9c)
+/** H264_DMA_IN_CH1_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 1 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH1_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH1_DBG_DATA_L_M  (H264_DMA_IN_CH1_DBG_DATA_L_V << H264_DMA_IN_CH1_DBG_DATA_L_S)
+#define H264_DMA_IN_CH1_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH1_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH1_DBG_DATA_H_REG register
+ *  in channel 1 debug data register
+ */
+#define H264_DMA_IN_CH1_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xba0)
+/** H264_DMA_IN_CH1_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 1 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH1_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH1_DBG_DATA_H_M  (H264_DMA_IN_CH1_DBG_DATA_H_V << H264_DMA_IN_CH1_DBG_DATA_H_S)
+#define H264_DMA_IN_CH1_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH1_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH2_DBG_DATA_L_REG register
+ *  in channel 2 debug data register
+ */
+#define H264_DMA_IN_CH2_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xba4)
+/** H264_DMA_IN_CH2_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 2 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH2_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH2_DBG_DATA_L_M  (H264_DMA_IN_CH2_DBG_DATA_L_V << H264_DMA_IN_CH2_DBG_DATA_L_S)
+#define H264_DMA_IN_CH2_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH2_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH2_DBG_DATA_H_REG register
+ *  in channel 2 debug data register
+ */
+#define H264_DMA_IN_CH2_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xba8)
+/** H264_DMA_IN_CH2_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 2 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH2_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH2_DBG_DATA_H_M  (H264_DMA_IN_CH2_DBG_DATA_H_V << H264_DMA_IN_CH2_DBG_DATA_H_S)
+#define H264_DMA_IN_CH2_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH2_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH3_DBG_DATA_L_REG register
+ *  in channel 3 debug data register
+ */
+#define H264_DMA_IN_CH3_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xbac)
+/** H264_DMA_IN_CH3_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 3 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH3_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH3_DBG_DATA_L_M  (H264_DMA_IN_CH3_DBG_DATA_L_V << H264_DMA_IN_CH3_DBG_DATA_L_S)
+#define H264_DMA_IN_CH3_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH3_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH3_DBG_DATA_H_REG register
+ *  in channel 3 debug data register
+ */
+#define H264_DMA_IN_CH3_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xbb0)
+/** H264_DMA_IN_CH3_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 3 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH3_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH3_DBG_DATA_H_M  (H264_DMA_IN_CH3_DBG_DATA_H_V << H264_DMA_IN_CH3_DBG_DATA_H_S)
+#define H264_DMA_IN_CH3_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH3_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH4_DBG_DATA_L_REG register
+ *  in channel 4 debug data register
+ */
+#define H264_DMA_IN_CH4_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xbb4)
+/** H264_DMA_IN_CH4_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 4 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH4_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH4_DBG_DATA_L_M  (H264_DMA_IN_CH4_DBG_DATA_L_V << H264_DMA_IN_CH4_DBG_DATA_L_S)
+#define H264_DMA_IN_CH4_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH4_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH4_DBG_DATA_H_REG register
+ *  in channel 4 debug data register
+ */
+#define H264_DMA_IN_CH4_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xbb8)
+/** H264_DMA_IN_CH4_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 4 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH4_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH4_DBG_DATA_H_M  (H264_DMA_IN_CH4_DBG_DATA_H_V << H264_DMA_IN_CH4_DBG_DATA_H_S)
+#define H264_DMA_IN_CH4_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH4_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH5_DBG_DATA_L_REG register
+ *  in channel 5 debug data register
+ */
+#define H264_DMA_IN_CH5_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xbbc)
+/** H264_DMA_IN_CH5_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 5 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH5_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH5_DBG_DATA_L_M  (H264_DMA_IN_CH5_DBG_DATA_L_V << H264_DMA_IN_CH5_DBG_DATA_L_S)
+#define H264_DMA_IN_CH5_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH5_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH5_DBG_DATA_H_REG register
+ *  in channel 5 debug data register
+ */
+#define H264_DMA_IN_CH5_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xbc0)
+/** H264_DMA_IN_CH5_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 5 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH5_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH5_DBG_DATA_H_M  (H264_DMA_IN_CH5_DBG_DATA_H_V << H264_DMA_IN_CH5_DBG_DATA_H_S)
+#define H264_DMA_IN_CH5_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH5_DBG_DATA_H_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/h264_dma_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/h264_dma_struct.h
new file mode 100644
index 0000000000..66197170e9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/h264_dma_struct.h
@@ -0,0 +1,7076 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of out_conf0_ch0 register
+ *  TX CH0 config0 register
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_ch0:1;
+        /** out_eof_mode_ch0 : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_ch0:1;
+        /** outdscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch0:1;
+        /** out_ecc_aes_en_ch0 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_ch0:1;
+        /** out_check_owner_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_ch0:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length_ch0 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_ch0:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en_ch0 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_ch0:1;
+        uint32_t reserved_13:3;
+        /** out_reorder_en_ch0 : R/W; bitpos: [16]; default: 0;
+         *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t out_reorder_en_ch0:1;
+        uint32_t reserved_17:7;
+        /** out_rst_ch0 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_ch0:1;
+        /** out_cmd_disable_ch0 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_ch0:1;
+        /** out_arb_weight_opt_dis_ch0 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_ch0:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_out_conf0_ch0_reg_t;
+
+/** Type of out_push_ch0 register
+ *  TX CH0 outfifo push register
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch0 : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_ch0:10;
+        /** outfifo_push_ch0 : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_ch0:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_out_push_ch0_reg_t;
+
+/** Type of out_link_conf_ch0 register
+ *  TX CH0 out_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_ch0 : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_ch0:1;
+        /** outlink_start_ch0 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_ch0:1;
+        /** outlink_restart_ch0 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_ch0:1;
+        /** outlink_park_ch0 : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_ch0:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_link_conf_ch0_reg_t;
+
+/** Type of out_ro_pd_conf_ch0 register
+ *  TX CH0 reorder power config register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** out_ro_ram_force_pd_ch0 : R/W; bitpos: [4]; default: 0;
+         *  dma reorder ram power down
+         */
+        uint32_t out_ro_ram_force_pd_ch0:1;
+        /** out_ro_ram_force_pu_ch0 : R/W; bitpos: [5]; default: 1;
+         *  dma reorder ram power up
+         */
+        uint32_t out_ro_ram_force_pu_ch0:1;
+        /** out_ro_ram_clk_fo_ch0 : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t out_ro_ram_clk_fo_ch0:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_dma_out_ro_pd_conf_ch0_reg_t;
+
+/** Type of out_push_ch1 register
+ *  TX CH1 outfifo push register
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch1 : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_ch1:10;
+        /** outfifo_push_ch1 : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_ch1:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_out_push_ch1_reg_t;
+
+/** Type of out_link_conf_ch1 register
+ *  TX CH1 out_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_ch1 : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_ch1:1;
+        /** outlink_start_ch1 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_ch1:1;
+        /** outlink_restart_ch1 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_ch1:1;
+        /** outlink_park_ch1 : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_ch1:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_link_conf_ch1_reg_t;
+
+/** Type of out_push_ch2 register
+ *  TX CH2 outfifo push register
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch2 : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_ch2:10;
+        /** outfifo_push_ch2 : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_ch2:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_out_push_ch2_reg_t;
+
+/** Type of out_link_conf_ch2 register
+ *  TX CH2 out_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_ch2 : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_ch2:1;
+        /** outlink_start_ch2 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_ch2:1;
+        /** outlink_restart_ch2 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_ch2:1;
+        /** outlink_park_ch2 : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_ch2:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_link_conf_ch2_reg_t;
+
+/** Type of out_push_ch3 register
+ *  TX CH3 outfifo push register
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch3 : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_ch3:10;
+        /** outfifo_push_ch3 : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_ch3:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_out_push_ch3_reg_t;
+
+/** Type of out_link_conf_ch3 register
+ *  TX CH3 out_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_ch3 : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_ch3:1;
+        /** outlink_start_ch3 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_ch3:1;
+        /** outlink_restart_ch3 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_ch3:1;
+        /** outlink_park_ch3 : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_ch3:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_link_conf_ch3_reg_t;
+
+/** Type of out_push_ch4 register
+ *  TX CH4 outfifo push register
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch4 : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_ch4:10;
+        /** outfifo_push_ch4 : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_ch4:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_out_push_ch4_reg_t;
+
+/** Type of out_link_conf_ch4 register
+ *  TX CH4 out_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_ch4 : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_ch4:1;
+        /** outlink_start_ch4 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_ch4:1;
+        /** outlink_restart_ch4 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_ch4:1;
+        /** outlink_park_ch4 : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_ch4:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_link_conf_ch4_reg_t;
+
+/** Type of in_conf0_ch0 register
+ *  RX CH0 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** indscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_ch0:1;
+        /** in_ecc_aes_en_ch0 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch0:1;
+        /** in_check_owner_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_ch0:1;
+        uint32_t reserved_5:1;
+        /** in_mem_burst_length_ch0 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch0:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch0 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch0:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch0 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch0:1;
+        /** in_cmd_disable_ch0 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch0:1;
+        /** in_arb_weight_opt_dis_ch0 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_ch0:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch0_reg_t;
+
+/** Type of in_pop_ch0 register
+ *  RX CH0 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch0 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch0:11;
+        /** infifo_pop_ch0 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch0:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch0_reg_t;
+
+/** Type of in_link_conf_ch0 register
+ *  RX CH0 in_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_ch0 : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_ch0:1;
+        /** inlink_stop_ch0 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_ch0:1;
+        /** inlink_start_ch0 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_ch0:1;
+        /** inlink_restart_ch0 : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_ch0:1;
+        /** inlink_park_ch0 : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_ch0:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_in_link_conf_ch0_reg_t;
+
+/** Type of in_ro_pd_conf_ch0 register
+ *  RX CH0 reorder power config register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** in_ro_ram_clk_fo_ch0 : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t in_ro_ram_clk_fo_ch0:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_dma_in_ro_pd_conf_ch0_reg_t;
+
+/** Type of in_conf0_ch1 register
+ *  RX CH1 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** indscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_ch1:1;
+        /** in_ecc_aes_en_ch1 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch1:1;
+        /** in_check_owner_ch1 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_ch1:1;
+        uint32_t reserved_5:1;
+        /** in_mem_burst_length_ch1 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch1:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch1 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch1:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch1 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch1:1;
+        /** in_cmd_disable_ch1 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch1:1;
+        /** in_arb_weight_opt_dis_ch1 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_ch1:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch1_reg_t;
+
+/** Type of in_pop_ch1 register
+ *  RX CH1 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch1 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch1:11;
+        /** infifo_pop_ch1 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch1:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch1_reg_t;
+
+/** Type of in_link_conf_ch1 register
+ *  RX CH1 in_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_ch1 : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_ch1:1;
+        /** inlink_stop_ch1 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_ch1:1;
+        /** inlink_start_ch1 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_ch1:1;
+        /** inlink_restart_ch1 : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_ch1:1;
+        /** inlink_park_ch1 : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_ch1:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_in_link_conf_ch1_reg_t;
+
+/** Type of in_conf0_ch2 register
+ *  RX CH2 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** indscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_ch2:1;
+        /** in_ecc_aes_en_ch2 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch2:1;
+        /** in_check_owner_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_ch2:1;
+        uint32_t reserved_5:1;
+        /** in_mem_burst_length_ch2 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 2. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch2:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch2 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch2:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch2 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch2:1;
+        /** in_cmd_disable_ch2 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch2:1;
+        /** in_arb_weight_opt_dis_ch2 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_ch2:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch2_reg_t;
+
+/** Type of in_pop_ch2 register
+ *  RX CH2 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch2 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch2:11;
+        /** infifo_pop_ch2 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch2:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch2_reg_t;
+
+/** Type of in_link_conf_ch2 register
+ *  RX CH2 in_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_ch2 : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_ch2:1;
+        /** inlink_stop_ch2 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_ch2:1;
+        /** inlink_start_ch2 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_ch2:1;
+        /** inlink_restart_ch2 : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_ch2:1;
+        /** inlink_park_ch2 : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_ch2:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_in_link_conf_ch2_reg_t;
+
+/** Type of in_conf0_ch3 register
+ *  RX CH3 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** indscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_ch3:1;
+        /** in_ecc_aes_en_ch3 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch3:1;
+        /** in_check_owner_ch3 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_ch3:1;
+        uint32_t reserved_5:1;
+        /** in_mem_burst_length_ch3 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch3:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch3 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch3:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch3 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch3:1;
+        /** in_cmd_disable_ch3 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch3:1;
+        /** in_arb_weight_opt_dis_ch3 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_ch3:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch3_reg_t;
+
+/** Type of in_pop_ch3 register
+ *  RX CH3 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch3 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch3:11;
+        /** infifo_pop_ch3 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch3:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch3_reg_t;
+
+/** Type of in_link_conf_ch3 register
+ *  RX CH3 in_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_ch3 : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_ch3:1;
+        /** inlink_stop_ch3 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_ch3:1;
+        /** inlink_start_ch3 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_ch3:1;
+        /** inlink_restart_ch3 : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_ch3:1;
+        /** inlink_park_ch3 : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_ch3:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_in_link_conf_ch3_reg_t;
+
+/** Type of in_conf0_ch4 register
+ *  RX CH4 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** indscr_burst_en_ch4 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_ch4:1;
+        /** in_ecc_aes_en_ch4 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch4:1;
+        /** in_check_owner_ch4 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_ch4:1;
+        uint32_t reserved_5:1;
+        /** in_mem_burst_length_ch4 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch4:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch4 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch4:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch4 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch4:1;
+        /** in_cmd_disable_ch4 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch4:1;
+        /** in_arb_weight_opt_dis_ch4 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_ch4:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch4_reg_t;
+
+/** Type of in_pop_ch4 register
+ *  RX CH4 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch4 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch4:11;
+        /** infifo_pop_ch4 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch4:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch4_reg_t;
+
+/** Type of in_link_conf_ch4 register
+ *  RX CH4 in_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_ch4 : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_ch4:1;
+        /** inlink_stop_ch4 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_ch4:1;
+        /** inlink_start_ch4 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_ch4:1;
+        /** inlink_restart_ch4 : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_ch4:1;
+        /** inlink_park_ch4 : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_ch4:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_in_link_conf_ch4_reg_t;
+
+/** Type of in_conf0_ch5 register
+ *  RX CH5 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** in_ecc_aes_en_ch5 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch5:1;
+        uint32_t reserved_4:2;
+        /** in_mem_burst_length_ch5 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch5:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch5 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch5:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch5 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch5:1;
+        /** in_cmd_disable_ch5 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch5:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch5_reg_t;
+
+/** Type of in_pop_ch5 register
+ *  RX CH5 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch5 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch5:11;
+        /** infifo_pop_ch5 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch5:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch5_reg_t;
+
+/** Type of rst_conf register
+ *  axi reset config register
+ */
+typedef union {
+    struct {
+        /** inter_axim_rd_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+         */
+        uint32_t inter_axim_rd_rst:1;
+        /** inter_axim_wr_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+         */
+        uint32_t inter_axim_wr_rst:1;
+        /** exter_axim_rd_rst : R/W; bitpos: [2]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+         */
+        uint32_t exter_axim_rd_rst:1;
+        /** exter_axim_wr_rst : R/W; bitpos: [3]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+         */
+        uint32_t exter_axim_wr_rst:1;
+        /** clk_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_dma_rst_conf_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of out_int_raw_ch0 register
+ *  TX CH0  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_ch0_int_raw:1;
+        /** out_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_ch0_int_raw:1;
+        /** out_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_ch0_int_raw:1;
+        /** out_total_eof_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_ch0_int_raw:1;
+        /** outfifo_ovf_l1_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_ch0_int_raw:1;
+        /** outfifo_udf_l1_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_ch0_int_raw:1;
+        /** outfifo_ovf_l2_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_ch0_int_raw:1;
+        /** outfifo_udf_l2_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_ch0_int_raw:1;
+        /** out_dscr_task_ovf_ch0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_ch0_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_raw_ch0_reg_t;
+
+/** Type of out_int_ena_ch0 register
+ *  TX CH0  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch0_int_ena:1;
+        /** out_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch0_int_ena:1;
+        /** out_dscr_err_ch0_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch0_int_ena:1;
+        /** out_total_eof_ch0_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch0_int_ena:1;
+        /** outfifo_ovf_l1_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch0_int_ena:1;
+        /** outfifo_udf_l1_ch0_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch0_int_ena:1;
+        /** outfifo_ovf_l2_ch0_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch0_int_ena:1;
+        /** outfifo_udf_l2_ch0_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch0_int_ena:1;
+        /** out_dscr_task_ovf_ch0_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch0_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_ena_ch0_reg_t;
+
+/** Type of out_int_st_ch0 register
+ *  TX CH0  interrupt st register
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch0_int_st:1;
+        /** out_eof_ch0_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch0_int_st:1;
+        /** out_dscr_err_ch0_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch0_int_st:1;
+        /** out_total_eof_ch0_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch0_int_st:1;
+        /** outfifo_ovf_l1_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch0_int_st:1;
+        /** outfifo_udf_l1_ch0_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch0_int_st:1;
+        /** outfifo_ovf_l2_ch0_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch0_int_st:1;
+        /** outfifo_udf_l2_ch0_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch0_int_st:1;
+        /** out_dscr_task_ovf_ch0_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch0_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_st_ch0_reg_t;
+
+/** Type of out_int_clr_ch0 register
+ *  TX CH0  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch0_int_clr:1;
+        /** out_eof_ch0_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch0_int_clr:1;
+        /** out_dscr_err_ch0_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch0_int_clr:1;
+        /** out_total_eof_ch0_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch0_int_clr:1;
+        /** outfifo_ovf_l1_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch0_int_clr:1;
+        /** outfifo_udf_l1_ch0_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch0_int_clr:1;
+        /** outfifo_ovf_l2_ch0_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch0_int_clr:1;
+        /** outfifo_udf_l2_ch0_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch0_int_clr:1;
+        /** out_dscr_task_ovf_ch0_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch0_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_clr_ch0_reg_t;
+
+/** Type of out_int_raw_ch1 register
+ *  TX CH1  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_ch1_int_raw:1;
+        /** out_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_ch1_int_raw:1;
+        /** out_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_ch1_int_raw:1;
+        /** out_total_eof_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_ch1_int_raw:1;
+        /** outfifo_ovf_l1_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_ch1_int_raw:1;
+        /** outfifo_udf_l1_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_ch1_int_raw:1;
+        /** outfifo_ovf_l2_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_ch1_int_raw:1;
+        /** outfifo_udf_l2_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_ch1_int_raw:1;
+        /** out_dscr_task_ovf_ch1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_ch1_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_raw_ch1_reg_t;
+
+/** Type of out_int_ena_ch1 register
+ *  TX CH1  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch1_int_ena:1;
+        /** out_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch1_int_ena:1;
+        /** out_dscr_err_ch1_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch1_int_ena:1;
+        /** out_total_eof_ch1_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch1_int_ena:1;
+        /** outfifo_ovf_l1_ch1_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch1_int_ena:1;
+        /** outfifo_udf_l1_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch1_int_ena:1;
+        /** outfifo_ovf_l2_ch1_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch1_int_ena:1;
+        /** outfifo_udf_l2_ch1_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch1_int_ena:1;
+        /** out_dscr_task_ovf_ch1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch1_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_ena_ch1_reg_t;
+
+/** Type of out_int_st_ch1 register
+ *  TX CH1  interrupt st register
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch1_int_st:1;
+        /** out_eof_ch1_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch1_int_st:1;
+        /** out_dscr_err_ch1_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch1_int_st:1;
+        /** out_total_eof_ch1_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch1_int_st:1;
+        /** outfifo_ovf_l1_ch1_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch1_int_st:1;
+        /** outfifo_udf_l1_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch1_int_st:1;
+        /** outfifo_ovf_l2_ch1_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch1_int_st:1;
+        /** outfifo_udf_l2_ch1_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch1_int_st:1;
+        /** out_dscr_task_ovf_ch1_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch1_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_st_ch1_reg_t;
+
+/** Type of out_int_clr_ch1 register
+ *  TX CH1  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch1_int_clr:1;
+        /** out_eof_ch1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch1_int_clr:1;
+        /** out_dscr_err_ch1_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch1_int_clr:1;
+        /** out_total_eof_ch1_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch1_int_clr:1;
+        /** outfifo_ovf_l1_ch1_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch1_int_clr:1;
+        /** outfifo_udf_l1_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch1_int_clr:1;
+        /** outfifo_ovf_l2_ch1_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch1_int_clr:1;
+        /** outfifo_udf_l2_ch1_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch1_int_clr:1;
+        /** out_dscr_task_ovf_ch1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch1_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_clr_ch1_reg_t;
+
+/** Type of out_int_raw_ch2 register
+ *  TX CH2  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_ch2_int_raw:1;
+        /** out_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_ch2_int_raw:1;
+        /** out_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_ch2_int_raw:1;
+        /** out_total_eof_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_ch2_int_raw:1;
+        /** outfifo_ovf_l1_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_ch2_int_raw:1;
+        /** outfifo_udf_l1_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_ch2_int_raw:1;
+        /** outfifo_ovf_l2_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_ch2_int_raw:1;
+        /** outfifo_udf_l2_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_ch2_int_raw:1;
+        /** out_dscr_task_ovf_ch2_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_ch2_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_raw_ch2_reg_t;
+
+/** Type of out_int_ena_ch2 register
+ *  TX CH2  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch2_int_ena:1;
+        /** out_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch2_int_ena:1;
+        /** out_dscr_err_ch2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch2_int_ena:1;
+        /** out_total_eof_ch2_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch2_int_ena:1;
+        /** outfifo_ovf_l1_ch2_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch2_int_ena:1;
+        /** outfifo_udf_l1_ch2_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch2_int_ena:1;
+        /** outfifo_ovf_l2_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch2_int_ena:1;
+        /** outfifo_udf_l2_ch2_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch2_int_ena:1;
+        /** out_dscr_task_ovf_ch2_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch2_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_ena_ch2_reg_t;
+
+/** Type of out_int_st_ch2 register
+ *  TX CH2  interrupt st register
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch2_int_st:1;
+        /** out_eof_ch2_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch2_int_st:1;
+        /** out_dscr_err_ch2_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch2_int_st:1;
+        /** out_total_eof_ch2_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch2_int_st:1;
+        /** outfifo_ovf_l1_ch2_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch2_int_st:1;
+        /** outfifo_udf_l1_ch2_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch2_int_st:1;
+        /** outfifo_ovf_l2_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch2_int_st:1;
+        /** outfifo_udf_l2_ch2_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch2_int_st:1;
+        /** out_dscr_task_ovf_ch2_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch2_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_st_ch2_reg_t;
+
+/** Type of out_int_clr_ch2 register
+ *  TX CH2  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch2_int_clr:1;
+        /** out_eof_ch2_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch2_int_clr:1;
+        /** out_dscr_err_ch2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch2_int_clr:1;
+        /** out_total_eof_ch2_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch2_int_clr:1;
+        /** outfifo_ovf_l1_ch2_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch2_int_clr:1;
+        /** outfifo_udf_l1_ch2_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch2_int_clr:1;
+        /** outfifo_ovf_l2_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch2_int_clr:1;
+        /** outfifo_udf_l2_ch2_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch2_int_clr:1;
+        /** out_dscr_task_ovf_ch2_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch2_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_clr_ch2_reg_t;
+
+/** Type of out_int_raw_ch3 register
+ *  TX CH3  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** out_done_ch3_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_ch3_int_raw:1;
+        /** out_eof_ch3_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_ch3_int_raw:1;
+        /** out_dscr_err_ch3_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_ch3_int_raw:1;
+        /** out_total_eof_ch3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_ch3_int_raw:1;
+        /** outfifo_ovf_l1_ch3_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_ch3_int_raw:1;
+        /** outfifo_udf_l1_ch3_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_ch3_int_raw:1;
+        /** outfifo_ovf_l2_ch3_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_ch3_int_raw:1;
+        /** outfifo_udf_l2_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_ch3_int_raw:1;
+        /** out_dscr_task_ovf_ch3_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_ch3_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_raw_ch3_reg_t;
+
+/** Type of out_int_ena_ch3 register
+ *  TX CH3  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** out_done_ch3_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch3_int_ena:1;
+        /** out_eof_ch3_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch3_int_ena:1;
+        /** out_dscr_err_ch3_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch3_int_ena:1;
+        /** out_total_eof_ch3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch3_int_ena:1;
+        /** outfifo_ovf_l1_ch3_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch3_int_ena:1;
+        /** outfifo_udf_l1_ch3_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch3_int_ena:1;
+        /** outfifo_ovf_l2_ch3_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch3_int_ena:1;
+        /** outfifo_udf_l2_ch3_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch3_int_ena:1;
+        /** out_dscr_task_ovf_ch3_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch3_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_ena_ch3_reg_t;
+
+/** Type of out_int_st_ch3 register
+ *  TX CH3  interrupt st register
+ */
+typedef union {
+    struct {
+        /** out_done_ch3_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch3_int_st:1;
+        /** out_eof_ch3_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch3_int_st:1;
+        /** out_dscr_err_ch3_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch3_int_st:1;
+        /** out_total_eof_ch3_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch3_int_st:1;
+        /** outfifo_ovf_l1_ch3_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch3_int_st:1;
+        /** outfifo_udf_l1_ch3_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch3_int_st:1;
+        /** outfifo_ovf_l2_ch3_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch3_int_st:1;
+        /** outfifo_udf_l2_ch3_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch3_int_st:1;
+        /** out_dscr_task_ovf_ch3_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch3_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_st_ch3_reg_t;
+
+/** Type of out_int_clr_ch3 register
+ *  TX CH3  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** out_done_ch3_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch3_int_clr:1;
+        /** out_eof_ch3_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch3_int_clr:1;
+        /** out_dscr_err_ch3_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch3_int_clr:1;
+        /** out_total_eof_ch3_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch3_int_clr:1;
+        /** outfifo_ovf_l1_ch3_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch3_int_clr:1;
+        /** outfifo_udf_l1_ch3_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch3_int_clr:1;
+        /** outfifo_ovf_l2_ch3_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch3_int_clr:1;
+        /** outfifo_udf_l2_ch3_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch3_int_clr:1;
+        /** out_dscr_task_ovf_ch3_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch3_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_clr_ch3_reg_t;
+
+/** Type of out_int_raw_ch4 register
+ *  TX CH4  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** out_done_ch4_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_ch4_int_raw:1;
+        /** out_eof_ch4_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_ch4_int_raw:1;
+        /** out_dscr_err_ch4_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_ch4_int_raw:1;
+        /** out_total_eof_ch4_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_ch4_int_raw:1;
+        /** outfifo_ovf_l1_ch4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_ch4_int_raw:1;
+        /** outfifo_udf_l1_ch4_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_ch4_int_raw:1;
+        /** outfifo_ovf_l2_ch4_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_ch4_int_raw:1;
+        /** outfifo_udf_l2_ch4_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_ch4_int_raw:1;
+        /** out_dscr_task_ovf_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_ch4_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_raw_ch4_reg_t;
+
+/** Type of out_int_ena_ch4 register
+ *  TX CH4  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** out_done_ch4_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch4_int_ena:1;
+        /** out_eof_ch4_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch4_int_ena:1;
+        /** out_dscr_err_ch4_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch4_int_ena:1;
+        /** out_total_eof_ch4_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch4_int_ena:1;
+        /** outfifo_ovf_l1_ch4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch4_int_ena:1;
+        /** outfifo_udf_l1_ch4_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch4_int_ena:1;
+        /** outfifo_ovf_l2_ch4_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch4_int_ena:1;
+        /** outfifo_udf_l2_ch4_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch4_int_ena:1;
+        /** out_dscr_task_ovf_ch4_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch4_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_ena_ch4_reg_t;
+
+/** Type of out_int_st_ch4 register
+ *  TX CH4  interrupt st register
+ */
+typedef union {
+    struct {
+        /** out_done_ch4_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch4_int_st:1;
+        /** out_eof_ch4_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch4_int_st:1;
+        /** out_dscr_err_ch4_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch4_int_st:1;
+        /** out_total_eof_ch4_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch4_int_st:1;
+        /** outfifo_ovf_l1_ch4_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch4_int_st:1;
+        /** outfifo_udf_l1_ch4_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch4_int_st:1;
+        /** outfifo_ovf_l2_ch4_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch4_int_st:1;
+        /** outfifo_udf_l2_ch4_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch4_int_st:1;
+        /** out_dscr_task_ovf_ch4_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch4_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_st_ch4_reg_t;
+
+/** Type of out_int_clr_ch4 register
+ *  TX CH4  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** out_done_ch4_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch4_int_clr:1;
+        /** out_eof_ch4_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch4_int_clr:1;
+        /** out_dscr_err_ch4_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch4_int_clr:1;
+        /** out_total_eof_ch4_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch4_int_clr:1;
+        /** outfifo_ovf_l1_ch4_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch4_int_clr:1;
+        /** outfifo_udf_l1_ch4_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch4_int_clr:1;
+        /** outfifo_ovf_l2_ch4_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch4_int_clr:1;
+        /** outfifo_udf_l2_ch4_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch4_int_clr:1;
+        /** out_dscr_task_ovf_ch4_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch4_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_clr_ch4_reg_t;
+
+/** Type of in_int_raw_ch0 register
+ *  RX CH0  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 0.
+         */
+        uint32_t in_done_ch0_int_raw:1;
+        /** in_suc_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_ch0_int_raw:1;
+        /** in_err_eof_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_ch0_int_raw:1;
+        /** in_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 0.
+         */
+        uint32_t in_dscr_err_ch0_int_raw:1;
+        /** infifo_ovf_l1_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch0_int_raw:1;
+        /** infifo_udf_l1_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch0_int_raw:1;
+        /** infifo_ovf_l2_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_ch0_int_raw:1;
+        /** infifo_udf_l2_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_ch0_int_raw:1;
+        /** in_dscr_empty_ch0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_ch0_int_raw:1;
+        /** in_dscr_task_ovf_ch0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_ch0_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch0_reg_t;
+
+/** Type of in_int_ena_ch0 register
+ *  RX CH0  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch0_int_ena:1;
+        /** in_suc_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch0_int_ena:1;
+        /** in_err_eof_ch0_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch0_int_ena:1;
+        /** in_dscr_err_ch0_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch0_int_ena:1;
+        /** infifo_ovf_l1_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch0_int_ena:1;
+        /** infifo_udf_l1_ch0_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch0_int_ena:1;
+        /** infifo_ovf_l2_ch0_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch0_int_ena:1;
+        /** infifo_udf_l2_ch0_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch0_int_ena:1;
+        /** in_dscr_empty_ch0_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch0_int_ena:1;
+        /** in_dscr_task_ovf_ch0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch0_int_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch0_reg_t;
+
+/** Type of in_int_st_ch0 register
+ *  RX CH0  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch0_int_st:1;
+        /** in_suc_eof_ch0_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch0_int_st:1;
+        /** in_err_eof_ch0_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch0_int_st:1;
+        /** in_dscr_err_ch0_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch0_int_st:1;
+        /** infifo_ovf_l1_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch0_int_st:1;
+        /** infifo_udf_l1_ch0_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch0_int_st:1;
+        /** infifo_ovf_l2_ch0_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch0_int_st:1;
+        /** infifo_udf_l2_ch0_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch0_int_st:1;
+        /** in_dscr_empty_ch0_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch0_int_st:1;
+        /** in_dscr_task_ovf_ch0_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch0_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch0_reg_t;
+
+/** Type of in_int_clr_ch0 register
+ *  RX CH0  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch0_int_clr:1;
+        /** in_suc_eof_ch0_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch0_int_clr:1;
+        /** in_err_eof_ch0_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch0_int_clr:1;
+        /** in_dscr_err_ch0_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch0_int_clr:1;
+        /** infifo_ovf_l1_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch0_int_clr:1;
+        /** infifo_udf_l1_ch0_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch0_int_clr:1;
+        /** infifo_ovf_l2_ch0_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch0_int_clr:1;
+        /** infifo_udf_l2_ch0_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch0_int_clr:1;
+        /** in_dscr_empty_ch0_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch0_int_clr:1;
+        /** in_dscr_task_ovf_ch0_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch0_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch0_reg_t;
+
+/** Type of in_int_raw_ch1 register
+ *  RX CH1  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
+         */
+        uint32_t in_done_ch1_int_raw:1;
+        /** in_suc_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
+         */
+        uint32_t in_suc_eof_ch1_int_raw:1;
+        /** in_err_eof_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_ch1_int_raw:1;
+        /** in_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 1.
+         */
+        uint32_t in_dscr_err_ch1_int_raw:1;
+        /** infifo_ovf_l1_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch1_int_raw:1;
+        /** infifo_udf_l1_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch1_int_raw:1;
+        /** infifo_ovf_l2_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_ch1_int_raw:1;
+        /** infifo_udf_l2_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_ch1_int_raw:1;
+        /** in_dscr_empty_ch1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_ch1_int_raw:1;
+        /** in_dscr_task_ovf_ch1_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_ch1_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch1_reg_t;
+
+/** Type of in_int_ena_ch1 register
+ *  RX CH1  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch1_int_ena:1;
+        /** in_suc_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch1_int_ena:1;
+        /** in_err_eof_ch1_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch1_int_ena:1;
+        /** in_dscr_err_ch1_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch1_int_ena:1;
+        /** infifo_ovf_l1_ch1_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch1_int_ena:1;
+        /** infifo_udf_l1_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch1_int_ena:1;
+        /** infifo_ovf_l2_ch1_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch1_int_ena:1;
+        /** infifo_udf_l2_ch1_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch1_int_ena:1;
+        /** in_dscr_empty_ch1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch1_int_ena:1;
+        /** in_dscr_task_ovf_ch1_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch1_int_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch1_reg_t;
+
+/** Type of in_int_st_ch1 register
+ *  RX CH1  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch1_int_st:1;
+        /** in_suc_eof_ch1_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch1_int_st:1;
+        /** in_err_eof_ch1_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch1_int_st:1;
+        /** in_dscr_err_ch1_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch1_int_st:1;
+        /** infifo_ovf_l1_ch1_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch1_int_st:1;
+        /** infifo_udf_l1_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch1_int_st:1;
+        /** infifo_ovf_l2_ch1_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch1_int_st:1;
+        /** infifo_udf_l2_ch1_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch1_int_st:1;
+        /** in_dscr_empty_ch1_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch1_int_st:1;
+        /** in_dscr_task_ovf_ch1_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch1_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch1_reg_t;
+
+/** Type of in_int_clr_ch1 register
+ *  RX CH1  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch1_int_clr:1;
+        /** in_suc_eof_ch1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch1_int_clr:1;
+        /** in_err_eof_ch1_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch1_int_clr:1;
+        /** in_dscr_err_ch1_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch1_int_clr:1;
+        /** infifo_ovf_l1_ch1_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch1_int_clr:1;
+        /** infifo_udf_l1_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch1_int_clr:1;
+        /** infifo_ovf_l2_ch1_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch1_int_clr:1;
+        /** infifo_udf_l2_ch1_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch1_int_clr:1;
+        /** in_dscr_empty_ch1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch1_int_clr:1;
+        /** in_dscr_task_ovf_ch1_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch1_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch1_reg_t;
+
+/** Type of in_int_raw_ch2 register
+ *  RX CH2  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
+         */
+        uint32_t in_done_ch2_int_raw:1;
+        /** in_suc_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
+         */
+        uint32_t in_suc_eof_ch2_int_raw:1;
+        /** in_err_eof_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_ch2_int_raw:1;
+        /** in_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 1.
+         */
+        uint32_t in_dscr_err_ch2_int_raw:1;
+        /** infifo_ovf_l1_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch2_int_raw:1;
+        /** infifo_udf_l1_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch2_int_raw:1;
+        /** infifo_ovf_l2_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_ch2_int_raw:1;
+        /** infifo_udf_l2_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_ch2_int_raw:1;
+        /** in_dscr_empty_ch2_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_ch2_int_raw:1;
+        /** in_dscr_task_ovf_ch2_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_ch2_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch2_reg_t;
+
+/** Type of in_int_ena_ch2 register
+ *  RX CH2  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch2_int_ena:1;
+        /** in_suc_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch2_int_ena:1;
+        /** in_err_eof_ch2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch2_int_ena:1;
+        /** in_dscr_err_ch2_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch2_int_ena:1;
+        /** infifo_ovf_l1_ch2_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch2_int_ena:1;
+        /** infifo_udf_l1_ch2_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch2_int_ena:1;
+        /** infifo_ovf_l2_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch2_int_ena:1;
+        /** infifo_udf_l2_ch2_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch2_int_ena:1;
+        /** in_dscr_empty_ch2_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch2_int_ena:1;
+        /** in_dscr_task_ovf_ch2_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch2_int_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch2_reg_t;
+
+/** Type of in_int_st_ch2 register
+ *  RX CH2  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch2_int_st:1;
+        /** in_suc_eof_ch2_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch2_int_st:1;
+        /** in_err_eof_ch2_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch2_int_st:1;
+        /** in_dscr_err_ch2_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch2_int_st:1;
+        /** infifo_ovf_l1_ch2_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch2_int_st:1;
+        /** infifo_udf_l1_ch2_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch2_int_st:1;
+        /** infifo_ovf_l2_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch2_int_st:1;
+        /** infifo_udf_l2_ch2_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch2_int_st:1;
+        /** in_dscr_empty_ch2_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch2_int_st:1;
+        /** in_dscr_task_ovf_ch2_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch2_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch2_reg_t;
+
+/** Type of in_int_clr_ch2 register
+ *  RX CH2  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch2_int_clr:1;
+        /** in_suc_eof_ch2_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch2_int_clr:1;
+        /** in_err_eof_ch2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch2_int_clr:1;
+        /** in_dscr_err_ch2_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch2_int_clr:1;
+        /** infifo_ovf_l1_ch2_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch2_int_clr:1;
+        /** infifo_udf_l1_ch2_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch2_int_clr:1;
+        /** infifo_ovf_l2_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch2_int_clr:1;
+        /** infifo_udf_l2_ch2_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch2_int_clr:1;
+        /** in_dscr_empty_ch2_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch2_int_clr:1;
+        /** in_dscr_task_ovf_ch2_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch2_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch2_reg_t;
+
+/** Type of in_int_raw_ch3 register
+ *  RX CH3  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch3_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
+         */
+        uint32_t in_done_ch3_int_raw:1;
+        /** in_suc_eof_ch3_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
+         */
+        uint32_t in_suc_eof_ch3_int_raw:1;
+        /** in_err_eof_ch3_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_ch3_int_raw:1;
+        /** in_dscr_err_ch3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 1.
+         */
+        uint32_t in_dscr_err_ch3_int_raw:1;
+        /** infifo_ovf_l1_ch3_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch3_int_raw:1;
+        /** infifo_udf_l1_ch3_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch3_int_raw:1;
+        /** infifo_ovf_l2_ch3_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_ch3_int_raw:1;
+        /** infifo_udf_l2_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_ch3_int_raw:1;
+        /** in_dscr_empty_ch3_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_ch3_int_raw:1;
+        /** in_dscr_task_ovf_ch3_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_ch3_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch3_reg_t;
+
+/** Type of in_int_ena_ch3 register
+ *  RX CH3  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch3_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch3_int_ena:1;
+        /** in_suc_eof_ch3_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch3_int_ena:1;
+        /** in_err_eof_ch3_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch3_int_ena:1;
+        /** in_dscr_err_ch3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch3_int_ena:1;
+        /** infifo_ovf_l1_ch3_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch3_int_ena:1;
+        /** infifo_udf_l1_ch3_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch3_int_ena:1;
+        /** infifo_ovf_l2_ch3_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch3_int_ena:1;
+        /** infifo_udf_l2_ch3_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch3_int_ena:1;
+        /** in_dscr_empty_ch3_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch3_int_ena:1;
+        /** in_dscr_task_ovf_ch3_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch3_int_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch3_reg_t;
+
+/** Type of in_int_st_ch3 register
+ *  RX CH3  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch3_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch3_int_st:1;
+        /** in_suc_eof_ch3_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch3_int_st:1;
+        /** in_err_eof_ch3_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch3_int_st:1;
+        /** in_dscr_err_ch3_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch3_int_st:1;
+        /** infifo_ovf_l1_ch3_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch3_int_st:1;
+        /** infifo_udf_l1_ch3_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch3_int_st:1;
+        /** infifo_ovf_l2_ch3_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch3_int_st:1;
+        /** infifo_udf_l2_ch3_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch3_int_st:1;
+        /** in_dscr_empty_ch3_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch3_int_st:1;
+        /** in_dscr_task_ovf_ch3_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch3_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch3_reg_t;
+
+/** Type of in_int_clr_ch3 register
+ *  RX CH3  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch3_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch3_int_clr:1;
+        /** in_suc_eof_ch3_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch3_int_clr:1;
+        /** in_err_eof_ch3_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch3_int_clr:1;
+        /** in_dscr_err_ch3_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch3_int_clr:1;
+        /** infifo_ovf_l1_ch3_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch3_int_clr:1;
+        /** infifo_udf_l1_ch3_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch3_int_clr:1;
+        /** infifo_ovf_l2_ch3_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch3_int_clr:1;
+        /** infifo_udf_l2_ch3_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch3_int_clr:1;
+        /** in_dscr_empty_ch3_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch3_int_clr:1;
+        /** in_dscr_task_ovf_ch3_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch3_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch3_reg_t;
+
+/** Type of in_int_raw_ch4 register
+ *  RX CH4  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch4_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
+         */
+        uint32_t in_done_ch4_int_raw:1;
+        /** in_suc_eof_ch4_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
+         */
+        uint32_t in_suc_eof_ch4_int_raw:1;
+        /** in_err_eof_ch4_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_ch4_int_raw:1;
+        /** in_dscr_err_ch4_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 1.
+         */
+        uint32_t in_dscr_err_ch4_int_raw:1;
+        /** infifo_ovf_l1_ch4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch4_int_raw:1;
+        /** infifo_udf_l1_ch4_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch4_int_raw:1;
+        /** infifo_ovf_l2_ch4_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_ch4_int_raw:1;
+        /** infifo_udf_l2_ch4_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_ch4_int_raw:1;
+        /** in_dscr_empty_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_ch4_int_raw:1;
+        /** in_dscr_task_ovf_ch4_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_ch4_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch4_reg_t;
+
+/** Type of in_int_ena_ch4 register
+ *  RX CH4  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch4_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch4_int_ena:1;
+        /** in_suc_eof_ch4_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch4_int_ena:1;
+        /** in_err_eof_ch4_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch4_int_ena:1;
+        /** in_dscr_err_ch4_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch4_int_ena:1;
+        /** infifo_ovf_l1_ch4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch4_int_ena:1;
+        /** infifo_udf_l1_ch4_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch4_int_ena:1;
+        /** infifo_ovf_l2_ch4_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch4_int_ena:1;
+        /** infifo_udf_l2_ch4_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch4_int_ena:1;
+        /** in_dscr_empty_ch4_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch4_int_ena:1;
+        /** in_dscr_task_ovf_ch4_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch4_int_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch4_reg_t;
+
+/** Type of in_int_st_ch4 register
+ *  RX CH4  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch4_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch4_int_st:1;
+        /** in_suc_eof_ch4_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch4_int_st:1;
+        /** in_err_eof_ch4_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch4_int_st:1;
+        /** in_dscr_err_ch4_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch4_int_st:1;
+        /** infifo_ovf_l1_ch4_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch4_int_st:1;
+        /** infifo_udf_l1_ch4_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch4_int_st:1;
+        /** infifo_ovf_l2_ch4_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch4_int_st:1;
+        /** infifo_udf_l2_ch4_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch4_int_st:1;
+        /** in_dscr_empty_ch4_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch4_int_st:1;
+        /** in_dscr_task_ovf_ch4_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch4_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch4_reg_t;
+
+/** Type of in_int_clr_ch4 register
+ *  RX CH4  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch4_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch4_int_clr:1;
+        /** in_suc_eof_ch4_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch4_int_clr:1;
+        /** in_err_eof_ch4_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch4_int_clr:1;
+        /** in_dscr_err_ch4_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch4_int_clr:1;
+        /** infifo_ovf_l1_ch4_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch4_int_clr:1;
+        /** infifo_udf_l1_ch4_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch4_int_clr:1;
+        /** infifo_ovf_l2_ch4_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch4_int_clr:1;
+        /** infifo_udf_l2_ch4_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch4_int_clr:1;
+        /** in_dscr_empty_ch4_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch4_int_clr:1;
+        /** in_dscr_task_ovf_ch4_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch4_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch4_reg_t;
+
+/** Type of in_int_raw_ch5 register
+ *  RX CH5  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch5_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
+         */
+        uint32_t in_done_ch5_int_raw:1;
+        /** in_suc_eof_ch5_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
+         */
+        uint32_t in_suc_eof_ch5_int_raw:1;
+        /** infifo_ovf_l1_ch5_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch5_int_raw:1;
+        /** infifo_udf_l1_ch5_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch5_int_raw:1;
+        /** fetch_mb_col_cnt_ovf_ch5_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t fetch_mb_col_cnt_ovf_ch5_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch5_reg_t;
+
+/** Type of in_int_ena_ch5 register
+ *  RX CH5  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch5_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch5_int_ena:1;
+        /** in_suc_eof_ch5_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch5_int_ena:1;
+        /** infifo_ovf_l1_ch5_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch5_int_ena:1;
+        /** infifo_udf_l1_ch5_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch5_int_ena:1;
+        /** fetch_mb_col_cnt_ovf_ch5_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t fetch_mb_col_cnt_ovf_ch5_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch5_reg_t;
+
+/** Type of in_int_st_ch5 register
+ *  RX CH5  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch5_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch5_int_st:1;
+        /** in_suc_eof_ch5_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch5_int_st:1;
+        /** infifo_ovf_l1_ch5_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch5_int_st:1;
+        /** infifo_udf_l1_ch5_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch5_int_st:1;
+        /** fetch_mb_col_cnt_ovf_ch5_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t fetch_mb_col_cnt_ovf_ch5_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch5_reg_t;
+
+/** Type of in_int_clr_ch5 register
+ *  RX CH5  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch5_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch5_int_clr:1;
+        /** in_suc_eof_ch5_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch5_int_clr:1;
+        /** infifo_ovf_l1_ch5_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch5_int_clr:1;
+        /** infifo_udf_l1_ch5_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch5_int_clr:1;
+        /** fetch_mb_col_cnt_ovf_ch5_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t fetch_mb_col_cnt_ovf_ch5_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch5_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of outfifo_status_ch0 register
+ *  TX CH0 outfifo status register
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_ch0 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l2_ch0:1;
+        /** outfifo_empty_l2_ch0 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l2_ch0:1;
+        /** outfifo_cnt_l2_ch0 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l2_ch0:4;
+        /** outfifo_full_l1_ch0 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l1_ch0:1;
+        /** outfifo_empty_l1_ch0 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l1_ch0:1;
+        /** outfifo_cnt_l1_ch0 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l1_ch0:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3_ch0 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l3_ch0:1;
+        /** outfifo_empty_l3_ch0 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l3_ch0:1;
+        /** outfifo_cnt_l3_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l3_ch0:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_outfifo_status_ch0_reg_t;
+
+/** Type of out_state_ch0 register
+ *  TX CH0 state register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_ch0:18;
+        /** out_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_ch0:2;
+        /** out_state_ch0 : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_ch0:4;
+        /** out_reset_avail_ch0 : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_ch0:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_out_state_ch0_reg_t;
+
+/** Type of out_eof_des_addr_ch0 register
+ *  TX CH0 eof des addr register
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_eof_des_addr_ch0_reg_t;
+
+/** Type of out_dscr_ch0 register
+ *  TX CH0 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_ch0_reg_t;
+
+/** Type of out_dscr_bf0_ch0 register
+ *  TX CH0 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf0_ch0_reg_t;
+
+/** Type of out_dscr_bf1_ch0 register
+ *  TX CH0 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf1_ch0_reg_t;
+
+/** Type of out_ro_status_ch0 register
+ *  TX CH0 reorder status register
+ */
+typedef union {
+    struct {
+        /** outfifo_ro_cnt_ch0 : RO; bitpos: [1:0]; default: 0;
+         *  The register stores the 8byte number of the data in reorder Tx FIFO for channel 0.
+         */
+        uint32_t outfifo_ro_cnt_ch0:2;
+        uint32_t reserved_2:4;
+        /** out_ro_wr_state_ch0 : RO; bitpos: [7:6]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t out_ro_wr_state_ch0:2;
+        /** out_ro_rd_state_ch0 : RO; bitpos: [9:8]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t out_ro_rd_state_ch0:2;
+        /** out_pixel_byte_ch0 : RO; bitpos: [13:10]; default: 2;
+         *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t out_pixel_byte_ch0:4;
+        /** out_burst_block_num_ch0 : RO; bitpos: [17:14]; default: 0;
+         *  the number of macro blocks contained in a burst of data at TX channel
+         */
+        uint32_t out_burst_block_num_ch0:4;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} h264_dma_out_ro_status_ch0_reg_t;
+
+/** Type of outfifo_status_ch1 register
+ *  TX CH1 outfifo status register
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_ch1 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t outfifo_full_l2_ch1:1;
+        /** outfifo_empty_l2_ch1 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t outfifo_empty_l2_ch1:1;
+        /** outfifo_cnt_l2_ch1 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t outfifo_cnt_l2_ch1:4;
+        /** outfifo_full_l1_ch1 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t outfifo_full_l1_ch1:1;
+        /** outfifo_empty_l1_ch1 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t outfifo_empty_l1_ch1:1;
+        /** outfifo_cnt_l1_ch1 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t outfifo_cnt_l1_ch1:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3_ch1 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t outfifo_full_l3_ch1:1;
+        /** outfifo_empty_l3_ch1 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t outfifo_empty_l3_ch1:1;
+        /** outfifo_cnt_l3_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t outfifo_cnt_l3_ch1:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_outfifo_status_ch1_reg_t;
+
+/** Type of out_state_ch1 register
+ *  TX CH1 state register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_ch1:18;
+        /** out_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_ch1:2;
+        /** out_state_ch1 : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_ch1:4;
+        /** out_reset_avail_ch1 : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_ch1:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_out_state_ch1_reg_t;
+
+/** Type of out_eof_des_addr_ch1 register
+ *  TX CH1 eof des addr register
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_eof_des_addr_ch1_reg_t;
+
+/** Type of out_dscr_ch1 register
+ *  TX CH1 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_ch1_reg_t;
+
+/** Type of out_dscr_bf0_ch1 register
+ *  TX CH1 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf0_ch1_reg_t;
+
+/** Type of out_dscr_bf1_ch1 register
+ *  TX CH1 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf1_ch1_reg_t;
+
+/** Type of outfifo_status_ch2 register
+ *  TX CH2 outfifo status register
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_ch2 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l2_ch2:1;
+        /** outfifo_empty_l2_ch2 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l2_ch2:1;
+        /** outfifo_cnt_l2_ch2 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l2_ch2:4;
+        /** outfifo_full_l1_ch2 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l1_ch2:1;
+        /** outfifo_empty_l1_ch2 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l1_ch2:1;
+        /** outfifo_cnt_l1_ch2 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l1_ch2:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3_ch2 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l3_ch2:1;
+        /** outfifo_empty_l3_ch2 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l3_ch2:1;
+        /** outfifo_cnt_l3_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l3_ch2:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_outfifo_status_ch2_reg_t;
+
+/** Type of out_state_ch2 register
+ *  TX CH2 state register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_ch2:18;
+        /** out_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_ch2:2;
+        /** out_state_ch2 : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_ch2:4;
+        /** out_reset_avail_ch2 : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_ch2:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_out_state_ch2_reg_t;
+
+/** Type of out_eof_des_addr_ch2 register
+ *  TX CH2 eof des addr register
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_eof_des_addr_ch2_reg_t;
+
+/** Type of out_dscr_ch2 register
+ *  TX CH2 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_ch2_reg_t;
+
+/** Type of out_dscr_bf0_ch2 register
+ *  TX CH2 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf0_ch2_reg_t;
+
+/** Type of out_dscr_bf1_ch2 register
+ *  TX CH2 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf1_ch2_reg_t;
+
+/** Type of outfifo_status_ch3 register
+ *  TX CH3 outfifo status register
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_ch3 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l2_ch3:1;
+        /** outfifo_empty_l2_ch3 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l2_ch3:1;
+        /** outfifo_cnt_l2_ch3 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l2_ch3:4;
+        /** outfifo_full_l1_ch3 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l1_ch3:1;
+        /** outfifo_empty_l1_ch3 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l1_ch3:1;
+        /** outfifo_cnt_l1_ch3 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l1_ch3:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3_ch3 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l3_ch3:1;
+        /** outfifo_empty_l3_ch3 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l3_ch3:1;
+        /** outfifo_cnt_l3_ch3 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l3_ch3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_outfifo_status_ch3_reg_t;
+
+/** Type of out_state_ch3 register
+ *  TX CH3 state register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch3 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_ch3:18;
+        /** out_dscr_state_ch3 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_ch3:2;
+        /** out_state_ch3 : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_ch3:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_state_ch3_reg_t;
+
+/** Type of out_eof_des_addr_ch3 register
+ *  TX CH3 eof des addr register
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_eof_des_addr_ch3_reg_t;
+
+/** Type of out_dscr_ch3 register
+ *  TX CH3 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_ch3_reg_t;
+
+/** Type of out_dscr_bf0_ch3 register
+ *  TX CH3 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf0_ch3_reg_t;
+
+/** Type of out_dscr_bf1_ch3 register
+ *  TX CH3 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf1_ch3_reg_t;
+
+/** Type of outfifo_status_ch4 register
+ *  TX CH4 outfifo status register
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_ch4 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l2_ch4:1;
+        /** outfifo_empty_l2_ch4 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l2_ch4:1;
+        /** outfifo_cnt_l2_ch4 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l2_ch4:4;
+        /** outfifo_full_l1_ch4 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l1_ch4:1;
+        /** outfifo_empty_l1_ch4 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l1_ch4:1;
+        /** outfifo_cnt_l1_ch4 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l1_ch4:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3_ch4 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l3_ch4:1;
+        /** outfifo_empty_l3_ch4 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l3_ch4:1;
+        /** outfifo_cnt_l3_ch4 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l3_ch4:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_outfifo_status_ch4_reg_t;
+
+/** Type of out_state_ch4 register
+ *  TX CH4 state register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch4 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_ch4:18;
+        /** out_dscr_state_ch4 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_ch4:2;
+        /** out_state_ch4 : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_ch4:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_state_ch4_reg_t;
+
+/** Type of out_eof_des_addr_ch4 register
+ *  TX CH4 eof des addr register
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_eof_des_addr_ch4_reg_t;
+
+/** Type of out_dscr_ch4 register
+ *  TX CH4 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_ch4_reg_t;
+
+/** Type of out_dscr_bf0_ch4 register
+ *  TX CH4 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf0_ch4_reg_t;
+
+/** Type of out_dscr_bf1_ch4 register
+ *  TX CH4 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf1_ch4_reg_t;
+
+/** Type of infifo_status_ch0 register
+ *  RX CH0 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_ch0 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_ch0:1;
+        /** infifo_empty_l2_ch0 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_ch0:1;
+        /** infifo_cnt_l2_ch0 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_ch0:4;
+        /** infifo_full_l1_ch0 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t infifo_full_l1_ch0:1;
+        /** infifo_empty_l1_ch0 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t infifo_empty_l1_ch0:1;
+        /** infifo_cnt_l1_ch0 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t infifo_cnt_l1_ch0:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3_ch0 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t infifo_full_l3_ch0:1;
+        /** infifo_empty_l3_ch0 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t infifo_empty_l3_ch0:1;
+        /** infifo_cnt_l3_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t infifo_cnt_l3_ch0:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch0_reg_t;
+
+/** Type of in_state_ch0 register
+ *  RX CH0 state register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_ch0:18;
+        /** in_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t in_dscr_state_ch0:2;
+        /** in_state_ch0 : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch0:3;
+        /** in_reset_avail_ch0 : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch0:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch0_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch0 register
+ *  RX CH0 eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_suc_eof_des_addr_ch0_reg_t;
+
+/** Type of in_err_eof_des_addr_ch0 register
+ *  RX CH0 err eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_err_eof_des_addr_ch0_reg_t;
+
+/** Type of in_dscr_ch0 register
+ *  RX CH0 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_ch0_reg_t;
+
+/** Type of in_dscr_bf0_ch0 register
+ *  RX CH0 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf0_ch0_reg_t;
+
+/** Type of in_dscr_bf1_ch0 register
+ *  RX CH0 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf1_ch0_reg_t;
+
+/** Type of infifo_status_ch1 register
+ *  RX CH1 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_ch1 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_ch1:1;
+        /** infifo_empty_l2_ch1 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_ch1:1;
+        /** infifo_cnt_l2_ch1 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_ch1:4;
+        /** infifo_full_l1_ch1 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l1_ch1:1;
+        /** infifo_empty_l1_ch1 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l1_ch1:1;
+        /** infifo_cnt_l1_ch1 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1_ch1:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3_ch1 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l3_ch1:1;
+        /** infifo_empty_l3_ch1 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l3_ch1:1;
+        /** infifo_cnt_l3_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l3_ch1:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch1_reg_t;
+
+/** Type of in_state_ch1 register
+ *  RX CH1 state register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_ch1:18;
+        /** in_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t in_dscr_state_ch1:2;
+        /** in_state_ch1 : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch1:3;
+        /** in_reset_avail_ch1 : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch1:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch1_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch1 register
+ *  RX CH1 eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_suc_eof_des_addr_ch1_reg_t;
+
+/** Type of in_err_eof_des_addr_ch1 register
+ *  RX CH1 err eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_err_eof_des_addr_ch1_reg_t;
+
+/** Type of in_dscr_ch1 register
+ *  RX CH1 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_ch1_reg_t;
+
+/** Type of in_dscr_bf0_ch1 register
+ *  RX CH1 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf0_ch1_reg_t;
+
+/** Type of in_dscr_bf1_ch1 register
+ *  RX CH1 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf1_ch1_reg_t;
+
+/** Type of infifo_status_ch2 register
+ *  RX CH2 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_ch2 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_ch2:1;
+        /** infifo_empty_l2_ch2 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_ch2:1;
+        /** infifo_cnt_l2_ch2 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_ch2:4;
+        /** infifo_full_l1_ch2 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l1_ch2:1;
+        /** infifo_empty_l1_ch2 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l1_ch2:1;
+        /** infifo_cnt_l1_ch2 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1_ch2:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3_ch2 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l3_ch2:1;
+        /** infifo_empty_l3_ch2 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l3_ch2:1;
+        /** infifo_cnt_l3_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l3_ch2:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch2_reg_t;
+
+/** Type of in_state_ch2 register
+ *  RX CH2 state register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_ch2:18;
+        /** in_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t in_dscr_state_ch2:2;
+        /** in_state_ch2 : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch2:3;
+        /** in_reset_avail_ch2 : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch2:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch2_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch2 register
+ *  RX CH2 eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_suc_eof_des_addr_ch2_reg_t;
+
+/** Type of in_err_eof_des_addr_ch2 register
+ *  RX CH2 err eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_err_eof_des_addr_ch2_reg_t;
+
+/** Type of in_dscr_ch2 register
+ *  RX CH2 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_ch2_reg_t;
+
+/** Type of in_dscr_bf0_ch2 register
+ *  RX CH2 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf0_ch2_reg_t;
+
+/** Type of in_dscr_bf1_ch2 register
+ *  RX CH2 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf1_ch2_reg_t;
+
+/** Type of infifo_status_ch3 register
+ *  RX CH3 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_ch3 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_ch3:1;
+        /** infifo_empty_l2_ch3 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_ch3:1;
+        /** infifo_cnt_l2_ch3 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_ch3:4;
+        /** infifo_full_l1_ch3 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l1_ch3:1;
+        /** infifo_empty_l1_ch3 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l1_ch3:1;
+        /** infifo_cnt_l1_ch3 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1_ch3:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3_ch3 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l3_ch3:1;
+        /** infifo_empty_l3_ch3 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l3_ch3:1;
+        /** infifo_cnt_l3_ch3 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l3_ch3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch3_reg_t;
+
+/** Type of in_state_ch3 register
+ *  RX CH3 state register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch3 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_ch3:18;
+        /** in_dscr_state_ch3 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t in_dscr_state_ch3:2;
+        /** in_state_ch3 : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch3:3;
+        /** in_reset_avail_ch3 : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch3:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch3_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch3 register
+ *  RX CH3 eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_suc_eof_des_addr_ch3_reg_t;
+
+/** Type of in_err_eof_des_addr_ch3 register
+ *  RX CH3 err eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_err_eof_des_addr_ch3_reg_t;
+
+/** Type of in_dscr_ch3 register
+ *  RX CH3 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_ch3_reg_t;
+
+/** Type of in_dscr_bf0_ch3 register
+ *  RX CH3 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf0_ch3_reg_t;
+
+/** Type of in_dscr_bf1_ch3 register
+ *  RX CH3 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf1_ch3_reg_t;
+
+/** Type of infifo_status_ch4 register
+ *  RX CH4 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_ch4 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_ch4:1;
+        /** infifo_empty_l2_ch4 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_ch4:1;
+        /** infifo_cnt_l2_ch4 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_ch4:4;
+        /** infifo_full_l1_ch4 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l1_ch4:1;
+        /** infifo_empty_l1_ch4 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l1_ch4:1;
+        /** infifo_cnt_l1_ch4 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1_ch4:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3_ch4 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l3_ch4:1;
+        /** infifo_empty_l3_ch4 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l3_ch4:1;
+        /** infifo_cnt_l3_ch4 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l3_ch4:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch4_reg_t;
+
+/** Type of in_state_ch4 register
+ *  RX CH4 state register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch4 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_ch4:18;
+        /** in_dscr_state_ch4 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t in_dscr_state_ch4:2;
+        /** in_state_ch4 : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch4:3;
+        /** in_reset_avail_ch4 : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch4:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch4_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch4 register
+ *  RX CH4 eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_suc_eof_des_addr_ch4_reg_t;
+
+/** Type of in_err_eof_des_addr_ch4 register
+ *  RX CH4 err eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_err_eof_des_addr_ch4_reg_t;
+
+/** Type of in_dscr_ch4 register
+ *  RX CH4 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_ch4_reg_t;
+
+/** Type of in_dscr_bf0_ch4 register
+ *  RX CH4 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf0_ch4_reg_t;
+
+/** Type of in_dscr_bf1_ch4 register
+ *  RX CH4 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf1_ch4_reg_t;
+
+/** Type of infifo_status_ch5 register
+ *  RX CH5 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l1_ch5 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l1_ch5:1;
+        /** infifo_empty_l1_ch5 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l1_ch5:1;
+        /** infifo_cnt_l1_ch5 : RO; bitpos: [6:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1_ch5:5;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch5_reg_t;
+
+/** Type of in_state_ch5 register
+ *  RX CH5 state register
+ */
+typedef union {
+    struct {
+        /** in_state_ch5 : RO; bitpos: [2:0]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch5:3;
+        /** in_reset_avail_ch5 : RO; bitpos: [3]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch5:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch5_reg_t;
+
+
+/** Group: out_link addr register */
+/** Type of out_link_addr_ch0 register
+ *  TX CH0 out_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_link_addr_ch0_reg_t;
+
+
+/** Group: tx ch0 arb register */
+/** Type of out_arb_ch0 register
+ *  TX CH0 arb register
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_ch0 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_ch0:4;
+        /** exter_out_arb_priority_ch0 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_out_arb_priority_ch0:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} h264_dma_out_arb_ch0_reg_t;
+
+
+/** Group: TX CH0 test mode register */
+/** Type of out_mode_enable_ch0 register
+ *  tx CH0 mode enable register
+ */
+typedef union {
+    struct {
+        /** out_test_mode_enable_ch0 : R/W; bitpos: [0]; default: 0;
+         *  tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test
+         *  mode
+         */
+        uint32_t out_test_mode_enable_ch0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} h264_dma_out_mode_enable_ch0_reg_t;
+
+/** Type of out_mode_yuv_ch0 register
+ *  tx CH0 test mode yuv value register
+ */
+typedef union {
+    struct {
+        /** out_test_y_value_ch0 : R/W; bitpos: [7:0]; default: 0;
+         *  tx CH0 test mode y value
+         */
+        uint32_t out_test_y_value_ch0:8;
+        /** out_test_u_value_ch0 : R/W; bitpos: [15:8]; default: 0;
+         *  tx CH0 test mode u value
+         */
+        uint32_t out_test_u_value_ch0:8;
+        /** out_test_v_value_ch0 : R/W; bitpos: [23:16]; default: 0;
+         *  tx CH0 test mode v value
+         */
+        uint32_t out_test_v_value_ch0:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_mode_yuv_ch0_reg_t;
+
+
+/** Group: ETM config register */
+/** Type of out_etm_conf_ch0 register
+ *  TX CH0 ETM config register
+ */
+typedef union {
+    struct {
+        /** out_etm_en_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t out_etm_en_ch0:1;
+        /** out_etm_loop_en_ch0 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t out_etm_loop_en_ch0:1;
+        /** out_dscr_task_mak_ch0 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t out_dscr_task_mak_ch0:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_out_etm_conf_ch0_reg_t;
+
+
+/** Group: TX CH0 debug info */
+/** Type of out_buf_len_ch0 register
+ *  tx CH0 buf len register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_buf_len_hb_ch0 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_buf_len_hb_ch0:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_ch0_reg_t;
+
+/** Type of out_fifo_bcnt_ch0 register
+ *  tx CH0 fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt_ch0 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt_ch0:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_out_fifo_bcnt_ch0_reg_t;
+
+/** Type of out_push_bytecnt_ch0 register
+ *  tx CH0 push byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_push_bytecnt_ch0 : RO; bitpos: [7:0]; default: 255;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_push_bytecnt_ch0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_out_push_bytecnt_ch0_reg_t;
+
+/** Type of out_xaddr_ch0 register
+ *  tx CH0 xaddr register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_xaddr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_xaddr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_xaddr_ch0_reg_t;
+
+
+/** Group: TX CH1 config0 register */
+/** Type of out_conf0_ch1 register
+ *  TX CH1 config0 register
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_ch1 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_ch1:1;
+        /** out_eof_mode_ch1 : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_ch1:1;
+        /** outdscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch1:1;
+        /** out_ecc_aes_en_ch1 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_ch1:1;
+        /** out_check_owner_ch1 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_ch1:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length_ch1 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 64 bytes
+         */
+        uint32_t out_mem_burst_length_ch1:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en_ch1 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_ch1:1;
+        uint32_t reserved_13:11;
+        /** out_rst_ch1 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_ch1:1;
+        /** out_cmd_disable_ch1 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_ch1:1;
+        /** out_arb_weight_opt_dis_ch1 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_ch1:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_out_conf0_ch1_reg_t;
+
+
+/** Group: TX CH1 out_link dscr addr register */
+/** Type of out_link_addr_ch1 register
+ *  TX CH1 out_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_link_addr_ch1_reg_t;
+
+
+/** Group: TX CH1 arb register */
+/** Type of out_arb_ch1 register
+ *  TX CH1 arb register
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_ch1 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_ch1:4;
+        uint32_t reserved_4:2;
+        /** inter_out_arb_priority_ch1 : R/W; bitpos: [6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_out_arb_priority_ch1:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_dma_out_arb_ch1_reg_t;
+
+
+/** Group: TX CH1 ETM config register */
+/** Type of out_etm_conf_ch1 register
+ *  TX CH1 ETM config register
+ */
+typedef union {
+    struct {
+        /** out_etm_en_ch1 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t out_etm_en_ch1:1;
+        /** out_etm_loop_en_ch1 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t out_etm_loop_en_ch1:1;
+        /** out_dscr_task_mak_ch1 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t out_dscr_task_mak_ch1:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_out_etm_conf_ch1_reg_t;
+
+
+/** Group: TX CH1 debug info */
+/** Type of out_buf_len_ch1 register
+ *  tx CH1 buf len register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_buf_len_hb_ch1 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_buf_len_hb_ch1:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_ch1_reg_t;
+
+/** Type of out_fifo_bcnt_ch1 register
+ *  tx CH1 fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt_ch1 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt_ch1:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_out_fifo_bcnt_ch1_reg_t;
+
+/** Type of out_push_bytecnt_ch1 register
+ *  tx CH1 push byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_push_bytecnt_ch1 : RO; bitpos: [7:0]; default: 255;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_push_bytecnt_ch1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_out_push_bytecnt_ch1_reg_t;
+
+/** Type of out_xaddr_ch1 register
+ *  tx CH1 xaddr register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_xaddr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_xaddr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_xaddr_ch1_reg_t;
+
+
+/** Group: TX CH2 config0 register */
+/** Type of out_conf0_ch2 register
+ *  TX CH2 config0 register
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_ch2 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_ch2:1;
+        /** out_eof_mode_ch2 : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_ch2:1;
+        /** outdscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch2:1;
+        /** out_ecc_aes_en_ch2 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_ch2:1;
+        /** out_check_owner_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_ch2:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length_ch2 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 2. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_ch2:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en_ch2 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_ch2:1;
+        uint32_t reserved_13:11;
+        /** out_rst_ch2 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_ch2:1;
+        /** out_cmd_disable_ch2 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_ch2:1;
+        /** out_arb_weight_opt_dis_ch2 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_ch2:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_out_conf0_ch2_reg_t;
+
+
+/** Group: TX CH2 out_link dscr addr register */
+/** Type of out_link_addr_ch2 register
+ *  TX CH2 out_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_link_addr_ch2_reg_t;
+
+
+/** Group: TX CH2 arb register */
+/** Type of out_arb_ch2 register
+ *  TX CH2 arb register
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_ch2 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_ch2:4;
+        uint32_t reserved_4:2;
+        /** inter_out_arb_priority_ch2 : R/W; bitpos: [6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_out_arb_priority_ch2:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_dma_out_arb_ch2_reg_t;
+
+
+/** Group: TX CH2 ETM config register */
+/** Type of out_etm_conf_ch2 register
+ *  TX CH2 ETM config register
+ */
+typedef union {
+    struct {
+        /** out_etm_en_ch2 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t out_etm_en_ch2:1;
+        /** out_etm_loop_en_ch2 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t out_etm_loop_en_ch2:1;
+        /** out_dscr_task_mak_ch2 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t out_dscr_task_mak_ch2:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_out_etm_conf_ch2_reg_t;
+
+
+/** Group: TX CH2 debug info */
+/** Type of out_buf_len_ch2 register
+ *  tx CH2 buf len register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_buf_len_hb_ch2 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_buf_len_hb_ch2:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_ch2_reg_t;
+
+/** Type of out_fifo_bcnt_ch2 register
+ *  tx CH2 fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt_ch2 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt_ch2:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_out_fifo_bcnt_ch2_reg_t;
+
+/** Type of out_push_bytecnt_ch2 register
+ *  tx CH2 push byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_push_bytecnt_ch2 : RO; bitpos: [7:0]; default: 255;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_push_bytecnt_ch2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_out_push_bytecnt_ch2_reg_t;
+
+/** Type of out_xaddr_ch2 register
+ *  tx CH2 xaddr register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_xaddr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_xaddr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_xaddr_ch2_reg_t;
+
+
+/** Group: TX CH3 config0 register */
+/** Type of out_conf0_ch3 register
+ *  TX CH3 config0 register
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_ch3 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_ch3:1;
+        /** out_eof_mode_ch3 : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_ch3:1;
+        /** outdscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch3:1;
+        /** out_ecc_aes_en_ch3 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_ch3:1;
+        /** out_check_owner_ch3 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_ch3:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length_ch3 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 3. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_ch3:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en_ch3 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_ch3:1;
+        uint32_t reserved_13:13;
+        /** out_arb_weight_opt_dis_ch3 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_ch3:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_out_conf0_ch3_reg_t;
+
+
+/** Group: TX CH3 out_link dscr addr register */
+/** Type of out_link_addr_ch3 register
+ *  TX CH3 out_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch3 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_link_addr_ch3_reg_t;
+
+
+/** Group: TX CH3 arb register */
+/** Type of out_arb_ch3 register
+ *  TX CH3 arb register
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_ch3 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_ch3:4;
+        /** exter_out_arb_priority_ch3 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_out_arb_priority_ch3:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} h264_dma_out_arb_ch3_reg_t;
+
+
+/** Group: TX CH3 ETM config register */
+/** Type of out_etm_conf_ch3 register
+ *  TX CH3 ETM config register
+ */
+typedef union {
+    struct {
+        /** out_etm_en_ch3 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t out_etm_en_ch3:1;
+        /** out_etm_loop_en_ch3 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t out_etm_loop_en_ch3:1;
+        /** out_dscr_task_mak_ch3 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t out_dscr_task_mak_ch3:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_out_etm_conf_ch3_reg_t;
+
+
+/** Group: TX CH3 debug info */
+/** Type of out_buf_len_ch3 register
+ *  tx CH3 buf len register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_buf_len_hb_ch3 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_buf_len_hb_ch3:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_ch3_reg_t;
+
+/** Type of out_fifo_bcnt_ch3 register
+ *  tx CH3 fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt_ch3 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt_ch3:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_out_fifo_bcnt_ch3_reg_t;
+
+/** Type of out_push_bytecnt_ch3 register
+ *  tx CH3 push byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_push_bytecnt_ch3 : RO; bitpos: [7:0]; default: 63;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_push_bytecnt_ch3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_out_push_bytecnt_ch3_reg_t;
+
+/** Type of out_xaddr_ch3 register
+ *  tx CH3 xaddr register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_xaddr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_xaddr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_xaddr_ch3_reg_t;
+
+/** Type of out_block_buf_len_ch3 register
+ *  tx CH3 block buf len register
+ */
+typedef union {
+    struct {
+        /** out_block_buf_len_ch3 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_block_buf_len_ch3:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_block_buf_len_ch3_reg_t;
+
+
+/** Group: TX CH4 config0 register */
+/** Type of out_conf0_ch4 register
+ *  TX CH4 config0 register
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_ch4 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_ch4:1;
+        /** out_eof_mode_ch4 : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_ch4:1;
+        /** outdscr_burst_en_ch4 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch4:1;
+        /** out_ecc_aes_en_ch4 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_ch4:1;
+        /** out_check_owner_ch4 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_ch4:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length_ch4 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 4. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_ch4:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en_ch4 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_ch4:1;
+        uint32_t reserved_13:13;
+        /** out_arb_weight_opt_dis_ch4 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_ch4:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_out_conf0_ch4_reg_t;
+
+
+/** Group: TX CH4 out_link dscr addr register */
+/** Type of out_link_addr_ch4 register
+ *  TX CH4 out_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch4 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_link_addr_ch4_reg_t;
+
+
+/** Group: TX CH4 arb register */
+/** Type of out_arb_ch4 register
+ *  TX CH4 arb register
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_ch4 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_ch4:4;
+        /** exter_out_arb_priority_ch4 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_out_arb_priority_ch4:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} h264_dma_out_arb_ch4_reg_t;
+
+
+/** Group: TX CH4 ETM config register */
+/** Type of out_etm_conf_ch4 register
+ *  TX CH4 ETM config register
+ */
+typedef union {
+    struct {
+        /** out_etm_en_ch4 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t out_etm_en_ch4:1;
+        /** out_etm_loop_en_ch4 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t out_etm_loop_en_ch4:1;
+        /** out_dscr_task_mak_ch4 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t out_dscr_task_mak_ch4:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_out_etm_conf_ch4_reg_t;
+
+
+/** Group: TX CH4 debug info */
+/** Type of out_buf_len_ch4 register
+ *  tx CH4 buf len register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_buf_len_hb_ch4 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_buf_len_hb_ch4:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_ch4_reg_t;
+
+/** Type of out_fifo_bcnt_ch4 register
+ *  tx CH4 fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt_ch4 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt_ch4:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_out_fifo_bcnt_ch4_reg_t;
+
+/** Type of out_push_bytecnt_ch4 register
+ *  tx CH4 push byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_push_bytecnt_ch4 : RO; bitpos: [7:0]; default: 63;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_push_bytecnt_ch4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_out_push_bytecnt_ch4_reg_t;
+
+/** Type of out_xaddr_ch4 register
+ *  tx CH4 xaddr register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_xaddr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_xaddr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_xaddr_ch4_reg_t;
+
+/** Type of out_block_buf_len_ch4 register
+ *  tx CH4 block buf len register
+ */
+typedef union {
+    struct {
+        /** out_block_buf_len_ch4 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_block_buf_len_ch4:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_block_buf_len_ch4_reg_t;
+
+
+/** Group: RX CH0 in_link dscr addr register */
+/** Type of in_link_addr_ch0 register
+ *  RX CH0 in_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_link_addr_ch0_reg_t;
+
+
+/** Group: RX CH0 arb register */
+/** Type of in_arb_ch0 register
+ *  RX CH0 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch0 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch0:4;
+        /** exter_in_arb_priority_ch0 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_in_arb_priority_ch0:2;
+        /** inter_in_arb_priority_ch0 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch0:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch0_reg_t;
+
+
+/** Group: RX CH0 ETM config register */
+/** Type of in_etm_conf_ch0 register
+ *  RX CH0 ETM config register
+ */
+typedef union {
+    struct {
+        /** in_etm_en_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t in_etm_en_ch0:1;
+        /** in_etm_loop_en_ch0 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t in_etm_loop_en_ch0:1;
+        /** in_dscr_task_mak_ch0 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t in_dscr_task_mak_ch0:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_etm_conf_ch0_reg_t;
+
+
+/** Group: RX CH0 debug info */
+/** Type of in_fifo_cnt_ch0 register
+ *  rx CH0 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch0 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch0:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch0_reg_t;
+
+/** Type of in_pop_data_cnt_ch0 register
+ *  rx CH0 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch0 : RO; bitpos: [7:0]; default: 7;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch0_reg_t;
+
+/** Type of in_xaddr_ch0 register
+ *  rx CH0 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch0_reg_t;
+
+/** Type of in_buf_hb_rcv_ch0 register
+ *  rx CH0 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch0 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch0:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch0_reg_t;
+
+
+/** Group: RX CH1 in_link dscr addr register */
+/** Type of in_link_addr_ch1 register
+ *  RX CH1 in_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_link_addr_ch1_reg_t;
+
+
+/** Group: RX CH1 arb register */
+/** Type of in_arb_ch1 register
+ *  RX CH1 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch1 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch1:4;
+        /** exter_in_arb_priority_ch1 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_in_arb_priority_ch1:2;
+        /** inter_in_arb_priority_ch1 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch1:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch1_reg_t;
+
+
+/** Group: RX CH1 ETM config register */
+/** Type of in_etm_conf_ch1 register
+ *  RX CH1 ETM config register
+ */
+typedef union {
+    struct {
+        /** in_etm_en_ch1 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t in_etm_en_ch1:1;
+        /** in_etm_loop_en_ch1 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t in_etm_loop_en_ch1:1;
+        /** in_dscr_task_mak_ch1 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t in_dscr_task_mak_ch1:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_etm_conf_ch1_reg_t;
+
+
+/** Group: RX CH1 debug info */
+/** Type of in_fifo_cnt_ch1 register
+ *  rx CH1 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch1 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch1:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch1_reg_t;
+
+/** Type of in_pop_data_cnt_ch1 register
+ *  rx CH1 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch1 : RO; bitpos: [7:0]; default: 7;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch1_reg_t;
+
+/** Type of in_xaddr_ch1 register
+ *  rx CH1 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch1_reg_t;
+
+/** Type of in_buf_hb_rcv_ch1 register
+ *  rx CH1 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch1 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch1:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch1_reg_t;
+
+
+/** Group: RX CH2 in_link dscr addr register */
+/** Type of in_link_addr_ch2 register
+ *  RX CH2 in_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_link_addr_ch2_reg_t;
+
+
+/** Group: RX CH2 arb register */
+/** Type of in_arb_ch2 register
+ *  RX CH2 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch2 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch2:4;
+        uint32_t reserved_4:2;
+        /** inter_in_arb_priority_ch2 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch2:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch2_reg_t;
+
+
+/** Group: RX CH2 ETM config register */
+/** Type of in_etm_conf_ch2 register
+ *  RX CH2 ETM config register
+ */
+typedef union {
+    struct {
+        /** in_etm_en_ch2 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t in_etm_en_ch2:1;
+        /** in_etm_loop_en_ch2 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t in_etm_loop_en_ch2:1;
+        /** in_dscr_task_mak_ch2 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t in_dscr_task_mak_ch2:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_etm_conf_ch2_reg_t;
+
+
+/** Group: RX CH2 debug info */
+/** Type of in_fifo_cnt_ch2 register
+ *  rx CH2 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch2 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch2:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch2_reg_t;
+
+/** Type of in_pop_data_cnt_ch2 register
+ *  rx CH2 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch2 : RO; bitpos: [7:0]; default: 7;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch2_reg_t;
+
+/** Type of in_xaddr_ch2 register
+ *  rx CH2 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch2_reg_t;
+
+/** Type of in_buf_hb_rcv_ch2 register
+ *  rx CH2 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch2 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch2:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch2_reg_t;
+
+
+/** Group: RX CH3 in_link dscr addr register */
+/** Type of in_link_addr_ch3 register
+ *  RX CH3 in_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch3 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_link_addr_ch3_reg_t;
+
+
+/** Group: RX CH3 arb register */
+/** Type of in_arb_ch3 register
+ *  RX CH3 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch3 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch3:4;
+        uint32_t reserved_4:2;
+        /** inter_in_arb_priority_ch3 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch3:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch3_reg_t;
+
+
+/** Group: RX CH3 ETM config register */
+/** Type of in_etm_conf_ch3 register
+ *  RX CH3 ETM config register
+ */
+typedef union {
+    struct {
+        /** in_etm_en_ch3 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t in_etm_en_ch3:1;
+        /** in_etm_loop_en_ch3 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t in_etm_loop_en_ch3:1;
+        /** in_dscr_task_mak_ch3 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t in_dscr_task_mak_ch3:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_etm_conf_ch3_reg_t;
+
+
+/** Group: RX CH3 debug info */
+/** Type of in_fifo_cnt_ch3 register
+ *  rx CH3 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch3 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch3:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch3_reg_t;
+
+/** Type of in_pop_data_cnt_ch3 register
+ *  rx CH3 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch3 : RO; bitpos: [7:0]; default: 7;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch3_reg_t;
+
+/** Type of in_xaddr_ch3 register
+ *  rx CH3 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch3_reg_t;
+
+/** Type of in_buf_hb_rcv_ch3 register
+ *  rx CH3 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch3 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch3:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch3_reg_t;
+
+
+/** Group: RX CH4 in_link dscr addr register */
+/** Type of in_link_addr_ch4 register
+ *  RX CH4 in_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch4 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_link_addr_ch4_reg_t;
+
+
+/** Group: RX CH4 arb register */
+/** Type of in_arb_ch4 register
+ *  RX CH4 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch4 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch4:4;
+        /** exter_in_arb_priority_ch4 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_in_arb_priority_ch4:2;
+        /** inter_in_arb_priority_ch4 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch4:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch4_reg_t;
+
+
+/** Group: RX CH4 ETM config register */
+/** Type of in_etm_conf_ch4 register
+ *  RX CH4 ETM config register
+ */
+typedef union {
+    struct {
+        /** in_etm_en_ch4 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t in_etm_en_ch4:1;
+        /** in_etm_loop_en_ch4 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t in_etm_loop_en_ch4:1;
+        /** in_dscr_task_mak_ch4 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t in_dscr_task_mak_ch4:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_etm_conf_ch4_reg_t;
+
+
+/** Group: RX CH4 debug info */
+/** Type of in_fifo_cnt_ch4 register
+ *  rx CH4 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch4 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch4:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch4_reg_t;
+
+/** Type of in_pop_data_cnt_ch4 register
+ *  rx CH4 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch4 : RO; bitpos: [7:0]; default: 7;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch4_reg_t;
+
+/** Type of in_xaddr_ch4 register
+ *  rx CH4 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch4_reg_t;
+
+/** Type of in_buf_hb_rcv_ch4 register
+ *  rx CH4 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch4 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch4:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch4_reg_t;
+
+
+/** Group: RX CH5 config1 register */
+/** Type of in_conf1_ch5 register
+ *  RX CH5 config1 register
+ */
+typedef union {
+    struct {
+        /** block_start_addr_ch5 : R/W; bitpos: [31:0]; default: 0;
+         *  RX Channel 5 destination start address
+         */
+        uint32_t block_start_addr_ch5:32;
+    };
+    uint32_t val;
+} h264_dma_in_conf1_ch5_reg_t;
+
+
+/** Group: RX CH5 config2 register */
+/** Type of in_conf2_ch5 register
+ *  RX CH5 config2 register
+ */
+typedef union {
+    struct {
+        /** block_row_length_12line_ch5 : R/W; bitpos: [15:0]; default: 30720;
+         *  The number of bytes contained in a row block 12line in RX channel 5
+         */
+        uint32_t block_row_length_12line_ch5:16;
+        /** block_row_length_4line_ch5 : R/W; bitpos: [31:16]; default: 15360;
+         *  The number of bytes contained in a row block 4line in RX channel 5
+         */
+        uint32_t block_row_length_4line_ch5:16;
+    };
+    uint32_t val;
+} h264_dma_in_conf2_ch5_reg_t;
+
+
+/** Group: RX CH5 config3 register */
+/** Type of in_conf3_ch5 register
+ *  RX CH5 config3 register
+ */
+typedef union {
+    struct {
+        /** block_length_12line_ch5 : R/W; bitpos: [13:0]; default: 256;
+         *  The number of bytes contained in a block 12line
+         */
+        uint32_t block_length_12line_ch5:14;
+        /** block_length_4line_ch5 : R/W; bitpos: [27:14]; default: 128;
+         *  The number of bytes contained in a block 4line
+         */
+        uint32_t block_length_4line_ch5:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_in_conf3_ch5_reg_t;
+
+
+/** Group: RX CH5 arb register */
+/** Type of in_arb_ch5 register
+ *  RX CH5 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch5 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch5:4;
+        uint32_t reserved_4:2;
+        /** inter_in_arb_priority_ch5 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch5:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch5_reg_t;
+
+
+/** Group: RX CH5 debug info */
+/** Type of in_fifo_cnt_ch5 register
+ *  rx CH5 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch5 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch5:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch5_reg_t;
+
+/** Type of in_pop_data_cnt_ch5 register
+ *  rx CH5 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch5 : RO; bitpos: [7:0]; default: 255;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch5:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch5_reg_t;
+
+/** Type of in_xaddr_ch5 register
+ *  rx CH5 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch5 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch5:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch5_reg_t;
+
+/** Type of in_buf_hb_rcv_ch5 register
+ *  rx CH5 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch5 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch5:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch5_reg_t;
+
+
+/** Group: inter axi err */
+/** Type of inter_axi_err register
+ *  inter memory axi err register
+ */
+typedef union {
+    struct {
+        /** inter_rid_err_cnt : RO; bitpos: [3:0]; default: 0;
+         *  AXI read id err cnt
+         */
+        uint32_t inter_rid_err_cnt:4;
+        /** inter_rresp_err_cnt : RO; bitpos: [7:4]; default: 0;
+         *  AXI read resp err cnt
+         */
+        uint32_t inter_rresp_err_cnt:4;
+        /** inter_wresp_err_cnt : RO; bitpos: [11:8]; default: 0;
+         *  AXI write resp err cnt
+         */
+        uint32_t inter_wresp_err_cnt:4;
+        /** inter_rd_fifo_cnt : RO; bitpos: [14:12]; default: 0;
+         *  AXI read cmd fifo remain cmd count
+         */
+        uint32_t inter_rd_fifo_cnt:3;
+        /** inter_rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0;
+         *  AXI read backup cmd fifo remain cmd count
+         */
+        uint32_t inter_rd_bak_fifo_cnt:4;
+        /** inter_wr_fifo_cnt : RO; bitpos: [21:19]; default: 0;
+         *  AXI write cmd fifo remain cmd count
+         */
+        uint32_t inter_wr_fifo_cnt:3;
+        /** inter_wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0;
+         *  AXI write backup cmd fifo remain cmd count
+         */
+        uint32_t inter_wr_bak_fifo_cnt:4;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} h264_dma_inter_axi_err_reg_t;
+
+
+/** Group: exter axi err */
+/** Type of exter_axi_err register
+ *  exter memory axi err register
+ */
+typedef union {
+    struct {
+        /** exter_rid_err_cnt : RO; bitpos: [3:0]; default: 0;
+         *  AXI read id err cnt
+         */
+        uint32_t exter_rid_err_cnt:4;
+        /** exter_rresp_err_cnt : RO; bitpos: [7:4]; default: 0;
+         *  AXI read resp err cnt
+         */
+        uint32_t exter_rresp_err_cnt:4;
+        /** exter_wresp_err_cnt : RO; bitpos: [11:8]; default: 0;
+         *  AXI write resp err cnt
+         */
+        uint32_t exter_wresp_err_cnt:4;
+        /** exter_rd_fifo_cnt : RO; bitpos: [14:12]; default: 0;
+         *  AXI read cmd fifo remain cmd count
+         */
+        uint32_t exter_rd_fifo_cnt:3;
+        /** exter_rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0;
+         *  AXI read backup cmd fifo remain cmd count
+         */
+        uint32_t exter_rd_bak_fifo_cnt:4;
+        /** exter_wr_fifo_cnt : RO; bitpos: [21:19]; default: 0;
+         *  AXI write cmd fifo remain cmd count
+         */
+        uint32_t exter_wr_fifo_cnt:3;
+        /** exter_wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0;
+         *  AXI write backup cmd fifo remain cmd count
+         */
+        uint32_t exter_wr_bak_fifo_cnt:4;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} h264_dma_exter_axi_err_reg_t;
+
+
+/** Group: dscr addr range register */
+/** Type of inter_mem_start_addr0 register
+ *  Start address of inter memory range0 register
+ */
+typedef union {
+    struct {
+        /** access_inter_mem_start_addr0 : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_inter_mem_start_addr0:32;
+    };
+    uint32_t val;
+} h264_dma_inter_mem_start_addr0_reg_t;
+
+/** Type of inter_mem_end_addr0 register
+ *  end address of inter memory range0 register
+ */
+typedef union {
+    struct {
+        /** access_inter_mem_end_addr0 : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_inter_mem_end_addr0:32;
+    };
+    uint32_t val;
+} h264_dma_inter_mem_end_addr0_reg_t;
+
+/** Type of inter_mem_start_addr1 register
+ *  Start address of inter memory range1 register
+ */
+typedef union {
+    struct {
+        /** access_inter_mem_start_addr1 : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_inter_mem_start_addr1:32;
+    };
+    uint32_t val;
+} h264_dma_inter_mem_start_addr1_reg_t;
+
+/** Type of inter_mem_end_addr1 register
+ *  end address of inter memory range1 register
+ */
+typedef union {
+    struct {
+        /** access_inter_mem_end_addr1 : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_inter_mem_end_addr1:32;
+    };
+    uint32_t val;
+} h264_dma_inter_mem_end_addr1_reg_t;
+
+/** Type of exter_mem_start_addr0 register
+ *  Start address of exter memory range0 register
+ */
+typedef union {
+    struct {
+        /** access_exter_mem_start_addr0 : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_exter_mem_start_addr0:32;
+    };
+    uint32_t val;
+} h264_dma_exter_mem_start_addr0_reg_t;
+
+/** Type of exter_mem_end_addr0 register
+ *  end address of exter memory range0 register
+ */
+typedef union {
+    struct {
+        /** access_exter_mem_end_addr0 : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_exter_mem_end_addr0:32;
+    };
+    uint32_t val;
+} h264_dma_exter_mem_end_addr0_reg_t;
+
+/** Type of exter_mem_start_addr1 register
+ *  Start address of exter memory range1 register
+ */
+typedef union {
+    struct {
+        /** access_exter_mem_start_addr1 : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_exter_mem_start_addr1:32;
+    };
+    uint32_t val;
+} h264_dma_exter_mem_start_addr1_reg_t;
+
+/** Type of exter_mem_end_addr1 register
+ *  end address of exter memory range1 register
+ */
+typedef union {
+    struct {
+        /** access_exter_mem_end_addr1 : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_exter_mem_end_addr1:32;
+    };
+    uint32_t val;
+} h264_dma_exter_mem_end_addr1_reg_t;
+
+
+/** Group: out arb config register */
+/** Type of out_arb_config register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t out_arb_timeout_num:16;
+        /** out_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t out_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} h264_dma_out_arb_config_reg_t;
+
+
+/** Group: in arb config register */
+/** Type of in_arb_config register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t in_arb_timeout_num:16;
+        /** in_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t in_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} h264_dma_in_arb_config_reg_t;
+
+
+/** Group: date register */
+/** Type of date register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 539165699;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} h264_dma_date_reg_t;
+
+
+/** Group: counter rst register */
+/** Type of counter_rst register
+ *  counter reset register
+ */
+typedef union {
+    struct {
+        /** rx_ch0_exter_counter_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0 to this bit to reset rx ch0 counter.
+         */
+        uint32_t rx_ch0_exter_counter_rst:1;
+        /** rx_ch1_exter_counter_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0 to this bit to reset rx ch1 counter.
+         */
+        uint32_t rx_ch1_exter_counter_rst:1;
+        /** rx_ch2_inter_counter_rst : R/W; bitpos: [2]; default: 0;
+         *  Write 1 then write 0 to this bit to reset rx ch2 counter.
+         */
+        uint32_t rx_ch2_inter_counter_rst:1;
+        /** rx_ch5_inter_counter_rst : R/W; bitpos: [3]; default: 0;
+         *  Write 1 then write 0 to this bit to reset rx ch5 counter.
+         */
+        uint32_t rx_ch5_inter_counter_rst:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_counter_rst_reg_t;
+
+
+/** Group: counter register */
+/** Type of rx_ch0_counter register
+ *  rx ch0 counter register
+ */
+typedef union {
+    struct {
+        /** rx_ch0_cnt : RO; bitpos: [22:0]; default: 0;
+         *  rx ch0 counter register
+         */
+        uint32_t rx_ch0_cnt:23;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} h264_dma_rx_ch0_counter_reg_t;
+
+/** Type of rx_ch1_counter register
+ *  rx ch1 counter register
+ */
+typedef union {
+    struct {
+        /** rx_ch1_cnt : RO; bitpos: [20:0]; default: 0;
+         *  rx ch1 counter register
+         */
+        uint32_t rx_ch1_cnt:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} h264_dma_rx_ch1_counter_reg_t;
+
+/** Type of rx_ch2_counter register
+ *  rx ch2 counter register
+ */
+typedef union {
+    struct {
+        /** rx_ch2_cnt : RO; bitpos: [10:0]; default: 0;
+         *  rx ch2 counter register
+         */
+        uint32_t rx_ch2_cnt:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_rx_ch2_counter_reg_t;
+
+/** Type of rx_ch5_counter register
+ *  rx ch5 counter register
+ */
+typedef union {
+    struct {
+        /** rx_ch5_cnt : RO; bitpos: [16:0]; default: 0;
+         *  rx ch5 counter register
+         */
+        uint32_t rx_ch5_cnt:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} h264_dma_rx_ch5_counter_reg_t;
+
+
+/** Group: pbyte register */
+/** Type of pbyte register
+ *  image pbyte register
+ */
+typedef union {
+    struct {
+        /** ori_pbyte : R/W; bitpos: [3:0]; default: 2;
+         *  configures bytes per pixel for ori img. 0: 0.5byte/pix, 1: 1byte/pix, 2:
+         *  1.5byte/pix, 3: 2byte/pix, 4: 3byte/pix
+         */
+        uint32_t ori_pbyte:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_pbyte_reg_t;
+
+
+/** Group: debug register */
+/** Type of ch_dbg_en register
+ *  channel debug enable register
+ */
+typedef union {
+    struct {
+        /** out_ch0_dbg_en : R/W; bitpos: [0]; default: 0;
+         *  configures whether to enable out channel 0 debug. 0: disable, 1: enable
+         */
+        uint32_t out_ch0_dbg_en:1;
+        /** out_ch1_dbg_en : R/W; bitpos: [1]; default: 0;
+         *  configures whether to enable out channel 1 debug. 0: disable, 1: enable
+         */
+        uint32_t out_ch1_dbg_en:1;
+        /** out_ch2_dbg_en : R/W; bitpos: [2]; default: 0;
+         *  configures whether to enable out channel 2 debug. 0: disable, 1: enable
+         */
+        uint32_t out_ch2_dbg_en:1;
+        /** out_ch3_dbg_en : R/W; bitpos: [3]; default: 0;
+         *  configures whether to enable out channel 3 debug. 0: disable, 1: enable
+         */
+        uint32_t out_ch3_dbg_en:1;
+        /** out_ch4_dbg_en : R/W; bitpos: [4]; default: 0;
+         *  configures whether to enable out channel 4 debug. 0: disable, 1: enable
+         */
+        uint32_t out_ch4_dbg_en:1;
+        uint32_t reserved_5:11;
+        /** in_ch0_dbg_en : R/W; bitpos: [16]; default: 0;
+         *  configures whether to enable in channel 0 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch0_dbg_en:1;
+        /** in_ch1_dbg_en : R/W; bitpos: [17]; default: 0;
+         *  configures whether to enable in channel 1 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch1_dbg_en:1;
+        /** in_ch2_dbg_en : R/W; bitpos: [18]; default: 0;
+         *  configures whether to enable in channel 2 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch2_dbg_en:1;
+        /** in_ch3_dbg_en : R/W; bitpos: [19]; default: 0;
+         *  configures whether to enable in channel 3 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch3_dbg_en:1;
+        /** in_ch4_dbg_en : R/W; bitpos: [20]; default: 0;
+         *  configures whether to enable in channel 4 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch4_dbg_en:1;
+        /** in_ch5_dbg_en : R/W; bitpos: [21]; default: 0;
+         *  configures whether to enable in channel 5 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch5_dbg_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} h264_dma_ch_dbg_en_reg_t;
+
+/** Type of out_ch0_dbg_data_l register
+ *  out channel 0 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch0_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 0 debug data bit 31-0
+         */
+        uint32_t out_ch0_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch0_dbg_data_l_reg_t;
+
+/** Type of out_ch0_dbg_data_h register
+ *  out channel 0 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch0_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 0 debug data bit 63-32
+         */
+        uint32_t out_ch0_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch0_dbg_data_h_reg_t;
+
+/** Type of out_ch1_dbg_data_l register
+ *  out channel 1 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch1_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 1 debug data bit 31-0
+         */
+        uint32_t out_ch1_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch1_dbg_data_l_reg_t;
+
+/** Type of out_ch1_dbg_data_h register
+ *  out channel 1 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch1_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 1 debug data bit 63-32
+         */
+        uint32_t out_ch1_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch1_dbg_data_h_reg_t;
+
+/** Type of out_ch2_dbg_data_l register
+ *  out channel 2 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch2_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 2 debug data bit 31-0
+         */
+        uint32_t out_ch2_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch2_dbg_data_l_reg_t;
+
+/** Type of out_ch2_dbg_data_h register
+ *  out channel 2 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch2_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 2 debug data bit 63-32
+         */
+        uint32_t out_ch2_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch2_dbg_data_h_reg_t;
+
+/** Type of out_ch3_dbg_data_l register
+ *  out channel 3 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch3_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 3 debug data bit 31-0
+         */
+        uint32_t out_ch3_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch3_dbg_data_l_reg_t;
+
+/** Type of out_ch3_dbg_data_h register
+ *  out channel 3 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch3_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 3 debug data bit 63-32
+         */
+        uint32_t out_ch3_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch3_dbg_data_h_reg_t;
+
+/** Type of out_ch4_dbg_data_l register
+ *  out channel 4 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch4_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 4 debug data bit 31-0
+         */
+        uint32_t out_ch4_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch4_dbg_data_l_reg_t;
+
+/** Type of out_ch4_dbg_data_h register
+ *  out channel 4 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch4_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 4 debug data bit 63-32
+         */
+        uint32_t out_ch4_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch4_dbg_data_h_reg_t;
+
+/** Type of in_ch0_dbg_data_l register
+ *  in channel 0 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch0_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 0 debug data bit 31-0
+         */
+        uint32_t in_ch0_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch0_dbg_data_l_reg_t;
+
+/** Type of in_ch0_dbg_data_h register
+ *  in channel 0 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch0_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 0 debug data bit 63-32
+         */
+        uint32_t in_ch0_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch0_dbg_data_h_reg_t;
+
+/** Type of in_ch1_dbg_data_l register
+ *  in channel 1 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch1_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 1 debug data bit 31-0
+         */
+        uint32_t in_ch1_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch1_dbg_data_l_reg_t;
+
+/** Type of in_ch1_dbg_data_h register
+ *  in channel 1 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch1_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 1 debug data bit 63-32
+         */
+        uint32_t in_ch1_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch1_dbg_data_h_reg_t;
+
+/** Type of in_ch2_dbg_data_l register
+ *  in channel 2 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch2_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 2 debug data bit 31-0
+         */
+        uint32_t in_ch2_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch2_dbg_data_l_reg_t;
+
+/** Type of in_ch2_dbg_data_h register
+ *  in channel 2 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch2_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 2 debug data bit 63-32
+         */
+        uint32_t in_ch2_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch2_dbg_data_h_reg_t;
+
+/** Type of in_ch3_dbg_data_l register
+ *  in channel 3 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch3_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 3 debug data bit 31-0
+         */
+        uint32_t in_ch3_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch3_dbg_data_l_reg_t;
+
+/** Type of in_ch3_dbg_data_h register
+ *  in channel 3 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch3_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 3 debug data bit 63-32
+         */
+        uint32_t in_ch3_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch3_dbg_data_h_reg_t;
+
+/** Type of in_ch4_dbg_data_l register
+ *  in channel 4 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch4_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 4 debug data bit 31-0
+         */
+        uint32_t in_ch4_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch4_dbg_data_l_reg_t;
+
+/** Type of in_ch4_dbg_data_h register
+ *  in channel 4 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch4_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 4 debug data bit 63-32
+         */
+        uint32_t in_ch4_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch4_dbg_data_h_reg_t;
+
+/** Type of in_ch5_dbg_data_l register
+ *  in channel 5 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch5_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 5 debug data bit 31-0
+         */
+        uint32_t in_ch5_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch5_dbg_data_l_reg_t;
+
+/** Type of in_ch5_dbg_data_h register
+ *  in channel 5 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch5_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 5 debug data bit 63-32
+         */
+        uint32_t in_ch5_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch5_dbg_data_h_reg_t;
+
+
+typedef struct {
+    volatile h264_dma_out_conf0_ch0_reg_t out_conf0_ch0;
+    volatile h264_dma_out_int_raw_ch0_reg_t out_int_raw_ch0;
+    volatile h264_dma_out_int_ena_ch0_reg_t out_int_ena_ch0;
+    volatile h264_dma_out_int_st_ch0_reg_t out_int_st_ch0;
+    volatile h264_dma_out_int_clr_ch0_reg_t out_int_clr_ch0;
+    volatile h264_dma_outfifo_status_ch0_reg_t outfifo_status_ch0;
+    volatile h264_dma_out_push_ch0_reg_t out_push_ch0;
+    volatile h264_dma_out_link_conf_ch0_reg_t out_link_conf_ch0;
+    volatile h264_dma_out_link_addr_ch0_reg_t out_link_addr_ch0;
+    volatile h264_dma_out_state_ch0_reg_t out_state_ch0;
+    volatile h264_dma_out_eof_des_addr_ch0_reg_t out_eof_des_addr_ch0;
+    volatile h264_dma_out_dscr_ch0_reg_t out_dscr_ch0;
+    volatile h264_dma_out_dscr_bf0_ch0_reg_t out_dscr_bf0_ch0;
+    volatile h264_dma_out_dscr_bf1_ch0_reg_t out_dscr_bf1_ch0;
+    uint32_t reserved_038;
+    volatile h264_dma_out_arb_ch0_reg_t out_arb_ch0;
+    volatile h264_dma_out_ro_status_ch0_reg_t out_ro_status_ch0;
+    volatile h264_dma_out_ro_pd_conf_ch0_reg_t out_ro_pd_conf_ch0;
+    uint32_t reserved_048[2];
+    volatile h264_dma_out_mode_enable_ch0_reg_t out_mode_enable_ch0;
+    volatile h264_dma_out_mode_yuv_ch0_reg_t out_mode_yuv_ch0;
+    uint32_t reserved_058[4];
+    volatile h264_dma_out_etm_conf_ch0_reg_t out_etm_conf_ch0;
+    uint32_t reserved_06c;
+    volatile h264_dma_out_buf_len_ch0_reg_t out_buf_len_ch0;
+    volatile h264_dma_out_fifo_bcnt_ch0_reg_t out_fifo_bcnt_ch0;
+    volatile h264_dma_out_push_bytecnt_ch0_reg_t out_push_bytecnt_ch0;
+    volatile h264_dma_out_xaddr_ch0_reg_t out_xaddr_ch0;
+    uint32_t reserved_080[32];
+    volatile h264_dma_out_conf0_ch1_reg_t out_conf0_ch1;
+    volatile h264_dma_out_int_raw_ch1_reg_t out_int_raw_ch1;
+    volatile h264_dma_out_int_ena_ch1_reg_t out_int_ena_ch1;
+    volatile h264_dma_out_int_st_ch1_reg_t out_int_st_ch1;
+    volatile h264_dma_out_int_clr_ch1_reg_t out_int_clr_ch1;
+    volatile h264_dma_outfifo_status_ch1_reg_t outfifo_status_ch1;
+    volatile h264_dma_out_push_ch1_reg_t out_push_ch1;
+    volatile h264_dma_out_link_conf_ch1_reg_t out_link_conf_ch1;
+    volatile h264_dma_out_link_addr_ch1_reg_t out_link_addr_ch1;
+    volatile h264_dma_out_state_ch1_reg_t out_state_ch1;
+    volatile h264_dma_out_eof_des_addr_ch1_reg_t out_eof_des_addr_ch1;
+    volatile h264_dma_out_dscr_ch1_reg_t out_dscr_ch1;
+    volatile h264_dma_out_dscr_bf0_ch1_reg_t out_dscr_bf0_ch1;
+    volatile h264_dma_out_dscr_bf1_ch1_reg_t out_dscr_bf1_ch1;
+    uint32_t reserved_138;
+    volatile h264_dma_out_arb_ch1_reg_t out_arb_ch1;
+    uint32_t reserved_140[10];
+    volatile h264_dma_out_etm_conf_ch1_reg_t out_etm_conf_ch1;
+    uint32_t reserved_16c;
+    volatile h264_dma_out_buf_len_ch1_reg_t out_buf_len_ch1;
+    volatile h264_dma_out_fifo_bcnt_ch1_reg_t out_fifo_bcnt_ch1;
+    volatile h264_dma_out_push_bytecnt_ch1_reg_t out_push_bytecnt_ch1;
+    volatile h264_dma_out_xaddr_ch1_reg_t out_xaddr_ch1;
+    uint32_t reserved_180[32];
+    volatile h264_dma_out_conf0_ch2_reg_t out_conf0_ch2;
+    volatile h264_dma_out_int_raw_ch2_reg_t out_int_raw_ch2;
+    volatile h264_dma_out_int_ena_ch2_reg_t out_int_ena_ch2;
+    volatile h264_dma_out_int_st_ch2_reg_t out_int_st_ch2;
+    volatile h264_dma_out_int_clr_ch2_reg_t out_int_clr_ch2;
+    volatile h264_dma_outfifo_status_ch2_reg_t outfifo_status_ch2;
+    volatile h264_dma_out_push_ch2_reg_t out_push_ch2;
+    volatile h264_dma_out_link_conf_ch2_reg_t out_link_conf_ch2;
+    volatile h264_dma_out_link_addr_ch2_reg_t out_link_addr_ch2;
+    volatile h264_dma_out_state_ch2_reg_t out_state_ch2;
+    volatile h264_dma_out_eof_des_addr_ch2_reg_t out_eof_des_addr_ch2;
+    volatile h264_dma_out_dscr_ch2_reg_t out_dscr_ch2;
+    volatile h264_dma_out_dscr_bf0_ch2_reg_t out_dscr_bf0_ch2;
+    volatile h264_dma_out_dscr_bf1_ch2_reg_t out_dscr_bf1_ch2;
+    uint32_t reserved_238;
+    volatile h264_dma_out_arb_ch2_reg_t out_arb_ch2;
+    uint32_t reserved_240[10];
+    volatile h264_dma_out_etm_conf_ch2_reg_t out_etm_conf_ch2;
+    uint32_t reserved_26c;
+    volatile h264_dma_out_buf_len_ch2_reg_t out_buf_len_ch2;
+    volatile h264_dma_out_fifo_bcnt_ch2_reg_t out_fifo_bcnt_ch2;
+    volatile h264_dma_out_push_bytecnt_ch2_reg_t out_push_bytecnt_ch2;
+    volatile h264_dma_out_xaddr_ch2_reg_t out_xaddr_ch2;
+    uint32_t reserved_280[32];
+    volatile h264_dma_out_conf0_ch3_reg_t out_conf0_ch3;
+    volatile h264_dma_out_int_raw_ch3_reg_t out_int_raw_ch3;
+    volatile h264_dma_out_int_ena_ch3_reg_t out_int_ena_ch3;
+    volatile h264_dma_out_int_st_ch3_reg_t out_int_st_ch3;
+    volatile h264_dma_out_int_clr_ch3_reg_t out_int_clr_ch3;
+    volatile h264_dma_outfifo_status_ch3_reg_t outfifo_status_ch3;
+    volatile h264_dma_out_push_ch3_reg_t out_push_ch3;
+    volatile h264_dma_out_link_conf_ch3_reg_t out_link_conf_ch3;
+    volatile h264_dma_out_link_addr_ch3_reg_t out_link_addr_ch3;
+    volatile h264_dma_out_state_ch3_reg_t out_state_ch3;
+    volatile h264_dma_out_eof_des_addr_ch3_reg_t out_eof_des_addr_ch3;
+    volatile h264_dma_out_dscr_ch3_reg_t out_dscr_ch3;
+    volatile h264_dma_out_dscr_bf0_ch3_reg_t out_dscr_bf0_ch3;
+    volatile h264_dma_out_dscr_bf1_ch3_reg_t out_dscr_bf1_ch3;
+    uint32_t reserved_338;
+    volatile h264_dma_out_arb_ch3_reg_t out_arb_ch3;
+    uint32_t reserved_340[10];
+    volatile h264_dma_out_etm_conf_ch3_reg_t out_etm_conf_ch3;
+    uint32_t reserved_36c;
+    volatile h264_dma_out_buf_len_ch3_reg_t out_buf_len_ch3;
+    volatile h264_dma_out_fifo_bcnt_ch3_reg_t out_fifo_bcnt_ch3;
+    volatile h264_dma_out_push_bytecnt_ch3_reg_t out_push_bytecnt_ch3;
+    volatile h264_dma_out_xaddr_ch3_reg_t out_xaddr_ch3;
+    volatile h264_dma_out_block_buf_len_ch3_reg_t out_block_buf_len_ch3;
+    uint32_t reserved_384[31];
+    volatile h264_dma_out_conf0_ch4_reg_t out_conf0_ch4;
+    volatile h264_dma_out_int_raw_ch4_reg_t out_int_raw_ch4;
+    volatile h264_dma_out_int_ena_ch4_reg_t out_int_ena_ch4;
+    volatile h264_dma_out_int_st_ch4_reg_t out_int_st_ch4;
+    volatile h264_dma_out_int_clr_ch4_reg_t out_int_clr_ch4;
+    volatile h264_dma_outfifo_status_ch4_reg_t outfifo_status_ch4;
+    volatile h264_dma_out_push_ch4_reg_t out_push_ch4;
+    volatile h264_dma_out_link_conf_ch4_reg_t out_link_conf_ch4;
+    volatile h264_dma_out_link_addr_ch4_reg_t out_link_addr_ch4;
+    volatile h264_dma_out_state_ch4_reg_t out_state_ch4;
+    volatile h264_dma_out_eof_des_addr_ch4_reg_t out_eof_des_addr_ch4;
+    volatile h264_dma_out_dscr_ch4_reg_t out_dscr_ch4;
+    volatile h264_dma_out_dscr_bf0_ch4_reg_t out_dscr_bf0_ch4;
+    volatile h264_dma_out_dscr_bf1_ch4_reg_t out_dscr_bf1_ch4;
+    uint32_t reserved_438;
+    volatile h264_dma_out_arb_ch4_reg_t out_arb_ch4;
+    uint32_t reserved_440[10];
+    volatile h264_dma_out_etm_conf_ch4_reg_t out_etm_conf_ch4;
+    uint32_t reserved_46c;
+    volatile h264_dma_out_buf_len_ch4_reg_t out_buf_len_ch4;
+    volatile h264_dma_out_fifo_bcnt_ch4_reg_t out_fifo_bcnt_ch4;
+    volatile h264_dma_out_push_bytecnt_ch4_reg_t out_push_bytecnt_ch4;
+    volatile h264_dma_out_xaddr_ch4_reg_t out_xaddr_ch4;
+    volatile h264_dma_out_block_buf_len_ch4_reg_t out_block_buf_len_ch4;
+    uint32_t reserved_484[31];
+    volatile h264_dma_in_conf0_ch0_reg_t in_conf0_ch0;
+    volatile h264_dma_in_int_raw_ch0_reg_t in_int_raw_ch0;
+    volatile h264_dma_in_int_ena_ch0_reg_t in_int_ena_ch0;
+    volatile h264_dma_in_int_st_ch0_reg_t in_int_st_ch0;
+    volatile h264_dma_in_int_clr_ch0_reg_t in_int_clr_ch0;
+    volatile h264_dma_infifo_status_ch0_reg_t infifo_status_ch0;
+    volatile h264_dma_in_pop_ch0_reg_t in_pop_ch0;
+    volatile h264_dma_in_link_conf_ch0_reg_t in_link_conf_ch0;
+    volatile h264_dma_in_link_addr_ch0_reg_t in_link_addr_ch0;
+    volatile h264_dma_in_state_ch0_reg_t in_state_ch0;
+    volatile h264_dma_in_suc_eof_des_addr_ch0_reg_t in_suc_eof_des_addr_ch0;
+    volatile h264_dma_in_err_eof_des_addr_ch0_reg_t in_err_eof_des_addr_ch0;
+    volatile h264_dma_in_dscr_ch0_reg_t in_dscr_ch0;
+    volatile h264_dma_in_dscr_bf0_ch0_reg_t in_dscr_bf0_ch0;
+    volatile h264_dma_in_dscr_bf1_ch0_reg_t in_dscr_bf1_ch0;
+    uint32_t reserved_53c;
+    volatile h264_dma_in_arb_ch0_reg_t in_arb_ch0;
+    uint32_t reserved_544;
+    volatile h264_dma_in_ro_pd_conf_ch0_reg_t in_ro_pd_conf_ch0;
+    uint32_t reserved_54c[8];
+    volatile h264_dma_in_etm_conf_ch0_reg_t in_etm_conf_ch0;
+    uint32_t reserved_570[4];
+    volatile h264_dma_in_fifo_cnt_ch0_reg_t in_fifo_cnt_ch0;
+    volatile h264_dma_in_pop_data_cnt_ch0_reg_t in_pop_data_cnt_ch0;
+    volatile h264_dma_in_xaddr_ch0_reg_t in_xaddr_ch0;
+    volatile h264_dma_in_buf_hb_rcv_ch0_reg_t in_buf_hb_rcv_ch0;
+    uint32_t reserved_590[28];
+    volatile h264_dma_in_conf0_ch1_reg_t in_conf0_ch1;
+    volatile h264_dma_in_int_raw_ch1_reg_t in_int_raw_ch1;
+    volatile h264_dma_in_int_ena_ch1_reg_t in_int_ena_ch1;
+    volatile h264_dma_in_int_st_ch1_reg_t in_int_st_ch1;
+    volatile h264_dma_in_int_clr_ch1_reg_t in_int_clr_ch1;
+    volatile h264_dma_infifo_status_ch1_reg_t infifo_status_ch1;
+    volatile h264_dma_in_pop_ch1_reg_t in_pop_ch1;
+    volatile h264_dma_in_link_conf_ch1_reg_t in_link_conf_ch1;
+    volatile h264_dma_in_link_addr_ch1_reg_t in_link_addr_ch1;
+    volatile h264_dma_in_state_ch1_reg_t in_state_ch1;
+    volatile h264_dma_in_suc_eof_des_addr_ch1_reg_t in_suc_eof_des_addr_ch1;
+    volatile h264_dma_in_err_eof_des_addr_ch1_reg_t in_err_eof_des_addr_ch1;
+    volatile h264_dma_in_dscr_ch1_reg_t in_dscr_ch1;
+    volatile h264_dma_in_dscr_bf0_ch1_reg_t in_dscr_bf0_ch1;
+    volatile h264_dma_in_dscr_bf1_ch1_reg_t in_dscr_bf1_ch1;
+    uint32_t reserved_63c;
+    volatile h264_dma_in_arb_ch1_reg_t in_arb_ch1;
+    uint32_t reserved_644;
+    volatile h264_dma_in_etm_conf_ch1_reg_t in_etm_conf_ch1;
+    uint32_t reserved_64c[13];
+    volatile h264_dma_in_fifo_cnt_ch1_reg_t in_fifo_cnt_ch1;
+    volatile h264_dma_in_pop_data_cnt_ch1_reg_t in_pop_data_cnt_ch1;
+    volatile h264_dma_in_xaddr_ch1_reg_t in_xaddr_ch1;
+    volatile h264_dma_in_buf_hb_rcv_ch1_reg_t in_buf_hb_rcv_ch1;
+    uint32_t reserved_690[28];
+    volatile h264_dma_in_conf0_ch2_reg_t in_conf0_ch2;
+    volatile h264_dma_in_int_raw_ch2_reg_t in_int_raw_ch2;
+    volatile h264_dma_in_int_ena_ch2_reg_t in_int_ena_ch2;
+    volatile h264_dma_in_int_st_ch2_reg_t in_int_st_ch2;
+    volatile h264_dma_in_int_clr_ch2_reg_t in_int_clr_ch2;
+    volatile h264_dma_infifo_status_ch2_reg_t infifo_status_ch2;
+    volatile h264_dma_in_pop_ch2_reg_t in_pop_ch2;
+    volatile h264_dma_in_link_conf_ch2_reg_t in_link_conf_ch2;
+    volatile h264_dma_in_link_addr_ch2_reg_t in_link_addr_ch2;
+    volatile h264_dma_in_state_ch2_reg_t in_state_ch2;
+    volatile h264_dma_in_suc_eof_des_addr_ch2_reg_t in_suc_eof_des_addr_ch2;
+    volatile h264_dma_in_err_eof_des_addr_ch2_reg_t in_err_eof_des_addr_ch2;
+    volatile h264_dma_in_dscr_ch2_reg_t in_dscr_ch2;
+    volatile h264_dma_in_dscr_bf0_ch2_reg_t in_dscr_bf0_ch2;
+    volatile h264_dma_in_dscr_bf1_ch2_reg_t in_dscr_bf1_ch2;
+    uint32_t reserved_73c;
+    volatile h264_dma_in_arb_ch2_reg_t in_arb_ch2;
+    uint32_t reserved_744;
+    volatile h264_dma_in_etm_conf_ch2_reg_t in_etm_conf_ch2;
+    uint32_t reserved_74c[13];
+    volatile h264_dma_in_fifo_cnt_ch2_reg_t in_fifo_cnt_ch2;
+    volatile h264_dma_in_pop_data_cnt_ch2_reg_t in_pop_data_cnt_ch2;
+    volatile h264_dma_in_xaddr_ch2_reg_t in_xaddr_ch2;
+    volatile h264_dma_in_buf_hb_rcv_ch2_reg_t in_buf_hb_rcv_ch2;
+    uint32_t reserved_790[28];
+    volatile h264_dma_in_conf0_ch3_reg_t in_conf0_ch3;
+    volatile h264_dma_in_int_raw_ch3_reg_t in_int_raw_ch3;
+    volatile h264_dma_in_int_ena_ch3_reg_t in_int_ena_ch3;
+    volatile h264_dma_in_int_st_ch3_reg_t in_int_st_ch3;
+    volatile h264_dma_in_int_clr_ch3_reg_t in_int_clr_ch3;
+    volatile h264_dma_infifo_status_ch3_reg_t infifo_status_ch3;
+    volatile h264_dma_in_pop_ch3_reg_t in_pop_ch3;
+    volatile h264_dma_in_link_conf_ch3_reg_t in_link_conf_ch3;
+    volatile h264_dma_in_link_addr_ch3_reg_t in_link_addr_ch3;
+    volatile h264_dma_in_state_ch3_reg_t in_state_ch3;
+    volatile h264_dma_in_suc_eof_des_addr_ch3_reg_t in_suc_eof_des_addr_ch3;
+    volatile h264_dma_in_err_eof_des_addr_ch3_reg_t in_err_eof_des_addr_ch3;
+    volatile h264_dma_in_dscr_ch3_reg_t in_dscr_ch3;
+    volatile h264_dma_in_dscr_bf0_ch3_reg_t in_dscr_bf0_ch3;
+    volatile h264_dma_in_dscr_bf1_ch3_reg_t in_dscr_bf1_ch3;
+    uint32_t reserved_83c;
+    volatile h264_dma_in_arb_ch3_reg_t in_arb_ch3;
+    uint32_t reserved_844;
+    volatile h264_dma_in_etm_conf_ch3_reg_t in_etm_conf_ch3;
+    uint32_t reserved_84c[13];
+    volatile h264_dma_in_fifo_cnt_ch3_reg_t in_fifo_cnt_ch3;
+    volatile h264_dma_in_pop_data_cnt_ch3_reg_t in_pop_data_cnt_ch3;
+    volatile h264_dma_in_xaddr_ch3_reg_t in_xaddr_ch3;
+    volatile h264_dma_in_buf_hb_rcv_ch3_reg_t in_buf_hb_rcv_ch3;
+    uint32_t reserved_890[28];
+    volatile h264_dma_in_conf0_ch4_reg_t in_conf0_ch4;
+    volatile h264_dma_in_int_raw_ch4_reg_t in_int_raw_ch4;
+    volatile h264_dma_in_int_ena_ch4_reg_t in_int_ena_ch4;
+    volatile h264_dma_in_int_st_ch4_reg_t in_int_st_ch4;
+    volatile h264_dma_in_int_clr_ch4_reg_t in_int_clr_ch4;
+    volatile h264_dma_infifo_status_ch4_reg_t infifo_status_ch4;
+    volatile h264_dma_in_pop_ch4_reg_t in_pop_ch4;
+    volatile h264_dma_in_link_conf_ch4_reg_t in_link_conf_ch4;
+    volatile h264_dma_in_link_addr_ch4_reg_t in_link_addr_ch4;
+    volatile h264_dma_in_state_ch4_reg_t in_state_ch4;
+    volatile h264_dma_in_suc_eof_des_addr_ch4_reg_t in_suc_eof_des_addr_ch4;
+    volatile h264_dma_in_err_eof_des_addr_ch4_reg_t in_err_eof_des_addr_ch4;
+    volatile h264_dma_in_dscr_ch4_reg_t in_dscr_ch4;
+    volatile h264_dma_in_dscr_bf0_ch4_reg_t in_dscr_bf0_ch4;
+    volatile h264_dma_in_dscr_bf1_ch4_reg_t in_dscr_bf1_ch4;
+    uint32_t reserved_93c;
+    volatile h264_dma_in_arb_ch4_reg_t in_arb_ch4;
+    uint32_t reserved_944;
+    volatile h264_dma_in_etm_conf_ch4_reg_t in_etm_conf_ch4;
+    uint32_t reserved_94c[13];
+    volatile h264_dma_in_fifo_cnt_ch4_reg_t in_fifo_cnt_ch4;
+    volatile h264_dma_in_pop_data_cnt_ch4_reg_t in_pop_data_cnt_ch4;
+    volatile h264_dma_in_xaddr_ch4_reg_t in_xaddr_ch4;
+    volatile h264_dma_in_buf_hb_rcv_ch4_reg_t in_buf_hb_rcv_ch4;
+    uint32_t reserved_990[28];
+    volatile h264_dma_in_conf0_ch5_reg_t in_conf0_ch5;
+    volatile h264_dma_in_conf1_ch5_reg_t in_conf1_ch5;
+    volatile h264_dma_in_conf2_ch5_reg_t in_conf2_ch5;
+    volatile h264_dma_in_conf3_ch5_reg_t in_conf3_ch5;
+    volatile h264_dma_in_int_raw_ch5_reg_t in_int_raw_ch5;
+    volatile h264_dma_in_int_ena_ch5_reg_t in_int_ena_ch5;
+    volatile h264_dma_in_int_st_ch5_reg_t in_int_st_ch5;
+    volatile h264_dma_in_int_clr_ch5_reg_t in_int_clr_ch5;
+    volatile h264_dma_infifo_status_ch5_reg_t infifo_status_ch5;
+    volatile h264_dma_in_pop_ch5_reg_t in_pop_ch5;
+    volatile h264_dma_in_state_ch5_reg_t in_state_ch5;
+    uint32_t reserved_a2c[5];
+    volatile h264_dma_in_arb_ch5_reg_t in_arb_ch5;
+    uint32_t reserved_a44[15];
+    volatile h264_dma_in_fifo_cnt_ch5_reg_t in_fifo_cnt_ch5;
+    volatile h264_dma_in_pop_data_cnt_ch5_reg_t in_pop_data_cnt_ch5;
+    volatile h264_dma_in_xaddr_ch5_reg_t in_xaddr_ch5;
+    volatile h264_dma_in_buf_hb_rcv_ch5_reg_t in_buf_hb_rcv_ch5;
+    uint32_t reserved_a90[28];
+    volatile h264_dma_inter_axi_err_reg_t inter_axi_err;
+    volatile h264_dma_exter_axi_err_reg_t exter_axi_err;
+    volatile h264_dma_rst_conf_reg_t rst_conf;
+    volatile h264_dma_inter_mem_start_addr0_reg_t inter_mem_start_addr0;
+    volatile h264_dma_inter_mem_end_addr0_reg_t inter_mem_end_addr0;
+    volatile h264_dma_inter_mem_start_addr1_reg_t inter_mem_start_addr1;
+    volatile h264_dma_inter_mem_end_addr1_reg_t inter_mem_end_addr1;
+    uint32_t reserved_b1c;
+    volatile h264_dma_exter_mem_start_addr0_reg_t exter_mem_start_addr0;
+    volatile h264_dma_exter_mem_end_addr0_reg_t exter_mem_end_addr0;
+    volatile h264_dma_exter_mem_start_addr1_reg_t exter_mem_start_addr1;
+    volatile h264_dma_exter_mem_end_addr1_reg_t exter_mem_end_addr1;
+    volatile h264_dma_out_arb_config_reg_t out_arb_config;
+    volatile h264_dma_in_arb_config_reg_t in_arb_config;
+    uint32_t reserved_b38;
+    volatile h264_dma_date_reg_t date;
+    uint32_t reserved_b40[4];
+    volatile h264_dma_counter_rst_reg_t counter_rst;
+    volatile h264_dma_rx_ch0_counter_reg_t rx_ch0_counter;
+    volatile h264_dma_rx_ch1_counter_reg_t rx_ch1_counter;
+    volatile h264_dma_rx_ch2_counter_reg_t rx_ch2_counter;
+    volatile h264_dma_rx_ch5_counter_reg_t rx_ch5_counter;
+    volatile h264_dma_pbyte_reg_t pbyte;
+    volatile h264_dma_ch_dbg_en_reg_t ch_dbg_en;
+    volatile h264_dma_out_ch0_dbg_data_l_reg_t out_ch0_dbg_data_l;
+    volatile h264_dma_out_ch0_dbg_data_h_reg_t out_ch0_dbg_data_h;
+    volatile h264_dma_out_ch1_dbg_data_l_reg_t out_ch1_dbg_data_l;
+    volatile h264_dma_out_ch1_dbg_data_h_reg_t out_ch1_dbg_data_h;
+    volatile h264_dma_out_ch2_dbg_data_l_reg_t out_ch2_dbg_data_l;
+    volatile h264_dma_out_ch2_dbg_data_h_reg_t out_ch2_dbg_data_h;
+    volatile h264_dma_out_ch3_dbg_data_l_reg_t out_ch3_dbg_data_l;
+    volatile h264_dma_out_ch3_dbg_data_h_reg_t out_ch3_dbg_data_h;
+    volatile h264_dma_out_ch4_dbg_data_l_reg_t out_ch4_dbg_data_l;
+    volatile h264_dma_out_ch4_dbg_data_h_reg_t out_ch4_dbg_data_h;
+    volatile h264_dma_in_ch0_dbg_data_l_reg_t in_ch0_dbg_data_l;
+    volatile h264_dma_in_ch0_dbg_data_h_reg_t in_ch0_dbg_data_h;
+    volatile h264_dma_in_ch1_dbg_data_l_reg_t in_ch1_dbg_data_l;
+    volatile h264_dma_in_ch1_dbg_data_h_reg_t in_ch1_dbg_data_h;
+    volatile h264_dma_in_ch2_dbg_data_l_reg_t in_ch2_dbg_data_l;
+    volatile h264_dma_in_ch2_dbg_data_h_reg_t in_ch2_dbg_data_h;
+    volatile h264_dma_in_ch3_dbg_data_l_reg_t in_ch3_dbg_data_l;
+    volatile h264_dma_in_ch3_dbg_data_h_reg_t in_ch3_dbg_data_h;
+    volatile h264_dma_in_ch4_dbg_data_l_reg_t in_ch4_dbg_data_l;
+    volatile h264_dma_in_ch4_dbg_data_h_reg_t in_ch4_dbg_data_h;
+    volatile h264_dma_in_ch5_dbg_data_l_reg_t in_ch5_dbg_data_l;
+    volatile h264_dma_in_ch5_dbg_data_h_reg_t in_ch5_dbg_data_h;
+} h264_dma_dev_t;
+
+extern h264_dma_dev_t H264_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(h264_dma_dev_t) == 0xbc4, "Invalid size of h264_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/h264_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/h264_reg.h
new file mode 100644
index 0000000000..9e6dbad249
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/h264_reg.h
@@ -0,0 +1,2488 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** H264_SYS_CTRL_REG register
+ *  H264 system level control register.
+ */
+#define H264_SYS_CTRL_REG (DR_REG_H264_BASE + 0x0)
+/** H264_FRAME_START : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to start encoding one frame.
+ *  0: Invalid. No effect
+ *  1: Start encoding one frame
+ */
+#define H264_FRAME_START    (BIT(0))
+#define H264_FRAME_START_M  (H264_FRAME_START_V << H264_FRAME_START_S)
+#define H264_FRAME_START_V  0x00000001U
+#define H264_FRAME_START_S  0
+/** H264_DMA_MOVE_START : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to start moving reference data from external mem.
+ *  0: Invalid. No effect
+ *  1: H264 start moving two MB lines of reference frame from external mem to internal
+ *  mem
+ */
+#define H264_DMA_MOVE_START    (BIT(1))
+#define H264_DMA_MOVE_START_M  (H264_DMA_MOVE_START_V << H264_DMA_MOVE_START_S)
+#define H264_DMA_MOVE_START_V  0x00000001U
+#define H264_DMA_MOVE_START_S  1
+/** H264_FRAME_MODE : R/W; bitpos: [2]; default: 0;
+ *  Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this
+ *  field must be set to 1 too.
+ *  0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA
+ *  1: Frame mode. Before every frame start, need reconfig reference frame DMA
+ */
+#define H264_FRAME_MODE    (BIT(2))
+#define H264_FRAME_MODE_M  (H264_FRAME_MODE_V << H264_FRAME_MODE_S)
+#define H264_FRAME_MODE_V  0x00000001U
+#define H264_FRAME_MODE_S  2
+/** H264_SYS_RST_PULSE : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to reset H264 ip.
+ *  0: Invalid. No effect
+ *  1: Reset H264 ip
+ */
+#define H264_SYS_RST_PULSE    (BIT(3))
+#define H264_SYS_RST_PULSE_M  (H264_SYS_RST_PULSE_V << H264_SYS_RST_PULSE_S)
+#define H264_SYS_RST_PULSE_V  0x00000001U
+#define H264_SYS_RST_PULSE_S  3
+
+/** H264_GOP_CONF_REG register
+ *  GOP related configuration register.
+ */
+#define H264_GOP_CONF_REG (DR_REG_H264_BASE + 0x4)
+/** H264_DUAL_STREAM_MODE : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable dual stream mode. When this field is set to 1,
+ *  H264_FRAME_MODE field must be set to 1 too.
+ *  0: Normal mode
+ *  1: Dual stream mode
+ */
+#define H264_DUAL_STREAM_MODE    (BIT(0))
+#define H264_DUAL_STREAM_MODE_M  (H264_DUAL_STREAM_MODE_V << H264_DUAL_STREAM_MODE_S)
+#define H264_DUAL_STREAM_MODE_V  0x00000001U
+#define H264_DUAL_STREAM_MODE_S  0
+/** H264_GOP_NUM : R/W; bitpos: [8:1]; default: 0;
+ *  Configures the frame number of one GOP.
+ *  0: The frame number of one GOP is infinite
+ *  Others: Actual frame number of one GOP
+ */
+#define H264_GOP_NUM    0x000000FFU
+#define H264_GOP_NUM_M  (H264_GOP_NUM_V << H264_GOP_NUM_S)
+#define H264_GOP_NUM_V  0x000000FFU
+#define H264_GOP_NUM_S  1
+
+/** H264_A_SYS_MB_RES_REG register
+ *  Video A horizontal and vertical MB resolution register.
+ */
+#define H264_A_SYS_MB_RES_REG (DR_REG_H264_BASE + 0x8)
+/** H264_A_SYS_TOTAL_MB_Y : R/W; bitpos: [6:0]; default: 0;
+ *  Configures video A vertical MB resolution.
+ */
+#define H264_A_SYS_TOTAL_MB_Y    0x0000007FU
+#define H264_A_SYS_TOTAL_MB_Y_M  (H264_A_SYS_TOTAL_MB_Y_V << H264_A_SYS_TOTAL_MB_Y_S)
+#define H264_A_SYS_TOTAL_MB_Y_V  0x0000007FU
+#define H264_A_SYS_TOTAL_MB_Y_S  0
+/** H264_A_SYS_TOTAL_MB_X : R/W; bitpos: [13:7]; default: 0;
+ *  Configures video A horizontal MB resolution.
+ */
+#define H264_A_SYS_TOTAL_MB_X    0x0000007FU
+#define H264_A_SYS_TOTAL_MB_X_M  (H264_A_SYS_TOTAL_MB_X_V << H264_A_SYS_TOTAL_MB_X_S)
+#define H264_A_SYS_TOTAL_MB_X_V  0x0000007FU
+#define H264_A_SYS_TOTAL_MB_X_S  7
+
+/** H264_A_SYS_CONF_REG register
+ *  Video A system level configuration register.
+ */
+#define H264_A_SYS_CONF_REG (DR_REG_H264_BASE + 0xc)
+/** H264_A_DB_TMP_READY_TRIGGER_MB_NUM : R/W; bitpos: [6:0]; default: 3;
+ *  Configures when to trigger  video A H264_DB_TMP_READY_INT. When the (MB number of
+ *  written db temp+1) is greater than this filed in first MB line, trigger
+ *  H264_DB_TMP_READY_INT. Min is 3.
+ */
+#define H264_A_DB_TMP_READY_TRIGGER_MB_NUM    0x0000007FU
+#define H264_A_DB_TMP_READY_TRIGGER_MB_NUM_M  (H264_A_DB_TMP_READY_TRIGGER_MB_NUM_V << H264_A_DB_TMP_READY_TRIGGER_MB_NUM_S)
+#define H264_A_DB_TMP_READY_TRIGGER_MB_NUM_V  0x0000007FU
+#define H264_A_DB_TMP_READY_TRIGGER_MB_NUM_S  0
+/** H264_A_REC_READY_TRIGGER_MB_LINES : R/W; bitpos: [13:7]; default: 4;
+ *  Configures when to trigger  video A H264_REC_READY_INT. When the MB line number of
+ *  generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT.
+ *  Min is 4.
+ */
+#define H264_A_REC_READY_TRIGGER_MB_LINES    0x0000007FU
+#define H264_A_REC_READY_TRIGGER_MB_LINES_M  (H264_A_REC_READY_TRIGGER_MB_LINES_V << H264_A_REC_READY_TRIGGER_MB_LINES_S)
+#define H264_A_REC_READY_TRIGGER_MB_LINES_V  0x0000007FU
+#define H264_A_REC_READY_TRIGGER_MB_LINES_S  7
+/** H264_A_INTRA_COST_CMP_OFFSET : R/W; bitpos: [29:14]; default: 0;
+ *  Configures video A intra cost offset when I MB compared with P MB.
+ */
+#define H264_A_INTRA_COST_CMP_OFFSET    0x0000FFFFU
+#define H264_A_INTRA_COST_CMP_OFFSET_M  (H264_A_INTRA_COST_CMP_OFFSET_V << H264_A_INTRA_COST_CMP_OFFSET_S)
+#define H264_A_INTRA_COST_CMP_OFFSET_V  0x0000FFFFU
+#define H264_A_INTRA_COST_CMP_OFFSET_S  14
+
+/** H264_A_DECI_SCORE_REG register
+ *  Video A luma and chroma MB decimate score Register.
+ */
+#define H264_A_DECI_SCORE_REG (DR_REG_H264_BASE + 0x10)
+/** H264_A_C_DECI_SCORE : R/W; bitpos: [9:0]; default: 0;
+ *  Configures video A chroma MB decimate score. When chroma score is smaller than it,
+ *  chroma decimate will be enable.
+ */
+#define H264_A_C_DECI_SCORE    0x000003FFU
+#define H264_A_C_DECI_SCORE_M  (H264_A_C_DECI_SCORE_V << H264_A_C_DECI_SCORE_S)
+#define H264_A_C_DECI_SCORE_V  0x000003FFU
+#define H264_A_C_DECI_SCORE_S  0
+/** H264_A_L_DECI_SCORE : R/W; bitpos: [19:10]; default: 0;
+ *  Configures video A luma MB decimate score. When luma score is smaller than it, luma
+ *  decimate will be enable.
+ */
+#define H264_A_L_DECI_SCORE    0x000003FFU
+#define H264_A_L_DECI_SCORE_M  (H264_A_L_DECI_SCORE_V << H264_A_L_DECI_SCORE_S)
+#define H264_A_L_DECI_SCORE_V  0x000003FFU
+#define H264_A_L_DECI_SCORE_S  10
+
+/** H264_A_DECI_SCORE_OFFSET_REG register
+ *  Video A luma and chroma MB decimate score offset Register.
+ */
+#define H264_A_DECI_SCORE_OFFSET_REG (DR_REG_H264_BASE + 0x14)
+/** H264_A_I16X16_DECI_SCORE_OFFSET : R/W; bitpos: [5:0]; default: 0;
+ *  Configures video A i16x16 MB decimate score offset. This offset will be added to
+ *  i16x16 MB score.
+ */
+#define H264_A_I16X16_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_A_I16X16_DECI_SCORE_OFFSET_M  (H264_A_I16X16_DECI_SCORE_OFFSET_V << H264_A_I16X16_DECI_SCORE_OFFSET_S)
+#define H264_A_I16X16_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_A_I16X16_DECI_SCORE_OFFSET_S  0
+/** H264_A_I_CHROMA_DECI_SCORE_OFFSET : R/W; bitpos: [11:6]; default: 0;
+ *  Configures video A I chroma MB decimate score offset. This offset will be added to
+ *  I chroma MB score.
+ */
+#define H264_A_I_CHROMA_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_A_I_CHROMA_DECI_SCORE_OFFSET_M  (H264_A_I_CHROMA_DECI_SCORE_OFFSET_V << H264_A_I_CHROMA_DECI_SCORE_OFFSET_S)
+#define H264_A_I_CHROMA_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_A_I_CHROMA_DECI_SCORE_OFFSET_S  6
+/** H264_A_P16X16_DECI_SCORE_OFFSET : R/W; bitpos: [17:12]; default: 0;
+ *  Configures video A p16x16 MB decimate score offset. This offset will be added to
+ *  p16x16 MB score.
+ */
+#define H264_A_P16X16_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_A_P16X16_DECI_SCORE_OFFSET_M  (H264_A_P16X16_DECI_SCORE_OFFSET_V << H264_A_P16X16_DECI_SCORE_OFFSET_S)
+#define H264_A_P16X16_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_A_P16X16_DECI_SCORE_OFFSET_S  12
+/** H264_A_P_CHROMA_DECI_SCORE_OFFSET : R/W; bitpos: [23:18]; default: 0;
+ *  Configures video A p chroma MB decimate score offset. This offset will be added to
+ *  p chroma MB score.
+ */
+#define H264_A_P_CHROMA_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_A_P_CHROMA_DECI_SCORE_OFFSET_M  (H264_A_P_CHROMA_DECI_SCORE_OFFSET_V << H264_A_P_CHROMA_DECI_SCORE_OFFSET_S)
+#define H264_A_P_CHROMA_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_A_P_CHROMA_DECI_SCORE_OFFSET_S  18
+
+/** H264_A_RC_CONF0_REG register
+ *  Video A rate control configuration register0.
+ */
+#define H264_A_RC_CONF0_REG (DR_REG_H264_BASE + 0x18)
+/** H264_A_QP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures video A frame level initial luma QP value.
+ */
+#define H264_A_QP    0x0000003FU
+#define H264_A_QP_M  (H264_A_QP_V << H264_A_QP_S)
+#define H264_A_QP_V  0x0000003FU
+#define H264_A_QP_S  0
+/** H264_A_RATE_CTRL_U : R/W; bitpos: [21:6]; default: 0;
+ *  Configures video A parameter U value. U = int((float) u << 8).
+ */
+#define H264_A_RATE_CTRL_U    0x0000FFFFU
+#define H264_A_RATE_CTRL_U_M  (H264_A_RATE_CTRL_U_V << H264_A_RATE_CTRL_U_S)
+#define H264_A_RATE_CTRL_U_V  0x0000FFFFU
+#define H264_A_RATE_CTRL_U_S  6
+/** H264_A_MB_RATE_CTRL_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures video A whether or not to open macro block rate ctrl.
+ *  1:Open the macro block rate ctrl
+ *  1:Close the macro block rate ctrl.
+ */
+#define H264_A_MB_RATE_CTRL_EN    (BIT(22))
+#define H264_A_MB_RATE_CTRL_EN_M  (H264_A_MB_RATE_CTRL_EN_V << H264_A_MB_RATE_CTRL_EN_S)
+#define H264_A_MB_RATE_CTRL_EN_V  0x00000001U
+#define H264_A_MB_RATE_CTRL_EN_S  22
+
+/** H264_A_RC_CONF1_REG register
+ *  Video A rate control configuration register1.
+ */
+#define H264_A_RC_CONF1_REG (DR_REG_H264_BASE + 0x1c)
+/** H264_A_CHROMA_DC_QP_DELTA : R/W; bitpos: [2:0]; default: 0;
+ *  Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma
+ *  QP(after map) + reg_chroma_dc_qp_delta.
+ */
+#define H264_A_CHROMA_DC_QP_DELTA    0x00000007U
+#define H264_A_CHROMA_DC_QP_DELTA_M  (H264_A_CHROMA_DC_QP_DELTA_V << H264_A_CHROMA_DC_QP_DELTA_S)
+#define H264_A_CHROMA_DC_QP_DELTA_V  0x00000007U
+#define H264_A_CHROMA_DC_QP_DELTA_S  0
+/** H264_A_CHROMA_QP_DELTA : R/W; bitpos: [6:3]; default: 0;
+ *  Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma
+ *  QP + reg_chroma_qp_delta.
+ */
+#define H264_A_CHROMA_QP_DELTA    0x0000000FU
+#define H264_A_CHROMA_QP_DELTA_M  (H264_A_CHROMA_QP_DELTA_V << H264_A_CHROMA_QP_DELTA_S)
+#define H264_A_CHROMA_QP_DELTA_V  0x0000000FU
+#define H264_A_CHROMA_QP_DELTA_S  3
+/** H264_A_QP_MIN : R/W; bitpos: [12:7]; default: 0;
+ *  Configures video A allowed luma QP min value.
+ */
+#define H264_A_QP_MIN    0x0000003FU
+#define H264_A_QP_MIN_M  (H264_A_QP_MIN_V << H264_A_QP_MIN_S)
+#define H264_A_QP_MIN_V  0x0000003FU
+#define H264_A_QP_MIN_S  7
+/** H264_A_QP_MAX : R/W; bitpos: [18:13]; default: 0;
+ *  Configures video A allowed luma QP max value.
+ */
+#define H264_A_QP_MAX    0x0000003FU
+#define H264_A_QP_MAX_M  (H264_A_QP_MAX_V << H264_A_QP_MAX_S)
+#define H264_A_QP_MAX_V  0x0000003FU
+#define H264_A_QP_MAX_S  13
+/** H264_A_MAD_FRAME_PRED : R/W; bitpos: [30:19]; default: 0;
+ *  Configures vdieo A frame level predicted MB MAD value.
+ */
+#define H264_A_MAD_FRAME_PRED    0x00000FFFU
+#define H264_A_MAD_FRAME_PRED_M  (H264_A_MAD_FRAME_PRED_V << H264_A_MAD_FRAME_PRED_S)
+#define H264_A_MAD_FRAME_PRED_V  0x00000FFFU
+#define H264_A_MAD_FRAME_PRED_S  19
+
+/** H264_A_DB_BYPASS_REG register
+ *  Video A Deblocking bypass register
+ */
+#define H264_A_DB_BYPASS_REG (DR_REG_H264_BASE + 0x20)
+/** H264_A_BYPASS_DB_FILTER : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to bypass video A deblcoking filter.
+ *  0: Open the deblock filter
+ *  1: Close the deblock filter
+ */
+#define H264_A_BYPASS_DB_FILTER    (BIT(0))
+#define H264_A_BYPASS_DB_FILTER_M  (H264_A_BYPASS_DB_FILTER_V << H264_A_BYPASS_DB_FILTER_S)
+#define H264_A_BYPASS_DB_FILTER_V  0x00000001U
+#define H264_A_BYPASS_DB_FILTER_S  0
+
+/** H264_A_ROI_REGION0_REG register
+ *  Video A H264 ROI region0 range configure register.
+ */
+#define H264_A_ROI_REGION0_REG (DR_REG_H264_BASE + 0x24)
+/** H264_A_ROI_REGION0_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 0 in Video A.
+ */
+#define H264_A_ROI_REGION0_X    0x0000007FU
+#define H264_A_ROI_REGION0_X_M  (H264_A_ROI_REGION0_X_V << H264_A_ROI_REGION0_X_S)
+#define H264_A_ROI_REGION0_X_V  0x0000007FU
+#define H264_A_ROI_REGION0_X_S  0
+/** H264_A_ROI_REGION0_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 0 in Video A.
+ */
+#define H264_A_ROI_REGION0_Y    0x0000007FU
+#define H264_A_ROI_REGION0_Y_M  (H264_A_ROI_REGION0_Y_V << H264_A_ROI_REGION0_Y_S)
+#define H264_A_ROI_REGION0_Y_V  0x0000007FU
+#define H264_A_ROI_REGION0_Y_S  7
+/** H264_A_ROI_REGION0_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 0 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION0_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION0_X_LEN_M  (H264_A_ROI_REGION0_X_LEN_V << H264_A_ROI_REGION0_X_LEN_S)
+#define H264_A_ROI_REGION0_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION0_X_LEN_S  14
+/** H264_A_ROI_REGION0_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 0 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION0_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION0_Y_LEN_M  (H264_A_ROI_REGION0_Y_LEN_V << H264_A_ROI_REGION0_Y_LEN_S)
+#define H264_A_ROI_REGION0_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION0_Y_LEN_S  21
+/** H264_A_ROI_REGION0_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 0 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION0_EN    (BIT(28))
+#define H264_A_ROI_REGION0_EN_M  (H264_A_ROI_REGION0_EN_V << H264_A_ROI_REGION0_EN_S)
+#define H264_A_ROI_REGION0_EN_V  0x00000001U
+#define H264_A_ROI_REGION0_EN_S  28
+
+/** H264_A_ROI_REGION1_REG register
+ *  Video A H264 ROI region1 range configure register.
+ */
+#define H264_A_ROI_REGION1_REG (DR_REG_H264_BASE + 0x28)
+/** H264_A_ROI_REGION1_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 1 in Video A.
+ */
+#define H264_A_ROI_REGION1_X    0x0000007FU
+#define H264_A_ROI_REGION1_X_M  (H264_A_ROI_REGION1_X_V << H264_A_ROI_REGION1_X_S)
+#define H264_A_ROI_REGION1_X_V  0x0000007FU
+#define H264_A_ROI_REGION1_X_S  0
+/** H264_A_ROI_REGION1_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 1 in Video A.
+ */
+#define H264_A_ROI_REGION1_Y    0x0000007FU
+#define H264_A_ROI_REGION1_Y_M  (H264_A_ROI_REGION1_Y_V << H264_A_ROI_REGION1_Y_S)
+#define H264_A_ROI_REGION1_Y_V  0x0000007FU
+#define H264_A_ROI_REGION1_Y_S  7
+/** H264_A_ROI_REGION1_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 1 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION1_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION1_X_LEN_M  (H264_A_ROI_REGION1_X_LEN_V << H264_A_ROI_REGION1_X_LEN_S)
+#define H264_A_ROI_REGION1_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION1_X_LEN_S  14
+/** H264_A_ROI_REGION1_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 1 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION1_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION1_Y_LEN_M  (H264_A_ROI_REGION1_Y_LEN_V << H264_A_ROI_REGION1_Y_LEN_S)
+#define H264_A_ROI_REGION1_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION1_Y_LEN_S  21
+/** H264_A_ROI_REGION1_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 1 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION1_EN    (BIT(28))
+#define H264_A_ROI_REGION1_EN_M  (H264_A_ROI_REGION1_EN_V << H264_A_ROI_REGION1_EN_S)
+#define H264_A_ROI_REGION1_EN_V  0x00000001U
+#define H264_A_ROI_REGION1_EN_S  28
+
+/** H264_A_ROI_REGION2_REG register
+ *  Video A H264 ROI region2 range configure register.
+ */
+#define H264_A_ROI_REGION2_REG (DR_REG_H264_BASE + 0x2c)
+/** H264_A_ROI_REGION2_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 2 in Video A.
+ */
+#define H264_A_ROI_REGION2_X    0x0000007FU
+#define H264_A_ROI_REGION2_X_M  (H264_A_ROI_REGION2_X_V << H264_A_ROI_REGION2_X_S)
+#define H264_A_ROI_REGION2_X_V  0x0000007FU
+#define H264_A_ROI_REGION2_X_S  0
+/** H264_A_ROI_REGION2_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 2 in Video A.
+ */
+#define H264_A_ROI_REGION2_Y    0x0000007FU
+#define H264_A_ROI_REGION2_Y_M  (H264_A_ROI_REGION2_Y_V << H264_A_ROI_REGION2_Y_S)
+#define H264_A_ROI_REGION2_Y_V  0x0000007FU
+#define H264_A_ROI_REGION2_Y_S  7
+/** H264_A_ROI_REGION2_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 2 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION2_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION2_X_LEN_M  (H264_A_ROI_REGION2_X_LEN_V << H264_A_ROI_REGION2_X_LEN_S)
+#define H264_A_ROI_REGION2_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION2_X_LEN_S  14
+/** H264_A_ROI_REGION2_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 2 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION2_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION2_Y_LEN_M  (H264_A_ROI_REGION2_Y_LEN_V << H264_A_ROI_REGION2_Y_LEN_S)
+#define H264_A_ROI_REGION2_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION2_Y_LEN_S  21
+/** H264_A_ROI_REGION2_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 2 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION2_EN    (BIT(28))
+#define H264_A_ROI_REGION2_EN_M  (H264_A_ROI_REGION2_EN_V << H264_A_ROI_REGION2_EN_S)
+#define H264_A_ROI_REGION2_EN_V  0x00000001U
+#define H264_A_ROI_REGION2_EN_S  28
+
+/** H264_A_ROI_REGION3_REG register
+ *  Video A H264 ROI region3 range configure register.
+ */
+#define H264_A_ROI_REGION3_REG (DR_REG_H264_BASE + 0x30)
+/** H264_A_ROI_REGION3_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 3 in Video A.
+ */
+#define H264_A_ROI_REGION3_X    0x0000007FU
+#define H264_A_ROI_REGION3_X_M  (H264_A_ROI_REGION3_X_V << H264_A_ROI_REGION3_X_S)
+#define H264_A_ROI_REGION3_X_V  0x0000007FU
+#define H264_A_ROI_REGION3_X_S  0
+/** H264_A_ROI_REGION3_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 3 in Video A.
+ */
+#define H264_A_ROI_REGION3_Y    0x0000007FU
+#define H264_A_ROI_REGION3_Y_M  (H264_A_ROI_REGION3_Y_V << H264_A_ROI_REGION3_Y_S)
+#define H264_A_ROI_REGION3_Y_V  0x0000007FU
+#define H264_A_ROI_REGION3_Y_S  7
+/** H264_A_ROI_REGION3_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 3 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION3_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION3_X_LEN_M  (H264_A_ROI_REGION3_X_LEN_V << H264_A_ROI_REGION3_X_LEN_S)
+#define H264_A_ROI_REGION3_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION3_X_LEN_S  14
+/** H264_A_ROI_REGION3_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 3 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION3_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION3_Y_LEN_M  (H264_A_ROI_REGION3_Y_LEN_V << H264_A_ROI_REGION3_Y_LEN_S)
+#define H264_A_ROI_REGION3_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION3_Y_LEN_S  21
+/** H264_A_ROI_REGION3_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 3 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION3_EN    (BIT(28))
+#define H264_A_ROI_REGION3_EN_M  (H264_A_ROI_REGION3_EN_V << H264_A_ROI_REGION3_EN_S)
+#define H264_A_ROI_REGION3_EN_V  0x00000001U
+#define H264_A_ROI_REGION3_EN_S  28
+
+/** H264_A_ROI_REGION4_REG register
+ *  Video A H264 ROI region4 range configure register.
+ */
+#define H264_A_ROI_REGION4_REG (DR_REG_H264_BASE + 0x34)
+/** H264_A_ROI_REGION4_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 4 in Video A.
+ */
+#define H264_A_ROI_REGION4_X    0x0000007FU
+#define H264_A_ROI_REGION4_X_M  (H264_A_ROI_REGION4_X_V << H264_A_ROI_REGION4_X_S)
+#define H264_A_ROI_REGION4_X_V  0x0000007FU
+#define H264_A_ROI_REGION4_X_S  0
+/** H264_A_ROI_REGION4_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 4 in Video A.
+ */
+#define H264_A_ROI_REGION4_Y    0x0000007FU
+#define H264_A_ROI_REGION4_Y_M  (H264_A_ROI_REGION4_Y_V << H264_A_ROI_REGION4_Y_S)
+#define H264_A_ROI_REGION4_Y_V  0x0000007FU
+#define H264_A_ROI_REGION4_Y_S  7
+/** H264_A_ROI_REGION4_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 4 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION4_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION4_X_LEN_M  (H264_A_ROI_REGION4_X_LEN_V << H264_A_ROI_REGION4_X_LEN_S)
+#define H264_A_ROI_REGION4_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION4_X_LEN_S  14
+/** H264_A_ROI_REGION4_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 4 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION4_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION4_Y_LEN_M  (H264_A_ROI_REGION4_Y_LEN_V << H264_A_ROI_REGION4_Y_LEN_S)
+#define H264_A_ROI_REGION4_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION4_Y_LEN_S  21
+/** H264_A_ROI_REGION4_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 4 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION4_EN    (BIT(28))
+#define H264_A_ROI_REGION4_EN_M  (H264_A_ROI_REGION4_EN_V << H264_A_ROI_REGION4_EN_S)
+#define H264_A_ROI_REGION4_EN_V  0x00000001U
+#define H264_A_ROI_REGION4_EN_S  28
+
+/** H264_A_ROI_REGION5_REG register
+ *  Video A H264 ROI region5 range configure register.
+ */
+#define H264_A_ROI_REGION5_REG (DR_REG_H264_BASE + 0x38)
+/** H264_A_ROI_REGION5_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontial start macroblocks of region 5 video A.
+ */
+#define H264_A_ROI_REGION5_X    0x0000007FU
+#define H264_A_ROI_REGION5_X_M  (H264_A_ROI_REGION5_X_V << H264_A_ROI_REGION5_X_S)
+#define H264_A_ROI_REGION5_X_V  0x0000007FU
+#define H264_A_ROI_REGION5_X_S  0
+/** H264_A_ROI_REGION5_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 5 video A.
+ */
+#define H264_A_ROI_REGION5_Y    0x0000007FU
+#define H264_A_ROI_REGION5_Y_M  (H264_A_ROI_REGION5_Y_V << H264_A_ROI_REGION5_Y_S)
+#define H264_A_ROI_REGION5_Y_V  0x0000007FU
+#define H264_A_ROI_REGION5_Y_S  7
+/** H264_A_ROI_REGION5_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 5
+ *  video A.
+ */
+#define H264_A_ROI_REGION5_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION5_X_LEN_M  (H264_A_ROI_REGION5_X_LEN_V << H264_A_ROI_REGION5_X_LEN_S)
+#define H264_A_ROI_REGION5_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION5_X_LEN_S  14
+/** H264_A_ROI_REGION5_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 5 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION5_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION5_Y_LEN_M  (H264_A_ROI_REGION5_Y_LEN_V << H264_A_ROI_REGION5_Y_LEN_S)
+#define H264_A_ROI_REGION5_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION5_Y_LEN_S  21
+/** H264_A_ROI_REGION5_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 5 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION5_EN    (BIT(28))
+#define H264_A_ROI_REGION5_EN_M  (H264_A_ROI_REGION5_EN_V << H264_A_ROI_REGION5_EN_S)
+#define H264_A_ROI_REGION5_EN_V  0x00000001U
+#define H264_A_ROI_REGION5_EN_S  28
+
+/** H264_A_ROI_REGION6_REG register
+ *  Video A H264 ROI region6 range configure register.
+ */
+#define H264_A_ROI_REGION6_REG (DR_REG_H264_BASE + 0x3c)
+/** H264_A_ROI_REGION6_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontial start macroblocks of region 6 video A.
+ */
+#define H264_A_ROI_REGION6_X    0x0000007FU
+#define H264_A_ROI_REGION6_X_M  (H264_A_ROI_REGION6_X_V << H264_A_ROI_REGION6_X_S)
+#define H264_A_ROI_REGION6_X_V  0x0000007FU
+#define H264_A_ROI_REGION6_X_S  0
+/** H264_A_ROI_REGION6_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 6 in video A.
+ */
+#define H264_A_ROI_REGION6_Y    0x0000007FU
+#define H264_A_ROI_REGION6_Y_M  (H264_A_ROI_REGION6_Y_V << H264_A_ROI_REGION6_Y_S)
+#define H264_A_ROI_REGION6_Y_V  0x0000007FU
+#define H264_A_ROI_REGION6_Y_S  7
+/** H264_A_ROI_REGION6_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 6 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION6_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION6_X_LEN_M  (H264_A_ROI_REGION6_X_LEN_V << H264_A_ROI_REGION6_X_LEN_S)
+#define H264_A_ROI_REGION6_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION6_X_LEN_S  14
+/** H264_A_ROI_REGION6_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 6 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION6_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION6_Y_LEN_M  (H264_A_ROI_REGION6_Y_LEN_V << H264_A_ROI_REGION6_Y_LEN_S)
+#define H264_A_ROI_REGION6_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION6_Y_LEN_S  21
+/** H264_A_ROI_REGION6_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 6 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION6_EN    (BIT(28))
+#define H264_A_ROI_REGION6_EN_M  (H264_A_ROI_REGION6_EN_V << H264_A_ROI_REGION6_EN_S)
+#define H264_A_ROI_REGION6_EN_V  0x00000001U
+#define H264_A_ROI_REGION6_EN_S  28
+
+/** H264_A_ROI_REGION7_REG register
+ *  Video A H264 ROI region7 range configure register.
+ */
+#define H264_A_ROI_REGION7_REG (DR_REG_H264_BASE + 0x40)
+/** H264_A_ROI_REGION7_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 7 in video A.
+ */
+#define H264_A_ROI_REGION7_X    0x0000007FU
+#define H264_A_ROI_REGION7_X_M  (H264_A_ROI_REGION7_X_V << H264_A_ROI_REGION7_X_S)
+#define H264_A_ROI_REGION7_X_V  0x0000007FU
+#define H264_A_ROI_REGION7_X_S  0
+/** H264_A_ROI_REGION7_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 7 in video A.
+ */
+#define H264_A_ROI_REGION7_Y    0x0000007FU
+#define H264_A_ROI_REGION7_Y_M  (H264_A_ROI_REGION7_Y_V << H264_A_ROI_REGION7_Y_S)
+#define H264_A_ROI_REGION7_Y_V  0x0000007FU
+#define H264_A_ROI_REGION7_Y_S  7
+/** H264_A_ROI_REGION7_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 7 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION7_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION7_X_LEN_M  (H264_A_ROI_REGION7_X_LEN_V << H264_A_ROI_REGION7_X_LEN_S)
+#define H264_A_ROI_REGION7_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION7_X_LEN_S  14
+/** H264_A_ROI_REGION7_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 7 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION7_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION7_Y_LEN_M  (H264_A_ROI_REGION7_Y_LEN_V << H264_A_ROI_REGION7_Y_LEN_S)
+#define H264_A_ROI_REGION7_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION7_Y_LEN_S  21
+/** H264_A_ROI_REGION7_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 7 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION7_EN    (BIT(28))
+#define H264_A_ROI_REGION7_EN_M  (H264_A_ROI_REGION7_EN_V << H264_A_ROI_REGION7_EN_S)
+#define H264_A_ROI_REGION7_EN_V  0x00000001U
+#define H264_A_ROI_REGION7_EN_S  28
+
+/** H264_A_ROI_REGION0_3_QP_REG register
+ *  Video A H264 ROI region0, region1,region2,region3 QP register.
+ */
+#define H264_A_ROI_REGION0_3_QP_REG (DR_REG_H264_BASE + 0x44)
+/** H264_A_ROI_REGION0_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 ROI region0 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION0_QP    0x0000007FU
+#define H264_A_ROI_REGION0_QP_M  (H264_A_ROI_REGION0_QP_V << H264_A_ROI_REGION0_QP_S)
+#define H264_A_ROI_REGION0_QP_V  0x0000007FU
+#define H264_A_ROI_REGION0_QP_S  0
+/** H264_A_ROI_REGION1_QP : R/W; bitpos: [13:7]; default: 0;
+ *  Configure H264 ROI region1 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION1_QP    0x0000007FU
+#define H264_A_ROI_REGION1_QP_M  (H264_A_ROI_REGION1_QP_V << H264_A_ROI_REGION1_QP_S)
+#define H264_A_ROI_REGION1_QP_V  0x0000007FU
+#define H264_A_ROI_REGION1_QP_S  7
+/** H264_A_ROI_REGION2_QP : R/W; bitpos: [20:14]; default: 0;
+ *  Configure H264 ROI region2 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION2_QP    0x0000007FU
+#define H264_A_ROI_REGION2_QP_M  (H264_A_ROI_REGION2_QP_V << H264_A_ROI_REGION2_QP_S)
+#define H264_A_ROI_REGION2_QP_V  0x0000007FU
+#define H264_A_ROI_REGION2_QP_S  14
+/** H264_A_ROI_REGION3_QP : R/W; bitpos: [27:21]; default: 0;
+ *  Configure H264 ROI region3 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION3_QP    0x0000007FU
+#define H264_A_ROI_REGION3_QP_M  (H264_A_ROI_REGION3_QP_V << H264_A_ROI_REGION3_QP_S)
+#define H264_A_ROI_REGION3_QP_V  0x0000007FU
+#define H264_A_ROI_REGION3_QP_S  21
+
+/** H264_A_ROI_REGION4_7_QP_REG register
+ *  Video A H264 ROI region4, region5,region6,region7 QP register.
+ */
+#define H264_A_ROI_REGION4_7_QP_REG (DR_REG_H264_BASE + 0x48)
+/** H264_A_ROI_REGION4_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 ROI region4 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION4_QP    0x0000007FU
+#define H264_A_ROI_REGION4_QP_M  (H264_A_ROI_REGION4_QP_V << H264_A_ROI_REGION4_QP_S)
+#define H264_A_ROI_REGION4_QP_V  0x0000007FU
+#define H264_A_ROI_REGION4_QP_S  0
+/** H264_A_ROI_REGION5_QP : R/W; bitpos: [13:7]; default: 0;
+ *  Configure H264 ROI region5 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION5_QP    0x0000007FU
+#define H264_A_ROI_REGION5_QP_M  (H264_A_ROI_REGION5_QP_V << H264_A_ROI_REGION5_QP_S)
+#define H264_A_ROI_REGION5_QP_V  0x0000007FU
+#define H264_A_ROI_REGION5_QP_S  7
+/** H264_A_ROI_REGION6_QP : R/W; bitpos: [20:14]; default: 0;
+ *  Configure H264 ROI region6 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION6_QP    0x0000007FU
+#define H264_A_ROI_REGION6_QP_M  (H264_A_ROI_REGION6_QP_V << H264_A_ROI_REGION6_QP_S)
+#define H264_A_ROI_REGION6_QP_V  0x0000007FU
+#define H264_A_ROI_REGION6_QP_S  14
+/** H264_A_ROI_REGION7_QP : R/W; bitpos: [27:21]; default: 0;
+ *  Configure H264 ROI region7 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION7_QP    0x0000007FU
+#define H264_A_ROI_REGION7_QP_M  (H264_A_ROI_REGION7_QP_V << H264_A_ROI_REGION7_QP_S)
+#define H264_A_ROI_REGION7_QP_V  0x0000007FU
+#define H264_A_ROI_REGION7_QP_S  21
+
+/** H264_A_NO_ROI_REGION_QP_OFFSET_REG register
+ *  Video A H264 no roi region QP register.
+ */
+#define H264_A_NO_ROI_REGION_QP_OFFSET_REG (DR_REG_H264_BASE + 0x4c)
+/** H264_A_NO_ROI_REGION_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 no region qp in video A, delta qp.
+ */
+#define H264_A_NO_ROI_REGION_QP    0x0000007FU
+#define H264_A_NO_ROI_REGION_QP_M  (H264_A_NO_ROI_REGION_QP_V << H264_A_NO_ROI_REGION_QP_S)
+#define H264_A_NO_ROI_REGION_QP_V  0x0000007FU
+#define H264_A_NO_ROI_REGION_QP_S  0
+
+/** H264_A_ROI_CONFIG_REG register
+ *  Video A H264 ROI configure register.
+ */
+#define H264_A_ROI_CONFIG_REG (DR_REG_H264_BASE + 0x50)
+/** H264_A_ROI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether or not to enable ROI in video A.
+ *  0:not enable ROI
+ *  1:enable ROI.
+ */
+#define H264_A_ROI_EN    (BIT(0))
+#define H264_A_ROI_EN_M  (H264_A_ROI_EN_V << H264_A_ROI_EN_S)
+#define H264_A_ROI_EN_V  0x00000001U
+#define H264_A_ROI_EN_S  0
+/** H264_A_ROI_MODE : R/W; bitpos: [1]; default: 0;
+ *  Configure the mode of ROI in video A.
+ *  0:fixed qp
+ *  1:delta qp.
+ */
+#define H264_A_ROI_MODE    (BIT(1))
+#define H264_A_ROI_MODE_M  (H264_A_ROI_MODE_V << H264_A_ROI_MODE_S)
+#define H264_A_ROI_MODE_V  0x00000001U
+#define H264_A_ROI_MODE_S  1
+
+/** H264_B_SYS_MB_RES_REG register
+ *  Video B horizontal and vertical MB resolution register.
+ */
+#define H264_B_SYS_MB_RES_REG (DR_REG_H264_BASE + 0x54)
+/** H264_B_SYS_TOTAL_MB_Y : R/W; bitpos: [6:0]; default: 0;
+ *  Configures video B vertical MB resolution.
+ */
+#define H264_B_SYS_TOTAL_MB_Y    0x0000007FU
+#define H264_B_SYS_TOTAL_MB_Y_M  (H264_B_SYS_TOTAL_MB_Y_V << H264_B_SYS_TOTAL_MB_Y_S)
+#define H264_B_SYS_TOTAL_MB_Y_V  0x0000007FU
+#define H264_B_SYS_TOTAL_MB_Y_S  0
+/** H264_B_SYS_TOTAL_MB_X : R/W; bitpos: [13:7]; default: 0;
+ *  Configures video B horizontal MB resolution.
+ */
+#define H264_B_SYS_TOTAL_MB_X    0x0000007FU
+#define H264_B_SYS_TOTAL_MB_X_M  (H264_B_SYS_TOTAL_MB_X_V << H264_B_SYS_TOTAL_MB_X_S)
+#define H264_B_SYS_TOTAL_MB_X_V  0x0000007FU
+#define H264_B_SYS_TOTAL_MB_X_S  7
+
+/** H264_B_SYS_CONF_REG register
+ *  Video B system level configuration register.
+ */
+#define H264_B_SYS_CONF_REG (DR_REG_H264_BASE + 0x58)
+/** H264_B_DB_TMP_READY_TRIGGER_MB_NUM : R/W; bitpos: [6:0]; default: 3;
+ *  Configures when to trigger  video B H264_DB_TMP_READY_INT. When the (MB number of
+ *  written db temp+1) is greater than this filed in first MB line, trigger
+ *  H264_DB_TMP_READY_INT. Min is 3.
+ */
+#define H264_B_DB_TMP_READY_TRIGGER_MB_NUM    0x0000007FU
+#define H264_B_DB_TMP_READY_TRIGGER_MB_NUM_M  (H264_B_DB_TMP_READY_TRIGGER_MB_NUM_V << H264_B_DB_TMP_READY_TRIGGER_MB_NUM_S)
+#define H264_B_DB_TMP_READY_TRIGGER_MB_NUM_V  0x0000007FU
+#define H264_B_DB_TMP_READY_TRIGGER_MB_NUM_S  0
+/** H264_B_REC_READY_TRIGGER_MB_LINES : R/W; bitpos: [13:7]; default: 4;
+ *  Configures when to trigger  video B H264_REC_READY_INT. When the MB line number of
+ *  generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT.
+ *  Min is 4.
+ */
+#define H264_B_REC_READY_TRIGGER_MB_LINES    0x0000007FU
+#define H264_B_REC_READY_TRIGGER_MB_LINES_M  (H264_B_REC_READY_TRIGGER_MB_LINES_V << H264_B_REC_READY_TRIGGER_MB_LINES_S)
+#define H264_B_REC_READY_TRIGGER_MB_LINES_V  0x0000007FU
+#define H264_B_REC_READY_TRIGGER_MB_LINES_S  7
+/** H264_B_INTRA_COST_CMP_OFFSET : R/W; bitpos: [29:14]; default: 0;
+ *  Configures video B intra cost offset when I MB compared with P MB.
+ */
+#define H264_B_INTRA_COST_CMP_OFFSET    0x0000FFFFU
+#define H264_B_INTRA_COST_CMP_OFFSET_M  (H264_B_INTRA_COST_CMP_OFFSET_V << H264_B_INTRA_COST_CMP_OFFSET_S)
+#define H264_B_INTRA_COST_CMP_OFFSET_V  0x0000FFFFU
+#define H264_B_INTRA_COST_CMP_OFFSET_S  14
+
+/** H264_B_DECI_SCORE_REG register
+ *  Video B luma and chroma MB decimate score Register.
+ */
+#define H264_B_DECI_SCORE_REG (DR_REG_H264_BASE + 0x5c)
+/** H264_B_C_DECI_SCORE : R/W; bitpos: [9:0]; default: 0;
+ *  Configures video B chroma MB decimate score. When chroma score is smaller than it,
+ *  chroma decimate will be enable.
+ */
+#define H264_B_C_DECI_SCORE    0x000003FFU
+#define H264_B_C_DECI_SCORE_M  (H264_B_C_DECI_SCORE_V << H264_B_C_DECI_SCORE_S)
+#define H264_B_C_DECI_SCORE_V  0x000003FFU
+#define H264_B_C_DECI_SCORE_S  0
+/** H264_B_L_DECI_SCORE : R/W; bitpos: [19:10]; default: 0;
+ *  Configures video B luma MB decimate score. When luma score is smaller than it, luma
+ *  decimate will be enable.
+ */
+#define H264_B_L_DECI_SCORE    0x000003FFU
+#define H264_B_L_DECI_SCORE_M  (H264_B_L_DECI_SCORE_V << H264_B_L_DECI_SCORE_S)
+#define H264_B_L_DECI_SCORE_V  0x000003FFU
+#define H264_B_L_DECI_SCORE_S  10
+
+/** H264_B_DECI_SCORE_OFFSET_REG register
+ *  Video B luma and chroma MB decimate score offset Register.
+ */
+#define H264_B_DECI_SCORE_OFFSET_REG (DR_REG_H264_BASE + 0x60)
+/** H264_B_I16X16_DECI_SCORE_OFFSET : R/W; bitpos: [5:0]; default: 0;
+ *  Configures video B i16x16 MB decimate score offset. This offset will be added to
+ *  i16x16 MB score.
+ */
+#define H264_B_I16X16_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_B_I16X16_DECI_SCORE_OFFSET_M  (H264_B_I16X16_DECI_SCORE_OFFSET_V << H264_B_I16X16_DECI_SCORE_OFFSET_S)
+#define H264_B_I16X16_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_B_I16X16_DECI_SCORE_OFFSET_S  0
+/** H264_B_I_CHROMA_DECI_SCORE_OFFSET : R/W; bitpos: [11:6]; default: 0;
+ *  Configures video B I chroma MB decimate score offset. This offset will be added to
+ *  I chroma MB score.
+ */
+#define H264_B_I_CHROMA_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_B_I_CHROMA_DECI_SCORE_OFFSET_M  (H264_B_I_CHROMA_DECI_SCORE_OFFSET_V << H264_B_I_CHROMA_DECI_SCORE_OFFSET_S)
+#define H264_B_I_CHROMA_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_B_I_CHROMA_DECI_SCORE_OFFSET_S  6
+/** H264_B_P16X16_DECI_SCORE_OFFSET : R/W; bitpos: [17:12]; default: 0;
+ *  Configures video B p16x16 MB decimate score offset. This offset will be added to
+ *  p16x16 MB score.
+ */
+#define H264_B_P16X16_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_B_P16X16_DECI_SCORE_OFFSET_M  (H264_B_P16X16_DECI_SCORE_OFFSET_V << H264_B_P16X16_DECI_SCORE_OFFSET_S)
+#define H264_B_P16X16_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_B_P16X16_DECI_SCORE_OFFSET_S  12
+/** H264_B_P_CHROMA_DECI_SCORE_OFFSET : R/W; bitpos: [23:18]; default: 0;
+ *  Configures video B p chroma MB decimate score offset. This offset will be added to
+ *  p chroma MB score.
+ */
+#define H264_B_P_CHROMA_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_B_P_CHROMA_DECI_SCORE_OFFSET_M  (H264_B_P_CHROMA_DECI_SCORE_OFFSET_V << H264_B_P_CHROMA_DECI_SCORE_OFFSET_S)
+#define H264_B_P_CHROMA_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_B_P_CHROMA_DECI_SCORE_OFFSET_S  18
+
+/** H264_B_RC_CONF0_REG register
+ *  Video B rate control configuration register0.
+ */
+#define H264_B_RC_CONF0_REG (DR_REG_H264_BASE + 0x64)
+/** H264_B_QP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures video B frame level initial luma QP value.
+ */
+#define H264_B_QP    0x0000003FU
+#define H264_B_QP_M  (H264_B_QP_V << H264_B_QP_S)
+#define H264_B_QP_V  0x0000003FU
+#define H264_B_QP_S  0
+/** H264_B_RATE_CTRL_U : R/W; bitpos: [21:6]; default: 0;
+ *  Configures video B parameter U value. U = int((float) u << 8).
+ */
+#define H264_B_RATE_CTRL_U    0x0000FFFFU
+#define H264_B_RATE_CTRL_U_M  (H264_B_RATE_CTRL_U_V << H264_B_RATE_CTRL_U_S)
+#define H264_B_RATE_CTRL_U_V  0x0000FFFFU
+#define H264_B_RATE_CTRL_U_S  6
+/** H264_B_MB_RATE_CTRL_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures video A whether or not to open macro block rate ctrl.
+ *  1:Open the macro block rate ctrl
+ *  1:Close the macro block rate ctrl.
+ */
+#define H264_B_MB_RATE_CTRL_EN    (BIT(22))
+#define H264_B_MB_RATE_CTRL_EN_M  (H264_B_MB_RATE_CTRL_EN_V << H264_B_MB_RATE_CTRL_EN_S)
+#define H264_B_MB_RATE_CTRL_EN_V  0x00000001U
+#define H264_B_MB_RATE_CTRL_EN_S  22
+
+/** H264_B_RC_CONF1_REG register
+ *  Video B rate control configuration register1.
+ */
+#define H264_B_RC_CONF1_REG (DR_REG_H264_BASE + 0x68)
+/** H264_B_CHROMA_DC_QP_DELTA : R/W; bitpos: [2:0]; default: 0;
+ *  Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma
+ *  QP(after map) + reg_chroma_dc_qp_delta.
+ */
+#define H264_B_CHROMA_DC_QP_DELTA    0x00000007U
+#define H264_B_CHROMA_DC_QP_DELTA_M  (H264_B_CHROMA_DC_QP_DELTA_V << H264_B_CHROMA_DC_QP_DELTA_S)
+#define H264_B_CHROMA_DC_QP_DELTA_V  0x00000007U
+#define H264_B_CHROMA_DC_QP_DELTA_S  0
+/** H264_B_CHROMA_QP_DELTA : R/W; bitpos: [6:3]; default: 0;
+ *  Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma
+ *  QP + reg_chroma_qp_delta.
+ */
+#define H264_B_CHROMA_QP_DELTA    0x0000000FU
+#define H264_B_CHROMA_QP_DELTA_M  (H264_B_CHROMA_QP_DELTA_V << H264_B_CHROMA_QP_DELTA_S)
+#define H264_B_CHROMA_QP_DELTA_V  0x0000000FU
+#define H264_B_CHROMA_QP_DELTA_S  3
+/** H264_B_QP_MIN : R/W; bitpos: [12:7]; default: 0;
+ *  Configures video B allowed luma QP min value.
+ */
+#define H264_B_QP_MIN    0x0000003FU
+#define H264_B_QP_MIN_M  (H264_B_QP_MIN_V << H264_B_QP_MIN_S)
+#define H264_B_QP_MIN_V  0x0000003FU
+#define H264_B_QP_MIN_S  7
+/** H264_B_QP_MAX : R/W; bitpos: [18:13]; default: 0;
+ *  Configures video B allowed luma QP max value.
+ */
+#define H264_B_QP_MAX    0x0000003FU
+#define H264_B_QP_MAX_M  (H264_B_QP_MAX_V << H264_B_QP_MAX_S)
+#define H264_B_QP_MAX_V  0x0000003FU
+#define H264_B_QP_MAX_S  13
+/** H264_B_MAD_FRAME_PRED : R/W; bitpos: [30:19]; default: 0;
+ *  Configures vdieo B frame level predicted MB MAD value.
+ */
+#define H264_B_MAD_FRAME_PRED    0x00000FFFU
+#define H264_B_MAD_FRAME_PRED_M  (H264_B_MAD_FRAME_PRED_V << H264_B_MAD_FRAME_PRED_S)
+#define H264_B_MAD_FRAME_PRED_V  0x00000FFFU
+#define H264_B_MAD_FRAME_PRED_S  19
+
+/** H264_B_DB_BYPASS_REG register
+ *  Video B Deblocking bypass register
+ */
+#define H264_B_DB_BYPASS_REG (DR_REG_H264_BASE + 0x6c)
+/** H264_B_BYPASS_DB_FILTER : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to bypass video B deblcoking filter.
+ *  0: Open the deblock filter
+ *  1: Close the deblock filter
+ */
+#define H264_B_BYPASS_DB_FILTER    (BIT(0))
+#define H264_B_BYPASS_DB_FILTER_M  (H264_B_BYPASS_DB_FILTER_V << H264_B_BYPASS_DB_FILTER_S)
+#define H264_B_BYPASS_DB_FILTER_V  0x00000001U
+#define H264_B_BYPASS_DB_FILTER_S  0
+
+/** H264_B_ROI_REGION0_REG register
+ *  Video B H264 ROI region0 range configure register.
+ */
+#define H264_B_ROI_REGION0_REG (DR_REG_H264_BASE + 0x70)
+/** H264_B_ROI_REGION0_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 0 in Video B.
+ */
+#define H264_B_ROI_REGION0_X    0x0000007FU
+#define H264_B_ROI_REGION0_X_M  (H264_B_ROI_REGION0_X_V << H264_B_ROI_REGION0_X_S)
+#define H264_B_ROI_REGION0_X_V  0x0000007FU
+#define H264_B_ROI_REGION0_X_S  0
+/** H264_B_ROI_REGION0_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 0 in Video B.
+ */
+#define H264_B_ROI_REGION0_Y    0x0000007FU
+#define H264_B_ROI_REGION0_Y_M  (H264_B_ROI_REGION0_Y_V << H264_B_ROI_REGION0_Y_S)
+#define H264_B_ROI_REGION0_Y_V  0x0000007FU
+#define H264_B_ROI_REGION0_Y_S  7
+/** H264_B_ROI_REGION0_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 0 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION0_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION0_X_LEN_M  (H264_B_ROI_REGION0_X_LEN_V << H264_B_ROI_REGION0_X_LEN_S)
+#define H264_B_ROI_REGION0_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION0_X_LEN_S  14
+/** H264_B_ROI_REGION0_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 0 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION0_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION0_Y_LEN_M  (H264_B_ROI_REGION0_Y_LEN_V << H264_B_ROI_REGION0_Y_LEN_S)
+#define H264_B_ROI_REGION0_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION0_Y_LEN_S  21
+/** H264_B_ROI_REGION0_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 0 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION0_EN    (BIT(28))
+#define H264_B_ROI_REGION0_EN_M  (H264_B_ROI_REGION0_EN_V << H264_B_ROI_REGION0_EN_S)
+#define H264_B_ROI_REGION0_EN_V  0x00000001U
+#define H264_B_ROI_REGION0_EN_S  28
+
+/** H264_B_ROI_REGION1_REG register
+ *  Video B H264 ROI region1 range configure register.
+ */
+#define H264_B_ROI_REGION1_REG (DR_REG_H264_BASE + 0x74)
+/** H264_B_ROI_REGION1_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 1 in Video B.
+ */
+#define H264_B_ROI_REGION1_X    0x0000007FU
+#define H264_B_ROI_REGION1_X_M  (H264_B_ROI_REGION1_X_V << H264_B_ROI_REGION1_X_S)
+#define H264_B_ROI_REGION1_X_V  0x0000007FU
+#define H264_B_ROI_REGION1_X_S  0
+/** H264_B_ROI_REGION1_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 1 in Video B.
+ */
+#define H264_B_ROI_REGION1_Y    0x0000007FU
+#define H264_B_ROI_REGION1_Y_M  (H264_B_ROI_REGION1_Y_V << H264_B_ROI_REGION1_Y_S)
+#define H264_B_ROI_REGION1_Y_V  0x0000007FU
+#define H264_B_ROI_REGION1_Y_S  7
+/** H264_B_ROI_REGION1_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 1 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION1_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION1_X_LEN_M  (H264_B_ROI_REGION1_X_LEN_V << H264_B_ROI_REGION1_X_LEN_S)
+#define H264_B_ROI_REGION1_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION1_X_LEN_S  14
+/** H264_B_ROI_REGION1_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 1 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION1_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION1_Y_LEN_M  (H264_B_ROI_REGION1_Y_LEN_V << H264_B_ROI_REGION1_Y_LEN_S)
+#define H264_B_ROI_REGION1_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION1_Y_LEN_S  21
+/** H264_B_ROI_REGION1_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 1 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION1_EN    (BIT(28))
+#define H264_B_ROI_REGION1_EN_M  (H264_B_ROI_REGION1_EN_V << H264_B_ROI_REGION1_EN_S)
+#define H264_B_ROI_REGION1_EN_V  0x00000001U
+#define H264_B_ROI_REGION1_EN_S  28
+
+/** H264_B_ROI_REGION2_REG register
+ *  Video B H264 ROI region2 range configure register.
+ */
+#define H264_B_ROI_REGION2_REG (DR_REG_H264_BASE + 0x78)
+/** H264_B_ROI_REGION2_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 2 in Video B.
+ */
+#define H264_B_ROI_REGION2_X    0x0000007FU
+#define H264_B_ROI_REGION2_X_M  (H264_B_ROI_REGION2_X_V << H264_B_ROI_REGION2_X_S)
+#define H264_B_ROI_REGION2_X_V  0x0000007FU
+#define H264_B_ROI_REGION2_X_S  0
+/** H264_B_ROI_REGION2_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 2 in Video B.
+ */
+#define H264_B_ROI_REGION2_Y    0x0000007FU
+#define H264_B_ROI_REGION2_Y_M  (H264_B_ROI_REGION2_Y_V << H264_B_ROI_REGION2_Y_S)
+#define H264_B_ROI_REGION2_Y_V  0x0000007FU
+#define H264_B_ROI_REGION2_Y_S  7
+/** H264_B_ROI_REGION2_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 2 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION2_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION2_X_LEN_M  (H264_B_ROI_REGION2_X_LEN_V << H264_B_ROI_REGION2_X_LEN_S)
+#define H264_B_ROI_REGION2_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION2_X_LEN_S  14
+/** H264_B_ROI_REGION2_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 2 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION2_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION2_Y_LEN_M  (H264_B_ROI_REGION2_Y_LEN_V << H264_B_ROI_REGION2_Y_LEN_S)
+#define H264_B_ROI_REGION2_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION2_Y_LEN_S  21
+/** H264_B_ROI_REGION2_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 2 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION2_EN    (BIT(28))
+#define H264_B_ROI_REGION2_EN_M  (H264_B_ROI_REGION2_EN_V << H264_B_ROI_REGION2_EN_S)
+#define H264_B_ROI_REGION2_EN_V  0x00000001U
+#define H264_B_ROI_REGION2_EN_S  28
+
+/** H264_B_ROI_REGION3_REG register
+ *  Video B H264 ROI region3 range configure register.
+ */
+#define H264_B_ROI_REGION3_REG (DR_REG_H264_BASE + 0x7c)
+/** H264_B_ROI_REGION3_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 3 in Video B.
+ */
+#define H264_B_ROI_REGION3_X    0x0000007FU
+#define H264_B_ROI_REGION3_X_M  (H264_B_ROI_REGION3_X_V << H264_B_ROI_REGION3_X_S)
+#define H264_B_ROI_REGION3_X_V  0x0000007FU
+#define H264_B_ROI_REGION3_X_S  0
+/** H264_B_ROI_REGION3_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 3 in Video B.
+ */
+#define H264_B_ROI_REGION3_Y    0x0000007FU
+#define H264_B_ROI_REGION3_Y_M  (H264_B_ROI_REGION3_Y_V << H264_B_ROI_REGION3_Y_S)
+#define H264_B_ROI_REGION3_Y_V  0x0000007FU
+#define H264_B_ROI_REGION3_Y_S  7
+/** H264_B_ROI_REGION3_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 3 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION3_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION3_X_LEN_M  (H264_B_ROI_REGION3_X_LEN_V << H264_B_ROI_REGION3_X_LEN_S)
+#define H264_B_ROI_REGION3_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION3_X_LEN_S  14
+/** H264_B_ROI_REGION3_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 3 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION3_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION3_Y_LEN_M  (H264_B_ROI_REGION3_Y_LEN_V << H264_B_ROI_REGION3_Y_LEN_S)
+#define H264_B_ROI_REGION3_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION3_Y_LEN_S  21
+/** H264_B_ROI_REGION3_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 3 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION3_EN    (BIT(28))
+#define H264_B_ROI_REGION3_EN_M  (H264_B_ROI_REGION3_EN_V << H264_B_ROI_REGION3_EN_S)
+#define H264_B_ROI_REGION3_EN_V  0x00000001U
+#define H264_B_ROI_REGION3_EN_S  28
+
+/** H264_B_ROI_REGION4_REG register
+ *  Video B H264 ROI region4 range configure register.
+ */
+#define H264_B_ROI_REGION4_REG (DR_REG_H264_BASE + 0x80)
+/** H264_B_ROI_REGION4_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 4 in Video B.
+ */
+#define H264_B_ROI_REGION4_X    0x0000007FU
+#define H264_B_ROI_REGION4_X_M  (H264_B_ROI_REGION4_X_V << H264_B_ROI_REGION4_X_S)
+#define H264_B_ROI_REGION4_X_V  0x0000007FU
+#define H264_B_ROI_REGION4_X_S  0
+/** H264_B_ROI_REGION4_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 4 in Video B.
+ */
+#define H264_B_ROI_REGION4_Y    0x0000007FU
+#define H264_B_ROI_REGION4_Y_M  (H264_B_ROI_REGION4_Y_V << H264_B_ROI_REGION4_Y_S)
+#define H264_B_ROI_REGION4_Y_V  0x0000007FU
+#define H264_B_ROI_REGION4_Y_S  7
+/** H264_B_ROI_REGION4_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 4 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION4_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION4_X_LEN_M  (H264_B_ROI_REGION4_X_LEN_V << H264_B_ROI_REGION4_X_LEN_S)
+#define H264_B_ROI_REGION4_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION4_X_LEN_S  14
+/** H264_B_ROI_REGION4_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 4 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION4_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION4_Y_LEN_M  (H264_B_ROI_REGION4_Y_LEN_V << H264_B_ROI_REGION4_Y_LEN_S)
+#define H264_B_ROI_REGION4_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION4_Y_LEN_S  21
+/** H264_B_ROI_REGION4_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 4 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION4_EN    (BIT(28))
+#define H264_B_ROI_REGION4_EN_M  (H264_B_ROI_REGION4_EN_V << H264_B_ROI_REGION4_EN_S)
+#define H264_B_ROI_REGION4_EN_V  0x00000001U
+#define H264_B_ROI_REGION4_EN_S  28
+
+/** H264_B_ROI_REGION5_REG register
+ *  Video B H264 ROI region5 range configure register.
+ */
+#define H264_B_ROI_REGION5_REG (DR_REG_H264_BASE + 0x84)
+/** H264_B_ROI_REGION5_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontial start macroblocks of region 5 video B.
+ */
+#define H264_B_ROI_REGION5_X    0x0000007FU
+#define H264_B_ROI_REGION5_X_M  (H264_B_ROI_REGION5_X_V << H264_B_ROI_REGION5_X_S)
+#define H264_B_ROI_REGION5_X_V  0x0000007FU
+#define H264_B_ROI_REGION5_X_S  0
+/** H264_B_ROI_REGION5_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 5 video B.
+ */
+#define H264_B_ROI_REGION5_Y    0x0000007FU
+#define H264_B_ROI_REGION5_Y_M  (H264_B_ROI_REGION5_Y_V << H264_B_ROI_REGION5_Y_S)
+#define H264_B_ROI_REGION5_Y_V  0x0000007FU
+#define H264_B_ROI_REGION5_Y_S  7
+/** H264_B_ROI_REGION5_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 5
+ *  video B.
+ */
+#define H264_B_ROI_REGION5_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION5_X_LEN_M  (H264_B_ROI_REGION5_X_LEN_V << H264_B_ROI_REGION5_X_LEN_S)
+#define H264_B_ROI_REGION5_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION5_X_LEN_S  14
+/** H264_B_ROI_REGION5_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 5 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION5_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION5_Y_LEN_M  (H264_B_ROI_REGION5_Y_LEN_V << H264_B_ROI_REGION5_Y_LEN_S)
+#define H264_B_ROI_REGION5_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION5_Y_LEN_S  21
+/** H264_B_ROI_REGION5_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 5 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION5_EN    (BIT(28))
+#define H264_B_ROI_REGION5_EN_M  (H264_B_ROI_REGION5_EN_V << H264_B_ROI_REGION5_EN_S)
+#define H264_B_ROI_REGION5_EN_V  0x00000001U
+#define H264_B_ROI_REGION5_EN_S  28
+
+/** H264_B_ROI_REGION6_REG register
+ *  Video B H264 ROI region6 range configure register.
+ */
+#define H264_B_ROI_REGION6_REG (DR_REG_H264_BASE + 0x88)
+/** H264_B_ROI_REGION6_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontial start macroblocks of region 6 video B.
+ */
+#define H264_B_ROI_REGION6_X    0x0000007FU
+#define H264_B_ROI_REGION6_X_M  (H264_B_ROI_REGION6_X_V << H264_B_ROI_REGION6_X_S)
+#define H264_B_ROI_REGION6_X_V  0x0000007FU
+#define H264_B_ROI_REGION6_X_S  0
+/** H264_B_ROI_REGION6_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 6 in video B.
+ */
+#define H264_B_ROI_REGION6_Y    0x0000007FU
+#define H264_B_ROI_REGION6_Y_M  (H264_B_ROI_REGION6_Y_V << H264_B_ROI_REGION6_Y_S)
+#define H264_B_ROI_REGION6_Y_V  0x0000007FU
+#define H264_B_ROI_REGION6_Y_S  7
+/** H264_B_ROI_REGION6_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 6 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION6_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION6_X_LEN_M  (H264_B_ROI_REGION6_X_LEN_V << H264_B_ROI_REGION6_X_LEN_S)
+#define H264_B_ROI_REGION6_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION6_X_LEN_S  14
+/** H264_B_ROI_REGION6_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 6 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION6_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION6_Y_LEN_M  (H264_B_ROI_REGION6_Y_LEN_V << H264_B_ROI_REGION6_Y_LEN_S)
+#define H264_B_ROI_REGION6_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION6_Y_LEN_S  21
+/** H264_B_ROI_REGION6_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 6 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION6_EN    (BIT(28))
+#define H264_B_ROI_REGION6_EN_M  (H264_B_ROI_REGION6_EN_V << H264_B_ROI_REGION6_EN_S)
+#define H264_B_ROI_REGION6_EN_V  0x00000001U
+#define H264_B_ROI_REGION6_EN_S  28
+
+/** H264_B_ROI_REGION7_REG register
+ *  Video B H264 ROI region7 range configure register.
+ */
+#define H264_B_ROI_REGION7_REG (DR_REG_H264_BASE + 0x8c)
+/** H264_B_ROI_REGION7_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 7 in video B.
+ */
+#define H264_B_ROI_REGION7_X    0x0000007FU
+#define H264_B_ROI_REGION7_X_M  (H264_B_ROI_REGION7_X_V << H264_B_ROI_REGION7_X_S)
+#define H264_B_ROI_REGION7_X_V  0x0000007FU
+#define H264_B_ROI_REGION7_X_S  0
+/** H264_B_ROI_REGION7_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 7 in video B.
+ */
+#define H264_B_ROI_REGION7_Y    0x0000007FU
+#define H264_B_ROI_REGION7_Y_M  (H264_B_ROI_REGION7_Y_V << H264_B_ROI_REGION7_Y_S)
+#define H264_B_ROI_REGION7_Y_V  0x0000007FU
+#define H264_B_ROI_REGION7_Y_S  7
+/** H264_B_ROI_REGION7_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 7 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION7_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION7_X_LEN_M  (H264_B_ROI_REGION7_X_LEN_V << H264_B_ROI_REGION7_X_LEN_S)
+#define H264_B_ROI_REGION7_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION7_X_LEN_S  14
+/** H264_B_ROI_REGION7_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 7 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION7_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION7_Y_LEN_M  (H264_B_ROI_REGION7_Y_LEN_V << H264_B_ROI_REGION7_Y_LEN_S)
+#define H264_B_ROI_REGION7_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION7_Y_LEN_S  21
+/** H264_B_ROI_REGION7_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 7 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION7_EN    (BIT(28))
+#define H264_B_ROI_REGION7_EN_M  (H264_B_ROI_REGION7_EN_V << H264_B_ROI_REGION7_EN_S)
+#define H264_B_ROI_REGION7_EN_V  0x00000001U
+#define H264_B_ROI_REGION7_EN_S  28
+
+/** H264_B_ROI_REGION0_3_QP_REG register
+ *  Video B H264 ROI region0, region1,region2,region3 QP register.
+ */
+#define H264_B_ROI_REGION0_3_QP_REG (DR_REG_H264_BASE + 0x90)
+/** H264_B_ROI_REGION0_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 ROI region0 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION0_QP    0x0000007FU
+#define H264_B_ROI_REGION0_QP_M  (H264_B_ROI_REGION0_QP_V << H264_B_ROI_REGION0_QP_S)
+#define H264_B_ROI_REGION0_QP_V  0x0000007FU
+#define H264_B_ROI_REGION0_QP_S  0
+/** H264_B_ROI_REGION1_QP : R/W; bitpos: [13:7]; default: 0;
+ *  Configure H264 ROI region1 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION1_QP    0x0000007FU
+#define H264_B_ROI_REGION1_QP_M  (H264_B_ROI_REGION1_QP_V << H264_B_ROI_REGION1_QP_S)
+#define H264_B_ROI_REGION1_QP_V  0x0000007FU
+#define H264_B_ROI_REGION1_QP_S  7
+/** H264_B_ROI_REGION2_QP : R/W; bitpos: [20:14]; default: 0;
+ *  Configure H264 ROI region2 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION2_QP    0x0000007FU
+#define H264_B_ROI_REGION2_QP_M  (H264_B_ROI_REGION2_QP_V << H264_B_ROI_REGION2_QP_S)
+#define H264_B_ROI_REGION2_QP_V  0x0000007FU
+#define H264_B_ROI_REGION2_QP_S  14
+/** H264_B_ROI_REGION3_QP : R/W; bitpos: [27:21]; default: 0;
+ *  Configure H264 ROI region3 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION3_QP    0x0000007FU
+#define H264_B_ROI_REGION3_QP_M  (H264_B_ROI_REGION3_QP_V << H264_B_ROI_REGION3_QP_S)
+#define H264_B_ROI_REGION3_QP_V  0x0000007FU
+#define H264_B_ROI_REGION3_QP_S  21
+
+/** H264_B_ROI_REGION4_7_QP_REG register
+ *  Video B H264 ROI region4, region5,region6,region7 QP register.
+ */
+#define H264_B_ROI_REGION4_7_QP_REG (DR_REG_H264_BASE + 0x94)
+/** H264_B_ROI_REGION4_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 ROI region4 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION4_QP    0x0000007FU
+#define H264_B_ROI_REGION4_QP_M  (H264_B_ROI_REGION4_QP_V << H264_B_ROI_REGION4_QP_S)
+#define H264_B_ROI_REGION4_QP_V  0x0000007FU
+#define H264_B_ROI_REGION4_QP_S  0
+/** H264_B_ROI_REGION5_QP : R/W; bitpos: [13:7]; default: 0;
+ *  Configure H264 ROI region5 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION5_QP    0x0000007FU
+#define H264_B_ROI_REGION5_QP_M  (H264_B_ROI_REGION5_QP_V << H264_B_ROI_REGION5_QP_S)
+#define H264_B_ROI_REGION5_QP_V  0x0000007FU
+#define H264_B_ROI_REGION5_QP_S  7
+/** H264_B_ROI_REGION6_QP : R/W; bitpos: [20:14]; default: 0;
+ *  Configure H264 ROI region6 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION6_QP    0x0000007FU
+#define H264_B_ROI_REGION6_QP_M  (H264_B_ROI_REGION6_QP_V << H264_B_ROI_REGION6_QP_S)
+#define H264_B_ROI_REGION6_QP_V  0x0000007FU
+#define H264_B_ROI_REGION6_QP_S  14
+/** H264_B_ROI_REGION7_QP : R/W; bitpos: [27:21]; default: 0;
+ *  Configure H264 ROI region7 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION7_QP    0x0000007FU
+#define H264_B_ROI_REGION7_QP_M  (H264_B_ROI_REGION7_QP_V << H264_B_ROI_REGION7_QP_S)
+#define H264_B_ROI_REGION7_QP_V  0x0000007FU
+#define H264_B_ROI_REGION7_QP_S  21
+
+/** H264_B_NO_ROI_REGION_QP_OFFSET_REG register
+ *  Video B H264 no roi region QP register.
+ */
+#define H264_B_NO_ROI_REGION_QP_OFFSET_REG (DR_REG_H264_BASE + 0x98)
+/** H264_B_NO_ROI_REGION_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 no region qp in video B, delta qp.
+ */
+#define H264_B_NO_ROI_REGION_QP    0x0000007FU
+#define H264_B_NO_ROI_REGION_QP_M  (H264_B_NO_ROI_REGION_QP_V << H264_B_NO_ROI_REGION_QP_S)
+#define H264_B_NO_ROI_REGION_QP_V  0x0000007FU
+#define H264_B_NO_ROI_REGION_QP_S  0
+
+/** H264_B_ROI_CONFIG_REG register
+ *  Video B H264 ROI configure register.
+ */
+#define H264_B_ROI_CONFIG_REG (DR_REG_H264_BASE + 0x9c)
+/** H264_B_ROI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether or not to enable ROI in video B.
+ *  0:not enable ROI
+ *  1:enable ROI.
+ */
+#define H264_B_ROI_EN    (BIT(0))
+#define H264_B_ROI_EN_M  (H264_B_ROI_EN_V << H264_B_ROI_EN_S)
+#define H264_B_ROI_EN_V  0x00000001U
+#define H264_B_ROI_EN_S  0
+/** H264_B_ROI_MODE : R/W; bitpos: [1]; default: 0;
+ *  Configure the mode of ROI in video B.
+ *  0:fixed qp
+ *  1:delta qp.
+ */
+#define H264_B_ROI_MODE    (BIT(1))
+#define H264_B_ROI_MODE_M  (H264_B_ROI_MODE_V << H264_B_ROI_MODE_S)
+#define H264_B_ROI_MODE_V  0x00000001U
+#define H264_B_ROI_MODE_S  1
+
+/** H264_RC_STATUS0_REG register
+ *  Rate control status register0.
+ */
+#define H264_RC_STATUS0_REG (DR_REG_H264_BASE + 0xa0)
+/** H264_FRAME_MAD_SUM : RO; bitpos: [20:0]; default: 0;
+ *  Represents all MB actual MAD sum value of one frame.
+ */
+#define H264_FRAME_MAD_SUM    0x001FFFFFU
+#define H264_FRAME_MAD_SUM_M  (H264_FRAME_MAD_SUM_V << H264_FRAME_MAD_SUM_S)
+#define H264_FRAME_MAD_SUM_V  0x001FFFFFU
+#define H264_FRAME_MAD_SUM_S  0
+
+/** H264_RC_STATUS1_REG register
+ *  Rate control status register1.
+ */
+#define H264_RC_STATUS1_REG (DR_REG_H264_BASE + 0xa4)
+/** H264_FRAME_ENC_BITS : RO; bitpos: [26:0]; default: 0;
+ *  Represents all MB actual encoding bits sum value of one frame.
+ */
+#define H264_FRAME_ENC_BITS    0x07FFFFFFU
+#define H264_FRAME_ENC_BITS_M  (H264_FRAME_ENC_BITS_V << H264_FRAME_ENC_BITS_S)
+#define H264_FRAME_ENC_BITS_V  0x07FFFFFFU
+#define H264_FRAME_ENC_BITS_S  0
+
+/** H264_RC_STATUS2_REG register
+ *  Rate control status register2.
+ */
+#define H264_RC_STATUS2_REG (DR_REG_H264_BASE + 0xa8)
+/** H264_FRAME_QP_SUM : RO; bitpos: [18:0]; default: 0;
+ *  Represents all MB actual luma QP sum value of one frame.
+ */
+#define H264_FRAME_QP_SUM    0x0007FFFFU
+#define H264_FRAME_QP_SUM_M  (H264_FRAME_QP_SUM_V << H264_FRAME_QP_SUM_S)
+#define H264_FRAME_QP_SUM_V  0x0007FFFFU
+#define H264_FRAME_QP_SUM_S  0
+
+/** H264_SLICE_HEADER_REMAIN_REG register
+ *  Frame Slice Header remain bit register.
+ */
+#define H264_SLICE_HEADER_REMAIN_REG (DR_REG_H264_BASE + 0xac)
+/** H264_SLICE_REMAIN_BITLENGTH : R/W; bitpos: [2:0]; default: 0;
+ *  Configures Slice Header remain bit number
+ */
+#define H264_SLICE_REMAIN_BITLENGTH    0x00000007U
+#define H264_SLICE_REMAIN_BITLENGTH_M  (H264_SLICE_REMAIN_BITLENGTH_V << H264_SLICE_REMAIN_BITLENGTH_S)
+#define H264_SLICE_REMAIN_BITLENGTH_V  0x00000007U
+#define H264_SLICE_REMAIN_BITLENGTH_S  0
+/** H264_SLICE_REMAIN_BIT : R/W; bitpos: [10:3]; default: 0;
+ *  Configures Slice Header remain bit
+ */
+#define H264_SLICE_REMAIN_BIT    0x000000FFU
+#define H264_SLICE_REMAIN_BIT_M  (H264_SLICE_REMAIN_BIT_V << H264_SLICE_REMAIN_BIT_S)
+#define H264_SLICE_REMAIN_BIT_V  0x000000FFU
+#define H264_SLICE_REMAIN_BIT_S  3
+
+/** H264_SLICE_HEADER_BYTE_LENGTH_REG register
+ *  Frame Slice Header byte length register.
+ */
+#define H264_SLICE_HEADER_BYTE_LENGTH_REG (DR_REG_H264_BASE + 0xb0)
+/** H264_SLICE_BYTE_LENGTH : R/W; bitpos: [3:0]; default: 0;
+ *  Configures Slice Header byte number
+ */
+#define H264_SLICE_BYTE_LENGTH    0x0000000FU
+#define H264_SLICE_BYTE_LENGTH_M  (H264_SLICE_BYTE_LENGTH_V << H264_SLICE_BYTE_LENGTH_S)
+#define H264_SLICE_BYTE_LENGTH_V  0x0000000FU
+#define H264_SLICE_BYTE_LENGTH_S  0
+
+/** H264_BS_THRESHOLD_REG register
+ *  Bitstream buffer overflow threshold register
+ */
+#define H264_BS_THRESHOLD_REG (DR_REG_H264_BASE + 0xb4)
+/** H264_BS_BUFFER_THRESHOLD : R/W; bitpos: [6:0]; default: 48;
+ *  Configures bitstream buffer overflow threshold. This value should be bigger than
+ *  the encode bytes of one 4x4 submb.
+ */
+#define H264_BS_BUFFER_THRESHOLD    0x0000007FU
+#define H264_BS_BUFFER_THRESHOLD_M  (H264_BS_BUFFER_THRESHOLD_V << H264_BS_BUFFER_THRESHOLD_S)
+#define H264_BS_BUFFER_THRESHOLD_V  0x0000007FU
+#define H264_BS_BUFFER_THRESHOLD_S  0
+
+/** H264_SLICE_HEADER_BYTE0_REG register
+ *  Frame Slice Header byte low 32 bit  register.
+ */
+#define H264_SLICE_HEADER_BYTE0_REG (DR_REG_H264_BASE + 0xb8)
+/** H264_SLICE_BYTE_LSB : R/W; bitpos: [31:0]; default: 0;
+ *  Configures Slice Header low 32 bit
+ */
+#define H264_SLICE_BYTE_LSB    0xFFFFFFFFU
+#define H264_SLICE_BYTE_LSB_M  (H264_SLICE_BYTE_LSB_V << H264_SLICE_BYTE_LSB_S)
+#define H264_SLICE_BYTE_LSB_V  0xFFFFFFFFU
+#define H264_SLICE_BYTE_LSB_S  0
+
+/** H264_SLICE_HEADER_BYTE1_REG register
+ *  Frame Slice Header byte high 32 bit  register.
+ */
+#define H264_SLICE_HEADER_BYTE1_REG (DR_REG_H264_BASE + 0xbc)
+/** H264_SLICE_BYTE_MSB : R/W; bitpos: [31:0]; default: 0;
+ *  Configures Slice Header high 32 bit
+ */
+#define H264_SLICE_BYTE_MSB    0xFFFFFFFFU
+#define H264_SLICE_BYTE_MSB_M  (H264_SLICE_BYTE_MSB_V << H264_SLICE_BYTE_MSB_S)
+#define H264_SLICE_BYTE_MSB_V  0xFFFFFFFFU
+#define H264_SLICE_BYTE_MSB_S  0
+
+/** H264_INT_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define H264_INT_RAW_REG (DR_REG_H264_BASE + 0xc0)
+/** H264_DB_TMP_READY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Raw status bit: The raw interrupt status of  H264_DB_TMP_READY_INT. Triggered when
+ *  H264 written enough db tmp pixel.
+ */
+#define H264_DB_TMP_READY_INT_RAW    (BIT(0))
+#define H264_DB_TMP_READY_INT_RAW_M  (H264_DB_TMP_READY_INT_RAW_V << H264_DB_TMP_READY_INT_RAW_S)
+#define H264_DB_TMP_READY_INT_RAW_V  0x00000001U
+#define H264_DB_TMP_READY_INT_RAW_S  0
+/** H264_REC_READY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Raw status bit: The raw interrupt status of  H264_REC_READY_INT. Triggered when
+ *  H264 encoding enough reconstruct pixel.
+ */
+#define H264_REC_READY_INT_RAW    (BIT(1))
+#define H264_REC_READY_INT_RAW_M  (H264_REC_READY_INT_RAW_V << H264_REC_READY_INT_RAW_S)
+#define H264_REC_READY_INT_RAW_V  0x00000001U
+#define H264_REC_READY_INT_RAW_S  1
+/** H264_FRAME_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Raw status bit: The raw interrupt status of  H264_FRAME_DONE_INT. Triggered when
+ *  H264 encoding one frame done.
+ */
+#define H264_FRAME_DONE_INT_RAW    (BIT(2))
+#define H264_FRAME_DONE_INT_RAW_M  (H264_FRAME_DONE_INT_RAW_V << H264_FRAME_DONE_INT_RAW_S)
+#define H264_FRAME_DONE_INT_RAW_V  0x00000001U
+#define H264_FRAME_DONE_INT_RAW_S  2
+/** H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT.
+ *  Triggered when H264 move two MB lines of reference frame from external mem to
+ *  internal mem done.
+ */
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW    (BIT(3))
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW_M  (H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW_V << H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW_S)
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW_V  0x00000001U
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW_S  3
+/** H264_BS_BUFFER_OVERFLOW_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Raw status bit: The raw interrupt status of H264_BS_BUFFER_OVERFLOW_INT. Triggered
+ *  when H264 bit stream buffer overflow.
+ */
+#define H264_BS_BUFFER_OVERFLOW_INT_RAW    (BIT(4))
+#define H264_BS_BUFFER_OVERFLOW_INT_RAW_M  (H264_BS_BUFFER_OVERFLOW_INT_RAW_V << H264_BS_BUFFER_OVERFLOW_INT_RAW_S)
+#define H264_BS_BUFFER_OVERFLOW_INT_RAW_V  0x00000001U
+#define H264_BS_BUFFER_OVERFLOW_INT_RAW_S  4
+
+/** H264_INT_ST_REG register
+ *  Interrupt masked status register
+ */
+#define H264_INT_ST_REG (DR_REG_H264_BASE + 0xc4)
+/** H264_DB_TMP_READY_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Masked status bit: The masked interrupt status of H264_DB_TMP_READY_INT. Valid only
+ *  when the H264_DB_TMP_READY_INT_ENA is set to 1.
+ */
+#define H264_DB_TMP_READY_INT_ST    (BIT(0))
+#define H264_DB_TMP_READY_INT_ST_M  (H264_DB_TMP_READY_INT_ST_V << H264_DB_TMP_READY_INT_ST_S)
+#define H264_DB_TMP_READY_INT_ST_V  0x00000001U
+#define H264_DB_TMP_READY_INT_ST_S  0
+/** H264_REC_READY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Masked status bit: The masked interrupt status of H264_REC_READY_INT. Valid only
+ *  when the H264_REC_READY_INT_ENA is set to 1.
+ */
+#define H264_REC_READY_INT_ST    (BIT(1))
+#define H264_REC_READY_INT_ST_M  (H264_REC_READY_INT_ST_V << H264_REC_READY_INT_ST_S)
+#define H264_REC_READY_INT_ST_V  0x00000001U
+#define H264_REC_READY_INT_ST_S  1
+/** H264_FRAME_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Masked status bit: The masked interrupt status of H264_FRAME_DONE_INT. Valid only
+ *  when the H264_FRAME_DONE_INT_ENA is set to 1.
+ */
+#define H264_FRAME_DONE_INT_ST    (BIT(2))
+#define H264_FRAME_DONE_INT_ST_M  (H264_FRAME_DONE_INT_ST_V << H264_FRAME_DONE_INT_ST_S)
+#define H264_FRAME_DONE_INT_ST_V  0x00000001U
+#define H264_FRAME_DONE_INT_ST_S  2
+/** H264_DMA_MOVE_2MB_LINE_DONE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT.
+ *  Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1.
+ */
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ST    (BIT(3))
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ST_M  (H264_DMA_MOVE_2MB_LINE_DONE_INT_ST_V << H264_DMA_MOVE_2MB_LINE_DONE_INT_ST_S)
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ST_V  0x00000001U
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ST_S  3
+/** H264_BS_BUFFER_OVERFLOW_INT_ST : RO; bitpos: [4]; default: 0;
+ *  Masked status bit: The masked interrupt status of H264_BS_BUFFER_OVERFLOW_INT.
+ *  Valid only when the H264_BS_BUFFER_OVERFLOW_INT_ENA is set to 1.
+ */
+#define H264_BS_BUFFER_OVERFLOW_INT_ST    (BIT(4))
+#define H264_BS_BUFFER_OVERFLOW_INT_ST_M  (H264_BS_BUFFER_OVERFLOW_INT_ST_V << H264_BS_BUFFER_OVERFLOW_INT_ST_S)
+#define H264_BS_BUFFER_OVERFLOW_INT_ST_V  0x00000001U
+#define H264_BS_BUFFER_OVERFLOW_INT_ST_S  4
+
+/** H264_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define H264_INT_ENA_REG (DR_REG_H264_BASE + 0xc8)
+/** H264_DB_TMP_READY_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Enable bit: Write 1 to enable H264_DB_TMP_READY_INT.
+ */
+#define H264_DB_TMP_READY_INT_ENA    (BIT(0))
+#define H264_DB_TMP_READY_INT_ENA_M  (H264_DB_TMP_READY_INT_ENA_V << H264_DB_TMP_READY_INT_ENA_S)
+#define H264_DB_TMP_READY_INT_ENA_V  0x00000001U
+#define H264_DB_TMP_READY_INT_ENA_S  0
+/** H264_REC_READY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Enable bit: Write 1 to enable H264_REC_READY_INT.
+ */
+#define H264_REC_READY_INT_ENA    (BIT(1))
+#define H264_REC_READY_INT_ENA_M  (H264_REC_READY_INT_ENA_V << H264_REC_READY_INT_ENA_S)
+#define H264_REC_READY_INT_ENA_V  0x00000001U
+#define H264_REC_READY_INT_ENA_S  1
+/** H264_FRAME_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Enable bit: Write 1 to enable H264_FRAME_DONE_INT.
+ */
+#define H264_FRAME_DONE_INT_ENA    (BIT(2))
+#define H264_FRAME_DONE_INT_ENA_M  (H264_FRAME_DONE_INT_ENA_V << H264_FRAME_DONE_INT_ENA_S)
+#define H264_FRAME_DONE_INT_ENA_V  0x00000001U
+#define H264_FRAME_DONE_INT_ENA_S  2
+/** H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT.
+ */
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA    (BIT(3))
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA_M  (H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA_V << H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA_S)
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA_V  0x00000001U
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA_S  3
+/** H264_BS_BUFFER_OVERFLOW_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Enable bit: Write 1 to enable H264_BS_BUFFER_OVERFLOW_INT.
+ */
+#define H264_BS_BUFFER_OVERFLOW_INT_ENA    (BIT(4))
+#define H264_BS_BUFFER_OVERFLOW_INT_ENA_M  (H264_BS_BUFFER_OVERFLOW_INT_ENA_V << H264_BS_BUFFER_OVERFLOW_INT_ENA_S)
+#define H264_BS_BUFFER_OVERFLOW_INT_ENA_V  0x00000001U
+#define H264_BS_BUFFER_OVERFLOW_INT_ENA_S  4
+
+/** H264_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define H264_INT_CLR_REG (DR_REG_H264_BASE + 0xcc)
+/** H264_DB_TMP_READY_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear bit: Write 1 to clear H264_DB_TMP_READY_INT.
+ */
+#define H264_DB_TMP_READY_INT_CLR    (BIT(0))
+#define H264_DB_TMP_READY_INT_CLR_M  (H264_DB_TMP_READY_INT_CLR_V << H264_DB_TMP_READY_INT_CLR_S)
+#define H264_DB_TMP_READY_INT_CLR_V  0x00000001U
+#define H264_DB_TMP_READY_INT_CLR_S  0
+/** H264_REC_READY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Clear bit: Write 1 to clear H264_REC_READY_INT.
+ */
+#define H264_REC_READY_INT_CLR    (BIT(1))
+#define H264_REC_READY_INT_CLR_M  (H264_REC_READY_INT_CLR_V << H264_REC_READY_INT_CLR_S)
+#define H264_REC_READY_INT_CLR_V  0x00000001U
+#define H264_REC_READY_INT_CLR_S  1
+/** H264_FRAME_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Clear bit: Write 1 to clear H264_FRAME_DONE_INT.
+ */
+#define H264_FRAME_DONE_INT_CLR    (BIT(2))
+#define H264_FRAME_DONE_INT_CLR_M  (H264_FRAME_DONE_INT_CLR_V << H264_FRAME_DONE_INT_CLR_S)
+#define H264_FRAME_DONE_INT_CLR_V  0x00000001U
+#define H264_FRAME_DONE_INT_CLR_S  2
+/** H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT.
+ */
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR    (BIT(3))
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR_M  (H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR_V << H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR_S)
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR_V  0x00000001U
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR_S  3
+/** H264_BS_BUFFER_OVERFLOW_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Clear bit: Write 1 to clear H264_BS_BUFFER_OVERFLOW_INT.
+ */
+#define H264_BS_BUFFER_OVERFLOW_INT_CLR    (BIT(4))
+#define H264_BS_BUFFER_OVERFLOW_INT_CLR_M  (H264_BS_BUFFER_OVERFLOW_INT_CLR_V << H264_BS_BUFFER_OVERFLOW_INT_CLR_S)
+#define H264_BS_BUFFER_OVERFLOW_INT_CLR_V  0x00000001U
+#define H264_BS_BUFFER_OVERFLOW_INT_CLR_S  4
+
+/** H264_CONF_REG register
+ *  General configuration register.
+ */
+#define H264_CONF_REG (DR_REG_H264_BASE + 0xd0)
+/** H264_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to open register clock gate.
+ *  0: Open the clock gate only when application writes registers
+ *  1: Force open the clock gate for register
+ */
+#define H264_CLK_EN    (BIT(0))
+#define H264_CLK_EN_M  (H264_CLK_EN_V << H264_CLK_EN_S)
+#define H264_CLK_EN_V  0x00000001U
+#define H264_CLK_EN_S  0
+/** H264_REC_RAM_CLK_EN2 : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to open the clock gate for rec ram2.
+ *  0: Open the clock gate only when application writes or reads rec ram2
+ *  1: Force open the clock gate for rec ram2
+ */
+#define H264_REC_RAM_CLK_EN2    (BIT(1))
+#define H264_REC_RAM_CLK_EN2_M  (H264_REC_RAM_CLK_EN2_V << H264_REC_RAM_CLK_EN2_S)
+#define H264_REC_RAM_CLK_EN2_V  0x00000001U
+#define H264_REC_RAM_CLK_EN2_S  1
+/** H264_REC_RAM_CLK_EN1 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to open the clock gate for rec ram1.
+ *  0: Open the clock gate only when application writes or reads rec ram1
+ *  1: Force open the clock gate for rec ram1
+ */
+#define H264_REC_RAM_CLK_EN1    (BIT(2))
+#define H264_REC_RAM_CLK_EN1_M  (H264_REC_RAM_CLK_EN1_V << H264_REC_RAM_CLK_EN1_S)
+#define H264_REC_RAM_CLK_EN1_V  0x00000001U
+#define H264_REC_RAM_CLK_EN1_S  2
+/** H264_QUANT_RAM_CLK_EN2 : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to open the clock gate for quant ram2.
+ *  0: Open the clock gate only when application writes or reads quant ram2
+ *  1: Force open the clock gate for quant ram2
+ */
+#define H264_QUANT_RAM_CLK_EN2    (BIT(3))
+#define H264_QUANT_RAM_CLK_EN2_M  (H264_QUANT_RAM_CLK_EN2_V << H264_QUANT_RAM_CLK_EN2_S)
+#define H264_QUANT_RAM_CLK_EN2_V  0x00000001U
+#define H264_QUANT_RAM_CLK_EN2_S  3
+/** H264_QUANT_RAM_CLK_EN1 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to open the clock gate for quant ram1.
+ *  0: Open the clock gate only when application writes or reads quant ram1
+ *  1: Force open the clock gate for quant ram1
+ */
+#define H264_QUANT_RAM_CLK_EN1    (BIT(4))
+#define H264_QUANT_RAM_CLK_EN1_M  (H264_QUANT_RAM_CLK_EN1_V << H264_QUANT_RAM_CLK_EN1_S)
+#define H264_QUANT_RAM_CLK_EN1_V  0x00000001U
+#define H264_QUANT_RAM_CLK_EN1_S  4
+/** H264_PRE_RAM_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to open the clock gate for pre ram.
+ *  0: Open the clock gate only when application writes or reads pre ram
+ *  1: Force open the clock gate for pre ram
+ */
+#define H264_PRE_RAM_CLK_EN    (BIT(5))
+#define H264_PRE_RAM_CLK_EN_M  (H264_PRE_RAM_CLK_EN_V << H264_PRE_RAM_CLK_EN_S)
+#define H264_PRE_RAM_CLK_EN_V  0x00000001U
+#define H264_PRE_RAM_CLK_EN_S  5
+/** H264_MVD_RAM_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to open the clock gate for mvd ram.
+ *  0: Open the clock gate only when application writes or reads mvd ram
+ *  1: Force open the clock gate for mvd ram
+ */
+#define H264_MVD_RAM_CLK_EN    (BIT(6))
+#define H264_MVD_RAM_CLK_EN_M  (H264_MVD_RAM_CLK_EN_V << H264_MVD_RAM_CLK_EN_S)
+#define H264_MVD_RAM_CLK_EN_V  0x00000001U
+#define H264_MVD_RAM_CLK_EN_S  6
+/** H264_MC_RAM_CLK_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to open the clock gate for mc ram.
+ *  0: Open the clock gate only when application writes or reads mc ram
+ *  1: Force open the clock gate for mc ram
+ */
+#define H264_MC_RAM_CLK_EN    (BIT(7))
+#define H264_MC_RAM_CLK_EN_M  (H264_MC_RAM_CLK_EN_V << H264_MC_RAM_CLK_EN_S)
+#define H264_MC_RAM_CLK_EN_V  0x00000001U
+#define H264_MC_RAM_CLK_EN_S  7
+/** H264_REF_RAM_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to open the clock gate for ref ram.
+ *  0: Open the clock gate only when application writes or reads ref ram
+ *  1: Force open the clock gate for ref ram
+ */
+#define H264_REF_RAM_CLK_EN    (BIT(8))
+#define H264_REF_RAM_CLK_EN_M  (H264_REF_RAM_CLK_EN_V << H264_REF_RAM_CLK_EN_S)
+#define H264_REF_RAM_CLK_EN_V  0x00000001U
+#define H264_REF_RAM_CLK_EN_S  8
+/** H264_I4X4_REF_RAM_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to open the clock gate for i4x4_mode ram.
+ *  0: Open the clock gate only when application writes or reads i4x4_mode ram
+ *  1: Force open the clock gate for i4x4_mode ram
+ */
+#define H264_I4X4_REF_RAM_CLK_EN    (BIT(9))
+#define H264_I4X4_REF_RAM_CLK_EN_M  (H264_I4X4_REF_RAM_CLK_EN_V << H264_I4X4_REF_RAM_CLK_EN_S)
+#define H264_I4X4_REF_RAM_CLK_EN_V  0x00000001U
+#define H264_I4X4_REF_RAM_CLK_EN_S  9
+/** H264_IME_RAM_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to open the clock gate for ime ram.
+ *  0: Open the clock gate only when application writes or reads ime ram
+ *  1: Force open the clock gate for ime ram
+ */
+#define H264_IME_RAM_CLK_EN    (BIT(10))
+#define H264_IME_RAM_CLK_EN_M  (H264_IME_RAM_CLK_EN_V << H264_IME_RAM_CLK_EN_S)
+#define H264_IME_RAM_CLK_EN_V  0x00000001U
+#define H264_IME_RAM_CLK_EN_S  10
+/** H264_FME_RAM_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to open the clock gate for fme ram.
+ *  0: Open the clock gate only when application writes or readsfme ram
+ *  1: Force open the clock gate for fme ram
+ */
+#define H264_FME_RAM_CLK_EN    (BIT(11))
+#define H264_FME_RAM_CLK_EN_M  (H264_FME_RAM_CLK_EN_V << H264_FME_RAM_CLK_EN_S)
+#define H264_FME_RAM_CLK_EN_V  0x00000001U
+#define H264_FME_RAM_CLK_EN_S  11
+/** H264_FETCH_RAM_CLK_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to open the clock gate for fetch ram.
+ *  0: Open the clock gate only when application writes or reads fetch ram
+ *  1: Force open the clock gate for fetch ram
+ */
+#define H264_FETCH_RAM_CLK_EN    (BIT(12))
+#define H264_FETCH_RAM_CLK_EN_M  (H264_FETCH_RAM_CLK_EN_V << H264_FETCH_RAM_CLK_EN_S)
+#define H264_FETCH_RAM_CLK_EN_V  0x00000001U
+#define H264_FETCH_RAM_CLK_EN_S  12
+/** H264_DB_RAM_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to open the clock gate for db ram.
+ *  0: Open the clock gate only when application writes or reads db ram
+ *  1: Force open the clock gate for db ram
+ */
+#define H264_DB_RAM_CLK_EN    (BIT(13))
+#define H264_DB_RAM_CLK_EN_M  (H264_DB_RAM_CLK_EN_V << H264_DB_RAM_CLK_EN_S)
+#define H264_DB_RAM_CLK_EN_V  0x00000001U
+#define H264_DB_RAM_CLK_EN_S  13
+/** H264_CUR_MB_RAM_CLK_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to open the clock gate for cur_mb ram.
+ *  0: Open the clock gate only when application writes or reads cur_mb ram
+ *  1: Force open the clock gate for cur_mb ram
+ */
+#define H264_CUR_MB_RAM_CLK_EN    (BIT(14))
+#define H264_CUR_MB_RAM_CLK_EN_M  (H264_CUR_MB_RAM_CLK_EN_V << H264_CUR_MB_RAM_CLK_EN_S)
+#define H264_CUR_MB_RAM_CLK_EN_V  0x00000001U
+#define H264_CUR_MB_RAM_CLK_EN_S  14
+/** H264_CAVLC_RAM_CLK_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to open the clock gate for cavlc ram.
+ *  0: Open the clock gate only when application writes or reads cavlc ram
+ *  1: Force open the clock gate for cavlc ram
+ */
+#define H264_CAVLC_RAM_CLK_EN    (BIT(15))
+#define H264_CAVLC_RAM_CLK_EN_M  (H264_CAVLC_RAM_CLK_EN_V << H264_CAVLC_RAM_CLK_EN_S)
+#define H264_CAVLC_RAM_CLK_EN_V  0x00000001U
+#define H264_CAVLC_RAM_CLK_EN_S  15
+/** H264_IME_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to open the clock gate for ime.
+ *  0: Open the clock gate only when ime work
+ *  1: Force open the clock gate for ime
+ */
+#define H264_IME_CLK_EN    (BIT(16))
+#define H264_IME_CLK_EN_M  (H264_IME_CLK_EN_V << H264_IME_CLK_EN_S)
+#define H264_IME_CLK_EN_V  0x00000001U
+#define H264_IME_CLK_EN_S  16
+/** H264_FME_CLK_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to open the clock gate for fme.
+ *  0: Open the clock gate only when fme work
+ *  1: Force open the clock gate for fme
+ */
+#define H264_FME_CLK_EN    (BIT(17))
+#define H264_FME_CLK_EN_M  (H264_FME_CLK_EN_V << H264_FME_CLK_EN_S)
+#define H264_FME_CLK_EN_V  0x00000001U
+#define H264_FME_CLK_EN_S  17
+/** H264_MC_CLK_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to open the clock gate for mc.
+ *  0: Open the clock gate only when mc work
+ *  1: Force open the clock gate for mc
+ */
+#define H264_MC_CLK_EN    (BIT(18))
+#define H264_MC_CLK_EN_M  (H264_MC_CLK_EN_V << H264_MC_CLK_EN_S)
+#define H264_MC_CLK_EN_V  0x00000001U
+#define H264_MC_CLK_EN_S  18
+/** H264_INTERPOLATOR_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to open the clock gate for interpolator.
+ *  0: Open the clock gate only when interpolator work
+ *  1: Force open the clock gate for interpolator
+ */
+#define H264_INTERPOLATOR_CLK_EN    (BIT(19))
+#define H264_INTERPOLATOR_CLK_EN_M  (H264_INTERPOLATOR_CLK_EN_V << H264_INTERPOLATOR_CLK_EN_S)
+#define H264_INTERPOLATOR_CLK_EN_V  0x00000001U
+#define H264_INTERPOLATOR_CLK_EN_S  19
+/** H264_DB_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to open the clock gate for deblocking filter.
+ *  0: Open the clock gate only when deblocking filter work
+ *  1: Force open the clock gate for deblocking filter
+ */
+#define H264_DB_CLK_EN    (BIT(20))
+#define H264_DB_CLK_EN_M  (H264_DB_CLK_EN_V << H264_DB_CLK_EN_S)
+#define H264_DB_CLK_EN_V  0x00000001U
+#define H264_DB_CLK_EN_S  20
+/** H264_CLAVLC_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to open the clock gate for cavlc.
+ *  0: Open the clock gate only when cavlc work
+ *  1: Force open the clock gate for cavlc
+ */
+#define H264_CLAVLC_CLK_EN    (BIT(21))
+#define H264_CLAVLC_CLK_EN_M  (H264_CLAVLC_CLK_EN_V << H264_CLAVLC_CLK_EN_S)
+#define H264_CLAVLC_CLK_EN_V  0x00000001U
+#define H264_CLAVLC_CLK_EN_S  21
+/** H264_INTRA_CLK_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to open the clock gate for intra.
+ *  0: Open the clock gate only when intra work
+ *  1: Force open the clock gate for intra
+ */
+#define H264_INTRA_CLK_EN    (BIT(22))
+#define H264_INTRA_CLK_EN_M  (H264_INTRA_CLK_EN_V << H264_INTRA_CLK_EN_S)
+#define H264_INTRA_CLK_EN_V  0x00000001U
+#define H264_INTRA_CLK_EN_S  22
+/** H264_DECI_CLK_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to open the clock gate for decimate.
+ *  0: Open the clock gate only when decimate work
+ *  1: Force open the clock gate for decimate
+ */
+#define H264_DECI_CLK_EN    (BIT(23))
+#define H264_DECI_CLK_EN_M  (H264_DECI_CLK_EN_V << H264_DECI_CLK_EN_S)
+#define H264_DECI_CLK_EN_V  0x00000001U
+#define H264_DECI_CLK_EN_S  23
+/** H264_BS_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Configures whether or not to open the clock gate for bs buffer.
+ *  0: Open the clock gate only when bs buffer work
+ *  1: Force open the clock gate for bs buffer
+ */
+#define H264_BS_CLK_EN    (BIT(24))
+#define H264_BS_CLK_EN_M  (H264_BS_CLK_EN_V << H264_BS_CLK_EN_S)
+#define H264_BS_CLK_EN_V  0x00000001U
+#define H264_BS_CLK_EN_S  24
+/** H264_MV_MERGE_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not to open the clock gate for mv merge.
+ *  0: Open the clock gate only when mv merge work
+ *  1: Force open the clock gate for mv merge
+ */
+#define H264_MV_MERGE_CLK_EN    (BIT(25))
+#define H264_MV_MERGE_CLK_EN_M  (H264_MV_MERGE_CLK_EN_V << H264_MV_MERGE_CLK_EN_S)
+#define H264_MV_MERGE_CLK_EN_V  0x00000001U
+#define H264_MV_MERGE_CLK_EN_S  25
+/** H264_CUR_MB_RDCMB_CLK_EN : R/W; bitpos: [26]; default: 0;
+ *  Configures whether or not to open the clock gate for cur_mb read macroblock.
+ *  0: Open the clock gate only when cur_mb read macroblock work
+ *  1: Force open the clock gate for  cur_mb read macroblock
+ */
+#define H264_CUR_MB_RDCMB_CLK_EN    (BIT(26))
+#define H264_CUR_MB_RDCMB_CLK_EN_M  (H264_CUR_MB_RDCMB_CLK_EN_V << H264_CUR_MB_RDCMB_CLK_EN_S)
+#define H264_CUR_MB_RDCMB_CLK_EN_V  0x00000001U
+#define H264_CUR_MB_RDCMB_CLK_EN_S  26
+/** H264_CUR_MB_REFRESH_REGGROUP_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to open the clock gate for cur_mb refresh register group.
+ *  0: Open the clock gate only when cur_mb refresh register group work
+ *  1: Force open the clock gate for  cur_mb  refresh register group
+ */
+#define H264_CUR_MB_REFRESH_REGGROUP_CLK_EN    (BIT(27))
+#define H264_CUR_MB_REFRESH_REGGROUP_CLK_EN_M  (H264_CUR_MB_REFRESH_REGGROUP_CLK_EN_V << H264_CUR_MB_REFRESH_REGGROUP_CLK_EN_S)
+#define H264_CUR_MB_REFRESH_REGGROUP_CLK_EN_V  0x00000001U
+#define H264_CUR_MB_REFRESH_REGGROUP_CLK_EN_S  27
+
+/** H264_MV_MERGE_CONFIG_REG register
+ *  Mv merge configuration register.
+ */
+#define H264_MV_MERGE_CONFIG_REG (DR_REG_H264_BASE + 0xd4)
+/** H264_MV_MERGE_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  Configure mv merge type.
+ *  0: merge p16x16 mv
+ *  1: merge min mv
+ *  2: merge max mv
+ *  3: not valid.
+ */
+#define H264_MV_MERGE_TYPE    0x00000003U
+#define H264_MV_MERGE_TYPE_M  (H264_MV_MERGE_TYPE_V << H264_MV_MERGE_TYPE_S)
+#define H264_MV_MERGE_TYPE_V  0x00000003U
+#define H264_MV_MERGE_TYPE_S  0
+/** H264_INT_MV_OUT_EN : R/W; bitpos: [2]; default: 0;
+ *  Configure mv merge output integer part not zero mv or all part not zero mv.
+ *  0: output all part not zero mv
+ *  1: output integer part not zero mv.
+ */
+#define H264_INT_MV_OUT_EN    (BIT(2))
+#define H264_INT_MV_OUT_EN_M  (H264_INT_MV_OUT_EN_V << H264_INT_MV_OUT_EN_S)
+#define H264_INT_MV_OUT_EN_V  0x00000001U
+#define H264_INT_MV_OUT_EN_S  2
+/** H264_A_MV_MERGE_EN : R/W; bitpos: [3]; default: 0;
+ *  Configure whether or not to enable video A mv merge.
+ *  0: disable
+ *  1: enable.
+ */
+#define H264_A_MV_MERGE_EN    (BIT(3))
+#define H264_A_MV_MERGE_EN_M  (H264_A_MV_MERGE_EN_V << H264_A_MV_MERGE_EN_S)
+#define H264_A_MV_MERGE_EN_V  0x00000001U
+#define H264_A_MV_MERGE_EN_S  3
+/** H264_B_MV_MERGE_EN : R/W; bitpos: [4]; default: 0;
+ *  Configure whether or not to enable video B mv merge.
+ *  0: disable
+ *  1: enable.
+ */
+#define H264_B_MV_MERGE_EN    (BIT(4))
+#define H264_B_MV_MERGE_EN_M  (H264_B_MV_MERGE_EN_V << H264_B_MV_MERGE_EN_S)
+#define H264_B_MV_MERGE_EN_V  0x00000001U
+#define H264_B_MV_MERGE_EN_S  4
+/** H264_MB_VALID_NUM : RO; bitpos: [17:5]; default: 0;
+ *  Represents the valid mb number of mv merge output.
+ */
+#define H264_MB_VALID_NUM    0x00001FFFU
+#define H264_MB_VALID_NUM_M  (H264_MB_VALID_NUM_V << H264_MB_VALID_NUM_S)
+#define H264_MB_VALID_NUM_V  0x00001FFFU
+#define H264_MB_VALID_NUM_S  5
+
+/** H264_DEBUG_DMA_SEL_REG register
+ *  Debug H264 DMA select register
+ */
+#define H264_DEBUG_DMA_SEL_REG (DR_REG_H264_BASE + 0xd8)
+/** H264_DBG_DMA_SEL : R/W; bitpos: [7:0]; default: 0;
+ *  Every bit represents a dma in h264
+ */
+#define H264_DBG_DMA_SEL    0x000000FFU
+#define H264_DBG_DMA_SEL_M  (H264_DBG_DMA_SEL_V << H264_DBG_DMA_SEL_S)
+#define H264_DBG_DMA_SEL_V  0x000000FFU
+#define H264_DBG_DMA_SEL_S  0
+
+/** H264_SYS_STATUS_REG register
+ *  System status register.
+ */
+#define H264_SYS_STATUS_REG (DR_REG_H264_BASE + 0xdc)
+/** H264_FRAME_NUM : RO; bitpos: [8:0]; default: 0;
+ *  Represents current frame number.
+ */
+#define H264_FRAME_NUM    0x000001FFU
+#define H264_FRAME_NUM_M  (H264_FRAME_NUM_V << H264_FRAME_NUM_S)
+#define H264_FRAME_NUM_V  0x000001FFU
+#define H264_FRAME_NUM_S  0
+/** H264_DUAL_STREAM_SEL : RO; bitpos: [9]; default: 0;
+ *  Represents which register group is used for cur frame.
+ *  0: Register group A is used
+ *  1: Register group B is used.
+ */
+#define H264_DUAL_STREAM_SEL    (BIT(9))
+#define H264_DUAL_STREAM_SEL_M  (H264_DUAL_STREAM_SEL_V << H264_DUAL_STREAM_SEL_S)
+#define H264_DUAL_STREAM_SEL_V  0x00000001U
+#define H264_DUAL_STREAM_SEL_S  9
+/** H264_INTRA_FLAG : RO; bitpos: [10]; default: 0;
+ *  Represents the type of current encoding frame.
+ *  0: P frame
+ *  1: I frame.
+ */
+#define H264_INTRA_FLAG    (BIT(10))
+#define H264_INTRA_FLAG_M  (H264_INTRA_FLAG_V << H264_INTRA_FLAG_S)
+#define H264_INTRA_FLAG_V  0x00000001U
+#define H264_INTRA_FLAG_S  10
+
+/** H264_FRAME_CODE_LENGTH_REG register
+ *  Frame code byte length register.
+ */
+#define H264_FRAME_CODE_LENGTH_REG (DR_REG_H264_BASE + 0xe0)
+/** H264_FRAME_CODE_LENGTH : RO; bitpos: [23:0]; default: 0;
+ *  Represents current frame code byte length.
+ */
+#define H264_FRAME_CODE_LENGTH    0x00FFFFFFU
+#define H264_FRAME_CODE_LENGTH_M  (H264_FRAME_CODE_LENGTH_V << H264_FRAME_CODE_LENGTH_S)
+#define H264_FRAME_CODE_LENGTH_V  0x00FFFFFFU
+#define H264_FRAME_CODE_LENGTH_S  0
+
+/** H264_DEBUG_INFO0_REG register
+ *  Debug information register0.
+ */
+#define H264_DEBUG_INFO0_REG (DR_REG_H264_BASE + 0xe4)
+/** H264_TOP_CTRL_INTER_DEBUG_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Represents top_ctrl_inter module FSM info.
+ */
+#define H264_TOP_CTRL_INTER_DEBUG_STATE    0x0000000FU
+#define H264_TOP_CTRL_INTER_DEBUG_STATE_M  (H264_TOP_CTRL_INTER_DEBUG_STATE_V << H264_TOP_CTRL_INTER_DEBUG_STATE_S)
+#define H264_TOP_CTRL_INTER_DEBUG_STATE_V  0x0000000FU
+#define H264_TOP_CTRL_INTER_DEBUG_STATE_S  0
+/** H264_TOP_CTRL_INTRA_DEBUG_STATE : RO; bitpos: [6:4]; default: 0;
+ *  Represents top_ctrl_intra module FSM info.
+ */
+#define H264_TOP_CTRL_INTRA_DEBUG_STATE    0x00000007U
+#define H264_TOP_CTRL_INTRA_DEBUG_STATE_M  (H264_TOP_CTRL_INTRA_DEBUG_STATE_V << H264_TOP_CTRL_INTRA_DEBUG_STATE_S)
+#define H264_TOP_CTRL_INTRA_DEBUG_STATE_V  0x00000007U
+#define H264_TOP_CTRL_INTRA_DEBUG_STATE_S  4
+/** H264_P_I_CMP_DEBUG_STATE : RO; bitpos: [9:7]; default: 0;
+ *  Represents p_i_cmp module FSM info.
+ */
+#define H264_P_I_CMP_DEBUG_STATE    0x00000007U
+#define H264_P_I_CMP_DEBUG_STATE_M  (H264_P_I_CMP_DEBUG_STATE_V << H264_P_I_CMP_DEBUG_STATE_S)
+#define H264_P_I_CMP_DEBUG_STATE_V  0x00000007U
+#define H264_P_I_CMP_DEBUG_STATE_S  7
+/** H264_MVD_DEBUG_STATE : RO; bitpos: [12:10]; default: 0;
+ *  Represents mvd module FSM info.
+ */
+#define H264_MVD_DEBUG_STATE    0x00000007U
+#define H264_MVD_DEBUG_STATE_M  (H264_MVD_DEBUG_STATE_V << H264_MVD_DEBUG_STATE_S)
+#define H264_MVD_DEBUG_STATE_V  0x00000007U
+#define H264_MVD_DEBUG_STATE_S  10
+/** H264_MC_CHROMA_IP_DEBUG_STATE : RO; bitpos: [13]; default: 0;
+ *  Represents mc_chroma_ip module FSM info.
+ */
+#define H264_MC_CHROMA_IP_DEBUG_STATE    (BIT(13))
+#define H264_MC_CHROMA_IP_DEBUG_STATE_M  (H264_MC_CHROMA_IP_DEBUG_STATE_V << H264_MC_CHROMA_IP_DEBUG_STATE_S)
+#define H264_MC_CHROMA_IP_DEBUG_STATE_V  0x00000001U
+#define H264_MC_CHROMA_IP_DEBUG_STATE_S  13
+/** H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE : RO; bitpos: [17:14]; default: 0;
+ *  Represents intra_16x16_chroma_ctrl module FSM info.
+ */
+#define H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE    0x0000000FU
+#define H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_M  (H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_V << H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_S)
+#define H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_V  0x0000000FU
+#define H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_S  14
+/** H264_INTRA_4X4_CTRL_DEBUG_STATE : RO; bitpos: [21:18]; default: 0;
+ *  Represents intra_4x4_ctrl module FSM info.
+ */
+#define H264_INTRA_4X4_CTRL_DEBUG_STATE    0x0000000FU
+#define H264_INTRA_4X4_CTRL_DEBUG_STATE_M  (H264_INTRA_4X4_CTRL_DEBUG_STATE_V << H264_INTRA_4X4_CTRL_DEBUG_STATE_S)
+#define H264_INTRA_4X4_CTRL_DEBUG_STATE_V  0x0000000FU
+#define H264_INTRA_4X4_CTRL_DEBUG_STATE_S  18
+/** H264_INTRA_TOP_CTRL_DEBUG_STATE : RO; bitpos: [24:22]; default: 0;
+ *  Represents intra_top_ctrl module FSM info.
+ */
+#define H264_INTRA_TOP_CTRL_DEBUG_STATE    0x00000007U
+#define H264_INTRA_TOP_CTRL_DEBUG_STATE_M  (H264_INTRA_TOP_CTRL_DEBUG_STATE_V << H264_INTRA_TOP_CTRL_DEBUG_STATE_S)
+#define H264_INTRA_TOP_CTRL_DEBUG_STATE_V  0x00000007U
+#define H264_INTRA_TOP_CTRL_DEBUG_STATE_S  22
+/** H264_IME_CTRL_DEBUG_STATE : RO; bitpos: [27:25]; default: 0;
+ *  Represents ime_ctrl module FSM info.
+ */
+#define H264_IME_CTRL_DEBUG_STATE    0x00000007U
+#define H264_IME_CTRL_DEBUG_STATE_M  (H264_IME_CTRL_DEBUG_STATE_V << H264_IME_CTRL_DEBUG_STATE_S)
+#define H264_IME_CTRL_DEBUG_STATE_V  0x00000007U
+#define H264_IME_CTRL_DEBUG_STATE_S  25
+
+/** H264_DEBUG_INFO1_REG register
+ *  Debug information register1.
+ */
+#define H264_DEBUG_INFO1_REG (DR_REG_H264_BASE + 0xe8)
+/** H264_FME_CTRL_DEBUG_STATE : RO; bitpos: [2:0]; default: 0;
+ *  Represents fme_ctrl module FSM info.
+ */
+#define H264_FME_CTRL_DEBUG_STATE    0x00000007U
+#define H264_FME_CTRL_DEBUG_STATE_M  (H264_FME_CTRL_DEBUG_STATE_V << H264_FME_CTRL_DEBUG_STATE_S)
+#define H264_FME_CTRL_DEBUG_STATE_V  0x00000007U
+#define H264_FME_CTRL_DEBUG_STATE_S  0
+/** H264_DECI_CALC_DEBUG_STATE : RO; bitpos: [4:3]; default: 0;
+ *  Represents deci_calc module's FSM info. DEV use only.
+ */
+#define H264_DECI_CALC_DEBUG_STATE    0x00000003U
+#define H264_DECI_CALC_DEBUG_STATE_M  (H264_DECI_CALC_DEBUG_STATE_V << H264_DECI_CALC_DEBUG_STATE_S)
+#define H264_DECI_CALC_DEBUG_STATE_V  0x00000003U
+#define H264_DECI_CALC_DEBUG_STATE_S  3
+/** H264_DB_DEBUG_STATE : RO; bitpos: [7:5]; default: 0;
+ *  Represents db module FSM info.
+ */
+#define H264_DB_DEBUG_STATE    0x00000007U
+#define H264_DB_DEBUG_STATE_M  (H264_DB_DEBUG_STATE_V << H264_DB_DEBUG_STATE_S)
+#define H264_DB_DEBUG_STATE_V  0x00000007U
+#define H264_DB_DEBUG_STATE_S  5
+/** H264_CAVLC_ENC_DEBUG_STATE : RO; bitpos: [11:8]; default: 0;
+ *  Represents cavlc module enc FSM info.
+ */
+#define H264_CAVLC_ENC_DEBUG_STATE    0x0000000FU
+#define H264_CAVLC_ENC_DEBUG_STATE_M  (H264_CAVLC_ENC_DEBUG_STATE_V << H264_CAVLC_ENC_DEBUG_STATE_S)
+#define H264_CAVLC_ENC_DEBUG_STATE_V  0x0000000FU
+#define H264_CAVLC_ENC_DEBUG_STATE_S  8
+/** H264_CAVLC_SCAN_DEBUG_STATE : RO; bitpos: [15:12]; default: 0;
+ *  Represents cavlc module scan FSM info.
+ */
+#define H264_CAVLC_SCAN_DEBUG_STATE    0x0000000FU
+#define H264_CAVLC_SCAN_DEBUG_STATE_M  (H264_CAVLC_SCAN_DEBUG_STATE_V << H264_CAVLC_SCAN_DEBUG_STATE_S)
+#define H264_CAVLC_SCAN_DEBUG_STATE_V  0x0000000FU
+#define H264_CAVLC_SCAN_DEBUG_STATE_S  12
+/** H264_CAVLC_CTRL_DEBUG_STATE : RO; bitpos: [17:16]; default: 0;
+ *  Represents cavlc module ctrl FSM info.
+ */
+#define H264_CAVLC_CTRL_DEBUG_STATE    0x00000003U
+#define H264_CAVLC_CTRL_DEBUG_STATE_M  (H264_CAVLC_CTRL_DEBUG_STATE_V << H264_CAVLC_CTRL_DEBUG_STATE_S)
+#define H264_CAVLC_CTRL_DEBUG_STATE_V  0x00000003U
+#define H264_CAVLC_CTRL_DEBUG_STATE_S  16
+
+/** H264_DEBUG_INFO2_REG register
+ *  Debug information register2.
+ */
+#define H264_DEBUG_INFO2_REG (DR_REG_H264_BASE + 0xec)
+/** H264_P_RC_DONE_DEBUG_FLAG : RO; bitpos: [0]; default: 0;
+ *  Represents p rate ctrl done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_RC_DONE_DEBUG_FLAG    (BIT(0))
+#define H264_P_RC_DONE_DEBUG_FLAG_M  (H264_P_RC_DONE_DEBUG_FLAG_V << H264_P_RC_DONE_DEBUG_FLAG_S)
+#define H264_P_RC_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_RC_DONE_DEBUG_FLAG_S  0
+/** H264_P_P_I_CMP_DONE_DEBUG_FLAG : RO; bitpos: [1]; default: 0;
+ *  Represents p p_i_cmp done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_P_I_CMP_DONE_DEBUG_FLAG    (BIT(1))
+#define H264_P_P_I_CMP_DONE_DEBUG_FLAG_M  (H264_P_P_I_CMP_DONE_DEBUG_FLAG_V << H264_P_P_I_CMP_DONE_DEBUG_FLAG_S)
+#define H264_P_P_I_CMP_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_P_I_CMP_DONE_DEBUG_FLAG_S  1
+/** H264_P_MV_MERGE_DONE_DEBUG_FLAG : RO; bitpos: [2]; default: 0;
+ *  Represents p mv merge done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_MV_MERGE_DONE_DEBUG_FLAG    (BIT(2))
+#define H264_P_MV_MERGE_DONE_DEBUG_FLAG_M  (H264_P_MV_MERGE_DONE_DEBUG_FLAG_V << H264_P_MV_MERGE_DONE_DEBUG_FLAG_S)
+#define H264_P_MV_MERGE_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_MV_MERGE_DONE_DEBUG_FLAG_S  2
+/** H264_P_MOVE_ORI_DONE_DEBUG_FLAG : RO; bitpos: [3]; default: 0;
+ *  Represents p move origin done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_MOVE_ORI_DONE_DEBUG_FLAG    (BIT(3))
+#define H264_P_MOVE_ORI_DONE_DEBUG_FLAG_M  (H264_P_MOVE_ORI_DONE_DEBUG_FLAG_V << H264_P_MOVE_ORI_DONE_DEBUG_FLAG_S)
+#define H264_P_MOVE_ORI_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_MOVE_ORI_DONE_DEBUG_FLAG_S  3
+/** H264_P_MC_DONE_DEBUG_FLAG : RO; bitpos: [4]; default: 0;
+ *  Represents p mc done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_MC_DONE_DEBUG_FLAG    (BIT(4))
+#define H264_P_MC_DONE_DEBUG_FLAG_M  (H264_P_MC_DONE_DEBUG_FLAG_V << H264_P_MC_DONE_DEBUG_FLAG_S)
+#define H264_P_MC_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_MC_DONE_DEBUG_FLAG_S  4
+/** H264_P_IME_DONE_DEBUG_FLAG : RO; bitpos: [5]; default: 0;
+ *  Represents p ime done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_IME_DONE_DEBUG_FLAG    (BIT(5))
+#define H264_P_IME_DONE_DEBUG_FLAG_M  (H264_P_IME_DONE_DEBUG_FLAG_V << H264_P_IME_DONE_DEBUG_FLAG_S)
+#define H264_P_IME_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_IME_DONE_DEBUG_FLAG_S  5
+/** H264_P_GET_ORI_DONE_DEBUG_FLAG : RO; bitpos: [6]; default: 0;
+ *  Represents p get origin done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_GET_ORI_DONE_DEBUG_FLAG    (BIT(6))
+#define H264_P_GET_ORI_DONE_DEBUG_FLAG_M  (H264_P_GET_ORI_DONE_DEBUG_FLAG_V << H264_P_GET_ORI_DONE_DEBUG_FLAG_S)
+#define H264_P_GET_ORI_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_GET_ORI_DONE_DEBUG_FLAG_S  6
+/** H264_P_FME_DONE_DEBUG_FLAG : RO; bitpos: [7]; default: 0;
+ *  Represents p fme done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_FME_DONE_DEBUG_FLAG    (BIT(7))
+#define H264_P_FME_DONE_DEBUG_FLAG_M  (H264_P_FME_DONE_DEBUG_FLAG_V << H264_P_FME_DONE_DEBUG_FLAG_S)
+#define H264_P_FME_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_FME_DONE_DEBUG_FLAG_S  7
+/** H264_P_FETCH_DONE_DEBUG_FLAG : RO; bitpos: [8]; default: 0;
+ *  Represents p fetch done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_FETCH_DONE_DEBUG_FLAG    (BIT(8))
+#define H264_P_FETCH_DONE_DEBUG_FLAG_M  (H264_P_FETCH_DONE_DEBUG_FLAG_V << H264_P_FETCH_DONE_DEBUG_FLAG_S)
+#define H264_P_FETCH_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_FETCH_DONE_DEBUG_FLAG_S  8
+/** H264_P_DB_DONE_DEBUG_FLAG : RO; bitpos: [9]; default: 0;
+ *  Represents p deblocking done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_DB_DONE_DEBUG_FLAG    (BIT(9))
+#define H264_P_DB_DONE_DEBUG_FLAG_M  (H264_P_DB_DONE_DEBUG_FLAG_V << H264_P_DB_DONE_DEBUG_FLAG_S)
+#define H264_P_DB_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_DB_DONE_DEBUG_FLAG_S  9
+/** H264_P_BS_BUF_DONE_DEBUG_FLAG : RO; bitpos: [10]; default: 0;
+ *  Represents p bitstream buffer done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_BS_BUF_DONE_DEBUG_FLAG    (BIT(10))
+#define H264_P_BS_BUF_DONE_DEBUG_FLAG_M  (H264_P_BS_BUF_DONE_DEBUG_FLAG_V << H264_P_BS_BUF_DONE_DEBUG_FLAG_S)
+#define H264_P_BS_BUF_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_BS_BUF_DONE_DEBUG_FLAG_S  10
+/** H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG : RO; bitpos: [11]; default: 0;
+ *  Represents dma move 2 ref mb line done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG    (BIT(11))
+#define H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_M  (H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_V << H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_S)
+#define H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_S  11
+/** H264_I_P_I_CMP_DONE_DEBUG_FLAG : RO; bitpos: [12]; default: 0;
+ *  Represents I p_i_cmp done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_P_I_CMP_DONE_DEBUG_FLAG    (BIT(12))
+#define H264_I_P_I_CMP_DONE_DEBUG_FLAG_M  (H264_I_P_I_CMP_DONE_DEBUG_FLAG_V << H264_I_P_I_CMP_DONE_DEBUG_FLAG_S)
+#define H264_I_P_I_CMP_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_P_I_CMP_DONE_DEBUG_FLAG_S  12
+/** H264_I_MOVE_ORI_DONE_DEBUG_FLAG : RO; bitpos: [13]; default: 0;
+ *  Represents I move origin done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_MOVE_ORI_DONE_DEBUG_FLAG    (BIT(13))
+#define H264_I_MOVE_ORI_DONE_DEBUG_FLAG_M  (H264_I_MOVE_ORI_DONE_DEBUG_FLAG_V << H264_I_MOVE_ORI_DONE_DEBUG_FLAG_S)
+#define H264_I_MOVE_ORI_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_MOVE_ORI_DONE_DEBUG_FLAG_S  13
+/** H264_I_GET_ORI_DONE_DEBUG_FLAG : RO; bitpos: [14]; default: 0;
+ *  Represents I get origin done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_GET_ORI_DONE_DEBUG_FLAG    (BIT(14))
+#define H264_I_GET_ORI_DONE_DEBUG_FLAG_M  (H264_I_GET_ORI_DONE_DEBUG_FLAG_V << H264_I_GET_ORI_DONE_DEBUG_FLAG_S)
+#define H264_I_GET_ORI_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_GET_ORI_DONE_DEBUG_FLAG_S  14
+/** H264_I_EC_DONE_DEBUG_FLAG : RO; bitpos: [15]; default: 0;
+ *  Represents I encoder done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_EC_DONE_DEBUG_FLAG    (BIT(15))
+#define H264_I_EC_DONE_DEBUG_FLAG_M  (H264_I_EC_DONE_DEBUG_FLAG_V << H264_I_EC_DONE_DEBUG_FLAG_S)
+#define H264_I_EC_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_EC_DONE_DEBUG_FLAG_S  15
+/** H264_I_DB_DONE_DEBUG_FLAG : RO; bitpos: [16]; default: 0;
+ *  Represents I deblocking done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_DB_DONE_DEBUG_FLAG    (BIT(16))
+#define H264_I_DB_DONE_DEBUG_FLAG_M  (H264_I_DB_DONE_DEBUG_FLAG_V << H264_I_DB_DONE_DEBUG_FLAG_S)
+#define H264_I_DB_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_DB_DONE_DEBUG_FLAG_S  16
+/** H264_I_BS_BUF_DONE_DEBUG_FLAG : RO; bitpos: [17]; default: 0;
+ *  Represents I bitstream buffer done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_BS_BUF_DONE_DEBUG_FLAG    (BIT(17))
+#define H264_I_BS_BUF_DONE_DEBUG_FLAG_M  (H264_I_BS_BUF_DONE_DEBUG_FLAG_V << H264_I_BS_BUF_DONE_DEBUG_FLAG_S)
+#define H264_I_BS_BUF_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_BS_BUF_DONE_DEBUG_FLAG_S  17
+
+/** H264_DATE_REG register
+ *  Version control register
+ */
+#define H264_DATE_REG (DR_REG_H264_BASE + 0xf0)
+/** H264_DATE : R/W; bitpos: [27:0]; default: 37823232;
+ *  Configures the version.
+ */
+#define H264_DATE    0x0FFFFFFFU
+#define H264_DATE_M  (H264_DATE_V << H264_DATE_S)
+#define H264_DATE_V  0x0FFFFFFFU
+#define H264_DATE_S  0
+
+/** H264_A_ORI_CONF_REG register
+ *  Video A original picture configuration register.
+ */
+#define H264_A_ORI_CONF_REG (DR_REG_H264_BASE + 0xf4)
+/** H264_A_ORI_COLOR_SPACE : R/W; bitpos: [2:0]; default: 4;
+ *  Configures video A original picture color space.
+ *  0: RGB888
+ *  1: RGB565
+ *  2: YUV444
+ *  3: YUV422
+ *  4: YUV420
+ *  5: GRAY
+ *  Others: Invalid
+ */
+#define H264_A_ORI_COLOR_SPACE    0x00000007U
+#define H264_A_ORI_COLOR_SPACE_M  (H264_A_ORI_COLOR_SPACE_V << H264_A_ORI_COLOR_SPACE_S)
+#define H264_A_ORI_COLOR_SPACE_V  0x00000007U
+#define H264_A_ORI_COLOR_SPACE_S  0
+
+/** H264_B_ORI_CONF_REG register
+ *  Video B original picture configuration register.
+ */
+#define H264_B_ORI_CONF_REG (DR_REG_H264_BASE + 0xf8)
+/** H264_B_ORI_COLOR_SPACE : R/W; bitpos: [2:0]; default: 4;
+ *  Configures video B original picture color space.
+ *  0: RGB888
+ *  1: RGB565
+ *  2: YUV444
+ *  3: YUV422
+ *  4: YUV420
+ *  5: GRAY
+ *  Others: Invalid
+ */
+#define H264_B_ORI_COLOR_SPACE    0x00000007U
+#define H264_B_ORI_COLOR_SPACE_M  (H264_B_ORI_COLOR_SPACE_V << H264_B_ORI_COLOR_SPACE_S)
+#define H264_B_ORI_COLOR_SPACE_V  0x00000007U
+#define H264_B_ORI_COLOR_SPACE_S  0
+
+/** H264_ORI_DEBUG_CONF_REG register
+ *  Original picture debug configuration register.
+ */
+#define H264_ORI_DEBUG_CONF_REG (DR_REG_H264_BASE + 0xfc)
+/** H264_DBG_REPLACE_ORI_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to replace original picture pixels.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_ORI_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_ORI_DATA_EN_M  (H264_DBG_REPLACE_ORI_DATA_EN_V << H264_DBG_REPLACE_ORI_DATA_EN_S)
+#define H264_DBG_REPLACE_ORI_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_ORI_DATA_EN_S  0
+/** H264_DBG_REPLACE_ORI_DATA : R/W; bitpos: [24:1]; default: 0;
+ *  Configures original picture pixels to be replaced. When the original picture color
+ *  space is RGB, byte0~2 is BGR. When the original picture color space is YUV, byte0~2
+ *  is VUY. When the original picture color space is GRAY, byte0 is GRAY.
+ */
+#define H264_DBG_REPLACE_ORI_DATA    0x00FFFFFFU
+#define H264_DBG_REPLACE_ORI_DATA_M  (H264_DBG_REPLACE_ORI_DATA_V << H264_DBG_REPLACE_ORI_DATA_S)
+#define H264_DBG_REPLACE_ORI_DATA_V  0x00FFFFFFU
+#define H264_DBG_REPLACE_ORI_DATA_S  1
+
+/** H264_MV_MERGE_DEBUG_CONF_REG register
+ *  Original picture debug configuration register.
+ */
+#define H264_MV_MERGE_DEBUG_CONF_REG (DR_REG_H264_BASE + 0x100)
+/** H264_DBG_REPLACE_MV_MERGE_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to replace mv merge data.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_MV_MERGE_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_MV_MERGE_DATA_EN_M  (H264_DBG_REPLACE_MV_MERGE_DATA_EN_V << H264_DBG_REPLACE_MV_MERGE_DATA_EN_S)
+#define H264_DBG_REPLACE_MV_MERGE_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_MV_MERGE_DATA_EN_S  0
+/** H264_DBG_REPLACE_MV_MERGE_DATA : R/W; bitpos: [8:1]; default: 0;
+ *  Configures mv merge data to be replaced.
+ */
+#define H264_DBG_REPLACE_MV_MERGE_DATA    0x000000FFU
+#define H264_DBG_REPLACE_MV_MERGE_DATA_M  (H264_DBG_REPLACE_MV_MERGE_DATA_V << H264_DBG_REPLACE_MV_MERGE_DATA_S)
+#define H264_DBG_REPLACE_MV_MERGE_DATA_V  0x000000FFU
+#define H264_DBG_REPLACE_MV_MERGE_DATA_S  1
+
+/** H264_BS_DEBUG_CONG_REG register
+ *  Encode bitstream debug configuration register
+ */
+#define H264_BS_DEBUG_CONG_REG (DR_REG_H264_BASE + 0x104)
+/** H264_DBG_REPLACE_WR_BS_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to replace bs data.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_WR_BS_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_WR_BS_DATA_EN_M  (H264_DBG_REPLACE_WR_BS_DATA_EN_V << H264_DBG_REPLACE_WR_BS_DATA_EN_S)
+#define H264_DBG_REPLACE_WR_BS_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_WR_BS_DATA_EN_S  0
+/** H264_DBG_REPLACE_WR_BS_DATA : R/W; bitpos: [8:1]; default: 0;
+ *  Configures bs data to be replaced
+ */
+#define H264_DBG_REPLACE_WR_BS_DATA    0x000000FFU
+#define H264_DBG_REPLACE_WR_BS_DATA_M  (H264_DBG_REPLACE_WR_BS_DATA_V << H264_DBG_REPLACE_WR_BS_DATA_S)
+#define H264_DBG_REPLACE_WR_BS_DATA_V  0x000000FFU
+#define H264_DBG_REPLACE_WR_BS_DATA_S  1
+
+/** H264_DB_WR_TEMP_DEBUG_CONG_REG register
+ *  Deblocking filter write temp debug configuration register
+ */
+#define H264_DB_WR_TEMP_DEBUG_CONG_REG (DR_REG_H264_BASE + 0x108)
+/** H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure deblocking filter whether or not to replace write temp data.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN_M  (H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN_V << H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN_S)
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN_S  0
+/** H264_DBG_REPLACE_WR_DB_TEMP_DATA : R/W; bitpos: [24:1]; default: 0;
+ *  Configure deblocking filter write temp data to be replaced.byte0~2 is VUY
+ */
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA    0x00FFFFFFU
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_M  (H264_DBG_REPLACE_WR_DB_TEMP_DATA_V << H264_DBG_REPLACE_WR_DB_TEMP_DATA_S)
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_V  0x00FFFFFFU
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_S  1
+
+/** H264_DB_RD_TEMP_DEBUG_CONG_REG register
+ *  Deblocking filter read temp debug configuration register
+ */
+#define H264_DB_RD_TEMP_DEBUG_CONG_REG (DR_REG_H264_BASE + 0x10c)
+/** H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure deblocking filter whether or not to replace read temp data.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN_M  (H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN_V << H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN_S)
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN_S  0
+/** H264_DBG_REPLACE_RD_DB_TEMP_DATA : R/W; bitpos: [24:1]; default: 0;
+ *  Configure deblocking filter read temp data to be replaced.byte0~2 is VUY
+ */
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA    0x00FFFFFFU
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_M  (H264_DBG_REPLACE_RD_DB_TEMP_DATA_V << H264_DBG_REPLACE_RD_DB_TEMP_DATA_S)
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_V  0x00FFFFFFU
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_S  1
+
+/** H264_DB_WR_DEBUG_CONG_REG register
+ *  Deblocking filter final data debug configuration register
+ */
+#define H264_DB_WR_DEBUG_CONG_REG (DR_REG_H264_BASE + 0x110)
+/** H264_DBG_REPLACE_WR_DB_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure deblocking filter whether or not to replace write data.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_WR_DB_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_WR_DB_DATA_EN_M  (H264_DBG_REPLACE_WR_DB_DATA_EN_V << H264_DBG_REPLACE_WR_DB_DATA_EN_S)
+#define H264_DBG_REPLACE_WR_DB_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_WR_DB_DATA_EN_S  0
+/** H264_DBG_REPLACE_WR_DB_DATA : R/W; bitpos: [24:1]; default: 0;
+ *  Configure deblocking filter write data to be replaced.byte0~2 is VUY
+ */
+#define H264_DBG_REPLACE_WR_DB_DATA    0x00FFFFFFU
+#define H264_DBG_REPLACE_WR_DB_DATA_M  (H264_DBG_REPLACE_WR_DB_DATA_V << H264_DBG_REPLACE_WR_DB_DATA_S)
+#define H264_DBG_REPLACE_WR_DB_DATA_V  0x00FFFFFFU
+#define H264_DBG_REPLACE_WR_DB_DATA_S  1
+
+/** H264_REF_DEBUG_CONG_REG register
+ *  Deblocking filter final data debug configuration register
+ */
+#define H264_REF_DEBUG_CONG_REG (DR_REG_H264_BASE + 0x114)
+/** H264_DBG_REPLACE_REF_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether to replace reference picture pixels.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_REF_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_REF_DATA_EN_M  (H264_DBG_REPLACE_REF_DATA_EN_V << H264_DBG_REPLACE_REF_DATA_EN_S)
+#define H264_DBG_REPLACE_REF_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_REF_DATA_EN_S  0
+/** H264_DBG_REPLACE_REF_DATA : R/W; bitpos: [24:1]; default: 0;
+ *  Configure reference picture pixels to be replaced.byte0~2 is VUY
+ */
+#define H264_DBG_REPLACE_REF_DATA    0x00FFFFFFU
+#define H264_DBG_REPLACE_REF_DATA_M  (H264_DBG_REPLACE_REF_DATA_V << H264_DBG_REPLACE_REF_DATA_S)
+#define H264_DBG_REPLACE_REF_DATA_V  0x00FFFFFFU
+#define H264_DBG_REPLACE_REF_DATA_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/h264_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/h264_struct.h
new file mode 100644
index 0000000000..81d4832dec
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/h264_struct.h
@@ -0,0 +1,2127 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of sys_ctrl register
+ *  H264 system level control register.
+ */
+typedef union {
+    struct {
+        /** frame_start : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to start encoding one frame.
+         *  0: Invalid. No effect
+         *  1: Start encoding one frame
+         */
+        uint32_t frame_start:1;
+        /** dma_move_start : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to start moving reference data from external mem.
+         *  0: Invalid. No effect
+         *  1: H264 start moving two MB lines of reference frame from external mem to internal
+         *  mem
+         */
+        uint32_t dma_move_start:1;
+        /** frame_mode : R/W; bitpos: [2]; default: 0;
+         *  Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this
+         *  field must be set to 1 too.
+         *  0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA
+         *  1: Frame mode. Before every frame start, need reconfig reference frame DMA
+         */
+        uint32_t frame_mode:1;
+        /** sys_rst_pulse : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to reset H264 ip.
+         *  0: Invalid. No effect
+         *  1: Reset H264 ip
+         */
+        uint32_t sys_rst_pulse:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_sys_ctrl_reg_t;
+
+/** Type of gop_conf register
+ *  GOP related configuration register.
+ */
+typedef union {
+    struct {
+        /** dual_stream_mode : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable dual stream mode. When this field is set to 1,
+         *  H264_FRAME_MODE field must be set to 1 too.
+         *  0: Normal mode
+         *  1: Dual stream mode
+         */
+        uint32_t dual_stream_mode:1;
+        /** gop_num : R/W; bitpos: [8:1]; default: 0;
+         *  Configures the frame number of one GOP.
+         *  0: The frame number of one GOP is infinite
+         *  Others: Actual frame number of one GOP
+         */
+        uint32_t gop_num:8;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_gop_conf_reg_t;
+
+/** Type of a_sys_mb_res register
+ *  Video A horizontal and vertical MB resolution register.
+ */
+typedef union {
+    struct {
+        /** a_sys_total_mb_y : R/W; bitpos: [6:0]; default: 0;
+         *  Configures video A vertical MB resolution.
+         */
+        uint32_t a_sys_total_mb_y:7;
+        /** a_sys_total_mb_x : R/W; bitpos: [13:7]; default: 0;
+         *  Configures video A horizontal MB resolution.
+         */
+        uint32_t a_sys_total_mb_x:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} h264_a_sys_mb_res_reg_t;
+
+/** Type of a_sys_conf register
+ *  Video A system level configuration register.
+ */
+typedef union {
+    struct {
+        /** a_db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3;
+         *  Configures when to trigger  video A H264_DB_TMP_READY_INT. When the (MB number of
+         *  written db temp+1) is greater than this filed in first MB line, trigger
+         *  H264_DB_TMP_READY_INT. Min is 3.
+         */
+        uint32_t a_db_tmp_ready_trigger_mb_num:7;
+        /** a_rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4;
+         *  Configures when to trigger  video A H264_REC_READY_INT. When the MB line number of
+         *  generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT.
+         *  Min is 4.
+         */
+        uint32_t a_rec_ready_trigger_mb_lines:7;
+        /** a_intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0;
+         *  Configures video A intra cost offset when I MB compared with P MB.
+         */
+        uint32_t a_intra_cost_cmp_offset:16;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} h264_a_sys_conf_reg_t;
+
+/** Type of a_deci_score register
+ *  Video A luma and chroma MB decimate score Register.
+ */
+typedef union {
+    struct {
+        /** a_c_deci_score : R/W; bitpos: [9:0]; default: 0;
+         *  Configures video A chroma MB decimate score. When chroma score is smaller than it,
+         *  chroma decimate will be enable.
+         */
+        uint32_t a_c_deci_score:10;
+        /** a_l_deci_score : R/W; bitpos: [19:10]; default: 0;
+         *  Configures video A luma MB decimate score. When luma score is smaller than it, luma
+         *  decimate will be enable.
+         */
+        uint32_t a_l_deci_score:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_a_deci_score_reg_t;
+
+/** Type of a_deci_score_offset register
+ *  Video A luma and chroma MB decimate score offset Register.
+ */
+typedef union {
+    struct {
+        /** a_i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0;
+         *  Configures video A i16x16 MB decimate score offset. This offset will be added to
+         *  i16x16 MB score.
+         */
+        uint32_t a_i16x16_deci_score_offset:6;
+        /** a_i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0;
+         *  Configures video A I chroma MB decimate score offset. This offset will be added to
+         *  I chroma MB score.
+         */
+        uint32_t a_i_chroma_deci_score_offset:6;
+        /** a_p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0;
+         *  Configures video A p16x16 MB decimate score offset. This offset will be added to
+         *  p16x16 MB score.
+         */
+        uint32_t a_p16x16_deci_score_offset:6;
+        /** a_p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0;
+         *  Configures video A p chroma MB decimate score offset. This offset will be added to
+         *  p chroma MB score.
+         */
+        uint32_t a_p_chroma_deci_score_offset:6;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_a_deci_score_offset_reg_t;
+
+/** Type of a_rc_conf0 register
+ *  Video A rate control configuration register0.
+ */
+typedef union {
+    struct {
+        /** a_qp : R/W; bitpos: [5:0]; default: 0;
+         *  Configures video A frame level initial luma QP value.
+         */
+        uint32_t a_qp:6;
+        /** a_rate_ctrl_u : R/W; bitpos: [21:6]; default: 0;
+         *  Configures video A parameter U value. U = int((float) u << 8).
+         */
+        uint32_t a_rate_ctrl_u:16;
+        /** a_mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0;
+         *  Configures video A whether or not to open macro block rate ctrl.
+         *  1:Open the macro block rate ctrl
+         *  1:Close the macro block rate ctrl.
+         */
+        uint32_t a_mb_rate_ctrl_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} h264_a_rc_conf0_reg_t;
+
+/** Type of a_rc_conf1 register
+ *  Video A rate control configuration register1.
+ */
+typedef union {
+    struct {
+        /** a_chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0;
+         *  Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma
+         *  QP(after map) + reg_chroma_dc_qp_delta.
+         */
+        uint32_t a_chroma_dc_qp_delta:3;
+        /** a_chroma_qp_delta : R/W; bitpos: [6:3]; default: 0;
+         *  Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma
+         *  QP + reg_chroma_qp_delta.
+         */
+        uint32_t a_chroma_qp_delta:4;
+        /** a_qp_min : R/W; bitpos: [12:7]; default: 0;
+         *  Configures video A allowed luma QP min value.
+         */
+        uint32_t a_qp_min:6;
+        /** a_qp_max : R/W; bitpos: [18:13]; default: 0;
+         *  Configures video A allowed luma QP max value.
+         */
+        uint32_t a_qp_max:6;
+        /** a_mad_frame_pred : R/W; bitpos: [30:19]; default: 0;
+         *  Configures vdieo A frame level predicted MB MAD value.
+         */
+        uint32_t a_mad_frame_pred:12;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} h264_a_rc_conf1_reg_t;
+
+/** Type of a_db_bypass register
+ *  Video A Deblocking bypass register
+ */
+typedef union {
+    struct {
+        /** a_bypass_db_filter : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to bypass video A deblcoking filter.
+         *  0: Open the deblock filter
+         *  1: Close the deblock filter
+         */
+        uint32_t a_bypass_db_filter:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} h264_a_db_bypass_reg_t;
+
+/** Type of a_roi_region0 register
+ *  Video A H264 ROI region0 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region0_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 0 in Video A.
+         */
+        uint32_t a_roi_region0_x:7;
+        /** a_roi_region0_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 0 in Video A.
+         */
+        uint32_t a_roi_region0_y:7;
+        /** a_roi_region0_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 0 in
+         *  Video A.
+         */
+        uint32_t a_roi_region0_x_len:7;
+        /** a_roi_region0_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 0 in
+         *  Video A.
+         */
+        uint32_t a_roi_region0_y_len:7;
+        /** a_roi_region0_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 0 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region0_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region0_reg_t;
+
+/** Type of a_roi_region1 register
+ *  Video A H264 ROI region1 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region1_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 1 in Video A.
+         */
+        uint32_t a_roi_region1_x:7;
+        /** a_roi_region1_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 1 in Video A.
+         */
+        uint32_t a_roi_region1_y:7;
+        /** a_roi_region1_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 1 in
+         *  Video A.
+         */
+        uint32_t a_roi_region1_x_len:7;
+        /** a_roi_region1_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 1 in
+         *  Video A.
+         */
+        uint32_t a_roi_region1_y_len:7;
+        /** a_roi_region1_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 1 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region1_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region1_reg_t;
+
+/** Type of a_roi_region2 register
+ *  Video A H264 ROI region2 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region2_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 2 in Video A.
+         */
+        uint32_t a_roi_region2_x:7;
+        /** a_roi_region2_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 2 in Video A.
+         */
+        uint32_t a_roi_region2_y:7;
+        /** a_roi_region2_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 2 in
+         *  Video A.
+         */
+        uint32_t a_roi_region2_x_len:7;
+        /** a_roi_region2_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 2 in
+         *  Video A.
+         */
+        uint32_t a_roi_region2_y_len:7;
+        /** a_roi_region2_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 2 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region2_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region2_reg_t;
+
+/** Type of a_roi_region3 register
+ *  Video A H264 ROI region3 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region3_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 3 in Video A.
+         */
+        uint32_t a_roi_region3_x:7;
+        /** a_roi_region3_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 3 in Video A.
+         */
+        uint32_t a_roi_region3_y:7;
+        /** a_roi_region3_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 3 in
+         *  video A.
+         */
+        uint32_t a_roi_region3_x_len:7;
+        /** a_roi_region3_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 3 in
+         *  video A.
+         */
+        uint32_t a_roi_region3_y_len:7;
+        /** a_roi_region3_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 3 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region3_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region3_reg_t;
+
+/** Type of a_roi_region4 register
+ *  Video A H264 ROI region4 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region4_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 4 in Video A.
+         */
+        uint32_t a_roi_region4_x:7;
+        /** a_roi_region4_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 4 in Video A.
+         */
+        uint32_t a_roi_region4_y:7;
+        /** a_roi_region4_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 4 in
+         *  video A.
+         */
+        uint32_t a_roi_region4_x_len:7;
+        /** a_roi_region4_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 4 in
+         *  video A.
+         */
+        uint32_t a_roi_region4_y_len:7;
+        /** a_roi_region4_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 4 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region4_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region4_reg_t;
+
+/** Type of a_roi_region5 register
+ *  Video A H264 ROI region5 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region5_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontial start macroblocks of region 5 video A.
+         */
+        uint32_t a_roi_region5_x:7;
+        /** a_roi_region5_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 5 video A.
+         */
+        uint32_t a_roi_region5_y:7;
+        /** a_roi_region5_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 5
+         *  video A.
+         */
+        uint32_t a_roi_region5_x_len:7;
+        /** a_roi_region5_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 5 in
+         *  video A.
+         */
+        uint32_t a_roi_region5_y_len:7;
+        /** a_roi_region5_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 5 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region5_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region5_reg_t;
+
+/** Type of a_roi_region6 register
+ *  Video A H264 ROI region6 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region6_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontial start macroblocks of region 6 video A.
+         */
+        uint32_t a_roi_region6_x:7;
+        /** a_roi_region6_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 6 in video A.
+         */
+        uint32_t a_roi_region6_y:7;
+        /** a_roi_region6_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 6 in
+         *  video A.
+         */
+        uint32_t a_roi_region6_x_len:7;
+        /** a_roi_region6_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 6 in
+         *  video A.
+         */
+        uint32_t a_roi_region6_y_len:7;
+        /** a_roi_region6_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 6 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region6_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region6_reg_t;
+
+/** Type of a_roi_region7 register
+ *  Video A H264 ROI region7 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region7_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 7 in video A.
+         */
+        uint32_t a_roi_region7_x:7;
+        /** a_roi_region7_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 7 in video A.
+         */
+        uint32_t a_roi_region7_y:7;
+        /** a_roi_region7_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 7 in
+         *  video A.
+         */
+        uint32_t a_roi_region7_x_len:7;
+        /** a_roi_region7_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 7 in
+         *  video A.
+         */
+        uint32_t a_roi_region7_y_len:7;
+        /** a_roi_region7_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 7 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region7_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region7_reg_t;
+
+/** Type of a_roi_region0_3_qp register
+ *  Video A H264 ROI region0, region1,region2,region3 QP register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region0_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 ROI region0 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region0_qp:7;
+        /** a_roi_region1_qp : R/W; bitpos: [13:7]; default: 0;
+         *  Configure H264 ROI region1 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region1_qp:7;
+        /** a_roi_region2_qp : R/W; bitpos: [20:14]; default: 0;
+         *  Configure H264 ROI region2 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region2_qp:7;
+        /** a_roi_region3_qp : R/W; bitpos: [27:21]; default: 0;
+         *  Configure H264 ROI region3 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region3_qp:7;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_a_roi_region0_3_qp_reg_t;
+
+/** Type of a_roi_region4_7_qp register
+ *  Video A H264 ROI region4, region5,region6,region7 QP register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region4_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 ROI region4 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region4_qp:7;
+        /** a_roi_region5_qp : R/W; bitpos: [13:7]; default: 0;
+         *  Configure H264 ROI region5 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region5_qp:7;
+        /** a_roi_region6_qp : R/W; bitpos: [20:14]; default: 0;
+         *  Configure H264 ROI region6 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region6_qp:7;
+        /** a_roi_region7_qp : R/W; bitpos: [27:21]; default: 0;
+         *  Configure H264 ROI region7 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region7_qp:7;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_a_roi_region4_7_qp_reg_t;
+
+/** Type of a_no_roi_region_qp_offset register
+ *  Video A H264 no roi region QP register.
+ */
+typedef union {
+    struct {
+        /** a_no_roi_region_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 no region qp in video A, delta qp.
+         */
+        uint32_t a_no_roi_region_qp:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_a_no_roi_region_qp_offset_reg_t;
+
+/** Type of a_roi_config register
+ *  Video A H264 ROI configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether or not to enable ROI in video A.
+         *  0:not enable ROI
+         *  1:enable ROI.
+         */
+        uint32_t a_roi_en:1;
+        /** a_roi_mode : R/W; bitpos: [1]; default: 0;
+         *  Configure the mode of ROI in video A.
+         *  0:fixed qp
+         *  1:delta qp.
+         */
+        uint32_t a_roi_mode:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} h264_a_roi_config_reg_t;
+
+/** Type of b_sys_mb_res register
+ *  Video B horizontal and vertical MB resolution register.
+ */
+typedef union {
+    struct {
+        /** b_sys_total_mb_y : R/W; bitpos: [6:0]; default: 0;
+         *  Configures video B vertical MB resolution.
+         */
+        uint32_t b_sys_total_mb_y:7;
+        /** b_sys_total_mb_x : R/W; bitpos: [13:7]; default: 0;
+         *  Configures video B horizontal MB resolution.
+         */
+        uint32_t b_sys_total_mb_x:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} h264_b_sys_mb_res_reg_t;
+
+/** Type of b_sys_conf register
+ *  Video B system level configuration register.
+ */
+typedef union {
+    struct {
+        /** b_db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3;
+         *  Configures when to trigger  video B H264_DB_TMP_READY_INT. When the (MB number of
+         *  written db temp+1) is greater than this filed in first MB line, trigger
+         *  H264_DB_TMP_READY_INT. Min is 3.
+         */
+        uint32_t b_db_tmp_ready_trigger_mb_num:7;
+        /** b_rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4;
+         *  Configures when to trigger  video B H264_REC_READY_INT. When the MB line number of
+         *  generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT.
+         *  Min is 4.
+         */
+        uint32_t b_rec_ready_trigger_mb_lines:7;
+        /** b_intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0;
+         *  Configures video B intra cost offset when I MB compared with P MB.
+         */
+        uint32_t b_intra_cost_cmp_offset:16;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} h264_b_sys_conf_reg_t;
+
+/** Type of b_deci_score register
+ *  Video B luma and chroma MB decimate score Register.
+ */
+typedef union {
+    struct {
+        /** b_c_deci_score : R/W; bitpos: [9:0]; default: 0;
+         *  Configures video B chroma MB decimate score. When chroma score is smaller than it,
+         *  chroma decimate will be enable.
+         */
+        uint32_t b_c_deci_score:10;
+        /** b_l_deci_score : R/W; bitpos: [19:10]; default: 0;
+         *  Configures video B luma MB decimate score. When luma score is smaller than it, luma
+         *  decimate will be enable.
+         */
+        uint32_t b_l_deci_score:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_b_deci_score_reg_t;
+
+/** Type of b_deci_score_offset register
+ *  Video B luma and chroma MB decimate score offset Register.
+ */
+typedef union {
+    struct {
+        /** b_i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0;
+         *  Configures video B i16x16 MB decimate score offset. This offset will be added to
+         *  i16x16 MB score.
+         */
+        uint32_t b_i16x16_deci_score_offset:6;
+        /** b_i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0;
+         *  Configures video B I chroma MB decimate score offset. This offset will be added to
+         *  I chroma MB score.
+         */
+        uint32_t b_i_chroma_deci_score_offset:6;
+        /** b_p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0;
+         *  Configures video B p16x16 MB decimate score offset. This offset will be added to
+         *  p16x16 MB score.
+         */
+        uint32_t b_p16x16_deci_score_offset:6;
+        /** b_p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0;
+         *  Configures video B p chroma MB decimate score offset. This offset will be added to
+         *  p chroma MB score.
+         */
+        uint32_t b_p_chroma_deci_score_offset:6;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_b_deci_score_offset_reg_t;
+
+/** Type of b_rc_conf0 register
+ *  Video B rate control configuration register0.
+ */
+typedef union {
+    struct {
+        /** b_qp : R/W; bitpos: [5:0]; default: 0;
+         *  Configures video B frame level initial luma QP value.
+         */
+        uint32_t b_qp:6;
+        /** b_rate_ctrl_u : R/W; bitpos: [21:6]; default: 0;
+         *  Configures video B parameter U value. U = int((float) u << 8).
+         */
+        uint32_t b_rate_ctrl_u:16;
+        /** b_mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0;
+         *  Configures video A whether or not to open macro block rate ctrl.
+         *  1:Open the macro block rate ctrl
+         *  1:Close the macro block rate ctrl.
+         */
+        uint32_t b_mb_rate_ctrl_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} h264_b_rc_conf0_reg_t;
+
+/** Type of b_rc_conf1 register
+ *  Video B rate control configuration register1.
+ */
+typedef union {
+    struct {
+        /** b_chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0;
+         *  Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma
+         *  QP(after map) + reg_chroma_dc_qp_delta.
+         */
+        uint32_t b_chroma_dc_qp_delta:3;
+        /** b_chroma_qp_delta : R/W; bitpos: [6:3]; default: 0;
+         *  Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma
+         *  QP + reg_chroma_qp_delta.
+         */
+        uint32_t b_chroma_qp_delta:4;
+        /** b_qp_min : R/W; bitpos: [12:7]; default: 0;
+         *  Configures video B allowed luma QP min value.
+         */
+        uint32_t b_qp_min:6;
+        /** b_qp_max : R/W; bitpos: [18:13]; default: 0;
+         *  Configures video B allowed luma QP max value.
+         */
+        uint32_t b_qp_max:6;
+        /** b_mad_frame_pred : R/W; bitpos: [30:19]; default: 0;
+         *  Configures vdieo B frame level predicted MB MAD value.
+         */
+        uint32_t b_mad_frame_pred:12;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} h264_b_rc_conf1_reg_t;
+
+/** Type of b_db_bypass register
+ *  Video B Deblocking bypass register
+ */
+typedef union {
+    struct {
+        /** b_bypass_db_filter : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to bypass video B deblcoking filter.
+         *  0: Open the deblock filter
+         *  1: Close the deblock filter
+         */
+        uint32_t b_bypass_db_filter:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} h264_b_db_bypass_reg_t;
+
+/** Type of b_roi_region0 register
+ *  Video B H264 ROI region0 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region0_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 0 in Video B.
+         */
+        uint32_t b_roi_region0_x:7;
+        /** b_roi_region0_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 0 in Video B.
+         */
+        uint32_t b_roi_region0_y:7;
+        /** b_roi_region0_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 0 in
+         *  Video B.
+         */
+        uint32_t b_roi_region0_x_len:7;
+        /** b_roi_region0_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 0 in
+         *  Video B.
+         */
+        uint32_t b_roi_region0_y_len:7;
+        /** b_roi_region0_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 0 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region0_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region0_reg_t;
+
+/** Type of b_roi_region1 register
+ *  Video B H264 ROI region1 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region1_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 1 in Video B.
+         */
+        uint32_t b_roi_region1_x:7;
+        /** b_roi_region1_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 1 in Video B.
+         */
+        uint32_t b_roi_region1_y:7;
+        /** b_roi_region1_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 1 in
+         *  Video B.
+         */
+        uint32_t b_roi_region1_x_len:7;
+        /** b_roi_region1_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 1 in
+         *  Video B.
+         */
+        uint32_t b_roi_region1_y_len:7;
+        /** b_roi_region1_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 1 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region1_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region1_reg_t;
+
+/** Type of b_roi_region2 register
+ *  Video B H264 ROI region2 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region2_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 2 in Video B.
+         */
+        uint32_t b_roi_region2_x:7;
+        /** b_roi_region2_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 2 in Video B.
+         */
+        uint32_t b_roi_region2_y:7;
+        /** b_roi_region2_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 2 in
+         *  Video B.
+         */
+        uint32_t b_roi_region2_x_len:7;
+        /** b_roi_region2_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 2 in
+         *  Video B.
+         */
+        uint32_t b_roi_region2_y_len:7;
+        /** b_roi_region2_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 2 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region2_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region2_reg_t;
+
+/** Type of b_roi_region3 register
+ *  Video B H264 ROI region3 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region3_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 3 in Video B.
+         */
+        uint32_t b_roi_region3_x:7;
+        /** b_roi_region3_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 3 in Video B.
+         */
+        uint32_t b_roi_region3_y:7;
+        /** b_roi_region3_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 3 in
+         *  video B.
+         */
+        uint32_t b_roi_region3_x_len:7;
+        /** b_roi_region3_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 3 in
+         *  video B.
+         */
+        uint32_t b_roi_region3_y_len:7;
+        /** b_roi_region3_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 3 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region3_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region3_reg_t;
+
+/** Type of b_roi_region4 register
+ *  Video B H264 ROI region4 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region4_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 4 in Video B.
+         */
+        uint32_t b_roi_region4_x:7;
+        /** b_roi_region4_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 4 in Video B.
+         */
+        uint32_t b_roi_region4_y:7;
+        /** b_roi_region4_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 4 in
+         *  video B.
+         */
+        uint32_t b_roi_region4_x_len:7;
+        /** b_roi_region4_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 4 in
+         *  video B.
+         */
+        uint32_t b_roi_region4_y_len:7;
+        /** b_roi_region4_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 4 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region4_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region4_reg_t;
+
+/** Type of b_roi_region5 register
+ *  Video B H264 ROI region5 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region5_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontial start macroblocks of region 5 video B.
+         */
+        uint32_t b_roi_region5_x:7;
+        /** b_roi_region5_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 5 video B.
+         */
+        uint32_t b_roi_region5_y:7;
+        /** b_roi_region5_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 5
+         *  video B.
+         */
+        uint32_t b_roi_region5_x_len:7;
+        /** b_roi_region5_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 5 in
+         *  video B.
+         */
+        uint32_t b_roi_region5_y_len:7;
+        /** b_roi_region5_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 5 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region5_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region5_reg_t;
+
+/** Type of b_roi_region6 register
+ *  Video B H264 ROI region6 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region6_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontial start macroblocks of region 6 video B.
+         */
+        uint32_t b_roi_region6_x:7;
+        /** b_roi_region6_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 6 in video B.
+         */
+        uint32_t b_roi_region6_y:7;
+        /** b_roi_region6_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 6 in
+         *  video B.
+         */
+        uint32_t b_roi_region6_x_len:7;
+        /** b_roi_region6_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 6 in
+         *  video B.
+         */
+        uint32_t b_roi_region6_y_len:7;
+        /** b_roi_region6_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 6 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region6_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region6_reg_t;
+
+/** Type of b_roi_region7 register
+ *  Video B H264 ROI region7 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region7_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 7 in video B.
+         */
+        uint32_t b_roi_region7_x:7;
+        /** b_roi_region7_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 7 in video B.
+         */
+        uint32_t b_roi_region7_y:7;
+        /** b_roi_region7_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 7 in
+         *  video B.
+         */
+        uint32_t b_roi_region7_x_len:7;
+        /** b_roi_region7_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 7 in
+         *  video B.
+         */
+        uint32_t b_roi_region7_y_len:7;
+        /** b_roi_region7_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 7 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region7_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region7_reg_t;
+
+/** Type of b_roi_region0_3_qp register
+ *  Video B H264 ROI region0, region1,region2,region3 QP register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region0_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 ROI region0 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region0_qp:7;
+        /** b_roi_region1_qp : R/W; bitpos: [13:7]; default: 0;
+         *  Configure H264 ROI region1 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region1_qp:7;
+        /** b_roi_region2_qp : R/W; bitpos: [20:14]; default: 0;
+         *  Configure H264 ROI region2 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region2_qp:7;
+        /** b_roi_region3_qp : R/W; bitpos: [27:21]; default: 0;
+         *  Configure H264 ROI region3 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region3_qp:7;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_b_roi_region0_3_qp_reg_t;
+
+/** Type of b_roi_region4_7_qp register
+ *  Video B H264 ROI region4, region5,region6,region7 QP register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region4_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 ROI region4 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region4_qp:7;
+        /** b_roi_region5_qp : R/W; bitpos: [13:7]; default: 0;
+         *  Configure H264 ROI region5 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region5_qp:7;
+        /** b_roi_region6_qp : R/W; bitpos: [20:14]; default: 0;
+         *  Configure H264 ROI region6 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region6_qp:7;
+        /** b_roi_region7_qp : R/W; bitpos: [27:21]; default: 0;
+         *  Configure H264 ROI region7 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region7_qp:7;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_b_roi_region4_7_qp_reg_t;
+
+/** Type of b_no_roi_region_qp_offset register
+ *  Video B H264 no roi region QP register.
+ */
+typedef union {
+    struct {
+        /** b_no_roi_region_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 no region qp in video B, delta qp.
+         */
+        uint32_t b_no_roi_region_qp:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_b_no_roi_region_qp_offset_reg_t;
+
+/** Type of b_roi_config register
+ *  Video B H264 ROI configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether or not to enable ROI in video B.
+         *  0:not enable ROI
+         *  1:enable ROI.
+         */
+        uint32_t b_roi_en:1;
+        /** b_roi_mode : R/W; bitpos: [1]; default: 0;
+         *  Configure the mode of ROI in video B.
+         *  0:fixed qp
+         *  1:delta qp.
+         */
+        uint32_t b_roi_mode:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} h264_b_roi_config_reg_t;
+
+/** Type of slice_header_remain register
+ *  Frame Slice Header remain bit register.
+ */
+typedef union {
+    struct {
+        /** slice_remain_bitlength : R/W; bitpos: [2:0]; default: 0;
+         *  Configures Slice Header remain bit number
+         */
+        uint32_t slice_remain_bitlength:3;
+        /** slice_remain_bit : R/W; bitpos: [10:3]; default: 0;
+         *  Configures Slice Header remain bit
+         */
+        uint32_t slice_remain_bit:8;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_slice_header_remain_reg_t;
+
+/** Type of slice_header_byte_length register
+ *  Frame Slice Header byte length register.
+ */
+typedef union {
+    struct {
+        /** slice_byte_length : R/W; bitpos: [3:0]; default: 0;
+         *  Configures Slice Header byte number
+         */
+        uint32_t slice_byte_length:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_slice_header_byte_length_reg_t;
+
+/** Type of bs_threshold register
+ *  Bitstream buffer overflow threshold register
+ */
+typedef union {
+    struct {
+        /** bs_buffer_threshold : R/W; bitpos: [6:0]; default: 48;
+         *  Configures bitstream buffer overflow threshold. This value should be bigger than
+         *  the encode bytes of one 4x4 submb.
+         */
+        uint32_t bs_buffer_threshold:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_bs_threshold_reg_t;
+
+/** Type of slice_header_byte0 register
+ *  Frame Slice Header byte low 32 bit  register.
+ */
+typedef union {
+    struct {
+        /** slice_byte_lsb : R/W; bitpos: [31:0]; default: 0;
+         *  Configures Slice Header low 32 bit
+         */
+        uint32_t slice_byte_lsb:32;
+    };
+    uint32_t val;
+} h264_slice_header_byte0_reg_t;
+
+/** Type of slice_header_byte1 register
+ *  Frame Slice Header byte high 32 bit  register.
+ */
+typedef union {
+    struct {
+        /** slice_byte_msb : R/W; bitpos: [31:0]; default: 0;
+         *  Configures Slice Header high 32 bit
+         */
+        uint32_t slice_byte_msb:32;
+    };
+    uint32_t val;
+} h264_slice_header_byte1_reg_t;
+
+/** Type of conf register
+ *  General configuration register.
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to open register clock gate.
+         *  0: Open the clock gate only when application writes registers
+         *  1: Force open the clock gate for register
+         */
+        uint32_t clk_en:1;
+        /** rec_ram_clk_en2 : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to open the clock gate for rec ram2.
+         *  0: Open the clock gate only when application writes or reads rec ram2
+         *  1: Force open the clock gate for rec ram2
+         */
+        uint32_t rec_ram_clk_en2:1;
+        /** rec_ram_clk_en1 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to open the clock gate for rec ram1.
+         *  0: Open the clock gate only when application writes or reads rec ram1
+         *  1: Force open the clock gate for rec ram1
+         */
+        uint32_t rec_ram_clk_en1:1;
+        /** quant_ram_clk_en2 : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to open the clock gate for quant ram2.
+         *  0: Open the clock gate only when application writes or reads quant ram2
+         *  1: Force open the clock gate for quant ram2
+         */
+        uint32_t quant_ram_clk_en2:1;
+        /** quant_ram_clk_en1 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to open the clock gate for quant ram1.
+         *  0: Open the clock gate only when application writes or reads quant ram1
+         *  1: Force open the clock gate for quant ram1
+         */
+        uint32_t quant_ram_clk_en1:1;
+        /** pre_ram_clk_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to open the clock gate for pre ram.
+         *  0: Open the clock gate only when application writes or reads pre ram
+         *  1: Force open the clock gate for pre ram
+         */
+        uint32_t pre_ram_clk_en:1;
+        /** mvd_ram_clk_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to open the clock gate for mvd ram.
+         *  0: Open the clock gate only when application writes or reads mvd ram
+         *  1: Force open the clock gate for mvd ram
+         */
+        uint32_t mvd_ram_clk_en:1;
+        /** mc_ram_clk_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to open the clock gate for mc ram.
+         *  0: Open the clock gate only when application writes or reads mc ram
+         *  1: Force open the clock gate for mc ram
+         */
+        uint32_t mc_ram_clk_en:1;
+        /** ref_ram_clk_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to open the clock gate for ref ram.
+         *  0: Open the clock gate only when application writes or reads ref ram
+         *  1: Force open the clock gate for ref ram
+         */
+        uint32_t ref_ram_clk_en:1;
+        /** i4x4_ref_ram_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to open the clock gate for i4x4_mode ram.
+         *  0: Open the clock gate only when application writes or reads i4x4_mode ram
+         *  1: Force open the clock gate for i4x4_mode ram
+         */
+        uint32_t i4x4_ref_ram_clk_en:1;
+        /** ime_ram_clk_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to open the clock gate for ime ram.
+         *  0: Open the clock gate only when application writes or reads ime ram
+         *  1: Force open the clock gate for ime ram
+         */
+        uint32_t ime_ram_clk_en:1;
+        /** fme_ram_clk_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to open the clock gate for fme ram.
+         *  0: Open the clock gate only when application writes or readsfme ram
+         *  1: Force open the clock gate for fme ram
+         */
+        uint32_t fme_ram_clk_en:1;
+        /** fetch_ram_clk_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to open the clock gate for fetch ram.
+         *  0: Open the clock gate only when application writes or reads fetch ram
+         *  1: Force open the clock gate for fetch ram
+         */
+        uint32_t fetch_ram_clk_en:1;
+        /** db_ram_clk_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to open the clock gate for db ram.
+         *  0: Open the clock gate only when application writes or reads db ram
+         *  1: Force open the clock gate for db ram
+         */
+        uint32_t db_ram_clk_en:1;
+        /** cur_mb_ram_clk_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to open the clock gate for cur_mb ram.
+         *  0: Open the clock gate only when application writes or reads cur_mb ram
+         *  1: Force open the clock gate for cur_mb ram
+         */
+        uint32_t cur_mb_ram_clk_en:1;
+        /** cavlc_ram_clk_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to open the clock gate for cavlc ram.
+         *  0: Open the clock gate only when application writes or reads cavlc ram
+         *  1: Force open the clock gate for cavlc ram
+         */
+        uint32_t cavlc_ram_clk_en:1;
+        /** ime_clk_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to open the clock gate for ime.
+         *  0: Open the clock gate only when ime work
+         *  1: Force open the clock gate for ime
+         */
+        uint32_t ime_clk_en:1;
+        /** fme_clk_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to open the clock gate for fme.
+         *  0: Open the clock gate only when fme work
+         *  1: Force open the clock gate for fme
+         */
+        uint32_t fme_clk_en:1;
+        /** mc_clk_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to open the clock gate for mc.
+         *  0: Open the clock gate only when mc work
+         *  1: Force open the clock gate for mc
+         */
+        uint32_t mc_clk_en:1;
+        /** interpolator_clk_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to open the clock gate for interpolator.
+         *  0: Open the clock gate only when interpolator work
+         *  1: Force open the clock gate for interpolator
+         */
+        uint32_t interpolator_clk_en:1;
+        /** db_clk_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to open the clock gate for deblocking filter.
+         *  0: Open the clock gate only when deblocking filter work
+         *  1: Force open the clock gate for deblocking filter
+         */
+        uint32_t db_clk_en:1;
+        /** clavlc_clk_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to open the clock gate for cavlc.
+         *  0: Open the clock gate only when cavlc work
+         *  1: Force open the clock gate for cavlc
+         */
+        uint32_t clavlc_clk_en:1;
+        /** intra_clk_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to open the clock gate for intra.
+         *  0: Open the clock gate only when intra work
+         *  1: Force open the clock gate for intra
+         */
+        uint32_t intra_clk_en:1;
+        /** deci_clk_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to open the clock gate for decimate.
+         *  0: Open the clock gate only when decimate work
+         *  1: Force open the clock gate for decimate
+         */
+        uint32_t deci_clk_en:1;
+        /** bs_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to open the clock gate for bs buffer.
+         *  0: Open the clock gate only when bs buffer work
+         *  1: Force open the clock gate for bs buffer
+         */
+        uint32_t bs_clk_en:1;
+        /** mv_merge_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to open the clock gate for mv merge.
+         *  0: Open the clock gate only when mv merge work
+         *  1: Force open the clock gate for mv merge
+         */
+        uint32_t mv_merge_clk_en:1;
+        /** cur_mb_rdcmb_clk_en : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to open the clock gate for cur_mb read macroblock.
+         *  0: Open the clock gate only when cur_mb read macroblock work
+         *  1: Force open the clock gate for  cur_mb read macroblock
+         */
+        uint32_t cur_mb_rdcmb_clk_en:1;
+        /** cur_mb_refresh_reggroup_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to open the clock gate for cur_mb refresh register group.
+         *  0: Open the clock gate only when cur_mb refresh register group work
+         *  1: Force open the clock gate for  cur_mb  refresh register group
+         */
+        uint32_t cur_mb_refresh_reggroup_clk_en:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_conf_reg_t;
+
+/** Type of mv_merge_config register
+ *  Mv merge configuration register.
+ */
+typedef union {
+    struct {
+        /** mv_merge_type : R/W; bitpos: [1:0]; default: 0;
+         *  Configure mv merge type.
+         *  0: merge p16x16 mv
+         *  1: merge min mv
+         *  2: merge max mv
+         *  3: not valid.
+         */
+        uint32_t mv_merge_type:2;
+        /** int_mv_out_en : R/W; bitpos: [2]; default: 0;
+         *  Configure mv merge output integer part not zero mv or all part not zero mv.
+         *  0: output all part not zero mv
+         *  1: output integer part not zero mv.
+         */
+        uint32_t int_mv_out_en:1;
+        /** a_mv_merge_en : R/W; bitpos: [3]; default: 0;
+         *  Configure whether or not to enable video A mv merge.
+         *  0: disable
+         *  1: enable.
+         */
+        uint32_t a_mv_merge_en:1;
+        /** b_mv_merge_en : R/W; bitpos: [4]; default: 0;
+         *  Configure whether or not to enable video B mv merge.
+         *  0: disable
+         *  1: enable.
+         */
+        uint32_t b_mv_merge_en:1;
+        /** mb_valid_num : RO; bitpos: [17:5]; default: 0;
+         *  Represents the valid mb number of mv merge output.
+         */
+        uint32_t mb_valid_num:13;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} h264_mv_merge_config_reg_t;
+
+/** Type of debug_dma_sel register
+ *  Debug H264 DMA select register
+ */
+typedef union {
+    struct {
+        /** dbg_dma_sel : R/W; bitpos: [7:0]; default: 0;
+         *  Every bit represents a dma in h264
+         */
+        uint32_t dbg_dma_sel:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_debug_dma_sel_reg_t;
+
+/** Type of a_ori_conf register
+ *  Video A original picture configuration register.
+ */
+typedef union {
+    struct {
+        /** a_ori_color_space : R/W; bitpos: [2:0]; default: 4;
+         *  Configures video A original picture color space.
+         *  0: RGB888
+         *  1: RGB565
+         *  2: YUV444
+         *  3: YUV422
+         *  4: YUV420
+         *  5: GRAY
+         *  Others: Invalid
+         */
+        uint32_t a_ori_color_space:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} h264_a_ori_conf_reg_t;
+
+/** Type of b_ori_conf register
+ *  Video B original picture configuration register.
+ */
+typedef union {
+    struct {
+        /** b_ori_color_space : R/W; bitpos: [2:0]; default: 4;
+         *  Configures video B original picture color space.
+         *  0: RGB888
+         *  1: RGB565
+         *  2: YUV444
+         *  3: YUV422
+         *  4: YUV420
+         *  5: GRAY
+         *  Others: Invalid
+         */
+        uint32_t b_ori_color_space:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} h264_b_ori_conf_reg_t;
+
+/** Type of ori_debug_conf register
+ *  Original picture debug configuration register.
+ */
+typedef union {
+    struct {
+        /** dbg_replace_ori_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to replace original picture pixels.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_ori_data_en:1;
+        /** dbg_replace_ori_data : R/W; bitpos: [24:1]; default: 0;
+         *  Configures original picture pixels to be replaced. When the original picture color
+         *  space is RGB, byte0~2 is BGR. When the original picture color space is YUV, byte0~2
+         *  is VUY. When the original picture color space is GRAY, byte0 is GRAY.
+         */
+        uint32_t dbg_replace_ori_data:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_ori_debug_conf_reg_t;
+
+/** Type of mv_merge_debug_conf register
+ *  Original picture debug configuration register.
+ */
+typedef union {
+    struct {
+        /** dbg_replace_mv_merge_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to replace mv merge data.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_mv_merge_data_en:1;
+        /** dbg_replace_mv_merge_data : R/W; bitpos: [8:1]; default: 0;
+         *  Configures mv merge data to be replaced.
+         */
+        uint32_t dbg_replace_mv_merge_data:8;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_mv_merge_debug_conf_reg_t;
+
+/** Type of bs_debug_cong register
+ *  Encode bitstream debug configuration register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_wr_bs_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to replace bs data.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_wr_bs_data_en:1;
+        /** dbg_replace_wr_bs_data : R/W; bitpos: [8:1]; default: 0;
+         *  Configures bs data to be replaced
+         */
+        uint32_t dbg_replace_wr_bs_data:8;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_bs_debug_cong_reg_t;
+
+/** Type of db_wr_temp_debug_cong register
+ *  Deblocking filter write temp debug configuration register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_wr_db_temp_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configure deblocking filter whether or not to replace write temp data.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_wr_db_temp_data_en:1;
+        /** dbg_replace_wr_db_temp_data : R/W; bitpos: [24:1]; default: 0;
+         *  Configure deblocking filter write temp data to be replaced.byte0~2 is VUY
+         */
+        uint32_t dbg_replace_wr_db_temp_data:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_db_wr_temp_debug_cong_reg_t;
+
+/** Type of db_rd_temp_debug_cong register
+ *  Deblocking filter read temp debug configuration register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_rd_db_temp_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configure deblocking filter whether or not to replace read temp data.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_rd_db_temp_data_en:1;
+        /** dbg_replace_rd_db_temp_data : R/W; bitpos: [24:1]; default: 0;
+         *  Configure deblocking filter read temp data to be replaced.byte0~2 is VUY
+         */
+        uint32_t dbg_replace_rd_db_temp_data:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_db_rd_temp_debug_cong_reg_t;
+
+/** Type of db_wr_debug_cong register
+ *  Deblocking filter final data debug configuration register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_wr_db_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configure deblocking filter whether or not to replace write data.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_wr_db_data_en:1;
+        /** dbg_replace_wr_db_data : R/W; bitpos: [24:1]; default: 0;
+         *  Configure deblocking filter write data to be replaced.byte0~2 is VUY
+         */
+        uint32_t dbg_replace_wr_db_data:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_db_wr_debug_cong_reg_t;
+
+/** Type of ref_debug_cong register
+ *  Deblocking filter final data debug configuration register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_ref_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether to replace reference picture pixels.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_ref_data_en:1;
+        /** dbg_replace_ref_data : R/W; bitpos: [24:1]; default: 0;
+         *  Configure reference picture pixels to be replaced.byte0~2 is VUY
+         */
+        uint32_t dbg_replace_ref_data:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_ref_debug_cong_reg_t;
+
+
+/** Group: Status Register */
+/** Type of rc_status0 register
+ *  Rate control status register0.
+ */
+typedef union {
+    struct {
+        /** frame_mad_sum : RO; bitpos: [20:0]; default: 0;
+         *  Represents all MB actual MAD sum value of one frame.
+         */
+        uint32_t frame_mad_sum:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} h264_rc_status0_reg_t;
+
+/** Type of rc_status1 register
+ *  Rate control status register1.
+ */
+typedef union {
+    struct {
+        /** frame_enc_bits : RO; bitpos: [26:0]; default: 0;
+         *  Represents all MB actual encoding bits sum value of one frame.
+         */
+        uint32_t frame_enc_bits:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_rc_status1_reg_t;
+
+/** Type of rc_status2 register
+ *  Rate control status register2.
+ */
+typedef union {
+    struct {
+        /** frame_qp_sum : RO; bitpos: [18:0]; default: 0;
+         *  Represents all MB actual luma QP sum value of one frame.
+         */
+        uint32_t frame_qp_sum:19;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} h264_rc_status2_reg_t;
+
+/** Type of sys_status register
+ *  System status register.
+ */
+typedef union {
+    struct {
+        /** frame_num : RO; bitpos: [8:0]; default: 0;
+         *  Represents current frame number.
+         */
+        uint32_t frame_num:9;
+        /** dual_stream_sel : RO; bitpos: [9]; default: 0;
+         *  Represents which register group is used for cur frame.
+         *  0: Register group A is used
+         *  1: Register group B is used.
+         */
+        uint32_t dual_stream_sel:1;
+        /** intra_flag : RO; bitpos: [10]; default: 0;
+         *  Represents the type of current encoding frame.
+         *  0: P frame
+         *  1: I frame.
+         */
+        uint32_t intra_flag:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_sys_status_reg_t;
+
+/** Type of frame_code_length register
+ *  Frame code byte length register.
+ */
+typedef union {
+    struct {
+        /** frame_code_length : RO; bitpos: [23:0]; default: 0;
+         *  Represents current frame code byte length.
+         */
+        uint32_t frame_code_length:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_frame_code_length_reg_t;
+
+/** Type of debug_info0 register
+ *  Debug information register0.
+ */
+typedef union {
+    struct {
+        /** top_ctrl_inter_debug_state : RO; bitpos: [3:0]; default: 0;
+         *  Represents top_ctrl_inter module FSM info.
+         */
+        uint32_t top_ctrl_inter_debug_state:4;
+        /** top_ctrl_intra_debug_state : RO; bitpos: [6:4]; default: 0;
+         *  Represents top_ctrl_intra module FSM info.
+         */
+        uint32_t top_ctrl_intra_debug_state:3;
+        /** p_i_cmp_debug_state : RO; bitpos: [9:7]; default: 0;
+         *  Represents p_i_cmp module FSM info.
+         */
+        uint32_t p_i_cmp_debug_state:3;
+        /** mvd_debug_state : RO; bitpos: [12:10]; default: 0;
+         *  Represents mvd module FSM info.
+         */
+        uint32_t mvd_debug_state:3;
+        /** mc_chroma_ip_debug_state : RO; bitpos: [13]; default: 0;
+         *  Represents mc_chroma_ip module FSM info.
+         */
+        uint32_t mc_chroma_ip_debug_state:1;
+        /** intra_16x16_chroma_ctrl_debug_state : RO; bitpos: [17:14]; default: 0;
+         *  Represents intra_16x16_chroma_ctrl module FSM info.
+         */
+        uint32_t intra_16x16_chroma_ctrl_debug_state:4;
+        /** intra_4x4_ctrl_debug_state : RO; bitpos: [21:18]; default: 0;
+         *  Represents intra_4x4_ctrl module FSM info.
+         */
+        uint32_t intra_4x4_ctrl_debug_state:4;
+        /** intra_top_ctrl_debug_state : RO; bitpos: [24:22]; default: 0;
+         *  Represents intra_top_ctrl module FSM info.
+         */
+        uint32_t intra_top_ctrl_debug_state:3;
+        /** ime_ctrl_debug_state : RO; bitpos: [27:25]; default: 0;
+         *  Represents ime_ctrl module FSM info.
+         */
+        uint32_t ime_ctrl_debug_state:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_debug_info0_reg_t;
+
+/** Type of debug_info1 register
+ *  Debug information register1.
+ */
+typedef union {
+    struct {
+        /** fme_ctrl_debug_state : RO; bitpos: [2:0]; default: 0;
+         *  Represents fme_ctrl module FSM info.
+         */
+        uint32_t fme_ctrl_debug_state:3;
+        /** deci_calc_debug_state : RO; bitpos: [4:3]; default: 0;
+         *  Represents deci_calc module's FSM info. DEV use only.
+         */
+        uint32_t deci_calc_debug_state:2;
+        /** db_debug_state : RO; bitpos: [7:5]; default: 0;
+         *  Represents db module FSM info.
+         */
+        uint32_t db_debug_state:3;
+        /** cavlc_enc_debug_state : RO; bitpos: [11:8]; default: 0;
+         *  Represents cavlc module enc FSM info.
+         */
+        uint32_t cavlc_enc_debug_state:4;
+        /** cavlc_scan_debug_state : RO; bitpos: [15:12]; default: 0;
+         *  Represents cavlc module scan FSM info.
+         */
+        uint32_t cavlc_scan_debug_state:4;
+        /** cavlc_ctrl_debug_state : RO; bitpos: [17:16]; default: 0;
+         *  Represents cavlc module ctrl FSM info.
+         */
+        uint32_t cavlc_ctrl_debug_state:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} h264_debug_info1_reg_t;
+
+/** Type of debug_info2 register
+ *  Debug information register2.
+ */
+typedef union {
+    struct {
+        /** p_rc_done_debug_flag : RO; bitpos: [0]; default: 0;
+         *  Represents p rate ctrl done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_rc_done_debug_flag:1;
+        /** p_p_i_cmp_done_debug_flag : RO; bitpos: [1]; default: 0;
+         *  Represents p p_i_cmp done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_p_i_cmp_done_debug_flag:1;
+        /** p_mv_merge_done_debug_flag : RO; bitpos: [2]; default: 0;
+         *  Represents p mv merge done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_mv_merge_done_debug_flag:1;
+        /** p_move_ori_done_debug_flag : RO; bitpos: [3]; default: 0;
+         *  Represents p move origin done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_move_ori_done_debug_flag:1;
+        /** p_mc_done_debug_flag : RO; bitpos: [4]; default: 0;
+         *  Represents p mc done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_mc_done_debug_flag:1;
+        /** p_ime_done_debug_flag : RO; bitpos: [5]; default: 0;
+         *  Represents p ime done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_ime_done_debug_flag:1;
+        /** p_get_ori_done_debug_flag : RO; bitpos: [6]; default: 0;
+         *  Represents p get origin done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_get_ori_done_debug_flag:1;
+        /** p_fme_done_debug_flag : RO; bitpos: [7]; default: 0;
+         *  Represents p fme done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_fme_done_debug_flag:1;
+        /** p_fetch_done_debug_flag : RO; bitpos: [8]; default: 0;
+         *  Represents p fetch done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_fetch_done_debug_flag:1;
+        /** p_db_done_debug_flag : RO; bitpos: [9]; default: 0;
+         *  Represents p deblocking done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_db_done_debug_flag:1;
+        /** p_bs_buf_done_debug_flag : RO; bitpos: [10]; default: 0;
+         *  Represents p bitstream buffer done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_bs_buf_done_debug_flag:1;
+        /** ref_move_2mb_line_done_debug_flag : RO; bitpos: [11]; default: 0;
+         *  Represents dma move 2 ref mb line done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t ref_move_2mb_line_done_debug_flag:1;
+        /** i_p_i_cmp_done_debug_flag : RO; bitpos: [12]; default: 0;
+         *  Represents I p_i_cmp done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_p_i_cmp_done_debug_flag:1;
+        /** i_move_ori_done_debug_flag : RO; bitpos: [13]; default: 0;
+         *  Represents I move origin done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_move_ori_done_debug_flag:1;
+        /** i_get_ori_done_debug_flag : RO; bitpos: [14]; default: 0;
+         *  Represents I get origin done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_get_ori_done_debug_flag:1;
+        /** i_ec_done_debug_flag : RO; bitpos: [15]; default: 0;
+         *  Represents I encoder done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_ec_done_debug_flag:1;
+        /** i_db_done_debug_flag : RO; bitpos: [16]; default: 0;
+         *  Represents I deblocking done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_db_done_debug_flag:1;
+        /** i_bs_buf_done_debug_flag : RO; bitpos: [17]; default: 0;
+         *  Represents I bitstream buffer done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_bs_buf_done_debug_flag:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} h264_debug_info2_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** db_tmp_ready_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Raw status bit: The raw interrupt status of  H264_DB_TMP_READY_INT. Triggered when
+         *  H264 written enough db tmp pixel.
+         */
+        uint32_t db_tmp_ready_int_raw:1;
+        /** rec_ready_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Raw status bit: The raw interrupt status of  H264_REC_READY_INT. Triggered when
+         *  H264 encoding enough reconstruct pixel.
+         */
+        uint32_t rec_ready_int_raw:1;
+        /** frame_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Raw status bit: The raw interrupt status of  H264_FRAME_DONE_INT. Triggered when
+         *  H264 encoding one frame done.
+         */
+        uint32_t frame_done_int_raw:1;
+        /** dma_move_2mb_line_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT.
+         *  Triggered when H264 move two MB lines of reference frame from external mem to
+         *  internal mem done.
+         */
+        uint32_t dma_move_2mb_line_done_int_raw:1;
+        /** bs_buffer_overflow_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Raw status bit: The raw interrupt status of H264_BS_BUFFER_OVERFLOW_INT. Triggered
+         *  when H264 bit stream buffer overflow.
+         */
+        uint32_t bs_buffer_overflow_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt masked status register
+ */
+typedef union {
+    struct {
+        /** db_tmp_ready_int_st : RO; bitpos: [0]; default: 0;
+         *  Masked status bit: The masked interrupt status of H264_DB_TMP_READY_INT. Valid only
+         *  when the H264_DB_TMP_READY_INT_ENA is set to 1.
+         */
+        uint32_t db_tmp_ready_int_st:1;
+        /** rec_ready_int_st : RO; bitpos: [1]; default: 0;
+         *  Masked status bit: The masked interrupt status of H264_REC_READY_INT. Valid only
+         *  when the H264_REC_READY_INT_ENA is set to 1.
+         */
+        uint32_t rec_ready_int_st:1;
+        /** frame_done_int_st : RO; bitpos: [2]; default: 0;
+         *  Masked status bit: The masked interrupt status of H264_FRAME_DONE_INT. Valid only
+         *  when the H264_FRAME_DONE_INT_ENA is set to 1.
+         */
+        uint32_t frame_done_int_st:1;
+        /** dma_move_2mb_line_done_int_st : RO; bitpos: [3]; default: 0;
+         *  Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT.
+         *  Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1.
+         */
+        uint32_t dma_move_2mb_line_done_int_st:1;
+        /** bs_buffer_overflow_int_st : RO; bitpos: [4]; default: 0;
+         *  Masked status bit: The masked interrupt status of H264_BS_BUFFER_OVERFLOW_INT.
+         *  Valid only when the H264_BS_BUFFER_OVERFLOW_INT_ENA is set to 1.
+         */
+        uint32_t bs_buffer_overflow_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** db_tmp_ready_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable bit: Write 1 to enable H264_DB_TMP_READY_INT.
+         */
+        uint32_t db_tmp_ready_int_ena:1;
+        /** rec_ready_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Enable bit: Write 1 to enable H264_REC_READY_INT.
+         */
+        uint32_t rec_ready_int_ena:1;
+        /** frame_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Enable bit: Write 1 to enable H264_FRAME_DONE_INT.
+         */
+        uint32_t frame_done_int_ena:1;
+        /** dma_move_2mb_line_done_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT.
+         */
+        uint32_t dma_move_2mb_line_done_int_ena:1;
+        /** bs_buffer_overflow_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Enable bit: Write 1 to enable H264_BS_BUFFER_OVERFLOW_INT.
+         */
+        uint32_t bs_buffer_overflow_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** db_tmp_ready_int_clr : WT; bitpos: [0]; default: 0;
+         *  Clear bit: Write 1 to clear H264_DB_TMP_READY_INT.
+         */
+        uint32_t db_tmp_ready_int_clr:1;
+        /** rec_ready_int_clr : WT; bitpos: [1]; default: 0;
+         *  Clear bit: Write 1 to clear H264_REC_READY_INT.
+         */
+        uint32_t rec_ready_int_clr:1;
+        /** frame_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Clear bit: Write 1 to clear H264_FRAME_DONE_INT.
+         */
+        uint32_t frame_done_int_clr:1;
+        /** dma_move_2mb_line_done_int_clr : WT; bitpos: [3]; default: 0;
+         *  Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT.
+         */
+        uint32_t dma_move_2mb_line_done_int_clr:1;
+        /** bs_buffer_overflow_int_clr : WT; bitpos: [4]; default: 0;
+         *  Clear bit: Write 1 to clear H264_BS_BUFFER_OVERFLOW_INT.
+         */
+        uint32_t bs_buffer_overflow_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37823232;
+         *  Configures the version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_date_reg_t;
+
+
+typedef struct {
+    volatile h264_sys_ctrl_reg_t sys_ctrl;
+    volatile h264_gop_conf_reg_t gop_conf;
+    volatile h264_a_sys_mb_res_reg_t a_sys_mb_res;
+    volatile h264_a_sys_conf_reg_t a_sys_conf;
+    volatile h264_a_deci_score_reg_t a_deci_score;
+    volatile h264_a_deci_score_offset_reg_t a_deci_score_offset;
+    volatile h264_a_rc_conf0_reg_t a_rc_conf0;
+    volatile h264_a_rc_conf1_reg_t a_rc_conf1;
+    volatile h264_a_db_bypass_reg_t a_db_bypass;
+    volatile h264_a_roi_region0_reg_t a_roi_region0;
+    volatile h264_a_roi_region1_reg_t a_roi_region1;
+    volatile h264_a_roi_region2_reg_t a_roi_region2;
+    volatile h264_a_roi_region3_reg_t a_roi_region3;
+    volatile h264_a_roi_region4_reg_t a_roi_region4;
+    volatile h264_a_roi_region5_reg_t a_roi_region5;
+    volatile h264_a_roi_region6_reg_t a_roi_region6;
+    volatile h264_a_roi_region7_reg_t a_roi_region7;
+    volatile h264_a_roi_region0_3_qp_reg_t a_roi_region0_3_qp;
+    volatile h264_a_roi_region4_7_qp_reg_t a_roi_region4_7_qp;
+    volatile h264_a_no_roi_region_qp_offset_reg_t a_no_roi_region_qp_offset;
+    volatile h264_a_roi_config_reg_t a_roi_config;
+    volatile h264_b_sys_mb_res_reg_t b_sys_mb_res;
+    volatile h264_b_sys_conf_reg_t b_sys_conf;
+    volatile h264_b_deci_score_reg_t b_deci_score;
+    volatile h264_b_deci_score_offset_reg_t b_deci_score_offset;
+    volatile h264_b_rc_conf0_reg_t b_rc_conf0;
+    volatile h264_b_rc_conf1_reg_t b_rc_conf1;
+    volatile h264_b_db_bypass_reg_t b_db_bypass;
+    volatile h264_b_roi_region0_reg_t b_roi_region0;
+    volatile h264_b_roi_region1_reg_t b_roi_region1;
+    volatile h264_b_roi_region2_reg_t b_roi_region2;
+    volatile h264_b_roi_region3_reg_t b_roi_region3;
+    volatile h264_b_roi_region4_reg_t b_roi_region4;
+    volatile h264_b_roi_region5_reg_t b_roi_region5;
+    volatile h264_b_roi_region6_reg_t b_roi_region6;
+    volatile h264_b_roi_region7_reg_t b_roi_region7;
+    volatile h264_b_roi_region0_3_qp_reg_t b_roi_region0_3_qp;
+    volatile h264_b_roi_region4_7_qp_reg_t b_roi_region4_7_qp;
+    volatile h264_b_no_roi_region_qp_offset_reg_t b_no_roi_region_qp_offset;
+    volatile h264_b_roi_config_reg_t b_roi_config;
+    volatile h264_rc_status0_reg_t rc_status0;
+    volatile h264_rc_status1_reg_t rc_status1;
+    volatile h264_rc_status2_reg_t rc_status2;
+    volatile h264_slice_header_remain_reg_t slice_header_remain;
+    volatile h264_slice_header_byte_length_reg_t slice_header_byte_length;
+    volatile h264_bs_threshold_reg_t bs_threshold;
+    volatile h264_slice_header_byte0_reg_t slice_header_byte0;
+    volatile h264_slice_header_byte1_reg_t slice_header_byte1;
+    volatile h264_int_raw_reg_t int_raw;
+    volatile h264_int_st_reg_t int_st;
+    volatile h264_int_ena_reg_t int_ena;
+    volatile h264_int_clr_reg_t int_clr;
+    volatile h264_conf_reg_t conf;
+    volatile h264_mv_merge_config_reg_t mv_merge_config;
+    volatile h264_debug_dma_sel_reg_t debug_dma_sel;
+    volatile h264_sys_status_reg_t sys_status;
+    volatile h264_frame_code_length_reg_t frame_code_length;
+    volatile h264_debug_info0_reg_t debug_info0;
+    volatile h264_debug_info1_reg_t debug_info1;
+    volatile h264_debug_info2_reg_t debug_info2;
+    volatile h264_date_reg_t date;
+    volatile h264_a_ori_conf_reg_t a_ori_conf;
+    volatile h264_b_ori_conf_reg_t b_ori_conf;
+    volatile h264_ori_debug_conf_reg_t ori_debug_conf;
+    volatile h264_mv_merge_debug_conf_reg_t mv_merge_debug_conf;
+    volatile h264_bs_debug_cong_reg_t bs_debug_cong;
+    volatile h264_db_wr_temp_debug_cong_reg_t db_wr_temp_debug_cong;
+    volatile h264_db_rd_temp_debug_cong_reg_t db_rd_temp_debug_cong;
+    volatile h264_db_wr_debug_cong_reg_t db_wr_debug_cong;
+    volatile h264_ref_debug_cong_reg_t ref_debug_cong;
+} h264_dev_t;
+
+extern h264_dev_t H264;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(h264_dev_t) == 0x118, "Invalid size of h264_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hmac_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hmac_reg.h
new file mode 100644
index 0000000000..bba02c8bb6
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hmac_reg.h
@@ -0,0 +1,282 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HMAC_SET_START_REG register
+ *  HMAC start control register
+ */
+#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
+/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable HMAC.
+ *
+ *  0: Disable HMAC
+ *
+ *  1: Enable HMAC
+ */
+#define HMAC_SET_START    (BIT(0))
+#define HMAC_SET_START_M  (HMAC_SET_START_V << HMAC_SET_START_S)
+#define HMAC_SET_START_V  0x00000001U
+#define HMAC_SET_START_S  0
+
+/** HMAC_SET_PARA_PURPOSE_REG register
+ *  HMAC parameter configuration register
+ */
+#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
+/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
+ *  Configures the HMAC purpose, refer to the Table . "
+ */
+#define HMAC_PURPOSE_SET    0x0000000FU
+#define HMAC_PURPOSE_SET_M  (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
+#define HMAC_PURPOSE_SET_V  0x0000000FU
+#define HMAC_PURPOSE_SET_S  0
+
+/** HMAC_SET_PARA_KEY_REG register
+ *  HMAC parameters configuration register
+ */
+#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
+/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
+ *  Configures HMAC key. There are six keys with index 0~5. Write the index of the
+ *  selected key to this field.
+ */
+#define HMAC_KEY_SET    0x00000007U
+#define HMAC_KEY_SET_M  (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
+#define HMAC_KEY_SET_V  0x00000007U
+#define HMAC_KEY_SET_S  0
+
+/** HMAC_SET_PARA_FINISH_REG register
+ *  HMAC configuration completion register
+ */
+#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
+/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
+ *  Configures whether to finish HMAC configuration.
+ *
+ *  0: No effect
+ *
+ *  1: Finish configuration
+ */
+#define HMAC_SET_PARA_END    (BIT(0))
+#define HMAC_SET_PARA_END_M  (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
+#define HMAC_SET_PARA_END_V  0x00000001U
+#define HMAC_SET_PARA_END_S  0
+
+/** HMAC_SET_MESSAGE_ONE_REG register
+ *  HMAC message control register
+ */
+#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
+/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
+ *  Calls SHA to calculate one message block.
+ */
+#define HMAC_SET_TEXT_ONE    (BIT(0))
+#define HMAC_SET_TEXT_ONE_M  (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
+#define HMAC_SET_TEXT_ONE_V  0x00000001U
+#define HMAC_SET_TEXT_ONE_S  0
+
+/** HMAC_SET_MESSAGE_ING_REG register
+ *  HMAC message continue register
+ */
+#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
+/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not there are unprocessed message blocks.
+ *
+ *  0: No unprocessed message block
+ *
+ *  1: There are still some message blocks to be processed.
+ */
+#define HMAC_SET_TEXT_ING    (BIT(0))
+#define HMAC_SET_TEXT_ING_M  (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
+#define HMAC_SET_TEXT_ING_V  0x00000001U
+#define HMAC_SET_TEXT_ING_S  0
+
+/** HMAC_SET_MESSAGE_END_REG register
+ *  HMAC message end register
+ */
+#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
+/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
+ *  Configures whether to start hardware padding.
+ *
+ *  0: No effect
+ *
+ *  1: Start hardware padding
+ */
+#define HMAC_SET_TEXT_END    (BIT(0))
+#define HMAC_SET_TEXT_END_M  (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
+#define HMAC_SET_TEXT_END_V  0x00000001U
+#define HMAC_SET_TEXT_END_S  0
+
+/** HMAC_SET_RESULT_FINISH_REG register
+ *  HMAC result reading finish register
+ */
+#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
+/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
+ *  Configures whether to exit upstream mode and clear calculation results.
+ *
+ *  0: Not exit
+ *
+ *  1: Exit upstream mode and clear calculation results.
+ */
+#define HMAC_SET_RESULT_END    (BIT(0))
+#define HMAC_SET_RESULT_END_M  (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
+#define HMAC_SET_RESULT_END_V  0x00000001U
+#define HMAC_SET_RESULT_END_S  0
+
+/** HMAC_SET_INVALIDATE_JTAG_REG register
+ *  Invalidate JTAG result register
+ */
+#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
+/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear calculation results when re-enabling JTAG in
+ *  downstream mode.
+ *
+ *  0: Not clear
+ *
+ *  1: Clear calculation results
+ */
+#define HMAC_SET_INVALIDATE_JTAG    (BIT(0))
+#define HMAC_SET_INVALIDATE_JTAG_M  (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
+#define HMAC_SET_INVALIDATE_JTAG_V  0x00000001U
+#define HMAC_SET_INVALIDATE_JTAG_S  0
+
+/** HMAC_SET_INVALIDATE_DS_REG register
+ *  Invalidate digital signature result register
+ */
+#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
+/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear calculation results of the DS module in
+ *  downstream mode.
+ *
+ *  0: Not clear
+ *
+ *  1: Clear calculation results
+ */
+#define HMAC_SET_INVALIDATE_DS    (BIT(0))
+#define HMAC_SET_INVALIDATE_DS_M  (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
+#define HMAC_SET_INVALIDATE_DS_V  0x00000001U
+#define HMAC_SET_INVALIDATE_DS_S  0
+
+/** HMAC_QUERY_ERROR_REG register
+ *  Stores matching results between keys generated by users and corresponding purposes
+ */
+#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
+/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an HMAC key matches the purpose.
+ *
+ *  0: Match
+ *
+ *  1: Error
+ */
+#define HMAC_QUREY_CHECK    (BIT(0))
+#define HMAC_QUREY_CHECK_M  (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
+#define HMAC_QUREY_CHECK_V  0x00000001U
+#define HMAC_QUREY_CHECK_S  0
+
+/** HMAC_QUERY_BUSY_REG register
+ *  Busy state of HMAC module
+ */
+#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
+/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
+ *  make sure HMAC is in an IDLE state.
+ *
+ *  0: Idle
+ *
+ *  1: HMAC is still working on the calculation
+ */
+#define HMAC_BUSY_STATE    (BIT(0))
+#define HMAC_BUSY_STATE_M  (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
+#define HMAC_BUSY_STATE_V  0x00000001U
+#define HMAC_BUSY_STATE_S  0
+
+/** HMAC_WR_MESSAGE_MEM register
+ *  Message block memory.
+ */
+#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
+#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
+
+/** HMAC_RD_RESULT_MEM register
+ *  Result from upstream.
+ */
+#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
+#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
+
+/** HMAC_SET_MESSAGE_PAD_REG register
+ *  Software padding register
+ */
+#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
+/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
+ *  Configures whether or not the padding is applied by software.
+ *
+ *  0: Not applied by software
+ *
+ *  1: Applied by software
+ */
+#define HMAC_SET_TEXT_PAD    (BIT(0))
+#define HMAC_SET_TEXT_PAD_M  (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
+#define HMAC_SET_TEXT_PAD_V  0x00000001U
+#define HMAC_SET_TEXT_PAD_S  0
+
+/** HMAC_ONE_BLOCK_REG register
+ *  One block message register
+ */
+#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
+/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
+ *  Write 1 to indicate there is only one block which already contains padding bits and
+ *  there is no need for padding.
+ */
+#define HMAC_SET_ONE_BLOCK    (BIT(0))
+#define HMAC_SET_ONE_BLOCK_M  (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
+#define HMAC_SET_ONE_BLOCK_V  0x00000001U
+#define HMAC_SET_ONE_BLOCK_S  0
+
+/** HMAC_SOFT_JTAG_CTRL_REG register
+ *  Jtag register 0.
+ */
+#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
+/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable JTAG authentication mode.
+ *
+ *  0: Disable
+ *
+ *  1: Enable
+ *
+ */
+#define HMAC_SOFT_JTAG_CTRL    (BIT(0))
+#define HMAC_SOFT_JTAG_CTRL_M  (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
+#define HMAC_SOFT_JTAG_CTRL_V  0x00000001U
+#define HMAC_SOFT_JTAG_CTRL_S  0
+
+/** HMAC_WR_JTAG_REG register
+ *  Re-enable JTAG register 1
+ */
+#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
+/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
+ *  Writes the comparing input used for re-enabling JTAG.
+ */
+#define HMAC_WR_JTAG    0xFFFFFFFFU
+#define HMAC_WR_JTAG_M  (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
+#define HMAC_WR_JTAG_V  0xFFFFFFFFU
+#define HMAC_WR_JTAG_S  0
+
+/** HMAC_DATE_REG register
+ *  Version control register
+ */
+#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
+/** HMAC_DATE : R/W; bitpos: [29:0]; default: 539166977;
+ *  Hmac date information/ hmac version information.
+ */
+#define HMAC_DATE    0x3FFFFFFFU
+#define HMAC_DATE_M  (HMAC_DATE_V << HMAC_DATE_S)
+#define HMAC_DATE_V  0x3FFFFFFFU
+#define HMAC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hmac_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hmac_struct.h
new file mode 100644
index 0000000000..9003f4d58f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hmac_struct.h
@@ -0,0 +1,344 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control/Status Registers */
+/** Type of set_start register
+ *  HMAC start control register
+ */
+typedef union {
+    struct {
+        /** set_start : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable HMAC.
+         *
+         *  0: Disable HMAC
+         *
+         *  1: Enable HMAC
+         */
+        uint32_t set_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_start_reg_t;
+
+/** Type of set_para_finish register
+ *  HMAC configuration completion register
+ */
+typedef union {
+    struct {
+        /** set_para_end : WS; bitpos: [0]; default: 0;
+         *  Configures whether to finish HMAC configuration.
+         *
+         *  0: No effect
+         *
+         *  1: Finish configuration
+         */
+        uint32_t set_para_end:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_para_finish_reg_t;
+
+/** Type of set_message_one register
+ *  HMAC message control register
+ */
+typedef union {
+    struct {
+        /** set_text_one : WS; bitpos: [0]; default: 0;
+         *  Calls SHA to calculate one message block.
+         */
+        uint32_t set_text_one:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_one_reg_t;
+
+/** Type of set_message_ing register
+ *  HMAC message continue register
+ */
+typedef union {
+    struct {
+        /** set_text_ing : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not there are unprocessed message blocks.
+         *
+         *  0: No unprocessed message block
+         *
+         *  1: There are still some message blocks to be processed.
+         */
+        uint32_t set_text_ing:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_ing_reg_t;
+
+/** Type of set_message_end register
+ *  HMAC message end register
+ */
+typedef union {
+    struct {
+        /** set_text_end : WS; bitpos: [0]; default: 0;
+         *  Configures whether to start hardware padding.
+         *
+         *  0: No effect
+         *
+         *  1: Start hardware padding
+         */
+        uint32_t set_text_end:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_end_reg_t;
+
+/** Type of set_result_finish register
+ *  HMAC result reading finish register
+ */
+typedef union {
+    struct {
+        /** set_result_end : WS; bitpos: [0]; default: 0;
+         *  Configures whether to exit upstream mode and clear calculation results.
+         *
+         *  0: Not exit
+         *
+         *  1: Exit upstream mode and clear calculation results.
+         */
+        uint32_t set_result_end:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_result_finish_reg_t;
+
+/** Type of set_invalidate_jtag register
+ *  Invalidate JTAG result register
+ */
+typedef union {
+    struct {
+        /** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear calculation results when re-enabling JTAG in
+         *  downstream mode.
+         *
+         *  0: Not clear
+         *
+         *  1: Clear calculation results
+         */
+        uint32_t set_invalidate_jtag:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_invalidate_jtag_reg_t;
+
+/** Type of set_invalidate_ds register
+ *  Invalidate digital signature result register
+ */
+typedef union {
+    struct {
+        /** set_invalidate_ds : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear calculation results of the DS module in
+         *  downstream mode.
+         *
+         *  0: Not clear
+         *
+         *  1: Clear calculation results
+         */
+        uint32_t set_invalidate_ds:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_invalidate_ds_reg_t;
+
+/** Type of query_error register
+ *  Stores matching results between keys generated by users and corresponding purposes
+ */
+typedef union {
+    struct {
+        /** qurey_check : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not an HMAC key matches the purpose.
+         *
+         *  0: Match
+         *
+         *  1: Error
+         */
+        uint32_t qurey_check:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_query_error_reg_t;
+
+/** Type of query_busy register
+ *  Busy state of HMAC module
+ */
+typedef union {
+    struct {
+        /** busy_state : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
+         *  make sure HMAC is in an IDLE state.
+         *
+         *  0: Idle
+         *
+         *  1: HMAC is still working on the calculation
+         */
+        uint32_t busy_state:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_query_busy_reg_t;
+
+/** Type of set_message_pad register
+ *  Software padding register
+ */
+typedef union {
+    struct {
+        /** set_text_pad : WO; bitpos: [0]; default: 0;
+         *  Configures whether or not the padding is applied by software.
+         *
+         *  0: Not applied by software
+         *
+         *  1: Applied by software
+         */
+        uint32_t set_text_pad:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_pad_reg_t;
+
+/** Type of one_block register
+ *  One block message register
+ */
+typedef union {
+    struct {
+        /** set_one_block : WS; bitpos: [0]; default: 0;
+         *  Write 1 to indicate there is only one block which already contains padding bits and
+         *  there is no need for padding.
+         */
+        uint32_t set_one_block:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_one_block_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of set_para_purpose register
+ *  HMAC parameter configuration register
+ */
+typedef union {
+    struct {
+        /** purpose_set : WO; bitpos: [3:0]; default: 0;
+         *  Configures the HMAC purpose, refer to the Table . "
+         */
+        uint32_t purpose_set:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hmac_set_para_purpose_reg_t;
+
+/** Type of set_para_key register
+ *  HMAC parameters configuration register
+ */
+typedef union {
+    struct {
+        /** key_set : WO; bitpos: [2:0]; default: 0;
+         *  Configures HMAC key. There are six keys with index 0~5. Write the index of the
+         *  selected key to this field.
+         */
+        uint32_t key_set:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hmac_set_para_key_reg_t;
+
+/** Type of wr_jtag register
+ *  Re-enable JTAG register 1
+ */
+typedef union {
+    struct {
+        /** wr_jtag : WO; bitpos: [31:0]; default: 0;
+         *  Writes the comparing input used for re-enabling JTAG.
+         */
+        uint32_t wr_jtag:32;
+    };
+    uint32_t val;
+} hmac_wr_jtag_reg_t;
+
+
+/** Group: Memory Type */
+
+/** Group: Configuration Register */
+/** Type of soft_jtag_ctrl register
+ *  Jtag register 0.
+ */
+typedef union {
+    struct {
+        /** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable JTAG authentication mode.
+         *
+         *  0: Disable
+         *
+         *  1: Enable
+         *
+         */
+        uint32_t soft_jtag_ctrl:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_soft_jtag_ctrl_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [29:0]; default: 539166977;
+         *  Hmac date information/ hmac version information.
+         */
+        uint32_t date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hmac_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[16];
+    volatile hmac_set_start_reg_t set_start;
+    volatile hmac_set_para_purpose_reg_t set_para_purpose;
+    volatile hmac_set_para_key_reg_t set_para_key;
+    volatile hmac_set_para_finish_reg_t set_para_finish;
+    volatile hmac_set_message_one_reg_t set_message_one;
+    volatile hmac_set_message_ing_reg_t set_message_ing;
+    volatile hmac_set_message_end_reg_t set_message_end;
+    volatile hmac_set_result_finish_reg_t set_result_finish;
+    volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
+    volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
+    volatile hmac_query_error_reg_t query_error;
+    volatile hmac_query_busy_reg_t query_busy;
+    uint32_t reserved_070[4];
+    volatile uint32_t wr_message[16];
+    volatile uint32_t rd_result[8];
+    uint32_t reserved_0e0[4];
+    volatile hmac_set_message_pad_reg_t set_message_pad;
+    volatile hmac_one_block_reg_t one_block;
+    volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
+    volatile hmac_wr_jtag_reg_t wr_jtag;
+    uint32_t reserved_100[63];
+    volatile hmac_date_reg_t date;
+} hmac_dev_t;
+
+extern hmac_dev_t HMAC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_eco5_reg.h
new file mode 100644
index 0000000000..8f08a8e399
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_eco5_reg.h
@@ -0,0 +1,779 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_HP2LP_TEE_PMS_DATE_REG register
+ *  NA
+ */
+#define TEE_HP2LP_TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
+/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
+ *  NA
+ */
+#define TEE_TEE_DATE    0xFFFFFFFFU
+#define TEE_TEE_DATE_M  (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
+#define TEE_TEE_DATE_V  0xFFFFFFFFU
+#define TEE_TEE_DATE_S  0
+
+/** TEE_PMS_CLK_EN_REG register
+ *  NA
+ */
+#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
+/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CLK_EN    (BIT(0))
+#define TEE_REG_CLK_EN_M  (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
+#define TEE_REG_CLK_EN_V  0x00000001U
+#define TEE_REG_CLK_EN_S  0
+
+/** TEE_HP_CORE0_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_HP_CORE0_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
+/** TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S  0
+/** TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S  1
+/** TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW    (BIT(2))
+#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S  2
+/** TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S  3
+/** TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW    (BIT(4))
+#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S  4
+/** TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW    (BIT(5))
+#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S  5
+/** TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S  6
+/** TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW    (BIT(7))
+#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S  7
+/** TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S  8
+/** TEE_REG_HP_CORE0_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW    (BIT(9))
+#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S  9
+/** TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW    (BIT(10))
+#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S  10
+/** TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW    (BIT(11))
+#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S  11
+/** TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S  12
+/** TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW    (BIT(13))
+#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S  13
+/** TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW    (BIT(14))
+#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S  14
+/** TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S  15
+/** TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S  16
+/** TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW    (BIT(17))
+#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S  17
+/** TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S  18
+/** TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW    (BIT(19))
+#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S  19
+/** TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_M  (TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S  20
+/** TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW    (BIT(21))
+#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S  21
+/** TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW    (BIT(22))
+#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S  22
+/** TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW    (BIT(23))
+#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S  23
+/** TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW    (BIT(24))
+#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_S  24
+
+/** TEE_HP_CORE0_UM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_HP_CORE0_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0xc)
+/** TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW    (BIT(0))
+#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S  0
+/** TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S  1
+/** TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW    (BIT(2))
+#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S  2
+/** TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW    (BIT(3))
+#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S  3
+/** TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW    (BIT(4))
+#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S  4
+/** TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW    (BIT(5))
+#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S  5
+/** TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW    (BIT(6))
+#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S  6
+/** TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW    (BIT(7))
+#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S  7
+/** TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S  8
+/** TEE_REG_HP_CORE0_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW    (BIT(9))
+#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S  9
+/** TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW    (BIT(10))
+#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S  10
+/** TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW    (BIT(11))
+#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S  11
+/** TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW    (BIT(12))
+#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S  12
+/** TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW    (BIT(13))
+#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S  13
+/** TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW    (BIT(14))
+#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S  14
+/** TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW    (BIT(15))
+#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S  15
+/** TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW    (BIT(16))
+#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S  16
+/** TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW    (BIT(17))
+#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S  17
+/** TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW    (BIT(18))
+#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S  18
+/** TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW    (BIT(19))
+#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S  19
+/** TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW    (BIT(20))
+#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_M  (TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S  20
+/** TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW    (BIT(21))
+#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S  21
+/** TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW    (BIT(22))
+#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S  22
+/** TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW    (BIT(23))
+#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S  23
+/** TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW    (BIT(24))
+#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_S  24
+
+/** TEE_HP_CORE1_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_HP_CORE1_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x10)
+/** TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S  0
+/** TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S  1
+/** TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW    (BIT(2))
+#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S  2
+/** TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S  3
+/** TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW    (BIT(4))
+#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S  4
+/** TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW    (BIT(5))
+#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S  5
+/** TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S  6
+/** TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW    (BIT(7))
+#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S  7
+/** TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S  8
+/** TEE_REG_HP_CORE1_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW    (BIT(9))
+#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S  9
+/** TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW    (BIT(10))
+#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S  10
+/** TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW    (BIT(11))
+#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S  11
+/** TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S  12
+/** TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW    (BIT(13))
+#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S  13
+/** TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW    (BIT(14))
+#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S  14
+/** TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S  15
+/** TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S  16
+/** TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW    (BIT(17))
+#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S  17
+/** TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S  18
+/** TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW    (BIT(19))
+#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S  19
+/** TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_M  (TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S  20
+/** TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW    (BIT(21))
+#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S  21
+/** TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW    (BIT(22))
+#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S  22
+/** TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW    (BIT(23))
+#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S  23
+/** TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW    (BIT(24))
+#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_S  24
+
+/** TEE_HP_CORE1_UM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_HP_CORE1_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x14)
+/** TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW    (BIT(0))
+#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S  0
+/** TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S  1
+/** TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW    (BIT(2))
+#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S  2
+/** TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW    (BIT(3))
+#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S  3
+/** TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW    (BIT(4))
+#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S  4
+/** TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW    (BIT(5))
+#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S  5
+/** TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW    (BIT(6))
+#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S  6
+/** TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW    (BIT(7))
+#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S  7
+/** TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S  8
+/** TEE_REG_HP_CORE1_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW    (BIT(9))
+#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S  9
+/** TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW    (BIT(10))
+#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S  10
+/** TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW    (BIT(11))
+#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S  11
+/** TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW    (BIT(12))
+#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S  12
+/** TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW    (BIT(13))
+#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S  13
+/** TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW    (BIT(14))
+#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S  14
+/** TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW    (BIT(15))
+#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S  15
+/** TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW    (BIT(16))
+#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S  16
+/** TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW    (BIT(17))
+#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S  17
+/** TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW    (BIT(18))
+#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S  18
+/** TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW    (BIT(19))
+#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S  19
+/** TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW    (BIT(20))
+#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_M  (TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S  20
+/** TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW    (BIT(21))
+#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S  21
+/** TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW    (BIT(22))
+#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S  22
+/** TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW    (BIT(23))
+#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S  23
+/** TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW    (BIT(24))
+#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_S  24
+
+/** TEE_REGDMA_PERI_PMS_REG register
+ *  NA
+ */
+#define TEE_REGDMA_PERI_PMS_REG (DR_REG_TEE_BASE + 0x18)
+/** TEE_REG_REGDMA_PERI_LP_RAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW    (BIT(0))
+#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_M  (TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V << TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S)
+#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S  0
+/** TEE_REG_REGDMA_PERI_LP_PERI_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW    (BIT(1))
+#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_M  (TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V << TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S)
+#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V  0x00000001U
+#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_reg.h
new file mode 100644
index 0000000000..3bebeb4ce4
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_reg.h
@@ -0,0 +1,969 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMS_HP2LP_PERI_PMS_DATE_REG register
+ *  Version control register
+ */
+#define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x0)
+/** PMS_HP2LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
+ *  Version control register
+ */
+#define PMS_HP2LP_PERI_PMS_DATE    0xFFFFFFFFU
+#define PMS_HP2LP_PERI_PMS_DATE_M  (PMS_HP2LP_PERI_PMS_DATE_V << PMS_HP2LP_PERI_PMS_DATE_S)
+#define PMS_HP2LP_PERI_PMS_DATE_V  0xFFFFFFFFU
+#define PMS_HP2LP_PERI_PMS_DATE_S  0
+
+/** PMS_HP2LP_PERI_PMS_CLK_EN_REG register
+ *  Clock gating register
+ */
+#define PMS_HP2LP_PERI_PMS_CLK_EN_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x4)
+/** PMS_HP2LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating
+ *  1: Keep the clock always on
+ */
+#define PMS_HP2LP_PERI_PMS_CLK_EN    (BIT(0))
+#define PMS_HP2LP_PERI_PMS_CLK_EN_M  (PMS_HP2LP_PERI_PMS_CLK_EN_V << PMS_HP2LP_PERI_PMS_CLK_EN_S)
+#define PMS_HP2LP_PERI_PMS_CLK_EN_V  0x00000001U
+#define PMS_HP2LP_PERI_PMS_CLK_EN_S  0
+
+/** PMS_HP_CORE0_MM_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU0 in machine mode
+ */
+#define PMS_HP_CORE0_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x8)
+/** PMS_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP System
+ *  Registers.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_M  (PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_V << PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_S  0
+/** PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP_AONCLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_M  (PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_HP_CORE0_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW_M  (PMS_HP_CORE0_MM_LP_TIMER_ALLOW_V << PMS_HP_CORE0_MM_LP_TIMER_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW_S  2
+/** PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP ANAPERI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_M  (PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_S  3
+/** PMS_HP_CORE0_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP PMU.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_HP_CORE0_MM_LP_PMU_ALLOW_M  (PMS_HP_CORE0_MM_LP_PMU_ALLOW_V << PMS_HP_CORE0_MM_LP_PMU_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_PMU_ALLOW_S  4
+/** PMS_HP_CORE0_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP WDT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_HP_CORE0_MM_LP_WDT_ALLOW_M  (PMS_HP_CORE0_MM_LP_WDT_ALLOW_V << PMS_HP_CORE0_MM_LP_WDT_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_WDT_ALLOW_S  5
+/** PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_M  (PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_S  6
+/** PMS_HP_CORE0_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE0_MM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_HP_CORE0_MM_LP_RTC_ALLOW_M  (PMS_HP_CORE0_MM_LP_RTC_ALLOW_V << PMS_HP_CORE0_MM_LP_RTC_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_RTC_ALLOW_S  7
+/** PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP PERICLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_M  (PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_HP_CORE0_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP UART.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_UART_ALLOW    (BIT(9))
+#define PMS_HP_CORE0_MM_LP_UART_ALLOW_M  (PMS_HP_CORE0_MM_LP_UART_ALLOW_V << PMS_HP_CORE0_MM_LP_UART_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_UART_ALLOW_S  9
+/** PMS_HP_CORE0_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP I2C.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_HP_CORE0_MM_LP_I2C_ALLOW_M  (PMS_HP_CORE0_MM_LP_I2C_ALLOW_V << PMS_HP_CORE0_MM_LP_I2C_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_I2C_ALLOW_S  10
+/** PMS_HP_CORE0_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_HP_CORE0_MM_LP_SPI_ALLOW_M  (PMS_HP_CORE0_MM_LP_SPI_ALLOW_V << PMS_HP_CORE0_MM_LP_SPI_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_SPI_ALLOW_S  11
+/** PMS_HP_CORE0_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_M  (PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_V << PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_S  12
+/** PMS_HP_CORE0_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_HP_CORE0_MM_LP_I2S_ALLOW_M  (PMS_HP_CORE0_MM_LP_I2S_ALLOW_V << PMS_HP_CORE0_MM_LP_I2S_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_I2S_ALLOW_S  13
+/** PMS_HP_CORE0_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_HP_CORE0_MM_LP_ADC_ALLOW_M  (PMS_HP_CORE0_MM_LP_ADC_ALLOW_V << PMS_HP_CORE0_MM_LP_ADC_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_ADC_ALLOW_S  14
+/** PMS_HP_CORE0_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP touch
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_M  (PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_V << PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_S  15
+/** PMS_HP_CORE0_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_M  (PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_V << PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_S  16
+/** PMS_HP_CORE0_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP INTR.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_HP_CORE0_MM_LP_INTR_ALLOW_M  (PMS_HP_CORE0_MM_LP_INTR_ALLOW_V << PMS_HP_CORE0_MM_LP_INTR_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_INTR_ALLOW_S  17
+/** PMS_HP_CORE0_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_M  (PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_V << PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_S  18
+/** PMS_HP_CORE0_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access
+ *  LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_HP_CORE0_MM_LP_PMS_ALLOW_M  (PMS_HP_CORE0_MM_LP_PMS_ALLOW_V << PMS_HP_CORE0_MM_LP_PMS_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_PMS_ALLOW_S  19
+/** PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_M  (PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_S)
+#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_S  20
+/** PMS_HP_CORE0_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW_M  (PMS_HP_CORE0_MM_LP_TSENS_ALLOW_V << PMS_HP_CORE0_MM_LP_TSENS_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW_S  21
+/** PMS_HP_CORE0_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to LP HUK.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_HP_CORE0_MM_LP_HUK_ALLOW_M  (PMS_HP_CORE0_MM_LP_HUK_ALLOW_V << PMS_HP_CORE0_MM_LP_HUK_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_HUK_ALLOW_S  22
+/** PMS_HP_CORE0_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_M  (PMS_HP_CORE0_MM_LP_SRAM_ALLOW_V << PMS_HP_CORE0_MM_LP_SRAM_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_S  23
+
+/** PMS_HP_CORE0_UM_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU0 in user mode
+ */
+#define PMS_HP_CORE0_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0xc)
+/** PMS_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP System
+ *  Registers.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_M  (PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_V << PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_S  0
+/** PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP_AONCLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_M  (PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_HP_CORE0_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW_M  (PMS_HP_CORE0_UM_LP_TIMER_ALLOW_V << PMS_HP_CORE0_UM_LP_TIMER_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW_S  2
+/** PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP ANAPERI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_M  (PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_S  3
+/** PMS_HP_CORE0_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP PMU.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_HP_CORE0_UM_LP_PMU_ALLOW_M  (PMS_HP_CORE0_UM_LP_PMU_ALLOW_V << PMS_HP_CORE0_UM_LP_PMU_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_PMU_ALLOW_S  4
+/** PMS_HP_CORE0_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP WDT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_HP_CORE0_UM_LP_WDT_ALLOW_M  (PMS_HP_CORE0_UM_LP_WDT_ALLOW_V << PMS_HP_CORE0_UM_LP_WDT_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_WDT_ALLOW_S  5
+/** PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_M  (PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_S  6
+/** PMS_HP_CORE0_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE0_UM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_HP_CORE0_UM_LP_RTC_ALLOW_M  (PMS_HP_CORE0_UM_LP_RTC_ALLOW_V << PMS_HP_CORE0_UM_LP_RTC_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_RTC_ALLOW_S  7
+/** PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP PERICLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_M  (PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_HP_CORE0_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP UART.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_UART_ALLOW    (BIT(9))
+#define PMS_HP_CORE0_UM_LP_UART_ALLOW_M  (PMS_HP_CORE0_UM_LP_UART_ALLOW_V << PMS_HP_CORE0_UM_LP_UART_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_UART_ALLOW_S  9
+/** PMS_HP_CORE0_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP I2C.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_HP_CORE0_UM_LP_I2C_ALLOW_M  (PMS_HP_CORE0_UM_LP_I2C_ALLOW_V << PMS_HP_CORE0_UM_LP_I2C_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_I2C_ALLOW_S  10
+/** PMS_HP_CORE0_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_HP_CORE0_UM_LP_SPI_ALLOW_M  (PMS_HP_CORE0_UM_LP_SPI_ALLOW_V << PMS_HP_CORE0_UM_LP_SPI_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_SPI_ALLOW_S  11
+/** PMS_HP_CORE0_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_M  (PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_V << PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_S  12
+/** PMS_HP_CORE0_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_HP_CORE0_UM_LP_I2S_ALLOW_M  (PMS_HP_CORE0_UM_LP_I2S_ALLOW_V << PMS_HP_CORE0_UM_LP_I2S_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_I2S_ALLOW_S  13
+/** PMS_HP_CORE0_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_HP_CORE0_UM_LP_ADC_ALLOW_M  (PMS_HP_CORE0_UM_LP_ADC_ALLOW_V << PMS_HP_CORE0_UM_LP_ADC_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_ADC_ALLOW_S  14
+/** PMS_HP_CORE0_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP touch sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_M  (PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_V << PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_S  15
+/** PMS_HP_CORE0_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_M  (PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_V << PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_S  16
+/** PMS_HP_CORE0_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP INTR.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_HP_CORE0_UM_LP_INTR_ALLOW_M  (PMS_HP_CORE0_UM_LP_INTR_ALLOW_V << PMS_HP_CORE0_UM_LP_INTR_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_INTR_ALLOW_S  17
+/** PMS_HP_CORE0_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_M  (PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_V << PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_S  18
+/** PMS_HP_CORE0_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_HP_CORE0_UM_LP_PMS_ALLOW_M  (PMS_HP_CORE0_UM_LP_PMS_ALLOW_V << PMS_HP_CORE0_UM_LP_PMS_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_PMS_ALLOW_S  19
+/** PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_M  (PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_S)
+#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_S  20
+/** PMS_HP_CORE0_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW_M  (PMS_HP_CORE0_UM_LP_TSENS_ALLOW_V << PMS_HP_CORE0_UM_LP_TSENS_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW_S  21
+/** PMS_HP_CORE0_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to LP HUK.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_HP_CORE0_UM_LP_HUK_ALLOW_M  (PMS_HP_CORE0_UM_LP_HUK_ALLOW_V << PMS_HP_CORE0_UM_LP_HUK_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_HUK_ALLOW_S  22
+/** PMS_HP_CORE0_UM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_M  (PMS_HP_CORE0_UM_LP_SRAM_ALLOW_V << PMS_HP_CORE0_UM_LP_SRAM_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_S  23
+
+/** PMS_HP_CORE1_MM_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU1 in machine mode
+ */
+#define PMS_HP_CORE1_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x10)
+/** PMS_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP System
+ *  Registers.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_M  (PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_V << PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_S  0
+/** PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP_AONCLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_M  (PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_HP_CORE1_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW_M  (PMS_HP_CORE1_MM_LP_TIMER_ALLOW_V << PMS_HP_CORE1_MM_LP_TIMER_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW_S  2
+/** PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP ANAPERI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_M  (PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_S  3
+/** PMS_HP_CORE1_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP PMU.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_HP_CORE1_MM_LP_PMU_ALLOW_M  (PMS_HP_CORE1_MM_LP_PMU_ALLOW_V << PMS_HP_CORE1_MM_LP_PMU_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_PMU_ALLOW_S  4
+/** PMS_HP_CORE1_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP WDT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_HP_CORE1_MM_LP_WDT_ALLOW_M  (PMS_HP_CORE1_MM_LP_WDT_ALLOW_V << PMS_HP_CORE1_MM_LP_WDT_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_WDT_ALLOW_S  5
+/** PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_M  (PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_S  6
+/** PMS_HP_CORE1_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE1_MM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_HP_CORE1_MM_LP_RTC_ALLOW_M  (PMS_HP_CORE1_MM_LP_RTC_ALLOW_V << PMS_HP_CORE1_MM_LP_RTC_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_RTC_ALLOW_S  7
+/** PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP PERICLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_M  (PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_HP_CORE1_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP UART.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_UART_ALLOW    (BIT(9))
+#define PMS_HP_CORE1_MM_LP_UART_ALLOW_M  (PMS_HP_CORE1_MM_LP_UART_ALLOW_V << PMS_HP_CORE1_MM_LP_UART_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_UART_ALLOW_S  9
+/** PMS_HP_CORE1_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP I2C.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_HP_CORE1_MM_LP_I2C_ALLOW_M  (PMS_HP_CORE1_MM_LP_I2C_ALLOW_V << PMS_HP_CORE1_MM_LP_I2C_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_I2C_ALLOW_S  10
+/** PMS_HP_CORE1_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_HP_CORE1_MM_LP_SPI_ALLOW_M  (PMS_HP_CORE1_MM_LP_SPI_ALLOW_V << PMS_HP_CORE1_MM_LP_SPI_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_SPI_ALLOW_S  11
+/** PMS_HP_CORE1_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_M  (PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_V << PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_S  12
+/** PMS_HP_CORE1_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_HP_CORE1_MM_LP_I2S_ALLOW_M  (PMS_HP_CORE1_MM_LP_I2S_ALLOW_V << PMS_HP_CORE1_MM_LP_I2S_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_I2S_ALLOW_S  13
+/** PMS_HP_CORE1_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_HP_CORE1_MM_LP_ADC_ALLOW_M  (PMS_HP_CORE1_MM_LP_ADC_ALLOW_V << PMS_HP_CORE1_MM_LP_ADC_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_ADC_ALLOW_S  14
+/** PMS_HP_CORE1_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP touch
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_M  (PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_V << PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_S  15
+/** PMS_HP_CORE1_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_M  (PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_V << PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_S  16
+/** PMS_HP_CORE1_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP INTR.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_HP_CORE1_MM_LP_INTR_ALLOW_M  (PMS_HP_CORE1_MM_LP_INTR_ALLOW_V << PMS_HP_CORE1_MM_LP_INTR_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_INTR_ALLOW_S  17
+/** PMS_HP_CORE1_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_M  (PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_V << PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_S  18
+/** PMS_HP_CORE1_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access
+ *  LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_HP_CORE1_MM_LP_PMS_ALLOW_M  (PMS_HP_CORE1_MM_LP_PMS_ALLOW_V << PMS_HP_CORE1_MM_LP_PMS_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_PMS_ALLOW_S  19
+/** PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_M  (PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_S)
+#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_S  20
+/** PMS_HP_CORE1_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW_M  (PMS_HP_CORE1_MM_LP_TSENS_ALLOW_V << PMS_HP_CORE1_MM_LP_TSENS_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW_S  21
+/** PMS_HP_CORE1_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to LP HUK.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_HP_CORE1_MM_LP_HUK_ALLOW_M  (PMS_HP_CORE1_MM_LP_HUK_ALLOW_V << PMS_HP_CORE1_MM_LP_HUK_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_HUK_ALLOW_S  22
+/** PMS_HP_CORE1_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_M  (PMS_HP_CORE1_MM_LP_SRAM_ALLOW_V << PMS_HP_CORE1_MM_LP_SRAM_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_S  23
+
+/** PMS_HP_CORE1_UM_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU1 in user mode
+ */
+#define PMS_HP_CORE1_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x14)
+/** PMS_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP System
+ *  Registers.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_M  (PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_V << PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_S  0
+/** PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP_AONCLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_M  (PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_HP_CORE1_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW_M  (PMS_HP_CORE1_UM_LP_TIMER_ALLOW_V << PMS_HP_CORE1_UM_LP_TIMER_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW_S  2
+/** PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP ANAPERI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_M  (PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_S  3
+/** PMS_HP_CORE1_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP PMU.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_HP_CORE1_UM_LP_PMU_ALLOW_M  (PMS_HP_CORE1_UM_LP_PMU_ALLOW_V << PMS_HP_CORE1_UM_LP_PMU_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_PMU_ALLOW_S  4
+/** PMS_HP_CORE1_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP WDT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_HP_CORE1_UM_LP_WDT_ALLOW_M  (PMS_HP_CORE1_UM_LP_WDT_ALLOW_V << PMS_HP_CORE1_UM_LP_WDT_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_WDT_ALLOW_S  5
+/** PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_M  (PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_S  6
+/** PMS_HP_CORE1_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE1_UM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_HP_CORE1_UM_LP_RTC_ALLOW_M  (PMS_HP_CORE1_UM_LP_RTC_ALLOW_V << PMS_HP_CORE1_UM_LP_RTC_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_RTC_ALLOW_S  7
+/** PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP PERICLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_M  (PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_HP_CORE1_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP UART.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_UART_ALLOW    (BIT(9))
+#define PMS_HP_CORE1_UM_LP_UART_ALLOW_M  (PMS_HP_CORE1_UM_LP_UART_ALLOW_V << PMS_HP_CORE1_UM_LP_UART_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_UART_ALLOW_S  9
+/** PMS_HP_CORE1_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP I2C.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_HP_CORE1_UM_LP_I2C_ALLOW_M  (PMS_HP_CORE1_UM_LP_I2C_ALLOW_V << PMS_HP_CORE1_UM_LP_I2C_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_I2C_ALLOW_S  10
+/** PMS_HP_CORE1_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_HP_CORE1_UM_LP_SPI_ALLOW_M  (PMS_HP_CORE1_UM_LP_SPI_ALLOW_V << PMS_HP_CORE1_UM_LP_SPI_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_SPI_ALLOW_S  11
+/** PMS_HP_CORE1_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_M  (PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_V << PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_S  12
+/** PMS_HP_CORE1_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_HP_CORE1_UM_LP_I2S_ALLOW_M  (PMS_HP_CORE1_UM_LP_I2S_ALLOW_V << PMS_HP_CORE1_UM_LP_I2S_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_I2S_ALLOW_S  13
+/** PMS_HP_CORE1_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_HP_CORE1_UM_LP_ADC_ALLOW_M  (PMS_HP_CORE1_UM_LP_ADC_ALLOW_V << PMS_HP_CORE1_UM_LP_ADC_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_ADC_ALLOW_S  14
+/** PMS_HP_CORE1_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP touch sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_M  (PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_V << PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_S  15
+/** PMS_HP_CORE1_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_M  (PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_V << PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_S  16
+/** PMS_HP_CORE1_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP INTR.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_HP_CORE1_UM_LP_INTR_ALLOW_M  (PMS_HP_CORE1_UM_LP_INTR_ALLOW_V << PMS_HP_CORE1_UM_LP_INTR_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_INTR_ALLOW_S  17
+/** PMS_HP_CORE1_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_M  (PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_V << PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_S  18
+/** PMS_HP_CORE1_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_HP_CORE1_UM_LP_PMS_ALLOW_M  (PMS_HP_CORE1_UM_LP_PMS_ALLOW_V << PMS_HP_CORE1_UM_LP_PMS_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_PMS_ALLOW_S  19
+/** PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_M  (PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_S)
+#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_S  20
+/** PMS_HP_CORE1_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW_M  (PMS_HP_CORE1_UM_LP_TSENS_ALLOW_V << PMS_HP_CORE1_UM_LP_TSENS_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW_S  21
+/** PMS_HP_CORE1_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to LP HUK.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_HP_CORE1_UM_LP_HUK_ALLOW_M  (PMS_HP_CORE1_UM_LP_HUK_ALLOW_V << PMS_HP_CORE1_UM_LP_HUK_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_HUK_ALLOW_S  22
+/** PMS_HP_CORE1_UM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_M  (PMS_HP_CORE1_UM_LP_SRAM_ALLOW_V << PMS_HP_CORE1_UM_LP_SRAM_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_S  23
+
+/** PMS_REGDMA_LP_PERI_PMS_REG register
+ *  LP Peripheral Permission register for REGDMA
+ */
+#define PMS_REGDMA_LP_PERI_PMS_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x18)
+/** PMS_REGDMA_PERI_LP_SRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether REGDMA has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_REGDMA_PERI_LP_SRAM_ALLOW    (BIT(0))
+#define PMS_REGDMA_PERI_LP_SRAM_ALLOW_M  (PMS_REGDMA_PERI_LP_SRAM_ALLOW_V << PMS_REGDMA_PERI_LP_SRAM_ALLOW_S)
+#define PMS_REGDMA_PERI_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_REGDMA_PERI_LP_SRAM_ALLOW_S  0
+/** PMS_REGDMA_PERI_LP_PERI_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether REGDMA has permission to access  all LP peripherals.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_REGDMA_PERI_LP_PERI_ALLOW    (BIT(1))
+#define PMS_REGDMA_PERI_LP_PERI_ALLOW_M  (PMS_REGDMA_PERI_LP_PERI_ALLOW_V << PMS_REGDMA_PERI_LP_PERI_ALLOW_S)
+#define PMS_REGDMA_PERI_LP_PERI_ALLOW_V  0x00000001U
+#define PMS_REGDMA_PERI_LP_PERI_ALLOW_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_struct.h
new file mode 100644
index 0000000000..7ec7f73652
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_struct.h
@@ -0,0 +1,530 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: TEE HP2LP TEE PMS DATE REG */
+/** Type of hp2lp_tee_pms_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tee_date : R/W; bitpos: [31:0]; default: 2363943;
+         *  NA
+         */
+        uint32_t tee_date:32;
+    };
+    uint32_t val;
+} tee_hp2lp_tee_pms_date_reg_t;
+
+
+/** Group: TEE PMS CLK EN REG */
+/** Type of pms_clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_pms_clk_en_reg_t;
+
+
+/** Group: TEE HP CORE0 MM PMS REG0 REG */
+/** Type of hp_core0_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_core0_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_sysreg_allow:1;
+        /** reg_hp_core0_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_aonclkrst_allow:1;
+        /** reg_hp_core0_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_timer_allow:1;
+        /** reg_hp_core0_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_anaperi_allow:1;
+        /** reg_hp_core0_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_pmu_allow:1;
+        /** reg_hp_core0_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_wdt_allow:1;
+        /** reg_hp_core0_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_mailbox_allow:1;
+        /** reg_hp_core0_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_rtc_allow:1;
+        /** reg_hp_core0_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_periclkrst_allow:1;
+        /** reg_hp_core0_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_uart_allow:1;
+        /** reg_hp_core0_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_i2c_allow:1;
+        /** reg_hp_core0_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_spi_allow:1;
+        /** reg_hp_core0_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_i2cmst_allow:1;
+        /** reg_hp_core0_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_i2s_allow:1;
+        /** reg_hp_core0_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_adc_allow:1;
+        /** reg_hp_core0_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_touch_allow:1;
+        /** reg_hp_core0_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_iomux_allow:1;
+        /** reg_hp_core0_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_intr_allow:1;
+        /** reg_hp_core0_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_efuse_allow:1;
+        /** reg_hp_core0_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_pms_allow:1;
+        /** reg_hp_core0_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_hp2lp_pms_allow:1;
+        /** reg_hp_core0_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_tsens_allow:1;
+        /** reg_hp_core0_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_huk_allow:1;
+        /** reg_hp_core0_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_tcm_ram_allow:1;
+        /** reg_hp_core0_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_trng_allow:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} tee_hp_core0_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE HP CORE0 UM PMS REG0 REG */
+/** Type of hp_core0_um_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_core0_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_sysreg_allow:1;
+        /** reg_hp_core0_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_aonclkrst_allow:1;
+        /** reg_hp_core0_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_timer_allow:1;
+        /** reg_hp_core0_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_anaperi_allow:1;
+        /** reg_hp_core0_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_pmu_allow:1;
+        /** reg_hp_core0_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_wdt_allow:1;
+        /** reg_hp_core0_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_mailbox_allow:1;
+        /** reg_hp_core0_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_rtc_allow:1;
+        /** reg_hp_core0_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_periclkrst_allow:1;
+        /** reg_hp_core0_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_uart_allow:1;
+        /** reg_hp_core0_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_i2c_allow:1;
+        /** reg_hp_core0_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_spi_allow:1;
+        /** reg_hp_core0_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_i2cmst_allow:1;
+        /** reg_hp_core0_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_i2s_allow:1;
+        /** reg_hp_core0_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_adc_allow:1;
+        /** reg_hp_core0_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_touch_allow:1;
+        /** reg_hp_core0_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_iomux_allow:1;
+        /** reg_hp_core0_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_intr_allow:1;
+        /** reg_hp_core0_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_efuse_allow:1;
+        /** reg_hp_core0_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_pms_allow:1;
+        /** reg_hp_core0_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_hp2lp_pms_allow:1;
+        /** reg_hp_core0_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_tsens_allow:1;
+        /** reg_hp_core0_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_huk_allow:1;
+        /** reg_hp_core0_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_tcm_ram_allow:1;
+        /** reg_hp_core0_um_lp_trng_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_trng_allow:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} tee_hp_core0_um_pms_reg0_reg_t;
+
+
+/** Group: TEE HP CORE1 MM PMS REG0 REG */
+/** Type of hp_core1_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_core1_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_sysreg_allow:1;
+        /** reg_hp_core1_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_aonclkrst_allow:1;
+        /** reg_hp_core1_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_timer_allow:1;
+        /** reg_hp_core1_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_anaperi_allow:1;
+        /** reg_hp_core1_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_pmu_allow:1;
+        /** reg_hp_core1_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_wdt_allow:1;
+        /** reg_hp_core1_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_mailbox_allow:1;
+        /** reg_hp_core1_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_rtc_allow:1;
+        /** reg_hp_core1_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_periclkrst_allow:1;
+        /** reg_hp_core1_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_uart_allow:1;
+        /** reg_hp_core1_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_i2c_allow:1;
+        /** reg_hp_core1_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_spi_allow:1;
+        /** reg_hp_core1_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_i2cmst_allow:1;
+        /** reg_hp_core1_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_i2s_allow:1;
+        /** reg_hp_core1_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_adc_allow:1;
+        /** reg_hp_core1_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_touch_allow:1;
+        /** reg_hp_core1_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_iomux_allow:1;
+        /** reg_hp_core1_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_intr_allow:1;
+        /** reg_hp_core1_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_efuse_allow:1;
+        /** reg_hp_core1_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_pms_allow:1;
+        /** reg_hp_core1_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_hp2lp_pms_allow:1;
+        /** reg_hp_core1_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_tsens_allow:1;
+        /** reg_hp_core1_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_huk_allow:1;
+        /** reg_hp_core1_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_tcm_ram_allow:1;
+        /** reg_hp_core1_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_trng_allow:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} tee_hp_core1_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE HP CORE1 UM PMS REG0 REG */
+/** Type of hp_core1_um_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_core1_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_sysreg_allow:1;
+        /** reg_hp_core1_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_aonclkrst_allow:1;
+        /** reg_hp_core1_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_timer_allow:1;
+        /** reg_hp_core1_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_anaperi_allow:1;
+        /** reg_hp_core1_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_pmu_allow:1;
+        /** reg_hp_core1_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_wdt_allow:1;
+        /** reg_hp_core1_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_mailbox_allow:1;
+        /** reg_hp_core1_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_rtc_allow:1;
+        /** reg_hp_core1_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_periclkrst_allow:1;
+        /** reg_hp_core1_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_uart_allow:1;
+        /** reg_hp_core1_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_i2c_allow:1;
+        /** reg_hp_core1_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_spi_allow:1;
+        /** reg_hp_core1_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_i2cmst_allow:1;
+        /** reg_hp_core1_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_i2s_allow:1;
+        /** reg_hp_core1_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_adc_allow:1;
+        /** reg_hp_core1_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_touch_allow:1;
+        /** reg_hp_core1_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_iomux_allow:1;
+        /** reg_hp_core1_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_intr_allow:1;
+        /** reg_hp_core1_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_efuse_allow:1;
+        /** reg_hp_core1_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_pms_allow:1;
+        /** reg_hp_core1_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_hp2lp_pms_allow:1;
+        /** reg_hp_core1_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_tsens_allow:1;
+        /** reg_hp_core1_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_huk_allow:1;
+        /** reg_hp_core1_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_tcm_ram_allow:1;
+        /** reg_hp_core1_um_lp_trng_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_trng_allow:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} tee_hp_core1_um_pms_reg0_reg_t;
+
+
+/** Group: TEE REGDMA PERI PMS REG */
+/** Type of regdma_peri_pms register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_regdma_peri_lp_ram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_regdma_peri_lp_ram_allow:1;
+        /** reg_regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_regdma_peri_lp_peri_allow:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_regdma_peri_pms_reg_t;
+
+
+typedef struct {
+    volatile tee_hp2lp_tee_pms_date_reg_t hp2lp_tee_pms_date;
+    volatile tee_pms_clk_en_reg_t pms_clk_en;
+    volatile tee_hp_core0_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0;
+    volatile tee_hp_core0_um_pms_reg0_reg_t hp_core0_um_pms_reg0;
+    volatile tee_hp_core1_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0;
+    volatile tee_hp_core1_um_pms_reg0_reg_t hp_core1_um_pms_reg0;
+    volatile tee_regdma_peri_pms_reg_t regdma_peri_pms;
+} tee_dev_t;
+
+extern tee_dev_t HP2LP_PERI_PMS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dev_t) == 0x1c, "Invalid size of tee_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h
new file mode 100644
index 0000000000..cc55fc066c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h
@@ -0,0 +1,2232 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_PMS_DATE_REG register
+ *  NA
+ */
+#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
+/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
+ *  NA
+ */
+#define TEE_TEE_DATE    0xFFFFFFFFU
+#define TEE_TEE_DATE_M  (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
+#define TEE_TEE_DATE_V  0xFFFFFFFFU
+#define TEE_TEE_DATE_S  0
+
+/** TEE_PMS_CLK_EN_REG register
+ *  NA
+ */
+#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
+/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CLK_EN    (BIT(0))
+#define TEE_REG_CLK_EN_M  (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
+#define TEE_REG_CLK_EN_V  0x00000001U
+#define TEE_REG_CLK_EN_S  0
+
+/** TEE_CORE0_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_CORE0_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
+/** TEE_REG_CORE0_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_PSRAM_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_MM_PSRAM_ALLOW_M  (TEE_REG_CORE0_MM_PSRAM_ALLOW_V << TEE_REG_CORE0_MM_PSRAM_ALLOW_S)
+#define TEE_REG_CORE0_MM_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_PSRAM_ALLOW_S  0
+/** TEE_REG_CORE0_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_FLASH_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_MM_FLASH_ALLOW_M  (TEE_REG_CORE0_MM_FLASH_ALLOW_V << TEE_REG_CORE0_MM_FLASH_ALLOW_S)
+#define TEE_REG_CORE0_MM_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_FLASH_ALLOW_S  1
+/** TEE_REG_CORE0_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_L2MEM_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_MM_L2MEM_ALLOW_M  (TEE_REG_CORE0_MM_L2MEM_ALLOW_V << TEE_REG_CORE0_MM_L2MEM_ALLOW_S)
+#define TEE_REG_CORE0_MM_L2MEM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_L2MEM_ALLOW_S  2
+/** TEE_REG_CORE0_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_L2ROM_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_MM_L2ROM_ALLOW_M  (TEE_REG_CORE0_MM_L2ROM_ALLOW_V << TEE_REG_CORE0_MM_L2ROM_ALLOW_S)
+#define TEE_REG_CORE0_MM_L2ROM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_L2ROM_ALLOW_S  3
+/** TEE_REG_CORE0_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_TRACE0_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_MM_TRACE0_ALLOW_M  (TEE_REG_CORE0_MM_TRACE0_ALLOW_V << TEE_REG_CORE0_MM_TRACE0_ALLOW_S)
+#define TEE_REG_CORE0_MM_TRACE0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_TRACE0_ALLOW_S  6
+/** TEE_REG_CORE0_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_TRACE1_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_MM_TRACE1_ALLOW_M  (TEE_REG_CORE0_MM_TRACE1_ALLOW_V << TEE_REG_CORE0_MM_TRACE1_ALLOW_S)
+#define TEE_REG_CORE0_MM_TRACE1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_TRACE1_ALLOW_S  7
+/** TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_M  (TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_S)
+#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_S  8
+/** TEE_REG_CORE0_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_M  (TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_V << TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_S)
+#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_S  9
+/** TEE_REG_CORE0_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_TCM_MON_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_MM_TCM_MON_ALLOW_M  (TEE_REG_CORE0_MM_TCM_MON_ALLOW_V << TEE_REG_CORE0_MM_TCM_MON_ALLOW_S)
+#define TEE_REG_CORE0_MM_TCM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_TCM_MON_ALLOW_S  10
+/** TEE_REG_CORE0_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_CACHE_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_MM_CACHE_ALLOW_M  (TEE_REG_CORE0_MM_CACHE_ALLOW_V << TEE_REG_CORE0_MM_CACHE_ALLOW_S)
+#define TEE_REG_CORE0_MM_CACHE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_CACHE_ALLOW_S  11
+
+/** TEE_CORE0_MM_PMS_REG1_REG register
+ *  NA
+ */
+#define TEE_CORE0_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0xc)
+/** TEE_REG_CORE0_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_M  (TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_V << TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_S  0
+/** TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_M  (TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_S  1
+/** TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_M  (TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** TEE_REG_CORE0_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW_M  (TEE_REG_CORE0_MM_HP_GDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_GDMA_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW_S  3
+/** TEE_REG_CORE0_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_M  (TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_S  4
+/** TEE_REG_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_M  (TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_V << TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_S  5
+/** TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_M  (TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_S  6
+/** TEE_REG_CORE0_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW_M  (TEE_REG_CORE0_MM_HP_JPEG_ALLOW_V << TEE_REG_CORE0_MM_HP_JPEG_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW_S  7
+/** TEE_REG_CORE0_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PPA_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_MM_HP_PPA_ALLOW_M  (TEE_REG_CORE0_MM_HP_PPA_ALLOW_V << TEE_REG_CORE0_MM_HP_PPA_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PPA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PPA_ALLOW_S  8
+/** TEE_REG_CORE0_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_M  (TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_V << TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_S  9
+/** TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_M  (TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_M  (TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_S  11
+/** TEE_REG_CORE0_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW    (BIT(12))
+#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW_M  (TEE_REG_CORE0_MM_HP_FLASH_ALLOW_V << TEE_REG_CORE0_MM_HP_FLASH_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW_S  12
+/** TEE_REG_CORE0_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_M  (TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_V << TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_S  13
+/** TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_M  (TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_S  14
+/** TEE_REG_CORE0_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW    (BIT(15))
+#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW_M  (TEE_REG_CORE0_MM_HP_GMAC_ALLOW_V << TEE_REG_CORE0_MM_HP_GMAC_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW_S  15
+/** TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_M  (TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_S  16
+/** TEE_REG_CORE0_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PVT_ALLOW    (BIT(17))
+#define TEE_REG_CORE0_MM_HP_PVT_ALLOW_M  (TEE_REG_CORE0_MM_HP_PVT_ALLOW_V << TEE_REG_CORE0_MM_HP_PVT_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PVT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PVT_ALLOW_S  17
+/** TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_M  (TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_S  18
+/** TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_M  (TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_S  19
+/** TEE_REG_CORE0_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_ISP_ALLOW    (BIT(20))
+#define TEE_REG_CORE0_MM_HP_ISP_ALLOW_M  (TEE_REG_CORE0_MM_HP_ISP_ALLOW_V << TEE_REG_CORE0_MM_HP_ISP_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_ISP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_ISP_ALLOW_S  20
+/** TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_M  (TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_S  21
+/** TEE_REG_CORE0_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_RMT_ALLOW    (BIT(22))
+#define TEE_REG_CORE0_MM_HP_RMT_ALLOW_M  (TEE_REG_CORE0_MM_HP_RMT_ALLOW_V << TEE_REG_CORE0_MM_HP_RMT_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_RMT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_RMT_ALLOW_S  22
+/** TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_M  (TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_M  (TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_S  24
+/** TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_S  25
+/** TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** TEE_REG_CORE0_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW    (BIT(27))
+#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW_M  (TEE_REG_CORE0_MM_DMA_PMS_ALLOW_V << TEE_REG_CORE0_MM_DMA_PMS_ALLOW_S)
+#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW_S  27
+/** TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_M  (TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_S  28
+/** TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW    (BIT(29))
+#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_M  (TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_S)
+#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_S  29
+
+/** TEE_CORE0_MM_PMS_REG2_REG register
+ *  NA
+ */
+#define TEE_CORE0_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x10)
+/** TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_M  (TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_S  0
+/** TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_M  (TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_S  1
+/** TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_M  (TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_M  (TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** TEE_REG_CORE0_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW_M  (TEE_REG_CORE0_MM_HP_I2C0_ALLOW_V << TEE_REG_CORE0_MM_HP_I2C0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW_S  4
+/** TEE_REG_CORE0_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW    (BIT(5))
+#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW_M  (TEE_REG_CORE0_MM_HP_I2C1_ALLOW_V << TEE_REG_CORE0_MM_HP_I2C1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW_S  5
+/** TEE_REG_CORE0_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW_M  (TEE_REG_CORE0_MM_HP_I2S0_ALLOW_V << TEE_REG_CORE0_MM_HP_I2S0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW_S  6
+/** TEE_REG_CORE0_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW_M  (TEE_REG_CORE0_MM_HP_I2S1_ALLOW_V << TEE_REG_CORE0_MM_HP_I2S1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW_S  7
+/** TEE_REG_CORE0_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW_M  (TEE_REG_CORE0_MM_HP_I2S2_ALLOW_V << TEE_REG_CORE0_MM_HP_I2S2_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW_S  8
+/** TEE_REG_CORE0_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW_M  (TEE_REG_CORE0_MM_HP_PCNT_ALLOW_V << TEE_REG_CORE0_MM_HP_PCNT_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW_S  9
+/** TEE_REG_CORE0_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UART0_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_MM_HP_UART0_ALLOW_M  (TEE_REG_CORE0_MM_HP_UART0_ALLOW_V << TEE_REG_CORE0_MM_HP_UART0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UART0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UART0_ALLOW_S  10
+/** TEE_REG_CORE0_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UART1_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_MM_HP_UART1_ALLOW_M  (TEE_REG_CORE0_MM_HP_UART1_ALLOW_V << TEE_REG_CORE0_MM_HP_UART1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UART1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UART1_ALLOW_S  11
+/** TEE_REG_CORE0_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UART2_ALLOW    (BIT(12))
+#define TEE_REG_CORE0_MM_HP_UART2_ALLOW_M  (TEE_REG_CORE0_MM_HP_UART2_ALLOW_V << TEE_REG_CORE0_MM_HP_UART2_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UART2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UART2_ALLOW_S  12
+/** TEE_REG_CORE0_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UART3_ALLOW    (BIT(13))
+#define TEE_REG_CORE0_MM_HP_UART3_ALLOW_M  (TEE_REG_CORE0_MM_HP_UART3_ALLOW_V << TEE_REG_CORE0_MM_HP_UART3_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UART3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UART3_ALLOW_S  13
+/** TEE_REG_CORE0_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UART4_ALLOW    (BIT(14))
+#define TEE_REG_CORE0_MM_HP_UART4_ALLOW_M  (TEE_REG_CORE0_MM_HP_UART4_ALLOW_V << TEE_REG_CORE0_MM_HP_UART4_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UART4_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UART4_ALLOW_S  14
+/** TEE_REG_CORE0_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_M  (TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_V << TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_S  15
+/** TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_M  (TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_S  16
+/** TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_M  (TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_S  17
+/** TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_M  (TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_S  18
+/** TEE_REG_CORE0_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW    (BIT(19))
+#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW_M  (TEE_REG_CORE0_MM_HP_LEDC_ALLOW_V << TEE_REG_CORE0_MM_HP_LEDC_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW_S  19
+/** TEE_REG_CORE0_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_ETM_ALLOW    (BIT(21))
+#define TEE_REG_CORE0_MM_HP_ETM_ALLOW_M  (TEE_REG_CORE0_MM_HP_ETM_ALLOW_V << TEE_REG_CORE0_MM_HP_ETM_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_ETM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_ETM_ALLOW_S  21
+/** TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_M  (TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_S  22
+/** TEE_REG_CORE0_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_M  (TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_V << TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_S  23
+/** TEE_REG_CORE0_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_M  (TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_V << TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_S  24
+/** TEE_REG_CORE0_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_M  (TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_V << TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_S  25
+/** TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_M  (TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_S  26
+/** TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_M  (TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_S  27
+/** TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_M  (TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_S  28
+/** TEE_REG_CORE0_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_ADC_ALLOW    (BIT(30))
+#define TEE_REG_CORE0_MM_HP_ADC_ALLOW_M  (TEE_REG_CORE0_MM_HP_ADC_ALLOW_V << TEE_REG_CORE0_MM_HP_ADC_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_ADC_ALLOW_S  30
+/** TEE_REG_CORE0_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW    (BIT(31))
+#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW_M  (TEE_REG_CORE0_MM_HP_UHCI_ALLOW_V << TEE_REG_CORE0_MM_HP_UHCI_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW_S  31
+
+/** TEE_CORE0_MM_PMS_REG3_REG register
+ *  NA
+ */
+#define TEE_CORE0_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x14)
+/** TEE_REG_CORE0_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW_M  (TEE_REG_CORE0_MM_HP_GPIO_ALLOW_V << TEE_REG_CORE0_MM_HP_GPIO_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW_S  0
+/** TEE_REG_CORE0_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_M  (TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_V << TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_S  1
+/** TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_M  (TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_S  2
+/** TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_M  (TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_S  3
+/** TEE_REG_CORE0_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_M  (TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_V << TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_S  4
+
+/** TEE_CORE0_UM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_CORE0_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x18)
+/** TEE_REG_CORE0_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_PSRAM_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_UM_PSRAM_ALLOW_M  (TEE_REG_CORE0_UM_PSRAM_ALLOW_V << TEE_REG_CORE0_UM_PSRAM_ALLOW_S)
+#define TEE_REG_CORE0_UM_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_PSRAM_ALLOW_S  0
+/** TEE_REG_CORE0_UM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_FLASH_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_UM_FLASH_ALLOW_M  (TEE_REG_CORE0_UM_FLASH_ALLOW_V << TEE_REG_CORE0_UM_FLASH_ALLOW_S)
+#define TEE_REG_CORE0_UM_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_FLASH_ALLOW_S  1
+/** TEE_REG_CORE0_UM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_L2MEM_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_UM_L2MEM_ALLOW_M  (TEE_REG_CORE0_UM_L2MEM_ALLOW_V << TEE_REG_CORE0_UM_L2MEM_ALLOW_S)
+#define TEE_REG_CORE0_UM_L2MEM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_L2MEM_ALLOW_S  2
+/** TEE_REG_CORE0_UM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_L2ROM_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_UM_L2ROM_ALLOW_M  (TEE_REG_CORE0_UM_L2ROM_ALLOW_V << TEE_REG_CORE0_UM_L2ROM_ALLOW_S)
+#define TEE_REG_CORE0_UM_L2ROM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_L2ROM_ALLOW_S  3
+/** TEE_REG_CORE0_UM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_TRACE0_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_UM_TRACE0_ALLOW_M  (TEE_REG_CORE0_UM_TRACE0_ALLOW_V << TEE_REG_CORE0_UM_TRACE0_ALLOW_S)
+#define TEE_REG_CORE0_UM_TRACE0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_TRACE0_ALLOW_S  6
+/** TEE_REG_CORE0_UM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_TRACE1_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_UM_TRACE1_ALLOW_M  (TEE_REG_CORE0_UM_TRACE1_ALLOW_V << TEE_REG_CORE0_UM_TRACE1_ALLOW_S)
+#define TEE_REG_CORE0_UM_TRACE1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_TRACE1_ALLOW_S  7
+/** TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_M  (TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_S)
+#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_S  8
+/** TEE_REG_CORE0_UM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_M  (TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_V << TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_S)
+#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_S  9
+/** TEE_REG_CORE0_UM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_TCM_MON_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_UM_TCM_MON_ALLOW_M  (TEE_REG_CORE0_UM_TCM_MON_ALLOW_V << TEE_REG_CORE0_UM_TCM_MON_ALLOW_S)
+#define TEE_REG_CORE0_UM_TCM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_TCM_MON_ALLOW_S  10
+/** TEE_REG_CORE0_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_CACHE_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_UM_CACHE_ALLOW_M  (TEE_REG_CORE0_UM_CACHE_ALLOW_V << TEE_REG_CORE0_UM_CACHE_ALLOW_S)
+#define TEE_REG_CORE0_UM_CACHE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_CACHE_ALLOW_S  11
+
+/** TEE_CORE0_UM_PMS_REG1_REG register
+ *  NA
+ */
+#define TEE_CORE0_UM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x1c)
+/** TEE_REG_CORE0_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_M  (TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_V << TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_S  0
+/** TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_M  (TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_S  1
+/** TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_M  (TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** TEE_REG_CORE0_UM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW_M  (TEE_REG_CORE0_UM_HP_GDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_GDMA_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW_S  3
+/** TEE_REG_CORE0_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_M  (TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_S  4
+/** TEE_REG_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW    (BIT(5))
+#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_M  (TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_V << TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_S  5
+/** TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_M  (TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_S  6
+/** TEE_REG_CORE0_UM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW_M  (TEE_REG_CORE0_UM_HP_JPEG_ALLOW_V << TEE_REG_CORE0_UM_HP_JPEG_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW_S  7
+/** TEE_REG_CORE0_UM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PPA_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_UM_HP_PPA_ALLOW_M  (TEE_REG_CORE0_UM_HP_PPA_ALLOW_V << TEE_REG_CORE0_UM_HP_PPA_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PPA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PPA_ALLOW_S  8
+/** TEE_REG_CORE0_UM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_M  (TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_V << TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_S  9
+/** TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_M  (TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_S  10
+/** TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_M  (TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_S  11
+/** TEE_REG_CORE0_UM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW    (BIT(12))
+#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW_M  (TEE_REG_CORE0_UM_HP_FLASH_ALLOW_V << TEE_REG_CORE0_UM_HP_FLASH_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW_S  12
+/** TEE_REG_CORE0_UM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW    (BIT(13))
+#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_M  (TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_V << TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_S  13
+/** TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW    (BIT(14))
+#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_M  (TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_S  14
+/** TEE_REG_CORE0_UM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW    (BIT(15))
+#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW_M  (TEE_REG_CORE0_UM_HP_GMAC_ALLOW_V << TEE_REG_CORE0_UM_HP_GMAC_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW_S  15
+/** TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW    (BIT(16))
+#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_M  (TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_S  16
+/** TEE_REG_CORE0_UM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PVT_ALLOW    (BIT(17))
+#define TEE_REG_CORE0_UM_HP_PVT_ALLOW_M  (TEE_REG_CORE0_UM_HP_PVT_ALLOW_V << TEE_REG_CORE0_UM_HP_PVT_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PVT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PVT_ALLOW_S  17
+/** TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_M  (TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_S  18
+/** TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_M  (TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_S  19
+/** TEE_REG_CORE0_UM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_ISP_ALLOW    (BIT(20))
+#define TEE_REG_CORE0_UM_HP_ISP_ALLOW_M  (TEE_REG_CORE0_UM_HP_ISP_ALLOW_V << TEE_REG_CORE0_UM_HP_ISP_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_ISP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_ISP_ALLOW_S  20
+/** TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW    (BIT(21))
+#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_M  (TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_S  21
+/** TEE_REG_CORE0_UM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_RMT_ALLOW    (BIT(22))
+#define TEE_REG_CORE0_UM_HP_RMT_ALLOW_M  (TEE_REG_CORE0_UM_HP_RMT_ALLOW_V << TEE_REG_CORE0_UM_HP_RMT_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_RMT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_RMT_ALLOW_S  22
+/** TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_M  (TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_S  23
+/** TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_M  (TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_S  24
+/** TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_S  25
+/** TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_S  26
+/** TEE_REG_CORE0_UM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW    (BIT(27))
+#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW_M  (TEE_REG_CORE0_UM_DMA_PMS_ALLOW_V << TEE_REG_CORE0_UM_DMA_PMS_ALLOW_S)
+#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW_S  27
+/** TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_M  (TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_S  28
+/** TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW    (BIT(29))
+#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_M  (TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_S)
+#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_S  29
+
+/** TEE_CORE0_UM_PMS_REG2_REG register
+ *  NA
+ */
+#define TEE_CORE0_UM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x20)
+/** TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_M  (TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_S  0
+/** TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_M  (TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_S  1
+/** TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_M  (TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_S  2
+/** TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_M  (TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_S  3
+/** TEE_REG_CORE0_UM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW_M  (TEE_REG_CORE0_UM_HP_I2C0_ALLOW_V << TEE_REG_CORE0_UM_HP_I2C0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW_S  4
+/** TEE_REG_CORE0_UM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW    (BIT(5))
+#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW_M  (TEE_REG_CORE0_UM_HP_I2C1_ALLOW_V << TEE_REG_CORE0_UM_HP_I2C1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW_S  5
+/** TEE_REG_CORE0_UM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW_M  (TEE_REG_CORE0_UM_HP_I2S0_ALLOW_V << TEE_REG_CORE0_UM_HP_I2S0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW_S  6
+/** TEE_REG_CORE0_UM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW_M  (TEE_REG_CORE0_UM_HP_I2S1_ALLOW_V << TEE_REG_CORE0_UM_HP_I2S1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW_S  7
+/** TEE_REG_CORE0_UM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW_M  (TEE_REG_CORE0_UM_HP_I2S2_ALLOW_V << TEE_REG_CORE0_UM_HP_I2S2_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW_S  8
+/** TEE_REG_CORE0_UM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW_M  (TEE_REG_CORE0_UM_HP_PCNT_ALLOW_V << TEE_REG_CORE0_UM_HP_PCNT_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW_S  9
+/** TEE_REG_CORE0_UM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UART0_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_UM_HP_UART0_ALLOW_M  (TEE_REG_CORE0_UM_HP_UART0_ALLOW_V << TEE_REG_CORE0_UM_HP_UART0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UART0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UART0_ALLOW_S  10
+/** TEE_REG_CORE0_UM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UART1_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_UM_HP_UART1_ALLOW_M  (TEE_REG_CORE0_UM_HP_UART1_ALLOW_V << TEE_REG_CORE0_UM_HP_UART1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UART1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UART1_ALLOW_S  11
+/** TEE_REG_CORE0_UM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UART2_ALLOW    (BIT(12))
+#define TEE_REG_CORE0_UM_HP_UART2_ALLOW_M  (TEE_REG_CORE0_UM_HP_UART2_ALLOW_V << TEE_REG_CORE0_UM_HP_UART2_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UART2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UART2_ALLOW_S  12
+/** TEE_REG_CORE0_UM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UART3_ALLOW    (BIT(13))
+#define TEE_REG_CORE0_UM_HP_UART3_ALLOW_M  (TEE_REG_CORE0_UM_HP_UART3_ALLOW_V << TEE_REG_CORE0_UM_HP_UART3_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UART3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UART3_ALLOW_S  13
+/** TEE_REG_CORE0_UM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UART4_ALLOW    (BIT(14))
+#define TEE_REG_CORE0_UM_HP_UART4_ALLOW_M  (TEE_REG_CORE0_UM_HP_UART4_ALLOW_V << TEE_REG_CORE0_UM_HP_UART4_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UART4_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UART4_ALLOW_S  14
+/** TEE_REG_CORE0_UM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW    (BIT(15))
+#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_M  (TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_V << TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_S  15
+/** TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW    (BIT(16))
+#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_M  (TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_S  16
+/** TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW    (BIT(17))
+#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_M  (TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_S  17
+/** TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_M  (TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_S  18
+/** TEE_REG_CORE0_UM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW    (BIT(19))
+#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW_M  (TEE_REG_CORE0_UM_HP_LEDC_ALLOW_V << TEE_REG_CORE0_UM_HP_LEDC_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW_S  19
+/** TEE_REG_CORE0_UM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_ETM_ALLOW    (BIT(21))
+#define TEE_REG_CORE0_UM_HP_ETM_ALLOW_M  (TEE_REG_CORE0_UM_HP_ETM_ALLOW_V << TEE_REG_CORE0_UM_HP_ETM_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_ETM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_ETM_ALLOW_S  21
+/** TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW    (BIT(22))
+#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_M  (TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_S  22
+/** TEE_REG_CORE0_UM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW    (BIT(23))
+#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_M  (TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_V << TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_S  23
+/** TEE_REG_CORE0_UM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW    (BIT(24))
+#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_M  (TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_V << TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_S  24
+/** TEE_REG_CORE0_UM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW    (BIT(25))
+#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_M  (TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_V << TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_S  25
+/** TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW    (BIT(26))
+#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_M  (TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_S  26
+/** TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_M  (TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_S  27
+/** TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW    (BIT(28))
+#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_M  (TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_S  28
+/** TEE_REG_CORE0_UM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_ADC_ALLOW    (BIT(30))
+#define TEE_REG_CORE0_UM_HP_ADC_ALLOW_M  (TEE_REG_CORE0_UM_HP_ADC_ALLOW_V << TEE_REG_CORE0_UM_HP_ADC_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_ADC_ALLOW_S  30
+/** TEE_REG_CORE0_UM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW    (BIT(31))
+#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW_M  (TEE_REG_CORE0_UM_HP_UHCI_ALLOW_V << TEE_REG_CORE0_UM_HP_UHCI_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW_S  31
+
+/** TEE_CORE0_UM_PMS_REG3_REG register
+ *  NA
+ */
+#define TEE_CORE0_UM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x24)
+/** TEE_REG_CORE0_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW_M  (TEE_REG_CORE0_UM_HP_GPIO_ALLOW_V << TEE_REG_CORE0_UM_HP_GPIO_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW_S  0
+/** TEE_REG_CORE0_UM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_M  (TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_V << TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_S  1
+/** TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_M  (TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_S  2
+/** TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_M  (TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_S  3
+/** TEE_REG_CORE0_UM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_M  (TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_V << TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_S  4
+
+/** TEE_CORE1_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_CORE1_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x28)
+/** TEE_REG_CORE1_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_PSRAM_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_MM_PSRAM_ALLOW_M  (TEE_REG_CORE1_MM_PSRAM_ALLOW_V << TEE_REG_CORE1_MM_PSRAM_ALLOW_S)
+#define TEE_REG_CORE1_MM_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_PSRAM_ALLOW_S  0
+/** TEE_REG_CORE1_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_FLASH_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_MM_FLASH_ALLOW_M  (TEE_REG_CORE1_MM_FLASH_ALLOW_V << TEE_REG_CORE1_MM_FLASH_ALLOW_S)
+#define TEE_REG_CORE1_MM_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_FLASH_ALLOW_S  1
+/** TEE_REG_CORE1_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_L2MEM_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_MM_L2MEM_ALLOW_M  (TEE_REG_CORE1_MM_L2MEM_ALLOW_V << TEE_REG_CORE1_MM_L2MEM_ALLOW_S)
+#define TEE_REG_CORE1_MM_L2MEM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_L2MEM_ALLOW_S  2
+/** TEE_REG_CORE1_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_L2ROM_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_MM_L2ROM_ALLOW_M  (TEE_REG_CORE1_MM_L2ROM_ALLOW_V << TEE_REG_CORE1_MM_L2ROM_ALLOW_S)
+#define TEE_REG_CORE1_MM_L2ROM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_L2ROM_ALLOW_S  3
+/** TEE_REG_CORE1_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_TRACE0_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_MM_TRACE0_ALLOW_M  (TEE_REG_CORE1_MM_TRACE0_ALLOW_V << TEE_REG_CORE1_MM_TRACE0_ALLOW_S)
+#define TEE_REG_CORE1_MM_TRACE0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_TRACE0_ALLOW_S  6
+/** TEE_REG_CORE1_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_TRACE1_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_MM_TRACE1_ALLOW_M  (TEE_REG_CORE1_MM_TRACE1_ALLOW_V << TEE_REG_CORE1_MM_TRACE1_ALLOW_S)
+#define TEE_REG_CORE1_MM_TRACE1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_TRACE1_ALLOW_S  7
+/** TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_M  (TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_S)
+#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_S  8
+/** TEE_REG_CORE1_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_M  (TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_V << TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_S)
+#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_S  9
+/** TEE_REG_CORE1_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_TCM_MON_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_MM_TCM_MON_ALLOW_M  (TEE_REG_CORE1_MM_TCM_MON_ALLOW_V << TEE_REG_CORE1_MM_TCM_MON_ALLOW_S)
+#define TEE_REG_CORE1_MM_TCM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_TCM_MON_ALLOW_S  10
+/** TEE_REG_CORE1_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_CACHE_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_MM_CACHE_ALLOW_M  (TEE_REG_CORE1_MM_CACHE_ALLOW_V << TEE_REG_CORE1_MM_CACHE_ALLOW_S)
+#define TEE_REG_CORE1_MM_CACHE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_CACHE_ALLOW_S  11
+
+/** TEE_CORE1_MM_PMS_REG1_REG register
+ *  NA
+ */
+#define TEE_CORE1_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x2c)
+/** TEE_REG_CORE1_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_M  (TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_V << TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_S  0
+/** TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_M  (TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_S  1
+/** TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_M  (TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** TEE_REG_CORE1_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW_M  (TEE_REG_CORE1_MM_HP_GDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_GDMA_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW_S  3
+/** TEE_REG_CORE1_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_M  (TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_S  4
+/** TEE_REG_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_M  (TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_V << TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_S  5
+/** TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_M  (TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_S  6
+/** TEE_REG_CORE1_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW_M  (TEE_REG_CORE1_MM_HP_JPEG_ALLOW_V << TEE_REG_CORE1_MM_HP_JPEG_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW_S  7
+/** TEE_REG_CORE1_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PPA_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_MM_HP_PPA_ALLOW_M  (TEE_REG_CORE1_MM_HP_PPA_ALLOW_V << TEE_REG_CORE1_MM_HP_PPA_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PPA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PPA_ALLOW_S  8
+/** TEE_REG_CORE1_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_M  (TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_V << TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_S  9
+/** TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_M  (TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_M  (TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_S  11
+/** TEE_REG_CORE1_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW    (BIT(12))
+#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW_M  (TEE_REG_CORE1_MM_HP_FLASH_ALLOW_V << TEE_REG_CORE1_MM_HP_FLASH_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW_S  12
+/** TEE_REG_CORE1_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_M  (TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_V << TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_S  13
+/** TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_M  (TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_S  14
+/** TEE_REG_CORE1_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW    (BIT(15))
+#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW_M  (TEE_REG_CORE1_MM_HP_GMAC_ALLOW_V << TEE_REG_CORE1_MM_HP_GMAC_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW_S  15
+/** TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_M  (TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_S  16
+/** TEE_REG_CORE1_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PVT_ALLOW    (BIT(17))
+#define TEE_REG_CORE1_MM_HP_PVT_ALLOW_M  (TEE_REG_CORE1_MM_HP_PVT_ALLOW_V << TEE_REG_CORE1_MM_HP_PVT_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PVT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PVT_ALLOW_S  17
+/** TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_M  (TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_S  18
+/** TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_M  (TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_S  19
+/** TEE_REG_CORE1_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_ISP_ALLOW    (BIT(20))
+#define TEE_REG_CORE1_MM_HP_ISP_ALLOW_M  (TEE_REG_CORE1_MM_HP_ISP_ALLOW_V << TEE_REG_CORE1_MM_HP_ISP_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_ISP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_ISP_ALLOW_S  20
+/** TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_M  (TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_S  21
+/** TEE_REG_CORE1_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_RMT_ALLOW    (BIT(22))
+#define TEE_REG_CORE1_MM_HP_RMT_ALLOW_M  (TEE_REG_CORE1_MM_HP_RMT_ALLOW_V << TEE_REG_CORE1_MM_HP_RMT_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_RMT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_RMT_ALLOW_S  22
+/** TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_M  (TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_M  (TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_S  24
+/** TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_S  25
+/** TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** TEE_REG_CORE1_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW    (BIT(27))
+#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW_M  (TEE_REG_CORE1_MM_DMA_PMS_ALLOW_V << TEE_REG_CORE1_MM_DMA_PMS_ALLOW_S)
+#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW_S  27
+/** TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_M  (TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_S  28
+/** TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW    (BIT(29))
+#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_M  (TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_S)
+#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_S  29
+
+/** TEE_CORE1_MM_PMS_REG2_REG register
+ *  NA
+ */
+#define TEE_CORE1_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x30)
+/** TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_M  (TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_S  0
+/** TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_M  (TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_S  1
+/** TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_M  (TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_M  (TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** TEE_REG_CORE1_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW_M  (TEE_REG_CORE1_MM_HP_I2C0_ALLOW_V << TEE_REG_CORE1_MM_HP_I2C0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW_S  4
+/** TEE_REG_CORE1_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW    (BIT(5))
+#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW_M  (TEE_REG_CORE1_MM_HP_I2C1_ALLOW_V << TEE_REG_CORE1_MM_HP_I2C1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW_S  5
+/** TEE_REG_CORE1_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW_M  (TEE_REG_CORE1_MM_HP_I2S0_ALLOW_V << TEE_REG_CORE1_MM_HP_I2S0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW_S  6
+/** TEE_REG_CORE1_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW_M  (TEE_REG_CORE1_MM_HP_I2S1_ALLOW_V << TEE_REG_CORE1_MM_HP_I2S1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW_S  7
+/** TEE_REG_CORE1_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW_M  (TEE_REG_CORE1_MM_HP_I2S2_ALLOW_V << TEE_REG_CORE1_MM_HP_I2S2_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW_S  8
+/** TEE_REG_CORE1_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW_M  (TEE_REG_CORE1_MM_HP_PCNT_ALLOW_V << TEE_REG_CORE1_MM_HP_PCNT_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW_S  9
+/** TEE_REG_CORE1_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UART0_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_MM_HP_UART0_ALLOW_M  (TEE_REG_CORE1_MM_HP_UART0_ALLOW_V << TEE_REG_CORE1_MM_HP_UART0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UART0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UART0_ALLOW_S  10
+/** TEE_REG_CORE1_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UART1_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_MM_HP_UART1_ALLOW_M  (TEE_REG_CORE1_MM_HP_UART1_ALLOW_V << TEE_REG_CORE1_MM_HP_UART1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UART1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UART1_ALLOW_S  11
+/** TEE_REG_CORE1_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UART2_ALLOW    (BIT(12))
+#define TEE_REG_CORE1_MM_HP_UART2_ALLOW_M  (TEE_REG_CORE1_MM_HP_UART2_ALLOW_V << TEE_REG_CORE1_MM_HP_UART2_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UART2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UART2_ALLOW_S  12
+/** TEE_REG_CORE1_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UART3_ALLOW    (BIT(13))
+#define TEE_REG_CORE1_MM_HP_UART3_ALLOW_M  (TEE_REG_CORE1_MM_HP_UART3_ALLOW_V << TEE_REG_CORE1_MM_HP_UART3_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UART3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UART3_ALLOW_S  13
+/** TEE_REG_CORE1_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UART4_ALLOW    (BIT(14))
+#define TEE_REG_CORE1_MM_HP_UART4_ALLOW_M  (TEE_REG_CORE1_MM_HP_UART4_ALLOW_V << TEE_REG_CORE1_MM_HP_UART4_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UART4_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UART4_ALLOW_S  14
+/** TEE_REG_CORE1_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_M  (TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_V << TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_S  15
+/** TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_M  (TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_S  16
+/** TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_M  (TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_S  17
+/** TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_M  (TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_S  18
+/** TEE_REG_CORE1_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW    (BIT(19))
+#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW_M  (TEE_REG_CORE1_MM_HP_LEDC_ALLOW_V << TEE_REG_CORE1_MM_HP_LEDC_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW_S  19
+/** TEE_REG_CORE1_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_ETM_ALLOW    (BIT(21))
+#define TEE_REG_CORE1_MM_HP_ETM_ALLOW_M  (TEE_REG_CORE1_MM_HP_ETM_ALLOW_V << TEE_REG_CORE1_MM_HP_ETM_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_ETM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_ETM_ALLOW_S  21
+/** TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_M  (TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_S  22
+/** TEE_REG_CORE1_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_M  (TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_V << TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_S  23
+/** TEE_REG_CORE1_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_M  (TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_V << TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_S  24
+/** TEE_REG_CORE1_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_M  (TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_V << TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_S  25
+/** TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_M  (TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_S  26
+/** TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_M  (TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_S  27
+/** TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_M  (TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_S  28
+/** TEE_REG_CORE1_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_ADC_ALLOW    (BIT(30))
+#define TEE_REG_CORE1_MM_HP_ADC_ALLOW_M  (TEE_REG_CORE1_MM_HP_ADC_ALLOW_V << TEE_REG_CORE1_MM_HP_ADC_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_ADC_ALLOW_S  30
+/** TEE_REG_CORE1_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW    (BIT(31))
+#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW_M  (TEE_REG_CORE1_MM_HP_UHCI_ALLOW_V << TEE_REG_CORE1_MM_HP_UHCI_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW_S  31
+
+/** TEE_CORE1_MM_PMS_REG3_REG register
+ *  NA
+ */
+#define TEE_CORE1_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x34)
+/** TEE_REG_CORE1_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW_M  (TEE_REG_CORE1_MM_HP_GPIO_ALLOW_V << TEE_REG_CORE1_MM_HP_GPIO_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW_S  0
+/** TEE_REG_CORE1_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_M  (TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_V << TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_S  1
+/** TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_M  (TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_S  2
+/** TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_M  (TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_S  3
+/** TEE_REG_CORE1_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_M  (TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_V << TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_S  4
+
+/** TEE_CORE1_UM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_CORE1_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x38)
+/** TEE_REG_CORE1_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_PSRAM_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_UM_PSRAM_ALLOW_M  (TEE_REG_CORE1_UM_PSRAM_ALLOW_V << TEE_REG_CORE1_UM_PSRAM_ALLOW_S)
+#define TEE_REG_CORE1_UM_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_PSRAM_ALLOW_S  0
+/** TEE_REG_CORE1_UM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_FLASH_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_UM_FLASH_ALLOW_M  (TEE_REG_CORE1_UM_FLASH_ALLOW_V << TEE_REG_CORE1_UM_FLASH_ALLOW_S)
+#define TEE_REG_CORE1_UM_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_FLASH_ALLOW_S  1
+/** TEE_REG_CORE1_UM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_L2MEM_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_UM_L2MEM_ALLOW_M  (TEE_REG_CORE1_UM_L2MEM_ALLOW_V << TEE_REG_CORE1_UM_L2MEM_ALLOW_S)
+#define TEE_REG_CORE1_UM_L2MEM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_L2MEM_ALLOW_S  2
+/** TEE_REG_CORE1_UM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_L2ROM_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_UM_L2ROM_ALLOW_M  (TEE_REG_CORE1_UM_L2ROM_ALLOW_V << TEE_REG_CORE1_UM_L2ROM_ALLOW_S)
+#define TEE_REG_CORE1_UM_L2ROM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_L2ROM_ALLOW_S  3
+/** TEE_REG_CORE1_UM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_TRACE0_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_UM_TRACE0_ALLOW_M  (TEE_REG_CORE1_UM_TRACE0_ALLOW_V << TEE_REG_CORE1_UM_TRACE0_ALLOW_S)
+#define TEE_REG_CORE1_UM_TRACE0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_TRACE0_ALLOW_S  6
+/** TEE_REG_CORE1_UM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_TRACE1_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_UM_TRACE1_ALLOW_M  (TEE_REG_CORE1_UM_TRACE1_ALLOW_V << TEE_REG_CORE1_UM_TRACE1_ALLOW_S)
+#define TEE_REG_CORE1_UM_TRACE1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_TRACE1_ALLOW_S  7
+/** TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_M  (TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_S)
+#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_S  8
+/** TEE_REG_CORE1_UM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_M  (TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_V << TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_S)
+#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_S  9
+/** TEE_REG_CORE1_UM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_TCM_MON_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_UM_TCM_MON_ALLOW_M  (TEE_REG_CORE1_UM_TCM_MON_ALLOW_V << TEE_REG_CORE1_UM_TCM_MON_ALLOW_S)
+#define TEE_REG_CORE1_UM_TCM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_TCM_MON_ALLOW_S  10
+/** TEE_REG_CORE1_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_CACHE_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_UM_CACHE_ALLOW_M  (TEE_REG_CORE1_UM_CACHE_ALLOW_V << TEE_REG_CORE1_UM_CACHE_ALLOW_S)
+#define TEE_REG_CORE1_UM_CACHE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_CACHE_ALLOW_S  11
+
+/** TEE_CORE1_UM_PMS_REG1_REG register
+ *  NA
+ */
+#define TEE_CORE1_UM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x3c)
+/** TEE_REG_CORE1_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_M  (TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_V << TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_S  0
+/** TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_M  (TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_S  1
+/** TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_M  (TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** TEE_REG_CORE1_UM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW_M  (TEE_REG_CORE1_UM_HP_GDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_GDMA_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW_S  3
+/** TEE_REG_CORE1_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_M  (TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_S  4
+/** TEE_REG_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW    (BIT(5))
+#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_M  (TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_V << TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_S  5
+/** TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_M  (TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_S  6
+/** TEE_REG_CORE1_UM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW_M  (TEE_REG_CORE1_UM_HP_JPEG_ALLOW_V << TEE_REG_CORE1_UM_HP_JPEG_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW_S  7
+/** TEE_REG_CORE1_UM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PPA_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_UM_HP_PPA_ALLOW_M  (TEE_REG_CORE1_UM_HP_PPA_ALLOW_V << TEE_REG_CORE1_UM_HP_PPA_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PPA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PPA_ALLOW_S  8
+/** TEE_REG_CORE1_UM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_M  (TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_V << TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_S  9
+/** TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_M  (TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_S  10
+/** TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_M  (TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_S  11
+/** TEE_REG_CORE1_UM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW    (BIT(12))
+#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW_M  (TEE_REG_CORE1_UM_HP_FLASH_ALLOW_V << TEE_REG_CORE1_UM_HP_FLASH_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW_S  12
+/** TEE_REG_CORE1_UM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW    (BIT(13))
+#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_M  (TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_V << TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_S  13
+/** TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW    (BIT(14))
+#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_M  (TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_S  14
+/** TEE_REG_CORE1_UM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW    (BIT(15))
+#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW_M  (TEE_REG_CORE1_UM_HP_GMAC_ALLOW_V << TEE_REG_CORE1_UM_HP_GMAC_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW_S  15
+/** TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW    (BIT(16))
+#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_M  (TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_S  16
+/** TEE_REG_CORE1_UM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PVT_ALLOW    (BIT(17))
+#define TEE_REG_CORE1_UM_HP_PVT_ALLOW_M  (TEE_REG_CORE1_UM_HP_PVT_ALLOW_V << TEE_REG_CORE1_UM_HP_PVT_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PVT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PVT_ALLOW_S  17
+/** TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_M  (TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_S  18
+/** TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_M  (TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_S  19
+/** TEE_REG_CORE1_UM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_ISP_ALLOW    (BIT(20))
+#define TEE_REG_CORE1_UM_HP_ISP_ALLOW_M  (TEE_REG_CORE1_UM_HP_ISP_ALLOW_V << TEE_REG_CORE1_UM_HP_ISP_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_ISP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_ISP_ALLOW_S  20
+/** TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW    (BIT(21))
+#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_M  (TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_S  21
+/** TEE_REG_CORE1_UM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_RMT_ALLOW    (BIT(22))
+#define TEE_REG_CORE1_UM_HP_RMT_ALLOW_M  (TEE_REG_CORE1_UM_HP_RMT_ALLOW_V << TEE_REG_CORE1_UM_HP_RMT_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_RMT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_RMT_ALLOW_S  22
+/** TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_M  (TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_S  23
+/** TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_M  (TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_S  24
+/** TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_S  25
+/** TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_S  26
+/** TEE_REG_CORE1_UM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW    (BIT(27))
+#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW_M  (TEE_REG_CORE1_UM_DMA_PMS_ALLOW_V << TEE_REG_CORE1_UM_DMA_PMS_ALLOW_S)
+#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW_S  27
+/** TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_M  (TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_S  28
+/** TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW    (BIT(29))
+#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_M  (TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_S)
+#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_S  29
+
+/** TEE_CORE1_UM_PMS_REG2_REG register
+ *  NA
+ */
+#define TEE_CORE1_UM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x40)
+/** TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_M  (TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_S  0
+/** TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_M  (TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_S  1
+/** TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_M  (TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_S  2
+/** TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_M  (TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_S  3
+/** TEE_REG_CORE1_UM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW_M  (TEE_REG_CORE1_UM_HP_I2C0_ALLOW_V << TEE_REG_CORE1_UM_HP_I2C0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW_S  4
+/** TEE_REG_CORE1_UM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW    (BIT(5))
+#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW_M  (TEE_REG_CORE1_UM_HP_I2C1_ALLOW_V << TEE_REG_CORE1_UM_HP_I2C1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW_S  5
+/** TEE_REG_CORE1_UM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW_M  (TEE_REG_CORE1_UM_HP_I2S0_ALLOW_V << TEE_REG_CORE1_UM_HP_I2S0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW_S  6
+/** TEE_REG_CORE1_UM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW_M  (TEE_REG_CORE1_UM_HP_I2S1_ALLOW_V << TEE_REG_CORE1_UM_HP_I2S1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW_S  7
+/** TEE_REG_CORE1_UM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW_M  (TEE_REG_CORE1_UM_HP_I2S2_ALLOW_V << TEE_REG_CORE1_UM_HP_I2S2_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW_S  8
+/** TEE_REG_CORE1_UM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW_M  (TEE_REG_CORE1_UM_HP_PCNT_ALLOW_V << TEE_REG_CORE1_UM_HP_PCNT_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW_S  9
+/** TEE_REG_CORE1_UM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UART0_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_UM_HP_UART0_ALLOW_M  (TEE_REG_CORE1_UM_HP_UART0_ALLOW_V << TEE_REG_CORE1_UM_HP_UART0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UART0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UART0_ALLOW_S  10
+/** TEE_REG_CORE1_UM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UART1_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_UM_HP_UART1_ALLOW_M  (TEE_REG_CORE1_UM_HP_UART1_ALLOW_V << TEE_REG_CORE1_UM_HP_UART1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UART1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UART1_ALLOW_S  11
+/** TEE_REG_CORE1_UM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UART2_ALLOW    (BIT(12))
+#define TEE_REG_CORE1_UM_HP_UART2_ALLOW_M  (TEE_REG_CORE1_UM_HP_UART2_ALLOW_V << TEE_REG_CORE1_UM_HP_UART2_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UART2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UART2_ALLOW_S  12
+/** TEE_REG_CORE1_UM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UART3_ALLOW    (BIT(13))
+#define TEE_REG_CORE1_UM_HP_UART3_ALLOW_M  (TEE_REG_CORE1_UM_HP_UART3_ALLOW_V << TEE_REG_CORE1_UM_HP_UART3_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UART3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UART3_ALLOW_S  13
+/** TEE_REG_CORE1_UM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UART4_ALLOW    (BIT(14))
+#define TEE_REG_CORE1_UM_HP_UART4_ALLOW_M  (TEE_REG_CORE1_UM_HP_UART4_ALLOW_V << TEE_REG_CORE1_UM_HP_UART4_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UART4_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UART4_ALLOW_S  14
+/** TEE_REG_CORE1_UM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW    (BIT(15))
+#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_M  (TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_V << TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_S  15
+/** TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW    (BIT(16))
+#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_M  (TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_S  16
+/** TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW    (BIT(17))
+#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_M  (TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_S  17
+/** TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_M  (TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_S  18
+/** TEE_REG_CORE1_UM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW    (BIT(19))
+#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW_M  (TEE_REG_CORE1_UM_HP_LEDC_ALLOW_V << TEE_REG_CORE1_UM_HP_LEDC_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW_S  19
+/** TEE_REG_CORE1_UM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_ETM_ALLOW    (BIT(21))
+#define TEE_REG_CORE1_UM_HP_ETM_ALLOW_M  (TEE_REG_CORE1_UM_HP_ETM_ALLOW_V << TEE_REG_CORE1_UM_HP_ETM_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_ETM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_ETM_ALLOW_S  21
+/** TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW    (BIT(22))
+#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_M  (TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_S  22
+/** TEE_REG_CORE1_UM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW    (BIT(23))
+#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_M  (TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_V << TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_S  23
+/** TEE_REG_CORE1_UM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW    (BIT(24))
+#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_M  (TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_V << TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_S  24
+/** TEE_REG_CORE1_UM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW    (BIT(25))
+#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_M  (TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_V << TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_S  25
+/** TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW    (BIT(26))
+#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_M  (TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_S  26
+/** TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_M  (TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_S  27
+/** TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW    (BIT(28))
+#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_M  (TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_S  28
+/** TEE_REG_CORE1_UM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_ADC_ALLOW    (BIT(30))
+#define TEE_REG_CORE1_UM_HP_ADC_ALLOW_M  (TEE_REG_CORE1_UM_HP_ADC_ALLOW_V << TEE_REG_CORE1_UM_HP_ADC_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_ADC_ALLOW_S  30
+/** TEE_REG_CORE1_UM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW    (BIT(31))
+#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW_M  (TEE_REG_CORE1_UM_HP_UHCI_ALLOW_V << TEE_REG_CORE1_UM_HP_UHCI_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW_S  31
+
+/** TEE_CORE1_UM_PMS_REG3_REG register
+ *  NA
+ */
+#define TEE_CORE1_UM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x44)
+/** TEE_REG_CORE1_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW_M  (TEE_REG_CORE1_UM_HP_GPIO_ALLOW_V << TEE_REG_CORE1_UM_HP_GPIO_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW_S  0
+/** TEE_REG_CORE1_UM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_M  (TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_V << TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_S  1
+/** TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_M  (TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_S  2
+/** TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_M  (TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_S  3
+/** TEE_REG_CORE1_UM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_M  (TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_V << TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_S  4
+
+/** TEE_REGDMA_PERI_PMS_REG register
+ *  NA
+ */
+#define TEE_REGDMA_PERI_PMS_REG (DR_REG_TEE_BASE + 0x48)
+/** TEE_REG_REGDMA_PERI_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_REGDMA_PERI_ALLOW    (BIT(0))
+#define TEE_REG_REGDMA_PERI_ALLOW_M  (TEE_REG_REGDMA_PERI_ALLOW_V << TEE_REG_REGDMA_PERI_ALLOW_S)
+#define TEE_REG_REGDMA_PERI_ALLOW_V  0x00000001U
+#define TEE_REG_REGDMA_PERI_ALLOW_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h
new file mode 100644
index 0000000000..96d629ea2f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h
@@ -0,0 +1,2840 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMS_HP_PERI_PMS_DATE_REG register
+ *  Version control register
+ */
+#define PMS_HP_PERI_PMS_DATE_REG (DR_REG_HP_PERI_PMS_BASE + 0x0)
+/** PMS_HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
+ *  Version control register.
+ */
+#define PMS_HP_PERI_PMS_DATE    0xFFFFFFFFU
+#define PMS_HP_PERI_PMS_DATE_M  (PMS_HP_PERI_PMS_DATE_V << PMS_HP_PERI_PMS_DATE_S)
+#define PMS_HP_PERI_PMS_DATE_V  0xFFFFFFFFU
+#define PMS_HP_PERI_PMS_DATE_S  0
+
+/** PMS_HP_PERI_PMS_CLK_EN_REG register
+ *  Clock gating register
+ */
+#define PMS_HP_PERI_PMS_CLK_EN_REG (DR_REG_HP_PERI_PMS_BASE + 0x4)
+/** PMS_HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating
+ *  1: Keep the clock always on
+ */
+#define PMS_HP_PERI_PMS_CLK_EN    (BIT(0))
+#define PMS_HP_PERI_PMS_CLK_EN_M  (PMS_HP_PERI_PMS_CLK_EN_V << PMS_HP_PERI_PMS_CLK_EN_S)
+#define PMS_HP_PERI_PMS_CLK_EN_V  0x00000001U
+#define PMS_HP_PERI_PMS_CLK_EN_S  0
+
+/** PMS_CORE0_MM_HP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU0 in machine mode
+ */
+#define PMS_CORE0_MM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x8)
+/** PMS_CORE0_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access external RAM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_PSRAM_ALLOW    (BIT(0))
+#define PMS_CORE0_MM_PSRAM_ALLOW_M  (PMS_CORE0_MM_PSRAM_ALLOW_V << PMS_CORE0_MM_PSRAM_ALLOW_S)
+#define PMS_CORE0_MM_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_PSRAM_ALLOW_S  0
+/** PMS_CORE0_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access external flash
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_FLASH_ALLOW    (BIT(1))
+#define PMS_CORE0_MM_FLASH_ALLOW_M  (PMS_CORE0_MM_FLASH_ALLOW_V << PMS_CORE0_MM_FLASH_ALLOW_S)
+#define PMS_CORE0_MM_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_FLASH_ALLOW_S  1
+/** PMS_CORE0_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP L2MEM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_L2MEM_ALLOW    (BIT(2))
+#define PMS_CORE0_MM_L2MEM_ALLOW_M  (PMS_CORE0_MM_L2MEM_ALLOW_V << PMS_CORE0_MM_L2MEM_ALLOW_S)
+#define PMS_CORE0_MM_L2MEM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_L2MEM_ALLOW_S  2
+/** PMS_CORE0_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP ROM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_L2ROM_ALLOW    (BIT(3))
+#define PMS_CORE0_MM_L2ROM_ALLOW_M  (PMS_CORE0_MM_L2ROM_ALLOW_V << PMS_CORE0_MM_L2ROM_ALLOW_S)
+#define PMS_CORE0_MM_L2ROM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_L2ROM_ALLOW_S  3
+/** PMS_CORE0_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access TRACE0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_TRACE0_ALLOW    (BIT(6))
+#define PMS_CORE0_MM_TRACE0_ALLOW_M  (PMS_CORE0_MM_TRACE0_ALLOW_V << PMS_CORE0_MM_TRACE0_ALLOW_S)
+#define PMS_CORE0_MM_TRACE0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_TRACE0_ALLOW_S  6
+/** PMS_CORE0_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access TRACE1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_TRACE1_ALLOW    (BIT(7))
+#define PMS_CORE0_MM_TRACE1_ALLOW_M  (PMS_CORE0_MM_TRACE1_ALLOW_V << PMS_CORE0_MM_TRACE1_ALLOW_S)
+#define PMS_CORE0_MM_TRACE1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_TRACE1_ALLOW_S  7
+/** PMS_CORE0_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access CPU bus
+ *  monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define PMS_CORE0_MM_CPU_BUS_MON_ALLOW_M  (PMS_CORE0_MM_CPU_BUS_MON_ALLOW_V << PMS_CORE0_MM_CPU_BUS_MON_ALLOW_S)
+#define PMS_CORE0_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_CPU_BUS_MON_ALLOW_S  8
+/** PMS_CORE0_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access L2MEM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define PMS_CORE0_MM_L2MEM_MON_ALLOW_M  (PMS_CORE0_MM_L2MEM_MON_ALLOW_V << PMS_CORE0_MM_L2MEM_MON_ALLOW_S)
+#define PMS_CORE0_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_L2MEM_MON_ALLOW_S  9
+/** PMS_CORE0_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access SPM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_SPM_MON_ALLOW    (BIT(10))
+#define PMS_CORE0_MM_SPM_MON_ALLOW_M  (PMS_CORE0_MM_SPM_MON_ALLOW_V << PMS_CORE0_MM_SPM_MON_ALLOW_S)
+#define PMS_CORE0_MM_SPM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_SPM_MON_ALLOW_S  10
+/** PMS_CORE0_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_CACHE_ALLOW    (BIT(11))
+#define PMS_CORE0_MM_CACHE_ALLOW_M  (PMS_CORE0_MM_CACHE_ALLOW_V << PMS_CORE0_MM_CACHE_ALLOW_S)
+#define PMS_CORE0_MM_CACHE_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_CACHE_ALLOW_S  11
+
+/** PMS_CORE0_MM_HP_PERI_PMS_REG1_REG register
+ *  Permission control register1 for HP CPU0 in machine mode
+ */
+#define PMS_CORE0_MM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0xc)
+/** PMS_CORE0_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP high-speed
+ *  USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define PMS_CORE0_MM_HP_USBOTG_ALLOW_M  (PMS_CORE0_MM_HP_USBOTG_ALLOW_V << PMS_CORE0_MM_HP_USBOTG_ALLOW_S)
+#define PMS_CORE0_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_USBOTG_ALLOW_S  0
+/** PMS_CORE0_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP full-speed
+ *  USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define PMS_CORE0_MM_HP_USBOTG11_ALLOW_M  (PMS_CORE0_MM_HP_USBOTG11_ALLOW_V << PMS_CORE0_MM_HP_USBOTG11_ALLOW_S)
+#define PMS_CORE0_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_USBOTG11_ALLOW_S  1
+/** PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP full-speed
+ *  USB 2.0 OTG's wrap.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_M  (PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_V << PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** PMS_CORE0_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP DW-GDMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_GDMA_ALLOW    (BIT(3))
+#define PMS_CORE0_MM_HP_GDMA_ALLOW_M  (PMS_CORE0_MM_HP_GDMA_ALLOW_V << PMS_CORE0_MM_HP_GDMA_ALLOW_S)
+#define PMS_CORE0_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_GDMA_ALLOW_S  3
+/** PMS_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP SDMMC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define PMS_CORE0_MM_HP_SDMMC_ALLOW_M  (PMS_CORE0_MM_HP_SDMMC_ALLOW_V << PMS_CORE0_MM_HP_SDMMC_ALLOW_S)
+#define PMS_CORE0_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_SDMMC_ALLOW_S  5
+/** PMS_CORE0_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access GDMA-AHB.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define PMS_CORE0_MM_HP_AHB_PDMA_ALLOW_M  (PMS_CORE0_MM_HP_AHB_PDMA_ALLOW_V << PMS_CORE0_MM_HP_AHB_PDMA_ALLOW_S)
+#define PMS_CORE0_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_AHB_PDMA_ALLOW_S  6
+/** PMS_CORE0_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP JPEG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_JPEG_ALLOW    (BIT(7))
+#define PMS_CORE0_MM_HP_JPEG_ALLOW_M  (PMS_CORE0_MM_HP_JPEG_ALLOW_V << PMS_CORE0_MM_HP_JPEG_ALLOW_S)
+#define PMS_CORE0_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_JPEG_ALLOW_S  7
+/** PMS_CORE0_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP PPA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_PPA_ALLOW    (BIT(8))
+#define PMS_CORE0_MM_HP_PPA_ALLOW_M  (PMS_CORE0_MM_HP_PPA_ALLOW_V << PMS_CORE0_MM_HP_PPA_ALLOW_S)
+#define PMS_CORE0_MM_HP_PPA_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PPA_ALLOW_S  8
+/** PMS_CORE0_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define PMS_CORE0_MM_HP_DMA2D_ALLOW_M  (PMS_CORE0_MM_HP_DMA2D_ALLOW_V << PMS_CORE0_MM_HP_DMA2D_ALLOW_S)
+#define PMS_CORE0_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_DMA2D_ALLOW_S  9
+/** PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP key manager.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW_M  (PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW_V << PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW_S)
+#define PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** PMS_CORE0_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP GDMA-AXI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define PMS_CORE0_MM_HP_AXI_PDMA_ALLOW_M  (PMS_CORE0_MM_HP_AXI_PDMA_ALLOW_V << PMS_CORE0_MM_HP_AXI_PDMA_ALLOW_S)
+#define PMS_CORE0_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_AXI_PDMA_ALLOW_S  11
+/** PMS_CORE0_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP flash MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_FLASH_ALLOW    (BIT(12))
+#define PMS_CORE0_MM_HP_FLASH_ALLOW_M  (PMS_CORE0_MM_HP_FLASH_ALLOW_V << PMS_CORE0_MM_HP_FLASH_ALLOW_S)
+#define PMS_CORE0_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_FLASH_ALLOW_S  12
+/** PMS_CORE0_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP PSRAM MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define PMS_CORE0_MM_HP_PSRAM_ALLOW_M  (PMS_CORE0_MM_HP_PSRAM_ALLOW_V << PMS_CORE0_MM_HP_PSRAM_ALLOW_S)
+#define PMS_CORE0_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PSRAM_ALLOW_S  13
+/** PMS_CORE0_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP CRYPTO
+ *  (including AES/SHA/RSA/HMAC Accelerators).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define PMS_CORE0_MM_HP_CRYPTO_ALLOW_M  (PMS_CORE0_MM_HP_CRYPTO_ALLOW_V << PMS_CORE0_MM_HP_CRYPTO_ALLOW_S)
+#define PMS_CORE0_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_CRYPTO_ALLOW_S  14
+/** PMS_CORE0_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP EMAC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_GMAC_ALLOW    (BIT(15))
+#define PMS_CORE0_MM_HP_GMAC_ALLOW_M  (PMS_CORE0_MM_HP_GMAC_ALLOW_V << PMS_CORE0_MM_HP_GMAC_ALLOW_S)
+#define PMS_CORE0_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_GMAC_ALLOW_S  15
+/** PMS_CORE0_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP high-speed
+ *  USB 2.0 OTG PHY.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define PMS_CORE0_MM_HP_USB_PHY_ALLOW_M  (PMS_CORE0_MM_HP_USB_PHY_ALLOW_V << PMS_CORE0_MM_HP_USB_PHY_ALLOW_S)
+#define PMS_CORE0_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_USB_PHY_ALLOW_S  16
+/** PMS_CORE0_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP PVT.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_CORE0_MM_HP_PVT_ALLOW    (BIT(17))
+#define PMS_CORE0_MM_HP_PVT_ALLOW_M  (PMS_CORE0_MM_HP_PVT_ALLOW_V << PMS_CORE0_MM_HP_PVT_ALLOW_S)
+#define PMS_CORE0_MM_HP_PVT_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PVT_ALLOW_S  17
+/** PMS_CORE0_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP MIPI CSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define PMS_CORE0_MM_HP_CSI_HOST_ALLOW_M  (PMS_CORE0_MM_HP_CSI_HOST_ALLOW_V << PMS_CORE0_MM_HP_CSI_HOST_ALLOW_S)
+#define PMS_CORE0_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_CSI_HOST_ALLOW_S  18
+/** PMS_CORE0_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP MIPI DSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define PMS_CORE0_MM_HP_DSI_HOST_ALLOW_M  (PMS_CORE0_MM_HP_DSI_HOST_ALLOW_V << PMS_CORE0_MM_HP_DSI_HOST_ALLOW_S)
+#define PMS_CORE0_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_DSI_HOST_ALLOW_S  19
+/** PMS_CORE0_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP ISP (Image
+ *  Signal Processor).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_ISP_ALLOW    (BIT(20))
+#define PMS_CORE0_MM_HP_ISP_ALLOW_M  (PMS_CORE0_MM_HP_ISP_ALLOW_V << PMS_CORE0_MM_HP_ISP_ALLOW_S)
+#define PMS_CORE0_MM_HP_ISP_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_ISP_ALLOW_S  20
+/** PMS_CORE0_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP H264
+ *  Encoder.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define PMS_CORE0_MM_HP_H264_CORE_ALLOW_M  (PMS_CORE0_MM_HP_H264_CORE_ALLOW_V << PMS_CORE0_MM_HP_H264_CORE_ALLOW_S)
+#define PMS_CORE0_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_H264_CORE_ALLOW_S  21
+/** PMS_CORE0_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP RMT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_RMT_ALLOW    (BIT(22))
+#define PMS_CORE0_MM_HP_RMT_ALLOW_M  (PMS_CORE0_MM_HP_RMT_ALLOW_V << PMS_CORE0_MM_HP_RMT_ALLOW_S)
+#define PMS_CORE0_MM_HP_RMT_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_RMT_ALLOW_S  22
+/** PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP bit
+ *  scrambler.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_M  (PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_S)
+#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** PMS_CORE0_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP AXI ICM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define PMS_CORE0_MM_HP_AXI_ICM_ALLOW_M  (PMS_CORE0_MM_HP_AXI_ICM_ALLOW_V << PMS_CORE0_MM_HP_AXI_ICM_ALLOW_S)
+#define PMS_CORE0_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_AXI_ICM_ALLOW_S  24
+/** PMS_CORE0_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access
+ *  HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define PMS_CORE0_MM_HP_PERI_PMS_ALLOW_M  (PMS_CORE0_MM_HP_PERI_PMS_ALLOW_V << PMS_CORE0_MM_HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE0_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PERI_PMS_ALLOW_S  25
+/** PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access
+ *  LP2HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW_M  (PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW_V << PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** PMS_CORE0_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP_DMA_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_DMA_PMS_ALLOW    (BIT(27))
+#define PMS_CORE0_MM_DMA_PMS_ALLOW_M  (PMS_CORE0_MM_DMA_PMS_ALLOW_V << PMS_CORE0_MM_DMA_PMS_ALLOW_S)
+#define PMS_CORE0_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_DMA_PMS_ALLOW_S  27
+/** PMS_CORE0_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_M  (PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_V << PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_S)
+#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_S  28
+
+/** PMS_CORE0_MM_HP_PERI_PMS_REG2_REG register
+ *  Permission control register2 for HP CPU0 in machine mode
+ */
+#define PMS_CORE0_MM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x10)
+/** PMS_CORE0_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP MCPWM0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define PMS_CORE0_MM_HP_MCPWM0_ALLOW_M  (PMS_CORE0_MM_HP_MCPWM0_ALLOW_V << PMS_CORE0_MM_HP_MCPWM0_ALLOW_S)
+#define PMS_CORE0_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_MCPWM0_ALLOW_S  0
+/** PMS_CORE0_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP MCPWM1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define PMS_CORE0_MM_HP_MCPWM1_ALLOW_M  (PMS_CORE0_MM_HP_MCPWM1_ALLOW_V << PMS_CORE0_MM_HP_MCPWM1_ALLOW_S)
+#define PMS_CORE0_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_MCPWM1_ALLOW_S  1
+/** PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP timer
+ *  group0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW_M  (PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW_V << PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP timer group1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW_M  (PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW_V << PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** PMS_CORE0_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I2C0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I2C0_ALLOW    (BIT(4))
+#define PMS_CORE0_MM_HP_I2C0_ALLOW_M  (PMS_CORE0_MM_HP_I2C0_ALLOW_V << PMS_CORE0_MM_HP_I2C0_ALLOW_S)
+#define PMS_CORE0_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I2C0_ALLOW_S  4
+/** PMS_CORE0_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I2C1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I2C1_ALLOW    (BIT(5))
+#define PMS_CORE0_MM_HP_I2C1_ALLOW_M  (PMS_CORE0_MM_HP_I2C1_ALLOW_V << PMS_CORE0_MM_HP_I2C1_ALLOW_S)
+#define PMS_CORE0_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I2C1_ALLOW_S  5
+/** PMS_CORE0_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I2S0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I2S0_ALLOW    (BIT(6))
+#define PMS_CORE0_MM_HP_I2S0_ALLOW_M  (PMS_CORE0_MM_HP_I2S0_ALLOW_V << PMS_CORE0_MM_HP_I2S0_ALLOW_S)
+#define PMS_CORE0_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I2S0_ALLOW_S  6
+/** PMS_CORE0_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I2S1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I2S1_ALLOW    (BIT(7))
+#define PMS_CORE0_MM_HP_I2S1_ALLOW_M  (PMS_CORE0_MM_HP_I2S1_ALLOW_V << PMS_CORE0_MM_HP_I2S1_ALLOW_S)
+#define PMS_CORE0_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I2S1_ALLOW_S  7
+/** PMS_CORE0_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I2S2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I2S2_ALLOW    (BIT(8))
+#define PMS_CORE0_MM_HP_I2S2_ALLOW_M  (PMS_CORE0_MM_HP_I2S2_ALLOW_V << PMS_CORE0_MM_HP_I2S2_ALLOW_S)
+#define PMS_CORE0_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I2S2_ALLOW_S  8
+/** PMS_CORE0_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP PCNT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_PCNT_ALLOW    (BIT(9))
+#define PMS_CORE0_MM_HP_PCNT_ALLOW_M  (PMS_CORE0_MM_HP_PCNT_ALLOW_V << PMS_CORE0_MM_HP_PCNT_ALLOW_S)
+#define PMS_CORE0_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PCNT_ALLOW_S  9
+/** PMS_CORE0_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UART0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UART0_ALLOW    (BIT(10))
+#define PMS_CORE0_MM_HP_UART0_ALLOW_M  (PMS_CORE0_MM_HP_UART0_ALLOW_V << PMS_CORE0_MM_HP_UART0_ALLOW_S)
+#define PMS_CORE0_MM_HP_UART0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UART0_ALLOW_S  10
+/** PMS_CORE0_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UART1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UART1_ALLOW    (BIT(11))
+#define PMS_CORE0_MM_HP_UART1_ALLOW_M  (PMS_CORE0_MM_HP_UART1_ALLOW_V << PMS_CORE0_MM_HP_UART1_ALLOW_S)
+#define PMS_CORE0_MM_HP_UART1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UART1_ALLOW_S  11
+/** PMS_CORE0_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UART2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UART2_ALLOW    (BIT(12))
+#define PMS_CORE0_MM_HP_UART2_ALLOW_M  (PMS_CORE0_MM_HP_UART2_ALLOW_V << PMS_CORE0_MM_HP_UART2_ALLOW_S)
+#define PMS_CORE0_MM_HP_UART2_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UART2_ALLOW_S  12
+/** PMS_CORE0_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UART3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UART3_ALLOW    (BIT(13))
+#define PMS_CORE0_MM_HP_UART3_ALLOW_M  (PMS_CORE0_MM_HP_UART3_ALLOW_V << PMS_CORE0_MM_HP_UART3_ALLOW_S)
+#define PMS_CORE0_MM_HP_UART3_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UART3_ALLOW_S  13
+/** PMS_CORE0_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UART4.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UART4_ALLOW    (BIT(14))
+#define PMS_CORE0_MM_HP_UART4_ALLOW_M  (PMS_CORE0_MM_HP_UART4_ALLOW_V << PMS_CORE0_MM_HP_UART4_ALLOW_S)
+#define PMS_CORE0_MM_HP_UART4_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UART4_ALLOW_S  14
+/** PMS_CORE0_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP PARLIO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define PMS_CORE0_MM_HP_PARLIO_ALLOW_M  (PMS_CORE0_MM_HP_PARLIO_ALLOW_V << PMS_CORE0_MM_HP_PARLIO_ALLOW_S)
+#define PMS_CORE0_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PARLIO_ALLOW_S  15
+/** PMS_CORE0_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP GP-SPI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define PMS_CORE0_MM_HP_GPSPI2_ALLOW_M  (PMS_CORE0_MM_HP_GPSPI2_ALLOW_V << PMS_CORE0_MM_HP_GPSPI2_ALLOW_S)
+#define PMS_CORE0_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_GPSPI2_ALLOW_S  16
+/** PMS_CORE0_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP GP-SPI3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define PMS_CORE0_MM_HP_GPSPI3_ALLOW_M  (PMS_CORE0_MM_HP_GPSPI3_ALLOW_V << PMS_CORE0_MM_HP_GPSPI3_ALLOW_S)
+#define PMS_CORE0_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_GPSPI3_ALLOW_S  17
+/** PMS_CORE0_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP USB
+ *  Serial/JTAG Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define PMS_CORE0_MM_HP_USBDEVICE_ALLOW_M  (PMS_CORE0_MM_HP_USBDEVICE_ALLOW_V << PMS_CORE0_MM_HP_USBDEVICE_ALLOW_S)
+#define PMS_CORE0_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_USBDEVICE_ALLOW_S  18
+/** PMS_CORE0_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP LEDC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_LEDC_ALLOW    (BIT(19))
+#define PMS_CORE0_MM_HP_LEDC_ALLOW_M  (PMS_CORE0_MM_HP_LEDC_ALLOW_V << PMS_CORE0_MM_HP_LEDC_ALLOW_S)
+#define PMS_CORE0_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_LEDC_ALLOW_S  19
+/** PMS_CORE0_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP ETM (Event
+ *  Task Matrix).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_ETM_ALLOW    (BIT(21))
+#define PMS_CORE0_MM_HP_ETM_ALLOW_M  (PMS_CORE0_MM_HP_ETM_ALLOW_V << PMS_CORE0_MM_HP_ETM_ALLOW_S)
+#define PMS_CORE0_MM_HP_ETM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_ETM_ALLOW_S  21
+/** PMS_CORE0_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP interrupt
+ *  matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define PMS_CORE0_MM_HP_INTRMTX_ALLOW_M  (PMS_CORE0_MM_HP_INTRMTX_ALLOW_V << PMS_CORE0_MM_HP_INTRMTX_ALLOW_S)
+#define PMS_CORE0_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_INTRMTX_ALLOW_S  22
+/** PMS_CORE0_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP TWAI0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define PMS_CORE0_MM_HP_TWAI0_ALLOW_M  (PMS_CORE0_MM_HP_TWAI0_ALLOW_V << PMS_CORE0_MM_HP_TWAI0_ALLOW_S)
+#define PMS_CORE0_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_TWAI0_ALLOW_S  23
+/** PMS_CORE0_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP TWAI1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define PMS_CORE0_MM_HP_TWAI1_ALLOW_M  (PMS_CORE0_MM_HP_TWAI1_ALLOW_V << PMS_CORE0_MM_HP_TWAI1_ALLOW_S)
+#define PMS_CORE0_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_TWAI1_ALLOW_S  24
+/** PMS_CORE0_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP TWAI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define PMS_CORE0_MM_HP_TWAI2_ALLOW_M  (PMS_CORE0_MM_HP_TWAI2_ALLOW_V << PMS_CORE0_MM_HP_TWAI2_ALLOW_S)
+#define PMS_CORE0_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_TWAI2_ALLOW_S  25
+/** PMS_CORE0_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I3C master
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define PMS_CORE0_MM_HP_I3C_MST_ALLOW_M  (PMS_CORE0_MM_HP_I3C_MST_ALLOW_V << PMS_CORE0_MM_HP_I3C_MST_ALLOW_S)
+#define PMS_CORE0_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I3C_MST_ALLOW_S  26
+/** PMS_CORE0_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I3C slave
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define PMS_CORE0_MM_HP_I3C_SLV_ALLOW_M  (PMS_CORE0_MM_HP_I3C_SLV_ALLOW_V << PMS_CORE0_MM_HP_I3C_SLV_ALLOW_S)
+#define PMS_CORE0_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I3C_SLV_ALLOW_S  27
+/** PMS_CORE0_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP LCD_CAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define PMS_CORE0_MM_HP_LCDCAM_ALLOW_M  (PMS_CORE0_MM_HP_LCDCAM_ALLOW_V << PMS_CORE0_MM_HP_LCDCAM_ALLOW_S)
+#define PMS_CORE0_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_LCDCAM_ALLOW_S  28
+/** PMS_CORE0_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_ADC_ALLOW    (BIT(30))
+#define PMS_CORE0_MM_HP_ADC_ALLOW_M  (PMS_CORE0_MM_HP_ADC_ALLOW_V << PMS_CORE0_MM_HP_ADC_ALLOW_S)
+#define PMS_CORE0_MM_HP_ADC_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_ADC_ALLOW_S  30
+/** PMS_CORE0_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UHCI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UHCI_ALLOW    (BIT(31))
+#define PMS_CORE0_MM_HP_UHCI_ALLOW_M  (PMS_CORE0_MM_HP_UHCI_ALLOW_V << PMS_CORE0_MM_HP_UHCI_ALLOW_S)
+#define PMS_CORE0_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UHCI_ALLOW_S  31
+
+/** PMS_CORE0_MM_HP_PERI_PMS_REG3_REG register
+ *  Permission control register3 for HP CPU0 in machine mode
+ */
+#define PMS_CORE0_MM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x14)
+/** PMS_CORE0_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP GPIO Matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_GPIO_ALLOW    (BIT(0))
+#define PMS_CORE0_MM_HP_GPIO_ALLOW_M  (PMS_CORE0_MM_HP_GPIO_ALLOW_V << PMS_CORE0_MM_HP_GPIO_ALLOW_S)
+#define PMS_CORE0_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_GPIO_ALLOW_S  0
+/** PMS_CORE0_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define PMS_CORE0_MM_HP_IOMUX_ALLOW_M  (PMS_CORE0_MM_HP_IOMUX_ALLOW_V << PMS_CORE0_MM_HP_IOMUX_ALLOW_S)
+#define PMS_CORE0_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_IOMUX_ALLOW_S  1
+/** PMS_CORE0_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP system
+ *  timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define PMS_CORE0_MM_HP_SYSTIMER_ALLOW_M  (PMS_CORE0_MM_HP_SYSTIMER_ALLOW_V << PMS_CORE0_MM_HP_SYSTIMER_ALLOW_S)
+#define PMS_CORE0_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_SYSTIMER_ALLOW_S  2
+/** PMS_CORE0_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP system
+ *  register.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define PMS_CORE0_MM_HP_SYS_REG_ALLOW_M  (PMS_CORE0_MM_HP_SYS_REG_ALLOW_V << PMS_CORE0_MM_HP_SYS_REG_ALLOW_S)
+#define PMS_CORE0_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_SYS_REG_ALLOW_S  3
+/** PMS_CORE0_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP_SYS_CLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define PMS_CORE0_MM_HP_CLKRST_ALLOW_M  (PMS_CORE0_MM_HP_CLKRST_ALLOW_V << PMS_CORE0_MM_HP_CLKRST_ALLOW_S)
+#define PMS_CORE0_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_CLKRST_ALLOW_S  4
+
+/** PMS_CORE0_UM_HP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU0 in user mode
+ */
+#define PMS_CORE0_UM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x18)
+/** PMS_CORE0_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access external RAM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_PSRAM_ALLOW    (BIT(0))
+#define PMS_CORE0_UM_PSRAM_ALLOW_M  (PMS_CORE0_UM_PSRAM_ALLOW_V << PMS_CORE0_UM_PSRAM_ALLOW_S)
+#define PMS_CORE0_UM_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_PSRAM_ALLOW_S  0
+/** PMS_CORE0_UM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access external flash
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_FLASH_ALLOW    (BIT(1))
+#define PMS_CORE0_UM_FLASH_ALLOW_M  (PMS_CORE0_UM_FLASH_ALLOW_V << PMS_CORE0_UM_FLASH_ALLOW_S)
+#define PMS_CORE0_UM_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_FLASH_ALLOW_S  1
+/** PMS_CORE0_UM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP L2MEM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_L2MEM_ALLOW    (BIT(2))
+#define PMS_CORE0_UM_L2MEM_ALLOW_M  (PMS_CORE0_UM_L2MEM_ALLOW_V << PMS_CORE0_UM_L2MEM_ALLOW_S)
+#define PMS_CORE0_UM_L2MEM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_L2MEM_ALLOW_S  2
+/** PMS_CORE0_UM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP ROM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_L2ROM_ALLOW    (BIT(3))
+#define PMS_CORE0_UM_L2ROM_ALLOW_M  (PMS_CORE0_UM_L2ROM_ALLOW_V << PMS_CORE0_UM_L2ROM_ALLOW_S)
+#define PMS_CORE0_UM_L2ROM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_L2ROM_ALLOW_S  3
+/** PMS_CORE0_UM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access TRACE0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_TRACE0_ALLOW    (BIT(6))
+#define PMS_CORE0_UM_TRACE0_ALLOW_M  (PMS_CORE0_UM_TRACE0_ALLOW_V << PMS_CORE0_UM_TRACE0_ALLOW_S)
+#define PMS_CORE0_UM_TRACE0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_TRACE0_ALLOW_S  6
+/** PMS_CORE0_UM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access TRACE1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_TRACE1_ALLOW    (BIT(7))
+#define PMS_CORE0_UM_TRACE1_ALLOW_M  (PMS_CORE0_UM_TRACE1_ALLOW_V << PMS_CORE0_UM_TRACE1_ALLOW_S)
+#define PMS_CORE0_UM_TRACE1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_TRACE1_ALLOW_S  7
+/** PMS_CORE0_UM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access CPU bus monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define PMS_CORE0_UM_CPU_BUS_MON_ALLOW_M  (PMS_CORE0_UM_CPU_BUS_MON_ALLOW_V << PMS_CORE0_UM_CPU_BUS_MON_ALLOW_S)
+#define PMS_CORE0_UM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_CPU_BUS_MON_ALLOW_S  8
+/** PMS_CORE0_UM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access L2MEM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_L2MEM_MON_ALLOW    (BIT(9))
+#define PMS_CORE0_UM_L2MEM_MON_ALLOW_M  (PMS_CORE0_UM_L2MEM_MON_ALLOW_V << PMS_CORE0_UM_L2MEM_MON_ALLOW_S)
+#define PMS_CORE0_UM_L2MEM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_L2MEM_MON_ALLOW_S  9
+/** PMS_CORE0_UM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access SPM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_SPM_MON_ALLOW    (BIT(10))
+#define PMS_CORE0_UM_SPM_MON_ALLOW_M  (PMS_CORE0_UM_SPM_MON_ALLOW_V << PMS_CORE0_UM_SPM_MON_ALLOW_S)
+#define PMS_CORE0_UM_SPM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_SPM_MON_ALLOW_S  10
+/** PMS_CORE0_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_CACHE_ALLOW    (BIT(11))
+#define PMS_CORE0_UM_CACHE_ALLOW_M  (PMS_CORE0_UM_CACHE_ALLOW_V << PMS_CORE0_UM_CACHE_ALLOW_S)
+#define PMS_CORE0_UM_CACHE_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_CACHE_ALLOW_S  11
+
+/** PMS_CORE0_UM_HP_PERI_PMS_REG1_REG register
+ *  Permission control register1 for HP CPU0 in user mode
+ */
+#define PMS_CORE0_UM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x1c)
+/** PMS_CORE0_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP high-speed USB
+ *  2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_USBOTG_ALLOW    (BIT(0))
+#define PMS_CORE0_UM_HP_USBOTG_ALLOW_M  (PMS_CORE0_UM_HP_USBOTG_ALLOW_V << PMS_CORE0_UM_HP_USBOTG_ALLOW_S)
+#define PMS_CORE0_UM_HP_USBOTG_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_USBOTG_ALLOW_S  0
+/** PMS_CORE0_UM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP full-speed USB
+ *  2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_USBOTG11_ALLOW    (BIT(1))
+#define PMS_CORE0_UM_HP_USBOTG11_ALLOW_M  (PMS_CORE0_UM_HP_USBOTG11_ALLOW_V << PMS_CORE0_UM_HP_USBOTG11_ALLOW_S)
+#define PMS_CORE0_UM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_USBOTG11_ALLOW_S  1
+/** PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP full-speed USB
+ *  2.0 OTG's wrap.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_M  (PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_V << PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_S)
+#define PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** PMS_CORE0_UM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP DW-GDMA.
+ *  0: Not allowed
+ *  1: Allowed
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_GDMA_ALLOW    (BIT(3))
+#define PMS_CORE0_UM_HP_GDMA_ALLOW_M  (PMS_CORE0_UM_HP_GDMA_ALLOW_V << PMS_CORE0_UM_HP_GDMA_ALLOW_S)
+#define PMS_CORE0_UM_HP_GDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_GDMA_ALLOW_S  3
+/** PMS_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP SDMMC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_SDMMC_ALLOW    (BIT(5))
+#define PMS_CORE0_UM_HP_SDMMC_ALLOW_M  (PMS_CORE0_UM_HP_SDMMC_ALLOW_V << PMS_CORE0_UM_HP_SDMMC_ALLOW_S)
+#define PMS_CORE0_UM_HP_SDMMC_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_SDMMC_ALLOW_S  5
+/** PMS_CORE0_UM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access GDMA-AHB.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define PMS_CORE0_UM_HP_AHB_PDMA_ALLOW_M  (PMS_CORE0_UM_HP_AHB_PDMA_ALLOW_V << PMS_CORE0_UM_HP_AHB_PDMA_ALLOW_S)
+#define PMS_CORE0_UM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_AHB_PDMA_ALLOW_S  6
+/** PMS_CORE0_UM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP JPEG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_JPEG_ALLOW    (BIT(7))
+#define PMS_CORE0_UM_HP_JPEG_ALLOW_M  (PMS_CORE0_UM_HP_JPEG_ALLOW_V << PMS_CORE0_UM_HP_JPEG_ALLOW_S)
+#define PMS_CORE0_UM_HP_JPEG_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_JPEG_ALLOW_S  7
+/** PMS_CORE0_UM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP PPA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_PPA_ALLOW    (BIT(8))
+#define PMS_CORE0_UM_HP_PPA_ALLOW_M  (PMS_CORE0_UM_HP_PPA_ALLOW_V << PMS_CORE0_UM_HP_PPA_ALLOW_S)
+#define PMS_CORE0_UM_HP_PPA_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PPA_ALLOW_S  8
+/** PMS_CORE0_UM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_DMA2D_ALLOW    (BIT(9))
+#define PMS_CORE0_UM_HP_DMA2D_ALLOW_M  (PMS_CORE0_UM_HP_DMA2D_ALLOW_V << PMS_CORE0_UM_HP_DMA2D_ALLOW_S)
+#define PMS_CORE0_UM_HP_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_DMA2D_ALLOW_S  9
+/** PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP key manager.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW_M  (PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW_V << PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW_S)
+#define PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW_S  10
+/** PMS_CORE0_UM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP GDMA-AXI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define PMS_CORE0_UM_HP_AXI_PDMA_ALLOW_M  (PMS_CORE0_UM_HP_AXI_PDMA_ALLOW_V << PMS_CORE0_UM_HP_AXI_PDMA_ALLOW_S)
+#define PMS_CORE0_UM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_AXI_PDMA_ALLOW_S  11
+/** PMS_CORE0_UM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP flash MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_FLASH_ALLOW    (BIT(12))
+#define PMS_CORE0_UM_HP_FLASH_ALLOW_M  (PMS_CORE0_UM_HP_FLASH_ALLOW_V << PMS_CORE0_UM_HP_FLASH_ALLOW_S)
+#define PMS_CORE0_UM_HP_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_FLASH_ALLOW_S  12
+/** PMS_CORE0_UM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP PSRAM MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_PSRAM_ALLOW    (BIT(13))
+#define PMS_CORE0_UM_HP_PSRAM_ALLOW_M  (PMS_CORE0_UM_HP_PSRAM_ALLOW_V << PMS_CORE0_UM_HP_PSRAM_ALLOW_S)
+#define PMS_CORE0_UM_HP_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PSRAM_ALLOW_S  13
+/** PMS_CORE0_UM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP CRYPTO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_CRYPTO_ALLOW    (BIT(14))
+#define PMS_CORE0_UM_HP_CRYPTO_ALLOW_M  (PMS_CORE0_UM_HP_CRYPTO_ALLOW_V << PMS_CORE0_UM_HP_CRYPTO_ALLOW_S)
+#define PMS_CORE0_UM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_CRYPTO_ALLOW_S  14
+/** PMS_CORE0_UM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP EMAC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_GMAC_ALLOW    (BIT(15))
+#define PMS_CORE0_UM_HP_GMAC_ALLOW_M  (PMS_CORE0_UM_HP_GMAC_ALLOW_V << PMS_CORE0_UM_HP_GMAC_ALLOW_S)
+#define PMS_CORE0_UM_HP_GMAC_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_GMAC_ALLOW_S  15
+/** PMS_CORE0_UM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP high-speed USB
+ *  2.0 OTG PHY.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_USB_PHY_ALLOW    (BIT(16))
+#define PMS_CORE0_UM_HP_USB_PHY_ALLOW_M  (PMS_CORE0_UM_HP_USB_PHY_ALLOW_V << PMS_CORE0_UM_HP_USB_PHY_ALLOW_S)
+#define PMS_CORE0_UM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_USB_PHY_ALLOW_S  16
+/** PMS_CORE0_UM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP PVT.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_CORE0_UM_HP_PVT_ALLOW    (BIT(17))
+#define PMS_CORE0_UM_HP_PVT_ALLOW_M  (PMS_CORE0_UM_HP_PVT_ALLOW_V << PMS_CORE0_UM_HP_PVT_ALLOW_S)
+#define PMS_CORE0_UM_HP_PVT_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PVT_ALLOW_S  17
+/** PMS_CORE0_UM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP MIPI CSI host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define PMS_CORE0_UM_HP_CSI_HOST_ALLOW_M  (PMS_CORE0_UM_HP_CSI_HOST_ALLOW_V << PMS_CORE0_UM_HP_CSI_HOST_ALLOW_S)
+#define PMS_CORE0_UM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_CSI_HOST_ALLOW_S  18
+/** PMS_CORE0_UM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP MIPI DSI host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define PMS_CORE0_UM_HP_DSI_HOST_ALLOW_M  (PMS_CORE0_UM_HP_DSI_HOST_ALLOW_V << PMS_CORE0_UM_HP_DSI_HOST_ALLOW_S)
+#define PMS_CORE0_UM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_DSI_HOST_ALLOW_S  19
+/** PMS_CORE0_UM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP ISP.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_ISP_ALLOW    (BIT(20))
+#define PMS_CORE0_UM_HP_ISP_ALLOW_M  (PMS_CORE0_UM_HP_ISP_ALLOW_V << PMS_CORE0_UM_HP_ISP_ALLOW_S)
+#define PMS_CORE0_UM_HP_ISP_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_ISP_ALLOW_S  20
+/** PMS_CORE0_UM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP H264 Encoder.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_H264_CORE_ALLOW    (BIT(21))
+#define PMS_CORE0_UM_HP_H264_CORE_ALLOW_M  (PMS_CORE0_UM_HP_H264_CORE_ALLOW_V << PMS_CORE0_UM_HP_H264_CORE_ALLOW_S)
+#define PMS_CORE0_UM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_H264_CORE_ALLOW_S  21
+/** PMS_CORE0_UM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP RMT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_RMT_ALLOW    (BIT(22))
+#define PMS_CORE0_UM_HP_RMT_ALLOW_M  (PMS_CORE0_UM_HP_RMT_ALLOW_V << PMS_CORE0_UM_HP_RMT_ALLOW_S)
+#define PMS_CORE0_UM_HP_RMT_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_RMT_ALLOW_S  22
+/** PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP bit scrambler.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_M  (PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_S)
+#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_S  23
+/** PMS_CORE0_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP AXI ICM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define PMS_CORE0_UM_HP_AXI_ICM_ALLOW_M  (PMS_CORE0_UM_HP_AXI_ICM_ALLOW_V << PMS_CORE0_UM_HP_AXI_ICM_ALLOW_S)
+#define PMS_CORE0_UM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_AXI_ICM_ALLOW_S  24
+/** PMS_CORE0_UM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define PMS_CORE0_UM_HP_PERI_PMS_ALLOW_M  (PMS_CORE0_UM_HP_PERI_PMS_ALLOW_V << PMS_CORE0_UM_HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE0_UM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PERI_PMS_ALLOW_S  25
+/** PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access
+ *  LP2HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW_M  (PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW_V << PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW_S  26
+/** PMS_CORE0_UM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP_DMA_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_DMA_PMS_ALLOW    (BIT(27))
+#define PMS_CORE0_UM_DMA_PMS_ALLOW_M  (PMS_CORE0_UM_DMA_PMS_ALLOW_V << PMS_CORE0_UM_DMA_PMS_ALLOW_S)
+#define PMS_CORE0_UM_DMA_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_DMA_PMS_ALLOW_S  27
+/** PMS_CORE0_UM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_M  (PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_V << PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_S)
+#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_S  28
+
+/** PMS_CORE0_UM_HP_PERI_PMS_REG2_REG register
+ *  Permission control register2 for HP CPU0 in user mode
+ */
+#define PMS_CORE0_UM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x20)
+/** PMS_CORE0_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP MCPWM0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_MCPWM0_ALLOW    (BIT(0))
+#define PMS_CORE0_UM_HP_MCPWM0_ALLOW_M  (PMS_CORE0_UM_HP_MCPWM0_ALLOW_V << PMS_CORE0_UM_HP_MCPWM0_ALLOW_S)
+#define PMS_CORE0_UM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_MCPWM0_ALLOW_S  0
+/** PMS_CORE0_UM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP MCPWM1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_MCPWM1_ALLOW    (BIT(1))
+#define PMS_CORE0_UM_HP_MCPWM1_ALLOW_M  (PMS_CORE0_UM_HP_MCPWM1_ALLOW_V << PMS_CORE0_UM_HP_MCPWM1_ALLOW_S)
+#define PMS_CORE0_UM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_MCPWM1_ALLOW_S  1
+/** PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP timer group0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW_M  (PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW_V << PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW_S)
+#define PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW_S  2
+/** PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP timer group1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW_M  (PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW_V << PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW_S)
+#define PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW_S  3
+/** PMS_CORE0_UM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I2C0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I2C0_ALLOW    (BIT(4))
+#define PMS_CORE0_UM_HP_I2C0_ALLOW_M  (PMS_CORE0_UM_HP_I2C0_ALLOW_V << PMS_CORE0_UM_HP_I2C0_ALLOW_S)
+#define PMS_CORE0_UM_HP_I2C0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I2C0_ALLOW_S  4
+/** PMS_CORE0_UM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I2C1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I2C1_ALLOW    (BIT(5))
+#define PMS_CORE0_UM_HP_I2C1_ALLOW_M  (PMS_CORE0_UM_HP_I2C1_ALLOW_V << PMS_CORE0_UM_HP_I2C1_ALLOW_S)
+#define PMS_CORE0_UM_HP_I2C1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I2C1_ALLOW_S  5
+/** PMS_CORE0_UM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I2S0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I2S0_ALLOW    (BIT(6))
+#define PMS_CORE0_UM_HP_I2S0_ALLOW_M  (PMS_CORE0_UM_HP_I2S0_ALLOW_V << PMS_CORE0_UM_HP_I2S0_ALLOW_S)
+#define PMS_CORE0_UM_HP_I2S0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I2S0_ALLOW_S  6
+/** PMS_CORE0_UM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I2S1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I2S1_ALLOW    (BIT(7))
+#define PMS_CORE0_UM_HP_I2S1_ALLOW_M  (PMS_CORE0_UM_HP_I2S1_ALLOW_V << PMS_CORE0_UM_HP_I2S1_ALLOW_S)
+#define PMS_CORE0_UM_HP_I2S1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I2S1_ALLOW_S  7
+/** PMS_CORE0_UM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I2S2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I2S2_ALLOW    (BIT(8))
+#define PMS_CORE0_UM_HP_I2S2_ALLOW_M  (PMS_CORE0_UM_HP_I2S2_ALLOW_V << PMS_CORE0_UM_HP_I2S2_ALLOW_S)
+#define PMS_CORE0_UM_HP_I2S2_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I2S2_ALLOW_S  8
+/** PMS_CORE0_UM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP PCNT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_PCNT_ALLOW    (BIT(9))
+#define PMS_CORE0_UM_HP_PCNT_ALLOW_M  (PMS_CORE0_UM_HP_PCNT_ALLOW_V << PMS_CORE0_UM_HP_PCNT_ALLOW_S)
+#define PMS_CORE0_UM_HP_PCNT_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PCNT_ALLOW_S  9
+/** PMS_CORE0_UM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UART0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UART0_ALLOW    (BIT(10))
+#define PMS_CORE0_UM_HP_UART0_ALLOW_M  (PMS_CORE0_UM_HP_UART0_ALLOW_V << PMS_CORE0_UM_HP_UART0_ALLOW_S)
+#define PMS_CORE0_UM_HP_UART0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UART0_ALLOW_S  10
+/** PMS_CORE0_UM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UART1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UART1_ALLOW    (BIT(11))
+#define PMS_CORE0_UM_HP_UART1_ALLOW_M  (PMS_CORE0_UM_HP_UART1_ALLOW_V << PMS_CORE0_UM_HP_UART1_ALLOW_S)
+#define PMS_CORE0_UM_HP_UART1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UART1_ALLOW_S  11
+/** PMS_CORE0_UM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UART2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UART2_ALLOW    (BIT(12))
+#define PMS_CORE0_UM_HP_UART2_ALLOW_M  (PMS_CORE0_UM_HP_UART2_ALLOW_V << PMS_CORE0_UM_HP_UART2_ALLOW_S)
+#define PMS_CORE0_UM_HP_UART2_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UART2_ALLOW_S  12
+/** PMS_CORE0_UM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UART3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UART3_ALLOW    (BIT(13))
+#define PMS_CORE0_UM_HP_UART3_ALLOW_M  (PMS_CORE0_UM_HP_UART3_ALLOW_V << PMS_CORE0_UM_HP_UART3_ALLOW_S)
+#define PMS_CORE0_UM_HP_UART3_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UART3_ALLOW_S  13
+/** PMS_CORE0_UM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UART4.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UART4_ALLOW    (BIT(14))
+#define PMS_CORE0_UM_HP_UART4_ALLOW_M  (PMS_CORE0_UM_HP_UART4_ALLOW_V << PMS_CORE0_UM_HP_UART4_ALLOW_S)
+#define PMS_CORE0_UM_HP_UART4_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UART4_ALLOW_S  14
+/** PMS_CORE0_UM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP PARLIO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_PARLIO_ALLOW    (BIT(15))
+#define PMS_CORE0_UM_HP_PARLIO_ALLOW_M  (PMS_CORE0_UM_HP_PARLIO_ALLOW_V << PMS_CORE0_UM_HP_PARLIO_ALLOW_S)
+#define PMS_CORE0_UM_HP_PARLIO_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PARLIO_ALLOW_S  15
+/** PMS_CORE0_UM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP GP-SPI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_GPSPI2_ALLOW    (BIT(16))
+#define PMS_CORE0_UM_HP_GPSPI2_ALLOW_M  (PMS_CORE0_UM_HP_GPSPI2_ALLOW_V << PMS_CORE0_UM_HP_GPSPI2_ALLOW_S)
+#define PMS_CORE0_UM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_GPSPI2_ALLOW_S  16
+/** PMS_CORE0_UM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP GP-SPI3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_GPSPI3_ALLOW    (BIT(17))
+#define PMS_CORE0_UM_HP_GPSPI3_ALLOW_M  (PMS_CORE0_UM_HP_GPSPI3_ALLOW_V << PMS_CORE0_UM_HP_GPSPI3_ALLOW_S)
+#define PMS_CORE0_UM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_GPSPI3_ALLOW_S  17
+/** PMS_CORE0_UM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP USB/Serial JTAG
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define PMS_CORE0_UM_HP_USBDEVICE_ALLOW_M  (PMS_CORE0_UM_HP_USBDEVICE_ALLOW_V << PMS_CORE0_UM_HP_USBDEVICE_ALLOW_S)
+#define PMS_CORE0_UM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_USBDEVICE_ALLOW_S  18
+/** PMS_CORE0_UM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP LEDC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_LEDC_ALLOW    (BIT(19))
+#define PMS_CORE0_UM_HP_LEDC_ALLOW_M  (PMS_CORE0_UM_HP_LEDC_ALLOW_V << PMS_CORE0_UM_HP_LEDC_ALLOW_S)
+#define PMS_CORE0_UM_HP_LEDC_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_LEDC_ALLOW_S  19
+/** PMS_CORE0_UM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP ETM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_ETM_ALLOW    (BIT(21))
+#define PMS_CORE0_UM_HP_ETM_ALLOW_M  (PMS_CORE0_UM_HP_ETM_ALLOW_V << PMS_CORE0_UM_HP_ETM_ALLOW_S)
+#define PMS_CORE0_UM_HP_ETM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_ETM_ALLOW_S  21
+/** PMS_CORE0_UM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP interrupt
+ *  matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_INTRMTX_ALLOW    (BIT(22))
+#define PMS_CORE0_UM_HP_INTRMTX_ALLOW_M  (PMS_CORE0_UM_HP_INTRMTX_ALLOW_V << PMS_CORE0_UM_HP_INTRMTX_ALLOW_S)
+#define PMS_CORE0_UM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_INTRMTX_ALLOW_S  22
+/** PMS_CORE0_UM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP TWAI0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_TWAI0_ALLOW    (BIT(23))
+#define PMS_CORE0_UM_HP_TWAI0_ALLOW_M  (PMS_CORE0_UM_HP_TWAI0_ALLOW_V << PMS_CORE0_UM_HP_TWAI0_ALLOW_S)
+#define PMS_CORE0_UM_HP_TWAI0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_TWAI0_ALLOW_S  23
+/** PMS_CORE0_UM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP TWAI1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_TWAI1_ALLOW    (BIT(24))
+#define PMS_CORE0_UM_HP_TWAI1_ALLOW_M  (PMS_CORE0_UM_HP_TWAI1_ALLOW_V << PMS_CORE0_UM_HP_TWAI1_ALLOW_S)
+#define PMS_CORE0_UM_HP_TWAI1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_TWAI1_ALLOW_S  24
+/** PMS_CORE0_UM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP TWAI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_TWAI2_ALLOW    (BIT(25))
+#define PMS_CORE0_UM_HP_TWAI2_ALLOW_M  (PMS_CORE0_UM_HP_TWAI2_ALLOW_V << PMS_CORE0_UM_HP_TWAI2_ALLOW_S)
+#define PMS_CORE0_UM_HP_TWAI2_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_TWAI2_ALLOW_S  25
+/** PMS_CORE0_UM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I3C master
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I3C_MST_ALLOW    (BIT(26))
+#define PMS_CORE0_UM_HP_I3C_MST_ALLOW_M  (PMS_CORE0_UM_HP_I3C_MST_ALLOW_V << PMS_CORE0_UM_HP_I3C_MST_ALLOW_S)
+#define PMS_CORE0_UM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I3C_MST_ALLOW_S  26
+/** PMS_CORE0_UM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I3C slave
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define PMS_CORE0_UM_HP_I3C_SLV_ALLOW_M  (PMS_CORE0_UM_HP_I3C_SLV_ALLOW_V << PMS_CORE0_UM_HP_I3C_SLV_ALLOW_S)
+#define PMS_CORE0_UM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I3C_SLV_ALLOW_S  27
+/** PMS_CORE0_UM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP LCD_CAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_LCDCAM_ALLOW    (BIT(28))
+#define PMS_CORE0_UM_HP_LCDCAM_ALLOW_M  (PMS_CORE0_UM_HP_LCDCAM_ALLOW_V << PMS_CORE0_UM_HP_LCDCAM_ALLOW_S)
+#define PMS_CORE0_UM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_LCDCAM_ALLOW_S  28
+/** PMS_CORE0_UM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_ADC_ALLOW    (BIT(30))
+#define PMS_CORE0_UM_HP_ADC_ALLOW_M  (PMS_CORE0_UM_HP_ADC_ALLOW_V << PMS_CORE0_UM_HP_ADC_ALLOW_S)
+#define PMS_CORE0_UM_HP_ADC_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_ADC_ALLOW_S  30
+/** PMS_CORE0_UM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UHCI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UHCI_ALLOW    (BIT(31))
+#define PMS_CORE0_UM_HP_UHCI_ALLOW_M  (PMS_CORE0_UM_HP_UHCI_ALLOW_V << PMS_CORE0_UM_HP_UHCI_ALLOW_S)
+#define PMS_CORE0_UM_HP_UHCI_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UHCI_ALLOW_S  31
+
+/** PMS_CORE0_UM_HP_PERI_PMS_REG3_REG register
+ *  Permission control register3 for HP CPU0 in user mode
+ */
+#define PMS_CORE0_UM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x24)
+/** PMS_CORE0_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP GPIO Matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_GPIO_ALLOW    (BIT(0))
+#define PMS_CORE0_UM_HP_GPIO_ALLOW_M  (PMS_CORE0_UM_HP_GPIO_ALLOW_V << PMS_CORE0_UM_HP_GPIO_ALLOW_S)
+#define PMS_CORE0_UM_HP_GPIO_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_GPIO_ALLOW_S  0
+/** PMS_CORE0_UM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_IOMUX_ALLOW    (BIT(1))
+#define PMS_CORE0_UM_HP_IOMUX_ALLOW_M  (PMS_CORE0_UM_HP_IOMUX_ALLOW_V << PMS_CORE0_UM_HP_IOMUX_ALLOW_S)
+#define PMS_CORE0_UM_HP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_IOMUX_ALLOW_S  1
+/** PMS_CORE0_UM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP system timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define PMS_CORE0_UM_HP_SYSTIMER_ALLOW_M  (PMS_CORE0_UM_HP_SYSTIMER_ALLOW_V << PMS_CORE0_UM_HP_SYSTIMER_ALLOW_S)
+#define PMS_CORE0_UM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_SYSTIMER_ALLOW_S  2
+/** PMS_CORE0_UM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP system
+ *  register.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_SYS_REG_ALLOW    (BIT(3))
+#define PMS_CORE0_UM_HP_SYS_REG_ALLOW_M  (PMS_CORE0_UM_HP_SYS_REG_ALLOW_V << PMS_CORE0_UM_HP_SYS_REG_ALLOW_S)
+#define PMS_CORE0_UM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_SYS_REG_ALLOW_S  3
+/** PMS_CORE0_UM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP_SYS_CLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_CLKRST_ALLOW    (BIT(4))
+#define PMS_CORE0_UM_HP_CLKRST_ALLOW_M  (PMS_CORE0_UM_HP_CLKRST_ALLOW_V << PMS_CORE0_UM_HP_CLKRST_ALLOW_S)
+#define PMS_CORE0_UM_HP_CLKRST_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_CLKRST_ALLOW_S  4
+
+/** PMS_CORE1_MM_HP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU1 in machine mode
+ */
+#define PMS_CORE1_MM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x28)
+/** PMS_CORE1_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access external RAM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_PSRAM_ALLOW    (BIT(0))
+#define PMS_CORE1_MM_PSRAM_ALLOW_M  (PMS_CORE1_MM_PSRAM_ALLOW_V << PMS_CORE1_MM_PSRAM_ALLOW_S)
+#define PMS_CORE1_MM_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_PSRAM_ALLOW_S  0
+/** PMS_CORE1_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access external flash
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_FLASH_ALLOW    (BIT(1))
+#define PMS_CORE1_MM_FLASH_ALLOW_M  (PMS_CORE1_MM_FLASH_ALLOW_V << PMS_CORE1_MM_FLASH_ALLOW_S)
+#define PMS_CORE1_MM_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_FLASH_ALLOW_S  1
+/** PMS_CORE1_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP L2MEM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_L2MEM_ALLOW    (BIT(2))
+#define PMS_CORE1_MM_L2MEM_ALLOW_M  (PMS_CORE1_MM_L2MEM_ALLOW_V << PMS_CORE1_MM_L2MEM_ALLOW_S)
+#define PMS_CORE1_MM_L2MEM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_L2MEM_ALLOW_S  2
+/** PMS_CORE1_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP ROM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_L2ROM_ALLOW    (BIT(3))
+#define PMS_CORE1_MM_L2ROM_ALLOW_M  (PMS_CORE1_MM_L2ROM_ALLOW_V << PMS_CORE1_MM_L2ROM_ALLOW_S)
+#define PMS_CORE1_MM_L2ROM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_L2ROM_ALLOW_S  3
+/** PMS_CORE1_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access TRACE0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_TRACE0_ALLOW    (BIT(6))
+#define PMS_CORE1_MM_TRACE0_ALLOW_M  (PMS_CORE1_MM_TRACE0_ALLOW_V << PMS_CORE1_MM_TRACE0_ALLOW_S)
+#define PMS_CORE1_MM_TRACE0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_TRACE0_ALLOW_S  6
+/** PMS_CORE1_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access TRACE1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_TRACE1_ALLOW    (BIT(7))
+#define PMS_CORE1_MM_TRACE1_ALLOW_M  (PMS_CORE1_MM_TRACE1_ALLOW_V << PMS_CORE1_MM_TRACE1_ALLOW_S)
+#define PMS_CORE1_MM_TRACE1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_TRACE1_ALLOW_S  7
+/** PMS_CORE1_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access CPU bus
+ *  monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define PMS_CORE1_MM_CPU_BUS_MON_ALLOW_M  (PMS_CORE1_MM_CPU_BUS_MON_ALLOW_V << PMS_CORE1_MM_CPU_BUS_MON_ALLOW_S)
+#define PMS_CORE1_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_CPU_BUS_MON_ALLOW_S  8
+/** PMS_CORE1_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access L2MEM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define PMS_CORE1_MM_L2MEM_MON_ALLOW_M  (PMS_CORE1_MM_L2MEM_MON_ALLOW_V << PMS_CORE1_MM_L2MEM_MON_ALLOW_S)
+#define PMS_CORE1_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_L2MEM_MON_ALLOW_S  9
+/** PMS_CORE1_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access SPM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_SPM_MON_ALLOW    (BIT(10))
+#define PMS_CORE1_MM_SPM_MON_ALLOW_M  (PMS_CORE1_MM_SPM_MON_ALLOW_V << PMS_CORE1_MM_SPM_MON_ALLOW_S)
+#define PMS_CORE1_MM_SPM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_SPM_MON_ALLOW_S  10
+/** PMS_CORE1_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_CACHE_ALLOW    (BIT(11))
+#define PMS_CORE1_MM_CACHE_ALLOW_M  (PMS_CORE1_MM_CACHE_ALLOW_V << PMS_CORE1_MM_CACHE_ALLOW_S)
+#define PMS_CORE1_MM_CACHE_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_CACHE_ALLOW_S  11
+
+/** PMS_CORE1_MM_HP_PERI_PMS_REG1_REG register
+ *  Permission control register1 for HP CPU1 in machine mode
+ */
+#define PMS_CORE1_MM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x2c)
+/** PMS_CORE1_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP high-speed
+ *  USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define PMS_CORE1_MM_HP_USBOTG_ALLOW_M  (PMS_CORE1_MM_HP_USBOTG_ALLOW_V << PMS_CORE1_MM_HP_USBOTG_ALLOW_S)
+#define PMS_CORE1_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_USBOTG_ALLOW_S  0
+/** PMS_CORE1_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP full-speed
+ *  USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define PMS_CORE1_MM_HP_USBOTG11_ALLOW_M  (PMS_CORE1_MM_HP_USBOTG11_ALLOW_V << PMS_CORE1_MM_HP_USBOTG11_ALLOW_S)
+#define PMS_CORE1_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_USBOTG11_ALLOW_S  1
+/** PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP full-speed
+ *  USB 2.0 OTG's wrap.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_M  (PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_V << PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** PMS_CORE1_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP DW-GDMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_GDMA_ALLOW    (BIT(3))
+#define PMS_CORE1_MM_HP_GDMA_ALLOW_M  (PMS_CORE1_MM_HP_GDMA_ALLOW_V << PMS_CORE1_MM_HP_GDMA_ALLOW_S)
+#define PMS_CORE1_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_GDMA_ALLOW_S  3
+/** PMS_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP SDMMC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define PMS_CORE1_MM_HP_SDMMC_ALLOW_M  (PMS_CORE1_MM_HP_SDMMC_ALLOW_V << PMS_CORE1_MM_HP_SDMMC_ALLOW_S)
+#define PMS_CORE1_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_SDMMC_ALLOW_S  5
+/** PMS_CORE1_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access GDMA-AHB.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define PMS_CORE1_MM_HP_AHB_PDMA_ALLOW_M  (PMS_CORE1_MM_HP_AHB_PDMA_ALLOW_V << PMS_CORE1_MM_HP_AHB_PDMA_ALLOW_S)
+#define PMS_CORE1_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_AHB_PDMA_ALLOW_S  6
+/** PMS_CORE1_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP JPEG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_JPEG_ALLOW    (BIT(7))
+#define PMS_CORE1_MM_HP_JPEG_ALLOW_M  (PMS_CORE1_MM_HP_JPEG_ALLOW_V << PMS_CORE1_MM_HP_JPEG_ALLOW_S)
+#define PMS_CORE1_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_JPEG_ALLOW_S  7
+/** PMS_CORE1_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP PPA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_PPA_ALLOW    (BIT(8))
+#define PMS_CORE1_MM_HP_PPA_ALLOW_M  (PMS_CORE1_MM_HP_PPA_ALLOW_V << PMS_CORE1_MM_HP_PPA_ALLOW_S)
+#define PMS_CORE1_MM_HP_PPA_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PPA_ALLOW_S  8
+/** PMS_CORE1_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define PMS_CORE1_MM_HP_DMA2D_ALLOW_M  (PMS_CORE1_MM_HP_DMA2D_ALLOW_V << PMS_CORE1_MM_HP_DMA2D_ALLOW_S)
+#define PMS_CORE1_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_DMA2D_ALLOW_S  9
+/** PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP key manager.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW_M  (PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW_V << PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW_S)
+#define PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** PMS_CORE1_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP GDMA-AXI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define PMS_CORE1_MM_HP_AXI_PDMA_ALLOW_M  (PMS_CORE1_MM_HP_AXI_PDMA_ALLOW_V << PMS_CORE1_MM_HP_AXI_PDMA_ALLOW_S)
+#define PMS_CORE1_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_AXI_PDMA_ALLOW_S  11
+/** PMS_CORE1_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP flash MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_FLASH_ALLOW    (BIT(12))
+#define PMS_CORE1_MM_HP_FLASH_ALLOW_M  (PMS_CORE1_MM_HP_FLASH_ALLOW_V << PMS_CORE1_MM_HP_FLASH_ALLOW_S)
+#define PMS_CORE1_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_FLASH_ALLOW_S  12
+/** PMS_CORE1_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP PSRAM MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define PMS_CORE1_MM_HP_PSRAM_ALLOW_M  (PMS_CORE1_MM_HP_PSRAM_ALLOW_V << PMS_CORE1_MM_HP_PSRAM_ALLOW_S)
+#define PMS_CORE1_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PSRAM_ALLOW_S  13
+/** PMS_CORE1_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP CRYPTO
+ *  (including AES/SHA/RSA/HMAC Accelerators).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define PMS_CORE1_MM_HP_CRYPTO_ALLOW_M  (PMS_CORE1_MM_HP_CRYPTO_ALLOW_V << PMS_CORE1_MM_HP_CRYPTO_ALLOW_S)
+#define PMS_CORE1_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_CRYPTO_ALLOW_S  14
+/** PMS_CORE1_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP EMAC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_GMAC_ALLOW    (BIT(15))
+#define PMS_CORE1_MM_HP_GMAC_ALLOW_M  (PMS_CORE1_MM_HP_GMAC_ALLOW_V << PMS_CORE1_MM_HP_GMAC_ALLOW_S)
+#define PMS_CORE1_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_GMAC_ALLOW_S  15
+/** PMS_CORE1_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP high-speed
+ *  USB 2.0 OTG PHY.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define PMS_CORE1_MM_HP_USB_PHY_ALLOW_M  (PMS_CORE1_MM_HP_USB_PHY_ALLOW_V << PMS_CORE1_MM_HP_USB_PHY_ALLOW_S)
+#define PMS_CORE1_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_USB_PHY_ALLOW_S  16
+/** PMS_CORE1_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP PVT.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_CORE1_MM_HP_PVT_ALLOW    (BIT(17))
+#define PMS_CORE1_MM_HP_PVT_ALLOW_M  (PMS_CORE1_MM_HP_PVT_ALLOW_V << PMS_CORE1_MM_HP_PVT_ALLOW_S)
+#define PMS_CORE1_MM_HP_PVT_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PVT_ALLOW_S  17
+/** PMS_CORE1_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP MIPI CSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define PMS_CORE1_MM_HP_CSI_HOST_ALLOW_M  (PMS_CORE1_MM_HP_CSI_HOST_ALLOW_V << PMS_CORE1_MM_HP_CSI_HOST_ALLOW_S)
+#define PMS_CORE1_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_CSI_HOST_ALLOW_S  18
+/** PMS_CORE1_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP MIPI DSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define PMS_CORE1_MM_HP_DSI_HOST_ALLOW_M  (PMS_CORE1_MM_HP_DSI_HOST_ALLOW_V << PMS_CORE1_MM_HP_DSI_HOST_ALLOW_S)
+#define PMS_CORE1_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_DSI_HOST_ALLOW_S  19
+/** PMS_CORE1_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP ISP (Image
+ *  Signal Processor).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_ISP_ALLOW    (BIT(20))
+#define PMS_CORE1_MM_HP_ISP_ALLOW_M  (PMS_CORE1_MM_HP_ISP_ALLOW_V << PMS_CORE1_MM_HP_ISP_ALLOW_S)
+#define PMS_CORE1_MM_HP_ISP_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_ISP_ALLOW_S  20
+/** PMS_CORE1_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP H264
+ *  Encoder.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define PMS_CORE1_MM_HP_H264_CORE_ALLOW_M  (PMS_CORE1_MM_HP_H264_CORE_ALLOW_V << PMS_CORE1_MM_HP_H264_CORE_ALLOW_S)
+#define PMS_CORE1_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_H264_CORE_ALLOW_S  21
+/** PMS_CORE1_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP RMT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_RMT_ALLOW    (BIT(22))
+#define PMS_CORE1_MM_HP_RMT_ALLOW_M  (PMS_CORE1_MM_HP_RMT_ALLOW_V << PMS_CORE1_MM_HP_RMT_ALLOW_S)
+#define PMS_CORE1_MM_HP_RMT_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_RMT_ALLOW_S  22
+/** PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP bit
+ *  scrambler.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_M  (PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_S)
+#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** PMS_CORE1_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP AXI ICM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define PMS_CORE1_MM_HP_AXI_ICM_ALLOW_M  (PMS_CORE1_MM_HP_AXI_ICM_ALLOW_V << PMS_CORE1_MM_HP_AXI_ICM_ALLOW_S)
+#define PMS_CORE1_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_AXI_ICM_ALLOW_S  24
+/** PMS_CORE1_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access
+ *  HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define PMS_CORE1_MM_HP_PERI_PMS_ALLOW_M  (PMS_CORE1_MM_HP_PERI_PMS_ALLOW_V << PMS_CORE1_MM_HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE1_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PERI_PMS_ALLOW_S  25
+/** PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access
+ *  LP2HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW_M  (PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW_V << PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** PMS_CORE1_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP_DMA_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_DMA_PMS_ALLOW    (BIT(27))
+#define PMS_CORE1_MM_DMA_PMS_ALLOW_M  (PMS_CORE1_MM_DMA_PMS_ALLOW_V << PMS_CORE1_MM_DMA_PMS_ALLOW_S)
+#define PMS_CORE1_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_DMA_PMS_ALLOW_S  27
+/** PMS_CORE1_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_M  (PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_V << PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_S)
+#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_S  28
+
+/** PMS_CORE1_MM_HP_PERI_PMS_REG2_REG register
+ *  Permission control register2 for HP CPU1 in machine mode
+ */
+#define PMS_CORE1_MM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x30)
+/** PMS_CORE1_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP MCPWM0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define PMS_CORE1_MM_HP_MCPWM0_ALLOW_M  (PMS_CORE1_MM_HP_MCPWM0_ALLOW_V << PMS_CORE1_MM_HP_MCPWM0_ALLOW_S)
+#define PMS_CORE1_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_MCPWM0_ALLOW_S  0
+/** PMS_CORE1_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP MCPWM1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define PMS_CORE1_MM_HP_MCPWM1_ALLOW_M  (PMS_CORE1_MM_HP_MCPWM1_ALLOW_V << PMS_CORE1_MM_HP_MCPWM1_ALLOW_S)
+#define PMS_CORE1_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_MCPWM1_ALLOW_S  1
+/** PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP timer
+ *  group0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW_M  (PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW_V << PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP timer group1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW_M  (PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW_V << PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** PMS_CORE1_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I2C0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I2C0_ALLOW    (BIT(4))
+#define PMS_CORE1_MM_HP_I2C0_ALLOW_M  (PMS_CORE1_MM_HP_I2C0_ALLOW_V << PMS_CORE1_MM_HP_I2C0_ALLOW_S)
+#define PMS_CORE1_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I2C0_ALLOW_S  4
+/** PMS_CORE1_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I2C1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I2C1_ALLOW    (BIT(5))
+#define PMS_CORE1_MM_HP_I2C1_ALLOW_M  (PMS_CORE1_MM_HP_I2C1_ALLOW_V << PMS_CORE1_MM_HP_I2C1_ALLOW_S)
+#define PMS_CORE1_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I2C1_ALLOW_S  5
+/** PMS_CORE1_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I2S0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I2S0_ALLOW    (BIT(6))
+#define PMS_CORE1_MM_HP_I2S0_ALLOW_M  (PMS_CORE1_MM_HP_I2S0_ALLOW_V << PMS_CORE1_MM_HP_I2S0_ALLOW_S)
+#define PMS_CORE1_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I2S0_ALLOW_S  6
+/** PMS_CORE1_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I2S1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I2S1_ALLOW    (BIT(7))
+#define PMS_CORE1_MM_HP_I2S1_ALLOW_M  (PMS_CORE1_MM_HP_I2S1_ALLOW_V << PMS_CORE1_MM_HP_I2S1_ALLOW_S)
+#define PMS_CORE1_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I2S1_ALLOW_S  7
+/** PMS_CORE1_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I2S2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I2S2_ALLOW    (BIT(8))
+#define PMS_CORE1_MM_HP_I2S2_ALLOW_M  (PMS_CORE1_MM_HP_I2S2_ALLOW_V << PMS_CORE1_MM_HP_I2S2_ALLOW_S)
+#define PMS_CORE1_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I2S2_ALLOW_S  8
+/** PMS_CORE1_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP PCNT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_PCNT_ALLOW    (BIT(9))
+#define PMS_CORE1_MM_HP_PCNT_ALLOW_M  (PMS_CORE1_MM_HP_PCNT_ALLOW_V << PMS_CORE1_MM_HP_PCNT_ALLOW_S)
+#define PMS_CORE1_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PCNT_ALLOW_S  9
+/** PMS_CORE1_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UART0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UART0_ALLOW    (BIT(10))
+#define PMS_CORE1_MM_HP_UART0_ALLOW_M  (PMS_CORE1_MM_HP_UART0_ALLOW_V << PMS_CORE1_MM_HP_UART0_ALLOW_S)
+#define PMS_CORE1_MM_HP_UART0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UART0_ALLOW_S  10
+/** PMS_CORE1_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UART1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UART1_ALLOW    (BIT(11))
+#define PMS_CORE1_MM_HP_UART1_ALLOW_M  (PMS_CORE1_MM_HP_UART1_ALLOW_V << PMS_CORE1_MM_HP_UART1_ALLOW_S)
+#define PMS_CORE1_MM_HP_UART1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UART1_ALLOW_S  11
+/** PMS_CORE1_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UART2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UART2_ALLOW    (BIT(12))
+#define PMS_CORE1_MM_HP_UART2_ALLOW_M  (PMS_CORE1_MM_HP_UART2_ALLOW_V << PMS_CORE1_MM_HP_UART2_ALLOW_S)
+#define PMS_CORE1_MM_HP_UART2_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UART2_ALLOW_S  12
+/** PMS_CORE1_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UART3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UART3_ALLOW    (BIT(13))
+#define PMS_CORE1_MM_HP_UART3_ALLOW_M  (PMS_CORE1_MM_HP_UART3_ALLOW_V << PMS_CORE1_MM_HP_UART3_ALLOW_S)
+#define PMS_CORE1_MM_HP_UART3_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UART3_ALLOW_S  13
+/** PMS_CORE1_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UART4.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UART4_ALLOW    (BIT(14))
+#define PMS_CORE1_MM_HP_UART4_ALLOW_M  (PMS_CORE1_MM_HP_UART4_ALLOW_V << PMS_CORE1_MM_HP_UART4_ALLOW_S)
+#define PMS_CORE1_MM_HP_UART4_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UART4_ALLOW_S  14
+/** PMS_CORE1_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP PARLIO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define PMS_CORE1_MM_HP_PARLIO_ALLOW_M  (PMS_CORE1_MM_HP_PARLIO_ALLOW_V << PMS_CORE1_MM_HP_PARLIO_ALLOW_S)
+#define PMS_CORE1_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PARLIO_ALLOW_S  15
+/** PMS_CORE1_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP GP-SPI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define PMS_CORE1_MM_HP_GPSPI2_ALLOW_M  (PMS_CORE1_MM_HP_GPSPI2_ALLOW_V << PMS_CORE1_MM_HP_GPSPI2_ALLOW_S)
+#define PMS_CORE1_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_GPSPI2_ALLOW_S  16
+/** PMS_CORE1_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP GP-SPI3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define PMS_CORE1_MM_HP_GPSPI3_ALLOW_M  (PMS_CORE1_MM_HP_GPSPI3_ALLOW_V << PMS_CORE1_MM_HP_GPSPI3_ALLOW_S)
+#define PMS_CORE1_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_GPSPI3_ALLOW_S  17
+/** PMS_CORE1_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP USB
+ *  Serial/JTAG Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define PMS_CORE1_MM_HP_USBDEVICE_ALLOW_M  (PMS_CORE1_MM_HP_USBDEVICE_ALLOW_V << PMS_CORE1_MM_HP_USBDEVICE_ALLOW_S)
+#define PMS_CORE1_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_USBDEVICE_ALLOW_S  18
+/** PMS_CORE1_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP LEDC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_LEDC_ALLOW    (BIT(19))
+#define PMS_CORE1_MM_HP_LEDC_ALLOW_M  (PMS_CORE1_MM_HP_LEDC_ALLOW_V << PMS_CORE1_MM_HP_LEDC_ALLOW_S)
+#define PMS_CORE1_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_LEDC_ALLOW_S  19
+/** PMS_CORE1_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP ETM (Event
+ *  Task Matrix).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_ETM_ALLOW    (BIT(21))
+#define PMS_CORE1_MM_HP_ETM_ALLOW_M  (PMS_CORE1_MM_HP_ETM_ALLOW_V << PMS_CORE1_MM_HP_ETM_ALLOW_S)
+#define PMS_CORE1_MM_HP_ETM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_ETM_ALLOW_S  21
+/** PMS_CORE1_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP interrupt
+ *  matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define PMS_CORE1_MM_HP_INTRMTX_ALLOW_M  (PMS_CORE1_MM_HP_INTRMTX_ALLOW_V << PMS_CORE1_MM_HP_INTRMTX_ALLOW_S)
+#define PMS_CORE1_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_INTRMTX_ALLOW_S  22
+/** PMS_CORE1_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP TWAI0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define PMS_CORE1_MM_HP_TWAI0_ALLOW_M  (PMS_CORE1_MM_HP_TWAI0_ALLOW_V << PMS_CORE1_MM_HP_TWAI0_ALLOW_S)
+#define PMS_CORE1_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_TWAI0_ALLOW_S  23
+/** PMS_CORE1_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP TWAI1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define PMS_CORE1_MM_HP_TWAI1_ALLOW_M  (PMS_CORE1_MM_HP_TWAI1_ALLOW_V << PMS_CORE1_MM_HP_TWAI1_ALLOW_S)
+#define PMS_CORE1_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_TWAI1_ALLOW_S  24
+/** PMS_CORE1_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP TWAI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define PMS_CORE1_MM_HP_TWAI2_ALLOW_M  (PMS_CORE1_MM_HP_TWAI2_ALLOW_V << PMS_CORE1_MM_HP_TWAI2_ALLOW_S)
+#define PMS_CORE1_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_TWAI2_ALLOW_S  25
+/** PMS_CORE1_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I3C master
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define PMS_CORE1_MM_HP_I3C_MST_ALLOW_M  (PMS_CORE1_MM_HP_I3C_MST_ALLOW_V << PMS_CORE1_MM_HP_I3C_MST_ALLOW_S)
+#define PMS_CORE1_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I3C_MST_ALLOW_S  26
+/** PMS_CORE1_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I3C slave
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define PMS_CORE1_MM_HP_I3C_SLV_ALLOW_M  (PMS_CORE1_MM_HP_I3C_SLV_ALLOW_V << PMS_CORE1_MM_HP_I3C_SLV_ALLOW_S)
+#define PMS_CORE1_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I3C_SLV_ALLOW_S  27
+/** PMS_CORE1_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP LCD_CAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define PMS_CORE1_MM_HP_LCDCAM_ALLOW_M  (PMS_CORE1_MM_HP_LCDCAM_ALLOW_V << PMS_CORE1_MM_HP_LCDCAM_ALLOW_S)
+#define PMS_CORE1_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_LCDCAM_ALLOW_S  28
+/** PMS_CORE1_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_ADC_ALLOW    (BIT(30))
+#define PMS_CORE1_MM_HP_ADC_ALLOW_M  (PMS_CORE1_MM_HP_ADC_ALLOW_V << PMS_CORE1_MM_HP_ADC_ALLOW_S)
+#define PMS_CORE1_MM_HP_ADC_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_ADC_ALLOW_S  30
+/** PMS_CORE1_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UHCI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UHCI_ALLOW    (BIT(31))
+#define PMS_CORE1_MM_HP_UHCI_ALLOW_M  (PMS_CORE1_MM_HP_UHCI_ALLOW_V << PMS_CORE1_MM_HP_UHCI_ALLOW_S)
+#define PMS_CORE1_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UHCI_ALLOW_S  31
+
+/** PMS_CORE1_MM_HP_PERI_PMS_REG3_REG register
+ *  Permission control register3 for HP CPU1 in machine mode
+ */
+#define PMS_CORE1_MM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x34)
+/** PMS_CORE1_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP GPIO Matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_GPIO_ALLOW    (BIT(0))
+#define PMS_CORE1_MM_HP_GPIO_ALLOW_M  (PMS_CORE1_MM_HP_GPIO_ALLOW_V << PMS_CORE1_MM_HP_GPIO_ALLOW_S)
+#define PMS_CORE1_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_GPIO_ALLOW_S  0
+/** PMS_CORE1_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define PMS_CORE1_MM_HP_IOMUX_ALLOW_M  (PMS_CORE1_MM_HP_IOMUX_ALLOW_V << PMS_CORE1_MM_HP_IOMUX_ALLOW_S)
+#define PMS_CORE1_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_IOMUX_ALLOW_S  1
+/** PMS_CORE1_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP system
+ *  timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define PMS_CORE1_MM_HP_SYSTIMER_ALLOW_M  (PMS_CORE1_MM_HP_SYSTIMER_ALLOW_V << PMS_CORE1_MM_HP_SYSTIMER_ALLOW_S)
+#define PMS_CORE1_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_SYSTIMER_ALLOW_S  2
+/** PMS_CORE1_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP system
+ *  register.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define PMS_CORE1_MM_HP_SYS_REG_ALLOW_M  (PMS_CORE1_MM_HP_SYS_REG_ALLOW_V << PMS_CORE1_MM_HP_SYS_REG_ALLOW_S)
+#define PMS_CORE1_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_SYS_REG_ALLOW_S  3
+/** PMS_CORE1_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP_SYS_CLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define PMS_CORE1_MM_HP_CLKRST_ALLOW_M  (PMS_CORE1_MM_HP_CLKRST_ALLOW_V << PMS_CORE1_MM_HP_CLKRST_ALLOW_S)
+#define PMS_CORE1_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_CLKRST_ALLOW_S  4
+
+/** PMS_CORE1_UM_HP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU1 in user mode
+ */
+#define PMS_CORE1_UM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x38)
+/** PMS_CORE1_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access external RAM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_PSRAM_ALLOW    (BIT(0))
+#define PMS_CORE1_UM_PSRAM_ALLOW_M  (PMS_CORE1_UM_PSRAM_ALLOW_V << PMS_CORE1_UM_PSRAM_ALLOW_S)
+#define PMS_CORE1_UM_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_PSRAM_ALLOW_S  0
+/** PMS_CORE1_UM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access external flash
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_FLASH_ALLOW    (BIT(1))
+#define PMS_CORE1_UM_FLASH_ALLOW_M  (PMS_CORE1_UM_FLASH_ALLOW_V << PMS_CORE1_UM_FLASH_ALLOW_S)
+#define PMS_CORE1_UM_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_FLASH_ALLOW_S  1
+/** PMS_CORE1_UM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP L2MEM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_L2MEM_ALLOW    (BIT(2))
+#define PMS_CORE1_UM_L2MEM_ALLOW_M  (PMS_CORE1_UM_L2MEM_ALLOW_V << PMS_CORE1_UM_L2MEM_ALLOW_S)
+#define PMS_CORE1_UM_L2MEM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_L2MEM_ALLOW_S  2
+/** PMS_CORE1_UM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP ROM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_L2ROM_ALLOW    (BIT(3))
+#define PMS_CORE1_UM_L2ROM_ALLOW_M  (PMS_CORE1_UM_L2ROM_ALLOW_V << PMS_CORE1_UM_L2ROM_ALLOW_S)
+#define PMS_CORE1_UM_L2ROM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_L2ROM_ALLOW_S  3
+/** PMS_CORE1_UM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access TRACE0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_TRACE0_ALLOW    (BIT(6))
+#define PMS_CORE1_UM_TRACE0_ALLOW_M  (PMS_CORE1_UM_TRACE0_ALLOW_V << PMS_CORE1_UM_TRACE0_ALLOW_S)
+#define PMS_CORE1_UM_TRACE0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_TRACE0_ALLOW_S  6
+/** PMS_CORE1_UM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access TRACE1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_TRACE1_ALLOW    (BIT(7))
+#define PMS_CORE1_UM_TRACE1_ALLOW_M  (PMS_CORE1_UM_TRACE1_ALLOW_V << PMS_CORE1_UM_TRACE1_ALLOW_S)
+#define PMS_CORE1_UM_TRACE1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_TRACE1_ALLOW_S  7
+/** PMS_CORE1_UM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access CPU bus monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define PMS_CORE1_UM_CPU_BUS_MON_ALLOW_M  (PMS_CORE1_UM_CPU_BUS_MON_ALLOW_V << PMS_CORE1_UM_CPU_BUS_MON_ALLOW_S)
+#define PMS_CORE1_UM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_CPU_BUS_MON_ALLOW_S  8
+/** PMS_CORE1_UM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access L2MEM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_L2MEM_MON_ALLOW    (BIT(9))
+#define PMS_CORE1_UM_L2MEM_MON_ALLOW_M  (PMS_CORE1_UM_L2MEM_MON_ALLOW_V << PMS_CORE1_UM_L2MEM_MON_ALLOW_S)
+#define PMS_CORE1_UM_L2MEM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_L2MEM_MON_ALLOW_S  9
+/** PMS_CORE1_UM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access SPM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_SPM_MON_ALLOW    (BIT(10))
+#define PMS_CORE1_UM_SPM_MON_ALLOW_M  (PMS_CORE1_UM_SPM_MON_ALLOW_V << PMS_CORE1_UM_SPM_MON_ALLOW_S)
+#define PMS_CORE1_UM_SPM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_SPM_MON_ALLOW_S  10
+/** PMS_CORE1_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_CACHE_ALLOW    (BIT(11))
+#define PMS_CORE1_UM_CACHE_ALLOW_M  (PMS_CORE1_UM_CACHE_ALLOW_V << PMS_CORE1_UM_CACHE_ALLOW_S)
+#define PMS_CORE1_UM_CACHE_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_CACHE_ALLOW_S  11
+
+/** PMS_CORE1_UM_HP_PERI_PMS_REG1_REG register
+ *  Permission control register1 for HP CPU1 in user mode
+ */
+#define PMS_CORE1_UM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x3c)
+/** PMS_CORE1_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP high-speed USB
+ *  2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_USBOTG_ALLOW    (BIT(0))
+#define PMS_CORE1_UM_HP_USBOTG_ALLOW_M  (PMS_CORE1_UM_HP_USBOTG_ALLOW_V << PMS_CORE1_UM_HP_USBOTG_ALLOW_S)
+#define PMS_CORE1_UM_HP_USBOTG_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_USBOTG_ALLOW_S  0
+/** PMS_CORE1_UM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP full-speed USB
+ *  2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_USBOTG11_ALLOW    (BIT(1))
+#define PMS_CORE1_UM_HP_USBOTG11_ALLOW_M  (PMS_CORE1_UM_HP_USBOTG11_ALLOW_V << PMS_CORE1_UM_HP_USBOTG11_ALLOW_S)
+#define PMS_CORE1_UM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_USBOTG11_ALLOW_S  1
+/** PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP full-speed USB
+ *  2.0 OTG's wrap.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_M  (PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_V << PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_S)
+#define PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** PMS_CORE1_UM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP DW-GDMA.
+ *  0: Not allowed
+ *  1: Allowed
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_GDMA_ALLOW    (BIT(3))
+#define PMS_CORE1_UM_HP_GDMA_ALLOW_M  (PMS_CORE1_UM_HP_GDMA_ALLOW_V << PMS_CORE1_UM_HP_GDMA_ALLOW_S)
+#define PMS_CORE1_UM_HP_GDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_GDMA_ALLOW_S  3
+/** PMS_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP SDMMC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_SDMMC_ALLOW    (BIT(5))
+#define PMS_CORE1_UM_HP_SDMMC_ALLOW_M  (PMS_CORE1_UM_HP_SDMMC_ALLOW_V << PMS_CORE1_UM_HP_SDMMC_ALLOW_S)
+#define PMS_CORE1_UM_HP_SDMMC_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_SDMMC_ALLOW_S  5
+/** PMS_CORE1_UM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access GDMA-AHB.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define PMS_CORE1_UM_HP_AHB_PDMA_ALLOW_M  (PMS_CORE1_UM_HP_AHB_PDMA_ALLOW_V << PMS_CORE1_UM_HP_AHB_PDMA_ALLOW_S)
+#define PMS_CORE1_UM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_AHB_PDMA_ALLOW_S  6
+/** PMS_CORE1_UM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP JPEG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_JPEG_ALLOW    (BIT(7))
+#define PMS_CORE1_UM_HP_JPEG_ALLOW_M  (PMS_CORE1_UM_HP_JPEG_ALLOW_V << PMS_CORE1_UM_HP_JPEG_ALLOW_S)
+#define PMS_CORE1_UM_HP_JPEG_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_JPEG_ALLOW_S  7
+/** PMS_CORE1_UM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP PPA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_PPA_ALLOW    (BIT(8))
+#define PMS_CORE1_UM_HP_PPA_ALLOW_M  (PMS_CORE1_UM_HP_PPA_ALLOW_V << PMS_CORE1_UM_HP_PPA_ALLOW_S)
+#define PMS_CORE1_UM_HP_PPA_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PPA_ALLOW_S  8
+/** PMS_CORE1_UM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_DMA2D_ALLOW    (BIT(9))
+#define PMS_CORE1_UM_HP_DMA2D_ALLOW_M  (PMS_CORE1_UM_HP_DMA2D_ALLOW_V << PMS_CORE1_UM_HP_DMA2D_ALLOW_S)
+#define PMS_CORE1_UM_HP_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_DMA2D_ALLOW_S  9
+/** PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP key manager.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW_M  (PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW_V << PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW_S)
+#define PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW_S  10
+/** PMS_CORE1_UM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP GDMA-AXI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define PMS_CORE1_UM_HP_AXI_PDMA_ALLOW_M  (PMS_CORE1_UM_HP_AXI_PDMA_ALLOW_V << PMS_CORE1_UM_HP_AXI_PDMA_ALLOW_S)
+#define PMS_CORE1_UM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_AXI_PDMA_ALLOW_S  11
+/** PMS_CORE1_UM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP flash MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_FLASH_ALLOW    (BIT(12))
+#define PMS_CORE1_UM_HP_FLASH_ALLOW_M  (PMS_CORE1_UM_HP_FLASH_ALLOW_V << PMS_CORE1_UM_HP_FLASH_ALLOW_S)
+#define PMS_CORE1_UM_HP_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_FLASH_ALLOW_S  12
+/** PMS_CORE1_UM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP PSRAM MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_PSRAM_ALLOW    (BIT(13))
+#define PMS_CORE1_UM_HP_PSRAM_ALLOW_M  (PMS_CORE1_UM_HP_PSRAM_ALLOW_V << PMS_CORE1_UM_HP_PSRAM_ALLOW_S)
+#define PMS_CORE1_UM_HP_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PSRAM_ALLOW_S  13
+/** PMS_CORE1_UM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP CRYPTO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_CRYPTO_ALLOW    (BIT(14))
+#define PMS_CORE1_UM_HP_CRYPTO_ALLOW_M  (PMS_CORE1_UM_HP_CRYPTO_ALLOW_V << PMS_CORE1_UM_HP_CRYPTO_ALLOW_S)
+#define PMS_CORE1_UM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_CRYPTO_ALLOW_S  14
+/** PMS_CORE1_UM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP EMAC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_GMAC_ALLOW    (BIT(15))
+#define PMS_CORE1_UM_HP_GMAC_ALLOW_M  (PMS_CORE1_UM_HP_GMAC_ALLOW_V << PMS_CORE1_UM_HP_GMAC_ALLOW_S)
+#define PMS_CORE1_UM_HP_GMAC_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_GMAC_ALLOW_S  15
+/** PMS_CORE1_UM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP high-speed USB
+ *  2.0 OTG PHY.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_USB_PHY_ALLOW    (BIT(16))
+#define PMS_CORE1_UM_HP_USB_PHY_ALLOW_M  (PMS_CORE1_UM_HP_USB_PHY_ALLOW_V << PMS_CORE1_UM_HP_USB_PHY_ALLOW_S)
+#define PMS_CORE1_UM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_USB_PHY_ALLOW_S  16
+/** PMS_CORE1_UM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP PVT.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_CORE1_UM_HP_PVT_ALLOW    (BIT(17))
+#define PMS_CORE1_UM_HP_PVT_ALLOW_M  (PMS_CORE1_UM_HP_PVT_ALLOW_V << PMS_CORE1_UM_HP_PVT_ALLOW_S)
+#define PMS_CORE1_UM_HP_PVT_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PVT_ALLOW_S  17
+/** PMS_CORE1_UM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP MIPI CSI host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define PMS_CORE1_UM_HP_CSI_HOST_ALLOW_M  (PMS_CORE1_UM_HP_CSI_HOST_ALLOW_V << PMS_CORE1_UM_HP_CSI_HOST_ALLOW_S)
+#define PMS_CORE1_UM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_CSI_HOST_ALLOW_S  18
+/** PMS_CORE1_UM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP MIPI DSI host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define PMS_CORE1_UM_HP_DSI_HOST_ALLOW_M  (PMS_CORE1_UM_HP_DSI_HOST_ALLOW_V << PMS_CORE1_UM_HP_DSI_HOST_ALLOW_S)
+#define PMS_CORE1_UM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_DSI_HOST_ALLOW_S  19
+/** PMS_CORE1_UM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP ISP.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_ISP_ALLOW    (BIT(20))
+#define PMS_CORE1_UM_HP_ISP_ALLOW_M  (PMS_CORE1_UM_HP_ISP_ALLOW_V << PMS_CORE1_UM_HP_ISP_ALLOW_S)
+#define PMS_CORE1_UM_HP_ISP_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_ISP_ALLOW_S  20
+/** PMS_CORE1_UM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP H264 Encoder.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_H264_CORE_ALLOW    (BIT(21))
+#define PMS_CORE1_UM_HP_H264_CORE_ALLOW_M  (PMS_CORE1_UM_HP_H264_CORE_ALLOW_V << PMS_CORE1_UM_HP_H264_CORE_ALLOW_S)
+#define PMS_CORE1_UM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_H264_CORE_ALLOW_S  21
+/** PMS_CORE1_UM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP RMT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_RMT_ALLOW    (BIT(22))
+#define PMS_CORE1_UM_HP_RMT_ALLOW_M  (PMS_CORE1_UM_HP_RMT_ALLOW_V << PMS_CORE1_UM_HP_RMT_ALLOW_S)
+#define PMS_CORE1_UM_HP_RMT_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_RMT_ALLOW_S  22
+/** PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP bit scrambler.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_M  (PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_S)
+#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_S  23
+/** PMS_CORE1_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP AXI ICM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define PMS_CORE1_UM_HP_AXI_ICM_ALLOW_M  (PMS_CORE1_UM_HP_AXI_ICM_ALLOW_V << PMS_CORE1_UM_HP_AXI_ICM_ALLOW_S)
+#define PMS_CORE1_UM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_AXI_ICM_ALLOW_S  24
+/** PMS_CORE1_UM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define PMS_CORE1_UM_HP_PERI_PMS_ALLOW_M  (PMS_CORE1_UM_HP_PERI_PMS_ALLOW_V << PMS_CORE1_UM_HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE1_UM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PERI_PMS_ALLOW_S  25
+/** PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access
+ *  LP2HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW_M  (PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW_V << PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW_S  26
+/** PMS_CORE1_UM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP_DMA_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_DMA_PMS_ALLOW    (BIT(27))
+#define PMS_CORE1_UM_DMA_PMS_ALLOW_M  (PMS_CORE1_UM_DMA_PMS_ALLOW_V << PMS_CORE1_UM_DMA_PMS_ALLOW_S)
+#define PMS_CORE1_UM_DMA_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_DMA_PMS_ALLOW_S  27
+/** PMS_CORE1_UM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_M  (PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_V << PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_S)
+#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_S  28
+
+/** PMS_CORE1_UM_HP_PERI_PMS_REG2_REG register
+ *  Permission control register2 for HP CPU1 in user mode
+ */
+#define PMS_CORE1_UM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x40)
+/** PMS_CORE1_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP MCPWM0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_MCPWM0_ALLOW    (BIT(0))
+#define PMS_CORE1_UM_HP_MCPWM0_ALLOW_M  (PMS_CORE1_UM_HP_MCPWM0_ALLOW_V << PMS_CORE1_UM_HP_MCPWM0_ALLOW_S)
+#define PMS_CORE1_UM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_MCPWM0_ALLOW_S  0
+/** PMS_CORE1_UM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP MCPWM1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_MCPWM1_ALLOW    (BIT(1))
+#define PMS_CORE1_UM_HP_MCPWM1_ALLOW_M  (PMS_CORE1_UM_HP_MCPWM1_ALLOW_V << PMS_CORE1_UM_HP_MCPWM1_ALLOW_S)
+#define PMS_CORE1_UM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_MCPWM1_ALLOW_S  1
+/** PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP timer group0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW_M  (PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW_V << PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW_S)
+#define PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW_S  2
+/** PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP timer group1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW_M  (PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW_V << PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW_S)
+#define PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW_S  3
+/** PMS_CORE1_UM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I2C0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I2C0_ALLOW    (BIT(4))
+#define PMS_CORE1_UM_HP_I2C0_ALLOW_M  (PMS_CORE1_UM_HP_I2C0_ALLOW_V << PMS_CORE1_UM_HP_I2C0_ALLOW_S)
+#define PMS_CORE1_UM_HP_I2C0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I2C0_ALLOW_S  4
+/** PMS_CORE1_UM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I2C1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I2C1_ALLOW    (BIT(5))
+#define PMS_CORE1_UM_HP_I2C1_ALLOW_M  (PMS_CORE1_UM_HP_I2C1_ALLOW_V << PMS_CORE1_UM_HP_I2C1_ALLOW_S)
+#define PMS_CORE1_UM_HP_I2C1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I2C1_ALLOW_S  5
+/** PMS_CORE1_UM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I2S0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I2S0_ALLOW    (BIT(6))
+#define PMS_CORE1_UM_HP_I2S0_ALLOW_M  (PMS_CORE1_UM_HP_I2S0_ALLOW_V << PMS_CORE1_UM_HP_I2S0_ALLOW_S)
+#define PMS_CORE1_UM_HP_I2S0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I2S0_ALLOW_S  6
+/** PMS_CORE1_UM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I2S1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I2S1_ALLOW    (BIT(7))
+#define PMS_CORE1_UM_HP_I2S1_ALLOW_M  (PMS_CORE1_UM_HP_I2S1_ALLOW_V << PMS_CORE1_UM_HP_I2S1_ALLOW_S)
+#define PMS_CORE1_UM_HP_I2S1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I2S1_ALLOW_S  7
+/** PMS_CORE1_UM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I2S2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I2S2_ALLOW    (BIT(8))
+#define PMS_CORE1_UM_HP_I2S2_ALLOW_M  (PMS_CORE1_UM_HP_I2S2_ALLOW_V << PMS_CORE1_UM_HP_I2S2_ALLOW_S)
+#define PMS_CORE1_UM_HP_I2S2_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I2S2_ALLOW_S  8
+/** PMS_CORE1_UM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP PCNT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_PCNT_ALLOW    (BIT(9))
+#define PMS_CORE1_UM_HP_PCNT_ALLOW_M  (PMS_CORE1_UM_HP_PCNT_ALLOW_V << PMS_CORE1_UM_HP_PCNT_ALLOW_S)
+#define PMS_CORE1_UM_HP_PCNT_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PCNT_ALLOW_S  9
+/** PMS_CORE1_UM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UART0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UART0_ALLOW    (BIT(10))
+#define PMS_CORE1_UM_HP_UART0_ALLOW_M  (PMS_CORE1_UM_HP_UART0_ALLOW_V << PMS_CORE1_UM_HP_UART0_ALLOW_S)
+#define PMS_CORE1_UM_HP_UART0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UART0_ALLOW_S  10
+/** PMS_CORE1_UM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UART1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UART1_ALLOW    (BIT(11))
+#define PMS_CORE1_UM_HP_UART1_ALLOW_M  (PMS_CORE1_UM_HP_UART1_ALLOW_V << PMS_CORE1_UM_HP_UART1_ALLOW_S)
+#define PMS_CORE1_UM_HP_UART1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UART1_ALLOW_S  11
+/** PMS_CORE1_UM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UART2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UART2_ALLOW    (BIT(12))
+#define PMS_CORE1_UM_HP_UART2_ALLOW_M  (PMS_CORE1_UM_HP_UART2_ALLOW_V << PMS_CORE1_UM_HP_UART2_ALLOW_S)
+#define PMS_CORE1_UM_HP_UART2_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UART2_ALLOW_S  12
+/** PMS_CORE1_UM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UART3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UART3_ALLOW    (BIT(13))
+#define PMS_CORE1_UM_HP_UART3_ALLOW_M  (PMS_CORE1_UM_HP_UART3_ALLOW_V << PMS_CORE1_UM_HP_UART3_ALLOW_S)
+#define PMS_CORE1_UM_HP_UART3_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UART3_ALLOW_S  13
+/** PMS_CORE1_UM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UART4.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UART4_ALLOW    (BIT(14))
+#define PMS_CORE1_UM_HP_UART4_ALLOW_M  (PMS_CORE1_UM_HP_UART4_ALLOW_V << PMS_CORE1_UM_HP_UART4_ALLOW_S)
+#define PMS_CORE1_UM_HP_UART4_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UART4_ALLOW_S  14
+/** PMS_CORE1_UM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP PARLIO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_PARLIO_ALLOW    (BIT(15))
+#define PMS_CORE1_UM_HP_PARLIO_ALLOW_M  (PMS_CORE1_UM_HP_PARLIO_ALLOW_V << PMS_CORE1_UM_HP_PARLIO_ALLOW_S)
+#define PMS_CORE1_UM_HP_PARLIO_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PARLIO_ALLOW_S  15
+/** PMS_CORE1_UM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP GP-SPI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_GPSPI2_ALLOW    (BIT(16))
+#define PMS_CORE1_UM_HP_GPSPI2_ALLOW_M  (PMS_CORE1_UM_HP_GPSPI2_ALLOW_V << PMS_CORE1_UM_HP_GPSPI2_ALLOW_S)
+#define PMS_CORE1_UM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_GPSPI2_ALLOW_S  16
+/** PMS_CORE1_UM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP GP-SPI3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_GPSPI3_ALLOW    (BIT(17))
+#define PMS_CORE1_UM_HP_GPSPI3_ALLOW_M  (PMS_CORE1_UM_HP_GPSPI3_ALLOW_V << PMS_CORE1_UM_HP_GPSPI3_ALLOW_S)
+#define PMS_CORE1_UM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_GPSPI3_ALLOW_S  17
+/** PMS_CORE1_UM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP USB/Serial JTAG
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define PMS_CORE1_UM_HP_USBDEVICE_ALLOW_M  (PMS_CORE1_UM_HP_USBDEVICE_ALLOW_V << PMS_CORE1_UM_HP_USBDEVICE_ALLOW_S)
+#define PMS_CORE1_UM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_USBDEVICE_ALLOW_S  18
+/** PMS_CORE1_UM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP LEDC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_LEDC_ALLOW    (BIT(19))
+#define PMS_CORE1_UM_HP_LEDC_ALLOW_M  (PMS_CORE1_UM_HP_LEDC_ALLOW_V << PMS_CORE1_UM_HP_LEDC_ALLOW_S)
+#define PMS_CORE1_UM_HP_LEDC_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_LEDC_ALLOW_S  19
+/** PMS_CORE1_UM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP ETM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_ETM_ALLOW    (BIT(21))
+#define PMS_CORE1_UM_HP_ETM_ALLOW_M  (PMS_CORE1_UM_HP_ETM_ALLOW_V << PMS_CORE1_UM_HP_ETM_ALLOW_S)
+#define PMS_CORE1_UM_HP_ETM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_ETM_ALLOW_S  21
+/** PMS_CORE1_UM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP interrupt
+ *  matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_INTRMTX_ALLOW    (BIT(22))
+#define PMS_CORE1_UM_HP_INTRMTX_ALLOW_M  (PMS_CORE1_UM_HP_INTRMTX_ALLOW_V << PMS_CORE1_UM_HP_INTRMTX_ALLOW_S)
+#define PMS_CORE1_UM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_INTRMTX_ALLOW_S  22
+/** PMS_CORE1_UM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP TWAI0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_TWAI0_ALLOW    (BIT(23))
+#define PMS_CORE1_UM_HP_TWAI0_ALLOW_M  (PMS_CORE1_UM_HP_TWAI0_ALLOW_V << PMS_CORE1_UM_HP_TWAI0_ALLOW_S)
+#define PMS_CORE1_UM_HP_TWAI0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_TWAI0_ALLOW_S  23
+/** PMS_CORE1_UM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP TWAI1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_TWAI1_ALLOW    (BIT(24))
+#define PMS_CORE1_UM_HP_TWAI1_ALLOW_M  (PMS_CORE1_UM_HP_TWAI1_ALLOW_V << PMS_CORE1_UM_HP_TWAI1_ALLOW_S)
+#define PMS_CORE1_UM_HP_TWAI1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_TWAI1_ALLOW_S  24
+/** PMS_CORE1_UM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP TWAI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_TWAI2_ALLOW    (BIT(25))
+#define PMS_CORE1_UM_HP_TWAI2_ALLOW_M  (PMS_CORE1_UM_HP_TWAI2_ALLOW_V << PMS_CORE1_UM_HP_TWAI2_ALLOW_S)
+#define PMS_CORE1_UM_HP_TWAI2_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_TWAI2_ALLOW_S  25
+/** PMS_CORE1_UM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I3C master
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I3C_MST_ALLOW    (BIT(26))
+#define PMS_CORE1_UM_HP_I3C_MST_ALLOW_M  (PMS_CORE1_UM_HP_I3C_MST_ALLOW_V << PMS_CORE1_UM_HP_I3C_MST_ALLOW_S)
+#define PMS_CORE1_UM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I3C_MST_ALLOW_S  26
+/** PMS_CORE1_UM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I3C slave
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define PMS_CORE1_UM_HP_I3C_SLV_ALLOW_M  (PMS_CORE1_UM_HP_I3C_SLV_ALLOW_V << PMS_CORE1_UM_HP_I3C_SLV_ALLOW_S)
+#define PMS_CORE1_UM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I3C_SLV_ALLOW_S  27
+/** PMS_CORE1_UM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP LCD_CAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_LCDCAM_ALLOW    (BIT(28))
+#define PMS_CORE1_UM_HP_LCDCAM_ALLOW_M  (PMS_CORE1_UM_HP_LCDCAM_ALLOW_V << PMS_CORE1_UM_HP_LCDCAM_ALLOW_S)
+#define PMS_CORE1_UM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_LCDCAM_ALLOW_S  28
+/** PMS_CORE1_UM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_ADC_ALLOW    (BIT(30))
+#define PMS_CORE1_UM_HP_ADC_ALLOW_M  (PMS_CORE1_UM_HP_ADC_ALLOW_V << PMS_CORE1_UM_HP_ADC_ALLOW_S)
+#define PMS_CORE1_UM_HP_ADC_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_ADC_ALLOW_S  30
+/** PMS_CORE1_UM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UHCI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UHCI_ALLOW    (BIT(31))
+#define PMS_CORE1_UM_HP_UHCI_ALLOW_M  (PMS_CORE1_UM_HP_UHCI_ALLOW_V << PMS_CORE1_UM_HP_UHCI_ALLOW_S)
+#define PMS_CORE1_UM_HP_UHCI_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UHCI_ALLOW_S  31
+
+/** PMS_CORE1_UM_HP_PERI_PMS_REG3_REG register
+ *  Permission control register3 for HP CPU1 in user mode
+ */
+#define PMS_CORE1_UM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x44)
+/** PMS_CORE1_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP GPIO Matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_GPIO_ALLOW    (BIT(0))
+#define PMS_CORE1_UM_HP_GPIO_ALLOW_M  (PMS_CORE1_UM_HP_GPIO_ALLOW_V << PMS_CORE1_UM_HP_GPIO_ALLOW_S)
+#define PMS_CORE1_UM_HP_GPIO_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_GPIO_ALLOW_S  0
+/** PMS_CORE1_UM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_IOMUX_ALLOW    (BIT(1))
+#define PMS_CORE1_UM_HP_IOMUX_ALLOW_M  (PMS_CORE1_UM_HP_IOMUX_ALLOW_V << PMS_CORE1_UM_HP_IOMUX_ALLOW_S)
+#define PMS_CORE1_UM_HP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_IOMUX_ALLOW_S  1
+/** PMS_CORE1_UM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP system timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define PMS_CORE1_UM_HP_SYSTIMER_ALLOW_M  (PMS_CORE1_UM_HP_SYSTIMER_ALLOW_V << PMS_CORE1_UM_HP_SYSTIMER_ALLOW_S)
+#define PMS_CORE1_UM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_SYSTIMER_ALLOW_S  2
+/** PMS_CORE1_UM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP system
+ *  register.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_SYS_REG_ALLOW    (BIT(3))
+#define PMS_CORE1_UM_HP_SYS_REG_ALLOW_M  (PMS_CORE1_UM_HP_SYS_REG_ALLOW_V << PMS_CORE1_UM_HP_SYS_REG_ALLOW_S)
+#define PMS_CORE1_UM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_SYS_REG_ALLOW_S  3
+/** PMS_CORE1_UM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP_SYS_CLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_CLKRST_ALLOW    (BIT(4))
+#define PMS_CORE1_UM_HP_CLKRST_ALLOW_M  (PMS_CORE1_UM_HP_CLKRST_ALLOW_V << PMS_CORE1_UM_HP_CLKRST_ALLOW_S)
+#define PMS_CORE1_UM_HP_CLKRST_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_CLKRST_ALLOW_S  4
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_struct.h
new file mode 100644
index 0000000000..64ad594c4c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_struct.h
@@ -0,0 +1,1490 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: TEE PMS DATE REG */
+/** Type of pms_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tee_date : R/W; bitpos: [31:0]; default: 2363943;
+         *  NA
+         */
+        uint32_t tee_date:32;
+    };
+    uint32_t val;
+} tee_pms_date_reg_t;
+
+
+/** Group: TEE PMS CLK EN REG */
+/** Type of pms_clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_pms_clk_en_reg_t;
+
+
+/** Group: TEE CORE0 MM PMS REG0 REG */
+/** Type of core0_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_mm_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_psram_allow:1;
+        /** reg_core0_mm_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_flash_allow:1;
+        /** reg_core0_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_l2mem_allow:1;
+        /** reg_core0_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_l2rom_allow:1;
+        uint32_t reserved_4:2;
+        /** reg_core0_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_trace0_allow:1;
+        /** reg_core0_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_trace1_allow:1;
+        /** reg_core0_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_cpu_bus_mon_allow:1;
+        /** reg_core0_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_l2mem_mon_allow:1;
+        /** reg_core0_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_tcm_mon_allow:1;
+        /** reg_core0_mm_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_cache_allow:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} tee_core0_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE CORE0 MM PMS REG1 REG */
+/** Type of core0_mm_pms_reg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_usbotg_allow:1;
+        /** reg_core0_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_usbotg11_allow:1;
+        /** reg_core0_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_usbotg11_wrap_allow:1;
+        /** reg_core0_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_gdma_allow:1;
+        /** reg_core0_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_regdma_allow:1;
+        /** reg_core0_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_sdmmc_allow:1;
+        /** reg_core0_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_ahb_pdma_allow:1;
+        /** reg_core0_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_jpeg_allow:1;
+        /** reg_core0_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_ppa_allow:1;
+        /** reg_core0_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_dma2d_allow:1;
+        /** reg_core0_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_key_manager_allow:1;
+        /** reg_core0_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_axi_pdma_allow:1;
+        /** reg_core0_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_flash_allow:1;
+        /** reg_core0_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_psram_allow:1;
+        /** reg_core0_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_crypto_allow:1;
+        /** reg_core0_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_gmac_allow:1;
+        /** reg_core0_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_usb_phy_allow:1;
+        /** reg_core0_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_pvt_allow:1;
+        /** reg_core0_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_csi_host_allow:1;
+        /** reg_core0_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_dsi_host_allow:1;
+        /** reg_core0_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_isp_allow:1;
+        /** reg_core0_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_h264_core_allow:1;
+        /** reg_core0_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_rmt_allow:1;
+        /** reg_core0_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_bitsrambler_allow:1;
+        /** reg_core0_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_axi_icm_allow:1;
+        /** reg_core0_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_peri_pms_allow:1;
+        /** reg_core0_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_lp2hp_peri_pms_allow:1;
+        /** reg_core0_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_dma_pms_allow:1;
+        /** reg_core0_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_h264_dma2d_allow:1;
+        /** reg_core0_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_axi_perf_mon_allow:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_core0_mm_pms_reg1_reg_t;
+
+
+/** Group: TEE CORE0 MM PMS REG2 REG */
+/** Type of core0_mm_pms_reg2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_mcpwm0_allow:1;
+        /** reg_core0_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_mcpwm1_allow:1;
+        /** reg_core0_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_timer_group0_allow:1;
+        /** reg_core0_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_timer_group1_allow:1;
+        /** reg_core0_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i2c0_allow:1;
+        /** reg_core0_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i2c1_allow:1;
+        /** reg_core0_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i2s0_allow:1;
+        /** reg_core0_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i2s1_allow:1;
+        /** reg_core0_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i2s2_allow:1;
+        /** reg_core0_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_pcnt_allow:1;
+        /** reg_core0_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uart0_allow:1;
+        /** reg_core0_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uart1_allow:1;
+        /** reg_core0_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uart2_allow:1;
+        /** reg_core0_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uart3_allow:1;
+        /** reg_core0_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uart4_allow:1;
+        /** reg_core0_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_parlio_allow:1;
+        /** reg_core0_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_gpspi2_allow:1;
+        /** reg_core0_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_gpspi3_allow:1;
+        /** reg_core0_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_usbdevice_allow:1;
+        /** reg_core0_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_ledc_allow:1;
+        uint32_t reserved_20:1;
+        /** reg_core0_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_etm_allow:1;
+        /** reg_core0_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_intrmtx_allow:1;
+        /** reg_core0_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_twai0_allow:1;
+        /** reg_core0_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_twai1_allow:1;
+        /** reg_core0_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_twai2_allow:1;
+        /** reg_core0_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i3c_mst_allow:1;
+        /** reg_core0_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i3c_slv_allow:1;
+        /** reg_core0_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_lcdcam_allow:1;
+        uint32_t reserved_29:1;
+        /** reg_core0_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_adc_allow:1;
+        /** reg_core0_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uhci_allow:1;
+    };
+    uint32_t val;
+} tee_core0_mm_pms_reg2_reg_t;
+
+
+/** Group: TEE CORE0 MM PMS REG3 REG */
+/** Type of core0_mm_pms_reg3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_gpio_allow:1;
+        /** reg_core0_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_iomux_allow:1;
+        /** reg_core0_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_systimer_allow:1;
+        /** reg_core0_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_sys_reg_allow:1;
+        /** reg_core0_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_clkrst_allow:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} tee_core0_mm_pms_reg3_reg_t;
+
+
+/** Group: TEE CORE0 UM PMS REG0 REG */
+/** Type of core0_um_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_um_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_psram_allow:1;
+        /** reg_core0_um_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_flash_allow:1;
+        /** reg_core0_um_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_l2mem_allow:1;
+        /** reg_core0_um_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_l2rom_allow:1;
+        uint32_t reserved_4:2;
+        /** reg_core0_um_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_trace0_allow:1;
+        /** reg_core0_um_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_trace1_allow:1;
+        /** reg_core0_um_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_cpu_bus_mon_allow:1;
+        /** reg_core0_um_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_l2mem_mon_allow:1;
+        /** reg_core0_um_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_tcm_mon_allow:1;
+        /** reg_core0_um_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_cache_allow:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} tee_core0_um_pms_reg0_reg_t;
+
+
+/** Group: TEE CORE0 UM PMS REG1 REG */
+/** Type of core0_um_pms_reg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_um_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_usbotg_allow:1;
+        /** reg_core0_um_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_usbotg11_allow:1;
+        /** reg_core0_um_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_usbotg11_wrap_allow:1;
+        /** reg_core0_um_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_gdma_allow:1;
+        /** reg_core0_um_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_regdma_allow:1;
+        /** reg_core0_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_sdmmc_allow:1;
+        /** reg_core0_um_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_ahb_pdma_allow:1;
+        /** reg_core0_um_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_jpeg_allow:1;
+        /** reg_core0_um_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_ppa_allow:1;
+        /** reg_core0_um_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_dma2d_allow:1;
+        /** reg_core0_um_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_key_manager_allow:1;
+        /** reg_core0_um_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_axi_pdma_allow:1;
+        /** reg_core0_um_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_flash_allow:1;
+        /** reg_core0_um_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_psram_allow:1;
+        /** reg_core0_um_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_crypto_allow:1;
+        /** reg_core0_um_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_gmac_allow:1;
+        /** reg_core0_um_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_usb_phy_allow:1;
+        /** reg_core0_um_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_pvt_allow:1;
+        /** reg_core0_um_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_csi_host_allow:1;
+        /** reg_core0_um_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_dsi_host_allow:1;
+        /** reg_core0_um_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_isp_allow:1;
+        /** reg_core0_um_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_h264_core_allow:1;
+        /** reg_core0_um_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_rmt_allow:1;
+        /** reg_core0_um_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_bitsrambler_allow:1;
+        /** reg_core0_um_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_axi_icm_allow:1;
+        /** reg_core0_um_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_peri_pms_allow:1;
+        /** reg_core0_um_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_lp2hp_peri_pms_allow:1;
+        /** reg_core0_um_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_dma_pms_allow:1;
+        /** reg_core0_um_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_h264_dma2d_allow:1;
+        /** reg_core0_um_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_axi_perf_mon_allow:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_core0_um_pms_reg1_reg_t;
+
+
+/** Group: TEE CORE0 UM PMS REG2 REG */
+/** Type of core0_um_pms_reg2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_um_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_mcpwm0_allow:1;
+        /** reg_core0_um_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_mcpwm1_allow:1;
+        /** reg_core0_um_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_timer_group0_allow:1;
+        /** reg_core0_um_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_timer_group1_allow:1;
+        /** reg_core0_um_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i2c0_allow:1;
+        /** reg_core0_um_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i2c1_allow:1;
+        /** reg_core0_um_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i2s0_allow:1;
+        /** reg_core0_um_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i2s1_allow:1;
+        /** reg_core0_um_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i2s2_allow:1;
+        /** reg_core0_um_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_pcnt_allow:1;
+        /** reg_core0_um_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uart0_allow:1;
+        /** reg_core0_um_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uart1_allow:1;
+        /** reg_core0_um_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uart2_allow:1;
+        /** reg_core0_um_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uart3_allow:1;
+        /** reg_core0_um_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uart4_allow:1;
+        /** reg_core0_um_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_parlio_allow:1;
+        /** reg_core0_um_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_gpspi2_allow:1;
+        /** reg_core0_um_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_gpspi3_allow:1;
+        /** reg_core0_um_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_usbdevice_allow:1;
+        /** reg_core0_um_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_ledc_allow:1;
+        uint32_t reserved_20:1;
+        /** reg_core0_um_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_etm_allow:1;
+        /** reg_core0_um_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_intrmtx_allow:1;
+        /** reg_core0_um_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_twai0_allow:1;
+        /** reg_core0_um_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_twai1_allow:1;
+        /** reg_core0_um_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_twai2_allow:1;
+        /** reg_core0_um_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i3c_mst_allow:1;
+        /** reg_core0_um_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i3c_slv_allow:1;
+        /** reg_core0_um_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_lcdcam_allow:1;
+        uint32_t reserved_29:1;
+        /** reg_core0_um_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_adc_allow:1;
+        /** reg_core0_um_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uhci_allow:1;
+    };
+    uint32_t val;
+} tee_core0_um_pms_reg2_reg_t;
+
+
+/** Group: TEE CORE0 UM PMS REG3 REG */
+/** Type of core0_um_pms_reg3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_um_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_gpio_allow:1;
+        /** reg_core0_um_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_iomux_allow:1;
+        /** reg_core0_um_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_systimer_allow:1;
+        /** reg_core0_um_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_sys_reg_allow:1;
+        /** reg_core0_um_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_clkrst_allow:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} tee_core0_um_pms_reg3_reg_t;
+
+
+/** Group: TEE CORE1 MM PMS REG0 REG */
+/** Type of core1_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_mm_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_psram_allow:1;
+        /** reg_core1_mm_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_flash_allow:1;
+        /** reg_core1_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_l2mem_allow:1;
+        /** reg_core1_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_l2rom_allow:1;
+        uint32_t reserved_4:2;
+        /** reg_core1_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_trace0_allow:1;
+        /** reg_core1_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_trace1_allow:1;
+        /** reg_core1_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_cpu_bus_mon_allow:1;
+        /** reg_core1_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_l2mem_mon_allow:1;
+        /** reg_core1_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_tcm_mon_allow:1;
+        /** reg_core1_mm_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_cache_allow:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} tee_core1_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE CORE1 MM PMS REG1 REG */
+/** Type of core1_mm_pms_reg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_usbotg_allow:1;
+        /** reg_core1_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_usbotg11_allow:1;
+        /** reg_core1_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_usbotg11_wrap_allow:1;
+        /** reg_core1_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_gdma_allow:1;
+        /** reg_core1_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_regdma_allow:1;
+        /** reg_core1_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_sdmmc_allow:1;
+        /** reg_core1_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_ahb_pdma_allow:1;
+        /** reg_core1_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_jpeg_allow:1;
+        /** reg_core1_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_ppa_allow:1;
+        /** reg_core1_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_dma2d_allow:1;
+        /** reg_core1_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_key_manager_allow:1;
+        /** reg_core1_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_axi_pdma_allow:1;
+        /** reg_core1_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_flash_allow:1;
+        /** reg_core1_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_psram_allow:1;
+        /** reg_core1_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_crypto_allow:1;
+        /** reg_core1_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_gmac_allow:1;
+        /** reg_core1_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_usb_phy_allow:1;
+        /** reg_core1_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_pvt_allow:1;
+        /** reg_core1_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_csi_host_allow:1;
+        /** reg_core1_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_dsi_host_allow:1;
+        /** reg_core1_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_isp_allow:1;
+        /** reg_core1_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_h264_core_allow:1;
+        /** reg_core1_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_rmt_allow:1;
+        /** reg_core1_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_bitsrambler_allow:1;
+        /** reg_core1_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_axi_icm_allow:1;
+        /** reg_core1_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_peri_pms_allow:1;
+        /** reg_core1_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_lp2hp_peri_pms_allow:1;
+        /** reg_core1_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_dma_pms_allow:1;
+        /** reg_core1_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_h264_dma2d_allow:1;
+        /** reg_core1_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_axi_perf_mon_allow:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_core1_mm_pms_reg1_reg_t;
+
+
+/** Group: TEE CORE1 MM PMS REG2 REG */
+/** Type of core1_mm_pms_reg2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_mcpwm0_allow:1;
+        /** reg_core1_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_mcpwm1_allow:1;
+        /** reg_core1_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_timer_group0_allow:1;
+        /** reg_core1_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_timer_group1_allow:1;
+        /** reg_core1_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i2c0_allow:1;
+        /** reg_core1_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i2c1_allow:1;
+        /** reg_core1_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i2s0_allow:1;
+        /** reg_core1_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i2s1_allow:1;
+        /** reg_core1_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i2s2_allow:1;
+        /** reg_core1_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_pcnt_allow:1;
+        /** reg_core1_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uart0_allow:1;
+        /** reg_core1_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uart1_allow:1;
+        /** reg_core1_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uart2_allow:1;
+        /** reg_core1_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uart3_allow:1;
+        /** reg_core1_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uart4_allow:1;
+        /** reg_core1_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_parlio_allow:1;
+        /** reg_core1_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_gpspi2_allow:1;
+        /** reg_core1_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_gpspi3_allow:1;
+        /** reg_core1_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_usbdevice_allow:1;
+        /** reg_core1_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_ledc_allow:1;
+        uint32_t reserved_20:1;
+        /** reg_core1_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_etm_allow:1;
+        /** reg_core1_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_intrmtx_allow:1;
+        /** reg_core1_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_twai0_allow:1;
+        /** reg_core1_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_twai1_allow:1;
+        /** reg_core1_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_twai2_allow:1;
+        /** reg_core1_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i3c_mst_allow:1;
+        /** reg_core1_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i3c_slv_allow:1;
+        /** reg_core1_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_lcdcam_allow:1;
+        uint32_t reserved_29:1;
+        /** reg_core1_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_adc_allow:1;
+        /** reg_core1_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uhci_allow:1;
+    };
+    uint32_t val;
+} tee_core1_mm_pms_reg2_reg_t;
+
+
+/** Group: TEE CORE1 MM PMS REG3 REG */
+/** Type of core1_mm_pms_reg3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_gpio_allow:1;
+        /** reg_core1_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_iomux_allow:1;
+        /** reg_core1_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_systimer_allow:1;
+        /** reg_core1_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_sys_reg_allow:1;
+        /** reg_core1_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_clkrst_allow:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} tee_core1_mm_pms_reg3_reg_t;
+
+
+/** Group: TEE CORE1 UM PMS REG0 REG */
+/** Type of core1_um_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_um_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_psram_allow:1;
+        /** reg_core1_um_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_flash_allow:1;
+        /** reg_core1_um_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_l2mem_allow:1;
+        /** reg_core1_um_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_l2rom_allow:1;
+        uint32_t reserved_4:2;
+        /** reg_core1_um_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_trace0_allow:1;
+        /** reg_core1_um_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_trace1_allow:1;
+        /** reg_core1_um_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_cpu_bus_mon_allow:1;
+        /** reg_core1_um_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_l2mem_mon_allow:1;
+        /** reg_core1_um_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_tcm_mon_allow:1;
+        /** reg_core1_um_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_cache_allow:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} tee_core1_um_pms_reg0_reg_t;
+
+
+/** Group: TEE CORE1 UM PMS REG1 REG */
+/** Type of core1_um_pms_reg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_um_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_usbotg_allow:1;
+        /** reg_core1_um_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_usbotg11_allow:1;
+        /** reg_core1_um_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_usbotg11_wrap_allow:1;
+        /** reg_core1_um_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_gdma_allow:1;
+        /** reg_core1_um_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_regdma_allow:1;
+        /** reg_core1_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_sdmmc_allow:1;
+        /** reg_core1_um_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_ahb_pdma_allow:1;
+        /** reg_core1_um_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_jpeg_allow:1;
+        /** reg_core1_um_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_ppa_allow:1;
+        /** reg_core1_um_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_dma2d_allow:1;
+        /** reg_core1_um_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_key_manager_allow:1;
+        /** reg_core1_um_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_axi_pdma_allow:1;
+        /** reg_core1_um_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_flash_allow:1;
+        /** reg_core1_um_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_psram_allow:1;
+        /** reg_core1_um_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_crypto_allow:1;
+        /** reg_core1_um_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_gmac_allow:1;
+        /** reg_core1_um_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_usb_phy_allow:1;
+        /** reg_core1_um_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_pvt_allow:1;
+        /** reg_core1_um_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_csi_host_allow:1;
+        /** reg_core1_um_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_dsi_host_allow:1;
+        /** reg_core1_um_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_isp_allow:1;
+        /** reg_core1_um_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_h264_core_allow:1;
+        /** reg_core1_um_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_rmt_allow:1;
+        /** reg_core1_um_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_bitsrambler_allow:1;
+        /** reg_core1_um_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_axi_icm_allow:1;
+        /** reg_core1_um_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_peri_pms_allow:1;
+        /** reg_core1_um_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_lp2hp_peri_pms_allow:1;
+        /** reg_core1_um_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_dma_pms_allow:1;
+        /** reg_core1_um_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_h264_dma2d_allow:1;
+        /** reg_core1_um_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_axi_perf_mon_allow:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_core1_um_pms_reg1_reg_t;
+
+
+/** Group: TEE CORE1 UM PMS REG2 REG */
+/** Type of core1_um_pms_reg2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_um_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_mcpwm0_allow:1;
+        /** reg_core1_um_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_mcpwm1_allow:1;
+        /** reg_core1_um_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_timer_group0_allow:1;
+        /** reg_core1_um_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_timer_group1_allow:1;
+        /** reg_core1_um_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i2c0_allow:1;
+        /** reg_core1_um_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i2c1_allow:1;
+        /** reg_core1_um_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i2s0_allow:1;
+        /** reg_core1_um_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i2s1_allow:1;
+        /** reg_core1_um_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i2s2_allow:1;
+        /** reg_core1_um_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_pcnt_allow:1;
+        /** reg_core1_um_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uart0_allow:1;
+        /** reg_core1_um_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uart1_allow:1;
+        /** reg_core1_um_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uart2_allow:1;
+        /** reg_core1_um_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uart3_allow:1;
+        /** reg_core1_um_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uart4_allow:1;
+        /** reg_core1_um_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_parlio_allow:1;
+        /** reg_core1_um_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_gpspi2_allow:1;
+        /** reg_core1_um_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_gpspi3_allow:1;
+        /** reg_core1_um_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_usbdevice_allow:1;
+        /** reg_core1_um_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_ledc_allow:1;
+        uint32_t reserved_20:1;
+        /** reg_core1_um_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_etm_allow:1;
+        /** reg_core1_um_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_intrmtx_allow:1;
+        /** reg_core1_um_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_twai0_allow:1;
+        /** reg_core1_um_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_twai1_allow:1;
+        /** reg_core1_um_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_twai2_allow:1;
+        /** reg_core1_um_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i3c_mst_allow:1;
+        /** reg_core1_um_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i3c_slv_allow:1;
+        /** reg_core1_um_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_lcdcam_allow:1;
+        uint32_t reserved_29:1;
+        /** reg_core1_um_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_adc_allow:1;
+        /** reg_core1_um_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uhci_allow:1;
+    };
+    uint32_t val;
+} tee_core1_um_pms_reg2_reg_t;
+
+
+/** Group: TEE CORE1 UM PMS REG3 REG */
+/** Type of core1_um_pms_reg3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_um_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_gpio_allow:1;
+        /** reg_core1_um_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_iomux_allow:1;
+        /** reg_core1_um_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_systimer_allow:1;
+        /** reg_core1_um_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_sys_reg_allow:1;
+        /** reg_core1_um_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_clkrst_allow:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} tee_core1_um_pms_reg3_reg_t;
+
+
+/** Group: TEE REGDMA PERI PMS REG */
+/** Type of regdma_peri_pms register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_regdma_peri_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_regdma_peri_allow:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_regdma_peri_pms_reg_t;
+
+
+typedef struct {
+    volatile tee_pms_date_reg_t pms_date;
+    volatile tee_pms_clk_en_reg_t pms_clk_en;
+    volatile tee_core0_mm_pms_reg0_reg_t core0_mm_pms_reg0;
+    volatile tee_core0_mm_pms_reg1_reg_t core0_mm_pms_reg1;
+    volatile tee_core0_mm_pms_reg2_reg_t core0_mm_pms_reg2;
+    volatile tee_core0_mm_pms_reg3_reg_t core0_mm_pms_reg3;
+    volatile tee_core0_um_pms_reg0_reg_t core0_um_pms_reg0;
+    volatile tee_core0_um_pms_reg1_reg_t core0_um_pms_reg1;
+    volatile tee_core0_um_pms_reg2_reg_t core0_um_pms_reg2;
+    volatile tee_core0_um_pms_reg3_reg_t core0_um_pms_reg3;
+    volatile tee_core1_mm_pms_reg0_reg_t core1_mm_pms_reg0;
+    volatile tee_core1_mm_pms_reg1_reg_t core1_mm_pms_reg1;
+    volatile tee_core1_mm_pms_reg2_reg_t core1_mm_pms_reg2;
+    volatile tee_core1_mm_pms_reg3_reg_t core1_mm_pms_reg3;
+    volatile tee_core1_um_pms_reg0_reg_t core1_um_pms_reg0;
+    volatile tee_core1_um_pms_reg1_reg_t core1_um_pms_reg1;
+    volatile tee_core1_um_pms_reg2_reg_t core1_um_pms_reg2;
+    volatile tee_core1_um_pms_reg3_reg_t core1_um_pms_reg3;
+    volatile tee_regdma_peri_pms_reg_t regdma_peri_pms;
+} tee_dev_t;
+
+extern tee_dev_t HP_PERI_PMS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dev_t) == 0x4c, "Invalid size of tee_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_sys_clkrst_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_sys_clkrst_reg.h
new file mode 100644
index 0000000000..571ef41a2e
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_sys_clkrst_reg.h
@@ -0,0 +1,4399 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_SYS_CLKRST_CLK_EN0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_CLK_EN0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x0)
+/** HP_SYS_CLKRST_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CLK_EN_M  (HP_SYS_CLKRST_REG_CLK_EN_V << HP_SYS_CLKRST_REG_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x4)
+/** HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM : R/W; bitpos: [3:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM    0x0000000FU
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_M  (HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_V << HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_S)
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_S  0
+/** HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE : WT; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE    (BIT(4))
+#define HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_M  (HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_V << HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_S)
+#define HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_S  4
+/** HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM : R/W; bitpos: [12:5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_S  5
+/** HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR : R/W; bitpos: [20:13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_S  13
+/** HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR : R/W; bitpos: [28:21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_S  21
+
+/** HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x8)
+/** HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM : R/W; bitpos: [31:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_S  24
+
+/** HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc)
+/** HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_S  0
+/** HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_S  8
+/** HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_S  16
+/** HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR : R/W; bitpos: [31:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_S  24
+
+/** HP_SYS_CLKRST_ROOT_CLK_CTRL3_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_ROOT_CLK_CTRL3_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x10)
+/** HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_S  0
+
+/** HP_SYS_CLKRST_SOC_CLK_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_SOC_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x14)
+/** HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_V << HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_V << HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN : R/W; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_S  11
+/** HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN : R/W; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN    (BIT(12))
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_S  12
+/** HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN    (BIT(13))
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_S  13
+/** HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN_S  15
+/** HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN : R/W; bitpos: [17]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN_S  17
+/** HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN : R/W; bitpos: [18]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN    (BIT(21))
+#define HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN_S  21
+/** HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN    (BIT(23))
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_S  23
+/** HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN_S  26
+/** HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN : R/W; bitpos: [29]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_S  29
+/** HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_S  30
+/** HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_SOC_CLK_CTRL1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_SOC_CLK_CTRL1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x18)
+/** HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN_S  11
+/** HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN    (BIT(12))
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_S  12
+/** HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN    (BIT(13))
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_S  13
+/** HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN_S  15
+/** HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN : R/W; bitpos: [17]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_S  17
+/** HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN : R/W; bitpos: [18]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN : R/W; bitpos: [21]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN    (BIT(21))
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_S  21
+/** HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN    (BIT(23))
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_S  23
+/** HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_S  26
+/** HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN : R/W; bitpos: [29]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S  29
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S  30
+/** HP_SYS_CLKRST_REG_H264_SYS_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_H264_SYS_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_H264_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_H264_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_H264_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_H264_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_H264_SYS_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_SOC_CLK_CTRL2_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_SOC_CLK_CTRL2_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1c)
+/** HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_V << HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_V << HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_ICM_APB_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_V << HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_ADC_APB_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_APB_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_ADC_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_ADC_APB_CLK_EN_V << HP_SYS_CLKRST_REG_ADC_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ADC_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ADC_APB_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_UART0_APB_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_UART1_APB_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_UART2_APB_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_UART3_APB_CLK_EN : R/W; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_UART4_APB_CLK_EN : R/W; bitpos: [11]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_APB_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_UART4_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART4_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART4_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART4_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART4_APB_CLK_EN_S  11
+/** HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN    (BIT(12))
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_S  12
+/** HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN    (BIT(13))
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_S  13
+/** HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_S  15
+/** HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN_S  17
+/** HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN : R/W; bitpos: [21]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN    (BIT(21))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_S  21
+/** HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN    (BIT(23))
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_V << HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_S  23
+/** HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN_S  26
+/** HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN : R/W; bitpos: [29]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_V << HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_S  29
+/** HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN_V << HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN_S  30
+/** HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_SOC_CLK_CTRL3_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_SOC_CLK_CTRL3_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x20)
+/** HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN_V << HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_V << HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_ETM_APB_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_V << HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_V << HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN_S  4
+
+/** HP_SYS_CLKRST_REF_CLK_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REF_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x24)
+/** HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 9;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 19;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_S  16
+/** HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM : R/W; bitpos: [31:24]; default: 2;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_S  24
+
+/** HP_SYS_CLKRST_REF_CLK_CTRL1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REF_CLK_CTRL1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x28)
+/** HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 3;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 5;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 23;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_S  16
+/** HP_SYS_CLKRST_REG_TM_400M_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_400M_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_TM_400M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_400M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_400M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_400M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_400M_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_TM_200M_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_200M_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_TM_200M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_200M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_200M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_200M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_200M_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_TM_100M_CLK_EN : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_100M_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_TM_100M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_100M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_100M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_100M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_100M_CLK_EN_S  26
+/** HP_SYS_CLKRST_REG_REF_50M_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_50M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_50M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_REF_25M_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_25M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_25M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_TM_480M_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_480M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_480M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN_S  29
+/** HP_SYS_CLKRST_REG_REF_240M_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_240M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_240M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN_S  30
+/** HP_SYS_CLKRST_REG_TM_240M_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_240M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_240M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_REF_CLK_CTRL2_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REF_CLK_CTRL2_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x2c)
+/** HP_SYS_CLKRST_REG_REF_160M_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_160M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_160M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TM_160M_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_160M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_160M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_REF_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_120M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_120M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_TM_120M_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_120M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_120M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_REF_80M_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_80M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_80M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_TM_80M_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_80M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_80M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_TM_60M_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_60M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_60M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_TM_48M_CLK_EN : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_48M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_48M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_REF_20M_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_20M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_20M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_TM_20M_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_20M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_20M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN_S  9
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL00_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL00_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x30)
+/** HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_M  (HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_V << HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_M  (HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_V << HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM : R/W; bitpos: [11:4]; default: 3;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_S  4
+/** HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL : R/W; bitpos: [13:12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_S  12
+/** HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN : R/W; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_M  (HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_V << HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_M  (HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_V << HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_S  15
+/** HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_S  16
+/** HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN_M  (HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN_V << HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL : R/W; bitpos: [26:25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL_S  25
+/** HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL    (BIT(28))
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL_S  28
+/** HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN_S  29
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL01_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL01_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x34)
+/** HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL    (BIT(8))
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL_S  8
+/** HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM : R/W; bitpos: [17:10]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM_S  10
+/** HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL    (BIT(18))
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL_S  18
+/** HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN    (BIT(21))
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN_S  21
+/** HP_SYS_CLKRST_REG_SDIO_HS_MODE : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE    (BIT(22))
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE_M  (HP_SYS_CLKRST_REG_SDIO_HS_MODE_V << HP_SYS_CLKRST_REG_SDIO_HS_MODE_S)
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE_S  22
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL    (BIT(23))
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_S  23
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_S  24
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL02_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL02_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x38)
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE : WT; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE    (BIT(8))
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_S  8
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L : R/W; bitpos: [12:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L    0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_S  9
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H : R/W; bitpos: [16:13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H    0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_S  13
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N : R/W; bitpos: [20:17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N    0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_S  17
+/** HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL : R/W; bitpos: [22:21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_S  21
+/** HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL : R/W; bitpos: [24:23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_S  23
+/** HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL : R/W; bitpos: [26:25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_S  25
+/** HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_S  29
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_S  30
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL03_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL03_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x3c)
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_S  1
+/** HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_S  2
+/** HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN_V << HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_S  5
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_S  7
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL : R/W; bitpos: [18:16]; default:
+ *  0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL    0x00000007U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL_V  0x00000007U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL_S  16
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM : R/W; bitpos: [26:19]; default:
+ *  1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM_S  19
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL10_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL10_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x40)
+/** HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL    (BIT(0))
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_I2C0_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C0_CLK_EN_V << HP_SYS_CLKRST_REG_I2C0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM : R/W; bitpos: [9:2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_S  2
+/** HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR : R/W; bitpos: [17:10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_S  10
+/** HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR : R/W; bitpos: [25:18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_S  18
+/** HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL    (BIT(26))
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_S  26
+/** HP_SYS_CLKRST_REG_I2C1_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C1_CLK_EN_V << HP_SYS_CLKRST_REG_I2C1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN_S  27
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL11_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL11_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x44)
+/** HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL : R/W; bitpos: [26:25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_S  25
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL12_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL12_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x48)
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_N : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_S  0
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_X : R/W; bitpos: [16:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_S  8
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y : R/W; bitpos: [25:17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_S  17
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL13_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL13_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x4c)
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_S  0
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1 : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1    (BIT(9))
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_S  9
+/** HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL : R/W; bitpos: [12:11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_S  11
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_N : R/W; bitpos: [20:13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_S  13
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_X : R/W; bitpos: [29:21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_S  21
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL14_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL14_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x50)
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_S  0
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z : R/W; bitpos: [17:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_S  9
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1 : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1    (BIT(18))
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_S  18
+/** HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL    (BIT(19))
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_M  (HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_V << HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_S  19
+/** HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL : R/W; bitpos: [22:21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_S  21
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_N : R/W; bitpos: [30:23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_S  23
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL15_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL15_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x54)
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_X : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_S  0
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y : R/W; bitpos: [17:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_S  9
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z : R/W; bitpos: [26:18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_S  18
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1    (BIT(27))
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_S  27
+/** HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL : R/W; bitpos: [30:29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_S  29
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL16_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL16_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x58)
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_N : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_S  0
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_X : R/W; bitpos: [16:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_S  8
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y : R/W; bitpos: [25:17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_S  17
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL17_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL17_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x5c)
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_S  0
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1 : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1    (BIT(9))
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_S  9
+/** HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL    (BIT(10))
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_M  (HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_V << HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_S  10
+/** HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN_S  11
+/** HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL : R/W; bitpos: [13:12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL_S  12
+/** HP_SYS_CLKRST_REG_I2S2_RX_DIV_N : R/W; bitpos: [21:14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S2_RX_DIV_N_V << HP_SYS_CLKRST_REG_I2S2_RX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_N_S  14
+/** HP_SYS_CLKRST_REG_I2S2_RX_DIV_X : R/W; bitpos: [30:22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S2_RX_DIV_X_V << HP_SYS_CLKRST_REG_I2S2_RX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_X_S  22
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL18_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL18_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x60)
+/** HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y_S  0
+/** HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z : R/W; bitpos: [17:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z_S  9
+/** HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1 : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1    (BIT(18))
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1_S  18
+/** HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL_S  20
+/** HP_SYS_CLKRST_REG_I2S2_TX_DIV_N : R/W; bitpos: [29:22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S2_TX_DIV_N_V << HP_SYS_CLKRST_REG_I2S2_TX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_N_S  22
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL19_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL19_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x64)
+/** HP_SYS_CLKRST_REG_I2S2_TX_DIV_X : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S2_TX_DIV_X_V << HP_SYS_CLKRST_REG_I2S2_TX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_X_S  0
+/** HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y : R/W; bitpos: [17:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y_S  9
+/** HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z : R/W; bitpos: [26:18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z_S  18
+/** HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1    (BIT(27))
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1_S  27
+/** HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL    (BIT(28))
+#define HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL_M  (HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL_V << HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL_S  28
+/** HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL : R/W; bitpos: [30:29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_S  29
+/** HP_SYS_CLKRST_REG_LCD_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN_M  (HP_SYS_CLKRST_REG_LCD_CLK_EN_V << HP_SYS_CLKRST_REG_LCD_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL110_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL110_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x68)
+/** HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_UART0_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN_M  (HP_SYS_CLKRST_REG_UART0_CLK_EN_V << HP_SYS_CLKRST_REG_UART0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN_S  26
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL111_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL111_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x6c)
+/** HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_UART1_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN_M  (HP_SYS_CLKRST_REG_UART1_CLK_EN_V << HP_SYS_CLKRST_REG_UART1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN_S  26
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL112_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL112_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x70)
+/** HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_UART2_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN_M  (HP_SYS_CLKRST_REG_UART2_CLK_EN_V << HP_SYS_CLKRST_REG_UART2_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN_S  26
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL113_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL113_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x74)
+/** HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_UART3_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN_M  (HP_SYS_CLKRST_REG_UART3_CLK_EN_V << HP_SYS_CLKRST_REG_UART3_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN_S  26
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL114_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL114_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x78)
+/** HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_UART4_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_UART4_CLK_EN_M  (HP_SYS_CLKRST_REG_UART4_CLK_EN_V << HP_SYS_CLKRST_REG_UART4_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART4_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART4_CLK_EN_S  26
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL115_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL115_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x7c)
+/** HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL    (BIT(24))
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_TWAI0_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI0_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL    (BIT(26))
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_S  26
+/** HP_SYS_CLKRST_REG_TWAI1_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI1_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL    (BIT(28))
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL_S  28
+/** HP_SYS_CLKRST_REG_TWAI2_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI2_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI2_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_EN_S  29
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL116_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL116_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x80)
+/** HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL    0x00000007U
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_V  0x00000007U
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_S  4
+/** HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_S  12
+/** HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL : R/W; bitpos: [23:21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL    0x00000007U
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_V  0x00000007U
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_S  21
+/** HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_S  24
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL117_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL117_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x84)
+/** HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL : R/W; bitpos: [18:17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_S  17
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM : R/W; bitpos: [27:20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_S  20
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL118_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL118_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x88)
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_S  0
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_S  8
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_S  16
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM : R/W; bitpos: [26:19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_S  19
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL119_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL119_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x8c)
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_S  0
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_S  8
+/** HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL_S  16
+/** HP_SYS_CLKRST_REG_I3C_MST_CLK_EN : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_EN_M  (HP_SYS_CLKRST_REG_I3C_MST_CLK_EN_V << HP_SYS_CLKRST_REG_I3C_MST_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM : R/W; bitpos: [26:19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM_S  19
+/** HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL : R/W; bitpos: [28:27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_S  27
+/** HP_SYS_CLKRST_REG_CAM_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN_M  (HP_SYS_CLKRST_REG_CAM_CLK_EN_V << HP_SYS_CLKRST_REG_CAM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN_S  29
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL120_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL120_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x90)
+/** HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_S  16
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL20_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL20_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x94)
+/** HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_MCPWM0_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_S  3
+/** HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL : R/W; bitpos: [12:11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_S  11
+/** HP_SYS_CLKRST_REG_MCPWM1_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN    (BIT(13))
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_S  13
+/** HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM : R/W; bitpos: [21:14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_S  14
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL : R/W; bitpos: [23:22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_S  22
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL : R/W; bitpos: [26:25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_S  25
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL : R/W; bitpos: [29:28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_S  28
+/** HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_S  30
+/** HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL21_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL21_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x98)
+/** HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL    0x0000000FU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM : R/W; bitpos: [19:4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM    0x0000FFFFU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_V  0x0000FFFFU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_S  4
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_S  20
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL : R/W; bitpos: [24:23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_S  23
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_S  26
+/** HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL    (BIT(29))
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_S  29
+/** HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_M  (HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_V << HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_S  30
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL22_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL22_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x9c)
+/** HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_LEDC_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LEDC_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_LEDC_CLK_EN_M  (HP_SYS_CLKRST_REG_LEDC_CLK_EN_V << HP_SYS_CLKRST_REG_LEDC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LEDC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_RMT_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN_M  (HP_SYS_CLKRST_REG_RMT_CLK_EN_V << HP_SYS_CLKRST_REG_RMT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM : R/W; bitpos: [13:6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_S  6
+/** HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR : R/W; bitpos: [21:14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_S  14
+/** HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR : R/W; bitpos: [29:22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_S  22
+/** HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL_S  30
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL23_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL23_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa0)
+/** HP_SYS_CLKRST_REG_ADC_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_ADC_CLK_EN_M  (HP_SYS_CLKRST_REG_ADC_CLK_EN_V << HP_SYS_CLKRST_REG_ADC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ADC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ADC_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM : R/W; bitpos: [8:1]; default: 4;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM_S  1
+/** HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR : R/W; bitpos: [16:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR_S  9
+/** HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR : R/W; bitpos: [24:17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR_S  17
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL24_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL24_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa4)
+/** HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_S  16
+/** HP_SYS_CLKRST_REG_PVT_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN_S  24
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL25_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL25_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa8)
+/** HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_S  11
+/** HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL : R/W; bitpos: [13:12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_S  12
+/** HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN : R/W; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_S  15
+/** HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN : R/W; bitpos: [17]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_S  17
+/** HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN : R/W; bitpos: [18]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN : R/W; bitpos: [21]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN    (BIT(21))
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_S  21
+/** HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL : R/W; bitpos: [24:23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL_S  23
+/** HP_SYS_CLKRST_REG_ISP_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ISP_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_ISP_CLK_EN_M  (HP_SYS_CLKRST_REG_ISP_CLK_EN_V << HP_SYS_CLKRST_REG_ISP_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ISP_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ISP_CLK_EN_S  25
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL26_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL26_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xac)
+/** HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL    (BIT(8))
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_S  8
+/** HP_SYS_CLKRST_REG_IOMUX_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN_M  (HP_SYS_CLKRST_REG_IOMUX_CLK_EN_V << HP_SYS_CLKRST_REG_IOMUX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM : R/W; bitpos: [17:10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_S  10
+/** HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL    (BIT(18))
+#define HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL_S  18
+/** HP_SYS_CLKRST_REG_H264_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_H264_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_H264_CLK_EN_M  (HP_SYS_CLKRST_REG_H264_CLK_EN_V << HP_SYS_CLKRST_REG_H264_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_H264_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_H264_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM : R/W; bitpos: [27:20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM_S  20
+/** HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL    (BIT(28))
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL_S  28
+/** HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN_V << HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN_S  29
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL27_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL27_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xb0)
+/** HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL    (BIT(8))
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL_S  8
+/** HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN_V << HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM : R/W; bitpos: [17:10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM_S  10
+
+/** HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xb4)
+/** HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON    (BIT(0))
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_S  0
+/** HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON    (BIT(1))
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_S  1
+/** HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON    (BIT(2))
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON_S  2
+/** HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON    (BIT(3))
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON_S  3
+/** HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON    (BIT(4))
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON_S  4
+/** HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON : R/W; bitpos: [5]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON    (BIT(5))
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_S  5
+/** HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON : R/W; bitpos: [6]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON    (BIT(6))
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_S  6
+/** HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON : R/W; bitpos: [7]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON    (BIT(7))
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_S  7
+/** HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON    (BIT(8))
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_S  8
+/** HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON : R/W; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON    (BIT(9))
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON_S  9
+/** HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON : R/W; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON    (BIT(10))
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON_S  10
+/** HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON : R/W; bitpos: [11]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON    (BIT(11))
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_S  11
+/** HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON : R/W; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON    (BIT(12))
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_S  12
+/** HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON : R/W; bitpos: [13]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON    (BIT(13))
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON_S  13
+/** HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON : R/W; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON    (BIT(14))
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON_S  14
+/** HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON : R/W; bitpos: [15]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON    (BIT(15))
+#define HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON_S  15
+/** HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON : R/W; bitpos: [16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON    (BIT(16))
+#define HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON_S  16
+/** HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON : R/W; bitpos: [17]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON    (BIT(17))
+#define HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON_S  17
+/** HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON : R/W; bitpos: [18]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON    (BIT(18))
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON_S  18
+
+/** HP_SYS_CLKRST_DPA_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_DPA_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xb8)
+/** HP_SYS_CLKRST_REG_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_M  (HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_V << HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_S)
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_S  0
+/** HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL    (BIT(2))
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_M  (HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_V << HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_S)
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_S  2
+
+/** HP_SYS_CLKRST_ANA_PLL_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_ANA_PLL_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xbc)
+/** HP_SYS_CLKRST_REG_PLLA_CAL_END : RO; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END    (BIT(0))
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END_M  (HP_SYS_CLKRST_REG_PLLA_CAL_END_V << HP_SYS_CLKRST_REG_PLLA_CAL_END_S)
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END_S  0
+/** HP_SYS_CLKRST_REG_PLLA_CAL_STOP : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP    (BIT(1))
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP_M  (HP_SYS_CLKRST_REG_PLLA_CAL_STOP_V << HP_SYS_CLKRST_REG_PLLA_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP_S  1
+/** HP_SYS_CLKRST_REG_CPU_PLL_CAL_END : RO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END    (BIT(2))
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_M  (HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_V << HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_S  2
+/** HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP    (BIT(3))
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M  (HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_V << HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_S  3
+/** HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END : RO; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END    (BIT(4))
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_M  (HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_V << HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_S  4
+/** HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP    (BIT(5))
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_M  (HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_V << HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_S  5
+/** HP_SYS_CLKRST_REG_SYS_PLL_CAL_END : RO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_END    (BIT(6))
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_END_M  (HP_SYS_CLKRST_REG_SYS_PLL_CAL_END_V << HP_SYS_CLKRST_REG_SYS_PLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_END_S  6
+/** HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP    (BIT(7))
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_M  (HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_V << HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_S  7
+/** HP_SYS_CLKRST_REG_MSPI_CAL_END : RO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END    (BIT(8))
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END_M  (HP_SYS_CLKRST_REG_MSPI_CAL_END_V << HP_SYS_CLKRST_REG_MSPI_CAL_END_S)
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END_S  8
+/** HP_SYS_CLKRST_REG_MSPI_CAL_STOP : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP    (BIT(9))
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP_M  (HP_SYS_CLKRST_REG_MSPI_CAL_STOP_V << HP_SYS_CLKRST_REG_MSPI_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP_S  9
+
+/** HP_SYS_CLKRST_HP_RST_EN0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HP_RST_EN0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc0)
+/** HP_SYS_CLKRST_REG_RST_EN_CORECTRL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CORECTRL    (BIT(0))
+#define HP_SYS_CLKRST_REG_RST_EN_CORECTRL_M  (HP_SYS_CLKRST_REG_RST_EN_CORECTRL_V << HP_SYS_CLKRST_REG_RST_EN_CORECTRL_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CORECTRL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CORECTRL_S  0
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_TOP : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_TOP    (BIT(1))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_TOP_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_TOP_V << HP_SYS_CLKRST_REG_RST_EN_PVT_TOP_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_TOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_TOP_S  1
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1 : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1    (BIT(2))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1_V << HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1_S  2
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2 : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2    (BIT(3))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2_V << HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2_S  3
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3 : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3    (BIT(4))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3_V << HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3_S  4
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4 : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4    (BIT(5))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_V << HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_S  5
+/** HP_SYS_CLKRST_REG_RST_EN_REGDMA : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_REGDMA    (BIT(6))
+#define HP_SYS_CLKRST_REG_RST_EN_REGDMA_M  (HP_SYS_CLKRST_REG_RST_EN_REGDMA_V << HP_SYS_CLKRST_REG_RST_EN_REGDMA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_REGDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_REGDMA_S  6
+/** HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL    (BIT(7))
+#define HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL_M  (HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL_V << HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL_S  7
+/** HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL    (BIT(8))
+#define HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL_M  (HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL_V << HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL_S  8
+/** HP_SYS_CLKRST_REG_RST_EN_CORETRACE0 : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE0    (BIT(9))
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE0_M  (HP_SYS_CLKRST_REG_RST_EN_CORETRACE0_V << HP_SYS_CLKRST_REG_RST_EN_CORETRACE0_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE0_S  9
+/** HP_SYS_CLKRST_REG_RST_EN_CORETRACE1 : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE1    (BIT(10))
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE1_M  (HP_SYS_CLKRST_REG_RST_EN_CORETRACE1_V << HP_SYS_CLKRST_REG_RST_EN_CORETRACE1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE1_S  10
+/** HP_SYS_CLKRST_REG_RST_EN_HP_TCM : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_HP_TCM    (BIT(11))
+#define HP_SYS_CLKRST_REG_RST_EN_HP_TCM_M  (HP_SYS_CLKRST_REG_RST_EN_HP_TCM_V << HP_SYS_CLKRST_REG_RST_EN_HP_TCM_S)
+#define HP_SYS_CLKRST_REG_RST_EN_HP_TCM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_HP_TCM_S  11
+/** HP_SYS_CLKRST_REG_RST_EN_HP_CACHE : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_HP_CACHE    (BIT(12))
+#define HP_SYS_CLKRST_REG_RST_EN_HP_CACHE_M  (HP_SYS_CLKRST_REG_RST_EN_HP_CACHE_V << HP_SYS_CLKRST_REG_RST_EN_HP_CACHE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_HP_CACHE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_HP_CACHE_S  12
+/** HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE    (BIT(13))
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE_M  (HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE_V << HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE_S  13
+/** HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE    (BIT(14))
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE_M  (HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE_V << HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE_S  14
+/** HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE    (BIT(15))
+#define HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE_M  (HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE_V << HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE_S  15
+/** HP_SYS_CLKRST_REG_RST_EN_L2_CACHE : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L2_CACHE    (BIT(16))
+#define HP_SYS_CLKRST_REG_RST_EN_L2_CACHE_M  (HP_SYS_CLKRST_REG_RST_EN_L2_CACHE_V << HP_SYS_CLKRST_REG_RST_EN_L2_CACHE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L2_CACHE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L2_CACHE_S  16
+/** HP_SYS_CLKRST_REG_RST_EN_L2_MEM : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L2_MEM    (BIT(17))
+#define HP_SYS_CLKRST_REG_RST_EN_L2_MEM_M  (HP_SYS_CLKRST_REG_RST_EN_L2_MEM_V << HP_SYS_CLKRST_REG_RST_EN_L2_MEM_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L2_MEM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L2_MEM_S  17
+/** HP_SYS_CLKRST_REG_RST_EN_L2MEMMON : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L2MEMMON    (BIT(18))
+#define HP_SYS_CLKRST_REG_RST_EN_L2MEMMON_M  (HP_SYS_CLKRST_REG_RST_EN_L2MEMMON_V << HP_SYS_CLKRST_REG_RST_EN_L2MEMMON_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L2MEMMON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L2MEMMON_S  18
+/** HP_SYS_CLKRST_REG_RST_EN_TCMMON : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_TCMMON    (BIT(19))
+#define HP_SYS_CLKRST_REG_RST_EN_TCMMON_M  (HP_SYS_CLKRST_REG_RST_EN_TCMMON_V << HP_SYS_CLKRST_REG_RST_EN_TCMMON_S)
+#define HP_SYS_CLKRST_REG_RST_EN_TCMMON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_TCMMON_S  19
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_APB : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_APB    (BIT(20))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_APB_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_APB_V << HP_SYS_CLKRST_REG_RST_EN_PVT_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_APB_S  20
+/** HP_SYS_CLKRST_REG_RST_EN_GDMA : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_GDMA    (BIT(21))
+#define HP_SYS_CLKRST_REG_RST_EN_GDMA_M  (HP_SYS_CLKRST_REG_RST_EN_GDMA_V << HP_SYS_CLKRST_REG_RST_EN_GDMA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_GDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_GDMA_S  21
+/** HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI    (BIT(22))
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI_M  (HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI_V << HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI_S)
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI_S  22
+/** HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI    (BIT(23))
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI_M  (HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI_V << HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI_S)
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI_S  23
+/** HP_SYS_CLKRST_REG_RST_EN_MSPI_APB : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB    (BIT(24))
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB_M  (HP_SYS_CLKRST_REG_RST_EN_MSPI_APB_V << HP_SYS_CLKRST_REG_RST_EN_MSPI_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB_S  24
+/** HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB    (BIT(25))
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB_M  (HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB_V << HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB_S  25
+/** HP_SYS_CLKRST_REG_RST_EN_DSI_BRG : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_DSI_BRG    (BIT(26))
+#define HP_SYS_CLKRST_REG_RST_EN_DSI_BRG_M  (HP_SYS_CLKRST_REG_RST_EN_DSI_BRG_V << HP_SYS_CLKRST_REG_RST_EN_DSI_BRG_S)
+#define HP_SYS_CLKRST_REG_RST_EN_DSI_BRG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_DSI_BRG_S  26
+/** HP_SYS_CLKRST_REG_RST_EN_CSI_HOST : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_HOST    (BIT(27))
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_HOST_M  (HP_SYS_CLKRST_REG_RST_EN_CSI_HOST_V << HP_SYS_CLKRST_REG_RST_EN_CSI_HOST_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_HOST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_HOST_S  27
+/** HP_SYS_CLKRST_REG_RST_EN_CSI_BRG : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_BRG    (BIT(28))
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_BRG_M  (HP_SYS_CLKRST_REG_RST_EN_CSI_BRG_V << HP_SYS_CLKRST_REG_RST_EN_CSI_BRG_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_BRG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_BRG_S  28
+/** HP_SYS_CLKRST_REG_RST_EN_ISP : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_ISP    (BIT(29))
+#define HP_SYS_CLKRST_REG_RST_EN_ISP_M  (HP_SYS_CLKRST_REG_RST_EN_ISP_V << HP_SYS_CLKRST_REG_RST_EN_ISP_S)
+#define HP_SYS_CLKRST_REG_RST_EN_ISP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_ISP_S  29
+/** HP_SYS_CLKRST_REG_RST_EN_JPEG : R/W; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_JPEG    (BIT(30))
+#define HP_SYS_CLKRST_REG_RST_EN_JPEG_M  (HP_SYS_CLKRST_REG_RST_EN_JPEG_V << HP_SYS_CLKRST_REG_RST_EN_JPEG_S)
+#define HP_SYS_CLKRST_REG_RST_EN_JPEG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_JPEG_S  30
+/** HP_SYS_CLKRST_REG_RST_EN_DMA2D : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_DMA2D    (BIT(31))
+#define HP_SYS_CLKRST_REG_RST_EN_DMA2D_M  (HP_SYS_CLKRST_REG_RST_EN_DMA2D_V << HP_SYS_CLKRST_REG_RST_EN_DMA2D_S)
+#define HP_SYS_CLKRST_REG_RST_EN_DMA2D_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_DMA2D_S  31
+
+/** HP_SYS_CLKRST_HP_RST_EN1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HP_RST_EN1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc4)
+/** HP_SYS_CLKRST_REG_RST_EN_PPA : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PPA    (BIT(0))
+#define HP_SYS_CLKRST_REG_RST_EN_PPA_M  (HP_SYS_CLKRST_REG_RST_EN_PPA_V << HP_SYS_CLKRST_REG_RST_EN_PPA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PPA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PPA_S  0
+/** HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA    (BIT(1))
+#define HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA_M  (HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA_V << HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA_S  1
+/** HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA    (BIT(2))
+#define HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA_M  (HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA_V << HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA_S  2
+/** HP_SYS_CLKRST_REG_RST_EN_IOMUX : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_IOMUX    (BIT(3))
+#define HP_SYS_CLKRST_REG_RST_EN_IOMUX_M  (HP_SYS_CLKRST_REG_RST_EN_IOMUX_V << HP_SYS_CLKRST_REG_RST_EN_IOMUX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_IOMUX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_IOMUX_S  3
+/** HP_SYS_CLKRST_REG_RST_EN_PADBIST : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PADBIST    (BIT(4))
+#define HP_SYS_CLKRST_REG_RST_EN_PADBIST_M  (HP_SYS_CLKRST_REG_RST_EN_PADBIST_V << HP_SYS_CLKRST_REG_RST_EN_PADBIST_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PADBIST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PADBIST_S  4
+/** HP_SYS_CLKRST_REG_RST_EN_STIMER : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_STIMER    (BIT(5))
+#define HP_SYS_CLKRST_REG_RST_EN_STIMER_M  (HP_SYS_CLKRST_REG_RST_EN_STIMER_V << HP_SYS_CLKRST_REG_RST_EN_STIMER_S)
+#define HP_SYS_CLKRST_REG_RST_EN_STIMER_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_STIMER_S  5
+/** HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0 : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0    (BIT(6))
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0_M  (HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0_V << HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0_S)
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0_S  6
+/** HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1 : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1    (BIT(7))
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1_M  (HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1_V << HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1_S  7
+/** HP_SYS_CLKRST_REG_RST_EN_UART0_CORE : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_CORE    (BIT(8))
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_CORE_M  (HP_SYS_CLKRST_REG_RST_EN_UART0_CORE_V << HP_SYS_CLKRST_REG_RST_EN_UART0_CORE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_CORE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_CORE_S  8
+/** HP_SYS_CLKRST_REG_RST_EN_UART1_CORE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_CORE    (BIT(9))
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_CORE_M  (HP_SYS_CLKRST_REG_RST_EN_UART1_CORE_V << HP_SYS_CLKRST_REG_RST_EN_UART1_CORE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_CORE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_CORE_S  9
+/** HP_SYS_CLKRST_REG_RST_EN_UART2_CORE : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_CORE    (BIT(10))
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_CORE_M  (HP_SYS_CLKRST_REG_RST_EN_UART2_CORE_V << HP_SYS_CLKRST_REG_RST_EN_UART2_CORE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_CORE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_CORE_S  10
+/** HP_SYS_CLKRST_REG_RST_EN_UART3_CORE : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_CORE    (BIT(11))
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_CORE_M  (HP_SYS_CLKRST_REG_RST_EN_UART3_CORE_V << HP_SYS_CLKRST_REG_RST_EN_UART3_CORE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_CORE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_CORE_S  11
+/** HP_SYS_CLKRST_REG_RST_EN_UART4_CORE : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_CORE    (BIT(12))
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_CORE_M  (HP_SYS_CLKRST_REG_RST_EN_UART4_CORE_V << HP_SYS_CLKRST_REG_RST_EN_UART4_CORE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_CORE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_CORE_S  12
+/** HP_SYS_CLKRST_REG_RST_EN_UART0_APB : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_APB    (BIT(13))
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_APB_M  (HP_SYS_CLKRST_REG_RST_EN_UART0_APB_V << HP_SYS_CLKRST_REG_RST_EN_UART0_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_APB_S  13
+/** HP_SYS_CLKRST_REG_RST_EN_UART1_APB : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_APB    (BIT(14))
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_APB_M  (HP_SYS_CLKRST_REG_RST_EN_UART1_APB_V << HP_SYS_CLKRST_REG_RST_EN_UART1_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_APB_S  14
+/** HP_SYS_CLKRST_REG_RST_EN_UART2_APB : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_APB    (BIT(15))
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_APB_M  (HP_SYS_CLKRST_REG_RST_EN_UART2_APB_V << HP_SYS_CLKRST_REG_RST_EN_UART2_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_APB_S  15
+/** HP_SYS_CLKRST_REG_RST_EN_UART3_APB : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_APB    (BIT(16))
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_APB_M  (HP_SYS_CLKRST_REG_RST_EN_UART3_APB_V << HP_SYS_CLKRST_REG_RST_EN_UART3_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_APB_S  16
+/** HP_SYS_CLKRST_REG_RST_EN_UART4_APB : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_APB    (BIT(17))
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_APB_M  (HP_SYS_CLKRST_REG_RST_EN_UART4_APB_V << HP_SYS_CLKRST_REG_RST_EN_UART4_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_APB_S  17
+/** HP_SYS_CLKRST_REG_RST_EN_UHCI : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UHCI    (BIT(18))
+#define HP_SYS_CLKRST_REG_RST_EN_UHCI_M  (HP_SYS_CLKRST_REG_RST_EN_UHCI_V << HP_SYS_CLKRST_REG_RST_EN_UHCI_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UHCI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UHCI_S  18
+/** HP_SYS_CLKRST_REG_RST_EN_I3CMST : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I3CMST    (BIT(19))
+#define HP_SYS_CLKRST_REG_RST_EN_I3CMST_M  (HP_SYS_CLKRST_REG_RST_EN_I3CMST_V << HP_SYS_CLKRST_REG_RST_EN_I3CMST_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I3CMST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I3CMST_S  19
+/** HP_SYS_CLKRST_REG_RST_EN_I3CSLV : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I3CSLV    (BIT(20))
+#define HP_SYS_CLKRST_REG_RST_EN_I3CSLV_M  (HP_SYS_CLKRST_REG_RST_EN_I3CSLV_V << HP_SYS_CLKRST_REG_RST_EN_I3CSLV_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I3CSLV_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I3CSLV_S  20
+/** HP_SYS_CLKRST_REG_RST_EN_I2C1 : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I2C1    (BIT(21))
+#define HP_SYS_CLKRST_REG_RST_EN_I2C1_M  (HP_SYS_CLKRST_REG_RST_EN_I2C1_V << HP_SYS_CLKRST_REG_RST_EN_I2C1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I2C1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I2C1_S  21
+/** HP_SYS_CLKRST_REG_RST_EN_I2C0 : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I2C0    (BIT(22))
+#define HP_SYS_CLKRST_REG_RST_EN_I2C0_M  (HP_SYS_CLKRST_REG_RST_EN_I2C0_V << HP_SYS_CLKRST_REG_RST_EN_I2C0_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I2C0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I2C0_S  22
+/** HP_SYS_CLKRST_REG_RST_EN_RMT : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_RMT    (BIT(23))
+#define HP_SYS_CLKRST_REG_RST_EN_RMT_M  (HP_SYS_CLKRST_REG_RST_EN_RMT_V << HP_SYS_CLKRST_REG_RST_EN_RMT_S)
+#define HP_SYS_CLKRST_REG_RST_EN_RMT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_RMT_S  23
+/** HP_SYS_CLKRST_REG_RST_EN_PWM0 : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PWM0    (BIT(24))
+#define HP_SYS_CLKRST_REG_RST_EN_PWM0_M  (HP_SYS_CLKRST_REG_RST_EN_PWM0_V << HP_SYS_CLKRST_REG_RST_EN_PWM0_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PWM0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PWM0_S  24
+/** HP_SYS_CLKRST_REG_RST_EN_PWM1 : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PWM1    (BIT(25))
+#define HP_SYS_CLKRST_REG_RST_EN_PWM1_M  (HP_SYS_CLKRST_REG_RST_EN_PWM1_V << HP_SYS_CLKRST_REG_RST_EN_PWM1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PWM1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PWM1_S  25
+/** HP_SYS_CLKRST_REG_RST_EN_CAN0 : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CAN0    (BIT(26))
+#define HP_SYS_CLKRST_REG_RST_EN_CAN0_M  (HP_SYS_CLKRST_REG_RST_EN_CAN0_V << HP_SYS_CLKRST_REG_RST_EN_CAN0_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CAN0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CAN0_S  26
+/** HP_SYS_CLKRST_REG_RST_EN_CAN1 : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CAN1    (BIT(27))
+#define HP_SYS_CLKRST_REG_RST_EN_CAN1_M  (HP_SYS_CLKRST_REG_RST_EN_CAN1_V << HP_SYS_CLKRST_REG_RST_EN_CAN1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CAN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CAN1_S  27
+/** HP_SYS_CLKRST_REG_RST_EN_CAN2 : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CAN2    (BIT(28))
+#define HP_SYS_CLKRST_REG_RST_EN_CAN2_M  (HP_SYS_CLKRST_REG_RST_EN_CAN2_V << HP_SYS_CLKRST_REG_RST_EN_CAN2_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CAN2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CAN2_S  28
+/** HP_SYS_CLKRST_REG_RST_EN_LEDC : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_LEDC    (BIT(29))
+#define HP_SYS_CLKRST_REG_RST_EN_LEDC_M  (HP_SYS_CLKRST_REG_RST_EN_LEDC_V << HP_SYS_CLKRST_REG_RST_EN_LEDC_S)
+#define HP_SYS_CLKRST_REG_RST_EN_LEDC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_LEDC_S  29
+/** HP_SYS_CLKRST_REG_RST_EN_PCNT : R/W; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PCNT    (BIT(30))
+#define HP_SYS_CLKRST_REG_RST_EN_PCNT_M  (HP_SYS_CLKRST_REG_RST_EN_PCNT_V << HP_SYS_CLKRST_REG_RST_EN_PCNT_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PCNT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PCNT_S  30
+/** HP_SYS_CLKRST_REG_RST_EN_ETM : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_ETM    (BIT(31))
+#define HP_SYS_CLKRST_REG_RST_EN_ETM_M  (HP_SYS_CLKRST_REG_RST_EN_ETM_V << HP_SYS_CLKRST_REG_RST_EN_ETM_S)
+#define HP_SYS_CLKRST_REG_RST_EN_ETM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_ETM_S  31
+
+/** HP_SYS_CLKRST_HP_RST_EN2_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HP_RST_EN2_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc8)
+/** HP_SYS_CLKRST_REG_RST_EN_INTRMTX : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_INTRMTX    (BIT(0))
+#define HP_SYS_CLKRST_REG_RST_EN_INTRMTX_M  (HP_SYS_CLKRST_REG_RST_EN_INTRMTX_V << HP_SYS_CLKRST_REG_RST_EN_INTRMTX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_INTRMTX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_INTRMTX_S  0
+/** HP_SYS_CLKRST_REG_RST_EN_PARLIO : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO    (BIT(1))
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_M  (HP_SYS_CLKRST_REG_RST_EN_PARLIO_V << HP_SYS_CLKRST_REG_RST_EN_PARLIO_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_S  1
+/** HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX    (BIT(2))
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX_M  (HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX_V << HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX_S  2
+/** HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX    (BIT(3))
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX_M  (HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX_V << HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX_S  3
+/** HP_SYS_CLKRST_REG_RST_EN_I2S0_APB : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I2S0_APB    (BIT(4))
+#define HP_SYS_CLKRST_REG_RST_EN_I2S0_APB_M  (HP_SYS_CLKRST_REG_RST_EN_I2S0_APB_V << HP_SYS_CLKRST_REG_RST_EN_I2S0_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I2S0_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I2S0_APB_S  4
+/** HP_SYS_CLKRST_REG_RST_EN_I2S1_APB : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I2S1_APB    (BIT(5))
+#define HP_SYS_CLKRST_REG_RST_EN_I2S1_APB_M  (HP_SYS_CLKRST_REG_RST_EN_I2S1_APB_V << HP_SYS_CLKRST_REG_RST_EN_I2S1_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I2S1_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I2S1_APB_S  5
+/** HP_SYS_CLKRST_REG_RST_EN_I2S2_APB : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I2S2_APB    (BIT(6))
+#define HP_SYS_CLKRST_REG_RST_EN_I2S2_APB_M  (HP_SYS_CLKRST_REG_RST_EN_I2S2_APB_V << HP_SYS_CLKRST_REG_RST_EN_I2S2_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I2S2_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I2S2_APB_S  6
+/** HP_SYS_CLKRST_REG_RST_EN_SPI2 : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_SPI2    (BIT(7))
+#define HP_SYS_CLKRST_REG_RST_EN_SPI2_M  (HP_SYS_CLKRST_REG_RST_EN_SPI2_V << HP_SYS_CLKRST_REG_RST_EN_SPI2_S)
+#define HP_SYS_CLKRST_REG_RST_EN_SPI2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_SPI2_S  7
+/** HP_SYS_CLKRST_REG_RST_EN_SPI3 : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_SPI3    (BIT(8))
+#define HP_SYS_CLKRST_REG_RST_EN_SPI3_M  (HP_SYS_CLKRST_REG_RST_EN_SPI3_V << HP_SYS_CLKRST_REG_RST_EN_SPI3_S)
+#define HP_SYS_CLKRST_REG_RST_EN_SPI3_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_SPI3_S  8
+/** HP_SYS_CLKRST_REG_RST_EN_LCDCAM : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_LCDCAM    (BIT(9))
+#define HP_SYS_CLKRST_REG_RST_EN_LCDCAM_M  (HP_SYS_CLKRST_REG_RST_EN_LCDCAM_V << HP_SYS_CLKRST_REG_RST_EN_LCDCAM_S)
+#define HP_SYS_CLKRST_REG_RST_EN_LCDCAM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_LCDCAM_S  9
+/** HP_SYS_CLKRST_REG_RST_EN_ADC : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_ADC    (BIT(10))
+#define HP_SYS_CLKRST_REG_RST_EN_ADC_M  (HP_SYS_CLKRST_REG_RST_EN_ADC_V << HP_SYS_CLKRST_REG_RST_EN_ADC_S)
+#define HP_SYS_CLKRST_REG_RST_EN_ADC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_ADC_S  10
+/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER    (BIT(11))
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_M  (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_S)
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_S  11
+/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX    (BIT(12))
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_M  (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_S  12
+/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX    (BIT(13))
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_M  (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_S  13
+/** HP_SYS_CLKRST_REG_RST_EN_CRYPTO : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CRYPTO    (BIT(14))
+#define HP_SYS_CLKRST_REG_RST_EN_CRYPTO_M  (HP_SYS_CLKRST_REG_RST_EN_CRYPTO_V << HP_SYS_CLKRST_REG_RST_EN_CRYPTO_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CRYPTO_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CRYPTO_S  14
+/** HP_SYS_CLKRST_REG_RST_EN_SEC : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_SEC    (BIT(15))
+#define HP_SYS_CLKRST_REG_RST_EN_SEC_M  (HP_SYS_CLKRST_REG_RST_EN_SEC_V << HP_SYS_CLKRST_REG_RST_EN_SEC_S)
+#define HP_SYS_CLKRST_REG_RST_EN_SEC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_SEC_S  15
+/** HP_SYS_CLKRST_REG_RST_EN_AES : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_AES    (BIT(16))
+#define HP_SYS_CLKRST_REG_RST_EN_AES_M  (HP_SYS_CLKRST_REG_RST_EN_AES_V << HP_SYS_CLKRST_REG_RST_EN_AES_S)
+#define HP_SYS_CLKRST_REG_RST_EN_AES_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_AES_S  16
+/** HP_SYS_CLKRST_REG_RST_EN_DS : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_DS    (BIT(17))
+#define HP_SYS_CLKRST_REG_RST_EN_DS_M  (HP_SYS_CLKRST_REG_RST_EN_DS_V << HP_SYS_CLKRST_REG_RST_EN_DS_S)
+#define HP_SYS_CLKRST_REG_RST_EN_DS_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_DS_S  17
+/** HP_SYS_CLKRST_REG_RST_EN_SHA : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_SHA    (BIT(18))
+#define HP_SYS_CLKRST_REG_RST_EN_SHA_M  (HP_SYS_CLKRST_REG_RST_EN_SHA_V << HP_SYS_CLKRST_REG_RST_EN_SHA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_SHA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_SHA_S  18
+/** HP_SYS_CLKRST_REG_RST_EN_HMAC : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_HMAC    (BIT(19))
+#define HP_SYS_CLKRST_REG_RST_EN_HMAC_M  (HP_SYS_CLKRST_REG_RST_EN_HMAC_V << HP_SYS_CLKRST_REG_RST_EN_HMAC_S)
+#define HP_SYS_CLKRST_REG_RST_EN_HMAC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_HMAC_S  19
+/** HP_SYS_CLKRST_REG_RST_EN_ECDSA : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_ECDSA    (BIT(20))
+#define HP_SYS_CLKRST_REG_RST_EN_ECDSA_M  (HP_SYS_CLKRST_REG_RST_EN_ECDSA_V << HP_SYS_CLKRST_REG_RST_EN_ECDSA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_ECDSA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_ECDSA_S  20
+/** HP_SYS_CLKRST_REG_RST_EN_RSA : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_RSA    (BIT(21))
+#define HP_SYS_CLKRST_REG_RST_EN_RSA_M  (HP_SYS_CLKRST_REG_RST_EN_RSA_V << HP_SYS_CLKRST_REG_RST_EN_RSA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_RSA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_RSA_S  21
+/** HP_SYS_CLKRST_REG_RST_EN_ECC : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_ECC    (BIT(22))
+#define HP_SYS_CLKRST_REG_RST_EN_ECC_M  (HP_SYS_CLKRST_REG_RST_EN_ECC_V << HP_SYS_CLKRST_REG_RST_EN_ECC_S)
+#define HP_SYS_CLKRST_REG_RST_EN_ECC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_ECC_S  22
+/** HP_SYS_CLKRST_REG_RST_EN_KM : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_KM    (BIT(23))
+#define HP_SYS_CLKRST_REG_RST_EN_KM_M  (HP_SYS_CLKRST_REG_RST_EN_KM_V << HP_SYS_CLKRST_REG_RST_EN_KM_S)
+#define HP_SYS_CLKRST_REG_RST_EN_KM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_KM_S  23
+/** HP_SYS_CLKRST_REG_RST_EN_H264 : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_H264    (BIT(24))
+#define HP_SYS_CLKRST_REG_RST_EN_H264_M  (HP_SYS_CLKRST_REG_RST_EN_H264_V << HP_SYS_CLKRST_REG_RST_EN_H264_S)
+#define HP_SYS_CLKRST_REG_RST_EN_H264_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_H264_S  24
+
+/** HP_SYS_CLKRST_HP_FORCE_NORST0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HP_FORCE_NORST0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xcc)
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CORE0 : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE0    (BIT(0))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CORE0_V << HP_SYS_CLKRST_REG_FORCE_NORST_CORE0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE0_S  0
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CORE1 : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE1    (BIT(1))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CORE1_V << HP_SYS_CLKRST_REG_FORCE_NORST_CORE1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE1_S  1
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0 : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0    (BIT(2))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0_V << HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0_S  2
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1 : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1    (BIT(3))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1_V << HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1_S  3
+/** HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON    (BIT(4))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON_M  (HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON_V << HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON_S  4
+/** HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON    (BIT(5))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON_M  (HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON_V << HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON_S  5
+/** HP_SYS_CLKRST_REG_FORCE_NORST_GDMA : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_GDMA    (BIT(6))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_GDMA_M  (HP_SYS_CLKRST_REG_FORCE_NORST_GDMA_V << HP_SYS_CLKRST_REG_FORCE_NORST_GDMA_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_GDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_GDMA_S  6
+/** HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI    (BIT(7))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI_M  (HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI_V << HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI_S  7
+/** HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI    (BIT(8))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI_M  (HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI_V << HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI_S  8
+/** HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB    (BIT(9))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB_M  (HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB_V << HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB_S  9
+/** HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB    (BIT(10))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB_M  (HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB_V << HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB_S  10
+/** HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG    (BIT(11))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG_M  (HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG_V << HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG_S  11
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST    (BIT(12))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST_V << HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST_S  12
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG    (BIT(13))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG_V << HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG_S  13
+/** HP_SYS_CLKRST_REG_FORCE_NORST_ISP : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ISP    (BIT(14))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ISP_M  (HP_SYS_CLKRST_REG_FORCE_NORST_ISP_V << HP_SYS_CLKRST_REG_FORCE_NORST_ISP_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ISP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ISP_S  14
+/** HP_SYS_CLKRST_REG_FORCE_NORST_JPEG : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_JPEG    (BIT(15))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_JPEG_M  (HP_SYS_CLKRST_REG_FORCE_NORST_JPEG_V << HP_SYS_CLKRST_REG_FORCE_NORST_JPEG_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_JPEG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_JPEG_S  15
+/** HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D    (BIT(16))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D_M  (HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D_V << HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D_S  16
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PPA : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PPA    (BIT(17))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PPA_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PPA_V << HP_SYS_CLKRST_REG_FORCE_NORST_PPA_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PPA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PPA_S  17
+/** HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA    (BIT(18))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA_M  (HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA_V << HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA_S  18
+/** HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA    (BIT(19))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA_M  (HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA_V << HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA_S  19
+/** HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX    (BIT(20))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX_V << HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX_S  20
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST    (BIT(21))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST_V << HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST_S  21
+/** HP_SYS_CLKRST_REG_FORCE_NORST_STIMER : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_STIMER    (BIT(22))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_STIMER_M  (HP_SYS_CLKRST_REG_FORCE_NORST_STIMER_V << HP_SYS_CLKRST_REG_FORCE_NORST_STIMER_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_STIMER_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_STIMER_S  22
+/** HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0 : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0    (BIT(23))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0_V << HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0_S  23
+/** HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1 : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1    (BIT(24))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1_V << HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1_S  24
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UART0 : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART0    (BIT(25))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UART0_V << HP_SYS_CLKRST_REG_FORCE_NORST_UART0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART0_S  25
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UART1 : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART1    (BIT(26))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UART1_V << HP_SYS_CLKRST_REG_FORCE_NORST_UART1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART1_S  26
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UART2 : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART2    (BIT(27))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART2_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UART2_V << HP_SYS_CLKRST_REG_FORCE_NORST_UART2_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART2_S  27
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UART3 : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART3    (BIT(28))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART3_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UART3_V << HP_SYS_CLKRST_REG_FORCE_NORST_UART3_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART3_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART3_S  28
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UART4 : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART4    (BIT(29))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART4_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UART4_V << HP_SYS_CLKRST_REG_FORCE_NORST_UART4_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART4_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART4_S  29
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UHCI : R/W; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UHCI    (BIT(30))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UHCI_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UHCI_V << HP_SYS_CLKRST_REG_FORCE_NORST_UHCI_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UHCI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UHCI_S  30
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST    (BIT(31))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST_V << HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST_S  31
+
+/** HP_SYS_CLKRST_HP_FORCE_NORST1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HP_FORCE_NORST1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xd0)
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV    (BIT(0))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV_V << HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV_S  0
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I2C1 : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C1    (BIT(1))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I2C1_V << HP_SYS_CLKRST_REG_FORCE_NORST_I2C1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C1_S  1
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I2C0 : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C0    (BIT(2))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I2C0_V << HP_SYS_CLKRST_REG_FORCE_NORST_I2C0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C0_S  2
+/** HP_SYS_CLKRST_REG_FORCE_NORST_RMT : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_RMT    (BIT(3))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_RMT_M  (HP_SYS_CLKRST_REG_FORCE_NORST_RMT_V << HP_SYS_CLKRST_REG_FORCE_NORST_RMT_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_RMT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_RMT_S  3
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PWM0 : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM0    (BIT(4))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PWM0_V << HP_SYS_CLKRST_REG_FORCE_NORST_PWM0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM0_S  4
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PWM1 : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM1    (BIT(5))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PWM1_V << HP_SYS_CLKRST_REG_FORCE_NORST_PWM1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM1_S  5
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CAN0 : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN0    (BIT(6))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CAN0_V << HP_SYS_CLKRST_REG_FORCE_NORST_CAN0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN0_S  6
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CAN1 : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN1    (BIT(7))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CAN1_V << HP_SYS_CLKRST_REG_FORCE_NORST_CAN1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN1_S  7
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CAN2 : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN2    (BIT(8))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN2_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CAN2_V << HP_SYS_CLKRST_REG_FORCE_NORST_CAN2_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN2_S  8
+/** HP_SYS_CLKRST_REG_FORCE_NORST_LEDC : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LEDC    (BIT(9))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LEDC_M  (HP_SYS_CLKRST_REG_FORCE_NORST_LEDC_V << HP_SYS_CLKRST_REG_FORCE_NORST_LEDC_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LEDC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LEDC_S  9
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PCNT : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PCNT    (BIT(10))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PCNT_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PCNT_V << HP_SYS_CLKRST_REG_FORCE_NORST_PCNT_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PCNT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PCNT_S  10
+/** HP_SYS_CLKRST_REG_FORCE_NORST_ETM : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ETM    (BIT(11))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ETM_M  (HP_SYS_CLKRST_REG_FORCE_NORST_ETM_V << HP_SYS_CLKRST_REG_FORCE_NORST_ETM_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ETM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ETM_S  11
+/** HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX    (BIT(12))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX_V << HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX_S  12
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO    (BIT(13))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_V << HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_S  13
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX    (BIT(14))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX_V << HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX_S  14
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX    (BIT(15))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX_V << HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX_S  15
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I2S0 : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S0    (BIT(16))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I2S0_V << HP_SYS_CLKRST_REG_FORCE_NORST_I2S0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S0_S  16
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I2S1 : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S1    (BIT(17))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I2S1_V << HP_SYS_CLKRST_REG_FORCE_NORST_I2S1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S1_S  17
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I2S2 : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S2    (BIT(18))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S2_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I2S2_V << HP_SYS_CLKRST_REG_FORCE_NORST_I2S2_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S2_S  18
+/** HP_SYS_CLKRST_REG_FORCE_NORST_SPI2 : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI2    (BIT(19))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI2_M  (HP_SYS_CLKRST_REG_FORCE_NORST_SPI2_V << HP_SYS_CLKRST_REG_FORCE_NORST_SPI2_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI2_S  19
+/** HP_SYS_CLKRST_REG_FORCE_NORST_SPI3 : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI3    (BIT(20))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI3_M  (HP_SYS_CLKRST_REG_FORCE_NORST_SPI3_V << HP_SYS_CLKRST_REG_FORCE_NORST_SPI3_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI3_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI3_S  20
+/** HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM    (BIT(21))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM_M  (HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM_V << HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM_S  21
+/** HP_SYS_CLKRST_REG_FORCE_NORST_ADC : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC    (BIT(22))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_M  (HP_SYS_CLKRST_REG_FORCE_NORST_ADC_V << HP_SYS_CLKRST_REG_FORCE_NORST_ADC_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_S  22
+/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER    (BIT(23))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_M  (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_S  23
+/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX    (BIT(24))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_S  24
+/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX    (BIT(25))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_S  25
+/** HP_SYS_CLKRST_REG_FORCE_NORST_H264 : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_H264    (BIT(26))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_H264_M  (HP_SYS_CLKRST_REG_FORCE_NORST_H264_V << HP_SYS_CLKRST_REG_FORCE_NORST_H264_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_H264_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_H264_S  26
+
+/** HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xd4)
+/** HP_SYS_CLKRST_REG_HPCORE0_STALL_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_M  (HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_V << HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_S)
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_S  0
+/** HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM : R/W; bitpos: [8:1]; default: 8;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_M  (HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_V << HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_S)
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_S  1
+/** HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN : R/W; bitpos: [16:9]; default: 8;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN    0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_M  (HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_V << HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_S)
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_S  9
+
+/** HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xd8)
+/** HP_SYS_CLKRST_REG_HPCORE1_STALL_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_M  (HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_V << HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_S)
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_S  0
+/** HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM : R/W; bitpos: [8:1]; default: 8;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_M  (HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_V << HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_S)
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_S  1
+/** HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN : R/W; bitpos: [16:9]; default: 8;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN    0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_M  (HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_V << HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_S)
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_S  9
+
+/** HP_SYS_CLKRST_CPU_SRC_FREQ0_REG register
+ *  CPU Source Frequency
+ */
+#define HP_SYS_CLKRST_CPU_SRC_FREQ0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xdc)
+/** HP_SYS_CLKRST_REG_CPU_SRC_FREQ : RO; bitpos: [31:0]; default: 0;
+ *  cpu source clock frequency, step by 0.25MHz
+ */
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ    0xFFFFFFFFU
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ_M  (HP_SYS_CLKRST_REG_CPU_SRC_FREQ_V << HP_SYS_CLKRST_REG_CPU_SRC_FREQ_S)
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ_V  0xFFFFFFFFU
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ_S  0
+
+/** HP_SYS_CLKRST_CPU_CLK_STATUS0_REG register
+ *  CPU Clock Status
+ */
+#define HP_SYS_CLKRST_CPU_CLK_STATUS0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xe0)
+/** HP_SYS_CLKRST_REG_ASIC_OR_FPGA : RO; bitpos: [0]; default: 0;
+ *  0: ASIC mode, 1: FPGA mode
+ */
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA    (BIT(0))
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA_M  (HP_SYS_CLKRST_REG_ASIC_OR_FPGA_V << HP_SYS_CLKRST_REG_ASIC_OR_FPGA_S)
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA_S  0
+/** HP_SYS_CLKRST_REG_CPU_DIV_EFFECT : RO; bitpos: [1]; default: 0;
+ *  0: Divider bypass, 1: Divider takes effect
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT    (BIT(1))
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_M  (HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_V << HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_S  1
+/** HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL : RO; bitpos: [2]; default: 0;
+ *  0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m
+ */
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL    (BIT(2))
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_M  (HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_V << HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_S)
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_S  2
+/** HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR : RO; bitpos: [10:3]; default: 0;
+ *  cpu current div number
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_M  (HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_V << HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_S  3
+/** HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR : RO; bitpos: [18:11]; default: 0;
+ *  cpu current div numerator
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_M  (HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_V << HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_S  11
+/** HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR : RO; bitpos: [26:19]; default: 0;
+ *  cpu current div denominator
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_M  (HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_V << HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_S  19
+
+/** HP_SYS_CLKRST_DBG_CLK_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_DBG_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xe4)
+/** HP_SYS_CLKRST_REG_DBG_CH0_SEL : R/W; bitpos: [7:0]; default: 255;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH0_SEL_V << HP_SYS_CLKRST_REG_DBG_CH0_SEL_S)
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL_S  0
+/** HP_SYS_CLKRST_REG_DBG_CH1_SEL : R/W; bitpos: [15:8]; default: 255;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH1_SEL_V << HP_SYS_CLKRST_REG_DBG_CH1_SEL_S)
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL_S  8
+/** HP_SYS_CLKRST_REG_DBG_CH2_SEL : R/W; bitpos: [23:16]; default: 255;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH2_SEL_V << HP_SYS_CLKRST_REG_DBG_CH2_SEL_S)
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_S  16
+/** HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM : R/W; bitpos: [31:24]; default: 3;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_S  24
+
+/** HP_SYS_CLKRST_DBG_CLK_CTRL1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_DBG_CLK_CTRL1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xe8)
+/** HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM : R/W; bitpos: [7:0]; default: 3;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_DBG_CH0_EN : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN_M  (HP_SYS_CLKRST_REG_DBG_CH0_EN_V << HP_SYS_CLKRST_REG_DBG_CH0_EN_S)
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN_S  16
+/** HP_SYS_CLKRST_REG_DBG_CH1_EN : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN_M  (HP_SYS_CLKRST_REG_DBG_CH1_EN_V << HP_SYS_CLKRST_REG_DBG_CH1_EN_S)
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN_S  17
+/** HP_SYS_CLKRST_REG_DBG_CH2_EN : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN_M  (HP_SYS_CLKRST_REG_DBG_CH2_EN_V << HP_SYS_CLKRST_REG_DBG_CH2_EN_S)
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN_S  18
+
+/** HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xec)
+/** HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL : R/W; bitpos: [0]; default: 0;
+ *  1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0
+ */
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL    (BIT(0))
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_M  (HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_V << HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_S)
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_S  0
+/** HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL : R/W; bitpos: [1]; default: 1;
+ *  1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1
+ */
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL    (BIT(1))
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_M  (HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_V << HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_S)
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_S  1
+
+/** HP_SYS_CLKRST_AXI_PERF_MON_CLKRST_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_AXI_PERF_MON_CLKRST_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xf0)
+/** HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures axi_perf_mon clk enable
+ */
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures axi_perf_mon rst enable
+ */
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN_M  (HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN_V << HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN_S)
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN_S  1
+
+/** HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xf4)
+/** HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether cpu core0 waiti signal can control clock gate. If both core0 and
+ *  core1 waiti_icg_en is 1, then only when core0 and core1 all in waiti will close
+ *  related clock
+ */
+#define HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN_M  (HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN_V << HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN_S)
+#define HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN_S  0
+/** HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN : R/W; bitpos: [1]; default: 1;
+ *  Configures whether cpu core1 waiti signal can control clock gate. If both core0 and
+ *  core1 waiti_icg_en is 1, then only when core0 and core1 all in waiti will close
+ *  related clock
+ */
+#define HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN_M  (HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN_V << HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN_S)
+#define HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_sys_clkrst_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_sys_clkrst_struct.h
new file mode 100644
index 0000000000..4fe2960175
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_sys_clkrst_struct.h
@@ -0,0 +1,3058 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_en */
+/** Type of clk_en0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_clk_en0_reg_t;
+
+
+/** Group: root_clk_ctrl */
+/** Type of root_clk_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_cpuicm_delay_num : R/W; bitpos: [3:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpuicm_delay_num:4;
+        /** reg_soc_clk_div_update : WT; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_soc_clk_div_update:1;
+        /** reg_cpu_clk_div_num : R/W; bitpos: [12:5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpu_clk_div_num:8;
+        /** reg_cpu_clk_div_numerator : R/W; bitpos: [20:13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpu_clk_div_numerator:8;
+        /** reg_cpu_clk_div_denominator : R/W; bitpos: [28:21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpu_clk_div_denominator:8;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} hp_sys_clkrst_root_clk_ctrl0_reg_t;
+
+/** Type of root_clk_ctrl1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_mem_clk_div_num : R/W; bitpos: [7:0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_mem_clk_div_num:8;
+        /** reg_mem_clk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mem_clk_div_numerator:8;
+        /** reg_mem_clk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mem_clk_div_denominator:8;
+        /** reg_sys_clk_div_num : R/W; bitpos: [31:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sys_clk_div_num:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_root_clk_ctrl1_reg_t;
+
+/** Type of root_clk_ctrl2 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_sys_clk_div_numerator : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sys_clk_div_numerator:8;
+        /** reg_sys_clk_div_denominator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sys_clk_div_denominator:8;
+        /** reg_apb_clk_div_num : R/W; bitpos: [23:16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_apb_clk_div_num:8;
+        /** reg_apb_clk_div_numerator : R/W; bitpos: [31:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_apb_clk_div_numerator:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_root_clk_ctrl2_reg_t;
+
+/** Type of root_clk_ctrl3 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_apb_clk_div_denominator : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_apb_clk_div_denominator:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_sys_clkrst_root_clk_ctrl3_reg_t;
+
+
+/** Group: soc_clk_ctrl */
+/** Type of soc_clk_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_core0_clic_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_core0_clic_clk_en:1;
+        /** reg_core1_clic_clk_en : R/W; bitpos: [1]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_core1_clic_clk_en:1;
+        /** reg_misc_cpu_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_misc_cpu_clk_en:1;
+        /** reg_core0_cpu_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_core0_cpu_clk_en:1;
+        /** reg_core1_cpu_clk_en : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_core1_cpu_clk_en:1;
+        /** reg_tcm_cpu_clk_en : R/W; bitpos: [5]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_tcm_cpu_clk_en:1;
+        /** reg_busmon_cpu_clk_en : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_busmon_cpu_clk_en:1;
+        /** reg_l1cache_cpu_clk_en : R/W; bitpos: [7]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_cpu_clk_en:1;
+        /** reg_l1cache_d_cpu_clk_en : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_d_cpu_clk_en:1;
+        /** reg_l1cache_i0_cpu_clk_en : R/W; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i0_cpu_clk_en:1;
+        /** reg_l1cache_i1_cpu_clk_en : R/W; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i1_cpu_clk_en:1;
+        /** reg_trace_cpu_clk_en : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_trace_cpu_clk_en:1;
+        /** reg_icm_cpu_clk_en : R/W; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_icm_cpu_clk_en:1;
+        /** reg_gdma_cpu_clk_en : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gdma_cpu_clk_en:1;
+        /** reg_vpu_cpu_clk_en : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_vpu_cpu_clk_en:1;
+        /** reg_l1cache_mem_clk_en : R/W; bitpos: [15]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_mem_clk_en:1;
+        /** reg_l1cache_d_mem_clk_en : R/W; bitpos: [16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_d_mem_clk_en:1;
+        /** reg_l1cache_i0_mem_clk_en : R/W; bitpos: [17]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i0_mem_clk_en:1;
+        /** reg_l1cache_i1_mem_clk_en : R/W; bitpos: [18]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i1_mem_clk_en:1;
+        /** reg_l2cache_mem_clk_en : R/W; bitpos: [19]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2cache_mem_clk_en:1;
+        /** reg_l2mem_mem_clk_en : R/W; bitpos: [20]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2mem_mem_clk_en:1;
+        /** reg_l2memmon_mem_clk_en : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_l2memmon_mem_clk_en:1;
+        /** reg_icm_mem_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_icm_mem_clk_en:1;
+        /** reg_misc_sys_clk_en : R/W; bitpos: [23]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_misc_sys_clk_en:1;
+        /** reg_trace_sys_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_trace_sys_clk_en:1;
+        /** reg_l2cache_sys_clk_en : R/W; bitpos: [25]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2cache_sys_clk_en:1;
+        /** reg_l2mem_sys_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2mem_sys_clk_en:1;
+        /** reg_l2memmon_sys_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_l2memmon_sys_clk_en:1;
+        /** reg_tcmmon_sys_clk_en : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tcmmon_sys_clk_en:1;
+        /** reg_icm_sys_clk_en : R/W; bitpos: [29]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_icm_sys_clk_en:1;
+        /** reg_flash_sys_clk_en : R/W; bitpos: [30]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_flash_sys_clk_en:1;
+        /** reg_psram_sys_clk_en : R/W; bitpos: [31]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_psram_sys_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_soc_clk_ctrl0_reg_t;
+
+/** Type of soc_clk_ctrl1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpspi2_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_sys_clk_en:1;
+        /** reg_gpspi3_sys_clk_en : R/W; bitpos: [1]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_sys_clk_en:1;
+        /** reg_regdma_sys_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_regdma_sys_clk_en:1;
+        /** reg_ahb_pdma_sys_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ahb_pdma_sys_clk_en:1;
+        /** reg_axi_pdma_sys_clk_en : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_axi_pdma_sys_clk_en:1;
+        /** reg_gdma_sys_clk_en : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gdma_sys_clk_en:1;
+        /** reg_dma2d_sys_clk_en : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dma2d_sys_clk_en:1;
+        /** reg_vpu_sys_clk_en : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_vpu_sys_clk_en:1;
+        /** reg_jpeg_sys_clk_en : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_jpeg_sys_clk_en:1;
+        /** reg_ppa_sys_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_ppa_sys_clk_en:1;
+        /** reg_csi_brg_sys_clk_en : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_csi_brg_sys_clk_en:1;
+        /** reg_csi_host_sys_clk_en : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_csi_host_sys_clk_en:1;
+        /** reg_dsi_sys_clk_en : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dsi_sys_clk_en:1;
+        /** reg_emac_sys_clk_en : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_sys_clk_en:1;
+        /** reg_sdmmc_sys_clk_en : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdmmc_sys_clk_en:1;
+        /** reg_usb_otg11_sys_clk_en : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_usb_otg11_sys_clk_en:1;
+        /** reg_usb_otg20_sys_clk_en : R/W; bitpos: [16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_usb_otg20_sys_clk_en:1;
+        /** reg_uhci_sys_clk_en : R/W; bitpos: [17]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uhci_sys_clk_en:1;
+        /** reg_uart0_sys_clk_en : R/W; bitpos: [18]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart0_sys_clk_en:1;
+        /** reg_uart1_sys_clk_en : R/W; bitpos: [19]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart1_sys_clk_en:1;
+        /** reg_uart2_sys_clk_en : R/W; bitpos: [20]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart2_sys_clk_en:1;
+        /** reg_uart3_sys_clk_en : R/W; bitpos: [21]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart3_sys_clk_en:1;
+        /** reg_uart4_sys_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart4_sys_clk_en:1;
+        /** reg_parlio_sys_clk_en : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_sys_clk_en:1;
+        /** reg_etm_sys_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_etm_sys_clk_en:1;
+        /** reg_pvt_sys_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_sys_clk_en:1;
+        /** reg_crypto_sys_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_sys_clk_en:1;
+        /** reg_key_manager_sys_clk_en : R/W; bitpos: [27]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_key_manager_sys_clk_en:1;
+        /** reg_bitscrambler_sys_clk_en : R/W; bitpos: [28]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_bitscrambler_sys_clk_en:1;
+        /** reg_bitscrambler_rx_sys_clk_en : R/W; bitpos: [29]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_bitscrambler_rx_sys_clk_en:1;
+        /** reg_bitscrambler_tx_sys_clk_en : R/W; bitpos: [30]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_bitscrambler_tx_sys_clk_en:1;
+        /** reg_h264_sys_clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_h264_sys_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_soc_clk_ctrl1_reg_t;
+
+/** Type of soc_clk_ctrl2 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_rmt_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_sys_clk_en:1;
+        /** reg_hp_clkrst_apb_clk_en : R/W; bitpos: [1]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_hp_clkrst_apb_clk_en:1;
+        /** reg_sysreg_apb_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_sysreg_apb_clk_en:1;
+        /** reg_icm_apb_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_icm_apb_clk_en:1;
+        /** reg_intrmtx_apb_clk_en : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_intrmtx_apb_clk_en:1;
+        /** reg_adc_apb_clk_en : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_adc_apb_clk_en:1;
+        /** reg_uhci_apb_clk_en : R/W; bitpos: [6]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uhci_apb_clk_en:1;
+        /** reg_uart0_apb_clk_en : R/W; bitpos: [7]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart0_apb_clk_en:1;
+        /** reg_uart1_apb_clk_en : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart1_apb_clk_en:1;
+        /** reg_uart2_apb_clk_en : R/W; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart2_apb_clk_en:1;
+        /** reg_uart3_apb_clk_en : R/W; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart3_apb_clk_en:1;
+        /** reg_uart4_apb_clk_en : R/W; bitpos: [11]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart4_apb_clk_en:1;
+        /** reg_i2c0_apb_clk_en : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_apb_clk_en:1;
+        /** reg_i2c1_apb_clk_en : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_apb_clk_en:1;
+        /** reg_i2s0_apb_clk_en : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_apb_clk_en:1;
+        /** reg_i2s1_apb_clk_en : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_apb_clk_en:1;
+        /** reg_i2s2_apb_clk_en : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_apb_clk_en:1;
+        /** reg_i3c_mst_apb_clk_en : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i3c_mst_apb_clk_en:1;
+        /** reg_i3c_slv_apb_clk_en : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i3c_slv_apb_clk_en:1;
+        /** reg_gpspi2_apb_clk_en : R/W; bitpos: [19]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_apb_clk_en:1;
+        /** reg_gpspi3_apb_clk_en : R/W; bitpos: [20]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_apb_clk_en:1;
+        /** reg_timergrp0_apb_clk_en : R/W; bitpos: [21]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_apb_clk_en:1;
+        /** reg_timergrp1_apb_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_apb_clk_en:1;
+        /** reg_systimer_apb_clk_en : R/W; bitpos: [23]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_systimer_apb_clk_en:1;
+        /** reg_twai0_apb_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai0_apb_clk_en:1;
+        /** reg_twai1_apb_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai1_apb_clk_en:1;
+        /** reg_twai2_apb_clk_en : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai2_apb_clk_en:1;
+        /** reg_mcpwm0_apb_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm0_apb_clk_en:1;
+        /** reg_mcpwm1_apb_clk_en : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm1_apb_clk_en:1;
+        /** reg_usb_device_apb_clk_en : R/W; bitpos: [29]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_usb_device_apb_clk_en:1;
+        /** reg_pcnt_apb_clk_en : R/W; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pcnt_apb_clk_en:1;
+        /** reg_parlio_apb_clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_apb_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_soc_clk_ctrl2_reg_t;
+
+/** Type of soc_clk_ctrl3 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ledc_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_ledc_apb_clk_en:1;
+        /** reg_lcdcam_apb_clk_en : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcdcam_apb_clk_en:1;
+        /** reg_etm_apb_clk_en : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_etm_apb_clk_en:1;
+        /** reg_iomux_apb_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_iomux_apb_clk_en:1;
+        /** reg_l2cache_l2mem_clk_en : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2cache_l2mem_clk_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_sys_clkrst_soc_clk_ctrl3_reg_t;
+
+
+/** Group: ref_clk_ctrl */
+/** Type of ref_clk_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ref_50m_clk_div_num : R/W; bitpos: [7:0]; default: 9;
+         *  Reserved
+         */
+        uint32_t reg_ref_50m_clk_div_num:8;
+        /** reg_ref_25m_clk_div_num : R/W; bitpos: [15:8]; default: 19;
+         *  Reserved
+         */
+        uint32_t reg_ref_25m_clk_div_num:8;
+        /** reg_ref_240m_clk_div_num : R/W; bitpos: [23:16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_240m_clk_div_num:8;
+        /** reg_ref_160m_clk_div_num : R/W; bitpos: [31:24]; default: 2;
+         *  Reserved
+         */
+        uint32_t reg_ref_160m_clk_div_num:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_clk_ctrl0_reg_t;
+
+/** Type of ref_clk_ctrl1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ref_120m_clk_div_num : R/W; bitpos: [7:0]; default: 3;
+         *  Reserved
+         */
+        uint32_t reg_ref_120m_clk_div_num:8;
+        /** reg_ref_80m_clk_div_num : R/W; bitpos: [15:8]; default: 5;
+         *  Reserved
+         */
+        uint32_t reg_ref_80m_clk_div_num:8;
+        /** reg_ref_20m_clk_div_num : R/W; bitpos: [23:16]; default: 23;
+         *  Reserved
+         */
+        uint32_t reg_ref_20m_clk_div_num:8;
+        /** reg_tm_400m_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_400m_clk_en:1;
+        /** reg_tm_200m_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_200m_clk_en:1;
+        /** reg_tm_100m_clk_en : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_100m_clk_en:1;
+        /** reg_ref_50m_clk_en : R/W; bitpos: [27]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_50m_clk_en:1;
+        /** reg_ref_25m_clk_en : R/W; bitpos: [28]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_25m_clk_en:1;
+        /** reg_tm_480m_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_480m_clk_en:1;
+        /** reg_ref_240m_clk_en : R/W; bitpos: [30]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_240m_clk_en:1;
+        /** reg_tm_240m_clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_240m_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_clk_ctrl1_reg_t;
+
+/** Type of ref_clk_ctrl2 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ref_160m_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_160m_clk_en:1;
+        /** reg_tm_160m_clk_en : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_160m_clk_en:1;
+        /** reg_ref_120m_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_120m_clk_en:1;
+        /** reg_tm_120m_clk_en : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_120m_clk_en:1;
+        /** reg_ref_80m_clk_en : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_80m_clk_en:1;
+        /** reg_tm_80m_clk_en : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_80m_clk_en:1;
+        /** reg_tm_60m_clk_en : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_60m_clk_en:1;
+        /** reg_tm_48m_clk_en : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_48m_clk_en:1;
+        /** reg_ref_20m_clk_en : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_20m_clk_en:1;
+        /** reg_tm_20m_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_20m_clk_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_clk_ctrl2_reg_t;
+
+
+/** Group: peri_clk_ctrl0 */
+/** Type of peri_clk_ctrl00 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_flash_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_clk_src_sel:2;
+        /** reg_flash_pll_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_flash_pll_clk_en:1;
+        /** reg_flash_core_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_flash_core_clk_en:1;
+        /** reg_flash_core_clk_div_num : R/W; bitpos: [11:4]; default: 3;
+         *  Reserved
+         */
+        uint32_t reg_flash_core_clk_div_num:8;
+        /** reg_psram_clk_src_sel : R/W; bitpos: [13:12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_clk_src_sel:2;
+        /** reg_psram_pll_clk_en : R/W; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_psram_pll_clk_en:1;
+        /** reg_psram_core_clk_en : R/W; bitpos: [15]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_psram_core_clk_en:1;
+        /** reg_psram_core_clk_div_num : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_core_clk_div_num:8;
+        /** reg_pad_emac_ref_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pad_emac_ref_clk_en:1;
+        /** reg_emac_rmii_clk_src_sel : R/W; bitpos: [26:25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_rmii_clk_src_sel:2;
+        /** reg_emac_rmii_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_rmii_clk_en:1;
+        /** reg_emac_rx_clk_src_sel : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_rx_clk_src_sel:1;
+        /** reg_emac_rx_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_rx_clk_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl00_reg_t;
+
+/** Type of peri_clk_ctrl01 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_emac_rx_clk_div_num : R/W; bitpos: [7:0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_emac_rx_clk_div_num:8;
+        /** reg_emac_tx_clk_src_sel : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_tx_clk_src_sel:1;
+        /** reg_emac_tx_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_tx_clk_en:1;
+        /** reg_emac_tx_clk_div_num : R/W; bitpos: [17:10]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_emac_tx_clk_div_num:8;
+        /** reg_emac_ptp_ref_clk_src_sel : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_ptp_ref_clk_src_sel:1;
+        /** reg_emac_ptp_ref_clk_en : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_ptp_ref_clk_en:1;
+        /** reg_emac_unused0_clk_en : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_unused0_clk_en:1;
+        /** reg_emac_unused1_clk_en : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_unused1_clk_en:1;
+        /** reg_sdio_hs_mode : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_hs_mode:1;
+        /** reg_sdio_ls_clk_src_sel : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_src_sel:1;
+        /** reg_sdio_ls_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl01_reg_t;
+
+/** Type of peri_clk_ctrl02 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_sdio_ls_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_div_num:8;
+        /** reg_sdio_ls_clk_edge_cfg_update : WT; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_edge_cfg_update:1;
+        /** reg_sdio_ls_clk_edge_l : R/W; bitpos: [12:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_edge_l:4;
+        /** reg_sdio_ls_clk_edge_h : R/W; bitpos: [16:13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_edge_h:4;
+        /** reg_sdio_ls_clk_edge_n : R/W; bitpos: [20:17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_edge_n:4;
+        /** reg_sdio_ls_slf_clk_edge_sel : R/W; bitpos: [22:21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_slf_clk_edge_sel:2;
+        /** reg_sdio_ls_drv_clk_edge_sel : R/W; bitpos: [24:23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_drv_clk_edge_sel:2;
+        /** reg_sdio_ls_sam_clk_edge_sel : R/W; bitpos: [26:25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_sam_clk_edge_sel:2;
+        /** reg_sdio_ls_slf_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_slf_clk_en:1;
+        /** reg_sdio_ls_drv_clk_en : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_drv_clk_en:1;
+        /** reg_sdio_ls_sam_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_sam_clk_en:1;
+        /** reg_mipi_dsi_dphy_clk_src_sel : R/W; bitpos: [31:30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dphy_clk_src_sel:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl02_reg_t;
+
+/** Type of peri_clk_ctrl03 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_mipi_dsi_dphy_cfg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dphy_cfg_clk_en:1;
+        /** reg_mipi_dsi_dphy_pll_refclk_en : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dphy_pll_refclk_en:1;
+        /** reg_mipi_csi_dphy_clk_src_sel : R/W; bitpos: [3:2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_csi_dphy_clk_src_sel:2;
+        /** reg_mipi_csi_dphy_cfg_clk_en : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_csi_dphy_cfg_clk_en:1;
+        /** reg_mipi_dsi_dpiclk_src_sel : R/W; bitpos: [6:5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dpiclk_src_sel:2;
+        /** reg_mipi_dsi_dpiclk_en : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dpiclk_en:1;
+        /** reg_mipi_dsi_dpiclk_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dpiclk_div_num:8;
+        /** reg_mipi_dsi_dphy_pll_refclk_src_sel : R/W; bitpos: [18:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dphy_pll_refclk_src_sel:3;
+        /** reg_mipi_dsi_dphy_pll_refclk_div_num : R/W; bitpos: [26:19]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dphy_pll_refclk_div_num:8;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl03_reg_t;
+
+
+/** Group: peri_clk_ctrl1 */
+/** Type of peri_clk_ctrl10 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2c0_clk_src_sel : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_clk_src_sel:1;
+        /** reg_i2c0_clk_en : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_clk_en:1;
+        /** reg_i2c0_clk_div_num : R/W; bitpos: [9:2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_clk_div_num:8;
+        /** reg_i2c0_clk_div_numerator : R/W; bitpos: [17:10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_clk_div_numerator:8;
+        /** reg_i2c0_clk_div_denominator : R/W; bitpos: [25:18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_clk_div_denominator:8;
+        /** reg_i2c1_clk_src_sel : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_clk_src_sel:1;
+        /** reg_i2c1_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_clk_en:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl10_reg_t;
+
+/** Type of peri_clk_ctrl11 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2c1_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_clk_div_num:8;
+        /** reg_i2c1_clk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_clk_div_numerator:8;
+        /** reg_i2c1_clk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_clk_div_denominator:8;
+        /** reg_i2s0_rx_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_clk_en:1;
+        /** reg_i2s0_rx_clk_src_sel : R/W; bitpos: [26:25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_clk_src_sel:2;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl11_reg_t;
+
+/** Type of peri_clk_ctrl12 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_rx_div_n : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_div_n:8;
+        /** reg_i2s0_rx_div_x : R/W; bitpos: [16:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_div_x:9;
+        /** reg_i2s0_rx_div_y : R/W; bitpos: [25:17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_div_y:9;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl12_reg_t;
+
+/** Type of peri_clk_ctrl13 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_rx_div_z : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_div_z:9;
+        /** reg_i2s0_rx_div_yn1 : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_div_yn1:1;
+        /** reg_i2s0_tx_clk_en : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_clk_en:1;
+        /** reg_i2s0_tx_clk_src_sel : R/W; bitpos: [12:11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_clk_src_sel:2;
+        /** reg_i2s0_tx_div_n : R/W; bitpos: [20:13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_div_n:8;
+        /** reg_i2s0_tx_div_x : R/W; bitpos: [29:21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_div_x:9;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl13_reg_t;
+
+/** Type of peri_clk_ctrl14 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_tx_div_y : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_div_y:9;
+        /** reg_i2s0_tx_div_z : R/W; bitpos: [17:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_div_z:9;
+        /** reg_i2s0_tx_div_yn1 : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_div_yn1:1;
+        /** reg_i2s0_mst_clk_sel : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_mst_clk_sel:1;
+        /** reg_i2s1_rx_clk_en : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_clk_en:1;
+        /** reg_i2s1_rx_clk_src_sel : R/W; bitpos: [22:21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_clk_src_sel:2;
+        /** reg_i2s1_rx_div_n : R/W; bitpos: [30:23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_div_n:8;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl14_reg_t;
+
+/** Type of peri_clk_ctrl15 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_rx_div_x : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_div_x:9;
+        /** reg_i2s1_rx_div_y : R/W; bitpos: [17:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_div_y:9;
+        /** reg_i2s1_rx_div_z : R/W; bitpos: [26:18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_div_z:9;
+        /** reg_i2s1_rx_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_div_yn1:1;
+        /** reg_i2s1_tx_clk_en : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_clk_en:1;
+        /** reg_i2s1_tx_clk_src_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_clk_src_sel:2;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl15_reg_t;
+
+/** Type of peri_clk_ctrl16 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_tx_div_n : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_div_n:8;
+        /** reg_i2s1_tx_div_x : R/W; bitpos: [16:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_div_x:9;
+        /** reg_i2s1_tx_div_y : R/W; bitpos: [25:17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_div_y:9;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl16_reg_t;
+
+/** Type of peri_clk_ctrl17 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_tx_div_z : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_div_z:9;
+        /** reg_i2s1_tx_div_yn1 : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_div_yn1:1;
+        /** reg_i2s1_mst_clk_sel : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_mst_clk_sel:1;
+        /** reg_i2s2_rx_clk_en : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_clk_en:1;
+        /** reg_i2s2_rx_clk_src_sel : R/W; bitpos: [13:12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_clk_src_sel:2;
+        /** reg_i2s2_rx_div_n : R/W; bitpos: [21:14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_div_n:8;
+        /** reg_i2s2_rx_div_x : R/W; bitpos: [30:22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_div_x:9;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl17_reg_t;
+
+/** Type of peri_clk_ctrl18 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s2_rx_div_y : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_div_y:9;
+        /** reg_i2s2_rx_div_z : R/W; bitpos: [17:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_div_z:9;
+        /** reg_i2s2_rx_div_yn1 : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_div_yn1:1;
+        /** reg_i2s2_tx_clk_en : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_clk_en:1;
+        /** reg_i2s2_tx_clk_src_sel : R/W; bitpos: [21:20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_clk_src_sel:2;
+        /** reg_i2s2_tx_div_n : R/W; bitpos: [29:22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_div_n:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl18_reg_t;
+
+/** Type of peri_clk_ctrl19 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s2_tx_div_x : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_div_x:9;
+        /** reg_i2s2_tx_div_y : R/W; bitpos: [17:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_div_y:9;
+        /** reg_i2s2_tx_div_z : R/W; bitpos: [26:18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_div_z:9;
+        /** reg_i2s2_tx_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_div_yn1:1;
+        /** reg_i2s2_mst_clk_sel : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_mst_clk_sel:1;
+        /** reg_lcd_clk_src_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcd_clk_src_sel:2;
+        /** reg_lcd_clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcd_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl19_reg_t;
+
+/** Type of peri_clk_ctrl110 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_lcd_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcd_clk_div_num:8;
+        /** reg_lcd_clk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcd_clk_div_numerator:8;
+        /** reg_lcd_clk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcd_clk_div_denominator:8;
+        /** reg_uart0_clk_src_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart0_clk_src_sel:2;
+        /** reg_uart0_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart0_clk_en:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl110_reg_t;
+
+/** Type of peri_clk_ctrl111 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_uart0_sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart0_sclk_div_num:8;
+        /** reg_uart0_sclk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart0_sclk_div_numerator:8;
+        /** reg_uart0_sclk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart0_sclk_div_denominator:8;
+        /** reg_uart1_clk_src_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart1_clk_src_sel:2;
+        /** reg_uart1_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart1_clk_en:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl111_reg_t;
+
+/** Type of peri_clk_ctrl112 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_uart1_sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart1_sclk_div_num:8;
+        /** reg_uart1_sclk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart1_sclk_div_numerator:8;
+        /** reg_uart1_sclk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart1_sclk_div_denominator:8;
+        /** reg_uart2_clk_src_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart2_clk_src_sel:2;
+        /** reg_uart2_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart2_clk_en:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl112_reg_t;
+
+/** Type of peri_clk_ctrl113 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_uart2_sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart2_sclk_div_num:8;
+        /** reg_uart2_sclk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart2_sclk_div_numerator:8;
+        /** reg_uart2_sclk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart2_sclk_div_denominator:8;
+        /** reg_uart3_clk_src_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart3_clk_src_sel:2;
+        /** reg_uart3_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart3_clk_en:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl113_reg_t;
+
+/** Type of peri_clk_ctrl114 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_uart3_sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart3_sclk_div_num:8;
+        /** reg_uart3_sclk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart3_sclk_div_numerator:8;
+        /** reg_uart3_sclk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart3_sclk_div_denominator:8;
+        /** reg_uart4_clk_src_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart4_clk_src_sel:2;
+        /** reg_uart4_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart4_clk_en:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl114_reg_t;
+
+/** Type of peri_clk_ctrl115 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_uart4_sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart4_sclk_div_num:8;
+        /** reg_uart4_sclk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart4_sclk_div_numerator:8;
+        /** reg_uart4_sclk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart4_sclk_div_denominator:8;
+        /** reg_twai0_clk_src_sel : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai0_clk_src_sel:1;
+        /** reg_twai0_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai0_clk_en:1;
+        /** reg_twai1_clk_src_sel : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai1_clk_src_sel:1;
+        /** reg_twai1_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai1_clk_en:1;
+        /** reg_twai2_clk_src_sel : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai2_clk_src_sel:1;
+        /** reg_twai2_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai2_clk_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl115_reg_t;
+
+/** Type of peri_clk_ctrl116 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpspi2_clk_src_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_clk_src_sel:3;
+        /** reg_gpspi2_hs_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_hs_clk_en:1;
+        /** reg_gpspi2_hs_clk_div_num : R/W; bitpos: [11:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_hs_clk_div_num:8;
+        /** reg_gpspi2_mst_clk_div_num : R/W; bitpos: [19:12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_mst_clk_div_num:8;
+        /** reg_gpspi2_mst_clk_en : R/W; bitpos: [20]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_mst_clk_en:1;
+        /** reg_gpspi3_clk_src_sel : R/W; bitpos: [23:21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_clk_src_sel:3;
+        /** reg_gpspi3_hs_clk_en : R/W; bitpos: [24]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_hs_clk_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl116_reg_t;
+
+/** Type of peri_clk_ctrl117 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpspi3_hs_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_hs_clk_div_num:8;
+        /** reg_gpspi3_mst_clk_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_mst_clk_div_num:8;
+        /** reg_gpspi3_mst_clk_en : R/W; bitpos: [16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_mst_clk_en:1;
+        /** reg_parlio_rx_clk_src_sel : R/W; bitpos: [18:17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_rx_clk_src_sel:2;
+        /** reg_parlio_rx_clk_en : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_rx_clk_en:1;
+        /** reg_parlio_rx_clk_div_num : R/W; bitpos: [27:20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_rx_clk_div_num:8;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl117_reg_t;
+
+/** Type of peri_clk_ctrl118 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_parlio_rx_clk_div_numerator : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_rx_clk_div_numerator:8;
+        /** reg_parlio_rx_clk_div_denominator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_rx_clk_div_denominator:8;
+        /** reg_parlio_tx_clk_src_sel : R/W; bitpos: [17:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_tx_clk_src_sel:2;
+        /** reg_parlio_tx_clk_en : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_tx_clk_en:1;
+        /** reg_parlio_tx_clk_div_num : R/W; bitpos: [26:19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_tx_clk_div_num:8;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl118_reg_t;
+
+/** Type of peri_clk_ctrl119 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_parlio_tx_clk_div_numerator : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_tx_clk_div_numerator:8;
+        /** reg_parlio_tx_clk_div_denominator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_tx_clk_div_denominator:8;
+        /** reg_i3c_mst_clk_src_sel : R/W; bitpos: [17:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i3c_mst_clk_src_sel:2;
+        /** reg_i3c_mst_clk_en : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i3c_mst_clk_en:1;
+        /** reg_i3c_mst_clk_div_num : R/W; bitpos: [26:19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i3c_mst_clk_div_num:8;
+        /** reg_cam_clk_src_sel : R/W; bitpos: [28:27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cam_clk_src_sel:2;
+        /** reg_cam_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cam_clk_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl119_reg_t;
+
+/** Type of peri_clk_ctrl120 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_cam_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cam_clk_div_num:8;
+        /** reg_cam_clk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cam_clk_div_numerator:8;
+        /** reg_cam_clk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cam_clk_div_denominator:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl120_reg_t;
+
+
+/** Group: peri_clk_ctrl2 */
+/** Type of peri_clk_ctrl20 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_mcpwm0_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm0_clk_src_sel:2;
+        /** reg_mcpwm0_clk_en : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm0_clk_en:1;
+        /** reg_mcpwm0_clk_div_num : R/W; bitpos: [10:3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm0_clk_div_num:8;
+        /** reg_mcpwm1_clk_src_sel : R/W; bitpos: [12:11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm1_clk_src_sel:2;
+        /** reg_mcpwm1_clk_en : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm1_clk_en:1;
+        /** reg_mcpwm1_clk_div_num : R/W; bitpos: [21:14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm1_clk_div_num:8;
+        /** reg_timergrp0_t0_src_sel : R/W; bitpos: [23:22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_t0_src_sel:2;
+        /** reg_timergrp0_t0_clk_en : R/W; bitpos: [24]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_t0_clk_en:1;
+        /** reg_timergrp0_t1_src_sel : R/W; bitpos: [26:25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_t1_src_sel:2;
+        /** reg_timergrp0_t1_clk_en : R/W; bitpos: [27]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_t1_clk_en:1;
+        /** reg_timergrp0_wdt_src_sel : R/W; bitpos: [29:28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_wdt_src_sel:2;
+        /** reg_timergrp0_wdt_clk_en : R/W; bitpos: [30]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_wdt_clk_en:1;
+        /** reg_timergrp0_tgrt_clk_en : R/W; bitpos: [31]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_tgrt_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl20_reg_t;
+
+/** Type of peri_clk_ctrl21 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_timergrp0_tgrt_clk_src_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_tgrt_clk_src_sel:4;
+        /** reg_timergrp0_tgrt_clk_div_num : R/W; bitpos: [19:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_tgrt_clk_div_num:16;
+        /** reg_timergrp1_t0_src_sel : R/W; bitpos: [21:20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_t0_src_sel:2;
+        /** reg_timergrp1_t0_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_t0_clk_en:1;
+        /** reg_timergrp1_t1_src_sel : R/W; bitpos: [24:23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_t1_src_sel:2;
+        /** reg_timergrp1_t1_clk_en : R/W; bitpos: [25]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_t1_clk_en:1;
+        /** reg_timergrp1_wdt_src_sel : R/W; bitpos: [27:26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_wdt_src_sel:2;
+        /** reg_timergrp1_wdt_clk_en : R/W; bitpos: [28]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_wdt_clk_en:1;
+        /** reg_systimer_clk_src_sel : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_systimer_clk_src_sel:1;
+        /** reg_systimer_clk_en : R/W; bitpos: [30]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_systimer_clk_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl21_reg_t;
+
+/** Type of peri_clk_ctrl22 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ledc_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_ledc_clk_src_sel:2;
+        /** reg_ledc_clk_en : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_ledc_clk_en:1;
+        /** reg_rmt_clk_src_sel : R/W; bitpos: [4:3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_clk_src_sel:2;
+        /** reg_rmt_clk_en : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_clk_en:1;
+        /** reg_rmt_clk_div_num : R/W; bitpos: [13:6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_clk_div_num:8;
+        /** reg_rmt_clk_div_numerator : R/W; bitpos: [21:14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_clk_div_numerator:8;
+        /** reg_rmt_clk_div_denominator : R/W; bitpos: [29:22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_clk_div_denominator:8;
+        /** reg_adc_clk_src_sel : R/W; bitpos: [31:30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_adc_clk_src_sel:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl22_reg_t;
+
+/** Type of peri_clk_ctrl23 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_adc_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_adc_clk_en:1;
+        /** reg_adc_clk_div_num : R/W; bitpos: [8:1]; default: 4;
+         *  Reserved
+         */
+        uint32_t reg_adc_clk_div_num:8;
+        /** reg_adc_clk_div_numerator : R/W; bitpos: [16:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_adc_clk_div_numerator:8;
+        /** reg_adc_clk_div_denominator : R/W; bitpos: [24:17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_adc_clk_div_denominator:8;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl23_reg_t;
+
+/** Type of peri_clk_ctrl24 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_adc_sar1_clk_div_num : R/W; bitpos: [7:0]; default: 4;
+         *  Reserved
+         */
+        uint32_t reg_adc_sar1_clk_div_num:8;
+        /** reg_adc_sar2_clk_div_num : R/W; bitpos: [15:8]; default: 4;
+         *  Reserved
+         */
+        uint32_t reg_adc_sar2_clk_div_num:8;
+        /** reg_pvt_clk_div_num : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_clk_div_num:8;
+        /** reg_pvt_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_clk_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl24_reg_t;
+
+/** Type of peri_clk_ctrl25 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_pvt_peri_group_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_peri_group_clk_div_num:8;
+        /** reg_pvt_peri_group1_clk_en : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_peri_group1_clk_en:1;
+        /** reg_pvt_peri_group2_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_peri_group2_clk_en:1;
+        /** reg_pvt_peri_group3_clk_en : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_peri_group3_clk_en:1;
+        /** reg_pvt_peri_group4_clk_en : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_peri_group4_clk_en:1;
+        /** reg_crypto_clk_src_sel : R/W; bitpos: [13:12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_crypto_clk_src_sel:2;
+        /** reg_crypto_aes_clk_en : R/W; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_aes_clk_en:1;
+        /** reg_crypto_ds_clk_en : R/W; bitpos: [15]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_ds_clk_en:1;
+        /** reg_crypto_ecc_clk_en : R/W; bitpos: [16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_ecc_clk_en:1;
+        /** reg_crypto_hmac_clk_en : R/W; bitpos: [17]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_hmac_clk_en:1;
+        /** reg_crypto_rsa_clk_en : R/W; bitpos: [18]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_rsa_clk_en:1;
+        /** reg_crypto_sec_clk_en : R/W; bitpos: [19]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_sec_clk_en:1;
+        /** reg_crypto_sha_clk_en : R/W; bitpos: [20]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_sha_clk_en:1;
+        /** reg_crypto_ecdsa_clk_en : R/W; bitpos: [21]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_ecdsa_clk_en:1;
+        /** reg_crypto_km_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_km_clk_en:1;
+        /** reg_isp_clk_src_sel : R/W; bitpos: [24:23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_isp_clk_src_sel:2;
+        /** reg_isp_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_isp_clk_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl25_reg_t;
+
+/** Type of peri_clk_ctrl26 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_isp_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_isp_clk_div_num:8;
+        /** reg_iomux_clk_src_sel : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_iomux_clk_src_sel:1;
+        /** reg_iomux_clk_en : R/W; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_iomux_clk_en:1;
+        /** reg_iomux_clk_div_num : R/W; bitpos: [17:10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_iomux_clk_div_num:8;
+        /** reg_h264_clk_src_sel : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_h264_clk_src_sel:1;
+        /** reg_h264_clk_en : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_h264_clk_en:1;
+        /** reg_h264_clk_div_num : R/W; bitpos: [27:20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_h264_clk_div_num:8;
+        /** reg_padbist_rx_clk_src_sel : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_rx_clk_src_sel:1;
+        /** reg_padbist_rx_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_rx_clk_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl26_reg_t;
+
+/** Type of peri_clk_ctrl27 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_padbist_rx_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_rx_clk_div_num:8;
+        /** reg_padbist_tx_clk_src_sel : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_tx_clk_src_sel:1;
+        /** reg_padbist_tx_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_tx_clk_en:1;
+        /** reg_padbist_tx_clk_div_num : R/W; bitpos: [17:10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_tx_clk_div_num:8;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl27_reg_t;
+
+
+/** Group: clk_force_on_ctrl */
+/** Type of clk_force_on_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_cpuicm_gated_clk_force_on : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_cpuicm_gated_clk_force_on:1;
+        /** reg_tcm_cpu_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_tcm_cpu_clk_force_on:1;
+        /** reg_busmon_cpu_clk_force_on : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_busmon_cpu_clk_force_on:1;
+        /** reg_l1cache_cpu_clk_force_on : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_cpu_clk_force_on:1;
+        /** reg_l1cache_d_cpu_clk_force_on : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_d_cpu_clk_force_on:1;
+        /** reg_l1cache_i0_cpu_clk_force_on : R/W; bitpos: [5]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i0_cpu_clk_force_on:1;
+        /** reg_l1cache_i1_cpu_clk_force_on : R/W; bitpos: [6]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i1_cpu_clk_force_on:1;
+        /** reg_trace_cpu_clk_force_on : R/W; bitpos: [7]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_trace_cpu_clk_force_on:1;
+        /** reg_trace_sys_clk_force_on : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_trace_sys_clk_force_on:1;
+        /** reg_l1cache_mem_clk_force_on : R/W; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_mem_clk_force_on:1;
+        /** reg_l1cache_d_mem_clk_force_on : R/W; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_d_mem_clk_force_on:1;
+        /** reg_l1cache_i0_mem_clk_force_on : R/W; bitpos: [11]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i0_mem_clk_force_on:1;
+        /** reg_l1cache_i1_mem_clk_force_on : R/W; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i1_mem_clk_force_on:1;
+        /** reg_l2cache_mem_clk_force_on : R/W; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2cache_mem_clk_force_on:1;
+        /** reg_l2mem_mem_clk_force_on : R/W; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2mem_mem_clk_force_on:1;
+        /** reg_sar1_clk_force_on : R/W; bitpos: [15]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_sar1_clk_force_on:1;
+        /** reg_sar2_clk_force_on : R/W; bitpos: [16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_sar2_clk_force_on:1;
+        /** reg_gmac_tx_clk_force_on : R/W; bitpos: [17]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gmac_tx_clk_force_on:1;
+        /** reg_l2cache_l2mem_clk_force_on : R/W; bitpos: [18]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2cache_l2mem_clk_force_on:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} hp_sys_clkrst_clk_force_on_ctrl0_reg_t;
+
+
+/** Group: dpa_ctrl */
+/** Type of dpa_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sec_dpa_level:2;
+        /** reg_sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sec_dpa_cfg_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dpa_ctrl0_reg_t;
+
+
+/** Group: ana_pll_ctrl */
+/** Type of ana_pll_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_plla_cal_end : RO; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_plla_cal_end:1;
+        /** reg_plla_cal_stop : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_plla_cal_stop:1;
+        /** reg_cpu_pll_cal_end : RO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpu_pll_cal_end:1;
+        /** reg_cpu_pll_cal_stop : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpu_pll_cal_stop:1;
+        /** reg_sdio_pll_cal_end : RO; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_pll_cal_end:1;
+        /** reg_sdio_pll_cal_stop : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_pll_cal_stop:1;
+        /** reg_sys_pll_cal_end : RO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sys_pll_cal_end:1;
+        /** reg_sys_pll_cal_stop : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sys_pll_cal_stop:1;
+        /** reg_mspi_cal_end : RO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mspi_cal_end:1;
+        /** reg_mspi_cal_stop : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mspi_cal_stop:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ana_pll_ctrl0_reg_t;
+
+
+/** Group: hp_rst_en */
+/** Type of hp_rst_en0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_rst_en_corectrl : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_corectrl:1;
+        /** reg_rst_en_pvt_top : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_top:1;
+        /** reg_rst_en_pvt_peri_group1 : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_peri_group1:1;
+        /** reg_rst_en_pvt_peri_group2 : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_peri_group2:1;
+        /** reg_rst_en_pvt_peri_group3 : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_peri_group3:1;
+        /** reg_rst_en_pvt_peri_group4 : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_peri_group4:1;
+        /** reg_rst_en_regdma : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_regdma:1;
+        /** reg_rst_en_core0_global : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_core0_global:1;
+        /** reg_rst_en_core1_global : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_core1_global:1;
+        /** reg_rst_en_coretrace0 : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_coretrace0:1;
+        /** reg_rst_en_coretrace1 : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_coretrace1:1;
+        /** reg_rst_en_hp_tcm : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_hp_tcm:1;
+        /** reg_rst_en_hp_cache : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_hp_cache:1;
+        /** reg_rst_en_l1_i0_cache : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l1_i0_cache:1;
+        /** reg_rst_en_l1_i1_cache : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l1_i1_cache:1;
+        /** reg_rst_en_l1_d_cache : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l1_d_cache:1;
+        /** reg_rst_en_l2_cache : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l2_cache:1;
+        /** reg_rst_en_l2_mem : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l2_mem:1;
+        /** reg_rst_en_l2memmon : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l2memmon:1;
+        /** reg_rst_en_tcmmon : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_tcmmon:1;
+        /** reg_rst_en_pvt_apb : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_apb:1;
+        /** reg_rst_en_gdma : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_gdma:1;
+        /** reg_rst_en_mspi_axi : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_mspi_axi:1;
+        /** reg_rst_en_dual_mspi_axi : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_dual_mspi_axi:1;
+        /** reg_rst_en_mspi_apb : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_mspi_apb:1;
+        /** reg_rst_en_dual_mspi_apb : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_dual_mspi_apb:1;
+        /** reg_rst_en_dsi_brg : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_dsi_brg:1;
+        /** reg_rst_en_csi_host : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_csi_host:1;
+        /** reg_rst_en_csi_brg : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_csi_brg:1;
+        /** reg_rst_en_isp : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_isp:1;
+        /** reg_rst_en_jpeg : R/W; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_jpeg:1;
+        /** reg_rst_en_dma2d : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_dma2d:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_rst_en0_reg_t;
+
+/** Type of hp_rst_en1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_rst_en_ppa : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ppa:1;
+        /** reg_rst_en_ahb_pdma : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ahb_pdma:1;
+        /** reg_rst_en_axi_pdma : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_axi_pdma:1;
+        /** reg_rst_en_iomux : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_iomux:1;
+        /** reg_rst_en_padbist : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_padbist:1;
+        /** reg_rst_en_stimer : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_stimer:1;
+        /** reg_rst_en_timergrp0 : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_timergrp0:1;
+        /** reg_rst_en_timergrp1 : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_timergrp1:1;
+        /** reg_rst_en_uart0_core : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart0_core:1;
+        /** reg_rst_en_uart1_core : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart1_core:1;
+        /** reg_rst_en_uart2_core : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart2_core:1;
+        /** reg_rst_en_uart3_core : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart3_core:1;
+        /** reg_rst_en_uart4_core : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart4_core:1;
+        /** reg_rst_en_uart0_apb : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart0_apb:1;
+        /** reg_rst_en_uart1_apb : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart1_apb:1;
+        /** reg_rst_en_uart2_apb : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart2_apb:1;
+        /** reg_rst_en_uart3_apb : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart3_apb:1;
+        /** reg_rst_en_uart4_apb : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart4_apb:1;
+        /** reg_rst_en_uhci : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uhci:1;
+        /** reg_rst_en_i3cmst : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i3cmst:1;
+        /** reg_rst_en_i3cslv : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i3cslv:1;
+        /** reg_rst_en_i2c1 : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i2c1:1;
+        /** reg_rst_en_i2c0 : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i2c0:1;
+        /** reg_rst_en_rmt : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_rmt:1;
+        /** reg_rst_en_pwm0 : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pwm0:1;
+        /** reg_rst_en_pwm1 : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pwm1:1;
+        /** reg_rst_en_twai0 : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_twai0:1;
+        /** reg_rst_en_twai1 : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_twai1:1;
+        /** reg_rst_en_twai2 : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_twai2:1;
+        /** reg_rst_en_ledc : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ledc:1;
+        /** reg_rst_en_pcnt : R/W; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pcnt:1;
+        /** reg_rst_en_etm : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_etm:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_rst_en1_reg_t;
+
+/** Type of hp_rst_en2 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_rst_en_intrmtx : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_intrmtx:1;
+        /** reg_rst_en_parlio : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_parlio:1;
+        /** reg_rst_en_parlio_rx : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_parlio_rx:1;
+        /** reg_rst_en_parlio_tx : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_parlio_tx:1;
+        /** reg_rst_en_i2s0_apb : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i2s0_apb:1;
+        /** reg_rst_en_i2s1_apb : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i2s1_apb:1;
+        /** reg_rst_en_i2s2_apb : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i2s2_apb:1;
+        /** reg_rst_en_spi2 : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_spi2:1;
+        /** reg_rst_en_spi3 : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_spi3:1;
+        /** reg_rst_en_lcdcam : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_lcdcam:1;
+        /** reg_rst_en_adc : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_adc:1;
+        /** reg_rst_en_bitscrambler : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_bitscrambler:1;
+        /** reg_rst_en_bitscrambler_rx : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_bitscrambler_rx:1;
+        /** reg_rst_en_bitscrambler_tx : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_bitscrambler_tx:1;
+        /** reg_rst_en_crypto : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_crypto:1;
+        /** reg_rst_en_sec : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_sec:1;
+        /** reg_rst_en_aes : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_aes:1;
+        /** reg_rst_en_ds : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ds:1;
+        /** reg_rst_en_sha : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_sha:1;
+        /** reg_rst_en_hmac : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_hmac:1;
+        /** reg_rst_en_ecdsa : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ecdsa:1;
+        /** reg_rst_en_rsa : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_rsa:1;
+        /** reg_rst_en_ecc : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ecc:1;
+        /** reg_rst_en_km : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_km:1;
+        /** reg_rst_en_h264 : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_h264:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_rst_en2_reg_t;
+
+
+/** Group: hp_force_norst */
+/** Type of hp_force_norst0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_force_norst_core0 : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_core0:1;
+        /** reg_force_norst_core1 : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_core1:1;
+        /** reg_force_norst_coretrace0 : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_coretrace0:1;
+        /** reg_force_norst_coretrace1 : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_coretrace1:1;
+        /** reg_force_norst_l2memmon : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_l2memmon:1;
+        /** reg_force_norst_tcmmon : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_tcmmon:1;
+        /** reg_force_norst_gdma : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_gdma:1;
+        /** reg_force_norst_mspi_axi : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_mspi_axi:1;
+        /** reg_force_norst_dual_mspi_axi : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_dual_mspi_axi:1;
+        /** reg_force_norst_mspi_apb : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_mspi_apb:1;
+        /** reg_force_norst_dual_mspi_apb : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_dual_mspi_apb:1;
+        /** reg_force_norst_dsi_brg : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_dsi_brg:1;
+        /** reg_force_norst_csi_host : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_csi_host:1;
+        /** reg_force_norst_csi_brg : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_csi_brg:1;
+        /** reg_force_norst_isp : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_isp:1;
+        /** reg_force_norst_jpeg : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_jpeg:1;
+        /** reg_force_norst_dma2d : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_dma2d:1;
+        /** reg_force_norst_ppa : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_ppa:1;
+        /** reg_force_norst_ahb_pdma : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_ahb_pdma:1;
+        /** reg_force_norst_axi_pdma : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_axi_pdma:1;
+        /** reg_force_norst_iomux : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_iomux:1;
+        /** reg_force_norst_padbist : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_padbist:1;
+        /** reg_force_norst_stimer : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_stimer:1;
+        /** reg_force_norst_timergrp0 : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_timergrp0:1;
+        /** reg_force_norst_timergrp1 : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_timergrp1:1;
+        /** reg_force_norst_uart0 : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uart0:1;
+        /** reg_force_norst_uart1 : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uart1:1;
+        /** reg_force_norst_uart2 : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uart2:1;
+        /** reg_force_norst_uart3 : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uart3:1;
+        /** reg_force_norst_uart4 : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uart4:1;
+        /** reg_force_norst_uhci : R/W; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uhci:1;
+        /** reg_force_norst_i3cmst : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i3cmst:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_force_norst0_reg_t;
+
+/** Type of hp_force_norst1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_force_norst_i3cslv : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i3cslv:1;
+        /** reg_force_norst_i2c1 : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i2c1:1;
+        /** reg_force_norst_i2c0 : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i2c0:1;
+        /** reg_force_norst_rmt : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_rmt:1;
+        /** reg_force_norst_pwm0 : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_pwm0:1;
+        /** reg_force_norst_pwm1 : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_pwm1:1;
+        /** reg_force_norst_can0 : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_can0:1;
+        /** reg_force_norst_can1 : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_can1:1;
+        /** reg_force_norst_can2 : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_can2:1;
+        /** reg_force_norst_ledc : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_ledc:1;
+        /** reg_force_norst_pcnt : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_pcnt:1;
+        /** reg_force_norst_etm : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_etm:1;
+        /** reg_force_norst_intrmtx : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_intrmtx:1;
+        /** reg_force_norst_parlio : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_parlio:1;
+        /** reg_force_norst_parlio_rx : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_parlio_rx:1;
+        /** reg_force_norst_parlio_tx : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_parlio_tx:1;
+        /** reg_force_norst_i2s0 : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i2s0:1;
+        /** reg_force_norst_i2s1 : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i2s1:1;
+        /** reg_force_norst_i2s2 : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i2s2:1;
+        /** reg_force_norst_spi2 : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_spi2:1;
+        /** reg_force_norst_spi3 : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_spi3:1;
+        /** reg_force_norst_lcdcam : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_lcdcam:1;
+        /** reg_force_norst_adc : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_adc:1;
+        /** reg_force_norst_bitscrambler : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_bitscrambler:1;
+        /** reg_force_norst_bitscrambler_rx : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_bitscrambler_rx:1;
+        /** reg_force_norst_bitscrambler_tx : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_bitscrambler_tx:1;
+        /** reg_force_norst_h264 : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_h264:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_force_norst1_reg_t;
+
+
+/** Group: hpwdt_core0_rst_ctrl */
+/** Type of hpwdt_core0_rst_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_hpcore0_stall_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_hpcore0_stall_en:1;
+        /** reg_hpcore0_stall_wait_num : R/W; bitpos: [8:1]; default: 8;
+         *  Reserved
+         */
+        uint32_t reg_hpcore0_stall_wait_num:8;
+        /** reg_wdt_hpcore0_rst_len : R/W; bitpos: [16:9]; default: 8;
+         *  Reserved
+         */
+        uint32_t reg_wdt_hpcore0_rst_len:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpwdt_core0_rst_ctrl0_reg_t;
+
+
+/** Group: hpwdt_core1_rst_ctrl */
+/** Type of hpwdt_core1_rst_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_hpcore1_stall_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_hpcore1_stall_en:1;
+        /** reg_hpcore1_stall_wait_num : R/W; bitpos: [8:1]; default: 8;
+         *  Reserved
+         */
+        uint32_t reg_hpcore1_stall_wait_num:8;
+        /** reg_wdt_hpcore1_rst_len : R/W; bitpos: [16:9]; default: 8;
+         *  Reserved
+         */
+        uint32_t reg_wdt_hpcore1_rst_len:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpwdt_core1_rst_ctrl0_reg_t;
+
+
+/** Group: cpu_src_freq */
+/** Type of cpu_src_freq0 register
+ *  CPU Source Frequency
+ */
+typedef union {
+    struct {
+        /** reg_cpu_src_freq : RO; bitpos: [31:0]; default: 0;
+         *  cpu source clock frequency, step by 0.25MHz
+         */
+        uint32_t reg_cpu_src_freq:32;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cpu_src_freq0_reg_t;
+
+
+/** Group: cpu_clk_status */
+/** Type of cpu_clk_status0 register
+ *  CPU Clock Status
+ */
+typedef union {
+    struct {
+        /** reg_asic_or_fpga : RO; bitpos: [0]; default: 0;
+         *  0: ASIC mode, 1: FPGA mode
+         */
+        uint32_t reg_asic_or_fpga:1;
+        /** reg_cpu_div_effect : RO; bitpos: [1]; default: 0;
+         *  0: Divider bypass, 1: Divider takes effect
+         */
+        uint32_t reg_cpu_div_effect:1;
+        /** reg_cpu_src_is_cpll : RO; bitpos: [2]; default: 0;
+         *  0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m
+         */
+        uint32_t reg_cpu_src_is_cpll:1;
+        /** reg_cpu_div_num_cur : RO; bitpos: [10:3]; default: 0;
+         *  cpu current div number
+         */
+        uint32_t reg_cpu_div_num_cur:8;
+        /** reg_cpu_div_numerator_cur : RO; bitpos: [18:11]; default: 0;
+         *  cpu current div numerator
+         */
+        uint32_t reg_cpu_div_numerator_cur:8;
+        /** reg_cpu_div_denominator_cur : RO; bitpos: [26:19]; default: 0;
+         *  cpu current div denominator
+         */
+        uint32_t reg_cpu_div_denominator_cur:8;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cpu_clk_status0_reg_t;
+
+
+/** Group: dbg_clk_ctrl */
+/** Type of dbg_clk_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_dbg_ch0_sel : R/W; bitpos: [7:0]; default: 255;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch0_sel:8;
+        /** reg_dbg_ch1_sel : R/W; bitpos: [15:8]; default: 255;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch1_sel:8;
+        /** reg_dbg_ch2_sel : R/W; bitpos: [23:16]; default: 255;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch2_sel:8;
+        /** reg_dbg_ch0_div_num : R/W; bitpos: [31:24]; default: 3;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch0_div_num:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dbg_clk_ctrl0_reg_t;
+
+/** Type of dbg_clk_ctrl1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_dbg_ch1_div_num : R/W; bitpos: [7:0]; default: 3;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch1_div_num:8;
+        /** reg_dbg_ch2_div_num : R/W; bitpos: [15:8]; default: 3;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch2_div_num:8;
+        /** reg_dbg_ch0_en : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch0_en:1;
+        /** reg_dbg_ch1_en : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch1_en:1;
+        /** reg_dbg_ch2_en : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch2_en:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dbg_clk_ctrl1_reg_t;
+
+
+/** Group: hpcore_wdt_reset_source */
+/** Type of hpcore_wdt_reset_source0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_hpcore0_wdt_reset_source_sel : R/W; bitpos: [0]; default: 0;
+         *  1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0
+         */
+        uint32_t reg_hpcore0_wdt_reset_source_sel:1;
+        /** reg_hpcore1_wdt_reset_source_sel : R/W; bitpos: [1]; default: 1;
+         *  1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1
+         */
+        uint32_t reg_hpcore1_wdt_reset_source_sel:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpcore_wdt_reset_source0_reg_t;
+
+
+/** Group: axi_perf_mon_clkrst_ctrl */
+/** Type of axi_perf_mon_clkrst_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_axi_perf_mon_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures axi_perf_mon clk enable
+         */
+        uint32_t reg_axi_perf_mon_sys_clk_en:1;
+        /** reg_axi_perf_mon_sys_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Configures axi_perf_mon rst enable
+         */
+        uint32_t reg_axi_perf_mon_sys_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_clkrst_axi_perf_mon_clkrst_ctrl0_reg_t;
+
+
+/** Group: cpu_waiti_ctrl */
+/** Type of cpu_waiti_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_core0_waiti_icg_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether cpu core0 waiti signal can control clock gate. If both core0 and
+         *  core1 waiti_icg_en is 1, then only when core0 and core1 all in waiti will close
+         *  related clock
+         */
+        uint32_t reg_core0_waiti_icg_en:1;
+        /** reg_core1_waiti_icg_en : R/W; bitpos: [1]; default: 1;
+         *  Configures whether cpu core1 waiti signal can control clock gate. If both core0 and
+         *  core1 waiti_icg_en is 1, then only when core0 and core1 all in waiti will close
+         *  related clock
+         */
+        uint32_t reg_core1_waiti_icg_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cpu_waiti_ctrl0_reg_t;
+
+
+typedef struct {
+    volatile hp_sys_clkrst_clk_en0_reg_t clk_en0;
+    volatile hp_sys_clkrst_root_clk_ctrl0_reg_t root_clk_ctrl0;
+    volatile hp_sys_clkrst_root_clk_ctrl1_reg_t root_clk_ctrl1;
+    volatile hp_sys_clkrst_root_clk_ctrl2_reg_t root_clk_ctrl2;
+    volatile hp_sys_clkrst_root_clk_ctrl3_reg_t root_clk_ctrl3;
+    volatile hp_sys_clkrst_soc_clk_ctrl0_reg_t soc_clk_ctrl0;
+    volatile hp_sys_clkrst_soc_clk_ctrl1_reg_t soc_clk_ctrl1;
+    volatile hp_sys_clkrst_soc_clk_ctrl2_reg_t soc_clk_ctrl2;
+    volatile hp_sys_clkrst_soc_clk_ctrl3_reg_t soc_clk_ctrl3;
+    volatile hp_sys_clkrst_ref_clk_ctrl0_reg_t ref_clk_ctrl0;
+    volatile hp_sys_clkrst_ref_clk_ctrl1_reg_t ref_clk_ctrl1;
+    volatile hp_sys_clkrst_ref_clk_ctrl2_reg_t ref_clk_ctrl2;
+    volatile hp_sys_clkrst_peri_clk_ctrl00_reg_t peri_clk_ctrl00;
+    volatile hp_sys_clkrst_peri_clk_ctrl01_reg_t peri_clk_ctrl01;
+    volatile hp_sys_clkrst_peri_clk_ctrl02_reg_t peri_clk_ctrl02;
+    volatile hp_sys_clkrst_peri_clk_ctrl03_reg_t peri_clk_ctrl03;
+    volatile hp_sys_clkrst_peri_clk_ctrl10_reg_t peri_clk_ctrl10;
+    volatile hp_sys_clkrst_peri_clk_ctrl11_reg_t peri_clk_ctrl11;
+    volatile hp_sys_clkrst_peri_clk_ctrl12_reg_t peri_clk_ctrl12;
+    volatile hp_sys_clkrst_peri_clk_ctrl13_reg_t peri_clk_ctrl13;
+    volatile hp_sys_clkrst_peri_clk_ctrl14_reg_t peri_clk_ctrl14;
+    volatile hp_sys_clkrst_peri_clk_ctrl15_reg_t peri_clk_ctrl15;
+    volatile hp_sys_clkrst_peri_clk_ctrl16_reg_t peri_clk_ctrl16;
+    volatile hp_sys_clkrst_peri_clk_ctrl17_reg_t peri_clk_ctrl17;
+    volatile hp_sys_clkrst_peri_clk_ctrl18_reg_t peri_clk_ctrl18;
+    volatile hp_sys_clkrst_peri_clk_ctrl19_reg_t peri_clk_ctrl19;
+    volatile hp_sys_clkrst_peri_clk_ctrl110_reg_t peri_clk_ctrl110;
+    volatile hp_sys_clkrst_peri_clk_ctrl111_reg_t peri_clk_ctrl111;
+    volatile hp_sys_clkrst_peri_clk_ctrl112_reg_t peri_clk_ctrl112;
+    volatile hp_sys_clkrst_peri_clk_ctrl113_reg_t peri_clk_ctrl113;
+    volatile hp_sys_clkrst_peri_clk_ctrl114_reg_t peri_clk_ctrl114;
+    volatile hp_sys_clkrst_peri_clk_ctrl115_reg_t peri_clk_ctrl115;
+    volatile hp_sys_clkrst_peri_clk_ctrl116_reg_t peri_clk_ctrl116;
+    volatile hp_sys_clkrst_peri_clk_ctrl117_reg_t peri_clk_ctrl117;
+    volatile hp_sys_clkrst_peri_clk_ctrl118_reg_t peri_clk_ctrl118;
+    volatile hp_sys_clkrst_peri_clk_ctrl119_reg_t peri_clk_ctrl119;
+    volatile hp_sys_clkrst_peri_clk_ctrl120_reg_t peri_clk_ctrl120;
+    volatile hp_sys_clkrst_peri_clk_ctrl20_reg_t peri_clk_ctrl20;
+    volatile hp_sys_clkrst_peri_clk_ctrl21_reg_t peri_clk_ctrl21;
+    volatile hp_sys_clkrst_peri_clk_ctrl22_reg_t peri_clk_ctrl22;
+    volatile hp_sys_clkrst_peri_clk_ctrl23_reg_t peri_clk_ctrl23;
+    volatile hp_sys_clkrst_peri_clk_ctrl24_reg_t peri_clk_ctrl24;
+    volatile hp_sys_clkrst_peri_clk_ctrl25_reg_t peri_clk_ctrl25;
+    volatile hp_sys_clkrst_peri_clk_ctrl26_reg_t peri_clk_ctrl26;
+    volatile hp_sys_clkrst_peri_clk_ctrl27_reg_t peri_clk_ctrl27;
+    volatile hp_sys_clkrst_clk_force_on_ctrl0_reg_t clk_force_on_ctrl0;
+    volatile hp_sys_clkrst_dpa_ctrl0_reg_t dpa_ctrl0;
+    volatile hp_sys_clkrst_ana_pll_ctrl0_reg_t ana_pll_ctrl0;
+    volatile hp_sys_clkrst_hp_rst_en0_reg_t hp_rst_en0;
+    volatile hp_sys_clkrst_hp_rst_en1_reg_t hp_rst_en1;
+    volatile hp_sys_clkrst_hp_rst_en2_reg_t hp_rst_en2;
+    volatile hp_sys_clkrst_hp_force_norst0_reg_t hp_force_norst0;
+    volatile hp_sys_clkrst_hp_force_norst1_reg_t hp_force_norst1;
+    volatile hp_sys_clkrst_hpwdt_core0_rst_ctrl0_reg_t hpwdt_core0_rst_ctrl0;
+    volatile hp_sys_clkrst_hpwdt_core1_rst_ctrl0_reg_t hpwdt_core1_rst_ctrl0;
+    volatile hp_sys_clkrst_cpu_src_freq0_reg_t cpu_src_freq0;
+    volatile hp_sys_clkrst_cpu_clk_status0_reg_t cpu_clk_status0;
+    volatile hp_sys_clkrst_dbg_clk_ctrl0_reg_t dbg_clk_ctrl0;
+    volatile hp_sys_clkrst_dbg_clk_ctrl1_reg_t dbg_clk_ctrl1;
+    volatile hp_sys_clkrst_hpcore_wdt_reset_source0_reg_t hpcore_wdt_reset_source0;
+    volatile hp_sys_clkrst_axi_perf_mon_clkrst_ctrl0_reg_t axi_perf_mon_clkrst_ctrl0;
+    volatile hp_sys_clkrst_cpu_waiti_ctrl0_reg_t cpu_waiti_ctrl0;
+} hp_sys_clkrst_dev_t;
+
+extern hp_sys_clkrst_dev_t HP_SYS_CLKRST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_sys_clkrst_dev_t) == 0xf8, "Invalid size of hp_sys_clkrst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_system_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_reg.h
new file mode 100644
index 0000000000..81cff32012
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_reg.h
@@ -0,0 +1,2173 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_SYSTEM_VER_DATE_REG register
+ *  NA
+ */
+#define HP_SYSTEM_VER_DATE_REG (DR_REG_HP_SYS_BASE + 0x0)
+/** HP_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539296519;
+ *  NA
+ */
+#define HP_SYSTEM_REG_VER_DATE    0xFFFFFFFFU
+#define HP_SYSTEM_REG_VER_DATE_M  (HP_REG_VER_DATE_V << HP_REG_VER_DATE_S)
+#define HP_SYSTEM_REG_VER_DATE_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_VER_DATE_S  0
+
+/** HP_CLK_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CLK_EN_REG (DR_REG_HP_SYS_BASE + 0x4)
+/** HP_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_CLK_EN    (BIT(0))
+#define HP_SYSTEM_REG_CLK_EN_M  (HP_REG_CLK_EN_V << HP_REG_CLK_EN_S)
+#define HP_SYSTEM_REG_CLK_EN_V  0x00000001U
+#define HP_SYSTEM_REG_CLK_EN_S  0
+
+/** HP_CPU_INT_FROM_CPU_0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_REG (DR_REG_HP_SYS_BASE + 0x10)
+/** HP_CPU_INT_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_M  (HP_CPU_INT_FROM_CPU_0_V << HP_CPU_INT_FROM_CPU_0_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_S  0
+
+/** HP_CPU_INT_FROM_CPU_1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_REG (DR_REG_HP_SYS_BASE + 0x14)
+/** HP_CPU_INT_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_M  (HP_CPU_INT_FROM_CPU_1_V << HP_CPU_INT_FROM_CPU_1_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_S  0
+
+/** HP_CPU_INT_FROM_CPU_2_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_REG (DR_REG_HP_SYS_BASE + 0x18)
+/** HP_CPU_INT_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_M  (HP_CPU_INT_FROM_CPU_2_V << HP_CPU_INT_FROM_CPU_2_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_S  0
+
+/** HP_CPU_INT_FROM_CPU_3_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_REG (DR_REG_HP_SYS_BASE + 0x1c)
+/** HP_CPU_INT_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_M  (HP_CPU_INT_FROM_CPU_3_V << HP_CPU_INT_FROM_CPU_3_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_S  0
+
+/** HP_CACHE_CLK_CONFIG_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CACHE_CLK_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x20)
+/** HP_REG_L2_CACHE_CLK_ON : R/W; bitpos: [0]; default: 1;
+ *  l2 cache clk enable
+ */
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON    (BIT(0))
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_M  (HP_REG_L2_CACHE_CLK_ON_V << HP_REG_L2_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_S  0
+/** HP_REG_L1_D_CACHE_CLK_ON : R/W; bitpos: [1]; default: 1;
+ *  l1 dcahce clk enable
+ */
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON    (BIT(1))
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_M  (HP_REG_L1_D_CACHE_CLK_ON_V << HP_REG_L1_D_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_S  1
+/** HP_REG_L1_I1_CACHE_CLK_ON : R/W; bitpos: [4]; default: 1;
+ *  l1 icahce1 clk enable
+ */
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON    (BIT(4))
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_M  (HP_REG_L1_I1_CACHE_CLK_ON_V << HP_REG_L1_I1_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_S  4
+/** HP_REG_L1_I0_CACHE_CLK_ON : R/W; bitpos: [5]; default: 1;
+ *  l1 icahce0 clk enable
+ */
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON    (BIT(5))
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_M  (HP_REG_L1_I0_CACHE_CLK_ON_V << HP_REG_L1_I0_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_S  5
+
+/** HP_CACHE_RESET_CONFIG_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CACHE_RESET_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x24)
+/** HP_REG_L1_D_CACHE_RESET : R/W; bitpos: [1]; default: 0;
+ *  set 1 to reset l1 dcahce
+ */
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET    (BIT(1))
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET_M  (HP_REG_L1_D_CACHE_RESET_V << HP_REG_L1_D_CACHE_RESET_S)
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET_S  1
+/** HP_REG_L1_I1_CACHE_RESET : R/W; bitpos: [4]; default: 0;
+ *  set 1 to reset l1 icahce1
+ */
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET    (BIT(4))
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_M  (HP_REG_L1_I1_CACHE_RESET_V << HP_REG_L1_I1_CACHE_RESET_S)
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_S  4
+/** HP_REG_L1_I0_CACHE_RESET : R/W; bitpos: [5]; default: 0;
+ *  set 1 to reset l1 icahce0
+ */
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET    (BIT(5))
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_M  (HP_REG_L1_I0_CACHE_RESET_V << HP_REG_L1_I0_CACHE_RESET_S)
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_S  5
+
+/** HP_SYS_DMA_ADDR_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_SYS_DMA_ADDR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x2c)
+/** HP_REG_SYS_DMA_ADDR_SEL : R/W; bitpos: [0]; default: 0;
+ *  0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx
+ */
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL    (BIT(0))
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_M  (HP_REG_SYS_DMA_ADDR_SEL_V << HP_REG_SYS_DMA_ADDR_SEL_S)
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_V  0x00000001U
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_S  0
+
+/** HP_TCM_RAM_WRR_CONFIG_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RAM_WRR_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x34)
+/** HP_REG_TCM_RAM_IBUS0_WT : R/W; bitpos: [2:0]; default: 7;
+ *  weight value of ibus0
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_M  (HP_REG_TCM_RAM_IBUS0_WT_V << HP_REG_TCM_RAM_IBUS0_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_S  0
+/** HP_REG_TCM_RAM_IBUS1_WT : R/W; bitpos: [5:3]; default: 7;
+ *  weight value of ibus1
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_M  (HP_REG_TCM_RAM_IBUS1_WT_V << HP_REG_TCM_RAM_IBUS1_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_S  3
+/** HP_REG_TCM_RAM_IBUS2_WT : R/W; bitpos: [8:6]; default: 4;
+ *  weight value of ibus2
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_M  (HP_REG_TCM_RAM_IBUS2_WT_V << HP_REG_TCM_RAM_IBUS2_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_S  6
+/** HP_REG_TCM_RAM_IBUS3_WT : R/W; bitpos: [11:9]; default: 4;
+ *  weight value of ibus3
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_M  (HP_REG_TCM_RAM_IBUS3_WT_V << HP_REG_TCM_RAM_IBUS3_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_S  9
+/** HP_REG_TCM_RAM_DBUS0_WT : R/W; bitpos: [14:12]; default: 5;
+ *  weight value of dbus0
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_M  (HP_REG_TCM_RAM_DBUS0_WT_V << HP_REG_TCM_RAM_DBUS0_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_S  12
+/** HP_REG_TCM_RAM_DBUS1_WT : R/W; bitpos: [17:15]; default: 5;
+ *  weight value of dbus1
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_M  (HP_REG_TCM_RAM_DBUS1_WT_V << HP_REG_TCM_RAM_DBUS1_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_S  15
+/** HP_REG_TCM_RAM_DBUS2_WT : R/W; bitpos: [20:18]; default: 3;
+ *  weight value of dbus2
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_M  (HP_REG_TCM_RAM_DBUS2_WT_V << HP_REG_TCM_RAM_DBUS2_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_S  18
+/** HP_REG_TCM_RAM_DBUS3_WT : R/W; bitpos: [23:21]; default: 3;
+ *  weight value of dbus3
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_M  (HP_REG_TCM_RAM_DBUS3_WT_V << HP_REG_TCM_RAM_DBUS3_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_S  21
+/** HP_REG_TCM_RAM_DMA_WT : R/W; bitpos: [26:24]; default: 2;
+ *  weight value of dma
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_M  (HP_REG_TCM_RAM_DMA_WT_V << HP_REG_TCM_RAM_DMA_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_S  24
+/** HP_REG_TCM_RAM_WRR_HIGH : R/W; bitpos: [31]; default: 1;
+ *  enable weighted round robin arbitration
+ */
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH    (BIT(31))
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_M  (HP_REG_TCM_RAM_WRR_HIGH_V << HP_REG_TCM_RAM_WRR_HIGH_S)
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_S  31
+
+/** HP_TCM_SW_PARITY_BWE_MASK_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_SW_PARITY_BWE_MASK_REG (DR_REG_HP_SYS_BASE + 0x38)
+/** HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to mask tcm bwe parity code bit
+ */
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL    (BIT(0))
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_M  (HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL_V << HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL_S)
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_S  0
+
+/** HP_TCM_RAM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RAM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x3c)
+/** HP_REG_HP_TCM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  hp_tcm clk gatig force on
+ */
+#define HP_SYSTEM_REG_HP_TCM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_HP_TCM_CLK_FORCE_ON_M  (HP_REG_HP_TCM_CLK_FORCE_ON_V << HP_REG_HP_TCM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_HP_TCM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_HP_TCM_CLK_FORCE_ON_S  0
+
+/** HP_L2_ROM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_ROM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x40)
+/** HP_REG_L2_ROM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  l2_rom clk gating force on
+ */
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_M  (HP_REG_L2_ROM_CLK_FORCE_ON_V << HP_REG_L2_ROM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_S  0
+
+/** HP_PROBEA_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBEA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x50)
+/** HP_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+ *  module's probe_out[31:0] in a mode
+ */
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_M  (HP_REG_PROBE_A_MOD_SEL_V << HP_REG_PROBE_A_MOD_SEL_S)
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
+/** HP_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  This field is used to selec module's probe_out[31:0] as probe out in a mode
+ */
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (HP_REG_PROBE_A_TOP_SEL_V << HP_REG_PROBE_A_TOP_SEL_S)
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
+/** HP_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  This field is used to selec probe_out[31:16]
+ */
+#define HP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
+#define HP_SYSTEM_REG_PROBE_L_SEL_M  (HP_REG_PROBE_L_SEL_V << HP_REG_PROBE_L_SEL_S)
+#define HP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
+#define HP_SYSTEM_REG_PROBE_L_SEL_S  24
+/** HP_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This field is used to selec probe_out[31:16]
+ */
+#define HP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
+#define HP_SYSTEM_REG_PROBE_H_SEL_M  (HP_REG_PROBE_H_SEL_V << HP_REG_PROBE_H_SEL_S)
+#define HP_SYSTEM_REG_PROBE_H_SEL_V  0x00000003U
+#define HP_SYSTEM_REG_PROBE_H_SEL_S  26
+/** HP_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to enable global debug probe in hp system.
+ */
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN    (BIT(28))
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_M  (HP_REG_PROBE_GLOBAL_EN_V << HP_REG_PROBE_GLOBAL_EN_S)
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_V  0x00000001U
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_S  28
+
+/** HP_PROBEB_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBEB_CTRL_REG (DR_REG_HP_SYS_BASE + 0x54)
+/** HP_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+ *  module's probe_out[31:0] in b mode.
+ */
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_M  (HP_REG_PROBE_B_MOD_SEL_V << HP_REG_PROBE_B_MOD_SEL_S)
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
+/** HP_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
+ */
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (HP_REG_PROBE_B_TOP_SEL_V << HP_REG_PROBE_B_TOP_SEL_S)
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_V  0x000000FFU
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_S  16
+/** HP_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
+ *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
+ */
+#define HP_SYSTEM_REG_PROBE_B_EN    (BIT(24))
+#define HP_SYSTEM_REG_PROBE_B_EN_M  (HP_REG_PROBE_B_EN_V << HP_REG_PROBE_B_EN_S)
+#define HP_SYSTEM_REG_PROBE_B_EN_V  0x00000001U
+#define HP_SYSTEM_REG_PROBE_B_EN_S  24
+
+/** HP_PROBE_OUT_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBE_OUT_REG (DR_REG_HP_SYS_BASE + 0x5c)
+/** HP_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_PROBE_TOP_OUT    0xFFFFFFFFU
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_M  (HP_REG_PROBE_TOP_OUT_V << HP_REG_PROBE_TOP_OUT_S)
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_S  0
+
+/** HP_L2_MEM_RAM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RAM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x60)
+/** HP_REG_L2_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  l2ram clk_gating force on
+ */
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_M  (HP_REG_L2_MEM_CLK_FORCE_ON_V << HP_REG_L2_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_S  0
+
+/** HP_CPU_CORESTALLED_ST_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_CORESTALLED_ST_REG (DR_REG_HP_SYS_BASE + 0x64)
+/** HP_REG_CORE0_CORESTALLED_ST : RO; bitpos: [0]; default: 0;
+ *  hp core0 corestalled status
+ */
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST    (BIT(0))
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_M  (HP_REG_CORE0_CORESTALLED_ST_V << HP_REG_CORE0_CORESTALLED_ST_S)
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_V  0x00000001U
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_S  0
+/** HP_REG_CORE1_CORESTALLED_ST : RO; bitpos: [1]; default: 0;
+ *  hp core1 corestalled status
+ */
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST    (BIT(1))
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_M  (HP_REG_CORE1_CORESTALLED_ST_V << HP_REG_CORE1_CORESTALLED_ST_S)
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_V  0x00000001U
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_S  1
+
+/** HP_CRYPTO_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CRYPTO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70)
+/** HP_REG_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_REG_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_REG_ENABLE_SPI_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+/** HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/** HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/** HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+
+/** HP_GPIO_O_HOLD_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HOLD_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x74)
+/** HP_REG_GPIO_0_HOLD_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  hold control for gpio47~16
+ */
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_M  (HP_REG_GPIO_0_HOLD_LOW_V << HP_REG_GPIO_0_HOLD_LOW_S)
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_S  0
+
+/** HP_GPIO_O_HOLD_CTRL1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HOLD_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x78)
+/** HP_REG_GPIO_0_HOLD_HIGH : R/W; bitpos: [8:0]; default: 0;
+ *  hold control for gpio56~48
+ */
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH    0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_M  (HP_REG_GPIO_0_HOLD_HIGH_V << HP_REG_GPIO_0_HOLD_HIGH_S)
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_V  0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_S  0
+
+/** HP_SYS_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_SYS_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0x7c)
+/** HP_REG_HP_SYS_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_EN_M  (HP_REG_HP_SYS_RDN_ECO_EN_V << HP_REG_HP_SYS_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_EN_S  0
+/** HP_REG_HP_SYS_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_RESULT_M  (HP_REG_HP_SYS_RDN_ECO_RESULT_V << HP_REG_HP_SYS_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_RESULT_S  1
+
+/** HP_CACHE_APB_POSTW_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CACHE_APB_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x80)
+/** HP_REG_CACHE_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  cache apb register interface post write enable, 1 will speed up write, but will
+ *  take some time to update value to register
+ */
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN    (BIT(0))
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_M  (HP_REG_CACHE_APB_POSTW_EN_V << HP_REG_CACHE_APB_POSTW_EN_S)
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_S  0
+
+/** HP_L2_MEM_SUBSIZE_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_SUBSIZE_REG (DR_REG_HP_SYS_BASE + 0x84)
+/** HP_REG_L2_MEM_SUB_BLKSIZE : R/W; bitpos: [1:0]; default: 0;
+ *  l2mem sub block size 00=>32 01=>64 10=>128 11=>256
+ */
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE    0x00000003U
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_M  (HP_REG_L2_MEM_SUB_BLKSIZE_V << HP_REG_L2_MEM_SUB_BLKSIZE_S)
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_V  0x00000003U
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_S  0
+
+/** HP_L2_MEM_INT_RAW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x9c)
+/** HP_REG_L2_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  intr triggered when two bit error detected and corrected from ecc
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_M  (HP_REG_L2_MEM_ECC_ERR_INT_RAW_V << HP_REG_L2_MEM_ECC_ERR_INT_RAW_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_S  0
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds
+ *  0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_S  1
+/** HP_REG_L2_MEM_ERR_RESP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  intr triggered when err response occurs
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_M  (HP_REG_L2_MEM_ERR_RESP_INT_RAW_V << HP_REG_L2_MEM_ERR_RESP_INT_RAW_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_S  2
+
+/** HP_L2_MEM_INT_ST_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_ST_REG (DR_REG_HP_SYS_BASE + 0xa0)
+/** HP_REG_L2_MEM_ECC_ERR_INT_ST : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_M  (HP_REG_L2_MEM_ECC_ERR_INT_ST_V << HP_REG_L2_MEM_ECC_ERR_INT_ST_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_S  0
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_ST_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_ST_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_S  1
+/** HP_REG_L2_MEM_ERR_RESP_INT_ST : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_M  (HP_REG_L2_MEM_ERR_RESP_INT_ST_V << HP_REG_L2_MEM_ERR_RESP_INT_ST_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_S  2
+
+/** HP_L2_MEM_INT_ENA_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0xa4)
+/** HP_REG_L2_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_M  (HP_REG_L2_MEM_ECC_ERR_INT_ENA_V << HP_REG_L2_MEM_ECC_ERR_INT_ENA_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_S  0
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_S  1
+/** HP_REG_L2_MEM_ERR_RESP_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_M  (HP_REG_L2_MEM_ERR_RESP_INT_ENA_V << HP_REG_L2_MEM_ERR_RESP_INT_ENA_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_S  2
+
+/** HP_L2_MEM_INT_CLR_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0xa8)
+/** HP_REG_L2_MEM_ECC_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_M  (HP_REG_L2_MEM_ECC_ERR_INT_CLR_V << HP_REG_L2_MEM_ECC_ERR_INT_CLR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_S  0
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_S  1
+/** HP_REG_L2_MEM_ERR_RESP_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_M  (HP_REG_L2_MEM_ERR_RESP_INT_CLR_V << HP_REG_L2_MEM_ERR_RESP_INT_CLR_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_S  2
+
+/** HP_L2_MEM_L2_RAM_ECC_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_L2_RAM_ECC_REG (DR_REG_HP_SYS_BASE + 0xac)
+/** HP_REG_L2_RAM_UNIT0_ECC_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_M  (HP_REG_L2_RAM_UNIT0_ECC_EN_V << HP_REG_L2_RAM_UNIT0_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_S  0
+/** HP_REG_L2_RAM_UNIT1_ECC_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN    (BIT(1))
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_M  (HP_REG_L2_RAM_UNIT1_ECC_EN_V << HP_REG_L2_RAM_UNIT1_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_S  1
+/** HP_REG_L2_RAM_UNIT2_ECC_EN : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN    (BIT(2))
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_M  (HP_REG_L2_RAM_UNIT2_ECC_EN_V << HP_REG_L2_RAM_UNIT2_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_S  2
+/** HP_REG_L2_RAM_UNIT3_ECC_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN    (BIT(3))
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_M  (HP_REG_L2_RAM_UNIT3_ECC_EN_V << HP_REG_L2_RAM_UNIT3_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_S  3
+/** HP_REG_L2_RAM_UNIT4_ECC_EN : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN    (BIT(4))
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_M  (HP_REG_L2_RAM_UNIT4_ECC_EN_V << HP_REG_L2_RAM_UNIT4_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_S  4
+/** HP_REG_L2_RAM_UNIT5_ECC_EN : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN    (BIT(5))
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_M  (HP_REG_L2_RAM_UNIT5_ECC_EN_V << HP_REG_L2_RAM_UNIT5_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_S  5
+
+/** HP_L2_MEM_INT_RECORD0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_RECORD0_REG (DR_REG_HP_SYS_BASE + 0xb0)
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR : RO; bitpos: [20:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR    0x001FFFFFU
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_V  0x001FFFFFU
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_S  0
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_WE : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE    (BIT(21))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_WE_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_WE_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_S  21
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER : RO; bitpos: [24:22]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER    0x00000007U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_V  0x00000007U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_S  22
+
+/** HP_L2_MEM_INT_RECORD1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_RECORD1_REG (DR_REG_HP_SYS_BASE + 0xb4)
+/** HP_REG_L2_MEM_ECC_ERR_INT_ADDR : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR    0x00007FFFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_M  (HP_REG_L2_MEM_ECC_ERR_INT_ADDR_V << HP_REG_L2_MEM_ECC_ERR_INT_ADDR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_V  0x00007FFFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_S  0
+/** HP_REG_L2_MEM_ECC_ONE_BIT_ERR : RO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR    (BIT(15))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_M  (HP_REG_L2_MEM_ECC_ONE_BIT_ERR_V << HP_REG_L2_MEM_ECC_ONE_BIT_ERR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_S  15
+/** HP_REG_L2_MEM_ECC_TWO_BIT_ERR : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR    (BIT(16))
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_M  (HP_REG_L2_MEM_ECC_TWO_BIT_ERR_V << HP_REG_L2_MEM_ECC_TWO_BIT_ERR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_S  16
+/** HP_REG_L2_MEM_ECC_ERR_BIT : RO; bitpos: [25:17]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT    0x000001FFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_M  (HP_REG_L2_MEM_ECC_ERR_BIT_V << HP_REG_L2_MEM_ECC_ERR_BIT_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_V  0x000001FFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_S  17
+/** HP_REG_L2_CACHE_ERR_BANK : RO; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK    (BIT(26))
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_M  (HP_REG_L2_CACHE_ERR_BANK_V << HP_REG_L2_CACHE_ERR_BANK_S)
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_V  0x00000001U
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_S  26
+
+/** HP_L2_MEM_L2_CACHE_ECC_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_L2_CACHE_ECC_REG (DR_REG_HP_SYS_BASE + 0xc4)
+/** HP_REG_L2_CACHE_ECC_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_M  (HP_REG_L2_CACHE_ECC_EN_V << HP_REG_L2_CACHE_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_S  0
+
+/** HP_L1CACHE_BUS0_ID_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L1CACHE_BUS0_ID_REG (DR_REG_HP_SYS_BASE + 0xc8)
+/** HP_REG_L1_CACHE_BUS0_ID : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID    0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_M  (HP_REG_L1_CACHE_BUS0_ID_V << HP_REG_L1_CACHE_BUS0_ID_S)
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_V  0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_S  0
+
+/** HP_L1CACHE_BUS1_ID_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L1CACHE_BUS1_ID_REG (DR_REG_HP_SYS_BASE + 0xcc)
+/** HP_REG_L1_CACHE_BUS1_ID : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID    0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_M  (HP_REG_L1_CACHE_BUS1_ID_V << HP_REG_L1_CACHE_BUS1_ID_S)
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_V  0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_S  0
+
+/** HP_L2_MEM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0xd8)
+/** HP_REG_L2_MEM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_M  (HP_REG_L2_MEM_RDN_ECO_EN_V << HP_REG_L2_MEM_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_S  0
+/** HP_REG_L2_MEM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_M  (HP_REG_L2_MEM_RDN_ECO_RESULT_V << HP_REG_L2_MEM_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_S  1
+
+/** HP_L2_MEM_RDN_ECO_LOW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RDN_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0xdc)
+/** HP_REG_L2_MEM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_M  (HP_REG_L2_MEM_RDN_ECO_LOW_V << HP_REG_L2_MEM_RDN_ECO_LOW_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_S  0
+
+/** HP_L2_MEM_RDN_ECO_HIGH_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RDN_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0xe0)
+/** HP_REG_L2_MEM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_M  (HP_REG_L2_MEM_RDN_ECO_HIGH_V << HP_REG_L2_MEM_RDN_ECO_HIGH_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_S  0
+
+/** HP_TCM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0xe4)
+/** HP_REG_HP_TCM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_EN_M  (HP_REG_HP_TCM_RDN_ECO_EN_V << HP_REG_HP_TCM_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_EN_S  0
+/** HP_REG_HP_TCM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_RESULT_M  (HP_REG_HP_TCM_RDN_ECO_RESULT_V << HP_REG_HP_TCM_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_RESULT_S  1
+
+/** HP_TCM_RDN_ECO_LOW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0xe8)
+/** HP_REG_HP_TCM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_LOW_M  (HP_REG_HP_TCM_RDN_ECO_LOW_V << HP_REG_HP_TCM_RDN_ECO_LOW_S)
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_LOW_S  0
+
+/** HP_TCM_RDN_ECO_HIGH_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0xec)
+/** HP_REG_HP_TCM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_HIGH_M  (HP_REG_HP_TCM_RDN_ECO_HIGH_V << HP_REG_HP_TCM_RDN_ECO_HIGH_S)
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_HIGH_S  0
+
+/** HP_GPIO_DED_HOLD_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_DED_HOLD_CTRL_REG (DR_REG_HP_SYS_BASE + 0xf0)
+/** HP_REG_GPIO_DED_HOLD : R/W; bitpos: [25:0]; default: 0;
+ *  hold control for gpio63~56
+ */
+#define HP_SYSTEM_REG_GPIO_DED_HOLD    0x03FFFFFFU
+#define HP_SYSTEM_REG_GPIO_DED_HOLD_M  (HP_REG_GPIO_DED_HOLD_V << HP_REG_GPIO_DED_HOLD_S)
+#define HP_SYSTEM_REG_GPIO_DED_HOLD_V  0x03FFFFFFU
+#define HP_SYSTEM_REG_GPIO_DED_HOLD_S  0
+
+/** HP_L2_MEM_SW_ECC_BWE_MASK_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_SW_ECC_BWE_MASK_REG (DR_REG_HP_SYS_BASE + 0xf4)
+/** HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to mask bwe hamming code bit
+ */
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_M  (HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_V << HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_S)
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_S  0
+
+/** HP_USB20OTG_MEM_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_USB20OTG_MEM_CTRL_REG (DR_REG_HP_SYS_BASE + 0xf8)
+/** HP_REG_USB20_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_M  (HP_REG_USB20_MEM_CLK_FORCE_ON_V << HP_REG_USB20_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_S  0
+
+/** HP_TCM_INT_RAW_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0xfc)
+/** HP_TCM_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_M  (HP_TCM_PARITY_ERR_INT_RAW_V << HP_TCM_PARITY_ERR_INT_RAW_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_S  31
+
+/** HP_TCM_INT_ST_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x100)
+/** HP_TCM_PARITY_ERR_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_M  (HP_TCM_PARITY_ERR_INT_ST_V << HP_TCM_PARITY_ERR_INT_ST_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_S  31
+
+/** HP_TCM_INT_ENA_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x104)
+/** HP_TCM_PARITY_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_M  (HP_TCM_PARITY_ERR_INT_ENA_V << HP_TCM_PARITY_ERR_INT_ENA_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_S  31
+
+/** HP_TCM_INT_CLR_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x108)
+/** HP_TCM_PARITY_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_M  (HP_TCM_PARITY_ERR_INT_CLR_V << HP_TCM_PARITY_ERR_INT_CLR_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_S  31
+
+/** HP_TCM_PARITY_INT_RECORD_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_INT_RECORD_REG (DR_REG_HP_SYS_BASE + 0x10c)
+/** HP_TCM_PARITY_ERR_INT_ADDR : RO; bitpos: [12:0]; default: 0;
+ *  hp tcm_parity_err_addr
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR    0x00001FFFU
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_M  (HP_TCM_PARITY_ERR_INT_ADDR_V << HP_TCM_PARITY_ERR_INT_ADDR_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_V  0x00001FFFU
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_S  0
+
+/** HP_L1_CACHE_PWR_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L1_CACHE_PWR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x110)
+/** HP_REG_L1_CACHE_MEM_FO : R/W; bitpos: [5:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO    0x0000003FU
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_M  (HP_REG_L1_CACHE_MEM_FO_V << HP_REG_L1_CACHE_MEM_FO_S)
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_V  0x0000003FU
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_S  0
+
+/** HP_L2_CACHE_PWR_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_CACHE_PWR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x114)
+/** HP_REG_L2_CACHE_MEM_FO : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO    0x00000003U
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_M  (HP_REG_L2_CACHE_MEM_FO_V << HP_REG_L2_CACHE_MEM_FO_S)
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_V  0x00000003U
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_S  0
+
+/** HP_CPU_WAITI_CONF_REG register
+ *  CPU_WAITI configuration register
+ */
+#define HP_SYSTEM_CPU_WAITI_CONF_REG (DR_REG_HP_SYS_BASE + 0x118)
+/** HP_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to force cpu_waiti_clk enable.
+ */
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (HP_CPU_WAIT_MODE_FORCE_ON_V << HP_CPU_WAIT_MODE_FORCE_ON_S)
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  0
+/** HP_CPU_WAITI_DELAY_NUM : R/W; bitpos: [4:1]; default: 0;
+ *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+ *  will close
+ */
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000FU
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_M  (HP_CPU_WAITI_DELAY_NUM_V << HP_CPU_WAITI_DELAY_NUM_S)
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_V  0x0000000FU
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_S  1
+
+/** HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG register
+ *  Core Debug runstall configure register
+ */
+#define HP_SYSTEM_SYS_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x11c)
+/** HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
+ */
+#define HP_SYSTEM_SYS_CORE_DEBUG_RUNSTALL_ENABLE    (BIT(0))
+#define HP_SYSTEM_SYS_CORE_DEBUG_RUNSTALL_ENABLE_M  (HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S)
+#define HP_SYSTEM_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V  0x00000001U
+#define HP_SYSTEM_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S  0
+
+/** HP_CORE_AHB_TIMEOUT_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x120)
+/** HP_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 ahb timeout handle
+ */
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_M  (HP_CORE_AHB_TIMEOUT_EN_V << HP_CORE_AHB_TIMEOUT_EN_S)
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_S  0
+/** HP_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 ahb bus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_M  (HP_CORE_AHB_TIMEOUT_THRES_V << HP_CORE_AHB_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_S  1
+
+/** HP_CORE_IBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x124)
+/** HP_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 ibus timeout handle
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_M  (HP_CORE_IBUS_TIMEOUT_EN_V << HP_CORE_IBUS_TIMEOUT_EN_S)
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_S  0
+/** HP_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 ibus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_M  (HP_CORE_IBUS_TIMEOUT_THRES_V << HP_CORE_IBUS_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_S  1
+
+/** HP_CORE_DBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x128)
+/** HP_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 dbus timeout handle
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_M  (HP_CORE_DBUS_TIMEOUT_EN_V << HP_CORE_DBUS_TIMEOUT_EN_S)
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_S  0
+/** HP_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 dbus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_M  (HP_CORE_DBUS_TIMEOUT_THRES_V << HP_CORE_DBUS_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_S  1
+
+/** HP_ICM_CPU_H2X_CFG_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_ICM_CPU_H2X_CFG_REG (DR_REG_HP_SYS_BASE + 0x138)
+/** HP_CPU_ICM_H2X_POST_WR_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN    (BIT(0))
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_M  (HP_CPU_ICM_H2X_POST_WR_EN_V << HP_CPU_ICM_H2X_POST_WR_EN_S)
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_S  0
+/** HP_CPU_ICM_H2X_CUT_THROUGH_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN    (BIT(1))
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_M  (HP_CPU_ICM_H2X_CUT_THROUGH_EN_V << HP_CPU_ICM_H2X_CUT_THROUGH_EN_S)
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_S  1
+/** HP_CPU_ICM_H2X_BRIDGE_BUSY : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY    (BIT(2))
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_M  (HP_CPU_ICM_H2X_BRIDGE_BUSY_V << HP_CPU_ICM_H2X_BRIDGE_BUSY_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_S  2
+
+/** HP_PERI1_APB_POSTW_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x13c)
+/** HP_PERI1_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  hp_peri1 apb register interface post write enable, 1 will speed up write, but will
+ *  take some time to update value to register
+ */
+#define HP_SYSTEM_PERI1_APB_POSTW_EN    (BIT(0))
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_M  (HP_PERI1_APB_POSTW_EN_V << HP_PERI1_APB_POSTW_EN_S)
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_S  0
+
+/** HP_BITSCRAMBLER_PERI_SEL_REG register
+ *  Bitscrambler Peri Sel
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_SYS_BASE + 0x140)
+/** HP_BITSCRAMBLER_PERI_RX_SEL : R/W; bitpos: [3:0]; default: 15;
+ *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler: 4'h0
+ *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+ *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+ *  else : none
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL    0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_M  (HP_BITSCRAMBLER_PERI_RX_SEL_V << HP_BITSCRAMBLER_PERI_RX_SEL_S)
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V  0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S  0
+/** HP_BITSCRAMBLER_PERI_TX_SEL : R/W; bitpos: [7:4]; default: 15;
+ *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler: 4'h0
+ *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+ *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+ *  else : none
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL    0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_M  (HP_BITSCRAMBLER_PERI_TX_SEL_V << HP_BITSCRAMBLER_PERI_TX_SEL_S)
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_V  0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_S  4
+
+/** HP_SYS_APB_SYNC_POSTW_EN_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_APB_SYNC_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x144)
+/** HP_SYS_GMAC_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_APB_POSTW_EN    (BIT(0))
+#define HP_SYSTEM_SYS_GMAC_APB_POSTW_EN_M  (HP_SYS_GMAC_APB_POSTW_EN_V << HP_SYS_GMAC_APB_POSTW_EN_S)
+#define HP_SYSTEM_SYS_GMAC_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_GMAC_APB_POSTW_EN_S  0
+/** HP_SYS_DSI_HOST_APB_POSTW_EN : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_DSI_HOST_APB_POSTW_EN    (BIT(1))
+#define HP_SYSTEM_SYS_DSI_HOST_APB_POSTW_EN_M  (HP_SYS_DSI_HOST_APB_POSTW_EN_V << HP_SYS_DSI_HOST_APB_POSTW_EN_S)
+#define HP_SYSTEM_SYS_DSI_HOST_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_DSI_HOST_APB_POSTW_EN_S  1
+/** HP_SYS_CSI_HOST_APB_SYNC_POSTW_EN : R/W; bitpos: [2]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_CSI_HOST_APB_SYNC_POSTW_EN    (BIT(2))
+#define HP_SYSTEM_SYS_CSI_HOST_APB_SYNC_POSTW_EN_M  (HP_SYS_CSI_HOST_APB_SYNC_POSTW_EN_V << HP_SYS_CSI_HOST_APB_SYNC_POSTW_EN_S)
+#define HP_SYSTEM_SYS_CSI_HOST_APB_SYNC_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_CSI_HOST_APB_SYNC_POSTW_EN_S  2
+/** HP_SYS_CSI_HOST_APB_ASYNC_POSTW_EN : R/W; bitpos: [3]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_CSI_HOST_APB_ASYNC_POSTW_EN    (BIT(3))
+#define HP_SYSTEM_SYS_CSI_HOST_APB_ASYNC_POSTW_EN_M  (HP_SYS_CSI_HOST_APB_ASYNC_POSTW_EN_V << HP_SYS_CSI_HOST_APB_ASYNC_POSTW_EN_S)
+#define HP_SYSTEM_SYS_CSI_HOST_APB_ASYNC_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_CSI_HOST_APB_ASYNC_POSTW_EN_S  3
+
+/** HP_SYS_GDMA_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GDMA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x148)
+/** HP_SYS_DEBUG_CH_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_DEBUG_CH_NUM    0x00000003U
+#define HP_SYSTEM_SYS_DEBUG_CH_NUM_M  (HP_SYS_DEBUG_CH_NUM_V << HP_SYS_DEBUG_CH_NUM_S)
+#define HP_SYSTEM_SYS_DEBUG_CH_NUM_V  0x00000003U
+#define HP_SYSTEM_SYS_DEBUG_CH_NUM_S  0
+
+/** HP_SYS_GMAC_CTRL0_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x14c)
+/** HP_SYS_PTP_PPS : RO; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PTP_PPS    (BIT(0))
+#define HP_SYSTEM_SYS_PTP_PPS_M  (HP_SYS_PTP_PPS_V << HP_SYS_PTP_PPS_S)
+#define HP_SYSTEM_SYS_PTP_PPS_V  0x00000001U
+#define HP_SYSTEM_SYS_PTP_PPS_S  0
+/** HP_SYS_SBD_FLOWCTRL : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_SBD_FLOWCTRL    (BIT(1))
+#define HP_SYSTEM_SYS_SBD_FLOWCTRL_M  (HP_SYS_SBD_FLOWCTRL_V << HP_SYS_SBD_FLOWCTRL_S)
+#define HP_SYSTEM_SYS_SBD_FLOWCTRL_V  0x00000001U
+#define HP_SYSTEM_SYS_SBD_FLOWCTRL_S  1
+/** HP_SYS_PHY_INTF_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_INTF_SEL    0x00000007U
+#define HP_SYSTEM_SYS_PHY_INTF_SEL_M  (HP_SYS_PHY_INTF_SEL_V << HP_SYS_PHY_INTF_SEL_S)
+#define HP_SYSTEM_SYS_PHY_INTF_SEL_V  0x00000007U
+#define HP_SYSTEM_SYS_PHY_INTF_SEL_S  2
+/** HP_SYS_GMAC_MEM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_MEM_CLK_FORCE_ON    (BIT(5))
+#define HP_SYSTEM_SYS_GMAC_MEM_CLK_FORCE_ON_M  (HP_SYS_GMAC_MEM_CLK_FORCE_ON_V << HP_SYS_GMAC_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_SYS_GMAC_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_SYS_GMAC_MEM_CLK_FORCE_ON_S  5
+/** HP_SYS_GMAC_RST_CLK_TX_N : RO; bitpos: [6]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_TX_N    (BIT(6))
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_TX_N_M  (HP_SYS_GMAC_RST_CLK_TX_N_V << HP_SYS_GMAC_RST_CLK_TX_N_S)
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_TX_N_V  0x00000001U
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_TX_N_S  6
+/** HP_SYS_GMAC_RST_CLK_RX_N : RO; bitpos: [7]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_RX_N    (BIT(7))
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_RX_N_M  (HP_SYS_GMAC_RST_CLK_RX_N_V << HP_SYS_GMAC_RST_CLK_RX_N_S)
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_RX_N_V  0x00000001U
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_RX_N_S  7
+
+/** HP_SYS_GMAC_CTRL1_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x150)
+/** HP_SYS_PTP_TIMESTAMP_L : RO; bitpos: [31:0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_L    0xFFFFFFFFU
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_L_M  (HP_SYS_PTP_TIMESTAMP_L_V << HP_SYS_PTP_TIMESTAMP_L_S)
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_L_V  0xFFFFFFFFU
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_L_S  0
+
+/** HP_SYS_GMAC_CTRL2_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_CTRL2_REG (DR_REG_HP_SYS_BASE + 0x154)
+/** HP_SYS_PTP_TIMESTAMP_H : RO; bitpos: [31:0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_H    0xFFFFFFFFU
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_H_M  (HP_SYS_PTP_TIMESTAMP_H_V << HP_SYS_PTP_TIMESTAMP_H_S)
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_H_V  0xFFFFFFFFU
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_H_S  0
+
+/** HP_SYS_VPU_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_VPU_CTRL_REG (DR_REG_HP_SYS_BASE + 0x158)
+/** HP_SYS_PPA_LSLP_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PPA_LSLP_MEM_PD    (BIT(0))
+#define HP_SYSTEM_SYS_PPA_LSLP_MEM_PD_M  (HP_SYS_PPA_LSLP_MEM_PD_V << HP_SYS_PPA_LSLP_MEM_PD_S)
+#define HP_SYSTEM_SYS_PPA_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_SYS_PPA_LSLP_MEM_PD_S  0
+/** HP_SYS_JPEG_SDSLP_MEM_PD : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_JPEG_SDSLP_MEM_PD    (BIT(1))
+#define HP_SYSTEM_SYS_JPEG_SDSLP_MEM_PD_M  (HP_SYS_JPEG_SDSLP_MEM_PD_V << HP_SYS_JPEG_SDSLP_MEM_PD_S)
+#define HP_SYSTEM_SYS_JPEG_SDSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_SYS_JPEG_SDSLP_MEM_PD_S  1
+/** HP_SYS_JPEG_LSLP_MEM_PD : R/W; bitpos: [2]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_JPEG_LSLP_MEM_PD    (BIT(2))
+#define HP_SYSTEM_SYS_JPEG_LSLP_MEM_PD_M  (HP_SYS_JPEG_LSLP_MEM_PD_V << HP_SYS_JPEG_LSLP_MEM_PD_S)
+#define HP_SYSTEM_SYS_JPEG_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_SYS_JPEG_LSLP_MEM_PD_S  2
+/** HP_SYS_JPEG_DSLP_MEM_PD : R/W; bitpos: [3]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_JPEG_DSLP_MEM_PD    (BIT(3))
+#define HP_SYSTEM_SYS_JPEG_DSLP_MEM_PD_M  (HP_SYS_JPEG_DSLP_MEM_PD_V << HP_SYS_JPEG_DSLP_MEM_PD_S)
+#define HP_SYSTEM_SYS_JPEG_DSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_SYS_JPEG_DSLP_MEM_PD_S  3
+/** HP_SYS_DMA2D_LSLP_MEM_PD : R/W; bitpos: [4]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_DMA2D_LSLP_MEM_PD    (BIT(4))
+#define HP_SYSTEM_SYS_DMA2D_LSLP_MEM_PD_M  (HP_SYS_DMA2D_LSLP_MEM_PD_V << HP_SYS_DMA2D_LSLP_MEM_PD_S)
+#define HP_SYSTEM_SYS_DMA2D_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_SYS_DMA2D_LSLP_MEM_PD_S  4
+
+/** HP_SYS_USBOTG20_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_USBOTG20_CTRL_REG (DR_REG_HP_SYS_BASE + 0x15c)
+/** HP_SYS_OTG_PHY_TEST_DONE : RO; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_OTG_PHY_TEST_DONE    (BIT(0))
+#define HP_SYSTEM_SYS_OTG_PHY_TEST_DONE_M  (HP_SYS_OTG_PHY_TEST_DONE_V << HP_SYS_OTG_PHY_TEST_DONE_S)
+#define HP_SYSTEM_SYS_OTG_PHY_TEST_DONE_V  0x00000001U
+#define HP_SYSTEM_SYS_OTG_PHY_TEST_DONE_S  0
+/** HP_SYS_USB_MEM_AUX_CTRL : R/W; bitpos: [14:1]; default: 4896;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_USB_MEM_AUX_CTRL    0x00003FFFU
+#define HP_SYSTEM_SYS_USB_MEM_AUX_CTRL_M  (HP_SYS_USB_MEM_AUX_CTRL_V << HP_SYS_USB_MEM_AUX_CTRL_S)
+#define HP_SYSTEM_SYS_USB_MEM_AUX_CTRL_V  0x00003FFFU
+#define HP_SYSTEM_SYS_USB_MEM_AUX_CTRL_S  1
+/** HP_SYS_PHY_SUSPENDM : R/W; bitpos: [15]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_SUSPENDM    (BIT(15))
+#define HP_SYSTEM_SYS_PHY_SUSPENDM_M  (HP_SYS_PHY_SUSPENDM_V << HP_SYS_PHY_SUSPENDM_S)
+#define HP_SYSTEM_SYS_PHY_SUSPENDM_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_SUSPENDM_S  15
+/** HP_SYS_PHY_SUSPEND_FORCE_EN : R/W; bitpos: [16]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_SUSPEND_FORCE_EN    (BIT(16))
+#define HP_SYSTEM_SYS_PHY_SUSPEND_FORCE_EN_M  (HP_SYS_PHY_SUSPEND_FORCE_EN_V << HP_SYS_PHY_SUSPEND_FORCE_EN_S)
+#define HP_SYSTEM_SYS_PHY_SUSPEND_FORCE_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_SUSPEND_FORCE_EN_S  16
+/** HP_SYS_PHY_RSTN : R/W; bitpos: [17]; default: 1;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_RSTN    (BIT(17))
+#define HP_SYSTEM_SYS_PHY_RSTN_M  (HP_SYS_PHY_RSTN_V << HP_SYS_PHY_RSTN_S)
+#define HP_SYSTEM_SYS_PHY_RSTN_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_RSTN_S  17
+/** HP_SYS_PHY_RESET_FORCE_EN : R/W; bitpos: [18]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_RESET_FORCE_EN    (BIT(18))
+#define HP_SYSTEM_SYS_PHY_RESET_FORCE_EN_M  (HP_SYS_PHY_RESET_FORCE_EN_V << HP_SYS_PHY_RESET_FORCE_EN_S)
+#define HP_SYSTEM_SYS_PHY_RESET_FORCE_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_RESET_FORCE_EN_S  18
+/** HP_SYS_PHY_PLL_FORCE_EN : R/W; bitpos: [19]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_PLL_FORCE_EN    (BIT(19))
+#define HP_SYSTEM_SYS_PHY_PLL_FORCE_EN_M  (HP_SYS_PHY_PLL_FORCE_EN_V << HP_SYS_PHY_PLL_FORCE_EN_S)
+#define HP_SYSTEM_SYS_PHY_PLL_FORCE_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_PLL_FORCE_EN_S  19
+/** HP_SYS_PHY_PLL_EN : R/W; bitpos: [20]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_PLL_EN    (BIT(20))
+#define HP_SYSTEM_SYS_PHY_PLL_EN_M  (HP_SYS_PHY_PLL_EN_V << HP_SYS_PHY_PLL_EN_S)
+#define HP_SYSTEM_SYS_PHY_PLL_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_PLL_EN_S  20
+/** HP_SYS_OTG_SUSPENDM : R/W; bitpos: [21]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_OTG_SUSPENDM    (BIT(21))
+#define HP_SYSTEM_SYS_OTG_SUSPENDM_M  (HP_SYS_OTG_SUSPENDM_V << HP_SYS_OTG_SUSPENDM_S)
+#define HP_SYSTEM_SYS_OTG_SUSPENDM_V  0x00000001U
+#define HP_SYSTEM_SYS_OTG_SUSPENDM_S  21
+/** HP_SYS_OTG_PHY_TXBITSTUFF_EN : R/W; bitpos: [22]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_OTG_PHY_TXBITSTUFF_EN    (BIT(22))
+#define HP_SYSTEM_SYS_OTG_PHY_TXBITSTUFF_EN_M  (HP_SYS_OTG_PHY_TXBITSTUFF_EN_V << HP_SYS_OTG_PHY_TXBITSTUFF_EN_S)
+#define HP_SYSTEM_SYS_OTG_PHY_TXBITSTUFF_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_OTG_PHY_TXBITSTUFF_EN_S  22
+/** HP_SYS_OTG_PHY_REFCLK_MODE : R/W; bitpos: [23]; default: 1;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_OTG_PHY_REFCLK_MODE    (BIT(23))
+#define HP_SYSTEM_SYS_OTG_PHY_REFCLK_MODE_M  (HP_SYS_OTG_PHY_REFCLK_MODE_V << HP_SYS_OTG_PHY_REFCLK_MODE_S)
+#define HP_SYSTEM_SYS_OTG_PHY_REFCLK_MODE_V  0x00000001U
+#define HP_SYSTEM_SYS_OTG_PHY_REFCLK_MODE_S  23
+/** HP_SYS_OTG_PHY_BISTEN : R/W; bitpos: [24]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_OTG_PHY_BISTEN    (BIT(24))
+#define HP_SYSTEM_SYS_OTG_PHY_BISTEN_M  (HP_SYS_OTG_PHY_BISTEN_V << HP_SYS_OTG_PHY_BISTEN_S)
+#define HP_SYSTEM_SYS_OTG_PHY_BISTEN_V  0x00000001U
+#define HP_SYSTEM_SYS_OTG_PHY_BISTEN_S  24
+
+/** HP_TCM_ERR_RESP_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_ERR_RESP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x160)
+/** HP_TCM_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on tcm error response
+ */
+#define HP_SYSTEM_TCM_ERR_RESP_EN    (BIT(0))
+#define HP_SYSTEM_TCM_ERR_RESP_EN_M  (HP_TCM_ERR_RESP_EN_V << HP_TCM_ERR_RESP_EN_S)
+#define HP_SYSTEM_TCM_ERR_RESP_EN_V  0x00000001U
+#define HP_SYSTEM_TCM_ERR_RESP_EN_S  0
+
+/** HP_L2_MEM_REFRESH_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_REFRESH_REG (DR_REG_HP_SYS_BASE + 0x164)
+/** HP_REG_L2_MEM_UNIT0_REFERSH_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT0_REFERSH_EN_V << HP_REG_L2_MEM_UNIT0_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_S  0
+/** HP_REG_L2_MEM_UNIT1_REFERSH_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT1_REFERSH_EN_V << HP_REG_L2_MEM_UNIT1_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_S  1
+/** HP_REG_L2_MEM_UNIT2_REFERSH_EN : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT2_REFERSH_EN_V << HP_REG_L2_MEM_UNIT2_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_S  2
+/** HP_REG_L2_MEM_UNIT3_REFERSH_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN    (BIT(3))
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT3_REFERSH_EN_V << HP_REG_L2_MEM_UNIT3_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_S  3
+/** HP_REG_L2_MEM_UNIT4_REFERSH_EN : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN    (BIT(4))
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT4_REFERSH_EN_V << HP_REG_L2_MEM_UNIT4_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_S  4
+/** HP_REG_L2_MEM_UNIT5_REFERSH_EN : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN    (BIT(5))
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT5_REFERSH_EN_V << HP_REG_L2_MEM_UNIT5_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_S  5
+/** HP_REG_L2_MEM_REFERSH_CNT_RESET : R/W; bitpos: [6]; default: 1;
+ *  Set 1 to reset l2mem_refresh_cnt
+ */
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET    (BIT(6))
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_M  (HP_REG_L2_MEM_REFERSH_CNT_RESET_V << HP_REG_L2_MEM_REFERSH_CNT_RESET_S)
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_S  6
+/** HP_REG_L2_MEM_UNIT0_REFRESH_DONE : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE    (BIT(7))
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT0_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT0_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_S  7
+/** HP_REG_L2_MEM_UNIT1_REFRESH_DONE : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE    (BIT(8))
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT1_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT1_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_S  8
+/** HP_REG_L2_MEM_UNIT2_REFRESH_DONE : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE    (BIT(9))
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT2_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT2_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_S  9
+/** HP_REG_L2_MEM_UNIT3_REFRESH_DONE : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE    (BIT(10))
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT3_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT3_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_S  10
+/** HP_REG_L2_MEM_UNIT4_REFRESH_DONE : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE    (BIT(11))
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT4_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT4_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_S  11
+/** HP_REG_L2_MEM_UNIT5_REFRESH_DONE : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE    (BIT(12))
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT5_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT5_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_S  12
+
+/** HP_TCM_INIT_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_INIT_REG (DR_REG_HP_SYS_BASE + 0x168)
+/** HP_REG_TCM_INIT_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_TCM_INIT_EN    (BIT(0))
+#define HP_SYSTEM_REG_TCM_INIT_EN_M  (HP_REG_TCM_INIT_EN_V << HP_REG_TCM_INIT_EN_S)
+#define HP_SYSTEM_REG_TCM_INIT_EN_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_INIT_EN_S  0
+/** HP_REG_TCM_INIT_CNT_RESET : R/W; bitpos: [1]; default: 1;
+ *  Set 1 to reset tcm init cnt
+ */
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET    (BIT(1))
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_M  (HP_REG_TCM_INIT_CNT_RESET_V << HP_REG_TCM_INIT_CNT_RESET_S)
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_S  1
+/** HP_REG_TCM_INIT_DONE : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_TCM_INIT_DONE    (BIT(2))
+#define HP_SYSTEM_REG_TCM_INIT_DONE_M  (HP_REG_TCM_INIT_DONE_V << HP_REG_TCM_INIT_DONE_S)
+#define HP_SYSTEM_REG_TCM_INIT_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_INIT_DONE_S  2
+
+/** HP_TCM_PARITY_CHECK_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_CHECK_CTRL_REG (DR_REG_HP_SYS_BASE + 0x16c)
+/** HP_TCM_PARITY_CHECK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on tcm parity check
+ */
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN    (BIT(0))
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN_M  (HP_TCM_PARITY_CHECK_EN_V << HP_TCM_PARITY_CHECK_EN_S)
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN_S  0
+
+/** HP_DESIGN_FOR_VERIFICATION0_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_DESIGN_FOR_VERIFICATION0_REG (DR_REG_HP_SYS_BASE + 0x170)
+/** HP_DFV0 : R/W; bitpos: [31:0]; default: 0;
+ *  register for DV
+ */
+#define HP_SYSTEM_DFV0    0xFFFFFFFFU
+#define HP_SYSTEM_DFV0_M  (HP_DFV0_V << HP_DFV0_S)
+#define HP_SYSTEM_DFV0_V  0xFFFFFFFFU
+#define HP_SYSTEM_DFV0_S  0
+
+/** HP_DESIGN_FOR_VERIFICATION1_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_DESIGN_FOR_VERIFICATION1_REG (DR_REG_HP_SYS_BASE + 0x174)
+/** HP_DFV1 : R/W; bitpos: [31:0]; default: 0;
+ *  register for DV
+ */
+#define HP_SYSTEM_DFV1    0xFFFFFFFFU
+#define HP_SYSTEM_DFV1_M  (HP_DFV1_V << HP_DFV1_S)
+#define HP_SYSTEM_DFV1_V  0xFFFFFFFFU
+#define HP_SYSTEM_DFV1_S  0
+
+/** HP_PSRAM_FLASH_ADDR_INTERCHANGE_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_REG (DR_REG_HP_SYS_BASE + 0x180)
+/** HP_PSRAM_FLASH_ADDR_INTERCHANGE_CPU : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu
+ *  access through cache
+ */
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU    (BIT(0))
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_M  (HP_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_V << HP_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_S)
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_V  0x00000001U
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_S  0
+/** HP_PSRAM_FLASH_ADDR_INTERCHANGE_DMA : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable addr interchange between psram and flash in axi matrix when dma
+ *  device access, lp core access and hp core access through ahb
+ */
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA    (BIT(1))
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_M  (HP_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_V << HP_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_S)
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_V  0x00000001U
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_S  1
+
+/** HP_AHB2AXI_BRESP_ERR_INT_RAW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x188)
+/** HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
+ *  post write mode in ahb2axi.
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW    (BIT(0))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_M  (HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V << HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S  0
+
+/** HP_AHB2AXI_BRESP_ERR_INT_ST_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x18c)
+/** HP_CPU_ICM_H2X_BRESP_ERR_INT_ST : RO; bitpos: [31]; default: 0;
+ *  the masked interrupt status of  cpu_icm_h2x_bresp_err
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_M  (HP_CPU_ICM_H2X_BRESP_ERR_INT_ST_V << HP_CPU_ICM_H2X_BRESP_ERR_INT_ST_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_S  31
+
+/** HP_AHB2AXI_BRESP_ERR_INT_ENA_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x190)
+/** HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to enable cpu_icm_h2x_bresp_err int
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_M  (HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V << HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S  31
+
+/** HP_AHB2AXI_BRESP_ERR_INT_CLR_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x194)
+/** HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  Write 1 to clear cpu_icm_h2x_bresp_err  int
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_M  (HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V << HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S  31
+
+/** HP_L2_MEM_ERR_RESP_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_L2_MEM_ERR_RESP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x198)
+/** HP_L2_MEM_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on l2mem error response
+ */
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN    (BIT(0))
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_M  (HP_L2_MEM_ERR_RESP_EN_V << HP_L2_MEM_ERR_RESP_EN_S)
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_V  0x00000001U
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_S  0
+
+/** HP_L2_MEM_AHB_BUFFER_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_L2_MEM_AHB_BUFFER_CTRL_REG (DR_REG_HP_SYS_BASE + 0x19c)
+/** HP_L2_MEM_AHB_WRBUFFER_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on l2mem ahb wr buffer
+ */
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN    (BIT(0))
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_M  (HP_L2_MEM_AHB_WRBUFFER_EN_V << HP_L2_MEM_AHB_WRBUFFER_EN_S)
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_V  0x00000001U
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_S  0
+/** HP_L2_MEM_AHB_RDBUFFER_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to turn on l2mem ahb rd buffer
+ */
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN    (BIT(1))
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_M  (HP_L2_MEM_AHB_RDBUFFER_EN_V << HP_L2_MEM_AHB_RDBUFFER_EN_S)
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_V  0x00000001U
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_S  1
+
+/** HP_CORE_DMACTIVE_LPCORE_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_REG (DR_REG_HP_SYS_BASE + 0x1a0)
+/** HP_CORE_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0;
+ *  hp core dmactive_lpcore value
+ */
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE    (BIT(0))
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_M  (HP_CORE_DMACTIVE_LPCORE_V << HP_CORE_DMACTIVE_LPCORE_S)
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_V  0x00000001U
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_S  0
+
+/** HP_CORE_ERR_RESP_DIS_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_REG (DR_REG_HP_SYS_BASE + 0x1a4)
+/** HP_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
+ *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
+ *  disable ahb err resp.
+ */
+#define HP_SYSTEM_CORE_ERR_RESP_DIS    0x00000007U
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_M  (HP_CORE_ERR_RESP_DIS_V << HP_CORE_ERR_RESP_DIS_S)
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_V  0x00000007U
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_S  0
+
+/** HP_CORE_TIMEOUT_INT_RAW_REG register
+ *  Hp core bus timeout interrupt raw register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x1a8)
+/** HP_CORE0_AHB_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  the raw interrupt status of hp core0  ahb timeout
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_M  (HP_CORE0_AHB_TIMEOUT_INT_RAW_V << HP_CORE0_AHB_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_S  0
+/** HP_CORE1_AHB_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  the raw interrupt status of hp core1  ahb timeout
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_M  (HP_CORE1_AHB_TIMEOUT_INT_RAW_V << HP_CORE1_AHB_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_S  1
+/** HP_CORE0_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  the raw interrupt status of hp core0  ibus timeout
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_M  (HP_CORE0_IBUS_TIMEOUT_INT_RAW_V << HP_CORE0_IBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_S  2
+/** HP_CORE1_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  the raw interrupt status of hp core1  ibus timeout
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_M  (HP_CORE1_IBUS_TIMEOUT_INT_RAW_V << HP_CORE1_IBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_S  3
+/** HP_CORE0_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  the raw interrupt status of hp core0  dbus timeout
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_M  (HP_CORE0_DBUS_TIMEOUT_INT_RAW_V << HP_CORE0_DBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_S  4
+/** HP_CORE1_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  the raw interrupt status of hp core1  dbus timeout
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_M  (HP_CORE1_DBUS_TIMEOUT_INT_RAW_V << HP_CORE1_DBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_S  5
+
+/** HP_CORE_TIMEOUT_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x1ac)
+/** HP_CORE0_AHB_TIMEOUT_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of hp core0  ahb timeout
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_M  (HP_CORE0_AHB_TIMEOUT_INT_ST_V << HP_CORE0_AHB_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_S  0
+/** HP_CORE1_AHB_TIMEOUT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of hp core1  ahb timeout
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_M  (HP_CORE1_AHB_TIMEOUT_INT_ST_V << HP_CORE1_AHB_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_S  1
+/** HP_CORE0_IBUS_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  the masked interrupt status of hp core0  ibus timeout
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_M  (HP_CORE0_IBUS_TIMEOUT_INT_ST_V << HP_CORE0_IBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_S  2
+/** HP_CORE1_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  the masked interrupt status of hp core1  ibus timeout
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_M  (HP_CORE1_IBUS_TIMEOUT_INT_ST_V << HP_CORE1_IBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_S  3
+/** HP_CORE0_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  the masked interrupt status of hp core0  dbus timeout
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_M  (HP_CORE0_DBUS_TIMEOUT_INT_ST_V << HP_CORE0_DBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_S  4
+/** HP_CORE1_DBUS_TIMEOUT_INT_ST : RO; bitpos: [5]; default: 0;
+ *  the masked interrupt status of hp core1  dbus timeout
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_M  (HP_CORE1_DBUS_TIMEOUT_INT_ST_V << HP_CORE1_DBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_S  5
+
+/** HP_CORE_TIMEOUT_INT_ENA_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x1b0)
+/** HP_CORE0_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable hp_core0_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_M  (HP_CORE0_AHB_TIMEOUT_INT_ENA_V << HP_CORE0_AHB_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_S  0
+/** HP_CORE1_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable hp_core1_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_M  (HP_CORE1_AHB_TIMEOUT_INT_ENA_V << HP_CORE1_AHB_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_S  1
+/** HP_CORE0_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable hp_core0_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_M  (HP_CORE0_IBUS_TIMEOUT_INT_ENA_V << HP_CORE0_IBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_S  2
+/** HP_CORE1_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable hp_core1_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_M  (HP_CORE1_IBUS_TIMEOUT_INT_ENA_V << HP_CORE1_IBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_S  3
+/** HP_CORE0_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable hp_core0_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_M  (HP_CORE0_DBUS_TIMEOUT_INT_ENA_V << HP_CORE0_DBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_S  4
+/** HP_CORE1_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable hp_core1_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_M  (HP_CORE1_DBUS_TIMEOUT_INT_ENA_V << HP_CORE1_DBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_S  5
+
+/** HP_CORE_TIMEOUT_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x1b4)
+/** HP_CORE0_AHB_TIMEOUT_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear hp_core0_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_M  (HP_CORE0_AHB_TIMEOUT_INT_CLR_V << HP_CORE0_AHB_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_S  0
+/** HP_CORE1_AHB_TIMEOUT_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear hp_core1_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_M  (HP_CORE1_AHB_TIMEOUT_INT_CLR_V << HP_CORE1_AHB_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_S  1
+/** HP_CORE0_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear hp_core0_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_M  (HP_CORE0_IBUS_TIMEOUT_INT_CLR_V << HP_CORE0_IBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_S  2
+/** HP_CORE1_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear hp_core1_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_M  (HP_CORE1_IBUS_TIMEOUT_INT_CLR_V << HP_CORE1_IBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_S  3
+/** HP_CORE0_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear hp_core0_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_M  (HP_CORE0_DBUS_TIMEOUT_INT_CLR_V << HP_CORE0_DBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_S  4
+/** HP_CORE1_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear hp_core1_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_M  (HP_CORE1_DBUS_TIMEOUT_INT_CLR_V << HP_CORE1_DBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_S  5
+
+/** HP_GPIO_O_HYS_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HYS_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x1c0)
+/** HP_REG_GPIO_0_HYS_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  hys control for gpio47~16
+ */
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_M  (HP_REG_GPIO_0_HYS_LOW_V << HP_REG_GPIO_0_HYS_LOW_S)
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_S  0
+
+/** HP_GPIO_O_HYS_CTRL1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HYS_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x1c4)
+/** HP_REG_GPIO_0_HYS_HIGH : R/W; bitpos: [8:0]; default: 0;
+ *  hys control for gpio56~48
+ */
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH    0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_M  (HP_REG_GPIO_0_HYS_HIGH_V << HP_REG_GPIO_0_HYS_HIGH_S)
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_V  0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_S  0
+
+/** HP_RSA_PD_CTRL_REG register
+ *  rsa pd ctrl register
+ */
+#define HP_SYSTEM_RSA_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1d0)
+/** HP_RSA_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down rsa internal memory.
+ */
+#define HP_SYSTEM_RSA_MEM_FORCE_PD    (BIT(0))
+#define HP_SYSTEM_RSA_MEM_FORCE_PD_M  (HP_RSA_MEM_FORCE_PD_V << HP_RSA_MEM_FORCE_PD_S)
+#define HP_SYSTEM_RSA_MEM_FORCE_PD_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_FORCE_PD_S  0
+/** HP_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up rsa internal memory
+ */
+#define HP_SYSTEM_RSA_MEM_FORCE_PU    (BIT(1))
+#define HP_SYSTEM_RSA_MEM_FORCE_PU_M  (HP_RSA_MEM_FORCE_PU_V << HP_RSA_MEM_FORCE_PU_S)
+#define HP_SYSTEM_RSA_MEM_FORCE_PU_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_FORCE_PU_S  1
+/** HP_RSA_MEM_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down rsa internal memory.
+ */
+#define HP_SYSTEM_RSA_MEM_PD    (BIT(2))
+#define HP_SYSTEM_RSA_MEM_PD_M  (HP_RSA_MEM_PD_V << HP_RSA_MEM_PD_S)
+#define HP_SYSTEM_RSA_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_PD_S  2
+
+/** HP_ECC_PD_CTRL_REG register
+ *  ecc pd ctrl register
+ */
+#define HP_SYSTEM_ECC_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1d4)
+/** HP_ECC_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down ecc internal memory.
+ */
+#define HP_SYSTEM_ECC_MEM_FORCE_PD    (BIT(0))
+#define HP_SYSTEM_ECC_MEM_FORCE_PD_M  (HP_ECC_MEM_FORCE_PD_V << HP_ECC_MEM_FORCE_PD_S)
+#define HP_SYSTEM_ECC_MEM_FORCE_PD_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_FORCE_PD_S  0
+/** HP_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up ecc internal memory
+ */
+#define HP_SYSTEM_ECC_MEM_FORCE_PU    (BIT(1))
+#define HP_SYSTEM_ECC_MEM_FORCE_PU_M  (HP_ECC_MEM_FORCE_PU_V << HP_ECC_MEM_FORCE_PU_S)
+#define HP_SYSTEM_ECC_MEM_FORCE_PU_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_FORCE_PU_S  1
+/** HP_ECC_MEM_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down ecc internal memory.
+ */
+#define HP_SYSTEM_ECC_MEM_PD    (BIT(2))
+#define HP_SYSTEM_ECC_MEM_PD_M  (HP_ECC_MEM_PD_V << HP_ECC_MEM_PD_S)
+#define HP_SYSTEM_ECC_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_PD_S  2
+
+/** HP_RNG_CFG_REG register
+ *  rng cfg register
+ */
+#define HP_SYSTEM_RNG_CFG_REG (DR_REG_HP_SYS_BASE + 0x1d8)
+/** HP_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE    (BIT(0))
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE_M  (HP_RNG_SAMPLE_ENABLE_V << HP_RNG_SAMPLE_ENABLE_S)
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE_V  0x00000001U
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE_S  0
+/** HP_RNG_CHAIN_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 0;
+ *  chain clk div num to pad for debug
+ */
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM    0x000000FFU
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_M  (HP_RNG_CHAIN_CLK_DIV_NUM_V << HP_RNG_CHAIN_CLK_DIV_NUM_S)
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_S  16
+
+/** HP_UART_PD_CTRL_REG register
+ *  ecc pd ctrl register
+ */
+#define HP_SYSTEM_UART_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1dc)
+/** HP_UART_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down hp uart internal memory.
+ */
+#define HP_SYSTEM_UART_MEM_FORCE_PD    (BIT(0))
+#define HP_SYSTEM_UART_MEM_FORCE_PD_M  (HP_UART_MEM_FORCE_PD_V << HP_UART_MEM_FORCE_PD_S)
+#define HP_SYSTEM_UART_MEM_FORCE_PD_V  0x00000001U
+#define HP_SYSTEM_UART_MEM_FORCE_PD_S  0
+/** HP_UART_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up hp uart  internal memory
+ */
+#define HP_SYSTEM_UART_MEM_FORCE_PU    (BIT(1))
+#define HP_SYSTEM_UART_MEM_FORCE_PU_M  (HP_UART_MEM_FORCE_PU_V << HP_UART_MEM_FORCE_PU_S)
+#define HP_SYSTEM_UART_MEM_FORCE_PU_V  0x00000001U
+#define HP_SYSTEM_UART_MEM_FORCE_PU_S  1
+
+/** HP_PERI_MEM_CLK_FORCE_ON_REG register
+ *  hp peri mem clk force on regpster
+ */
+#define HP_SYSTEM_PERI_MEM_CLK_FORCE_ON_REG (DR_REG_HP_SYS_BASE + 0x1e0)
+/** HP_RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force on mem clk in rmt
+ */
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_M  (HP_RMT_MEM_CLK_FORCE_ON_V << HP_RMT_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_S  0
+/** HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to force on tx mem clk in bitscrambler
+ */
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON    (BIT(1))
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_M  (HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V << HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S  1
+/** HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force on rx mem clk in bitscrambler
+ */
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON    (BIT(2))
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_M  (HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V << HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S  2
+/** HP_GDMA_MEM_CLK_FORCE_ON : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force on mem clk in gdma
+ */
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON    (BIT(3))
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_M  (HP_GDMA_MEM_CLK_FORCE_ON_V << HP_GDMA_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_S  3
+
+/** HP_USB_OTGHS_PHY_ST_REG register
+ *  Usb otg2.0 PHY status register
+ */
+#define HP_SYSTEM_USB_OTGHS_PHY_ST_REG (DR_REG_HP_SYS_BASE + 0x1e8)
+/** HP_USB_SOFT_RESET_ACTV_PDOMAIN : RO; bitpos: [0]; default: 0;
+ *  Todo
+ */
+#define HP_SYSTEM_USB_SOFT_RESET_ACTV_PDOMAIN    (BIT(0))
+#define HP_SYSTEM_USB_SOFT_RESET_ACTV_PDOMAIN_M  (HP_USB_SOFT_RESET_ACTV_PDOMAIN_V << HP_USB_SOFT_RESET_ACTV_PDOMAIN_S)
+#define HP_SYSTEM_USB_SOFT_RESET_ACTV_PDOMAIN_V  0x00000001U
+#define HP_SYSTEM_USB_SOFT_RESET_ACTV_PDOMAIN_S  0
+/** HP_UTMISRP_SESSEND : RO; bitpos: [1]; default: 0;
+ *  Todo
+ */
+#define HP_SYSTEM_UTMISRP_SESSEND    (BIT(1))
+#define HP_SYSTEM_UTMISRP_SESSEND_M  (HP_UTMISRP_SESSEND_V << HP_UTMISRP_SESSEND_S)
+#define HP_SYSTEM_UTMISRP_SESSEND_V  0x00000001U
+#define HP_SYSTEM_UTMISRP_SESSEND_S  1
+/** HP_UTMIOTG_VBUSVALID : RO; bitpos: [2]; default: 0;
+ *  Todo
+ */
+#define HP_SYSTEM_UTMIOTG_VBUSVALID    (BIT(2))
+#define HP_SYSTEM_UTMIOTG_VBUSVALID_M  (HP_UTMIOTG_VBUSVALID_V << HP_UTMIOTG_VBUSVALID_S)
+#define HP_SYSTEM_UTMIOTG_VBUSVALID_V  0x00000001U
+#define HP_SYSTEM_UTMIOTG_VBUSVALID_S  2
+/** HP_UTMISRP_BVALID : RO; bitpos: [3]; default: 0;
+ *  Todo
+ */
+#define HP_SYSTEM_UTMISRP_BVALID    (BIT(3))
+#define HP_SYSTEM_UTMISRP_BVALID_M  (HP_UTMISRP_BVALID_V << HP_UTMISRP_BVALID_S)
+#define HP_SYSTEM_UTMISRP_BVALID_V  0x00000001U
+#define HP_SYSTEM_UTMISRP_BVALID_S  3
+/** HP_UTMISRP_SESSVALID : RO; bitpos: [4]; default: 0;
+ *  Todo
+ */
+#define HP_SYSTEM_UTMISRP_SESSVALID    (BIT(4))
+#define HP_SYSTEM_UTMISRP_SESSVALID_M  (HP_UTMISRP_SESSVALID_V << HP_UTMISRP_SESSVALID_S)
+#define HP_SYSTEM_UTMISRP_SESSVALID_V  0x00000001U
+#define HP_SYSTEM_UTMISRP_SESSVALID_S  4
+
+/** HP_CPU_WAKEUP_EVENT_REG register
+ *  cpu wakeup event ctrl register
+ */
+#define HP_SYSTEM_CPU_WAKEUP_EVENT_REG (DR_REG_HP_SYS_BASE + 0x1ec)
+/** HP_CORE0_WAKEUP_EVENT : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to wake up hp core0
+ */
+#define HP_SYSTEM_CORE0_WAKEUP_EVENT    (BIT(0))
+#define HP_SYSTEM_CORE0_WAKEUP_EVENT_M  (HP_CORE0_WAKEUP_EVENT_V << HP_CORE0_WAKEUP_EVENT_S)
+#define HP_SYSTEM_CORE0_WAKEUP_EVENT_V  0x00000001U
+#define HP_SYSTEM_CORE0_WAKEUP_EVENT_S  0
+/** HP_CORE1_WAKEUP_EVENT : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to wake up hp core1
+ */
+#define HP_SYSTEM_CORE1_WAKEUP_EVENT    (BIT(1))
+#define HP_SYSTEM_CORE1_WAKEUP_EVENT_M  (HP_CORE1_WAKEUP_EVENT_V << HP_CORE1_WAKEUP_EVENT_S)
+#define HP_SYSTEM_CORE1_WAKEUP_EVENT_V  0x00000001U
+#define HP_SYSTEM_CORE1_WAKEUP_EVENT_S  1
+
+/** HP_HP2LP_INTR_GROUP0_EN_REG register
+ *  HpP2LP Interrupt Enable Register Group0
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP0_EN_REG (DR_REG_HP_SYS_BASE + 0x1f0)
+/** HP_H2LP_INTR_GROUP0_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP0_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP0_EN_M  (HP_H2LP_INTR_GROUP0_EN_V << HP_H2LP_INTR_GROUP0_EN_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP0_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP0_EN_S  0
+
+/** HP_HP2LP_INTR_GROUP1_EN_REG register
+ *  HpP2LP Interrupt Enable Register Group1
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP1_EN_REG (DR_REG_HP_SYS_BASE + 0x1f4)
+/** HP_H2LP_INTR_GROUP1_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP1_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP1_EN_M  (HP_H2LP_INTR_GROUP1_EN_V << HP_H2LP_INTR_GROUP1_EN_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP1_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP1_EN_S  0
+
+/** HP_HP2LP_INTR_GROUP2_EN_REG register
+ *  HpP2LP Interrupt Enable Register Group2
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP2_EN_REG (DR_REG_HP_SYS_BASE + 0x1f8)
+/** HP_H2LP_INTR_GROUP2_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP2_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP2_EN_M  (HP_H2LP_INTR_GROUP2_EN_V << HP_H2LP_INTR_GROUP2_EN_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP2_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP2_EN_S  0
+
+/** HP_HP2LP_INTR_GROUP3_EN_REG register
+ *  HpP2LP Interrupt Enable Register Group3
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP3_EN_REG (DR_REG_HP_SYS_BASE + 0x1fc)
+/** HP_H2LP_INTR_GROUP3_EN : R/W; bitpos: [13:0]; default: 16383;
+ *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP3_EN    0x00003FFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP3_EN_M  (HP_H2LP_INTR_GROUP3_EN_V << HP_H2LP_INTR_GROUP3_EN_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP3_EN_V  0x00003FFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP3_EN_S  0
+
+/** HP_HP2LP_INTR_GROUP0_ST_REG register
+ *  HpP2LP Interrupt Status Register Group0
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP0_ST_REG (DR_REG_HP_SYS_BASE + 0x200)
+/** HP_H2LP_INTR_GROUP0_ST : RO; bitpos: [31:0]; default: 0;
+ *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP0_ST    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP0_ST_M  (HP_H2LP_INTR_GROUP0_ST_V << HP_H2LP_INTR_GROUP0_ST_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP0_ST_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP0_ST_S  0
+
+/** HP_HP2LP_INTR_GROUP1_ST_REG register
+ *  HpP2LP Interrupt Enable Register Group1
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP1_ST_REG (DR_REG_HP_SYS_BASE + 0x204)
+/** HP_H2LP_INTR_GROUP1_ST : RO; bitpos: [31:0]; default: 0;
+ *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP1_ST    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP1_ST_M  (HP_H2LP_INTR_GROUP1_ST_V << HP_H2LP_INTR_GROUP1_ST_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP1_ST_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP1_ST_S  0
+
+/** HP_HP2LP_INTR_GROUP2_ST_REG register
+ *  HpP2LP Interrupt Enable Register Group2
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP2_ST_REG (DR_REG_HP_SYS_BASE + 0x208)
+/** HP_H2LP_INTR_GROUP2_ST : RO; bitpos: [31:0]; default: 0;
+ *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP2_ST    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP2_ST_M  (HP_H2LP_INTR_GROUP2_ST_V << HP_H2LP_INTR_GROUP2_ST_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP2_ST_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP2_ST_S  0
+
+/** HP_HP2LP_INTR_GROUP3_ST_REG register
+ *  HpP2LP Interrupt Enable Register Group3
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP3_ST_REG (DR_REG_HP_SYS_BASE + 0x20c)
+/** HP_H2LP_INTR_GROUP3_ST : RO; bitpos: [13:0]; default: 0;
+ *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP3_ST    0x00003FFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP3_ST_M  (HP_H2LP_INTR_GROUP3_ST_V << HP_H2LP_INTR_GROUP3_ST_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP3_ST_V  0x00003FFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP3_ST_S  0
+
+/** HP_HP2LP_WAKEUP_GROUP0_EN_REG register
+ *  HpP2LP Wakeup Enable Register Group0
+ */
+#define HP_SYSTEM_HP2LP_WAKEUP_GROUP0_EN_REG (DR_REG_HP_SYS_BASE + 0x210)
+/** HP_H2LP_WAKEUP_GROUP0_EN : R/W; bitpos: [31:0]; default: 0;
+ *  Set each bit to enable corresponding peripheral wakeup to PMU.
+ */
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP0_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP0_EN_M  (HP_H2LP_WAKEUP_GROUP0_EN_V << HP_H2LP_WAKEUP_GROUP0_EN_S)
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP0_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP0_EN_S  0
+
+/** HP_HP2LP_WAKEUP_GROUP1_EN_REG register
+ *  HpP2LP Wakeup Enable Register Group1
+ */
+#define HP_SYSTEM_HP2LP_WAKEUP_GROUP1_EN_REG (DR_REG_HP_SYS_BASE + 0x214)
+/** HP_H2LP_WAKEUP_GROUP1_EN : R/W; bitpos: [31:0]; default: 0;
+ *  Set each bit to enable corresponding peripheral wakeup to PMU.
+ */
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP1_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP1_EN_M  (HP_H2LP_WAKEUP_GROUP1_EN_V << HP_H2LP_WAKEUP_GROUP1_EN_S)
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP1_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP1_EN_S  0
+
+/** HP_HP2LP_WAKEUP_GROUP2_EN_REG register
+ *  HpP2LP Wakeup Enable Register Group2
+ */
+#define HP_SYSTEM_HP2LP_WAKEUP_GROUP2_EN_REG (DR_REG_HP_SYS_BASE + 0x218)
+/** HP_H2LP_WAKEUP_GROUP2_EN : R/W; bitpos: [31:0]; default: 0;
+ *  Set each bit to enable corresponding peripheral wakeup to PMU.
+ */
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP2_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP2_EN_M  (HP_H2LP_WAKEUP_GROUP2_EN_V << HP_H2LP_WAKEUP_GROUP2_EN_S)
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP2_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP2_EN_S  0
+
+/** HP_HP2LP_WAKEUP_GROUP3_EN_REG register
+ *  HpP2LP Wakeup Enable Register Group3
+ */
+#define HP_SYSTEM_HP2LP_WAKEUP_GROUP3_EN_REG (DR_REG_HP_SYS_BASE + 0x21c)
+/** HP_H2LP_WAKEUP_GROUP3_EN : R/W; bitpos: [13:0]; default: 0;
+ *  Set each bit to enable corresponding peripheral wakeup to PMU.
+ */
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP3_EN    0x00003FFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP3_EN_M  (HP_H2LP_WAKEUP_GROUP3_EN_V << HP_H2LP_WAKEUP_GROUP3_EN_S)
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP3_EN_V  0x00003FFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP3_EN_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
new file mode 100644
index 0000000000..e48b0e6b43
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
@@ -0,0 +1,2257 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: HP SYS VER DATE REG */
+/** Type of sys_ver_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [31:0]; default: 539296519;
+         *  NA
+         */
+        uint32_t reg_ver_date:32;
+    };
+    uint32_t val;
+} hp_sys_ver_date_reg_t;
+
+
+/** Group: HP CLK EN REG */
+/** Type of clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_clk_en_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 0 REG */
+/** Type of cpu_int_from_cpu_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_0 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_cpu_int_from_cpu_0_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 1 REG */
+/** Type of cpu_int_from_cpu_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_1 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_1:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_cpu_int_from_cpu_1_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 2 REG */
+/** Type of cpu_int_from_cpu_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_2 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_2:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_cpu_int_from_cpu_2_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 3 REG */
+/** Type of cpu_int_from_cpu_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_3 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_3:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_cpu_int_from_cpu_3_reg_t;
+
+
+/** Group: HP CACHE CLK CONFIG REG */
+/** Type of cache_clk_config register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_cache_clk_on : R/W; bitpos: [0]; default: 1;
+         *  l2 cache clk enable
+         */
+        uint32_t reg_l2_cache_clk_on:1;
+        /** reg_l1_d_cache_clk_on : R/W; bitpos: [1]; default: 1;
+         *  l1 dcahce clk enable
+         */
+        uint32_t reg_l1_d_cache_clk_on:1;
+        uint32_t reserved_2:2;
+        /** reg_l1_i1_cache_clk_on : R/W; bitpos: [4]; default: 1;
+         *  l1 icahce1 clk enable
+         */
+        uint32_t reg_l1_i1_cache_clk_on:1;
+        /** reg_l1_i0_cache_clk_on : R/W; bitpos: [5]; default: 1;
+         *  l1 icahce0 clk enable
+         */
+        uint32_t reg_l1_i0_cache_clk_on:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_cache_clk_config_reg_t;
+
+
+/** Group: HP CACHE RESET CONFIG REG */
+/** Type of cache_reset_config register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** reg_l1_d_cache_reset : R/W; bitpos: [1]; default: 0;
+         *  set 1 to reset l1 dcahce
+         */
+        uint32_t reg_l1_d_cache_reset:1;
+        uint32_t reserved_2:2;
+        /** reg_l1_i1_cache_reset : R/W; bitpos: [4]; default: 0;
+         *  set 1 to reset l1 icahce1
+         */
+        uint32_t reg_l1_i1_cache_reset:1;
+        /** reg_l1_i0_cache_reset : R/W; bitpos: [5]; default: 0;
+         *  set 1 to reset l1 icahce0
+         */
+        uint32_t reg_l1_i0_cache_reset:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_cache_reset_config_reg_t;
+
+
+/** Group: HP SYS DMA ADDR CTRL REG */
+/** Type of sys_dma_addr_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sys_dma_addr_sel : R/W; bitpos: [0]; default: 0;
+         *  0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx
+         */
+        uint32_t reg_sys_dma_addr_sel:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_dma_addr_ctrl_reg_t;
+
+
+/** Group: HP TCM RAM WRR CONFIG REG */
+/** Type of tcm_ram_wrr_config register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tcm_ram_ibus0_wt : R/W; bitpos: [2:0]; default: 7;
+         *  weight value of ibus0
+         */
+        uint32_t reg_tcm_ram_ibus0_wt:3;
+        /** reg_tcm_ram_ibus1_wt : R/W; bitpos: [5:3]; default: 7;
+         *  weight value of ibus1
+         */
+        uint32_t reg_tcm_ram_ibus1_wt:3;
+        /** reg_tcm_ram_ibus2_wt : R/W; bitpos: [8:6]; default: 4;
+         *  weight value of ibus2
+         */
+        uint32_t reg_tcm_ram_ibus2_wt:3;
+        /** reg_tcm_ram_ibus3_wt : R/W; bitpos: [11:9]; default: 4;
+         *  weight value of ibus3
+         */
+        uint32_t reg_tcm_ram_ibus3_wt:3;
+        /** reg_tcm_ram_dbus0_wt : R/W; bitpos: [14:12]; default: 5;
+         *  weight value of dbus0
+         */
+        uint32_t reg_tcm_ram_dbus0_wt:3;
+        /** reg_tcm_ram_dbus1_wt : R/W; bitpos: [17:15]; default: 5;
+         *  weight value of dbus1
+         */
+        uint32_t reg_tcm_ram_dbus1_wt:3;
+        /** reg_tcm_ram_dbus2_wt : R/W; bitpos: [20:18]; default: 3;
+         *  weight value of dbus2
+         */
+        uint32_t reg_tcm_ram_dbus2_wt:3;
+        /** reg_tcm_ram_dbus3_wt : R/W; bitpos: [23:21]; default: 3;
+         *  weight value of dbus3
+         */
+        uint32_t reg_tcm_ram_dbus3_wt:3;
+        /** reg_tcm_ram_dma_wt : R/W; bitpos: [26:24]; default: 2;
+         *  weight value of dma
+         */
+        uint32_t reg_tcm_ram_dma_wt:3;
+        uint32_t reserved_27:4;
+        /** reg_tcm_ram_wrr_high : R/W; bitpos: [31]; default: 1;
+         *  enable weighted round robin arbitration
+         */
+        uint32_t reg_tcm_ram_wrr_high:1;
+    };
+    uint32_t val;
+} hp_tcm_ram_wrr_config_reg_t;
+
+
+/** Group: HP TCM SW PARITY BWE MASK REG */
+/** Type of tcm_sw_parity_bwe_mask register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tcm_sw_parity_bwe_mask_ctrl : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to mask tcm bwe parity code bit
+         */
+        uint32_t reg_tcm_sw_parity_bwe_mask_ctrl:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_tcm_sw_parity_bwe_mask_reg_t;
+
+
+/** Group: HP TCM RAM PWR CTRL0 REG */
+/** Type of tcm_ram_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_tcm_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  hp_tcm clk gatig force on
+         */
+        uint32_t reg_hp_tcm_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_tcm_ram_pwr_ctrl0_reg_t;
+
+
+/** Group: HP L2 ROM PWR CTRL0 REG */
+/** Type of l2_rom_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_rom_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  l2_rom clk gating force on
+         */
+        uint32_t reg_l2_rom_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_l2_rom_pwr_ctrl0_reg_t;
+
+
+/** Group: HP PROBEA CTRL REG */
+/** Type of probea_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+         *  module's probe_out[31:0] in a mode
+         */
+        uint32_t reg_probe_a_mod_sel:16;
+        /** reg_probe_a_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  This field is used to selec module's probe_out[31:0] as probe out in a mode
+         */
+        uint32_t reg_probe_a_top_sel:8;
+        /** reg_probe_l_sel : R/W; bitpos: [25:24]; default: 0;
+         *  This field is used to selec probe_out[31:16]
+         */
+        uint32_t reg_probe_l_sel:2;
+        /** reg_probe_h_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This field is used to selec probe_out[31:16]
+         */
+        uint32_t reg_probe_h_sel:2;
+        /** reg_probe_global_en : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to enable global debug probe in hp system.
+         */
+        uint32_t reg_probe_global_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} hp_probea_ctrl_reg_t;
+
+
+/** Group: HP PROBEB CTRL REG */
+/** Type of probeb_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+         *  module's probe_out[31:0] in b mode.
+         */
+        uint32_t reg_probe_b_mod_sel:16;
+        /** reg_probe_b_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
+         */
+        uint32_t reg_probe_b_top_sel:8;
+        /** reg_probe_b_en : R/W; bitpos: [24]; default: 0;
+         *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
+         */
+        uint32_t reg_probe_b_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_probeb_ctrl_reg_t;
+
+
+/** Group: HP PROBE OUT REG */
+/** Type of probe_out register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_top_out : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_probe_top_out:32;
+    };
+    uint32_t val;
+} hp_probe_out_reg_t;
+
+
+/** Group: HP L2 MEM RAM PWR CTRL0 REG */
+/** Type of l2_mem_ram_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  l2ram clk_gating force on
+         */
+        uint32_t reg_l2_mem_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_l2_mem_ram_pwr_ctrl0_reg_t;
+
+
+/** Group: HP CPU CORESTALLED ST REG */
+/** Type of cpu_corestalled_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_corestalled_st : RO; bitpos: [0]; default: 0;
+         *  hp core0 corestalled status
+         */
+        uint32_t reg_core0_corestalled_st:1;
+        /** reg_core1_corestalled_st : RO; bitpos: [1]; default: 0;
+         *  hp core1 corestalled status
+         */
+        uint32_t reg_core1_corestalled_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_cpu_corestalled_st_reg_t;
+
+
+/** Group: HP CRYPTO CTRL REG */
+/** Type of crypto_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_spi_manual_encrypt:1;
+        /** reg_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_db_encrypt:1;
+        /** reg_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_g0cb_decrypt:1;
+        /** reg_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_manual_encrypt:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_crypto_ctrl_reg_t;
+
+
+/** Group: HP GPIO O HOLD CTRL0 REG */
+/** Type of gpio_o_hold_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hold_low : R/W; bitpos: [31:0]; default: 0;
+         *  hold control for gpio47~16
+         */
+        uint32_t reg_gpio_0_hold_low:32;
+    };
+    uint32_t val;
+} hp_gpio_o_hold_ctrl0_reg_t;
+
+
+/** Group: HP GPIO O HOLD CTRL1 REG */
+/** Type of gpio_o_hold_ctrl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hold_high : R/W; bitpos: [8:0]; default: 0;
+         *  hold control for gpio56~48
+         */
+        uint32_t reg_gpio_0_hold_high:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_gpio_o_hold_ctrl1_reg_t;
+
+
+/** Group: HP SYS RDN ECO CS REG */
+/** Type of sys_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_sys_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_sys_rdn_eco_en:1;
+        /** reg_hp_sys_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_sys_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_rdn_eco_cs_reg_t;
+
+
+/** Group: HP CACHE APB POSTW EN REG */
+/** Type of cache_apb_postw_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cache_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  cache apb register interface post write enable, 1 will speed up write, but will
+         *  take some time to update value to register
+         */
+        uint32_t reg_cache_apb_postw_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_cache_apb_postw_en_reg_t;
+
+
+/** Group: HP L2 MEM SUBSIZE REG */
+/** Type of l2_mem_subsize register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_sub_blksize : R/W; bitpos: [1:0]; default: 0;
+         *  l2mem sub block size 00=>32 01=>64 10=>128 11=>256
+         */
+        uint32_t reg_l2_mem_sub_blksize:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_l2_mem_subsize_reg_t;
+
+
+/** Group: HP L2 MEM INT RAW REG */
+/** Type of l2_mem_int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  intr triggered when two bit error detected and corrected from ecc
+         */
+        uint32_t reg_l2_mem_ecc_err_int_raw:1;
+        /** reg_l2_mem_exceed_addr_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds
+         *  0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_raw:1;
+        /** reg_l2_mem_err_resp_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  intr triggered when err response occurs
+         */
+        uint32_t reg_l2_mem_err_resp_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_l2_mem_int_raw_reg_t;
+
+
+/** Group: HP L2 MEM INT ST REG */
+/** Type of l2_mem_int_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_st : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_st:1;
+        /** reg_l2_mem_exceed_addr_int_st : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_st:1;
+        /** reg_l2_mem_err_resp_int_st : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_err_resp_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_l2_mem_int_st_reg_t;
+
+
+/** Group: HP L2 MEM INT ENA REG */
+/** Type of l2_mem_int_ena register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_ena : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_ena:1;
+        /** reg_l2_mem_exceed_addr_int_ena : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_ena:1;
+        /** reg_l2_mem_err_resp_int_ena : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_err_resp_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_l2_mem_int_ena_reg_t;
+
+
+/** Group: HP L2 MEM INT CLR REG */
+/** Type of l2_mem_int_clr register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_clr : WT; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_clr:1;
+        /** reg_l2_mem_exceed_addr_int_clr : WT; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_clr:1;
+        /** reg_l2_mem_err_resp_int_clr : WT; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_err_resp_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_l2_mem_int_clr_reg_t;
+
+
+/** Group: HP L2 MEM L2 RAM ECC REG */
+/** Type of l2_mem_l2_ram_ecc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_ram_unit0_ecc_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit0_ecc_en:1;
+        /** reg_l2_ram_unit1_ecc_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit1_ecc_en:1;
+        /** reg_l2_ram_unit2_ecc_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit2_ecc_en:1;
+        /** reg_l2_ram_unit3_ecc_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit3_ecc_en:1;
+        /** reg_l2_ram_unit4_ecc_en : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit4_ecc_en:1;
+        /** reg_l2_ram_unit5_ecc_en : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit5_ecc_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_l2_mem_l2_ram_ecc_reg_t;
+
+
+/** Group: HP L2 MEM INT RECORD0 REG */
+/** Type of l2_mem_int_record0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_exceed_addr_int_addr : RO; bitpos: [20:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_addr:21;
+        /** reg_l2_mem_exceed_addr_int_we : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_we:1;
+        /** reg_l2_mem_exceed_addr_int_master : RO; bitpos: [24:22]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_master:3;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_l2_mem_int_record0_reg_t;
+
+
+/** Group: HP L2 MEM INT RECORD1 REG */
+/** Type of l2_mem_int_record1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_addr : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_addr:15;
+        /** reg_l2_mem_ecc_one_bit_err : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_one_bit_err:1;
+        /** reg_l2_mem_ecc_two_bit_err : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_two_bit_err:1;
+        /** reg_l2_mem_ecc_err_bit : RO; bitpos: [25:17]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_bit:9;
+        /** reg_l2_cache_err_bank : RO; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_cache_err_bank:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_l2_mem_int_record1_reg_t;
+
+
+/** Group: HP L2 MEM L2 CACHE ECC REG */
+/** Type of l2_mem_l2_cache_ecc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_cache_ecc_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_cache_ecc_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_l2_mem_l2_cache_ecc_reg_t;
+
+
+/** Group: HP L1CACHE BUS0 ID REG */
+/** Type of l1cache_bus0_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l1_cache_bus0_id : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l1_cache_bus0_id:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_l1cache_bus0_id_reg_t;
+
+
+/** Group: HP L1CACHE BUS1 ID REG */
+/** Type of l1cache_bus1_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l1_cache_bus1_id : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l1_cache_bus1_id:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_l1cache_bus1_id_reg_t;
+
+
+/** Group: HP L2 MEM RDN ECO CS REG */
+/** Type of l2_mem_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_en:1;
+        /** reg_l2_mem_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_l2_mem_rdn_eco_cs_reg_t;
+
+
+/** Group: HP L2 MEM RDN ECO LOW REG */
+/** Type of l2_mem_rdn_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_low:32;
+    };
+    uint32_t val;
+} hp_l2_mem_rdn_eco_low_reg_t;
+
+
+/** Group: HP L2 MEM RDN ECO HIGH REG */
+/** Type of l2_mem_rdn_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_high:32;
+    };
+    uint32_t val;
+} hp_l2_mem_rdn_eco_high_reg_t;
+
+
+/** Group: HP TCM RDN ECO CS REG */
+/** Type of tcm_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_tcm_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_tcm_rdn_eco_en:1;
+        /** reg_hp_tcm_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_tcm_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_tcm_rdn_eco_cs_reg_t;
+
+
+/** Group: HP TCM RDN ECO LOW REG */
+/** Type of tcm_rdn_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_tcm_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_tcm_rdn_eco_low:32;
+    };
+    uint32_t val;
+} hp_tcm_rdn_eco_low_reg_t;
+
+
+/** Group: HP TCM RDN ECO HIGH REG */
+/** Type of tcm_rdn_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_tcm_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  NA
+         */
+        uint32_t reg_hp_tcm_rdn_eco_high:32;
+    };
+    uint32_t val;
+} hp_tcm_rdn_eco_high_reg_t;
+
+
+/** Group: HP GPIO DEAD HOLD CTRL REG */
+/** Type of gpio_ded_hold_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_ded_hold : R/W; bitpos: [25:0]; default: 0;
+         *  hold control for gpio63~56
+         */
+        uint32_t reg_gpio_ded_hold:26;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} hp_gpio_ded_hold_ctrl_reg_t;
+
+
+/** Group: HP L2 MEM SW ECC BWE MASK REG */
+/** Type of l2_mem_sw_ecc_bwe_mask register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_sw_ecc_bwe_mask_ctrl : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to mask bwe hamming code bit
+         */
+        uint32_t reg_l2_mem_sw_ecc_bwe_mask_ctrl:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_l2_mem_sw_ecc_bwe_mask_reg_t;
+
+
+/** Group: HP USB20OTG MEM CTRL REG */
+/** Type of usb20otg_mem_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_usb20_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_usb20_mem_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_usb20otg_mem_ctrl_reg_t;
+
+
+/** Group: configure_register */
+/** Type of tcm_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_raw:1;
+    };
+    uint32_t val;
+} hp_tcm_int_raw_reg_t;
+
+/** Type of tcm_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_st:1;
+    };
+    uint32_t val;
+} hp_tcm_int_st_reg_t;
+
+/** Type of tcm_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_ena:1;
+    };
+    uint32_t val;
+} hp_tcm_int_ena_reg_t;
+
+/** Type of tcm_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_clr:1;
+    };
+    uint32_t val;
+} hp_tcm_int_clr_reg_t;
+
+/** Type of core_ahb_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_ahb_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 ahb timeout handle
+         */
+        uint32_t core_ahb_timeout_en:1;
+        /** core_ahb_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 ahb bus timeout  threshold
+         */
+        uint32_t core_ahb_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_core_ahb_timeout_reg_t;
+
+/** Type of core_ibus_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_ibus_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 ibus timeout handle
+         */
+        uint32_t core_ibus_timeout_en:1;
+        /** core_ibus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 ibus timeout  threshold
+         */
+        uint32_t core_ibus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_core_ibus_timeout_reg_t;
+
+/** Type of core_dbus_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_dbus_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 dbus timeout handle
+         */
+        uint32_t core_dbus_timeout_en:1;
+        /** core_dbus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 dbus timeout  threshold
+         */
+        uint32_t core_dbus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_core_dbus_timeout_reg_t;
+
+/** Type of icm_cpu_h2x_cfg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** cpu_icm_h2x_post_wr_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_post_wr_en:1;
+        /** cpu_icm_h2x_cut_through_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_cut_through_en:1;
+        /** cpu_icm_h2x_bridge_busy : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_bridge_busy:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_icm_cpu_h2x_cfg_reg_t;
+
+/** Type of bitscrambler_peri_sel register
+ *  Bitscrambler Peri Sel
+ */
+typedef union {
+    struct {
+        /** bitscrambler_peri_rx_sel : R/W; bitpos: [3:0]; default: 15;
+         *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler: 4'h0
+         *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+         *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+         *  else : none
+         */
+        uint32_t bitscrambler_peri_rx_sel:4;
+        /** bitscrambler_peri_tx_sel : R/W; bitpos: [7:4]; default: 15;
+         *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler: 4'h0
+         *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+         *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+         *  else : none
+         */
+        uint32_t bitscrambler_peri_tx_sel:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_bitscrambler_peri_sel_reg_t;
+
+
+/** Group: HP_TCM_PARITY_INT_RECORD_REG */
+/** Type of tcm_parity_int_record register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tcm_parity_err_int_addr : RO; bitpos: [12:0]; default: 0;
+         *  hp tcm_parity_err_addr
+         */
+        uint32_t tcm_parity_err_int_addr:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} hp_tcm_parity_int_record_reg_t;
+
+
+/** Group: HP L1 CACHE PWR CTRL REG */
+/** Type of l1_cache_pwr_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l1_cache_mem_fo : R/W; bitpos: [5:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_l1_cache_mem_fo:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_l1_cache_pwr_ctrl_reg_t;
+
+
+/** Group: HP L2 CACHE PWR CTRL REG */
+/** Type of l2_cache_pwr_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_cache_mem_fo : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_l2_cache_mem_fo:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_l2_cache_pwr_ctrl_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of cpu_waiti_conf register
+ *  CPU_WAITI configuration register
+ */
+typedef union {
+    struct {
+        /** cpu_wait_mode_force_on : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to force cpu_waiti_clk enable.
+         */
+        uint32_t cpu_wait_mode_force_on:1;
+        /** cpu_waiti_delay_num : R/W; bitpos: [4:1]; default: 0;
+         *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+         *  will close
+         */
+        uint32_t cpu_waiti_delay_num:4;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_cpu_waiti_conf_reg_t;
+
+/** Type of sys_core_debug_runstall_conf register
+ *  Core Debug runstall configure register
+ */
+typedef union {
+    struct {
+        /** sys_core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
+         *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
+         */
+        uint32_t sys_core_debug_runstall_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_core_debug_runstall_conf_reg_t;
+
+/** Type of rsa_pd_ctrl register
+ *  rsa pd ctrl register
+ */
+typedef union {
+    struct {
+        /** rsa_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down rsa internal memory.
+         */
+        uint32_t rsa_mem_force_pd:1;
+        /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up rsa internal memory
+         */
+        uint32_t rsa_mem_force_pu:1;
+        /** rsa_mem_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power down rsa internal memory.
+         */
+        uint32_t rsa_mem_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_rsa_pd_ctrl_reg_t;
+
+/** Type of ecc_pd_ctrl register
+ *  ecc pd ctrl register
+ */
+typedef union {
+    struct {
+        /** ecc_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down ecc internal memory.
+         */
+        uint32_t ecc_mem_force_pd:1;
+        /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up ecc internal memory
+         */
+        uint32_t ecc_mem_force_pu:1;
+        /** ecc_mem_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power down ecc internal memory.
+         */
+        uint32_t ecc_mem_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_ecc_pd_ctrl_reg_t;
+
+/** Type of rng_cfg register
+ *  rng cfg register
+ */
+typedef union {
+    struct {
+        /** rng_sample_enable : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rng_sample_enable:1;
+        uint32_t reserved_1:15;
+        /** rng_chain_clk_div_num : R/W; bitpos: [23:16]; default: 0;
+         *  chain clk div num to pad for debug
+         */
+        uint32_t rng_chain_clk_div_num:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_rng_cfg_reg_t;
+
+/** Type of uart_pd_ctrl register
+ *  ecc pd ctrl register
+ */
+typedef union {
+    struct {
+        /** uart_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down hp uart internal memory.
+         */
+        uint32_t uart_mem_force_pd:1;
+        /** uart_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up hp uart  internal memory
+         */
+        uint32_t uart_mem_force_pu:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_uart_pd_ctrl_reg_t;
+
+/** Type of peri_mem_clk_force_on register
+ *  hp peri mem clk force on regpster
+ */
+typedef union {
+    struct {
+        /** rmt_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force on mem clk in rmt
+         */
+        uint32_t rmt_mem_clk_force_on:1;
+        /** bitscrambler_tx_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to force on tx mem clk in bitscrambler
+         */
+        uint32_t bitscrambler_tx_mem_clk_force_on:1;
+        /** bitscrambler_rx_mem_clk_force_on : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force on rx mem clk in bitscrambler
+         */
+        uint32_t bitscrambler_rx_mem_clk_force_on:1;
+        /** gdma_mem_clk_force_on : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force on mem clk in gdma
+         */
+        uint32_t gdma_mem_clk_force_on:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_peri_mem_clk_force_on_reg_t;
+
+/** Type of cpu_wakeup_event register
+ *  cpu wakeup event ctrl register
+ */
+typedef union {
+    struct {
+        /** core0_wakeup_event : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to wake up hp core0
+         */
+        uint32_t core0_wakeup_event:1;
+        /** core1_wakeup_event : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to wake up hp core1
+         */
+        uint32_t core1_wakeup_event:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_cpu_wakeup_event_reg_t;
+
+/** Type of hp2lp_intr_group0_en register
+ *  HpP2LP Interrupt Enable Register Group0
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group0_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group0_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group0_en_reg_t;
+
+/** Type of hp2lp_intr_group1_en register
+ *  HpP2LP Interrupt Enable Register Group1
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group1_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group1_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group1_en_reg_t;
+
+/** Type of hp2lp_intr_group2_en register
+ *  HpP2LP Interrupt Enable Register Group2
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group2_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group2_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group2_en_reg_t;
+
+/** Type of hp2lp_intr_group3_en register
+ *  HpP2LP Interrupt Enable Register Group3
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group3_en : R/W; bitpos: [13:0]; default: 16383;
+         *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group3_en:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group3_en_reg_t;
+
+/** Type of hp2lp_wakeup_group0_en register
+ *  HpP2LP Wakeup Enable Register Group0
+ */
+typedef union {
+    struct {
+        /** h2lp_wakeup_group0_en : R/W; bitpos: [31:0]; default: 0;
+         *  Set each bit to enable corresponding peripheral wakeup to PMU.
+         */
+        uint32_t h2lp_wakeup_group0_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_wakeup_group0_en_reg_t;
+
+/** Type of hp2lp_wakeup_group1_en register
+ *  HpP2LP Wakeup Enable Register Group1
+ */
+typedef union {
+    struct {
+        /** h2lp_wakeup_group1_en : R/W; bitpos: [31:0]; default: 0;
+         *  Set each bit to enable corresponding peripheral wakeup to PMU.
+         */
+        uint32_t h2lp_wakeup_group1_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_wakeup_group1_en_reg_t;
+
+/** Type of hp2lp_wakeup_group2_en register
+ *  HpP2LP Wakeup Enable Register Group2
+ */
+typedef union {
+    struct {
+        /** h2lp_wakeup_group2_en : R/W; bitpos: [31:0]; default: 0;
+         *  Set each bit to enable corresponding peripheral wakeup to PMU.
+         */
+        uint32_t h2lp_wakeup_group2_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_wakeup_group2_en_reg_t;
+
+/** Type of hp2lp_wakeup_group3_en register
+ *  HpP2LP Wakeup Enable Register Group3
+ */
+typedef union {
+    struct {
+        /** h2lp_wakeup_group3_en : R/W; bitpos: [13:0]; default: 0;
+         *  Set each bit to enable corresponding peripheral wakeup to PMU.
+         */
+        uint32_t h2lp_wakeup_group3_en:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_hp2lp_wakeup_group3_en_reg_t;
+
+
+/** Group: HP PERI1 APB POSTW EN REG */
+/** Type of peri1_apb_postw_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** peri1_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  hp_peri1 apb register interface post write enable, 1 will speed up write, but will
+         *  take some time to update value to register
+         */
+        uint32_t peri1_apb_postw_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_peri1_apb_postw_en_reg_t;
+
+
+/** Group: APB Sync Register */
+/** Type of sys_apb_sync_postw_en register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_gmac_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_apb_postw_en:1;
+        /** sys_dsi_host_apb_postw_en : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_dsi_host_apb_postw_en:1;
+        /** sys_csi_host_apb_sync_postw_en : R/W; bitpos: [2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_csi_host_apb_sync_postw_en:1;
+        /** sys_csi_host_apb_async_postw_en : R/W; bitpos: [3]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_csi_host_apb_async_postw_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_apb_sync_postw_en_reg_t;
+
+
+/** Group: GDMA Ctonrol Register */
+/** Type of sys_gdma_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_debug_ch_num : R/W; bitpos: [1:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_debug_ch_num:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_gdma_ctrl_reg_t;
+
+
+/** Group: GMAC Control Register */
+/** Type of sys_gmac_ctrl0 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_pps : RO; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_pps:1;
+        /** sys_sbd_flowctrl : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_sbd_flowctrl:1;
+        /** sys_phy_intf_sel : R/W; bitpos: [4:2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_intf_sel:3;
+        /** sys_gmac_mem_clk_force_on : R/W; bitpos: [5]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_mem_clk_force_on:1;
+        /** sys_gmac_rst_clk_tx_n : RO; bitpos: [6]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_rst_clk_tx_n:1;
+        /** sys_gmac_rst_clk_rx_n : RO; bitpos: [7]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_rst_clk_rx_n:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_sys_gmac_ctrl0_reg_t;
+
+/** Type of sys_gmac_ctrl1 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_timestamp_l : RO; bitpos: [31:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_timestamp_l:32;
+    };
+    uint32_t val;
+} hp_sys_gmac_ctrl1_reg_t;
+
+/** Type of sys_gmac_ctrl2 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_timestamp_h : RO; bitpos: [31:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_timestamp_h:32;
+    };
+    uint32_t val;
+} hp_sys_gmac_ctrl2_reg_t;
+
+
+/** Group: VPU Control Register */
+/** Type of sys_vpu_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ppa_lslp_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ppa_lslp_mem_pd:1;
+        /** sys_jpeg_sdslp_mem_pd : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_sdslp_mem_pd:1;
+        /** sys_jpeg_lslp_mem_pd : R/W; bitpos: [2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_lslp_mem_pd:1;
+        /** sys_jpeg_dslp_mem_pd : R/W; bitpos: [3]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_dslp_mem_pd:1;
+        /** sys_dma2d_lslp_mem_pd : R/W; bitpos: [4]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_dma2d_lslp_mem_pd:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_sys_vpu_ctrl_reg_t;
+
+
+/** Group: USB OTG20 Control Register */
+/** Type of sys_usbotg20_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_otg_phy_test_done : RO; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_test_done:1;
+        /** sys_usb_mem_aux_ctrl : R/W; bitpos: [14:1]; default: 4896;
+         *  N/A
+         */
+        uint32_t sys_usb_mem_aux_ctrl:14;
+        /** sys_phy_suspendm : R/W; bitpos: [15]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_suspendm:1;
+        /** sys_phy_suspend_force_en : R/W; bitpos: [16]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_suspend_force_en:1;
+        /** sys_phy_rstn : R/W; bitpos: [17]; default: 1;
+         *  N/A
+         */
+        uint32_t sys_phy_rstn:1;
+        /** sys_phy_reset_force_en : R/W; bitpos: [18]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_reset_force_en:1;
+        /** sys_phy_pll_force_en : R/W; bitpos: [19]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_pll_force_en:1;
+        /** sys_phy_pll_en : R/W; bitpos: [20]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_pll_en:1;
+        /** sys_otg_suspendm : R/W; bitpos: [21]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_suspendm:1;
+        /** sys_otg_phy_txbitstuff_en : R/W; bitpos: [22]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_txbitstuff_en:1;
+        /** sys_otg_phy_refclk_mode : R/W; bitpos: [23]; default: 1;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_refclk_mode:1;
+        /** sys_otg_phy_bisten : R/W; bitpos: [24]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_bisten:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_usbotg20_ctrl_reg_t;
+
+
+/** Group: HP_TCM_ERR_RESP_CTRL_REG */
+/** Type of tcm_err_resp_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tcm_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on tcm error response
+         */
+        uint32_t tcm_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_tcm_err_resp_ctrl_reg_t;
+
+
+/** Group: HP L2 MEM REFRESH REG */
+/** Type of l2_mem_refresh register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_unit0_refersh_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit0_refersh_en:1;
+        /** reg_l2_mem_unit1_refersh_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit1_refersh_en:1;
+        /** reg_l2_mem_unit2_refersh_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit2_refersh_en:1;
+        /** reg_l2_mem_unit3_refersh_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit3_refersh_en:1;
+        /** reg_l2_mem_unit4_refersh_en : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit4_refersh_en:1;
+        /** reg_l2_mem_unit5_refersh_en : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit5_refersh_en:1;
+        /** reg_l2_mem_refersh_cnt_reset : R/W; bitpos: [6]; default: 1;
+         *  Set 1 to reset l2mem_refresh_cnt
+         */
+        uint32_t reg_l2_mem_refersh_cnt_reset:1;
+        /** reg_l2_mem_unit0_refresh_done : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit0_refresh_done:1;
+        /** reg_l2_mem_unit1_refresh_done : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit1_refresh_done:1;
+        /** reg_l2_mem_unit2_refresh_done : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit2_refresh_done:1;
+        /** reg_l2_mem_unit3_refresh_done : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit3_refresh_done:1;
+        /** reg_l2_mem_unit4_refresh_done : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit4_refresh_done:1;
+        /** reg_l2_mem_unit5_refresh_done : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit5_refresh_done:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} hp_l2_mem_refresh_reg_t;
+
+
+/** Group: HP TCM INIT REG */
+/** Type of tcm_init register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tcm_init_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_tcm_init_en:1;
+        /** reg_tcm_init_cnt_reset : R/W; bitpos: [1]; default: 1;
+         *  Set 1 to reset tcm init cnt
+         */
+        uint32_t reg_tcm_init_cnt_reset:1;
+        /** reg_tcm_init_done : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_tcm_init_done:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_tcm_init_reg_t;
+
+
+/** Group: HP_TCM_PARITY_CHECK_CTRL_REG */
+/** Type of tcm_parity_check_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tcm_parity_check_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on tcm parity check
+         */
+        uint32_t tcm_parity_check_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_tcm_parity_check_ctrl_reg_t;
+
+
+/** Group: HP_DESIGN_FOR_VERIFICATION0 */
+/** Type of design_for_verification0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dfv0 : R/W; bitpos: [31:0]; default: 0;
+         *  register for DV
+         */
+        uint32_t dfv0:32;
+    };
+    uint32_t val;
+} hp_design_for_verification0_reg_t;
+
+
+/** Group: HP_DESIGN_FOR_VERIFICATION1 */
+/** Type of design_for_verification1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dfv1 : R/W; bitpos: [31:0]; default: 0;
+         *  register for DV
+         */
+        uint32_t dfv1:32;
+    };
+    uint32_t val;
+} hp_design_for_verification1_reg_t;
+
+
+/** Group: HP_PSRAM_FLASH_ADDR_INTERCHANGE */
+/** Type of psram_flash_addr_interchange register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** psram_flash_addr_interchange_cpu : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu
+         *  access through cache
+         */
+        uint32_t psram_flash_addr_interchange_cpu:1;
+        /** psram_flash_addr_interchange_dma : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable addr interchange between psram and flash in axi matrix when dma
+         *  device access, lp core access and hp core access through ahb
+         */
+        uint32_t psram_flash_addr_interchange_dma:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_psram_flash_addr_interchange_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of ahb2axi_bresp_err_int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_icm_h2x_bresp_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
+         *  post write mode in ahb2axi.
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_ahb2axi_bresp_err_int_raw_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** cpu_icm_h2x_bresp_err_int_st : RO; bitpos: [31]; default: 0;
+         *  the masked interrupt status of  cpu_icm_h2x_bresp_err
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_st:1;
+    };
+    uint32_t val;
+} hp_ahb2axi_bresp_err_int_st_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** cpu_icm_h2x_bresp_err_int_ena : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to enable cpu_icm_h2x_bresp_err int
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_ena:1;
+    };
+    uint32_t val;
+} hp_ahb2axi_bresp_err_int_ena_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** cpu_icm_h2x_bresp_err_int_clr : WT; bitpos: [31]; default: 0;
+         *  Write 1 to clear cpu_icm_h2x_bresp_err  int
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_clr:1;
+    };
+    uint32_t val;
+} hp_ahb2axi_bresp_err_int_clr_reg_t;
+
+/** Type of core_timeout_int_raw register
+ *  Hp core bus timeout interrupt raw register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  the raw interrupt status of hp core0  ahb timeout
+         */
+        uint32_t core0_ahb_timeout_int_raw:1;
+        /** core1_ahb_timeout_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  the raw interrupt status of hp core1  ahb timeout
+         */
+        uint32_t core1_ahb_timeout_int_raw:1;
+        /** core0_ibus_timeout_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  the raw interrupt status of hp core0  ibus timeout
+         */
+        uint32_t core0_ibus_timeout_int_raw:1;
+        /** core1_ibus_timeout_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  the raw interrupt status of hp core1  ibus timeout
+         */
+        uint32_t core1_ibus_timeout_int_raw:1;
+        /** core0_dbus_timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  the raw interrupt status of hp core0  dbus timeout
+         */
+        uint32_t core0_dbus_timeout_int_raw:1;
+        /** core1_dbus_timeout_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  the raw interrupt status of hp core1  dbus timeout
+         */
+        uint32_t core1_dbus_timeout_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_core_timeout_int_raw_reg_t;
+
+/** Type of core_timeout_int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of hp core0  ahb timeout
+         */
+        uint32_t core0_ahb_timeout_int_st:1;
+        /** core1_ahb_timeout_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of hp core1  ahb timeout
+         */
+        uint32_t core1_ahb_timeout_int_st:1;
+        /** core0_ibus_timeout_int_st : RO; bitpos: [2]; default: 0;
+         *  the masked interrupt status of hp core0  ibus timeout
+         */
+        uint32_t core0_ibus_timeout_int_st:1;
+        /** core1_ibus_timeout_int_st : RO; bitpos: [3]; default: 0;
+         *  the masked interrupt status of hp core1  ibus timeout
+         */
+        uint32_t core1_ibus_timeout_int_st:1;
+        /** core0_dbus_timeout_int_st : RO; bitpos: [4]; default: 0;
+         *  the masked interrupt status of hp core0  dbus timeout
+         */
+        uint32_t core0_dbus_timeout_int_st:1;
+        /** core1_dbus_timeout_int_st : RO; bitpos: [5]; default: 0;
+         *  the masked interrupt status of hp core1  dbus timeout
+         */
+        uint32_t core1_dbus_timeout_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_core_timeout_int_st_reg_t;
+
+/** Type of core_timeout_int_ena register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable hp_core0_ahb_timeout int
+         */
+        uint32_t core0_ahb_timeout_int_ena:1;
+        /** core1_ahb_timeout_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable hp_core1_ahb_timeout int
+         */
+        uint32_t core1_ahb_timeout_int_ena:1;
+        /** core0_ibus_timeout_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable hp_core0_ibus_timeout int
+         */
+        uint32_t core0_ibus_timeout_int_ena:1;
+        /** core1_ibus_timeout_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable hp_core1_ibus_timeout int
+         */
+        uint32_t core1_ibus_timeout_int_ena:1;
+        /** core0_dbus_timeout_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable hp_core0_dbus_timeout int
+         */
+        uint32_t core0_dbus_timeout_int_ena:1;
+        /** core1_dbus_timeout_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable hp_core1_dbus_timeout int
+         */
+        uint32_t core1_dbus_timeout_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_core_timeout_int_ena_reg_t;
+
+/** Type of core_timeout_int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear hp_core0_ahb_timeout int
+         */
+        uint32_t core0_ahb_timeout_int_clr:1;
+        /** core1_ahb_timeout_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear hp_core1_ahb_timeout int
+         */
+        uint32_t core1_ahb_timeout_int_clr:1;
+        /** core0_ibus_timeout_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear hp_core0_ibus_timeout int
+         */
+        uint32_t core0_ibus_timeout_int_clr:1;
+        /** core1_ibus_timeout_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear hp_core1_ibus_timeout int
+         */
+        uint32_t core1_ibus_timeout_int_clr:1;
+        /** core0_dbus_timeout_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear hp_core0_dbus_timeout int
+         */
+        uint32_t core0_dbus_timeout_int_clr:1;
+        /** core1_dbus_timeout_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear hp_core1_dbus_timeout int
+         */
+        uint32_t core1_dbus_timeout_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_core_timeout_int_clr_reg_t;
+
+
+/** Group: HP_L2_MEM_ERR_RESP_CTRL_REG */
+/** Type of l2_mem_err_resp_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** l2_mem_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on l2mem error response
+         */
+        uint32_t l2_mem_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_l2_mem_err_resp_ctrl_reg_t;
+
+
+/** Group: HP_L2_MEM_AHB_BUFFER_CTRL_REG */
+/** Type of l2_mem_ahb_buffer_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** l2_mem_ahb_wrbuffer_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on l2mem ahb wr buffer
+         */
+        uint32_t l2_mem_ahb_wrbuffer_en:1;
+        /** l2_mem_ahb_rdbuffer_en : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to turn on l2mem ahb rd buffer
+         */
+        uint32_t l2_mem_ahb_rdbuffer_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_l2_mem_ahb_buffer_ctrl_reg_t;
+
+
+/** Group: HP_CORE_DMACTIVE_LPCORE_REG */
+/** Type of core_dmactive_lpcore register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_dmactive_lpcore : RO; bitpos: [0]; default: 0;
+         *  hp core dmactive_lpcore value
+         */
+        uint32_t core_dmactive_lpcore:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_core_dmactive_lpcore_reg_t;
+
+
+/** Group: control registers */
+/** Type of core_err_resp_dis register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_err_resp_dis : R/W; bitpos: [2:0]; default: 0;
+         *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
+         *  disable ahb err resp.
+         */
+        uint32_t core_err_resp_dis:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_core_err_resp_dis_reg_t;
+
+
+/** Group: HP GPIO O HYS CTRL0 REG */
+/** Type of gpio_o_hys_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hys_low : R/W; bitpos: [31:0]; default: 0;
+         *  hys control for gpio47~16
+         */
+        uint32_t reg_gpio_0_hys_low:32;
+    };
+    uint32_t val;
+} hp_gpio_o_hys_ctrl0_reg_t;
+
+
+/** Group: HP GPIO O HYS CTRL1 REG */
+/** Type of gpio_o_hys_ctrl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hys_high : R/W; bitpos: [8:0]; default: 0;
+         *  hys control for gpio56~48
+         */
+        uint32_t reg_gpio_0_hys_high:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_gpio_o_hys_ctrl1_reg_t;
+
+
+/** Group: HP USB20OTG PHY ST REG */
+/** Type of usb_otghs_phy_st register
+ *  Usb otg2.0 PHY status register
+ */
+typedef union {
+    struct {
+        /** usb_soft_reset_actv_pdomain : RO; bitpos: [0]; default: 0;
+         *  Todo
+         */
+        uint32_t usb_soft_reset_actv_pdomain:1;
+        /** utmisrp_sessend : RO; bitpos: [1]; default: 0;
+         *  Todo
+         */
+        uint32_t utmisrp_sessend:1;
+        /** utmiotg_vbusvalid : RO; bitpos: [2]; default: 0;
+         *  Todo
+         */
+        uint32_t utmiotg_vbusvalid:1;
+        /** utmisrp_bvalid : RO; bitpos: [3]; default: 0;
+         *  Todo
+         */
+        uint32_t utmisrp_bvalid:1;
+        /** utmisrp_sessvalid : RO; bitpos: [4]; default: 0;
+         *  Todo
+         */
+        uint32_t utmisrp_sessvalid:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_usb_otghs_phy_st_reg_t;
+
+
+/** Group: Status Register */
+/** Type of hp2lp_intr_group0_st register
+ *  HpP2LP Interrupt Status Register Group0
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group0_st : RO; bitpos: [31:0]; default: 0;
+         *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group0_st:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group0_st_reg_t;
+
+/** Type of hp2lp_intr_group1_st register
+ *  HpP2LP Interrupt Enable Register Group1
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group1_st : RO; bitpos: [31:0]; default: 0;
+         *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group1_st:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group1_st_reg_t;
+
+/** Type of hp2lp_intr_group2_st register
+ *  HpP2LP Interrupt Enable Register Group2
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group2_st : RO; bitpos: [31:0]; default: 0;
+         *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group2_st:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group2_st_reg_t;
+
+/** Type of hp2lp_intr_group3_st register
+ *  HpP2LP Interrupt Enable Register Group3
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group3_st : RO; bitpos: [13:0]; default: 0;
+         *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group3_st:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group3_st_reg_t;
+
+
+typedef struct {
+    volatile hp_sys_ver_date_reg_t sys_ver_date;
+    volatile hp_clk_en_reg_t clk_en;
+    uint32_t reserved_008[2];
+    volatile hp_cpu_int_from_cpu_0_reg_t cpu_int_from_cpu_0;
+    volatile hp_cpu_int_from_cpu_1_reg_t cpu_int_from_cpu_1;
+    volatile hp_cpu_int_from_cpu_2_reg_t cpu_int_from_cpu_2;
+    volatile hp_cpu_int_from_cpu_3_reg_t cpu_int_from_cpu_3;
+    volatile hp_cache_clk_config_reg_t cache_clk_config;
+    volatile hp_cache_reset_config_reg_t cache_reset_config;
+    uint32_t reserved_028;
+    volatile hp_sys_dma_addr_ctrl_reg_t sys_dma_addr_ctrl;
+    uint32_t reserved_030;
+    volatile hp_tcm_ram_wrr_config_reg_t tcm_ram_wrr_config;
+    volatile hp_tcm_sw_parity_bwe_mask_reg_t tcm_sw_parity_bwe_mask;
+    volatile hp_tcm_ram_pwr_ctrl0_reg_t tcm_ram_pwr_ctrl0;
+    volatile hp_l2_rom_pwr_ctrl0_reg_t l2_rom_pwr_ctrl0;
+    uint32_t reserved_044[3];
+    volatile hp_probea_ctrl_reg_t probea_ctrl;
+    volatile hp_probeb_ctrl_reg_t probeb_ctrl;
+    uint32_t reserved_058;
+    volatile hp_probe_out_reg_t probe_out;
+    volatile hp_l2_mem_ram_pwr_ctrl0_reg_t l2_mem_ram_pwr_ctrl0;
+    volatile hp_cpu_corestalled_st_reg_t cpu_corestalled_st;
+    uint32_t reserved_068[2];
+    volatile hp_crypto_ctrl_reg_t crypto_ctrl;
+    volatile hp_gpio_o_hold_ctrl0_reg_t gpio_o_hold_ctrl0;
+    volatile hp_gpio_o_hold_ctrl1_reg_t gpio_o_hold_ctrl1;
+    volatile hp_sys_rdn_eco_cs_reg_t sys_rdn_eco_cs;
+    volatile hp_cache_apb_postw_en_reg_t cache_apb_postw_en;
+    volatile hp_l2_mem_subsize_reg_t l2_mem_subsize;
+    uint32_t reserved_088[5];
+    volatile hp_l2_mem_int_raw_reg_t l2_mem_int_raw;
+    volatile hp_l2_mem_int_st_reg_t l2_mem_int_st;
+    volatile hp_l2_mem_int_ena_reg_t l2_mem_int_ena;
+    volatile hp_l2_mem_int_clr_reg_t l2_mem_int_clr;
+    volatile hp_l2_mem_l2_ram_ecc_reg_t l2_mem_l2_ram_ecc;
+    volatile hp_l2_mem_int_record0_reg_t l2_mem_int_record0;
+    volatile hp_l2_mem_int_record1_reg_t l2_mem_int_record1;
+    uint32_t reserved_0b8[3];
+    volatile hp_l2_mem_l2_cache_ecc_reg_t l2_mem_l2_cache_ecc;
+    volatile hp_l1cache_bus0_id_reg_t l1cache_bus0_id;
+    volatile hp_l1cache_bus1_id_reg_t l1cache_bus1_id;
+    uint32_t reserved_0d0[2];
+    volatile hp_l2_mem_rdn_eco_cs_reg_t l2_mem_rdn_eco_cs;
+    volatile hp_l2_mem_rdn_eco_low_reg_t l2_mem_rdn_eco_low;
+    volatile hp_l2_mem_rdn_eco_high_reg_t l2_mem_rdn_eco_high;
+    volatile hp_tcm_rdn_eco_cs_reg_t tcm_rdn_eco_cs;
+    volatile hp_tcm_rdn_eco_low_reg_t tcm_rdn_eco_low;
+    volatile hp_tcm_rdn_eco_high_reg_t tcm_rdn_eco_high;
+    volatile hp_gpio_ded_hold_ctrl_reg_t gpio_ded_hold_ctrl;
+    volatile hp_l2_mem_sw_ecc_bwe_mask_reg_t l2_mem_sw_ecc_bwe_mask;
+    volatile hp_usb20otg_mem_ctrl_reg_t usb20otg_mem_ctrl;
+    volatile hp_tcm_int_raw_reg_t tcm_int_raw;
+    volatile hp_tcm_int_st_reg_t tcm_int_st;
+    volatile hp_tcm_int_ena_reg_t tcm_int_ena;
+    volatile hp_tcm_int_clr_reg_t tcm_int_clr;
+    volatile hp_tcm_parity_int_record_reg_t tcm_parity_int_record;
+    volatile hp_l1_cache_pwr_ctrl_reg_t l1_cache_pwr_ctrl;
+    volatile hp_l2_cache_pwr_ctrl_reg_t l2_cache_pwr_ctrl;
+    volatile hp_cpu_waiti_conf_reg_t cpu_waiti_conf;
+    volatile hp_sys_core_debug_runstall_conf_reg_t sys_core_debug_runstall_conf;
+    volatile hp_core_ahb_timeout_reg_t core_ahb_timeout;
+    volatile hp_core_ibus_timeout_reg_t core_ibus_timeout;
+    volatile hp_core_dbus_timeout_reg_t core_dbus_timeout;
+    uint32_t reserved_12c[3];
+    volatile hp_icm_cpu_h2x_cfg_reg_t icm_cpu_h2x_cfg;
+    volatile hp_peri1_apb_postw_en_reg_t peri1_apb_postw_en;
+    volatile hp_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel;
+    volatile hp_sys_apb_sync_postw_en_reg_t sys_apb_sync_postw_en;
+    volatile hp_sys_gdma_ctrl_reg_t sys_gdma_ctrl;
+    volatile hp_sys_gmac_ctrl0_reg_t sys_gmac_ctrl0;
+    volatile hp_sys_gmac_ctrl1_reg_t sys_gmac_ctrl1;
+    volatile hp_sys_gmac_ctrl2_reg_t sys_gmac_ctrl2;
+    volatile hp_sys_vpu_ctrl_reg_t sys_vpu_ctrl;
+    volatile hp_sys_usbotg20_ctrl_reg_t sys_usbotg20_ctrl;
+    volatile hp_tcm_err_resp_ctrl_reg_t tcm_err_resp_ctrl;
+    volatile hp_l2_mem_refresh_reg_t l2_mem_refresh;
+    volatile hp_tcm_init_reg_t tcm_init;
+    volatile hp_tcm_parity_check_ctrl_reg_t tcm_parity_check_ctrl;
+    volatile hp_design_for_verification0_reg_t design_for_verification0;
+    volatile hp_design_for_verification1_reg_t design_for_verification1;
+    uint32_t reserved_178[2];
+    volatile hp_psram_flash_addr_interchange_reg_t psram_flash_addr_interchange;
+    uint32_t reserved_184;
+    volatile hp_ahb2axi_bresp_err_int_raw_reg_t ahb2axi_bresp_err_int_raw;
+    volatile hp_ahb2axi_bresp_err_int_st_reg_t ahb2axi_bresp_err_int_st;
+    volatile hp_ahb2axi_bresp_err_int_ena_reg_t ahb2axi_bresp_err_int_ena;
+    volatile hp_ahb2axi_bresp_err_int_clr_reg_t ahb2axi_bresp_err_int_clr;
+    volatile hp_l2_mem_err_resp_ctrl_reg_t l2_mem_err_resp_ctrl;
+    volatile hp_l2_mem_ahb_buffer_ctrl_reg_t l2_mem_ahb_buffer_ctrl;
+    volatile hp_core_dmactive_lpcore_reg_t core_dmactive_lpcore;
+    volatile hp_core_err_resp_dis_reg_t core_err_resp_dis;
+    volatile hp_core_timeout_int_raw_reg_t core_timeout_int_raw;
+    volatile hp_core_timeout_int_st_reg_t core_timeout_int_st;
+    volatile hp_core_timeout_int_ena_reg_t core_timeout_int_ena;
+    volatile hp_core_timeout_int_clr_reg_t core_timeout_int_clr;
+    uint32_t reserved_1b8[2];
+    volatile hp_gpio_o_hys_ctrl0_reg_t gpio_o_hys_ctrl0;
+    volatile hp_gpio_o_hys_ctrl1_reg_t gpio_o_hys_ctrl1;
+    uint32_t reserved_1c8[2];
+    volatile hp_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
+    volatile hp_ecc_pd_ctrl_reg_t ecc_pd_ctrl;
+    volatile hp_rng_cfg_reg_t rng_cfg;
+    volatile hp_uart_pd_ctrl_reg_t uart_pd_ctrl;
+    volatile hp_peri_mem_clk_force_on_reg_t peri_mem_clk_force_on;
+    uint32_t reserved_1e4;
+    volatile hp_usb_otghs_phy_st_reg_t usb_otghs_phy_st;
+    volatile hp_cpu_wakeup_event_reg_t cpu_wakeup_event;
+    volatile hp_hp2lp_intr_group0_en_reg_t hp2lp_intr_group0_en;
+    volatile hp_hp2lp_intr_group1_en_reg_t hp2lp_intr_group1_en;
+    volatile hp_hp2lp_intr_group2_en_reg_t hp2lp_intr_group2_en;
+    volatile hp_hp2lp_intr_group3_en_reg_t hp2lp_intr_group3_en;
+    volatile hp_hp2lp_intr_group0_st_reg_t hp2lp_intr_group0_st;
+    volatile hp_hp2lp_intr_group1_st_reg_t hp2lp_intr_group1_st;
+    volatile hp_hp2lp_intr_group2_st_reg_t hp2lp_intr_group2_st;
+    volatile hp_hp2lp_intr_group3_st_reg_t hp2lp_intr_group3_st;
+    volatile hp_hp2lp_wakeup_group0_en_reg_t hp2lp_wakeup_group0_en;
+    volatile hp_hp2lp_wakeup_group1_en_reg_t hp2lp_wakeup_group1_en;
+    volatile hp_hp2lp_wakeup_group2_en_reg_t hp2lp_wakeup_group2_en;
+    volatile hp_hp2lp_wakeup_group3_en_reg_t hp2lp_wakeup_group3_en;
+} hp_dev_t;
+
+extern hp_dev_t HP_SYSTEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_dev_t) == 0x220, "Invalid size of hp_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/huk_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/huk_reg.h
new file mode 100644
index 0000000000..20c44c4d3d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/huk_reg.h
@@ -0,0 +1,230 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HUK_CLK_REG register
+ *  HUK Generator clock gate control register
+ */
+#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
+/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Write 1 to force on register clock gate.
+ */
+#define HUK_CLK_EN    (BIT(0))
+#define HUK_CLK_EN_M  (HUK_CLK_EN_V << HUK_CLK_EN_S)
+#define HUK_CLK_EN_V  0x00000001U
+#define HUK_CLK_EN_S  0
+/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to force on memory clock gate.
+ */
+#define HUK_MEM_CG_FORCE_ON    (BIT(1))
+#define HUK_MEM_CG_FORCE_ON_M  (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
+#define HUK_MEM_CG_FORCE_ON_V  0x00000001U
+#define HUK_MEM_CG_FORCE_ON_S  1
+
+/** HUK_INT_RAW_REG register
+ *  HUK Generator interrupt raw register, valid in level.
+ */
+#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
+/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_RAW    (BIT(0))
+#define HUK_PREP_DONE_INT_RAW_M  (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
+#define HUK_PREP_DONE_INT_RAW_V  0x00000001U
+#define HUK_PREP_DONE_INT_RAW_S  0
+/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_RAW    (BIT(1))
+#define HUK_PROC_DONE_INT_RAW_M  (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
+#define HUK_PROC_DONE_INT_RAW_V  0x00000001U
+#define HUK_PROC_DONE_INT_RAW_S  1
+/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_RAW    (BIT(2))
+#define HUK_POST_DONE_INT_RAW_M  (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
+#define HUK_POST_DONE_INT_RAW_V  0x00000001U
+#define HUK_POST_DONE_INT_RAW_S  2
+
+/** HUK_INT_ST_REG register
+ *  HUK Generator interrupt status register.
+ */
+#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
+/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_ST    (BIT(0))
+#define HUK_PREP_DONE_INT_ST_M  (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
+#define HUK_PREP_DONE_INT_ST_V  0x00000001U
+#define HUK_PREP_DONE_INT_ST_S  0
+/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_ST    (BIT(1))
+#define HUK_PROC_DONE_INT_ST_M  (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
+#define HUK_PROC_DONE_INT_ST_V  0x00000001U
+#define HUK_PROC_DONE_INT_ST_S  1
+/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_ST    (BIT(2))
+#define HUK_POST_DONE_INT_ST_M  (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
+#define HUK_POST_DONE_INT_ST_V  0x00000001U
+#define HUK_POST_DONE_INT_ST_S  2
+
+/** HUK_INT_ENA_REG register
+ *  HUK Generator interrupt enable register.
+ */
+#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
+/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_ENA    (BIT(0))
+#define HUK_PREP_DONE_INT_ENA_M  (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
+#define HUK_PREP_DONE_INT_ENA_V  0x00000001U
+#define HUK_PREP_DONE_INT_ENA_S  0
+/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_ENA    (BIT(1))
+#define HUK_PROC_DONE_INT_ENA_M  (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
+#define HUK_PROC_DONE_INT_ENA_V  0x00000001U
+#define HUK_PROC_DONE_INT_ENA_S  1
+/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_ENA    (BIT(2))
+#define HUK_POST_DONE_INT_ENA_M  (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
+#define HUK_POST_DONE_INT_ENA_V  0x00000001U
+#define HUK_POST_DONE_INT_ENA_S  2
+
+/** HUK_INT_CLR_REG register
+ *  HUK Generator interrupt clear register.
+ */
+#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
+/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_CLR    (BIT(0))
+#define HUK_PREP_DONE_INT_CLR_M  (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
+#define HUK_PREP_DONE_INT_CLR_V  0x00000001U
+#define HUK_PREP_DONE_INT_CLR_S  0
+/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_CLR    (BIT(1))
+#define HUK_PROC_DONE_INT_CLR_M  (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
+#define HUK_PROC_DONE_INT_CLR_V  0x00000001U
+#define HUK_PROC_DONE_INT_CLR_S  1
+/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_CLR    (BIT(2))
+#define HUK_POST_DONE_INT_CLR_M  (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
+#define HUK_POST_DONE_INT_CLR_V  0x00000001U
+#define HUK_POST_DONE_INT_CLR_S  2
+
+/** HUK_CONF_REG register
+ *  HUK Generator configuration register
+ */
+#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
+/** HUK_MODE : R/W; bitpos: [0]; default: 0;
+ *  Set this field to choose the huk process. 1: process huk generate mode. 0: process
+ *  huk recovery mode.
+ */
+#define HUK_MODE    (BIT(0))
+#define HUK_MODE_M  (HUK_MODE_V << HUK_MODE_S)
+#define HUK_MODE_V  0x00000001U
+#define HUK_MODE_S  0
+
+/** HUK_START_REG register
+ *  HUK Generator control register
+ */
+#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
+/** HUK_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to continue HUK Generator operation at LOAD/GAIN state.
+ */
+#define HUK_START    (BIT(0))
+#define HUK_START_M  (HUK_START_V << HUK_START_S)
+#define HUK_START_V  0x00000001U
+#define HUK_START_S  0
+/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to start HUK Generator at IDLE state.
+ */
+#define HUK_CONTINUE    (BIT(1))
+#define HUK_CONTINUE_M  (HUK_CONTINUE_V << HUK_CONTINUE_S)
+#define HUK_CONTINUE_V  0x00000001U
+#define HUK_CONTINUE_S  1
+
+/** HUK_STATE_REG register
+ *  HUK Generator state register
+ */
+#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
+/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
+ *  The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+ */
+#define HUK_STATE    0x00000003U
+#define HUK_STATE_M  (HUK_STATE_V << HUK_STATE_S)
+#define HUK_STATE_V  0x00000003U
+#define HUK_STATE_S  0
+
+/** HUK_STATUS_REG register
+ *  HUK Generator HUK status register
+ */
+#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
+/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
+ *  2: HUK is generated but invalid. 3: reserved.
+ */
+#define HUK_STATUS    0x00000003U
+#define HUK_STATUS_M  (HUK_STATUS_V << HUK_STATUS_S)
+#define HUK_STATUS_V  0x00000003U
+#define HUK_STATUS_S  0
+/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
+ *  The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
+ *  are in the PUF SRAM. 7: Error Level, HUK is invalid.
+ */
+#define HUK_RISK_LEVEL    0x00000007U
+#define HUK_RISK_LEVEL_M  (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
+#define HUK_RISK_LEVEL_V  0x00000007U
+#define HUK_RISK_LEVEL_S  2
+/** HUK_UPDATE_REQ : RO; bitpos: [5]; default: 0;
+ *  The update request of HUK info. 0: User can update HUK info according to the risk
+ *  level. 1: The HUK info is expired, and user need to update it.
+ */
+#define HUK_UPDATE_REQ    (BIT(5))
+#define HUK_UPDATE_REQ_M  (HUK_UPDATE_REQ_V << HUK_UPDATE_REQ_S)
+#define HUK_UPDATE_REQ_V  0x00000001U
+#define HUK_UPDATE_REQ_S  5
+
+/** HUK_DATE_REG register
+ *  Version control register
+ */
+#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
+/** HUK_DATE : R/W; bitpos: [27:0]; default: 37765232;
+ *  HUK Generator version control register.
+ */
+#define HUK_DATE    0x0FFFFFFFU
+#define HUK_DATE_M  (HUK_DATE_V << HUK_DATE_S)
+#define HUK_DATE_V  0x0FFFFFFFU
+#define HUK_DATE_S  0
+
+/** HUK_INFO_MEM register
+ *  The memory that stores HUK info.
+ */
+#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
+#define HUK_INFO_MEM_SIZE_BYTES 384
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/huk_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/huk_struct.h
new file mode 100644
index 0000000000..ed5f416920
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/huk_struct.h
@@ -0,0 +1,247 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Clock gate register */
+/** Type of clk register
+ *  HUK Generator clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_en:1;
+        /** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to force on memory clock gate.
+         */
+        uint32_t mem_cg_force_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} huk_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  HUK Generator interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_raw:1;
+        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_raw:1;
+        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_raw_reg_t;
+
+/** Type of int_st register
+ *  HUK Generator interrupt status register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_st:1;
+        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_st:1;
+        /** post_done_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_st_reg_t;
+
+/** Type of int_ena register
+ *  HUK Generator interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_ena:1;
+        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_ena:1;
+        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  HUK Generator interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_clr:1;
+        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_clr:1;
+        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_clr_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  HUK Generator configuration register
+ */
+typedef union {
+    struct {
+        /** mode : R/W; bitpos: [0]; default: 0;
+         *  Set this field to choose the huk process. 1: process huk generate mode. 0: process
+         *  huk recovery mode.
+         */
+        uint32_t mode:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} huk_conf_reg_t;
+
+
+/** Group: Control registers */
+/** Type of start register
+ *  HUK Generator control register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to continue HUK Generator operation at LOAD/GAIN state.
+         */
+        uint32_t start:1;
+        /** continue : WT; bitpos: [1]; default: 0;
+         *  Write 1 to start HUK Generator at IDLE state.
+         */
+        uint32_t conti:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} huk_start_reg_t;
+
+
+/** Group: State registers */
+/** Type of state register
+ *  HUK Generator state register
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [1:0]; default: 0;
+         *  The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+         */
+        uint32_t state:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} huk_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of status register
+ *  HUK Generator HUK status register
+ */
+typedef union {
+    struct {
+        /** status : RO; bitpos: [1:0]; default: 0;
+         *  The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
+         *  2: HUK is generated but invalid. 3: reserved.
+         */
+        uint32_t status:2;
+        /** risk_level : RO; bitpos: [4:2]; default: 0;
+         *  The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
+         *  are in the PUF SRAM. 7: Error Level, HUK is invalid.
+         */
+        uint32_t risk_level:3;
+        /** update_req : RO; bitpos: [5]; default: 0;
+         *  The update request of HUK info. 0: User can update HUK info according to the risk
+         *  level. 1: The HUK info is expired, and user need to update it.
+         */
+        uint32_t update_req:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} huk_status_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37765232;
+         *  HUK Generator version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} huk_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile huk_clk_reg_t clk;
+    volatile huk_int_raw_reg_t int_raw;
+    volatile huk_int_st_reg_t int_st;
+    volatile huk_int_ena_reg_t int_ena;
+    volatile huk_int_clr_reg_t int_clr;
+    uint32_t reserved_018[2];
+    volatile huk_conf_reg_t conf;
+    volatile huk_start_reg_t start;
+    volatile huk_state_reg_t state;
+    uint32_t reserved_02c[2];
+    volatile huk_status_reg_t status;
+    uint32_t reserved_038[49];
+    volatile huk_date_reg_t date;
+    volatile uint32_t info[96];
+} huk_dev_t;
+
+extern huk_dev_t HUK;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_reg.h
new file mode 100644
index 0000000000..dc16cfa416
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_reg.h
@@ -0,0 +1,301 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2C_ANA_MST_I2C0_CTRL_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
+/** I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_CTRL    0x01FFFFFFU
+#define I2C_ANA_MST_I2C0_CTRL_M  (I2C_ANA_MST_I2C0_CTRL_V << I2C_ANA_MST_I2C0_CTRL_S)
+#define I2C_ANA_MST_I2C0_CTRL_V  0x01FFFFFFU
+#define I2C_ANA_MST_I2C0_CTRL_S  0
+/** I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_BUSY    (BIT(25))
+#define I2C_ANA_MST_I2C0_BUSY_M  (I2C_ANA_MST_I2C0_BUSY_V << I2C_ANA_MST_I2C0_BUSY_S)
+#define I2C_ANA_MST_I2C0_BUSY_V  0x00000001U
+#define I2C_ANA_MST_I2C0_BUSY_S  25
+
+/** I2C_ANA_MST_I2C1_CTRL_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
+/** I2C_ANA_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_CTRL    0x01FFFFFFU
+#define I2C_ANA_MST_I2C1_CTRL_M  (I2C_ANA_MST_I2C1_CTRL_V << I2C_ANA_MST_I2C1_CTRL_S)
+#define I2C_ANA_MST_I2C1_CTRL_V  0x01FFFFFFU
+#define I2C_ANA_MST_I2C1_CTRL_S  0
+/** I2C_ANA_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_BUSY    (BIT(25))
+#define I2C_ANA_MST_I2C1_BUSY_M  (I2C_ANA_MST_I2C1_BUSY_V << I2C_ANA_MST_I2C1_BUSY_S)
+#define I2C_ANA_MST_I2C1_BUSY_V  0x00000001U
+#define I2C_ANA_MST_I2C1_BUSY_S  25
+
+/** I2C_ANA_MST_I2C0_CONF_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
+/** I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_CONF    0x00FFFFFFU
+#define I2C_ANA_MST_I2C0_CONF_M  (I2C_ANA_MST_I2C0_CONF_V << I2C_ANA_MST_I2C0_CONF_S)
+#define I2C_ANA_MST_I2C0_CONF_V  0x00FFFFFFU
+#define I2C_ANA_MST_I2C0_CONF_S  0
+/** I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_STATUS    0x000000FFU
+#define I2C_ANA_MST_I2C0_STATUS_M  (I2C_ANA_MST_I2C0_STATUS_V << I2C_ANA_MST_I2C0_STATUS_S)
+#define I2C_ANA_MST_I2C0_STATUS_V  0x000000FFU
+#define I2C_ANA_MST_I2C0_STATUS_S  24
+
+/** I2C_ANA_MST_I2C1_CONF_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc)
+/** I2C_ANA_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_CONF    0x00FFFFFFU
+#define I2C_ANA_MST_I2C1_CONF_M  (I2C_ANA_MST_I2C1_CONF_V << I2C_ANA_MST_I2C1_CONF_S)
+#define I2C_ANA_MST_I2C1_CONF_V  0x00FFFFFFU
+#define I2C_ANA_MST_I2C1_CONF_S  0
+/** I2C_ANA_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_STATUS    0x000000FFU
+#define I2C_ANA_MST_I2C1_STATUS_M  (I2C_ANA_MST_I2C1_STATUS_V << I2C_ANA_MST_I2C1_STATUS_S)
+#define I2C_ANA_MST_I2C1_STATUS_V  0x000000FFU
+#define I2C_ANA_MST_I2C1_STATUS_S  24
+
+/** I2C_ANA_MST_I2C_BURST_CONF_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
+/** I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL    0xFFFFFFFFU
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M  (I2C_ANA_MST_I2C_MST_BURST_CTRL_V << I2C_ANA_MST_I2C_MST_BURST_CTRL_S)
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V  0xFFFFFFFFU
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S  0
+
+/** I2C_ANA_MST_I2C_BURST_STATUS_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
+/** I2C_ANA_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST_BURST_DONE    (BIT(0))
+#define I2C_ANA_MST_I2C_MST_BURST_DONE_M  (I2C_ANA_MST_I2C_MST_BURST_DONE_V << I2C_ANA_MST_I2C_MST_BURST_DONE_S)
+#define I2C_ANA_MST_I2C_MST_BURST_DONE_V  0x00000001U
+#define I2C_ANA_MST_I2C_MST_BURST_DONE_S  0
+/** I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG    (BIT(1))
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M  (I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S)
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V  0x00000001U
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S  1
+/** I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG    (BIT(2))
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M  (I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S)
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V  0x00000001U
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S  2
+/** I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W; bitpos: [31:20]; default: 1024;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT    0x00000FFFU
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M  (I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V << I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S)
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V  0x00000FFFU
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S  20
+
+/** I2C_ANA_MST_ANA_CONF0_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
+/** I2C_ANA_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF0    0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF0_M  (I2C_ANA_MST_ANA_CONF0_V << I2C_ANA_MST_ANA_CONF0_S)
+#define I2C_ANA_MST_ANA_CONF0_V  0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF0_S  0
+/** I2C_ANA_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_STATUS0    0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS0_M  (I2C_ANA_MST_ANA_STATUS0_V << I2C_ANA_MST_ANA_STATUS0_S)
+#define I2C_ANA_MST_ANA_STATUS0_V  0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS0_S  24
+
+/** I2C_ANA_MST_ANA_CONF1_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c)
+/** I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF1    0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF1_M  (I2C_ANA_MST_ANA_CONF1_V << I2C_ANA_MST_ANA_CONF1_S)
+#define I2C_ANA_MST_ANA_CONF1_V  0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF1_S  0
+/** I2C_ANA_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_STATUS1    0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS1_M  (I2C_ANA_MST_ANA_STATUS1_V << I2C_ANA_MST_ANA_STATUS1_S)
+#define I2C_ANA_MST_ANA_STATUS1_V  0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS1_S  24
+
+/** I2C_ANA_MST_ANA_CONF2_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
+/** I2C_ANA_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF2    0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF2_M  (I2C_ANA_MST_ANA_CONF2_V << I2C_ANA_MST_ANA_CONF2_S)
+#define I2C_ANA_MST_ANA_CONF2_V  0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF2_S  0
+/** I2C_ANA_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_STATUS2    0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS2_M  (I2C_ANA_MST_ANA_STATUS2_V << I2C_ANA_MST_ANA_STATUS2_S)
+#define I2C_ANA_MST_ANA_STATUS2_V  0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS2_S  24
+
+/** I2C_ANA_MST_I2C0_CTRL1_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
+/** I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR    0x0000003FU
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M  (I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V  0x0000003FU
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S  0
+/** I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD    0x0000001FU
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M  (I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V  0x0000001FU
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S  6
+
+/** I2C_ANA_MST_I2C1_CTRL1_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
+/** I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR    0x0000003FU
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M  (I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V  0x0000003FU
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S  0
+/** I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD    0x0000001FU
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M  (I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V  0x0000001FU
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S  6
+
+/** I2C_ANA_MST_HW_I2C_CTRL_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c)
+/** I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
+ *  need des
+ */
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR    0x0000003FU
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M  (I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V  0x0000003FU
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S  0
+/** I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
+ *  need des
+ */
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD    0x0000001FU
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M  (I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V  0x0000001FU
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S  6
+/** I2C_ANA_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ARBITER_DIS    (BIT(11))
+#define I2C_ANA_MST_ARBITER_DIS_M  (I2C_ANA_MST_ARBITER_DIS_V << I2C_ANA_MST_ARBITER_DIS_S)
+#define I2C_ANA_MST_ARBITER_DIS_V  0x00000001U
+#define I2C_ANA_MST_ARBITER_DIS_S  11
+
+/** I2C_ANA_MST_NOUSE_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
+/** I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST_NOUSE    0xFFFFFFFFU
+#define I2C_ANA_MST_I2C_MST_NOUSE_M  (I2C_ANA_MST_I2C_MST_NOUSE_V << I2C_ANA_MST_I2C_MST_NOUSE_S)
+#define I2C_ANA_MST_I2C_MST_NOUSE_V  0xFFFFFFFFU
+#define I2C_ANA_MST_I2C_MST_NOUSE_S  0
+
+/** I2C_ANA_MST_CLK160M_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_CLK160M_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
+/** I2C_ANA_MST_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M    (BIT(0))
+#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_M  (I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V << I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S)
+#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V  0x00000001U
+#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S  0
+
+/** I2C_ANA_MST_DATE_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x38)
+/** I2C_ANA_MST_DATE : R/W; bitpos: [27:0]; default: 36717104;
+ *  need des
+ */
+#define I2C_ANA_MST_DATE    0x0FFFFFFFU
+#define I2C_ANA_MST_DATE_M  (I2C_ANA_MST_DATE_V << I2C_ANA_MST_DATE_S)
+#define I2C_ANA_MST_DATE_V  0x0FFFFFFFU
+#define I2C_ANA_MST_DATE_S  0
+/** I2C_ANA_MST_I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST_CLK_EN    (BIT(28))
+#define I2C_ANA_MST_I2C_MST_CLK_EN_M  (I2C_ANA_MST_I2C_MST_CLK_EN_V << I2C_ANA_MST_I2C_MST_CLK_EN_S)
+#define I2C_ANA_MST_I2C_MST_CLK_EN_V  0x00000001U
+#define I2C_ANA_MST_I2C_MST_CLK_EN_S  28
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_struct.h
new file mode 100644
index 0000000000..2d3457bffa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_struct.h
@@ -0,0 +1,304 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configure Register */
+/** Type of i2c0_ctrl register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c0_ctrl:25;
+        /** i2c0_busy : RO; bitpos: [25]; default: 0;
+         *  need des
+         */
+        uint32_t i2c0_busy:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c0_ctrl_reg_t;
+
+/** Type of i2c1_ctrl register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c1_ctrl : R/W; bitpos: [24:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c1_ctrl:25;
+        /** i2c1_busy : RO; bitpos: [25]; default: 0;
+         *  need des
+         */
+        uint32_t i2c1_busy:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c1_ctrl_reg_t;
+
+/** Type of i2c0_conf register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c0_conf:24;
+        /** i2c0_status : RO; bitpos: [31:24]; default: 0;
+         *  need des
+         */
+        uint32_t i2c0_status:8;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c0_conf_reg_t;
+
+/** Type of i2c1_conf register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c1_conf : R/W; bitpos: [23:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c1_conf:24;
+        /** i2c1_status : RO; bitpos: [31:24]; default: 0;
+         *  need des
+         */
+        uint32_t i2c1_status:8;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c1_conf_reg_t;
+
+/** Type of i2c_burst_conf register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c_mst_burst_ctrl : R/W; bitpos: [31:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst_burst_ctrl:32;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c_burst_conf_reg_t;
+
+/** Type of i2c_burst_status register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c_mst_burst_done : RO; bitpos: [0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst_burst_done:1;
+        /** i2c_mst0_burst_err_flag : RO; bitpos: [1]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst0_burst_err_flag:1;
+        /** i2c_mst1_burst_err_flag : RO; bitpos: [2]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst1_burst_err_flag:1;
+        uint32_t reserved_3:17;
+        /** i2c_mst_burst_timeout_cnt : R/W; bitpos: [31:20]; default: 1024;
+         *  need des
+         */
+        uint32_t i2c_mst_burst_timeout_cnt:12;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c_burst_status_reg_t;
+
+/** Type of ana_conf0 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** ana_conf0 : R/W; bitpos: [23:0]; default: 0;
+         *  need des
+         */
+        uint32_t ana_conf0:24;
+        /** ana_status0 : RO; bitpos: [31:24]; default: 0;
+         *  need des
+         */
+        uint32_t ana_status0:8;
+    };
+    uint32_t val;
+} i2c_ana_mst_ana_conf0_reg_t;
+
+/** Type of ana_conf1 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
+         *  need des
+         */
+        uint32_t ana_conf1:24;
+        /** ana_status1 : RO; bitpos: [31:24]; default: 0;
+         *  need des
+         */
+        uint32_t ana_status1:8;
+    };
+    uint32_t val;
+} i2c_ana_mst_ana_conf1_reg_t;
+
+/** Type of ana_conf2 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** ana_conf2 : R/W; bitpos: [23:0]; default: 0;
+         *  need des
+         */
+        uint32_t ana_conf2:24;
+        /** ana_status2 : RO; bitpos: [31:24]; default: 0;
+         *  need des
+         */
+        uint32_t ana_status2:8;
+    };
+    uint32_t val;
+} i2c_ana_mst_ana_conf2_reg_t;
+
+/** Type of i2c0_ctrl1 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c0_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
+         *  need des
+         */
+        uint32_t i2c0_scl_pulse_dur:6;
+        /** i2c0_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
+         *  need des
+         */
+        uint32_t i2c0_sda_side_guard:5;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c0_ctrl1_reg_t;
+
+/** Type of i2c1_ctrl1 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c1_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
+         *  need des
+         */
+        uint32_t i2c1_scl_pulse_dur:6;
+        /** i2c1_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
+         *  need des
+         */
+        uint32_t i2c1_sda_side_guard:5;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c1_ctrl1_reg_t;
+
+/** Type of hw_i2c_ctrl register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** hw_i2c_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
+         *  need des
+         */
+        uint32_t hw_i2c_scl_pulse_dur:6;
+        /** hw_i2c_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
+         *  need des
+         */
+        uint32_t hw_i2c_sda_side_guard:5;
+        /** arbiter_dis : R/W; bitpos: [11]; default: 0;
+         *  need des
+         */
+        uint32_t arbiter_dis:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2c_ana_mst_hw_i2c_ctrl_reg_t;
+
+/** Type of nouse register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst_nouse:32;
+    };
+    uint32_t val;
+} i2c_ana_mst_nouse_reg_t;
+
+/** Type of clk160m register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** clk_i2c_mst_sel_160m : R/W; bitpos: [0]; default: 0;
+         *  need des
+         */
+        uint32_t clk_i2c_mst_sel_160m:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2c_ana_mst_clk160m_reg_t;
+
+/** Type of date register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36717104;
+         *  need des
+         */
+        uint32_t date:28;
+        /** i2c_mst_clk_en : R/W; bitpos: [28]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} i2c_ana_mst_date_reg_t;
+
+
+typedef struct {
+    volatile i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
+    volatile i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl;
+    volatile i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
+    volatile i2c_ana_mst_i2c1_conf_reg_t i2c1_conf;
+    volatile i2c_ana_mst_i2c_burst_conf_reg_t i2c_burst_conf;
+    volatile i2c_ana_mst_i2c_burst_status_reg_t i2c_burst_status;
+    volatile i2c_ana_mst_ana_conf0_reg_t ana_conf0;
+    volatile i2c_ana_mst_ana_conf1_reg_t ana_conf1;
+    volatile i2c_ana_mst_ana_conf2_reg_t ana_conf2;
+    volatile i2c_ana_mst_i2c0_ctrl1_reg_t i2c0_ctrl1;
+    volatile i2c_ana_mst_i2c1_ctrl1_reg_t i2c1_ctrl1;
+    volatile i2c_ana_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl;
+    volatile i2c_ana_mst_nouse_reg_t nouse;
+    volatile i2c_ana_mst_clk160m_reg_t clk160m;
+    volatile i2c_ana_mst_date_reg_t date;
+} i2c_ana_mst_dev_t;
+
+extern i2c_ana_mst_dev_t I2C_ANA_MST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_ana_mst_dev_t) == 0x3c, "Invalid size of i2c_ana_mst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2c_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i2c_eco5_struct.h
new file mode 100644
index 0000000000..4f3e3789eb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i2c_eco5_struct.h
@@ -0,0 +1,1235 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Timing registers */
+/** Type of scl_low_period register
+ *  Configures the low level width of the SCL
+ *  Clock
+ */
+typedef union {
+    struct {
+        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the low level width of the SCL Clock in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_low_period:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_low_period_reg_t;
+
+/** Type of sda_hold register
+ *  Configures the hold time after a negative SCL edge
+ */
+typedef union {
+    struct {
+        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the time to hold the data after the falling edge of SCL.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_hold_reg_t;
+
+/** Type of sda_sample register
+ *  Configures the sample time after a positive SCL edge
+ */
+typedef union {
+    struct {
+        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the time for sampling SDA.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_sample_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_sample_reg_t;
+
+/** Type of scl_high_period register
+ *  Configures the high level width of SCL
+ */
+typedef union {
+    struct {
+        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures for how long SCL remains high in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_high_period:9;
+        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
+         *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_wait_high_period:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_scl_high_period_reg_t;
+
+/** Type of scl_start_hold register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+typedef union {
+    struct {
+        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the falling edge of SDA and the falling edge of SCL for
+         *  a START condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_start_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_start_hold_reg_t;
+
+/** Type of scl_rstart_setup register
+ *  Configures the delay between the positive
+ *  edge of SCL and the negative edge of SDA
+ */
+typedef union {
+    struct {
+        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the positive edge of SCL and the negative edge of SDA
+         *  for a RESTART condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_rstart_setup_reg_t;
+
+/** Type of scl_stop_hold register
+ *  Configures the delay after the SCL clock
+ *  edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the delay after the STOP condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_hold_reg_t;
+
+/** Type of scl_stop_setup register
+ *  Configures the delay between the SDA and
+ *  SCL positive edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the positive edgeof SCL and the
+         *  positive edge of SDA, in I2C module clock cycles.
+         */
+        uint32_t scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_setup_reg_t;
+
+/** Type of scl_st_time_out register
+ *  SCL status time out register
+ */
+typedef union {
+    struct {
+        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
+         *  more than 23.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_st_time_out_reg_t;
+
+/** Type of scl_main_st_time_out register
+ *  SCL main status time out register
+ */
+typedef union {
+    struct {
+        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be
+         *  no more than 23.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_main_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_main_st_time_out_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of ctr register
+ *  Transmission setting
+ */
+typedef union {
+    struct {
+        /** sda_force_out : R/W; bitpos: [0]; default: 0;
+         *  Configures the SDA output mode.
+         *  0: Open drain output
+         *  1: Direct output
+         */
+        uint32_t sda_force_out:1;
+        /** scl_force_out : R/W; bitpos: [1]; default: 0;
+         *  Configures the SCL output mode.
+         *  0: Open drain output
+         *  1: Direct output
+         */
+        uint32_t scl_force_out:1;
+        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
+         *  Configures the sample mode for SDA.
+         *  0: Sample SDA data on the SCL high level
+         *  1: Sample SDA data on the SCL low level
+         */
+        uint32_t sample_scl_level:1;
+        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
+         *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
+         *  reached the threshold.
+         */
+        uint32_t rx_full_ack_level:1;
+        /** ms_mode : R/W; bitpos: [4]; default: 0;
+         *  Configures the module as an I2C Master or Slave.
+         *  0: Slave
+         *  1: Master
+         */
+        uint32_t ms_mode:1;
+        /** trans_start : WT; bitpos: [5]; default: 0;
+         *  Configures whether the slave starts sending the data in txfifo.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t trans_start:1;
+        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
+         *  Configures to control the sending order for data needing to be sent.
+         *  0: send data from the most significant bit
+         *  1: send data from the least significant bit
+         */
+        uint32_t tx_lsb_first:1;
+        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
+         *  Configures to control the storage order for received data.
+         *  0: receive data from the most significant bit
+         *  1: receive data from the least significant bit
+         */
+        uint32_t rx_lsb_first:1;
+        /** clk_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to gate clock signal for registers.
+         *  0: Support clock only when registers are read or written to by software
+         *  1: Force clock on for registers
+         */
+        uint32_t clk_en:1;
+        /** arbitration_en : R/W; bitpos: [9]; default: 1;
+         *  Configures to enable I2C bus arbitration detection.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t arbitration_en:1;
+        /** fsm_rst : WT; bitpos: [10]; default: 0;
+         *  Configures to reset the SCL_FSM.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t fsm_rst:1;
+        /** conf_upgate : WT; bitpos: [11]; default: 0;
+         *  Configures this bit for synchronization.
+         *  0: No effect
+         *  1: Synchronize
+         */
+        uint32_t conf_upgate:1;
+        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
+         *  Configures to enable slave to send data automatically
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t slv_tx_auto_start_en:1;
+        /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
+         *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
+         *  0: Not check
+         *  1: Check
+         */
+        uint32_t addr_10bit_rw_check_en:1;
+        /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
+         *  Configures to support the 7 bit general call function.
+         *  0: Not support
+         *  1: Support
+         */
+        uint32_t addr_broadcasting_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_ctr_reg_t;
+
+/** Type of to register
+ *  Setting time out control for receiving data
+ */
+typedef union {
+    struct {
+        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the timeout threshold period for SCL stucking at high or low level. The
+         *  actual period is 2\^{}(reg_time_out_value).
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t time_out_value:5;
+        /** time_out_en : R/W; bitpos: [5]; default: 0;
+         *  Configures to enable time out control.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t time_out_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i2c_to_reg_t;
+
+/** Type of slave_addr register
+ *  Local slave address setting
+ */
+typedef union {
+    struct {
+        /** slave_addr : R/W; bitpos: [14:0]; default: 0;
+         *  Configure the slave address of I2C Slave.
+         */
+        uint32_t slave_addr:15;
+        uint32_t reserved_15:16;
+        /** addr_10bit_en : R/W; bitpos: [31]; default: 0;
+         *  Configures to enable the slave 10-bit addressing mode in master mode.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t addr_10bit_en:1;
+    };
+    uint32_t val;
+} i2c_slave_addr_reg_t;
+
+/** Type of fifo_conf register
+ *  FIFO configuration register
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
+         *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
+         *  I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0],
+         *  I2C_RXFIFO_WM_INT_RAW bit will be valid.
+         *  \tododone{For CJ, please check this description. I habe doubt about
+         *  reg_reg_fifo_prt_en.CJ: modified}
+         */
+        uint32_t rxfifo_wm_thrhd:5;
+        /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
+         *  Configures the water mark threshold of TXFIFO in nonfifo access mode.  When
+         *  I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0],
+         *  I2C_TXFIFO_WM_INT_RAW bit will be valid.
+         */
+        uint32_t txfifo_wm_thrhd:5;
+        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
+         *  Configures to enable APB nonfifo access.
+         */
+        uint32_t nonfifo_en:1;
+        /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
+         *  Configures the slave to enable dual address mode. When this mode is enabled, the
+         *  byte received after the I2C address byte represents the offset address in the I2C
+         *  Slave RAM.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t fifo_addr_cfg_en:1;
+        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
+         *  Configures to reset RXFIFO.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t rx_fifo_rst:1;
+        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
+         *  Configures to reset TXFIFO.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t tx_fifo_rst:1;
+        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
+         *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
+         *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t fifo_prt_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_fifo_conf_reg_t;
+
+/** Type of filter_cfg register
+ *  SCL and SDA filter configuration register
+ */
+typedef union {
+    struct {
+        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_filter_thres:4;
+        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_filter_thres:4;
+        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
+         *  Configures to enable the filter function for SCL.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t scl_filter_en:1;
+        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
+         *  Configures to enable the filter function for SDA.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t sda_filter_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} i2c_filter_cfg_reg_t;
+
+/** Type of scl_sp_conf register
+ *  Power configuration register
+ */
+typedef union {
+    struct {
+        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
+         *  equals to I2C_SCL_RST_SLV_NUM[4:0].
+         */
+        uint32_t scl_rst_slv_en:1;
+        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
+         *  Configure the pulses of SCL generated in I2C master mode.
+         *  Valid when I2C_SCL_RST_SLV_EN is 1.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_rst_slv_num:5;
+        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
+         *  Configures to power down the I2C output SCL line.
+         *  0: Not power down.
+         *  1: Not work and power down.
+         *  Valid only when I2C_SCL_FORCE_OUT is 1.
+         */
+        uint32_t scl_pd_en:1;
+        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
+         *  Configures to power down the I2C output SDA line.
+         *  0: Not power down.
+         *  1: Not work and power down.
+         *  Valid only when I2C_SDA_FORCE_OUT is 1.
+         */
+        uint32_t sda_pd_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_scl_sp_conf_reg_t;
+
+/** Type of scl_stretch_conf register
+ *  Set SCL stretch of I2C slave
+ */
+typedef union {
+    struct {
+        /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
+         *  Configures the time period to release the SCL line from stretching to avoid timing
+         *  violation. Usually it should be larger than the SDA setup time.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t stretch_protect_num:10;
+        /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
+         *  Configures to enable slave SCL stretch function. The SCL output line will be
+         *  stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The
+         *  stretch cause can be seen in I2C_STRETCH_CAUSE.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t slave_scl_stretch_en:1;
+        /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
+         *  Configures to clear the I2C slave SCL stretch function.
+         *  0: No effect
+         *  1: Clear
+         */
+        uint32_t slave_scl_stretch_clr:1;
+        /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
+         *  Configures to enable the function for slave to control ACK level.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t slave_byte_ack_ctl_en:1;
+        /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
+         *  Set the ACK level when slave controlling ACK level function enables.
+         *  0: Low level
+         *  1: High level
+         */
+        uint32_t slave_byte_ack_lvl:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i2c_scl_stretch_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of sr register
+ *  Describe I2C work status
+ */
+typedef union {
+    struct {
+        /** resp_rec : RO; bitpos: [0]; default: 0;
+         *  Represents the received ACK value in master mode or slave mode.
+         *  0: ACK
+         *  1: NACK.
+         */
+        uint32_t resp_rec:1;
+        /** slave_rw : RO; bitpos: [1]; default: 0;
+         *  Represents the transfer direction in slave mode.
+         *  1: Master reads from slave
+         *  0: Master writes to slave.
+         */
+        uint32_t slave_rw:1;
+        uint32_t reserved_2:1;
+        /** arb_lost : RO; bitpos: [3]; default: 0;
+         *  Represents whether the I2C controller loses control of SCL line.
+         *  0: No arbitration lost
+         *  1: Arbitration lost
+         */
+        uint32_t arb_lost:1;
+        /** bus_busy : RO; bitpos: [4]; default: 0;
+         *  Represents the I2C bus state.
+         *  1: The I2C bus is busy transferring data
+         *  0: The I2C bus is in idle state.
+         */
+        uint32_t bus_busy:1;
+        /** slave_addressed : RO; bitpos: [5]; default: 0;
+         *  Represents whether the address sent by the master is equal to the address of the
+         *  slave.
+         *  Valid only when the module is configured as an I2C Slave.
+         *  0: Not equal
+         *  1: Equal
+         */
+        uint32_t slave_addressed:1;
+        uint32_t reserved_6:2;
+        /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
+         *  Represents the number of data bytes received in RAM.
+         */
+        uint32_t rxfifo_cnt:6;
+        /** stretch_cause : RO; bitpos: [15:14]; default: 3;
+         *  Represents the cause of SCL clocking stretching in slave mode.
+         *  0: Stretching SCL low when the master starts to read data.
+         *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
+         *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
+         */
+        uint32_t stretch_cause:2;
+        uint32_t reserved_16:2;
+        /** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
+         *  Represents the number of data bytes to be sent.
+         */
+        uint32_t txfifo_cnt:6;
+        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
+         *  Represents the states of the I2C module state machine.
+         *  0: Idle
+         *  1: Address shift
+         *  2: ACK address
+         *  3: Rx data
+         *  4: Tx data
+         *  5: Send ACK
+         *  6: Wait ACK
+         */
+        uint32_t scl_main_state_last:3;
+        uint32_t reserved_27:1;
+        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
+         *  Represents the states of the state machine used to produce SCL.
+         *  0: Idle
+         *  1: Start
+         *  2: Negative edge
+         *  3: Low
+         *  4: Positive edge
+         *  5: High
+         *  6: Stop
+         */
+        uint32_t scl_state_last:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2c_sr_reg_t;
+
+/** Type of fifo_st register
+ *  FIFO status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
+         *  Represents the offset address of the APB reading from RXFIFO.
+         */
+        uint32_t rxfifo_raddr:5;
+        /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
+         *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
+         */
+        uint32_t rxfifo_waddr:5;
+        /** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
+         *  Represents the offset address of i2c module reading from TXFIFO.
+         */
+        uint32_t txfifo_raddr:5;
+        /** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
+         *  Represents the offset address of APB bus writing to TXFIFO.
+         */
+        uint32_t txfifo_waddr:5;
+        uint32_t reserved_20:2;
+        /** slave_rw_point : RO; bitpos: [29:22]; default: 0;
+         *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
+         *  I2C slave mode.
+         */
+        uint32_t slave_rw_point:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2c_fifo_st_reg_t;
+
+/** Type of data register
+ *  Rx FIFO read data
+ */
+typedef union {
+    struct {
+        /** fifo_rdata : HRO; bitpos: [7:0]; default: 0;
+         *  Represents the value of RXFIFO read data.
+         */
+        uint32_t fifo_rdata:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_data_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_raw:1;
+        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
+         *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_raw:1;
+        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_raw:1;
+        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_raw:1;
+        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_raw:1;
+        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_raw:1;
+        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_raw:1;
+        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_raw:1;
+        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_raw:1;
+        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_raw:1;
+        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_raw:1;
+        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_raw:1;
+        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_raw:1;
+        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  The raw interrupt status of I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_raw:1;
+        /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_raw:1;
+        /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
+         *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_raw:1;
+        /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_raw:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_clr:1;
+        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_clr:1;
+        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_clr:1;
+        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_clr:1;
+        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_clr:1;
+        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_clr:1;
+        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_clr:1;
+        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_clr:1;
+        /** nack_int_clr : WT; bitpos: [10]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_clr:1;
+        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_clr:1;
+        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_clr:1;
+        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
+         *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_clr:1;
+        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
+         *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_clr:1;
+        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  Write 1 to clear I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_clr:1;
+        /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_clr:1;
+        /** general_call_int_clr : WT; bitpos: [17]; default: 0;
+         *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_clr:1;
+        /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_clr:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_ena:1;
+        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_ena:1;
+        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_ena:1;
+        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_ena:1;
+        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_ena:1;
+        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_ena:1;
+        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_ena:1;
+        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_ena:1;
+        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_ena:1;
+        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_ena:1;
+        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_ena:1;
+        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Write 1 to enable I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_ena:1;
+        /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_ena:1;
+        /** general_call_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_ena:1;
+        /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_ena:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_ena_reg_t;
+
+/** Type of int_status register
+ *  Status of captured I2C communication events
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_st:1;
+        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_st:1;
+        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_st:1;
+        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_st:1;
+        /** time_out_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_st:1;
+        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_st:1;
+        /** nack_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_st:1;
+        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_st:1;
+        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_st:1;
+        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_st:1;
+        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_st:1;
+        /** det_start_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status status of I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_st:1;
+        /** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_st:1;
+        /** general_call_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_st:1;
+        /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_st:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_status_reg_t;
+
+
+/** Group: Command registers */
+/** Type of comd0 register
+ *  I2C command register 0
+ */
+typedef union {
+    struct {
+        /** command0 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 0.
+         *  It consists of three parts:
+         *  op_code is the command
+         *  1: WRITE
+         *  2: STOP
+         *  3: READ
+         *  4: END
+         *  6: RSTART
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure  for more information.
+         *  \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}"
+         */
+        uint32_t command0:14;
+        uint32_t reserved_14:17;
+        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 0 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command0_done:1;
+    };
+    uint32_t val;
+} i2c_comd0_reg_t;
+
+/** Type of comd1 register
+ *  I2C command register 1
+ */
+typedef union {
+    struct {
+        /** command1 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 1.
+         *  See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command1:14;
+        uint32_t reserved_14:17;
+        /** command1_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 1 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command1_done:1;
+    };
+    uint32_t val;
+} i2c_comd1_reg_t;
+
+/** Type of comd2 register
+ *  I2C command register 2
+ */
+typedef union {
+    struct {
+        /** command2 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 2. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command2:14;
+        uint32_t reserved_14:17;
+        /** command2_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 2 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command2_done:1;
+    };
+    uint32_t val;
+} i2c_comd2_reg_t;
+
+/** Type of comd3 register
+ *  I2C command register 3
+ */
+typedef union {
+    struct {
+        /** command3 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 3. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command3:14;
+        uint32_t reserved_14:17;
+        /** command3_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 3 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command3_done:1;
+    };
+    uint32_t val;
+} i2c_comd3_reg_t;
+
+/** Type of comd4 register
+ *  I2C command register 4
+ */
+typedef union {
+    struct {
+        /** command4 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 4. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command4:14;
+        uint32_t reserved_14:17;
+        /** command4_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 4 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command4_done:1;
+    };
+    uint32_t val;
+} i2c_comd4_reg_t;
+
+/** Type of comd5 register
+ *  I2C command register 5
+ */
+typedef union {
+    struct {
+        /** command5 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 5. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command5:14;
+        uint32_t reserved_14:17;
+        /** command5_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 5 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command5_done:1;
+    };
+    uint32_t val;
+} i2c_comd5_reg_t;
+
+/** Type of comd6 register
+ *  I2C command register 6
+ */
+typedef union {
+    struct {
+        /** command6 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 6. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command6:14;
+        uint32_t reserved_14:17;
+        /** command6_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 6 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command6_done:1;
+    };
+    uint32_t val;
+} i2c_comd6_reg_t;
+
+/** Type of comd7 register
+ *  I2C command register 7
+ */
+typedef union {
+    struct {
+        /** command7 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 7. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command7:14;
+        uint32_t reserved_14:17;
+        /** command7_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 7 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command7_done:1;
+    };
+    uint32_t val;
+} i2c_comd7_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 37765248;
+         *  Version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} i2c_date_reg_t;
+
+
+/** Group: Address register */
+/** Type of txfifo_start_addr register
+ *  I2C TXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Represents the I2C txfifo first address.
+         */
+        uint32_t txfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_txfifo_start_addr_reg_t;
+
+/** Type of rxfifo_start_addr register
+ *  I2C RXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Represents the I2C rxfifo first address.
+         */
+        uint32_t rxfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_rxfifo_start_addr_reg_t;
+
+
+typedef struct {
+    volatile i2c_scl_low_period_reg_t scl_low_period;
+    volatile i2c_ctr_reg_t ctr;
+    volatile i2c_sr_reg_t sr;
+    volatile i2c_to_reg_t to;
+    volatile i2c_slave_addr_reg_t slave_addr;
+    volatile i2c_fifo_st_reg_t fifo_st;
+    volatile i2c_fifo_conf_reg_t fifo_conf;
+    volatile i2c_data_reg_t data;
+    volatile i2c_int_raw_reg_t int_raw;
+    volatile i2c_int_clr_reg_t int_clr;
+    volatile i2c_int_ena_reg_t int_ena;
+    volatile i2c_int_status_reg_t int_status;
+    volatile i2c_sda_hold_reg_t sda_hold;
+    volatile i2c_sda_sample_reg_t sda_sample;
+    volatile i2c_scl_high_period_reg_t scl_high_period;
+    uint32_t reserved_03c;
+    volatile i2c_scl_start_hold_reg_t scl_start_hold;
+    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
+    volatile i2c_filter_cfg_reg_t filter_cfg;
+    uint32_t reserved_054;
+    volatile i2c_comd0_reg_t comd0;
+    volatile i2c_comd1_reg_t comd1;
+    volatile i2c_comd2_reg_t comd2;
+    volatile i2c_comd3_reg_t comd3;
+    volatile i2c_comd4_reg_t comd4;
+    volatile i2c_comd5_reg_t comd5;
+    volatile i2c_comd6_reg_t comd6;
+    volatile i2c_comd7_reg_t comd7;
+    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
+    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
+    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
+    volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
+    uint32_t reserved_088[28];
+    volatile i2c_date_reg_t date;
+    uint32_t reserved_0fc;
+    volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
+    uint32_t reserved_104[31];
+    volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
+} i2c_dev_t;
+
+extern i2c_dev_t I2C0;
+extern i2c_dev_t I2C1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/i2c_reg.h
new file mode 100644
index 0000000000..0ba382e077
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i2c_reg.h
@@ -0,0 +1,1478 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2C_SCL_LOW_PERIOD_REG register
+ *  Configures the low level width of the SCL
+ *  Clock
+ */
+#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0)
+/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the low level width of the SCL Clock in master mode.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_LOW_PERIOD    0x000001FFU
+#define I2C_SCL_LOW_PERIOD_M  (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
+#define I2C_SCL_LOW_PERIOD_V  0x000001FFU
+#define I2C_SCL_LOW_PERIOD_S  0
+
+/** I2C_CTR_REG register
+ *  Transmission setting
+ */
+#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4)
+/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
+ *  Configures the SDA output mode.
+ *  0: Open drain output
+ *  1: Direct output
+ */
+#define I2C_SDA_FORCE_OUT    (BIT(0))
+#define I2C_SDA_FORCE_OUT_M  (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S)
+#define I2C_SDA_FORCE_OUT_V  0x00000001U
+#define I2C_SDA_FORCE_OUT_S  0
+/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0;
+ *  Configures the SCL output mode.
+ *  0: Open drain output
+ *  1: Direct output
+ */
+#define I2C_SCL_FORCE_OUT    (BIT(1))
+#define I2C_SCL_FORCE_OUT_M  (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S)
+#define I2C_SCL_FORCE_OUT_V  0x00000001U
+#define I2C_SCL_FORCE_OUT_S  1
+/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
+ *  Configures the sample mode for SDA.
+ *  0: Sample SDA data on the SCL high level
+ *  1: Sample SDA data on the SCL low level
+ */
+#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
+#define I2C_SAMPLE_SCL_LEVEL_V  0x00000001U
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
+ *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
+ *  reached the threshold.
+ */
+#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_M  (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
+#define I2C_RX_FULL_ACK_LEVEL_V  0x00000001U
+#define I2C_RX_FULL_ACK_LEVEL_S  3
+/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0;
+ *  Configures the module as an I2C Master or Slave.
+ *  0: Slave
+ *  1: Master
+ */
+#define I2C_MS_MODE    (BIT(4))
+#define I2C_MS_MODE_M  (I2C_MS_MODE_V << I2C_MS_MODE_S)
+#define I2C_MS_MODE_V  0x00000001U
+#define I2C_MS_MODE_S  4
+/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
+ *  Configures whether the slave starts sending the data in txfifo.
+ *  0: No effect
+ *  1: Start
+ */
+#define I2C_TRANS_START    (BIT(5))
+#define I2C_TRANS_START_M  (I2C_TRANS_START_V << I2C_TRANS_START_S)
+#define I2C_TRANS_START_V  0x00000001U
+#define I2C_TRANS_START_S  5
+/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
+ *  Configures to control the sending order for data needing to be sent.
+ *  0: send data from the most significant bit
+ *  1: send data from the least significant bit
+ */
+#define I2C_TX_LSB_FIRST    (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
+#define I2C_TX_LSB_FIRST_V  0x00000001U
+#define I2C_TX_LSB_FIRST_S  6
+/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
+ *  Configures to control the storage order for received data.
+ *  0: receive data from the most significant bit
+ *  1: receive data from the least significant bit
+ */
+#define I2C_RX_LSB_FIRST    (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
+#define I2C_RX_LSB_FIRST_V  0x00000001U
+#define I2C_RX_LSB_FIRST_S  7
+/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether to gate clock signal for registers.
+ *  0: Support clock only when registers are read or written to by software
+ *  1: Force clock on for registers
+ */
+#define I2C_CLK_EN    (BIT(8))
+#define I2C_CLK_EN_M  (I2C_CLK_EN_V << I2C_CLK_EN_S)
+#define I2C_CLK_EN_V  0x00000001U
+#define I2C_CLK_EN_S  8
+/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
+ *  Configures to enable I2C bus arbitration detection.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_ARBITRATION_EN    (BIT(9))
+#define I2C_ARBITRATION_EN_M  (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
+#define I2C_ARBITRATION_EN_V  0x00000001U
+#define I2C_ARBITRATION_EN_S  9
+/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
+ *  Configures to reset the SCL_FSM.
+ *  0: No effect
+ *  1: Reset
+ */
+#define I2C_FSM_RST    (BIT(10))
+#define I2C_FSM_RST_M  (I2C_FSM_RST_V << I2C_FSM_RST_S)
+#define I2C_FSM_RST_V  0x00000001U
+#define I2C_FSM_RST_S  10
+/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
+ *  Configures this bit for synchronization.
+ *  0: No effect
+ *  1: Synchronize
+ */
+#define I2C_CONF_UPGATE    (BIT(11))
+#define I2C_CONF_UPGATE_M  (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S)
+#define I2C_CONF_UPGATE_V  0x00000001U
+#define I2C_CONF_UPGATE_S  11
+/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures to enable slave to send data automatically
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
+#define I2C_SLV_TX_AUTO_START_EN_M  (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S)
+#define I2C_SLV_TX_AUTO_START_EN_V  0x00000001U
+#define I2C_SLV_TX_AUTO_START_EN_S  12
+/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
+ *  0: Not check
+ *  1: Check
+ */
+#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
+#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S)
+#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x00000001U
+#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
+/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures to support the 7 bit general call function.
+ *  0: Not support
+ *  1: Support
+ */
+#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
+#define I2C_ADDR_BROADCASTING_EN_M  (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S)
+#define I2C_ADDR_BROADCASTING_EN_V  0x00000001U
+#define I2C_ADDR_BROADCASTING_EN_S  14
+
+/** I2C_SR_REG register
+ *  Describe I2C work status
+ */
+#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8)
+/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
+ *  Represents the received ACK value in master mode or slave mode.
+ *  0: ACK
+ *  1: NACK.
+ */
+#define I2C_RESP_REC    (BIT(0))
+#define I2C_RESP_REC_M  (I2C_RESP_REC_V << I2C_RESP_REC_S)
+#define I2C_RESP_REC_V  0x00000001U
+#define I2C_RESP_REC_S  0
+/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
+ *  Represents the transfer direction in slave mode.
+ *  1: Master reads from slave
+ *  0: Master writes to slave.
+ */
+#define I2C_SLAVE_RW    (BIT(1))
+#define I2C_SLAVE_RW_M  (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S)
+#define I2C_SLAVE_RW_V  0x00000001U
+#define I2C_SLAVE_RW_S  1
+/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
+ *  Represents whether the I2C controller loses control of SCL line.
+ *  0: No arbitration lost
+ *  1: Arbitration lost
+ */
+#define I2C_ARB_LOST    (BIT(3))
+#define I2C_ARB_LOST_M  (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
+#define I2C_ARB_LOST_V  0x00000001U
+#define I2C_ARB_LOST_S  3
+/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
+ *  Represents the I2C bus state.
+ *  1: The I2C bus is busy transferring data
+ *  0: The I2C bus is in idle state.
+ */
+#define I2C_BUS_BUSY    (BIT(4))
+#define I2C_BUS_BUSY_M  (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
+#define I2C_BUS_BUSY_V  0x00000001U
+#define I2C_BUS_BUSY_S  4
+/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0;
+ *  Represents whether the address sent by the master is equal to the address of the
+ *  slave.
+ *  Valid only when the module is configured as an I2C Slave.
+ *  0: Not equal
+ *  1: Equal
+ */
+#define I2C_SLAVE_ADDRESSED    (BIT(5))
+#define I2C_SLAVE_ADDRESSED_M  (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S)
+#define I2C_SLAVE_ADDRESSED_V  0x00000001U
+#define I2C_SLAVE_ADDRESSED_S  5
+/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0;
+ *  Represents the number of data bytes received in RAM.
+ */
+#define I2C_RXFIFO_CNT    0x0000003FU
+#define I2C_RXFIFO_CNT_M  (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S)
+#define I2C_RXFIFO_CNT_V  0x0000003FU
+#define I2C_RXFIFO_CNT_S  8
+/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3;
+ *  Represents the cause of SCL clocking stretching in slave mode.
+ *  0: Stretching SCL low when the master starts to read data.
+ *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
+ *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
+ */
+#define I2C_STRETCH_CAUSE    0x00000003U
+#define I2C_STRETCH_CAUSE_M  (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S)
+#define I2C_STRETCH_CAUSE_V  0x00000003U
+#define I2C_STRETCH_CAUSE_S  14
+/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0;
+ *  Represents the number of data bytes to be sent.
+ */
+#define I2C_TXFIFO_CNT    0x0000003FU
+#define I2C_TXFIFO_CNT_M  (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S)
+#define I2C_TXFIFO_CNT_V  0x0000003FU
+#define I2C_TXFIFO_CNT_S  18
+/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
+ *  Represents the states of the I2C module state machine.
+ *  0: Idle
+ *  1: Address shift
+ *  2: ACK address
+ *  3: Rx data
+ *  4: Tx data
+ *  5: Send ACK
+ *  6: Wait ACK
+ */
+#define I2C_SCL_MAIN_STATE_LAST    0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_M  (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S)
+#define I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
+ *  Represents the states of the state machine used to produce SCL.
+ *  0: Idle
+ *  1: Start
+ *  2: Negative edge
+ *  3: Low
+ *  4: Positive edge
+ *  5: High
+ *  6: Stop
+ */
+#define I2C_SCL_STATE_LAST    0x00000007U
+#define I2C_SCL_STATE_LAST_M  (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S)
+#define I2C_SCL_STATE_LAST_V  0x00000007U
+#define I2C_SCL_STATE_LAST_S  28
+
+/** I2C_TO_REG register
+ *  Setting time out control for receiving data
+ */
+#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xc)
+/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the timeout threshold period for SCL stucking at high or low level. The
+ *  actual period is 2\^{}(reg_time_out_value).
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_TIME_OUT_VALUE    0x0000001FU
+#define I2C_TIME_OUT_VALUE_M  (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
+#define I2C_TIME_OUT_VALUE_V  0x0000001FU
+#define I2C_TIME_OUT_VALUE_S  0
+/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures to enable time out control.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_TIME_OUT_EN    (BIT(5))
+#define I2C_TIME_OUT_EN_M  (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
+#define I2C_TIME_OUT_EN_V  0x00000001U
+#define I2C_TIME_OUT_EN_S  5
+
+/** I2C_SLAVE_ADDR_REG register
+ *  Local slave address setting
+ */
+#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10)
+/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
+ *  Configure the slave address of I2C Slave.
+ */
+#define I2C_SLAVE_ADDR    0x00007FFFU
+#define I2C_SLAVE_ADDR_M  (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S)
+#define I2C_SLAVE_ADDR_V  0x00007FFFU
+#define I2C_SLAVE_ADDR_S  0
+/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures to enable the slave 10-bit addressing mode in master mode.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_ADDR_10BIT_EN    (BIT(31))
+#define I2C_ADDR_10BIT_EN_M  (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S)
+#define I2C_ADDR_10BIT_EN_V  0x00000001U
+#define I2C_ADDR_10BIT_EN_S  31
+
+/** I2C_FIFO_ST_REG register
+ *  FIFO status register
+ */
+#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14)
+/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
+ *  Represents the offset address of the APB reading from RXFIFO.
+ */
+#define I2C_RXFIFO_RADDR    0x0000001FU
+#define I2C_RXFIFO_RADDR_M  (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S)
+#define I2C_RXFIFO_RADDR_V  0x0000001FU
+#define I2C_RXFIFO_RADDR_S  0
+/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0;
+ *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
+ */
+#define I2C_RXFIFO_WADDR    0x0000001FU
+#define I2C_RXFIFO_WADDR_M  (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S)
+#define I2C_RXFIFO_WADDR_V  0x0000001FU
+#define I2C_RXFIFO_WADDR_S  5
+/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0;
+ *  Represents the offset address of i2c module reading from TXFIFO.
+ */
+#define I2C_TXFIFO_RADDR    0x0000001FU
+#define I2C_TXFIFO_RADDR_M  (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S)
+#define I2C_TXFIFO_RADDR_V  0x0000001FU
+#define I2C_TXFIFO_RADDR_S  10
+/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0;
+ *  Represents the offset address of APB bus writing to TXFIFO.
+ */
+#define I2C_TXFIFO_WADDR    0x0000001FU
+#define I2C_TXFIFO_WADDR_M  (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S)
+#define I2C_TXFIFO_WADDR_V  0x0000001FU
+#define I2C_TXFIFO_WADDR_S  15
+/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0;
+ *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
+ *  I2C slave mode.
+ */
+#define I2C_SLAVE_RW_POINT    0x000000FFU
+#define I2C_SLAVE_RW_POINT_M  (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S)
+#define I2C_SLAVE_RW_POINT_V  0x000000FFU
+#define I2C_SLAVE_RW_POINT_S  22
+
+/** I2C_FIFO_CONF_REG register
+ *  FIFO configuration register
+ */
+#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18)
+/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
+ *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
+ *  I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0],
+ *  I2C_RXFIFO_WM_INT_RAW bit will be valid.
+ *  \tododone{For CJ, please check this description. I habe doubt about
+ *  reg_reg_fifo_prt_en.CJ: modified}
+ */
+#define I2C_RXFIFO_WM_THRHD    0x0000001FU
+#define I2C_RXFIFO_WM_THRHD_M  (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S)
+#define I2C_RXFIFO_WM_THRHD_V  0x0000001FU
+#define I2C_RXFIFO_WM_THRHD_S  0
+/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4;
+ *  Configures the water mark threshold of TXFIFO in nonfifo access mode.  When
+ *  I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0],
+ *  I2C_TXFIFO_WM_INT_RAW bit will be valid.
+ */
+#define I2C_TXFIFO_WM_THRHD    0x0000001FU
+#define I2C_TXFIFO_WM_THRHD_M  (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S)
+#define I2C_TXFIFO_WM_THRHD_V  0x0000001FU
+#define I2C_TXFIFO_WM_THRHD_S  5
+/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures to enable APB nonfifo access.
+ */
+#define I2C_NONFIFO_EN    (BIT(10))
+#define I2C_NONFIFO_EN_M  (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S)
+#define I2C_NONFIFO_EN_V  0x00000001U
+#define I2C_NONFIFO_EN_S  10
+/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures the slave to enable dual address mode. When this mode is enabled, the
+ *  byte received after the I2C address byte represents the offset address in the I2C
+ *  Slave RAM.
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_M  (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S)
+#define I2C_FIFO_ADDR_CFG_EN_V  0x00000001U
+#define I2C_FIFO_ADDR_CFG_EN_S  11
+/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
+ *  Configures to reset RXFIFO.
+ *  0: No effect
+ *  1: Reset
+ */
+#define I2C_RX_FIFO_RST    (BIT(12))
+#define I2C_RX_FIFO_RST_M  (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S)
+#define I2C_RX_FIFO_RST_V  0x00000001U
+#define I2C_RX_FIFO_RST_S  12
+/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
+ *  Configures to reset TXFIFO.
+ *  0: No effect
+ *  1: Reset
+ */
+#define I2C_TX_FIFO_RST    (BIT(13))
+#define I2C_TX_FIFO_RST_M  (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S)
+#define I2C_TX_FIFO_RST_V  0x00000001U
+#define I2C_TX_FIFO_RST_S  13
+/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
+ *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
+ *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_FIFO_PRT_EN    (BIT(14))
+#define I2C_FIFO_PRT_EN_M  (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
+#define I2C_FIFO_PRT_EN_V  0x00000001U
+#define I2C_FIFO_PRT_EN_S  14
+
+/** I2C_DATA_REG register
+ *  Rx FIFO read data
+ */
+#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1c)
+/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
+ *  Represents the value of RXFIFO read data.
+ */
+#define I2C_FIFO_RDATA    0x000000FFU
+#define I2C_FIFO_RDATA_M  (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S)
+#define I2C_FIFO_RDATA_V  0x000000FFU
+#define I2C_FIFO_RDATA_S  0
+
+/** I2C_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20)
+/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_M  (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S)
+#define I2C_RXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_RAW_S  0
+/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
+ *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_M  (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S)
+#define I2C_TXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_RAW_S  1
+/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S)
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_RAW    (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S)
+#define I2C_END_DETECT_INT_RAW_V  0x00000001U
+#define I2C_END_DETECT_INT_RAW_S  3
+/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S)
+#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
+/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S)
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S)
+#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
+/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
+ *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S)
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
+ *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_RAW    (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S)
+#define I2C_TIME_OUT_INT_RAW_V  0x00000001U
+#define I2C_TIME_OUT_INT_RAW_S  8
+/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
+ *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_RAW    (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S)
+#define I2C_TRANS_START_INT_RAW_V  0x00000001U
+#define I2C_TRANS_START_INT_RAW_S  9
+/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_RAW    (BIT(10))
+#define I2C_NACK_INT_RAW_M  (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S)
+#define I2C_NACK_INT_RAW_V  0x00000001U
+#define I2C_NACK_INT_RAW_S  10
+/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
+ *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_M  (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S)
+#define I2C_TXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_RAW_S  11
+/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_M  (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S)
+#define I2C_RXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_RAW_S  12
+/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
+ *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S)
+#define I2C_SCL_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
+ *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S)
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
+ *  The raw interrupt status of I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_RAW    (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S)
+#define I2C_DET_START_INT_RAW_V  0x00000001U
+#define I2C_DET_START_INT_RAW_S  15
+/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_M  (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S)
+#define I2C_SLAVE_STRETCH_INT_RAW_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_RAW_S  16
+/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0;
+ *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
+#define I2C_GENERAL_CALL_INT_RAW_M  (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S)
+#define I2C_GENERAL_CALL_INT_RAW_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_RAW_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M  (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S  18
+
+/** I2C_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24)
+/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_M  (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S)
+#define I2C_RXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_CLR_S  0
+/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_M  (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S)
+#define I2C_TXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_CLR_S  1
+/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S)
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_CLR    (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S)
+#define I2C_END_DETECT_INT_CLR_V  0x00000001U
+#define I2C_END_DETECT_INT_CLR_S  3
+/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S)
+#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
+/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S)
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S)
+#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
+/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S)
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_CLR    (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S)
+#define I2C_TIME_OUT_INT_CLR_V  0x00000001U
+#define I2C_TIME_OUT_INT_CLR_S  8
+/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_CLR    (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S)
+#define I2C_TRANS_START_INT_CLR_V  0x00000001U
+#define I2C_TRANS_START_INT_CLR_S  9
+/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_CLR    (BIT(10))
+#define I2C_NACK_INT_CLR_M  (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S)
+#define I2C_NACK_INT_CLR_V  0x00000001U
+#define I2C_NACK_INT_CLR_S  10
+/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_M  (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S)
+#define I2C_TXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_CLR_S  11
+/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_M  (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S)
+#define I2C_RXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_CLR_S  12
+/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S)
+#define I2C_SCL_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S)
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Write 1 to clear I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_CLR    (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S)
+#define I2C_DET_START_INT_CLR_V  0x00000001U
+#define I2C_DET_START_INT_CLR_S  15
+/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_M  (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S)
+#define I2C_SLAVE_STRETCH_INT_CLR_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_CLR_S  16
+/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
+#define I2C_GENERAL_CALL_INT_CLR_M  (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S)
+#define I2C_GENERAL_CALL_INT_CLR_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_CLR_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M  (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S  18
+
+/** I2C_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28)
+/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_M  (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S)
+#define I2C_RXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ENA_S  0
+/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_M  (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S)
+#define I2C_TXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ENA_S  1
+/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S)
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ENA    (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S)
+#define I2C_END_DETECT_INT_ENA_V  0x00000001U
+#define I2C_END_DETECT_INT_ENA_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S)
+#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
+/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S)
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S)
+#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
+/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S)
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ENA    (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S)
+#define I2C_TIME_OUT_INT_ENA_V  0x00000001U
+#define I2C_TIME_OUT_INT_ENA_S  8
+/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ENA    (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S)
+#define I2C_TRANS_START_INT_ENA_V  0x00000001U
+#define I2C_TRANS_START_INT_ENA_S  9
+/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ENA    (BIT(10))
+#define I2C_NACK_INT_ENA_M  (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S)
+#define I2C_NACK_INT_ENA_V  0x00000001U
+#define I2C_NACK_INT_ENA_S  10
+/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_M  (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S)
+#define I2C_TXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ENA_S  11
+/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_M  (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S)
+#define I2C_RXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ENA_S  12
+/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S)
+#define I2C_SCL_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  Write 1 to enable I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ENA    (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S)
+#define I2C_DET_START_INT_ENA_V  0x00000001U
+#define I2C_DET_START_INT_ENA_S  15
+/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_M  (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S)
+#define I2C_SLAVE_STRETCH_INT_ENA_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_ENA_S  16
+/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ENA_M  (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S)
+#define I2C_GENERAL_CALL_INT_ENA_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_ENA_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S  18
+
+/** I2C_INT_STATUS_REG register
+ *  Status of captured I2C communication events
+ */
+#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2c)
+/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_M  (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S)
+#define I2C_RXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ST_S  0
+/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_M  (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S)
+#define I2C_TXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ST_S  1
+/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S)
+#define I2C_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ST    (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S)
+#define I2C_END_DETECT_INT_ST_V  0x00000001U
+#define I2C_END_DETECT_INT_ST_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_M  (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S)
+#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
+/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S)
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_M  (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S)
+#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
+/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S)
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ST    (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S)
+#define I2C_TIME_OUT_INT_ST_V  0x00000001U
+#define I2C_TIME_OUT_INT_ST_S  8
+/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ST    (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S)
+#define I2C_TRANS_START_INT_ST_V  0x00000001U
+#define I2C_TRANS_START_INT_ST_S  9
+/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ST    (BIT(10))
+#define I2C_NACK_INT_ST_M  (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S)
+#define I2C_NACK_INT_ST_V  0x00000001U
+#define I2C_NACK_INT_ST_S  10
+/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_M  (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S)
+#define I2C_TXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ST_S  11
+/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_M  (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S)
+#define I2C_RXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ST_S  12
+/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S)
+#define I2C_SCL_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ST_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked interrupt status status of I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ST    (BIT(15))
+#define I2C_DET_START_INT_ST_M  (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S)
+#define I2C_DET_START_INT_ST_V  0x00000001U
+#define I2C_DET_START_INT_ST_S  15
+/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_M  (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S)
+#define I2C_SLAVE_STRETCH_INT_ST_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_ST_S  16
+/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ST_M  (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S)
+#define I2C_GENERAL_CALL_INT_ST_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_ST_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S  18
+
+/** I2C_SDA_HOLD_REG register
+ *  Configures the hold time after a negative SCL edge
+ */
+#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30)
+/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the time to hold the data after the falling edge of SCL.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SDA_HOLD_TIME    0x000001FFU
+#define I2C_SDA_HOLD_TIME_M  (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
+#define I2C_SDA_HOLD_TIME_V  0x000001FFU
+#define I2C_SDA_HOLD_TIME_S  0
+
+/** I2C_SDA_SAMPLE_REG register
+ *  Configures the sample time after a positive SCL edge
+ */
+#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34)
+/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the time for sampling SDA.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SDA_SAMPLE_TIME    0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_M  (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
+#define I2C_SDA_SAMPLE_TIME_V  0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+/** I2C_SCL_HIGH_PERIOD_REG register
+ *  Configures the high level width of SCL
+ */
+#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38)
+/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  Configures for how long SCL remains high in master mode.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_HIGH_PERIOD    0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_M  (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
+#define I2C_SCL_HIGH_PERIOD_V  0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_S  0
+/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
+ *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_M  (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
+#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
+
+/** I2C_SCL_START_HOLD_REG register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40)
+/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the time between the falling edge of SDA and the falling edge of SCL for
+ *  a START condition.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_START_HOLD_TIME    0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_M  (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
+#define I2C_SCL_START_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+/** I2C_SCL_RSTART_SETUP_REG register
+ *  Configures the delay between the positive
+ *  edge of SCL and the negative edge of SDA
+ */
+#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44)
+/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the time between the positive edge of SCL and the negative edge of SDA
+ *  for a RESTART condition.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_RSTART_SETUP_TIME    0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_M  (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+/** I2C_SCL_STOP_HOLD_REG register
+ *  Configures the delay after the SCL clock
+ *  edge for a stop condition
+ */
+#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48)
+/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the delay after the STOP condition.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_STOP_HOLD_TIME    0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_M  (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
+#define I2C_SCL_STOP_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+/** I2C_SCL_STOP_SETUP_REG register
+ *  Configures the delay between the SDA and
+ *  SCL positive edge for a stop condition
+ */
+#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4c)
+/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the positive edgeof SCL and the
+ *  positive edge of SDA, in I2C module clock cycles.
+ */
+#define I2C_SCL_STOP_SETUP_TIME    0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_M  (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S)
+#define I2C_SCL_STOP_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+/** I2C_FILTER_CFG_REG register
+ *  SCL and SDA filter configuration register
+ */
+#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50)
+/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
+ *  input has smaller width than this register value, the I2C controller will ignore
+ *  that pulse.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_FILTER_THRES    0x0000000FU
+#define I2C_SCL_FILTER_THRES_M  (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
+#define I2C_SCL_FILTER_THRES_V  0x0000000FU
+#define I2C_SCL_FILTER_THRES_S  0
+/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
+ *  input has smaller width than this register value, the I2C controller will ignore
+ *  that pulse.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SDA_FILTER_THRES    0x0000000FU
+#define I2C_SDA_FILTER_THRES_M  (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
+#define I2C_SDA_FILTER_THRES_V  0x0000000FU
+#define I2C_SDA_FILTER_THRES_S  4
+/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
+ *  Configures to enable the filter function for SCL.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_SCL_FILTER_EN    (BIT(8))
+#define I2C_SCL_FILTER_EN_M  (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
+#define I2C_SCL_FILTER_EN_V  0x00000001U
+#define I2C_SCL_FILTER_EN_S  8
+/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
+ *  Configures to enable the filter function for SDA.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_SDA_FILTER_EN    (BIT(9))
+#define I2C_SDA_FILTER_EN_M  (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
+#define I2C_SDA_FILTER_EN_V  0x00000001U
+#define I2C_SDA_FILTER_EN_S  9
+
+/** I2C_COMD0_REG register
+ *  I2C command register 0
+ */
+#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58)
+/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 0.
+ *  It consists of three parts:
+ *  op_code is the command
+ *  1: WRITE
+ *  2: STOP
+ *  3: READ
+ *  4: END
+ *  6: RSTART
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure  for more information.
+ *  \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}"
+ */
+#define I2C_COMMAND0    0x00003FFFU
+#define I2C_COMMAND0_M  (I2C_COMMAND0_V << I2C_COMMAND0_S)
+#define I2C_COMMAND0_V  0x00003FFFU
+#define I2C_COMMAND0_S  0
+/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 0 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND0_DONE    (BIT(31))
+#define I2C_COMMAND0_DONE_M  (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
+#define I2C_COMMAND0_DONE_V  0x00000001U
+#define I2C_COMMAND0_DONE_S  31
+
+/** I2C_COMD1_REG register
+ *  I2C command register 1
+ */
+#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5c)
+/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 1.
+ *  See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND1    0x00003FFFU
+#define I2C_COMMAND1_M  (I2C_COMMAND1_V << I2C_COMMAND1_S)
+#define I2C_COMMAND1_V  0x00003FFFU
+#define I2C_COMMAND1_S  0
+/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 1 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND1_DONE    (BIT(31))
+#define I2C_COMMAND1_DONE_M  (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
+#define I2C_COMMAND1_DONE_V  0x00000001U
+#define I2C_COMMAND1_DONE_S  31
+
+/** I2C_COMD2_REG register
+ *  I2C command register 2
+ */
+#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60)
+/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 2. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND2    0x00003FFFU
+#define I2C_COMMAND2_M  (I2C_COMMAND2_V << I2C_COMMAND2_S)
+#define I2C_COMMAND2_V  0x00003FFFU
+#define I2C_COMMAND2_S  0
+/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 2 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND2_DONE    (BIT(31))
+#define I2C_COMMAND2_DONE_M  (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
+#define I2C_COMMAND2_DONE_V  0x00000001U
+#define I2C_COMMAND2_DONE_S  31
+
+/** I2C_COMD3_REG register
+ *  I2C command register 3
+ */
+#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64)
+/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 3. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND3    0x00003FFFU
+#define I2C_COMMAND3_M  (I2C_COMMAND3_V << I2C_COMMAND3_S)
+#define I2C_COMMAND3_V  0x00003FFFU
+#define I2C_COMMAND3_S  0
+/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 3 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND3_DONE    (BIT(31))
+#define I2C_COMMAND3_DONE_M  (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
+#define I2C_COMMAND3_DONE_V  0x00000001U
+#define I2C_COMMAND3_DONE_S  31
+
+/** I2C_COMD4_REG register
+ *  I2C command register 4
+ */
+#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68)
+/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 4. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND4    0x00003FFFU
+#define I2C_COMMAND4_M  (I2C_COMMAND4_V << I2C_COMMAND4_S)
+#define I2C_COMMAND4_V  0x00003FFFU
+#define I2C_COMMAND4_S  0
+/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 4 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND4_DONE    (BIT(31))
+#define I2C_COMMAND4_DONE_M  (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
+#define I2C_COMMAND4_DONE_V  0x00000001U
+#define I2C_COMMAND4_DONE_S  31
+
+/** I2C_COMD5_REG register
+ *  I2C command register 5
+ */
+#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6c)
+/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 5. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND5    0x00003FFFU
+#define I2C_COMMAND5_M  (I2C_COMMAND5_V << I2C_COMMAND5_S)
+#define I2C_COMMAND5_V  0x00003FFFU
+#define I2C_COMMAND5_S  0
+/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 5 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND5_DONE    (BIT(31))
+#define I2C_COMMAND5_DONE_M  (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
+#define I2C_COMMAND5_DONE_V  0x00000001U
+#define I2C_COMMAND5_DONE_S  31
+
+/** I2C_COMD6_REG register
+ *  I2C command register 6
+ */
+#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70)
+/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 6. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND6    0x00003FFFU
+#define I2C_COMMAND6_M  (I2C_COMMAND6_V << I2C_COMMAND6_S)
+#define I2C_COMMAND6_V  0x00003FFFU
+#define I2C_COMMAND6_S  0
+/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 6 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND6_DONE    (BIT(31))
+#define I2C_COMMAND6_DONE_M  (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
+#define I2C_COMMAND6_DONE_V  0x00000001U
+#define I2C_COMMAND6_DONE_S  31
+
+/** I2C_COMD7_REG register
+ *  I2C command register 7
+ */
+#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74)
+/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 7. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND7    0x00003FFFU
+#define I2C_COMMAND7_M  (I2C_COMMAND7_V << I2C_COMMAND7_S)
+#define I2C_COMMAND7_V  0x00003FFFU
+#define I2C_COMMAND7_S  0
+/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 7 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND7_DONE    (BIT(31))
+#define I2C_COMMAND7_DONE_M  (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
+#define I2C_COMMAND7_DONE_V  0x00000001U
+#define I2C_COMMAND7_DONE_S  31
+
+/** I2C_SCL_ST_TIME_OUT_REG register
+ *  SCL status time out register
+ */
+#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78)
+/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
+ *  more than 23.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_ST_TO_I2C_M  (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
+#define I2C_SCL_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_ST_TO_I2C_S  0
+
+/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
+ *  SCL main status time out register
+ */
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7c)
+/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be
+ *  no more than 23.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_MAIN_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_M  (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
+#define I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_S  0
+
+/** I2C_SCL_SP_CONF_REG register
+ *  Power configuration register
+ */
+#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80)
+/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
+ *  equals to I2C_SCL_RST_SLV_NUM[4:0].
+ */
+#define I2C_SCL_RST_SLV_EN    (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S)
+#define I2C_SCL_RST_SLV_EN_V  0x00000001U
+#define I2C_SCL_RST_SLV_EN_S  0
+/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
+ *  Configure the pulses of SCL generated in I2C master mode.
+ *  Valid when I2C_SCL_RST_SLV_EN is 1.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_RST_SLV_NUM    0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_M  (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
+#define I2C_SCL_RST_SLV_NUM_V  0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_S  1
+/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures to power down the I2C output SCL line.
+ *  0: Not power down.
+ *  1: Not work and power down.
+ *  Valid only when I2C_SCL_FORCE_OUT is 1.
+ */
+#define I2C_SCL_PD_EN    (BIT(6))
+#define I2C_SCL_PD_EN_M  (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S)
+#define I2C_SCL_PD_EN_V  0x00000001U
+#define I2C_SCL_PD_EN_S  6
+/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures to power down the I2C output SDA line.
+ *  0: Not power down.
+ *  1: Not work and power down.
+ *  Valid only when I2C_SDA_FORCE_OUT is 1.
+ */
+#define I2C_SDA_PD_EN    (BIT(7))
+#define I2C_SDA_PD_EN_M  (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S)
+#define I2C_SDA_PD_EN_V  0x00000001U
+#define I2C_SDA_PD_EN_S  7
+
+/** I2C_SCL_STRETCH_CONF_REG register
+ *  Set SCL stretch of I2C slave
+ */
+#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84)
+/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
+ *  Configures the time period to release the SCL line from stretching to avoid timing
+ *  violation. Usually it should be larger than the SDA setup time.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_STRETCH_PROTECT_NUM    0x000003FFU
+#define I2C_STRETCH_PROTECT_NUM_M  (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S)
+#define I2C_STRETCH_PROTECT_NUM_V  0x000003FFU
+#define I2C_STRETCH_PROTECT_NUM_S  0
+/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures to enable slave SCL stretch function. The SCL output line will be
+ *  stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The
+ *  stretch cause can be seen in I2C_STRETCH_CAUSE.
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_M  (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S)
+#define I2C_SLAVE_SCL_STRETCH_EN_V  0x00000001U
+#define I2C_SLAVE_SCL_STRETCH_EN_S  10
+/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures to clear the I2C slave SCL stretch function.
+ *  0: No effect
+ *  1: Clear
+ */
+#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_M  (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S)
+#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x00000001U
+#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
+/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures to enable the function for slave to control ACK level.
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S)
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x00000001U
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
+/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0;
+ *  Set the ACK level when slave controlling ACK level function enables.
+ *  0: Low level
+ *  1: High level
+ */
+#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
+#define I2C_SLAVE_BYTE_ACK_LVL_M  (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S)
+#define I2C_SLAVE_BYTE_ACK_LVL_V  0x00000001U
+#define I2C_SLAVE_BYTE_ACK_LVL_S  13
+
+/** I2C_DATE_REG register
+ *  Version register
+ */
+#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xf8)
+/** I2C_DATE : R/W; bitpos: [31:0]; default: 37765248;
+ *  Version control register.
+ */
+#define I2C_DATE    0xFFFFFFFFU
+#define I2C_DATE_M  (I2C_DATE_V << I2C_DATE_S)
+#define I2C_DATE_V  0xFFFFFFFFU
+#define I2C_DATE_S  0
+
+/** I2C_TXFIFO_START_ADDR_REG register
+ *  I2C TXFIFO base address register
+ */
+#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100)
+/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Represents the I2C txfifo first address.
+ */
+#define I2C_TXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_M  (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S)
+#define I2C_TXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_S  0
+
+/** I2C_RXFIFO_START_ADDR_REG register
+ *  I2C RXFIFO base address register
+ */
+#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180)
+/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Represents the I2C rxfifo first address.
+ */
+#define I2C_RXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_M  (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S)
+#define I2C_RXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2c_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i2c_struct.h
new file mode 100644
index 0000000000..b8c06265a1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i2c_struct.h
@@ -0,0 +1,1095 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Timing registers */
+/** Type of scl_low_period register
+ *  Configures the low level width of the SCL Clock.
+ */
+typedef union {
+    struct {
+        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the low level width of the SCL Clock.
+         *  Measurement unit: i2c_sclk.
+         */
+        uint32_t scl_low_period:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_low_period_reg_t;
+
+/** Type of sda_hold register
+ *  Configures the hold time after a negative SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the time to hold the data after the falling edge of SCL.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_hold_reg_t;
+
+/** Type of sda_sample register
+ *  Configures the sample time after a positive SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the sample time after a positive SCL edge.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_sample_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_sample_reg_t;
+
+/** Type of scl_high_period register
+ *  Configures the high level width of SCL
+ */
+typedef union {
+    struct {
+        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures for how long SCL remains high in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_high_period:9;
+        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
+         *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_wait_high_period:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_scl_high_period_reg_t;
+
+/** Type of scl_start_hold register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+typedef union {
+    struct {
+        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the falling edge of SDA and the falling edge of SCL for
+         *  a START condition.
+         *  Measurement unit: i2c_sclk.
+         */
+        uint32_t scl_start_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_start_hold_reg_t;
+
+/** Type of scl_rstart_setup register
+ *  Configures the delay between the positive edge of SCL and the negative edge of SDA
+ */
+typedef union {
+    struct {
+        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the positive edge of SCL and the negative edge of SDA
+         *  for a RESTART condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_rstart_setup_reg_t;
+
+/** Type of scl_stop_hold register
+ *  Configures the delay after the SCL clock edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the delay after the STOP condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_hold_reg_t;
+
+/** Type of scl_stop_setup register
+ *  Configures the delay between the SDA and SCL rising edge for a stop condition.
+ *  Measurement unit: i2c_sclk
+ */
+typedef union {
+    struct {
+        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the rising edge of SCL and the rising edge of SDA.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_setup_reg_t;
+
+/** Type of scl_st_time_out register
+ *  SCL status time out register
+ */
+typedef union {
+    struct {
+        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
+         *  more than 23.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_st_time_out_reg_t;
+
+/** Type of scl_main_st_time_out register
+ *  SCL main status time out register
+ */
+typedef union {
+    struct {
+        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
+         *  no more than 23.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_main_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_main_st_time_out_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of ctr register
+ *  Transmission setting
+ */
+typedef union {
+    struct {
+        /** sda_force_out : R/W; bitpos: [0]; default: 0;
+         *  Configures the SDA output mode
+         *  1: Direct output,
+         *
+         *  0: Open drain output.
+         */
+        uint32_t sda_force_out:1;
+        /** scl_force_out : R/W; bitpos: [1]; default: 0;
+         *  Configures the SCL output mode
+         *  1: Direct output,
+         *
+         *  0: Open drain output.
+         */
+        uint32_t scl_force_out:1;
+        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
+         *  Configures the sample mode for SDA.
+         *  1: Sample SDA data on the SCL low level.
+         *
+         *  0: Sample SDA data on the SCL high level.
+         */
+        uint32_t sample_scl_level:1;
+        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
+         *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
+         *  reached the threshold.
+         */
+        uint32_t rx_full_ack_level:1;
+        /** ms_mode : R/W; bitpos: [4]; default: 0;
+         *  Configures the module as an I2C Master or Slave.
+         *  0: Slave
+         *
+         *  1: Master
+         */
+        uint32_t ms_mode:1;
+        /** trans_start : WT; bitpos: [5]; default: 0;
+         *  Configures to start sending the data in txfifo for slave.
+         *  0: No effect
+         *
+         *  1: Start
+         */
+        uint32_t trans_start:1;
+        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
+         *  Configures to control the sending order for data needing to be sent.
+         *  1: send data from the least significant bit,
+         *
+         *  0: send data from the most significant bit.
+         */
+        uint32_t tx_lsb_first:1;
+        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
+         *  Configures to control the storage order for received data.
+         *  1: receive data from the least significant bit
+         *
+         *  0: receive data from the most significant bit.
+         */
+        uint32_t rx_lsb_first:1;
+        /** clk_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to gate clock signal for registers.
+         *
+         *  0: Force clock on for registers
+         *
+         *  1: Support clock only when registers are read or written to by software.
+         */
+        uint32_t clk_en:1;
+        /** arbitration_en : R/W; bitpos: [9]; default: 1;
+         *  Configures to enable I2C bus arbitration detection.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t arbitration_en:1;
+        /** fsm_rst : WT; bitpos: [10]; default: 0;
+         *  Configures to reset the SCL_FSM.
+         *  0: No effect
+         *
+         *  1: Reset
+         */
+        uint32_t fsm_rst:1;
+        /** conf_upgate : WT; bitpos: [11]; default: 0;
+         *  Configures this bit for synchronization
+         *  0: No effect
+         *
+         *  1: Synchronize
+         */
+        uint32_t conf_upgate:1;
+        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
+         *  Configures to enable slave to send data automatically
+         *  0: Disable
+         *
+         *  1: Enable
+         */
+        uint32_t slv_tx_auto_start_en:1;
+        /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
+         *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
+         *  0: Not check
+         *
+         *  1: Check
+         */
+        uint32_t addr_10bit_rw_check_en:1;
+        /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
+         *  Configures to support the 7bit general call function.
+         *  0: Not support
+         *
+         *  1: Support
+         */
+        uint32_t addr_broadcasting_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_ctr_reg_t;
+
+/** Type of to register
+ *  Setting time out control for receiving data.
+ */
+typedef union {
+    struct {
+        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the timeout threshold period for SCL stucking at high or low level. The
+         *  actual period is 2^(reg_time_out_value).
+         *  Measurement unit: i2c_sclk.
+         */
+        uint32_t time_out_value:5;
+        /** time_out_en : R/W; bitpos: [5]; default: 0;
+         *  Configures to enable time out control.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t time_out_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i2c_to_reg_t;
+
+/** Type of slave_addr register
+ *  Local slave address setting
+ */
+typedef union {
+    struct {
+        /** slave_addr : R/W; bitpos: [14:0]; default: 0;
+         *  Configure the slave address of I2C Slave.
+         */
+        uint32_t slave_addr:15;
+        uint32_t reserved_15:16;
+        /** addr_10bit_en : R/W; bitpos: [31]; default: 0;
+         *  Configures to enable the slave 10-bit addressing mode in master mode.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t addr_10bit_en:1;
+    };
+    uint32_t val;
+} i2c_slave_addr_reg_t;
+
+/** Type of fifo_conf register
+ *  FIFO configuration register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
+         *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
+         *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t rxfifo_wm_thrhd:5;
+        /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
+         *  Configures the water mark threshold of TXFIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
+         *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t txfifo_wm_thrhd:5;
+        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
+         *  Configures to enable APB nonfifo access.
+         */
+        uint32_t nonfifo_en:1;
+        /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
+         *  Configures to enable double addressing mode. When this mode is enabled, the byte
+         *  received after the I2C address byte represents the offset address in the I2C Slave
+         *  RAM.
+         *  0: Disable
+         *
+         *  1: Enable
+         */
+        uint32_t fifo_addr_cfg_en:1;
+        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
+         *  Configures to reset RXFIFO.
+         *  0: No effect
+         *
+         *  1: Reset
+         */
+        uint32_t rx_fifo_rst:1;
+        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
+         *  Configures to reset TXFIFO.
+         *  0: No effect
+         *
+         *  1: Reset
+         */
+        uint32_t tx_fifo_rst:1;
+        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
+         *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
+         *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t fifo_prt_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_fifo_conf_reg_t;
+
+/** Type of filter_cfg register
+ *  SCL and SDA filter configuration register
+ */
+typedef union {
+    struct {
+        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_filter_thres:4;
+        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_filter_thres:4;
+        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
+         *  Configures to enable the filter function for SCL.
+         */
+        uint32_t scl_filter_en:1;
+        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
+         *  Configures to enable the filter function for SDA.
+         */
+        uint32_t sda_filter_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} i2c_filter_cfg_reg_t;
+
+/** Type of scl_sp_conf register
+ *  Power configuration register
+ */
+typedef union {
+    struct {
+        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
+         *  equals to reg_scl_rst_slv_num[4:0].
+         */
+        uint32_t scl_rst_slv_en:1;
+        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
+         *  Configure the pulses of SCL generated in I2C master mode.
+         *  Valid when reg_scl_rst_slv_en is 1.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_rst_slv_num:5;
+        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
+         *  Configures to power down the I2C output SCL line.
+         *  0: Not power down.
+         *
+         *  1: Power down.
+         *  Valid only when reg_scl_force_out is 1.
+         */
+        uint32_t scl_pd_en:1;
+        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
+         *  Configures to power down the I2C output SDA line.
+         *  0: Not power down.
+         *
+         *  1: Power down.
+         *  Valid only when reg_sda_force_out is 1.
+         */
+        uint32_t sda_pd_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_scl_sp_conf_reg_t;
+
+/** Type of scl_stretch_conf register
+ *  Set SCL stretch of I2C slave
+ */
+typedef union {
+    struct {
+        /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
+         *  Configures the time period to release the SCL line from stretching to avoid timing
+         *  violation. Usually it should be larger than the SDA setup time.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t stretch_protect_num:10;
+        /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
+         *  Configures to enable slave SCL stretch function.
+         *  0: Disable
+         *
+         *  1: Enable
+         *  The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and
+         *  stretch event happens. The stretch cause can be seen in reg_stretch_cause.
+         */
+        uint32_t slave_scl_stretch_en:1;
+        /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
+         *  Configures to clear the I2C slave SCL stretch function.
+         *  0: No effect
+         *
+         *  1: Clear
+         */
+        uint32_t slave_scl_stretch_clr:1;
+        /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
+         *  Configures to enable the function for slave to control ACK level.
+         *  0: Disable
+         *
+         *  1: Enable
+         */
+        uint32_t slave_byte_ack_ctl_en:1;
+        /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
+         *  Set the ACK level when slave controlling ACK level function enables.
+         *  0: Low level
+         *
+         *  1: High level
+         */
+        uint32_t slave_byte_ack_lvl:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i2c_scl_stretch_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of sr register
+ *  Describe I2C work status.
+ */
+typedef union {
+    struct {
+        /** resp_rec : RO; bitpos: [0]; default: 0;
+         *  Represents the received ACK value in master mode or slave mode.
+         *  0: ACK,
+         *
+         *  1: NACK.
+         */
+        uint32_t resp_rec:1;
+        /** slave_rw : RO; bitpos: [1]; default: 0;
+         *  Represents the transfer direction in slave mode,.
+         *  1: Master reads from slave,
+         *
+         *  0: Master writes to slave.
+         */
+        uint32_t slave_rw:1;
+        uint32_t reserved_2:1;
+        /** arb_lost : RO; bitpos: [3]; default: 0;
+         *  Represents whether the I2C controller loses control of SCL line.
+         *  0: No arbitration lost
+         *
+         *  1: Arbitration lost
+         */
+        uint32_t arb_lost:1;
+        /** bus_busy : RO; bitpos: [4]; default: 0;
+         *  Represents the I2C bus state.
+         *  1: The I2C bus is busy transferring data,
+         *
+         *  0: The I2C bus is in idle state.
+         */
+        uint32_t bus_busy:1;
+        /** slave_addressed : RO; bitpos: [5]; default: 0;
+         *  Represents whether the address sent by the master is equal to the address of the
+         *  slave.
+         *  Valid only when the module is configured as an I2C Slave.
+         *  0: Not equal
+         *
+         *  1: Equal
+         */
+        uint32_t slave_addressed:1;
+        uint32_t reserved_6:2;
+        /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
+         *  Represents the number of data bytes to be sent.
+         */
+        uint32_t rxfifo_cnt:6;
+        /** stretch_cause : RO; bitpos: [15:14]; default: 3;
+         *  Represents the cause of SCL clocking stretching in slave mode.
+         *  0: Stretching SCL low when the master starts to read data.
+         *
+         *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
+         *
+         *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
+         */
+        uint32_t stretch_cause:2;
+        uint32_t reserved_16:2;
+        /** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
+         *  Represents the number of data bytes received in RAM.
+         */
+        uint32_t txfifo_cnt:6;
+        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
+         *  Represents the states of the I2C module state machine.
+         *  0: Idle,
+         *
+         *  1: Address shift,
+         *
+         *  2: ACK address,
+         *
+         *  3: Rx data,
+         *
+         *  4: Tx data,
+         *
+         *  5: Send ACK,
+         *
+         *  6: Wait ACK
+         */
+        uint32_t scl_main_state_last:3;
+        uint32_t reserved_27:1;
+        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
+         *  Represents the states of the state machine used to produce SCL.
+         *  0: Idle,
+         *
+         *  1: Start,
+         *
+         *  2: Negative edge,
+         *
+         *  3: Low,
+         *
+         *  4: Positive edge,
+         *
+         *  5: High,
+         *
+         *  6: Stop
+         */
+        uint32_t scl_state_last:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2c_sr_reg_t;
+
+/** Type of fifo_st register
+ *  FIFO status register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
+         *  Represents the offset address of the APB reading from RXFIFO
+         */
+        uint32_t rxfifo_raddr:5;
+        /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
+         *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
+         */
+        uint32_t rxfifo_waddr:5;
+        /** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
+         *  Represents the offset address of i2c module reading from TXFIFO.
+         */
+        uint32_t txfifo_raddr:5;
+        /** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
+         *  Represents the offset address of APB bus writing to TXFIFO.
+         */
+        uint32_t txfifo_waddr:5;
+        uint32_t reserved_20:2;
+        /** slave_rw_point : RO; bitpos: [29:22]; default: 0;
+         *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
+         *  I2C slave mode.
+         */
+        uint32_t slave_rw_point:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2c_fifo_st_reg_t;
+
+/** Type of data register
+ *  Rx FIFO read data.
+ */
+typedef union {
+    struct {
+        /** fifo_rdata : HRO; bitpos: [7:0]; default: 0;
+         *  Represents the value of RXFIFO read data.
+         */
+        uint32_t fifo_rdata:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_data_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_raw:1;
+        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
+         *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_raw:1;
+        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_raw:1;
+        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_raw:1;
+        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_raw:1;
+        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_raw:1;
+        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_raw:1;
+        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_raw:1;
+        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_raw:1;
+        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_raw:1;
+        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_raw:1;
+        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_raw:1;
+        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_raw:1;
+        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  The raw interrupt status of I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_raw:1;
+        /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_raw:1;
+        /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
+         *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_raw:1;
+        /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_raw:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_clr:1;
+        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_clr:1;
+        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_clr:1;
+        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_clr:1;
+        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_clr:1;
+        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_clr:1;
+        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_clr:1;
+        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_clr:1;
+        /** nack_int_clr : WT; bitpos: [10]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_clr:1;
+        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_clr:1;
+        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_clr:1;
+        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
+         *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_clr:1;
+        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
+         *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_clr:1;
+        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  Write 1 to clear I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_clr:1;
+        /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_clr:1;
+        /** general_call_int_clr : WT; bitpos: [17]; default: 0;
+         *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_clr:1;
+        /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_clr:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_ena:1;
+        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_ena:1;
+        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_ena:1;
+        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_ena:1;
+        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_ena:1;
+        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_ena:1;
+        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_ena:1;
+        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_ena:1;
+        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_ena:1;
+        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_ena:1;
+        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_ena:1;
+        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Write 1 to enable I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_ena:1;
+        /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_ena:1;
+        /** general_call_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_ena:1;
+        /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_ena:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_ena_reg_t;
+
+/** Type of int_status register
+ *  Status of captured I2C communication events
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_st:1;
+        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_st:1;
+        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_st:1;
+        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_st:1;
+        /** time_out_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_st:1;
+        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_st:1;
+        /** nack_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_st:1;
+        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_st:1;
+        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_st:1;
+        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_st:1;
+        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_st:1;
+        /** det_start_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status status of I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_st:1;
+        /** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_st:1;
+        /** general_call_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_st:1;
+        /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_st:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_status_reg_t;
+
+
+/** Group: Command registers */
+/** Type of comd0 register
+ *  I2C command register 0~7
+ */
+typedef union {
+    struct {
+        /** command : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command. It consists of three parts:
+         *  op_code is the command,
+         *  0: RSTART,
+         *  1: WRITE,
+         *  2: READ,
+         *  3: STOP,
+         *  4: END.
+         *
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more information.
+         */
+        uint32_t command:14;
+        uint32_t reserved_14:17;
+        /** command_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command is done in I2C Master mode.
+         *  0: Not done
+         *
+         *  1: Done
+         */
+        uint32_t command_done:1;
+    };
+    uint32_t val;
+} i2c_comd_reg_t;
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35656050;
+         *  Version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} i2c_date_reg_t;
+
+
+typedef struct {
+    volatile i2c_scl_low_period_reg_t scl_low_period;
+    volatile i2c_ctr_reg_t ctr;
+    volatile i2c_sr_reg_t sr;
+    volatile i2c_to_reg_t to;
+    volatile i2c_slave_addr_reg_t slave_addr;
+    volatile i2c_fifo_st_reg_t fifo_st;
+    volatile i2c_fifo_conf_reg_t fifo_conf;
+    volatile i2c_data_reg_t data;
+    volatile i2c_int_raw_reg_t int_raw;
+    volatile i2c_int_clr_reg_t int_clr;
+    volatile i2c_int_ena_reg_t int_ena;
+    volatile i2c_int_status_reg_t int_status;
+    volatile i2c_sda_hold_reg_t sda_hold;
+    volatile i2c_sda_sample_reg_t sda_sample;
+    volatile i2c_scl_high_period_reg_t scl_high_period;
+    uint32_t reserved_03c;
+    volatile i2c_scl_start_hold_reg_t scl_start_hold;
+    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
+    volatile i2c_filter_cfg_reg_t filter_cfg;
+    uint32_t reserved_054;
+    volatile i2c_comd_reg_t command[8];
+    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
+    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
+    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
+    volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
+    uint32_t reserved_088[28];
+    volatile i2c_date_reg_t date;
+    uint32_t reserved_0fc;
+    volatile uint32_t txfifo_mem[32];
+    volatile uint32_t rxfifo_mem[32];
+} i2c_dev_t;
+
+extern i2c_dev_t I2C0;
+extern i2c_dev_t I2C1;
+extern i2c_dev_t LP_I2C;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2s_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i2s_eco5_struct.h
new file mode 100644
index 0000000000..fac3b8b8fd
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i2s_eco5_struct.h
@@ -0,0 +1,1009 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        uint32_t reserved_14:1;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t rx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:8;
+        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_rx_conf1_reg_t;
+
+/** Type of rx_pdm2pcm_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:19;
+        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable PDM2PCM RX mode. 0: DIsable.
+         */
+        uint32_t rx_pdm2pcm_en:1;
+        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
+         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+         *  sampling rate is 128. 0: down sampling rate is 64.
+         */
+        uint32_t rx_pdm_sinc_dsr_16_en:1;
+        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
+         *  Configure PDM RX amplify number.
+         */
+        uint32_t rx_pdm2pcm_amplify_num:4;
+        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
+         *  I2S PDM RX bypass hp filter or not.
+         */
+        uint32_t rx_pdm_hp_bypass:1;
+        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_5:3;
+        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_0:3;
+    };
+    uint32_t val;
+} i2s_rx_pdm2pcm_conf_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan2_en:1;
+        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan3_en:1;
+        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan4_en:1;
+        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan5_en:1;
+        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan6_en:1;
+        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan7_en:1;
+        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan8_en:1;
+        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan9_en:1;
+        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan10_en:1;
+        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan11_en:1;
+        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan12_en:1;
+        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan13_en:1;
+        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan14_en:1;
+        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan15_en:1;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rxeof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_rxeof_num_reg_t;
+
+
+/** Group: TX Control and configuration registers */
+/** Type of tx_conf register
+ *  I2S TX configure register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset transmitter
+         */
+        uint32_t tx_reset:1;
+        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Tx AFIFO
+         */
+        uint32_t tx_fifo_reset:1;
+        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start transmitting data
+         */
+        uint32_t tx_start:1;
+        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave transmitter mode
+         */
+        uint32_t tx_slave_mod:1;
+        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+         */
+        uint32_t tx_stop_en:1;
+        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
+         *  1: The value of Left channel data is equal to the value of right channel data in
+         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+         */
+        uint32_t tx_chan_equal:1;
+        /** tx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter in mono mode
+         */
+        uint32_t tx_mono:1;
+        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+         *  value.
+         */
+        uint32_t tx_big_endian:1;
+        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t tx_update:1;
+        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+         *  channel data value is valid in I2S TX mono mode.
+         */
+        uint32_t tx_mono_fst_vld:1;
+        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
+         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t tx_pcm_conf:2;
+        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+         */
+        uint32_t tx_pcm_bypass:1;
+        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable transmitter in Phillips standard mode
+         */
+        uint32_t tx_msb_shift:1;
+        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
+         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+         *  generate pos/neg edge in master mode.
+         */
+        uint32_t tx_bck_no_dly:1;
+        /** tx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+         */
+        uint32_t tx_left_align:1;
+        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+         */
+        uint32_t tx_24_fill_en:1;
+        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+         */
+        uint32_t tx_ws_idle_pol:1;
+        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+         *  sent first.
+         */
+        uint32_t tx_bit_order:1;
+        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_tdm_en:1;
+        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_pdm_en:1;
+        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in transmitter mode.
+         */
+        uint32_t tx_bck_div_num:6;
+        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
+         *  I2S transmitter channel mode configuration bits.
+         */
+        uint32_t tx_chan_mod:3;
+        /** sig_loopback : R/W; bitpos: [30]; default: 0;
+         *  Enable signal loop back mode with transmitter module and receiver module sharing
+         *  the same WS and BCK signals.
+         */
+        uint32_t sig_loopback:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_tx_conf_reg_t;
+
+/** Type of tx_conf1 register
+ *  I2S TX configure register 1
+ */
+typedef union {
+    struct {
+        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t tx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t tx_bits_mod:5;
+        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Tx half sample bits -1.
+         */
+        uint32_t tx_half_sample_bits:8;
+        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Tx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t tx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_tx_conf1_reg_t;
+
+/** Type of tx_pcm2pdm_conf register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
+         *  I2S TX PDM OSR2 value
+         */
+        uint32_t tx_pdm_sinc_osr2:4;
+        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
+         *  I2S TX PDM prescale for sigmadelta
+         */
+        uint32_t tx_pdm_prescale:8;
+        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_hp_in_shift:2;
+        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_lp_in_shift:2;
+        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sinc_in_shift:2;
+        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sigmadelta_in_shift:2;
+        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
+         *  I2S TX PDM sigmadelta dither2 value
+         */
+        uint32_t tx_pdm_sigmadelta_dither2:1;
+        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
+         *  I2S TX PDM sigmadelta dither value
+         */
+        uint32_t tx_pdm_sigmadelta_dither:1;
+        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
+         *  I2S TX PDM dac mode enable
+         */
+        uint32_t tx_pdm_dac_2out_en:1;
+        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
+         *  I2S TX PDM dac 2channel enable
+         */
+        uint32_t tx_pdm_dac_mode_en:1;
+        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
+         *  I2S TX PDM Converter enable
+         */
+        uint32_t pcm2pdm_conv_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf1 register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
+         *  I2S TX PDM Fp
+         */
+        uint32_t tx_pdm_fp:10;
+        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
+         *  I2S TX PDM Fs
+         */
+        uint32_t tx_pdm_fs:10;
+        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_5:3;
+        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_0:3;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf1_reg_t;
+
+/** Type of tx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan0_en:1;
+        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan1_en:1;
+        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan2_en:1;
+        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan3_en:1;
+        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan4_en:1;
+        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan5_en:1;
+        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan6_en:1;
+        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan7_en:1;
+        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan8_en:1;
+        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan9_en:1;
+        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan10_en:1;
+        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan11_en:1;
+        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan12_en:1;
+        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan13_en:1;
+        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan14_en:1;
+        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan15_en:1;
+        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t tx_tdm_tot_chan_num:4;
+        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
+         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+         *  only the data of the enabled channels is sent, then this bit should be set. Clear
+         *  it when all the data stored in DMA TX buffer is for enabled channels.
+         */
+        uint32_t tx_tdm_skip_msk_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i2s_tx_tdm_ctrl_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:2;
+        /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd1_in_dm:2;
+        uint32_t reserved_6:2;
+        /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0;
+         *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd2_in_dm:2;
+        uint32_t reserved_10:2;
+        /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0;
+         *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd3_in_dm:2;
+        uint32_t reserved_14:2;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_rx_timing_reg_t;
+
+
+/** Group: TX clock and timing registers */
+/** Type of tx_timing register
+ *  I2S TX timing control register
+ */
+typedef union {
+    struct {
+        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd_out_dm:2;
+        uint32_t reserved_2:2;
+        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd1_out_dm:2;
+        uint32_t reserved_6:10;
+        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_tx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_sigle_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} i2s_conf_sigle_data_reg_t;
+
+
+/** Group: TX status registers */
+/** Type of state register
+ *  I2S TX status register
+ */
+typedef union {
+    struct {
+        /** tx_idle : RO; bitpos: [0]; default: 1;
+         *  1: i2s_tx is idle state. 0: i2s_tx is working.
+         */
+        uint32_t tx_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_state_reg_t;
+
+
+/** Group: ETM registers */
+/** Type of etm_conf register
+ *  I2S ETM configure register
+ */
+typedef union {
+    struct {
+        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
+         *  I2S ETM send x words event. When sending word number of
+         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_tx_send_word_num:10;
+        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
+         *  I2S ETM receive x words event. When receiving word number of
+         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_rx_receive_word_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_etm_conf_reg_t;
+
+
+/** Group: Sync counter registers */
+/** Type of fifo_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx fifo counter value.
+         */
+        uint32_t tx_fifo_cnt:31;
+        /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx fifo counter.
+         */
+        uint32_t tx_fifo_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_fifo_cnt_reg_t;
+
+/** Type of bck_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx bck counter value.
+         */
+        uint32_t tx_bck_cnt:31;
+        /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx bck counter.
+         */
+        uint32_t tx_bck_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_bck_cnt_reg_t;
+
+
+/** Group: Clock registers */
+/** Type of clk_gate register
+ *  Clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit to enable clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_clk_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36713024;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile i2s_int_raw_reg_t int_raw;
+    volatile i2s_int_st_reg_t int_st;
+    volatile i2s_int_ena_reg_t int_ena;
+    volatile i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile i2s_rx_conf_reg_t rx_conf;
+    volatile i2s_tx_conf_reg_t tx_conf;
+    volatile i2s_rx_conf1_reg_t rx_conf1;
+    volatile i2s_tx_conf1_reg_t tx_conf1;
+    uint32_t reserved_030[4];
+    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
+    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
+    volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
+    uint32_t reserved_04c;
+    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
+    volatile i2s_rx_timing_reg_t rx_timing;
+    volatile i2s_tx_timing_reg_t tx_timing;
+    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile i2s_rxeof_num_reg_t rxeof_num;
+    volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
+    volatile i2s_state_reg_t state;
+    volatile i2s_etm_conf_reg_t etm_conf;
+    volatile i2s_fifo_cnt_reg_t fifo_cnt;
+    volatile i2s_bck_cnt_reg_t bck_cnt;
+    volatile i2s_clk_gate_reg_t clk_gate;
+    volatile i2s_date_reg_t date;
+} i2s_dev_t;
+
+extern i2s_dev_t I2S0;
+extern i2s_dev_t I2S1;
+extern i2s_dev_t I2S2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2s_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/i2s_reg.h
new file mode 100644
index 0000000000..8c99c7dfb1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i2s_reg.h
@@ -0,0 +1,1270 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE + (i) * 0x1000)
+
+/** I2S_INT_RAW_REG register
+ *  I2S interrupt raw register, valid in level.
+ */
+#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
+/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_RAW    (BIT(0))
+#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
+#define I2S_RX_DONE_INT_RAW_V  0x00000001U
+#define I2S_RX_DONE_INT_RAW_S  0
+/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_RAW    (BIT(1))
+#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
+#define I2S_TX_DONE_INT_RAW_V  0x00000001U
+#define I2S_TX_DONE_INT_RAW_S  1
+/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_RAW    (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
+#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_RX_HUNG_INT_RAW_S  2
+/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_RAW    (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
+#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_TX_HUNG_INT_RAW_S  3
+
+/** I2S_INT_ST_REG register
+ *  I2S interrupt status register.
+ */
+#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
+/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ST    (BIT(0))
+#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
+#define I2S_RX_DONE_INT_ST_V  0x00000001U
+#define I2S_RX_DONE_INT_ST_S  0
+/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ST    (BIT(1))
+#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
+#define I2S_TX_DONE_INT_ST_V  0x00000001U
+#define I2S_TX_DONE_INT_ST_S  1
+/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ST    (BIT(2))
+#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
+#define I2S_RX_HUNG_INT_ST_V  0x00000001U
+#define I2S_RX_HUNG_INT_ST_S  2
+/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ST    (BIT(3))
+#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
+#define I2S_TX_HUNG_INT_ST_V  0x00000001U
+#define I2S_TX_HUNG_INT_ST_S  3
+
+/** I2S_INT_ENA_REG register
+ *  I2S interrupt enable register.
+ */
+#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
+/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ENA    (BIT(0))
+#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
+#define I2S_RX_DONE_INT_ENA_V  0x00000001U
+#define I2S_RX_DONE_INT_ENA_S  0
+/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ENA    (BIT(1))
+#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
+#define I2S_TX_DONE_INT_ENA_V  0x00000001U
+#define I2S_TX_DONE_INT_ENA_S  1
+/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ENA    (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
+#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_RX_HUNG_INT_ENA_S  2
+/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ENA    (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
+#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_TX_HUNG_INT_ENA_S  3
+
+/** I2S_INT_CLR_REG register
+ *  I2S interrupt clear register.
+ */
+#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
+/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_CLR    (BIT(0))
+#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
+#define I2S_RX_DONE_INT_CLR_V  0x00000001U
+#define I2S_RX_DONE_INT_CLR_S  0
+/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_CLR    (BIT(1))
+#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
+#define I2S_TX_DONE_INT_CLR_V  0x00000001U
+#define I2S_TX_DONE_INT_CLR_S  1
+/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_CLR    (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
+#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_RX_HUNG_INT_CLR_S  2
+/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_CLR    (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
+#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_TX_HUNG_INT_CLR_S  3
+
+/** I2S_RX_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
+/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset receiver
+ */
+#define I2S_RX_RESET    (BIT(0))
+#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
+#define I2S_RX_RESET_V  0x00000001U
+#define I2S_RX_RESET_S  0
+/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Rx AFIFO
+ */
+#define I2S_RX_FIFO_RESET    (BIT(1))
+#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
+#define I2S_RX_FIFO_RESET_V  0x00000001U
+#define I2S_RX_FIFO_RESET_S  1
+/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start receiving data
+ */
+#define I2S_RX_START    (BIT(2))
+#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
+#define I2S_RX_START_V  0x00000001U
+#define I2S_RX_START_S  2
+/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave receiver mode
+ */
+#define I2S_RX_SLAVE_MOD    (BIT(3))
+#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
+#define I2S_RX_SLAVE_MOD_V  0x00000001U
+#define I2S_RX_SLAVE_MOD_S  3
+/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+ *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+ */
+#define I2S_RX_STOP_MODE    0x00000003U
+#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
+#define I2S_RX_STOP_MODE_V  0x00000003U
+#define I2S_RX_STOP_MODE_S  4
+/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable receiver  in mono mode
+ */
+#define I2S_RX_MONO    (BIT(6))
+#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
+#define I2S_RX_MONO_V  0x00000001U
+#define I2S_RX_MONO_S  6
+/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+ */
+#define I2S_RX_BIG_ENDIAN    (BIT(7))
+#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
+#define I2S_RX_BIG_ENDIAN_V  0x00000001U
+#define I2S_RX_BIG_ENDIAN_S  7
+/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_RX_UPDATE    (BIT(8))
+#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
+#define I2S_RX_UPDATE_V  0x00000001U
+#define I2S_RX_UPDATE_S  8
+/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+ *  channel data value is valid in I2S RX mono mode.
+ */
+#define I2S_RX_MONO_FST_VLD    (BIT(9))
+#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
+#define I2S_RX_MONO_FST_VLD_V  0x00000001U
+#define I2S_RX_MONO_FST_VLD_S  9
+/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
+ *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_RX_PCM_CONF    0x00000003U
+#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
+#define I2S_RX_PCM_CONF_V  0x00000003U
+#define I2S_RX_PCM_CONF_S  10
+/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass Compress/Decompress module for received data.
+ */
+#define I2S_RX_PCM_BYPASS    (BIT(12))
+#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
+#define I2S_RX_PCM_BYPASS_V  0x00000001U
+#define I2S_RX_PCM_BYPASS_S  12
+/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable receiver in Phillips standard mode
+ */
+#define I2S_RX_MSB_SHIFT    (BIT(13))
+#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
+#define I2S_RX_MSB_SHIFT_V  0x00000001U
+#define I2S_RX_MSB_SHIFT_S  13
+/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+ */
+#define I2S_RX_LEFT_ALIGN    (BIT(15))
+#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
+#define I2S_RX_LEFT_ALIGN_V  0x00000001U
+#define I2S_RX_LEFT_ALIGN_S  15
+/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+ */
+#define I2S_RX_24_FILL_EN    (BIT(16))
+#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
+#define I2S_RX_24_FILL_EN_V  0x00000001U
+#define I2S_RX_24_FILL_EN_S  16
+/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+ *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+ */
+#define I2S_RX_WS_IDLE_POL    (BIT(17))
+#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
+#define I2S_RX_WS_IDLE_POL_V  0x00000001U
+#define I2S_RX_WS_IDLE_POL_S  17
+/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+ *  is received first.
+ */
+#define I2S_RX_BIT_ORDER    (BIT(18))
+#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
+#define I2S_RX_BIT_ORDER_V  0x00000001U
+#define I2S_RX_BIT_ORDER_S  18
+/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_TDM_EN    (BIT(19))
+#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
+#define I2S_RX_TDM_EN_V  0x00000001U
+#define I2S_RX_TDM_EN_S  19
+/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_PDM_EN    (BIT(20))
+#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
+#define I2S_RX_PDM_EN_V  0x00000001U
+#define I2S_RX_PDM_EN_S  20
+/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in receiver mode.
+ */
+#define I2S_RX_BCK_DIV_NUM    0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
+#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_S  21
+
+/** I2S_TX_CONF_REG register
+ *  I2S TX configure register
+ */
+#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24)
+/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset transmitter
+ */
+#define I2S_TX_RESET    (BIT(0))
+#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
+#define I2S_TX_RESET_V  0x00000001U
+#define I2S_TX_RESET_S  0
+/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Tx AFIFO
+ */
+#define I2S_TX_FIFO_RESET    (BIT(1))
+#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
+#define I2S_TX_FIFO_RESET_V  0x00000001U
+#define I2S_TX_FIFO_RESET_S  1
+/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start transmitting data
+ */
+#define I2S_TX_START    (BIT(2))
+#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
+#define I2S_TX_START_V  0x00000001U
+#define I2S_TX_START_S  2
+/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave transmitter mode
+ */
+#define I2S_TX_SLAVE_MOD    (BIT(3))
+#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
+#define I2S_TX_SLAVE_MOD_V  0x00000001U
+#define I2S_TX_SLAVE_MOD_S  3
+/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+ */
+#define I2S_TX_STOP_EN    (BIT(4))
+#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
+#define I2S_TX_STOP_EN_V  0x00000001U
+#define I2S_TX_STOP_EN_S  4
+/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0;
+ *  1: The value of Left channel data is equal to the value of right channel data in
+ *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+ *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+ */
+#define I2S_TX_CHAN_EQUAL    (BIT(5))
+#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
+#define I2S_TX_CHAN_EQUAL_V  0x00000001U
+#define I2S_TX_CHAN_EQUAL_S  5
+/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter in mono mode
+ */
+#define I2S_TX_MONO    (BIT(6))
+#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
+#define I2S_TX_MONO_V  0x00000001U
+#define I2S_TX_MONO_S  6
+/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+ *  value.
+ */
+#define I2S_TX_BIG_ENDIAN    (BIT(7))
+#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
+#define I2S_TX_BIG_ENDIAN_V  0x00000001U
+#define I2S_TX_BIG_ENDIAN_S  7
+/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_TX_UPDATE    (BIT(8))
+#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
+#define I2S_TX_UPDATE_V  0x00000001U
+#define I2S_TX_UPDATE_S  8
+/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+ *  channel data value is valid in I2S TX mono mode.
+ */
+#define I2S_TX_MONO_FST_VLD    (BIT(9))
+#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
+#define I2S_TX_MONO_FST_VLD_V  0x00000001U
+#define I2S_TX_MONO_FST_VLD_S  9
+/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
+ *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_TX_PCM_CONF    0x00000003U
+#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
+#define I2S_TX_PCM_CONF_V  0x00000003U
+#define I2S_TX_PCM_CONF_S  10
+/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+ */
+#define I2S_TX_PCM_BYPASS    (BIT(12))
+#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
+#define I2S_TX_PCM_BYPASS_V  0x00000001U
+#define I2S_TX_PCM_BYPASS_S  12
+/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable transmitter in Phillips standard mode
+ */
+#define I2S_TX_MSB_SHIFT    (BIT(13))
+#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
+#define I2S_TX_MSB_SHIFT_V  0x00000001U
+#define I2S_TX_MSB_SHIFT_S  13
+/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1;
+ *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+ *  generate pos/neg edge in master mode.
+ */
+#define I2S_TX_BCK_NO_DLY    (BIT(14))
+#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
+#define I2S_TX_BCK_NO_DLY_V  0x00000001U
+#define I2S_TX_BCK_NO_DLY_S  14
+/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+ */
+#define I2S_TX_LEFT_ALIGN    (BIT(15))
+#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
+#define I2S_TX_LEFT_ALIGN_V  0x00000001U
+#define I2S_TX_LEFT_ALIGN_S  15
+/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+ */
+#define I2S_TX_24_FILL_EN    (BIT(16))
+#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
+#define I2S_TX_24_FILL_EN_V  0x00000001U
+#define I2S_TX_24_FILL_EN_S  16
+/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+ *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+ */
+#define I2S_TX_WS_IDLE_POL    (BIT(17))
+#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
+#define I2S_TX_WS_IDLE_POL_V  0x00000001U
+#define I2S_TX_WS_IDLE_POL_S  17
+/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+ *  sent first.
+ */
+#define I2S_TX_BIT_ORDER    (BIT(18))
+#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
+#define I2S_TX_BIT_ORDER_V  0x00000001U
+#define I2S_TX_BIT_ORDER_S  18
+/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_TDM_EN    (BIT(19))
+#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
+#define I2S_TX_TDM_EN_V  0x00000001U
+#define I2S_TX_TDM_EN_S  19
+/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_PDM_EN    (BIT(20))
+#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
+#define I2S_TX_PDM_EN_V  0x00000001U
+#define I2S_TX_PDM_EN_S  20
+/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in transmitter mode.
+ */
+#define I2S_TX_BCK_DIV_NUM    0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
+#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_S  21
+/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0;
+ *  I2S transmitter channel mode configuration bits.
+ */
+#define I2S_TX_CHAN_MOD    0x00000007U
+#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
+#define I2S_TX_CHAN_MOD_V  0x00000007U
+#define I2S_TX_CHAN_MOD_S  27
+/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0;
+ *  Enable signal loop back mode with transmitter module and receiver module sharing
+ *  the same WS and BCK signals.
+ */
+#define I2S_SIG_LOOPBACK    (BIT(30))
+#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
+#define I2S_SIG_LOOPBACK_V  0x00000001U
+#define I2S_SIG_LOOPBACK_S  30
+
+/** I2S_RX_CONF1_REG register
+ *  I2S RX configure register 1
+ */
+#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28)
+/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_RX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
+#define I2S_RX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_S  0
+/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+ *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_RX_BITS_MOD    0x0000001FU
+#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
+#define I2S_RX_BITS_MOD_V  0x0000001FU
+#define I2S_RX_BITS_MOD_S  14
+/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Rx half sample bits -1.
+ */
+#define I2S_RX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
+#define I2S_RX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_S  19
+/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Rx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
+#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_S  27
+
+/** I2S_TX_CONF1_REG register
+ *  I2S TX configure register 1
+ */
+#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c)
+/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_TX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
+#define I2S_TX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_S  0
+/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+ *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_TX_BITS_MOD    0x0000001FU
+#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
+#define I2S_TX_BITS_MOD_V  0x0000001FU
+#define I2S_TX_BITS_MOD_S  14
+/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Tx half sample bits -1.
+ */
+#define I2S_TX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
+#define I2S_TX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_S  19
+/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Tx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
+#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_S  27
+
+/** I2S_TX_PCM2PDM_CONF_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x40)
+/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
+ *  I2S TX PDM OSR2 value
+ */
+#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
+#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_S  1
+/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
+ *  I2S TX PDM prescale for sigmadelta
+ */
+#define I2S_TX_PDM_PRESCALE    0x000000FFU
+#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
+#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
+#define I2S_TX_PDM_PRESCALE_S  5
+/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_S  13
+/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_S  15
+/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
+/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
+/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
+ *  I2S TX PDM sigmadelta dither2 value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
+/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
+ *  I2S TX PDM sigmadelta dither value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
+/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
+ *  I2S TX PDM dac mode enable
+ */
+#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
+#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_2OUT_EN_S  23
+/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
+ *  I2S TX PDM dac 2channel enable
+ */
+#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
+#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_MODE_EN_S  24
+/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
+ *  I2S TX PDM Converter enable
+ */
+#define I2S_PCM2PDM_CONV_EN    (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
+#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
+#define I2S_PCM2PDM_CONV_EN_S  25
+
+/** I2S_TX_PCM2PDM_CONF1_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44)
+/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
+ *  I2S TX PDM Fp
+ */
+#define I2S_TX_PDM_FP    0x000003FFU
+#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
+#define I2S_TX_PDM_FP_V  0x000003FFU
+#define I2S_TX_PDM_FP_S  0
+/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
+ *  I2S TX PDM Fs
+ */
+#define I2S_TX_PDM_FS    0x000003FFU
+#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
+#define I2S_TX_PDM_FS_V  0x000003FFU
+#define I2S_TX_PDM_FS_S  10
+/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
+#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_S  20
+/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
+#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_S  23
+
+/** I2S_RX_PDM2PCM_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_PDM2PCM_CONF_REG(i) (REG_I2S_BASE(i) + 0x48)
+/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable PDM2PCM RX mode. 0: DIsable.
+ */
+#define I2S_RX_PDM2PCM_EN    (BIT(19))
+#define I2S_RX_PDM2PCM_EN_M  (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
+#define I2S_RX_PDM2PCM_EN_V  0x00000001U
+#define I2S_RX_PDM2PCM_EN_S  19
+/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
+ *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+ *  sampling rate is 128. 0: down sampling rate is 64.
+ */
+#define I2S_RX_PDM_SINC_DSR_16_EN    (BIT(20))
+#define I2S_RX_PDM_SINC_DSR_16_EN_M  (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
+#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x00000001U
+#define I2S_RX_PDM_SINC_DSR_16_EN_S  20
+/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
+ *  Configure PDM RX amplify number.
+ */
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM    0x0000000FU
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M  (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V  0x0000000FU
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S  21
+/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
+ *  I2S PDM RX bypass hp filter or not.
+ */
+#define I2S_RX_PDM_HP_BYPASS    (BIT(25))
+#define I2S_RX_PDM_HP_BYPASS_M  (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
+#define I2S_RX_PDM_HP_BYPASS_V  0x00000001U
+#define I2S_RX_PDM_HP_BYPASS_S  25
+/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
+ *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+ *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_RX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_RX_IIR_HP_MULT12_5_M  (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
+#define I2S_RX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_RX_IIR_HP_MULT12_5_S  26
+/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
+ *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+ *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_RX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_RX_IIR_HP_MULT12_0_M  (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
+#define I2S_RX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_RX_IIR_HP_MULT12_0_S  29
+
+/** I2S_RX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50)
+/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
+#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
+/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
+#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
+#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
+/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
+#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
+/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
+#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
+/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
+#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
+/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
+#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
+/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
+#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
+/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
+#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN8_EN_S  8
+/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
+#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN9_EN_S  9
+/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
+#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN10_EN_S  10
+/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
+#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN11_EN_S  11
+/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
+#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN12_EN_S  12
+/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
+#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN13_EN_S  13
+/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
+#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN14_EN_S  14
+/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
+#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN15_EN_S  15
+/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
+#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
+
+/** I2S_TX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
+/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
+#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN0_EN_S  0
+/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
+#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN1_EN_S  1
+/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
+#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN2_EN_S  2
+/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
+#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN3_EN_S  3
+/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
+#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN4_EN_S  4
+/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
+#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN5_EN_S  5
+/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
+#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN6_EN_S  6
+/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
+#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN7_EN_S  7
+/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
+#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN8_EN_S  8
+/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
+#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN9_EN_S  9
+/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
+#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN10_EN_S  10
+/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
+#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN11_EN_S  11
+/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
+#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN12_EN_S  12
+/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
+#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN13_EN_S  13
+/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
+#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN14_EN_S  14
+/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
+#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN15_EN_S  15
+/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
+#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
+/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
+ *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+ *  only the data of the enabled channels is sent, then this bit should be set. Clear
+ *  it when all the data stored in DMA TX buffer is for enabled channels.
+ */
+#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
+#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
+#define I2S_TX_TDM_SKIP_MSK_EN_S  20
+
+/** I2S_RX_TIMING_REG register
+ *  I2S RX timing control register
+ */
+#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58)
+/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD_IN_DM    0x00000003U
+#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
+#define I2S_RX_SD_IN_DM_V  0x00000003U
+#define I2S_RX_SD_IN_DM_S  0
+/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD1_IN_DM    0x00000003U
+#define I2S_RX_SD1_IN_DM_M  (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S)
+#define I2S_RX_SD1_IN_DM_V  0x00000003U
+#define I2S_RX_SD1_IN_DM_S  4
+/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0;
+ *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD2_IN_DM    0x00000003U
+#define I2S_RX_SD2_IN_DM_M  (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S)
+#define I2S_RX_SD2_IN_DM_V  0x00000003U
+#define I2S_RX_SD2_IN_DM_S  8
+/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0;
+ *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD3_IN_DM    0x00000003U
+#define I2S_RX_SD3_IN_DM_M  (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S)
+#define I2S_RX_SD3_IN_DM_V  0x00000003U
+#define I2S_RX_SD3_IN_DM_S  12
+/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_OUT_DM    0x00000003U
+#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
+#define I2S_RX_WS_OUT_DM_V  0x00000003U
+#define I2S_RX_WS_OUT_DM_S  16
+/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_OUT_DM    0x00000003U
+#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
+#define I2S_RX_BCK_OUT_DM_V  0x00000003U
+#define I2S_RX_BCK_OUT_DM_S  20
+/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_IN_DM    0x00000003U
+#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
+#define I2S_RX_WS_IN_DM_V  0x00000003U
+#define I2S_RX_WS_IN_DM_S  24
+/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_IN_DM    0x00000003U
+#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
+#define I2S_RX_BCK_IN_DM_V  0x00000003U
+#define I2S_RX_BCK_IN_DM_S  28
+
+/** I2S_TX_TIMING_REG register
+ *  I2S TX timing control register
+ */
+#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c)
+/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD_OUT_DM    0x00000003U
+#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
+#define I2S_TX_SD_OUT_DM_V  0x00000003U
+#define I2S_TX_SD_OUT_DM_S  0
+/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD1_OUT_DM    0x00000003U
+#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
+#define I2S_TX_SD1_OUT_DM_V  0x00000003U
+#define I2S_TX_SD1_OUT_DM_S  4
+/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_OUT_DM    0x00000003U
+#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
+#define I2S_TX_WS_OUT_DM_V  0x00000003U
+#define I2S_TX_WS_OUT_DM_S  16
+/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_OUT_DM    0x00000003U
+#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
+#define I2S_TX_BCK_OUT_DM_V  0x00000003U
+#define I2S_TX_BCK_OUT_DM_S  20
+/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_IN_DM    0x00000003U
+#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
+#define I2S_TX_WS_IN_DM_V  0x00000003U
+#define I2S_TX_WS_IN_DM_S  24
+/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_IN_DM    0x00000003U
+#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
+#define I2S_TX_BCK_IN_DM_V  0x00000003U
+#define I2S_TX_BCK_IN_DM_S  28
+
+/** I2S_LC_HUNG_CONF_REG register
+ *  I2S HUNG configure register.
+ */
+#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60)
+/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+ *  when fifo hung counter is equal to this value
+ */
+#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
+#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_S  0
+/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  The bits are used to scale tick counter threshold. The tick counter is reset when
+ *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+ */
+#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  The enable bit for FIFO timeout
+ */
+#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+
+/** I2S_RXEOF_NUM_REG register
+ *  I2S RX data number control register.
+ */
+#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64)
+/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
+ *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+ *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+ */
+#define I2S_RX_EOF_NUM    0x00000FFFU
+#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
+#define I2S_RX_EOF_NUM_V  0x00000FFFU
+#define I2S_RX_EOF_NUM_S  0
+
+/** I2S_CONF_SIGLE_DATA_REG register
+ *  I2S signal data register
+ */
+#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
+/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The configured constant channel data to be sent out.
+ */
+#define I2S_SINGLE_DATA    0xFFFFFFFFU
+#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
+#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
+#define I2S_SINGLE_DATA_S  0
+
+/** I2S_STATE_REG register
+ *  I2S TX status register
+ */
+#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c)
+/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
+ *  1: i2s_tx is idle state. 0: i2s_tx is working.
+ */
+#define I2S_TX_IDLE    (BIT(0))
+#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
+#define I2S_TX_IDLE_V  0x00000001U
+#define I2S_TX_IDLE_S  0
+
+/** I2S_ETM_CONF_REG register
+ *  I2S ETM configure register
+ */
+#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70)
+/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
+ *  I2S ETM send x words event. When sending word number of
+ *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
+#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_S  0
+/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
+ *  I2S ETM receive x words event. When receiving word number of
+ *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
+
+/** I2S_FIFO_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_FIFO_CNT_REG(i) (REG_I2S_BASE(i) + 0x74)
+/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
+ *  tx fifo counter value.
+ */
+#define I2S_TX_FIFO_CNT    0x7FFFFFFFU
+#define I2S_TX_FIFO_CNT_M  (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S)
+#define I2S_TX_FIFO_CNT_V  0x7FFFFFFFU
+#define I2S_TX_FIFO_CNT_S  0
+/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset tx fifo counter.
+ */
+#define I2S_TX_FIFO_CNT_RST    (BIT(31))
+#define I2S_TX_FIFO_CNT_RST_M  (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S)
+#define I2S_TX_FIFO_CNT_RST_V  0x00000001U
+#define I2S_TX_FIFO_CNT_RST_S  31
+
+/** I2S_BCK_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_BCK_CNT_REG(i) (REG_I2S_BASE(i) + 0x78)
+/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
+ *  tx bck counter value.
+ */
+#define I2S_TX_BCK_CNT    0x7FFFFFFFU
+#define I2S_TX_BCK_CNT_M  (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S)
+#define I2S_TX_BCK_CNT_V  0x7FFFFFFFU
+#define I2S_TX_BCK_CNT_S  0
+/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset tx bck counter.
+ */
+#define I2S_TX_BCK_CNT_RST    (BIT(31))
+#define I2S_TX_BCK_CNT_RST_M  (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S)
+#define I2S_TX_BCK_CNT_RST_V  0x00000001U
+#define I2S_TX_BCK_CNT_RST_S  31
+
+/** I2S_CLK_GATE_REG register
+ *  Clock gate register
+ */
+#define I2S_CLK_GATE_REG(i) (REG_I2S_BASE(i) + 0x7c)
+/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  set this bit to enable clock gate
+ */
+#define I2S_CLK_EN    (BIT(0))
+#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
+#define I2S_CLK_EN_V  0x00000001U
+#define I2S_CLK_EN_S  0
+
+/** I2S_DATE_REG register
+ *  Version control register
+ */
+#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x80)
+/** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024;
+ *  I2S version control register
+ */
+#define I2S_DATE    0x0FFFFFFFU
+#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
+#define I2S_DATE_V  0x0FFFFFFFU
+#define I2S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2s_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i2s_struct.h
new file mode 100644
index 0000000000..727e9aae71
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i2s_struct.h
@@ -0,0 +1,1012 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        uint32_t reserved_14:1;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t rx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:8;
+        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_rx_conf1_reg_t;
+
+/** Type of rx_pdm2pcm_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:19;
+        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable PDM2PCM RX mode. 0: DIsable.
+         */
+        uint32_t rx_pdm2pcm_en:1;
+        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
+         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+         *  sampling rate is 128. 0: down sampling rate is 64.
+         */
+        uint32_t rx_pdm_sinc_dsr_16_en:1;
+        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
+         *  Configure PDM RX amplify number.
+         */
+        uint32_t rx_pdm2pcm_amplify_num:4;
+        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
+         *  I2S PDM RX bypass hp filter or not.
+         */
+        uint32_t rx_pdm_hp_bypass:1;
+        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_5:3;
+        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_0:3;
+    };
+    uint32_t val;
+} i2s_rx_pdm2pcm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
+         *  I2S TX PDM bypass hp filter or not. The option has been removed.
+         */
+        uint32_t tx_pdm_hp_bypass:1;
+        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
+         *  I2S TX PDM OSR2 value
+         */
+        uint32_t tx_pdm_sinc_osr2:4;
+        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
+         *  I2S TX PDM prescale for sigmadelta
+         */
+        uint32_t tx_pdm_prescale:8;
+        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_hp_in_shift:2;
+        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_lp_in_shift:2;
+        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sinc_in_shift:2;
+        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sigmadelta_in_shift:2;
+        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
+         *  I2S TX PDM sigmadelta dither2 value
+         */
+        uint32_t tx_pdm_sigmadelta_dither2:1;
+        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
+         *  I2S TX PDM sigmadelta dither value
+         */
+        uint32_t tx_pdm_sigmadelta_dither:1;
+        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
+         *  I2S TX PDM dac mode enable
+         */
+        uint32_t tx_pdm_dac_2out_en:1;
+        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
+         *  I2S TX PDM dac 2channel enable
+         */
+        uint32_t tx_pdm_dac_mode_en:1;
+        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
+         *  I2S TX PDM Converter enable
+         */
+        uint32_t pcm2pdm_conv_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf1 register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
+         *  I2S TX PDM Fp
+         */
+        uint32_t tx_pdm_fp:10;
+        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
+         *  I2S TX PDM Fs
+         */
+        uint32_t tx_pdm_fs:10;
+        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_5:3;
+        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_0:3;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf1_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan2_en:1;
+        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan3_en:1;
+        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan4_en:1;
+        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan5_en:1;
+        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan6_en:1;
+        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan7_en:1;
+        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan8_en:1;
+        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan9_en:1;
+        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan10_en:1;
+        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan11_en:1;
+        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan12_en:1;
+        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan13_en:1;
+        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan14_en:1;
+        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan15_en:1;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rx_eof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_rx_eof_num_reg_t;
+
+
+/** Group: TX Control and configuration registers */
+/** Type of tx_conf register
+ *  I2S TX configure register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset transmitter
+         */
+        uint32_t tx_reset:1;
+        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Tx AFIFO
+         */
+        uint32_t tx_fifo_reset:1;
+        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start transmitting data
+         */
+        uint32_t tx_start:1;
+        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave transmitter mode
+         */
+        uint32_t tx_slave_mod:1;
+        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+         */
+        uint32_t tx_stop_en:1;
+        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
+         *  1: The value of Left channel data is equal to the value of right channel data in
+         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+         */
+        uint32_t tx_chan_equal:1;
+        /** tx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter in mono mode
+         */
+        uint32_t tx_mono:1;
+        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+         *  value.
+         */
+        uint32_t tx_big_endian:1;
+        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t tx_update:1;
+        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+         *  channel data value is valid in I2S TX mono mode.
+         */
+        uint32_t tx_mono_fst_vld:1;
+        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
+         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t tx_pcm_conf:2;
+        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+         */
+        uint32_t tx_pcm_bypass:1;
+        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable transmitter in Phillips standard mode
+         */
+        uint32_t tx_msb_shift:1;
+        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
+         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+         *  generate pos/neg edge in master mode.
+         */
+        uint32_t tx_bck_no_dly:1;
+        /** tx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+         */
+        uint32_t tx_left_align:1;
+        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+         */
+        uint32_t tx_24_fill_en:1;
+        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+         */
+        uint32_t tx_ws_idle_pol:1;
+        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+         *  sent first.
+         */
+        uint32_t tx_bit_order:1;
+        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_tdm_en:1;
+        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_pdm_en:1;
+        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in transmitter mode.
+         */
+        uint32_t tx_bck_div_num:6;
+        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
+         *  I2S transmitter channel mode configuration bits.
+         */
+        uint32_t tx_chan_mod:3;
+        /** sig_loopback : R/W; bitpos: [30]; default: 0;
+         *  Enable signal loop back mode with transmitter module and receiver module sharing
+         *  the same WS and BCK signals.
+         */
+        uint32_t sig_loopback:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_tx_conf_reg_t;
+
+/** Type of tx_conf1 register
+ *  I2S TX configure register 1
+ */
+typedef union {
+    struct {
+        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t tx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t tx_bits_mod:5;
+        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Tx half sample bits -1.
+         */
+        uint32_t tx_half_sample_bits:8;
+        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Tx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t tx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_tx_conf1_reg_t;
+
+/** Type of tx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan0_en:1;
+        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan1_en:1;
+        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan2_en:1;
+        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan3_en:1;
+        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan4_en:1;
+        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan5_en:1;
+        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan6_en:1;
+        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan7_en:1;
+        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan8_en:1;
+        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan9_en:1;
+        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan10_en:1;
+        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan11_en:1;
+        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan12_en:1;
+        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan13_en:1;
+        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan14_en:1;
+        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan15_en:1;
+        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t tx_tdm_tot_chan_num:4;
+        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
+         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+         *  only the data of the enabled channels is sent, then this bit should be set. Clear
+         *  it when all the data stored in DMA TX buffer is for enabled channels.
+         */
+        uint32_t tx_tdm_skip_msk_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i2s_tx_tdm_ctrl_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:2;
+        /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd1_in_dm:2;
+        uint32_t reserved_6:2;
+        /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0;
+         *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd2_in_dm:2;
+        uint32_t reserved_10:2;
+        /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0;
+         *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd3_in_dm:2;
+        uint32_t reserved_14:2;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_rx_timing_reg_t;
+
+
+/** Group: TX clock and timing registers */
+/** Type of tx_timing register
+ *  I2S TX timing control register
+ */
+typedef union {
+    struct {
+        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd_out_dm:2;
+        uint32_t reserved_2:2;
+        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd1_out_dm:2;
+        uint32_t reserved_6:10;
+        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_tx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_single_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} i2s_conf_single_data_reg_t;
+
+
+/** Group: TX status registers */
+/** Type of state register
+ *  I2S TX status register
+ */
+typedef union {
+    struct {
+        /** tx_idle : RO; bitpos: [0]; default: 1;
+         *  1: i2s_tx is idle state. 0: i2s_tx is working.
+         */
+        uint32_t tx_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_state_reg_t;
+
+
+/** Group: ETM registers */
+/** Type of etm_conf register
+ *  I2S ETM configure register
+ */
+typedef union {
+    struct {
+        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
+         *  I2S ETM send x words event. When sending word number of
+         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_tx_send_word_num:10;
+        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
+         *  I2S ETM receive x words event. When receiving word number of
+         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_rx_receive_word_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_etm_conf_reg_t;
+
+
+/** Group: Sync counter registers */
+/** Type of fifo_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx fifo counter value.
+         */
+        uint32_t tx_fifo_cnt:31;
+        /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx fifo counter.
+         */
+        uint32_t tx_fifo_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_fifo_cnt_reg_t;
+
+/** Type of bck_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx bck counter value.
+         */
+        uint32_t tx_bck_cnt:31;
+        /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx bck counter.
+         */
+        uint32_t tx_bck_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_bck_cnt_reg_t;
+
+
+/** Group: Clock registers */
+/** Type of clk_gate register
+ *  Clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit to enable clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_clk_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36713024;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile i2s_int_raw_reg_t int_raw;
+    volatile i2s_int_st_reg_t int_st;
+    volatile i2s_int_ena_reg_t int_ena;
+    volatile i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile i2s_rx_conf_reg_t rx_conf;
+    volatile i2s_tx_conf_reg_t tx_conf;
+    volatile i2s_rx_conf1_reg_t rx_conf1;
+    volatile i2s_tx_conf1_reg_t tx_conf1;
+    uint32_t reserved_030[4];
+    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
+    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
+    volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
+    uint32_t reserved_04c;
+    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
+    volatile i2s_rx_timing_reg_t rx_timing;
+    volatile i2s_tx_timing_reg_t tx_timing;
+    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile i2s_rx_eof_num_reg_t rx_eof_num;
+    volatile i2s_conf_single_data_reg_t conf_single_data;
+    volatile i2s_state_reg_t state;
+    volatile i2s_etm_conf_reg_t etm_conf;
+    volatile i2s_fifo_cnt_reg_t fifo_cnt;
+    volatile i2s_bck_cnt_reg_t bck_cnt;
+    volatile i2s_clk_gate_reg_t clk_gate;
+    volatile i2s_date_reg_t date;
+} i2s_dev_t;
+
+extern i2s_dev_t I2S0;
+extern i2s_dev_t I2S1;
+extern i2s_dev_t I2S2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_mem_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_mem_eco5_struct.h
new file mode 100644
index 0000000000..b6d4d6431d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_mem_eco5_struct.h
@@ -0,0 +1,1354 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: I3C COMMAND BUF PORT REG */
+/** Type of command_buf_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_command : R/W; bitpos: [31:0]; default: 0;
+         *  Contains a Command Descriptor structure that depends on the requested transfer
+         *  type. Command Descriptor structure is used to schedule the transfers to devices on
+         *  I3C bus.
+         */
+        uint32_t reg_command:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_command_buf_port_reg_t;
+
+
+/** Group: I3C RESPONSE BUF PORT REG */
+/** Type of response_buf_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** response : RO; bitpos: [31:0]; default: 0;
+         *  The Response Buffer can be read through this register. The response status for each
+         *  Command is written into the Response Buffer by the controller if ROC (Response On
+         *  Completion) bit is set or if transfer error has occurred. The response buffer can
+         *  be read through this register.
+         */
+        uint32_t response:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_response_buf_port_reg_t;
+
+
+/** Group: I3C RX DATA PORT REG */
+/** Type of rx_data_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** rx_data_port : RO; bitpos: [31:0]; default: 0;
+         *  Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is
+         *  always packed in 4-byte aligned data words.  If the length of data transfer is not
+         *  aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional
+         *  data bytes have to be ignored) at the end of the transferred data. The valid data
+         *  must be identified using the DATA_LENGTH filed in the Response Descriptor.
+         */
+        uint32_t rx_data_port:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_rx_data_port_reg_t;
+
+
+/** Group: I3C TX DATA PORT REG */
+/** Type of tx_data_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tx_data_port : R/W; bitpos: [31:0]; default: 0;
+         *  Transmit Data Port. Transmit data is mapped to the Tx-data  buffer and transmit
+         *  data is always packed in 4-byte aligned data words.  If the length of data transfer
+         *  is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the
+         *  additional data bytes have to be ignored) at the end of the transferred data. The
+         *  valid data must be identified using the DATA_LENGTH filed in the Response
+         *  Descriptor.
+         */
+        uint32_t reg_tx_data_port:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_tx_data_port_reg_t;
+
+
+/** Group: I3C IBI STATUS BUF REG */
+/** Type of ibi_status_buf register
+ *  In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is
+ *  used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)
+ */
+typedef union {
+    struct {
+        /** data_length : RO; bitpos: [7:0]; default: 0;
+         *  This field represents the length of data received along with IBI, in bytes.
+         */
+        uint32_t data_length:8;
+        /** ibi_id : RO; bitpos: [15:8]; default: 0;
+         *  IBI Identifier. The byte received after START which includes the address the R/W
+         *  bit: Device  address and R/W bit in case of Slave Interrupt or Master Request.
+         */
+        uint32_t ibi_id:8;
+        uint32_t reserved_16:12;
+        /** ibi_sts : RO; bitpos: [28]; default: 0;
+         *  IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI
+         *  Data is always packed in4-byte aligned and put to the IBI Buffer. This register
+         *  When read from, reads the data from the IBI buffer. IBI Status register when read
+         *  from, returns the data from the IBI Buffer and indicates how the controller
+         *  responded to incoming IBI(SIR, MR and HJ).
+         */
+        uint32_t ibi_sts:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} i3c_mst_mem_ibi_status_buf_reg_t;
+
+
+/** Group: I3C IBI DATA BUF REG */
+/** Type of ibi_data_buf register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ibi_data : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_ibi_data_buf_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE1 LOC REG */
+/** Type of dev_addr_table1_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev1_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev1_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev1_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev1_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev1_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev1_nack_retry_cnt:2;
+        /** reg_dat_dev1_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev1_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table1_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE2 LOC REG */
+/** Type of dev_addr_table2_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev2_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev2_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev2_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev2_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev2_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev2_nack_retry_cnt:2;
+        /** reg_dat_dev2_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev2_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table2_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE3 LOC REG */
+/** Type of dev_addr_table3_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev3_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev3_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev3_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev3_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev3_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev3_nack_retry_cnt:2;
+        /** reg_dat_dev3_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev3_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table3_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE4 LOC REG */
+/** Type of dev_addr_table4_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev4_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev4_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev4_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev4_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev4_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev4_nack_retry_cnt:2;
+        /** reg_dat_dev4_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev4_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table4_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE5 LOC REG */
+/** Type of dev_addr_table5_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev5_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev5_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev5_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev5_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev5_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev5_nack_retry_cnt:2;
+        /** reg_dat_dev5_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev5_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table5_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE6 LOC REG */
+/** Type of dev_addr_table6_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev6_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev6_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev6_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev6_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev6_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev6_nack_retry_cnt:2;
+        /** reg_dat_dev6_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev6_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table6_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE7 LOC REG */
+/** Type of dev_addr_table7_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev7_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev7_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev7_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev7_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev7_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev7_nack_retry_cnt:2;
+        /** reg_dat_dev7_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev7_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table7_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE8 LOC REG */
+/** Type of dev_addr_table8_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev8_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev8_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev8_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev8_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev8_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev8_nack_retry_cnt:2;
+        /** reg_dat_dev8_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev8_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table8_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE9 LOC REG */
+/** Type of dev_addr_table9_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev9_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev9_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev9_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev9_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev9_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev9_nack_retry_cnt:2;
+        /** reg_dat_dev9_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev9_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table9_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE10 LOC REG */
+/** Type of dev_addr_table10_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev10_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev10_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev10_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev10_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev10_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev10_nack_retry_cnt:2;
+        /** reg_dat_dev10_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev10_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table10_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE11 LOC REG */
+/** Type of dev_addr_table11_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev11_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev11_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev11_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev11_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev11_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev11_nack_retry_cnt:2;
+        /** reg_dat_dev11_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev11_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table11_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE12 LOC REG */
+/** Type of dev_addr_table12_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev12_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev12_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev12_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev12_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev12_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev12_nack_retry_cnt:2;
+        /** reg_dat_dev12_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev12_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table12_loc_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE1 LOC1 REG */
+/** Type of dev_char_table1_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev1_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev1_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table1_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE1 LOC2 REG */
+/** Type of dev_char_table1_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev1_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev1_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table1_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE1 LOC3 REG */
+/** Type of dev_char_table1_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev1_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev1_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table1_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE1 LOC4 REG */
+/** Type of dev_char_table1_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev1_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev1_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table1_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE2 LOC1 REG */
+/** Type of dev_char_table2_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev2_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev2_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table2_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE2 LOC2 REG */
+/** Type of dev_char_table2_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev2_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev2_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table2_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE2 LOC3 REG */
+/** Type of dev_char_table2_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev2_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev2_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table2_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE2 LOC4 REG */
+/** Type of dev_char_table2_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev2_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev2_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table2_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE3 LOC1 REG */
+/** Type of dev_char_table3_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev3_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev3_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table3_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE3 LOC2 REG */
+/** Type of dev_char_table3_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev3_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev3_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table3_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE3 LOC3 REG */
+/** Type of dev_char_table3_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev3_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev3_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table3_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE3 LOC4 REG */
+/** Type of dev_char_table3_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev3_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev3_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table3_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE4 LOC1 REG */
+/** Type of dev_char_table4_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev4_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev4_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table4_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE4 LOC2 REG */
+/** Type of dev_char_table4_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev4_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev4_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table4_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE4 LOC3 REG */
+/** Type of dev_char_table4_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev4_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev4_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table4_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE4 LOC4 REG */
+/** Type of dev_char_table4_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev4_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev4_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table4_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE5 LOC1 REG */
+/** Type of dev_char_table5_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev5_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev5_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table5_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE5 LOC2 REG */
+/** Type of dev_char_table5_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev5_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev5_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table5_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE5 LOC3 REG */
+/** Type of dev_char_table5_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev5_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev5_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table5_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE5 LOC4 REG */
+/** Type of dev_char_table5_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev5_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev5_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table5_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE6 LOC1 REG */
+/** Type of dev_char_table6_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev6_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev6_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table6_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE6 LOC2 REG */
+/** Type of dev_char_table6_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev6_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev6_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table6_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE6 LOC3 REG */
+/** Type of dev_char_table6_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev6_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev6_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table6_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE6 LOC4 REG */
+/** Type of dev_char_table6_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev6_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev6_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table6_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE7 LOC1 REG */
+/** Type of dev_char_table7_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev7_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev7_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table7_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE7 LOC2 REG */
+/** Type of dev_char_table7_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev7_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev7_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table7_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE7 LOC3 REG */
+/** Type of dev_char_table7_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev7_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev7_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table7_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE7 LOC4 REG */
+/** Type of dev_char_table7_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev7_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev7_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table7_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE8 LOC1 REG */
+/** Type of dev_char_table8_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev8_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev8_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table8_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE8 LOC2 REG */
+/** Type of dev_char_table8_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev8_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev8_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table8_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE8 LOC3 REG */
+/** Type of dev_char_table8_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev8_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev8_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table8_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE8 LOC4 REG */
+/** Type of dev_char_table8_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev8_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev8_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table8_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE9 LOC1 REG */
+/** Type of dev_char_table9_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev9_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev9_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table9_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE9 LOC2 REG */
+/** Type of dev_char_table9_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev9_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev9_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table9_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE9 LOC3 REG */
+/** Type of dev_char_table9_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev9_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev9_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table9_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE9 LOC4 REG */
+/** Type of dev_char_table9_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev9_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev9_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table9_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE10 LOC1 REG */
+/** Type of dev_char_table10_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev10_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev10_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table10_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE10 LOC2 REG */
+/** Type of dev_char_table10_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev10_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev10_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table10_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE10 LOC3 REG */
+/** Type of dev_char_table10_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev10_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev10_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table10_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE10 LOC4 REG */
+/** Type of dev_char_table10_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev10_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev10_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table10_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE11 LOC1 REG */
+/** Type of dev_char_table11_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev11_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev11_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table11_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE11 LOC2 REG */
+/** Type of dev_char_table11_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev11_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev11_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table11_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE11 LOC3 REG */
+/** Type of dev_char_table11_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev11_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev11_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table11_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE11 LOC4 REG */
+/** Type of dev_char_table11_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev11_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev11_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table11_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE12 LOC1 REG */
+/** Type of dev_char_table12_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev12_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev12_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table12_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE12 LOC2 REG */
+/** Type of dev_char_table12_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev12_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev12_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table12_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE12 LOC3 REG */
+/** Type of dev_char_table12_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev12_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev12_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table12_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE12 LOC4 REG */
+/** Type of dev_char_table12_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev12_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev12_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table12_loc4_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[2];
+    volatile i3c_mst_mem_command_buf_port_reg_t command_buf_port;
+    volatile i3c_mst_mem_response_buf_port_reg_t response_buf_port;
+    volatile i3c_mst_mem_rx_data_port_reg_t rx_data_port;
+    volatile i3c_mst_mem_tx_data_port_reg_t tx_data_port;
+    volatile i3c_mst_mem_ibi_status_buf_reg_t ibi_status_buf;
+    uint32_t reserved_01c[9];
+    volatile i3c_mst_mem_ibi_data_buf_reg_t ibi_data_buf;
+    uint32_t reserved_044[31];
+    volatile i3c_mst_mem_dev_addr_table1_loc_reg_t dev_addr_table1_loc;
+    volatile i3c_mst_mem_dev_addr_table2_loc_reg_t dev_addr_table2_loc;
+    volatile i3c_mst_mem_dev_addr_table3_loc_reg_t dev_addr_table3_loc;
+    volatile i3c_mst_mem_dev_addr_table4_loc_reg_t dev_addr_table4_loc;
+    volatile i3c_mst_mem_dev_addr_table5_loc_reg_t dev_addr_table5_loc;
+    volatile i3c_mst_mem_dev_addr_table6_loc_reg_t dev_addr_table6_loc;
+    volatile i3c_mst_mem_dev_addr_table7_loc_reg_t dev_addr_table7_loc;
+    volatile i3c_mst_mem_dev_addr_table8_loc_reg_t dev_addr_table8_loc;
+    volatile i3c_mst_mem_dev_addr_table9_loc_reg_t dev_addr_table9_loc;
+    volatile i3c_mst_mem_dev_addr_table10_loc_reg_t dev_addr_table10_loc;
+    volatile i3c_mst_mem_dev_addr_table11_loc_reg_t dev_addr_table11_loc;
+    volatile i3c_mst_mem_dev_addr_table12_loc_reg_t dev_addr_table12_loc;
+    uint32_t reserved_0f0[4];
+    volatile i3c_mst_mem_dev_char_table1_loc1_reg_t dev_char_table1_loc1;
+    volatile i3c_mst_mem_dev_char_table1_loc2_reg_t dev_char_table1_loc2;
+    volatile i3c_mst_mem_dev_char_table1_loc3_reg_t dev_char_table1_loc3;
+    volatile i3c_mst_mem_dev_char_table1_loc4_reg_t dev_char_table1_loc4;
+    volatile i3c_mst_mem_dev_char_table2_loc1_reg_t dev_char_table2_loc1;
+    volatile i3c_mst_mem_dev_char_table2_loc2_reg_t dev_char_table2_loc2;
+    volatile i3c_mst_mem_dev_char_table2_loc3_reg_t dev_char_table2_loc3;
+    volatile i3c_mst_mem_dev_char_table2_loc4_reg_t dev_char_table2_loc4;
+    volatile i3c_mst_mem_dev_char_table3_loc1_reg_t dev_char_table3_loc1;
+    volatile i3c_mst_mem_dev_char_table3_loc2_reg_t dev_char_table3_loc2;
+    volatile i3c_mst_mem_dev_char_table3_loc3_reg_t dev_char_table3_loc3;
+    volatile i3c_mst_mem_dev_char_table3_loc4_reg_t dev_char_table3_loc4;
+    volatile i3c_mst_mem_dev_char_table4_loc1_reg_t dev_char_table4_loc1;
+    volatile i3c_mst_mem_dev_char_table4_loc2_reg_t dev_char_table4_loc2;
+    volatile i3c_mst_mem_dev_char_table4_loc3_reg_t dev_char_table4_loc3;
+    volatile i3c_mst_mem_dev_char_table4_loc4_reg_t dev_char_table4_loc4;
+    volatile i3c_mst_mem_dev_char_table5_loc1_reg_t dev_char_table5_loc1;
+    volatile i3c_mst_mem_dev_char_table5_loc2_reg_t dev_char_table5_loc2;
+    volatile i3c_mst_mem_dev_char_table5_loc3_reg_t dev_char_table5_loc3;
+    volatile i3c_mst_mem_dev_char_table5_loc4_reg_t dev_char_table5_loc4;
+    volatile i3c_mst_mem_dev_char_table6_loc1_reg_t dev_char_table6_loc1;
+    volatile i3c_mst_mem_dev_char_table6_loc2_reg_t dev_char_table6_loc2;
+    volatile i3c_mst_mem_dev_char_table6_loc3_reg_t dev_char_table6_loc3;
+    volatile i3c_mst_mem_dev_char_table6_loc4_reg_t dev_char_table6_loc4;
+    volatile i3c_mst_mem_dev_char_table7_loc1_reg_t dev_char_table7_loc1;
+    volatile i3c_mst_mem_dev_char_table7_loc2_reg_t dev_char_table7_loc2;
+    volatile i3c_mst_mem_dev_char_table7_loc3_reg_t dev_char_table7_loc3;
+    volatile i3c_mst_mem_dev_char_table7_loc4_reg_t dev_char_table7_loc4;
+    volatile i3c_mst_mem_dev_char_table8_loc1_reg_t dev_char_table8_loc1;
+    volatile i3c_mst_mem_dev_char_table8_loc2_reg_t dev_char_table8_loc2;
+    volatile i3c_mst_mem_dev_char_table8_loc3_reg_t dev_char_table8_loc3;
+    volatile i3c_mst_mem_dev_char_table8_loc4_reg_t dev_char_table8_loc4;
+    volatile i3c_mst_mem_dev_char_table9_loc1_reg_t dev_char_table9_loc1;
+    volatile i3c_mst_mem_dev_char_table9_loc2_reg_t dev_char_table9_loc2;
+    volatile i3c_mst_mem_dev_char_table9_loc3_reg_t dev_char_table9_loc3;
+    volatile i3c_mst_mem_dev_char_table9_loc4_reg_t dev_char_table9_loc4;
+    volatile i3c_mst_mem_dev_char_table10_loc1_reg_t dev_char_table10_loc1;
+    volatile i3c_mst_mem_dev_char_table10_loc2_reg_t dev_char_table10_loc2;
+    volatile i3c_mst_mem_dev_char_table10_loc3_reg_t dev_char_table10_loc3;
+    volatile i3c_mst_mem_dev_char_table10_loc4_reg_t dev_char_table10_loc4;
+    volatile i3c_mst_mem_dev_char_table11_loc1_reg_t dev_char_table11_loc1;
+    volatile i3c_mst_mem_dev_char_table11_loc2_reg_t dev_char_table11_loc2;
+    volatile i3c_mst_mem_dev_char_table11_loc3_reg_t dev_char_table11_loc3;
+    volatile i3c_mst_mem_dev_char_table11_loc4_reg_t dev_char_table11_loc4;
+    volatile i3c_mst_mem_dev_char_table12_loc1_reg_t dev_char_table12_loc1;
+    volatile i3c_mst_mem_dev_char_table12_loc2_reg_t dev_char_table12_loc2;
+    volatile i3c_mst_mem_dev_char_table12_loc3_reg_t dev_char_table12_loc3;
+    volatile i3c_mst_mem_dev_char_table12_loc4_reg_t dev_char_table12_loc4;
+} i3c_mst_mem_dev_t;
+
+extern i3c_mst_mem_dev_t I3C_MST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i3c_mst_mem_dev_t) == 0x1c0, "Invalid size of i3c_mst_mem_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_mem_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_mem_reg.h
new file mode 100644
index 0000000000..4b729dde74
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_mem_reg.h
@@ -0,0 +1,1166 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I3C_MST_MEM_COMMAND_BUF_PORT_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_COMMAND_BUF_PORT_REG (DR_REG_I3C_MST_MEM_BASE + 0x8)
+/** I3C_MST_MEM_REG_COMMAND : R/W; bitpos: [31:0]; default: 0;
+ *  Contains a Command Descriptor structure that depends on the requested transfer
+ *  type. Command Descriptor structure is used to schedule the transfers to devices on
+ *  I3C bus.
+ */
+#define I3C_MST_MEM_REG_COMMAND    0xFFFFFFFFU
+#define I3C_MST_MEM_REG_COMMAND_M  (I3C_MST_MEM_REG_COMMAND_V << I3C_MST_MEM_REG_COMMAND_S)
+#define I3C_MST_MEM_REG_COMMAND_V  0xFFFFFFFFU
+#define I3C_MST_MEM_REG_COMMAND_S  0
+
+/** I3C_MST_MEM_RESPONSE_BUF_PORT_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_RESPONSE_BUF_PORT_REG (DR_REG_I3C_MST_MEM_BASE + 0xc)
+/** I3C_MST_MEM_RESPONSE : RO; bitpos: [31:0]; default: 0;
+ *  The Response Buffer can be read through this register. The response status for each
+ *  Command is written into the Response Buffer by the controller if ROC (Response On
+ *  Completion) bit is set or if transfer error has occurred. The response buffer can
+ *  be read through this register.
+ */
+#define I3C_MST_MEM_RESPONSE    0xFFFFFFFFU
+#define I3C_MST_MEM_RESPONSE_M  (I3C_MST_MEM_RESPONSE_V << I3C_MST_MEM_RESPONSE_S)
+#define I3C_MST_MEM_RESPONSE_V  0xFFFFFFFFU
+#define I3C_MST_MEM_RESPONSE_S  0
+
+/** I3C_MST_MEM_RX_DATA_PORT_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_RX_DATA_PORT_REG (DR_REG_I3C_MST_MEM_BASE + 0x10)
+/** I3C_MST_MEM_RX_DATA_PORT : RO; bitpos: [31:0]; default: 0;
+ *  Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is
+ *  always packed in 4-byte aligned data words.  If the length of data transfer is not
+ *  aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional
+ *  data bytes have to be ignored) at the end of the transferred data. The valid data
+ *  must be identified using the DATA_LENGTH filed in the Response Descriptor.
+ */
+#define I3C_MST_MEM_RX_DATA_PORT    0xFFFFFFFFU
+#define I3C_MST_MEM_RX_DATA_PORT_M  (I3C_MST_MEM_RX_DATA_PORT_V << I3C_MST_MEM_RX_DATA_PORT_S)
+#define I3C_MST_MEM_RX_DATA_PORT_V  0xFFFFFFFFU
+#define I3C_MST_MEM_RX_DATA_PORT_S  0
+
+/** I3C_MST_MEM_TX_DATA_PORT_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_TX_DATA_PORT_REG (DR_REG_I3C_MST_MEM_BASE + 0x14)
+/** I3C_MST_MEM_REG_TX_DATA_PORT : R/W; bitpos: [31:0]; default: 0;
+ *  Transmit Data Port. Transmit data is mapped to the Tx-data  buffer and transmit
+ *  data is always packed in 4-byte aligned data words.  If the length of data transfer
+ *  is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the
+ *  additional data bytes have to be ignored) at the end of the transferred data. The
+ *  valid data must be identified using the DATA_LENGTH filed in the Response
+ *  Descriptor.
+ */
+#define I3C_MST_MEM_REG_TX_DATA_PORT    0xFFFFFFFFU
+#define I3C_MST_MEM_REG_TX_DATA_PORT_M  (I3C_MST_MEM_REG_TX_DATA_PORT_V << I3C_MST_MEM_REG_TX_DATA_PORT_S)
+#define I3C_MST_MEM_REG_TX_DATA_PORT_V  0xFFFFFFFFU
+#define I3C_MST_MEM_REG_TX_DATA_PORT_S  0
+
+/** I3C_MST_MEM_IBI_STATUS_BUF_REG register
+ *  In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is
+ *  used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)
+ */
+#define I3C_MST_MEM_IBI_STATUS_BUF_REG (DR_REG_I3C_MST_MEM_BASE + 0x18)
+/** I3C_MST_MEM_DATA_LENGTH : RO; bitpos: [7:0]; default: 0;
+ *  This field represents the length of data received along with IBI, in bytes.
+ */
+#define I3C_MST_MEM_DATA_LENGTH    0x000000FFU
+#define I3C_MST_MEM_DATA_LENGTH_M  (I3C_MST_MEM_DATA_LENGTH_V << I3C_MST_MEM_DATA_LENGTH_S)
+#define I3C_MST_MEM_DATA_LENGTH_V  0x000000FFU
+#define I3C_MST_MEM_DATA_LENGTH_S  0
+/** I3C_MST_MEM_IBI_ID : RO; bitpos: [15:8]; default: 0;
+ *  IBI Identifier. The byte received after START which includes the address the R/W
+ *  bit: Device  address and R/W bit in case of Slave Interrupt or Master Request.
+ */
+#define I3C_MST_MEM_IBI_ID    0x000000FFU
+#define I3C_MST_MEM_IBI_ID_M  (I3C_MST_MEM_IBI_ID_V << I3C_MST_MEM_IBI_ID_S)
+#define I3C_MST_MEM_IBI_ID_V  0x000000FFU
+#define I3C_MST_MEM_IBI_ID_S  8
+/** I3C_MST_MEM_IBI_STS : RO; bitpos: [28]; default: 0;
+ *  IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI
+ *  Data is always packed in4-byte aligned and put to the IBI Buffer. This register
+ *  When read from, reads the data from the IBI buffer. IBI Status register when read
+ *  from, returns the data from the IBI Buffer and indicates how the controller
+ *  responded to incoming IBI(SIR, MR and HJ).
+ */
+#define I3C_MST_MEM_IBI_STS    (BIT(28))
+#define I3C_MST_MEM_IBI_STS_M  (I3C_MST_MEM_IBI_STS_V << I3C_MST_MEM_IBI_STS_S)
+#define I3C_MST_MEM_IBI_STS_V  0x00000001U
+#define I3C_MST_MEM_IBI_STS_S  28
+
+/** I3C_MST_MEM_IBI_DATA_BUF_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_IBI_DATA_BUF_REG (DR_REG_I3C_MST_MEM_BASE + 0x40)
+/** I3C_MST_MEM_IBI_DATA : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_IBI_DATA    0xFFFFFFFFU
+#define I3C_MST_MEM_IBI_DATA_M  (I3C_MST_MEM_IBI_DATA_V << I3C_MST_MEM_IBI_DATA_S)
+#define I3C_MST_MEM_IBI_DATA_V  0xFFFFFFFFU
+#define I3C_MST_MEM_IBI_DATA_S  0
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xc0)
+/** I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV1_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV1_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV1_I2C_M  (I3C_MST_MEM_REG_DAT_DEV1_I2C_V << I3C_MST_MEM_REG_DAT_DEV1_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV1_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV1_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xc4)
+/** I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV2_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV2_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV2_I2C_M  (I3C_MST_MEM_REG_DAT_DEV2_I2C_V << I3C_MST_MEM_REG_DAT_DEV2_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV2_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV2_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xc8)
+/** I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV3_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV3_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV3_I2C_M  (I3C_MST_MEM_REG_DAT_DEV3_I2C_V << I3C_MST_MEM_REG_DAT_DEV3_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV3_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV3_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xcc)
+/** I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV4_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV4_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV4_I2C_M  (I3C_MST_MEM_REG_DAT_DEV4_I2C_V << I3C_MST_MEM_REG_DAT_DEV4_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV4_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV4_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xd0)
+/** I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV5_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV5_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV5_I2C_M  (I3C_MST_MEM_REG_DAT_DEV5_I2C_V << I3C_MST_MEM_REG_DAT_DEV5_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV5_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV5_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xd4)
+/** I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV6_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV6_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV6_I2C_M  (I3C_MST_MEM_REG_DAT_DEV6_I2C_V << I3C_MST_MEM_REG_DAT_DEV6_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV6_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV6_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xd8)
+/** I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV7_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV7_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV7_I2C_M  (I3C_MST_MEM_REG_DAT_DEV7_I2C_V << I3C_MST_MEM_REG_DAT_DEV7_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV7_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV7_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xdc)
+/** I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV8_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV8_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV8_I2C_M  (I3C_MST_MEM_REG_DAT_DEV8_I2C_V << I3C_MST_MEM_REG_DAT_DEV8_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV8_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV8_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xe0)
+/** I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV9_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV9_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV9_I2C_M  (I3C_MST_MEM_REG_DAT_DEV9_I2C_V << I3C_MST_MEM_REG_DAT_DEV9_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV9_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV9_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xe4)
+/** I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV10_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV10_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV10_I2C_M  (I3C_MST_MEM_REG_DAT_DEV10_I2C_V << I3C_MST_MEM_REG_DAT_DEV10_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV10_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV10_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xe8)
+/** I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV11_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV11_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV11_I2C_M  (I3C_MST_MEM_REG_DAT_DEV11_I2C_V << I3C_MST_MEM_REG_DAT_DEV11_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV11_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV11_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xec)
+/** I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV12_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV12_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV12_I2C_M  (I3C_MST_MEM_REG_DAT_DEV12_I2C_V << I3C_MST_MEM_REG_DAT_DEV12_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV12_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV12_I2C_S  31
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE1_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE1_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x100)
+/** I3C_MST_MEM_DCT_DEV1_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV1_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC1_M  (I3C_MST_MEM_DCT_DEV1_LOC1_V << I3C_MST_MEM_DCT_DEV1_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV1_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE1_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE1_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x104)
+/** I3C_MST_MEM_DCT_DEV1_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV1_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC2_M  (I3C_MST_MEM_DCT_DEV1_LOC2_V << I3C_MST_MEM_DCT_DEV1_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV1_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE1_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE1_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x108)
+/** I3C_MST_MEM_DCT_DEV1_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV1_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC3_M  (I3C_MST_MEM_DCT_DEV1_LOC3_V << I3C_MST_MEM_DCT_DEV1_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV1_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE1_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE1_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x10c)
+/** I3C_MST_MEM_DCT_DEV1_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV1_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC4_M  (I3C_MST_MEM_DCT_DEV1_LOC4_V << I3C_MST_MEM_DCT_DEV1_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV1_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE2_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE2_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x110)
+/** I3C_MST_MEM_DCT_DEV2_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV2_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC1_M  (I3C_MST_MEM_DCT_DEV2_LOC1_V << I3C_MST_MEM_DCT_DEV2_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV2_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE2_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE2_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x114)
+/** I3C_MST_MEM_DCT_DEV2_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV2_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC2_M  (I3C_MST_MEM_DCT_DEV2_LOC2_V << I3C_MST_MEM_DCT_DEV2_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV2_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE2_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE2_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x118)
+/** I3C_MST_MEM_DCT_DEV2_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV2_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC3_M  (I3C_MST_MEM_DCT_DEV2_LOC3_V << I3C_MST_MEM_DCT_DEV2_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV2_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE2_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE2_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x11c)
+/** I3C_MST_MEM_DCT_DEV2_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV2_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC4_M  (I3C_MST_MEM_DCT_DEV2_LOC4_V << I3C_MST_MEM_DCT_DEV2_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV2_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE3_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE3_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x120)
+/** I3C_MST_MEM_DCT_DEV3_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV3_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC1_M  (I3C_MST_MEM_DCT_DEV3_LOC1_V << I3C_MST_MEM_DCT_DEV3_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV3_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE3_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE3_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x124)
+/** I3C_MST_MEM_DCT_DEV3_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV3_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC2_M  (I3C_MST_MEM_DCT_DEV3_LOC2_V << I3C_MST_MEM_DCT_DEV3_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV3_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE3_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE3_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x128)
+/** I3C_MST_MEM_DCT_DEV3_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV3_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC3_M  (I3C_MST_MEM_DCT_DEV3_LOC3_V << I3C_MST_MEM_DCT_DEV3_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV3_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE3_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE3_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x12c)
+/** I3C_MST_MEM_DCT_DEV3_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV3_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC4_M  (I3C_MST_MEM_DCT_DEV3_LOC4_V << I3C_MST_MEM_DCT_DEV3_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV3_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE4_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE4_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x130)
+/** I3C_MST_MEM_DCT_DEV4_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV4_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC1_M  (I3C_MST_MEM_DCT_DEV4_LOC1_V << I3C_MST_MEM_DCT_DEV4_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV4_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE4_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE4_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x134)
+/** I3C_MST_MEM_DCT_DEV4_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV4_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC2_M  (I3C_MST_MEM_DCT_DEV4_LOC2_V << I3C_MST_MEM_DCT_DEV4_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV4_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE4_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE4_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x138)
+/** I3C_MST_MEM_DCT_DEV4_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV4_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC3_M  (I3C_MST_MEM_DCT_DEV4_LOC3_V << I3C_MST_MEM_DCT_DEV4_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV4_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE4_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE4_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x13c)
+/** I3C_MST_MEM_DCT_DEV4_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV4_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC4_M  (I3C_MST_MEM_DCT_DEV4_LOC4_V << I3C_MST_MEM_DCT_DEV4_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV4_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE5_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE5_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x140)
+/** I3C_MST_MEM_DCT_DEV5_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV5_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC1_M  (I3C_MST_MEM_DCT_DEV5_LOC1_V << I3C_MST_MEM_DCT_DEV5_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV5_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE5_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE5_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x144)
+/** I3C_MST_MEM_DCT_DEV5_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV5_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC2_M  (I3C_MST_MEM_DCT_DEV5_LOC2_V << I3C_MST_MEM_DCT_DEV5_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV5_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE5_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE5_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x148)
+/** I3C_MST_MEM_DCT_DEV5_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV5_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC3_M  (I3C_MST_MEM_DCT_DEV5_LOC3_V << I3C_MST_MEM_DCT_DEV5_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV5_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE5_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE5_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x14c)
+/** I3C_MST_MEM_DCT_DEV5_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV5_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC4_M  (I3C_MST_MEM_DCT_DEV5_LOC4_V << I3C_MST_MEM_DCT_DEV5_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV5_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE6_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE6_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x150)
+/** I3C_MST_MEM_DCT_DEV6_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV6_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC1_M  (I3C_MST_MEM_DCT_DEV6_LOC1_V << I3C_MST_MEM_DCT_DEV6_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV6_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE6_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE6_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x154)
+/** I3C_MST_MEM_DCT_DEV6_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV6_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC2_M  (I3C_MST_MEM_DCT_DEV6_LOC2_V << I3C_MST_MEM_DCT_DEV6_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV6_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE6_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE6_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x158)
+/** I3C_MST_MEM_DCT_DEV6_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV6_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC3_M  (I3C_MST_MEM_DCT_DEV6_LOC3_V << I3C_MST_MEM_DCT_DEV6_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV6_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE6_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE6_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x15c)
+/** I3C_MST_MEM_DCT_DEV6_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV6_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC4_M  (I3C_MST_MEM_DCT_DEV6_LOC4_V << I3C_MST_MEM_DCT_DEV6_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV6_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE7_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE7_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x160)
+/** I3C_MST_MEM_DCT_DEV7_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV7_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC1_M  (I3C_MST_MEM_DCT_DEV7_LOC1_V << I3C_MST_MEM_DCT_DEV7_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV7_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE7_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE7_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x164)
+/** I3C_MST_MEM_DCT_DEV7_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV7_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC2_M  (I3C_MST_MEM_DCT_DEV7_LOC2_V << I3C_MST_MEM_DCT_DEV7_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV7_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE7_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE7_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x168)
+/** I3C_MST_MEM_DCT_DEV7_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV7_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC3_M  (I3C_MST_MEM_DCT_DEV7_LOC3_V << I3C_MST_MEM_DCT_DEV7_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV7_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE7_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE7_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x16c)
+/** I3C_MST_MEM_DCT_DEV7_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV7_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC4_M  (I3C_MST_MEM_DCT_DEV7_LOC4_V << I3C_MST_MEM_DCT_DEV7_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV7_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE8_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE8_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x170)
+/** I3C_MST_MEM_DCT_DEV8_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV8_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC1_M  (I3C_MST_MEM_DCT_DEV8_LOC1_V << I3C_MST_MEM_DCT_DEV8_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV8_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE8_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE8_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x174)
+/** I3C_MST_MEM_DCT_DEV8_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV8_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC2_M  (I3C_MST_MEM_DCT_DEV8_LOC2_V << I3C_MST_MEM_DCT_DEV8_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV8_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE8_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE8_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x178)
+/** I3C_MST_MEM_DCT_DEV8_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV8_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC3_M  (I3C_MST_MEM_DCT_DEV8_LOC3_V << I3C_MST_MEM_DCT_DEV8_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV8_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE8_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE8_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x17c)
+/** I3C_MST_MEM_DCT_DEV8_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV8_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC4_M  (I3C_MST_MEM_DCT_DEV8_LOC4_V << I3C_MST_MEM_DCT_DEV8_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV8_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE9_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE9_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x180)
+/** I3C_MST_MEM_DCT_DEV9_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV9_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC1_M  (I3C_MST_MEM_DCT_DEV9_LOC1_V << I3C_MST_MEM_DCT_DEV9_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV9_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE9_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE9_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x184)
+/** I3C_MST_MEM_DCT_DEV9_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV9_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC2_M  (I3C_MST_MEM_DCT_DEV9_LOC2_V << I3C_MST_MEM_DCT_DEV9_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV9_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE9_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE9_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x188)
+/** I3C_MST_MEM_DCT_DEV9_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV9_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC3_M  (I3C_MST_MEM_DCT_DEV9_LOC3_V << I3C_MST_MEM_DCT_DEV9_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV9_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE9_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE9_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x18c)
+/** I3C_MST_MEM_DCT_DEV9_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV9_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC4_M  (I3C_MST_MEM_DCT_DEV9_LOC4_V << I3C_MST_MEM_DCT_DEV9_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV9_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE10_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE10_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x190)
+/** I3C_MST_MEM_DCT_DEV10_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV10_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC1_M  (I3C_MST_MEM_DCT_DEV10_LOC1_V << I3C_MST_MEM_DCT_DEV10_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV10_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE10_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE10_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x194)
+/** I3C_MST_MEM_DCT_DEV10_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV10_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC2_M  (I3C_MST_MEM_DCT_DEV10_LOC2_V << I3C_MST_MEM_DCT_DEV10_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV10_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE10_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE10_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x198)
+/** I3C_MST_MEM_DCT_DEV10_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV10_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC3_M  (I3C_MST_MEM_DCT_DEV10_LOC3_V << I3C_MST_MEM_DCT_DEV10_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV10_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE10_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE10_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x19c)
+/** I3C_MST_MEM_DCT_DEV10_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV10_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC4_M  (I3C_MST_MEM_DCT_DEV10_LOC4_V << I3C_MST_MEM_DCT_DEV10_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV10_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE11_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE11_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x1a0)
+/** I3C_MST_MEM_DCT_DEV11_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV11_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC1_M  (I3C_MST_MEM_DCT_DEV11_LOC1_V << I3C_MST_MEM_DCT_DEV11_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV11_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE11_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE11_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x1a4)
+/** I3C_MST_MEM_DCT_DEV11_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV11_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC2_M  (I3C_MST_MEM_DCT_DEV11_LOC2_V << I3C_MST_MEM_DCT_DEV11_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV11_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE11_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE11_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x1a8)
+/** I3C_MST_MEM_DCT_DEV11_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV11_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC3_M  (I3C_MST_MEM_DCT_DEV11_LOC3_V << I3C_MST_MEM_DCT_DEV11_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV11_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE11_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE11_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x1ac)
+/** I3C_MST_MEM_DCT_DEV11_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV11_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC4_M  (I3C_MST_MEM_DCT_DEV11_LOC4_V << I3C_MST_MEM_DCT_DEV11_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV11_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE12_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE12_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x1b0)
+/** I3C_MST_MEM_DCT_DEV12_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV12_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC1_M  (I3C_MST_MEM_DCT_DEV12_LOC1_V << I3C_MST_MEM_DCT_DEV12_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV12_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE12_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE12_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x1b4)
+/** I3C_MST_MEM_DCT_DEV12_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV12_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC2_M  (I3C_MST_MEM_DCT_DEV12_LOC2_V << I3C_MST_MEM_DCT_DEV12_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV12_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE12_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE12_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x1b8)
+/** I3C_MST_MEM_DCT_DEV12_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV12_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC3_M  (I3C_MST_MEM_DCT_DEV12_LOC3_V << I3C_MST_MEM_DCT_DEV12_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV12_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE12_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE12_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x1bc)
+/** I3C_MST_MEM_DCT_DEV12_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV12_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC4_M  (I3C_MST_MEM_DCT_DEV12_LOC4_V << I3C_MST_MEM_DCT_DEV12_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV12_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC4_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_mem_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_mem_struct.h
new file mode 100644
index 0000000000..1d2b2bf779
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_mem_struct.h
@@ -0,0 +1,196 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: I3C COMMAND BUF PORT REG */
+/** Type of command_buf_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_command : R/W; bitpos: [31:0]; default: 0;
+         *  Contains a Command Descriptor structure that depends on the requested transfer
+         *  type. Command Descriptor structure is used to schedule the transfers to devices on
+         *  I3C bus.
+         */
+        uint32_t reg_command:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_command_buf_port_reg_t;
+
+
+/** Group: I3C RESPONSE BUF PORT REG */
+/** Type of response_buf_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** response : RO; bitpos: [31:0]; default: 0;
+         *  The Response Buffer can be read through this register. The response status for each
+         *  Command is written into the Response Buffer by the controller if ROC (Response On
+         *  Completion) bit is set or if transfer error has occurred. The response buffer can
+         *  be read through this register.
+         */
+        uint32_t response:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_response_buf_port_reg_t;
+
+
+/** Group: I3C RX DATA PORT REG */
+/** Type of rx_data_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** rx_data_port : RO; bitpos: [31:0]; default: 0;
+         *  Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is
+         *  always packed in 4-byte aligned data words.  If the length of data transfer is not
+         *  aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional
+         *  data bytes have to be ignored) at the end of the transferred data. The valid data
+         *  must be identified using the DATA_LENGTH filed in the Response Descriptor.
+         */
+        uint32_t rx_data_port:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_rx_data_port_reg_t;
+
+
+/** Group: I3C TX DATA PORT REG */
+/** Type of tx_data_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tx_data_port : R/W; bitpos: [31:0]; default: 0;
+         *  Transmit Data Port. Transmit data is mapped to the Tx-data  buffer and transmit
+         *  data is always packed in 4-byte aligned data words.  If the length of data transfer
+         *  is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the
+         *  additional data bytes have to be ignored) at the end of the transferred data. The
+         *  valid data must be identified using the DATA_LENGTH filed in the Response
+         *  Descriptor.
+         */
+        uint32_t reg_tx_data_port:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_tx_data_port_reg_t;
+
+
+/** Group: I3C IBI STATUS BUF REG */
+/** Type of ibi_status_buf register
+ *  In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is
+ *  used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)
+ */
+typedef union {
+    struct {
+        /** data_length : RO; bitpos: [7:0]; default: 0;
+         *  This field represents the length of data received along with IBI, in bytes.
+         */
+        uint32_t data_length:8;
+        /** ibi_id : RO; bitpos: [15:8]; default: 0;
+         *  IBI Identifier. The byte received after START which includes the address the R/W
+         *  bit: Device  address and R/W bit in case of Slave Interrupt or Master Request.
+         */
+        uint32_t ibi_id:8;
+        uint32_t reserved_16:12;
+        /** ibi_sts : RO; bitpos: [28]; default: 0;
+         *  IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI
+         *  Data is always packed in4-byte aligned and put to the IBI Buffer. This register
+         *  When read from, reads the data from the IBI buffer. IBI Status register when read
+         *  from, returns the data from the IBI Buffer and indicates how the controller
+         *  responded to incoming IBI(SIR, MR and HJ).
+         */
+        uint32_t ibi_sts:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} i3c_mst_mem_ibi_status_buf_reg_t;
+
+
+/** Group: I3C IBI DATA BUF REG */
+/** Type of ibi_data_buf register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ibi_data : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_ibi_data_buf_reg_t;
+
+/** Group: I3C DEV ADDR TABLEn LOC REG */
+/** Type of dev_addr_tablen_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_devn_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_devn_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev12_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_devn_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev12_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_devn_nack_retry_cnt:2;
+        /** reg_dat_dev12_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_devn_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_tablen_loc_reg_t;
+
+typedef struct {
+    volatile uint32_t loc1;
+    volatile uint32_t loc2;
+    volatile uint32_t loc3;
+    volatile uint32_t loc4;
+} i3c_mst_mem_dev_char_tablen_reg_t;
+
+typedef struct {
+    uint32_t reserved_000[2];
+    volatile i3c_mst_mem_command_buf_port_reg_t command_buf_port;
+    volatile i3c_mst_mem_response_buf_port_reg_t response_buf_port;
+    volatile i3c_mst_mem_rx_data_port_reg_t rx_data_port;
+    volatile i3c_mst_mem_tx_data_port_reg_t tx_data_port;
+    volatile i3c_mst_mem_ibi_status_buf_reg_t ibi_status_buf;
+    uint32_t reserved_01c[9];
+    volatile i3c_mst_mem_ibi_data_buf_reg_t ibi_data_buf;
+    uint32_t reserved_044[31];
+    volatile i3c_mst_mem_dev_addr_tablen_loc_reg_t dev_addr_table[12];
+    uint32_t reserved_0f0[4];
+    volatile i3c_mst_mem_dev_char_tablen_reg_t dev_char_table[12];
+} i3c_mst_mem_dev_t;
+
+extern i3c_mst_mem_dev_t I3C_MST_MEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i3c_mst_mem_dev_t) == 0x1c0, "Invalid size of i3c_mst_mem_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_reg.h
new file mode 100644
index 0000000000..34cef41cee
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_reg.h
@@ -0,0 +1,1353 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I3C_MST_DEVICE_CTRL_REG register
+ *  DEVICE_CTRL register controls the transfer properties and disposition of
+ *  controllers capabilities.
+ */
+#define I3C_MST_DEVICE_CTRL_REG (DR_REG_I3C_MST_BASE + 0x0)
+/** I3C_MST_REG_BA_INCLUDE : R/W; bitpos: [1]; default: 0;
+ *  This bit is used to include I3C broadcast address(0x7E) for private transfer.(If
+ *  I3C broadcast address is not include for the private transfer, In-Band Interrupts
+ *  driven from Slaves may not win address arbitration. Hence IBIs will get delayed)
+ */
+#define I3C_MST_REG_BA_INCLUDE    (BIT(1))
+#define I3C_MST_REG_BA_INCLUDE_M  (I3C_MST_REG_BA_INCLUDE_V << I3C_MST_REG_BA_INCLUDE_S)
+#define I3C_MST_REG_BA_INCLUDE_V  0x00000001U
+#define I3C_MST_REG_BA_INCLUDE_S  1
+/** I3C_MST_REG_TRANS_START : R/W; bitpos: [2]; default: 0;
+ *  Transfer Start
+ */
+#define I3C_MST_REG_TRANS_START    (BIT(2))
+#define I3C_MST_REG_TRANS_START_M  (I3C_MST_REG_TRANS_START_V << I3C_MST_REG_TRANS_START_S)
+#define I3C_MST_REG_TRANS_START_V  0x00000001U
+#define I3C_MST_REG_TRANS_START_S  2
+/** I3C_MST_REG_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_CLK_EN    (BIT(3))
+#define I3C_MST_REG_CLK_EN_M  (I3C_MST_REG_CLK_EN_V << I3C_MST_REG_CLK_EN_S)
+#define I3C_MST_REG_CLK_EN_V  0x00000001U
+#define I3C_MST_REG_CLK_EN_S  3
+/** I3C_MST_REG_IBI_RSTART_TRANS_EN : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_RSTART_TRANS_EN    (BIT(4))
+#define I3C_MST_REG_IBI_RSTART_TRANS_EN_M  (I3C_MST_REG_IBI_RSTART_TRANS_EN_V << I3C_MST_REG_IBI_RSTART_TRANS_EN_S)
+#define I3C_MST_REG_IBI_RSTART_TRANS_EN_V  0x00000001U
+#define I3C_MST_REG_IBI_RSTART_TRANS_EN_S  4
+/** I3C_MST_REG_AUTO_DIS_IBI_EN : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define I3C_MST_REG_AUTO_DIS_IBI_EN    (BIT(5))
+#define I3C_MST_REG_AUTO_DIS_IBI_EN_M  (I3C_MST_REG_AUTO_DIS_IBI_EN_V << I3C_MST_REG_AUTO_DIS_IBI_EN_S)
+#define I3C_MST_REG_AUTO_DIS_IBI_EN_V  0x00000001U
+#define I3C_MST_REG_AUTO_DIS_IBI_EN_S  5
+/** I3C_MST_REG_DMA_RX_EN : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_DMA_RX_EN    (BIT(6))
+#define I3C_MST_REG_DMA_RX_EN_M  (I3C_MST_REG_DMA_RX_EN_V << I3C_MST_REG_DMA_RX_EN_S)
+#define I3C_MST_REG_DMA_RX_EN_V  0x00000001U
+#define I3C_MST_REG_DMA_RX_EN_S  6
+/** I3C_MST_REG_DMA_TX_EN : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_DMA_TX_EN    (BIT(7))
+#define I3C_MST_REG_DMA_TX_EN_M  (I3C_MST_REG_DMA_TX_EN_V << I3C_MST_REG_DMA_TX_EN_S)
+#define I3C_MST_REG_DMA_TX_EN_V  0x00000001U
+#define I3C_MST_REG_DMA_TX_EN_S  7
+/** I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN : R/W; bitpos: [8]; default: 0;
+ *  0: rx high bit first, 1: rx low bit first
+ */
+#define I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN    (BIT(8))
+#define I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN_M  (I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN_V << I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN_S)
+#define I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN_V  0x00000001U
+#define I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN_S  8
+/** I3C_MST_REG_RX_BIT_ORDER : R/W; bitpos: [9]; default: 0;
+ *  0: rx low byte fist, 1: rx high byte first
+ */
+#define I3C_MST_REG_RX_BIT_ORDER    (BIT(9))
+#define I3C_MST_REG_RX_BIT_ORDER_M  (I3C_MST_REG_RX_BIT_ORDER_V << I3C_MST_REG_RX_BIT_ORDER_S)
+#define I3C_MST_REG_RX_BIT_ORDER_V  0x00000001U
+#define I3C_MST_REG_RX_BIT_ORDER_S  9
+/** I3C_MST_REG_RX_BYTE_ORDER : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RX_BYTE_ORDER    (BIT(10))
+#define I3C_MST_REG_RX_BYTE_ORDER_M  (I3C_MST_REG_RX_BYTE_ORDER_V << I3C_MST_REG_RX_BYTE_ORDER_S)
+#define I3C_MST_REG_RX_BYTE_ORDER_V  0x00000001U
+#define I3C_MST_REG_RX_BYTE_ORDER_S  10
+/** I3C_MST_REG_SCL_PULLUP_FORCE_EN : R/W; bitpos: [11]; default: 0;
+ *  This bit is used to force scl_pullup_en
+ */
+#define I3C_MST_REG_SCL_PULLUP_FORCE_EN    (BIT(11))
+#define I3C_MST_REG_SCL_PULLUP_FORCE_EN_M  (I3C_MST_REG_SCL_PULLUP_FORCE_EN_V << I3C_MST_REG_SCL_PULLUP_FORCE_EN_S)
+#define I3C_MST_REG_SCL_PULLUP_FORCE_EN_V  0x00000001U
+#define I3C_MST_REG_SCL_PULLUP_FORCE_EN_S  11
+/** I3C_MST_REG_SCL_OE_FORCE_EN : R/W; bitpos: [12]; default: 1;
+ *  This bit is used to force scl_oe
+ */
+#define I3C_MST_REG_SCL_OE_FORCE_EN    (BIT(12))
+#define I3C_MST_REG_SCL_OE_FORCE_EN_M  (I3C_MST_REG_SCL_OE_FORCE_EN_V << I3C_MST_REG_SCL_OE_FORCE_EN_S)
+#define I3C_MST_REG_SCL_OE_FORCE_EN_V  0x00000001U
+#define I3C_MST_REG_SCL_OE_FORCE_EN_S  12
+/** I3C_MST_REG_SDA_PP_RD_PULLUP_EN : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_SDA_PP_RD_PULLUP_EN    (BIT(13))
+#define I3C_MST_REG_SDA_PP_RD_PULLUP_EN_M  (I3C_MST_REG_SDA_PP_RD_PULLUP_EN_V << I3C_MST_REG_SDA_PP_RD_PULLUP_EN_S)
+#define I3C_MST_REG_SDA_PP_RD_PULLUP_EN_V  0x00000001U
+#define I3C_MST_REG_SDA_PP_RD_PULLUP_EN_S  13
+/** I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN    (BIT(14))
+#define I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_M  (I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_V << I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_S)
+#define I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_V  0x00000001U
+#define I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_S  14
+/** I3C_MST_REG_SDA_PP_WR_PULLUP_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_SDA_PP_WR_PULLUP_EN    (BIT(15))
+#define I3C_MST_REG_SDA_PP_WR_PULLUP_EN_M  (I3C_MST_REG_SDA_PP_WR_PULLUP_EN_V << I3C_MST_REG_SDA_PP_WR_PULLUP_EN_S)
+#define I3C_MST_REG_SDA_PP_WR_PULLUP_EN_V  0x00000001U
+#define I3C_MST_REG_SDA_PP_WR_PULLUP_EN_S  15
+/** I3C_MST_REG_DATA_BYTE_CNT_UNLATCH : R/W; bitpos: [16]; default: 0;
+ *  1: read current real-time updated value  0: read latch data byte cnt value
+ */
+#define I3C_MST_REG_DATA_BYTE_CNT_UNLATCH    (BIT(16))
+#define I3C_MST_REG_DATA_BYTE_CNT_UNLATCH_M  (I3C_MST_REG_DATA_BYTE_CNT_UNLATCH_V << I3C_MST_REG_DATA_BYTE_CNT_UNLATCH_S)
+#define I3C_MST_REG_DATA_BYTE_CNT_UNLATCH_V  0x00000001U
+#define I3C_MST_REG_DATA_BYTE_CNT_UNLATCH_S  16
+/** I3C_MST_REG_MEM_CLK_FORCE_ON : R/W; bitpos: [17]; default: 0;
+ *  1: dev characteristic and address table memory clk  date force on . 0 :  clock
+ *  gating by rd/wr.
+ */
+#define I3C_MST_REG_MEM_CLK_FORCE_ON    (BIT(17))
+#define I3C_MST_REG_MEM_CLK_FORCE_ON_M  (I3C_MST_REG_MEM_CLK_FORCE_ON_V << I3C_MST_REG_MEM_CLK_FORCE_ON_S)
+#define I3C_MST_REG_MEM_CLK_FORCE_ON_V  0x00000001U
+#define I3C_MST_REG_MEM_CLK_FORCE_ON_S  17
+
+/** I3C_MST_BUFFER_THLD_CTRL_REG register
+ *  In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C
+ *  controller generates an IBI status. This field controls the number of IBI status
+ *  entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt.
+ */
+#define I3C_MST_BUFFER_THLD_CTRL_REG (DR_REG_I3C_MST_BASE + 0x1c)
+/** I3C_MST_REG_CMD_BUF_EMPTY_THLD : R/W; bitpos: [3:0]; default: 1;
+ *  Command Buffer Empty Threshold Value is used to control the number of empty
+ *  locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT
+ *  interrupt.
+ */
+#define I3C_MST_REG_CMD_BUF_EMPTY_THLD    0x0000000FU
+#define I3C_MST_REG_CMD_BUF_EMPTY_THLD_M  (I3C_MST_REG_CMD_BUF_EMPTY_THLD_V << I3C_MST_REG_CMD_BUF_EMPTY_THLD_S)
+#define I3C_MST_REG_CMD_BUF_EMPTY_THLD_V  0x0000000FU
+#define I3C_MST_REG_CMD_BUF_EMPTY_THLD_S  0
+/** I3C_MST_REG_RESP_BUF_THLD : R/W; bitpos: [8:6]; default: 1;
+ *  Response Buffer Threshold Value is used to control the number of entries in the
+ *  Response Buffer that trigger the RESP_READY_STAT_INTR.
+ */
+#define I3C_MST_REG_RESP_BUF_THLD    0x00000007U
+#define I3C_MST_REG_RESP_BUF_THLD_M  (I3C_MST_REG_RESP_BUF_THLD_V << I3C_MST_REG_RESP_BUF_THLD_S)
+#define I3C_MST_REG_RESP_BUF_THLD_V  0x00000007U
+#define I3C_MST_REG_RESP_BUF_THLD_S  6
+/** I3C_MST_REG_IBI_DATA_BUF_THLD : R/W; bitpos: [14:12]; default: 1;
+ *  In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C
+ *  controller generates an IBI status. This field controls the number of IBI data
+ *  entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt.
+ */
+#define I3C_MST_REG_IBI_DATA_BUF_THLD    0x00000007U
+#define I3C_MST_REG_IBI_DATA_BUF_THLD_M  (I3C_MST_REG_IBI_DATA_BUF_THLD_V << I3C_MST_REG_IBI_DATA_BUF_THLD_S)
+#define I3C_MST_REG_IBI_DATA_BUF_THLD_V  0x00000007U
+#define I3C_MST_REG_IBI_DATA_BUF_THLD_S  12
+/** I3C_MST_REG_IBI_STATUS_BUF_THLD : R/W; bitpos: [20:18]; default: 1;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_STATUS_BUF_THLD    0x00000007U
+#define I3C_MST_REG_IBI_STATUS_BUF_THLD_M  (I3C_MST_REG_IBI_STATUS_BUF_THLD_V << I3C_MST_REG_IBI_STATUS_BUF_THLD_S)
+#define I3C_MST_REG_IBI_STATUS_BUF_THLD_V  0x00000007U
+#define I3C_MST_REG_IBI_STATUS_BUF_THLD_S  18
+
+/** I3C_MST_DATA_BUFFER_THLD_CTRL_REG register
+ *  NA
+ */
+#define I3C_MST_DATA_BUFFER_THLD_CTRL_REG (DR_REG_I3C_MST_BASE + 0x20)
+/** I3C_MST_REG_TX_DATA_BUF_THLD : R/W; bitpos: [2:0]; default: 1;
+ *  Transmit Buffer Threshold Value. This field controls the number of empty locations
+ *  in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values:
+ *  000:2  001:4  010:8  011:16  100:31, else:31
+ */
+#define I3C_MST_REG_TX_DATA_BUF_THLD    0x00000007U
+#define I3C_MST_REG_TX_DATA_BUF_THLD_M  (I3C_MST_REG_TX_DATA_BUF_THLD_V << I3C_MST_REG_TX_DATA_BUF_THLD_S)
+#define I3C_MST_REG_TX_DATA_BUF_THLD_V  0x00000007U
+#define I3C_MST_REG_TX_DATA_BUF_THLD_S  0
+/** I3C_MST_REG_RX_DATA_BUF_THLD : R/W; bitpos: [5:3]; default: 1;
+ *  Receive Buffer Threshold Value. This field controls the number of empty locations
+ *  in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2  001:4
+ *  010:8  011:16  100:31, else:31
+ */
+#define I3C_MST_REG_RX_DATA_BUF_THLD    0x00000007U
+#define I3C_MST_REG_RX_DATA_BUF_THLD_M  (I3C_MST_REG_RX_DATA_BUF_THLD_V << I3C_MST_REG_RX_DATA_BUF_THLD_S)
+#define I3C_MST_REG_RX_DATA_BUF_THLD_V  0x00000007U
+#define I3C_MST_REG_RX_DATA_BUF_THLD_S  3
+
+/** I3C_MST_IBI_NOTIFY_CTRL_REG register
+ *  NA
+ */
+#define I3C_MST_IBI_NOTIFY_CTRL_REG (DR_REG_I3C_MST_BASE + 0x24)
+/** I3C_MST_REG_NOTIFY_SIR_REJECTED : R/W; bitpos: [2]; default: 0;
+ *  Notify Rejected Slave Interrupt Request Control. This bit is used to suppress
+ *  reporting to the application about Slave Interrupt Request. 0:Suppress passing the
+ *  IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request
+ *  is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI
+ *  Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed
+ *  and auto-disabled based on the IBI_SIR_REQ_REJECT registerl.
+ */
+#define I3C_MST_REG_NOTIFY_SIR_REJECTED    (BIT(2))
+#define I3C_MST_REG_NOTIFY_SIR_REJECTED_M  (I3C_MST_REG_NOTIFY_SIR_REJECTED_V << I3C_MST_REG_NOTIFY_SIR_REJECTED_S)
+#define I3C_MST_REG_NOTIFY_SIR_REJECTED_V  0x00000001U
+#define I3C_MST_REG_NOTIFY_SIR_REJECTED_S  2
+
+/** I3C_MST_IBI_SIR_REQ_PAYLOAD_REG register
+ *  NA
+ */
+#define I3C_MST_IBI_SIR_REQ_PAYLOAD_REG (DR_REG_I3C_MST_BASE + 0x28)
+/** I3C_MST_REG_SIR_REQ_PAYLOAD : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_SIR_REQ_PAYLOAD    0xFFFFFFFFU
+#define I3C_MST_REG_SIR_REQ_PAYLOAD_M  (I3C_MST_REG_SIR_REQ_PAYLOAD_V << I3C_MST_REG_SIR_REQ_PAYLOAD_S)
+#define I3C_MST_REG_SIR_REQ_PAYLOAD_V  0xFFFFFFFFU
+#define I3C_MST_REG_SIR_REQ_PAYLOAD_S  0
+
+/** I3C_MST_IBI_SIR_REQ_REJECT_REG register
+ *  NA
+ */
+#define I3C_MST_IBI_SIR_REQ_REJECT_REG (DR_REG_I3C_MST_BASE + 0x2c)
+/** I3C_MST_REG_SIR_REQ_REJECT : R/W; bitpos: [31:0]; default: 0;
+ *  The application of controller can decide whether to send ACK or NACK for Slave
+ *  request received from any I3C device. A device specific response control bit is
+ *  provided to select the response option, Master will ACK/NACK the Master Request
+ *  based on programming of control bit, corresponding to the interrupting device.
+ *  0:ACK the SIR Request  1:NACK and send direct auto disable CCC
+ */
+#define I3C_MST_REG_SIR_REQ_REJECT    0xFFFFFFFFU
+#define I3C_MST_REG_SIR_REQ_REJECT_M  (I3C_MST_REG_SIR_REQ_REJECT_V << I3C_MST_REG_SIR_REQ_REJECT_S)
+#define I3C_MST_REG_SIR_REQ_REJECT_V  0xFFFFFFFFU
+#define I3C_MST_REG_SIR_REQ_REJECT_S  0
+
+/** I3C_MST_INT_CLR_REG register
+ *  NA
+ */
+#define I3C_MST_INT_CLR_REG (DR_REG_I3C_MST_BASE + 0x30)
+/** I3C_MST_TX_DATA_BUF_THLD_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TX_DATA_BUF_THLD_INT_CLR    (BIT(0))
+#define I3C_MST_TX_DATA_BUF_THLD_INT_CLR_M  (I3C_MST_TX_DATA_BUF_THLD_INT_CLR_V << I3C_MST_TX_DATA_BUF_THLD_INT_CLR_S)
+#define I3C_MST_TX_DATA_BUF_THLD_INT_CLR_V  0x00000001U
+#define I3C_MST_TX_DATA_BUF_THLD_INT_CLR_S  0
+/** I3C_MST_RX_DATA_BUF_THLD_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RX_DATA_BUF_THLD_INT_CLR    (BIT(1))
+#define I3C_MST_RX_DATA_BUF_THLD_INT_CLR_M  (I3C_MST_RX_DATA_BUF_THLD_INT_CLR_V << I3C_MST_RX_DATA_BUF_THLD_INT_CLR_S)
+#define I3C_MST_RX_DATA_BUF_THLD_INT_CLR_V  0x00000001U
+#define I3C_MST_RX_DATA_BUF_THLD_INT_CLR_S  1
+/** I3C_MST_IBI_STATUS_THLD_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_THLD_INT_CLR    (BIT(2))
+#define I3C_MST_IBI_STATUS_THLD_INT_CLR_M  (I3C_MST_IBI_STATUS_THLD_INT_CLR_V << I3C_MST_IBI_STATUS_THLD_INT_CLR_S)
+#define I3C_MST_IBI_STATUS_THLD_INT_CLR_V  0x00000001U
+#define I3C_MST_IBI_STATUS_THLD_INT_CLR_S  2
+/** I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR    (BIT(3))
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR_M  (I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR_V << I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR_S)
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR_V  0x00000001U
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR_S  3
+/** I3C_MST_RESP_READY_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_READY_INT_CLR    (BIT(4))
+#define I3C_MST_RESP_READY_INT_CLR_M  (I3C_MST_RESP_READY_INT_CLR_V << I3C_MST_RESP_READY_INT_CLR_S)
+#define I3C_MST_RESP_READY_INT_CLR_V  0x00000001U
+#define I3C_MST_RESP_READY_INT_CLR_S  4
+/** I3C_MST_NXT_CMD_REQ_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_CLR    (BIT(5))
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_CLR_M  (I3C_MST_NXT_CMD_REQ_ERR_INT_CLR_V << I3C_MST_NXT_CMD_REQ_ERR_INT_CLR_S)
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_CLR_V  0x00000001U
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_CLR_S  5
+/** I3C_MST_TRANSFER_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_ERR_INT_CLR    (BIT(6))
+#define I3C_MST_TRANSFER_ERR_INT_CLR_M  (I3C_MST_TRANSFER_ERR_INT_CLR_V << I3C_MST_TRANSFER_ERR_INT_CLR_S)
+#define I3C_MST_TRANSFER_ERR_INT_CLR_V  0x00000001U
+#define I3C_MST_TRANSFER_ERR_INT_CLR_S  6
+/** I3C_MST_TRANSFER_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_COMPLETE_INT_CLR    (BIT(7))
+#define I3C_MST_TRANSFER_COMPLETE_INT_CLR_M  (I3C_MST_TRANSFER_COMPLETE_INT_CLR_V << I3C_MST_TRANSFER_COMPLETE_INT_CLR_S)
+#define I3C_MST_TRANSFER_COMPLETE_INT_CLR_V  0x00000001U
+#define I3C_MST_TRANSFER_COMPLETE_INT_CLR_S  7
+/** I3C_MST_COMMAND_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_COMMAND_DONE_INT_CLR    (BIT(8))
+#define I3C_MST_COMMAND_DONE_INT_CLR_M  (I3C_MST_COMMAND_DONE_INT_CLR_V << I3C_MST_COMMAND_DONE_INT_CLR_S)
+#define I3C_MST_COMMAND_DONE_INT_CLR_V  0x00000001U
+#define I3C_MST_COMMAND_DONE_INT_CLR_S  8
+/** I3C_MST_DETECT_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_DETECT_START_INT_CLR    (BIT(9))
+#define I3C_MST_DETECT_START_INT_CLR_M  (I3C_MST_DETECT_START_INT_CLR_V << I3C_MST_DETECT_START_INT_CLR_S)
+#define I3C_MST_DETECT_START_INT_CLR_V  0x00000001U
+#define I3C_MST_DETECT_START_INT_CLR_S  9
+/** I3C_MST_RESP_BUF_OVF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_BUF_OVF_INT_CLR    (BIT(10))
+#define I3C_MST_RESP_BUF_OVF_INT_CLR_M  (I3C_MST_RESP_BUF_OVF_INT_CLR_V << I3C_MST_RESP_BUF_OVF_INT_CLR_S)
+#define I3C_MST_RESP_BUF_OVF_INT_CLR_V  0x00000001U
+#define I3C_MST_RESP_BUF_OVF_INT_CLR_S  10
+/** I3C_MST_IBI_DATA_BUF_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_CLR    (BIT(11))
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_CLR_M  (I3C_MST_IBI_DATA_BUF_OVF_INT_CLR_V << I3C_MST_IBI_DATA_BUF_OVF_INT_CLR_S)
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_CLR_V  0x00000001U
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_CLR_S  11
+/** I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR    (BIT(12))
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR_M  (I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR_V << I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR_S)
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR_V  0x00000001U
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR_S  12
+/** I3C_MST_IBI_HANDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_HANDLE_DONE_INT_CLR    (BIT(13))
+#define I3C_MST_IBI_HANDLE_DONE_INT_CLR_M  (I3C_MST_IBI_HANDLE_DONE_INT_CLR_V << I3C_MST_IBI_HANDLE_DONE_INT_CLR_S)
+#define I3C_MST_IBI_HANDLE_DONE_INT_CLR_V  0x00000001U
+#define I3C_MST_IBI_HANDLE_DONE_INT_CLR_S  13
+/** I3C_MST_IBI_DETECT_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DETECT_INT_CLR    (BIT(14))
+#define I3C_MST_IBI_DETECT_INT_CLR_M  (I3C_MST_IBI_DETECT_INT_CLR_V << I3C_MST_IBI_DETECT_INT_CLR_S)
+#define I3C_MST_IBI_DETECT_INT_CLR_V  0x00000001U
+#define I3C_MST_IBI_DETECT_INT_CLR_S  14
+/** I3C_MST_CMD_CCC_MISMATCH_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_CCC_MISMATCH_INT_CLR    (BIT(15))
+#define I3C_MST_CMD_CCC_MISMATCH_INT_CLR_M  (I3C_MST_CMD_CCC_MISMATCH_INT_CLR_V << I3C_MST_CMD_CCC_MISMATCH_INT_CLR_S)
+#define I3C_MST_CMD_CCC_MISMATCH_INT_CLR_V  0x00000001U
+#define I3C_MST_CMD_CCC_MISMATCH_INT_CLR_S  15
+
+/** I3C_MST_INT_RAW_REG register
+ *  NA
+ */
+#define I3C_MST_INT_RAW_REG (DR_REG_I3C_MST_BASE + 0x34)
+/** I3C_MST_TX_DATA_BUF_THLD_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TX_DATA_BUF_THLD_INT_RAW    (BIT(0))
+#define I3C_MST_TX_DATA_BUF_THLD_INT_RAW_M  (I3C_MST_TX_DATA_BUF_THLD_INT_RAW_V << I3C_MST_TX_DATA_BUF_THLD_INT_RAW_S)
+#define I3C_MST_TX_DATA_BUF_THLD_INT_RAW_V  0x00000001U
+#define I3C_MST_TX_DATA_BUF_THLD_INT_RAW_S  0
+/** I3C_MST_RX_DATA_BUF_THLD_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RX_DATA_BUF_THLD_INT_RAW    (BIT(1))
+#define I3C_MST_RX_DATA_BUF_THLD_INT_RAW_M  (I3C_MST_RX_DATA_BUF_THLD_INT_RAW_V << I3C_MST_RX_DATA_BUF_THLD_INT_RAW_S)
+#define I3C_MST_RX_DATA_BUF_THLD_INT_RAW_V  0x00000001U
+#define I3C_MST_RX_DATA_BUF_THLD_INT_RAW_S  1
+/** I3C_MST_IBI_STATUS_THLD_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_THLD_INT_RAW    (BIT(2))
+#define I3C_MST_IBI_STATUS_THLD_INT_RAW_M  (I3C_MST_IBI_STATUS_THLD_INT_RAW_V << I3C_MST_IBI_STATUS_THLD_INT_RAW_S)
+#define I3C_MST_IBI_STATUS_THLD_INT_RAW_V  0x00000001U
+#define I3C_MST_IBI_STATUS_THLD_INT_RAW_S  2
+/** I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW    (BIT(3))
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW_M  (I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW_V << I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW_S)
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW_V  0x00000001U
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW_S  3
+/** I3C_MST_RESP_READY_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_READY_INT_RAW    (BIT(4))
+#define I3C_MST_RESP_READY_INT_RAW_M  (I3C_MST_RESP_READY_INT_RAW_V << I3C_MST_RESP_READY_INT_RAW_S)
+#define I3C_MST_RESP_READY_INT_RAW_V  0x00000001U
+#define I3C_MST_RESP_READY_INT_RAW_S  4
+/** I3C_MST_NXT_CMD_REQ_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_RAW    (BIT(5))
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_RAW_M  (I3C_MST_NXT_CMD_REQ_ERR_INT_RAW_V << I3C_MST_NXT_CMD_REQ_ERR_INT_RAW_S)
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_RAW_V  0x00000001U
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_RAW_S  5
+/** I3C_MST_TRANSFER_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_ERR_INT_RAW    (BIT(6))
+#define I3C_MST_TRANSFER_ERR_INT_RAW_M  (I3C_MST_TRANSFER_ERR_INT_RAW_V << I3C_MST_TRANSFER_ERR_INT_RAW_S)
+#define I3C_MST_TRANSFER_ERR_INT_RAW_V  0x00000001U
+#define I3C_MST_TRANSFER_ERR_INT_RAW_S  6
+/** I3C_MST_TRANSFER_COMPLETE_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_COMPLETE_INT_RAW    (BIT(7))
+#define I3C_MST_TRANSFER_COMPLETE_INT_RAW_M  (I3C_MST_TRANSFER_COMPLETE_INT_RAW_V << I3C_MST_TRANSFER_COMPLETE_INT_RAW_S)
+#define I3C_MST_TRANSFER_COMPLETE_INT_RAW_V  0x00000001U
+#define I3C_MST_TRANSFER_COMPLETE_INT_RAW_S  7
+/** I3C_MST_COMMAND_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_COMMAND_DONE_INT_RAW    (BIT(8))
+#define I3C_MST_COMMAND_DONE_INT_RAW_M  (I3C_MST_COMMAND_DONE_INT_RAW_V << I3C_MST_COMMAND_DONE_INT_RAW_S)
+#define I3C_MST_COMMAND_DONE_INT_RAW_V  0x00000001U
+#define I3C_MST_COMMAND_DONE_INT_RAW_S  8
+/** I3C_MST_DETECT_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_DETECT_START_INT_RAW    (BIT(9))
+#define I3C_MST_DETECT_START_INT_RAW_M  (I3C_MST_DETECT_START_INT_RAW_V << I3C_MST_DETECT_START_INT_RAW_S)
+#define I3C_MST_DETECT_START_INT_RAW_V  0x00000001U
+#define I3C_MST_DETECT_START_INT_RAW_S  9
+/** I3C_MST_RESP_BUF_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_BUF_OVF_INT_RAW    (BIT(10))
+#define I3C_MST_RESP_BUF_OVF_INT_RAW_M  (I3C_MST_RESP_BUF_OVF_INT_RAW_V << I3C_MST_RESP_BUF_OVF_INT_RAW_S)
+#define I3C_MST_RESP_BUF_OVF_INT_RAW_V  0x00000001U
+#define I3C_MST_RESP_BUF_OVF_INT_RAW_S  10
+/** I3C_MST_IBI_DATA_BUF_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_RAW    (BIT(11))
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_RAW_M  (I3C_MST_IBI_DATA_BUF_OVF_INT_RAW_V << I3C_MST_IBI_DATA_BUF_OVF_INT_RAW_S)
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_RAW_V  0x00000001U
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_RAW_S  11
+/** I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW    (BIT(12))
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW_M  (I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW_V << I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW_S)
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW_V  0x00000001U
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW_S  12
+/** I3C_MST_IBI_HANDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_HANDLE_DONE_INT_RAW    (BIT(13))
+#define I3C_MST_IBI_HANDLE_DONE_INT_RAW_M  (I3C_MST_IBI_HANDLE_DONE_INT_RAW_V << I3C_MST_IBI_HANDLE_DONE_INT_RAW_S)
+#define I3C_MST_IBI_HANDLE_DONE_INT_RAW_V  0x00000001U
+#define I3C_MST_IBI_HANDLE_DONE_INT_RAW_S  13
+/** I3C_MST_IBI_DETECT_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DETECT_INT_RAW    (BIT(14))
+#define I3C_MST_IBI_DETECT_INT_RAW_M  (I3C_MST_IBI_DETECT_INT_RAW_V << I3C_MST_IBI_DETECT_INT_RAW_S)
+#define I3C_MST_IBI_DETECT_INT_RAW_V  0x00000001U
+#define I3C_MST_IBI_DETECT_INT_RAW_S  14
+/** I3C_MST_CMD_CCC_MISMATCH_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_CCC_MISMATCH_INT_RAW    (BIT(15))
+#define I3C_MST_CMD_CCC_MISMATCH_INT_RAW_M  (I3C_MST_CMD_CCC_MISMATCH_INT_RAW_V << I3C_MST_CMD_CCC_MISMATCH_INT_RAW_S)
+#define I3C_MST_CMD_CCC_MISMATCH_INT_RAW_V  0x00000001U
+#define I3C_MST_CMD_CCC_MISMATCH_INT_RAW_S  15
+
+/** I3C_MST_INT_ST_REG register
+ *  NA
+ */
+#define I3C_MST_INT_ST_REG (DR_REG_I3C_MST_BASE + 0x38)
+/** I3C_MST_TX_DATA_BUF_THLD_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This interrupt is generated when number of empty locations in transmit buffer is
+ *  greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in
+ *  DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+ *  number of empty locations in transmit buffer is less than threshold value.
+ */
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ST    (BIT(0))
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ST_M  (I3C_MST_TX_DATA_BUF_THLD_INT_ST_V << I3C_MST_TX_DATA_BUF_THLD_INT_ST_S)
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ST_V  0x00000001U
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ST_S  0
+/** I3C_MST_RX_DATA_BUF_THLD_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This interrupt is generated when number of entries in receive buffer is greater
+ *  than or equal to threshold value specified by RX_BUF_THLD field in
+ *  DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+ *  number of entries in receive buffer is less than threshold value.
+ */
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ST    (BIT(1))
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ST_M  (I3C_MST_RX_DATA_BUF_THLD_INT_ST_V << I3C_MST_RX_DATA_BUF_THLD_INT_ST_S)
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ST_V  0x00000001U
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ST_S  1
+/** I3C_MST_IBI_STATUS_THLD_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Only used in master mode. This interrupt is generated when number of entries in IBI
+ *  buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field
+ *  in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+ *  number of entries in IBI buffer is less than threshold value.
+ */
+#define I3C_MST_IBI_STATUS_THLD_INT_ST    (BIT(2))
+#define I3C_MST_IBI_STATUS_THLD_INT_ST_M  (I3C_MST_IBI_STATUS_THLD_INT_ST_V << I3C_MST_IBI_STATUS_THLD_INT_ST_S)
+#define I3C_MST_IBI_STATUS_THLD_INT_ST_V  0x00000001U
+#define I3C_MST_IBI_STATUS_THLD_INT_ST_S  2
+/** I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This interrupt is generated when number of empty locations in command buffer is
+ *  greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in
+ *  BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number
+ *  of empty locations in command buffer is less than threshold value.
+ */
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST    (BIT(3))
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST_M  (I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST_V << I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST_S)
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST_V  0x00000001U
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST_S  3
+/** I3C_MST_RESP_READY_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This interrupt is generated when number of entries in response buffer is greater
+ *  than or equal to threshold value specified by RESP_BUF_THLD field in
+ *  BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number
+ *  of entries in response buffer is less than threshold value.
+ */
+#define I3C_MST_RESP_READY_INT_ST    (BIT(4))
+#define I3C_MST_RESP_READY_INT_ST_M  (I3C_MST_RESP_READY_INT_ST_V << I3C_MST_RESP_READY_INT_ST_S)
+#define I3C_MST_RESP_READY_INT_ST_V  0x00000001U
+#define I3C_MST_RESP_READY_INT_ST_S  4
+/** I3C_MST_NXT_CMD_REQ_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This interrupt is generated if toc is 0(master will restart next command), but
+ *  command buf is empty.
+ */
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ST    (BIT(5))
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ST_M  (I3C_MST_NXT_CMD_REQ_ERR_INT_ST_V << I3C_MST_NXT_CMD_REQ_ERR_INT_ST_S)
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ST_V  0x00000001U
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ST_S  5
+/** I3C_MST_TRANSFER_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This interrupt is generated if any error occurs during transfer. The error type
+ *  will be specified in the response packet associated with the command (in ERR_STATUS
+ *  field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1.
+ */
+#define I3C_MST_TRANSFER_ERR_INT_ST    (BIT(6))
+#define I3C_MST_TRANSFER_ERR_INT_ST_M  (I3C_MST_TRANSFER_ERR_INT_ST_V << I3C_MST_TRANSFER_ERR_INT_ST_S)
+#define I3C_MST_TRANSFER_ERR_INT_ST_V  0x00000001U
+#define I3C_MST_TRANSFER_ERR_INT_ST_S  6
+/** I3C_MST_TRANSFER_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_COMPLETE_INT_ST    (BIT(7))
+#define I3C_MST_TRANSFER_COMPLETE_INT_ST_M  (I3C_MST_TRANSFER_COMPLETE_INT_ST_V << I3C_MST_TRANSFER_COMPLETE_INT_ST_S)
+#define I3C_MST_TRANSFER_COMPLETE_INT_ST_V  0x00000001U
+#define I3C_MST_TRANSFER_COMPLETE_INT_ST_S  7
+/** I3C_MST_COMMAND_DONE_INT_ST : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_COMMAND_DONE_INT_ST    (BIT(8))
+#define I3C_MST_COMMAND_DONE_INT_ST_M  (I3C_MST_COMMAND_DONE_INT_ST_V << I3C_MST_COMMAND_DONE_INT_ST_S)
+#define I3C_MST_COMMAND_DONE_INT_ST_V  0x00000001U
+#define I3C_MST_COMMAND_DONE_INT_ST_S  8
+/** I3C_MST_DETECT_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_DETECT_START_INT_ST    (BIT(9))
+#define I3C_MST_DETECT_START_INT_ST_M  (I3C_MST_DETECT_START_INT_ST_V << I3C_MST_DETECT_START_INT_ST_S)
+#define I3C_MST_DETECT_START_INT_ST_V  0x00000001U
+#define I3C_MST_DETECT_START_INT_ST_S  9
+/** I3C_MST_RESP_BUF_OVF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_BUF_OVF_INT_ST    (BIT(10))
+#define I3C_MST_RESP_BUF_OVF_INT_ST_M  (I3C_MST_RESP_BUF_OVF_INT_ST_V << I3C_MST_RESP_BUF_OVF_INT_ST_S)
+#define I3C_MST_RESP_BUF_OVF_INT_ST_V  0x00000001U
+#define I3C_MST_RESP_BUF_OVF_INT_ST_S  10
+/** I3C_MST_IBI_DATA_BUF_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ST    (BIT(11))
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ST_M  (I3C_MST_IBI_DATA_BUF_OVF_INT_ST_V << I3C_MST_IBI_DATA_BUF_OVF_INT_ST_S)
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ST_V  0x00000001U
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ST_S  11
+/** I3C_MST_IBI_STATUS_BUF_OVF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ST    (BIT(12))
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ST_M  (I3C_MST_IBI_STATUS_BUF_OVF_INT_ST_V << I3C_MST_IBI_STATUS_BUF_OVF_INT_ST_S)
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ST_V  0x00000001U
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ST_S  12
+/** I3C_MST_IBI_HANDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_HANDLE_DONE_INT_ST    (BIT(13))
+#define I3C_MST_IBI_HANDLE_DONE_INT_ST_M  (I3C_MST_IBI_HANDLE_DONE_INT_ST_V << I3C_MST_IBI_HANDLE_DONE_INT_ST_S)
+#define I3C_MST_IBI_HANDLE_DONE_INT_ST_V  0x00000001U
+#define I3C_MST_IBI_HANDLE_DONE_INT_ST_S  13
+/** I3C_MST_IBI_DETECT_INT_ST : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DETECT_INT_ST    (BIT(14))
+#define I3C_MST_IBI_DETECT_INT_ST_M  (I3C_MST_IBI_DETECT_INT_ST_V << I3C_MST_IBI_DETECT_INT_ST_S)
+#define I3C_MST_IBI_DETECT_INT_ST_V  0x00000001U
+#define I3C_MST_IBI_DETECT_INT_ST_S  14
+/** I3C_MST_CMD_CCC_MISMATCH_INT_ST : RO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ST    (BIT(15))
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ST_M  (I3C_MST_CMD_CCC_MISMATCH_INT_ST_V << I3C_MST_CMD_CCC_MISMATCH_INT_ST_S)
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ST_V  0x00000001U
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ST_S  15
+
+/** I3C_MST_INT_ST_ENA_REG register
+ *  The Interrupt status will be updated in INTR_STATUS register if corresponding
+ *  Status Enable bit set.
+ */
+#define I3C_MST_INT_ST_ENA_REG (DR_REG_I3C_MST_BASE + 0x3c)
+/** I3C_MST_TX_DATA_BUF_THLD_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Transmit Buffer threshold status enable.
+ */
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ENA    (BIT(0))
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ENA_M  (I3C_MST_TX_DATA_BUF_THLD_INT_ENA_V << I3C_MST_TX_DATA_BUF_THLD_INT_ENA_S)
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ENA_V  0x00000001U
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ENA_S  0
+/** I3C_MST_RX_DATA_BUF_THLD_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Receive Buffer threshold status enable.
+ */
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ENA    (BIT(1))
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ENA_M  (I3C_MST_RX_DATA_BUF_THLD_INT_ENA_V << I3C_MST_RX_DATA_BUF_THLD_INT_ENA_S)
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ENA_V  0x00000001U
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ENA_S  1
+/** I3C_MST_IBI_STATUS_THLD_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Only used in master mode. IBI Buffer threshold status enable.
+ */
+#define I3C_MST_IBI_STATUS_THLD_INT_ENA    (BIT(2))
+#define I3C_MST_IBI_STATUS_THLD_INT_ENA_M  (I3C_MST_IBI_STATUS_THLD_INT_ENA_V << I3C_MST_IBI_STATUS_THLD_INT_ENA_S)
+#define I3C_MST_IBI_STATUS_THLD_INT_ENA_V  0x00000001U
+#define I3C_MST_IBI_STATUS_THLD_INT_ENA_S  2
+/** I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Command buffer ready status enable.
+ */
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA    (BIT(3))
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA_M  (I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA_V << I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA_S)
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA_V  0x00000001U
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA_S  3
+/** I3C_MST_RESP_READY_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Response buffer ready status enable.
+ */
+#define I3C_MST_RESP_READY_INT_ENA    (BIT(4))
+#define I3C_MST_RESP_READY_INT_ENA_M  (I3C_MST_RESP_READY_INT_ENA_V << I3C_MST_RESP_READY_INT_ENA_S)
+#define I3C_MST_RESP_READY_INT_ENA_V  0x00000001U
+#define I3C_MST_RESP_READY_INT_ENA_S  4
+/** I3C_MST_NXT_CMD_REQ_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  next command request error status enable
+ */
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ENA    (BIT(5))
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ENA_M  (I3C_MST_NXT_CMD_REQ_ERR_INT_ENA_V << I3C_MST_NXT_CMD_REQ_ERR_INT_ENA_S)
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ENA_V  0x00000001U
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ENA_S  5
+/** I3C_MST_TRANSFER_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Transfer error status enable
+ */
+#define I3C_MST_TRANSFER_ERR_INT_ENA    (BIT(6))
+#define I3C_MST_TRANSFER_ERR_INT_ENA_M  (I3C_MST_TRANSFER_ERR_INT_ENA_V << I3C_MST_TRANSFER_ERR_INT_ENA_S)
+#define I3C_MST_TRANSFER_ERR_INT_ENA_V  0x00000001U
+#define I3C_MST_TRANSFER_ERR_INT_ENA_S  6
+/** I3C_MST_TRANSFER_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_COMPLETE_INT_ENA    (BIT(7))
+#define I3C_MST_TRANSFER_COMPLETE_INT_ENA_M  (I3C_MST_TRANSFER_COMPLETE_INT_ENA_V << I3C_MST_TRANSFER_COMPLETE_INT_ENA_S)
+#define I3C_MST_TRANSFER_COMPLETE_INT_ENA_V  0x00000001U
+#define I3C_MST_TRANSFER_COMPLETE_INT_ENA_S  7
+/** I3C_MST_COMMAND_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_COMMAND_DONE_INT_ENA    (BIT(8))
+#define I3C_MST_COMMAND_DONE_INT_ENA_M  (I3C_MST_COMMAND_DONE_INT_ENA_V << I3C_MST_COMMAND_DONE_INT_ENA_S)
+#define I3C_MST_COMMAND_DONE_INT_ENA_V  0x00000001U
+#define I3C_MST_COMMAND_DONE_INT_ENA_S  8
+/** I3C_MST_DETECT_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_DETECT_START_INT_ENA    (BIT(9))
+#define I3C_MST_DETECT_START_INT_ENA_M  (I3C_MST_DETECT_START_INT_ENA_V << I3C_MST_DETECT_START_INT_ENA_S)
+#define I3C_MST_DETECT_START_INT_ENA_V  0x00000001U
+#define I3C_MST_DETECT_START_INT_ENA_S  9
+/** I3C_MST_RESP_BUF_OVF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_BUF_OVF_INT_ENA    (BIT(10))
+#define I3C_MST_RESP_BUF_OVF_INT_ENA_M  (I3C_MST_RESP_BUF_OVF_INT_ENA_V << I3C_MST_RESP_BUF_OVF_INT_ENA_S)
+#define I3C_MST_RESP_BUF_OVF_INT_ENA_V  0x00000001U
+#define I3C_MST_RESP_BUF_OVF_INT_ENA_S  10
+/** I3C_MST_IBI_DATA_BUF_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ENA    (BIT(11))
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ENA_M  (I3C_MST_IBI_DATA_BUF_OVF_INT_ENA_V << I3C_MST_IBI_DATA_BUF_OVF_INT_ENA_S)
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ENA_V  0x00000001U
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ENA_S  11
+/** I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA    (BIT(12))
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA_M  (I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA_V << I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA_S)
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA_V  0x00000001U
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA_S  12
+/** I3C_MST_IBI_HANDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_HANDLE_DONE_INT_ENA    (BIT(13))
+#define I3C_MST_IBI_HANDLE_DONE_INT_ENA_M  (I3C_MST_IBI_HANDLE_DONE_INT_ENA_V << I3C_MST_IBI_HANDLE_DONE_INT_ENA_S)
+#define I3C_MST_IBI_HANDLE_DONE_INT_ENA_V  0x00000001U
+#define I3C_MST_IBI_HANDLE_DONE_INT_ENA_S  13
+/** I3C_MST_IBI_DETECT_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DETECT_INT_ENA    (BIT(14))
+#define I3C_MST_IBI_DETECT_INT_ENA_M  (I3C_MST_IBI_DETECT_INT_ENA_V << I3C_MST_IBI_DETECT_INT_ENA_S)
+#define I3C_MST_IBI_DETECT_INT_ENA_V  0x00000001U
+#define I3C_MST_IBI_DETECT_INT_ENA_S  14
+/** I3C_MST_CMD_CCC_MISMATCH_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ENA    (BIT(15))
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ENA_M  (I3C_MST_CMD_CCC_MISMATCH_INT_ENA_V << I3C_MST_CMD_CCC_MISMATCH_INT_ENA_S)
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ENA_V  0x00000001U
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ENA_S  15
+
+/** I3C_MST_RESET_CTRL_REG register
+ *  NA
+ */
+#define I3C_MST_RESET_CTRL_REG (DR_REG_I3C_MST_BASE + 0x44)
+/** I3C_MST_REG_CORE_SOFT_RST : WT; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_CORE_SOFT_RST    (BIT(0))
+#define I3C_MST_REG_CORE_SOFT_RST_M  (I3C_MST_REG_CORE_SOFT_RST_V << I3C_MST_REG_CORE_SOFT_RST_S)
+#define I3C_MST_REG_CORE_SOFT_RST_V  0x00000001U
+#define I3C_MST_REG_CORE_SOFT_RST_S  0
+/** I3C_MST_REG_CMD_BUF_RST : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_CMD_BUF_RST    (BIT(1))
+#define I3C_MST_REG_CMD_BUF_RST_M  (I3C_MST_REG_CMD_BUF_RST_V << I3C_MST_REG_CMD_BUF_RST_S)
+#define I3C_MST_REG_CMD_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_CMD_BUF_RST_S  1
+/** I3C_MST_REG_RESP_BUF_RST : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RESP_BUF_RST    (BIT(2))
+#define I3C_MST_REG_RESP_BUF_RST_M  (I3C_MST_REG_RESP_BUF_RST_V << I3C_MST_REG_RESP_BUF_RST_S)
+#define I3C_MST_REG_RESP_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_RESP_BUF_RST_S  2
+/** I3C_MST_REG_TX_DATA_BUF_BUF_RST : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_TX_DATA_BUF_BUF_RST    (BIT(3))
+#define I3C_MST_REG_TX_DATA_BUF_BUF_RST_M  (I3C_MST_REG_TX_DATA_BUF_BUF_RST_V << I3C_MST_REG_TX_DATA_BUF_BUF_RST_S)
+#define I3C_MST_REG_TX_DATA_BUF_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_TX_DATA_BUF_BUF_RST_S  3
+/** I3C_MST_REG_RX_DATA_BUF_RST : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RX_DATA_BUF_RST    (BIT(4))
+#define I3C_MST_REG_RX_DATA_BUF_RST_M  (I3C_MST_REG_RX_DATA_BUF_RST_V << I3C_MST_REG_RX_DATA_BUF_RST_S)
+#define I3C_MST_REG_RX_DATA_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_RX_DATA_BUF_RST_S  4
+/** I3C_MST_REG_IBI_DATA_BUF_RST : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_DATA_BUF_RST    (BIT(5))
+#define I3C_MST_REG_IBI_DATA_BUF_RST_M  (I3C_MST_REG_IBI_DATA_BUF_RST_V << I3C_MST_REG_IBI_DATA_BUF_RST_S)
+#define I3C_MST_REG_IBI_DATA_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_IBI_DATA_BUF_RST_S  5
+/** I3C_MST_REG_IBI_STATUS_BUF_RST : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_STATUS_BUF_RST    (BIT(6))
+#define I3C_MST_REG_IBI_STATUS_BUF_RST_M  (I3C_MST_REG_IBI_STATUS_BUF_RST_V << I3C_MST_REG_IBI_STATUS_BUF_RST_S)
+#define I3C_MST_REG_IBI_STATUS_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_IBI_STATUS_BUF_RST_S  6
+
+/** I3C_MST_BUFFER_STATUS_LEVEL_REG register
+ *  BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.
+ */
+#define I3C_MST_BUFFER_STATUS_LEVEL_REG (DR_REG_I3C_MST_BASE + 0x48)
+/** I3C_MST_CMD_BUF_EMPTY_CNT : RO; bitpos: [4:0]; default: 16;
+ *  Command Buffer Empty Locations contains the number of empty locations in the
+ *  command buffer.
+ */
+#define I3C_MST_CMD_BUF_EMPTY_CNT    0x0000001FU
+#define I3C_MST_CMD_BUF_EMPTY_CNT_M  (I3C_MST_CMD_BUF_EMPTY_CNT_V << I3C_MST_CMD_BUF_EMPTY_CNT_S)
+#define I3C_MST_CMD_BUF_EMPTY_CNT_V  0x0000001FU
+#define I3C_MST_CMD_BUF_EMPTY_CNT_S  0
+/** I3C_MST_RESP_BUF_CNT : RO; bitpos: [11:8]; default: 0;
+ *  Response Buffer Level Value contains the number of valid data entries in the
+ *  response buffer.
+ */
+#define I3C_MST_RESP_BUF_CNT    0x0000000FU
+#define I3C_MST_RESP_BUF_CNT_M  (I3C_MST_RESP_BUF_CNT_V << I3C_MST_RESP_BUF_CNT_S)
+#define I3C_MST_RESP_BUF_CNT_V  0x0000000FU
+#define I3C_MST_RESP_BUF_CNT_S  8
+/** I3C_MST_IBI_DATA_BUF_CNT : RO; bitpos: [19:16]; default: 0;
+ *  IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This
+ *  is field is used in master mode.
+ */
+#define I3C_MST_IBI_DATA_BUF_CNT    0x0000000FU
+#define I3C_MST_IBI_DATA_BUF_CNT_M  (I3C_MST_IBI_DATA_BUF_CNT_V << I3C_MST_IBI_DATA_BUF_CNT_S)
+#define I3C_MST_IBI_DATA_BUF_CNT_V  0x0000000FU
+#define I3C_MST_IBI_DATA_BUF_CNT_S  16
+/** I3C_MST_IBI_STATUS_BUF_CNT : RO; bitpos: [27:24]; default: 0;
+ *  IBI Buffer Status Count contains the number of IBI status entries in the IBI
+ *  Buffer. This field is used in master mode.
+ */
+#define I3C_MST_IBI_STATUS_BUF_CNT    0x0000000FU
+#define I3C_MST_IBI_STATUS_BUF_CNT_M  (I3C_MST_IBI_STATUS_BUF_CNT_V << I3C_MST_IBI_STATUS_BUF_CNT_S)
+#define I3C_MST_IBI_STATUS_BUF_CNT_V  0x0000000FU
+#define I3C_MST_IBI_STATUS_BUF_CNT_S  24
+
+/** I3C_MST_DATA_BUFFER_STATUS_LEVEL_REG register
+ *  DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.
+ */
+#define I3C_MST_DATA_BUFFER_STATUS_LEVEL_REG (DR_REG_I3C_MST_BASE + 0x4c)
+/** I3C_MST_TX_DATA_BUF_EMPTY_CNT : RO; bitpos: [5:0]; default: 32;
+ *  Transmit Buffer Empty Level Value contains the number of empty locations in the
+ *  transmit Buffer.
+ */
+#define I3C_MST_TX_DATA_BUF_EMPTY_CNT    0x0000003FU
+#define I3C_MST_TX_DATA_BUF_EMPTY_CNT_M  (I3C_MST_TX_DATA_BUF_EMPTY_CNT_V << I3C_MST_TX_DATA_BUF_EMPTY_CNT_S)
+#define I3C_MST_TX_DATA_BUF_EMPTY_CNT_V  0x0000003FU
+#define I3C_MST_TX_DATA_BUF_EMPTY_CNT_S  0
+/** I3C_MST_RX_DATA_BUF_CNT : RO; bitpos: [21:16]; default: 0;
+ *  Receive Buffer Level value contains the number of valid data entries in the receive
+ *  buffer.
+ */
+#define I3C_MST_RX_DATA_BUF_CNT    0x0000003FU
+#define I3C_MST_RX_DATA_BUF_CNT_M  (I3C_MST_RX_DATA_BUF_CNT_V << I3C_MST_RX_DATA_BUF_CNT_S)
+#define I3C_MST_RX_DATA_BUF_CNT_V  0x0000003FU
+#define I3C_MST_RX_DATA_BUF_CNT_S  16
+
+/** I3C_MST_PRESENT_STATE0_REG register
+ *  NA
+ */
+#define I3C_MST_PRESENT_STATE0_REG (DR_REG_I3C_MST_BASE + 0x50)
+/** I3C_MST_SDA_LVL : RO; bitpos: [0]; default: 1;
+ *  This bit is used to check the SCL line level to recover from error and  for
+ *  debugging. This bit reflects the value of synchronized scl_in_a.
+ */
+#define I3C_MST_SDA_LVL    (BIT(0))
+#define I3C_MST_SDA_LVL_M  (I3C_MST_SDA_LVL_V << I3C_MST_SDA_LVL_S)
+#define I3C_MST_SDA_LVL_V  0x00000001U
+#define I3C_MST_SDA_LVL_S  0
+/** I3C_MST_SCL_LVL : RO; bitpos: [1]; default: 1;
+ *  This bit is used to check the SDA line level to recover from error and  for
+ *  debugging. This bit reflects the value of synchronized sda_in_a.
+ */
+#define I3C_MST_SCL_LVL    (BIT(1))
+#define I3C_MST_SCL_LVL_M  (I3C_MST_SCL_LVL_V << I3C_MST_SCL_LVL_S)
+#define I3C_MST_SCL_LVL_V  0x00000001U
+#define I3C_MST_SCL_LVL_S  1
+/** I3C_MST_BUS_BUSY : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define I3C_MST_BUS_BUSY    (BIT(2))
+#define I3C_MST_BUS_BUSY_M  (I3C_MST_BUS_BUSY_V << I3C_MST_BUS_BUSY_S)
+#define I3C_MST_BUS_BUSY_V  0x00000001U
+#define I3C_MST_BUS_BUSY_S  2
+/** I3C_MST_BUS_FREE : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define I3C_MST_BUS_FREE    (BIT(3))
+#define I3C_MST_BUS_FREE_M  (I3C_MST_BUS_FREE_V << I3C_MST_BUS_FREE_S)
+#define I3C_MST_BUS_FREE_V  0x00000001U
+#define I3C_MST_BUS_FREE_S  3
+/** I3C_MST_CMD_TID : RO; bitpos: [12:9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_TID    0x0000000FU
+#define I3C_MST_CMD_TID_M  (I3C_MST_CMD_TID_V << I3C_MST_CMD_TID_S)
+#define I3C_MST_CMD_TID_V  0x0000000FU
+#define I3C_MST_CMD_TID_S  9
+/** I3C_MST_SCL_GEN_FSM_STATE : RO; bitpos: [15:13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_SCL_GEN_FSM_STATE    0x00000007U
+#define I3C_MST_SCL_GEN_FSM_STATE_M  (I3C_MST_SCL_GEN_FSM_STATE_V << I3C_MST_SCL_GEN_FSM_STATE_S)
+#define I3C_MST_SCL_GEN_FSM_STATE_V  0x00000007U
+#define I3C_MST_SCL_GEN_FSM_STATE_S  13
+/** I3C_MST_IBI_EV_HANDLE_FSM_STATE : RO; bitpos: [18:16]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_EV_HANDLE_FSM_STATE    0x00000007U
+#define I3C_MST_IBI_EV_HANDLE_FSM_STATE_M  (I3C_MST_IBI_EV_HANDLE_FSM_STATE_V << I3C_MST_IBI_EV_HANDLE_FSM_STATE_S)
+#define I3C_MST_IBI_EV_HANDLE_FSM_STATE_V  0x00000007U
+#define I3C_MST_IBI_EV_HANDLE_FSM_STATE_S  16
+/** I3C_MST_I2C_MODE_FSM_STATE : RO; bitpos: [21:19]; default: 0;
+ *  NA
+ */
+#define I3C_MST_I2C_MODE_FSM_STATE    0x00000007U
+#define I3C_MST_I2C_MODE_FSM_STATE_M  (I3C_MST_I2C_MODE_FSM_STATE_V << I3C_MST_I2C_MODE_FSM_STATE_S)
+#define I3C_MST_I2C_MODE_FSM_STATE_V  0x00000007U
+#define I3C_MST_I2C_MODE_FSM_STATE_S  19
+/** I3C_MST_SDR_MODE_FSM_STATE : RO; bitpos: [25:22]; default: 0;
+ *  NA
+ */
+#define I3C_MST_SDR_MODE_FSM_STATE    0x0000000FU
+#define I3C_MST_SDR_MODE_FSM_STATE_M  (I3C_MST_SDR_MODE_FSM_STATE_V << I3C_MST_SDR_MODE_FSM_STATE_S)
+#define I3C_MST_SDR_MODE_FSM_STATE_V  0x0000000FU
+#define I3C_MST_SDR_MODE_FSM_STATE_S  22
+/** I3C_MST_DAA_MODE_FSM_STATE : RO; bitpos: [28:26]; default: 0;
+ *  Reflects whether the Master Controller is in IDLE or not. This bit will be set when
+ *  all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the
+ *  Master State machine is in idle state. 0X0: not in idle  0x1: in idle
+ */
+#define I3C_MST_DAA_MODE_FSM_STATE    0x00000007U
+#define I3C_MST_DAA_MODE_FSM_STATE_M  (I3C_MST_DAA_MODE_FSM_STATE_V << I3C_MST_DAA_MODE_FSM_STATE_S)
+#define I3C_MST_DAA_MODE_FSM_STATE_V  0x00000007U
+#define I3C_MST_DAA_MODE_FSM_STATE_S  26
+/** I3C_MST_MAIN_FSM_STATE : RO; bitpos: [31:29]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MAIN_FSM_STATE    0x00000007U
+#define I3C_MST_MAIN_FSM_STATE_M  (I3C_MST_MAIN_FSM_STATE_V << I3C_MST_MAIN_FSM_STATE_S)
+#define I3C_MST_MAIN_FSM_STATE_V  0x00000007U
+#define I3C_MST_MAIN_FSM_STATE_S  29
+
+/** I3C_MST_PRESENT_STATE1_REG register
+ *  NA
+ */
+#define I3C_MST_PRESENT_STATE1_REG (DR_REG_I3C_MST_BASE + 0x54)
+/** I3C_MST_DATA_BYTE_CNT : RO; bitpos: [15:0]; default: 0;
+ *  Present transfer data byte cnt: tx data byte cnt if write  rx data byte cnt if read
+ *  ibi data byte cnt if IBI handle.
+ */
+#define I3C_MST_DATA_BYTE_CNT    0x0000FFFFU
+#define I3C_MST_DATA_BYTE_CNT_M  (I3C_MST_DATA_BYTE_CNT_V << I3C_MST_DATA_BYTE_CNT_S)
+#define I3C_MST_DATA_BYTE_CNT_V  0x0000FFFFU
+#define I3C_MST_DATA_BYTE_CNT_S  0
+
+/** I3C_MST_DEVICE_TABLE_REG register
+ *  Pointer for Device Address Table
+ */
+#define I3C_MST_DEVICE_TABLE_REG (DR_REG_I3C_MST_BASE + 0x58)
+/** I3C_MST_REG_DCT_DAA_INIT_INDEX : R/W; bitpos: [3:0]; default: 0;
+ *  Reserved
+ */
+#define I3C_MST_REG_DCT_DAA_INIT_INDEX    0x0000000FU
+#define I3C_MST_REG_DCT_DAA_INIT_INDEX_M  (I3C_MST_REG_DCT_DAA_INIT_INDEX_V << I3C_MST_REG_DCT_DAA_INIT_INDEX_S)
+#define I3C_MST_REG_DCT_DAA_INIT_INDEX_V  0x0000000FU
+#define I3C_MST_REG_DCT_DAA_INIT_INDEX_S  0
+/** I3C_MST_REG_DAT_DAA_INIT_INDEX : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_DAT_DAA_INIT_INDEX    0x0000000FU
+#define I3C_MST_REG_DAT_DAA_INIT_INDEX_M  (I3C_MST_REG_DAT_DAA_INIT_INDEX_V << I3C_MST_REG_DAT_DAA_INIT_INDEX_S)
+#define I3C_MST_REG_DAT_DAA_INIT_INDEX_V  0x0000000FU
+#define I3C_MST_REG_DAT_DAA_INIT_INDEX_S  4
+/** I3C_MST_PRESENT_DCT_INDEX : RO; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_PRESENT_DCT_INDEX    0x0000000FU
+#define I3C_MST_PRESENT_DCT_INDEX_M  (I3C_MST_PRESENT_DCT_INDEX_V << I3C_MST_PRESENT_DCT_INDEX_S)
+#define I3C_MST_PRESENT_DCT_INDEX_V  0x0000000FU
+#define I3C_MST_PRESENT_DCT_INDEX_S  8
+/** I3C_MST_PRESENT_DAT_INDEX : RO; bitpos: [15:12]; default: 0;
+ *  NA
+ */
+#define I3C_MST_PRESENT_DAT_INDEX    0x0000000FU
+#define I3C_MST_PRESENT_DAT_INDEX_M  (I3C_MST_PRESENT_DAT_INDEX_V << I3C_MST_PRESENT_DAT_INDEX_S)
+#define I3C_MST_PRESENT_DAT_INDEX_V  0x0000000FU
+#define I3C_MST_PRESENT_DAT_INDEX_S  12
+
+/** I3C_MST_TIME_OUT_VALUE_REG register
+ *  NA
+ */
+#define I3C_MST_TIME_OUT_VALUE_REG (DR_REG_I3C_MST_BASE + 0x5c)
+/** I3C_MST_REG_RESP_BUF_TO_VALUE : R/W; bitpos: [4:0]; default: 16;
+ *  NA
+ */
+#define I3C_MST_REG_RESP_BUF_TO_VALUE    0x0000001FU
+#define I3C_MST_REG_RESP_BUF_TO_VALUE_M  (I3C_MST_REG_RESP_BUF_TO_VALUE_V << I3C_MST_REG_RESP_BUF_TO_VALUE_S)
+#define I3C_MST_REG_RESP_BUF_TO_VALUE_V  0x0000001FU
+#define I3C_MST_REG_RESP_BUF_TO_VALUE_S  0
+/** I3C_MST_REG_RESP_BUF_TO_EN : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RESP_BUF_TO_EN    (BIT(5))
+#define I3C_MST_REG_RESP_BUF_TO_EN_M  (I3C_MST_REG_RESP_BUF_TO_EN_V << I3C_MST_REG_RESP_BUF_TO_EN_S)
+#define I3C_MST_REG_RESP_BUF_TO_EN_V  0x00000001U
+#define I3C_MST_REG_RESP_BUF_TO_EN_S  5
+/** I3C_MST_REG_IBI_DATA_BUF_TO_VALUE : R/W; bitpos: [10:6]; default: 16;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_DATA_BUF_TO_VALUE    0x0000001FU
+#define I3C_MST_REG_IBI_DATA_BUF_TO_VALUE_M  (I3C_MST_REG_IBI_DATA_BUF_TO_VALUE_V << I3C_MST_REG_IBI_DATA_BUF_TO_VALUE_S)
+#define I3C_MST_REG_IBI_DATA_BUF_TO_VALUE_V  0x0000001FU
+#define I3C_MST_REG_IBI_DATA_BUF_TO_VALUE_S  6
+/** I3C_MST_REG_IBI_DATA_BUF_TO_EN : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_DATA_BUF_TO_EN    (BIT(11))
+#define I3C_MST_REG_IBI_DATA_BUF_TO_EN_M  (I3C_MST_REG_IBI_DATA_BUF_TO_EN_V << I3C_MST_REG_IBI_DATA_BUF_TO_EN_S)
+#define I3C_MST_REG_IBI_DATA_BUF_TO_EN_V  0x00000001U
+#define I3C_MST_REG_IBI_DATA_BUF_TO_EN_S  11
+/** I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE : R/W; bitpos: [16:12]; default: 16;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE    0x0000001FU
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE_M  (I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE_V << I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE_S)
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE_V  0x0000001FU
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE_S  12
+/** I3C_MST_REG_IBI_STATUS_BUF_TO_EN : R/W; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_EN    (BIT(17))
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_EN_M  (I3C_MST_REG_IBI_STATUS_BUF_TO_EN_V << I3C_MST_REG_IBI_STATUS_BUF_TO_EN_S)
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_EN_V  0x00000001U
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_EN_S  17
+/** I3C_MST_REG_RX_DATA_BUF_TO_VALUE : R/W; bitpos: [22:18]; default: 16;
+ *  NA
+ */
+#define I3C_MST_REG_RX_DATA_BUF_TO_VALUE    0x0000001FU
+#define I3C_MST_REG_RX_DATA_BUF_TO_VALUE_M  (I3C_MST_REG_RX_DATA_BUF_TO_VALUE_V << I3C_MST_REG_RX_DATA_BUF_TO_VALUE_S)
+#define I3C_MST_REG_RX_DATA_BUF_TO_VALUE_V  0x0000001FU
+#define I3C_MST_REG_RX_DATA_BUF_TO_VALUE_S  18
+/** I3C_MST_REG_RX_DATA_BUF_TO_EN : R/W; bitpos: [23]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RX_DATA_BUF_TO_EN    (BIT(23))
+#define I3C_MST_REG_RX_DATA_BUF_TO_EN_M  (I3C_MST_REG_RX_DATA_BUF_TO_EN_V << I3C_MST_REG_RX_DATA_BUF_TO_EN_S)
+#define I3C_MST_REG_RX_DATA_BUF_TO_EN_V  0x00000001U
+#define I3C_MST_REG_RX_DATA_BUF_TO_EN_S  23
+
+/** I3C_MST_SCL_I3C_MST_OD_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_I3C_MST_OD_TIME_REG (DR_REG_I3C_MST_BASE + 0x60)
+/** I3C_MST_REG_I3C_MST_OD_LOW_PERIOD : R/W; bitpos: [15:0]; default: 25;
+ *  SCL Open-Drain low count for I3C transfers targeted to I3C devices.
+ */
+#define I3C_MST_REG_I3C_MST_OD_LOW_PERIOD    0x0000FFFFU
+#define I3C_MST_REG_I3C_MST_OD_LOW_PERIOD_M  (I3C_MST_REG_I3C_MST_OD_LOW_PERIOD_V << I3C_MST_REG_I3C_MST_OD_LOW_PERIOD_S)
+#define I3C_MST_REG_I3C_MST_OD_LOW_PERIOD_V  0x0000FFFFU
+#define I3C_MST_REG_I3C_MST_OD_LOW_PERIOD_S  0
+/** I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD : R/W; bitpos: [31:16]; default: 5;
+ *  SCL Open-Drain High count for I3C transfers targeted to I3C devices.
+ */
+#define I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD    0x0000FFFFU
+#define I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD_M  (I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD_V << I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD_S)
+#define I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD_V  0x0000FFFFU
+#define I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD_S  16
+
+/** I3C_MST_SCL_I3C_MST_PP_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_I3C_MST_PP_TIME_REG (DR_REG_I3C_MST_BASE + 0x64)
+/** I3C_MST_REG_I3C_MST_PP_LOW_PERIOD : R/W; bitpos: [7:0]; default: 5;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_PP_LOW_PERIOD    0x000000FFU
+#define I3C_MST_REG_I3C_MST_PP_LOW_PERIOD_M  (I3C_MST_REG_I3C_MST_PP_LOW_PERIOD_V << I3C_MST_REG_I3C_MST_PP_LOW_PERIOD_S)
+#define I3C_MST_REG_I3C_MST_PP_LOW_PERIOD_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_PP_LOW_PERIOD_S  0
+/** I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD : R/W; bitpos: [23:16]; default: 5;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD    0x000000FFU
+#define I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD_M  (I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD_V << I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD_S)
+#define I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD_S  16
+
+/** I3C_MST_SCL_I2C_FM_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_I2C_FM_TIME_REG (DR_REG_I3C_MST_BASE + 0x68)
+/** I3C_MST_REG_I2C_FM_LOW_PERIOD : R/W; bitpos: [15:0]; default: 163;
+ *  NA
+ */
+#define I3C_MST_REG_I2C_FM_LOW_PERIOD    0x0000FFFFU
+#define I3C_MST_REG_I2C_FM_LOW_PERIOD_M  (I3C_MST_REG_I2C_FM_LOW_PERIOD_V << I3C_MST_REG_I2C_FM_LOW_PERIOD_S)
+#define I3C_MST_REG_I2C_FM_LOW_PERIOD_V  0x0000FFFFU
+#define I3C_MST_REG_I2C_FM_LOW_PERIOD_S  0
+/** I3C_MST_REG_I2C_FM_HIGH_PERIOD : R/W; bitpos: [31:16]; default: 75;
+ *  The SCL open-drain low count timing for I2C Fast Mode transfers.
+ */
+#define I3C_MST_REG_I2C_FM_HIGH_PERIOD    0x0000FFFFU
+#define I3C_MST_REG_I2C_FM_HIGH_PERIOD_M  (I3C_MST_REG_I2C_FM_HIGH_PERIOD_V << I3C_MST_REG_I2C_FM_HIGH_PERIOD_S)
+#define I3C_MST_REG_I2C_FM_HIGH_PERIOD_V  0x0000FFFFU
+#define I3C_MST_REG_I2C_FM_HIGH_PERIOD_S  16
+
+/** I3C_MST_SCL_I2C_FMP_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_I2C_FMP_TIME_REG (DR_REG_I3C_MST_BASE + 0x6c)
+/** I3C_MST_REG_I2C_FMP_LOW_PERIOD : R/W; bitpos: [15:0]; default: 63;
+ *  NA
+ */
+#define I3C_MST_REG_I2C_FMP_LOW_PERIOD    0x0000FFFFU
+#define I3C_MST_REG_I2C_FMP_LOW_PERIOD_M  (I3C_MST_REG_I2C_FMP_LOW_PERIOD_V << I3C_MST_REG_I2C_FMP_LOW_PERIOD_S)
+#define I3C_MST_REG_I2C_FMP_LOW_PERIOD_V  0x0000FFFFU
+#define I3C_MST_REG_I2C_FMP_LOW_PERIOD_S  0
+/** I3C_MST_REG_I2C_FMP_HIGH_PERIOD : R/W; bitpos: [23:16]; default: 33;
+ *  NA
+ */
+#define I3C_MST_REG_I2C_FMP_HIGH_PERIOD    0x000000FFU
+#define I3C_MST_REG_I2C_FMP_HIGH_PERIOD_M  (I3C_MST_REG_I2C_FMP_HIGH_PERIOD_V << I3C_MST_REG_I2C_FMP_HIGH_PERIOD_S)
+#define I3C_MST_REG_I2C_FMP_HIGH_PERIOD_V  0x000000FFU
+#define I3C_MST_REG_I2C_FMP_HIGH_PERIOD_S  16
+
+/** I3C_MST_SCL_EXT_LOW_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_EXT_LOW_TIME_REG (DR_REG_I3C_MST_BASE + 0x70)
+/** I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1 : R/W; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1    0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1_M  (I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1_V << I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1_S)
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1_S  0
+/** I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2 : R/W; bitpos: [15:8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2    0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2_M  (I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2_V << I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2_S)
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2_S  8
+/** I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3 : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3    0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3_M  (I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3_V << I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3_S)
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3_S  16
+/** I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4 : R/W; bitpos: [31:24]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4    0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4_M  (I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4_V << I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4_S)
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4_S  24
+
+/** I3C_MST_SDA_SAMPLE_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SDA_SAMPLE_TIME_REG (DR_REG_I3C_MST_BASE + 0x74)
+/** I3C_MST_REG_SDA_OD_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  It is used to adjust sda sample point when scl high under open drain speed
+ */
+#define I3C_MST_REG_SDA_OD_SAMPLE_TIME    0x000001FFU
+#define I3C_MST_REG_SDA_OD_SAMPLE_TIME_M  (I3C_MST_REG_SDA_OD_SAMPLE_TIME_V << I3C_MST_REG_SDA_OD_SAMPLE_TIME_S)
+#define I3C_MST_REG_SDA_OD_SAMPLE_TIME_V  0x000001FFU
+#define I3C_MST_REG_SDA_OD_SAMPLE_TIME_S  0
+/** I3C_MST_REG_SDA_PP_SAMPLE_TIME : R/W; bitpos: [13:9]; default: 0;
+ *  It is used to adjust sda sample point when scl high under push pull speed
+ */
+#define I3C_MST_REG_SDA_PP_SAMPLE_TIME    0x0000001FU
+#define I3C_MST_REG_SDA_PP_SAMPLE_TIME_M  (I3C_MST_REG_SDA_PP_SAMPLE_TIME_V << I3C_MST_REG_SDA_PP_SAMPLE_TIME_S)
+#define I3C_MST_REG_SDA_PP_SAMPLE_TIME_V  0x0000001FU
+#define I3C_MST_REG_SDA_PP_SAMPLE_TIME_S  9
+
+/** I3C_MST_SDA_HOLD_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SDA_HOLD_TIME_REG (DR_REG_I3C_MST_BASE + 0x78)
+/** I3C_MST_REG_SDA_OD_TX_HOLD_TIME : R/W; bitpos: [8:0]; default: 1;
+ *  It is used to adjust sda drive point after scl neg under open drain speed
+ */
+#define I3C_MST_REG_SDA_OD_TX_HOLD_TIME    0x000001FFU
+#define I3C_MST_REG_SDA_OD_TX_HOLD_TIME_M  (I3C_MST_REG_SDA_OD_TX_HOLD_TIME_V << I3C_MST_REG_SDA_OD_TX_HOLD_TIME_S)
+#define I3C_MST_REG_SDA_OD_TX_HOLD_TIME_V  0x000001FFU
+#define I3C_MST_REG_SDA_OD_TX_HOLD_TIME_S  0
+/** I3C_MST_REG_SDA_PP_TX_HOLD_TIME : R/W; bitpos: [13:9]; default: 0;
+ *  It is used to adjust sda dirve point after scl neg under push pull speed
+ */
+#define I3C_MST_REG_SDA_PP_TX_HOLD_TIME    0x0000001FU
+#define I3C_MST_REG_SDA_PP_TX_HOLD_TIME_M  (I3C_MST_REG_SDA_PP_TX_HOLD_TIME_V << I3C_MST_REG_SDA_PP_TX_HOLD_TIME_S)
+#define I3C_MST_REG_SDA_PP_TX_HOLD_TIME_V  0x0000001FU
+#define I3C_MST_REG_SDA_PP_TX_HOLD_TIME_S  9
+
+/** I3C_MST_SCL_START_HOLD_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_START_HOLD_REG (DR_REG_I3C_MST_BASE + 0x7c)
+/** I3C_MST_REG_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  I2C_SCL_START_HOLD_TIME
+ */
+#define I3C_MST_REG_SCL_START_HOLD_TIME    0x000001FFU
+#define I3C_MST_REG_SCL_START_HOLD_TIME_M  (I3C_MST_REG_SCL_START_HOLD_TIME_V << I3C_MST_REG_SCL_START_HOLD_TIME_S)
+#define I3C_MST_REG_SCL_START_HOLD_TIME_V  0x000001FFU
+#define I3C_MST_REG_SCL_START_HOLD_TIME_S  0
+/** I3C_MST_REG_START_DET_HOLD_TIME : R/W; bitpos: [10:9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_START_DET_HOLD_TIME    0x00000003U
+#define I3C_MST_REG_START_DET_HOLD_TIME_M  (I3C_MST_REG_START_DET_HOLD_TIME_V << I3C_MST_REG_START_DET_HOLD_TIME_S)
+#define I3C_MST_REG_START_DET_HOLD_TIME_V  0x00000003U
+#define I3C_MST_REG_START_DET_HOLD_TIME_S  9
+
+/** I3C_MST_SCL_RSTART_SETUP_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_RSTART_SETUP_REG (DR_REG_I3C_MST_BASE + 0x80)
+/** I3C_MST_REG_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  I2C_SCL_RSTART_SETUP_TIME
+ */
+#define I3C_MST_REG_SCL_RSTART_SETUP_TIME    0x000001FFU
+#define I3C_MST_REG_SCL_RSTART_SETUP_TIME_M  (I3C_MST_REG_SCL_RSTART_SETUP_TIME_V << I3C_MST_REG_SCL_RSTART_SETUP_TIME_S)
+#define I3C_MST_REG_SCL_RSTART_SETUP_TIME_V  0x000001FFU
+#define I3C_MST_REG_SCL_RSTART_SETUP_TIME_S  0
+
+/** I3C_MST_SCL_STOP_HOLD_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_STOP_HOLD_REG (DR_REG_I3C_MST_BASE + 0x84)
+/** I3C_MST_REG_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  I2C_SCL_STOP_HOLD_TIME
+ */
+#define I3C_MST_REG_SCL_STOP_HOLD_TIME    0x000001FFU
+#define I3C_MST_REG_SCL_STOP_HOLD_TIME_M  (I3C_MST_REG_SCL_STOP_HOLD_TIME_V << I3C_MST_REG_SCL_STOP_HOLD_TIME_S)
+#define I3C_MST_REG_SCL_STOP_HOLD_TIME_V  0x000001FFU
+#define I3C_MST_REG_SCL_STOP_HOLD_TIME_S  0
+
+/** I3C_MST_SCL_STOP_SETUP_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_STOP_SETUP_REG (DR_REG_I3C_MST_BASE + 0x88)
+/** I3C_MST_REG_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  I2C_SCL_STOP_SETUP_TIME
+ */
+#define I3C_MST_REG_SCL_STOP_SETUP_TIME    0x000001FFU
+#define I3C_MST_REG_SCL_STOP_SETUP_TIME_M  (I3C_MST_REG_SCL_STOP_SETUP_TIME_V << I3C_MST_REG_SCL_STOP_SETUP_TIME_S)
+#define I3C_MST_REG_SCL_STOP_SETUP_TIME_V  0x000001FFU
+#define I3C_MST_REG_SCL_STOP_SETUP_TIME_S  0
+
+/** I3C_MST_BUS_FREE_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_BUS_FREE_TIME_REG (DR_REG_I3C_MST_BASE + 0x90)
+/** I3C_MST_REG_BUS_FREE_TIME : R/W; bitpos: [15:0]; default: 5;
+ *  I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus
+ *  System, this field represents tCAS.  In Mixed Bus System, this field is expected to
+ *  be programmed to tLOW of I2C Timing.
+ */
+#define I3C_MST_REG_BUS_FREE_TIME    0x0000FFFFU
+#define I3C_MST_REG_BUS_FREE_TIME_M  (I3C_MST_REG_BUS_FREE_TIME_V << I3C_MST_REG_BUS_FREE_TIME_S)
+#define I3C_MST_REG_BUS_FREE_TIME_V  0x0000FFFFU
+#define I3C_MST_REG_BUS_FREE_TIME_S  0
+
+/** I3C_MST_SCL_TERMN_T_EXT_LOW_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_TERMN_T_EXT_LOW_TIME_REG (DR_REG_I3C_MST_BASE + 0x94)
+/** I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME : R/W; bitpos: [7:0]; default: 2;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME    0x000000FFU
+#define I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_M  (I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_V << I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_S)
+#define I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_S  0
+
+/** I3C_MST_VER_ID_REG register
+ *  NA
+ */
+#define I3C_MST_VER_ID_REG (DR_REG_I3C_MST_BASE + 0xa0)
+/** I3C_MST_REG_I3C_MST_VER_ID : R/W; bitpos: [31:0]; default: 539165956;
+ *  This field indicates the controller current release number that is read by an
+ *  application.
+ */
+#define I3C_MST_REG_I3C_MST_VER_ID    0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_VER_ID_M  (I3C_MST_REG_I3C_MST_VER_ID_V << I3C_MST_REG_I3C_MST_VER_ID_S)
+#define I3C_MST_REG_I3C_MST_VER_ID_V  0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_VER_ID_S  0
+
+/** I3C_MST_VER_TYPE_REG register
+ *  NA
+ */
+#define I3C_MST_VER_TYPE_REG (DR_REG_I3C_MST_BASE + 0xa4)
+/** I3C_MST_REG_I3C_MST_VER_TYPE : R/W; bitpos: [31:0]; default: 0;
+ *  This field indicates the controller current release type that is read by an
+ *  application.
+ */
+#define I3C_MST_REG_I3C_MST_VER_TYPE    0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_VER_TYPE_M  (I3C_MST_REG_I3C_MST_VER_TYPE_V << I3C_MST_REG_I3C_MST_VER_TYPE_S)
+#define I3C_MST_REG_I3C_MST_VER_TYPE_V  0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_VER_TYPE_S  0
+
+/** I3C_MST_FPGA_DEBUG_PROBE_REG register
+ *  NA
+ */
+#define I3C_MST_FPGA_DEBUG_PROBE_REG (DR_REG_I3C_MST_BASE + 0xac)
+/** I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE : R/W; bitpos: [31:0]; default: 1;
+ *  For Debug Probe Test on FPGA
+ */
+#define I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE    0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE_M  (I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE_V << I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE_S)
+#define I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE_V  0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE_S  0
+
+/** I3C_MST_RND_ECO_CS_REG register
+ *  NA
+ */
+#define I3C_MST_RND_ECO_CS_REG (DR_REG_I3C_MST_BASE + 0xb0)
+/** I3C_MST_REG_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RND_ECO_EN    (BIT(0))
+#define I3C_MST_REG_RND_ECO_EN_M  (I3C_MST_REG_RND_ECO_EN_V << I3C_MST_REG_RND_ECO_EN_S)
+#define I3C_MST_REG_RND_ECO_EN_V  0x00000001U
+#define I3C_MST_REG_RND_ECO_EN_S  0
+/** I3C_MST_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RND_ECO_RESULT    (BIT(1))
+#define I3C_MST_RND_ECO_RESULT_M  (I3C_MST_RND_ECO_RESULT_V << I3C_MST_RND_ECO_RESULT_S)
+#define I3C_MST_RND_ECO_RESULT_V  0x00000001U
+#define I3C_MST_RND_ECO_RESULT_S  1
+
+/** I3C_MST_RND_ECO_LOW_REG register
+ *  NA
+ */
+#define I3C_MST_RND_ECO_LOW_REG (DR_REG_I3C_MST_BASE + 0xb4)
+/** I3C_MST_REG_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RND_ECO_LOW    0xFFFFFFFFU
+#define I3C_MST_REG_RND_ECO_LOW_M  (I3C_MST_REG_RND_ECO_LOW_V << I3C_MST_REG_RND_ECO_LOW_S)
+#define I3C_MST_REG_RND_ECO_LOW_V  0xFFFFFFFFU
+#define I3C_MST_REG_RND_ECO_LOW_S  0
+
+/** I3C_MST_RND_ECO_HIGH_REG register
+ *  NA
+ */
+#define I3C_MST_RND_ECO_HIGH_REG (DR_REG_I3C_MST_BASE + 0xb8)
+/** I3C_MST_REG_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 65535;
+ *  NA
+ */
+#define I3C_MST_REG_RND_ECO_HIGH    0xFFFFFFFFU
+#define I3C_MST_REG_RND_ECO_HIGH_M  (I3C_MST_REG_RND_ECO_HIGH_V << I3C_MST_REG_RND_ECO_HIGH_S)
+#define I3C_MST_REG_RND_ECO_HIGH_V  0xFFFFFFFFU
+#define I3C_MST_REG_RND_ECO_HIGH_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_struct.h
new file mode 100644
index 0000000000..de7c314a21
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i3c_mst_struct.h
@@ -0,0 +1,1183 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: I3C DEVICE CTRL REG */
+/** Type of device_ctrl register
+ *  DEVICE_CTRL register controls the transfer properties and disposition of
+ *  controllers capabilities.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** reg_ba_include : R/W; bitpos: [1]; default: 0;
+         *  This bit is used to include I3C broadcast address(0x7E) for private transfer.(If
+         *  I3C broadcast address is not include for the private transfer, In-Band Interrupts
+         *  driven from Slaves may not win address arbitration. Hence IBIs will get delayed)
+         */
+        uint32_t reg_ba_include:1;
+        /** reg_trans_start : R/W; bitpos: [2]; default: 0;
+         *  Transfer Start
+         */
+        uint32_t reg_trans_start:1;
+        /** reg_clk_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        /** reg_ibi_rstart_trans_en : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_ibi_rstart_trans_en:1;
+        /** reg_auto_dis_ibi_en : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_auto_dis_ibi_en:1;
+        /** reg_dma_rx_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dma_rx_en:1;
+        /** reg_dma_tx_en : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dma_tx_en:1;
+        /** reg_multi_slv_single_ccc_en : R/W; bitpos: [8]; default: 0;
+         *  0: rx high bit first, 1: rx low bit first
+         */
+        uint32_t reg_multi_slv_single_ccc_en:1;
+        /** reg_rx_bit_order : R/W; bitpos: [9]; default: 0;
+         *  0: rx low byte fist, 1: rx high byte first
+         */
+        uint32_t reg_rx_bit_order:1;
+        /** reg_rx_byte_order : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rx_byte_order:1;
+        /** reg_scl_pullup_force_en : R/W; bitpos: [11]; default: 0;
+         *  This bit is used to force scl_pullup_en
+         */
+        uint32_t reg_scl_pullup_force_en:1;
+        /** reg_scl_oe_force_en : R/W; bitpos: [12]; default: 1;
+         *  This bit is used to force scl_oe
+         */
+        uint32_t reg_scl_oe_force_en:1;
+        /** reg_sda_pp_rd_pullup_en : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sda_pp_rd_pullup_en:1;
+        /** reg_sda_rd_tbit_hlvl_pullup_en : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sda_rd_tbit_hlvl_pullup_en:1;
+        /** reg_sda_pp_wr_pullup_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sda_pp_wr_pullup_en:1;
+        /** reg_data_byte_cnt_unlatch : R/W; bitpos: [16]; default: 0;
+         *  1: read current real-time updated value  0: read latch data byte cnt value
+         */
+        uint32_t reg_data_byte_cnt_unlatch:1;
+        /** reg_mem_clk_force_on : R/W; bitpos: [17]; default: 0;
+         *  1: dev characteristic and address table memory clk  date force on . 0 :  clock
+         *  gating by rd/wr.
+         */
+        uint32_t reg_mem_clk_force_on:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} i3c_mst_device_ctrl_reg_t;
+
+
+/** Group: I3C BUFFER THLD CTRL REG */
+/** Type of buffer_thld_ctrl register
+ *  In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C
+ *  controller generates an IBI status. This field controls the number of IBI status
+ *  entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt.
+ */
+typedef union {
+    struct {
+        /** reg_cmd_buf_empty_thld : R/W; bitpos: [3:0]; default: 1;
+         *  Command Buffer Empty Threshold Value is used to control the number of empty
+         *  locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT
+         *  interrupt.
+         */
+        uint32_t reg_cmd_buf_empty_thld:4;
+        uint32_t reserved_4:2;
+        /** reg_resp_buf_thld : R/W; bitpos: [8:6]; default: 1;
+         *  Response Buffer Threshold Value is used to control the number of entries in the
+         *  Response Buffer that trigger the RESP_READY_STAT_INTR.
+         */
+        uint32_t reg_resp_buf_thld:3;
+        uint32_t reserved_9:3;
+        /** reg_ibi_data_buf_thld : R/W; bitpos: [14:12]; default: 1;
+         *  In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C
+         *  controller generates an IBI status. This field controls the number of IBI data
+         *  entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt.
+         */
+        uint32_t reg_ibi_data_buf_thld:3;
+        uint32_t reserved_15:3;
+        /** reg_ibi_status_buf_thld : R/W; bitpos: [20:18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_ibi_status_buf_thld:3;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i3c_mst_buffer_thld_ctrl_reg_t;
+
+
+/** Group: I3C DATA BUFFER THLD CTRL REG */
+/** Type of data_buffer_thld_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tx_data_buf_thld : R/W; bitpos: [2:0]; default: 1;
+         *  Transmit Buffer Threshold Value. This field controls the number of empty locations
+         *  in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values:
+         *  000:2  001:4  010:8  011:16  100:31, else:31
+         */
+        uint32_t reg_tx_data_buf_thld:3;
+        /** reg_rx_data_buf_thld : R/W; bitpos: [5:3]; default: 1;
+         *  Receive Buffer Threshold Value. This field controls the number of empty locations
+         *  in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2  001:4
+         *  010:8  011:16  100:31, else:31
+         */
+        uint32_t reg_rx_data_buf_thld:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i3c_mst_data_buffer_thld_ctrl_reg_t;
+
+
+/** Group: I3C IBI NOTIFY CTRL REG */
+/** Type of ibi_notify_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_notify_sir_rejected : R/W; bitpos: [2]; default: 0;
+         *  Notify Rejected Slave Interrupt Request Control. This bit is used to suppress
+         *  reporting to the application about Slave Interrupt Request. 0:Suppress passing the
+         *  IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request
+         *  is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI
+         *  Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed
+         *  and auto-disabled based on the IBI_SIR_REQ_REJECT registerl.
+         */
+        uint32_t reg_notify_sir_rejected:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} i3c_mst_ibi_notify_ctrl_reg_t;
+
+
+/** Group: I3C IBI SIR REQ PAYLOAD REG */
+/** Type of ibi_sir_req_payload register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sir_req_payload : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sir_req_payload:32;
+    };
+    uint32_t val;
+} i3c_mst_ibi_sir_req_payload_reg_t;
+
+
+/** Group: I3C IBI SIR REQ REJECT REG */
+/** Type of ibi_sir_req_reject register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sir_req_reject : R/W; bitpos: [31:0]; default: 0;
+         *  The application of controller can decide whether to send ACK or NACK for Slave
+         *  request received from any I3C device. A device specific response control bit is
+         *  provided to select the response option, Master will ACK/NACK the Master Request
+         *  based on programming of control bit, corresponding to the interrupting device.
+         *  0:ACK the SIR Request  1:NACK and send direct auto disable CCC
+         */
+        uint32_t reg_sir_req_reject:32;
+    };
+    uint32_t val;
+} i3c_mst_ibi_sir_req_reject_reg_t;
+
+
+/** Group: I3C INT CLR REG */
+/** Type of int_clr register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tx_data_buf_thld_int_clr : WT; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t tx_data_buf_thld_int_clr:1;
+        /** rx_data_buf_thld_int_clr : WT; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t rx_data_buf_thld_int_clr:1;
+        /** ibi_status_thld_int_clr : WT; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_thld_int_clr:1;
+        /** cmd_buf_empty_thld_int_clr : WT; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_buf_empty_thld_int_clr:1;
+        /** resp_ready_int_clr : WT; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t resp_ready_int_clr:1;
+        /** nxt_cmd_req_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t nxt_cmd_req_err_int_clr:1;
+        /** transfer_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_err_int_clr:1;
+        /** transfer_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_complete_int_clr:1;
+        /** command_done_int_clr : WT; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t command_done_int_clr:1;
+        /** detect_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t detect_start_int_clr:1;
+        /** resp_buf_ovf_int_clr : WT; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t resp_buf_ovf_int_clr:1;
+        /** ibi_data_buf_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data_buf_ovf_int_clr:1;
+        /** ibi_status_buf_ovf_int_clr : WT; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_buf_ovf_int_clr:1;
+        /** ibi_handle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_handle_done_int_clr:1;
+        /** ibi_detect_int_clr : WT; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_detect_int_clr:1;
+        /** cmd_ccc_mismatch_int_clr : WT; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_ccc_mismatch_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_int_clr_reg_t;
+
+
+/** Group: I3C INT RAW REG */
+/** Type of int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tx_data_buf_thld_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t tx_data_buf_thld_int_raw:1;
+        /** rx_data_buf_thld_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t rx_data_buf_thld_int_raw:1;
+        /** ibi_status_thld_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_thld_int_raw:1;
+        /** cmd_buf_empty_thld_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t cmd_buf_empty_thld_int_raw:1;
+        /** resp_ready_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t resp_ready_int_raw:1;
+        /** nxt_cmd_req_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t nxt_cmd_req_err_int_raw:1;
+        /** transfer_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_err_int_raw:1;
+        /** transfer_complete_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_complete_int_raw:1;
+        /** command_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t command_done_int_raw:1;
+        /** detect_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t detect_start_int_raw:1;
+        /** resp_buf_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t resp_buf_ovf_int_raw:1;
+        /** ibi_data_buf_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data_buf_ovf_int_raw:1;
+        /** ibi_status_buf_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_buf_ovf_int_raw:1;
+        /** ibi_handle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_handle_done_int_raw:1;
+        /** ibi_detect_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_detect_int_raw:1;
+        /** cmd_ccc_mismatch_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_ccc_mismatch_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_int_raw_reg_t;
+
+
+/** Group: I3C INT ST REG */
+/** Type of int_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tx_data_buf_thld_int_st : RO; bitpos: [0]; default: 0;
+         *  This interrupt is generated when number of empty locations in transmit buffer is
+         *  greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in
+         *  DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+         *  number of empty locations in transmit buffer is less than threshold value.
+         */
+        uint32_t tx_data_buf_thld_int_st:1;
+        /** rx_data_buf_thld_int_st : RO; bitpos: [1]; default: 0;
+         *  This interrupt is generated when number of entries in receive buffer is greater
+         *  than or equal to threshold value specified by RX_BUF_THLD field in
+         *  DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+         *  number of entries in receive buffer is less than threshold value.
+         */
+        uint32_t rx_data_buf_thld_int_st:1;
+        /** ibi_status_thld_int_st : RO; bitpos: [2]; default: 0;
+         *  Only used in master mode. This interrupt is generated when number of entries in IBI
+         *  buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field
+         *  in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+         *  number of entries in IBI buffer is less than threshold value.
+         */
+        uint32_t ibi_status_thld_int_st:1;
+        /** cmd_buf_empty_thld_int_st : RO; bitpos: [3]; default: 0;
+         *  This interrupt is generated when number of empty locations in command buffer is
+         *  greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in
+         *  BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number
+         *  of empty locations in command buffer is less than threshold value.
+         */
+        uint32_t cmd_buf_empty_thld_int_st:1;
+        /** resp_ready_int_st : RO; bitpos: [4]; default: 0;
+         *  This interrupt is generated when number of entries in response buffer is greater
+         *  than or equal to threshold value specified by RESP_BUF_THLD field in
+         *  BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number
+         *  of entries in response buffer is less than threshold value.
+         */
+        uint32_t resp_ready_int_st:1;
+        /** nxt_cmd_req_err_int_st : RO; bitpos: [5]; default: 0;
+         *  This interrupt is generated if toc is 0(master will restart next command), but
+         *  command buf is empty.
+         */
+        uint32_t nxt_cmd_req_err_int_st:1;
+        /** transfer_err_int_st : RO; bitpos: [6]; default: 0;
+         *  This interrupt is generated if any error occurs during transfer. The error type
+         *  will be specified in the response packet associated with the command (in ERR_STATUS
+         *  field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1.
+         */
+        uint32_t transfer_err_int_st:1;
+        /** transfer_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_complete_int_st:1;
+        /** command_done_int_st : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t command_done_int_st:1;
+        /** detect_start_int_st : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t detect_start_int_st:1;
+        /** resp_buf_ovf_int_st : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t resp_buf_ovf_int_st:1;
+        /** ibi_data_buf_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data_buf_ovf_int_st:1;
+        /** ibi_status_buf_ovf_int_st : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_buf_ovf_int_st:1;
+        /** ibi_handle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_handle_done_int_st:1;
+        /** ibi_detect_int_st : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_detect_int_st:1;
+        /** cmd_ccc_mismatch_int_st : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_ccc_mismatch_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_int_st_reg_t;
+
+
+/** Group: I3C INT ST ENA REG */
+/** Type of int_st_ena register
+ *  The Interrupt status will be updated in INTR_STATUS register if corresponding
+ *  Status Enable bit set.
+ */
+typedef union {
+    struct {
+        /** tx_data_buf_thld_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Transmit Buffer threshold status enable.
+         */
+        uint32_t tx_data_buf_thld_int_ena:1;
+        /** rx_data_buf_thld_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Receive Buffer threshold status enable.
+         */
+        uint32_t rx_data_buf_thld_int_ena:1;
+        /** ibi_status_thld_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Only used in master mode. IBI Buffer threshold status enable.
+         */
+        uint32_t ibi_status_thld_int_ena:1;
+        /** cmd_buf_empty_thld_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Command buffer ready status enable.
+         */
+        uint32_t cmd_buf_empty_thld_int_ena:1;
+        /** resp_ready_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Response buffer ready status enable.
+         */
+        uint32_t resp_ready_int_ena:1;
+        /** nxt_cmd_req_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  next command request error status enable
+         */
+        uint32_t nxt_cmd_req_err_int_ena:1;
+        /** transfer_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Transfer error status enable
+         */
+        uint32_t transfer_err_int_ena:1;
+        /** transfer_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_complete_int_ena:1;
+        /** command_done_int_ena : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t command_done_int_ena:1;
+        /** detect_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t detect_start_int_ena:1;
+        /** resp_buf_ovf_int_ena : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t resp_buf_ovf_int_ena:1;
+        /** ibi_data_buf_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data_buf_ovf_int_ena:1;
+        /** ibi_status_buf_ovf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_buf_ovf_int_ena:1;
+        /** ibi_handle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_handle_done_int_ena:1;
+        /** ibi_detect_int_ena : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_detect_int_ena:1;
+        /** cmd_ccc_mismatch_int_ena : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_ccc_mismatch_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_int_st_ena_reg_t;
+
+
+/** Group: I3C RESET CTRL REG */
+/** Type of reset_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core_soft_rst : WT; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_core_soft_rst:1;
+        /** reg_cmd_buf_rst : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cmd_buf_rst:1;
+        /** reg_resp_buf_rst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_resp_buf_rst:1;
+        /** reg_tx_data_buf_buf_rst : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_tx_data_buf_buf_rst:1;
+        /** reg_rx_data_buf_rst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rx_data_buf_rst:1;
+        /** reg_ibi_data_buf_rst : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_ibi_data_buf_rst:1;
+        /** reg_ibi_status_buf_rst : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t reg_ibi_status_buf_rst:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} i3c_mst_reset_ctrl_reg_t;
+
+
+/** Group: I3C BUFFER STATUS LEVEL REG */
+/** Type of buffer_status_level register
+ *  BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.
+ */
+typedef union {
+    struct {
+        /** cmd_buf_empty_cnt : RO; bitpos: [4:0]; default: 16;
+         *  Command Buffer Empty Locations contains the number of empty locations in the
+         *  command buffer.
+         */
+        uint32_t cmd_buf_empty_cnt:5;
+        uint32_t reserved_5:3;
+        /** resp_buf_cnt : RO; bitpos: [11:8]; default: 0;
+         *  Response Buffer Level Value contains the number of valid data entries in the
+         *  response buffer.
+         */
+        uint32_t resp_buf_cnt:4;
+        uint32_t reserved_12:4;
+        /** ibi_data_buf_cnt : RO; bitpos: [19:16]; default: 0;
+         *  IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This
+         *  is field is used in master mode.
+         */
+        uint32_t ibi_data_buf_cnt:4;
+        uint32_t reserved_20:4;
+        /** ibi_status_buf_cnt : RO; bitpos: [27:24]; default: 0;
+         *  IBI Buffer Status Count contains the number of IBI status entries in the IBI
+         *  Buffer. This field is used in master mode.
+         */
+        uint32_t ibi_status_buf_cnt:4;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i3c_mst_buffer_status_level_reg_t;
+
+
+/** Group: I3C DATA BUFFER STATUS LEVEL REG */
+/** Type of data_buffer_status_level register
+ *  DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.
+ */
+typedef union {
+    struct {
+        /** tx_data_buf_empty_cnt : RO; bitpos: [5:0]; default: 32;
+         *  Transmit Buffer Empty Level Value contains the number of empty locations in the
+         *  transmit Buffer.
+         */
+        uint32_t tx_data_buf_empty_cnt:6;
+        uint32_t reserved_6:10;
+        /** rx_data_buf_cnt : RO; bitpos: [21:16]; default: 0;
+         *  Receive Buffer Level value contains the number of valid data entries in the receive
+         *  buffer.
+         */
+        uint32_t rx_data_buf_cnt:6;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} i3c_mst_data_buffer_status_level_reg_t;
+
+
+/** Group: I3C PRESENT STATE0 REG */
+/** Type of present_state0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sda_lvl : RO; bitpos: [0]; default: 1;
+         *  This bit is used to check the SCL line level to recover from error and  for
+         *  debugging. This bit reflects the value of synchronized scl_in_a.
+         */
+        uint32_t sda_lvl:1;
+        /** scl_lvl : RO; bitpos: [1]; default: 1;
+         *  This bit is used to check the SDA line level to recover from error and  for
+         *  debugging. This bit reflects the value of synchronized sda_in_a.
+         */
+        uint32_t scl_lvl:1;
+        /** bus_busy : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t bus_busy:1;
+        /** bus_free : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t bus_free:1;
+        uint32_t reserved_4:5;
+        /** cmd_tid : RO; bitpos: [12:9]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_tid:4;
+        /** scl_gen_fsm_state : RO; bitpos: [15:13]; default: 0;
+         *  NA
+         */
+        uint32_t scl_gen_fsm_state:3;
+        /** ibi_ev_handle_fsm_state : RO; bitpos: [18:16]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_ev_handle_fsm_state:3;
+        /** i2c_mode_fsm_state : RO; bitpos: [21:19]; default: 0;
+         *  NA
+         */
+        uint32_t i2c_mode_fsm_state:3;
+        /** sdr_mode_fsm_state : RO; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t sdr_mode_fsm_state:4;
+        /** daa_mode_fsm_state : RO; bitpos: [28:26]; default: 0;
+         *  Reflects whether the Master Controller is in IDLE or not. This bit will be set when
+         *  all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the
+         *  Master State machine is in idle state. 0X0: not in idle  0x1: in idle
+         */
+        uint32_t daa_mode_fsm_state:3;
+        /** main_fsm_state : RO; bitpos: [31:29]; default: 0;
+         *  NA
+         */
+        uint32_t main_fsm_state:3;
+    };
+    uint32_t val;
+} i3c_mst_present_state0_reg_t;
+
+
+/** Group: I3C PRESENT STATE1 REG */
+/** Type of present_state1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** data_byte_cnt : RO; bitpos: [15:0]; default: 0;
+         *  Present transfer data byte cnt: tx data byte cnt if write  rx data byte cnt if read
+         *  ibi data byte cnt if IBI handle.
+         */
+        uint32_t data_byte_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_present_state1_reg_t;
+
+
+/** Group: I3C DEVICE TABLE REG */
+/** Type of device_table register
+ *  Pointer for Device Address Table
+ */
+typedef union {
+    struct {
+        /** reg_dct_daa_init_index : R/W; bitpos: [3:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dct_daa_init_index:4;
+        /** reg_dat_daa_init_index : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_daa_init_index:4;
+        /** present_dct_index : RO; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t present_dct_index:4;
+        /** present_dat_index : RO; bitpos: [15:12]; default: 0;
+         *  NA
+         */
+        uint32_t present_dat_index:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_device_table_reg_t;
+
+
+/** Group: I3C TIME OUT VALUE REG */
+/** Type of time_out_value register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_resp_buf_to_value : R/W; bitpos: [4:0]; default: 16;
+         *  NA
+         */
+        uint32_t reg_resp_buf_to_value:5;
+        /** reg_resp_buf_to_en : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_resp_buf_to_en:1;
+        /** reg_ibi_data_buf_to_value : R/W; bitpos: [10:6]; default: 16;
+         *  NA
+         */
+        uint32_t reg_ibi_data_buf_to_value:5;
+        /** reg_ibi_data_buf_to_en : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t reg_ibi_data_buf_to_en:1;
+        /** reg_ibi_status_buf_to_value : R/W; bitpos: [16:12]; default: 16;
+         *  NA
+         */
+        uint32_t reg_ibi_status_buf_to_value:5;
+        /** reg_ibi_status_buf_to_en : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t reg_ibi_status_buf_to_en:1;
+        /** reg_rx_data_buf_to_value : R/W; bitpos: [22:18]; default: 16;
+         *  NA
+         */
+        uint32_t reg_rx_data_buf_to_value:5;
+        /** reg_rx_data_buf_to_en : R/W; bitpos: [23]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rx_data_buf_to_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} i3c_mst_time_out_value_reg_t;
+
+
+/** Group: I3C SCL I3C OD TIME REG */
+/** Type of scl_i3c_mst_od_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_od_low_period : R/W; bitpos: [15:0]; default: 25;
+         *  SCL Open-Drain low count for I3C transfers targeted to I3C devices.
+         */
+        uint32_t reg_i3c_mst_od_low_period:16;
+        /** reg_i3c_mst_od_high_period : R/W; bitpos: [31:16]; default: 5;
+         *  SCL Open-Drain High count for I3C transfers targeted to I3C devices.
+         */
+        uint32_t reg_i3c_mst_od_high_period:16;
+    };
+    uint32_t val;
+} i3c_mst_scl_i3c_mst_od_time_reg_t;
+
+
+/** Group: I3C SCL I3C PP TIME REG */
+/** Type of scl_i3c_mst_pp_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_pp_low_period : R/W; bitpos: [7:0]; default: 5;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_pp_low_period:8;
+        uint32_t reserved_8:8;
+        /** reg_i3c_mst_pp_high_period : R/W; bitpos: [23:16]; default: 5;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_pp_high_period:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} i3c_mst_scl_i3c_mst_pp_time_reg_t;
+
+
+/** Group: I3C SCL I2C FM TIME REG */
+/** Type of scl_i2c_fm_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i2c_fm_low_period : R/W; bitpos: [15:0]; default: 163;
+         *  NA
+         */
+        uint32_t reg_i2c_fm_low_period:16;
+        /** reg_i2c_fm_high_period : R/W; bitpos: [31:16]; default: 75;
+         *  The SCL open-drain low count timing for I2C Fast Mode transfers.
+         */
+        uint32_t reg_i2c_fm_high_period:16;
+    };
+    uint32_t val;
+} i3c_mst_scl_i2c_fm_time_reg_t;
+
+
+/** Group: I3C SCL I2C FMP TIME REG */
+/** Type of scl_i2c_fmp_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i2c_fmp_low_period : R/W; bitpos: [15:0]; default: 63;
+         *  NA
+         */
+        uint32_t reg_i2c_fmp_low_period:16;
+        /** reg_i2c_fmp_high_period : R/W; bitpos: [23:16]; default: 33;
+         *  NA
+         */
+        uint32_t reg_i2c_fmp_high_period:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} i3c_mst_scl_i2c_fmp_time_reg_t;
+
+
+/** Group: I3C SCL EXT LOW TIME REG */
+/** Type of scl_ext_low_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_ext_low_period1 : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_ext_low_period1:8;
+        /** reg_i3c_mst_ext_low_period2 : R/W; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_ext_low_period2:8;
+        /** reg_i3c_mst_ext_low_period3 : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_ext_low_period3:8;
+        /** reg_i3c_mst_ext_low_period4 : R/W; bitpos: [31:24]; default: 0;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_ext_low_period4:8;
+    };
+    uint32_t val;
+} i3c_mst_scl_ext_low_time_reg_t;
+
+
+/** Group: I3C SDA SAMPLE TIME REG */
+/** Type of sda_sample_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sda_od_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  It is used to adjust sda sample point when scl high under open drain speed
+         */
+        uint32_t reg_sda_od_sample_time:9;
+        /** reg_sda_pp_sample_time : R/W; bitpos: [13:9]; default: 0;
+         *  It is used to adjust sda sample point when scl high under push pull speed
+         */
+        uint32_t reg_sda_pp_sample_time:5;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i3c_mst_sda_sample_time_reg_t;
+
+
+/** Group: I3C SDA HOLD TIME REG */
+/** Type of sda_hold_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sda_od_tx_hold_time : R/W; bitpos: [8:0]; default: 1;
+         *  It is used to adjust sda drive point after scl neg under open drain speed
+         */
+        uint32_t reg_sda_od_tx_hold_time:9;
+        /** reg_sda_pp_tx_hold_time : R/W; bitpos: [13:9]; default: 0;
+         *  It is used to adjust sda dirve point after scl neg under push pull speed
+         */
+        uint32_t reg_sda_pp_tx_hold_time:5;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i3c_mst_sda_hold_time_reg_t;
+
+
+/** Group: I3C SCL START HOLD REG */
+/** Type of scl_start_hold register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  I2C_SCL_START_HOLD_TIME
+         */
+        uint32_t reg_scl_start_hold_time:9;
+        /** reg_start_det_hold_time : R/W; bitpos: [10:9]; default: 0;
+         *  NA
+         */
+        uint32_t reg_start_det_hold_time:2;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} i3c_mst_scl_start_hold_reg_t;
+
+
+/** Group: I3C SCL RSTART SETUP REG */
+/** Type of scl_rstart_setup register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  I2C_SCL_RSTART_SETUP_TIME
+         */
+        uint32_t reg_scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i3c_mst_scl_rstart_setup_reg_t;
+
+
+/** Group: I3C SCL STOP HOLD REG */
+/** Type of scl_stop_hold register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  I2C_SCL_STOP_HOLD_TIME
+         */
+        uint32_t reg_scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i3c_mst_scl_stop_hold_reg_t;
+
+
+/** Group: I3C SCL STOP SETUP REG */
+/** Type of scl_stop_setup register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  I2C_SCL_STOP_SETUP_TIME
+         */
+        uint32_t reg_scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i3c_mst_scl_stop_setup_reg_t;
+
+
+/** Group: I3C BUS FREE TIME REG */
+/** Type of bus_free_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_bus_free_time : R/W; bitpos: [15:0]; default: 5;
+         *  I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus
+         *  System, this field represents tCAS.  In Mixed Bus System, this field is expected to
+         *  be programmed to tLOW of I2C Timing.
+         */
+        uint32_t reg_bus_free_time:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_bus_free_time_reg_t;
+
+
+/** Group: I3C SCL TERMN T EXT LOW TIME REG */
+/** Type of scl_termn_t_ext_low_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_termn_t_ext_low_time : R/W; bitpos: [7:0]; default: 2;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_termn_t_ext_low_time:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i3c_mst_scl_termn_t_ext_low_time_reg_t;
+
+
+/** Group: I3C VER ID REG */
+/** Type of ver_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_ver_id : R/W; bitpos: [31:0]; default: 539165956;
+         *  This field indicates the controller current release number that is read by an
+         *  application.
+         */
+        uint32_t reg_i3c_mst_ver_id:32;
+    };
+    uint32_t val;
+} i3c_mst_ver_id_reg_t;
+
+
+/** Group: I3C VER TYPE REG */
+/** Type of ver_type register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_ver_type : R/W; bitpos: [31:0]; default: 0;
+         *  This field indicates the controller current release type that is read by an
+         *  application.
+         */
+        uint32_t reg_i3c_mst_ver_type:32;
+    };
+    uint32_t val;
+} i3c_mst_ver_type_reg_t;
+
+
+/** Group: I3C FPGA DEBUG PROBE REG */
+/** Type of fpga_debug_probe register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_fpga_debug_probe : R/W; bitpos: [31:0]; default: 1;
+         *  For Debug Probe Test on FPGA
+         */
+        uint32_t reg_i3c_mst_fpga_debug_probe:32;
+    };
+    uint32_t val;
+} i3c_mst_fpga_debug_probe_reg_t;
+
+
+/** Group: I3C RND ECO CS REG */
+/** Type of rnd_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rnd_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rnd_eco_en:1;
+        /** rnd_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t rnd_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} i3c_mst_rnd_eco_cs_reg_t;
+
+
+/** Group: I3C RND ECO LOW REG */
+/** Type of rnd_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rnd_eco_low:32;
+    };
+    uint32_t val;
+} i3c_mst_rnd_eco_low_reg_t;
+
+
+/** Group: I3C RND ECO HIGH REG */
+/** Type of rnd_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rnd_eco_high : R/W; bitpos: [31:0]; default: 65535;
+         *  NA
+         */
+        uint32_t reg_rnd_eco_high:32;
+    };
+    uint32_t val;
+} i3c_mst_rnd_eco_high_reg_t;
+
+
+typedef struct i3c_mst_dev_t {
+    volatile i3c_mst_device_ctrl_reg_t device_ctrl;
+    uint32_t reserved_004[6];
+    volatile i3c_mst_buffer_thld_ctrl_reg_t buffer_thld_ctrl;
+    volatile i3c_mst_data_buffer_thld_ctrl_reg_t data_buffer_thld_ctrl;
+    volatile i3c_mst_ibi_notify_ctrl_reg_t ibi_notify_ctrl;
+    volatile i3c_mst_ibi_sir_req_payload_reg_t ibi_sir_req_payload;
+    volatile i3c_mst_ibi_sir_req_reject_reg_t ibi_sir_req_reject;
+    volatile i3c_mst_int_clr_reg_t int_clr;
+    volatile i3c_mst_int_raw_reg_t int_raw;
+    volatile i3c_mst_int_st_reg_t int_st;
+    volatile i3c_mst_int_st_ena_reg_t int_st_ena;
+    uint32_t reserved_040;
+    volatile i3c_mst_reset_ctrl_reg_t reset_ctrl;
+    volatile i3c_mst_buffer_status_level_reg_t buffer_status_level;
+    volatile i3c_mst_data_buffer_status_level_reg_t data_buffer_status_level;
+    volatile i3c_mst_present_state0_reg_t present_state0;
+    volatile i3c_mst_present_state1_reg_t present_state1;
+    volatile i3c_mst_device_table_reg_t device_table;
+    volatile i3c_mst_time_out_value_reg_t time_out_value;
+    volatile i3c_mst_scl_i3c_mst_od_time_reg_t scl_i3c_mst_od_time;
+    volatile i3c_mst_scl_i3c_mst_pp_time_reg_t scl_i3c_mst_pp_time;
+    volatile i3c_mst_scl_i2c_fm_time_reg_t scl_i2c_fm_time;
+    volatile i3c_mst_scl_i2c_fmp_time_reg_t scl_i2c_fmp_time;
+    volatile i3c_mst_scl_ext_low_time_reg_t scl_ext_low_time;
+    volatile i3c_mst_sda_sample_time_reg_t sda_sample_time;
+    volatile i3c_mst_sda_hold_time_reg_t sda_hold_time;
+    volatile i3c_mst_scl_start_hold_reg_t scl_start_hold;
+    volatile i3c_mst_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i3c_mst_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i3c_mst_scl_stop_setup_reg_t scl_stop_setup;
+    uint32_t reserved_08c;
+    volatile i3c_mst_bus_free_time_reg_t bus_free_time;
+    volatile i3c_mst_scl_termn_t_ext_low_time_reg_t scl_termn_t_ext_low_time;
+    uint32_t reserved_098[2];
+    volatile i3c_mst_ver_id_reg_t ver_id;
+    volatile i3c_mst_ver_type_reg_t ver_type;
+    uint32_t reserved_0a8;
+    volatile i3c_mst_fpga_debug_probe_reg_t fpga_debug_probe;
+    volatile i3c_mst_rnd_eco_cs_reg_t rnd_eco_cs;
+    volatile i3c_mst_rnd_eco_low_reg_t rnd_eco_low;
+    volatile i3c_mst_rnd_eco_high_reg_t rnd_eco_high;
+} i3c_mst_dev_t;
+
+extern i3c_mst_dev_t I3C_MST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i3c_mst_dev_t) == 0xbc, "Invalid size of i3c_mst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i3c_slv_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/i3c_slv_reg.h
new file mode 100644
index 0000000000..00343ef2f9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i3c_slv_reg.h
@@ -0,0 +1,585 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I3C_SLV_CONFIG_REG register
+ *  NA
+ */
+#define I3C_SLV_CONFIG_REG (DR_REG_I3C_SLV_BASE + 0x4)
+/** I3C_SLV_SLVENA : R/W; bitpos: [0]; default: 1;
+ *  1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus.
+ *  This should be not set until registers such as PARTNO, IDEXT and the like are set
+ *  1st  -if used- since they impact data to the master
+ */
+#define I3C_SLV_SLVENA    (BIT(0))
+#define I3C_SLV_SLVENA_M  (I3C_SLV_SLVENA_V << I3C_SLV_SLVENA_S)
+#define I3C_SLV_SLVENA_V  0x00000001U
+#define I3C_SLV_SLVENA_S  0
+/** I3C_SLV_NACK : R/W; bitpos: [1]; default: 0;
+ *  1:the slave will NACK all requests to it except CCC broadcast. This should be used
+ *  with caution as the Master may determine the slave is missing if overused.
+ */
+#define I3C_SLV_NACK    (BIT(1))
+#define I3C_SLV_NACK_M  (I3C_SLV_NACK_V << I3C_SLV_NACK_S)
+#define I3C_SLV_NACK_V  0x00000001U
+#define I3C_SLV_NACK_S  1
+/** I3C_SLV_MATCHSS : R/W; bitpos: [2]; default: 0;
+ *  1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This
+ *  allows START and STOP to be used to detect end of a message to /from this slave.
+ */
+#define I3C_SLV_MATCHSS    (BIT(2))
+#define I3C_SLV_MATCHSS_M  (I3C_SLV_MATCHSS_V << I3C_SLV_MATCHSS_S)
+#define I3C_SLV_MATCHSS_V  0x00000001U
+#define I3C_SLV_MATCHSS_S  2
+/** I3C_SLV_S0IGNORE : R/W; bitpos: [3]; default: 0;
+ *  If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an
+ *  Exit Pattern. This should only be used when the bus will not use HDR.
+ */
+#define I3C_SLV_S0IGNORE    (BIT(3))
+#define I3C_SLV_S0IGNORE_M  (I3C_SLV_S0IGNORE_V << I3C_SLV_S0IGNORE_S)
+#define I3C_SLV_S0IGNORE_V  0x00000001U
+#define I3C_SLV_S0IGNORE_S  3
+/** I3C_SLV_DDROK : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_DDROK    (BIT(4))
+#define I3C_SLV_DDROK_M  (I3C_SLV_DDROK_V << I3C_SLV_DDROK_S)
+#define I3C_SLV_DDROK_V  0x00000001U
+#define I3C_SLV_DDROK_S  4
+/** I3C_SLV_IDRAND : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_IDRAND    (BIT(8))
+#define I3C_SLV_IDRAND_M  (I3C_SLV_IDRAND_V << I3C_SLV_IDRAND_S)
+#define I3C_SLV_IDRAND_V  0x00000001U
+#define I3C_SLV_IDRAND_S  8
+/** I3C_SLV_OFFLINE : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_OFFLINE    (BIT(9))
+#define I3C_SLV_OFFLINE_M  (I3C_SLV_OFFLINE_V << I3C_SLV_OFFLINE_S)
+#define I3C_SLV_OFFLINE_V  0x00000001U
+#define I3C_SLV_OFFLINE_S  9
+/** I3C_SLV_BAMATCH : R/W; bitpos: [23:16]; default: 47;
+ *  Bus Available condition match value for current ???Slow clock???. This provides the
+ *  count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low
+ *  when the Master is not doing so. The max width , and so max value, is controlled by
+ *  the block. Only if enabled for events such IBI or MR or HJ, and if enabled to
+ *  provide this as a register. With is limited to CLK_SLOW_BITS
+ */
+#define I3C_SLV_BAMATCH    0x000000FFU
+#define I3C_SLV_BAMATCH_M  (I3C_SLV_BAMATCH_V << I3C_SLV_BAMATCH_S)
+#define I3C_SLV_BAMATCH_V  0x000000FFU
+#define I3C_SLV_BAMATCH_S  16
+/** I3C_SLV_SADDR : R/W; bitpos: [31:25]; default: 0;
+ *  If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled
+ *  to use one and to be provided by SW. Block may provide in HW as well.
+ */
+#define I3C_SLV_SADDR    0x0000007FU
+#define I3C_SLV_SADDR_M  (I3C_SLV_SADDR_V << I3C_SLV_SADDR_S)
+#define I3C_SLV_SADDR_V  0x0000007FU
+#define I3C_SLV_SADDR_S  25
+
+/** I3C_SLV_STATUS_REG register
+ *  NA
+ */
+#define I3C_SLV_STATUS_REG (DR_REG_I3C_SLV_BASE + 0x8)
+/** I3C_SLV_STNOTSTOP : RO; bitpos: [0]; default: 0;
+ *  Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also
+ *  set when busy. Note that this can also be true from an S0 or S1 error, which waits
+ *  for an Exit Pattern.
+ */
+#define I3C_SLV_STNOTSTOP    (BIT(0))
+#define I3C_SLV_STNOTSTOP_M  (I3C_SLV_STNOTSTOP_V << I3C_SLV_STNOTSTOP_S)
+#define I3C_SLV_STNOTSTOP_V  0x00000001U
+#define I3C_SLV_STNOTSTOP_S  0
+/** I3C_SLV_STMSG : RO; bitpos: [1]; default: 0;
+ *  Is 1 if this bus Slave is listening to the bus traffic or responding, If
+ *  STNOSTOP=1, then this will be 0 when a non-matching address seen until next
+ *  respeated START it STOP.
+ */
+#define I3C_SLV_STMSG    (BIT(1))
+#define I3C_SLV_STMSG_M  (I3C_SLV_STMSG_V << I3C_SLV_STMSG_S)
+#define I3C_SLV_STMSG_V  0x00000001U
+#define I3C_SLV_STMSG_S  1
+/** I3C_SLV_STCCCH : RO; bitpos: [2]; default: 0;
+ *  Is 1 if a CCC message is being handled automatically.
+ */
+#define I3C_SLV_STCCCH    (BIT(2))
+#define I3C_SLV_STCCCH_M  (I3C_SLV_STCCCH_V << I3C_SLV_STCCCH_S)
+#define I3C_SLV_STCCCH_V  0x00000001U
+#define I3C_SLV_STCCCH_S  2
+/** I3C_SLV_STREQRD : RO; bitpos: [3]; default: 0;
+ *  1 if the req in process is an sdr read from this slave or an IBI is being pushed
+ *  out,
+ */
+#define I3C_SLV_STREQRD    (BIT(3))
+#define I3C_SLV_STREQRD_M  (I3C_SLV_STREQRD_V << I3C_SLV_STREQRD_S)
+#define I3C_SLV_STREQRD_V  0x00000001U
+#define I3C_SLV_STREQRD_S  3
+/** I3C_SLV_STREQWR : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_STREQWR    (BIT(4))
+#define I3C_SLV_STREQWR_M  (I3C_SLV_STREQWR_V << I3C_SLV_STREQWR_S)
+#define I3C_SLV_STREQWR_V  0x00000001U
+#define I3C_SLV_STREQWR_S  4
+/** I3C_SLV_STDAA : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_STDAA    (BIT(5))
+#define I3C_SLV_STDAA_M  (I3C_SLV_STDAA_V << I3C_SLV_STDAA_S)
+#define I3C_SLV_STDAA_V  0x00000001U
+#define I3C_SLV_STDAA_S  5
+/** I3C_SLV_STHDR : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_STHDR    (BIT(6))
+#define I3C_SLV_STHDR_M  (I3C_SLV_STHDR_V << I3C_SLV_STHDR_S)
+#define I3C_SLV_STHDR_V  0x00000001U
+#define I3C_SLV_STHDR_S  6
+/** I3C_SLV_START : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_START    (BIT(8))
+#define I3C_SLV_START_M  (I3C_SLV_START_V << I3C_SLV_START_S)
+#define I3C_SLV_START_V  0x00000001U
+#define I3C_SLV_START_S  8
+/** I3C_SLV_MATCHED : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_MATCHED    (BIT(9))
+#define I3C_SLV_MATCHED_M  (I3C_SLV_MATCHED_V << I3C_SLV_MATCHED_S)
+#define I3C_SLV_MATCHED_V  0x00000001U
+#define I3C_SLV_MATCHED_S  9
+/** I3C_SLV_STOP : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_STOP    (BIT(10))
+#define I3C_SLV_STOP_M  (I3C_SLV_STOP_V << I3C_SLV_STOP_S)
+#define I3C_SLV_STOP_V  0x00000001U
+#define I3C_SLV_STOP_S  10
+/** I3C_SLV_RXPEND : RO; bitpos: [11]; default: 0;
+ *  Receiving a message from master,which is not being handled by block(not a CCC
+ *  internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which
+ *  defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will
+ *  self-clear if data is read(FIFO and non-FIFO)
+ */
+#define I3C_SLV_RXPEND    (BIT(11))
+#define I3C_SLV_RXPEND_M  (I3C_SLV_RXPEND_V << I3C_SLV_RXPEND_S)
+#define I3C_SLV_RXPEND_V  0x00000001U
+#define I3C_SLV_RXPEND_S  11
+/** I3C_SLV_TXNOTFULL : RO; bitpos: [12]; default: 0;
+ *  Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all
+ *  but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is
+ *  enabled for TX, it will also be signaled to provide more.
+ */
+#define I3C_SLV_TXNOTFULL    (BIT(12))
+#define I3C_SLV_TXNOTFULL_M  (I3C_SLV_TXNOTFULL_V << I3C_SLV_TXNOTFULL_S)
+#define I3C_SLV_TXNOTFULL_V  0x00000001U
+#define I3C_SLV_TXNOTFULL_S  12
+/** I3C_SLV_DACHG : R/W; bitpos: [13]; default: 0;
+ *  The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in
+ *  that state of being valid or none. Actual DA can be seen in the DYNADDR register.
+ *  Note that this will also be used when MAP Auto feature is configured. This will be
+ *  changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main
+ *  DA(0) will indicate if last change was due to Auto MAP.
+ */
+#define I3C_SLV_DACHG    (BIT(13))
+#define I3C_SLV_DACHG_M  (I3C_SLV_DACHG_V << I3C_SLV_DACHG_S)
+#define I3C_SLV_DACHG_V  0x00000001U
+#define I3C_SLV_DACHG_S  13
+/** I3C_SLV_CCC : R/W; bitpos: [14]; default: 0;
+ *  A common -command-code(CCC), not handled by block, has been received. This acts
+ *  differently between: *Broadcasted ones, which will then also correspond with RXPEND
+ *  and the 1st byte will be the CCC(command) . *Direct ones, which may never be
+ *  directed to this device.  If it is, then the TXSEND or RXPEND will be triggered
+ *  with this end the RXPEND will contain the command.
+ */
+#define I3C_SLV_CCC    (BIT(14))
+#define I3C_SLV_CCC_M  (I3C_SLV_CCC_V << I3C_SLV_CCC_S)
+#define I3C_SLV_CCC_V  0x00000001U
+#define I3C_SLV_CCC_S  14
+/** I3C_SLV_ERRWARN : RO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_ERRWARN    (BIT(15))
+#define I3C_SLV_ERRWARN_M  (I3C_SLV_ERRWARN_V << I3C_SLV_ERRWARN_S)
+#define I3C_SLV_ERRWARN_V  0x00000001U
+#define I3C_SLV_ERRWARN_S  15
+/** I3C_SLV_HDRMATCH : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_HDRMATCH    (BIT(16))
+#define I3C_SLV_HDRMATCH_M  (I3C_SLV_HDRMATCH_V << I3C_SLV_HDRMATCH_S)
+#define I3C_SLV_HDRMATCH_V  0x00000001U
+#define I3C_SLV_HDRMATCH_S  16
+
+/** I3C_SLV_CTRL_REG register
+ *  NA
+ */
+#define I3C_SLV_CTRL_REG (DR_REG_I3C_SLV_BASE + 0xc)
+/** I3C_SLV_SLV_EVENT : R/W; bitpos: [1:0]; default: 0;
+ *  If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will
+ *  show the status as it progresses. Once completed, the field will automatically
+ *  return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal
+ *  mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1:
+ *  start an IBI. This will try to push through an IBI on the bus. If data associate
+ *  with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is
+ *  enabled, this will include anytime control related bytes  further, the IBIDATA byte
+ *  will have bit7 set to 1.
+ */
+#define I3C_SLV_SLV_EVENT    0x00000003U
+#define I3C_SLV_SLV_EVENT_M  (I3C_SLV_SLV_EVENT_V << I3C_SLV_SLV_EVENT_S)
+#define I3C_SLV_SLV_EVENT_V  0x00000003U
+#define I3C_SLV_SLV_EVENT_S  0
+/** I3C_SLV_EXTDATA : R/W; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define I3C_SLV_EXTDATA    (BIT(3))
+#define I3C_SLV_EXTDATA_M  (I3C_SLV_EXTDATA_V << I3C_SLV_EXTDATA_S)
+#define I3C_SLV_EXTDATA_V  0x00000001U
+#define I3C_SLV_EXTDATA_S  3
+/** I3C_SLV_MAPIDX : R/W; bitpos: [7:4]; default: 0;
+ *  Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic
+ *  Address, or can be any valid index.
+ */
+#define I3C_SLV_MAPIDX    0x0000000FU
+#define I3C_SLV_MAPIDX_M  (I3C_SLV_MAPIDX_V << I3C_SLV_MAPIDX_S)
+#define I3C_SLV_MAPIDX_V  0x0000000FU
+#define I3C_SLV_MAPIDX_S  4
+/** I3C_SLV_IBIDATA : R/W; bitpos: [15:8]; default: 0;
+ *  Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is
+ *  required.
+ */
+#define I3C_SLV_IBIDATA    0x000000FFU
+#define I3C_SLV_IBIDATA_M  (I3C_SLV_IBIDATA_V << I3C_SLV_IBIDATA_S)
+#define I3C_SLV_IBIDATA_V  0x000000FFU
+#define I3C_SLV_IBIDATA_S  8
+/** I3C_SLV_PENDINT : R/W; bitpos: [19:16]; default: 0;
+ *  Should be set to the pending interrupt that GETSTATUS CCC will return. This should
+ *  be maintained by the application if used and configured, as the Master will read
+ *  this. If not configured, the GETSTATUS field will return 1 if an IBI is pending,
+ *  and 0 otherwise.
+ */
+#define I3C_SLV_PENDINT    0x0000000FU
+#define I3C_SLV_PENDINT_M  (I3C_SLV_PENDINT_V << I3C_SLV_PENDINT_S)
+#define I3C_SLV_PENDINT_V  0x0000000FU
+#define I3C_SLV_PENDINT_S  16
+/** I3C_SLV_ACTSTATE : R/W; bitpos: [21:20]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_ACTSTATE    0x00000003U
+#define I3C_SLV_ACTSTATE_M  (I3C_SLV_ACTSTATE_V << I3C_SLV_ACTSTATE_S)
+#define I3C_SLV_ACTSTATE_V  0x00000003U
+#define I3C_SLV_ACTSTATE_S  20
+/** I3C_SLV_VENDINFO : R/W; bitpos: [31:24]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_VENDINFO    0x000000FFU
+#define I3C_SLV_VENDINFO_M  (I3C_SLV_VENDINFO_V << I3C_SLV_VENDINFO_S)
+#define I3C_SLV_VENDINFO_V  0x000000FFU
+#define I3C_SLV_VENDINFO_S  24
+
+/** I3C_SLV_INTSET_REG register
+ *  INSET allows setting enables for interrupts(connecting the corresponding STATUS
+ *  source to causing an IRQ to the processor)
+ */
+#define I3C_SLV_INTSET_REG (DR_REG_I3C_SLV_BASE + 0x10)
+/** I3C_SLV_STOP_ENA : R/W; bitpos: [10]; default: 0;
+ *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+ *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+ *  relates to the state of being stopped.
+ */
+#define I3C_SLV_STOP_ENA    (BIT(10))
+#define I3C_SLV_STOP_ENA_M  (I3C_SLV_STOP_ENA_V << I3C_SLV_STOP_ENA_S)
+#define I3C_SLV_STOP_ENA_V  0x00000001U
+#define I3C_SLV_STOP_ENA_S  10
+/** I3C_SLV_RXPEND_ENA : R/W; bitpos: [11]; default: 0;
+ *  Interrupt when receiving a message from Master, which is not being handled by the
+ *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+ *  trigger. If DMA, then message end.
+ */
+#define I3C_SLV_RXPEND_ENA    (BIT(11))
+#define I3C_SLV_RXPEND_ENA_M  (I3C_SLV_RXPEND_ENA_V << I3C_SLV_RXPEND_ENA_S)
+#define I3C_SLV_RXPEND_ENA_V  0x00000001U
+#define I3C_SLV_RXPEND_ENA_S  11
+/** I3C_SLV_TXSEND_ENA : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_TXSEND_ENA    (BIT(12))
+#define I3C_SLV_TXSEND_ENA_M  (I3C_SLV_TXSEND_ENA_V << I3C_SLV_TXSEND_ENA_S)
+#define I3C_SLV_TXSEND_ENA_V  0x00000001U
+#define I3C_SLV_TXSEND_ENA_S  12
+
+/** I3C_SLV_INTCLR_REG register
+ *  NA
+ */
+#define I3C_SLV_INTCLR_REG (DR_REG_I3C_SLV_BASE + 0x14)
+/** I3C_SLV_STOP_CLR : WO; bitpos: [10]; default: 0;
+ *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+ *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+ *  relates to the state of being stopped.
+ */
+#define I3C_SLV_STOP_CLR    (BIT(10))
+#define I3C_SLV_STOP_CLR_M  (I3C_SLV_STOP_CLR_V << I3C_SLV_STOP_CLR_S)
+#define I3C_SLV_STOP_CLR_V  0x00000001U
+#define I3C_SLV_STOP_CLR_S  10
+/** I3C_SLV_RXPEND_CLR : WO; bitpos: [11]; default: 0;
+ *  Interrupt when receiving a message from Master, which is not being handled by the
+ *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+ *  trigger. If DMA, then message end.
+ */
+#define I3C_SLV_RXPEND_CLR    (BIT(11))
+#define I3C_SLV_RXPEND_CLR_M  (I3C_SLV_RXPEND_CLR_V << I3C_SLV_RXPEND_CLR_S)
+#define I3C_SLV_RXPEND_CLR_V  0x00000001U
+#define I3C_SLV_RXPEND_CLR_S  11
+/** I3C_SLV_TXSEND_CLR : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_TXSEND_CLR    (BIT(12))
+#define I3C_SLV_TXSEND_CLR_M  (I3C_SLV_TXSEND_CLR_V << I3C_SLV_TXSEND_CLR_S)
+#define I3C_SLV_TXSEND_CLR_V  0x00000001U
+#define I3C_SLV_TXSEND_CLR_S  12
+
+/** I3C_SLV_INTMASKED_REG register
+ *  NA
+ */
+#define I3C_SLV_INTMASKED_REG (DR_REG_I3C_SLV_BASE + 0x18)
+/** I3C_SLV_STOP_MASK : RO; bitpos: [10]; default: 0;
+ *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+ *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+ *  relates to the state of being stopped.
+ */
+#define I3C_SLV_STOP_MASK    (BIT(10))
+#define I3C_SLV_STOP_MASK_M  (I3C_SLV_STOP_MASK_V << I3C_SLV_STOP_MASK_S)
+#define I3C_SLV_STOP_MASK_V  0x00000001U
+#define I3C_SLV_STOP_MASK_S  10
+/** I3C_SLV_RXPEND_MASK : RO; bitpos: [11]; default: 0;
+ *  Interrupt when receiving a message from Master, which is not being handled by the
+ *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+ *  trigger. If DMA, then message end.
+ */
+#define I3C_SLV_RXPEND_MASK    (BIT(11))
+#define I3C_SLV_RXPEND_MASK_M  (I3C_SLV_RXPEND_MASK_V << I3C_SLV_RXPEND_MASK_S)
+#define I3C_SLV_RXPEND_MASK_V  0x00000001U
+#define I3C_SLV_RXPEND_MASK_S  11
+/** I3C_SLV_TXSEND_MASK : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_TXSEND_MASK    (BIT(12))
+#define I3C_SLV_TXSEND_MASK_M  (I3C_SLV_TXSEND_MASK_V << I3C_SLV_TXSEND_MASK_S)
+#define I3C_SLV_TXSEND_MASK_V  0x00000001U
+#define I3C_SLV_TXSEND_MASK_S  12
+
+/** I3C_SLV_DATACTRL_REG register
+ *  NA
+ */
+#define I3C_SLV_DATACTRL_REG (DR_REG_I3C_SLV_BASE + 0x2c)
+/** I3C_SLV_FLUSHTB : WO; bitpos: [0]; default: 0;
+ *  Flushes the from-bus buffer/FIFO. Not normally used
+ */
+#define I3C_SLV_FLUSHTB    (BIT(0))
+#define I3C_SLV_FLUSHTB_M  (I3C_SLV_FLUSHTB_V << I3C_SLV_FLUSHTB_S)
+#define I3C_SLV_FLUSHTB_V  0x00000001U
+#define I3C_SLV_FLUSHTB_S  0
+/** I3C_SLV_FLUSHFB : WO; bitpos: [1]; default: 0;
+ *  Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message
+ *  prematurely
+ */
+#define I3C_SLV_FLUSHFB    (BIT(1))
+#define I3C_SLV_FLUSHFB_M  (I3C_SLV_FLUSHFB_V << I3C_SLV_FLUSHFB_S)
+#define I3C_SLV_FLUSHFB_V  0x00000001U
+#define I3C_SLV_FLUSHFB_S  1
+/** I3C_SLV_UNLOCK : WO; bitpos: [3]; default: 0;
+ *  If this bit is not written 1, the register bits from 7 to 4 are not changed on
+ *  write.
+ */
+#define I3C_SLV_UNLOCK    (BIT(3))
+#define I3C_SLV_UNLOCK_M  (I3C_SLV_UNLOCK_V << I3C_SLV_UNLOCK_S)
+#define I3C_SLV_UNLOCK_V  0x00000001U
+#define I3C_SLV_UNLOCK_S  3
+/** I3C_SLV_TXTRIG : R/W; bitpos: [5:4]; default: 3;
+ *  Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled).
+ *  The defaults is 3
+ */
+#define I3C_SLV_TXTRIG    0x00000003U
+#define I3C_SLV_TXTRIG_M  (I3C_SLV_TXTRIG_V << I3C_SLV_TXTRIG_S)
+#define I3C_SLV_TXTRIG_V  0x00000003U
+#define I3C_SLV_TXTRIG_S  4
+/** I3C_SLV_RXTRIG : R/W; bitpos: [7:6]; default: 2;
+ *  Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled).
+ *  The defaults is 3
+ */
+#define I3C_SLV_RXTRIG    0x00000003U
+#define I3C_SLV_RXTRIG_M  (I3C_SLV_RXTRIG_V << I3C_SLV_RXTRIG_S)
+#define I3C_SLV_RXTRIG_V  0x00000003U
+#define I3C_SLV_RXTRIG_S  6
+/** I3C_SLV_TXCOUNT : RO; bitpos: [20:16]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_TXCOUNT    0x0000001FU
+#define I3C_SLV_TXCOUNT_M  (I3C_SLV_TXCOUNT_V << I3C_SLV_TXCOUNT_S)
+#define I3C_SLV_TXCOUNT_V  0x0000001FU
+#define I3C_SLV_TXCOUNT_S  16
+/** I3C_SLV_RXCOUNT : RO; bitpos: [28:24]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_RXCOUNT    0x0000001FU
+#define I3C_SLV_RXCOUNT_M  (I3C_SLV_RXCOUNT_V << I3C_SLV_RXCOUNT_S)
+#define I3C_SLV_RXCOUNT_V  0x0000001FU
+#define I3C_SLV_RXCOUNT_S  24
+/** I3C_SLV_TXFULL : RO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_TXFULL    (BIT(30))
+#define I3C_SLV_TXFULL_M  (I3C_SLV_TXFULL_V << I3C_SLV_TXFULL_S)
+#define I3C_SLV_TXFULL_V  0x00000001U
+#define I3C_SLV_TXFULL_S  30
+/** I3C_SLV_RXEMPTY : RO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_RXEMPTY    (BIT(31))
+#define I3C_SLV_RXEMPTY_M  (I3C_SLV_RXEMPTY_V << I3C_SLV_RXEMPTY_S)
+#define I3C_SLV_RXEMPTY_V  0x00000001U
+#define I3C_SLV_RXEMPTY_S  31
+
+/** I3C_SLV_WDATAB_REG register
+ *  NA
+ */
+#define I3C_SLV_WDATAB_REG (DR_REG_I3C_SLV_BASE + 0x30)
+/** I3C_SLV_WDATAB : WO; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_WDATAB    0x000000FFU
+#define I3C_SLV_WDATAB_M  (I3C_SLV_WDATAB_V << I3C_SLV_WDATAB_S)
+#define I3C_SLV_WDATAB_V  0x000000FFU
+#define I3C_SLV_WDATAB_S  0
+/** I3C_SLV_WDATA_END : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_WDATA_END    (BIT(8))
+#define I3C_SLV_WDATA_END_M  (I3C_SLV_WDATA_END_V << I3C_SLV_WDATA_END_S)
+#define I3C_SLV_WDATA_END_V  0x00000001U
+#define I3C_SLV_WDATA_END_S  8
+
+/** I3C_SLV_WDATABE_REG register
+ *  NA
+ */
+#define I3C_SLV_WDATABE_REG (DR_REG_I3C_SLV_BASE + 0x34)
+/** I3C_SLV_WDATABE : WO; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_WDATABE    0x000000FFU
+#define I3C_SLV_WDATABE_M  (I3C_SLV_WDATABE_V << I3C_SLV_WDATABE_S)
+#define I3C_SLV_WDATABE_V  0x000000FFU
+#define I3C_SLV_WDATABE_S  0
+
+/** I3C_SLV_RDARAB_REG register
+ *  Read Byte Data (from-bus) register
+ */
+#define I3C_SLV_RDARAB_REG (DR_REG_I3C_SLV_BASE + 0x40)
+/** I3C_SLV_DATA0 : RO; bitpos: [7:0]; default: 0;
+ *  This register allows reading a byte from the bus unless external FIFO is used. A
+ *  byte should not be read unless there is data waiting, as indicated by the RXPEND
+ *  bit being set in the STATUS register
+ */
+#define I3C_SLV_DATA0    0x000000FFU
+#define I3C_SLV_DATA0_M  (I3C_SLV_DATA0_V << I3C_SLV_DATA0_S)
+#define I3C_SLV_DATA0_V  0x000000FFU
+#define I3C_SLV_DATA0_S  0
+
+/** I3C_SLV_RDATAH_REG register
+ *  Read Half-word Data (from-bus) register
+ */
+#define I3C_SLV_RDATAH_REG (DR_REG_I3C_SLV_BASE + 0x48)
+/** I3C_SLV_DATA_LSB : RO; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_DATA_LSB    0x000000FFU
+#define I3C_SLV_DATA_LSB_M  (I3C_SLV_DATA_LSB_V << I3C_SLV_DATA_LSB_S)
+#define I3C_SLV_DATA_LSB_V  0x000000FFU
+#define I3C_SLV_DATA_LSB_S  0
+/** I3C_SLV_DATA_MSB : RO; bitpos: [15:8]; default: 0;
+ *  This register allows reading a Half-word (byte pair)  from the bus unless external
+ *  FIFO is used. A Half-word should not be read unless there is at least 2 bytes of
+ *  data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space
+ *  in the DATACTRL register
+ */
+#define I3C_SLV_DATA_MSB    0x000000FFU
+#define I3C_SLV_DATA_MSB_M  (I3C_SLV_DATA_MSB_V << I3C_SLV_DATA_MSB_S)
+#define I3C_SLV_DATA_MSB_V  0x000000FFU
+#define I3C_SLV_DATA_MSB_S  8
+
+/** I3C_SLV_CAPABILITIES2_REG register
+ *  NA
+ */
+#define I3C_SLV_CAPABILITIES2_REG (DR_REG_I3C_SLV_BASE + 0x5c)
+/** I3C_SLV_CAPABLITIES2 : RO; bitpos: [31:0]; default: 256;
+ *  NA
+ */
+#define I3C_SLV_CAPABLITIES2    0xFFFFFFFFU
+#define I3C_SLV_CAPABLITIES2_M  (I3C_SLV_CAPABLITIES2_V << I3C_SLV_CAPABLITIES2_S)
+#define I3C_SLV_CAPABLITIES2_V  0xFFFFFFFFU
+#define I3C_SLV_CAPABLITIES2_S  0
+
+/** I3C_SLV_CAPABILITIES_REG register
+ *  NA
+ */
+#define I3C_SLV_CAPABILITIES_REG (DR_REG_I3C_SLV_BASE + 0x60)
+/** I3C_SLV_CAPABLITIES : RO; bitpos: [31:0]; default: 2081684508;
+ *  NA
+ */
+#define I3C_SLV_CAPABLITIES    0xFFFFFFFFU
+#define I3C_SLV_CAPABLITIES_M  (I3C_SLV_CAPABLITIES_V << I3C_SLV_CAPABLITIES_S)
+#define I3C_SLV_CAPABLITIES_V  0xFFFFFFFFU
+#define I3C_SLV_CAPABLITIES_S  0
+
+/** I3C_SLV_IDPARTNO_REG register
+ *  NA
+ */
+#define I3C_SLV_IDPARTNO_REG (DR_REG_I3C_SLV_BASE + 0x6c)
+/** I3C_SLV_PARTNO : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_PARTNO    0xFFFFFFFFU
+#define I3C_SLV_PARTNO_M  (I3C_SLV_PARTNO_V << I3C_SLV_PARTNO_S)
+#define I3C_SLV_PARTNO_V  0xFFFFFFFFU
+#define I3C_SLV_PARTNO_S  0
+
+/** I3C_SLV_IDEXT_REG register
+ *  NA
+ */
+#define I3C_SLV_IDEXT_REG (DR_REG_I3C_SLV_BASE + 0x70)
+/** I3C_SLV_IDEXT : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_IDEXT    0xFFFFFFFFU
+#define I3C_SLV_IDEXT_M  (I3C_SLV_IDEXT_V << I3C_SLV_IDEXT_S)
+#define I3C_SLV_IDEXT_V  0xFFFFFFFFU
+#define I3C_SLV_IDEXT_S  0
+
+/** I3C_SLV_VENDORID_REG register
+ *  NA
+ */
+#define I3C_SLV_VENDORID_REG (DR_REG_I3C_SLV_BASE + 0x74)
+/** I3C_SLV_VID : R/W; bitpos: [14:0]; default: 21840;
+ *  NA
+ */
+#define I3C_SLV_VID    0x00007FFFU
+#define I3C_SLV_VID_M  (I3C_SLV_VID_V << I3C_SLV_VID_S)
+#define I3C_SLV_VID_V  0x00007FFFU
+#define I3C_SLV_VID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i3c_slv_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i3c_slv_struct.h
new file mode 100644
index 0000000000..dd95aff933
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/i3c_slv_struct.h
@@ -0,0 +1,550 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: I3C_SLV CONFIG REG */
+/** Type of config register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** slvena : R/W; bitpos: [0]; default: 1;
+         *  1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus.
+         *  This should be not set until registers such as PARTNO, IDEXT and the like are set
+         *  1st  -if used- since they impact data to the master
+         */
+        uint32_t slvena:1;
+        /** nack : R/W; bitpos: [1]; default: 0;
+         *  1:the slave will NACK all requests to it except CCC broadcast. This should be used
+         *  with caution as the Master may determine the slave is missing if overused.
+         */
+        uint32_t nack:1;
+        /** matchss : R/W; bitpos: [2]; default: 0;
+         *  1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This
+         *  allows START and STOP to be used to detect end of a message to /from this slave.
+         */
+        uint32_t matchss:1;
+        /** s0ignore : R/W; bitpos: [3]; default: 0;
+         *  If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an
+         *  Exit Pattern. This should only be used when the bus will not use HDR.
+         */
+        uint32_t s0ignore:1;
+        /** ddrok : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ddrok:1;
+        uint32_t reserved_5:3;
+        /** idrand : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t idrand:1;
+        /** offline : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t offline:1;
+        uint32_t reserved_10:6;
+        /** bamatch : R/W; bitpos: [23:16]; default: 47;
+         *  Bus Available condition match value for current ???Slow clock???. This provides the
+         *  count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low
+         *  when the Master is not doing so. The max width , and so max value, is controlled by
+         *  the block. Only if enabled for events such IBI or MR or HJ, and if enabled to
+         *  provide this as a register. With is limited to CLK_SLOW_BITS
+         */
+        uint32_t bamatch:8;
+        uint32_t reserved_24:1;
+        /** saddr : R/W; bitpos: [31:25]; default: 0;
+         *  If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled
+         *  to use one and to be provided by SW. Block may provide in HW as well.
+         */
+        uint32_t saddr:7;
+    };
+    uint32_t val;
+} i3c_slv_config_reg_t;
+
+
+/** Group: I3C_SLV STATUS REG */
+/** Type of status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** stnotstop : RO; bitpos: [0]; default: 0;
+         *  Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also
+         *  set when busy. Note that this can also be true from an S0 or S1 error, which waits
+         *  for an Exit Pattern.
+         */
+        uint32_t stnotstop:1;
+        /** stmsg : RO; bitpos: [1]; default: 0;
+         *  Is 1 if this bus Slave is listening to the bus traffic or responding, If
+         *  STNOSTOP=1, then this will be 0 when a non-matching address seen until next
+         *  respeated START it STOP.
+         */
+        uint32_t stmsg:1;
+        /** stccch : RO; bitpos: [2]; default: 0;
+         *  Is 1 if a CCC message is being handled automatically.
+         */
+        uint32_t stccch:1;
+        /** streqrd : RO; bitpos: [3]; default: 0;
+         *  1 if the req in process is an sdr read from this slave or an IBI is being pushed
+         *  out,
+         */
+        uint32_t streqrd:1;
+        /** streqwr : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t streqwr:1;
+        /** stdaa : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t stdaa:1;
+        /** sthdr : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t sthdr:1;
+        uint32_t reserved_7:1;
+        /** start : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t start:1;
+        /** matched : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t matched:1;
+        /** stop : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t stop:1;
+        /** rxpend : RO; bitpos: [11]; default: 0;
+         *  Receiving a message from master,which is not being handled by block(not a CCC
+         *  internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which
+         *  defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will
+         *  self-clear if data is read(FIFO and non-FIFO)
+         */
+        uint32_t rxpend:1;
+        /** txnotfull : RO; bitpos: [12]; default: 0;
+         *  Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all
+         *  but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is
+         *  enabled for TX, it will also be signaled to provide more.
+         */
+        uint32_t txnotfull:1;
+        /** dachg : R/W; bitpos: [13]; default: 0;
+         *  The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in
+         *  that state of being valid or none. Actual DA can be seen in the DYNADDR register.
+         *  Note that this will also be used when MAP Auto feature is configured. This will be
+         *  changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main
+         *  DA(0) will indicate if last change was due to Auto MAP.
+         */
+        uint32_t dachg:1;
+        /** ccc : R/W; bitpos: [14]; default: 0;
+         *  A common -command-code(CCC), not handled by block, has been received. This acts
+         *  differently between: *Broadcasted ones, which will then also correspond with RXPEND
+         *  and the 1st byte will be the CCC(command) . *Direct ones, which may never be
+         *  directed to this device.  If it is, then the TXSEND or RXPEND will be triggered
+         *  with this end the RXPEND will contain the command.
+         */
+        uint32_t ccc:1;
+        /** errwarn : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t errwarn:1;
+        /** hdrmatch : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t hdrmatch:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} i3c_slv_status_reg_t;
+
+
+/** Group: I3C_SLV CTRL REG */
+/** Type of ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** slv_event : R/W; bitpos: [1:0]; default: 0;
+         *  If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will
+         *  show the status as it progresses. Once completed, the field will automatically
+         *  return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal
+         *  mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1:
+         *  start an IBI. This will try to push through an IBI on the bus. If data associate
+         *  with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is
+         *  enabled, this will include anytime control related bytes  further, the IBIDATA byte
+         *  will have bit7 set to 1.
+         */
+        uint32_t slv_event:2;
+        uint32_t reserved_2:1;
+        /** extdata : R/W; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t extdata:1;
+        /** mapidx : R/W; bitpos: [7:4]; default: 0;
+         *  Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic
+         *  Address, or can be any valid index.
+         */
+        uint32_t mapidx:4;
+        /** ibidata : R/W; bitpos: [15:8]; default: 0;
+         *  Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is
+         *  required.
+         */
+        uint32_t ibidata:8;
+        /** pendint : R/W; bitpos: [19:16]; default: 0;
+         *  Should be set to the pending interrupt that GETSTATUS CCC will return. This should
+         *  be maintained by the application if used and configured, as the Master will read
+         *  this. If not configured, the GETSTATUS field will return 1 if an IBI is pending,
+         *  and 0 otherwise.
+         */
+        uint32_t pendint:4;
+        /** actstate : R/W; bitpos: [21:20]; default: 0;
+         *  NA
+         */
+        uint32_t actstate:2;
+        uint32_t reserved_22:2;
+        /** vendinfo : R/W; bitpos: [31:24]; default: 0;
+         *  NA
+         */
+        uint32_t vendinfo:8;
+    };
+    uint32_t val;
+} i3c_slv_ctrl_reg_t;
+
+
+/** Group: I3C_SLV INTSET REG */
+/** Type of intset register
+ *  INSET allows setting enables for interrupts(connecting the corresponding STATUS
+ *  source to causing an IRQ to the processor)
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** stop_ena : R/W; bitpos: [10]; default: 0;
+         *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+         *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+         *  relates to the state of being stopped.
+         */
+        uint32_t stop_ena:1;
+        /** rxpend_ena : R/W; bitpos: [11]; default: 0;
+         *  Interrupt when receiving a message from Master, which is not being handled by the
+         *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+         *  trigger. If DMA, then message end.
+         */
+        uint32_t rxpend_ena:1;
+        /** txsend_ena : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t txsend_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} i3c_slv_intset_reg_t;
+
+
+/** Group: I3C_SLV INTCLR REG */
+/** Type of intclr register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** stop_clr : WO; bitpos: [10]; default: 0;
+         *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+         *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+         *  relates to the state of being stopped.
+         */
+        uint32_t stop_clr:1;
+        /** rxpend_clr : WO; bitpos: [11]; default: 0;
+         *  Interrupt when receiving a message from Master, which is not being handled by the
+         *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+         *  trigger. If DMA, then message end.
+         */
+        uint32_t rxpend_clr:1;
+        /** txsend_clr : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t txsend_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} i3c_slv_intclr_reg_t;
+
+
+/** Group: I3C_SLV INTMASKED REG */
+/** Type of intmasked register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** stop_mask : RO; bitpos: [10]; default: 0;
+         *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+         *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+         *  relates to the state of being stopped.
+         */
+        uint32_t stop_mask:1;
+        /** rxpend_mask : RO; bitpos: [11]; default: 0;
+         *  Interrupt when receiving a message from Master, which is not being handled by the
+         *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+         *  trigger. If DMA, then message end.
+         */
+        uint32_t rxpend_mask:1;
+        /** txsend_mask : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t txsend_mask:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} i3c_slv_intmasked_reg_t;
+
+
+/** Group: I3C_SLV DATACTRL REG */
+/** Type of datactrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** flushtb : WO; bitpos: [0]; default: 0;
+         *  Flushes the from-bus buffer/FIFO. Not normally used
+         */
+        uint32_t flushtb:1;
+        /** flushfb : WO; bitpos: [1]; default: 0;
+         *  Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message
+         *  prematurely
+         */
+        uint32_t flushfb:1;
+        uint32_t reserved_2:1;
+        /** unlock : WO; bitpos: [3]; default: 0;
+         *  If this bit is not written 1, the register bits from 7 to 4 are not changed on
+         *  write.
+         */
+        uint32_t unlock:1;
+        /** txtrig : R/W; bitpos: [5:4]; default: 3;
+         *  Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled).
+         *  The defaults is 3
+         */
+        uint32_t txtrig:2;
+        /** rxtrig : R/W; bitpos: [7:6]; default: 2;
+         *  Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled).
+         *  The defaults is 3
+         */
+        uint32_t rxtrig:2;
+        uint32_t reserved_8:8;
+        /** txcount : RO; bitpos: [20:16]; default: 0;
+         *  NA
+         */
+        uint32_t txcount:5;
+        uint32_t reserved_21:3;
+        /** rxcount : RO; bitpos: [28:24]; default: 0;
+         *  NA
+         */
+        uint32_t rxcount:5;
+        uint32_t reserved_29:1;
+        /** txfull : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t txfull:1;
+        /** rxempty : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t rxempty:1;
+    };
+    uint32_t val;
+} i3c_slv_datactrl_reg_t;
+
+
+/** Group: I3C_SLV WDATAB REG */
+/** Type of wdatab register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** wdatab : WO; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t wdatab:8;
+        /** wdata_end : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t wdata_end:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i3c_slv_wdatab_reg_t;
+
+
+/** Group: I3C_SLV WDATABE REG */
+/** Type of wdatabe register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** wdatabe : WO; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t wdatabe:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i3c_slv_wdatabe_reg_t;
+
+
+/** Group: I3C_SLV RDARAB REG */
+/** Type of rdarab register
+ *  Read Byte Data (from-bus) register
+ */
+typedef union {
+    struct {
+        /** data0 : RO; bitpos: [7:0]; default: 0;
+         *  This register allows reading a byte from the bus unless external FIFO is used. A
+         *  byte should not be read unless there is data waiting, as indicated by the RXPEND
+         *  bit being set in the STATUS register
+         */
+        uint32_t data0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i3c_slv_rdarab_reg_t;
+
+
+/** Group: I3C_SLV RDATAH REG */
+/** Type of rdatah register
+ *  Read Half-word Data (from-bus) register
+ */
+typedef union {
+    struct {
+        /** data_lsb : RO; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t data_lsb:8;
+        /** data_msb : RO; bitpos: [15:8]; default: 0;
+         *  This register allows reading a Half-word (byte pair)  from the bus unless external
+         *  FIFO is used. A Half-word should not be read unless there is at least 2 bytes of
+         *  data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space
+         *  in the DATACTRL register
+         */
+        uint32_t data_msb:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_slv_rdatah_reg_t;
+
+
+/** Group: I3C_SLV CAPABILITIES2 REG */
+/** Type of capabilities2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** capablities2 : RO; bitpos: [31:0]; default: 256;
+         *  NA
+         */
+        uint32_t capablities2:32;
+    };
+    uint32_t val;
+} i3c_slv_capabilities2_reg_t;
+
+
+/** Group: I3C_SLV CAPABILITIES REG */
+/** Type of capabilities register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** capabilities : RO; bitpos: [31:0]; default: 2081684508;
+         *  NA
+         */
+        uint32_t capabilities:32;
+    };
+    uint32_t val;
+} i3c_slv_capabilities_reg_t;
+
+
+/** Group: I3C_SLV IDPARTNO REG */
+/** Type of idpartno register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** partno : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t partno:32;
+    };
+    uint32_t val;
+} i3c_slv_idpartno_reg_t;
+
+
+/** Group: I3C_SLV IDEXT REG */
+/** Type of idext register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** idext : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t idext:32;
+    };
+    uint32_t val;
+} i3c_slv_idext_reg_t;
+
+
+/** Group: I3C_SLV VENDORID REG */
+/** Type of vendorid register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid : R/W; bitpos: [14:0]; default: 21840;
+         *  NA
+         */
+        uint32_t vid:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i3c_slv_vendorid_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile i3c_slv_config_reg_t config;
+    volatile i3c_slv_status_reg_t status;
+    volatile i3c_slv_ctrl_reg_t ctrl;
+    volatile i3c_slv_intset_reg_t intset;
+    volatile i3c_slv_intclr_reg_t intclr;
+    volatile i3c_slv_intmasked_reg_t intmasked;
+    uint32_t reserved_01c[4];
+    volatile i3c_slv_datactrl_reg_t datactrl;
+    volatile i3c_slv_wdatab_reg_t wdatab;
+    volatile i3c_slv_wdatabe_reg_t wdatabe;
+    uint32_t reserved_038[2];
+    volatile i3c_slv_rdarab_reg_t rdarab;
+    uint32_t reserved_044;
+    volatile i3c_slv_rdatah_reg_t rdatah;
+    uint32_t reserved_04c[4];
+    volatile i3c_slv_capabilities2_reg_t capabilities2;
+    volatile i3c_slv_capabilities_reg_t capabilities;
+    uint32_t reserved_064[2];
+    volatile i3c_slv_idpartno_reg_t idpartno;
+    volatile i3c_slv_idext_reg_t idext;
+    volatile i3c_slv_vendorid_reg_t vendorid;
+} i3c_slv_dev_t;
+
+extern i3c_slv_dev_t I3C_SLV;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i3c_slv_dev_t) == 0x78, "Invalid size of i3c_slv_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_qos_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_qos_reg.h
new file mode 100644
index 0000000000..8f1143edce
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_qos_reg.h
@@ -0,0 +1,176 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ICM_AXI_VERID_FILEDS_REG register
+ *  NA
+ */
+#define ICM_AXI_VERID_FILEDS_REG (DR_REG_ICM_AXI_BASE + 0x0)
+/** ICM_AXI_REG_VERID : RO; bitpos: [31:0]; default: 875574314;
+ *  NA
+ */
+#define ICM_AXI_REG_VERID    0xFFFFFFFFU
+#define ICM_AXI_REG_VERID_M  (ICM_AXI_REG_VERID_V << ICM_AXI_REG_VERID_S)
+#define ICM_AXI_REG_VERID_V  0xFFFFFFFFU
+#define ICM_AXI_REG_VERID_S  0
+
+/** ICM_AXI_HW_CFG_REG_REG register
+ *  NA
+ */
+#define ICM_AXI_HW_CFG_REG_REG (DR_REG_ICM_AXI_BASE + 0x4)
+/** ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT    (BIT(0))
+#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_M  (ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_V << ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_S)
+#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_S  0
+/** ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT    (BIT(1))
+#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_M  (ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_V << ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_S)
+#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_S  1
+/** ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT    (BIT(2))
+#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_M  (ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_V << ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_S)
+#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_S  2
+/** ICM_AXI_REG_AXI_HWCFG_LOCK_EN : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN    (BIT(3))
+#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN_M  (ICM_AXI_REG_AXI_HWCFG_LOCK_EN_V << ICM_AXI_REG_AXI_HWCFG_LOCK_EN_S)
+#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN_S  3
+/** ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN : RO; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN    (BIT(4))
+#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_M  (ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_V << ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_S)
+#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_S  4
+/** ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE    (BIT(5))
+#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_M  (ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_V << ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_S)
+#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_S  5
+/** ICM_AXI_REG_AXI_HWCFG_REMAP_EN : RO; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN    (BIT(6))
+#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN_M  (ICM_AXI_REG_AXI_HWCFG_REMAP_EN_V << ICM_AXI_REG_AXI_HWCFG_REMAP_EN_S)
+#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN_S  6
+/** ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN    (BIT(7))
+#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_M  (ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_V << ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_S)
+#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_S  7
+/** ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN : RO; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN    (BIT(8))
+#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_M  (ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_V << ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_S)
+#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_S  8
+/** ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS : RO; bitpos: [16:12]; default: 13;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS    0x0000001FU
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_M  (ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_V << ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_S)
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_V  0x0000001FU
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_S  12
+/** ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES : RO; bitpos: [24:20]; default: 7;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES    0x0000001FU
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_M  (ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_V << ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_S)
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_V  0x0000001FU
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_S  20
+
+/** ICM_AXI_CMD_REG register
+ *  NA
+ */
+#define ICM_AXI_CMD_REG (DR_REG_ICM_AXI_BASE + 0x8)
+/** ICM_AXI_REG_AXI_CMD : R/W; bitpos: [2:0]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_CMD    0x00000007U
+#define ICM_AXI_REG_AXI_CMD_M  (ICM_AXI_REG_AXI_CMD_V << ICM_AXI_REG_AXI_CMD_S)
+#define ICM_AXI_REG_AXI_CMD_V  0x00000007U
+#define ICM_AXI_REG_AXI_CMD_S  0
+/** ICM_AXI_REG_RD_WR_CHAN : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_RD_WR_CHAN    (BIT(7))
+#define ICM_AXI_REG_RD_WR_CHAN_M  (ICM_AXI_REG_RD_WR_CHAN_V << ICM_AXI_REG_RD_WR_CHAN_S)
+#define ICM_AXI_REG_RD_WR_CHAN_V  0x00000001U
+#define ICM_AXI_REG_RD_WR_CHAN_S  7
+/** ICM_AXI_REG_AXI_MASTER_PORT : R/W; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_MASTER_PORT    0x0000000FU
+#define ICM_AXI_REG_AXI_MASTER_PORT_M  (ICM_AXI_REG_AXI_MASTER_PORT_V << ICM_AXI_REG_AXI_MASTER_PORT_S)
+#define ICM_AXI_REG_AXI_MASTER_PORT_V  0x0000000FU
+#define ICM_AXI_REG_AXI_MASTER_PORT_S  8
+/** ICM_AXI_REG_AXI_ERR_BIT : RO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_ERR_BIT    (BIT(28))
+#define ICM_AXI_REG_AXI_ERR_BIT_M  (ICM_AXI_REG_AXI_ERR_BIT_V << ICM_AXI_REG_AXI_ERR_BIT_S)
+#define ICM_AXI_REG_AXI_ERR_BIT_V  0x00000001U
+#define ICM_AXI_REG_AXI_ERR_BIT_S  28
+/** ICM_AXI_REG_AXI_SOFT_RESET_BIT : R/W; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_SOFT_RESET_BIT    (BIT(29))
+#define ICM_AXI_REG_AXI_SOFT_RESET_BIT_M  (ICM_AXI_REG_AXI_SOFT_RESET_BIT_V << ICM_AXI_REG_AXI_SOFT_RESET_BIT_S)
+#define ICM_AXI_REG_AXI_SOFT_RESET_BIT_V  0x00000001U
+#define ICM_AXI_REG_AXI_SOFT_RESET_BIT_S  29
+/** ICM_AXI_REG_AXI_RD_WR_CMD : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_RD_WR_CMD    (BIT(30))
+#define ICM_AXI_REG_AXI_RD_WR_CMD_M  (ICM_AXI_REG_AXI_RD_WR_CMD_V << ICM_AXI_REG_AXI_RD_WR_CMD_S)
+#define ICM_AXI_REG_AXI_RD_WR_CMD_V  0x00000001U
+#define ICM_AXI_REG_AXI_RD_WR_CMD_S  30
+/** ICM_AXI_REG_AXI_CMD_EN : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_CMD_EN    (BIT(31))
+#define ICM_AXI_REG_AXI_CMD_EN_M  (ICM_AXI_REG_AXI_CMD_EN_V << ICM_AXI_REG_AXI_CMD_EN_S)
+#define ICM_AXI_REG_AXI_CMD_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_CMD_EN_S  31
+
+/** ICM_AXI_DATA_REG register
+ *  NA
+ */
+#define ICM_AXI_DATA_REG (DR_REG_ICM_AXI_BASE + 0xc)
+/** ICM_AXI_REG_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_DATA    0xFFFFFFFFU
+#define ICM_AXI_REG_DATA_M  (ICM_AXI_REG_DATA_V << ICM_AXI_REG_DATA_S)
+#define ICM_AXI_REG_DATA_V  0xFFFFFFFFU
+#define ICM_AXI_REG_DATA_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_qos_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_qos_struct.h
new file mode 100644
index 0000000000..8e66405ca9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_qos_struct.h
@@ -0,0 +1,157 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: ICM AXI VERID FIELDS REG */
+/** Type of verid_fileds register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_verid : RO; bitpos: [31:0]; default: 875574314;
+         *  NA
+         */
+        uint32_t reg_verid:32;
+    };
+    uint32_t val;
+} icm_axi_verid_fileds_reg_t;
+
+
+/** Group: ICM AXI HW CFG REG REG */
+/** Type of hw_cfg_reg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_axi_hwcfg_qos_support : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_qos_support:1;
+        /** reg_axi_hwcfg_apb3_support : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_apb3_support:1;
+        /** reg_axi_hwcfg_axi4_support : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_axi4_support:1;
+        /** reg_axi_hwcfg_lock_en : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_lock_en:1;
+        /** reg_axi_hwcfg_trust_zone_en : RO; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_trust_zone_en:1;
+        /** reg_axi_hwcfg_decoder_type : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_decoder_type:1;
+        /** reg_axi_hwcfg_remap_en : RO; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_remap_en:1;
+        /** reg_axi_hwcfg_bi_dir_cmd_en : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_bi_dir_cmd_en:1;
+        /** reg_axi_hwcfg_low_power_inf_en : RO; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_low_power_inf_en:1;
+        uint32_t reserved_9:3;
+        /** reg_axi_hwcfg_axi_num_masters : RO; bitpos: [16:12]; default: 13;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_axi_num_masters:5;
+        uint32_t reserved_17:3;
+        /** reg_axi_hwcfg_axi_num_slaves : RO; bitpos: [24:20]; default: 7;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_axi_num_slaves:5;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} icm_axi_hw_cfg_reg_reg_t;
+
+
+/** Group: ICM AXI CMD REG */
+/** Type of cmd register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_axi_cmd : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_cmd:3;
+        uint32_t reserved_3:4;
+        /** reg_rd_wr_chan : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rd_wr_chan:1;
+        /** reg_axi_master_port : R/W; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_master_port:4;
+        uint32_t reserved_12:16;
+        /** reg_axi_err_bit : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_err_bit:1;
+        /** reg_axi_soft_reset_bit : R/W; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_soft_reset_bit:1;
+        /** reg_axi_rd_wr_cmd : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_rd_wr_cmd:1;
+        /** reg_axi_cmd_en : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_cmd_en:1;
+    };
+    uint32_t val;
+} icm_axi_cmd_reg_t;
+
+
+/** Group: ICM AXI DATA REG */
+/** Type of data register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_data : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_data:32;
+    };
+    uint32_t val;
+} icm_axi_data_reg_t;
+
+
+typedef struct {
+    volatile icm_axi_verid_fileds_reg_t verid_fileds;
+    volatile icm_axi_hw_cfg_reg_reg_t hw_cfg_reg;
+    volatile icm_axi_cmd_reg_t cmd;
+    volatile icm_axi_data_reg_t data;
+} icm_axi_dev_t;
+
+extern icm_axi_dev_t ICM_SYS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(icm_axi_dev_t) == 0x10, "Invalid size of icm_axi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_reg.h
new file mode 100644
index 0000000000..160f1de846
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_reg.h
@@ -0,0 +1,546 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ICM_VER_DATE_REG register
+ *  NA
+ */
+#define ICM_VER_DATE_REG (DR_REG_ICM_BASE + 0x0)
+/** ICM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165204;
+ *  NA
+ */
+#define ICM_REG_VER_DATE    0xFFFFFFFFU
+#define ICM_REG_VER_DATE_M  (ICM_REG_VER_DATE_V << ICM_REG_VER_DATE_S)
+#define ICM_REG_VER_DATE_V  0xFFFFFFFFU
+#define ICM_REG_VER_DATE_S  0
+
+/** ICM_CLK_EN_REG register
+ *  NA
+ */
+#define ICM_CLK_EN_REG (DR_REG_ICM_BASE + 0x4)
+/** ICM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CLK_EN    (BIT(0))
+#define ICM_REG_CLK_EN_M  (ICM_REG_CLK_EN_V << ICM_REG_CLK_EN_S)
+#define ICM_REG_CLK_EN_V  0x00000001U
+#define ICM_REG_CLK_EN_S  0
+
+/** ICM_DLOCK_STATUS_REG register
+ *  NA
+ */
+#define ICM_DLOCK_STATUS_REG (DR_REG_ICM_BASE + 0x8)
+/** ICM_REG_DLOCK_MST : RO; bitpos: [3:0]; default: 0;
+ *  Lowest numbered deadlocked master
+ */
+#define ICM_REG_DLOCK_MST    0x0000000FU
+#define ICM_REG_DLOCK_MST_M  (ICM_REG_DLOCK_MST_V << ICM_REG_DLOCK_MST_S)
+#define ICM_REG_DLOCK_MST_V  0x0000000FU
+#define ICM_REG_DLOCK_MST_S  0
+/** ICM_REG_DLOCK_SLV : RO; bitpos: [6:4]; default: 0;
+ *  Slave with which dlock_mst is deadlocked
+ */
+#define ICM_REG_DLOCK_SLV    0x00000007U
+#define ICM_REG_DLOCK_SLV_M  (ICM_REG_DLOCK_SLV_V << ICM_REG_DLOCK_SLV_S)
+#define ICM_REG_DLOCK_SLV_V  0x00000007U
+#define ICM_REG_DLOCK_SLV_S  4
+/** ICM_REG_DLOCK_ID : RO; bitpos: [10:7]; default: 0;
+ *  AXI ID of deadlocked transaction
+ */
+#define ICM_REG_DLOCK_ID    0x0000000FU
+#define ICM_REG_DLOCK_ID_M  (ICM_REG_DLOCK_ID_V << ICM_REG_DLOCK_ID_S)
+#define ICM_REG_DLOCK_ID_V  0x0000000FU
+#define ICM_REG_DLOCK_ID_S  7
+/** ICM_REG_DLOCK_WR : RO; bitpos: [11]; default: 0;
+ *  Asserted if deadlocked transaction is a write
+ */
+#define ICM_REG_DLOCK_WR    (BIT(11))
+#define ICM_REG_DLOCK_WR_M  (ICM_REG_DLOCK_WR_V << ICM_REG_DLOCK_WR_S)
+#define ICM_REG_DLOCK_WR_V  0x00000001U
+#define ICM_REG_DLOCK_WR_S  11
+
+/** ICM_INT_RAW_REG register
+ *  NA
+ */
+#define ICM_INT_RAW_REG (DR_REG_ICM_BASE + 0xc)
+/** ICM_REG_DLOCK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DLOCK_INT_RAW    (BIT(0))
+#define ICM_REG_DLOCK_INT_RAW_M  (ICM_REG_DLOCK_INT_RAW_V << ICM_REG_DLOCK_INT_RAW_S)
+#define ICM_REG_DLOCK_INT_RAW_V  0x00000001U
+#define ICM_REG_DLOCK_INT_RAW_S  0
+/** ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW    (BIT(1))
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_M  (ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_S  1
+/** ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW    (BIT(2))
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_M  (ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_S  2
+
+/** ICM_INT_ST_REG register
+ *  NA
+ */
+#define ICM_INT_ST_REG (DR_REG_ICM_BASE + 0x10)
+/** ICM_REG_DLOCK_INT_ST : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DLOCK_INT_ST    (BIT(0))
+#define ICM_REG_DLOCK_INT_ST_M  (ICM_REG_DLOCK_INT_ST_V << ICM_REG_DLOCK_INT_ST_S)
+#define ICM_REG_DLOCK_INT_ST_V  0x00000001U
+#define ICM_REG_DLOCK_INT_ST_S  0
+/** ICM_REG_ICM_SYS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST    (BIT(1))
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_M  (ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_S  1
+/** ICM_REG_ICM_CPU_ADDRHOLE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST    (BIT(2))
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_M  (ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_S  2
+
+/** ICM_INT_ENA_REG register
+ *  NA
+ */
+#define ICM_INT_ENA_REG (DR_REG_ICM_BASE + 0x14)
+/** ICM_REG_DLOCK_INT_ENA : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define ICM_REG_DLOCK_INT_ENA    (BIT(0))
+#define ICM_REG_DLOCK_INT_ENA_M  (ICM_REG_DLOCK_INT_ENA_V << ICM_REG_DLOCK_INT_ENA_S)
+#define ICM_REG_DLOCK_INT_ENA_V  0x00000001U
+#define ICM_REG_DLOCK_INT_ENA_S  0
+/** ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA    (BIT(1))
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_M  (ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_S  1
+/** ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA    (BIT(2))
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_M  (ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_S  2
+
+/** ICM_INT_CLR_REG register
+ *  NA
+ */
+#define ICM_INT_CLR_REG (DR_REG_ICM_BASE + 0x18)
+/** ICM_REG_DLOCK_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DLOCK_INT_CLR    (BIT(0))
+#define ICM_REG_DLOCK_INT_CLR_M  (ICM_REG_DLOCK_INT_CLR_V << ICM_REG_DLOCK_INT_CLR_S)
+#define ICM_REG_DLOCK_INT_CLR_V  0x00000001U
+#define ICM_REG_DLOCK_INT_CLR_S  0
+/** ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR    (BIT(1))
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_M  (ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_S  1
+/** ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR    (BIT(2))
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_M  (ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_S  2
+
+/** ICM_MST_ARB_PRIORITY_REG0_REG register
+ *  NA
+ */
+#define ICM_MST_ARB_PRIORITY_REG0_REG (DR_REG_ICM_BASE + 0x1c)
+/** ICM_REG_CPU_PRIORITY : R/W; bitpos: [3:0]; default: 0;
+ *  CPU arbitration priority for command channels between masters connected to sys_icm
+ */
+#define ICM_REG_CPU_PRIORITY    0x0000000FU
+#define ICM_REG_CPU_PRIORITY_M  (ICM_REG_CPU_PRIORITY_V << ICM_REG_CPU_PRIORITY_S)
+#define ICM_REG_CPU_PRIORITY_V  0x0000000FU
+#define ICM_REG_CPU_PRIORITY_S  0
+/** ICM_REG_CACHE_PRIORITY : R/W; bitpos: [7:4]; default: 0;
+ *  CACHE arbitration priority for command channels between masters connected to sys_icm
+ */
+#define ICM_REG_CACHE_PRIORITY    0x0000000FU
+#define ICM_REG_CACHE_PRIORITY_M  (ICM_REG_CACHE_PRIORITY_V << ICM_REG_CACHE_PRIORITY_S)
+#define ICM_REG_CACHE_PRIORITY_V  0x0000000FU
+#define ICM_REG_CACHE_PRIORITY_S  4
+/** ICM_REG_DMA2D_PRIORITY : R/W; bitpos: [11:8]; default: 0;
+ *  GFX arbitration priority for command channels between masters connected to sys_icm
+ */
+#define ICM_REG_DMA2D_PRIORITY    0x0000000FU
+#define ICM_REG_DMA2D_PRIORITY_M  (ICM_REG_DMA2D_PRIORITY_V << ICM_REG_DMA2D_PRIORITY_S)
+#define ICM_REG_DMA2D_PRIORITY_V  0x0000000FU
+#define ICM_REG_DMA2D_PRIORITY_S  8
+/** ICM_REG_GDMA_MST1_PRIORITY : R/W; bitpos: [15:12]; default: 0;
+ *  GDMA mst1 arbitration priority for command channels between masters connected to
+ *  sys_icm
+ */
+#define ICM_REG_GDMA_MST1_PRIORITY    0x0000000FU
+#define ICM_REG_GDMA_MST1_PRIORITY_M  (ICM_REG_GDMA_MST1_PRIORITY_V << ICM_REG_GDMA_MST1_PRIORITY_S)
+#define ICM_REG_GDMA_MST1_PRIORITY_V  0x0000000FU
+#define ICM_REG_GDMA_MST1_PRIORITY_S  12
+/** ICM_REG_GDMA_MST2_PRIORITY : R/W; bitpos: [19:16]; default: 0;
+ *  GDMA mst2 arbitration priority for command channels between masters connected to
+ *  sys_icm
+ */
+#define ICM_REG_GDMA_MST2_PRIORITY    0x0000000FU
+#define ICM_REG_GDMA_MST2_PRIORITY_M  (ICM_REG_GDMA_MST2_PRIORITY_V << ICM_REG_GDMA_MST2_PRIORITY_S)
+#define ICM_REG_GDMA_MST2_PRIORITY_V  0x0000000FU
+#define ICM_REG_GDMA_MST2_PRIORITY_S  16
+/** ICM_REG_H264_M1_PRIORITY : R/W; bitpos: [23:20]; default: 0;
+ *  H264 mst1 arbitration priority for command channels between masters connected to
+ *  sys_icm
+ */
+#define ICM_REG_H264_M1_PRIORITY    0x0000000FU
+#define ICM_REG_H264_M1_PRIORITY_M  (ICM_REG_H264_M1_PRIORITY_V << ICM_REG_H264_M1_PRIORITY_S)
+#define ICM_REG_H264_M1_PRIORITY_V  0x0000000FU
+#define ICM_REG_H264_M1_PRIORITY_S  20
+/** ICM_REG_H264_M2_PRIORITY : R/W; bitpos: [27:24]; default: 0;
+ *  H264 mst2 arbitration priority for command channels between masters connected to
+ *  sys_icm
+ */
+#define ICM_REG_H264_M2_PRIORITY    0x0000000FU
+#define ICM_REG_H264_M2_PRIORITY_M  (ICM_REG_H264_M2_PRIORITY_V << ICM_REG_H264_M2_PRIORITY_S)
+#define ICM_REG_H264_M2_PRIORITY_V  0x0000000FU
+#define ICM_REG_H264_M2_PRIORITY_S  24
+/** ICM_REG_AXI_PDMA_PRIORITY : R/W; bitpos: [31:28]; default: 0;
+ *  AXI PDMA  arbitration priority for command channels between masters connected to
+ *  sys_icm
+ */
+#define ICM_REG_AXI_PDMA_PRIORITY    0x0000000FU
+#define ICM_REG_AXI_PDMA_PRIORITY_M  (ICM_REG_AXI_PDMA_PRIORITY_V << ICM_REG_AXI_PDMA_PRIORITY_S)
+#define ICM_REG_AXI_PDMA_PRIORITY_V  0x0000000FU
+#define ICM_REG_AXI_PDMA_PRIORITY_S  28
+
+/** ICM_SLV_ARB_PRIORITY_REG register
+ *  NA
+ */
+#define ICM_SLV_ARB_PRIORITY_REG (DR_REG_ICM_BASE + 0x24)
+/** ICM_REG_L2MEM_PRIORITY : R/W; bitpos: [5:3]; default: 0;
+ *  L2MEM arbitration priority for response channels between slaves connected to sys_icm
+ */
+#define ICM_REG_L2MEM_PRIORITY    0x00000007U
+#define ICM_REG_L2MEM_PRIORITY_M  (ICM_REG_L2MEM_PRIORITY_V << ICM_REG_L2MEM_PRIORITY_S)
+#define ICM_REG_L2MEM_PRIORITY_V  0x00000007U
+#define ICM_REG_L2MEM_PRIORITY_S  3
+/** ICM_REG_FLASH_MSPI_PRIORITY : R/W; bitpos: [14:12]; default: 0;
+ *  FLASH MSPI arbitration priority for response channels between slaves connected to
+ *  sys_icm
+ */
+#define ICM_REG_FLASH_MSPI_PRIORITY    0x00000007U
+#define ICM_REG_FLASH_MSPI_PRIORITY_M  (ICM_REG_FLASH_MSPI_PRIORITY_V << ICM_REG_FLASH_MSPI_PRIORITY_S)
+#define ICM_REG_FLASH_MSPI_PRIORITY_V  0x00000007U
+#define ICM_REG_FLASH_MSPI_PRIORITY_S  12
+/** ICM_REG_PSRAM_MSPI_PRIORITY : R/W; bitpos: [17:15]; default: 0;
+ *  PSRAM MSPI arbitration priority for response channels between slaves connected to
+ *  sys_icm
+ */
+#define ICM_REG_PSRAM_MSPI_PRIORITY    0x00000007U
+#define ICM_REG_PSRAM_MSPI_PRIORITY_M  (ICM_REG_PSRAM_MSPI_PRIORITY_V << ICM_REG_PSRAM_MSPI_PRIORITY_S)
+#define ICM_REG_PSRAM_MSPI_PRIORITY_V  0x00000007U
+#define ICM_REG_PSRAM_MSPI_PRIORITY_S  15
+/** ICM_REG_LCD_PRIORITY : R/W; bitpos: [20:18]; default: 0;
+ *  MIPI_LCD registers arbitration priority for response channels between slaves
+ *  connected to sys_icm
+ */
+#define ICM_REG_LCD_PRIORITY    0x00000007U
+#define ICM_REG_LCD_PRIORITY_M  (ICM_REG_LCD_PRIORITY_V << ICM_REG_LCD_PRIORITY_S)
+#define ICM_REG_LCD_PRIORITY_V  0x00000007U
+#define ICM_REG_LCD_PRIORITY_S  18
+/** ICM_REG_CAM_PRIORITY : R/W; bitpos: [23:21]; default: 0;
+ *  MIPI_CAM registers arbitration priority for response channels between slaves
+ *  connected to sys_icm
+ */
+#define ICM_REG_CAM_PRIORITY    0x00000007U
+#define ICM_REG_CAM_PRIORITY_M  (ICM_REG_CAM_PRIORITY_V << ICM_REG_CAM_PRIORITY_S)
+#define ICM_REG_CAM_PRIORITY_V  0x00000007U
+#define ICM_REG_CAM_PRIORITY_S  21
+
+/** ICM_MST_ARQOS_REG0_REG register
+ *  NA
+ */
+#define ICM_MST_ARQOS_REG0_REG (DR_REG_ICM_BASE + 0x28)
+/** ICM_REG_CPU_ARQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CPU_ARQOS    0x0000000FU
+#define ICM_REG_CPU_ARQOS_M  (ICM_REG_CPU_ARQOS_V << ICM_REG_CPU_ARQOS_S)
+#define ICM_REG_CPU_ARQOS_V  0x0000000FU
+#define ICM_REG_CPU_ARQOS_S  0
+/** ICM_REG_CACHE_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CACHE_ARQOS    0x0000000FU
+#define ICM_REG_CACHE_ARQOS_M  (ICM_REG_CACHE_ARQOS_V << ICM_REG_CACHE_ARQOS_S)
+#define ICM_REG_CACHE_ARQOS_V  0x0000000FU
+#define ICM_REG_CACHE_ARQOS_S  4
+/** ICM_REG_DMA2D_ARQOS : R/W; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DMA2D_ARQOS    0x0000000FU
+#define ICM_REG_DMA2D_ARQOS_M  (ICM_REG_DMA2D_ARQOS_V << ICM_REG_DMA2D_ARQOS_S)
+#define ICM_REG_DMA2D_ARQOS_V  0x0000000FU
+#define ICM_REG_DMA2D_ARQOS_S  8
+/** ICM_REG_GDMA_MST1_ARQOS : R/W; bitpos: [15:12]; default: 0;
+ *  NA
+ */
+#define ICM_REG_GDMA_MST1_ARQOS    0x0000000FU
+#define ICM_REG_GDMA_MST1_ARQOS_M  (ICM_REG_GDMA_MST1_ARQOS_V << ICM_REG_GDMA_MST1_ARQOS_S)
+#define ICM_REG_GDMA_MST1_ARQOS_V  0x0000000FU
+#define ICM_REG_GDMA_MST1_ARQOS_S  12
+/** ICM_REG_GDMA_MST2_ARQOS : R/W; bitpos: [19:16]; default: 0;
+ *  NA
+ */
+#define ICM_REG_GDMA_MST2_ARQOS    0x0000000FU
+#define ICM_REG_GDMA_MST2_ARQOS_M  (ICM_REG_GDMA_MST2_ARQOS_V << ICM_REG_GDMA_MST2_ARQOS_S)
+#define ICM_REG_GDMA_MST2_ARQOS_V  0x0000000FU
+#define ICM_REG_GDMA_MST2_ARQOS_S  16
+/** ICM_REG_H264_DMA2D_M1_ARQOS : R/W; bitpos: [23:20]; default: 0;
+ *  NA
+ */
+#define ICM_REG_H264_DMA2D_M1_ARQOS    0x0000000FU
+#define ICM_REG_H264_DMA2D_M1_ARQOS_M  (ICM_REG_H264_DMA2D_M1_ARQOS_V << ICM_REG_H264_DMA2D_M1_ARQOS_S)
+#define ICM_REG_H264_DMA2D_M1_ARQOS_V  0x0000000FU
+#define ICM_REG_H264_DMA2D_M1_ARQOS_S  20
+/** ICM_REG_H264_DMA2D_M2_ARQOS : R/W; bitpos: [27:24]; default: 0;
+ *  NA
+ */
+#define ICM_REG_H264_DMA2D_M2_ARQOS    0x0000000FU
+#define ICM_REG_H264_DMA2D_M2_ARQOS_M  (ICM_REG_H264_DMA2D_M2_ARQOS_V << ICM_REG_H264_DMA2D_M2_ARQOS_S)
+#define ICM_REG_H264_DMA2D_M2_ARQOS_V  0x0000000FU
+#define ICM_REG_H264_DMA2D_M2_ARQOS_S  24
+/** ICM_REG_AXI_PDMA_INT_ARQOS : R/W; bitpos: [31:28]; default: 0;
+ *  NA
+ */
+#define ICM_REG_AXI_PDMA_INT_ARQOS    0x0000000FU
+#define ICM_REG_AXI_PDMA_INT_ARQOS_M  (ICM_REG_AXI_PDMA_INT_ARQOS_V << ICM_REG_AXI_PDMA_INT_ARQOS_S)
+#define ICM_REG_AXI_PDMA_INT_ARQOS_V  0x0000000FU
+#define ICM_REG_AXI_PDMA_INT_ARQOS_S  28
+
+/** ICM_MST_AWQOS_REG0_REG register
+ *  NA
+ */
+#define ICM_MST_AWQOS_REG0_REG (DR_REG_ICM_BASE + 0x30)
+/** ICM_REG_CPU_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CPU_AWQOS    0x0000000FU
+#define ICM_REG_CPU_AWQOS_M  (ICM_REG_CPU_AWQOS_V << ICM_REG_CPU_AWQOS_S)
+#define ICM_REG_CPU_AWQOS_V  0x0000000FU
+#define ICM_REG_CPU_AWQOS_S  0
+/** ICM_REG_CACHE_AWQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CACHE_AWQOS    0x0000000FU
+#define ICM_REG_CACHE_AWQOS_M  (ICM_REG_CACHE_AWQOS_V << ICM_REG_CACHE_AWQOS_S)
+#define ICM_REG_CACHE_AWQOS_V  0x0000000FU
+#define ICM_REG_CACHE_AWQOS_S  4
+/** ICM_REG_DMA2D_AWQOS : R/W; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DMA2D_AWQOS    0x0000000FU
+#define ICM_REG_DMA2D_AWQOS_M  (ICM_REG_DMA2D_AWQOS_V << ICM_REG_DMA2D_AWQOS_S)
+#define ICM_REG_DMA2D_AWQOS_V  0x0000000FU
+#define ICM_REG_DMA2D_AWQOS_S  8
+/** ICM_REG_GDMA_MST1_AWQOS : R/W; bitpos: [15:12]; default: 0;
+ *  NA
+ */
+#define ICM_REG_GDMA_MST1_AWQOS    0x0000000FU
+#define ICM_REG_GDMA_MST1_AWQOS_M  (ICM_REG_GDMA_MST1_AWQOS_V << ICM_REG_GDMA_MST1_AWQOS_S)
+#define ICM_REG_GDMA_MST1_AWQOS_V  0x0000000FU
+#define ICM_REG_GDMA_MST1_AWQOS_S  12
+/** ICM_REG_GDMA_MST2_AWQOS : R/W; bitpos: [19:16]; default: 0;
+ *  NA
+ */
+#define ICM_REG_GDMA_MST2_AWQOS    0x0000000FU
+#define ICM_REG_GDMA_MST2_AWQOS_M  (ICM_REG_GDMA_MST2_AWQOS_V << ICM_REG_GDMA_MST2_AWQOS_S)
+#define ICM_REG_GDMA_MST2_AWQOS_V  0x0000000FU
+#define ICM_REG_GDMA_MST2_AWQOS_S  16
+/** ICM_REG_H264_DMA2D_M1_AWQOS : R/W; bitpos: [23:20]; default: 0;
+ *  NA
+ */
+#define ICM_REG_H264_DMA2D_M1_AWQOS    0x0000000FU
+#define ICM_REG_H264_DMA2D_M1_AWQOS_M  (ICM_REG_H264_DMA2D_M1_AWQOS_V << ICM_REG_H264_DMA2D_M1_AWQOS_S)
+#define ICM_REG_H264_DMA2D_M1_AWQOS_V  0x0000000FU
+#define ICM_REG_H264_DMA2D_M1_AWQOS_S  20
+/** ICM_REG_H264_DMA2D_M2_AWQOS : R/W; bitpos: [27:24]; default: 0;
+ *  NA
+ */
+#define ICM_REG_H264_DMA2D_M2_AWQOS    0x0000000FU
+#define ICM_REG_H264_DMA2D_M2_AWQOS_M  (ICM_REG_H264_DMA2D_M2_AWQOS_V << ICM_REG_H264_DMA2D_M2_AWQOS_S)
+#define ICM_REG_H264_DMA2D_M2_AWQOS_V  0x0000000FU
+#define ICM_REG_H264_DMA2D_M2_AWQOS_S  24
+/** ICM_REG_PDMA_INT_AWQOS : R/W; bitpos: [31:28]; default: 0;
+ *  NA
+ */
+#define ICM_REG_PDMA_INT_AWQOS    0x0000000FU
+#define ICM_REG_PDMA_INT_AWQOS_M  (ICM_REG_PDMA_INT_AWQOS_V << ICM_REG_PDMA_INT_AWQOS_S)
+#define ICM_REG_PDMA_INT_AWQOS_V  0x0000000FU
+#define ICM_REG_PDMA_INT_AWQOS_S  28
+
+/** ICM_SYS_ADDRHOLE_ADDR_REG register
+ *  icm sys addr hole address registers
+ */
+#define ICM_SYS_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x38)
+/** ICM_REG_ICM_SYS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR    0xFFFFFFFFU
+#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_M  (ICM_REG_ICM_SYS_ADDRHOLE_ADDR_V << ICM_REG_ICM_SYS_ADDRHOLE_ADDR_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_V  0xFFFFFFFFU
+#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_S  0
+
+/** ICM_SYS_ADDRHOLE_INFO_REG register
+ *  NA
+ */
+#define ICM_SYS_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x3c)
+/** ICM_REG_ICM_SYS_ADDRHOLE_ID : RO; bitpos: [7:0]; default: 0;
+ *  master id = 4-bit CID + 4-bit  UID(refer to related IP) . CID is used to verify
+ *  master in icm. CID: 4'h1: cache, 4'h5 gdma mst1, 4'h6: gdma mst2, 4'h8: axi pdma,
+ *  4'ha: dma2d, 4'hb: h264 mst1, 4'hc: h264 mst2.
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_ID    0x000000FFU
+#define ICM_REG_ICM_SYS_ADDRHOLE_ID_M  (ICM_REG_ICM_SYS_ADDRHOLE_ID_V << ICM_REG_ICM_SYS_ADDRHOLE_ID_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_ID_V  0x000000FFU
+#define ICM_REG_ICM_SYS_ADDRHOLE_ID_S  0
+/** ICM_REG_ICM_SYS_ADDRHOLE_WR : RO; bitpos: [8]; default: 0;
+ *  1: illegal address access, 0: access without permission
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_WR    (BIT(8))
+#define ICM_REG_ICM_SYS_ADDRHOLE_WR_M  (ICM_REG_ICM_SYS_ADDRHOLE_WR_V << ICM_REG_ICM_SYS_ADDRHOLE_WR_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_WR_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_WR_S  8
+/** ICM_REG_ICM_SYS_ADDRHOLE_SECURE : RO; bitpos: [9]; default: 0;
+ *  It is illegall access address if reg_icm_cpu_addrhole_secure is 1, Otherwise, it
+ *  the address without permission to access.
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE    (BIT(9))
+#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_M  (ICM_REG_ICM_SYS_ADDRHOLE_SECURE_V << ICM_REG_ICM_SYS_ADDRHOLE_SECURE_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_S  9
+
+/** ICM_CPU_ADDRHOLE_ADDR_REG register
+ *  icm cpu addr hole address registers
+ */
+#define ICM_CPU_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x40)
+/** ICM_REG_ICM_CPU_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  It is illegall access address if reg_icm_cpu_addrhole_secure is 1. Otherwise, it
+ *  the address without permission to access.
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR    0xFFFFFFFFU
+#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_M  (ICM_REG_ICM_CPU_ADDRHOLE_ADDR_V << ICM_REG_ICM_CPU_ADDRHOLE_ADDR_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_V  0xFFFFFFFFU
+#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_S  0
+
+/** ICM_CPU_ADDRHOLE_INFO_REG register
+ *  NA
+ */
+#define ICM_CPU_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x44)
+/** ICM_REG_ICM_CPU_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
+ *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
+ *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
+ *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_ID    0x0000001FU
+#define ICM_REG_ICM_CPU_ADDRHOLE_ID_M  (ICM_REG_ICM_CPU_ADDRHOLE_ID_V << ICM_REG_ICM_CPU_ADDRHOLE_ID_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_ID_V  0x0000001FU
+#define ICM_REG_ICM_CPU_ADDRHOLE_ID_S  0
+/** ICM_REG_ICM_CPU_ADDRHOLE_WR : RO; bitpos: [8]; default: 0;
+ *  1:write trans, 0: read trans.
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_WR    (BIT(8))
+#define ICM_REG_ICM_CPU_ADDRHOLE_WR_M  (ICM_REG_ICM_CPU_ADDRHOLE_WR_V << ICM_REG_ICM_CPU_ADDRHOLE_WR_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_WR_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_WR_S  8
+/** ICM_REG_ICM_CPU_ADDRHOLE_SECURE : RO; bitpos: [9]; default: 0;
+ *  1: illegal address access, 0: access without permission
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE    (BIT(9))
+#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_M  (ICM_REG_ICM_CPU_ADDRHOLE_SECURE_V << ICM_REG_ICM_CPU_ADDRHOLE_SECURE_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_S  9
+
+/** ICM_DLOCK_TIMEOUT_REG register
+ *  NA
+ */
+#define ICM_DLOCK_TIMEOUT_REG (DR_REG_ICM_BASE + 0x48)
+/** ICM_REG_DLOCK_TIMEOUT : R/W; bitpos: [12:0]; default: 2048;
+ *  if no response until reg_dlock_timeout bus clock cycle, deadlock will happen
+ */
+#define ICM_REG_DLOCK_TIMEOUT    0x00001FFFU
+#define ICM_REG_DLOCK_TIMEOUT_M  (ICM_REG_DLOCK_TIMEOUT_V << ICM_REG_DLOCK_TIMEOUT_S)
+#define ICM_REG_DLOCK_TIMEOUT_V  0x00001FFFU
+#define ICM_REG_DLOCK_TIMEOUT_S  0
+
+/** ICM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define ICM_RDN_ECO_CS_REG (DR_REG_ICM_BASE + 0x50)
+/** ICM_REG_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_RDN_ECO_EN    (BIT(0))
+#define ICM_REG_RDN_ECO_EN_M  (ICM_REG_RDN_ECO_EN_V << ICM_REG_RDN_ECO_EN_S)
+#define ICM_REG_RDN_ECO_EN_V  0x00000001U
+#define ICM_REG_RDN_ECO_EN_S  0
+/** ICM_REG_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define ICM_REG_RDN_ECO_RESULT    (BIT(1))
+#define ICM_REG_RDN_ECO_RESULT_M  (ICM_REG_RDN_ECO_RESULT_V << ICM_REG_RDN_ECO_RESULT_S)
+#define ICM_REG_RDN_ECO_RESULT_V  0x00000001U
+#define ICM_REG_RDN_ECO_RESULT_S  1
+
+/** ICM_RDN_ECO_LOW_REG register
+ *  NA
+ */
+#define ICM_RDN_ECO_LOW_REG (DR_REG_ICM_BASE + 0x54)
+/** ICM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define ICM_RDN_ECO_LOW    0xFFFFFFFFU
+#define ICM_RDN_ECO_LOW_M  (ICM_RDN_ECO_LOW_V << ICM_RDN_ECO_LOW_S)
+#define ICM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define ICM_RDN_ECO_LOW_S  0
+
+/** ICM_RDN_ECO_HIGH_REG register
+ *  NA
+ */
+#define ICM_RDN_ECO_HIGH_REG (DR_REG_ICM_BASE + 0x58)
+/** ICM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  NA
+ */
+#define ICM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define ICM_RDN_ECO_HIGH_M  (ICM_RDN_ECO_HIGH_V << ICM_RDN_ECO_HIGH_S)
+#define ICM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define ICM_RDN_ECO_HIGH_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_struct.h
new file mode 100644
index 0000000000..92fe8de9fd
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_struct.h
@@ -0,0 +1,521 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: ICM VER DATE REG */
+/** Type of ver_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [31:0]; default: 539165204;
+         *  NA
+         */
+        uint32_t reg_ver_date:32;
+    };
+    uint32_t val;
+} icm_ver_date_reg_t;
+
+
+/** Group: ICM CLK EN REG */
+/** Type of clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} icm_clk_en_reg_t;
+
+
+/** Group: ICM DLOCK STATUS REG */
+/** Type of dlock_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_mst : RO; bitpos: [3:0]; default: 0;
+         *  Lowest numbered deadlocked master
+         */
+        uint32_t reg_dlock_mst:4;
+        /** reg_dlock_slv : RO; bitpos: [6:4]; default: 0;
+         *  Slave with which dlock_mst is deadlocked
+         */
+        uint32_t reg_dlock_slv:3;
+        /** reg_dlock_id : RO; bitpos: [10:7]; default: 0;
+         *  AXI ID of deadlocked transaction
+         */
+        uint32_t reg_dlock_id:4;
+        /** reg_dlock_wr : RO; bitpos: [11]; default: 0;
+         *  Asserted if deadlocked transaction is a write
+         */
+        uint32_t reg_dlock_wr:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} icm_dlock_status_reg_t;
+
+
+/** Group: ICM INT RAW REG */
+/** Type of int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dlock_int_raw:1;
+        /** reg_icm_sys_addrhole_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_sys_addrhole_int_raw:1;
+        /** reg_icm_cpu_addrhole_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_cpu_addrhole_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} icm_int_raw_reg_t;
+
+
+/** Group: ICM INT ST REG */
+/** Type of int_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_int_st : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dlock_int_st:1;
+        /** reg_icm_sys_addrhole_int_st : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_sys_addrhole_int_st:1;
+        /** reg_icm_cpu_addrhole_int_st : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_cpu_addrhole_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} icm_int_st_reg_t;
+
+
+/** Group: ICM INT ENA REG */
+/** Type of int_ena register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_int_ena : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_dlock_int_ena:1;
+        /** reg_icm_sys_addrhole_int_ena : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_icm_sys_addrhole_int_ena:1;
+        /** reg_icm_cpu_addrhole_int_ena : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_icm_cpu_addrhole_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} icm_int_ena_reg_t;
+
+
+/** Group: ICM INT CLR REG */
+/** Type of int_clr register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_int_clr : WT; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dlock_int_clr:1;
+        /** reg_icm_sys_addrhole_int_clr : WT; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_sys_addrhole_int_clr:1;
+        /** reg_icm_cpu_addrhole_int_clr : WT; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_cpu_addrhole_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} icm_int_clr_reg_t;
+
+
+/** Group: ICM MST ARB PRIORITY REG0 REG */
+/** Type of mst_arb_priority_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cpu_priority : R/W; bitpos: [3:0]; default: 0;
+         *  CPU arbitration priority for command channels between masters connected to sys_icm
+         */
+        uint32_t reg_cpu_priority:4;
+        /** reg_cache_priority : R/W; bitpos: [7:4]; default: 0;
+         *  CACHE arbitration priority for command channels between masters connected to sys_icm
+         */
+        uint32_t reg_cache_priority:4;
+        /** reg_dma2d_priority : R/W; bitpos: [11:8]; default: 0;
+         *  GFX arbitration priority for command channels between masters connected to sys_icm
+         */
+        uint32_t reg_dma2d_priority:4;
+        /** reg_gdma_mst1_priority : R/W; bitpos: [15:12]; default: 0;
+         *  GDMA mst1 arbitration priority for command channels between masters connected to
+         *  sys_icm
+         */
+        uint32_t reg_gdma_mst1_priority:4;
+        /** reg_gdma_mst2_priority : R/W; bitpos: [19:16]; default: 0;
+         *  GDMA mst2 arbitration priority for command channels between masters connected to
+         *  sys_icm
+         */
+        uint32_t reg_gdma_mst2_priority:4;
+        /** reg_h264_m1_priority : R/W; bitpos: [23:20]; default: 0;
+         *  H264 mst1 arbitration priority for command channels between masters connected to
+         *  sys_icm
+         */
+        uint32_t reg_h264_m1_priority:4;
+        /** reg_h264_m2_priority : R/W; bitpos: [27:24]; default: 0;
+         *  H264 mst2 arbitration priority for command channels between masters connected to
+         *  sys_icm
+         */
+        uint32_t reg_h264_m2_priority:4;
+        /** reg_axi_pdma_priority : R/W; bitpos: [31:28]; default: 0;
+         *  AXI PDMA  arbitration priority for command channels between masters connected to
+         *  sys_icm
+         */
+        uint32_t reg_axi_pdma_priority:4;
+    };
+    uint32_t val;
+} icm_mst_arb_priority_reg0_reg_t;
+
+
+/** Group: ICM SLV ARB PRIORITY REG */
+/** Type of slv_arb_priority register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** reg_l2mem_priority : R/W; bitpos: [5:3]; default: 0;
+         *  L2MEM arbitration priority for response channels between slaves connected to sys_icm
+         */
+        uint32_t reg_l2mem_priority:3;
+        uint32_t reserved_6:6;
+        /** reg_flash_mspi_priority : R/W; bitpos: [14:12]; default: 0;
+         *  FLASH MSPI arbitration priority for response channels between slaves connected to
+         *  sys_icm
+         */
+        uint32_t reg_flash_mspi_priority:3;
+        /** reg_psram_mspi_priority : R/W; bitpos: [17:15]; default: 0;
+         *  PSRAM MSPI arbitration priority for response channels between slaves connected to
+         *  sys_icm
+         */
+        uint32_t reg_psram_mspi_priority:3;
+        /** reg_lcd_priority : R/W; bitpos: [20:18]; default: 0;
+         *  MIPI_LCD registers arbitration priority for response channels between slaves
+         *  connected to sys_icm
+         */
+        uint32_t reg_lcd_priority:3;
+        /** reg_cam_priority : R/W; bitpos: [23:21]; default: 0;
+         *  MIPI_CAM registers arbitration priority for response channels between slaves
+         *  connected to sys_icm
+         */
+        uint32_t reg_cam_priority:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} icm_slv_arb_priority_reg_t;
+
+
+/** Group: ICM MST ARQOS REG0 REG */
+/** Type of mst_arqos_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cpu_arqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cpu_arqos:4;
+        /** reg_cache_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cache_arqos:4;
+        /** reg_dma2d_arqos : R/W; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dma2d_arqos:4;
+        /** reg_gdma_mst1_arqos : R/W; bitpos: [15:12]; default: 0;
+         *  NA
+         */
+        uint32_t reg_gdma_mst1_arqos:4;
+        /** reg_gdma_mst2_arqos : R/W; bitpos: [19:16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_gdma_mst2_arqos:4;
+        /** reg_h264_dma2d_m1_arqos : R/W; bitpos: [23:20]; default: 0;
+         *  NA
+         */
+        uint32_t reg_h264_dma2d_m1_arqos:4;
+        /** reg_h264_dma2d_m2_arqos : R/W; bitpos: [27:24]; default: 0;
+         *  NA
+         */
+        uint32_t reg_h264_dma2d_m2_arqos:4;
+        /** reg_axi_pdma_int_arqos : R/W; bitpos: [31:28]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_pdma_int_arqos:4;
+    };
+    uint32_t val;
+} icm_mst_arqos_reg0_reg_t;
+
+
+/** Group: ICM MST AWQOS REG0 REG */
+/** Type of mst_awqos_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cpu_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cpu_awqos:4;
+        /** reg_cache_awqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cache_awqos:4;
+        /** reg_dma2d_awqos : R/W; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dma2d_awqos:4;
+        /** reg_gdma_mst1_awqos : R/W; bitpos: [15:12]; default: 0;
+         *  NA
+         */
+        uint32_t reg_gdma_mst1_awqos:4;
+        /** reg_gdma_mst2_awqos : R/W; bitpos: [19:16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_gdma_mst2_awqos:4;
+        /** reg_h264_dma2d_m1_awqos : R/W; bitpos: [23:20]; default: 0;
+         *  NA
+         */
+        uint32_t reg_h264_dma2d_m1_awqos:4;
+        /** reg_h264_dma2d_m2_awqos : R/W; bitpos: [27:24]; default: 0;
+         *  NA
+         */
+        uint32_t reg_h264_dma2d_m2_awqos:4;
+        /** reg_pdma_int_awqos : R/W; bitpos: [31:28]; default: 0;
+         *  NA
+         */
+        uint32_t reg_pdma_int_awqos:4;
+    };
+    uint32_t val;
+} icm_mst_awqos_reg0_reg_t;
+
+
+/** Group: ICM ADDRHOLE ADDR REG */
+/** Type of sys_addrhole_addr register
+ *  icm sys addr hole address registers
+ */
+typedef union {
+    struct {
+        /** reg_icm_sys_addrhole_addr : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_sys_addrhole_addr:32;
+    };
+    uint32_t val;
+} icm_sys_addrhole_addr_reg_t;
+
+/** Type of cpu_addrhole_addr register
+ *  icm cpu addr hole address registers
+ */
+typedef union {
+    struct {
+        /** reg_icm_cpu_addrhole_addr : RO; bitpos: [31:0]; default: 0;
+         *  It is illegall access address if reg_icm_cpu_addrhole_secure is 1. Otherwise, it
+         *  the address without permission to access.
+         */
+        uint32_t reg_icm_cpu_addrhole_addr:32;
+    };
+    uint32_t val;
+} icm_cpu_addrhole_addr_reg_t;
+
+
+/** Group: ICM ADDRHOLE INFO REG */
+/** Type of sys_addrhole_info register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_icm_sys_addrhole_id : RO; bitpos: [7:0]; default: 0;
+         *  master id = 4-bit CID + 4-bit  UID(refer to related IP) . CID is used to verify
+         *  master in icm. CID: 4'h1: cache, 4'h5 gdma mst1, 4'h6: gdma mst2, 4'h8: axi pdma,
+         *  4'ha: dma2d, 4'hb: h264 mst1, 4'hc: h264 mst2.
+         */
+        uint32_t reg_icm_sys_addrhole_id:8;
+        /** reg_icm_sys_addrhole_wr : RO; bitpos: [8]; default: 0;
+         *  1: illegal address access, 0: access without permission
+         */
+        uint32_t reg_icm_sys_addrhole_wr:1;
+        /** reg_icm_sys_addrhole_secure : RO; bitpos: [9]; default: 0;
+         *  It is illegall access address if reg_icm_cpu_addrhole_secure is 1, Otherwise, it
+         *  the address without permission to access.
+         */
+        uint32_t reg_icm_sys_addrhole_secure:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} icm_sys_addrhole_info_reg_t;
+
+/** Type of cpu_addrhole_info register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_icm_cpu_addrhole_id : RO; bitpos: [4:0]; default: 0;
+         *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
+         *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
+         *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
+         */
+        uint32_t reg_icm_cpu_addrhole_id:5;
+        uint32_t reserved_5:3;
+        /** reg_icm_cpu_addrhole_wr : RO; bitpos: [8]; default: 0;
+         *  1:write trans, 0: read trans.
+         */
+        uint32_t reg_icm_cpu_addrhole_wr:1;
+        /** reg_icm_cpu_addrhole_secure : RO; bitpos: [9]; default: 0;
+         *  1: illegal address access, 0: access without permission
+         */
+        uint32_t reg_icm_cpu_addrhole_secure:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} icm_cpu_addrhole_info_reg_t;
+
+
+/** Group: ICM DLOCK TIMEOUT REG */
+/** Type of dlock_timeout register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_timeout : R/W; bitpos: [12:0]; default: 2048;
+         *  if no response until reg_dlock_timeout bus clock cycle, deadlock will happen
+         */
+        uint32_t reg_dlock_timeout:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} icm_dlock_timeout_reg_t;
+
+
+/** Group: ICM RDN ECO CS REG */
+/** Type of rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rdn_eco_en:1;
+        /** reg_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} icm_rdn_eco_cs_reg_t;
+
+
+/** Group: ICM RDN ECO LOW REG */
+/** Type of rdn_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} icm_rdn_eco_low_reg_t;
+
+
+/** Group: ICM RDN ECO HIGH REG */
+/** Type of rdn_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  NA
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} icm_rdn_eco_high_reg_t;
+
+
+typedef struct {
+    volatile icm_ver_date_reg_t ver_date;
+    volatile icm_clk_en_reg_t clk_en;
+    volatile icm_dlock_status_reg_t dlock_status;
+    volatile icm_int_raw_reg_t int_raw;
+    volatile icm_int_st_reg_t int_st;
+    volatile icm_int_ena_reg_t int_ena;
+    volatile icm_int_clr_reg_t int_clr;
+    volatile icm_mst_arb_priority_reg0_reg_t mst_arb_priority_reg0;
+    uint32_t reserved_020;
+    volatile icm_slv_arb_priority_reg_t slv_arb_priority;
+    volatile icm_mst_arqos_reg0_reg_t mst_arqos_reg0;
+    uint32_t reserved_02c;
+    volatile icm_mst_awqos_reg0_reg_t mst_awqos_reg0;
+    uint32_t reserved_034;
+    volatile icm_sys_addrhole_addr_reg_t sys_addrhole_addr;
+    volatile icm_sys_addrhole_info_reg_t sys_addrhole_info;
+    volatile icm_cpu_addrhole_addr_reg_t cpu_addrhole_addr;
+    volatile icm_cpu_addrhole_info_reg_t cpu_addrhole_info;
+    volatile icm_dlock_timeout_reg_t dlock_timeout;
+    uint32_t reserved_04c;
+    volatile icm_rdn_eco_cs_reg_t rdn_eco_cs;
+    volatile icm_rdn_eco_low_reg_t rdn_eco_low;
+    volatile icm_rdn_eco_high_reg_t rdn_eco_high;
+} icm_dev_t;
+
+extern icm_dev_t ICM_SYS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(icm_dev_t) == 0x5c, "Invalid size of icm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core0_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core0_reg.h
new file mode 100644
index 0000000000..0bfca792f2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core0_reg.h
@@ -0,0 +1,3592 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CORE0_LP_RTC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
+/** CORE0_CORE0_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_MAP_M  (CORE0_CORE0_LP_RTC_INT_MAP_V << CORE0_CORE0_LP_RTC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_MAP_S  0
+/** CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
+/** CORE0_CORE0_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_MAP_M  (CORE0_CORE0_LP_WDT_INT_MAP_V << CORE0_CORE0_LP_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_MAP_S  0
+/** CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_TIMER_REG_0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
+/** CORE0_CORE0_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_M  (CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_V << CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_S  0
+/** CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_TIMER_REG_1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc)
+/** CORE0_CORE0_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_M  (CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_V << CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_S  0
+/** CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_MB_HP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
+/** CORE0_CORE0_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_MAP_M  (CORE0_CORE0_MB_HP_INT_MAP_V << CORE0_CORE0_MB_HP_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_MAP_S  0
+/** CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_MB_LP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
+/** CORE0_CORE0_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_MAP_M  (CORE0_CORE0_MB_LP_INT_MAP_V << CORE0_CORE0_MB_LP_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_MAP_S  0
+/** CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PMU_REG_0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
+/** CORE0_CORE0_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_MAP_M  (CORE0_CORE0_PMU_REG_0_INT_MAP_V << CORE0_CORE0_PMU_REG_0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_MAP_S  0
+/** CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PMU_REG_1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c)
+/** CORE0_CORE0_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_MAP_M  (CORE0_CORE0_PMU_REG_1_INT_MAP_V << CORE0_CORE0_PMU_REG_1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_MAP_S  0
+/** CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_ANAPERI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
+/** CORE0_CORE0_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_MAP_M  (CORE0_CORE0_LP_ANAPERI_INT_MAP_V << CORE0_CORE0_LP_ANAPERI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_MAP_S  0
+/** CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_ADC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
+/** CORE0_CORE0_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_MAP_M  (CORE0_CORE0_LP_ADC_INT_MAP_V << CORE0_CORE0_LP_ADC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_MAP_S  0
+/** CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_GPIO_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
+/** CORE0_CORE0_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_MAP_M  (CORE0_CORE0_LP_GPIO_INT_MAP_V << CORE0_CORE0_LP_GPIO_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_MAP_S  0
+/** CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_I2C_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c)
+/** CORE0_CORE0_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_MAP_M  (CORE0_CORE0_LP_I2C_INT_MAP_V << CORE0_CORE0_LP_I2C_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_MAP_S  0
+/** CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_I2S_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
+/** CORE0_CORE0_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_MAP_M  (CORE0_CORE0_LP_I2S_INT_MAP_V << CORE0_CORE0_LP_I2S_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_MAP_S  0
+/** CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_SPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
+/** CORE0_CORE0_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_MAP_M  (CORE0_CORE0_LP_SPI_INT_MAP_V << CORE0_CORE0_LP_SPI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_MAP_S  0
+/** CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_TOUCH_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
+/** CORE0_CORE0_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_MAP_M  (CORE0_CORE0_LP_TOUCH_INT_MAP_V << CORE0_CORE0_LP_TOUCH_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_MAP_S  0
+/** CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_TSENS_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c)
+/** CORE0_CORE0_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_MAP_M  (CORE0_CORE0_LP_TSENS_INT_MAP_V << CORE0_CORE0_LP_TSENS_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_MAP_S  0
+/** CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_UART_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
+/** CORE0_CORE0_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_MAP_M  (CORE0_CORE0_LP_UART_INT_MAP_V << CORE0_CORE0_LP_UART_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_MAP_S  0
+/** CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_EFUSE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
+/** CORE0_CORE0_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_MAP_M  (CORE0_CORE0_LP_EFUSE_INT_MAP_V << CORE0_CORE0_LP_EFUSE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_MAP_S  0
+/** CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_SW_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
+/** CORE0_CORE0_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_MAP_M  (CORE0_CORE0_LP_SW_INT_MAP_V << CORE0_CORE0_LP_SW_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_MAP_S  0
+/** CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_SYSREG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c)
+/** CORE0_CORE0_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_MAP_M  (CORE0_CORE0_LP_SYSREG_INT_MAP_V << CORE0_CORE0_LP_SYSREG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_MAP_S  0
+/** CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_HUK_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
+/** CORE0_CORE0_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_MAP_M  (CORE0_CORE0_LP_HUK_INT_MAP_V << CORE0_CORE0_LP_HUK_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_MAP_S  0
+/** CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SYS_ICM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
+/** CORE0_CORE0_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_MAP_M  (CORE0_CORE0_SYS_ICM_INT_MAP_V << CORE0_CORE0_SYS_ICM_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_MAP_S  0
+/** CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_USB_DEVICE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
+/** CORE0_CORE0_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_MAP_M  (CORE0_CORE0_USB_DEVICE_INT_MAP_V << CORE0_CORE0_USB_DEVICE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_MAP_S  0
+/** CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SDIO_HOST_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c)
+/** CORE0_CORE0_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_MAP_M  (CORE0_CORE0_SDIO_HOST_INT_MAP_V << CORE0_CORE0_SDIO_HOST_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_MAP_S  0
+/** CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GDMA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
+/** CORE0_CORE0_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_MAP_M  (CORE0_CORE0_GDMA_INT_MAP_V << CORE0_CORE0_GDMA_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_MAP_S  0
+/** CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SPI2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
+/** CORE0_CORE0_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_MAP_M  (CORE0_CORE0_SPI2_INT_MAP_V << CORE0_CORE0_SPI2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_MAP_S  0
+/** CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SPI3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
+/** CORE0_CORE0_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_MAP_M  (CORE0_CORE0_SPI3_INT_MAP_V << CORE0_CORE0_SPI3_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_MAP_S  0
+/** CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I2S0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c)
+/** CORE0_CORE0_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_MAP_M  (CORE0_CORE0_I2S0_INT_MAP_V << CORE0_CORE0_I2S0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_MAP_S  0
+/** CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I2S1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
+/** CORE0_CORE0_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_MAP_M  (CORE0_CORE0_I2S1_INT_MAP_V << CORE0_CORE0_I2S1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_MAP_S  0
+/** CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I2S2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
+/** CORE0_CORE0_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_MAP_M  (CORE0_CORE0_I2S2_INT_MAP_V << CORE0_CORE0_I2S2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_MAP_S  0
+/** CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UHCI0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
+/** CORE0_CORE0_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_MAP_M  (CORE0_CORE0_UHCI0_INT_MAP_V << CORE0_CORE0_UHCI0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_MAP_S  0
+/** CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UART0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c)
+/** CORE0_CORE0_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UART0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART0_INT_MAP_M  (CORE0_CORE0_UART0_INT_MAP_V << CORE0_CORE0_UART0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UART0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART0_INT_MAP_S  0
+/** CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UART1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
+/** CORE0_CORE0_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UART1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART1_INT_MAP_M  (CORE0_CORE0_UART1_INT_MAP_V << CORE0_CORE0_UART1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UART1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART1_INT_MAP_S  0
+/** CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UART2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
+/** CORE0_CORE0_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UART2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART2_INT_MAP_M  (CORE0_CORE0_UART2_INT_MAP_V << CORE0_CORE0_UART2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UART2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART2_INT_MAP_S  0
+/** CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UART3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
+/** CORE0_CORE0_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UART3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART3_INT_MAP_M  (CORE0_CORE0_UART3_INT_MAP_V << CORE0_CORE0_UART3_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UART3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART3_INT_MAP_S  0
+/** CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UART4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
+/** CORE0_CORE0_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UART4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART4_INT_MAP_M  (CORE0_CORE0_UART4_INT_MAP_V << CORE0_CORE0_UART4_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UART4_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART4_INT_MAP_S  0
+/** CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LCD_CAM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
+/** CORE0_CORE0_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_MAP_M  (CORE0_CORE0_LCD_CAM_INT_MAP_V << CORE0_CORE0_LCD_CAM_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_MAP_S  0
+/** CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_ADC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
+/** CORE0_CORE0_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_ADC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ADC_INT_MAP_M  (CORE0_CORE0_ADC_INT_MAP_V << CORE0_CORE0_ADC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_ADC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ADC_INT_MAP_S  0
+/** CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PWM0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
+/** CORE0_CORE0_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_MAP_M  (CORE0_CORE0_PWM0_INT_MAP_V << CORE0_CORE0_PWM0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_MAP_S  0
+/** CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PWM1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
+/** CORE0_CORE0_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_MAP_M  (CORE0_CORE0_PWM1_INT_MAP_V << CORE0_CORE0_PWM1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_MAP_S  0
+/** CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CAN0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
+/** CORE0_CORE0_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_MAP_M  (CORE0_CORE0_CAN0_INT_MAP_V << CORE0_CORE0_CAN0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_MAP_S  0
+/** CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CAN1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4)
+/** CORE0_CORE0_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_MAP_M  (CORE0_CORE0_CAN1_INT_MAP_V << CORE0_CORE0_CAN1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_MAP_S  0
+/** CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CAN2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8)
+/** CORE0_CORE0_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_MAP_M  (CORE0_CORE0_CAN2_INT_MAP_V << CORE0_CORE0_CAN2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_MAP_S  0
+/** CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_RMT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
+/** CORE0_CORE0_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_RMT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_RMT_INT_MAP_M  (CORE0_CORE0_RMT_INT_MAP_V << CORE0_CORE0_RMT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_RMT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_RMT_INT_MAP_S  0
+/** CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I2C0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0)
+/** CORE0_CORE0_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_MAP_M  (CORE0_CORE0_I2C0_INT_MAP_V << CORE0_CORE0_I2C0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_MAP_S  0
+/** CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I2C1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4)
+/** CORE0_CORE0_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_MAP_M  (CORE0_CORE0_I2C1_INT_MAP_V << CORE0_CORE0_I2C1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_MAP_S  0
+/** CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP0_T0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8)
+/** CORE0_CORE0_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_MAP_M  (CORE0_CORE0_TIMERGRP0_T0_INT_MAP_V << CORE0_CORE0_TIMERGRP0_T0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP0_T1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc)
+/** CORE0_CORE0_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_MAP_M  (CORE0_CORE0_TIMERGRP0_T1_INT_MAP_V << CORE0_CORE0_TIMERGRP0_T1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP0_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
+/** CORE0_CORE0_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_M  (CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_V << CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP1_T0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
+/** CORE0_CORE0_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_MAP_M  (CORE0_CORE0_TIMERGRP1_T0_INT_MAP_V << CORE0_CORE0_TIMERGRP1_T0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP1_T1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
+/** CORE0_CORE0_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_MAP_M  (CORE0_CORE0_TIMERGRP1_T1_INT_MAP_V << CORE0_CORE0_TIMERGRP1_T1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP1_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
+/** CORE0_CORE0_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_M  (CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_V << CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LEDC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
+/** CORE0_CORE0_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_MAP_M  (CORE0_CORE0_LEDC_INT_MAP_V << CORE0_CORE0_LEDC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_MAP_S  0
+/** CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SYSTIMER_TARGET0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
+/** CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_M  (CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
+/** CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SYSTIMER_TARGET1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
+/** CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_M  (CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
+/** CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SYSTIMER_TARGET2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
+/** CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_M  (CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
+/** CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
+/** CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
+/** CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8)
+/** CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec)
+/** CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0)
+/** CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4)
+/** CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8)
+/** CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc)
+/** CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
+/** CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
+/** CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
+/** CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
+/** CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_RSA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
+/** CORE0_CORE0_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_RSA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_RSA_INT_MAP_M  (CORE0_CORE0_RSA_INT_MAP_V << CORE0_CORE0_RSA_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_RSA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_RSA_INT_MAP_S  0
+/** CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AES_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
+/** CORE0_CORE0_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AES_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AES_INT_MAP_M  (CORE0_CORE0_AES_INT_MAP_V << CORE0_CORE0_AES_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AES_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AES_INT_MAP_S  0
+/** CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SHA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
+/** CORE0_CORE0_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SHA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SHA_INT_MAP_M  (CORE0_CORE0_SHA_INT_MAP_V << CORE0_CORE0_SHA_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SHA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SHA_INT_MAP_S  0
+/** CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_ECC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
+/** CORE0_CORE0_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_ECC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ECC_INT_MAP_M  (CORE0_CORE0_ECC_INT_MAP_V << CORE0_CORE0_ECC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_ECC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ECC_INT_MAP_S  0
+/** CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_ECDSA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
+/** CORE0_CORE0_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_MAP_M  (CORE0_CORE0_ECDSA_INT_MAP_V << CORE0_CORE0_ECDSA_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_MAP_S  0
+/** CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_KM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
+/** CORE0_CORE0_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_KM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_KM_INT_MAP_M  (CORE0_CORE0_KM_INT_MAP_V << CORE0_CORE0_KM_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_KM_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_KM_INT_MAP_S  0
+/** CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GPIO_INT0_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
+/** CORE0_CORE0_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_MAP_M  (CORE0_CORE0_GPIO_INT0_MAP_V << CORE0_CORE0_GPIO_INT0_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_MAP_S  0
+/** CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC_V << CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GPIO_INT1_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
+/** CORE0_CORE0_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_MAP_M  (CORE0_CORE0_GPIO_INT1_MAP_V << CORE0_CORE0_GPIO_INT1_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_MAP_S  0
+/** CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC_V << CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GPIO_INT2_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
+/** CORE0_CORE0_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_MAP_M  (CORE0_CORE0_GPIO_INT2_MAP_V << CORE0_CORE0_GPIO_INT2_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_MAP_S  0
+/** CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC_V << CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GPIO_INT3_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
+/** CORE0_CORE0_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_MAP_M  (CORE0_CORE0_GPIO_INT3_MAP_V << CORE0_CORE0_GPIO_INT3_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_MAP_S  0
+/** CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC_V << CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GPIO_PAD_COMP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
+/** CORE0_CORE0_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_M  (CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_V << CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_S  0
+/** CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CPU_INT_FROM_CPU_0_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
+/** CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_S  0
+/** CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_V << CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CPU_INT_FROM_CPU_1_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
+/** CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_S  0
+/** CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_V << CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CPU_INT_FROM_CPU_2_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
+/** CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_S  0
+/** CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_V << CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CPU_INT_FROM_CPU_3_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
+/** CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_S  0
+/** CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_V << CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CACHE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
+/** CORE0_CORE0_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_MAP_M  (CORE0_CORE0_CACHE_INT_MAP_V << CORE0_CORE0_CACHE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_MAP_S  0
+/** CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_FLASH_MSPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
+/** CORE0_CORE0_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_MAP_M  (CORE0_CORE0_FLASH_MSPI_INT_MAP_V << CORE0_CORE0_FLASH_MSPI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_MAP_S  0
+/** CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CSI_BRIDGE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
+/** CORE0_CORE0_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_MAP_M  (CORE0_CORE0_CSI_BRIDGE_INT_MAP_V << CORE0_CORE0_CSI_BRIDGE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_MAP_S  0
+/** CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DSI_BRIDGE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
+/** CORE0_CORE0_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_MAP_M  (CORE0_CORE0_DSI_BRIDGE_INT_MAP_V << CORE0_CORE0_DSI_BRIDGE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_MAP_S  0
+/** CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CSI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c)
+/** CORE0_CORE0_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CSI_INT_MAP_M  (CORE0_CORE0_CSI_INT_MAP_V << CORE0_CORE0_CSI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CSI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CSI_INT_MAP_S  0
+/** CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DSI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
+/** CORE0_CORE0_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DSI_INT_MAP_M  (CORE0_CORE0_DSI_INT_MAP_V << CORE0_CORE0_DSI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DSI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DSI_INT_MAP_S  0
+/** CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GMII_PHY_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
+/** CORE0_CORE0_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_MAP_M  (CORE0_CORE0_GMII_PHY_INT_MAP_V << CORE0_CORE0_GMII_PHY_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_MAP_S  0
+/** CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
+/** CORE0_CORE0_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LPI_INT_MAP_M  (CORE0_CORE0_LPI_INT_MAP_V << CORE0_CORE0_LPI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LPI_INT_MAP_S  0
+/** CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PMT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c)
+/** CORE0_CORE0_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PMT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMT_INT_MAP_M  (CORE0_CORE0_PMT_INT_MAP_V << CORE0_CORE0_PMT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PMT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMT_INT_MAP_S  0
+/** CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SBD_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
+/** CORE0_CORE0_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SBD_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SBD_INT_MAP_M  (CORE0_CORE0_SBD_INT_MAP_V << CORE0_CORE0_SBD_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SBD_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SBD_INT_MAP_S  0
+/** CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_USB_OTG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
+/** CORE0_CORE0_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_MAP_M  (CORE0_CORE0_USB_OTG_INT_MAP_V << CORE0_CORE0_USB_OTG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_MAP_S  0
+/** CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
+/** CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  (CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S  0
+/** CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6];
+ *  default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7];
+ *  default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_JPEG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17c)
+/** CORE0_CORE0_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_MAP_M  (CORE0_CORE0_JPEG_INT_MAP_V << CORE0_CORE0_JPEG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_MAP_S  0
+/** CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PPA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
+/** CORE0_CORE0_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PPA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PPA_INT_MAP_M  (CORE0_CORE0_PPA_INT_MAP_V << CORE0_CORE0_PPA_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PPA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PPA_INT_MAP_S  0
+/** CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CORE0_TRACE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
+/** CORE0_CORE0_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_MAP_M  (CORE0_CORE0_CORE0_TRACE_INT_MAP_V << CORE0_CORE0_CORE0_TRACE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_MAP_S  0
+/** CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CORE1_TRACE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
+/** CORE0_CORE0_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_MAP_M  (CORE0_CORE0_CORE1_TRACE_INT_MAP_V << CORE0_CORE0_CORE1_TRACE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_MAP_S  0
+/** CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_HP_CORE_CTRL_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18c)
+/** CORE0_CORE0_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_MAP_M  (CORE0_CORE0_HP_CORE_CTRL_INT_MAP_V << CORE0_CORE0_HP_CORE_CTRL_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_MAP_S  0
+/** CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_ISP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
+/** CORE0_CORE0_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_ISP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ISP_INT_MAP_M  (CORE0_CORE0_ISP_INT_MAP_V << CORE0_CORE0_ISP_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_ISP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ISP_INT_MAP_S  0
+/** CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I3C_MST_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
+/** CORE0_CORE0_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_MAP_M  (CORE0_CORE0_I3C_MST_INT_MAP_V << CORE0_CORE0_I3C_MST_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_MAP_S  0
+/** CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I3C_SLV_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
+/** CORE0_CORE0_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_MAP_M  (CORE0_CORE0_I3C_SLV_INT_MAP_V << CORE0_CORE0_I3C_SLV_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_MAP_S  0
+/** CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_USB_OTG11_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c)
+/** CORE0_CORE0_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_MAP_M  (CORE0_CORE0_USB_OTG11_INT_MAP_V << CORE0_CORE0_USB_OTG11_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_MAP_S  0
+/** CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a0)
+/** CORE0_CORE0_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_M  (CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a4)
+/** CORE0_CORE0_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_M  (CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a8)
+/** CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ac)
+/** CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b0)
+/** CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PSRAM_MSPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b4)
+/** CORE0_CORE0_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_MAP_M  (CORE0_CORE0_PSRAM_MSPI_INT_MAP_V << CORE0_CORE0_PSRAM_MSPI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_MAP_S  0
+/** CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_HP_SYSREG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b8)
+/** CORE0_CORE0_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_MAP_M  (CORE0_CORE0_HP_SYSREG_INT_MAP_V << CORE0_CORE0_HP_SYSREG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_MAP_S  0
+/** CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PCNT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1bc)
+/** CORE0_CORE0_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_MAP_M  (CORE0_CORE0_PCNT_INT_MAP_V << CORE0_CORE0_PCNT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_MAP_S  0
+/** CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_HP_PAU_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c0)
+/** CORE0_CORE0_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_MAP_M  (CORE0_CORE0_HP_PAU_INT_MAP_V << CORE0_CORE0_HP_PAU_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_MAP_S  0
+/** CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_HP_PARLIO_RX_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c4)
+/** CORE0_CORE0_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_MAP_M  (CORE0_CORE0_HP_PARLIO_RX_INT_MAP_V << CORE0_CORE0_HP_PARLIO_RX_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_MAP_S  0
+/** CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_HP_PARLIO_TX_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c8)
+/** CORE0_CORE0_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_MAP_M  (CORE0_CORE0_HP_PARLIO_TX_INT_MAP_V << CORE0_CORE0_HP_PARLIO_TX_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_MAP_S  0
+/** CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1cc)
+/** CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d0)
+/** CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d4)
+/** CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d8)
+/** CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1dc)
+/** CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e0)
+/** CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e4)
+/** CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e8)
+/** CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ec)
+/** CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f0)
+/** CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f4)
+/** CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_REG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f8)
+/** CORE0_CORE0_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_MAP_M  (CORE0_CORE0_H264_REG_INT_MAP_V << CORE0_CORE0_H264_REG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_MAP_S  0
+/** CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_ASSIST_DEBUG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1fc)
+/** CORE0_CORE0_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_MAP_M  (CORE0_CORE0_ASSIST_DEBUG_INT_MAP_V << CORE0_CORE0_ASSIST_DEBUG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_MAP_S  0
+/** CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_INTR_STATUS_REG_0_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x200)
+/** CORE0_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_0_M  (CORE0_CORE0_INTR_STATUS_0_V << CORE0_CORE0_INTR_STATUS_0_S)
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_0_S  0
+
+/** CORE0_INTR_STATUS_REG_1_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x204)
+/** CORE0_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_1_M  (CORE0_CORE0_INTR_STATUS_1_V << CORE0_CORE0_INTR_STATUS_1_S)
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_1_S  0
+
+/** CORE0_INTR_STATUS_REG_2_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x208)
+/** CORE0_CORE0_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_2_M  (CORE0_CORE0_INTR_STATUS_2_V << CORE0_CORE0_INTR_STATUS_2_S)
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_2_S  0
+
+/** CORE0_INTR_STATUS_REG_3_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20c)
+/** CORE0_CORE0_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_3_M  (CORE0_CORE0_INTR_STATUS_3_V << CORE0_CORE0_INTR_STATUS_3_S)
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_3_S  0
+
+/** CORE0_CLOCK_GATE_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x210)
+/** CORE0_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_REG_CLK_EN    (BIT(0))
+#define INTERRUPT_CORE0_CORE0_REG_CLK_EN_M  (CORE0_CORE0_REG_CLK_EN_V << CORE0_CORE0_REG_CLK_EN_S)
+#define INTERRUPT_CORE0_CORE0_REG_CLK_EN_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_REG_CLK_EN_S  0
+
+/** CORE0_DMA2D_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x214)
+/** CORE0_CORE0_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_MAP_M  (CORE0_CORE0_DMA2D_IN_CH2_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_OUT_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x218)
+/** CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PERF_MON_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PERF_MON_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x21c)
+/** CORE0_CORE0_AXI_PERF_MON_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_MAP_M  (CORE0_CORE0_AXI_PERF_MON_INT_MAP_V << CORE0_CORE0_AXI_PERF_MON_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_INTR_STATUS_REG_4_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x220)
+/** CORE0_CORE0_INTR_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_4_M  (CORE0_CORE0_INTR_STATUS_4_V << CORE0_CORE0_INTR_STATUS_4_S)
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_4_S  0
+
+/** CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x228)
+/** CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_M  (CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_V << CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_S  0
+
+/** CORE0_INTR_SEC_STATUS_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SEC_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x22c)
+/** CORE0_CORE0_INTR_SEC_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SEC_STATUS    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SEC_STATUS_M  (CORE0_CORE0_INTR_SEC_STATUS_V << CORE0_CORE0_INTR_SEC_STATUS_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SEC_STATUS_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SEC_STATUS_S  0
+
+/** CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x230)
+/** CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_M  (CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_V << CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_S  0
+
+/** CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x234)
+/** CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_M  (CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_V << CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_S  0
+
+/** CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x238)
+/** CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_M  (CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_V << CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_S  0
+
+/** CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x23c)
+/** CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_M  (CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_V << CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_S  0
+
+/** CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x240)
+/** CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_M  (CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_V << CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_S  0
+
+/** CORE0_INTERRUPT_REG_DATE_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3fc)
+/** CORE0_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 38806144;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTERRUPT_REG_DATE_M  (CORE0_CORE0_INTERRUPT_REG_DATE_V << CORE0_CORE0_INTERRUPT_REG_DATE_S)
+#define INTERRUPT_CORE0_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTERRUPT_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core0_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core0_struct.h
new file mode 100644
index 0000000000..3b33d6c820
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core0_struct.h
@@ -0,0 +1,3528 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: CORE0 LP RTC INT MAP REG */
+/** Type of lp_rtc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_rtc_int_map:6;
+        /** core0_lp_rtc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_rtc_int_src_pass_in_sec:1;
+        /** core0_lp_rtc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_rtc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_rtc_int_map_reg_t;
+
+
+/** Group: CORE0 LP WDT INT MAP REG */
+/** Type of lp_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_wdt_int_map:6;
+        /** core0_lp_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_wdt_int_src_pass_in_sec:1;
+        /** core0_lp_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_wdt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_wdt_int_map_reg_t;
+
+
+/** Group: CORE0 LP TIMER REG 0 INT MAP REG */
+/** Type of lp_timer_reg_0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_timer_reg_0_int_map:6;
+        /** core0_lp_timer_reg_0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_timer_reg_0_int_src_pass_in_sec:1;
+        /** core0_lp_timer_reg_0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_timer_reg_0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_timer_reg_0_int_map_reg_t;
+
+
+/** Group: CORE0 LP TIMER REG 1 INT MAP REG */
+/** Type of lp_timer_reg_1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_timer_reg_1_int_map:6;
+        /** core0_lp_timer_reg_1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_timer_reg_1_int_src_pass_in_sec:1;
+        /** core0_lp_timer_reg_1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_timer_reg_1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_timer_reg_1_int_map_reg_t;
+
+
+/** Group: CORE0 MB HP INT MAP REG */
+/** Type of mb_hp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_mb_hp_int_map:6;
+        /** core0_mb_hp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_mb_hp_int_src_pass_in_sec:1;
+        /** core0_mb_hp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_mb_hp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_mb_hp_int_map_reg_t;
+
+
+/** Group: CORE0 MB LP INT MAP REG */
+/** Type of mb_lp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_mb_lp_int_map:6;
+        /** core0_mb_lp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_mb_lp_int_src_pass_in_sec:1;
+        /** core0_mb_lp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_mb_lp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_mb_lp_int_map_reg_t;
+
+
+/** Group: CORE0 PMU REG 0 INT MAP REG */
+/** Type of pmu_reg_0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pmu_reg_0_int_map:6;
+        /** core0_pmu_reg_0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmu_reg_0_int_src_pass_in_sec:1;
+        /** core0_pmu_reg_0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmu_reg_0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pmu_reg_0_int_map_reg_t;
+
+
+/** Group: CORE0 PMU REG 1 INT MAP REG */
+/** Type of pmu_reg_1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pmu_reg_1_int_map:6;
+        /** core0_pmu_reg_1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmu_reg_1_int_src_pass_in_sec:1;
+        /** core0_pmu_reg_1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmu_reg_1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pmu_reg_1_int_map_reg_t;
+
+
+/** Group: CORE0 LP ANAPERI INT MAP REG */
+/** Type of lp_anaperi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_anaperi_int_map:6;
+        /** core0_lp_anaperi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_anaperi_int_src_pass_in_sec:1;
+        /** core0_lp_anaperi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_anaperi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_anaperi_int_map_reg_t;
+
+
+/** Group: CORE0 LP ADC INT MAP REG */
+/** Type of lp_adc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_adc_int_map:6;
+        /** core0_lp_adc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_adc_int_src_pass_in_sec:1;
+        /** core0_lp_adc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_adc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_adc_int_map_reg_t;
+
+
+/** Group: CORE0 LP GPIO INT MAP REG */
+/** Type of lp_gpio_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_gpio_int_map:6;
+        /** core0_lp_gpio_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_gpio_int_src_pass_in_sec:1;
+        /** core0_lp_gpio_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_gpio_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_gpio_int_map_reg_t;
+
+
+/** Group: CORE0 LP I2C INT MAP REG */
+/** Type of lp_i2c_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_i2c_int_map:6;
+        /** core0_lp_i2c_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_i2c_int_src_pass_in_sec:1;
+        /** core0_lp_i2c_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_i2c_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_i2c_int_map_reg_t;
+
+
+/** Group: CORE0 LP I2S INT MAP REG */
+/** Type of lp_i2s_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_i2s_int_map:6;
+        /** core0_lp_i2s_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_i2s_int_src_pass_in_sec:1;
+        /** core0_lp_i2s_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_i2s_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_i2s_int_map_reg_t;
+
+
+/** Group: CORE0 LP SPI INT MAP REG */
+/** Type of lp_spi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_spi_int_map:6;
+        /** core0_lp_spi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_spi_int_src_pass_in_sec:1;
+        /** core0_lp_spi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_spi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_spi_int_map_reg_t;
+
+
+/** Group: CORE0 LP TOUCH INT MAP REG */
+/** Type of lp_touch_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_touch_int_map:6;
+        /** core0_lp_touch_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_touch_int_src_pass_in_sec:1;
+        /** core0_lp_touch_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_touch_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_touch_int_map_reg_t;
+
+
+/** Group: CORE0 LP TSENS INT MAP REG */
+/** Type of lp_tsens_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_tsens_int_map:6;
+        /** core0_lp_tsens_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_tsens_int_src_pass_in_sec:1;
+        /** core0_lp_tsens_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_tsens_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_tsens_int_map_reg_t;
+
+
+/** Group: CORE0 LP UART INT MAP REG */
+/** Type of lp_uart_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_uart_int_map:6;
+        /** core0_lp_uart_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_uart_int_src_pass_in_sec:1;
+        /** core0_lp_uart_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_uart_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_uart_int_map_reg_t;
+
+
+/** Group: CORE0 LP EFUSE INT MAP REG */
+/** Type of lp_efuse_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_efuse_int_map:6;
+        /** core0_lp_efuse_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_efuse_int_src_pass_in_sec:1;
+        /** core0_lp_efuse_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_efuse_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_efuse_int_map_reg_t;
+
+
+/** Group: CORE0 LP SW INT MAP REG */
+/** Type of lp_sw_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_sw_int_map:6;
+        /** core0_lp_sw_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_sw_int_src_pass_in_sec:1;
+        /** core0_lp_sw_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_sw_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_sw_int_map_reg_t;
+
+
+/** Group: CORE0 LP SYSREG INT MAP REG */
+/** Type of lp_sysreg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_sysreg_int_map:6;
+        /** core0_lp_sysreg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_sysreg_int_src_pass_in_sec:1;
+        /** core0_lp_sysreg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_sysreg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_sysreg_int_map_reg_t;
+
+
+/** Group: CORE0 LP HUK INT MAP REG */
+/** Type of lp_huk_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_huk_int_map:6;
+        /** core0_lp_huk_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_huk_int_src_pass_in_sec:1;
+        /** core0_lp_huk_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_huk_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_huk_int_map_reg_t;
+
+
+/** Group: CORE0 SYS ICM INT MAP REG */
+/** Type of sys_icm_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_sys_icm_int_map:6;
+        /** core0_sys_icm_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sys_icm_int_src_pass_in_sec:1;
+        /** core0_sys_icm_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sys_icm_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_sys_icm_int_map_reg_t;
+
+
+/** Group: CORE0 USB DEVICE INT MAP REG */
+/** Type of usb_device_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_usb_device_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_usb_device_int_map:6;
+        /** core0_usb_device_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_device_int_src_pass_in_sec:1;
+        /** core0_usb_device_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_device_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_usb_device_int_map_reg_t;
+
+
+/** Group: CORE0 SDIO HOST INT MAP REG */
+/** Type of sdio_host_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_sdio_host_int_map:6;
+        /** core0_sdio_host_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sdio_host_int_src_pass_in_sec:1;
+        /** core0_sdio_host_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sdio_host_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_sdio_host_int_map_reg_t;
+
+
+/** Group: CORE0 GDMA INT MAP REG */
+/** Type of gdma_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gdma_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gdma_int_map:6;
+        /** core0_gdma_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gdma_int_src_pass_in_sec:1;
+        /** core0_gdma_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gdma_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gdma_int_map_reg_t;
+
+
+/** Group: CORE0 SPI2 INT MAP REG */
+/** Type of spi2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_spi2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_spi2_int_map:6;
+        /** core0_spi2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_spi2_int_src_pass_in_sec:1;
+        /** core0_spi2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_spi2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_spi2_int_map_reg_t;
+
+
+/** Group: CORE0 SPI3 INT MAP REG */
+/** Type of spi3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_spi3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_spi3_int_map:6;
+        /** core0_spi3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_spi3_int_src_pass_in_sec:1;
+        /** core0_spi3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_spi3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_spi3_int_map_reg_t;
+
+
+/** Group: CORE0 I2S0 INT MAP REG */
+/** Type of i2s0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i2s0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i2s0_int_map:6;
+        /** core0_i2s0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s0_int_src_pass_in_sec:1;
+        /** core0_i2s0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i2s0_int_map_reg_t;
+
+
+/** Group: CORE0 I2S1 INT MAP REG */
+/** Type of i2s1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i2s1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i2s1_int_map:6;
+        /** core0_i2s1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s1_int_src_pass_in_sec:1;
+        /** core0_i2s1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i2s1_int_map_reg_t;
+
+
+/** Group: CORE0 I2S2 INT MAP REG */
+/** Type of i2s2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i2s2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i2s2_int_map:6;
+        /** core0_i2s2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s2_int_src_pass_in_sec:1;
+        /** core0_i2s2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i2s2_int_map_reg_t;
+
+
+/** Group: CORE0 UHCI0 INT MAP REG */
+/** Type of uhci0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uhci0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uhci0_int_map:6;
+        /** core0_uhci0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uhci0_int_src_pass_in_sec:1;
+        /** core0_uhci0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uhci0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uhci0_int_map_reg_t;
+
+
+/** Group: CORE0 UART0 INT MAP REG */
+/** Type of uart0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uart0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uart0_int_map:6;
+        /** core0_uart0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart0_int_src_pass_in_sec:1;
+        /** core0_uart0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uart0_int_map_reg_t;
+
+
+/** Group: CORE0 UART1 INT MAP REG */
+/** Type of uart1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uart1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uart1_int_map:6;
+        /** core0_uart1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart1_int_src_pass_in_sec:1;
+        /** core0_uart1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uart1_int_map_reg_t;
+
+
+/** Group: CORE0 UART2 INT MAP REG */
+/** Type of uart2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uart2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uart2_int_map:6;
+        /** core0_uart2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart2_int_src_pass_in_sec:1;
+        /** core0_uart2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uart2_int_map_reg_t;
+
+
+/** Group: CORE0 UART3 INT MAP REG */
+/** Type of uart3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uart3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uart3_int_map:6;
+        /** core0_uart3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart3_int_src_pass_in_sec:1;
+        /** core0_uart3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uart3_int_map_reg_t;
+
+
+/** Group: CORE0 UART4 INT MAP REG */
+/** Type of uart4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uart4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uart4_int_map:6;
+        /** core0_uart4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart4_int_src_pass_in_sec:1;
+        /** core0_uart4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart4_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uart4_int_map_reg_t;
+
+
+/** Group: CORE0 LCD CAM INT MAP REG */
+/** Type of lcd_cam_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lcd_cam_int_map:6;
+        /** core0_lcd_cam_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lcd_cam_int_src_pass_in_sec:1;
+        /** core0_lcd_cam_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lcd_cam_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lcd_cam_int_map_reg_t;
+
+
+/** Group: CORE0 ADC INT MAP REG */
+/** Type of adc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_adc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_adc_int_map:6;
+        /** core0_adc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_adc_int_src_pass_in_sec:1;
+        /** core0_adc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_adc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_adc_int_map_reg_t;
+
+
+/** Group: CORE0 PWM0 INT MAP REG */
+/** Type of pwm0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pwm0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pwm0_int_map:6;
+        /** core0_pwm0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pwm0_int_src_pass_in_sec:1;
+        /** core0_pwm0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pwm0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pwm0_int_map_reg_t;
+
+
+/** Group: CORE0 PWM1 INT MAP REG */
+/** Type of pwm1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pwm1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pwm1_int_map:6;
+        /** core0_pwm1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pwm1_int_src_pass_in_sec:1;
+        /** core0_pwm1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pwm1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pwm1_int_map_reg_t;
+
+
+/** Group: CORE0 CAN0 INT MAP REG */
+/** Type of can0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_can0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_can0_int_map:6;
+        /** core0_can0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can0_int_src_pass_in_sec:1;
+        /** core0_can0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_can0_int_map_reg_t;
+
+
+/** Group: CORE0 CAN1 INT MAP REG */
+/** Type of can1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_can1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_can1_int_map:6;
+        /** core0_can1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can1_int_src_pass_in_sec:1;
+        /** core0_can1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_can1_int_map_reg_t;
+
+
+/** Group: CORE0 CAN2 INT MAP REG */
+/** Type of can2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_can2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_can2_int_map:6;
+        /** core0_can2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can2_int_src_pass_in_sec:1;
+        /** core0_can2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_can2_int_map_reg_t;
+
+
+/** Group: CORE0 RMT INT MAP REG */
+/** Type of rmt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_rmt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_rmt_int_map:6;
+        /** core0_rmt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_rmt_int_src_pass_in_sec:1;
+        /** core0_rmt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_rmt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_rmt_int_map_reg_t;
+
+
+/** Group: CORE0 I2C0 INT MAP REG */
+/** Type of i2c0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i2c0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i2c0_int_map:6;
+        /** core0_i2c0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2c0_int_src_pass_in_sec:1;
+        /** core0_i2c0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2c0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i2c0_int_map_reg_t;
+
+
+/** Group: CORE0 I2C1 INT MAP REG */
+/** Type of i2c1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i2c1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i2c1_int_map:6;
+        /** core0_i2c1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2c1_int_src_pass_in_sec:1;
+        /** core0_i2c1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2c1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i2c1_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP0 T0 INT MAP REG */
+/** Type of timergrp0_t0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp0_t0_int_map:6;
+        /** core0_timergrp0_t0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_t0_int_src_pass_in_sec:1;
+        /** core0_timergrp0_t0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_t0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp0_t0_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP0 T1 INT MAP REG */
+/** Type of timergrp0_t1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp0_t1_int_map:6;
+        /** core0_timergrp0_t1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_t1_int_src_pass_in_sec:1;
+        /** core0_timergrp0_t1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_t1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp0_t1_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP0 WDT INT MAP REG */
+/** Type of timergrp0_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp0_wdt_int_map:6;
+        /** core0_timergrp0_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_wdt_int_src_pass_in_sec:1;
+        /** core0_timergrp0_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_wdt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp0_wdt_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP1 T0 INT MAP REG */
+/** Type of timergrp1_t0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp1_t0_int_map:6;
+        /** core0_timergrp1_t0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_t0_int_src_pass_in_sec:1;
+        /** core0_timergrp1_t0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_t0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp1_t0_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP1 T1 INT MAP REG */
+/** Type of timergrp1_t1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp1_t1_int_map:6;
+        /** core0_timergrp1_t1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_t1_int_src_pass_in_sec:1;
+        /** core0_timergrp1_t1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_t1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp1_t1_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP1 WDT INT MAP REG */
+/** Type of timergrp1_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp1_wdt_int_map:6;
+        /** core0_timergrp1_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_wdt_int_src_pass_in_sec:1;
+        /** core0_timergrp1_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_wdt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp1_wdt_int_map_reg_t;
+
+
+/** Group: CORE0 LEDC INT MAP REG */
+/** Type of ledc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ledc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ledc_int_map:6;
+        /** core0_ledc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ledc_int_src_pass_in_sec:1;
+        /** core0_ledc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ledc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ledc_int_map_reg_t;
+
+
+/** Group: CORE0 SYSTIMER TARGET0 INT MAP REG */
+/** Type of systimer_target0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_systimer_target0_int_map:6;
+        /** core0_systimer_target0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target0_int_src_pass_in_sec:1;
+        /** core0_systimer_target0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_systimer_target0_int_map_reg_t;
+
+
+/** Group: CORE0 SYSTIMER TARGET1 INT MAP REG */
+/** Type of systimer_target1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_systimer_target1_int_map:6;
+        /** core0_systimer_target1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target1_int_src_pass_in_sec:1;
+        /** core0_systimer_target1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_systimer_target1_int_map_reg_t;
+
+
+/** Group: CORE0 SYSTIMER TARGET2 INT MAP REG */
+/** Type of systimer_target2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_systimer_target2_int_map:6;
+        /** core0_systimer_target2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target2_int_src_pass_in_sec:1;
+        /** core0_systimer_target2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_systimer_target2_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA IN CH0 INT MAP REG */
+/** Type of ahb_pdma_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_in_ch0_int_map:6;
+        /** core0_ahb_pdma_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch0_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA IN CH1 INT MAP REG */
+/** Type of ahb_pdma_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_in_ch1_int_map:6;
+        /** core0_ahb_pdma_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch1_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA IN CH2 INT MAP REG */
+/** Type of ahb_pdma_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_in_ch2_int_map:6;
+        /** core0_ahb_pdma_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch2_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA OUT CH0 INT MAP REG */
+/** Type of ahb_pdma_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_out_ch0_int_map:6;
+        /** core0_ahb_pdma_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch0_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA OUT CH1 INT MAP REG */
+/** Type of ahb_pdma_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_out_ch1_int_map:6;
+        /** core0_ahb_pdma_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch1_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA OUT CH2 INT MAP REG */
+/** Type of ahb_pdma_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_out_ch2_int_map:6;
+        /** core0_ahb_pdma_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch2_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA IN CH0 INT MAP REG */
+/** Type of axi_pdma_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_in_ch0_int_map:6;
+        /** core0_axi_pdma_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch0_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA IN CH1 INT MAP REG */
+/** Type of axi_pdma_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_in_ch1_int_map:6;
+        /** core0_axi_pdma_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch1_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA IN CH2 INT MAP REG */
+/** Type of axi_pdma_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_in_ch2_int_map:6;
+        /** core0_axi_pdma_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch2_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA OUT CH0 INT MAP REG */
+/** Type of axi_pdma_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_out_ch0_int_map:6;
+        /** core0_axi_pdma_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch0_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA OUT CH1 INT MAP REG */
+/** Type of axi_pdma_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_out_ch1_int_map:6;
+        /** core0_axi_pdma_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch1_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA OUT CH2 INT MAP REG */
+/** Type of axi_pdma_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_out_ch2_int_map:6;
+        /** core0_axi_pdma_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch2_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 RSA INT MAP REG */
+/** Type of rsa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_rsa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_rsa_int_map:6;
+        /** core0_rsa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_rsa_int_src_pass_in_sec:1;
+        /** core0_rsa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_rsa_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_rsa_int_map_reg_t;
+
+
+/** Group: CORE0 AES INT MAP REG */
+/** Type of aes_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_aes_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_aes_int_map:6;
+        /** core0_aes_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_aes_int_src_pass_in_sec:1;
+        /** core0_aes_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_aes_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_aes_int_map_reg_t;
+
+
+/** Group: CORE0 SHA INT MAP REG */
+/** Type of sha_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_sha_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_sha_int_map:6;
+        /** core0_sha_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sha_int_src_pass_in_sec:1;
+        /** core0_sha_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sha_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_sha_int_map_reg_t;
+
+
+/** Group: CORE0 ECC INT MAP REG */
+/** Type of ecc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ecc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ecc_int_map:6;
+        /** core0_ecc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ecc_int_src_pass_in_sec:1;
+        /** core0_ecc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ecc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ecc_int_map_reg_t;
+
+
+/** Group: CORE0 ECDSA INT MAP REG */
+/** Type of ecdsa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ecdsa_int_map:6;
+        /** core0_ecdsa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ecdsa_int_src_pass_in_sec:1;
+        /** core0_ecdsa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ecdsa_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ecdsa_int_map_reg_t;
+
+
+/** Group: CORE0 KM INT MAP REG */
+/** Type of km_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_km_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_km_int_map:6;
+        /** core0_km_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_km_int_src_pass_in_sec:1;
+        /** core0_km_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_km_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_km_int_map_reg_t;
+
+
+/** Group: CORE0 GPIO INT0 MAP REG */
+/** Type of gpio_int0_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gpio_int0_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gpio_int0_map:6;
+        /** core0_gpio_int0_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int0_src_pass_in_sec:1;
+        /** core0_gpio_int0_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int0_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gpio_int0_map_reg_t;
+
+
+/** Group: CORE0 GPIO INT1 MAP REG */
+/** Type of gpio_int1_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gpio_int1_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gpio_int1_map:6;
+        /** core0_gpio_int1_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int1_src_pass_in_sec:1;
+        /** core0_gpio_int1_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int1_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gpio_int1_map_reg_t;
+
+
+/** Group: CORE0 GPIO INT2 MAP REG */
+/** Type of gpio_int2_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gpio_int2_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gpio_int2_map:6;
+        /** core0_gpio_int2_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int2_src_pass_in_sec:1;
+        /** core0_gpio_int2_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int2_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gpio_int2_map_reg_t;
+
+
+/** Group: CORE0 GPIO INT3 MAP REG */
+/** Type of gpio_int3_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gpio_int3_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gpio_int3_map:6;
+        /** core0_gpio_int3_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int3_src_pass_in_sec:1;
+        /** core0_gpio_int3_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int3_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gpio_int3_map_reg_t;
+
+
+/** Group: CORE0 GPIO PAD COMP INT MAP REG */
+/** Type of gpio_pad_comp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gpio_pad_comp_int_map:6;
+        /** core0_gpio_pad_comp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_pad_comp_int_src_pass_in_sec:1;
+        /** core0_gpio_pad_comp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_pad_comp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gpio_pad_comp_int_map_reg_t;
+
+
+/** Group: CORE0 CPU INT FROM CPU 0 MAP REG */
+/** Type of cpu_int_from_cpu_0_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_cpu_int_from_cpu_0_map:6;
+        /** core0_cpu_int_from_cpu_0_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_0_src_pass_in_sec:1;
+        /** core0_cpu_int_from_cpu_0_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_0_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_cpu_int_from_cpu_0_map_reg_t;
+
+
+/** Group: CORE0 CPU INT FROM CPU 1 MAP REG */
+/** Type of cpu_int_from_cpu_1_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_cpu_int_from_cpu_1_map:6;
+        /** core0_cpu_int_from_cpu_1_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_1_src_pass_in_sec:1;
+        /** core0_cpu_int_from_cpu_1_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_1_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_cpu_int_from_cpu_1_map_reg_t;
+
+
+/** Group: CORE0 CPU INT FROM CPU 2 MAP REG */
+/** Type of cpu_int_from_cpu_2_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_cpu_int_from_cpu_2_map:6;
+        /** core0_cpu_int_from_cpu_2_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_2_src_pass_in_sec:1;
+        /** core0_cpu_int_from_cpu_2_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_2_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_cpu_int_from_cpu_2_map_reg_t;
+
+
+/** Group: CORE0 CPU INT FROM CPU 3 MAP REG */
+/** Type of cpu_int_from_cpu_3_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_cpu_int_from_cpu_3_map:6;
+        /** core0_cpu_int_from_cpu_3_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_3_src_pass_in_sec:1;
+        /** core0_cpu_int_from_cpu_3_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_3_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_cpu_int_from_cpu_3_map_reg_t;
+
+
+/** Group: CORE0 CACHE INT MAP REG */
+/** Type of cache_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_cache_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_cache_int_map:6;
+        /** core0_cache_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cache_int_src_pass_in_sec:1;
+        /** core0_cache_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cache_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_cache_int_map_reg_t;
+
+
+/** Group: CORE0 FLASH MSPI INT MAP REG */
+/** Type of flash_mspi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_flash_mspi_int_map:6;
+        /** core0_flash_mspi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_flash_mspi_int_src_pass_in_sec:1;
+        /** core0_flash_mspi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_flash_mspi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_flash_mspi_int_map_reg_t;
+
+
+/** Group: CORE0 CSI BRIDGE INT MAP REG */
+/** Type of csi_bridge_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_csi_bridge_int_map:6;
+        /** core0_csi_bridge_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_csi_bridge_int_src_pass_in_sec:1;
+        /** core0_csi_bridge_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_csi_bridge_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_csi_bridge_int_map_reg_t;
+
+
+/** Group: CORE0 DSI BRIDGE INT MAP REG */
+/** Type of dsi_bridge_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dsi_bridge_int_map:6;
+        /** core0_dsi_bridge_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dsi_bridge_int_src_pass_in_sec:1;
+        /** core0_dsi_bridge_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dsi_bridge_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dsi_bridge_int_map_reg_t;
+
+
+/** Group: CORE0 CSI INT MAP REG */
+/** Type of csi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_csi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_csi_int_map:6;
+        /** core0_csi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_csi_int_src_pass_in_sec:1;
+        /** core0_csi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_csi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_csi_int_map_reg_t;
+
+
+/** Group: CORE0 DSI INT MAP REG */
+/** Type of dsi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dsi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dsi_int_map:6;
+        /** core0_dsi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dsi_int_src_pass_in_sec:1;
+        /** core0_dsi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dsi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dsi_int_map_reg_t;
+
+
+/** Group: CORE0 GMII PHY INT MAP REG */
+/** Type of gmii_phy_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gmii_phy_int_map:6;
+        /** core0_gmii_phy_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gmii_phy_int_src_pass_in_sec:1;
+        /** core0_gmii_phy_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gmii_phy_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gmii_phy_int_map_reg_t;
+
+
+/** Group: CORE0 LPI INT MAP REG */
+/** Type of lpi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lpi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lpi_int_map:6;
+        /** core0_lpi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lpi_int_src_pass_in_sec:1;
+        /** core0_lpi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lpi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lpi_int_map_reg_t;
+
+
+/** Group: CORE0 PMT INT MAP REG */
+/** Type of pmt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pmt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pmt_int_map:6;
+        /** core0_pmt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmt_int_src_pass_in_sec:1;
+        /** core0_pmt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pmt_int_map_reg_t;
+
+
+/** Group: CORE0 SBD INT MAP REG */
+/** Type of sbd_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_sbd_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_sbd_int_map:6;
+        /** core0_sbd_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sbd_int_src_pass_in_sec:1;
+        /** core0_sbd_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sbd_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_sbd_int_map_reg_t;
+
+
+/** Group: CORE0 USB OTG INT MAP REG */
+/** Type of usb_otg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_usb_otg_int_map:6;
+        /** core0_usb_otg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg_int_src_pass_in_sec:1;
+        /** core0_usb_otg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_usb_otg_int_map_reg_t;
+
+
+/** Group: CORE0 USB OTG ENDP MULTI PROC INT MAP REG */
+/** Type of usb_otg_endp_multi_proc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_usb_otg_endp_multi_proc_int_map:6;
+        /** core0_usb_otg_endp_multi_proc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg_endp_multi_proc_int_src_pass_in_sec:1;
+        /** core0_usb_otg_endp_multi_proc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg_endp_multi_proc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_usb_otg_endp_multi_proc_int_map_reg_t;
+
+
+/** Group: CORE0 JPEG INT MAP REG */
+/** Type of jpeg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_jpeg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_jpeg_int_map:6;
+        /** core0_jpeg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_jpeg_int_src_pass_in_sec:1;
+        /** core0_jpeg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_jpeg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_jpeg_int_map_reg_t;
+
+
+/** Group: CORE0 PPA INT MAP REG */
+/** Type of ppa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ppa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ppa_int_map:6;
+        /** core0_ppa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ppa_int_src_pass_in_sec:1;
+        /** core0_ppa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ppa_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ppa_int_map_reg_t;
+
+
+/** Group: CORE0 CORE0 TRACE INT MAP REG */
+/** Type of core0_trace_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_core0_trace_int_map:6;
+        /** core0_core0_trace_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_core0_trace_int_src_pass_in_sec:1;
+        /** core0_core0_trace_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_core0_trace_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_core0_trace_int_map_reg_t;
+
+
+/** Group: CORE0 CORE1 TRACE INT MAP REG */
+/** Type of core1_trace_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_core1_trace_int_map:6;
+        /** core0_core1_trace_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_core1_trace_int_src_pass_in_sec:1;
+        /** core0_core1_trace_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_core1_trace_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_core1_trace_int_map_reg_t;
+
+
+/** Group: CORE0 HP CORE CTRL INT MAP REG */
+/** Type of hp_core_ctrl_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_hp_core_ctrl_int_map:6;
+        /** core0_hp_core_ctrl_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_core_ctrl_int_src_pass_in_sec:1;
+        /** core0_hp_core_ctrl_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_core_ctrl_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_hp_core_ctrl_int_map_reg_t;
+
+
+/** Group: CORE0 ISP INT MAP REG */
+/** Type of isp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_isp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_isp_int_map:6;
+        /** core0_isp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_isp_int_src_pass_in_sec:1;
+        /** core0_isp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_isp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_isp_int_map_reg_t;
+
+
+/** Group: CORE0 I3C MST INT MAP REG */
+/** Type of i3c_mst_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i3c_mst_int_map:6;
+        /** core0_i3c_mst_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i3c_mst_int_src_pass_in_sec:1;
+        /** core0_i3c_mst_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i3c_mst_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i3c_mst_int_map_reg_t;
+
+
+/** Group: CORE0 I3C SLV INT MAP REG */
+/** Type of i3c_slv_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i3c_slv_int_map:6;
+        /** core0_i3c_slv_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i3c_slv_int_src_pass_in_sec:1;
+        /** core0_i3c_slv_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i3c_slv_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i3c_slv_int_map_reg_t;
+
+
+/** Group: CORE0 USB OTG11 INT MAP REG */
+/** Type of usb_otg11_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_usb_otg11_int_map:6;
+        /** core0_usb_otg11_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg11_int_src_pass_in_sec:1;
+        /** core0_usb_otg11_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg11_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_usb_otg11_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D IN CH0 INT MAP REG */
+/** Type of dma2d_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_in_ch0_int_map:6;
+        /** core0_dma2d_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch0_int_src_pass_in_sec:1;
+        /** core0_dma2d_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D IN CH1 INT MAP REG */
+/** Type of dma2d_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_in_ch1_int_map:6;
+        /** core0_dma2d_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch1_int_src_pass_in_sec:1;
+        /** core0_dma2d_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D OUT CH0 INT MAP REG */
+/** Type of dma2d_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_out_ch0_int_map:6;
+        /** core0_dma2d_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch0_int_src_pass_in_sec:1;
+        /** core0_dma2d_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D OUT CH1 INT MAP REG */
+/** Type of dma2d_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_out_ch1_int_map:6;
+        /** core0_dma2d_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch1_int_src_pass_in_sec:1;
+        /** core0_dma2d_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D OUT CH2 INT MAP REG */
+/** Type of dma2d_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_out_ch2_int_map:6;
+        /** core0_dma2d_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch2_int_src_pass_in_sec:1;
+        /** core0_dma2d_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 PSRAM MSPI INT MAP REG */
+/** Type of psram_mspi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_psram_mspi_int_map:6;
+        /** core0_psram_mspi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_psram_mspi_int_src_pass_in_sec:1;
+        /** core0_psram_mspi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_psram_mspi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_psram_mspi_int_map_reg_t;
+
+
+/** Group: CORE0 HP SYSREG INT MAP REG */
+/** Type of hp_sysreg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_hp_sysreg_int_map:6;
+        /** core0_hp_sysreg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_sysreg_int_src_pass_in_sec:1;
+        /** core0_hp_sysreg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_sysreg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_hp_sysreg_int_map_reg_t;
+
+
+/** Group: CORE0 PCNT INT MAP REG */
+/** Type of pcnt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pcnt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pcnt_int_map:6;
+        /** core0_pcnt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pcnt_int_src_pass_in_sec:1;
+        /** core0_pcnt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pcnt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pcnt_int_map_reg_t;
+
+
+/** Group: CORE0 HP PAU INT MAP REG */
+/** Type of hp_pau_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_hp_pau_int_map:6;
+        /** core0_hp_pau_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_pau_int_src_pass_in_sec:1;
+        /** core0_hp_pau_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_pau_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_hp_pau_int_map_reg_t;
+
+
+/** Group: CORE0 HP PARLIO RX INT MAP REG */
+/** Type of hp_parlio_rx_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_hp_parlio_rx_int_map:6;
+        /** core0_hp_parlio_rx_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_parlio_rx_int_src_pass_in_sec:1;
+        /** core0_hp_parlio_rx_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_parlio_rx_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_hp_parlio_rx_int_map_reg_t;
+
+
+/** Group: CORE0 HP PARLIO TX INT MAP REG */
+/** Type of hp_parlio_tx_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_hp_parlio_tx_int_map:6;
+        /** core0_hp_parlio_tx_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_parlio_tx_int_src_pass_in_sec:1;
+        /** core0_hp_parlio_tx_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_parlio_tx_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_hp_parlio_tx_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D OUT CH0 INT MAP REG */
+/** Type of h264_dma2d_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_out_ch0_int_map:6;
+        /** core0_h264_dma2d_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch0_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D OUT CH1 INT MAP REG */
+/** Type of h264_dma2d_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_out_ch1_int_map:6;
+        /** core0_h264_dma2d_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch1_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D OUT CH2 INT MAP REG */
+/** Type of h264_dma2d_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_out_ch2_int_map:6;
+        /** core0_h264_dma2d_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch2_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D OUT CH3 INT MAP REG */
+/** Type of h264_dma2d_out_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_out_ch3_int_map:6;
+        /** core0_h264_dma2d_out_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch3_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_out_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_out_ch3_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D OUT CH4 INT MAP REG */
+/** Type of h264_dma2d_out_ch4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_out_ch4_int_map:6;
+        /** core0_h264_dma2d_out_ch4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch4_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_out_ch4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch4_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_out_ch4_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH0 INT MAP REG */
+/** Type of h264_dma2d_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch0_int_map:6;
+        /** core0_h264_dma2d_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch0_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH1 INT MAP REG */
+/** Type of h264_dma2d_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch1_int_map:6;
+        /** core0_h264_dma2d_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch1_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH2 INT MAP REG */
+/** Type of h264_dma2d_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch2_int_map:6;
+        /** core0_h264_dma2d_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch2_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH3 INT MAP REG */
+/** Type of h264_dma2d_in_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch3_int_map:6;
+        /** core0_h264_dma2d_in_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch3_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch3_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH4 INT MAP REG */
+/** Type of h264_dma2d_in_ch4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch4_int_map:6;
+        /** core0_h264_dma2d_in_ch4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch4_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch4_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch4_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH5 INT MAP REG */
+/** Type of h264_dma2d_in_ch5_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch5_int_map:6;
+        /** core0_h264_dma2d_in_ch5_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch5_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch5_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch5_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch5_int_map_reg_t;
+
+
+/** Group: CORE0 H264 REG INT MAP REG */
+/** Type of h264_reg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_reg_int_map:6;
+        /** core0_h264_reg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_reg_int_src_pass_in_sec:1;
+        /** core0_h264_reg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_reg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_reg_int_map_reg_t;
+
+
+/** Group: CORE0 ASSIST DEBUG INT MAP REG */
+/** Type of assist_debug_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_assist_debug_int_map:6;
+        /** core0_assist_debug_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_assist_debug_int_src_pass_in_sec:1;
+        /** core0_assist_debug_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_assist_debug_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_assist_debug_int_map_reg_t;
+
+
+/** Group: CORE0 INTR STATUS REG 0 REG */
+/** Type of intr_status_reg_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_status_0:32;
+    };
+    uint32_t val;
+} core0_intr_status_reg_0_reg_t;
+
+
+/** Group: CORE0 INTR STATUS REG 1 REG */
+/** Type of intr_status_reg_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_status_1:32;
+    };
+    uint32_t val;
+} core0_intr_status_reg_1_reg_t;
+
+
+/** Group: CORE0 INTR STATUS REG 2 REG */
+/** Type of intr_status_reg_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_status_2:32;
+    };
+    uint32_t val;
+} core0_intr_status_reg_2_reg_t;
+
+
+/** Group: CORE0 INTR STATUS REG 3 REG */
+/** Type of intr_status_reg_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_status_3:32;
+    };
+    uint32_t val;
+} core0_intr_status_reg_3_reg_t;
+
+
+/** Group: CORE0 CLOCK GATE REG */
+/** Type of clock_gate register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t core0_reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} core0_clock_gate_reg_t;
+
+
+/** Group: CORE0 DMA2D IN CH2 INT MAP REG */
+/** Type of dma2d_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_in_ch2_int_map:6;
+        /** core0_dma2d_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch2_int_src_pass_in_sec:1;
+        /** core0_dma2d_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D OUT CH3 INT MAP REG */
+/** Type of dma2d_out_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_out_ch3_int_map:6;
+        /** core0_dma2d_out_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch3_int_src_pass_in_sec:1;
+        /** core0_dma2d_out_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_out_ch3_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PERF MON INT MAP REG */
+/** Type of axi_perf_mon_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_perf_mon_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_perf_mon_int_map:6;
+        /** core0_axi_perf_mon_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_perf_mon_int_src_pass_in_sec:1;
+        /** core0_axi_perf_mon_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_perf_mon_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_perf_mon_int_map_reg_t;
+
+
+/** Group: CORE0 INTR STATUS REG 4 REG */
+/** Type of intr_status_reg_4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_status_4:32;
+    };
+    uint32_t val;
+} core0_intr_status_reg_4_reg_t;
+
+
+/** Group: CORE0 INTR SIG IDX ASSERT IN SEC REG */
+/** Type of intr_sig_idx_assert_in_sec register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_sig_idx_assert_in_sec : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_sig_idx_assert_in_sec:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} core0_intr_sig_idx_assert_in_sec_reg_t;
+
+
+/** Group: CORE0 INTR SEC STATUS REG */
+/** Type of intr_sec_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_sec_status : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_sec_status:32;
+    };
+    uint32_t val;
+} core0_intr_sec_status_reg_t;
+
+
+/** Group: CORE0 INTR SRC PASS IN SEC STATUS 0 REG */
+/** Type of intr_src_pass_in_sec_status_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_src_pass_in_sec_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_src_pass_in_sec_status_0:32;
+    };
+    uint32_t val;
+} core0_intr_src_pass_in_sec_status_0_reg_t;
+
+
+/** Group: CORE0 INTR SRC PASS IN SEC STATUS 1 REG */
+/** Type of intr_src_pass_in_sec_status_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_src_pass_in_sec_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_src_pass_in_sec_status_1:32;
+    };
+    uint32_t val;
+} core0_intr_src_pass_in_sec_status_1_reg_t;
+
+
+/** Group: CORE0 INTR SRC PASS IN SEC STATUS 2 REG */
+/** Type of intr_src_pass_in_sec_status_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_src_pass_in_sec_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_src_pass_in_sec_status_2:32;
+    };
+    uint32_t val;
+} core0_intr_src_pass_in_sec_status_2_reg_t;
+
+
+/** Group: CORE0 INTR SRC PASS IN SEC STATUS 3 REG */
+/** Type of intr_src_pass_in_sec_status_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_src_pass_in_sec_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_src_pass_in_sec_status_3:32;
+    };
+    uint32_t val;
+} core0_intr_src_pass_in_sec_status_3_reg_t;
+
+
+/** Group: CORE0 INTR SRC PASS IN SEC STATUS 4 REG */
+/** Type of intr_src_pass_in_sec_status_4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_src_pass_in_sec_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_src_pass_in_sec_status_4:32;
+    };
+    uint32_t val;
+} core0_intr_src_pass_in_sec_status_4_reg_t;
+
+
+/** Group: CORE0 INTERRUPT REG DATE REG */
+/** Type of interrupt_reg_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_interrupt_reg_date : R/W; bitpos: [27:0]; default: 38806144;
+         *  NA
+         */
+        uint32_t core0_interrupt_reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} core0_interrupt_reg_date_reg_t;
+
+
+typedef struct {
+    volatile core0_lp_rtc_int_map_reg_t lp_rtc_int_map;
+    volatile core0_lp_wdt_int_map_reg_t lp_wdt_int_map;
+    volatile core0_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map;
+    volatile core0_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map;
+    volatile core0_mb_hp_int_map_reg_t mb_hp_int_map;
+    volatile core0_mb_lp_int_map_reg_t mb_lp_int_map;
+    volatile core0_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map;
+    volatile core0_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map;
+    volatile core0_lp_anaperi_int_map_reg_t lp_anaperi_int_map;
+    volatile core0_lp_adc_int_map_reg_t lp_adc_int_map;
+    volatile core0_lp_gpio_int_map_reg_t lp_gpio_int_map;
+    volatile core0_lp_i2c_int_map_reg_t lp_i2c_int_map;
+    volatile core0_lp_i2s_int_map_reg_t lp_i2s_int_map;
+    volatile core0_lp_spi_int_map_reg_t lp_spi_int_map;
+    volatile core0_lp_touch_int_map_reg_t lp_touch_int_map;
+    volatile core0_lp_tsens_int_map_reg_t lp_tsens_int_map;
+    volatile core0_lp_uart_int_map_reg_t lp_uart_int_map;
+    volatile core0_lp_efuse_int_map_reg_t lp_efuse_int_map;
+    volatile core0_lp_sw_int_map_reg_t lp_sw_int_map;
+    volatile core0_lp_sysreg_int_map_reg_t lp_sysreg_int_map;
+    volatile core0_lp_huk_int_map_reg_t lp_huk_int_map;
+    volatile core0_sys_icm_int_map_reg_t sys_icm_int_map;
+    volatile core0_usb_device_int_map_reg_t usb_device_int_map;
+    volatile core0_sdio_host_int_map_reg_t sdio_host_int_map;
+    volatile core0_gdma_int_map_reg_t gdma_int_map;
+    volatile core0_spi2_int_map_reg_t spi2_int_map;
+    volatile core0_spi3_int_map_reg_t spi3_int_map;
+    volatile core0_i2s0_int_map_reg_t i2s0_int_map;
+    volatile core0_i2s1_int_map_reg_t i2s1_int_map;
+    volatile core0_i2s2_int_map_reg_t i2s2_int_map;
+    volatile core0_uhci0_int_map_reg_t uhci0_int_map;
+    volatile core0_uart0_int_map_reg_t uart0_int_map;
+    volatile core0_uart1_int_map_reg_t uart1_int_map;
+    volatile core0_uart2_int_map_reg_t uart2_int_map;
+    volatile core0_uart3_int_map_reg_t uart3_int_map;
+    volatile core0_uart4_int_map_reg_t uart4_int_map;
+    volatile core0_lcd_cam_int_map_reg_t lcd_cam_int_map;
+    volatile core0_adc_int_map_reg_t adc_int_map;
+    volatile core0_pwm0_int_map_reg_t pwm0_int_map;
+    volatile core0_pwm1_int_map_reg_t pwm1_int_map;
+    volatile core0_can0_int_map_reg_t can0_int_map;
+    volatile core0_can1_int_map_reg_t can1_int_map;
+    volatile core0_can2_int_map_reg_t can2_int_map;
+    volatile core0_rmt_int_map_reg_t rmt_int_map;
+    volatile core0_i2c0_int_map_reg_t i2c0_int_map;
+    volatile core0_i2c1_int_map_reg_t i2c1_int_map;
+    volatile core0_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map;
+    volatile core0_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map;
+    volatile core0_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map;
+    volatile core0_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map;
+    volatile core0_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map;
+    volatile core0_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map;
+    volatile core0_ledc_int_map_reg_t ledc_int_map;
+    volatile core0_systimer_target0_int_map_reg_t systimer_target0_int_map;
+    volatile core0_systimer_target1_int_map_reg_t systimer_target1_int_map;
+    volatile core0_systimer_target2_int_map_reg_t systimer_target2_int_map;
+    volatile core0_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map;
+    volatile core0_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map;
+    volatile core0_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map;
+    volatile core0_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map;
+    volatile core0_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map;
+    volatile core0_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map;
+    volatile core0_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map;
+    volatile core0_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map;
+    volatile core0_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map;
+    volatile core0_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map;
+    volatile core0_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map;
+    volatile core0_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map;
+    volatile core0_rsa_int_map_reg_t rsa_int_map;
+    volatile core0_aes_int_map_reg_t aes_int_map;
+    volatile core0_sha_int_map_reg_t sha_int_map;
+    volatile core0_ecc_int_map_reg_t ecc_int_map;
+    volatile core0_ecdsa_int_map_reg_t ecdsa_int_map;
+    volatile core0_km_int_map_reg_t km_int_map;
+    volatile core0_gpio_int0_map_reg_t gpio_int0_map;
+    volatile core0_gpio_int1_map_reg_t gpio_int1_map;
+    volatile core0_gpio_int2_map_reg_t gpio_int2_map;
+    volatile core0_gpio_int3_map_reg_t gpio_int3_map;
+    volatile core0_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map;
+    volatile core0_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map;
+    volatile core0_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map;
+    volatile core0_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map;
+    volatile core0_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map;
+    volatile core0_cache_int_map_reg_t cache_int_map;
+    volatile core0_flash_mspi_int_map_reg_t flash_mspi_int_map;
+    volatile core0_csi_bridge_int_map_reg_t csi_bridge_int_map;
+    volatile core0_dsi_bridge_int_map_reg_t dsi_bridge_int_map;
+    volatile core0_csi_int_map_reg_t csi_int_map;
+    volatile core0_dsi_int_map_reg_t dsi_int_map;
+    volatile core0_gmii_phy_int_map_reg_t gmii_phy_int_map;
+    volatile core0_lpi_int_map_reg_t lpi_int_map;
+    volatile core0_pmt_int_map_reg_t pmt_int_map;
+    volatile core0_sbd_int_map_reg_t sbd_int_map;
+    volatile core0_usb_otg_int_map_reg_t usb_otg_int_map;
+    volatile core0_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map;
+    volatile core0_jpeg_int_map_reg_t jpeg_int_map;
+    volatile core0_ppa_int_map_reg_t ppa_int_map;
+    volatile core0_core0_trace_int_map_reg_t core0_trace_int_map;
+    volatile core0_core1_trace_int_map_reg_t core1_trace_int_map;
+    volatile core0_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map;
+    volatile core0_isp_int_map_reg_t isp_int_map;
+    volatile core0_i3c_mst_int_map_reg_t i3c_mst_int_map;
+    volatile core0_i3c_slv_int_map_reg_t i3c_slv_int_map;
+    volatile core0_usb_otg11_int_map_reg_t usb_otg11_int_map;
+    volatile core0_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map;
+    volatile core0_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map;
+    volatile core0_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map;
+    volatile core0_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map;
+    volatile core0_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map;
+    volatile core0_psram_mspi_int_map_reg_t psram_mspi_int_map;
+    volatile core0_hp_sysreg_int_map_reg_t hp_sysreg_int_map;
+    volatile core0_pcnt_int_map_reg_t pcnt_int_map;
+    volatile core0_hp_pau_int_map_reg_t hp_pau_int_map;
+    volatile core0_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map;
+    volatile core0_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map;
+    volatile core0_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map;
+    volatile core0_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map;
+    volatile core0_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map;
+    volatile core0_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map;
+    volatile core0_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map;
+    volatile core0_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map;
+    volatile core0_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map;
+    volatile core0_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map;
+    volatile core0_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map;
+    volatile core0_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map;
+    volatile core0_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map;
+    volatile core0_h264_reg_int_map_reg_t h264_reg_int_map;
+    volatile core0_assist_debug_int_map_reg_t assist_debug_int_map;
+    volatile core0_intr_status_reg_0_reg_t intr_status_reg_0;
+    volatile core0_intr_status_reg_1_reg_t intr_status_reg_1;
+    volatile core0_intr_status_reg_2_reg_t intr_status_reg_2;
+    volatile core0_intr_status_reg_3_reg_t intr_status_reg_3;
+    volatile core0_clock_gate_reg_t clock_gate;
+    volatile core0_dma2d_in_ch2_int_map_reg_t dma2d_in_ch2_int_map;
+    volatile core0_dma2d_out_ch3_int_map_reg_t dma2d_out_ch3_int_map;
+    volatile core0_axi_perf_mon_int_map_reg_t axi_perf_mon_int_map;
+    volatile core0_intr_status_reg_4_reg_t intr_status_reg_4;
+    uint32_t reserved_224;
+    volatile core0_intr_sig_idx_assert_in_sec_reg_t intr_sig_idx_assert_in_sec;
+    volatile core0_intr_sec_status_reg_t intr_sec_status;
+    volatile core0_intr_src_pass_in_sec_status_0_reg_t intr_src_pass_in_sec_status_0;
+    volatile core0_intr_src_pass_in_sec_status_1_reg_t intr_src_pass_in_sec_status_1;
+    volatile core0_intr_src_pass_in_sec_status_2_reg_t intr_src_pass_in_sec_status_2;
+    volatile core0_intr_src_pass_in_sec_status_3_reg_t intr_src_pass_in_sec_status_3;
+    volatile core0_intr_src_pass_in_sec_status_4_reg_t intr_src_pass_in_sec_status_4;
+    uint32_t reserved_244[110];
+    volatile core0_interrupt_reg_date_reg_t interrupt_reg_date;
+} core0_dev_t;
+
+extern core0_dev_t INTR_CORE0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(core0_dev_t) == 0x400, "Invalid size of core0_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core1_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core1_reg.h
new file mode 100644
index 0000000000..0cc0a6746b
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core1_reg.h
@@ -0,0 +1,3592 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CORE1_LP_RTC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x0)
+/** CORE1_CORE1_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_MAP_M  (CORE1_CORE1_LP_RTC_INT_MAP_V << CORE1_CORE1_LP_RTC_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_MAP_S  0
+/** CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4)
+/** CORE1_CORE1_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_MAP_M  (CORE1_CORE1_LP_WDT_INT_MAP_V << CORE1_CORE1_LP_WDT_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_MAP_S  0
+/** CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_TIMER_REG_0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8)
+/** CORE1_CORE1_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_M  (CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_V << CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_S  0
+/** CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_TIMER_REG_1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc)
+/** CORE1_CORE1_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_M  (CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_V << CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_S  0
+/** CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_MB_HP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10)
+/** CORE1_CORE1_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_MAP_M  (CORE1_CORE1_MB_HP_INT_MAP_V << CORE1_CORE1_MB_HP_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_MAP_S  0
+/** CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_MB_LP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14)
+/** CORE1_CORE1_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_MAP_M  (CORE1_CORE1_MB_LP_INT_MAP_V << CORE1_CORE1_MB_LP_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_MAP_S  0
+/** CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_PMU_REG_0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18)
+/** CORE1_CORE1_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_MAP_M  (CORE1_CORE1_PMU_REG_0_INT_MAP_V << CORE1_CORE1_PMU_REG_0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_MAP_S  0
+/** CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_PMU_REG_1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c)
+/** CORE1_CORE1_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_MAP_M  (CORE1_CORE1_PMU_REG_1_INT_MAP_V << CORE1_CORE1_PMU_REG_1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_MAP_S  0
+/** CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_ANAPERI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20)
+/** CORE1_CORE1_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_MAP_M  (CORE1_CORE1_LP_ANAPERI_INT_MAP_V << CORE1_CORE1_LP_ANAPERI_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_MAP_S  0
+/** CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_ADC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x24)
+/** CORE1_CORE1_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_MAP_M  (CORE1_CORE1_LP_ADC_INT_MAP_V << CORE1_CORE1_LP_ADC_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_MAP_S  0
+/** CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_GPIO_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x28)
+/** CORE1_CORE1_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_MAP_M  (CORE1_CORE1_LP_GPIO_INT_MAP_V << CORE1_CORE1_LP_GPIO_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_MAP_S  0
+/** CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_I2C_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2c)
+/** CORE1_CORE1_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_MAP_M  (CORE1_CORE1_LP_I2C_INT_MAP_V << CORE1_CORE1_LP_I2C_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_MAP_S  0
+/** CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_I2S_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x30)
+/** CORE1_CORE1_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_MAP_M  (CORE1_CORE1_LP_I2S_INT_MAP_V << CORE1_CORE1_LP_I2S_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_MAP_S  0
+/** CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_SPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x34)
+/** CORE1_CORE1_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_MAP_M  (CORE1_CORE1_LP_SPI_INT_MAP_V << CORE1_CORE1_LP_SPI_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_MAP_S  0
+/** CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_TOUCH_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x38)
+/** CORE1_CORE1_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_MAP_M  (CORE1_CORE1_LP_TOUCH_INT_MAP_V << CORE1_CORE1_LP_TOUCH_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_MAP_S  0
+/** CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_TSENS_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3c)
+/** CORE1_CORE1_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_MAP_M  (CORE1_CORE1_LP_TSENS_INT_MAP_V << CORE1_CORE1_LP_TSENS_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_MAP_S  0
+/** CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_UART_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x40)
+/** CORE1_CORE1_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_MAP_M  (CORE1_CORE1_LP_UART_INT_MAP_V << CORE1_CORE1_LP_UART_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_MAP_S  0
+/** CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_EFUSE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x44)
+/** CORE1_CORE1_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_MAP_M  (CORE1_CORE1_LP_EFUSE_INT_MAP_V << CORE1_CORE1_LP_EFUSE_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_MAP_S  0
+/** CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_SW_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x48)
+/** CORE1_CORE1_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_MAP_M  (CORE1_CORE1_LP_SW_INT_MAP_V << CORE1_CORE1_LP_SW_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_MAP_S  0
+/** CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_SYSREG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4c)
+/** CORE1_CORE1_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_MAP_M  (CORE1_CORE1_LP_SYSREG_INT_MAP_V << CORE1_CORE1_LP_SYSREG_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_MAP_S  0
+/** CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LP_HUK_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x50)
+/** CORE1_CORE1_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_MAP_M  (CORE1_CORE1_LP_HUK_INT_MAP_V << CORE1_CORE1_LP_HUK_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_MAP_S  0
+/** CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_SYS_ICM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x54)
+/** CORE1_CORE1_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_MAP_M  (CORE1_CORE1_SYS_ICM_INT_MAP_V << CORE1_CORE1_SYS_ICM_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_MAP_S  0
+/** CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_USB_DEVICE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x58)
+/** CORE1_CORE1_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_MAP_M  (CORE1_CORE1_USB_DEVICE_INT_MAP_V << CORE1_CORE1_USB_DEVICE_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_MAP_S  0
+/** CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_SDIO_HOST_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x5c)
+/** CORE1_CORE1_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_MAP_M  (CORE1_CORE1_SDIO_HOST_INT_MAP_V << CORE1_CORE1_SDIO_HOST_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_MAP_S  0
+/** CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_GDMA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x60)
+/** CORE1_CORE1_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_MAP_M  (CORE1_CORE1_GDMA_INT_MAP_V << CORE1_CORE1_GDMA_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_MAP_S  0
+/** CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_SPI2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x64)
+/** CORE1_CORE1_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_MAP_M  (CORE1_CORE1_SPI2_INT_MAP_V << CORE1_CORE1_SPI2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_MAP_S  0
+/** CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_SPI3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x68)
+/** CORE1_CORE1_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_MAP_M  (CORE1_CORE1_SPI3_INT_MAP_V << CORE1_CORE1_SPI3_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_MAP_S  0
+/** CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_I2S0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x6c)
+/** CORE1_CORE1_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_MAP_M  (CORE1_CORE1_I2S0_INT_MAP_V << CORE1_CORE1_I2S0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_MAP_S  0
+/** CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_I2S1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x70)
+/** CORE1_CORE1_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_MAP_M  (CORE1_CORE1_I2S1_INT_MAP_V << CORE1_CORE1_I2S1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_MAP_S  0
+/** CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_I2S2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x74)
+/** CORE1_CORE1_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_MAP_M  (CORE1_CORE1_I2S2_INT_MAP_V << CORE1_CORE1_I2S2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_MAP_S  0
+/** CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_UHCI0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x78)
+/** CORE1_CORE1_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_MAP_M  (CORE1_CORE1_UHCI0_INT_MAP_V << CORE1_CORE1_UHCI0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_MAP_S  0
+/** CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_UART0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x7c)
+/** CORE1_CORE1_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_UART0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UART0_INT_MAP_M  (CORE1_CORE1_UART0_INT_MAP_V << CORE1_CORE1_UART0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_UART0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UART0_INT_MAP_S  0
+/** CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_UART1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80)
+/** CORE1_CORE1_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_UART1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UART1_INT_MAP_M  (CORE1_CORE1_UART1_INT_MAP_V << CORE1_CORE1_UART1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_UART1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UART1_INT_MAP_S  0
+/** CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_UART2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84)
+/** CORE1_CORE1_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_UART2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UART2_INT_MAP_M  (CORE1_CORE1_UART2_INT_MAP_V << CORE1_CORE1_UART2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_UART2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UART2_INT_MAP_S  0
+/** CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_UART3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88)
+/** CORE1_CORE1_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_UART3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UART3_INT_MAP_M  (CORE1_CORE1_UART3_INT_MAP_V << CORE1_CORE1_UART3_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_UART3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UART3_INT_MAP_S  0
+/** CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_UART4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8c)
+/** CORE1_CORE1_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_UART4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UART4_INT_MAP_M  (CORE1_CORE1_UART4_INT_MAP_V << CORE1_CORE1_UART4_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_UART4_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_UART4_INT_MAP_S  0
+/** CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LCD_CAM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90)
+/** CORE1_CORE1_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_MAP_M  (CORE1_CORE1_LCD_CAM_INT_MAP_V << CORE1_CORE1_LCD_CAM_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_MAP_S  0
+/** CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_ADC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94)
+/** CORE1_CORE1_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_ADC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_ADC_INT_MAP_M  (CORE1_CORE1_ADC_INT_MAP_V << CORE1_CORE1_ADC_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_ADC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_ADC_INT_MAP_S  0
+/** CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_PWM0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x98)
+/** CORE1_CORE1_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_MAP_M  (CORE1_CORE1_PWM0_INT_MAP_V << CORE1_CORE1_PWM0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_MAP_S  0
+/** CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_PWM1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x9c)
+/** CORE1_CORE1_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_MAP_M  (CORE1_CORE1_PWM1_INT_MAP_V << CORE1_CORE1_PWM1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_MAP_S  0
+/** CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CAN0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa0)
+/** CORE1_CORE1_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_MAP_M  (CORE1_CORE1_CAN0_INT_MAP_V << CORE1_CORE1_CAN0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_MAP_S  0
+/** CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CAN1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa4)
+/** CORE1_CORE1_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_MAP_M  (CORE1_CORE1_CAN1_INT_MAP_V << CORE1_CORE1_CAN1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_MAP_S  0
+/** CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CAN2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa8)
+/** CORE1_CORE1_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_MAP_M  (CORE1_CORE1_CAN2_INT_MAP_V << CORE1_CORE1_CAN2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_MAP_S  0
+/** CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_RMT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xac)
+/** CORE1_CORE1_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_RMT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_RMT_INT_MAP_M  (CORE1_CORE1_RMT_INT_MAP_V << CORE1_CORE1_RMT_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_RMT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_RMT_INT_MAP_S  0
+/** CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_I2C0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb0)
+/** CORE1_CORE1_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_MAP_M  (CORE1_CORE1_I2C0_INT_MAP_V << CORE1_CORE1_I2C0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_MAP_S  0
+/** CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_I2C1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb4)
+/** CORE1_CORE1_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_MAP_M  (CORE1_CORE1_I2C1_INT_MAP_V << CORE1_CORE1_I2C1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_MAP_S  0
+/** CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_TIMERGRP0_T0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb8)
+/** CORE1_CORE1_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_MAP_M  (CORE1_CORE1_TIMERGRP0_T0_INT_MAP_V << CORE1_CORE1_TIMERGRP0_T0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_MAP_S  0
+/** CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_TIMERGRP0_T1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xbc)
+/** CORE1_CORE1_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_MAP_M  (CORE1_CORE1_TIMERGRP0_T1_INT_MAP_V << CORE1_CORE1_TIMERGRP0_T1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_MAP_S  0
+/** CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_TIMERGRP0_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc0)
+/** CORE1_CORE1_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_M  (CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_V << CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_S  0
+/** CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_TIMERGRP1_T0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc4)
+/** CORE1_CORE1_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_MAP_M  (CORE1_CORE1_TIMERGRP1_T0_INT_MAP_V << CORE1_CORE1_TIMERGRP1_T0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_MAP_S  0
+/** CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_TIMERGRP1_T1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc8)
+/** CORE1_CORE1_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_MAP_M  (CORE1_CORE1_TIMERGRP1_T1_INT_MAP_V << CORE1_CORE1_TIMERGRP1_T1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_MAP_S  0
+/** CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_TIMERGRP1_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xcc)
+/** CORE1_CORE1_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_M  (CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_V << CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_S  0
+/** CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LEDC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd0)
+/** CORE1_CORE1_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_MAP_M  (CORE1_CORE1_LEDC_INT_MAP_V << CORE1_CORE1_LEDC_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_MAP_S  0
+/** CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_SYSTIMER_TARGET0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd4)
+/** CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_M  (CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_S  0
+/** CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_SYSTIMER_TARGET1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd8)
+/** CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_M  (CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_S  0
+/** CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_SYSTIMER_TARGET2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xdc)
+/** CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_M  (CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_S  0
+/** CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe0)
+/** CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S  0
+/** CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe4)
+/** CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S  0
+/** CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe8)
+/** CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S  0
+/** CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xec)
+/** CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S  0
+/** CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf0)
+/** CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S  0
+/** CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf4)
+/** CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M  (CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S  0
+/** CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf8)
+/** CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S  0
+/** CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xfc)
+/** CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S  0
+/** CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x100)
+/** CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S  0
+/** CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x104)
+/** CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S  0
+/** CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x108)
+/** CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S  0
+/** CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10c)
+/** CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M  (CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S  0
+/** CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_RSA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x110)
+/** CORE1_CORE1_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_RSA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_RSA_INT_MAP_M  (CORE1_CORE1_RSA_INT_MAP_V << CORE1_CORE1_RSA_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_RSA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_RSA_INT_MAP_S  0
+/** CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AES_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x114)
+/** CORE1_CORE1_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AES_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AES_INT_MAP_M  (CORE1_CORE1_AES_INT_MAP_V << CORE1_CORE1_AES_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AES_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AES_INT_MAP_S  0
+/** CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_SHA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x118)
+/** CORE1_CORE1_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_SHA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SHA_INT_MAP_M  (CORE1_CORE1_SHA_INT_MAP_V << CORE1_CORE1_SHA_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_SHA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SHA_INT_MAP_S  0
+/** CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_ECC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x11c)
+/** CORE1_CORE1_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_ECC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_ECC_INT_MAP_M  (CORE1_CORE1_ECC_INT_MAP_V << CORE1_CORE1_ECC_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_ECC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_ECC_INT_MAP_S  0
+/** CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_ECDSA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x120)
+/** CORE1_CORE1_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_MAP_M  (CORE1_CORE1_ECDSA_INT_MAP_V << CORE1_CORE1_ECDSA_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_MAP_S  0
+/** CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_KM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x124)
+/** CORE1_CORE1_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_KM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_KM_INT_MAP_M  (CORE1_CORE1_KM_INT_MAP_V << CORE1_CORE1_KM_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_KM_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_KM_INT_MAP_S  0
+/** CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_GPIO_INT0_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x128)
+/** CORE1_CORE1_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_MAP_M  (CORE1_CORE1_GPIO_INT0_MAP_V << CORE1_CORE1_GPIO_INT0_MAP_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_MAP_S  0
+/** CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC_M  (CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC_V << CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_GPIO_INT1_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x12c)
+/** CORE1_CORE1_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_MAP_M  (CORE1_CORE1_GPIO_INT1_MAP_V << CORE1_CORE1_GPIO_INT1_MAP_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_MAP_S  0
+/** CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC_M  (CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC_V << CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_GPIO_INT2_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x130)
+/** CORE1_CORE1_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_MAP_M  (CORE1_CORE1_GPIO_INT2_MAP_V << CORE1_CORE1_GPIO_INT2_MAP_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_MAP_S  0
+/** CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC_M  (CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC_V << CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_GPIO_INT3_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x134)
+/** CORE1_CORE1_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_MAP_M  (CORE1_CORE1_GPIO_INT3_MAP_V << CORE1_CORE1_GPIO_INT3_MAP_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_MAP_S  0
+/** CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC_M  (CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC_V << CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_GPIO_PAD_COMP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x138)
+/** CORE1_CORE1_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_M  (CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_V << CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_S  0
+/** CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CPU_INT_FROM_CPU_0_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x13c)
+/** CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_M  (CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_S  0
+/** CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_V << CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CPU_INT_FROM_CPU_1_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x140)
+/** CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_M  (CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_S  0
+/** CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_V << CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CPU_INT_FROM_CPU_2_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x144)
+/** CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_M  (CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_S  0
+/** CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_V << CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CPU_INT_FROM_CPU_3_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x148)
+/** CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_M  (CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_S  0
+/** CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_V << CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CACHE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14c)
+/** CORE1_CORE1_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_MAP_M  (CORE1_CORE1_CACHE_INT_MAP_V << CORE1_CORE1_CACHE_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_MAP_S  0
+/** CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_FLASH_MSPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x150)
+/** CORE1_CORE1_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_MAP_M  (CORE1_CORE1_FLASH_MSPI_INT_MAP_V << CORE1_CORE1_FLASH_MSPI_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_MAP_S  0
+/** CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CSI_BRIDGE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x154)
+/** CORE1_CORE1_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_MAP_M  (CORE1_CORE1_CSI_BRIDGE_INT_MAP_V << CORE1_CORE1_CSI_BRIDGE_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_MAP_S  0
+/** CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_DSI_BRIDGE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x158)
+/** CORE1_CORE1_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_MAP_M  (CORE1_CORE1_DSI_BRIDGE_INT_MAP_V << CORE1_CORE1_DSI_BRIDGE_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_MAP_S  0
+/** CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CSI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x15c)
+/** CORE1_CORE1_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CSI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CSI_INT_MAP_M  (CORE1_CORE1_CSI_INT_MAP_V << CORE1_CORE1_CSI_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CSI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CSI_INT_MAP_S  0
+/** CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_DSI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x160)
+/** CORE1_CORE1_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_DSI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DSI_INT_MAP_M  (CORE1_CORE1_DSI_INT_MAP_V << CORE1_CORE1_DSI_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_DSI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DSI_INT_MAP_S  0
+/** CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_GMII_PHY_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x164)
+/** CORE1_CORE1_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_MAP_M  (CORE1_CORE1_GMII_PHY_INT_MAP_V << CORE1_CORE1_GMII_PHY_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_MAP_S  0
+/** CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_LPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x168)
+/** CORE1_CORE1_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_LPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LPI_INT_MAP_M  (CORE1_CORE1_LPI_INT_MAP_V << CORE1_CORE1_LPI_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_LPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_LPI_INT_MAP_S  0
+/** CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_PMT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x16c)
+/** CORE1_CORE1_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_PMT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PMT_INT_MAP_M  (CORE1_CORE1_PMT_INT_MAP_V << CORE1_CORE1_PMT_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_PMT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PMT_INT_MAP_S  0
+/** CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_SBD_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x170)
+/** CORE1_CORE1_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_SBD_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SBD_INT_MAP_M  (CORE1_CORE1_SBD_INT_MAP_V << CORE1_CORE1_SBD_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_SBD_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_SBD_INT_MAP_S  0
+/** CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_USB_OTG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x174)
+/** CORE1_CORE1_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_MAP_M  (CORE1_CORE1_USB_OTG_INT_MAP_V << CORE1_CORE1_USB_OTG_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_MAP_S  0
+/** CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x178)
+/** CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  (CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S  0
+/** CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6];
+ *  default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7];
+ *  default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_JPEG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x17c)
+/** CORE1_CORE1_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_MAP_M  (CORE1_CORE1_JPEG_INT_MAP_V << CORE1_CORE1_JPEG_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_MAP_S  0
+/** CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_PPA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x180)
+/** CORE1_CORE1_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_PPA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PPA_INT_MAP_M  (CORE1_CORE1_PPA_INT_MAP_V << CORE1_CORE1_PPA_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_PPA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PPA_INT_MAP_S  0
+/** CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CORE0_TRACE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x184)
+/** CORE1_CORE1_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_MAP_M  (CORE1_CORE1_CORE0_TRACE_INT_MAP_V << CORE1_CORE1_CORE0_TRACE_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_MAP_S  0
+/** CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_CORE1_TRACE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x188)
+/** CORE1_CORE1_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_MAP_M  (CORE1_CORE1_CORE1_TRACE_INT_MAP_V << CORE1_CORE1_CORE1_TRACE_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_MAP_S  0
+/** CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_HP_CORE_CTRL_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18c)
+/** CORE1_CORE1_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_MAP_M  (CORE1_CORE1_HP_CORE_CTRL_INT_MAP_V << CORE1_CORE1_HP_CORE_CTRL_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_MAP_S  0
+/** CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_ISP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x190)
+/** CORE1_CORE1_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_ISP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_ISP_INT_MAP_M  (CORE1_CORE1_ISP_INT_MAP_V << CORE1_CORE1_ISP_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_ISP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_ISP_INT_MAP_S  0
+/** CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_I3C_MST_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x194)
+/** CORE1_CORE1_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_MAP_M  (CORE1_CORE1_I3C_MST_INT_MAP_V << CORE1_CORE1_I3C_MST_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_MAP_S  0
+/** CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_I3C_SLV_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x198)
+/** CORE1_CORE1_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_MAP_M  (CORE1_CORE1_I3C_SLV_INT_MAP_V << CORE1_CORE1_I3C_SLV_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_MAP_S  0
+/** CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_USB_OTG11_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x19c)
+/** CORE1_CORE1_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_MAP_M  (CORE1_CORE1_USB_OTG11_INT_MAP_V << CORE1_CORE1_USB_OTG11_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_MAP_S  0
+/** CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_DMA2D_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a0)
+/** CORE1_CORE1_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_M  (CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_S  0
+/** CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_DMA2D_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a4)
+/** CORE1_CORE1_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_M  (CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_S  0
+/** CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_DMA2D_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a8)
+/** CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_M  (CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_S  0
+/** CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_DMA2D_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ac)
+/** CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_M  (CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_S  0
+/** CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_DMA2D_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b0)
+/** CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_M  (CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_S  0
+/** CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_PSRAM_MSPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b4)
+/** CORE1_CORE1_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_MAP_M  (CORE1_CORE1_PSRAM_MSPI_INT_MAP_V << CORE1_CORE1_PSRAM_MSPI_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_MAP_S  0
+/** CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_HP_SYSREG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b8)
+/** CORE1_CORE1_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_MAP_M  (CORE1_CORE1_HP_SYSREG_INT_MAP_V << CORE1_CORE1_HP_SYSREG_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_MAP_S  0
+/** CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_PCNT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1bc)
+/** CORE1_CORE1_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_MAP_M  (CORE1_CORE1_PCNT_INT_MAP_V << CORE1_CORE1_PCNT_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_MAP_S  0
+/** CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_HP_PAU_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c0)
+/** CORE1_CORE1_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_MAP_M  (CORE1_CORE1_HP_PAU_INT_MAP_V << CORE1_CORE1_HP_PAU_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_MAP_S  0
+/** CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_HP_PARLIO_RX_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c4)
+/** CORE1_CORE1_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_MAP_M  (CORE1_CORE1_HP_PARLIO_RX_INT_MAP_V << CORE1_CORE1_HP_PARLIO_RX_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_MAP_S  0
+/** CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_HP_PARLIO_TX_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c8)
+/** CORE1_CORE1_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_MAP_M  (CORE1_CORE1_HP_PARLIO_TX_INT_MAP_V << CORE1_CORE1_HP_PARLIO_TX_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_MAP_S  0
+/** CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1cc)
+/** CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d0)
+/** CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d4)
+/** CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d8)
+/** CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1dc)
+/** CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e0)
+/** CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e4)
+/** CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e8)
+/** CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ec)
+/** CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f0)
+/** CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f4)
+/** CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M  (CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S  0
+/** CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_H264_REG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f8)
+/** CORE1_CORE1_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_MAP_M  (CORE1_CORE1_H264_REG_INT_MAP_V << CORE1_CORE1_H264_REG_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_MAP_S  0
+/** CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_ASSIST_DEBUG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1fc)
+/** CORE1_CORE1_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_MAP_M  (CORE1_CORE1_ASSIST_DEBUG_INT_MAP_V << CORE1_CORE1_ASSIST_DEBUG_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_MAP_S  0
+/** CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_INTR_STATUS_REG_0_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x200)
+/** CORE1_CORE1_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_0_M  (CORE1_CORE1_INTR_STATUS_0_V << CORE1_CORE1_INTR_STATUS_0_S)
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_0_S  0
+
+/** CORE1_INTR_STATUS_REG_1_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x204)
+/** CORE1_CORE1_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_1_M  (CORE1_CORE1_INTR_STATUS_1_V << CORE1_CORE1_INTR_STATUS_1_S)
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_1_S  0
+
+/** CORE1_INTR_STATUS_REG_2_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x208)
+/** CORE1_CORE1_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_2_M  (CORE1_CORE1_INTR_STATUS_2_V << CORE1_CORE1_INTR_STATUS_2_S)
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_2_S  0
+
+/** CORE1_INTR_STATUS_REG_3_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20c)
+/** CORE1_CORE1_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_3_M  (CORE1_CORE1_INTR_STATUS_3_V << CORE1_CORE1_INTR_STATUS_3_S)
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_3_S  0
+
+/** CORE1_CLOCK_GATE_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x210)
+/** CORE1_CORE1_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_REG_CLK_EN    (BIT(0))
+#define INTERRUPT_CORE1_CORE1_REG_CLK_EN_M  (CORE1_CORE1_REG_CLK_EN_V << CORE1_CORE1_REG_CLK_EN_S)
+#define INTERRUPT_CORE1_CORE1_REG_CLK_EN_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_REG_CLK_EN_S  0
+
+/** CORE1_DMA2D_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x214)
+/** CORE1_CORE1_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_MAP_M  (CORE1_CORE1_DMA2D_IN_CH2_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_MAP_S  0
+/** CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_DMA2D_OUT_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x218)
+/** CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP_M  (CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP_S  0
+/** CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_AXI_PERF_MON_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_AXI_PERF_MON_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x21c)
+/** CORE1_CORE1_AXI_PERF_MON_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_MAP_M  (CORE1_CORE1_AXI_PERF_MON_INT_MAP_V << CORE1_CORE1_AXI_PERF_MON_INT_MAP_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_MAP_S  0
+/** CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_M  (CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_S  6
+/** CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_M  (CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE1_INTR_STATUS_REG_4_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_STATUS_REG_4_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x220)
+/** CORE1_CORE1_INTR_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_4_M  (CORE1_CORE1_INTR_STATUS_4_V << CORE1_CORE1_INTR_STATUS_4_S)
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_STATUS_4_S  0
+
+/** CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x228)
+/** CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_M  (CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_V << CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_S)
+#define INTERRUPT_CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_S  0
+
+/** CORE1_INTR_SEC_STATUS_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_SEC_STATUS_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x22c)
+/** CORE1_CORE1_INTR_SEC_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_SEC_STATUS    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SEC_STATUS_M  (CORE1_CORE1_INTR_SEC_STATUS_V << CORE1_CORE1_INTR_SEC_STATUS_S)
+#define INTERRUPT_CORE1_CORE1_INTR_SEC_STATUS_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SEC_STATUS_S  0
+
+/** CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x230)
+/** CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_M  (CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_V << CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_S)
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_S  0
+
+/** CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x234)
+/** CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_M  (CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_V << CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_S)
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_S  0
+
+/** CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x238)
+/** CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_M  (CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_V << CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_S)
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_S  0
+
+/** CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x23c)
+/** CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_M  (CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_V << CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_S)
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_S  0
+
+/** CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x240)
+/** CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_M  (CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_V << CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_S)
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_S  0
+
+/** CORE1_INTERRUPT_REG_DATE_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3fc)
+/** CORE1_CORE1_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 38806144;
+ *  NA
+ */
+#define INTERRUPT_CORE1_CORE1_INTERRUPT_REG_DATE    0x0FFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTERRUPT_REG_DATE_M  (CORE1_CORE1_INTERRUPT_REG_DATE_V << CORE1_CORE1_INTERRUPT_REG_DATE_S)
+#define INTERRUPT_CORE1_CORE1_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
+#define INTERRUPT_CORE1_CORE1_INTERRUPT_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core1_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core1_struct.h
new file mode 100644
index 0000000000..67d86f98bb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/interrupt_core1_struct.h
@@ -0,0 +1,3528 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: CORE1 LP RTC INT MAP REG */
+/** Type of lp_rtc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_rtc_int_map:6;
+        /** core1_lp_rtc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_rtc_int_src_pass_in_sec:1;
+        /** core1_lp_rtc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_rtc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_rtc_int_map_reg_t;
+
+
+/** Group: CORE1 LP WDT INT MAP REG */
+/** Type of lp_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_wdt_int_map:6;
+        /** core1_lp_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_wdt_int_src_pass_in_sec:1;
+        /** core1_lp_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_wdt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_wdt_int_map_reg_t;
+
+
+/** Group: CORE1 LP TIMER REG 0 INT MAP REG */
+/** Type of lp_timer_reg_0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_timer_reg_0_int_map:6;
+        /** core1_lp_timer_reg_0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_timer_reg_0_int_src_pass_in_sec:1;
+        /** core1_lp_timer_reg_0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_timer_reg_0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_timer_reg_0_int_map_reg_t;
+
+
+/** Group: CORE1 LP TIMER REG 1 INT MAP REG */
+/** Type of lp_timer_reg_1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_timer_reg_1_int_map:6;
+        /** core1_lp_timer_reg_1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_timer_reg_1_int_src_pass_in_sec:1;
+        /** core1_lp_timer_reg_1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_timer_reg_1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_timer_reg_1_int_map_reg_t;
+
+
+/** Group: CORE1 MB HP INT MAP REG */
+/** Type of mb_hp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_mb_hp_int_map:6;
+        /** core1_mb_hp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_mb_hp_int_src_pass_in_sec:1;
+        /** core1_mb_hp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_mb_hp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_mb_hp_int_map_reg_t;
+
+
+/** Group: CORE1 MB LP INT MAP REG */
+/** Type of mb_lp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_mb_lp_int_map:6;
+        /** core1_mb_lp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_mb_lp_int_src_pass_in_sec:1;
+        /** core1_mb_lp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_mb_lp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_mb_lp_int_map_reg_t;
+
+
+/** Group: CORE1 PMU REG 0 INT MAP REG */
+/** Type of pmu_reg_0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_pmu_reg_0_int_map:6;
+        /** core1_pmu_reg_0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pmu_reg_0_int_src_pass_in_sec:1;
+        /** core1_pmu_reg_0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pmu_reg_0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_pmu_reg_0_int_map_reg_t;
+
+
+/** Group: CORE1 PMU REG 1 INT MAP REG */
+/** Type of pmu_reg_1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_pmu_reg_1_int_map:6;
+        /** core1_pmu_reg_1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pmu_reg_1_int_src_pass_in_sec:1;
+        /** core1_pmu_reg_1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pmu_reg_1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_pmu_reg_1_int_map_reg_t;
+
+
+/** Group: CORE1 LP ANAPERI INT MAP REG */
+/** Type of lp_anaperi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_anaperi_int_map:6;
+        /** core1_lp_anaperi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_anaperi_int_src_pass_in_sec:1;
+        /** core1_lp_anaperi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_anaperi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_anaperi_int_map_reg_t;
+
+
+/** Group: CORE1 LP ADC INT MAP REG */
+/** Type of lp_adc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_adc_int_map:6;
+        /** core1_lp_adc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_adc_int_src_pass_in_sec:1;
+        /** core1_lp_adc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_adc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_adc_int_map_reg_t;
+
+
+/** Group: CORE1 LP GPIO INT MAP REG */
+/** Type of lp_gpio_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_gpio_int_map:6;
+        /** core1_lp_gpio_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_gpio_int_src_pass_in_sec:1;
+        /** core1_lp_gpio_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_gpio_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_gpio_int_map_reg_t;
+
+
+/** Group: CORE1 LP I2C INT MAP REG */
+/** Type of lp_i2c_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_i2c_int_map:6;
+        /** core1_lp_i2c_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_i2c_int_src_pass_in_sec:1;
+        /** core1_lp_i2c_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_i2c_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_i2c_int_map_reg_t;
+
+
+/** Group: CORE1 LP I2S INT MAP REG */
+/** Type of lp_i2s_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_i2s_int_map:6;
+        /** core1_lp_i2s_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_i2s_int_src_pass_in_sec:1;
+        /** core1_lp_i2s_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_i2s_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_i2s_int_map_reg_t;
+
+
+/** Group: CORE1 LP SPI INT MAP REG */
+/** Type of lp_spi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_spi_int_map:6;
+        /** core1_lp_spi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_spi_int_src_pass_in_sec:1;
+        /** core1_lp_spi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_spi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_spi_int_map_reg_t;
+
+
+/** Group: CORE1 LP TOUCH INT MAP REG */
+/** Type of lp_touch_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_touch_int_map:6;
+        /** core1_lp_touch_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_touch_int_src_pass_in_sec:1;
+        /** core1_lp_touch_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_touch_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_touch_int_map_reg_t;
+
+
+/** Group: CORE1 LP TSENS INT MAP REG */
+/** Type of lp_tsens_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_tsens_int_map:6;
+        /** core1_lp_tsens_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_tsens_int_src_pass_in_sec:1;
+        /** core1_lp_tsens_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_tsens_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_tsens_int_map_reg_t;
+
+
+/** Group: CORE1 LP UART INT MAP REG */
+/** Type of lp_uart_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_uart_int_map:6;
+        /** core1_lp_uart_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_uart_int_src_pass_in_sec:1;
+        /** core1_lp_uart_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_uart_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_uart_int_map_reg_t;
+
+
+/** Group: CORE1 LP EFUSE INT MAP REG */
+/** Type of lp_efuse_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_efuse_int_map:6;
+        /** core1_lp_efuse_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_efuse_int_src_pass_in_sec:1;
+        /** core1_lp_efuse_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_efuse_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_efuse_int_map_reg_t;
+
+
+/** Group: CORE1 LP SW INT MAP REG */
+/** Type of lp_sw_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_sw_int_map:6;
+        /** core1_lp_sw_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_sw_int_src_pass_in_sec:1;
+        /** core1_lp_sw_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_sw_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_sw_int_map_reg_t;
+
+
+/** Group: CORE1 LP SYSREG INT MAP REG */
+/** Type of lp_sysreg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_sysreg_int_map:6;
+        /** core1_lp_sysreg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_sysreg_int_src_pass_in_sec:1;
+        /** core1_lp_sysreg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_sysreg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_sysreg_int_map_reg_t;
+
+
+/** Group: CORE1 LP HUK INT MAP REG */
+/** Type of lp_huk_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lp_huk_int_map:6;
+        /** core1_lp_huk_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_huk_int_src_pass_in_sec:1;
+        /** core1_lp_huk_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lp_huk_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lp_huk_int_map_reg_t;
+
+
+/** Group: CORE1 SYS ICM INT MAP REG */
+/** Type of sys_icm_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_sys_icm_int_map:6;
+        /** core1_sys_icm_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_sys_icm_int_src_pass_in_sec:1;
+        /** core1_sys_icm_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_sys_icm_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_sys_icm_int_map_reg_t;
+
+
+/** Group: CORE1 USB DEVICE INT MAP REG */
+/** Type of usb_device_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_usb_device_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_usb_device_int_map:6;
+        /** core1_usb_device_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_usb_device_int_src_pass_in_sec:1;
+        /** core1_usb_device_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_usb_device_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_usb_device_int_map_reg_t;
+
+
+/** Group: CORE1 SDIO HOST INT MAP REG */
+/** Type of sdio_host_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_sdio_host_int_map:6;
+        /** core1_sdio_host_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_sdio_host_int_src_pass_in_sec:1;
+        /** core1_sdio_host_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_sdio_host_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_sdio_host_int_map_reg_t;
+
+
+/** Group: CORE1 GDMA INT MAP REG */
+/** Type of gdma_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_gdma_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_gdma_int_map:6;
+        /** core1_gdma_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gdma_int_src_pass_in_sec:1;
+        /** core1_gdma_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gdma_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_gdma_int_map_reg_t;
+
+
+/** Group: CORE1 SPI2 INT MAP REG */
+/** Type of spi2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_spi2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_spi2_int_map:6;
+        /** core1_spi2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_spi2_int_src_pass_in_sec:1;
+        /** core1_spi2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_spi2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_spi2_int_map_reg_t;
+
+
+/** Group: CORE1 SPI3 INT MAP REG */
+/** Type of spi3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_spi3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_spi3_int_map:6;
+        /** core1_spi3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_spi3_int_src_pass_in_sec:1;
+        /** core1_spi3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_spi3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_spi3_int_map_reg_t;
+
+
+/** Group: CORE1 I2S0 INT MAP REG */
+/** Type of i2s0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_i2s0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_i2s0_int_map:6;
+        /** core1_i2s0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i2s0_int_src_pass_in_sec:1;
+        /** core1_i2s0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i2s0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_i2s0_int_map_reg_t;
+
+
+/** Group: CORE1 I2S1 INT MAP REG */
+/** Type of i2s1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_i2s1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_i2s1_int_map:6;
+        /** core1_i2s1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i2s1_int_src_pass_in_sec:1;
+        /** core1_i2s1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i2s1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_i2s1_int_map_reg_t;
+
+
+/** Group: CORE1 I2S2 INT MAP REG */
+/** Type of i2s2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_i2s2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_i2s2_int_map:6;
+        /** core1_i2s2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i2s2_int_src_pass_in_sec:1;
+        /** core1_i2s2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i2s2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_i2s2_int_map_reg_t;
+
+
+/** Group: CORE1 UHCI0 INT MAP REG */
+/** Type of uhci0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_uhci0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_uhci0_int_map:6;
+        /** core1_uhci0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uhci0_int_src_pass_in_sec:1;
+        /** core1_uhci0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uhci0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_uhci0_int_map_reg_t;
+
+
+/** Group: CORE1 UART0 INT MAP REG */
+/** Type of uart0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_uart0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_uart0_int_map:6;
+        /** core1_uart0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uart0_int_src_pass_in_sec:1;
+        /** core1_uart0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uart0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_uart0_int_map_reg_t;
+
+
+/** Group: CORE1 UART1 INT MAP REG */
+/** Type of uart1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_uart1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_uart1_int_map:6;
+        /** core1_uart1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uart1_int_src_pass_in_sec:1;
+        /** core1_uart1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uart1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_uart1_int_map_reg_t;
+
+
+/** Group: CORE1 UART2 INT MAP REG */
+/** Type of uart2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_uart2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_uart2_int_map:6;
+        /** core1_uart2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uart2_int_src_pass_in_sec:1;
+        /** core1_uart2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uart2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_uart2_int_map_reg_t;
+
+
+/** Group: CORE1 UART3 INT MAP REG */
+/** Type of uart3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_uart3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_uart3_int_map:6;
+        /** core1_uart3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uart3_int_src_pass_in_sec:1;
+        /** core1_uart3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uart3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_uart3_int_map_reg_t;
+
+
+/** Group: CORE1 UART4 INT MAP REG */
+/** Type of uart4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_uart4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_uart4_int_map:6;
+        /** core1_uart4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uart4_int_src_pass_in_sec:1;
+        /** core1_uart4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_uart4_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_uart4_int_map_reg_t;
+
+
+/** Group: CORE1 LCD CAM INT MAP REG */
+/** Type of lcd_cam_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lcd_cam_int_map:6;
+        /** core1_lcd_cam_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lcd_cam_int_src_pass_in_sec:1;
+        /** core1_lcd_cam_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lcd_cam_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lcd_cam_int_map_reg_t;
+
+
+/** Group: CORE1 ADC INT MAP REG */
+/** Type of adc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_adc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_adc_int_map:6;
+        /** core1_adc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_adc_int_src_pass_in_sec:1;
+        /** core1_adc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_adc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_adc_int_map_reg_t;
+
+
+/** Group: CORE1 PWM0 INT MAP REG */
+/** Type of pwm0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_pwm0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_pwm0_int_map:6;
+        /** core1_pwm0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pwm0_int_src_pass_in_sec:1;
+        /** core1_pwm0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pwm0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_pwm0_int_map_reg_t;
+
+
+/** Group: CORE1 PWM1 INT MAP REG */
+/** Type of pwm1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_pwm1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_pwm1_int_map:6;
+        /** core1_pwm1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pwm1_int_src_pass_in_sec:1;
+        /** core1_pwm1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pwm1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_pwm1_int_map_reg_t;
+
+
+/** Group: CORE1 CAN0 INT MAP REG */
+/** Type of can0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_can0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_can0_int_map:6;
+        /** core1_can0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_can0_int_src_pass_in_sec:1;
+        /** core1_can0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_can0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_can0_int_map_reg_t;
+
+
+/** Group: CORE1 CAN1 INT MAP REG */
+/** Type of can1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_can1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_can1_int_map:6;
+        /** core1_can1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_can1_int_src_pass_in_sec:1;
+        /** core1_can1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_can1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_can1_int_map_reg_t;
+
+
+/** Group: CORE1 CAN2 INT MAP REG */
+/** Type of can2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_can2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_can2_int_map:6;
+        /** core1_can2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_can2_int_src_pass_in_sec:1;
+        /** core1_can2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_can2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_can2_int_map_reg_t;
+
+
+/** Group: CORE1 RMT INT MAP REG */
+/** Type of rmt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_rmt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_rmt_int_map:6;
+        /** core1_rmt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_rmt_int_src_pass_in_sec:1;
+        /** core1_rmt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_rmt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_rmt_int_map_reg_t;
+
+
+/** Group: CORE1 I2C0 INT MAP REG */
+/** Type of i2c0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_i2c0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_i2c0_int_map:6;
+        /** core1_i2c0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i2c0_int_src_pass_in_sec:1;
+        /** core1_i2c0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i2c0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_i2c0_int_map_reg_t;
+
+
+/** Group: CORE1 I2C1 INT MAP REG */
+/** Type of i2c1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_i2c1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_i2c1_int_map:6;
+        /** core1_i2c1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i2c1_int_src_pass_in_sec:1;
+        /** core1_i2c1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i2c1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_i2c1_int_map_reg_t;
+
+
+/** Group: CORE1 TIMERGRP0 T0 INT MAP REG */
+/** Type of timergrp0_t0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_timergrp0_t0_int_map:6;
+        /** core1_timergrp0_t0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp0_t0_int_src_pass_in_sec:1;
+        /** core1_timergrp0_t0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp0_t0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_timergrp0_t0_int_map_reg_t;
+
+
+/** Group: CORE1 TIMERGRP0 T1 INT MAP REG */
+/** Type of timergrp0_t1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_timergrp0_t1_int_map:6;
+        /** core1_timergrp0_t1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp0_t1_int_src_pass_in_sec:1;
+        /** core1_timergrp0_t1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp0_t1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_timergrp0_t1_int_map_reg_t;
+
+
+/** Group: CORE1 TIMERGRP0 WDT INT MAP REG */
+/** Type of timergrp0_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_timergrp0_wdt_int_map:6;
+        /** core1_timergrp0_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp0_wdt_int_src_pass_in_sec:1;
+        /** core1_timergrp0_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp0_wdt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_timergrp0_wdt_int_map_reg_t;
+
+
+/** Group: CORE1 TIMERGRP1 T0 INT MAP REG */
+/** Type of timergrp1_t0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_timergrp1_t0_int_map:6;
+        /** core1_timergrp1_t0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp1_t0_int_src_pass_in_sec:1;
+        /** core1_timergrp1_t0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp1_t0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_timergrp1_t0_int_map_reg_t;
+
+
+/** Group: CORE1 TIMERGRP1 T1 INT MAP REG */
+/** Type of timergrp1_t1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_timergrp1_t1_int_map:6;
+        /** core1_timergrp1_t1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp1_t1_int_src_pass_in_sec:1;
+        /** core1_timergrp1_t1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp1_t1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_timergrp1_t1_int_map_reg_t;
+
+
+/** Group: CORE1 TIMERGRP1 WDT INT MAP REG */
+/** Type of timergrp1_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_timergrp1_wdt_int_map:6;
+        /** core1_timergrp1_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp1_wdt_int_src_pass_in_sec:1;
+        /** core1_timergrp1_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_timergrp1_wdt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_timergrp1_wdt_int_map_reg_t;
+
+
+/** Group: CORE1 LEDC INT MAP REG */
+/** Type of ledc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_ledc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_ledc_int_map:6;
+        /** core1_ledc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ledc_int_src_pass_in_sec:1;
+        /** core1_ledc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ledc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_ledc_int_map_reg_t;
+
+
+/** Group: CORE1 SYSTIMER TARGET0 INT MAP REG */
+/** Type of systimer_target0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_systimer_target0_int_map:6;
+        /** core1_systimer_target0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_systimer_target0_int_src_pass_in_sec:1;
+        /** core1_systimer_target0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_systimer_target0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_systimer_target0_int_map_reg_t;
+
+
+/** Group: CORE1 SYSTIMER TARGET1 INT MAP REG */
+/** Type of systimer_target1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_systimer_target1_int_map:6;
+        /** core1_systimer_target1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_systimer_target1_int_src_pass_in_sec:1;
+        /** core1_systimer_target1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_systimer_target1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_systimer_target1_int_map_reg_t;
+
+
+/** Group: CORE1 SYSTIMER TARGET2 INT MAP REG */
+/** Type of systimer_target2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_systimer_target2_int_map:6;
+        /** core1_systimer_target2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_systimer_target2_int_src_pass_in_sec:1;
+        /** core1_systimer_target2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_systimer_target2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_systimer_target2_int_map_reg_t;
+
+
+/** Group: CORE1 AHB PDMA IN CH0 INT MAP REG */
+/** Type of ahb_pdma_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_ahb_pdma_in_ch0_int_map:6;
+        /** core1_ahb_pdma_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_in_ch0_int_src_pass_in_sec:1;
+        /** core1_ahb_pdma_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_ahb_pdma_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE1 AHB PDMA IN CH1 INT MAP REG */
+/** Type of ahb_pdma_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_ahb_pdma_in_ch1_int_map:6;
+        /** core1_ahb_pdma_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_in_ch1_int_src_pass_in_sec:1;
+        /** core1_ahb_pdma_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_ahb_pdma_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE1 AHB PDMA IN CH2 INT MAP REG */
+/** Type of ahb_pdma_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_ahb_pdma_in_ch2_int_map:6;
+        /** core1_ahb_pdma_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_in_ch2_int_src_pass_in_sec:1;
+        /** core1_ahb_pdma_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_ahb_pdma_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE1 AHB PDMA OUT CH0 INT MAP REG */
+/** Type of ahb_pdma_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_ahb_pdma_out_ch0_int_map:6;
+        /** core1_ahb_pdma_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_out_ch0_int_src_pass_in_sec:1;
+        /** core1_ahb_pdma_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_ahb_pdma_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE1 AHB PDMA OUT CH1 INT MAP REG */
+/** Type of ahb_pdma_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_ahb_pdma_out_ch1_int_map:6;
+        /** core1_ahb_pdma_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_out_ch1_int_src_pass_in_sec:1;
+        /** core1_ahb_pdma_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_ahb_pdma_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE1 AHB PDMA OUT CH2 INT MAP REG */
+/** Type of ahb_pdma_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_ahb_pdma_out_ch2_int_map:6;
+        /** core1_ahb_pdma_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_out_ch2_int_src_pass_in_sec:1;
+        /** core1_ahb_pdma_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ahb_pdma_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_ahb_pdma_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE1 AXI PDMA IN CH0 INT MAP REG */
+/** Type of axi_pdma_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_axi_pdma_in_ch0_int_map:6;
+        /** core1_axi_pdma_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_in_ch0_int_src_pass_in_sec:1;
+        /** core1_axi_pdma_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_axi_pdma_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE1 AXI PDMA IN CH1 INT MAP REG */
+/** Type of axi_pdma_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_axi_pdma_in_ch1_int_map:6;
+        /** core1_axi_pdma_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_in_ch1_int_src_pass_in_sec:1;
+        /** core1_axi_pdma_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_axi_pdma_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE1 AXI PDMA IN CH2 INT MAP REG */
+/** Type of axi_pdma_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_axi_pdma_in_ch2_int_map:6;
+        /** core1_axi_pdma_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_in_ch2_int_src_pass_in_sec:1;
+        /** core1_axi_pdma_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_axi_pdma_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE1 AXI PDMA OUT CH0 INT MAP REG */
+/** Type of axi_pdma_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_axi_pdma_out_ch0_int_map:6;
+        /** core1_axi_pdma_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_out_ch0_int_src_pass_in_sec:1;
+        /** core1_axi_pdma_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_axi_pdma_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE1 AXI PDMA OUT CH1 INT MAP REG */
+/** Type of axi_pdma_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_axi_pdma_out_ch1_int_map:6;
+        /** core1_axi_pdma_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_out_ch1_int_src_pass_in_sec:1;
+        /** core1_axi_pdma_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_axi_pdma_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE1 AXI PDMA OUT CH2 INT MAP REG */
+/** Type of axi_pdma_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_axi_pdma_out_ch2_int_map:6;
+        /** core1_axi_pdma_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_out_ch2_int_src_pass_in_sec:1;
+        /** core1_axi_pdma_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_pdma_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_axi_pdma_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE1 RSA INT MAP REG */
+/** Type of rsa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_rsa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_rsa_int_map:6;
+        /** core1_rsa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_rsa_int_src_pass_in_sec:1;
+        /** core1_rsa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_rsa_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_rsa_int_map_reg_t;
+
+
+/** Group: CORE1 AES INT MAP REG */
+/** Type of aes_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_aes_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_aes_int_map:6;
+        /** core1_aes_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_aes_int_src_pass_in_sec:1;
+        /** core1_aes_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_aes_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_aes_int_map_reg_t;
+
+
+/** Group: CORE1 SHA INT MAP REG */
+/** Type of sha_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_sha_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_sha_int_map:6;
+        /** core1_sha_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_sha_int_src_pass_in_sec:1;
+        /** core1_sha_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_sha_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_sha_int_map_reg_t;
+
+
+/** Group: CORE1 ECC INT MAP REG */
+/** Type of ecc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_ecc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_ecc_int_map:6;
+        /** core1_ecc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ecc_int_src_pass_in_sec:1;
+        /** core1_ecc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ecc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_ecc_int_map_reg_t;
+
+
+/** Group: CORE1 ECDSA INT MAP REG */
+/** Type of ecdsa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_ecdsa_int_map:6;
+        /** core1_ecdsa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ecdsa_int_src_pass_in_sec:1;
+        /** core1_ecdsa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ecdsa_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_ecdsa_int_map_reg_t;
+
+
+/** Group: CORE1 KM INT MAP REG */
+/** Type of km_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_km_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_km_int_map:6;
+        /** core1_km_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_km_int_src_pass_in_sec:1;
+        /** core1_km_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_km_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_km_int_map_reg_t;
+
+
+/** Group: CORE1 GPIO INT0 MAP REG */
+/** Type of gpio_int0_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_gpio_int0_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_gpio_int0_map:6;
+        /** core1_gpio_int0_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gpio_int0_src_pass_in_sec:1;
+        /** core1_gpio_int0_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gpio_int0_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_gpio_int0_map_reg_t;
+
+
+/** Group: CORE1 GPIO INT1 MAP REG */
+/** Type of gpio_int1_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_gpio_int1_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_gpio_int1_map:6;
+        /** core1_gpio_int1_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gpio_int1_src_pass_in_sec:1;
+        /** core1_gpio_int1_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gpio_int1_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_gpio_int1_map_reg_t;
+
+
+/** Group: CORE1 GPIO INT2 MAP REG */
+/** Type of gpio_int2_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_gpio_int2_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_gpio_int2_map:6;
+        /** core1_gpio_int2_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gpio_int2_src_pass_in_sec:1;
+        /** core1_gpio_int2_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gpio_int2_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_gpio_int2_map_reg_t;
+
+
+/** Group: CORE1 GPIO INT3 MAP REG */
+/** Type of gpio_int3_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_gpio_int3_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_gpio_int3_map:6;
+        /** core1_gpio_int3_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gpio_int3_src_pass_in_sec:1;
+        /** core1_gpio_int3_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gpio_int3_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_gpio_int3_map_reg_t;
+
+
+/** Group: CORE1 GPIO PAD COMP INT MAP REG */
+/** Type of gpio_pad_comp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_gpio_pad_comp_int_map:6;
+        /** core1_gpio_pad_comp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gpio_pad_comp_int_src_pass_in_sec:1;
+        /** core1_gpio_pad_comp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gpio_pad_comp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_gpio_pad_comp_int_map_reg_t;
+
+
+/** Group: CORE1 CPU INT FROM CPU 0 MAP REG */
+/** Type of cpu_int_from_cpu_0_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_cpu_int_from_cpu_0_map:6;
+        /** core1_cpu_int_from_cpu_0_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_cpu_int_from_cpu_0_src_pass_in_sec:1;
+        /** core1_cpu_int_from_cpu_0_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_cpu_int_from_cpu_0_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_cpu_int_from_cpu_0_map_reg_t;
+
+
+/** Group: CORE1 CPU INT FROM CPU 1 MAP REG */
+/** Type of cpu_int_from_cpu_1_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_cpu_int_from_cpu_1_map:6;
+        /** core1_cpu_int_from_cpu_1_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_cpu_int_from_cpu_1_src_pass_in_sec:1;
+        /** core1_cpu_int_from_cpu_1_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_cpu_int_from_cpu_1_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_cpu_int_from_cpu_1_map_reg_t;
+
+
+/** Group: CORE1 CPU INT FROM CPU 2 MAP REG */
+/** Type of cpu_int_from_cpu_2_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_cpu_int_from_cpu_2_map:6;
+        /** core1_cpu_int_from_cpu_2_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_cpu_int_from_cpu_2_src_pass_in_sec:1;
+        /** core1_cpu_int_from_cpu_2_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_cpu_int_from_cpu_2_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_cpu_int_from_cpu_2_map_reg_t;
+
+
+/** Group: CORE1 CPU INT FROM CPU 3 MAP REG */
+/** Type of cpu_int_from_cpu_3_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_cpu_int_from_cpu_3_map:6;
+        /** core1_cpu_int_from_cpu_3_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_cpu_int_from_cpu_3_src_pass_in_sec:1;
+        /** core1_cpu_int_from_cpu_3_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_cpu_int_from_cpu_3_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_cpu_int_from_cpu_3_map_reg_t;
+
+
+/** Group: CORE1 CACHE INT MAP REG */
+/** Type of cache_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_cache_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_cache_int_map:6;
+        /** core1_cache_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_cache_int_src_pass_in_sec:1;
+        /** core1_cache_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_cache_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_cache_int_map_reg_t;
+
+
+/** Group: CORE1 FLASH MSPI INT MAP REG */
+/** Type of flash_mspi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_flash_mspi_int_map:6;
+        /** core1_flash_mspi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_flash_mspi_int_src_pass_in_sec:1;
+        /** core1_flash_mspi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_flash_mspi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_flash_mspi_int_map_reg_t;
+
+
+/** Group: CORE1 CSI BRIDGE INT MAP REG */
+/** Type of csi_bridge_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_csi_bridge_int_map:6;
+        /** core1_csi_bridge_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_csi_bridge_int_src_pass_in_sec:1;
+        /** core1_csi_bridge_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_csi_bridge_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_csi_bridge_int_map_reg_t;
+
+
+/** Group: CORE1 DSI BRIDGE INT MAP REG */
+/** Type of dsi_bridge_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_dsi_bridge_int_map:6;
+        /** core1_dsi_bridge_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dsi_bridge_int_src_pass_in_sec:1;
+        /** core1_dsi_bridge_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dsi_bridge_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_dsi_bridge_int_map_reg_t;
+
+
+/** Group: CORE1 CSI INT MAP REG */
+/** Type of csi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_csi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_csi_int_map:6;
+        /** core1_csi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_csi_int_src_pass_in_sec:1;
+        /** core1_csi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_csi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_csi_int_map_reg_t;
+
+
+/** Group: CORE1 DSI INT MAP REG */
+/** Type of dsi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_dsi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_dsi_int_map:6;
+        /** core1_dsi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dsi_int_src_pass_in_sec:1;
+        /** core1_dsi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dsi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_dsi_int_map_reg_t;
+
+
+/** Group: CORE1 GMII PHY INT MAP REG */
+/** Type of gmii_phy_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_gmii_phy_int_map:6;
+        /** core1_gmii_phy_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gmii_phy_int_src_pass_in_sec:1;
+        /** core1_gmii_phy_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_gmii_phy_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_gmii_phy_int_map_reg_t;
+
+
+/** Group: CORE1 LPI INT MAP REG */
+/** Type of lpi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_lpi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_lpi_int_map:6;
+        /** core1_lpi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lpi_int_src_pass_in_sec:1;
+        /** core1_lpi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_lpi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_lpi_int_map_reg_t;
+
+
+/** Group: CORE1 PMT INT MAP REG */
+/** Type of pmt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_pmt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_pmt_int_map:6;
+        /** core1_pmt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pmt_int_src_pass_in_sec:1;
+        /** core1_pmt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pmt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_pmt_int_map_reg_t;
+
+
+/** Group: CORE1 SBD INT MAP REG */
+/** Type of sbd_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_sbd_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_sbd_int_map:6;
+        /** core1_sbd_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_sbd_int_src_pass_in_sec:1;
+        /** core1_sbd_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_sbd_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_sbd_int_map_reg_t;
+
+
+/** Group: CORE1 USB OTG INT MAP REG */
+/** Type of usb_otg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_usb_otg_int_map:6;
+        /** core1_usb_otg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_usb_otg_int_src_pass_in_sec:1;
+        /** core1_usb_otg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_usb_otg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_usb_otg_int_map_reg_t;
+
+
+/** Group: CORE1 USB OTG ENDP MULTI PROC INT MAP REG */
+/** Type of usb_otg_endp_multi_proc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_usb_otg_endp_multi_proc_int_map:6;
+        /** core1_usb_otg_endp_multi_proc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_usb_otg_endp_multi_proc_int_src_pass_in_sec:1;
+        /** core1_usb_otg_endp_multi_proc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_usb_otg_endp_multi_proc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_usb_otg_endp_multi_proc_int_map_reg_t;
+
+
+/** Group: CORE1 JPEG INT MAP REG */
+/** Type of jpeg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_jpeg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_jpeg_int_map:6;
+        /** core1_jpeg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_jpeg_int_src_pass_in_sec:1;
+        /** core1_jpeg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_jpeg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_jpeg_int_map_reg_t;
+
+
+/** Group: CORE1 PPA INT MAP REG */
+/** Type of ppa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_ppa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_ppa_int_map:6;
+        /** core1_ppa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ppa_int_src_pass_in_sec:1;
+        /** core1_ppa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_ppa_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_ppa_int_map_reg_t;
+
+
+/** Group: CORE1 CORE0 TRACE INT MAP REG */
+/** Type of core0_trace_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_core0_trace_int_map:6;
+        /** core1_core0_trace_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_core0_trace_int_src_pass_in_sec:1;
+        /** core1_core0_trace_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_core0_trace_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_core0_trace_int_map_reg_t;
+
+
+/** Group: CORE1 CORE1 TRACE INT MAP REG */
+/** Type of core1_trace_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_core1_trace_int_map:6;
+        /** core1_core1_trace_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_core1_trace_int_src_pass_in_sec:1;
+        /** core1_core1_trace_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_core1_trace_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_core1_trace_int_map_reg_t;
+
+
+/** Group: CORE1 HP CORE CTRL INT MAP REG */
+/** Type of hp_core_ctrl_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_hp_core_ctrl_int_map:6;
+        /** core1_hp_core_ctrl_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_hp_core_ctrl_int_src_pass_in_sec:1;
+        /** core1_hp_core_ctrl_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_hp_core_ctrl_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_hp_core_ctrl_int_map_reg_t;
+
+
+/** Group: CORE1 ISP INT MAP REG */
+/** Type of isp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_isp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_isp_int_map:6;
+        /** core1_isp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_isp_int_src_pass_in_sec:1;
+        /** core1_isp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_isp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_isp_int_map_reg_t;
+
+
+/** Group: CORE1 I3C MST INT MAP REG */
+/** Type of i3c_mst_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_i3c_mst_int_map:6;
+        /** core1_i3c_mst_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i3c_mst_int_src_pass_in_sec:1;
+        /** core1_i3c_mst_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i3c_mst_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_i3c_mst_int_map_reg_t;
+
+
+/** Group: CORE1 I3C SLV INT MAP REG */
+/** Type of i3c_slv_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_i3c_slv_int_map:6;
+        /** core1_i3c_slv_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i3c_slv_int_src_pass_in_sec:1;
+        /** core1_i3c_slv_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_i3c_slv_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_i3c_slv_int_map_reg_t;
+
+
+/** Group: CORE1 USB OTG11 INT MAP REG */
+/** Type of usb_otg11_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_usb_otg11_int_map:6;
+        /** core1_usb_otg11_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_usb_otg11_int_src_pass_in_sec:1;
+        /** core1_usb_otg11_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_usb_otg11_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_usb_otg11_int_map_reg_t;
+
+
+/** Group: CORE1 DMA2D IN CH0 INT MAP REG */
+/** Type of dma2d_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_dma2d_in_ch0_int_map:6;
+        /** core1_dma2d_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_in_ch0_int_src_pass_in_sec:1;
+        /** core1_dma2d_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_dma2d_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE1 DMA2D IN CH1 INT MAP REG */
+/** Type of dma2d_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_dma2d_in_ch1_int_map:6;
+        /** core1_dma2d_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_in_ch1_int_src_pass_in_sec:1;
+        /** core1_dma2d_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_dma2d_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE1 DMA2D OUT CH0 INT MAP REG */
+/** Type of dma2d_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_dma2d_out_ch0_int_map:6;
+        /** core1_dma2d_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_out_ch0_int_src_pass_in_sec:1;
+        /** core1_dma2d_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_dma2d_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE1 DMA2D OUT CH1 INT MAP REG */
+/** Type of dma2d_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_dma2d_out_ch1_int_map:6;
+        /** core1_dma2d_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_out_ch1_int_src_pass_in_sec:1;
+        /** core1_dma2d_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_dma2d_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE1 DMA2D OUT CH2 INT MAP REG */
+/** Type of dma2d_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_dma2d_out_ch2_int_map:6;
+        /** core1_dma2d_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_out_ch2_int_src_pass_in_sec:1;
+        /** core1_dma2d_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_dma2d_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE1 PSRAM MSPI INT MAP REG */
+/** Type of psram_mspi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_psram_mspi_int_map:6;
+        /** core1_psram_mspi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_psram_mspi_int_src_pass_in_sec:1;
+        /** core1_psram_mspi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_psram_mspi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_psram_mspi_int_map_reg_t;
+
+
+/** Group: CORE1 HP SYSREG INT MAP REG */
+/** Type of hp_sysreg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_hp_sysreg_int_map:6;
+        /** core1_hp_sysreg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_hp_sysreg_int_src_pass_in_sec:1;
+        /** core1_hp_sysreg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_hp_sysreg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_hp_sysreg_int_map_reg_t;
+
+
+/** Group: CORE1 PCNT INT MAP REG */
+/** Type of pcnt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_pcnt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_pcnt_int_map:6;
+        /** core1_pcnt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pcnt_int_src_pass_in_sec:1;
+        /** core1_pcnt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_pcnt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_pcnt_int_map_reg_t;
+
+
+/** Group: CORE1 HP PAU INT MAP REG */
+/** Type of hp_pau_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_hp_pau_int_map:6;
+        /** core1_hp_pau_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_hp_pau_int_src_pass_in_sec:1;
+        /** core1_hp_pau_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_hp_pau_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_hp_pau_int_map_reg_t;
+
+
+/** Group: CORE1 HP PARLIO RX INT MAP REG */
+/** Type of hp_parlio_rx_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_hp_parlio_rx_int_map:6;
+        /** core1_hp_parlio_rx_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_hp_parlio_rx_int_src_pass_in_sec:1;
+        /** core1_hp_parlio_rx_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_hp_parlio_rx_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_hp_parlio_rx_int_map_reg_t;
+
+
+/** Group: CORE1 HP PARLIO TX INT MAP REG */
+/** Type of hp_parlio_tx_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_hp_parlio_tx_int_map:6;
+        /** core1_hp_parlio_tx_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_hp_parlio_tx_int_src_pass_in_sec:1;
+        /** core1_hp_parlio_tx_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_hp_parlio_tx_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_hp_parlio_tx_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D OUT CH0 INT MAP REG */
+/** Type of h264_dma2d_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_out_ch0_int_map:6;
+        /** core1_h264_dma2d_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_out_ch0_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D OUT CH1 INT MAP REG */
+/** Type of h264_dma2d_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_out_ch1_int_map:6;
+        /** core1_h264_dma2d_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_out_ch1_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D OUT CH2 INT MAP REG */
+/** Type of h264_dma2d_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_out_ch2_int_map:6;
+        /** core1_h264_dma2d_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_out_ch2_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D OUT CH3 INT MAP REG */
+/** Type of h264_dma2d_out_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_out_ch3_int_map:6;
+        /** core1_h264_dma2d_out_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_out_ch3_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_out_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_out_ch3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_out_ch3_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D OUT CH4 INT MAP REG */
+/** Type of h264_dma2d_out_ch4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_out_ch4_int_map:6;
+        /** core1_h264_dma2d_out_ch4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_out_ch4_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_out_ch4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_out_ch4_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_out_ch4_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D IN CH0 INT MAP REG */
+/** Type of h264_dma2d_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_in_ch0_int_map:6;
+        /** core1_h264_dma2d_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch0_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D IN CH1 INT MAP REG */
+/** Type of h264_dma2d_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_in_ch1_int_map:6;
+        /** core1_h264_dma2d_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch1_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D IN CH2 INT MAP REG */
+/** Type of h264_dma2d_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_in_ch2_int_map:6;
+        /** core1_h264_dma2d_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch2_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D IN CH3 INT MAP REG */
+/** Type of h264_dma2d_in_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_in_ch3_int_map:6;
+        /** core1_h264_dma2d_in_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch3_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_in_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_in_ch3_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D IN CH4 INT MAP REG */
+/** Type of h264_dma2d_in_ch4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_in_ch4_int_map:6;
+        /** core1_h264_dma2d_in_ch4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch4_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_in_ch4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch4_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_in_ch4_int_map_reg_t;
+
+
+/** Group: CORE1 H264 DMA2D IN CH5 INT MAP REG */
+/** Type of h264_dma2d_in_ch5_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_dma2d_in_ch5_int_map:6;
+        /** core1_h264_dma2d_in_ch5_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch5_int_src_pass_in_sec:1;
+        /** core1_h264_dma2d_in_ch5_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_dma2d_in_ch5_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_dma2d_in_ch5_int_map_reg_t;
+
+
+/** Group: CORE1 H264 REG INT MAP REG */
+/** Type of h264_reg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_h264_reg_int_map:6;
+        /** core1_h264_reg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_reg_int_src_pass_in_sec:1;
+        /** core1_h264_reg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_h264_reg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_h264_reg_int_map_reg_t;
+
+
+/** Group: CORE1 ASSIST DEBUG INT MAP REG */
+/** Type of assist_debug_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_assist_debug_int_map:6;
+        /** core1_assist_debug_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_assist_debug_int_src_pass_in_sec:1;
+        /** core1_assist_debug_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_assist_debug_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_assist_debug_int_map_reg_t;
+
+
+/** Group: CORE1 INTR STATUS REG 0 REG */
+/** Type of intr_status_reg_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_status_0:32;
+    };
+    uint32_t val;
+} core1_intr_status_reg_0_reg_t;
+
+
+/** Group: CORE1 INTR STATUS REG 1 REG */
+/** Type of intr_status_reg_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_status_1:32;
+    };
+    uint32_t val;
+} core1_intr_status_reg_1_reg_t;
+
+
+/** Group: CORE1 INTR STATUS REG 2 REG */
+/** Type of intr_status_reg_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_status_2:32;
+    };
+    uint32_t val;
+} core1_intr_status_reg_2_reg_t;
+
+
+/** Group: CORE1 INTR STATUS REG 3 REG */
+/** Type of intr_status_reg_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_status_3:32;
+    };
+    uint32_t val;
+} core1_intr_status_reg_3_reg_t;
+
+
+/** Group: CORE1 CLOCK GATE REG */
+/** Type of clock_gate register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t core1_reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} core1_clock_gate_reg_t;
+
+
+/** Group: CORE1 DMA2D IN CH2 INT MAP REG */
+/** Type of dma2d_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_dma2d_in_ch2_int_map:6;
+        /** core1_dma2d_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_in_ch2_int_src_pass_in_sec:1;
+        /** core1_dma2d_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_dma2d_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE1 DMA2D OUT CH3 INT MAP REG */
+/** Type of dma2d_out_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_dma2d_out_ch3_int_map:6;
+        /** core1_dma2d_out_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_out_ch3_int_src_pass_in_sec:1;
+        /** core1_dma2d_out_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_dma2d_out_ch3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_dma2d_out_ch3_int_map_reg_t;
+
+
+/** Group: CORE1 AXI PERF MON INT MAP REG */
+/** Type of axi_perf_mon_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_axi_perf_mon_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_axi_perf_mon_int_map:6;
+        /** core1_axi_perf_mon_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_perf_mon_int_src_pass_in_sec:1;
+        /** core1_axi_perf_mon_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core1_axi_perf_mon_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core1_axi_perf_mon_int_map_reg_t;
+
+
+/** Group: CORE1 INTR STATUS REG 4 REG */
+/** Type of intr_status_reg_4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_status_4:32;
+    };
+    uint32_t val;
+} core1_intr_status_reg_4_reg_t;
+
+
+/** Group: CORE1 INTR SIG IDX ASSERT IN SEC REG */
+/** Type of intr_sig_idx_assert_in_sec register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_sig_idx_assert_in_sec : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_sig_idx_assert_in_sec:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} core1_intr_sig_idx_assert_in_sec_reg_t;
+
+
+/** Group: CORE1 INTR SEC STATUS REG */
+/** Type of intr_sec_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_sec_status : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_sec_status:32;
+    };
+    uint32_t val;
+} core1_intr_sec_status_reg_t;
+
+
+/** Group: CORE1 INTR SRC PASS IN SEC STATUS 0 REG */
+/** Type of intr_src_pass_in_sec_status_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_src_pass_in_sec_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_src_pass_in_sec_status_0:32;
+    };
+    uint32_t val;
+} core1_intr_src_pass_in_sec_status_0_reg_t;
+
+
+/** Group: CORE1 INTR SRC PASS IN SEC STATUS 1 REG */
+/** Type of intr_src_pass_in_sec_status_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_src_pass_in_sec_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_src_pass_in_sec_status_1:32;
+    };
+    uint32_t val;
+} core1_intr_src_pass_in_sec_status_1_reg_t;
+
+
+/** Group: CORE1 INTR SRC PASS IN SEC STATUS 2 REG */
+/** Type of intr_src_pass_in_sec_status_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_src_pass_in_sec_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_src_pass_in_sec_status_2:32;
+    };
+    uint32_t val;
+} core1_intr_src_pass_in_sec_status_2_reg_t;
+
+
+/** Group: CORE1 INTR SRC PASS IN SEC STATUS 3 REG */
+/** Type of intr_src_pass_in_sec_status_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_src_pass_in_sec_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_src_pass_in_sec_status_3:32;
+    };
+    uint32_t val;
+} core1_intr_src_pass_in_sec_status_3_reg_t;
+
+
+/** Group: CORE1 INTR SRC PASS IN SEC STATUS 4 REG */
+/** Type of intr_src_pass_in_sec_status_4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_intr_src_pass_in_sec_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core1_intr_src_pass_in_sec_status_4:32;
+    };
+    uint32_t val;
+} core1_intr_src_pass_in_sec_status_4_reg_t;
+
+
+/** Group: CORE1 INTERRUPT REG DATE REG */
+/** Type of interrupt_reg_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core1_interrupt_reg_date : R/W; bitpos: [27:0]; default: 38806144;
+         *  NA
+         */
+        uint32_t core1_interrupt_reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} core1_interrupt_reg_date_reg_t;
+
+
+typedef struct {
+    volatile core1_lp_rtc_int_map_reg_t lp_rtc_int_map;
+    volatile core1_lp_wdt_int_map_reg_t lp_wdt_int_map;
+    volatile core1_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map;
+    volatile core1_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map;
+    volatile core1_mb_hp_int_map_reg_t mb_hp_int_map;
+    volatile core1_mb_lp_int_map_reg_t mb_lp_int_map;
+    volatile core1_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map;
+    volatile core1_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map;
+    volatile core1_lp_anaperi_int_map_reg_t lp_anaperi_int_map;
+    volatile core1_lp_adc_int_map_reg_t lp_adc_int_map;
+    volatile core1_lp_gpio_int_map_reg_t lp_gpio_int_map;
+    volatile core1_lp_i2c_int_map_reg_t lp_i2c_int_map;
+    volatile core1_lp_i2s_int_map_reg_t lp_i2s_int_map;
+    volatile core1_lp_spi_int_map_reg_t lp_spi_int_map;
+    volatile core1_lp_touch_int_map_reg_t lp_touch_int_map;
+    volatile core1_lp_tsens_int_map_reg_t lp_tsens_int_map;
+    volatile core1_lp_uart_int_map_reg_t lp_uart_int_map;
+    volatile core1_lp_efuse_int_map_reg_t lp_efuse_int_map;
+    volatile core1_lp_sw_int_map_reg_t lp_sw_int_map;
+    volatile core1_lp_sysreg_int_map_reg_t lp_sysreg_int_map;
+    volatile core1_lp_huk_int_map_reg_t lp_huk_int_map;
+    volatile core1_sys_icm_int_map_reg_t sys_icm_int_map;
+    volatile core1_usb_device_int_map_reg_t usb_device_int_map;
+    volatile core1_sdio_host_int_map_reg_t sdio_host_int_map;
+    volatile core1_gdma_int_map_reg_t gdma_int_map;
+    volatile core1_spi2_int_map_reg_t spi2_int_map;
+    volatile core1_spi3_int_map_reg_t spi3_int_map;
+    volatile core1_i2s0_int_map_reg_t i2s0_int_map;
+    volatile core1_i2s1_int_map_reg_t i2s1_int_map;
+    volatile core1_i2s2_int_map_reg_t i2s2_int_map;
+    volatile core1_uhci0_int_map_reg_t uhci0_int_map;
+    volatile core1_uart0_int_map_reg_t uart0_int_map;
+    volatile core1_uart1_int_map_reg_t uart1_int_map;
+    volatile core1_uart2_int_map_reg_t uart2_int_map;
+    volatile core1_uart3_int_map_reg_t uart3_int_map;
+    volatile core1_uart4_int_map_reg_t uart4_int_map;
+    volatile core1_lcd_cam_int_map_reg_t lcd_cam_int_map;
+    volatile core1_adc_int_map_reg_t adc_int_map;
+    volatile core1_pwm0_int_map_reg_t pwm0_int_map;
+    volatile core1_pwm1_int_map_reg_t pwm1_int_map;
+    volatile core1_can0_int_map_reg_t can0_int_map;
+    volatile core1_can1_int_map_reg_t can1_int_map;
+    volatile core1_can2_int_map_reg_t can2_int_map;
+    volatile core1_rmt_int_map_reg_t rmt_int_map;
+    volatile core1_i2c0_int_map_reg_t i2c0_int_map;
+    volatile core1_i2c1_int_map_reg_t i2c1_int_map;
+    volatile core1_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map;
+    volatile core1_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map;
+    volatile core1_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map;
+    volatile core1_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map;
+    volatile core1_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map;
+    volatile core1_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map;
+    volatile core1_ledc_int_map_reg_t ledc_int_map;
+    volatile core1_systimer_target0_int_map_reg_t systimer_target0_int_map;
+    volatile core1_systimer_target1_int_map_reg_t systimer_target1_int_map;
+    volatile core1_systimer_target2_int_map_reg_t systimer_target2_int_map;
+    volatile core1_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map;
+    volatile core1_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map;
+    volatile core1_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map;
+    volatile core1_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map;
+    volatile core1_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map;
+    volatile core1_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map;
+    volatile core1_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map;
+    volatile core1_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map;
+    volatile core1_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map;
+    volatile core1_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map;
+    volatile core1_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map;
+    volatile core1_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map;
+    volatile core1_rsa_int_map_reg_t rsa_int_map;
+    volatile core1_aes_int_map_reg_t aes_int_map;
+    volatile core1_sha_int_map_reg_t sha_int_map;
+    volatile core1_ecc_int_map_reg_t ecc_int_map;
+    volatile core1_ecdsa_int_map_reg_t ecdsa_int_map;
+    volatile core1_km_int_map_reg_t km_int_map;
+    volatile core1_gpio_int0_map_reg_t gpio_int0_map;
+    volatile core1_gpio_int1_map_reg_t gpio_int1_map;
+    volatile core1_gpio_int2_map_reg_t gpio_int2_map;
+    volatile core1_gpio_int3_map_reg_t gpio_int3_map;
+    volatile core1_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map;
+    volatile core1_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map;
+    volatile core1_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map;
+    volatile core1_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map;
+    volatile core1_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map;
+    volatile core1_cache_int_map_reg_t cache_int_map;
+    volatile core1_flash_mspi_int_map_reg_t flash_mspi_int_map;
+    volatile core1_csi_bridge_int_map_reg_t csi_bridge_int_map;
+    volatile core1_dsi_bridge_int_map_reg_t dsi_bridge_int_map;
+    volatile core1_csi_int_map_reg_t csi_int_map;
+    volatile core1_dsi_int_map_reg_t dsi_int_map;
+    volatile core1_gmii_phy_int_map_reg_t gmii_phy_int_map;
+    volatile core1_lpi_int_map_reg_t lpi_int_map;
+    volatile core1_pmt_int_map_reg_t pmt_int_map;
+    volatile core1_sbd_int_map_reg_t sbd_int_map;
+    volatile core1_usb_otg_int_map_reg_t usb_otg_int_map;
+    volatile core1_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map;
+    volatile core1_jpeg_int_map_reg_t jpeg_int_map;
+    volatile core1_ppa_int_map_reg_t ppa_int_map;
+    volatile core1_core0_trace_int_map_reg_t core0_trace_int_map;
+    volatile core1_core1_trace_int_map_reg_t core1_trace_int_map;
+    volatile core1_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map;
+    volatile core1_isp_int_map_reg_t isp_int_map;
+    volatile core1_i3c_mst_int_map_reg_t i3c_mst_int_map;
+    volatile core1_i3c_slv_int_map_reg_t i3c_slv_int_map;
+    volatile core1_usb_otg11_int_map_reg_t usb_otg11_int_map;
+    volatile core1_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map;
+    volatile core1_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map;
+    volatile core1_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map;
+    volatile core1_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map;
+    volatile core1_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map;
+    volatile core1_psram_mspi_int_map_reg_t psram_mspi_int_map;
+    volatile core1_hp_sysreg_int_map_reg_t hp_sysreg_int_map;
+    volatile core1_pcnt_int_map_reg_t pcnt_int_map;
+    volatile core1_hp_pau_int_map_reg_t hp_pau_int_map;
+    volatile core1_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map;
+    volatile core1_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map;
+    volatile core1_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map;
+    volatile core1_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map;
+    volatile core1_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map;
+    volatile core1_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map;
+    volatile core1_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map;
+    volatile core1_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map;
+    volatile core1_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map;
+    volatile core1_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map;
+    volatile core1_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map;
+    volatile core1_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map;
+    volatile core1_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map;
+    volatile core1_h264_reg_int_map_reg_t h264_reg_int_map;
+    volatile core1_assist_debug_int_map_reg_t assist_debug_int_map;
+    volatile core1_intr_status_reg_0_reg_t intr_status_reg_0;
+    volatile core1_intr_status_reg_1_reg_t intr_status_reg_1;
+    volatile core1_intr_status_reg_2_reg_t intr_status_reg_2;
+    volatile core1_intr_status_reg_3_reg_t intr_status_reg_3;
+    volatile core1_clock_gate_reg_t clock_gate;
+    volatile core1_dma2d_in_ch2_int_map_reg_t dma2d_in_ch2_int_map;
+    volatile core1_dma2d_out_ch3_int_map_reg_t dma2d_out_ch3_int_map;
+    volatile core1_axi_perf_mon_int_map_reg_t axi_perf_mon_int_map;
+    volatile core1_intr_status_reg_4_reg_t intr_status_reg_4;
+    uint32_t reserved_224;
+    volatile core1_intr_sig_idx_assert_in_sec_reg_t intr_sig_idx_assert_in_sec;
+    volatile core1_intr_sec_status_reg_t intr_sec_status;
+    volatile core1_intr_src_pass_in_sec_status_0_reg_t intr_src_pass_in_sec_status_0;
+    volatile core1_intr_src_pass_in_sec_status_1_reg_t intr_src_pass_in_sec_status_1;
+    volatile core1_intr_src_pass_in_sec_status_2_reg_t intr_src_pass_in_sec_status_2;
+    volatile core1_intr_src_pass_in_sec_status_3_reg_t intr_src_pass_in_sec_status_3;
+    volatile core1_intr_src_pass_in_sec_status_4_reg_t intr_src_pass_in_sec_status_4;
+    uint32_t reserved_244[110];
+    volatile core1_interrupt_reg_date_reg_t interrupt_reg_date;
+} core1_dev_t;
+
+extern core1_dev_t INTR_CORE0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(core1_dev_t) == 0x400, "Invalid size of core1_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/interrupts.h b/components/soc/esp32p4/register/hw_ver3/soc/interrupts.h
new file mode 100644
index 0000000000..2b03a849a4
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/interrupts.h
@@ -0,0 +1,157 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//Interrupt hardware source table
+//This table is decided by hardware, don't touch this.
+typedef enum {
+    ETS_LP_RTC_INT_SOURCE,
+    ETS_LP_WDT_INT_SOURCE,
+    ETS_LP_TIMER_REG_0_INT_SOURCE,
+    ETS_LP_TIMER_REG_1_INT_SOURCE,
+    ETS_MB_HP_INT_SOURCE,
+    ETS_MB_LP_INT_SOURCE,
+    ETS_PMU_REG_0_INT_SOURCE,
+    ETS_PMU_REG_1_INT_SOURCE,
+    ETS_LP_ANAPERI_INT_SOURCE,
+    ETS_LP_ADC_INT_SOURCE,
+    ETS_LP_GPIO_INT_SOURCE,
+    ETS_LP_I2C_INT_SOURCE,
+    ETS_LP_I2S_INT_SOURCE,
+    ETS_LP_SPI_INT_SOURCE,
+    ETS_LP_TOUCH_INT_SOURCE,
+    ETS_LP_TSENS_INT_SOURCE,
+    ETS_LP_UART_INT_SOURCE,
+    ETS_LP_EFUSE_INT_SOURCE,
+    ETS_LP_SW_INT_SOURCE,
+    ETS_LP_SYSREG_INT_SOURCE,
+    ETS_LP_HUK_INT_SOURCE,
+    ETS_SYS_ICM_INT_SOURCE,
+    ETS_USB_DEVICE_INT_SOURCE,
+    ETS_SDIO_HOST_INT_SOURCE,
+    ETS_GDMA_INT_SOURCE,
+    ETS_SPI2_INT_SOURCE,
+    ETS_SPI3_INT_SOURCE,
+    ETS_I2S0_INT_SOURCE,
+    ETS_I2S1_INT_SOURCE,
+    ETS_I2S2_INT_SOURCE,
+    ETS_UHCI0_INT_SOURCE,
+    ETS_UART0_INT_SOURCE,
+    ETS_UART1_INT_SOURCE,
+    ETS_UART2_INT_SOURCE,
+    ETS_UART3_INT_SOURCE,
+    ETS_UART4_INT_SOURCE,
+    ETS_LCD_CAM_INT_SOURCE,
+    ETS_ADC_INT_SOURCE,
+    ETS_PWM0_INT_SOURCE,
+    ETS_PWM1_INT_SOURCE,
+    ETS_TWAI0_INT_SOURCE,
+    ETS_TWAI1_INT_SOURCE,
+    ETS_TWAI2_INT_SOURCE,
+    ETS_RMT_INT_SOURCE,
+    ETS_I2C0_INT_SOURCE,
+    ETS_I2C1_INT_SOURCE,
+    ETS_TIMERGRP0_T0_INT_SOURCE,
+    ETS_TIMERGRP0_T1_INT_SOURCE,
+    ETS_TIMERGRP0_WDT_INT_SOURCE,
+    ETS_TIMERGRP1_T0_INT_SOURCE,
+    ETS_TIMERGRP1_T1_INT_SOURCE,
+    ETS_TIMERGRP1_WDT_INT_SOURCE,
+    ETS_LEDC_INT_SOURCE,
+    ETS_SYSTIMER_TARGET0_INT_SOURCE,
+    ETS_SYSTIMER_TARGET1_INT_SOURCE,
+    ETS_SYSTIMER_TARGET2_INT_SOURCE,
+    ETS_AHB_PDMA_IN_CH0_INT_SOURCE,
+    ETS_AHB_PDMA_IN_CH1_INT_SOURCE,
+    ETS_AHB_PDMA_IN_CH2_INT_SOURCE,
+    ETS_AHB_PDMA_OUT_CH0_INT_SOURCE,
+    ETS_AHB_PDMA_OUT_CH1_INT_SOURCE,
+    ETS_AHB_PDMA_OUT_CH2_INT_SOURCE,
+    ETS_AXI_PDMA_IN_CH0_INT_SOURCE,
+    ETS_AXI_PDMA_IN_CH1_INT_SOURCE,
+    ETS_AXI_PDMA_IN_CH2_INT_SOURCE,
+    ETS_AXI_PDMA_OUT_CH0_INT_SOURCE,
+    ETS_AXI_PDMA_OUT_CH1_INT_SOURCE,
+    ETS_AXI_PDMA_OUT_CH2_INT_SOURCE,
+    ETS_RSA_INT_SOURCE,
+    ETS_AES_INT_SOURCE,
+    ETS_SHA_INT_SOURCE,
+    ETS_ECC_INT_SOURCE,
+    ETS_ECDSA_INT_SOURCE,
+    ETS_KM_INT_SOURCE,
+    ETS_GPIO_INT0_SOURCE,
+    ETS_GPIO_INT1_SOURCE,
+    ETS_GPIO_INT2_SOURCE,
+    ETS_GPIO_INT3_SOURCE,
+    ETS_GPIO_PAD_COMP_INT_SOURCE,
+    ETS_CPU_INT_FROM_CPU_0_SOURCE,
+    ETS_CPU_INT_FROM_CPU_1_SOURCE,
+    ETS_CPU_INT_FROM_CPU_2_SOURCE,
+    ETS_CPU_INT_FROM_CPU_3_SOURCE,
+    ETS_CACHE_INT_SOURCE,
+    ETS_FLASH_MSPI_INT_SOURCE,
+    ETS_CSI_BRIDGE_INT_SOURCE,
+    ETS_DSI_BRIDGE_INT_SOURCE,
+    ETS_CSI_INT_SOURCE,
+    ETS_DSI_INT_SOURCE,
+    ETS_GMII_PHY_INT_SOURCE,
+    ETS_LPI_INT_SOURCE,
+    ETS_PMT_INT_SOURCE,
+    ETS_SBD_INT_SOURCE,
+    ETS_USB_OTG_INT_SOURCE,
+    ETS_USB_OTG_ENDP_MULTI_PROC_INT_SOURCE,
+    ETS_JPEG_INT_SOURCE,
+    ETS_PPA_INT_SOURCE,
+    ETS_CORE0_TRACE_INT_SOURCE,
+    ETS_CORE1_TRACE_INT_SOURCE,
+    ETS_HP_CORE_CTRL_INT_SOURCE,
+    ETS_ISP_INT_SOURCE,
+    ETS_I3C_MST_INT_SOURCE,
+    ETS_I3C_SLV_INT_SOURCE,
+    ETS_USB_OTG11_INT_SOURCE,
+    ETS_DMA2D_IN_CH0_INT_SOURCE,
+    ETS_DMA2D_IN_CH1_INT_SOURCE,
+    ETS_DMA2D_OUT_CH0_INT_SOURCE,
+    ETS_DMA2D_OUT_CH1_INT_SOURCE,
+    ETS_DMA2D_OUT_CH2_INT_SOURCE,
+    ETS_PSRAM_MSPI_INT_SOURCE,
+    ETS_HP_SYSREG_INT_SOURCE,
+    ETS_PCNT_INT_SOURCE,
+    ETS_HP_PAU_INT_SOURCE,
+    ETS_HP_PARLIO_RX_INT_SOURCE,
+    ETS_HP_PARLIO_TX_INT_SOURCE,
+    ETS_H264_DMA2D_OUT_CH0_INT_SOURCE,
+    ETS_H264_DMA2D_OUT_CH1_INT_SOURCE,
+    ETS_H264_DMA2D_OUT_CH2_INT_SOURCE,
+    ETS_H264_DMA2D_OUT_CH3_INT_SOURCE,
+    ETS_H264_DMA2D_OUT_CH4_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH0_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH1_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH2_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH3_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH4_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH5_INT_SOURCE,
+    ETS_H264_REG_INT_SOURCE,
+    ETS_ASSIST_DEBUG_INT_SOURCE,
+    ETS_DMA2D_IN_CH2_INT_SOURCE,
+    ETS_DMA2D_OUT_CH3_INT_SOURCE,
+    ETS_AXI_PERF_MON_INT_SOURCE,
+    ETS_MAX_INTR_SOURCE,
+} periph_interrupt_t;
+
+extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h
new file mode 100644
index 0000000000..c651fb6e56
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h
@@ -0,0 +1,5466 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// definitions below are generated from pin_txt.csv
+#define PERIPHS_IO_MUX_U_PAD_GPIO0                   (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO0_GPIO0_0                                                 0
+#define FUNC_GPIO0_GPIO0                                                   1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO1                   (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO1_GPIO1_0                                                 0
+#define FUNC_GPIO1_GPIO1                                                   1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO2                   (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO2_MTCK                                                    0
+#define FUNC_GPIO2_GPIO2                                                   1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO3                   (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO3_MTDI                                                    0
+#define FUNC_GPIO3_GPIO3                                                   1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO4                   (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO4_MTMS                                                    0
+#define FUNC_GPIO4_GPIO4                                                   1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO5                   (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO5_MTDO                                                    0
+#define FUNC_GPIO5_GPIO5                                                   1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO6                   (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO6_GPIO6_0                                                 0
+#define FUNC_GPIO6_GPIO6                                                   1
+#define FUNC_GPIO6_SPI2_HOLD_PAD                                           3
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO7                   (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO7_GPIO7_0                                                 0
+#define FUNC_GPIO7_GPIO7                                                   1
+#define FUNC_GPIO7_SPI2_CS_PAD                                             3
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO8                   (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO8_GPIO8_0                                                 0
+#define FUNC_GPIO8_GPIO8                                                   1
+#define FUNC_GPIO8_UART0_RTS_PAD                                           2
+#define FUNC_GPIO8_SPI2_D_PAD                                              3
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO9                   (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO9_GPIO9_0                                                 0
+#define FUNC_GPIO9_GPIO9                                                   1
+#define FUNC_GPIO9_UART0_CTS_PAD                                           2
+#define FUNC_GPIO9_SPI2_CK_PAD                                             3
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO10                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO10_GPIO10_0                                               0
+#define FUNC_GPIO10_GPIO10                                                 1
+#define FUNC_GPIO10_UART1_TXD_PAD                                          2
+#define FUNC_GPIO10_SPI2_Q_PAD                                             3
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO11                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO11_GPIO11_0                                               0
+#define FUNC_GPIO11_GPIO11                                                 1
+#define FUNC_GPIO11_UART1_RXD_PAD                                          2
+#define FUNC_GPIO11_SPI2_WP_PAD                                            3
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO12                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO12_GPIO12_0                                               0
+#define FUNC_GPIO12_GPIO12                                                 1
+#define FUNC_GPIO12_UART1_RTS_PAD                                          2
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO13                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO13_GPIO13_0                                               0
+#define FUNC_GPIO13_GPIO13                                                 1
+#define FUNC_GPIO13_UART1_CTS_PAD                                          2
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO14                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO14_GPIO14_0                                               0
+#define FUNC_GPIO14_GPIO14                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO15                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO15_GPIO15_0                                               0
+#define FUNC_GPIO15_GPIO15                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO16                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO16_GPIO16_0                                               0
+#define FUNC_GPIO16_GPIO16                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO17                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO17_GPIO17_0                                               0
+#define FUNC_GPIO17_GPIO17                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO18                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO18_GPIO18_0                                               0
+#define FUNC_GPIO18_GPIO18                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO19                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO19_GPIO19_0                                               0
+#define FUNC_GPIO19_GPIO19                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO20                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO20_GPIO20_0                                               0
+#define FUNC_GPIO20_GPIO20                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO21                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO21_GPIO21_0                                               0
+#define FUNC_GPIO21_GPIO21                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO22                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO22_GPIO22_0                                               0
+#define FUNC_GPIO22_GPIO22                                                 1
+#define FUNC_GPIO22_DBG_PSRAM_CK_PAD                                       4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO23                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO23_GPIO23_0                                               0
+#define FUNC_GPIO23_GPIO23                                                 1
+#define FUNC_GPIO23_REF_50M_CLK_PAD                                        3
+#define FUNC_GPIO23_DBG_PSRAM_CS_PAD                                       4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO24                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO24_GPIO24_0                                               0
+#define FUNC_GPIO24_GPIO24                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO25                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO25_GPIO25_0                                               0
+#define FUNC_GPIO25_GPIO25                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO26                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO26_GPIO26_0                                               0
+#define FUNC_GPIO26_GPIO26                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO27                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO27_GPIO27_0                                               0
+#define FUNC_GPIO27_GPIO27                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO28                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO28_GPIO28_0                                               0
+#define FUNC_GPIO28_GPIO28                                                 1
+#define FUNC_GPIO28_SPI2_CS_PAD                                            2
+#define FUNC_GPIO28_GMAC_PHY_RXDV_PAD                                      3
+#define FUNC_GPIO28_DBG_PSRAM_D_PAD                                        4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO29                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO29_GPIO29_0                                               0
+#define FUNC_GPIO29_GPIO29                                                 1
+#define FUNC_GPIO29_SPI2_D_PAD                                             2
+#define FUNC_GPIO29_GMAC_PHY_RXD0_PAD                                      3
+#define FUNC_GPIO29_DBG_PSRAM_Q_PAD                                        4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO30                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO30_GPIO30_0                                               0
+#define FUNC_GPIO30_GPIO30                                                 1
+#define FUNC_GPIO30_SPI2_CK_PAD                                            2
+#define FUNC_GPIO30_GMAC_PHY_RXD1_PAD                                      3
+#define FUNC_GPIO30_DBG_PSRAM_WP_PAD                                       4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO31                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO31_GPIO31_0                                               0
+#define FUNC_GPIO31_GPIO31                                                 1
+#define FUNC_GPIO31_SPI2_Q_PAD                                             2
+#define FUNC_GPIO31_GMAC_PHY_RXER_PAD                                      3
+#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD                                     4
+
+// Strapping: Diag Group Sel1
+#define PERIPHS_IO_MUX_U_PAD_GPIO32                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO32_GPIO32_0                                               0
+#define FUNC_GPIO32_GPIO32                                                 1
+#define FUNC_GPIO32_SPI2_HOLD_PAD                                          2
+#define FUNC_GPIO32_GMAC_RMII_CLK_PAD                                      3
+#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD                                      4
+
+// Strapping: Diag Group Sel0
+#define PERIPHS_IO_MUX_U_PAD_GPIO33                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO33_GPIO33_0                                               0
+#define FUNC_GPIO33_GPIO33                                                 1
+#define FUNC_GPIO33_SPI2_WP_PAD                                            2
+#define FUNC_GPIO33_GMAC_PHY_TXEN_PAD                                      3
+#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD                                      4
+
+// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag
+#define PERIPHS_IO_MUX_U_PAD_GPIO34                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO34_GPIO34_0                                               0
+#define FUNC_GPIO34_GPIO34                                                 1
+#define FUNC_GPIO34_SPI2_IO4_PAD                                           2
+#define FUNC_GPIO34_GMAC_PHY_TXD0_PAD                                      3
+#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD                                      4
+
+// Strapping: Boot Mode select 3
+#define PERIPHS_IO_MUX_U_PAD_GPIO35                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO35_GPIO35_0                                               0
+#define FUNC_GPIO35_GPIO35                                                 1
+#define FUNC_GPIO35_SPI2_IO5_PAD                                           2
+#define FUNC_GPIO35_GMAC_PHY_TXD1_PAD                                      3
+#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD                                      4
+
+// Strapping: Boot Mode select 2
+#define PERIPHS_IO_MUX_U_PAD_GPIO36                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO36_GPIO36_0                                               0
+#define FUNC_GPIO36_GPIO36                                                 1
+#define FUNC_GPIO36_SPI2_IO6_PAD                                           2
+#define FUNC_GPIO36_GMAC_PHY_TXER_PAD                                      3
+#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD                                    4
+
+// Strapping: Boot Mode select 1
+#define PERIPHS_IO_MUX_U_PAD_GPIO37                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO37_UART0_TXD_PAD                                          0
+#define FUNC_GPIO37_GPIO37                                                 1
+#define FUNC_GPIO37_SPI2_IO7_PAD                                           2
+
+// Strapping: Boot Mode select 0
+#define PERIPHS_IO_MUX_U_PAD_GPIO38                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO38_UART0_RXD_PAD                                          0
+#define FUNC_GPIO38_GPIO38                                                 1
+#define FUNC_GPIO38_SPI2_DQS_PAD                                           2
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO39                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO39_SD1_CDATA0_PAD                                         0
+#define FUNC_GPIO39_GPIO39                                                 1
+#define FUNC_GPIO39_BIST_PAD                                               2
+#define FUNC_GPIO39_REF_50M_CLK_PAD                                        3
+#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD                                      4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO40                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO40_SD1_CDATA1_PAD                                         0
+#define FUNC_GPIO40_GPIO40                                                 1
+#define FUNC_GPIO40_BIST_PAD                                               2
+#define FUNC_GPIO40_GMAC_PHY_TXEN_PAD                                      3
+#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD                                      4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO41                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO41_SD1_CDATA2_PAD                                         0
+#define FUNC_GPIO41_GPIO41                                                 1
+#define FUNC_GPIO41_BIST_PAD                                               2
+#define FUNC_GPIO41_GMAC_PHY_TXD0_PAD                                      3
+#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD                                     4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO42                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO42_SD1_CDATA3_PAD                                         0
+#define FUNC_GPIO42_GPIO42                                                 1
+#define FUNC_GPIO42_BIST_PAD                                               2
+#define FUNC_GPIO42_GMAC_PHY_TXD1_PAD                                      3
+#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD                                     4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO43                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO43_SD1_CCLK_PAD                                           0
+#define FUNC_GPIO43_GPIO43                                                 1
+#define FUNC_GPIO43_BIST_PAD                                               2
+#define FUNC_GPIO43_GMAC_PHY_TXER_PAD                                      3
+#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD                                     4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO44                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO44_SD1_CCMD_PAD                                           0
+#define FUNC_GPIO44_GPIO44                                                 1
+#define FUNC_GPIO44_BIST_PAD                                               2
+#define FUNC_GPIO44_GMAC_RMII_CLK_PAD                                      3
+#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD                                     4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO45                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO45_SD1_CDATA4_PAD                                         0
+#define FUNC_GPIO45_GPIO45                                                 1
+#define FUNC_GPIO45_BIST_PAD                                               2
+#define FUNC_GPIO45_GMAC_PHY_RXDV_PAD                                      3
+#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD                                     4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO46                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO46_SD1_CDATA5_PAD                                         0
+#define FUNC_GPIO46_GPIO46                                                 1
+#define FUNC_GPIO46_BIST_PAD                                               2
+#define FUNC_GPIO46_GMAC_PHY_RXD0_PAD                                      3
+#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD                                     4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO47                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO47_SD1_CDATA6_PAD                                         0
+#define FUNC_GPIO47_GPIO47                                                 1
+#define FUNC_GPIO47_BIST_PAD                                               2
+#define FUNC_GPIO47_GMAC_PHY_RXD1_PAD                                      3
+#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD                                    4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO48                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO48_SD1_CDATA7_PAD                                         0
+#define FUNC_GPIO48_GPIO48                                                 1
+#define FUNC_GPIO48_BIST_PAD                                               2
+#define FUNC_GPIO48_GMAC_PHY_RXER_PAD                                      3
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO49                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO49_GPIO49_0                                               0
+#define FUNC_GPIO49_GPIO49                                                 1
+#define FUNC_GPIO49_GMAC_PHY_TXEN_PAD                                      3
+#define FUNC_GPIO49_DBG_FLASH_CS_PAD                                       4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO50                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO50_GPIO50_0                                               0
+#define FUNC_GPIO50_GPIO50                                                 1
+#define FUNC_GPIO50_GMAC_RMII_CLK_PAD                                      3
+#define FUNC_GPIO50_DBG_FLASH_Q_PAD                                        4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO51                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO51_GPIO51_0                                               0
+#define FUNC_GPIO51_GPIO51                                                 1
+#define FUNC_GPIO51_GMAC_PHY_RXDV_PAD                                      3
+#define FUNC_GPIO51_DBG_FLASH_WP_PAD                                       4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO52                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO52_GPIO52_0                                               0
+#define FUNC_GPIO52_GPIO52                                                 1
+#define FUNC_GPIO52_GMAC_PHY_RXD0_PAD                                      3
+#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD                                     4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO53                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO53_GPIO53_0                                               0
+#define FUNC_GPIO53_GPIO53                                                 1
+#define FUNC_GPIO53_GMAC_PHY_RXD1_PAD                                      3
+#define FUNC_GPIO53_DBG_FLASH_CK_PAD                                       4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO54                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO54_GPIO54_0                                               0
+#define FUNC_GPIO54_GPIO54                                                 1
+#define FUNC_GPIO54_GMAC_PHY_RXER_PAD                                      3
+#define FUNC_GPIO54_DBG_FLASH_D_PAD                                        4
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO55                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO55_GPIO55_0                                               0
+#define FUNC_GPIO55_GPIO55                                                 1
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO56                  (REG_IO_MUX_BASE + 0x0)
+#define FUNC_GPIO56_GPIO56_0                                               0
+#define FUNC_GPIO56_GPIO56                                                 1
+
+
+/** IO_MUX_gpio0_REG register
+ *  iomux control register for gpio0
+ */
+#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x4)
+/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO0_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO0_MCU_OE_M  (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S)
+#define IO_MUX_GPIO0_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO0_MCU_OE_S  0
+/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO0_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO0_SLP_SEL_M  (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S)
+#define IO_MUX_GPIO0_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO0_SLP_SEL_S  1
+/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO0_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO0_MCU_WPD_M  (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S)
+#define IO_MUX_GPIO0_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO0_MCU_WPD_S  2
+/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO0_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO0_MCU_WPU_M  (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S)
+#define IO_MUX_GPIO0_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO0_MCU_WPU_S  3
+/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO0_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO0_MCU_IE_M  (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S)
+#define IO_MUX_GPIO0_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO0_MCU_IE_S  4
+/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO0_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO0_MCU_DRV_M  (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S)
+#define IO_MUX_GPIO0_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO0_MCU_DRV_S  5
+/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO0_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO0_FUN_WPD_M  (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S)
+#define IO_MUX_GPIO0_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO0_FUN_WPD_S  7
+/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO0_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO0_FUN_WPU_M  (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S)
+#define IO_MUX_GPIO0_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO0_FUN_WPU_S  8
+/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO0_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO0_FUN_IE_M  (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S)
+#define IO_MUX_GPIO0_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO0_FUN_IE_S  9
+/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO0_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO0_FUN_DRV_M  (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S)
+#define IO_MUX_GPIO0_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO0_FUN_DRV_S  10
+/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO0_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO0_MCU_SEL_M  (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S)
+#define IO_MUX_GPIO0_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO0_MCU_SEL_S  12
+/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO0_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO0_FILTER_EN_M  (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S)
+#define IO_MUX_GPIO0_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO0_FILTER_EN_S  15
+
+/** IO_MUX_gpio1_REG register
+ *  iomux control register for gpio1
+ */
+#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x8)
+/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO1_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO1_MCU_OE_M  (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S)
+#define IO_MUX_GPIO1_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO1_MCU_OE_S  0
+/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO1_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO1_SLP_SEL_M  (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S)
+#define IO_MUX_GPIO1_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO1_SLP_SEL_S  1
+/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO1_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO1_MCU_WPD_M  (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S)
+#define IO_MUX_GPIO1_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO1_MCU_WPD_S  2
+/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO1_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO1_MCU_WPU_M  (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S)
+#define IO_MUX_GPIO1_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO1_MCU_WPU_S  3
+/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO1_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO1_MCU_IE_M  (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S)
+#define IO_MUX_GPIO1_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO1_MCU_IE_S  4
+/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO1_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO1_MCU_DRV_M  (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S)
+#define IO_MUX_GPIO1_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO1_MCU_DRV_S  5
+/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO1_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO1_FUN_WPD_M  (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S)
+#define IO_MUX_GPIO1_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO1_FUN_WPD_S  7
+/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO1_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO1_FUN_WPU_M  (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S)
+#define IO_MUX_GPIO1_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO1_FUN_WPU_S  8
+/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO1_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO1_FUN_IE_M  (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S)
+#define IO_MUX_GPIO1_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO1_FUN_IE_S  9
+/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO1_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO1_FUN_DRV_M  (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S)
+#define IO_MUX_GPIO1_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO1_FUN_DRV_S  10
+/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO1_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO1_MCU_SEL_M  (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S)
+#define IO_MUX_GPIO1_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO1_MCU_SEL_S  12
+/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO1_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO1_FILTER_EN_M  (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S)
+#define IO_MUX_GPIO1_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO1_FILTER_EN_S  15
+
+/** IO_MUX_gpio2_REG register
+ *  iomux control register for gpio2
+ */
+#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0xc)
+/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO2_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO2_MCU_OE_M  (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S)
+#define IO_MUX_GPIO2_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO2_MCU_OE_S  0
+/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO2_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO2_SLP_SEL_M  (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S)
+#define IO_MUX_GPIO2_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO2_SLP_SEL_S  1
+/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO2_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO2_MCU_WPD_M  (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S)
+#define IO_MUX_GPIO2_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO2_MCU_WPD_S  2
+/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO2_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO2_MCU_WPU_M  (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S)
+#define IO_MUX_GPIO2_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO2_MCU_WPU_S  3
+/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO2_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO2_MCU_IE_M  (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S)
+#define IO_MUX_GPIO2_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO2_MCU_IE_S  4
+/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO2_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO2_MCU_DRV_M  (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S)
+#define IO_MUX_GPIO2_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO2_MCU_DRV_S  5
+/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO2_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO2_FUN_WPD_M  (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S)
+#define IO_MUX_GPIO2_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO2_FUN_WPD_S  7
+/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO2_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO2_FUN_WPU_M  (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S)
+#define IO_MUX_GPIO2_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO2_FUN_WPU_S  8
+/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO2_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO2_FUN_IE_M  (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S)
+#define IO_MUX_GPIO2_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO2_FUN_IE_S  9
+/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO2_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO2_FUN_DRV_M  (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S)
+#define IO_MUX_GPIO2_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO2_FUN_DRV_S  10
+/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO2_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO2_MCU_SEL_M  (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S)
+#define IO_MUX_GPIO2_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO2_MCU_SEL_S  12
+/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO2_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO2_FILTER_EN_M  (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S)
+#define IO_MUX_GPIO2_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO2_FILTER_EN_S  15
+
+/** IO_MUX_gpio3_REG register
+ *  iomux control register for gpio3
+ */
+#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0x10)
+/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO3_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO3_MCU_OE_M  (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S)
+#define IO_MUX_GPIO3_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO3_MCU_OE_S  0
+/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO3_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO3_SLP_SEL_M  (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S)
+#define IO_MUX_GPIO3_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO3_SLP_SEL_S  1
+/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO3_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO3_MCU_WPD_M  (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S)
+#define IO_MUX_GPIO3_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO3_MCU_WPD_S  2
+/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO3_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO3_MCU_WPU_M  (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S)
+#define IO_MUX_GPIO3_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO3_MCU_WPU_S  3
+/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO3_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO3_MCU_IE_M  (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S)
+#define IO_MUX_GPIO3_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO3_MCU_IE_S  4
+/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO3_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO3_MCU_DRV_M  (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S)
+#define IO_MUX_GPIO3_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO3_MCU_DRV_S  5
+/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO3_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO3_FUN_WPD_M  (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S)
+#define IO_MUX_GPIO3_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO3_FUN_WPD_S  7
+/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO3_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO3_FUN_WPU_M  (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S)
+#define IO_MUX_GPIO3_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO3_FUN_WPU_S  8
+/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO3_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO3_FUN_IE_M  (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S)
+#define IO_MUX_GPIO3_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO3_FUN_IE_S  9
+/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO3_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO3_FUN_DRV_M  (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S)
+#define IO_MUX_GPIO3_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO3_FUN_DRV_S  10
+/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO3_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO3_MCU_SEL_M  (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S)
+#define IO_MUX_GPIO3_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO3_MCU_SEL_S  12
+/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO3_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO3_FILTER_EN_M  (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S)
+#define IO_MUX_GPIO3_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO3_FILTER_EN_S  15
+
+/** IO_MUX_gpio4_REG register
+ *  iomux control register for gpio4
+ */
+#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x14)
+/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO4_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO4_MCU_OE_M  (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S)
+#define IO_MUX_GPIO4_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO4_MCU_OE_S  0
+/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO4_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO4_SLP_SEL_M  (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S)
+#define IO_MUX_GPIO4_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO4_SLP_SEL_S  1
+/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO4_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO4_MCU_WPD_M  (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S)
+#define IO_MUX_GPIO4_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO4_MCU_WPD_S  2
+/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO4_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO4_MCU_WPU_M  (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S)
+#define IO_MUX_GPIO4_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO4_MCU_WPU_S  3
+/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO4_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO4_MCU_IE_M  (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S)
+#define IO_MUX_GPIO4_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO4_MCU_IE_S  4
+/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO4_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO4_MCU_DRV_M  (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S)
+#define IO_MUX_GPIO4_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO4_MCU_DRV_S  5
+/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO4_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO4_FUN_WPD_M  (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S)
+#define IO_MUX_GPIO4_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO4_FUN_WPD_S  7
+/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO4_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO4_FUN_WPU_M  (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S)
+#define IO_MUX_GPIO4_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO4_FUN_WPU_S  8
+/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO4_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO4_FUN_IE_M  (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S)
+#define IO_MUX_GPIO4_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO4_FUN_IE_S  9
+/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO4_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO4_FUN_DRV_M  (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S)
+#define IO_MUX_GPIO4_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO4_FUN_DRV_S  10
+/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO4_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO4_MCU_SEL_M  (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S)
+#define IO_MUX_GPIO4_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO4_MCU_SEL_S  12
+/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO4_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO4_FILTER_EN_M  (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S)
+#define IO_MUX_GPIO4_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO4_FILTER_EN_S  15
+
+/** IO_MUX_gpio5_REG register
+ *  iomux control register for gpio5
+ */
+#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x18)
+/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO5_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO5_MCU_OE_M  (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S)
+#define IO_MUX_GPIO5_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO5_MCU_OE_S  0
+/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO5_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO5_SLP_SEL_M  (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S)
+#define IO_MUX_GPIO5_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO5_SLP_SEL_S  1
+/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO5_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO5_MCU_WPD_M  (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S)
+#define IO_MUX_GPIO5_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO5_MCU_WPD_S  2
+/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO5_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO5_MCU_WPU_M  (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S)
+#define IO_MUX_GPIO5_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO5_MCU_WPU_S  3
+/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO5_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO5_MCU_IE_M  (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S)
+#define IO_MUX_GPIO5_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO5_MCU_IE_S  4
+/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO5_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO5_MCU_DRV_M  (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S)
+#define IO_MUX_GPIO5_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO5_MCU_DRV_S  5
+/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO5_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO5_FUN_WPD_M  (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S)
+#define IO_MUX_GPIO5_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO5_FUN_WPD_S  7
+/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO5_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO5_FUN_WPU_M  (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S)
+#define IO_MUX_GPIO5_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO5_FUN_WPU_S  8
+/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO5_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO5_FUN_IE_M  (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S)
+#define IO_MUX_GPIO5_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO5_FUN_IE_S  9
+/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO5_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO5_FUN_DRV_M  (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S)
+#define IO_MUX_GPIO5_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO5_FUN_DRV_S  10
+/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO5_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO5_MCU_SEL_M  (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S)
+#define IO_MUX_GPIO5_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO5_MCU_SEL_S  12
+/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO5_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO5_FILTER_EN_M  (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S)
+#define IO_MUX_GPIO5_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO5_FILTER_EN_S  15
+
+/** IO_MUX_gpio6_REG register
+ *  iomux control register for gpio6
+ */
+#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x1c)
+/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO6_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO6_MCU_OE_M  (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S)
+#define IO_MUX_GPIO6_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO6_MCU_OE_S  0
+/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO6_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO6_SLP_SEL_M  (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S)
+#define IO_MUX_GPIO6_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO6_SLP_SEL_S  1
+/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO6_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO6_MCU_WPD_M  (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S)
+#define IO_MUX_GPIO6_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO6_MCU_WPD_S  2
+/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO6_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO6_MCU_WPU_M  (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S)
+#define IO_MUX_GPIO6_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO6_MCU_WPU_S  3
+/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO6_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO6_MCU_IE_M  (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S)
+#define IO_MUX_GPIO6_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO6_MCU_IE_S  4
+/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO6_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO6_MCU_DRV_M  (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S)
+#define IO_MUX_GPIO6_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO6_MCU_DRV_S  5
+/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO6_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO6_FUN_WPD_M  (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S)
+#define IO_MUX_GPIO6_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO6_FUN_WPD_S  7
+/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO6_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO6_FUN_WPU_M  (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S)
+#define IO_MUX_GPIO6_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO6_FUN_WPU_S  8
+/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO6_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO6_FUN_IE_M  (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S)
+#define IO_MUX_GPIO6_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO6_FUN_IE_S  9
+/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO6_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO6_FUN_DRV_M  (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S)
+#define IO_MUX_GPIO6_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO6_FUN_DRV_S  10
+/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO6_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO6_MCU_SEL_M  (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S)
+#define IO_MUX_GPIO6_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO6_MCU_SEL_S  12
+/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO6_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO6_FILTER_EN_M  (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S)
+#define IO_MUX_GPIO6_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO6_FILTER_EN_S  15
+
+/** IO_MUX_gpio7_REG register
+ *  iomux control register for gpio7
+ */
+#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x20)
+/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO7_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO7_MCU_OE_M  (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S)
+#define IO_MUX_GPIO7_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO7_MCU_OE_S  0
+/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO7_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO7_SLP_SEL_M  (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S)
+#define IO_MUX_GPIO7_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO7_SLP_SEL_S  1
+/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO7_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO7_MCU_WPD_M  (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S)
+#define IO_MUX_GPIO7_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO7_MCU_WPD_S  2
+/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO7_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO7_MCU_WPU_M  (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S)
+#define IO_MUX_GPIO7_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO7_MCU_WPU_S  3
+/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO7_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO7_MCU_IE_M  (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S)
+#define IO_MUX_GPIO7_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO7_MCU_IE_S  4
+/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO7_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO7_MCU_DRV_M  (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S)
+#define IO_MUX_GPIO7_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO7_MCU_DRV_S  5
+/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO7_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO7_FUN_WPD_M  (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S)
+#define IO_MUX_GPIO7_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO7_FUN_WPD_S  7
+/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO7_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO7_FUN_WPU_M  (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S)
+#define IO_MUX_GPIO7_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO7_FUN_WPU_S  8
+/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO7_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO7_FUN_IE_M  (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S)
+#define IO_MUX_GPIO7_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO7_FUN_IE_S  9
+/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO7_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO7_FUN_DRV_M  (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S)
+#define IO_MUX_GPIO7_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO7_FUN_DRV_S  10
+/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO7_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO7_MCU_SEL_M  (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S)
+#define IO_MUX_GPIO7_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO7_MCU_SEL_S  12
+/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO7_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO7_FILTER_EN_M  (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S)
+#define IO_MUX_GPIO7_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO7_FILTER_EN_S  15
+
+/** IO_MUX_gpio8_REG register
+ *  iomux control register for gpio8
+ */
+#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x24)
+/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO8_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO8_MCU_OE_M  (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S)
+#define IO_MUX_GPIO8_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO8_MCU_OE_S  0
+/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO8_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO8_SLP_SEL_M  (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S)
+#define IO_MUX_GPIO8_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO8_SLP_SEL_S  1
+/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO8_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO8_MCU_WPD_M  (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S)
+#define IO_MUX_GPIO8_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO8_MCU_WPD_S  2
+/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO8_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO8_MCU_WPU_M  (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S)
+#define IO_MUX_GPIO8_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO8_MCU_WPU_S  3
+/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO8_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO8_MCU_IE_M  (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S)
+#define IO_MUX_GPIO8_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO8_MCU_IE_S  4
+/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO8_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO8_MCU_DRV_M  (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S)
+#define IO_MUX_GPIO8_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO8_MCU_DRV_S  5
+/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO8_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO8_FUN_WPD_M  (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S)
+#define IO_MUX_GPIO8_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO8_FUN_WPD_S  7
+/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO8_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO8_FUN_WPU_M  (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S)
+#define IO_MUX_GPIO8_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO8_FUN_WPU_S  8
+/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO8_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO8_FUN_IE_M  (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S)
+#define IO_MUX_GPIO8_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO8_FUN_IE_S  9
+/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO8_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO8_FUN_DRV_M  (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S)
+#define IO_MUX_GPIO8_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO8_FUN_DRV_S  10
+/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO8_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO8_MCU_SEL_M  (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S)
+#define IO_MUX_GPIO8_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO8_MCU_SEL_S  12
+/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO8_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO8_FILTER_EN_M  (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S)
+#define IO_MUX_GPIO8_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO8_FILTER_EN_S  15
+
+/** IO_MUX_gpio9_REG register
+ *  iomux control register for gpio9
+ */
+#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x28)
+/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO9_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO9_MCU_OE_M  (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S)
+#define IO_MUX_GPIO9_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO9_MCU_OE_S  0
+/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO9_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO9_SLP_SEL_M  (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S)
+#define IO_MUX_GPIO9_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO9_SLP_SEL_S  1
+/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO9_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO9_MCU_WPD_M  (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S)
+#define IO_MUX_GPIO9_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO9_MCU_WPD_S  2
+/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO9_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO9_MCU_WPU_M  (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S)
+#define IO_MUX_GPIO9_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO9_MCU_WPU_S  3
+/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO9_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO9_MCU_IE_M  (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S)
+#define IO_MUX_GPIO9_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO9_MCU_IE_S  4
+/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO9_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO9_MCU_DRV_M  (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S)
+#define IO_MUX_GPIO9_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO9_MCU_DRV_S  5
+/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO9_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO9_FUN_WPD_M  (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S)
+#define IO_MUX_GPIO9_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO9_FUN_WPD_S  7
+/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO9_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO9_FUN_WPU_M  (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S)
+#define IO_MUX_GPIO9_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO9_FUN_WPU_S  8
+/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO9_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO9_FUN_IE_M  (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S)
+#define IO_MUX_GPIO9_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO9_FUN_IE_S  9
+/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO9_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO9_FUN_DRV_M  (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S)
+#define IO_MUX_GPIO9_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO9_FUN_DRV_S  10
+/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO9_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO9_MCU_SEL_M  (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S)
+#define IO_MUX_GPIO9_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO9_MCU_SEL_S  12
+/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO9_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO9_FILTER_EN_M  (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S)
+#define IO_MUX_GPIO9_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO9_FILTER_EN_S  15
+
+/** IO_MUX_gpio10_REG register
+ *  iomux control register for gpio10
+ */
+#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x2c)
+/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO10_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO10_MCU_OE_M  (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S)
+#define IO_MUX_GPIO10_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO10_MCU_OE_S  0
+/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO10_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO10_SLP_SEL_M  (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S)
+#define IO_MUX_GPIO10_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO10_SLP_SEL_S  1
+/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO10_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO10_MCU_WPD_M  (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S)
+#define IO_MUX_GPIO10_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO10_MCU_WPD_S  2
+/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO10_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO10_MCU_WPU_M  (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S)
+#define IO_MUX_GPIO10_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO10_MCU_WPU_S  3
+/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO10_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO10_MCU_IE_M  (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S)
+#define IO_MUX_GPIO10_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO10_MCU_IE_S  4
+/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO10_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO10_MCU_DRV_M  (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S)
+#define IO_MUX_GPIO10_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO10_MCU_DRV_S  5
+/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO10_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO10_FUN_WPD_M  (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S)
+#define IO_MUX_GPIO10_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO10_FUN_WPD_S  7
+/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO10_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO10_FUN_WPU_M  (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S)
+#define IO_MUX_GPIO10_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO10_FUN_WPU_S  8
+/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO10_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO10_FUN_IE_M  (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S)
+#define IO_MUX_GPIO10_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO10_FUN_IE_S  9
+/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO10_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO10_FUN_DRV_M  (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S)
+#define IO_MUX_GPIO10_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO10_FUN_DRV_S  10
+/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO10_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO10_MCU_SEL_M  (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S)
+#define IO_MUX_GPIO10_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO10_MCU_SEL_S  12
+/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO10_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO10_FILTER_EN_M  (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S)
+#define IO_MUX_GPIO10_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO10_FILTER_EN_S  15
+
+/** IO_MUX_gpio11_REG register
+ *  iomux control register for gpio11
+ */
+#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x30)
+/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO11_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO11_MCU_OE_M  (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S)
+#define IO_MUX_GPIO11_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO11_MCU_OE_S  0
+/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO11_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO11_SLP_SEL_M  (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S)
+#define IO_MUX_GPIO11_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO11_SLP_SEL_S  1
+/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO11_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO11_MCU_WPD_M  (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S)
+#define IO_MUX_GPIO11_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO11_MCU_WPD_S  2
+/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO11_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO11_MCU_WPU_M  (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S)
+#define IO_MUX_GPIO11_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO11_MCU_WPU_S  3
+/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO11_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO11_MCU_IE_M  (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S)
+#define IO_MUX_GPIO11_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO11_MCU_IE_S  4
+/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO11_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO11_MCU_DRV_M  (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S)
+#define IO_MUX_GPIO11_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO11_MCU_DRV_S  5
+/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO11_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO11_FUN_WPD_M  (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S)
+#define IO_MUX_GPIO11_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO11_FUN_WPD_S  7
+/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO11_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO11_FUN_WPU_M  (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S)
+#define IO_MUX_GPIO11_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO11_FUN_WPU_S  8
+/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO11_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO11_FUN_IE_M  (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S)
+#define IO_MUX_GPIO11_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO11_FUN_IE_S  9
+/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO11_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO11_FUN_DRV_M  (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S)
+#define IO_MUX_GPIO11_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO11_FUN_DRV_S  10
+/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO11_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO11_MCU_SEL_M  (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S)
+#define IO_MUX_GPIO11_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO11_MCU_SEL_S  12
+/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO11_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO11_FILTER_EN_M  (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S)
+#define IO_MUX_GPIO11_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO11_FILTER_EN_S  15
+
+/** IO_MUX_gpio12_REG register
+ *  iomux control register for gpio12
+ */
+#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x34)
+/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO12_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO12_MCU_OE_M  (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S)
+#define IO_MUX_GPIO12_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO12_MCU_OE_S  0
+/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO12_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO12_SLP_SEL_M  (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S)
+#define IO_MUX_GPIO12_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO12_SLP_SEL_S  1
+/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO12_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO12_MCU_WPD_M  (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S)
+#define IO_MUX_GPIO12_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO12_MCU_WPD_S  2
+/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO12_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO12_MCU_WPU_M  (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S)
+#define IO_MUX_GPIO12_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO12_MCU_WPU_S  3
+/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO12_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO12_MCU_IE_M  (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S)
+#define IO_MUX_GPIO12_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO12_MCU_IE_S  4
+/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO12_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO12_MCU_DRV_M  (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S)
+#define IO_MUX_GPIO12_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO12_MCU_DRV_S  5
+/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO12_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO12_FUN_WPD_M  (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S)
+#define IO_MUX_GPIO12_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO12_FUN_WPD_S  7
+/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO12_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO12_FUN_WPU_M  (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S)
+#define IO_MUX_GPIO12_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO12_FUN_WPU_S  8
+/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO12_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO12_FUN_IE_M  (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S)
+#define IO_MUX_GPIO12_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO12_FUN_IE_S  9
+/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO12_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO12_FUN_DRV_M  (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S)
+#define IO_MUX_GPIO12_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO12_FUN_DRV_S  10
+/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO12_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO12_MCU_SEL_M  (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S)
+#define IO_MUX_GPIO12_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO12_MCU_SEL_S  12
+/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO12_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO12_FILTER_EN_M  (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S)
+#define IO_MUX_GPIO12_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO12_FILTER_EN_S  15
+
+/** IO_MUX_gpio13_REG register
+ *  iomux control register for gpio13
+ */
+#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x38)
+/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO13_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO13_MCU_OE_M  (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S)
+#define IO_MUX_GPIO13_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO13_MCU_OE_S  0
+/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO13_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO13_SLP_SEL_M  (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S)
+#define IO_MUX_GPIO13_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO13_SLP_SEL_S  1
+/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO13_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO13_MCU_WPD_M  (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S)
+#define IO_MUX_GPIO13_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO13_MCU_WPD_S  2
+/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO13_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO13_MCU_WPU_M  (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S)
+#define IO_MUX_GPIO13_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO13_MCU_WPU_S  3
+/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO13_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO13_MCU_IE_M  (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S)
+#define IO_MUX_GPIO13_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO13_MCU_IE_S  4
+/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO13_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO13_MCU_DRV_M  (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S)
+#define IO_MUX_GPIO13_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO13_MCU_DRV_S  5
+/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO13_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO13_FUN_WPD_M  (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S)
+#define IO_MUX_GPIO13_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO13_FUN_WPD_S  7
+/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO13_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO13_FUN_WPU_M  (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S)
+#define IO_MUX_GPIO13_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO13_FUN_WPU_S  8
+/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO13_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO13_FUN_IE_M  (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S)
+#define IO_MUX_GPIO13_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO13_FUN_IE_S  9
+/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO13_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO13_FUN_DRV_M  (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S)
+#define IO_MUX_GPIO13_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO13_FUN_DRV_S  10
+/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO13_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO13_MCU_SEL_M  (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S)
+#define IO_MUX_GPIO13_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO13_MCU_SEL_S  12
+/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO13_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO13_FILTER_EN_M  (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S)
+#define IO_MUX_GPIO13_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO13_FILTER_EN_S  15
+
+/** IO_MUX_gpio14_REG register
+ *  iomux control register for gpio14
+ */
+#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x3c)
+/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO14_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO14_MCU_OE_M  (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S)
+#define IO_MUX_GPIO14_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO14_MCU_OE_S  0
+/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO14_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO14_SLP_SEL_M  (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S)
+#define IO_MUX_GPIO14_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO14_SLP_SEL_S  1
+/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO14_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO14_MCU_WPD_M  (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S)
+#define IO_MUX_GPIO14_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO14_MCU_WPD_S  2
+/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO14_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO14_MCU_WPU_M  (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S)
+#define IO_MUX_GPIO14_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO14_MCU_WPU_S  3
+/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO14_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO14_MCU_IE_M  (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S)
+#define IO_MUX_GPIO14_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO14_MCU_IE_S  4
+/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO14_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO14_MCU_DRV_M  (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S)
+#define IO_MUX_GPIO14_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO14_MCU_DRV_S  5
+/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO14_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO14_FUN_WPD_M  (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S)
+#define IO_MUX_GPIO14_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO14_FUN_WPD_S  7
+/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO14_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO14_FUN_WPU_M  (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S)
+#define IO_MUX_GPIO14_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO14_FUN_WPU_S  8
+/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO14_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO14_FUN_IE_M  (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S)
+#define IO_MUX_GPIO14_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO14_FUN_IE_S  9
+/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO14_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO14_FUN_DRV_M  (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S)
+#define IO_MUX_GPIO14_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO14_FUN_DRV_S  10
+/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO14_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO14_MCU_SEL_M  (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S)
+#define IO_MUX_GPIO14_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO14_MCU_SEL_S  12
+/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO14_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO14_FILTER_EN_M  (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S)
+#define IO_MUX_GPIO14_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO14_FILTER_EN_S  15
+
+/** IO_MUX_gpio15_REG register
+ *  iomux control register for gpio15
+ */
+#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x40)
+/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO15_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO15_MCU_OE_M  (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S)
+#define IO_MUX_GPIO15_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO15_MCU_OE_S  0
+/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO15_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO15_SLP_SEL_M  (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S)
+#define IO_MUX_GPIO15_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO15_SLP_SEL_S  1
+/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO15_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO15_MCU_WPD_M  (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S)
+#define IO_MUX_GPIO15_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO15_MCU_WPD_S  2
+/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO15_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO15_MCU_WPU_M  (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S)
+#define IO_MUX_GPIO15_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO15_MCU_WPU_S  3
+/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO15_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO15_MCU_IE_M  (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S)
+#define IO_MUX_GPIO15_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO15_MCU_IE_S  4
+/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO15_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO15_MCU_DRV_M  (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S)
+#define IO_MUX_GPIO15_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO15_MCU_DRV_S  5
+/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO15_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO15_FUN_WPD_M  (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S)
+#define IO_MUX_GPIO15_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO15_FUN_WPD_S  7
+/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO15_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO15_FUN_WPU_M  (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S)
+#define IO_MUX_GPIO15_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO15_FUN_WPU_S  8
+/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO15_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO15_FUN_IE_M  (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S)
+#define IO_MUX_GPIO15_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO15_FUN_IE_S  9
+/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO15_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO15_FUN_DRV_M  (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S)
+#define IO_MUX_GPIO15_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO15_FUN_DRV_S  10
+/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO15_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO15_MCU_SEL_M  (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S)
+#define IO_MUX_GPIO15_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO15_MCU_SEL_S  12
+/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO15_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO15_FILTER_EN_M  (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S)
+#define IO_MUX_GPIO15_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO15_FILTER_EN_S  15
+
+/** IO_MUX_gpio16_REG register
+ *  iomux control register for gpio16
+ */
+#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x44)
+/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO16_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO16_MCU_OE_M  (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S)
+#define IO_MUX_GPIO16_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO16_MCU_OE_S  0
+/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO16_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO16_SLP_SEL_M  (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S)
+#define IO_MUX_GPIO16_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO16_SLP_SEL_S  1
+/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO16_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO16_MCU_WPD_M  (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S)
+#define IO_MUX_GPIO16_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO16_MCU_WPD_S  2
+/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO16_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO16_MCU_WPU_M  (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S)
+#define IO_MUX_GPIO16_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO16_MCU_WPU_S  3
+/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO16_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO16_MCU_IE_M  (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S)
+#define IO_MUX_GPIO16_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO16_MCU_IE_S  4
+/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO16_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO16_MCU_DRV_M  (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S)
+#define IO_MUX_GPIO16_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO16_MCU_DRV_S  5
+/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO16_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO16_FUN_WPD_M  (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S)
+#define IO_MUX_GPIO16_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO16_FUN_WPD_S  7
+/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO16_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO16_FUN_WPU_M  (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S)
+#define IO_MUX_GPIO16_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO16_FUN_WPU_S  8
+/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO16_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO16_FUN_IE_M  (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S)
+#define IO_MUX_GPIO16_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO16_FUN_IE_S  9
+/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO16_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO16_FUN_DRV_M  (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S)
+#define IO_MUX_GPIO16_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO16_FUN_DRV_S  10
+/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO16_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO16_MCU_SEL_M  (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S)
+#define IO_MUX_GPIO16_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO16_MCU_SEL_S  12
+/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO16_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO16_FILTER_EN_M  (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S)
+#define IO_MUX_GPIO16_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO16_FILTER_EN_S  15
+
+/** IO_MUX_gpio17_REG register
+ *  iomux control register for gpio17
+ */
+#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x48)
+/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO17_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO17_MCU_OE_M  (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S)
+#define IO_MUX_GPIO17_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO17_MCU_OE_S  0
+/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO17_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO17_SLP_SEL_M  (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S)
+#define IO_MUX_GPIO17_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO17_SLP_SEL_S  1
+/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO17_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO17_MCU_WPD_M  (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S)
+#define IO_MUX_GPIO17_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO17_MCU_WPD_S  2
+/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO17_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO17_MCU_WPU_M  (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S)
+#define IO_MUX_GPIO17_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO17_MCU_WPU_S  3
+/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO17_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO17_MCU_IE_M  (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S)
+#define IO_MUX_GPIO17_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO17_MCU_IE_S  4
+/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO17_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO17_MCU_DRV_M  (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S)
+#define IO_MUX_GPIO17_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO17_MCU_DRV_S  5
+/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO17_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO17_FUN_WPD_M  (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S)
+#define IO_MUX_GPIO17_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO17_FUN_WPD_S  7
+/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO17_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO17_FUN_WPU_M  (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S)
+#define IO_MUX_GPIO17_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO17_FUN_WPU_S  8
+/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO17_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO17_FUN_IE_M  (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S)
+#define IO_MUX_GPIO17_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO17_FUN_IE_S  9
+/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO17_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO17_FUN_DRV_M  (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S)
+#define IO_MUX_GPIO17_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO17_FUN_DRV_S  10
+/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO17_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO17_MCU_SEL_M  (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S)
+#define IO_MUX_GPIO17_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO17_MCU_SEL_S  12
+/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO17_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO17_FILTER_EN_M  (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S)
+#define IO_MUX_GPIO17_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO17_FILTER_EN_S  15
+
+/** IO_MUX_gpio18_REG register
+ *  iomux control register for gpio18
+ */
+#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x4c)
+/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO18_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO18_MCU_OE_M  (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S)
+#define IO_MUX_GPIO18_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO18_MCU_OE_S  0
+/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO18_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO18_SLP_SEL_M  (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S)
+#define IO_MUX_GPIO18_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO18_SLP_SEL_S  1
+/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO18_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO18_MCU_WPD_M  (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S)
+#define IO_MUX_GPIO18_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO18_MCU_WPD_S  2
+/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO18_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO18_MCU_WPU_M  (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S)
+#define IO_MUX_GPIO18_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO18_MCU_WPU_S  3
+/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO18_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO18_MCU_IE_M  (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S)
+#define IO_MUX_GPIO18_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO18_MCU_IE_S  4
+/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO18_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO18_MCU_DRV_M  (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S)
+#define IO_MUX_GPIO18_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO18_MCU_DRV_S  5
+/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO18_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO18_FUN_WPD_M  (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S)
+#define IO_MUX_GPIO18_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO18_FUN_WPD_S  7
+/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO18_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO18_FUN_WPU_M  (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S)
+#define IO_MUX_GPIO18_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO18_FUN_WPU_S  8
+/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO18_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO18_FUN_IE_M  (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S)
+#define IO_MUX_GPIO18_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO18_FUN_IE_S  9
+/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO18_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO18_FUN_DRV_M  (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S)
+#define IO_MUX_GPIO18_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO18_FUN_DRV_S  10
+/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO18_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO18_MCU_SEL_M  (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S)
+#define IO_MUX_GPIO18_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO18_MCU_SEL_S  12
+/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO18_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO18_FILTER_EN_M  (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S)
+#define IO_MUX_GPIO18_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO18_FILTER_EN_S  15
+
+/** IO_MUX_gpio19_REG register
+ *  iomux control register for gpio19
+ */
+#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x50)
+/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO19_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO19_MCU_OE_M  (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S)
+#define IO_MUX_GPIO19_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO19_MCU_OE_S  0
+/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO19_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO19_SLP_SEL_M  (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S)
+#define IO_MUX_GPIO19_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO19_SLP_SEL_S  1
+/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO19_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO19_MCU_WPD_M  (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S)
+#define IO_MUX_GPIO19_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO19_MCU_WPD_S  2
+/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO19_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO19_MCU_WPU_M  (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S)
+#define IO_MUX_GPIO19_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO19_MCU_WPU_S  3
+/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO19_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO19_MCU_IE_M  (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S)
+#define IO_MUX_GPIO19_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO19_MCU_IE_S  4
+/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO19_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO19_MCU_DRV_M  (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S)
+#define IO_MUX_GPIO19_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO19_MCU_DRV_S  5
+/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO19_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO19_FUN_WPD_M  (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S)
+#define IO_MUX_GPIO19_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO19_FUN_WPD_S  7
+/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO19_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO19_FUN_WPU_M  (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S)
+#define IO_MUX_GPIO19_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO19_FUN_WPU_S  8
+/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO19_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO19_FUN_IE_M  (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S)
+#define IO_MUX_GPIO19_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO19_FUN_IE_S  9
+/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO19_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO19_FUN_DRV_M  (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S)
+#define IO_MUX_GPIO19_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO19_FUN_DRV_S  10
+/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO19_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO19_MCU_SEL_M  (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S)
+#define IO_MUX_GPIO19_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO19_MCU_SEL_S  12
+/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO19_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO19_FILTER_EN_M  (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S)
+#define IO_MUX_GPIO19_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO19_FILTER_EN_S  15
+
+/** IO_MUX_gpio20_REG register
+ *  iomux control register for gpio20
+ */
+#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x54)
+/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO20_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO20_MCU_OE_M  (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S)
+#define IO_MUX_GPIO20_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO20_MCU_OE_S  0
+/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO20_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO20_SLP_SEL_M  (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S)
+#define IO_MUX_GPIO20_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO20_SLP_SEL_S  1
+/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO20_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO20_MCU_WPD_M  (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S)
+#define IO_MUX_GPIO20_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO20_MCU_WPD_S  2
+/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO20_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO20_MCU_WPU_M  (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S)
+#define IO_MUX_GPIO20_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO20_MCU_WPU_S  3
+/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO20_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO20_MCU_IE_M  (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S)
+#define IO_MUX_GPIO20_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO20_MCU_IE_S  4
+/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO20_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO20_MCU_DRV_M  (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S)
+#define IO_MUX_GPIO20_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO20_MCU_DRV_S  5
+/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO20_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO20_FUN_WPD_M  (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S)
+#define IO_MUX_GPIO20_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO20_FUN_WPD_S  7
+/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO20_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO20_FUN_WPU_M  (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S)
+#define IO_MUX_GPIO20_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO20_FUN_WPU_S  8
+/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO20_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO20_FUN_IE_M  (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S)
+#define IO_MUX_GPIO20_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO20_FUN_IE_S  9
+/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO20_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO20_FUN_DRV_M  (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S)
+#define IO_MUX_GPIO20_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO20_FUN_DRV_S  10
+/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO20_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO20_MCU_SEL_M  (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S)
+#define IO_MUX_GPIO20_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO20_MCU_SEL_S  12
+/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO20_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO20_FILTER_EN_M  (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S)
+#define IO_MUX_GPIO20_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO20_FILTER_EN_S  15
+
+/** IO_MUX_gpio21_REG register
+ *  iomux control register for gpio21
+ */
+#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x58)
+/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO21_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO21_MCU_OE_M  (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S)
+#define IO_MUX_GPIO21_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO21_MCU_OE_S  0
+/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO21_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO21_SLP_SEL_M  (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S)
+#define IO_MUX_GPIO21_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO21_SLP_SEL_S  1
+/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO21_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO21_MCU_WPD_M  (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S)
+#define IO_MUX_GPIO21_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO21_MCU_WPD_S  2
+/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO21_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO21_MCU_WPU_M  (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S)
+#define IO_MUX_GPIO21_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO21_MCU_WPU_S  3
+/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO21_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO21_MCU_IE_M  (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S)
+#define IO_MUX_GPIO21_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO21_MCU_IE_S  4
+/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO21_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO21_MCU_DRV_M  (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S)
+#define IO_MUX_GPIO21_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO21_MCU_DRV_S  5
+/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO21_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO21_FUN_WPD_M  (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S)
+#define IO_MUX_GPIO21_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO21_FUN_WPD_S  7
+/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO21_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO21_FUN_WPU_M  (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S)
+#define IO_MUX_GPIO21_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO21_FUN_WPU_S  8
+/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO21_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO21_FUN_IE_M  (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S)
+#define IO_MUX_GPIO21_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO21_FUN_IE_S  9
+/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO21_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO21_FUN_DRV_M  (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S)
+#define IO_MUX_GPIO21_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO21_FUN_DRV_S  10
+/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO21_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO21_MCU_SEL_M  (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S)
+#define IO_MUX_GPIO21_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO21_MCU_SEL_S  12
+/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO21_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO21_FILTER_EN_M  (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S)
+#define IO_MUX_GPIO21_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO21_FILTER_EN_S  15
+
+/** IO_MUX_gpio22_REG register
+ *  iomux control register for gpio22
+ */
+#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x5c)
+/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO22_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO22_MCU_OE_M  (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S)
+#define IO_MUX_GPIO22_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO22_MCU_OE_S  0
+/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO22_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO22_SLP_SEL_M  (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S)
+#define IO_MUX_GPIO22_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO22_SLP_SEL_S  1
+/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO22_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO22_MCU_WPD_M  (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S)
+#define IO_MUX_GPIO22_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO22_MCU_WPD_S  2
+/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO22_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO22_MCU_WPU_M  (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S)
+#define IO_MUX_GPIO22_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO22_MCU_WPU_S  3
+/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO22_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO22_MCU_IE_M  (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S)
+#define IO_MUX_GPIO22_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO22_MCU_IE_S  4
+/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO22_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO22_MCU_DRV_M  (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S)
+#define IO_MUX_GPIO22_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO22_MCU_DRV_S  5
+/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO22_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO22_FUN_WPD_M  (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S)
+#define IO_MUX_GPIO22_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO22_FUN_WPD_S  7
+/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO22_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO22_FUN_WPU_M  (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S)
+#define IO_MUX_GPIO22_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO22_FUN_WPU_S  8
+/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO22_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO22_FUN_IE_M  (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S)
+#define IO_MUX_GPIO22_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO22_FUN_IE_S  9
+/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO22_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO22_FUN_DRV_M  (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S)
+#define IO_MUX_GPIO22_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO22_FUN_DRV_S  10
+/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO22_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO22_MCU_SEL_M  (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S)
+#define IO_MUX_GPIO22_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO22_MCU_SEL_S  12
+/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO22_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO22_FILTER_EN_M  (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S)
+#define IO_MUX_GPIO22_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO22_FILTER_EN_S  15
+
+/** IO_MUX_gpio23_REG register
+ *  iomux control register for gpio23
+ */
+#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x60)
+/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO23_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO23_MCU_OE_M  (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S)
+#define IO_MUX_GPIO23_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO23_MCU_OE_S  0
+/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO23_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO23_SLP_SEL_M  (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S)
+#define IO_MUX_GPIO23_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO23_SLP_SEL_S  1
+/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO23_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO23_MCU_WPD_M  (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S)
+#define IO_MUX_GPIO23_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO23_MCU_WPD_S  2
+/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO23_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO23_MCU_WPU_M  (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S)
+#define IO_MUX_GPIO23_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO23_MCU_WPU_S  3
+/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO23_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO23_MCU_IE_M  (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S)
+#define IO_MUX_GPIO23_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO23_MCU_IE_S  4
+/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO23_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO23_MCU_DRV_M  (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S)
+#define IO_MUX_GPIO23_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO23_MCU_DRV_S  5
+/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO23_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO23_FUN_WPD_M  (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S)
+#define IO_MUX_GPIO23_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO23_FUN_WPD_S  7
+/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO23_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO23_FUN_WPU_M  (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S)
+#define IO_MUX_GPIO23_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO23_FUN_WPU_S  8
+/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO23_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO23_FUN_IE_M  (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S)
+#define IO_MUX_GPIO23_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO23_FUN_IE_S  9
+/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO23_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO23_FUN_DRV_M  (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S)
+#define IO_MUX_GPIO23_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO23_FUN_DRV_S  10
+/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO23_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO23_MCU_SEL_M  (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S)
+#define IO_MUX_GPIO23_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO23_MCU_SEL_S  12
+/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO23_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO23_FILTER_EN_M  (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S)
+#define IO_MUX_GPIO23_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO23_FILTER_EN_S  15
+
+/** IO_MUX_gpio24_REG register
+ *  iomux control register for gpio24
+ */
+#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x64)
+/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO24_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO24_MCU_OE_M  (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S)
+#define IO_MUX_GPIO24_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO24_MCU_OE_S  0
+/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO24_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO24_SLP_SEL_M  (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S)
+#define IO_MUX_GPIO24_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO24_SLP_SEL_S  1
+/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO24_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO24_MCU_WPD_M  (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S)
+#define IO_MUX_GPIO24_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO24_MCU_WPD_S  2
+/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO24_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO24_MCU_WPU_M  (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S)
+#define IO_MUX_GPIO24_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO24_MCU_WPU_S  3
+/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO24_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO24_MCU_IE_M  (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S)
+#define IO_MUX_GPIO24_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO24_MCU_IE_S  4
+/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO24_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO24_MCU_DRV_M  (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S)
+#define IO_MUX_GPIO24_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO24_MCU_DRV_S  5
+/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO24_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO24_FUN_WPD_M  (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S)
+#define IO_MUX_GPIO24_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO24_FUN_WPD_S  7
+/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO24_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO24_FUN_WPU_M  (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S)
+#define IO_MUX_GPIO24_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO24_FUN_WPU_S  8
+/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO24_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO24_FUN_IE_M  (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S)
+#define IO_MUX_GPIO24_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO24_FUN_IE_S  9
+/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 3;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO24_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO24_FUN_DRV_M  (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S)
+#define IO_MUX_GPIO24_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO24_FUN_DRV_S  10
+/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO24_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO24_MCU_SEL_M  (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S)
+#define IO_MUX_GPIO24_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO24_MCU_SEL_S  12
+/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO24_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO24_FILTER_EN_M  (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S)
+#define IO_MUX_GPIO24_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO24_FILTER_EN_S  15
+
+/** IO_MUX_gpio25_REG register
+ *  iomux control register for gpio25
+ */
+#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x68)
+/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO25_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO25_MCU_OE_M  (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S)
+#define IO_MUX_GPIO25_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO25_MCU_OE_S  0
+/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO25_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO25_SLP_SEL_M  (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S)
+#define IO_MUX_GPIO25_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO25_SLP_SEL_S  1
+/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO25_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO25_MCU_WPD_M  (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S)
+#define IO_MUX_GPIO25_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO25_MCU_WPD_S  2
+/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO25_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO25_MCU_WPU_M  (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S)
+#define IO_MUX_GPIO25_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO25_MCU_WPU_S  3
+/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO25_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO25_MCU_IE_M  (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S)
+#define IO_MUX_GPIO25_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO25_MCU_IE_S  4
+/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO25_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO25_MCU_DRV_M  (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S)
+#define IO_MUX_GPIO25_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO25_MCU_DRV_S  5
+/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO25_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO25_FUN_WPD_M  (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S)
+#define IO_MUX_GPIO25_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO25_FUN_WPD_S  7
+/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO25_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO25_FUN_WPU_M  (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S)
+#define IO_MUX_GPIO25_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO25_FUN_WPU_S  8
+/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO25_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO25_FUN_IE_M  (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S)
+#define IO_MUX_GPIO25_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO25_FUN_IE_S  9
+/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 3;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO25_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO25_FUN_DRV_M  (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S)
+#define IO_MUX_GPIO25_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO25_FUN_DRV_S  10
+/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO25_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO25_MCU_SEL_M  (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S)
+#define IO_MUX_GPIO25_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO25_MCU_SEL_S  12
+/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO25_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO25_FILTER_EN_M  (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S)
+#define IO_MUX_GPIO25_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO25_FILTER_EN_S  15
+
+/** IO_MUX_gpio26_REG register
+ *  iomux control register for gpio26
+ */
+#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x6c)
+/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO26_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO26_MCU_OE_M  (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S)
+#define IO_MUX_GPIO26_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO26_MCU_OE_S  0
+/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO26_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO26_SLP_SEL_M  (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S)
+#define IO_MUX_GPIO26_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO26_SLP_SEL_S  1
+/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO26_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO26_MCU_WPD_M  (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S)
+#define IO_MUX_GPIO26_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO26_MCU_WPD_S  2
+/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO26_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO26_MCU_WPU_M  (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S)
+#define IO_MUX_GPIO26_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO26_MCU_WPU_S  3
+/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO26_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO26_MCU_IE_M  (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S)
+#define IO_MUX_GPIO26_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO26_MCU_IE_S  4
+/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO26_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO26_MCU_DRV_M  (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S)
+#define IO_MUX_GPIO26_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO26_MCU_DRV_S  5
+/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO26_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO26_FUN_WPD_M  (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S)
+#define IO_MUX_GPIO26_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO26_FUN_WPD_S  7
+/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO26_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO26_FUN_WPU_M  (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S)
+#define IO_MUX_GPIO26_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO26_FUN_WPU_S  8
+/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO26_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO26_FUN_IE_M  (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S)
+#define IO_MUX_GPIO26_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO26_FUN_IE_S  9
+/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO26_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO26_FUN_DRV_M  (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S)
+#define IO_MUX_GPIO26_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO26_FUN_DRV_S  10
+/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO26_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO26_MCU_SEL_M  (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S)
+#define IO_MUX_GPIO26_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO26_MCU_SEL_S  12
+/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO26_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO26_FILTER_EN_M  (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S)
+#define IO_MUX_GPIO26_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO26_FILTER_EN_S  15
+
+/** IO_MUX_gpio27_REG register
+ *  iomux control register for gpio27
+ */
+#define IO_MUX_GPIO27_REG (DR_REG_IO_MUX_BASE + 0x70)
+/** IO_MUX_GPIO27_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO27_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO27_MCU_OE_M  (IO_MUX_GPIO27_MCU_OE_V << IO_MUX_GPIO27_MCU_OE_S)
+#define IO_MUX_GPIO27_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO27_MCU_OE_S  0
+/** IO_MUX_GPIO27_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO27_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO27_SLP_SEL_M  (IO_MUX_GPIO27_SLP_SEL_V << IO_MUX_GPIO27_SLP_SEL_S)
+#define IO_MUX_GPIO27_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO27_SLP_SEL_S  1
+/** IO_MUX_GPIO27_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO27_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO27_MCU_WPD_M  (IO_MUX_GPIO27_MCU_WPD_V << IO_MUX_GPIO27_MCU_WPD_S)
+#define IO_MUX_GPIO27_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO27_MCU_WPD_S  2
+/** IO_MUX_GPIO27_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO27_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO27_MCU_WPU_M  (IO_MUX_GPIO27_MCU_WPU_V << IO_MUX_GPIO27_MCU_WPU_S)
+#define IO_MUX_GPIO27_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO27_MCU_WPU_S  3
+/** IO_MUX_GPIO27_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO27_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO27_MCU_IE_M  (IO_MUX_GPIO27_MCU_IE_V << IO_MUX_GPIO27_MCU_IE_S)
+#define IO_MUX_GPIO27_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO27_MCU_IE_S  4
+/** IO_MUX_GPIO27_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO27_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO27_MCU_DRV_M  (IO_MUX_GPIO27_MCU_DRV_V << IO_MUX_GPIO27_MCU_DRV_S)
+#define IO_MUX_GPIO27_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO27_MCU_DRV_S  5
+/** IO_MUX_GPIO27_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO27_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO27_FUN_WPD_M  (IO_MUX_GPIO27_FUN_WPD_V << IO_MUX_GPIO27_FUN_WPD_S)
+#define IO_MUX_GPIO27_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO27_FUN_WPD_S  7
+/** IO_MUX_GPIO27_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO27_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO27_FUN_WPU_M  (IO_MUX_GPIO27_FUN_WPU_V << IO_MUX_GPIO27_FUN_WPU_S)
+#define IO_MUX_GPIO27_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO27_FUN_WPU_S  8
+/** IO_MUX_GPIO27_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO27_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO27_FUN_IE_M  (IO_MUX_GPIO27_FUN_IE_V << IO_MUX_GPIO27_FUN_IE_S)
+#define IO_MUX_GPIO27_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO27_FUN_IE_S  9
+/** IO_MUX_GPIO27_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO27_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO27_FUN_DRV_M  (IO_MUX_GPIO27_FUN_DRV_V << IO_MUX_GPIO27_FUN_DRV_S)
+#define IO_MUX_GPIO27_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO27_FUN_DRV_S  10
+/** IO_MUX_GPIO27_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO27_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO27_MCU_SEL_M  (IO_MUX_GPIO27_MCU_SEL_V << IO_MUX_GPIO27_MCU_SEL_S)
+#define IO_MUX_GPIO27_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO27_MCU_SEL_S  12
+/** IO_MUX_GPIO27_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO27_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO27_FILTER_EN_M  (IO_MUX_GPIO27_FILTER_EN_V << IO_MUX_GPIO27_FILTER_EN_S)
+#define IO_MUX_GPIO27_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO27_FILTER_EN_S  15
+
+/** IO_MUX_gpio28_REG register
+ *  iomux control register for gpio28
+ */
+#define IO_MUX_GPIO28_REG (DR_REG_IO_MUX_BASE + 0x74)
+/** IO_MUX_GPIO28_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO28_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO28_MCU_OE_M  (IO_MUX_GPIO28_MCU_OE_V << IO_MUX_GPIO28_MCU_OE_S)
+#define IO_MUX_GPIO28_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO28_MCU_OE_S  0
+/** IO_MUX_GPIO28_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO28_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO28_SLP_SEL_M  (IO_MUX_GPIO28_SLP_SEL_V << IO_MUX_GPIO28_SLP_SEL_S)
+#define IO_MUX_GPIO28_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO28_SLP_SEL_S  1
+/** IO_MUX_GPIO28_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO28_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO28_MCU_WPD_M  (IO_MUX_GPIO28_MCU_WPD_V << IO_MUX_GPIO28_MCU_WPD_S)
+#define IO_MUX_GPIO28_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO28_MCU_WPD_S  2
+/** IO_MUX_GPIO28_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO28_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO28_MCU_WPU_M  (IO_MUX_GPIO28_MCU_WPU_V << IO_MUX_GPIO28_MCU_WPU_S)
+#define IO_MUX_GPIO28_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO28_MCU_WPU_S  3
+/** IO_MUX_GPIO28_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO28_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO28_MCU_IE_M  (IO_MUX_GPIO28_MCU_IE_V << IO_MUX_GPIO28_MCU_IE_S)
+#define IO_MUX_GPIO28_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO28_MCU_IE_S  4
+/** IO_MUX_GPIO28_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO28_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO28_MCU_DRV_M  (IO_MUX_GPIO28_MCU_DRV_V << IO_MUX_GPIO28_MCU_DRV_S)
+#define IO_MUX_GPIO28_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO28_MCU_DRV_S  5
+/** IO_MUX_GPIO28_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO28_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO28_FUN_WPD_M  (IO_MUX_GPIO28_FUN_WPD_V << IO_MUX_GPIO28_FUN_WPD_S)
+#define IO_MUX_GPIO28_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO28_FUN_WPD_S  7
+/** IO_MUX_GPIO28_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO28_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO28_FUN_WPU_M  (IO_MUX_GPIO28_FUN_WPU_V << IO_MUX_GPIO28_FUN_WPU_S)
+#define IO_MUX_GPIO28_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO28_FUN_WPU_S  8
+/** IO_MUX_GPIO28_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO28_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO28_FUN_IE_M  (IO_MUX_GPIO28_FUN_IE_V << IO_MUX_GPIO28_FUN_IE_S)
+#define IO_MUX_GPIO28_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO28_FUN_IE_S  9
+/** IO_MUX_GPIO28_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO28_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO28_FUN_DRV_M  (IO_MUX_GPIO28_FUN_DRV_V << IO_MUX_GPIO28_FUN_DRV_S)
+#define IO_MUX_GPIO28_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO28_FUN_DRV_S  10
+/** IO_MUX_GPIO28_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO28_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO28_MCU_SEL_M  (IO_MUX_GPIO28_MCU_SEL_V << IO_MUX_GPIO28_MCU_SEL_S)
+#define IO_MUX_GPIO28_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO28_MCU_SEL_S  12
+/** IO_MUX_GPIO28_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO28_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO28_FILTER_EN_M  (IO_MUX_GPIO28_FILTER_EN_V << IO_MUX_GPIO28_FILTER_EN_S)
+#define IO_MUX_GPIO28_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO28_FILTER_EN_S  15
+
+/** IO_MUX_gpio29_REG register
+ *  iomux control register for gpio29
+ */
+#define IO_MUX_GPIO29_REG (DR_REG_IO_MUX_BASE + 0x78)
+/** IO_MUX_GPIO29_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO29_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO29_MCU_OE_M  (IO_MUX_GPIO29_MCU_OE_V << IO_MUX_GPIO29_MCU_OE_S)
+#define IO_MUX_GPIO29_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO29_MCU_OE_S  0
+/** IO_MUX_GPIO29_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO29_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO29_SLP_SEL_M  (IO_MUX_GPIO29_SLP_SEL_V << IO_MUX_GPIO29_SLP_SEL_S)
+#define IO_MUX_GPIO29_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO29_SLP_SEL_S  1
+/** IO_MUX_GPIO29_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO29_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO29_MCU_WPD_M  (IO_MUX_GPIO29_MCU_WPD_V << IO_MUX_GPIO29_MCU_WPD_S)
+#define IO_MUX_GPIO29_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO29_MCU_WPD_S  2
+/** IO_MUX_GPIO29_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO29_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO29_MCU_WPU_M  (IO_MUX_GPIO29_MCU_WPU_V << IO_MUX_GPIO29_MCU_WPU_S)
+#define IO_MUX_GPIO29_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO29_MCU_WPU_S  3
+/** IO_MUX_GPIO29_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO29_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO29_MCU_IE_M  (IO_MUX_GPIO29_MCU_IE_V << IO_MUX_GPIO29_MCU_IE_S)
+#define IO_MUX_GPIO29_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO29_MCU_IE_S  4
+/** IO_MUX_GPIO29_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO29_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO29_MCU_DRV_M  (IO_MUX_GPIO29_MCU_DRV_V << IO_MUX_GPIO29_MCU_DRV_S)
+#define IO_MUX_GPIO29_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO29_MCU_DRV_S  5
+/** IO_MUX_GPIO29_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO29_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO29_FUN_WPD_M  (IO_MUX_GPIO29_FUN_WPD_V << IO_MUX_GPIO29_FUN_WPD_S)
+#define IO_MUX_GPIO29_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO29_FUN_WPD_S  7
+/** IO_MUX_GPIO29_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO29_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO29_FUN_WPU_M  (IO_MUX_GPIO29_FUN_WPU_V << IO_MUX_GPIO29_FUN_WPU_S)
+#define IO_MUX_GPIO29_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO29_FUN_WPU_S  8
+/** IO_MUX_GPIO29_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO29_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO29_FUN_IE_M  (IO_MUX_GPIO29_FUN_IE_V << IO_MUX_GPIO29_FUN_IE_S)
+#define IO_MUX_GPIO29_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO29_FUN_IE_S  9
+/** IO_MUX_GPIO29_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO29_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO29_FUN_DRV_M  (IO_MUX_GPIO29_FUN_DRV_V << IO_MUX_GPIO29_FUN_DRV_S)
+#define IO_MUX_GPIO29_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO29_FUN_DRV_S  10
+/** IO_MUX_GPIO29_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO29_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO29_MCU_SEL_M  (IO_MUX_GPIO29_MCU_SEL_V << IO_MUX_GPIO29_MCU_SEL_S)
+#define IO_MUX_GPIO29_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO29_MCU_SEL_S  12
+/** IO_MUX_GPIO29_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO29_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO29_FILTER_EN_M  (IO_MUX_GPIO29_FILTER_EN_V << IO_MUX_GPIO29_FILTER_EN_S)
+#define IO_MUX_GPIO29_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO29_FILTER_EN_S  15
+
+/** IO_MUX_gpio30_REG register
+ *  iomux control register for gpio30
+ */
+#define IO_MUX_GPIO30_REG (DR_REG_IO_MUX_BASE + 0x7c)
+/** IO_MUX_GPIO30_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO30_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO30_MCU_OE_M  (IO_MUX_GPIO30_MCU_OE_V << IO_MUX_GPIO30_MCU_OE_S)
+#define IO_MUX_GPIO30_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO30_MCU_OE_S  0
+/** IO_MUX_GPIO30_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO30_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO30_SLP_SEL_M  (IO_MUX_GPIO30_SLP_SEL_V << IO_MUX_GPIO30_SLP_SEL_S)
+#define IO_MUX_GPIO30_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO30_SLP_SEL_S  1
+/** IO_MUX_GPIO30_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO30_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO30_MCU_WPD_M  (IO_MUX_GPIO30_MCU_WPD_V << IO_MUX_GPIO30_MCU_WPD_S)
+#define IO_MUX_GPIO30_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO30_MCU_WPD_S  2
+/** IO_MUX_GPIO30_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO30_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO30_MCU_WPU_M  (IO_MUX_GPIO30_MCU_WPU_V << IO_MUX_GPIO30_MCU_WPU_S)
+#define IO_MUX_GPIO30_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO30_MCU_WPU_S  3
+/** IO_MUX_GPIO30_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO30_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO30_MCU_IE_M  (IO_MUX_GPIO30_MCU_IE_V << IO_MUX_GPIO30_MCU_IE_S)
+#define IO_MUX_GPIO30_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO30_MCU_IE_S  4
+/** IO_MUX_GPIO30_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO30_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO30_MCU_DRV_M  (IO_MUX_GPIO30_MCU_DRV_V << IO_MUX_GPIO30_MCU_DRV_S)
+#define IO_MUX_GPIO30_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO30_MCU_DRV_S  5
+/** IO_MUX_GPIO30_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO30_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO30_FUN_WPD_M  (IO_MUX_GPIO30_FUN_WPD_V << IO_MUX_GPIO30_FUN_WPD_S)
+#define IO_MUX_GPIO30_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO30_FUN_WPD_S  7
+/** IO_MUX_GPIO30_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO30_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO30_FUN_WPU_M  (IO_MUX_GPIO30_FUN_WPU_V << IO_MUX_GPIO30_FUN_WPU_S)
+#define IO_MUX_GPIO30_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO30_FUN_WPU_S  8
+/** IO_MUX_GPIO30_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO30_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO30_FUN_IE_M  (IO_MUX_GPIO30_FUN_IE_V << IO_MUX_GPIO30_FUN_IE_S)
+#define IO_MUX_GPIO30_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO30_FUN_IE_S  9
+/** IO_MUX_GPIO30_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO30_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO30_FUN_DRV_M  (IO_MUX_GPIO30_FUN_DRV_V << IO_MUX_GPIO30_FUN_DRV_S)
+#define IO_MUX_GPIO30_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO30_FUN_DRV_S  10
+/** IO_MUX_GPIO30_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO30_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO30_MCU_SEL_M  (IO_MUX_GPIO30_MCU_SEL_V << IO_MUX_GPIO30_MCU_SEL_S)
+#define IO_MUX_GPIO30_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO30_MCU_SEL_S  12
+/** IO_MUX_GPIO30_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO30_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO30_FILTER_EN_M  (IO_MUX_GPIO30_FILTER_EN_V << IO_MUX_GPIO30_FILTER_EN_S)
+#define IO_MUX_GPIO30_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO30_FILTER_EN_S  15
+
+/** IO_MUX_gpio31_REG register
+ *  iomux control register for gpio31
+ */
+#define IO_MUX_GPIO31_REG (DR_REG_IO_MUX_BASE + 0x80)
+/** IO_MUX_GPIO31_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO31_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO31_MCU_OE_M  (IO_MUX_GPIO31_MCU_OE_V << IO_MUX_GPIO31_MCU_OE_S)
+#define IO_MUX_GPIO31_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO31_MCU_OE_S  0
+/** IO_MUX_GPIO31_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO31_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO31_SLP_SEL_M  (IO_MUX_GPIO31_SLP_SEL_V << IO_MUX_GPIO31_SLP_SEL_S)
+#define IO_MUX_GPIO31_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO31_SLP_SEL_S  1
+/** IO_MUX_GPIO31_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO31_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO31_MCU_WPD_M  (IO_MUX_GPIO31_MCU_WPD_V << IO_MUX_GPIO31_MCU_WPD_S)
+#define IO_MUX_GPIO31_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO31_MCU_WPD_S  2
+/** IO_MUX_GPIO31_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO31_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO31_MCU_WPU_M  (IO_MUX_GPIO31_MCU_WPU_V << IO_MUX_GPIO31_MCU_WPU_S)
+#define IO_MUX_GPIO31_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO31_MCU_WPU_S  3
+/** IO_MUX_GPIO31_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO31_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO31_MCU_IE_M  (IO_MUX_GPIO31_MCU_IE_V << IO_MUX_GPIO31_MCU_IE_S)
+#define IO_MUX_GPIO31_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO31_MCU_IE_S  4
+/** IO_MUX_GPIO31_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO31_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO31_MCU_DRV_M  (IO_MUX_GPIO31_MCU_DRV_V << IO_MUX_GPIO31_MCU_DRV_S)
+#define IO_MUX_GPIO31_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO31_MCU_DRV_S  5
+/** IO_MUX_GPIO31_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO31_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO31_FUN_WPD_M  (IO_MUX_GPIO31_FUN_WPD_V << IO_MUX_GPIO31_FUN_WPD_S)
+#define IO_MUX_GPIO31_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO31_FUN_WPD_S  7
+/** IO_MUX_GPIO31_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO31_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO31_FUN_WPU_M  (IO_MUX_GPIO31_FUN_WPU_V << IO_MUX_GPIO31_FUN_WPU_S)
+#define IO_MUX_GPIO31_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO31_FUN_WPU_S  8
+/** IO_MUX_GPIO31_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO31_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO31_FUN_IE_M  (IO_MUX_GPIO31_FUN_IE_V << IO_MUX_GPIO31_FUN_IE_S)
+#define IO_MUX_GPIO31_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO31_FUN_IE_S  9
+/** IO_MUX_GPIO31_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO31_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO31_FUN_DRV_M  (IO_MUX_GPIO31_FUN_DRV_V << IO_MUX_GPIO31_FUN_DRV_S)
+#define IO_MUX_GPIO31_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO31_FUN_DRV_S  10
+/** IO_MUX_GPIO31_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO31_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO31_MCU_SEL_M  (IO_MUX_GPIO31_MCU_SEL_V << IO_MUX_GPIO31_MCU_SEL_S)
+#define IO_MUX_GPIO31_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO31_MCU_SEL_S  12
+/** IO_MUX_GPIO31_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO31_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO31_FILTER_EN_M  (IO_MUX_GPIO31_FILTER_EN_V << IO_MUX_GPIO31_FILTER_EN_S)
+#define IO_MUX_GPIO31_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO31_FILTER_EN_S  15
+
+/** IO_MUX_gpio32_REG register
+ *  iomux control register for gpio32
+ */
+#define IO_MUX_GPIO32_REG (DR_REG_IO_MUX_BASE + 0x84)
+/** IO_MUX_GPIO32_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO32_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO32_MCU_OE_M  (IO_MUX_GPIO32_MCU_OE_V << IO_MUX_GPIO32_MCU_OE_S)
+#define IO_MUX_GPIO32_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO32_MCU_OE_S  0
+/** IO_MUX_GPIO32_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO32_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO32_SLP_SEL_M  (IO_MUX_GPIO32_SLP_SEL_V << IO_MUX_GPIO32_SLP_SEL_S)
+#define IO_MUX_GPIO32_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO32_SLP_SEL_S  1
+/** IO_MUX_GPIO32_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO32_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO32_MCU_WPD_M  (IO_MUX_GPIO32_MCU_WPD_V << IO_MUX_GPIO32_MCU_WPD_S)
+#define IO_MUX_GPIO32_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO32_MCU_WPD_S  2
+/** IO_MUX_GPIO32_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO32_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO32_MCU_WPU_M  (IO_MUX_GPIO32_MCU_WPU_V << IO_MUX_GPIO32_MCU_WPU_S)
+#define IO_MUX_GPIO32_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO32_MCU_WPU_S  3
+/** IO_MUX_GPIO32_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO32_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO32_MCU_IE_M  (IO_MUX_GPIO32_MCU_IE_V << IO_MUX_GPIO32_MCU_IE_S)
+#define IO_MUX_GPIO32_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO32_MCU_IE_S  4
+/** IO_MUX_GPIO32_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO32_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO32_MCU_DRV_M  (IO_MUX_GPIO32_MCU_DRV_V << IO_MUX_GPIO32_MCU_DRV_S)
+#define IO_MUX_GPIO32_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO32_MCU_DRV_S  5
+/** IO_MUX_GPIO32_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO32_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO32_FUN_WPD_M  (IO_MUX_GPIO32_FUN_WPD_V << IO_MUX_GPIO32_FUN_WPD_S)
+#define IO_MUX_GPIO32_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO32_FUN_WPD_S  7
+/** IO_MUX_GPIO32_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO32_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO32_FUN_WPU_M  (IO_MUX_GPIO32_FUN_WPU_V << IO_MUX_GPIO32_FUN_WPU_S)
+#define IO_MUX_GPIO32_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO32_FUN_WPU_S  8
+/** IO_MUX_GPIO32_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO32_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO32_FUN_IE_M  (IO_MUX_GPIO32_FUN_IE_V << IO_MUX_GPIO32_FUN_IE_S)
+#define IO_MUX_GPIO32_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO32_FUN_IE_S  9
+/** IO_MUX_GPIO32_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO32_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO32_FUN_DRV_M  (IO_MUX_GPIO32_FUN_DRV_V << IO_MUX_GPIO32_FUN_DRV_S)
+#define IO_MUX_GPIO32_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO32_FUN_DRV_S  10
+/** IO_MUX_GPIO32_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO32_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO32_MCU_SEL_M  (IO_MUX_GPIO32_MCU_SEL_V << IO_MUX_GPIO32_MCU_SEL_S)
+#define IO_MUX_GPIO32_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO32_MCU_SEL_S  12
+/** IO_MUX_GPIO32_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO32_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO32_FILTER_EN_M  (IO_MUX_GPIO32_FILTER_EN_V << IO_MUX_GPIO32_FILTER_EN_S)
+#define IO_MUX_GPIO32_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO32_FILTER_EN_S  15
+/** IO_MUX_GPIO32_RUE_I3C : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO32_RUE_I3C    (BIT(16))
+#define IO_MUX_GPIO32_RUE_I3C_M  (IO_MUX_GPIO32_RUE_I3C_V << IO_MUX_GPIO32_RUE_I3C_S)
+#define IO_MUX_GPIO32_RUE_I3C_V  0x00000001U
+#define IO_MUX_GPIO32_RUE_I3C_S  16
+/** IO_MUX_GPIO32_RU_I3C : R/W; bitpos: [18:17]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO32_RU_I3C    0x00000003U
+#define IO_MUX_GPIO32_RU_I3C_M  (IO_MUX_GPIO32_RU_I3C_V << IO_MUX_GPIO32_RU_I3C_S)
+#define IO_MUX_GPIO32_RU_I3C_V  0x00000003U
+#define IO_MUX_GPIO32_RU_I3C_S  17
+/** IO_MUX_GPIO32_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO32_RUE_SEL_I3C    (BIT(19))
+#define IO_MUX_GPIO32_RUE_SEL_I3C_M  (IO_MUX_GPIO32_RUE_SEL_I3C_V << IO_MUX_GPIO32_RUE_SEL_I3C_S)
+#define IO_MUX_GPIO32_RUE_SEL_I3C_V  0x00000001U
+#define IO_MUX_GPIO32_RUE_SEL_I3C_S  19
+
+/** IO_MUX_gpio33_REG register
+ *  iomux control register for gpio33
+ */
+#define IO_MUX_GPIO33_REG (DR_REG_IO_MUX_BASE + 0x88)
+/** IO_MUX_GPIO33_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO33_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO33_MCU_OE_M  (IO_MUX_GPIO33_MCU_OE_V << IO_MUX_GPIO33_MCU_OE_S)
+#define IO_MUX_GPIO33_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO33_MCU_OE_S  0
+/** IO_MUX_GPIO33_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO33_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO33_SLP_SEL_M  (IO_MUX_GPIO33_SLP_SEL_V << IO_MUX_GPIO33_SLP_SEL_S)
+#define IO_MUX_GPIO33_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO33_SLP_SEL_S  1
+/** IO_MUX_GPIO33_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO33_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO33_MCU_WPD_M  (IO_MUX_GPIO33_MCU_WPD_V << IO_MUX_GPIO33_MCU_WPD_S)
+#define IO_MUX_GPIO33_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO33_MCU_WPD_S  2
+/** IO_MUX_GPIO33_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO33_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO33_MCU_WPU_M  (IO_MUX_GPIO33_MCU_WPU_V << IO_MUX_GPIO33_MCU_WPU_S)
+#define IO_MUX_GPIO33_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO33_MCU_WPU_S  3
+/** IO_MUX_GPIO33_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO33_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO33_MCU_IE_M  (IO_MUX_GPIO33_MCU_IE_V << IO_MUX_GPIO33_MCU_IE_S)
+#define IO_MUX_GPIO33_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO33_MCU_IE_S  4
+/** IO_MUX_GPIO33_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO33_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO33_MCU_DRV_M  (IO_MUX_GPIO33_MCU_DRV_V << IO_MUX_GPIO33_MCU_DRV_S)
+#define IO_MUX_GPIO33_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO33_MCU_DRV_S  5
+/** IO_MUX_GPIO33_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO33_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO33_FUN_WPD_M  (IO_MUX_GPIO33_FUN_WPD_V << IO_MUX_GPIO33_FUN_WPD_S)
+#define IO_MUX_GPIO33_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO33_FUN_WPD_S  7
+/** IO_MUX_GPIO33_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO33_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO33_FUN_WPU_M  (IO_MUX_GPIO33_FUN_WPU_V << IO_MUX_GPIO33_FUN_WPU_S)
+#define IO_MUX_GPIO33_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO33_FUN_WPU_S  8
+/** IO_MUX_GPIO33_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO33_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO33_FUN_IE_M  (IO_MUX_GPIO33_FUN_IE_V << IO_MUX_GPIO33_FUN_IE_S)
+#define IO_MUX_GPIO33_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO33_FUN_IE_S  9
+/** IO_MUX_GPIO33_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO33_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO33_FUN_DRV_M  (IO_MUX_GPIO33_FUN_DRV_V << IO_MUX_GPIO33_FUN_DRV_S)
+#define IO_MUX_GPIO33_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO33_FUN_DRV_S  10
+/** IO_MUX_GPIO33_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO33_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO33_MCU_SEL_M  (IO_MUX_GPIO33_MCU_SEL_V << IO_MUX_GPIO33_MCU_SEL_S)
+#define IO_MUX_GPIO33_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO33_MCU_SEL_S  12
+/** IO_MUX_GPIO33_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO33_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO33_FILTER_EN_M  (IO_MUX_GPIO33_FILTER_EN_V << IO_MUX_GPIO33_FILTER_EN_S)
+#define IO_MUX_GPIO33_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO33_FILTER_EN_S  15
+/** IO_MUX_GPIO33_RUE_I3C : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO33_RUE_I3C    (BIT(16))
+#define IO_MUX_GPIO33_RUE_I3C_M  (IO_MUX_GPIO33_RUE_I3C_V << IO_MUX_GPIO33_RUE_I3C_S)
+#define IO_MUX_GPIO33_RUE_I3C_V  0x00000001U
+#define IO_MUX_GPIO33_RUE_I3C_S  16
+/** IO_MUX_GPIO33_RU_I3C : R/W; bitpos: [18:17]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO33_RU_I3C    0x00000003U
+#define IO_MUX_GPIO33_RU_I3C_M  (IO_MUX_GPIO33_RU_I3C_V << IO_MUX_GPIO33_RU_I3C_S)
+#define IO_MUX_GPIO33_RU_I3C_V  0x00000003U
+#define IO_MUX_GPIO33_RU_I3C_S  17
+/** IO_MUX_GPIO33_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define IO_MUX_GPIO33_RUE_SEL_I3C    (BIT(19))
+#define IO_MUX_GPIO33_RUE_SEL_I3C_M  (IO_MUX_GPIO33_RUE_SEL_I3C_V << IO_MUX_GPIO33_RUE_SEL_I3C_S)
+#define IO_MUX_GPIO33_RUE_SEL_I3C_V  0x00000001U
+#define IO_MUX_GPIO33_RUE_SEL_I3C_S  19
+
+/** IO_MUX_gpio34_REG register
+ *  iomux control register for gpio34
+ */
+#define IO_MUX_GPIO34_REG (DR_REG_IO_MUX_BASE + 0x8c)
+/** IO_MUX_GPIO34_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO34_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO34_MCU_OE_M  (IO_MUX_GPIO34_MCU_OE_V << IO_MUX_GPIO34_MCU_OE_S)
+#define IO_MUX_GPIO34_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO34_MCU_OE_S  0
+/** IO_MUX_GPIO34_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO34_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO34_SLP_SEL_M  (IO_MUX_GPIO34_SLP_SEL_V << IO_MUX_GPIO34_SLP_SEL_S)
+#define IO_MUX_GPIO34_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO34_SLP_SEL_S  1
+/** IO_MUX_GPIO34_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO34_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO34_MCU_WPD_M  (IO_MUX_GPIO34_MCU_WPD_V << IO_MUX_GPIO34_MCU_WPD_S)
+#define IO_MUX_GPIO34_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO34_MCU_WPD_S  2
+/** IO_MUX_GPIO34_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO34_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO34_MCU_WPU_M  (IO_MUX_GPIO34_MCU_WPU_V << IO_MUX_GPIO34_MCU_WPU_S)
+#define IO_MUX_GPIO34_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO34_MCU_WPU_S  3
+/** IO_MUX_GPIO34_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO34_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO34_MCU_IE_M  (IO_MUX_GPIO34_MCU_IE_V << IO_MUX_GPIO34_MCU_IE_S)
+#define IO_MUX_GPIO34_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO34_MCU_IE_S  4
+/** IO_MUX_GPIO34_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO34_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO34_MCU_DRV_M  (IO_MUX_GPIO34_MCU_DRV_V << IO_MUX_GPIO34_MCU_DRV_S)
+#define IO_MUX_GPIO34_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO34_MCU_DRV_S  5
+/** IO_MUX_GPIO34_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO34_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO34_FUN_WPD_M  (IO_MUX_GPIO34_FUN_WPD_V << IO_MUX_GPIO34_FUN_WPD_S)
+#define IO_MUX_GPIO34_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO34_FUN_WPD_S  7
+/** IO_MUX_GPIO34_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO34_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO34_FUN_WPU_M  (IO_MUX_GPIO34_FUN_WPU_V << IO_MUX_GPIO34_FUN_WPU_S)
+#define IO_MUX_GPIO34_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO34_FUN_WPU_S  8
+/** IO_MUX_GPIO34_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO34_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO34_FUN_IE_M  (IO_MUX_GPIO34_FUN_IE_V << IO_MUX_GPIO34_FUN_IE_S)
+#define IO_MUX_GPIO34_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO34_FUN_IE_S  9
+/** IO_MUX_GPIO34_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO34_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO34_FUN_DRV_M  (IO_MUX_GPIO34_FUN_DRV_V << IO_MUX_GPIO34_FUN_DRV_S)
+#define IO_MUX_GPIO34_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO34_FUN_DRV_S  10
+/** IO_MUX_GPIO34_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO34_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO34_MCU_SEL_M  (IO_MUX_GPIO34_MCU_SEL_V << IO_MUX_GPIO34_MCU_SEL_S)
+#define IO_MUX_GPIO34_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO34_MCU_SEL_S  12
+/** IO_MUX_GPIO34_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO34_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO34_FILTER_EN_M  (IO_MUX_GPIO34_FILTER_EN_V << IO_MUX_GPIO34_FILTER_EN_S)
+#define IO_MUX_GPIO34_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO34_FILTER_EN_S  15
+
+/** IO_MUX_gpio35_REG register
+ *  iomux control register for gpio35
+ */
+#define IO_MUX_GPIO35_REG (DR_REG_IO_MUX_BASE + 0x90)
+/** IO_MUX_GPIO35_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO35_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO35_MCU_OE_M  (IO_MUX_GPIO35_MCU_OE_V << IO_MUX_GPIO35_MCU_OE_S)
+#define IO_MUX_GPIO35_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO35_MCU_OE_S  0
+/** IO_MUX_GPIO35_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO35_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO35_SLP_SEL_M  (IO_MUX_GPIO35_SLP_SEL_V << IO_MUX_GPIO35_SLP_SEL_S)
+#define IO_MUX_GPIO35_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO35_SLP_SEL_S  1
+/** IO_MUX_GPIO35_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO35_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO35_MCU_WPD_M  (IO_MUX_GPIO35_MCU_WPD_V << IO_MUX_GPIO35_MCU_WPD_S)
+#define IO_MUX_GPIO35_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO35_MCU_WPD_S  2
+/** IO_MUX_GPIO35_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO35_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO35_MCU_WPU_M  (IO_MUX_GPIO35_MCU_WPU_V << IO_MUX_GPIO35_MCU_WPU_S)
+#define IO_MUX_GPIO35_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO35_MCU_WPU_S  3
+/** IO_MUX_GPIO35_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO35_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO35_MCU_IE_M  (IO_MUX_GPIO35_MCU_IE_V << IO_MUX_GPIO35_MCU_IE_S)
+#define IO_MUX_GPIO35_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO35_MCU_IE_S  4
+/** IO_MUX_GPIO35_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO35_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO35_MCU_DRV_M  (IO_MUX_GPIO35_MCU_DRV_V << IO_MUX_GPIO35_MCU_DRV_S)
+#define IO_MUX_GPIO35_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO35_MCU_DRV_S  5
+/** IO_MUX_GPIO35_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO35_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO35_FUN_WPD_M  (IO_MUX_GPIO35_FUN_WPD_V << IO_MUX_GPIO35_FUN_WPD_S)
+#define IO_MUX_GPIO35_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO35_FUN_WPD_S  7
+/** IO_MUX_GPIO35_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO35_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO35_FUN_WPU_M  (IO_MUX_GPIO35_FUN_WPU_V << IO_MUX_GPIO35_FUN_WPU_S)
+#define IO_MUX_GPIO35_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO35_FUN_WPU_S  8
+/** IO_MUX_GPIO35_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO35_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO35_FUN_IE_M  (IO_MUX_GPIO35_FUN_IE_V << IO_MUX_GPIO35_FUN_IE_S)
+#define IO_MUX_GPIO35_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO35_FUN_IE_S  9
+/** IO_MUX_GPIO35_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO35_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO35_FUN_DRV_M  (IO_MUX_GPIO35_FUN_DRV_V << IO_MUX_GPIO35_FUN_DRV_S)
+#define IO_MUX_GPIO35_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO35_FUN_DRV_S  10
+/** IO_MUX_GPIO35_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO35_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO35_MCU_SEL_M  (IO_MUX_GPIO35_MCU_SEL_V << IO_MUX_GPIO35_MCU_SEL_S)
+#define IO_MUX_GPIO35_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO35_MCU_SEL_S  12
+/** IO_MUX_GPIO35_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO35_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO35_FILTER_EN_M  (IO_MUX_GPIO35_FILTER_EN_V << IO_MUX_GPIO35_FILTER_EN_S)
+#define IO_MUX_GPIO35_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO35_FILTER_EN_S  15
+
+/** IO_MUX_gpio36_REG register
+ *  iomux control register for gpio36
+ */
+#define IO_MUX_GPIO36_REG (DR_REG_IO_MUX_BASE + 0x94)
+/** IO_MUX_GPIO36_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO36_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO36_MCU_OE_M  (IO_MUX_GPIO36_MCU_OE_V << IO_MUX_GPIO36_MCU_OE_S)
+#define IO_MUX_GPIO36_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO36_MCU_OE_S  0
+/** IO_MUX_GPIO36_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO36_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO36_SLP_SEL_M  (IO_MUX_GPIO36_SLP_SEL_V << IO_MUX_GPIO36_SLP_SEL_S)
+#define IO_MUX_GPIO36_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO36_SLP_SEL_S  1
+/** IO_MUX_GPIO36_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO36_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO36_MCU_WPD_M  (IO_MUX_GPIO36_MCU_WPD_V << IO_MUX_GPIO36_MCU_WPD_S)
+#define IO_MUX_GPIO36_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO36_MCU_WPD_S  2
+/** IO_MUX_GPIO36_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO36_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO36_MCU_WPU_M  (IO_MUX_GPIO36_MCU_WPU_V << IO_MUX_GPIO36_MCU_WPU_S)
+#define IO_MUX_GPIO36_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO36_MCU_WPU_S  3
+/** IO_MUX_GPIO36_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO36_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO36_MCU_IE_M  (IO_MUX_GPIO36_MCU_IE_V << IO_MUX_GPIO36_MCU_IE_S)
+#define IO_MUX_GPIO36_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO36_MCU_IE_S  4
+/** IO_MUX_GPIO36_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO36_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO36_MCU_DRV_M  (IO_MUX_GPIO36_MCU_DRV_V << IO_MUX_GPIO36_MCU_DRV_S)
+#define IO_MUX_GPIO36_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO36_MCU_DRV_S  5
+/** IO_MUX_GPIO36_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO36_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO36_FUN_WPD_M  (IO_MUX_GPIO36_FUN_WPD_V << IO_MUX_GPIO36_FUN_WPD_S)
+#define IO_MUX_GPIO36_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO36_FUN_WPD_S  7
+/** IO_MUX_GPIO36_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO36_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO36_FUN_WPU_M  (IO_MUX_GPIO36_FUN_WPU_V << IO_MUX_GPIO36_FUN_WPU_S)
+#define IO_MUX_GPIO36_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO36_FUN_WPU_S  8
+/** IO_MUX_GPIO36_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO36_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO36_FUN_IE_M  (IO_MUX_GPIO36_FUN_IE_V << IO_MUX_GPIO36_FUN_IE_S)
+#define IO_MUX_GPIO36_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO36_FUN_IE_S  9
+/** IO_MUX_GPIO36_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO36_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO36_FUN_DRV_M  (IO_MUX_GPIO36_FUN_DRV_V << IO_MUX_GPIO36_FUN_DRV_S)
+#define IO_MUX_GPIO36_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO36_FUN_DRV_S  10
+/** IO_MUX_GPIO36_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO36_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO36_MCU_SEL_M  (IO_MUX_GPIO36_MCU_SEL_V << IO_MUX_GPIO36_MCU_SEL_S)
+#define IO_MUX_GPIO36_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO36_MCU_SEL_S  12
+/** IO_MUX_GPIO36_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO36_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO36_FILTER_EN_M  (IO_MUX_GPIO36_FILTER_EN_V << IO_MUX_GPIO36_FILTER_EN_S)
+#define IO_MUX_GPIO36_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO36_FILTER_EN_S  15
+
+/** IO_MUX_gpio37_REG register
+ *  iomux control register for gpio37
+ */
+#define IO_MUX_GPIO37_REG (DR_REG_IO_MUX_BASE + 0x98)
+/** IO_MUX_GPIO37_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO37_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO37_MCU_OE_M  (IO_MUX_GPIO37_MCU_OE_V << IO_MUX_GPIO37_MCU_OE_S)
+#define IO_MUX_GPIO37_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO37_MCU_OE_S  0
+/** IO_MUX_GPIO37_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO37_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO37_SLP_SEL_M  (IO_MUX_GPIO37_SLP_SEL_V << IO_MUX_GPIO37_SLP_SEL_S)
+#define IO_MUX_GPIO37_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO37_SLP_SEL_S  1
+/** IO_MUX_GPIO37_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO37_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO37_MCU_WPD_M  (IO_MUX_GPIO37_MCU_WPD_V << IO_MUX_GPIO37_MCU_WPD_S)
+#define IO_MUX_GPIO37_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO37_MCU_WPD_S  2
+/** IO_MUX_GPIO37_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO37_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO37_MCU_WPU_M  (IO_MUX_GPIO37_MCU_WPU_V << IO_MUX_GPIO37_MCU_WPU_S)
+#define IO_MUX_GPIO37_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO37_MCU_WPU_S  3
+/** IO_MUX_GPIO37_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO37_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO37_MCU_IE_M  (IO_MUX_GPIO37_MCU_IE_V << IO_MUX_GPIO37_MCU_IE_S)
+#define IO_MUX_GPIO37_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO37_MCU_IE_S  4
+/** IO_MUX_GPIO37_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO37_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO37_MCU_DRV_M  (IO_MUX_GPIO37_MCU_DRV_V << IO_MUX_GPIO37_MCU_DRV_S)
+#define IO_MUX_GPIO37_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO37_MCU_DRV_S  5
+/** IO_MUX_GPIO37_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO37_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO37_FUN_WPD_M  (IO_MUX_GPIO37_FUN_WPD_V << IO_MUX_GPIO37_FUN_WPD_S)
+#define IO_MUX_GPIO37_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO37_FUN_WPD_S  7
+/** IO_MUX_GPIO37_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO37_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO37_FUN_WPU_M  (IO_MUX_GPIO37_FUN_WPU_V << IO_MUX_GPIO37_FUN_WPU_S)
+#define IO_MUX_GPIO37_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO37_FUN_WPU_S  8
+/** IO_MUX_GPIO37_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO37_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO37_FUN_IE_M  (IO_MUX_GPIO37_FUN_IE_V << IO_MUX_GPIO37_FUN_IE_S)
+#define IO_MUX_GPIO37_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO37_FUN_IE_S  9
+/** IO_MUX_GPIO37_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO37_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO37_FUN_DRV_M  (IO_MUX_GPIO37_FUN_DRV_V << IO_MUX_GPIO37_FUN_DRV_S)
+#define IO_MUX_GPIO37_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO37_FUN_DRV_S  10
+/** IO_MUX_GPIO37_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO37_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO37_MCU_SEL_M  (IO_MUX_GPIO37_MCU_SEL_V << IO_MUX_GPIO37_MCU_SEL_S)
+#define IO_MUX_GPIO37_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO37_MCU_SEL_S  12
+/** IO_MUX_GPIO37_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO37_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO37_FILTER_EN_M  (IO_MUX_GPIO37_FILTER_EN_V << IO_MUX_GPIO37_FILTER_EN_S)
+#define IO_MUX_GPIO37_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO37_FILTER_EN_S  15
+
+/** IO_MUX_gpio38_REG register
+ *  iomux control register for gpio38
+ */
+#define IO_MUX_GPIO38_REG (DR_REG_IO_MUX_BASE + 0x9c)
+/** IO_MUX_GPIO38_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO38_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO38_MCU_OE_M  (IO_MUX_GPIO38_MCU_OE_V << IO_MUX_GPIO38_MCU_OE_S)
+#define IO_MUX_GPIO38_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO38_MCU_OE_S  0
+/** IO_MUX_GPIO38_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO38_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO38_SLP_SEL_M  (IO_MUX_GPIO38_SLP_SEL_V << IO_MUX_GPIO38_SLP_SEL_S)
+#define IO_MUX_GPIO38_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO38_SLP_SEL_S  1
+/** IO_MUX_GPIO38_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO38_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO38_MCU_WPD_M  (IO_MUX_GPIO38_MCU_WPD_V << IO_MUX_GPIO38_MCU_WPD_S)
+#define IO_MUX_GPIO38_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO38_MCU_WPD_S  2
+/** IO_MUX_GPIO38_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO38_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO38_MCU_WPU_M  (IO_MUX_GPIO38_MCU_WPU_V << IO_MUX_GPIO38_MCU_WPU_S)
+#define IO_MUX_GPIO38_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO38_MCU_WPU_S  3
+/** IO_MUX_GPIO38_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO38_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO38_MCU_IE_M  (IO_MUX_GPIO38_MCU_IE_V << IO_MUX_GPIO38_MCU_IE_S)
+#define IO_MUX_GPIO38_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO38_MCU_IE_S  4
+/** IO_MUX_GPIO38_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO38_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO38_MCU_DRV_M  (IO_MUX_GPIO38_MCU_DRV_V << IO_MUX_GPIO38_MCU_DRV_S)
+#define IO_MUX_GPIO38_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO38_MCU_DRV_S  5
+/** IO_MUX_GPIO38_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO38_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO38_FUN_WPD_M  (IO_MUX_GPIO38_FUN_WPD_V << IO_MUX_GPIO38_FUN_WPD_S)
+#define IO_MUX_GPIO38_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO38_FUN_WPD_S  7
+/** IO_MUX_GPIO38_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO38_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO38_FUN_WPU_M  (IO_MUX_GPIO38_FUN_WPU_V << IO_MUX_GPIO38_FUN_WPU_S)
+#define IO_MUX_GPIO38_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO38_FUN_WPU_S  8
+/** IO_MUX_GPIO38_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO38_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO38_FUN_IE_M  (IO_MUX_GPIO38_FUN_IE_V << IO_MUX_GPIO38_FUN_IE_S)
+#define IO_MUX_GPIO38_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO38_FUN_IE_S  9
+/** IO_MUX_GPIO38_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO38_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO38_FUN_DRV_M  (IO_MUX_GPIO38_FUN_DRV_V << IO_MUX_GPIO38_FUN_DRV_S)
+#define IO_MUX_GPIO38_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO38_FUN_DRV_S  10
+/** IO_MUX_GPIO38_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO38_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO38_MCU_SEL_M  (IO_MUX_GPIO38_MCU_SEL_V << IO_MUX_GPIO38_MCU_SEL_S)
+#define IO_MUX_GPIO38_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO38_MCU_SEL_S  12
+/** IO_MUX_GPIO38_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO38_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO38_FILTER_EN_M  (IO_MUX_GPIO38_FILTER_EN_V << IO_MUX_GPIO38_FILTER_EN_S)
+#define IO_MUX_GPIO38_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO38_FILTER_EN_S  15
+
+/** IO_MUX_gpio39_REG register
+ *  iomux control register for gpio39
+ */
+#define IO_MUX_GPIO39_REG (DR_REG_IO_MUX_BASE + 0xa0)
+/** IO_MUX_GPIO39_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO39_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO39_MCU_OE_M  (IO_MUX_GPIO39_MCU_OE_V << IO_MUX_GPIO39_MCU_OE_S)
+#define IO_MUX_GPIO39_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO39_MCU_OE_S  0
+/** IO_MUX_GPIO39_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO39_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO39_SLP_SEL_M  (IO_MUX_GPIO39_SLP_SEL_V << IO_MUX_GPIO39_SLP_SEL_S)
+#define IO_MUX_GPIO39_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO39_SLP_SEL_S  1
+/** IO_MUX_GPIO39_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO39_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO39_MCU_WPD_M  (IO_MUX_GPIO39_MCU_WPD_V << IO_MUX_GPIO39_MCU_WPD_S)
+#define IO_MUX_GPIO39_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO39_MCU_WPD_S  2
+/** IO_MUX_GPIO39_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO39_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO39_MCU_WPU_M  (IO_MUX_GPIO39_MCU_WPU_V << IO_MUX_GPIO39_MCU_WPU_S)
+#define IO_MUX_GPIO39_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO39_MCU_WPU_S  3
+/** IO_MUX_GPIO39_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO39_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO39_MCU_IE_M  (IO_MUX_GPIO39_MCU_IE_V << IO_MUX_GPIO39_MCU_IE_S)
+#define IO_MUX_GPIO39_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO39_MCU_IE_S  4
+/** IO_MUX_GPIO39_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO39_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO39_MCU_DRV_M  (IO_MUX_GPIO39_MCU_DRV_V << IO_MUX_GPIO39_MCU_DRV_S)
+#define IO_MUX_GPIO39_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO39_MCU_DRV_S  5
+/** IO_MUX_GPIO39_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO39_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO39_FUN_WPD_M  (IO_MUX_GPIO39_FUN_WPD_V << IO_MUX_GPIO39_FUN_WPD_S)
+#define IO_MUX_GPIO39_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO39_FUN_WPD_S  7
+/** IO_MUX_GPIO39_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO39_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO39_FUN_WPU_M  (IO_MUX_GPIO39_FUN_WPU_V << IO_MUX_GPIO39_FUN_WPU_S)
+#define IO_MUX_GPIO39_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO39_FUN_WPU_S  8
+/** IO_MUX_GPIO39_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO39_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO39_FUN_IE_M  (IO_MUX_GPIO39_FUN_IE_V << IO_MUX_GPIO39_FUN_IE_S)
+#define IO_MUX_GPIO39_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO39_FUN_IE_S  9
+/** IO_MUX_GPIO39_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO39_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO39_FUN_DRV_M  (IO_MUX_GPIO39_FUN_DRV_V << IO_MUX_GPIO39_FUN_DRV_S)
+#define IO_MUX_GPIO39_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO39_FUN_DRV_S  10
+/** IO_MUX_GPIO39_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO39_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO39_MCU_SEL_M  (IO_MUX_GPIO39_MCU_SEL_V << IO_MUX_GPIO39_MCU_SEL_S)
+#define IO_MUX_GPIO39_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO39_MCU_SEL_S  12
+/** IO_MUX_GPIO39_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO39_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO39_FILTER_EN_M  (IO_MUX_GPIO39_FILTER_EN_V << IO_MUX_GPIO39_FILTER_EN_S)
+#define IO_MUX_GPIO39_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO39_FILTER_EN_S  15
+
+/** IO_MUX_gpio40_REG register
+ *  iomux control register for gpio40
+ */
+#define IO_MUX_GPIO40_REG (DR_REG_IO_MUX_BASE + 0xa4)
+/** IO_MUX_GPIO40_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO40_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO40_MCU_OE_M  (IO_MUX_GPIO40_MCU_OE_V << IO_MUX_GPIO40_MCU_OE_S)
+#define IO_MUX_GPIO40_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO40_MCU_OE_S  0
+/** IO_MUX_GPIO40_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO40_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO40_SLP_SEL_M  (IO_MUX_GPIO40_SLP_SEL_V << IO_MUX_GPIO40_SLP_SEL_S)
+#define IO_MUX_GPIO40_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO40_SLP_SEL_S  1
+/** IO_MUX_GPIO40_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO40_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO40_MCU_WPD_M  (IO_MUX_GPIO40_MCU_WPD_V << IO_MUX_GPIO40_MCU_WPD_S)
+#define IO_MUX_GPIO40_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO40_MCU_WPD_S  2
+/** IO_MUX_GPIO40_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO40_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO40_MCU_WPU_M  (IO_MUX_GPIO40_MCU_WPU_V << IO_MUX_GPIO40_MCU_WPU_S)
+#define IO_MUX_GPIO40_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO40_MCU_WPU_S  3
+/** IO_MUX_GPIO40_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO40_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO40_MCU_IE_M  (IO_MUX_GPIO40_MCU_IE_V << IO_MUX_GPIO40_MCU_IE_S)
+#define IO_MUX_GPIO40_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO40_MCU_IE_S  4
+/** IO_MUX_GPIO40_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO40_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO40_MCU_DRV_M  (IO_MUX_GPIO40_MCU_DRV_V << IO_MUX_GPIO40_MCU_DRV_S)
+#define IO_MUX_GPIO40_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO40_MCU_DRV_S  5
+/** IO_MUX_GPIO40_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO40_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO40_FUN_WPD_M  (IO_MUX_GPIO40_FUN_WPD_V << IO_MUX_GPIO40_FUN_WPD_S)
+#define IO_MUX_GPIO40_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO40_FUN_WPD_S  7
+/** IO_MUX_GPIO40_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO40_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO40_FUN_WPU_M  (IO_MUX_GPIO40_FUN_WPU_V << IO_MUX_GPIO40_FUN_WPU_S)
+#define IO_MUX_GPIO40_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO40_FUN_WPU_S  8
+/** IO_MUX_GPIO40_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO40_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO40_FUN_IE_M  (IO_MUX_GPIO40_FUN_IE_V << IO_MUX_GPIO40_FUN_IE_S)
+#define IO_MUX_GPIO40_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO40_FUN_IE_S  9
+/** IO_MUX_GPIO40_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO40_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO40_FUN_DRV_M  (IO_MUX_GPIO40_FUN_DRV_V << IO_MUX_GPIO40_FUN_DRV_S)
+#define IO_MUX_GPIO40_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO40_FUN_DRV_S  10
+/** IO_MUX_GPIO40_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO40_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO40_MCU_SEL_M  (IO_MUX_GPIO40_MCU_SEL_V << IO_MUX_GPIO40_MCU_SEL_S)
+#define IO_MUX_GPIO40_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO40_MCU_SEL_S  12
+/** IO_MUX_GPIO40_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO40_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO40_FILTER_EN_M  (IO_MUX_GPIO40_FILTER_EN_V << IO_MUX_GPIO40_FILTER_EN_S)
+#define IO_MUX_GPIO40_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO40_FILTER_EN_S  15
+
+/** IO_MUX_gpio41_REG register
+ *  iomux control register for gpio41
+ */
+#define IO_MUX_GPIO41_REG (DR_REG_IO_MUX_BASE + 0xa8)
+/** IO_MUX_GPIO41_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO41_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO41_MCU_OE_M  (IO_MUX_GPIO41_MCU_OE_V << IO_MUX_GPIO41_MCU_OE_S)
+#define IO_MUX_GPIO41_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO41_MCU_OE_S  0
+/** IO_MUX_GPIO41_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO41_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO41_SLP_SEL_M  (IO_MUX_GPIO41_SLP_SEL_V << IO_MUX_GPIO41_SLP_SEL_S)
+#define IO_MUX_GPIO41_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO41_SLP_SEL_S  1
+/** IO_MUX_GPIO41_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO41_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO41_MCU_WPD_M  (IO_MUX_GPIO41_MCU_WPD_V << IO_MUX_GPIO41_MCU_WPD_S)
+#define IO_MUX_GPIO41_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO41_MCU_WPD_S  2
+/** IO_MUX_GPIO41_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO41_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO41_MCU_WPU_M  (IO_MUX_GPIO41_MCU_WPU_V << IO_MUX_GPIO41_MCU_WPU_S)
+#define IO_MUX_GPIO41_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO41_MCU_WPU_S  3
+/** IO_MUX_GPIO41_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO41_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO41_MCU_IE_M  (IO_MUX_GPIO41_MCU_IE_V << IO_MUX_GPIO41_MCU_IE_S)
+#define IO_MUX_GPIO41_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO41_MCU_IE_S  4
+/** IO_MUX_GPIO41_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO41_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO41_MCU_DRV_M  (IO_MUX_GPIO41_MCU_DRV_V << IO_MUX_GPIO41_MCU_DRV_S)
+#define IO_MUX_GPIO41_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO41_MCU_DRV_S  5
+/** IO_MUX_GPIO41_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO41_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO41_FUN_WPD_M  (IO_MUX_GPIO41_FUN_WPD_V << IO_MUX_GPIO41_FUN_WPD_S)
+#define IO_MUX_GPIO41_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO41_FUN_WPD_S  7
+/** IO_MUX_GPIO41_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO41_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO41_FUN_WPU_M  (IO_MUX_GPIO41_FUN_WPU_V << IO_MUX_GPIO41_FUN_WPU_S)
+#define IO_MUX_GPIO41_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO41_FUN_WPU_S  8
+/** IO_MUX_GPIO41_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO41_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO41_FUN_IE_M  (IO_MUX_GPIO41_FUN_IE_V << IO_MUX_GPIO41_FUN_IE_S)
+#define IO_MUX_GPIO41_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO41_FUN_IE_S  9
+/** IO_MUX_GPIO41_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO41_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO41_FUN_DRV_M  (IO_MUX_GPIO41_FUN_DRV_V << IO_MUX_GPIO41_FUN_DRV_S)
+#define IO_MUX_GPIO41_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO41_FUN_DRV_S  10
+/** IO_MUX_GPIO41_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO41_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO41_MCU_SEL_M  (IO_MUX_GPIO41_MCU_SEL_V << IO_MUX_GPIO41_MCU_SEL_S)
+#define IO_MUX_GPIO41_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO41_MCU_SEL_S  12
+/** IO_MUX_GPIO41_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO41_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO41_FILTER_EN_M  (IO_MUX_GPIO41_FILTER_EN_V << IO_MUX_GPIO41_FILTER_EN_S)
+#define IO_MUX_GPIO41_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO41_FILTER_EN_S  15
+
+/** IO_MUX_gpio42_REG register
+ *  iomux control register for gpio42
+ */
+#define IO_MUX_GPIO42_REG (DR_REG_IO_MUX_BASE + 0xac)
+/** IO_MUX_GPIO42_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO42_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO42_MCU_OE_M  (IO_MUX_GPIO42_MCU_OE_V << IO_MUX_GPIO42_MCU_OE_S)
+#define IO_MUX_GPIO42_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO42_MCU_OE_S  0
+/** IO_MUX_GPIO42_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO42_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO42_SLP_SEL_M  (IO_MUX_GPIO42_SLP_SEL_V << IO_MUX_GPIO42_SLP_SEL_S)
+#define IO_MUX_GPIO42_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO42_SLP_SEL_S  1
+/** IO_MUX_GPIO42_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO42_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO42_MCU_WPD_M  (IO_MUX_GPIO42_MCU_WPD_V << IO_MUX_GPIO42_MCU_WPD_S)
+#define IO_MUX_GPIO42_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO42_MCU_WPD_S  2
+/** IO_MUX_GPIO42_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO42_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO42_MCU_WPU_M  (IO_MUX_GPIO42_MCU_WPU_V << IO_MUX_GPIO42_MCU_WPU_S)
+#define IO_MUX_GPIO42_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO42_MCU_WPU_S  3
+/** IO_MUX_GPIO42_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO42_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO42_MCU_IE_M  (IO_MUX_GPIO42_MCU_IE_V << IO_MUX_GPIO42_MCU_IE_S)
+#define IO_MUX_GPIO42_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO42_MCU_IE_S  4
+/** IO_MUX_GPIO42_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO42_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO42_MCU_DRV_M  (IO_MUX_GPIO42_MCU_DRV_V << IO_MUX_GPIO42_MCU_DRV_S)
+#define IO_MUX_GPIO42_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO42_MCU_DRV_S  5
+/** IO_MUX_GPIO42_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO42_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO42_FUN_WPD_M  (IO_MUX_GPIO42_FUN_WPD_V << IO_MUX_GPIO42_FUN_WPD_S)
+#define IO_MUX_GPIO42_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO42_FUN_WPD_S  7
+/** IO_MUX_GPIO42_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO42_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO42_FUN_WPU_M  (IO_MUX_GPIO42_FUN_WPU_V << IO_MUX_GPIO42_FUN_WPU_S)
+#define IO_MUX_GPIO42_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO42_FUN_WPU_S  8
+/** IO_MUX_GPIO42_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO42_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO42_FUN_IE_M  (IO_MUX_GPIO42_FUN_IE_V << IO_MUX_GPIO42_FUN_IE_S)
+#define IO_MUX_GPIO42_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO42_FUN_IE_S  9
+/** IO_MUX_GPIO42_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO42_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO42_FUN_DRV_M  (IO_MUX_GPIO42_FUN_DRV_V << IO_MUX_GPIO42_FUN_DRV_S)
+#define IO_MUX_GPIO42_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO42_FUN_DRV_S  10
+/** IO_MUX_GPIO42_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO42_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO42_MCU_SEL_M  (IO_MUX_GPIO42_MCU_SEL_V << IO_MUX_GPIO42_MCU_SEL_S)
+#define IO_MUX_GPIO42_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO42_MCU_SEL_S  12
+/** IO_MUX_GPIO42_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO42_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO42_FILTER_EN_M  (IO_MUX_GPIO42_FILTER_EN_V << IO_MUX_GPIO42_FILTER_EN_S)
+#define IO_MUX_GPIO42_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO42_FILTER_EN_S  15
+
+/** IO_MUX_gpio43_REG register
+ *  iomux control register for gpio43
+ */
+#define IO_MUX_GPIO43_REG (DR_REG_IO_MUX_BASE + 0xb0)
+/** IO_MUX_GPIO43_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO43_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO43_MCU_OE_M  (IO_MUX_GPIO43_MCU_OE_V << IO_MUX_GPIO43_MCU_OE_S)
+#define IO_MUX_GPIO43_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO43_MCU_OE_S  0
+/** IO_MUX_GPIO43_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO43_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO43_SLP_SEL_M  (IO_MUX_GPIO43_SLP_SEL_V << IO_MUX_GPIO43_SLP_SEL_S)
+#define IO_MUX_GPIO43_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO43_SLP_SEL_S  1
+/** IO_MUX_GPIO43_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO43_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO43_MCU_WPD_M  (IO_MUX_GPIO43_MCU_WPD_V << IO_MUX_GPIO43_MCU_WPD_S)
+#define IO_MUX_GPIO43_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO43_MCU_WPD_S  2
+/** IO_MUX_GPIO43_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO43_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO43_MCU_WPU_M  (IO_MUX_GPIO43_MCU_WPU_V << IO_MUX_GPIO43_MCU_WPU_S)
+#define IO_MUX_GPIO43_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO43_MCU_WPU_S  3
+/** IO_MUX_GPIO43_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO43_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO43_MCU_IE_M  (IO_MUX_GPIO43_MCU_IE_V << IO_MUX_GPIO43_MCU_IE_S)
+#define IO_MUX_GPIO43_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO43_MCU_IE_S  4
+/** IO_MUX_GPIO43_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO43_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO43_MCU_DRV_M  (IO_MUX_GPIO43_MCU_DRV_V << IO_MUX_GPIO43_MCU_DRV_S)
+#define IO_MUX_GPIO43_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO43_MCU_DRV_S  5
+/** IO_MUX_GPIO43_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO43_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO43_FUN_WPD_M  (IO_MUX_GPIO43_FUN_WPD_V << IO_MUX_GPIO43_FUN_WPD_S)
+#define IO_MUX_GPIO43_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO43_FUN_WPD_S  7
+/** IO_MUX_GPIO43_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO43_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO43_FUN_WPU_M  (IO_MUX_GPIO43_FUN_WPU_V << IO_MUX_GPIO43_FUN_WPU_S)
+#define IO_MUX_GPIO43_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO43_FUN_WPU_S  8
+/** IO_MUX_GPIO43_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO43_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO43_FUN_IE_M  (IO_MUX_GPIO43_FUN_IE_V << IO_MUX_GPIO43_FUN_IE_S)
+#define IO_MUX_GPIO43_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO43_FUN_IE_S  9
+/** IO_MUX_GPIO43_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO43_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO43_FUN_DRV_M  (IO_MUX_GPIO43_FUN_DRV_V << IO_MUX_GPIO43_FUN_DRV_S)
+#define IO_MUX_GPIO43_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO43_FUN_DRV_S  10
+/** IO_MUX_GPIO43_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO43_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO43_MCU_SEL_M  (IO_MUX_GPIO43_MCU_SEL_V << IO_MUX_GPIO43_MCU_SEL_S)
+#define IO_MUX_GPIO43_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO43_MCU_SEL_S  12
+/** IO_MUX_GPIO43_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO43_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO43_FILTER_EN_M  (IO_MUX_GPIO43_FILTER_EN_V << IO_MUX_GPIO43_FILTER_EN_S)
+#define IO_MUX_GPIO43_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO43_FILTER_EN_S  15
+
+/** IO_MUX_gpio44_REG register
+ *  iomux control register for gpio44
+ */
+#define IO_MUX_GPIO44_REG (DR_REG_IO_MUX_BASE + 0xb4)
+/** IO_MUX_GPIO44_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO44_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO44_MCU_OE_M  (IO_MUX_GPIO44_MCU_OE_V << IO_MUX_GPIO44_MCU_OE_S)
+#define IO_MUX_GPIO44_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO44_MCU_OE_S  0
+/** IO_MUX_GPIO44_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO44_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO44_SLP_SEL_M  (IO_MUX_GPIO44_SLP_SEL_V << IO_MUX_GPIO44_SLP_SEL_S)
+#define IO_MUX_GPIO44_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO44_SLP_SEL_S  1
+/** IO_MUX_GPIO44_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO44_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO44_MCU_WPD_M  (IO_MUX_GPIO44_MCU_WPD_V << IO_MUX_GPIO44_MCU_WPD_S)
+#define IO_MUX_GPIO44_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO44_MCU_WPD_S  2
+/** IO_MUX_GPIO44_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO44_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO44_MCU_WPU_M  (IO_MUX_GPIO44_MCU_WPU_V << IO_MUX_GPIO44_MCU_WPU_S)
+#define IO_MUX_GPIO44_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO44_MCU_WPU_S  3
+/** IO_MUX_GPIO44_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO44_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO44_MCU_IE_M  (IO_MUX_GPIO44_MCU_IE_V << IO_MUX_GPIO44_MCU_IE_S)
+#define IO_MUX_GPIO44_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO44_MCU_IE_S  4
+/** IO_MUX_GPIO44_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO44_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO44_MCU_DRV_M  (IO_MUX_GPIO44_MCU_DRV_V << IO_MUX_GPIO44_MCU_DRV_S)
+#define IO_MUX_GPIO44_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO44_MCU_DRV_S  5
+/** IO_MUX_GPIO44_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO44_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO44_FUN_WPD_M  (IO_MUX_GPIO44_FUN_WPD_V << IO_MUX_GPIO44_FUN_WPD_S)
+#define IO_MUX_GPIO44_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO44_FUN_WPD_S  7
+/** IO_MUX_GPIO44_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO44_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO44_FUN_WPU_M  (IO_MUX_GPIO44_FUN_WPU_V << IO_MUX_GPIO44_FUN_WPU_S)
+#define IO_MUX_GPIO44_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO44_FUN_WPU_S  8
+/** IO_MUX_GPIO44_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO44_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO44_FUN_IE_M  (IO_MUX_GPIO44_FUN_IE_V << IO_MUX_GPIO44_FUN_IE_S)
+#define IO_MUX_GPIO44_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO44_FUN_IE_S  9
+/** IO_MUX_GPIO44_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO44_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO44_FUN_DRV_M  (IO_MUX_GPIO44_FUN_DRV_V << IO_MUX_GPIO44_FUN_DRV_S)
+#define IO_MUX_GPIO44_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO44_FUN_DRV_S  10
+/** IO_MUX_GPIO44_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO44_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO44_MCU_SEL_M  (IO_MUX_GPIO44_MCU_SEL_V << IO_MUX_GPIO44_MCU_SEL_S)
+#define IO_MUX_GPIO44_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO44_MCU_SEL_S  12
+/** IO_MUX_GPIO44_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO44_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO44_FILTER_EN_M  (IO_MUX_GPIO44_FILTER_EN_V << IO_MUX_GPIO44_FILTER_EN_S)
+#define IO_MUX_GPIO44_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO44_FILTER_EN_S  15
+
+/** IO_MUX_gpio45_REG register
+ *  iomux control register for gpio45
+ */
+#define IO_MUX_GPIO45_REG (DR_REG_IO_MUX_BASE + 0xb8)
+/** IO_MUX_GPIO45_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO45_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO45_MCU_OE_M  (IO_MUX_GPIO45_MCU_OE_V << IO_MUX_GPIO45_MCU_OE_S)
+#define IO_MUX_GPIO45_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO45_MCU_OE_S  0
+/** IO_MUX_GPIO45_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO45_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO45_SLP_SEL_M  (IO_MUX_GPIO45_SLP_SEL_V << IO_MUX_GPIO45_SLP_SEL_S)
+#define IO_MUX_GPIO45_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO45_SLP_SEL_S  1
+/** IO_MUX_GPIO45_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO45_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO45_MCU_WPD_M  (IO_MUX_GPIO45_MCU_WPD_V << IO_MUX_GPIO45_MCU_WPD_S)
+#define IO_MUX_GPIO45_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO45_MCU_WPD_S  2
+/** IO_MUX_GPIO45_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO45_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO45_MCU_WPU_M  (IO_MUX_GPIO45_MCU_WPU_V << IO_MUX_GPIO45_MCU_WPU_S)
+#define IO_MUX_GPIO45_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO45_MCU_WPU_S  3
+/** IO_MUX_GPIO45_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO45_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO45_MCU_IE_M  (IO_MUX_GPIO45_MCU_IE_V << IO_MUX_GPIO45_MCU_IE_S)
+#define IO_MUX_GPIO45_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO45_MCU_IE_S  4
+/** IO_MUX_GPIO45_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO45_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO45_MCU_DRV_M  (IO_MUX_GPIO45_MCU_DRV_V << IO_MUX_GPIO45_MCU_DRV_S)
+#define IO_MUX_GPIO45_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO45_MCU_DRV_S  5
+/** IO_MUX_GPIO45_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO45_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO45_FUN_WPD_M  (IO_MUX_GPIO45_FUN_WPD_V << IO_MUX_GPIO45_FUN_WPD_S)
+#define IO_MUX_GPIO45_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO45_FUN_WPD_S  7
+/** IO_MUX_GPIO45_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO45_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO45_FUN_WPU_M  (IO_MUX_GPIO45_FUN_WPU_V << IO_MUX_GPIO45_FUN_WPU_S)
+#define IO_MUX_GPIO45_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO45_FUN_WPU_S  8
+/** IO_MUX_GPIO45_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO45_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO45_FUN_IE_M  (IO_MUX_GPIO45_FUN_IE_V << IO_MUX_GPIO45_FUN_IE_S)
+#define IO_MUX_GPIO45_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO45_FUN_IE_S  9
+/** IO_MUX_GPIO45_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO45_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO45_FUN_DRV_M  (IO_MUX_GPIO45_FUN_DRV_V << IO_MUX_GPIO45_FUN_DRV_S)
+#define IO_MUX_GPIO45_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO45_FUN_DRV_S  10
+/** IO_MUX_GPIO45_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO45_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO45_MCU_SEL_M  (IO_MUX_GPIO45_MCU_SEL_V << IO_MUX_GPIO45_MCU_SEL_S)
+#define IO_MUX_GPIO45_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO45_MCU_SEL_S  12
+/** IO_MUX_GPIO45_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO45_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO45_FILTER_EN_M  (IO_MUX_GPIO45_FILTER_EN_V << IO_MUX_GPIO45_FILTER_EN_S)
+#define IO_MUX_GPIO45_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO45_FILTER_EN_S  15
+
+/** IO_MUX_gpio46_REG register
+ *  iomux control register for gpio46
+ */
+#define IO_MUX_GPIO46_REG (DR_REG_IO_MUX_BASE + 0xbc)
+/** IO_MUX_GPIO46_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO46_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO46_MCU_OE_M  (IO_MUX_GPIO46_MCU_OE_V << IO_MUX_GPIO46_MCU_OE_S)
+#define IO_MUX_GPIO46_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO46_MCU_OE_S  0
+/** IO_MUX_GPIO46_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO46_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO46_SLP_SEL_M  (IO_MUX_GPIO46_SLP_SEL_V << IO_MUX_GPIO46_SLP_SEL_S)
+#define IO_MUX_GPIO46_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO46_SLP_SEL_S  1
+/** IO_MUX_GPIO46_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO46_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO46_MCU_WPD_M  (IO_MUX_GPIO46_MCU_WPD_V << IO_MUX_GPIO46_MCU_WPD_S)
+#define IO_MUX_GPIO46_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO46_MCU_WPD_S  2
+/** IO_MUX_GPIO46_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO46_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO46_MCU_WPU_M  (IO_MUX_GPIO46_MCU_WPU_V << IO_MUX_GPIO46_MCU_WPU_S)
+#define IO_MUX_GPIO46_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO46_MCU_WPU_S  3
+/** IO_MUX_GPIO46_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO46_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO46_MCU_IE_M  (IO_MUX_GPIO46_MCU_IE_V << IO_MUX_GPIO46_MCU_IE_S)
+#define IO_MUX_GPIO46_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO46_MCU_IE_S  4
+/** IO_MUX_GPIO46_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO46_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO46_MCU_DRV_M  (IO_MUX_GPIO46_MCU_DRV_V << IO_MUX_GPIO46_MCU_DRV_S)
+#define IO_MUX_GPIO46_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO46_MCU_DRV_S  5
+/** IO_MUX_GPIO46_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO46_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO46_FUN_WPD_M  (IO_MUX_GPIO46_FUN_WPD_V << IO_MUX_GPIO46_FUN_WPD_S)
+#define IO_MUX_GPIO46_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO46_FUN_WPD_S  7
+/** IO_MUX_GPIO46_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO46_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO46_FUN_WPU_M  (IO_MUX_GPIO46_FUN_WPU_V << IO_MUX_GPIO46_FUN_WPU_S)
+#define IO_MUX_GPIO46_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO46_FUN_WPU_S  8
+/** IO_MUX_GPIO46_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO46_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO46_FUN_IE_M  (IO_MUX_GPIO46_FUN_IE_V << IO_MUX_GPIO46_FUN_IE_S)
+#define IO_MUX_GPIO46_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO46_FUN_IE_S  9
+/** IO_MUX_GPIO46_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO46_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO46_FUN_DRV_M  (IO_MUX_GPIO46_FUN_DRV_V << IO_MUX_GPIO46_FUN_DRV_S)
+#define IO_MUX_GPIO46_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO46_FUN_DRV_S  10
+/** IO_MUX_GPIO46_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO46_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO46_MCU_SEL_M  (IO_MUX_GPIO46_MCU_SEL_V << IO_MUX_GPIO46_MCU_SEL_S)
+#define IO_MUX_GPIO46_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO46_MCU_SEL_S  12
+/** IO_MUX_GPIO46_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO46_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO46_FILTER_EN_M  (IO_MUX_GPIO46_FILTER_EN_V << IO_MUX_GPIO46_FILTER_EN_S)
+#define IO_MUX_GPIO46_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO46_FILTER_EN_S  15
+
+/** IO_MUX_gpio47_REG register
+ *  iomux control register for gpio47
+ */
+#define IO_MUX_GPIO47_REG (DR_REG_IO_MUX_BASE + 0xc0)
+/** IO_MUX_GPIO47_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO47_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO47_MCU_OE_M  (IO_MUX_GPIO47_MCU_OE_V << IO_MUX_GPIO47_MCU_OE_S)
+#define IO_MUX_GPIO47_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO47_MCU_OE_S  0
+/** IO_MUX_GPIO47_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO47_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO47_SLP_SEL_M  (IO_MUX_GPIO47_SLP_SEL_V << IO_MUX_GPIO47_SLP_SEL_S)
+#define IO_MUX_GPIO47_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO47_SLP_SEL_S  1
+/** IO_MUX_GPIO47_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO47_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO47_MCU_WPD_M  (IO_MUX_GPIO47_MCU_WPD_V << IO_MUX_GPIO47_MCU_WPD_S)
+#define IO_MUX_GPIO47_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO47_MCU_WPD_S  2
+/** IO_MUX_GPIO47_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO47_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO47_MCU_WPU_M  (IO_MUX_GPIO47_MCU_WPU_V << IO_MUX_GPIO47_MCU_WPU_S)
+#define IO_MUX_GPIO47_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO47_MCU_WPU_S  3
+/** IO_MUX_GPIO47_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO47_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO47_MCU_IE_M  (IO_MUX_GPIO47_MCU_IE_V << IO_MUX_GPIO47_MCU_IE_S)
+#define IO_MUX_GPIO47_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO47_MCU_IE_S  4
+/** IO_MUX_GPIO47_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO47_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO47_MCU_DRV_M  (IO_MUX_GPIO47_MCU_DRV_V << IO_MUX_GPIO47_MCU_DRV_S)
+#define IO_MUX_GPIO47_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO47_MCU_DRV_S  5
+/** IO_MUX_GPIO47_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO47_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO47_FUN_WPD_M  (IO_MUX_GPIO47_FUN_WPD_V << IO_MUX_GPIO47_FUN_WPD_S)
+#define IO_MUX_GPIO47_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO47_FUN_WPD_S  7
+/** IO_MUX_GPIO47_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO47_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO47_FUN_WPU_M  (IO_MUX_GPIO47_FUN_WPU_V << IO_MUX_GPIO47_FUN_WPU_S)
+#define IO_MUX_GPIO47_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO47_FUN_WPU_S  8
+/** IO_MUX_GPIO47_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO47_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO47_FUN_IE_M  (IO_MUX_GPIO47_FUN_IE_V << IO_MUX_GPIO47_FUN_IE_S)
+#define IO_MUX_GPIO47_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO47_FUN_IE_S  9
+/** IO_MUX_GPIO47_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO47_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO47_FUN_DRV_M  (IO_MUX_GPIO47_FUN_DRV_V << IO_MUX_GPIO47_FUN_DRV_S)
+#define IO_MUX_GPIO47_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO47_FUN_DRV_S  10
+/** IO_MUX_GPIO47_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO47_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO47_MCU_SEL_M  (IO_MUX_GPIO47_MCU_SEL_V << IO_MUX_GPIO47_MCU_SEL_S)
+#define IO_MUX_GPIO47_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO47_MCU_SEL_S  12
+/** IO_MUX_GPIO47_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO47_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO47_FILTER_EN_M  (IO_MUX_GPIO47_FILTER_EN_V << IO_MUX_GPIO47_FILTER_EN_S)
+#define IO_MUX_GPIO47_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO47_FILTER_EN_S  15
+
+/** IO_MUX_gpio48_REG register
+ *  iomux control register for gpio48
+ */
+#define IO_MUX_GPIO48_REG (DR_REG_IO_MUX_BASE + 0xc4)
+/** IO_MUX_GPIO48_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO48_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO48_MCU_OE_M  (IO_MUX_GPIO48_MCU_OE_V << IO_MUX_GPIO48_MCU_OE_S)
+#define IO_MUX_GPIO48_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO48_MCU_OE_S  0
+/** IO_MUX_GPIO48_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO48_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO48_SLP_SEL_M  (IO_MUX_GPIO48_SLP_SEL_V << IO_MUX_GPIO48_SLP_SEL_S)
+#define IO_MUX_GPIO48_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO48_SLP_SEL_S  1
+/** IO_MUX_GPIO48_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO48_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO48_MCU_WPD_M  (IO_MUX_GPIO48_MCU_WPD_V << IO_MUX_GPIO48_MCU_WPD_S)
+#define IO_MUX_GPIO48_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO48_MCU_WPD_S  2
+/** IO_MUX_GPIO48_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO48_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO48_MCU_WPU_M  (IO_MUX_GPIO48_MCU_WPU_V << IO_MUX_GPIO48_MCU_WPU_S)
+#define IO_MUX_GPIO48_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO48_MCU_WPU_S  3
+/** IO_MUX_GPIO48_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO48_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO48_MCU_IE_M  (IO_MUX_GPIO48_MCU_IE_V << IO_MUX_GPIO48_MCU_IE_S)
+#define IO_MUX_GPIO48_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO48_MCU_IE_S  4
+/** IO_MUX_GPIO48_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO48_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO48_MCU_DRV_M  (IO_MUX_GPIO48_MCU_DRV_V << IO_MUX_GPIO48_MCU_DRV_S)
+#define IO_MUX_GPIO48_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO48_MCU_DRV_S  5
+/** IO_MUX_GPIO48_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO48_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO48_FUN_WPD_M  (IO_MUX_GPIO48_FUN_WPD_V << IO_MUX_GPIO48_FUN_WPD_S)
+#define IO_MUX_GPIO48_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO48_FUN_WPD_S  7
+/** IO_MUX_GPIO48_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO48_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO48_FUN_WPU_M  (IO_MUX_GPIO48_FUN_WPU_V << IO_MUX_GPIO48_FUN_WPU_S)
+#define IO_MUX_GPIO48_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO48_FUN_WPU_S  8
+/** IO_MUX_GPIO48_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO48_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO48_FUN_IE_M  (IO_MUX_GPIO48_FUN_IE_V << IO_MUX_GPIO48_FUN_IE_S)
+#define IO_MUX_GPIO48_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO48_FUN_IE_S  9
+/** IO_MUX_GPIO48_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO48_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO48_FUN_DRV_M  (IO_MUX_GPIO48_FUN_DRV_V << IO_MUX_GPIO48_FUN_DRV_S)
+#define IO_MUX_GPIO48_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO48_FUN_DRV_S  10
+/** IO_MUX_GPIO48_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO48_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO48_MCU_SEL_M  (IO_MUX_GPIO48_MCU_SEL_V << IO_MUX_GPIO48_MCU_SEL_S)
+#define IO_MUX_GPIO48_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO48_MCU_SEL_S  12
+/** IO_MUX_GPIO48_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO48_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO48_FILTER_EN_M  (IO_MUX_GPIO48_FILTER_EN_V << IO_MUX_GPIO48_FILTER_EN_S)
+#define IO_MUX_GPIO48_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO48_FILTER_EN_S  15
+
+/** IO_MUX_gpio49_REG register
+ *  iomux control register for gpio49
+ */
+#define IO_MUX_GPIO49_REG (DR_REG_IO_MUX_BASE + 0xc8)
+/** IO_MUX_GPIO49_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO49_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO49_MCU_OE_M  (IO_MUX_GPIO49_MCU_OE_V << IO_MUX_GPIO49_MCU_OE_S)
+#define IO_MUX_GPIO49_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO49_MCU_OE_S  0
+/** IO_MUX_GPIO49_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO49_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO49_SLP_SEL_M  (IO_MUX_GPIO49_SLP_SEL_V << IO_MUX_GPIO49_SLP_SEL_S)
+#define IO_MUX_GPIO49_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO49_SLP_SEL_S  1
+/** IO_MUX_GPIO49_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO49_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO49_MCU_WPD_M  (IO_MUX_GPIO49_MCU_WPD_V << IO_MUX_GPIO49_MCU_WPD_S)
+#define IO_MUX_GPIO49_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO49_MCU_WPD_S  2
+/** IO_MUX_GPIO49_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO49_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO49_MCU_WPU_M  (IO_MUX_GPIO49_MCU_WPU_V << IO_MUX_GPIO49_MCU_WPU_S)
+#define IO_MUX_GPIO49_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO49_MCU_WPU_S  3
+/** IO_MUX_GPIO49_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO49_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO49_MCU_IE_M  (IO_MUX_GPIO49_MCU_IE_V << IO_MUX_GPIO49_MCU_IE_S)
+#define IO_MUX_GPIO49_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO49_MCU_IE_S  4
+/** IO_MUX_GPIO49_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO49_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO49_MCU_DRV_M  (IO_MUX_GPIO49_MCU_DRV_V << IO_MUX_GPIO49_MCU_DRV_S)
+#define IO_MUX_GPIO49_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO49_MCU_DRV_S  5
+/** IO_MUX_GPIO49_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO49_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO49_FUN_WPD_M  (IO_MUX_GPIO49_FUN_WPD_V << IO_MUX_GPIO49_FUN_WPD_S)
+#define IO_MUX_GPIO49_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO49_FUN_WPD_S  7
+/** IO_MUX_GPIO49_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO49_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO49_FUN_WPU_M  (IO_MUX_GPIO49_FUN_WPU_V << IO_MUX_GPIO49_FUN_WPU_S)
+#define IO_MUX_GPIO49_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO49_FUN_WPU_S  8
+/** IO_MUX_GPIO49_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO49_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO49_FUN_IE_M  (IO_MUX_GPIO49_FUN_IE_V << IO_MUX_GPIO49_FUN_IE_S)
+#define IO_MUX_GPIO49_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO49_FUN_IE_S  9
+/** IO_MUX_GPIO49_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO49_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO49_FUN_DRV_M  (IO_MUX_GPIO49_FUN_DRV_V << IO_MUX_GPIO49_FUN_DRV_S)
+#define IO_MUX_GPIO49_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO49_FUN_DRV_S  10
+/** IO_MUX_GPIO49_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO49_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO49_MCU_SEL_M  (IO_MUX_GPIO49_MCU_SEL_V << IO_MUX_GPIO49_MCU_SEL_S)
+#define IO_MUX_GPIO49_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO49_MCU_SEL_S  12
+/** IO_MUX_GPIO49_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO49_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO49_FILTER_EN_M  (IO_MUX_GPIO49_FILTER_EN_V << IO_MUX_GPIO49_FILTER_EN_S)
+#define IO_MUX_GPIO49_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO49_FILTER_EN_S  15
+
+/** IO_MUX_gpio50_REG register
+ *  iomux control register for gpio50
+ */
+#define IO_MUX_GPIO50_REG (DR_REG_IO_MUX_BASE + 0xcc)
+/** IO_MUX_GPIO50_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO50_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO50_MCU_OE_M  (IO_MUX_GPIO50_MCU_OE_V << IO_MUX_GPIO50_MCU_OE_S)
+#define IO_MUX_GPIO50_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO50_MCU_OE_S  0
+/** IO_MUX_GPIO50_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO50_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO50_SLP_SEL_M  (IO_MUX_GPIO50_SLP_SEL_V << IO_MUX_GPIO50_SLP_SEL_S)
+#define IO_MUX_GPIO50_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO50_SLP_SEL_S  1
+/** IO_MUX_GPIO50_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO50_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO50_MCU_WPD_M  (IO_MUX_GPIO50_MCU_WPD_V << IO_MUX_GPIO50_MCU_WPD_S)
+#define IO_MUX_GPIO50_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO50_MCU_WPD_S  2
+/** IO_MUX_GPIO50_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO50_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO50_MCU_WPU_M  (IO_MUX_GPIO50_MCU_WPU_V << IO_MUX_GPIO50_MCU_WPU_S)
+#define IO_MUX_GPIO50_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO50_MCU_WPU_S  3
+/** IO_MUX_GPIO50_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO50_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO50_MCU_IE_M  (IO_MUX_GPIO50_MCU_IE_V << IO_MUX_GPIO50_MCU_IE_S)
+#define IO_MUX_GPIO50_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO50_MCU_IE_S  4
+/** IO_MUX_GPIO50_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO50_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO50_MCU_DRV_M  (IO_MUX_GPIO50_MCU_DRV_V << IO_MUX_GPIO50_MCU_DRV_S)
+#define IO_MUX_GPIO50_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO50_MCU_DRV_S  5
+/** IO_MUX_GPIO50_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO50_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO50_FUN_WPD_M  (IO_MUX_GPIO50_FUN_WPD_V << IO_MUX_GPIO50_FUN_WPD_S)
+#define IO_MUX_GPIO50_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO50_FUN_WPD_S  7
+/** IO_MUX_GPIO50_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO50_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO50_FUN_WPU_M  (IO_MUX_GPIO50_FUN_WPU_V << IO_MUX_GPIO50_FUN_WPU_S)
+#define IO_MUX_GPIO50_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO50_FUN_WPU_S  8
+/** IO_MUX_GPIO50_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO50_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO50_FUN_IE_M  (IO_MUX_GPIO50_FUN_IE_V << IO_MUX_GPIO50_FUN_IE_S)
+#define IO_MUX_GPIO50_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO50_FUN_IE_S  9
+/** IO_MUX_GPIO50_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO50_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO50_FUN_DRV_M  (IO_MUX_GPIO50_FUN_DRV_V << IO_MUX_GPIO50_FUN_DRV_S)
+#define IO_MUX_GPIO50_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO50_FUN_DRV_S  10
+/** IO_MUX_GPIO50_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO50_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO50_MCU_SEL_M  (IO_MUX_GPIO50_MCU_SEL_V << IO_MUX_GPIO50_MCU_SEL_S)
+#define IO_MUX_GPIO50_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO50_MCU_SEL_S  12
+/** IO_MUX_GPIO50_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO50_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO50_FILTER_EN_M  (IO_MUX_GPIO50_FILTER_EN_V << IO_MUX_GPIO50_FILTER_EN_S)
+#define IO_MUX_GPIO50_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO50_FILTER_EN_S  15
+
+/** IO_MUX_gpio51_REG register
+ *  iomux control register for gpio51
+ */
+#define IO_MUX_GPIO51_REG (DR_REG_IO_MUX_BASE + 0xd0)
+/** IO_MUX_GPIO51_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO51_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO51_MCU_OE_M  (IO_MUX_GPIO51_MCU_OE_V << IO_MUX_GPIO51_MCU_OE_S)
+#define IO_MUX_GPIO51_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO51_MCU_OE_S  0
+/** IO_MUX_GPIO51_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO51_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO51_SLP_SEL_M  (IO_MUX_GPIO51_SLP_SEL_V << IO_MUX_GPIO51_SLP_SEL_S)
+#define IO_MUX_GPIO51_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO51_SLP_SEL_S  1
+/** IO_MUX_GPIO51_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO51_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO51_MCU_WPD_M  (IO_MUX_GPIO51_MCU_WPD_V << IO_MUX_GPIO51_MCU_WPD_S)
+#define IO_MUX_GPIO51_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO51_MCU_WPD_S  2
+/** IO_MUX_GPIO51_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO51_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO51_MCU_WPU_M  (IO_MUX_GPIO51_MCU_WPU_V << IO_MUX_GPIO51_MCU_WPU_S)
+#define IO_MUX_GPIO51_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO51_MCU_WPU_S  3
+/** IO_MUX_GPIO51_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO51_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO51_MCU_IE_M  (IO_MUX_GPIO51_MCU_IE_V << IO_MUX_GPIO51_MCU_IE_S)
+#define IO_MUX_GPIO51_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO51_MCU_IE_S  4
+/** IO_MUX_GPIO51_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO51_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO51_MCU_DRV_M  (IO_MUX_GPIO51_MCU_DRV_V << IO_MUX_GPIO51_MCU_DRV_S)
+#define IO_MUX_GPIO51_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO51_MCU_DRV_S  5
+/** IO_MUX_GPIO51_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO51_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO51_FUN_WPD_M  (IO_MUX_GPIO51_FUN_WPD_V << IO_MUX_GPIO51_FUN_WPD_S)
+#define IO_MUX_GPIO51_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO51_FUN_WPD_S  7
+/** IO_MUX_GPIO51_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO51_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO51_FUN_WPU_M  (IO_MUX_GPIO51_FUN_WPU_V << IO_MUX_GPIO51_FUN_WPU_S)
+#define IO_MUX_GPIO51_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO51_FUN_WPU_S  8
+/** IO_MUX_GPIO51_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO51_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO51_FUN_IE_M  (IO_MUX_GPIO51_FUN_IE_V << IO_MUX_GPIO51_FUN_IE_S)
+#define IO_MUX_GPIO51_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO51_FUN_IE_S  9
+/** IO_MUX_GPIO51_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO51_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO51_FUN_DRV_M  (IO_MUX_GPIO51_FUN_DRV_V << IO_MUX_GPIO51_FUN_DRV_S)
+#define IO_MUX_GPIO51_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO51_FUN_DRV_S  10
+/** IO_MUX_GPIO51_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO51_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO51_MCU_SEL_M  (IO_MUX_GPIO51_MCU_SEL_V << IO_MUX_GPIO51_MCU_SEL_S)
+#define IO_MUX_GPIO51_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO51_MCU_SEL_S  12
+/** IO_MUX_GPIO51_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO51_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO51_FILTER_EN_M  (IO_MUX_GPIO51_FILTER_EN_V << IO_MUX_GPIO51_FILTER_EN_S)
+#define IO_MUX_GPIO51_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO51_FILTER_EN_S  15
+
+/** IO_MUX_gpio52_REG register
+ *  iomux control register for gpio52
+ */
+#define IO_MUX_GPIO52_REG (DR_REG_IO_MUX_BASE + 0xd4)
+/** IO_MUX_GPIO52_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO52_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO52_MCU_OE_M  (IO_MUX_GPIO52_MCU_OE_V << IO_MUX_GPIO52_MCU_OE_S)
+#define IO_MUX_GPIO52_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO52_MCU_OE_S  0
+/** IO_MUX_GPIO52_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO52_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO52_SLP_SEL_M  (IO_MUX_GPIO52_SLP_SEL_V << IO_MUX_GPIO52_SLP_SEL_S)
+#define IO_MUX_GPIO52_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO52_SLP_SEL_S  1
+/** IO_MUX_GPIO52_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO52_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO52_MCU_WPD_M  (IO_MUX_GPIO52_MCU_WPD_V << IO_MUX_GPIO52_MCU_WPD_S)
+#define IO_MUX_GPIO52_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO52_MCU_WPD_S  2
+/** IO_MUX_GPIO52_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO52_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO52_MCU_WPU_M  (IO_MUX_GPIO52_MCU_WPU_V << IO_MUX_GPIO52_MCU_WPU_S)
+#define IO_MUX_GPIO52_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO52_MCU_WPU_S  3
+/** IO_MUX_GPIO52_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO52_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO52_MCU_IE_M  (IO_MUX_GPIO52_MCU_IE_V << IO_MUX_GPIO52_MCU_IE_S)
+#define IO_MUX_GPIO52_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO52_MCU_IE_S  4
+/** IO_MUX_GPIO52_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO52_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO52_MCU_DRV_M  (IO_MUX_GPIO52_MCU_DRV_V << IO_MUX_GPIO52_MCU_DRV_S)
+#define IO_MUX_GPIO52_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO52_MCU_DRV_S  5
+/** IO_MUX_GPIO52_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO52_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO52_FUN_WPD_M  (IO_MUX_GPIO52_FUN_WPD_V << IO_MUX_GPIO52_FUN_WPD_S)
+#define IO_MUX_GPIO52_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO52_FUN_WPD_S  7
+/** IO_MUX_GPIO52_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO52_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO52_FUN_WPU_M  (IO_MUX_GPIO52_FUN_WPU_V << IO_MUX_GPIO52_FUN_WPU_S)
+#define IO_MUX_GPIO52_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO52_FUN_WPU_S  8
+/** IO_MUX_GPIO52_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO52_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO52_FUN_IE_M  (IO_MUX_GPIO52_FUN_IE_V << IO_MUX_GPIO52_FUN_IE_S)
+#define IO_MUX_GPIO52_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO52_FUN_IE_S  9
+/** IO_MUX_GPIO52_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO52_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO52_FUN_DRV_M  (IO_MUX_GPIO52_FUN_DRV_V << IO_MUX_GPIO52_FUN_DRV_S)
+#define IO_MUX_GPIO52_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO52_FUN_DRV_S  10
+/** IO_MUX_GPIO52_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO52_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO52_MCU_SEL_M  (IO_MUX_GPIO52_MCU_SEL_V << IO_MUX_GPIO52_MCU_SEL_S)
+#define IO_MUX_GPIO52_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO52_MCU_SEL_S  12
+/** IO_MUX_GPIO52_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO52_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO52_FILTER_EN_M  (IO_MUX_GPIO52_FILTER_EN_V << IO_MUX_GPIO52_FILTER_EN_S)
+#define IO_MUX_GPIO52_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO52_FILTER_EN_S  15
+
+/** IO_MUX_gpio53_REG register
+ *  iomux control register for gpio53
+ */
+#define IO_MUX_GPIO53_REG (DR_REG_IO_MUX_BASE + 0xd8)
+/** IO_MUX_GPIO53_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO53_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO53_MCU_OE_M  (IO_MUX_GPIO53_MCU_OE_V << IO_MUX_GPIO53_MCU_OE_S)
+#define IO_MUX_GPIO53_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO53_MCU_OE_S  0
+/** IO_MUX_GPIO53_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO53_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO53_SLP_SEL_M  (IO_MUX_GPIO53_SLP_SEL_V << IO_MUX_GPIO53_SLP_SEL_S)
+#define IO_MUX_GPIO53_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO53_SLP_SEL_S  1
+/** IO_MUX_GPIO53_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO53_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO53_MCU_WPD_M  (IO_MUX_GPIO53_MCU_WPD_V << IO_MUX_GPIO53_MCU_WPD_S)
+#define IO_MUX_GPIO53_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO53_MCU_WPD_S  2
+/** IO_MUX_GPIO53_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO53_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO53_MCU_WPU_M  (IO_MUX_GPIO53_MCU_WPU_V << IO_MUX_GPIO53_MCU_WPU_S)
+#define IO_MUX_GPIO53_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO53_MCU_WPU_S  3
+/** IO_MUX_GPIO53_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO53_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO53_MCU_IE_M  (IO_MUX_GPIO53_MCU_IE_V << IO_MUX_GPIO53_MCU_IE_S)
+#define IO_MUX_GPIO53_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO53_MCU_IE_S  4
+/** IO_MUX_GPIO53_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO53_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO53_MCU_DRV_M  (IO_MUX_GPIO53_MCU_DRV_V << IO_MUX_GPIO53_MCU_DRV_S)
+#define IO_MUX_GPIO53_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO53_MCU_DRV_S  5
+/** IO_MUX_GPIO53_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO53_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO53_FUN_WPD_M  (IO_MUX_GPIO53_FUN_WPD_V << IO_MUX_GPIO53_FUN_WPD_S)
+#define IO_MUX_GPIO53_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO53_FUN_WPD_S  7
+/** IO_MUX_GPIO53_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO53_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO53_FUN_WPU_M  (IO_MUX_GPIO53_FUN_WPU_V << IO_MUX_GPIO53_FUN_WPU_S)
+#define IO_MUX_GPIO53_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO53_FUN_WPU_S  8
+/** IO_MUX_GPIO53_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO53_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO53_FUN_IE_M  (IO_MUX_GPIO53_FUN_IE_V << IO_MUX_GPIO53_FUN_IE_S)
+#define IO_MUX_GPIO53_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO53_FUN_IE_S  9
+/** IO_MUX_GPIO53_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO53_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO53_FUN_DRV_M  (IO_MUX_GPIO53_FUN_DRV_V << IO_MUX_GPIO53_FUN_DRV_S)
+#define IO_MUX_GPIO53_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO53_FUN_DRV_S  10
+/** IO_MUX_GPIO53_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO53_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO53_MCU_SEL_M  (IO_MUX_GPIO53_MCU_SEL_V << IO_MUX_GPIO53_MCU_SEL_S)
+#define IO_MUX_GPIO53_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO53_MCU_SEL_S  12
+/** IO_MUX_GPIO53_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO53_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO53_FILTER_EN_M  (IO_MUX_GPIO53_FILTER_EN_V << IO_MUX_GPIO53_FILTER_EN_S)
+#define IO_MUX_GPIO53_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO53_FILTER_EN_S  15
+
+/** IO_MUX_gpio54_REG register
+ *  iomux control register for gpio54
+ */
+#define IO_MUX_GPIO54_REG (DR_REG_IO_MUX_BASE + 0xdc)
+/** IO_MUX_GPIO54_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO54_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO54_MCU_OE_M  (IO_MUX_GPIO54_MCU_OE_V << IO_MUX_GPIO54_MCU_OE_S)
+#define IO_MUX_GPIO54_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO54_MCU_OE_S  0
+/** IO_MUX_GPIO54_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO54_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO54_SLP_SEL_M  (IO_MUX_GPIO54_SLP_SEL_V << IO_MUX_GPIO54_SLP_SEL_S)
+#define IO_MUX_GPIO54_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO54_SLP_SEL_S  1
+/** IO_MUX_GPIO54_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO54_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO54_MCU_WPD_M  (IO_MUX_GPIO54_MCU_WPD_V << IO_MUX_GPIO54_MCU_WPD_S)
+#define IO_MUX_GPIO54_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO54_MCU_WPD_S  2
+/** IO_MUX_GPIO54_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO54_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO54_MCU_WPU_M  (IO_MUX_GPIO54_MCU_WPU_V << IO_MUX_GPIO54_MCU_WPU_S)
+#define IO_MUX_GPIO54_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO54_MCU_WPU_S  3
+/** IO_MUX_GPIO54_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO54_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO54_MCU_IE_M  (IO_MUX_GPIO54_MCU_IE_V << IO_MUX_GPIO54_MCU_IE_S)
+#define IO_MUX_GPIO54_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO54_MCU_IE_S  4
+/** IO_MUX_GPIO54_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO54_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO54_MCU_DRV_M  (IO_MUX_GPIO54_MCU_DRV_V << IO_MUX_GPIO54_MCU_DRV_S)
+#define IO_MUX_GPIO54_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO54_MCU_DRV_S  5
+/** IO_MUX_GPIO54_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO54_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO54_FUN_WPD_M  (IO_MUX_GPIO54_FUN_WPD_V << IO_MUX_GPIO54_FUN_WPD_S)
+#define IO_MUX_GPIO54_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO54_FUN_WPD_S  7
+/** IO_MUX_GPIO54_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO54_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO54_FUN_WPU_M  (IO_MUX_GPIO54_FUN_WPU_V << IO_MUX_GPIO54_FUN_WPU_S)
+#define IO_MUX_GPIO54_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO54_FUN_WPU_S  8
+/** IO_MUX_GPIO54_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO54_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO54_FUN_IE_M  (IO_MUX_GPIO54_FUN_IE_V << IO_MUX_GPIO54_FUN_IE_S)
+#define IO_MUX_GPIO54_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO54_FUN_IE_S  9
+/** IO_MUX_GPIO54_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO54_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO54_FUN_DRV_M  (IO_MUX_GPIO54_FUN_DRV_V << IO_MUX_GPIO54_FUN_DRV_S)
+#define IO_MUX_GPIO54_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO54_FUN_DRV_S  10
+/** IO_MUX_GPIO54_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO54_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO54_MCU_SEL_M  (IO_MUX_GPIO54_MCU_SEL_V << IO_MUX_GPIO54_MCU_SEL_S)
+#define IO_MUX_GPIO54_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO54_MCU_SEL_S  12
+/** IO_MUX_GPIO54_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO54_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO54_FILTER_EN_M  (IO_MUX_GPIO54_FILTER_EN_V << IO_MUX_GPIO54_FILTER_EN_S)
+#define IO_MUX_GPIO54_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO54_FILTER_EN_S  15
+
+/** IO_MUX_gpio55_REG register
+ *  iomux control register for gpio55
+ */
+#define IO_MUX_GPIO55_REG (DR_REG_IO_MUX_BASE + 0xe0)
+/** IO_MUX_GPIO55_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO55_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO55_MCU_OE_M  (IO_MUX_GPIO55_MCU_OE_V << IO_MUX_GPIO55_MCU_OE_S)
+#define IO_MUX_GPIO55_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO55_MCU_OE_S  0
+/** IO_MUX_GPIO55_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO55_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO55_SLP_SEL_M  (IO_MUX_GPIO55_SLP_SEL_V << IO_MUX_GPIO55_SLP_SEL_S)
+#define IO_MUX_GPIO55_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO55_SLP_SEL_S  1
+/** IO_MUX_GPIO55_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO55_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO55_MCU_WPD_M  (IO_MUX_GPIO55_MCU_WPD_V << IO_MUX_GPIO55_MCU_WPD_S)
+#define IO_MUX_GPIO55_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO55_MCU_WPD_S  2
+/** IO_MUX_GPIO55_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO55_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO55_MCU_WPU_M  (IO_MUX_GPIO55_MCU_WPU_V << IO_MUX_GPIO55_MCU_WPU_S)
+#define IO_MUX_GPIO55_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO55_MCU_WPU_S  3
+/** IO_MUX_GPIO55_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO55_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO55_MCU_IE_M  (IO_MUX_GPIO55_MCU_IE_V << IO_MUX_GPIO55_MCU_IE_S)
+#define IO_MUX_GPIO55_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO55_MCU_IE_S  4
+/** IO_MUX_GPIO55_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO55_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO55_MCU_DRV_M  (IO_MUX_GPIO55_MCU_DRV_V << IO_MUX_GPIO55_MCU_DRV_S)
+#define IO_MUX_GPIO55_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO55_MCU_DRV_S  5
+/** IO_MUX_GPIO55_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO55_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO55_FUN_WPD_M  (IO_MUX_GPIO55_FUN_WPD_V << IO_MUX_GPIO55_FUN_WPD_S)
+#define IO_MUX_GPIO55_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO55_FUN_WPD_S  7
+/** IO_MUX_GPIO55_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO55_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO55_FUN_WPU_M  (IO_MUX_GPIO55_FUN_WPU_V << IO_MUX_GPIO55_FUN_WPU_S)
+#define IO_MUX_GPIO55_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO55_FUN_WPU_S  8
+/** IO_MUX_GPIO55_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO55_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO55_FUN_IE_M  (IO_MUX_GPIO55_FUN_IE_V << IO_MUX_GPIO55_FUN_IE_S)
+#define IO_MUX_GPIO55_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO55_FUN_IE_S  9
+/** IO_MUX_GPIO55_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO55_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO55_FUN_DRV_M  (IO_MUX_GPIO55_FUN_DRV_V << IO_MUX_GPIO55_FUN_DRV_S)
+#define IO_MUX_GPIO55_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO55_FUN_DRV_S  10
+/** IO_MUX_GPIO55_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO55_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO55_MCU_SEL_M  (IO_MUX_GPIO55_MCU_SEL_V << IO_MUX_GPIO55_MCU_SEL_S)
+#define IO_MUX_GPIO55_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO55_MCU_SEL_S  12
+/** IO_MUX_GPIO55_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO55_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO55_FILTER_EN_M  (IO_MUX_GPIO55_FILTER_EN_V << IO_MUX_GPIO55_FILTER_EN_S)
+#define IO_MUX_GPIO55_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO55_FILTER_EN_S  15
+
+/** IO_MUX_gpio56_REG register
+ *  iomux control register for gpio56
+ */
+#define IO_MUX_GPIO56_REG (DR_REG_IO_MUX_BASE + 0xe4)
+/** IO_MUX_GPIO56_MCU_OE : R/W; bitpos: [0]; default: 0;
+ *  output enable on sleep mode
+ */
+#define IO_MUX_GPIO56_MCU_OE    (BIT(0))
+#define IO_MUX_GPIO56_MCU_OE_M  (IO_MUX_GPIO56_MCU_OE_V << IO_MUX_GPIO56_MCU_OE_S)
+#define IO_MUX_GPIO56_MCU_OE_V  0x00000001U
+#define IO_MUX_GPIO56_MCU_OE_S  0
+/** IO_MUX_GPIO56_SLP_SEL : R/W; bitpos: [1]; default: 0;
+ *  io sleep mode enable. set 1 to enable sleep mode.
+ */
+#define IO_MUX_GPIO56_SLP_SEL    (BIT(1))
+#define IO_MUX_GPIO56_SLP_SEL_M  (IO_MUX_GPIO56_SLP_SEL_V << IO_MUX_GPIO56_SLP_SEL_S)
+#define IO_MUX_GPIO56_SLP_SEL_V  0x00000001U
+#define IO_MUX_GPIO56_SLP_SEL_S  1
+/** IO_MUX_GPIO56_MCU_WPD : R/W; bitpos: [2]; default: 0;
+ *  pull-down enable on sleep mode
+ */
+#define IO_MUX_GPIO56_MCU_WPD    (BIT(2))
+#define IO_MUX_GPIO56_MCU_WPD_M  (IO_MUX_GPIO56_MCU_WPD_V << IO_MUX_GPIO56_MCU_WPD_S)
+#define IO_MUX_GPIO56_MCU_WPD_V  0x00000001U
+#define IO_MUX_GPIO56_MCU_WPD_S  2
+/** IO_MUX_GPIO56_MCU_WPU : R/W; bitpos: [3]; default: 0;
+ *  pull-up enable on sleep mode
+ */
+#define IO_MUX_GPIO56_MCU_WPU    (BIT(3))
+#define IO_MUX_GPIO56_MCU_WPU_M  (IO_MUX_GPIO56_MCU_WPU_V << IO_MUX_GPIO56_MCU_WPU_S)
+#define IO_MUX_GPIO56_MCU_WPU_V  0x00000001U
+#define IO_MUX_GPIO56_MCU_WPU_S  3
+/** IO_MUX_GPIO56_MCU_IE : R/W; bitpos: [4]; default: 0;
+ *  input enable on sleep mode
+ */
+#define IO_MUX_GPIO56_MCU_IE    (BIT(4))
+#define IO_MUX_GPIO56_MCU_IE_M  (IO_MUX_GPIO56_MCU_IE_V << IO_MUX_GPIO56_MCU_IE_S)
+#define IO_MUX_GPIO56_MCU_IE_V  0x00000001U
+#define IO_MUX_GPIO56_MCU_IE_S  4
+/** IO_MUX_GPIO56_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
+ *  select drive strength on sleep mode
+ */
+#define IO_MUX_GPIO56_MCU_DRV    0x00000003U
+#define IO_MUX_GPIO56_MCU_DRV_M  (IO_MUX_GPIO56_MCU_DRV_V << IO_MUX_GPIO56_MCU_DRV_S)
+#define IO_MUX_GPIO56_MCU_DRV_V  0x00000003U
+#define IO_MUX_GPIO56_MCU_DRV_S  5
+/** IO_MUX_GPIO56_FUN_WPD : R/W; bitpos: [7]; default: 0;
+ *  pull-down enable
+ */
+#define IO_MUX_GPIO56_FUN_WPD    (BIT(7))
+#define IO_MUX_GPIO56_FUN_WPD_M  (IO_MUX_GPIO56_FUN_WPD_V << IO_MUX_GPIO56_FUN_WPD_S)
+#define IO_MUX_GPIO56_FUN_WPD_V  0x00000001U
+#define IO_MUX_GPIO56_FUN_WPD_S  7
+/** IO_MUX_GPIO56_FUN_WPU : R/W; bitpos: [8]; default: 0;
+ *  pull-up enable
+ */
+#define IO_MUX_GPIO56_FUN_WPU    (BIT(8))
+#define IO_MUX_GPIO56_FUN_WPU_M  (IO_MUX_GPIO56_FUN_WPU_V << IO_MUX_GPIO56_FUN_WPU_S)
+#define IO_MUX_GPIO56_FUN_WPU_V  0x00000001U
+#define IO_MUX_GPIO56_FUN_WPU_S  8
+/** IO_MUX_GPIO56_FUN_IE : R/W; bitpos: [9]; default: 0;
+ *  input enable
+ */
+#define IO_MUX_GPIO56_FUN_IE    (BIT(9))
+#define IO_MUX_GPIO56_FUN_IE_M  (IO_MUX_GPIO56_FUN_IE_V << IO_MUX_GPIO56_FUN_IE_S)
+#define IO_MUX_GPIO56_FUN_IE_V  0x00000001U
+#define IO_MUX_GPIO56_FUN_IE_S  9
+/** IO_MUX_GPIO56_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
+ *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+ */
+#define IO_MUX_GPIO56_FUN_DRV    0x00000003U
+#define IO_MUX_GPIO56_FUN_DRV_M  (IO_MUX_GPIO56_FUN_DRV_V << IO_MUX_GPIO56_FUN_DRV_S)
+#define IO_MUX_GPIO56_FUN_DRV_V  0x00000003U
+#define IO_MUX_GPIO56_FUN_DRV_S  10
+/** IO_MUX_GPIO56_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  0:select function0, 1:select function1 ...
+ */
+#define IO_MUX_GPIO56_MCU_SEL    0x00000007U
+#define IO_MUX_GPIO56_MCU_SEL_M  (IO_MUX_GPIO56_MCU_SEL_V << IO_MUX_GPIO56_MCU_SEL_S)
+#define IO_MUX_GPIO56_MCU_SEL_V  0x00000007U
+#define IO_MUX_GPIO56_MCU_SEL_S  12
+/** IO_MUX_GPIO56_FILTER_EN : R/W; bitpos: [15]; default: 0;
+ *  input filter enable
+ */
+#define IO_MUX_GPIO56_FILTER_EN    (BIT(15))
+#define IO_MUX_GPIO56_FILTER_EN_M  (IO_MUX_GPIO56_FILTER_EN_V << IO_MUX_GPIO56_FILTER_EN_S)
+#define IO_MUX_GPIO56_FILTER_EN_V  0x00000001U
+#define IO_MUX_GPIO56_FILTER_EN_S  15
+
+/** IO_MUX_DATE_REG register
+ *  iomux version
+ */
+#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x104)
+/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 2101794;
+ *  csv date
+ */
+#define IO_MUX_DATE    0x0FFFFFFFU
+#define IO_MUX_DATE_M  (IO_MUX_DATE_V << IO_MUX_DATE_S)
+#define IO_MUX_DATE_V  0x0FFFFFFFU
+#define IO_MUX_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h
new file mode 100644
index 0000000000..0ebee78c34
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h
@@ -0,0 +1,3430 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: IOMUX Register */
+/** Type of gpio0 register
+ *  iomux control register for gpio0
+ */
+typedef union {
+    struct {
+        /** gpio0_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio0_mcu_oe:1;
+        /** gpio0_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio0_slp_sel:1;
+        /** gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio0_mcu_wpd:1;
+        /** gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio0_mcu_wpu:1;
+        /** gpio0_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio0_mcu_ie:1;
+        /** gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio0_mcu_drv:2;
+        /** gpio0_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio0_fun_wpd:1;
+        /** gpio0_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio0_fun_wpu:1;
+        /** gpio0_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio0_fun_ie:1;
+        /** gpio0_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio0_fun_drv:2;
+        /** gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio0_mcu_sel:3;
+        /** gpio0_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio0_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio0_reg_t;
+
+/** Type of gpio1 register
+ *  iomux control register for gpio1
+ */
+typedef union {
+    struct {
+        /** gpio1_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio1_mcu_oe:1;
+        /** gpio1_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio1_slp_sel:1;
+        /** gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio1_mcu_wpd:1;
+        /** gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio1_mcu_wpu:1;
+        /** gpio1_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio1_mcu_ie:1;
+        /** gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio1_mcu_drv:2;
+        /** gpio1_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio1_fun_wpd:1;
+        /** gpio1_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio1_fun_wpu:1;
+        /** gpio1_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio1_fun_ie:1;
+        /** gpio1_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio1_fun_drv:2;
+        /** gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio1_mcu_sel:3;
+        /** gpio1_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio1_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio1_reg_t;
+
+/** Type of gpio2 register
+ *  iomux control register for gpio2
+ */
+typedef union {
+    struct {
+        /** gpio2_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio2_mcu_oe:1;
+        /** gpio2_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio2_slp_sel:1;
+        /** gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio2_mcu_wpd:1;
+        /** gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio2_mcu_wpu:1;
+        /** gpio2_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio2_mcu_ie:1;
+        /** gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio2_mcu_drv:2;
+        /** gpio2_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio2_fun_wpd:1;
+        /** gpio2_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio2_fun_wpu:1;
+        /** gpio2_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio2_fun_ie:1;
+        /** gpio2_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio2_fun_drv:2;
+        /** gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio2_mcu_sel:3;
+        /** gpio2_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio2_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio2_reg_t;
+
+/** Type of gpio3 register
+ *  iomux control register for gpio3
+ */
+typedef union {
+    struct {
+        /** gpio3_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio3_mcu_oe:1;
+        /** gpio3_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio3_slp_sel:1;
+        /** gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio3_mcu_wpd:1;
+        /** gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio3_mcu_wpu:1;
+        /** gpio3_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio3_mcu_ie:1;
+        /** gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio3_mcu_drv:2;
+        /** gpio3_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio3_fun_wpd:1;
+        /** gpio3_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio3_fun_wpu:1;
+        /** gpio3_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio3_fun_ie:1;
+        /** gpio3_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio3_fun_drv:2;
+        /** gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio3_mcu_sel:3;
+        /** gpio3_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio3_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio3_reg_t;
+
+/** Type of gpio4 register
+ *  iomux control register for gpio4
+ */
+typedef union {
+    struct {
+        /** gpio4_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio4_mcu_oe:1;
+        /** gpio4_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio4_slp_sel:1;
+        /** gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio4_mcu_wpd:1;
+        /** gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio4_mcu_wpu:1;
+        /** gpio4_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio4_mcu_ie:1;
+        /** gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio4_mcu_drv:2;
+        /** gpio4_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio4_fun_wpd:1;
+        /** gpio4_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio4_fun_wpu:1;
+        /** gpio4_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio4_fun_ie:1;
+        /** gpio4_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio4_fun_drv:2;
+        /** gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio4_mcu_sel:3;
+        /** gpio4_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio4_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio4_reg_t;
+
+/** Type of gpio5 register
+ *  iomux control register for gpio5
+ */
+typedef union {
+    struct {
+        /** gpio5_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio5_mcu_oe:1;
+        /** gpio5_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio5_slp_sel:1;
+        /** gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio5_mcu_wpd:1;
+        /** gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio5_mcu_wpu:1;
+        /** gpio5_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio5_mcu_ie:1;
+        /** gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio5_mcu_drv:2;
+        /** gpio5_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio5_fun_wpd:1;
+        /** gpio5_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio5_fun_wpu:1;
+        /** gpio5_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio5_fun_ie:1;
+        /** gpio5_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio5_fun_drv:2;
+        /** gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio5_mcu_sel:3;
+        /** gpio5_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio5_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio5_reg_t;
+
+/** Type of gpio6 register
+ *  iomux control register for gpio6
+ */
+typedef union {
+    struct {
+        /** gpio6_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio6_mcu_oe:1;
+        /** gpio6_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio6_slp_sel:1;
+        /** gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio6_mcu_wpd:1;
+        /** gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio6_mcu_wpu:1;
+        /** gpio6_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio6_mcu_ie:1;
+        /** gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio6_mcu_drv:2;
+        /** gpio6_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio6_fun_wpd:1;
+        /** gpio6_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio6_fun_wpu:1;
+        /** gpio6_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio6_fun_ie:1;
+        /** gpio6_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio6_fun_drv:2;
+        /** gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio6_mcu_sel:3;
+        /** gpio6_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio6_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio6_reg_t;
+
+/** Type of gpio7 register
+ *  iomux control register for gpio7
+ */
+typedef union {
+    struct {
+        /** gpio7_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio7_mcu_oe:1;
+        /** gpio7_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio7_slp_sel:1;
+        /** gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio7_mcu_wpd:1;
+        /** gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio7_mcu_wpu:1;
+        /** gpio7_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio7_mcu_ie:1;
+        /** gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio7_mcu_drv:2;
+        /** gpio7_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio7_fun_wpd:1;
+        /** gpio7_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio7_fun_wpu:1;
+        /** gpio7_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio7_fun_ie:1;
+        /** gpio7_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio7_fun_drv:2;
+        /** gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio7_mcu_sel:3;
+        /** gpio7_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio7_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio7_reg_t;
+
+/** Type of gpio8 register
+ *  iomux control register for gpio8
+ */
+typedef union {
+    struct {
+        /** gpio8_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio8_mcu_oe:1;
+        /** gpio8_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio8_slp_sel:1;
+        /** gpio8_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio8_mcu_wpd:1;
+        /** gpio8_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio8_mcu_wpu:1;
+        /** gpio8_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio8_mcu_ie:1;
+        /** gpio8_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio8_mcu_drv:2;
+        /** gpio8_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio8_fun_wpd:1;
+        /** gpio8_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio8_fun_wpu:1;
+        /** gpio8_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio8_fun_ie:1;
+        /** gpio8_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio8_fun_drv:2;
+        /** gpio8_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio8_mcu_sel:3;
+        /** gpio8_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio8_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio8_reg_t;
+
+/** Type of gpio9 register
+ *  iomux control register for gpio9
+ */
+typedef union {
+    struct {
+        /** gpio9_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio9_mcu_oe:1;
+        /** gpio9_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio9_slp_sel:1;
+        /** gpio9_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio9_mcu_wpd:1;
+        /** gpio9_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio9_mcu_wpu:1;
+        /** gpio9_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio9_mcu_ie:1;
+        /** gpio9_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio9_mcu_drv:2;
+        /** gpio9_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio9_fun_wpd:1;
+        /** gpio9_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio9_fun_wpu:1;
+        /** gpio9_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio9_fun_ie:1;
+        /** gpio9_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio9_fun_drv:2;
+        /** gpio9_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio9_mcu_sel:3;
+        /** gpio9_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio9_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio9_reg_t;
+
+/** Type of gpio10 register
+ *  iomux control register for gpio10
+ */
+typedef union {
+    struct {
+        /** gpio10_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio10_mcu_oe:1;
+        /** gpio10_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio10_slp_sel:1;
+        /** gpio10_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio10_mcu_wpd:1;
+        /** gpio10_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio10_mcu_wpu:1;
+        /** gpio10_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio10_mcu_ie:1;
+        /** gpio10_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio10_mcu_drv:2;
+        /** gpio10_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio10_fun_wpd:1;
+        /** gpio10_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio10_fun_wpu:1;
+        /** gpio10_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio10_fun_ie:1;
+        /** gpio10_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio10_fun_drv:2;
+        /** gpio10_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio10_mcu_sel:3;
+        /** gpio10_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio10_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio10_reg_t;
+
+/** Type of gpio11 register
+ *  iomux control register for gpio11
+ */
+typedef union {
+    struct {
+        /** gpio11_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio11_mcu_oe:1;
+        /** gpio11_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio11_slp_sel:1;
+        /** gpio11_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio11_mcu_wpd:1;
+        /** gpio11_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio11_mcu_wpu:1;
+        /** gpio11_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio11_mcu_ie:1;
+        /** gpio11_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio11_mcu_drv:2;
+        /** gpio11_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio11_fun_wpd:1;
+        /** gpio11_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio11_fun_wpu:1;
+        /** gpio11_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio11_fun_ie:1;
+        /** gpio11_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio11_fun_drv:2;
+        /** gpio11_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio11_mcu_sel:3;
+        /** gpio11_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio11_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio11_reg_t;
+
+/** Type of gpio12 register
+ *  iomux control register for gpio12
+ */
+typedef union {
+    struct {
+        /** gpio12_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio12_mcu_oe:1;
+        /** gpio12_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio12_slp_sel:1;
+        /** gpio12_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio12_mcu_wpd:1;
+        /** gpio12_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio12_mcu_wpu:1;
+        /** gpio12_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio12_mcu_ie:1;
+        /** gpio12_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio12_mcu_drv:2;
+        /** gpio12_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio12_fun_wpd:1;
+        /** gpio12_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio12_fun_wpu:1;
+        /** gpio12_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio12_fun_ie:1;
+        /** gpio12_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio12_fun_drv:2;
+        /** gpio12_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio12_mcu_sel:3;
+        /** gpio12_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio12_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio12_reg_t;
+
+/** Type of gpio13 register
+ *  iomux control register for gpio13
+ */
+typedef union {
+    struct {
+        /** gpio13_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio13_mcu_oe:1;
+        /** gpio13_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio13_slp_sel:1;
+        /** gpio13_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio13_mcu_wpd:1;
+        /** gpio13_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio13_mcu_wpu:1;
+        /** gpio13_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio13_mcu_ie:1;
+        /** gpio13_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio13_mcu_drv:2;
+        /** gpio13_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio13_fun_wpd:1;
+        /** gpio13_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio13_fun_wpu:1;
+        /** gpio13_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio13_fun_ie:1;
+        /** gpio13_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio13_fun_drv:2;
+        /** gpio13_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio13_mcu_sel:3;
+        /** gpio13_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio13_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio13_reg_t;
+
+/** Type of gpio14 register
+ *  iomux control register for gpio14
+ */
+typedef union {
+    struct {
+        /** gpio14_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio14_mcu_oe:1;
+        /** gpio14_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio14_slp_sel:1;
+        /** gpio14_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio14_mcu_wpd:1;
+        /** gpio14_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio14_mcu_wpu:1;
+        /** gpio14_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio14_mcu_ie:1;
+        /** gpio14_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio14_mcu_drv:2;
+        /** gpio14_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio14_fun_wpd:1;
+        /** gpio14_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio14_fun_wpu:1;
+        /** gpio14_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio14_fun_ie:1;
+        /** gpio14_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio14_fun_drv:2;
+        /** gpio14_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio14_mcu_sel:3;
+        /** gpio14_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio14_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio14_reg_t;
+
+/** Type of gpio15 register
+ *  iomux control register for gpio15
+ */
+typedef union {
+    struct {
+        /** gpio15_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio15_mcu_oe:1;
+        /** gpio15_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio15_slp_sel:1;
+        /** gpio15_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio15_mcu_wpd:1;
+        /** gpio15_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio15_mcu_wpu:1;
+        /** gpio15_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio15_mcu_ie:1;
+        /** gpio15_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio15_mcu_drv:2;
+        /** gpio15_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio15_fun_wpd:1;
+        /** gpio15_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio15_fun_wpu:1;
+        /** gpio15_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio15_fun_ie:1;
+        /** gpio15_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio15_fun_drv:2;
+        /** gpio15_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio15_mcu_sel:3;
+        /** gpio15_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio15_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio15_reg_t;
+
+/** Type of gpio16 register
+ *  iomux control register for gpio16
+ */
+typedef union {
+    struct {
+        /** gpio16_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio16_mcu_oe:1;
+        /** gpio16_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio16_slp_sel:1;
+        /** gpio16_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio16_mcu_wpd:1;
+        /** gpio16_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio16_mcu_wpu:1;
+        /** gpio16_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio16_mcu_ie:1;
+        /** gpio16_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio16_mcu_drv:2;
+        /** gpio16_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio16_fun_wpd:1;
+        /** gpio16_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio16_fun_wpu:1;
+        /** gpio16_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio16_fun_ie:1;
+        /** gpio16_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio16_fun_drv:2;
+        /** gpio16_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio16_mcu_sel:3;
+        /** gpio16_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio16_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio16_reg_t;
+
+/** Type of gpio17 register
+ *  iomux control register for gpio17
+ */
+typedef union {
+    struct {
+        /** gpio17_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio17_mcu_oe:1;
+        /** gpio17_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio17_slp_sel:1;
+        /** gpio17_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio17_mcu_wpd:1;
+        /** gpio17_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio17_mcu_wpu:1;
+        /** gpio17_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio17_mcu_ie:1;
+        /** gpio17_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio17_mcu_drv:2;
+        /** gpio17_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio17_fun_wpd:1;
+        /** gpio17_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio17_fun_wpu:1;
+        /** gpio17_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio17_fun_ie:1;
+        /** gpio17_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio17_fun_drv:2;
+        /** gpio17_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio17_mcu_sel:3;
+        /** gpio17_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio17_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio17_reg_t;
+
+/** Type of gpio18 register
+ *  iomux control register for gpio18
+ */
+typedef union {
+    struct {
+        /** gpio18_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio18_mcu_oe:1;
+        /** gpio18_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio18_slp_sel:1;
+        /** gpio18_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio18_mcu_wpd:1;
+        /** gpio18_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio18_mcu_wpu:1;
+        /** gpio18_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio18_mcu_ie:1;
+        /** gpio18_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio18_mcu_drv:2;
+        /** gpio18_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio18_fun_wpd:1;
+        /** gpio18_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio18_fun_wpu:1;
+        /** gpio18_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio18_fun_ie:1;
+        /** gpio18_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio18_fun_drv:2;
+        /** gpio18_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio18_mcu_sel:3;
+        /** gpio18_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio18_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio18_reg_t;
+
+/** Type of gpio19 register
+ *  iomux control register for gpio19
+ */
+typedef union {
+    struct {
+        /** gpio19_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio19_mcu_oe:1;
+        /** gpio19_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio19_slp_sel:1;
+        /** gpio19_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio19_mcu_wpd:1;
+        /** gpio19_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio19_mcu_wpu:1;
+        /** gpio19_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio19_mcu_ie:1;
+        /** gpio19_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio19_mcu_drv:2;
+        /** gpio19_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio19_fun_wpd:1;
+        /** gpio19_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio19_fun_wpu:1;
+        /** gpio19_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio19_fun_ie:1;
+        /** gpio19_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio19_fun_drv:2;
+        /** gpio19_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio19_mcu_sel:3;
+        /** gpio19_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio19_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio19_reg_t;
+
+/** Type of gpio20 register
+ *  iomux control register for gpio20
+ */
+typedef union {
+    struct {
+        /** gpio20_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio20_mcu_oe:1;
+        /** gpio20_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio20_slp_sel:1;
+        /** gpio20_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio20_mcu_wpd:1;
+        /** gpio20_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio20_mcu_wpu:1;
+        /** gpio20_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio20_mcu_ie:1;
+        /** gpio20_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio20_mcu_drv:2;
+        /** gpio20_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio20_fun_wpd:1;
+        /** gpio20_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio20_fun_wpu:1;
+        /** gpio20_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio20_fun_ie:1;
+        /** gpio20_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio20_fun_drv:2;
+        /** gpio20_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio20_mcu_sel:3;
+        /** gpio20_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio20_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio20_reg_t;
+
+/** Type of gpio21 register
+ *  iomux control register for gpio21
+ */
+typedef union {
+    struct {
+        /** gpio21_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio21_mcu_oe:1;
+        /** gpio21_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio21_slp_sel:1;
+        /** gpio21_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio21_mcu_wpd:1;
+        /** gpio21_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio21_mcu_wpu:1;
+        /** gpio21_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio21_mcu_ie:1;
+        /** gpio21_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio21_mcu_drv:2;
+        /** gpio21_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio21_fun_wpd:1;
+        /** gpio21_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio21_fun_wpu:1;
+        /** gpio21_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio21_fun_ie:1;
+        /** gpio21_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio21_fun_drv:2;
+        /** gpio21_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio21_mcu_sel:3;
+        /** gpio21_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio21_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio21_reg_t;
+
+/** Type of gpio22 register
+ *  iomux control register for gpio22
+ */
+typedef union {
+    struct {
+        /** gpio22_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio22_mcu_oe:1;
+        /** gpio22_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio22_slp_sel:1;
+        /** gpio22_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio22_mcu_wpd:1;
+        /** gpio22_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio22_mcu_wpu:1;
+        /** gpio22_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio22_mcu_ie:1;
+        /** gpio22_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio22_mcu_drv:2;
+        /** gpio22_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio22_fun_wpd:1;
+        /** gpio22_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio22_fun_wpu:1;
+        /** gpio22_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio22_fun_ie:1;
+        /** gpio22_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio22_fun_drv:2;
+        /** gpio22_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio22_mcu_sel:3;
+        /** gpio22_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio22_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio22_reg_t;
+
+/** Type of gpio23 register
+ *  iomux control register for gpio23
+ */
+typedef union {
+    struct {
+        /** gpio23_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio23_mcu_oe:1;
+        /** gpio23_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio23_slp_sel:1;
+        /** gpio23_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio23_mcu_wpd:1;
+        /** gpio23_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio23_mcu_wpu:1;
+        /** gpio23_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio23_mcu_ie:1;
+        /** gpio23_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio23_mcu_drv:2;
+        /** gpio23_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio23_fun_wpd:1;
+        /** gpio23_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio23_fun_wpu:1;
+        /** gpio23_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio23_fun_ie:1;
+        /** gpio23_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio23_fun_drv:2;
+        /** gpio23_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio23_mcu_sel:3;
+        /** gpio23_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio23_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio23_reg_t;
+
+/** Type of gpio24 register
+ *  iomux control register for gpio24
+ */
+typedef union {
+    struct {
+        /** gpio24_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio24_mcu_oe:1;
+        /** gpio24_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio24_slp_sel:1;
+        /** gpio24_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio24_mcu_wpd:1;
+        /** gpio24_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio24_mcu_wpu:1;
+        /** gpio24_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio24_mcu_ie:1;
+        /** gpio24_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio24_mcu_drv:2;
+        /** gpio24_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio24_fun_wpd:1;
+        /** gpio24_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio24_fun_wpu:1;
+        /** gpio24_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio24_fun_ie:1;
+        /** gpio24_fun_drv : R/W; bitpos: [11:10]; default: 3;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio24_fun_drv:2;
+        /** gpio24_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio24_mcu_sel:3;
+        /** gpio24_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio24_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio24_reg_t;
+
+/** Type of gpio25 register
+ *  iomux control register for gpio25
+ */
+typedef union {
+    struct {
+        /** gpio25_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio25_mcu_oe:1;
+        /** gpio25_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio25_slp_sel:1;
+        /** gpio25_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio25_mcu_wpd:1;
+        /** gpio25_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio25_mcu_wpu:1;
+        /** gpio25_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio25_mcu_ie:1;
+        /** gpio25_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio25_mcu_drv:2;
+        /** gpio25_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio25_fun_wpd:1;
+        /** gpio25_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio25_fun_wpu:1;
+        /** gpio25_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio25_fun_ie:1;
+        /** gpio25_fun_drv : R/W; bitpos: [11:10]; default: 3;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio25_fun_drv:2;
+        /** gpio25_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio25_mcu_sel:3;
+        /** gpio25_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio25_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio25_reg_t;
+
+/** Type of gpio26 register
+ *  iomux control register for gpio26
+ */
+typedef union {
+    struct {
+        /** gpio26_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio26_mcu_oe:1;
+        /** gpio26_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio26_slp_sel:1;
+        /** gpio26_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio26_mcu_wpd:1;
+        /** gpio26_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio26_mcu_wpu:1;
+        /** gpio26_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio26_mcu_ie:1;
+        /** gpio26_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio26_mcu_drv:2;
+        /** gpio26_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio26_fun_wpd:1;
+        /** gpio26_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio26_fun_wpu:1;
+        /** gpio26_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio26_fun_ie:1;
+        /** gpio26_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio26_fun_drv:2;
+        /** gpio26_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio26_mcu_sel:3;
+        /** gpio26_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio26_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio26_reg_t;
+
+/** Type of gpio27 register
+ *  iomux control register for gpio27
+ */
+typedef union {
+    struct {
+        /** gpio27_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio27_mcu_oe:1;
+        /** gpio27_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio27_slp_sel:1;
+        /** gpio27_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio27_mcu_wpd:1;
+        /** gpio27_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio27_mcu_wpu:1;
+        /** gpio27_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio27_mcu_ie:1;
+        /** gpio27_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio27_mcu_drv:2;
+        /** gpio27_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio27_fun_wpd:1;
+        /** gpio27_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio27_fun_wpu:1;
+        /** gpio27_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio27_fun_ie:1;
+        /** gpio27_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio27_fun_drv:2;
+        /** gpio27_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio27_mcu_sel:3;
+        /** gpio27_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio27_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio27_reg_t;
+
+/** Type of gpio28 register
+ *  iomux control register for gpio28
+ */
+typedef union {
+    struct {
+        /** gpio28_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio28_mcu_oe:1;
+        /** gpio28_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio28_slp_sel:1;
+        /** gpio28_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio28_mcu_wpd:1;
+        /** gpio28_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio28_mcu_wpu:1;
+        /** gpio28_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio28_mcu_ie:1;
+        /** gpio28_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio28_mcu_drv:2;
+        /** gpio28_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio28_fun_wpd:1;
+        /** gpio28_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio28_fun_wpu:1;
+        /** gpio28_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio28_fun_ie:1;
+        /** gpio28_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio28_fun_drv:2;
+        /** gpio28_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio28_mcu_sel:3;
+        /** gpio28_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio28_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio28_reg_t;
+
+/** Type of gpio29 register
+ *  iomux control register for gpio29
+ */
+typedef union {
+    struct {
+        /** gpio29_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio29_mcu_oe:1;
+        /** gpio29_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio29_slp_sel:1;
+        /** gpio29_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio29_mcu_wpd:1;
+        /** gpio29_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio29_mcu_wpu:1;
+        /** gpio29_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio29_mcu_ie:1;
+        /** gpio29_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio29_mcu_drv:2;
+        /** gpio29_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio29_fun_wpd:1;
+        /** gpio29_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio29_fun_wpu:1;
+        /** gpio29_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio29_fun_ie:1;
+        /** gpio29_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio29_fun_drv:2;
+        /** gpio29_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio29_mcu_sel:3;
+        /** gpio29_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio29_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio29_reg_t;
+
+/** Type of gpio30 register
+ *  iomux control register for gpio30
+ */
+typedef union {
+    struct {
+        /** gpio30_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio30_mcu_oe:1;
+        /** gpio30_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio30_slp_sel:1;
+        /** gpio30_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio30_mcu_wpd:1;
+        /** gpio30_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio30_mcu_wpu:1;
+        /** gpio30_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio30_mcu_ie:1;
+        /** gpio30_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio30_mcu_drv:2;
+        /** gpio30_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio30_fun_wpd:1;
+        /** gpio30_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio30_fun_wpu:1;
+        /** gpio30_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio30_fun_ie:1;
+        /** gpio30_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio30_fun_drv:2;
+        /** gpio30_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio30_mcu_sel:3;
+        /** gpio30_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio30_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio30_reg_t;
+
+/** Type of gpio31 register
+ *  iomux control register for gpio31
+ */
+typedef union {
+    struct {
+        /** gpio31_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio31_mcu_oe:1;
+        /** gpio31_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio31_slp_sel:1;
+        /** gpio31_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio31_mcu_wpd:1;
+        /** gpio31_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio31_mcu_wpu:1;
+        /** gpio31_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio31_mcu_ie:1;
+        /** gpio31_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio31_mcu_drv:2;
+        /** gpio31_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio31_fun_wpd:1;
+        /** gpio31_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio31_fun_wpu:1;
+        /** gpio31_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio31_fun_ie:1;
+        /** gpio31_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio31_fun_drv:2;
+        /** gpio31_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio31_mcu_sel:3;
+        /** gpio31_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio31_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio31_reg_t;
+
+/** Type of gpio32 register
+ *  iomux control register for gpio32
+ */
+typedef union {
+    struct {
+        /** gpio32_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio32_mcu_oe:1;
+        /** gpio32_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio32_slp_sel:1;
+        /** gpio32_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio32_mcu_wpd:1;
+        /** gpio32_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio32_mcu_wpu:1;
+        /** gpio32_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio32_mcu_ie:1;
+        /** gpio32_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio32_mcu_drv:2;
+        /** gpio32_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio32_fun_wpd:1;
+        /** gpio32_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio32_fun_wpu:1;
+        /** gpio32_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio32_fun_ie:1;
+        /** gpio32_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio32_fun_drv:2;
+        /** gpio32_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio32_mcu_sel:3;
+        /** gpio32_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio32_filter_en:1;
+        /** gpio32_rue_i3c : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t gpio32_rue_i3c:1;
+        /** gpio32_ru_i3c : R/W; bitpos: [18:17]; default: 0;
+         *  NA
+         */
+        uint32_t gpio32_ru_i3c:2;
+        /** gpio32_rue_sel_i3c : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t gpio32_rue_sel_i3c:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} io_mux_gpio32_reg_t;
+
+/** Type of gpio33 register
+ *  iomux control register for gpio33
+ */
+typedef union {
+    struct {
+        /** gpio33_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio33_mcu_oe:1;
+        /** gpio33_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio33_slp_sel:1;
+        /** gpio33_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio33_mcu_wpd:1;
+        /** gpio33_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio33_mcu_wpu:1;
+        /** gpio33_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio33_mcu_ie:1;
+        /** gpio33_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio33_mcu_drv:2;
+        /** gpio33_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio33_fun_wpd:1;
+        /** gpio33_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio33_fun_wpu:1;
+        /** gpio33_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio33_fun_ie:1;
+        /** gpio33_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio33_fun_drv:2;
+        /** gpio33_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio33_mcu_sel:3;
+        /** gpio33_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio33_filter_en:1;
+        /** gpio33_rue_i3c : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t gpio33_rue_i3c:1;
+        /** gpio33_ru_i3c : R/W; bitpos: [18:17]; default: 0;
+         *  NA
+         */
+        uint32_t gpio33_ru_i3c:2;
+        /** gpio33_rue_sel_i3c : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t gpio33_rue_sel_i3c:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} io_mux_gpio33_reg_t;
+
+/** Type of gpio34 register
+ *  iomux control register for gpio34
+ */
+typedef union {
+    struct {
+        /** gpio34_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio34_mcu_oe:1;
+        /** gpio34_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio34_slp_sel:1;
+        /** gpio34_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio34_mcu_wpd:1;
+        /** gpio34_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio34_mcu_wpu:1;
+        /** gpio34_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio34_mcu_ie:1;
+        /** gpio34_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio34_mcu_drv:2;
+        /** gpio34_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio34_fun_wpd:1;
+        /** gpio34_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio34_fun_wpu:1;
+        /** gpio34_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio34_fun_ie:1;
+        /** gpio34_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio34_fun_drv:2;
+        /** gpio34_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio34_mcu_sel:3;
+        /** gpio34_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio34_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio34_reg_t;
+
+/** Type of gpio35 register
+ *  iomux control register for gpio35
+ */
+typedef union {
+    struct {
+        /** gpio35_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio35_mcu_oe:1;
+        /** gpio35_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio35_slp_sel:1;
+        /** gpio35_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio35_mcu_wpd:1;
+        /** gpio35_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio35_mcu_wpu:1;
+        /** gpio35_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio35_mcu_ie:1;
+        /** gpio35_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio35_mcu_drv:2;
+        /** gpio35_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio35_fun_wpd:1;
+        /** gpio35_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio35_fun_wpu:1;
+        /** gpio35_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio35_fun_ie:1;
+        /** gpio35_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio35_fun_drv:2;
+        /** gpio35_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio35_mcu_sel:3;
+        /** gpio35_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio35_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio35_reg_t;
+
+/** Type of gpio36 register
+ *  iomux control register for gpio36
+ */
+typedef union {
+    struct {
+        /** gpio36_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio36_mcu_oe:1;
+        /** gpio36_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio36_slp_sel:1;
+        /** gpio36_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio36_mcu_wpd:1;
+        /** gpio36_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio36_mcu_wpu:1;
+        /** gpio36_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio36_mcu_ie:1;
+        /** gpio36_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio36_mcu_drv:2;
+        /** gpio36_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio36_fun_wpd:1;
+        /** gpio36_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio36_fun_wpu:1;
+        /** gpio36_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio36_fun_ie:1;
+        /** gpio36_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio36_fun_drv:2;
+        /** gpio36_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio36_mcu_sel:3;
+        /** gpio36_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio36_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio36_reg_t;
+
+/** Type of gpio37 register
+ *  iomux control register for gpio37
+ */
+typedef union {
+    struct {
+        /** gpio37_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio37_mcu_oe:1;
+        /** gpio37_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio37_slp_sel:1;
+        /** gpio37_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio37_mcu_wpd:1;
+        /** gpio37_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio37_mcu_wpu:1;
+        /** gpio37_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio37_mcu_ie:1;
+        /** gpio37_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio37_mcu_drv:2;
+        /** gpio37_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio37_fun_wpd:1;
+        /** gpio37_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio37_fun_wpu:1;
+        /** gpio37_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio37_fun_ie:1;
+        /** gpio37_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio37_fun_drv:2;
+        /** gpio37_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio37_mcu_sel:3;
+        /** gpio37_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio37_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio37_reg_t;
+
+/** Type of gpio38 register
+ *  iomux control register for gpio38
+ */
+typedef union {
+    struct {
+        /** gpio38_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio38_mcu_oe:1;
+        /** gpio38_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio38_slp_sel:1;
+        /** gpio38_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio38_mcu_wpd:1;
+        /** gpio38_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio38_mcu_wpu:1;
+        /** gpio38_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio38_mcu_ie:1;
+        /** gpio38_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio38_mcu_drv:2;
+        /** gpio38_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio38_fun_wpd:1;
+        /** gpio38_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio38_fun_wpu:1;
+        /** gpio38_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio38_fun_ie:1;
+        /** gpio38_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio38_fun_drv:2;
+        /** gpio38_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio38_mcu_sel:3;
+        /** gpio38_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio38_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio38_reg_t;
+
+/** Type of gpio39 register
+ *  iomux control register for gpio39
+ */
+typedef union {
+    struct {
+        /** gpio39_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio39_mcu_oe:1;
+        /** gpio39_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio39_slp_sel:1;
+        /** gpio39_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio39_mcu_wpd:1;
+        /** gpio39_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio39_mcu_wpu:1;
+        /** gpio39_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio39_mcu_ie:1;
+        /** gpio39_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio39_mcu_drv:2;
+        /** gpio39_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio39_fun_wpd:1;
+        /** gpio39_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio39_fun_wpu:1;
+        /** gpio39_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio39_fun_ie:1;
+        /** gpio39_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio39_fun_drv:2;
+        /** gpio39_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio39_mcu_sel:3;
+        /** gpio39_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio39_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio39_reg_t;
+
+/** Type of gpio40 register
+ *  iomux control register for gpio40
+ */
+typedef union {
+    struct {
+        /** gpio40_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio40_mcu_oe:1;
+        /** gpio40_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio40_slp_sel:1;
+        /** gpio40_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio40_mcu_wpd:1;
+        /** gpio40_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio40_mcu_wpu:1;
+        /** gpio40_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio40_mcu_ie:1;
+        /** gpio40_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio40_mcu_drv:2;
+        /** gpio40_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio40_fun_wpd:1;
+        /** gpio40_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio40_fun_wpu:1;
+        /** gpio40_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio40_fun_ie:1;
+        /** gpio40_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio40_fun_drv:2;
+        /** gpio40_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio40_mcu_sel:3;
+        /** gpio40_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio40_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio40_reg_t;
+
+/** Type of gpio41 register
+ *  iomux control register for gpio41
+ */
+typedef union {
+    struct {
+        /** gpio41_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio41_mcu_oe:1;
+        /** gpio41_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio41_slp_sel:1;
+        /** gpio41_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio41_mcu_wpd:1;
+        /** gpio41_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio41_mcu_wpu:1;
+        /** gpio41_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio41_mcu_ie:1;
+        /** gpio41_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio41_mcu_drv:2;
+        /** gpio41_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio41_fun_wpd:1;
+        /** gpio41_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio41_fun_wpu:1;
+        /** gpio41_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio41_fun_ie:1;
+        /** gpio41_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio41_fun_drv:2;
+        /** gpio41_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio41_mcu_sel:3;
+        /** gpio41_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio41_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio41_reg_t;
+
+/** Type of gpio42 register
+ *  iomux control register for gpio42
+ */
+typedef union {
+    struct {
+        /** gpio42_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio42_mcu_oe:1;
+        /** gpio42_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio42_slp_sel:1;
+        /** gpio42_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio42_mcu_wpd:1;
+        /** gpio42_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio42_mcu_wpu:1;
+        /** gpio42_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio42_mcu_ie:1;
+        /** gpio42_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio42_mcu_drv:2;
+        /** gpio42_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio42_fun_wpd:1;
+        /** gpio42_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio42_fun_wpu:1;
+        /** gpio42_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio42_fun_ie:1;
+        /** gpio42_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio42_fun_drv:2;
+        /** gpio42_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio42_mcu_sel:3;
+        /** gpio42_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio42_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio42_reg_t;
+
+/** Type of gpio43 register
+ *  iomux control register for gpio43
+ */
+typedef union {
+    struct {
+        /** gpio43_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio43_mcu_oe:1;
+        /** gpio43_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio43_slp_sel:1;
+        /** gpio43_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio43_mcu_wpd:1;
+        /** gpio43_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio43_mcu_wpu:1;
+        /** gpio43_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio43_mcu_ie:1;
+        /** gpio43_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio43_mcu_drv:2;
+        /** gpio43_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio43_fun_wpd:1;
+        /** gpio43_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio43_fun_wpu:1;
+        /** gpio43_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio43_fun_ie:1;
+        /** gpio43_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio43_fun_drv:2;
+        /** gpio43_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio43_mcu_sel:3;
+        /** gpio43_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio43_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio43_reg_t;
+
+/** Type of gpio44 register
+ *  iomux control register for gpio44
+ */
+typedef union {
+    struct {
+        /** gpio44_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio44_mcu_oe:1;
+        /** gpio44_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio44_slp_sel:1;
+        /** gpio44_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio44_mcu_wpd:1;
+        /** gpio44_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio44_mcu_wpu:1;
+        /** gpio44_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio44_mcu_ie:1;
+        /** gpio44_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio44_mcu_drv:2;
+        /** gpio44_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio44_fun_wpd:1;
+        /** gpio44_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio44_fun_wpu:1;
+        /** gpio44_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio44_fun_ie:1;
+        /** gpio44_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio44_fun_drv:2;
+        /** gpio44_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio44_mcu_sel:3;
+        /** gpio44_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio44_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio44_reg_t;
+
+/** Type of gpio45 register
+ *  iomux control register for gpio45
+ */
+typedef union {
+    struct {
+        /** gpio45_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio45_mcu_oe:1;
+        /** gpio45_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio45_slp_sel:1;
+        /** gpio45_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio45_mcu_wpd:1;
+        /** gpio45_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio45_mcu_wpu:1;
+        /** gpio45_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio45_mcu_ie:1;
+        /** gpio45_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio45_mcu_drv:2;
+        /** gpio45_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio45_fun_wpd:1;
+        /** gpio45_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio45_fun_wpu:1;
+        /** gpio45_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio45_fun_ie:1;
+        /** gpio45_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio45_fun_drv:2;
+        /** gpio45_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio45_mcu_sel:3;
+        /** gpio45_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio45_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio45_reg_t;
+
+/** Type of gpio46 register
+ *  iomux control register for gpio46
+ */
+typedef union {
+    struct {
+        /** gpio46_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio46_mcu_oe:1;
+        /** gpio46_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio46_slp_sel:1;
+        /** gpio46_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio46_mcu_wpd:1;
+        /** gpio46_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio46_mcu_wpu:1;
+        /** gpio46_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio46_mcu_ie:1;
+        /** gpio46_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio46_mcu_drv:2;
+        /** gpio46_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio46_fun_wpd:1;
+        /** gpio46_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio46_fun_wpu:1;
+        /** gpio46_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio46_fun_ie:1;
+        /** gpio46_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio46_fun_drv:2;
+        /** gpio46_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio46_mcu_sel:3;
+        /** gpio46_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio46_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio46_reg_t;
+
+/** Type of gpio47 register
+ *  iomux control register for gpio47
+ */
+typedef union {
+    struct {
+        /** gpio47_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio47_mcu_oe:1;
+        /** gpio47_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio47_slp_sel:1;
+        /** gpio47_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio47_mcu_wpd:1;
+        /** gpio47_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio47_mcu_wpu:1;
+        /** gpio47_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio47_mcu_ie:1;
+        /** gpio47_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio47_mcu_drv:2;
+        /** gpio47_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio47_fun_wpd:1;
+        /** gpio47_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio47_fun_wpu:1;
+        /** gpio47_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio47_fun_ie:1;
+        /** gpio47_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio47_fun_drv:2;
+        /** gpio47_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio47_mcu_sel:3;
+        /** gpio47_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio47_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio47_reg_t;
+
+/** Type of gpio48 register
+ *  iomux control register for gpio48
+ */
+typedef union {
+    struct {
+        /** gpio48_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio48_mcu_oe:1;
+        /** gpio48_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio48_slp_sel:1;
+        /** gpio48_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio48_mcu_wpd:1;
+        /** gpio48_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio48_mcu_wpu:1;
+        /** gpio48_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio48_mcu_ie:1;
+        /** gpio48_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio48_mcu_drv:2;
+        /** gpio48_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio48_fun_wpd:1;
+        /** gpio48_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio48_fun_wpu:1;
+        /** gpio48_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio48_fun_ie:1;
+        /** gpio48_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio48_fun_drv:2;
+        /** gpio48_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio48_mcu_sel:3;
+        /** gpio48_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio48_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio48_reg_t;
+
+/** Type of gpio49 register
+ *  iomux control register for gpio49
+ */
+typedef union {
+    struct {
+        /** gpio49_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio49_mcu_oe:1;
+        /** gpio49_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio49_slp_sel:1;
+        /** gpio49_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio49_mcu_wpd:1;
+        /** gpio49_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio49_mcu_wpu:1;
+        /** gpio49_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio49_mcu_ie:1;
+        /** gpio49_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio49_mcu_drv:2;
+        /** gpio49_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio49_fun_wpd:1;
+        /** gpio49_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio49_fun_wpu:1;
+        /** gpio49_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio49_fun_ie:1;
+        /** gpio49_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio49_fun_drv:2;
+        /** gpio49_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio49_mcu_sel:3;
+        /** gpio49_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio49_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio49_reg_t;
+
+/** Type of gpio50 register
+ *  iomux control register for gpio50
+ */
+typedef union {
+    struct {
+        /** gpio50_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio50_mcu_oe:1;
+        /** gpio50_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio50_slp_sel:1;
+        /** gpio50_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio50_mcu_wpd:1;
+        /** gpio50_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio50_mcu_wpu:1;
+        /** gpio50_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio50_mcu_ie:1;
+        /** gpio50_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio50_mcu_drv:2;
+        /** gpio50_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio50_fun_wpd:1;
+        /** gpio50_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio50_fun_wpu:1;
+        /** gpio50_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio50_fun_ie:1;
+        /** gpio50_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio50_fun_drv:2;
+        /** gpio50_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio50_mcu_sel:3;
+        /** gpio50_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio50_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio50_reg_t;
+
+/** Type of gpio51 register
+ *  iomux control register for gpio51
+ */
+typedef union {
+    struct {
+        /** gpio51_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio51_mcu_oe:1;
+        /** gpio51_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio51_slp_sel:1;
+        /** gpio51_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio51_mcu_wpd:1;
+        /** gpio51_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio51_mcu_wpu:1;
+        /** gpio51_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio51_mcu_ie:1;
+        /** gpio51_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio51_mcu_drv:2;
+        /** gpio51_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio51_fun_wpd:1;
+        /** gpio51_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio51_fun_wpu:1;
+        /** gpio51_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio51_fun_ie:1;
+        /** gpio51_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio51_fun_drv:2;
+        /** gpio51_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio51_mcu_sel:3;
+        /** gpio51_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio51_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio51_reg_t;
+
+/** Type of gpio52 register
+ *  iomux control register for gpio52
+ */
+typedef union {
+    struct {
+        /** gpio52_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio52_mcu_oe:1;
+        /** gpio52_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio52_slp_sel:1;
+        /** gpio52_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio52_mcu_wpd:1;
+        /** gpio52_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio52_mcu_wpu:1;
+        /** gpio52_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio52_mcu_ie:1;
+        /** gpio52_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio52_mcu_drv:2;
+        /** gpio52_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio52_fun_wpd:1;
+        /** gpio52_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio52_fun_wpu:1;
+        /** gpio52_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio52_fun_ie:1;
+        /** gpio52_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio52_fun_drv:2;
+        /** gpio52_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio52_mcu_sel:3;
+        /** gpio52_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio52_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio52_reg_t;
+
+/** Type of gpio53 register
+ *  iomux control register for gpio53
+ */
+typedef union {
+    struct {
+        /** gpio53_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio53_mcu_oe:1;
+        /** gpio53_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio53_slp_sel:1;
+        /** gpio53_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio53_mcu_wpd:1;
+        /** gpio53_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio53_mcu_wpu:1;
+        /** gpio53_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio53_mcu_ie:1;
+        /** gpio53_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio53_mcu_drv:2;
+        /** gpio53_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio53_fun_wpd:1;
+        /** gpio53_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio53_fun_wpu:1;
+        /** gpio53_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio53_fun_ie:1;
+        /** gpio53_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio53_fun_drv:2;
+        /** gpio53_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio53_mcu_sel:3;
+        /** gpio53_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio53_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio53_reg_t;
+
+/** Type of gpio54 register
+ *  iomux control register for gpio54
+ */
+typedef union {
+    struct {
+        /** gpio54_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio54_mcu_oe:1;
+        /** gpio54_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio54_slp_sel:1;
+        /** gpio54_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio54_mcu_wpd:1;
+        /** gpio54_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio54_mcu_wpu:1;
+        /** gpio54_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio54_mcu_ie:1;
+        /** gpio54_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio54_mcu_drv:2;
+        /** gpio54_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio54_fun_wpd:1;
+        /** gpio54_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio54_fun_wpu:1;
+        /** gpio54_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio54_fun_ie:1;
+        /** gpio54_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio54_fun_drv:2;
+        /** gpio54_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio54_mcu_sel:3;
+        /** gpio54_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio54_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio54_reg_t;
+
+/** Type of gpio55 register
+ *  iomux control register for gpio55
+ */
+typedef union {
+    struct {
+        /** gpio55_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio55_mcu_oe:1;
+        /** gpio55_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio55_slp_sel:1;
+        /** gpio55_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio55_mcu_wpd:1;
+        /** gpio55_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio55_mcu_wpu:1;
+        /** gpio55_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio55_mcu_ie:1;
+        /** gpio55_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio55_mcu_drv:2;
+        /** gpio55_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio55_fun_wpd:1;
+        /** gpio55_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio55_fun_wpu:1;
+        /** gpio55_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio55_fun_ie:1;
+        /** gpio55_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio55_fun_drv:2;
+        /** gpio55_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio55_mcu_sel:3;
+        /** gpio55_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio55_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio55_reg_t;
+
+/** Type of gpio56 register
+ *  iomux control register for gpio56
+ */
+typedef union {
+    struct {
+        /** gpio56_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t gpio56_mcu_oe:1;
+        /** gpio56_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t gpio56_slp_sel:1;
+        /** gpio56_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t gpio56_mcu_wpd:1;
+        /** gpio56_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t gpio56_mcu_wpu:1;
+        /** gpio56_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t gpio56_mcu_ie:1;
+        /** gpio56_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t gpio56_mcu_drv:2;
+        /** gpio56_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t gpio56_fun_wpd:1;
+        /** gpio56_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t gpio56_fun_wpu:1;
+        /** gpio56_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t gpio56_fun_ie:1;
+        /** gpio56_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t gpio56_fun_drv:2;
+        /** gpio56_mcu_sel : R/W; bitpos: [14:12]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t gpio56_mcu_sel:3;
+        /** gpio56_filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t gpio56_filter_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} io_mux_gpio56_reg_t;
+
+/** Type of date register
+ *  iomux version
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2101794;
+         *  csv date
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} io_mux_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile io_mux_gpio0_reg_t gpio0;
+    volatile io_mux_gpio1_reg_t gpio1;
+    volatile io_mux_gpio2_reg_t gpio2;
+    volatile io_mux_gpio3_reg_t gpio3;
+    volatile io_mux_gpio4_reg_t gpio4;
+    volatile io_mux_gpio5_reg_t gpio5;
+    volatile io_mux_gpio6_reg_t gpio6;
+    volatile io_mux_gpio7_reg_t gpio7;
+    volatile io_mux_gpio8_reg_t gpio8;
+    volatile io_mux_gpio9_reg_t gpio9;
+    volatile io_mux_gpio10_reg_t gpio10;
+    volatile io_mux_gpio11_reg_t gpio11;
+    volatile io_mux_gpio12_reg_t gpio12;
+    volatile io_mux_gpio13_reg_t gpio13;
+    volatile io_mux_gpio14_reg_t gpio14;
+    volatile io_mux_gpio15_reg_t gpio15;
+    volatile io_mux_gpio16_reg_t gpio16;
+    volatile io_mux_gpio17_reg_t gpio17;
+    volatile io_mux_gpio18_reg_t gpio18;
+    volatile io_mux_gpio19_reg_t gpio19;
+    volatile io_mux_gpio20_reg_t gpio20;
+    volatile io_mux_gpio21_reg_t gpio21;
+    volatile io_mux_gpio22_reg_t gpio22;
+    volatile io_mux_gpio23_reg_t gpio23;
+    volatile io_mux_gpio24_reg_t gpio24;
+    volatile io_mux_gpio25_reg_t gpio25;
+    volatile io_mux_gpio26_reg_t gpio26;
+    volatile io_mux_gpio27_reg_t gpio27;
+    volatile io_mux_gpio28_reg_t gpio28;
+    volatile io_mux_gpio29_reg_t gpio29;
+    volatile io_mux_gpio30_reg_t gpio30;
+    volatile io_mux_gpio31_reg_t gpio31;
+    volatile io_mux_gpio32_reg_t gpio32;
+    volatile io_mux_gpio33_reg_t gpio33;
+    volatile io_mux_gpio34_reg_t gpio34;
+    volatile io_mux_gpio35_reg_t gpio35;
+    volatile io_mux_gpio36_reg_t gpio36;
+    volatile io_mux_gpio37_reg_t gpio37;
+    volatile io_mux_gpio38_reg_t gpio38;
+    volatile io_mux_gpio39_reg_t gpio39;
+    volatile io_mux_gpio40_reg_t gpio40;
+    volatile io_mux_gpio41_reg_t gpio41;
+    volatile io_mux_gpio42_reg_t gpio42;
+    volatile io_mux_gpio43_reg_t gpio43;
+    volatile io_mux_gpio44_reg_t gpio44;
+    volatile io_mux_gpio45_reg_t gpio45;
+    volatile io_mux_gpio46_reg_t gpio46;
+    volatile io_mux_gpio47_reg_t gpio47;
+    volatile io_mux_gpio48_reg_t gpio48;
+    volatile io_mux_gpio49_reg_t gpio49;
+    volatile io_mux_gpio50_reg_t gpio50;
+    volatile io_mux_gpio51_reg_t gpio51;
+    volatile io_mux_gpio52_reg_t gpio52;
+    volatile io_mux_gpio53_reg_t gpio53;
+    volatile io_mux_gpio54_reg_t gpio54;
+    volatile io_mux_gpio55_reg_t gpio55;
+    volatile io_mux_gpio56_reg_t gpio56;
+    uint32_t reserved_0e8[7];
+    volatile io_mux_date_reg_t date;
+} io_mux_dev_t;
+
+extern io_mux_dev_t IO_MUX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h
new file mode 100644
index 0000000000..b8eac91be1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h
@@ -0,0 +1,524 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include "soc/soc.h"
+
+//TODO: IDF-13419
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
+
+#define IO_MUX_GPIO0_REG                    PERIPHS_IO_MUX_U_PAD_GPIO0
+#define IO_MUX_GPIO1_REG                    PERIPHS_IO_MUX_U_PAD_GPIO1
+#define IO_MUX_GPIO2_REG                    PERIPHS_IO_MUX_U_PAD_GPIO2
+#define IO_MUX_GPIO3_REG                    PERIPHS_IO_MUX_U_PAD_GPIO3
+#define IO_MUX_GPIO4_REG                    PERIPHS_IO_MUX_U_PAD_GPIO4
+#define IO_MUX_GPIO5_REG                    PERIPHS_IO_MUX_U_PAD_GPIO5
+#define IO_MUX_GPIO6_REG                    PERIPHS_IO_MUX_U_PAD_GPIO6
+#define IO_MUX_GPIO7_REG                    PERIPHS_IO_MUX_U_PAD_GPIO7
+#define IO_MUX_GPIO8_REG                    PERIPHS_IO_MUX_U_PAD_GPIO8
+#define IO_MUX_GPIO9_REG                    PERIPHS_IO_MUX_U_PAD_GPIO9
+#define IO_MUX_GPIO10_REG                   PERIPHS_IO_MUX_U_PAD_GPIO10
+#define IO_MUX_GPIO11_REG                   PERIPHS_IO_MUX_U_PAD_GPIO11
+#define IO_MUX_GPIO12_REG                   PERIPHS_IO_MUX_U_PAD_GPIO12
+#define IO_MUX_GPIO13_REG                   PERIPHS_IO_MUX_U_PAD_GPIO13
+#define IO_MUX_GPIO14_REG                   PERIPHS_IO_MUX_U_PAD_GPIO14
+#define IO_MUX_GPIO15_REG                   PERIPHS_IO_MUX_U_PAD_GPIO15
+#define IO_MUX_GPIO16_REG                   PERIPHS_IO_MUX_U_PAD_GPIO16
+#define IO_MUX_GPIO17_REG                   PERIPHS_IO_MUX_U_PAD_GPIO17
+#define IO_MUX_GPIO18_REG                   PERIPHS_IO_MUX_U_PAD_GPIO18
+#define IO_MUX_GPIO19_REG                   PERIPHS_IO_MUX_U_PAD_GPIO19
+#define IO_MUX_GPIO20_REG                   PERIPHS_IO_MUX_U_PAD_GPIO20
+#define IO_MUX_GPIO21_REG                   PERIPHS_IO_MUX_U_PAD_GPIO21
+#define IO_MUX_GPIO22_REG                   PERIPHS_IO_MUX_U_PAD_GPIO22
+#define IO_MUX_GPIO23_REG                   PERIPHS_IO_MUX_U_PAD_GPIO23
+#define IO_MUX_GPIO24_REG                   PERIPHS_IO_MUX_U_PAD_GPIO24
+#define IO_MUX_GPIO25_REG                   PERIPHS_IO_MUX_U_PAD_GPIO25
+#define IO_MUX_GPIO26_REG                   PERIPHS_IO_MUX_U_PAD_GPIO26
+#define IO_MUX_GPIO27_REG                   PERIPHS_IO_MUX_U_PAD_GPIO27
+#define IO_MUX_GPIO28_REG                   PERIPHS_IO_MUX_U_PAD_GPIO28
+#define IO_MUX_GPIO29_REG                   PERIPHS_IO_MUX_U_PAD_GPIO29
+#define IO_MUX_GPIO30_REG                   PERIPHS_IO_MUX_U_PAD_GPIO30
+#define IO_MUX_GPIO31_REG                   PERIPHS_IO_MUX_U_PAD_GPIO31
+#define IO_MUX_GPIO32_REG                   PERIPHS_IO_MUX_U_PAD_GPIO32
+#define IO_MUX_GPIO33_REG                   PERIPHS_IO_MUX_U_PAD_GPIO33
+#define IO_MUX_GPIO34_REG                   PERIPHS_IO_MUX_U_PAD_GPIO34
+#define IO_MUX_GPIO35_REG                   PERIPHS_IO_MUX_U_PAD_GPIO35
+#define IO_MUX_GPIO36_REG                   PERIPHS_IO_MUX_U_PAD_GPIO36
+#define IO_MUX_GPIO37_REG                   PERIPHS_IO_MUX_U_PAD_GPIO37
+#define IO_MUX_GPIO38_REG                   PERIPHS_IO_MUX_U_PAD_GPIO38
+#define IO_MUX_GPIO39_REG                   PERIPHS_IO_MUX_U_PAD_GPIO39
+#define IO_MUX_GPIO40_REG                   PERIPHS_IO_MUX_U_PAD_GPIO40
+#define IO_MUX_GPIO41_REG                   PERIPHS_IO_MUX_U_PAD_GPIO41
+#define IO_MUX_GPIO42_REG                   PERIPHS_IO_MUX_U_PAD_GPIO42
+#define IO_MUX_GPIO43_REG                   PERIPHS_IO_MUX_U_PAD_GPIO43
+#define IO_MUX_GPIO44_REG                   PERIPHS_IO_MUX_U_PAD_GPIO44
+#define IO_MUX_GPIO45_REG                   PERIPHS_IO_MUX_U_PAD_GPIO45
+#define IO_MUX_GPIO46_REG                   PERIPHS_IO_MUX_U_PAD_GPIO46
+#define IO_MUX_GPIO47_REG                   PERIPHS_IO_MUX_U_PAD_GPIO47
+#define IO_MUX_GPIO48_REG                   PERIPHS_IO_MUX_U_PAD_GPIO48
+#define IO_MUX_GPIO49_REG                   PERIPHS_IO_MUX_U_PAD_GPIO49
+#define IO_MUX_GPIO50_REG                   PERIPHS_IO_MUX_U_PAD_GPIO50
+#define IO_MUX_GPIO51_REG                   PERIPHS_IO_MUX_U_PAD_GPIO51
+#define IO_MUX_GPIO52_REG                   PERIPHS_IO_MUX_U_PAD_GPIO52
+#define IO_MUX_GPIO53_REG                   PERIPHS_IO_MUX_U_PAD_GPIO53
+#define IO_MUX_GPIO54_REG                   PERIPHS_IO_MUX_U_PAD_GPIO54
+
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+// TODO: IDF-7499, IDF-7495
+// SPI pins defined here are all wrong. On P4, these pins are individual pins, don't use normal GPIO pins anymore.
+// Please check iomux_mspi_pin_struct/reg.h
+#include "soc/gpio_num.h"
+#define SPI_CS1_GPIO_NUM GPIO_NUM_MAX
+#define SPI_HD_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_WP_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_CS0_GPIO_NUM GPIO_NUM_MAX
+#define SPI_CLK_GPIO_NUM GPIO_NUM_MAX
+#define SPI_Q_GPIO_NUM   GPIO_NUM_MAX
+#define SPI_D_GPIO_NUM   GPIO_NUM_MAX
+#define SPI_D4_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_D5_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_D6_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_D7_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_DQS_GPIO_NUM GPIO_NUM_MAX
+
+#define SD_CLK_GPIO_NUM           43
+#define SD_CMD_GPIO_NUM           44
+#define SD_DATA0_GPIO_NUM         39
+#define SD_DATA1_GPIO_NUM         40
+#define SD_DATA2_GPIO_NUM         41
+#define SD_DATA3_GPIO_NUM         42
+#define SD_DATA4_GPIO_NUM         45
+#define SD_DATA5_GPIO_NUM         46
+#define SD_DATA6_GPIO_NUM         47
+#define SD_DATA7_GPIO_NUM         48
+
+#define USB_INT_PHY0_DM_GPIO_NUM  24
+#define USB_INT_PHY0_DP_GPIO_NUM  25
+#define USB_INT_PHY1_DM_GPIO_NUM  26
+#define USB_INT_PHY1_DP_GPIO_NUM  27
+
+// We would fix the USB PHY usage on P4: PHY0 -> USJ, PHY1 -> USB_OTG
+#define USB_USJ_INT_PHY_DM_GPIO_NUM     USB_INT_PHY0_DM_GPIO_NUM
+#define USB_USJ_INT_PHY_DP_GPIO_NUM     USB_INT_PHY0_DP_GPIO_NUM
+#define USB_OTG_INT_PHY_DM_GPIO_NUM     USB_INT_PHY1_DM_GPIO_NUM
+#define USB_OTG_INT_PHY_DP_GPIO_NUM     USB_INT_PHY1_DP_GPIO_NUM
+
+#define MAX_RTC_GPIO_NUM             15
+#define MAX_PAD_GPIO_NUM             54
+#define MAX_GPIO_NUM                 56
+
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+
+// definitions below are generated from pin_txt.csv
+#define PERIPHS_IO_MUX_U_PAD_GPIO0                 (REG_IO_MUX_BASE + 0x4)
+#define FUNC_GPIO0_GPIO0                                                 1
+#define FUNC_GPIO0_GPIO0_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO1                 (REG_IO_MUX_BASE + 0x8)
+#define FUNC_GPIO1_GPIO1                                                 1
+#define FUNC_GPIO1_GPIO1_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO2                 (REG_IO_MUX_BASE + 0xC)
+#define FUNC_GPIO2_GPIO2                                                 1
+#define FUNC_GPIO2_MTCK                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO3                (REG_IO_MUX_BASE + 0x10)
+#define FUNC_GPIO3_GPIO3                                                 1
+#define FUNC_GPIO3_MTDI                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO4                (REG_IO_MUX_BASE + 0x14)
+#define FUNC_GPIO4_GPIO4                                                 1
+#define FUNC_GPIO4_MTMS                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO5                (REG_IO_MUX_BASE + 0x18)
+#define FUNC_GPIO5_GPIO5                                                 1
+#define FUNC_GPIO5_MTDO                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO6                (REG_IO_MUX_BASE + 0x1C)
+#define FUNC_GPIO6_SPI2_HOLD_PAD                                         3
+#define FUNC_GPIO6_GPIO6                                                 1
+#define FUNC_GPIO6_GPIO6_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO7                (REG_IO_MUX_BASE + 0x20)
+#define FUNC_GPIO7_SPI2_CS_PAD                                           3
+#define FUNC_GPIO7_GPIO7                                                 1
+#define FUNC_GPIO7_GPIO7_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO8                (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO8_SPI2_D_PAD                                            3
+#define FUNC_GPIO8_UART0_RTS_PAD                                         2
+#define FUNC_GPIO8_GPIO8                                                 1
+#define FUNC_GPIO8_GPIO8_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO9                (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO9_SPI2_CK_PAD                                           3
+#define FUNC_GPIO9_UART0_CTS_PAD                                         2
+#define FUNC_GPIO9_GPIO9                                                 1
+#define FUNC_GPIO9_GPIO9_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO10               (REG_IO_MUX_BASE + 0x2C)
+#define FUNC_GPIO10_SPI2_Q_PAD                                           3
+#define FUNC_GPIO10_UART1_TXD_PAD                                        2
+#define FUNC_GPIO10_GPIO10                                               1
+#define FUNC_GPIO10_GPIO10_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO11               (REG_IO_MUX_BASE + 0x30)
+#define FUNC_GPIO11_SPI2_WP_PAD                                          3
+#define FUNC_GPIO11_UART1_RXD_PAD                                        2
+#define FUNC_GPIO11_GPIO11                                               1
+#define FUNC_GPIO11_GPIO11_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO12               (REG_IO_MUX_BASE + 0x34)
+#define FUNC_GPIO12_UART1_RTS_PAD                                        2
+#define FUNC_GPIO12_GPIO12                                               1
+#define FUNC_GPIO12_GPIO12_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO13               (REG_IO_MUX_BASE + 0x38)
+#define FUNC_GPIO13_UART1_CTS_PAD                                        2
+#define FUNC_GPIO13_GPIO13                                               1
+#define FUNC_GPIO13_GPIO13_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO14               (REG_IO_MUX_BASE + 0x3C)
+#define FUNC_GPIO14_GPIO14                                               1
+#define FUNC_GPIO14_GPIO14_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO15               (REG_IO_MUX_BASE + 0x40)
+#define FUNC_GPIO15_GPIO15                                               1
+#define FUNC_GPIO15_GPIO15_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO16               (REG_IO_MUX_BASE + 0x44)
+#define FUNC_GPIO16_GPIO16                                               1
+#define FUNC_GPIO16_GPIO16_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO17               (REG_IO_MUX_BASE + 0x48)
+#define FUNC_GPIO17_GPIO17                                               1
+#define FUNC_GPIO17_GPIO17_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO18               (REG_IO_MUX_BASE + 0x4C)
+#define FUNC_GPIO18_GPIO18                                               1
+#define FUNC_GPIO18_GPIO18_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO19               (REG_IO_MUX_BASE + 0x50)
+#define FUNC_GPIO19_GPIO19                                               1
+#define FUNC_GPIO19_GPIO19_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO20               (REG_IO_MUX_BASE + 0x54)
+#define FUNC_GPIO20_GPIO20                                               1
+#define FUNC_GPIO20_GPIO20_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO21               (REG_IO_MUX_BASE + 0x58)
+#define FUNC_GPIO21_GPIO21                                               1
+#define FUNC_GPIO21_GPIO21_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO22               (REG_IO_MUX_BASE + 0x5C)
+#define FUNC_GPIO22_DBG_PSRAM_CK_PAD                                     4
+#define FUNC_GPIO22_GPIO22                                               1
+#define FUNC_GPIO22_GPIO22_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO23               (REG_IO_MUX_BASE + 0x60)
+#define FUNC_GPIO23_DBG_PSRAM_CS_PAD                                     4
+#define FUNC_GPIO23_REF_50M_CLK_PAD                                      3
+#define FUNC_GPIO23_GPIO23                                               1
+#define FUNC_GPIO23_GPIO23_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO24               (REG_IO_MUX_BASE + 0x64)
+#define FUNC_GPIO24_GPIO24                                               1
+#define FUNC_GPIO24_GPIO24_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO25               (REG_IO_MUX_BASE + 0x68)
+#define FUNC_GPIO25_GPIO25                                               1
+#define FUNC_GPIO25_GPIO25_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO26               (REG_IO_MUX_BASE + 0x6C)
+#define FUNC_GPIO26_GPIO26                                               1
+#define FUNC_GPIO26_GPIO26_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO27               (REG_IO_MUX_BASE + 0x70)
+#define FUNC_GPIO27_GPIO27                                               1
+#define FUNC_GPIO27_GPIO27_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO28               (REG_IO_MUX_BASE + 0x74)
+#define FUNC_GPIO28_DBG_PSRAM_D_PAD                                      4
+#define FUNC_GPIO28_EMAC_PHY_RXDV_PAD                                    3
+#define FUNC_GPIO28_SPI2_CS_PAD                                          2
+#define FUNC_GPIO28_GPIO28                                               1
+#define FUNC_GPIO28_GPIO28_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO29               (REG_IO_MUX_BASE + 0x78)
+#define FUNC_GPIO29_DBG_PSRAM_Q_PAD                                      4
+#define FUNC_GPIO29_EMAC_PHY_RXD0_PAD                                    3
+#define FUNC_GPIO29_SPI2_D_PAD                                           2
+#define FUNC_GPIO29_GPIO29                                               1
+#define FUNC_GPIO29_GPIO29_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO30               (REG_IO_MUX_BASE + 0x7C)
+#define FUNC_GPIO30_DBG_PSRAM_WP_PAD                                     4
+#define FUNC_GPIO30_EMAC_PHY_RXD1_PAD                                    3
+#define FUNC_GPIO30_SPI2_CK_PAD                                          2
+#define FUNC_GPIO30_GPIO30                                               1
+#define FUNC_GPIO30_GPIO30_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO31               (REG_IO_MUX_BASE + 0x80)
+#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD                                   4
+#define FUNC_GPIO31_EMAC_PHY_RXER_PAD                                    3
+#define FUNC_GPIO31_SPI2_Q_PAD                                           2
+#define FUNC_GPIO31_GPIO31                                               1
+#define FUNC_GPIO31_GPIO31_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO32               (REG_IO_MUX_BASE + 0x84)
+#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD                                    4
+#define FUNC_GPIO32_EMAC_RMII_CLK_PAD                                    3
+#define FUNC_GPIO32_SPI2_HOLD_PAD                                        2
+#define FUNC_GPIO32_GPIO32                                               1
+#define FUNC_GPIO32_GPIO32_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO33               (REG_IO_MUX_BASE + 0x88)
+#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD                                    4
+#define FUNC_GPIO33_EMAC_PHY_TXEN_PAD                                    3
+#define FUNC_GPIO33_SPI2_WP_PAD                                          2
+#define FUNC_GPIO33_GPIO33                                               1
+#define FUNC_GPIO33_GPIO33_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO34               (REG_IO_MUX_BASE + 0x8C)
+#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD                                    4
+#define FUNC_GPIO34_EMAC_PHY_TXD0_PAD                                    3
+#define FUNC_GPIO34_SPI2_IO4_PAD                                         2
+#define FUNC_GPIO34_GPIO34                                               1
+#define FUNC_GPIO34_GPIO34_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO35               (REG_IO_MUX_BASE + 0x90)
+#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD                                    4
+#define FUNC_GPIO35_EMAC_PHY_TXD1_PAD                                    3
+#define FUNC_GPIO35_SPI2_IO5_PAD                                         2
+#define FUNC_GPIO35_GPIO35                                               1
+#define FUNC_GPIO35_GPIO35_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO36               (REG_IO_MUX_BASE + 0x94)
+#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD                                  4
+#define FUNC_GPIO36_EMAC_PHY_TXER_PAD                                    3
+#define FUNC_GPIO36_SPI2_IO6_PAD                                         2
+#define FUNC_GPIO36_GPIO36                                               1
+#define FUNC_GPIO36_GPIO36_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO37               (REG_IO_MUX_BASE + 0x98)
+#define FUNC_GPIO37_SPI2_IO7_PAD                                         2
+#define FUNC_GPIO37_GPIO37                                               1
+#define FUNC_GPIO37_UART0_TXD_PAD                                        0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO38               (REG_IO_MUX_BASE + 0x9C)
+#define FUNC_GPIO38_SPI2_DQS_PAD                                         2
+#define FUNC_GPIO38_GPIO38                                               1
+#define FUNC_GPIO38_UART0_RXD_PAD                                        0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO39               (REG_IO_MUX_BASE + 0xA0)
+#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD                                    4
+#define FUNC_GPIO39_REF_50M_CLK_PAD                                      3
+#define FUNC_GPIO39_BIST_PAD                                             2
+#define FUNC_GPIO39_GPIO39                                               1
+#define FUNC_GPIO39_SD1_CDATA0_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO40               (REG_IO_MUX_BASE + 0xA4)
+#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD                                    4
+#define FUNC_GPIO40_EMAC_PHY_TXEN_PAD                                    3
+#define FUNC_GPIO40_BIST_PAD                                             2
+#define FUNC_GPIO40_GPIO40                                               1
+#define FUNC_GPIO40_SD1_CDATA1_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO41               (REG_IO_MUX_BASE + 0xA8)
+#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD                                   4
+#define FUNC_GPIO41_EMAC_PHY_TXD0_PAD                                    3
+#define FUNC_GPIO41_BIST_PAD                                             2
+#define FUNC_GPIO41_GPIO41                                               1
+#define FUNC_GPIO41_SD1_CDATA2_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO42               (REG_IO_MUX_BASE + 0xAC)
+#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD                                   4
+#define FUNC_GPIO42_EMAC_PHY_TXD1_PAD                                    3
+#define FUNC_GPIO42_BIST_PAD                                             2
+#define FUNC_GPIO42_GPIO42                                               1
+#define FUNC_GPIO42_SD1_CDATA3_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO43               (REG_IO_MUX_BASE + 0xB0)
+#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD                                   4
+#define FUNC_GPIO43_EMAC_PHY_TXER_PAD                                    3
+#define FUNC_GPIO43_BIST_PAD                                             2
+#define FUNC_GPIO43_GPIO43                                               1
+#define FUNC_GPIO43_SD1_CCLK_PAD                                         0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO44               (REG_IO_MUX_BASE + 0xB4)
+#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD                                   4
+#define FUNC_GPIO44_EMAC_RMII_CLK_PAD                                    3
+#define FUNC_GPIO44_BIST_PAD                                             2
+#define FUNC_GPIO44_GPIO44                                               1
+#define FUNC_GPIO44_SD1_CCMD_PAD                                         0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO45               (REG_IO_MUX_BASE + 0xB8)
+#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD                                   4
+#define FUNC_GPIO45_EMAC_PHY_RXDV_PAD                                    3
+#define FUNC_GPIO45_BIST_PAD                                             2
+#define FUNC_GPIO45_GPIO45                                               1
+#define FUNC_GPIO45_SD1_CDATA4_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO46               (REG_IO_MUX_BASE + 0xBC)
+#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD                                   4
+#define FUNC_GPIO46_EMAC_PHY_RXD0_PAD                                    3
+#define FUNC_GPIO46_BIST_PAD                                             2
+#define FUNC_GPIO46_GPIO46                                               1
+#define FUNC_GPIO46_SD1_CDATA5_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO47               (REG_IO_MUX_BASE + 0xC0)
+#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD                                  4
+#define FUNC_GPIO47_EMAC_PHY_RXD1_PAD                                    3
+#define FUNC_GPIO47_BIST_PAD                                             2
+#define FUNC_GPIO47_GPIO47                                               1
+#define FUNC_GPIO47_SD1_CDATA6_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO48               (REG_IO_MUX_BASE + 0xC4)
+#define FUNC_GPIO48_EMAC_PHY_RXER_PAD                                    3
+#define FUNC_GPIO48_BIST_PAD                                             2
+#define FUNC_GPIO48_GPIO48                                               1
+#define FUNC_GPIO48_SD1_CDATA7_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO49               (REG_IO_MUX_BASE + 0xC8)
+#define FUNC_GPIO49_DBG_FLASH_CS_PAD                                      4
+#define FUNC_GPIO49_EMAC_PHY_TXEN_PAD                                    3
+#define FUNC_GPIO49_GPIO49                                               1
+#define FUNC_GPIO49_GPIO49_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO50               (REG_IO_MUX_BASE + 0xCC)
+#define FUNC_GPIO50_DBG_FLASH_Q_PAD                                       4
+#define FUNC_GPIO50_EMAC_RMII_CLK_PAD                                    3
+#define FUNC_GPIO50_GPIO50                                               1
+#define FUNC_GPIO50_GPIO50_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO51               (REG_IO_MUX_BASE + 0xD0)
+#define FUNC_GPIO51_DBG_FLASH_WP_PAD                                     4
+#define FUNC_GPIO51_EMAC_PHY_RXDV_PAD                                    3
+#define FUNC_GPIO51_GPIO51                                               1
+#define FUNC_GPIO51_GPIO51_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO52               (REG_IO_MUX_BASE + 0xD4)
+#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD                                   4
+#define FUNC_GPIO52_EMAC_PHY_RXD0_PAD                                    3
+#define FUNC_GPIO52_GPIO52                                               1
+#define FUNC_GPIO52_GPIO52_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO53               (REG_IO_MUX_BASE + 0xD8)
+#define FUNC_GPIO53_DBG_FLASH_CK_PAD                                      4
+#define FUNC_GPIO53_EMAC_PHY_RXD1_PAD                                    3
+#define FUNC_GPIO53_GPIO53                                               1
+#define FUNC_GPIO53_GPIO53_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO54               (REG_IO_MUX_BASE + 0xDC)
+#define FUNC_GPIO54_DBG_FLASH_D_PAD                                       4
+#define FUNC_GPIO54_EMAC_PHY_RXER_PAD                                    3
+#define FUNC_GPIO54_GPIO54                                               1
+#define FUNC_GPIO54_GPIO54_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO55               (REG_IO_MUX_BASE + 0xE0)
+#define FUNC_GPIO55_GPIO55                                               1
+#define FUNC_GPIO55_GPIO55_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO56               (REG_IO_MUX_BASE + 0xE4)
+#define FUNC_GPIO56_GPIO56                                               1
+#define FUNC_GPIO56_GPIO56_0                                             0
+
+#define IO_MUX_DATE_REG          (REG_IO_MUX_BASE + 0x104)
+/* IO_MUX_DATE : R/W ;bitpos:[27:0] ;default: 27'h0201222 ; */
+/*description: csv date.*/
+#define IO_MUX_DATE    0x0FFFFFFF
+#define IO_MUX_DATE_M  ((IO_MUX_DATE_V)<<(IO_MUX_DATE_S))
+#define IO_MUX_DATE_V  0xFFFFFFF
+#define IO_MUX_DATE_S  0
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h
new file mode 100644
index 0000000000..b2b0e66306
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h
@@ -0,0 +1,102 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13419
+/** Type of GPIO register
+ *  IO MUX gpio configuration register
+ */
+typedef union {
+    struct {
+        /** mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t mcu_oe:1;
+        /** slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t slp_sel:1;
+        /** mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t mcu_wpd:1;
+        /** mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t mcu_wpu:1;
+        /** mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t mcu_ie:1;
+        /** mcu_drv : R/W; bitpos: [5:6]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t mcu_drv:2;
+        /** fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t fun_wpd:1;
+        /** fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t fun_wpu:1;
+        /** fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t fun_ie:1;
+        /** fun_drv : R/W; bitpos: [10:11]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t fun_drv:2;
+        /** mcu_sel : R/W; bitpos: [12:14]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t mcu_sel:3;
+        /** filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t filter_en:1;
+        uint32_t reserved16 :16;
+    };
+    uint32_t val;
+} io_mux_gpio_reg_t;
+
+/** Type of date register
+ *  IO_MUX version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2101794;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} io_mux_date_reg_t;
+
+
+typedef struct io_mux_dev_t {
+    uint32_t reserved_0;
+    volatile io_mux_gpio_reg_t gpio[57];
+    uint32_t reserved_e8[7];
+    volatile io_mux_date_reg_t date;
+} io_mux_dev_t;
+
+extern io_mux_dev_t IO_MUX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/iomux_mspi_pin_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/iomux_mspi_pin_reg.h
new file mode 100644
index 0000000000..db2188d109
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/iomux_mspi_pin_reg.h
@@ -0,0 +1,1391 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** IOMUX_MSPI_PIN_CLK_EN0_REG register
+ *  apb registers auto clock gating reg
+ */
+#define IOMUX_MSPI_PIN_CLK_EN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x0)
+/** IOMUX_MSPI_PIN_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  1: auto clock gating on
+ *  0: auto clock gating off
+ */
+#define IOMUX_MSPI_PIN_REG_CLK_EN    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_CLK_EN_M  (IOMUX_MSPI_PIN_REG_CLK_EN_V << IOMUX_MSPI_PIN_REG_CLK_EN_S)
+#define IOMUX_MSPI_PIN_REG_CLK_EN_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_CLK_EN_S  0
+
+/** IOMUX_MSPI_PIN_FLASH_CS_PIN0_REG register
+ *  IOMUX_MSPI_PIN_FLASH_CS_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_FLASH_CS_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x4)
+/** IOMUX_MSPI_PIN_REG_FLASH_CS_HYS : R/W; bitpos: [0]; default: 0;
+ *  flash cs hys
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_HYS    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_HYS_M  (IOMUX_MSPI_PIN_REG_FLASH_CS_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_CS_HYS_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_HYS_S  0
+/** IOMUX_MSPI_PIN_REG_FLASH_CS_IE : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_IE    (BIT(1))
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_IE_M  (IOMUX_MSPI_PIN_REG_FLASH_CS_IE_V << IOMUX_MSPI_PIN_REG_FLASH_CS_IE_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_IE_S  1
+/** IOMUX_MSPI_PIN_REG_FLASH_CS_WPU : R/W; bitpos: [2]; default: 0;
+ *  flash cs wpu
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPU    (BIT(2))
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPU_M  (IOMUX_MSPI_PIN_REG_FLASH_CS_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_CS_WPU_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPU_S  2
+/** IOMUX_MSPI_PIN_REG_FLASH_CS_WPD : R/W; bitpos: [3]; default: 0;
+ *  flash cs wpd
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPD    (BIT(3))
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPD_M  (IOMUX_MSPI_PIN_REG_FLASH_CS_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_CS_WPD_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPD_S  3
+/** IOMUX_MSPI_PIN_REG_FLASH_CS_DRV : R/W; bitpos: [5:4]; default: 0;
+ *  flash cs drv
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_DRV_M  (IOMUX_MSPI_PIN_REG_FLASH_CS_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_CS_DRV_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_CS_DRV_S  4
+
+/** IOMUX_MSPI_PIN_FLASH_Q_PIN0_REG register
+ *  IOMUX_MSPI_PIN_FLASH_Q_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_FLASH_Q_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x8)
+/** IOMUX_MSPI_PIN_REG_FLASH_Q_HYS : R/W; bitpos: [0]; default: 0;
+ *  flash q hys
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_HYS    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_HYS_M  (IOMUX_MSPI_PIN_REG_FLASH_Q_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_Q_HYS_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_HYS_S  0
+/** IOMUX_MSPI_PIN_REG_FLASH_Q_IE : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_IE    (BIT(1))
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_IE_M  (IOMUX_MSPI_PIN_REG_FLASH_Q_IE_V << IOMUX_MSPI_PIN_REG_FLASH_Q_IE_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_IE_S  1
+/** IOMUX_MSPI_PIN_REG_FLASH_Q_WPU : R/W; bitpos: [2]; default: 0;
+ *  flash q wpu
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPU    (BIT(2))
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPU_M  (IOMUX_MSPI_PIN_REG_FLASH_Q_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_Q_WPU_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPU_S  2
+/** IOMUX_MSPI_PIN_REG_FLASH_Q_WPD : R/W; bitpos: [3]; default: 0;
+ *  flash q wpd
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPD    (BIT(3))
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPD_M  (IOMUX_MSPI_PIN_REG_FLASH_Q_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_Q_WPD_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPD_S  3
+/** IOMUX_MSPI_PIN_REG_FLASH_Q_DRV : R/W; bitpos: [5:4]; default: 0;
+ *  flash q drv
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_DRV_M  (IOMUX_MSPI_PIN_REG_FLASH_Q_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_Q_DRV_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_Q_DRV_S  4
+
+/** IOMUX_MSPI_PIN_FLASH_WP_PIN0_REG register
+ *  IOMUX_MSPI_PIN_FLASH_WP_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_FLASH_WP_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0xc)
+/** IOMUX_MSPI_PIN_REG_FLASH_WP_HYS : R/W; bitpos: [0]; default: 0;
+ *  flash wp hys
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_HYS    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_HYS_M  (IOMUX_MSPI_PIN_REG_FLASH_WP_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_WP_HYS_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_HYS_S  0
+/** IOMUX_MSPI_PIN_REG_FLASH_WP_IE : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_IE    (BIT(1))
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_IE_M  (IOMUX_MSPI_PIN_REG_FLASH_WP_IE_V << IOMUX_MSPI_PIN_REG_FLASH_WP_IE_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_IE_S  1
+/** IOMUX_MSPI_PIN_REG_FLASH_WP_WPU : R/W; bitpos: [2]; default: 0;
+ *  flash wp wpu
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPU    (BIT(2))
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPU_M  (IOMUX_MSPI_PIN_REG_FLASH_WP_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_WP_WPU_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPU_S  2
+/** IOMUX_MSPI_PIN_REG_FLASH_WP_WPD : R/W; bitpos: [3]; default: 0;
+ *  flash wp wpd
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPD    (BIT(3))
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPD_M  (IOMUX_MSPI_PIN_REG_FLASH_WP_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_WP_WPD_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPD_S  3
+/** IOMUX_MSPI_PIN_REG_FLASH_WP_DRV : R/W; bitpos: [5:4]; default: 0;
+ *  flash wp drv
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_DRV_M  (IOMUX_MSPI_PIN_REG_FLASH_WP_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_WP_DRV_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_WP_DRV_S  4
+
+/** IOMUX_MSPI_PIN_FLASH_HOLD_PIN0_REG register
+ *  IOMUX_MSPI_PIN_FLASH_HOLD_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_FLASH_HOLD_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x10)
+/** IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS : R/W; bitpos: [0]; default: 0;
+ *  flash hold hys
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS_M  (IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS_S  0
+/** IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE    (BIT(1))
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE_M  (IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE_V << IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE_S  1
+/** IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU : R/W; bitpos: [2]; default: 0;
+ *  flash hold wpu
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU    (BIT(2))
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU_M  (IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU_S  2
+/** IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD : R/W; bitpos: [3]; default: 0;
+ *  flash hold wpd
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD    (BIT(3))
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD_M  (IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD_S  3
+/** IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV : R/W; bitpos: [5:4]; default: 0;
+ *  flash hold drv
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV_M  (IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV_S  4
+
+/** IOMUX_MSPI_PIN_FLASH_CK_PIN0_REG register
+ *  IOMUX_MSPI_PIN_FLASH_CK_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_FLASH_CK_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x14)
+/** IOMUX_MSPI_PIN_REG_FLASH_CK_HYS : R/W; bitpos: [0]; default: 0;
+ *  flash ck hys
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_HYS    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_HYS_M  (IOMUX_MSPI_PIN_REG_FLASH_CK_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_CK_HYS_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_HYS_S  0
+/** IOMUX_MSPI_PIN_REG_FLASH_CK_IE : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_IE    (BIT(1))
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_IE_M  (IOMUX_MSPI_PIN_REG_FLASH_CK_IE_V << IOMUX_MSPI_PIN_REG_FLASH_CK_IE_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_IE_S  1
+/** IOMUX_MSPI_PIN_REG_FLASH_CK_WPU : R/W; bitpos: [2]; default: 0;
+ *  flash ck wpu
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPU    (BIT(2))
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPU_M  (IOMUX_MSPI_PIN_REG_FLASH_CK_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_CK_WPU_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPU_S  2
+/** IOMUX_MSPI_PIN_REG_FLASH_CK_WPD : R/W; bitpos: [3]; default: 0;
+ *  flash ck wpd
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPD    (BIT(3))
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPD_M  (IOMUX_MSPI_PIN_REG_FLASH_CK_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_CK_WPD_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPD_S  3
+/** IOMUX_MSPI_PIN_REG_FLASH_CK_DRV : R/W; bitpos: [5:4]; default: 0;
+ *  flash ck drv
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_DRV_M  (IOMUX_MSPI_PIN_REG_FLASH_CK_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_CK_DRV_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_CK_DRV_S  4
+
+/** IOMUX_MSPI_PIN_FLASH_D_PIN0_REG register
+ *  IOMUX_MSPI_PIN_FLASH_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_FLASH_D_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x18)
+/** IOMUX_MSPI_PIN_REG_FLASH_D_HYS : R/W; bitpos: [0]; default: 0;
+ *  flash d hys
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_D_HYS    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_FLASH_D_HYS_M  (IOMUX_MSPI_PIN_REG_FLASH_D_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_D_HYS_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_D_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_D_HYS_S  0
+/** IOMUX_MSPI_PIN_REG_FLASH_D_IE : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_D_IE    (BIT(1))
+#define IOMUX_MSPI_PIN_REG_FLASH_D_IE_M  (IOMUX_MSPI_PIN_REG_FLASH_D_IE_V << IOMUX_MSPI_PIN_REG_FLASH_D_IE_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_D_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_D_IE_S  1
+/** IOMUX_MSPI_PIN_REG_FLASH_D_WPU : R/W; bitpos: [2]; default: 0;
+ *  flash d wpu
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_D_WPU    (BIT(2))
+#define IOMUX_MSPI_PIN_REG_FLASH_D_WPU_M  (IOMUX_MSPI_PIN_REG_FLASH_D_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_D_WPU_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_D_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_D_WPU_S  2
+/** IOMUX_MSPI_PIN_REG_FLASH_D_WPD : R/W; bitpos: [3]; default: 0;
+ *  flash d wpd
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_D_WPD    (BIT(3))
+#define IOMUX_MSPI_PIN_REG_FLASH_D_WPD_M  (IOMUX_MSPI_PIN_REG_FLASH_D_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_D_WPD_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_D_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_FLASH_D_WPD_S  3
+/** IOMUX_MSPI_PIN_REG_FLASH_D_DRV : R/W; bitpos: [5:4]; default: 0;
+ *  flash d drv
+ */
+#define IOMUX_MSPI_PIN_REG_FLASH_D_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_D_DRV_M  (IOMUX_MSPI_PIN_REG_FLASH_D_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_D_DRV_S)
+#define IOMUX_MSPI_PIN_REG_FLASH_D_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_FLASH_D_DRV_S  4
+
+/** IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x1c)
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram d dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram d dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram d hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_D_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram d wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram d wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram d drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_Q_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_Q_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x20)
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram q dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram q dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram q hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram q wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram q wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram q drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_WP_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_WP_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x24)
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram wp dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram wp dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram wp hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram wp wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram wp wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram wp drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_HOLD_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_HOLD_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x28)
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram hold dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram hold dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram hold hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram hold wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram hold wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram hold drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ4_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ4_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x2c)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq4 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq4 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq4 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq4 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq4 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq4 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ5_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ5_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x30)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq5 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq5 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq5 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq5 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq5 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq5 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ6_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ6_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x34)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq6 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq6 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq6 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq6 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq6 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq6 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ7_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ7_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x38)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq7 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq7 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq7 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq7 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq7 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq7 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQS_0_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQS_0_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x3c)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD : R/W; bitpos: [0]; default: 0;
+ *  psram xpd dqs0
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE : R/W; bitpos: [2:1]; default: 0;
+ *  psram dqs0 phase
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_S  1
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI : R/W; bitpos: [6:3]; default: 0;
+ *  psram dqs0 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_S  3
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90 : R/W; bitpos: [10:7]; default: 0;
+ *  psram dqs0 delay 90
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_S  7
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS : R/W; bitpos: [11]; default: 0;
+ *  psram dqs0 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE    (BIT(12))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU : R/W; bitpos: [13]; default: 0;
+ *  psram dqs0 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU    (BIT(13))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_S  13
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD : R/W; bitpos: [14]; default: 0;
+ *  psram dqs0 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD    (BIT(14))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_S  14
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV : R/W; bitpos: [16:15]; default: 0;
+ *  psram dqs0 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_S  15
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270 : R/W; bitpos: [20:17]; default: 0;
+ *  psram dqs0 delay 270
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_S  17
+
+/** IOMUX_MSPI_PIN_PSRAM_CK_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_CK_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x40)
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram ck dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram ck dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram ck hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram ck wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram ck wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram ck drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x44)
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram cs dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram cs dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram cs hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram cs wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram cs wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram cs drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ8_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ8_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x48)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq8 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq8 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq8 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq8 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq8 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq8 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ9_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ9_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x4c)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq9 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq9 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq9 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq9 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq9 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq9 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ10_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ10_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x50)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq10 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq10 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq10 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq10 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq10 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq10 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ11_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ11_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x54)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq11 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq11 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq11 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq11 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq11 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq11 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ12_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ12_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x58)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq12 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq12 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq12 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq12 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq12 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq12 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ13_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ13_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x5c)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq13 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq13 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq13 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq13 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq13 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq13 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ14_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ14_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x60)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq14 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq14 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq14 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq14 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq14 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq14 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ15_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ15_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x64)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq15 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq15 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq15 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq15 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq15 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV : R/W; bitpos: [13:12]; default: 0;
+ *  psram dq15 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV_S  12
+
+/** IOMUX_MSPI_PIN_PSRAM_DQS_1_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQS_1_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x68)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD : R/W; bitpos: [0]; default: 0;
+ *  psram xpd dqs1
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE : R/W; bitpos: [2:1]; default: 0;
+ *  psram dqs1 phase
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE_S  1
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI : R/W; bitpos: [6:3]; default: 0;
+ *  psram dqs1 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI_S  3
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90 : R/W; bitpos: [10:7]; default: 0;
+ *  psram dqs1 delay 90
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90_S  7
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS : R/W; bitpos: [11]; default: 0;
+ *  psram dqs1 hys
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE    (BIT(12))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU : R/W; bitpos: [13]; default: 0;
+ *  psram dqs1 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU    (BIT(13))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU_S  13
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD : R/W; bitpos: [14]; default: 0;
+ *  psram dqs1 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD    (BIT(14))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD_S  14
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV : R/W; bitpos: [16:15]; default: 0;
+ *  psram dqs1 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV_S  15
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270 : R/W; bitpos: [20:17]; default: 0;
+ *  psram dqs1 delay 270
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270_S  17
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/iomux_mspi_pin_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/iomux_mspi_pin_struct.h
new file mode 100644
index 0000000000..f5ab610d58
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/iomux_mspi_pin_struct.h
@@ -0,0 +1,333 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_en */
+/** Type of clk_en0 register
+ *  apb registers auto clock gating reg
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  1: auto clock gating on
+         *  0: auto clock gating off
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} iomux_mspi_pin_clk_en0_reg_t;
+
+
+/** Group: flash_cs_pin */
+/** Type of flash_cs_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_CS_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_cs_hys : R/W; bitpos: [0]; default: 0;
+         *  flash cs hys
+         */
+        uint32_t reg_flash_cs_hys:1;
+        /** reg_flash_cs_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_cs_ie:1;
+        /** reg_flash_cs_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash cs wpu
+         */
+        uint32_t reg_flash_cs_wpu:1;
+        /** reg_flash_cs_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash cs wpd
+         */
+        uint32_t reg_flash_cs_wpd:1;
+        /** reg_flash_cs_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash cs drv
+         */
+        uint32_t reg_flash_cs_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_cs_pin0_reg_t;
+
+
+/** Group: flash_q_pin */
+/** Type of flash_q_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_Q_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_q_hys : R/W; bitpos: [0]; default: 0;
+         *  flash q hys
+         */
+        uint32_t reg_flash_q_hys:1;
+        /** reg_flash_q_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_q_ie:1;
+        /** reg_flash_q_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash q wpu
+         */
+        uint32_t reg_flash_q_wpu:1;
+        /** reg_flash_q_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash q wpd
+         */
+        uint32_t reg_flash_q_wpd:1;
+        /** reg_flash_q_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash q drv
+         */
+        uint32_t reg_flash_q_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_q_pin0_reg_t;
+
+
+/** Group: flash_wp_pin */
+/** Type of flash_wp_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_WP_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_wp_hys : R/W; bitpos: [0]; default: 0;
+         *  flash wp hys
+         */
+        uint32_t reg_flash_wp_hys:1;
+        /** reg_flash_wp_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_wp_ie:1;
+        /** reg_flash_wp_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash wp wpu
+         */
+        uint32_t reg_flash_wp_wpu:1;
+        /** reg_flash_wp_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash wp wpd
+         */
+        uint32_t reg_flash_wp_wpd:1;
+        /** reg_flash_wp_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash wp drv
+         */
+        uint32_t reg_flash_wp_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_wp_pin0_reg_t;
+
+
+/** Group: flash_hold_pin */
+/** Type of flash_hold_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_HOLD_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_hold_hys : R/W; bitpos: [0]; default: 0;
+         *  flash hold hys
+         */
+        uint32_t reg_flash_hold_hys:1;
+        /** reg_flash_hold_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_hold_ie:1;
+        /** reg_flash_hold_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash hold wpu
+         */
+        uint32_t reg_flash_hold_wpu:1;
+        /** reg_flash_hold_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash hold wpd
+         */
+        uint32_t reg_flash_hold_wpd:1;
+        /** reg_flash_hold_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash hold drv
+         */
+        uint32_t reg_flash_hold_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_hold_pin0_reg_t;
+
+
+/** Group: flash_ck_pin */
+/** Type of flash_ck_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_CK_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_ck_hys : R/W; bitpos: [0]; default: 0;
+         *  flash ck hys
+         */
+        uint32_t reg_flash_ck_hys:1;
+        /** reg_flash_ck_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_ck_ie:1;
+        /** reg_flash_ck_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash ck wpu
+         */
+        uint32_t reg_flash_ck_wpu:1;
+        /** reg_flash_ck_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash ck wpd
+         */
+        uint32_t reg_flash_ck_wpd:1;
+        /** reg_flash_ck_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash ck drv
+         */
+        uint32_t reg_flash_ck_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_ck_pin0_reg_t;
+
+
+/** Group: flash_d_pin */
+/** Type of flash_d_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_d_hys : R/W; bitpos: [0]; default: 0;
+         *  flash d hys
+         */
+        uint32_t reg_flash_d_hys:1;
+        /** reg_flash_d_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_d_ie:1;
+        /** reg_flash_d_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash d wpu
+         */
+        uint32_t reg_flash_d_wpu:1;
+        /** reg_flash_d_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash d wpd
+         */
+        uint32_t reg_flash_d_wpd:1;
+        /** reg_flash_d_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash d drv
+         */
+        uint32_t reg_flash_d_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_d_pin0_reg_t;
+
+
+/** psram_pin */
+typedef union {
+    struct {
+        /** reg_psram_pin_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram pin dli
+         */
+        uint32_t reg_psram_pin_dli:4;
+        /** reg_psram_pin_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram pin dlc
+         */
+        uint32_t reg_psram_pin_dlc:4;
+        /** reg_psram_pin_hys : R/W; bitpos: [8]; default: 0;
+         *  psram pin hys
+         */
+        uint32_t reg_psram_pin_hys:1;
+        /** reg_psram_pin_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_pin_ie:1;
+        /** reg_psram_pin_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram pin wpu
+         */
+        uint32_t reg_psram_pin_wpu:1;
+        /** reg_psram_pin_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram pin wpd
+         */
+        uint32_t reg_psram_pin_wpd:1;
+        /** reg_psram_d_drv : R/W; bitpos: [13:12]; default: 0;
+         *  psram pin drv
+         */
+        uint32_t reg_psram_d_drv:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_pin_reg_t;
+
+/** psram_dqs_pin */
+typedef union {
+    struct {
+        /** reg_psram_dqs_xpd : R/W; bitpos: [0]; default: 0;
+         *  psram xpd dqs
+         */
+        uint32_t reg_psram_dqs_xpd:1;
+        /** reg_psram_dqs_phase : R/W; bitpos: [2:1]; default: 0;
+         *  psram dqs phase
+         */
+        uint32_t reg_psram_dqs_phase:2;
+        /** reg_psram_dqs_dli : R/W; bitpos: [6:3]; default: 0;
+         *  psram dqs dli
+         */
+        uint32_t reg_psram_dqs_dli:4;
+        /** reg_psram_dqs_delay_90 : R/W; bitpos: [10:7]; default: 0;
+         *  psram dqs delay 90
+         */
+        uint32_t reg_psram_dqs_delay_90:4;
+        /** reg_psram_dqs_hys : R/W; bitpos: [11]; default: 0;
+         *  psram dqs hys
+         */
+        uint32_t reg_psram_dqs_hys:1;
+        /** reg_psram_dqs_ie : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_dqs_ie:1;
+        /** reg_psram_dqs_wpu : R/W; bitpos: [13]; default: 0;
+         *  psram dqs wpu
+         */
+        uint32_t reg_psram_dqs_wpu:1;
+        /** reg_psram_dqs_wpd : R/W; bitpos: [14]; default: 0;
+         *  psram dqs wpd
+         */
+        uint32_t reg_psram_dqs_wpd:1;
+        /** reg_psram_dqs_drv : R/W; bitpos: [16:15]; default: 0;
+         *  psram dqs drv
+         */
+        uint32_t reg_psram_dqs_drv:2;
+        /** reg_psram_dqs_delay_270 : R/W; bitpos: [20:17]; default: 0;
+         *  psram dqs delay 270
+         */
+        uint32_t reg_psram_dqs_delay_270:4;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_dqs_pin_reg_t;
+
+/** psram_pin group */
+typedef struct {
+    volatile iomux_mspi_pin_psram_pin_reg_t pin_group0[8];   //for d, q, wp, hold, dq4, dq5, dq6, dq7
+    volatile iomux_mspi_pin_psram_dqs_pin_reg_t dqs0;
+    volatile iomux_mspi_pin_psram_pin_reg_t pin_group1[10];  //for ck, cs, dq8, dq9, dq10, dq11, dq12, dq13, dq14, dq15
+    volatile iomux_mspi_pin_psram_dqs_pin_reg_t dqs1;
+} iomux_mspi_pin_psram_pin_grp_reg_t;
+
+typedef struct {
+    volatile iomux_mspi_pin_clk_en0_reg_t clk_en0;
+    volatile iomux_mspi_pin_flash_cs_pin0_reg_t flash_cs_pin0;
+    volatile iomux_mspi_pin_flash_q_pin0_reg_t flash_q_pin0;
+    volatile iomux_mspi_pin_flash_wp_pin0_reg_t flash_wp_pin0;
+    volatile iomux_mspi_pin_flash_hold_pin0_reg_t flash_hold_pin0;
+    volatile iomux_mspi_pin_flash_ck_pin0_reg_t flash_ck_pin0;
+    volatile iomux_mspi_pin_flash_d_pin0_reg_t flash_d_pin0;
+    volatile iomux_mspi_pin_psram_pin_grp_reg_t psram_pin_group;
+} iomux_mspi_pin_dev_t;
+
+extern iomux_mspi_pin_dev_t MSPI_IOMUX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(iomux_mspi_pin_dev_t) == 0x6c, "Invalid size of iomux_mspi_pin_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/isp_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/isp_eco5_struct.h
new file mode 100644
index 0000000000..ce7d9518aa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/isp_eco5_struct.h
@@ -0,0 +1,4182 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Version Register */
+/** Type of ver_date register
+ *  version control register
+ */
+typedef union {
+    struct {
+        /** ver_data : R/W; bitpos: [31:0]; default: 539035144;
+         *  csv version
+         */
+        uint32_t ver_data:32;
+    };
+    uint32_t val;
+} isp_ver_date_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of clk_en register
+ *  isp clk control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the clk force on of isp reg. 0: disable, 1: enable
+         */
+        uint32_t clk_en:1;
+        /** clk_blc_force_on : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the clk force on of blc. 0: disable, 1: enable
+         */
+        uint32_t clk_blc_force_on:1;
+        /** clk_dpc_force_on : R/W; bitpos: [2]; default: 0;
+         *  this bit configures the clk force on of dpc. 0: disable, 1: enable
+         */
+        uint32_t clk_dpc_force_on:1;
+        /** clk_bf_force_on : R/W; bitpos: [3]; default: 0;
+         *  this bit configures the clk force on of bf. 0: disable, 1: enable
+         */
+        uint32_t clk_bf_force_on:1;
+        /** clk_lsc_force_on : R/W; bitpos: [4]; default: 0;
+         *  this bit configures the clk force on of lsc. 0: disable, 1: enable
+         */
+        uint32_t clk_lsc_force_on:1;
+        /** clk_demosaic_force_on : R/W; bitpos: [5]; default: 0;
+         *  this bit configures the clk force on of demosaic. 0: disable, 1: enable
+         */
+        uint32_t clk_demosaic_force_on:1;
+        /** clk_median_force_on : R/W; bitpos: [6]; default: 0;
+         *  this bit configures the clk force on of median. 0: disable, 1: enable
+         */
+        uint32_t clk_median_force_on:1;
+        /** clk_ccm_force_on : R/W; bitpos: [7]; default: 0;
+         *  this bit configures the clk force on of ccm. 0: disable, 1: enable
+         */
+        uint32_t clk_ccm_force_on:1;
+        /** clk_gamma_force_on : R/W; bitpos: [8]; default: 0;
+         *  this bit configures the clk force on of gamma. 0: disable, 1: enable
+         */
+        uint32_t clk_gamma_force_on:1;
+        /** clk_rgb2yuv_force_on : R/W; bitpos: [9]; default: 0;
+         *  this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable
+         */
+        uint32_t clk_rgb2yuv_force_on:1;
+        /** clk_sharp_force_on : R/W; bitpos: [10]; default: 0;
+         *  this bit configures the clk force on of sharp. 0: disable, 1: enable
+         */
+        uint32_t clk_sharp_force_on:1;
+        /** clk_color_force_on : R/W; bitpos: [11]; default: 0;
+         *  this bit configures the clk force on of color. 0: disable, 1: enable
+         */
+        uint32_t clk_color_force_on:1;
+        /** clk_yuv2rgb_force_on : R/W; bitpos: [12]; default: 0;
+         *  this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable
+         */
+        uint32_t clk_yuv2rgb_force_on:1;
+        /** clk_ae_force_on : R/W; bitpos: [13]; default: 0;
+         *  this bit configures the clk force on of ae. 0: disable, 1: enable
+         */
+        uint32_t clk_ae_force_on:1;
+        /** clk_af_force_on : R/W; bitpos: [14]; default: 0;
+         *  this bit configures the clk force on of af. 0: disable, 1: enable
+         */
+        uint32_t clk_af_force_on:1;
+        /** clk_awb_force_on : R/W; bitpos: [15]; default: 0;
+         *  this bit configures the clk force on of awb. 0: disable, 1: enable
+         */
+        uint32_t clk_awb_force_on:1;
+        /** clk_hist_force_on : R/W; bitpos: [16]; default: 0;
+         *  this bit configures the clk force on of hist. 0: disable, 1: enable
+         */
+        uint32_t clk_hist_force_on:1;
+        /** clk_mipi_idi_force_on : R/W; bitpos: [17]; default: 0;
+         *  this bit configures the clk force on of mipi idi input. 0: disable, 1: enable
+         */
+        uint32_t clk_mipi_idi_force_on:1;
+        /** isp_mem_clk_force_on : R/W; bitpos: [18]; default: 0;
+         *  this bit configures the clk force on of all isp memory. 0: disable, 1: enable
+         */
+        uint32_t isp_mem_clk_force_on:1;
+        /** clk_crop_force_on : R/W; bitpos: [19]; default: 0;
+         *  this bit configures the clk force on of crop. 0: disable, 1: enable
+         */
+        uint32_t clk_crop_force_on:1;
+        /** clk_wbg_force_on : R/W; bitpos: [20]; default: 0;
+         *  this bit configures the clk force on of wbg. 0: disable, 1: enable
+         */
+        uint32_t clk_wbg_force_on:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} isp_clk_en_reg_t;
+
+/** Type of cntl register
+ *  isp module enable control register
+ */
+typedef union {
+    struct {
+        /** mipi_data_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures mipi input data enable. 0: disable, 1: enable
+         */
+        uint32_t mipi_data_en:1;
+        /** isp_en : R/W; bitpos: [1]; default: 1;
+         *  this bit configures isp global enable. 0: disable, 1: enable
+         */
+        uint32_t isp_en:1;
+        /** blc_en : R/W; bitpos: [2]; default: 0;
+         *  this bit configures blc enable. 0: disable, 1: enable
+         */
+        uint32_t blc_en:1;
+        /** dpc_en : R/W; bitpos: [3]; default: 0;
+         *  this bit configures dpc enable. 0: disable, 1: enable
+         */
+        uint32_t dpc_en:1;
+        /** bf_en : R/W; bitpos: [4]; default: 0;
+         *  this bit configures bf enable. 0: disable, 1: enable
+         */
+        uint32_t bf_en:1;
+        /** lsc_en : R/W; bitpos: [5]; default: 0;
+         *  this bit configures lsc enable. 0: disable, 1: enable
+         */
+        uint32_t lsc_en:1;
+        /** demosaic_en : R/W; bitpos: [6]; default: 1;
+         *  this bit configures demosaic enable. 0: disable, 1: enable
+         */
+        uint32_t demosaic_en:1;
+        /** median_en : R/W; bitpos: [7]; default: 0;
+         *  this bit configures median enable. 0: disable, 1: enable
+         */
+        uint32_t median_en:1;
+        /** ccm_en : R/W; bitpos: [8]; default: 0;
+         *  this bit configures ccm enable. 0: disable, 1: enable
+         */
+        uint32_t ccm_en:1;
+        /** gamma_en : R/W; bitpos: [9]; default: 0;
+         *  this bit configures gamma enable. 0: disable, 1: enable
+         */
+        uint32_t gamma_en:1;
+        /** rgb2yuv_en : R/W; bitpos: [10]; default: 1;
+         *  this bit configures rgb2yuv enable. 0: disable, 1: enable
+         */
+        uint32_t rgb2yuv_en:1;
+        /** sharp_en : R/W; bitpos: [11]; default: 0;
+         *  this bit configures sharp enable. 0: disable, 1: enable
+         */
+        uint32_t sharp_en:1;
+        /** color_en : R/W; bitpos: [12]; default: 0;
+         *  this bit configures color enable. 0: disable, 1: enable
+         */
+        uint32_t color_en:1;
+        /** yuv2rgb_en : R/W; bitpos: [13]; default: 1;
+         *  this bit configures yuv2rgb enable. 0: disable, 1: enable
+         */
+        uint32_t yuv2rgb_en:1;
+        /** ae_en : R/W; bitpos: [14]; default: 0;
+         *  this bit configures ae enable. 0: disable, 1: enable
+         */
+        uint32_t ae_en:1;
+        /** af_en : R/W; bitpos: [15]; default: 0;
+         *  this bit configures af enable. 0: disable, 1: enable
+         */
+        uint32_t af_en:1;
+        /** awb_en : R/W; bitpos: [16]; default: 0;
+         *  this bit configures awb enable. 0: disable, 1: enable
+         */
+        uint32_t awb_en:1;
+        /** hist_en : R/W; bitpos: [17]; default: 0;
+         *  this bit configures hist enable. 0: disable, 1: enable
+         */
+        uint32_t hist_en:1;
+        /** crop_en : R/W; bitpos: [18]; default: 0;
+         *  this bit configures crop enable. 0: disable, 1: enable
+         */
+        uint32_t crop_en:1;
+        /** wbg_en : R/W; bitpos: [19]; default: 0;
+         *  this bit configures wbg enable. 0: disable, 1: enable
+         */
+        uint32_t wbg_en:1;
+        uint32_t reserved_20:4;
+        /** byte_endian_order : R/W; bitpos: [24]; default: 0;
+         *  select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1:
+         *  {[7:0], [15:8], [23:16], [31:24]}
+         */
+        uint32_t byte_endian_order:1;
+        /** isp_data_type : R/W; bitpos: [26:25]; default: 0;
+         *  this field configures input data type, 0:RAW8 1:RAW10 2:RAW12
+         */
+        uint32_t isp_data_type:2;
+        /** isp_in_src : R/W; bitpos: [28:27]; default: 0;
+         *  this field configures input data source, 0:CSI HOST 1:CAM 2:DMA
+         */
+        uint32_t isp_in_src:2;
+        /** isp_out_type : R/W; bitpos: [31:29]; default: 2;
+         *  this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4:
+         *  RGB565
+         */
+        uint32_t isp_out_type:3;
+    };
+    uint32_t val;
+} isp_cntl_reg_t;
+
+/** Type of hsync_cnt register
+ *  header hsync interval control register
+ */
+typedef union {
+    struct {
+        /** hsync_cnt : R/W; bitpos: [7:0]; default: 7;
+         *  this field configures the number of clock before hsync and after vsync and line_end
+         *  when decodes pix data from idi to isp
+         */
+        uint32_t hsync_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} isp_hsync_cnt_reg_t;
+
+/** Type of frame_cfg register
+ *  frame control parameter register
+ */
+typedef union {
+    struct {
+        /** vadr_num : R/W; bitpos: [11:0]; default: 480;
+         *  this field configures input image size in y-direction, image row number - 1
+         */
+        uint32_t vadr_num:12;
+        /** hadr_num : R/W; bitpos: [23:12]; default: 480;
+         *  this field configures input image size in x-direction, image line number - 1
+         */
+        uint32_t hadr_num:12;
+        uint32_t reserved_24:3;
+        /** bayer_mode : R/W; bitpos: [28:27]; default: 0;
+         *  this field configures the bayer mode of input pixel. 00 : BG/GR    01 : GB/RG   10
+         *  : GR/BG  11 : RG/GB
+         */
+        uint32_t bayer_mode:2;
+        /** hsync_start_exist : R/W; bitpos: [29]; default: 1;
+         *  this bit configures the line end packet exist or not. 0: not exist, 1: exist
+         */
+        uint32_t hsync_start_exist:1;
+        /** hsync_end_exist : R/W; bitpos: [30]; default: 1;
+         *  this bit configures the line start packet exist or not. 0: not exist, 1: exist
+         */
+        uint32_t hsync_end_exist:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} isp_frame_cfg_reg_t;
+
+/** Type of ccm_coef0 register
+ *  ccm coef register 0
+ */
+typedef union {
+    struct {
+        /** ccm_rr : R/W; bitpos: [12:0]; default: 256;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_rr:13;
+        /** ccm_rg : R/W; bitpos: [25:13]; default: 0;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_rg:13;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_ccm_coef0_reg_t;
+
+/** Type of ccm_coef1 register
+ *  ccm coef register 1
+ */
+typedef union {
+    struct {
+        /** ccm_rb : R/W; bitpos: [12:0]; default: 0;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_rb:13;
+        /** ccm_gr : R/W; bitpos: [25:13]; default: 0;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_gr:13;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_ccm_coef1_reg_t;
+
+/** Type of ccm_coef3 register
+ *  ccm coef register 3
+ */
+typedef union {
+    struct {
+        /** ccm_gg : R/W; bitpos: [12:0]; default: 256;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_gg:13;
+        /** ccm_gb : R/W; bitpos: [25:13]; default: 0;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_gb:13;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_ccm_coef3_reg_t;
+
+/** Type of ccm_coef4 register
+ *  ccm coef register 4
+ */
+typedef union {
+    struct {
+        /** ccm_br : R/W; bitpos: [12:0]; default: 0;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_br:13;
+        /** ccm_bg : R/W; bitpos: [25:13]; default: 0;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_bg:13;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_ccm_coef4_reg_t;
+
+/** Type of ccm_coef5 register
+ *  ccm coef register 5
+ */
+typedef union {
+    struct {
+        /** ccm_bb : R/W; bitpos: [12:0]; default: 256;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_bb:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} isp_ccm_coef5_reg_t;
+
+/** Type of bf_matrix_ctrl register
+ *  bf pix2matrix ctrl
+ */
+typedef union {
+    struct {
+        /** bf_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0;
+         *  matrix tail pixen low level threshold, should not to large to prevent expanding to
+         *  next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0
+         *  and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse
+         *  function
+         */
+        uint32_t bf_tail_pixen_pulse_tl:8;
+        /** bf_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0;
+         *  matrix tail pixen high level threshold, must < hnum-1, only
+         *  reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and
+         *  reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse
+         *  function
+         */
+        uint32_t bf_tail_pixen_pulse_th:8;
+        /** bf_padding_data : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures bf matrix padding data
+         */
+        uint32_t bf_padding_data:8;
+        /** bf_padding_mode : R/W; bitpos: [24]; default: 0;
+         *  this bit configures the padding mode of bf matrix.  0: use pixel in image to do
+         *  padding   1: use reg_padding_data to do padding
+         */
+        uint32_t bf_padding_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} isp_bf_matrix_ctrl_reg_t;
+
+/** Type of bf_sigma register
+ *  bf denoising level control register
+ */
+typedef union {
+    struct {
+        /** sigma : R/W; bitpos: [5:0]; default: 2;
+         *  this field configures the bayer denoising level, valid data from 2 to 20
+         */
+        uint32_t sigma:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} isp_bf_sigma_reg_t;
+
+/** Type of bf_gau0 register
+ *  bf gau template register 0
+ */
+typedef union {
+    struct {
+        /** gau_template21 : R/W; bitpos: [3:0]; default: 15;
+         *  this field configures index 21 of gaussian template
+         */
+        uint32_t gau_template21:4;
+        /** gau_template20 : R/W; bitpos: [7:4]; default: 15;
+         *  this field configures index 20 of gaussian template
+         */
+        uint32_t gau_template20:4;
+        /** gau_template12 : R/W; bitpos: [11:8]; default: 15;
+         *  this field configures index 12 of gaussian template
+         */
+        uint32_t gau_template12:4;
+        /** gau_template11 : R/W; bitpos: [15:12]; default: 15;
+         *  this field configures index 11 of gaussian template
+         */
+        uint32_t gau_template11:4;
+        /** gau_template10 : R/W; bitpos: [19:16]; default: 15;
+         *  this field configures index 10 of gaussian template
+         */
+        uint32_t gau_template10:4;
+        /** gau_template02 : R/W; bitpos: [23:20]; default: 15;
+         *  this field configures index 02 of gaussian template
+         */
+        uint32_t gau_template02:4;
+        /** gau_template01 : R/W; bitpos: [27:24]; default: 15;
+         *  this field configures index 01 of gaussian template
+         */
+        uint32_t gau_template01:4;
+        /** gau_template00 : R/W; bitpos: [31:28]; default: 15;
+         *  this field configures index 00 of gaussian template
+         */
+        uint32_t gau_template00:4;
+    };
+    uint32_t val;
+} isp_bf_gau0_reg_t;
+
+/** Type of bf_gau1 register
+ *  bf gau template register 1
+ */
+typedef union {
+    struct {
+        /** gau_template22 : R/W; bitpos: [3:0]; default: 15;
+         *  this field configures index 22 of gaussian template
+         */
+        uint32_t gau_template22:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} isp_bf_gau1_reg_t;
+
+/** Type of dpc_ctrl register
+ *  DPC mode control register
+ */
+typedef union {
+    struct {
+        /** dpc_check_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the check mode enable. 0: disable, 1: enable
+         */
+        uint32_t dpc_check_en:1;
+        /** sta_en : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the sta dpc enable. 0: disable, 1: enable
+         */
+        uint32_t sta_en:1;
+        /** dyn_en : R/W; bitpos: [2]; default: 1;
+         *  this bit configures the dyn dpc enable. 0: disable, 1: enable
+         */
+        uint32_t dyn_en:1;
+        /** dpc_black_en : R/W; bitpos: [3]; default: 0;
+         *  this bit configures input image type select when in check mode, 0: white img, 1:
+         *  black img
+         */
+        uint32_t dpc_black_en:1;
+        /** dpc_method_sel : R/W; bitpos: [4]; default: 0;
+         *  this bit configures dyn dpc method select. 0: simple method, 1: hard method
+         */
+        uint32_t dpc_method_sel:1;
+        /** dpc_check_od_en : R/W; bitpos: [5]; default: 0;
+         *  this bit configures output pixel data when in check mode or not. 0: no data output,
+         *  1: data output
+         */
+        uint32_t dpc_check_od_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} isp_dpc_ctrl_reg_t;
+
+/** Type of dpc_conf register
+ *  DPC parameter config register
+ */
+typedef union {
+    struct {
+        /** dpc_threshold_l : R/W; bitpos: [7:0]; default: 48;
+         *  this bit configures the threshold to detect black img in check mode, or the low
+         *  threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit
+         *  10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1
+         */
+        uint32_t dpc_threshold_l:8;
+        /** dpc_threshold_h : R/W; bitpos: [15:8]; default: 48;
+         *  this bit configures the threshold to detect white img in check mode, or the high
+         *  threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit
+         *  10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1
+         */
+        uint32_t dpc_threshold_h:8;
+        /** dpc_factor_dark : R/W; bitpos: [21:16]; default: 16;
+         *  this field configures the dynamic correction method 1 dark   factor
+         */
+        uint32_t dpc_factor_dark:6;
+        /** dpc_factor_brig : R/W; bitpos: [27:22]; default: 16;
+         *  this field configures the dynamic correction method 1 bright factor
+         */
+        uint32_t dpc_factor_brig:6;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_dpc_conf_reg_t;
+
+/** Type of dpc_matrix_ctrl register
+ *  dpc pix2matrix ctrl
+ */
+typedef union {
+    struct {
+        /** dpc_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0;
+         *  matrix tail pixen low level threshold,  should not to large to prevent expanding to
+         *  next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0
+         *  and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail
+         *  pulse function
+         */
+        uint32_t dpc_tail_pixen_pulse_tl:8;
+        /** dpc_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0;
+         *  matrix tail pixen high level threshold, must < hnum-1, only
+         *  reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and
+         *  reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse
+         *  function
+         */
+        uint32_t dpc_tail_pixen_pulse_th:8;
+        /** dpc_padding_data : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures dpc matrix padding data
+         */
+        uint32_t dpc_padding_data:8;
+        /** dpc_padding_mode : R/W; bitpos: [24]; default: 0;
+         *  this bit configures the padding mode of dpc matrix.  0: use pixel in image to do
+         *  padding   1: use reg_padding_data to do padding
+         */
+        uint32_t dpc_padding_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} isp_dpc_matrix_ctrl_reg_t;
+
+/** Type of lut_cmd register
+ *  LUT command register
+ */
+typedef union {
+    struct {
+        /** lut_addr : WT; bitpos: [11:0]; default: 0;
+         *  this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b
+         *  lut, 01 sel r_gr lut
+         */
+        uint32_t lut_addr:12;
+        /** lut_num : WT; bitpos: [15:12]; default: 0;
+         *  this field configures the lut selection. 0000:LSC LUT. 0001:DPC LUT. 0010:AWB LUT
+         */
+        uint32_t lut_num:4;
+        /** lut_cmd : WT; bitpos: [16]; default: 0;
+         *  this bit configures the access event of lut. 0:rd 1: wr
+         */
+        uint32_t lut_cmd:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_lut_cmd_reg_t;
+
+/** Type of lut_wdata register
+ *  LUT write data register
+ */
+typedef union {
+    struct {
+        /** lut_wdata : R/W; bitpos: [31:0]; default: 0;
+         *  this field configures the write data of lut. please initial ISP_LUT_WDATA before
+         *  write ISP_LUT_CMD register
+         */
+        uint32_t lut_wdata:32;
+    };
+    uint32_t val;
+} isp_lut_wdata_reg_t;
+
+/** Type of lsc_tablesize register
+ *  LSC point in x-direction
+ */
+typedef union {
+    struct {
+        /** lsc_xtablesize : R/W; bitpos: [4:0]; default: 31;
+         *  this field configures lsc table size in x-direction
+         */
+        uint32_t lsc_xtablesize:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} isp_lsc_tablesize_reg_t;
+
+/** Type of demosaic_matrix_ctrl register
+ *  demosaic pix2matrix ctrl
+ */
+typedef union {
+    struct {
+        /** demosaic_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0;
+         *  matrix tail pixen low level threshold,  should not to large to prevent expanding to
+         *  next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and
+         *  reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th <
+         *  reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function
+         */
+        uint32_t demosaic_tail_pixen_pulse_tl:8;
+        /** demosaic_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0;
+         *  matrix tail pixen high level threshold, must < hnum-1, only
+         *  reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and
+         *  reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable
+         *  tail pulse function
+         */
+        uint32_t demosaic_tail_pixen_pulse_th:8;
+        /** demosaic_padding_data : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures demosaic matrix padding data
+         */
+        uint32_t demosaic_padding_data:8;
+        /** demosaic_padding_mode : R/W; bitpos: [24]; default: 0;
+         *  this bit configures the padding mode of demosaic matrix.  0: use pixel in image to
+         *  do padding   1: use reg_padding_data to do padding
+         */
+        uint32_t demosaic_padding_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} isp_demosaic_matrix_ctrl_reg_t;
+
+/** Type of demosaic_grad_ratio register
+ *  demosaic gradient select ratio
+ */
+typedef union {
+    struct {
+        /** demosaic_grad_ratio : R/W; bitpos: [5:0]; default: 16;
+         *  this field configures demosaic gradient select ratio
+         */
+        uint32_t demosaic_grad_ratio:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} isp_demosaic_grad_ratio_reg_t;
+
+/** Type of median_matrix_ctrl register
+ *  median pix2matrix ctrl
+ */
+typedef union {
+    struct {
+        /** median_padding_data : R/W; bitpos: [7:0]; default: 0;
+         *  this field configures median matrix padding data
+         */
+        uint32_t median_padding_data:8;
+        /** median_padding_mode : R/W; bitpos: [8]; default: 0;
+         *  this bit configures the padding mode of median matrix.  0: use pixel in image to do
+         *  padding   1: use reg_padding_data to do padding
+         */
+        uint32_t median_padding_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} isp_median_matrix_ctrl_reg_t;
+
+/** Type of gamma_ctrl register
+ *  gamma control register
+ */
+typedef union {
+    struct {
+        /** gamma_update : R/W; bitpos: [0]; default: 0;
+         *  Indicates that gamma register configuration is complete
+         */
+        uint32_t gamma_update:1;
+        /** gamma_b_last_correct : R/W; bitpos: [1]; default: 1;
+         *  this bit configures enable of last b segment correcction. 0: disable, 1: enable
+         */
+        uint32_t gamma_b_last_correct:1;
+        /** gamma_g_last_correct : R/W; bitpos: [2]; default: 1;
+         *  this bit configures enable of last g segment correcction. 0: disable, 1: enable
+         */
+        uint32_t gamma_g_last_correct:1;
+        /** gamma_r_last_correct : R/W; bitpos: [3]; default: 1;
+         *  this bit configures enable of last r segment correcction. 0: disable, 1: enable
+         */
+        uint32_t gamma_r_last_correct:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} isp_gamma_ctrl_reg_t;
+
+/** Type of gamma_ry1 register
+ *  point of Y-axis of r channel gamma curve register 1
+ */
+typedef union {
+    struct {
+        /** gamma_r_y03 : R/W; bitpos: [7:0]; default: 64;
+         *  this field configures the point 3 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y03:8;
+        /** gamma_r_y02 : R/W; bitpos: [15:8]; default: 48;
+         *  this field configures the point 2 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y02:8;
+        /** gamma_r_y01 : R/W; bitpos: [23:16]; default: 32;
+         *  this field configures the point 1 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y01:8;
+        /** gamma_r_y00 : R/W; bitpos: [31:24]; default: 16;
+         *  this field configures the point 0 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y00:8;
+    };
+    uint32_t val;
+} isp_gamma_ry1_reg_t;
+
+/** Type of gamma_ry2 register
+ *  point of Y-axis of r channel gamma curve register 2
+ */
+typedef union {
+    struct {
+        /** gamma_r_y07 : R/W; bitpos: [7:0]; default: 128;
+         *  this field configures the point 7 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y07:8;
+        /** gamma_r_y06 : R/W; bitpos: [15:8]; default: 112;
+         *  this field configures the point 6 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y06:8;
+        /** gamma_r_y05 : R/W; bitpos: [23:16]; default: 96;
+         *  this field configures the point 5 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y05:8;
+        /** gamma_r_y04 : R/W; bitpos: [31:24]; default: 80;
+         *  this field configures the point 4 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y04:8;
+    };
+    uint32_t val;
+} isp_gamma_ry2_reg_t;
+
+/** Type of gamma_ry3 register
+ *  point of Y-axis of r channel gamma curve register 3
+ */
+typedef union {
+    struct {
+        /** gamma_r_y0b : R/W; bitpos: [7:0]; default: 192;
+         *  this field configures the point 11 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y0b:8;
+        /** gamma_r_y0a : R/W; bitpos: [15:8]; default: 176;
+         *  this field configures the point 10 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y0a:8;
+        /** gamma_r_y09 : R/W; bitpos: [23:16]; default: 160;
+         *  this field configures the point 9 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y09:8;
+        /** gamma_r_y08 : R/W; bitpos: [31:24]; default: 144;
+         *  this field configures the point 8 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y08:8;
+    };
+    uint32_t val;
+} isp_gamma_ry3_reg_t;
+
+/** Type of gamma_ry4 register
+ *  point of Y-axis of r channel gamma curve register 4
+ */
+typedef union {
+    struct {
+        /** gamma_r_y0f : R/W; bitpos: [7:0]; default: 255;
+         *  this field configures the point 15 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y0f:8;
+        /** gamma_r_y0e : R/W; bitpos: [15:8]; default: 240;
+         *  this field configures the point 14 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y0e:8;
+        /** gamma_r_y0d : R/W; bitpos: [23:16]; default: 224;
+         *  this field configures the point 13 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y0d:8;
+        /** gamma_r_y0c : R/W; bitpos: [31:24]; default: 208;
+         *  this field configures the point 12 of Y-axis of r channel gamma curve
+         */
+        uint32_t gamma_r_y0c:8;
+    };
+    uint32_t val;
+} isp_gamma_ry4_reg_t;
+
+/** Type of gamma_gy1 register
+ *  point of Y-axis of g channel gamma curve register 1
+ */
+typedef union {
+    struct {
+        /** gamma_g_y03 : R/W; bitpos: [7:0]; default: 64;
+         *  this field configures the point 3 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y03:8;
+        /** gamma_g_y02 : R/W; bitpos: [15:8]; default: 48;
+         *  this field configures the point 2 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y02:8;
+        /** gamma_g_y01 : R/W; bitpos: [23:16]; default: 32;
+         *  this field configures the point 1 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y01:8;
+        /** gamma_g_y00 : R/W; bitpos: [31:24]; default: 16;
+         *  this field configures the point 0 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y00:8;
+    };
+    uint32_t val;
+} isp_gamma_gy1_reg_t;
+
+/** Type of gamma_gy2 register
+ *  point of Y-axis of g channel gamma curve register 2
+ */
+typedef union {
+    struct {
+        /** gamma_g_y07 : R/W; bitpos: [7:0]; default: 128;
+         *  this field configures the point 7 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y07:8;
+        /** gamma_g_y06 : R/W; bitpos: [15:8]; default: 112;
+         *  this field configures the point 6 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y06:8;
+        /** gamma_g_y05 : R/W; bitpos: [23:16]; default: 96;
+         *  this field configures the point 5 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y05:8;
+        /** gamma_g_y04 : R/W; bitpos: [31:24]; default: 80;
+         *  this field configures the point 4 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y04:8;
+    };
+    uint32_t val;
+} isp_gamma_gy2_reg_t;
+
+/** Type of gamma_gy3 register
+ *  point of Y-axis of g channel gamma curve register 3
+ */
+typedef union {
+    struct {
+        /** gamma_g_y0b : R/W; bitpos: [7:0]; default: 192;
+         *  this field configures the point 11 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y0b:8;
+        /** gamma_g_y0a : R/W; bitpos: [15:8]; default: 176;
+         *  this field configures the point 10 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y0a:8;
+        /** gamma_g_y09 : R/W; bitpos: [23:16]; default: 160;
+         *  this field configures the point 9 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y09:8;
+        /** gamma_g_y08 : R/W; bitpos: [31:24]; default: 144;
+         *  this field configures the point 8 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y08:8;
+    };
+    uint32_t val;
+} isp_gamma_gy3_reg_t;
+
+/** Type of gamma_gy4 register
+ *  point of Y-axis of g channel gamma curve register 4
+ */
+typedef union {
+    struct {
+        /** gamma_g_y0f : R/W; bitpos: [7:0]; default: 255;
+         *  this field configures the point 15 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y0f:8;
+        /** gamma_g_y0e : R/W; bitpos: [15:8]; default: 240;
+         *  this field configures the point 14 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y0e:8;
+        /** gamma_g_y0d : R/W; bitpos: [23:16]; default: 224;
+         *  this field configures the point 13 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y0d:8;
+        /** gamma_g_y0c : R/W; bitpos: [31:24]; default: 208;
+         *  this field configures the point 12 of Y-axis of g channel gamma curve
+         */
+        uint32_t gamma_g_y0c:8;
+    };
+    uint32_t val;
+} isp_gamma_gy4_reg_t;
+
+/** Type of gamma_by1 register
+ *  point of Y-axis of b channel gamma curve register 1
+ */
+typedef union {
+    struct {
+        /** gamma_b_y03 : R/W; bitpos: [7:0]; default: 64;
+         *  this field configures the point 3 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y03:8;
+        /** gamma_b_y02 : R/W; bitpos: [15:8]; default: 48;
+         *  this field configures the point 2 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y02:8;
+        /** gamma_b_y01 : R/W; bitpos: [23:16]; default: 32;
+         *  this field configures the point 1 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y01:8;
+        /** gamma_b_y00 : R/W; bitpos: [31:24]; default: 16;
+         *  this field configures the point 0 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y00:8;
+    };
+    uint32_t val;
+} isp_gamma_by1_reg_t;
+
+/** Type of gamma_by2 register
+ *  point of Y-axis of b channel gamma curve register 2
+ */
+typedef union {
+    struct {
+        /** gamma_b_y07 : R/W; bitpos: [7:0]; default: 128;
+         *  this field configures the point 7 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y07:8;
+        /** gamma_b_y06 : R/W; bitpos: [15:8]; default: 112;
+         *  this field configures the point 6 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y06:8;
+        /** gamma_b_y05 : R/W; bitpos: [23:16]; default: 96;
+         *  this field configures the point 5 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y05:8;
+        /** gamma_b_y04 : R/W; bitpos: [31:24]; default: 80;
+         *  this field configures the point 4 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y04:8;
+    };
+    uint32_t val;
+} isp_gamma_by2_reg_t;
+
+/** Type of gamma_by3 register
+ *  point of Y-axis of b channel gamma curve register 3
+ */
+typedef union {
+    struct {
+        /** gamma_b_y0b : R/W; bitpos: [7:0]; default: 192;
+         *  this field configures the point 11 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y0b:8;
+        /** gamma_b_y0a : R/W; bitpos: [15:8]; default: 176;
+         *  this field configures the point 10 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y0a:8;
+        /** gamma_b_y09 : R/W; bitpos: [23:16]; default: 160;
+         *  this field configures the point 9 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y09:8;
+        /** gamma_b_y08 : R/W; bitpos: [31:24]; default: 144;
+         *  this field configures the point 8 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y08:8;
+    };
+    uint32_t val;
+} isp_gamma_by3_reg_t;
+
+/** Type of gamma_by4 register
+ *  point of Y-axis of b channel gamma curve register 4
+ */
+typedef union {
+    struct {
+        /** gamma_b_y0f : R/W; bitpos: [7:0]; default: 255;
+         *  this field configures the point 15 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y0f:8;
+        /** gamma_b_y0e : R/W; bitpos: [15:8]; default: 240;
+         *  this field configures the point 14 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y0e:8;
+        /** gamma_b_y0d : R/W; bitpos: [23:16]; default: 224;
+         *  this field configures the point 13 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y0d:8;
+        /** gamma_b_y0c : R/W; bitpos: [31:24]; default: 208;
+         *  this field configures the point 12 of Y-axis of b channel gamma curve
+         */
+        uint32_t gamma_b_y0c:8;
+    };
+    uint32_t val;
+} isp_gamma_by4_reg_t;
+
+/** Type of gamma_rx1 register
+ *  point of X-axis of r channel gamma curve register 1
+ */
+typedef union {
+    struct {
+        /** gamma_r_x07 : R/W; bitpos: [2:0]; default: 4;
+         *  this field configures the point 7 of X-axis of r channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x07:3;
+        /** gamma_r_x06 : R/W; bitpos: [5:3]; default: 4;
+         *  this field configures the point 6 of X-axis of r channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x06:3;
+        /** gamma_r_x05 : R/W; bitpos: [8:6]; default: 4;
+         *  this field configures the point 5 of X-axis of r channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x05:3;
+        /** gamma_r_x04 : R/W; bitpos: [11:9]; default: 4;
+         *  this field configures the point 4 of X-axis of r channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x04:3;
+        /** gamma_r_x03 : R/W; bitpos: [14:12]; default: 4;
+         *  this field configures the point 3 of X-axis of r channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x03:3;
+        /** gamma_r_x02 : R/W; bitpos: [17:15]; default: 4;
+         *  this field configures the point 2 of X-axis of r channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x02:3;
+        /** gamma_r_x01 : R/W; bitpos: [20:18]; default: 4;
+         *  this field configures the point 1 of X-axis of r channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x01:3;
+        /** gamma_r_x00 : R/W; bitpos: [23:21]; default: 4;
+         *  this field configures the point 0 of X-axis of r channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x00:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_gamma_rx1_reg_t;
+
+/** Type of gamma_rx2 register
+ *  point of X-axis of r channel gamma curve register 2
+ */
+typedef union {
+    struct {
+        /** gamma_r_x0f : R/W; bitpos: [2:0]; default: 4;
+         *  this field configures the point 15 of X-axis of r channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x0f:3;
+        /** gamma_r_x0e : R/W; bitpos: [5:3]; default: 4;
+         *  this field configures the point 14 of X-axis of r channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x0e:3;
+        /** gamma_r_x0d : R/W; bitpos: [8:6]; default: 4;
+         *  this field configures the point 13 of X-axis of r channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x0d:3;
+        /** gamma_r_x0c : R/W; bitpos: [11:9]; default: 4;
+         *  this field configures the point 12 of X-axis of r channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x0c:3;
+        /** gamma_r_x0b : R/W; bitpos: [14:12]; default: 4;
+         *  this field configures the point 11 of X-axis of r channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x0b:3;
+        /** gamma_r_x0a : R/W; bitpos: [17:15]; default: 4;
+         *  this field configures the point 10 of X-axis of r channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x0a:3;
+        /** gamma_r_x09 : R/W; bitpos: [20:18]; default: 4;
+         *  this field configures the point 9 of X-axis of r channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x09:3;
+        /** gamma_r_x08 : R/W; bitpos: [23:21]; default: 4;
+         *  this field configures the point 8 of X-axis of r channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_r_x08:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_gamma_rx2_reg_t;
+
+/** Type of gamma_gx1 register
+ *  point of X-axis of g channel gamma curve register 1
+ */
+typedef union {
+    struct {
+        /** gamma_g_x07 : R/W; bitpos: [2:0]; default: 4;
+         *  this field configures the point 7 of X-axis of g channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x07:3;
+        /** gamma_g_x06 : R/W; bitpos: [5:3]; default: 4;
+         *  this field configures the point 6 of X-axis of g channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x06:3;
+        /** gamma_g_x05 : R/W; bitpos: [8:6]; default: 4;
+         *  this field configures the point 5 of X-axis of g channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x05:3;
+        /** gamma_g_x04 : R/W; bitpos: [11:9]; default: 4;
+         *  this field configures the point 4 of X-axis of g channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x04:3;
+        /** gamma_g_x03 : R/W; bitpos: [14:12]; default: 4;
+         *  this field configures the point 3 of X-axis of g channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x03:3;
+        /** gamma_g_x02 : R/W; bitpos: [17:15]; default: 4;
+         *  this field configures the point 2 of X-axis of g channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x02:3;
+        /** gamma_g_x01 : R/W; bitpos: [20:18]; default: 4;
+         *  this field configures the point 1 of X-axis of g channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x01:3;
+        /** gamma_g_x00 : R/W; bitpos: [23:21]; default: 4;
+         *  this field configures the point 0 of X-axis of g channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x00:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_gamma_gx1_reg_t;
+
+/** Type of gamma_gx2 register
+ *  point of X-axis of g channel gamma curve register 2
+ */
+typedef union {
+    struct {
+        /** gamma_g_x0f : R/W; bitpos: [2:0]; default: 4;
+         *  this field configures the point 15 of X-axis of g channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x0f:3;
+        /** gamma_g_x0e : R/W; bitpos: [5:3]; default: 4;
+         *  this field configures the point 14 of X-axis of g channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x0e:3;
+        /** gamma_g_x0d : R/W; bitpos: [8:6]; default: 4;
+         *  this field configures the point 13 of X-axis of g channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x0d:3;
+        /** gamma_g_x0c : R/W; bitpos: [11:9]; default: 4;
+         *  this field configures the point 12 of X-axis of g channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x0c:3;
+        /** gamma_g_x0b : R/W; bitpos: [14:12]; default: 4;
+         *  this field configures the point 11 of X-axis of g channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x0b:3;
+        /** gamma_g_x0a : R/W; bitpos: [17:15]; default: 4;
+         *  this field configures the point 10 of X-axis of g channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x0a:3;
+        /** gamma_g_x09 : R/W; bitpos: [20:18]; default: 4;
+         *  this field configures the point 9 of X-axis of g channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x09:3;
+        /** gamma_g_x08 : R/W; bitpos: [23:21]; default: 4;
+         *  this field configures the point 8 of X-axis of g channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_g_x08:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_gamma_gx2_reg_t;
+
+/** Type of gamma_bx1 register
+ *  point of X-axis of b channel gamma curve register 1
+ */
+typedef union {
+    struct {
+        /** gamma_b_x07 : R/W; bitpos: [2:0]; default: 4;
+         *  this field configures the point 7 of X-axis of b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x07:3;
+        /** gamma_b_x06 : R/W; bitpos: [5:3]; default: 4;
+         *  this field configures the point 6 of X-axis of b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x06:3;
+        /** gamma_b_x05 : R/W; bitpos: [8:6]; default: 4;
+         *  this field configures the point 5 of X-axis of b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x05:3;
+        /** gamma_b_x04 : R/W; bitpos: [11:9]; default: 4;
+         *  this field configures the point 4 of X-axis of b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x04:3;
+        /** gamma_b_x03 : R/W; bitpos: [14:12]; default: 4;
+         *  this field configures the point 3 of X-axis of b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x03:3;
+        /** gamma_b_x02 : R/W; bitpos: [17:15]; default: 4;
+         *  this field configures the point 2 of X-axis of b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x02:3;
+        /** gamma_b_x01 : R/W; bitpos: [20:18]; default: 4;
+         *  this field configures the point 1 of X-axis of b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x01:3;
+        /** gamma_b_x00 : R/W; bitpos: [23:21]; default: 4;
+         *  this field configures the point 0 of X-axis of b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x00:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_gamma_bx1_reg_t;
+
+/** Type of gamma_bx2 register
+ *  point of X-axis of b channel gamma curve register 2
+ */
+typedef union {
+    struct {
+        /** gamma_b_x0f : R/W; bitpos: [2:0]; default: 4;
+         *  this field configures the point 15 of X-axis of b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x0f:3;
+        /** gamma_b_x0e : R/W; bitpos: [5:3]; default: 4;
+         *  this field configures the point 14 of X-axis of b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x0e:3;
+        /** gamma_b_x0d : R/W; bitpos: [8:6]; default: 4;
+         *  this field configures the point 13 of X-axis of b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x0d:3;
+        /** gamma_b_x0c : R/W; bitpos: [11:9]; default: 4;
+         *  this field configures the point 12 of X-axis of b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x0c:3;
+        /** gamma_b_x0b : R/W; bitpos: [14:12]; default: 4;
+         *  this field configures the point 11 of X-axis of b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x0b:3;
+        /** gamma_b_x0a : R/W; bitpos: [17:15]; default: 4;
+         *  this field configures the point 10 of X-axis of b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x0a:3;
+        /** gamma_b_x09 : R/W; bitpos: [20:18]; default: 4;
+         *  this field configures the point 9 of X-axis of b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x09:3;
+        /** gamma_b_x08 : R/W; bitpos: [23:21]; default: 4;
+         *  this field configures the point 8 of X-axis of b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_b_x08:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_gamma_bx2_reg_t;
+
+/** Type of ae_ctrl register
+ *  ae control register
+ */
+typedef union {
+    struct {
+        /** ae_update : WT; bitpos: [0]; default: 0;
+         *  write 1 to this bit triggers one statistic event
+         */
+        uint32_t ae_update:1;
+        /** ae_select : R/W; bitpos: [1]; default: 0;
+         *  this field configures ae input data source, 0: data from median, 1: data from gama
+         */
+        uint32_t ae_select:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} isp_ae_ctrl_reg_t;
+
+/** Type of ae_monitor register
+ *  ae monitor control register
+ */
+typedef union {
+    struct {
+        /** ae_monitor_tl : R/W; bitpos: [7:0]; default: 0;
+         *  this field configures the lower lum threshold of ae monitor
+         */
+        uint32_t ae_monitor_tl:8;
+        /** ae_monitor_th : R/W; bitpos: [15:8]; default: 0;
+         *  this field configures the higher lum threshold of ae monitor
+         */
+        uint32_t ae_monitor_th:8;
+        /** ae_monitor_period : R/W; bitpos: [21:16]; default: 0;
+         *  this field configures ae monitor frame period
+         */
+        uint32_t ae_monitor_period:6;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} isp_ae_monitor_reg_t;
+
+/** Type of ae_bx register
+ *  ae window register in x-direction
+ */
+typedef union {
+    struct {
+        /** ae_x_bsize : R/W; bitpos: [10:0]; default: 384;
+         *  this field configures every block x size
+         */
+        uint32_t ae_x_bsize:11;
+        /** ae_x_start : R/W; bitpos: [21:11]; default: 0;
+         *  this field configures first block start x address
+         */
+        uint32_t ae_x_start:11;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} isp_ae_bx_reg_t;
+
+/** Type of ae_by register
+ *  ae window register in y-direction
+ */
+typedef union {
+    struct {
+        /** ae_y_bsize : R/W; bitpos: [10:0]; default: 216;
+         *  this field configures every block y size
+         */
+        uint32_t ae_y_bsize:11;
+        /** ae_y_start : R/W; bitpos: [21:11]; default: 0;
+         *  this field configures first block start y address
+         */
+        uint32_t ae_y_start:11;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} isp_ae_by_reg_t;
+
+/** Type of ae_winpixnum register
+ *  ae sub-window pix num register
+ */
+typedef union {
+    struct {
+        /** ae_subwin_pixnum : R/W; bitpos: [16:0]; default: 82944;
+         *  this field configures the pixel number of each sub win
+         */
+        uint32_t ae_subwin_pixnum:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_ae_winpixnum_reg_t;
+
+/** Type of ae_win_reciprocal register
+ *  reciprocal of ae sub-window pixel number
+ */
+typedef union {
+    struct {
+        /** ae_subwin_recip : R/W; bitpos: [19:0]; default: 0;
+         *  this field configures the reciprocal of each subwin_pixnum, 20bit fraction
+         */
+        uint32_t ae_subwin_recip:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} isp_ae_win_reciprocal_reg_t;
+
+/** Type of sharp_ctrl0 register
+ *  sharp control register 0
+ */
+typedef union {
+    struct {
+        /** sharp_threshold_low : R/W; bitpos: [7:0]; default: 0;
+         *  this field configures sharpen threshold for detail
+         */
+        uint32_t sharp_threshold_low:8;
+        /** sharp_threshold_high : R/W; bitpos: [15:8]; default: 0;
+         *  this field configures sharpen threshold for edge
+         */
+        uint32_t sharp_threshold_high:8;
+        /** sharp_amount_low : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures sharpen amount for detail
+         */
+        uint32_t sharp_amount_low:8;
+        /** sharp_amount_high : R/W; bitpos: [31:24]; default: 0;
+         *  this field configures sharpen amount for edge
+         */
+        uint32_t sharp_amount_high:8;
+    };
+    uint32_t val;
+} isp_sharp_ctrl0_reg_t;
+
+/** Type of sharp_filter0 register
+ *  sharp usm config register 0
+ */
+typedef union {
+    struct {
+        /** sharp_filter_coe00 : R/W; bitpos: [4:0]; default: 1;
+         *  this field configures unsharp masking(usm) filter coefficient
+         */
+        uint32_t sharp_filter_coe00:5;
+        /** sharp_filter_coe01 : R/W; bitpos: [9:5]; default: 2;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe01:5;
+        /** sharp_filter_coe02 : R/W; bitpos: [14:10]; default: 1;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe02:5;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} isp_sharp_filter0_reg_t;
+
+/** Type of sharp_filter1 register
+ *  sharp usm config register 1
+ */
+typedef union {
+    struct {
+        /** sharp_filter_coe10 : R/W; bitpos: [4:0]; default: 2;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe10:5;
+        /** sharp_filter_coe11 : R/W; bitpos: [9:5]; default: 4;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe11:5;
+        /** sharp_filter_coe12 : R/W; bitpos: [14:10]; default: 2;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe12:5;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} isp_sharp_filter1_reg_t;
+
+/** Type of sharp_filter2 register
+ *  sharp usm config register 2
+ */
+typedef union {
+    struct {
+        /** sharp_filter_coe20 : R/W; bitpos: [4:0]; default: 1;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe20:5;
+        /** sharp_filter_coe21 : R/W; bitpos: [9:5]; default: 2;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe21:5;
+        /** sharp_filter_coe22 : R/W; bitpos: [14:10]; default: 1;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe22:5;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} isp_sharp_filter2_reg_t;
+
+/** Type of sharp_matrix_ctrl register
+ *  sharp pix2matrix ctrl
+ */
+typedef union {
+    struct {
+        /** sharp_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0;
+         *  matrix tail pixen low level threshold,  should not to large to prevent expanding to
+         *  next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and
+         *  reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th <
+         *  reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function
+         */
+        uint32_t sharp_tail_pixen_pulse_tl:8;
+        /** sharp_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0;
+         *  matrix tail pixen high level threshold, must < hnum-1, only
+         *  reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and
+         *  reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail
+         *  pulse function
+         */
+        uint32_t sharp_tail_pixen_pulse_th:8;
+        /** sharp_padding_data : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures sharp padding data
+         */
+        uint32_t sharp_padding_data:8;
+        /** sharp_padding_mode : R/W; bitpos: [24]; default: 0;
+         *  this field configures sharp padding mode
+         */
+        uint32_t sharp_padding_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} isp_sharp_matrix_ctrl_reg_t;
+
+/** Type of sharp_ctrl1 register
+ *  sharp control register 1
+ */
+typedef union {
+    struct {
+        /** sharp_gradient_max : RO; bitpos: [7:0]; default: 0;
+         *  this field configures sharp max gradient, refresh at the end of each frame end
+         */
+        uint32_t sharp_gradient_max:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} isp_sharp_ctrl1_reg_t;
+
+/** Type of dma_cntl register
+ *  isp dma source trans control register
+ */
+typedef union {
+    struct {
+        /** dma_en : WT; bitpos: [0]; default: 0;
+         *  write 1 to trigger dma to get 1 frame
+         */
+        uint32_t dma_en:1;
+        /** dma_update_reg : R/W; bitpos: [1]; default: 0;
+         *  write 1 to update reg_dma_burst_len & reg_dma_data_type
+         */
+        uint32_t dma_update_reg:1;
+        /** dma_data_type : R/W; bitpos: [7:2]; default: 42;
+         *  this field configures the idi data type for image data
+         */
+        uint32_t dma_data_type:6;
+        /** dma_burst_len : R/W; bitpos: [19:8]; default: 128;
+         *  this field configures dma burst len when data source is dma. set according to
+         *  dma_msize, it is the number of 64bits in a dma transfer
+         */
+        uint32_t dma_burst_len:12;
+        /** dma_interval : R/W; bitpos: [31:20]; default: 1;
+         *  this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ...
+         */
+        uint32_t dma_interval:12;
+    };
+    uint32_t val;
+} isp_dma_cntl_reg_t;
+
+/** Type of dma_raw_data register
+ *  isp dma source total raw number set register
+ */
+typedef union {
+    struct {
+        /** dma_raw_num_total : R/W; bitpos: [21:0]; default: 0;
+         *  this field configures the the number of 64bits in a frame
+         */
+        uint32_t dma_raw_num_total:22;
+        uint32_t reserved_22:9;
+        /** dma_raw_num_total_set : WT; bitpos: [31]; default: 0;
+         *  write 1 to update reg_dma_raw_num_total
+         */
+        uint32_t dma_raw_num_total_set:1;
+    };
+    uint32_t val;
+} isp_dma_raw_data_reg_t;
+
+/** Type of cam_cntl register
+ *  isp cam source control register
+ */
+typedef union {
+    struct {
+        /** cam_en : R/W; bitpos: [0]; default: 0;
+         *  write 1 to start receive camera data, write 0 to disable
+         */
+        uint32_t cam_en:1;
+        /** cam_update_reg : R/W; bitpos: [1]; default: 0;
+         *  write 1 to update ISP_CAM_CONF
+         */
+        uint32_t cam_update_reg:1;
+        /** cam_reset : R/W; bitpos: [2]; default: 1;
+         *  this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset
+         */
+        uint32_t cam_reset:1;
+        /** cam_clk_inv : R/W; bitpos: [3]; default: 0;
+         *  this bit configures the inversion of cam clk from pad. 0: not invert cam clk, 1:
+         *  invert cam clk
+         */
+        uint32_t cam_clk_inv:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} isp_cam_cntl_reg_t;
+
+/** Type of cam_conf register
+ *  isp cam source config register
+ */
+typedef union {
+    struct {
+        /** cam_data_order : R/W; bitpos: [0]; default: 0;
+         *  this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0],
+         *  cam_data_in[15:8]}
+         */
+        uint32_t cam_data_order:1;
+        /** cam_2byte_mode : R/W; bitpos: [1]; default: 0;
+         *  this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0:
+         *  disable, 1: enable
+         */
+        uint32_t cam_2byte_mode:1;
+        /** cam_data_type : R/W; bitpos: [7:2]; default: 42;
+         *  this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c:
+         *  RAW12
+         */
+        uint32_t cam_data_type:6;
+        /** cam_de_inv : R/W; bitpos: [8]; default: 0;
+         *  this bit configures cam data enable invert. 0: not invert, 1: invert
+         */
+        uint32_t cam_de_inv:1;
+        /** cam_hsync_inv : R/W; bitpos: [9]; default: 0;
+         *  this bit configures cam hsync invert. 0: not invert, 1: invert
+         */
+        uint32_t cam_hsync_inv:1;
+        /** cam_vsync_inv : R/W; bitpos: [10]; default: 0;
+         *  this bit configures cam vsync invert. 0: not invert, 1: invert
+         */
+        uint32_t cam_vsync_inv:1;
+        /** cam_vsync_filter_thres : R/W; bitpos: [13:11]; default: 0;
+         *  this bit configures the number of clock of vsync filter length
+         */
+        uint32_t cam_vsync_filter_thres:3;
+        /** cam_vsync_filter_en : R/W; bitpos: [14]; default: 0;
+         *  this bit configures vsync filter en
+         */
+        uint32_t cam_vsync_filter_en:1;
+        /** cam_de_only : R/W; bitpos: [15]; default: 0;
+         *  configures whether cam inf only has de, no hsync data. 0: has hsync, 1: no hsync
+         */
+        uint32_t cam_de_only:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} isp_cam_conf_reg_t;
+
+/** Type of af_ctrl0 register
+ *  af control register 0
+ */
+typedef union {
+    struct {
+        /** af_auto_update : R/W; bitpos: [0]; default: 0;
+         *  this bit configures auto_update enable. when set to 1, will update sum and lum each
+         *  frame
+         */
+        uint32_t af_auto_update:1;
+        uint32_t reserved_1:3;
+        /** af_manual_update : WT; bitpos: [4]; default: 0;
+         *  write 1 to this bit will update the sum and lum once
+         */
+        uint32_t af_manual_update:1;
+        uint32_t reserved_5:3;
+        /** af_env_threshold : R/W; bitpos: [11:8]; default: 0;
+         *  this field configures env threshold. when both sum and lum changes larger than this
+         *  value, consider environment changes and need to trigger a new autofocus. 4Bit
+         *  fractional
+         */
+        uint32_t af_env_threshold:4;
+        uint32_t reserved_12:4;
+        /** af_env_period : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures environment changes detection period (frame). When set to 0,
+         *  disable this function
+         */
+        uint32_t af_env_period:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_af_ctrl0_reg_t;
+
+/** Type of af_ctrl1 register
+ *  af control register 1
+ */
+typedef union {
+    struct {
+        /** af_thpixnum : R/W; bitpos: [21:0]; default: 0;
+         *  this field configures pixnum used when calculating the autofocus threshold. Set to
+         *  0 to disable threshold calculation
+         */
+        uint32_t af_thpixnum:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} isp_af_ctrl1_reg_t;
+
+/** Type of af_gen_th_ctrl register
+ *  af gen threshold control register
+ */
+typedef union {
+    struct {
+        /** af_gen_threshold_min : R/W; bitpos: [15:0]; default: 128;
+         *  this field configures min threshold when use auto_threshold
+         */
+        uint32_t af_gen_threshold_min:16;
+        /** af_gen_threshold_max : R/W; bitpos: [31:16]; default: 1088;
+         *  this field configures max threshold when use auto_threshold
+         */
+        uint32_t af_gen_threshold_max:16;
+    };
+    uint32_t val;
+} isp_af_gen_th_ctrl_reg_t;
+
+/** Type of af_env_user_th_sum register
+ *  af monitor user sum threshold register
+ */
+typedef union {
+    struct {
+        /** af_env_user_threshold_sum : R/W; bitpos: [31:0]; default: 0;
+         *  this field configures user setup env detect sum threshold
+         */
+        uint32_t af_env_user_threshold_sum:32;
+    };
+    uint32_t val;
+} isp_af_env_user_th_sum_reg_t;
+
+/** Type of af_env_user_th_lum register
+ *  af monitor user lum threshold register
+ */
+typedef union {
+    struct {
+        /** af_env_user_threshold_lum : R/W; bitpos: [29:0]; default: 0;
+         *  this field configures user setup env detect lum threshold
+         */
+        uint32_t af_env_user_threshold_lum:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_af_env_user_th_lum_reg_t;
+
+/** Type of af_threshold register
+ *  af threshold register
+ */
+typedef union {
+    struct {
+        /** af_threshold : R/W; bitpos: [15:0]; default: 256;
+         *  this field configures user threshold. When set to non-zero, autofocus will use this
+         *  threshold
+         */
+        uint32_t af_threshold:16;
+        /** af_gen_threshold : RO; bitpos: [31:16]; default: 0;
+         *  this field represents the last calculated threshold
+         */
+        uint32_t af_gen_threshold:16;
+    };
+    uint32_t val;
+} isp_af_threshold_reg_t;
+
+/** Type of af_hscale_a register
+ *  h-scale of af window a register
+ */
+typedef union {
+    struct {
+        /** af_rpoint_a : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures left coordinate of focus window a, must >= 2
+         */
+        uint32_t af_rpoint_a:12;
+        uint32_t reserved_12:4;
+        /** af_lpoint_a : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures top coordinate of focus window a, must >= 2
+         */
+        uint32_t af_lpoint_a:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_hscale_a_reg_t;
+
+/** Type of af_vscale_a register
+ *  v-scale of af window a register
+ */
+typedef union {
+    struct {
+        /** af_bpoint_a : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures right coordinate of focus window a, must <= hnum-2
+         */
+        uint32_t af_bpoint_a:12;
+        uint32_t reserved_12:4;
+        /** af_tpoint_a : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures bottom coordinate of focus window a, must <= hnum-2
+         */
+        uint32_t af_tpoint_a:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_vscale_a_reg_t;
+
+/** Type of af_hscale_b register
+ *  h-scale of af window b register
+ */
+typedef union {
+    struct {
+        /** af_rpoint_b : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures left coordinate of focus window b, must >= 2
+         */
+        uint32_t af_rpoint_b:12;
+        uint32_t reserved_12:4;
+        /** af_lpoint_b : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures top coordinate of focus window b, must >= 2
+         */
+        uint32_t af_lpoint_b:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_hscale_b_reg_t;
+
+/** Type of af_vscale_b register
+ *  v-scale of af window b register
+ */
+typedef union {
+    struct {
+        /** af_bpoint_b : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures right coordinate of focus window b, must <= hnum-2
+         */
+        uint32_t af_bpoint_b:12;
+        uint32_t reserved_12:4;
+        /** af_tpoint_b : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures bottom coordinate of focus window b, must <= hnum-2
+         */
+        uint32_t af_tpoint_b:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_vscale_b_reg_t;
+
+/** Type of af_hscale_c register
+ *  v-scale of af window c register
+ */
+typedef union {
+    struct {
+        /** af_rpoint_c : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures left coordinate of focus window c, must >= 2
+         */
+        uint32_t af_rpoint_c:12;
+        uint32_t reserved_12:4;
+        /** af_lpoint_c : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures top coordinate of focus window c, must >= 2
+         */
+        uint32_t af_lpoint_c:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_hscale_c_reg_t;
+
+/** Type of af_vscale_c register
+ *  v-scale of af window c register
+ */
+typedef union {
+    struct {
+        /** af_bpoint_c : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures right coordinate of focus window c, must <= hnum-2
+         */
+        uint32_t af_bpoint_c:12;
+        uint32_t reserved_12:4;
+        /** af_tpoint_c : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures bottom coordinate of focus window c, must <= hnum-2
+         */
+        uint32_t af_tpoint_c:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_vscale_c_reg_t;
+
+/** Type of awb_mode register
+ *  awb mode control register
+ */
+typedef union {
+    struct {
+        /** awb_mode : R/W; bitpos: [1:0]; default: 3;
+         *  this field configures awb algo sel. 00: none selected. 01: sel algo0. 10: sel
+         *  algo1. 11: sel both algo0 and algo1
+         */
+        uint32_t awb_mode:2;
+        uint32_t reserved_2:2;
+        /** awb_sample : R/W; bitpos: [4]; default: 0;
+         *  this bit configures awb sample location, 0:before ccm, 1:after ccm
+         */
+        uint32_t awb_sample:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} isp_awb_mode_reg_t;
+
+/** Type of awb_hscale register
+ *  h-scale of awb window
+ */
+typedef union {
+    struct {
+        /** awb_rpoint : R/W; bitpos: [11:0]; default: 1919;
+         *  this field configures awb window right coordinate
+         */
+        uint32_t awb_rpoint:12;
+        uint32_t reserved_12:4;
+        /** awb_lpoint : R/W; bitpos: [27:16]; default: 0;
+         *  this field configures awb window left coordinate
+         */
+        uint32_t awb_lpoint:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_awb_hscale_reg_t;
+
+/** Type of awb_vscale register
+ *  v-scale of awb window
+ */
+typedef union {
+    struct {
+        /** awb_bpoint : R/W; bitpos: [11:0]; default: 1079;
+         *  this field configures awb window bottom coordinate
+         */
+        uint32_t awb_bpoint:12;
+        uint32_t reserved_12:4;
+        /** awb_tpoint : R/W; bitpos: [27:16]; default: 0;
+         *  this field configures awb window top coordinate
+         */
+        uint32_t awb_tpoint:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_awb_vscale_reg_t;
+
+/** Type of awb_th_lum register
+ *  awb lum threshold register
+ */
+typedef union {
+    struct {
+        /** awb_min_lum : R/W; bitpos: [9:0]; default: 0;
+         *  this field configures lower threshold of r+g+b
+         */
+        uint32_t awb_min_lum:10;
+        uint32_t reserved_10:6;
+        /** awb_max_lum : R/W; bitpos: [25:16]; default: 765;
+         *  this field configures upper threshold of r+g+b
+         */
+        uint32_t awb_max_lum:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_awb_th_lum_reg_t;
+
+/** Type of awb_th_rg register
+ *  awb r/g threshold register
+ */
+typedef union {
+    struct {
+        /** awb_min_rg : R/W; bitpos: [9:0]; default: 0;
+         *  this field configures lower threshold of r/g, 2bit integer and 8bit fraction
+         */
+        uint32_t awb_min_rg:10;
+        uint32_t reserved_10:6;
+        /** awb_max_rg : R/W; bitpos: [25:16]; default: 1023;
+         *  this field configures upper threshold of r/g, 2bit integer and 8bit fraction
+         */
+        uint32_t awb_max_rg:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_awb_th_rg_reg_t;
+
+/** Type of awb_th_bg register
+ *  awb b/g threshold register
+ */
+typedef union {
+    struct {
+        /** awb_min_bg : R/W; bitpos: [9:0]; default: 0;
+         *  this field configures lower threshold of b/g, 2bit integer and 8bit fraction
+         */
+        uint32_t awb_min_bg:10;
+        uint32_t reserved_10:6;
+        /** awb_max_bg : R/W; bitpos: [25:16]; default: 1023;
+         *  this field configures upper threshold of b/g, 2bit integer and 8bit fraction
+         */
+        uint32_t awb_max_bg:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_awb_th_bg_reg_t;
+
+/** Type of color_ctrl register
+ *  color control register
+ */
+typedef union {
+    struct {
+        /** color_saturation : R/W; bitpos: [7:0]; default: 128;
+         *  this field configures the color saturation value
+         */
+        uint32_t color_saturation:8;
+        /** color_hue : R/W; bitpos: [15:8]; default: 0;
+         *  this field configures the color hue angle
+         */
+        uint32_t color_hue:8;
+        /** color_contrast : R/W; bitpos: [23:16]; default: 128;
+         *  this field configures the color contrast value
+         */
+        uint32_t color_contrast:8;
+        /** color_brightness : R/W; bitpos: [31:24]; default: 0;
+         *  this field configures the color brightness value, signed 2's complement
+         */
+        uint32_t color_brightness:8;
+    };
+    uint32_t val;
+} isp_color_ctrl_reg_t;
+
+/** Type of blc_value register
+ *  blc black level register
+ */
+typedef union {
+    struct {
+        /** blc_r3_value : R/W; bitpos: [7:0]; default: 0;
+         *  this field configures the black level of bottom right channel of bayer img
+         */
+        uint32_t blc_r3_value:8;
+        /** blc_r2_value : R/W; bitpos: [15:8]; default: 0;
+         *  this field configures the black level of bottom left channel of bayer img
+         */
+        uint32_t blc_r2_value:8;
+        /** blc_r1_value : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures the black level of top right channel of bayer img
+         */
+        uint32_t blc_r1_value:8;
+        /** blc_r0_value : R/W; bitpos: [31:24]; default: 0;
+         *  this field configures the black level of top left channel of bayer img
+         */
+        uint32_t blc_r0_value:8;
+    };
+    uint32_t val;
+} isp_blc_value_reg_t;
+
+/** Type of blc_ctrl0 register
+ *  blc stretch control register
+ */
+typedef union {
+    struct {
+        /** blc_r3_stretch : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the stretch feature of bottom right channel. 0: stretch
+         *  disable, 1: stretch enable
+         */
+        uint32_t blc_r3_stretch:1;
+        /** blc_r2_stretch : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the stretch feature of bottom left channel. 0: stretch disable,
+         *  1: stretch enable
+         */
+        uint32_t blc_r2_stretch:1;
+        /** blc_r1_stretch : R/W; bitpos: [2]; default: 0;
+         *  this bit configures the stretch feature of top right channel. 0: stretch disable,
+         *  1: stretch enable
+         */
+        uint32_t blc_r1_stretch:1;
+        /** blc_r0_stretch : R/W; bitpos: [3]; default: 0;
+         *  this bit configures the stretch feature of top left channel. 0: stretch disable, 1:
+         *  stretch enable
+         */
+        uint32_t blc_r0_stretch:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} isp_blc_ctrl0_reg_t;
+
+/** Type of blc_ctrl1 register
+ *  blc window control register
+ */
+typedef union {
+    struct {
+        /** blc_window_top : R/W; bitpos: [10:0]; default: 0;
+         *  this field configures blc average calculation window top
+         */
+        uint32_t blc_window_top:11;
+        /** blc_window_left : R/W; bitpos: [21:11]; default: 0;
+         *  this field configures blc average calculation window left
+         */
+        uint32_t blc_window_left:11;
+        /** blc_window_vnum : R/W; bitpos: [25:22]; default: 0;
+         *  this field configures blc average calculation window vnum
+         */
+        uint32_t blc_window_vnum:4;
+        /** blc_window_hnum : R/W; bitpos: [29:26]; default: 0;
+         *  this field configures blc average calculation window hnum
+         */
+        uint32_t blc_window_hnum:4;
+        /** blc_filter_en : R/W; bitpos: [30]; default: 0;
+         *  this bit configures enable blc average input filter. 0: disable, 1: enable
+         */
+        uint32_t blc_filter_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} isp_blc_ctrl1_reg_t;
+
+/** Type of blc_ctrl2 register
+ *  blc black threshold control register
+ */
+typedef union {
+    struct {
+        /** blc_r3_th : R/W; bitpos: [7:0]; default: 0;
+         *  this field configures black threshold when get blc average of bottom right channel
+         */
+        uint32_t blc_r3_th:8;
+        /** blc_r2_th : R/W; bitpos: [15:8]; default: 0;
+         *  this field configures black threshold when get blc average of bottom left channel
+         */
+        uint32_t blc_r2_th:8;
+        /** blc_r1_th : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures black threshold when get blc average of top right channel
+         */
+        uint32_t blc_r1_th:8;
+        /** blc_r0_th : R/W; bitpos: [31:24]; default: 0;
+         *  this field configures black threshold when get blc average of top left channel
+         */
+        uint32_t blc_r0_th:8;
+    };
+    uint32_t val;
+} isp_blc_ctrl2_reg_t;
+
+/** Type of hist_mode register
+ *  histogram mode control register
+ */
+typedef union {
+    struct {
+        /** hist_mode : R/W; bitpos: [2:0]; default: 4;
+         *  this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4:
+         *  RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V
+         */
+        uint32_t hist_mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} isp_hist_mode_reg_t;
+
+/** Type of hist_coeff register
+ *  histogram rgb to gray coefficients register
+ */
+typedef union {
+    struct {
+        /** hist_coeff_b : R/W; bitpos: [7:0]; default: 85;
+         *  this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r
+         *  and coeff_g and coeff_b should be 256
+         */
+        uint32_t hist_coeff_b:8;
+        /** hist_coeff_g : R/W; bitpos: [15:8]; default: 85;
+         *  this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r
+         *  and coeff_g and coeff_b should be 256
+         */
+        uint32_t hist_coeff_g:8;
+        /** hist_coeff_r : R/W; bitpos: [23:16]; default: 85;
+         *  this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r
+         *  and coeff_g and coeff_b should be 256
+         */
+        uint32_t hist_coeff_r:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_hist_coeff_reg_t;
+
+/** Type of hist_offs register
+ *  histogram window offsets register
+ */
+typedef union {
+    struct {
+        /** hist_y_offs : R/W; bitpos: [11:0]; default: 0;
+         *  this field configures y coordinate of first window
+         */
+        uint32_t hist_y_offs:12;
+        uint32_t reserved_12:4;
+        /** hist_x_offs : R/W; bitpos: [27:16]; default: 0;
+         *  this field configures x coordinate of first window
+         */
+        uint32_t hist_x_offs:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_hist_offs_reg_t;
+
+/** Type of hist_size register
+ *  histogram sub-window size register
+ */
+typedef union {
+    struct {
+        /** hist_y_size : R/W; bitpos: [8:0]; default: 32;
+         *  this field configures y direction size of subwindow
+         */
+        uint32_t hist_y_size:9;
+        uint32_t reserved_9:7;
+        /** hist_x_size : R/W; bitpos: [24:16]; default: 18;
+         *  this field configures x direction size of subwindow
+         */
+        uint32_t hist_x_size:9;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} isp_hist_size_reg_t;
+
+/** Type of hist_seg0 register
+ *  histogram bin control register 0
+ */
+typedef union {
+    struct {
+        /** hist_seg_3_4 : R/W; bitpos: [7:0]; default: 64;
+         *  this field configures threshold of histogram bin 3 and bin 4
+         */
+        uint32_t hist_seg_3_4:8;
+        /** hist_seg_2_3 : R/W; bitpos: [15:8]; default: 48;
+         *  this field configures threshold of histogram bin 2 and bin 3
+         */
+        uint32_t hist_seg_2_3:8;
+        /** hist_seg_1_2 : R/W; bitpos: [23:16]; default: 32;
+         *  this field configures threshold of histogram bin 1 and bin 2
+         */
+        uint32_t hist_seg_1_2:8;
+        /** hist_seg_0_1 : R/W; bitpos: [31:24]; default: 16;
+         *  this field configures threshold of histogram bin 0 and bin 1
+         */
+        uint32_t hist_seg_0_1:8;
+    };
+    uint32_t val;
+} isp_hist_seg0_reg_t;
+
+/** Type of hist_seg1 register
+ *  histogram bin control register 1
+ */
+typedef union {
+    struct {
+        /** hist_seg_7_8 : R/W; bitpos: [7:0]; default: 128;
+         *  this field configures threshold of histogram bin 7 and bin 8
+         */
+        uint32_t hist_seg_7_8:8;
+        /** hist_seg_6_7 : R/W; bitpos: [15:8]; default: 112;
+         *  this field configures threshold of histogram bin 6 and bin 7
+         */
+        uint32_t hist_seg_6_7:8;
+        /** hist_seg_5_6 : R/W; bitpos: [23:16]; default: 96;
+         *  this field configures threshold of histogram bin 5 and bin 6
+         */
+        uint32_t hist_seg_5_6:8;
+        /** hist_seg_4_5 : R/W; bitpos: [31:24]; default: 80;
+         *  this field configures threshold of histogram bin 4 and bin 5
+         */
+        uint32_t hist_seg_4_5:8;
+    };
+    uint32_t val;
+} isp_hist_seg1_reg_t;
+
+/** Type of hist_seg2 register
+ *  histogram bin control register 2
+ */
+typedef union {
+    struct {
+        /** hist_seg_11_12 : R/W; bitpos: [7:0]; default: 192;
+         *  this field configures threshold of histogram bin 11 and bin 12
+         */
+        uint32_t hist_seg_11_12:8;
+        /** hist_seg_10_11 : R/W; bitpos: [15:8]; default: 176;
+         *  this field configures threshold of histogram bin 10 and bin 11
+         */
+        uint32_t hist_seg_10_11:8;
+        /** hist_seg_9_10 : R/W; bitpos: [23:16]; default: 160;
+         *  this field configures threshold of histogram bin 9 and bin 10
+         */
+        uint32_t hist_seg_9_10:8;
+        /** hist_seg_8_9 : R/W; bitpos: [31:24]; default: 144;
+         *  this field configures threshold of histogram bin 8 and bin 9
+         */
+        uint32_t hist_seg_8_9:8;
+    };
+    uint32_t val;
+} isp_hist_seg2_reg_t;
+
+/** Type of hist_seg3 register
+ *  histogram bin control register 3
+ */
+typedef union {
+    struct {
+        /** hist_seg_14_15 : R/W; bitpos: [7:0]; default: 240;
+         *  this field configures threshold of histogram bin 14 and bin 15
+         */
+        uint32_t hist_seg_14_15:8;
+        /** hist_seg_13_14 : R/W; bitpos: [15:8]; default: 224;
+         *  this field configures threshold of histogram bin 13 and bin 14
+         */
+        uint32_t hist_seg_13_14:8;
+        /** hist_seg_12_13 : R/W; bitpos: [23:16]; default: 208;
+         *  this field configures threshold of histogram bin 12 and bin 13
+         */
+        uint32_t hist_seg_12_13:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_hist_seg3_reg_t;
+
+/** Type of hist_weight0 register
+ *  histogram sub-window weight register 0
+ */
+typedef union {
+    struct {
+        /** hist_weight_03 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 03
+         */
+        uint32_t hist_weight_03:8;
+        /** hist_weight_02 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 02
+         */
+        uint32_t hist_weight_02:8;
+        /** hist_weight_01 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 01
+         */
+        uint32_t hist_weight_01:8;
+        /** hist_weight_00 : R/W; bitpos: [31:24]; default: 1;
+         *  this field configures weight of subwindow 00 and sum of all weight should be 256
+         */
+        uint32_t hist_weight_00:8;
+    };
+    uint32_t val;
+} isp_hist_weight0_reg_t;
+
+/** Type of hist_weight1 register
+ *  histogram sub-window weight register 1
+ */
+typedef union {
+    struct {
+        /** hist_weight_12 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 12
+         */
+        uint32_t hist_weight_12:8;
+        /** hist_weight_11 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 11
+         */
+        uint32_t hist_weight_11:8;
+        /** hist_weight_10 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 10
+         */
+        uint32_t hist_weight_10:8;
+        /** hist_weight_04 : R/W; bitpos: [31:24]; default: 1;
+         *  this field configures weight of subwindow 04
+         */
+        uint32_t hist_weight_04:8;
+    };
+    uint32_t val;
+} isp_hist_weight1_reg_t;
+
+/** Type of hist_weight2 register
+ *  histogram sub-window weight register 2
+ */
+typedef union {
+    struct {
+        /** hist_weight_21 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 21
+         */
+        uint32_t hist_weight_21:8;
+        /** hist_weight_20 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 20
+         */
+        uint32_t hist_weight_20:8;
+        /** hist_weight_14 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 04
+         */
+        uint32_t hist_weight_14:8;
+        /** hist_weight_13 : R/W; bitpos: [31:24]; default: 1;
+         *  this field configures weight of subwindow 13
+         */
+        uint32_t hist_weight_13:8;
+    };
+    uint32_t val;
+} isp_hist_weight2_reg_t;
+
+/** Type of hist_weight3 register
+ *  histogram sub-window weight register 3
+ */
+typedef union {
+    struct {
+        /** hist_weight_30 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 30
+         */
+        uint32_t hist_weight_30:8;
+        /** hist_weight_24 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 24
+         */
+        uint32_t hist_weight_24:8;
+        /** hist_weight_23 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 23
+         */
+        uint32_t hist_weight_23:8;
+        /** hist_weight_22 : R/W; bitpos: [31:24]; default: 232;
+         *  this field configures weight of subwindow 22
+         */
+        uint32_t hist_weight_22:8;
+    };
+    uint32_t val;
+} isp_hist_weight3_reg_t;
+
+/** Type of hist_weight4 register
+ *  histogram sub-window weight register 4
+ */
+typedef union {
+    struct {
+        /** hist_weight_34 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 34
+         */
+        uint32_t hist_weight_34:8;
+        /** hist_weight_33 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 33
+         */
+        uint32_t hist_weight_33:8;
+        /** hist_weight_32 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 32
+         */
+        uint32_t hist_weight_32:8;
+        /** hist_weight_31 : R/W; bitpos: [31:24]; default: 1;
+         *  this field configures weight of subwindow 31
+         */
+        uint32_t hist_weight_31:8;
+    };
+    uint32_t val;
+} isp_hist_weight4_reg_t;
+
+/** Type of hist_weight5 register
+ *  histogram sub-window weight register 5
+ */
+typedef union {
+    struct {
+        /** hist_weight_43 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 43
+         */
+        uint32_t hist_weight_43:8;
+        /** hist_weight_42 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 42
+         */
+        uint32_t hist_weight_42:8;
+        /** hist_weight_41 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 41
+         */
+        uint32_t hist_weight_41:8;
+        /** hist_weight_40 : R/W; bitpos: [31:24]; default: 1;
+         *  this field configures weight of subwindow 40
+         */
+        uint32_t hist_weight_40:8;
+    };
+    uint32_t val;
+} isp_hist_weight5_reg_t;
+
+/** Type of hist_weight6 register
+ *  histogram sub-window weight register 6
+ */
+typedef union {
+    struct {
+        /** hist_weight_44 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 44
+         */
+        uint32_t hist_weight_44:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} isp_hist_weight6_reg_t;
+
+/** Type of mem_aux_ctrl_0 register
+ *  mem aux control register 0
+ */
+typedef union {
+    struct {
+        /** header_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures the mem_aux of isp input buffer memory
+         */
+        uint32_t header_mem_aux_ctrl:14;
+        uint32_t reserved_14:2;
+        /** dpc_lut_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896;
+         *  this field represents this field configures the mem_aux of dpc lut memory
+         */
+        uint32_t dpc_lut_mem_aux_ctrl:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_mem_aux_ctrl_0_reg_t;
+
+/** Type of mem_aux_ctrl_1 register
+ *  mem aux control register 1
+ */
+typedef union {
+    struct {
+        /** lsc_lut_r_gr_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures the mem_aux of lsc r gr lut memory
+         */
+        uint32_t lsc_lut_r_gr_mem_aux_ctrl:14;
+        uint32_t reserved_14:2;
+        /** lsc_lut_gb_b_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896;
+         *  this field configures the mem_aux of lsc gb b lut memory
+         */
+        uint32_t lsc_lut_gb_b_mem_aux_ctrl:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_mem_aux_ctrl_1_reg_t;
+
+/** Type of mem_aux_ctrl_2 register
+ *  mem aux control register 2
+ */
+typedef union {
+    struct {
+        /** bf_matrix_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures the mem_aux of bf line buffer memory
+         */
+        uint32_t bf_matrix_mem_aux_ctrl:14;
+        uint32_t reserved_14:2;
+        /** dpc_matrix_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896;
+         *  this field configures the mem_aux of dpc line buffer memory
+         */
+        uint32_t dpc_matrix_mem_aux_ctrl:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_mem_aux_ctrl_2_reg_t;
+
+/** Type of mem_aux_ctrl_3 register
+ *  mem aux control register 3
+ */
+typedef union {
+    struct {
+        /** sharp_matrix_y_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures the mem_aux of sharp y line buffer memory
+         */
+        uint32_t sharp_matrix_y_mem_aux_ctrl:14;
+        uint32_t reserved_14:2;
+        /** demosaic_matrix_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896;
+         *  this field configures the mem_aux of demosaic line buffer memory
+         */
+        uint32_t demosaic_matrix_mem_aux_ctrl:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_mem_aux_ctrl_3_reg_t;
+
+/** Type of mem_aux_ctrl_4 register
+ *  mem aux control register 4
+ */
+typedef union {
+    struct {
+        /** sharp_matrix_uv_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures the mem_aux of sharp uv line buffer memory
+         */
+        uint32_t sharp_matrix_uv_mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} isp_mem_aux_ctrl_4_reg_t;
+
+/** Type of yuv_format register
+ *  yuv format control register
+ */
+typedef union {
+    struct {
+        /** yuv_mode : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709
+         */
+        uint32_t yuv_mode:1;
+        /** yuv_range : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the yuv range. 0: full range, 1: limit range
+         */
+        uint32_t yuv_range:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} isp_yuv_format_reg_t;
+
+/** Type of rdn_eco_low register
+ *  rdn eco all low register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rdn_eco_low
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} isp_rdn_eco_low_reg_t;
+
+/** Type of rdn_eco_high register
+ *  rdn eco all high register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rdn_eco_high
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} isp_rdn_eco_high_reg_t;
+
+/** Type of crop_ctrl register
+ *  isp_crop ctrl register
+ */
+typedef union {
+    struct {
+        /** crop_sft_rst : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear err st
+         */
+        uint32_t crop_sft_rst:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} isp_crop_ctrl_reg_t;
+
+/** Type of crop_y_capture register
+ *  isp_crop row capture range register
+ */
+typedef union {
+    struct {
+        /** crop_y_start : R/W; bitpos: [11:0]; default: 0;
+         *  isp_crop capture row start index
+         */
+        uint32_t crop_y_start:12;
+        /** crop_y_end : R/W; bitpos: [23:12]; default: 0;
+         *  isp_crop capture row end index
+         */
+        uint32_t crop_y_end:12;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_crop_y_capture_reg_t;
+
+/** Type of crop_x_capture register
+ *  isp_crop col capture range register
+ */
+typedef union {
+    struct {
+        /** crop_x_start : R/W; bitpos: [11:0]; default: 0;
+         *  isp_crop capture col start index
+         */
+        uint32_t crop_x_start:12;
+        /** crop_x_end : R/W; bitpos: [23:12]; default: 0;
+         *  isp_crop capture col end index
+         */
+        uint32_t crop_x_end:12;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_crop_x_capture_reg_t;
+
+/** Type of crop_err_st register
+ *  crop error state register
+ */
+typedef union {
+    struct {
+        /** crop_y_mismatch : RO; bitpos: [0]; default: 0;
+         *  Represents isp_corp row end index over image size
+         */
+        uint32_t crop_y_mismatch:1;
+        /** crop_x_mismatch : RO; bitpos: [1]; default: 0;
+         *  Represents isp_corp col end index over image size
+         */
+        uint32_t crop_x_mismatch:1;
+        /** crop_y_end_even : RO; bitpos: [2]; default: 0;
+         *  Represents isp_corp row end index is an even number
+         */
+        uint32_t crop_y_end_even:1;
+        /** crop_x_end_even : RO; bitpos: [3]; default: 0;
+         *  Represents isp_corp col end index is an even number
+         */
+        uint32_t crop_x_end_even:1;
+        /** crop_y_start_odd : RO; bitpos: [4]; default: 0;
+         *  Represents isp_corp row start index is an odd number
+         */
+        uint32_t crop_y_start_odd:1;
+        /** crop_x_start_odd : RO; bitpos: [5]; default: 0;
+         *  Represents isp_corp col start index is an odd number
+         */
+        uint32_t crop_x_start_odd:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} isp_crop_err_st_reg_t;
+
+/** Type of wbg_coef_r register
+ *  white balance red gain register 0
+ */
+typedef union {
+    struct {
+        /** wbg_r : R/W; bitpos: [11:0]; default: 256;
+         *  Configures the white balance red gain
+         */
+        uint32_t wbg_r:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} isp_wbg_coef_r_reg_t;
+
+/** Type of wbg_coef_g register
+ *  white balance green gain register 0
+ */
+typedef union {
+    struct {
+        /** wbg_g : R/W; bitpos: [11:0]; default: 256;
+         *  Configures the white balance green gain
+         */
+        uint32_t wbg_g:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} isp_wbg_coef_g_reg_t;
+
+/** Type of wbg_coef_b register
+ *  white balance blue gain register 0
+ */
+typedef union {
+    struct {
+        /** wbg_b : R/W; bitpos: [11:0]; default: 256;
+         *  Configures the white balance blue gain
+         */
+        uint32_t wbg_b:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} isp_wbg_coef_b_reg_t;
+
+/** Type of color_hue_ctrl register
+ *  color control register
+ */
+typedef union {
+    struct {
+        /** color_hue_h : R/W; bitpos: [0]; default: 0;
+         *  Configures the color hue angle most bit
+         */
+        uint32_t color_hue_h:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} isp_color_hue_ctrl_reg_t;
+
+/** Type of awb_bx register
+ *  awb window register in x-direction
+ */
+typedef union {
+    struct {
+        /** awb_x_bsize : R/W; bitpos: [11:0]; default: 0;
+         *  Configures every block x size, min number is 4
+         */
+        uint32_t awb_x_bsize:12;
+        /** awb_x_start : R/W; bitpos: [23:12]; default: 0;
+         *  Configures first block start x address
+         */
+        uint32_t awb_x_start:12;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_awb_bx_reg_t;
+
+/** Type of awb_by register
+ *  awb window register in y-direction
+ */
+typedef union {
+    struct {
+        /** awb_y_bsize : R/W; bitpos: [11:0]; default: 0;
+         *  Configures every block y size
+         */
+        uint32_t awb_y_bsize:12;
+        /** awb_y_start : R/W; bitpos: [23:12]; default: 0;
+         *  Configures first block start y address
+         */
+        uint32_t awb_y_start:12;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_awb_by_reg_t;
+
+/** Type of state register
+ *  awb window register in y-direction
+ */
+typedef union {
+    struct {
+        /** tail_busy : RO; bitpos: [0]; default: 0;
+         *  Represents isp_tail state
+         */
+        uint32_t tail_busy:1;
+        /** header_busy : RO; bitpos: [1]; default: 0;
+         *  Represents isp_header state
+         */
+        uint32_t header_busy:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} isp_state_reg_t;
+
+/** Type of shadow_reg_ctrl register
+ *  shadow register ctrl register
+ */
+typedef union {
+    struct {
+        /** blc_update : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to update blc configuration register
+         */
+        uint32_t blc_update:1;
+        /** dpc_update : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to update dpc configuration register
+         */
+        uint32_t dpc_update:1;
+        /** bf_update : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to update bf configuration register
+         */
+        uint32_t bf_update:1;
+        /** wbg_update : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to update wbg configuration register
+         */
+        uint32_t wbg_update:1;
+        /** ccm_update : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to update ccm configuration register
+         */
+        uint32_t ccm_update:1;
+        uint32_t reserved_5:1;
+        /** sharp_update : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to update sharp configuration register
+         */
+        uint32_t sharp_update:1;
+        /** color_update : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to update color configuration register
+         */
+        uint32_t color_update:1;
+        uint32_t reserved_8:22;
+        /** shadow_update_sel : R/W; bitpos: [31:30]; default: 1;
+         *  Configures shadow register update type. 0: no shadow register. 1: update every
+         *  vsyn. 2: update only the next vsync after write reg_xxx_update
+         */
+        uint32_t shadow_update_sel:2;
+    };
+    uint32_t val;
+} isp_shadow_reg_ctrl_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of dpc_deadpix_cnt register
+ *  DPC dead-pix number register
+ */
+typedef union {
+    struct {
+        /** dpc_deadpix_cnt : RO; bitpos: [9:0]; default: 0;
+         *  this field represents the dead pixel count
+         */
+        uint32_t dpc_deadpix_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} isp_dpc_deadpix_cnt_reg_t;
+
+/** Type of lut_rdata register
+ *  LUT read data register
+ */
+typedef union {
+    struct {
+        /** lut_rdata : RO; bitpos: [31:0]; default: 0;
+         *  this field represents the read data of lut. read ISP_LUT_RDATA after write
+         *  ISP_LUT_CMD register
+         */
+        uint32_t lut_rdata:32;
+    };
+    uint32_t val;
+} isp_lut_rdata_reg_t;
+
+/** Type of ae_block_mean_0 register
+ *  ae statistic result register 0
+ */
+typedef union {
+    struct {
+        /** ae_b03_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block03 Y mean data
+         */
+        uint32_t ae_b03_mean:8;
+        /** ae_b02_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block02 Y mean data
+         */
+        uint32_t ae_b02_mean:8;
+        /** ae_b01_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block01 Y mean data
+         */
+        uint32_t ae_b01_mean:8;
+        /** ae_b00_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block00 Y mean data
+         */
+        uint32_t ae_b00_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_0_reg_t;
+
+/** Type of ae_block_mean_1 register
+ *  ae statistic result register 1
+ */
+typedef union {
+    struct {
+        /** ae_b12_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block12 Y mean data
+         */
+        uint32_t ae_b12_mean:8;
+        /** ae_b11_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block11 Y mean data
+         */
+        uint32_t ae_b11_mean:8;
+        /** ae_b10_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block10 Y mean data
+         */
+        uint32_t ae_b10_mean:8;
+        /** ae_b04_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block04 Y mean data
+         */
+        uint32_t ae_b04_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_1_reg_t;
+
+/** Type of ae_block_mean_2 register
+ *  ae statistic result register 2
+ */
+typedef union {
+    struct {
+        /** ae_b21_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block21 Y mean data
+         */
+        uint32_t ae_b21_mean:8;
+        /** ae_b20_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block20 Y mean data
+         */
+        uint32_t ae_b20_mean:8;
+        /** ae_b14_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block14 Y mean data
+         */
+        uint32_t ae_b14_mean:8;
+        /** ae_b13_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block13 Y mean data
+         */
+        uint32_t ae_b13_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_2_reg_t;
+
+/** Type of ae_block_mean_3 register
+ *  ae statistic result register 3
+ */
+typedef union {
+    struct {
+        /** ae_b30_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block30 Y mean data
+         */
+        uint32_t ae_b30_mean:8;
+        /** ae_b24_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block24 Y mean data
+         */
+        uint32_t ae_b24_mean:8;
+        /** ae_b23_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block23 Y mean data
+         */
+        uint32_t ae_b23_mean:8;
+        /** ae_b22_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block22 Y mean data
+         */
+        uint32_t ae_b22_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_3_reg_t;
+
+/** Type of ae_block_mean_4 register
+ *  ae statistic result register 4
+ */
+typedef union {
+    struct {
+        /** ae_b34_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block34 Y mean data
+         */
+        uint32_t ae_b34_mean:8;
+        /** ae_b33_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block33 Y mean data
+         */
+        uint32_t ae_b33_mean:8;
+        /** ae_b32_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block32 Y mean data
+         */
+        uint32_t ae_b32_mean:8;
+        /** ae_b31_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block31 Y mean data
+         */
+        uint32_t ae_b31_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_4_reg_t;
+
+/** Type of ae_block_mean_5 register
+ *  ae statistic result register 5
+ */
+typedef union {
+    struct {
+        /** ae_b43_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block43 Y mean data
+         */
+        uint32_t ae_b43_mean:8;
+        /** ae_b42_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block42 Y mean data
+         */
+        uint32_t ae_b42_mean:8;
+        /** ae_b41_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block41 Y mean data
+         */
+        uint32_t ae_b41_mean:8;
+        /** ae_b40_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block40 Y mean data
+         */
+        uint32_t ae_b40_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_5_reg_t;
+
+/** Type of ae_block_mean_6 register
+ *  ae statistic result register 6
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** ae_b44_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block44 Y mean data
+         */
+        uint32_t ae_b44_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_6_reg_t;
+
+/** Type of af_sum_a register
+ *  result of sum of af window a
+ */
+typedef union {
+    struct {
+        /** af_suma : RO; bitpos: [29:0]; default: 0;
+         *  this field represents the result of accumulation of pix grad of focus window a
+         */
+        uint32_t af_suma:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_af_sum_a_reg_t;
+
+/** Type of af_sum_b register
+ *  result of sum of af window b
+ */
+typedef union {
+    struct {
+        /** af_sumb : RO; bitpos: [29:0]; default: 0;
+         *  this field represents the result of accumulation of pix grad of focus window b
+         */
+        uint32_t af_sumb:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_af_sum_b_reg_t;
+
+/** Type of af_sum_c register
+ *  result of sum of af window c
+ */
+typedef union {
+    struct {
+        /** af_sumc : RO; bitpos: [29:0]; default: 0;
+         *  this field represents the result of accumulation of pix grad of focus window c
+         */
+        uint32_t af_sumc:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_af_sum_c_reg_t;
+
+/** Type of af_lum_a register
+ *  result of lum of af window a
+ */
+typedef union {
+    struct {
+        /** af_luma : RO; bitpos: [27:0]; default: 0;
+         *  this field represents the result of accumulation of pix light of focus window a
+         */
+        uint32_t af_luma:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_lum_a_reg_t;
+
+/** Type of af_lum_b register
+ *  result of lum of af window b
+ */
+typedef union {
+    struct {
+        /** af_lumb : RO; bitpos: [27:0]; default: 0;
+         *  this field represents the result of accumulation of pix light of focus window b
+         */
+        uint32_t af_lumb:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_lum_b_reg_t;
+
+/** Type of af_lum_c register
+ *  result of lum of af window c
+ */
+typedef union {
+    struct {
+        /** af_lumc : RO; bitpos: [27:0]; default: 0;
+         *  this field represents the result of accumulation of pix light of focus window c
+         */
+        uint32_t af_lumc:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_lum_c_reg_t;
+
+/** Type of awb0_white_cnt register
+ *  result of awb white point number
+ */
+typedef union {
+    struct {
+        /** awb0_white_cnt : RO; bitpos: [23:0]; default: 0;
+         *  this field configures number of white point detected of algo0
+         */
+        uint32_t awb0_white_cnt:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_awb0_white_cnt_reg_t;
+
+/** Type of awb0_acc_r register
+ *  result of accumulate of r channel of all white points
+ */
+typedef union {
+    struct {
+        /** awb0_acc_r : RO; bitpos: [31:0]; default: 0;
+         *  this field represents accumulate of channel r of all white point of algo0
+         */
+        uint32_t awb0_acc_r:32;
+    };
+    uint32_t val;
+} isp_awb0_acc_r_reg_t;
+
+/** Type of awb0_acc_g register
+ *  result of accumulate of g channel of all white points
+ */
+typedef union {
+    struct {
+        /** awb0_acc_g : RO; bitpos: [31:0]; default: 0;
+         *  this field represents accumulate of channel g of all white point of algo0
+         */
+        uint32_t awb0_acc_g:32;
+    };
+    uint32_t val;
+} isp_awb0_acc_g_reg_t;
+
+/** Type of awb0_acc_b register
+ *  result of accumulate of b channel of all white points
+ */
+typedef union {
+    struct {
+        /** awb0_acc_b : RO; bitpos: [31:0]; default: 0;
+         *  this field represents accumulate of channel b of all white point of algo0
+         */
+        uint32_t awb0_acc_b:32;
+    };
+    uint32_t val;
+} isp_awb0_acc_b_reg_t;
+
+/** Type of blc_mean register
+ *  results of the average of black window
+ */
+typedef union {
+    struct {
+        /** blc_r3_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field represents the average black value of bottom right channel
+         */
+        uint32_t blc_r3_mean:8;
+        /** blc_r2_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field represents the average black value of bottom left channel
+         */
+        uint32_t blc_r2_mean:8;
+        /** blc_r1_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field represents the average black value of top right channel
+         */
+        uint32_t blc_r1_mean:8;
+        /** blc_r0_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field represents the average black value of top left channel
+         */
+        uint32_t blc_r0_mean:8;
+    };
+    uint32_t val;
+} isp_blc_mean_reg_t;
+
+/** Type of hist_bin0 register
+ *  result of histogram bin 0
+ */
+typedef union {
+    struct {
+        /** hist_bin_0 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 0
+         */
+        uint32_t hist_bin_0:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin0_reg_t;
+
+/** Type of hist_bin1 register
+ *  result of histogram bin 1
+ */
+typedef union {
+    struct {
+        /** hist_bin_1 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 1
+         */
+        uint32_t hist_bin_1:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin1_reg_t;
+
+/** Type of hist_bin2 register
+ *  result of histogram bin 2
+ */
+typedef union {
+    struct {
+        /** hist_bin_2 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 2
+         */
+        uint32_t hist_bin_2:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin2_reg_t;
+
+/** Type of hist_bin3 register
+ *  result of histogram bin 3
+ */
+typedef union {
+    struct {
+        /** hist_bin_3 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 3
+         */
+        uint32_t hist_bin_3:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin3_reg_t;
+
+/** Type of hist_bin4 register
+ *  result of histogram bin 4
+ */
+typedef union {
+    struct {
+        /** hist_bin_4 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 4
+         */
+        uint32_t hist_bin_4:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin4_reg_t;
+
+/** Type of hist_bin5 register
+ *  result of histogram bin 5
+ */
+typedef union {
+    struct {
+        /** hist_bin_5 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 5
+         */
+        uint32_t hist_bin_5:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin5_reg_t;
+
+/** Type of hist_bin6 register
+ *  result of histogram bin 6
+ */
+typedef union {
+    struct {
+        /** hist_bin_6 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 6
+         */
+        uint32_t hist_bin_6:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin6_reg_t;
+
+/** Type of hist_bin7 register
+ *  result of histogram bin 7
+ */
+typedef union {
+    struct {
+        /** hist_bin_7 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 7
+         */
+        uint32_t hist_bin_7:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin7_reg_t;
+
+/** Type of hist_bin8 register
+ *  result of histogram bin 8
+ */
+typedef union {
+    struct {
+        /** hist_bin_8 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 8
+         */
+        uint32_t hist_bin_8:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin8_reg_t;
+
+/** Type of hist_bin9 register
+ *  result of histogram bin 9
+ */
+typedef union {
+    struct {
+        /** hist_bin_9 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 9
+         */
+        uint32_t hist_bin_9:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin9_reg_t;
+
+/** Type of hist_bin10 register
+ *  result of histogram bin 10
+ */
+typedef union {
+    struct {
+        /** hist_bin_10 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 10
+         */
+        uint32_t hist_bin_10:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin10_reg_t;
+
+/** Type of hist_bin11 register
+ *  result of histogram bin 11
+ */
+typedef union {
+    struct {
+        /** hist_bin_11 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 11
+         */
+        uint32_t hist_bin_11:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin11_reg_t;
+
+/** Type of hist_bin12 register
+ *  result of histogram bin 12
+ */
+typedef union {
+    struct {
+        /** hist_bin_12 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 12
+         */
+        uint32_t hist_bin_12:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin12_reg_t;
+
+/** Type of hist_bin13 register
+ *  result of histogram bin 13
+ */
+typedef union {
+    struct {
+        /** hist_bin_13 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 13
+         */
+        uint32_t hist_bin_13:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin13_reg_t;
+
+/** Type of hist_bin14 register
+ *  result of histogram bin 14
+ */
+typedef union {
+    struct {
+        /** hist_bin_14 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 14
+         */
+        uint32_t hist_bin_14:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin14_reg_t;
+
+/** Type of hist_bin15 register
+ *  result of histogram bin 15
+ */
+typedef union {
+    struct {
+        /** hist_bin_15 : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin 15
+         */
+        uint32_t hist_bin_15:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_bin15_reg_t;
+
+/** Type of rdn_eco_cs register
+ *  rdn eco cs register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  rdn_eco_en
+         */
+        uint32_t rdn_eco_en:1;
+        /** rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  rdn_eco_result
+         */
+        uint32_t rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} isp_rdn_eco_cs_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  raw interrupt register
+ */
+typedef union {
+    struct {
+        /** isp_data_type_err_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  the raw interrupt status of input data type error. isp only support RGB bayer data
+         *  type, other type will report type_err_int
+         */
+        uint32_t isp_data_type_err_int_raw:1;
+        /** isp_async_fifo_ovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  the raw interrupt status of isp input fifo overflow
+         */
+        uint32_t isp_async_fifo_ovf_int_raw:1;
+        /** isp_buf_full_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  the raw interrupt status of isp input buffer full
+         */
+        uint32_t isp_buf_full_int_raw:1;
+        /** isp_hvnum_setting_err_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  the raw interrupt status of hnum and vnum setting format error
+         */
+        uint32_t isp_hvnum_setting_err_int_raw:1;
+        /** isp_data_type_setting_err_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  the raw interrupt status of setting invalid reg_data_type
+         */
+        uint32_t isp_data_type_setting_err_int_raw:1;
+        /** isp_mipi_hnum_unmatch_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  the raw interrupt status of hnum setting unmatch with mipi input
+         */
+        uint32_t isp_mipi_hnum_unmatch_int_raw:1;
+        /** dpc_check_done_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  the raw interrupt status of dpc check done
+         */
+        uint32_t dpc_check_done_int_raw:1;
+        /** gamma_xcoord_err_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  the raw interrupt status of gamma setting error. it report the sum of the lengths
+         *  represented by reg_gamma_x00~x0F isn't equal to 256
+         */
+        uint32_t gamma_xcoord_err_int_raw:1;
+        /** ae_monitor_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  the raw interrupt status of ae monitor
+         */
+        uint32_t ae_monitor_int_raw:1;
+        /** ae_frame_done_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  the raw interrupt status of ae.
+         */
+        uint32_t ae_frame_done_int_raw:1;
+        /** af_fdone_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  the raw interrupt status of af statistic. when auto_update enable, each frame done
+         *  will send one int pulse when manual_update, each time when write 1 to
+         *  reg_manual_update will send a int pulse when next frame done
+         */
+        uint32_t af_fdone_int_raw:1;
+        /** af_env_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  the raw interrupt status of af monitor. send a int pulse when env_det function
+         *  enabled and environment changes detected
+         */
+        uint32_t af_env_int_raw:1;
+        /** awb_fdone_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  the raw interrupt status of awb. send a int pulse when statistic of one awb frame
+         *  done
+         */
+        uint32_t awb_fdone_int_raw:1;
+        /** hist_fdone_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  the raw interrupt status of histogram. send a int pulse when statistic of one frame
+         *  histogram done
+         */
+        uint32_t hist_fdone_int_raw:1;
+        /** frame_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  the raw interrupt status of isp frame end
+         */
+        uint32_t frame_int_raw:1;
+        /** blc_frame_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  the raw interrupt status of blc frame done
+         */
+        uint32_t blc_frame_int_raw:1;
+        /** lsc_frame_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
+         *  the raw interrupt status of lsc frame done
+         */
+        uint32_t lsc_frame_int_raw:1;
+        /** dpc_frame_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
+         *  the raw interrupt status of dpc frame done
+         */
+        uint32_t dpc_frame_int_raw:1;
+        /** bf_frame_int_raw : R/SS/WTC; bitpos: [18]; default: 0;
+         *  the raw interrupt status of bf frame done
+         */
+        uint32_t bf_frame_int_raw:1;
+        /** demosaic_frame_int_raw : R/SS/WTC; bitpos: [19]; default: 0;
+         *  the raw interrupt status of demosaic frame done
+         */
+        uint32_t demosaic_frame_int_raw:1;
+        /** median_frame_int_raw : R/SS/WTC; bitpos: [20]; default: 0;
+         *  the raw interrupt status of median frame done
+         */
+        uint32_t median_frame_int_raw:1;
+        /** ccm_frame_int_raw : R/SS/WTC; bitpos: [21]; default: 0;
+         *  the raw interrupt status of ccm frame done
+         */
+        uint32_t ccm_frame_int_raw:1;
+        /** gamma_frame_int_raw : R/SS/WTC; bitpos: [22]; default: 0;
+         *  the raw interrupt status of gamma frame done
+         */
+        uint32_t gamma_frame_int_raw:1;
+        /** rgb2yuv_frame_int_raw : R/SS/WTC; bitpos: [23]; default: 0;
+         *  the raw interrupt status of rgb2yuv frame done
+         */
+        uint32_t rgb2yuv_frame_int_raw:1;
+        /** sharp_frame_int_raw : R/SS/WTC; bitpos: [24]; default: 0;
+         *  the raw interrupt status of sharp frame done
+         */
+        uint32_t sharp_frame_int_raw:1;
+        /** color_frame_int_raw : R/SS/WTC; bitpos: [25]; default: 0;
+         *  the raw interrupt status of color frame done
+         */
+        uint32_t color_frame_int_raw:1;
+        /** yuv2rgb_frame_int_raw : R/SS/WTC; bitpos: [26]; default: 0;
+         *  the raw interrupt status of yuv2rgb frame done
+         */
+        uint32_t yuv2rgb_frame_int_raw:1;
+        /** tail_idi_frame_int_raw : R/SS/WTC; bitpos: [27]; default: 0;
+         *  the raw interrupt status of isp_tail idi frame_end
+         */
+        uint32_t tail_idi_frame_int_raw:1;
+        /** header_idi_frame_int_raw : R/SS/WTC; bitpos: [28]; default: 0;
+         *  the raw interrupt status of real input frame end of isp_input
+         */
+        uint32_t header_idi_frame_int_raw:1;
+        /** crop_frame_int_raw : R/SS/WTC; bitpos: [29]; default: 0;
+         *  the raw interrupt status of crop frame done
+         */
+        uint32_t crop_frame_int_raw:1;
+        /** wbg_frame_int_raw : R/SS/WTC; bitpos: [30]; default: 0;
+         *  the raw interrupt status of wbg frame done
+         */
+        uint32_t wbg_frame_int_raw:1;
+        /** crop_err_int_raw : R/SS/WTC; bitpos: [31]; default: 0;
+         *  the raw interrupt status of crop error
+         */
+        uint32_t crop_err_int_raw:1;
+    };
+    uint32_t val;
+} isp_int_raw_reg_t;
+
+/** Type of int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** isp_data_type_err_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of input data type error
+         */
+        uint32_t isp_data_type_err_int_st:1;
+        /** isp_async_fifo_ovf_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of isp input fifo overflow
+         */
+        uint32_t isp_async_fifo_ovf_int_st:1;
+        /** isp_buf_full_int_st : RO; bitpos: [2]; default: 0;
+         *  the masked interrupt status of isp input buffer full
+         */
+        uint32_t isp_buf_full_int_st:1;
+        /** isp_hvnum_setting_err_int_st : RO; bitpos: [3]; default: 0;
+         *  the masked interrupt status of hnum and vnum setting format error
+         */
+        uint32_t isp_hvnum_setting_err_int_st:1;
+        /** isp_data_type_setting_err_int_st : RO; bitpos: [4]; default: 0;
+         *  the masked interrupt status of setting invalid reg_data_type
+         */
+        uint32_t isp_data_type_setting_err_int_st:1;
+        /** isp_mipi_hnum_unmatch_int_st : RO; bitpos: [5]; default: 0;
+         *  the masked interrupt status of hnum setting unmatch with mipi input
+         */
+        uint32_t isp_mipi_hnum_unmatch_int_st:1;
+        /** dpc_check_done_int_st : RO; bitpos: [6]; default: 0;
+         *  the masked interrupt status of dpc check done
+         */
+        uint32_t dpc_check_done_int_st:1;
+        /** gamma_xcoord_err_int_st : RO; bitpos: [7]; default: 0;
+         *  the masked interrupt status of gamma setting error
+         */
+        uint32_t gamma_xcoord_err_int_st:1;
+        /** ae_monitor_int_st : RO; bitpos: [8]; default: 0;
+         *  the masked interrupt status of ae monitor
+         */
+        uint32_t ae_monitor_int_st:1;
+        /** ae_frame_done_int_st : RO; bitpos: [9]; default: 0;
+         *  the masked interrupt status of ae
+         */
+        uint32_t ae_frame_done_int_st:1;
+        /** af_fdone_int_st : RO; bitpos: [10]; default: 0;
+         *  the masked interrupt status of af statistic
+         */
+        uint32_t af_fdone_int_st:1;
+        /** af_env_int_st : RO; bitpos: [11]; default: 0;
+         *  the masked interrupt status of af monitor
+         */
+        uint32_t af_env_int_st:1;
+        /** awb_fdone_int_st : RO; bitpos: [12]; default: 0;
+         *  the masked interrupt status of awb
+         */
+        uint32_t awb_fdone_int_st:1;
+        /** hist_fdone_int_st : RO; bitpos: [13]; default: 0;
+         *  the masked interrupt status of histogram
+         */
+        uint32_t hist_fdone_int_st:1;
+        /** frame_int_st : RO; bitpos: [14]; default: 0;
+         *  the masked interrupt status of isp frame end
+         */
+        uint32_t frame_int_st:1;
+        /** blc_frame_int_st : RO; bitpos: [15]; default: 0;
+         *  the masked interrupt status of blc frame done
+         */
+        uint32_t blc_frame_int_st:1;
+        /** lsc_frame_int_st : RO; bitpos: [16]; default: 0;
+         *  the masked interrupt status of lsc frame done
+         */
+        uint32_t lsc_frame_int_st:1;
+        /** dpc_frame_int_st : RO; bitpos: [17]; default: 0;
+         *  the masked interrupt status of dpc frame done
+         */
+        uint32_t dpc_frame_int_st:1;
+        /** bf_frame_int_st : RO; bitpos: [18]; default: 0;
+         *  the masked interrupt status of bf frame done
+         */
+        uint32_t bf_frame_int_st:1;
+        /** demosaic_frame_int_st : RO; bitpos: [19]; default: 0;
+         *  the masked interrupt status of demosaic frame done
+         */
+        uint32_t demosaic_frame_int_st:1;
+        /** median_frame_int_st : RO; bitpos: [20]; default: 0;
+         *  the masked interrupt status of median frame done
+         */
+        uint32_t median_frame_int_st:1;
+        /** ccm_frame_int_st : RO; bitpos: [21]; default: 0;
+         *  the masked interrupt status of ccm frame done
+         */
+        uint32_t ccm_frame_int_st:1;
+        /** gamma_frame_int_st : RO; bitpos: [22]; default: 0;
+         *  the masked interrupt status of gamma frame done
+         */
+        uint32_t gamma_frame_int_st:1;
+        /** rgb2yuv_frame_int_st : RO; bitpos: [23]; default: 0;
+         *  the masked interrupt status of rgb2yuv frame done
+         */
+        uint32_t rgb2yuv_frame_int_st:1;
+        /** sharp_frame_int_st : RO; bitpos: [24]; default: 0;
+         *  the masked interrupt status of sharp frame done
+         */
+        uint32_t sharp_frame_int_st:1;
+        /** color_frame_int_st : RO; bitpos: [25]; default: 0;
+         *  the masked interrupt status of color frame done
+         */
+        uint32_t color_frame_int_st:1;
+        /** yuv2rgb_frame_int_st : RO; bitpos: [26]; default: 0;
+         *  the masked interrupt status of yuv2rgb frame done
+         */
+        uint32_t yuv2rgb_frame_int_st:1;
+        /** tail_idi_frame_int_st : RO; bitpos: [27]; default: 0;
+         *  the masked interrupt status of isp_tail idi frame_end
+         */
+        uint32_t tail_idi_frame_int_st:1;
+        /** header_idi_frame_int_st : RO; bitpos: [28]; default: 0;
+         *  the masked interrupt status of real input frame end of isp_input
+         */
+        uint32_t header_idi_frame_int_st:1;
+        /** crop_frame_int_st : RO; bitpos: [29]; default: 0;
+         *  the masked interrupt status of crop frame done
+         */
+        uint32_t crop_frame_int_st:1;
+        /** wbg_frame_int_st : RO; bitpos: [30]; default: 0;
+         *  the masked interrupt status of wbg frame done
+         */
+        uint32_t wbg_frame_int_st:1;
+        /** crop_err_int_st : RO; bitpos: [31]; default: 0;
+         *  the masked interrupt status of crop error
+         */
+        uint32_t crop_err_int_st:1;
+    };
+    uint32_t val;
+} isp_int_st_reg_t;
+
+/** Type of int_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** isp_data_type_err_int_ena : R/W; bitpos: [0]; default: 1;
+         *  write 1 to enable input data type error
+         */
+        uint32_t isp_data_type_err_int_ena:1;
+        /** isp_async_fifo_ovf_int_ena : R/W; bitpos: [1]; default: 1;
+         *  write 1 to enable isp input fifo overflow
+         */
+        uint32_t isp_async_fifo_ovf_int_ena:1;
+        /** isp_buf_full_int_ena : R/W; bitpos: [2]; default: 0;
+         *  write 1 to enable isp input buffer full
+         */
+        uint32_t isp_buf_full_int_ena:1;
+        /** isp_hvnum_setting_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  write 1 to enable hnum and vnum setting format error
+         */
+        uint32_t isp_hvnum_setting_err_int_ena:1;
+        /** isp_data_type_setting_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  write 1 to enable setting invalid reg_data_type
+         */
+        uint32_t isp_data_type_setting_err_int_ena:1;
+        /** isp_mipi_hnum_unmatch_int_ena : R/W; bitpos: [5]; default: 0;
+         *  write 1 to enable hnum setting unmatch with mipi input
+         */
+        uint32_t isp_mipi_hnum_unmatch_int_ena:1;
+        /** dpc_check_done_int_ena : R/W; bitpos: [6]; default: 1;
+         *  write 1 to enable dpc check done
+         */
+        uint32_t dpc_check_done_int_ena:1;
+        /** gamma_xcoord_err_int_ena : R/W; bitpos: [7]; default: 1;
+         *  write 1 to enable gamma setting error
+         */
+        uint32_t gamma_xcoord_err_int_ena:1;
+        /** ae_monitor_int_ena : R/W; bitpos: [8]; default: 0;
+         *  write 1 to enable ae monitor
+         */
+        uint32_t ae_monitor_int_ena:1;
+        /** ae_frame_done_int_ena : R/W; bitpos: [9]; default: 0;
+         *  write 1 to enable ae
+         */
+        uint32_t ae_frame_done_int_ena:1;
+        /** af_fdone_int_ena : R/W; bitpos: [10]; default: 0;
+         *  write 1 to enable af statistic
+         */
+        uint32_t af_fdone_int_ena:1;
+        /** af_env_int_ena : R/W; bitpos: [11]; default: 0;
+         *  write 1 to enable af monitor
+         */
+        uint32_t af_env_int_ena:1;
+        /** awb_fdone_int_ena : R/W; bitpos: [12]; default: 0;
+         *  write 1 to enable awb
+         */
+        uint32_t awb_fdone_int_ena:1;
+        /** hist_fdone_int_ena : R/W; bitpos: [13]; default: 0;
+         *  write 1 to enable histogram
+         */
+        uint32_t hist_fdone_int_ena:1;
+        /** frame_int_ena : R/W; bitpos: [14]; default: 0;
+         *  write 1 to enable isp frame end
+         */
+        uint32_t frame_int_ena:1;
+        /** blc_frame_int_ena : R/W; bitpos: [15]; default: 0;
+         *  write 1 to enable blc frame done
+         */
+        uint32_t blc_frame_int_ena:1;
+        /** lsc_frame_int_ena : R/W; bitpos: [16]; default: 0;
+         *  write 1 to enable lsc frame done
+         */
+        uint32_t lsc_frame_int_ena:1;
+        /** dpc_frame_int_ena : R/W; bitpos: [17]; default: 0;
+         *  write 1 to enable dpc frame done
+         */
+        uint32_t dpc_frame_int_ena:1;
+        /** bf_frame_int_ena : R/W; bitpos: [18]; default: 0;
+         *  write 1 to enable bf frame done
+         */
+        uint32_t bf_frame_int_ena:1;
+        /** demosaic_frame_int_ena : R/W; bitpos: [19]; default: 0;
+         *  write 1 to enable demosaic frame done
+         */
+        uint32_t demosaic_frame_int_ena:1;
+        /** median_frame_int_ena : R/W; bitpos: [20]; default: 0;
+         *  write 1 to enable median frame done
+         */
+        uint32_t median_frame_int_ena:1;
+        /** ccm_frame_int_ena : R/W; bitpos: [21]; default: 0;
+         *  write 1 to enable ccm frame done
+         */
+        uint32_t ccm_frame_int_ena:1;
+        /** gamma_frame_int_ena : R/W; bitpos: [22]; default: 0;
+         *  write 1 to enable gamma frame done
+         */
+        uint32_t gamma_frame_int_ena:1;
+        /** rgb2yuv_frame_int_ena : R/W; bitpos: [23]; default: 0;
+         *  write 1 to enable rgb2yuv frame done
+         */
+        uint32_t rgb2yuv_frame_int_ena:1;
+        /** sharp_frame_int_ena : R/W; bitpos: [24]; default: 0;
+         *  write 1 to enable sharp frame done
+         */
+        uint32_t sharp_frame_int_ena:1;
+        /** color_frame_int_ena : R/W; bitpos: [25]; default: 0;
+         *  write 1 to enable color frame done
+         */
+        uint32_t color_frame_int_ena:1;
+        /** yuv2rgb_frame_int_ena : R/W; bitpos: [26]; default: 0;
+         *  write 1 to enable yuv2rgb frame done
+         */
+        uint32_t yuv2rgb_frame_int_ena:1;
+        /** tail_idi_frame_int_ena : R/W; bitpos: [27]; default: 0;
+         *  write 1 to enable isp_tail idi frame_end
+         */
+        uint32_t tail_idi_frame_int_ena:1;
+        /** header_idi_frame_int_ena : R/W; bitpos: [28]; default: 0;
+         *  write 1 to enable real input frame end of isp_input
+         */
+        uint32_t header_idi_frame_int_ena:1;
+        /** crop_frame_int_ena : R/W; bitpos: [29]; default: 0;
+         *  write 1 to enable crop frame done
+         */
+        uint32_t crop_frame_int_ena:1;
+        /** wbg_frame_int_ena : R/W; bitpos: [30]; default: 0;
+         *  write 1 to enable wbg frame done
+         */
+        uint32_t wbg_frame_int_ena:1;
+        /** crop_err_int_ena : R/W; bitpos: [31]; default: 0;
+         *  write 1 to enable crop error
+         */
+        uint32_t crop_err_int_ena:1;
+    };
+    uint32_t val;
+} isp_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** isp_data_type_err_int_clr : WT; bitpos: [0]; default: 0;
+         *  write 1 to clear input data type error
+         */
+        uint32_t isp_data_type_err_int_clr:1;
+        /** isp_async_fifo_ovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  write 1 to clear isp input fifo overflow
+         */
+        uint32_t isp_async_fifo_ovf_int_clr:1;
+        /** isp_buf_full_int_clr : WT; bitpos: [2]; default: 0;
+         *  write 1 to clear isp input buffer full
+         */
+        uint32_t isp_buf_full_int_clr:1;
+        /** isp_hvnum_setting_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  write 1 to clear hnum and vnum setting format error
+         */
+        uint32_t isp_hvnum_setting_err_int_clr:1;
+        /** isp_data_type_setting_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  write 1 to clear setting invalid reg_data_type
+         */
+        uint32_t isp_data_type_setting_err_int_clr:1;
+        /** isp_mipi_hnum_unmatch_int_clr : WT; bitpos: [5]; default: 0;
+         *  write 1 to clear hnum setting unmatch with mipi input
+         */
+        uint32_t isp_mipi_hnum_unmatch_int_clr:1;
+        /** dpc_check_done_int_clr : WT; bitpos: [6]; default: 0;
+         *  write 1 to clear dpc check done
+         */
+        uint32_t dpc_check_done_int_clr:1;
+        /** gamma_xcoord_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  write 1 to clear gamma setting error
+         */
+        uint32_t gamma_xcoord_err_int_clr:1;
+        /** ae_monitor_int_clr : WT; bitpos: [8]; default: 0;
+         *  write 1 to clear ae monitor
+         */
+        uint32_t ae_monitor_int_clr:1;
+        /** ae_frame_done_int_clr : WT; bitpos: [9]; default: 0;
+         *  write 1 to clear ae
+         */
+        uint32_t ae_frame_done_int_clr:1;
+        /** af_fdone_int_clr : WT; bitpos: [10]; default: 0;
+         *  write 1 to clear af statistic
+         */
+        uint32_t af_fdone_int_clr:1;
+        /** af_env_int_clr : WT; bitpos: [11]; default: 0;
+         *  write 1 to clear af monitor
+         */
+        uint32_t af_env_int_clr:1;
+        /** awb_fdone_int_clr : WT; bitpos: [12]; default: 0;
+         *  write 1 to clear awb
+         */
+        uint32_t awb_fdone_int_clr:1;
+        /** hist_fdone_int_clr : WT; bitpos: [13]; default: 0;
+         *  write 1 to clear histogram
+         */
+        uint32_t hist_fdone_int_clr:1;
+        /** frame_int_clr : WT; bitpos: [14]; default: 0;
+         *  write 1 to clear isp frame end
+         */
+        uint32_t frame_int_clr:1;
+        /** blc_frame_int_clr : WT; bitpos: [15]; default: 0;
+         *  write 1 to clear blc frame done
+         */
+        uint32_t blc_frame_int_clr:1;
+        /** lsc_frame_int_clr : WT; bitpos: [16]; default: 0;
+         *  write 1 to clear lsc frame done
+         */
+        uint32_t lsc_frame_int_clr:1;
+        /** dpc_frame_int_clr : WT; bitpos: [17]; default: 0;
+         *  write 1 to clear dpc frame done
+         */
+        uint32_t dpc_frame_int_clr:1;
+        /** bf_frame_int_clr : WT; bitpos: [18]; default: 0;
+         *  write 1 to clear bf frame done
+         */
+        uint32_t bf_frame_int_clr:1;
+        /** demosaic_frame_int_clr : WT; bitpos: [19]; default: 0;
+         *  write 1 to clear demosaic frame done
+         */
+        uint32_t demosaic_frame_int_clr:1;
+        /** median_frame_int_clr : WT; bitpos: [20]; default: 0;
+         *  write 1 to clear median frame done
+         */
+        uint32_t median_frame_int_clr:1;
+        /** ccm_frame_int_clr : WT; bitpos: [21]; default: 0;
+         *  write 1 to clear ccm frame done
+         */
+        uint32_t ccm_frame_int_clr:1;
+        /** gamma_frame_int_clr : WT; bitpos: [22]; default: 0;
+         *  write 1 to clear gamma frame done
+         */
+        uint32_t gamma_frame_int_clr:1;
+        /** rgb2yuv_frame_int_clr : WT; bitpos: [23]; default: 0;
+         *  write 1 to clear rgb2yuv frame done
+         */
+        uint32_t rgb2yuv_frame_int_clr:1;
+        /** sharp_frame_int_clr : WT; bitpos: [24]; default: 0;
+         *  write 1 to clear sharp frame done
+         */
+        uint32_t sharp_frame_int_clr:1;
+        /** color_frame_int_clr : WT; bitpos: [25]; default: 0;
+         *  write 1 to clear color frame done
+         */
+        uint32_t color_frame_int_clr:1;
+        /** yuv2rgb_frame_int_clr : WT; bitpos: [26]; default: 0;
+         *  write 1 to clear yuv2rgb frame done
+         */
+        uint32_t yuv2rgb_frame_int_clr:1;
+        /** tail_idi_frame_int_clr : WT; bitpos: [27]; default: 0;
+         *  write 1 to clear isp_tail idi frame_end
+         */
+        uint32_t tail_idi_frame_int_clr:1;
+        /** header_idi_frame_int_clr : WT; bitpos: [28]; default: 0;
+         *  write 1 to clear real input frame end of isp_input
+         */
+        uint32_t header_idi_frame_int_clr:1;
+        /** crop_frame_int_clr : WT; bitpos: [29]; default: 0;
+         *  write 1 to clear crop frame done
+         */
+        uint32_t crop_frame_int_clr:1;
+        /** wbg_frame_int_clr : WT; bitpos: [30]; default: 0;
+         *  write 1 to clear wbg frame done
+         */
+        uint32_t wbg_frame_int_clr:1;
+        /** crop_err_int_clr : WT; bitpos: [31]; default: 0;
+         *  write 1 to clear crop error
+         */
+        uint32_t crop_err_int_clr:1;
+    };
+    uint32_t val;
+} isp_int_clr_reg_t;
+
+
+typedef struct {
+    volatile isp_ver_date_reg_t ver_date;
+    volatile isp_clk_en_reg_t clk_en;
+    volatile isp_cntl_reg_t cntl;
+    volatile isp_hsync_cnt_reg_t hsync_cnt;
+    volatile isp_frame_cfg_reg_t frame_cfg;
+    volatile isp_ccm_coef0_reg_t ccm_coef0;
+    volatile isp_ccm_coef1_reg_t ccm_coef1;
+    volatile isp_ccm_coef3_reg_t ccm_coef3;
+    volatile isp_ccm_coef4_reg_t ccm_coef4;
+    volatile isp_ccm_coef5_reg_t ccm_coef5;
+    volatile isp_bf_matrix_ctrl_reg_t bf_matrix_ctrl;
+    volatile isp_bf_sigma_reg_t bf_sigma;
+    volatile isp_bf_gau0_reg_t bf_gau0;
+    volatile isp_bf_gau1_reg_t bf_gau1;
+    volatile isp_dpc_ctrl_reg_t dpc_ctrl;
+    volatile isp_dpc_conf_reg_t dpc_conf;
+    volatile isp_dpc_matrix_ctrl_reg_t dpc_matrix_ctrl;
+    volatile isp_dpc_deadpix_cnt_reg_t dpc_deadpix_cnt;
+    volatile isp_lut_cmd_reg_t lut_cmd;
+    volatile isp_lut_wdata_reg_t lut_wdata;
+    volatile isp_lut_rdata_reg_t lut_rdata;
+    volatile isp_lsc_tablesize_reg_t lsc_tablesize;
+    volatile isp_demosaic_matrix_ctrl_reg_t demosaic_matrix_ctrl;
+    volatile isp_demosaic_grad_ratio_reg_t demosaic_grad_ratio;
+    volatile isp_median_matrix_ctrl_reg_t median_matrix_ctrl;
+    volatile isp_int_raw_reg_t int_raw;
+    volatile isp_int_st_reg_t int_st;
+    volatile isp_int_ena_reg_t int_ena;
+    volatile isp_int_clr_reg_t int_clr;
+    volatile isp_gamma_ctrl_reg_t gamma_ctrl;
+    volatile isp_gamma_ry1_reg_t gamma_ry1;
+    volatile isp_gamma_ry2_reg_t gamma_ry2;
+    volatile isp_gamma_ry3_reg_t gamma_ry3;
+    volatile isp_gamma_ry4_reg_t gamma_ry4;
+    volatile isp_gamma_gy1_reg_t gamma_gy1;
+    volatile isp_gamma_gy2_reg_t gamma_gy2;
+    volatile isp_gamma_gy3_reg_t gamma_gy3;
+    volatile isp_gamma_gy4_reg_t gamma_gy4;
+    volatile isp_gamma_by1_reg_t gamma_by1;
+    volatile isp_gamma_by2_reg_t gamma_by2;
+    volatile isp_gamma_by3_reg_t gamma_by3;
+    volatile isp_gamma_by4_reg_t gamma_by4;
+    volatile isp_gamma_rx1_reg_t gamma_rx1;
+    volatile isp_gamma_rx2_reg_t gamma_rx2;
+    volatile isp_gamma_gx1_reg_t gamma_gx1;
+    volatile isp_gamma_gx2_reg_t gamma_gx2;
+    volatile isp_gamma_bx1_reg_t gamma_bx1;
+    volatile isp_gamma_bx2_reg_t gamma_bx2;
+    volatile isp_ae_ctrl_reg_t ae_ctrl;
+    volatile isp_ae_monitor_reg_t ae_monitor;
+    volatile isp_ae_bx_reg_t ae_bx;
+    volatile isp_ae_by_reg_t ae_by;
+    volatile isp_ae_winpixnum_reg_t ae_winpixnum;
+    volatile isp_ae_win_reciprocal_reg_t ae_win_reciprocal;
+    volatile isp_ae_block_mean_0_reg_t ae_block_mean_0;
+    volatile isp_ae_block_mean_1_reg_t ae_block_mean_1;
+    volatile isp_ae_block_mean_2_reg_t ae_block_mean_2;
+    volatile isp_ae_block_mean_3_reg_t ae_block_mean_3;
+    volatile isp_ae_block_mean_4_reg_t ae_block_mean_4;
+    volatile isp_ae_block_mean_5_reg_t ae_block_mean_5;
+    volatile isp_ae_block_mean_6_reg_t ae_block_mean_6;
+    volatile isp_sharp_ctrl0_reg_t sharp_ctrl0;
+    volatile isp_sharp_filter0_reg_t sharp_filter0;
+    volatile isp_sharp_filter1_reg_t sharp_filter1;
+    volatile isp_sharp_filter2_reg_t sharp_filter2;
+    volatile isp_sharp_matrix_ctrl_reg_t sharp_matrix_ctrl;
+    volatile isp_sharp_ctrl1_reg_t sharp_ctrl1;
+    volatile isp_dma_cntl_reg_t dma_cntl;
+    volatile isp_dma_raw_data_reg_t dma_raw_data;
+    volatile isp_cam_cntl_reg_t cam_cntl;
+    volatile isp_cam_conf_reg_t cam_conf;
+    volatile isp_af_ctrl0_reg_t af_ctrl0;
+    volatile isp_af_ctrl1_reg_t af_ctrl1;
+    volatile isp_af_gen_th_ctrl_reg_t af_gen_th_ctrl;
+    volatile isp_af_env_user_th_sum_reg_t af_env_user_th_sum;
+    volatile isp_af_env_user_th_lum_reg_t af_env_user_th_lum;
+    volatile isp_af_threshold_reg_t af_threshold;
+    volatile isp_af_hscale_a_reg_t af_hscale_a;
+    volatile isp_af_vscale_a_reg_t af_vscale_a;
+    volatile isp_af_hscale_b_reg_t af_hscale_b;
+    volatile isp_af_vscale_b_reg_t af_vscale_b;
+    volatile isp_af_hscale_c_reg_t af_hscale_c;
+    volatile isp_af_vscale_c_reg_t af_vscale_c;
+    volatile isp_af_sum_a_reg_t af_sum_a;
+    volatile isp_af_sum_b_reg_t af_sum_b;
+    volatile isp_af_sum_c_reg_t af_sum_c;
+    volatile isp_af_lum_a_reg_t af_lum_a;
+    volatile isp_af_lum_b_reg_t af_lum_b;
+    volatile isp_af_lum_c_reg_t af_lum_c;
+    volatile isp_awb_mode_reg_t awb_mode;
+    volatile isp_awb_hscale_reg_t awb_hscale;
+    volatile isp_awb_vscale_reg_t awb_vscale;
+    volatile isp_awb_th_lum_reg_t awb_th_lum;
+    volatile isp_awb_th_rg_reg_t awb_th_rg;
+    volatile isp_awb_th_bg_reg_t awb_th_bg;
+    volatile isp_awb0_white_cnt_reg_t awb0_white_cnt;
+    volatile isp_awb0_acc_r_reg_t awb0_acc_r;
+    volatile isp_awb0_acc_g_reg_t awb0_acc_g;
+    volatile isp_awb0_acc_b_reg_t awb0_acc_b;
+    volatile isp_color_ctrl_reg_t color_ctrl;
+    volatile isp_blc_value_reg_t blc_value;
+    volatile isp_blc_ctrl0_reg_t blc_ctrl0;
+    volatile isp_blc_ctrl1_reg_t blc_ctrl1;
+    volatile isp_blc_ctrl2_reg_t blc_ctrl2;
+    volatile isp_blc_mean_reg_t blc_mean;
+    volatile isp_hist_mode_reg_t hist_mode;
+    volatile isp_hist_coeff_reg_t hist_coeff;
+    volatile isp_hist_offs_reg_t hist_offs;
+    volatile isp_hist_size_reg_t hist_size;
+    volatile isp_hist_seg0_reg_t hist_seg0;
+    volatile isp_hist_seg1_reg_t hist_seg1;
+    volatile isp_hist_seg2_reg_t hist_seg2;
+    volatile isp_hist_seg3_reg_t hist_seg3;
+    volatile isp_hist_weight0_reg_t hist_weight0;
+    volatile isp_hist_weight1_reg_t hist_weight1;
+    volatile isp_hist_weight2_reg_t hist_weight2;
+    volatile isp_hist_weight3_reg_t hist_weight3;
+    volatile isp_hist_weight4_reg_t hist_weight4;
+    volatile isp_hist_weight5_reg_t hist_weight5;
+    volatile isp_hist_weight6_reg_t hist_weight6;
+    volatile isp_hist_bin0_reg_t hist_bin0;
+    volatile isp_hist_bin1_reg_t hist_bin1;
+    volatile isp_hist_bin2_reg_t hist_bin2;
+    volatile isp_hist_bin3_reg_t hist_bin3;
+    volatile isp_hist_bin4_reg_t hist_bin4;
+    volatile isp_hist_bin5_reg_t hist_bin5;
+    volatile isp_hist_bin6_reg_t hist_bin6;
+    volatile isp_hist_bin7_reg_t hist_bin7;
+    volatile isp_hist_bin8_reg_t hist_bin8;
+    volatile isp_hist_bin9_reg_t hist_bin9;
+    volatile isp_hist_bin10_reg_t hist_bin10;
+    volatile isp_hist_bin11_reg_t hist_bin11;
+    volatile isp_hist_bin12_reg_t hist_bin12;
+    volatile isp_hist_bin13_reg_t hist_bin13;
+    volatile isp_hist_bin14_reg_t hist_bin14;
+    volatile isp_hist_bin15_reg_t hist_bin15;
+    volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0;
+    volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1;
+    volatile isp_mem_aux_ctrl_2_reg_t mem_aux_ctrl_2;
+    volatile isp_mem_aux_ctrl_3_reg_t mem_aux_ctrl_3;
+    volatile isp_mem_aux_ctrl_4_reg_t mem_aux_ctrl_4;
+    volatile isp_yuv_format_reg_t yuv_format;
+    volatile isp_rdn_eco_cs_reg_t rdn_eco_cs;
+    volatile isp_rdn_eco_low_reg_t rdn_eco_low;
+    volatile isp_rdn_eco_high_reg_t rdn_eco_high;
+    volatile isp_crop_ctrl_reg_t crop_ctrl;
+    volatile isp_crop_y_capture_reg_t crop_y_capture;
+    volatile isp_crop_x_capture_reg_t crop_x_capture;
+    volatile isp_crop_err_st_reg_t crop_err_st;
+    volatile isp_wbg_coef_r_reg_t wbg_coef_r;
+    volatile isp_wbg_coef_g_reg_t wbg_coef_g;
+    volatile isp_wbg_coef_b_reg_t wbg_coef_b;
+    volatile isp_color_hue_ctrl_reg_t color_hue_ctrl;
+    volatile isp_awb_bx_reg_t awb_bx;
+    volatile isp_awb_by_reg_t awb_by;
+    volatile isp_state_reg_t state;
+    volatile isp_shadow_reg_ctrl_reg_t shadow_reg_ctrl;
+} isp_dev_t;
+
+extern isp_dev_t ISP;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(isp_dev_t) == 0x274, "Invalid size of isp_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/isp_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/isp_reg.h
new file mode 100644
index 0000000000..f4d25d40e4
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/isp_reg.h
@@ -0,0 +1,4999 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ISP_VER_DATE_REG register
+ *  version control register
+ */
+#define ISP_VER_DATE_REG (DR_REG_ISP_BASE + 0x0)
+/** ISP_VER_DATA : R/W; bitpos: [31:0]; default: 539035144;
+ *  csv version
+ */
+#define ISP_VER_DATA    0xFFFFFFFFU
+#define ISP_VER_DATA_M  (ISP_VER_DATA_V << ISP_VER_DATA_S)
+#define ISP_VER_DATA_V  0xFFFFFFFFU
+#define ISP_VER_DATA_S  0
+
+/** ISP_CLK_EN_REG register
+ *  isp clk control register
+ */
+#define ISP_CLK_EN_REG (DR_REG_ISP_BASE + 0x4)
+/** ISP_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures the clk force on of isp reg. 0: disable, 1: enable
+ */
+#define ISP_CLK_EN    (BIT(0))
+#define ISP_CLK_EN_M  (ISP_CLK_EN_V << ISP_CLK_EN_S)
+#define ISP_CLK_EN_V  0x00000001U
+#define ISP_CLK_EN_S  0
+/** ISP_CLK_BLC_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  this bit configures the clk force on of blc. 0: disable, 1: enable
+ */
+#define ISP_CLK_BLC_FORCE_ON    (BIT(1))
+#define ISP_CLK_BLC_FORCE_ON_M  (ISP_CLK_BLC_FORCE_ON_V << ISP_CLK_BLC_FORCE_ON_S)
+#define ISP_CLK_BLC_FORCE_ON_V  0x00000001U
+#define ISP_CLK_BLC_FORCE_ON_S  1
+/** ISP_CLK_DPC_FORCE_ON : R/W; bitpos: [2]; default: 0;
+ *  this bit configures the clk force on of dpc. 0: disable, 1: enable
+ */
+#define ISP_CLK_DPC_FORCE_ON    (BIT(2))
+#define ISP_CLK_DPC_FORCE_ON_M  (ISP_CLK_DPC_FORCE_ON_V << ISP_CLK_DPC_FORCE_ON_S)
+#define ISP_CLK_DPC_FORCE_ON_V  0x00000001U
+#define ISP_CLK_DPC_FORCE_ON_S  2
+/** ISP_CLK_BF_FORCE_ON : R/W; bitpos: [3]; default: 0;
+ *  this bit configures the clk force on of bf. 0: disable, 1: enable
+ */
+#define ISP_CLK_BF_FORCE_ON    (BIT(3))
+#define ISP_CLK_BF_FORCE_ON_M  (ISP_CLK_BF_FORCE_ON_V << ISP_CLK_BF_FORCE_ON_S)
+#define ISP_CLK_BF_FORCE_ON_V  0x00000001U
+#define ISP_CLK_BF_FORCE_ON_S  3
+/** ISP_CLK_LSC_FORCE_ON : R/W; bitpos: [4]; default: 0;
+ *  this bit configures the clk force on of lsc. 0: disable, 1: enable
+ */
+#define ISP_CLK_LSC_FORCE_ON    (BIT(4))
+#define ISP_CLK_LSC_FORCE_ON_M  (ISP_CLK_LSC_FORCE_ON_V << ISP_CLK_LSC_FORCE_ON_S)
+#define ISP_CLK_LSC_FORCE_ON_V  0x00000001U
+#define ISP_CLK_LSC_FORCE_ON_S  4
+/** ISP_CLK_DEMOSAIC_FORCE_ON : R/W; bitpos: [5]; default: 0;
+ *  this bit configures the clk force on of demosaic. 0: disable, 1: enable
+ */
+#define ISP_CLK_DEMOSAIC_FORCE_ON    (BIT(5))
+#define ISP_CLK_DEMOSAIC_FORCE_ON_M  (ISP_CLK_DEMOSAIC_FORCE_ON_V << ISP_CLK_DEMOSAIC_FORCE_ON_S)
+#define ISP_CLK_DEMOSAIC_FORCE_ON_V  0x00000001U
+#define ISP_CLK_DEMOSAIC_FORCE_ON_S  5
+/** ISP_CLK_MEDIAN_FORCE_ON : R/W; bitpos: [6]; default: 0;
+ *  this bit configures the clk force on of median. 0: disable, 1: enable
+ */
+#define ISP_CLK_MEDIAN_FORCE_ON    (BIT(6))
+#define ISP_CLK_MEDIAN_FORCE_ON_M  (ISP_CLK_MEDIAN_FORCE_ON_V << ISP_CLK_MEDIAN_FORCE_ON_S)
+#define ISP_CLK_MEDIAN_FORCE_ON_V  0x00000001U
+#define ISP_CLK_MEDIAN_FORCE_ON_S  6
+/** ISP_CLK_CCM_FORCE_ON : R/W; bitpos: [7]; default: 0;
+ *  this bit configures the clk force on of ccm. 0: disable, 1: enable
+ */
+#define ISP_CLK_CCM_FORCE_ON    (BIT(7))
+#define ISP_CLK_CCM_FORCE_ON_M  (ISP_CLK_CCM_FORCE_ON_V << ISP_CLK_CCM_FORCE_ON_S)
+#define ISP_CLK_CCM_FORCE_ON_V  0x00000001U
+#define ISP_CLK_CCM_FORCE_ON_S  7
+/** ISP_CLK_GAMMA_FORCE_ON : R/W; bitpos: [8]; default: 0;
+ *  this bit configures the clk force on of gamma. 0: disable, 1: enable
+ */
+#define ISP_CLK_GAMMA_FORCE_ON    (BIT(8))
+#define ISP_CLK_GAMMA_FORCE_ON_M  (ISP_CLK_GAMMA_FORCE_ON_V << ISP_CLK_GAMMA_FORCE_ON_S)
+#define ISP_CLK_GAMMA_FORCE_ON_V  0x00000001U
+#define ISP_CLK_GAMMA_FORCE_ON_S  8
+/** ISP_CLK_RGB2YUV_FORCE_ON : R/W; bitpos: [9]; default: 0;
+ *  this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable
+ */
+#define ISP_CLK_RGB2YUV_FORCE_ON    (BIT(9))
+#define ISP_CLK_RGB2YUV_FORCE_ON_M  (ISP_CLK_RGB2YUV_FORCE_ON_V << ISP_CLK_RGB2YUV_FORCE_ON_S)
+#define ISP_CLK_RGB2YUV_FORCE_ON_V  0x00000001U
+#define ISP_CLK_RGB2YUV_FORCE_ON_S  9
+/** ISP_CLK_SHARP_FORCE_ON : R/W; bitpos: [10]; default: 0;
+ *  this bit configures the clk force on of sharp. 0: disable, 1: enable
+ */
+#define ISP_CLK_SHARP_FORCE_ON    (BIT(10))
+#define ISP_CLK_SHARP_FORCE_ON_M  (ISP_CLK_SHARP_FORCE_ON_V << ISP_CLK_SHARP_FORCE_ON_S)
+#define ISP_CLK_SHARP_FORCE_ON_V  0x00000001U
+#define ISP_CLK_SHARP_FORCE_ON_S  10
+/** ISP_CLK_COLOR_FORCE_ON : R/W; bitpos: [11]; default: 0;
+ *  this bit configures the clk force on of color. 0: disable, 1: enable
+ */
+#define ISP_CLK_COLOR_FORCE_ON    (BIT(11))
+#define ISP_CLK_COLOR_FORCE_ON_M  (ISP_CLK_COLOR_FORCE_ON_V << ISP_CLK_COLOR_FORCE_ON_S)
+#define ISP_CLK_COLOR_FORCE_ON_V  0x00000001U
+#define ISP_CLK_COLOR_FORCE_ON_S  11
+/** ISP_CLK_YUV2RGB_FORCE_ON : R/W; bitpos: [12]; default: 0;
+ *  this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable
+ */
+#define ISP_CLK_YUV2RGB_FORCE_ON    (BIT(12))
+#define ISP_CLK_YUV2RGB_FORCE_ON_M  (ISP_CLK_YUV2RGB_FORCE_ON_V << ISP_CLK_YUV2RGB_FORCE_ON_S)
+#define ISP_CLK_YUV2RGB_FORCE_ON_V  0x00000001U
+#define ISP_CLK_YUV2RGB_FORCE_ON_S  12
+/** ISP_CLK_AE_FORCE_ON : R/W; bitpos: [13]; default: 0;
+ *  this bit configures the clk force on of ae. 0: disable, 1: enable
+ */
+#define ISP_CLK_AE_FORCE_ON    (BIT(13))
+#define ISP_CLK_AE_FORCE_ON_M  (ISP_CLK_AE_FORCE_ON_V << ISP_CLK_AE_FORCE_ON_S)
+#define ISP_CLK_AE_FORCE_ON_V  0x00000001U
+#define ISP_CLK_AE_FORCE_ON_S  13
+/** ISP_CLK_AF_FORCE_ON : R/W; bitpos: [14]; default: 0;
+ *  this bit configures the clk force on of af. 0: disable, 1: enable
+ */
+#define ISP_CLK_AF_FORCE_ON    (BIT(14))
+#define ISP_CLK_AF_FORCE_ON_M  (ISP_CLK_AF_FORCE_ON_V << ISP_CLK_AF_FORCE_ON_S)
+#define ISP_CLK_AF_FORCE_ON_V  0x00000001U
+#define ISP_CLK_AF_FORCE_ON_S  14
+/** ISP_CLK_AWB_FORCE_ON : R/W; bitpos: [15]; default: 0;
+ *  this bit configures the clk force on of awb. 0: disable, 1: enable
+ */
+#define ISP_CLK_AWB_FORCE_ON    (BIT(15))
+#define ISP_CLK_AWB_FORCE_ON_M  (ISP_CLK_AWB_FORCE_ON_V << ISP_CLK_AWB_FORCE_ON_S)
+#define ISP_CLK_AWB_FORCE_ON_V  0x00000001U
+#define ISP_CLK_AWB_FORCE_ON_S  15
+/** ISP_CLK_HIST_FORCE_ON : R/W; bitpos: [16]; default: 0;
+ *  this bit configures the clk force on of hist. 0: disable, 1: enable
+ */
+#define ISP_CLK_HIST_FORCE_ON    (BIT(16))
+#define ISP_CLK_HIST_FORCE_ON_M  (ISP_CLK_HIST_FORCE_ON_V << ISP_CLK_HIST_FORCE_ON_S)
+#define ISP_CLK_HIST_FORCE_ON_V  0x00000001U
+#define ISP_CLK_HIST_FORCE_ON_S  16
+/** ISP_CLK_MIPI_IDI_FORCE_ON : R/W; bitpos: [17]; default: 0;
+ *  this bit configures the clk force on of mipi idi input. 0: disable, 1: enable
+ */
+#define ISP_CLK_MIPI_IDI_FORCE_ON    (BIT(17))
+#define ISP_CLK_MIPI_IDI_FORCE_ON_M  (ISP_CLK_MIPI_IDI_FORCE_ON_V << ISP_CLK_MIPI_IDI_FORCE_ON_S)
+#define ISP_CLK_MIPI_IDI_FORCE_ON_V  0x00000001U
+#define ISP_CLK_MIPI_IDI_FORCE_ON_S  17
+/** ISP_ISP_MEM_CLK_FORCE_ON : R/W; bitpos: [18]; default: 0;
+ *  this bit configures the clk force on of all isp memory. 0: disable, 1: enable
+ */
+#define ISP_ISP_MEM_CLK_FORCE_ON    (BIT(18))
+#define ISP_ISP_MEM_CLK_FORCE_ON_M  (ISP_ISP_MEM_CLK_FORCE_ON_V << ISP_ISP_MEM_CLK_FORCE_ON_S)
+#define ISP_ISP_MEM_CLK_FORCE_ON_V  0x00000001U
+#define ISP_ISP_MEM_CLK_FORCE_ON_S  18
+/** ISP_CLK_CROP_FORCE_ON : R/W; bitpos: [19]; default: 0;
+ *  this bit configures the clk force on of crop. 0: disable, 1: enable
+ */
+#define ISP_CLK_CROP_FORCE_ON    (BIT(19))
+#define ISP_CLK_CROP_FORCE_ON_M  (ISP_CLK_CROP_FORCE_ON_V << ISP_CLK_CROP_FORCE_ON_S)
+#define ISP_CLK_CROP_FORCE_ON_V  0x00000001U
+#define ISP_CLK_CROP_FORCE_ON_S  19
+/** ISP_CLK_WBG_FORCE_ON : R/W; bitpos: [20]; default: 0;
+ *  this bit configures the clk force on of wbg. 0: disable, 1: enable
+ */
+#define ISP_CLK_WBG_FORCE_ON    (BIT(20))
+#define ISP_CLK_WBG_FORCE_ON_M  (ISP_CLK_WBG_FORCE_ON_V << ISP_CLK_WBG_FORCE_ON_S)
+#define ISP_CLK_WBG_FORCE_ON_V  0x00000001U
+#define ISP_CLK_WBG_FORCE_ON_S  20
+
+/** ISP_CNTL_REG register
+ *  isp module enable control register
+ */
+#define ISP_CNTL_REG (DR_REG_ISP_BASE + 0x8)
+/** ISP_MIPI_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures mipi input data enable. 0: disable, 1: enable
+ */
+#define ISP_MIPI_DATA_EN    (BIT(0))
+#define ISP_MIPI_DATA_EN_M  (ISP_MIPI_DATA_EN_V << ISP_MIPI_DATA_EN_S)
+#define ISP_MIPI_DATA_EN_V  0x00000001U
+#define ISP_MIPI_DATA_EN_S  0
+/** ISP_ISP_EN : R/W; bitpos: [1]; default: 1;
+ *  this bit configures isp global enable. 0: disable, 1: enable
+ */
+#define ISP_ISP_EN    (BIT(1))
+#define ISP_ISP_EN_M  (ISP_ISP_EN_V << ISP_ISP_EN_S)
+#define ISP_ISP_EN_V  0x00000001U
+#define ISP_ISP_EN_S  1
+/** ISP_BLC_EN : R/W; bitpos: [2]; default: 0;
+ *  this bit configures blc enable. 0: disable, 1: enable
+ */
+#define ISP_BLC_EN    (BIT(2))
+#define ISP_BLC_EN_M  (ISP_BLC_EN_V << ISP_BLC_EN_S)
+#define ISP_BLC_EN_V  0x00000001U
+#define ISP_BLC_EN_S  2
+/** ISP_DPC_EN : R/W; bitpos: [3]; default: 0;
+ *  this bit configures dpc enable. 0: disable, 1: enable
+ */
+#define ISP_DPC_EN    (BIT(3))
+#define ISP_DPC_EN_M  (ISP_DPC_EN_V << ISP_DPC_EN_S)
+#define ISP_DPC_EN_V  0x00000001U
+#define ISP_DPC_EN_S  3
+/** ISP_BF_EN : R/W; bitpos: [4]; default: 0;
+ *  this bit configures bf enable. 0: disable, 1: enable
+ */
+#define ISP_BF_EN    (BIT(4))
+#define ISP_BF_EN_M  (ISP_BF_EN_V << ISP_BF_EN_S)
+#define ISP_BF_EN_V  0x00000001U
+#define ISP_BF_EN_S  4
+/** ISP_LSC_EN : R/W; bitpos: [5]; default: 0;
+ *  this bit configures lsc enable. 0: disable, 1: enable
+ */
+#define ISP_LSC_EN    (BIT(5))
+#define ISP_LSC_EN_M  (ISP_LSC_EN_V << ISP_LSC_EN_S)
+#define ISP_LSC_EN_V  0x00000001U
+#define ISP_LSC_EN_S  5
+/** ISP_DEMOSAIC_EN : R/W; bitpos: [6]; default: 1;
+ *  this bit configures demosaic enable. 0: disable, 1: enable
+ */
+#define ISP_DEMOSAIC_EN    (BIT(6))
+#define ISP_DEMOSAIC_EN_M  (ISP_DEMOSAIC_EN_V << ISP_DEMOSAIC_EN_S)
+#define ISP_DEMOSAIC_EN_V  0x00000001U
+#define ISP_DEMOSAIC_EN_S  6
+/** ISP_MEDIAN_EN : R/W; bitpos: [7]; default: 0;
+ *  this bit configures median enable. 0: disable, 1: enable
+ */
+#define ISP_MEDIAN_EN    (BIT(7))
+#define ISP_MEDIAN_EN_M  (ISP_MEDIAN_EN_V << ISP_MEDIAN_EN_S)
+#define ISP_MEDIAN_EN_V  0x00000001U
+#define ISP_MEDIAN_EN_S  7
+/** ISP_CCM_EN : R/W; bitpos: [8]; default: 0;
+ *  this bit configures ccm enable. 0: disable, 1: enable
+ */
+#define ISP_CCM_EN    (BIT(8))
+#define ISP_CCM_EN_M  (ISP_CCM_EN_V << ISP_CCM_EN_S)
+#define ISP_CCM_EN_V  0x00000001U
+#define ISP_CCM_EN_S  8
+/** ISP_GAMMA_EN : R/W; bitpos: [9]; default: 0;
+ *  this bit configures gamma enable. 0: disable, 1: enable
+ */
+#define ISP_GAMMA_EN    (BIT(9))
+#define ISP_GAMMA_EN_M  (ISP_GAMMA_EN_V << ISP_GAMMA_EN_S)
+#define ISP_GAMMA_EN_V  0x00000001U
+#define ISP_GAMMA_EN_S  9
+/** ISP_RGB2YUV_EN : R/W; bitpos: [10]; default: 1;
+ *  this bit configures rgb2yuv enable. 0: disable, 1: enable
+ */
+#define ISP_RGB2YUV_EN    (BIT(10))
+#define ISP_RGB2YUV_EN_M  (ISP_RGB2YUV_EN_V << ISP_RGB2YUV_EN_S)
+#define ISP_RGB2YUV_EN_V  0x00000001U
+#define ISP_RGB2YUV_EN_S  10
+/** ISP_SHARP_EN : R/W; bitpos: [11]; default: 0;
+ *  this bit configures sharp enable. 0: disable, 1: enable
+ */
+#define ISP_SHARP_EN    (BIT(11))
+#define ISP_SHARP_EN_M  (ISP_SHARP_EN_V << ISP_SHARP_EN_S)
+#define ISP_SHARP_EN_V  0x00000001U
+#define ISP_SHARP_EN_S  11
+/** ISP_COLOR_EN : R/W; bitpos: [12]; default: 0;
+ *  this bit configures color enable. 0: disable, 1: enable
+ */
+#define ISP_COLOR_EN    (BIT(12))
+#define ISP_COLOR_EN_M  (ISP_COLOR_EN_V << ISP_COLOR_EN_S)
+#define ISP_COLOR_EN_V  0x00000001U
+#define ISP_COLOR_EN_S  12
+/** ISP_YUV2RGB_EN : R/W; bitpos: [13]; default: 1;
+ *  this bit configures yuv2rgb enable. 0: disable, 1: enable
+ */
+#define ISP_YUV2RGB_EN    (BIT(13))
+#define ISP_YUV2RGB_EN_M  (ISP_YUV2RGB_EN_V << ISP_YUV2RGB_EN_S)
+#define ISP_YUV2RGB_EN_V  0x00000001U
+#define ISP_YUV2RGB_EN_S  13
+/** ISP_AE_EN : R/W; bitpos: [14]; default: 0;
+ *  this bit configures ae enable. 0: disable, 1: enable
+ */
+#define ISP_AE_EN    (BIT(14))
+#define ISP_AE_EN_M  (ISP_AE_EN_V << ISP_AE_EN_S)
+#define ISP_AE_EN_V  0x00000001U
+#define ISP_AE_EN_S  14
+/** ISP_AF_EN : R/W; bitpos: [15]; default: 0;
+ *  this bit configures af enable. 0: disable, 1: enable
+ */
+#define ISP_AF_EN    (BIT(15))
+#define ISP_AF_EN_M  (ISP_AF_EN_V << ISP_AF_EN_S)
+#define ISP_AF_EN_V  0x00000001U
+#define ISP_AF_EN_S  15
+/** ISP_AWB_EN : R/W; bitpos: [16]; default: 0;
+ *  this bit configures awb enable. 0: disable, 1: enable
+ */
+#define ISP_AWB_EN    (BIT(16))
+#define ISP_AWB_EN_M  (ISP_AWB_EN_V << ISP_AWB_EN_S)
+#define ISP_AWB_EN_V  0x00000001U
+#define ISP_AWB_EN_S  16
+/** ISP_HIST_EN : R/W; bitpos: [17]; default: 0;
+ *  this bit configures hist enable. 0: disable, 1: enable
+ */
+#define ISP_HIST_EN    (BIT(17))
+#define ISP_HIST_EN_M  (ISP_HIST_EN_V << ISP_HIST_EN_S)
+#define ISP_HIST_EN_V  0x00000001U
+#define ISP_HIST_EN_S  17
+/** ISP_CROP_EN : R/W; bitpos: [18]; default: 0;
+ *  this bit configures crop enable. 0: disable, 1: enable
+ */
+#define ISP_CROP_EN    (BIT(18))
+#define ISP_CROP_EN_M  (ISP_CROP_EN_V << ISP_CROP_EN_S)
+#define ISP_CROP_EN_V  0x00000001U
+#define ISP_CROP_EN_S  18
+/** ISP_WBG_EN : R/W; bitpos: [19]; default: 0;
+ *  this bit configures wbg enable. 0: disable, 1: enable
+ */
+#define ISP_WBG_EN    (BIT(19))
+#define ISP_WBG_EN_M  (ISP_WBG_EN_V << ISP_WBG_EN_S)
+#define ISP_WBG_EN_V  0x00000001U
+#define ISP_WBG_EN_S  19
+/** ISP_BYTE_ENDIAN_ORDER : R/W; bitpos: [24]; default: 0;
+ *  select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1:
+ *  {[7:0], [15:8], [23:16], [31:24]}
+ */
+#define ISP_BYTE_ENDIAN_ORDER    (BIT(24))
+#define ISP_BYTE_ENDIAN_ORDER_M  (ISP_BYTE_ENDIAN_ORDER_V << ISP_BYTE_ENDIAN_ORDER_S)
+#define ISP_BYTE_ENDIAN_ORDER_V  0x00000001U
+#define ISP_BYTE_ENDIAN_ORDER_S  24
+/** ISP_ISP_DATA_TYPE : R/W; bitpos: [26:25]; default: 0;
+ *  this field configures input data type, 0:RAW8 1:RAW10 2:RAW12
+ */
+#define ISP_ISP_DATA_TYPE    0x00000003U
+#define ISP_ISP_DATA_TYPE_M  (ISP_ISP_DATA_TYPE_V << ISP_ISP_DATA_TYPE_S)
+#define ISP_ISP_DATA_TYPE_V  0x00000003U
+#define ISP_ISP_DATA_TYPE_S  25
+/** ISP_ISP_IN_SRC : R/W; bitpos: [28:27]; default: 0;
+ *  this field configures input data source, 0:CSI HOST 1:CAM 2:DMA
+ */
+#define ISP_ISP_IN_SRC    0x00000003U
+#define ISP_ISP_IN_SRC_M  (ISP_ISP_IN_SRC_V << ISP_ISP_IN_SRC_S)
+#define ISP_ISP_IN_SRC_V  0x00000003U
+#define ISP_ISP_IN_SRC_S  27
+/** ISP_ISP_OUT_TYPE : R/W; bitpos: [31:29]; default: 2;
+ *  this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4:
+ *  RGB565
+ */
+#define ISP_ISP_OUT_TYPE    0x00000007U
+#define ISP_ISP_OUT_TYPE_M  (ISP_ISP_OUT_TYPE_V << ISP_ISP_OUT_TYPE_S)
+#define ISP_ISP_OUT_TYPE_V  0x00000007U
+#define ISP_ISP_OUT_TYPE_S  29
+
+/** ISP_HSYNC_CNT_REG register
+ *  header hsync interval control register
+ */
+#define ISP_HSYNC_CNT_REG (DR_REG_ISP_BASE + 0xc)
+/** ISP_HSYNC_CNT : R/W; bitpos: [7:0]; default: 7;
+ *  this field configures the number of clock before hsync and after vsync and line_end
+ *  when decodes pix data from idi to isp
+ */
+#define ISP_HSYNC_CNT    0x000000FFU
+#define ISP_HSYNC_CNT_M  (ISP_HSYNC_CNT_V << ISP_HSYNC_CNT_S)
+#define ISP_HSYNC_CNT_V  0x000000FFU
+#define ISP_HSYNC_CNT_S  0
+
+/** ISP_FRAME_CFG_REG register
+ *  frame control parameter register
+ */
+#define ISP_FRAME_CFG_REG (DR_REG_ISP_BASE + 0x10)
+/** ISP_VADR_NUM : R/W; bitpos: [11:0]; default: 480;
+ *  this field configures input image size in y-direction, image row number - 1
+ */
+#define ISP_VADR_NUM    0x00000FFFU
+#define ISP_VADR_NUM_M  (ISP_VADR_NUM_V << ISP_VADR_NUM_S)
+#define ISP_VADR_NUM_V  0x00000FFFU
+#define ISP_VADR_NUM_S  0
+/** ISP_HADR_NUM : R/W; bitpos: [23:12]; default: 480;
+ *  this field configures input image size in x-direction, image line number - 1
+ */
+#define ISP_HADR_NUM    0x00000FFFU
+#define ISP_HADR_NUM_M  (ISP_HADR_NUM_V << ISP_HADR_NUM_S)
+#define ISP_HADR_NUM_V  0x00000FFFU
+#define ISP_HADR_NUM_S  12
+/** ISP_BAYER_MODE : R/W; bitpos: [28:27]; default: 0;
+ *  this field configures the bayer mode of input pixel. 00 : BG/GR    01 : GB/RG   10
+ *  : GR/BG  11 : RG/GB
+ */
+#define ISP_BAYER_MODE    0x00000003U
+#define ISP_BAYER_MODE_M  (ISP_BAYER_MODE_V << ISP_BAYER_MODE_S)
+#define ISP_BAYER_MODE_V  0x00000003U
+#define ISP_BAYER_MODE_S  27
+/** ISP_HSYNC_START_EXIST : R/W; bitpos: [29]; default: 1;
+ *  this bit configures the line end packet exist or not. 0: not exist, 1: exist
+ */
+#define ISP_HSYNC_START_EXIST    (BIT(29))
+#define ISP_HSYNC_START_EXIST_M  (ISP_HSYNC_START_EXIST_V << ISP_HSYNC_START_EXIST_S)
+#define ISP_HSYNC_START_EXIST_V  0x00000001U
+#define ISP_HSYNC_START_EXIST_S  29
+/** ISP_HSYNC_END_EXIST : R/W; bitpos: [30]; default: 1;
+ *  this bit configures the line start packet exist or not. 0: not exist, 1: exist
+ */
+#define ISP_HSYNC_END_EXIST    (BIT(30))
+#define ISP_HSYNC_END_EXIST_M  (ISP_HSYNC_END_EXIST_V << ISP_HSYNC_END_EXIST_S)
+#define ISP_HSYNC_END_EXIST_V  0x00000001U
+#define ISP_HSYNC_END_EXIST_S  30
+
+/** ISP_CCM_COEF0_REG register
+ *  ccm coef register 0
+ */
+#define ISP_CCM_COEF0_REG (DR_REG_ISP_BASE + 0x14)
+/** ISP_CCM_RR : R/W; bitpos: [12:0]; default: 256;
+ *  this field configures the color correction matrix coefficient
+ */
+#define ISP_CCM_RR    0x00001FFFU
+#define ISP_CCM_RR_M  (ISP_CCM_RR_V << ISP_CCM_RR_S)
+#define ISP_CCM_RR_V  0x00001FFFU
+#define ISP_CCM_RR_S  0
+/** ISP_CCM_RG : R/W; bitpos: [25:13]; default: 0;
+ *  this field configures the color correction matrix coefficient
+ */
+#define ISP_CCM_RG    0x00001FFFU
+#define ISP_CCM_RG_M  (ISP_CCM_RG_V << ISP_CCM_RG_S)
+#define ISP_CCM_RG_V  0x00001FFFU
+#define ISP_CCM_RG_S  13
+
+/** ISP_CCM_COEF1_REG register
+ *  ccm coef register 1
+ */
+#define ISP_CCM_COEF1_REG (DR_REG_ISP_BASE + 0x18)
+/** ISP_CCM_RB : R/W; bitpos: [12:0]; default: 0;
+ *  this field configures the color correction matrix coefficient
+ */
+#define ISP_CCM_RB    0x00001FFFU
+#define ISP_CCM_RB_M  (ISP_CCM_RB_V << ISP_CCM_RB_S)
+#define ISP_CCM_RB_V  0x00001FFFU
+#define ISP_CCM_RB_S  0
+/** ISP_CCM_GR : R/W; bitpos: [25:13]; default: 0;
+ *  this field configures the color correction matrix coefficient
+ */
+#define ISP_CCM_GR    0x00001FFFU
+#define ISP_CCM_GR_M  (ISP_CCM_GR_V << ISP_CCM_GR_S)
+#define ISP_CCM_GR_V  0x00001FFFU
+#define ISP_CCM_GR_S  13
+
+/** ISP_CCM_COEF3_REG register
+ *  ccm coef register 3
+ */
+#define ISP_CCM_COEF3_REG (DR_REG_ISP_BASE + 0x1c)
+/** ISP_CCM_GG : R/W; bitpos: [12:0]; default: 256;
+ *  this field configures the color correction matrix coefficient
+ */
+#define ISP_CCM_GG    0x00001FFFU
+#define ISP_CCM_GG_M  (ISP_CCM_GG_V << ISP_CCM_GG_S)
+#define ISP_CCM_GG_V  0x00001FFFU
+#define ISP_CCM_GG_S  0
+/** ISP_CCM_GB : R/W; bitpos: [25:13]; default: 0;
+ *  this field configures the color correction matrix coefficient
+ */
+#define ISP_CCM_GB    0x00001FFFU
+#define ISP_CCM_GB_M  (ISP_CCM_GB_V << ISP_CCM_GB_S)
+#define ISP_CCM_GB_V  0x00001FFFU
+#define ISP_CCM_GB_S  13
+
+/** ISP_CCM_COEF4_REG register
+ *  ccm coef register 4
+ */
+#define ISP_CCM_COEF4_REG (DR_REG_ISP_BASE + 0x20)
+/** ISP_CCM_BR : R/W; bitpos: [12:0]; default: 0;
+ *  this field configures the color correction matrix coefficient
+ */
+#define ISP_CCM_BR    0x00001FFFU
+#define ISP_CCM_BR_M  (ISP_CCM_BR_V << ISP_CCM_BR_S)
+#define ISP_CCM_BR_V  0x00001FFFU
+#define ISP_CCM_BR_S  0
+/** ISP_CCM_BG : R/W; bitpos: [25:13]; default: 0;
+ *  this field configures the color correction matrix coefficient
+ */
+#define ISP_CCM_BG    0x00001FFFU
+#define ISP_CCM_BG_M  (ISP_CCM_BG_V << ISP_CCM_BG_S)
+#define ISP_CCM_BG_V  0x00001FFFU
+#define ISP_CCM_BG_S  13
+
+/** ISP_CCM_COEF5_REG register
+ *  ccm coef register 5
+ */
+#define ISP_CCM_COEF5_REG (DR_REG_ISP_BASE + 0x24)
+/** ISP_CCM_BB : R/W; bitpos: [12:0]; default: 256;
+ *  this field configures the color correction matrix coefficient
+ */
+#define ISP_CCM_BB    0x00001FFFU
+#define ISP_CCM_BB_M  (ISP_CCM_BB_V << ISP_CCM_BB_S)
+#define ISP_CCM_BB_V  0x00001FFFU
+#define ISP_CCM_BB_S  0
+
+/** ISP_BF_MATRIX_CTRL_REG register
+ *  bf pix2matrix ctrl
+ */
+#define ISP_BF_MATRIX_CTRL_REG (DR_REG_ISP_BASE + 0x28)
+/** ISP_BF_TAIL_PIXEN_PULSE_TL : R/W; bitpos: [7:0]; default: 0;
+ *  matrix tail pixen low level threshold, should not to large to prevent expanding to
+ *  next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0
+ *  and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse
+ *  function
+ */
+#define ISP_BF_TAIL_PIXEN_PULSE_TL    0x000000FFU
+#define ISP_BF_TAIL_PIXEN_PULSE_TL_M  (ISP_BF_TAIL_PIXEN_PULSE_TL_V << ISP_BF_TAIL_PIXEN_PULSE_TL_S)
+#define ISP_BF_TAIL_PIXEN_PULSE_TL_V  0x000000FFU
+#define ISP_BF_TAIL_PIXEN_PULSE_TL_S  0
+/** ISP_BF_TAIL_PIXEN_PULSE_TH : R/W; bitpos: [15:8]; default: 0;
+ *  matrix tail pixen high level threshold, must < hnum-1, only
+ *  reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and
+ *  reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse
+ *  function
+ */
+#define ISP_BF_TAIL_PIXEN_PULSE_TH    0x000000FFU
+#define ISP_BF_TAIL_PIXEN_PULSE_TH_M  (ISP_BF_TAIL_PIXEN_PULSE_TH_V << ISP_BF_TAIL_PIXEN_PULSE_TH_S)
+#define ISP_BF_TAIL_PIXEN_PULSE_TH_V  0x000000FFU
+#define ISP_BF_TAIL_PIXEN_PULSE_TH_S  8
+/** ISP_BF_PADDING_DATA : R/W; bitpos: [23:16]; default: 0;
+ *  this field configures bf matrix padding data
+ */
+#define ISP_BF_PADDING_DATA    0x000000FFU
+#define ISP_BF_PADDING_DATA_M  (ISP_BF_PADDING_DATA_V << ISP_BF_PADDING_DATA_S)
+#define ISP_BF_PADDING_DATA_V  0x000000FFU
+#define ISP_BF_PADDING_DATA_S  16
+/** ISP_BF_PADDING_MODE : R/W; bitpos: [24]; default: 0;
+ *  this bit configures the padding mode of bf matrix.  0: use pixel in image to do
+ *  padding   1: use reg_padding_data to do padding
+ */
+#define ISP_BF_PADDING_MODE    (BIT(24))
+#define ISP_BF_PADDING_MODE_M  (ISP_BF_PADDING_MODE_V << ISP_BF_PADDING_MODE_S)
+#define ISP_BF_PADDING_MODE_V  0x00000001U
+#define ISP_BF_PADDING_MODE_S  24
+
+/** ISP_BF_SIGMA_REG register
+ *  bf denoising level control register
+ */
+#define ISP_BF_SIGMA_REG (DR_REG_ISP_BASE + 0x2c)
+/** ISP_SIGMA : R/W; bitpos: [5:0]; default: 2;
+ *  this field configures the bayer denoising level, valid data from 2 to 20
+ */
+#define ISP_SIGMA    0x0000003FU
+#define ISP_SIGMA_M  (ISP_SIGMA_V << ISP_SIGMA_S)
+#define ISP_SIGMA_V  0x0000003FU
+#define ISP_SIGMA_S  0
+
+/** ISP_BF_GAU0_REG register
+ *  bf gau template register 0
+ */
+#define ISP_BF_GAU0_REG (DR_REG_ISP_BASE + 0x30)
+/** ISP_GAU_TEMPLATE21 : R/W; bitpos: [3:0]; default: 15;
+ *  this field configures index 21 of gaussian template
+ */
+#define ISP_GAU_TEMPLATE21    0x0000000FU
+#define ISP_GAU_TEMPLATE21_M  (ISP_GAU_TEMPLATE21_V << ISP_GAU_TEMPLATE21_S)
+#define ISP_GAU_TEMPLATE21_V  0x0000000FU
+#define ISP_GAU_TEMPLATE21_S  0
+/** ISP_GAU_TEMPLATE20 : R/W; bitpos: [7:4]; default: 15;
+ *  this field configures index 20 of gaussian template
+ */
+#define ISP_GAU_TEMPLATE20    0x0000000FU
+#define ISP_GAU_TEMPLATE20_M  (ISP_GAU_TEMPLATE20_V << ISP_GAU_TEMPLATE20_S)
+#define ISP_GAU_TEMPLATE20_V  0x0000000FU
+#define ISP_GAU_TEMPLATE20_S  4
+/** ISP_GAU_TEMPLATE12 : R/W; bitpos: [11:8]; default: 15;
+ *  this field configures index 12 of gaussian template
+ */
+#define ISP_GAU_TEMPLATE12    0x0000000FU
+#define ISP_GAU_TEMPLATE12_M  (ISP_GAU_TEMPLATE12_V << ISP_GAU_TEMPLATE12_S)
+#define ISP_GAU_TEMPLATE12_V  0x0000000FU
+#define ISP_GAU_TEMPLATE12_S  8
+/** ISP_GAU_TEMPLATE11 : R/W; bitpos: [15:12]; default: 15;
+ *  this field configures index 11 of gaussian template
+ */
+#define ISP_GAU_TEMPLATE11    0x0000000FU
+#define ISP_GAU_TEMPLATE11_M  (ISP_GAU_TEMPLATE11_V << ISP_GAU_TEMPLATE11_S)
+#define ISP_GAU_TEMPLATE11_V  0x0000000FU
+#define ISP_GAU_TEMPLATE11_S  12
+/** ISP_GAU_TEMPLATE10 : R/W; bitpos: [19:16]; default: 15;
+ *  this field configures index 10 of gaussian template
+ */
+#define ISP_GAU_TEMPLATE10    0x0000000FU
+#define ISP_GAU_TEMPLATE10_M  (ISP_GAU_TEMPLATE10_V << ISP_GAU_TEMPLATE10_S)
+#define ISP_GAU_TEMPLATE10_V  0x0000000FU
+#define ISP_GAU_TEMPLATE10_S  16
+/** ISP_GAU_TEMPLATE02 : R/W; bitpos: [23:20]; default: 15;
+ *  this field configures index 02 of gaussian template
+ */
+#define ISP_GAU_TEMPLATE02    0x0000000FU
+#define ISP_GAU_TEMPLATE02_M  (ISP_GAU_TEMPLATE02_V << ISP_GAU_TEMPLATE02_S)
+#define ISP_GAU_TEMPLATE02_V  0x0000000FU
+#define ISP_GAU_TEMPLATE02_S  20
+/** ISP_GAU_TEMPLATE01 : R/W; bitpos: [27:24]; default: 15;
+ *  this field configures index 01 of gaussian template
+ */
+#define ISP_GAU_TEMPLATE01    0x0000000FU
+#define ISP_GAU_TEMPLATE01_M  (ISP_GAU_TEMPLATE01_V << ISP_GAU_TEMPLATE01_S)
+#define ISP_GAU_TEMPLATE01_V  0x0000000FU
+#define ISP_GAU_TEMPLATE01_S  24
+/** ISP_GAU_TEMPLATE00 : R/W; bitpos: [31:28]; default: 15;
+ *  this field configures index 00 of gaussian template
+ */
+#define ISP_GAU_TEMPLATE00    0x0000000FU
+#define ISP_GAU_TEMPLATE00_M  (ISP_GAU_TEMPLATE00_V << ISP_GAU_TEMPLATE00_S)
+#define ISP_GAU_TEMPLATE00_V  0x0000000FU
+#define ISP_GAU_TEMPLATE00_S  28
+
+/** ISP_BF_GAU1_REG register
+ *  bf gau template register 1
+ */
+#define ISP_BF_GAU1_REG (DR_REG_ISP_BASE + 0x34)
+/** ISP_GAU_TEMPLATE22 : R/W; bitpos: [3:0]; default: 15;
+ *  this field configures index 22 of gaussian template
+ */
+#define ISP_GAU_TEMPLATE22    0x0000000FU
+#define ISP_GAU_TEMPLATE22_M  (ISP_GAU_TEMPLATE22_V << ISP_GAU_TEMPLATE22_S)
+#define ISP_GAU_TEMPLATE22_V  0x0000000FU
+#define ISP_GAU_TEMPLATE22_S  0
+
+/** ISP_DPC_CTRL_REG register
+ *  DPC mode control register
+ */
+#define ISP_DPC_CTRL_REG (DR_REG_ISP_BASE + 0x38)
+/** ISP_DPC_CHECK_EN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures the check mode enable. 0: disable, 1: enable
+ */
+#define ISP_DPC_CHECK_EN    (BIT(0))
+#define ISP_DPC_CHECK_EN_M  (ISP_DPC_CHECK_EN_V << ISP_DPC_CHECK_EN_S)
+#define ISP_DPC_CHECK_EN_V  0x00000001U
+#define ISP_DPC_CHECK_EN_S  0
+/** ISP_STA_EN : R/W; bitpos: [1]; default: 0;
+ *  this bit configures the sta dpc enable. 0: disable, 1: enable
+ */
+#define ISP_STA_EN    (BIT(1))
+#define ISP_STA_EN_M  (ISP_STA_EN_V << ISP_STA_EN_S)
+#define ISP_STA_EN_V  0x00000001U
+#define ISP_STA_EN_S  1
+/** ISP_DYN_EN : R/W; bitpos: [2]; default: 1;
+ *  this bit configures the dyn dpc enable. 0: disable, 1: enable
+ */
+#define ISP_DYN_EN    (BIT(2))
+#define ISP_DYN_EN_M  (ISP_DYN_EN_V << ISP_DYN_EN_S)
+#define ISP_DYN_EN_V  0x00000001U
+#define ISP_DYN_EN_S  2
+/** ISP_DPC_BLACK_EN : R/W; bitpos: [3]; default: 0;
+ *  this bit configures input image type select when in check mode, 0: white img, 1:
+ *  black img
+ */
+#define ISP_DPC_BLACK_EN    (BIT(3))
+#define ISP_DPC_BLACK_EN_M  (ISP_DPC_BLACK_EN_V << ISP_DPC_BLACK_EN_S)
+#define ISP_DPC_BLACK_EN_V  0x00000001U
+#define ISP_DPC_BLACK_EN_S  3
+/** ISP_DPC_METHOD_SEL : R/W; bitpos: [4]; default: 0;
+ *  this bit configures dyn dpc method select. 0: simple method, 1: hard method
+ */
+#define ISP_DPC_METHOD_SEL    (BIT(4))
+#define ISP_DPC_METHOD_SEL_M  (ISP_DPC_METHOD_SEL_V << ISP_DPC_METHOD_SEL_S)
+#define ISP_DPC_METHOD_SEL_V  0x00000001U
+#define ISP_DPC_METHOD_SEL_S  4
+/** ISP_DPC_CHECK_OD_EN : R/W; bitpos: [5]; default: 0;
+ *  this bit configures output pixel data when in check mode or not. 0: no data output,
+ *  1: data output
+ */
+#define ISP_DPC_CHECK_OD_EN    (BIT(5))
+#define ISP_DPC_CHECK_OD_EN_M  (ISP_DPC_CHECK_OD_EN_V << ISP_DPC_CHECK_OD_EN_S)
+#define ISP_DPC_CHECK_OD_EN_V  0x00000001U
+#define ISP_DPC_CHECK_OD_EN_S  5
+
+/** ISP_DPC_CONF_REG register
+ *  DPC parameter config register
+ */
+#define ISP_DPC_CONF_REG (DR_REG_ISP_BASE + 0x3c)
+/** ISP_DPC_THRESHOLD_L : R/W; bitpos: [7:0]; default: 48;
+ *  this bit configures the threshold to detect black img in check mode, or the low
+ *  threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit
+ *  10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1
+ */
+#define ISP_DPC_THRESHOLD_L    0x000000FFU
+#define ISP_DPC_THRESHOLD_L_M  (ISP_DPC_THRESHOLD_L_V << ISP_DPC_THRESHOLD_L_S)
+#define ISP_DPC_THRESHOLD_L_V  0x000000FFU
+#define ISP_DPC_THRESHOLD_L_S  0
+/** ISP_DPC_THRESHOLD_H : R/W; bitpos: [15:8]; default: 48;
+ *  this bit configures the threshold to detect white img in check mode, or the high
+ *  threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit
+ *  10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1
+ */
+#define ISP_DPC_THRESHOLD_H    0x000000FFU
+#define ISP_DPC_THRESHOLD_H_M  (ISP_DPC_THRESHOLD_H_V << ISP_DPC_THRESHOLD_H_S)
+#define ISP_DPC_THRESHOLD_H_V  0x000000FFU
+#define ISP_DPC_THRESHOLD_H_S  8
+/** ISP_DPC_FACTOR_DARK : R/W; bitpos: [21:16]; default: 16;
+ *  this field configures the dynamic correction method 1 dark   factor
+ */
+#define ISP_DPC_FACTOR_DARK    0x0000003FU
+#define ISP_DPC_FACTOR_DARK_M  (ISP_DPC_FACTOR_DARK_V << ISP_DPC_FACTOR_DARK_S)
+#define ISP_DPC_FACTOR_DARK_V  0x0000003FU
+#define ISP_DPC_FACTOR_DARK_S  16
+/** ISP_DPC_FACTOR_BRIG : R/W; bitpos: [27:22]; default: 16;
+ *  this field configures the dynamic correction method 1 bright factor
+ */
+#define ISP_DPC_FACTOR_BRIG    0x0000003FU
+#define ISP_DPC_FACTOR_BRIG_M  (ISP_DPC_FACTOR_BRIG_V << ISP_DPC_FACTOR_BRIG_S)
+#define ISP_DPC_FACTOR_BRIG_V  0x0000003FU
+#define ISP_DPC_FACTOR_BRIG_S  22
+
+/** ISP_DPC_MATRIX_CTRL_REG register
+ *  dpc pix2matrix ctrl
+ */
+#define ISP_DPC_MATRIX_CTRL_REG (DR_REG_ISP_BASE + 0x40)
+/** ISP_DPC_TAIL_PIXEN_PULSE_TL : R/W; bitpos: [7:0]; default: 0;
+ *  matrix tail pixen low level threshold,  should not to large to prevent expanding to
+ *  next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0
+ *  and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail
+ *  pulse function
+ */
+#define ISP_DPC_TAIL_PIXEN_PULSE_TL    0x000000FFU
+#define ISP_DPC_TAIL_PIXEN_PULSE_TL_M  (ISP_DPC_TAIL_PIXEN_PULSE_TL_V << ISP_DPC_TAIL_PIXEN_PULSE_TL_S)
+#define ISP_DPC_TAIL_PIXEN_PULSE_TL_V  0x000000FFU
+#define ISP_DPC_TAIL_PIXEN_PULSE_TL_S  0
+/** ISP_DPC_TAIL_PIXEN_PULSE_TH : R/W; bitpos: [15:8]; default: 0;
+ *  matrix tail pixen high level threshold, must < hnum-1, only
+ *  reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and
+ *  reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse
+ *  function
+ */
+#define ISP_DPC_TAIL_PIXEN_PULSE_TH    0x000000FFU
+#define ISP_DPC_TAIL_PIXEN_PULSE_TH_M  (ISP_DPC_TAIL_PIXEN_PULSE_TH_V << ISP_DPC_TAIL_PIXEN_PULSE_TH_S)
+#define ISP_DPC_TAIL_PIXEN_PULSE_TH_V  0x000000FFU
+#define ISP_DPC_TAIL_PIXEN_PULSE_TH_S  8
+/** ISP_DPC_PADDING_DATA : R/W; bitpos: [23:16]; default: 0;
+ *  this field configures dpc matrix padding data
+ */
+#define ISP_DPC_PADDING_DATA    0x000000FFU
+#define ISP_DPC_PADDING_DATA_M  (ISP_DPC_PADDING_DATA_V << ISP_DPC_PADDING_DATA_S)
+#define ISP_DPC_PADDING_DATA_V  0x000000FFU
+#define ISP_DPC_PADDING_DATA_S  16
+/** ISP_DPC_PADDING_MODE : R/W; bitpos: [24]; default: 0;
+ *  this bit configures the padding mode of dpc matrix.  0: use pixel in image to do
+ *  padding   1: use reg_padding_data to do padding
+ */
+#define ISP_DPC_PADDING_MODE    (BIT(24))
+#define ISP_DPC_PADDING_MODE_M  (ISP_DPC_PADDING_MODE_V << ISP_DPC_PADDING_MODE_S)
+#define ISP_DPC_PADDING_MODE_V  0x00000001U
+#define ISP_DPC_PADDING_MODE_S  24
+
+/** ISP_DPC_DEADPIX_CNT_REG register
+ *  DPC dead-pix number register
+ */
+#define ISP_DPC_DEADPIX_CNT_REG (DR_REG_ISP_BASE + 0x44)
+/** ISP_DPC_DEADPIX_CNT : RO; bitpos: [9:0]; default: 0;
+ *  this field represents the dead pixel count
+ */
+#define ISP_DPC_DEADPIX_CNT    0x000003FFU
+#define ISP_DPC_DEADPIX_CNT_M  (ISP_DPC_DEADPIX_CNT_V << ISP_DPC_DEADPIX_CNT_S)
+#define ISP_DPC_DEADPIX_CNT_V  0x000003FFU
+#define ISP_DPC_DEADPIX_CNT_S  0
+
+/** ISP_LUT_CMD_REG register
+ *  LUT command register
+ */
+#define ISP_LUT_CMD_REG (DR_REG_ISP_BASE + 0x48)
+/** ISP_LUT_ADDR : WT; bitpos: [11:0]; default: 0;
+ *  this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b
+ *  lut, 01 sel r_gr lut
+ */
+#define ISP_LUT_ADDR    0x00000FFFU
+#define ISP_LUT_ADDR_M  (ISP_LUT_ADDR_V << ISP_LUT_ADDR_S)
+#define ISP_LUT_ADDR_V  0x00000FFFU
+#define ISP_LUT_ADDR_S  0
+/** ISP_LUT_NUM : WT; bitpos: [15:12]; default: 0;
+ *  this field configures the lut selection. 0000:LSC LUT. 0001:DPC LUT. 0010:AWB LUT
+ */
+#define ISP_LUT_NUM    0x0000000FU
+#define ISP_LUT_NUM_M  (ISP_LUT_NUM_V << ISP_LUT_NUM_S)
+#define ISP_LUT_NUM_V  0x0000000FU
+#define ISP_LUT_NUM_S  12
+/** ISP_LUT_CMD : WT; bitpos: [16]; default: 0;
+ *  this bit configures the access event of lut. 0:rd 1: wr
+ */
+#define ISP_LUT_CMD    (BIT(16))
+#define ISP_LUT_CMD_M  (ISP_LUT_CMD_V << ISP_LUT_CMD_S)
+#define ISP_LUT_CMD_V  0x00000001U
+#define ISP_LUT_CMD_S  16
+
+/** ISP_LUT_WDATA_REG register
+ *  LUT write data register
+ */
+#define ISP_LUT_WDATA_REG (DR_REG_ISP_BASE + 0x4c)
+/** ISP_LUT_WDATA : R/W; bitpos: [31:0]; default: 0;
+ *  this field configures the write data of lut. please initial ISP_LUT_WDATA before
+ *  write ISP_LUT_CMD register
+ */
+#define ISP_LUT_WDATA    0xFFFFFFFFU
+#define ISP_LUT_WDATA_M  (ISP_LUT_WDATA_V << ISP_LUT_WDATA_S)
+#define ISP_LUT_WDATA_V  0xFFFFFFFFU
+#define ISP_LUT_WDATA_S  0
+
+/** ISP_LUT_RDATA_REG register
+ *  LUT read data register
+ */
+#define ISP_LUT_RDATA_REG (DR_REG_ISP_BASE + 0x50)
+/** ISP_LUT_RDATA : RO; bitpos: [31:0]; default: 0;
+ *  this field represents the read data of lut. read ISP_LUT_RDATA after write
+ *  ISP_LUT_CMD register
+ */
+#define ISP_LUT_RDATA    0xFFFFFFFFU
+#define ISP_LUT_RDATA_M  (ISP_LUT_RDATA_V << ISP_LUT_RDATA_S)
+#define ISP_LUT_RDATA_V  0xFFFFFFFFU
+#define ISP_LUT_RDATA_S  0
+
+/** ISP_LSC_TABLESIZE_REG register
+ *  LSC point in x-direction
+ */
+#define ISP_LSC_TABLESIZE_REG (DR_REG_ISP_BASE + 0x54)
+/** ISP_LSC_XTABLESIZE : R/W; bitpos: [4:0]; default: 31;
+ *  this field configures lsc table size in x-direction
+ */
+#define ISP_LSC_XTABLESIZE    0x0000001FU
+#define ISP_LSC_XTABLESIZE_M  (ISP_LSC_XTABLESIZE_V << ISP_LSC_XTABLESIZE_S)
+#define ISP_LSC_XTABLESIZE_V  0x0000001FU
+#define ISP_LSC_XTABLESIZE_S  0
+
+/** ISP_DEMOSAIC_MATRIX_CTRL_REG register
+ *  demosaic pix2matrix ctrl
+ */
+#define ISP_DEMOSAIC_MATRIX_CTRL_REG (DR_REG_ISP_BASE + 0x58)
+/** ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL : R/W; bitpos: [7:0]; default: 0;
+ *  matrix tail pixen low level threshold,  should not to large to prevent expanding to
+ *  next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and
+ *  reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th <
+ *  reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function
+ */
+#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL    0x000000FFU
+#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL_M  (ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL_V << ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL_S)
+#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL_V  0x000000FFU
+#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL_S  0
+/** ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH : R/W; bitpos: [15:8]; default: 0;
+ *  matrix tail pixen high level threshold, must < hnum-1, only
+ *  reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and
+ *  reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable
+ *  tail pulse function
+ */
+#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH    0x000000FFU
+#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH_M  (ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH_V << ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH_S)
+#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH_V  0x000000FFU
+#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH_S  8
+/** ISP_DEMOSAIC_PADDING_DATA : R/W; bitpos: [23:16]; default: 0;
+ *  this field configures demosaic matrix padding data
+ */
+#define ISP_DEMOSAIC_PADDING_DATA    0x000000FFU
+#define ISP_DEMOSAIC_PADDING_DATA_M  (ISP_DEMOSAIC_PADDING_DATA_V << ISP_DEMOSAIC_PADDING_DATA_S)
+#define ISP_DEMOSAIC_PADDING_DATA_V  0x000000FFU
+#define ISP_DEMOSAIC_PADDING_DATA_S  16
+/** ISP_DEMOSAIC_PADDING_MODE : R/W; bitpos: [24]; default: 0;
+ *  this bit configures the padding mode of demosaic matrix.  0: use pixel in image to
+ *  do padding   1: use reg_padding_data to do padding
+ */
+#define ISP_DEMOSAIC_PADDING_MODE    (BIT(24))
+#define ISP_DEMOSAIC_PADDING_MODE_M  (ISP_DEMOSAIC_PADDING_MODE_V << ISP_DEMOSAIC_PADDING_MODE_S)
+#define ISP_DEMOSAIC_PADDING_MODE_V  0x00000001U
+#define ISP_DEMOSAIC_PADDING_MODE_S  24
+
+/** ISP_DEMOSAIC_GRAD_RATIO_REG register
+ *  demosaic gradient select ratio
+ */
+#define ISP_DEMOSAIC_GRAD_RATIO_REG (DR_REG_ISP_BASE + 0x5c)
+/** ISP_DEMOSAIC_GRAD_RATIO : R/W; bitpos: [5:0]; default: 16;
+ *  this field configures demosaic gradient select ratio
+ */
+#define ISP_DEMOSAIC_GRAD_RATIO    0x0000003FU
+#define ISP_DEMOSAIC_GRAD_RATIO_M  (ISP_DEMOSAIC_GRAD_RATIO_V << ISP_DEMOSAIC_GRAD_RATIO_S)
+#define ISP_DEMOSAIC_GRAD_RATIO_V  0x0000003FU
+#define ISP_DEMOSAIC_GRAD_RATIO_S  0
+
+/** ISP_MEDIAN_MATRIX_CTRL_REG register
+ *  median pix2matrix ctrl
+ */
+#define ISP_MEDIAN_MATRIX_CTRL_REG (DR_REG_ISP_BASE + 0x60)
+/** ISP_MEDIAN_PADDING_DATA : R/W; bitpos: [7:0]; default: 0;
+ *  this field configures median matrix padding data
+ */
+#define ISP_MEDIAN_PADDING_DATA    0x000000FFU
+#define ISP_MEDIAN_PADDING_DATA_M  (ISP_MEDIAN_PADDING_DATA_V << ISP_MEDIAN_PADDING_DATA_S)
+#define ISP_MEDIAN_PADDING_DATA_V  0x000000FFU
+#define ISP_MEDIAN_PADDING_DATA_S  0
+/** ISP_MEDIAN_PADDING_MODE : R/W; bitpos: [8]; default: 0;
+ *  this bit configures the padding mode of median matrix.  0: use pixel in image to do
+ *  padding   1: use reg_padding_data to do padding
+ */
+#define ISP_MEDIAN_PADDING_MODE    (BIT(8))
+#define ISP_MEDIAN_PADDING_MODE_M  (ISP_MEDIAN_PADDING_MODE_V << ISP_MEDIAN_PADDING_MODE_S)
+#define ISP_MEDIAN_PADDING_MODE_V  0x00000001U
+#define ISP_MEDIAN_PADDING_MODE_S  8
+
+/** ISP_INT_RAW_REG register
+ *  raw interrupt register
+ */
+#define ISP_INT_RAW_REG (DR_REG_ISP_BASE + 0x64)
+/** ISP_ISP_DATA_TYPE_ERR_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  the raw interrupt status of input data type error. isp only support RGB bayer data
+ *  type, other type will report type_err_int
+ */
+#define ISP_ISP_DATA_TYPE_ERR_INT_RAW    (BIT(0))
+#define ISP_ISP_DATA_TYPE_ERR_INT_RAW_M  (ISP_ISP_DATA_TYPE_ERR_INT_RAW_V << ISP_ISP_DATA_TYPE_ERR_INT_RAW_S)
+#define ISP_ISP_DATA_TYPE_ERR_INT_RAW_V  0x00000001U
+#define ISP_ISP_DATA_TYPE_ERR_INT_RAW_S  0
+/** ISP_ISP_ASYNC_FIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  the raw interrupt status of isp input fifo overflow
+ */
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_RAW    (BIT(1))
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_RAW_M  (ISP_ISP_ASYNC_FIFO_OVF_INT_RAW_V << ISP_ISP_ASYNC_FIFO_OVF_INT_RAW_S)
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_RAW_V  0x00000001U
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_RAW_S  1
+/** ISP_ISP_BUF_FULL_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  the raw interrupt status of isp input buffer full
+ */
+#define ISP_ISP_BUF_FULL_INT_RAW    (BIT(2))
+#define ISP_ISP_BUF_FULL_INT_RAW_M  (ISP_ISP_BUF_FULL_INT_RAW_V << ISP_ISP_BUF_FULL_INT_RAW_S)
+#define ISP_ISP_BUF_FULL_INT_RAW_V  0x00000001U
+#define ISP_ISP_BUF_FULL_INT_RAW_S  2
+/** ISP_ISP_HVNUM_SETTING_ERR_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  the raw interrupt status of hnum and vnum setting format error
+ */
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_RAW    (BIT(3))
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_RAW_M  (ISP_ISP_HVNUM_SETTING_ERR_INT_RAW_V << ISP_ISP_HVNUM_SETTING_ERR_INT_RAW_S)
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_RAW_V  0x00000001U
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_RAW_S  3
+/** ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  the raw interrupt status of setting invalid reg_data_type
+ */
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW    (BIT(4))
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_M  (ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_V << ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_S)
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_V  0x00000001U
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_S  4
+/** ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  the raw interrupt status of hnum setting unmatch with mipi input
+ */
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW    (BIT(5))
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW_M  (ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW_V << ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW_S)
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW_V  0x00000001U
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW_S  5
+/** ISP_DPC_CHECK_DONE_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  the raw interrupt status of dpc check done
+ */
+#define ISP_DPC_CHECK_DONE_INT_RAW    (BIT(6))
+#define ISP_DPC_CHECK_DONE_INT_RAW_M  (ISP_DPC_CHECK_DONE_INT_RAW_V << ISP_DPC_CHECK_DONE_INT_RAW_S)
+#define ISP_DPC_CHECK_DONE_INT_RAW_V  0x00000001U
+#define ISP_DPC_CHECK_DONE_INT_RAW_S  6
+/** ISP_GAMMA_XCOORD_ERR_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
+ *  the raw interrupt status of gamma setting error. it report the sum of the lengths
+ *  represented by reg_gamma_x00~x0F isn't equal to 256
+ */
+#define ISP_GAMMA_XCOORD_ERR_INT_RAW    (BIT(7))
+#define ISP_GAMMA_XCOORD_ERR_INT_RAW_M  (ISP_GAMMA_XCOORD_ERR_INT_RAW_V << ISP_GAMMA_XCOORD_ERR_INT_RAW_S)
+#define ISP_GAMMA_XCOORD_ERR_INT_RAW_V  0x00000001U
+#define ISP_GAMMA_XCOORD_ERR_INT_RAW_S  7
+/** ISP_AE_MONITOR_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
+ *  the raw interrupt status of ae monitor
+ */
+#define ISP_AE_MONITOR_INT_RAW    (BIT(8))
+#define ISP_AE_MONITOR_INT_RAW_M  (ISP_AE_MONITOR_INT_RAW_V << ISP_AE_MONITOR_INT_RAW_S)
+#define ISP_AE_MONITOR_INT_RAW_V  0x00000001U
+#define ISP_AE_MONITOR_INT_RAW_S  8
+/** ISP_AE_FRAME_DONE_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
+ *  the raw interrupt status of ae.
+ */
+#define ISP_AE_FRAME_DONE_INT_RAW    (BIT(9))
+#define ISP_AE_FRAME_DONE_INT_RAW_M  (ISP_AE_FRAME_DONE_INT_RAW_V << ISP_AE_FRAME_DONE_INT_RAW_S)
+#define ISP_AE_FRAME_DONE_INT_RAW_V  0x00000001U
+#define ISP_AE_FRAME_DONE_INT_RAW_S  9
+/** ISP_AF_FDONE_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
+ *  the raw interrupt status of af statistic. when auto_update enable, each frame done
+ *  will send one int pulse when manual_update, each time when write 1 to
+ *  reg_manual_update will send a int pulse when next frame done
+ */
+#define ISP_AF_FDONE_INT_RAW    (BIT(10))
+#define ISP_AF_FDONE_INT_RAW_M  (ISP_AF_FDONE_INT_RAW_V << ISP_AF_FDONE_INT_RAW_S)
+#define ISP_AF_FDONE_INT_RAW_V  0x00000001U
+#define ISP_AF_FDONE_INT_RAW_S  10
+/** ISP_AF_ENV_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
+ *  the raw interrupt status of af monitor. send a int pulse when env_det function
+ *  enabled and environment changes detected
+ */
+#define ISP_AF_ENV_INT_RAW    (BIT(11))
+#define ISP_AF_ENV_INT_RAW_M  (ISP_AF_ENV_INT_RAW_V << ISP_AF_ENV_INT_RAW_S)
+#define ISP_AF_ENV_INT_RAW_V  0x00000001U
+#define ISP_AF_ENV_INT_RAW_S  11
+/** ISP_AWB_FDONE_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
+ *  the raw interrupt status of awb. send a int pulse when statistic of one awb frame
+ *  done
+ */
+#define ISP_AWB_FDONE_INT_RAW    (BIT(12))
+#define ISP_AWB_FDONE_INT_RAW_M  (ISP_AWB_FDONE_INT_RAW_V << ISP_AWB_FDONE_INT_RAW_S)
+#define ISP_AWB_FDONE_INT_RAW_V  0x00000001U
+#define ISP_AWB_FDONE_INT_RAW_S  12
+/** ISP_HIST_FDONE_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
+ *  the raw interrupt status of histogram. send a int pulse when statistic of one frame
+ *  histogram done
+ */
+#define ISP_HIST_FDONE_INT_RAW    (BIT(13))
+#define ISP_HIST_FDONE_INT_RAW_M  (ISP_HIST_FDONE_INT_RAW_V << ISP_HIST_FDONE_INT_RAW_S)
+#define ISP_HIST_FDONE_INT_RAW_V  0x00000001U
+#define ISP_HIST_FDONE_INT_RAW_S  13
+/** ISP_FRAME_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
+ *  the raw interrupt status of isp frame end
+ */
+#define ISP_FRAME_INT_RAW    (BIT(14))
+#define ISP_FRAME_INT_RAW_M  (ISP_FRAME_INT_RAW_V << ISP_FRAME_INT_RAW_S)
+#define ISP_FRAME_INT_RAW_V  0x00000001U
+#define ISP_FRAME_INT_RAW_S  14
+/** ISP_BLC_FRAME_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
+ *  the raw interrupt status of blc frame done
+ */
+#define ISP_BLC_FRAME_INT_RAW    (BIT(15))
+#define ISP_BLC_FRAME_INT_RAW_M  (ISP_BLC_FRAME_INT_RAW_V << ISP_BLC_FRAME_INT_RAW_S)
+#define ISP_BLC_FRAME_INT_RAW_V  0x00000001U
+#define ISP_BLC_FRAME_INT_RAW_S  15
+/** ISP_LSC_FRAME_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0;
+ *  the raw interrupt status of lsc frame done
+ */
+#define ISP_LSC_FRAME_INT_RAW    (BIT(16))
+#define ISP_LSC_FRAME_INT_RAW_M  (ISP_LSC_FRAME_INT_RAW_V << ISP_LSC_FRAME_INT_RAW_S)
+#define ISP_LSC_FRAME_INT_RAW_V  0x00000001U
+#define ISP_LSC_FRAME_INT_RAW_S  16
+/** ISP_DPC_FRAME_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0;
+ *  the raw interrupt status of dpc frame done
+ */
+#define ISP_DPC_FRAME_INT_RAW    (BIT(17))
+#define ISP_DPC_FRAME_INT_RAW_M  (ISP_DPC_FRAME_INT_RAW_V << ISP_DPC_FRAME_INT_RAW_S)
+#define ISP_DPC_FRAME_INT_RAW_V  0x00000001U
+#define ISP_DPC_FRAME_INT_RAW_S  17
+/** ISP_BF_FRAME_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0;
+ *  the raw interrupt status of bf frame done
+ */
+#define ISP_BF_FRAME_INT_RAW    (BIT(18))
+#define ISP_BF_FRAME_INT_RAW_M  (ISP_BF_FRAME_INT_RAW_V << ISP_BF_FRAME_INT_RAW_S)
+#define ISP_BF_FRAME_INT_RAW_V  0x00000001U
+#define ISP_BF_FRAME_INT_RAW_S  18
+/** ISP_DEMOSAIC_FRAME_INT_RAW : R/SS/WTC; bitpos: [19]; default: 0;
+ *  the raw interrupt status of demosaic frame done
+ */
+#define ISP_DEMOSAIC_FRAME_INT_RAW    (BIT(19))
+#define ISP_DEMOSAIC_FRAME_INT_RAW_M  (ISP_DEMOSAIC_FRAME_INT_RAW_V << ISP_DEMOSAIC_FRAME_INT_RAW_S)
+#define ISP_DEMOSAIC_FRAME_INT_RAW_V  0x00000001U
+#define ISP_DEMOSAIC_FRAME_INT_RAW_S  19
+/** ISP_MEDIAN_FRAME_INT_RAW : R/SS/WTC; bitpos: [20]; default: 0;
+ *  the raw interrupt status of median frame done
+ */
+#define ISP_MEDIAN_FRAME_INT_RAW    (BIT(20))
+#define ISP_MEDIAN_FRAME_INT_RAW_M  (ISP_MEDIAN_FRAME_INT_RAW_V << ISP_MEDIAN_FRAME_INT_RAW_S)
+#define ISP_MEDIAN_FRAME_INT_RAW_V  0x00000001U
+#define ISP_MEDIAN_FRAME_INT_RAW_S  20
+/** ISP_CCM_FRAME_INT_RAW : R/SS/WTC; bitpos: [21]; default: 0;
+ *  the raw interrupt status of ccm frame done
+ */
+#define ISP_CCM_FRAME_INT_RAW    (BIT(21))
+#define ISP_CCM_FRAME_INT_RAW_M  (ISP_CCM_FRAME_INT_RAW_V << ISP_CCM_FRAME_INT_RAW_S)
+#define ISP_CCM_FRAME_INT_RAW_V  0x00000001U
+#define ISP_CCM_FRAME_INT_RAW_S  21
+/** ISP_GAMMA_FRAME_INT_RAW : R/SS/WTC; bitpos: [22]; default: 0;
+ *  the raw interrupt status of gamma frame done
+ */
+#define ISP_GAMMA_FRAME_INT_RAW    (BIT(22))
+#define ISP_GAMMA_FRAME_INT_RAW_M  (ISP_GAMMA_FRAME_INT_RAW_V << ISP_GAMMA_FRAME_INT_RAW_S)
+#define ISP_GAMMA_FRAME_INT_RAW_V  0x00000001U
+#define ISP_GAMMA_FRAME_INT_RAW_S  22
+/** ISP_RGB2YUV_FRAME_INT_RAW : R/SS/WTC; bitpos: [23]; default: 0;
+ *  the raw interrupt status of rgb2yuv frame done
+ */
+#define ISP_RGB2YUV_FRAME_INT_RAW    (BIT(23))
+#define ISP_RGB2YUV_FRAME_INT_RAW_M  (ISP_RGB2YUV_FRAME_INT_RAW_V << ISP_RGB2YUV_FRAME_INT_RAW_S)
+#define ISP_RGB2YUV_FRAME_INT_RAW_V  0x00000001U
+#define ISP_RGB2YUV_FRAME_INT_RAW_S  23
+/** ISP_SHARP_FRAME_INT_RAW : R/SS/WTC; bitpos: [24]; default: 0;
+ *  the raw interrupt status of sharp frame done
+ */
+#define ISP_SHARP_FRAME_INT_RAW    (BIT(24))
+#define ISP_SHARP_FRAME_INT_RAW_M  (ISP_SHARP_FRAME_INT_RAW_V << ISP_SHARP_FRAME_INT_RAW_S)
+#define ISP_SHARP_FRAME_INT_RAW_V  0x00000001U
+#define ISP_SHARP_FRAME_INT_RAW_S  24
+/** ISP_COLOR_FRAME_INT_RAW : R/SS/WTC; bitpos: [25]; default: 0;
+ *  the raw interrupt status of color frame done
+ */
+#define ISP_COLOR_FRAME_INT_RAW    (BIT(25))
+#define ISP_COLOR_FRAME_INT_RAW_M  (ISP_COLOR_FRAME_INT_RAW_V << ISP_COLOR_FRAME_INT_RAW_S)
+#define ISP_COLOR_FRAME_INT_RAW_V  0x00000001U
+#define ISP_COLOR_FRAME_INT_RAW_S  25
+/** ISP_YUV2RGB_FRAME_INT_RAW : R/SS/WTC; bitpos: [26]; default: 0;
+ *  the raw interrupt status of yuv2rgb frame done
+ */
+#define ISP_YUV2RGB_FRAME_INT_RAW    (BIT(26))
+#define ISP_YUV2RGB_FRAME_INT_RAW_M  (ISP_YUV2RGB_FRAME_INT_RAW_V << ISP_YUV2RGB_FRAME_INT_RAW_S)
+#define ISP_YUV2RGB_FRAME_INT_RAW_V  0x00000001U
+#define ISP_YUV2RGB_FRAME_INT_RAW_S  26
+/** ISP_TAIL_IDI_FRAME_INT_RAW : R/SS/WTC; bitpos: [27]; default: 0;
+ *  the raw interrupt status of isp_tail idi frame_end
+ */
+#define ISP_TAIL_IDI_FRAME_INT_RAW    (BIT(27))
+#define ISP_TAIL_IDI_FRAME_INT_RAW_M  (ISP_TAIL_IDI_FRAME_INT_RAW_V << ISP_TAIL_IDI_FRAME_INT_RAW_S)
+#define ISP_TAIL_IDI_FRAME_INT_RAW_V  0x00000001U
+#define ISP_TAIL_IDI_FRAME_INT_RAW_S  27
+/** ISP_HEADER_IDI_FRAME_INT_RAW : R/SS/WTC; bitpos: [28]; default: 0;
+ *  the raw interrupt status of real input frame end of isp_input
+ */
+#define ISP_HEADER_IDI_FRAME_INT_RAW    (BIT(28))
+#define ISP_HEADER_IDI_FRAME_INT_RAW_M  (ISP_HEADER_IDI_FRAME_INT_RAW_V << ISP_HEADER_IDI_FRAME_INT_RAW_S)
+#define ISP_HEADER_IDI_FRAME_INT_RAW_V  0x00000001U
+#define ISP_HEADER_IDI_FRAME_INT_RAW_S  28
+/** ISP_CROP_FRAME_INT_RAW : R/SS/WTC; bitpos: [29]; default: 0;
+ *  the raw interrupt status of crop frame done
+ */
+#define ISP_CROP_FRAME_INT_RAW    (BIT(29))
+#define ISP_CROP_FRAME_INT_RAW_M  (ISP_CROP_FRAME_INT_RAW_V << ISP_CROP_FRAME_INT_RAW_S)
+#define ISP_CROP_FRAME_INT_RAW_V  0x00000001U
+#define ISP_CROP_FRAME_INT_RAW_S  29
+/** ISP_WBG_FRAME_INT_RAW : R/SS/WTC; bitpos: [30]; default: 0;
+ *  the raw interrupt status of wbg frame done
+ */
+#define ISP_WBG_FRAME_INT_RAW    (BIT(30))
+#define ISP_WBG_FRAME_INT_RAW_M  (ISP_WBG_FRAME_INT_RAW_V << ISP_WBG_FRAME_INT_RAW_S)
+#define ISP_WBG_FRAME_INT_RAW_V  0x00000001U
+#define ISP_WBG_FRAME_INT_RAW_S  30
+/** ISP_CROP_ERR_INT_RAW : R/SS/WTC; bitpos: [31]; default: 0;
+ *  the raw interrupt status of crop error
+ */
+#define ISP_CROP_ERR_INT_RAW    (BIT(31))
+#define ISP_CROP_ERR_INT_RAW_M  (ISP_CROP_ERR_INT_RAW_V << ISP_CROP_ERR_INT_RAW_S)
+#define ISP_CROP_ERR_INT_RAW_V  0x00000001U
+#define ISP_CROP_ERR_INT_RAW_S  31
+
+/** ISP_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define ISP_INT_ST_REG (DR_REG_ISP_BASE + 0x68)
+/** ISP_ISP_DATA_TYPE_ERR_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of input data type error
+ */
+#define ISP_ISP_DATA_TYPE_ERR_INT_ST    (BIT(0))
+#define ISP_ISP_DATA_TYPE_ERR_INT_ST_M  (ISP_ISP_DATA_TYPE_ERR_INT_ST_V << ISP_ISP_DATA_TYPE_ERR_INT_ST_S)
+#define ISP_ISP_DATA_TYPE_ERR_INT_ST_V  0x00000001U
+#define ISP_ISP_DATA_TYPE_ERR_INT_ST_S  0
+/** ISP_ISP_ASYNC_FIFO_OVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of isp input fifo overflow
+ */
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_ST    (BIT(1))
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_ST_M  (ISP_ISP_ASYNC_FIFO_OVF_INT_ST_V << ISP_ISP_ASYNC_FIFO_OVF_INT_ST_S)
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_ST_V  0x00000001U
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_ST_S  1
+/** ISP_ISP_BUF_FULL_INT_ST : RO; bitpos: [2]; default: 0;
+ *  the masked interrupt status of isp input buffer full
+ */
+#define ISP_ISP_BUF_FULL_INT_ST    (BIT(2))
+#define ISP_ISP_BUF_FULL_INT_ST_M  (ISP_ISP_BUF_FULL_INT_ST_V << ISP_ISP_BUF_FULL_INT_ST_S)
+#define ISP_ISP_BUF_FULL_INT_ST_V  0x00000001U
+#define ISP_ISP_BUF_FULL_INT_ST_S  2
+/** ISP_ISP_HVNUM_SETTING_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  the masked interrupt status of hnum and vnum setting format error
+ */
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_ST    (BIT(3))
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_ST_M  (ISP_ISP_HVNUM_SETTING_ERR_INT_ST_V << ISP_ISP_HVNUM_SETTING_ERR_INT_ST_S)
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_ST_V  0x00000001U
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_ST_S  3
+/** ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  the masked interrupt status of setting invalid reg_data_type
+ */
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST    (BIT(4))
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST_M  (ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST_V << ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST_S)
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST_V  0x00000001U
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST_S  4
+/** ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST : RO; bitpos: [5]; default: 0;
+ *  the masked interrupt status of hnum setting unmatch with mipi input
+ */
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST    (BIT(5))
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST_M  (ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST_V << ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST_S)
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST_V  0x00000001U
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST_S  5
+/** ISP_DPC_CHECK_DONE_INT_ST : RO; bitpos: [6]; default: 0;
+ *  the masked interrupt status of dpc check done
+ */
+#define ISP_DPC_CHECK_DONE_INT_ST    (BIT(6))
+#define ISP_DPC_CHECK_DONE_INT_ST_M  (ISP_DPC_CHECK_DONE_INT_ST_V << ISP_DPC_CHECK_DONE_INT_ST_S)
+#define ISP_DPC_CHECK_DONE_INT_ST_V  0x00000001U
+#define ISP_DPC_CHECK_DONE_INT_ST_S  6
+/** ISP_GAMMA_XCOORD_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  the masked interrupt status of gamma setting error
+ */
+#define ISP_GAMMA_XCOORD_ERR_INT_ST    (BIT(7))
+#define ISP_GAMMA_XCOORD_ERR_INT_ST_M  (ISP_GAMMA_XCOORD_ERR_INT_ST_V << ISP_GAMMA_XCOORD_ERR_INT_ST_S)
+#define ISP_GAMMA_XCOORD_ERR_INT_ST_V  0x00000001U
+#define ISP_GAMMA_XCOORD_ERR_INT_ST_S  7
+/** ISP_AE_MONITOR_INT_ST : RO; bitpos: [8]; default: 0;
+ *  the masked interrupt status of ae monitor
+ */
+#define ISP_AE_MONITOR_INT_ST    (BIT(8))
+#define ISP_AE_MONITOR_INT_ST_M  (ISP_AE_MONITOR_INT_ST_V << ISP_AE_MONITOR_INT_ST_S)
+#define ISP_AE_MONITOR_INT_ST_V  0x00000001U
+#define ISP_AE_MONITOR_INT_ST_S  8
+/** ISP_AE_FRAME_DONE_INT_ST : RO; bitpos: [9]; default: 0;
+ *  the masked interrupt status of ae
+ */
+#define ISP_AE_FRAME_DONE_INT_ST    (BIT(9))
+#define ISP_AE_FRAME_DONE_INT_ST_M  (ISP_AE_FRAME_DONE_INT_ST_V << ISP_AE_FRAME_DONE_INT_ST_S)
+#define ISP_AE_FRAME_DONE_INT_ST_V  0x00000001U
+#define ISP_AE_FRAME_DONE_INT_ST_S  9
+/** ISP_AF_FDONE_INT_ST : RO; bitpos: [10]; default: 0;
+ *  the masked interrupt status of af statistic
+ */
+#define ISP_AF_FDONE_INT_ST    (BIT(10))
+#define ISP_AF_FDONE_INT_ST_M  (ISP_AF_FDONE_INT_ST_V << ISP_AF_FDONE_INT_ST_S)
+#define ISP_AF_FDONE_INT_ST_V  0x00000001U
+#define ISP_AF_FDONE_INT_ST_S  10
+/** ISP_AF_ENV_INT_ST : RO; bitpos: [11]; default: 0;
+ *  the masked interrupt status of af monitor
+ */
+#define ISP_AF_ENV_INT_ST    (BIT(11))
+#define ISP_AF_ENV_INT_ST_M  (ISP_AF_ENV_INT_ST_V << ISP_AF_ENV_INT_ST_S)
+#define ISP_AF_ENV_INT_ST_V  0x00000001U
+#define ISP_AF_ENV_INT_ST_S  11
+/** ISP_AWB_FDONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  the masked interrupt status of awb
+ */
+#define ISP_AWB_FDONE_INT_ST    (BIT(12))
+#define ISP_AWB_FDONE_INT_ST_M  (ISP_AWB_FDONE_INT_ST_V << ISP_AWB_FDONE_INT_ST_S)
+#define ISP_AWB_FDONE_INT_ST_V  0x00000001U
+#define ISP_AWB_FDONE_INT_ST_S  12
+/** ISP_HIST_FDONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  the masked interrupt status of histogram
+ */
+#define ISP_HIST_FDONE_INT_ST    (BIT(13))
+#define ISP_HIST_FDONE_INT_ST_M  (ISP_HIST_FDONE_INT_ST_V << ISP_HIST_FDONE_INT_ST_S)
+#define ISP_HIST_FDONE_INT_ST_V  0x00000001U
+#define ISP_HIST_FDONE_INT_ST_S  13
+/** ISP_FRAME_INT_ST : RO; bitpos: [14]; default: 0;
+ *  the masked interrupt status of isp frame end
+ */
+#define ISP_FRAME_INT_ST    (BIT(14))
+#define ISP_FRAME_INT_ST_M  (ISP_FRAME_INT_ST_V << ISP_FRAME_INT_ST_S)
+#define ISP_FRAME_INT_ST_V  0x00000001U
+#define ISP_FRAME_INT_ST_S  14
+/** ISP_BLC_FRAME_INT_ST : RO; bitpos: [15]; default: 0;
+ *  the masked interrupt status of blc frame done
+ */
+#define ISP_BLC_FRAME_INT_ST    (BIT(15))
+#define ISP_BLC_FRAME_INT_ST_M  (ISP_BLC_FRAME_INT_ST_V << ISP_BLC_FRAME_INT_ST_S)
+#define ISP_BLC_FRAME_INT_ST_V  0x00000001U
+#define ISP_BLC_FRAME_INT_ST_S  15
+/** ISP_LSC_FRAME_INT_ST : RO; bitpos: [16]; default: 0;
+ *  the masked interrupt status of lsc frame done
+ */
+#define ISP_LSC_FRAME_INT_ST    (BIT(16))
+#define ISP_LSC_FRAME_INT_ST_M  (ISP_LSC_FRAME_INT_ST_V << ISP_LSC_FRAME_INT_ST_S)
+#define ISP_LSC_FRAME_INT_ST_V  0x00000001U
+#define ISP_LSC_FRAME_INT_ST_S  16
+/** ISP_DPC_FRAME_INT_ST : RO; bitpos: [17]; default: 0;
+ *  the masked interrupt status of dpc frame done
+ */
+#define ISP_DPC_FRAME_INT_ST    (BIT(17))
+#define ISP_DPC_FRAME_INT_ST_M  (ISP_DPC_FRAME_INT_ST_V << ISP_DPC_FRAME_INT_ST_S)
+#define ISP_DPC_FRAME_INT_ST_V  0x00000001U
+#define ISP_DPC_FRAME_INT_ST_S  17
+/** ISP_BF_FRAME_INT_ST : RO; bitpos: [18]; default: 0;
+ *  the masked interrupt status of bf frame done
+ */
+#define ISP_BF_FRAME_INT_ST    (BIT(18))
+#define ISP_BF_FRAME_INT_ST_M  (ISP_BF_FRAME_INT_ST_V << ISP_BF_FRAME_INT_ST_S)
+#define ISP_BF_FRAME_INT_ST_V  0x00000001U
+#define ISP_BF_FRAME_INT_ST_S  18
+/** ISP_DEMOSAIC_FRAME_INT_ST : RO; bitpos: [19]; default: 0;
+ *  the masked interrupt status of demosaic frame done
+ */
+#define ISP_DEMOSAIC_FRAME_INT_ST    (BIT(19))
+#define ISP_DEMOSAIC_FRAME_INT_ST_M  (ISP_DEMOSAIC_FRAME_INT_ST_V << ISP_DEMOSAIC_FRAME_INT_ST_S)
+#define ISP_DEMOSAIC_FRAME_INT_ST_V  0x00000001U
+#define ISP_DEMOSAIC_FRAME_INT_ST_S  19
+/** ISP_MEDIAN_FRAME_INT_ST : RO; bitpos: [20]; default: 0;
+ *  the masked interrupt status of median frame done
+ */
+#define ISP_MEDIAN_FRAME_INT_ST    (BIT(20))
+#define ISP_MEDIAN_FRAME_INT_ST_M  (ISP_MEDIAN_FRAME_INT_ST_V << ISP_MEDIAN_FRAME_INT_ST_S)
+#define ISP_MEDIAN_FRAME_INT_ST_V  0x00000001U
+#define ISP_MEDIAN_FRAME_INT_ST_S  20
+/** ISP_CCM_FRAME_INT_ST : RO; bitpos: [21]; default: 0;
+ *  the masked interrupt status of ccm frame done
+ */
+#define ISP_CCM_FRAME_INT_ST    (BIT(21))
+#define ISP_CCM_FRAME_INT_ST_M  (ISP_CCM_FRAME_INT_ST_V << ISP_CCM_FRAME_INT_ST_S)
+#define ISP_CCM_FRAME_INT_ST_V  0x00000001U
+#define ISP_CCM_FRAME_INT_ST_S  21
+/** ISP_GAMMA_FRAME_INT_ST : RO; bitpos: [22]; default: 0;
+ *  the masked interrupt status of gamma frame done
+ */
+#define ISP_GAMMA_FRAME_INT_ST    (BIT(22))
+#define ISP_GAMMA_FRAME_INT_ST_M  (ISP_GAMMA_FRAME_INT_ST_V << ISP_GAMMA_FRAME_INT_ST_S)
+#define ISP_GAMMA_FRAME_INT_ST_V  0x00000001U
+#define ISP_GAMMA_FRAME_INT_ST_S  22
+/** ISP_RGB2YUV_FRAME_INT_ST : RO; bitpos: [23]; default: 0;
+ *  the masked interrupt status of rgb2yuv frame done
+ */
+#define ISP_RGB2YUV_FRAME_INT_ST    (BIT(23))
+#define ISP_RGB2YUV_FRAME_INT_ST_M  (ISP_RGB2YUV_FRAME_INT_ST_V << ISP_RGB2YUV_FRAME_INT_ST_S)
+#define ISP_RGB2YUV_FRAME_INT_ST_V  0x00000001U
+#define ISP_RGB2YUV_FRAME_INT_ST_S  23
+/** ISP_SHARP_FRAME_INT_ST : RO; bitpos: [24]; default: 0;
+ *  the masked interrupt status of sharp frame done
+ */
+#define ISP_SHARP_FRAME_INT_ST    (BIT(24))
+#define ISP_SHARP_FRAME_INT_ST_M  (ISP_SHARP_FRAME_INT_ST_V << ISP_SHARP_FRAME_INT_ST_S)
+#define ISP_SHARP_FRAME_INT_ST_V  0x00000001U
+#define ISP_SHARP_FRAME_INT_ST_S  24
+/** ISP_COLOR_FRAME_INT_ST : RO; bitpos: [25]; default: 0;
+ *  the masked interrupt status of color frame done
+ */
+#define ISP_COLOR_FRAME_INT_ST    (BIT(25))
+#define ISP_COLOR_FRAME_INT_ST_M  (ISP_COLOR_FRAME_INT_ST_V << ISP_COLOR_FRAME_INT_ST_S)
+#define ISP_COLOR_FRAME_INT_ST_V  0x00000001U
+#define ISP_COLOR_FRAME_INT_ST_S  25
+/** ISP_YUV2RGB_FRAME_INT_ST : RO; bitpos: [26]; default: 0;
+ *  the masked interrupt status of yuv2rgb frame done
+ */
+#define ISP_YUV2RGB_FRAME_INT_ST    (BIT(26))
+#define ISP_YUV2RGB_FRAME_INT_ST_M  (ISP_YUV2RGB_FRAME_INT_ST_V << ISP_YUV2RGB_FRAME_INT_ST_S)
+#define ISP_YUV2RGB_FRAME_INT_ST_V  0x00000001U
+#define ISP_YUV2RGB_FRAME_INT_ST_S  26
+/** ISP_TAIL_IDI_FRAME_INT_ST : RO; bitpos: [27]; default: 0;
+ *  the masked interrupt status of isp_tail idi frame_end
+ */
+#define ISP_TAIL_IDI_FRAME_INT_ST    (BIT(27))
+#define ISP_TAIL_IDI_FRAME_INT_ST_M  (ISP_TAIL_IDI_FRAME_INT_ST_V << ISP_TAIL_IDI_FRAME_INT_ST_S)
+#define ISP_TAIL_IDI_FRAME_INT_ST_V  0x00000001U
+#define ISP_TAIL_IDI_FRAME_INT_ST_S  27
+/** ISP_HEADER_IDI_FRAME_INT_ST : RO; bitpos: [28]; default: 0;
+ *  the masked interrupt status of real input frame end of isp_input
+ */
+#define ISP_HEADER_IDI_FRAME_INT_ST    (BIT(28))
+#define ISP_HEADER_IDI_FRAME_INT_ST_M  (ISP_HEADER_IDI_FRAME_INT_ST_V << ISP_HEADER_IDI_FRAME_INT_ST_S)
+#define ISP_HEADER_IDI_FRAME_INT_ST_V  0x00000001U
+#define ISP_HEADER_IDI_FRAME_INT_ST_S  28
+/** ISP_CROP_FRAME_INT_ST : RO; bitpos: [29]; default: 0;
+ *  the masked interrupt status of crop frame done
+ */
+#define ISP_CROP_FRAME_INT_ST    (BIT(29))
+#define ISP_CROP_FRAME_INT_ST_M  (ISP_CROP_FRAME_INT_ST_V << ISP_CROP_FRAME_INT_ST_S)
+#define ISP_CROP_FRAME_INT_ST_V  0x00000001U
+#define ISP_CROP_FRAME_INT_ST_S  29
+/** ISP_WBG_FRAME_INT_ST : RO; bitpos: [30]; default: 0;
+ *  the masked interrupt status of wbg frame done
+ */
+#define ISP_WBG_FRAME_INT_ST    (BIT(30))
+#define ISP_WBG_FRAME_INT_ST_M  (ISP_WBG_FRAME_INT_ST_V << ISP_WBG_FRAME_INT_ST_S)
+#define ISP_WBG_FRAME_INT_ST_V  0x00000001U
+#define ISP_WBG_FRAME_INT_ST_S  30
+/** ISP_CROP_ERR_INT_ST : RO; bitpos: [31]; default: 0;
+ *  the masked interrupt status of crop error
+ */
+#define ISP_CROP_ERR_INT_ST    (BIT(31))
+#define ISP_CROP_ERR_INT_ST_M  (ISP_CROP_ERR_INT_ST_V << ISP_CROP_ERR_INT_ST_S)
+#define ISP_CROP_ERR_INT_ST_V  0x00000001U
+#define ISP_CROP_ERR_INT_ST_S  31
+
+/** ISP_INT_ENA_REG register
+ *  interrupt enable register
+ */
+#define ISP_INT_ENA_REG (DR_REG_ISP_BASE + 0x6c)
+/** ISP_ISP_DATA_TYPE_ERR_INT_ENA : R/W; bitpos: [0]; default: 1;
+ *  write 1 to enable input data type error
+ */
+#define ISP_ISP_DATA_TYPE_ERR_INT_ENA    (BIT(0))
+#define ISP_ISP_DATA_TYPE_ERR_INT_ENA_M  (ISP_ISP_DATA_TYPE_ERR_INT_ENA_V << ISP_ISP_DATA_TYPE_ERR_INT_ENA_S)
+#define ISP_ISP_DATA_TYPE_ERR_INT_ENA_V  0x00000001U
+#define ISP_ISP_DATA_TYPE_ERR_INT_ENA_S  0
+/** ISP_ISP_ASYNC_FIFO_OVF_INT_ENA : R/W; bitpos: [1]; default: 1;
+ *  write 1 to enable isp input fifo overflow
+ */
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_ENA    (BIT(1))
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_ENA_M  (ISP_ISP_ASYNC_FIFO_OVF_INT_ENA_V << ISP_ISP_ASYNC_FIFO_OVF_INT_ENA_S)
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_ENA_V  0x00000001U
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_ENA_S  1
+/** ISP_ISP_BUF_FULL_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  write 1 to enable isp input buffer full
+ */
+#define ISP_ISP_BUF_FULL_INT_ENA    (BIT(2))
+#define ISP_ISP_BUF_FULL_INT_ENA_M  (ISP_ISP_BUF_FULL_INT_ENA_V << ISP_ISP_BUF_FULL_INT_ENA_S)
+#define ISP_ISP_BUF_FULL_INT_ENA_V  0x00000001U
+#define ISP_ISP_BUF_FULL_INT_ENA_S  2
+/** ISP_ISP_HVNUM_SETTING_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  write 1 to enable hnum and vnum setting format error
+ */
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_ENA    (BIT(3))
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_ENA_M  (ISP_ISP_HVNUM_SETTING_ERR_INT_ENA_V << ISP_ISP_HVNUM_SETTING_ERR_INT_ENA_S)
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_ENA_V  0x00000001U
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_ENA_S  3
+/** ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  write 1 to enable setting invalid reg_data_type
+ */
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA    (BIT(4))
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_M  (ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_V << ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_S)
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_V  0x00000001U
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_S  4
+/** ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  write 1 to enable hnum setting unmatch with mipi input
+ */
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA    (BIT(5))
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA_M  (ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA_V << ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA_S)
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA_V  0x00000001U
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA_S  5
+/** ISP_DPC_CHECK_DONE_INT_ENA : R/W; bitpos: [6]; default: 1;
+ *  write 1 to enable dpc check done
+ */
+#define ISP_DPC_CHECK_DONE_INT_ENA    (BIT(6))
+#define ISP_DPC_CHECK_DONE_INT_ENA_M  (ISP_DPC_CHECK_DONE_INT_ENA_V << ISP_DPC_CHECK_DONE_INT_ENA_S)
+#define ISP_DPC_CHECK_DONE_INT_ENA_V  0x00000001U
+#define ISP_DPC_CHECK_DONE_INT_ENA_S  6
+/** ISP_GAMMA_XCOORD_ERR_INT_ENA : R/W; bitpos: [7]; default: 1;
+ *  write 1 to enable gamma setting error
+ */
+#define ISP_GAMMA_XCOORD_ERR_INT_ENA    (BIT(7))
+#define ISP_GAMMA_XCOORD_ERR_INT_ENA_M  (ISP_GAMMA_XCOORD_ERR_INT_ENA_V << ISP_GAMMA_XCOORD_ERR_INT_ENA_S)
+#define ISP_GAMMA_XCOORD_ERR_INT_ENA_V  0x00000001U
+#define ISP_GAMMA_XCOORD_ERR_INT_ENA_S  7
+/** ISP_AE_MONITOR_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  write 1 to enable ae monitor
+ */
+#define ISP_AE_MONITOR_INT_ENA    (BIT(8))
+#define ISP_AE_MONITOR_INT_ENA_M  (ISP_AE_MONITOR_INT_ENA_V << ISP_AE_MONITOR_INT_ENA_S)
+#define ISP_AE_MONITOR_INT_ENA_V  0x00000001U
+#define ISP_AE_MONITOR_INT_ENA_S  8
+/** ISP_AE_FRAME_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  write 1 to enable ae
+ */
+#define ISP_AE_FRAME_DONE_INT_ENA    (BIT(9))
+#define ISP_AE_FRAME_DONE_INT_ENA_M  (ISP_AE_FRAME_DONE_INT_ENA_V << ISP_AE_FRAME_DONE_INT_ENA_S)
+#define ISP_AE_FRAME_DONE_INT_ENA_V  0x00000001U
+#define ISP_AE_FRAME_DONE_INT_ENA_S  9
+/** ISP_AF_FDONE_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  write 1 to enable af statistic
+ */
+#define ISP_AF_FDONE_INT_ENA    (BIT(10))
+#define ISP_AF_FDONE_INT_ENA_M  (ISP_AF_FDONE_INT_ENA_V << ISP_AF_FDONE_INT_ENA_S)
+#define ISP_AF_FDONE_INT_ENA_V  0x00000001U
+#define ISP_AF_FDONE_INT_ENA_S  10
+/** ISP_AF_ENV_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  write 1 to enable af monitor
+ */
+#define ISP_AF_ENV_INT_ENA    (BIT(11))
+#define ISP_AF_ENV_INT_ENA_M  (ISP_AF_ENV_INT_ENA_V << ISP_AF_ENV_INT_ENA_S)
+#define ISP_AF_ENV_INT_ENA_V  0x00000001U
+#define ISP_AF_ENV_INT_ENA_S  11
+/** ISP_AWB_FDONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  write 1 to enable awb
+ */
+#define ISP_AWB_FDONE_INT_ENA    (BIT(12))
+#define ISP_AWB_FDONE_INT_ENA_M  (ISP_AWB_FDONE_INT_ENA_V << ISP_AWB_FDONE_INT_ENA_S)
+#define ISP_AWB_FDONE_INT_ENA_V  0x00000001U
+#define ISP_AWB_FDONE_INT_ENA_S  12
+/** ISP_HIST_FDONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  write 1 to enable histogram
+ */
+#define ISP_HIST_FDONE_INT_ENA    (BIT(13))
+#define ISP_HIST_FDONE_INT_ENA_M  (ISP_HIST_FDONE_INT_ENA_V << ISP_HIST_FDONE_INT_ENA_S)
+#define ISP_HIST_FDONE_INT_ENA_V  0x00000001U
+#define ISP_HIST_FDONE_INT_ENA_S  13
+/** ISP_FRAME_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  write 1 to enable isp frame end
+ */
+#define ISP_FRAME_INT_ENA    (BIT(14))
+#define ISP_FRAME_INT_ENA_M  (ISP_FRAME_INT_ENA_V << ISP_FRAME_INT_ENA_S)
+#define ISP_FRAME_INT_ENA_V  0x00000001U
+#define ISP_FRAME_INT_ENA_S  14
+/** ISP_BLC_FRAME_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  write 1 to enable blc frame done
+ */
+#define ISP_BLC_FRAME_INT_ENA    (BIT(15))
+#define ISP_BLC_FRAME_INT_ENA_M  (ISP_BLC_FRAME_INT_ENA_V << ISP_BLC_FRAME_INT_ENA_S)
+#define ISP_BLC_FRAME_INT_ENA_V  0x00000001U
+#define ISP_BLC_FRAME_INT_ENA_S  15
+/** ISP_LSC_FRAME_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  write 1 to enable lsc frame done
+ */
+#define ISP_LSC_FRAME_INT_ENA    (BIT(16))
+#define ISP_LSC_FRAME_INT_ENA_M  (ISP_LSC_FRAME_INT_ENA_V << ISP_LSC_FRAME_INT_ENA_S)
+#define ISP_LSC_FRAME_INT_ENA_V  0x00000001U
+#define ISP_LSC_FRAME_INT_ENA_S  16
+/** ISP_DPC_FRAME_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  write 1 to enable dpc frame done
+ */
+#define ISP_DPC_FRAME_INT_ENA    (BIT(17))
+#define ISP_DPC_FRAME_INT_ENA_M  (ISP_DPC_FRAME_INT_ENA_V << ISP_DPC_FRAME_INT_ENA_S)
+#define ISP_DPC_FRAME_INT_ENA_V  0x00000001U
+#define ISP_DPC_FRAME_INT_ENA_S  17
+/** ISP_BF_FRAME_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  write 1 to enable bf frame done
+ */
+#define ISP_BF_FRAME_INT_ENA    (BIT(18))
+#define ISP_BF_FRAME_INT_ENA_M  (ISP_BF_FRAME_INT_ENA_V << ISP_BF_FRAME_INT_ENA_S)
+#define ISP_BF_FRAME_INT_ENA_V  0x00000001U
+#define ISP_BF_FRAME_INT_ENA_S  18
+/** ISP_DEMOSAIC_FRAME_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  write 1 to enable demosaic frame done
+ */
+#define ISP_DEMOSAIC_FRAME_INT_ENA    (BIT(19))
+#define ISP_DEMOSAIC_FRAME_INT_ENA_M  (ISP_DEMOSAIC_FRAME_INT_ENA_V << ISP_DEMOSAIC_FRAME_INT_ENA_S)
+#define ISP_DEMOSAIC_FRAME_INT_ENA_V  0x00000001U
+#define ISP_DEMOSAIC_FRAME_INT_ENA_S  19
+/** ISP_MEDIAN_FRAME_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  write 1 to enable median frame done
+ */
+#define ISP_MEDIAN_FRAME_INT_ENA    (BIT(20))
+#define ISP_MEDIAN_FRAME_INT_ENA_M  (ISP_MEDIAN_FRAME_INT_ENA_V << ISP_MEDIAN_FRAME_INT_ENA_S)
+#define ISP_MEDIAN_FRAME_INT_ENA_V  0x00000001U
+#define ISP_MEDIAN_FRAME_INT_ENA_S  20
+/** ISP_CCM_FRAME_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  write 1 to enable ccm frame done
+ */
+#define ISP_CCM_FRAME_INT_ENA    (BIT(21))
+#define ISP_CCM_FRAME_INT_ENA_M  (ISP_CCM_FRAME_INT_ENA_V << ISP_CCM_FRAME_INT_ENA_S)
+#define ISP_CCM_FRAME_INT_ENA_V  0x00000001U
+#define ISP_CCM_FRAME_INT_ENA_S  21
+/** ISP_GAMMA_FRAME_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  write 1 to enable gamma frame done
+ */
+#define ISP_GAMMA_FRAME_INT_ENA    (BIT(22))
+#define ISP_GAMMA_FRAME_INT_ENA_M  (ISP_GAMMA_FRAME_INT_ENA_V << ISP_GAMMA_FRAME_INT_ENA_S)
+#define ISP_GAMMA_FRAME_INT_ENA_V  0x00000001U
+#define ISP_GAMMA_FRAME_INT_ENA_S  22
+/** ISP_RGB2YUV_FRAME_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  write 1 to enable rgb2yuv frame done
+ */
+#define ISP_RGB2YUV_FRAME_INT_ENA    (BIT(23))
+#define ISP_RGB2YUV_FRAME_INT_ENA_M  (ISP_RGB2YUV_FRAME_INT_ENA_V << ISP_RGB2YUV_FRAME_INT_ENA_S)
+#define ISP_RGB2YUV_FRAME_INT_ENA_V  0x00000001U
+#define ISP_RGB2YUV_FRAME_INT_ENA_S  23
+/** ISP_SHARP_FRAME_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  write 1 to enable sharp frame done
+ */
+#define ISP_SHARP_FRAME_INT_ENA    (BIT(24))
+#define ISP_SHARP_FRAME_INT_ENA_M  (ISP_SHARP_FRAME_INT_ENA_V << ISP_SHARP_FRAME_INT_ENA_S)
+#define ISP_SHARP_FRAME_INT_ENA_V  0x00000001U
+#define ISP_SHARP_FRAME_INT_ENA_S  24
+/** ISP_COLOR_FRAME_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  write 1 to enable color frame done
+ */
+#define ISP_COLOR_FRAME_INT_ENA    (BIT(25))
+#define ISP_COLOR_FRAME_INT_ENA_M  (ISP_COLOR_FRAME_INT_ENA_V << ISP_COLOR_FRAME_INT_ENA_S)
+#define ISP_COLOR_FRAME_INT_ENA_V  0x00000001U
+#define ISP_COLOR_FRAME_INT_ENA_S  25
+/** ISP_YUV2RGB_FRAME_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  write 1 to enable yuv2rgb frame done
+ */
+#define ISP_YUV2RGB_FRAME_INT_ENA    (BIT(26))
+#define ISP_YUV2RGB_FRAME_INT_ENA_M  (ISP_YUV2RGB_FRAME_INT_ENA_V << ISP_YUV2RGB_FRAME_INT_ENA_S)
+#define ISP_YUV2RGB_FRAME_INT_ENA_V  0x00000001U
+#define ISP_YUV2RGB_FRAME_INT_ENA_S  26
+/** ISP_TAIL_IDI_FRAME_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  write 1 to enable isp_tail idi frame_end
+ */
+#define ISP_TAIL_IDI_FRAME_INT_ENA    (BIT(27))
+#define ISP_TAIL_IDI_FRAME_INT_ENA_M  (ISP_TAIL_IDI_FRAME_INT_ENA_V << ISP_TAIL_IDI_FRAME_INT_ENA_S)
+#define ISP_TAIL_IDI_FRAME_INT_ENA_V  0x00000001U
+#define ISP_TAIL_IDI_FRAME_INT_ENA_S  27
+/** ISP_HEADER_IDI_FRAME_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  write 1 to enable real input frame end of isp_input
+ */
+#define ISP_HEADER_IDI_FRAME_INT_ENA    (BIT(28))
+#define ISP_HEADER_IDI_FRAME_INT_ENA_M  (ISP_HEADER_IDI_FRAME_INT_ENA_V << ISP_HEADER_IDI_FRAME_INT_ENA_S)
+#define ISP_HEADER_IDI_FRAME_INT_ENA_V  0x00000001U
+#define ISP_HEADER_IDI_FRAME_INT_ENA_S  28
+/** ISP_CROP_FRAME_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  write 1 to enable crop frame done
+ */
+#define ISP_CROP_FRAME_INT_ENA    (BIT(29))
+#define ISP_CROP_FRAME_INT_ENA_M  (ISP_CROP_FRAME_INT_ENA_V << ISP_CROP_FRAME_INT_ENA_S)
+#define ISP_CROP_FRAME_INT_ENA_V  0x00000001U
+#define ISP_CROP_FRAME_INT_ENA_S  29
+/** ISP_WBG_FRAME_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  write 1 to enable wbg frame done
+ */
+#define ISP_WBG_FRAME_INT_ENA    (BIT(30))
+#define ISP_WBG_FRAME_INT_ENA_M  (ISP_WBG_FRAME_INT_ENA_V << ISP_WBG_FRAME_INT_ENA_S)
+#define ISP_WBG_FRAME_INT_ENA_V  0x00000001U
+#define ISP_WBG_FRAME_INT_ENA_S  30
+/** ISP_CROP_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  write 1 to enable crop error
+ */
+#define ISP_CROP_ERR_INT_ENA    (BIT(31))
+#define ISP_CROP_ERR_INT_ENA_M  (ISP_CROP_ERR_INT_ENA_V << ISP_CROP_ERR_INT_ENA_S)
+#define ISP_CROP_ERR_INT_ENA_V  0x00000001U
+#define ISP_CROP_ERR_INT_ENA_S  31
+
+/** ISP_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define ISP_INT_CLR_REG (DR_REG_ISP_BASE + 0x70)
+/** ISP_ISP_DATA_TYPE_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  write 1 to clear input data type error
+ */
+#define ISP_ISP_DATA_TYPE_ERR_INT_CLR    (BIT(0))
+#define ISP_ISP_DATA_TYPE_ERR_INT_CLR_M  (ISP_ISP_DATA_TYPE_ERR_INT_CLR_V << ISP_ISP_DATA_TYPE_ERR_INT_CLR_S)
+#define ISP_ISP_DATA_TYPE_ERR_INT_CLR_V  0x00000001U
+#define ISP_ISP_DATA_TYPE_ERR_INT_CLR_S  0
+/** ISP_ISP_ASYNC_FIFO_OVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  write 1 to clear isp input fifo overflow
+ */
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_CLR    (BIT(1))
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_CLR_M  (ISP_ISP_ASYNC_FIFO_OVF_INT_CLR_V << ISP_ISP_ASYNC_FIFO_OVF_INT_CLR_S)
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_CLR_V  0x00000001U
+#define ISP_ISP_ASYNC_FIFO_OVF_INT_CLR_S  1
+/** ISP_ISP_BUF_FULL_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  write 1 to clear isp input buffer full
+ */
+#define ISP_ISP_BUF_FULL_INT_CLR    (BIT(2))
+#define ISP_ISP_BUF_FULL_INT_CLR_M  (ISP_ISP_BUF_FULL_INT_CLR_V << ISP_ISP_BUF_FULL_INT_CLR_S)
+#define ISP_ISP_BUF_FULL_INT_CLR_V  0x00000001U
+#define ISP_ISP_BUF_FULL_INT_CLR_S  2
+/** ISP_ISP_HVNUM_SETTING_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  write 1 to clear hnum and vnum setting format error
+ */
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_CLR    (BIT(3))
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_CLR_M  (ISP_ISP_HVNUM_SETTING_ERR_INT_CLR_V << ISP_ISP_HVNUM_SETTING_ERR_INT_CLR_S)
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_CLR_V  0x00000001U
+#define ISP_ISP_HVNUM_SETTING_ERR_INT_CLR_S  3
+/** ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  write 1 to clear setting invalid reg_data_type
+ */
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR    (BIT(4))
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_M  (ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_V << ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_S)
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_V  0x00000001U
+#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_S  4
+/** ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  write 1 to clear hnum setting unmatch with mipi input
+ */
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR    (BIT(5))
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR_M  (ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR_V << ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR_S)
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR_V  0x00000001U
+#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR_S  5
+/** ISP_DPC_CHECK_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  write 1 to clear dpc check done
+ */
+#define ISP_DPC_CHECK_DONE_INT_CLR    (BIT(6))
+#define ISP_DPC_CHECK_DONE_INT_CLR_M  (ISP_DPC_CHECK_DONE_INT_CLR_V << ISP_DPC_CHECK_DONE_INT_CLR_S)
+#define ISP_DPC_CHECK_DONE_INT_CLR_V  0x00000001U
+#define ISP_DPC_CHECK_DONE_INT_CLR_S  6
+/** ISP_GAMMA_XCOORD_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  write 1 to clear gamma setting error
+ */
+#define ISP_GAMMA_XCOORD_ERR_INT_CLR    (BIT(7))
+#define ISP_GAMMA_XCOORD_ERR_INT_CLR_M  (ISP_GAMMA_XCOORD_ERR_INT_CLR_V << ISP_GAMMA_XCOORD_ERR_INT_CLR_S)
+#define ISP_GAMMA_XCOORD_ERR_INT_CLR_V  0x00000001U
+#define ISP_GAMMA_XCOORD_ERR_INT_CLR_S  7
+/** ISP_AE_MONITOR_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  write 1 to clear ae monitor
+ */
+#define ISP_AE_MONITOR_INT_CLR    (BIT(8))
+#define ISP_AE_MONITOR_INT_CLR_M  (ISP_AE_MONITOR_INT_CLR_V << ISP_AE_MONITOR_INT_CLR_S)
+#define ISP_AE_MONITOR_INT_CLR_V  0x00000001U
+#define ISP_AE_MONITOR_INT_CLR_S  8
+/** ISP_AE_FRAME_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  write 1 to clear ae
+ */
+#define ISP_AE_FRAME_DONE_INT_CLR    (BIT(9))
+#define ISP_AE_FRAME_DONE_INT_CLR_M  (ISP_AE_FRAME_DONE_INT_CLR_V << ISP_AE_FRAME_DONE_INT_CLR_S)
+#define ISP_AE_FRAME_DONE_INT_CLR_V  0x00000001U
+#define ISP_AE_FRAME_DONE_INT_CLR_S  9
+/** ISP_AF_FDONE_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  write 1 to clear af statistic
+ */
+#define ISP_AF_FDONE_INT_CLR    (BIT(10))
+#define ISP_AF_FDONE_INT_CLR_M  (ISP_AF_FDONE_INT_CLR_V << ISP_AF_FDONE_INT_CLR_S)
+#define ISP_AF_FDONE_INT_CLR_V  0x00000001U
+#define ISP_AF_FDONE_INT_CLR_S  10
+/** ISP_AF_ENV_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  write 1 to clear af monitor
+ */
+#define ISP_AF_ENV_INT_CLR    (BIT(11))
+#define ISP_AF_ENV_INT_CLR_M  (ISP_AF_ENV_INT_CLR_V << ISP_AF_ENV_INT_CLR_S)
+#define ISP_AF_ENV_INT_CLR_V  0x00000001U
+#define ISP_AF_ENV_INT_CLR_S  11
+/** ISP_AWB_FDONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  write 1 to clear awb
+ */
+#define ISP_AWB_FDONE_INT_CLR    (BIT(12))
+#define ISP_AWB_FDONE_INT_CLR_M  (ISP_AWB_FDONE_INT_CLR_V << ISP_AWB_FDONE_INT_CLR_S)
+#define ISP_AWB_FDONE_INT_CLR_V  0x00000001U
+#define ISP_AWB_FDONE_INT_CLR_S  12
+/** ISP_HIST_FDONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  write 1 to clear histogram
+ */
+#define ISP_HIST_FDONE_INT_CLR    (BIT(13))
+#define ISP_HIST_FDONE_INT_CLR_M  (ISP_HIST_FDONE_INT_CLR_V << ISP_HIST_FDONE_INT_CLR_S)
+#define ISP_HIST_FDONE_INT_CLR_V  0x00000001U
+#define ISP_HIST_FDONE_INT_CLR_S  13
+/** ISP_FRAME_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  write 1 to clear isp frame end
+ */
+#define ISP_FRAME_INT_CLR    (BIT(14))
+#define ISP_FRAME_INT_CLR_M  (ISP_FRAME_INT_CLR_V << ISP_FRAME_INT_CLR_S)
+#define ISP_FRAME_INT_CLR_V  0x00000001U
+#define ISP_FRAME_INT_CLR_S  14
+/** ISP_BLC_FRAME_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  write 1 to clear blc frame done
+ */
+#define ISP_BLC_FRAME_INT_CLR    (BIT(15))
+#define ISP_BLC_FRAME_INT_CLR_M  (ISP_BLC_FRAME_INT_CLR_V << ISP_BLC_FRAME_INT_CLR_S)
+#define ISP_BLC_FRAME_INT_CLR_V  0x00000001U
+#define ISP_BLC_FRAME_INT_CLR_S  15
+/** ISP_LSC_FRAME_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  write 1 to clear lsc frame done
+ */
+#define ISP_LSC_FRAME_INT_CLR    (BIT(16))
+#define ISP_LSC_FRAME_INT_CLR_M  (ISP_LSC_FRAME_INT_CLR_V << ISP_LSC_FRAME_INT_CLR_S)
+#define ISP_LSC_FRAME_INT_CLR_V  0x00000001U
+#define ISP_LSC_FRAME_INT_CLR_S  16
+/** ISP_DPC_FRAME_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  write 1 to clear dpc frame done
+ */
+#define ISP_DPC_FRAME_INT_CLR    (BIT(17))
+#define ISP_DPC_FRAME_INT_CLR_M  (ISP_DPC_FRAME_INT_CLR_V << ISP_DPC_FRAME_INT_CLR_S)
+#define ISP_DPC_FRAME_INT_CLR_V  0x00000001U
+#define ISP_DPC_FRAME_INT_CLR_S  17
+/** ISP_BF_FRAME_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  write 1 to clear bf frame done
+ */
+#define ISP_BF_FRAME_INT_CLR    (BIT(18))
+#define ISP_BF_FRAME_INT_CLR_M  (ISP_BF_FRAME_INT_CLR_V << ISP_BF_FRAME_INT_CLR_S)
+#define ISP_BF_FRAME_INT_CLR_V  0x00000001U
+#define ISP_BF_FRAME_INT_CLR_S  18
+/** ISP_DEMOSAIC_FRAME_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  write 1 to clear demosaic frame done
+ */
+#define ISP_DEMOSAIC_FRAME_INT_CLR    (BIT(19))
+#define ISP_DEMOSAIC_FRAME_INT_CLR_M  (ISP_DEMOSAIC_FRAME_INT_CLR_V << ISP_DEMOSAIC_FRAME_INT_CLR_S)
+#define ISP_DEMOSAIC_FRAME_INT_CLR_V  0x00000001U
+#define ISP_DEMOSAIC_FRAME_INT_CLR_S  19
+/** ISP_MEDIAN_FRAME_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  write 1 to clear median frame done
+ */
+#define ISP_MEDIAN_FRAME_INT_CLR    (BIT(20))
+#define ISP_MEDIAN_FRAME_INT_CLR_M  (ISP_MEDIAN_FRAME_INT_CLR_V << ISP_MEDIAN_FRAME_INT_CLR_S)
+#define ISP_MEDIAN_FRAME_INT_CLR_V  0x00000001U
+#define ISP_MEDIAN_FRAME_INT_CLR_S  20
+/** ISP_CCM_FRAME_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  write 1 to clear ccm frame done
+ */
+#define ISP_CCM_FRAME_INT_CLR    (BIT(21))
+#define ISP_CCM_FRAME_INT_CLR_M  (ISP_CCM_FRAME_INT_CLR_V << ISP_CCM_FRAME_INT_CLR_S)
+#define ISP_CCM_FRAME_INT_CLR_V  0x00000001U
+#define ISP_CCM_FRAME_INT_CLR_S  21
+/** ISP_GAMMA_FRAME_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  write 1 to clear gamma frame done
+ */
+#define ISP_GAMMA_FRAME_INT_CLR    (BIT(22))
+#define ISP_GAMMA_FRAME_INT_CLR_M  (ISP_GAMMA_FRAME_INT_CLR_V << ISP_GAMMA_FRAME_INT_CLR_S)
+#define ISP_GAMMA_FRAME_INT_CLR_V  0x00000001U
+#define ISP_GAMMA_FRAME_INT_CLR_S  22
+/** ISP_RGB2YUV_FRAME_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  write 1 to clear rgb2yuv frame done
+ */
+#define ISP_RGB2YUV_FRAME_INT_CLR    (BIT(23))
+#define ISP_RGB2YUV_FRAME_INT_CLR_M  (ISP_RGB2YUV_FRAME_INT_CLR_V << ISP_RGB2YUV_FRAME_INT_CLR_S)
+#define ISP_RGB2YUV_FRAME_INT_CLR_V  0x00000001U
+#define ISP_RGB2YUV_FRAME_INT_CLR_S  23
+/** ISP_SHARP_FRAME_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  write 1 to clear sharp frame done
+ */
+#define ISP_SHARP_FRAME_INT_CLR    (BIT(24))
+#define ISP_SHARP_FRAME_INT_CLR_M  (ISP_SHARP_FRAME_INT_CLR_V << ISP_SHARP_FRAME_INT_CLR_S)
+#define ISP_SHARP_FRAME_INT_CLR_V  0x00000001U
+#define ISP_SHARP_FRAME_INT_CLR_S  24
+/** ISP_COLOR_FRAME_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  write 1 to clear color frame done
+ */
+#define ISP_COLOR_FRAME_INT_CLR    (BIT(25))
+#define ISP_COLOR_FRAME_INT_CLR_M  (ISP_COLOR_FRAME_INT_CLR_V << ISP_COLOR_FRAME_INT_CLR_S)
+#define ISP_COLOR_FRAME_INT_CLR_V  0x00000001U
+#define ISP_COLOR_FRAME_INT_CLR_S  25
+/** ISP_YUV2RGB_FRAME_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  write 1 to clear yuv2rgb frame done
+ */
+#define ISP_YUV2RGB_FRAME_INT_CLR    (BIT(26))
+#define ISP_YUV2RGB_FRAME_INT_CLR_M  (ISP_YUV2RGB_FRAME_INT_CLR_V << ISP_YUV2RGB_FRAME_INT_CLR_S)
+#define ISP_YUV2RGB_FRAME_INT_CLR_V  0x00000001U
+#define ISP_YUV2RGB_FRAME_INT_CLR_S  26
+/** ISP_TAIL_IDI_FRAME_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  write 1 to clear isp_tail idi frame_end
+ */
+#define ISP_TAIL_IDI_FRAME_INT_CLR    (BIT(27))
+#define ISP_TAIL_IDI_FRAME_INT_CLR_M  (ISP_TAIL_IDI_FRAME_INT_CLR_V << ISP_TAIL_IDI_FRAME_INT_CLR_S)
+#define ISP_TAIL_IDI_FRAME_INT_CLR_V  0x00000001U
+#define ISP_TAIL_IDI_FRAME_INT_CLR_S  27
+/** ISP_HEADER_IDI_FRAME_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  write 1 to clear real input frame end of isp_input
+ */
+#define ISP_HEADER_IDI_FRAME_INT_CLR    (BIT(28))
+#define ISP_HEADER_IDI_FRAME_INT_CLR_M  (ISP_HEADER_IDI_FRAME_INT_CLR_V << ISP_HEADER_IDI_FRAME_INT_CLR_S)
+#define ISP_HEADER_IDI_FRAME_INT_CLR_V  0x00000001U
+#define ISP_HEADER_IDI_FRAME_INT_CLR_S  28
+/** ISP_CROP_FRAME_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  write 1 to clear crop frame done
+ */
+#define ISP_CROP_FRAME_INT_CLR    (BIT(29))
+#define ISP_CROP_FRAME_INT_CLR_M  (ISP_CROP_FRAME_INT_CLR_V << ISP_CROP_FRAME_INT_CLR_S)
+#define ISP_CROP_FRAME_INT_CLR_V  0x00000001U
+#define ISP_CROP_FRAME_INT_CLR_S  29
+/** ISP_WBG_FRAME_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  write 1 to clear wbg frame done
+ */
+#define ISP_WBG_FRAME_INT_CLR    (BIT(30))
+#define ISP_WBG_FRAME_INT_CLR_M  (ISP_WBG_FRAME_INT_CLR_V << ISP_WBG_FRAME_INT_CLR_S)
+#define ISP_WBG_FRAME_INT_CLR_V  0x00000001U
+#define ISP_WBG_FRAME_INT_CLR_S  30
+/** ISP_CROP_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  write 1 to clear crop error
+ */
+#define ISP_CROP_ERR_INT_CLR    (BIT(31))
+#define ISP_CROP_ERR_INT_CLR_M  (ISP_CROP_ERR_INT_CLR_V << ISP_CROP_ERR_INT_CLR_S)
+#define ISP_CROP_ERR_INT_CLR_V  0x00000001U
+#define ISP_CROP_ERR_INT_CLR_S  31
+
+/** ISP_GAMMA_CTRL_REG register
+ *  gamma control register
+ */
+#define ISP_GAMMA_CTRL_REG (DR_REG_ISP_BASE + 0x74)
+/** ISP_GAMMA_UPDATE : R/W; bitpos: [0]; default: 0;
+ *  Indicates that gamma register configuration is complete
+ */
+#define ISP_GAMMA_UPDATE    (BIT(0))
+#define ISP_GAMMA_UPDATE_M  (ISP_GAMMA_UPDATE_V << ISP_GAMMA_UPDATE_S)
+#define ISP_GAMMA_UPDATE_V  0x00000001U
+#define ISP_GAMMA_UPDATE_S  0
+/** ISP_GAMMA_B_LAST_CORRECT : R/W; bitpos: [1]; default: 1;
+ *  this bit configures enable of last b segment correcction. 0: disable, 1: enable
+ */
+#define ISP_GAMMA_B_LAST_CORRECT    (BIT(1))
+#define ISP_GAMMA_B_LAST_CORRECT_M  (ISP_GAMMA_B_LAST_CORRECT_V << ISP_GAMMA_B_LAST_CORRECT_S)
+#define ISP_GAMMA_B_LAST_CORRECT_V  0x00000001U
+#define ISP_GAMMA_B_LAST_CORRECT_S  1
+/** ISP_GAMMA_G_LAST_CORRECT : R/W; bitpos: [2]; default: 1;
+ *  this bit configures enable of last g segment correcction. 0: disable, 1: enable
+ */
+#define ISP_GAMMA_G_LAST_CORRECT    (BIT(2))
+#define ISP_GAMMA_G_LAST_CORRECT_M  (ISP_GAMMA_G_LAST_CORRECT_V << ISP_GAMMA_G_LAST_CORRECT_S)
+#define ISP_GAMMA_G_LAST_CORRECT_V  0x00000001U
+#define ISP_GAMMA_G_LAST_CORRECT_S  2
+/** ISP_GAMMA_R_LAST_CORRECT : R/W; bitpos: [3]; default: 1;
+ *  this bit configures enable of last r segment correcction. 0: disable, 1: enable
+ */
+#define ISP_GAMMA_R_LAST_CORRECT    (BIT(3))
+#define ISP_GAMMA_R_LAST_CORRECT_M  (ISP_GAMMA_R_LAST_CORRECT_V << ISP_GAMMA_R_LAST_CORRECT_S)
+#define ISP_GAMMA_R_LAST_CORRECT_V  0x00000001U
+#define ISP_GAMMA_R_LAST_CORRECT_S  3
+
+/** ISP_GAMMA_RY1_REG register
+ *  point of Y-axis of r channel gamma curve register 1
+ */
+#define ISP_GAMMA_RY1_REG (DR_REG_ISP_BASE + 0x78)
+/** ISP_GAMMA_R_Y03 : R/W; bitpos: [7:0]; default: 64;
+ *  this field configures the point 3 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y03    0x000000FFU
+#define ISP_GAMMA_R_Y03_M  (ISP_GAMMA_R_Y03_V << ISP_GAMMA_R_Y03_S)
+#define ISP_GAMMA_R_Y03_V  0x000000FFU
+#define ISP_GAMMA_R_Y03_S  0
+/** ISP_GAMMA_R_Y02 : R/W; bitpos: [15:8]; default: 48;
+ *  this field configures the point 2 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y02    0x000000FFU
+#define ISP_GAMMA_R_Y02_M  (ISP_GAMMA_R_Y02_V << ISP_GAMMA_R_Y02_S)
+#define ISP_GAMMA_R_Y02_V  0x000000FFU
+#define ISP_GAMMA_R_Y02_S  8
+/** ISP_GAMMA_R_Y01 : R/W; bitpos: [23:16]; default: 32;
+ *  this field configures the point 1 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y01    0x000000FFU
+#define ISP_GAMMA_R_Y01_M  (ISP_GAMMA_R_Y01_V << ISP_GAMMA_R_Y01_S)
+#define ISP_GAMMA_R_Y01_V  0x000000FFU
+#define ISP_GAMMA_R_Y01_S  16
+/** ISP_GAMMA_R_Y00 : R/W; bitpos: [31:24]; default: 16;
+ *  this field configures the point 0 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y00    0x000000FFU
+#define ISP_GAMMA_R_Y00_M  (ISP_GAMMA_R_Y00_V << ISP_GAMMA_R_Y00_S)
+#define ISP_GAMMA_R_Y00_V  0x000000FFU
+#define ISP_GAMMA_R_Y00_S  24
+
+/** ISP_GAMMA_RY2_REG register
+ *  point of Y-axis of r channel gamma curve register 2
+ */
+#define ISP_GAMMA_RY2_REG (DR_REG_ISP_BASE + 0x7c)
+/** ISP_GAMMA_R_Y07 : R/W; bitpos: [7:0]; default: 128;
+ *  this field configures the point 7 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y07    0x000000FFU
+#define ISP_GAMMA_R_Y07_M  (ISP_GAMMA_R_Y07_V << ISP_GAMMA_R_Y07_S)
+#define ISP_GAMMA_R_Y07_V  0x000000FFU
+#define ISP_GAMMA_R_Y07_S  0
+/** ISP_GAMMA_R_Y06 : R/W; bitpos: [15:8]; default: 112;
+ *  this field configures the point 6 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y06    0x000000FFU
+#define ISP_GAMMA_R_Y06_M  (ISP_GAMMA_R_Y06_V << ISP_GAMMA_R_Y06_S)
+#define ISP_GAMMA_R_Y06_V  0x000000FFU
+#define ISP_GAMMA_R_Y06_S  8
+/** ISP_GAMMA_R_Y05 : R/W; bitpos: [23:16]; default: 96;
+ *  this field configures the point 5 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y05    0x000000FFU
+#define ISP_GAMMA_R_Y05_M  (ISP_GAMMA_R_Y05_V << ISP_GAMMA_R_Y05_S)
+#define ISP_GAMMA_R_Y05_V  0x000000FFU
+#define ISP_GAMMA_R_Y05_S  16
+/** ISP_GAMMA_R_Y04 : R/W; bitpos: [31:24]; default: 80;
+ *  this field configures the point 4 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y04    0x000000FFU
+#define ISP_GAMMA_R_Y04_M  (ISP_GAMMA_R_Y04_V << ISP_GAMMA_R_Y04_S)
+#define ISP_GAMMA_R_Y04_V  0x000000FFU
+#define ISP_GAMMA_R_Y04_S  24
+
+/** ISP_GAMMA_RY3_REG register
+ *  point of Y-axis of r channel gamma curve register 3
+ */
+#define ISP_GAMMA_RY3_REG (DR_REG_ISP_BASE + 0x80)
+/** ISP_GAMMA_R_Y0B : R/W; bitpos: [7:0]; default: 192;
+ *  this field configures the point 11 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y0B    0x000000FFU
+#define ISP_GAMMA_R_Y0B_M  (ISP_GAMMA_R_Y0B_V << ISP_GAMMA_R_Y0B_S)
+#define ISP_GAMMA_R_Y0B_V  0x000000FFU
+#define ISP_GAMMA_R_Y0B_S  0
+/** ISP_GAMMA_R_Y0A : R/W; bitpos: [15:8]; default: 176;
+ *  this field configures the point 10 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y0A    0x000000FFU
+#define ISP_GAMMA_R_Y0A_M  (ISP_GAMMA_R_Y0A_V << ISP_GAMMA_R_Y0A_S)
+#define ISP_GAMMA_R_Y0A_V  0x000000FFU
+#define ISP_GAMMA_R_Y0A_S  8
+/** ISP_GAMMA_R_Y09 : R/W; bitpos: [23:16]; default: 160;
+ *  this field configures the point 9 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y09    0x000000FFU
+#define ISP_GAMMA_R_Y09_M  (ISP_GAMMA_R_Y09_V << ISP_GAMMA_R_Y09_S)
+#define ISP_GAMMA_R_Y09_V  0x000000FFU
+#define ISP_GAMMA_R_Y09_S  16
+/** ISP_GAMMA_R_Y08 : R/W; bitpos: [31:24]; default: 144;
+ *  this field configures the point 8 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y08    0x000000FFU
+#define ISP_GAMMA_R_Y08_M  (ISP_GAMMA_R_Y08_V << ISP_GAMMA_R_Y08_S)
+#define ISP_GAMMA_R_Y08_V  0x000000FFU
+#define ISP_GAMMA_R_Y08_S  24
+
+/** ISP_GAMMA_RY4_REG register
+ *  point of Y-axis of r channel gamma curve register 4
+ */
+#define ISP_GAMMA_RY4_REG (DR_REG_ISP_BASE + 0x84)
+/** ISP_GAMMA_R_Y0F : R/W; bitpos: [7:0]; default: 255;
+ *  this field configures the point 15 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y0F    0x000000FFU
+#define ISP_GAMMA_R_Y0F_M  (ISP_GAMMA_R_Y0F_V << ISP_GAMMA_R_Y0F_S)
+#define ISP_GAMMA_R_Y0F_V  0x000000FFU
+#define ISP_GAMMA_R_Y0F_S  0
+/** ISP_GAMMA_R_Y0E : R/W; bitpos: [15:8]; default: 240;
+ *  this field configures the point 14 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y0E    0x000000FFU
+#define ISP_GAMMA_R_Y0E_M  (ISP_GAMMA_R_Y0E_V << ISP_GAMMA_R_Y0E_S)
+#define ISP_GAMMA_R_Y0E_V  0x000000FFU
+#define ISP_GAMMA_R_Y0E_S  8
+/** ISP_GAMMA_R_Y0D : R/W; bitpos: [23:16]; default: 224;
+ *  this field configures the point 13 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y0D    0x000000FFU
+#define ISP_GAMMA_R_Y0D_M  (ISP_GAMMA_R_Y0D_V << ISP_GAMMA_R_Y0D_S)
+#define ISP_GAMMA_R_Y0D_V  0x000000FFU
+#define ISP_GAMMA_R_Y0D_S  16
+/** ISP_GAMMA_R_Y0C : R/W; bitpos: [31:24]; default: 208;
+ *  this field configures the point 12 of Y-axis of r channel gamma curve
+ */
+#define ISP_GAMMA_R_Y0C    0x000000FFU
+#define ISP_GAMMA_R_Y0C_M  (ISP_GAMMA_R_Y0C_V << ISP_GAMMA_R_Y0C_S)
+#define ISP_GAMMA_R_Y0C_V  0x000000FFU
+#define ISP_GAMMA_R_Y0C_S  24
+
+/** ISP_GAMMA_GY1_REG register
+ *  point of Y-axis of g channel gamma curve register 1
+ */
+#define ISP_GAMMA_GY1_REG (DR_REG_ISP_BASE + 0x88)
+/** ISP_GAMMA_G_Y03 : R/W; bitpos: [7:0]; default: 64;
+ *  this field configures the point 3 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y03    0x000000FFU
+#define ISP_GAMMA_G_Y03_M  (ISP_GAMMA_G_Y03_V << ISP_GAMMA_G_Y03_S)
+#define ISP_GAMMA_G_Y03_V  0x000000FFU
+#define ISP_GAMMA_G_Y03_S  0
+/** ISP_GAMMA_G_Y02 : R/W; bitpos: [15:8]; default: 48;
+ *  this field configures the point 2 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y02    0x000000FFU
+#define ISP_GAMMA_G_Y02_M  (ISP_GAMMA_G_Y02_V << ISP_GAMMA_G_Y02_S)
+#define ISP_GAMMA_G_Y02_V  0x000000FFU
+#define ISP_GAMMA_G_Y02_S  8
+/** ISP_GAMMA_G_Y01 : R/W; bitpos: [23:16]; default: 32;
+ *  this field configures the point 1 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y01    0x000000FFU
+#define ISP_GAMMA_G_Y01_M  (ISP_GAMMA_G_Y01_V << ISP_GAMMA_G_Y01_S)
+#define ISP_GAMMA_G_Y01_V  0x000000FFU
+#define ISP_GAMMA_G_Y01_S  16
+/** ISP_GAMMA_G_Y00 : R/W; bitpos: [31:24]; default: 16;
+ *  this field configures the point 0 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y00    0x000000FFU
+#define ISP_GAMMA_G_Y00_M  (ISP_GAMMA_G_Y00_V << ISP_GAMMA_G_Y00_S)
+#define ISP_GAMMA_G_Y00_V  0x000000FFU
+#define ISP_GAMMA_G_Y00_S  24
+
+/** ISP_GAMMA_GY2_REG register
+ *  point of Y-axis of g channel gamma curve register 2
+ */
+#define ISP_GAMMA_GY2_REG (DR_REG_ISP_BASE + 0x8c)
+/** ISP_GAMMA_G_Y07 : R/W; bitpos: [7:0]; default: 128;
+ *  this field configures the point 7 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y07    0x000000FFU
+#define ISP_GAMMA_G_Y07_M  (ISP_GAMMA_G_Y07_V << ISP_GAMMA_G_Y07_S)
+#define ISP_GAMMA_G_Y07_V  0x000000FFU
+#define ISP_GAMMA_G_Y07_S  0
+/** ISP_GAMMA_G_Y06 : R/W; bitpos: [15:8]; default: 112;
+ *  this field configures the point 6 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y06    0x000000FFU
+#define ISP_GAMMA_G_Y06_M  (ISP_GAMMA_G_Y06_V << ISP_GAMMA_G_Y06_S)
+#define ISP_GAMMA_G_Y06_V  0x000000FFU
+#define ISP_GAMMA_G_Y06_S  8
+/** ISP_GAMMA_G_Y05 : R/W; bitpos: [23:16]; default: 96;
+ *  this field configures the point 5 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y05    0x000000FFU
+#define ISP_GAMMA_G_Y05_M  (ISP_GAMMA_G_Y05_V << ISP_GAMMA_G_Y05_S)
+#define ISP_GAMMA_G_Y05_V  0x000000FFU
+#define ISP_GAMMA_G_Y05_S  16
+/** ISP_GAMMA_G_Y04 : R/W; bitpos: [31:24]; default: 80;
+ *  this field configures the point 4 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y04    0x000000FFU
+#define ISP_GAMMA_G_Y04_M  (ISP_GAMMA_G_Y04_V << ISP_GAMMA_G_Y04_S)
+#define ISP_GAMMA_G_Y04_V  0x000000FFU
+#define ISP_GAMMA_G_Y04_S  24
+
+/** ISP_GAMMA_GY3_REG register
+ *  point of Y-axis of g channel gamma curve register 3
+ */
+#define ISP_GAMMA_GY3_REG (DR_REG_ISP_BASE + 0x90)
+/** ISP_GAMMA_G_Y0B : R/W; bitpos: [7:0]; default: 192;
+ *  this field configures the point 11 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y0B    0x000000FFU
+#define ISP_GAMMA_G_Y0B_M  (ISP_GAMMA_G_Y0B_V << ISP_GAMMA_G_Y0B_S)
+#define ISP_GAMMA_G_Y0B_V  0x000000FFU
+#define ISP_GAMMA_G_Y0B_S  0
+/** ISP_GAMMA_G_Y0A : R/W; bitpos: [15:8]; default: 176;
+ *  this field configures the point 10 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y0A    0x000000FFU
+#define ISP_GAMMA_G_Y0A_M  (ISP_GAMMA_G_Y0A_V << ISP_GAMMA_G_Y0A_S)
+#define ISP_GAMMA_G_Y0A_V  0x000000FFU
+#define ISP_GAMMA_G_Y0A_S  8
+/** ISP_GAMMA_G_Y09 : R/W; bitpos: [23:16]; default: 160;
+ *  this field configures the point 9 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y09    0x000000FFU
+#define ISP_GAMMA_G_Y09_M  (ISP_GAMMA_G_Y09_V << ISP_GAMMA_G_Y09_S)
+#define ISP_GAMMA_G_Y09_V  0x000000FFU
+#define ISP_GAMMA_G_Y09_S  16
+/** ISP_GAMMA_G_Y08 : R/W; bitpos: [31:24]; default: 144;
+ *  this field configures the point 8 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y08    0x000000FFU
+#define ISP_GAMMA_G_Y08_M  (ISP_GAMMA_G_Y08_V << ISP_GAMMA_G_Y08_S)
+#define ISP_GAMMA_G_Y08_V  0x000000FFU
+#define ISP_GAMMA_G_Y08_S  24
+
+/** ISP_GAMMA_GY4_REG register
+ *  point of Y-axis of g channel gamma curve register 4
+ */
+#define ISP_GAMMA_GY4_REG (DR_REG_ISP_BASE + 0x94)
+/** ISP_GAMMA_G_Y0F : R/W; bitpos: [7:0]; default: 255;
+ *  this field configures the point 15 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y0F    0x000000FFU
+#define ISP_GAMMA_G_Y0F_M  (ISP_GAMMA_G_Y0F_V << ISP_GAMMA_G_Y0F_S)
+#define ISP_GAMMA_G_Y0F_V  0x000000FFU
+#define ISP_GAMMA_G_Y0F_S  0
+/** ISP_GAMMA_G_Y0E : R/W; bitpos: [15:8]; default: 240;
+ *  this field configures the point 14 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y0E    0x000000FFU
+#define ISP_GAMMA_G_Y0E_M  (ISP_GAMMA_G_Y0E_V << ISP_GAMMA_G_Y0E_S)
+#define ISP_GAMMA_G_Y0E_V  0x000000FFU
+#define ISP_GAMMA_G_Y0E_S  8
+/** ISP_GAMMA_G_Y0D : R/W; bitpos: [23:16]; default: 224;
+ *  this field configures the point 13 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y0D    0x000000FFU
+#define ISP_GAMMA_G_Y0D_M  (ISP_GAMMA_G_Y0D_V << ISP_GAMMA_G_Y0D_S)
+#define ISP_GAMMA_G_Y0D_V  0x000000FFU
+#define ISP_GAMMA_G_Y0D_S  16
+/** ISP_GAMMA_G_Y0C : R/W; bitpos: [31:24]; default: 208;
+ *  this field configures the point 12 of Y-axis of g channel gamma curve
+ */
+#define ISP_GAMMA_G_Y0C    0x000000FFU
+#define ISP_GAMMA_G_Y0C_M  (ISP_GAMMA_G_Y0C_V << ISP_GAMMA_G_Y0C_S)
+#define ISP_GAMMA_G_Y0C_V  0x000000FFU
+#define ISP_GAMMA_G_Y0C_S  24
+
+/** ISP_GAMMA_BY1_REG register
+ *  point of Y-axis of b channel gamma curve register 1
+ */
+#define ISP_GAMMA_BY1_REG (DR_REG_ISP_BASE + 0x98)
+/** ISP_GAMMA_B_Y03 : R/W; bitpos: [7:0]; default: 64;
+ *  this field configures the point 3 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y03    0x000000FFU
+#define ISP_GAMMA_B_Y03_M  (ISP_GAMMA_B_Y03_V << ISP_GAMMA_B_Y03_S)
+#define ISP_GAMMA_B_Y03_V  0x000000FFU
+#define ISP_GAMMA_B_Y03_S  0
+/** ISP_GAMMA_B_Y02 : R/W; bitpos: [15:8]; default: 48;
+ *  this field configures the point 2 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y02    0x000000FFU
+#define ISP_GAMMA_B_Y02_M  (ISP_GAMMA_B_Y02_V << ISP_GAMMA_B_Y02_S)
+#define ISP_GAMMA_B_Y02_V  0x000000FFU
+#define ISP_GAMMA_B_Y02_S  8
+/** ISP_GAMMA_B_Y01 : R/W; bitpos: [23:16]; default: 32;
+ *  this field configures the point 1 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y01    0x000000FFU
+#define ISP_GAMMA_B_Y01_M  (ISP_GAMMA_B_Y01_V << ISP_GAMMA_B_Y01_S)
+#define ISP_GAMMA_B_Y01_V  0x000000FFU
+#define ISP_GAMMA_B_Y01_S  16
+/** ISP_GAMMA_B_Y00 : R/W; bitpos: [31:24]; default: 16;
+ *  this field configures the point 0 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y00    0x000000FFU
+#define ISP_GAMMA_B_Y00_M  (ISP_GAMMA_B_Y00_V << ISP_GAMMA_B_Y00_S)
+#define ISP_GAMMA_B_Y00_V  0x000000FFU
+#define ISP_GAMMA_B_Y00_S  24
+
+/** ISP_GAMMA_BY2_REG register
+ *  point of Y-axis of b channel gamma curve register 2
+ */
+#define ISP_GAMMA_BY2_REG (DR_REG_ISP_BASE + 0x9c)
+/** ISP_GAMMA_B_Y07 : R/W; bitpos: [7:0]; default: 128;
+ *  this field configures the point 7 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y07    0x000000FFU
+#define ISP_GAMMA_B_Y07_M  (ISP_GAMMA_B_Y07_V << ISP_GAMMA_B_Y07_S)
+#define ISP_GAMMA_B_Y07_V  0x000000FFU
+#define ISP_GAMMA_B_Y07_S  0
+/** ISP_GAMMA_B_Y06 : R/W; bitpos: [15:8]; default: 112;
+ *  this field configures the point 6 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y06    0x000000FFU
+#define ISP_GAMMA_B_Y06_M  (ISP_GAMMA_B_Y06_V << ISP_GAMMA_B_Y06_S)
+#define ISP_GAMMA_B_Y06_V  0x000000FFU
+#define ISP_GAMMA_B_Y06_S  8
+/** ISP_GAMMA_B_Y05 : R/W; bitpos: [23:16]; default: 96;
+ *  this field configures the point 5 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y05    0x000000FFU
+#define ISP_GAMMA_B_Y05_M  (ISP_GAMMA_B_Y05_V << ISP_GAMMA_B_Y05_S)
+#define ISP_GAMMA_B_Y05_V  0x000000FFU
+#define ISP_GAMMA_B_Y05_S  16
+/** ISP_GAMMA_B_Y04 : R/W; bitpos: [31:24]; default: 80;
+ *  this field configures the point 4 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y04    0x000000FFU
+#define ISP_GAMMA_B_Y04_M  (ISP_GAMMA_B_Y04_V << ISP_GAMMA_B_Y04_S)
+#define ISP_GAMMA_B_Y04_V  0x000000FFU
+#define ISP_GAMMA_B_Y04_S  24
+
+/** ISP_GAMMA_BY3_REG register
+ *  point of Y-axis of b channel gamma curve register 3
+ */
+#define ISP_GAMMA_BY3_REG (DR_REG_ISP_BASE + 0xa0)
+/** ISP_GAMMA_B_Y0B : R/W; bitpos: [7:0]; default: 192;
+ *  this field configures the point 11 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y0B    0x000000FFU
+#define ISP_GAMMA_B_Y0B_M  (ISP_GAMMA_B_Y0B_V << ISP_GAMMA_B_Y0B_S)
+#define ISP_GAMMA_B_Y0B_V  0x000000FFU
+#define ISP_GAMMA_B_Y0B_S  0
+/** ISP_GAMMA_B_Y0A : R/W; bitpos: [15:8]; default: 176;
+ *  this field configures the point 10 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y0A    0x000000FFU
+#define ISP_GAMMA_B_Y0A_M  (ISP_GAMMA_B_Y0A_V << ISP_GAMMA_B_Y0A_S)
+#define ISP_GAMMA_B_Y0A_V  0x000000FFU
+#define ISP_GAMMA_B_Y0A_S  8
+/** ISP_GAMMA_B_Y09 : R/W; bitpos: [23:16]; default: 160;
+ *  this field configures the point 9 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y09    0x000000FFU
+#define ISP_GAMMA_B_Y09_M  (ISP_GAMMA_B_Y09_V << ISP_GAMMA_B_Y09_S)
+#define ISP_GAMMA_B_Y09_V  0x000000FFU
+#define ISP_GAMMA_B_Y09_S  16
+/** ISP_GAMMA_B_Y08 : R/W; bitpos: [31:24]; default: 144;
+ *  this field configures the point 8 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y08    0x000000FFU
+#define ISP_GAMMA_B_Y08_M  (ISP_GAMMA_B_Y08_V << ISP_GAMMA_B_Y08_S)
+#define ISP_GAMMA_B_Y08_V  0x000000FFU
+#define ISP_GAMMA_B_Y08_S  24
+
+/** ISP_GAMMA_BY4_REG register
+ *  point of Y-axis of b channel gamma curve register 4
+ */
+#define ISP_GAMMA_BY4_REG (DR_REG_ISP_BASE + 0xa4)
+/** ISP_GAMMA_B_Y0F : R/W; bitpos: [7:0]; default: 255;
+ *  this field configures the point 15 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y0F    0x000000FFU
+#define ISP_GAMMA_B_Y0F_M  (ISP_GAMMA_B_Y0F_V << ISP_GAMMA_B_Y0F_S)
+#define ISP_GAMMA_B_Y0F_V  0x000000FFU
+#define ISP_GAMMA_B_Y0F_S  0
+/** ISP_GAMMA_B_Y0E : R/W; bitpos: [15:8]; default: 240;
+ *  this field configures the point 14 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y0E    0x000000FFU
+#define ISP_GAMMA_B_Y0E_M  (ISP_GAMMA_B_Y0E_V << ISP_GAMMA_B_Y0E_S)
+#define ISP_GAMMA_B_Y0E_V  0x000000FFU
+#define ISP_GAMMA_B_Y0E_S  8
+/** ISP_GAMMA_B_Y0D : R/W; bitpos: [23:16]; default: 224;
+ *  this field configures the point 13 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y0D    0x000000FFU
+#define ISP_GAMMA_B_Y0D_M  (ISP_GAMMA_B_Y0D_V << ISP_GAMMA_B_Y0D_S)
+#define ISP_GAMMA_B_Y0D_V  0x000000FFU
+#define ISP_GAMMA_B_Y0D_S  16
+/** ISP_GAMMA_B_Y0C : R/W; bitpos: [31:24]; default: 208;
+ *  this field configures the point 12 of Y-axis of b channel gamma curve
+ */
+#define ISP_GAMMA_B_Y0C    0x000000FFU
+#define ISP_GAMMA_B_Y0C_M  (ISP_GAMMA_B_Y0C_V << ISP_GAMMA_B_Y0C_S)
+#define ISP_GAMMA_B_Y0C_V  0x000000FFU
+#define ISP_GAMMA_B_Y0C_S  24
+
+/** ISP_GAMMA_RX1_REG register
+ *  point of X-axis of r channel gamma curve register 1
+ */
+#define ISP_GAMMA_RX1_REG (DR_REG_ISP_BASE + 0xa8)
+/** ISP_GAMMA_R_X07 : R/W; bitpos: [2:0]; default: 4;
+ *  this field configures the point 7 of X-axis of r channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X07    0x00000007U
+#define ISP_GAMMA_R_X07_M  (ISP_GAMMA_R_X07_V << ISP_GAMMA_R_X07_S)
+#define ISP_GAMMA_R_X07_V  0x00000007U
+#define ISP_GAMMA_R_X07_S  0
+/** ISP_GAMMA_R_X06 : R/W; bitpos: [5:3]; default: 4;
+ *  this field configures the point 6 of X-axis of r channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X06    0x00000007U
+#define ISP_GAMMA_R_X06_M  (ISP_GAMMA_R_X06_V << ISP_GAMMA_R_X06_S)
+#define ISP_GAMMA_R_X06_V  0x00000007U
+#define ISP_GAMMA_R_X06_S  3
+/** ISP_GAMMA_R_X05 : R/W; bitpos: [8:6]; default: 4;
+ *  this field configures the point 5 of X-axis of r channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X05    0x00000007U
+#define ISP_GAMMA_R_X05_M  (ISP_GAMMA_R_X05_V << ISP_GAMMA_R_X05_S)
+#define ISP_GAMMA_R_X05_V  0x00000007U
+#define ISP_GAMMA_R_X05_S  6
+/** ISP_GAMMA_R_X04 : R/W; bitpos: [11:9]; default: 4;
+ *  this field configures the point 4 of X-axis of r channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X04    0x00000007U
+#define ISP_GAMMA_R_X04_M  (ISP_GAMMA_R_X04_V << ISP_GAMMA_R_X04_S)
+#define ISP_GAMMA_R_X04_V  0x00000007U
+#define ISP_GAMMA_R_X04_S  9
+/** ISP_GAMMA_R_X03 : R/W; bitpos: [14:12]; default: 4;
+ *  this field configures the point 3 of X-axis of r channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X03    0x00000007U
+#define ISP_GAMMA_R_X03_M  (ISP_GAMMA_R_X03_V << ISP_GAMMA_R_X03_S)
+#define ISP_GAMMA_R_X03_V  0x00000007U
+#define ISP_GAMMA_R_X03_S  12
+/** ISP_GAMMA_R_X02 : R/W; bitpos: [17:15]; default: 4;
+ *  this field configures the point 2 of X-axis of r channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X02    0x00000007U
+#define ISP_GAMMA_R_X02_M  (ISP_GAMMA_R_X02_V << ISP_GAMMA_R_X02_S)
+#define ISP_GAMMA_R_X02_V  0x00000007U
+#define ISP_GAMMA_R_X02_S  15
+/** ISP_GAMMA_R_X01 : R/W; bitpos: [20:18]; default: 4;
+ *  this field configures the point 1 of X-axis of r channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X01    0x00000007U
+#define ISP_GAMMA_R_X01_M  (ISP_GAMMA_R_X01_V << ISP_GAMMA_R_X01_S)
+#define ISP_GAMMA_R_X01_V  0x00000007U
+#define ISP_GAMMA_R_X01_S  18
+/** ISP_GAMMA_R_X00 : R/W; bitpos: [23:21]; default: 4;
+ *  this field configures the point 0 of X-axis of r channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X00    0x00000007U
+#define ISP_GAMMA_R_X00_M  (ISP_GAMMA_R_X00_V << ISP_GAMMA_R_X00_S)
+#define ISP_GAMMA_R_X00_V  0x00000007U
+#define ISP_GAMMA_R_X00_S  21
+
+/** ISP_GAMMA_RX2_REG register
+ *  point of X-axis of r channel gamma curve register 2
+ */
+#define ISP_GAMMA_RX2_REG (DR_REG_ISP_BASE + 0xac)
+/** ISP_GAMMA_R_X0F : R/W; bitpos: [2:0]; default: 4;
+ *  this field configures the point 15 of X-axis of r channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X0F    0x00000007U
+#define ISP_GAMMA_R_X0F_M  (ISP_GAMMA_R_X0F_V << ISP_GAMMA_R_X0F_S)
+#define ISP_GAMMA_R_X0F_V  0x00000007U
+#define ISP_GAMMA_R_X0F_S  0
+/** ISP_GAMMA_R_X0E : R/W; bitpos: [5:3]; default: 4;
+ *  this field configures the point 14 of X-axis of r channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X0E    0x00000007U
+#define ISP_GAMMA_R_X0E_M  (ISP_GAMMA_R_X0E_V << ISP_GAMMA_R_X0E_S)
+#define ISP_GAMMA_R_X0E_V  0x00000007U
+#define ISP_GAMMA_R_X0E_S  3
+/** ISP_GAMMA_R_X0D : R/W; bitpos: [8:6]; default: 4;
+ *  this field configures the point 13 of X-axis of r channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X0D    0x00000007U
+#define ISP_GAMMA_R_X0D_M  (ISP_GAMMA_R_X0D_V << ISP_GAMMA_R_X0D_S)
+#define ISP_GAMMA_R_X0D_V  0x00000007U
+#define ISP_GAMMA_R_X0D_S  6
+/** ISP_GAMMA_R_X0C : R/W; bitpos: [11:9]; default: 4;
+ *  this field configures the point 12 of X-axis of r channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X0C    0x00000007U
+#define ISP_GAMMA_R_X0C_M  (ISP_GAMMA_R_X0C_V << ISP_GAMMA_R_X0C_S)
+#define ISP_GAMMA_R_X0C_V  0x00000007U
+#define ISP_GAMMA_R_X0C_S  9
+/** ISP_GAMMA_R_X0B : R/W; bitpos: [14:12]; default: 4;
+ *  this field configures the point 11 of X-axis of r channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X0B    0x00000007U
+#define ISP_GAMMA_R_X0B_M  (ISP_GAMMA_R_X0B_V << ISP_GAMMA_R_X0B_S)
+#define ISP_GAMMA_R_X0B_V  0x00000007U
+#define ISP_GAMMA_R_X0B_S  12
+/** ISP_GAMMA_R_X0A : R/W; bitpos: [17:15]; default: 4;
+ *  this field configures the point 10 of X-axis of r channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X0A    0x00000007U
+#define ISP_GAMMA_R_X0A_M  (ISP_GAMMA_R_X0A_V << ISP_GAMMA_R_X0A_S)
+#define ISP_GAMMA_R_X0A_V  0x00000007U
+#define ISP_GAMMA_R_X0A_S  15
+/** ISP_GAMMA_R_X09 : R/W; bitpos: [20:18]; default: 4;
+ *  this field configures the point 9 of X-axis of r channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X09    0x00000007U
+#define ISP_GAMMA_R_X09_M  (ISP_GAMMA_R_X09_V << ISP_GAMMA_R_X09_S)
+#define ISP_GAMMA_R_X09_V  0x00000007U
+#define ISP_GAMMA_R_X09_S  18
+/** ISP_GAMMA_R_X08 : R/W; bitpos: [23:21]; default: 4;
+ *  this field configures the point 8 of X-axis of r channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_R_X08    0x00000007U
+#define ISP_GAMMA_R_X08_M  (ISP_GAMMA_R_X08_V << ISP_GAMMA_R_X08_S)
+#define ISP_GAMMA_R_X08_V  0x00000007U
+#define ISP_GAMMA_R_X08_S  21
+
+/** ISP_GAMMA_GX1_REG register
+ *  point of X-axis of g channel gamma curve register 1
+ */
+#define ISP_GAMMA_GX1_REG (DR_REG_ISP_BASE + 0xb0)
+/** ISP_GAMMA_G_X07 : R/W; bitpos: [2:0]; default: 4;
+ *  this field configures the point 7 of X-axis of g channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X07    0x00000007U
+#define ISP_GAMMA_G_X07_M  (ISP_GAMMA_G_X07_V << ISP_GAMMA_G_X07_S)
+#define ISP_GAMMA_G_X07_V  0x00000007U
+#define ISP_GAMMA_G_X07_S  0
+/** ISP_GAMMA_G_X06 : R/W; bitpos: [5:3]; default: 4;
+ *  this field configures the point 6 of X-axis of g channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X06    0x00000007U
+#define ISP_GAMMA_G_X06_M  (ISP_GAMMA_G_X06_V << ISP_GAMMA_G_X06_S)
+#define ISP_GAMMA_G_X06_V  0x00000007U
+#define ISP_GAMMA_G_X06_S  3
+/** ISP_GAMMA_G_X05 : R/W; bitpos: [8:6]; default: 4;
+ *  this field configures the point 5 of X-axis of g channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X05    0x00000007U
+#define ISP_GAMMA_G_X05_M  (ISP_GAMMA_G_X05_V << ISP_GAMMA_G_X05_S)
+#define ISP_GAMMA_G_X05_V  0x00000007U
+#define ISP_GAMMA_G_X05_S  6
+/** ISP_GAMMA_G_X04 : R/W; bitpos: [11:9]; default: 4;
+ *  this field configures the point 4 of X-axis of g channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X04    0x00000007U
+#define ISP_GAMMA_G_X04_M  (ISP_GAMMA_G_X04_V << ISP_GAMMA_G_X04_S)
+#define ISP_GAMMA_G_X04_V  0x00000007U
+#define ISP_GAMMA_G_X04_S  9
+/** ISP_GAMMA_G_X03 : R/W; bitpos: [14:12]; default: 4;
+ *  this field configures the point 3 of X-axis of g channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X03    0x00000007U
+#define ISP_GAMMA_G_X03_M  (ISP_GAMMA_G_X03_V << ISP_GAMMA_G_X03_S)
+#define ISP_GAMMA_G_X03_V  0x00000007U
+#define ISP_GAMMA_G_X03_S  12
+/** ISP_GAMMA_G_X02 : R/W; bitpos: [17:15]; default: 4;
+ *  this field configures the point 2 of X-axis of g channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X02    0x00000007U
+#define ISP_GAMMA_G_X02_M  (ISP_GAMMA_G_X02_V << ISP_GAMMA_G_X02_S)
+#define ISP_GAMMA_G_X02_V  0x00000007U
+#define ISP_GAMMA_G_X02_S  15
+/** ISP_GAMMA_G_X01 : R/W; bitpos: [20:18]; default: 4;
+ *  this field configures the point 1 of X-axis of g channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X01    0x00000007U
+#define ISP_GAMMA_G_X01_M  (ISP_GAMMA_G_X01_V << ISP_GAMMA_G_X01_S)
+#define ISP_GAMMA_G_X01_V  0x00000007U
+#define ISP_GAMMA_G_X01_S  18
+/** ISP_GAMMA_G_X00 : R/W; bitpos: [23:21]; default: 4;
+ *  this field configures the point 0 of X-axis of g channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X00    0x00000007U
+#define ISP_GAMMA_G_X00_M  (ISP_GAMMA_G_X00_V << ISP_GAMMA_G_X00_S)
+#define ISP_GAMMA_G_X00_V  0x00000007U
+#define ISP_GAMMA_G_X00_S  21
+
+/** ISP_GAMMA_GX2_REG register
+ *  point of X-axis of g channel gamma curve register 2
+ */
+#define ISP_GAMMA_GX2_REG (DR_REG_ISP_BASE + 0xb4)
+/** ISP_GAMMA_G_X0F : R/W; bitpos: [2:0]; default: 4;
+ *  this field configures the point 15 of X-axis of g channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X0F    0x00000007U
+#define ISP_GAMMA_G_X0F_M  (ISP_GAMMA_G_X0F_V << ISP_GAMMA_G_X0F_S)
+#define ISP_GAMMA_G_X0F_V  0x00000007U
+#define ISP_GAMMA_G_X0F_S  0
+/** ISP_GAMMA_G_X0E : R/W; bitpos: [5:3]; default: 4;
+ *  this field configures the point 14 of X-axis of g channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X0E    0x00000007U
+#define ISP_GAMMA_G_X0E_M  (ISP_GAMMA_G_X0E_V << ISP_GAMMA_G_X0E_S)
+#define ISP_GAMMA_G_X0E_V  0x00000007U
+#define ISP_GAMMA_G_X0E_S  3
+/** ISP_GAMMA_G_X0D : R/W; bitpos: [8:6]; default: 4;
+ *  this field configures the point 13 of X-axis of g channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X0D    0x00000007U
+#define ISP_GAMMA_G_X0D_M  (ISP_GAMMA_G_X0D_V << ISP_GAMMA_G_X0D_S)
+#define ISP_GAMMA_G_X0D_V  0x00000007U
+#define ISP_GAMMA_G_X0D_S  6
+/** ISP_GAMMA_G_X0C : R/W; bitpos: [11:9]; default: 4;
+ *  this field configures the point 12 of X-axis of g channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X0C    0x00000007U
+#define ISP_GAMMA_G_X0C_M  (ISP_GAMMA_G_X0C_V << ISP_GAMMA_G_X0C_S)
+#define ISP_GAMMA_G_X0C_V  0x00000007U
+#define ISP_GAMMA_G_X0C_S  9
+/** ISP_GAMMA_G_X0B : R/W; bitpos: [14:12]; default: 4;
+ *  this field configures the point 11 of X-axis of g channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X0B    0x00000007U
+#define ISP_GAMMA_G_X0B_M  (ISP_GAMMA_G_X0B_V << ISP_GAMMA_G_X0B_S)
+#define ISP_GAMMA_G_X0B_V  0x00000007U
+#define ISP_GAMMA_G_X0B_S  12
+/** ISP_GAMMA_G_X0A : R/W; bitpos: [17:15]; default: 4;
+ *  this field configures the point 10 of X-axis of g channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X0A    0x00000007U
+#define ISP_GAMMA_G_X0A_M  (ISP_GAMMA_G_X0A_V << ISP_GAMMA_G_X0A_S)
+#define ISP_GAMMA_G_X0A_V  0x00000007U
+#define ISP_GAMMA_G_X0A_S  15
+/** ISP_GAMMA_G_X09 : R/W; bitpos: [20:18]; default: 4;
+ *  this field configures the point 9 of X-axis of g channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X09    0x00000007U
+#define ISP_GAMMA_G_X09_M  (ISP_GAMMA_G_X09_V << ISP_GAMMA_G_X09_S)
+#define ISP_GAMMA_G_X09_V  0x00000007U
+#define ISP_GAMMA_G_X09_S  18
+/** ISP_GAMMA_G_X08 : R/W; bitpos: [23:21]; default: 4;
+ *  this field configures the point 8 of X-axis of g channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_G_X08    0x00000007U
+#define ISP_GAMMA_G_X08_M  (ISP_GAMMA_G_X08_V << ISP_GAMMA_G_X08_S)
+#define ISP_GAMMA_G_X08_V  0x00000007U
+#define ISP_GAMMA_G_X08_S  21
+
+/** ISP_GAMMA_BX1_REG register
+ *  point of X-axis of b channel gamma curve register 1
+ */
+#define ISP_GAMMA_BX1_REG (DR_REG_ISP_BASE + 0xb8)
+/** ISP_GAMMA_B_X07 : R/W; bitpos: [2:0]; default: 4;
+ *  this field configures the point 7 of X-axis of b channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X07    0x00000007U
+#define ISP_GAMMA_B_X07_M  (ISP_GAMMA_B_X07_V << ISP_GAMMA_B_X07_S)
+#define ISP_GAMMA_B_X07_V  0x00000007U
+#define ISP_GAMMA_B_X07_S  0
+/** ISP_GAMMA_B_X06 : R/W; bitpos: [5:3]; default: 4;
+ *  this field configures the point 6 of X-axis of b channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X06    0x00000007U
+#define ISP_GAMMA_B_X06_M  (ISP_GAMMA_B_X06_V << ISP_GAMMA_B_X06_S)
+#define ISP_GAMMA_B_X06_V  0x00000007U
+#define ISP_GAMMA_B_X06_S  3
+/** ISP_GAMMA_B_X05 : R/W; bitpos: [8:6]; default: 4;
+ *  this field configures the point 5 of X-axis of b channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X05    0x00000007U
+#define ISP_GAMMA_B_X05_M  (ISP_GAMMA_B_X05_V << ISP_GAMMA_B_X05_S)
+#define ISP_GAMMA_B_X05_V  0x00000007U
+#define ISP_GAMMA_B_X05_S  6
+/** ISP_GAMMA_B_X04 : R/W; bitpos: [11:9]; default: 4;
+ *  this field configures the point 4 of X-axis of b channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X04    0x00000007U
+#define ISP_GAMMA_B_X04_M  (ISP_GAMMA_B_X04_V << ISP_GAMMA_B_X04_S)
+#define ISP_GAMMA_B_X04_V  0x00000007U
+#define ISP_GAMMA_B_X04_S  9
+/** ISP_GAMMA_B_X03 : R/W; bitpos: [14:12]; default: 4;
+ *  this field configures the point 3 of X-axis of b channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X03    0x00000007U
+#define ISP_GAMMA_B_X03_M  (ISP_GAMMA_B_X03_V << ISP_GAMMA_B_X03_S)
+#define ISP_GAMMA_B_X03_V  0x00000007U
+#define ISP_GAMMA_B_X03_S  12
+/** ISP_GAMMA_B_X02 : R/W; bitpos: [17:15]; default: 4;
+ *  this field configures the point 2 of X-axis of b channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X02    0x00000007U
+#define ISP_GAMMA_B_X02_M  (ISP_GAMMA_B_X02_V << ISP_GAMMA_B_X02_S)
+#define ISP_GAMMA_B_X02_V  0x00000007U
+#define ISP_GAMMA_B_X02_S  15
+/** ISP_GAMMA_B_X01 : R/W; bitpos: [20:18]; default: 4;
+ *  this field configures the point 1 of X-axis of b channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X01    0x00000007U
+#define ISP_GAMMA_B_X01_M  (ISP_GAMMA_B_X01_V << ISP_GAMMA_B_X01_S)
+#define ISP_GAMMA_B_X01_V  0x00000007U
+#define ISP_GAMMA_B_X01_S  18
+/** ISP_GAMMA_B_X00 : R/W; bitpos: [23:21]; default: 4;
+ *  this field configures the point 0 of X-axis of b channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X00    0x00000007U
+#define ISP_GAMMA_B_X00_M  (ISP_GAMMA_B_X00_V << ISP_GAMMA_B_X00_S)
+#define ISP_GAMMA_B_X00_V  0x00000007U
+#define ISP_GAMMA_B_X00_S  21
+
+/** ISP_GAMMA_BX2_REG register
+ *  point of X-axis of b channel gamma curve register 2
+ */
+#define ISP_GAMMA_BX2_REG (DR_REG_ISP_BASE + 0xbc)
+/** ISP_GAMMA_B_X0F : R/W; bitpos: [2:0]; default: 4;
+ *  this field configures the point 15 of X-axis of b channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X0F    0x00000007U
+#define ISP_GAMMA_B_X0F_M  (ISP_GAMMA_B_X0F_V << ISP_GAMMA_B_X0F_S)
+#define ISP_GAMMA_B_X0F_V  0x00000007U
+#define ISP_GAMMA_B_X0F_S  0
+/** ISP_GAMMA_B_X0E : R/W; bitpos: [5:3]; default: 4;
+ *  this field configures the point 14 of X-axis of b channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X0E    0x00000007U
+#define ISP_GAMMA_B_X0E_M  (ISP_GAMMA_B_X0E_V << ISP_GAMMA_B_X0E_S)
+#define ISP_GAMMA_B_X0E_V  0x00000007U
+#define ISP_GAMMA_B_X0E_S  3
+/** ISP_GAMMA_B_X0D : R/W; bitpos: [8:6]; default: 4;
+ *  this field configures the point 13 of X-axis of b channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X0D    0x00000007U
+#define ISP_GAMMA_B_X0D_M  (ISP_GAMMA_B_X0D_V << ISP_GAMMA_B_X0D_S)
+#define ISP_GAMMA_B_X0D_V  0x00000007U
+#define ISP_GAMMA_B_X0D_S  6
+/** ISP_GAMMA_B_X0C : R/W; bitpos: [11:9]; default: 4;
+ *  this field configures the point 12 of X-axis of b channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X0C    0x00000007U
+#define ISP_GAMMA_B_X0C_M  (ISP_GAMMA_B_X0C_V << ISP_GAMMA_B_X0C_S)
+#define ISP_GAMMA_B_X0C_V  0x00000007U
+#define ISP_GAMMA_B_X0C_S  9
+/** ISP_GAMMA_B_X0B : R/W; bitpos: [14:12]; default: 4;
+ *  this field configures the point 11 of X-axis of b channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X0B    0x00000007U
+#define ISP_GAMMA_B_X0B_M  (ISP_GAMMA_B_X0B_V << ISP_GAMMA_B_X0B_S)
+#define ISP_GAMMA_B_X0B_V  0x00000007U
+#define ISP_GAMMA_B_X0B_S  12
+/** ISP_GAMMA_B_X0A : R/W; bitpos: [17:15]; default: 4;
+ *  this field configures the point 10 of X-axis of b channel gamma curve, it
+ *  represents the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X0A    0x00000007U
+#define ISP_GAMMA_B_X0A_M  (ISP_GAMMA_B_X0A_V << ISP_GAMMA_B_X0A_S)
+#define ISP_GAMMA_B_X0A_V  0x00000007U
+#define ISP_GAMMA_B_X0A_S  15
+/** ISP_GAMMA_B_X09 : R/W; bitpos: [20:18]; default: 4;
+ *  this field configures the point 9 of X-axis of b channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X09    0x00000007U
+#define ISP_GAMMA_B_X09_M  (ISP_GAMMA_B_X09_V << ISP_GAMMA_B_X09_S)
+#define ISP_GAMMA_B_X09_V  0x00000007U
+#define ISP_GAMMA_B_X09_S  18
+/** ISP_GAMMA_B_X08 : R/W; bitpos: [23:21]; default: 4;
+ *  this field configures the point 8 of X-axis of b channel gamma curve, it represents
+ *  the power of the distance from the previous point
+ */
+#define ISP_GAMMA_B_X08    0x00000007U
+#define ISP_GAMMA_B_X08_M  (ISP_GAMMA_B_X08_V << ISP_GAMMA_B_X08_S)
+#define ISP_GAMMA_B_X08_V  0x00000007U
+#define ISP_GAMMA_B_X08_S  21
+
+/** ISP_AE_CTRL_REG register
+ *  ae control register
+ */
+#define ISP_AE_CTRL_REG (DR_REG_ISP_BASE + 0xc0)
+/** ISP_AE_UPDATE : WT; bitpos: [0]; default: 0;
+ *  write 1 to this bit triggers one statistic event
+ */
+#define ISP_AE_UPDATE    (BIT(0))
+#define ISP_AE_UPDATE_M  (ISP_AE_UPDATE_V << ISP_AE_UPDATE_S)
+#define ISP_AE_UPDATE_V  0x00000001U
+#define ISP_AE_UPDATE_S  0
+/** ISP_AE_SELECT : R/W; bitpos: [1]; default: 0;
+ *  this field configures ae input data source, 0: data from median, 1: data from gama
+ */
+#define ISP_AE_SELECT    (BIT(1))
+#define ISP_AE_SELECT_M  (ISP_AE_SELECT_V << ISP_AE_SELECT_S)
+#define ISP_AE_SELECT_V  0x00000001U
+#define ISP_AE_SELECT_S  1
+
+/** ISP_AE_MONITOR_REG register
+ *  ae monitor control register
+ */
+#define ISP_AE_MONITOR_REG (DR_REG_ISP_BASE + 0xc4)
+/** ISP_AE_MONITOR_TL : R/W; bitpos: [7:0]; default: 0;
+ *  this field configures the lower lum threshold of ae monitor
+ */
+#define ISP_AE_MONITOR_TL    0x000000FFU
+#define ISP_AE_MONITOR_TL_M  (ISP_AE_MONITOR_TL_V << ISP_AE_MONITOR_TL_S)
+#define ISP_AE_MONITOR_TL_V  0x000000FFU
+#define ISP_AE_MONITOR_TL_S  0
+/** ISP_AE_MONITOR_TH : R/W; bitpos: [15:8]; default: 0;
+ *  this field configures the higher lum threshold of ae monitor
+ */
+#define ISP_AE_MONITOR_TH    0x000000FFU
+#define ISP_AE_MONITOR_TH_M  (ISP_AE_MONITOR_TH_V << ISP_AE_MONITOR_TH_S)
+#define ISP_AE_MONITOR_TH_V  0x000000FFU
+#define ISP_AE_MONITOR_TH_S  8
+/** ISP_AE_MONITOR_PERIOD : R/W; bitpos: [21:16]; default: 0;
+ *  this field configures ae monitor frame period
+ */
+#define ISP_AE_MONITOR_PERIOD    0x0000003FU
+#define ISP_AE_MONITOR_PERIOD_M  (ISP_AE_MONITOR_PERIOD_V << ISP_AE_MONITOR_PERIOD_S)
+#define ISP_AE_MONITOR_PERIOD_V  0x0000003FU
+#define ISP_AE_MONITOR_PERIOD_S  16
+
+/** ISP_AE_BX_REG register
+ *  ae window register in x-direction
+ */
+#define ISP_AE_BX_REG (DR_REG_ISP_BASE + 0xc8)
+/** ISP_AE_X_BSIZE : R/W; bitpos: [10:0]; default: 384;
+ *  this field configures every block x size
+ */
+#define ISP_AE_X_BSIZE    0x000007FFU
+#define ISP_AE_X_BSIZE_M  (ISP_AE_X_BSIZE_V << ISP_AE_X_BSIZE_S)
+#define ISP_AE_X_BSIZE_V  0x000007FFU
+#define ISP_AE_X_BSIZE_S  0
+/** ISP_AE_X_START : R/W; bitpos: [21:11]; default: 0;
+ *  this field configures first block start x address
+ */
+#define ISP_AE_X_START    0x000007FFU
+#define ISP_AE_X_START_M  (ISP_AE_X_START_V << ISP_AE_X_START_S)
+#define ISP_AE_X_START_V  0x000007FFU
+#define ISP_AE_X_START_S  11
+
+/** ISP_AE_BY_REG register
+ *  ae window register in y-direction
+ */
+#define ISP_AE_BY_REG (DR_REG_ISP_BASE + 0xcc)
+/** ISP_AE_Y_BSIZE : R/W; bitpos: [10:0]; default: 216;
+ *  this field configures every block y size
+ */
+#define ISP_AE_Y_BSIZE    0x000007FFU
+#define ISP_AE_Y_BSIZE_M  (ISP_AE_Y_BSIZE_V << ISP_AE_Y_BSIZE_S)
+#define ISP_AE_Y_BSIZE_V  0x000007FFU
+#define ISP_AE_Y_BSIZE_S  0
+/** ISP_AE_Y_START : R/W; bitpos: [21:11]; default: 0;
+ *  this field configures first block start y address
+ */
+#define ISP_AE_Y_START    0x000007FFU
+#define ISP_AE_Y_START_M  (ISP_AE_Y_START_V << ISP_AE_Y_START_S)
+#define ISP_AE_Y_START_V  0x000007FFU
+#define ISP_AE_Y_START_S  11
+
+/** ISP_AE_WINPIXNUM_REG register
+ *  ae sub-window pix num register
+ */
+#define ISP_AE_WINPIXNUM_REG (DR_REG_ISP_BASE + 0xd0)
+/** ISP_AE_SUBWIN_PIXNUM : R/W; bitpos: [16:0]; default: 82944;
+ *  this field configures the pixel number of each sub win
+ */
+#define ISP_AE_SUBWIN_PIXNUM    0x0001FFFFU
+#define ISP_AE_SUBWIN_PIXNUM_M  (ISP_AE_SUBWIN_PIXNUM_V << ISP_AE_SUBWIN_PIXNUM_S)
+#define ISP_AE_SUBWIN_PIXNUM_V  0x0001FFFFU
+#define ISP_AE_SUBWIN_PIXNUM_S  0
+
+/** ISP_AE_WIN_RECIPROCAL_REG register
+ *  reciprocal of ae sub-window pixel number
+ */
+#define ISP_AE_WIN_RECIPROCAL_REG (DR_REG_ISP_BASE + 0xd4)
+/** ISP_AE_SUBWIN_RECIP : R/W; bitpos: [19:0]; default: 0;
+ *  this field configures the reciprocal of each subwin_pixnum, 20bit fraction
+ */
+#define ISP_AE_SUBWIN_RECIP    0x000FFFFFU
+#define ISP_AE_SUBWIN_RECIP_M  (ISP_AE_SUBWIN_RECIP_V << ISP_AE_SUBWIN_RECIP_S)
+#define ISP_AE_SUBWIN_RECIP_V  0x000FFFFFU
+#define ISP_AE_SUBWIN_RECIP_S  0
+
+/** ISP_AE_BLOCK_MEAN_0_REG register
+ *  ae statistic result register 0
+ */
+#define ISP_AE_BLOCK_MEAN_0_REG (DR_REG_ISP_BASE + 0xd8)
+/** ISP_AE_B03_MEAN : RO; bitpos: [7:0]; default: 0;
+ *  this field configures block03 Y mean data
+ */
+#define ISP_AE_B03_MEAN    0x000000FFU
+#define ISP_AE_B03_MEAN_M  (ISP_AE_B03_MEAN_V << ISP_AE_B03_MEAN_S)
+#define ISP_AE_B03_MEAN_V  0x000000FFU
+#define ISP_AE_B03_MEAN_S  0
+/** ISP_AE_B02_MEAN : RO; bitpos: [15:8]; default: 0;
+ *  this field configures block02 Y mean data
+ */
+#define ISP_AE_B02_MEAN    0x000000FFU
+#define ISP_AE_B02_MEAN_M  (ISP_AE_B02_MEAN_V << ISP_AE_B02_MEAN_S)
+#define ISP_AE_B02_MEAN_V  0x000000FFU
+#define ISP_AE_B02_MEAN_S  8
+/** ISP_AE_B01_MEAN : RO; bitpos: [23:16]; default: 0;
+ *  this field configures block01 Y mean data
+ */
+#define ISP_AE_B01_MEAN    0x000000FFU
+#define ISP_AE_B01_MEAN_M  (ISP_AE_B01_MEAN_V << ISP_AE_B01_MEAN_S)
+#define ISP_AE_B01_MEAN_V  0x000000FFU
+#define ISP_AE_B01_MEAN_S  16
+/** ISP_AE_B00_MEAN : RO; bitpos: [31:24]; default: 0;
+ *  this field configures block00 Y mean data
+ */
+#define ISP_AE_B00_MEAN    0x000000FFU
+#define ISP_AE_B00_MEAN_M  (ISP_AE_B00_MEAN_V << ISP_AE_B00_MEAN_S)
+#define ISP_AE_B00_MEAN_V  0x000000FFU
+#define ISP_AE_B00_MEAN_S  24
+
+/** ISP_AE_BLOCK_MEAN_1_REG register
+ *  ae statistic result register 1
+ */
+#define ISP_AE_BLOCK_MEAN_1_REG (DR_REG_ISP_BASE + 0xdc)
+/** ISP_AE_B12_MEAN : RO; bitpos: [7:0]; default: 0;
+ *  this field configures block12 Y mean data
+ */
+#define ISP_AE_B12_MEAN    0x000000FFU
+#define ISP_AE_B12_MEAN_M  (ISP_AE_B12_MEAN_V << ISP_AE_B12_MEAN_S)
+#define ISP_AE_B12_MEAN_V  0x000000FFU
+#define ISP_AE_B12_MEAN_S  0
+/** ISP_AE_B11_MEAN : RO; bitpos: [15:8]; default: 0;
+ *  this field configures block11 Y mean data
+ */
+#define ISP_AE_B11_MEAN    0x000000FFU
+#define ISP_AE_B11_MEAN_M  (ISP_AE_B11_MEAN_V << ISP_AE_B11_MEAN_S)
+#define ISP_AE_B11_MEAN_V  0x000000FFU
+#define ISP_AE_B11_MEAN_S  8
+/** ISP_AE_B10_MEAN : RO; bitpos: [23:16]; default: 0;
+ *  this field configures block10 Y mean data
+ */
+#define ISP_AE_B10_MEAN    0x000000FFU
+#define ISP_AE_B10_MEAN_M  (ISP_AE_B10_MEAN_V << ISP_AE_B10_MEAN_S)
+#define ISP_AE_B10_MEAN_V  0x000000FFU
+#define ISP_AE_B10_MEAN_S  16
+/** ISP_AE_B04_MEAN : RO; bitpos: [31:24]; default: 0;
+ *  this field configures block04 Y mean data
+ */
+#define ISP_AE_B04_MEAN    0x000000FFU
+#define ISP_AE_B04_MEAN_M  (ISP_AE_B04_MEAN_V << ISP_AE_B04_MEAN_S)
+#define ISP_AE_B04_MEAN_V  0x000000FFU
+#define ISP_AE_B04_MEAN_S  24
+
+/** ISP_AE_BLOCK_MEAN_2_REG register
+ *  ae statistic result register 2
+ */
+#define ISP_AE_BLOCK_MEAN_2_REG (DR_REG_ISP_BASE + 0xe0)
+/** ISP_AE_B21_MEAN : RO; bitpos: [7:0]; default: 0;
+ *  this field configures block21 Y mean data
+ */
+#define ISP_AE_B21_MEAN    0x000000FFU
+#define ISP_AE_B21_MEAN_M  (ISP_AE_B21_MEAN_V << ISP_AE_B21_MEAN_S)
+#define ISP_AE_B21_MEAN_V  0x000000FFU
+#define ISP_AE_B21_MEAN_S  0
+/** ISP_AE_B20_MEAN : RO; bitpos: [15:8]; default: 0;
+ *  this field configures block20 Y mean data
+ */
+#define ISP_AE_B20_MEAN    0x000000FFU
+#define ISP_AE_B20_MEAN_M  (ISP_AE_B20_MEAN_V << ISP_AE_B20_MEAN_S)
+#define ISP_AE_B20_MEAN_V  0x000000FFU
+#define ISP_AE_B20_MEAN_S  8
+/** ISP_AE_B14_MEAN : RO; bitpos: [23:16]; default: 0;
+ *  this field configures block14 Y mean data
+ */
+#define ISP_AE_B14_MEAN    0x000000FFU
+#define ISP_AE_B14_MEAN_M  (ISP_AE_B14_MEAN_V << ISP_AE_B14_MEAN_S)
+#define ISP_AE_B14_MEAN_V  0x000000FFU
+#define ISP_AE_B14_MEAN_S  16
+/** ISP_AE_B13_MEAN : RO; bitpos: [31:24]; default: 0;
+ *  this field configures block13 Y mean data
+ */
+#define ISP_AE_B13_MEAN    0x000000FFU
+#define ISP_AE_B13_MEAN_M  (ISP_AE_B13_MEAN_V << ISP_AE_B13_MEAN_S)
+#define ISP_AE_B13_MEAN_V  0x000000FFU
+#define ISP_AE_B13_MEAN_S  24
+
+/** ISP_AE_BLOCK_MEAN_3_REG register
+ *  ae statistic result register 3
+ */
+#define ISP_AE_BLOCK_MEAN_3_REG (DR_REG_ISP_BASE + 0xe4)
+/** ISP_AE_B30_MEAN : RO; bitpos: [7:0]; default: 0;
+ *  this field configures block30 Y mean data
+ */
+#define ISP_AE_B30_MEAN    0x000000FFU
+#define ISP_AE_B30_MEAN_M  (ISP_AE_B30_MEAN_V << ISP_AE_B30_MEAN_S)
+#define ISP_AE_B30_MEAN_V  0x000000FFU
+#define ISP_AE_B30_MEAN_S  0
+/** ISP_AE_B24_MEAN : RO; bitpos: [15:8]; default: 0;
+ *  this field configures block24 Y mean data
+ */
+#define ISP_AE_B24_MEAN    0x000000FFU
+#define ISP_AE_B24_MEAN_M  (ISP_AE_B24_MEAN_V << ISP_AE_B24_MEAN_S)
+#define ISP_AE_B24_MEAN_V  0x000000FFU
+#define ISP_AE_B24_MEAN_S  8
+/** ISP_AE_B23_MEAN : RO; bitpos: [23:16]; default: 0;
+ *  this field configures block23 Y mean data
+ */
+#define ISP_AE_B23_MEAN    0x000000FFU
+#define ISP_AE_B23_MEAN_M  (ISP_AE_B23_MEAN_V << ISP_AE_B23_MEAN_S)
+#define ISP_AE_B23_MEAN_V  0x000000FFU
+#define ISP_AE_B23_MEAN_S  16
+/** ISP_AE_B22_MEAN : RO; bitpos: [31:24]; default: 0;
+ *  this field configures block22 Y mean data
+ */
+#define ISP_AE_B22_MEAN    0x000000FFU
+#define ISP_AE_B22_MEAN_M  (ISP_AE_B22_MEAN_V << ISP_AE_B22_MEAN_S)
+#define ISP_AE_B22_MEAN_V  0x000000FFU
+#define ISP_AE_B22_MEAN_S  24
+
+/** ISP_AE_BLOCK_MEAN_4_REG register
+ *  ae statistic result register 4
+ */
+#define ISP_AE_BLOCK_MEAN_4_REG (DR_REG_ISP_BASE + 0xe8)
+/** ISP_AE_B34_MEAN : RO; bitpos: [7:0]; default: 0;
+ *  this field configures block34 Y mean data
+ */
+#define ISP_AE_B34_MEAN    0x000000FFU
+#define ISP_AE_B34_MEAN_M  (ISP_AE_B34_MEAN_V << ISP_AE_B34_MEAN_S)
+#define ISP_AE_B34_MEAN_V  0x000000FFU
+#define ISP_AE_B34_MEAN_S  0
+/** ISP_AE_B33_MEAN : RO; bitpos: [15:8]; default: 0;
+ *  this field configures block33 Y mean data
+ */
+#define ISP_AE_B33_MEAN    0x000000FFU
+#define ISP_AE_B33_MEAN_M  (ISP_AE_B33_MEAN_V << ISP_AE_B33_MEAN_S)
+#define ISP_AE_B33_MEAN_V  0x000000FFU
+#define ISP_AE_B33_MEAN_S  8
+/** ISP_AE_B32_MEAN : RO; bitpos: [23:16]; default: 0;
+ *  this field configures block32 Y mean data
+ */
+#define ISP_AE_B32_MEAN    0x000000FFU
+#define ISP_AE_B32_MEAN_M  (ISP_AE_B32_MEAN_V << ISP_AE_B32_MEAN_S)
+#define ISP_AE_B32_MEAN_V  0x000000FFU
+#define ISP_AE_B32_MEAN_S  16
+/** ISP_AE_B31_MEAN : RO; bitpos: [31:24]; default: 0;
+ *  this field configures block31 Y mean data
+ */
+#define ISP_AE_B31_MEAN    0x000000FFU
+#define ISP_AE_B31_MEAN_M  (ISP_AE_B31_MEAN_V << ISP_AE_B31_MEAN_S)
+#define ISP_AE_B31_MEAN_V  0x000000FFU
+#define ISP_AE_B31_MEAN_S  24
+
+/** ISP_AE_BLOCK_MEAN_5_REG register
+ *  ae statistic result register 5
+ */
+#define ISP_AE_BLOCK_MEAN_5_REG (DR_REG_ISP_BASE + 0xec)
+/** ISP_AE_B43_MEAN : RO; bitpos: [7:0]; default: 0;
+ *  this field configures block43 Y mean data
+ */
+#define ISP_AE_B43_MEAN    0x000000FFU
+#define ISP_AE_B43_MEAN_M  (ISP_AE_B43_MEAN_V << ISP_AE_B43_MEAN_S)
+#define ISP_AE_B43_MEAN_V  0x000000FFU
+#define ISP_AE_B43_MEAN_S  0
+/** ISP_AE_B42_MEAN : RO; bitpos: [15:8]; default: 0;
+ *  this field configures block42 Y mean data
+ */
+#define ISP_AE_B42_MEAN    0x000000FFU
+#define ISP_AE_B42_MEAN_M  (ISP_AE_B42_MEAN_V << ISP_AE_B42_MEAN_S)
+#define ISP_AE_B42_MEAN_V  0x000000FFU
+#define ISP_AE_B42_MEAN_S  8
+/** ISP_AE_B41_MEAN : RO; bitpos: [23:16]; default: 0;
+ *  this field configures block41 Y mean data
+ */
+#define ISP_AE_B41_MEAN    0x000000FFU
+#define ISP_AE_B41_MEAN_M  (ISP_AE_B41_MEAN_V << ISP_AE_B41_MEAN_S)
+#define ISP_AE_B41_MEAN_V  0x000000FFU
+#define ISP_AE_B41_MEAN_S  16
+/** ISP_AE_B40_MEAN : RO; bitpos: [31:24]; default: 0;
+ *  this field configures block40 Y mean data
+ */
+#define ISP_AE_B40_MEAN    0x000000FFU
+#define ISP_AE_B40_MEAN_M  (ISP_AE_B40_MEAN_V << ISP_AE_B40_MEAN_S)
+#define ISP_AE_B40_MEAN_V  0x000000FFU
+#define ISP_AE_B40_MEAN_S  24
+
+/** ISP_AE_BLOCK_MEAN_6_REG register
+ *  ae statistic result register 6
+ */
+#define ISP_AE_BLOCK_MEAN_6_REG (DR_REG_ISP_BASE + 0xf0)
+/** ISP_AE_B44_MEAN : RO; bitpos: [31:24]; default: 0;
+ *  this field configures block44 Y mean data
+ */
+#define ISP_AE_B44_MEAN    0x000000FFU
+#define ISP_AE_B44_MEAN_M  (ISP_AE_B44_MEAN_V << ISP_AE_B44_MEAN_S)
+#define ISP_AE_B44_MEAN_V  0x000000FFU
+#define ISP_AE_B44_MEAN_S  24
+
+/** ISP_SHARP_CTRL0_REG register
+ *  sharp control register 0
+ */
+#define ISP_SHARP_CTRL0_REG (DR_REG_ISP_BASE + 0xf4)
+/** ISP_SHARP_THRESHOLD_LOW : R/W; bitpos: [7:0]; default: 0;
+ *  this field configures sharpen threshold for detail
+ */
+#define ISP_SHARP_THRESHOLD_LOW    0x000000FFU
+#define ISP_SHARP_THRESHOLD_LOW_M  (ISP_SHARP_THRESHOLD_LOW_V << ISP_SHARP_THRESHOLD_LOW_S)
+#define ISP_SHARP_THRESHOLD_LOW_V  0x000000FFU
+#define ISP_SHARP_THRESHOLD_LOW_S  0
+/** ISP_SHARP_THRESHOLD_HIGH : R/W; bitpos: [15:8]; default: 0;
+ *  this field configures sharpen threshold for edge
+ */
+#define ISP_SHARP_THRESHOLD_HIGH    0x000000FFU
+#define ISP_SHARP_THRESHOLD_HIGH_M  (ISP_SHARP_THRESHOLD_HIGH_V << ISP_SHARP_THRESHOLD_HIGH_S)
+#define ISP_SHARP_THRESHOLD_HIGH_V  0x000000FFU
+#define ISP_SHARP_THRESHOLD_HIGH_S  8
+/** ISP_SHARP_AMOUNT_LOW : R/W; bitpos: [23:16]; default: 0;
+ *  this field configures sharpen amount for detail
+ */
+#define ISP_SHARP_AMOUNT_LOW    0x000000FFU
+#define ISP_SHARP_AMOUNT_LOW_M  (ISP_SHARP_AMOUNT_LOW_V << ISP_SHARP_AMOUNT_LOW_S)
+#define ISP_SHARP_AMOUNT_LOW_V  0x000000FFU
+#define ISP_SHARP_AMOUNT_LOW_S  16
+/** ISP_SHARP_AMOUNT_HIGH : R/W; bitpos: [31:24]; default: 0;
+ *  this field configures sharpen amount for edge
+ */
+#define ISP_SHARP_AMOUNT_HIGH    0x000000FFU
+#define ISP_SHARP_AMOUNT_HIGH_M  (ISP_SHARP_AMOUNT_HIGH_V << ISP_SHARP_AMOUNT_HIGH_S)
+#define ISP_SHARP_AMOUNT_HIGH_V  0x000000FFU
+#define ISP_SHARP_AMOUNT_HIGH_S  24
+
+/** ISP_SHARP_FILTER0_REG register
+ *  sharp usm config register 0
+ */
+#define ISP_SHARP_FILTER0_REG (DR_REG_ISP_BASE + 0xf8)
+/** ISP_SHARP_FILTER_COE00 : R/W; bitpos: [4:0]; default: 1;
+ *  this field configures unsharp masking(usm) filter coefficient
+ */
+#define ISP_SHARP_FILTER_COE00    0x0000001FU
+#define ISP_SHARP_FILTER_COE00_M  (ISP_SHARP_FILTER_COE00_V << ISP_SHARP_FILTER_COE00_S)
+#define ISP_SHARP_FILTER_COE00_V  0x0000001FU
+#define ISP_SHARP_FILTER_COE00_S  0
+/** ISP_SHARP_FILTER_COE01 : R/W; bitpos: [9:5]; default: 2;
+ *  this field configures usm filter coefficient
+ */
+#define ISP_SHARP_FILTER_COE01    0x0000001FU
+#define ISP_SHARP_FILTER_COE01_M  (ISP_SHARP_FILTER_COE01_V << ISP_SHARP_FILTER_COE01_S)
+#define ISP_SHARP_FILTER_COE01_V  0x0000001FU
+#define ISP_SHARP_FILTER_COE01_S  5
+/** ISP_SHARP_FILTER_COE02 : R/W; bitpos: [14:10]; default: 1;
+ *  this field configures usm filter coefficient
+ */
+#define ISP_SHARP_FILTER_COE02    0x0000001FU
+#define ISP_SHARP_FILTER_COE02_M  (ISP_SHARP_FILTER_COE02_V << ISP_SHARP_FILTER_COE02_S)
+#define ISP_SHARP_FILTER_COE02_V  0x0000001FU
+#define ISP_SHARP_FILTER_COE02_S  10
+
+/** ISP_SHARP_FILTER1_REG register
+ *  sharp usm config register 1
+ */
+#define ISP_SHARP_FILTER1_REG (DR_REG_ISP_BASE + 0xfc)
+/** ISP_SHARP_FILTER_COE10 : R/W; bitpos: [4:0]; default: 2;
+ *  this field configures usm filter coefficient
+ */
+#define ISP_SHARP_FILTER_COE10    0x0000001FU
+#define ISP_SHARP_FILTER_COE10_M  (ISP_SHARP_FILTER_COE10_V << ISP_SHARP_FILTER_COE10_S)
+#define ISP_SHARP_FILTER_COE10_V  0x0000001FU
+#define ISP_SHARP_FILTER_COE10_S  0
+/** ISP_SHARP_FILTER_COE11 : R/W; bitpos: [9:5]; default: 4;
+ *  this field configures usm filter coefficient
+ */
+#define ISP_SHARP_FILTER_COE11    0x0000001FU
+#define ISP_SHARP_FILTER_COE11_M  (ISP_SHARP_FILTER_COE11_V << ISP_SHARP_FILTER_COE11_S)
+#define ISP_SHARP_FILTER_COE11_V  0x0000001FU
+#define ISP_SHARP_FILTER_COE11_S  5
+/** ISP_SHARP_FILTER_COE12 : R/W; bitpos: [14:10]; default: 2;
+ *  this field configures usm filter coefficient
+ */
+#define ISP_SHARP_FILTER_COE12    0x0000001FU
+#define ISP_SHARP_FILTER_COE12_M  (ISP_SHARP_FILTER_COE12_V << ISP_SHARP_FILTER_COE12_S)
+#define ISP_SHARP_FILTER_COE12_V  0x0000001FU
+#define ISP_SHARP_FILTER_COE12_S  10
+
+/** ISP_SHARP_FILTER2_REG register
+ *  sharp usm config register 2
+ */
+#define ISP_SHARP_FILTER2_REG (DR_REG_ISP_BASE + 0x100)
+/** ISP_SHARP_FILTER_COE20 : R/W; bitpos: [4:0]; default: 1;
+ *  this field configures usm filter coefficient
+ */
+#define ISP_SHARP_FILTER_COE20    0x0000001FU
+#define ISP_SHARP_FILTER_COE20_M  (ISP_SHARP_FILTER_COE20_V << ISP_SHARP_FILTER_COE20_S)
+#define ISP_SHARP_FILTER_COE20_V  0x0000001FU
+#define ISP_SHARP_FILTER_COE20_S  0
+/** ISP_SHARP_FILTER_COE21 : R/W; bitpos: [9:5]; default: 2;
+ *  this field configures usm filter coefficient
+ */
+#define ISP_SHARP_FILTER_COE21    0x0000001FU
+#define ISP_SHARP_FILTER_COE21_M  (ISP_SHARP_FILTER_COE21_V << ISP_SHARP_FILTER_COE21_S)
+#define ISP_SHARP_FILTER_COE21_V  0x0000001FU
+#define ISP_SHARP_FILTER_COE21_S  5
+/** ISP_SHARP_FILTER_COE22 : R/W; bitpos: [14:10]; default: 1;
+ *  this field configures usm filter coefficient
+ */
+#define ISP_SHARP_FILTER_COE22    0x0000001FU
+#define ISP_SHARP_FILTER_COE22_M  (ISP_SHARP_FILTER_COE22_V << ISP_SHARP_FILTER_COE22_S)
+#define ISP_SHARP_FILTER_COE22_V  0x0000001FU
+#define ISP_SHARP_FILTER_COE22_S  10
+
+/** ISP_SHARP_MATRIX_CTRL_REG register
+ *  sharp pix2matrix ctrl
+ */
+#define ISP_SHARP_MATRIX_CTRL_REG (DR_REG_ISP_BASE + 0x104)
+/** ISP_SHARP_TAIL_PIXEN_PULSE_TL : R/W; bitpos: [7:0]; default: 0;
+ *  matrix tail pixen low level threshold,  should not to large to prevent expanding to
+ *  next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and
+ *  reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th <
+ *  reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function
+ */
+#define ISP_SHARP_TAIL_PIXEN_PULSE_TL    0x000000FFU
+#define ISP_SHARP_TAIL_PIXEN_PULSE_TL_M  (ISP_SHARP_TAIL_PIXEN_PULSE_TL_V << ISP_SHARP_TAIL_PIXEN_PULSE_TL_S)
+#define ISP_SHARP_TAIL_PIXEN_PULSE_TL_V  0x000000FFU
+#define ISP_SHARP_TAIL_PIXEN_PULSE_TL_S  0
+/** ISP_SHARP_TAIL_PIXEN_PULSE_TH : R/W; bitpos: [15:8]; default: 0;
+ *  matrix tail pixen high level threshold, must < hnum-1, only
+ *  reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and
+ *  reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail
+ *  pulse function
+ */
+#define ISP_SHARP_TAIL_PIXEN_PULSE_TH    0x000000FFU
+#define ISP_SHARP_TAIL_PIXEN_PULSE_TH_M  (ISP_SHARP_TAIL_PIXEN_PULSE_TH_V << ISP_SHARP_TAIL_PIXEN_PULSE_TH_S)
+#define ISP_SHARP_TAIL_PIXEN_PULSE_TH_V  0x000000FFU
+#define ISP_SHARP_TAIL_PIXEN_PULSE_TH_S  8
+/** ISP_SHARP_PADDING_DATA : R/W; bitpos: [23:16]; default: 0;
+ *  this field configures sharp padding data
+ */
+#define ISP_SHARP_PADDING_DATA    0x000000FFU
+#define ISP_SHARP_PADDING_DATA_M  (ISP_SHARP_PADDING_DATA_V << ISP_SHARP_PADDING_DATA_S)
+#define ISP_SHARP_PADDING_DATA_V  0x000000FFU
+#define ISP_SHARP_PADDING_DATA_S  16
+/** ISP_SHARP_PADDING_MODE : R/W; bitpos: [24]; default: 0;
+ *  this field configures sharp padding mode
+ */
+#define ISP_SHARP_PADDING_MODE    (BIT(24))
+#define ISP_SHARP_PADDING_MODE_M  (ISP_SHARP_PADDING_MODE_V << ISP_SHARP_PADDING_MODE_S)
+#define ISP_SHARP_PADDING_MODE_V  0x00000001U
+#define ISP_SHARP_PADDING_MODE_S  24
+
+/** ISP_SHARP_CTRL1_REG register
+ *  sharp control register 1
+ */
+#define ISP_SHARP_CTRL1_REG (DR_REG_ISP_BASE + 0x108)
+/** ISP_SHARP_GRADIENT_MAX : RO; bitpos: [7:0]; default: 0;
+ *  this field configures sharp max gradient, refresh at the end of each frame end
+ */
+#define ISP_SHARP_GRADIENT_MAX    0x000000FFU
+#define ISP_SHARP_GRADIENT_MAX_M  (ISP_SHARP_GRADIENT_MAX_V << ISP_SHARP_GRADIENT_MAX_S)
+#define ISP_SHARP_GRADIENT_MAX_V  0x000000FFU
+#define ISP_SHARP_GRADIENT_MAX_S  0
+
+/** ISP_DMA_CNTL_REG register
+ *  isp dma source trans control register
+ */
+#define ISP_DMA_CNTL_REG (DR_REG_ISP_BASE + 0x10c)
+/** ISP_DMA_EN : WT; bitpos: [0]; default: 0;
+ *  write 1 to trigger dma to get 1 frame
+ */
+#define ISP_DMA_EN    (BIT(0))
+#define ISP_DMA_EN_M  (ISP_DMA_EN_V << ISP_DMA_EN_S)
+#define ISP_DMA_EN_V  0x00000001U
+#define ISP_DMA_EN_S  0
+/** ISP_DMA_UPDATE_REG : R/W; bitpos: [1]; default: 0;
+ *  write 1 to update reg_dma_burst_len & reg_dma_data_type
+ */
+#define ISP_DMA_UPDATE_REG    (BIT(1))
+#define ISP_DMA_UPDATE_REG_M  (ISP_DMA_UPDATE_REG_V << ISP_DMA_UPDATE_REG_S)
+#define ISP_DMA_UPDATE_REG_V  0x00000001U
+#define ISP_DMA_UPDATE_REG_S  1
+/** ISP_DMA_DATA_TYPE : R/W; bitpos: [7:2]; default: 42;
+ *  this field configures the idi data type for image data
+ */
+#define ISP_DMA_DATA_TYPE    0x0000003FU
+#define ISP_DMA_DATA_TYPE_M  (ISP_DMA_DATA_TYPE_V << ISP_DMA_DATA_TYPE_S)
+#define ISP_DMA_DATA_TYPE_V  0x0000003FU
+#define ISP_DMA_DATA_TYPE_S  2
+/** ISP_DMA_BURST_LEN : R/W; bitpos: [19:8]; default: 128;
+ *  this field configures dma burst len when data source is dma. set according to
+ *  dma_msize, it is the number of 64bits in a dma transfer
+ */
+#define ISP_DMA_BURST_LEN    0x00000FFFU
+#define ISP_DMA_BURST_LEN_M  (ISP_DMA_BURST_LEN_V << ISP_DMA_BURST_LEN_S)
+#define ISP_DMA_BURST_LEN_V  0x00000FFFU
+#define ISP_DMA_BURST_LEN_S  8
+/** ISP_DMA_INTERVAL : R/W; bitpos: [31:20]; default: 1;
+ *  this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ...
+ */
+#define ISP_DMA_INTERVAL    0x00000FFFU
+#define ISP_DMA_INTERVAL_M  (ISP_DMA_INTERVAL_V << ISP_DMA_INTERVAL_S)
+#define ISP_DMA_INTERVAL_V  0x00000FFFU
+#define ISP_DMA_INTERVAL_S  20
+
+/** ISP_DMA_RAW_DATA_REG register
+ *  isp dma source total raw number set register
+ */
+#define ISP_DMA_RAW_DATA_REG (DR_REG_ISP_BASE + 0x110)
+/** ISP_DMA_RAW_NUM_TOTAL : R/W; bitpos: [21:0]; default: 0;
+ *  this field configures the the number of 64bits in a frame
+ */
+#define ISP_DMA_RAW_NUM_TOTAL    0x003FFFFFU
+#define ISP_DMA_RAW_NUM_TOTAL_M  (ISP_DMA_RAW_NUM_TOTAL_V << ISP_DMA_RAW_NUM_TOTAL_S)
+#define ISP_DMA_RAW_NUM_TOTAL_V  0x003FFFFFU
+#define ISP_DMA_RAW_NUM_TOTAL_S  0
+/** ISP_DMA_RAW_NUM_TOTAL_SET : WT; bitpos: [31]; default: 0;
+ *  write 1 to update reg_dma_raw_num_total
+ */
+#define ISP_DMA_RAW_NUM_TOTAL_SET    (BIT(31))
+#define ISP_DMA_RAW_NUM_TOTAL_SET_M  (ISP_DMA_RAW_NUM_TOTAL_SET_V << ISP_DMA_RAW_NUM_TOTAL_SET_S)
+#define ISP_DMA_RAW_NUM_TOTAL_SET_V  0x00000001U
+#define ISP_DMA_RAW_NUM_TOTAL_SET_S  31
+
+/** ISP_CAM_CNTL_REG register
+ *  isp cam source control register
+ */
+#define ISP_CAM_CNTL_REG (DR_REG_ISP_BASE + 0x114)
+/** ISP_CAM_EN : R/W; bitpos: [0]; default: 0;
+ *  write 1 to start receive camera data, write 0 to disable
+ */
+#define ISP_CAM_EN    (BIT(0))
+#define ISP_CAM_EN_M  (ISP_CAM_EN_V << ISP_CAM_EN_S)
+#define ISP_CAM_EN_V  0x00000001U
+#define ISP_CAM_EN_S  0
+/** ISP_CAM_UPDATE_REG : R/W; bitpos: [1]; default: 0;
+ *  write 1 to update ISP_CAM_CONF
+ */
+#define ISP_CAM_UPDATE_REG    (BIT(1))
+#define ISP_CAM_UPDATE_REG_M  (ISP_CAM_UPDATE_REG_V << ISP_CAM_UPDATE_REG_S)
+#define ISP_CAM_UPDATE_REG_V  0x00000001U
+#define ISP_CAM_UPDATE_REG_S  1
+/** ISP_CAM_RESET : R/W; bitpos: [2]; default: 1;
+ *  this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset
+ */
+#define ISP_CAM_RESET    (BIT(2))
+#define ISP_CAM_RESET_M  (ISP_CAM_RESET_V << ISP_CAM_RESET_S)
+#define ISP_CAM_RESET_V  0x00000001U
+#define ISP_CAM_RESET_S  2
+/** ISP_CAM_CLK_INV : R/W; bitpos: [3]; default: 0;
+ *  this bit configures the inversion of cam clk from pad. 0: not invert cam clk, 1:
+ *  invert cam clk
+ */
+#define ISP_CAM_CLK_INV    (BIT(3))
+#define ISP_CAM_CLK_INV_M  (ISP_CAM_CLK_INV_V << ISP_CAM_CLK_INV_S)
+#define ISP_CAM_CLK_INV_V  0x00000001U
+#define ISP_CAM_CLK_INV_S  3
+
+/** ISP_CAM_CONF_REG register
+ *  isp cam source config register
+ */
+#define ISP_CAM_CONF_REG (DR_REG_ISP_BASE + 0x118)
+/** ISP_CAM_DATA_ORDER : R/W; bitpos: [0]; default: 0;
+ *  this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0],
+ *  cam_data_in[15:8]}
+ */
+#define ISP_CAM_DATA_ORDER    (BIT(0))
+#define ISP_CAM_DATA_ORDER_M  (ISP_CAM_DATA_ORDER_V << ISP_CAM_DATA_ORDER_S)
+#define ISP_CAM_DATA_ORDER_V  0x00000001U
+#define ISP_CAM_DATA_ORDER_S  0
+/** ISP_CAM_2BYTE_MODE : R/W; bitpos: [1]; default: 0;
+ *  this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0:
+ *  disable, 1: enable
+ */
+#define ISP_CAM_2BYTE_MODE    (BIT(1))
+#define ISP_CAM_2BYTE_MODE_M  (ISP_CAM_2BYTE_MODE_V << ISP_CAM_2BYTE_MODE_S)
+#define ISP_CAM_2BYTE_MODE_V  0x00000001U
+#define ISP_CAM_2BYTE_MODE_S  1
+/** ISP_CAM_DATA_TYPE : R/W; bitpos: [7:2]; default: 42;
+ *  this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c:
+ *  RAW12
+ */
+#define ISP_CAM_DATA_TYPE    0x0000003FU
+#define ISP_CAM_DATA_TYPE_M  (ISP_CAM_DATA_TYPE_V << ISP_CAM_DATA_TYPE_S)
+#define ISP_CAM_DATA_TYPE_V  0x0000003FU
+#define ISP_CAM_DATA_TYPE_S  2
+/** ISP_CAM_DE_INV : R/W; bitpos: [8]; default: 0;
+ *  this bit configures cam data enable invert. 0: not invert, 1: invert
+ */
+#define ISP_CAM_DE_INV    (BIT(8))
+#define ISP_CAM_DE_INV_M  (ISP_CAM_DE_INV_V << ISP_CAM_DE_INV_S)
+#define ISP_CAM_DE_INV_V  0x00000001U
+#define ISP_CAM_DE_INV_S  8
+/** ISP_CAM_HSYNC_INV : R/W; bitpos: [9]; default: 0;
+ *  this bit configures cam hsync invert. 0: not invert, 1: invert
+ */
+#define ISP_CAM_HSYNC_INV    (BIT(9))
+#define ISP_CAM_HSYNC_INV_M  (ISP_CAM_HSYNC_INV_V << ISP_CAM_HSYNC_INV_S)
+#define ISP_CAM_HSYNC_INV_V  0x00000001U
+#define ISP_CAM_HSYNC_INV_S  9
+/** ISP_CAM_VSYNC_INV : R/W; bitpos: [10]; default: 0;
+ *  this bit configures cam vsync invert. 0: not invert, 1: invert
+ */
+#define ISP_CAM_VSYNC_INV    (BIT(10))
+#define ISP_CAM_VSYNC_INV_M  (ISP_CAM_VSYNC_INV_V << ISP_CAM_VSYNC_INV_S)
+#define ISP_CAM_VSYNC_INV_V  0x00000001U
+#define ISP_CAM_VSYNC_INV_S  10
+/** ISP_CAM_VSYNC_FILTER_THRES : R/W; bitpos: [13:11]; default: 0;
+ *  this bit configures the number of clock of vsync filter length
+ */
+#define ISP_CAM_VSYNC_FILTER_THRES    0x00000007U
+#define ISP_CAM_VSYNC_FILTER_THRES_M  (ISP_CAM_VSYNC_FILTER_THRES_V << ISP_CAM_VSYNC_FILTER_THRES_S)
+#define ISP_CAM_VSYNC_FILTER_THRES_V  0x00000007U
+#define ISP_CAM_VSYNC_FILTER_THRES_S  11
+/** ISP_CAM_VSYNC_FILTER_EN : R/W; bitpos: [14]; default: 0;
+ *  this bit configures vsync filter en
+ */
+#define ISP_CAM_VSYNC_FILTER_EN    (BIT(14))
+#define ISP_CAM_VSYNC_FILTER_EN_M  (ISP_CAM_VSYNC_FILTER_EN_V << ISP_CAM_VSYNC_FILTER_EN_S)
+#define ISP_CAM_VSYNC_FILTER_EN_V  0x00000001U
+#define ISP_CAM_VSYNC_FILTER_EN_S  14
+/** ISP_CAM_DE_ONLY : R/W; bitpos: [15]; default: 0;
+ *  configures whether cam inf only has de, no hsync data. 0: has hsync, 1: no hsync
+ */
+#define ISP_CAM_DE_ONLY    (BIT(15))
+#define ISP_CAM_DE_ONLY_M  (ISP_CAM_DE_ONLY_V << ISP_CAM_DE_ONLY_S)
+#define ISP_CAM_DE_ONLY_V  0x00000001U
+#define ISP_CAM_DE_ONLY_S  15
+
+/** ISP_AF_CTRL0_REG register
+ *  af control register 0
+ */
+#define ISP_AF_CTRL0_REG (DR_REG_ISP_BASE + 0x11c)
+/** ISP_AF_AUTO_UPDATE : R/W; bitpos: [0]; default: 0;
+ *  this bit configures auto_update enable. when set to 1, will update sum and lum each
+ *  frame
+ */
+#define ISP_AF_AUTO_UPDATE    (BIT(0))
+#define ISP_AF_AUTO_UPDATE_M  (ISP_AF_AUTO_UPDATE_V << ISP_AF_AUTO_UPDATE_S)
+#define ISP_AF_AUTO_UPDATE_V  0x00000001U
+#define ISP_AF_AUTO_UPDATE_S  0
+/** ISP_AF_MANUAL_UPDATE : WT; bitpos: [4]; default: 0;
+ *  write 1 to this bit will update the sum and lum once
+ */
+#define ISP_AF_MANUAL_UPDATE    (BIT(4))
+#define ISP_AF_MANUAL_UPDATE_M  (ISP_AF_MANUAL_UPDATE_V << ISP_AF_MANUAL_UPDATE_S)
+#define ISP_AF_MANUAL_UPDATE_V  0x00000001U
+#define ISP_AF_MANUAL_UPDATE_S  4
+/** ISP_AF_ENV_THRESHOLD : R/W; bitpos: [11:8]; default: 0;
+ *  this field configures env threshold. when both sum and lum changes larger than this
+ *  value, consider environment changes and need to trigger a new autofocus. 4Bit
+ *  fractional
+ */
+#define ISP_AF_ENV_THRESHOLD    0x0000000FU
+#define ISP_AF_ENV_THRESHOLD_M  (ISP_AF_ENV_THRESHOLD_V << ISP_AF_ENV_THRESHOLD_S)
+#define ISP_AF_ENV_THRESHOLD_V  0x0000000FU
+#define ISP_AF_ENV_THRESHOLD_S  8
+/** ISP_AF_ENV_PERIOD : R/W; bitpos: [23:16]; default: 0;
+ *  this field configures environment changes detection period (frame). When set to 0,
+ *  disable this function
+ */
+#define ISP_AF_ENV_PERIOD    0x000000FFU
+#define ISP_AF_ENV_PERIOD_M  (ISP_AF_ENV_PERIOD_V << ISP_AF_ENV_PERIOD_S)
+#define ISP_AF_ENV_PERIOD_V  0x000000FFU
+#define ISP_AF_ENV_PERIOD_S  16
+
+/** ISP_AF_CTRL1_REG register
+ *  af control register 1
+ */
+#define ISP_AF_CTRL1_REG (DR_REG_ISP_BASE + 0x120)
+/** ISP_AF_THPIXNUM : R/W; bitpos: [21:0]; default: 0;
+ *  this field configures pixnum used when calculating the autofocus threshold. Set to
+ *  0 to disable threshold calculation
+ */
+#define ISP_AF_THPIXNUM    0x003FFFFFU
+#define ISP_AF_THPIXNUM_M  (ISP_AF_THPIXNUM_V << ISP_AF_THPIXNUM_S)
+#define ISP_AF_THPIXNUM_V  0x003FFFFFU
+#define ISP_AF_THPIXNUM_S  0
+
+/** ISP_AF_GEN_TH_CTRL_REG register
+ *  af gen threshold control register
+ */
+#define ISP_AF_GEN_TH_CTRL_REG (DR_REG_ISP_BASE + 0x124)
+/** ISP_AF_GEN_THRESHOLD_MIN : R/W; bitpos: [15:0]; default: 128;
+ *  this field configures min threshold when use auto_threshold
+ */
+#define ISP_AF_GEN_THRESHOLD_MIN    0x0000FFFFU
+#define ISP_AF_GEN_THRESHOLD_MIN_M  (ISP_AF_GEN_THRESHOLD_MIN_V << ISP_AF_GEN_THRESHOLD_MIN_S)
+#define ISP_AF_GEN_THRESHOLD_MIN_V  0x0000FFFFU
+#define ISP_AF_GEN_THRESHOLD_MIN_S  0
+/** ISP_AF_GEN_THRESHOLD_MAX : R/W; bitpos: [31:16]; default: 1088;
+ *  this field configures max threshold when use auto_threshold
+ */
+#define ISP_AF_GEN_THRESHOLD_MAX    0x0000FFFFU
+#define ISP_AF_GEN_THRESHOLD_MAX_M  (ISP_AF_GEN_THRESHOLD_MAX_V << ISP_AF_GEN_THRESHOLD_MAX_S)
+#define ISP_AF_GEN_THRESHOLD_MAX_V  0x0000FFFFU
+#define ISP_AF_GEN_THRESHOLD_MAX_S  16
+
+/** ISP_AF_ENV_USER_TH_SUM_REG register
+ *  af monitor user sum threshold register
+ */
+#define ISP_AF_ENV_USER_TH_SUM_REG (DR_REG_ISP_BASE + 0x128)
+/** ISP_AF_ENV_USER_THRESHOLD_SUM : R/W; bitpos: [31:0]; default: 0;
+ *  this field configures user setup env detect sum threshold
+ */
+#define ISP_AF_ENV_USER_THRESHOLD_SUM    0xFFFFFFFFU
+#define ISP_AF_ENV_USER_THRESHOLD_SUM_M  (ISP_AF_ENV_USER_THRESHOLD_SUM_V << ISP_AF_ENV_USER_THRESHOLD_SUM_S)
+#define ISP_AF_ENV_USER_THRESHOLD_SUM_V  0xFFFFFFFFU
+#define ISP_AF_ENV_USER_THRESHOLD_SUM_S  0
+
+/** ISP_AF_ENV_USER_TH_LUM_REG register
+ *  af monitor user lum threshold register
+ */
+#define ISP_AF_ENV_USER_TH_LUM_REG (DR_REG_ISP_BASE + 0x12c)
+/** ISP_AF_ENV_USER_THRESHOLD_LUM : R/W; bitpos: [29:0]; default: 0;
+ *  this field configures user setup env detect lum threshold
+ */
+#define ISP_AF_ENV_USER_THRESHOLD_LUM    0x3FFFFFFFU
+#define ISP_AF_ENV_USER_THRESHOLD_LUM_M  (ISP_AF_ENV_USER_THRESHOLD_LUM_V << ISP_AF_ENV_USER_THRESHOLD_LUM_S)
+#define ISP_AF_ENV_USER_THRESHOLD_LUM_V  0x3FFFFFFFU
+#define ISP_AF_ENV_USER_THRESHOLD_LUM_S  0
+
+/** ISP_AF_THRESHOLD_REG register
+ *  af threshold register
+ */
+#define ISP_AF_THRESHOLD_REG (DR_REG_ISP_BASE + 0x130)
+/** ISP_AF_THRESHOLD : R/W; bitpos: [15:0]; default: 256;
+ *  this field configures user threshold. When set to non-zero, autofocus will use this
+ *  threshold
+ */
+#define ISP_AF_THRESHOLD    0x0000FFFFU
+#define ISP_AF_THRESHOLD_M  (ISP_AF_THRESHOLD_V << ISP_AF_THRESHOLD_S)
+#define ISP_AF_THRESHOLD_V  0x0000FFFFU
+#define ISP_AF_THRESHOLD_S  0
+/** ISP_AF_GEN_THRESHOLD : RO; bitpos: [31:16]; default: 0;
+ *  this field represents the last calculated threshold
+ */
+#define ISP_AF_GEN_THRESHOLD    0x0000FFFFU
+#define ISP_AF_GEN_THRESHOLD_M  (ISP_AF_GEN_THRESHOLD_V << ISP_AF_GEN_THRESHOLD_S)
+#define ISP_AF_GEN_THRESHOLD_V  0x0000FFFFU
+#define ISP_AF_GEN_THRESHOLD_S  16
+
+/** ISP_AF_HSCALE_A_REG register
+ *  h-scale of af window a register
+ */
+#define ISP_AF_HSCALE_A_REG (DR_REG_ISP_BASE + 0x134)
+/** ISP_AF_RPOINT_A : R/W; bitpos: [11:0]; default: 128;
+ *  this field configures left coordinate of focus window a, must >= 2
+ */
+#define ISP_AF_RPOINT_A    0x00000FFFU
+#define ISP_AF_RPOINT_A_M  (ISP_AF_RPOINT_A_V << ISP_AF_RPOINT_A_S)
+#define ISP_AF_RPOINT_A_V  0x00000FFFU
+#define ISP_AF_RPOINT_A_S  0
+/** ISP_AF_LPOINT_A : R/W; bitpos: [27:16]; default: 1;
+ *  this field configures top coordinate of focus window a, must >= 2
+ */
+#define ISP_AF_LPOINT_A    0x00000FFFU
+#define ISP_AF_LPOINT_A_M  (ISP_AF_LPOINT_A_V << ISP_AF_LPOINT_A_S)
+#define ISP_AF_LPOINT_A_V  0x00000FFFU
+#define ISP_AF_LPOINT_A_S  16
+
+/** ISP_AF_VSCALE_A_REG register
+ *  v-scale of af window a register
+ */
+#define ISP_AF_VSCALE_A_REG (DR_REG_ISP_BASE + 0x138)
+/** ISP_AF_BPOINT_A : R/W; bitpos: [11:0]; default: 128;
+ *  this field configures right coordinate of focus window a, must <= hnum-2
+ */
+#define ISP_AF_BPOINT_A    0x00000FFFU
+#define ISP_AF_BPOINT_A_M  (ISP_AF_BPOINT_A_V << ISP_AF_BPOINT_A_S)
+#define ISP_AF_BPOINT_A_V  0x00000FFFU
+#define ISP_AF_BPOINT_A_S  0
+/** ISP_AF_TPOINT_A : R/W; bitpos: [27:16]; default: 1;
+ *  this field configures bottom coordinate of focus window a, must <= hnum-2
+ */
+#define ISP_AF_TPOINT_A    0x00000FFFU
+#define ISP_AF_TPOINT_A_M  (ISP_AF_TPOINT_A_V << ISP_AF_TPOINT_A_S)
+#define ISP_AF_TPOINT_A_V  0x00000FFFU
+#define ISP_AF_TPOINT_A_S  16
+
+/** ISP_AF_HSCALE_B_REG register
+ *  h-scale of af window b register
+ */
+#define ISP_AF_HSCALE_B_REG (DR_REG_ISP_BASE + 0x13c)
+/** ISP_AF_RPOINT_B : R/W; bitpos: [11:0]; default: 128;
+ *  this field configures left coordinate of focus window b, must >= 2
+ */
+#define ISP_AF_RPOINT_B    0x00000FFFU
+#define ISP_AF_RPOINT_B_M  (ISP_AF_RPOINT_B_V << ISP_AF_RPOINT_B_S)
+#define ISP_AF_RPOINT_B_V  0x00000FFFU
+#define ISP_AF_RPOINT_B_S  0
+/** ISP_AF_LPOINT_B : R/W; bitpos: [27:16]; default: 1;
+ *  this field configures top coordinate of focus window b, must >= 2
+ */
+#define ISP_AF_LPOINT_B    0x00000FFFU
+#define ISP_AF_LPOINT_B_M  (ISP_AF_LPOINT_B_V << ISP_AF_LPOINT_B_S)
+#define ISP_AF_LPOINT_B_V  0x00000FFFU
+#define ISP_AF_LPOINT_B_S  16
+
+/** ISP_AF_VSCALE_B_REG register
+ *  v-scale of af window b register
+ */
+#define ISP_AF_VSCALE_B_REG (DR_REG_ISP_BASE + 0x140)
+/** ISP_AF_BPOINT_B : R/W; bitpos: [11:0]; default: 128;
+ *  this field configures right coordinate of focus window b, must <= hnum-2
+ */
+#define ISP_AF_BPOINT_B    0x00000FFFU
+#define ISP_AF_BPOINT_B_M  (ISP_AF_BPOINT_B_V << ISP_AF_BPOINT_B_S)
+#define ISP_AF_BPOINT_B_V  0x00000FFFU
+#define ISP_AF_BPOINT_B_S  0
+/** ISP_AF_TPOINT_B : R/W; bitpos: [27:16]; default: 1;
+ *  this field configures bottom coordinate of focus window b, must <= hnum-2
+ */
+#define ISP_AF_TPOINT_B    0x00000FFFU
+#define ISP_AF_TPOINT_B_M  (ISP_AF_TPOINT_B_V << ISP_AF_TPOINT_B_S)
+#define ISP_AF_TPOINT_B_V  0x00000FFFU
+#define ISP_AF_TPOINT_B_S  16
+
+/** ISP_AF_HSCALE_C_REG register
+ *  v-scale of af window c register
+ */
+#define ISP_AF_HSCALE_C_REG (DR_REG_ISP_BASE + 0x144)
+/** ISP_AF_RPOINT_C : R/W; bitpos: [11:0]; default: 128;
+ *  this field configures left coordinate of focus window c, must >= 2
+ */
+#define ISP_AF_RPOINT_C    0x00000FFFU
+#define ISP_AF_RPOINT_C_M  (ISP_AF_RPOINT_C_V << ISP_AF_RPOINT_C_S)
+#define ISP_AF_RPOINT_C_V  0x00000FFFU
+#define ISP_AF_RPOINT_C_S  0
+/** ISP_AF_LPOINT_C : R/W; bitpos: [27:16]; default: 1;
+ *  this field configures top coordinate of focus window c, must >= 2
+ */
+#define ISP_AF_LPOINT_C    0x00000FFFU
+#define ISP_AF_LPOINT_C_M  (ISP_AF_LPOINT_C_V << ISP_AF_LPOINT_C_S)
+#define ISP_AF_LPOINT_C_V  0x00000FFFU
+#define ISP_AF_LPOINT_C_S  16
+
+/** ISP_AF_VSCALE_C_REG register
+ *  v-scale of af window c register
+ */
+#define ISP_AF_VSCALE_C_REG (DR_REG_ISP_BASE + 0x148)
+/** ISP_AF_BPOINT_C : R/W; bitpos: [11:0]; default: 128;
+ *  this field configures right coordinate of focus window c, must <= hnum-2
+ */
+#define ISP_AF_BPOINT_C    0x00000FFFU
+#define ISP_AF_BPOINT_C_M  (ISP_AF_BPOINT_C_V << ISP_AF_BPOINT_C_S)
+#define ISP_AF_BPOINT_C_V  0x00000FFFU
+#define ISP_AF_BPOINT_C_S  0
+/** ISP_AF_TPOINT_C : R/W; bitpos: [27:16]; default: 1;
+ *  this field configures bottom coordinate of focus window c, must <= hnum-2
+ */
+#define ISP_AF_TPOINT_C    0x00000FFFU
+#define ISP_AF_TPOINT_C_M  (ISP_AF_TPOINT_C_V << ISP_AF_TPOINT_C_S)
+#define ISP_AF_TPOINT_C_V  0x00000FFFU
+#define ISP_AF_TPOINT_C_S  16
+
+/** ISP_AF_SUM_A_REG register
+ *  result of sum of af window a
+ */
+#define ISP_AF_SUM_A_REG (DR_REG_ISP_BASE + 0x14c)
+/** ISP_AF_SUMA : RO; bitpos: [29:0]; default: 0;
+ *  this field represents the result of accumulation of pix grad of focus window a
+ */
+#define ISP_AF_SUMA    0x3FFFFFFFU
+#define ISP_AF_SUMA_M  (ISP_AF_SUMA_V << ISP_AF_SUMA_S)
+#define ISP_AF_SUMA_V  0x3FFFFFFFU
+#define ISP_AF_SUMA_S  0
+
+/** ISP_AF_SUM_B_REG register
+ *  result of sum of af window b
+ */
+#define ISP_AF_SUM_B_REG (DR_REG_ISP_BASE + 0x150)
+/** ISP_AF_SUMB : RO; bitpos: [29:0]; default: 0;
+ *  this field represents the result of accumulation of pix grad of focus window b
+ */
+#define ISP_AF_SUMB    0x3FFFFFFFU
+#define ISP_AF_SUMB_M  (ISP_AF_SUMB_V << ISP_AF_SUMB_S)
+#define ISP_AF_SUMB_V  0x3FFFFFFFU
+#define ISP_AF_SUMB_S  0
+
+/** ISP_AF_SUM_C_REG register
+ *  result of sum of af window c
+ */
+#define ISP_AF_SUM_C_REG (DR_REG_ISP_BASE + 0x154)
+/** ISP_AF_SUMC : RO; bitpos: [29:0]; default: 0;
+ *  this field represents the result of accumulation of pix grad of focus window c
+ */
+#define ISP_AF_SUMC    0x3FFFFFFFU
+#define ISP_AF_SUMC_M  (ISP_AF_SUMC_V << ISP_AF_SUMC_S)
+#define ISP_AF_SUMC_V  0x3FFFFFFFU
+#define ISP_AF_SUMC_S  0
+
+/** ISP_AF_LUM_A_REG register
+ *  result of lum of af window a
+ */
+#define ISP_AF_LUM_A_REG (DR_REG_ISP_BASE + 0x158)
+/** ISP_AF_LUMA : RO; bitpos: [27:0]; default: 0;
+ *  this field represents the result of accumulation of pix light of focus window a
+ */
+#define ISP_AF_LUMA    0x0FFFFFFFU
+#define ISP_AF_LUMA_M  (ISP_AF_LUMA_V << ISP_AF_LUMA_S)
+#define ISP_AF_LUMA_V  0x0FFFFFFFU
+#define ISP_AF_LUMA_S  0
+
+/** ISP_AF_LUM_B_REG register
+ *  result of lum of af window b
+ */
+#define ISP_AF_LUM_B_REG (DR_REG_ISP_BASE + 0x15c)
+/** ISP_AF_LUMB : RO; bitpos: [27:0]; default: 0;
+ *  this field represents the result of accumulation of pix light of focus window b
+ */
+#define ISP_AF_LUMB    0x0FFFFFFFU
+#define ISP_AF_LUMB_M  (ISP_AF_LUMB_V << ISP_AF_LUMB_S)
+#define ISP_AF_LUMB_V  0x0FFFFFFFU
+#define ISP_AF_LUMB_S  0
+
+/** ISP_AF_LUM_C_REG register
+ *  result of lum of af window c
+ */
+#define ISP_AF_LUM_C_REG (DR_REG_ISP_BASE + 0x160)
+/** ISP_AF_LUMC : RO; bitpos: [27:0]; default: 0;
+ *  this field represents the result of accumulation of pix light of focus window c
+ */
+#define ISP_AF_LUMC    0x0FFFFFFFU
+#define ISP_AF_LUMC_M  (ISP_AF_LUMC_V << ISP_AF_LUMC_S)
+#define ISP_AF_LUMC_V  0x0FFFFFFFU
+#define ISP_AF_LUMC_S  0
+
+/** ISP_AWB_MODE_REG register
+ *  awb mode control register
+ */
+#define ISP_AWB_MODE_REG (DR_REG_ISP_BASE + 0x164)
+/** ISP_AWB_MODE : R/W; bitpos: [1:0]; default: 3;
+ *  this field configures awb algo sel. 00: none selected. 01: sel algo0. 10: sel
+ *  algo1. 11: sel both algo0 and algo1
+ */
+#define ISP_AWB_MODE    0x00000003U
+#define ISP_AWB_MODE_M  (ISP_AWB_MODE_V << ISP_AWB_MODE_S)
+#define ISP_AWB_MODE_V  0x00000003U
+#define ISP_AWB_MODE_S  0
+/** ISP_AWB_SAMPLE : R/W; bitpos: [4]; default: 0;
+ *  this bit configures awb sample location, 0:before ccm, 1:after ccm
+ */
+#define ISP_AWB_SAMPLE    (BIT(4))
+#define ISP_AWB_SAMPLE_M  (ISP_AWB_SAMPLE_V << ISP_AWB_SAMPLE_S)
+#define ISP_AWB_SAMPLE_V  0x00000001U
+#define ISP_AWB_SAMPLE_S  4
+
+/** ISP_AWB_HSCALE_REG register
+ *  h-scale of awb window
+ */
+#define ISP_AWB_HSCALE_REG (DR_REG_ISP_BASE + 0x168)
+/** ISP_AWB_RPOINT : R/W; bitpos: [11:0]; default: 1919;
+ *  this field configures awb window right coordinate
+ */
+#define ISP_AWB_RPOINT    0x00000FFFU
+#define ISP_AWB_RPOINT_M  (ISP_AWB_RPOINT_V << ISP_AWB_RPOINT_S)
+#define ISP_AWB_RPOINT_V  0x00000FFFU
+#define ISP_AWB_RPOINT_S  0
+/** ISP_AWB_LPOINT : R/W; bitpos: [27:16]; default: 0;
+ *  this field configures awb window left coordinate
+ */
+#define ISP_AWB_LPOINT    0x00000FFFU
+#define ISP_AWB_LPOINT_M  (ISP_AWB_LPOINT_V << ISP_AWB_LPOINT_S)
+#define ISP_AWB_LPOINT_V  0x00000FFFU
+#define ISP_AWB_LPOINT_S  16
+
+/** ISP_AWB_VSCALE_REG register
+ *  v-scale of awb window
+ */
+#define ISP_AWB_VSCALE_REG (DR_REG_ISP_BASE + 0x16c)
+/** ISP_AWB_BPOINT : R/W; bitpos: [11:0]; default: 1079;
+ *  this field configures awb window bottom coordinate
+ */
+#define ISP_AWB_BPOINT    0x00000FFFU
+#define ISP_AWB_BPOINT_M  (ISP_AWB_BPOINT_V << ISP_AWB_BPOINT_S)
+#define ISP_AWB_BPOINT_V  0x00000FFFU
+#define ISP_AWB_BPOINT_S  0
+/** ISP_AWB_TPOINT : R/W; bitpos: [27:16]; default: 0;
+ *  this field configures awb window top coordinate
+ */
+#define ISP_AWB_TPOINT    0x00000FFFU
+#define ISP_AWB_TPOINT_M  (ISP_AWB_TPOINT_V << ISP_AWB_TPOINT_S)
+#define ISP_AWB_TPOINT_V  0x00000FFFU
+#define ISP_AWB_TPOINT_S  16
+
+/** ISP_AWB_TH_LUM_REG register
+ *  awb lum threshold register
+ */
+#define ISP_AWB_TH_LUM_REG (DR_REG_ISP_BASE + 0x170)
+/** ISP_AWB_MIN_LUM : R/W; bitpos: [9:0]; default: 0;
+ *  this field configures lower threshold of r+g+b
+ */
+#define ISP_AWB_MIN_LUM    0x000003FFU
+#define ISP_AWB_MIN_LUM_M  (ISP_AWB_MIN_LUM_V << ISP_AWB_MIN_LUM_S)
+#define ISP_AWB_MIN_LUM_V  0x000003FFU
+#define ISP_AWB_MIN_LUM_S  0
+/** ISP_AWB_MAX_LUM : R/W; bitpos: [25:16]; default: 765;
+ *  this field configures upper threshold of r+g+b
+ */
+#define ISP_AWB_MAX_LUM    0x000003FFU
+#define ISP_AWB_MAX_LUM_M  (ISP_AWB_MAX_LUM_V << ISP_AWB_MAX_LUM_S)
+#define ISP_AWB_MAX_LUM_V  0x000003FFU
+#define ISP_AWB_MAX_LUM_S  16
+
+/** ISP_AWB_TH_RG_REG register
+ *  awb r/g threshold register
+ */
+#define ISP_AWB_TH_RG_REG (DR_REG_ISP_BASE + 0x174)
+/** ISP_AWB_MIN_RG : R/W; bitpos: [9:0]; default: 0;
+ *  this field configures lower threshold of r/g, 2bit integer and 8bit fraction
+ */
+#define ISP_AWB_MIN_RG    0x000003FFU
+#define ISP_AWB_MIN_RG_M  (ISP_AWB_MIN_RG_V << ISP_AWB_MIN_RG_S)
+#define ISP_AWB_MIN_RG_V  0x000003FFU
+#define ISP_AWB_MIN_RG_S  0
+/** ISP_AWB_MAX_RG : R/W; bitpos: [25:16]; default: 1023;
+ *  this field configures upper threshold of r/g, 2bit integer and 8bit fraction
+ */
+#define ISP_AWB_MAX_RG    0x000003FFU
+#define ISP_AWB_MAX_RG_M  (ISP_AWB_MAX_RG_V << ISP_AWB_MAX_RG_S)
+#define ISP_AWB_MAX_RG_V  0x000003FFU
+#define ISP_AWB_MAX_RG_S  16
+
+/** ISP_AWB_TH_BG_REG register
+ *  awb b/g threshold register
+ */
+#define ISP_AWB_TH_BG_REG (DR_REG_ISP_BASE + 0x178)
+/** ISP_AWB_MIN_BG : R/W; bitpos: [9:0]; default: 0;
+ *  this field configures lower threshold of b/g, 2bit integer and 8bit fraction
+ */
+#define ISP_AWB_MIN_BG    0x000003FFU
+#define ISP_AWB_MIN_BG_M  (ISP_AWB_MIN_BG_V << ISP_AWB_MIN_BG_S)
+#define ISP_AWB_MIN_BG_V  0x000003FFU
+#define ISP_AWB_MIN_BG_S  0
+/** ISP_AWB_MAX_BG : R/W; bitpos: [25:16]; default: 1023;
+ *  this field configures upper threshold of b/g, 2bit integer and 8bit fraction
+ */
+#define ISP_AWB_MAX_BG    0x000003FFU
+#define ISP_AWB_MAX_BG_M  (ISP_AWB_MAX_BG_V << ISP_AWB_MAX_BG_S)
+#define ISP_AWB_MAX_BG_V  0x000003FFU
+#define ISP_AWB_MAX_BG_S  16
+
+/** ISP_AWB0_WHITE_CNT_REG register
+ *  result of awb white point number
+ */
+#define ISP_AWB0_WHITE_CNT_REG (DR_REG_ISP_BASE + 0x17c)
+/** ISP_AWB0_WHITE_CNT : RO; bitpos: [23:0]; default: 0;
+ *  this field configures number of white point detected of algo0
+ */
+#define ISP_AWB0_WHITE_CNT    0x00FFFFFFU
+#define ISP_AWB0_WHITE_CNT_M  (ISP_AWB0_WHITE_CNT_V << ISP_AWB0_WHITE_CNT_S)
+#define ISP_AWB0_WHITE_CNT_V  0x00FFFFFFU
+#define ISP_AWB0_WHITE_CNT_S  0
+
+/** ISP_AWB0_ACC_R_REG register
+ *  result of accumulate of r channel of all white points
+ */
+#define ISP_AWB0_ACC_R_REG (DR_REG_ISP_BASE + 0x180)
+/** ISP_AWB0_ACC_R : RO; bitpos: [31:0]; default: 0;
+ *  this field represents accumulate of channel r of all white point of algo0
+ */
+#define ISP_AWB0_ACC_R    0xFFFFFFFFU
+#define ISP_AWB0_ACC_R_M  (ISP_AWB0_ACC_R_V << ISP_AWB0_ACC_R_S)
+#define ISP_AWB0_ACC_R_V  0xFFFFFFFFU
+#define ISP_AWB0_ACC_R_S  0
+
+/** ISP_AWB0_ACC_G_REG register
+ *  result of accumulate of g channel of all white points
+ */
+#define ISP_AWB0_ACC_G_REG (DR_REG_ISP_BASE + 0x184)
+/** ISP_AWB0_ACC_G : RO; bitpos: [31:0]; default: 0;
+ *  this field represents accumulate of channel g of all white point of algo0
+ */
+#define ISP_AWB0_ACC_G    0xFFFFFFFFU
+#define ISP_AWB0_ACC_G_M  (ISP_AWB0_ACC_G_V << ISP_AWB0_ACC_G_S)
+#define ISP_AWB0_ACC_G_V  0xFFFFFFFFU
+#define ISP_AWB0_ACC_G_S  0
+
+/** ISP_AWB0_ACC_B_REG register
+ *  result of accumulate of b channel of all white points
+ */
+#define ISP_AWB0_ACC_B_REG (DR_REG_ISP_BASE + 0x188)
+/** ISP_AWB0_ACC_B : RO; bitpos: [31:0]; default: 0;
+ *  this field represents accumulate of channel b of all white point of algo0
+ */
+#define ISP_AWB0_ACC_B    0xFFFFFFFFU
+#define ISP_AWB0_ACC_B_M  (ISP_AWB0_ACC_B_V << ISP_AWB0_ACC_B_S)
+#define ISP_AWB0_ACC_B_V  0xFFFFFFFFU
+#define ISP_AWB0_ACC_B_S  0
+
+/** ISP_COLOR_CTRL_REG register
+ *  color control register
+ */
+#define ISP_COLOR_CTRL_REG (DR_REG_ISP_BASE + 0x18c)
+/** ISP_COLOR_SATURATION : R/W; bitpos: [7:0]; default: 128;
+ *  this field configures the color saturation value
+ */
+#define ISP_COLOR_SATURATION    0x000000FFU
+#define ISP_COLOR_SATURATION_M  (ISP_COLOR_SATURATION_V << ISP_COLOR_SATURATION_S)
+#define ISP_COLOR_SATURATION_V  0x000000FFU
+#define ISP_COLOR_SATURATION_S  0
+/** ISP_COLOR_HUE : R/W; bitpos: [15:8]; default: 0;
+ *  this field configures the color hue angle
+ */
+#define ISP_COLOR_HUE    0x000000FFU
+#define ISP_COLOR_HUE_M  (ISP_COLOR_HUE_V << ISP_COLOR_HUE_S)
+#define ISP_COLOR_HUE_V  0x000000FFU
+#define ISP_COLOR_HUE_S  8
+/** ISP_COLOR_CONTRAST : R/W; bitpos: [23:16]; default: 128;
+ *  this field configures the color contrast value
+ */
+#define ISP_COLOR_CONTRAST    0x000000FFU
+#define ISP_COLOR_CONTRAST_M  (ISP_COLOR_CONTRAST_V << ISP_COLOR_CONTRAST_S)
+#define ISP_COLOR_CONTRAST_V  0x000000FFU
+#define ISP_COLOR_CONTRAST_S  16
+/** ISP_COLOR_BRIGHTNESS : R/W; bitpos: [31:24]; default: 0;
+ *  this field configures the color brightness value, signed 2's complement
+ */
+#define ISP_COLOR_BRIGHTNESS    0x000000FFU
+#define ISP_COLOR_BRIGHTNESS_M  (ISP_COLOR_BRIGHTNESS_V << ISP_COLOR_BRIGHTNESS_S)
+#define ISP_COLOR_BRIGHTNESS_V  0x000000FFU
+#define ISP_COLOR_BRIGHTNESS_S  24
+
+/** ISP_BLC_VALUE_REG register
+ *  blc black level register
+ */
+#define ISP_BLC_VALUE_REG (DR_REG_ISP_BASE + 0x190)
+/** ISP_BLC_R3_VALUE : R/W; bitpos: [7:0]; default: 0;
+ *  this field configures the black level of bottom right channel of bayer img
+ */
+#define ISP_BLC_R3_VALUE    0x000000FFU
+#define ISP_BLC_R3_VALUE_M  (ISP_BLC_R3_VALUE_V << ISP_BLC_R3_VALUE_S)
+#define ISP_BLC_R3_VALUE_V  0x000000FFU
+#define ISP_BLC_R3_VALUE_S  0
+/** ISP_BLC_R2_VALUE : R/W; bitpos: [15:8]; default: 0;
+ *  this field configures the black level of bottom left channel of bayer img
+ */
+#define ISP_BLC_R2_VALUE    0x000000FFU
+#define ISP_BLC_R2_VALUE_M  (ISP_BLC_R2_VALUE_V << ISP_BLC_R2_VALUE_S)
+#define ISP_BLC_R2_VALUE_V  0x000000FFU
+#define ISP_BLC_R2_VALUE_S  8
+/** ISP_BLC_R1_VALUE : R/W; bitpos: [23:16]; default: 0;
+ *  this field configures the black level of top right channel of bayer img
+ */
+#define ISP_BLC_R1_VALUE    0x000000FFU
+#define ISP_BLC_R1_VALUE_M  (ISP_BLC_R1_VALUE_V << ISP_BLC_R1_VALUE_S)
+#define ISP_BLC_R1_VALUE_V  0x000000FFU
+#define ISP_BLC_R1_VALUE_S  16
+/** ISP_BLC_R0_VALUE : R/W; bitpos: [31:24]; default: 0;
+ *  this field configures the black level of top left channel of bayer img
+ */
+#define ISP_BLC_R0_VALUE    0x000000FFU
+#define ISP_BLC_R0_VALUE_M  (ISP_BLC_R0_VALUE_V << ISP_BLC_R0_VALUE_S)
+#define ISP_BLC_R0_VALUE_V  0x000000FFU
+#define ISP_BLC_R0_VALUE_S  24
+
+/** ISP_BLC_CTRL0_REG register
+ *  blc stretch control register
+ */
+#define ISP_BLC_CTRL0_REG (DR_REG_ISP_BASE + 0x194)
+/** ISP_BLC_R3_STRETCH : R/W; bitpos: [0]; default: 0;
+ *  this bit configures the stretch feature of bottom right channel. 0: stretch
+ *  disable, 1: stretch enable
+ */
+#define ISP_BLC_R3_STRETCH    (BIT(0))
+#define ISP_BLC_R3_STRETCH_M  (ISP_BLC_R3_STRETCH_V << ISP_BLC_R3_STRETCH_S)
+#define ISP_BLC_R3_STRETCH_V  0x00000001U
+#define ISP_BLC_R3_STRETCH_S  0
+/** ISP_BLC_R2_STRETCH : R/W; bitpos: [1]; default: 0;
+ *  this bit configures the stretch feature of bottom left channel. 0: stretch disable,
+ *  1: stretch enable
+ */
+#define ISP_BLC_R2_STRETCH    (BIT(1))
+#define ISP_BLC_R2_STRETCH_M  (ISP_BLC_R2_STRETCH_V << ISP_BLC_R2_STRETCH_S)
+#define ISP_BLC_R2_STRETCH_V  0x00000001U
+#define ISP_BLC_R2_STRETCH_S  1
+/** ISP_BLC_R1_STRETCH : R/W; bitpos: [2]; default: 0;
+ *  this bit configures the stretch feature of top right channel. 0: stretch disable,
+ *  1: stretch enable
+ */
+#define ISP_BLC_R1_STRETCH    (BIT(2))
+#define ISP_BLC_R1_STRETCH_M  (ISP_BLC_R1_STRETCH_V << ISP_BLC_R1_STRETCH_S)
+#define ISP_BLC_R1_STRETCH_V  0x00000001U
+#define ISP_BLC_R1_STRETCH_S  2
+/** ISP_BLC_R0_STRETCH : R/W; bitpos: [3]; default: 0;
+ *  this bit configures the stretch feature of top left channel. 0: stretch disable, 1:
+ *  stretch enable
+ */
+#define ISP_BLC_R0_STRETCH    (BIT(3))
+#define ISP_BLC_R0_STRETCH_M  (ISP_BLC_R0_STRETCH_V << ISP_BLC_R0_STRETCH_S)
+#define ISP_BLC_R0_STRETCH_V  0x00000001U
+#define ISP_BLC_R0_STRETCH_S  3
+
+/** ISP_BLC_CTRL1_REG register
+ *  blc window control register
+ */
+#define ISP_BLC_CTRL1_REG (DR_REG_ISP_BASE + 0x198)
+/** ISP_BLC_WINDOW_TOP : R/W; bitpos: [10:0]; default: 0;
+ *  this field configures blc average calculation window top
+ */
+#define ISP_BLC_WINDOW_TOP    0x000007FFU
+#define ISP_BLC_WINDOW_TOP_M  (ISP_BLC_WINDOW_TOP_V << ISP_BLC_WINDOW_TOP_S)
+#define ISP_BLC_WINDOW_TOP_V  0x000007FFU
+#define ISP_BLC_WINDOW_TOP_S  0
+/** ISP_BLC_WINDOW_LEFT : R/W; bitpos: [21:11]; default: 0;
+ *  this field configures blc average calculation window left
+ */
+#define ISP_BLC_WINDOW_LEFT    0x000007FFU
+#define ISP_BLC_WINDOW_LEFT_M  (ISP_BLC_WINDOW_LEFT_V << ISP_BLC_WINDOW_LEFT_S)
+#define ISP_BLC_WINDOW_LEFT_V  0x000007FFU
+#define ISP_BLC_WINDOW_LEFT_S  11
+/** ISP_BLC_WINDOW_VNUM : R/W; bitpos: [25:22]; default: 0;
+ *  this field configures blc average calculation window vnum
+ */
+#define ISP_BLC_WINDOW_VNUM    0x0000000FU
+#define ISP_BLC_WINDOW_VNUM_M  (ISP_BLC_WINDOW_VNUM_V << ISP_BLC_WINDOW_VNUM_S)
+#define ISP_BLC_WINDOW_VNUM_V  0x0000000FU
+#define ISP_BLC_WINDOW_VNUM_S  22
+/** ISP_BLC_WINDOW_HNUM : R/W; bitpos: [29:26]; default: 0;
+ *  this field configures blc average calculation window hnum
+ */
+#define ISP_BLC_WINDOW_HNUM    0x0000000FU
+#define ISP_BLC_WINDOW_HNUM_M  (ISP_BLC_WINDOW_HNUM_V << ISP_BLC_WINDOW_HNUM_S)
+#define ISP_BLC_WINDOW_HNUM_V  0x0000000FU
+#define ISP_BLC_WINDOW_HNUM_S  26
+/** ISP_BLC_FILTER_EN : R/W; bitpos: [30]; default: 0;
+ *  this bit configures enable blc average input filter. 0: disable, 1: enable
+ */
+#define ISP_BLC_FILTER_EN    (BIT(30))
+#define ISP_BLC_FILTER_EN_M  (ISP_BLC_FILTER_EN_V << ISP_BLC_FILTER_EN_S)
+#define ISP_BLC_FILTER_EN_V  0x00000001U
+#define ISP_BLC_FILTER_EN_S  30
+
+/** ISP_BLC_CTRL2_REG register
+ *  blc black threshold control register
+ */
+#define ISP_BLC_CTRL2_REG (DR_REG_ISP_BASE + 0x19c)
+/** ISP_BLC_R3_TH : R/W; bitpos: [7:0]; default: 0;
+ *  this field configures black threshold when get blc average of bottom right channel
+ */
+#define ISP_BLC_R3_TH    0x000000FFU
+#define ISP_BLC_R3_TH_M  (ISP_BLC_R3_TH_V << ISP_BLC_R3_TH_S)
+#define ISP_BLC_R3_TH_V  0x000000FFU
+#define ISP_BLC_R3_TH_S  0
+/** ISP_BLC_R2_TH : R/W; bitpos: [15:8]; default: 0;
+ *  this field configures black threshold when get blc average of bottom left channel
+ */
+#define ISP_BLC_R2_TH    0x000000FFU
+#define ISP_BLC_R2_TH_M  (ISP_BLC_R2_TH_V << ISP_BLC_R2_TH_S)
+#define ISP_BLC_R2_TH_V  0x000000FFU
+#define ISP_BLC_R2_TH_S  8
+/** ISP_BLC_R1_TH : R/W; bitpos: [23:16]; default: 0;
+ *  this field configures black threshold when get blc average of top right channel
+ */
+#define ISP_BLC_R1_TH    0x000000FFU
+#define ISP_BLC_R1_TH_M  (ISP_BLC_R1_TH_V << ISP_BLC_R1_TH_S)
+#define ISP_BLC_R1_TH_V  0x000000FFU
+#define ISP_BLC_R1_TH_S  16
+/** ISP_BLC_R0_TH : R/W; bitpos: [31:24]; default: 0;
+ *  this field configures black threshold when get blc average of top left channel
+ */
+#define ISP_BLC_R0_TH    0x000000FFU
+#define ISP_BLC_R0_TH_M  (ISP_BLC_R0_TH_V << ISP_BLC_R0_TH_S)
+#define ISP_BLC_R0_TH_V  0x000000FFU
+#define ISP_BLC_R0_TH_S  24
+
+/** ISP_BLC_MEAN_REG register
+ *  results of the average of black window
+ */
+#define ISP_BLC_MEAN_REG (DR_REG_ISP_BASE + 0x1a0)
+/** ISP_BLC_R3_MEAN : RO; bitpos: [7:0]; default: 0;
+ *  this field represents the average black value of bottom right channel
+ */
+#define ISP_BLC_R3_MEAN    0x000000FFU
+#define ISP_BLC_R3_MEAN_M  (ISP_BLC_R3_MEAN_V << ISP_BLC_R3_MEAN_S)
+#define ISP_BLC_R3_MEAN_V  0x000000FFU
+#define ISP_BLC_R3_MEAN_S  0
+/** ISP_BLC_R2_MEAN : RO; bitpos: [15:8]; default: 0;
+ *  this field represents the average black value of bottom left channel
+ */
+#define ISP_BLC_R2_MEAN    0x000000FFU
+#define ISP_BLC_R2_MEAN_M  (ISP_BLC_R2_MEAN_V << ISP_BLC_R2_MEAN_S)
+#define ISP_BLC_R2_MEAN_V  0x000000FFU
+#define ISP_BLC_R2_MEAN_S  8
+/** ISP_BLC_R1_MEAN : RO; bitpos: [23:16]; default: 0;
+ *  this field represents the average black value of top right channel
+ */
+#define ISP_BLC_R1_MEAN    0x000000FFU
+#define ISP_BLC_R1_MEAN_M  (ISP_BLC_R1_MEAN_V << ISP_BLC_R1_MEAN_S)
+#define ISP_BLC_R1_MEAN_V  0x000000FFU
+#define ISP_BLC_R1_MEAN_S  16
+/** ISP_BLC_R0_MEAN : RO; bitpos: [31:24]; default: 0;
+ *  this field represents the average black value of top left channel
+ */
+#define ISP_BLC_R0_MEAN    0x000000FFU
+#define ISP_BLC_R0_MEAN_M  (ISP_BLC_R0_MEAN_V << ISP_BLC_R0_MEAN_S)
+#define ISP_BLC_R0_MEAN_V  0x000000FFU
+#define ISP_BLC_R0_MEAN_S  24
+
+/** ISP_HIST_MODE_REG register
+ *  histogram mode control register
+ */
+#define ISP_HIST_MODE_REG (DR_REG_ISP_BASE + 0x1a4)
+/** ISP_HIST_MODE : R/W; bitpos: [2:0]; default: 4;
+ *  this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4:
+ *  RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V
+ */
+#define ISP_HIST_MODE    0x00000007U
+#define ISP_HIST_MODE_M  (ISP_HIST_MODE_V << ISP_HIST_MODE_S)
+#define ISP_HIST_MODE_V  0x00000007U
+#define ISP_HIST_MODE_S  0
+
+/** ISP_HIST_COEFF_REG register
+ *  histogram rgb to gray coefficients register
+ */
+#define ISP_HIST_COEFF_REG (DR_REG_ISP_BASE + 0x1a8)
+/** ISP_HIST_COEFF_B : R/W; bitpos: [7:0]; default: 85;
+ *  this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r
+ *  and coeff_g and coeff_b should be 256
+ */
+#define ISP_HIST_COEFF_B    0x000000FFU
+#define ISP_HIST_COEFF_B_M  (ISP_HIST_COEFF_B_V << ISP_HIST_COEFF_B_S)
+#define ISP_HIST_COEFF_B_V  0x000000FFU
+#define ISP_HIST_COEFF_B_S  0
+/** ISP_HIST_COEFF_G : R/W; bitpos: [15:8]; default: 85;
+ *  this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r
+ *  and coeff_g and coeff_b should be 256
+ */
+#define ISP_HIST_COEFF_G    0x000000FFU
+#define ISP_HIST_COEFF_G_M  (ISP_HIST_COEFF_G_V << ISP_HIST_COEFF_G_S)
+#define ISP_HIST_COEFF_G_V  0x000000FFU
+#define ISP_HIST_COEFF_G_S  8
+/** ISP_HIST_COEFF_R : R/W; bitpos: [23:16]; default: 85;
+ *  this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r
+ *  and coeff_g and coeff_b should be 256
+ */
+#define ISP_HIST_COEFF_R    0x000000FFU
+#define ISP_HIST_COEFF_R_M  (ISP_HIST_COEFF_R_V << ISP_HIST_COEFF_R_S)
+#define ISP_HIST_COEFF_R_V  0x000000FFU
+#define ISP_HIST_COEFF_R_S  16
+
+/** ISP_HIST_OFFS_REG register
+ *  histogram window offsets register
+ */
+#define ISP_HIST_OFFS_REG (DR_REG_ISP_BASE + 0x1ac)
+/** ISP_HIST_Y_OFFS : R/W; bitpos: [11:0]; default: 0;
+ *  this field configures y coordinate of first window
+ */
+#define ISP_HIST_Y_OFFS    0x00000FFFU
+#define ISP_HIST_Y_OFFS_M  (ISP_HIST_Y_OFFS_V << ISP_HIST_Y_OFFS_S)
+#define ISP_HIST_Y_OFFS_V  0x00000FFFU
+#define ISP_HIST_Y_OFFS_S  0
+/** ISP_HIST_X_OFFS : R/W; bitpos: [27:16]; default: 0;
+ *  this field configures x coordinate of first window
+ */
+#define ISP_HIST_X_OFFS    0x00000FFFU
+#define ISP_HIST_X_OFFS_M  (ISP_HIST_X_OFFS_V << ISP_HIST_X_OFFS_S)
+#define ISP_HIST_X_OFFS_V  0x00000FFFU
+#define ISP_HIST_X_OFFS_S  16
+
+/** ISP_HIST_SIZE_REG register
+ *  histogram sub-window size register
+ */
+#define ISP_HIST_SIZE_REG (DR_REG_ISP_BASE + 0x1b0)
+/** ISP_HIST_Y_SIZE : R/W; bitpos: [8:0]; default: 32;
+ *  this field configures y direction size of subwindow
+ */
+#define ISP_HIST_Y_SIZE    0x000001FFU
+#define ISP_HIST_Y_SIZE_M  (ISP_HIST_Y_SIZE_V << ISP_HIST_Y_SIZE_S)
+#define ISP_HIST_Y_SIZE_V  0x000001FFU
+#define ISP_HIST_Y_SIZE_S  0
+/** ISP_HIST_X_SIZE : R/W; bitpos: [24:16]; default: 18;
+ *  this field configures x direction size of subwindow
+ */
+#define ISP_HIST_X_SIZE    0x000001FFU
+#define ISP_HIST_X_SIZE_M  (ISP_HIST_X_SIZE_V << ISP_HIST_X_SIZE_S)
+#define ISP_HIST_X_SIZE_V  0x000001FFU
+#define ISP_HIST_X_SIZE_S  16
+
+/** ISP_HIST_SEG0_REG register
+ *  histogram bin control register 0
+ */
+#define ISP_HIST_SEG0_REG (DR_REG_ISP_BASE + 0x1b4)
+/** ISP_HIST_SEG_3_4 : R/W; bitpos: [7:0]; default: 64;
+ *  this field configures threshold of histogram bin 3 and bin 4
+ */
+#define ISP_HIST_SEG_3_4    0x000000FFU
+#define ISP_HIST_SEG_3_4_M  (ISP_HIST_SEG_3_4_V << ISP_HIST_SEG_3_4_S)
+#define ISP_HIST_SEG_3_4_V  0x000000FFU
+#define ISP_HIST_SEG_3_4_S  0
+/** ISP_HIST_SEG_2_3 : R/W; bitpos: [15:8]; default: 48;
+ *  this field configures threshold of histogram bin 2 and bin 3
+ */
+#define ISP_HIST_SEG_2_3    0x000000FFU
+#define ISP_HIST_SEG_2_3_M  (ISP_HIST_SEG_2_3_V << ISP_HIST_SEG_2_3_S)
+#define ISP_HIST_SEG_2_3_V  0x000000FFU
+#define ISP_HIST_SEG_2_3_S  8
+/** ISP_HIST_SEG_1_2 : R/W; bitpos: [23:16]; default: 32;
+ *  this field configures threshold of histogram bin 1 and bin 2
+ */
+#define ISP_HIST_SEG_1_2    0x000000FFU
+#define ISP_HIST_SEG_1_2_M  (ISP_HIST_SEG_1_2_V << ISP_HIST_SEG_1_2_S)
+#define ISP_HIST_SEG_1_2_V  0x000000FFU
+#define ISP_HIST_SEG_1_2_S  16
+/** ISP_HIST_SEG_0_1 : R/W; bitpos: [31:24]; default: 16;
+ *  this field configures threshold of histogram bin 0 and bin 1
+ */
+#define ISP_HIST_SEG_0_1    0x000000FFU
+#define ISP_HIST_SEG_0_1_M  (ISP_HIST_SEG_0_1_V << ISP_HIST_SEG_0_1_S)
+#define ISP_HIST_SEG_0_1_V  0x000000FFU
+#define ISP_HIST_SEG_0_1_S  24
+
+/** ISP_HIST_SEG1_REG register
+ *  histogram bin control register 1
+ */
+#define ISP_HIST_SEG1_REG (DR_REG_ISP_BASE + 0x1b8)
+/** ISP_HIST_SEG_7_8 : R/W; bitpos: [7:0]; default: 128;
+ *  this field configures threshold of histogram bin 7 and bin 8
+ */
+#define ISP_HIST_SEG_7_8    0x000000FFU
+#define ISP_HIST_SEG_7_8_M  (ISP_HIST_SEG_7_8_V << ISP_HIST_SEG_7_8_S)
+#define ISP_HIST_SEG_7_8_V  0x000000FFU
+#define ISP_HIST_SEG_7_8_S  0
+/** ISP_HIST_SEG_6_7 : R/W; bitpos: [15:8]; default: 112;
+ *  this field configures threshold of histogram bin 6 and bin 7
+ */
+#define ISP_HIST_SEG_6_7    0x000000FFU
+#define ISP_HIST_SEG_6_7_M  (ISP_HIST_SEG_6_7_V << ISP_HIST_SEG_6_7_S)
+#define ISP_HIST_SEG_6_7_V  0x000000FFU
+#define ISP_HIST_SEG_6_7_S  8
+/** ISP_HIST_SEG_5_6 : R/W; bitpos: [23:16]; default: 96;
+ *  this field configures threshold of histogram bin 5 and bin 6
+ */
+#define ISP_HIST_SEG_5_6    0x000000FFU
+#define ISP_HIST_SEG_5_6_M  (ISP_HIST_SEG_5_6_V << ISP_HIST_SEG_5_6_S)
+#define ISP_HIST_SEG_5_6_V  0x000000FFU
+#define ISP_HIST_SEG_5_6_S  16
+/** ISP_HIST_SEG_4_5 : R/W; bitpos: [31:24]; default: 80;
+ *  this field configures threshold of histogram bin 4 and bin 5
+ */
+#define ISP_HIST_SEG_4_5    0x000000FFU
+#define ISP_HIST_SEG_4_5_M  (ISP_HIST_SEG_4_5_V << ISP_HIST_SEG_4_5_S)
+#define ISP_HIST_SEG_4_5_V  0x000000FFU
+#define ISP_HIST_SEG_4_5_S  24
+
+/** ISP_HIST_SEG2_REG register
+ *  histogram bin control register 2
+ */
+#define ISP_HIST_SEG2_REG (DR_REG_ISP_BASE + 0x1bc)
+/** ISP_HIST_SEG_11_12 : R/W; bitpos: [7:0]; default: 192;
+ *  this field configures threshold of histogram bin 11 and bin 12
+ */
+#define ISP_HIST_SEG_11_12    0x000000FFU
+#define ISP_HIST_SEG_11_12_M  (ISP_HIST_SEG_11_12_V << ISP_HIST_SEG_11_12_S)
+#define ISP_HIST_SEG_11_12_V  0x000000FFU
+#define ISP_HIST_SEG_11_12_S  0
+/** ISP_HIST_SEG_10_11 : R/W; bitpos: [15:8]; default: 176;
+ *  this field configures threshold of histogram bin 10 and bin 11
+ */
+#define ISP_HIST_SEG_10_11    0x000000FFU
+#define ISP_HIST_SEG_10_11_M  (ISP_HIST_SEG_10_11_V << ISP_HIST_SEG_10_11_S)
+#define ISP_HIST_SEG_10_11_V  0x000000FFU
+#define ISP_HIST_SEG_10_11_S  8
+/** ISP_HIST_SEG_9_10 : R/W; bitpos: [23:16]; default: 160;
+ *  this field configures threshold of histogram bin 9 and bin 10
+ */
+#define ISP_HIST_SEG_9_10    0x000000FFU
+#define ISP_HIST_SEG_9_10_M  (ISP_HIST_SEG_9_10_V << ISP_HIST_SEG_9_10_S)
+#define ISP_HIST_SEG_9_10_V  0x000000FFU
+#define ISP_HIST_SEG_9_10_S  16
+/** ISP_HIST_SEG_8_9 : R/W; bitpos: [31:24]; default: 144;
+ *  this field configures threshold of histogram bin 8 and bin 9
+ */
+#define ISP_HIST_SEG_8_9    0x000000FFU
+#define ISP_HIST_SEG_8_9_M  (ISP_HIST_SEG_8_9_V << ISP_HIST_SEG_8_9_S)
+#define ISP_HIST_SEG_8_9_V  0x000000FFU
+#define ISP_HIST_SEG_8_9_S  24
+
+/** ISP_HIST_SEG3_REG register
+ *  histogram bin control register 3
+ */
+#define ISP_HIST_SEG3_REG (DR_REG_ISP_BASE + 0x1c0)
+/** ISP_HIST_SEG_14_15 : R/W; bitpos: [7:0]; default: 240;
+ *  this field configures threshold of histogram bin 14 and bin 15
+ */
+#define ISP_HIST_SEG_14_15    0x000000FFU
+#define ISP_HIST_SEG_14_15_M  (ISP_HIST_SEG_14_15_V << ISP_HIST_SEG_14_15_S)
+#define ISP_HIST_SEG_14_15_V  0x000000FFU
+#define ISP_HIST_SEG_14_15_S  0
+/** ISP_HIST_SEG_13_14 : R/W; bitpos: [15:8]; default: 224;
+ *  this field configures threshold of histogram bin 13 and bin 14
+ */
+#define ISP_HIST_SEG_13_14    0x000000FFU
+#define ISP_HIST_SEG_13_14_M  (ISP_HIST_SEG_13_14_V << ISP_HIST_SEG_13_14_S)
+#define ISP_HIST_SEG_13_14_V  0x000000FFU
+#define ISP_HIST_SEG_13_14_S  8
+/** ISP_HIST_SEG_12_13 : R/W; bitpos: [23:16]; default: 208;
+ *  this field configures threshold of histogram bin 12 and bin 13
+ */
+#define ISP_HIST_SEG_12_13    0x000000FFU
+#define ISP_HIST_SEG_12_13_M  (ISP_HIST_SEG_12_13_V << ISP_HIST_SEG_12_13_S)
+#define ISP_HIST_SEG_12_13_V  0x000000FFU
+#define ISP_HIST_SEG_12_13_S  16
+
+/** ISP_HIST_WEIGHT0_REG register
+ *  histogram sub-window weight register 0
+ */
+#define ISP_HIST_WEIGHT0_REG (DR_REG_ISP_BASE + 0x1c4)
+/** ISP_HIST_WEIGHT_03 : R/W; bitpos: [7:0]; default: 1;
+ *  this field configures weight of subwindow 03
+ */
+#define ISP_HIST_WEIGHT_03    0x000000FFU
+#define ISP_HIST_WEIGHT_03_M  (ISP_HIST_WEIGHT_03_V << ISP_HIST_WEIGHT_03_S)
+#define ISP_HIST_WEIGHT_03_V  0x000000FFU
+#define ISP_HIST_WEIGHT_03_S  0
+/** ISP_HIST_WEIGHT_02 : R/W; bitpos: [15:8]; default: 1;
+ *  this field configures weight of subwindow 02
+ */
+#define ISP_HIST_WEIGHT_02    0x000000FFU
+#define ISP_HIST_WEIGHT_02_M  (ISP_HIST_WEIGHT_02_V << ISP_HIST_WEIGHT_02_S)
+#define ISP_HIST_WEIGHT_02_V  0x000000FFU
+#define ISP_HIST_WEIGHT_02_S  8
+/** ISP_HIST_WEIGHT_01 : R/W; bitpos: [23:16]; default: 1;
+ *  this field configures weight of subwindow 01
+ */
+#define ISP_HIST_WEIGHT_01    0x000000FFU
+#define ISP_HIST_WEIGHT_01_M  (ISP_HIST_WEIGHT_01_V << ISP_HIST_WEIGHT_01_S)
+#define ISP_HIST_WEIGHT_01_V  0x000000FFU
+#define ISP_HIST_WEIGHT_01_S  16
+/** ISP_HIST_WEIGHT_00 : R/W; bitpos: [31:24]; default: 1;
+ *  this field configures weight of subwindow 00 and sum of all weight should be 256
+ */
+#define ISP_HIST_WEIGHT_00    0x000000FFU
+#define ISP_HIST_WEIGHT_00_M  (ISP_HIST_WEIGHT_00_V << ISP_HIST_WEIGHT_00_S)
+#define ISP_HIST_WEIGHT_00_V  0x000000FFU
+#define ISP_HIST_WEIGHT_00_S  24
+
+/** ISP_HIST_WEIGHT1_REG register
+ *  histogram sub-window weight register 1
+ */
+#define ISP_HIST_WEIGHT1_REG (DR_REG_ISP_BASE + 0x1c8)
+/** ISP_HIST_WEIGHT_12 : R/W; bitpos: [7:0]; default: 1;
+ *  this field configures weight of subwindow 12
+ */
+#define ISP_HIST_WEIGHT_12    0x000000FFU
+#define ISP_HIST_WEIGHT_12_M  (ISP_HIST_WEIGHT_12_V << ISP_HIST_WEIGHT_12_S)
+#define ISP_HIST_WEIGHT_12_V  0x000000FFU
+#define ISP_HIST_WEIGHT_12_S  0
+/** ISP_HIST_WEIGHT_11 : R/W; bitpos: [15:8]; default: 1;
+ *  this field configures weight of subwindow 11
+ */
+#define ISP_HIST_WEIGHT_11    0x000000FFU
+#define ISP_HIST_WEIGHT_11_M  (ISP_HIST_WEIGHT_11_V << ISP_HIST_WEIGHT_11_S)
+#define ISP_HIST_WEIGHT_11_V  0x000000FFU
+#define ISP_HIST_WEIGHT_11_S  8
+/** ISP_HIST_WEIGHT_10 : R/W; bitpos: [23:16]; default: 1;
+ *  this field configures weight of subwindow 10
+ */
+#define ISP_HIST_WEIGHT_10    0x000000FFU
+#define ISP_HIST_WEIGHT_10_M  (ISP_HIST_WEIGHT_10_V << ISP_HIST_WEIGHT_10_S)
+#define ISP_HIST_WEIGHT_10_V  0x000000FFU
+#define ISP_HIST_WEIGHT_10_S  16
+/** ISP_HIST_WEIGHT_04 : R/W; bitpos: [31:24]; default: 1;
+ *  this field configures weight of subwindow 04
+ */
+#define ISP_HIST_WEIGHT_04    0x000000FFU
+#define ISP_HIST_WEIGHT_04_M  (ISP_HIST_WEIGHT_04_V << ISP_HIST_WEIGHT_04_S)
+#define ISP_HIST_WEIGHT_04_V  0x000000FFU
+#define ISP_HIST_WEIGHT_04_S  24
+
+/** ISP_HIST_WEIGHT2_REG register
+ *  histogram sub-window weight register 2
+ */
+#define ISP_HIST_WEIGHT2_REG (DR_REG_ISP_BASE + 0x1cc)
+/** ISP_HIST_WEIGHT_21 : R/W; bitpos: [7:0]; default: 1;
+ *  this field configures weight of subwindow 21
+ */
+#define ISP_HIST_WEIGHT_21    0x000000FFU
+#define ISP_HIST_WEIGHT_21_M  (ISP_HIST_WEIGHT_21_V << ISP_HIST_WEIGHT_21_S)
+#define ISP_HIST_WEIGHT_21_V  0x000000FFU
+#define ISP_HIST_WEIGHT_21_S  0
+/** ISP_HIST_WEIGHT_20 : R/W; bitpos: [15:8]; default: 1;
+ *  this field configures weight of subwindow 20
+ */
+#define ISP_HIST_WEIGHT_20    0x000000FFU
+#define ISP_HIST_WEIGHT_20_M  (ISP_HIST_WEIGHT_20_V << ISP_HIST_WEIGHT_20_S)
+#define ISP_HIST_WEIGHT_20_V  0x000000FFU
+#define ISP_HIST_WEIGHT_20_S  8
+/** ISP_HIST_WEIGHT_14 : R/W; bitpos: [23:16]; default: 1;
+ *  this field configures weight of subwindow 04
+ */
+#define ISP_HIST_WEIGHT_14    0x000000FFU
+#define ISP_HIST_WEIGHT_14_M  (ISP_HIST_WEIGHT_14_V << ISP_HIST_WEIGHT_14_S)
+#define ISP_HIST_WEIGHT_14_V  0x000000FFU
+#define ISP_HIST_WEIGHT_14_S  16
+/** ISP_HIST_WEIGHT_13 : R/W; bitpos: [31:24]; default: 1;
+ *  this field configures weight of subwindow 13
+ */
+#define ISP_HIST_WEIGHT_13    0x000000FFU
+#define ISP_HIST_WEIGHT_13_M  (ISP_HIST_WEIGHT_13_V << ISP_HIST_WEIGHT_13_S)
+#define ISP_HIST_WEIGHT_13_V  0x000000FFU
+#define ISP_HIST_WEIGHT_13_S  24
+
+/** ISP_HIST_WEIGHT3_REG register
+ *  histogram sub-window weight register 3
+ */
+#define ISP_HIST_WEIGHT3_REG (DR_REG_ISP_BASE + 0x1d0)
+/** ISP_HIST_WEIGHT_30 : R/W; bitpos: [7:0]; default: 1;
+ *  this field configures weight of subwindow 30
+ */
+#define ISP_HIST_WEIGHT_30    0x000000FFU
+#define ISP_HIST_WEIGHT_30_M  (ISP_HIST_WEIGHT_30_V << ISP_HIST_WEIGHT_30_S)
+#define ISP_HIST_WEIGHT_30_V  0x000000FFU
+#define ISP_HIST_WEIGHT_30_S  0
+/** ISP_HIST_WEIGHT_24 : R/W; bitpos: [15:8]; default: 1;
+ *  this field configures weight of subwindow 24
+ */
+#define ISP_HIST_WEIGHT_24    0x000000FFU
+#define ISP_HIST_WEIGHT_24_M  (ISP_HIST_WEIGHT_24_V << ISP_HIST_WEIGHT_24_S)
+#define ISP_HIST_WEIGHT_24_V  0x000000FFU
+#define ISP_HIST_WEIGHT_24_S  8
+/** ISP_HIST_WEIGHT_23 : R/W; bitpos: [23:16]; default: 1;
+ *  this field configures weight of subwindow 23
+ */
+#define ISP_HIST_WEIGHT_23    0x000000FFU
+#define ISP_HIST_WEIGHT_23_M  (ISP_HIST_WEIGHT_23_V << ISP_HIST_WEIGHT_23_S)
+#define ISP_HIST_WEIGHT_23_V  0x000000FFU
+#define ISP_HIST_WEIGHT_23_S  16
+/** ISP_HIST_WEIGHT_22 : R/W; bitpos: [31:24]; default: 232;
+ *  this field configures weight of subwindow 22
+ */
+#define ISP_HIST_WEIGHT_22    0x000000FFU
+#define ISP_HIST_WEIGHT_22_M  (ISP_HIST_WEIGHT_22_V << ISP_HIST_WEIGHT_22_S)
+#define ISP_HIST_WEIGHT_22_V  0x000000FFU
+#define ISP_HIST_WEIGHT_22_S  24
+
+/** ISP_HIST_WEIGHT4_REG register
+ *  histogram sub-window weight register 4
+ */
+#define ISP_HIST_WEIGHT4_REG (DR_REG_ISP_BASE + 0x1d4)
+/** ISP_HIST_WEIGHT_34 : R/W; bitpos: [7:0]; default: 1;
+ *  this field configures weight of subwindow 34
+ */
+#define ISP_HIST_WEIGHT_34    0x000000FFU
+#define ISP_HIST_WEIGHT_34_M  (ISP_HIST_WEIGHT_34_V << ISP_HIST_WEIGHT_34_S)
+#define ISP_HIST_WEIGHT_34_V  0x000000FFU
+#define ISP_HIST_WEIGHT_34_S  0
+/** ISP_HIST_WEIGHT_33 : R/W; bitpos: [15:8]; default: 1;
+ *  this field configures weight of subwindow 33
+ */
+#define ISP_HIST_WEIGHT_33    0x000000FFU
+#define ISP_HIST_WEIGHT_33_M  (ISP_HIST_WEIGHT_33_V << ISP_HIST_WEIGHT_33_S)
+#define ISP_HIST_WEIGHT_33_V  0x000000FFU
+#define ISP_HIST_WEIGHT_33_S  8
+/** ISP_HIST_WEIGHT_32 : R/W; bitpos: [23:16]; default: 1;
+ *  this field configures weight of subwindow 32
+ */
+#define ISP_HIST_WEIGHT_32    0x000000FFU
+#define ISP_HIST_WEIGHT_32_M  (ISP_HIST_WEIGHT_32_V << ISP_HIST_WEIGHT_32_S)
+#define ISP_HIST_WEIGHT_32_V  0x000000FFU
+#define ISP_HIST_WEIGHT_32_S  16
+/** ISP_HIST_WEIGHT_31 : R/W; bitpos: [31:24]; default: 1;
+ *  this field configures weight of subwindow 31
+ */
+#define ISP_HIST_WEIGHT_31    0x000000FFU
+#define ISP_HIST_WEIGHT_31_M  (ISP_HIST_WEIGHT_31_V << ISP_HIST_WEIGHT_31_S)
+#define ISP_HIST_WEIGHT_31_V  0x000000FFU
+#define ISP_HIST_WEIGHT_31_S  24
+
+/** ISP_HIST_WEIGHT5_REG register
+ *  histogram sub-window weight register 5
+ */
+#define ISP_HIST_WEIGHT5_REG (DR_REG_ISP_BASE + 0x1d8)
+/** ISP_HIST_WEIGHT_43 : R/W; bitpos: [7:0]; default: 1;
+ *  this field configures weight of subwindow 43
+ */
+#define ISP_HIST_WEIGHT_43    0x000000FFU
+#define ISP_HIST_WEIGHT_43_M  (ISP_HIST_WEIGHT_43_V << ISP_HIST_WEIGHT_43_S)
+#define ISP_HIST_WEIGHT_43_V  0x000000FFU
+#define ISP_HIST_WEIGHT_43_S  0
+/** ISP_HIST_WEIGHT_42 : R/W; bitpos: [15:8]; default: 1;
+ *  this field configures weight of subwindow 42
+ */
+#define ISP_HIST_WEIGHT_42    0x000000FFU
+#define ISP_HIST_WEIGHT_42_M  (ISP_HIST_WEIGHT_42_V << ISP_HIST_WEIGHT_42_S)
+#define ISP_HIST_WEIGHT_42_V  0x000000FFU
+#define ISP_HIST_WEIGHT_42_S  8
+/** ISP_HIST_WEIGHT_41 : R/W; bitpos: [23:16]; default: 1;
+ *  this field configures weight of subwindow 41
+ */
+#define ISP_HIST_WEIGHT_41    0x000000FFU
+#define ISP_HIST_WEIGHT_41_M  (ISP_HIST_WEIGHT_41_V << ISP_HIST_WEIGHT_41_S)
+#define ISP_HIST_WEIGHT_41_V  0x000000FFU
+#define ISP_HIST_WEIGHT_41_S  16
+/** ISP_HIST_WEIGHT_40 : R/W; bitpos: [31:24]; default: 1;
+ *  this field configures weight of subwindow 40
+ */
+#define ISP_HIST_WEIGHT_40    0x000000FFU
+#define ISP_HIST_WEIGHT_40_M  (ISP_HIST_WEIGHT_40_V << ISP_HIST_WEIGHT_40_S)
+#define ISP_HIST_WEIGHT_40_V  0x000000FFU
+#define ISP_HIST_WEIGHT_40_S  24
+
+/** ISP_HIST_WEIGHT6_REG register
+ *  histogram sub-window weight register 6
+ */
+#define ISP_HIST_WEIGHT6_REG (DR_REG_ISP_BASE + 0x1dc)
+/** ISP_HIST_WEIGHT_44 : R/W; bitpos: [7:0]; default: 1;
+ *  this field configures weight of subwindow 44
+ */
+#define ISP_HIST_WEIGHT_44    0x000000FFU
+#define ISP_HIST_WEIGHT_44_M  (ISP_HIST_WEIGHT_44_V << ISP_HIST_WEIGHT_44_S)
+#define ISP_HIST_WEIGHT_44_V  0x000000FFU
+#define ISP_HIST_WEIGHT_44_S  0
+
+/** ISP_HIST_BIN0_REG register
+ *  result of histogram bin 0
+ */
+#define ISP_HIST_BIN0_REG (DR_REG_ISP_BASE + 0x1e0)
+/** ISP_HIST_BIN_0 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 0
+ */
+#define ISP_HIST_BIN_0    0x0001FFFFU
+#define ISP_HIST_BIN_0_M  (ISP_HIST_BIN_0_V << ISP_HIST_BIN_0_S)
+#define ISP_HIST_BIN_0_V  0x0001FFFFU
+#define ISP_HIST_BIN_0_S  0
+
+/** ISP_HIST_BIN1_REG register
+ *  result of histogram bin 1
+ */
+#define ISP_HIST_BIN1_REG (DR_REG_ISP_BASE + 0x1e4)
+/** ISP_HIST_BIN_1 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 1
+ */
+#define ISP_HIST_BIN_1    0x0001FFFFU
+#define ISP_HIST_BIN_1_M  (ISP_HIST_BIN_1_V << ISP_HIST_BIN_1_S)
+#define ISP_HIST_BIN_1_V  0x0001FFFFU
+#define ISP_HIST_BIN_1_S  0
+
+/** ISP_HIST_BIN2_REG register
+ *  result of histogram bin 2
+ */
+#define ISP_HIST_BIN2_REG (DR_REG_ISP_BASE + 0x1e8)
+/** ISP_HIST_BIN_2 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 2
+ */
+#define ISP_HIST_BIN_2    0x0001FFFFU
+#define ISP_HIST_BIN_2_M  (ISP_HIST_BIN_2_V << ISP_HIST_BIN_2_S)
+#define ISP_HIST_BIN_2_V  0x0001FFFFU
+#define ISP_HIST_BIN_2_S  0
+
+/** ISP_HIST_BIN3_REG register
+ *  result of histogram bin 3
+ */
+#define ISP_HIST_BIN3_REG (DR_REG_ISP_BASE + 0x1ec)
+/** ISP_HIST_BIN_3 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 3
+ */
+#define ISP_HIST_BIN_3    0x0001FFFFU
+#define ISP_HIST_BIN_3_M  (ISP_HIST_BIN_3_V << ISP_HIST_BIN_3_S)
+#define ISP_HIST_BIN_3_V  0x0001FFFFU
+#define ISP_HIST_BIN_3_S  0
+
+/** ISP_HIST_BIN4_REG register
+ *  result of histogram bin 4
+ */
+#define ISP_HIST_BIN4_REG (DR_REG_ISP_BASE + 0x1f0)
+/** ISP_HIST_BIN_4 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 4
+ */
+#define ISP_HIST_BIN_4    0x0001FFFFU
+#define ISP_HIST_BIN_4_M  (ISP_HIST_BIN_4_V << ISP_HIST_BIN_4_S)
+#define ISP_HIST_BIN_4_V  0x0001FFFFU
+#define ISP_HIST_BIN_4_S  0
+
+/** ISP_HIST_BIN5_REG register
+ *  result of histogram bin 5
+ */
+#define ISP_HIST_BIN5_REG (DR_REG_ISP_BASE + 0x1f4)
+/** ISP_HIST_BIN_5 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 5
+ */
+#define ISP_HIST_BIN_5    0x0001FFFFU
+#define ISP_HIST_BIN_5_M  (ISP_HIST_BIN_5_V << ISP_HIST_BIN_5_S)
+#define ISP_HIST_BIN_5_V  0x0001FFFFU
+#define ISP_HIST_BIN_5_S  0
+
+/** ISP_HIST_BIN6_REG register
+ *  result of histogram bin 6
+ */
+#define ISP_HIST_BIN6_REG (DR_REG_ISP_BASE + 0x1f8)
+/** ISP_HIST_BIN_6 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 6
+ */
+#define ISP_HIST_BIN_6    0x0001FFFFU
+#define ISP_HIST_BIN_6_M  (ISP_HIST_BIN_6_V << ISP_HIST_BIN_6_S)
+#define ISP_HIST_BIN_6_V  0x0001FFFFU
+#define ISP_HIST_BIN_6_S  0
+
+/** ISP_HIST_BIN7_REG register
+ *  result of histogram bin 7
+ */
+#define ISP_HIST_BIN7_REG (DR_REG_ISP_BASE + 0x1fc)
+/** ISP_HIST_BIN_7 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 7
+ */
+#define ISP_HIST_BIN_7    0x0001FFFFU
+#define ISP_HIST_BIN_7_M  (ISP_HIST_BIN_7_V << ISP_HIST_BIN_7_S)
+#define ISP_HIST_BIN_7_V  0x0001FFFFU
+#define ISP_HIST_BIN_7_S  0
+
+/** ISP_HIST_BIN8_REG register
+ *  result of histogram bin 8
+ */
+#define ISP_HIST_BIN8_REG (DR_REG_ISP_BASE + 0x200)
+/** ISP_HIST_BIN_8 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 8
+ */
+#define ISP_HIST_BIN_8    0x0001FFFFU
+#define ISP_HIST_BIN_8_M  (ISP_HIST_BIN_8_V << ISP_HIST_BIN_8_S)
+#define ISP_HIST_BIN_8_V  0x0001FFFFU
+#define ISP_HIST_BIN_8_S  0
+
+/** ISP_HIST_BIN9_REG register
+ *  result of histogram bin 9
+ */
+#define ISP_HIST_BIN9_REG (DR_REG_ISP_BASE + 0x204)
+/** ISP_HIST_BIN_9 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 9
+ */
+#define ISP_HIST_BIN_9    0x0001FFFFU
+#define ISP_HIST_BIN_9_M  (ISP_HIST_BIN_9_V << ISP_HIST_BIN_9_S)
+#define ISP_HIST_BIN_9_V  0x0001FFFFU
+#define ISP_HIST_BIN_9_S  0
+
+/** ISP_HIST_BIN10_REG register
+ *  result of histogram bin 10
+ */
+#define ISP_HIST_BIN10_REG (DR_REG_ISP_BASE + 0x208)
+/** ISP_HIST_BIN_10 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 10
+ */
+#define ISP_HIST_BIN_10    0x0001FFFFU
+#define ISP_HIST_BIN_10_M  (ISP_HIST_BIN_10_V << ISP_HIST_BIN_10_S)
+#define ISP_HIST_BIN_10_V  0x0001FFFFU
+#define ISP_HIST_BIN_10_S  0
+
+/** ISP_HIST_BIN11_REG register
+ *  result of histogram bin 11
+ */
+#define ISP_HIST_BIN11_REG (DR_REG_ISP_BASE + 0x20c)
+/** ISP_HIST_BIN_11 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 11
+ */
+#define ISP_HIST_BIN_11    0x0001FFFFU
+#define ISP_HIST_BIN_11_M  (ISP_HIST_BIN_11_V << ISP_HIST_BIN_11_S)
+#define ISP_HIST_BIN_11_V  0x0001FFFFU
+#define ISP_HIST_BIN_11_S  0
+
+/** ISP_HIST_BIN12_REG register
+ *  result of histogram bin 12
+ */
+#define ISP_HIST_BIN12_REG (DR_REG_ISP_BASE + 0x210)
+/** ISP_HIST_BIN_12 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 12
+ */
+#define ISP_HIST_BIN_12    0x0001FFFFU
+#define ISP_HIST_BIN_12_M  (ISP_HIST_BIN_12_V << ISP_HIST_BIN_12_S)
+#define ISP_HIST_BIN_12_V  0x0001FFFFU
+#define ISP_HIST_BIN_12_S  0
+
+/** ISP_HIST_BIN13_REG register
+ *  result of histogram bin 13
+ */
+#define ISP_HIST_BIN13_REG (DR_REG_ISP_BASE + 0x214)
+/** ISP_HIST_BIN_13 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 13
+ */
+#define ISP_HIST_BIN_13    0x0001FFFFU
+#define ISP_HIST_BIN_13_M  (ISP_HIST_BIN_13_V << ISP_HIST_BIN_13_S)
+#define ISP_HIST_BIN_13_V  0x0001FFFFU
+#define ISP_HIST_BIN_13_S  0
+
+/** ISP_HIST_BIN14_REG register
+ *  result of histogram bin 14
+ */
+#define ISP_HIST_BIN14_REG (DR_REG_ISP_BASE + 0x218)
+/** ISP_HIST_BIN_14 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 14
+ */
+#define ISP_HIST_BIN_14    0x0001FFFFU
+#define ISP_HIST_BIN_14_M  (ISP_HIST_BIN_14_V << ISP_HIST_BIN_14_S)
+#define ISP_HIST_BIN_14_V  0x0001FFFFU
+#define ISP_HIST_BIN_14_S  0
+
+/** ISP_HIST_BIN15_REG register
+ *  result of histogram bin 15
+ */
+#define ISP_HIST_BIN15_REG (DR_REG_ISP_BASE + 0x21c)
+/** ISP_HIST_BIN_15 : RO; bitpos: [16:0]; default: 0;
+ *  this field represents result of histogram bin 15
+ */
+#define ISP_HIST_BIN_15    0x0001FFFFU
+#define ISP_HIST_BIN_15_M  (ISP_HIST_BIN_15_V << ISP_HIST_BIN_15_S)
+#define ISP_HIST_BIN_15_V  0x0001FFFFU
+#define ISP_HIST_BIN_15_S  0
+
+/** ISP_MEM_AUX_CTRL_0_REG register
+ *  mem aux control register 0
+ */
+#define ISP_MEM_AUX_CTRL_0_REG (DR_REG_ISP_BASE + 0x220)
+/** ISP_HEADER_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  this field configures the mem_aux of isp input buffer memory
+ */
+#define ISP_HEADER_MEM_AUX_CTRL    0x00003FFFU
+#define ISP_HEADER_MEM_AUX_CTRL_M  (ISP_HEADER_MEM_AUX_CTRL_V << ISP_HEADER_MEM_AUX_CTRL_S)
+#define ISP_HEADER_MEM_AUX_CTRL_V  0x00003FFFU
+#define ISP_HEADER_MEM_AUX_CTRL_S  0
+/** ISP_DPC_LUT_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896;
+ *  this field represents this field configures the mem_aux of dpc lut memory
+ */
+#define ISP_DPC_LUT_MEM_AUX_CTRL    0x00003FFFU
+#define ISP_DPC_LUT_MEM_AUX_CTRL_M  (ISP_DPC_LUT_MEM_AUX_CTRL_V << ISP_DPC_LUT_MEM_AUX_CTRL_S)
+#define ISP_DPC_LUT_MEM_AUX_CTRL_V  0x00003FFFU
+#define ISP_DPC_LUT_MEM_AUX_CTRL_S  16
+
+/** ISP_MEM_AUX_CTRL_1_REG register
+ *  mem aux control register 1
+ */
+#define ISP_MEM_AUX_CTRL_1_REG (DR_REG_ISP_BASE + 0x224)
+/** ISP_LSC_LUT_R_GR_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  this field configures the mem_aux of lsc r gr lut memory
+ */
+#define ISP_LSC_LUT_R_GR_MEM_AUX_CTRL    0x00003FFFU
+#define ISP_LSC_LUT_R_GR_MEM_AUX_CTRL_M  (ISP_LSC_LUT_R_GR_MEM_AUX_CTRL_V << ISP_LSC_LUT_R_GR_MEM_AUX_CTRL_S)
+#define ISP_LSC_LUT_R_GR_MEM_AUX_CTRL_V  0x00003FFFU
+#define ISP_LSC_LUT_R_GR_MEM_AUX_CTRL_S  0
+/** ISP_LSC_LUT_GB_B_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896;
+ *  this field configures the mem_aux of lsc gb b lut memory
+ */
+#define ISP_LSC_LUT_GB_B_MEM_AUX_CTRL    0x00003FFFU
+#define ISP_LSC_LUT_GB_B_MEM_AUX_CTRL_M  (ISP_LSC_LUT_GB_B_MEM_AUX_CTRL_V << ISP_LSC_LUT_GB_B_MEM_AUX_CTRL_S)
+#define ISP_LSC_LUT_GB_B_MEM_AUX_CTRL_V  0x00003FFFU
+#define ISP_LSC_LUT_GB_B_MEM_AUX_CTRL_S  16
+
+/** ISP_MEM_AUX_CTRL_2_REG register
+ *  mem aux control register 2
+ */
+#define ISP_MEM_AUX_CTRL_2_REG (DR_REG_ISP_BASE + 0x228)
+/** ISP_BF_MATRIX_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  this field configures the mem_aux of bf line buffer memory
+ */
+#define ISP_BF_MATRIX_MEM_AUX_CTRL    0x00003FFFU
+#define ISP_BF_MATRIX_MEM_AUX_CTRL_M  (ISP_BF_MATRIX_MEM_AUX_CTRL_V << ISP_BF_MATRIX_MEM_AUX_CTRL_S)
+#define ISP_BF_MATRIX_MEM_AUX_CTRL_V  0x00003FFFU
+#define ISP_BF_MATRIX_MEM_AUX_CTRL_S  0
+/** ISP_DPC_MATRIX_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896;
+ *  this field configures the mem_aux of dpc line buffer memory
+ */
+#define ISP_DPC_MATRIX_MEM_AUX_CTRL    0x00003FFFU
+#define ISP_DPC_MATRIX_MEM_AUX_CTRL_M  (ISP_DPC_MATRIX_MEM_AUX_CTRL_V << ISP_DPC_MATRIX_MEM_AUX_CTRL_S)
+#define ISP_DPC_MATRIX_MEM_AUX_CTRL_V  0x00003FFFU
+#define ISP_DPC_MATRIX_MEM_AUX_CTRL_S  16
+
+/** ISP_MEM_AUX_CTRL_3_REG register
+ *  mem aux control register 3
+ */
+#define ISP_MEM_AUX_CTRL_3_REG (DR_REG_ISP_BASE + 0x22c)
+/** ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  this field configures the mem_aux of sharp y line buffer memory
+ */
+#define ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL    0x00003FFFU
+#define ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL_M  (ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL_V << ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL_S)
+#define ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL_V  0x00003FFFU
+#define ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL_S  0
+/** ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896;
+ *  this field configures the mem_aux of demosaic line buffer memory
+ */
+#define ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL    0x00003FFFU
+#define ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL_M  (ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL_V << ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL_S)
+#define ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL_V  0x00003FFFU
+#define ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL_S  16
+
+/** ISP_MEM_AUX_CTRL_4_REG register
+ *  mem aux control register 4
+ */
+#define ISP_MEM_AUX_CTRL_4_REG (DR_REG_ISP_BASE + 0x230)
+/** ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  this field configures the mem_aux of sharp uv line buffer memory
+ */
+#define ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL    0x00003FFFU
+#define ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL_M  (ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL_V << ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL_S)
+#define ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL_V  0x00003FFFU
+#define ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL_S  0
+
+/** ISP_YUV_FORMAT_REG register
+ *  yuv format control register
+ */
+#define ISP_YUV_FORMAT_REG (DR_REG_ISP_BASE + 0x234)
+/** ISP_YUV_MODE : R/W; bitpos: [0]; default: 0;
+ *  this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709
+ */
+#define ISP_YUV_MODE    (BIT(0))
+#define ISP_YUV_MODE_M  (ISP_YUV_MODE_V << ISP_YUV_MODE_S)
+#define ISP_YUV_MODE_V  0x00000001U
+#define ISP_YUV_MODE_S  0
+/** ISP_YUV_RANGE : R/W; bitpos: [1]; default: 0;
+ *  this bit configures the yuv range. 0: full range, 1: limit range
+ */
+#define ISP_YUV_RANGE    (BIT(1))
+#define ISP_YUV_RANGE_M  (ISP_YUV_RANGE_V << ISP_YUV_RANGE_S)
+#define ISP_YUV_RANGE_V  0x00000001U
+#define ISP_YUV_RANGE_S  1
+
+/** ISP_RDN_ECO_CS_REG register
+ *  rdn eco cs register
+ */
+#define ISP_RDN_ECO_CS_REG (DR_REG_ISP_BASE + 0x238)
+/** ISP_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  rdn_eco_en
+ */
+#define ISP_RDN_ECO_EN    (BIT(0))
+#define ISP_RDN_ECO_EN_M  (ISP_RDN_ECO_EN_V << ISP_RDN_ECO_EN_S)
+#define ISP_RDN_ECO_EN_V  0x00000001U
+#define ISP_RDN_ECO_EN_S  0
+/** ISP_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  rdn_eco_result
+ */
+#define ISP_RDN_ECO_RESULT    (BIT(1))
+#define ISP_RDN_ECO_RESULT_M  (ISP_RDN_ECO_RESULT_V << ISP_RDN_ECO_RESULT_S)
+#define ISP_RDN_ECO_RESULT_V  0x00000001U
+#define ISP_RDN_ECO_RESULT_S  1
+
+/** ISP_RDN_ECO_LOW_REG register
+ *  rdn eco all low register
+ */
+#define ISP_RDN_ECO_LOW_REG (DR_REG_ISP_BASE + 0x23c)
+/** ISP_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  rdn_eco_low
+ */
+#define ISP_RDN_ECO_LOW    0xFFFFFFFFU
+#define ISP_RDN_ECO_LOW_M  (ISP_RDN_ECO_LOW_V << ISP_RDN_ECO_LOW_S)
+#define ISP_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define ISP_RDN_ECO_LOW_S  0
+
+/** ISP_RDN_ECO_HIGH_REG register
+ *  rdn eco all high register
+ */
+#define ISP_RDN_ECO_HIGH_REG (DR_REG_ISP_BASE + 0x240)
+/** ISP_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  rdn_eco_high
+ */
+#define ISP_RDN_ECO_HIGH    0xFFFFFFFFU
+#define ISP_RDN_ECO_HIGH_M  (ISP_RDN_ECO_HIGH_V << ISP_RDN_ECO_HIGH_S)
+#define ISP_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define ISP_RDN_ECO_HIGH_S  0
+
+/** ISP_CROP_CTRL_REG register
+ *  isp_crop ctrl register
+ */
+#define ISP_CROP_CTRL_REG (DR_REG_ISP_BASE + 0x244)
+/** ISP_CROP_SFT_RST : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear err st
+ */
+#define ISP_CROP_SFT_RST    (BIT(0))
+#define ISP_CROP_SFT_RST_M  (ISP_CROP_SFT_RST_V << ISP_CROP_SFT_RST_S)
+#define ISP_CROP_SFT_RST_V  0x00000001U
+#define ISP_CROP_SFT_RST_S  0
+
+/** ISP_CROP_Y_CAPTURE_REG register
+ *  isp_crop row capture range register
+ */
+#define ISP_CROP_Y_CAPTURE_REG (DR_REG_ISP_BASE + 0x248)
+/** ISP_CROP_Y_START : R/W; bitpos: [11:0]; default: 0;
+ *  isp_crop capture row start index
+ */
+#define ISP_CROP_Y_START    0x00000FFFU
+#define ISP_CROP_Y_START_M  (ISP_CROP_Y_START_V << ISP_CROP_Y_START_S)
+#define ISP_CROP_Y_START_V  0x00000FFFU
+#define ISP_CROP_Y_START_S  0
+/** ISP_CROP_Y_END : R/W; bitpos: [23:12]; default: 0;
+ *  isp_crop capture row end index
+ */
+#define ISP_CROP_Y_END    0x00000FFFU
+#define ISP_CROP_Y_END_M  (ISP_CROP_Y_END_V << ISP_CROP_Y_END_S)
+#define ISP_CROP_Y_END_V  0x00000FFFU
+#define ISP_CROP_Y_END_S  12
+
+/** ISP_CROP_X_CAPTURE_REG register
+ *  isp_crop col capture range register
+ */
+#define ISP_CROP_X_CAPTURE_REG (DR_REG_ISP_BASE + 0x24c)
+/** ISP_CROP_X_START : R/W; bitpos: [11:0]; default: 0;
+ *  isp_crop capture col start index
+ */
+#define ISP_CROP_X_START    0x00000FFFU
+#define ISP_CROP_X_START_M  (ISP_CROP_X_START_V << ISP_CROP_X_START_S)
+#define ISP_CROP_X_START_V  0x00000FFFU
+#define ISP_CROP_X_START_S  0
+/** ISP_CROP_X_END : R/W; bitpos: [23:12]; default: 0;
+ *  isp_crop capture col end index
+ */
+#define ISP_CROP_X_END    0x00000FFFU
+#define ISP_CROP_X_END_M  (ISP_CROP_X_END_V << ISP_CROP_X_END_S)
+#define ISP_CROP_X_END_V  0x00000FFFU
+#define ISP_CROP_X_END_S  12
+
+/** ISP_CROP_ERR_ST_REG register
+ *  crop error state register
+ */
+#define ISP_CROP_ERR_ST_REG (DR_REG_ISP_BASE + 0x250)
+/** ISP_CROP_Y_MISMATCH : RO; bitpos: [0]; default: 0;
+ *  Represents isp_corp row end index over image size
+ */
+#define ISP_CROP_Y_MISMATCH    (BIT(0))
+#define ISP_CROP_Y_MISMATCH_M  (ISP_CROP_Y_MISMATCH_V << ISP_CROP_Y_MISMATCH_S)
+#define ISP_CROP_Y_MISMATCH_V  0x00000001U
+#define ISP_CROP_Y_MISMATCH_S  0
+/** ISP_CROP_X_MISMATCH : RO; bitpos: [1]; default: 0;
+ *  Represents isp_corp col end index over image size
+ */
+#define ISP_CROP_X_MISMATCH    (BIT(1))
+#define ISP_CROP_X_MISMATCH_M  (ISP_CROP_X_MISMATCH_V << ISP_CROP_X_MISMATCH_S)
+#define ISP_CROP_X_MISMATCH_V  0x00000001U
+#define ISP_CROP_X_MISMATCH_S  1
+/** ISP_CROP_Y_END_EVEN : RO; bitpos: [2]; default: 0;
+ *  Represents isp_corp row end index is an even number
+ */
+#define ISP_CROP_Y_END_EVEN    (BIT(2))
+#define ISP_CROP_Y_END_EVEN_M  (ISP_CROP_Y_END_EVEN_V << ISP_CROP_Y_END_EVEN_S)
+#define ISP_CROP_Y_END_EVEN_V  0x00000001U
+#define ISP_CROP_Y_END_EVEN_S  2
+/** ISP_CROP_X_END_EVEN : RO; bitpos: [3]; default: 0;
+ *  Represents isp_corp col end index is an even number
+ */
+#define ISP_CROP_X_END_EVEN    (BIT(3))
+#define ISP_CROP_X_END_EVEN_M  (ISP_CROP_X_END_EVEN_V << ISP_CROP_X_END_EVEN_S)
+#define ISP_CROP_X_END_EVEN_V  0x00000001U
+#define ISP_CROP_X_END_EVEN_S  3
+/** ISP_CROP_Y_START_ODD : RO; bitpos: [4]; default: 0;
+ *  Represents isp_corp row start index is an odd number
+ */
+#define ISP_CROP_Y_START_ODD    (BIT(4))
+#define ISP_CROP_Y_START_ODD_M  (ISP_CROP_Y_START_ODD_V << ISP_CROP_Y_START_ODD_S)
+#define ISP_CROP_Y_START_ODD_V  0x00000001U
+#define ISP_CROP_Y_START_ODD_S  4
+/** ISP_CROP_X_START_ODD : RO; bitpos: [5]; default: 0;
+ *  Represents isp_corp col start index is an odd number
+ */
+#define ISP_CROP_X_START_ODD    (BIT(5))
+#define ISP_CROP_X_START_ODD_M  (ISP_CROP_X_START_ODD_V << ISP_CROP_X_START_ODD_S)
+#define ISP_CROP_X_START_ODD_V  0x00000001U
+#define ISP_CROP_X_START_ODD_S  5
+
+/** ISP_WBG_COEF_R_REG register
+ *  white balance red gain register 0
+ */
+#define ISP_WBG_COEF_R_REG (DR_REG_ISP_BASE + 0x254)
+/** ISP_WBG_R : R/W; bitpos: [11:0]; default: 256;
+ *  Configures the white balance red gain
+ */
+#define ISP_WBG_R    0x00000FFFU
+#define ISP_WBG_R_M  (ISP_WBG_R_V << ISP_WBG_R_S)
+#define ISP_WBG_R_V  0x00000FFFU
+#define ISP_WBG_R_S  0
+
+/** ISP_WBG_COEF_G_REG register
+ *  white balance green gain register 0
+ */
+#define ISP_WBG_COEF_G_REG (DR_REG_ISP_BASE + 0x258)
+/** ISP_WBG_G : R/W; bitpos: [11:0]; default: 256;
+ *  Configures the white balance green gain
+ */
+#define ISP_WBG_G    0x00000FFFU
+#define ISP_WBG_G_M  (ISP_WBG_G_V << ISP_WBG_G_S)
+#define ISP_WBG_G_V  0x00000FFFU
+#define ISP_WBG_G_S  0
+
+/** ISP_WBG_COEF_B_REG register
+ *  white balance blue gain register 0
+ */
+#define ISP_WBG_COEF_B_REG (DR_REG_ISP_BASE + 0x25c)
+/** ISP_WBG_B : R/W; bitpos: [11:0]; default: 256;
+ *  Configures the white balance blue gain
+ */
+#define ISP_WBG_B    0x00000FFFU
+#define ISP_WBG_B_M  (ISP_WBG_B_V << ISP_WBG_B_S)
+#define ISP_WBG_B_V  0x00000FFFU
+#define ISP_WBG_B_S  0
+
+/** ISP_COLOR_HUE_CTRL_REG register
+ *  color control register
+ */
+#define ISP_COLOR_HUE_CTRL_REG (DR_REG_ISP_BASE + 0x260)
+/** ISP_COLOR_HUE_H : R/W; bitpos: [0]; default: 0;
+ *  Configures the color hue angle most bit
+ */
+#define ISP_COLOR_HUE_H    (BIT(0))
+#define ISP_COLOR_HUE_H_M  (ISP_COLOR_HUE_H_V << ISP_COLOR_HUE_H_S)
+#define ISP_COLOR_HUE_H_V  0x00000001U
+#define ISP_COLOR_HUE_H_S  0
+
+/** ISP_AWB_BX_REG register
+ *  awb window register in x-direction
+ */
+#define ISP_AWB_BX_REG (DR_REG_ISP_BASE + 0x264)
+/** ISP_AWB_X_BSIZE : R/W; bitpos: [11:0]; default: 0;
+ *  Configures every block x size, min number is 4
+ */
+#define ISP_AWB_X_BSIZE    0x00000FFFU
+#define ISP_AWB_X_BSIZE_M  (ISP_AWB_X_BSIZE_V << ISP_AWB_X_BSIZE_S)
+#define ISP_AWB_X_BSIZE_V  0x00000FFFU
+#define ISP_AWB_X_BSIZE_S  0
+/** ISP_AWB_X_START : R/W; bitpos: [23:12]; default: 0;
+ *  Configures first block start x address
+ */
+#define ISP_AWB_X_START    0x00000FFFU
+#define ISP_AWB_X_START_M  (ISP_AWB_X_START_V << ISP_AWB_X_START_S)
+#define ISP_AWB_X_START_V  0x00000FFFU
+#define ISP_AWB_X_START_S  12
+
+/** ISP_AWB_BY_REG register
+ *  awb window register in y-direction
+ */
+#define ISP_AWB_BY_REG (DR_REG_ISP_BASE + 0x268)
+/** ISP_AWB_Y_BSIZE : R/W; bitpos: [11:0]; default: 0;
+ *  Configures every block y size
+ */
+#define ISP_AWB_Y_BSIZE    0x00000FFFU
+#define ISP_AWB_Y_BSIZE_M  (ISP_AWB_Y_BSIZE_V << ISP_AWB_Y_BSIZE_S)
+#define ISP_AWB_Y_BSIZE_V  0x00000FFFU
+#define ISP_AWB_Y_BSIZE_S  0
+/** ISP_AWB_Y_START : R/W; bitpos: [23:12]; default: 0;
+ *  Configures first block start y address
+ */
+#define ISP_AWB_Y_START    0x00000FFFU
+#define ISP_AWB_Y_START_M  (ISP_AWB_Y_START_V << ISP_AWB_Y_START_S)
+#define ISP_AWB_Y_START_V  0x00000FFFU
+#define ISP_AWB_Y_START_S  12
+
+/** ISP_STATE_REG register
+ *  awb window register in y-direction
+ */
+#define ISP_STATE_REG (DR_REG_ISP_BASE + 0x26c)
+/** ISP_TAIL_BUSY : RO; bitpos: [0]; default: 0;
+ *  Represents isp_tail state
+ */
+#define ISP_TAIL_BUSY    (BIT(0))
+#define ISP_TAIL_BUSY_M  (ISP_TAIL_BUSY_V << ISP_TAIL_BUSY_S)
+#define ISP_TAIL_BUSY_V  0x00000001U
+#define ISP_TAIL_BUSY_S  0
+/** ISP_HEADER_BUSY : RO; bitpos: [1]; default: 0;
+ *  Represents isp_header state
+ */
+#define ISP_HEADER_BUSY    (BIT(1))
+#define ISP_HEADER_BUSY_M  (ISP_HEADER_BUSY_V << ISP_HEADER_BUSY_S)
+#define ISP_HEADER_BUSY_V  0x00000001U
+#define ISP_HEADER_BUSY_S  1
+
+/** ISP_SHADOW_REG_CTRL_REG register
+ *  shadow register ctrl register
+ */
+#define ISP_SHADOW_REG_CTRL_REG (DR_REG_ISP_BASE + 0x270)
+/** ISP_BLC_UPDATE : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to update blc configuration register
+ */
+#define ISP_BLC_UPDATE    (BIT(0))
+#define ISP_BLC_UPDATE_M  (ISP_BLC_UPDATE_V << ISP_BLC_UPDATE_S)
+#define ISP_BLC_UPDATE_V  0x00000001U
+#define ISP_BLC_UPDATE_S  0
+/** ISP_DPC_UPDATE : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to update dpc configuration register
+ */
+#define ISP_DPC_UPDATE    (BIT(1))
+#define ISP_DPC_UPDATE_M  (ISP_DPC_UPDATE_V << ISP_DPC_UPDATE_S)
+#define ISP_DPC_UPDATE_V  0x00000001U
+#define ISP_DPC_UPDATE_S  1
+/** ISP_BF_UPDATE : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to update bf configuration register
+ */
+#define ISP_BF_UPDATE    (BIT(2))
+#define ISP_BF_UPDATE_M  (ISP_BF_UPDATE_V << ISP_BF_UPDATE_S)
+#define ISP_BF_UPDATE_V  0x00000001U
+#define ISP_BF_UPDATE_S  2
+/** ISP_WBG_UPDATE : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to update wbg configuration register
+ */
+#define ISP_WBG_UPDATE    (BIT(3))
+#define ISP_WBG_UPDATE_M  (ISP_WBG_UPDATE_V << ISP_WBG_UPDATE_S)
+#define ISP_WBG_UPDATE_V  0x00000001U
+#define ISP_WBG_UPDATE_S  3
+/** ISP_CCM_UPDATE : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to update ccm configuration register
+ */
+#define ISP_CCM_UPDATE    (BIT(4))
+#define ISP_CCM_UPDATE_M  (ISP_CCM_UPDATE_V << ISP_CCM_UPDATE_S)
+#define ISP_CCM_UPDATE_V  0x00000001U
+#define ISP_CCM_UPDATE_S  4
+/** ISP_SHARP_UPDATE : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to update sharp configuration register
+ */
+#define ISP_SHARP_UPDATE    (BIT(6))
+#define ISP_SHARP_UPDATE_M  (ISP_SHARP_UPDATE_V << ISP_SHARP_UPDATE_S)
+#define ISP_SHARP_UPDATE_V  0x00000001U
+#define ISP_SHARP_UPDATE_S  6
+/** ISP_COLOR_UPDATE : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to update color configuration register
+ */
+#define ISP_COLOR_UPDATE    (BIT(7))
+#define ISP_COLOR_UPDATE_M  (ISP_COLOR_UPDATE_V << ISP_COLOR_UPDATE_S)
+#define ISP_COLOR_UPDATE_V  0x00000001U
+#define ISP_COLOR_UPDATE_S  7
+/** ISP_SHADOW_UPDATE_SEL : R/W; bitpos: [31:30]; default: 1;
+ *  Configures shadow register update type. 0: no shadow register. 1: update every
+ *  vsyn. 2: update only the next vsync after write reg_xxx_update
+ */
+#define ISP_SHADOW_UPDATE_SEL    0x00000003U
+#define ISP_SHADOW_UPDATE_SEL_M  (ISP_SHADOW_UPDATE_SEL_V << ISP_SHADOW_UPDATE_SEL_S)
+#define ISP_SHADOW_UPDATE_SEL_V  0x00000003U
+#define ISP_SHADOW_UPDATE_SEL_S  30
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/isp_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/isp_struct.h
new file mode 100644
index 0000000000..8f65f76752
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/isp_struct.h
@@ -0,0 +1,3285 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Version Register */
+/** Type of ver_date register
+ *  version control register
+ */
+typedef union {
+    struct {
+        /** ver_data : R/W; bitpos: [31:0]; default: 539035144;
+         *  csv version
+         */
+        uint32_t ver_data:32;
+    };
+    uint32_t val;
+} isp_ver_date_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of clk_en register
+ *  isp clk control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the clk force on of isp reg. 0: disable, 1: enable
+         */
+        uint32_t clk_en:1;
+        /** clk_blc_force_on : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the clk force on of blc. 0: disable, 1: enable
+         */
+        uint32_t clk_blc_force_on:1;
+        /** clk_dpc_force_on : R/W; bitpos: [2]; default: 0;
+         *  this bit configures the clk force on of dpc. 0: disable, 1: enable
+         */
+        uint32_t clk_dpc_force_on:1;
+        /** clk_bf_force_on : R/W; bitpos: [3]; default: 0;
+         *  this bit configures the clk force on of bf. 0: disable, 1: enable
+         */
+        uint32_t clk_bf_force_on:1;
+        /** clk_lsc_force_on : R/W; bitpos: [4]; default: 0;
+         *  this bit configures the clk force on of lsc. 0: disable, 1: enable
+         */
+        uint32_t clk_lsc_force_on:1;
+        /** clk_demosaic_force_on : R/W; bitpos: [5]; default: 0;
+         *  this bit configures the clk force on of demosaic. 0: disable, 1: enable
+         */
+        uint32_t clk_demosaic_force_on:1;
+        /** clk_median_force_on : R/W; bitpos: [6]; default: 0;
+         *  this bit configures the clk force on of median. 0: disable, 1: enable
+         */
+        uint32_t clk_median_force_on:1;
+        /** clk_ccm_force_on : R/W; bitpos: [7]; default: 0;
+         *  this bit configures the clk force on of ccm. 0: disable, 1: enable
+         */
+        uint32_t clk_ccm_force_on:1;
+        /** clk_gamma_force_on : R/W; bitpos: [8]; default: 0;
+         *  this bit configures the clk force on of gamma. 0: disable, 1: enable
+         */
+        uint32_t clk_gamma_force_on:1;
+        /** clk_rgb2yuv_force_on : R/W; bitpos: [9]; default: 0;
+         *  this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable
+         */
+        uint32_t clk_rgb2yuv_force_on:1;
+        /** clk_sharp_force_on : R/W; bitpos: [10]; default: 0;
+         *  this bit configures the clk force on of sharp. 0: disable, 1: enable
+         */
+        uint32_t clk_sharp_force_on:1;
+        /** clk_color_force_on : R/W; bitpos: [11]; default: 0;
+         *  this bit configures the clk force on of color. 0: disable, 1: enable
+         */
+        uint32_t clk_color_force_on:1;
+        /** clk_yuv2rgb_force_on : R/W; bitpos: [12]; default: 0;
+         *  this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable
+         */
+        uint32_t clk_yuv2rgb_force_on:1;
+        /** clk_ae_force_on : R/W; bitpos: [13]; default: 0;
+         *  this bit configures the clk force on of ae. 0: disable, 1: enable
+         */
+        uint32_t clk_ae_force_on:1;
+        /** clk_af_force_on : R/W; bitpos: [14]; default: 0;
+         *  this bit configures the clk force on of af. 0: disable, 1: enable
+         */
+        uint32_t clk_af_force_on:1;
+        /** clk_awb_force_on : R/W; bitpos: [15]; default: 0;
+         *  this bit configures the clk force on of awb. 0: disable, 1: enable
+         */
+        uint32_t clk_awb_force_on:1;
+        /** clk_hist_force_on : R/W; bitpos: [16]; default: 0;
+         *  this bit configures the clk force on of hist. 0: disable, 1: enable
+         */
+        uint32_t clk_hist_force_on:1;
+        /** clk_mipi_idi_force_on : R/W; bitpos: [17]; default: 0;
+         *  this bit configures the clk force on of mipi idi input. 0: disable, 1: enable
+         */
+        uint32_t clk_mipi_idi_force_on:1;
+        /** isp_mem_clk_force_on : R/W; bitpos: [18]; default: 0;
+         *  this bit configures the clk force on of all isp memory. 0: disable, 1: enable
+         */
+        uint32_t isp_mem_clk_force_on:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} isp_clk_en_reg_t;
+
+/** Type of cntl register
+ *  isp module enable control register
+ */
+typedef union {
+    struct {
+        /** mipi_data_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures mipi input data enable. 0: disable, 1: enable
+         */
+        uint32_t mipi_data_en:1;
+        /** isp_en : R/W; bitpos: [1]; default: 1;
+         *  this bit configures isp global enable. 0: disable, 1: enable
+         */
+        uint32_t isp_en:1;
+        /** blc_en : R/W; bitpos: [2]; default: 0;
+         *  this bit configures blc enable. 0: disable, 1: enable
+         */
+        uint32_t blc_en:1;
+        /** dpc_en : R/W; bitpos: [3]; default: 0;
+         *  this bit configures dpc enable. 0: disable, 1: enable
+         */
+        uint32_t dpc_en:1;
+        /** bf_en : R/W; bitpos: [4]; default: 0;
+         *  this bit configures bf enable. 0: disable, 1: enable
+         */
+        uint32_t bf_en:1;
+        /** lsc_en : R/W; bitpos: [5]; default: 0;
+         *  this bit configures lsc enable. 0: disable, 1: enable
+         */
+        uint32_t lsc_en:1;
+        /** demosaic_en : R/W; bitpos: [6]; default: 1;
+         *  this bit configures demosaic enable. 0: disable, 1: enable
+         */
+        uint32_t demosaic_en:1;
+        /** median_en : R/W; bitpos: [7]; default: 0;
+         *  this bit configures median enable. 0: disable, 1: enable
+         */
+        uint32_t median_en:1;
+        /** ccm_en : R/W; bitpos: [8]; default: 0;
+         *  this bit configures ccm enable. 0: disable, 1: enable
+         */
+        uint32_t ccm_en:1;
+        /** gamma_en : R/W; bitpos: [9]; default: 0;
+         *  this bit configures gamma enable. 0: disable, 1: enable
+         */
+        uint32_t gamma_en:1;
+        /** rgb2yuv_en : R/W; bitpos: [10]; default: 1;
+         *  this bit configures rgb2yuv enable. 0: disable, 1: enable
+         */
+        uint32_t rgb2yuv_en:1;
+        /** sharp_en : R/W; bitpos: [11]; default: 0;
+         *  this bit configures sharp enable. 0: disable, 1: enable
+         */
+        uint32_t sharp_en:1;
+        /** color_en : R/W; bitpos: [12]; default: 0;
+         *  this bit configures color enable. 0: disable, 1: enable
+         */
+        uint32_t color_en:1;
+        /** yuv2rgb_en : R/W; bitpos: [13]; default: 1;
+         *  this bit configures yuv2rgb enable. 0: disable, 1: enable
+         */
+        uint32_t yuv2rgb_en:1;
+        /** ae_en : R/W; bitpos: [14]; default: 0;
+         *  this bit configures ae enable. 0: disable, 1: enable
+         */
+        uint32_t ae_en:1;
+        /** af_en : R/W; bitpos: [15]; default: 0;
+         *  this bit configures af enable. 0: disable, 1: enable
+         */
+        uint32_t af_en:1;
+        /** awb_en : R/W; bitpos: [16]; default: 0;
+         *  this bit configures awb enable. 0: disable, 1: enable
+         */
+        uint32_t awb_en:1;
+        /** hist_en : R/W; bitpos: [17]; default: 0;
+         *  this bit configures hist enable. 0: disable, 1: enable
+         */
+        uint32_t hist_en:1;
+        uint32_t reserved_18:6;
+        /** byte_endian_order : R/W; bitpos: [24]; default: 0;
+         *  select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1:
+         *  {[7:0], [15:8], [23:16], [31:24]}
+         */
+        uint32_t byte_endian_order:1;
+        /** isp_data_type : R/W; bitpos: [26:25]; default: 0;
+         *  this field configures input data type, 0:RAW8 1:RAW10 2:RAW12
+         */
+        uint32_t isp_data_type:2;
+        /** isp_in_src : R/W; bitpos: [28:27]; default: 0;
+         *  this field configures input data source, 0:CSI HOST 1:CAM 2:DMA
+         */
+        uint32_t isp_in_src:2;
+        /** isp_out_type : R/W; bitpos: [31:29]; default: 2;
+         *  this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4:
+         *  RGB565
+         */
+        uint32_t isp_out_type:3;
+    };
+    uint32_t val;
+} isp_cntl_reg_t;
+
+/** Type of hsync_cnt register
+ *  header hsync interval control register
+ */
+typedef union {
+    struct {
+        /** hsync_cnt : R/W; bitpos: [7:0]; default: 7;
+         *  this field configures the number of clock before hsync and after vsync and line_end
+         *  when decodes pix data from idi to isp
+         */
+        uint32_t hsync_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} isp_hsync_cnt_reg_t;
+
+/** Type of frame_cfg register
+ *  frame control parameter register
+ */
+typedef union {
+    struct {
+        /** vadr_num : R/W; bitpos: [11:0]; default: 480;
+         *  this field configures input image size in y-direction, image row number - 1
+         */
+        uint32_t vadr_num:12;
+        /** hadr_num : R/W; bitpos: [23:12]; default: 480;
+         *  this field configures input image size in x-direction, image line number - 1
+         */
+        uint32_t hadr_num:12;
+        uint32_t reserved_24:3;
+        /** bayer_mode : R/W; bitpos: [28:27]; default: 0;
+         *  this field configures the bayer mode of input pixel. 00 : BG/GR    01 : GB/RG   10
+         *  : GR/BG  11 : RG/GB
+         */
+        uint32_t bayer_mode:2;
+        /** hsync_start_exist : R/W; bitpos: [29]; default: 1;
+         *  this bit configures the line end start exist or not. 0: not exist, 1: exist
+         */
+        uint32_t hsync_start_exist:1;
+        /** hsync_end_exist : R/W; bitpos: [30]; default: 1;
+         *  this bit configures the line end packet exist or not. 0: not exist, 1: exist
+         */
+        uint32_t hsync_end_exist:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} isp_frame_cfg_reg_t;
+
+/** Type of ccm_coef0 register
+ *  ccm coef register 0
+ */
+typedef union {
+    struct {
+        /** ccm_rr : R/W; bitpos: [12:0]; default: 1856;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_rr:13;
+        /** ccm_rg : R/W; bitpos: [25:13]; default: 4736;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_rg:13;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_ccm_coef0_reg_t;
+
+/** Type of ccm_coef1 register
+ *  ccm coef register 1
+ */
+typedef union {
+    struct {
+        /** ccm_rb : R/W; bitpos: [12:0]; default: 4288;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_rb:13;
+        /** ccm_gr : R/W; bitpos: [25:13]; default: 4416;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_gr:13;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_ccm_coef1_reg_t;
+
+/** Type of ccm_coef3 register
+ *  ccm coef register 3
+ */
+typedef union {
+    struct {
+        /** ccm_gg : R/W; bitpos: [12:0]; default: 1664;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_gg:13;
+        /** ccm_gb : R/W; bitpos: [25:13]; default: 4352;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_gb:13;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_ccm_coef3_reg_t;
+
+/** Type of ccm_coef4 register
+ *  ccm coef register 4
+ */
+typedef union {
+    struct {
+        /** ccm_br : R/W; bitpos: [12:0]; default: 4160;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_br:13;
+        /** ccm_bg : R/W; bitpos: [25:13]; default: 4800;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_bg:13;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_ccm_coef4_reg_t;
+
+/** Type of ccm_coef5 register
+ *  ccm coef register 5
+ */
+typedef union {
+    struct {
+        /** ccm_bb : R/W; bitpos: [12:0]; default: 1856;
+         *  this field configures the color correction matrix coefficient
+         */
+        uint32_t ccm_bb:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} isp_ccm_coef5_reg_t;
+
+/** Type of bf_matrix_ctrl register
+ *  bf pix2matrix ctrl
+ */
+typedef union {
+    struct {
+        /** bf_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0;
+         *  matrix tail pixen low level threshold, should not to large to prevent expanding to
+         *  next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0
+         *  and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse
+         *  function
+         */
+        uint32_t bf_tail_pixen_pulse_tl:8;
+        /** bf_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0;
+         *  matrix tail pixen high level threshold, must < hnum-1, only
+         *  reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and
+         *  reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse
+         *  function
+         */
+        uint32_t bf_tail_pixen_pulse_th:8;
+        /** bf_padding_data : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures bf matrix padding data
+         */
+        uint32_t bf_padding_data:8;
+        /** bf_padding_mode : R/W; bitpos: [24]; default: 0;
+         *  this bit configures the padding mode of bf matrix.  0: use pixel in image to do
+         *  padding   1: use reg_padding_data to do padding
+         */
+        uint32_t bf_padding_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} isp_bf_matrix_ctrl_reg_t;
+
+/** Type of bf_sigma register
+ *  bf denoising level control register
+ */
+typedef union {
+    struct {
+        /** sigma : R/W; bitpos: [5:0]; default: 2;
+         *  this field configures the bayer denoising level, valid data from 2 to 20
+         */
+        uint32_t sigma:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} isp_bf_sigma_reg_t;
+
+/** Type of bf_gau0 register
+ *  bf gau template register 0
+ */
+typedef union {
+    struct {
+        /** gau_template21 : R/W; bitpos: [3:0]; default: 15;
+         *  this field configures index 21 of gaussian template
+         */
+        uint32_t gau_template21:4;
+        /** gau_template20 : R/W; bitpos: [7:4]; default: 15;
+         *  this field configures index 20 of gaussian template
+         */
+        uint32_t gau_template20:4;
+        /** gau_template12 : R/W; bitpos: [11:8]; default: 15;
+         *  this field configures index 12 of gaussian template
+         */
+        uint32_t gau_template12:4;
+        /** gau_template11 : R/W; bitpos: [15:12]; default: 15;
+         *  this field configures index 11 of gaussian template
+         */
+        uint32_t gau_template11:4;
+        /** gau_template10 : R/W; bitpos: [19:16]; default: 15;
+         *  this field configures index 10 of gaussian template
+         */
+        uint32_t gau_template10:4;
+        /** gau_template02 : R/W; bitpos: [23:20]; default: 15;
+         *  this field configures index 02 of gaussian template
+         */
+        uint32_t gau_template02:4;
+        /** gau_template01 : R/W; bitpos: [27:24]; default: 15;
+         *  this field configures index 01 of gaussian template
+         */
+        uint32_t gau_template01:4;
+        /** gau_template00 : R/W; bitpos: [31:28]; default: 15;
+         *  this field configures index 00 of gaussian template
+         */
+        uint32_t gau_template00:4;
+    };
+    uint32_t val;
+} isp_bf_gau0_reg_t;
+
+/** Type of bf_gau1 register
+ *  bf gau template register 1
+ */
+typedef union {
+    struct {
+        /** gau_template22 : R/W; bitpos: [3:0]; default: 15;
+         *  this field configures index 22 of gaussian template
+         */
+        uint32_t gau_template22:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} isp_bf_gau1_reg_t;
+
+/** Type of dpc_ctrl register
+ *  DPC mode control register
+ */
+typedef union {
+    struct {
+        /** dpc_check_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the check mode enable. 0: disable, 1: enable
+         */
+        uint32_t dpc_check_en:1;
+        /** sta_en : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the sta dpc enable. 0: disable, 1: enable
+         */
+        uint32_t sta_en:1;
+        /** dyn_en : R/W; bitpos: [2]; default: 1;
+         *  this bit configures the dyn dpc enable. 0: disable, 1: enable
+         */
+        uint32_t dyn_en:1;
+        /** dpc_black_en : R/W; bitpos: [3]; default: 0;
+         *  this bit configures input image type select when in check mode, 0: white img, 1:
+         *  black img
+         */
+        uint32_t dpc_black_en:1;
+        /** dpc_method_sel : R/W; bitpos: [4]; default: 0;
+         *  this bit configures dyn dpc method select. 0: simple method, 1: hard method
+         */
+        uint32_t dpc_method_sel:1;
+        /** dpc_check_od_en : R/W; bitpos: [5]; default: 0;
+         *  this bit configures output pixel data when in check mode or not. 0: no data output,
+         *  1: data output
+         */
+        uint32_t dpc_check_od_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} isp_dpc_ctrl_reg_t;
+
+/** Type of dpc_conf register
+ *  DPC parameter config register
+ */
+typedef union {
+    struct {
+        /** dpc_threshold_l : R/W; bitpos: [7:0]; default: 48;
+         *  this bit configures the threshold to detect black img in check mode, or the low
+         *  threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit
+         *  10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1
+         */
+        uint32_t dpc_threshold_l:8;
+        /** dpc_threshold_h : R/W; bitpos: [15:8]; default: 48;
+         *  this bit configures the threshold to detect white img in check mode, or the high
+         *  threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit
+         *  10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1
+         */
+        uint32_t dpc_threshold_h:8;
+        /** dpc_factor_dark : R/W; bitpos: [21:16]; default: 16;
+         *  this field configures the dynamic correction method 1 dark   factor
+         */
+        uint32_t dpc_factor_dark:6;
+        /** dpc_factor_brig : R/W; bitpos: [27:22]; default: 16;
+         *  this field configures the dynamic correction method 1 bright factor
+         */
+        uint32_t dpc_factor_brig:6;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_dpc_conf_reg_t;
+
+/** Type of dpc_matrix_ctrl register
+ *  dpc pix2matrix ctrl
+ */
+typedef union {
+    struct {
+        /** dpc_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0;
+         *  matrix tail pixen low level threshold,  should not to large to prevent expanding to
+         *  next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0
+         *  and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail
+         *  pulse function
+         */
+        uint32_t dpc_tail_pixen_pulse_tl:8;
+        /** dpc_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0;
+         *  matrix tail pixen high level threshold, must < hnum-1, only
+         *  reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and
+         *  reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse
+         *  function
+         */
+        uint32_t dpc_tail_pixen_pulse_th:8;
+        /** dpc_padding_data : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures dpc matrix padding data
+         */
+        uint32_t dpc_padding_data:8;
+        /** dpc_padding_mode : R/W; bitpos: [24]; default: 0;
+         *  this bit configures the padding mode of dpc matrix.  0: use pixel in image to do
+         *  padding   1: use reg_padding_data to do padding
+         */
+        uint32_t dpc_padding_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} isp_dpc_matrix_ctrl_reg_t;
+
+/** Type of lut_cmd register
+ *  LUT command register
+ */
+typedef union {
+    struct {
+        /** lut_addr : WT; bitpos: [11:0]; default: 0;
+         *  this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b
+         *  lut, 01 sel r_gr lut
+         */
+        uint32_t lut_addr:12;
+        /** lut_num : WT; bitpos: [15:12]; default: 0;
+         *  this field configures the lut selection. 0000:LSC LUT 0001:DPC LUT
+         */
+        uint32_t lut_num:4;
+        /** lut_cmd : WT; bitpos: [16]; default: 0;
+         *  this bit configures the access event of lut. 0:rd 1: wr
+         */
+        uint32_t lut_cmd:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_lut_cmd_reg_t;
+
+/** Type of lut_wdata register
+ *  LUT write data register
+ */
+typedef union {
+    struct {
+        /** lut_wdata : R/W; bitpos: [31:0]; default: 0;
+         *  this field configures the write data of lut. please initial ISP_LUT_WDATA before
+         *  write ISP_LUT_CMD register
+         */
+        uint32_t lut_wdata:32;
+    };
+    uint32_t val;
+} isp_lut_wdata_reg_t;
+
+/** Type of lsc_tablesize register
+ *  LSC point in x-direction
+ */
+typedef union {
+    struct {
+        /** lsc_xtablesize : R/W; bitpos: [4:0]; default: 31;
+         *  this field configures lsc table size in x-direction
+         */
+        uint32_t lsc_xtablesize:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} isp_lsc_tablesize_reg_t;
+
+/** Type of demosaic_matrix_ctrl register
+ *  demosaic pix2matrix ctrl
+ */
+typedef union {
+    struct {
+        /** demosaic_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0;
+         *  matrix tail pixen low level threshold,  should not to large to prevent expanding to
+         *  next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and
+         *  reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th <
+         *  reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function
+         */
+        uint32_t demosaic_tail_pixen_pulse_tl:8;
+        /** demosaic_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0;
+         *  matrix tail pixen high level threshold, must < hnum-1, only
+         *  reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and
+         *  reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable
+         *  tail pulse function
+         */
+        uint32_t demosaic_tail_pixen_pulse_th:8;
+        /** demosaic_padding_data : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures demosaic matrix padding data
+         */
+        uint32_t demosaic_padding_data:8;
+        /** demosaic_padding_mode : R/W; bitpos: [24]; default: 0;
+         *  this bit configures the padding mode of demosaic matrix.  0: use pixel in image to
+         *  do padding   1: use reg_padding_data to do padding
+         */
+        uint32_t demosaic_padding_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} isp_demosaic_matrix_ctrl_reg_t;
+
+/** Type of demosaic_grad_ratio register
+ *  demosaic gradient select ratio
+ */
+typedef union {
+    struct {
+        /** demosaic_grad_ratio : R/W; bitpos: [5:0]; default: 16;
+         *  this field configures demosaic gradient select ratio
+         */
+        uint32_t demosaic_grad_ratio:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} isp_demosaic_grad_ratio_reg_t;
+
+/** Type of median_matrix_ctrl register
+ *  median pix2matrix ctrl
+ */
+typedef union {
+    struct {
+        /** median_padding_data : R/W; bitpos: [7:0]; default: 0;
+         *  this field configures median matrix padding data
+         */
+        uint32_t median_padding_data:8;
+        /** median_padding_mode : R/W; bitpos: [8]; default: 0;
+         *  this bit configures the padding mode of median matrix.  0: use pixel in image to do
+         *  padding   1: use reg_padding_data to do padding
+         */
+        uint32_t median_padding_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} isp_median_matrix_ctrl_reg_t;
+
+/** Type of gamma_ctrl register
+ *  gamma control register
+ */
+typedef union {
+    struct {
+        /** gamma_update : R/W; bitpos: [0]; default: 0;
+         *  Indicates that gamma register configuration is complete
+         */
+        uint32_t gamma_update:1;
+        /** gamma_b_last_correct : R/W; bitpos: [1]; default: 1;
+         *  this bit configures enable of last b segment correcction. 0: disable, 1: enable
+         */
+        uint32_t gamma_b_last_correct:1;
+        /** gamma_g_last_correct : R/W; bitpos: [2]; default: 1;
+         *  this bit configures enable of last g segment correcction. 0: disable, 1: enable
+         */
+        uint32_t gamma_g_last_correct:1;
+        /** gamma_r_last_correct : R/W; bitpos: [3]; default: 1;
+         *  this bit configures enable of last r segment correcction. 0: disable, 1: enable
+         */
+        uint32_t gamma_r_last_correct:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} isp_gamma_ctrl_reg_t;
+
+/** Type of gamma_y1 register
+ *  point of Y-axis of r/g/b channel gamma curve register 1
+ */
+typedef union {
+    struct {
+        /** gamma_y03 : R/W; bitpos: [7:0]; default: 64;
+         *  this field configures the point 3 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y03:8;
+        /** gamma_y02 : R/W; bitpos: [15:8]; default: 48;
+         *  this field configures the point 2 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y02:8;
+        /** gamma_y01 : R/W; bitpos: [23:16]; default: 32;
+         *  this field configures the point 1 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y01:8;
+        /** gamma_y00 : R/W; bitpos: [31:24]; default: 16;
+         *  this field configures the point 0 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y00:8;
+    };
+    uint32_t val;
+} isp_gamma_y1_reg_t;
+
+/** Type of gamma_y2 register
+ *  point of Y-axis of r/g/b channel gamma curve register 2
+ */
+typedef union {
+    struct {
+        /** gamma_y07 : R/W; bitpos: [7:0]; default: 128;
+         *  this field configures the point 7 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y07:8;
+        /** gamma_y06 : R/W; bitpos: [15:8]; default: 112;
+         *  this field configures the point 6 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y06:8;
+        /** gamma_y05 : R/W; bitpos: [23:16]; default: 96;
+         *  this field configures the point 5 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y05:8;
+        /** gamma_y04 : R/W; bitpos: [31:24]; default: 80;
+         *  this field configures the point 4 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y04:8;
+    };
+    uint32_t val;
+} isp_gamma_y2_reg_t;
+
+/** Type of gamma_y3 register
+ *  point of Y-axis of r/g/b channel gamma curve register 3
+ */
+typedef union {
+    struct {
+        /** gamma_y0b : R/W; bitpos: [7:0]; default: 192;
+         *  this field configures the point 11 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y0b:8;
+        /** gamma_y0a : R/W; bitpos: [15:8]; default: 176;
+         *  this field configures the point 10 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y0a:8;
+        /** gamma_y09 : R/W; bitpos: [23:16]; default: 160;
+         *  this field configures the point 9 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y09:8;
+        /** gamma_y08 : R/W; bitpos: [31:24]; default: 144;
+         *  this field configures the point 8 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y08:8;
+    };
+    uint32_t val;
+} isp_gamma_y3_reg_t;
+
+/** Type of gamma_y4 register
+ *  point of Y-axis of r/g/b channel gamma curve register 4
+ */
+typedef union {
+    struct {
+        /** gamma_y0f : R/W; bitpos: [7:0]; default: 255;
+         *  this field configures the point 15 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y0f:8;
+        /** gamma_y0e : R/W; bitpos: [15:8]; default: 240;
+         *  this field configures the point 14 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y0e:8;
+        /** gamma_y0d : R/W; bitpos: [23:16]; default: 224;
+         *  this field configures the point 13 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y0d:8;
+        /** gamma_y0c : R/W; bitpos: [31:24]; default: 208;
+         *  this field configures the point 12 of Y-axis of r/g/b channel gamma curve
+         */
+        uint32_t gamma_y0c:8;
+    };
+    uint32_t val;
+} isp_gamma_y4_reg_t;
+
+/** Type of gamma_x1 register
+ *  point of X-axis of r/g/b channel gamma curve register 1
+ */
+typedef union {
+    struct {
+        /** gamma_r_x07 : R/W; bitpos: [2:0]; default: 4;
+         *  this field configures the point 7 of X-axis of r/g/b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_x07:3;
+        /** gamma_r_x06 : R/W; bitpos: [5:3]; default: 4;
+         *  this field configures the point 6 of X-axis of r/g/b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_x06:3;
+        /** gamma_x05 : R/W; bitpos: [8:6]; default: 4;
+         *  this field configures the point 5 of X-axis of r/g/b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_x05:3;
+        /** gamma_x04 : R/W; bitpos: [11:9]; default: 4;
+         *  this field configures the point 4 of X-axis of r/g/b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_x04:3;
+        /** gamma_x03 : R/W; bitpos: [14:12]; default: 4;
+         *  this field configures the point 3 of X-axis of r/g/b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_x03:3;
+        /** gamma_x02 : R/W; bitpos: [17:15]; default: 4;
+         *  this field configures the point 2 of X-axis of r/g/b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_x02:3;
+        /** gamma_x01 : R/W; bitpos: [20:18]; default: 4;
+         *  this field configures the point 1 of X-axis of r/g/b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_x01:3;
+        /** gamma_x00 : R/W; bitpos: [23:21]; default: 4;
+         *  this field configures the point 0 of X-axis of r/g/b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_x00:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_gamma_x1_reg_t;
+
+/** Type of gamma_x2 register
+ *  point of X-axis of r/g/b channel gamma curve register 2
+ */
+typedef union {
+    struct {
+        /** gamma_x0f : R/W; bitpos: [2:0]; default: 4;
+         *  this field configures the point 15 of X-axis of r/g/b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_x0f:3;
+        /** gamma_x0e : R/W; bitpos: [5:3]; default: 4;
+         *  this field configures the point 14 of X-axis of r/g/b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_x0e:3;
+        /** gamma_x0d : R/W; bitpos: [8:6]; default: 4;
+         *  this field configures the point 13 of X-axis of r/g/b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_x0d:3;
+        /** gamma_x0c : R/W; bitpos: [11:9]; default: 4;
+         *  this field configures the point 12 of X-axis of r/g/b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_x0c:3;
+        /** gamma_x0b : R/W; bitpos: [14:12]; default: 4;
+         *  this field configures the point 11 of X-axis of r/g/b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_x0b:3;
+        /** gamma_x0a : R/W; bitpos: [17:15]; default: 4;
+         *  this field configures the point 10 of X-axis of r/g/b channel gamma curve, it
+         *  represents the power of the distance from the previous point
+         */
+        uint32_t gamma_x0a:3;
+        /** gamma_x09 : R/W; bitpos: [20:18]; default: 4;
+         *  this field configures the point 9 of X-axis of r/g/b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_x09:3;
+        /** gamma_x08 : R/W; bitpos: [23:21]; default: 4;
+         *  this field configures the point 8 of X-axis of r/g/b channel gamma curve, it represents
+         *  the power of the distance from the previous point
+         */
+        uint32_t gamma_x08:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_gamma_x2_reg_t;
+
+/** Type of ae_ctrl register
+ *  ae control register
+ */
+typedef union {
+    struct {
+        /** ae_update : WT; bitpos: [0]; default: 0;
+         *  write 1 to this bit triggers one statistic event
+         */
+        uint32_t ae_update:1;
+        /** ae_select : R/W; bitpos: [1]; default: 0;
+         *  this field configures ae input data source, 0: data from median, 1: data from gama
+         */
+        uint32_t ae_select:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} isp_ae_ctrl_reg_t;
+
+/** Type of ae_monitor register
+ *  ae monitor control register
+ */
+typedef union {
+    struct {
+        /** ae_monitor_tl : R/W; bitpos: [7:0]; default: 0;
+         *  this field configures the lower lum threshold of ae monitor
+         */
+        uint32_t ae_monitor_tl:8;
+        /** ae_monitor_th : R/W; bitpos: [15:8]; default: 0;
+         *  this field configures the higher lum threshold of ae monitor
+         */
+        uint32_t ae_monitor_th:8;
+        /** ae_monitor_period : R/W; bitpos: [21:16]; default: 0;
+         *  this field configures ae monitor frame period
+         */
+        uint32_t ae_monitor_period:6;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} isp_ae_monitor_reg_t;
+
+/** Type of ae_bx register
+ *  ae window register in x-direction
+ */
+typedef union {
+    struct {
+        /** ae_x_bsize : R/W; bitpos: [10:0]; default: 384;
+         *  this field configures every block x size
+         */
+        uint32_t ae_x_bsize:11;
+        /** ae_x_start : R/W; bitpos: [21:11]; default: 0;
+         *  this field configures first block start x address
+         */
+        uint32_t ae_x_start:11;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} isp_ae_bx_reg_t;
+
+/** Type of ae_by register
+ *  ae window register in y-direction
+ */
+typedef union {
+    struct {
+        /** ae_y_bsize : R/W; bitpos: [10:0]; default: 216;
+         *  this field configures every block y size
+         */
+        uint32_t ae_y_bsize:11;
+        /** ae_y_start : R/W; bitpos: [21:11]; default: 0;
+         *  this field configures first block start y address
+         */
+        uint32_t ae_y_start:11;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} isp_ae_by_reg_t;
+
+/** Type of ae_winpixnum register
+ *  ae sub-window pix num register
+ */
+typedef union {
+    struct {
+        /** ae_subwin_pixnum : R/W; bitpos: [16:0]; default: 82944;
+         *  this field configures the pixel number of each sub win
+         */
+        uint32_t ae_subwin_pixnum:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_ae_winpixnum_reg_t;
+
+/** Type of ae_win_reciprocal register
+ *  reciprocal of ae sub-window pixel number
+ */
+typedef union {
+    struct {
+        /** ae_subwin_recip : R/W; bitpos: [19:0]; default: 0;
+         *  this field configures the reciprocal of each subwin_pixnum, 20bit fraction
+         */
+        uint32_t ae_subwin_recip:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} isp_ae_win_reciprocal_reg_t;
+
+/** Type of sharp_ctrl0 register
+ *  sharp control register 0
+ */
+typedef union {
+    struct {
+        /** sharp_threshold_low : R/W; bitpos: [7:0]; default: 0;
+         *  this field configures sharpen threshold for detail
+         */
+        uint32_t sharp_threshold_low:8;
+        /** sharp_threshold_high : R/W; bitpos: [15:8]; default: 0;
+         *  this field configures sharpen threshold for edge
+         */
+        uint32_t sharp_threshold_high:8;
+        /** sharp_amount_low : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures sharpen amount for detail
+         */
+        uint32_t sharp_amount_low:8;
+        /** sharp_amount_high : R/W; bitpos: [31:24]; default: 0;
+         *  this field configures sharpen amount for edge
+         */
+        uint32_t sharp_amount_high:8;
+    };
+    uint32_t val;
+} isp_sharp_ctrl0_reg_t;
+
+/** Type of sharp_filter0 register
+ *  sharp usm config register 0
+ */
+typedef union {
+    struct {
+        /** sharp_filter_coe00 : R/W; bitpos: [4:0]; default: 1;
+         *  this field configures unsharp masking(usm) filter coefficient
+         */
+        uint32_t sharp_filter_coe00:5;
+        /** sharp_filter_coe01 : R/W; bitpos: [9:5]; default: 2;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe01:5;
+        /** sharp_filter_coe02 : R/W; bitpos: [14:10]; default: 1;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe02:5;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} isp_sharp_filter0_reg_t;
+
+/** Type of sharp_filter1 register
+ *  sharp usm config register 1
+ */
+typedef union {
+    struct {
+        /** sharp_filter_coe10 : R/W; bitpos: [4:0]; default: 2;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe10:5;
+        /** sharp_filter_coe11 : R/W; bitpos: [9:5]; default: 4;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe11:5;
+        /** sharp_filter_coe12 : R/W; bitpos: [14:10]; default: 2;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe12:5;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} isp_sharp_filter1_reg_t;
+
+/** Type of sharp_filter2 register
+ *  sharp usm config register 2
+ */
+typedef union {
+    struct {
+        /** sharp_filter_coe20 : R/W; bitpos: [4:0]; default: 1;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe20:5;
+        /** sharp_filter_coe21 : R/W; bitpos: [9:5]; default: 2;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe21:5;
+        /** sharp_filter_coe22 : R/W; bitpos: [14:10]; default: 1;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe22:5;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} isp_sharp_filter2_reg_t;
+
+typedef union {
+    struct {
+        /** sharp_filter_coe0 : R/W; bitpos: [4:0]; default: 1;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe0:5;
+        /** sharp_filter_coe1 : R/W; bitpos: [9:5]; default: 2;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe1:5;
+        /** sharp_filter_coe2 : R/W; bitpos: [14:10]; default: 1;
+         *  this field configures usm filter coefficient
+         */
+        uint32_t sharp_filter_coe2:5;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} isp_sharp_filter_reg_t;
+
+/** Type of sharp_matrix_ctrl register
+ *  sharp pix2matrix ctrl
+ */
+typedef union {
+    struct {
+        /** sharp_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0;
+         *  matrix tail pixen low level threshold,  should not to large to prevent expanding to
+         *  next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and
+         *  reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th <
+         *  reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function
+         */
+        uint32_t sharp_tail_pixen_pulse_tl:8;
+        /** sharp_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0;
+         *  matrix tail pixen high level threshold, must < hnum-1, only
+         *  reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and
+         *  reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail
+         *  pulse function
+         */
+        uint32_t sharp_tail_pixen_pulse_th:8;
+        /** sharp_padding_data : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures sharp padding data
+         */
+        uint32_t sharp_padding_data:8;
+        /** sharp_padding_mode : R/W; bitpos: [24]; default: 0;
+         *  this field configures sharp padding mode
+         */
+        uint32_t sharp_padding_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} isp_sharp_matrix_ctrl_reg_t;
+
+/** Type of sharp_ctrl1 register
+ *  sharp control register 1
+ */
+typedef union {
+    struct {
+        /** sharp_gradient_max : RO; bitpos: [7:0]; default: 0;
+         *  this field configures sharp max gradient, refresh at the end of each frame end
+         */
+        uint32_t sharp_gradient_max:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} isp_sharp_ctrl1_reg_t;
+
+/** Type of dma_cntl register
+ *  isp dma source trans control register
+ */
+typedef union {
+    struct {
+        /** dma_en : WT; bitpos: [0]; default: 0;
+         *  write 1 to trigger dma to get 1 frame
+         */
+        uint32_t dma_en:1;
+        /** dma_update_reg : R/W; bitpos: [1]; default: 0;
+         *  write 1 to update reg_dma_burst_len & reg_dma_data_type
+         */
+        uint32_t dma_update_reg:1;
+        /** dma_data_type : R/W; bitpos: [7:2]; default: 42;
+         *  this field configures the idi data type for image data
+         */
+        uint32_t dma_data_type:6;
+        /** dma_burst_len : R/W; bitpos: [19:8]; default: 128;
+         *  this field configures dma burst len when data source is dma. set according to
+         *  dma_msize, it is the number of 64bits in a dma transfer
+         */
+        uint32_t dma_burst_len:12;
+        /** dma_interval : R/W; bitpos: [31:20]; default: 1;
+         *  this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ...
+         */
+        uint32_t dma_interval:12;
+    };
+    uint32_t val;
+} isp_dma_cntl_reg_t;
+
+/** Type of dma_raw_data register
+ *  isp dma source total raw number set register
+ */
+typedef union {
+    struct {
+        /** dma_raw_num_total : R/W; bitpos: [21:0]; default: 0;
+         *  this field configures the the number of 64bits in a frame
+         */
+        uint32_t dma_raw_num_total:22;
+        uint32_t reserved_22:9;
+        /** dma_raw_num_total_set : WT; bitpos: [31]; default: 0;
+         *  write 1 to update reg_dma_raw_num_total
+         */
+        uint32_t dma_raw_num_total_set:1;
+    };
+    uint32_t val;
+} isp_dma_raw_data_reg_t;
+
+/** Type of cam_cntl register
+ *  isp cam source control register
+ */
+typedef union {
+    struct {
+        /** cam_en : R/W; bitpos: [0]; default: 0;
+         *  write 1 to start receive camera data, write 0 to disable
+         */
+        uint32_t cam_en:1;
+        /** cam_update_reg : R/W; bitpos: [1]; default: 0;
+         *  write 1 to update ISP_CAM_CONF
+         */
+        uint32_t cam_update_reg:1;
+        /** cam_reset : R/W; bitpos: [2]; default: 1;
+         *  this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset
+         */
+        uint32_t cam_reset:1;
+        /** cam_clk_inv : R/W; bitpos: [3]; default: 0;
+         *  this bit configures the inversion of cam clk from pad. 0: not invert cam clk, 1:
+         *  invert cam clk
+         */
+        uint32_t cam_clk_inv:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} isp_cam_cntl_reg_t;
+
+/** Type of cam_conf register
+ *  isp cam source config register
+ */
+typedef union {
+    struct {
+        /** cam_data_order : R/W; bitpos: [0]; default: 0;
+         *  this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0],
+         *  cam_data_in[15:8]}
+         */
+        uint32_t cam_data_order:1;
+        /** cam_2byte_mode : R/W; bitpos: [1]; default: 0;
+         *  this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0:
+         *  disable, 1: enable
+         */
+        uint32_t cam_2byte_mode:1;
+        /** cam_data_type : R/W; bitpos: [7:2]; default: 42;
+         *  this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c:
+         *  RAW12
+         */
+        uint32_t cam_data_type:6;
+        /** cam_de_inv : R/W; bitpos: [8]; default: 0;
+         *  this bit configures cam data enable invert. 0: not invert, 1: invert
+         */
+        uint32_t cam_de_inv:1;
+        /** cam_hsync_inv : R/W; bitpos: [9]; default: 0;
+         *  this bit configures cam hsync invert. 0: not invert, 1: invert
+         */
+        uint32_t cam_hsync_inv:1;
+        /** cam_vsync_inv : R/W; bitpos: [10]; default: 0;
+         *  this bit configures cam vsync invert. 0: not invert, 1: invert
+         */
+        uint32_t cam_vsync_inv:1;
+        /** cam_vsync_filter_thres : R/W; bitpos: [13:11]; default: 0;
+         *  this bit configures the number of clock of vsync filter length
+         */
+        uint32_t cam_vsync_filter_thres:3;
+        /** cam_vsync_filter_en : R/W; bitpos: [14]; default: 0;
+         *  this bit configures vsync filter en
+         */
+        uint32_t cam_vsync_filter_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} isp_cam_conf_reg_t;
+
+/** Type of af_ctrl0 register
+ *  af control register 0
+ */
+typedef union {
+    struct {
+        /** af_auto_update : R/W; bitpos: [0]; default: 0;
+         *  this bit configures auto_update enable. when set to 1, will update sum and lum each
+         *  frame
+         */
+        uint32_t af_auto_update:1;
+        uint32_t reserved_1:3;
+        /** af_manual_update : WT; bitpos: [4]; default: 0;
+         *  write 1 to this bit will update the sum and lum once
+         */
+        uint32_t af_manual_update:1;
+        uint32_t reserved_5:3;
+        /** af_env_threshold : R/W; bitpos: [11:8]; default: 0;
+         *  this field configures env threshold. when both sum and lum changes larger than this
+         *  value, consider environment changes and need to trigger a new autofocus. 4Bit
+         *  fractional
+         */
+        uint32_t af_env_threshold:4;
+        uint32_t reserved_12:4;
+        /** af_env_period : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures environment changes detection period (frame). When set to 0,
+         *  disable this function
+         */
+        uint32_t af_env_period:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_af_ctrl0_reg_t;
+
+/** Type of af_ctrl1 register
+ *  af control register 1
+ */
+typedef union {
+    struct {
+        /** af_thpixnum : R/W; bitpos: [21:0]; default: 0;
+         *  this field configures pixnum used when calculating the autofocus threshold. Set to
+         *  0 to disable threshold calculation
+         */
+        uint32_t af_thpixnum:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} isp_af_ctrl1_reg_t;
+
+/** Type of af_gen_th_ctrl register
+ *  af gen threshold control register
+ */
+typedef union {
+    struct {
+        /** af_gen_threshold_min : R/W; bitpos: [15:0]; default: 128;
+         *  this field configures min threshold when use auto_threshold
+         */
+        uint32_t af_gen_threshold_min:16;
+        /** af_gen_threshold_max : R/W; bitpos: [31:16]; default: 1088;
+         *  this field configures max threshold when use auto_threshold
+         */
+        uint32_t af_gen_threshold_max:16;
+    };
+    uint32_t val;
+} isp_af_gen_th_ctrl_reg_t;
+
+/** Type of af_env_user_th_sum register
+ *  af monitor user sum threshold register
+ */
+typedef union {
+    struct {
+        /** af_env_user_threshold_sum : R/W; bitpos: [31:0]; default: 0;
+         *  this field configures user setup env detect sum threshold
+         */
+        uint32_t af_env_user_threshold_sum:32;
+    };
+    uint32_t val;
+} isp_af_env_user_th_sum_reg_t;
+
+/** Type of af_env_user_th_lum register
+ *  af monitor user lum threshold register
+ */
+typedef union {
+    struct {
+        /** af_env_user_threshold_lum : R/W; bitpos: [29:0]; default: 0;
+         *  this field configures user setup env detect lum threshold
+         */
+        uint32_t af_env_user_threshold_lum:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_af_env_user_th_lum_reg_t;
+
+/** Type of af_threshold register
+ *  af threshold register
+ */
+typedef union {
+    struct {
+        /** af_threshold : R/W; bitpos: [15:0]; default: 256;
+         *  this field configures user threshold. When set to non-zero, autofocus will use this
+         *  threshold
+         */
+        uint32_t af_threshold:16;
+        /** af_gen_threshold : RO; bitpos: [31:16]; default: 0;
+         *  this field represents the last calculated threshold
+         */
+        uint32_t af_gen_threshold:16;
+    };
+    uint32_t val;
+} isp_af_threshold_reg_t;
+
+/** Type of af_hscale_a register
+ *  h-scale of af window a register
+ */
+typedef union {
+    struct {
+        /** af_rpoint_a : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures left coordinate of focus window a, must >= 2
+         */
+        uint32_t af_rpoint_a:12;
+        uint32_t reserved_12:4;
+        /** af_lpoint_a : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures top coordinate of focus window a, must >= 2
+         */
+        uint32_t af_lpoint_a:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_hscale_a_reg_t;
+
+/** Type of af_vscale_a register
+ *  v-scale of af window a register
+ */
+typedef union {
+    struct {
+        /** af_bpoint_a : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures right coordinate of focus window a, must <= hnum-2
+         */
+        uint32_t af_bpoint_a:12;
+        uint32_t reserved_12:4;
+        /** af_tpoint_a : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures bottom coordinate of focus window a, must <= hnum-2
+         */
+        uint32_t af_tpoint_a:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_vscale_a_reg_t;
+
+/** Type of af_hscale_b register
+ *  h-scale of af window b register
+ */
+typedef union {
+    struct {
+        /** af_rpoint_b : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures left coordinate of focus window b, must >= 2
+         */
+        uint32_t af_rpoint_b:12;
+        uint32_t reserved_12:4;
+        /** af_lpoint_b : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures top coordinate of focus window b, must >= 2
+         */
+        uint32_t af_lpoint_b:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_hscale_b_reg_t;
+
+/** Type of af_vscale_b register
+ *  v-scale of af window b register
+ */
+typedef union {
+    struct {
+        /** af_bpoint_b : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures right coordinate of focus window b, must <= hnum-2
+         */
+        uint32_t af_bpoint_b:12;
+        uint32_t reserved_12:4;
+        /** af_tpoint_b : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures bottom coordinate of focus window b, must <= hnum-2
+         */
+        uint32_t af_tpoint_b:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_vscale_b_reg_t;
+
+/** Type of af_hscale_c register
+ *  v-scale of af window c register
+ */
+typedef union {
+    struct {
+        /** af_rpoint_c : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures left coordinate of focus window c, must >= 2
+         */
+        uint32_t af_rpoint_c:12;
+        uint32_t reserved_12:4;
+        /** af_lpoint_c : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures top coordinate of focus window c, must >= 2
+         */
+        uint32_t af_lpoint_c:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_hscale_c_reg_t;
+
+/** Type of af_vscale_c register
+ *  v-scale of af window c register
+ */
+typedef union {
+    struct {
+        /** af_bpoint_c : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures right coordinate of focus window c, must <= hnum-2
+         */
+        uint32_t af_bpoint_c:12;
+        uint32_t reserved_12:4;
+        /** af_tpoint_c : R/W; bitpos: [27:16]; default: 1;
+         *  this field configures bottom coordinate of focus window c, must <= hnum-2
+         */
+        uint32_t af_tpoint_c:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_vscale_c_reg_t;
+
+/** Type of awb_mode register
+ *  awb mode control register
+ */
+typedef union {
+    struct {
+        /** awb_mode : R/W; bitpos: [1:0]; default: 3;
+         *  this field configures awb algo sel. 00: none selected. 01: sel algo0. 10: sel
+         *  algo1. 11: sel both algo0 and algo1
+         */
+        uint32_t awb_mode:2;
+        uint32_t reserved_2:2;
+        /** awb_sample : R/W; bitpos: [4]; default: 0;
+         *  this bit configures awb sample location, 0:before ccm, 1:after ccm
+         */
+        uint32_t awb_sample:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} isp_awb_mode_reg_t;
+
+/** Type of awb_hscale register
+ *  h-scale of awb window
+ */
+typedef union {
+    struct {
+        /** awb_rpoint : R/W; bitpos: [11:0]; default: 1919;
+         *  this field configures awb window right coordinate
+         */
+        uint32_t awb_rpoint:12;
+        uint32_t reserved_12:4;
+        /** awb_lpoint : R/W; bitpos: [27:16]; default: 0;
+         *  this field configures awb window left coordinate
+         */
+        uint32_t awb_lpoint:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_awb_hscale_reg_t;
+
+/** Type of awb_vscale register
+ *  v-scale of awb window
+ */
+typedef union {
+    struct {
+        /** awb_bpoint : R/W; bitpos: [11:0]; default: 1079;
+         *  this field configures awb window bottom coordinate
+         */
+        uint32_t awb_bpoint:12;
+        uint32_t reserved_12:4;
+        /** awb_tpoint : R/W; bitpos: [27:16]; default: 0;
+         *  this field configures awb window top coordinate
+         */
+        uint32_t awb_tpoint:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_awb_vscale_reg_t;
+
+/** Type of awb_th_lum register
+ *  awb lum threshold register
+ */
+typedef union {
+    struct {
+        /** awb_min_lum : R/W; bitpos: [9:0]; default: 0;
+         *  this field configures lower threshold of r+g+b
+         */
+        uint32_t awb_min_lum:10;
+        uint32_t reserved_10:6;
+        /** awb_max_lum : R/W; bitpos: [25:16]; default: 765;
+         *  this field configures upper threshold of r+g+b
+         */
+        uint32_t awb_max_lum:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_awb_th_lum_reg_t;
+
+/** Type of awb_th_rg register
+ *  awb r/g threshold register
+ */
+typedef union {
+    struct {
+        /** awb_min_rg : R/W; bitpos: [9:0]; default: 0;
+         *  this field configures lower threshold of r/g, 2bit integer and 8bit fraction
+         */
+        uint32_t awb_min_rg:10;
+        uint32_t reserved_10:6;
+        /** awb_max_rg : R/W; bitpos: [25:16]; default: 1023;
+         *  this field configures upper threshold of r/g, 2bit integer and 8bit fraction
+         */
+        uint32_t awb_max_rg:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_awb_th_rg_reg_t;
+
+/** Type of awb_th_bg register
+ *  awb b/g threshold register
+ */
+typedef union {
+    struct {
+        /** awb_min_bg : R/W; bitpos: [9:0]; default: 0;
+         *  this field configures lower threshold of b/g, 2bit integer and 8bit fraction
+         */
+        uint32_t awb_min_bg:10;
+        uint32_t reserved_10:6;
+        /** awb_max_bg : R/W; bitpos: [25:16]; default: 1023;
+         *  this field configures upper threshold of b/g, 2bit integer and 8bit fraction
+         */
+        uint32_t awb_max_bg:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} isp_awb_th_bg_reg_t;
+
+/** Type of color_ctrl register
+ *  color control register
+ */
+typedef union {
+    struct {
+        /** color_saturation : R/W; bitpos: [7:0]; default: 128;
+         *  this field configures the color saturation value
+         */
+        uint32_t color_saturation:8;
+        /** color_hue : R/W; bitpos: [15:8]; default: 0;
+         *  this field configures the color hue angle
+         */
+        uint32_t color_hue:8;
+        /** color_contrast : R/W; bitpos: [23:16]; default: 128;
+         *  this field configures the color contrast value
+         */
+        uint32_t color_contrast:8;
+        /** color_brightness : R/W; bitpos: [31:24]; default: 0;
+         *  this field configures the color brightness value, signed 2's complement
+         */
+        uint32_t color_brightness:8;
+    };
+    uint32_t val;
+} isp_color_ctrl_reg_t;
+
+/** Type of blc_value register
+ *  blc black level register
+ */
+typedef union {
+    struct {
+        /** blc_r3_value : R/W; bitpos: [7:0]; default: 0;
+         *  this field configures the black level of bottom right channel of bayer img
+         */
+        uint32_t blc_r3_value:8;
+        /** blc_r2_value : R/W; bitpos: [15:8]; default: 0;
+         *  this field configures the black level of bottom left channel of bayer img
+         */
+        uint32_t blc_r2_value:8;
+        /** blc_r1_value : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures the black level of top right channel of bayer img
+         */
+        uint32_t blc_r1_value:8;
+        /** blc_r0_value : R/W; bitpos: [31:24]; default: 0;
+         *  this field configures the black level of top left channel of bayer img
+         */
+        uint32_t blc_r0_value:8;
+    };
+    uint32_t val;
+} isp_blc_value_reg_t;
+
+/** Type of blc_ctrl0 register
+ *  blc stretch control register
+ */
+typedef union {
+    struct {
+        /** blc_r3_stretch : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the stretch feature of bottom right channel. 0: stretch
+         *  disable, 1: stretch enable
+         */
+        uint32_t blc_r3_stretch:1;
+        /** blc_r2_stretch : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the stretch feature of bottom left channel. 0: stretch disable,
+         *  1: stretch enable
+         */
+        uint32_t blc_r2_stretch:1;
+        /** blc_r1_stretch : R/W; bitpos: [2]; default: 0;
+         *  this bit configures the stretch feature of top right channel. 0: stretch disable,
+         *  1: stretch enable
+         */
+        uint32_t blc_r1_stretch:1;
+        /** blc_r0_stretch : R/W; bitpos: [3]; default: 0;
+         *  this bit configures the stretch feature of top left channel. 0: stretch disable, 1:
+         *  stretch enable
+         */
+        uint32_t blc_r0_stretch:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} isp_blc_ctrl0_reg_t;
+
+/** Type of blc_ctrl1 register
+ *  blc window control register
+ */
+typedef union {
+    struct {
+        /** blc_window_top : R/W; bitpos: [10:0]; default: 0;
+         *  this field configures blc average calculation window top
+         */
+        uint32_t blc_window_top:11;
+        /** blc_window_left : R/W; bitpos: [21:11]; default: 0;
+         *  this field configures blc average calculation window left
+         */
+        uint32_t blc_window_left:11;
+        /** blc_window_vnum : R/W; bitpos: [25:22]; default: 0;
+         *  this field configures blc average calculation window vnum
+         */
+        uint32_t blc_window_vnum:4;
+        /** blc_window_hnum : R/W; bitpos: [29:26]; default: 0;
+         *  this field configures blc average calculation window hnum
+         */
+        uint32_t blc_window_hnum:4;
+        /** blc_filter_en : R/W; bitpos: [30]; default: 0;
+         *  this bit configures enable blc average input filter. 0: disable, 1: enable
+         */
+        uint32_t blc_filter_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} isp_blc_ctrl1_reg_t;
+
+/** Type of blc_ctrl2 register
+ *  blc black threshold control register
+ */
+typedef union {
+    struct {
+        /** blc_r3_th : R/W; bitpos: [7:0]; default: 0;
+         *  this field configures black threshold when get blc average of bottom right channel
+         */
+        uint32_t blc_r3_th:8;
+        /** blc_r2_th : R/W; bitpos: [15:8]; default: 0;
+         *  this field configures black threshold when get blc average of bottom left channel
+         */
+        uint32_t blc_r2_th:8;
+        /** blc_r1_th : R/W; bitpos: [23:16]; default: 0;
+         *  this field configures black threshold when get blc average of top right channel
+         */
+        uint32_t blc_r1_th:8;
+        /** blc_r0_th : R/W; bitpos: [31:24]; default: 0;
+         *  this field configures black threshold when get blc average of top left channel
+         */
+        uint32_t blc_r0_th:8;
+    };
+    uint32_t val;
+} isp_blc_ctrl2_reg_t;
+
+/** Type of hist_mode register
+ *  histogram mode control register
+ */
+typedef union {
+    struct {
+        /** hist_mode : R/W; bitpos: [2:0]; default: 4;
+         *  this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4:
+         *  RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V
+         */
+        uint32_t hist_mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} isp_hist_mode_reg_t;
+
+/** Type of hist_coeff register
+ *  histogram rgb to gray coefficients register
+ */
+typedef union {
+    struct {
+        /** hist_coeff_b : R/W; bitpos: [7:0]; default: 85;
+         *  this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r
+         *  and coeff_g and coeff_b should be 256
+         */
+        uint32_t hist_coeff_b:8;
+        /** hist_coeff_g : R/W; bitpos: [15:8]; default: 85;
+         *  this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r
+         *  and coeff_g and coeff_b should be 256
+         */
+        uint32_t hist_coeff_g:8;
+        /** hist_coeff_r : R/W; bitpos: [23:16]; default: 85;
+         *  this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r
+         *  and coeff_g and coeff_b should be 256
+         */
+        uint32_t hist_coeff_r:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_hist_coeff_reg_t;
+
+/** Type of hist_offs register
+ *  histogram window offsets register
+ */
+typedef union {
+    struct {
+        /** hist_y_offs : R/W; bitpos: [11:0]; default: 0;
+         *  this field configures y coordinate of first window
+         */
+        uint32_t hist_y_offs:12;
+        uint32_t reserved_12:4;
+        /** hist_x_offs : R/W; bitpos: [27:16]; default: 0;
+         *  this field configures x coordinate of first window
+         */
+        uint32_t hist_x_offs:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_hist_offs_reg_t;
+
+/** Type of hist_size register
+ *  histogram sub-window size register
+ */
+typedef union {
+    struct {
+        /** hist_y_size : R/W; bitpos: [8:0]; default: 32;
+         *  this field configures y direction size of subwindow
+         */
+        uint32_t hist_y_size:9;
+        uint32_t reserved_9:7;
+        /** hist_x_size : R/W; bitpos: [24:16]; default: 18;
+         *  this field configures x direction size of subwindow
+         */
+        uint32_t hist_x_size:9;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} isp_hist_size_reg_t;
+
+/** Type of hist_seg register
+ *  histogram bin control register
+ */
+typedef union {
+    struct {
+        /** hist_seg: R/W;
+         * default:
+         * 16, 32, 48, 64,
+         * 80, 96, 112, 128,
+         * 144, 160, 176, 192,
+         * 208, 224, 240
+         *  this field configures threshold of histogram
+         */
+        uint8_t hist_seg_b[4];
+    };
+    uint32_t val;
+} isp_hist_seg_reg_t;
+
+
+/** Type of hist_seg0 register
+ *  histogram bin control register 0
+ */
+typedef union {
+    struct {
+        /** hist_seg_3_4 : R/W; bitpos: [7:0]; default: 64;
+         *  this field configures threshold of histogram bin 3 and bin 4
+         */
+        uint32_t hist_seg_3_4:8;
+        /** hist_seg_2_3 : R/W; bitpos: [15:8]; default: 48;
+         *  this field configures threshold of histogram bin 2 and bin 3
+         */
+        uint32_t hist_seg_2_3:8;
+        /** hist_seg_1_2 : R/W; bitpos: [23:16]; default: 32;
+         *  this field configures threshold of histogram bin 1 and bin 2
+         */
+        uint32_t hist_seg_1_2:8;
+        /** hist_seg_0_1 : R/W; bitpos: [31:24]; default: 16;
+         *  this field configures threshold of histogram bin 0 and bin 1
+         */
+        uint32_t hist_seg_0_1:8;
+    };
+    uint32_t val;
+} isp_hist_seg0_reg_t;
+
+/** Type of hist_seg1 register
+ *  histogram bin control register 1
+ */
+typedef union {
+    struct {
+        /** hist_seg_7_8 : R/W; bitpos: [7:0]; default: 128;
+         *  this field configures threshold of histogram bin 7 and bin 8
+         */
+        uint32_t hist_seg_7_8:8;
+        /** hist_seg_6_7 : R/W; bitpos: [15:8]; default: 112;
+         *  this field configures threshold of histogram bin 6 and bin 7
+         */
+        uint32_t hist_seg_6_7:8;
+        /** hist_seg_5_6 : R/W; bitpos: [23:16]; default: 96;
+         *  this field configures threshold of histogram bin 5 and bin 6
+         */
+        uint32_t hist_seg_5_6:8;
+        /** hist_seg_4_5 : R/W; bitpos: [31:24]; default: 80;
+         *  this field configures threshold of histogram bin 4 and bin 5
+         */
+        uint32_t hist_seg_4_5:8;
+    };
+    uint32_t val;
+} isp_hist_seg1_reg_t;
+
+/** Type of hist_seg2 register
+ *  histogram bin control register 2
+ */
+typedef union {
+    struct {
+        /** hist_seg_11_12 : R/W; bitpos: [7:0]; default: 192;
+         *  this field configures threshold of histogram bin 11 and bin 12
+         */
+        uint32_t hist_seg_11_12:8;
+        /** hist_seg_10_11 : R/W; bitpos: [15:8]; default: 176;
+         *  this field configures threshold of histogram bin 10 and bin 11
+         */
+        uint32_t hist_seg_10_11:8;
+        /** hist_seg_9_10 : R/W; bitpos: [23:16]; default: 160;
+         *  this field configures threshold of histogram bin 9 and bin 10
+         */
+        uint32_t hist_seg_9_10:8;
+        /** hist_seg_8_9 : R/W; bitpos: [31:24]; default: 144;
+         *  this field configures threshold of histogram bin 8 and bin 9
+         */
+        uint32_t hist_seg_8_9:8;
+    };
+    uint32_t val;
+} isp_hist_seg2_reg_t;
+
+/** Type of hist_seg3 register
+ *  histogram bin control register 3
+ */
+typedef union {
+    struct {
+        /** hist_seg_14_15 : R/W; bitpos: [7:0]; default: 240;
+         *  this field configures threshold of histogram bin 14 and bin 15
+         */
+        uint32_t hist_seg_14_15:8;
+        /** hist_seg_13_14 : R/W; bitpos: [15:8]; default: 224;
+         *  this field configures threshold of histogram bin 13 and bin 14
+         */
+        uint32_t hist_seg_13_14:8;
+        /** hist_seg_12_13 : R/W; bitpos: [23:16]; default: 208;
+         *  this field configures threshold of histogram bin 12 and bin 13
+         */
+        uint32_t hist_seg_12_13:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_hist_seg3_reg_t;
+
+/** Type of hist_weight register
+ *  histogram sub-window weight register 0
+ */
+typedef union {
+    struct {
+        /** histogram weight : RO; bitpos: [31:0];
+         *  weight[12] default 232, others default 1
+         *  this field represents the weight of histogram subwindow, sum of all weight should be 256
+         */
+        uint8_t hist_weight_b[4];
+    };
+    uint32_t val;
+} isp_hist_weight_reg_t;
+
+/** Type of hist_weight0 register
+ *  histogram sub-window weight register 0
+ */
+typedef union {
+    struct {
+        /** hist_weight_03 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 03
+         */
+        uint32_t hist_weight_03:8;
+        /** hist_weight_02 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 02
+         */
+        uint32_t hist_weight_02:8;
+        /** hist_weight_01 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 01
+         */
+        uint32_t hist_weight_01:8;
+        /** hist_weight_00 : R/W; bitpos: [31:24]; default: 1;
+         *  this field configures weight of subwindow 00 and sum of all weight should be 256
+         */
+        uint32_t hist_weight_00:8;
+    };
+    uint32_t val;
+} isp_hist_weight0_reg_t;
+
+/** Type of hist_weight1 register
+ *  histogram sub-window weight register 1
+ */
+typedef union {
+    struct {
+        /** hist_weight_12 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 12
+         */
+        uint32_t hist_weight_12:8;
+        /** hist_weight_11 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 11
+         */
+        uint32_t hist_weight_11:8;
+        /** hist_weight_10 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 10
+         */
+        uint32_t hist_weight_10:8;
+        /** hist_weight_04 : R/W; bitpos: [31:24]; default: 1;
+         *  this field configures weight of subwindow 04
+         */
+        uint32_t hist_weight_04:8;
+    };
+    uint32_t val;
+} isp_hist_weight1_reg_t;
+
+/** Type of hist_weight2 register
+ *  histogram sub-window weight register 2
+ */
+typedef union {
+    struct {
+        /** hist_weight_21 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 21
+         */
+        uint32_t hist_weight_21:8;
+        /** hist_weight_20 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 20
+         */
+        uint32_t hist_weight_20:8;
+        /** hist_weight_14 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 04
+         */
+        uint32_t hist_weight_14:8;
+        /** hist_weight_13 : R/W; bitpos: [31:24]; default: 1;
+         *  this field configures weight of subwindow 13
+         */
+        uint32_t hist_weight_13:8;
+    };
+    uint32_t val;
+} isp_hist_weight2_reg_t;
+
+/** Type of hist_weight3 register
+ *  histogram sub-window weight register 3
+ */
+typedef union {
+    struct {
+        /** hist_weight_30 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 30
+         */
+        uint32_t hist_weight_30:8;
+        /** hist_weight_24 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 24
+         */
+        uint32_t hist_weight_24:8;
+        /** hist_weight_23 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 23
+         */
+        uint32_t hist_weight_23:8;
+        /** hist_weight_22 : R/W; bitpos: [31:24]; default: 232;
+         *  this field configures weight of subwindow 22
+         */
+        uint32_t hist_weight_22:8;
+    };
+    uint32_t val;
+} isp_hist_weight3_reg_t;
+
+/** Type of hist_weight4 register
+ *  histogram sub-window weight register 4
+ */
+typedef union {
+    struct {
+        /** hist_weight_34 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 34
+         */
+        uint32_t hist_weight_34:8;
+        /** hist_weight_33 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 33
+         */
+        uint32_t hist_weight_33:8;
+        /** hist_weight_32 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 32
+         */
+        uint32_t hist_weight_32:8;
+        /** hist_weight_31 : R/W; bitpos: [31:24]; default: 1;
+         *  this field configures weight of subwindow 31
+         */
+        uint32_t hist_weight_31:8;
+    };
+    uint32_t val;
+} isp_hist_weight4_reg_t;
+
+/** Type of hist_weight5 register
+ *  histogram sub-window weight register 5
+ */
+typedef union {
+    struct {
+        /** hist_weight_43 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 43
+         */
+        uint32_t hist_weight_43:8;
+        /** hist_weight_42 : R/W; bitpos: [15:8]; default: 1;
+         *  this field configures weight of subwindow 42
+         */
+        uint32_t hist_weight_42:8;
+        /** hist_weight_41 : R/W; bitpos: [23:16]; default: 1;
+         *  this field configures weight of subwindow 41
+         */
+        uint32_t hist_weight_41:8;
+        /** hist_weight_40 : R/W; bitpos: [31:24]; default: 1;
+         *  this field configures weight of subwindow 40
+         */
+        uint32_t hist_weight_40:8;
+    };
+    uint32_t val;
+} isp_hist_weight5_reg_t;
+
+/** Type of hist_weight6 register
+ *  histogram sub-window weight register 6
+ */
+typedef union {
+    struct {
+        /** hist_weight_44 : R/W; bitpos: [7:0]; default: 1;
+         *  this field configures weight of subwindow 44
+         */
+        uint32_t hist_weight_44:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} isp_hist_weight6_reg_t;
+
+/** Type of mem_aux_ctrl_0 register
+ *  mem aux control register 0
+ */
+typedef union {
+    struct {
+        /** header_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures the mem_aux of isp input buffer memory
+         */
+        uint32_t header_mem_aux_ctrl:14;
+        uint32_t reserved_14:2;
+        /** dpc_lut_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896;
+         *  this field represents this field configures the mem_aux of dpc lut memory
+         */
+        uint32_t dpc_lut_mem_aux_ctrl:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_mem_aux_ctrl_0_reg_t;
+
+/** Type of mem_aux_ctrl_1 register
+ *  mem aux control register 1
+ */
+typedef union {
+    struct {
+        /** lsc_lut_r_gr_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures the mem_aux of lsc r gr lut memory
+         */
+        uint32_t lsc_lut_r_gr_mem_aux_ctrl:14;
+        uint32_t reserved_14:2;
+        /** lsc_lut_gb_b_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896;
+         *  this field configures the mem_aux of lsc gb b lut memory
+         */
+        uint32_t lsc_lut_gb_b_mem_aux_ctrl:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_mem_aux_ctrl_1_reg_t;
+
+/** Type of mem_aux_ctrl_2 register
+ *  mem aux control register 2
+ */
+typedef union {
+    struct {
+        /** bf_matrix_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures the mem_aux of bf line buffer memory
+         */
+        uint32_t bf_matrix_mem_aux_ctrl:14;
+        uint32_t reserved_14:2;
+        /** dpc_matrix_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896;
+         *  this field configures the mem_aux of dpc line buffer memory
+         */
+        uint32_t dpc_matrix_mem_aux_ctrl:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_mem_aux_ctrl_2_reg_t;
+
+/** Type of mem_aux_ctrl_3 register
+ *  mem aux control register 3
+ */
+typedef union {
+    struct {
+        /** sharp_matrix_y_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures the mem_aux of sharp y line buffer memory
+         */
+        uint32_t sharp_matrix_y_mem_aux_ctrl:14;
+        uint32_t reserved_14:2;
+        /** demosaic_matrix_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896;
+         *  this field configures the mem_aux of demosaic line buffer memory
+         */
+        uint32_t demosaic_matrix_mem_aux_ctrl:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_mem_aux_ctrl_3_reg_t;
+
+/** Type of mem_aux_ctrl_4 register
+ *  mem aux control register 4
+ */
+typedef union {
+    struct {
+        /** sharp_matrix_uv_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures the mem_aux of sharp uv line buffer memory
+         */
+        uint32_t sharp_matrix_uv_mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} isp_mem_aux_ctrl_4_reg_t;
+
+/** Type of yuv_format register
+ *  yuv format control register
+ */
+typedef union {
+    struct {
+        /** yuv_mode : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709
+         */
+        uint32_t yuv_mode:1;
+        /** yuv_range : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the yuv range. 0: full range, 1: limit range
+         */
+        uint32_t yuv_range:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} isp_yuv_format_reg_t;
+
+/** Type of rdn_eco_low register
+ *  rdn eco all low register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rdn_eco_low
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} isp_rdn_eco_low_reg_t;
+
+/** Type of rdn_eco_high register
+ *  rdn eco all high register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rdn_eco_high
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} isp_rdn_eco_high_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of dpc_deadpix_cnt register
+ *  DPC dead-pix number register
+ */
+typedef union {
+    struct {
+        /** dpc_deadpix_cnt : RO; bitpos: [9:0]; default: 0;
+         *  this field represents the dead pixel count
+         */
+        uint32_t dpc_deadpix_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} isp_dpc_deadpix_cnt_reg_t;
+
+/** Type of lut_rdata register
+ *  LUT read data register
+ */
+typedef union {
+    struct {
+        /** lut_rdata : RO; bitpos: [31:0]; default: 0;
+         *  this field represents the read data of lut. read ISP_LUT_RDATA after write
+         *  ISP_LUT_CMD register
+         */
+        uint32_t lut_rdata:32;
+    };
+    uint32_t val;
+} isp_lut_rdata_reg_t;
+
+/** Type of ae_block_mean register
+ *  ae statistic result
+ */
+typedef union {
+    struct {
+        /** ae_lum : RO; bitpos: [31:0]; default: 0;
+         *  this field represents the result of AE block
+         */
+        uint8_t ae_b_mean[4];
+    };
+    uint32_t val;
+} isp_ae_block_mean_reg_t;
+
+/** Type of ae_block_mean_0 register
+ *  ae statistic result register 0
+ */
+typedef union {
+    struct {
+        /** ae_b03_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block03 Y mean data
+         */
+        uint32_t ae_b03_mean:8;
+        /** ae_b02_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block02 Y mean data
+         */
+        uint32_t ae_b02_mean:8;
+        /** ae_b01_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block01 Y mean data
+         */
+        uint32_t ae_b01_mean:8;
+        /** ae_b00_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block00 Y mean data
+         */
+        uint32_t ae_b00_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_0_reg_t;
+
+/** Type of ae_block_mean_1 register
+ *  ae statistic result register 1
+ */
+typedef union {
+    struct {
+        /** ae_b12_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block12 Y mean data
+         */
+        uint32_t ae_b12_mean:8;
+        /** ae_b11_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block11 Y mean data
+         */
+        uint32_t ae_b11_mean:8;
+        /** ae_b10_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block10 Y mean data
+         */
+        uint32_t ae_b10_mean:8;
+        /** ae_b04_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block04 Y mean data
+         */
+        uint32_t ae_b04_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_1_reg_t;
+
+/** Type of ae_block_mean_2 register
+ *  ae statistic result register 2
+ */
+typedef union {
+    struct {
+        /** ae_b21_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block21 Y mean data
+         */
+        uint32_t ae_b21_mean:8;
+        /** ae_b20_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block20 Y mean data
+         */
+        uint32_t ae_b20_mean:8;
+        /** ae_b14_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block14 Y mean data
+         */
+        uint32_t ae_b14_mean:8;
+        /** ae_b13_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block13 Y mean data
+         */
+        uint32_t ae_b13_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_2_reg_t;
+
+/** Type of ae_block_mean_3 register
+ *  ae statistic result register 3
+ */
+typedef union {
+    struct {
+        /** ae_b30_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block30 Y mean data
+         */
+        uint32_t ae_b30_mean:8;
+        /** ae_b24_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block24 Y mean data
+         */
+        uint32_t ae_b24_mean:8;
+        /** ae_b23_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block23 Y mean data
+         */
+        uint32_t ae_b23_mean:8;
+        /** ae_b22_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block22 Y mean data
+         */
+        uint32_t ae_b22_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_3_reg_t;
+
+/** Type of ae_block_mean_4 register
+ *  ae statistic result register 4
+ */
+typedef union {
+    struct {
+        /** ae_b34_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block34 Y mean data
+         */
+        uint32_t ae_b34_mean:8;
+        /** ae_b33_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block33 Y mean data
+         */
+        uint32_t ae_b33_mean:8;
+        /** ae_b32_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block32 Y mean data
+         */
+        uint32_t ae_b32_mean:8;
+        /** ae_b31_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block31 Y mean data
+         */
+        uint32_t ae_b31_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_4_reg_t;
+
+/** Type of ae_block_mean_5 register
+ *  ae statistic result register 5
+ */
+typedef union {
+    struct {
+        /** ae_b43_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field configures block43 Y mean data
+         */
+        uint32_t ae_b43_mean:8;
+        /** ae_b42_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field configures block42 Y mean data
+         */
+        uint32_t ae_b42_mean:8;
+        /** ae_b41_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field configures block41 Y mean data
+         */
+        uint32_t ae_b41_mean:8;
+        /** ae_b40_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block40 Y mean data
+         */
+        uint32_t ae_b40_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_5_reg_t;
+
+/** Type of ae_block_mean_6 register
+ *  ae statistic result register 6
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** ae_b44_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field configures block44 Y mean data
+         */
+        uint32_t ae_b44_mean:8;
+    };
+    uint32_t val;
+} isp_ae_block_mean_6_reg_t;
+/** Type of af_sum_a register
+ *  result of sum of af window a
+ */
+typedef union {
+    struct {
+        /** af_suma : RO; bitpos: [29:0]; default: 0;
+         *  this field represents the result of accumulation of pix grad of focus window a
+         */
+        uint32_t af_suma:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_af_sum_a_reg_t;
+
+/** Type of af_sum_b register
+ *  result of sum of af window b
+ */
+typedef union {
+    struct {
+        /** af_sumb : RO; bitpos: [29:0]; default: 0;
+         *  this field represents the result of accumulation of pix grad of focus window b
+         */
+        uint32_t af_sumb:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_af_sum_b_reg_t;
+
+/** Type of af_sum_c register
+ *  result of sum of af window c
+ */
+typedef union {
+    struct {
+        /** af_sumc : RO; bitpos: [29:0]; default: 0;
+         *  this field represents the result of accumulation of pix grad of focus window c
+         */
+        uint32_t af_sumc:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} isp_af_sum_c_reg_t;
+
+/** Type of af_lum_a register
+ *  result of lum of af window a
+ */
+typedef union {
+    struct {
+        /** af_luma : RO; bitpos: [27:0]; default: 0;
+         *  this field represents the result of accumulation of pix light of focus window a
+         */
+        uint32_t af_luma:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_lum_a_reg_t;
+
+/** Type of af_lum_b register
+ *  result of lum of af window b
+ */
+typedef union {
+    struct {
+        /** af_lumb : RO; bitpos: [27:0]; default: 0;
+         *  this field represents the result of accumulation of pix light of focus window b
+         */
+        uint32_t af_lumb:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_lum_b_reg_t;
+
+/** Type of af_lum_c register
+ *  result of lum of af window c
+ */
+typedef union {
+    struct {
+        /** af_lumc : RO; bitpos: [27:0]; default: 0;
+         *  this field represents the result of accumulation of pix light of focus window c
+         */
+        uint32_t af_lumc:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} isp_af_lum_c_reg_t;
+
+/** Type of awb0_white_cnt register
+ *  result of awb white point number
+ */
+typedef union {
+    struct {
+        /** awb0_white_cnt : RO; bitpos: [23:0]; default: 0;
+         *  this field configures number of white point detected of algo0
+         */
+        uint32_t awb0_white_cnt:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} isp_awb0_white_cnt_reg_t;
+
+/** Type of awb0_acc_r register
+ *  result of accumulate of r channel of all white points
+ */
+typedef union {
+    struct {
+        /** awb0_acc_r : RO; bitpos: [31:0]; default: 0;
+         *  this field represents accumulate of channel r of all white point of algo0
+         */
+        uint32_t awb0_acc_r:32;
+    };
+    uint32_t val;
+} isp_awb0_acc_r_reg_t;
+
+/** Type of awb0_acc_g register
+ *  result of accumulate of g channel of all white points
+ */
+typedef union {
+    struct {
+        /** awb0_acc_g : RO; bitpos: [31:0]; default: 0;
+         *  this field represents accumulate of channel g of all white point of algo0
+         */
+        uint32_t awb0_acc_g:32;
+    };
+    uint32_t val;
+} isp_awb0_acc_g_reg_t;
+
+/** Type of awb0_acc_b register
+ *  result of accumulate of b channel of all white points
+ */
+typedef union {
+    struct {
+        /** awb0_acc_b : RO; bitpos: [31:0]; default: 0;
+         *  this field represents accumulate of channel b of all white point of algo0
+         */
+        uint32_t awb0_acc_b:32;
+    };
+    uint32_t val;
+} isp_awb0_acc_b_reg_t;
+
+/** Type of blc_mean register
+ *  results of the average of black window
+ */
+typedef union {
+    struct {
+        /** blc_r3_mean : RO; bitpos: [7:0]; default: 0;
+         *  this field represents the average black value of bottom right channel
+         */
+        uint32_t blc_r3_mean:8;
+        /** blc_r2_mean : RO; bitpos: [15:8]; default: 0;
+         *  this field represents the average black value of bottom left channel
+         */
+        uint32_t blc_r2_mean:8;
+        /** blc_r1_mean : RO; bitpos: [23:16]; default: 0;
+         *  this field represents the average black value of top right channel
+         */
+        uint32_t blc_r1_mean:8;
+        /** blc_r0_mean : RO; bitpos: [31:24]; default: 0;
+         *  this field represents the average black value of top left channel
+         */
+        uint32_t blc_r0_mean:8;
+    };
+    uint32_t val;
+} isp_blc_mean_reg_t;
+
+/** Type of hist_bin register
+ *  result of histogram bin n
+ */
+typedef union {
+    struct {
+        /** hist_bin_n : RO; bitpos: [16:0]; default: 0;
+         *  this field represents result of histogram bin n
+         */
+        uint32_t hist_bin_n:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} isp_hist_binn_reg_t;
+
+/** Type of rdn_eco_cs register
+ *  rdn eco cs register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  rdn_eco_en
+         */
+        uint32_t rdn_eco_en:1;
+        /** rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  rdn_eco_result
+         */
+        uint32_t rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} isp_rdn_eco_cs_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  raw interrupt register
+ */
+typedef union {
+    struct {
+        /** isp_data_type_err_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  the raw interrupt status of input data type error. isp only support RGB bayer data
+         *  type, other type will report type_err_int
+         */
+        uint32_t isp_data_type_err_int_raw:1;
+        /** isp_async_fifo_ovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  the raw interrupt status of isp input fifo overflow
+         */
+        uint32_t isp_async_fifo_ovf_int_raw:1;
+        /** isp_buf_full_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  the raw interrupt status of isp input buffer full
+         */
+        uint32_t isp_buf_full_int_raw:1;
+        /** isp_hvnum_setting_err_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  the raw interrupt status of hnum and vnum setting format error
+         */
+        uint32_t isp_hvnum_setting_err_int_raw:1;
+        /** isp_data_type_setting_err_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  the raw interrupt status of setting invalid reg_data_type
+         */
+        uint32_t isp_data_type_setting_err_int_raw:1;
+        /** isp_mipi_hnum_unmatch_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  the raw interrupt status of hnum setting unmatch with mipi input
+         */
+        uint32_t isp_mipi_hnum_unmatch_int_raw:1;
+        /** dpc_check_done_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  the raw interrupt status of dpc check done
+         */
+        uint32_t dpc_check_done_int_raw:1;
+        /** gamma_xcoord_err_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  the raw interrupt status of gamma setting error. it report the sum of the lengths
+         *  represented by reg_gamma_x00~x0F isn't equal to 256
+         */
+        uint32_t gamma_xcoord_err_int_raw:1;
+        /** ae_monitor_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  the raw interrupt status of ae monitor
+         */
+        uint32_t ae_monitor_int_raw:1;
+        /** ae_frame_done_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  the raw interrupt status of ae.
+         */
+        uint32_t ae_frame_done_int_raw:1;
+        /** af_fdone_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  the raw interrupt status of af statistic. when auto_update enable, each frame done
+         *  will send one int pulse when manual_update, each time when write 1 to
+         *  reg_manual_update will send a int pulse when next frame done
+         */
+        uint32_t af_fdone_int_raw:1;
+        /** af_env_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  the raw interrupt status of af monitor. send a int pulse when env_det function
+         *  enabled and environment changes detected
+         */
+        uint32_t af_env_int_raw:1;
+        /** awb_fdone_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  the raw interrupt status of awb. send a int pulse when statistic of one awb frame
+         *  done
+         */
+        uint32_t awb_fdone_int_raw:1;
+        /** hist_fdone_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  the raw interrupt status of histogram. send a int pulse when statistic of one frame
+         *  histogram done
+         */
+        uint32_t hist_fdone_int_raw:1;
+        /** frame_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  the raw interrupt status of isp frame end
+         */
+        uint32_t frame_int_raw:1;
+        /** blc_frame_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  the raw interrupt status of blc frame done
+         */
+        uint32_t blc_frame_int_raw:1;
+        /** lsc_frame_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
+         *  the raw interrupt status of lsc frame done
+         */
+        uint32_t lsc_frame_int_raw:1;
+        /** dpc_frame_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
+         *  the raw interrupt status of dpc frame done
+         */
+        uint32_t dpc_frame_int_raw:1;
+        /** bf_frame_int_raw : R/SS/WTC; bitpos: [18]; default: 0;
+         *  the raw interrupt status of bf frame done
+         */
+        uint32_t bf_frame_int_raw:1;
+        /** demosaic_frame_int_raw : R/SS/WTC; bitpos: [19]; default: 0;
+         *  the raw interrupt status of demosaic frame done
+         */
+        uint32_t demosaic_frame_int_raw:1;
+        /** median_frame_int_raw : R/SS/WTC; bitpos: [20]; default: 0;
+         *  the raw interrupt status of median frame done
+         */
+        uint32_t median_frame_int_raw:1;
+        /** ccm_frame_int_raw : R/SS/WTC; bitpos: [21]; default: 0;
+         *  the raw interrupt status of ccm frame done
+         */
+        uint32_t ccm_frame_int_raw:1;
+        /** gamma_frame_int_raw : R/SS/WTC; bitpos: [22]; default: 0;
+         *  the raw interrupt status of gamma frame done
+         */
+        uint32_t gamma_frame_int_raw:1;
+        /** rgb2yuv_frame_int_raw : R/SS/WTC; bitpos: [23]; default: 0;
+         *  the raw interrupt status of rgb2yuv frame done
+         */
+        uint32_t rgb2yuv_frame_int_raw:1;
+        /** sharp_frame_int_raw : R/SS/WTC; bitpos: [24]; default: 0;
+         *  the raw interrupt status of sharp frame done
+         */
+        uint32_t sharp_frame_int_raw:1;
+        /** color_frame_int_raw : R/SS/WTC; bitpos: [25]; default: 0;
+         *  the raw interrupt status of color frame done
+         */
+        uint32_t color_frame_int_raw:1;
+        /** yuv2rgb_frame_int_raw : R/SS/WTC; bitpos: [26]; default: 0;
+         *  the raw interrupt status of yuv2rgb frame done
+         */
+        uint32_t yuv2rgb_frame_int_raw:1;
+        /** tail_idi_frame_int_raw : R/SS/WTC; bitpos: [27]; default: 0;
+         *  the raw interrupt status of isp_tail idi frame_end
+         */
+        uint32_t tail_idi_frame_int_raw:1;
+        /** header_idi_frame_int_raw : R/SS/WTC; bitpos: [28]; default: 0;
+         *  the raw interrupt status of real input frame end of isp_input
+         */
+        uint32_t header_idi_frame_int_raw:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} isp_int_raw_reg_t;
+
+/** Type of int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** isp_data_type_err_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of input data type error
+         */
+        uint32_t isp_data_type_err_int_st:1;
+        /** isp_async_fifo_ovf_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of isp input fifo overflow
+         */
+        uint32_t isp_async_fifo_ovf_int_st:1;
+        /** isp_buf_full_int_st : RO; bitpos: [2]; default: 0;
+         *  the masked interrupt status of isp input buffer full
+         */
+        uint32_t isp_buf_full_int_st:1;
+        /** isp_hvnum_setting_err_int_st : RO; bitpos: [3]; default: 0;
+         *  the masked interrupt status of hnum and vnum setting format error
+         */
+        uint32_t isp_hvnum_setting_err_int_st:1;
+        /** isp_data_type_setting_err_int_st : RO; bitpos: [4]; default: 0;
+         *  the masked interrupt status of setting invalid reg_data_type
+         */
+        uint32_t isp_data_type_setting_err_int_st:1;
+        /** isp_mipi_hnum_unmatch_int_st : RO; bitpos: [5]; default: 0;
+         *  the masked interrupt status of hnum setting unmatch with mipi input
+         */
+        uint32_t isp_mipi_hnum_unmatch_int_st:1;
+        /** dpc_check_done_int_st : RO; bitpos: [6]; default: 0;
+         *  the masked interrupt status of dpc check done
+         */
+        uint32_t dpc_check_done_int_st:1;
+        /** gamma_xcoord_err_int_st : RO; bitpos: [7]; default: 0;
+         *  the masked interrupt status of gamma setting error
+         */
+        uint32_t gamma_xcoord_err_int_st:1;
+        /** ae_monitor_int_st : RO; bitpos: [8]; default: 0;
+         *  the masked interrupt status of ae monitor
+         */
+        uint32_t ae_monitor_int_st:1;
+        /** ae_frame_done_int_st : RO; bitpos: [9]; default: 0;
+         *  the masked interrupt status of ae
+         */
+        uint32_t ae_frame_done_int_st:1;
+        /** af_fdone_int_st : RO; bitpos: [10]; default: 0;
+         *  the masked interrupt status of af statistic
+         */
+        uint32_t af_fdone_int_st:1;
+        /** af_env_int_st : RO; bitpos: [11]; default: 0;
+         *  the masked interrupt status of af monitor
+         */
+        uint32_t af_env_int_st:1;
+        /** awb_fdone_int_st : RO; bitpos: [12]; default: 0;
+         *  the masked interrupt status of awb
+         */
+        uint32_t awb_fdone_int_st:1;
+        /** hist_fdone_int_st : RO; bitpos: [13]; default: 0;
+         *  the masked interrupt status of histogram
+         */
+        uint32_t hist_fdone_int_st:1;
+        /** frame_int_st : RO; bitpos: [14]; default: 0;
+         *  the masked interrupt status of isp frame end
+         */
+        uint32_t frame_int_st:1;
+        /** blc_frame_int_st : RO; bitpos: [15]; default: 0;
+         *  the masked interrupt status of blc frame done
+         */
+        uint32_t blc_frame_int_st:1;
+        /** lsc_frame_int_st : RO; bitpos: [16]; default: 0;
+         *  the masked interrupt status of lsc frame done
+         */
+        uint32_t lsc_frame_int_st:1;
+        /** dpc_frame_int_st : RO; bitpos: [17]; default: 0;
+         *  the masked interrupt status of dpc frame done
+         */
+        uint32_t dpc_frame_int_st:1;
+        /** bf_frame_int_st : RO; bitpos: [18]; default: 0;
+         *  the masked interrupt status of bf frame done
+         */
+        uint32_t bf_frame_int_st:1;
+        /** demosaic_frame_int_st : RO; bitpos: [19]; default: 0;
+         *  the masked interrupt status of demosaic frame done
+         */
+        uint32_t demosaic_frame_int_st:1;
+        /** median_frame_int_st : RO; bitpos: [20]; default: 0;
+         *  the masked interrupt status of median frame done
+         */
+        uint32_t median_frame_int_st:1;
+        /** ccm_frame_int_st : RO; bitpos: [21]; default: 0;
+         *  the masked interrupt status of ccm frame done
+         */
+        uint32_t ccm_frame_int_st:1;
+        /** gamma_frame_int_st : RO; bitpos: [22]; default: 0;
+         *  the masked interrupt status of gamma frame done
+         */
+        uint32_t gamma_frame_int_st:1;
+        /** rgb2yuv_frame_int_st : RO; bitpos: [23]; default: 0;
+         *  the masked interrupt status of rgb2yuv frame done
+         */
+        uint32_t rgb2yuv_frame_int_st:1;
+        /** sharp_frame_int_st : RO; bitpos: [24]; default: 0;
+         *  the masked interrupt status of sharp frame done
+         */
+        uint32_t sharp_frame_int_st:1;
+        /** color_frame_int_st : RO; bitpos: [25]; default: 0;
+         *  the masked interrupt status of color frame done
+         */
+        uint32_t color_frame_int_st:1;
+        /** yuv2rgb_frame_int_st : RO; bitpos: [26]; default: 0;
+         *  the masked interrupt status of yuv2rgb frame done
+         */
+        uint32_t yuv2rgb_frame_int_st:1;
+        /** tail_idi_frame_int_st : RO; bitpos: [27]; default: 0;
+         *  the masked interrupt status of isp_tail idi frame_end
+         */
+        uint32_t tail_idi_frame_int_st:1;
+        /** header_idi_frame_int_st : RO; bitpos: [28]; default: 0;
+         *  the masked interrupt status of real input frame end of isp_input
+         */
+        uint32_t header_idi_frame_int_st:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} isp_int_st_reg_t;
+
+/** Type of int_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** isp_data_type_err_int_ena : R/W; bitpos: [0]; default: 1;
+         *  write 1 to enable input data type error
+         */
+        uint32_t isp_data_type_err_int_ena:1;
+        /** isp_async_fifo_ovf_int_ena : R/W; bitpos: [1]; default: 1;
+         *  write 1 to enable isp input fifo overflow
+         */
+        uint32_t isp_async_fifo_ovf_int_ena:1;
+        /** isp_buf_full_int_ena : R/W; bitpos: [2]; default: 0;
+         *  write 1 to enable isp input buffer full
+         */
+        uint32_t isp_buf_full_int_ena:1;
+        /** isp_hvnum_setting_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  write 1 to enable hnum and vnum setting format error
+         */
+        uint32_t isp_hvnum_setting_err_int_ena:1;
+        /** isp_data_type_setting_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  write 1 to enable setting invalid reg_data_type
+         */
+        uint32_t isp_data_type_setting_err_int_ena:1;
+        /** isp_mipi_hnum_unmatch_int_ena : R/W; bitpos: [5]; default: 0;
+         *  write 1 to enable hnum setting unmatch with mipi input
+         */
+        uint32_t isp_mipi_hnum_unmatch_int_ena:1;
+        /** dpc_check_done_int_ena : R/W; bitpos: [6]; default: 1;
+         *  write 1 to enable dpc check done
+         */
+        uint32_t dpc_check_done_int_ena:1;
+        /** gamma_xcoord_err_int_ena : R/W; bitpos: [7]; default: 1;
+         *  write 1 to enable gamma setting error
+         */
+        uint32_t gamma_xcoord_err_int_ena:1;
+        /** ae_monitor_int_ena : R/W; bitpos: [8]; default: 0;
+         *  write 1 to enable ae monitor
+         */
+        uint32_t ae_monitor_int_ena:1;
+        /** ae_frame_done_int_ena : R/W; bitpos: [9]; default: 0;
+         *  write 1 to enable ae
+         */
+        uint32_t ae_frame_done_int_ena:1;
+        /** af_fdone_int_ena : R/W; bitpos: [10]; default: 0;
+         *  write 1 to enable af statistic
+         */
+        uint32_t af_fdone_int_ena:1;
+        /** af_env_int_ena : R/W; bitpos: [11]; default: 0;
+         *  write 1 to enable af monitor
+         */
+        uint32_t af_env_int_ena:1;
+        /** awb_fdone_int_ena : R/W; bitpos: [12]; default: 0;
+         *  write 1 to enable awb
+         */
+        uint32_t awb_fdone_int_ena:1;
+        /** hist_fdone_int_ena : R/W; bitpos: [13]; default: 0;
+         *  write 1 to enable histogram
+         */
+        uint32_t hist_fdone_int_ena:1;
+        /** frame_int_ena : R/W; bitpos: [14]; default: 0;
+         *  write 1 to enable isp frame end
+         */
+        uint32_t frame_int_ena:1;
+        /** blc_frame_int_ena : R/W; bitpos: [15]; default: 0;
+         *  write 1 to enable blc frame done
+         */
+        uint32_t blc_frame_int_ena:1;
+        /** lsc_frame_int_ena : R/W; bitpos: [16]; default: 0;
+         *  write 1 to enable lsc frame done
+         */
+        uint32_t lsc_frame_int_ena:1;
+        /** dpc_frame_int_ena : R/W; bitpos: [17]; default: 0;
+         *  write 1 to enable dpc frame done
+         */
+        uint32_t dpc_frame_int_ena:1;
+        /** bf_frame_int_ena : R/W; bitpos: [18]; default: 0;
+         *  write 1 to enable bf frame done
+         */
+        uint32_t bf_frame_int_ena:1;
+        /** demosaic_frame_int_ena : R/W; bitpos: [19]; default: 0;
+         *  write 1 to enable demosaic frame done
+         */
+        uint32_t demosaic_frame_int_ena:1;
+        /** median_frame_int_ena : R/W; bitpos: [20]; default: 0;
+         *  write 1 to enable median frame done
+         */
+        uint32_t median_frame_int_ena:1;
+        /** ccm_frame_int_ena : R/W; bitpos: [21]; default: 0;
+         *  write 1 to enable ccm frame done
+         */
+        uint32_t ccm_frame_int_ena:1;
+        /** gamma_frame_int_ena : R/W; bitpos: [22]; default: 0;
+         *  write 1 to enable gamma frame done
+         */
+        uint32_t gamma_frame_int_ena:1;
+        /** rgb2yuv_frame_int_ena : R/W; bitpos: [23]; default: 0;
+         *  write 1 to enable rgb2yuv frame done
+         */
+        uint32_t rgb2yuv_frame_int_ena:1;
+        /** sharp_frame_int_ena : R/W; bitpos: [24]; default: 0;
+         *  write 1 to enable sharp frame done
+         */
+        uint32_t sharp_frame_int_ena:1;
+        /** color_frame_int_ena : R/W; bitpos: [25]; default: 0;
+         *  write 1 to enable color frame done
+         */
+        uint32_t color_frame_int_ena:1;
+        /** yuv2rgb_frame_int_ena : R/W; bitpos: [26]; default: 0;
+         *  write 1 to enable yuv2rgb frame done
+         */
+        uint32_t yuv2rgb_frame_int_ena:1;
+        /** tail_idi_frame_int_ena : R/W; bitpos: [27]; default: 0;
+         *  write 1 to enable isp_tail idi frame_end
+         */
+        uint32_t tail_idi_frame_int_ena:1;
+        /** header_idi_frame_int_ena : R/W; bitpos: [28]; default: 0;
+         *  write 1 to enable real input frame end of isp_input
+         */
+        uint32_t header_idi_frame_int_ena:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} isp_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** isp_data_type_err_int_clr : WT; bitpos: [0]; default: 0;
+         *  write 1 to clear input data type error
+         */
+        uint32_t isp_data_type_err_int_clr:1;
+        /** isp_async_fifo_ovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  write 1 to clear isp input fifo overflow
+         */
+        uint32_t isp_async_fifo_ovf_int_clr:1;
+        /** isp_buf_full_int_clr : WT; bitpos: [2]; default: 0;
+         *  write 1 to clear isp input buffer full
+         */
+        uint32_t isp_buf_full_int_clr:1;
+        /** isp_hvnum_setting_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  write 1 to clear hnum and vnum setting format error
+         */
+        uint32_t isp_hvnum_setting_err_int_clr:1;
+        /** isp_data_type_setting_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  write 1 to clear setting invalid reg_data_type
+         */
+        uint32_t isp_data_type_setting_err_int_clr:1;
+        /** isp_mipi_hnum_unmatch_int_clr : WT; bitpos: [5]; default: 0;
+         *  write 1 to clear hnum setting unmatch with mipi input
+         */
+        uint32_t isp_mipi_hnum_unmatch_int_clr:1;
+        /** dpc_check_done_int_clr : WT; bitpos: [6]; default: 0;
+         *  write 1 to clear dpc check done
+         */
+        uint32_t dpc_check_done_int_clr:1;
+        /** gamma_xcoord_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  write 1 to clear gamma setting error
+         */
+        uint32_t gamma_xcoord_err_int_clr:1;
+        /** ae_monitor_int_clr : WT; bitpos: [8]; default: 0;
+         *  write 1 to clear ae monitor
+         */
+        uint32_t ae_monitor_int_clr:1;
+        /** ae_frame_done_int_clr : WT; bitpos: [9]; default: 0;
+         *  write 1 to clear ae
+         */
+        uint32_t ae_frame_done_int_clr:1;
+        /** af_fdone_int_clr : WT; bitpos: [10]; default: 0;
+         *  write 1 to clear af statistic
+         */
+        uint32_t af_fdone_int_clr:1;
+        /** af_env_int_clr : WT; bitpos: [11]; default: 0;
+         *  write 1 to clear af monitor
+         */
+        uint32_t af_env_int_clr:1;
+        /** awb_fdone_int_clr : WT; bitpos: [12]; default: 0;
+         *  write 1 to clear awb
+         */
+        uint32_t awb_fdone_int_clr:1;
+        /** hist_fdone_int_clr : WT; bitpos: [13]; default: 0;
+         *  write 1 to clear histogram
+         */
+        uint32_t hist_fdone_int_clr:1;
+        /** frame_int_clr : WT; bitpos: [14]; default: 0;
+         *  write 1 to clear isp frame end
+         */
+        uint32_t frame_int_clr:1;
+        /** blc_frame_int_clr : WT; bitpos: [15]; default: 0;
+         *  write 1 to clear blc frame done
+         */
+        uint32_t blc_frame_int_clr:1;
+        /** lsc_frame_int_clr : WT; bitpos: [16]; default: 0;
+         *  write 1 to clear lsc frame done
+         */
+        uint32_t lsc_frame_int_clr:1;
+        /** dpc_frame_int_clr : WT; bitpos: [17]; default: 0;
+         *  write 1 to clear dpc frame done
+         */
+        uint32_t dpc_frame_int_clr:1;
+        /** bf_frame_int_clr : WT; bitpos: [18]; default: 0;
+         *  write 1 to clear bf frame done
+         */
+        uint32_t bf_frame_int_clr:1;
+        /** demosaic_frame_int_clr : WT; bitpos: [19]; default: 0;
+         *  write 1 to clear demosaic frame done
+         */
+        uint32_t demosaic_frame_int_clr:1;
+        /** median_frame_int_clr : WT; bitpos: [20]; default: 0;
+         *  write 1 to clear median frame done
+         */
+        uint32_t median_frame_int_clr:1;
+        /** ccm_frame_int_clr : WT; bitpos: [21]; default: 0;
+         *  write 1 to clear ccm frame done
+         */
+        uint32_t ccm_frame_int_clr:1;
+        /** gamma_frame_int_clr : WT; bitpos: [22]; default: 0;
+         *  write 1 to clear gamma frame done
+         */
+        uint32_t gamma_frame_int_clr:1;
+        /** rgb2yuv_frame_int_clr : WT; bitpos: [23]; default: 0;
+         *  write 1 to clear rgb2yuv frame done
+         */
+        uint32_t rgb2yuv_frame_int_clr:1;
+        /** sharp_frame_int_clr : WT; bitpos: [24]; default: 0;
+         *  write 1 to clear sharp frame done
+         */
+        uint32_t sharp_frame_int_clr:1;
+        /** color_frame_int_clr : WT; bitpos: [25]; default: 0;
+         *  write 1 to clear color frame done
+         */
+        uint32_t color_frame_int_clr:1;
+        /** yuv2rgb_frame_int_clr : WT; bitpos: [26]; default: 0;
+         *  write 1 to clear yuv2rgb frame done
+         */
+        uint32_t yuv2rgb_frame_int_clr:1;
+        /** tail_idi_frame_int_clr : WT; bitpos: [27]; default: 0;
+         *  write 1 to clear isp_tail idi frame_end
+         */
+        uint32_t tail_idi_frame_int_clr:1;
+        /** header_idi_frame_int_clr : WT; bitpos: [28]; default: 0;
+         *  write 1 to clear real input frame end of isp_input
+         */
+        uint32_t header_idi_frame_int_clr:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} isp_int_clr_reg_t;
+
+typedef struct {
+    volatile isp_gamma_y1_reg_t gamma_y1;
+    volatile isp_gamma_y2_reg_t gamma_y2;
+    volatile isp_gamma_y3_reg_t gamma_y3;
+    volatile isp_gamma_y4_reg_t gamma_y4;
+} isp_gamma_y_reg_t;
+
+typedef struct {
+    volatile isp_gamma_x1_reg_t gamma_x1;
+    volatile isp_gamma_x2_reg_t gamma_x2;
+} isp_gamma_x_reg_t;
+
+typedef struct {
+    volatile isp_ver_date_reg_t ver_date;
+    volatile isp_clk_en_reg_t clk_en;
+    volatile isp_cntl_reg_t cntl;
+    volatile isp_hsync_cnt_reg_t hsync_cnt;
+    volatile isp_frame_cfg_reg_t frame_cfg;
+    volatile isp_ccm_coef0_reg_t ccm_coef0;
+    volatile isp_ccm_coef1_reg_t ccm_coef1;
+    volatile isp_ccm_coef3_reg_t ccm_coef3;
+    volatile isp_ccm_coef4_reg_t ccm_coef4;
+    volatile isp_ccm_coef5_reg_t ccm_coef5;
+    volatile isp_bf_matrix_ctrl_reg_t bf_matrix_ctrl;
+    volatile isp_bf_sigma_reg_t bf_sigma;
+    volatile isp_bf_gau0_reg_t bf_gau0;
+    volatile isp_bf_gau1_reg_t bf_gau1;
+    volatile isp_dpc_ctrl_reg_t dpc_ctrl;
+    volatile isp_dpc_conf_reg_t dpc_conf;
+    volatile isp_dpc_matrix_ctrl_reg_t dpc_matrix_ctrl;
+    volatile isp_dpc_deadpix_cnt_reg_t dpc_deadpix_cnt;
+    volatile isp_lut_cmd_reg_t lut_cmd;
+    volatile isp_lut_wdata_reg_t lut_wdata;
+    volatile isp_lut_rdata_reg_t lut_rdata;
+    volatile isp_lsc_tablesize_reg_t lsc_tablesize;
+    volatile isp_demosaic_matrix_ctrl_reg_t demosaic_matrix_ctrl;
+    volatile isp_demosaic_grad_ratio_reg_t demosaic_grad_ratio;
+    volatile isp_median_matrix_ctrl_reg_t median_matrix_ctrl;
+    volatile isp_int_raw_reg_t int_raw;
+    volatile isp_int_st_reg_t int_st;
+    volatile isp_int_ena_reg_t int_ena;
+    volatile isp_int_clr_reg_t int_clr;
+    volatile isp_gamma_ctrl_reg_t gamma_ctrl;
+    volatile isp_gamma_y_reg_t gamma_rgb_y[3]; // r: gamma_rgb_y[0], g: gamma_rgb_y[1], b: gamma_rgb_y[2]
+    volatile isp_gamma_x_reg_t gamma_rgb_x[3]; // r: gamma_rgb_x[0], g: gamma_rgb_x[1], b: gamma_rgb_x[2]
+    volatile isp_ae_ctrl_reg_t ae_ctrl;
+    volatile isp_ae_monitor_reg_t ae_monitor;
+    volatile isp_ae_bx_reg_t ae_bx;
+    volatile isp_ae_by_reg_t ae_by;
+    volatile isp_ae_winpixnum_reg_t ae_winpixnum;
+    volatile isp_ae_win_reciprocal_reg_t ae_win_reciprocal;
+    volatile isp_ae_block_mean_reg_t ae_block_mean[7];
+    volatile isp_sharp_ctrl0_reg_t sharp_ctrl0;
+    volatile isp_sharp_filter_reg_t sharp_filter[3];
+    volatile isp_sharp_matrix_ctrl_reg_t sharp_matrix_ctrl;
+    volatile isp_sharp_ctrl1_reg_t sharp_ctrl1;
+    volatile isp_dma_cntl_reg_t dma_cntl;
+    volatile isp_dma_raw_data_reg_t dma_raw_data;
+    volatile isp_cam_cntl_reg_t cam_cntl;
+    volatile isp_cam_conf_reg_t cam_conf;
+    volatile isp_af_ctrl0_reg_t af_ctrl0;
+    volatile isp_af_ctrl1_reg_t af_ctrl1;
+    volatile isp_af_gen_th_ctrl_reg_t af_gen_th_ctrl;
+    volatile isp_af_env_user_th_sum_reg_t af_env_user_th_sum;
+    volatile isp_af_env_user_th_lum_reg_t af_env_user_th_lum;
+    volatile isp_af_threshold_reg_t af_threshold;
+    volatile isp_af_hscale_a_reg_t af_hscale_a;
+    volatile isp_af_vscale_a_reg_t af_vscale_a;
+    volatile isp_af_hscale_b_reg_t af_hscale_b;
+    volatile isp_af_vscale_b_reg_t af_vscale_b;
+    volatile isp_af_hscale_c_reg_t af_hscale_c;
+    volatile isp_af_vscale_c_reg_t af_vscale_c;
+    volatile isp_af_sum_a_reg_t af_sum_a;
+    volatile isp_af_sum_b_reg_t af_sum_b;
+    volatile isp_af_sum_c_reg_t af_sum_c;
+    volatile isp_af_lum_a_reg_t af_lum_a;
+    volatile isp_af_lum_b_reg_t af_lum_b;
+    volatile isp_af_lum_c_reg_t af_lum_c;
+    volatile isp_awb_mode_reg_t awb_mode;
+    volatile isp_awb_hscale_reg_t awb_hscale;
+    volatile isp_awb_vscale_reg_t awb_vscale;
+    volatile isp_awb_th_lum_reg_t awb_th_lum;
+    volatile isp_awb_th_rg_reg_t awb_th_rg;
+    volatile isp_awb_th_bg_reg_t awb_th_bg;
+    volatile isp_awb0_white_cnt_reg_t awb0_white_cnt;
+    volatile isp_awb0_acc_r_reg_t awb0_acc_r;
+    volatile isp_awb0_acc_g_reg_t awb0_acc_g;
+    volatile isp_awb0_acc_b_reg_t awb0_acc_b;
+    volatile isp_color_ctrl_reg_t color_ctrl;
+    volatile isp_blc_value_reg_t blc_value;
+    volatile isp_blc_ctrl0_reg_t blc_ctrl0;
+    volatile isp_blc_ctrl1_reg_t blc_ctrl1;
+    volatile isp_blc_ctrl2_reg_t blc_ctrl2;
+    volatile isp_blc_mean_reg_t blc_mean;
+    volatile isp_hist_mode_reg_t hist_mode;
+    volatile isp_hist_coeff_reg_t hist_coeff;
+    volatile isp_hist_offs_reg_t hist_offs;
+    volatile isp_hist_size_reg_t hist_size;
+    volatile isp_hist_seg_reg_t hist_seg[4];
+    volatile isp_hist_weight_reg_t hist_weight[7];
+    volatile isp_hist_binn_reg_t hist_binn[16];
+    volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0;
+    volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1;
+    volatile isp_mem_aux_ctrl_2_reg_t mem_aux_ctrl_2;
+    volatile isp_mem_aux_ctrl_3_reg_t mem_aux_ctrl_3;
+    volatile isp_mem_aux_ctrl_4_reg_t mem_aux_ctrl_4;
+    volatile isp_yuv_format_reg_t yuv_format;
+    volatile isp_rdn_eco_cs_reg_t rdn_eco_cs;
+    volatile isp_rdn_eco_low_reg_t rdn_eco_low;
+    volatile isp_rdn_eco_high_reg_t rdn_eco_high;
+} isp_dev_t;
+
+extern isp_dev_t ISP;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(isp_dev_t) == 0x244, "Invalid size of isp_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/jpeg_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/jpeg_eco5_struct.h
new file mode 100644
index 0000000000..c2c73c5bb5
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/jpeg_eco5_struct.h
@@ -0,0 +1,1483 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of config register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** fsm_rst : WT; bitpos: [0]; default: 0;
+         *  fsm reset
+         */
+        uint32_t fsm_rst:1;
+        /** jpeg_start : WT; bitpos: [1]; default: 0;
+         *  start to compress a new pic(in dma reg mode)
+         */
+        uint32_t jpeg_start:1;
+        /** qnr_precision : R/W; bitpos: [2]; default: 0;
+         *  0:8bit qnr,1:12bit qnr(TBD)
+         */
+        uint32_t qnr_precision:1;
+        /** ff_check_en : R/W; bitpos: [3]; default: 1;
+         *  enable whether to add '00' after 'ff'
+         */
+        uint32_t ff_check_en:1;
+        /** sample_sel : R/W; bitpos: [5:4]; default: 1;
+         *  0:yuv444,1:yuv422, 2:yuv420
+         */
+        uint32_t sample_sel:2;
+        /** dma_linklist_mode : RO; bitpos: [6]; default: 1;
+         *  1:use linklist to configure dma
+         */
+        uint32_t dma_linklist_mode:1;
+        /** debug_direct_out_en : R/W; bitpos: [7]; default: 0;
+         *  0:normal mode,1:debug mode for direct output from input
+         */
+        uint32_t debug_direct_out_en:1;
+        /** qnr_fifo_en : R/W; bitpos: [8]; default: 1;
+         *  0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram
+         */
+        uint32_t qnr_fifo_en:1;
+        /** lqnr_tbl_sel : R/W; bitpos: [10:9]; default: 0;
+         *  choose  luminance quntization table id(TBD)
+         */
+        uint32_t lqnr_tbl_sel:2;
+        /** cqnr_tbl_sel : R/W; bitpos: [12:11]; default: 1;
+         *  choose  chrominance quntization table id (TBD)
+         */
+        uint32_t cqnr_tbl_sel:2;
+        /** color_space : R/W; bitpos: [14:13]; default: 0;
+         *  configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray
+         */
+        uint32_t color_space:2;
+        /** dht_fifo_en : R/W; bitpos: [15]; default: 1;
+         *  0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to
+         *  write dht len_total/codemin/value table. Reading dht len_total/codemin/value table
+         *  only has nonfifo way
+         */
+        uint32_t dht_fifo_en:1;
+        /** mem_clk_force_on : R/W; bitpos: [16]; default: 0;
+         *  force memory's clock enabled
+         */
+        uint32_t mem_clk_force_on:1;
+        /** decode_timeout_thres : R/W; bitpos: [22:17]; default: 32;
+         *  decode pause period to trigger decode_timeout int, the timeout periods =2 power
+         *  (reg_decode_timeout_thres) -1
+         */
+        uint32_t decode_timeout_thres:6;
+        /** decode_timeout_task_sel : R/W; bitpos: [23]; default: 0;
+         *  0: software use reset to abort decode process ,1: decoder abort decode process by
+         *  itself
+         */
+        uint32_t decode_timeout_task_sel:1;
+        /** soft_rst : R/W; bitpos: [24]; default: 0;
+         *  when set to 1, soft reset JPEG module except jpeg_reg module
+         */
+        uint32_t soft_rst:1;
+        /** fifo_rst : R/W; bitpos: [25]; default: 0;
+         *  fifo reset
+         */
+        uint32_t fifo_rst:1;
+        /** pixel_rev : R/W; bitpos: [26]; default: 0;
+         *  reverse the source color pixel
+         */
+        uint32_t pixel_rev:1;
+        /** tailer_en : R/W; bitpos: [27]; default: 0;
+         *  set this bit to add EOI of '0xffd9' at the end of bitstream
+         */
+        uint32_t tailer_en:1;
+        /** pause_en : R/W; bitpos: [28]; default: 0;
+         *  set this bit to pause jpeg encoding
+         */
+        uint32_t pause_en:1;
+        /** mem_force_pd : R/W; bitpos: [29]; default: 0;
+         *  0: no operation,1:force jpeg memory to power down
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [30]; default: 0;
+         *  0: no operation,1:force jpeg memory to power up
+         */
+        uint32_t mem_force_pu:1;
+        /** mode : R/W; bitpos: [31]; default: 0;
+         *  0:encoder mode, 1: decoder mode
+         */
+        uint32_t mode:1;
+    };
+    uint32_t val;
+} jpeg_config_reg_t;
+
+/** Type of dqt_info register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** t0_dqt_info : R/W; bitpos: [7:0]; default: 0;
+         *  Configure dqt table0's quantization coefficient precision in bit[7:4], configure
+         *  dqt table0's table id in bit[3:0]
+         */
+        uint32_t t0_dqt_info:8;
+        /** t1_dqt_info : R/W; bitpos: [15:8]; default: 1;
+         *  Configure dqt table1's quantization coefficient precision in bit[7:4], configure
+         *  dqt table1's table id in bit[3:0]
+         */
+        uint32_t t1_dqt_info:8;
+        /** t2_dqt_info : R/W; bitpos: [23:16]; default: 2;
+         *  Configure dqt table2's quantization coefficient precision in bit[7:4], configure
+         *  dqt table2's table id in bit[3:0]
+         */
+        uint32_t t2_dqt_info:8;
+        /** t3_dqt_info : R/W; bitpos: [31:24]; default: 3;
+         *  Configure dqt table3's quantization coefficient precision in bit[7:4], configure
+         *  dqt table3's table id in bit[3:0]
+         */
+        uint32_t t3_dqt_info:8;
+    };
+    uint32_t val;
+} jpeg_dqt_info_reg_t;
+
+/** Type of pic_size register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** va : R/W; bitpos: [15:0]; default: 480;
+         *  configure picture's height. when encode, the max configurable bits is 14, when
+         *  decode, the max configurable bits is 16
+         */
+        uint32_t va:16;
+        /** ha : R/W; bitpos: [31:16]; default: 640;
+         *  configure picture's width. when encode, the max configurable bits is 14, when
+         *  decode, the max configurable bits is 16
+         */
+        uint32_t ha:16;
+    };
+    uint32_t val;
+} jpeg_pic_size_reg_t;
+
+/** Type of extd_config register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** extd_color_space_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether to extend picture's color space
+         *  0:disable
+         *  1:enable
+         */
+        uint32_t extd_color_space_en:1;
+        /** extd_color_space : R/W; bitpos: [1]; default: 0;
+         *  Configure extended picture's color space. Valid when JPEG_EXTD_COLOR_SPACE_EN
+         *  configured to 1
+         *  0:yuv444
+         *  1:yuv420
+         */
+        uint32_t extd_color_space:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} jpeg_extd_config_reg_t;
+
+/** Type of t0qnr register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** t0_qnr_val : HRO; bitpos: [31:0]; default: 0;
+         *  write this reg to configure 64 quantization coefficient in t0 table
+         */
+        uint32_t t0_qnr_val:32;
+    };
+    uint32_t val;
+} jpeg_t0qnr_reg_t;
+
+/** Type of t1qnr register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** t1_qnr_val : HRO; bitpos: [31:0]; default: 0;
+         *  write this reg to configure 64 quantization coefficient in t1 table
+         */
+        uint32_t t1_qnr_val:32;
+    };
+    uint32_t val;
+} jpeg_t1qnr_reg_t;
+
+/** Type of t2qnr register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** t2_qnr_val : HRO; bitpos: [31:0]; default: 0;
+         *  write this reg to configure 64 quantization coefficient in t2 table
+         */
+        uint32_t t2_qnr_val:32;
+    };
+    uint32_t val;
+} jpeg_t2qnr_reg_t;
+
+/** Type of t3qnr register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** t3_qnr_val : HRO; bitpos: [31:0]; default: 0;
+         *  write this reg to configure 64 quantization coefficient in t3 table
+         */
+        uint32_t t3_qnr_val:32;
+    };
+    uint32_t val;
+} jpeg_t3qnr_reg_t;
+
+/** Type of decode_conf register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** restart_interval : R/W; bitpos: [15:0]; default: 0;
+         *  configure restart interval in DRI marker when decode
+         */
+        uint32_t restart_interval:16;
+        /** component_num : R/W; bitpos: [23:16]; default: 3;
+         *  configure number of components in frame when decode
+         */
+        uint32_t component_num:8;
+        /** sw_dht_en : RO; bitpos: [24]; default: 1;
+         *  software decode dht table enable
+         */
+        uint32_t sw_dht_en:1;
+        /** sos_check_byte_num : R/W; bitpos: [26:25]; default: 3;
+         *  Configure the byte number to check next sos marker in the multi-scan picture after
+         *  one scan is decoded down. The real check number is reg_sos_check_byte_num+1
+         */
+        uint32_t sos_check_byte_num:2;
+        /** rst_check_byte_num : R/W; bitpos: [28:27]; default: 3;
+         *  Configure the byte number to check next rst marker after one rst interval is
+         *  decoded down. The real check number is reg_rst_check_byte_num+1
+         */
+        uint32_t rst_check_byte_num:2;
+        /** multi_scan_err_check : R/W; bitpos: [29]; default: 0;
+         *  reserved for decoder
+         */
+        uint32_t multi_scan_err_check:1;
+        /** dezigzag_ready_ctl : R/W; bitpos: [30]; default: 1;
+         *  reserved for decoder
+         */
+        uint32_t dezigzag_ready_ctl:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} jpeg_decode_conf_reg_t;
+
+/** Type of c0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** c0_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0;
+         *  choose  c0 quntization table id (TBD)
+         */
+        uint32_t c0_dqt_tbl_sel:8;
+        /** c0_y_factor : R/W; bitpos: [11:8]; default: 1;
+         *  vertical sampling factor of c0
+         */
+        uint32_t c0_y_factor:4;
+        /** c0_x_factor : R/W; bitpos: [15:12]; default: 1;
+         *  horizontal sampling factor of c0
+         */
+        uint32_t c0_x_factor:4;
+        /** c0_id : R/W; bitpos: [23:16]; default: 0;
+         *  the identifier of c0
+         */
+        uint32_t c0_id:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} jpeg_c0_reg_t;
+
+/** Type of c1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** c1_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0;
+         *  choose  c1 quntization table id (TBD)
+         */
+        uint32_t c1_dqt_tbl_sel:8;
+        /** c1_y_factor : R/W; bitpos: [11:8]; default: 1;
+         *  vertical sampling factor of c1
+         */
+        uint32_t c1_y_factor:4;
+        /** c1_x_factor : R/W; bitpos: [15:12]; default: 1;
+         *  horizontal sampling factor of c1
+         */
+        uint32_t c1_x_factor:4;
+        /** c1_id : R/W; bitpos: [23:16]; default: 0;
+         *  the identifier of c1
+         */
+        uint32_t c1_id:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} jpeg_c1_reg_t;
+
+/** Type of c2 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** c2_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0;
+         *  choose  c2 quntization table id (TBD)
+         */
+        uint32_t c2_dqt_tbl_sel:8;
+        /** c2_y_factor : R/W; bitpos: [11:8]; default: 1;
+         *  vertical sampling factor of c2
+         */
+        uint32_t c2_y_factor:4;
+        /** c2_x_factor : R/W; bitpos: [15:12]; default: 1;
+         *  horizontal sampling factor of c2
+         */
+        uint32_t c2_x_factor:4;
+        /** c2_id : R/W; bitpos: [23:16]; default: 0;
+         *  the identifier of c2
+         */
+        uint32_t c2_id:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} jpeg_c2_reg_t;
+
+/** Type of c3 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** c3_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0;
+         *  choose  c3 quntization table id (TBD)
+         */
+        uint32_t c3_dqt_tbl_sel:8;
+        /** c3_y_factor : R/W; bitpos: [11:8]; default: 1;
+         *  vertical sampling factor of c3
+         */
+        uint32_t c3_y_factor:4;
+        /** c3_x_factor : R/W; bitpos: [15:12]; default: 1;
+         *  horizontal sampling factor of c3
+         */
+        uint32_t c3_x_factor:4;
+        /** c3_id : R/W; bitpos: [23:16]; default: 0;
+         *  the identifier of c3
+         */
+        uint32_t c3_id:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} jpeg_c3_reg_t;
+
+/** Type of dht_info register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** dc0_dht_id : R/W; bitpos: [3:0]; default: 0;
+         *  configure dht dc table 0 id
+         */
+        uint32_t dc0_dht_id:4;
+        /** dc1_dht_id : R/W; bitpos: [7:4]; default: 1;
+         *  configure dht dc table 1 id
+         */
+        uint32_t dc1_dht_id:4;
+        /** ac0_dht_id : R/W; bitpos: [11:8]; default: 0;
+         *  configure dht ac table 0 id
+         */
+        uint32_t ac0_dht_id:4;
+        /** ac1_dht_id : R/W; bitpos: [15:12]; default: 1;
+         *  configure dht ac table 1 id
+         */
+        uint32_t ac1_dht_id:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} jpeg_dht_info_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Interrupt raw registers
+ */
+typedef union {
+    struct {
+        /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This raw interrupt bit turns to high level when JPEG finishes encoding a picture..
+         */
+        uint32_t done_int_raw:1;
+        /** rle_parallel_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit to sign that rle parallel error when decoding.
+         */
+        uint32_t rle_parallel_err_int_raw:1;
+        /** cid_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit to sign that scan id check with component fails when decoding.
+         */
+        uint32_t cid_err_int_raw:1;
+        /** c_dht_dc_id_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit to sign that scan component's dc dht id check with dc dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_dc_id_err_int_raw:1;
+        /** c_dht_ac_id_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit to sign that scan component's ac dht id check with ac dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_ac_id_err_int_raw:1;
+        /** c_dqt_id_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit to sign that scan component's dqt id check with dqt table's
+         *  id fails when decoding.
+         */
+        uint32_t c_dqt_id_err_int_raw:1;
+        /** rst_uxp_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit to sign that RST header marker is detected but restart
+         *  interval is 0 when decoding.
+         */
+        uint32_t rst_uxp_err_int_raw:1;
+        /** rst_check_none_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit to sign that RST header marker is not detected but restart
+         *  interval is not 0 when decoding.
+         */
+        uint32_t rst_check_none_err_int_raw:1;
+        /** rst_check_pos_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit to sign that RST header marker position mismatches with
+         *  restart interval when decoding.
+         */
+        uint32_t rst_check_pos_err_int_raw:1;
+        /** out_eof_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when the last pixel of one square has
+         *  been transmitted for Tx channel.
+         */
+        uint32_t out_eof_int_raw:1;
+        /** sr_color_mode_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit to sign that the selected source color mode is not supported.
+         */
+        uint32_t sr_color_mode_err_int_raw:1;
+        /** dct_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit to sign that one dct calculation is finished.
+         */
+        uint32_t dct_done_int_raw:1;
+        /** bs_last_block_eof_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit to sign that the coding process for last block is finished.
+         */
+        uint32_t bs_last_block_eof_int_raw:1;
+        /** scan_check_none_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit to sign that SOS header marker is not detected but there are
+         *  still components left to be decoded.
+         */
+        uint32_t scan_check_none_err_int_raw:1;
+        /** scan_check_pos_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw interrupt bit to sign that SOS header marker position wrong when decoding.
+         */
+        uint32_t scan_check_pos_err_int_raw:1;
+        /** uxp_det_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw interrupt bit to sign that unsupported header marker is detected when
+         *  decoding.
+         */
+        uint32_t uxp_det_int_raw:1;
+        /** en_frame_eof_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw interrupt bit to sign that received pixel blocks are smaller than expected
+         *  when encoding.
+         */
+        uint32_t en_frame_eof_err_int_raw:1;
+        /** en_frame_eof_lack_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw interrupt bit to sign that the frame eof sign bit from dma input is missing
+         *  when encoding. But the number of pixel blocks is enough.
+         */
+        uint32_t en_frame_eof_lack_int_raw:1;
+        /** de_frame_eof_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw interrupt bit to sign that decoded blocks are smaller than expected when
+         *  decoding.
+         */
+        uint32_t de_frame_eof_err_int_raw:1;
+        /** de_frame_eof_lack_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw interrupt bit to sign that the either frame eof from dma input or eoi
+         *  marker is missing when encoding. But the number of decoded blocks is enough.
+         */
+        uint32_t de_frame_eof_lack_int_raw:1;
+        /** sos_unmatch_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw interrupt bit to sign that the component number of a scan is 0 or does not
+         *  match the sos marker's length when decoding.
+         */
+        uint32_t sos_unmatch_err_int_raw:1;
+        /** marker_err_fst_scan_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  The raw interrupt bit to sign that the first scan has header marker error when
+         *  decoding.
+         */
+        uint32_t marker_err_fst_scan_int_raw:1;
+        /** marker_err_other_scan_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  The raw interrupt bit to sign that the following scans but not the first scan have
+         *  header marker error when decoding.
+         */
+        uint32_t marker_err_other_scan_int_raw:1;
+        /** undet_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  The raw interrupt bit to sign that JPEG format is not detected at the eof data of a
+         *  packet when decoding.
+         */
+        uint32_t undet_int_raw:1;
+        /** decode_timeout_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  The raw interrupt bit to sign that decode pause time is longer than the setting
+         *  decode timeout time when decoding.
+         */
+        uint32_t decode_timeout_int_raw:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} jpeg_int_raw_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable registers
+ */
+typedef union {
+    struct {
+        /** done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This enable interrupt bit turns to high level when JPEG finishes encoding a
+         *  picture..
+         */
+        uint32_t done_int_ena:1;
+        /** rle_parallel_err_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable interrupt bit to sign that rle parallel error when decoding.
+         */
+        uint32_t rle_parallel_err_int_ena:1;
+        /** cid_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable interrupt bit to sign that scan id check with component fails when
+         *  decoding.
+         */
+        uint32_t cid_err_int_ena:1;
+        /** c_dht_dc_id_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable interrupt bit to sign that scan component's dc dht id check with dc dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_dc_id_err_int_ena:1;
+        /** c_dht_ac_id_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable interrupt bit to sign that scan component's ac dht id check with ac dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_ac_id_err_int_ena:1;
+        /** c_dqt_id_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The enable interrupt bit to sign that scan component's dqt id check with dqt
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dqt_id_err_int_ena:1;
+        /** rst_uxp_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The enable interrupt bit to sign that RST header marker is detected but restart
+         *  interval is 0 when decoding.
+         */
+        uint32_t rst_uxp_err_int_ena:1;
+        /** rst_check_none_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The enable interrupt bit to sign that RST header marker is not detected but restart
+         *  interval is not 0 when decoding.
+         */
+        uint32_t rst_check_none_err_int_ena:1;
+        /** rst_check_pos_err_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The enable interrupt bit to sign that RST header marker position mismatches with
+         *  restart interval when decoding.
+         */
+        uint32_t rst_check_pos_err_int_ena:1;
+        /** out_eof_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The enable interrupt bit turns to high level when the last pixel of one square has
+         *  been transmitted for Tx channel.
+         */
+        uint32_t out_eof_int_ena:1;
+        /** sr_color_mode_err_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The enable interrupt bit to sign that the selected source color mode is not
+         *  supported.
+         */
+        uint32_t sr_color_mode_err_int_ena:1;
+        /** dct_done_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The enable interrupt bit to sign that one dct calculation is finished.
+         */
+        uint32_t dct_done_int_ena:1;
+        /** bs_last_block_eof_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The enable interrupt bit to sign that the coding process for last block is finished.
+         */
+        uint32_t bs_last_block_eof_int_ena:1;
+        /** scan_check_none_err_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The enable interrupt bit to sign that SOS header marker is not detected but there
+         *  are still components left to be decoded.
+         */
+        uint32_t scan_check_none_err_int_ena:1;
+        /** scan_check_pos_err_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The enable interrupt bit to sign that SOS header marker position wrong when
+         *  decoding.
+         */
+        uint32_t scan_check_pos_err_int_ena:1;
+        /** uxp_det_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The enable interrupt bit to sign that unsupported header marker is detected when
+         *  decoding.
+         */
+        uint32_t uxp_det_int_ena:1;
+        /** en_frame_eof_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The enable interrupt bit to sign that received pixel blocks are smaller than
+         *  expected when encoding.
+         */
+        uint32_t en_frame_eof_err_int_ena:1;
+        /** en_frame_eof_lack_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The enable interrupt bit to sign that the frame eof sign bit from dma input is
+         *  missing when encoding. But the number of pixel blocks is enough.
+         */
+        uint32_t en_frame_eof_lack_int_ena:1;
+        /** de_frame_eof_err_int_ena : R/W; bitpos: [18]; default: 0;
+         *  The enable interrupt bit to sign that decoded blocks are smaller than expected when
+         *  decoding.
+         */
+        uint32_t de_frame_eof_err_int_ena:1;
+        /** de_frame_eof_lack_int_ena : R/W; bitpos: [19]; default: 0;
+         *  The enable interrupt bit to sign that the either frame eof from dma input or eoi
+         *  marker is missing when encoding. But the number of decoded blocks is enough.
+         */
+        uint32_t de_frame_eof_lack_int_ena:1;
+        /** sos_unmatch_err_int_ena : R/W; bitpos: [20]; default: 0;
+         *  The enable interrupt bit to sign that the component number of a scan is 0 or does
+         *  not match the sos marker's length when decoding.
+         */
+        uint32_t sos_unmatch_err_int_ena:1;
+        /** marker_err_fst_scan_int_ena : R/W; bitpos: [21]; default: 0;
+         *  The enable interrupt bit to sign that the first scan has header marker error when
+         *  decoding.
+         */
+        uint32_t marker_err_fst_scan_int_ena:1;
+        /** marker_err_other_scan_int_ena : R/W; bitpos: [22]; default: 0;
+         *  The enable interrupt bit to sign that the following scans but not the first scan
+         *  have header marker error when decoding.
+         */
+        uint32_t marker_err_other_scan_int_ena:1;
+        /** undet_int_ena : R/W; bitpos: [23]; default: 0;
+         *  The enable interrupt bit to sign that JPEG format is not detected at the eof data
+         *  of a packet when decoding.
+         */
+        uint32_t undet_int_ena:1;
+        /** decode_timeout_int_ena : R/W; bitpos: [24]; default: 0;
+         *  The enable interrupt bit to sign that decode pause time is longer than the setting
+         *  decode timeout time when decoding.
+         */
+        uint32_t decode_timeout_int_ena:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} jpeg_int_ena_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status registers
+ */
+typedef union {
+    struct {
+        /** done_int_st : RO; bitpos: [0]; default: 0;
+         *  This status interrupt bit turns to high level when JPEG finishes encoding a
+         *  picture..
+         */
+        uint32_t done_int_st:1;
+        /** rle_parallel_err_int_st : RO; bitpos: [1]; default: 0;
+         *  The status interrupt bit to sign that rle parallel error when decoding.
+         */
+        uint32_t rle_parallel_err_int_st:1;
+        /** cid_err_int_st : RO; bitpos: [2]; default: 0;
+         *  The status interrupt bit to sign that scan id check with component fails when
+         *  decoding.
+         */
+        uint32_t cid_err_int_st:1;
+        /** c_dht_dc_id_err_int_st : RO; bitpos: [3]; default: 0;
+         *  The status interrupt bit to sign that scan component's dc dht id check with dc dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_dc_id_err_int_st:1;
+        /** c_dht_ac_id_err_int_st : RO; bitpos: [4]; default: 0;
+         *  The status interrupt bit to sign that scan component's ac dht id check with ac dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_ac_id_err_int_st:1;
+        /** c_dqt_id_err_int_st : RO; bitpos: [5]; default: 0;
+         *  The status interrupt bit to sign that scan component's dqt id check with dqt
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dqt_id_err_int_st:1;
+        /** rst_uxp_err_int_st : RO; bitpos: [6]; default: 0;
+         *  The status interrupt bit to sign that RST header marker is detected but restart
+         *  interval is 0 when decoding.
+         */
+        uint32_t rst_uxp_err_int_st:1;
+        /** rst_check_none_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The status interrupt bit to sign that RST header marker is not detected but restart
+         *  interval is not 0 when decoding.
+         */
+        uint32_t rst_check_none_err_int_st:1;
+        /** rst_check_pos_err_int_st : RO; bitpos: [8]; default: 0;
+         *  The status interrupt bit to sign that RST header marker position mismatches with
+         *  restart interval when decoding.
+         */
+        uint32_t rst_check_pos_err_int_st:1;
+        /** out_eof_int_st : RO; bitpos: [9]; default: 0;
+         *  The status interrupt bit turns to high level when the last pixel of one square has
+         *  been transmitted for Tx channel.
+         */
+        uint32_t out_eof_int_st:1;
+        /** sr_color_mode_err_int_st : RO; bitpos: [10]; default: 0;
+         *  The status interrupt bit to sign that the selected source color mode is not
+         *  supported.
+         */
+        uint32_t sr_color_mode_err_int_st:1;
+        /** dct_done_int_st : RO; bitpos: [11]; default: 0;
+         *  The status interrupt bit to sign that one dct calculation is finished.
+         */
+        uint32_t dct_done_int_st:1;
+        /** bs_last_block_eof_int_st : RO; bitpos: [12]; default: 0;
+         *  The status interrupt bit to sign that the coding process for last block is finished.
+         */
+        uint32_t bs_last_block_eof_int_st:1;
+        /** scan_check_none_err_int_st : RO; bitpos: [13]; default: 0;
+         *  The status interrupt bit to sign that SOS header marker is not detected but there
+         *  are still components left to be decoded.
+         */
+        uint32_t scan_check_none_err_int_st:1;
+        /** scan_check_pos_err_int_st : RO; bitpos: [14]; default: 0;
+         *  The status interrupt bit to sign that SOS header marker position wrong when
+         *  decoding.
+         */
+        uint32_t scan_check_pos_err_int_st:1;
+        /** uxp_det_int_st : RO; bitpos: [15]; default: 0;
+         *  The status interrupt bit to sign that unsupported header marker is detected when
+         *  decoding.
+         */
+        uint32_t uxp_det_int_st:1;
+        /** en_frame_eof_err_int_st : RO; bitpos: [16]; default: 0;
+         *  The status interrupt bit to sign that received pixel blocks are smaller than
+         *  expected when encoding.
+         */
+        uint32_t en_frame_eof_err_int_st:1;
+        /** en_frame_eof_lack_int_st : RO; bitpos: [17]; default: 0;
+         *  The status interrupt bit to sign that the frame eof sign bit from dma input is
+         *  missing when encoding. But the number of pixel blocks is enough.
+         */
+        uint32_t en_frame_eof_lack_int_st:1;
+        /** de_frame_eof_err_int_st : RO; bitpos: [18]; default: 0;
+         *  The status interrupt bit to sign that decoded blocks are smaller than expected when
+         *  decoding.
+         */
+        uint32_t de_frame_eof_err_int_st:1;
+        /** de_frame_eof_lack_int_st : RO; bitpos: [19]; default: 0;
+         *  The status interrupt bit to sign that the either frame eof from dma input or eoi
+         *  marker is missing when encoding. But the number of decoded blocks is enough.
+         */
+        uint32_t de_frame_eof_lack_int_st:1;
+        /** sos_unmatch_err_int_st : RO; bitpos: [20]; default: 0;
+         *  The status interrupt bit to sign that the component number of a scan is 0 or does
+         *  not match the sos marker's length when decoding.
+         */
+        uint32_t sos_unmatch_err_int_st:1;
+        /** marker_err_fst_scan_int_st : RO; bitpos: [21]; default: 0;
+         *  The status interrupt bit to sign that the first scan has header marker error when
+         *  decoding.
+         */
+        uint32_t marker_err_fst_scan_int_st:1;
+        /** marker_err_other_scan_int_st : RO; bitpos: [22]; default: 0;
+         *  The status interrupt bit to sign that the following scans but not the first scan
+         *  have header marker error when decoding.
+         */
+        uint32_t marker_err_other_scan_int_st:1;
+        /** undet_int_st : RO; bitpos: [23]; default: 0;
+         *  The status interrupt bit to sign that JPEG format is not detected at the eof data
+         *  of a packet when decoding.
+         */
+        uint32_t undet_int_st:1;
+        /** decode_timeout_int_st : RO; bitpos: [24]; default: 0;
+         *  The status interrupt bit to sign that decode pause time is longer than the setting
+         *  decode timeout time when decoding.
+         */
+        uint32_t decode_timeout_int_st:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} jpeg_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear registers
+ */
+typedef union {
+    struct {
+        /** done_int_clr : WT; bitpos: [0]; default: 0;
+         *  This clear interrupt bit turns to high level when JPEG finishes encoding a picture..
+         */
+        uint32_t done_int_clr:1;
+        /** rle_parallel_err_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear interrupt bit to sign that rle parallel error when decoding.
+         */
+        uint32_t rle_parallel_err_int_clr:1;
+        /** cid_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear interrupt bit to sign that scan id check with component fails when
+         *  decoding.
+         */
+        uint32_t cid_err_int_clr:1;
+        /** c_dht_dc_id_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear interrupt bit to sign that scan component's dc dht id check with dc dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_dc_id_err_int_clr:1;
+        /** c_dht_ac_id_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear interrupt bit to sign that scan component's ac dht id check with ac dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_ac_id_err_int_clr:1;
+        /** c_dqt_id_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  The clear interrupt bit to sign that scan component's dqt id check with dqt table's
+         *  id fails when decoding.
+         */
+        uint32_t c_dqt_id_err_int_clr:1;
+        /** rst_uxp_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  The clear interrupt bit to sign that RST header marker is detected but restart
+         *  interval is 0 when decoding.
+         */
+        uint32_t rst_uxp_err_int_clr:1;
+        /** rst_check_none_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  The clear interrupt bit to sign that RST header marker is not detected but restart
+         *  interval is not 0 when decoding.
+         */
+        uint32_t rst_check_none_err_int_clr:1;
+        /** rst_check_pos_err_int_clr : WT; bitpos: [8]; default: 0;
+         *  The clear interrupt bit to sign that RST header marker position mismatches with
+         *  restart interval when decoding.
+         */
+        uint32_t rst_check_pos_err_int_clr:1;
+        /** out_eof_int_clr : WT; bitpos: [9]; default: 0;
+         *  The clear interrupt bit turns to high level when the last pixel of one square has
+         *  been transmitted for Tx channel.
+         */
+        uint32_t out_eof_int_clr:1;
+        /** sr_color_mode_err_int_clr : WT; bitpos: [10]; default: 0;
+         *  The clear interrupt bit to sign that the selected source color mode is not
+         *  supported.
+         */
+        uint32_t sr_color_mode_err_int_clr:1;
+        /** dct_done_int_clr : WT; bitpos: [11]; default: 0;
+         *  The clear interrupt bit to sign that one dct calculation is finished.
+         */
+        uint32_t dct_done_int_clr:1;
+        /** bs_last_block_eof_int_clr : WT; bitpos: [12]; default: 0;
+         *  The clear interrupt bit to sign that the coding process for last block is finished.
+         */
+        uint32_t bs_last_block_eof_int_clr:1;
+        /** scan_check_none_err_int_clr : WT; bitpos: [13]; default: 0;
+         *  The clear interrupt bit to sign that SOS header marker is not detected but there
+         *  are still components left to be decoded.
+         */
+        uint32_t scan_check_none_err_int_clr:1;
+        /** scan_check_pos_err_int_clr : WT; bitpos: [14]; default: 0;
+         *  The clear interrupt bit to sign that SOS header marker position wrong when decoding.
+         */
+        uint32_t scan_check_pos_err_int_clr:1;
+        /** uxp_det_int_clr : WT; bitpos: [15]; default: 0;
+         *  The clear interrupt bit to sign that unsupported header marker is detected when
+         *  decoding.
+         */
+        uint32_t uxp_det_int_clr:1;
+        /** en_frame_eof_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  The clear interrupt bit to sign that received pixel blocks are smaller than
+         *  expected when encoding.
+         */
+        uint32_t en_frame_eof_err_int_clr:1;
+        /** en_frame_eof_lack_int_clr : WT; bitpos: [17]; default: 0;
+         *  The clear interrupt bit to sign that the frame eof sign bit from dma input is
+         *  missing when encoding. But the number of pixel blocks is enough.
+         */
+        uint32_t en_frame_eof_lack_int_clr:1;
+        /** de_frame_eof_err_int_clr : WT; bitpos: [18]; default: 0;
+         *  The clear interrupt bit to sign that decoded blocks are smaller than expected when
+         *  decoding.
+         */
+        uint32_t de_frame_eof_err_int_clr:1;
+        /** de_frame_eof_lack_int_clr : WT; bitpos: [19]; default: 0;
+         *  The clear interrupt bit to sign that the either frame eof from dma input or eoi
+         *  marker is missing when encoding. But the number of decoded blocks is enough.
+         */
+        uint32_t de_frame_eof_lack_int_clr:1;
+        /** sos_unmatch_err_int_clr : WT; bitpos: [20]; default: 0;
+         *  The clear interrupt bit to sign that the component number of a scan is 0 or does
+         *  not match the sos marker's length when decoding.
+         */
+        uint32_t sos_unmatch_err_int_clr:1;
+        /** marker_err_fst_scan_int_clr : WT; bitpos: [21]; default: 0;
+         *  The clear interrupt bit to sign that the first scan has header marker error when
+         *  decoding.
+         */
+        uint32_t marker_err_fst_scan_int_clr:1;
+        /** marker_err_other_scan_int_clr : WT; bitpos: [22]; default: 0;
+         *  The clear interrupt bit to sign that the following scans but not the first scan
+         *  have header marker error when decoding.
+         */
+        uint32_t marker_err_other_scan_int_clr:1;
+        /** undet_int_clr : WT; bitpos: [23]; default: 0;
+         *  The clear interrupt bit to sign that JPEG format is not detected at the eof data of
+         *  a packet when decoding.
+         */
+        uint32_t undet_int_clr:1;
+        /** decode_timeout_int_clr : WT; bitpos: [24]; default: 0;
+         *  The clear interrupt bit to sign that decode pause time is longer than the setting
+         *  decode timeout time when decoding.
+         */
+        uint32_t decode_timeout_int_clr:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} jpeg_int_clr_reg_t;
+
+
+/** Group: Trace and Debug registers */
+/** Type of status0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:11;
+        /** bitstream_eof_vld_cnt : RO; bitpos: [16:11]; default: 0;
+         *  the valid bit count for last bitstream
+         */
+        uint32_t bitstream_eof_vld_cnt:6;
+        /** dctout_zzscan_addr : RO; bitpos: [22:17]; default: 0;
+         *  the zig-zag read addr from dctout_ram
+         */
+        uint32_t dctout_zzscan_addr:6;
+        /** qnrval_zzscan_addr : RO; bitpos: [28:23]; default: 0;
+         *  the zig-zag read addr from qnrval_ram
+         */
+        uint32_t qnrval_zzscan_addr:6;
+        /** reg_state_yuv : RO; bitpos: [31:29]; default: 0;
+         *  the state of jpeg fsm
+         */
+        uint32_t reg_state_yuv:3;
+    };
+    uint32_t val;
+} jpeg_status0_reg_t;
+
+/** Type of status2 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** source_pixel : RO; bitpos: [23:0]; default: 0;
+         *  source pixels fetched from dma
+         */
+        uint32_t source_pixel:24;
+        /** last_block : RO; bitpos: [24]; default: 0;
+         *  indicate the encoding process for the last mcu of the picture
+         */
+        uint32_t last_block:1;
+        /** last_mcu : RO; bitpos: [25]; default: 0;
+         *  indicate the encoding process for the last block of the picture
+         */
+        uint32_t last_mcu:1;
+        /** last_dc : RO; bitpos: [26]; default: 0;
+         *  indicate the encoding process is at the header of the last block of the picture
+         */
+        uint32_t last_dc:1;
+        /** packfifo_ready : RO; bitpos: [27]; default: 1;
+         *  the jpeg pack_fifo ready signal, high active
+         */
+        uint32_t packfifo_ready:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} jpeg_status2_reg_t;
+
+/** Type of status3 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** yo : RO; bitpos: [8:0]; default: 0;
+         *  component y transferred from rgb input
+         */
+        uint32_t yo:9;
+        /** y_ready : RO; bitpos: [9]; default: 0;
+         *  component y valid signal, high active
+         */
+        uint32_t y_ready:1;
+        /** cbo : RO; bitpos: [18:10]; default: 0;
+         *  component cb transferred from rgb input
+         */
+        uint32_t cbo:9;
+        /** cb_ready : RO; bitpos: [19]; default: 0;
+         *  component cb valid signal, high active
+         */
+        uint32_t cb_ready:1;
+        /** cro : RO; bitpos: [28:20]; default: 0;
+         *  component cr transferred from rgb input
+         */
+        uint32_t cro:9;
+        /** cr_ready : RO; bitpos: [29]; default: 0;
+         *  component cr valid signal, high active
+         */
+        uint32_t cr_ready:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} jpeg_status3_reg_t;
+
+/** Type of status4 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** hfm_bitstream : RO; bitpos: [31:0]; default: 0;
+         *  the hufman bitstream during encoding process
+         */
+        uint32_t hfm_bitstream:32;
+    };
+    uint32_t val;
+} jpeg_status4_reg_t;
+
+/** Type of dht_totlen_dc0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_totlen_dc0 : HRO; bitpos: [31:0]; default: 0;
+         *  write the numbers of 1~n codeword length sum from 1~16 of dc0 table
+         */
+        uint32_t dht_totlen_dc0:32;
+    };
+    uint32_t val;
+} jpeg_dht_totlen_dc0_reg_t;
+
+/** Type of dht_val_dc0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_val_dc0 : HRO; bitpos: [31:0]; default: 0;
+         *  write codeword corresponding huffman values of dc0 table
+         */
+        uint32_t dht_val_dc0:32;
+    };
+    uint32_t val;
+} jpeg_dht_val_dc0_reg_t;
+
+/** Type of dht_totlen_ac0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_totlen_ac0 : HRO; bitpos: [31:0]; default: 0;
+         *  write the numbers of 1~n codeword length sum from 1~16 of ac0 table
+         */
+        uint32_t dht_totlen_ac0:32;
+    };
+    uint32_t val;
+} jpeg_dht_totlen_ac0_reg_t;
+
+/** Type of dht_val_ac0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_val_ac0 : HRO; bitpos: [31:0]; default: 0;
+         *  write codeword corresponding huffman values of ac0 table
+         */
+        uint32_t dht_val_ac0:32;
+    };
+    uint32_t val;
+} jpeg_dht_val_ac0_reg_t;
+
+/** Type of dht_totlen_dc1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_totlen_dc1 : HRO; bitpos: [31:0]; default: 0;
+         *  write the numbers of 1~n codeword length sum from 1~16 of dc1 table
+         */
+        uint32_t dht_totlen_dc1:32;
+    };
+    uint32_t val;
+} jpeg_dht_totlen_dc1_reg_t;
+
+/** Type of dht_val_dc1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_val_dc1 : HRO; bitpos: [31:0]; default: 0;
+         *  write codeword corresponding huffman values of dc1 table
+         */
+        uint32_t dht_val_dc1:32;
+    };
+    uint32_t val;
+} jpeg_dht_val_dc1_reg_t;
+
+/** Type of dht_totlen_ac1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_totlen_ac1 : HRO; bitpos: [31:0]; default: 0;
+         *  write the numbers of 1~n codeword length sum from 1~16 of ac1 table
+         */
+        uint32_t dht_totlen_ac1:32;
+    };
+    uint32_t val;
+} jpeg_dht_totlen_ac1_reg_t;
+
+/** Type of dht_val_ac1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_val_ac1 : HRO; bitpos: [31:0]; default: 0;
+         *  write codeword corresponding huffman values of ac1 table
+         */
+        uint32_t dht_val_ac1:32;
+    };
+    uint32_t val;
+} jpeg_dht_val_ac1_reg_t;
+
+/** Type of dht_codemin_dc0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_codemin_dc0 : HRO; bitpos: [31:0]; default: 0;
+         *  write the minimum codeword of  code length from 1~16 of dc0 table. The codeword is
+         *  left shifted to the MSB position of a 16bit word
+         */
+        uint32_t dht_codemin_dc0:32;
+    };
+    uint32_t val;
+} jpeg_dht_codemin_dc0_reg_t;
+
+/** Type of dht_codemin_ac0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_codemin_ac0 : HRO; bitpos: [31:0]; default: 0;
+         *  write the minimum codeword of  code length from 1~16 of ac0 table. The codeword is
+         *  left shifted to the MSB position of a 16bit word
+         */
+        uint32_t dht_codemin_ac0:32;
+    };
+    uint32_t val;
+} jpeg_dht_codemin_ac0_reg_t;
+
+/** Type of dht_codemin_dc1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_codemin_dc1 : HRO; bitpos: [31:0]; default: 0;
+         *  write the minimum codeword of  code length from 1~16 of dc1 table. The codeword is
+         *  left shifted to the MSB position of a 16bit word
+         */
+        uint32_t dht_codemin_dc1:32;
+    };
+    uint32_t val;
+} jpeg_dht_codemin_dc1_reg_t;
+
+/** Type of dht_codemin_ac1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_codemin_ac1 : HRO; bitpos: [31:0]; default: 0;
+         *  write the minimum codeword of  code length from 1~16 of ac1 table. The codeword is
+         *  left shifted to the MSB position of a 16bit word
+         */
+        uint32_t dht_codemin_ac1:32;
+    };
+    uint32_t val;
+} jpeg_dht_codemin_ac1_reg_t;
+
+/** Type of decoder_status0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** decode_byte_cnt : RO; bitpos: [25:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t decode_byte_cnt:26;
+        /** header_dec_st : RO; bitpos: [29:26]; default: 0;
+         *  Reserved
+         */
+        uint32_t header_dec_st:4;
+        /** decode_sample_sel : RO; bitpos: [31:30]; default: 0;
+         *  Reserved
+         */
+        uint32_t decode_sample_sel:2;
+    };
+    uint32_t val;
+} jpeg_decoder_status0_reg_t;
+
+/** Type of decoder_status1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** encode_data : RO; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t encode_data:16;
+        /** count_q : RO; bitpos: [22:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t count_q:7;
+        /** mcu_fsm_ready : RO; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t mcu_fsm_ready:1;
+        /** decode_data : RO; bitpos: [31:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t decode_data:8;
+    };
+    uint32_t val;
+} jpeg_decoder_status1_reg_t;
+
+/** Type of decoder_status2 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** comp_block_num : RO; bitpos: [25:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t comp_block_num:26;
+        /** scan_num : RO; bitpos: [28:26]; default: 0;
+         *  Reserved
+         */
+        uint32_t scan_num:3;
+        /** rst_check_wait : RO; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t rst_check_wait:1;
+        /** scan_check_wait : RO; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t scan_check_wait:1;
+        /** mcu_in_proc : RO; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t mcu_in_proc:1;
+    };
+    uint32_t val;
+} jpeg_decoder_status2_reg_t;
+
+/** Type of decoder_status3 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** lookup_data : RO; bitpos: [31:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t lookup_data:32;
+    };
+    uint32_t val;
+} jpeg_decoder_status3_reg_t;
+
+/** Type of decoder_status4 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** block_eof_cnt : RO; bitpos: [25:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t block_eof_cnt:26;
+        /** dezigzag_ready : RO; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t dezigzag_ready:1;
+        /** de_frame_eof_check : RO; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t de_frame_eof_check:1;
+        /** de_dma2d_in_push : RO; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t de_dma2d_in_push:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} jpeg_decoder_status4_reg_t;
+
+/** Type of decoder_status5 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** idct_hfm_data : RO; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t idct_hfm_data:16;
+        /** ns0 : RO; bitpos: [18:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t ns0:3;
+        /** ns1 : RO; bitpos: [21:19]; default: 0;
+         *  Reserved
+         */
+        uint32_t ns1:3;
+        /** ns2 : RO; bitpos: [24:22]; default: 0;
+         *  Reserved
+         */
+        uint32_t ns2:3;
+        /** ns3 : RO; bitpos: [27:25]; default: 0;
+         *  Reserved
+         */
+        uint32_t ns3:3;
+        /** data_last_o : RO; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t data_last_o:1;
+        /** rdn_result : RO; bitpos: [29]; default: 0;
+         *  redundant registers for jpeg
+         */
+        uint32_t rdn_result:1;
+        /** rdn_ena : R/W; bitpos: [30]; default: 0;
+         *  redundant control registers for jpeg
+         */
+        uint32_t rdn_ena:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} jpeg_decoder_status5_reg_t;
+
+/** Type of status5 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** pic_block_num : RO; bitpos: [23:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t pic_block_num:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} jpeg_status5_reg_t;
+
+/** Type of eco_low register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  redundant registers for jpeg
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} jpeg_eco_low_reg_t;
+
+/** Type of eco_high register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  redundant registers for jpeg
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} jpeg_eco_high_reg_t;
+
+/** Type of sys register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} jpeg_sys_reg_t;
+
+/** Type of version register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** jpeg_ver : R/W; bitpos: [27:0]; default: 37823072;
+         *  Reserved
+         */
+        uint32_t jpeg_ver:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} jpeg_version_reg_t;
+
+
+typedef struct {
+    volatile jpeg_config_reg_t config;
+    volatile jpeg_dqt_info_reg_t dqt_info;
+    volatile jpeg_pic_size_reg_t pic_size;
+    volatile jpeg_extd_config_reg_t extd_config;
+    volatile jpeg_t0qnr_reg_t t0qnr;
+    volatile jpeg_t1qnr_reg_t t1qnr;
+    volatile jpeg_t2qnr_reg_t t2qnr;
+    volatile jpeg_t3qnr_reg_t t3qnr;
+    volatile jpeg_decode_conf_reg_t decode_conf;
+    volatile jpeg_c0_reg_t c0;
+    volatile jpeg_c1_reg_t c1;
+    volatile jpeg_c2_reg_t c2;
+    volatile jpeg_c3_reg_t c3;
+    volatile jpeg_dht_info_reg_t dht_info;
+    volatile jpeg_int_raw_reg_t int_raw;
+    volatile jpeg_int_ena_reg_t int_ena;
+    volatile jpeg_int_st_reg_t int_st;
+    volatile jpeg_int_clr_reg_t int_clr;
+    volatile jpeg_status0_reg_t status0;
+    volatile jpeg_status2_reg_t status2;
+    volatile jpeg_status3_reg_t status3;
+    volatile jpeg_status4_reg_t status4;
+    volatile jpeg_dht_totlen_dc0_reg_t dht_totlen_dc0;
+    volatile jpeg_dht_val_dc0_reg_t dht_val_dc0;
+    volatile jpeg_dht_totlen_ac0_reg_t dht_totlen_ac0;
+    volatile jpeg_dht_val_ac0_reg_t dht_val_ac0;
+    volatile jpeg_dht_totlen_dc1_reg_t dht_totlen_dc1;
+    volatile jpeg_dht_val_dc1_reg_t dht_val_dc1;
+    volatile jpeg_dht_totlen_ac1_reg_t dht_totlen_ac1;
+    volatile jpeg_dht_val_ac1_reg_t dht_val_ac1;
+    volatile jpeg_dht_codemin_dc0_reg_t dht_codemin_dc0;
+    volatile jpeg_dht_codemin_ac0_reg_t dht_codemin_ac0;
+    volatile jpeg_dht_codemin_dc1_reg_t dht_codemin_dc1;
+    volatile jpeg_dht_codemin_ac1_reg_t dht_codemin_ac1;
+    volatile jpeg_decoder_status0_reg_t decoder_status0;
+    volatile jpeg_decoder_status1_reg_t decoder_status1;
+    volatile jpeg_decoder_status2_reg_t decoder_status2;
+    volatile jpeg_decoder_status3_reg_t decoder_status3;
+    volatile jpeg_decoder_status4_reg_t decoder_status4;
+    volatile jpeg_decoder_status5_reg_t decoder_status5;
+    volatile jpeg_status5_reg_t status5;
+    volatile jpeg_eco_low_reg_t eco_low;
+    volatile jpeg_eco_high_reg_t eco_high;
+    uint32_t reserved_0ac[19];
+    volatile jpeg_sys_reg_t sys;
+    volatile jpeg_version_reg_t version;
+} jpeg_dev_t;
+
+extern jpeg_dev_t JPEG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(jpeg_dev_t) == 0x100, "Invalid size of jpeg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/jpeg_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/jpeg_reg.h
new file mode 100644
index 0000000000..17e1f4bee7
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/jpeg_reg.h
@@ -0,0 +1,1884 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** JPEG_CONFIG_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_CONFIG_REG (DR_REG_JPEG_BASE + 0x0)
+/** JPEG_FSM_RST : WT; bitpos: [0]; default: 0;
+ *  fsm reset
+ */
+#define JPEG_FSM_RST    (BIT(0))
+#define JPEG_FSM_RST_M  (JPEG_FSM_RST_V << JPEG_FSM_RST_S)
+#define JPEG_FSM_RST_V  0x00000001U
+#define JPEG_FSM_RST_S  0
+/** JPEG_JPEG_START : WT; bitpos: [1]; default: 0;
+ *  start to compress a new pic(in dma reg mode)
+ */
+#define JPEG_JPEG_START    (BIT(1))
+#define JPEG_JPEG_START_M  (JPEG_JPEG_START_V << JPEG_JPEG_START_S)
+#define JPEG_JPEG_START_V  0x00000001U
+#define JPEG_JPEG_START_S  1
+/** JPEG_QNR_PRECISION : R/W; bitpos: [2]; default: 0;
+ *  0:8bit qnr,1:12bit qnr(TBD)
+ */
+#define JPEG_QNR_PRECISION    (BIT(2))
+#define JPEG_QNR_PRECISION_M  (JPEG_QNR_PRECISION_V << JPEG_QNR_PRECISION_S)
+#define JPEG_QNR_PRECISION_V  0x00000001U
+#define JPEG_QNR_PRECISION_S  2
+/** JPEG_FF_CHECK_EN : R/W; bitpos: [3]; default: 1;
+ *  enable whether to add '00' after 'ff'
+ */
+#define JPEG_FF_CHECK_EN    (BIT(3))
+#define JPEG_FF_CHECK_EN_M  (JPEG_FF_CHECK_EN_V << JPEG_FF_CHECK_EN_S)
+#define JPEG_FF_CHECK_EN_V  0x00000001U
+#define JPEG_FF_CHECK_EN_S  3
+/** JPEG_SAMPLE_SEL : R/W; bitpos: [5:4]; default: 1;
+ *  0:yuv444,1:yuv422, 2:yuv420
+ */
+#define JPEG_SAMPLE_SEL    0x00000003U
+#define JPEG_SAMPLE_SEL_M  (JPEG_SAMPLE_SEL_V << JPEG_SAMPLE_SEL_S)
+#define JPEG_SAMPLE_SEL_V  0x00000003U
+#define JPEG_SAMPLE_SEL_S  4
+/** JPEG_DMA_LINKLIST_MODE : RO; bitpos: [6]; default: 1;
+ *  1:use linklist to configure dma
+ */
+#define JPEG_DMA_LINKLIST_MODE    (BIT(6))
+#define JPEG_DMA_LINKLIST_MODE_M  (JPEG_DMA_LINKLIST_MODE_V << JPEG_DMA_LINKLIST_MODE_S)
+#define JPEG_DMA_LINKLIST_MODE_V  0x00000001U
+#define JPEG_DMA_LINKLIST_MODE_S  6
+/** JPEG_DEBUG_DIRECT_OUT_EN : R/W; bitpos: [7]; default: 0;
+ *  0:normal mode,1:debug mode for direct output from input
+ */
+#define JPEG_DEBUG_DIRECT_OUT_EN    (BIT(7))
+#define JPEG_DEBUG_DIRECT_OUT_EN_M  (JPEG_DEBUG_DIRECT_OUT_EN_V << JPEG_DEBUG_DIRECT_OUT_EN_S)
+#define JPEG_DEBUG_DIRECT_OUT_EN_V  0x00000001U
+#define JPEG_DEBUG_DIRECT_OUT_EN_S  7
+/** JPEG_QNR_FIFO_EN : R/W; bitpos: [8]; default: 1;
+ *  0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram
+ */
+#define JPEG_QNR_FIFO_EN    (BIT(8))
+#define JPEG_QNR_FIFO_EN_M  (JPEG_QNR_FIFO_EN_V << JPEG_QNR_FIFO_EN_S)
+#define JPEG_QNR_FIFO_EN_V  0x00000001U
+#define JPEG_QNR_FIFO_EN_S  8
+/** JPEG_LQNR_TBL_SEL : R/W; bitpos: [10:9]; default: 0;
+ *  choose  luminance quntization table id(TBD)
+ */
+#define JPEG_LQNR_TBL_SEL    0x00000003U
+#define JPEG_LQNR_TBL_SEL_M  (JPEG_LQNR_TBL_SEL_V << JPEG_LQNR_TBL_SEL_S)
+#define JPEG_LQNR_TBL_SEL_V  0x00000003U
+#define JPEG_LQNR_TBL_SEL_S  9
+/** JPEG_CQNR_TBL_SEL : R/W; bitpos: [12:11]; default: 1;
+ *  choose  chrominance quntization table id (TBD)
+ */
+#define JPEG_CQNR_TBL_SEL    0x00000003U
+#define JPEG_CQNR_TBL_SEL_M  (JPEG_CQNR_TBL_SEL_V << JPEG_CQNR_TBL_SEL_S)
+#define JPEG_CQNR_TBL_SEL_V  0x00000003U
+#define JPEG_CQNR_TBL_SEL_S  11
+/** JPEG_COLOR_SPACE : R/W; bitpos: [14:13]; default: 0;
+ *  configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray
+ */
+#define JPEG_COLOR_SPACE    0x00000003U
+#define JPEG_COLOR_SPACE_M  (JPEG_COLOR_SPACE_V << JPEG_COLOR_SPACE_S)
+#define JPEG_COLOR_SPACE_V  0x00000003U
+#define JPEG_COLOR_SPACE_S  13
+/** JPEG_DHT_FIFO_EN : R/W; bitpos: [15]; default: 1;
+ *  0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to
+ *  write dht len_total/codemin/value table. Reading dht len_total/codemin/value table
+ *  only has nonfifo way
+ */
+#define JPEG_DHT_FIFO_EN    (BIT(15))
+#define JPEG_DHT_FIFO_EN_M  (JPEG_DHT_FIFO_EN_V << JPEG_DHT_FIFO_EN_S)
+#define JPEG_DHT_FIFO_EN_V  0x00000001U
+#define JPEG_DHT_FIFO_EN_S  15
+/** JPEG_MEM_CLK_FORCE_ON : R/W; bitpos: [16]; default: 0;
+ *  force memory's clock enabled
+ */
+#define JPEG_MEM_CLK_FORCE_ON    (BIT(16))
+#define JPEG_MEM_CLK_FORCE_ON_M  (JPEG_MEM_CLK_FORCE_ON_V << JPEG_MEM_CLK_FORCE_ON_S)
+#define JPEG_MEM_CLK_FORCE_ON_V  0x00000001U
+#define JPEG_MEM_CLK_FORCE_ON_S  16
+/** JPEG_DECODE_TIMEOUT_THRES : R/W; bitpos: [22:17]; default: 32;
+ *  decode pause period to trigger decode_timeout int, the timeout periods =2 power
+ *  (reg_decode_timeout_thres) -1
+ */
+#define JPEG_DECODE_TIMEOUT_THRES    0x0000003FU
+#define JPEG_DECODE_TIMEOUT_THRES_M  (JPEG_DECODE_TIMEOUT_THRES_V << JPEG_DECODE_TIMEOUT_THRES_S)
+#define JPEG_DECODE_TIMEOUT_THRES_V  0x0000003FU
+#define JPEG_DECODE_TIMEOUT_THRES_S  17
+/** JPEG_DECODE_TIMEOUT_TASK_SEL : R/W; bitpos: [23]; default: 0;
+ *  0: software use reset to abort decode process ,1: decoder abort decode process by
+ *  itself
+ */
+#define JPEG_DECODE_TIMEOUT_TASK_SEL    (BIT(23))
+#define JPEG_DECODE_TIMEOUT_TASK_SEL_M  (JPEG_DECODE_TIMEOUT_TASK_SEL_V << JPEG_DECODE_TIMEOUT_TASK_SEL_S)
+#define JPEG_DECODE_TIMEOUT_TASK_SEL_V  0x00000001U
+#define JPEG_DECODE_TIMEOUT_TASK_SEL_S  23
+/** JPEG_SOFT_RST : R/W; bitpos: [24]; default: 0;
+ *  when set to 1, soft reset JPEG module except jpeg_reg module
+ */
+#define JPEG_SOFT_RST    (BIT(24))
+#define JPEG_SOFT_RST_M  (JPEG_SOFT_RST_V << JPEG_SOFT_RST_S)
+#define JPEG_SOFT_RST_V  0x00000001U
+#define JPEG_SOFT_RST_S  24
+/** JPEG_FIFO_RST : R/W; bitpos: [25]; default: 0;
+ *  fifo reset
+ */
+#define JPEG_FIFO_RST    (BIT(25))
+#define JPEG_FIFO_RST_M  (JPEG_FIFO_RST_V << JPEG_FIFO_RST_S)
+#define JPEG_FIFO_RST_V  0x00000001U
+#define JPEG_FIFO_RST_S  25
+/** JPEG_PIXEL_REV : R/W; bitpos: [26]; default: 0;
+ *  reverse the source color pixel
+ */
+#define JPEG_PIXEL_REV    (BIT(26))
+#define JPEG_PIXEL_REV_M  (JPEG_PIXEL_REV_V << JPEG_PIXEL_REV_S)
+#define JPEG_PIXEL_REV_V  0x00000001U
+#define JPEG_PIXEL_REV_S  26
+/** JPEG_TAILER_EN : R/W; bitpos: [27]; default: 0;
+ *  set this bit to add EOI of '0xffd9' at the end of bitstream
+ */
+#define JPEG_TAILER_EN    (BIT(27))
+#define JPEG_TAILER_EN_M  (JPEG_TAILER_EN_V << JPEG_TAILER_EN_S)
+#define JPEG_TAILER_EN_V  0x00000001U
+#define JPEG_TAILER_EN_S  27
+/** JPEG_PAUSE_EN : R/W; bitpos: [28]; default: 0;
+ *  set this bit to pause jpeg encoding
+ */
+#define JPEG_PAUSE_EN    (BIT(28))
+#define JPEG_PAUSE_EN_M  (JPEG_PAUSE_EN_V << JPEG_PAUSE_EN_S)
+#define JPEG_PAUSE_EN_V  0x00000001U
+#define JPEG_PAUSE_EN_S  28
+/** JPEG_MEM_FORCE_PD : R/W; bitpos: [29]; default: 0;
+ *  0: no operation,1:force jpeg memory to power down
+ */
+#define JPEG_MEM_FORCE_PD    (BIT(29))
+#define JPEG_MEM_FORCE_PD_M  (JPEG_MEM_FORCE_PD_V << JPEG_MEM_FORCE_PD_S)
+#define JPEG_MEM_FORCE_PD_V  0x00000001U
+#define JPEG_MEM_FORCE_PD_S  29
+/** JPEG_MEM_FORCE_PU : R/W; bitpos: [30]; default: 0;
+ *  0: no operation,1:force jpeg memory to power up
+ */
+#define JPEG_MEM_FORCE_PU    (BIT(30))
+#define JPEG_MEM_FORCE_PU_M  (JPEG_MEM_FORCE_PU_V << JPEG_MEM_FORCE_PU_S)
+#define JPEG_MEM_FORCE_PU_V  0x00000001U
+#define JPEG_MEM_FORCE_PU_S  30
+/** JPEG_MODE : R/W; bitpos: [31]; default: 0;
+ *  0:encoder mode, 1: decoder mode
+ */
+#define JPEG_MODE    (BIT(31))
+#define JPEG_MODE_M  (JPEG_MODE_V << JPEG_MODE_S)
+#define JPEG_MODE_V  0x00000001U
+#define JPEG_MODE_S  31
+
+/** JPEG_DQT_INFO_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_DQT_INFO_REG (DR_REG_JPEG_BASE + 0x4)
+/** JPEG_T0_DQT_INFO : R/W; bitpos: [7:0]; default: 0;
+ *  Configure dqt table0's quantization coefficient precision in bit[7:4], configure
+ *  dqt table0's table id in bit[3:0]
+ */
+#define JPEG_T0_DQT_INFO    0x000000FFU
+#define JPEG_T0_DQT_INFO_M  (JPEG_T0_DQT_INFO_V << JPEG_T0_DQT_INFO_S)
+#define JPEG_T0_DQT_INFO_V  0x000000FFU
+#define JPEG_T0_DQT_INFO_S  0
+/** JPEG_T1_DQT_INFO : R/W; bitpos: [15:8]; default: 1;
+ *  Configure dqt table1's quantization coefficient precision in bit[7:4], configure
+ *  dqt table1's table id in bit[3:0]
+ */
+#define JPEG_T1_DQT_INFO    0x000000FFU
+#define JPEG_T1_DQT_INFO_M  (JPEG_T1_DQT_INFO_V << JPEG_T1_DQT_INFO_S)
+#define JPEG_T1_DQT_INFO_V  0x000000FFU
+#define JPEG_T1_DQT_INFO_S  8
+/** JPEG_T2_DQT_INFO : R/W; bitpos: [23:16]; default: 2;
+ *  Configure dqt table2's quantization coefficient precision in bit[7:4], configure
+ *  dqt table2's table id in bit[3:0]
+ */
+#define JPEG_T2_DQT_INFO    0x000000FFU
+#define JPEG_T2_DQT_INFO_M  (JPEG_T2_DQT_INFO_V << JPEG_T2_DQT_INFO_S)
+#define JPEG_T2_DQT_INFO_V  0x000000FFU
+#define JPEG_T2_DQT_INFO_S  16
+/** JPEG_T3_DQT_INFO : R/W; bitpos: [31:24]; default: 3;
+ *  Configure dqt table3's quantization coefficient precision in bit[7:4], configure
+ *  dqt table3's table id in bit[3:0]
+ */
+#define JPEG_T3_DQT_INFO    0x000000FFU
+#define JPEG_T3_DQT_INFO_M  (JPEG_T3_DQT_INFO_V << JPEG_T3_DQT_INFO_S)
+#define JPEG_T3_DQT_INFO_V  0x000000FFU
+#define JPEG_T3_DQT_INFO_S  24
+
+/** JPEG_PIC_SIZE_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_PIC_SIZE_REG (DR_REG_JPEG_BASE + 0x8)
+/** JPEG_VA : R/W; bitpos: [15:0]; default: 480;
+ *  configure picture's height. when encode, the max configurable bits is 14, when
+ *  decode, the max configurable bits is 16
+ */
+#define JPEG_VA    0x0000FFFFU
+#define JPEG_VA_M  (JPEG_VA_V << JPEG_VA_S)
+#define JPEG_VA_V  0x0000FFFFU
+#define JPEG_VA_S  0
+/** JPEG_HA : R/W; bitpos: [31:16]; default: 640;
+ *  configure picture's width. when encode, the max configurable bits is 14, when
+ *  decode, the max configurable bits is 16
+ */
+#define JPEG_HA    0x0000FFFFU
+#define JPEG_HA_M  (JPEG_HA_V << JPEG_HA_S)
+#define JPEG_HA_V  0x0000FFFFU
+#define JPEG_HA_S  16
+
+/** JPEG_EXTD_CONFIG_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_EXTD_CONFIG_REG (DR_REG_JPEG_BASE + 0xc)
+/** JPEG_EXTD_COLOR_SPACE_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether to extend picture's color space
+ *  0:disable
+ *  1:enable
+ */
+#define JPEG_EXTD_COLOR_SPACE_EN    (BIT(0))
+#define JPEG_EXTD_COLOR_SPACE_EN_M  (JPEG_EXTD_COLOR_SPACE_EN_V << JPEG_EXTD_COLOR_SPACE_EN_S)
+#define JPEG_EXTD_COLOR_SPACE_EN_V  0x00000001U
+#define JPEG_EXTD_COLOR_SPACE_EN_S  0
+/** JPEG_EXTD_COLOR_SPACE : R/W; bitpos: [1]; default: 0;
+ *  Configure extended picture's color space. Valid when JPEG_EXTD_COLOR_SPACE_EN
+ *  configured to 1
+ *  0:yuv444
+ *  1:yuv420
+ */
+#define JPEG_EXTD_COLOR_SPACE    (BIT(1))
+#define JPEG_EXTD_COLOR_SPACE_M  (JPEG_EXTD_COLOR_SPACE_V << JPEG_EXTD_COLOR_SPACE_S)
+#define JPEG_EXTD_COLOR_SPACE_V  0x00000001U
+#define JPEG_EXTD_COLOR_SPACE_S  1
+
+/** JPEG_T0QNR_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_T0QNR_REG (DR_REG_JPEG_BASE + 0x10)
+/** JPEG_T0_QNR_VAL : HRO; bitpos: [31:0]; default: 0;
+ *  write this reg to configure 64 quantization coefficient in t0 table
+ */
+#define JPEG_T0_QNR_VAL    0xFFFFFFFFU
+#define JPEG_T0_QNR_VAL_M  (JPEG_T0_QNR_VAL_V << JPEG_T0_QNR_VAL_S)
+#define JPEG_T0_QNR_VAL_V  0xFFFFFFFFU
+#define JPEG_T0_QNR_VAL_S  0
+
+/** JPEG_T1QNR_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_T1QNR_REG (DR_REG_JPEG_BASE + 0x14)
+/** JPEG_T1_QNR_VAL : HRO; bitpos: [31:0]; default: 0;
+ *  write this reg to configure 64 quantization coefficient in t1 table
+ */
+#define JPEG_T1_QNR_VAL    0xFFFFFFFFU
+#define JPEG_T1_QNR_VAL_M  (JPEG_T1_QNR_VAL_V << JPEG_T1_QNR_VAL_S)
+#define JPEG_T1_QNR_VAL_V  0xFFFFFFFFU
+#define JPEG_T1_QNR_VAL_S  0
+
+/** JPEG_T2QNR_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_T2QNR_REG (DR_REG_JPEG_BASE + 0x18)
+/** JPEG_T2_QNR_VAL : HRO; bitpos: [31:0]; default: 0;
+ *  write this reg to configure 64 quantization coefficient in t2 table
+ */
+#define JPEG_T2_QNR_VAL    0xFFFFFFFFU
+#define JPEG_T2_QNR_VAL_M  (JPEG_T2_QNR_VAL_V << JPEG_T2_QNR_VAL_S)
+#define JPEG_T2_QNR_VAL_V  0xFFFFFFFFU
+#define JPEG_T2_QNR_VAL_S  0
+
+/** JPEG_T3QNR_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_T3QNR_REG (DR_REG_JPEG_BASE + 0x1c)
+/** JPEG_T3_QNR_VAL : HRO; bitpos: [31:0]; default: 0;
+ *  write this reg to configure 64 quantization coefficient in t3 table
+ */
+#define JPEG_T3_QNR_VAL    0xFFFFFFFFU
+#define JPEG_T3_QNR_VAL_M  (JPEG_T3_QNR_VAL_V << JPEG_T3_QNR_VAL_S)
+#define JPEG_T3_QNR_VAL_V  0xFFFFFFFFU
+#define JPEG_T3_QNR_VAL_S  0
+
+/** JPEG_DECODE_CONF_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_DECODE_CONF_REG (DR_REG_JPEG_BASE + 0x20)
+/** JPEG_RESTART_INTERVAL : R/W; bitpos: [15:0]; default: 0;
+ *  configure restart interval in DRI marker when decode
+ */
+#define JPEG_RESTART_INTERVAL    0x0000FFFFU
+#define JPEG_RESTART_INTERVAL_M  (JPEG_RESTART_INTERVAL_V << JPEG_RESTART_INTERVAL_S)
+#define JPEG_RESTART_INTERVAL_V  0x0000FFFFU
+#define JPEG_RESTART_INTERVAL_S  0
+/** JPEG_COMPONENT_NUM : R/W; bitpos: [23:16]; default: 3;
+ *  configure number of components in frame when decode
+ */
+#define JPEG_COMPONENT_NUM    0x000000FFU
+#define JPEG_COMPONENT_NUM_M  (JPEG_COMPONENT_NUM_V << JPEG_COMPONENT_NUM_S)
+#define JPEG_COMPONENT_NUM_V  0x000000FFU
+#define JPEG_COMPONENT_NUM_S  16
+/** JPEG_SW_DHT_EN : RO; bitpos: [24]; default: 1;
+ *  software decode dht table enable
+ */
+#define JPEG_SW_DHT_EN    (BIT(24))
+#define JPEG_SW_DHT_EN_M  (JPEG_SW_DHT_EN_V << JPEG_SW_DHT_EN_S)
+#define JPEG_SW_DHT_EN_V  0x00000001U
+#define JPEG_SW_DHT_EN_S  24
+/** JPEG_SOS_CHECK_BYTE_NUM : R/W; bitpos: [26:25]; default: 3;
+ *  Configure the byte number to check next sos marker in the multi-scan picture after
+ *  one scan is decoded down. The real check number is reg_sos_check_byte_num+1
+ */
+#define JPEG_SOS_CHECK_BYTE_NUM    0x00000003U
+#define JPEG_SOS_CHECK_BYTE_NUM_M  (JPEG_SOS_CHECK_BYTE_NUM_V << JPEG_SOS_CHECK_BYTE_NUM_S)
+#define JPEG_SOS_CHECK_BYTE_NUM_V  0x00000003U
+#define JPEG_SOS_CHECK_BYTE_NUM_S  25
+/** JPEG_RST_CHECK_BYTE_NUM : R/W; bitpos: [28:27]; default: 3;
+ *  Configure the byte number to check next rst marker after one rst interval is
+ *  decoded down. The real check number is reg_rst_check_byte_num+1
+ */
+#define JPEG_RST_CHECK_BYTE_NUM    0x00000003U
+#define JPEG_RST_CHECK_BYTE_NUM_M  (JPEG_RST_CHECK_BYTE_NUM_V << JPEG_RST_CHECK_BYTE_NUM_S)
+#define JPEG_RST_CHECK_BYTE_NUM_V  0x00000003U
+#define JPEG_RST_CHECK_BYTE_NUM_S  27
+/** JPEG_MULTI_SCAN_ERR_CHECK : R/W; bitpos: [29]; default: 0;
+ *  reserved for decoder
+ */
+#define JPEG_MULTI_SCAN_ERR_CHECK    (BIT(29))
+#define JPEG_MULTI_SCAN_ERR_CHECK_M  (JPEG_MULTI_SCAN_ERR_CHECK_V << JPEG_MULTI_SCAN_ERR_CHECK_S)
+#define JPEG_MULTI_SCAN_ERR_CHECK_V  0x00000001U
+#define JPEG_MULTI_SCAN_ERR_CHECK_S  29
+/** JPEG_DEZIGZAG_READY_CTL : R/W; bitpos: [30]; default: 1;
+ *  reserved for decoder
+ */
+#define JPEG_DEZIGZAG_READY_CTL    (BIT(30))
+#define JPEG_DEZIGZAG_READY_CTL_M  (JPEG_DEZIGZAG_READY_CTL_V << JPEG_DEZIGZAG_READY_CTL_S)
+#define JPEG_DEZIGZAG_READY_CTL_V  0x00000001U
+#define JPEG_DEZIGZAG_READY_CTL_S  30
+
+/** JPEG_C0_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_C0_REG (DR_REG_JPEG_BASE + 0x24)
+/** JPEG_C0_DQT_TBL_SEL : R/W; bitpos: [7:0]; default: 0;
+ *  choose  c0 quntization table id (TBD)
+ */
+#define JPEG_C0_DQT_TBL_SEL    0x000000FFU
+#define JPEG_C0_DQT_TBL_SEL_M  (JPEG_C0_DQT_TBL_SEL_V << JPEG_C0_DQT_TBL_SEL_S)
+#define JPEG_C0_DQT_TBL_SEL_V  0x000000FFU
+#define JPEG_C0_DQT_TBL_SEL_S  0
+/** JPEG_C0_Y_FACTOR : R/W; bitpos: [11:8]; default: 1;
+ *  vertical sampling factor of c0
+ */
+#define JPEG_C0_Y_FACTOR    0x0000000FU
+#define JPEG_C0_Y_FACTOR_M  (JPEG_C0_Y_FACTOR_V << JPEG_C0_Y_FACTOR_S)
+#define JPEG_C0_Y_FACTOR_V  0x0000000FU
+#define JPEG_C0_Y_FACTOR_S  8
+/** JPEG_C0_X_FACTOR : R/W; bitpos: [15:12]; default: 1;
+ *  horizontal sampling factor of c0
+ */
+#define JPEG_C0_X_FACTOR    0x0000000FU
+#define JPEG_C0_X_FACTOR_M  (JPEG_C0_X_FACTOR_V << JPEG_C0_X_FACTOR_S)
+#define JPEG_C0_X_FACTOR_V  0x0000000FU
+#define JPEG_C0_X_FACTOR_S  12
+/** JPEG_C0_ID : R/W; bitpos: [23:16]; default: 0;
+ *  the identifier of c0
+ */
+#define JPEG_C0_ID    0x000000FFU
+#define JPEG_C0_ID_M  (JPEG_C0_ID_V << JPEG_C0_ID_S)
+#define JPEG_C0_ID_V  0x000000FFU
+#define JPEG_C0_ID_S  16
+
+/** JPEG_C1_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_C1_REG (DR_REG_JPEG_BASE + 0x28)
+/** JPEG_C1_DQT_TBL_SEL : R/W; bitpos: [7:0]; default: 0;
+ *  choose  c1 quntization table id (TBD)
+ */
+#define JPEG_C1_DQT_TBL_SEL    0x000000FFU
+#define JPEG_C1_DQT_TBL_SEL_M  (JPEG_C1_DQT_TBL_SEL_V << JPEG_C1_DQT_TBL_SEL_S)
+#define JPEG_C1_DQT_TBL_SEL_V  0x000000FFU
+#define JPEG_C1_DQT_TBL_SEL_S  0
+/** JPEG_C1_Y_FACTOR : R/W; bitpos: [11:8]; default: 1;
+ *  vertical sampling factor of c1
+ */
+#define JPEG_C1_Y_FACTOR    0x0000000FU
+#define JPEG_C1_Y_FACTOR_M  (JPEG_C1_Y_FACTOR_V << JPEG_C1_Y_FACTOR_S)
+#define JPEG_C1_Y_FACTOR_V  0x0000000FU
+#define JPEG_C1_Y_FACTOR_S  8
+/** JPEG_C1_X_FACTOR : R/W; bitpos: [15:12]; default: 1;
+ *  horizontal sampling factor of c1
+ */
+#define JPEG_C1_X_FACTOR    0x0000000FU
+#define JPEG_C1_X_FACTOR_M  (JPEG_C1_X_FACTOR_V << JPEG_C1_X_FACTOR_S)
+#define JPEG_C1_X_FACTOR_V  0x0000000FU
+#define JPEG_C1_X_FACTOR_S  12
+/** JPEG_C1_ID : R/W; bitpos: [23:16]; default: 0;
+ *  the identifier of c1
+ */
+#define JPEG_C1_ID    0x000000FFU
+#define JPEG_C1_ID_M  (JPEG_C1_ID_V << JPEG_C1_ID_S)
+#define JPEG_C1_ID_V  0x000000FFU
+#define JPEG_C1_ID_S  16
+
+/** JPEG_C2_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_C2_REG (DR_REG_JPEG_BASE + 0x2c)
+/** JPEG_C2_DQT_TBL_SEL : R/W; bitpos: [7:0]; default: 0;
+ *  choose  c2 quntization table id (TBD)
+ */
+#define JPEG_C2_DQT_TBL_SEL    0x000000FFU
+#define JPEG_C2_DQT_TBL_SEL_M  (JPEG_C2_DQT_TBL_SEL_V << JPEG_C2_DQT_TBL_SEL_S)
+#define JPEG_C2_DQT_TBL_SEL_V  0x000000FFU
+#define JPEG_C2_DQT_TBL_SEL_S  0
+/** JPEG_C2_Y_FACTOR : R/W; bitpos: [11:8]; default: 1;
+ *  vertical sampling factor of c2
+ */
+#define JPEG_C2_Y_FACTOR    0x0000000FU
+#define JPEG_C2_Y_FACTOR_M  (JPEG_C2_Y_FACTOR_V << JPEG_C2_Y_FACTOR_S)
+#define JPEG_C2_Y_FACTOR_V  0x0000000FU
+#define JPEG_C2_Y_FACTOR_S  8
+/** JPEG_C2_X_FACTOR : R/W; bitpos: [15:12]; default: 1;
+ *  horizontal sampling factor of c2
+ */
+#define JPEG_C2_X_FACTOR    0x0000000FU
+#define JPEG_C2_X_FACTOR_M  (JPEG_C2_X_FACTOR_V << JPEG_C2_X_FACTOR_S)
+#define JPEG_C2_X_FACTOR_V  0x0000000FU
+#define JPEG_C2_X_FACTOR_S  12
+/** JPEG_C2_ID : R/W; bitpos: [23:16]; default: 0;
+ *  the identifier of c2
+ */
+#define JPEG_C2_ID    0x000000FFU
+#define JPEG_C2_ID_M  (JPEG_C2_ID_V << JPEG_C2_ID_S)
+#define JPEG_C2_ID_V  0x000000FFU
+#define JPEG_C2_ID_S  16
+
+/** JPEG_C3_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_C3_REG (DR_REG_JPEG_BASE + 0x30)
+/** JPEG_C3_DQT_TBL_SEL : R/W; bitpos: [7:0]; default: 0;
+ *  choose  c3 quntization table id (TBD)
+ */
+#define JPEG_C3_DQT_TBL_SEL    0x000000FFU
+#define JPEG_C3_DQT_TBL_SEL_M  (JPEG_C3_DQT_TBL_SEL_V << JPEG_C3_DQT_TBL_SEL_S)
+#define JPEG_C3_DQT_TBL_SEL_V  0x000000FFU
+#define JPEG_C3_DQT_TBL_SEL_S  0
+/** JPEG_C3_Y_FACTOR : R/W; bitpos: [11:8]; default: 1;
+ *  vertical sampling factor of c3
+ */
+#define JPEG_C3_Y_FACTOR    0x0000000FU
+#define JPEG_C3_Y_FACTOR_M  (JPEG_C3_Y_FACTOR_V << JPEG_C3_Y_FACTOR_S)
+#define JPEG_C3_Y_FACTOR_V  0x0000000FU
+#define JPEG_C3_Y_FACTOR_S  8
+/** JPEG_C3_X_FACTOR : R/W; bitpos: [15:12]; default: 1;
+ *  horizontal sampling factor of c3
+ */
+#define JPEG_C3_X_FACTOR    0x0000000FU
+#define JPEG_C3_X_FACTOR_M  (JPEG_C3_X_FACTOR_V << JPEG_C3_X_FACTOR_S)
+#define JPEG_C3_X_FACTOR_V  0x0000000FU
+#define JPEG_C3_X_FACTOR_S  12
+/** JPEG_C3_ID : R/W; bitpos: [23:16]; default: 0;
+ *  the identifier of c3
+ */
+#define JPEG_C3_ID    0x000000FFU
+#define JPEG_C3_ID_M  (JPEG_C3_ID_V << JPEG_C3_ID_S)
+#define JPEG_C3_ID_V  0x000000FFU
+#define JPEG_C3_ID_S  16
+
+/** JPEG_DHT_INFO_REG register
+ *  Control and configuration registers
+ */
+#define JPEG_DHT_INFO_REG (DR_REG_JPEG_BASE + 0x34)
+/** JPEG_DC0_DHT_ID : R/W; bitpos: [3:0]; default: 0;
+ *  configure dht dc table 0 id
+ */
+#define JPEG_DC0_DHT_ID    0x0000000FU
+#define JPEG_DC0_DHT_ID_M  (JPEG_DC0_DHT_ID_V << JPEG_DC0_DHT_ID_S)
+#define JPEG_DC0_DHT_ID_V  0x0000000FU
+#define JPEG_DC0_DHT_ID_S  0
+/** JPEG_DC1_DHT_ID : R/W; bitpos: [7:4]; default: 1;
+ *  configure dht dc table 1 id
+ */
+#define JPEG_DC1_DHT_ID    0x0000000FU
+#define JPEG_DC1_DHT_ID_M  (JPEG_DC1_DHT_ID_V << JPEG_DC1_DHT_ID_S)
+#define JPEG_DC1_DHT_ID_V  0x0000000FU
+#define JPEG_DC1_DHT_ID_S  4
+/** JPEG_AC0_DHT_ID : R/W; bitpos: [11:8]; default: 0;
+ *  configure dht ac table 0 id
+ */
+#define JPEG_AC0_DHT_ID    0x0000000FU
+#define JPEG_AC0_DHT_ID_M  (JPEG_AC0_DHT_ID_V << JPEG_AC0_DHT_ID_S)
+#define JPEG_AC0_DHT_ID_V  0x0000000FU
+#define JPEG_AC0_DHT_ID_S  8
+/** JPEG_AC1_DHT_ID : R/W; bitpos: [15:12]; default: 1;
+ *  configure dht ac table 1 id
+ */
+#define JPEG_AC1_DHT_ID    0x0000000FU
+#define JPEG_AC1_DHT_ID_M  (JPEG_AC1_DHT_ID_V << JPEG_AC1_DHT_ID_S)
+#define JPEG_AC1_DHT_ID_V  0x0000000FU
+#define JPEG_AC1_DHT_ID_S  12
+
+/** JPEG_INT_RAW_REG register
+ *  Interrupt raw registers
+ */
+#define JPEG_INT_RAW_REG (DR_REG_JPEG_BASE + 0x38)
+/** JPEG_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This raw interrupt bit turns to high level when JPEG finishes encoding a picture..
+ */
+#define JPEG_DONE_INT_RAW    (BIT(0))
+#define JPEG_DONE_INT_RAW_M  (JPEG_DONE_INT_RAW_V << JPEG_DONE_INT_RAW_S)
+#define JPEG_DONE_INT_RAW_V  0x00000001U
+#define JPEG_DONE_INT_RAW_S  0
+/** JPEG_RLE_PARALLEL_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit to sign that rle parallel error when decoding.
+ */
+#define JPEG_RLE_PARALLEL_ERR_INT_RAW    (BIT(1))
+#define JPEG_RLE_PARALLEL_ERR_INT_RAW_M  (JPEG_RLE_PARALLEL_ERR_INT_RAW_V << JPEG_RLE_PARALLEL_ERR_INT_RAW_S)
+#define JPEG_RLE_PARALLEL_ERR_INT_RAW_V  0x00000001U
+#define JPEG_RLE_PARALLEL_ERR_INT_RAW_S  1
+/** JPEG_CID_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit to sign that scan id check with component fails when decoding.
+ */
+#define JPEG_CID_ERR_INT_RAW    (BIT(2))
+#define JPEG_CID_ERR_INT_RAW_M  (JPEG_CID_ERR_INT_RAW_V << JPEG_CID_ERR_INT_RAW_S)
+#define JPEG_CID_ERR_INT_RAW_V  0x00000001U
+#define JPEG_CID_ERR_INT_RAW_S  2
+/** JPEG_C_DHT_DC_ID_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit to sign that scan component's dc dht id check with dc dht
+ *  table's id fails when decoding.
+ */
+#define JPEG_C_DHT_DC_ID_ERR_INT_RAW    (BIT(3))
+#define JPEG_C_DHT_DC_ID_ERR_INT_RAW_M  (JPEG_C_DHT_DC_ID_ERR_INT_RAW_V << JPEG_C_DHT_DC_ID_ERR_INT_RAW_S)
+#define JPEG_C_DHT_DC_ID_ERR_INT_RAW_V  0x00000001U
+#define JPEG_C_DHT_DC_ID_ERR_INT_RAW_S  3
+/** JPEG_C_DHT_AC_ID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit to sign that scan component's ac dht id check with ac dht
+ *  table's id fails when decoding.
+ */
+#define JPEG_C_DHT_AC_ID_ERR_INT_RAW    (BIT(4))
+#define JPEG_C_DHT_AC_ID_ERR_INT_RAW_M  (JPEG_C_DHT_AC_ID_ERR_INT_RAW_V << JPEG_C_DHT_AC_ID_ERR_INT_RAW_S)
+#define JPEG_C_DHT_AC_ID_ERR_INT_RAW_V  0x00000001U
+#define JPEG_C_DHT_AC_ID_ERR_INT_RAW_S  4
+/** JPEG_C_DQT_ID_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit to sign that scan component's dqt id check with dqt table's
+ *  id fails when decoding.
+ */
+#define JPEG_C_DQT_ID_ERR_INT_RAW    (BIT(5))
+#define JPEG_C_DQT_ID_ERR_INT_RAW_M  (JPEG_C_DQT_ID_ERR_INT_RAW_V << JPEG_C_DQT_ID_ERR_INT_RAW_S)
+#define JPEG_C_DQT_ID_ERR_INT_RAW_V  0x00000001U
+#define JPEG_C_DQT_ID_ERR_INT_RAW_S  5
+/** JPEG_RST_UXP_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit to sign that RST header marker is detected but restart
+ *  interval is 0 when decoding.
+ */
+#define JPEG_RST_UXP_ERR_INT_RAW    (BIT(6))
+#define JPEG_RST_UXP_ERR_INT_RAW_M  (JPEG_RST_UXP_ERR_INT_RAW_V << JPEG_RST_UXP_ERR_INT_RAW_S)
+#define JPEG_RST_UXP_ERR_INT_RAW_V  0x00000001U
+#define JPEG_RST_UXP_ERR_INT_RAW_S  6
+/** JPEG_RST_CHECK_NONE_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit to sign that RST header marker is not detected but restart
+ *  interval is not 0 when decoding.
+ */
+#define JPEG_RST_CHECK_NONE_ERR_INT_RAW    (BIT(7))
+#define JPEG_RST_CHECK_NONE_ERR_INT_RAW_M  (JPEG_RST_CHECK_NONE_ERR_INT_RAW_V << JPEG_RST_CHECK_NONE_ERR_INT_RAW_S)
+#define JPEG_RST_CHECK_NONE_ERR_INT_RAW_V  0x00000001U
+#define JPEG_RST_CHECK_NONE_ERR_INT_RAW_S  7
+/** JPEG_RST_CHECK_POS_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit to sign that RST header marker position mismatches with
+ *  restart interval when decoding.
+ */
+#define JPEG_RST_CHECK_POS_ERR_INT_RAW    (BIT(8))
+#define JPEG_RST_CHECK_POS_ERR_INT_RAW_M  (JPEG_RST_CHECK_POS_ERR_INT_RAW_V << JPEG_RST_CHECK_POS_ERR_INT_RAW_S)
+#define JPEG_RST_CHECK_POS_ERR_INT_RAW_V  0x00000001U
+#define JPEG_RST_CHECK_POS_ERR_INT_RAW_S  8
+/** JPEG_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when the last pixel of one square has
+ *  been transmitted for Tx channel.
+ */
+#define JPEG_OUT_EOF_INT_RAW    (BIT(9))
+#define JPEG_OUT_EOF_INT_RAW_M  (JPEG_OUT_EOF_INT_RAW_V << JPEG_OUT_EOF_INT_RAW_S)
+#define JPEG_OUT_EOF_INT_RAW_V  0x00000001U
+#define JPEG_OUT_EOF_INT_RAW_S  9
+/** JPEG_SR_COLOR_MODE_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit to sign that the selected source color mode is not supported.
+ */
+#define JPEG_SR_COLOR_MODE_ERR_INT_RAW    (BIT(10))
+#define JPEG_SR_COLOR_MODE_ERR_INT_RAW_M  (JPEG_SR_COLOR_MODE_ERR_INT_RAW_V << JPEG_SR_COLOR_MODE_ERR_INT_RAW_S)
+#define JPEG_SR_COLOR_MODE_ERR_INT_RAW_V  0x00000001U
+#define JPEG_SR_COLOR_MODE_ERR_INT_RAW_S  10
+/** JPEG_DCT_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit to sign that one dct calculation is finished.
+ */
+#define JPEG_DCT_DONE_INT_RAW    (BIT(11))
+#define JPEG_DCT_DONE_INT_RAW_M  (JPEG_DCT_DONE_INT_RAW_V << JPEG_DCT_DONE_INT_RAW_S)
+#define JPEG_DCT_DONE_INT_RAW_V  0x00000001U
+#define JPEG_DCT_DONE_INT_RAW_S  11
+/** JPEG_BS_LAST_BLOCK_EOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit to sign that the coding process for last block is finished.
+ */
+#define JPEG_BS_LAST_BLOCK_EOF_INT_RAW    (BIT(12))
+#define JPEG_BS_LAST_BLOCK_EOF_INT_RAW_M  (JPEG_BS_LAST_BLOCK_EOF_INT_RAW_V << JPEG_BS_LAST_BLOCK_EOF_INT_RAW_S)
+#define JPEG_BS_LAST_BLOCK_EOF_INT_RAW_V  0x00000001U
+#define JPEG_BS_LAST_BLOCK_EOF_INT_RAW_S  12
+/** JPEG_SCAN_CHECK_NONE_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit to sign that SOS header marker is not detected but there are
+ *  still components left to be decoded.
+ */
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_RAW    (BIT(13))
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_RAW_M  (JPEG_SCAN_CHECK_NONE_ERR_INT_RAW_V << JPEG_SCAN_CHECK_NONE_ERR_INT_RAW_S)
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_RAW_V  0x00000001U
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_RAW_S  13
+/** JPEG_SCAN_CHECK_POS_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt bit to sign that SOS header marker position wrong when decoding.
+ */
+#define JPEG_SCAN_CHECK_POS_ERR_INT_RAW    (BIT(14))
+#define JPEG_SCAN_CHECK_POS_ERR_INT_RAW_M  (JPEG_SCAN_CHECK_POS_ERR_INT_RAW_V << JPEG_SCAN_CHECK_POS_ERR_INT_RAW_S)
+#define JPEG_SCAN_CHECK_POS_ERR_INT_RAW_V  0x00000001U
+#define JPEG_SCAN_CHECK_POS_ERR_INT_RAW_S  14
+/** JPEG_UXP_DET_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw interrupt bit to sign that unsupported header marker is detected when
+ *  decoding.
+ */
+#define JPEG_UXP_DET_INT_RAW    (BIT(15))
+#define JPEG_UXP_DET_INT_RAW_M  (JPEG_UXP_DET_INT_RAW_V << JPEG_UXP_DET_INT_RAW_S)
+#define JPEG_UXP_DET_INT_RAW_V  0x00000001U
+#define JPEG_UXP_DET_INT_RAW_S  15
+/** JPEG_EN_FRAME_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw interrupt bit to sign that received pixel blocks are smaller than expected
+ *  when encoding.
+ */
+#define JPEG_EN_FRAME_EOF_ERR_INT_RAW    (BIT(16))
+#define JPEG_EN_FRAME_EOF_ERR_INT_RAW_M  (JPEG_EN_FRAME_EOF_ERR_INT_RAW_V << JPEG_EN_FRAME_EOF_ERR_INT_RAW_S)
+#define JPEG_EN_FRAME_EOF_ERR_INT_RAW_V  0x00000001U
+#define JPEG_EN_FRAME_EOF_ERR_INT_RAW_S  16
+/** JPEG_EN_FRAME_EOF_LACK_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw interrupt bit to sign that the frame eof sign bit from dma input is missing
+ *  when encoding. But the number of pixel blocks is enough.
+ */
+#define JPEG_EN_FRAME_EOF_LACK_INT_RAW    (BIT(17))
+#define JPEG_EN_FRAME_EOF_LACK_INT_RAW_M  (JPEG_EN_FRAME_EOF_LACK_INT_RAW_V << JPEG_EN_FRAME_EOF_LACK_INT_RAW_S)
+#define JPEG_EN_FRAME_EOF_LACK_INT_RAW_V  0x00000001U
+#define JPEG_EN_FRAME_EOF_LACK_INT_RAW_S  17
+/** JPEG_DE_FRAME_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The raw interrupt bit to sign that decoded blocks are smaller than expected when
+ *  decoding.
+ */
+#define JPEG_DE_FRAME_EOF_ERR_INT_RAW    (BIT(18))
+#define JPEG_DE_FRAME_EOF_ERR_INT_RAW_M  (JPEG_DE_FRAME_EOF_ERR_INT_RAW_V << JPEG_DE_FRAME_EOF_ERR_INT_RAW_S)
+#define JPEG_DE_FRAME_EOF_ERR_INT_RAW_V  0x00000001U
+#define JPEG_DE_FRAME_EOF_ERR_INT_RAW_S  18
+/** JPEG_DE_FRAME_EOF_LACK_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw interrupt bit to sign that the either frame eof from dma input or eoi
+ *  marker is missing when encoding. But the number of decoded blocks is enough.
+ */
+#define JPEG_DE_FRAME_EOF_LACK_INT_RAW    (BIT(19))
+#define JPEG_DE_FRAME_EOF_LACK_INT_RAW_M  (JPEG_DE_FRAME_EOF_LACK_INT_RAW_V << JPEG_DE_FRAME_EOF_LACK_INT_RAW_S)
+#define JPEG_DE_FRAME_EOF_LACK_INT_RAW_V  0x00000001U
+#define JPEG_DE_FRAME_EOF_LACK_INT_RAW_S  19
+/** JPEG_SOS_UNMATCH_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw interrupt bit to sign that the component number of a scan is 0 or does not
+ *  match the sos marker's length when decoding.
+ */
+#define JPEG_SOS_UNMATCH_ERR_INT_RAW    (BIT(20))
+#define JPEG_SOS_UNMATCH_ERR_INT_RAW_M  (JPEG_SOS_UNMATCH_ERR_INT_RAW_V << JPEG_SOS_UNMATCH_ERR_INT_RAW_S)
+#define JPEG_SOS_UNMATCH_ERR_INT_RAW_V  0x00000001U
+#define JPEG_SOS_UNMATCH_ERR_INT_RAW_S  20
+/** JPEG_MARKER_ERR_FST_SCAN_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  The raw interrupt bit to sign that the first scan has header marker error when
+ *  decoding.
+ */
+#define JPEG_MARKER_ERR_FST_SCAN_INT_RAW    (BIT(21))
+#define JPEG_MARKER_ERR_FST_SCAN_INT_RAW_M  (JPEG_MARKER_ERR_FST_SCAN_INT_RAW_V << JPEG_MARKER_ERR_FST_SCAN_INT_RAW_S)
+#define JPEG_MARKER_ERR_FST_SCAN_INT_RAW_V  0x00000001U
+#define JPEG_MARKER_ERR_FST_SCAN_INT_RAW_S  21
+/** JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  The raw interrupt bit to sign that the following scans but not the first scan have
+ *  header marker error when decoding.
+ */
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW    (BIT(22))
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW_M  (JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW_V << JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW_S)
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW_V  0x00000001U
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW_S  22
+/** JPEG_UNDET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  The raw interrupt bit to sign that JPEG format is not detected at the eof data of a
+ *  packet when decoding.
+ */
+#define JPEG_UNDET_INT_RAW    (BIT(23))
+#define JPEG_UNDET_INT_RAW_M  (JPEG_UNDET_INT_RAW_V << JPEG_UNDET_INT_RAW_S)
+#define JPEG_UNDET_INT_RAW_V  0x00000001U
+#define JPEG_UNDET_INT_RAW_S  23
+/** JPEG_DECODE_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  The raw interrupt bit to sign that decode pause time is longer than the setting
+ *  decode timeout time when decoding.
+ */
+#define JPEG_DECODE_TIMEOUT_INT_RAW    (BIT(24))
+#define JPEG_DECODE_TIMEOUT_INT_RAW_M  (JPEG_DECODE_TIMEOUT_INT_RAW_V << JPEG_DECODE_TIMEOUT_INT_RAW_S)
+#define JPEG_DECODE_TIMEOUT_INT_RAW_V  0x00000001U
+#define JPEG_DECODE_TIMEOUT_INT_RAW_S  24
+
+/** JPEG_INT_ENA_REG register
+ *  Interrupt enable registers
+ */
+#define JPEG_INT_ENA_REG (DR_REG_JPEG_BASE + 0x3c)
+/** JPEG_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This enable interrupt bit turns to high level when JPEG finishes encoding a
+ *  picture..
+ */
+#define JPEG_DONE_INT_ENA    (BIT(0))
+#define JPEG_DONE_INT_ENA_M  (JPEG_DONE_INT_ENA_V << JPEG_DONE_INT_ENA_S)
+#define JPEG_DONE_INT_ENA_V  0x00000001U
+#define JPEG_DONE_INT_ENA_S  0
+/** JPEG_RLE_PARALLEL_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable interrupt bit to sign that rle parallel error when decoding.
+ */
+#define JPEG_RLE_PARALLEL_ERR_INT_ENA    (BIT(1))
+#define JPEG_RLE_PARALLEL_ERR_INT_ENA_M  (JPEG_RLE_PARALLEL_ERR_INT_ENA_V << JPEG_RLE_PARALLEL_ERR_INT_ENA_S)
+#define JPEG_RLE_PARALLEL_ERR_INT_ENA_V  0x00000001U
+#define JPEG_RLE_PARALLEL_ERR_INT_ENA_S  1
+/** JPEG_CID_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable interrupt bit to sign that scan id check with component fails when
+ *  decoding.
+ */
+#define JPEG_CID_ERR_INT_ENA    (BIT(2))
+#define JPEG_CID_ERR_INT_ENA_M  (JPEG_CID_ERR_INT_ENA_V << JPEG_CID_ERR_INT_ENA_S)
+#define JPEG_CID_ERR_INT_ENA_V  0x00000001U
+#define JPEG_CID_ERR_INT_ENA_S  2
+/** JPEG_C_DHT_DC_ID_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable interrupt bit to sign that scan component's dc dht id check with dc dht
+ *  table's id fails when decoding.
+ */
+#define JPEG_C_DHT_DC_ID_ERR_INT_ENA    (BIT(3))
+#define JPEG_C_DHT_DC_ID_ERR_INT_ENA_M  (JPEG_C_DHT_DC_ID_ERR_INT_ENA_V << JPEG_C_DHT_DC_ID_ERR_INT_ENA_S)
+#define JPEG_C_DHT_DC_ID_ERR_INT_ENA_V  0x00000001U
+#define JPEG_C_DHT_DC_ID_ERR_INT_ENA_S  3
+/** JPEG_C_DHT_AC_ID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable interrupt bit to sign that scan component's ac dht id check with ac dht
+ *  table's id fails when decoding.
+ */
+#define JPEG_C_DHT_AC_ID_ERR_INT_ENA    (BIT(4))
+#define JPEG_C_DHT_AC_ID_ERR_INT_ENA_M  (JPEG_C_DHT_AC_ID_ERR_INT_ENA_V << JPEG_C_DHT_AC_ID_ERR_INT_ENA_S)
+#define JPEG_C_DHT_AC_ID_ERR_INT_ENA_V  0x00000001U
+#define JPEG_C_DHT_AC_ID_ERR_INT_ENA_S  4
+/** JPEG_C_DQT_ID_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The enable interrupt bit to sign that scan component's dqt id check with dqt
+ *  table's id fails when decoding.
+ */
+#define JPEG_C_DQT_ID_ERR_INT_ENA    (BIT(5))
+#define JPEG_C_DQT_ID_ERR_INT_ENA_M  (JPEG_C_DQT_ID_ERR_INT_ENA_V << JPEG_C_DQT_ID_ERR_INT_ENA_S)
+#define JPEG_C_DQT_ID_ERR_INT_ENA_V  0x00000001U
+#define JPEG_C_DQT_ID_ERR_INT_ENA_S  5
+/** JPEG_RST_UXP_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable interrupt bit to sign that RST header marker is detected but restart
+ *  interval is 0 when decoding.
+ */
+#define JPEG_RST_UXP_ERR_INT_ENA    (BIT(6))
+#define JPEG_RST_UXP_ERR_INT_ENA_M  (JPEG_RST_UXP_ERR_INT_ENA_V << JPEG_RST_UXP_ERR_INT_ENA_S)
+#define JPEG_RST_UXP_ERR_INT_ENA_V  0x00000001U
+#define JPEG_RST_UXP_ERR_INT_ENA_S  6
+/** JPEG_RST_CHECK_NONE_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable interrupt bit to sign that RST header marker is not detected but restart
+ *  interval is not 0 when decoding.
+ */
+#define JPEG_RST_CHECK_NONE_ERR_INT_ENA    (BIT(7))
+#define JPEG_RST_CHECK_NONE_ERR_INT_ENA_M  (JPEG_RST_CHECK_NONE_ERR_INT_ENA_V << JPEG_RST_CHECK_NONE_ERR_INT_ENA_S)
+#define JPEG_RST_CHECK_NONE_ERR_INT_ENA_V  0x00000001U
+#define JPEG_RST_CHECK_NONE_ERR_INT_ENA_S  7
+/** JPEG_RST_CHECK_POS_ERR_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The enable interrupt bit to sign that RST header marker position mismatches with
+ *  restart interval when decoding.
+ */
+#define JPEG_RST_CHECK_POS_ERR_INT_ENA    (BIT(8))
+#define JPEG_RST_CHECK_POS_ERR_INT_ENA_M  (JPEG_RST_CHECK_POS_ERR_INT_ENA_V << JPEG_RST_CHECK_POS_ERR_INT_ENA_S)
+#define JPEG_RST_CHECK_POS_ERR_INT_ENA_V  0x00000001U
+#define JPEG_RST_CHECK_POS_ERR_INT_ENA_S  8
+/** JPEG_OUT_EOF_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The enable interrupt bit turns to high level when the last pixel of one square has
+ *  been transmitted for Tx channel.
+ */
+#define JPEG_OUT_EOF_INT_ENA    (BIT(9))
+#define JPEG_OUT_EOF_INT_ENA_M  (JPEG_OUT_EOF_INT_ENA_V << JPEG_OUT_EOF_INT_ENA_S)
+#define JPEG_OUT_EOF_INT_ENA_V  0x00000001U
+#define JPEG_OUT_EOF_INT_ENA_S  9
+/** JPEG_SR_COLOR_MODE_ERR_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable interrupt bit to sign that the selected source color mode is not
+ *  supported.
+ */
+#define JPEG_SR_COLOR_MODE_ERR_INT_ENA    (BIT(10))
+#define JPEG_SR_COLOR_MODE_ERR_INT_ENA_M  (JPEG_SR_COLOR_MODE_ERR_INT_ENA_V << JPEG_SR_COLOR_MODE_ERR_INT_ENA_S)
+#define JPEG_SR_COLOR_MODE_ERR_INT_ENA_V  0x00000001U
+#define JPEG_SR_COLOR_MODE_ERR_INT_ENA_S  10
+/** JPEG_DCT_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The enable interrupt bit to sign that one dct calculation is finished.
+ */
+#define JPEG_DCT_DONE_INT_ENA    (BIT(11))
+#define JPEG_DCT_DONE_INT_ENA_M  (JPEG_DCT_DONE_INT_ENA_V << JPEG_DCT_DONE_INT_ENA_S)
+#define JPEG_DCT_DONE_INT_ENA_V  0x00000001U
+#define JPEG_DCT_DONE_INT_ENA_S  11
+/** JPEG_BS_LAST_BLOCK_EOF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The enable interrupt bit to sign that the coding process for last block is finished.
+ */
+#define JPEG_BS_LAST_BLOCK_EOF_INT_ENA    (BIT(12))
+#define JPEG_BS_LAST_BLOCK_EOF_INT_ENA_M  (JPEG_BS_LAST_BLOCK_EOF_INT_ENA_V << JPEG_BS_LAST_BLOCK_EOF_INT_ENA_S)
+#define JPEG_BS_LAST_BLOCK_EOF_INT_ENA_V  0x00000001U
+#define JPEG_BS_LAST_BLOCK_EOF_INT_ENA_S  12
+/** JPEG_SCAN_CHECK_NONE_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The enable interrupt bit to sign that SOS header marker is not detected but there
+ *  are still components left to be decoded.
+ */
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_ENA    (BIT(13))
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_ENA_M  (JPEG_SCAN_CHECK_NONE_ERR_INT_ENA_V << JPEG_SCAN_CHECK_NONE_ERR_INT_ENA_S)
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_ENA_V  0x00000001U
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_ENA_S  13
+/** JPEG_SCAN_CHECK_POS_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The enable interrupt bit to sign that SOS header marker position wrong when
+ *  decoding.
+ */
+#define JPEG_SCAN_CHECK_POS_ERR_INT_ENA    (BIT(14))
+#define JPEG_SCAN_CHECK_POS_ERR_INT_ENA_M  (JPEG_SCAN_CHECK_POS_ERR_INT_ENA_V << JPEG_SCAN_CHECK_POS_ERR_INT_ENA_S)
+#define JPEG_SCAN_CHECK_POS_ERR_INT_ENA_V  0x00000001U
+#define JPEG_SCAN_CHECK_POS_ERR_INT_ENA_S  14
+/** JPEG_UXP_DET_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The enable interrupt bit to sign that unsupported header marker is detected when
+ *  decoding.
+ */
+#define JPEG_UXP_DET_INT_ENA    (BIT(15))
+#define JPEG_UXP_DET_INT_ENA_M  (JPEG_UXP_DET_INT_ENA_V << JPEG_UXP_DET_INT_ENA_S)
+#define JPEG_UXP_DET_INT_ENA_V  0x00000001U
+#define JPEG_UXP_DET_INT_ENA_S  15
+/** JPEG_EN_FRAME_EOF_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The enable interrupt bit to sign that received pixel blocks are smaller than
+ *  expected when encoding.
+ */
+#define JPEG_EN_FRAME_EOF_ERR_INT_ENA    (BIT(16))
+#define JPEG_EN_FRAME_EOF_ERR_INT_ENA_M  (JPEG_EN_FRAME_EOF_ERR_INT_ENA_V << JPEG_EN_FRAME_EOF_ERR_INT_ENA_S)
+#define JPEG_EN_FRAME_EOF_ERR_INT_ENA_V  0x00000001U
+#define JPEG_EN_FRAME_EOF_ERR_INT_ENA_S  16
+/** JPEG_EN_FRAME_EOF_LACK_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The enable interrupt bit to sign that the frame eof sign bit from dma input is
+ *  missing when encoding. But the number of pixel blocks is enough.
+ */
+#define JPEG_EN_FRAME_EOF_LACK_INT_ENA    (BIT(17))
+#define JPEG_EN_FRAME_EOF_LACK_INT_ENA_M  (JPEG_EN_FRAME_EOF_LACK_INT_ENA_V << JPEG_EN_FRAME_EOF_LACK_INT_ENA_S)
+#define JPEG_EN_FRAME_EOF_LACK_INT_ENA_V  0x00000001U
+#define JPEG_EN_FRAME_EOF_LACK_INT_ENA_S  17
+/** JPEG_DE_FRAME_EOF_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  The enable interrupt bit to sign that decoded blocks are smaller than expected when
+ *  decoding.
+ */
+#define JPEG_DE_FRAME_EOF_ERR_INT_ENA    (BIT(18))
+#define JPEG_DE_FRAME_EOF_ERR_INT_ENA_M  (JPEG_DE_FRAME_EOF_ERR_INT_ENA_V << JPEG_DE_FRAME_EOF_ERR_INT_ENA_S)
+#define JPEG_DE_FRAME_EOF_ERR_INT_ENA_V  0x00000001U
+#define JPEG_DE_FRAME_EOF_ERR_INT_ENA_S  18
+/** JPEG_DE_FRAME_EOF_LACK_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  The enable interrupt bit to sign that the either frame eof from dma input or eoi
+ *  marker is missing when encoding. But the number of decoded blocks is enough.
+ */
+#define JPEG_DE_FRAME_EOF_LACK_INT_ENA    (BIT(19))
+#define JPEG_DE_FRAME_EOF_LACK_INT_ENA_M  (JPEG_DE_FRAME_EOF_LACK_INT_ENA_V << JPEG_DE_FRAME_EOF_LACK_INT_ENA_S)
+#define JPEG_DE_FRAME_EOF_LACK_INT_ENA_V  0x00000001U
+#define JPEG_DE_FRAME_EOF_LACK_INT_ENA_S  19
+/** JPEG_SOS_UNMATCH_ERR_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  The enable interrupt bit to sign that the component number of a scan is 0 or does
+ *  not match the sos marker's length when decoding.
+ */
+#define JPEG_SOS_UNMATCH_ERR_INT_ENA    (BIT(20))
+#define JPEG_SOS_UNMATCH_ERR_INT_ENA_M  (JPEG_SOS_UNMATCH_ERR_INT_ENA_V << JPEG_SOS_UNMATCH_ERR_INT_ENA_S)
+#define JPEG_SOS_UNMATCH_ERR_INT_ENA_V  0x00000001U
+#define JPEG_SOS_UNMATCH_ERR_INT_ENA_S  20
+/** JPEG_MARKER_ERR_FST_SCAN_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  The enable interrupt bit to sign that the first scan has header marker error when
+ *  decoding.
+ */
+#define JPEG_MARKER_ERR_FST_SCAN_INT_ENA    (BIT(21))
+#define JPEG_MARKER_ERR_FST_SCAN_INT_ENA_M  (JPEG_MARKER_ERR_FST_SCAN_INT_ENA_V << JPEG_MARKER_ERR_FST_SCAN_INT_ENA_S)
+#define JPEG_MARKER_ERR_FST_SCAN_INT_ENA_V  0x00000001U
+#define JPEG_MARKER_ERR_FST_SCAN_INT_ENA_S  21
+/** JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  The enable interrupt bit to sign that the following scans but not the first scan
+ *  have header marker error when decoding.
+ */
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA    (BIT(22))
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA_M  (JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA_V << JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA_S)
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA_V  0x00000001U
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA_S  22
+/** JPEG_UNDET_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  The enable interrupt bit to sign that JPEG format is not detected at the eof data
+ *  of a packet when decoding.
+ */
+#define JPEG_UNDET_INT_ENA    (BIT(23))
+#define JPEG_UNDET_INT_ENA_M  (JPEG_UNDET_INT_ENA_V << JPEG_UNDET_INT_ENA_S)
+#define JPEG_UNDET_INT_ENA_V  0x00000001U
+#define JPEG_UNDET_INT_ENA_S  23
+/** JPEG_DECODE_TIMEOUT_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  The enable interrupt bit to sign that decode pause time is longer than the setting
+ *  decode timeout time when decoding.
+ */
+#define JPEG_DECODE_TIMEOUT_INT_ENA    (BIT(24))
+#define JPEG_DECODE_TIMEOUT_INT_ENA_M  (JPEG_DECODE_TIMEOUT_INT_ENA_V << JPEG_DECODE_TIMEOUT_INT_ENA_S)
+#define JPEG_DECODE_TIMEOUT_INT_ENA_V  0x00000001U
+#define JPEG_DECODE_TIMEOUT_INT_ENA_S  24
+
+/** JPEG_INT_ST_REG register
+ *  Interrupt status registers
+ */
+#define JPEG_INT_ST_REG (DR_REG_JPEG_BASE + 0x40)
+/** JPEG_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This status interrupt bit turns to high level when JPEG finishes encoding a
+ *  picture..
+ */
+#define JPEG_DONE_INT_ST    (BIT(0))
+#define JPEG_DONE_INT_ST_M  (JPEG_DONE_INT_ST_V << JPEG_DONE_INT_ST_S)
+#define JPEG_DONE_INT_ST_V  0x00000001U
+#define JPEG_DONE_INT_ST_S  0
+/** JPEG_RLE_PARALLEL_ERR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status interrupt bit to sign that rle parallel error when decoding.
+ */
+#define JPEG_RLE_PARALLEL_ERR_INT_ST    (BIT(1))
+#define JPEG_RLE_PARALLEL_ERR_INT_ST_M  (JPEG_RLE_PARALLEL_ERR_INT_ST_V << JPEG_RLE_PARALLEL_ERR_INT_ST_S)
+#define JPEG_RLE_PARALLEL_ERR_INT_ST_V  0x00000001U
+#define JPEG_RLE_PARALLEL_ERR_INT_ST_S  1
+/** JPEG_CID_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status interrupt bit to sign that scan id check with component fails when
+ *  decoding.
+ */
+#define JPEG_CID_ERR_INT_ST    (BIT(2))
+#define JPEG_CID_ERR_INT_ST_M  (JPEG_CID_ERR_INT_ST_V << JPEG_CID_ERR_INT_ST_S)
+#define JPEG_CID_ERR_INT_ST_V  0x00000001U
+#define JPEG_CID_ERR_INT_ST_S  2
+/** JPEG_C_DHT_DC_ID_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status interrupt bit to sign that scan component's dc dht id check with dc dht
+ *  table's id fails when decoding.
+ */
+#define JPEG_C_DHT_DC_ID_ERR_INT_ST    (BIT(3))
+#define JPEG_C_DHT_DC_ID_ERR_INT_ST_M  (JPEG_C_DHT_DC_ID_ERR_INT_ST_V << JPEG_C_DHT_DC_ID_ERR_INT_ST_S)
+#define JPEG_C_DHT_DC_ID_ERR_INT_ST_V  0x00000001U
+#define JPEG_C_DHT_DC_ID_ERR_INT_ST_S  3
+/** JPEG_C_DHT_AC_ID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status interrupt bit to sign that scan component's ac dht id check with ac dht
+ *  table's id fails when decoding.
+ */
+#define JPEG_C_DHT_AC_ID_ERR_INT_ST    (BIT(4))
+#define JPEG_C_DHT_AC_ID_ERR_INT_ST_M  (JPEG_C_DHT_AC_ID_ERR_INT_ST_V << JPEG_C_DHT_AC_ID_ERR_INT_ST_S)
+#define JPEG_C_DHT_AC_ID_ERR_INT_ST_V  0x00000001U
+#define JPEG_C_DHT_AC_ID_ERR_INT_ST_S  4
+/** JPEG_C_DQT_ID_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The status interrupt bit to sign that scan component's dqt id check with dqt
+ *  table's id fails when decoding.
+ */
+#define JPEG_C_DQT_ID_ERR_INT_ST    (BIT(5))
+#define JPEG_C_DQT_ID_ERR_INT_ST_M  (JPEG_C_DQT_ID_ERR_INT_ST_V << JPEG_C_DQT_ID_ERR_INT_ST_S)
+#define JPEG_C_DQT_ID_ERR_INT_ST_V  0x00000001U
+#define JPEG_C_DQT_ID_ERR_INT_ST_S  5
+/** JPEG_RST_UXP_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The status interrupt bit to sign that RST header marker is detected but restart
+ *  interval is 0 when decoding.
+ */
+#define JPEG_RST_UXP_ERR_INT_ST    (BIT(6))
+#define JPEG_RST_UXP_ERR_INT_ST_M  (JPEG_RST_UXP_ERR_INT_ST_V << JPEG_RST_UXP_ERR_INT_ST_S)
+#define JPEG_RST_UXP_ERR_INT_ST_V  0x00000001U
+#define JPEG_RST_UXP_ERR_INT_ST_S  6
+/** JPEG_RST_CHECK_NONE_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The status interrupt bit to sign that RST header marker is not detected but restart
+ *  interval is not 0 when decoding.
+ */
+#define JPEG_RST_CHECK_NONE_ERR_INT_ST    (BIT(7))
+#define JPEG_RST_CHECK_NONE_ERR_INT_ST_M  (JPEG_RST_CHECK_NONE_ERR_INT_ST_V << JPEG_RST_CHECK_NONE_ERR_INT_ST_S)
+#define JPEG_RST_CHECK_NONE_ERR_INT_ST_V  0x00000001U
+#define JPEG_RST_CHECK_NONE_ERR_INT_ST_S  7
+/** JPEG_RST_CHECK_POS_ERR_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The status interrupt bit to sign that RST header marker position mismatches with
+ *  restart interval when decoding.
+ */
+#define JPEG_RST_CHECK_POS_ERR_INT_ST    (BIT(8))
+#define JPEG_RST_CHECK_POS_ERR_INT_ST_M  (JPEG_RST_CHECK_POS_ERR_INT_ST_V << JPEG_RST_CHECK_POS_ERR_INT_ST_S)
+#define JPEG_RST_CHECK_POS_ERR_INT_ST_V  0x00000001U
+#define JPEG_RST_CHECK_POS_ERR_INT_ST_S  8
+/** JPEG_OUT_EOF_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The status interrupt bit turns to high level when the last pixel of one square has
+ *  been transmitted for Tx channel.
+ */
+#define JPEG_OUT_EOF_INT_ST    (BIT(9))
+#define JPEG_OUT_EOF_INT_ST_M  (JPEG_OUT_EOF_INT_ST_V << JPEG_OUT_EOF_INT_ST_S)
+#define JPEG_OUT_EOF_INT_ST_V  0x00000001U
+#define JPEG_OUT_EOF_INT_ST_S  9
+/** JPEG_SR_COLOR_MODE_ERR_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status interrupt bit to sign that the selected source color mode is not
+ *  supported.
+ */
+#define JPEG_SR_COLOR_MODE_ERR_INT_ST    (BIT(10))
+#define JPEG_SR_COLOR_MODE_ERR_INT_ST_M  (JPEG_SR_COLOR_MODE_ERR_INT_ST_V << JPEG_SR_COLOR_MODE_ERR_INT_ST_S)
+#define JPEG_SR_COLOR_MODE_ERR_INT_ST_V  0x00000001U
+#define JPEG_SR_COLOR_MODE_ERR_INT_ST_S  10
+/** JPEG_DCT_DONE_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The status interrupt bit to sign that one dct calculation is finished.
+ */
+#define JPEG_DCT_DONE_INT_ST    (BIT(11))
+#define JPEG_DCT_DONE_INT_ST_M  (JPEG_DCT_DONE_INT_ST_V << JPEG_DCT_DONE_INT_ST_S)
+#define JPEG_DCT_DONE_INT_ST_V  0x00000001U
+#define JPEG_DCT_DONE_INT_ST_S  11
+/** JPEG_BS_LAST_BLOCK_EOF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The status interrupt bit to sign that the coding process for last block is finished.
+ */
+#define JPEG_BS_LAST_BLOCK_EOF_INT_ST    (BIT(12))
+#define JPEG_BS_LAST_BLOCK_EOF_INT_ST_M  (JPEG_BS_LAST_BLOCK_EOF_INT_ST_V << JPEG_BS_LAST_BLOCK_EOF_INT_ST_S)
+#define JPEG_BS_LAST_BLOCK_EOF_INT_ST_V  0x00000001U
+#define JPEG_BS_LAST_BLOCK_EOF_INT_ST_S  12
+/** JPEG_SCAN_CHECK_NONE_ERR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The status interrupt bit to sign that SOS header marker is not detected but there
+ *  are still components left to be decoded.
+ */
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_ST    (BIT(13))
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_ST_M  (JPEG_SCAN_CHECK_NONE_ERR_INT_ST_V << JPEG_SCAN_CHECK_NONE_ERR_INT_ST_S)
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_ST_V  0x00000001U
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_ST_S  13
+/** JPEG_SCAN_CHECK_POS_ERR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The status interrupt bit to sign that SOS header marker position wrong when
+ *  decoding.
+ */
+#define JPEG_SCAN_CHECK_POS_ERR_INT_ST    (BIT(14))
+#define JPEG_SCAN_CHECK_POS_ERR_INT_ST_M  (JPEG_SCAN_CHECK_POS_ERR_INT_ST_V << JPEG_SCAN_CHECK_POS_ERR_INT_ST_S)
+#define JPEG_SCAN_CHECK_POS_ERR_INT_ST_V  0x00000001U
+#define JPEG_SCAN_CHECK_POS_ERR_INT_ST_S  14
+/** JPEG_UXP_DET_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The status interrupt bit to sign that unsupported header marker is detected when
+ *  decoding.
+ */
+#define JPEG_UXP_DET_INT_ST    (BIT(15))
+#define JPEG_UXP_DET_INT_ST_M  (JPEG_UXP_DET_INT_ST_V << JPEG_UXP_DET_INT_ST_S)
+#define JPEG_UXP_DET_INT_ST_V  0x00000001U
+#define JPEG_UXP_DET_INT_ST_S  15
+/** JPEG_EN_FRAME_EOF_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The status interrupt bit to sign that received pixel blocks are smaller than
+ *  expected when encoding.
+ */
+#define JPEG_EN_FRAME_EOF_ERR_INT_ST    (BIT(16))
+#define JPEG_EN_FRAME_EOF_ERR_INT_ST_M  (JPEG_EN_FRAME_EOF_ERR_INT_ST_V << JPEG_EN_FRAME_EOF_ERR_INT_ST_S)
+#define JPEG_EN_FRAME_EOF_ERR_INT_ST_V  0x00000001U
+#define JPEG_EN_FRAME_EOF_ERR_INT_ST_S  16
+/** JPEG_EN_FRAME_EOF_LACK_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The status interrupt bit to sign that the frame eof sign bit from dma input is
+ *  missing when encoding. But the number of pixel blocks is enough.
+ */
+#define JPEG_EN_FRAME_EOF_LACK_INT_ST    (BIT(17))
+#define JPEG_EN_FRAME_EOF_LACK_INT_ST_M  (JPEG_EN_FRAME_EOF_LACK_INT_ST_V << JPEG_EN_FRAME_EOF_LACK_INT_ST_S)
+#define JPEG_EN_FRAME_EOF_LACK_INT_ST_V  0x00000001U
+#define JPEG_EN_FRAME_EOF_LACK_INT_ST_S  17
+/** JPEG_DE_FRAME_EOF_ERR_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The status interrupt bit to sign that decoded blocks are smaller than expected when
+ *  decoding.
+ */
+#define JPEG_DE_FRAME_EOF_ERR_INT_ST    (BIT(18))
+#define JPEG_DE_FRAME_EOF_ERR_INT_ST_M  (JPEG_DE_FRAME_EOF_ERR_INT_ST_V << JPEG_DE_FRAME_EOF_ERR_INT_ST_S)
+#define JPEG_DE_FRAME_EOF_ERR_INT_ST_V  0x00000001U
+#define JPEG_DE_FRAME_EOF_ERR_INT_ST_S  18
+/** JPEG_DE_FRAME_EOF_LACK_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The status interrupt bit to sign that the either frame eof from dma input or eoi
+ *  marker is missing when encoding. But the number of decoded blocks is enough.
+ */
+#define JPEG_DE_FRAME_EOF_LACK_INT_ST    (BIT(19))
+#define JPEG_DE_FRAME_EOF_LACK_INT_ST_M  (JPEG_DE_FRAME_EOF_LACK_INT_ST_V << JPEG_DE_FRAME_EOF_LACK_INT_ST_S)
+#define JPEG_DE_FRAME_EOF_LACK_INT_ST_V  0x00000001U
+#define JPEG_DE_FRAME_EOF_LACK_INT_ST_S  19
+/** JPEG_SOS_UNMATCH_ERR_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The status interrupt bit to sign that the component number of a scan is 0 or does
+ *  not match the sos marker's length when decoding.
+ */
+#define JPEG_SOS_UNMATCH_ERR_INT_ST    (BIT(20))
+#define JPEG_SOS_UNMATCH_ERR_INT_ST_M  (JPEG_SOS_UNMATCH_ERR_INT_ST_V << JPEG_SOS_UNMATCH_ERR_INT_ST_S)
+#define JPEG_SOS_UNMATCH_ERR_INT_ST_V  0x00000001U
+#define JPEG_SOS_UNMATCH_ERR_INT_ST_S  20
+/** JPEG_MARKER_ERR_FST_SCAN_INT_ST : RO; bitpos: [21]; default: 0;
+ *  The status interrupt bit to sign that the first scan has header marker error when
+ *  decoding.
+ */
+#define JPEG_MARKER_ERR_FST_SCAN_INT_ST    (BIT(21))
+#define JPEG_MARKER_ERR_FST_SCAN_INT_ST_M  (JPEG_MARKER_ERR_FST_SCAN_INT_ST_V << JPEG_MARKER_ERR_FST_SCAN_INT_ST_S)
+#define JPEG_MARKER_ERR_FST_SCAN_INT_ST_V  0x00000001U
+#define JPEG_MARKER_ERR_FST_SCAN_INT_ST_S  21
+/** JPEG_MARKER_ERR_OTHER_SCAN_INT_ST : RO; bitpos: [22]; default: 0;
+ *  The status interrupt bit to sign that the following scans but not the first scan
+ *  have header marker error when decoding.
+ */
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ST    (BIT(22))
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ST_M  (JPEG_MARKER_ERR_OTHER_SCAN_INT_ST_V << JPEG_MARKER_ERR_OTHER_SCAN_INT_ST_S)
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ST_V  0x00000001U
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ST_S  22
+/** JPEG_UNDET_INT_ST : RO; bitpos: [23]; default: 0;
+ *  The status interrupt bit to sign that JPEG format is not detected at the eof data
+ *  of a packet when decoding.
+ */
+#define JPEG_UNDET_INT_ST    (BIT(23))
+#define JPEG_UNDET_INT_ST_M  (JPEG_UNDET_INT_ST_V << JPEG_UNDET_INT_ST_S)
+#define JPEG_UNDET_INT_ST_V  0x00000001U
+#define JPEG_UNDET_INT_ST_S  23
+/** JPEG_DECODE_TIMEOUT_INT_ST : RO; bitpos: [24]; default: 0;
+ *  The status interrupt bit to sign that decode pause time is longer than the setting
+ *  decode timeout time when decoding.
+ */
+#define JPEG_DECODE_TIMEOUT_INT_ST    (BIT(24))
+#define JPEG_DECODE_TIMEOUT_INT_ST_M  (JPEG_DECODE_TIMEOUT_INT_ST_V << JPEG_DECODE_TIMEOUT_INT_ST_S)
+#define JPEG_DECODE_TIMEOUT_INT_ST_V  0x00000001U
+#define JPEG_DECODE_TIMEOUT_INT_ST_S  24
+
+/** JPEG_INT_CLR_REG register
+ *  Interrupt clear registers
+ */
+#define JPEG_INT_CLR_REG (DR_REG_JPEG_BASE + 0x44)
+/** JPEG_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  This clear interrupt bit turns to high level when JPEG finishes encoding a picture..
+ */
+#define JPEG_DONE_INT_CLR    (BIT(0))
+#define JPEG_DONE_INT_CLR_M  (JPEG_DONE_INT_CLR_V << JPEG_DONE_INT_CLR_S)
+#define JPEG_DONE_INT_CLR_V  0x00000001U
+#define JPEG_DONE_INT_CLR_S  0
+/** JPEG_RLE_PARALLEL_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear interrupt bit to sign that rle parallel error when decoding.
+ */
+#define JPEG_RLE_PARALLEL_ERR_INT_CLR    (BIT(1))
+#define JPEG_RLE_PARALLEL_ERR_INT_CLR_M  (JPEG_RLE_PARALLEL_ERR_INT_CLR_V << JPEG_RLE_PARALLEL_ERR_INT_CLR_S)
+#define JPEG_RLE_PARALLEL_ERR_INT_CLR_V  0x00000001U
+#define JPEG_RLE_PARALLEL_ERR_INT_CLR_S  1
+/** JPEG_CID_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear interrupt bit to sign that scan id check with component fails when
+ *  decoding.
+ */
+#define JPEG_CID_ERR_INT_CLR    (BIT(2))
+#define JPEG_CID_ERR_INT_CLR_M  (JPEG_CID_ERR_INT_CLR_V << JPEG_CID_ERR_INT_CLR_S)
+#define JPEG_CID_ERR_INT_CLR_V  0x00000001U
+#define JPEG_CID_ERR_INT_CLR_S  2
+/** JPEG_C_DHT_DC_ID_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear interrupt bit to sign that scan component's dc dht id check with dc dht
+ *  table's id fails when decoding.
+ */
+#define JPEG_C_DHT_DC_ID_ERR_INT_CLR    (BIT(3))
+#define JPEG_C_DHT_DC_ID_ERR_INT_CLR_M  (JPEG_C_DHT_DC_ID_ERR_INT_CLR_V << JPEG_C_DHT_DC_ID_ERR_INT_CLR_S)
+#define JPEG_C_DHT_DC_ID_ERR_INT_CLR_V  0x00000001U
+#define JPEG_C_DHT_DC_ID_ERR_INT_CLR_S  3
+/** JPEG_C_DHT_AC_ID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear interrupt bit to sign that scan component's ac dht id check with ac dht
+ *  table's id fails when decoding.
+ */
+#define JPEG_C_DHT_AC_ID_ERR_INT_CLR    (BIT(4))
+#define JPEG_C_DHT_AC_ID_ERR_INT_CLR_M  (JPEG_C_DHT_AC_ID_ERR_INT_CLR_V << JPEG_C_DHT_AC_ID_ERR_INT_CLR_S)
+#define JPEG_C_DHT_AC_ID_ERR_INT_CLR_V  0x00000001U
+#define JPEG_C_DHT_AC_ID_ERR_INT_CLR_S  4
+/** JPEG_C_DQT_ID_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The clear interrupt bit to sign that scan component's dqt id check with dqt table's
+ *  id fails when decoding.
+ */
+#define JPEG_C_DQT_ID_ERR_INT_CLR    (BIT(5))
+#define JPEG_C_DQT_ID_ERR_INT_CLR_M  (JPEG_C_DQT_ID_ERR_INT_CLR_V << JPEG_C_DQT_ID_ERR_INT_CLR_S)
+#define JPEG_C_DQT_ID_ERR_INT_CLR_V  0x00000001U
+#define JPEG_C_DQT_ID_ERR_INT_CLR_S  5
+/** JPEG_RST_UXP_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The clear interrupt bit to sign that RST header marker is detected but restart
+ *  interval is 0 when decoding.
+ */
+#define JPEG_RST_UXP_ERR_INT_CLR    (BIT(6))
+#define JPEG_RST_UXP_ERR_INT_CLR_M  (JPEG_RST_UXP_ERR_INT_CLR_V << JPEG_RST_UXP_ERR_INT_CLR_S)
+#define JPEG_RST_UXP_ERR_INT_CLR_V  0x00000001U
+#define JPEG_RST_UXP_ERR_INT_CLR_S  6
+/** JPEG_RST_CHECK_NONE_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The clear interrupt bit to sign that RST header marker is not detected but restart
+ *  interval is not 0 when decoding.
+ */
+#define JPEG_RST_CHECK_NONE_ERR_INT_CLR    (BIT(7))
+#define JPEG_RST_CHECK_NONE_ERR_INT_CLR_M  (JPEG_RST_CHECK_NONE_ERR_INT_CLR_V << JPEG_RST_CHECK_NONE_ERR_INT_CLR_S)
+#define JPEG_RST_CHECK_NONE_ERR_INT_CLR_V  0x00000001U
+#define JPEG_RST_CHECK_NONE_ERR_INT_CLR_S  7
+/** JPEG_RST_CHECK_POS_ERR_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The clear interrupt bit to sign that RST header marker position mismatches with
+ *  restart interval when decoding.
+ */
+#define JPEG_RST_CHECK_POS_ERR_INT_CLR    (BIT(8))
+#define JPEG_RST_CHECK_POS_ERR_INT_CLR_M  (JPEG_RST_CHECK_POS_ERR_INT_CLR_V << JPEG_RST_CHECK_POS_ERR_INT_CLR_S)
+#define JPEG_RST_CHECK_POS_ERR_INT_CLR_V  0x00000001U
+#define JPEG_RST_CHECK_POS_ERR_INT_CLR_S  8
+/** JPEG_OUT_EOF_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The clear interrupt bit turns to high level when the last pixel of one square has
+ *  been transmitted for Tx channel.
+ */
+#define JPEG_OUT_EOF_INT_CLR    (BIT(9))
+#define JPEG_OUT_EOF_INT_CLR_M  (JPEG_OUT_EOF_INT_CLR_V << JPEG_OUT_EOF_INT_CLR_S)
+#define JPEG_OUT_EOF_INT_CLR_V  0x00000001U
+#define JPEG_OUT_EOF_INT_CLR_S  9
+/** JPEG_SR_COLOR_MODE_ERR_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The clear interrupt bit to sign that the selected source color mode is not
+ *  supported.
+ */
+#define JPEG_SR_COLOR_MODE_ERR_INT_CLR    (BIT(10))
+#define JPEG_SR_COLOR_MODE_ERR_INT_CLR_M  (JPEG_SR_COLOR_MODE_ERR_INT_CLR_V << JPEG_SR_COLOR_MODE_ERR_INT_CLR_S)
+#define JPEG_SR_COLOR_MODE_ERR_INT_CLR_V  0x00000001U
+#define JPEG_SR_COLOR_MODE_ERR_INT_CLR_S  10
+/** JPEG_DCT_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The clear interrupt bit to sign that one dct calculation is finished.
+ */
+#define JPEG_DCT_DONE_INT_CLR    (BIT(11))
+#define JPEG_DCT_DONE_INT_CLR_M  (JPEG_DCT_DONE_INT_CLR_V << JPEG_DCT_DONE_INT_CLR_S)
+#define JPEG_DCT_DONE_INT_CLR_V  0x00000001U
+#define JPEG_DCT_DONE_INT_CLR_S  11
+/** JPEG_BS_LAST_BLOCK_EOF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The clear interrupt bit to sign that the coding process for last block is finished.
+ */
+#define JPEG_BS_LAST_BLOCK_EOF_INT_CLR    (BIT(12))
+#define JPEG_BS_LAST_BLOCK_EOF_INT_CLR_M  (JPEG_BS_LAST_BLOCK_EOF_INT_CLR_V << JPEG_BS_LAST_BLOCK_EOF_INT_CLR_S)
+#define JPEG_BS_LAST_BLOCK_EOF_INT_CLR_V  0x00000001U
+#define JPEG_BS_LAST_BLOCK_EOF_INT_CLR_S  12
+/** JPEG_SCAN_CHECK_NONE_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The clear interrupt bit to sign that SOS header marker is not detected but there
+ *  are still components left to be decoded.
+ */
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_CLR    (BIT(13))
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_CLR_M  (JPEG_SCAN_CHECK_NONE_ERR_INT_CLR_V << JPEG_SCAN_CHECK_NONE_ERR_INT_CLR_S)
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_CLR_V  0x00000001U
+#define JPEG_SCAN_CHECK_NONE_ERR_INT_CLR_S  13
+/** JPEG_SCAN_CHECK_POS_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  The clear interrupt bit to sign that SOS header marker position wrong when decoding.
+ */
+#define JPEG_SCAN_CHECK_POS_ERR_INT_CLR    (BIT(14))
+#define JPEG_SCAN_CHECK_POS_ERR_INT_CLR_M  (JPEG_SCAN_CHECK_POS_ERR_INT_CLR_V << JPEG_SCAN_CHECK_POS_ERR_INT_CLR_S)
+#define JPEG_SCAN_CHECK_POS_ERR_INT_CLR_V  0x00000001U
+#define JPEG_SCAN_CHECK_POS_ERR_INT_CLR_S  14
+/** JPEG_UXP_DET_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  The clear interrupt bit to sign that unsupported header marker is detected when
+ *  decoding.
+ */
+#define JPEG_UXP_DET_INT_CLR    (BIT(15))
+#define JPEG_UXP_DET_INT_CLR_M  (JPEG_UXP_DET_INT_CLR_V << JPEG_UXP_DET_INT_CLR_S)
+#define JPEG_UXP_DET_INT_CLR_V  0x00000001U
+#define JPEG_UXP_DET_INT_CLR_S  15
+/** JPEG_EN_FRAME_EOF_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  The clear interrupt bit to sign that received pixel blocks are smaller than
+ *  expected when encoding.
+ */
+#define JPEG_EN_FRAME_EOF_ERR_INT_CLR    (BIT(16))
+#define JPEG_EN_FRAME_EOF_ERR_INT_CLR_M  (JPEG_EN_FRAME_EOF_ERR_INT_CLR_V << JPEG_EN_FRAME_EOF_ERR_INT_CLR_S)
+#define JPEG_EN_FRAME_EOF_ERR_INT_CLR_V  0x00000001U
+#define JPEG_EN_FRAME_EOF_ERR_INT_CLR_S  16
+/** JPEG_EN_FRAME_EOF_LACK_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  The clear interrupt bit to sign that the frame eof sign bit from dma input is
+ *  missing when encoding. But the number of pixel blocks is enough.
+ */
+#define JPEG_EN_FRAME_EOF_LACK_INT_CLR    (BIT(17))
+#define JPEG_EN_FRAME_EOF_LACK_INT_CLR_M  (JPEG_EN_FRAME_EOF_LACK_INT_CLR_V << JPEG_EN_FRAME_EOF_LACK_INT_CLR_S)
+#define JPEG_EN_FRAME_EOF_LACK_INT_CLR_V  0x00000001U
+#define JPEG_EN_FRAME_EOF_LACK_INT_CLR_S  17
+/** JPEG_DE_FRAME_EOF_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  The clear interrupt bit to sign that decoded blocks are smaller than expected when
+ *  decoding.
+ */
+#define JPEG_DE_FRAME_EOF_ERR_INT_CLR    (BIT(18))
+#define JPEG_DE_FRAME_EOF_ERR_INT_CLR_M  (JPEG_DE_FRAME_EOF_ERR_INT_CLR_V << JPEG_DE_FRAME_EOF_ERR_INT_CLR_S)
+#define JPEG_DE_FRAME_EOF_ERR_INT_CLR_V  0x00000001U
+#define JPEG_DE_FRAME_EOF_ERR_INT_CLR_S  18
+/** JPEG_DE_FRAME_EOF_LACK_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  The clear interrupt bit to sign that the either frame eof from dma input or eoi
+ *  marker is missing when encoding. But the number of decoded blocks is enough.
+ */
+#define JPEG_DE_FRAME_EOF_LACK_INT_CLR    (BIT(19))
+#define JPEG_DE_FRAME_EOF_LACK_INT_CLR_M  (JPEG_DE_FRAME_EOF_LACK_INT_CLR_V << JPEG_DE_FRAME_EOF_LACK_INT_CLR_S)
+#define JPEG_DE_FRAME_EOF_LACK_INT_CLR_V  0x00000001U
+#define JPEG_DE_FRAME_EOF_LACK_INT_CLR_S  19
+/** JPEG_SOS_UNMATCH_ERR_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  The clear interrupt bit to sign that the component number of a scan is 0 or does
+ *  not match the sos marker's length when decoding.
+ */
+#define JPEG_SOS_UNMATCH_ERR_INT_CLR    (BIT(20))
+#define JPEG_SOS_UNMATCH_ERR_INT_CLR_M  (JPEG_SOS_UNMATCH_ERR_INT_CLR_V << JPEG_SOS_UNMATCH_ERR_INT_CLR_S)
+#define JPEG_SOS_UNMATCH_ERR_INT_CLR_V  0x00000001U
+#define JPEG_SOS_UNMATCH_ERR_INT_CLR_S  20
+/** JPEG_MARKER_ERR_FST_SCAN_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  The clear interrupt bit to sign that the first scan has header marker error when
+ *  decoding.
+ */
+#define JPEG_MARKER_ERR_FST_SCAN_INT_CLR    (BIT(21))
+#define JPEG_MARKER_ERR_FST_SCAN_INT_CLR_M  (JPEG_MARKER_ERR_FST_SCAN_INT_CLR_V << JPEG_MARKER_ERR_FST_SCAN_INT_CLR_S)
+#define JPEG_MARKER_ERR_FST_SCAN_INT_CLR_V  0x00000001U
+#define JPEG_MARKER_ERR_FST_SCAN_INT_CLR_S  21
+/** JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  The clear interrupt bit to sign that the following scans but not the first scan
+ *  have header marker error when decoding.
+ */
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR    (BIT(22))
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR_M  (JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR_V << JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR_S)
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR_V  0x00000001U
+#define JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR_S  22
+/** JPEG_UNDET_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  The clear interrupt bit to sign that JPEG format is not detected at the eof data of
+ *  a packet when decoding.
+ */
+#define JPEG_UNDET_INT_CLR    (BIT(23))
+#define JPEG_UNDET_INT_CLR_M  (JPEG_UNDET_INT_CLR_V << JPEG_UNDET_INT_CLR_S)
+#define JPEG_UNDET_INT_CLR_V  0x00000001U
+#define JPEG_UNDET_INT_CLR_S  23
+/** JPEG_DECODE_TIMEOUT_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  The clear interrupt bit to sign that decode pause time is longer than the setting
+ *  decode timeout time when decoding.
+ */
+#define JPEG_DECODE_TIMEOUT_INT_CLR    (BIT(24))
+#define JPEG_DECODE_TIMEOUT_INT_CLR_M  (JPEG_DECODE_TIMEOUT_INT_CLR_V << JPEG_DECODE_TIMEOUT_INT_CLR_S)
+#define JPEG_DECODE_TIMEOUT_INT_CLR_V  0x00000001U
+#define JPEG_DECODE_TIMEOUT_INT_CLR_S  24
+
+/** JPEG_STATUS0_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_STATUS0_REG (DR_REG_JPEG_BASE + 0x48)
+/** JPEG_BITSTREAM_EOF_VLD_CNT : RO; bitpos: [16:11]; default: 0;
+ *  the valid bit count for last bitstream
+ */
+#define JPEG_BITSTREAM_EOF_VLD_CNT    0x0000003FU
+#define JPEG_BITSTREAM_EOF_VLD_CNT_M  (JPEG_BITSTREAM_EOF_VLD_CNT_V << JPEG_BITSTREAM_EOF_VLD_CNT_S)
+#define JPEG_BITSTREAM_EOF_VLD_CNT_V  0x0000003FU
+#define JPEG_BITSTREAM_EOF_VLD_CNT_S  11
+/** JPEG_DCTOUT_ZZSCAN_ADDR : RO; bitpos: [22:17]; default: 0;
+ *  the zig-zag read addr from dctout_ram
+ */
+#define JPEG_DCTOUT_ZZSCAN_ADDR    0x0000003FU
+#define JPEG_DCTOUT_ZZSCAN_ADDR_M  (JPEG_DCTOUT_ZZSCAN_ADDR_V << JPEG_DCTOUT_ZZSCAN_ADDR_S)
+#define JPEG_DCTOUT_ZZSCAN_ADDR_V  0x0000003FU
+#define JPEG_DCTOUT_ZZSCAN_ADDR_S  17
+/** JPEG_QNRVAL_ZZSCAN_ADDR : RO; bitpos: [28:23]; default: 0;
+ *  the zig-zag read addr from qnrval_ram
+ */
+#define JPEG_QNRVAL_ZZSCAN_ADDR    0x0000003FU
+#define JPEG_QNRVAL_ZZSCAN_ADDR_M  (JPEG_QNRVAL_ZZSCAN_ADDR_V << JPEG_QNRVAL_ZZSCAN_ADDR_S)
+#define JPEG_QNRVAL_ZZSCAN_ADDR_V  0x0000003FU
+#define JPEG_QNRVAL_ZZSCAN_ADDR_S  23
+/** JPEG_REG_STATE_YUV : RO; bitpos: [31:29]; default: 0;
+ *  the state of jpeg fsm
+ */
+#define JPEG_REG_STATE_YUV    0x00000007U
+#define JPEG_REG_STATE_YUV_M  (JPEG_REG_STATE_YUV_V << JPEG_REG_STATE_YUV_S)
+#define JPEG_REG_STATE_YUV_V  0x00000007U
+#define JPEG_REG_STATE_YUV_S  29
+
+/** JPEG_STATUS2_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_STATUS2_REG (DR_REG_JPEG_BASE + 0x4c)
+/** JPEG_SOURCE_PIXEL : RO; bitpos: [23:0]; default: 0;
+ *  source pixels fetched from dma
+ */
+#define JPEG_SOURCE_PIXEL    0x00FFFFFFU
+#define JPEG_SOURCE_PIXEL_M  (JPEG_SOURCE_PIXEL_V << JPEG_SOURCE_PIXEL_S)
+#define JPEG_SOURCE_PIXEL_V  0x00FFFFFFU
+#define JPEG_SOURCE_PIXEL_S  0
+/** JPEG_LAST_BLOCK : RO; bitpos: [24]; default: 0;
+ *  indicate the encoding process for the last mcu of the picture
+ */
+#define JPEG_LAST_BLOCK    (BIT(24))
+#define JPEG_LAST_BLOCK_M  (JPEG_LAST_BLOCK_V << JPEG_LAST_BLOCK_S)
+#define JPEG_LAST_BLOCK_V  0x00000001U
+#define JPEG_LAST_BLOCK_S  24
+/** JPEG_LAST_MCU : RO; bitpos: [25]; default: 0;
+ *  indicate the encoding process for the last block of the picture
+ */
+#define JPEG_LAST_MCU    (BIT(25))
+#define JPEG_LAST_MCU_M  (JPEG_LAST_MCU_V << JPEG_LAST_MCU_S)
+#define JPEG_LAST_MCU_V  0x00000001U
+#define JPEG_LAST_MCU_S  25
+/** JPEG_LAST_DC : RO; bitpos: [26]; default: 0;
+ *  indicate the encoding process is at the header of the last block of the picture
+ */
+#define JPEG_LAST_DC    (BIT(26))
+#define JPEG_LAST_DC_M  (JPEG_LAST_DC_V << JPEG_LAST_DC_S)
+#define JPEG_LAST_DC_V  0x00000001U
+#define JPEG_LAST_DC_S  26
+/** JPEG_PACKFIFO_READY : RO; bitpos: [27]; default: 1;
+ *  the jpeg pack_fifo ready signal, high active
+ */
+#define JPEG_PACKFIFO_READY    (BIT(27))
+#define JPEG_PACKFIFO_READY_M  (JPEG_PACKFIFO_READY_V << JPEG_PACKFIFO_READY_S)
+#define JPEG_PACKFIFO_READY_V  0x00000001U
+#define JPEG_PACKFIFO_READY_S  27
+
+/** JPEG_STATUS3_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_STATUS3_REG (DR_REG_JPEG_BASE + 0x50)
+/** JPEG_YO : RO; bitpos: [8:0]; default: 0;
+ *  component y transferred from rgb input
+ */
+#define JPEG_YO    0x000001FFU
+#define JPEG_YO_M  (JPEG_YO_V << JPEG_YO_S)
+#define JPEG_YO_V  0x000001FFU
+#define JPEG_YO_S  0
+/** JPEG_Y_READY : RO; bitpos: [9]; default: 0;
+ *  component y valid signal, high active
+ */
+#define JPEG_Y_READY    (BIT(9))
+#define JPEG_Y_READY_M  (JPEG_Y_READY_V << JPEG_Y_READY_S)
+#define JPEG_Y_READY_V  0x00000001U
+#define JPEG_Y_READY_S  9
+/** JPEG_CBO : RO; bitpos: [18:10]; default: 0;
+ *  component cb transferred from rgb input
+ */
+#define JPEG_CBO    0x000001FFU
+#define JPEG_CBO_M  (JPEG_CBO_V << JPEG_CBO_S)
+#define JPEG_CBO_V  0x000001FFU
+#define JPEG_CBO_S  10
+/** JPEG_CB_READY : RO; bitpos: [19]; default: 0;
+ *  component cb valid signal, high active
+ */
+#define JPEG_CB_READY    (BIT(19))
+#define JPEG_CB_READY_M  (JPEG_CB_READY_V << JPEG_CB_READY_S)
+#define JPEG_CB_READY_V  0x00000001U
+#define JPEG_CB_READY_S  19
+/** JPEG_CRO : RO; bitpos: [28:20]; default: 0;
+ *  component cr transferred from rgb input
+ */
+#define JPEG_CRO    0x000001FFU
+#define JPEG_CRO_M  (JPEG_CRO_V << JPEG_CRO_S)
+#define JPEG_CRO_V  0x000001FFU
+#define JPEG_CRO_S  20
+/** JPEG_CR_READY : RO; bitpos: [29]; default: 0;
+ *  component cr valid signal, high active
+ */
+#define JPEG_CR_READY    (BIT(29))
+#define JPEG_CR_READY_M  (JPEG_CR_READY_V << JPEG_CR_READY_S)
+#define JPEG_CR_READY_V  0x00000001U
+#define JPEG_CR_READY_S  29
+
+/** JPEG_STATUS4_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_STATUS4_REG (DR_REG_JPEG_BASE + 0x54)
+/** JPEG_HFM_BITSTREAM : RO; bitpos: [31:0]; default: 0;
+ *  the hufman bitstream during encoding process
+ */
+#define JPEG_HFM_BITSTREAM    0xFFFFFFFFU
+#define JPEG_HFM_BITSTREAM_M  (JPEG_HFM_BITSTREAM_V << JPEG_HFM_BITSTREAM_S)
+#define JPEG_HFM_BITSTREAM_V  0xFFFFFFFFU
+#define JPEG_HFM_BITSTREAM_S  0
+
+/** JPEG_DHT_TOTLEN_DC0_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_TOTLEN_DC0_REG (DR_REG_JPEG_BASE + 0x58)
+/** JPEG_DHT_TOTLEN_DC0 : HRO; bitpos: [31:0]; default: 0;
+ *  write the numbers of 1~n codeword length sum from 1~16 of dc0 table
+ */
+#define JPEG_DHT_TOTLEN_DC0    0xFFFFFFFFU
+#define JPEG_DHT_TOTLEN_DC0_M  (JPEG_DHT_TOTLEN_DC0_V << JPEG_DHT_TOTLEN_DC0_S)
+#define JPEG_DHT_TOTLEN_DC0_V  0xFFFFFFFFU
+#define JPEG_DHT_TOTLEN_DC0_S  0
+
+/** JPEG_DHT_VAl_DC0_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_VAL_DC0_REG (DR_REG_JPEG_BASE + 0x5c)
+/** JPEG_DHT_VAL_DC0 : HRO; bitpos: [31:0]; default: 0;
+ *  write codeword corresponding huffman values of dc0 table
+ */
+#define JPEG_DHT_VAL_DC0    0xFFFFFFFFU
+#define JPEG_DHT_VAL_DC0_M  (JPEG_DHT_VAL_DC0_V << JPEG_DHT_VAL_DC0_S)
+#define JPEG_DHT_VAL_DC0_V  0xFFFFFFFFU
+#define JPEG_DHT_VAL_DC0_S  0
+
+/** JPEG_DHT_TOTLEN_AC0_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_TOTLEN_AC0_REG (DR_REG_JPEG_BASE + 0x60)
+/** JPEG_DHT_TOTLEN_AC0 : HRO; bitpos: [31:0]; default: 0;
+ *  write the numbers of 1~n codeword length sum from 1~16 of ac0 table
+ */
+#define JPEG_DHT_TOTLEN_AC0    0xFFFFFFFFU
+#define JPEG_DHT_TOTLEN_AC0_M  (JPEG_DHT_TOTLEN_AC0_V << JPEG_DHT_TOTLEN_AC0_S)
+#define JPEG_DHT_TOTLEN_AC0_V  0xFFFFFFFFU
+#define JPEG_DHT_TOTLEN_AC0_S  0
+
+/** JPEG_DHT_VAl_AC0_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_VAL_AC0_REG (DR_REG_JPEG_BASE + 0x64)
+/** JPEG_DHT_VAL_AC0 : HRO; bitpos: [31:0]; default: 0;
+ *  write codeword corresponding huffman values of ac0 table
+ */
+#define JPEG_DHT_VAL_AC0    0xFFFFFFFFU
+#define JPEG_DHT_VAL_AC0_M  (JPEG_DHT_VAL_AC0_V << JPEG_DHT_VAL_AC0_S)
+#define JPEG_DHT_VAL_AC0_V  0xFFFFFFFFU
+#define JPEG_DHT_VAL_AC0_S  0
+
+/** JPEG_DHT_TOTLEN_DC1_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_TOTLEN_DC1_REG (DR_REG_JPEG_BASE + 0x68)
+/** JPEG_DHT_TOTLEN_DC1 : HRO; bitpos: [31:0]; default: 0;
+ *  write the numbers of 1~n codeword length sum from 1~16 of dc1 table
+ */
+#define JPEG_DHT_TOTLEN_DC1    0xFFFFFFFFU
+#define JPEG_DHT_TOTLEN_DC1_M  (JPEG_DHT_TOTLEN_DC1_V << JPEG_DHT_TOTLEN_DC1_S)
+#define JPEG_DHT_TOTLEN_DC1_V  0xFFFFFFFFU
+#define JPEG_DHT_TOTLEN_DC1_S  0
+
+/** JPEG_DHT_VAl_DC1_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_VAL_DC1_REG (DR_REG_JPEG_BASE + 0x6c)
+/** JPEG_DHT_VAL_DC1 : HRO; bitpos: [31:0]; default: 0;
+ *  write codeword corresponding huffman values of dc1 table
+ */
+#define JPEG_DHT_VAL_DC1    0xFFFFFFFFU
+#define JPEG_DHT_VAL_DC1_M  (JPEG_DHT_VAL_DC1_V << JPEG_DHT_VAL_DC1_S)
+#define JPEG_DHT_VAL_DC1_V  0xFFFFFFFFU
+#define JPEG_DHT_VAL_DC1_S  0
+
+/** JPEG_DHT_TOTLEN_AC1_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_TOTLEN_AC1_REG (DR_REG_JPEG_BASE + 0x70)
+/** JPEG_DHT_TOTLEN_AC1 : HRO; bitpos: [31:0]; default: 0;
+ *  write the numbers of 1~n codeword length sum from 1~16 of ac1 table
+ */
+#define JPEG_DHT_TOTLEN_AC1    0xFFFFFFFFU
+#define JPEG_DHT_TOTLEN_AC1_M  (JPEG_DHT_TOTLEN_AC1_V << JPEG_DHT_TOTLEN_AC1_S)
+#define JPEG_DHT_TOTLEN_AC1_V  0xFFFFFFFFU
+#define JPEG_DHT_TOTLEN_AC1_S  0
+
+/** JPEG_DHT_VAl_AC1_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_VAL_AC1_REG (DR_REG_JPEG_BASE + 0x74)
+/** JPEG_DHT_VAL_AC1 : HRO; bitpos: [31:0]; default: 0;
+ *  write codeword corresponding huffman values of ac1 table
+ */
+#define JPEG_DHT_VAL_AC1    0xFFFFFFFFU
+#define JPEG_DHT_VAL_AC1_M  (JPEG_DHT_VAL_AC1_V << JPEG_DHT_VAL_AC1_S)
+#define JPEG_DHT_VAL_AC1_V  0xFFFFFFFFU
+#define JPEG_DHT_VAL_AC1_S  0
+
+/** JPEG_DHT_CODEMIN_DC0_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_CODEMIN_DC0_REG (DR_REG_JPEG_BASE + 0x78)
+/** JPEG_DHT_CODEMIN_DC0 : HRO; bitpos: [31:0]; default: 0;
+ *  write the minimum codeword of  code length from 1~16 of dc0 table. The codeword is
+ *  left shifted to the MSB position of a 16bit word
+ */
+#define JPEG_DHT_CODEMIN_DC0    0xFFFFFFFFU
+#define JPEG_DHT_CODEMIN_DC0_M  (JPEG_DHT_CODEMIN_DC0_V << JPEG_DHT_CODEMIN_DC0_S)
+#define JPEG_DHT_CODEMIN_DC0_V  0xFFFFFFFFU
+#define JPEG_DHT_CODEMIN_DC0_S  0
+
+/** JPEG_DHT_CODEMIN_AC0_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_CODEMIN_AC0_REG (DR_REG_JPEG_BASE + 0x7c)
+/** JPEG_DHT_CODEMIN_AC0 : HRO; bitpos: [31:0]; default: 0;
+ *  write the minimum codeword of  code length from 1~16 of ac0 table. The codeword is
+ *  left shifted to the MSB position of a 16bit word
+ */
+#define JPEG_DHT_CODEMIN_AC0    0xFFFFFFFFU
+#define JPEG_DHT_CODEMIN_AC0_M  (JPEG_DHT_CODEMIN_AC0_V << JPEG_DHT_CODEMIN_AC0_S)
+#define JPEG_DHT_CODEMIN_AC0_V  0xFFFFFFFFU
+#define JPEG_DHT_CODEMIN_AC0_S  0
+
+/** JPEG_DHT_CODEMIN_DC1_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_CODEMIN_DC1_REG (DR_REG_JPEG_BASE + 0x80)
+/** JPEG_DHT_CODEMIN_DC1 : HRO; bitpos: [31:0]; default: 0;
+ *  write the minimum codeword of  code length from 1~16 of dc1 table. The codeword is
+ *  left shifted to the MSB position of a 16bit word
+ */
+#define JPEG_DHT_CODEMIN_DC1    0xFFFFFFFFU
+#define JPEG_DHT_CODEMIN_DC1_M  (JPEG_DHT_CODEMIN_DC1_V << JPEG_DHT_CODEMIN_DC1_S)
+#define JPEG_DHT_CODEMIN_DC1_V  0xFFFFFFFFU
+#define JPEG_DHT_CODEMIN_DC1_S  0
+
+/** JPEG_DHT_CODEMIN_AC1_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DHT_CODEMIN_AC1_REG (DR_REG_JPEG_BASE + 0x84)
+/** JPEG_DHT_CODEMIN_AC1 : HRO; bitpos: [31:0]; default: 0;
+ *  write the minimum codeword of  code length from 1~16 of ac1 table. The codeword is
+ *  left shifted to the MSB position of a 16bit word
+ */
+#define JPEG_DHT_CODEMIN_AC1    0xFFFFFFFFU
+#define JPEG_DHT_CODEMIN_AC1_M  (JPEG_DHT_CODEMIN_AC1_V << JPEG_DHT_CODEMIN_AC1_S)
+#define JPEG_DHT_CODEMIN_AC1_V  0xFFFFFFFFU
+#define JPEG_DHT_CODEMIN_AC1_S  0
+
+/** JPEG_DECODER_STATUS0_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DECODER_STATUS0_REG (DR_REG_JPEG_BASE + 0x88)
+/** JPEG_DECODE_BYTE_CNT : RO; bitpos: [25:0]; default: 0;
+ *  Reserved
+ */
+#define JPEG_DECODE_BYTE_CNT    0x03FFFFFFU
+#define JPEG_DECODE_BYTE_CNT_M  (JPEG_DECODE_BYTE_CNT_V << JPEG_DECODE_BYTE_CNT_S)
+#define JPEG_DECODE_BYTE_CNT_V  0x03FFFFFFU
+#define JPEG_DECODE_BYTE_CNT_S  0
+/** JPEG_HEADER_DEC_ST : RO; bitpos: [29:26]; default: 0;
+ *  Reserved
+ */
+#define JPEG_HEADER_DEC_ST    0x0000000FU
+#define JPEG_HEADER_DEC_ST_M  (JPEG_HEADER_DEC_ST_V << JPEG_HEADER_DEC_ST_S)
+#define JPEG_HEADER_DEC_ST_V  0x0000000FU
+#define JPEG_HEADER_DEC_ST_S  26
+/** JPEG_DECODE_SAMPLE_SEL : RO; bitpos: [31:30]; default: 0;
+ *  Reserved
+ */
+#define JPEG_DECODE_SAMPLE_SEL    0x00000003U
+#define JPEG_DECODE_SAMPLE_SEL_M  (JPEG_DECODE_SAMPLE_SEL_V << JPEG_DECODE_SAMPLE_SEL_S)
+#define JPEG_DECODE_SAMPLE_SEL_V  0x00000003U
+#define JPEG_DECODE_SAMPLE_SEL_S  30
+
+/** JPEG_DECODER_STATUS1_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DECODER_STATUS1_REG (DR_REG_JPEG_BASE + 0x8c)
+/** JPEG_ENCODE_DATA : RO; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define JPEG_ENCODE_DATA    0x0000FFFFU
+#define JPEG_ENCODE_DATA_M  (JPEG_ENCODE_DATA_V << JPEG_ENCODE_DATA_S)
+#define JPEG_ENCODE_DATA_V  0x0000FFFFU
+#define JPEG_ENCODE_DATA_S  0
+/** JPEG_COUNT_Q : RO; bitpos: [22:16]; default: 0;
+ *  Reserved
+ */
+#define JPEG_COUNT_Q    0x0000007FU
+#define JPEG_COUNT_Q_M  (JPEG_COUNT_Q_V << JPEG_COUNT_Q_S)
+#define JPEG_COUNT_Q_V  0x0000007FU
+#define JPEG_COUNT_Q_S  16
+/** JPEG_MCU_FSM_READY : RO; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define JPEG_MCU_FSM_READY    (BIT(23))
+#define JPEG_MCU_FSM_READY_M  (JPEG_MCU_FSM_READY_V << JPEG_MCU_FSM_READY_S)
+#define JPEG_MCU_FSM_READY_V  0x00000001U
+#define JPEG_MCU_FSM_READY_S  23
+/** JPEG_DECODE_DATA : RO; bitpos: [31:24]; default: 0;
+ *  Reserved
+ */
+#define JPEG_DECODE_DATA    0x000000FFU
+#define JPEG_DECODE_DATA_M  (JPEG_DECODE_DATA_V << JPEG_DECODE_DATA_S)
+#define JPEG_DECODE_DATA_V  0x000000FFU
+#define JPEG_DECODE_DATA_S  24
+
+/** JPEG_DECODER_STATUS2_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DECODER_STATUS2_REG (DR_REG_JPEG_BASE + 0x90)
+/** JPEG_COMP_BLOCK_NUM : RO; bitpos: [25:0]; default: 0;
+ *  Reserved
+ */
+#define JPEG_COMP_BLOCK_NUM    0x03FFFFFFU
+#define JPEG_COMP_BLOCK_NUM_M  (JPEG_COMP_BLOCK_NUM_V << JPEG_COMP_BLOCK_NUM_S)
+#define JPEG_COMP_BLOCK_NUM_V  0x03FFFFFFU
+#define JPEG_COMP_BLOCK_NUM_S  0
+/** JPEG_SCAN_NUM : RO; bitpos: [28:26]; default: 0;
+ *  Reserved
+ */
+#define JPEG_SCAN_NUM    0x00000007U
+#define JPEG_SCAN_NUM_M  (JPEG_SCAN_NUM_V << JPEG_SCAN_NUM_S)
+#define JPEG_SCAN_NUM_V  0x00000007U
+#define JPEG_SCAN_NUM_S  26
+/** JPEG_RST_CHECK_WAIT : RO; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define JPEG_RST_CHECK_WAIT    (BIT(29))
+#define JPEG_RST_CHECK_WAIT_M  (JPEG_RST_CHECK_WAIT_V << JPEG_RST_CHECK_WAIT_S)
+#define JPEG_RST_CHECK_WAIT_V  0x00000001U
+#define JPEG_RST_CHECK_WAIT_S  29
+/** JPEG_SCAN_CHECK_WAIT : RO; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define JPEG_SCAN_CHECK_WAIT    (BIT(30))
+#define JPEG_SCAN_CHECK_WAIT_M  (JPEG_SCAN_CHECK_WAIT_V << JPEG_SCAN_CHECK_WAIT_S)
+#define JPEG_SCAN_CHECK_WAIT_V  0x00000001U
+#define JPEG_SCAN_CHECK_WAIT_S  30
+/** JPEG_MCU_IN_PROC : RO; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define JPEG_MCU_IN_PROC    (BIT(31))
+#define JPEG_MCU_IN_PROC_M  (JPEG_MCU_IN_PROC_V << JPEG_MCU_IN_PROC_S)
+#define JPEG_MCU_IN_PROC_V  0x00000001U
+#define JPEG_MCU_IN_PROC_S  31
+
+/** JPEG_DECODER_STATUS3_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DECODER_STATUS3_REG (DR_REG_JPEG_BASE + 0x94)
+/** JPEG_LOOKUP_DATA : RO; bitpos: [31:0]; default: 0;
+ *  Reserved
+ */
+#define JPEG_LOOKUP_DATA    0xFFFFFFFFU
+#define JPEG_LOOKUP_DATA_M  (JPEG_LOOKUP_DATA_V << JPEG_LOOKUP_DATA_S)
+#define JPEG_LOOKUP_DATA_V  0xFFFFFFFFU
+#define JPEG_LOOKUP_DATA_S  0
+
+/** JPEG_DECODER_STATUS4_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DECODER_STATUS4_REG (DR_REG_JPEG_BASE + 0x98)
+/** JPEG_BLOCK_EOF_CNT : RO; bitpos: [25:0]; default: 0;
+ *  Reserved
+ */
+#define JPEG_BLOCK_EOF_CNT    0x03FFFFFFU
+#define JPEG_BLOCK_EOF_CNT_M  (JPEG_BLOCK_EOF_CNT_V << JPEG_BLOCK_EOF_CNT_S)
+#define JPEG_BLOCK_EOF_CNT_V  0x03FFFFFFU
+#define JPEG_BLOCK_EOF_CNT_S  0
+/** JPEG_DEZIGZAG_READY : RO; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define JPEG_DEZIGZAG_READY    (BIT(26))
+#define JPEG_DEZIGZAG_READY_M  (JPEG_DEZIGZAG_READY_V << JPEG_DEZIGZAG_READY_S)
+#define JPEG_DEZIGZAG_READY_V  0x00000001U
+#define JPEG_DEZIGZAG_READY_S  26
+/** JPEG_DE_FRAME_EOF_CHECK : RO; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define JPEG_DE_FRAME_EOF_CHECK    (BIT(27))
+#define JPEG_DE_FRAME_EOF_CHECK_M  (JPEG_DE_FRAME_EOF_CHECK_V << JPEG_DE_FRAME_EOF_CHECK_S)
+#define JPEG_DE_FRAME_EOF_CHECK_V  0x00000001U
+#define JPEG_DE_FRAME_EOF_CHECK_S  27
+/** JPEG_DE_DMA2D_IN_PUSH : RO; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define JPEG_DE_DMA2D_IN_PUSH    (BIT(28))
+#define JPEG_DE_DMA2D_IN_PUSH_M  (JPEG_DE_DMA2D_IN_PUSH_V << JPEG_DE_DMA2D_IN_PUSH_S)
+#define JPEG_DE_DMA2D_IN_PUSH_V  0x00000001U
+#define JPEG_DE_DMA2D_IN_PUSH_S  28
+
+/** JPEG_DECODER_STATUS5_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_DECODER_STATUS5_REG (DR_REG_JPEG_BASE + 0x9c)
+/** JPEG_IDCT_HFM_DATA : RO; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define JPEG_IDCT_HFM_DATA    0x0000FFFFU
+#define JPEG_IDCT_HFM_DATA_M  (JPEG_IDCT_HFM_DATA_V << JPEG_IDCT_HFM_DATA_S)
+#define JPEG_IDCT_HFM_DATA_V  0x0000FFFFU
+#define JPEG_IDCT_HFM_DATA_S  0
+/** JPEG_NS0 : RO; bitpos: [18:16]; default: 0;
+ *  Reserved
+ */
+#define JPEG_NS0    0x00000007U
+#define JPEG_NS0_M  (JPEG_NS0_V << JPEG_NS0_S)
+#define JPEG_NS0_V  0x00000007U
+#define JPEG_NS0_S  16
+/** JPEG_NS1 : RO; bitpos: [21:19]; default: 0;
+ *  Reserved
+ */
+#define JPEG_NS1    0x00000007U
+#define JPEG_NS1_M  (JPEG_NS1_V << JPEG_NS1_S)
+#define JPEG_NS1_V  0x00000007U
+#define JPEG_NS1_S  19
+/** JPEG_NS2 : RO; bitpos: [24:22]; default: 0;
+ *  Reserved
+ */
+#define JPEG_NS2    0x00000007U
+#define JPEG_NS2_M  (JPEG_NS2_V << JPEG_NS2_S)
+#define JPEG_NS2_V  0x00000007U
+#define JPEG_NS2_S  22
+/** JPEG_NS3 : RO; bitpos: [27:25]; default: 0;
+ *  Reserved
+ */
+#define JPEG_NS3    0x00000007U
+#define JPEG_NS3_M  (JPEG_NS3_V << JPEG_NS3_S)
+#define JPEG_NS3_V  0x00000007U
+#define JPEG_NS3_S  25
+/** JPEG_DATA_LAST_O : RO; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define JPEG_DATA_LAST_O    (BIT(28))
+#define JPEG_DATA_LAST_O_M  (JPEG_DATA_LAST_O_V << JPEG_DATA_LAST_O_S)
+#define JPEG_DATA_LAST_O_V  0x00000001U
+#define JPEG_DATA_LAST_O_S  28
+/** JPEG_RDN_RESULT : RO; bitpos: [29]; default: 0;
+ *  redundant registers for jpeg
+ */
+#define JPEG_RDN_RESULT    (BIT(29))
+#define JPEG_RDN_RESULT_M  (JPEG_RDN_RESULT_V << JPEG_RDN_RESULT_S)
+#define JPEG_RDN_RESULT_V  0x00000001U
+#define JPEG_RDN_RESULT_S  29
+/** JPEG_RDN_ENA : R/W; bitpos: [30]; default: 0;
+ *  redundant control registers for jpeg
+ */
+#define JPEG_RDN_ENA    (BIT(30))
+#define JPEG_RDN_ENA_M  (JPEG_RDN_ENA_V << JPEG_RDN_ENA_S)
+#define JPEG_RDN_ENA_V  0x00000001U
+#define JPEG_RDN_ENA_S  30
+
+/** JPEG_STATUS5_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_STATUS5_REG (DR_REG_JPEG_BASE + 0xa0)
+/** JPEG_PIC_BLOCK_NUM : RO; bitpos: [23:0]; default: 0;
+ *  Reserved
+ */
+#define JPEG_PIC_BLOCK_NUM    0x00FFFFFFU
+#define JPEG_PIC_BLOCK_NUM_M  (JPEG_PIC_BLOCK_NUM_V << JPEG_PIC_BLOCK_NUM_S)
+#define JPEG_PIC_BLOCK_NUM_V  0x00FFFFFFU
+#define JPEG_PIC_BLOCK_NUM_S  0
+
+/** JPEG_ECO_LOW_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_ECO_LOW_REG (DR_REG_JPEG_BASE + 0xa4)
+/** JPEG_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  redundant registers for jpeg
+ */
+#define JPEG_RDN_ECO_LOW    0xFFFFFFFFU
+#define JPEG_RDN_ECO_LOW_M  (JPEG_RDN_ECO_LOW_V << JPEG_RDN_ECO_LOW_S)
+#define JPEG_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define JPEG_RDN_ECO_LOW_S  0
+
+/** JPEG_ECO_HIGH_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_ECO_HIGH_REG (DR_REG_JPEG_BASE + 0xa8)
+/** JPEG_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  redundant registers for jpeg
+ */
+#define JPEG_RDN_ECO_HIGH    0xFFFFFFFFU
+#define JPEG_RDN_ECO_HIGH_M  (JPEG_RDN_ECO_HIGH_V << JPEG_RDN_ECO_HIGH_S)
+#define JPEG_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define JPEG_RDN_ECO_HIGH_S  0
+
+/** JPEG_SYS_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_SYS_REG (DR_REG_JPEG_BASE + 0xf8)
+/** JPEG_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define JPEG_CLK_EN    (BIT(31))
+#define JPEG_CLK_EN_M  (JPEG_CLK_EN_V << JPEG_CLK_EN_S)
+#define JPEG_CLK_EN_V  0x00000001U
+#define JPEG_CLK_EN_S  31
+
+/** JPEG_VERSION_REG register
+ *  Trace and Debug registers
+ */
+#define JPEG_VERSION_REG (DR_REG_JPEG_BASE + 0xfc)
+/** JPEG_JPEG_VER : R/W; bitpos: [27:0]; default: 37823072;
+ *  Reserved
+ */
+#define JPEG_JPEG_VER    0x0FFFFFFFU
+#define JPEG_JPEG_VER_M  (JPEG_JPEG_VER_V << JPEG_JPEG_VER_S)
+#define JPEG_JPEG_VER_V  0x0FFFFFFFU
+#define JPEG_JPEG_VER_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/jpeg_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/jpeg_struct.h
new file mode 100644
index 0000000000..854c04e63b
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/jpeg_struct.h
@@ -0,0 +1,1460 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of config register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** fsm_rst : WT; bitpos: [0]; default: 0;
+         *  fsm reset
+         */
+        uint32_t fsm_rst:1;
+        /** jpeg_start : WT; bitpos: [1]; default: 0;
+         *  start to compress a new pic(in dma reg mode)
+         */
+        uint32_t jpeg_start:1;
+        /** qnr_presition : R/W; bitpos: [2]; default: 0;
+         *  0:8bit qnr,1:12bit qnr(TBD)
+         */
+        uint32_t qnr_presition:1;
+        /** ff_check_en : R/W; bitpos: [3]; default: 1;
+         *  enable whether to add "00" after "ff"
+         */
+        uint32_t ff_check_en:1;
+        /** sample_sel : R/W; bitpos: [5:4]; default: 1;
+         *  0:yuv444,1:yuv422, 2:yuv420
+         */
+        uint32_t sample_sel:2;
+        /** dma_linklist_mode : RO; bitpos: [6]; default: 1;
+         *  1:use linklist to configure dma
+         */
+        uint32_t dma_linklist_mode:1;
+        /** debug_direct_out_en : R/W; bitpos: [7]; default: 0;
+         *  0:normal mode,1:debug mode for direct output from input
+         */
+        uint32_t debug_direct_out_en:1;
+        /** qnr_fifo_en : R/W; bitpos: [8]; default: 1;
+         *  0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram
+         */
+        uint32_t qnr_fifo_en:1;
+        /** lqnr_tbl_sel : R/W; bitpos: [10:9]; default: 0;
+         *  choose  luminance quntization table id(TBD)
+         */
+        uint32_t lqnr_tbl_sel:2;
+        /** cqnr_tbl_sel : R/W; bitpos: [12:11]; default: 1;
+         *  choose  chrominance quntization table id (TBD)
+         */
+        uint32_t cqnr_tbl_sel:2;
+        /** color_space : R/W; bitpos: [14:13]; default: 0;
+         *  configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray
+         */
+        uint32_t color_space:2;
+        /** dht_fifo_en : R/W; bitpos: [15]; default: 1;
+         *  0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to
+         *  write dht len_total/codemin/value table. Reading dht len_total/codemin/value table
+         *  only has nonfifo way
+         */
+        uint32_t dht_fifo_en:1;
+        /** mem_clk_force_on : R/W; bitpos: [16]; default: 0;
+         *  force memory's clock enabled
+         */
+        uint32_t mem_clk_force_on:1;
+        /** jfif_ver : R/W; bitpos: [22:17]; default: 32;
+         *  decode pause period to trigger decode_timeout int, the timeout periods =2 power
+         *  (reg_decode_timeout_thres) -1
+         */
+        uint32_t jfif_ver:6;
+        /** decode_timeout_task_sel : R/W; bitpos: [23]; default: 0;
+         *  0: software use reset to abort decode process ,1: decoder abort decode process by
+         *  itself
+         */
+        uint32_t decode_timeout_task_sel:1;
+        /** soft_rst : R/W; bitpos: [24]; default: 0;
+         *  when set to 1, soft reset JPEG module except jpeg_reg module
+         */
+        uint32_t soft_rst:1;
+        /** fifo_rst : R/W; bitpos: [25]; default: 0;
+         *  fifo reset
+         */
+        uint32_t fifo_rst:1;
+        /** pixel_rev : R/W; bitpos: [26]; default: 0;
+         *  reverse the source color pixel
+         */
+        uint32_t pixel_rev:1;
+        /** tailer_en : R/W; bitpos: [27]; default: 0;
+         *  set this bit to add EOI of "0xffd9" at the end of bitstream
+         */
+        uint32_t tailer_en:1;
+        /** pause_en : R/W; bitpos: [28]; default: 0;
+         *  set this bit to pause jpeg encoding
+         */
+        uint32_t pause_en:1;
+        /** mem_force_pd : R/W; bitpos: [29]; default: 0;
+         *  0: no operation,1:force jpeg memory to power down
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [30]; default: 0;
+         *  0: no operation,1:force jpeg memory to power up
+         */
+        uint32_t mem_force_pu:1;
+        /** mode : R/W; bitpos: [31]; default: 0;
+         *  0:encoder mode, 1: decoder mode
+         */
+        uint32_t mode:1;
+    };
+    uint32_t val;
+} jpeg_config_reg_t;
+
+/** Type of dqt_info register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** t0_dqt_info : R/W; bitpos: [7:0]; default: 0;
+         *  Configure dqt table0's quantization coefficient precision in bit[7:4], configure
+         *  dqt table0's table id in bit[3:0]
+         */
+        uint32_t t0_dqt_info:8;
+        /** t1_dqt_info : R/W; bitpos: [15:8]; default: 1;
+         *  Configure dqt table1's quantization coefficient precision in bit[7:4], configure
+         *  dqt table1's table id in bit[3:0]
+         */
+        uint32_t t1_dqt_info:8;
+        /** t2_dqt_info : R/W; bitpos: [23:16]; default: 2;
+         *  Configure dqt table2's quantization coefficient precision in bit[7:4], configure
+         *  dqt table2's table id in bit[3:0]
+         */
+        uint32_t t2_dqt_info:8;
+        /** t3_dqt_info : R/W; bitpos: [31:24]; default: 3;
+         *  Configure dqt table3's quantization coefficient precision in bit[7:4], configure
+         *  dqt table3's table id in bit[3:0]
+         */
+        uint32_t t3_dqt_info:8;
+    };
+    uint32_t val;
+} jpeg_dqt_info_reg_t;
+
+/** Type of pic_size register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** va : R/W; bitpos: [15:0]; default: 480;
+         *  configure picture's height. when encode, the max configurable bits is 14, when
+         *  decode, the max configurable bits is 16
+         */
+        uint32_t va:16;
+        /** ha : R/W; bitpos: [31:16]; default: 640;
+         *  configure picture's width. when encode, the max configurable bits is 14, when
+         *  decode, the max configurable bits is 16
+         */
+        uint32_t ha:16;
+    };
+    uint32_t val;
+} jpeg_pic_size_reg_t;
+
+/** Type of t0qnr register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** t0_qnr_val : HRO; bitpos: [31:0]; default: 0;
+         *  write this reg to configure 64 quantization coefficient in t0 table
+         */
+        uint32_t t0_qnr_val:32;
+    };
+    uint32_t val;
+} jpeg_t0qnr_reg_t;
+
+/** Type of t1qnr register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chrominance_qnr_val : HRO; bitpos: [31:0]; default: 0;
+         *  write this reg to configure 64 quantization coefficient in t1 table
+         */
+        uint32_t chrominance_qnr_val:32;
+    };
+    uint32_t val;
+} jpeg_t1qnr_reg_t;
+
+/** Type of t2qnr register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** t2_qnr_val : HRO; bitpos: [31:0]; default: 0;
+         *  write this reg to configure 64 quantization coefficient in t2 table
+         */
+        uint32_t t2_qnr_val:32;
+    };
+    uint32_t val;
+} jpeg_t2qnr_reg_t;
+
+/** Type of t3qnr register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** t3_qnr_val : HRO; bitpos: [31:0]; default: 0;
+         *  write this reg to configure 64 quantization coefficient in t3 table
+         */
+        uint32_t t3_qnr_val:32;
+    };
+    uint32_t val;
+} jpeg_t3qnr_reg_t;
+
+/** Type of decode_conf register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** restart_interval : R/W; bitpos: [15:0]; default: 0;
+         *  configure restart interval in DRI marker when decode
+         */
+        uint32_t restart_interval:16;
+        /** component_num : R/W; bitpos: [23:16]; default: 3;
+         *  configure number of components in frame when decode
+         */
+        uint32_t component_num:8;
+        /** sw_dht_en : RO; bitpos: [24]; default: 1;
+         *  software decode dht table enable
+         */
+        uint32_t sw_dht_en:1;
+        /** sos_check_byte_num : R/W; bitpos: [26:25]; default: 3;
+         *  Configure the byte number to check next sos marker in the multi-scan picture after
+         *  one scan is decoded down. The real check number is reg_sos_check_byte_num+1
+         */
+        uint32_t sos_check_byte_num:2;
+        /** rst_check_byte_num : R/W; bitpos: [28:27]; default: 3;
+         *  Configure the byte number to check next rst marker after one rst interval is
+         *  decoded down. The real check number is reg_rst_check_byte_num+1
+         */
+        uint32_t rst_check_byte_num:2;
+        /** multi_scan_err_check : R/W; bitpos: [29]; default: 0;
+         *  reserved for decoder
+         */
+        uint32_t multi_scan_err_check:1;
+        /** dezigzag_ready_ctl : R/W; bitpos: [30]; default: 1;
+         *  reserved for decoder
+         */
+        uint32_t dezigzag_ready_ctl:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} jpeg_decode_conf_reg_t;
+
+/** Type of c0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** c0_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0;
+         *  choose  c0 quntization table id (TBD)
+         */
+        uint32_t c0_dqt_tbl_sel:8;
+        /** c0_y_factor : R/W; bitpos: [11:8]; default: 1;
+         *  vertical sampling factor of c0
+         */
+        uint32_t c0_y_factor:4;
+        /** c0_x_factor : R/W; bitpos: [15:12]; default: 1;
+         *  horizontal sampling factor of c0
+         */
+        uint32_t c0_x_factor:4;
+        /** c0_id : R/W; bitpos: [23:16]; default: 0;
+         *  the identifier of c0
+         */
+        uint32_t c0_id:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} jpeg_c0_reg_t;
+
+/** Type of c1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** c1_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0;
+         *  choose  c1 quntization table id (TBD)
+         */
+        uint32_t c1_dqt_tbl_sel:8;
+        /** c1_y_factor : R/W; bitpos: [11:8]; default: 1;
+         *  vertical sampling factor of c1
+         */
+        uint32_t c1_y_factor:4;
+        /** c1_x_factor : R/W; bitpos: [15:12]; default: 1;
+         *  horizontal sampling factor of c1
+         */
+        uint32_t c1_x_factor:4;
+        /** c1_id : R/W; bitpos: [23:16]; default: 0;
+         *  the identifier of c1
+         */
+        uint32_t c1_id:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} jpeg_c1_reg_t;
+
+/** Type of c2 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** c2_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0;
+         *  choose  c2 quntization table id (TBD)
+         */
+        uint32_t c2_dqt_tbl_sel:8;
+        /** c2_y_factor : R/W; bitpos: [11:8]; default: 1;
+         *  vertical sampling factor of c2
+         */
+        uint32_t c2_y_factor:4;
+        /** c2_x_factor : R/W; bitpos: [15:12]; default: 1;
+         *  horizontal sampling factor of c2
+         */
+        uint32_t c2_x_factor:4;
+        /** c2_id : R/W; bitpos: [23:16]; default: 0;
+         *  the identifier of c2
+         */
+        uint32_t c2_id:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} jpeg_c2_reg_t;
+
+/** Type of c3 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** c3_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0;
+         *  choose  c3 quntization table id (TBD)
+         */
+        uint32_t c3_dqt_tbl_sel:8;
+        /** c3_y_factor : R/W; bitpos: [11:8]; default: 1;
+         *  vertical sampling factor of c3
+         */
+        uint32_t c3_y_factor:4;
+        /** c3_x_factor : R/W; bitpos: [15:12]; default: 1;
+         *  horizontal sampling factor of c3
+         */
+        uint32_t c3_x_factor:4;
+        /** c3_id : R/W; bitpos: [23:16]; default: 0;
+         *  the identifier of c3
+         */
+        uint32_t c3_id:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} jpeg_c3_reg_t;
+
+/** Type of dht_info register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** dc0_dht_id : R/W; bitpos: [3:0]; default: 0;
+         *  configure dht dc table 0 id
+         */
+        uint32_t dc0_dht_id:4;
+        /** dc1_dht_id : R/W; bitpos: [7:4]; default: 1;
+         *  configure dht dc table 1 id
+         */
+        uint32_t dc1_dht_id:4;
+        /** ac0_dht_id : R/W; bitpos: [11:8]; default: 0;
+         *  configure dht ac table 0 id
+         */
+        uint32_t ac0_dht_id:4;
+        /** ac1_dht_id : R/W; bitpos: [15:12]; default: 1;
+         *  configure dht ac table 1 id
+         */
+        uint32_t ac1_dht_id:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} jpeg_dht_info_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Interrupt raw registers
+ */
+typedef union {
+    struct {
+        /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This raw interrupt bit turns to high level when JPEG finishes encoding a picture..
+         */
+        uint32_t done_int_raw:1;
+        /** rle_parallel_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit to sign that rle parallel error when decoding.
+         */
+        uint32_t rle_parallel_err_int_raw:1;
+        /** cid_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit to sign that scan id check with component fails when decoding.
+         */
+        uint32_t cid_err_int_raw:1;
+        /** c_dht_dc_id_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit to sign that scan component's dc dht id check with dc dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_dc_id_err_int_raw:1;
+        /** c_dht_ac_id_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit to sign that scan component's ac dht id check with ac dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_ac_id_err_int_raw:1;
+        /** c_dqt_id_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit to sign that scan component's dqt id check with dqt table's
+         *  id fails when decoding.
+         */
+        uint32_t c_dqt_id_err_int_raw:1;
+        /** rst_uxp_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit to sign that RST header marker is detected but restart
+         *  interval is 0 when decoding.
+         */
+        uint32_t rst_uxp_err_int_raw:1;
+        /** rst_check_none_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit to sign that RST header marker is not detected but restart
+         *  interval is not 0 when decoding.
+         */
+        uint32_t rst_check_none_err_int_raw:1;
+        /** rst_check_pos_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit to sign that RST header marker position mismatches with
+         *  restart interval when decoding.
+         */
+        uint32_t rst_check_pos_err_int_raw:1;
+        /** out_eof_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when the last pixel of one square has
+         *  been transmitted for Tx channel.
+         */
+        uint32_t out_eof_int_raw:1;
+        /** sr_color_mode_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit to sign that the selected source color mode is not supported.
+         */
+        uint32_t sr_color_mode_err_int_raw:1;
+        /** dct_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit to sign that one dct calculation is finished.
+         */
+        uint32_t dct_done_int_raw:1;
+        /** bs_last_block_eof_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit to sign that the coding process for last block is finished.
+         */
+        uint32_t bs_last_block_eof_int_raw:1;
+        /** scan_check_none_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit to sign that SOS header marker is not detected but there are
+         *  still components left to be decoded.
+         */
+        uint32_t scan_check_none_err_int_raw:1;
+        /** scan_check_pos_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw interrupt bit to sign that SOS header marker position wrong when decoding.
+         */
+        uint32_t scan_check_pos_err_int_raw:1;
+        /** uxp_det_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw interrupt bit to sign that unsupported header marker is detected when
+         *  decoding.
+         */
+        uint32_t uxp_det_int_raw:1;
+        /** en_frame_eof_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw interrupt bit to sign that received pixel blocks are smaller than expected
+         *  when encoding.
+         */
+        uint32_t en_frame_eof_err_int_raw:1;
+        /** en_frame_eof_lack_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw interrupt bit to sign that the frame eof sign bit from dma input is missing
+         *  when encoding. But the number of pixel blocks is enough.
+         */
+        uint32_t en_frame_eof_lack_int_raw:1;
+        /** de_frame_eof_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw interrupt bit to sign that decoded blocks are smaller than expected when
+         *  decoding.
+         */
+        uint32_t de_frame_eof_err_int_raw:1;
+        /** de_frame_eof_lack_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw interrupt bit to sign that the either frame eof from dma input or eoi
+         *  marker is missing when encoding. But the number of decoded blocks is enough.
+         */
+        uint32_t de_frame_eof_lack_int_raw:1;
+        /** sos_unmatch_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw interrupt bit to sign that the component number of a scan is 0 or does not
+         *  match the sos marker's length when decoding.
+         */
+        uint32_t sos_unmatch_err_int_raw:1;
+        /** marker_err_fst_scan_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  The raw interrupt bit to sign that the first scan has header marker error when
+         *  decoding.
+         */
+        uint32_t marker_err_fst_scan_int_raw:1;
+        /** marker_err_other_scan_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  The raw interrupt bit to sign that the following scans but not the first scan have
+         *  header marker error when decoding.
+         */
+        uint32_t marker_err_other_scan_int_raw:1;
+        /** undet_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  The raw interrupt bit to sign that JPEG format is not detected at the eof data of a
+         *  packet when decoding.
+         */
+        uint32_t undet_int_raw:1;
+        /** decode_timeout_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  The raw interrupt bit to sign that decode pause time is longer than the setting
+         *  decode timeout time when decoding.
+         */
+        uint32_t decode_timeout_int_raw:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} jpeg_int_raw_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable registers
+ */
+typedef union {
+    struct {
+        /** done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This enable interrupt bit turns to high level when JPEG finishes encoding a
+         *  picture..
+         */
+        uint32_t done_int_ena:1;
+        /** rle_parallel_err_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable interrupt bit to sign that rle parallel error when decoding.
+         */
+        uint32_t rle_parallel_err_int_ena:1;
+        /** cid_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable interrupt bit to sign that scan id check with component fails when
+         *  decoding.
+         */
+        uint32_t cid_err_int_ena:1;
+        /** c_dht_dc_id_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable interrupt bit to sign that scan component's dc dht id check with dc dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_dc_id_err_int_ena:1;
+        /** c_dht_ac_id_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable interrupt bit to sign that scan component's ac dht id check with ac dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_ac_id_err_int_ena:1;
+        /** c_dqt_id_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The enable interrupt bit to sign that scan component's dqt id check with dqt
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dqt_id_err_int_ena:1;
+        /** rst_uxp_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The enable interrupt bit to sign that RST header marker is detected but restart
+         *  interval is 0 when decoding.
+         */
+        uint32_t rst_uxp_err_int_ena:1;
+        /** rst_check_none_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The enable interrupt bit to sign that RST header marker is not detected but restart
+         *  interval is not 0 when decoding.
+         */
+        uint32_t rst_check_none_err_int_ena:1;
+        /** rst_check_pos_err_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The enable interrupt bit to sign that RST header marker position mismatches with
+         *  restart interval when decoding.
+         */
+        uint32_t rst_check_pos_err_int_ena:1;
+        /** out_eof_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The enable interrupt bit turns to high level when the last pixel of one square has
+         *  been transmitted for Tx channel.
+         */
+        uint32_t out_eof_int_ena:1;
+        /** sr_color_mode_err_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The enable interrupt bit to sign that the selected source color mode is not
+         *  supported.
+         */
+        uint32_t sr_color_mode_err_int_ena:1;
+        /** dct_done_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The enable interrupt bit to sign that one dct calculation is finished.
+         */
+        uint32_t dct_done_int_ena:1;
+        /** bs_last_block_eof_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The enable interrupt bit to sign that the coding process for last block is finished.
+         */
+        uint32_t bs_last_block_eof_int_ena:1;
+        /** scan_check_none_err_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The enable interrupt bit to sign that SOS header marker is not detected but there
+         *  are still components left to be decoded.
+         */
+        uint32_t scan_check_none_err_int_ena:1;
+        /** scan_check_pos_err_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The enable interrupt bit to sign that SOS header marker position wrong when
+         *  decoding.
+         */
+        uint32_t scan_check_pos_err_int_ena:1;
+        /** uxp_det_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The enable interrupt bit to sign that unsupported header marker is detected when
+         *  decoding.
+         */
+        uint32_t uxp_det_int_ena:1;
+        /** en_frame_eof_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The enable interrupt bit to sign that received pixel blocks are smaller than
+         *  expected when encoding.
+         */
+        uint32_t en_frame_eof_err_int_ena:1;
+        /** en_frame_eof_lack_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The enable interrupt bit to sign that the frame eof sign bit from dma input is
+         *  missing when encoding. But the number of pixel blocks is enough.
+         */
+        uint32_t en_frame_eof_lack_int_ena:1;
+        /** de_frame_eof_err_int_ena : R/W; bitpos: [18]; default: 0;
+         *  The enable interrupt bit to sign that decoded blocks are smaller than expected when
+         *  decoding.
+         */
+        uint32_t de_frame_eof_err_int_ena:1;
+        /** de_frame_eof_lack_int_ena : R/W; bitpos: [19]; default: 0;
+         *  The enable interrupt bit to sign that the either frame eof from dma input or eoi
+         *  marker is missing when encoding. But the number of decoded blocks is enough.
+         */
+        uint32_t de_frame_eof_lack_int_ena:1;
+        /** sos_unmatch_err_int_ena : R/W; bitpos: [20]; default: 0;
+         *  The enable interrupt bit to sign that the component number of a scan is 0 or does
+         *  not match the sos marker's length when decoding.
+         */
+        uint32_t sos_unmatch_err_int_ena:1;
+        /** marker_err_fst_scan_int_ena : R/W; bitpos: [21]; default: 0;
+         *  The enable interrupt bit to sign that the first scan has header marker error when
+         *  decoding.
+         */
+        uint32_t marker_err_fst_scan_int_ena:1;
+        /** marker_err_other_scan_int_ena : R/W; bitpos: [22]; default: 0;
+         *  The enable interrupt bit to sign that the following scans but not the first scan
+         *  have header marker error when decoding.
+         */
+        uint32_t marker_err_other_scan_int_ena:1;
+        /** undet_int_ena : R/W; bitpos: [23]; default: 0;
+         *  The enable interrupt bit to sign that JPEG format is not detected at the eof data
+         *  of a packet when decoding.
+         */
+        uint32_t undet_int_ena:1;
+        /** decode_timeout_int_ena : R/W; bitpos: [24]; default: 0;
+         *  The enable interrupt bit to sign that decode pause time is longer than the setting
+         *  decode timeout time when decoding.
+         */
+        uint32_t decode_timeout_int_ena:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} jpeg_int_ena_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status registers
+ */
+typedef union {
+    struct {
+        /** done_int_st : RO; bitpos: [0]; default: 0;
+         *  This status interrupt bit turns to high level when JPEG finishes encoding a
+         *  picture..
+         */
+        uint32_t done_int_st:1;
+        /** rle_parallel_err_int_st : RO; bitpos: [1]; default: 0;
+         *  The status interrupt bit to sign that rle parallel error when decoding.
+         */
+        uint32_t rle_parallel_err_int_st:1;
+        /** cid_err_int_st : RO; bitpos: [2]; default: 0;
+         *  The status interrupt bit to sign that scan id check with component fails when
+         *  decoding.
+         */
+        uint32_t cid_err_int_st:1;
+        /** c_dht_dc_id_err_int_st : RO; bitpos: [3]; default: 0;
+         *  The status interrupt bit to sign that scan component's dc dht id check with dc dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_dc_id_err_int_st:1;
+        /** c_dht_ac_id_err_int_st : RO; bitpos: [4]; default: 0;
+         *  The status interrupt bit to sign that scan component's ac dht id check with ac dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_ac_id_err_int_st:1;
+        /** c_dqt_id_err_int_st : RO; bitpos: [5]; default: 0;
+         *  The status interrupt bit to sign that scan component's dqt id check with dqt
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dqt_id_err_int_st:1;
+        /** rst_uxp_err_int_st : RO; bitpos: [6]; default: 0;
+         *  The status interrupt bit to sign that RST header marker is detected but restart
+         *  interval is 0 when decoding.
+         */
+        uint32_t rst_uxp_err_int_st:1;
+        /** rst_check_none_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The status interrupt bit to sign that RST header marker is not detected but restart
+         *  interval is not 0 when decoding.
+         */
+        uint32_t rst_check_none_err_int_st:1;
+        /** rst_check_pos_err_int_st : RO; bitpos: [8]; default: 0;
+         *  The status interrupt bit to sign that RST header marker position mismatches with
+         *  restart interval when decoding.
+         */
+        uint32_t rst_check_pos_err_int_st:1;
+        /** out_eof_int_st : RO; bitpos: [9]; default: 0;
+         *  The status interrupt bit turns to high level when the last pixel of one square has
+         *  been transmitted for Tx channel.
+         */
+        uint32_t out_eof_int_st:1;
+        /** sr_color_mode_err_int_st : RO; bitpos: [10]; default: 0;
+         *  The status interrupt bit to sign that the selected source color mode is not
+         *  supported.
+         */
+        uint32_t sr_color_mode_err_int_st:1;
+        /** dct_done_int_st : RO; bitpos: [11]; default: 0;
+         *  The status interrupt bit to sign that one dct calculation is finished.
+         */
+        uint32_t dct_done_int_st:1;
+        /** bs_last_block_eof_int_st : RO; bitpos: [12]; default: 0;
+         *  The status interrupt bit to sign that the coding process for last block is finished.
+         */
+        uint32_t bs_last_block_eof_int_st:1;
+        /** scan_check_none_err_int_st : RO; bitpos: [13]; default: 0;
+         *  The status interrupt bit to sign that SOS header marker is not detected but there
+         *  are still components left to be decoded.
+         */
+        uint32_t scan_check_none_err_int_st:1;
+        /** scan_check_pos_err_int_st : RO; bitpos: [14]; default: 0;
+         *  The status interrupt bit to sign that SOS header marker position wrong when
+         *  decoding.
+         */
+        uint32_t scan_check_pos_err_int_st:1;
+        /** uxp_det_int_st : RO; bitpos: [15]; default: 0;
+         *  The status interrupt bit to sign that unsupported header marker is detected when
+         *  decoding.
+         */
+        uint32_t uxp_det_int_st:1;
+        /** en_frame_eof_err_int_st : RO; bitpos: [16]; default: 0;
+         *  The status interrupt bit to sign that received pixel blocks are smaller than
+         *  expected when encoding.
+         */
+        uint32_t en_frame_eof_err_int_st:1;
+        /** en_frame_eof_lack_int_st : RO; bitpos: [17]; default: 0;
+         *  The status interrupt bit to sign that the frame eof sign bit from dma input is
+         *  missing when encoding. But the number of pixel blocks is enough.
+         */
+        uint32_t en_frame_eof_lack_int_st:1;
+        /** de_frame_eof_err_int_st : RO; bitpos: [18]; default: 0;
+         *  The status interrupt bit to sign that decoded blocks are smaller than expected when
+         *  decoding.
+         */
+        uint32_t de_frame_eof_err_int_st:1;
+        /** de_frame_eof_lack_int_st : RO; bitpos: [19]; default: 0;
+         *  The status interrupt bit to sign that the either frame eof from dma input or eoi
+         *  marker is missing when encoding. But the number of decoded blocks is enough.
+         */
+        uint32_t de_frame_eof_lack_int_st:1;
+        /** sos_unmatch_err_int_st : RO; bitpos: [20]; default: 0;
+         *  The status interrupt bit to sign that the component number of a scan is 0 or does
+         *  not match the sos marker's length when decoding.
+         */
+        uint32_t sos_unmatch_err_int_st:1;
+        /** marker_err_fst_scan_int_st : RO; bitpos: [21]; default: 0;
+         *  The status interrupt bit to sign that the first scan has header marker error when
+         *  decoding.
+         */
+        uint32_t marker_err_fst_scan_int_st:1;
+        /** marker_err_other_scan_int_st : RO; bitpos: [22]; default: 0;
+         *  The status interrupt bit to sign that the following scans but not the first scan
+         *  have header marker error when decoding.
+         */
+        uint32_t marker_err_other_scan_int_st:1;
+        /** undet_int_st : RO; bitpos: [23]; default: 0;
+         *  The status interrupt bit to sign that JPEG format is not detected at the eof data
+         *  of a packet when decoding.
+         */
+        uint32_t undet_int_st:1;
+        /** decode_timeout_int_st : RO; bitpos: [24]; default: 0;
+         *  The status interrupt bit to sign that decode pause time is longer than the setting
+         *  decode timeout time when decoding.
+         */
+        uint32_t decode_timeout_int_st:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} jpeg_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear registers
+ */
+typedef union {
+    struct {
+        /** done_int_clr : WT; bitpos: [0]; default: 0;
+         *  This clear interrupt bit turns to high level when JPEG finishes encoding a picture..
+         */
+        uint32_t done_int_clr:1;
+        /** rle_parallel_err_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear interrupt bit to sign that rle parallel error when decoding.
+         */
+        uint32_t rle_parallel_err_int_clr:1;
+        /** cid_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear interrupt bit to sign that scan id check with component fails when
+         *  decoding.
+         */
+        uint32_t cid_err_int_clr:1;
+        /** c_dht_dc_id_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear interrupt bit to sign that scan component's dc dht id check with dc dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_dc_id_err_int_clr:1;
+        /** c_dht_ac_id_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear interrupt bit to sign that scan component's ac dht id check with ac dht
+         *  table's id fails when decoding.
+         */
+        uint32_t c_dht_ac_id_err_int_clr:1;
+        /** c_dqt_id_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  The clear interrupt bit to sign that scan component's dqt id check with dqt table's
+         *  id fails when decoding.
+         */
+        uint32_t c_dqt_id_err_int_clr:1;
+        /** rst_uxp_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  The clear interrupt bit to sign that RST header marker is detected but restart
+         *  interval is 0 when decoding.
+         */
+        uint32_t rst_uxp_err_int_clr:1;
+        /** rst_check_none_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  The clear interrupt bit to sign that RST header marker is not detected but restart
+         *  interval is not 0 when decoding.
+         */
+        uint32_t rst_check_none_err_int_clr:1;
+        /** rst_check_pos_err_int_clr : WT; bitpos: [8]; default: 0;
+         *  The clear interrupt bit to sign that RST header marker position mismatches with
+         *  restart interval when decoding.
+         */
+        uint32_t rst_check_pos_err_int_clr:1;
+        /** out_eof_int_clr : WT; bitpos: [9]; default: 0;
+         *  The clear interrupt bit turns to high level when the last pixel of one square has
+         *  been transmitted for Tx channel.
+         */
+        uint32_t out_eof_int_clr:1;
+        /** sr_color_mode_err_int_clr : WT; bitpos: [10]; default: 0;
+         *  The clear interrupt bit to sign that the selected source color mode is not
+         *  supported.
+         */
+        uint32_t sr_color_mode_err_int_clr:1;
+        /** dct_done_int_clr : WT; bitpos: [11]; default: 0;
+         *  The clear interrupt bit to sign that one dct calculation is finished.
+         */
+        uint32_t dct_done_int_clr:1;
+        /** bs_last_block_eof_int_clr : WT; bitpos: [12]; default: 0;
+         *  The clear interrupt bit to sign that the coding process for last block is finished.
+         */
+        uint32_t bs_last_block_eof_int_clr:1;
+        /** scan_check_none_err_int_clr : WT; bitpos: [13]; default: 0;
+         *  The clear interrupt bit to sign that SOS header marker is not detected but there
+         *  are still components left to be decoded.
+         */
+        uint32_t scan_check_none_err_int_clr:1;
+        /** scan_check_pos_err_int_clr : WT; bitpos: [14]; default: 0;
+         *  The clear interrupt bit to sign that SOS header marker position wrong when decoding.
+         */
+        uint32_t scan_check_pos_err_int_clr:1;
+        /** uxp_det_int_clr : WT; bitpos: [15]; default: 0;
+         *  The clear interrupt bit to sign that unsupported header marker is detected when
+         *  decoding.
+         */
+        uint32_t uxp_det_int_clr:1;
+        /** en_frame_eof_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  The clear interrupt bit to sign that received pixel blocks are smaller than
+         *  expected when encoding.
+         */
+        uint32_t en_frame_eof_err_int_clr:1;
+        /** en_frame_eof_lack_int_clr : WT; bitpos: [17]; default: 0;
+         *  The clear interrupt bit to sign that the frame eof sign bit from dma input is
+         *  missing when encoding. But the number of pixel blocks is enough.
+         */
+        uint32_t en_frame_eof_lack_int_clr:1;
+        /** de_frame_eof_err_int_clr : WT; bitpos: [18]; default: 0;
+         *  The clear interrupt bit to sign that decoded blocks are smaller than expected when
+         *  decoding.
+         */
+        uint32_t de_frame_eof_err_int_clr:1;
+        /** de_frame_eof_lack_int_clr : WT; bitpos: [19]; default: 0;
+         *  The clear interrupt bit to sign that the either frame eof from dma input or eoi
+         *  marker is missing when encoding. But the number of decoded blocks is enough.
+         */
+        uint32_t de_frame_eof_lack_int_clr:1;
+        /** sos_unmatch_err_int_clr : WT; bitpos: [20]; default: 0;
+         *  The clear interrupt bit to sign that the component number of a scan is 0 or does
+         *  not match the sos marker's length when decoding.
+         */
+        uint32_t sos_unmatch_err_int_clr:1;
+        /** marker_err_fst_scan_int_clr : WT; bitpos: [21]; default: 0;
+         *  The clear interrupt bit to sign that the first scan has header marker error when
+         *  decoding.
+         */
+        uint32_t marker_err_fst_scan_int_clr:1;
+        /** marker_err_other_scan_int_clr : WT; bitpos: [22]; default: 0;
+         *  The clear interrupt bit to sign that the following scans but not the first scan
+         *  have header marker error when decoding.
+         */
+        uint32_t marker_err_other_scan_int_clr:1;
+        /** undet_int_clr : WT; bitpos: [23]; default: 0;
+         *  The clear interrupt bit to sign that JPEG format is not detected at the eof data of
+         *  a packet when decoding.
+         */
+        uint32_t undet_int_clr:1;
+        /** decode_timeout_int_clr : WT; bitpos: [24]; default: 0;
+         *  The clear interrupt bit to sign that decode pause time is longer than the setting
+         *  decode timeout time when decoding.
+         */
+        uint32_t decode_timeout_int_clr:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} jpeg_int_clr_reg_t;
+
+
+/** Group: Trace and Debug registers */
+/** Type of status0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:11;
+        /** bitstream_eof_vld_cnt : RO; bitpos: [16:11]; default: 0;
+         *  the valid bit count for last bitstream
+         */
+        uint32_t bitstream_eof_vld_cnt:6;
+        /** dctout_zzscan_addr : RO; bitpos: [22:17]; default: 0;
+         *  the zig-zag read addr from dctout_ram
+         */
+        uint32_t dctout_zzscan_addr:6;
+        /** qnrval_zzscan_addr : RO; bitpos: [28:23]; default: 0;
+         *  the zig-zag read addr from qnrval_ram
+         */
+        uint32_t qnrval_zzscan_addr:6;
+        /** reg_state_yuv : RO; bitpos: [31:29]; default: 0;
+         *  the state of jpeg fsm
+         */
+        uint32_t reg_state_yuv:3;
+    };
+    uint32_t val;
+} jpeg_status0_reg_t;
+
+/** Type of status2 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** source_pixel : RO; bitpos: [23:0]; default: 0;
+         *  source pixels fetched from dma
+         */
+        uint32_t source_pixel:24;
+        /** last_block : RO; bitpos: [24]; default: 0;
+         *  indicate the encoding process for the last mcu of the picture
+         */
+        uint32_t last_block:1;
+        /** last_mcu : RO; bitpos: [25]; default: 0;
+         *  indicate the encoding process for the last block of the picture
+         */
+        uint32_t last_mcu:1;
+        /** last_dc : RO; bitpos: [26]; default: 0;
+         *  indicate the encoding process is at the header of the last block of the picture
+         */
+        uint32_t last_dc:1;
+        /** packfifo_ready : RO; bitpos: [27]; default: 1;
+         *  the jpeg pack_fifo ready signal, high active
+         */
+        uint32_t packfifo_ready:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} jpeg_status2_reg_t;
+
+/** Type of status3 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** yo : RO; bitpos: [8:0]; default: 0;
+         *  component y transferred from rgb input
+         */
+        uint32_t yo:9;
+        /** y_ready : RO; bitpos: [9]; default: 0;
+         *  component y valid signal, high active
+         */
+        uint32_t y_ready:1;
+        /** cbo : RO; bitpos: [18:10]; default: 0;
+         *  component cb transferred from rgb input
+         */
+        uint32_t cbo:9;
+        /** cb_ready : RO; bitpos: [19]; default: 0;
+         *  component cb valid signal, high active
+         */
+        uint32_t cb_ready:1;
+        /** cro : RO; bitpos: [28:20]; default: 0;
+         *  component cr transferred from rgb input
+         */
+        uint32_t cro:9;
+        /** cr_ready : RO; bitpos: [29]; default: 0;
+         *  component cr valid signal, high active
+         */
+        uint32_t cr_ready:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} jpeg_status3_reg_t;
+
+/** Type of status4 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** hfm_bitstream : RO; bitpos: [31:0]; default: 0;
+         *  the hufman bitstream during encoding process
+         */
+        uint32_t hfm_bitstream:32;
+    };
+    uint32_t val;
+} jpeg_status4_reg_t;
+
+/** Type of dht_totlen_dc0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_totlen_dc0 : HRO; bitpos: [31:0]; default: 0;
+         *  write the numbers of 1~n codeword length sum from 1~16 of dc0 table
+         */
+        uint32_t dht_totlen_dc0:32;
+    };
+    uint32_t val;
+} jpeg_dht_totlen_dc0_reg_t;
+
+/** Type of dht_val_dc0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_val_dc0 : HRO; bitpos: [31:0]; default: 0;
+         *  write codeword corresponding huffman values of dc0 table
+         */
+        uint32_t dht_val_dc0:32;
+    };
+    uint32_t val;
+} jpeg_dht_val_dc0_reg_t;
+
+/** Type of dht_totlen_ac0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_totlen_ac0 : HRO; bitpos: [31:0]; default: 0;
+         *  write the numbers of 1~n codeword length sum from 1~16 of ac0 table
+         */
+        uint32_t dht_totlen_ac0:32;
+    };
+    uint32_t val;
+} jpeg_dht_totlen_ac0_reg_t;
+
+/** Type of dht_val_ac0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_val_ac0 : HRO; bitpos: [31:0]; default: 0;
+         *  write codeword corresponding huffman values of ac0 table
+         */
+        uint32_t dht_val_ac0:32;
+    };
+    uint32_t val;
+} jpeg_dht_val_ac0_reg_t;
+
+/** Type of dht_totlen_dc1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_totlen_dc1 : HRO; bitpos: [31:0]; default: 0;
+         *  write the numbers of 1~n codeword length sum from 1~16 of dc1 table
+         */
+        uint32_t dht_totlen_dc1:32;
+    };
+    uint32_t val;
+} jpeg_dht_totlen_dc1_reg_t;
+
+/** Type of dht_val_dc1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_val_dc1 : HRO; bitpos: [31:0]; default: 0;
+         *  write codeword corresponding huffman values of dc1 table
+         */
+        uint32_t dht_val_dc1:32;
+    };
+    uint32_t val;
+} jpeg_dht_val_dc1_reg_t;
+
+/** Type of dht_totlen_ac1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_totlen_ac1 : HRO; bitpos: [31:0]; default: 0;
+         *  write the numbers of 1~n codeword length sum from 1~16 of ac1 table
+         */
+        uint32_t dht_totlen_ac1:32;
+    };
+    uint32_t val;
+} jpeg_dht_totlen_ac1_reg_t;
+
+/** Type of dht_val_ac1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_val_ac1 : HRO; bitpos: [31:0]; default: 0;
+         *  write codeword corresponding huffman values of ac1 table
+         */
+        uint32_t dht_val_ac1:32;
+    };
+    uint32_t val;
+} jpeg_dht_val_ac1_reg_t;
+
+/** Type of dht_codemin_dc0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_codemin_dc0 : HRO; bitpos: [31:0]; default: 0;
+         *  write the minimum codeword of  code length from 1~16 of dc0 table. The codeword is
+         *  left shifted to the MSB position of a 16bit word
+         */
+        uint32_t dht_codemin_dc0:32;
+    };
+    uint32_t val;
+} jpeg_dht_codemin_dc0_reg_t;
+
+/** Type of dht_codemin_ac0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_codemin_ac0 : HRO; bitpos: [31:0]; default: 0;
+         *  write the minimum codeword of  code length from 1~16 of ac0 table. The codeword is
+         *  left shifted to the MSB position of a 16bit word
+         */
+        uint32_t dht_codemin_ac0:32;
+    };
+    uint32_t val;
+} jpeg_dht_codemin_ac0_reg_t;
+
+/** Type of dht_codemin_dc1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_codemin_dc1 : HRO; bitpos: [31:0]; default: 0;
+         *  write the minimum codeword of  code length from 1~16 of dc1 table. The codeword is
+         *  left shifted to the MSB position of a 16bit word
+         */
+        uint32_t dht_codemin_dc1:32;
+    };
+    uint32_t val;
+} jpeg_dht_codemin_dc1_reg_t;
+
+/** Type of dht_codemin_ac1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** dht_codemin_ac1 : HRO; bitpos: [31:0]; default: 0;
+         *  write the minimum codeword of  code length from 1~16 of ac1 table. The codeword is
+         *  left shifted to the MSB position of a 16bit word
+         */
+        uint32_t dht_codemin_ac1:32;
+    };
+    uint32_t val;
+} jpeg_dht_codemin_ac1_reg_t;
+
+/** Type of decoder_status0 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** decode_byte_cnt : RO; bitpos: [25:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t decode_byte_cnt:26;
+        /** header_dec_st : RO; bitpos: [29:26]; default: 0;
+         *  Reserved
+         */
+        uint32_t header_dec_st:4;
+        /** decode_sample_sel : RO; bitpos: [31:30]; default: 0;
+         *  Reserved
+         */
+        uint32_t decode_sample_sel:2;
+    };
+    uint32_t val;
+} jpeg_decoder_status0_reg_t;
+
+/** Type of decoder_status1 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** encode_data : RO; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t encode_data:16;
+        /** count_q : RO; bitpos: [22:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t count_q:7;
+        /** mcu_fsm_ready : RO; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t mcu_fsm_ready:1;
+        /** decode_data : RO; bitpos: [31:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t decode_data:8;
+    };
+    uint32_t val;
+} jpeg_decoder_status1_reg_t;
+
+/** Type of decoder_status2 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** comp_block_num : RO; bitpos: [25:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t comp_block_num:26;
+        /** scan_num : RO; bitpos: [28:26]; default: 0;
+         *  Reserved
+         */
+        uint32_t scan_num:3;
+        /** rst_check_wait : RO; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t rst_check_wait:1;
+        /** scan_check_wait : RO; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t scan_check_wait:1;
+        /** mcu_in_proc : RO; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t mcu_in_proc:1;
+    };
+    uint32_t val;
+} jpeg_decoder_status2_reg_t;
+
+/** Type of decoder_status3 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** lookup_data : RO; bitpos: [31:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t lookup_data:32;
+    };
+    uint32_t val;
+} jpeg_decoder_status3_reg_t;
+
+/** Type of decoder_status4 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** block_eof_cnt : RO; bitpos: [25:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t block_eof_cnt:26;
+        /** dezigzag_ready : RO; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t dezigzag_ready:1;
+        /** de_frame_eof_check : RO; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t de_frame_eof_check:1;
+        /** de_dma2d_in_push : RO; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t de_dma2d_in_push:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} jpeg_decoder_status4_reg_t;
+
+/** Type of decoder_status5 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** idct_hfm_data : RO; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t idct_hfm_data:16;
+        /** ns0 : RO; bitpos: [18:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t ns0:3;
+        /** ns1 : RO; bitpos: [21:19]; default: 0;
+         *  Reserved
+         */
+        uint32_t ns1:3;
+        /** ns2 : RO; bitpos: [24:22]; default: 0;
+         *  Reserved
+         */
+        uint32_t ns2:3;
+        /** ns3 : RO; bitpos: [27:25]; default: 0;
+         *  Reserved
+         */
+        uint32_t ns3:3;
+        /** data_last_o : RO; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t data_last_o:1;
+        /** rdn_result : RO; bitpos: [29]; default: 0;
+         *  redundant registers for jpeg
+         */
+        uint32_t rdn_result:1;
+        /** rdn_ena : R/W; bitpos: [30]; default: 0;
+         *  redundant control registers for jpeg
+         */
+        uint32_t rdn_ena:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} jpeg_decoder_status5_reg_t;
+
+/** Type of status5 register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** pic_block_num : RO; bitpos: [23:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t pic_block_num:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} jpeg_status5_reg_t;
+
+/** Type of eco_low register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  redundant registers for jpeg
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} jpeg_eco_low_reg_t;
+
+/** Type of eco_high register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  redundant registers for jpeg
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} jpeg_eco_high_reg_t;
+
+/** Type of sys register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} jpeg_sys_reg_t;
+
+/** Type of version register
+ *  Trace and Debug registers
+ */
+typedef union {
+    struct {
+        /** jpeg_ver : R/W; bitpos: [27:0]; default: 34673040;
+         *  Reserved
+         */
+        uint32_t jpeg_ver:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} jpeg_version_reg_t;
+
+
+typedef struct jpeg_dev_t {
+    volatile jpeg_config_reg_t config;
+    volatile jpeg_dqt_info_reg_t dqt_info;
+    volatile jpeg_pic_size_reg_t pic_size;
+    uint32_t reserved_00c;
+    volatile jpeg_t0qnr_reg_t t0qnr;
+    volatile jpeg_t1qnr_reg_t t1qnr;
+    volatile jpeg_t2qnr_reg_t t2qnr;
+    volatile jpeg_t3qnr_reg_t t3qnr;
+    volatile jpeg_decode_conf_reg_t decode_conf;
+    volatile jpeg_c0_reg_t c0;
+    volatile jpeg_c1_reg_t c1;
+    volatile jpeg_c2_reg_t c2;
+    volatile jpeg_c3_reg_t c3;
+    volatile jpeg_dht_info_reg_t dht_info;
+    volatile jpeg_int_raw_reg_t int_raw;
+    volatile jpeg_int_ena_reg_t int_ena;
+    volatile jpeg_int_st_reg_t int_st;
+    volatile jpeg_int_clr_reg_t int_clr;
+    volatile jpeg_status0_reg_t status0;
+    volatile jpeg_status2_reg_t status2;
+    volatile jpeg_status3_reg_t status3;
+    volatile jpeg_status4_reg_t status4;
+    volatile jpeg_dht_totlen_dc0_reg_t dht_totlen_dc0;
+    volatile jpeg_dht_val_dc0_reg_t dht_val_dc0;
+    volatile jpeg_dht_totlen_ac0_reg_t dht_totlen_ac0;
+    volatile jpeg_dht_val_ac0_reg_t dht_val_ac0;
+    volatile jpeg_dht_totlen_dc1_reg_t dht_totlen_dc1;
+    volatile jpeg_dht_val_dc1_reg_t dht_val_dc1;
+    volatile jpeg_dht_totlen_ac1_reg_t dht_totlen_ac1;
+    volatile jpeg_dht_val_ac1_reg_t dht_val_ac1;
+    volatile jpeg_dht_codemin_dc0_reg_t dht_codemin_dc0;
+    volatile jpeg_dht_codemin_ac0_reg_t dht_codemin_ac0;
+    volatile jpeg_dht_codemin_dc1_reg_t dht_codemin_dc1;
+    volatile jpeg_dht_codemin_ac1_reg_t dht_codemin_ac1;
+    volatile jpeg_decoder_status0_reg_t decoder_status0;
+    volatile jpeg_decoder_status1_reg_t decoder_status1;
+    volatile jpeg_decoder_status2_reg_t decoder_status2;
+    volatile jpeg_decoder_status3_reg_t decoder_status3;
+    volatile jpeg_decoder_status4_reg_t decoder_status4;
+    volatile jpeg_decoder_status5_reg_t decoder_status5;
+    volatile jpeg_status5_reg_t status5;
+    volatile jpeg_eco_low_reg_t eco_low;
+    volatile jpeg_eco_high_reg_t eco_high;
+    uint32_t reserved_0ac[19];
+    volatile jpeg_sys_reg_t sys;
+    volatile jpeg_version_reg_t version;
+} jpeg_dev_t;
+
+extern jpeg_dev_t JPEG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(jpeg_dev_t) == 0x100, "Invalid size of jpeg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/keymng_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/keymng_eco5_reg.h
new file mode 100644
index 0000000000..a385df2586
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/keymng_eco5_reg.h
@@ -0,0 +1,395 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** KEYMNG_CLK_REG register
+ *  Key Manager clock gate control register
+ */
+#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
+/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  Write 1 to force on register clock gate.
+ */
+#define KEYMNG_REG_CG_FORCE_ON    (BIT(0))
+#define KEYMNG_REG_CG_FORCE_ON_M  (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S)
+#define KEYMNG_REG_CG_FORCE_ON_V  0x00000001U
+#define KEYMNG_REG_CG_FORCE_ON_S  0
+/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to force on memory clock gate.
+ */
+#define KEYMNG_MEM_CG_FORCE_ON    (BIT(1))
+#define KEYMNG_MEM_CG_FORCE_ON_M  (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
+#define KEYMNG_MEM_CG_FORCE_ON_V  0x00000001U
+#define KEYMNG_MEM_CG_FORCE_ON_S  1
+
+/** KEYMNG_INT_RAW_REG register
+ *  Key Manager interrupt raw register, valid in level.
+ */
+#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
+/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_RAW    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_RAW_M  (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
+#define KEYMNG_PREP_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_RAW_S  0
+/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_RAW    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_RAW_M  (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
+#define KEYMNG_PROC_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_RAW_S  1
+/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_RAW    (BIT(2))
+#define KEYMNG_POST_DONE_INT_RAW_M  (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
+#define KEYMNG_POST_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_RAW_S  2
+
+/** KEYMNG_INT_ST_REG register
+ *  Key Manager interrupt status register.
+ */
+#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
+/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_ST    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_ST_M  (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
+#define KEYMNG_PREP_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_ST_S  0
+/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_ST    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_ST_M  (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
+#define KEYMNG_PROC_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_ST_S  1
+/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_ST    (BIT(2))
+#define KEYMNG_POST_DONE_INT_ST_M  (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
+#define KEYMNG_POST_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_ST_S  2
+
+/** KEYMNG_INT_ENA_REG register
+ *  Key Manager interrupt enable register.
+ */
+#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
+/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_ENA    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_ENA_M  (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
+#define KEYMNG_PREP_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_ENA_S  0
+/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_ENA    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_ENA_M  (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
+#define KEYMNG_PROC_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_ENA_S  1
+/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_ENA    (BIT(2))
+#define KEYMNG_POST_DONE_INT_ENA_M  (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
+#define KEYMNG_POST_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_ENA_S  2
+
+/** KEYMNG_INT_CLR_REG register
+ *  Key Manager interrupt clear register.
+ */
+#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
+/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_CLR    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_CLR_M  (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
+#define KEYMNG_PREP_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_CLR_S  0
+/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_CLR    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_CLR_M  (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
+#define KEYMNG_PROC_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_CLR_S  1
+/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_CLR    (BIT(2))
+#define KEYMNG_POST_DONE_INT_CLR_M  (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
+#define KEYMNG_POST_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_CLR_S  2
+
+/** KEYMNG_STATIC_REG register
+ *  Key Manager static configuration register
+ */
+#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
+/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0;
+ *  Set each bit to choose efuse key instead of key manager deployed key. Each bit
+ *  stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
+ *  bit 1 for flash_key; bit 0 for ecdsa_key
+ */
+#define KEYMNG_USE_EFUSE_KEY    0x0000001FU
+#define KEYMNG_USE_EFUSE_KEY_M  (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
+#define KEYMNG_USE_EFUSE_KEY_V  0x0000001FU
+#define KEYMNG_USE_EFUSE_KEY_S  0
+/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
+ *  The core clock cycle number to sample one rng input data. Please set it bigger than
+ *  the clock cycle ratio: T_rng/T_km
+ */
+#define KEYMNG_RND_SWITCH_CYCLE    0x0000001FU
+#define KEYMNG_RND_SWITCH_CYCLE_M  (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
+#define KEYMNG_RND_SWITCH_CYCLE_V  0x0000001FU
+#define KEYMNG_RND_SWITCH_CYCLE_S  5
+/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to use software written init key instead of efuse_init_key.
+ */
+#define KEYMNG_USE_SW_INIT_KEY    (BIT(10))
+#define KEYMNG_USE_SW_INIT_KEY_M  (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
+#define KEYMNG_USE_SW_INIT_KEY_V  0x00000001U
+#define KEYMNG_USE_SW_INIT_KEY_S  10
+/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
+ *  xts-aes-256. 0: use xts-aes-128.
+ */
+#define KEYMNG_FLASH_KEY_LEN    (BIT(11))
+#define KEYMNG_FLASH_KEY_LEN_M  (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S)
+#define KEYMNG_FLASH_KEY_LEN_V  0x00000001U
+#define KEYMNG_FLASH_KEY_LEN_S  11
+/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
+ *  xts-aes-256. 0: use xts-aes-128.
+ */
+#define KEYMNG_PSRAM_KEY_LEN    (BIT(12))
+#define KEYMNG_PSRAM_KEY_LEN_M  (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S)
+#define KEYMNG_PSRAM_KEY_LEN_V  0x00000001U
+#define KEYMNG_PSRAM_KEY_LEN_S  12
+
+/** KEYMNG_LOCK_REG register
+ *  Key Manager static configuration locker register
+ */
+#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
+/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0;
+ *  Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
+ *  reg_use_efuse_key.
+ */
+#define KEYMNG_USE_EFUSE_KEY_LOCK    0x0000001FU
+#define KEYMNG_USE_EFUSE_KEY_LOCK_M  (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
+#define KEYMNG_USE_EFUSE_KEY_LOCK_V  0x0000001FU
+#define KEYMNG_USE_EFUSE_KEY_LOCK_S  0
+/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
+ *  Write 1 to lock reg_rnd_switch_cycle.
+ */
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK    (BIT(5))
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M  (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V  0x00000001U
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S  5
+/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0;
+ *  Write 1 to lock reg_use_sw_init_key.
+ */
+#define KEYMNG_USE_SW_INIT_KEY_LOCK    (BIT(6))
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_M  (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_V  0x00000001U
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_S  6
+/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0;
+ *  Write 1 to lock reg_flash_key_len.
+ */
+#define KEYMNG_FLASH_KEY_LEN_LOCK    (BIT(7))
+#define KEYMNG_FLASH_KEY_LEN_LOCK_M  (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S)
+#define KEYMNG_FLASH_KEY_LEN_LOCK_V  0x00000001U
+#define KEYMNG_FLASH_KEY_LEN_LOCK_S  7
+/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0;
+ *  Write 1 to lock reg_psram_key_len.
+ */
+#define KEYMNG_PSRAM_KEY_LEN_LOCK    (BIT(8))
+#define KEYMNG_PSRAM_KEY_LEN_LOCK_M  (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S)
+#define KEYMNG_PSRAM_KEY_LEN_LOCK_V  0x00000001U
+#define KEYMNG_PSRAM_KEY_LEN_LOCK_S  8
+
+/** KEYMNG_CONF_REG register
+ *  Key Manager configuration register
+ */
+#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
+/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
+ *  mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
+ */
+#define KEYMNG_KGEN_MODE    0x00000007U
+#define KEYMNG_KGEN_MODE_M  (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
+#define KEYMNG_KGEN_MODE_V  0x00000007U
+#define KEYMNG_KGEN_MODE_S  0
+/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
+ *  Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
+ *  flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
+ *  psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
+ *  ecdsa_key_384_h. Others: reserved.
+ */
+#define KEYMNG_KEY_PURPOSE    0x0000000FU
+#define KEYMNG_KEY_PURPOSE_M  (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
+#define KEYMNG_KEY_PURPOSE_V  0x0000000FU
+#define KEYMNG_KEY_PURPOSE_S  3
+
+/** KEYMNG_START_REG register
+ *  Key Manager control register
+ */
+#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
+/** KEYMNG_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to continue Key Manager operation at LOAD/GAIN state.
+ */
+#define KEYMNG_START    (BIT(0))
+#define KEYMNG_START_M  (KEYMNG_START_V << KEYMNG_START_S)
+#define KEYMNG_START_V  0x00000001U
+#define KEYMNG_START_S  0
+/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to start Key Manager at IDLE state.
+ */
+#define KEYMNG_CONTINUE    (BIT(1))
+#define KEYMNG_CONTINUE_M  (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
+#define KEYMNG_CONTINUE_V  0x00000001U
+#define KEYMNG_CONTINUE_S  1
+
+/** KEYMNG_STATE_REG register
+ *  Key Manager state register
+ */
+#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
+/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
+ *  The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+ */
+#define KEYMNG_STATE    0x00000003U
+#define KEYMNG_STATE_M  (KEYMNG_STATE_V << KEYMNG_STATE_S)
+#define KEYMNG_STATE_V  0x00000003U
+#define KEYMNG_STATE_S  0
+
+/** KEYMNG_RESULT_REG register
+ *  Key Manager operation result register
+ */
+#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
+/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The procedure result bit of Key Manager, only valid when Key Manager procedure is
+ *  done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
+ */
+#define KEYMNG_PROC_RESULT    (BIT(0))
+#define KEYMNG_PROC_RESULT_M  (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
+#define KEYMNG_PROC_RESULT_V  0x00000001U
+#define KEYMNG_PROC_RESULT_S  0
+
+/** KEYMNG_KEY_VLD_REG register
+ *  Key Manager key status register
+ */
+#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
+/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0;
+ *  The status bit for key_ecdsa_192.   1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_ECDSA_192_VLD    (BIT(0))
+#define KEYMNG_KEY_ECDSA_192_VLD_M  (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S)
+#define KEYMNG_KEY_ECDSA_192_VLD_V  0x00000001U
+#define KEYMNG_KEY_ECDSA_192_VLD_S  0
+/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0;
+ *  The status bit for key_ecdsa_256.   1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_ECDSA_256_VLD    (BIT(1))
+#define KEYMNG_KEY_ECDSA_256_VLD_M  (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S)
+#define KEYMNG_KEY_ECDSA_256_VLD_V  0x00000001U
+#define KEYMNG_KEY_ECDSA_256_VLD_S  1
+/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0;
+ *  The status bit for key_flash.     1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_FLASH_VLD    (BIT(2))
+#define KEYMNG_KEY_FLASH_VLD_M  (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S)
+#define KEYMNG_KEY_FLASH_VLD_V  0x00000001U
+#define KEYMNG_KEY_FLASH_VLD_S  2
+/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0;
+ *  The status bit for key_hmac.    1: The key has been deployed correctly. 0: The key
+ *  has not been deployed yet.
+ */
+#define KEYMNG_KEY_HMAC_VLD    (BIT(3))
+#define KEYMNG_KEY_HMAC_VLD_M  (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S)
+#define KEYMNG_KEY_HMAC_VLD_V  0x00000001U
+#define KEYMNG_KEY_HMAC_VLD_S  3
+/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0;
+ *  The status bit for key_ds.         1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_DS_VLD    (BIT(4))
+#define KEYMNG_KEY_DS_VLD_M  (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S)
+#define KEYMNG_KEY_DS_VLD_V  0x00000001U
+#define KEYMNG_KEY_DS_VLD_S  4
+/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0;
+ *  The status bit for key_psram.   1: The key has been deployed correctly. 0: The key
+ *  has not been deployed yet.
+ */
+#define KEYMNG_KEY_PSRAM_VLD    (BIT(5))
+#define KEYMNG_KEY_PSRAM_VLD_M  (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S)
+#define KEYMNG_KEY_PSRAM_VLD_V  0x00000001U
+#define KEYMNG_KEY_PSRAM_VLD_S  5
+/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0;
+ *  The status bit for key_ecdsa_384.   1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_ECDSA_384_VLD    (BIT(6))
+#define KEYMNG_KEY_ECDSA_384_VLD_M  (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S)
+#define KEYMNG_KEY_ECDSA_384_VLD_V  0x00000001U
+#define KEYMNG_KEY_ECDSA_384_VLD_S  6
+
+/** KEYMNG_HUK_VLD_REG register
+ *  Key Manager HUK status register
+ */
+#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
+/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
+ *  The HUK status. 0: HUK is not valid. 1: HUK is valid.
+ */
+#define KEYMNG_HUK_VALID    (BIT(0))
+#define KEYMNG_HUK_VALID_M  (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
+#define KEYMNG_HUK_VALID_V  0x00000001U
+#define KEYMNG_HUK_VALID_S  0
+
+/** KEYMNG_DATE_REG register
+ *  Version control register
+ */
+#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
+/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824;
+ *  Key Manager version control register.
+ */
+#define KEYMNG_DATE    0x0FFFFFFFU
+#define KEYMNG_DATE_M  (KEYMNG_DATE_V << KEYMNG_DATE_S)
+#define KEYMNG_DATE_V  0x0FFFFFFFU
+#define KEYMNG_DATE_S  0
+
+/** KEYMNG_ASSIST_INFO_MEM register
+ *  The memory that stores assist key info.
+ */
+#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
+#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
+
+/** KEYMNG_PUBLIC_INFO_MEM register
+ *  The memory that stores public key info.
+ */
+#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
+#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
+
+/** KEYMNG_SW_INIT_KEY_MEM register
+ *  The memory that stores software written init key.
+ */
+#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
+#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/keymng_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/keymng_reg.h
new file mode 100644
index 0000000000..86cef480c0
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/keymng_reg.h
@@ -0,0 +1,366 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** KEYMNG_CLK_REG register
+ *  Key Manager clock gate control register
+ */
+#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
+/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Write 1 to force on register clock gate.
+ */
+#define KEYMNG_CLK_EN    (BIT(0))
+#define KEYMNG_CLK_EN_M  (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S)
+#define KEYMNG_CLK_EN_V  0x00000001U
+#define KEYMNG_CLK_EN_S  0
+/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to force on memory clock gate.
+ */
+#define KEYMNG_MEM_CG_FORCE_ON    (BIT(1))
+#define KEYMNG_MEM_CG_FORCE_ON_M  (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
+#define KEYMNG_MEM_CG_FORCE_ON_V  0x00000001U
+#define KEYMNG_MEM_CG_FORCE_ON_S  1
+
+/** KEYMNG_INT_RAW_REG register
+ *  Key Manager interrupt raw register, valid in level.
+ */
+#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
+/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_RAW    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_RAW_M  (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
+#define KEYMNG_PREP_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_RAW_S  0
+/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_RAW    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_RAW_M  (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
+#define KEYMNG_PROC_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_RAW_S  1
+/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_RAW    (BIT(2))
+#define KEYMNG_POST_DONE_INT_RAW_M  (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
+#define KEYMNG_POST_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_RAW_S  2
+
+/** KEYMNG_INT_ST_REG register
+ *  Key Manager interrupt status register.
+ */
+#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
+/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_ST    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_ST_M  (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
+#define KEYMNG_PREP_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_ST_S  0
+/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_ST    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_ST_M  (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
+#define KEYMNG_PROC_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_ST_S  1
+/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_ST    (BIT(2))
+#define KEYMNG_POST_DONE_INT_ST_M  (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
+#define KEYMNG_POST_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_ST_S  2
+
+/** KEYMNG_INT_ENA_REG register
+ *  Key Manager interrupt enable register.
+ */
+#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
+/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_ENA    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_ENA_M  (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
+#define KEYMNG_PREP_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_ENA_S  0
+/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_ENA    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_ENA_M  (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
+#define KEYMNG_PROC_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_ENA_S  1
+/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_ENA    (BIT(2))
+#define KEYMNG_POST_DONE_INT_ENA_M  (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
+#define KEYMNG_POST_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_ENA_S  2
+
+/** KEYMNG_INT_CLR_REG register
+ *  Key Manager interrupt clear register.
+ */
+#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
+/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_CLR    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_CLR_M  (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
+#define KEYMNG_PREP_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_CLR_S  0
+/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_CLR    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_CLR_M  (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
+#define KEYMNG_PROC_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_CLR_S  1
+/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_CLR    (BIT(2))
+#define KEYMNG_POST_DONE_INT_CLR_M  (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
+#define KEYMNG_POST_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_CLR_S  2
+
+/** KEYMNG_STATIC_REG register
+ *  Key Manager static configuration register
+ */
+#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
+
+/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set this bit to choose efuse key instead of key manager deployed key for xts_key.*/
+#define KEYMNG_USE_EFUSE_KEY_XTS    (BIT(1))
+#define KEYMNG_USE_EFUSE_KEY_XTS_M  ((KEYMNG_USE_EFUSE_KEY_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_XTS_S))
+#define KEYMNG_USE_EFUSE_KEY_XTS_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_XTS_S  1
+
+/* KEYMNG_USE_EFUSE_KEY_ECDSA : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set this bit to choose efuse key instead of key manager deployed key for ecdsa_key.*/
+#define KEYMNG_USE_EFUSE_KEY_ECDSA    (BIT(0))
+#define KEYMNG_USE_EFUSE_KEY_ECDSA_M  ((KEYMNG_USE_EFUSE_KEY_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_ECDSA_S))
+#define KEYMNG_USE_EFUSE_KEY_ECDSA_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_ECDSA_S  0
+
+/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15;
+ *  The core clock cycle number to sample one rng input data. Please set it bigger than
+ *  the clock cycle ratio: T_rng/T_km
+ */
+#define KEYMNG_RND_SWITCH_CYCLE    0x0000001FU
+#define KEYMNG_RND_SWITCH_CYCLE_M  (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
+#define KEYMNG_RND_SWITCH_CYCLE_V  0x0000001FU
+#define KEYMNG_RND_SWITCH_CYCLE_S  4
+/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to use software written init key instead of efuse_init_key.
+ */
+#define KEYMNG_USE_SW_INIT_KEY    (BIT(9))
+#define KEYMNG_USE_SW_INIT_KEY_M  (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
+#define KEYMNG_USE_SW_INIT_KEY_V  0x00000001U
+#define KEYMNG_USE_SW_INIT_KEY_S  9
+/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
+ *  xts-aes-128.
+ */
+#define KEYMNG_XTS_AES_KEY_LEN    (BIT(10))
+#define KEYMNG_XTS_AES_KEY_LEN_M  (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S)
+#define KEYMNG_XTS_AES_KEY_LEN_V  0x00000001U
+#define KEYMNG_XTS_AES_KEY_LEN_S  10
+
+/** KEYMNG_LOCK_REG register
+ *  Key Manager static configuration locker register
+ */
+#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
+
+/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ; bitpos:[1] ; default: 1'd0 ; */
+/* description: Set thus bit to choose efuse key instead of key manager deployed key for xts_key */
+#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS    (BIT(1))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_M  ((KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S  1
+
+/* KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W ; bitpos:[0] ; default: 1'd0 ; */
+/* description: Write 1 to lock ecdsa-key */
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA    (BIT(0))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M  ((KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S  0
+
+/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0;
+ *  Write 1 to lock reg_rnd_switch_cycle.
+ */
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK    (BIT(4))
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M  (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V  0x00000001U
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S  4
+/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0;
+ *  Write 1 to lock reg_use_sw_init_key.
+ */
+#define KEYMNG_USE_SW_INIT_KEY_LOCK    (BIT(5))
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_M  (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_V  0x00000001U
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_S  5
+/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0;
+ *  Write 1 to lock reg_xts_aes_key_len.
+ */
+#define KEYMNG_XTS_AES_KEY_LEN_LOCK    (BIT(6))
+#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M  (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S)
+#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V  0x00000001U
+#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S  6
+
+/** KEYMNG_CONF_REG register
+ *  Key Manager configuration register
+ */
+#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
+/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
+ *  mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
+ */
+#define KEYMNG_KGEN_MODE    0x00000007U
+#define KEYMNG_KGEN_MODE_M  (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
+#define KEYMNG_KGEN_MODE_V  0x00000007U
+#define KEYMNG_KGEN_MODE_S  0
+/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
+ *  Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
+ *  xts_256_2_key. 4. xts_128_key. others: reserved.
+ */
+#define KEYMNG_KEY_PURPOSE    0x0000000FU
+#define KEYMNG_KEY_PURPOSE_M  (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
+#define KEYMNG_KEY_PURPOSE_V  0x0000000FU
+#define KEYMNG_KEY_PURPOSE_S  3
+
+#define KEYMNG_KEY_PURPOSE_ECDSA    (BIT(0))
+#define KEYMNG_KEY_PURPOSE_ECDSA_M  (KEYMNG_KEY_PURPOSE_ECDSA_V << KEYMNG_KEY_PURPOSE_ECDSA_S)
+#define KEYMNG_KEY_PURPOSE_ECDSA_V  0x00000001U
+#define KEYMNG_KEY_PURPOSE_ECDSA_S  0
+
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1    (BIT(1))
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_M  (KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S)
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V  0x00000001U
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S  1
+
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2    (BIT(2))
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_M  (KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S)
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V  0x00000001U
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S  2
+
+/** KEYMNG_START_REG register
+ *  Key Manager control register
+ */
+#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
+/** KEYMNG_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to continue Key Manager operation at LOAD/GAIN state.
+ */
+#define KEYMNG_START    (BIT(0))
+#define KEYMNG_START_M  (KEYMNG_START_V << KEYMNG_START_S)
+#define KEYMNG_START_V  0x00000001U
+#define KEYMNG_START_S  0
+/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to start Key Manager at IDLE state.
+ */
+#define KEYMNG_CONTINUE    (BIT(1))
+#define KEYMNG_CONTINUE_M  (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
+#define KEYMNG_CONTINUE_V  0x00000001U
+#define KEYMNG_CONTINUE_S  1
+
+/** KEYMNG_STATE_REG register
+ *  Key Manager state register
+ */
+#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
+/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
+ *  The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+ */
+#define KEYMNG_STATE    0x00000003U
+#define KEYMNG_STATE_M  (KEYMNG_STATE_V << KEYMNG_STATE_S)
+#define KEYMNG_STATE_V  0x00000003U
+#define KEYMNG_STATE_S  0
+
+/** KEYMNG_RESULT_REG register
+ *  Key Manager operation result register
+ */
+#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
+/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The procedure result bit of Key Manager, only valid when Key Manager procedure is
+ *  done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
+ */
+#define KEYMNG_PROC_RESULT    (BIT(0))
+#define KEYMNG_PROC_RESULT_M  (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
+#define KEYMNG_PROC_RESULT_V  0x00000001U
+#define KEYMNG_PROC_RESULT_S  0
+
+/** KEYMNG_KEY_VLD_REG register
+ *  Key Manager key status register
+ */
+#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
+/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0;
+ *  The status bit for key_ecdsa.   1: The key has been deployed correctly. 0: The key
+ *  has not been deployed yet.
+ */
+#define KEYMNG_KEY_ECDSA_VLD    (BIT(0))
+#define KEYMNG_KEY_ECDSA_VLD_M  (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S)
+#define KEYMNG_KEY_ECDSA_VLD_V  0x00000001U
+#define KEYMNG_KEY_ECDSA_VLD_S  0
+/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0;
+ *  The status bit for key_xts.        1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_XTS_VLD    (BIT(1))
+#define KEYMNG_KEY_XTS_VLD_M  (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S)
+#define KEYMNG_KEY_XTS_VLD_V  0x00000001U
+#define KEYMNG_KEY_XTS_VLD_S  1
+
+/** KEYMNG_HUK_VLD_REG register
+ *  Key Manager HUK status register
+ */
+#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
+/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
+ *  The HUK status. 0: HUK is not valid. 1: HUK is valid.
+ */
+#define KEYMNG_HUK_VALID    (BIT(0))
+#define KEYMNG_HUK_VALID_M  (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
+#define KEYMNG_HUK_VALID_V  0x00000001U
+#define KEYMNG_HUK_VALID_S  0
+
+/** KEYMNG_DATE_REG register
+ *  Version control register
+ */
+#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
+/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704;
+ *  Key Manager version control register.
+ */
+#define KEYMNG_DATE    0x0FFFFFFFU
+#define KEYMNG_DATE_M  (KEYMNG_DATE_V << KEYMNG_DATE_S)
+#define KEYMNG_DATE_V  0x0FFFFFFFU
+#define KEYMNG_DATE_S  0
+
+/** KEYMNG_ASSIST_INFO_MEM register
+ *  The memory that stores assist key info.
+ */
+#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
+#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
+
+/** KEYMNG_PUBLIC_INFO_MEM register
+ *  The memory that stores public key info.
+ */
+#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
+#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
+
+/** KEYMNG_SW_INIT_KEY_MEM register
+ *  The memory that stores software written init key.
+ */
+#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
+#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/keymng_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/keymng_struct.h
new file mode 100644
index 0000000000..d46c34fcd5
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/keymng_struct.h
@@ -0,0 +1,375 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Clock gate register */
+/** Type of clk register
+ *  Key Manager clock gate control register
+ */
+typedef union {
+    struct {
+        /** reg_cg_force_on : R/W; bitpos: [0]; default: 1;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t reg_cg_force_on:1;
+        /** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to force on memory clock gate.
+         */
+        uint32_t mem_cg_force_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} keymng_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Key Manager interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the km_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_raw:1;
+        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the km_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_raw:1;
+        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the km_post_done_int interrupt
+         */
+        uint32_t post_done_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} keymng_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Key Manager interrupt status register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the km_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_st:1;
+        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the km_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_st:1;
+        /** post_done_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the km_post_done_int interrupt
+         */
+        uint32_t post_done_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} keymng_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Key Manager interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the km_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_ena:1;
+        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the km_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_ena:1;
+        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the km_post_done_int interrupt
+         */
+        uint32_t post_done_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} keymng_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Key Manager interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the km_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_clr:1;
+        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the km_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_clr:1;
+        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the km_post_done_int interrupt
+         */
+        uint32_t post_done_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} keymng_int_clr_reg_t;
+
+
+/** Group: Static configuration registers */
+/** Type of static register
+ *  Key Manager static configuration register
+ */
+typedef union {
+    struct {
+        /** use_efuse_key : R/W; bitpos: [4:0]; default: 0;
+         *  Set each bit to choose efuse key instead of key manager deployed key. Each bit
+         *  stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
+         *  bit 1 for flash_key; bit 0 for ecdsa_key
+         */
+        uint32_t use_efuse_key:5;
+        /** rnd_switch_cycle : R/W; bitpos: [9:5]; default: 15;
+         *  The core clock cycle number to sample one rng input data. Please set it bigger than
+         *  the clock cycle ratio: T_rng/T_km
+         */
+        uint32_t rnd_switch_cycle:5;
+        /** use_sw_init_key : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to use software written init key instead of efuse_init_key.
+         */
+        uint32_t use_sw_init_key:1;
+        /** flash_key_len : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
+         *  xts-aes-256. 0: use xts-aes-128.
+         */
+        uint32_t flash_key_len:1;
+        /** psram_key_len : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
+         *  xts-aes-256. 0: use xts-aes-128.
+         */
+        uint32_t psram_key_len:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} keymng_static_reg_t;
+
+/** Type of lock register
+ *  Key Manager static configuration locker register
+ */
+typedef union {
+    struct {
+        /** use_efuse_key_lock : R/W1; bitpos: [4:0]; default: 0;
+         *  Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
+         *  reg_use_efuse_key.
+         */
+        uint32_t use_efuse_key_lock:5;
+        /** rnd_switch_cycle_lock : R/W1; bitpos: [5]; default: 0;
+         *  Write 1 to lock reg_rnd_switch_cycle.
+         */
+        uint32_t rnd_switch_cycle_lock:1;
+        /** use_sw_init_key_lock : R/W1; bitpos: [6]; default: 0;
+         *  Write 1 to lock reg_use_sw_init_key.
+         */
+        uint32_t use_sw_init_key_lock:1;
+        /** flash_key_len_lock : R/W1; bitpos: [7]; default: 0;
+         *  Write 1 to lock reg_flash_key_len.
+         */
+        uint32_t flash_key_len_lock:1;
+        /** psram_key_len_lock : R/W1; bitpos: [8]; default: 0;
+         *  Write 1 to lock reg_psram_key_len.
+         */
+        uint32_t psram_key_len_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} keymng_lock_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  Key Manager configuration register
+ */
+typedef union {
+    struct {
+        /** kgen_mode : R/W; bitpos: [2:0]; default: 0;
+         *  Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
+         *  mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
+         */
+        uint32_t kgen_mode:3;
+        /** key_purpose : R/W; bitpos: [6:3]; default: 0;
+         *  Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
+         *  flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
+         *  psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
+         *  ecdsa_key_384_h. Others: reserved.
+         */
+        uint32_t key_purpose:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} keymng_conf_reg_t;
+
+
+/** Group: Control registers */
+/** Type of start register
+ *  Key Manager control register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to continue Key Manager operation at LOAD/GAIN state.
+         */
+        uint32_t start:1;
+        /** continue : WT; bitpos: [1]; default: 0;
+         *  Write 1 to start Key Manager at IDLE state.
+         */
+        uint32_t conti:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} keymng_start_reg_t;
+
+
+/** Group: State registers */
+/** Type of state register
+ *  Key Manager state register
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [1:0]; default: 0;
+         *  The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+         */
+        uint32_t state:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} keymng_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of result register
+ *  Key Manager operation result register
+ */
+typedef union {
+    struct {
+        /** proc_result : RO/SS; bitpos: [0]; default: 0;
+         *  The procedure result bit of Key Manager, only valid when Key Manager procedure is
+         *  done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
+         */
+        uint32_t proc_result:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} keymng_result_reg_t;
+
+/** Type of key_vld register
+ *  Key Manager key status register
+ */
+typedef union {
+    struct {
+        /** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0;
+         *  The status bit for key_ecdsa_192.   1: The key has been deployed correctly. 0: The
+         *  key has not been deployed yet.
+         */
+        uint32_t key_ecdsa_192_vld:1;
+        /** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0;
+         *  The status bit for key_ecdsa_256.   1: The key has been deployed correctly. 0: The
+         *  key has not been deployed yet.
+         */
+        uint32_t key_ecdsa_256_vld:1;
+        /** key_flash_vld : RO; bitpos: [2]; default: 0;
+         *  The status bit for key_flash.     1: The key has been deployed correctly. 0: The
+         *  key has not been deployed yet.
+         */
+        uint32_t key_flash_vld:1;
+        /** key_hmac_vld : RO; bitpos: [3]; default: 0;
+         *  The status bit for key_hmac.    1: The key has been deployed correctly. 0: The key
+         *  has not been deployed yet.
+         */
+        uint32_t key_hmac_vld:1;
+        /** key_ds_vld : RO; bitpos: [4]; default: 0;
+         *  The status bit for key_ds.         1: The key has been deployed correctly. 0: The
+         *  key has not been deployed yet.
+         */
+        uint32_t key_ds_vld:1;
+        /** key_psram_vld : RO; bitpos: [5]; default: 0;
+         *  The status bit for key_psram.   1: The key has been deployed correctly. 0: The key
+         *  has not been deployed yet.
+         */
+        uint32_t key_psram_vld:1;
+        /** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0;
+         *  The status bit for key_ecdsa_384.   1: The key has been deployed correctly. 0: The
+         *  key has not been deployed yet.
+         */
+        uint32_t key_ecdsa_384_vld:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} keymng_key_vld_reg_t;
+
+/** Type of huk_vld register
+ *  Key Manager HUK status register
+ */
+typedef union {
+    struct {
+        /** huk_valid : RO; bitpos: [0]; default: 0;
+         *  The HUK status. 0: HUK is not valid. 1: HUK is valid.
+         */
+        uint32_t huk_valid:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} keymng_huk_vld_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37781824;
+         *  Key Manager version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} keymng_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile keymng_clk_reg_t clk;
+    volatile keymng_int_raw_reg_t int_raw;
+    volatile keymng_int_st_reg_t int_st;
+    volatile keymng_int_ena_reg_t int_ena;
+    volatile keymng_int_clr_reg_t int_clr;
+    volatile keymng_static_reg_t static_conf;
+    volatile keymng_lock_reg_t lock;
+    volatile keymng_conf_reg_t conf;
+    volatile keymng_start_reg_t start;
+    volatile keymng_state_reg_t state;
+    volatile keymng_result_reg_t result;
+    volatile keymng_key_vld_reg_t key_vld;
+    volatile keymng_huk_vld_reg_t huk_vld;
+    uint32_t reserved_038[49];
+    volatile keymng_date_reg_t date;
+    volatile uint32_t assist_info[16];
+    volatile uint32_t public_info[16];
+    volatile uint32_t sw_init_key[8];
+} keymng_dev_t;
+
+extern keymng_dev_t KEYMNG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_eco5_struct.h
new file mode 100644
index 0000000000..6864fab433
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_eco5_struct.h
@@ -0,0 +1,875 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: lcd configuration registers */
+/** Type of lcd_clock register
+ *  LCD clock config register.
+ */
+typedef union {
+    struct {
+        /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3;
+         *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
+         */
+        uint32_t lcd_clkcnt_n:6;
+        /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1;
+         *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
+         */
+        uint32_t lcd_clk_equ_sysclk:1;
+        /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0;
+         *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
+         */
+        uint32_t lcd_ck_idle_edge:1;
+        /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0;
+         *  1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low
+         *  in the second half data cycle.
+         */
+        uint32_t lcd_ck_out_edge:1;
+        /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral LCD clock divider value
+         */
+        uint32_t lcd_clkm_div_num:8;
+        /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t lcd_clkm_div_b:6;
+        /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t lcd_clkm_div_a:6;
+        /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t lcd_clk_sel:2;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_clock_reg_t;
+
+/** Type of lcd_rgb_yuv register
+ *  LCD YUV/RGB converter configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:18;
+        /** lcd_conv_rgb2rgb_mode : R/W; bitpos: [19:18]; default: 3;
+         *  0:rgb888 trans to rgb565. 1:rgb565 trans to rgb888.2,3:disabled
+         */
+        uint32_t lcd_conv_rgb2rgb_mode:2;
+        /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t lcd_conv_8bits_data_inv:1;
+        /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0;
+         *  0: txtorx mode off. 1: txtorx mode on.
+         */
+        uint32_t lcd_conv_txtorx:1;
+        /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422.  2: to yuv411. 1,3: disabled.  To enable yuv2yuv mode, trans_mode
+         *  must be set to 1.
+         */
+        uint32_t lcd_conv_yuv2yuv_mode:2;
+        /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in
+         */
+        uint32_t lcd_conv_yuv_mode:2;
+        /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t lcd_conv_protocol_mode:1;
+        /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_out_mode:1;
+        /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_in_mode:1;
+        /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t lcd_conv_mode_8bits_on:1;
+        /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t lcd_conv_trans_mode:1;
+        /** lcd_conv_enable : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t lcd_conv_enable:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_rgb_yuv_reg_t;
+
+/** Type of lcd_user register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1;
+         *  The output data cycles minus 1 of LCD module.
+         */
+        uint32_t lcd_dout_cyclelen:13;
+        /** lcd_always_out_en : R/W; bitpos: [13]; default: 0;
+         *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
+         *  reg_lcd_reset is set.
+         */
+        uint32_t lcd_always_out_en:1;
+        /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0;
+         *  0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
+         */
+        uint32_t lcd_dout_byte_swizzle_mode:3;
+        /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0;
+         *  1: enable byte swizzle 0: disable
+         */
+        uint32_t lcd_dout_byte_swizzle_enable:1;
+        /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0;
+         *  1: change bit order in every byte. 0: Not change.
+         */
+        uint32_t lcd_dout_bit_order:1;
+        /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0;
+         *  2: 24bit mode. 1: 16bit mode. 0: 8bit mode
+         */
+        uint32_t lcd_byte_mode:2;
+        /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0;
+         *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t lcd_update_reg:1;
+        /** lcd_bit_order : R/W; bitpos: [22]; default: 0;
+         *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t lcd_bit_order:1;
+        /** lcd_byte_order : R/W; bitpos: [23]; default: 0;
+         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         */
+        uint32_t lcd_byte_order:1;
+        /** lcd_dout : R/W; bitpos: [24]; default: 0;
+         *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dout:1;
+        /** lcd_dummy : R/W; bitpos: [25]; default: 0;
+         *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dummy:1;
+        /** lcd_cmd : R/W; bitpos: [26]; default: 0;
+         *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_cmd:1;
+        /** lcd_start : R/W/SC; bitpos: [27]; default: 0;
+         *  LCD start sending data enable signal, valid in high level.
+         */
+        uint32_t lcd_start:1;
+        /** lcd_reset : WT; bitpos: [28]; default: 0;
+         *  The value of  command.
+         */
+        uint32_t lcd_reset:1;
+        /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0;
+         *  The dummy cycle length minus 1.
+         */
+        uint32_t lcd_dummy_cyclelen:2;
+        /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0;
+         *  The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
+         */
+        uint32_t lcd_cmd_2_cycle_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_user_reg_t;
+
+/** Type of lcd_misc register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
+         */
+        uint32_t lcd_wire_mode:2;
+        /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3;
+         *  The setup cycle length minus 1 in LCD non-RGB mode.
+         */
+        uint32_t lcd_vfk_cyclelen:6;
+        /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0;
+         *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
+         *  time cycle length in LCD non-RGB mode.
+         */
+        uint32_t lcd_vbk_cyclelen:13;
+        /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0;
+         *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
+         *  the current frame is sent out.
+         */
+        uint32_t lcd_next_frame_en:1;
+        /** lcd_bk_en : R/W; bitpos: [26]; default: 0;
+         *  1: Enable blank region when LCD sends data out. 0: No blank region.
+         */
+        uint32_t lcd_bk_en:1;
+        /** lcd_afifo_reset : WT; bitpos: [27]; default: 0;
+         *  LCD AFIFO reset signal.
+         */
+        uint32_t lcd_afifo_reset:1;
+        /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_data_set:1;
+        /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_dummy_set:1;
+        /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_cmd_set:1;
+        /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0;
+         *  The default value of LCD_CD.
+         */
+        uint32_t lcd_cd_idle_edge:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_misc_reg_t;
+
+/** Type of lcd_ctrl register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0;
+         *  It is the horizontal blank front porch of a frame.
+         */
+        uint32_t lcd_hb_front:11;
+        /** lcd_va_height : R/W; bitpos: [20:11]; default: 0;
+         *  It is the vertical active height of a frame.
+         */
+        uint32_t lcd_va_height:10;
+        /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0;
+         *  It is the vertical total height of a frame.
+         */
+        uint32_t lcd_vt_height:10;
+        /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0;
+         *  1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
+         */
+        uint32_t lcd_rgb_mode_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl_reg_t;
+
+/** Type of lcd_ctrl1 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0;
+         *  It is the vertical blank front porch of a frame.
+         */
+        uint32_t lcd_vb_front:8;
+        /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0;
+         *  It is the horizontal active width of a frame.
+         */
+        uint32_t lcd_ha_width:12;
+        /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0;
+         *  It is the horizontal total width of a frame.
+         */
+        uint32_t lcd_ht_width:12;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl1_reg_t;
+
+/** Type of lcd_ctrl2 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1;
+         *  It is the position of LCD_VSYNC active pulse in a line.
+         */
+        uint32_t lcd_vsync_width:7;
+        /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0;
+         *  It is the idle value of LCD_VSYNC.
+         */
+        uint32_t lcd_vsync_idle_pol:1;
+        /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0;
+         *  It is the idle value of LCD_DE.
+         */
+        uint32_t lcd_de_idle_pol:1;
+        /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0;
+         *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
+         *  pulse is valid only in active region lines in RGB mode.
+         */
+        uint32_t lcd_hs_blank_en:1;
+        uint32_t reserved_10:6;
+        /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_width:7;
+        /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0;
+         *  It is the idle value of LCD_HSYNC.
+         */
+        uint32_t lcd_hsync_idle_pol:1;
+        /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_position:8;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl2_reg_t;
+
+/** Type of lcd_first_cmd_val register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value of first cmd cycle.
+         */
+        uint32_t lcd_first_cmd_value:32;
+    };
+    uint32_t val;
+} lcdcam_lcd_first_cmd_val_reg_t;
+
+/** Type of lcd_latter_cmd_val register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value of latter cmd cycle.
+         */
+        uint32_t lcd_latter_cmd_value:32;
+    };
+    uint32_t val;
+} lcdcam_lcd_latter_cmd_val_reg_t;
+
+/** Type of lcd_dly_mode_cfg1 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** dout16_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout16_mode:2;
+        /** dout17_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout17_mode:2;
+        /** dout18_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout18_mode:2;
+        /** dout19_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout19_mode:2;
+        /** dout20_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout20_mode:2;
+        /** dout21_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout21_mode:2;
+        /** dout22_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout22_mode:2;
+        /** dout23_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout23_mode:2;
+        /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_cd_mode:2;
+        /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_de_mode:2;
+        /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_hsync_mode:2;
+        /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_vsync_mode:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lcdcam_lcd_dly_mode_cfg1_reg_t;
+
+/** Type of lcd_dly_mode_cfg2 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout0_mode:2;
+        /** dout1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout1_mode:2;
+        /** dout2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout2_mode:2;
+        /** dout3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout3_mode:2;
+        /** dout4_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout4_mode:2;
+        /** dout5_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout5_mode:2;
+        /** dout6_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout6_mode:2;
+        /** dout7_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout7_mode:2;
+        /** dout8_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout8_mode:2;
+        /** dout9_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout9_mode:2;
+        /** dout10_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout10_mode:2;
+        /** dout11_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout11_mode:2;
+        /** dout12_mode : R/W; bitpos: [25:24]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout12_mode:2;
+        /** dout13_mode : R/W; bitpos: [27:26]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout13_mode:2;
+        /** dout14_mode : R/W; bitpos: [29:28]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout14_mode:2;
+        /** dout15_mode : R/W; bitpos: [31:30]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout15_mode:2;
+    };
+    uint32_t val;
+} lcdcam_lcd_dly_mode_cfg2_reg_t;
+
+
+/** Group: cam configuration registers */
+/** Type of cam_ctrl register
+ *  CAM config register.
+ */
+typedef union {
+    struct {
+        /** cam_stop_en : R/W; bitpos: [0]; default: 0;
+         *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
+         */
+        uint32_t cam_stop_en:1;
+        /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0;
+         *  Filter threshold value for CAM_VSYNC signal.
+         */
+        uint32_t cam_vsync_filter_thres:3;
+        /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0;
+         *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t cam_update_reg:1;
+        /** cam_byte_order : R/W; bitpos: [5]; default: 0;
+         *  1: invert data byte order. 0: Not change.
+         */
+        uint32_t cam_byte_order:1;
+        /** cam_bit_order : R/W; bitpos: [6]; default: 0;
+         *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t cam_bit_order:1;
+        /** cam_line_int_en : R/W; bitpos: [7]; default: 0;
+         *  1: Enable to generate CAM_HS_INT. 0: Disable.
+         */
+        uint32_t cam_line_int_en:1;
+        /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0;
+         *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
+         *  reg_cam_rec_data_cyclelen.
+         */
+        uint32_t cam_vs_eof_en:1;
+        /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral Camera clock divider value
+         */
+        uint32_t cam_clkm_div_num:8;
+        /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t cam_clkm_div_b:6;
+        /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t cam_clkm_div_a:6;
+        /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t cam_clk_sel:2;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} lcdcam_cam_ctrl_reg_t;
+
+/** Type of cam_ctrl1 register
+ *  CAM config register.
+ */
+typedef union {
+    struct {
+        /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0;
+         *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
+         */
+        uint32_t cam_rec_data_bytelen:16;
+        /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0;
+         *  The line number minus 1 to generate cam_hs_int.
+         */
+        uint32_t cam_line_int_num:6;
+        /** cam_clk_inv : R/W; bitpos: [22]; default: 0;
+         *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
+         */
+        uint32_t cam_clk_inv:1;
+        /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0;
+         *  1: Enable CAM_VSYNC filter function. 0: bypass.
+         */
+        uint32_t cam_vsync_filter_en:1;
+        /** cam_2byte_en : R/W; bitpos: [24]; default: 0;
+         *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
+         */
+        uint32_t cam_2byte_en:1;
+        /** cam_de_inv : R/W; bitpos: [25]; default: 0;
+         *  CAM_DE invert enable signal, valid in high level.
+         */
+        uint32_t cam_de_inv:1;
+        /** cam_hsync_inv : R/W; bitpos: [26]; default: 0;
+         *  CAM_HSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_hsync_inv:1;
+        /** cam_vsync_inv : R/W; bitpos: [27]; default: 0;
+         *  CAM_VSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_vsync_inv:1;
+        /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0;
+         *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
+         *  signals are CAM_DE and CAM_VSYNC.
+         */
+        uint32_t cam_vh_de_mode_en:1;
+        /** cam_start : R/W/SC; bitpos: [29]; default: 0;
+         *  Camera module start signal.
+         */
+        uint32_t cam_start:1;
+        /** cam_reset : WT; bitpos: [30]; default: 0;
+         *  Camera module reset signal.
+         */
+        uint32_t cam_reset:1;
+        /** cam_afifo_reset : WT; bitpos: [31]; default: 0;
+         *  Camera AFIFO reset signal.
+         */
+        uint32_t cam_afifo_reset:1;
+    };
+    uint32_t val;
+} lcdcam_cam_ctrl1_reg_t;
+
+/** Type of cam_rgb_yuv register
+ *  CAM YUV/RGB converter configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t cam_conv_8bits_data_inv:1;
+        /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+         *  trans_mode must be set to 1.
+         */
+        uint32_t cam_conv_yuv2yuv_mode:2;
+        /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+         *  mode of Data_in
+         */
+        uint32_t cam_conv_yuv_mode:2;
+        /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t cam_conv_protocol_mode:1;
+        /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_out_mode:1;
+        /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_in_mode:1;
+        /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t cam_conv_mode_8bits_on:1;
+        /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t cam_conv_trans_mode:1;
+        /** cam_conv_enable : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t cam_conv_enable:1;
+    };
+    uint32_t val;
+} lcdcam_cam_rgb_yuv_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of lc_dma_int_ena register
+ *  LCDCAM interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_ena:1;
+        /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_ena:1;
+        /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_ena:1;
+        /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_ena:1;
+        /** lcd_underrun_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_ena_reg_t;
+
+/** Type of lc_dma_int_raw register
+ *  LCDCAM interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_raw:1;
+        /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_raw:1;
+        /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_raw:1;
+        /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_raw:1;
+        /** lcd_underrun_int_raw : RO/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_raw_reg_t;
+
+/** Type of lc_dma_int_st register
+ *  LCDCAM interrupt status register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0;
+         *  The status bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_st:1;
+        /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_st:1;
+        /** cam_vsync_int_st : RO; bitpos: [2]; default: 0;
+         *  The status bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_st:1;
+        /** cam_hs_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for Camera transfer end interrupt.
+         */
+        uint32_t cam_hs_int_st:1;
+        /** lcd_underrun_int_st : RO; bitpos: [4]; default: 0;
+         *  The status bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_st_reg_t;
+
+/** Type of lc_dma_int_clr register
+ *  LCDCAM interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_clr:1;
+        /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_clr:1;
+        /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_clr:1;
+        /** cam_hs_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_clr:1;
+        /** lcd_underrun_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_clr_reg_t;
+
+
+/** Group: Version register */
+/** Type of lc_reg_date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** lc_date : R/W; bitpos: [27:0]; default: 38806054;
+         *  LCD_CAM version control register
+         */
+        uint32_t lc_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lcdcam_lc_reg_date_reg_t;
+
+
+typedef struct {
+    volatile lcdcam_lcd_clock_reg_t lcd_clock;
+    volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
+    volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;
+    volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv;
+    volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv;
+    volatile lcdcam_lcd_user_reg_t lcd_user;
+    volatile lcdcam_lcd_misc_reg_t lcd_misc;
+    volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl;
+    volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1;
+    volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2;
+    volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val;
+    volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val;
+    volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1;
+    uint32_t reserved_034;
+    volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2;
+    uint32_t reserved_03c[10];
+    volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena;
+    volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw;
+    volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st;
+    volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr;
+    uint32_t reserved_074[34];
+    volatile lcdcam_lc_reg_date_reg_t lc_reg_date;
+} lcdcam_dev_t;
+
+extern lcdcam_dev_t LCD_CAM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_reg.h
new file mode 100644
index 0000000000..971324f56c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_reg.h
@@ -0,0 +1,1179 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LCDCAM_LCD_CLOCK_REG register
+ *  LCD clock config register.
+ */
+#define LCDCAM_LCD_CLOCK_REG (DR_REG_LCDCAM_BASE + 0x0)
+/** LCDCAM_LCD_CLKCNT_N : R/W; bitpos: [5:0]; default: 3;
+ *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
+ */
+#define LCDCAM_LCD_CLKCNT_N    0x0000003FU
+#define LCDCAM_LCD_CLKCNT_N_M  (LCDCAM_LCD_CLKCNT_N_V << LCDCAM_LCD_CLKCNT_N_S)
+#define LCDCAM_LCD_CLKCNT_N_V  0x0000003FU
+#define LCDCAM_LCD_CLKCNT_N_S  0
+/** LCDCAM_LCD_CLK_EQU_SYSCLK : R/W; bitpos: [6]; default: 1;
+ *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
+ */
+#define LCDCAM_LCD_CLK_EQU_SYSCLK    (BIT(6))
+#define LCDCAM_LCD_CLK_EQU_SYSCLK_M  (LCDCAM_LCD_CLK_EQU_SYSCLK_V << LCDCAM_LCD_CLK_EQU_SYSCLK_S)
+#define LCDCAM_LCD_CLK_EQU_SYSCLK_V  0x00000001U
+#define LCDCAM_LCD_CLK_EQU_SYSCLK_S  6
+/** LCDCAM_LCD_CK_IDLE_EDGE : R/W; bitpos: [7]; default: 0;
+ *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
+ */
+#define LCDCAM_LCD_CK_IDLE_EDGE    (BIT(7))
+#define LCDCAM_LCD_CK_IDLE_EDGE_M  (LCDCAM_LCD_CK_IDLE_EDGE_V << LCDCAM_LCD_CK_IDLE_EDGE_S)
+#define LCDCAM_LCD_CK_IDLE_EDGE_V  0x00000001U
+#define LCDCAM_LCD_CK_IDLE_EDGE_S  7
+/** LCDCAM_LCD_CK_OUT_EDGE : R/W; bitpos: [8]; default: 0;
+ *  1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low
+ *  in the second half data cycle.
+ */
+#define LCDCAM_LCD_CK_OUT_EDGE    (BIT(8))
+#define LCDCAM_LCD_CK_OUT_EDGE_M  (LCDCAM_LCD_CK_OUT_EDGE_V << LCDCAM_LCD_CK_OUT_EDGE_S)
+#define LCDCAM_LCD_CK_OUT_EDGE_V  0x00000001U
+#define LCDCAM_LCD_CK_OUT_EDGE_S  8
+/** LCDCAM_LCD_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4;
+ *  Integral LCD clock divider value
+ */
+#define LCDCAM_LCD_CLKM_DIV_NUM    0x000000FFU
+#define LCDCAM_LCD_CLKM_DIV_NUM_M  (LCDCAM_LCD_CLKM_DIV_NUM_V << LCDCAM_LCD_CLKM_DIV_NUM_S)
+#define LCDCAM_LCD_CLKM_DIV_NUM_V  0x000000FFU
+#define LCDCAM_LCD_CLKM_DIV_NUM_S  9
+/** LCDCAM_LCD_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0;
+ *  Fractional clock divider numerator value
+ */
+#define LCDCAM_LCD_CLKM_DIV_B    0x0000003FU
+#define LCDCAM_LCD_CLKM_DIV_B_M  (LCDCAM_LCD_CLKM_DIV_B_V << LCDCAM_LCD_CLKM_DIV_B_S)
+#define LCDCAM_LCD_CLKM_DIV_B_V  0x0000003FU
+#define LCDCAM_LCD_CLKM_DIV_B_S  17
+/** LCDCAM_LCD_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0;
+ *  Fractional clock divider denominator value
+ */
+#define LCDCAM_LCD_CLKM_DIV_A    0x0000003FU
+#define LCDCAM_LCD_CLKM_DIV_A_M  (LCDCAM_LCD_CLKM_DIV_A_V << LCDCAM_LCD_CLKM_DIV_A_S)
+#define LCDCAM_LCD_CLKM_DIV_A_V  0x0000003FU
+#define LCDCAM_LCD_CLKM_DIV_A_S  23
+/** LCDCAM_LCD_CLK_SEL : R/W; bitpos: [30:29]; default: 0;
+ *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+ */
+#define LCDCAM_LCD_CLK_SEL    0x00000003U
+#define LCDCAM_LCD_CLK_SEL_M  (LCDCAM_LCD_CLK_SEL_V << LCDCAM_LCD_CLK_SEL_S)
+#define LCDCAM_LCD_CLK_SEL_V  0x00000003U
+#define LCDCAM_LCD_CLK_SEL_S  29
+/** LCDCAM_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to enable clk gate
+ */
+#define LCDCAM_CLK_EN    (BIT(31))
+#define LCDCAM_CLK_EN_M  (LCDCAM_CLK_EN_V << LCDCAM_CLK_EN_S)
+#define LCDCAM_CLK_EN_V  0x00000001U
+#define LCDCAM_CLK_EN_S  31
+
+/** LCDCAM_CAM_CTRL_REG register
+ *  CAM config register.
+ */
+#define LCDCAM_CAM_CTRL_REG (DR_REG_LCDCAM_BASE + 0x4)
+/** LCDCAM_CAM_STOP_EN : R/W; bitpos: [0]; default: 0;
+ *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
+ */
+#define LCDCAM_CAM_STOP_EN    (BIT(0))
+#define LCDCAM_CAM_STOP_EN_M  (LCDCAM_CAM_STOP_EN_V << LCDCAM_CAM_STOP_EN_S)
+#define LCDCAM_CAM_STOP_EN_V  0x00000001U
+#define LCDCAM_CAM_STOP_EN_S  0
+/** LCDCAM_CAM_VSYNC_FILTER_THRES : R/W; bitpos: [3:1]; default: 0;
+ *  Filter threshold value for CAM_VSYNC signal.
+ */
+#define LCDCAM_CAM_VSYNC_FILTER_THRES    0x00000007U
+#define LCDCAM_CAM_VSYNC_FILTER_THRES_M  (LCDCAM_CAM_VSYNC_FILTER_THRES_V << LCDCAM_CAM_VSYNC_FILTER_THRES_S)
+#define LCDCAM_CAM_VSYNC_FILTER_THRES_V  0x00000007U
+#define LCDCAM_CAM_VSYNC_FILTER_THRES_S  1
+/** LCDCAM_CAM_UPDATE_REG : R/W/SC; bitpos: [4]; default: 0;
+ *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
+ */
+#define LCDCAM_CAM_UPDATE_REG    (BIT(4))
+#define LCDCAM_CAM_UPDATE_REG_M  (LCDCAM_CAM_UPDATE_REG_V << LCDCAM_CAM_UPDATE_REG_S)
+#define LCDCAM_CAM_UPDATE_REG_V  0x00000001U
+#define LCDCAM_CAM_UPDATE_REG_S  4
+/** LCDCAM_CAM_BYTE_ORDER : R/W; bitpos: [5]; default: 0;
+ *  1: invert data byte order. 0: Not change.
+ */
+#define LCDCAM_CAM_BYTE_ORDER    (BIT(5))
+#define LCDCAM_CAM_BYTE_ORDER_M  (LCDCAM_CAM_BYTE_ORDER_V << LCDCAM_CAM_BYTE_ORDER_S)
+#define LCDCAM_CAM_BYTE_ORDER_V  0x00000001U
+#define LCDCAM_CAM_BYTE_ORDER_S  5
+/** LCDCAM_CAM_BIT_ORDER : R/W; bitpos: [6]; default: 0;
+ *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
+ *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+ */
+#define LCDCAM_CAM_BIT_ORDER    (BIT(6))
+#define LCDCAM_CAM_BIT_ORDER_M  (LCDCAM_CAM_BIT_ORDER_V << LCDCAM_CAM_BIT_ORDER_S)
+#define LCDCAM_CAM_BIT_ORDER_V  0x00000001U
+#define LCDCAM_CAM_BIT_ORDER_S  6
+/** LCDCAM_CAM_LINE_INT_EN : R/W; bitpos: [7]; default: 0;
+ *  1: Enable to generate CAM_HS_INT. 0: Disable.
+ */
+#define LCDCAM_CAM_LINE_INT_EN    (BIT(7))
+#define LCDCAM_CAM_LINE_INT_EN_M  (LCDCAM_CAM_LINE_INT_EN_V << LCDCAM_CAM_LINE_INT_EN_S)
+#define LCDCAM_CAM_LINE_INT_EN_V  0x00000001U
+#define LCDCAM_CAM_LINE_INT_EN_S  7
+/** LCDCAM_CAM_VS_EOF_EN : R/W; bitpos: [8]; default: 0;
+ *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
+ *  reg_cam_rec_data_cyclelen.
+ */
+#define LCDCAM_CAM_VS_EOF_EN    (BIT(8))
+#define LCDCAM_CAM_VS_EOF_EN_M  (LCDCAM_CAM_VS_EOF_EN_V << LCDCAM_CAM_VS_EOF_EN_S)
+#define LCDCAM_CAM_VS_EOF_EN_V  0x00000001U
+#define LCDCAM_CAM_VS_EOF_EN_S  8
+/** LCDCAM_CAM_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4;
+ *  Integral Camera clock divider value
+ */
+#define LCDCAM_CAM_CLKM_DIV_NUM    0x000000FFU
+#define LCDCAM_CAM_CLKM_DIV_NUM_M  (LCDCAM_CAM_CLKM_DIV_NUM_V << LCDCAM_CAM_CLKM_DIV_NUM_S)
+#define LCDCAM_CAM_CLKM_DIV_NUM_V  0x000000FFU
+#define LCDCAM_CAM_CLKM_DIV_NUM_S  9
+/** LCDCAM_CAM_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0;
+ *  Fractional clock divider numerator value
+ */
+#define LCDCAM_CAM_CLKM_DIV_B    0x0000003FU
+#define LCDCAM_CAM_CLKM_DIV_B_M  (LCDCAM_CAM_CLKM_DIV_B_V << LCDCAM_CAM_CLKM_DIV_B_S)
+#define LCDCAM_CAM_CLKM_DIV_B_V  0x0000003FU
+#define LCDCAM_CAM_CLKM_DIV_B_S  17
+/** LCDCAM_CAM_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0;
+ *  Fractional clock divider denominator value
+ */
+#define LCDCAM_CAM_CLKM_DIV_A    0x0000003FU
+#define LCDCAM_CAM_CLKM_DIV_A_M  (LCDCAM_CAM_CLKM_DIV_A_V << LCDCAM_CAM_CLKM_DIV_A_S)
+#define LCDCAM_CAM_CLKM_DIV_A_V  0x0000003FU
+#define LCDCAM_CAM_CLKM_DIV_A_S  23
+/** LCDCAM_CAM_CLK_SEL : R/W; bitpos: [30:29]; default: 0;
+ *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+ */
+#define LCDCAM_CAM_CLK_SEL    0x00000003U
+#define LCDCAM_CAM_CLK_SEL_M  (LCDCAM_CAM_CLK_SEL_V << LCDCAM_CAM_CLK_SEL_S)
+#define LCDCAM_CAM_CLK_SEL_V  0x00000003U
+#define LCDCAM_CAM_CLK_SEL_S  29
+
+/** LCDCAM_CAM_CTRL1_REG register
+ *  CAM config register.
+ */
+#define LCDCAM_CAM_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x8)
+/** LCDCAM_CAM_REC_DATA_BYTELEN : R/W; bitpos: [15:0]; default: 0;
+ *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
+ */
+#define LCDCAM_CAM_REC_DATA_BYTELEN    0x0000FFFFU
+#define LCDCAM_CAM_REC_DATA_BYTELEN_M  (LCDCAM_CAM_REC_DATA_BYTELEN_V << LCDCAM_CAM_REC_DATA_BYTELEN_S)
+#define LCDCAM_CAM_REC_DATA_BYTELEN_V  0x0000FFFFU
+#define LCDCAM_CAM_REC_DATA_BYTELEN_S  0
+/** LCDCAM_CAM_LINE_INT_NUM : R/W; bitpos: [21:16]; default: 0;
+ *  The line number minus 1 to generate cam_hs_int.
+ */
+#define LCDCAM_CAM_LINE_INT_NUM    0x0000003FU
+#define LCDCAM_CAM_LINE_INT_NUM_M  (LCDCAM_CAM_LINE_INT_NUM_V << LCDCAM_CAM_LINE_INT_NUM_S)
+#define LCDCAM_CAM_LINE_INT_NUM_V  0x0000003FU
+#define LCDCAM_CAM_LINE_INT_NUM_S  16
+/** LCDCAM_CAM_CLK_INV : R/W; bitpos: [22]; default: 0;
+ *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
+ */
+#define LCDCAM_CAM_CLK_INV    (BIT(22))
+#define LCDCAM_CAM_CLK_INV_M  (LCDCAM_CAM_CLK_INV_V << LCDCAM_CAM_CLK_INV_S)
+#define LCDCAM_CAM_CLK_INV_V  0x00000001U
+#define LCDCAM_CAM_CLK_INV_S  22
+/** LCDCAM_CAM_VSYNC_FILTER_EN : R/W; bitpos: [23]; default: 0;
+ *  1: Enable CAM_VSYNC filter function. 0: bypass.
+ */
+#define LCDCAM_CAM_VSYNC_FILTER_EN    (BIT(23))
+#define LCDCAM_CAM_VSYNC_FILTER_EN_M  (LCDCAM_CAM_VSYNC_FILTER_EN_V << LCDCAM_CAM_VSYNC_FILTER_EN_S)
+#define LCDCAM_CAM_VSYNC_FILTER_EN_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_FILTER_EN_S  23
+/** LCDCAM_CAM_2BYTE_EN : R/W; bitpos: [24]; default: 0;
+ *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
+ */
+#define LCDCAM_CAM_2BYTE_EN    (BIT(24))
+#define LCDCAM_CAM_2BYTE_EN_M  (LCDCAM_CAM_2BYTE_EN_V << LCDCAM_CAM_2BYTE_EN_S)
+#define LCDCAM_CAM_2BYTE_EN_V  0x00000001U
+#define LCDCAM_CAM_2BYTE_EN_S  24
+/** LCDCAM_CAM_DE_INV : R/W; bitpos: [25]; default: 0;
+ *  CAM_DE invert enable signal, valid in high level.
+ */
+#define LCDCAM_CAM_DE_INV    (BIT(25))
+#define LCDCAM_CAM_DE_INV_M  (LCDCAM_CAM_DE_INV_V << LCDCAM_CAM_DE_INV_S)
+#define LCDCAM_CAM_DE_INV_V  0x00000001U
+#define LCDCAM_CAM_DE_INV_S  25
+/** LCDCAM_CAM_HSYNC_INV : R/W; bitpos: [26]; default: 0;
+ *  CAM_HSYNC invert enable signal, valid in high level.
+ */
+#define LCDCAM_CAM_HSYNC_INV    (BIT(26))
+#define LCDCAM_CAM_HSYNC_INV_M  (LCDCAM_CAM_HSYNC_INV_V << LCDCAM_CAM_HSYNC_INV_S)
+#define LCDCAM_CAM_HSYNC_INV_V  0x00000001U
+#define LCDCAM_CAM_HSYNC_INV_S  26
+/** LCDCAM_CAM_VSYNC_INV : R/W; bitpos: [27]; default: 0;
+ *  CAM_VSYNC invert enable signal, valid in high level.
+ */
+#define LCDCAM_CAM_VSYNC_INV    (BIT(27))
+#define LCDCAM_CAM_VSYNC_INV_M  (LCDCAM_CAM_VSYNC_INV_V << LCDCAM_CAM_VSYNC_INV_S)
+#define LCDCAM_CAM_VSYNC_INV_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_INV_S  27
+/** LCDCAM_CAM_VH_DE_MODE_EN : R/W; bitpos: [28]; default: 0;
+ *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
+ *  signals are CAM_DE and CAM_VSYNC.
+ */
+#define LCDCAM_CAM_VH_DE_MODE_EN    (BIT(28))
+#define LCDCAM_CAM_VH_DE_MODE_EN_M  (LCDCAM_CAM_VH_DE_MODE_EN_V << LCDCAM_CAM_VH_DE_MODE_EN_S)
+#define LCDCAM_CAM_VH_DE_MODE_EN_V  0x00000001U
+#define LCDCAM_CAM_VH_DE_MODE_EN_S  28
+/** LCDCAM_CAM_START : R/W/SC; bitpos: [29]; default: 0;
+ *  Camera module start signal.
+ */
+#define LCDCAM_CAM_START    (BIT(29))
+#define LCDCAM_CAM_START_M  (LCDCAM_CAM_START_V << LCDCAM_CAM_START_S)
+#define LCDCAM_CAM_START_V  0x00000001U
+#define LCDCAM_CAM_START_S  29
+/** LCDCAM_CAM_RESET : WT; bitpos: [30]; default: 0;
+ *  Camera module reset signal.
+ */
+#define LCDCAM_CAM_RESET    (BIT(30))
+#define LCDCAM_CAM_RESET_M  (LCDCAM_CAM_RESET_V << LCDCAM_CAM_RESET_S)
+#define LCDCAM_CAM_RESET_V  0x00000001U
+#define LCDCAM_CAM_RESET_S  30
+/** LCDCAM_CAM_AFIFO_RESET : WT; bitpos: [31]; default: 0;
+ *  Camera AFIFO reset signal.
+ */
+#define LCDCAM_CAM_AFIFO_RESET    (BIT(31))
+#define LCDCAM_CAM_AFIFO_RESET_M  (LCDCAM_CAM_AFIFO_RESET_V << LCDCAM_CAM_AFIFO_RESET_S)
+#define LCDCAM_CAM_AFIFO_RESET_V  0x00000001U
+#define LCDCAM_CAM_AFIFO_RESET_S  31
+
+/** LCDCAM_CAM_RGB_YUV_REG register
+ *  CAM YUV/RGB converter configuration register.
+ */
+#define LCDCAM_CAM_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0xc)
+/** LCDCAM_CAM_CONV_8BITS_DATA_INV : R/W; bitpos: [21]; default: 0;
+ *  1:invert every two 8bits input data. 2. disabled.
+ */
+#define LCDCAM_CAM_CONV_8BITS_DATA_INV    (BIT(21))
+#define LCDCAM_CAM_CONV_8BITS_DATA_INV_M  (LCDCAM_CAM_CONV_8BITS_DATA_INV_V << LCDCAM_CAM_CONV_8BITS_DATA_INV_S)
+#define LCDCAM_CAM_CONV_8BITS_DATA_INV_V  0x00000001U
+#define LCDCAM_CAM_CONV_8BITS_DATA_INV_S  21
+/** LCDCAM_CAM_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3;
+ *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+ *  trans_mode must be set to 1.
+ */
+#define LCDCAM_CAM_CONV_YUV2YUV_MODE    0x00000003U
+#define LCDCAM_CAM_CONV_YUV2YUV_MODE_M  (LCDCAM_CAM_CONV_YUV2YUV_MODE_V << LCDCAM_CAM_CONV_YUV2YUV_MODE_S)
+#define LCDCAM_CAM_CONV_YUV2YUV_MODE_V  0x00000003U
+#define LCDCAM_CAM_CONV_YUV2YUV_MODE_S  22
+/** LCDCAM_CAM_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+ *  mode of Data_in
+ */
+#define LCDCAM_CAM_CONV_YUV_MODE    0x00000003U
+#define LCDCAM_CAM_CONV_YUV_MODE_M  (LCDCAM_CAM_CONV_YUV_MODE_V << LCDCAM_CAM_CONV_YUV_MODE_S)
+#define LCDCAM_CAM_CONV_YUV_MODE_V  0x00000003U
+#define LCDCAM_CAM_CONV_YUV_MODE_S  24
+/** LCDCAM_CAM_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0;
+ *  0:BT601. 1:BT709.
+ */
+#define LCDCAM_CAM_CONV_PROTOCOL_MODE    (BIT(26))
+#define LCDCAM_CAM_CONV_PROTOCOL_MODE_M  (LCDCAM_CAM_CONV_PROTOCOL_MODE_V << LCDCAM_CAM_CONV_PROTOCOL_MODE_S)
+#define LCDCAM_CAM_CONV_PROTOCOL_MODE_V  0x00000001U
+#define LCDCAM_CAM_CONV_PROTOCOL_MODE_S  26
+/** LCDCAM_CAM_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0;
+ *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+ */
+#define LCDCAM_CAM_CONV_DATA_OUT_MODE    (BIT(27))
+#define LCDCAM_CAM_CONV_DATA_OUT_MODE_M  (LCDCAM_CAM_CONV_DATA_OUT_MODE_V << LCDCAM_CAM_CONV_DATA_OUT_MODE_S)
+#define LCDCAM_CAM_CONV_DATA_OUT_MODE_V  0x00000001U
+#define LCDCAM_CAM_CONV_DATA_OUT_MODE_S  27
+/** LCDCAM_CAM_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0;
+ *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+ */
+#define LCDCAM_CAM_CONV_DATA_IN_MODE    (BIT(28))
+#define LCDCAM_CAM_CONV_DATA_IN_MODE_M  (LCDCAM_CAM_CONV_DATA_IN_MODE_V << LCDCAM_CAM_CONV_DATA_IN_MODE_S)
+#define LCDCAM_CAM_CONV_DATA_IN_MODE_V  0x00000001U
+#define LCDCAM_CAM_CONV_DATA_IN_MODE_S  28
+/** LCDCAM_CAM_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0;
+ *  0: 16bits mode. 1: 8bits mode.
+ */
+#define LCDCAM_CAM_CONV_MODE_8BITS_ON    (BIT(29))
+#define LCDCAM_CAM_CONV_MODE_8BITS_ON_M  (LCDCAM_CAM_CONV_MODE_8BITS_ON_V << LCDCAM_CAM_CONV_MODE_8BITS_ON_S)
+#define LCDCAM_CAM_CONV_MODE_8BITS_ON_V  0x00000001U
+#define LCDCAM_CAM_CONV_MODE_8BITS_ON_S  29
+/** LCDCAM_CAM_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0;
+ *  0: YUV to RGB. 1: RGB to YUV.
+ */
+#define LCDCAM_CAM_CONV_TRANS_MODE    (BIT(30))
+#define LCDCAM_CAM_CONV_TRANS_MODE_M  (LCDCAM_CAM_CONV_TRANS_MODE_V << LCDCAM_CAM_CONV_TRANS_MODE_S)
+#define LCDCAM_CAM_CONV_TRANS_MODE_V  0x00000001U
+#define LCDCAM_CAM_CONV_TRANS_MODE_S  30
+/** LCDCAM_CAM_CONV_ENABLE : R/W; bitpos: [31]; default: 0;
+ *  0: Bypass converter. 1: Enable converter.
+ */
+#define LCDCAM_CAM_CONV_ENABLE    (BIT(31))
+#define LCDCAM_CAM_CONV_ENABLE_M  (LCDCAM_CAM_CONV_ENABLE_V << LCDCAM_CAM_CONV_ENABLE_S)
+#define LCDCAM_CAM_CONV_ENABLE_V  0x00000001U
+#define LCDCAM_CAM_CONV_ENABLE_S  31
+
+/** LCDCAM_LCD_RGB_YUV_REG register
+ *  LCD YUV/RGB converter configuration register.
+ */
+#define LCDCAM_LCD_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0x10)
+/** LCDCAM_LCD_CONV_RGB2RGB_MODE : R/W; bitpos: [19:18]; default: 3;
+ *  0:rgb888 trans to rgb565. 1:rgb565 trans to rgb888.2,3:disabled
+ */
+#define LCDCAM_LCD_CONV_RGB2RGB_MODE    0x00000003U
+#define LCDCAM_LCD_CONV_RGB2RGB_MODE_M  (LCDCAM_LCD_CONV_RGB2RGB_MODE_V << LCDCAM_LCD_CONV_RGB2RGB_MODE_S)
+#define LCDCAM_LCD_CONV_RGB2RGB_MODE_V  0x00000003U
+#define LCDCAM_LCD_CONV_RGB2RGB_MODE_S  18
+/** LCDCAM_LCD_CONV_8BITS_DATA_INV : R/W; bitpos: [20]; default: 0;
+ *  1:invert every two 8bits input data. 2. disabled.
+ */
+#define LCDCAM_LCD_CONV_8BITS_DATA_INV    (BIT(20))
+#define LCDCAM_LCD_CONV_8BITS_DATA_INV_M  (LCDCAM_LCD_CONV_8BITS_DATA_INV_V << LCDCAM_LCD_CONV_8BITS_DATA_INV_S)
+#define LCDCAM_LCD_CONV_8BITS_DATA_INV_V  0x00000001U
+#define LCDCAM_LCD_CONV_8BITS_DATA_INV_S  20
+/** LCDCAM_LCD_CONV_TXTORX : R/W; bitpos: [21]; default: 0;
+ *  0: txtorx mode off. 1: txtorx mode on.
+ */
+#define LCDCAM_LCD_CONV_TXTORX    (BIT(21))
+#define LCDCAM_LCD_CONV_TXTORX_M  (LCDCAM_LCD_CONV_TXTORX_V << LCDCAM_LCD_CONV_TXTORX_S)
+#define LCDCAM_LCD_CONV_TXTORX_V  0x00000001U
+#define LCDCAM_LCD_CONV_TXTORX_S  21
+/** LCDCAM_LCD_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3;
+ *  0: to yuv422.  2: to yuv411. 1,3: disabled.  To enable yuv2yuv mode, trans_mode
+ *  must be set to 1.
+ */
+#define LCDCAM_LCD_CONV_YUV2YUV_MODE    0x00000003U
+#define LCDCAM_LCD_CONV_YUV2YUV_MODE_M  (LCDCAM_LCD_CONV_YUV2YUV_MODE_V << LCDCAM_LCD_CONV_YUV2YUV_MODE_S)
+#define LCDCAM_LCD_CONV_YUV2YUV_MODE_V  0x00000003U
+#define LCDCAM_LCD_CONV_YUV2YUV_MODE_S  22
+/** LCDCAM_LCD_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  0: yuv422. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in
+ */
+#define LCDCAM_LCD_CONV_YUV_MODE    0x00000003U
+#define LCDCAM_LCD_CONV_YUV_MODE_M  (LCDCAM_LCD_CONV_YUV_MODE_V << LCDCAM_LCD_CONV_YUV_MODE_S)
+#define LCDCAM_LCD_CONV_YUV_MODE_V  0x00000003U
+#define LCDCAM_LCD_CONV_YUV_MODE_S  24
+/** LCDCAM_LCD_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0;
+ *  0:BT601. 1:BT709.
+ */
+#define LCDCAM_LCD_CONV_PROTOCOL_MODE    (BIT(26))
+#define LCDCAM_LCD_CONV_PROTOCOL_MODE_M  (LCDCAM_LCD_CONV_PROTOCOL_MODE_V << LCDCAM_LCD_CONV_PROTOCOL_MODE_S)
+#define LCDCAM_LCD_CONV_PROTOCOL_MODE_V  0x00000001U
+#define LCDCAM_LCD_CONV_PROTOCOL_MODE_S  26
+/** LCDCAM_LCD_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0;
+ *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+ */
+#define LCDCAM_LCD_CONV_DATA_OUT_MODE    (BIT(27))
+#define LCDCAM_LCD_CONV_DATA_OUT_MODE_M  (LCDCAM_LCD_CONV_DATA_OUT_MODE_V << LCDCAM_LCD_CONV_DATA_OUT_MODE_S)
+#define LCDCAM_LCD_CONV_DATA_OUT_MODE_V  0x00000001U
+#define LCDCAM_LCD_CONV_DATA_OUT_MODE_S  27
+/** LCDCAM_LCD_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0;
+ *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+ */
+#define LCDCAM_LCD_CONV_DATA_IN_MODE    (BIT(28))
+#define LCDCAM_LCD_CONV_DATA_IN_MODE_M  (LCDCAM_LCD_CONV_DATA_IN_MODE_V << LCDCAM_LCD_CONV_DATA_IN_MODE_S)
+#define LCDCAM_LCD_CONV_DATA_IN_MODE_V  0x00000001U
+#define LCDCAM_LCD_CONV_DATA_IN_MODE_S  28
+/** LCDCAM_LCD_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0;
+ *  0: 16bits mode. 1: 8bits mode.
+ */
+#define LCDCAM_LCD_CONV_MODE_8BITS_ON    (BIT(29))
+#define LCDCAM_LCD_CONV_MODE_8BITS_ON_M  (LCDCAM_LCD_CONV_MODE_8BITS_ON_V << LCDCAM_LCD_CONV_MODE_8BITS_ON_S)
+#define LCDCAM_LCD_CONV_MODE_8BITS_ON_V  0x00000001U
+#define LCDCAM_LCD_CONV_MODE_8BITS_ON_S  29
+/** LCDCAM_LCD_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0;
+ *  0: YUV to RGB. 1: RGB to YUV.
+ */
+#define LCDCAM_LCD_CONV_TRANS_MODE    (BIT(30))
+#define LCDCAM_LCD_CONV_TRANS_MODE_M  (LCDCAM_LCD_CONV_TRANS_MODE_V << LCDCAM_LCD_CONV_TRANS_MODE_S)
+#define LCDCAM_LCD_CONV_TRANS_MODE_V  0x00000001U
+#define LCDCAM_LCD_CONV_TRANS_MODE_S  30
+/** LCDCAM_LCD_CONV_ENABLE : R/W; bitpos: [31]; default: 0;
+ *  0: Bypass converter. 1: Enable converter.
+ */
+#define LCDCAM_LCD_CONV_ENABLE    (BIT(31))
+#define LCDCAM_LCD_CONV_ENABLE_M  (LCDCAM_LCD_CONV_ENABLE_V << LCDCAM_LCD_CONV_ENABLE_S)
+#define LCDCAM_LCD_CONV_ENABLE_V  0x00000001U
+#define LCDCAM_LCD_CONV_ENABLE_S  31
+
+/** LCDCAM_LCD_USER_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_USER_REG (DR_REG_LCDCAM_BASE + 0x14)
+/** LCDCAM_LCD_DOUT_CYCLELEN : R/W; bitpos: [12:0]; default: 1;
+ *  The output data cycles minus 1 of LCD module.
+ */
+#define LCDCAM_LCD_DOUT_CYCLELEN    0x00001FFFU
+#define LCDCAM_LCD_DOUT_CYCLELEN_M  (LCDCAM_LCD_DOUT_CYCLELEN_V << LCDCAM_LCD_DOUT_CYCLELEN_S)
+#define LCDCAM_LCD_DOUT_CYCLELEN_V  0x00001FFFU
+#define LCDCAM_LCD_DOUT_CYCLELEN_S  0
+/** LCDCAM_LCD_ALWAYS_OUT_EN : R/W; bitpos: [13]; default: 0;
+ *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
+ *  reg_lcd_reset is set.
+ */
+#define LCDCAM_LCD_ALWAYS_OUT_EN    (BIT(13))
+#define LCDCAM_LCD_ALWAYS_OUT_EN_M  (LCDCAM_LCD_ALWAYS_OUT_EN_V << LCDCAM_LCD_ALWAYS_OUT_EN_S)
+#define LCDCAM_LCD_ALWAYS_OUT_EN_V  0x00000001U
+#define LCDCAM_LCD_ALWAYS_OUT_EN_S  13
+/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE : R/W; bitpos: [16:14]; default: 0;
+ *  0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
+ */
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE    0x00000007U
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_M  (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S)
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V  0x00000007U
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S  14
+/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE : R/W; bitpos: [17]; default: 0;
+ *  1: enable byte swizzle 0: disable
+ */
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE    (BIT(17))
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_M  (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S)
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V  0x00000001U
+#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S  17
+/** LCDCAM_LCD_DOUT_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  1: change bit order in every byte. 0: Not change.
+ */
+#define LCDCAM_LCD_DOUT_BIT_ORDER    (BIT(18))
+#define LCDCAM_LCD_DOUT_BIT_ORDER_M  (LCDCAM_LCD_DOUT_BIT_ORDER_V << LCDCAM_LCD_DOUT_BIT_ORDER_S)
+#define LCDCAM_LCD_DOUT_BIT_ORDER_V  0x00000001U
+#define LCDCAM_LCD_DOUT_BIT_ORDER_S  18
+/** LCDCAM_LCD_BYTE_MODE : R/W; bitpos: [20:19]; default: 0;
+ *  2: 24bit mode. 1: 16bit mode. 0: 8bit mode
+ */
+#define LCDCAM_LCD_BYTE_MODE    0x00000003U
+#define LCDCAM_LCD_BYTE_MODE_M  (LCDCAM_LCD_BYTE_MODE_V << LCDCAM_LCD_BYTE_MODE_S)
+#define LCDCAM_LCD_BYTE_MODE_V  0x00000003U
+#define LCDCAM_LCD_BYTE_MODE_S  19
+/** LCDCAM_LCD_UPDATE_REG : R/W/SC; bitpos: [21]; default: 0;
+ *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
+ */
+#define LCDCAM_LCD_UPDATE_REG    (BIT(21))
+#define LCDCAM_LCD_UPDATE_REG_M  (LCDCAM_LCD_UPDATE_REG_V << LCDCAM_LCD_UPDATE_REG_S)
+#define LCDCAM_LCD_UPDATE_REG_V  0x00000001U
+#define LCDCAM_LCD_UPDATE_REG_S  21
+/** LCDCAM_LCD_BIT_ORDER : R/W; bitpos: [22]; default: 0;
+ *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
+ *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+ */
+#define LCDCAM_LCD_BIT_ORDER    (BIT(22))
+#define LCDCAM_LCD_BIT_ORDER_M  (LCDCAM_LCD_BIT_ORDER_V << LCDCAM_LCD_BIT_ORDER_S)
+#define LCDCAM_LCD_BIT_ORDER_V  0x00000001U
+#define LCDCAM_LCD_BIT_ORDER_S  22
+/** LCDCAM_LCD_BYTE_ORDER : R/W; bitpos: [23]; default: 0;
+ *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+ */
+#define LCDCAM_LCD_BYTE_ORDER    (BIT(23))
+#define LCDCAM_LCD_BYTE_ORDER_M  (LCDCAM_LCD_BYTE_ORDER_V << LCDCAM_LCD_BYTE_ORDER_S)
+#define LCDCAM_LCD_BYTE_ORDER_V  0x00000001U
+#define LCDCAM_LCD_BYTE_ORDER_S  23
+/** LCDCAM_LCD_DOUT : R/W; bitpos: [24]; default: 0;
+ *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
+ */
+#define LCDCAM_LCD_DOUT    (BIT(24))
+#define LCDCAM_LCD_DOUT_M  (LCDCAM_LCD_DOUT_V << LCDCAM_LCD_DOUT_S)
+#define LCDCAM_LCD_DOUT_V  0x00000001U
+#define LCDCAM_LCD_DOUT_S  24
+/** LCDCAM_LCD_DUMMY : R/W; bitpos: [25]; default: 0;
+ *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
+ */
+#define LCDCAM_LCD_DUMMY    (BIT(25))
+#define LCDCAM_LCD_DUMMY_M  (LCDCAM_LCD_DUMMY_V << LCDCAM_LCD_DUMMY_S)
+#define LCDCAM_LCD_DUMMY_V  0x00000001U
+#define LCDCAM_LCD_DUMMY_S  25
+/** LCDCAM_LCD_CMD : R/W; bitpos: [26]; default: 0;
+ *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
+ */
+#define LCDCAM_LCD_CMD    (BIT(26))
+#define LCDCAM_LCD_CMD_M  (LCDCAM_LCD_CMD_V << LCDCAM_LCD_CMD_S)
+#define LCDCAM_LCD_CMD_V  0x00000001U
+#define LCDCAM_LCD_CMD_S  26
+/** LCDCAM_LCD_START : R/W/SC; bitpos: [27]; default: 0;
+ *  LCD start sending data enable signal, valid in high level.
+ */
+#define LCDCAM_LCD_START    (BIT(27))
+#define LCDCAM_LCD_START_M  (LCDCAM_LCD_START_V << LCDCAM_LCD_START_S)
+#define LCDCAM_LCD_START_V  0x00000001U
+#define LCDCAM_LCD_START_S  27
+/** LCDCAM_LCD_RESET : WT; bitpos: [28]; default: 0;
+ *  The value of  command.
+ */
+#define LCDCAM_LCD_RESET    (BIT(28))
+#define LCDCAM_LCD_RESET_M  (LCDCAM_LCD_RESET_V << LCDCAM_LCD_RESET_S)
+#define LCDCAM_LCD_RESET_V  0x00000001U
+#define LCDCAM_LCD_RESET_S  28
+/** LCDCAM_LCD_DUMMY_CYCLELEN : R/W; bitpos: [30:29]; default: 0;
+ *  The dummy cycle length minus 1.
+ */
+#define LCDCAM_LCD_DUMMY_CYCLELEN    0x00000003U
+#define LCDCAM_LCD_DUMMY_CYCLELEN_M  (LCDCAM_LCD_DUMMY_CYCLELEN_V << LCDCAM_LCD_DUMMY_CYCLELEN_S)
+#define LCDCAM_LCD_DUMMY_CYCLELEN_V  0x00000003U
+#define LCDCAM_LCD_DUMMY_CYCLELEN_S  29
+/** LCDCAM_LCD_CMD_2_CYCLE_EN : R/W; bitpos: [31]; default: 0;
+ *  The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
+ */
+#define LCDCAM_LCD_CMD_2_CYCLE_EN    (BIT(31))
+#define LCDCAM_LCD_CMD_2_CYCLE_EN_M  (LCDCAM_LCD_CMD_2_CYCLE_EN_V << LCDCAM_LCD_CMD_2_CYCLE_EN_S)
+#define LCDCAM_LCD_CMD_2_CYCLE_EN_V  0x00000001U
+#define LCDCAM_LCD_CMD_2_CYCLE_EN_S  31
+
+/** LCDCAM_LCD_MISC_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_MISC_REG (DR_REG_LCDCAM_BASE + 0x18)
+/** LCDCAM_LCD_WIRE_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
+ */
+#define LCDCAM_LCD_WIRE_MODE    0x00000003U
+#define LCDCAM_LCD_WIRE_MODE_M  (LCDCAM_LCD_WIRE_MODE_V << LCDCAM_LCD_WIRE_MODE_S)
+#define LCDCAM_LCD_WIRE_MODE_V  0x00000003U
+#define LCDCAM_LCD_WIRE_MODE_S  4
+/** LCDCAM_LCD_VFK_CYCLELEN : R/W; bitpos: [11:6]; default: 3;
+ *  The setup cycle length minus 1 in LCD non-RGB mode.
+ */
+#define LCDCAM_LCD_VFK_CYCLELEN    0x0000003FU
+#define LCDCAM_LCD_VFK_CYCLELEN_M  (LCDCAM_LCD_VFK_CYCLELEN_V << LCDCAM_LCD_VFK_CYCLELEN_S)
+#define LCDCAM_LCD_VFK_CYCLELEN_V  0x0000003FU
+#define LCDCAM_LCD_VFK_CYCLELEN_S  6
+/** LCDCAM_LCD_VBK_CYCLELEN : R/W; bitpos: [24:12]; default: 0;
+ *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
+ *  time cycle length in LCD non-RGB mode.
+ */
+#define LCDCAM_LCD_VBK_CYCLELEN    0x00001FFFU
+#define LCDCAM_LCD_VBK_CYCLELEN_M  (LCDCAM_LCD_VBK_CYCLELEN_V << LCDCAM_LCD_VBK_CYCLELEN_S)
+#define LCDCAM_LCD_VBK_CYCLELEN_V  0x00001FFFU
+#define LCDCAM_LCD_VBK_CYCLELEN_S  12
+/** LCDCAM_LCD_NEXT_FRAME_EN : R/W; bitpos: [25]; default: 0;
+ *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
+ *  the current frame is sent out.
+ */
+#define LCDCAM_LCD_NEXT_FRAME_EN    (BIT(25))
+#define LCDCAM_LCD_NEXT_FRAME_EN_M  (LCDCAM_LCD_NEXT_FRAME_EN_V << LCDCAM_LCD_NEXT_FRAME_EN_S)
+#define LCDCAM_LCD_NEXT_FRAME_EN_V  0x00000001U
+#define LCDCAM_LCD_NEXT_FRAME_EN_S  25
+/** LCDCAM_LCD_BK_EN : R/W; bitpos: [26]; default: 0;
+ *  1: Enable blank region when LCD sends data out. 0: No blank region.
+ */
+#define LCDCAM_LCD_BK_EN    (BIT(26))
+#define LCDCAM_LCD_BK_EN_M  (LCDCAM_LCD_BK_EN_V << LCDCAM_LCD_BK_EN_S)
+#define LCDCAM_LCD_BK_EN_V  0x00000001U
+#define LCDCAM_LCD_BK_EN_S  26
+/** LCDCAM_LCD_AFIFO_RESET : WT; bitpos: [27]; default: 0;
+ *  LCD AFIFO reset signal.
+ */
+#define LCDCAM_LCD_AFIFO_RESET    (BIT(27))
+#define LCDCAM_LCD_AFIFO_RESET_M  (LCDCAM_LCD_AFIFO_RESET_V << LCDCAM_LCD_AFIFO_RESET_S)
+#define LCDCAM_LCD_AFIFO_RESET_V  0x00000001U
+#define LCDCAM_LCD_AFIFO_RESET_S  27
+/** LCDCAM_LCD_CD_DATA_SET : R/W; bitpos: [28]; default: 0;
+ *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
+ *  reg_cd_idle_edge.
+ */
+#define LCDCAM_LCD_CD_DATA_SET    (BIT(28))
+#define LCDCAM_LCD_CD_DATA_SET_M  (LCDCAM_LCD_CD_DATA_SET_V << LCDCAM_LCD_CD_DATA_SET_S)
+#define LCDCAM_LCD_CD_DATA_SET_V  0x00000001U
+#define LCDCAM_LCD_CD_DATA_SET_S  28
+/** LCDCAM_LCD_CD_DUMMY_SET : R/W; bitpos: [29]; default: 0;
+ *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
+ *  reg_cd_idle_edge.
+ */
+#define LCDCAM_LCD_CD_DUMMY_SET    (BIT(29))
+#define LCDCAM_LCD_CD_DUMMY_SET_M  (LCDCAM_LCD_CD_DUMMY_SET_V << LCDCAM_LCD_CD_DUMMY_SET_S)
+#define LCDCAM_LCD_CD_DUMMY_SET_V  0x00000001U
+#define LCDCAM_LCD_CD_DUMMY_SET_S  29
+/** LCDCAM_LCD_CD_CMD_SET : R/W; bitpos: [30]; default: 0;
+ *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
+ *  reg_cd_idle_edge.
+ */
+#define LCDCAM_LCD_CD_CMD_SET    (BIT(30))
+#define LCDCAM_LCD_CD_CMD_SET_M  (LCDCAM_LCD_CD_CMD_SET_V << LCDCAM_LCD_CD_CMD_SET_S)
+#define LCDCAM_LCD_CD_CMD_SET_V  0x00000001U
+#define LCDCAM_LCD_CD_CMD_SET_S  30
+/** LCDCAM_LCD_CD_IDLE_EDGE : R/W; bitpos: [31]; default: 0;
+ *  The default value of LCD_CD.
+ */
+#define LCDCAM_LCD_CD_IDLE_EDGE    (BIT(31))
+#define LCDCAM_LCD_CD_IDLE_EDGE_M  (LCDCAM_LCD_CD_IDLE_EDGE_V << LCDCAM_LCD_CD_IDLE_EDGE_S)
+#define LCDCAM_LCD_CD_IDLE_EDGE_V  0x00000001U
+#define LCDCAM_LCD_CD_IDLE_EDGE_S  31
+
+/** LCDCAM_LCD_CTRL_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_CTRL_REG (DR_REG_LCDCAM_BASE + 0x1c)
+/** LCDCAM_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0;
+ *  It is the horizontal blank front porch of a frame.
+ */
+#define LCDCAM_LCD_HB_FRONT    0x000007FFU
+#define LCDCAM_LCD_HB_FRONT_M  (LCDCAM_LCD_HB_FRONT_V << LCDCAM_LCD_HB_FRONT_S)
+#define LCDCAM_LCD_HB_FRONT_V  0x000007FFU
+#define LCDCAM_LCD_HB_FRONT_S  0
+/** LCDCAM_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0;
+ *  It is the vertical active height of a frame.
+ */
+#define LCDCAM_LCD_VA_HEIGHT    0x000003FFU
+#define LCDCAM_LCD_VA_HEIGHT_M  (LCDCAM_LCD_VA_HEIGHT_V << LCDCAM_LCD_VA_HEIGHT_S)
+#define LCDCAM_LCD_VA_HEIGHT_V  0x000003FFU
+#define LCDCAM_LCD_VA_HEIGHT_S  11
+/** LCDCAM_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0;
+ *  It is the vertical total height of a frame.
+ */
+#define LCDCAM_LCD_VT_HEIGHT    0x000003FFU
+#define LCDCAM_LCD_VT_HEIGHT_M  (LCDCAM_LCD_VT_HEIGHT_V << LCDCAM_LCD_VT_HEIGHT_S)
+#define LCDCAM_LCD_VT_HEIGHT_V  0x000003FFU
+#define LCDCAM_LCD_VT_HEIGHT_S  21
+/** LCDCAM_LCD_RGB_MODE_EN : R/W; bitpos: [31]; default: 0;
+ *  1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
+ */
+#define LCDCAM_LCD_RGB_MODE_EN    (BIT(31))
+#define LCDCAM_LCD_RGB_MODE_EN_M  (LCDCAM_LCD_RGB_MODE_EN_V << LCDCAM_LCD_RGB_MODE_EN_S)
+#define LCDCAM_LCD_RGB_MODE_EN_V  0x00000001U
+#define LCDCAM_LCD_RGB_MODE_EN_S  31
+
+/** LCDCAM_LCD_CTRL1_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x20)
+/** LCDCAM_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0;
+ *  It is the vertical blank front porch of a frame.
+ */
+#define LCDCAM_LCD_VB_FRONT    0x000000FFU
+#define LCDCAM_LCD_VB_FRONT_M  (LCDCAM_LCD_VB_FRONT_V << LCDCAM_LCD_VB_FRONT_S)
+#define LCDCAM_LCD_VB_FRONT_V  0x000000FFU
+#define LCDCAM_LCD_VB_FRONT_S  0
+/** LCDCAM_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0;
+ *  It is the horizontal active width of a frame.
+ */
+#define LCDCAM_LCD_HA_WIDTH    0x00000FFFU
+#define LCDCAM_LCD_HA_WIDTH_M  (LCDCAM_LCD_HA_WIDTH_V << LCDCAM_LCD_HA_WIDTH_S)
+#define LCDCAM_LCD_HA_WIDTH_V  0x00000FFFU
+#define LCDCAM_LCD_HA_WIDTH_S  8
+/** LCDCAM_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0;
+ *  It is the horizontal total width of a frame.
+ */
+#define LCDCAM_LCD_HT_WIDTH    0x00000FFFU
+#define LCDCAM_LCD_HT_WIDTH_M  (LCDCAM_LCD_HT_WIDTH_V << LCDCAM_LCD_HT_WIDTH_S)
+#define LCDCAM_LCD_HT_WIDTH_V  0x00000FFFU
+#define LCDCAM_LCD_HT_WIDTH_S  20
+
+/** LCDCAM_LCD_CTRL2_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_CTRL2_REG (DR_REG_LCDCAM_BASE + 0x24)
+/** LCDCAM_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 1;
+ *  It is the position of LCD_VSYNC active pulse in a line.
+ */
+#define LCDCAM_LCD_VSYNC_WIDTH    0x0000007FU
+#define LCDCAM_LCD_VSYNC_WIDTH_M  (LCDCAM_LCD_VSYNC_WIDTH_V << LCDCAM_LCD_VSYNC_WIDTH_S)
+#define LCDCAM_LCD_VSYNC_WIDTH_V  0x0000007FU
+#define LCDCAM_LCD_VSYNC_WIDTH_S  0
+/** LCDCAM_LCD_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0;
+ *  It is the idle value of LCD_VSYNC.
+ */
+#define LCDCAM_LCD_VSYNC_IDLE_POL    (BIT(7))
+#define LCDCAM_LCD_VSYNC_IDLE_POL_M  (LCDCAM_LCD_VSYNC_IDLE_POL_V << LCDCAM_LCD_VSYNC_IDLE_POL_S)
+#define LCDCAM_LCD_VSYNC_IDLE_POL_V  0x00000001U
+#define LCDCAM_LCD_VSYNC_IDLE_POL_S  7
+/** LCDCAM_LCD_DE_IDLE_POL : R/W; bitpos: [8]; default: 0;
+ *  It is the idle value of LCD_DE.
+ */
+#define LCDCAM_LCD_DE_IDLE_POL    (BIT(8))
+#define LCDCAM_LCD_DE_IDLE_POL_M  (LCDCAM_LCD_DE_IDLE_POL_V << LCDCAM_LCD_DE_IDLE_POL_S)
+#define LCDCAM_LCD_DE_IDLE_POL_V  0x00000001U
+#define LCDCAM_LCD_DE_IDLE_POL_S  8
+/** LCDCAM_LCD_HS_BLANK_EN : R/W; bitpos: [9]; default: 0;
+ *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
+ *  pulse is valid only in active region lines in RGB mode.
+ */
+#define LCDCAM_LCD_HS_BLANK_EN    (BIT(9))
+#define LCDCAM_LCD_HS_BLANK_EN_M  (LCDCAM_LCD_HS_BLANK_EN_V << LCDCAM_LCD_HS_BLANK_EN_S)
+#define LCDCAM_LCD_HS_BLANK_EN_V  0x00000001U
+#define LCDCAM_LCD_HS_BLANK_EN_S  9
+/** LCDCAM_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 1;
+ *  It is the position of LCD_HSYNC active pulse in a line.
+ */
+#define LCDCAM_LCD_HSYNC_WIDTH    0x0000007FU
+#define LCDCAM_LCD_HSYNC_WIDTH_M  (LCDCAM_LCD_HSYNC_WIDTH_V << LCDCAM_LCD_HSYNC_WIDTH_S)
+#define LCDCAM_LCD_HSYNC_WIDTH_V  0x0000007FU
+#define LCDCAM_LCD_HSYNC_WIDTH_S  16
+/** LCDCAM_LCD_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0;
+ *  It is the idle value of LCD_HSYNC.
+ */
+#define LCDCAM_LCD_HSYNC_IDLE_POL    (BIT(23))
+#define LCDCAM_LCD_HSYNC_IDLE_POL_M  (LCDCAM_LCD_HSYNC_IDLE_POL_V << LCDCAM_LCD_HSYNC_IDLE_POL_S)
+#define LCDCAM_LCD_HSYNC_IDLE_POL_V  0x00000001U
+#define LCDCAM_LCD_HSYNC_IDLE_POL_S  23
+/** LCDCAM_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0;
+ *  It is the position of LCD_HSYNC active pulse in a line.
+ */
+#define LCDCAM_LCD_HSYNC_POSITION    0x000000FFU
+#define LCDCAM_LCD_HSYNC_POSITION_M  (LCDCAM_LCD_HSYNC_POSITION_V << LCDCAM_LCD_HSYNC_POSITION_S)
+#define LCDCAM_LCD_HSYNC_POSITION_V  0x000000FFU
+#define LCDCAM_LCD_HSYNC_POSITION_S  24
+
+/** LCDCAM_LCD_FIRST_CMD_VAL_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_FIRST_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x28)
+/** LCDCAM_LCD_FIRST_CMD_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  The LCD write command value of first cmd cycle.
+ */
+#define LCDCAM_LCD_FIRST_CMD_VALUE    0xFFFFFFFFU
+#define LCDCAM_LCD_FIRST_CMD_VALUE_M  (LCDCAM_LCD_FIRST_CMD_VALUE_V << LCDCAM_LCD_FIRST_CMD_VALUE_S)
+#define LCDCAM_LCD_FIRST_CMD_VALUE_V  0xFFFFFFFFU
+#define LCDCAM_LCD_FIRST_CMD_VALUE_S  0
+
+/** LCDCAM_LCD_LATTER_CMD_VAL_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_LATTER_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x2c)
+/** LCDCAM_LCD_LATTER_CMD_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  The LCD write command value of latter cmd cycle.
+ */
+#define LCDCAM_LCD_LATTER_CMD_VALUE    0xFFFFFFFFU
+#define LCDCAM_LCD_LATTER_CMD_VALUE_M  (LCDCAM_LCD_LATTER_CMD_VALUE_V << LCDCAM_LCD_LATTER_CMD_VALUE_S)
+#define LCDCAM_LCD_LATTER_CMD_VALUE_V  0xFFFFFFFFU
+#define LCDCAM_LCD_LATTER_CMD_VALUE_S  0
+
+/** LCDCAM_LCD_DLY_MODE_CFG1_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_DLY_MODE_CFG1_REG (DR_REG_LCDCAM_BASE + 0x30)
+/** LCDCAM_DOUT16_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT16_MODE    0x00000003U
+#define LCDCAM_DOUT16_MODE_M  (LCDCAM_DOUT16_MODE_V << LCDCAM_DOUT16_MODE_S)
+#define LCDCAM_DOUT16_MODE_V  0x00000003U
+#define LCDCAM_DOUT16_MODE_S  0
+/** LCDCAM_DOUT17_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT17_MODE    0x00000003U
+#define LCDCAM_DOUT17_MODE_M  (LCDCAM_DOUT17_MODE_V << LCDCAM_DOUT17_MODE_S)
+#define LCDCAM_DOUT17_MODE_V  0x00000003U
+#define LCDCAM_DOUT17_MODE_S  2
+/** LCDCAM_DOUT18_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT18_MODE    0x00000003U
+#define LCDCAM_DOUT18_MODE_M  (LCDCAM_DOUT18_MODE_V << LCDCAM_DOUT18_MODE_S)
+#define LCDCAM_DOUT18_MODE_V  0x00000003U
+#define LCDCAM_DOUT18_MODE_S  4
+/** LCDCAM_DOUT19_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT19_MODE    0x00000003U
+#define LCDCAM_DOUT19_MODE_M  (LCDCAM_DOUT19_MODE_V << LCDCAM_DOUT19_MODE_S)
+#define LCDCAM_DOUT19_MODE_V  0x00000003U
+#define LCDCAM_DOUT19_MODE_S  6
+/** LCDCAM_DOUT20_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT20_MODE    0x00000003U
+#define LCDCAM_DOUT20_MODE_M  (LCDCAM_DOUT20_MODE_V << LCDCAM_DOUT20_MODE_S)
+#define LCDCAM_DOUT20_MODE_V  0x00000003U
+#define LCDCAM_DOUT20_MODE_S  8
+/** LCDCAM_DOUT21_MODE : R/W; bitpos: [11:10]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT21_MODE    0x00000003U
+#define LCDCAM_DOUT21_MODE_M  (LCDCAM_DOUT21_MODE_V << LCDCAM_DOUT21_MODE_S)
+#define LCDCAM_DOUT21_MODE_V  0x00000003U
+#define LCDCAM_DOUT21_MODE_S  10
+/** LCDCAM_DOUT22_MODE : R/W; bitpos: [13:12]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT22_MODE    0x00000003U
+#define LCDCAM_DOUT22_MODE_M  (LCDCAM_DOUT22_MODE_V << LCDCAM_DOUT22_MODE_S)
+#define LCDCAM_DOUT22_MODE_V  0x00000003U
+#define LCDCAM_DOUT22_MODE_S  12
+/** LCDCAM_DOUT23_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT23_MODE    0x00000003U
+#define LCDCAM_DOUT23_MODE_M  (LCDCAM_DOUT23_MODE_V << LCDCAM_DOUT23_MODE_S)
+#define LCDCAM_DOUT23_MODE_V  0x00000003U
+#define LCDCAM_DOUT23_MODE_S  14
+/** LCDCAM_LCD_CD_MODE : R/W; bitpos: [17:16]; default: 0;
+ *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+ *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCDCAM_LCD_CD_MODE    0x00000003U
+#define LCDCAM_LCD_CD_MODE_M  (LCDCAM_LCD_CD_MODE_V << LCDCAM_LCD_CD_MODE_S)
+#define LCDCAM_LCD_CD_MODE_V  0x00000003U
+#define LCDCAM_LCD_CD_MODE_S  16
+/** LCDCAM_LCD_DE_MODE : R/W; bitpos: [19:18]; default: 0;
+ *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+ *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCDCAM_LCD_DE_MODE    0x00000003U
+#define LCDCAM_LCD_DE_MODE_M  (LCDCAM_LCD_DE_MODE_V << LCDCAM_LCD_DE_MODE_S)
+#define LCDCAM_LCD_DE_MODE_V  0x00000003U
+#define LCDCAM_LCD_DE_MODE_S  18
+/** LCDCAM_LCD_HSYNC_MODE : R/W; bitpos: [21:20]; default: 0;
+ *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+ *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCDCAM_LCD_HSYNC_MODE    0x00000003U
+#define LCDCAM_LCD_HSYNC_MODE_M  (LCDCAM_LCD_HSYNC_MODE_V << LCDCAM_LCD_HSYNC_MODE_S)
+#define LCDCAM_LCD_HSYNC_MODE_V  0x00000003U
+#define LCDCAM_LCD_HSYNC_MODE_S  20
+/** LCDCAM_LCD_VSYNC_MODE : R/W; bitpos: [23:22]; default: 0;
+ *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+ *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCDCAM_LCD_VSYNC_MODE    0x00000003U
+#define LCDCAM_LCD_VSYNC_MODE_M  (LCDCAM_LCD_VSYNC_MODE_V << LCDCAM_LCD_VSYNC_MODE_S)
+#define LCDCAM_LCD_VSYNC_MODE_V  0x00000003U
+#define LCDCAM_LCD_VSYNC_MODE_S  22
+
+/** LCDCAM_LCD_DLY_MODE_CFG2_REG register
+ *  LCD config register.
+ */
+#define LCDCAM_LCD_DLY_MODE_CFG2_REG (DR_REG_LCDCAM_BASE + 0x38)
+/** LCDCAM_DOUT0_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT0_MODE    0x00000003U
+#define LCDCAM_DOUT0_MODE_M  (LCDCAM_DOUT0_MODE_V << LCDCAM_DOUT0_MODE_S)
+#define LCDCAM_DOUT0_MODE_V  0x00000003U
+#define LCDCAM_DOUT0_MODE_S  0
+/** LCDCAM_DOUT1_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT1_MODE    0x00000003U
+#define LCDCAM_DOUT1_MODE_M  (LCDCAM_DOUT1_MODE_V << LCDCAM_DOUT1_MODE_S)
+#define LCDCAM_DOUT1_MODE_V  0x00000003U
+#define LCDCAM_DOUT1_MODE_S  2
+/** LCDCAM_DOUT2_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT2_MODE    0x00000003U
+#define LCDCAM_DOUT2_MODE_M  (LCDCAM_DOUT2_MODE_V << LCDCAM_DOUT2_MODE_S)
+#define LCDCAM_DOUT2_MODE_V  0x00000003U
+#define LCDCAM_DOUT2_MODE_S  4
+/** LCDCAM_DOUT3_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT3_MODE    0x00000003U
+#define LCDCAM_DOUT3_MODE_M  (LCDCAM_DOUT3_MODE_V << LCDCAM_DOUT3_MODE_S)
+#define LCDCAM_DOUT3_MODE_V  0x00000003U
+#define LCDCAM_DOUT3_MODE_S  6
+/** LCDCAM_DOUT4_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT4_MODE    0x00000003U
+#define LCDCAM_DOUT4_MODE_M  (LCDCAM_DOUT4_MODE_V << LCDCAM_DOUT4_MODE_S)
+#define LCDCAM_DOUT4_MODE_V  0x00000003U
+#define LCDCAM_DOUT4_MODE_S  8
+/** LCDCAM_DOUT5_MODE : R/W; bitpos: [11:10]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT5_MODE    0x00000003U
+#define LCDCAM_DOUT5_MODE_M  (LCDCAM_DOUT5_MODE_V << LCDCAM_DOUT5_MODE_S)
+#define LCDCAM_DOUT5_MODE_V  0x00000003U
+#define LCDCAM_DOUT5_MODE_S  10
+/** LCDCAM_DOUT6_MODE : R/W; bitpos: [13:12]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT6_MODE    0x00000003U
+#define LCDCAM_DOUT6_MODE_M  (LCDCAM_DOUT6_MODE_V << LCDCAM_DOUT6_MODE_S)
+#define LCDCAM_DOUT6_MODE_V  0x00000003U
+#define LCDCAM_DOUT6_MODE_S  12
+/** LCDCAM_DOUT7_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT7_MODE    0x00000003U
+#define LCDCAM_DOUT7_MODE_M  (LCDCAM_DOUT7_MODE_V << LCDCAM_DOUT7_MODE_S)
+#define LCDCAM_DOUT7_MODE_V  0x00000003U
+#define LCDCAM_DOUT7_MODE_S  14
+/** LCDCAM_DOUT8_MODE : R/W; bitpos: [17:16]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT8_MODE    0x00000003U
+#define LCDCAM_DOUT8_MODE_M  (LCDCAM_DOUT8_MODE_V << LCDCAM_DOUT8_MODE_S)
+#define LCDCAM_DOUT8_MODE_V  0x00000003U
+#define LCDCAM_DOUT8_MODE_S  16
+/** LCDCAM_DOUT9_MODE : R/W; bitpos: [19:18]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT9_MODE    0x00000003U
+#define LCDCAM_DOUT9_MODE_M  (LCDCAM_DOUT9_MODE_V << LCDCAM_DOUT9_MODE_S)
+#define LCDCAM_DOUT9_MODE_V  0x00000003U
+#define LCDCAM_DOUT9_MODE_S  18
+/** LCDCAM_DOUT10_MODE : R/W; bitpos: [21:20]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT10_MODE    0x00000003U
+#define LCDCAM_DOUT10_MODE_M  (LCDCAM_DOUT10_MODE_V << LCDCAM_DOUT10_MODE_S)
+#define LCDCAM_DOUT10_MODE_V  0x00000003U
+#define LCDCAM_DOUT10_MODE_S  20
+/** LCDCAM_DOUT11_MODE : R/W; bitpos: [23:22]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT11_MODE    0x00000003U
+#define LCDCAM_DOUT11_MODE_M  (LCDCAM_DOUT11_MODE_V << LCDCAM_DOUT11_MODE_S)
+#define LCDCAM_DOUT11_MODE_V  0x00000003U
+#define LCDCAM_DOUT11_MODE_S  22
+/** LCDCAM_DOUT12_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT12_MODE    0x00000003U
+#define LCDCAM_DOUT12_MODE_M  (LCDCAM_DOUT12_MODE_V << LCDCAM_DOUT12_MODE_S)
+#define LCDCAM_DOUT12_MODE_V  0x00000003U
+#define LCDCAM_DOUT12_MODE_S  24
+/** LCDCAM_DOUT13_MODE : R/W; bitpos: [27:26]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT13_MODE    0x00000003U
+#define LCDCAM_DOUT13_MODE_M  (LCDCAM_DOUT13_MODE_V << LCDCAM_DOUT13_MODE_S)
+#define LCDCAM_DOUT13_MODE_V  0x00000003U
+#define LCDCAM_DOUT13_MODE_S  26
+/** LCDCAM_DOUT14_MODE : R/W; bitpos: [29:28]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT14_MODE    0x00000003U
+#define LCDCAM_DOUT14_MODE_M  (LCDCAM_DOUT14_MODE_V << LCDCAM_DOUT14_MODE_S)
+#define LCDCAM_DOUT14_MODE_V  0x00000003U
+#define LCDCAM_DOUT14_MODE_S  28
+/** LCDCAM_DOUT15_MODE : R/W; bitpos: [31:30]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCDCAM_DOUT15_MODE    0x00000003U
+#define LCDCAM_DOUT15_MODE_M  (LCDCAM_DOUT15_MODE_V << LCDCAM_DOUT15_MODE_S)
+#define LCDCAM_DOUT15_MODE_V  0x00000003U
+#define LCDCAM_DOUT15_MODE_S  30
+
+/** LCDCAM_LC_DMA_INT_ENA_REG register
+ *  LCDCAM interrupt enable register.
+ */
+#define LCDCAM_LC_DMA_INT_ENA_REG (DR_REG_LCDCAM_BASE + 0x64)
+/** LCDCAM_LCD_VSYNC_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for LCD frame end interrupt.
+ */
+#define LCDCAM_LCD_VSYNC_INT_ENA    (BIT(0))
+#define LCDCAM_LCD_VSYNC_INT_ENA_M  (LCDCAM_LCD_VSYNC_INT_ENA_V << LCDCAM_LCD_VSYNC_INT_ENA_S)
+#define LCDCAM_LCD_VSYNC_INT_ENA_V  0x00000001U
+#define LCDCAM_LCD_VSYNC_INT_ENA_S  0
+/** LCDCAM_LCD_TRANS_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for lcd transfer end interrupt.
+ */
+#define LCDCAM_LCD_TRANS_DONE_INT_ENA    (BIT(1))
+#define LCDCAM_LCD_TRANS_DONE_INT_ENA_M  (LCDCAM_LCD_TRANS_DONE_INT_ENA_V << LCDCAM_LCD_TRANS_DONE_INT_ENA_S)
+#define LCDCAM_LCD_TRANS_DONE_INT_ENA_V  0x00000001U
+#define LCDCAM_LCD_TRANS_DONE_INT_ENA_S  1
+/** LCDCAM_CAM_VSYNC_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for Camera frame end interrupt.
+ */
+#define LCDCAM_CAM_VSYNC_INT_ENA    (BIT(2))
+#define LCDCAM_CAM_VSYNC_INT_ENA_M  (LCDCAM_CAM_VSYNC_INT_ENA_V << LCDCAM_CAM_VSYNC_INT_ENA_S)
+#define LCDCAM_CAM_VSYNC_INT_ENA_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_INT_ENA_S  2
+/** LCDCAM_CAM_HS_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for Camera line interrupt.
+ */
+#define LCDCAM_CAM_HS_INT_ENA    (BIT(3))
+#define LCDCAM_CAM_HS_INT_ENA_M  (LCDCAM_CAM_HS_INT_ENA_V << LCDCAM_CAM_HS_INT_ENA_S)
+#define LCDCAM_CAM_HS_INT_ENA_V  0x00000001U
+#define LCDCAM_CAM_HS_INT_ENA_S  3
+/** LCDCAM_LCD_UNDERRUN_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for LCD underrun interrupt
+ */
+#define LCDCAM_LCD_UNDERRUN_INT_ENA    (BIT(4))
+#define LCDCAM_LCD_UNDERRUN_INT_ENA_M  (LCDCAM_LCD_UNDERRUN_INT_ENA_V << LCDCAM_LCD_UNDERRUN_INT_ENA_S)
+#define LCDCAM_LCD_UNDERRUN_INT_ENA_V  0x00000001U
+#define LCDCAM_LCD_UNDERRUN_INT_ENA_S  4
+
+/** LCDCAM_LC_DMA_INT_RAW_REG register
+ *  LCDCAM interrupt raw register, valid in level.
+ */
+#define LCDCAM_LC_DMA_INT_RAW_REG (DR_REG_LCDCAM_BASE + 0x68)
+/** LCDCAM_LCD_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit for LCD frame end interrupt.
+ */
+#define LCDCAM_LCD_VSYNC_INT_RAW    (BIT(0))
+#define LCDCAM_LCD_VSYNC_INT_RAW_M  (LCDCAM_LCD_VSYNC_INT_RAW_V << LCDCAM_LCD_VSYNC_INT_RAW_S)
+#define LCDCAM_LCD_VSYNC_INT_RAW_V  0x00000001U
+#define LCDCAM_LCD_VSYNC_INT_RAW_S  0
+/** LCDCAM_LCD_TRANS_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit for lcd transfer end interrupt.
+ */
+#define LCDCAM_LCD_TRANS_DONE_INT_RAW    (BIT(1))
+#define LCDCAM_LCD_TRANS_DONE_INT_RAW_M  (LCDCAM_LCD_TRANS_DONE_INT_RAW_V << LCDCAM_LCD_TRANS_DONE_INT_RAW_S)
+#define LCDCAM_LCD_TRANS_DONE_INT_RAW_V  0x00000001U
+#define LCDCAM_LCD_TRANS_DONE_INT_RAW_S  1
+/** LCDCAM_CAM_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for Camera frame end interrupt.
+ */
+#define LCDCAM_CAM_VSYNC_INT_RAW    (BIT(2))
+#define LCDCAM_CAM_VSYNC_INT_RAW_M  (LCDCAM_CAM_VSYNC_INT_RAW_V << LCDCAM_CAM_VSYNC_INT_RAW_S)
+#define LCDCAM_CAM_VSYNC_INT_RAW_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_INT_RAW_S  2
+/** LCDCAM_CAM_HS_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for Camera line interrupt.
+ */
+#define LCDCAM_CAM_HS_INT_RAW    (BIT(3))
+#define LCDCAM_CAM_HS_INT_RAW_M  (LCDCAM_CAM_HS_INT_RAW_V << LCDCAM_CAM_HS_INT_RAW_S)
+#define LCDCAM_CAM_HS_INT_RAW_V  0x00000001U
+#define LCDCAM_CAM_HS_INT_RAW_S  3
+/** LCDCAM_LCD_UNDERRUN_INT_RAW : RO/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for LCD underrun interrupt
+ */
+#define LCDCAM_LCD_UNDERRUN_INT_RAW    (BIT(4))
+#define LCDCAM_LCD_UNDERRUN_INT_RAW_M  (LCDCAM_LCD_UNDERRUN_INT_RAW_V << LCDCAM_LCD_UNDERRUN_INT_RAW_S)
+#define LCDCAM_LCD_UNDERRUN_INT_RAW_V  0x00000001U
+#define LCDCAM_LCD_UNDERRUN_INT_RAW_S  4
+
+/** LCDCAM_LC_DMA_INT_ST_REG register
+ *  LCDCAM interrupt status register.
+ */
+#define LCDCAM_LC_DMA_INT_ST_REG (DR_REG_LCDCAM_BASE + 0x6c)
+/** LCDCAM_LCD_VSYNC_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for LCD frame end interrupt.
+ */
+#define LCDCAM_LCD_VSYNC_INT_ST    (BIT(0))
+#define LCDCAM_LCD_VSYNC_INT_ST_M  (LCDCAM_LCD_VSYNC_INT_ST_V << LCDCAM_LCD_VSYNC_INT_ST_S)
+#define LCDCAM_LCD_VSYNC_INT_ST_V  0x00000001U
+#define LCDCAM_LCD_VSYNC_INT_ST_S  0
+/** LCDCAM_LCD_TRANS_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for lcd transfer end interrupt.
+ */
+#define LCDCAM_LCD_TRANS_DONE_INT_ST    (BIT(1))
+#define LCDCAM_LCD_TRANS_DONE_INT_ST_M  (LCDCAM_LCD_TRANS_DONE_INT_ST_V << LCDCAM_LCD_TRANS_DONE_INT_ST_S)
+#define LCDCAM_LCD_TRANS_DONE_INT_ST_V  0x00000001U
+#define LCDCAM_LCD_TRANS_DONE_INT_ST_S  1
+/** LCDCAM_CAM_VSYNC_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for Camera frame end interrupt.
+ */
+#define LCDCAM_CAM_VSYNC_INT_ST    (BIT(2))
+#define LCDCAM_CAM_VSYNC_INT_ST_M  (LCDCAM_CAM_VSYNC_INT_ST_V << LCDCAM_CAM_VSYNC_INT_ST_S)
+#define LCDCAM_CAM_VSYNC_INT_ST_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_INT_ST_S  2
+/** LCDCAM_CAM_HS_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for Camera transfer end interrupt.
+ */
+#define LCDCAM_CAM_HS_INT_ST    (BIT(3))
+#define LCDCAM_CAM_HS_INT_ST_M  (LCDCAM_CAM_HS_INT_ST_V << LCDCAM_CAM_HS_INT_ST_S)
+#define LCDCAM_CAM_HS_INT_ST_V  0x00000001U
+#define LCDCAM_CAM_HS_INT_ST_S  3
+/** LCDCAM_LCD_UNDERRUN_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for LCD underrun interrupt
+ */
+#define LCDCAM_LCD_UNDERRUN_INT_ST    (BIT(4))
+#define LCDCAM_LCD_UNDERRUN_INT_ST_M  (LCDCAM_LCD_UNDERRUN_INT_ST_V << LCDCAM_LCD_UNDERRUN_INT_ST_S)
+#define LCDCAM_LCD_UNDERRUN_INT_ST_V  0x00000001U
+#define LCDCAM_LCD_UNDERRUN_INT_ST_S  4
+
+/** LCDCAM_LC_DMA_INT_CLR_REG register
+ *  LCDCAM interrupt clear register.
+ */
+#define LCDCAM_LC_DMA_INT_CLR_REG (DR_REG_LCDCAM_BASE + 0x70)
+/** LCDCAM_LCD_VSYNC_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for LCD frame end interrupt.
+ */
+#define LCDCAM_LCD_VSYNC_INT_CLR    (BIT(0))
+#define LCDCAM_LCD_VSYNC_INT_CLR_M  (LCDCAM_LCD_VSYNC_INT_CLR_V << LCDCAM_LCD_VSYNC_INT_CLR_S)
+#define LCDCAM_LCD_VSYNC_INT_CLR_V  0x00000001U
+#define LCDCAM_LCD_VSYNC_INT_CLR_S  0
+/** LCDCAM_LCD_TRANS_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for lcd transfer end interrupt.
+ */
+#define LCDCAM_LCD_TRANS_DONE_INT_CLR    (BIT(1))
+#define LCDCAM_LCD_TRANS_DONE_INT_CLR_M  (LCDCAM_LCD_TRANS_DONE_INT_CLR_V << LCDCAM_LCD_TRANS_DONE_INT_CLR_S)
+#define LCDCAM_LCD_TRANS_DONE_INT_CLR_V  0x00000001U
+#define LCDCAM_LCD_TRANS_DONE_INT_CLR_S  1
+/** LCDCAM_CAM_VSYNC_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for Camera frame end interrupt.
+ */
+#define LCDCAM_CAM_VSYNC_INT_CLR    (BIT(2))
+#define LCDCAM_CAM_VSYNC_INT_CLR_M  (LCDCAM_CAM_VSYNC_INT_CLR_V << LCDCAM_CAM_VSYNC_INT_CLR_S)
+#define LCDCAM_CAM_VSYNC_INT_CLR_V  0x00000001U
+#define LCDCAM_CAM_VSYNC_INT_CLR_S  2
+/** LCDCAM_CAM_HS_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for Camera line interrupt.
+ */
+#define LCDCAM_CAM_HS_INT_CLR    (BIT(3))
+#define LCDCAM_CAM_HS_INT_CLR_M  (LCDCAM_CAM_HS_INT_CLR_V << LCDCAM_CAM_HS_INT_CLR_S)
+#define LCDCAM_CAM_HS_INT_CLR_V  0x00000001U
+#define LCDCAM_CAM_HS_INT_CLR_S  3
+/** LCDCAM_LCD_UNDERRUN_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for LCD underrun interrupt
+ */
+#define LCDCAM_LCD_UNDERRUN_INT_CLR    (BIT(4))
+#define LCDCAM_LCD_UNDERRUN_INT_CLR_M  (LCDCAM_LCD_UNDERRUN_INT_CLR_V << LCDCAM_LCD_UNDERRUN_INT_CLR_S)
+#define LCDCAM_LCD_UNDERRUN_INT_CLR_V  0x00000001U
+#define LCDCAM_LCD_UNDERRUN_INT_CLR_S  4
+
+/** LCDCAM_LC_REG_DATE_REG register
+ *  Version register
+ */
+#define LCDCAM_LC_REG_DATE_REG (DR_REG_LCDCAM_BASE + 0xfc)
+/** LCDCAM_LC_DATE : R/W; bitpos: [27:0]; default: 38806054;
+ *  LCD_CAM version control register
+ */
+#define LCDCAM_LC_DATE    0x0FFFFFFFU
+#define LCDCAM_LC_DATE_M  (LCDCAM_LC_DATE_V << LCDCAM_LC_DATE_S)
+#define LCDCAM_LC_DATE_V  0x0FFFFFFFU
+#define LCDCAM_LC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h
new file mode 100644
index 0000000000..470ef9961a
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h
@@ -0,0 +1,857 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: lcd configuration registers */
+/** Type of lcd_clock register
+ *  LCD clock config register.
+ */
+typedef union {
+    struct {
+        /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3;
+         *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
+         */
+        uint32_t lcd_clkcnt_n:6;
+        /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1;
+         *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
+         */
+        uint32_t lcd_clk_equ_sysclk:1;
+        /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0;
+         *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
+         */
+        uint32_t lcd_ck_idle_edge:1;
+        /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0;
+         *  1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low
+         *  in the second half data cycle.
+         */
+        uint32_t lcd_ck_out_edge:1;
+        /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral LCD clock divider value
+         */
+        uint32_t lcd_clkm_div_num:8;
+        /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t lcd_clkm_div_b:6;
+        /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t lcd_clkm_div_a:6;
+        /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t lcd_clk_sel:2;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_clock_reg_t;
+
+/** Type of lcd_rgb_yuv register
+ *  LCD YUV/RGB converter configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t lcd_conv_8bits_data_inv:1;
+        /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0;
+         *  0: txtorx mode off. 1: txtorx mode on.
+         */
+        uint32_t lcd_conv_txtorx:1;
+        /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+         *  trans_mode must be set to 1.
+         */
+        uint32_t lcd_conv_yuv2yuv_mode:2;
+        /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+         *  mode of Data_in
+         */
+        uint32_t lcd_conv_yuv_mode:2;
+        /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t lcd_conv_protocol_mode:1;
+        /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_out_mode:1;
+        /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_in_mode:1;
+        /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t lcd_conv_mode_8bits_on:1;
+        /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t lcd_conv_trans_mode:1;
+        /** lcd_conv_enable : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t lcd_conv_enable:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_rgb_yuv_reg_t;
+
+/** Type of lcd_user register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1;
+         *  The output data cycles minus 1 of LCD module.
+         */
+        uint32_t lcd_dout_cyclelen:13;
+        /** lcd_always_out_en : R/W; bitpos: [13]; default: 0;
+         *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
+         *  reg_lcd_reset is set.
+         */
+        uint32_t lcd_always_out_en:1;
+        /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0;
+         *  0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
+         */
+        uint32_t lcd_dout_byte_swizzle_mode:3;
+        /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0;
+         *  1: enable byte swizzle 0: disable
+         */
+        uint32_t lcd_dout_byte_swizzle_enable:1;
+        /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0;
+         *  1: change bit order in every byte. 0: Not change.
+         */
+        uint32_t lcd_dout_bit_order:1;
+        /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0;
+         *  2: 24bit mode. 1: 16bit mode. 0: 8bit mode
+         */
+        uint32_t lcd_byte_mode:2;
+        /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0;
+         *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t lcd_update_reg:1;
+        /** lcd_bit_order : R/W; bitpos: [22]; default: 0;
+         *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t lcd_bit_order:1;
+        /** lcd_byte_order : R/W; bitpos: [23]; default: 0;
+         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         */
+        uint32_t lcd_byte_order:1;
+        /** lcd_dout : R/W; bitpos: [24]; default: 0;
+         *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dout:1;
+        /** lcd_dummy : R/W; bitpos: [25]; default: 0;
+         *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dummy:1;
+        /** lcd_cmd : R/W; bitpos: [26]; default: 0;
+         *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_cmd:1;
+        /** lcd_start : R/W/SC; bitpos: [27]; default: 0;
+         *  LCD start sending data enable signal, valid in high level.
+         */
+        uint32_t lcd_start:1;
+        /** lcd_reset : WT; bitpos: [28]; default: 0;
+         *  The value of  command.
+         */
+        uint32_t lcd_reset:1;
+        /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0;
+         *  The dummy cycle length minus 1.
+         */
+        uint32_t lcd_dummy_cyclelen:2;
+        /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0;
+         *  The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
+         */
+        uint32_t lcd_cmd_2_cycle_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_user_reg_t;
+
+/** Type of lcd_misc register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
+         */
+        uint32_t lcd_wire_mode:2;
+        /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3;
+         *  The setup cycle length minus 1 in LCD non-RGB mode.
+         */
+        uint32_t lcd_vfk_cyclelen:6;
+        /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0;
+         *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
+         *  time cycle length in LCD non-RGB mode.
+         */
+        uint32_t lcd_vbk_cyclelen:13;
+        /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0;
+         *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
+         *  the current frame is sent out.
+         */
+        uint32_t lcd_next_frame_en:1;
+        /** lcd_bk_en : R/W; bitpos: [26]; default: 0;
+         *  1: Enable blank region when LCD sends data out. 0: No blank region.
+         */
+        uint32_t lcd_bk_en:1;
+        /** lcd_afifo_reset : WT; bitpos: [27]; default: 0;
+         *  LCD AFIFO reset signal.
+         */
+        uint32_t lcd_afifo_reset:1;
+        /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_data_set:1;
+        /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_dummy_set:1;
+        /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_cmd_set:1;
+        /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0;
+         *  The default value of LCD_CD.
+         */
+        uint32_t lcd_cd_idle_edge:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_misc_reg_t;
+
+/** Type of lcd_ctrl register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0;
+         *  It is the horizontal blank front porch of a frame.
+         */
+        uint32_t lcd_hb_front:11;
+        /** lcd_va_height : R/W; bitpos: [20:11]; default: 0;
+         *  It is the vertical active height of a frame.
+         */
+        uint32_t lcd_va_height:10;
+        /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0;
+         *  It is the vertical total height of a frame.
+         */
+        uint32_t lcd_vt_height:10;
+        /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0;
+         *  1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
+         */
+        uint32_t lcd_rgb_mode_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl_reg_t;
+
+/** Type of lcd_ctrl1 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0;
+         *  It is the vertical blank front porch of a frame.
+         */
+        uint32_t lcd_vb_front:8;
+        /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0;
+         *  It is the horizontal active width of a frame.
+         */
+        uint32_t lcd_ha_width:12;
+        /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0;
+         *  It is the horizontal total width of a frame.
+         */
+        uint32_t lcd_ht_width:12;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl1_reg_t;
+
+/** Type of lcd_ctrl2 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1;
+         *  It is the position of LCD_VSYNC active pulse in a line.
+         */
+        uint32_t lcd_vsync_width:7;
+        /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0;
+         *  It is the idle value of LCD_VSYNC.
+         */
+        uint32_t lcd_vsync_idle_pol:1;
+        /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0;
+         *  It is the idle value of LCD_DE.
+         */
+        uint32_t lcd_de_idle_pol:1;
+        /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0;
+         *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
+         *  pulse is valid only in active region lines in RGB mode.
+         */
+        uint32_t lcd_hs_blank_en:1;
+        uint32_t reserved_10:6;
+        /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_width:7;
+        /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0;
+         *  It is the idle value of LCD_HSYNC.
+         */
+        uint32_t lcd_hsync_idle_pol:1;
+        /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_position:8;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl2_reg_t;
+
+/** Type of lcd_first_cmd_val register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value of first cmd cycle.
+         */
+        uint32_t lcd_first_cmd_value:32;
+    };
+    uint32_t val;
+} lcdcam_lcd_first_cmd_val_reg_t;
+
+/** Type of lcd_latter_cmd_val register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value of latter cmd cycle.
+         */
+        uint32_t lcd_latter_cmd_value:32;
+    };
+    uint32_t val;
+} lcdcam_lcd_latter_cmd_val_reg_t;
+
+/** Type of lcd_dly_mode_cfg1 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** dout16_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout16_mode:2;
+        /** dout17_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout17_mode:2;
+        /** dout18_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout18_mode:2;
+        /** dout19_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout19_mode:2;
+        /** dout20_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout20_mode:2;
+        /** dout21_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout21_mode:2;
+        /** dout22_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout22_mode:2;
+        /** dout23_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout23_mode:2;
+        /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_cd_mode:2;
+        /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_de_mode:2;
+        /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_hsync_mode:2;
+        /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_vsync_mode:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lcdcam_lcd_dly_mode_cfg1_reg_t;
+
+/** Type of lcd_dly_mode_cfg2 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout0_mode:2;
+        /** dout1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout1_mode:2;
+        /** dout2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout2_mode:2;
+        /** dout3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout3_mode:2;
+        /** dout4_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout4_mode:2;
+        /** dout5_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout5_mode:2;
+        /** dout6_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout6_mode:2;
+        /** dout7_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout7_mode:2;
+        /** dout8_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout8_mode:2;
+        /** dout9_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout9_mode:2;
+        /** dout10_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout10_mode:2;
+        /** dout11_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout11_mode:2;
+        /** dout12_mode : R/W; bitpos: [25:24]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout12_mode:2;
+        /** dout13_mode : R/W; bitpos: [27:26]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout13_mode:2;
+        /** dout14_mode : R/W; bitpos: [29:28]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout14_mode:2;
+        /** dout15_mode : R/W; bitpos: [31:30]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout15_mode:2;
+    };
+    uint32_t val;
+} lcdcam_lcd_dly_mode_cfg2_reg_t;
+
+
+/** Group: cam configuration registers */
+/** Type of cam_ctrl register
+ *  CAM config register.
+ */
+typedef union {
+    struct {
+        /** cam_stop_en : R/W; bitpos: [0]; default: 0;
+         *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
+         */
+        uint32_t cam_stop_en:1;
+        /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0;
+         *  Filter threshold value for CAM_VSYNC signal.
+         */
+        uint32_t cam_vsync_filter_thres:3;
+        /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0;
+         *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t cam_update_reg:1;
+        /** cam_byte_order : R/W; bitpos: [5]; default: 0;
+         *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t cam_byte_order:1;
+        /** cam_bit_order : R/W; bitpos: [6]; default: 0;
+         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         */
+        uint32_t cam_bit_order:1;
+        /** cam_line_int_en : R/W; bitpos: [7]; default: 0;
+         *  1: Enable to generate CAM_HS_INT. 0: Disable.
+         */
+        uint32_t cam_line_int_en:1;
+        /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0;
+         *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
+         *  reg_cam_rec_data_cyclelen.
+         */
+        uint32_t cam_vs_eof_en:1;
+        /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral Camera clock divider value
+         */
+        uint32_t cam_clkm_div_num:8;
+        /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t cam_clkm_div_b:6;
+        /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t cam_clkm_div_a:6;
+        /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t cam_clk_sel:2;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} lcdcam_cam_ctrl_reg_t;
+
+/** Type of cam_ctrl1 register
+ *  CAM config register.
+ */
+typedef union {
+    struct {
+        /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0;
+         *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
+         */
+        uint32_t cam_rec_data_bytelen:16;
+        /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0;
+         *  The line number minus 1 to generate cam_hs_int.
+         */
+        uint32_t cam_line_int_num:6;
+        /** cam_clk_inv : R/W; bitpos: [22]; default: 0;
+         *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
+         */
+        uint32_t cam_clk_inv:1;
+        /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0;
+         *  1: Enable CAM_VSYNC filter function. 0: bypass.
+         */
+        uint32_t cam_vsync_filter_en:1;
+        /** cam_2byte_en : R/W; bitpos: [24]; default: 0;
+         *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
+         */
+        uint32_t cam_2byte_en:1;
+        /** cam_de_inv : R/W; bitpos: [25]; default: 0;
+         *  CAM_DE invert enable signal, valid in high level.
+         */
+        uint32_t cam_de_inv:1;
+        /** cam_hsync_inv : R/W; bitpos: [26]; default: 0;
+         *  CAM_HSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_hsync_inv:1;
+        /** cam_vsync_inv : R/W; bitpos: [27]; default: 0;
+         *  CAM_VSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_vsync_inv:1;
+        /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0;
+         *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
+         *  signals are CAM_DE and CAM_VSYNC.
+         */
+        uint32_t cam_vh_de_mode_en:1;
+        /** cam_start : R/W/SC; bitpos: [29]; default: 0;
+         *  Camera module start signal.
+         */
+        uint32_t cam_start:1;
+        /** cam_reset : WT; bitpos: [30]; default: 0;
+         *  Camera module reset signal.
+         */
+        uint32_t cam_reset:1;
+        /** cam_afifo_reset : WT; bitpos: [31]; default: 0;
+         *  Camera AFIFO reset signal.
+         */
+        uint32_t cam_afifo_reset:1;
+    };
+    uint32_t val;
+} lcdcam_cam_ctrl1_reg_t;
+
+/** Type of cam_rgb_yuv register
+ *  CAM YUV/RGB converter configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t cam_conv_8bits_data_inv:1;
+        /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+         *  trans_mode must be set to 1.
+         */
+        uint32_t cam_conv_yuv2yuv_mode:2;
+        /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+         *  mode of Data_in
+         */
+        uint32_t cam_conv_yuv_mode:2;
+        /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t cam_conv_protocol_mode:1;
+        /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_out_mode:1;
+        /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_in_mode:1;
+        /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t cam_conv_mode_8bits_on:1;
+        /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t cam_conv_trans_mode:1;
+        /** cam_conv_enable : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t cam_conv_enable:1;
+    };
+    uint32_t val;
+} lcdcam_cam_rgb_yuv_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of lc_dma_int_ena register
+ *  LCDCAM interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_ena:1;
+        /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_ena:1;
+        /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_ena:1;
+        /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_ena_reg_t;
+
+/** Type of lc_dma_int_raw register
+ *  LCDCAM interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_raw:1;
+        /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_raw:1;
+        /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_raw:1;
+        /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_raw_reg_t;
+
+/** Type of lc_dma_int_st register
+ *  LCDCAM interrupt status register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0;
+         *  The status bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_st:1;
+        /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_st:1;
+        /** cam_vsync_int_st : RO; bitpos: [2]; default: 0;
+         *  The status bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_st:1;
+        /** cam_hs_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for Camera transfer end interrupt.
+         */
+        uint32_t cam_hs_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_st_reg_t;
+
+/** Type of lc_dma_int_clr register
+ *  LCDCAM interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_clr:1;
+        /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_clr:1;
+        /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_clr:1;
+        /** cam_hs_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_clr_reg_t;
+
+
+/** Group: Version register */
+/** Type of lc_reg_date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** lc_date : R/W; bitpos: [27:0]; default: 36712592;
+         *  LCD_CAM version control register
+         */
+        uint32_t lc_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lcdcam_lc_reg_date_reg_t;
+
+
+typedef struct lcd_cam_dev_t {
+    volatile lcdcam_lcd_clock_reg_t lcd_clock;
+    volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
+    volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;
+    volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv;
+    volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv;
+    volatile lcdcam_lcd_user_reg_t lcd_user;
+    volatile lcdcam_lcd_misc_reg_t lcd_misc;
+    volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl;
+    volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1;
+    volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2;
+    volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val;
+    volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val;
+    volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1;
+    uint32_t reserved_034;
+    volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2;
+    uint32_t reserved_03c[10];
+    volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena;
+    volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw;
+    volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st;
+    volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr;
+    uint32_t reserved_074[34];
+    volatile lcdcam_lc_reg_date_reg_t lc_reg_date;
+} lcd_cam_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
+#endif
+
+extern lcd_cam_dev_t LCD_CAM;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h
new file mode 100644
index 0000000000..b10ff9f379
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h
@@ -0,0 +1,3116 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LEDC_CH0_CONF0_REG register
+ *  Configuration register 0 for channel 0
+ */
+#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0)
+/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 0 selected.
+ *  0: Select timer0
+ *  1: Select timer1
+ *  2: Select timer2
+ *  3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH0    0x00000003U
+#define LEDC_TIMER_SEL_CH0_M  (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S)
+#define LEDC_TIMER_SEL_CH0_V  0x00000003U
+#define LEDC_TIMER_SEL_CH0_S  0
+/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 0.
+ *  0: Signal output disable
+ *  1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH0    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH0_M  (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S)
+#define LEDC_SIG_OUT_EN_CH0_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH0_S  2
+/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 0 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH0 is 0.
+ *  0: Output level is low
+ *  1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH0    (BIT(3))
+#define LEDC_IDLE_LV_CH0_M  (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S)
+#define LEDC_IDLE_LV_CH0_V  0x00000001U
+#define LEDC_IDLE_LV_CH0_S  3
+/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0,
+ *  LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0,
+ *  LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel
+ *  0, and will be automatically cleared by hardware.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_PARA_UP_CH0    (BIT(4))
+#define LEDC_PARA_UP_CH0_M  (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S)
+#define LEDC_PARA_UP_CH0_V  0x00000001U
+#define LEDC_PARA_UP_CH0_S  4
+/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt
+ *  will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH0    0x000003FFU
+#define LEDC_OVF_NUM_CH0_M  (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S)
+#define LEDC_OVF_NUM_CH0_V  0x000003FFU
+#define LEDC_OVF_NUM_CH0_S  5
+/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH0    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH0_M  (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S)
+#define LEDC_OVF_CNT_EN_CH0_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH0_S  15
+/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 0.
+ *  0: Invalid. No effect
+ *  1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH0    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH0_M  (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S)
+#define LEDC_OVF_CNT_RESET_CH0_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH0_S  16
+
+/** LEDC_CH0_HPOINT_REG register
+ *  High point register for channel 0
+ */
+#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4)
+/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 0. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH0    0x000FFFFFU
+#define LEDC_HPOINT_CH0_M  (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S)
+#define LEDC_HPOINT_CH0_V  0x000FFFFFU
+#define LEDC_HPOINT_CH0_S  0
+
+/** LEDC_CH0_DUTY_REG register
+ *  Initial duty cycle register for channel 0
+ */
+#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8)
+/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 0.
+ */
+#define LEDC_DUTY_CH0    0x01FFFFFFU
+#define LEDC_DUTY_CH0_M  (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S)
+#define LEDC_DUTY_CH0_V  0x01FFFFFFU
+#define LEDC_DUTY_CH0_S  0
+
+/** LEDC_CH0_CONF1_REG register
+ *  Configuration register 1 for channel 0
+ */
+#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc)
+/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.
+ *  0: Not take effect
+ *  1: Take effect
+ */
+#define LEDC_DUTY_START_CH0    (BIT(31))
+#define LEDC_DUTY_START_CH0_M  (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S)
+#define LEDC_DUTY_START_CH0_V  0x00000001U
+#define LEDC_DUTY_START_CH0_S  31
+
+/** LEDC_CH0_DUTY_R_REG register
+ *  Current duty cycle register for channel 0
+ */
+#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10)
+/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 0.
+ */
+#define LEDC_DUTY_CH0_R    0x01FFFFFFU
+#define LEDC_DUTY_CH0_R_M  (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S)
+#define LEDC_DUTY_CH0_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH0_R_S  0
+
+/** LEDC_CH1_CONF0_REG register
+ *  Configuration register 0 for channel 1
+ */
+#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14)
+/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 1 selected.
+ *  0: Select timer0
+ *  1: Select timer1
+ *  2: Select timer2
+ *  3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH1    0x00000003U
+#define LEDC_TIMER_SEL_CH1_M  (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S)
+#define LEDC_TIMER_SEL_CH1_V  0x00000003U
+#define LEDC_TIMER_SEL_CH1_S  0
+/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 1.
+ *  0: Signal output disable
+ *  1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH1    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH1_M  (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S)
+#define LEDC_SIG_OUT_EN_CH1_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH1_S  2
+/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 1 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH1 is 0.
+ *  0: Output level is low
+ *  1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH1    (BIT(3))
+#define LEDC_IDLE_LV_CH1_M  (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S)
+#define LEDC_IDLE_LV_CH1_V  0x00000001U
+#define LEDC_IDLE_LV_CH1_S  3
+/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1,
+ *  LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1,
+ *  LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel
+ *  1, and will be automatically cleared by hardware.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_PARA_UP_CH1    (BIT(4))
+#define LEDC_PARA_UP_CH1_M  (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S)
+#define LEDC_PARA_UP_CH1_V  0x00000001U
+#define LEDC_PARA_UP_CH1_S  4
+/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt
+ *  will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH1    0x000003FFU
+#define LEDC_OVF_NUM_CH1_M  (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S)
+#define LEDC_OVF_NUM_CH1_V  0x000003FFU
+#define LEDC_OVF_NUM_CH1_S  5
+/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH1    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH1_M  (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S)
+#define LEDC_OVF_CNT_EN_CH1_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH1_S  15
+/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 1.
+ *  0: Invalid. No effect
+ *  1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH1    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH1_M  (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S)
+#define LEDC_OVF_CNT_RESET_CH1_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH1_S  16
+
+/** LEDC_CH1_HPOINT_REG register
+ *  High point register for channel 1
+ */
+#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18)
+/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 1. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH1    0x000FFFFFU
+#define LEDC_HPOINT_CH1_M  (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S)
+#define LEDC_HPOINT_CH1_V  0x000FFFFFU
+#define LEDC_HPOINT_CH1_S  0
+
+/** LEDC_CH1_DUTY_REG register
+ *  Initial duty cycle register for channel 1
+ */
+#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c)
+/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 1.
+ */
+#define LEDC_DUTY_CH1    0x01FFFFFFU
+#define LEDC_DUTY_CH1_M  (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S)
+#define LEDC_DUTY_CH1_V  0x01FFFFFFU
+#define LEDC_DUTY_CH1_S  0
+
+/** LEDC_CH1_CONF1_REG register
+ *  Configuration register 1 for channel 1
+ */
+#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20)
+/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.
+ *  0: Not take effect
+ *  1: Take effect
+ */
+#define LEDC_DUTY_START_CH1    (BIT(31))
+#define LEDC_DUTY_START_CH1_M  (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S)
+#define LEDC_DUTY_START_CH1_V  0x00000001U
+#define LEDC_DUTY_START_CH1_S  31
+
+/** LEDC_CH1_DUTY_R_REG register
+ *  Current duty cycle register for channel 1
+ */
+#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24)
+/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 1.
+ */
+#define LEDC_DUTY_CH1_R    0x01FFFFFFU
+#define LEDC_DUTY_CH1_R_M  (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S)
+#define LEDC_DUTY_CH1_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH1_R_S  0
+
+/** LEDC_CH2_CONF0_REG register
+ *  Configuration register 0 for channel 2
+ */
+#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28)
+/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 2 selected.
+ *  0: Select timer0
+ *  1: Select timer1
+ *  2: Select timer2
+ *  3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH2    0x00000003U
+#define LEDC_TIMER_SEL_CH2_M  (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S)
+#define LEDC_TIMER_SEL_CH2_V  0x00000003U
+#define LEDC_TIMER_SEL_CH2_S  0
+/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 2.
+ *  0: Signal output disable
+ *  1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH2    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH2_M  (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S)
+#define LEDC_SIG_OUT_EN_CH2_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH2_S  2
+/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 2 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH2 is 0.
+ *  0: Output level is low
+ *  1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH2    (BIT(3))
+#define LEDC_IDLE_LV_CH2_M  (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S)
+#define LEDC_IDLE_LV_CH2_V  0x00000001U
+#define LEDC_IDLE_LV_CH2_S  3
+/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2,
+ *  LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2,
+ *  LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel
+ *  2, and will be automatically cleared by hardware.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_PARA_UP_CH2    (BIT(4))
+#define LEDC_PARA_UP_CH2_M  (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S)
+#define LEDC_PARA_UP_CH2_V  0x00000001U
+#define LEDC_PARA_UP_CH2_S  4
+/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt
+ *  will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH2    0x000003FFU
+#define LEDC_OVF_NUM_CH2_M  (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S)
+#define LEDC_OVF_NUM_CH2_V  0x000003FFU
+#define LEDC_OVF_NUM_CH2_S  5
+/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH2    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH2_M  (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S)
+#define LEDC_OVF_CNT_EN_CH2_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH2_S  15
+/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 2.
+ *  0: Invalid. No effect
+ *  1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH2    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH2_M  (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S)
+#define LEDC_OVF_CNT_RESET_CH2_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH2_S  16
+
+/** LEDC_CH2_HPOINT_REG register
+ *  High point register for channel 2
+ */
+#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c)
+/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 2. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH2    0x000FFFFFU
+#define LEDC_HPOINT_CH2_M  (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S)
+#define LEDC_HPOINT_CH2_V  0x000FFFFFU
+#define LEDC_HPOINT_CH2_S  0
+
+/** LEDC_CH2_DUTY_REG register
+ *  Initial duty cycle register for channel 2
+ */
+#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30)
+/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 2.
+ */
+#define LEDC_DUTY_CH2    0x01FFFFFFU
+#define LEDC_DUTY_CH2_M  (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S)
+#define LEDC_DUTY_CH2_V  0x01FFFFFFU
+#define LEDC_DUTY_CH2_S  0
+
+/** LEDC_CH2_CONF1_REG register
+ *  Configuration register 1 for channel 2
+ */
+#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34)
+/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.
+ *  0: Not take effect
+ *  1: Take effect
+ */
+#define LEDC_DUTY_START_CH2    (BIT(31))
+#define LEDC_DUTY_START_CH2_M  (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S)
+#define LEDC_DUTY_START_CH2_V  0x00000001U
+#define LEDC_DUTY_START_CH2_S  31
+
+/** LEDC_CH2_DUTY_R_REG register
+ *  Current duty cycle register for channel 2
+ */
+#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38)
+/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 2.
+ */
+#define LEDC_DUTY_CH2_R    0x01FFFFFFU
+#define LEDC_DUTY_CH2_R_M  (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S)
+#define LEDC_DUTY_CH2_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH2_R_S  0
+
+/** LEDC_CH3_CONF0_REG register
+ *  Configuration register 0 for channel 3
+ */
+#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c)
+/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 3 selected.
+ *  0: Select timer0
+ *  1: Select timer1
+ *  2: Select timer2
+ *  3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH3    0x00000003U
+#define LEDC_TIMER_SEL_CH3_M  (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S)
+#define LEDC_TIMER_SEL_CH3_V  0x00000003U
+#define LEDC_TIMER_SEL_CH3_S  0
+/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 3.
+ *  0: Signal output disable
+ *  1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH3    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH3_M  (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S)
+#define LEDC_SIG_OUT_EN_CH3_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH3_S  2
+/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 3 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH3 is 0.
+ *  0: Output level is low
+ *  1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH3    (BIT(3))
+#define LEDC_IDLE_LV_CH3_M  (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S)
+#define LEDC_IDLE_LV_CH3_V  0x00000001U
+#define LEDC_IDLE_LV_CH3_S  3
+/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3,
+ *  LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3,
+ *  LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel
+ *  3, and will be automatically cleared by hardware.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_PARA_UP_CH3    (BIT(4))
+#define LEDC_PARA_UP_CH3_M  (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S)
+#define LEDC_PARA_UP_CH3_V  0x00000001U
+#define LEDC_PARA_UP_CH3_S  4
+/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt
+ *  will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH3    0x000003FFU
+#define LEDC_OVF_NUM_CH3_M  (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S)
+#define LEDC_OVF_NUM_CH3_V  0x000003FFU
+#define LEDC_OVF_NUM_CH3_S  5
+/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH3    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH3_M  (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S)
+#define LEDC_OVF_CNT_EN_CH3_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH3_S  15
+/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 3.
+ *  0: Invalid. No effect
+ *  1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH3    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH3_M  (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S)
+#define LEDC_OVF_CNT_RESET_CH3_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH3_S  16
+
+/** LEDC_CH3_HPOINT_REG register
+ *  High point register for channel 3
+ */
+#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40)
+/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 3. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH3    0x000FFFFFU
+#define LEDC_HPOINT_CH3_M  (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S)
+#define LEDC_HPOINT_CH3_V  0x000FFFFFU
+#define LEDC_HPOINT_CH3_S  0
+
+/** LEDC_CH3_DUTY_REG register
+ *  Initial duty cycle register for channel 3
+ */
+#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44)
+/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 3.
+ */
+#define LEDC_DUTY_CH3    0x01FFFFFFU
+#define LEDC_DUTY_CH3_M  (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S)
+#define LEDC_DUTY_CH3_V  0x01FFFFFFU
+#define LEDC_DUTY_CH3_S  0
+
+/** LEDC_CH3_CONF1_REG register
+ *  Configuration register 1 for channel 3
+ */
+#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48)
+/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.
+ *  0: Not take effect
+ *  1: Take effect
+ */
+#define LEDC_DUTY_START_CH3    (BIT(31))
+#define LEDC_DUTY_START_CH3_M  (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S)
+#define LEDC_DUTY_START_CH3_V  0x00000001U
+#define LEDC_DUTY_START_CH3_S  31
+
+/** LEDC_CH3_DUTY_R_REG register
+ *  Current duty cycle register for channel 3
+ */
+#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c)
+/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 3.
+ */
+#define LEDC_DUTY_CH3_R    0x01FFFFFFU
+#define LEDC_DUTY_CH3_R_M  (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S)
+#define LEDC_DUTY_CH3_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH3_R_S  0
+
+/** LEDC_CH4_CONF0_REG register
+ *  Configuration register 0 for channel 4
+ */
+#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50)
+/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 4 selected.
+ *  0: Select timer0
+ *  1: Select timer1
+ *  2: Select timer2
+ *  3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH4    0x00000003U
+#define LEDC_TIMER_SEL_CH4_M  (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S)
+#define LEDC_TIMER_SEL_CH4_V  0x00000003U
+#define LEDC_TIMER_SEL_CH4_S  0
+/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 4.
+ *  0: Signal output disable
+ *  1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH4    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH4_M  (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S)
+#define LEDC_SIG_OUT_EN_CH4_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH4_S  2
+/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 4 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH4 is 0.
+ *  0: Output level is low
+ *  1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH4    (BIT(3))
+#define LEDC_IDLE_LV_CH4_M  (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S)
+#define LEDC_IDLE_LV_CH4_V  0x00000001U
+#define LEDC_IDLE_LV_CH4_S  3
+/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4,
+ *  LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4,
+ *  LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel
+ *  4, and will be automatically cleared by hardware.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_PARA_UP_CH4    (BIT(4))
+#define LEDC_PARA_UP_CH4_M  (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S)
+#define LEDC_PARA_UP_CH4_V  0x00000001U
+#define LEDC_PARA_UP_CH4_S  4
+/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt
+ *  will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH4    0x000003FFU
+#define LEDC_OVF_NUM_CH4_M  (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S)
+#define LEDC_OVF_NUM_CH4_V  0x000003FFU
+#define LEDC_OVF_NUM_CH4_S  5
+/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 4.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH4    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH4_M  (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S)
+#define LEDC_OVF_CNT_EN_CH4_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH4_S  15
+/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 4.
+ *  0: Invalid. No effect
+ *  1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH4    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH4_M  (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S)
+#define LEDC_OVF_CNT_RESET_CH4_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH4_S  16
+
+/** LEDC_CH4_HPOINT_REG register
+ *  High point register for channel 4
+ */
+#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54)
+/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 4. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH4    0x000FFFFFU
+#define LEDC_HPOINT_CH4_M  (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S)
+#define LEDC_HPOINT_CH4_V  0x000FFFFFU
+#define LEDC_HPOINT_CH4_S  0
+
+/** LEDC_CH4_DUTY_REG register
+ *  Initial duty cycle register for channel 4
+ */
+#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58)
+/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 4.
+ */
+#define LEDC_DUTY_CH4    0x01FFFFFFU
+#define LEDC_DUTY_CH4_M  (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S)
+#define LEDC_DUTY_CH4_V  0x01FFFFFFU
+#define LEDC_DUTY_CH4_S  0
+
+/** LEDC_CH4_CONF1_REG register
+ *  Configuration register 1 for channel 4
+ */
+#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c)
+/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.
+ *  0: Not take effect
+ *  1: Take effect
+ */
+#define LEDC_DUTY_START_CH4    (BIT(31))
+#define LEDC_DUTY_START_CH4_M  (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S)
+#define LEDC_DUTY_START_CH4_V  0x00000001U
+#define LEDC_DUTY_START_CH4_S  31
+
+/** LEDC_CH4_DUTY_R_REG register
+ *  Current duty cycle register for channel 4
+ */
+#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60)
+/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 4.
+ */
+#define LEDC_DUTY_CH4_R    0x01FFFFFFU
+#define LEDC_DUTY_CH4_R_M  (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S)
+#define LEDC_DUTY_CH4_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH4_R_S  0
+
+/** LEDC_CH5_CONF0_REG register
+ *  Configuration register 0 for channel 5
+ */
+#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64)
+/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 5 selected.
+ *  0: Select timer0
+ *  1: Select timer1
+ *  2: Select timer2
+ *  3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH5    0x00000003U
+#define LEDC_TIMER_SEL_CH5_M  (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S)
+#define LEDC_TIMER_SEL_CH5_V  0x00000003U
+#define LEDC_TIMER_SEL_CH5_S  0
+/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 5.
+ *  0: Signal output disable
+ *  1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH5    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH5_M  (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S)
+#define LEDC_SIG_OUT_EN_CH5_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH5_S  2
+/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 5 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH5 is 0.
+ *  0: Output level is low
+ *  1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH5    (BIT(3))
+#define LEDC_IDLE_LV_CH5_M  (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S)
+#define LEDC_IDLE_LV_CH5_V  0x00000001U
+#define LEDC_IDLE_LV_CH5_S  3
+/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5,
+ *  LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5,
+ *  LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel
+ *  5, and will be automatically cleared by hardware.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_PARA_UP_CH5    (BIT(4))
+#define LEDC_PARA_UP_CH5_M  (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S)
+#define LEDC_PARA_UP_CH5_V  0x00000001U
+#define LEDC_PARA_UP_CH5_S  4
+/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt
+ *  will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH5    0x000003FFU
+#define LEDC_OVF_NUM_CH5_M  (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S)
+#define LEDC_OVF_NUM_CH5_V  0x000003FFU
+#define LEDC_OVF_NUM_CH5_S  5
+/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 5.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH5    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH5_M  (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S)
+#define LEDC_OVF_CNT_EN_CH5_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH5_S  15
+/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 5.
+ *  0: Invalid. No effect
+ *  1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH5    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH5_M  (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S)
+#define LEDC_OVF_CNT_RESET_CH5_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH5_S  16
+
+/** LEDC_CH5_HPOINT_REG register
+ *  High point register for channel 5
+ */
+#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68)
+/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 5. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH5    0x000FFFFFU
+#define LEDC_HPOINT_CH5_M  (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S)
+#define LEDC_HPOINT_CH5_V  0x000FFFFFU
+#define LEDC_HPOINT_CH5_S  0
+
+/** LEDC_CH5_DUTY_REG register
+ *  Initial duty cycle register for channel 5
+ */
+#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c)
+/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 5.
+ */
+#define LEDC_DUTY_CH5    0x01FFFFFFU
+#define LEDC_DUTY_CH5_M  (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S)
+#define LEDC_DUTY_CH5_V  0x01FFFFFFU
+#define LEDC_DUTY_CH5_S  0
+
+/** LEDC_CH5_CONF1_REG register
+ *  Configuration register 1 for channel 5
+ */
+#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70)
+/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.
+ *  0: Not take effect
+ *  1: Take effect
+ */
+#define LEDC_DUTY_START_CH5    (BIT(31))
+#define LEDC_DUTY_START_CH5_M  (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S)
+#define LEDC_DUTY_START_CH5_V  0x00000001U
+#define LEDC_DUTY_START_CH5_S  31
+
+/** LEDC_CH5_DUTY_R_REG register
+ *  Current duty cycle register for channel 5
+ */
+#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74)
+/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 5.
+ */
+#define LEDC_DUTY_CH5_R    0x01FFFFFFU
+#define LEDC_DUTY_CH5_R_M  (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S)
+#define LEDC_DUTY_CH5_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH5_R_S  0
+
+/** LEDC_CH6_CONF0_REG register
+ *  Configuration register 0 for channel 6
+ */
+#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78)
+/** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 6 selected.
+ *  0: Select timer0
+ *  1: Select timer1
+ *  2: Select timer2
+ *  3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH6    0x00000003U
+#define LEDC_TIMER_SEL_CH6_M  (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S)
+#define LEDC_TIMER_SEL_CH6_V  0x00000003U
+#define LEDC_TIMER_SEL_CH6_S  0
+/** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 6.
+ *  0: Signal output disable
+ *  1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH6    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH6_M  (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S)
+#define LEDC_SIG_OUT_EN_CH6_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH6_S  2
+/** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 6 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH6 is 0.
+ *  0: Output level is low
+ *  1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH6    (BIT(3))
+#define LEDC_IDLE_LV_CH6_M  (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S)
+#define LEDC_IDLE_LV_CH6_V  0x00000001U
+#define LEDC_IDLE_LV_CH6_S  3
+/** LEDC_PARA_UP_CH6 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6,
+ *  LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6,
+ *  LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel
+ *  6, and will be automatically cleared by hardware.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_PARA_UP_CH6    (BIT(4))
+#define LEDC_PARA_UP_CH6_M  (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S)
+#define LEDC_PARA_UP_CH6_V  0x00000001U
+#define LEDC_PARA_UP_CH6_S  4
+/** LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH6_INT interrupt
+ *  will be triggered when channel 6 overflows for (LEDC_OVF_NUM_CH6 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH6    0x000003FFU
+#define LEDC_OVF_NUM_CH6_M  (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S)
+#define LEDC_OVF_NUM_CH6_V  0x000003FFU
+#define LEDC_OVF_NUM_CH6_S  5
+/** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 6.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH6    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH6_M  (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S)
+#define LEDC_OVF_CNT_EN_CH6_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH6_S  15
+/** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 6.
+ *  0: Invalid. No effect
+ *  1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH6    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH6_M  (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S)
+#define LEDC_OVF_CNT_RESET_CH6_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH6_S  16
+
+/** LEDC_CH6_HPOINT_REG register
+ *  High point register for channel 6
+ */
+#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c)
+/** LEDC_HPOINT_CH6 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 6. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH6    0x000FFFFFU
+#define LEDC_HPOINT_CH6_M  (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S)
+#define LEDC_HPOINT_CH6_V  0x000FFFFFU
+#define LEDC_HPOINT_CH6_S  0
+
+/** LEDC_CH6_DUTY_REG register
+ *  Initial duty cycle register for channel 6
+ */
+#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80)
+/** LEDC_DUTY_CH6 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 6.
+ */
+#define LEDC_DUTY_CH6    0x01FFFFFFU
+#define LEDC_DUTY_CH6_M  (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S)
+#define LEDC_DUTY_CH6_V  0x01FFFFFFU
+#define LEDC_DUTY_CH6_S  0
+
+/** LEDC_CH6_CONF1_REG register
+ *  Configuration register 1 for channel 6
+ */
+#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84)
+/** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.
+ *  0: Not take effect
+ *  1: Take effect
+ */
+#define LEDC_DUTY_START_CH6    (BIT(31))
+#define LEDC_DUTY_START_CH6_M  (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S)
+#define LEDC_DUTY_START_CH6_V  0x00000001U
+#define LEDC_DUTY_START_CH6_S  31
+
+/** LEDC_CH6_DUTY_R_REG register
+ *  Current duty cycle register for channel 6
+ */
+#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88)
+/** LEDC_DUTY_CH6_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 6.
+ */
+#define LEDC_DUTY_CH6_R    0x01FFFFFFU
+#define LEDC_DUTY_CH6_R_M  (LEDC_DUTY_CH6_R_V << LEDC_DUTY_CH6_R_S)
+#define LEDC_DUTY_CH6_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH6_R_S  0
+
+/** LEDC_CH7_CONF0_REG register
+ *  Configuration register 0 for channel 7
+ */
+#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c)
+/** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 7 selected.
+ *  0: Select timer0
+ *  1: Select timer1
+ *  2: Select timer2
+ *  3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH7    0x00000003U
+#define LEDC_TIMER_SEL_CH7_M  (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S)
+#define LEDC_TIMER_SEL_CH7_V  0x00000003U
+#define LEDC_TIMER_SEL_CH7_S  0
+/** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 7.
+ *  0: Signal output disable
+ *  1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH7    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH7_M  (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S)
+#define LEDC_SIG_OUT_EN_CH7_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH7_S  2
+/** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 7 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH7 is 0.
+ *  0: Output level is low
+ *  1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH7    (BIT(3))
+#define LEDC_IDLE_LV_CH7_M  (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S)
+#define LEDC_IDLE_LV_CH7_V  0x00000001U
+#define LEDC_IDLE_LV_CH7_S  3
+/** LEDC_PARA_UP_CH7 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7,
+ *  LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7,
+ *  LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel
+ *  7, and will be automatically cleared by hardware.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_PARA_UP_CH7    (BIT(4))
+#define LEDC_PARA_UP_CH7_M  (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S)
+#define LEDC_PARA_UP_CH7_V  0x00000001U
+#define LEDC_PARA_UP_CH7_S  4
+/** LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH7_INT interrupt
+ *  will be triggered when channel 7 overflows for (LEDC_OVF_NUM_CH7 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH7    0x000003FFU
+#define LEDC_OVF_NUM_CH7_M  (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S)
+#define LEDC_OVF_NUM_CH7_V  0x000003FFU
+#define LEDC_OVF_NUM_CH7_S  5
+/** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 7.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH7    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH7_M  (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S)
+#define LEDC_OVF_CNT_EN_CH7_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH7_S  15
+/** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 7.
+ *  0: Invalid. No effect
+ *  1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH7    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH7_M  (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S)
+#define LEDC_OVF_CNT_RESET_CH7_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH7_S  16
+
+/** LEDC_CH7_HPOINT_REG register
+ *  High point register for channel 7
+ */
+#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90)
+/** LEDC_HPOINT_CH7 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 7. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH7    0x000FFFFFU
+#define LEDC_HPOINT_CH7_M  (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S)
+#define LEDC_HPOINT_CH7_V  0x000FFFFFU
+#define LEDC_HPOINT_CH7_S  0
+
+/** LEDC_CH7_DUTY_REG register
+ *  Initial duty cycle register for channel 7
+ */
+#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94)
+/** LEDC_DUTY_CH7 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 7.
+ */
+#define LEDC_DUTY_CH7    0x01FFFFFFU
+#define LEDC_DUTY_CH7_M  (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S)
+#define LEDC_DUTY_CH7_V  0x01FFFFFFU
+#define LEDC_DUTY_CH7_S  0
+
+/** LEDC_CH7_CONF1_REG register
+ *  Configuration register 1 for channel 7
+ */
+#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98)
+/** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.
+ *  0: Not take effect
+ *  1: Take effect
+ */
+#define LEDC_DUTY_START_CH7    (BIT(31))
+#define LEDC_DUTY_START_CH7_M  (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S)
+#define LEDC_DUTY_START_CH7_V  0x00000001U
+#define LEDC_DUTY_START_CH7_S  31
+
+/** LEDC_CH7_DUTY_R_REG register
+ *  Current duty cycle register for channel 7
+ */
+#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c)
+/** LEDC_DUTY_CH7_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 7.
+ */
+#define LEDC_DUTY_CH7_R    0x01FFFFFFU
+#define LEDC_DUTY_CH7_R_M  (LEDC_DUTY_CH7_R_V << LEDC_DUTY_CH7_R_S)
+#define LEDC_DUTY_CH7_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH7_R_S  0
+
+/** LEDC_TIMER0_CONF_REG register
+ *  Timer 0 configuration register
+ */
+#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0)
+/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the range of the counter in timer 0.
+ */
+#define LEDC_TIMER0_DUTY_RES    0x0000001FU
+#define LEDC_TIMER0_DUTY_RES_M  (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S)
+#define LEDC_TIMER0_DUTY_RES_V  0x0000001FU
+#define LEDC_TIMER0_DUTY_RES_S  0
+/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0;
+ *  Configures the divisor for the divider in timer 0.The least significant eight bits
+ *  represent the fractional part.
+ */
+#define LEDC_CLK_DIV_TIMER0    0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER0_M  (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S)
+#define LEDC_CLK_DIV_TIMER0_V  0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER0_S  5
+/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to pause the counter in timer 0.
+ *  0: Normal
+ *  1: Pause
+ */
+#define LEDC_TIMER0_PAUSE    (BIT(23))
+#define LEDC_TIMER0_PAUSE_M  (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S)
+#define LEDC_TIMER0_PAUSE_V  0x00000001U
+#define LEDC_TIMER0_PAUSE_S  23
+/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1;
+ *  Configures whether or not to reset timer 0. The counter will show 0 after reset.
+ *  0: Not reset
+ *  1: Reset
+ */
+#define LEDC_TIMER0_RST    (BIT(24))
+#define LEDC_TIMER0_RST_M  (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S)
+#define LEDC_TIMER0_RST_V  0x00000001U
+#define LEDC_TIMER0_RST_S  24
+/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_TIMER0_PARA_UP    (BIT(26))
+#define LEDC_TIMER0_PARA_UP_M  (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S)
+#define LEDC_TIMER0_PARA_UP_V  0x00000001U
+#define LEDC_TIMER0_PARA_UP_S  26
+
+/** LEDC_TIMER0_VALUE_REG register
+ *  Timer 0 current counter value register
+ */
+#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4)
+/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0;
+ *  Represents the current counter value of timer 0.
+ */
+#define LEDC_TIMER0_CNT    0x000FFFFFU
+#define LEDC_TIMER0_CNT_M  (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S)
+#define LEDC_TIMER0_CNT_V  0x000FFFFFU
+#define LEDC_TIMER0_CNT_S  0
+
+/** LEDC_TIMER1_CONF_REG register
+ *  Timer 1 configuration register
+ */
+#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8)
+/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the range of the counter in timer 1.
+ */
+#define LEDC_TIMER1_DUTY_RES    0x0000001FU
+#define LEDC_TIMER1_DUTY_RES_M  (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S)
+#define LEDC_TIMER1_DUTY_RES_V  0x0000001FU
+#define LEDC_TIMER1_DUTY_RES_S  0
+/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0;
+ *  Configures the divisor for the divider in timer 1.The least significant eight bits
+ *  represent the fractional part.
+ */
+#define LEDC_CLK_DIV_TIMER1    0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER1_M  (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S)
+#define LEDC_CLK_DIV_TIMER1_V  0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER1_S  5
+/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to pause the counter in timer 1.
+ *  0: Normal
+ *  1: Pause
+ */
+#define LEDC_TIMER1_PAUSE    (BIT(23))
+#define LEDC_TIMER1_PAUSE_M  (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S)
+#define LEDC_TIMER1_PAUSE_V  0x00000001U
+#define LEDC_TIMER1_PAUSE_S  23
+/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1;
+ *  Configures whether or not to reset timer 1. The counter will show 0 after reset.
+ *  0: Not reset
+ *  1: Reset
+ */
+#define LEDC_TIMER1_RST    (BIT(24))
+#define LEDC_TIMER1_RST_M  (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S)
+#define LEDC_TIMER1_RST_V  0x00000001U
+#define LEDC_TIMER1_RST_S  24
+/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_TIMER1_PARA_UP    (BIT(26))
+#define LEDC_TIMER1_PARA_UP_M  (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S)
+#define LEDC_TIMER1_PARA_UP_V  0x00000001U
+#define LEDC_TIMER1_PARA_UP_S  26
+
+/** LEDC_TIMER1_VALUE_REG register
+ *  Timer 1 current counter value register
+ */
+#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac)
+/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0;
+ *  Represents the current counter value of timer 1.
+ */
+#define LEDC_TIMER1_CNT    0x000FFFFFU
+#define LEDC_TIMER1_CNT_M  (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S)
+#define LEDC_TIMER1_CNT_V  0x000FFFFFU
+#define LEDC_TIMER1_CNT_S  0
+
+/** LEDC_TIMER2_CONF_REG register
+ *  Timer 2 configuration register
+ */
+#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0)
+/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the range of the counter in timer 2.
+ */
+#define LEDC_TIMER2_DUTY_RES    0x0000001FU
+#define LEDC_TIMER2_DUTY_RES_M  (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S)
+#define LEDC_TIMER2_DUTY_RES_V  0x0000001FU
+#define LEDC_TIMER2_DUTY_RES_S  0
+/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0;
+ *  Configures the divisor for the divider in timer 2.The least significant eight bits
+ *  represent the fractional part.
+ */
+#define LEDC_CLK_DIV_TIMER2    0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER2_M  (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S)
+#define LEDC_CLK_DIV_TIMER2_V  0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER2_S  5
+/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to pause the counter in timer 2.
+ *  0: Normal
+ *  1: Pause
+ */
+#define LEDC_TIMER2_PAUSE    (BIT(23))
+#define LEDC_TIMER2_PAUSE_M  (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S)
+#define LEDC_TIMER2_PAUSE_V  0x00000001U
+#define LEDC_TIMER2_PAUSE_S  23
+/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1;
+ *  Configures whether or not to reset timer 2. The counter will show 0 after reset.
+ *  0: Not reset
+ *  1: Reset
+ */
+#define LEDC_TIMER2_RST    (BIT(24))
+#define LEDC_TIMER2_RST_M  (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S)
+#define LEDC_TIMER2_RST_V  0x00000001U
+#define LEDC_TIMER2_RST_S  24
+/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_TIMER2_PARA_UP    (BIT(26))
+#define LEDC_TIMER2_PARA_UP_M  (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S)
+#define LEDC_TIMER2_PARA_UP_V  0x00000001U
+#define LEDC_TIMER2_PARA_UP_S  26
+
+/** LEDC_TIMER2_VALUE_REG register
+ *  Timer 2 current counter value register
+ */
+#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4)
+/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0;
+ *  Represents the current counter value of timer 2.
+ */
+#define LEDC_TIMER2_CNT    0x000FFFFFU
+#define LEDC_TIMER2_CNT_M  (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S)
+#define LEDC_TIMER2_CNT_V  0x000FFFFFU
+#define LEDC_TIMER2_CNT_S  0
+
+/** LEDC_TIMER3_CONF_REG register
+ *  Timer 3 configuration register
+ */
+#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8)
+/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the range of the counter in timer 3.
+ */
+#define LEDC_TIMER3_DUTY_RES    0x0000001FU
+#define LEDC_TIMER3_DUTY_RES_M  (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S)
+#define LEDC_TIMER3_DUTY_RES_V  0x0000001FU
+#define LEDC_TIMER3_DUTY_RES_S  0
+/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0;
+ *  Configures the divisor for the divider in timer 3.The least significant eight bits
+ *  represent the fractional part.
+ */
+#define LEDC_CLK_DIV_TIMER3    0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER3_M  (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S)
+#define LEDC_CLK_DIV_TIMER3_V  0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER3_S  5
+/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to pause the counter in timer 3.
+ *  0: Normal
+ *  1: Pause
+ */
+#define LEDC_TIMER3_PAUSE    (BIT(23))
+#define LEDC_TIMER3_PAUSE_M  (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S)
+#define LEDC_TIMER3_PAUSE_V  0x00000001U
+#define LEDC_TIMER3_PAUSE_S  23
+/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1;
+ *  Configures whether or not to reset timer 3. The counter will show 0 after reset.
+ *  0: Not reset
+ *  1: Reset
+ */
+#define LEDC_TIMER3_RST    (BIT(24))
+#define LEDC_TIMER3_RST_M  (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S)
+#define LEDC_TIMER3_RST_V  0x00000001U
+#define LEDC_TIMER3_RST_S  24
+/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES.
+ *  0: Invalid. No effect
+ *  1: Update
+ */
+#define LEDC_TIMER3_PARA_UP    (BIT(26))
+#define LEDC_TIMER3_PARA_UP_M  (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S)
+#define LEDC_TIMER3_PARA_UP_V  0x00000001U
+#define LEDC_TIMER3_PARA_UP_S  26
+
+/** LEDC_TIMER3_VALUE_REG register
+ *  Timer 3 current counter value register
+ */
+#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc)
+/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0;
+ *  Represents the current counter value of timer 3.
+ */
+#define LEDC_TIMER3_CNT    0x000FFFFFU
+#define LEDC_TIMER3_CNT_M  (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S)
+#define LEDC_TIMER3_CNT_V  0x000FFFFFU
+#define LEDC_TIMER3_CNT_S  0
+
+/** LEDC_INT_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0)
+/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the
+ *  timer0 has reached its maximum counter value.
+ */
+#define LEDC_TIMER0_OVF_INT_RAW    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_RAW_M  (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S)
+#define LEDC_TIMER0_OVF_INT_RAW_V  0x00000001U
+#define LEDC_TIMER0_OVF_INT_RAW_S  0
+/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the
+ *  timer1 has reached its maximum counter value.
+ */
+#define LEDC_TIMER1_OVF_INT_RAW    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_RAW_M  (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S)
+#define LEDC_TIMER1_OVF_INT_RAW_V  0x00000001U
+#define LEDC_TIMER1_OVF_INT_RAW_S  1
+/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the
+ *  timer2 has reached its maximum counter value.
+ */
+#define LEDC_TIMER2_OVF_INT_RAW    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_RAW_M  (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S)
+#define LEDC_TIMER2_OVF_INT_RAW_V  0x00000001U
+#define LEDC_TIMER2_OVF_INT_RAW_S  2
+/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the
+ *  timer3 has reached its maximum counter value.
+ */
+#define LEDC_TIMER3_OVF_INT_RAW    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_RAW_M  (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S)
+#define LEDC_TIMER3_OVF_INT_RAW_V  0x00000001U
+#define LEDC_TIMER3_OVF_INT_RAW_S  3
+/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S  4
+/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S  5
+/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S  6
+/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S  7
+/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S  8
+/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S  9
+/** LEDC_DUTY_CHNG_END_CH6_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW    (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S  10
+/** LEDC_DUTY_CHNG_END_CH7_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW    (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S  11
+/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.
+ */
+#define LEDC_OVF_CNT_CH0_INT_RAW    (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_RAW_M  (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S)
+#define LEDC_OVF_CNT_CH0_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH0_INT_RAW_S  12
+/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.
+ */
+#define LEDC_OVF_CNT_CH1_INT_RAW    (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_RAW_M  (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S)
+#define LEDC_OVF_CNT_CH1_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH1_INT_RAW_S  13
+/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.
+ */
+#define LEDC_OVF_CNT_CH2_INT_RAW    (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_RAW_M  (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S)
+#define LEDC_OVF_CNT_CH2_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH2_INT_RAW_S  14
+/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.
+ */
+#define LEDC_OVF_CNT_CH3_INT_RAW    (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_RAW_M  (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S)
+#define LEDC_OVF_CNT_CH3_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH3_INT_RAW_S  15
+/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.
+ */
+#define LEDC_OVF_CNT_CH4_INT_RAW    (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_RAW_M  (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S)
+#define LEDC_OVF_CNT_CH4_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH4_INT_RAW_S  16
+/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.
+ */
+#define LEDC_OVF_CNT_CH5_INT_RAW    (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_RAW_M  (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S)
+#define LEDC_OVF_CNT_CH5_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH5_INT_RAW_S  17
+/** LEDC_OVF_CNT_CH6_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6.
+ */
+#define LEDC_OVF_CNT_CH6_INT_RAW    (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_RAW_M  (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S)
+#define LEDC_OVF_CNT_CH6_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH6_INT_RAW_S  18
+/** LEDC_OVF_CNT_CH7_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7.
+ */
+#define LEDC_OVF_CNT_CH7_INT_RAW    (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_RAW_M  (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S)
+#define LEDC_OVF_CNT_CH7_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH7_INT_RAW_S  19
+
+/** LEDC_INT_ST_REG register
+ *  Interrupt masked status register
+ */
+#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4)
+/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only
+ *  when LEDC_TIMER0_OVF_INT_ENA is set to 1.
+ */
+#define LEDC_TIMER0_OVF_INT_ST    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_ST_M  (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S)
+#define LEDC_TIMER0_OVF_INT_ST_V  0x00000001U
+#define LEDC_TIMER0_OVF_INT_ST_S  0
+/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only
+ *  when LEDC_TIMER1_OVF_INT_ENA is set to 1.
+ */
+#define LEDC_TIMER1_OVF_INT_ST    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_ST_M  (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S)
+#define LEDC_TIMER1_OVF_INT_ST_V  0x00000001U
+#define LEDC_TIMER1_OVF_INT_ST_S  1
+/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only
+ *  when LEDC_TIMER2_OVF_INT_ENA is set to 1.
+ */
+#define LEDC_TIMER2_OVF_INT_ST    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_ST_M  (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S)
+#define LEDC_TIMER2_OVF_INT_ST_V  0x00000001U
+#define LEDC_TIMER2_OVF_INT_ST_S  2
+/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only
+ *  when LEDC_TIMER3_OVF_INT_ENA is set to 1.
+ */
+#define LEDC_TIMER3_OVF_INT_ST    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_ST_M  (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S)
+#define LEDC_TIMER3_OVF_INT_ST_V  0x00000001U
+#define LEDC_TIMER3_OVF_INT_ST_S  3
+/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M  (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S  4
+/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M  (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S  5
+/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M  (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S  6
+/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M  (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S  7
+/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M  (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S  8
+/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M  (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S  9
+/** LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST    (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M  (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S  10
+/** LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST    (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M  (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S  11
+/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only
+ *  when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH0_INT_ST    (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_ST_M  (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S)
+#define LEDC_OVF_CNT_CH0_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH0_INT_ST_S  12
+/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only
+ *  when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH1_INT_ST    (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_ST_M  (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S)
+#define LEDC_OVF_CNT_CH1_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH1_INT_ST_S  13
+/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only
+ *  when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH2_INT_ST    (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_ST_M  (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S)
+#define LEDC_OVF_CNT_CH2_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH2_INT_ST_S  14
+/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only
+ *  when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH3_INT_ST    (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_ST_M  (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S)
+#define LEDC_OVF_CNT_CH3_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH3_INT_ST_S  15
+/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only
+ *  when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH4_INT_ST    (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_ST_M  (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S)
+#define LEDC_OVF_CNT_CH4_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH4_INT_ST_S  16
+/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only
+ *  when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH5_INT_ST    (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_ST_M  (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S)
+#define LEDC_OVF_CNT_CH5_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH5_INT_ST_S  17
+/** LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only
+ *  when LEDC_OVF_CNT_CH6_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH6_INT_ST    (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_ST_M  (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S)
+#define LEDC_OVF_CNT_CH6_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH6_INT_ST_S  18
+/** LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only
+ *  when LEDC_OVF_CNT_CH7_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH7_INT_ST    (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_ST_M  (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S)
+#define LEDC_OVF_CNT_CH7_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH7_INT_ST_S  19
+
+/** LEDC_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8)
+/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT.
+ */
+#define LEDC_TIMER0_OVF_INT_ENA    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_ENA_M  (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S)
+#define LEDC_TIMER0_OVF_INT_ENA_V  0x00000001U
+#define LEDC_TIMER0_OVF_INT_ENA_S  0
+/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT.
+ */
+#define LEDC_TIMER1_OVF_INT_ENA    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_ENA_M  (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S)
+#define LEDC_TIMER1_OVF_INT_ENA_V  0x00000001U
+#define LEDC_TIMER1_OVF_INT_ENA_S  1
+/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT.
+ */
+#define LEDC_TIMER2_OVF_INT_ENA    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_ENA_M  (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S)
+#define LEDC_TIMER2_OVF_INT_ENA_V  0x00000001U
+#define LEDC_TIMER2_OVF_INT_ENA_S  2
+/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT.
+ */
+#define LEDC_TIMER3_OVF_INT_ENA    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_ENA_M  (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S)
+#define LEDC_TIMER3_OVF_INT_ENA_V  0x00000001U
+#define LEDC_TIMER3_OVF_INT_ENA_S  3
+/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S  4
+/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S  5
+/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S  6
+/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S  7
+/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S  8
+/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S  9
+/** LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA    (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S  10
+/** LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA    (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S  11
+/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT.
+ */
+#define LEDC_OVF_CNT_CH0_INT_ENA    (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_ENA_M  (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S)
+#define LEDC_OVF_CNT_CH0_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH0_INT_ENA_S  12
+/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT.
+ */
+#define LEDC_OVF_CNT_CH1_INT_ENA    (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_ENA_M  (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S)
+#define LEDC_OVF_CNT_CH1_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH1_INT_ENA_S  13
+/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT.
+ */
+#define LEDC_OVF_CNT_CH2_INT_ENA    (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_ENA_M  (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S)
+#define LEDC_OVF_CNT_CH2_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH2_INT_ENA_S  14
+/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT.
+ */
+#define LEDC_OVF_CNT_CH3_INT_ENA    (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_ENA_M  (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S)
+#define LEDC_OVF_CNT_CH3_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH3_INT_ENA_S  15
+/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT.
+ */
+#define LEDC_OVF_CNT_CH4_INT_ENA    (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_ENA_M  (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S)
+#define LEDC_OVF_CNT_CH4_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH4_INT_ENA_S  16
+/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT.
+ */
+#define LEDC_OVF_CNT_CH5_INT_ENA    (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_ENA_M  (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S)
+#define LEDC_OVF_CNT_CH5_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH5_INT_ENA_S  17
+/** LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT.
+ */
+#define LEDC_OVF_CNT_CH6_INT_ENA    (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_ENA_M  (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S)
+#define LEDC_OVF_CNT_CH6_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH6_INT_ENA_S  18
+/** LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT.
+ */
+#define LEDC_OVF_CNT_CH7_INT_ENA    (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_ENA_M  (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S)
+#define LEDC_OVF_CNT_CH7_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH7_INT_ENA_S  19
+
+/** LEDC_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc)
+/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT.
+ */
+#define LEDC_TIMER0_OVF_INT_CLR    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_CLR_M  (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S)
+#define LEDC_TIMER0_OVF_INT_CLR_V  0x00000001U
+#define LEDC_TIMER0_OVF_INT_CLR_S  0
+/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT.
+ */
+#define LEDC_TIMER1_OVF_INT_CLR    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_CLR_M  (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S)
+#define LEDC_TIMER1_OVF_INT_CLR_V  0x00000001U
+#define LEDC_TIMER1_OVF_INT_CLR_S  1
+/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT.
+ */
+#define LEDC_TIMER2_OVF_INT_CLR    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_CLR_M  (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S)
+#define LEDC_TIMER2_OVF_INT_CLR_V  0x00000001U
+#define LEDC_TIMER2_OVF_INT_CLR_S  2
+/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT.
+ */
+#define LEDC_TIMER3_OVF_INT_CLR    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_CLR_M  (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S)
+#define LEDC_TIMER3_OVF_INT_CLR_V  0x00000001U
+#define LEDC_TIMER3_OVF_INT_CLR_S  3
+/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S  4
+/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S  5
+/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S  6
+/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S  7
+/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S  8
+/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S  9
+/** LEDC_DUTY_CHNG_END_CH6_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR    (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S  10
+/** LEDC_DUTY_CHNG_END_CH7_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR    (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S  11
+/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT.
+ */
+#define LEDC_OVF_CNT_CH0_INT_CLR    (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_CLR_M  (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S)
+#define LEDC_OVF_CNT_CH0_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH0_INT_CLR_S  12
+/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT.
+ */
+#define LEDC_OVF_CNT_CH1_INT_CLR    (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_CLR_M  (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S)
+#define LEDC_OVF_CNT_CH1_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH1_INT_CLR_S  13
+/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT.
+ */
+#define LEDC_OVF_CNT_CH2_INT_CLR    (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_CLR_M  (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S)
+#define LEDC_OVF_CNT_CH2_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH2_INT_CLR_S  14
+/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT.
+ */
+#define LEDC_OVF_CNT_CH3_INT_CLR    (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_CLR_M  (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S)
+#define LEDC_OVF_CNT_CH3_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH3_INT_CLR_S  15
+/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT.
+ */
+#define LEDC_OVF_CNT_CH4_INT_CLR    (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_CLR_M  (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S)
+#define LEDC_OVF_CNT_CH4_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH4_INT_CLR_S  16
+/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT.
+ */
+#define LEDC_OVF_CNT_CH5_INT_CLR    (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_CLR_M  (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S)
+#define LEDC_OVF_CNT_CH5_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH5_INT_CLR_S  17
+/** LEDC_OVF_CNT_CH6_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT.
+ */
+#define LEDC_OVF_CNT_CH6_INT_CLR    (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_CLR_M  (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S)
+#define LEDC_OVF_CNT_CH6_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH6_INT_CLR_S  18
+/** LEDC_OVF_CNT_CH7_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT.
+ */
+#define LEDC_OVF_CNT_CH7_INT_CLR    (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_CLR_M  (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S)
+#define LEDC_OVF_CNT_CH7_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH7_INT_CLR_S  19
+
+/** LEDC_CH0_GAMMA_CONF_REG register
+ *  Ledc ch0 gamma config register.
+ */
+#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100)
+/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch0.
+ */
+#define LEDC_CH0_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH0_GAMMA_ENTRY_NUM_M  (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH0_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH0_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch0.
+ *  0: Invalid. No effect
+ *  1: Pause
+ */
+#define LEDC_CH0_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH0_GAMMA_PAUSE_M  (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S)
+#define LEDC_CH0_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH0_GAMMA_PAUSE_S  5
+/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch0.
+ *  0: Invalid. No effect
+ *  1: Resume
+ */
+#define LEDC_CH0_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH0_GAMMA_RESUME_M  (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S)
+#define LEDC_CH0_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH0_GAMMA_RESUME_S  6
+
+/** LEDC_CH1_GAMMA_CONF_REG register
+ *  Ledc ch1 gamma config register.
+ */
+#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104)
+/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch1.
+ */
+#define LEDC_CH1_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH1_GAMMA_ENTRY_NUM_M  (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH1_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH1_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch1.
+ *  0: Invalid. No effect
+ *  1: Pause
+ */
+#define LEDC_CH1_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH1_GAMMA_PAUSE_M  (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S)
+#define LEDC_CH1_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH1_GAMMA_PAUSE_S  5
+/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch1.
+ *  0: Invalid. No effect
+ *  1: Resume
+ */
+#define LEDC_CH1_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH1_GAMMA_RESUME_M  (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S)
+#define LEDC_CH1_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH1_GAMMA_RESUME_S  6
+
+/** LEDC_CH2_GAMMA_CONF_REG register
+ *  Ledc ch2 gamma config register.
+ */
+#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108)
+/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch2.
+ */
+#define LEDC_CH2_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH2_GAMMA_ENTRY_NUM_M  (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH2_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH2_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch2.
+ *  0: Invalid. No effect
+ *  1: Pause
+ */
+#define LEDC_CH2_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH2_GAMMA_PAUSE_M  (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S)
+#define LEDC_CH2_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH2_GAMMA_PAUSE_S  5
+/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch2.
+ *  0: Invalid. No effect
+ *  1: Resume
+ */
+#define LEDC_CH2_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH2_GAMMA_RESUME_M  (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S)
+#define LEDC_CH2_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH2_GAMMA_RESUME_S  6
+
+/** LEDC_CH3_GAMMA_CONF_REG register
+ *  Ledc ch3 gamma config register.
+ */
+#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c)
+/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch3.
+ */
+#define LEDC_CH3_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH3_GAMMA_ENTRY_NUM_M  (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH3_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH3_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch3.
+ *  0: Invalid. No effect
+ *  1: Pause
+ */
+#define LEDC_CH3_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH3_GAMMA_PAUSE_M  (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S)
+#define LEDC_CH3_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH3_GAMMA_PAUSE_S  5
+/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch3.
+ *  0: Invalid. No effect
+ *  1: Resume
+ */
+#define LEDC_CH3_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH3_GAMMA_RESUME_M  (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S)
+#define LEDC_CH3_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH3_GAMMA_RESUME_S  6
+
+/** LEDC_CH4_GAMMA_CONF_REG register
+ *  Ledc ch4 gamma config register.
+ */
+#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110)
+/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch4.
+ */
+#define LEDC_CH4_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH4_GAMMA_ENTRY_NUM_M  (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH4_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH4_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch4.
+ *  0: Invalid. No effect
+ *  1: Pause
+ */
+#define LEDC_CH4_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH4_GAMMA_PAUSE_M  (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S)
+#define LEDC_CH4_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH4_GAMMA_PAUSE_S  5
+/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch4.
+ *  0: Invalid. No effect
+ *  1: Resume
+ */
+#define LEDC_CH4_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH4_GAMMA_RESUME_M  (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S)
+#define LEDC_CH4_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH4_GAMMA_RESUME_S  6
+
+/** LEDC_CH5_GAMMA_CONF_REG register
+ *  Ledc ch5 gamma config register.
+ */
+#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114)
+/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch5.
+ */
+#define LEDC_CH5_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH5_GAMMA_ENTRY_NUM_M  (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH5_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH5_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch5.
+ *  0: Invalid. No effect
+ *  1: Pause
+ */
+#define LEDC_CH5_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH5_GAMMA_PAUSE_M  (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S)
+#define LEDC_CH5_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH5_GAMMA_PAUSE_S  5
+/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch5.
+ *  0: Invalid. No effect
+ *  1: Resume
+ */
+#define LEDC_CH5_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH5_GAMMA_RESUME_M  (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S)
+#define LEDC_CH5_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH5_GAMMA_RESUME_S  6
+
+/** LEDC_CH6_GAMMA_CONF_REG register
+ *  Ledc ch6 gamma config register.
+ */
+#define LEDC_CH6_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x118)
+/** LEDC_CH6_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch6.
+ */
+#define LEDC_CH6_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH6_GAMMA_ENTRY_NUM_M  (LEDC_CH6_GAMMA_ENTRY_NUM_V << LEDC_CH6_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH6_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH6_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch6.
+ *  0: Invalid. No effect
+ *  1: Pause
+ */
+#define LEDC_CH6_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH6_GAMMA_PAUSE_M  (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S)
+#define LEDC_CH6_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH6_GAMMA_PAUSE_S  5
+/** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch6.
+ *  0: Invalid. No effect
+ *  1: Resume
+ */
+#define LEDC_CH6_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH6_GAMMA_RESUME_M  (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S)
+#define LEDC_CH6_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH6_GAMMA_RESUME_S  6
+
+/** LEDC_CH7_GAMMA_CONF_REG register
+ *  Ledc ch7 gamma config register.
+ */
+#define LEDC_CH7_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x11c)
+/** LEDC_CH7_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch7.
+ */
+#define LEDC_CH7_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH7_GAMMA_ENTRY_NUM_M  (LEDC_CH7_GAMMA_ENTRY_NUM_V << LEDC_CH7_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH7_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH7_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch7.
+ *  0: Invalid. No effect
+ *  1: Pause
+ */
+#define LEDC_CH7_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH7_GAMMA_PAUSE_M  (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S)
+#define LEDC_CH7_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH7_GAMMA_PAUSE_S  5
+/** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch7.
+ *  0: Invalid. No effect
+ *  1: Resume
+ */
+#define LEDC_CH7_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH7_GAMMA_RESUME_M  (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S)
+#define LEDC_CH7_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH7_GAMMA_RESUME_S  6
+
+/** LEDC_EVT_TASK_EN0_REG register
+ *  Ledc event task enable bit register0.
+ */
+#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120)
+/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable the ledc_ch0_duty_chng_end event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH0_EN    (BIT(0))
+#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S  0
+/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable the ledc_ch1_duty_chng_end event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH1_EN    (BIT(1))
+#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S  1
+/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable the ledc_ch2_duty_chng_end event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH2_EN    (BIT(2))
+#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S  2
+/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable the ledc_ch3_duty_chng_end event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH3_EN    (BIT(3))
+#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S  3
+/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable the ledc_ch4_duty_chng_end event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH4_EN    (BIT(4))
+#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S  4
+/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable the ledc_ch5_duty_chng_end event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH5_EN    (BIT(5))
+#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S  5
+/** LEDC_EVT_DUTY_CHNG_END_CH6_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable the ledc_ch6_duty_chng_end event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH6_EN    (BIT(6))
+#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH6_EN_V << LEDC_EVT_DUTY_CHNG_END_CH6_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_S  6
+/** LEDC_EVT_DUTY_CHNG_END_CH7_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable the ledc_ch7_duty_chng_end event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH7_EN    (BIT(7))
+#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH7_EN_V << LEDC_EVT_DUTY_CHNG_END_CH7_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_S  7
+/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH0_EN    (BIT(8))
+#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S  8
+/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH1_EN    (BIT(9))
+#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S  9
+/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH2_EN    (BIT(10))
+#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S  10
+/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH3_EN    (BIT(11))
+#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S  11
+/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH4_EN    (BIT(12))
+#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S  12
+/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH5_EN    (BIT(13))
+#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S  13
+/** LEDC_EVT_OVF_CNT_PLS_CH6_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH6_EN    (BIT(14))
+#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH6_EN_V << LEDC_EVT_OVF_CNT_PLS_CH6_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_S  14
+/** LEDC_EVT_OVF_CNT_PLS_CH7_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH7_EN    (BIT(15))
+#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH7_EN_V << LEDC_EVT_OVF_CNT_PLS_CH7_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_S  15
+/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable the ledc_timer0_ovf event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_TIME_OVF_TIMER0_EN    (BIT(16))
+#define LEDC_EVT_TIME_OVF_TIMER0_EN_M  (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S)
+#define LEDC_EVT_TIME_OVF_TIMER0_EN_V  0x00000001U
+#define LEDC_EVT_TIME_OVF_TIMER0_EN_S  16
+/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable the ledc_timer1_ovf event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_TIME_OVF_TIMER1_EN    (BIT(17))
+#define LEDC_EVT_TIME_OVF_TIMER1_EN_M  (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S)
+#define LEDC_EVT_TIME_OVF_TIMER1_EN_V  0x00000001U
+#define LEDC_EVT_TIME_OVF_TIMER1_EN_S  17
+/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable the ledc_timer2_ovf event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_TIME_OVF_TIMER2_EN    (BIT(18))
+#define LEDC_EVT_TIME_OVF_TIMER2_EN_M  (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S)
+#define LEDC_EVT_TIME_OVF_TIMER2_EN_V  0x00000001U
+#define LEDC_EVT_TIME_OVF_TIMER2_EN_S  18
+/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable the ledc_timer3_ovf event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_TIME_OVF_TIMER3_EN    (BIT(19))
+#define LEDC_EVT_TIME_OVF_TIMER3_EN_M  (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S)
+#define LEDC_EVT_TIME_OVF_TIMER3_EN_V  0x00000001U
+#define LEDC_EVT_TIME_OVF_TIMER3_EN_S  19
+/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable the ledc_timer0_cmp event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_TIME0_CMP_EN    (BIT(20))
+#define LEDC_EVT_TIME0_CMP_EN_M  (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S)
+#define LEDC_EVT_TIME0_CMP_EN_V  0x00000001U
+#define LEDC_EVT_TIME0_CMP_EN_S  20
+/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable the ledc_timer1_cmp event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_TIME1_CMP_EN    (BIT(21))
+#define LEDC_EVT_TIME1_CMP_EN_M  (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S)
+#define LEDC_EVT_TIME1_CMP_EN_V  0x00000001U
+#define LEDC_EVT_TIME1_CMP_EN_S  21
+/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable the ledc_timer2_cmp event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_TIME2_CMP_EN    (BIT(22))
+#define LEDC_EVT_TIME2_CMP_EN_M  (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S)
+#define LEDC_EVT_TIME2_CMP_EN_V  0x00000001U
+#define LEDC_EVT_TIME2_CMP_EN_S  22
+/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable the ledc_timer3_cmp event.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_EVT_TIME3_CMP_EN    (BIT(23))
+#define LEDC_EVT_TIME3_CMP_EN_M  (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S)
+#define LEDC_EVT_TIME3_CMP_EN_V  0x00000001U
+#define LEDC_EVT_TIME3_CMP_EN_S  23
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0;
+ *  Configures whether or not to enable the ledc_ch0_duty_scale_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN    (BIT(24))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S  24
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not to enable the ledc_ch1_duty_scale_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN    (BIT(25))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S  25
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0;
+ *  Configures whether or not to enable the ledc_ch2_duty_scale_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN    (BIT(26))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S  26
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to enable the ledc_ch3_duty_scale_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN    (BIT(27))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S  27
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable the ledc_ch4_duty_scale_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN    (BIT(28))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S  28
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable the ledc_ch5_duty_scale_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN    (BIT(29))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S  29
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN : R/W; bitpos: [30]; default: 0;
+ *  Configures whether or not to enable the ledc_ch6_duty_scale_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN    (BIT(30))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S  30
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures whether or not to enable the ledc_ch7_duty_scale_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN    (BIT(31))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S  31
+
+/** LEDC_EVT_TASK_EN1_REG register
+ *  Ledc event task enable bit register1.
+ */
+#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124)
+/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable ledc_timer0_res_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER0_RES_UPDATE_EN    (BIT(0))
+#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M  (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S)
+#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V  0x00000001U
+#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S  0
+/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable ledc_timer1_res_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER1_RES_UPDATE_EN    (BIT(1))
+#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M  (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S)
+#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V  0x00000001U
+#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S  1
+/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable ledc_timer2_res_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER2_RES_UPDATE_EN    (BIT(2))
+#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M  (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S)
+#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V  0x00000001U
+#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S  2
+/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable ledc_timer3_res_update task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER3_RES_UPDATE_EN    (BIT(3))
+#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M  (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S)
+#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V  0x00000001U
+#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S  3
+/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable ledc_timer0_cap task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER0_CAP_EN    (BIT(4))
+#define LEDC_TASK_TIMER0_CAP_EN_M  (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S)
+#define LEDC_TASK_TIMER0_CAP_EN_V  0x00000001U
+#define LEDC_TASK_TIMER0_CAP_EN_S  4
+/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable ledc_timer1_cap task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER1_CAP_EN    (BIT(5))
+#define LEDC_TASK_TIMER1_CAP_EN_M  (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S)
+#define LEDC_TASK_TIMER1_CAP_EN_V  0x00000001U
+#define LEDC_TASK_TIMER1_CAP_EN_S  5
+/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable ledc_timer2_cap task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER2_CAP_EN    (BIT(6))
+#define LEDC_TASK_TIMER2_CAP_EN_M  (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S)
+#define LEDC_TASK_TIMER2_CAP_EN_V  0x00000001U
+#define LEDC_TASK_TIMER2_CAP_EN_S  6
+/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ledc_timer3_cap task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER3_CAP_EN    (BIT(7))
+#define LEDC_TASK_TIMER3_CAP_EN_M  (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S)
+#define LEDC_TASK_TIMER3_CAP_EN_V  0x00000001U
+#define LEDC_TASK_TIMER3_CAP_EN_S  7
+/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable ledc_ch0_sig_out_dis task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH0_EN    (BIT(8))
+#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S  8
+/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable ledc_ch1_sig_out_dis task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH1_EN    (BIT(9))
+#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S  9
+/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable ledc_ch2_sig_out_dis task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH2_EN    (BIT(10))
+#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S  10
+/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable ledc_ch3_sig_out_dis task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH3_EN    (BIT(11))
+#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S  11
+/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable ledc_ch4_sig_out_dis task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH4_EN    (BIT(12))
+#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S  12
+/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable ledc_ch5_sig_out_dis task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH5_EN    (BIT(13))
+#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S  13
+/** LEDC_TASK_SIG_OUT_DIS_CH6_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable ledc_ch6_sig_out_dis task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH6_EN    (BIT(14))
+#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH6_EN_V << LEDC_TASK_SIG_OUT_DIS_CH6_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_S  14
+/** LEDC_TASK_SIG_OUT_DIS_CH7_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable ledc_ch7_sig_out_dis task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH7_EN    (BIT(15))
+#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH7_EN_V << LEDC_TASK_SIG_OUT_DIS_CH7_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_S  15
+/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH0_EN    (BIT(16))
+#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M  (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S  16
+/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH1_EN    (BIT(17))
+#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M  (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S  17
+/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH2_EN    (BIT(18))
+#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M  (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S  18
+/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH3_EN    (BIT(19))
+#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M  (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S  19
+/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH4_EN    (BIT(20))
+#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M  (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S  20
+/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH5_EN    (BIT(21))
+#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M  (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S  21
+/** LEDC_TASK_OVF_CNT_RST_CH6_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH6_EN    (BIT(22))
+#define LEDC_TASK_OVF_CNT_RST_CH6_EN_M  (LEDC_TASK_OVF_CNT_RST_CH6_EN_V << LEDC_TASK_OVF_CNT_RST_CH6_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH6_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH6_EN_S  22
+/** LEDC_TASK_OVF_CNT_RST_CH7_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH7_EN    (BIT(23))
+#define LEDC_TASK_OVF_CNT_RST_CH7_EN_M  (LEDC_TASK_OVF_CNT_RST_CH7_EN_V << LEDC_TASK_OVF_CNT_RST_CH7_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH7_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH7_EN_S  23
+/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0;
+ *  Configures whether or not to enable ledc_timer0_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER0_RST_EN    (BIT(24))
+#define LEDC_TASK_TIMER0_RST_EN_M  (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S)
+#define LEDC_TASK_TIMER0_RST_EN_V  0x00000001U
+#define LEDC_TASK_TIMER0_RST_EN_S  24
+/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not to enable ledc_timer1_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER1_RST_EN    (BIT(25))
+#define LEDC_TASK_TIMER1_RST_EN_M  (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S)
+#define LEDC_TASK_TIMER1_RST_EN_V  0x00000001U
+#define LEDC_TASK_TIMER1_RST_EN_S  25
+/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0;
+ *  Configures whether or not to enable ledc_timer2_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER2_RST_EN    (BIT(26))
+#define LEDC_TASK_TIMER2_RST_EN_M  (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S)
+#define LEDC_TASK_TIMER2_RST_EN_V  0x00000001U
+#define LEDC_TASK_TIMER2_RST_EN_S  26
+/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to enable ledc_timer3_rst task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER3_RST_EN    (BIT(27))
+#define LEDC_TASK_TIMER3_RST_EN_M  (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S)
+#define LEDC_TASK_TIMER3_RST_EN_V  0x00000001U
+#define LEDC_TASK_TIMER3_RST_EN_S  27
+/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable ledc_timer0_pause_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN    (BIT(28))
+#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S)
+#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V  0x00000001U
+#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S  28
+/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable ledc_timer1_pause_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN    (BIT(29))
+#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S)
+#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V  0x00000001U
+#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S  29
+/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0;
+ *  Configures whether or not to enable ledc_timer2_pause_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN    (BIT(30))
+#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S)
+#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V  0x00000001U
+#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S  30
+/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures whether or not to enable ledc_timer3_pause_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN    (BIT(31))
+#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S)
+#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V  0x00000001U
+#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S  31
+
+/** LEDC_EVT_TASK_EN2_REG register
+ *  Ledc event task enable bit register2.
+ */
+#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128)
+/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable ledc_ch0_gamma_restart task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH0_EN    (BIT(0))
+#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M  (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S  0
+/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable ledc_ch1_gamma_restart task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH1_EN    (BIT(1))
+#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M  (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S  1
+/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable ledc_ch2_gamma_restart task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH2_EN    (BIT(2))
+#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M  (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S  2
+/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable ledc_ch3_gamma_restart task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH3_EN    (BIT(3))
+#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M  (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S  3
+/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable ledc_ch4_gamma_restart task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH4_EN    (BIT(4))
+#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M  (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S  4
+/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable ledc_ch5_gamma_restart task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH5_EN    (BIT(5))
+#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M  (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S  5
+/** LEDC_TASK_GAMMA_RESTART_CH6_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable ledc_ch6_gamma_restart task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH6_EN    (BIT(6))
+#define LEDC_TASK_GAMMA_RESTART_CH6_EN_M  (LEDC_TASK_GAMMA_RESTART_CH6_EN_V << LEDC_TASK_GAMMA_RESTART_CH6_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH6_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH6_EN_S  6
+/** LEDC_TASK_GAMMA_RESTART_CH7_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ledc_ch7_gamma_restart task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH7_EN    (BIT(7))
+#define LEDC_TASK_GAMMA_RESTART_CH7_EN_M  (LEDC_TASK_GAMMA_RESTART_CH7_EN_V << LEDC_TASK_GAMMA_RESTART_CH7_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH7_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH7_EN_S  7
+/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable ledc_ch0_gamma_pause task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH0_EN    (BIT(8))
+#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S  8
+/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable ledc_ch1_gamma_pause task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH1_EN    (BIT(9))
+#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S  9
+/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable ledc_ch2_gamma_pause task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH2_EN    (BIT(10))
+#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S  10
+/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable ledc_ch3_gamma_pause task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH3_EN    (BIT(11))
+#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S  11
+/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable ledc_ch4_gamma_pause task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH4_EN    (BIT(12))
+#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S  12
+/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable ledc_ch5_gamma_pause task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH5_EN    (BIT(13))
+#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S  13
+/** LEDC_TASK_GAMMA_PAUSE_CH6_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable ledc_ch6_gamma_pause task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH6_EN    (BIT(14))
+#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH6_EN_V << LEDC_TASK_GAMMA_PAUSE_CH6_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_S  14
+/** LEDC_TASK_GAMMA_PAUSE_CH7_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable ledc_ch7_gamma_pause task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH7_EN    (BIT(15))
+#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH7_EN_V << LEDC_TASK_GAMMA_PAUSE_CH7_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_S  15
+/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable ledc_ch0_gamma_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH0_EN    (BIT(16))
+#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M  (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S  16
+/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable ledc_ch1_gamma_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH1_EN    (BIT(17))
+#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M  (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S  17
+/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable ledc_ch2_gamma_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH2_EN    (BIT(18))
+#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M  (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S  18
+/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable ledc_ch3_gamma_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH3_EN    (BIT(19))
+#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M  (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S  19
+/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable ledc_ch4_gamma_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH4_EN    (BIT(20))
+#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M  (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S  20
+/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable ledc_ch5_gamma_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH5_EN    (BIT(21))
+#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M  (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S  21
+/** LEDC_TASK_GAMMA_RESUME_CH6_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable ledc_ch6_gamma_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH6_EN    (BIT(22))
+#define LEDC_TASK_GAMMA_RESUME_CH6_EN_M  (LEDC_TASK_GAMMA_RESUME_CH6_EN_V << LEDC_TASK_GAMMA_RESUME_CH6_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH6_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH6_EN_S  22
+/** LEDC_TASK_GAMMA_RESUME_CH7_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable ledc_ch7_gamma_resume task.
+ *  0: Disable
+ *  1: Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH7_EN    (BIT(23))
+#define LEDC_TASK_GAMMA_RESUME_CH7_EN_M  (LEDC_TASK_GAMMA_RESUME_CH7_EN_V << LEDC_TASK_GAMMA_RESUME_CH7_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH7_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH7_EN_S  23
+
+/** LEDC_TIMER0_CMP_REG register
+ *  Ledc timer0 compare value register.
+ */
+#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140)
+/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0;
+ *  Configures the comparison value for LEDC timer0.
+ */
+#define LEDC_TIMER0_CMP    0x000FFFFFU
+#define LEDC_TIMER0_CMP_M  (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S)
+#define LEDC_TIMER0_CMP_V  0x000FFFFFU
+#define LEDC_TIMER0_CMP_S  0
+
+/** LEDC_TIMER1_CMP_REG register
+ *  Ledc timer1 compare value register.
+ */
+#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144)
+/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0;
+ *  Configures the comparison value for LEDC timer1.
+ */
+#define LEDC_TIMER1_CMP    0x000FFFFFU
+#define LEDC_TIMER1_CMP_M  (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S)
+#define LEDC_TIMER1_CMP_V  0x000FFFFFU
+#define LEDC_TIMER1_CMP_S  0
+
+/** LEDC_TIMER2_CMP_REG register
+ *  Ledc timer2 compare value register.
+ */
+#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148)
+/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0;
+ *  Configures the comparison value for LEDC timer2.
+ */
+#define LEDC_TIMER2_CMP    0x000FFFFFU
+#define LEDC_TIMER2_CMP_M  (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S)
+#define LEDC_TIMER2_CMP_V  0x000FFFFFU
+#define LEDC_TIMER2_CMP_S  0
+
+/** LEDC_TIMER3_CMP_REG register
+ *  Ledc timer3 compare value register.
+ */
+#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c)
+/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0;
+ *  Configures the comparison value for LEDC timer3.
+ */
+#define LEDC_TIMER3_CMP    0x000FFFFFU
+#define LEDC_TIMER3_CMP_M  (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S)
+#define LEDC_TIMER3_CMP_V  0x000FFFFFU
+#define LEDC_TIMER3_CMP_S  0
+
+/** LEDC_TIMER0_CNT_CAP_REG register
+ *  Ledc timer0 captured count value register.
+ */
+#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150)
+/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0;
+ *  Represents the captured LEDC timer0 count value.
+ */
+#define LEDC_TIMER0_CNT_CAP    0x000FFFFFU
+#define LEDC_TIMER0_CNT_CAP_M  (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S)
+#define LEDC_TIMER0_CNT_CAP_V  0x000FFFFFU
+#define LEDC_TIMER0_CNT_CAP_S  0
+
+/** LEDC_TIMER1_CNT_CAP_REG register
+ *  Ledc timer1 captured count value register.
+ */
+#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154)
+/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0;
+ *  Represents the captured LEDC timer1 count value.
+ */
+#define LEDC_TIMER1_CNT_CAP    0x000FFFFFU
+#define LEDC_TIMER1_CNT_CAP_M  (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S)
+#define LEDC_TIMER1_CNT_CAP_V  0x000FFFFFU
+#define LEDC_TIMER1_CNT_CAP_S  0
+
+/** LEDC_TIMER2_CNT_CAP_REG register
+ *  Ledc timer2 captured count value register.
+ */
+#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158)
+/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0;
+ *  Represents the captured LEDC timer2 count value.
+ */
+#define LEDC_TIMER2_CNT_CAP    0x000FFFFFU
+#define LEDC_TIMER2_CNT_CAP_M  (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S)
+#define LEDC_TIMER2_CNT_CAP_V  0x000FFFFFU
+#define LEDC_TIMER2_CNT_CAP_S  0
+
+/** LEDC_TIMER3_CNT_CAP_REG register
+ *  Ledc timer3 captured count value register.
+ */
+#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c)
+/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0;
+ *  Represents the captured LEDC timer3 count value.
+ */
+#define LEDC_TIMER3_CNT_CAP    0x000FFFFFU
+#define LEDC_TIMER3_CNT_CAP_M  (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S)
+#define LEDC_TIMER3_CNT_CAP_V  0x000FFFFFU
+#define LEDC_TIMER3_CNT_CAP_S  0
+
+/** LEDC_CONF_REG register
+ *  LEDC global configuration register
+ */
+#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170)
+/** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  Configures the clock source for the four timers.
+ *  0: APB_CLK
+ *  1: RC_FAST_CLK
+ *  2: XTAL_CLK
+ *  3: Invalid. No clock
+ */
+#define LEDC_APB_CLK_SEL    0x00000003U
+#define LEDC_APB_CLK_SEL_M  (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S)
+#define LEDC_APB_CLK_SEL_V  0x00000003U
+#define LEDC_APB_CLK_SEL_S  0
+/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to open LEDC ch0 gamma ram clock gate.
+ *  0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram
+ *  1: Force open the clock gate for LEDC ch0 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH0    (BIT(2))
+#define LEDC_GAMMA_RAM_CLK_EN_CH0_M  (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH0_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH0_S  2
+/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to open LEDC ch1 gamma ram clock gate.
+ *  0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram
+ *  1: Force open the clock gate for LEDC ch1 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH1    (BIT(3))
+#define LEDC_GAMMA_RAM_CLK_EN_CH1_M  (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH1_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH1_S  3
+/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to open LEDC ch2 gamma ram clock gate.
+ *  0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram
+ *  1: Force open the clock gate for LEDC ch2 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH2    (BIT(4))
+#define LEDC_GAMMA_RAM_CLK_EN_CH2_M  (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH2_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH2_S  4
+/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to open LEDC ch3 gamma ram clock gate.
+ *  0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram
+ *  1: Force open the clock gate for LEDC ch3 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH3    (BIT(5))
+#define LEDC_GAMMA_RAM_CLK_EN_CH3_M  (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH3_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH3_S  5
+/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to open LEDC ch4 gamma ram clock gate.
+ *  0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram
+ *  1: Force open the clock gate for LEDC ch4 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH4    (BIT(6))
+#define LEDC_GAMMA_RAM_CLK_EN_CH4_M  (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH4_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH4_S  6
+/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to open LEDC ch5 gamma ram clock gate.
+ *  0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram
+ *  1: Force open the clock gate for LEDC ch5 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH5    (BIT(7))
+#define LEDC_GAMMA_RAM_CLK_EN_CH5_M  (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH5_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH5_S  7
+/** LEDC_GAMMA_RAM_CLK_EN_CH6 : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to open LEDC ch6 gamma ram clock gate.
+ *  0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram
+ *  1: Force open the clock gate for LEDC ch6 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH6    (BIT(8))
+#define LEDC_GAMMA_RAM_CLK_EN_CH6_M  (LEDC_GAMMA_RAM_CLK_EN_CH6_V << LEDC_GAMMA_RAM_CLK_EN_CH6_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH6_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH6_S  8
+/** LEDC_GAMMA_RAM_CLK_EN_CH7 : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to open LEDC ch7 gamma ram clock gate.
+ *  0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram
+ *  1: Force open the clock gate for LEDC ch7 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH7    (BIT(9))
+#define LEDC_GAMMA_RAM_CLK_EN_CH7_M  (LEDC_GAMMA_RAM_CLK_EN_CH7_V << LEDC_GAMMA_RAM_CLK_EN_CH7_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH7_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH7_S  9
+/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures whether or not to open register clock gate.
+ *  0: Open the clock gate only when application writes registers
+ *  1: Force open the clock gate for register
+ */
+#define LEDC_CLK_EN    (BIT(31))
+#define LEDC_CLK_EN_M  (LEDC_CLK_EN_V << LEDC_CLK_EN_S)
+#define LEDC_CLK_EN_V  0x00000001U
+#define LEDC_CLK_EN_S  31
+
+/** LEDC_DATE_REG register
+ *  Version control register
+ */
+#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174)
+/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 37765152;
+ *  Configures the version.
+ */
+#define LEDC_LEDC_DATE    0x0FFFFFFFU
+#define LEDC_LEDC_DATE_M  (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S)
+#define LEDC_LEDC_DATE_V  0x0FFFFFFFU
+#define LEDC_LEDC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h
new file mode 100644
index 0000000000..ef59597ded
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h
@@ -0,0 +1,1359 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of chn_conf0 register
+ *  Configuration register 0 for channel n
+ */
+typedef union {
+    struct {
+        /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Configures which timer is channel n selected.
+         *  0: Select timer0
+         *  1: Select timer1
+         *  2: Select timer2
+         *  3: Select timer3
+         */
+        uint32_t timer_sel_chn:2;
+        /** sig_out_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable signal output on channel n.
+         *  0: Signal output disable
+         *  1: Signal output enable
+         */
+        uint32_t sig_out_en_chn:1;
+        /** idle_lv_chn : R/W; bitpos: [3]; default: 0;
+         *  Configures the output value when channel n is inactive. Valid only when
+         *  LEDC_SIG_OUT_EN_CHn is 0.
+         *  0: Output level is low
+         *  1: Output level is high
+         */
+        uint32_t idle_lv_chn:1;
+        /** para_up_chn : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn,
+         *  LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn,
+         *  LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel
+         *  n, and will be automatically cleared by hardware.
+         *  0: Invalid. No effect
+         *  1: Update
+         */
+        uint32_t para_up_chn:1;
+        /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0;
+         *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt
+         *  will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times.
+         */
+        uint32_t ovf_num_chn:10;
+        /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable the ovf_cnt of channel n.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t ovf_cnt_en_chn:1;
+        /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to reset the  ovf_cnt of channel n.
+         *  0: Invalid. No effect
+         *  1: Reset the ovf_cnt
+         */
+        uint32_t ovf_cnt_reset_chn:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} ledc_chn_conf0_reg_t;
+
+/** Type of chn_hpoint register
+ *  High point register for channel n
+ */
+typedef union {
+    struct {
+        /** hpoint_chn : R/W; bitpos: [19:0]; default: 0;
+         *  Configures high point of signal output on channel n. The output value changes to
+         *  high when the selected timers has reached the value specified by this register.
+         */
+        uint32_t hpoint_chn:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_chn_hpoint_reg_t;
+
+/** Type of chn_duty register
+ *  Initial duty cycle register for channel n
+ */
+typedef union {
+    struct {
+        /** duty_chn : R/W; bitpos: [24:0]; default: 0;
+         *  Configures the duty of signal output on channel n.
+         */
+        uint32_t duty_chn:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} ledc_chn_duty_reg_t;
+
+/** Type of chn_conf1 register
+ *  Configuration register 1 for channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0;
+         *  Configures whether the duty cycle fading configurations take effect.
+         *  0: Not take effect
+         *  1: Take effect
+         */
+        uint32_t duty_start_chn:1;
+    };
+    uint32_t val;
+} ledc_chn_conf1_reg_t;
+
+/** Type of timern_conf register
+ *  Timer n configuration register
+ */
+typedef union {
+    struct {
+        /** timern_duty_res : R/W; bitpos: [4:0]; default: 0;
+         *  Configures the range of the counter in timer n.
+         */
+        uint32_t timern_duty_res:5;
+        /** clk_div_timern : R/W; bitpos: [22:5]; default: 0;
+         *  Configures the divisor for the divider in timer n.The least significant eight bits
+         *  represent the fractional part.
+         */
+        uint32_t clk_div_timern:18;
+        /** timern_pause : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to pause the counter in timer n.
+         *  0: Normal
+         *  1: Pause
+         */
+        uint32_t timern_pause:1;
+        /** timern_rst : R/W; bitpos: [24]; default: 1;
+         *  Configures whether or not to reset timer n. The counter will show 0 after reset.
+         *  0: Not reset
+         *  1: Reset
+         */
+        uint32_t timern_rst:1;
+        uint32_t reserved_25:1;
+        /** timern_para_up : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES.
+         *  0: Invalid. No effect
+         *  1: Update
+         */
+        uint32_t timern_para_up:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} ledc_timern_conf_reg_t;
+
+/** Type of chn_gamma_conf register
+ *  Ledc chn gamma config register.
+ */
+typedef union {
+    struct {
+        /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0;
+         *  Configures the number of duty cycle fading rages for LEDC chn.
+         */
+        uint32_t chn_gamma_entry_num:5;
+        /** chn_gamma_pause : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to pause duty cycle fading of LEDC chn.
+         *  0: Invalid. No effect
+         *  1: Pause
+         */
+        uint32_t chn_gamma_pause:1;
+        /** chn_gamma_resume : WT; bitpos: [6]; default: 0;
+         *  Configures whether or nor to resume duty cycle fading of LEDC chn.
+         *  0: Invalid. No effect
+         *  1: Resume
+         */
+        uint32_t chn_gamma_resume:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ledc_chn_gamma_conf_reg_t;
+
+/** Type of evt_task_en0 register
+ *  Ledc event task enable bit register0.
+ */
+typedef union {
+    struct {
+        /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable the ledc_ch0_duty_chng_end event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch0_en:1;
+        /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable the ledc_ch1_duty_chng_end event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch1_en:1;
+        /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable the ledc_ch2_duty_chng_end event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch2_en:1;
+        /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable the ledc_ch3_duty_chng_end event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch3_en:1;
+        /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable the ledc_ch4_duty_chng_end event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch4_en:1;
+        /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable the ledc_ch5_duty_chng_end event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch5_en:1;
+        /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable the ledc_ch6_duty_chng_end event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch6_en:1;
+        /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable the ledc_ch7_duty_chng_end event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch7_en:1;
+        /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch0_en:1;
+        /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch1_en:1;
+        /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch2_en:1;
+        /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch3_en:1;
+        /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch4_en:1;
+        /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch5_en:1;
+        /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch6_en:1;
+        /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch7_en:1;
+        /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable the ledc_timer0_ovf event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_time_ovf_timer0_en:1;
+        /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable the ledc_timer1_ovf event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_time_ovf_timer1_en:1;
+        /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable the ledc_timer2_ovf event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_time_ovf_timer2_en:1;
+        /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable the ledc_timer3_ovf event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_time_ovf_timer3_en:1;
+        /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable the ledc_timer0_cmp event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_time0_cmp_en:1;
+        /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable the ledc_timer1_cmp event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_time1_cmp_en:1;
+        /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable the ledc_timer2_cmp event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_time2_cmp_en:1;
+        /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable the ledc_timer3_cmp event.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_time3_cmp_en:1;
+        /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable the ledc_ch0_duty_scale_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_duty_scale_update_ch0_en:1;
+        /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to enable the ledc_ch1_duty_scale_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_duty_scale_update_ch1_en:1;
+        /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to enable the ledc_ch2_duty_scale_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_duty_scale_update_ch2_en:1;
+        /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable the ledc_ch3_duty_scale_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_duty_scale_update_ch3_en:1;
+        /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable the ledc_ch4_duty_scale_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_duty_scale_update_ch4_en:1;
+        /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable the ledc_ch5_duty_scale_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_duty_scale_update_ch5_en:1;
+        /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0;
+         *  Configures whether or not to enable the ledc_ch6_duty_scale_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_duty_scale_update_ch6_en:1;
+        /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0;
+         *  Configures whether or not to enable the ledc_ch7_duty_scale_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_duty_scale_update_ch7_en:1;
+    };
+    uint32_t val;
+} ledc_evt_task_en0_reg_t;
+
+/** Type of evt_task_en1 register
+ *  Ledc event task enable bit register1.
+ */
+typedef union {
+    struct {
+        /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable ledc_timer0_res_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer0_res_update_en:1;
+        /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable ledc_timer1_res_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer1_res_update_en:1;
+        /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable ledc_timer2_res_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer2_res_update_en:1;
+        /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable ledc_timer3_res_update task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer3_res_update_en:1;
+        /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable ledc_timer0_cap task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer0_cap_en:1;
+        /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable ledc_timer1_cap task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer1_cap_en:1;
+        /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable ledc_timer2_cap task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer2_cap_en:1;
+        /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable ledc_timer3_cap task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer3_cap_en:1;
+        /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable ledc_ch0_sig_out_dis task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_sig_out_dis_ch0_en:1;
+        /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable ledc_ch1_sig_out_dis task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_sig_out_dis_ch1_en:1;
+        /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable ledc_ch2_sig_out_dis task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_sig_out_dis_ch2_en:1;
+        /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable ledc_ch3_sig_out_dis task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_sig_out_dis_ch3_en:1;
+        /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable ledc_ch4_sig_out_dis task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_sig_out_dis_ch4_en:1;
+        /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable ledc_ch5_sig_out_dis task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_sig_out_dis_ch5_en:1;
+        /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable ledc_ch6_sig_out_dis task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_sig_out_dis_ch6_en:1;
+        /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable ledc_ch7_sig_out_dis task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_sig_out_dis_ch7_en:1;
+        /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch0_en:1;
+        /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch1_en:1;
+        /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch2_en:1;
+        /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch3_en:1;
+        /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch4_en:1;
+        /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch5_en:1;
+        /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch6_en:1;
+        /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch7_en:1;
+        /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable ledc_timer0_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer0_rst_en:1;
+        /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to enable ledc_timer1_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer1_rst_en:1;
+        /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to enable ledc_timer2_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer2_rst_en:1;
+        /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable ledc_timer3_rst task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer3_rst_en:1;
+        /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable ledc_timer0_pause_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer0_pause_resume_en:1;
+        /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable ledc_timer1_pause_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer1_pause_resume_en:1;
+        /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0;
+         *  Configures whether or not to enable ledc_timer2_pause_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer2_pause_resume_en:1;
+        /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0;
+         *  Configures whether or not to enable ledc_timer3_pause_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer3_pause_resume_en:1;
+    };
+    uint32_t val;
+} ledc_evt_task_en1_reg_t;
+
+/** Type of evt_task_en2 register
+ *  Ledc event task enable bit register2.
+ */
+typedef union {
+    struct {
+        /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable ledc_ch0_gamma_restart task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_restart_ch0_en:1;
+        /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable ledc_ch1_gamma_restart task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_restart_ch1_en:1;
+        /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable ledc_ch2_gamma_restart task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_restart_ch2_en:1;
+        /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable ledc_ch3_gamma_restart task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_restart_ch3_en:1;
+        /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable ledc_ch4_gamma_restart task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_restart_ch4_en:1;
+        /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable ledc_ch5_gamma_restart task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_restart_ch5_en:1;
+        /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable ledc_ch6_gamma_restart task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_restart_ch6_en:1;
+        /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable ledc_ch7_gamma_restart task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_restart_ch7_en:1;
+        /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable ledc_ch0_gamma_pause task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_pause_ch0_en:1;
+        /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable ledc_ch1_gamma_pause task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_pause_ch1_en:1;
+        /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable ledc_ch2_gamma_pause task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_pause_ch2_en:1;
+        /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable ledc_ch3_gamma_pause task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_pause_ch3_en:1;
+        /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable ledc_ch4_gamma_pause task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_pause_ch4_en:1;
+        /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable ledc_ch5_gamma_pause task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_pause_ch5_en:1;
+        /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable ledc_ch6_gamma_pause task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_pause_ch6_en:1;
+        /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable ledc_ch7_gamma_pause task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_pause_ch7_en:1;
+        /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable ledc_ch0_gamma_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_resume_ch0_en:1;
+        /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable ledc_ch1_gamma_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_resume_ch1_en:1;
+        /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable ledc_ch2_gamma_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_resume_ch2_en:1;
+        /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable ledc_ch3_gamma_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_resume_ch3_en:1;
+        /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable ledc_ch4_gamma_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_resume_ch4_en:1;
+        /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable ledc_ch5_gamma_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_resume_ch5_en:1;
+        /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable ledc_ch6_gamma_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_resume_ch6_en:1;
+        /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable ledc_ch7_gamma_resume task.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gamma_resume_ch7_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ledc_evt_task_en2_reg_t;
+
+/** Type of timern_cmp register
+ *  Ledc timern compare value register.
+ */
+typedef union {
+    struct {
+        /** timern_cmp : R/W; bitpos: [19:0]; default: 0;
+         *  Configures the comparison value for LEDC timern.
+         */
+        uint32_t timern_cmp:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_timern_cmp_reg_t;
+
+/** Type of conf register
+ *  LEDC global configuration register
+ */
+typedef union {
+    struct {
+        /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Configures the clock source for the four timers.
+         *  0: APB_CLK
+         *  1: RC_FAST_CLK
+         *  2: XTAL_CLK
+         *  3: Invalid. No clock
+         */
+        uint32_t apb_clk_sel:2;
+        /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to open LEDC ch0 gamma ram clock gate.
+         *  0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram
+         *  1: Force open the clock gate for LEDC ch0 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch0:1;
+        /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to open LEDC ch1 gamma ram clock gate.
+         *  0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram
+         *  1: Force open the clock gate for LEDC ch1 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch1:1;
+        /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to open LEDC ch2 gamma ram clock gate.
+         *  0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram
+         *  1: Force open the clock gate for LEDC ch2 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch2:1;
+        /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to open LEDC ch3 gamma ram clock gate.
+         *  0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram
+         *  1: Force open the clock gate for LEDC ch3 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch3:1;
+        /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to open LEDC ch4 gamma ram clock gate.
+         *  0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram
+         *  1: Force open the clock gate for LEDC ch4 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch4:1;
+        /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to open LEDC ch5 gamma ram clock gate.
+         *  0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram
+         *  1: Force open the clock gate for LEDC ch5 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch5:1;
+        /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to open LEDC ch6 gamma ram clock gate.
+         *  0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram
+         *  1: Force open the clock gate for LEDC ch6 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch6:1;
+        /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to open LEDC ch7 gamma ram clock gate.
+         *  0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram
+         *  1: Force open the clock gate for LEDC ch7 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch7:1;
+        uint32_t reserved_10:21;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Configures whether or not to open register clock gate.
+         *  0: Open the clock gate only when application writes registers
+         *  1: Force open the clock gate for register
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} ledc_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of chn_duty_r register
+ *  Current duty cycle register for channel n
+ */
+typedef union {
+    struct {
+        /** duty_chn_r : RO; bitpos: [24:0]; default: 0;
+         *  Represents the current duty of output signal on channel n.
+         */
+        uint32_t duty_chn_r:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} ledc_chn_duty_r_reg_t;
+
+/** Type of timern_value register
+ *  Timer n current counter value register
+ */
+typedef union {
+    struct {
+        /** timern_cnt : RO; bitpos: [19:0]; default: 0;
+         *  Represents the current counter value of timer n.
+         */
+        uint32_t timern_cnt:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_timern_value_reg_t;
+
+/** Type of timern_cnt_cap register
+ *  Ledc timern captured count value register.
+ */
+typedef union {
+    struct {
+        /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0;
+         *  Represents the captured LEDC timern count value.
+         */
+        uint32_t timern_cnt_cap:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_timern_cnt_cap_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the
+         *  timer0 has reached its maximum counter value.
+         */
+        uint32_t timer0_ovf_int_raw:1;
+        /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the
+         *  timer1 has reached its maximum counter value.
+         */
+        uint32_t timer1_ovf_int_raw:1;
+        /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the
+         *  timer2 has reached its maximum counter value.
+         */
+        uint32_t timer2_ovf_int_raw:1;
+        /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the
+         *  timer3 has reached its maximum counter value.
+         */
+        uint32_t timer3_ovf_int_raw:1;
+        /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch0_int_raw:1;
+        /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch1_int_raw:1;
+        /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch2_int_raw:1;
+        /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch3_int_raw:1;
+        /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch4_int_raw:1;
+        /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch5_int_raw:1;
+        /** duty_chng_end_ch6_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch6_int_raw:1;
+        /** duty_chng_end_ch7_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch7_int_raw:1;
+        /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.
+         */
+        uint32_t ovf_cnt_ch0_int_raw:1;
+        /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.
+         */
+        uint32_t ovf_cnt_ch1_int_raw:1;
+        /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.
+         */
+        uint32_t ovf_cnt_ch2_int_raw:1;
+        /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.
+         */
+        uint32_t ovf_cnt_ch3_int_raw:1;
+        /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.
+         */
+        uint32_t ovf_cnt_ch4_int_raw:1;
+        /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.
+         */
+        uint32_t ovf_cnt_ch5_int_raw:1;
+        /** ovf_cnt_ch6_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6.
+         */
+        uint32_t ovf_cnt_ch6_int_raw:1;
+        /** ovf_cnt_ch7_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7.
+         */
+        uint32_t ovf_cnt_ch7_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt masked status register
+ */
+typedef union {
+    struct {
+        /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only
+         *  when LEDC_TIMER0_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer0_ovf_int_st:1;
+        /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only
+         *  when LEDC_TIMER1_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer1_ovf_int_st:1;
+        /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only
+         *  when LEDC_TIMER2_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer2_ovf_int_st:1;
+        /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only
+         *  when LEDC_TIMER3_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer3_ovf_int_st:1;
+        /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch0_int_st:1;
+        /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch1_int_st:1;
+        /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch2_int_st:1;
+        /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch3_int_st:1;
+        /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch4_int_st:1;
+        /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch5_int_st:1;
+        /** duty_chng_end_ch6_int_st : RO; bitpos: [10]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch6_int_st:1;
+        /** duty_chng_end_ch7_int_st : RO; bitpos: [11]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch7_int_st:1;
+        /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only
+         *  when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch0_int_st:1;
+        /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only
+         *  when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch1_int_st:1;
+        /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only
+         *  when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch2_int_st:1;
+        /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only
+         *  when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch3_int_st:1;
+        /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only
+         *  when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch4_int_st:1;
+        /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only
+         *  when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch5_int_st:1;
+        /** ovf_cnt_ch6_int_st : RO; bitpos: [18]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only
+         *  when LEDC_OVF_CNT_CH6_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch6_int_st:1;
+        /** ovf_cnt_ch7_int_st : RO; bitpos: [19]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only
+         *  when LEDC_OVF_CNT_CH7_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch7_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT.
+         */
+        uint32_t timer0_ovf_int_ena:1;
+        /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT.
+         */
+        uint32_t timer1_ovf_int_ena:1;
+        /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT.
+         */
+        uint32_t timer2_ovf_int_ena:1;
+        /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT.
+         */
+        uint32_t timer3_ovf_int_ena:1;
+        /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT.
+         */
+        uint32_t duty_chng_end_ch0_int_ena:1;
+        /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT.
+         */
+        uint32_t duty_chng_end_ch1_int_ena:1;
+        /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT.
+         */
+        uint32_t duty_chng_end_ch2_int_ena:1;
+        /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT.
+         */
+        uint32_t duty_chng_end_ch3_int_ena:1;
+        /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT.
+         */
+        uint32_t duty_chng_end_ch4_int_ena:1;
+        /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT.
+         */
+        uint32_t duty_chng_end_ch5_int_ena:1;
+        /** duty_chng_end_ch6_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT.
+         */
+        uint32_t duty_chng_end_ch6_int_ena:1;
+        /** duty_chng_end_ch7_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT.
+         */
+        uint32_t duty_chng_end_ch7_int_ena:1;
+        /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT.
+         */
+        uint32_t ovf_cnt_ch0_int_ena:1;
+        /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT.
+         */
+        uint32_t ovf_cnt_ch1_int_ena:1;
+        /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT.
+         */
+        uint32_t ovf_cnt_ch2_int_ena:1;
+        /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT.
+         */
+        uint32_t ovf_cnt_ch3_int_ena:1;
+        /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT.
+         */
+        uint32_t ovf_cnt_ch4_int_ena:1;
+        /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT.
+         */
+        uint32_t ovf_cnt_ch5_int_ena:1;
+        /** ovf_cnt_ch6_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT.
+         */
+        uint32_t ovf_cnt_ch6_int_ena:1;
+        /** ovf_cnt_ch7_int_ena : R/W; bitpos: [19]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT.
+         */
+        uint32_t ovf_cnt_ch7_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT.
+         */
+        uint32_t timer0_ovf_int_clr:1;
+        /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT.
+         */
+        uint32_t timer1_ovf_int_clr:1;
+        /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT.
+         */
+        uint32_t timer2_ovf_int_clr:1;
+        /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT.
+         */
+        uint32_t timer3_ovf_int_clr:1;
+        /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT.
+         */
+        uint32_t duty_chng_end_ch0_int_clr:1;
+        /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT.
+         */
+        uint32_t duty_chng_end_ch1_int_clr:1;
+        /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT.
+         */
+        uint32_t duty_chng_end_ch2_int_clr:1;
+        /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT.
+         */
+        uint32_t duty_chng_end_ch3_int_clr:1;
+        /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT.
+         */
+        uint32_t duty_chng_end_ch4_int_clr:1;
+        /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT.
+         */
+        uint32_t duty_chng_end_ch5_int_clr:1;
+        /** duty_chng_end_ch6_int_clr : WT; bitpos: [10]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT.
+         */
+        uint32_t duty_chng_end_ch6_int_clr:1;
+        /** duty_chng_end_ch7_int_clr : WT; bitpos: [11]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT.
+         */
+        uint32_t duty_chng_end_ch7_int_clr:1;
+        /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT.
+         */
+        uint32_t ovf_cnt_ch0_int_clr:1;
+        /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT.
+         */
+        uint32_t ovf_cnt_ch1_int_clr:1;
+        /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT.
+         */
+        uint32_t ovf_cnt_ch2_int_clr:1;
+        /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT.
+         */
+        uint32_t ovf_cnt_ch3_int_clr:1;
+        /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT.
+         */
+        uint32_t ovf_cnt_ch4_int_clr:1;
+        /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT.
+         */
+        uint32_t ovf_cnt_ch5_int_clr:1;
+        /** ovf_cnt_ch6_int_clr : WT; bitpos: [18]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT.
+         */
+        uint32_t ovf_cnt_ch6_int_clr:1;
+        /** ovf_cnt_ch7_int_clr : WT; bitpos: [19]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT.
+         */
+        uint32_t ovf_cnt_ch7_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** ledc_date : R/W; bitpos: [27:0]; default: 37765152;
+         *  Configures the version.
+         */
+        uint32_t ledc_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ledc_date_reg_t;
+
+
+typedef struct {
+    volatile ledc_chn_conf0_reg_t ch0_conf0;
+    volatile ledc_chn_hpoint_reg_t ch0_hpoint;
+    volatile ledc_chn_duty_reg_t ch0_duty;
+    volatile ledc_chn_conf1_reg_t ch0_conf1;
+    volatile ledc_chn_duty_r_reg_t ch0_duty_r;
+    volatile ledc_chn_conf0_reg_t ch1_conf0;
+    volatile ledc_chn_hpoint_reg_t ch1_hpoint;
+    volatile ledc_chn_duty_reg_t ch1_duty;
+    volatile ledc_chn_conf1_reg_t ch1_conf1;
+    volatile ledc_chn_duty_r_reg_t ch1_duty_r;
+    volatile ledc_chn_conf0_reg_t ch2_conf0;
+    volatile ledc_chn_hpoint_reg_t ch2_hpoint;
+    volatile ledc_chn_duty_reg_t ch2_duty;
+    volatile ledc_chn_conf1_reg_t ch2_conf1;
+    volatile ledc_chn_duty_r_reg_t ch2_duty_r;
+    volatile ledc_chn_conf0_reg_t ch3_conf0;
+    volatile ledc_chn_hpoint_reg_t ch3_hpoint;
+    volatile ledc_chn_duty_reg_t ch3_duty;
+    volatile ledc_chn_conf1_reg_t ch3_conf1;
+    volatile ledc_chn_duty_r_reg_t ch3_duty_r;
+    volatile ledc_chn_conf0_reg_t ch4_conf0;
+    volatile ledc_chn_hpoint_reg_t ch4_hpoint;
+    volatile ledc_chn_duty_reg_t ch4_duty;
+    volatile ledc_chn_conf1_reg_t ch4_conf1;
+    volatile ledc_chn_duty_r_reg_t ch4_duty_r;
+    volatile ledc_chn_conf0_reg_t ch5_conf0;
+    volatile ledc_chn_hpoint_reg_t ch5_hpoint;
+    volatile ledc_chn_duty_reg_t ch5_duty;
+    volatile ledc_chn_conf1_reg_t ch5_conf1;
+    volatile ledc_chn_duty_r_reg_t ch5_duty_r;
+    volatile ledc_chn_conf0_reg_t ch6_conf0;
+    volatile ledc_chn_hpoint_reg_t ch6_hpoint;
+    volatile ledc_chn_duty_reg_t ch6_duty;
+    volatile ledc_chn_conf1_reg_t ch6_conf1;
+    volatile ledc_chn_duty_r_reg_t ch6_duty_r;
+    volatile ledc_chn_conf0_reg_t ch7_conf0;
+    volatile ledc_chn_hpoint_reg_t ch7_hpoint;
+    volatile ledc_chn_duty_reg_t ch7_duty;
+    volatile ledc_chn_conf1_reg_t ch7_conf1;
+    volatile ledc_chn_duty_r_reg_t ch7_duty_r;
+    volatile ledc_timern_conf_reg_t timer0_conf;
+    volatile ledc_timern_value_reg_t timer0_value;
+    volatile ledc_timern_conf_reg_t timer1_conf;
+    volatile ledc_timern_value_reg_t timer1_value;
+    volatile ledc_timern_conf_reg_t timer2_conf;
+    volatile ledc_timern_value_reg_t timer2_value;
+    volatile ledc_timern_conf_reg_t timer3_conf;
+    volatile ledc_timern_value_reg_t timer3_value;
+    volatile ledc_int_raw_reg_t int_raw;
+    volatile ledc_int_st_reg_t int_st;
+    volatile ledc_int_ena_reg_t int_ena;
+    volatile ledc_int_clr_reg_t int_clr;
+    uint32_t reserved_0d0[12];
+    volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[8];
+    volatile ledc_evt_task_en0_reg_t evt_task_en0;
+    volatile ledc_evt_task_en1_reg_t evt_task_en1;
+    volatile ledc_evt_task_en2_reg_t evt_task_en2;
+    uint32_t reserved_12c[5];
+    volatile ledc_timern_cmp_reg_t timern_cmp[4];
+    volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4];
+    uint32_t reserved_160[4];
+    volatile ledc_conf_reg_t conf;
+    volatile ledc_date_reg_t date;
+} ledc_dev_t;
+
+extern ledc_dev_t LEDC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h
new file mode 100644
index 0000000000..05d7e02bbc
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h
@@ -0,0 +1,5742 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LEDC_CH0_CONF0_REG register
+ *  Configuration register 0 for channel 0
+ */
+#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0)
+/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 0 selected.\\0: Select timer0\\1: Select
+ *  timer1\\2: Select timer2\\3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH0    0x00000003U
+#define LEDC_TIMER_SEL_CH0_M  (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S)
+#define LEDC_TIMER_SEL_CH0_V  0x00000003U
+#define LEDC_TIMER_SEL_CH0_S  0
+/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 0.\\0: Signal output
+ *  disable\\1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH0    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH0_M  (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S)
+#define LEDC_SIG_OUT_EN_CH0_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH0_S  2
+/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 0 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH0 is 0.\\0: Output level is low\\1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH0    (BIT(3))
+#define LEDC_IDLE_LV_CH0_M  (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S)
+#define LEDC_IDLE_LV_CH0_V  0x00000001U
+#define LEDC_IDLE_LV_CH0_S  3
+/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0,
+ *  LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0,
+ *  LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel
+ *  0, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_PARA_UP_CH0    (BIT(4))
+#define LEDC_PARA_UP_CH0_M  (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S)
+#define LEDC_PARA_UP_CH0_V  0x00000001U
+#define LEDC_PARA_UP_CH0_S  4
+/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt
+ *  will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH0    0x000003FFU
+#define LEDC_OVF_NUM_CH0_M  (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S)
+#define LEDC_OVF_NUM_CH0_V  0x000003FFU
+#define LEDC_OVF_NUM_CH0_S  5
+/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 0.\\0: Disable\\1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH0    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH0_M  (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S)
+#define LEDC_OVF_CNT_EN_CH0_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH0_S  15
+/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 0.\\0: Invalid. No
+ *  effect\\1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH0    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH0_M  (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S)
+#define LEDC_OVF_CNT_RESET_CH0_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH0_S  16
+
+/** LEDC_CH0_HPOINT_REG register
+ *  High point register for channel 0
+ */
+#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4)
+/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 0. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH0    0x000FFFFFU
+#define LEDC_HPOINT_CH0_M  (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S)
+#define LEDC_HPOINT_CH0_V  0x000FFFFFU
+#define LEDC_HPOINT_CH0_S  0
+
+/** LEDC_CH0_DUTY_REG register
+ *  Initial duty cycle register for channel 0
+ */
+#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8)
+/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 0.
+ */
+#define LEDC_DUTY_CH0    0x01FFFFFFU
+#define LEDC_DUTY_CH0_M  (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S)
+#define LEDC_DUTY_CH0_V  0x01FFFFFFU
+#define LEDC_DUTY_CH0_S  0
+
+/** LEDC_CH0_CONF1_REG register
+ *  Configuration register 1 for channel 0
+ */
+#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc)
+/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
+ *  effect\\1: Take effect
+ */
+#define LEDC_DUTY_START_CH0    (BIT(31))
+#define LEDC_DUTY_START_CH0_M  (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S)
+#define LEDC_DUTY_START_CH0_V  0x00000001U
+#define LEDC_DUTY_START_CH0_S  31
+
+/** LEDC_CH0_DUTY_R_REG register
+ *  Current duty cycle register for channel 0
+ */
+#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10)
+/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 0.
+ */
+#define LEDC_DUTY_CH0_R    0x01FFFFFFU
+#define LEDC_DUTY_CH0_R_M  (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S)
+#define LEDC_DUTY_CH0_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH0_R_S  0
+
+/** LEDC_CH1_CONF0_REG register
+ *  Configuration register 0 for channel 1
+ */
+#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14)
+/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 1 selected.\\0: Select timer0\\1: Select
+ *  timer1\\2: Select timer2\\3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH1    0x00000003U
+#define LEDC_TIMER_SEL_CH1_M  (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S)
+#define LEDC_TIMER_SEL_CH1_V  0x00000003U
+#define LEDC_TIMER_SEL_CH1_S  0
+/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 1.\\0: Signal output
+ *  disable\\1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH1    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH1_M  (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S)
+#define LEDC_SIG_OUT_EN_CH1_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH1_S  2
+/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 1 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH1 is 0.\\0: Output level is low\\1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH1    (BIT(3))
+#define LEDC_IDLE_LV_CH1_M  (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S)
+#define LEDC_IDLE_LV_CH1_V  0x00000001U
+#define LEDC_IDLE_LV_CH1_S  3
+/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1,
+ *  LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1,
+ *  LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel
+ *  1, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_PARA_UP_CH1    (BIT(4))
+#define LEDC_PARA_UP_CH1_M  (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S)
+#define LEDC_PARA_UP_CH1_V  0x00000001U
+#define LEDC_PARA_UP_CH1_S  4
+/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt
+ *  will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH1    0x000003FFU
+#define LEDC_OVF_NUM_CH1_M  (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S)
+#define LEDC_OVF_NUM_CH1_V  0x000003FFU
+#define LEDC_OVF_NUM_CH1_S  5
+/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 1.\\0: Disable\\1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH1    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH1_M  (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S)
+#define LEDC_OVF_CNT_EN_CH1_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH1_S  15
+/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 1.\\0: Invalid. No
+ *  effect\\1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH1    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH1_M  (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S)
+#define LEDC_OVF_CNT_RESET_CH1_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH1_S  16
+
+/** LEDC_CH1_HPOINT_REG register
+ *  High point register for channel 1
+ */
+#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18)
+/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 1. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH1    0x000FFFFFU
+#define LEDC_HPOINT_CH1_M  (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S)
+#define LEDC_HPOINT_CH1_V  0x000FFFFFU
+#define LEDC_HPOINT_CH1_S  0
+
+/** LEDC_CH1_DUTY_REG register
+ *  Initial duty cycle register for channel 1
+ */
+#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c)
+/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 1.
+ */
+#define LEDC_DUTY_CH1    0x01FFFFFFU
+#define LEDC_DUTY_CH1_M  (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S)
+#define LEDC_DUTY_CH1_V  0x01FFFFFFU
+#define LEDC_DUTY_CH1_S  0
+
+/** LEDC_CH1_CONF1_REG register
+ *  Configuration register 1 for channel 1
+ */
+#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20)
+/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
+ *  effect\\1: Take effect
+ */
+#define LEDC_DUTY_START_CH1    (BIT(31))
+#define LEDC_DUTY_START_CH1_M  (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S)
+#define LEDC_DUTY_START_CH1_V  0x00000001U
+#define LEDC_DUTY_START_CH1_S  31
+
+/** LEDC_CH1_DUTY_R_REG register
+ *  Current duty cycle register for channel 1
+ */
+#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24)
+/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 1.
+ */
+#define LEDC_DUTY_CH1_R    0x01FFFFFFU
+#define LEDC_DUTY_CH1_R_M  (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S)
+#define LEDC_DUTY_CH1_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH1_R_S  0
+
+/** LEDC_CH2_CONF0_REG register
+ *  Configuration register 0 for channel 2
+ */
+#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28)
+/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 2 selected.\\0: Select timer0\\1: Select
+ *  timer1\\2: Select timer2\\3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH2    0x00000003U
+#define LEDC_TIMER_SEL_CH2_M  (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S)
+#define LEDC_TIMER_SEL_CH2_V  0x00000003U
+#define LEDC_TIMER_SEL_CH2_S  0
+/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 2.\\0: Signal output
+ *  disable\\1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH2    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH2_M  (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S)
+#define LEDC_SIG_OUT_EN_CH2_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH2_S  2
+/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 2 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH2 is 0.\\0: Output level is low\\1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH2    (BIT(3))
+#define LEDC_IDLE_LV_CH2_M  (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S)
+#define LEDC_IDLE_LV_CH2_V  0x00000001U
+#define LEDC_IDLE_LV_CH2_S  3
+/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2,
+ *  LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2,
+ *  LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel
+ *  2, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_PARA_UP_CH2    (BIT(4))
+#define LEDC_PARA_UP_CH2_M  (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S)
+#define LEDC_PARA_UP_CH2_V  0x00000001U
+#define LEDC_PARA_UP_CH2_S  4
+/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt
+ *  will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH2    0x000003FFU
+#define LEDC_OVF_NUM_CH2_M  (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S)
+#define LEDC_OVF_NUM_CH2_V  0x000003FFU
+#define LEDC_OVF_NUM_CH2_S  5
+/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 2.\\0: Disable\\1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH2    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH2_M  (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S)
+#define LEDC_OVF_CNT_EN_CH2_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH2_S  15
+/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 2.\\0: Invalid. No
+ *  effect\\1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH2    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH2_M  (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S)
+#define LEDC_OVF_CNT_RESET_CH2_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH2_S  16
+
+/** LEDC_CH2_HPOINT_REG register
+ *  High point register for channel 2
+ */
+#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c)
+/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 2. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH2    0x000FFFFFU
+#define LEDC_HPOINT_CH2_M  (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S)
+#define LEDC_HPOINT_CH2_V  0x000FFFFFU
+#define LEDC_HPOINT_CH2_S  0
+
+/** LEDC_CH2_DUTY_REG register
+ *  Initial duty cycle register for channel 2
+ */
+#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30)
+/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 2.
+ */
+#define LEDC_DUTY_CH2    0x01FFFFFFU
+#define LEDC_DUTY_CH2_M  (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S)
+#define LEDC_DUTY_CH2_V  0x01FFFFFFU
+#define LEDC_DUTY_CH2_S  0
+
+/** LEDC_CH2_CONF1_REG register
+ *  Configuration register 1 for channel 2
+ */
+#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34)
+/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
+ *  effect\\1: Take effect
+ */
+#define LEDC_DUTY_START_CH2    (BIT(31))
+#define LEDC_DUTY_START_CH2_M  (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S)
+#define LEDC_DUTY_START_CH2_V  0x00000001U
+#define LEDC_DUTY_START_CH2_S  31
+
+/** LEDC_CH2_DUTY_R_REG register
+ *  Current duty cycle register for channel 2
+ */
+#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38)
+/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 2.
+ */
+#define LEDC_DUTY_CH2_R    0x01FFFFFFU
+#define LEDC_DUTY_CH2_R_M  (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S)
+#define LEDC_DUTY_CH2_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH2_R_S  0
+
+/** LEDC_CH3_CONF0_REG register
+ *  Configuration register 0 for channel 3
+ */
+#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c)
+/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 3 selected.\\0: Select timer0\\1: Select
+ *  timer1\\2: Select timer2\\3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH3    0x00000003U
+#define LEDC_TIMER_SEL_CH3_M  (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S)
+#define LEDC_TIMER_SEL_CH3_V  0x00000003U
+#define LEDC_TIMER_SEL_CH3_S  0
+/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 3.\\0: Signal output
+ *  disable\\1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH3    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH3_M  (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S)
+#define LEDC_SIG_OUT_EN_CH3_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH3_S  2
+/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 3 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH3 is 0.\\0: Output level is low\\1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH3    (BIT(3))
+#define LEDC_IDLE_LV_CH3_M  (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S)
+#define LEDC_IDLE_LV_CH3_V  0x00000001U
+#define LEDC_IDLE_LV_CH3_S  3
+/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3,
+ *  LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3,
+ *  LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel
+ *  3, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_PARA_UP_CH3    (BIT(4))
+#define LEDC_PARA_UP_CH3_M  (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S)
+#define LEDC_PARA_UP_CH3_V  0x00000001U
+#define LEDC_PARA_UP_CH3_S  4
+/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt
+ *  will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH3    0x000003FFU
+#define LEDC_OVF_NUM_CH3_M  (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S)
+#define LEDC_OVF_NUM_CH3_V  0x000003FFU
+#define LEDC_OVF_NUM_CH3_S  5
+/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 3.\\0: Disable\\1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH3    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH3_M  (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S)
+#define LEDC_OVF_CNT_EN_CH3_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH3_S  15
+/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 3.\\0: Invalid. No
+ *  effect\\1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH3    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH3_M  (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S)
+#define LEDC_OVF_CNT_RESET_CH3_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH3_S  16
+
+/** LEDC_CH3_HPOINT_REG register
+ *  High point register for channel 3
+ */
+#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40)
+/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 3. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH3    0x000FFFFFU
+#define LEDC_HPOINT_CH3_M  (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S)
+#define LEDC_HPOINT_CH3_V  0x000FFFFFU
+#define LEDC_HPOINT_CH3_S  0
+
+/** LEDC_CH3_DUTY_REG register
+ *  Initial duty cycle register for channel 3
+ */
+#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44)
+/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 3.
+ */
+#define LEDC_DUTY_CH3    0x01FFFFFFU
+#define LEDC_DUTY_CH3_M  (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S)
+#define LEDC_DUTY_CH3_V  0x01FFFFFFU
+#define LEDC_DUTY_CH3_S  0
+
+/** LEDC_CH3_CONF1_REG register
+ *  Configuration register 1 for channel 3
+ */
+#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48)
+/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
+ *  effect\\1: Take effect
+ */
+#define LEDC_DUTY_START_CH3    (BIT(31))
+#define LEDC_DUTY_START_CH3_M  (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S)
+#define LEDC_DUTY_START_CH3_V  0x00000001U
+#define LEDC_DUTY_START_CH3_S  31
+
+/** LEDC_CH3_DUTY_R_REG register
+ *  Current duty cycle register for channel 3
+ */
+#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c)
+/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 3.
+ */
+#define LEDC_DUTY_CH3_R    0x01FFFFFFU
+#define LEDC_DUTY_CH3_R_M  (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S)
+#define LEDC_DUTY_CH3_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH3_R_S  0
+
+/** LEDC_CH4_CONF0_REG register
+ *  Configuration register 0 for channel 4
+ */
+#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50)
+/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 4 selected.\\0: Select timer0\\1: Select
+ *  timer1\\2: Select timer2\\3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH4    0x00000003U
+#define LEDC_TIMER_SEL_CH4_M  (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S)
+#define LEDC_TIMER_SEL_CH4_V  0x00000003U
+#define LEDC_TIMER_SEL_CH4_S  0
+/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 4.\\0: Signal output
+ *  disable\\1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH4    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH4_M  (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S)
+#define LEDC_SIG_OUT_EN_CH4_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH4_S  2
+/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 4 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH4 is 0.\\0: Output level is low\\1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH4    (BIT(3))
+#define LEDC_IDLE_LV_CH4_M  (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S)
+#define LEDC_IDLE_LV_CH4_V  0x00000001U
+#define LEDC_IDLE_LV_CH4_S  3
+/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4,
+ *  LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4,
+ *  LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel
+ *  4, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_PARA_UP_CH4    (BIT(4))
+#define LEDC_PARA_UP_CH4_M  (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S)
+#define LEDC_PARA_UP_CH4_V  0x00000001U
+#define LEDC_PARA_UP_CH4_S  4
+/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt
+ *  will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH4    0x000003FFU
+#define LEDC_OVF_NUM_CH4_M  (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S)
+#define LEDC_OVF_NUM_CH4_V  0x000003FFU
+#define LEDC_OVF_NUM_CH4_S  5
+/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 4.\\0: Disable\\1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH4    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH4_M  (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S)
+#define LEDC_OVF_CNT_EN_CH4_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH4_S  15
+/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 4.\\0: Invalid. No
+ *  effect\\1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH4    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH4_M  (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S)
+#define LEDC_OVF_CNT_RESET_CH4_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH4_S  16
+
+/** LEDC_CH4_HPOINT_REG register
+ *  High point register for channel 4
+ */
+#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54)
+/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 4. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH4    0x000FFFFFU
+#define LEDC_HPOINT_CH4_M  (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S)
+#define LEDC_HPOINT_CH4_V  0x000FFFFFU
+#define LEDC_HPOINT_CH4_S  0
+
+/** LEDC_CH4_DUTY_REG register
+ *  Initial duty cycle register for channel 4
+ */
+#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58)
+/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 4.
+ */
+#define LEDC_DUTY_CH4    0x01FFFFFFU
+#define LEDC_DUTY_CH4_M  (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S)
+#define LEDC_DUTY_CH4_V  0x01FFFFFFU
+#define LEDC_DUTY_CH4_S  0
+
+/** LEDC_CH4_CONF1_REG register
+ *  Configuration register 1 for channel 4
+ */
+#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c)
+/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
+ *  effect\\1: Take effect
+ */
+#define LEDC_DUTY_START_CH4    (BIT(31))
+#define LEDC_DUTY_START_CH4_M  (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S)
+#define LEDC_DUTY_START_CH4_V  0x00000001U
+#define LEDC_DUTY_START_CH4_S  31
+
+/** LEDC_CH4_DUTY_R_REG register
+ *  Current duty cycle register for channel 4
+ */
+#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60)
+/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 4.
+ */
+#define LEDC_DUTY_CH4_R    0x01FFFFFFU
+#define LEDC_DUTY_CH4_R_M  (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S)
+#define LEDC_DUTY_CH4_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH4_R_S  0
+
+/** LEDC_CH5_CONF0_REG register
+ *  Configuration register 0 for channel 5
+ */
+#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64)
+/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 5 selected.\\0: Select timer0\\1: Select
+ *  timer1\\2: Select timer2\\3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH5    0x00000003U
+#define LEDC_TIMER_SEL_CH5_M  (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S)
+#define LEDC_TIMER_SEL_CH5_V  0x00000003U
+#define LEDC_TIMER_SEL_CH5_S  0
+/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 5.\\0: Signal output
+ *  disable\\1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH5    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH5_M  (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S)
+#define LEDC_SIG_OUT_EN_CH5_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH5_S  2
+/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 5 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH5 is 0.\\0: Output level is low\\1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH5    (BIT(3))
+#define LEDC_IDLE_LV_CH5_M  (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S)
+#define LEDC_IDLE_LV_CH5_V  0x00000001U
+#define LEDC_IDLE_LV_CH5_S  3
+/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5,
+ *  LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5,
+ *  LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel
+ *  5, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_PARA_UP_CH5    (BIT(4))
+#define LEDC_PARA_UP_CH5_M  (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S)
+#define LEDC_PARA_UP_CH5_V  0x00000001U
+#define LEDC_PARA_UP_CH5_S  4
+/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt
+ *  will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH5    0x000003FFU
+#define LEDC_OVF_NUM_CH5_M  (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S)
+#define LEDC_OVF_NUM_CH5_V  0x000003FFU
+#define LEDC_OVF_NUM_CH5_S  5
+/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 5.\\0: Disable\\1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH5    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH5_M  (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S)
+#define LEDC_OVF_CNT_EN_CH5_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH5_S  15
+/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 5.\\0: Invalid. No
+ *  effect\\1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH5    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH5_M  (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S)
+#define LEDC_OVF_CNT_RESET_CH5_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH5_S  16
+
+/** LEDC_CH5_HPOINT_REG register
+ *  High point register for channel 5
+ */
+#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68)
+/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 5. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH5    0x000FFFFFU
+#define LEDC_HPOINT_CH5_M  (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S)
+#define LEDC_HPOINT_CH5_V  0x000FFFFFU
+#define LEDC_HPOINT_CH5_S  0
+
+/** LEDC_CH5_DUTY_REG register
+ *  Initial duty cycle register for channel 5
+ */
+#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c)
+/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 5.
+ */
+#define LEDC_DUTY_CH5    0x01FFFFFFU
+#define LEDC_DUTY_CH5_M  (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S)
+#define LEDC_DUTY_CH5_V  0x01FFFFFFU
+#define LEDC_DUTY_CH5_S  0
+
+/** LEDC_CH5_CONF1_REG register
+ *  Configuration register 1 for channel 5
+ */
+#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70)
+/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
+ *  effect\\1: Take effect
+ */
+#define LEDC_DUTY_START_CH5    (BIT(31))
+#define LEDC_DUTY_START_CH5_M  (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S)
+#define LEDC_DUTY_START_CH5_V  0x00000001U
+#define LEDC_DUTY_START_CH5_S  31
+
+/** LEDC_CH5_DUTY_R_REG register
+ *  Current duty cycle register for channel 5
+ */
+#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74)
+/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 5.
+ */
+#define LEDC_DUTY_CH5_R    0x01FFFFFFU
+#define LEDC_DUTY_CH5_R_M  (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S)
+#define LEDC_DUTY_CH5_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH5_R_S  0
+
+/** LEDC_CH6_CONF0_REG register
+ *  Configuration register 0 for channel 6
+ */
+#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78)
+/** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 6 selected.\\0: Select timer0\\1: Select
+ *  timer1\\2: Select timer2\\3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH6    0x00000003U
+#define LEDC_TIMER_SEL_CH6_M  (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S)
+#define LEDC_TIMER_SEL_CH6_V  0x00000003U
+#define LEDC_TIMER_SEL_CH6_S  0
+/** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 6.\\0: Signal output
+ *  disable\\1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH6    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH6_M  (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S)
+#define LEDC_SIG_OUT_EN_CH6_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH6_S  2
+/** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 6 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH6 is 0.\\0: Output level is low\\1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH6    (BIT(3))
+#define LEDC_IDLE_LV_CH6_M  (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S)
+#define LEDC_IDLE_LV_CH6_V  0x00000001U
+#define LEDC_IDLE_LV_CH6_S  3
+/** LEDC_PARA_UP_CH6 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6,
+ *  LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6,
+ *  LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel
+ *  6, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_PARA_UP_CH6    (BIT(4))
+#define LEDC_PARA_UP_CH6_M  (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S)
+#define LEDC_PARA_UP_CH6_V  0x00000001U
+#define LEDC_PARA_UP_CH6_S  4
+/** LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH6_INT interrupt
+ *  will be triggered when channel 6 overflows for (LEDC_OVF_NUM_CH6 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH6    0x000003FFU
+#define LEDC_OVF_NUM_CH6_M  (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S)
+#define LEDC_OVF_NUM_CH6_V  0x000003FFU
+#define LEDC_OVF_NUM_CH6_S  5
+/** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 6.\\0: Disable\\1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH6    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH6_M  (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S)
+#define LEDC_OVF_CNT_EN_CH6_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH6_S  15
+/** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 6.\\0: Invalid. No
+ *  effect\\1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH6    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH6_M  (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S)
+#define LEDC_OVF_CNT_RESET_CH6_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH6_S  16
+
+/** LEDC_CH6_HPOINT_REG register
+ *  High point register for channel 6
+ */
+#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c)
+/** LEDC_HPOINT_CH6 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 6. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH6    0x000FFFFFU
+#define LEDC_HPOINT_CH6_M  (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S)
+#define LEDC_HPOINT_CH6_V  0x000FFFFFU
+#define LEDC_HPOINT_CH6_S  0
+
+/** LEDC_CH6_DUTY_REG register
+ *  Initial duty cycle register for channel 6
+ */
+#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80)
+/** LEDC_DUTY_CH6 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 6.
+ */
+#define LEDC_DUTY_CH6    0x01FFFFFFU
+#define LEDC_DUTY_CH6_M  (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S)
+#define LEDC_DUTY_CH6_V  0x01FFFFFFU
+#define LEDC_DUTY_CH6_S  0
+
+/** LEDC_CH6_CONF1_REG register
+ *  Configuration register 1 for channel 6
+ */
+#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84)
+/** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
+ *  effect\\1: Take effect
+ */
+#define LEDC_DUTY_START_CH6    (BIT(31))
+#define LEDC_DUTY_START_CH6_M  (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S)
+#define LEDC_DUTY_START_CH6_V  0x00000001U
+#define LEDC_DUTY_START_CH6_S  31
+
+/** LEDC_CH6_DUTY_R_REG register
+ *  Current duty cycle register for channel 6
+ */
+#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88)
+/** LEDC_DUTY_CH6_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 6.
+ */
+#define LEDC_DUTY_CH6_R    0x01FFFFFFU
+#define LEDC_DUTY_CH6_R_M  (LEDC_DUTY_CH6_R_V << LEDC_DUTY_CH6_R_S)
+#define LEDC_DUTY_CH6_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH6_R_S  0
+
+/** LEDC_CH7_CONF0_REG register
+ *  Configuration register 0 for channel 7
+ */
+#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c)
+/** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which timer is channel 7 selected.\\0: Select timer0\\1: Select
+ *  timer1\\2: Select timer2\\3: Select timer3
+ */
+#define LEDC_TIMER_SEL_CH7    0x00000003U
+#define LEDC_TIMER_SEL_CH7_M  (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S)
+#define LEDC_TIMER_SEL_CH7_V  0x00000003U
+#define LEDC_TIMER_SEL_CH7_S  0
+/** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable signal output on channel 7.\\0: Signal output
+ *  disable\\1: Signal output enable
+ */
+#define LEDC_SIG_OUT_EN_CH7    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH7_M  (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S)
+#define LEDC_SIG_OUT_EN_CH7_V  0x00000001U
+#define LEDC_SIG_OUT_EN_CH7_S  2
+/** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0;
+ *  Configures the output value when channel 7 is inactive. Valid only when
+ *  LEDC_SIG_OUT_EN_CH7 is 0.\\0: Output level is low\\1: Output level is high
+ */
+#define LEDC_IDLE_LV_CH7    (BIT(3))
+#define LEDC_IDLE_LV_CH7_M  (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S)
+#define LEDC_IDLE_LV_CH7_V  0x00000001U
+#define LEDC_IDLE_LV_CH7_S  3
+/** LEDC_PARA_UP_CH7 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7,
+ *  LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7,
+ *  LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel
+ *  7, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_PARA_UP_CH7    (BIT(4))
+#define LEDC_PARA_UP_CH7_M  (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S)
+#define LEDC_PARA_UP_CH7_V  0x00000001U
+#define LEDC_PARA_UP_CH7_S  4
+/** LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0;
+ *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH7_INT interrupt
+ *  will be triggered when channel 7 overflows for (LEDC_OVF_NUM_CH7 + 1) times.
+ */
+#define LEDC_OVF_NUM_CH7    0x000003FFU
+#define LEDC_OVF_NUM_CH7_M  (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S)
+#define LEDC_OVF_NUM_CH7_V  0x000003FFU
+#define LEDC_OVF_NUM_CH7_S  5
+/** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ovf_cnt of channel 7.\\0: Disable\\1: Enable
+ */
+#define LEDC_OVF_CNT_EN_CH7    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH7_M  (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S)
+#define LEDC_OVF_CNT_EN_CH7_V  0x00000001U
+#define LEDC_OVF_CNT_EN_CH7_S  15
+/** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to reset the  ovf_cnt of channel 7.\\0: Invalid. No
+ *  effect\\1: Reset the ovf_cnt
+ */
+#define LEDC_OVF_CNT_RESET_CH7    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH7_M  (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S)
+#define LEDC_OVF_CNT_RESET_CH7_V  0x00000001U
+#define LEDC_OVF_CNT_RESET_CH7_S  16
+
+/** LEDC_CH7_HPOINT_REG register
+ *  High point register for channel 7
+ */
+#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90)
+/** LEDC_HPOINT_CH7 : R/W; bitpos: [19:0]; default: 0;
+ *  Configures high point of signal output on channel 7. The output value changes to
+ *  high when the selected timers has reached the value specified by this register.
+ */
+#define LEDC_HPOINT_CH7    0x000FFFFFU
+#define LEDC_HPOINT_CH7_M  (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S)
+#define LEDC_HPOINT_CH7_V  0x000FFFFFU
+#define LEDC_HPOINT_CH7_S  0
+
+/** LEDC_CH7_DUTY_REG register
+ *  Initial duty cycle register for channel 7
+ */
+#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94)
+/** LEDC_DUTY_CH7 : R/W; bitpos: [24:0]; default: 0;
+ *  Configures the duty of signal output on channel 7.
+ */
+#define LEDC_DUTY_CH7    0x01FFFFFFU
+#define LEDC_DUTY_CH7_M  (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S)
+#define LEDC_DUTY_CH7_V  0x01FFFFFFU
+#define LEDC_DUTY_CH7_S  0
+
+/** LEDC_CH7_CONF1_REG register
+ *  Configuration register 1 for channel 7
+ */
+#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98)
+/** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
+ *  effect\\1: Take effect
+ */
+#define LEDC_DUTY_START_CH7    (BIT(31))
+#define LEDC_DUTY_START_CH7_M  (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S)
+#define LEDC_DUTY_START_CH7_V  0x00000001U
+#define LEDC_DUTY_START_CH7_S  31
+
+/** LEDC_CH7_DUTY_R_REG register
+ *  Current duty cycle register for channel 7
+ */
+#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c)
+/** LEDC_DUTY_CH7_R : RO; bitpos: [24:0]; default: 0;
+ *  Represents the current duty of output signal on channel 7.
+ */
+#define LEDC_DUTY_CH7_R    0x01FFFFFFU
+#define LEDC_DUTY_CH7_R_M  (LEDC_DUTY_CH7_R_V << LEDC_DUTY_CH7_R_S)
+#define LEDC_DUTY_CH7_R_V  0x01FFFFFFU
+#define LEDC_DUTY_CH7_R_S  0
+
+/** LEDC_TIMER0_CONF_REG register
+ *  Timer 0 configuration register
+ */
+#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0)
+/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the range of the counter in timer 0.
+ */
+#define LEDC_TIMER0_DUTY_RES    0x0000001FU
+#define LEDC_TIMER0_DUTY_RES_M  (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S)
+#define LEDC_TIMER0_DUTY_RES_V  0x0000001FU
+#define LEDC_TIMER0_DUTY_RES_S  0
+/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0;
+ *  Configures the divisor for the divider in timer 0.The least significant eight bits
+ *  represent the fractional part.
+ */
+#define LEDC_CLK_DIV_TIMER0    0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER0_M  (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S)
+#define LEDC_CLK_DIV_TIMER0_V  0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER0_S  5
+/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to pause the counter in timer 0.\\0: Normal\\1: Pause
+ */
+#define LEDC_TIMER0_PAUSE    (BIT(23))
+#define LEDC_TIMER0_PAUSE_M  (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S)
+#define LEDC_TIMER0_PAUSE_V  0x00000001U
+#define LEDC_TIMER0_PAUSE_S  23
+/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1;
+ *  Configures whether or not to reset timer 0. The counter will show 0 after
+ *  reset.\\0: Not reset\\1: Reset
+ */
+#define LEDC_TIMER0_RST    (BIT(24))
+#define LEDC_TIMER0_RST_M  (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S)
+#define LEDC_TIMER0_RST_V  0x00000001U
+#define LEDC_TIMER0_RST_S  24
+/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0;
+ *  Configures which clock is timer 0 selected. Unused.
+ */
+#define LEDC_TICK_SEL_TIMER0    (BIT(25))
+#define LEDC_TICK_SEL_TIMER0_M  (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S)
+#define LEDC_TICK_SEL_TIMER0_V  0x00000001U
+#define LEDC_TICK_SEL_TIMER0_S  25
+/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to update LEDC_CLK_DIV_TIMER0 and
+ *  LEDC_TIMER0_DUTY_RES.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_TIMER0_PARA_UP    (BIT(26))
+#define LEDC_TIMER0_PARA_UP_M  (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S)
+#define LEDC_TIMER0_PARA_UP_V  0x00000001U
+#define LEDC_TIMER0_PARA_UP_S  26
+
+/** LEDC_TIMER0_VALUE_REG register
+ *  Timer 0 current counter value register
+ */
+#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4)
+/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0;
+ *  Represents the current counter value of timer 0.
+ */
+#define LEDC_TIMER0_CNT    0x000FFFFFU
+#define LEDC_TIMER0_CNT_M  (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S)
+#define LEDC_TIMER0_CNT_V  0x000FFFFFU
+#define LEDC_TIMER0_CNT_S  0
+
+/** LEDC_TIMER1_CONF_REG register
+ *  Timer 1 configuration register
+ */
+#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8)
+/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the range of the counter in timer 1.
+ */
+#define LEDC_TIMER1_DUTY_RES    0x0000001FU
+#define LEDC_TIMER1_DUTY_RES_M  (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S)
+#define LEDC_TIMER1_DUTY_RES_V  0x0000001FU
+#define LEDC_TIMER1_DUTY_RES_S  0
+/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0;
+ *  Configures the divisor for the divider in timer 1.The least significant eight bits
+ *  represent the fractional part.
+ */
+#define LEDC_CLK_DIV_TIMER1    0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER1_M  (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S)
+#define LEDC_CLK_DIV_TIMER1_V  0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER1_S  5
+/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to pause the counter in timer 1.\\0: Normal\\1: Pause
+ */
+#define LEDC_TIMER1_PAUSE    (BIT(23))
+#define LEDC_TIMER1_PAUSE_M  (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S)
+#define LEDC_TIMER1_PAUSE_V  0x00000001U
+#define LEDC_TIMER1_PAUSE_S  23
+/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1;
+ *  Configures whether or not to reset timer 1. The counter will show 0 after
+ *  reset.\\0: Not reset\\1: Reset
+ */
+#define LEDC_TIMER1_RST    (BIT(24))
+#define LEDC_TIMER1_RST_M  (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S)
+#define LEDC_TIMER1_RST_V  0x00000001U
+#define LEDC_TIMER1_RST_S  24
+/** LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [25]; default: 0;
+ *  Configures which clock is timer 1 selected. Unused.
+ */
+#define LEDC_TICK_SEL_TIMER1    (BIT(25))
+#define LEDC_TICK_SEL_TIMER1_M  (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S)
+#define LEDC_TICK_SEL_TIMER1_V  0x00000001U
+#define LEDC_TICK_SEL_TIMER1_S  25
+/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to update LEDC_CLK_DIV_TIMER1 and
+ *  LEDC_TIMER1_DUTY_RES.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_TIMER1_PARA_UP    (BIT(26))
+#define LEDC_TIMER1_PARA_UP_M  (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S)
+#define LEDC_TIMER1_PARA_UP_V  0x00000001U
+#define LEDC_TIMER1_PARA_UP_S  26
+
+/** LEDC_TIMER1_VALUE_REG register
+ *  Timer 1 current counter value register
+ */
+#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac)
+/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0;
+ *  Represents the current counter value of timer 1.
+ */
+#define LEDC_TIMER1_CNT    0x000FFFFFU
+#define LEDC_TIMER1_CNT_M  (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S)
+#define LEDC_TIMER1_CNT_V  0x000FFFFFU
+#define LEDC_TIMER1_CNT_S  0
+
+/** LEDC_TIMER2_CONF_REG register
+ *  Timer 2 configuration register
+ */
+#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0)
+/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the range of the counter in timer 2.
+ */
+#define LEDC_TIMER2_DUTY_RES    0x0000001FU
+#define LEDC_TIMER2_DUTY_RES_M  (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S)
+#define LEDC_TIMER2_DUTY_RES_V  0x0000001FU
+#define LEDC_TIMER2_DUTY_RES_S  0
+/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0;
+ *  Configures the divisor for the divider in timer 2.The least significant eight bits
+ *  represent the fractional part.
+ */
+#define LEDC_CLK_DIV_TIMER2    0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER2_M  (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S)
+#define LEDC_CLK_DIV_TIMER2_V  0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER2_S  5
+/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to pause the counter in timer 2.\\0: Normal\\1: Pause
+ */
+#define LEDC_TIMER2_PAUSE    (BIT(23))
+#define LEDC_TIMER2_PAUSE_M  (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S)
+#define LEDC_TIMER2_PAUSE_V  0x00000001U
+#define LEDC_TIMER2_PAUSE_S  23
+/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1;
+ *  Configures whether or not to reset timer 2. The counter will show 0 after
+ *  reset.\\0: Not reset\\1: Reset
+ */
+#define LEDC_TIMER2_RST    (BIT(24))
+#define LEDC_TIMER2_RST_M  (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S)
+#define LEDC_TIMER2_RST_V  0x00000001U
+#define LEDC_TIMER2_RST_S  24
+/** LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [25]; default: 0;
+ *  Configures which clock is timer 2 selected. Unused.
+ */
+#define LEDC_TICK_SEL_TIMER2    (BIT(25))
+#define LEDC_TICK_SEL_TIMER2_M  (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S)
+#define LEDC_TICK_SEL_TIMER2_V  0x00000001U
+#define LEDC_TICK_SEL_TIMER2_S  25
+/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to update LEDC_CLK_DIV_TIMER2 and
+ *  LEDC_TIMER2_DUTY_RES.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_TIMER2_PARA_UP    (BIT(26))
+#define LEDC_TIMER2_PARA_UP_M  (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S)
+#define LEDC_TIMER2_PARA_UP_V  0x00000001U
+#define LEDC_TIMER2_PARA_UP_S  26
+
+/** LEDC_TIMER2_VALUE_REG register
+ *  Timer 2 current counter value register
+ */
+#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4)
+/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0;
+ *  Represents the current counter value of timer 2.
+ */
+#define LEDC_TIMER2_CNT    0x000FFFFFU
+#define LEDC_TIMER2_CNT_M  (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S)
+#define LEDC_TIMER2_CNT_V  0x000FFFFFU
+#define LEDC_TIMER2_CNT_S  0
+
+/** LEDC_TIMER3_CONF_REG register
+ *  Timer 3 configuration register
+ */
+#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8)
+/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the range of the counter in timer 3.
+ */
+#define LEDC_TIMER3_DUTY_RES    0x0000001FU
+#define LEDC_TIMER3_DUTY_RES_M  (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S)
+#define LEDC_TIMER3_DUTY_RES_V  0x0000001FU
+#define LEDC_TIMER3_DUTY_RES_S  0
+/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0;
+ *  Configures the divisor for the divider in timer 3.The least significant eight bits
+ *  represent the fractional part.
+ */
+#define LEDC_CLK_DIV_TIMER3    0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER3_M  (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S)
+#define LEDC_CLK_DIV_TIMER3_V  0x0003FFFFU
+#define LEDC_CLK_DIV_TIMER3_S  5
+/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to pause the counter in timer 3.\\0: Normal\\1: Pause
+ */
+#define LEDC_TIMER3_PAUSE    (BIT(23))
+#define LEDC_TIMER3_PAUSE_M  (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S)
+#define LEDC_TIMER3_PAUSE_V  0x00000001U
+#define LEDC_TIMER3_PAUSE_S  23
+/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1;
+ *  Configures whether or not to reset timer 3. The counter will show 0 after
+ *  reset.\\0: Not reset\\1: Reset
+ */
+#define LEDC_TIMER3_RST    (BIT(24))
+#define LEDC_TIMER3_RST_M  (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S)
+#define LEDC_TIMER3_RST_V  0x00000001U
+#define LEDC_TIMER3_RST_S  24
+/** LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [25]; default: 0;
+ *  Configures which clock is timer 3 selected. Unused.
+ */
+#define LEDC_TICK_SEL_TIMER3    (BIT(25))
+#define LEDC_TICK_SEL_TIMER3_M  (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S)
+#define LEDC_TICK_SEL_TIMER3_V  0x00000001U
+#define LEDC_TICK_SEL_TIMER3_S  25
+/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to update LEDC_CLK_DIV_TIMER3 and
+ *  LEDC_TIMER3_DUTY_RES.\\0: Invalid. No effect\\1: Update
+ */
+#define LEDC_TIMER3_PARA_UP    (BIT(26))
+#define LEDC_TIMER3_PARA_UP_M  (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S)
+#define LEDC_TIMER3_PARA_UP_V  0x00000001U
+#define LEDC_TIMER3_PARA_UP_S  26
+
+/** LEDC_TIMER3_VALUE_REG register
+ *  Timer 3 current counter value register
+ */
+#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc)
+/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0;
+ *  Represents the current counter value of timer 3.
+ */
+#define LEDC_TIMER3_CNT    0x000FFFFFU
+#define LEDC_TIMER3_CNT_M  (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S)
+#define LEDC_TIMER3_CNT_V  0x000FFFFFU
+#define LEDC_TIMER3_CNT_S  0
+
+/** LEDC_INT_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0)
+/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the
+ *  timer0 has reached its maximum counter value.
+ */
+#define LEDC_TIMER0_OVF_INT_RAW    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_RAW_M  (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S)
+#define LEDC_TIMER0_OVF_INT_RAW_V  0x00000001U
+#define LEDC_TIMER0_OVF_INT_RAW_S  0
+/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the
+ *  timer1 has reached its maximum counter value.
+ */
+#define LEDC_TIMER1_OVF_INT_RAW    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_RAW_M  (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S)
+#define LEDC_TIMER1_OVF_INT_RAW_V  0x00000001U
+#define LEDC_TIMER1_OVF_INT_RAW_S  1
+/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the
+ *  timer2 has reached its maximum counter value.
+ */
+#define LEDC_TIMER2_OVF_INT_RAW    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_RAW_M  (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S)
+#define LEDC_TIMER2_OVF_INT_RAW_V  0x00000001U
+#define LEDC_TIMER2_OVF_INT_RAW_S  2
+/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the
+ *  timer3 has reached its maximum counter value.
+ */
+#define LEDC_TIMER3_OVF_INT_RAW    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_RAW_M  (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S)
+#define LEDC_TIMER3_OVF_INT_RAW_V  0x00000001U
+#define LEDC_TIMER3_OVF_INT_RAW_S  3
+/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S  4
+/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S  5
+/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S  6
+/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S  7
+/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S  8
+/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S  9
+/** LEDC_DUTY_CHNG_END_CH6_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW    (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S  10
+/** LEDC_DUTY_CHNG_END_CH7_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered
+ *  when the fading of duty has finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW    (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S  11
+/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.
+ */
+#define LEDC_OVF_CNT_CH0_INT_RAW    (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_RAW_M  (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S)
+#define LEDC_OVF_CNT_CH0_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH0_INT_RAW_S  12
+/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.
+ */
+#define LEDC_OVF_CNT_CH1_INT_RAW    (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_RAW_M  (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S)
+#define LEDC_OVF_CNT_CH1_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH1_INT_RAW_S  13
+/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.
+ */
+#define LEDC_OVF_CNT_CH2_INT_RAW    (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_RAW_M  (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S)
+#define LEDC_OVF_CNT_CH2_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH2_INT_RAW_S  14
+/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.
+ */
+#define LEDC_OVF_CNT_CH3_INT_RAW    (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_RAW_M  (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S)
+#define LEDC_OVF_CNT_CH3_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH3_INT_RAW_S  15
+/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.
+ */
+#define LEDC_OVF_CNT_CH4_INT_RAW    (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_RAW_M  (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S)
+#define LEDC_OVF_CNT_CH4_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH4_INT_RAW_S  16
+/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.
+ */
+#define LEDC_OVF_CNT_CH5_INT_RAW    (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_RAW_M  (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S)
+#define LEDC_OVF_CNT_CH5_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH5_INT_RAW_S  17
+/** LEDC_OVF_CNT_CH6_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6.
+ */
+#define LEDC_OVF_CNT_CH6_INT_RAW    (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_RAW_M  (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S)
+#define LEDC_OVF_CNT_CH6_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH6_INT_RAW_S  18
+/** LEDC_OVF_CNT_CH7_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when
+ *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7.
+ */
+#define LEDC_OVF_CNT_CH7_INT_RAW    (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_RAW_M  (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S)
+#define LEDC_OVF_CNT_CH7_INT_RAW_V  0x00000001U
+#define LEDC_OVF_CNT_CH7_INT_RAW_S  19
+
+/** LEDC_INT_ST_REG register
+ *  Interrupt masked status register
+ */
+#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4)
+/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only
+ *  when LEDC_TIMER0_OVF_INT_ENA is set to 1.
+ */
+#define LEDC_TIMER0_OVF_INT_ST    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_ST_M  (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S)
+#define LEDC_TIMER0_OVF_INT_ST_V  0x00000001U
+#define LEDC_TIMER0_OVF_INT_ST_S  0
+/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only
+ *  when LEDC_TIMER1_OVF_INT_ENA is set to 1.
+ */
+#define LEDC_TIMER1_OVF_INT_ST    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_ST_M  (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S)
+#define LEDC_TIMER1_OVF_INT_ST_V  0x00000001U
+#define LEDC_TIMER1_OVF_INT_ST_S  1
+/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only
+ *  when LEDC_TIMER2_OVF_INT_ENA is set to 1.
+ */
+#define LEDC_TIMER2_OVF_INT_ST    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_ST_M  (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S)
+#define LEDC_TIMER2_OVF_INT_ST_V  0x00000001U
+#define LEDC_TIMER2_OVF_INT_ST_S  2
+/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only
+ *  when LEDC_TIMER3_OVF_INT_ENA is set to 1.
+ */
+#define LEDC_TIMER3_OVF_INT_ST    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_ST_M  (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S)
+#define LEDC_TIMER3_OVF_INT_ST_V  0x00000001U
+#define LEDC_TIMER3_OVF_INT_ST_S  3
+/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M  (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S  4
+/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M  (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S  5
+/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M  (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S  6
+/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M  (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S  7
+/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M  (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S  8
+/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M  (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S  9
+/** LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST    (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M  (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S  10
+/** LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid
+ *  only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST    (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M  (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S  11
+/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only
+ *  when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH0_INT_ST    (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_ST_M  (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S)
+#define LEDC_OVF_CNT_CH0_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH0_INT_ST_S  12
+/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only
+ *  when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH1_INT_ST    (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_ST_M  (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S)
+#define LEDC_OVF_CNT_CH1_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH1_INT_ST_S  13
+/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only
+ *  when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH2_INT_ST    (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_ST_M  (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S)
+#define LEDC_OVF_CNT_CH2_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH2_INT_ST_S  14
+/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only
+ *  when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH3_INT_ST    (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_ST_M  (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S)
+#define LEDC_OVF_CNT_CH3_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH3_INT_ST_S  15
+/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only
+ *  when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH4_INT_ST    (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_ST_M  (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S)
+#define LEDC_OVF_CNT_CH4_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH4_INT_ST_S  16
+/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only
+ *  when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH5_INT_ST    (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_ST_M  (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S)
+#define LEDC_OVF_CNT_CH5_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH5_INT_ST_S  17
+/** LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only
+ *  when LEDC_OVF_CNT_CH6_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH6_INT_ST    (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_ST_M  (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S)
+#define LEDC_OVF_CNT_CH6_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH6_INT_ST_S  18
+/** LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0;
+ *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only
+ *  when LEDC_OVF_CNT_CH7_INT_ENA is set to 1.
+ */
+#define LEDC_OVF_CNT_CH7_INT_ST    (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_ST_M  (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S)
+#define LEDC_OVF_CNT_CH7_INT_ST_V  0x00000001U
+#define LEDC_OVF_CNT_CH7_INT_ST_S  19
+
+/** LEDC_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8)
+/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT.
+ */
+#define LEDC_TIMER0_OVF_INT_ENA    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_ENA_M  (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S)
+#define LEDC_TIMER0_OVF_INT_ENA_V  0x00000001U
+#define LEDC_TIMER0_OVF_INT_ENA_S  0
+/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT.
+ */
+#define LEDC_TIMER1_OVF_INT_ENA    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_ENA_M  (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S)
+#define LEDC_TIMER1_OVF_INT_ENA_V  0x00000001U
+#define LEDC_TIMER1_OVF_INT_ENA_S  1
+/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT.
+ */
+#define LEDC_TIMER2_OVF_INT_ENA    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_ENA_M  (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S)
+#define LEDC_TIMER2_OVF_INT_ENA_V  0x00000001U
+#define LEDC_TIMER2_OVF_INT_ENA_S  2
+/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT.
+ */
+#define LEDC_TIMER3_OVF_INT_ENA    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_ENA_M  (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S)
+#define LEDC_TIMER3_OVF_INT_ENA_V  0x00000001U
+#define LEDC_TIMER3_OVF_INT_ENA_S  3
+/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S  4
+/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S  5
+/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S  6
+/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S  7
+/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S  8
+/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S  9
+/** LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA    (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S  10
+/** LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA    (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S  11
+/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT.
+ */
+#define LEDC_OVF_CNT_CH0_INT_ENA    (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_ENA_M  (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S)
+#define LEDC_OVF_CNT_CH0_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH0_INT_ENA_S  12
+/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT.
+ */
+#define LEDC_OVF_CNT_CH1_INT_ENA    (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_ENA_M  (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S)
+#define LEDC_OVF_CNT_CH1_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH1_INT_ENA_S  13
+/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT.
+ */
+#define LEDC_OVF_CNT_CH2_INT_ENA    (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_ENA_M  (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S)
+#define LEDC_OVF_CNT_CH2_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH2_INT_ENA_S  14
+/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT.
+ */
+#define LEDC_OVF_CNT_CH3_INT_ENA    (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_ENA_M  (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S)
+#define LEDC_OVF_CNT_CH3_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH3_INT_ENA_S  15
+/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT.
+ */
+#define LEDC_OVF_CNT_CH4_INT_ENA    (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_ENA_M  (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S)
+#define LEDC_OVF_CNT_CH4_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH4_INT_ENA_S  16
+/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT.
+ */
+#define LEDC_OVF_CNT_CH5_INT_ENA    (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_ENA_M  (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S)
+#define LEDC_OVF_CNT_CH5_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH5_INT_ENA_S  17
+/** LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT.
+ */
+#define LEDC_OVF_CNT_CH6_INT_ENA    (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_ENA_M  (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S)
+#define LEDC_OVF_CNT_CH6_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH6_INT_ENA_S  18
+/** LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT.
+ */
+#define LEDC_OVF_CNT_CH7_INT_ENA    (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_ENA_M  (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S)
+#define LEDC_OVF_CNT_CH7_INT_ENA_V  0x00000001U
+#define LEDC_OVF_CNT_CH7_INT_ENA_S  19
+
+/** LEDC_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc)
+/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT.
+ */
+#define LEDC_TIMER0_OVF_INT_CLR    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_CLR_M  (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S)
+#define LEDC_TIMER0_OVF_INT_CLR_V  0x00000001U
+#define LEDC_TIMER0_OVF_INT_CLR_S  0
+/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT.
+ */
+#define LEDC_TIMER1_OVF_INT_CLR    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_CLR_M  (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S)
+#define LEDC_TIMER1_OVF_INT_CLR_V  0x00000001U
+#define LEDC_TIMER1_OVF_INT_CLR_S  1
+/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT.
+ */
+#define LEDC_TIMER2_OVF_INT_CLR    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_CLR_M  (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S)
+#define LEDC_TIMER2_OVF_INT_CLR_V  0x00000001U
+#define LEDC_TIMER2_OVF_INT_CLR_S  2
+/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT.
+ */
+#define LEDC_TIMER3_OVF_INT_CLR    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_CLR_M  (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S)
+#define LEDC_TIMER3_OVF_INT_CLR_V  0x00000001U
+#define LEDC_TIMER3_OVF_INT_CLR_S  3
+/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S  4
+/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S  5
+/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S  6
+/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S  7
+/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S  8
+/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S  9
+/** LEDC_DUTY_CHNG_END_CH6_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR    (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S  10
+/** LEDC_DUTY_CHNG_END_CH7_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT.
+ */
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR    (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V  0x00000001U
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S  11
+/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT.
+ */
+#define LEDC_OVF_CNT_CH0_INT_CLR    (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_CLR_M  (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S)
+#define LEDC_OVF_CNT_CH0_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH0_INT_CLR_S  12
+/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT.
+ */
+#define LEDC_OVF_CNT_CH1_INT_CLR    (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_CLR_M  (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S)
+#define LEDC_OVF_CNT_CH1_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH1_INT_CLR_S  13
+/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT.
+ */
+#define LEDC_OVF_CNT_CH2_INT_CLR    (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_CLR_M  (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S)
+#define LEDC_OVF_CNT_CH2_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH2_INT_CLR_S  14
+/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT.
+ */
+#define LEDC_OVF_CNT_CH3_INT_CLR    (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_CLR_M  (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S)
+#define LEDC_OVF_CNT_CH3_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH3_INT_CLR_S  15
+/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT.
+ */
+#define LEDC_OVF_CNT_CH4_INT_CLR    (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_CLR_M  (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S)
+#define LEDC_OVF_CNT_CH4_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH4_INT_CLR_S  16
+/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT.
+ */
+#define LEDC_OVF_CNT_CH5_INT_CLR    (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_CLR_M  (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S)
+#define LEDC_OVF_CNT_CH5_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH5_INT_CLR_S  17
+/** LEDC_OVF_CNT_CH6_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT.
+ */
+#define LEDC_OVF_CNT_CH6_INT_CLR    (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_CLR_M  (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S)
+#define LEDC_OVF_CNT_CH6_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH6_INT_CLR_S  18
+/** LEDC_OVF_CNT_CH7_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT.
+ */
+#define LEDC_OVF_CNT_CH7_INT_CLR    (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_CLR_M  (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S)
+#define LEDC_OVF_CNT_CH7_INT_CLR_V  0x00000001U
+#define LEDC_OVF_CNT_CH7_INT_CLR_S  19
+
+/** LEDC_CH0_GAMMA_CONF_REG register
+ *  Ledc ch0 gamma config register.
+ */
+#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100)
+/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch0.
+ */
+#define LEDC_CH0_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH0_GAMMA_ENTRY_NUM_M  (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH0_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH0_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch0.\\0: Invalid. No
+ *  effect\\1: Pause
+ */
+#define LEDC_CH0_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH0_GAMMA_PAUSE_M  (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S)
+#define LEDC_CH0_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH0_GAMMA_PAUSE_S  5
+/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch0.\\0: Invalid. No
+ *  effect\\1: Resume
+ */
+#define LEDC_CH0_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH0_GAMMA_RESUME_M  (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S)
+#define LEDC_CH0_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH0_GAMMA_RESUME_S  6
+
+/** LEDC_CH1_GAMMA_CONF_REG register
+ *  Ledc ch1 gamma config register.
+ */
+#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104)
+/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch1.
+ */
+#define LEDC_CH1_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH1_GAMMA_ENTRY_NUM_M  (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH1_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH1_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch1.\\0: Invalid. No
+ *  effect\\1: Pause
+ */
+#define LEDC_CH1_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH1_GAMMA_PAUSE_M  (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S)
+#define LEDC_CH1_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH1_GAMMA_PAUSE_S  5
+/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch1.\\0: Invalid. No
+ *  effect\\1: Resume
+ */
+#define LEDC_CH1_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH1_GAMMA_RESUME_M  (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S)
+#define LEDC_CH1_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH1_GAMMA_RESUME_S  6
+
+/** LEDC_CH2_GAMMA_CONF_REG register
+ *  Ledc ch2 gamma config register.
+ */
+#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108)
+/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch2.
+ */
+#define LEDC_CH2_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH2_GAMMA_ENTRY_NUM_M  (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH2_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH2_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch2.\\0: Invalid. No
+ *  effect\\1: Pause
+ */
+#define LEDC_CH2_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH2_GAMMA_PAUSE_M  (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S)
+#define LEDC_CH2_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH2_GAMMA_PAUSE_S  5
+/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch2.\\0: Invalid. No
+ *  effect\\1: Resume
+ */
+#define LEDC_CH2_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH2_GAMMA_RESUME_M  (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S)
+#define LEDC_CH2_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH2_GAMMA_RESUME_S  6
+
+/** LEDC_CH3_GAMMA_CONF_REG register
+ *  Ledc ch3 gamma config register.
+ */
+#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c)
+/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch3.
+ */
+#define LEDC_CH3_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH3_GAMMA_ENTRY_NUM_M  (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH3_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH3_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch3.\\0: Invalid. No
+ *  effect\\1: Pause
+ */
+#define LEDC_CH3_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH3_GAMMA_PAUSE_M  (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S)
+#define LEDC_CH3_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH3_GAMMA_PAUSE_S  5
+/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch3.\\0: Invalid. No
+ *  effect\\1: Resume
+ */
+#define LEDC_CH3_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH3_GAMMA_RESUME_M  (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S)
+#define LEDC_CH3_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH3_GAMMA_RESUME_S  6
+
+/** LEDC_CH4_GAMMA_CONF_REG register
+ *  Ledc ch4 gamma config register.
+ */
+#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110)
+/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch4.
+ */
+#define LEDC_CH4_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH4_GAMMA_ENTRY_NUM_M  (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH4_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH4_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch4.\\0: Invalid. No
+ *  effect\\1: Pause
+ */
+#define LEDC_CH4_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH4_GAMMA_PAUSE_M  (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S)
+#define LEDC_CH4_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH4_GAMMA_PAUSE_S  5
+/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch4.\\0: Invalid. No
+ *  effect\\1: Resume
+ */
+#define LEDC_CH4_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH4_GAMMA_RESUME_M  (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S)
+#define LEDC_CH4_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH4_GAMMA_RESUME_S  6
+
+/** LEDC_CH5_GAMMA_CONF_REG register
+ *  Ledc ch5 gamma config register.
+ */
+#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114)
+/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch5.
+ */
+#define LEDC_CH5_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH5_GAMMA_ENTRY_NUM_M  (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH5_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH5_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch5.\\0: Invalid. No
+ *  effect\\1: Pause
+ */
+#define LEDC_CH5_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH5_GAMMA_PAUSE_M  (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S)
+#define LEDC_CH5_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH5_GAMMA_PAUSE_S  5
+/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch5.\\0: Invalid. No
+ *  effect\\1: Resume
+ */
+#define LEDC_CH5_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH5_GAMMA_RESUME_M  (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S)
+#define LEDC_CH5_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH5_GAMMA_RESUME_S  6
+
+/** LEDC_CH6_GAMMA_CONF_REG register
+ *  Ledc ch6 gamma config register.
+ */
+#define LEDC_CH6_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x118)
+/** LEDC_CH6_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch6.
+ */
+#define LEDC_CH6_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH6_GAMMA_ENTRY_NUM_M  (LEDC_CH6_GAMMA_ENTRY_NUM_V << LEDC_CH6_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH6_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH6_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch6.\\0: Invalid. No
+ *  effect\\1: Pause
+ */
+#define LEDC_CH6_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH6_GAMMA_PAUSE_M  (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S)
+#define LEDC_CH6_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH6_GAMMA_PAUSE_S  5
+/** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch6.\\0: Invalid. No
+ *  effect\\1: Resume
+ */
+#define LEDC_CH6_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH6_GAMMA_RESUME_M  (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S)
+#define LEDC_CH6_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH6_GAMMA_RESUME_S  6
+
+/** LEDC_CH7_GAMMA_CONF_REG register
+ *  Ledc ch7 gamma config register.
+ */
+#define LEDC_CH7_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x11c)
+/** LEDC_CH7_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
+ *  Configures the number of duty cycle fading rages for LEDC ch7.
+ */
+#define LEDC_CH7_GAMMA_ENTRY_NUM    0x0000001FU
+#define LEDC_CH7_GAMMA_ENTRY_NUM_M  (LEDC_CH7_GAMMA_ENTRY_NUM_V << LEDC_CH7_GAMMA_ENTRY_NUM_S)
+#define LEDC_CH7_GAMMA_ENTRY_NUM_V  0x0000001FU
+#define LEDC_CH7_GAMMA_ENTRY_NUM_S  0
+/** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to pause duty cycle fading of LEDC ch7.\\0: Invalid. No
+ *  effect\\1: Pause
+ */
+#define LEDC_CH7_GAMMA_PAUSE    (BIT(5))
+#define LEDC_CH7_GAMMA_PAUSE_M  (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S)
+#define LEDC_CH7_GAMMA_PAUSE_V  0x00000001U
+#define LEDC_CH7_GAMMA_PAUSE_S  5
+/** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
+ *  Configures whether or nor to resume duty cycle fading of LEDC ch7.\\0: Invalid. No
+ *  effect\\1: Resume
+ */
+#define LEDC_CH7_GAMMA_RESUME    (BIT(6))
+#define LEDC_CH7_GAMMA_RESUME_M  (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S)
+#define LEDC_CH7_GAMMA_RESUME_V  0x00000001U
+#define LEDC_CH7_GAMMA_RESUME_S  6
+
+/** LEDC_EVT_TASK_EN0_REG register
+ *  Ledc event task enable bit register0.
+ */
+#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120)
+/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH0_EN    (BIT(0))
+#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S  0
+/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH1_EN    (BIT(1))
+#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S  1
+/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH2_EN    (BIT(2))
+#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S  2
+/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH3_EN    (BIT(3))
+#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S  3
+/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH4_EN    (BIT(4))
+#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S  4
+/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH5_EN    (BIT(5))
+#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S  5
+/** LEDC_EVT_DUTY_CHNG_END_CH6_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH6_EN    (BIT(6))
+#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH6_EN_V << LEDC_EVT_DUTY_CHNG_END_CH6_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_S  6
+/** LEDC_EVT_DUTY_CHNG_END_CH7_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_EVT_DUTY_CHNG_END_CH7_EN    (BIT(7))
+#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH7_EN_V << LEDC_EVT_DUTY_CHNG_END_CH7_EN_S)
+#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_V  0x00000001U
+#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_S  7
+/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH0_EN    (BIT(8))
+#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S  8
+/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH1_EN    (BIT(9))
+#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S  9
+/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH2_EN    (BIT(10))
+#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S  10
+/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH3_EN    (BIT(11))
+#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S  11
+/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH4_EN    (BIT(12))
+#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S  12
+/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH5_EN    (BIT(13))
+#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S  13
+/** LEDC_EVT_OVF_CNT_PLS_CH6_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH6_EN    (BIT(14))
+#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH6_EN_V << LEDC_EVT_OVF_CNT_PLS_CH6_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_S  14
+/** LEDC_EVT_OVF_CNT_PLS_CH7_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_OVF_CNT_PLS_CH7_EN    (BIT(15))
+#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH7_EN_V << LEDC_EVT_OVF_CNT_PLS_CH7_EN_S)
+#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_V  0x00000001U
+#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_S  15
+/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_TIME_OVF_TIMER0_EN    (BIT(16))
+#define LEDC_EVT_TIME_OVF_TIMER0_EN_M  (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S)
+#define LEDC_EVT_TIME_OVF_TIMER0_EN_V  0x00000001U
+#define LEDC_EVT_TIME_OVF_TIMER0_EN_S  16
+/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_TIME_OVF_TIMER1_EN    (BIT(17))
+#define LEDC_EVT_TIME_OVF_TIMER1_EN_M  (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S)
+#define LEDC_EVT_TIME_OVF_TIMER1_EN_V  0x00000001U
+#define LEDC_EVT_TIME_OVF_TIMER1_EN_S  17
+/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_TIME_OVF_TIMER2_EN    (BIT(18))
+#define LEDC_EVT_TIME_OVF_TIMER2_EN_M  (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S)
+#define LEDC_EVT_TIME_OVF_TIMER2_EN_V  0x00000001U
+#define LEDC_EVT_TIME_OVF_TIMER2_EN_S  18
+/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_TIME_OVF_TIMER3_EN    (BIT(19))
+#define LEDC_EVT_TIME_OVF_TIMER3_EN_M  (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S)
+#define LEDC_EVT_TIME_OVF_TIMER3_EN_V  0x00000001U
+#define LEDC_EVT_TIME_OVF_TIMER3_EN_S  19
+/** LEDC_EVT_TIMER0_CMP_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_TIMER0_CMP_EN    (BIT(20))
+#define LEDC_EVT_TIMER0_CMP_EN_M  (LEDC_EVT_TIMER0_CMP_EN_V << LEDC_EVT_TIMER0_CMP_EN_S)
+#define LEDC_EVT_TIMER0_CMP_EN_V  0x00000001U
+#define LEDC_EVT_TIMER0_CMP_EN_S  20
+/** LEDC_EVT_TIMER1_CMP_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_TIMER1_CMP_EN    (BIT(21))
+#define LEDC_EVT_TIMER1_CMP_EN_M  (LEDC_EVT_TIMER1_CMP_EN_V << LEDC_EVT_TIMER1_CMP_EN_S)
+#define LEDC_EVT_TIMER1_CMP_EN_V  0x00000001U
+#define LEDC_EVT_TIMER1_CMP_EN_S  21
+/** LEDC_EVT_TIMER2_CMP_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_TIMER2_CMP_EN    (BIT(22))
+#define LEDC_EVT_TIMER2_CMP_EN_M  (LEDC_EVT_TIMER2_CMP_EN_V << LEDC_EVT_TIMER2_CMP_EN_S)
+#define LEDC_EVT_TIMER2_CMP_EN_V  0x00000001U
+#define LEDC_EVT_TIMER2_CMP_EN_S  22
+/** LEDC_EVT_TIMER3_CMP_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_EVT_TIMER3_CMP_EN    (BIT(23))
+#define LEDC_EVT_TIMER3_CMP_EN_M  (LEDC_EVT_TIMER3_CMP_EN_V << LEDC_EVT_TIMER3_CMP_EN_S)
+#define LEDC_EVT_TIMER3_CMP_EN_V  0x00000001U
+#define LEDC_EVT_TIMER3_CMP_EN_S  23
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0;
+ *  Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN    (BIT(24))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S  24
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN    (BIT(25))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S  25
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0;
+ *  Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN    (BIT(26))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S  26
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN    (BIT(27))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S  27
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN    (BIT(28))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S  28
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN    (BIT(29))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S  29
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN : R/W; bitpos: [30]; default: 0;
+ *  Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN    (BIT(30))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S  30
+/** LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0:
+ *  Disable\\1: Enable
+ */
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN    (BIT(31))
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S)
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V  0x00000001U
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S  31
+
+/** LEDC_EVT_TASK_EN1_REG register
+ *  Ledc event task enable bit register1.
+ */
+#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124)
+/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_TIMER0_RES_UPDATE_EN    (BIT(0))
+#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M  (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S)
+#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V  0x00000001U
+#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S  0
+/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_TIMER1_RES_UPDATE_EN    (BIT(1))
+#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M  (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S)
+#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V  0x00000001U
+#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S  1
+/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_TIMER2_RES_UPDATE_EN    (BIT(2))
+#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M  (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S)
+#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V  0x00000001U
+#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S  2
+/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_TIMER3_RES_UPDATE_EN    (BIT(3))
+#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M  (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S)
+#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V  0x00000001U
+#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S  3
+/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable
+ */
+#define LEDC_TASK_TIMER0_CAP_EN    (BIT(4))
+#define LEDC_TASK_TIMER0_CAP_EN_M  (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S)
+#define LEDC_TASK_TIMER0_CAP_EN_V  0x00000001U
+#define LEDC_TASK_TIMER0_CAP_EN_S  4
+/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable
+ */
+#define LEDC_TASK_TIMER1_CAP_EN    (BIT(5))
+#define LEDC_TASK_TIMER1_CAP_EN_M  (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S)
+#define LEDC_TASK_TIMER1_CAP_EN_V  0x00000001U
+#define LEDC_TASK_TIMER1_CAP_EN_S  5
+/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable
+ */
+#define LEDC_TASK_TIMER2_CAP_EN    (BIT(6))
+#define LEDC_TASK_TIMER2_CAP_EN_M  (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S)
+#define LEDC_TASK_TIMER2_CAP_EN_V  0x00000001U
+#define LEDC_TASK_TIMER2_CAP_EN_S  6
+/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable
+ */
+#define LEDC_TASK_TIMER3_CAP_EN    (BIT(7))
+#define LEDC_TASK_TIMER3_CAP_EN_M  (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S)
+#define LEDC_TASK_TIMER3_CAP_EN_V  0x00000001U
+#define LEDC_TASK_TIMER3_CAP_EN_S  7
+/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH0_EN    (BIT(8))
+#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S  8
+/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH1_EN    (BIT(9))
+#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S  9
+/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH2_EN    (BIT(10))
+#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S  10
+/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH3_EN    (BIT(11))
+#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S  11
+/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH4_EN    (BIT(12))
+#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S  12
+/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH5_EN    (BIT(13))
+#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S  13
+/** LEDC_TASK_SIG_OUT_DIS_CH6_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH6_EN    (BIT(14))
+#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH6_EN_V << LEDC_TASK_SIG_OUT_DIS_CH6_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_S  14
+/** LEDC_TASK_SIG_OUT_DIS_CH7_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_SIG_OUT_DIS_CH7_EN    (BIT(15))
+#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH7_EN_V << LEDC_TASK_SIG_OUT_DIS_CH7_EN_S)
+#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_V  0x00000001U
+#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_S  15
+/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH0_EN    (BIT(16))
+#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M  (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S  16
+/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH1_EN    (BIT(17))
+#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M  (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S  17
+/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH2_EN    (BIT(18))
+#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M  (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S  18
+/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH3_EN    (BIT(19))
+#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M  (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S  19
+/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH4_EN    (BIT(20))
+#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M  (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S  20
+/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH5_EN    (BIT(21))
+#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M  (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S  21
+/** LEDC_TASK_OVF_CNT_RST_CH6_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH6_EN    (BIT(22))
+#define LEDC_TASK_OVF_CNT_RST_CH6_EN_M  (LEDC_TASK_OVF_CNT_RST_CH6_EN_V << LEDC_TASK_OVF_CNT_RST_CH6_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH6_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH6_EN_S  22
+/** LEDC_TASK_OVF_CNT_RST_CH7_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_OVF_CNT_RST_CH7_EN    (BIT(23))
+#define LEDC_TASK_OVF_CNT_RST_CH7_EN_M  (LEDC_TASK_OVF_CNT_RST_CH7_EN_V << LEDC_TASK_OVF_CNT_RST_CH7_EN_S)
+#define LEDC_TASK_OVF_CNT_RST_CH7_EN_V  0x00000001U
+#define LEDC_TASK_OVF_CNT_RST_CH7_EN_S  23
+/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0;
+ *  Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable
+ */
+#define LEDC_TASK_TIMER0_RST_EN    (BIT(24))
+#define LEDC_TASK_TIMER0_RST_EN_M  (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S)
+#define LEDC_TASK_TIMER0_RST_EN_V  0x00000001U
+#define LEDC_TASK_TIMER0_RST_EN_S  24
+/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable
+ */
+#define LEDC_TASK_TIMER1_RST_EN    (BIT(25))
+#define LEDC_TASK_TIMER1_RST_EN_M  (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S)
+#define LEDC_TASK_TIMER1_RST_EN_V  0x00000001U
+#define LEDC_TASK_TIMER1_RST_EN_S  25
+/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0;
+ *  Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable
+ */
+#define LEDC_TASK_TIMER2_RST_EN    (BIT(26))
+#define LEDC_TASK_TIMER2_RST_EN_M  (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S)
+#define LEDC_TASK_TIMER2_RST_EN_V  0x00000001U
+#define LEDC_TASK_TIMER2_RST_EN_S  26
+/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable
+ */
+#define LEDC_TASK_TIMER3_RST_EN    (BIT(27))
+#define LEDC_TASK_TIMER3_RST_EN_M  (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S)
+#define LEDC_TASK_TIMER3_RST_EN_V  0x00000001U
+#define LEDC_TASK_TIMER3_RST_EN_S  27
+/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN    (BIT(28))
+#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S)
+#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V  0x00000001U
+#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S  28
+/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN    (BIT(29))
+#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S)
+#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V  0x00000001U
+#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S  29
+/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0;
+ *  Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN    (BIT(30))
+#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S)
+#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V  0x00000001U
+#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S  30
+/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN    (BIT(31))
+#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S)
+#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V  0x00000001U
+#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S  31
+
+/** LEDC_EVT_TASK_EN2_REG register
+ *  Ledc event task enable bit register2.
+ */
+#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128)
+/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH0_EN    (BIT(0))
+#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M  (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S  0
+/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH1_EN    (BIT(1))
+#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M  (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S  1
+/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH2_EN    (BIT(2))
+#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M  (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S  2
+/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH3_EN    (BIT(3))
+#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M  (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S  3
+/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH4_EN    (BIT(4))
+#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M  (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S  4
+/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH5_EN    (BIT(5))
+#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M  (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S  5
+/** LEDC_TASK_GAMMA_RESTART_CH6_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH6_EN    (BIT(6))
+#define LEDC_TASK_GAMMA_RESTART_CH6_EN_M  (LEDC_TASK_GAMMA_RESTART_CH6_EN_V << LEDC_TASK_GAMMA_RESTART_CH6_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH6_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH6_EN_S  6
+/** LEDC_TASK_GAMMA_RESTART_CH7_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESTART_CH7_EN    (BIT(7))
+#define LEDC_TASK_GAMMA_RESTART_CH7_EN_M  (LEDC_TASK_GAMMA_RESTART_CH7_EN_V << LEDC_TASK_GAMMA_RESTART_CH7_EN_S)
+#define LEDC_TASK_GAMMA_RESTART_CH7_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESTART_CH7_EN_S  7
+/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH0_EN    (BIT(8))
+#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S  8
+/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH1_EN    (BIT(9))
+#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S  9
+/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH2_EN    (BIT(10))
+#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S  10
+/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH3_EN    (BIT(11))
+#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S  11
+/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH4_EN    (BIT(12))
+#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S  12
+/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH5_EN    (BIT(13))
+#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S  13
+/** LEDC_TASK_GAMMA_PAUSE_CH6_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH6_EN    (BIT(14))
+#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH6_EN_V << LEDC_TASK_GAMMA_PAUSE_CH6_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_S  14
+/** LEDC_TASK_GAMMA_PAUSE_CH7_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_PAUSE_CH7_EN    (BIT(15))
+#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH7_EN_V << LEDC_TASK_GAMMA_PAUSE_CH7_EN_S)
+#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_S  15
+/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH0_EN    (BIT(16))
+#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M  (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S  16
+/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH1_EN    (BIT(17))
+#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M  (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S  17
+/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH2_EN    (BIT(18))
+#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M  (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S  18
+/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH3_EN    (BIT(19))
+#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M  (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S  19
+/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH4_EN    (BIT(20))
+#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M  (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S  20
+/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH5_EN    (BIT(21))
+#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M  (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S  21
+/** LEDC_TASK_GAMMA_RESUME_CH6_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH6_EN    (BIT(22))
+#define LEDC_TASK_GAMMA_RESUME_CH6_EN_M  (LEDC_TASK_GAMMA_RESUME_CH6_EN_V << LEDC_TASK_GAMMA_RESUME_CH6_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH6_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH6_EN_S  22
+/** LEDC_TASK_GAMMA_RESUME_CH7_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1:
+ *  Enable
+ */
+#define LEDC_TASK_GAMMA_RESUME_CH7_EN    (BIT(23))
+#define LEDC_TASK_GAMMA_RESUME_CH7_EN_M  (LEDC_TASK_GAMMA_RESUME_CH7_EN_V << LEDC_TASK_GAMMA_RESUME_CH7_EN_S)
+#define LEDC_TASK_GAMMA_RESUME_CH7_EN_V  0x00000001U
+#define LEDC_TASK_GAMMA_RESUME_CH7_EN_S  23
+
+/** LEDC_TIMER0_CMP_REG register
+ *  Ledc timer0 compare value register.
+ */
+#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140)
+/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0;
+ *  Configures the comparison value for LEDC timer0.
+ */
+#define LEDC_TIMER0_CMP    0x000FFFFFU
+#define LEDC_TIMER0_CMP_M  (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S)
+#define LEDC_TIMER0_CMP_V  0x000FFFFFU
+#define LEDC_TIMER0_CMP_S  0
+
+/** LEDC_TIMER1_CMP_REG register
+ *  Ledc timer1 compare value register.
+ */
+#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144)
+/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0;
+ *  Configures the comparison value for LEDC timer1.
+ */
+#define LEDC_TIMER1_CMP    0x000FFFFFU
+#define LEDC_TIMER1_CMP_M  (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S)
+#define LEDC_TIMER1_CMP_V  0x000FFFFFU
+#define LEDC_TIMER1_CMP_S  0
+
+/** LEDC_TIMER2_CMP_REG register
+ *  Ledc timer2 compare value register.
+ */
+#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148)
+/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0;
+ *  Configures the comparison value for LEDC timer2.
+ */
+#define LEDC_TIMER2_CMP    0x000FFFFFU
+#define LEDC_TIMER2_CMP_M  (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S)
+#define LEDC_TIMER2_CMP_V  0x000FFFFFU
+#define LEDC_TIMER2_CMP_S  0
+
+/** LEDC_TIMER3_CMP_REG register
+ *  Ledc timer3 compare value register.
+ */
+#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c)
+/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0;
+ *  Configures the comparison value for LEDC timer3.
+ */
+#define LEDC_TIMER3_CMP    0x000FFFFFU
+#define LEDC_TIMER3_CMP_M  (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S)
+#define LEDC_TIMER3_CMP_V  0x000FFFFFU
+#define LEDC_TIMER3_CMP_S  0
+
+/** LEDC_TIMER0_CNT_CAP_REG register
+ *  Ledc timer0 captured count value register.
+ */
+#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150)
+/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0;
+ *  Represents the captured LEDC timer0 count value.
+ */
+#define LEDC_TIMER0_CNT_CAP    0x000FFFFFU
+#define LEDC_TIMER0_CNT_CAP_M  (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S)
+#define LEDC_TIMER0_CNT_CAP_V  0x000FFFFFU
+#define LEDC_TIMER0_CNT_CAP_S  0
+
+/** LEDC_TIMER1_CNT_CAP_REG register
+ *  Ledc timer1 captured count value register.
+ */
+#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154)
+/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0;
+ *  Represents the captured LEDC timer1 count value.
+ */
+#define LEDC_TIMER1_CNT_CAP    0x000FFFFFU
+#define LEDC_TIMER1_CNT_CAP_M  (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S)
+#define LEDC_TIMER1_CNT_CAP_V  0x000FFFFFU
+#define LEDC_TIMER1_CNT_CAP_S  0
+
+/** LEDC_TIMER2_CNT_CAP_REG register
+ *  Ledc timer2 captured count value register.
+ */
+#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158)
+/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0;
+ *  Represents the captured LEDC timer2 count value.
+ */
+#define LEDC_TIMER2_CNT_CAP    0x000FFFFFU
+#define LEDC_TIMER2_CNT_CAP_M  (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S)
+#define LEDC_TIMER2_CNT_CAP_V  0x000FFFFFU
+#define LEDC_TIMER2_CNT_CAP_S  0
+
+/** LEDC_TIMER3_CNT_CAP_REG register
+ *  Ledc timer3 captured count value register.
+ */
+#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c)
+/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0;
+ *  Represents the captured LEDC timer3 count value.
+ */
+#define LEDC_TIMER3_CNT_CAP    0x000FFFFFU
+#define LEDC_TIMER3_CNT_CAP_M  (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S)
+#define LEDC_TIMER3_CNT_CAP_V  0x000FFFFFU
+#define LEDC_TIMER3_CNT_CAP_S  0
+
+/** LEDC_CONF_REG register
+ *  LEDC global configuration register
+ */
+#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170)
+/** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2:
+ *  XTAL_CLK\\3: Invalid. No clock
+ */
+#define LEDC_APB_CLK_SEL    0x00000003U
+#define LEDC_APB_CLK_SEL_M  (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S)
+#define LEDC_APB_CLK_SEL_V  0x00000003U
+#define LEDC_APB_CLK_SEL_S  0
+/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock
+ *  gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the
+ *  clock gate for LEDC ch0 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH0    (BIT(2))
+#define LEDC_GAMMA_RAM_CLK_EN_CH0_M  (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH0_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH0_S  2
+/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock
+ *  gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the
+ *  clock gate for LEDC ch1 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH1    (BIT(3))
+#define LEDC_GAMMA_RAM_CLK_EN_CH1_M  (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH1_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH1_S  3
+/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock
+ *  gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the
+ *  clock gate for LEDC ch2 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH2    (BIT(4))
+#define LEDC_GAMMA_RAM_CLK_EN_CH2_M  (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH2_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH2_S  4
+/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock
+ *  gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the
+ *  clock gate for LEDC ch3 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH3    (BIT(5))
+#define LEDC_GAMMA_RAM_CLK_EN_CH3_M  (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH3_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH3_S  5
+/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock
+ *  gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the
+ *  clock gate for LEDC ch4 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH4    (BIT(6))
+#define LEDC_GAMMA_RAM_CLK_EN_CH4_M  (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH4_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH4_S  6
+/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock
+ *  gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the
+ *  clock gate for LEDC ch5 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH5    (BIT(7))
+#define LEDC_GAMMA_RAM_CLK_EN_CH5_M  (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH5_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH5_S  7
+/** LEDC_GAMMA_RAM_CLK_EN_CH6 : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock
+ *  gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the
+ *  clock gate for LEDC ch6 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH6    (BIT(8))
+#define LEDC_GAMMA_RAM_CLK_EN_CH6_M  (LEDC_GAMMA_RAM_CLK_EN_CH6_V << LEDC_GAMMA_RAM_CLK_EN_CH6_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH6_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH6_S  8
+/** LEDC_GAMMA_RAM_CLK_EN_CH7 : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock
+ *  gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the
+ *  clock gate for LEDC ch7 gamma ram
+ */
+#define LEDC_GAMMA_RAM_CLK_EN_CH7    (BIT(9))
+#define LEDC_GAMMA_RAM_CLK_EN_CH7_M  (LEDC_GAMMA_RAM_CLK_EN_CH7_V << LEDC_GAMMA_RAM_CLK_EN_CH7_S)
+#define LEDC_GAMMA_RAM_CLK_EN_CH7_V  0x00000001U
+#define LEDC_GAMMA_RAM_CLK_EN_CH7_S  9
+/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
+ *  when application writes registers\\1: Force open the clock gate for register
+ */
+#define LEDC_CLK_EN    (BIT(31))
+#define LEDC_CLK_EN_M  (LEDC_CLK_EN_V << LEDC_CLK_EN_S)
+#define LEDC_CLK_EN_V  0x00000001U
+#define LEDC_CLK_EN_S  31
+
+/** LEDC_DATE_REG register
+ *  Version control register
+ */
+#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174)
+/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 36712560;
+ *  Configures the version.
+ */
+#define LEDC_LEDC_DATE    0x0FFFFFFFU
+#define LEDC_LEDC_DATE_M  (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S)
+#define LEDC_LEDC_DATE_V  0x0FFFFFFFU
+#define LEDC_LEDC_DATE_S  0
+
+/** LEDC gamma fade config ram registers
+ *  16 words (32bit) per channel * 8 channels
+ */
+#define LEDC_CH0_GAMMA_RANGE0_REG  (DR_REG_LEDC_BASE + 0x400)
+/* LEDC_CH0_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE0_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE0_SCALE_M  ((LEDC_CH0_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE0_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE0_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE0_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE1_REG  (DR_REG_LEDC_BASE + 0x404)
+/* LEDC_CH0_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE1_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE1_SCALE_M  ((LEDC_CH0_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE1_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE1_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE1_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE2_REG  (DR_REG_LEDC_BASE + 0x408)
+/* LEDC_CH0_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE2_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE2_SCALE_M  ((LEDC_CH0_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE2_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE2_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE2_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE3_REG  (DR_REG_LEDC_BASE + 0x40c)
+/* LEDC_CH0_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE3_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE3_SCALE_M  ((LEDC_CH0_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE3_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE3_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE3_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE4_REG  (DR_REG_LEDC_BASE + 0x410)
+/* LEDC_CH0_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE4_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE4_SCALE_M  ((LEDC_CH0_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE4_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE4_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE4_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE5_REG  (DR_REG_LEDC_BASE + 0x414)
+/* LEDC_CH0_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE5_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE5_SCALE_M  ((LEDC_CH0_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE5_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE5_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE5_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE6_REG  (DR_REG_LEDC_BASE + 0x418)
+/* LEDC_CH0_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE6_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE6_SCALE_M  ((LEDC_CH0_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE6_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE6_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE6_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE7_REG  (DR_REG_LEDC_BASE + 0x41c)
+/* LEDC_CH0_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE7_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE7_SCALE_M  ((LEDC_CH0_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE7_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE7_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE7_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE8_REG  (DR_REG_LEDC_BASE + 0x420)
+/* LEDC_CH0_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE8_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE8_SCALE_M  ((LEDC_CH0_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE8_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE8_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE8_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE9_REG  (DR_REG_LEDC_BASE + 0x424)
+/* LEDC_CH0_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE9_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE9_SCALE_M  ((LEDC_CH0_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE9_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE9_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE9_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE10_REG  (DR_REG_LEDC_BASE + 0x428)
+/* LEDC_CH0_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE10_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE10_SCALE_M  ((LEDC_CH0_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE10_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE10_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE10_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE11_REG  (DR_REG_LEDC_BASE + 0x42c)
+/* LEDC_CH0_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE11_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE11_SCALE_M  ((LEDC_CH0_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE11_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE11_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE11_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE12_REG  (DR_REG_LEDC_BASE + 0x430)
+/* LEDC_CH0_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE12_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE12_SCALE_M  ((LEDC_CH0_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE12_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE12_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE12_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE13_REG  (DR_REG_LEDC_BASE + 0x434)
+/* LEDC_CH0_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE13_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE13_SCALE_M  ((LEDC_CH0_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE13_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE13_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE13_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE14_REG  (DR_REG_LEDC_BASE + 0x438)
+/* LEDC_CH0_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE14_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE14_SCALE_M  ((LEDC_CH0_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE14_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE14_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE14_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC_S  0
+
+#define LEDC_CH0_GAMMA_RANGE15_REG  (DR_REG_LEDC_BASE + 0x43c)
+/* LEDC_CH0_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_M  ((LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_S))
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_S  21
+/* LEDC_CH0_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE15_SCALE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE15_SCALE_M  ((LEDC_CH0_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE15_SCALE_S))
+#define LEDC_CH0_GAMMA_RANGE15_SCALE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE15_SCALE_S  11
+/* LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE    0x000003FF
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_M  ((LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_S))
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_S  1
+/* LEDC_CH0_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC    (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC_M  (BIT(0))
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC_V  0x1
+#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC_S  0
+
+
+#define LEDC_CH1_GAMMA_RANGE0_REG  (DR_REG_LEDC_BASE + 0x440)
+/* LEDC_CH1_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE0_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE0_SCALE_M  ((LEDC_CH1_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE0_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE0_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE0_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE1_REG  (DR_REG_LEDC_BASE + 0x444)
+/* LEDC_CH1_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE1_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE1_SCALE_M  ((LEDC_CH1_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE1_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE1_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE1_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE2_REG  (DR_REG_LEDC_BASE + 0x448)
+/* LEDC_CH1_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE2_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE2_SCALE_M  ((LEDC_CH1_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE2_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE2_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE2_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE3_REG  (DR_REG_LEDC_BASE + 0x44c)
+/* LEDC_CH1_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE3_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE3_SCALE_M  ((LEDC_CH1_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE3_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE3_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE3_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE4_REG  (DR_REG_LEDC_BASE + 0x450)
+/* LEDC_CH1_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE4_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE4_SCALE_M  ((LEDC_CH1_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE4_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE4_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE4_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE5_REG  (DR_REG_LEDC_BASE + 0x454)
+/* LEDC_CH1_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE5_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE5_SCALE_M  ((LEDC_CH1_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE5_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE5_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE5_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE6_REG  (DR_REG_LEDC_BASE + 0x458)
+/* LEDC_CH1_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE6_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE6_SCALE_M  ((LEDC_CH1_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE6_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE6_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE6_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE7_REG  (DR_REG_LEDC_BASE + 0x45c)
+/* LEDC_CH1_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE7_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE7_SCALE_M  ((LEDC_CH1_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE7_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE7_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE7_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE8_REG  (DR_REG_LEDC_BASE + 0x460)
+/* LEDC_CH1_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE8_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE8_SCALE_M  ((LEDC_CH1_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE8_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE8_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE8_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE9_REG  (DR_REG_LEDC_BASE + 0x464)
+/* LEDC_CH1_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE9_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE9_SCALE_M  ((LEDC_CH1_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE9_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE9_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE9_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE10_REG  (DR_REG_LEDC_BASE + 0x468)
+/* LEDC_CH1_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE10_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE10_SCALE_M  ((LEDC_CH1_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE10_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE10_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE10_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE11_REG  (DR_REG_LEDC_BASE + 0x46c)
+/* LEDC_CH1_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE11_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE11_SCALE_M  ((LEDC_CH1_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE11_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE11_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE11_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE12_REG  (DR_REG_LEDC_BASE + 0x470)
+/* LEDC_CH1_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE12_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE12_SCALE_M  ((LEDC_CH1_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE12_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE12_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE12_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE13_REG  (DR_REG_LEDC_BASE + 0x474)
+/* LEDC_CH1_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE13_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE13_SCALE_M  ((LEDC_CH1_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE13_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE13_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE13_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE14_REG  (DR_REG_LEDC_BASE + 0x478)
+/* LEDC_CH1_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE14_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE14_SCALE_M  ((LEDC_CH1_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE14_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE14_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE14_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC_S  0
+
+#define LEDC_CH1_GAMMA_RANGE15_REG  (DR_REG_LEDC_BASE + 0x47c)
+/* LEDC_CH1_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_M  ((LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_S))
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_S  21
+/* LEDC_CH1_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE15_SCALE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE15_SCALE_M  ((LEDC_CH1_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE15_SCALE_S))
+#define LEDC_CH1_GAMMA_RANGE15_SCALE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE15_SCALE_S  11
+/* LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE    0x000003FF
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_M  ((LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_S))
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_S  1
+/* LEDC_CH1_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC    (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC_M  (BIT(0))
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC_V  0x1
+#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC_S  0
+
+
+#define LEDC_CH2_GAMMA_RANGE0_REG  (DR_REG_LEDC_BASE + 0x480)
+/* LEDC_CH2_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE0_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE0_SCALE_M  ((LEDC_CH2_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE0_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE0_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE0_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE1_REG  (DR_REG_LEDC_BASE + 0x484)
+/* LEDC_CH2_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE1_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE1_SCALE_M  ((LEDC_CH2_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE1_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE1_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE1_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE2_REG  (DR_REG_LEDC_BASE + 0x488)
+/* LEDC_CH2_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE2_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE2_SCALE_M  ((LEDC_CH2_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE2_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE2_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE2_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE3_REG  (DR_REG_LEDC_BASE + 0x48c)
+/* LEDC_CH2_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE3_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE3_SCALE_M  ((LEDC_CH2_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE3_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE3_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE3_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE4_REG  (DR_REG_LEDC_BASE + 0x490)
+/* LEDC_CH2_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE4_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE4_SCALE_M  ((LEDC_CH2_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE4_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE4_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE4_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE5_REG  (DR_REG_LEDC_BASE + 0x494)
+/* LEDC_CH2_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE5_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE5_SCALE_M  ((LEDC_CH2_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE5_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE5_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE5_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE6_REG  (DR_REG_LEDC_BASE + 0x498)
+/* LEDC_CH2_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE6_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE6_SCALE_M  ((LEDC_CH2_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE6_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE6_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE6_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE7_REG  (DR_REG_LEDC_BASE + 0x49c)
+/* LEDC_CH2_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE7_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE7_SCALE_M  ((LEDC_CH2_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE7_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE7_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE7_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE8_REG  (DR_REG_LEDC_BASE + 0x4a0)
+/* LEDC_CH2_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE8_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE8_SCALE_M  ((LEDC_CH2_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE8_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE8_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE8_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE9_REG  (DR_REG_LEDC_BASE + 0x4a4)
+/* LEDC_CH2_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE9_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE9_SCALE_M  ((LEDC_CH2_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE9_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE9_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE9_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE10_REG  (DR_REG_LEDC_BASE + 0x4a8)
+/* LEDC_CH2_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE10_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE10_SCALE_M  ((LEDC_CH2_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE10_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE10_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE10_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE11_REG  (DR_REG_LEDC_BASE + 0x4ac)
+/* LEDC_CH2_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE11_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE11_SCALE_M  ((LEDC_CH2_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE11_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE11_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE11_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE12_REG  (DR_REG_LEDC_BASE + 0x4b0)
+/* LEDC_CH2_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE12_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE12_SCALE_M  ((LEDC_CH2_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE12_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE12_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE12_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE13_REG  (DR_REG_LEDC_BASE + 0x4b4)
+/* LEDC_CH2_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE13_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE13_SCALE_M  ((LEDC_CH2_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE13_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE13_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE13_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE14_REG  (DR_REG_LEDC_BASE + 0x4b8)
+/* LEDC_CH2_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE14_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE14_SCALE_M  ((LEDC_CH2_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE14_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE14_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE14_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC_S  0
+
+#define LEDC_CH2_GAMMA_RANGE15_REG  (DR_REG_LEDC_BASE + 0x4bc)
+/* LEDC_CH2_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_M  ((LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_S))
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_S  21
+/* LEDC_CH2_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE15_SCALE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE15_SCALE_M  ((LEDC_CH2_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE15_SCALE_S))
+#define LEDC_CH2_GAMMA_RANGE15_SCALE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE15_SCALE_S  11
+/* LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE    0x000003FF
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_M  ((LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_S))
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_S  1
+/* LEDC_CH2_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC    (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC_M  (BIT(0))
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC_V  0x1
+#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC_S  0
+
+
+#define LEDC_CH3_GAMMA_RANGE0_REG  (DR_REG_LEDC_BASE + 0x4c0)
+/* LEDC_CH3_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE0_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE0_SCALE_M  ((LEDC_CH3_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE0_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE0_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE0_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE1_REG  (DR_REG_LEDC_BASE + 0x4c4)
+/* LEDC_CH3_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE1_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE1_SCALE_M  ((LEDC_CH3_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE1_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE1_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE1_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE2_REG  (DR_REG_LEDC_BASE + 0x4c8)
+/* LEDC_CH3_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE2_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE2_SCALE_M  ((LEDC_CH3_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE2_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE2_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE2_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE3_REG  (DR_REG_LEDC_BASE + 0x4cc)
+/* LEDC_CH3_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE3_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE3_SCALE_M  ((LEDC_CH3_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE3_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE3_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE3_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE4_REG  (DR_REG_LEDC_BASE + 0x4d0)
+/* LEDC_CH3_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE4_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE4_SCALE_M  ((LEDC_CH3_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE4_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE4_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE4_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE5_REG  (DR_REG_LEDC_BASE + 0x4d4)
+/* LEDC_CH3_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE5_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE5_SCALE_M  ((LEDC_CH3_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE5_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE5_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE5_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE6_REG  (DR_REG_LEDC_BASE + 0x4d8)
+/* LEDC_CH3_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE6_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE6_SCALE_M  ((LEDC_CH3_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE6_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE6_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE6_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE7_REG  (DR_REG_LEDC_BASE + 0x4dc)
+/* LEDC_CH3_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE7_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE7_SCALE_M  ((LEDC_CH3_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE7_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE7_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE7_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE8_REG  (DR_REG_LEDC_BASE + 0x4e0)
+/* LEDC_CH3_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE8_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE8_SCALE_M  ((LEDC_CH3_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE8_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE8_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE8_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE9_REG  (DR_REG_LEDC_BASE + 0x4e4)
+/* LEDC_CH3_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE9_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE9_SCALE_M  ((LEDC_CH3_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE9_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE9_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE9_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE10_REG  (DR_REG_LEDC_BASE + 0x4e8)
+/* LEDC_CH3_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE10_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE10_SCALE_M  ((LEDC_CH3_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE10_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE10_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE10_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE11_REG  (DR_REG_LEDC_BASE + 0x4ec)
+/* LEDC_CH3_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE11_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE11_SCALE_M  ((LEDC_CH3_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE11_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE11_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE11_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE12_REG  (DR_REG_LEDC_BASE + 0x4f0)
+/* LEDC_CH3_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE12_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE12_SCALE_M  ((LEDC_CH3_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE12_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE12_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE12_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE13_REG  (DR_REG_LEDC_BASE + 0x4f4)
+/* LEDC_CH3_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE13_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE13_SCALE_M  ((LEDC_CH3_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE13_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE13_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE13_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE14_REG  (DR_REG_LEDC_BASE + 0x4f8)
+/* LEDC_CH3_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE14_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE14_SCALE_M  ((LEDC_CH3_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE14_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE14_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE14_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC_S  0
+
+#define LEDC_CH3_GAMMA_RANGE15_REG  (DR_REG_LEDC_BASE + 0x4fc)
+/* LEDC_CH3_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_M  ((LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_S))
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_S  21
+/* LEDC_CH3_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE15_SCALE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE15_SCALE_M  ((LEDC_CH3_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE15_SCALE_S))
+#define LEDC_CH3_GAMMA_RANGE15_SCALE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE15_SCALE_S  11
+/* LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE    0x000003FF
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_M  ((LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_S))
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_S  1
+/* LEDC_CH3_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC    (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC_M  (BIT(0))
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC_V  0x1
+#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC_S  0
+
+
+#define LEDC_CH4_GAMMA_RANGE0_REG  (DR_REG_LEDC_BASE + 0x500)
+/* LEDC_CH4_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE0_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE0_SCALE_M  ((LEDC_CH4_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE0_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE0_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE0_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE1_REG  (DR_REG_LEDC_BASE + 0x504)
+/* LEDC_CH4_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE1_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE1_SCALE_M  ((LEDC_CH4_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE1_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE1_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE1_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE2_REG  (DR_REG_LEDC_BASE + 0x508)
+/* LEDC_CH4_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE2_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE2_SCALE_M  ((LEDC_CH4_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE2_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE2_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE2_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE3_REG  (DR_REG_LEDC_BASE + 0x50c)
+/* LEDC_CH4_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE3_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE3_SCALE_M  ((LEDC_CH4_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE3_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE3_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE3_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE4_REG  (DR_REG_LEDC_BASE + 0x510)
+/* LEDC_CH4_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE4_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE4_SCALE_M  ((LEDC_CH4_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE4_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE4_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE4_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE5_REG  (DR_REG_LEDC_BASE + 0x514)
+/* LEDC_CH4_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE5_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE5_SCALE_M  ((LEDC_CH4_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE5_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE5_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE5_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE6_REG  (DR_REG_LEDC_BASE + 0x518)
+/* LEDC_CH4_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE6_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE6_SCALE_M  ((LEDC_CH4_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE6_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE6_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE6_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE7_REG  (DR_REG_LEDC_BASE + 0x51c)
+/* LEDC_CH4_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE7_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE7_SCALE_M  ((LEDC_CH4_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE7_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE7_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE7_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE8_REG  (DR_REG_LEDC_BASE + 0x520)
+/* LEDC_CH4_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE8_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE8_SCALE_M  ((LEDC_CH4_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE8_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE8_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE8_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE9_REG  (DR_REG_LEDC_BASE + 0x524)
+/* LEDC_CH4_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE9_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE9_SCALE_M  ((LEDC_CH4_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE9_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE9_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE9_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE10_REG  (DR_REG_LEDC_BASE + 0x528)
+/* LEDC_CH4_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE10_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE10_SCALE_M  ((LEDC_CH4_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE10_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE10_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE10_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE11_REG  (DR_REG_LEDC_BASE + 0x52c)
+/* LEDC_CH4_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE11_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE11_SCALE_M  ((LEDC_CH4_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE11_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE11_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE11_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE12_REG  (DR_REG_LEDC_BASE + 0x530)
+/* LEDC_CH4_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE12_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE12_SCALE_M  ((LEDC_CH4_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE12_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE12_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE12_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE13_REG  (DR_REG_LEDC_BASE + 0x534)
+/* LEDC_CH4_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE13_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE13_SCALE_M  ((LEDC_CH4_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE13_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE13_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE13_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE14_REG  (DR_REG_LEDC_BASE + 0x538)
+/* LEDC_CH4_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE14_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE14_SCALE_M  ((LEDC_CH4_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE14_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE14_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE14_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC_S  0
+
+#define LEDC_CH4_GAMMA_RANGE15_REG  (DR_REG_LEDC_BASE + 0x53c)
+/* LEDC_CH4_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_M  ((LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_S))
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_S  21
+/* LEDC_CH4_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE15_SCALE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE15_SCALE_M  ((LEDC_CH4_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE15_SCALE_S))
+#define LEDC_CH4_GAMMA_RANGE15_SCALE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE15_SCALE_S  11
+/* LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE    0x000003FF
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_M  ((LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_S))
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_S  1
+/* LEDC_CH4_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC    (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC_M  (BIT(0))
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC_V  0x1
+#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC_S  0
+
+
+#define LEDC_CH5_GAMMA_RANGE0_REG  (DR_REG_LEDC_BASE + 0x540)
+/* LEDC_CH5_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE0_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE0_SCALE_M  ((LEDC_CH5_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE0_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE0_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE0_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE1_REG  (DR_REG_LEDC_BASE + 0x544)
+/* LEDC_CH5_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE1_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE1_SCALE_M  ((LEDC_CH5_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE1_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE1_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE1_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE2_REG  (DR_REG_LEDC_BASE + 0x548)
+/* LEDC_CH5_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE2_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE2_SCALE_M  ((LEDC_CH5_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE2_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE2_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE2_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE3_REG  (DR_REG_LEDC_BASE + 0x54c)
+/* LEDC_CH5_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE3_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE3_SCALE_M  ((LEDC_CH5_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE3_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE3_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE3_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE4_REG  (DR_REG_LEDC_BASE + 0x550)
+/* LEDC_CH5_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE4_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE4_SCALE_M  ((LEDC_CH5_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE4_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE4_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE4_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE5_REG  (DR_REG_LEDC_BASE + 0x554)
+/* LEDC_CH5_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE5_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE5_SCALE_M  ((LEDC_CH5_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE5_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE5_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE5_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE6_REG  (DR_REG_LEDC_BASE + 0x558)
+/* LEDC_CH5_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE6_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE6_SCALE_M  ((LEDC_CH5_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE6_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE6_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE6_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE7_REG  (DR_REG_LEDC_BASE + 0x55c)
+/* LEDC_CH5_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE7_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE7_SCALE_M  ((LEDC_CH5_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE7_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE7_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE7_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE8_REG  (DR_REG_LEDC_BASE + 0x560)
+/* LEDC_CH5_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE8_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE8_SCALE_M  ((LEDC_CH5_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE8_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE8_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE8_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE9_REG  (DR_REG_LEDC_BASE + 0x564)
+/* LEDC_CH5_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE9_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE9_SCALE_M  ((LEDC_CH5_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE9_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE9_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE9_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE10_REG  (DR_REG_LEDC_BASE + 0x568)
+/* LEDC_CH5_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE10_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE10_SCALE_M  ((LEDC_CH5_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE10_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE10_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE10_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE11_REG  (DR_REG_LEDC_BASE + 0x56c)
+/* LEDC_CH5_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE11_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE11_SCALE_M  ((LEDC_CH5_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE11_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE11_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE11_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE12_REG  (DR_REG_LEDC_BASE + 0x570)
+/* LEDC_CH5_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE12_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE12_SCALE_M  ((LEDC_CH5_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE12_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE12_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE12_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE13_REG  (DR_REG_LEDC_BASE + 0x574)
+/* LEDC_CH5_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE13_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE13_SCALE_M  ((LEDC_CH5_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE13_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE13_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE13_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE14_REG  (DR_REG_LEDC_BASE + 0x578)
+/* LEDC_CH5_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE14_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE14_SCALE_M  ((LEDC_CH5_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE14_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE14_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE14_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC_S  0
+
+#define LEDC_CH5_GAMMA_RANGE15_REG  (DR_REG_LEDC_BASE + 0x57c)
+/* LEDC_CH5_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_M  ((LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_S))
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_S  21
+/* LEDC_CH5_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE15_SCALE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE15_SCALE_M  ((LEDC_CH5_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE15_SCALE_S))
+#define LEDC_CH5_GAMMA_RANGE15_SCALE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE15_SCALE_S  11
+/* LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE    0x000003FF
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_M  ((LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_S))
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_S  1
+/* LEDC_CH5_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC    (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC_M  (BIT(0))
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC_V  0x1
+#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC_S  0
+
+
+#define LEDC_CH6_GAMMA_RANGE0_REG  (DR_REG_LEDC_BASE + 0x580)
+/* LEDC_CH6_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE0_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE0_SCALE_M  ((LEDC_CH6_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE0_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE0_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE0_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE1_REG  (DR_REG_LEDC_BASE + 0x584)
+/* LEDC_CH6_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE1_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE1_SCALE_M  ((LEDC_CH6_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE1_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE1_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE1_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE2_REG  (DR_REG_LEDC_BASE + 0x588)
+/* LEDC_CH6_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE2_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE2_SCALE_M  ((LEDC_CH6_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE2_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE2_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE2_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE3_REG  (DR_REG_LEDC_BASE + 0x58c)
+/* LEDC_CH6_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE3_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE3_SCALE_M  ((LEDC_CH6_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE3_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE3_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE3_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE4_REG  (DR_REG_LEDC_BASE + 0x590)
+/* LEDC_CH6_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE4_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE4_SCALE_M  ((LEDC_CH6_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE4_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE4_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE4_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE5_REG  (DR_REG_LEDC_BASE + 0x594)
+/* LEDC_CH6_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE5_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE5_SCALE_M  ((LEDC_CH6_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE5_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE5_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE5_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE6_REG  (DR_REG_LEDC_BASE + 0x598)
+/* LEDC_CH6_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE6_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE6_SCALE_M  ((LEDC_CH6_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE6_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE6_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE6_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE7_REG  (DR_REG_LEDC_BASE + 0x59c)
+/* LEDC_CH6_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE7_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE7_SCALE_M  ((LEDC_CH6_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE7_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE7_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE7_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE8_REG  (DR_REG_LEDC_BASE + 0x5a0)
+/* LEDC_CH6_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE8_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE8_SCALE_M  ((LEDC_CH6_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE8_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE8_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE8_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE9_REG  (DR_REG_LEDC_BASE + 0x5a4)
+/* LEDC_CH6_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE9_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE9_SCALE_M  ((LEDC_CH6_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE9_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE9_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE9_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE10_REG  (DR_REG_LEDC_BASE + 0x5a8)
+/* LEDC_CH6_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE10_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE10_SCALE_M  ((LEDC_CH6_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE10_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE10_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE10_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE11_REG  (DR_REG_LEDC_BASE + 0x5ac)
+/* LEDC_CH6_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE11_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE11_SCALE_M  ((LEDC_CH6_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE11_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE11_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE11_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE12_REG  (DR_REG_LEDC_BASE + 0x5b0)
+/* LEDC_CH6_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE12_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE12_SCALE_M  ((LEDC_CH6_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE12_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE12_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE12_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE13_REG  (DR_REG_LEDC_BASE + 0x5b4)
+/* LEDC_CH6_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE13_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE13_SCALE_M  ((LEDC_CH6_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE13_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE13_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE13_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE14_REG  (DR_REG_LEDC_BASE + 0x5b8)
+/* LEDC_CH6_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE14_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE14_SCALE_M  ((LEDC_CH6_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE14_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE14_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE14_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC_S  0
+
+#define LEDC_CH6_GAMMA_RANGE15_REG  (DR_REG_LEDC_BASE + 0x5bc)
+/* LEDC_CH6_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_M  ((LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_S))
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_S  21
+/* LEDC_CH6_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE15_SCALE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE15_SCALE_M  ((LEDC_CH6_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE15_SCALE_S))
+#define LEDC_CH6_GAMMA_RANGE15_SCALE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE15_SCALE_S  11
+/* LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE    0x000003FF
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_M  ((LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_S))
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_S  1
+/* LEDC_CH6_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC    (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC_M  (BIT(0))
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC_V  0x1
+#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC_S  0
+
+
+#define LEDC_CH7_GAMMA_RANGE0_REG  (DR_REG_LEDC_BASE + 0x5c0)
+/* LEDC_CH7_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE0_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE0_SCALE_M  ((LEDC_CH7_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE0_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE0_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE0_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE1_REG  (DR_REG_LEDC_BASE + 0x5c4)
+/* LEDC_CH7_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE1_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE1_SCALE_M  ((LEDC_CH7_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE1_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE1_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE1_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE2_REG  (DR_REG_LEDC_BASE + 0x5c8)
+/* LEDC_CH7_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE2_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE2_SCALE_M  ((LEDC_CH7_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE2_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE2_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE2_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE3_REG  (DR_REG_LEDC_BASE + 0x5cc)
+/* LEDC_CH7_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE3_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE3_SCALE_M  ((LEDC_CH7_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE3_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE3_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE3_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE4_REG  (DR_REG_LEDC_BASE + 0x5d0)
+/* LEDC_CH7_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE4_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE4_SCALE_M  ((LEDC_CH7_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE4_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE4_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE4_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE5_REG  (DR_REG_LEDC_BASE + 0x5d4)
+/* LEDC_CH7_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE5_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE5_SCALE_M  ((LEDC_CH7_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE5_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE5_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE5_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE6_REG  (DR_REG_LEDC_BASE + 0x5d8)
+/* LEDC_CH7_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE6_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE6_SCALE_M  ((LEDC_CH7_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE6_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE6_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE6_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE7_REG  (DR_REG_LEDC_BASE + 0x5dc)
+/* LEDC_CH7_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE7_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE7_SCALE_M  ((LEDC_CH7_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE7_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE7_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE7_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE8_REG  (DR_REG_LEDC_BASE + 0x5e0)
+/* LEDC_CH7_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE8_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE8_SCALE_M  ((LEDC_CH7_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE8_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE8_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE8_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE9_REG  (DR_REG_LEDC_BASE + 0x5e4)
+/* LEDC_CH7_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE9_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE9_SCALE_M  ((LEDC_CH7_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE9_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE9_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE9_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE10_REG  (DR_REG_LEDC_BASE + 0x5e8)
+/* LEDC_CH7_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE10_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE10_SCALE_M  ((LEDC_CH7_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE10_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE10_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE10_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE11_REG  (DR_REG_LEDC_BASE + 0x5ec)
+/* LEDC_CH7_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE11_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE11_SCALE_M  ((LEDC_CH7_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE11_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE11_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE11_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE12_REG  (DR_REG_LEDC_BASE + 0x5f0)
+/* LEDC_CH7_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE12_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE12_SCALE_M  ((LEDC_CH7_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE12_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE12_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE12_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE13_REG  (DR_REG_LEDC_BASE + 0x5f4)
+/* LEDC_CH7_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE13_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE13_SCALE_M  ((LEDC_CH7_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE13_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE13_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE13_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE14_REG  (DR_REG_LEDC_BASE + 0x5f8)
+/* LEDC_CH7_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE14_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE14_SCALE_M  ((LEDC_CH7_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE14_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE14_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE14_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC_S  0
+
+#define LEDC_CH7_GAMMA_RANGE15_REG  (DR_REG_LEDC_BASE + 0x5fc)
+/* LEDC_CH7_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_M  ((LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_S))
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_S  21
+/* LEDC_CH7_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE15_SCALE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE15_SCALE_M  ((LEDC_CH7_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE15_SCALE_S))
+#define LEDC_CH7_GAMMA_RANGE15_SCALE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE15_SCALE_S  11
+/* LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE    0x000003FF
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_M  ((LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_S))
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_V  0x3FF
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_S  1
+/* LEDC_CH7_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC    (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC_M  (BIT(0))
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC_V  0x1
+#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h
new file mode 100644
index 0000000000..23029726e8
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h
@@ -0,0 +1,1258 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: conf0 */
+/** Type of chn_conf0 register
+ *  Configuration register 0 for channel n
+ */
+typedef union {
+    struct {
+        /** timer_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Configures which timer is channel n selected.\\0: Select timer0\\1: Select
+         *  timer1\\2: Select timer2\\3: Select timer3
+         */
+        uint32_t timer_sel:2;
+        /** sig_out_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable signal output on channel n.\\0: Signal output
+         *  disable\\1: Signal output enable
+         */
+        uint32_t sig_out_en:1;
+        /** idle_lv : R/W; bitpos: [3]; default: 0;
+         *  Configures the output value when channel n is inactive. Valid only when
+         *  LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high
+         */
+        uint32_t idle_lv:1;
+        /** para_up : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn,
+         *  LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn,
+         *  LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel
+         *  n, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
+         */
+        uint32_t para_up:1;
+        /** ovf_num : R/W; bitpos: [14:5]; default: 0;
+         *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt
+         *  will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times.
+         */
+        uint32_t ovf_num:10;
+        /** ovf_cnt_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable
+         */
+        uint32_t ovf_cnt_en:1;
+        /** ovf_cnt_reset : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to reset the  ovf_cnt of channel n.\\0: Invalid. No
+         *  effect\\1: Reset the ovf_cnt
+         */
+        uint32_t ovf_cnt_reset:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} ledc_chn_conf0_reg_t;
+
+/** Type of chn_hpoint register
+ *  High point register for channel n
+ */
+typedef union {
+    struct {
+        /** hpoint : R/W; bitpos: [19:0]; default: 0;
+         *  Configures high point of signal output on channel n. The output value changes to
+         *  high when the selected timers has reached the value specified by this register.
+         */
+        uint32_t hpoint:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_chn_hpoint_reg_t;
+
+/** Type of chn_duty register
+ *  Initial duty cycle register for channel n
+ */
+typedef union {
+    struct {
+        /** duty : R/W; bitpos: [24:0]; default: 0;
+         *  Configures the duty of signal output on channel n.
+         */
+        uint32_t duty:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} ledc_chn_duty_reg_t;
+
+/** Type of chn_conf1 register
+ *  Configuration register 1 for channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** duty_start : R/W/SC; bitpos: [31]; default: 0;
+         *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
+         *  effect\\1: Take effect
+         */
+        uint32_t duty_start:1;
+    };
+    uint32_t val;
+} ledc_chn_conf1_reg_t;
+
+/** Type of chn_duty_r register
+ *  Current duty cycle register for channel n
+ */
+typedef union {
+    struct {
+        /** duty_ch0_r : RO; bitpos: [24:0]; default: 0;
+         *  Represents the current duty of output signal on channel n.
+         */
+        uint32_t duty:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} ledc_chn_duty_r_reg_t;
+
+
+/** Group: conf1 */
+/** Type of timern_conf register
+ *  Timer n configuration register
+ */
+typedef union {
+    struct {
+        /** duty_res : R/W; bitpos: [4:0]; default: 0;
+         *  Configures the range of the counter in timer n.
+         */
+        uint32_t duty_res:5;
+        /** clk_div : R/W; bitpos: [22:5]; default: 0;
+         *  Configures the divisor for the divider in timer n.The least significant eight bits
+         *  represent the fractional part.
+         */
+        uint32_t clk_div:18;
+        /** pause : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause
+         */
+        uint32_t pause:1;
+        /** rst : R/W; bitpos: [24]; default: 1;
+         *  Configures whether or not to reset timer n. The counter will show 0 after
+         *  reset.\\0: Not reset\\1: Reset
+         */
+        uint32_t rst:1;
+        /** tick_sel : R/W; bitpos: [25]; default: 0;
+         *  Configures which clock is timer n selected. Unused.
+         */
+        uint32_t tick_sel:1;
+        /** para_up : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to update LEDC_CLK_DIV_TIMERn and
+         *  LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update
+         */
+        uint32_t para_up:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} ledc_timern_conf_reg_t;
+
+/** Type of timern_value register
+ *  Timer n current counter value register
+ */
+typedef union {
+    struct {
+        /** cnt : RO; bitpos: [19:0]; default: 0;
+         *  Represents the current counter value of timer n.
+         */
+        uint32_t cnt:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_timern_value_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the
+         *  timer0 has reached its maximum counter value.
+         */
+        uint32_t timer0_ovf_int_raw:1;
+        /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the
+         *  timer1 has reached its maximum counter value.
+         */
+        uint32_t timer1_ovf_int_raw:1;
+        /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the
+         *  timer2 has reached its maximum counter value.
+         */
+        uint32_t timer2_ovf_int_raw:1;
+        /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the
+         *  timer3 has reached its maximum counter value.
+         */
+        uint32_t timer3_ovf_int_raw:1;
+        /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch0_int_raw:1;
+        /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch1_int_raw:1;
+        /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch2_int_raw:1;
+        /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch3_int_raw:1;
+        /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch4_int_raw:1;
+        /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch5_int_raw:1;
+        /** duty_chng_end_ch6_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch6_int_raw:1;
+        /** duty_chng_end_ch7_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered
+         *  when the fading of duty has finished.
+         */
+        uint32_t duty_chng_end_ch7_int_raw:1;
+        /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.
+         */
+        uint32_t ovf_cnt_ch0_int_raw:1;
+        /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.
+         */
+        uint32_t ovf_cnt_ch1_int_raw:1;
+        /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.
+         */
+        uint32_t ovf_cnt_ch2_int_raw:1;
+        /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.
+         */
+        uint32_t ovf_cnt_ch3_int_raw:1;
+        /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.
+         */
+        uint32_t ovf_cnt_ch4_int_raw:1;
+        /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.
+         */
+        uint32_t ovf_cnt_ch5_int_raw:1;
+        /** ovf_cnt_ch6_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6.
+         */
+        uint32_t ovf_cnt_ch6_int_raw:1;
+        /** ovf_cnt_ch7_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when
+         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7.
+         */
+        uint32_t ovf_cnt_ch7_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt masked status register
+ */
+typedef union {
+    struct {
+        /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only
+         *  when LEDC_TIMER0_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer0_ovf_int_st:1;
+        /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only
+         *  when LEDC_TIMER1_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer1_ovf_int_st:1;
+        /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only
+         *  when LEDC_TIMER2_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer2_ovf_int_st:1;
+        /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only
+         *  when LEDC_TIMER3_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer3_ovf_int_st:1;
+        /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch0_int_st:1;
+        /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch1_int_st:1;
+        /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch2_int_st:1;
+        /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch3_int_st:1;
+        /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch4_int_st:1;
+        /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch5_int_st:1;
+        /** duty_chng_end_ch6_int_st : RO; bitpos: [10]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch6_int_st:1;
+        /** duty_chng_end_ch7_int_st : RO; bitpos: [11]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid
+         *  only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1.
+         */
+        uint32_t duty_chng_end_ch7_int_st:1;
+        /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only
+         *  when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch0_int_st:1;
+        /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only
+         *  when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch1_int_st:1;
+        /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only
+         *  when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch2_int_st:1;
+        /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only
+         *  when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch3_int_st:1;
+        /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only
+         *  when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch4_int_st:1;
+        /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only
+         *  when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch5_int_st:1;
+        /** ovf_cnt_ch6_int_st : RO; bitpos: [18]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only
+         *  when LEDC_OVF_CNT_CH6_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch6_int_st:1;
+        /** ovf_cnt_ch7_int_st : RO; bitpos: [19]; default: 0;
+         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only
+         *  when LEDC_OVF_CNT_CH7_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch7_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT.
+         */
+        uint32_t timer0_ovf_int_ena:1;
+        /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT.
+         */
+        uint32_t timer1_ovf_int_ena:1;
+        /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT.
+         */
+        uint32_t timer2_ovf_int_ena:1;
+        /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT.
+         */
+        uint32_t timer3_ovf_int_ena:1;
+        /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT.
+         */
+        uint32_t duty_chng_end_ch0_int_ena:1;
+        /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT.
+         */
+        uint32_t duty_chng_end_ch1_int_ena:1;
+        /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT.
+         */
+        uint32_t duty_chng_end_ch2_int_ena:1;
+        /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT.
+         */
+        uint32_t duty_chng_end_ch3_int_ena:1;
+        /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT.
+         */
+        uint32_t duty_chng_end_ch4_int_ena:1;
+        /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT.
+         */
+        uint32_t duty_chng_end_ch5_int_ena:1;
+        /** duty_chng_end_ch6_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT.
+         */
+        uint32_t duty_chng_end_ch6_int_ena:1;
+        /** duty_chng_end_ch7_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT.
+         */
+        uint32_t duty_chng_end_ch7_int_ena:1;
+        /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT.
+         */
+        uint32_t ovf_cnt_ch0_int_ena:1;
+        /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT.
+         */
+        uint32_t ovf_cnt_ch1_int_ena:1;
+        /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT.
+         */
+        uint32_t ovf_cnt_ch2_int_ena:1;
+        /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT.
+         */
+        uint32_t ovf_cnt_ch3_int_ena:1;
+        /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT.
+         */
+        uint32_t ovf_cnt_ch4_int_ena:1;
+        /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT.
+         */
+        uint32_t ovf_cnt_ch5_int_ena:1;
+        /** ovf_cnt_ch6_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT.
+         */
+        uint32_t ovf_cnt_ch6_int_ena:1;
+        /** ovf_cnt_ch7_int_ena : R/W; bitpos: [19]; default: 0;
+         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT.
+         */
+        uint32_t ovf_cnt_ch7_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT.
+         */
+        uint32_t timer0_ovf_int_clr:1;
+        /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT.
+         */
+        uint32_t timer1_ovf_int_clr:1;
+        /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT.
+         */
+        uint32_t timer2_ovf_int_clr:1;
+        /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT.
+         */
+        uint32_t timer3_ovf_int_clr:1;
+        /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT.
+         */
+        uint32_t duty_chng_end_ch0_int_clr:1;
+        /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT.
+         */
+        uint32_t duty_chng_end_ch1_int_clr:1;
+        /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT.
+         */
+        uint32_t duty_chng_end_ch2_int_clr:1;
+        /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT.
+         */
+        uint32_t duty_chng_end_ch3_int_clr:1;
+        /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT.
+         */
+        uint32_t duty_chng_end_ch4_int_clr:1;
+        /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT.
+         */
+        uint32_t duty_chng_end_ch5_int_clr:1;
+        /** duty_chng_end_ch6_int_clr : WT; bitpos: [10]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT.
+         */
+        uint32_t duty_chng_end_ch6_int_clr:1;
+        /** duty_chng_end_ch7_int_clr : WT; bitpos: [11]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT.
+         */
+        uint32_t duty_chng_end_ch7_int_clr:1;
+        /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT.
+         */
+        uint32_t ovf_cnt_ch0_int_clr:1;
+        /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT.
+         */
+        uint32_t ovf_cnt_ch1_int_clr:1;
+        /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT.
+         */
+        uint32_t ovf_cnt_ch2_int_clr:1;
+        /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT.
+         */
+        uint32_t ovf_cnt_ch3_int_clr:1;
+        /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT.
+         */
+        uint32_t ovf_cnt_ch4_int_clr:1;
+        /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT.
+         */
+        uint32_t ovf_cnt_ch5_int_clr:1;
+        /** ovf_cnt_ch6_int_clr : WT; bitpos: [18]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT.
+         */
+        uint32_t ovf_cnt_ch6_int_clr:1;
+        /** ovf_cnt_ch7_int_clr : WT; bitpos: [19]; default: 0;
+         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT.
+         */
+        uint32_t ovf_cnt_ch7_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_int_clr_reg_t;
+
+
+/** Group: gamma */
+/** Type of chn_gamma_conf register
+ *  Ledc chn gamma config register.
+ */
+typedef union {
+    struct {
+        /** ch0_gamma_entry_num : R/W; bitpos: [4:0]; default: 0;
+         *  Configures the number of duty cycle fading rages for LEDC chn.
+         */
+        uint32_t ch0_gamma_entry_num:5;
+        /** ch0_gamma_pause : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No
+         *  effect\\1: Pause
+         */
+        uint32_t ch0_gamma_pause:1;
+        /** ch0_gamma_resume : WT; bitpos: [6]; default: 0;
+         *  Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No
+         *  effect\\1: Resume
+         */
+        uint32_t ch0_gamma_resume:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ledc_chn_gamma_conf_reg_t;
+
+
+/** Group: en0 */
+/** Type of evt_task_en0 register
+ *  Ledc event task enable bit register0.
+ */
+typedef union {
+    struct {
+        /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch0_en:1;
+        /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch1_en:1;
+        /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch2_en:1;
+        /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch3_en:1;
+        /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch4_en:1;
+        /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch5_en:1;
+        /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch6_en:1;
+        /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_duty_chng_end_ch7_en:1;
+        /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch0_en:1;
+        /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch1_en:1;
+        /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch2_en:1;
+        /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch3_en:1;
+        /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch4_en:1;
+        /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch5_en:1;
+        /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch6_en:1;
+        /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_ovf_cnt_pls_ch7_en:1;
+        /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_time_ovf_timer0_en:1;
+        /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_time_ovf_timer1_en:1;
+        /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_time_ovf_timer2_en:1;
+        /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_time_ovf_timer3_en:1;
+        /** evt_timer0_cmp_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer0_cmp_en:1;
+        /** evt_timer1_cmp_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer1_cmp_en:1;
+        /** evt_timer2_cmp_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer2_cmp_en:1;
+        /** evt_timer3_cmp_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer3_cmp_en:1;
+        /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_duty_scale_update_ch0_en:1;
+        /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_duty_scale_update_ch1_en:1;
+        /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_duty_scale_update_ch2_en:1;
+        /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_duty_scale_update_ch3_en:1;
+        /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_duty_scale_update_ch4_en:1;
+        /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_duty_scale_update_ch5_en:1;
+        /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0;
+         *  Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_duty_scale_update_ch6_en:1;
+        /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0;
+         *  Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_duty_scale_update_ch7_en:1;
+    };
+    uint32_t val;
+} ledc_evt_task_en0_reg_t;
+
+
+/** Group: en1 */
+/** Type of evt_task_en1 register
+ *  Ledc event task enable bit register1.
+ */
+typedef union {
+    struct {
+        /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_timer0_res_update_en:1;
+        /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_timer1_res_update_en:1;
+        /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_timer2_res_update_en:1;
+        /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_timer3_res_update_en:1;
+        /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer0_cap_en:1;
+        /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer1_cap_en:1;
+        /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer2_cap_en:1;
+        /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer3_cap_en:1;
+        /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_sig_out_dis_ch0_en:1;
+        /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_sig_out_dis_ch1_en:1;
+        /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_sig_out_dis_ch2_en:1;
+        /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_sig_out_dis_ch3_en:1;
+        /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_sig_out_dis_ch4_en:1;
+        /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_sig_out_dis_ch5_en:1;
+        /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_sig_out_dis_ch6_en:1;
+        /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_sig_out_dis_ch7_en:1;
+        /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch0_en:1;
+        /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch1_en:1;
+        /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch2_en:1;
+        /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch3_en:1;
+        /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch4_en:1;
+        /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch5_en:1;
+        /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch6_en:1;
+        /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_ovf_cnt_rst_ch7_en:1;
+        /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer0_rst_en:1;
+        /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer1_rst_en:1;
+        /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer2_rst_en:1;
+        /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer3_rst_en:1;
+        /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_timer0_pause_resume_en:1;
+        /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_timer1_pause_resume_en:1;
+        /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0;
+         *  Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_timer2_pause_resume_en:1;
+        /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0;
+         *  Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_timer3_pause_resume_en:1;
+    };
+    uint32_t val;
+} ledc_evt_task_en1_reg_t;
+
+
+/** Group: en2 */
+/** Type of evt_task_en2 register
+ *  Ledc event task enable bit register2.
+ */
+typedef union {
+    struct {
+        /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_restart_ch0_en:1;
+        /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_restart_ch1_en:1;
+        /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_restart_ch2_en:1;
+        /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_restart_ch3_en:1;
+        /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_restart_ch4_en:1;
+        /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_restart_ch5_en:1;
+        /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_restart_ch6_en:1;
+        /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_restart_ch7_en:1;
+        /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_pause_ch0_en:1;
+        /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_pause_ch1_en:1;
+        /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_pause_ch2_en:1;
+        /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_pause_ch3_en:1;
+        /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_pause_ch4_en:1;
+        /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_pause_ch5_en:1;
+        /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_pause_ch6_en:1;
+        /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_pause_ch7_en:1;
+        /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_resume_ch0_en:1;
+        /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_resume_ch1_en:1;
+        /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_resume_ch2_en:1;
+        /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_resume_ch3_en:1;
+        /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_resume_ch4_en:1;
+        /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_resume_ch5_en:1;
+        /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_resume_ch6_en:1;
+        /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_gamma_resume_ch7_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ledc_evt_task_en2_reg_t;
+
+
+/** Group: cmp */
+/** Type of timern_cmp register
+ *  Ledc timern compare value register.
+ */
+typedef union {
+    struct {
+        /** timer0_cmp : R/W; bitpos: [19:0]; default: 0;
+         *  Configures the comparison value for LEDC timern.
+         */
+        uint32_t timer0_cmp:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_timern_cmp_reg_t;
+
+
+/** Group: cap */
+/** Type of timern_cnt_cap register
+ *  Ledc timern captured count value register.
+ */
+typedef union {
+    struct {
+        /** timer0_cnt_cap : RO; bitpos: [19:0]; default: 0;
+         *  Represents the captured LEDC timern count value.
+         */
+        uint32_t timer_cnt_cap:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} ledc_timern_cnt_cap_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of conf register
+ *  LEDC global configuration register
+ */
+typedef union {
+    struct {
+        /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2:
+         *  XTAL_CLK\\3: Invalid. No clock
+         */
+        uint32_t apb_clk_sel:2;
+        /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock
+         *  gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the
+         *  clock gate for LEDC ch0 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch0:1;
+        /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock
+         *  gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the
+         *  clock gate for LEDC ch1 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch1:1;
+        /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock
+         *  gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the
+         *  clock gate for LEDC ch2 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch2:1;
+        /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock
+         *  gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the
+         *  clock gate for LEDC ch3 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch3:1;
+        /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock
+         *  gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the
+         *  clock gate for LEDC ch4 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch4:1;
+        /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock
+         *  gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the
+         *  clock gate for LEDC ch5 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch5:1;
+        /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock
+         *  gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the
+         *  clock gate for LEDC ch6 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch6:1;
+        /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock
+         *  gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the
+         *  clock gate for LEDC ch7 gamma ram
+         */
+        uint32_t gamma_ram_clk_en_ch7:1;
+        uint32_t reserved_10:21;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
+         *  when application writes registers\\1: Force open the clock gate for register
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} ledc_conf_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** ledc_date : R/W; bitpos: [27:0]; default: 36712560;
+         *  Configures the version.
+         */
+        uint32_t ledc_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ledc_date_reg_t;
+
+typedef struct {
+    volatile ledc_chn_conf0_reg_t conf0;
+    volatile ledc_chn_hpoint_reg_t hpoint;
+    volatile ledc_chn_duty_reg_t duty_init;
+    volatile ledc_chn_conf1_reg_t conf1;
+    volatile ledc_chn_duty_r_reg_t duty_r;
+} ledc_chn_reg_t;
+
+typedef struct {
+    volatile ledc_chn_reg_t channel[8];
+} ledc_ch_group_reg_t;
+
+typedef struct {
+    volatile ledc_timern_conf_reg_t conf;
+    volatile ledc_timern_value_reg_t value;
+} ledc_timerx_reg_t;
+
+typedef struct {
+    volatile ledc_timerx_reg_t timer[4];
+} ledc_timer_group_reg_t;
+
+typedef struct {
+    volatile ledc_ch_group_reg_t channel_group[1];
+    volatile ledc_timer_group_reg_t timer_group[1];
+    volatile ledc_int_raw_reg_t int_raw;
+    volatile ledc_int_st_reg_t  int_st;
+    volatile ledc_int_ena_reg_t int_ena;
+    volatile ledc_int_clr_reg_t int_clr;
+    uint32_t reserved_0d0[12];
+    volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[8];
+    volatile ledc_evt_task_en0_reg_t evt_task_en0;
+    volatile ledc_evt_task_en1_reg_t evt_task_en1;
+    volatile ledc_evt_task_en2_reg_t evt_task_en2;
+    uint32_t reserved_12c[5];
+    volatile ledc_timern_cmp_reg_t timern_cmp[4];
+    volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4];
+    uint32_t reserved_160[4];
+    volatile ledc_conf_reg_t conf;
+    volatile ledc_date_reg_t date;
+} ledc_dev_t;
+
+
+/**
+ * Gamma fade param group ram type
+ */
+typedef union {
+    struct {
+        uint32_t duty_inc       :1;
+        uint32_t duty_cycle     :10;
+        uint32_t scale          :10;
+        uint32_t duty_num       :10;
+        uint32_t reserved       :1;
+    };
+    uint32_t val;
+} ledc_channel_gamma_fade_param_t;
+
+typedef struct {
+    volatile ledc_channel_gamma_fade_param_t entry[16];
+} ledc_gamma_channel_t;
+
+typedef struct {
+    volatile ledc_gamma_channel_t channel[8];
+} ledc_gamma_ram_t;
+
+
+extern ledc_dev_t LEDC;
+extern ledc_gamma_ram_t LEDC_GAMMA_RAM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure");
+_Static_assert(sizeof(ledc_gamma_ram_t) == 0x200, "Invalid size of ledc_gamma_ram_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h
new file mode 100644
index 0000000000..0d7ce67bd9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h
@@ -0,0 +1,585 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_LP2HP_PMS_DATE_REG register
+ *  NA
+ */
+#define TEE_LP2HP_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
+/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
+ *  NA
+ */
+#define TEE_TEE_DATE    0xFFFFFFFFU
+#define TEE_TEE_DATE_M  (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
+#define TEE_TEE_DATE_V  0xFFFFFFFFU
+#define TEE_TEE_DATE_S  0
+
+/** TEE_PMS_CLK_EN_REG register
+ *  NA
+ */
+#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
+/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CLK_EN    (BIT(0))
+#define TEE_REG_CLK_EN_M  (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
+#define TEE_REG_CLK_EN_V  0x00000001U
+#define TEE_REG_CLK_EN_S  0
+
+/** TEE_LP_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
+/** TEE_REG_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_PSRAM_ALLOW    (BIT(0))
+#define TEE_REG_LP_MM_PSRAM_ALLOW_M  (TEE_REG_LP_MM_PSRAM_ALLOW_V << TEE_REG_LP_MM_PSRAM_ALLOW_S)
+#define TEE_REG_LP_MM_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_PSRAM_ALLOW_S  0
+/** TEE_REG_LP_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_FLASH_ALLOW    (BIT(1))
+#define TEE_REG_LP_MM_FLASH_ALLOW_M  (TEE_REG_LP_MM_FLASH_ALLOW_V << TEE_REG_LP_MM_FLASH_ALLOW_S)
+#define TEE_REG_LP_MM_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_FLASH_ALLOW_S  1
+/** TEE_REG_LP_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_L2MEM_ALLOW    (BIT(2))
+#define TEE_REG_LP_MM_L2MEM_ALLOW_M  (TEE_REG_LP_MM_L2MEM_ALLOW_V << TEE_REG_LP_MM_L2MEM_ALLOW_S)
+#define TEE_REG_LP_MM_L2MEM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_L2MEM_ALLOW_S  2
+/** TEE_REG_LP_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_L2ROM_ALLOW    (BIT(3))
+#define TEE_REG_LP_MM_L2ROM_ALLOW_M  (TEE_REG_LP_MM_L2ROM_ALLOW_V << TEE_REG_LP_MM_L2ROM_ALLOW_S)
+#define TEE_REG_LP_MM_L2ROM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_L2ROM_ALLOW_S  3
+/** TEE_REG_LP_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_TRACE0_ALLOW    (BIT(6))
+#define TEE_REG_LP_MM_TRACE0_ALLOW_M  (TEE_REG_LP_MM_TRACE0_ALLOW_V << TEE_REG_LP_MM_TRACE0_ALLOW_S)
+#define TEE_REG_LP_MM_TRACE0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_TRACE0_ALLOW_S  6
+/** TEE_REG_LP_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_TRACE1_ALLOW    (BIT(7))
+#define TEE_REG_LP_MM_TRACE1_ALLOW_M  (TEE_REG_LP_MM_TRACE1_ALLOW_V << TEE_REG_LP_MM_TRACE1_ALLOW_S)
+#define TEE_REG_LP_MM_TRACE1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_TRACE1_ALLOW_S  7
+/** TEE_REG_LP_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_M  (TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S)
+#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S  8
+/** TEE_REG_LP_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_M  (TEE_REG_LP_MM_L2MEM_MON_ALLOW_V << TEE_REG_LP_MM_L2MEM_MON_ALLOW_S)
+#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_S  9
+/** TEE_REG_LP_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_TCM_MON_ALLOW    (BIT(10))
+#define TEE_REG_LP_MM_TCM_MON_ALLOW_M  (TEE_REG_LP_MM_TCM_MON_ALLOW_V << TEE_REG_LP_MM_TCM_MON_ALLOW_S)
+#define TEE_REG_LP_MM_TCM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_TCM_MON_ALLOW_S  10
+/** TEE_REG_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_CACHE_ALLOW    (BIT(11))
+#define TEE_REG_LP_MM_CACHE_ALLOW_M  (TEE_REG_LP_MM_CACHE_ALLOW_V << TEE_REG_LP_MM_CACHE_ALLOW_S)
+#define TEE_REG_LP_MM_CACHE_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_CACHE_ALLOW_S  11
+
+/** TEE_LP_MM_PMS_REG1_REG register
+ *  NA
+ */
+#define TEE_LP_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x30)
+/** TEE_REG_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_M  (TEE_REG_LP_MM_HP_USBOTG_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG_ALLOW_S)
+#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_S  0
+/** TEE_REG_LP_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_M  (TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S)
+#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S  1
+/** TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_M  (TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** TEE_REG_LP_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_GDMA_ALLOW    (BIT(3))
+#define TEE_REG_LP_MM_HP_GDMA_ALLOW_M  (TEE_REG_LP_MM_HP_GDMA_ALLOW_V << TEE_REG_LP_MM_HP_GDMA_ALLOW_S)
+#define TEE_REG_LP_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_GDMA_ALLOW_S  3
+/** TEE_REG_LP_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_REGDMA_ALLOW    (BIT(4))
+#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_M  (TEE_REG_LP_MM_HP_REGDMA_ALLOW_V << TEE_REG_LP_MM_HP_REGDMA_ALLOW_S)
+#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_S  4
+/** TEE_REG_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_M  (TEE_REG_LP_MM_HP_SDMMC_ALLOW_V << TEE_REG_LP_MM_HP_SDMMC_ALLOW_S)
+#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_S  5
+/** TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_M  (TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S)
+#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S  6
+/** TEE_REG_LP_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_JPEG_ALLOW    (BIT(7))
+#define TEE_REG_LP_MM_HP_JPEG_ALLOW_M  (TEE_REG_LP_MM_HP_JPEG_ALLOW_V << TEE_REG_LP_MM_HP_JPEG_ALLOW_S)
+#define TEE_REG_LP_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_JPEG_ALLOW_S  7
+/** TEE_REG_LP_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PPA_ALLOW    (BIT(8))
+#define TEE_REG_LP_MM_HP_PPA_ALLOW_M  (TEE_REG_LP_MM_HP_PPA_ALLOW_V << TEE_REG_LP_MM_HP_PPA_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PPA_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PPA_ALLOW_S  8
+/** TEE_REG_LP_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_M  (TEE_REG_LP_MM_HP_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_DMA2D_ALLOW_S)
+#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_S  9
+/** TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_M  (TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S)
+#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_M  (TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S)
+#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S  11
+/** TEE_REG_LP_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_FLASH_ALLOW    (BIT(12))
+#define TEE_REG_LP_MM_HP_FLASH_ALLOW_M  (TEE_REG_LP_MM_HP_FLASH_ALLOW_V << TEE_REG_LP_MM_HP_FLASH_ALLOW_S)
+#define TEE_REG_LP_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_FLASH_ALLOW_S  12
+/** TEE_REG_LP_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_M  (TEE_REG_LP_MM_HP_PSRAM_ALLOW_V << TEE_REG_LP_MM_HP_PSRAM_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_S  13
+/** TEE_REG_LP_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_M  (TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V << TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S)
+#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S  14
+/** TEE_REG_LP_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_GMAC_ALLOW    (BIT(15))
+#define TEE_REG_LP_MM_HP_GMAC_ALLOW_M  (TEE_REG_LP_MM_HP_GMAC_ALLOW_V << TEE_REG_LP_MM_HP_GMAC_ALLOW_S)
+#define TEE_REG_LP_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_GMAC_ALLOW_S  15
+/** TEE_REG_LP_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_M  (TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V << TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S)
+#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S  16
+/** TEE_REG_LP_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PVT_ALLOW    (BIT(17))
+#define TEE_REG_LP_MM_HP_PVT_ALLOW_M  (TEE_REG_LP_MM_HP_PVT_ALLOW_V << TEE_REG_LP_MM_HP_PVT_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PVT_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PVT_ALLOW_S  17
+/** TEE_REG_LP_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_M  (TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S)
+#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S  18
+/** TEE_REG_LP_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_M  (TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S)
+#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S  19
+/** TEE_REG_LP_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_ISP_ALLOW    (BIT(20))
+#define TEE_REG_LP_MM_HP_ISP_ALLOW_M  (TEE_REG_LP_MM_HP_ISP_ALLOW_V << TEE_REG_LP_MM_HP_ISP_ALLOW_S)
+#define TEE_REG_LP_MM_HP_ISP_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_ISP_ALLOW_S  20
+/** TEE_REG_LP_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_M  (TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V << TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S)
+#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S  21
+/** TEE_REG_LP_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_RMT_ALLOW    (BIT(22))
+#define TEE_REG_LP_MM_HP_RMT_ALLOW_M  (TEE_REG_LP_MM_HP_RMT_ALLOW_V << TEE_REG_LP_MM_HP_RMT_ALLOW_S)
+#define TEE_REG_LP_MM_HP_RMT_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_RMT_ALLOW_S  22
+/** TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_M  (TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_S)
+#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** TEE_REG_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_M  (TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S)
+#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S  24
+/** TEE_REG_LP_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_M  (TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S  25
+/** TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_M  (TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** TEE_REG_LP_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_DMA_PMS_ALLOW    (BIT(27))
+#define TEE_REG_LP_MM_DMA_PMS_ALLOW_M  (TEE_REG_LP_MM_DMA_PMS_ALLOW_V << TEE_REG_LP_MM_DMA_PMS_ALLOW_S)
+#define TEE_REG_LP_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_DMA_PMS_ALLOW_S  27
+/** TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_M  (TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S)
+#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S  28
+/** TEE_REG_LP_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW    (BIT(29))
+#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_M  (TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_S)
+#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_S  29
+
+/** TEE_LP_MM_PMS_REG2_REG register
+ *  NA
+ */
+#define TEE_LP_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0xa4)
+/** TEE_REG_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_M  (TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S  0
+/** TEE_REG_LP_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_M  (TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S  1
+/** TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_M  (TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_M  (TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** TEE_REG_LP_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I2C0_ALLOW    (BIT(4))
+#define TEE_REG_LP_MM_HP_I2C0_ALLOW_M  (TEE_REG_LP_MM_HP_I2C0_ALLOW_V << TEE_REG_LP_MM_HP_I2C0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I2C0_ALLOW_S  4
+/** TEE_REG_LP_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I2C1_ALLOW    (BIT(5))
+#define TEE_REG_LP_MM_HP_I2C1_ALLOW_M  (TEE_REG_LP_MM_HP_I2C1_ALLOW_V << TEE_REG_LP_MM_HP_I2C1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I2C1_ALLOW_S  5
+/** TEE_REG_LP_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I2S0_ALLOW    (BIT(6))
+#define TEE_REG_LP_MM_HP_I2S0_ALLOW_M  (TEE_REG_LP_MM_HP_I2S0_ALLOW_V << TEE_REG_LP_MM_HP_I2S0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I2S0_ALLOW_S  6
+/** TEE_REG_LP_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I2S1_ALLOW    (BIT(7))
+#define TEE_REG_LP_MM_HP_I2S1_ALLOW_M  (TEE_REG_LP_MM_HP_I2S1_ALLOW_V << TEE_REG_LP_MM_HP_I2S1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I2S1_ALLOW_S  7
+/** TEE_REG_LP_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I2S2_ALLOW    (BIT(8))
+#define TEE_REG_LP_MM_HP_I2S2_ALLOW_M  (TEE_REG_LP_MM_HP_I2S2_ALLOW_V << TEE_REG_LP_MM_HP_I2S2_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I2S2_ALLOW_S  8
+/** TEE_REG_LP_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PCNT_ALLOW    (BIT(9))
+#define TEE_REG_LP_MM_HP_PCNT_ALLOW_M  (TEE_REG_LP_MM_HP_PCNT_ALLOW_V << TEE_REG_LP_MM_HP_PCNT_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PCNT_ALLOW_S  9
+/** TEE_REG_LP_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UART0_ALLOW    (BIT(10))
+#define TEE_REG_LP_MM_HP_UART0_ALLOW_M  (TEE_REG_LP_MM_HP_UART0_ALLOW_V << TEE_REG_LP_MM_HP_UART0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UART0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UART0_ALLOW_S  10
+/** TEE_REG_LP_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UART1_ALLOW    (BIT(11))
+#define TEE_REG_LP_MM_HP_UART1_ALLOW_M  (TEE_REG_LP_MM_HP_UART1_ALLOW_V << TEE_REG_LP_MM_HP_UART1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UART1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UART1_ALLOW_S  11
+/** TEE_REG_LP_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UART2_ALLOW    (BIT(12))
+#define TEE_REG_LP_MM_HP_UART2_ALLOW_M  (TEE_REG_LP_MM_HP_UART2_ALLOW_V << TEE_REG_LP_MM_HP_UART2_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UART2_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UART2_ALLOW_S  12
+/** TEE_REG_LP_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UART3_ALLOW    (BIT(13))
+#define TEE_REG_LP_MM_HP_UART3_ALLOW_M  (TEE_REG_LP_MM_HP_UART3_ALLOW_V << TEE_REG_LP_MM_HP_UART3_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UART3_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UART3_ALLOW_S  13
+/** TEE_REG_LP_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UART4_ALLOW    (BIT(14))
+#define TEE_REG_LP_MM_HP_UART4_ALLOW_M  (TEE_REG_LP_MM_HP_UART4_ALLOW_V << TEE_REG_LP_MM_HP_UART4_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UART4_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UART4_ALLOW_S  14
+/** TEE_REG_LP_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_M  (TEE_REG_LP_MM_HP_PARLIO_ALLOW_V << TEE_REG_LP_MM_HP_PARLIO_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_S  15
+/** TEE_REG_LP_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_M  (TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S)
+#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S  16
+/** TEE_REG_LP_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_M  (TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S)
+#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S  17
+/** TEE_REG_LP_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_M  (TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S)
+#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S  18
+/** TEE_REG_LP_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_LEDC_ALLOW    (BIT(19))
+#define TEE_REG_LP_MM_HP_LEDC_ALLOW_M  (TEE_REG_LP_MM_HP_LEDC_ALLOW_V << TEE_REG_LP_MM_HP_LEDC_ALLOW_S)
+#define TEE_REG_LP_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_LEDC_ALLOW_S  19
+/** TEE_REG_LP_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_ETM_ALLOW    (BIT(21))
+#define TEE_REG_LP_MM_HP_ETM_ALLOW_M  (TEE_REG_LP_MM_HP_ETM_ALLOW_V << TEE_REG_LP_MM_HP_ETM_ALLOW_S)
+#define TEE_REG_LP_MM_HP_ETM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_ETM_ALLOW_S  21
+/** TEE_REG_LP_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_M  (TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V << TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S)
+#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S  22
+/** TEE_REG_LP_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_M  (TEE_REG_LP_MM_HP_TWAI0_ALLOW_V << TEE_REG_LP_MM_HP_TWAI0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_S  23
+/** TEE_REG_LP_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_M  (TEE_REG_LP_MM_HP_TWAI1_ALLOW_V << TEE_REG_LP_MM_HP_TWAI1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_S  24
+/** TEE_REG_LP_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_M  (TEE_REG_LP_MM_HP_TWAI2_ALLOW_V << TEE_REG_LP_MM_HP_TWAI2_ALLOW_S)
+#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_S  25
+/** TEE_REG_LP_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_M  (TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V << TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S  26
+/** TEE_REG_LP_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_M  (TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S  27
+/** TEE_REG_LP_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_M  (TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V << TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S)
+#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S  28
+/** TEE_REG_LP_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_ADC_ALLOW    (BIT(30))
+#define TEE_REG_LP_MM_HP_ADC_ALLOW_M  (TEE_REG_LP_MM_HP_ADC_ALLOW_V << TEE_REG_LP_MM_HP_ADC_ALLOW_S)
+#define TEE_REG_LP_MM_HP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_ADC_ALLOW_S  30
+/** TEE_REG_LP_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UHCI_ALLOW    (BIT(31))
+#define TEE_REG_LP_MM_HP_UHCI_ALLOW_M  (TEE_REG_LP_MM_HP_UHCI_ALLOW_V << TEE_REG_LP_MM_HP_UHCI_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UHCI_ALLOW_S  31
+
+/** TEE_LP_MM_PMS_REG3_REG register
+ *  NA
+ */
+#define TEE_LP_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x11c)
+/** TEE_REG_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_GPIO_ALLOW    (BIT(0))
+#define TEE_REG_LP_MM_HP_GPIO_ALLOW_M  (TEE_REG_LP_MM_HP_GPIO_ALLOW_V << TEE_REG_LP_MM_HP_GPIO_ALLOW_S)
+#define TEE_REG_LP_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_GPIO_ALLOW_S  0
+/** TEE_REG_LP_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_M  (TEE_REG_LP_MM_HP_IOMUX_ALLOW_V << TEE_REG_LP_MM_HP_IOMUX_ALLOW_S)
+#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_S  1
+/** TEE_REG_LP_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_M  (TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S)
+#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S  2
+/** TEE_REG_LP_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_M  (TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V << TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S)
+#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S  3
+/** TEE_REG_LP_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_M  (TEE_REG_LP_MM_HP_CLKRST_ALLOW_V << TEE_REG_LP_MM_HP_CLKRST_ALLOW_S)
+#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_S  4
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h
new file mode 100644
index 0000000000..acd5976904
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h
@@ -0,0 +1,749 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMS_LP2HP_PERI_PMS_DATE_REG register
+ *  Version control register
+ */
+#define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x0)
+/** PMS_LP2HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
+ *  Version control register.
+ */
+#define PMS_LP2HP_PERI_PMS_DATE    0xFFFFFFFFU
+#define PMS_LP2HP_PERI_PMS_DATE_M  (PMS_LP2HP_PERI_PMS_DATE_V << PMS_LP2HP_PERI_PMS_DATE_S)
+#define PMS_LP2HP_PERI_PMS_DATE_V  0xFFFFFFFFU
+#define PMS_LP2HP_PERI_PMS_DATE_S  0
+
+/** PMS_LP2HP_PERI_PMS_CLK_EN_REG register
+ *  Clock gating register
+ */
+#define PMS_LP2HP_PERI_PMS_CLK_EN_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x4)
+/** PMS_LP2HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating.
+ *  1: Keep the clock always on.
+ */
+#define PMS_LP2HP_PERI_PMS_CLK_EN    (BIT(0))
+#define PMS_LP2HP_PERI_PMS_CLK_EN_M  (PMS_LP2HP_PERI_PMS_CLK_EN_V << PMS_LP2HP_PERI_PMS_CLK_EN_S)
+#define PMS_LP2HP_PERI_PMS_CLK_EN_V  0x00000001U
+#define PMS_LP2HP_PERI_PMS_CLK_EN_S  0
+
+/** PMS_LP_MM_PMS_REG0_REG register
+ *  Permission control register0 for the LP CPU in machine mode
+ */
+#define PMS_LP_MM_PMS_REG0_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x8)
+/** PMS_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access external RAM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_PSRAM_ALLOW    (BIT(0))
+#define PMS_LP_MM_PSRAM_ALLOW_M  (PMS_LP_MM_PSRAM_ALLOW_V << PMS_LP_MM_PSRAM_ALLOW_S)
+#define PMS_LP_MM_PSRAM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_PSRAM_ALLOW_S  0
+/** PMS_LP_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access external
+ *  flash without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_FLASH_ALLOW    (BIT(1))
+#define PMS_LP_MM_FLASH_ALLOW_M  (PMS_LP_MM_FLASH_ALLOW_V << PMS_LP_MM_FLASH_ALLOW_S)
+#define PMS_LP_MM_FLASH_ALLOW_V  0x00000001U
+#define PMS_LP_MM_FLASH_ALLOW_S  1
+/** PMS_LP_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP L2M2M
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_L2MEM_ALLOW    (BIT(2))
+#define PMS_LP_MM_L2MEM_ALLOW_M  (PMS_LP_MM_L2MEM_ALLOW_V << PMS_LP_MM_L2MEM_ALLOW_S)
+#define PMS_LP_MM_L2MEM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_L2MEM_ALLOW_S  2
+/** PMS_LP_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP ROM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_L2ROM_ALLOW    (BIT(3))
+#define PMS_LP_MM_L2ROM_ALLOW_M  (PMS_LP_MM_L2ROM_ALLOW_V << PMS_LP_MM_L2ROM_ALLOW_S)
+#define PMS_LP_MM_L2ROM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_L2ROM_ALLOW_S  3
+/** PMS_LP_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access TRACE0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_TRACE0_ALLOW    (BIT(6))
+#define PMS_LP_MM_TRACE0_ALLOW_M  (PMS_LP_MM_TRACE0_ALLOW_V << PMS_LP_MM_TRACE0_ALLOW_S)
+#define PMS_LP_MM_TRACE0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_TRACE0_ALLOW_S  6
+/** PMS_LP_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access TRACE1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_TRACE1_ALLOW    (BIT(7))
+#define PMS_LP_MM_TRACE1_ALLOW_M  (PMS_LP_MM_TRACE1_ALLOW_V << PMS_LP_MM_TRACE1_ALLOW_S)
+#define PMS_LP_MM_TRACE1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_TRACE1_ALLOW_S  7
+/** PMS_LP_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access CPU bus
+ *  monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define PMS_LP_MM_CPU_BUS_MON_ALLOW_M  (PMS_LP_MM_CPU_BUS_MON_ALLOW_V << PMS_LP_MM_CPU_BUS_MON_ALLOW_S)
+#define PMS_LP_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define PMS_LP_MM_CPU_BUS_MON_ALLOW_S  8
+/** PMS_LP_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access L2MEM
+ *  monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define PMS_LP_MM_L2MEM_MON_ALLOW_M  (PMS_LP_MM_L2MEM_MON_ALLOW_V << PMS_LP_MM_L2MEM_MON_ALLOW_S)
+#define PMS_LP_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define PMS_LP_MM_L2MEM_MON_ALLOW_S  9
+/** PMS_LP_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access SPM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_SPM_MON_ALLOW    (BIT(10))
+#define PMS_LP_MM_SPM_MON_ALLOW_M  (PMS_LP_MM_SPM_MON_ALLOW_V << PMS_LP_MM_SPM_MON_ALLOW_S)
+#define PMS_LP_MM_SPM_MON_ALLOW_V  0x00000001U
+#define PMS_LP_MM_SPM_MON_ALLOW_S  10
+/** PMS_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_CACHE_ALLOW    (BIT(11))
+#define PMS_LP_MM_CACHE_ALLOW_M  (PMS_LP_MM_CACHE_ALLOW_V << PMS_LP_MM_CACHE_ALLOW_S)
+#define PMS_LP_MM_CACHE_ALLOW_V  0x00000001U
+#define PMS_LP_MM_CACHE_ALLOW_S  11
+
+/** PMS_LP_MM_PMS_REG1_REG register
+ *  Permission control register1 for the LP CPU in machine mode
+ */
+#define PMS_LP_MM_PMS_REG1_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x30)
+/** PMS_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP
+ *  high-speed USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define PMS_LP_MM_HP_USBOTG_ALLOW_M  (PMS_LP_MM_HP_USBOTG_ALLOW_V << PMS_LP_MM_HP_USBOTG_ALLOW_S)
+#define PMS_LP_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_USBOTG_ALLOW_S  0
+/** PMS_LP_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP
+ *  full-speed USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define PMS_LP_MM_HP_USBOTG11_ALLOW_M  (PMS_LP_MM_HP_USBOTG11_ALLOW_V << PMS_LP_MM_HP_USBOTG11_ALLOW_S)
+#define PMS_LP_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_USBOTG11_ALLOW_S  1
+/** PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP
+ *  full-speed USB 2.0 OTG's wrap.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_M  (PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_V << PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** PMS_LP_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP DW-GDMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_GDMA_ALLOW    (BIT(3))
+#define PMS_LP_MM_HP_GDMA_ALLOW_M  (PMS_LP_MM_HP_GDMA_ALLOW_V << PMS_LP_MM_HP_GDMA_ALLOW_S)
+#define PMS_LP_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_GDMA_ALLOW_S  3
+/** PMS_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP SDMMC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define PMS_LP_MM_HP_SDMMC_ALLOW_M  (PMS_LP_MM_HP_SDMMC_ALLOW_V << PMS_LP_MM_HP_SDMMC_ALLOW_S)
+#define PMS_LP_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_SDMMC_ALLOW_S  5
+/** PMS_LP_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access GDMA-AHB.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define PMS_LP_MM_HP_AHB_PDMA_ALLOW_M  (PMS_LP_MM_HP_AHB_PDMA_ALLOW_V << PMS_LP_MM_HP_AHB_PDMA_ALLOW_S)
+#define PMS_LP_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_AHB_PDMA_ALLOW_S  6
+/** PMS_LP_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP JPEG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_JPEG_ALLOW    (BIT(7))
+#define PMS_LP_MM_HP_JPEG_ALLOW_M  (PMS_LP_MM_HP_JPEG_ALLOW_V << PMS_LP_MM_HP_JPEG_ALLOW_S)
+#define PMS_LP_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_JPEG_ALLOW_S  7
+/** PMS_LP_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP PPA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_PPA_ALLOW    (BIT(8))
+#define PMS_LP_MM_HP_PPA_ALLOW_M  (PMS_LP_MM_HP_PPA_ALLOW_V << PMS_LP_MM_HP_PPA_ALLOW_S)
+#define PMS_LP_MM_HP_PPA_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PPA_ALLOW_S  8
+/** PMS_LP_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define PMS_LP_MM_HP_DMA2D_ALLOW_M  (PMS_LP_MM_HP_DMA2D_ALLOW_V << PMS_LP_MM_HP_DMA2D_ALLOW_S)
+#define PMS_LP_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_DMA2D_ALLOW_S  9
+/** PMS_LP_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP key
+ *  manager.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW_M  (PMS_LP_MM_HP_KEY_MANAGER_ALLOW_V << PMS_LP_MM_HP_KEY_MANAGER_ALLOW_S)
+#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** PMS_LP_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP GDMA-AXI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define PMS_LP_MM_HP_AXI_PDMA_ALLOW_M  (PMS_LP_MM_HP_AXI_PDMA_ALLOW_V << PMS_LP_MM_HP_AXI_PDMA_ALLOW_S)
+#define PMS_LP_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_AXI_PDMA_ALLOW_S  11
+/** PMS_LP_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP flash
+ *  MSPI controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_FLASH_ALLOW    (BIT(12))
+#define PMS_LP_MM_HP_FLASH_ALLOW_M  (PMS_LP_MM_HP_FLASH_ALLOW_V << PMS_LP_MM_HP_FLASH_ALLOW_S)
+#define PMS_LP_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_FLASH_ALLOW_S  12
+/** PMS_LP_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP PSRAM
+ *  MSPI controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define PMS_LP_MM_HP_PSRAM_ALLOW_M  (PMS_LP_MM_HP_PSRAM_ALLOW_V << PMS_LP_MM_HP_PSRAM_ALLOW_S)
+#define PMS_LP_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PSRAM_ALLOW_S  13
+/** PMS_LP_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP CRYPTO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define PMS_LP_MM_HP_CRYPTO_ALLOW_M  (PMS_LP_MM_HP_CRYPTO_ALLOW_V << PMS_LP_MM_HP_CRYPTO_ALLOW_S)
+#define PMS_LP_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_CRYPTO_ALLOW_S  14
+/** PMS_LP_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP EMAC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_GMAC_ALLOW    (BIT(15))
+#define PMS_LP_MM_HP_GMAC_ALLOW_M  (PMS_LP_MM_HP_GMAC_ALLOW_V << PMS_LP_MM_HP_GMAC_ALLOW_S)
+#define PMS_LP_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_GMAC_ALLOW_S  15
+/** PMS_LP_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP
+ *  high-speed USB 2.0 OTG PHY.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define PMS_LP_MM_HP_USB_PHY_ALLOW_M  (PMS_LP_MM_HP_USB_PHY_ALLOW_V << PMS_LP_MM_HP_USB_PHY_ALLOW_S)
+#define PMS_LP_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_USB_PHY_ALLOW_S  16
+/** PMS_LP_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP PVT.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_LP_MM_HP_PVT_ALLOW    (BIT(17))
+#define PMS_LP_MM_HP_PVT_ALLOW_M  (PMS_LP_MM_HP_PVT_ALLOW_V << PMS_LP_MM_HP_PVT_ALLOW_S)
+#define PMS_LP_MM_HP_PVT_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PVT_ALLOW_S  17
+/** PMS_LP_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP MIPI CSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define PMS_LP_MM_HP_CSI_HOST_ALLOW_M  (PMS_LP_MM_HP_CSI_HOST_ALLOW_V << PMS_LP_MM_HP_CSI_HOST_ALLOW_S)
+#define PMS_LP_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_CSI_HOST_ALLOW_S  18
+/** PMS_LP_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP MIPI DSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define PMS_LP_MM_HP_DSI_HOST_ALLOW_M  (PMS_LP_MM_HP_DSI_HOST_ALLOW_V << PMS_LP_MM_HP_DSI_HOST_ALLOW_S)
+#define PMS_LP_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_DSI_HOST_ALLOW_S  19
+/** PMS_LP_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP ISP.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_ISP_ALLOW    (BIT(20))
+#define PMS_LP_MM_HP_ISP_ALLOW_M  (PMS_LP_MM_HP_ISP_ALLOW_V << PMS_LP_MM_HP_ISP_ALLOW_S)
+#define PMS_LP_MM_HP_ISP_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_ISP_ALLOW_S  20
+/** PMS_LP_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP H264
+ *  Encoder.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define PMS_LP_MM_HP_H264_CORE_ALLOW_M  (PMS_LP_MM_HP_H264_CORE_ALLOW_V << PMS_LP_MM_HP_H264_CORE_ALLOW_S)
+#define PMS_LP_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_H264_CORE_ALLOW_S  21
+/** PMS_LP_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP RMT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_RMT_ALLOW    (BIT(22))
+#define PMS_LP_MM_HP_RMT_ALLOW_M  (PMS_LP_MM_HP_RMT_ALLOW_V << PMS_LP_MM_HP_RMT_ALLOW_S)
+#define PMS_LP_MM_HP_RMT_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_RMT_ALLOW_S  22
+/** PMS_LP_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP bit
+ *  scrambler.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_M  (PMS_LP_MM_HP_BITSRAMBLER_ALLOW_V << PMS_LP_MM_HP_BITSRAMBLER_ALLOW_S)
+#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** PMS_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP AXI ICM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define PMS_LP_MM_HP_AXI_ICM_ALLOW_M  (PMS_LP_MM_HP_AXI_ICM_ALLOW_V << PMS_LP_MM_HP_AXI_ICM_ALLOW_S)
+#define PMS_LP_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_AXI_ICM_ALLOW_S  24
+/** PMS_LP_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access
+ *  HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define PMS_LP_MM_HP_PERI_PMS_ALLOW_M  (PMS_LP_MM_HP_PERI_PMS_ALLOW_V << PMS_LP_MM_HP_PERI_PMS_ALLOW_S)
+#define PMS_LP_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PERI_PMS_ALLOW_S  25
+/** PMS_LP_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access
+ *  LP2HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_M  (PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_V << PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** PMS_LP_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access
+ *  HP_DMA_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_DMA_PMS_ALLOW    (BIT(27))
+#define PMS_LP_MM_DMA_PMS_ALLOW_M  (PMS_LP_MM_DMA_PMS_ALLOW_V << PMS_LP_MM_DMA_PMS_ALLOW_S)
+#define PMS_LP_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_DMA_PMS_ALLOW_S  27
+/** PMS_LP_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_M  (PMS_LP_MM_HP_H264_DMA2D_ALLOW_V << PMS_LP_MM_HP_H264_DMA2D_ALLOW_S)
+#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_S  28
+
+/** PMS_LP_MM_PMS_REG2_REG register
+ *  Permission control register2 for the LP CPU in machine mode
+ */
+#define PMS_LP_MM_PMS_REG2_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0xa4)
+/** PMS_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP MCPWM0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define PMS_LP_MM_HP_MCPWM0_ALLOW_M  (PMS_LP_MM_HP_MCPWM0_ALLOW_V << PMS_LP_MM_HP_MCPWM0_ALLOW_S)
+#define PMS_LP_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_MCPWM0_ALLOW_S  0
+/** PMS_LP_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP MCPWM1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define PMS_LP_MM_HP_MCPWM1_ALLOW_M  (PMS_LP_MM_HP_MCPWM1_ALLOW_V << PMS_LP_MM_HP_MCPWM1_ALLOW_S)
+#define PMS_LP_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_MCPWM1_ALLOW_S  1
+/** PMS_LP_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP timer
+ *  group0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_M  (PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_V << PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** PMS_LP_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP timer
+ *  group1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_M  (PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_V << PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** PMS_LP_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I2C0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I2C0_ALLOW    (BIT(4))
+#define PMS_LP_MM_HP_I2C0_ALLOW_M  (PMS_LP_MM_HP_I2C0_ALLOW_V << PMS_LP_MM_HP_I2C0_ALLOW_S)
+#define PMS_LP_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I2C0_ALLOW_S  4
+/** PMS_LP_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I2C1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I2C1_ALLOW    (BIT(5))
+#define PMS_LP_MM_HP_I2C1_ALLOW_M  (PMS_LP_MM_HP_I2C1_ALLOW_V << PMS_LP_MM_HP_I2C1_ALLOW_S)
+#define PMS_LP_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I2C1_ALLOW_S  5
+/** PMS_LP_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I2S0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I2S0_ALLOW    (BIT(6))
+#define PMS_LP_MM_HP_I2S0_ALLOW_M  (PMS_LP_MM_HP_I2S0_ALLOW_V << PMS_LP_MM_HP_I2S0_ALLOW_S)
+#define PMS_LP_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I2S0_ALLOW_S  6
+/** PMS_LP_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I2S1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I2S1_ALLOW    (BIT(7))
+#define PMS_LP_MM_HP_I2S1_ALLOW_M  (PMS_LP_MM_HP_I2S1_ALLOW_V << PMS_LP_MM_HP_I2S1_ALLOW_S)
+#define PMS_LP_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I2S1_ALLOW_S  7
+/** PMS_LP_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I2S2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I2S2_ALLOW    (BIT(8))
+#define PMS_LP_MM_HP_I2S2_ALLOW_M  (PMS_LP_MM_HP_I2S2_ALLOW_V << PMS_LP_MM_HP_I2S2_ALLOW_S)
+#define PMS_LP_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I2S2_ALLOW_S  8
+/** PMS_LP_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP PCNT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_PCNT_ALLOW    (BIT(9))
+#define PMS_LP_MM_HP_PCNT_ALLOW_M  (PMS_LP_MM_HP_PCNT_ALLOW_V << PMS_LP_MM_HP_PCNT_ALLOW_S)
+#define PMS_LP_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PCNT_ALLOW_S  9
+/** PMS_LP_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UART0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UART0_ALLOW    (BIT(10))
+#define PMS_LP_MM_HP_UART0_ALLOW_M  (PMS_LP_MM_HP_UART0_ALLOW_V << PMS_LP_MM_HP_UART0_ALLOW_S)
+#define PMS_LP_MM_HP_UART0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UART0_ALLOW_S  10
+/** PMS_LP_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UART1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UART1_ALLOW    (BIT(11))
+#define PMS_LP_MM_HP_UART1_ALLOW_M  (PMS_LP_MM_HP_UART1_ALLOW_V << PMS_LP_MM_HP_UART1_ALLOW_S)
+#define PMS_LP_MM_HP_UART1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UART1_ALLOW_S  11
+/** PMS_LP_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UART2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UART2_ALLOW    (BIT(12))
+#define PMS_LP_MM_HP_UART2_ALLOW_M  (PMS_LP_MM_HP_UART2_ALLOW_V << PMS_LP_MM_HP_UART2_ALLOW_S)
+#define PMS_LP_MM_HP_UART2_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UART2_ALLOW_S  12
+/** PMS_LP_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UART3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UART3_ALLOW    (BIT(13))
+#define PMS_LP_MM_HP_UART3_ALLOW_M  (PMS_LP_MM_HP_UART3_ALLOW_V << PMS_LP_MM_HP_UART3_ALLOW_S)
+#define PMS_LP_MM_HP_UART3_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UART3_ALLOW_S  13
+/** PMS_LP_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UART4.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UART4_ALLOW    (BIT(14))
+#define PMS_LP_MM_HP_UART4_ALLOW_M  (PMS_LP_MM_HP_UART4_ALLOW_V << PMS_LP_MM_HP_UART4_ALLOW_S)
+#define PMS_LP_MM_HP_UART4_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UART4_ALLOW_S  14
+/** PMS_LP_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP PARLIO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define PMS_LP_MM_HP_PARLIO_ALLOW_M  (PMS_LP_MM_HP_PARLIO_ALLOW_V << PMS_LP_MM_HP_PARLIO_ALLOW_S)
+#define PMS_LP_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PARLIO_ALLOW_S  15
+/** PMS_LP_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP GP-SPI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define PMS_LP_MM_HP_GPSPI2_ALLOW_M  (PMS_LP_MM_HP_GPSPI2_ALLOW_V << PMS_LP_MM_HP_GPSPI2_ALLOW_S)
+#define PMS_LP_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_GPSPI2_ALLOW_S  16
+/** PMS_LP_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP GP-SPI3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define PMS_LP_MM_HP_GPSPI3_ALLOW_M  (PMS_LP_MM_HP_GPSPI3_ALLOW_V << PMS_LP_MM_HP_GPSPI3_ALLOW_S)
+#define PMS_LP_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_GPSPI3_ALLOW_S  17
+/** PMS_LP_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP
+ *  USB/Serial JTAG Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define PMS_LP_MM_HP_USBDEVICE_ALLOW_M  (PMS_LP_MM_HP_USBDEVICE_ALLOW_V << PMS_LP_MM_HP_USBDEVICE_ALLOW_S)
+#define PMS_LP_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_USBDEVICE_ALLOW_S  18
+/** PMS_LP_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP LEDC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_LEDC_ALLOW    (BIT(19))
+#define PMS_LP_MM_HP_LEDC_ALLOW_M  (PMS_LP_MM_HP_LEDC_ALLOW_V << PMS_LP_MM_HP_LEDC_ALLOW_S)
+#define PMS_LP_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_LEDC_ALLOW_S  19
+/** PMS_LP_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP ETM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_ETM_ALLOW    (BIT(21))
+#define PMS_LP_MM_HP_ETM_ALLOW_M  (PMS_LP_MM_HP_ETM_ALLOW_V << PMS_LP_MM_HP_ETM_ALLOW_S)
+#define PMS_LP_MM_HP_ETM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_ETM_ALLOW_S  21
+/** PMS_LP_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP interrupt
+ *  matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define PMS_LP_MM_HP_INTRMTX_ALLOW_M  (PMS_LP_MM_HP_INTRMTX_ALLOW_V << PMS_LP_MM_HP_INTRMTX_ALLOW_S)
+#define PMS_LP_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_INTRMTX_ALLOW_S  22
+/** PMS_LP_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP TWAI0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define PMS_LP_MM_HP_TWAI0_ALLOW_M  (PMS_LP_MM_HP_TWAI0_ALLOW_V << PMS_LP_MM_HP_TWAI0_ALLOW_S)
+#define PMS_LP_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_TWAI0_ALLOW_S  23
+/** PMS_LP_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP TWAI1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define PMS_LP_MM_HP_TWAI1_ALLOW_M  (PMS_LP_MM_HP_TWAI1_ALLOW_V << PMS_LP_MM_HP_TWAI1_ALLOW_S)
+#define PMS_LP_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_TWAI1_ALLOW_S  24
+/** PMS_LP_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP TWAI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define PMS_LP_MM_HP_TWAI2_ALLOW_M  (PMS_LP_MM_HP_TWAI2_ALLOW_V << PMS_LP_MM_HP_TWAI2_ALLOW_S)
+#define PMS_LP_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_TWAI2_ALLOW_S  25
+/** PMS_LP_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I3C
+ *  master controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define PMS_LP_MM_HP_I3C_MST_ALLOW_M  (PMS_LP_MM_HP_I3C_MST_ALLOW_V << PMS_LP_MM_HP_I3C_MST_ALLOW_S)
+#define PMS_LP_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I3C_MST_ALLOW_S  26
+/** PMS_LP_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I3C slave
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define PMS_LP_MM_HP_I3C_SLV_ALLOW_M  (PMS_LP_MM_HP_I3C_SLV_ALLOW_V << PMS_LP_MM_HP_I3C_SLV_ALLOW_S)
+#define PMS_LP_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I3C_SLV_ALLOW_S  27
+/** PMS_LP_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP LCD_CAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define PMS_LP_MM_HP_LCDCAM_ALLOW_M  (PMS_LP_MM_HP_LCDCAM_ALLOW_V << PMS_LP_MM_HP_LCDCAM_ALLOW_S)
+#define PMS_LP_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_LCDCAM_ALLOW_S  28
+/** PMS_LP_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_ADC_ALLOW    (BIT(30))
+#define PMS_LP_MM_HP_ADC_ALLOW_M  (PMS_LP_MM_HP_ADC_ALLOW_V << PMS_LP_MM_HP_ADC_ALLOW_S)
+#define PMS_LP_MM_HP_ADC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_ADC_ALLOW_S  30
+/** PMS_LP_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UHCI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UHCI_ALLOW    (BIT(31))
+#define PMS_LP_MM_HP_UHCI_ALLOW_M  (PMS_LP_MM_HP_UHCI_ALLOW_V << PMS_LP_MM_HP_UHCI_ALLOW_S)
+#define PMS_LP_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UHCI_ALLOW_S  31
+
+/** PMS_LP_MM_PMS_REG3_REG register
+ *  Permission control register3 for the LP CPU in machine mode
+ */
+#define PMS_LP_MM_PMS_REG3_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x11c)
+/** PMS_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP GPIO
+ *  Matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_GPIO_ALLOW    (BIT(0))
+#define PMS_LP_MM_HP_GPIO_ALLOW_M  (PMS_LP_MM_HP_GPIO_ALLOW_V << PMS_LP_MM_HP_GPIO_ALLOW_S)
+#define PMS_LP_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_GPIO_ALLOW_S  0
+/** PMS_LP_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define PMS_LP_MM_HP_IOMUX_ALLOW_M  (PMS_LP_MM_HP_IOMUX_ALLOW_V << PMS_LP_MM_HP_IOMUX_ALLOW_S)
+#define PMS_LP_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_IOMUX_ALLOW_S  1
+/** PMS_LP_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP system
+ *  timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define PMS_LP_MM_HP_SYSTIMER_ALLOW_M  (PMS_LP_MM_HP_SYSTIMER_ALLOW_V << PMS_LP_MM_HP_SYSTIMER_ALLOW_S)
+#define PMS_LP_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_SYSTIMER_ALLOW_S  2
+/** PMS_LP_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP system
+ *  register.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define PMS_LP_MM_HP_SYS_REG_ALLOW_M  (PMS_LP_MM_HP_SYS_REG_ALLOW_V << PMS_LP_MM_HP_SYS_REG_ALLOW_S)
+#define PMS_LP_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_SYS_REG_ALLOW_S  3
+/** PMS_LP_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access
+ *  HP_SYS_CLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define PMS_LP_MM_HP_CLKRST_ALLOW_M  (PMS_LP_MM_HP_CLKRST_ALLOW_V << PMS_LP_MM_HP_CLKRST_ALLOW_S)
+#define PMS_LP_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_CLKRST_ALLOW_S  4
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_struct.h
new file mode 100644
index 0000000000..6fe0b0dc70
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_struct.h
@@ -0,0 +1,414 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: TEE LP2HP PMS DATE REG */
+/** Type of lp2hp_pms_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tee_date : R/W; bitpos: [31:0]; default: 2363943;
+         *  NA
+         */
+        uint32_t tee_date:32;
+    };
+    uint32_t val;
+} tee_lp2hp_pms_date_reg_t;
+
+
+/** Group: TEE PMS CLK EN REG */
+/** Type of pms_clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_pms_clk_en_reg_t;
+
+
+/** Group: TEE LP MM PMS REG0 REG */
+/** Type of lp_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_mm_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_psram_allow:1;
+        /** reg_lp_mm_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_flash_allow:1;
+        /** reg_lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_l2mem_allow:1;
+        /** reg_lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_l2rom_allow:1;
+        uint32_t reserved_4:2;
+        /** reg_lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_trace0_allow:1;
+        /** reg_lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_trace1_allow:1;
+        /** reg_lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_cpu_bus_mon_allow:1;
+        /** reg_lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_l2mem_mon_allow:1;
+        /** reg_lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_tcm_mon_allow:1;
+        /** reg_lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_cache_allow:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} tee_lp_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE LP MM PMS REG1 REG */
+/** Type of lp_mm_pms_reg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_usbotg_allow:1;
+        /** reg_lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_usbotg11_allow:1;
+        /** reg_lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_usbotg11_wrap_allow:1;
+        /** reg_lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_gdma_allow:1;
+        /** reg_lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_regdma_allow:1;
+        /** reg_lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_sdmmc_allow:1;
+        /** reg_lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_ahb_pdma_allow:1;
+        /** reg_lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_jpeg_allow:1;
+        /** reg_lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_ppa_allow:1;
+        /** reg_lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_dma2d_allow:1;
+        /** reg_lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_key_manager_allow:1;
+        /** reg_lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_axi_pdma_allow:1;
+        /** reg_lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_flash_allow:1;
+        /** reg_lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_psram_allow:1;
+        /** reg_lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_crypto_allow:1;
+        /** reg_lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_gmac_allow:1;
+        /** reg_lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_usb_phy_allow:1;
+        /** reg_lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_pvt_allow:1;
+        /** reg_lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_csi_host_allow:1;
+        /** reg_lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_dsi_host_allow:1;
+        /** reg_lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_isp_allow:1;
+        /** reg_lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_h264_core_allow:1;
+        /** reg_lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_rmt_allow:1;
+        /** reg_lp_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_bitsrambler_allow:1;
+        /** reg_lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_axi_icm_allow:1;
+        /** reg_lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_peri_pms_allow:1;
+        /** reg_lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp2hp_peri_pms_allow:1;
+        /** reg_lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_dma_pms_allow:1;
+        /** reg_lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_h264_dma2d_allow:1;
+        /** reg_lp_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_axi_perf_mon_allow:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_lp_mm_pms_reg1_reg_t;
+
+
+/** Group: TEE LP MM PMS REG2 REG */
+/** Type of lp_mm_pms_reg2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_mcpwm0_allow:1;
+        /** reg_lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_mcpwm1_allow:1;
+        /** reg_lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_timer_group0_allow:1;
+        /** reg_lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_timer_group1_allow:1;
+        /** reg_lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i2c0_allow:1;
+        /** reg_lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i2c1_allow:1;
+        /** reg_lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i2s0_allow:1;
+        /** reg_lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i2s1_allow:1;
+        /** reg_lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i2s2_allow:1;
+        /** reg_lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_pcnt_allow:1;
+        /** reg_lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uart0_allow:1;
+        /** reg_lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uart1_allow:1;
+        /** reg_lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uart2_allow:1;
+        /** reg_lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uart3_allow:1;
+        /** reg_lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uart4_allow:1;
+        /** reg_lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_parlio_allow:1;
+        /** reg_lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_gpspi2_allow:1;
+        /** reg_lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_gpspi3_allow:1;
+        /** reg_lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_usbdevice_allow:1;
+        /** reg_lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_ledc_allow:1;
+        uint32_t reserved_20:1;
+        /** reg_lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_etm_allow:1;
+        /** reg_lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_intrmtx_allow:1;
+        /** reg_lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_twai0_allow:1;
+        /** reg_lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_twai1_allow:1;
+        /** reg_lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_twai2_allow:1;
+        /** reg_lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i3c_mst_allow:1;
+        /** reg_lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i3c_slv_allow:1;
+        /** reg_lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_lcdcam_allow:1;
+        uint32_t reserved_29:1;
+        /** reg_lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_adc_allow:1;
+        /** reg_lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uhci_allow:1;
+    };
+    uint32_t val;
+} tee_lp_mm_pms_reg2_reg_t;
+
+
+/** Group: TEE LP MM PMS REG3 REG */
+/** Type of lp_mm_pms_reg3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_gpio_allow:1;
+        /** reg_lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_iomux_allow:1;
+        /** reg_lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_systimer_allow:1;
+        /** reg_lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_sys_reg_allow:1;
+        /** reg_lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_clkrst_allow:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} tee_lp_mm_pms_reg3_reg_t;
+
+
+typedef struct {
+    volatile tee_lp2hp_pms_date_reg_t lp2hp_pms_date;
+    volatile tee_pms_clk_en_reg_t pms_clk_en;
+    volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
+    uint32_t reserved_00c[9];
+    volatile tee_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1;
+    uint32_t reserved_034[28];
+    volatile tee_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2;
+    uint32_t reserved_0a8[29];
+    volatile tee_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3;
+} tee_dev_t;
+
+extern tee_dev_t LP2HP_PERI_PMS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dev_t) == 0x120, "Invalid size of tee_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_adc_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_adc_eco5_reg.h
new file mode 100644
index 0000000000..ef3629ede9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_adc_eco5_reg.h
@@ -0,0 +1,704 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RTCADC_READER1_CTRL_REG register
+ *  Control the read operation of ADC1.
+ */
+#define RTCADC_READER1_CTRL_REG (DR_REG_RTCADC_BASE + 0x0)
+/** RTCADC_SAR1_CLK_DIV : R/W; bitpos: [7:0]; default: 2;
+ *  Clock divider.
+ */
+#define RTCADC_SAR1_CLK_DIV    0x000000FFU
+#define RTCADC_SAR1_CLK_DIV_M  (RTCADC_SAR1_CLK_DIV_V << RTCADC_SAR1_CLK_DIV_S)
+#define RTCADC_SAR1_CLK_DIV_V  0x000000FFU
+#define RTCADC_SAR1_CLK_DIV_S  0
+/** RTCADC_SAR1_DATA_INV : R/W; bitpos: [28]; default: 0;
+ *  Invert SAR ADC1 data.
+ */
+#define RTCADC_SAR1_DATA_INV    (BIT(28))
+#define RTCADC_SAR1_DATA_INV_M  (RTCADC_SAR1_DATA_INV_V << RTCADC_SAR1_DATA_INV_S)
+#define RTCADC_SAR1_DATA_INV_V  0x00000001U
+#define RTCADC_SAR1_DATA_INV_S  28
+/** RTCADC_SAR1_INT_EN : R/W; bitpos: [29]; default: 1;
+ *  Enable saradc1 to send out interrupt.
+ */
+#define RTCADC_SAR1_INT_EN    (BIT(29))
+#define RTCADC_SAR1_INT_EN_M  (RTCADC_SAR1_INT_EN_V << RTCADC_SAR1_INT_EN_S)
+#define RTCADC_SAR1_INT_EN_V  0x00000001U
+#define RTCADC_SAR1_INT_EN_S  29
+/** RTCADC_SAR1_EN_PAD_FORCE_ENABLE : R/W; bitpos: [31:30]; default: 0;
+ *  Force enable adc en_pad to analog circuit 2'b11: force enable .
+ */
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE    0x00000003U
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_M  (RTCADC_SAR1_EN_PAD_FORCE_ENABLE_V << RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S)
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_V  0x00000003U
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S  30
+
+/** RTCADC_MEAS1_CTRL2_REG register
+ *  ADC1 configuration registers.
+ */
+#define RTCADC_MEAS1_CTRL2_REG (DR_REG_RTCADC_BASE + 0xc)
+/** RTCADC_MEAS1_DATA_SAR : RO; bitpos: [15:0]; default: 0;
+ *  SAR ADC1 data.
+ */
+#define RTCADC_MEAS1_DATA_SAR    0x0000FFFFU
+#define RTCADC_MEAS1_DATA_SAR_M  (RTCADC_MEAS1_DATA_SAR_V << RTCADC_MEAS1_DATA_SAR_S)
+#define RTCADC_MEAS1_DATA_SAR_V  0x0000FFFFU
+#define RTCADC_MEAS1_DATA_SAR_S  0
+/** RTCADC_MEAS1_DONE_SAR : RO; bitpos: [16]; default: 0;
+ *  SAR ADC1 conversion done indication.
+ */
+#define RTCADC_MEAS1_DONE_SAR    (BIT(16))
+#define RTCADC_MEAS1_DONE_SAR_M  (RTCADC_MEAS1_DONE_SAR_V << RTCADC_MEAS1_DONE_SAR_S)
+#define RTCADC_MEAS1_DONE_SAR_V  0x00000001U
+#define RTCADC_MEAS1_DONE_SAR_S  16
+/** RTCADC_MEAS1_START_SAR : R/W; bitpos: [17]; default: 0;
+ *  SAR ADC1 controller (in RTC) starts conversion.
+ */
+#define RTCADC_MEAS1_START_SAR    (BIT(17))
+#define RTCADC_MEAS1_START_SAR_M  (RTCADC_MEAS1_START_SAR_V << RTCADC_MEAS1_START_SAR_S)
+#define RTCADC_MEAS1_START_SAR_V  0x00000001U
+#define RTCADC_MEAS1_START_SAR_S  17
+/** RTCADC_MEAS1_START_FORCE : R/W; bitpos: [18]; default: 0;
+ *  1: SAR ADC1 controller (in RTC) is started by SW.
+ */
+#define RTCADC_MEAS1_START_FORCE    (BIT(18))
+#define RTCADC_MEAS1_START_FORCE_M  (RTCADC_MEAS1_START_FORCE_V << RTCADC_MEAS1_START_FORCE_S)
+#define RTCADC_MEAS1_START_FORCE_V  0x00000001U
+#define RTCADC_MEAS1_START_FORCE_S  18
+/** RTCADC_SAR1_EN_PAD : R/W; bitpos: [30:19]; default: 0;
+ *  SAR ADC1 pad enable bitmap.
+ */
+#define RTCADC_SAR1_EN_PAD    0x00000FFFU
+#define RTCADC_SAR1_EN_PAD_M  (RTCADC_SAR1_EN_PAD_V << RTCADC_SAR1_EN_PAD_S)
+#define RTCADC_SAR1_EN_PAD_V  0x00000FFFU
+#define RTCADC_SAR1_EN_PAD_S  19
+/** RTCADC_SAR1_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0;
+ *  1: SAR ADC1 pad enable bitmap is controlled by SW.
+ */
+#define RTCADC_SAR1_EN_PAD_FORCE    (BIT(31))
+#define RTCADC_SAR1_EN_PAD_FORCE_M  (RTCADC_SAR1_EN_PAD_FORCE_V << RTCADC_SAR1_EN_PAD_FORCE_S)
+#define RTCADC_SAR1_EN_PAD_FORCE_V  0x00000001U
+#define RTCADC_SAR1_EN_PAD_FORCE_S  31
+
+/** RTCADC_MEAS1_MUX_REG register
+ *  SAR ADC1 MUX register.
+ */
+#define RTCADC_MEAS1_MUX_REG (DR_REG_RTCADC_BASE + 0x10)
+/** RTCADC_SAR1_DIG_FORCE : R/W; bitpos: [31]; default: 0;
+ *  1: SAR ADC1 controlled by DIG ADC1 CTRL.
+ */
+#define RTCADC_SAR1_DIG_FORCE    (BIT(31))
+#define RTCADC_SAR1_DIG_FORCE_M  (RTCADC_SAR1_DIG_FORCE_V << RTCADC_SAR1_DIG_FORCE_S)
+#define RTCADC_SAR1_DIG_FORCE_V  0x00000001U
+#define RTCADC_SAR1_DIG_FORCE_S  31
+
+/** RTCADC_ATTEN1_REG register
+ *  ADC1 attenuation registers.
+ */
+#define RTCADC_ATTEN1_REG (DR_REG_RTCADC_BASE + 0x14)
+/** RTCADC_SAR1_ATTEN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  2-bit attenuation for each pad.
+ */
+#define RTCADC_SAR1_ATTEN    0xFFFFFFFFU
+#define RTCADC_SAR1_ATTEN_M  (RTCADC_SAR1_ATTEN_V << RTCADC_SAR1_ATTEN_S)
+#define RTCADC_SAR1_ATTEN_V  0xFFFFFFFFU
+#define RTCADC_SAR1_ATTEN_S  0
+
+/** RTCADC_READER2_CTRL_REG register
+ *  Control the read operation of ADC2.
+ */
+#define RTCADC_READER2_CTRL_REG (DR_REG_RTCADC_BASE + 0x24)
+/** RTCADC_SAR2_CLK_DIV : R/W; bitpos: [7:0]; default: 2;
+ *  Clock divider.
+ */
+#define RTCADC_SAR2_CLK_DIV    0x000000FFU
+#define RTCADC_SAR2_CLK_DIV_M  (RTCADC_SAR2_CLK_DIV_V << RTCADC_SAR2_CLK_DIV_S)
+#define RTCADC_SAR2_CLK_DIV_V  0x000000FFU
+#define RTCADC_SAR2_CLK_DIV_S  0
+/** RTCADC_SAR2_WAIT_ARB_CYCLE : R/W; bitpos: [17:16]; default: 1;
+ *  Wait arbit stable after sar_done.
+ */
+#define RTCADC_SAR2_WAIT_ARB_CYCLE    0x00000003U
+#define RTCADC_SAR2_WAIT_ARB_CYCLE_M  (RTCADC_SAR2_WAIT_ARB_CYCLE_V << RTCADC_SAR2_WAIT_ARB_CYCLE_S)
+#define RTCADC_SAR2_WAIT_ARB_CYCLE_V  0x00000003U
+#define RTCADC_SAR2_WAIT_ARB_CYCLE_S  16
+/** RTCADC_SAR2_EN_PAD_FORCE_ENABLE : R/W; bitpos: [28:27]; default: 0;
+ *  Force enable adc en_pad to analog circuit 2'b11: force enable .
+ */
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE    0x00000003U
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_M  (RTCADC_SAR2_EN_PAD_FORCE_ENABLE_V << RTCADC_SAR2_EN_PAD_FORCE_ENABLE_S)
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_V  0x00000003U
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_S  27
+/** RTCADC_SAR2_DATA_INV : R/W; bitpos: [29]; default: 0;
+ *  Invert SAR ADC2 data.
+ */
+#define RTCADC_SAR2_DATA_INV    (BIT(29))
+#define RTCADC_SAR2_DATA_INV_M  (RTCADC_SAR2_DATA_INV_V << RTCADC_SAR2_DATA_INV_S)
+#define RTCADC_SAR2_DATA_INV_V  0x00000001U
+#define RTCADC_SAR2_DATA_INV_S  29
+/** RTCADC_SAR2_INT_EN : R/W; bitpos: [30]; default: 1;
+ *  Enable saradc2 to send out interrupt.
+ */
+#define RTCADC_SAR2_INT_EN    (BIT(30))
+#define RTCADC_SAR2_INT_EN_M  (RTCADC_SAR2_INT_EN_V << RTCADC_SAR2_INT_EN_S)
+#define RTCADC_SAR2_INT_EN_V  0x00000001U
+#define RTCADC_SAR2_INT_EN_S  30
+
+/** RTCADC_MEAS2_CTRL1_REG register
+ *  ADC2 configuration registers.
+ */
+#define RTCADC_MEAS2_CTRL1_REG (DR_REG_RTCADC_BASE + 0x2c)
+/** RTCADC_SAR2_CNTL_STATE : RO; bitpos: [2:0]; default: 0;
+ *  saradc2_cntl_fsm.
+ */
+#define RTCADC_SAR2_CNTL_STATE    0x00000007U
+#define RTCADC_SAR2_CNTL_STATE_M  (RTCADC_SAR2_CNTL_STATE_V << RTCADC_SAR2_CNTL_STATE_S)
+#define RTCADC_SAR2_CNTL_STATE_V  0x00000007U
+#define RTCADC_SAR2_CNTL_STATE_S  0
+/** RTCADC_SAR2_PWDET_CAL_EN : R/W; bitpos: [3]; default: 0;
+ *  RTC control pwdet enable.
+ */
+#define RTCADC_SAR2_PWDET_CAL_EN    (BIT(3))
+#define RTCADC_SAR2_PWDET_CAL_EN_M  (RTCADC_SAR2_PWDET_CAL_EN_V << RTCADC_SAR2_PWDET_CAL_EN_S)
+#define RTCADC_SAR2_PWDET_CAL_EN_V  0x00000001U
+#define RTCADC_SAR2_PWDET_CAL_EN_S  3
+/** RTCADC_SAR2_PKDET_CAL_EN : R/W; bitpos: [4]; default: 0;
+ *  RTC control pkdet enable.
+ */
+#define RTCADC_SAR2_PKDET_CAL_EN    (BIT(4))
+#define RTCADC_SAR2_PKDET_CAL_EN_M  (RTCADC_SAR2_PKDET_CAL_EN_V << RTCADC_SAR2_PKDET_CAL_EN_S)
+#define RTCADC_SAR2_PKDET_CAL_EN_V  0x00000001U
+#define RTCADC_SAR2_PKDET_CAL_EN_S  4
+/** RTCADC_SAR2_EN_TEST : R/W; bitpos: [5]; default: 0;
+ *  SAR2_EN_TEST.
+ */
+#define RTCADC_SAR2_EN_TEST    (BIT(5))
+#define RTCADC_SAR2_EN_TEST_M  (RTCADC_SAR2_EN_TEST_V << RTCADC_SAR2_EN_TEST_S)
+#define RTCADC_SAR2_EN_TEST_V  0x00000001U
+#define RTCADC_SAR2_EN_TEST_S  5
+
+/** RTCADC_MEAS2_CTRL2_REG register
+ *  ADC2 configuration registers.
+ */
+#define RTCADC_MEAS2_CTRL2_REG (DR_REG_RTCADC_BASE + 0x30)
+/** RTCADC_MEAS2_DATA_SAR : RO; bitpos: [15:0]; default: 0;
+ *  SAR ADC2 data.
+ */
+#define RTCADC_MEAS2_DATA_SAR    0x0000FFFFU
+#define RTCADC_MEAS2_DATA_SAR_M  (RTCADC_MEAS2_DATA_SAR_V << RTCADC_MEAS2_DATA_SAR_S)
+#define RTCADC_MEAS2_DATA_SAR_V  0x0000FFFFU
+#define RTCADC_MEAS2_DATA_SAR_S  0
+/** RTCADC_MEAS2_DONE_SAR : RO; bitpos: [16]; default: 0;
+ *  SAR ADC2 conversion done indication.
+ */
+#define RTCADC_MEAS2_DONE_SAR    (BIT(16))
+#define RTCADC_MEAS2_DONE_SAR_M  (RTCADC_MEAS2_DONE_SAR_V << RTCADC_MEAS2_DONE_SAR_S)
+#define RTCADC_MEAS2_DONE_SAR_V  0x00000001U
+#define RTCADC_MEAS2_DONE_SAR_S  16
+/** RTCADC_MEAS2_START_SAR : R/W; bitpos: [17]; default: 0;
+ *  SAR ADC2 controller (in RTC) starts conversion.
+ */
+#define RTCADC_MEAS2_START_SAR    (BIT(17))
+#define RTCADC_MEAS2_START_SAR_M  (RTCADC_MEAS2_START_SAR_V << RTCADC_MEAS2_START_SAR_S)
+#define RTCADC_MEAS2_START_SAR_V  0x00000001U
+#define RTCADC_MEAS2_START_SAR_S  17
+/** RTCADC_MEAS2_START_FORCE : R/W; bitpos: [18]; default: 0;
+ *  1: SAR ADC2 controller (in RTC) is started by SW.
+ */
+#define RTCADC_MEAS2_START_FORCE    (BIT(18))
+#define RTCADC_MEAS2_START_FORCE_M  (RTCADC_MEAS2_START_FORCE_V << RTCADC_MEAS2_START_FORCE_S)
+#define RTCADC_MEAS2_START_FORCE_V  0x00000001U
+#define RTCADC_MEAS2_START_FORCE_S  18
+/** RTCADC_SAR2_EN_PAD : R/W; bitpos: [30:19]; default: 0;
+ *  SAR ADC2 pad enable bitmap.
+ */
+#define RTCADC_SAR2_EN_PAD    0x00000FFFU
+#define RTCADC_SAR2_EN_PAD_M  (RTCADC_SAR2_EN_PAD_V << RTCADC_SAR2_EN_PAD_S)
+#define RTCADC_SAR2_EN_PAD_V  0x00000FFFU
+#define RTCADC_SAR2_EN_PAD_S  19
+/** RTCADC_SAR2_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0;
+ *  1: SAR ADC2 pad enable bitmap is controlled by SW.
+ */
+#define RTCADC_SAR2_EN_PAD_FORCE    (BIT(31))
+#define RTCADC_SAR2_EN_PAD_FORCE_M  (RTCADC_SAR2_EN_PAD_FORCE_V << RTCADC_SAR2_EN_PAD_FORCE_S)
+#define RTCADC_SAR2_EN_PAD_FORCE_V  0x00000001U
+#define RTCADC_SAR2_EN_PAD_FORCE_S  31
+
+/** RTCADC_MEAS2_MUX_REG register
+ *  SAR ADC2 MUX register.
+ */
+#define RTCADC_MEAS2_MUX_REG (DR_REG_RTCADC_BASE + 0x34)
+/** RTCADC_SAR2_PWDET_CCT : R/W; bitpos: [30:28]; default: 0;
+ *  SAR2_PWDET_CCT.
+ */
+#define RTCADC_SAR2_PWDET_CCT    0x00000007U
+#define RTCADC_SAR2_PWDET_CCT_M  (RTCADC_SAR2_PWDET_CCT_V << RTCADC_SAR2_PWDET_CCT_S)
+#define RTCADC_SAR2_PWDET_CCT_V  0x00000007U
+#define RTCADC_SAR2_PWDET_CCT_S  28
+/** RTCADC_SAR2_RTC_FORCE : R/W; bitpos: [31]; default: 0;
+ *  In sleep, force to use rtc to control ADC.
+ */
+#define RTCADC_SAR2_RTC_FORCE    (BIT(31))
+#define RTCADC_SAR2_RTC_FORCE_M  (RTCADC_SAR2_RTC_FORCE_V << RTCADC_SAR2_RTC_FORCE_S)
+#define RTCADC_SAR2_RTC_FORCE_V  0x00000001U
+#define RTCADC_SAR2_RTC_FORCE_S  31
+
+/** RTCADC_ATTEN2_REG register
+ *  ADC1 attenuation registers.
+ */
+#define RTCADC_ATTEN2_REG (DR_REG_RTCADC_BASE + 0x38)
+/** RTCADC_SAR2_ATTEN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  2-bit attenuation for each pad.
+ */
+#define RTCADC_SAR2_ATTEN    0xFFFFFFFFU
+#define RTCADC_SAR2_ATTEN_M  (RTCADC_SAR2_ATTEN_V << RTCADC_SAR2_ATTEN_S)
+#define RTCADC_SAR2_ATTEN_V  0xFFFFFFFFU
+#define RTCADC_SAR2_ATTEN_S  0
+
+/** RTCADC_FORCE_WPD_SAR_REG register
+ *  In sleep, force to use rtc to control ADC
+ */
+#define RTCADC_FORCE_WPD_SAR_REG (DR_REG_RTCADC_BASE + 0x3c)
+/** RTCADC_FORCE_XPD_SAR1 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
+ *  control.
+ */
+#define RTCADC_FORCE_XPD_SAR1    0x00000003U
+#define RTCADC_FORCE_XPD_SAR1_M  (RTCADC_FORCE_XPD_SAR1_V << RTCADC_FORCE_XPD_SAR1_S)
+#define RTCADC_FORCE_XPD_SAR1_V  0x00000003U
+#define RTCADC_FORCE_XPD_SAR1_S  0
+/** RTCADC_FORCE_XPD_SAR2 : R/W; bitpos: [3:2]; default: 0;
+ *  2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
+ *  control.
+ */
+#define RTCADC_FORCE_XPD_SAR2    0x00000003U
+#define RTCADC_FORCE_XPD_SAR2_M  (RTCADC_FORCE_XPD_SAR2_V << RTCADC_FORCE_XPD_SAR2_S)
+#define RTCADC_FORCE_XPD_SAR2_V  0x00000003U
+#define RTCADC_FORCE_XPD_SAR2_S  2
+
+/** RTCADC_COCPU_INT_RAW_REG register
+ *  Interrupt raw registers.
+ */
+#define RTCADC_COCPU_INT_RAW_REG (DR_REG_RTCADC_BASE + 0x48)
+/** RTCADC_COCPU_SARADC1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int raw.
+ */
+#define RTCADC_COCPU_SARADC1_INT_RAW    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_RAW_M  (RTCADC_COCPU_SARADC1_INT_RAW_V << RTCADC_COCPU_SARADC1_INT_RAW_S)
+#define RTCADC_COCPU_SARADC1_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_RAW_S  0
+/** RTCADC_COCPU_SARADC2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int raw.
+ */
+#define RTCADC_COCPU_SARADC2_INT_RAW    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_RAW_M  (RTCADC_COCPU_SARADC2_INT_RAW_V << RTCADC_COCPU_SARADC2_INT_RAW_S)
+#define RTCADC_COCPU_SARADC2_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_RAW_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int raw.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_M  (RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int raw.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_M  (RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int raw.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_M  (RTCADC_COCPU_SARADC1_WAKE_INT_RAW_V << RTCADC_COCPU_SARADC1_WAKE_INT_RAW_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int raw.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_M  (RTCADC_COCPU_SARADC2_WAKE_INT_RAW_V << RTCADC_COCPU_SARADC2_WAKE_INT_RAW_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_S  5
+
+/** RTCADC_INT_ENA_REG register
+ *  Interrupt enable registers.
+ */
+#define RTCADC_INT_ENA_REG (DR_REG_RTCADC_BASE + 0x4c)
+/** RTCADC_COCPU_SARADC1_INT_ENA : R/WTC; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int enable.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ENA    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ENA_M  (RTCADC_COCPU_SARADC1_INT_ENA_V << RTCADC_COCPU_SARADC1_INT_ENA_S)
+#define RTCADC_COCPU_SARADC1_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ENA_S  0
+/** RTCADC_COCPU_SARADC2_INT_ENA : R/WTC; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int enable.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ENA    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ENA_M  (RTCADC_COCPU_SARADC2_INT_ENA_V << RTCADC_COCPU_SARADC2_INT_ENA_S)
+#define RTCADC_COCPU_SARADC2_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ENA_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA : R/WTC; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int enable.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA : R/WTC; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int enable.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA : R/WTC; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int enable.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA : R/WTC; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int enable.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_S  5
+
+/** RTCADC_INT_ST_REG register
+ *  Interrupt status registers.
+ */
+#define RTCADC_INT_ST_REG (DR_REG_RTCADC_BASE + 0x50)
+/** RTCADC_COCPU_SARADC1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int status.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ST    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ST_M  (RTCADC_COCPU_SARADC1_INT_ST_V << RTCADC_COCPU_SARADC1_INT_ST_S)
+#define RTCADC_COCPU_SARADC1_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ST_S  0
+/** RTCADC_COCPU_SARADC2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int status.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ST    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ST_M  (RTCADC_COCPU_SARADC2_INT_ST_V << RTCADC_COCPU_SARADC2_INT_ST_S)
+#define RTCADC_COCPU_SARADC2_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ST_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int status.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ST_V << RTCADC_COCPU_SARADC1_ERROR_INT_ST_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int status.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ST_V << RTCADC_COCPU_SARADC2_ERROR_INT_ST_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int status.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ST_V << RTCADC_COCPU_SARADC1_WAKE_INT_ST_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int status.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ST_V << RTCADC_COCPU_SARADC2_WAKE_INT_ST_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_S  5
+
+/** RTCADC_INT_CLR_REG register
+ *  Interrupt clear registers.
+ */
+#define RTCADC_INT_CLR_REG (DR_REG_RTCADC_BASE + 0x54)
+/** RTCADC_COCPU_SARADC1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int clear.
+ */
+#define RTCADC_COCPU_SARADC1_INT_CLR    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_CLR_M  (RTCADC_COCPU_SARADC1_INT_CLR_V << RTCADC_COCPU_SARADC1_INT_CLR_S)
+#define RTCADC_COCPU_SARADC1_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_CLR_S  0
+/** RTCADC_COCPU_SARADC2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int clear.
+ */
+#define RTCADC_COCPU_SARADC2_INT_CLR    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_CLR_M  (RTCADC_COCPU_SARADC2_INT_CLR_V << RTCADC_COCPU_SARADC2_INT_CLR_S)
+#define RTCADC_COCPU_SARADC2_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_CLR_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int clear.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_M  (RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int clear.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_M  (RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int clear.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_M  (RTCADC_COCPU_SARADC1_WAKE_INT_CLR_V << RTCADC_COCPU_SARADC1_WAKE_INT_CLR_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int clear.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_M  (RTCADC_COCPU_SARADC2_WAKE_INT_CLR_V << RTCADC_COCPU_SARADC2_WAKE_INT_CLR_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_S  5
+
+/** RTCADC_INT_ENA_W1TS_REG register
+ *  Interrupt enable assert registers.
+ */
+#define RTCADC_INT_ENA_W1TS_REG (DR_REG_RTCADC_BASE + 0x58)
+/** RTCADC_COCPU_SARADC1_INT_ENA_W1TS : WT; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC1_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_S  0
+/** RTCADC_COCPU_SARADC2_INT_ENA_W1TS : WT; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS : WT; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS : WT; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS : WT; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS : WT; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_S  5
+
+/** RTCADC_INT_ENA_W1TC_REG register
+ *  Interrupt enable deassert registers.
+ */
+#define RTCADC_INT_ENA_W1TC_REG (DR_REG_RTCADC_BASE + 0x5c)
+/** RTCADC_COCPU_SARADC1_INT_ENA_W1TC : WT; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC1_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_S  0
+/** RTCADC_COCPU_SARADC2_INT_ENA_W1TC : WT; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC : WT; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC : WT; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC : WT; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC : WT; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_S  5
+
+/** RTCADC_WAKEUP1_REG register
+ *  ADC1 wakeup configuration registers.
+ */
+#define RTCADC_WAKEUP1_REG (DR_REG_RTCADC_BASE + 0x60)
+/** RTCADC_SAR1_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0;
+ *  Lower threshold.
+ */
+#define RTCADC_SAR1_WAKEUP_TH_LOW    0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_LOW_M  (RTCADC_SAR1_WAKEUP_TH_LOW_V << RTCADC_SAR1_WAKEUP_TH_LOW_S)
+#define RTCADC_SAR1_WAKEUP_TH_LOW_V  0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_LOW_S  0
+/** RTCADC_SAR1_WAKEUP_TH_HIGH : R/W; bitpos: [25:14]; default: 4095;
+ *  Upper threshold.
+ */
+#define RTCADC_SAR1_WAKEUP_TH_HIGH    0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_HIGH_M  (RTCADC_SAR1_WAKEUP_TH_HIGH_V << RTCADC_SAR1_WAKEUP_TH_HIGH_S)
+#define RTCADC_SAR1_WAKEUP_TH_HIGH_V  0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_HIGH_S  14
+/** RTCADC_SAR1_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
+ *  Indicates that this wakeup event arose from exceeding upper threshold.
+ */
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH    (BIT(29))
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_M  (RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_V << RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_S)
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_V  0x00000001U
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_S  29
+/** RTCADC_SAR1_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
+ *  Wakeup function enable.
+ */
+#define RTCADC_SAR1_WAKEUP_EN    (BIT(30))
+#define RTCADC_SAR1_WAKEUP_EN_M  (RTCADC_SAR1_WAKEUP_EN_V << RTCADC_SAR1_WAKEUP_EN_S)
+#define RTCADC_SAR1_WAKEUP_EN_V  0x00000001U
+#define RTCADC_SAR1_WAKEUP_EN_S  30
+/** RTCADC_SAR1_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
+ *  0:absolute value comparison mode. 1: relative value comparison mode.
+ */
+#define RTCADC_SAR1_WAKEUP_MODE    (BIT(31))
+#define RTCADC_SAR1_WAKEUP_MODE_M  (RTCADC_SAR1_WAKEUP_MODE_V << RTCADC_SAR1_WAKEUP_MODE_S)
+#define RTCADC_SAR1_WAKEUP_MODE_V  0x00000001U
+#define RTCADC_SAR1_WAKEUP_MODE_S  31
+
+/** RTCADC_WAKEUP2_REG register
+ *  ADC2 wakeup configuration registers.
+ */
+#define RTCADC_WAKEUP2_REG (DR_REG_RTCADC_BASE + 0x64)
+/** RTCADC_SAR2_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0;
+ *  Lower threshold.
+ */
+#define RTCADC_SAR2_WAKEUP_TH_LOW    0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_LOW_M  (RTCADC_SAR2_WAKEUP_TH_LOW_V << RTCADC_SAR2_WAKEUP_TH_LOW_S)
+#define RTCADC_SAR2_WAKEUP_TH_LOW_V  0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_LOW_S  0
+/** RTCADC_SAR2_WAKEUP_TH_HIGH : R/W; bitpos: [25:14]; default: 4095;
+ *  Upper threshold.
+ */
+#define RTCADC_SAR2_WAKEUP_TH_HIGH    0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_HIGH_M  (RTCADC_SAR2_WAKEUP_TH_HIGH_V << RTCADC_SAR2_WAKEUP_TH_HIGH_S)
+#define RTCADC_SAR2_WAKEUP_TH_HIGH_V  0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_HIGH_S  14
+/** RTCADC_SAR2_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
+ *  Indicates that this wakeup event arose from exceeding upper threshold.
+ */
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH    (BIT(29))
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_M  (RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_V << RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_S)
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_V  0x00000001U
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_S  29
+/** RTCADC_SAR2_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
+ *  Wakeup function enable.
+ */
+#define RTCADC_SAR2_WAKEUP_EN    (BIT(30))
+#define RTCADC_SAR2_WAKEUP_EN_M  (RTCADC_SAR2_WAKEUP_EN_V << RTCADC_SAR2_WAKEUP_EN_S)
+#define RTCADC_SAR2_WAKEUP_EN_V  0x00000001U
+#define RTCADC_SAR2_WAKEUP_EN_S  30
+/** RTCADC_SAR2_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
+ *  0:absolute value comparison mode. 1: relative value comparison mode.
+ */
+#define RTCADC_SAR2_WAKEUP_MODE    (BIT(31))
+#define RTCADC_SAR2_WAKEUP_MODE_M  (RTCADC_SAR2_WAKEUP_MODE_V << RTCADC_SAR2_WAKEUP_MODE_S)
+#define RTCADC_SAR2_WAKEUP_MODE_V  0x00000001U
+#define RTCADC_SAR2_WAKEUP_MODE_S  31
+
+/** RTCADC_WAKEUP_SEL_REG register
+ *  Wakeup source select register.
+ */
+#define RTCADC_WAKEUP_SEL_REG (DR_REG_RTCADC_BASE + 0x68)
+/** RTCADC_SAR_WAKEUP_SEL : R/W; bitpos: [0]; default: 0;
+ *  0: ADC1. 1: ADC2.
+ */
+#define RTCADC_SAR_WAKEUP_SEL    (BIT(0))
+#define RTCADC_SAR_WAKEUP_SEL_M  (RTCADC_SAR_WAKEUP_SEL_V << RTCADC_SAR_WAKEUP_SEL_S)
+#define RTCADC_SAR_WAKEUP_SEL_V  0x00000001U
+#define RTCADC_SAR_WAKEUP_SEL_S  0
+
+/** RTCADC_SAR1_HW_WAKEUP_REG register
+ *  Hardware automatic sampling registers for wakeup function.
+ */
+#define RTCADC_SAR1_HW_WAKEUP_REG (DR_REG_RTCADC_BASE + 0x6c)
+/** RTCADC_ADC1_HW_READ_EN_I : R/W; bitpos: [0]; default: 0;
+ *  Enable hardware automatic sampling.
+ */
+#define RTCADC_ADC1_HW_READ_EN_I    (BIT(0))
+#define RTCADC_ADC1_HW_READ_EN_I_M  (RTCADC_ADC1_HW_READ_EN_I_V << RTCADC_ADC1_HW_READ_EN_I_S)
+#define RTCADC_ADC1_HW_READ_EN_I_V  0x00000001U
+#define RTCADC_ADC1_HW_READ_EN_I_S  0
+/** RTCADC_ADC1_HW_READ_RATE_I : R/W; bitpos: [16:1]; default: 100;
+ *  Hardware automatic sampling rate.
+ */
+#define RTCADC_ADC1_HW_READ_RATE_I    0x0000FFFFU
+#define RTCADC_ADC1_HW_READ_RATE_I_M  (RTCADC_ADC1_HW_READ_RATE_I_V << RTCADC_ADC1_HW_READ_RATE_I_S)
+#define RTCADC_ADC1_HW_READ_RATE_I_V  0x0000FFFFU
+#define RTCADC_ADC1_HW_READ_RATE_I_S  1
+
+/** RTCADC_SAR2_HW_WAKEUP_REG register
+ *  Hardware automatic sampling registers for wakeup function.
+ */
+#define RTCADC_SAR2_HW_WAKEUP_REG (DR_REG_RTCADC_BASE + 0x70)
+/** RTCADC_ADC2_HW_READ_EN_I : R/W; bitpos: [0]; default: 0;
+ *  Enable hardware automatic sampling.
+ */
+#define RTCADC_ADC2_HW_READ_EN_I    (BIT(0))
+#define RTCADC_ADC2_HW_READ_EN_I_M  (RTCADC_ADC2_HW_READ_EN_I_V << RTCADC_ADC2_HW_READ_EN_I_S)
+#define RTCADC_ADC2_HW_READ_EN_I_V  0x00000001U
+#define RTCADC_ADC2_HW_READ_EN_I_S  0
+/** RTCADC_ADC2_HW_READ_RATE_I : R/W; bitpos: [16:1]; default: 100;
+ *  Hardware automatic sampling rate.
+ */
+#define RTCADC_ADC2_HW_READ_RATE_I    0x0000FFFFU
+#define RTCADC_ADC2_HW_READ_RATE_I_M  (RTCADC_ADC2_HW_READ_RATE_I_V << RTCADC_ADC2_HW_READ_RATE_I_S)
+#define RTCADC_ADC2_HW_READ_RATE_I_V  0x0000FFFFU
+#define RTCADC_ADC2_HW_READ_RATE_I_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_adc_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_adc_reg.h
new file mode 100644
index 0000000000..aba191049e
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_adc_reg.h
@@ -0,0 +1,704 @@
+/**
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RTCADC_READER1_CTRL_REG register
+ *  Control the read operation of ADC1.
+ */
+#define RTCADC_READER1_CTRL_REG (DR_REG_LP_ADC_BASE + 0x0)
+/** RTCADC_SAR1_CLK_DIV : R/W; bitpos: [7:0]; default: 2;
+ *  Clock divider.
+ */
+#define RTCADC_SAR1_CLK_DIV    0x000000FFU
+#define RTCADC_SAR1_CLK_DIV_M  (RTCADC_SAR1_CLK_DIV_V << RTCADC_SAR1_CLK_DIV_S)
+#define RTCADC_SAR1_CLK_DIV_V  0x000000FFU
+#define RTCADC_SAR1_CLK_DIV_S  0
+/** RTCADC_SAR1_DATA_INV : R/W; bitpos: [28]; default: 0;
+ *  Invert SAR ADC1 data.
+ */
+#define RTCADC_SAR1_DATA_INV    (BIT(28))
+#define RTCADC_SAR1_DATA_INV_M  (RTCADC_SAR1_DATA_INV_V << RTCADC_SAR1_DATA_INV_S)
+#define RTCADC_SAR1_DATA_INV_V  0x00000001U
+#define RTCADC_SAR1_DATA_INV_S  28
+/** RTCADC_SAR1_INT_EN : R/W; bitpos: [29]; default: 1;
+ *  Enable saradc1 to send out interrupt.
+ */
+#define RTCADC_SAR1_INT_EN    (BIT(29))
+#define RTCADC_SAR1_INT_EN_M  (RTCADC_SAR1_INT_EN_V << RTCADC_SAR1_INT_EN_S)
+#define RTCADC_SAR1_INT_EN_V  0x00000001U
+#define RTCADC_SAR1_INT_EN_S  29
+/** RTCADC_SAR1_EN_PAD_FORCE_ENABLE : R/W; bitpos: [31:30]; default: 0;
+ *  Force enable adc en_pad to analog circuit 2'b11: force enable .
+ */
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE    0x00000003U
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_M  (RTCADC_SAR1_EN_PAD_FORCE_ENABLE_V << RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S)
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_V  0x00000003U
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S  30
+
+/** RTCADC_MEAS1_CTRL2_REG register
+ *  ADC1 configuration registers.
+ */
+#define RTCADC_MEAS1_CTRL2_REG (DR_REG_LP_ADC_BASE + 0xc)
+/** RTCADC_MEAS1_DATA_SAR : RO; bitpos: [15:0]; default: 0;
+ *  SAR ADC1 data.
+ */
+#define RTCADC_MEAS1_DATA_SAR    0x0000FFFFU
+#define RTCADC_MEAS1_DATA_SAR_M  (RTCADC_MEAS1_DATA_SAR_V << RTCADC_MEAS1_DATA_SAR_S)
+#define RTCADC_MEAS1_DATA_SAR_V  0x0000FFFFU
+#define RTCADC_MEAS1_DATA_SAR_S  0
+/** RTCADC_MEAS1_DONE_SAR : RO; bitpos: [16]; default: 0;
+ *  SAR ADC1 conversion done indication.
+ */
+#define RTCADC_MEAS1_DONE_SAR    (BIT(16))
+#define RTCADC_MEAS1_DONE_SAR_M  (RTCADC_MEAS1_DONE_SAR_V << RTCADC_MEAS1_DONE_SAR_S)
+#define RTCADC_MEAS1_DONE_SAR_V  0x00000001U
+#define RTCADC_MEAS1_DONE_SAR_S  16
+/** RTCADC_MEAS1_START_SAR : R/W; bitpos: [17]; default: 0;
+ *  SAR ADC1 controller (in RTC) starts conversion.
+ */
+#define RTCADC_MEAS1_START_SAR    (BIT(17))
+#define RTCADC_MEAS1_START_SAR_M  (RTCADC_MEAS1_START_SAR_V << RTCADC_MEAS1_START_SAR_S)
+#define RTCADC_MEAS1_START_SAR_V  0x00000001U
+#define RTCADC_MEAS1_START_SAR_S  17
+/** RTCADC_MEAS1_START_FORCE : R/W; bitpos: [18]; default: 0;
+ *  1: SAR ADC1 controller (in RTC) is started by SW.
+ */
+#define RTCADC_MEAS1_START_FORCE    (BIT(18))
+#define RTCADC_MEAS1_START_FORCE_M  (RTCADC_MEAS1_START_FORCE_V << RTCADC_MEAS1_START_FORCE_S)
+#define RTCADC_MEAS1_START_FORCE_V  0x00000001U
+#define RTCADC_MEAS1_START_FORCE_S  18
+/** RTCADC_SAR1_EN_PAD : R/W; bitpos: [30:19]; default: 0;
+ *  SAR ADC1 pad enable bitmap.
+ */
+#define RTCADC_SAR1_EN_PAD    0x00000FFFU
+#define RTCADC_SAR1_EN_PAD_M  (RTCADC_SAR1_EN_PAD_V << RTCADC_SAR1_EN_PAD_S)
+#define RTCADC_SAR1_EN_PAD_V  0x00000FFFU
+#define RTCADC_SAR1_EN_PAD_S  19
+/** RTCADC_SAR1_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0;
+ *  1: SAR ADC1 pad enable bitmap is controlled by SW.
+ */
+#define RTCADC_SAR1_EN_PAD_FORCE    (BIT(31))
+#define RTCADC_SAR1_EN_PAD_FORCE_M  (RTCADC_SAR1_EN_PAD_FORCE_V << RTCADC_SAR1_EN_PAD_FORCE_S)
+#define RTCADC_SAR1_EN_PAD_FORCE_V  0x00000001U
+#define RTCADC_SAR1_EN_PAD_FORCE_S  31
+
+/** RTCADC_MEAS1_MUX_REG register
+ *  SAR ADC1 MUX register.
+ */
+#define RTCADC_MEAS1_MUX_REG (DR_REG_LP_ADC_BASE + 0x10)
+/** RTCADC_SAR1_DIG_FORCE : R/W; bitpos: [31]; default: 0;
+ *  1: SAR ADC1 controlled by DIG ADC1 CTRL.
+ */
+#define RTCADC_SAR1_DIG_FORCE    (BIT(31))
+#define RTCADC_SAR1_DIG_FORCE_M  (RTCADC_SAR1_DIG_FORCE_V << RTCADC_SAR1_DIG_FORCE_S)
+#define RTCADC_SAR1_DIG_FORCE_V  0x00000001U
+#define RTCADC_SAR1_DIG_FORCE_S  31
+
+/** RTCADC_ATTEN1_REG register
+ *  ADC1 attenuation registers.
+ */
+#define RTCADC_ATTEN1_REG (DR_REG_LP_ADC_BASE + 0x14)
+/** RTCADC_SAR1_ATTEN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  2-bit attenuation for each pad.
+ */
+#define RTCADC_SAR1_ATTEN    0xFFFFFFFFU
+#define RTCADC_SAR1_ATTEN_M  (RTCADC_SAR1_ATTEN_V << RTCADC_SAR1_ATTEN_S)
+#define RTCADC_SAR1_ATTEN_V  0xFFFFFFFFU
+#define RTCADC_SAR1_ATTEN_S  0
+
+/** RTCADC_READER2_CTRL_REG register
+ *  Control the read operation of ADC2.
+ */
+#define RTCADC_READER2_CTRL_REG (DR_REG_LP_ADC_BASE + 0x24)
+/** RTCADC_SAR2_CLK_DIV : R/W; bitpos: [7:0]; default: 2;
+ *  Clock divider.
+ */
+#define RTCADC_SAR2_CLK_DIV    0x000000FFU
+#define RTCADC_SAR2_CLK_DIV_M  (RTCADC_SAR2_CLK_DIV_V << RTCADC_SAR2_CLK_DIV_S)
+#define RTCADC_SAR2_CLK_DIV_V  0x000000FFU
+#define RTCADC_SAR2_CLK_DIV_S  0
+/** RTCADC_SAR2_WAIT_ARB_CYCLE : R/W; bitpos: [17:16]; default: 1;
+ *  Wait arbit stable after sar_done.
+ */
+#define RTCADC_SAR2_WAIT_ARB_CYCLE    0x00000003U
+#define RTCADC_SAR2_WAIT_ARB_CYCLE_M  (RTCADC_SAR2_WAIT_ARB_CYCLE_V << RTCADC_SAR2_WAIT_ARB_CYCLE_S)
+#define RTCADC_SAR2_WAIT_ARB_CYCLE_V  0x00000003U
+#define RTCADC_SAR2_WAIT_ARB_CYCLE_S  16
+/** RTCADC_SAR2_EN_PAD_FORCE_ENABLE : R/W; bitpos: [28:27]; default: 0;
+ *  Force enable adc en_pad to analog circuit 2'b11: force enable .
+ */
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE    0x00000003U
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_M  (RTCADC_SAR2_EN_PAD_FORCE_ENABLE_V << RTCADC_SAR2_EN_PAD_FORCE_ENABLE_S)
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_V  0x00000003U
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_S  27
+/** RTCADC_SAR2_DATA_INV : R/W; bitpos: [29]; default: 0;
+ *  Invert SAR ADC2 data.
+ */
+#define RTCADC_SAR2_DATA_INV    (BIT(29))
+#define RTCADC_SAR2_DATA_INV_M  (RTCADC_SAR2_DATA_INV_V << RTCADC_SAR2_DATA_INV_S)
+#define RTCADC_SAR2_DATA_INV_V  0x00000001U
+#define RTCADC_SAR2_DATA_INV_S  29
+/** RTCADC_SAR2_INT_EN : R/W; bitpos: [30]; default: 1;
+ *  Enable saradc2 to send out interrupt.
+ */
+#define RTCADC_SAR2_INT_EN    (BIT(30))
+#define RTCADC_SAR2_INT_EN_M  (RTCADC_SAR2_INT_EN_V << RTCADC_SAR2_INT_EN_S)
+#define RTCADC_SAR2_INT_EN_V  0x00000001U
+#define RTCADC_SAR2_INT_EN_S  30
+
+/** RTCADC_MEAS2_CTRL1_REG register
+ *  ADC2 configuration registers.
+ */
+#define RTCADC_MEAS2_CTRL1_REG (DR_REG_LP_ADC_BASE + 0x2c)
+/** RTCADC_SAR2_CNTL_STATE : RO; bitpos: [2:0]; default: 0;
+ *  saradc2_cntl_fsm.
+ */
+#define RTCADC_SAR2_CNTL_STATE    0x00000007U
+#define RTCADC_SAR2_CNTL_STATE_M  (RTCADC_SAR2_CNTL_STATE_V << RTCADC_SAR2_CNTL_STATE_S)
+#define RTCADC_SAR2_CNTL_STATE_V  0x00000007U
+#define RTCADC_SAR2_CNTL_STATE_S  0
+/** RTCADC_SAR2_PWDET_CAL_EN : R/W; bitpos: [3]; default: 0;
+ *  RTC control pwdet enable.
+ */
+#define RTCADC_SAR2_PWDET_CAL_EN    (BIT(3))
+#define RTCADC_SAR2_PWDET_CAL_EN_M  (RTCADC_SAR2_PWDET_CAL_EN_V << RTCADC_SAR2_PWDET_CAL_EN_S)
+#define RTCADC_SAR2_PWDET_CAL_EN_V  0x00000001U
+#define RTCADC_SAR2_PWDET_CAL_EN_S  3
+/** RTCADC_SAR2_PKDET_CAL_EN : R/W; bitpos: [4]; default: 0;
+ *  RTC control pkdet enable.
+ */
+#define RTCADC_SAR2_PKDET_CAL_EN    (BIT(4))
+#define RTCADC_SAR2_PKDET_CAL_EN_M  (RTCADC_SAR2_PKDET_CAL_EN_V << RTCADC_SAR2_PKDET_CAL_EN_S)
+#define RTCADC_SAR2_PKDET_CAL_EN_V  0x00000001U
+#define RTCADC_SAR2_PKDET_CAL_EN_S  4
+/** RTCADC_SAR2_EN_TEST : R/W; bitpos: [5]; default: 0;
+ *  SAR2_EN_TEST.
+ */
+#define RTCADC_SAR2_EN_TEST    (BIT(5))
+#define RTCADC_SAR2_EN_TEST_M  (RTCADC_SAR2_EN_TEST_V << RTCADC_SAR2_EN_TEST_S)
+#define RTCADC_SAR2_EN_TEST_V  0x00000001U
+#define RTCADC_SAR2_EN_TEST_S  5
+
+/** RTCADC_MEAS2_CTRL2_REG register
+ *  ADC2 configuration registers.
+ */
+#define RTCADC_MEAS2_CTRL2_REG (DR_REG_LP_ADC_BASE + 0x30)
+/** RTCADC_MEAS2_DATA_SAR : RO; bitpos: [15:0]; default: 0;
+ *  SAR ADC2 data.
+ */
+#define RTCADC_MEAS2_DATA_SAR    0x0000FFFFU
+#define RTCADC_MEAS2_DATA_SAR_M  (RTCADC_MEAS2_DATA_SAR_V << RTCADC_MEAS2_DATA_SAR_S)
+#define RTCADC_MEAS2_DATA_SAR_V  0x0000FFFFU
+#define RTCADC_MEAS2_DATA_SAR_S  0
+/** RTCADC_MEAS2_DONE_SAR : RO; bitpos: [16]; default: 0;
+ *  SAR ADC2 conversion done indication.
+ */
+#define RTCADC_MEAS2_DONE_SAR    (BIT(16))
+#define RTCADC_MEAS2_DONE_SAR_M  (RTCADC_MEAS2_DONE_SAR_V << RTCADC_MEAS2_DONE_SAR_S)
+#define RTCADC_MEAS2_DONE_SAR_V  0x00000001U
+#define RTCADC_MEAS2_DONE_SAR_S  16
+/** RTCADC_MEAS2_START_SAR : R/W; bitpos: [17]; default: 0;
+ *  SAR ADC2 controller (in RTC) starts conversion.
+ */
+#define RTCADC_MEAS2_START_SAR    (BIT(17))
+#define RTCADC_MEAS2_START_SAR_M  (RTCADC_MEAS2_START_SAR_V << RTCADC_MEAS2_START_SAR_S)
+#define RTCADC_MEAS2_START_SAR_V  0x00000001U
+#define RTCADC_MEAS2_START_SAR_S  17
+/** RTCADC_MEAS2_START_FORCE : R/W; bitpos: [18]; default: 0;
+ *  1: SAR ADC2 controller (in RTC) is started by SW.
+ */
+#define RTCADC_MEAS2_START_FORCE    (BIT(18))
+#define RTCADC_MEAS2_START_FORCE_M  (RTCADC_MEAS2_START_FORCE_V << RTCADC_MEAS2_START_FORCE_S)
+#define RTCADC_MEAS2_START_FORCE_V  0x00000001U
+#define RTCADC_MEAS2_START_FORCE_S  18
+/** RTCADC_SAR2_EN_PAD : R/W; bitpos: [30:19]; default: 0;
+ *  SAR ADC2 pad enable bitmap.
+ */
+#define RTCADC_SAR2_EN_PAD    0x00000FFFU
+#define RTCADC_SAR2_EN_PAD_M  (RTCADC_SAR2_EN_PAD_V << RTCADC_SAR2_EN_PAD_S)
+#define RTCADC_SAR2_EN_PAD_V  0x00000FFFU
+#define RTCADC_SAR2_EN_PAD_S  19
+/** RTCADC_SAR2_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0;
+ *  1: SAR ADC2 pad enable bitmap is controlled by SW.
+ */
+#define RTCADC_SAR2_EN_PAD_FORCE    (BIT(31))
+#define RTCADC_SAR2_EN_PAD_FORCE_M  (RTCADC_SAR2_EN_PAD_FORCE_V << RTCADC_SAR2_EN_PAD_FORCE_S)
+#define RTCADC_SAR2_EN_PAD_FORCE_V  0x00000001U
+#define RTCADC_SAR2_EN_PAD_FORCE_S  31
+
+/** RTCADC_MEAS2_MUX_REG register
+ *  SAR ADC2 MUX register.
+ */
+#define RTCADC_MEAS2_MUX_REG (DR_REG_LP_ADC_BASE + 0x34)
+/** RTCADC_SAR2_PWDET_CCT : R/W; bitpos: [30:28]; default: 0;
+ *  SAR2_PWDET_CCT.
+ */
+#define RTCADC_SAR2_PWDET_CCT    0x00000007U
+#define RTCADC_SAR2_PWDET_CCT_M  (RTCADC_SAR2_PWDET_CCT_V << RTCADC_SAR2_PWDET_CCT_S)
+#define RTCADC_SAR2_PWDET_CCT_V  0x00000007U
+#define RTCADC_SAR2_PWDET_CCT_S  28
+/** RTCADC_SAR2_RTC_FORCE : R/W; bitpos: [31]; default: 0;
+ *  In sleep, force to use rtc to control ADC.
+ */
+#define RTCADC_SAR2_RTC_FORCE    (BIT(31))
+#define RTCADC_SAR2_RTC_FORCE_M  (RTCADC_SAR2_RTC_FORCE_V << RTCADC_SAR2_RTC_FORCE_S)
+#define RTCADC_SAR2_RTC_FORCE_V  0x00000001U
+#define RTCADC_SAR2_RTC_FORCE_S  31
+
+/** RTCADC_ATTEN2_REG register
+ *  ADC1 attenuation registers.
+ */
+#define RTCADC_ATTEN2_REG (DR_REG_LP_ADC_BASE + 0x38)
+/** RTCADC_SAR2_ATTEN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  2-bit attenuation for each pad.
+ */
+#define RTCADC_SAR2_ATTEN    0xFFFFFFFFU
+#define RTCADC_SAR2_ATTEN_M  (RTCADC_SAR2_ATTEN_V << RTCADC_SAR2_ATTEN_S)
+#define RTCADC_SAR2_ATTEN_V  0xFFFFFFFFU
+#define RTCADC_SAR2_ATTEN_S  0
+
+/** RTCADC_FORCE_WPD_SAR_REG register
+ *  In sleep, force to use rtc to control ADC
+ */
+#define RTCADC_FORCE_WPD_SAR_REG (DR_REG_LP_ADC_BASE + 0x3c)
+/** RTCADC_FORCE_XPD_SAR1 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
+ *  control.
+ */
+#define RTCADC_FORCE_XPD_SAR1    0x00000003U
+#define RTCADC_FORCE_XPD_SAR1_M  (RTCADC_FORCE_XPD_SAR1_V << RTCADC_FORCE_XPD_SAR1_S)
+#define RTCADC_FORCE_XPD_SAR1_V  0x00000003U
+#define RTCADC_FORCE_XPD_SAR1_S  0
+/** RTCADC_FORCE_XPD_SAR2 : R/W; bitpos: [3:2]; default: 0;
+ *  2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
+ *  control.
+ */
+#define RTCADC_FORCE_XPD_SAR2    0x00000003U
+#define RTCADC_FORCE_XPD_SAR2_M  (RTCADC_FORCE_XPD_SAR2_V << RTCADC_FORCE_XPD_SAR2_S)
+#define RTCADC_FORCE_XPD_SAR2_V  0x00000003U
+#define RTCADC_FORCE_XPD_SAR2_S  2
+
+/** RTCADC_COCPU_INT_RAW_REG register
+ *  Interrupt raw registers.
+ */
+#define RTCADC_COCPU_INT_RAW_REG (DR_REG_LP_ADC_BASE + 0x48)
+/** RTCADC_COCPU_SARADC1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int raw.
+ */
+#define RTCADC_COCPU_SARADC1_INT_RAW    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_RAW_M  (RTCADC_COCPU_SARADC1_INT_RAW_V << RTCADC_COCPU_SARADC1_INT_RAW_S)
+#define RTCADC_COCPU_SARADC1_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_RAW_S  0
+/** RTCADC_COCPU_SARADC2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int raw.
+ */
+#define RTCADC_COCPU_SARADC2_INT_RAW    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_RAW_M  (RTCADC_COCPU_SARADC2_INT_RAW_V << RTCADC_COCPU_SARADC2_INT_RAW_S)
+#define RTCADC_COCPU_SARADC2_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_RAW_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int raw.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_M  (RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int raw.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_M  (RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int raw.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_M  (RTCADC_COCPU_SARADC1_WAKE_INT_RAW_V << RTCADC_COCPU_SARADC1_WAKE_INT_RAW_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int raw.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_M  (RTCADC_COCPU_SARADC2_WAKE_INT_RAW_V << RTCADC_COCPU_SARADC2_WAKE_INT_RAW_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_S  5
+
+/** RTCADC_INT_ENA_REG register
+ *  Interrupt enable registers.
+ */
+#define RTCADC_INT_ENA_REG (DR_REG_LP_ADC_BASE + 0x4c)
+/** RTCADC_COCPU_SARADC1_INT_ENA : R/WTC; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int enable.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ENA    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ENA_M  (RTCADC_COCPU_SARADC1_INT_ENA_V << RTCADC_COCPU_SARADC1_INT_ENA_S)
+#define RTCADC_COCPU_SARADC1_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ENA_S  0
+/** RTCADC_COCPU_SARADC2_INT_ENA : R/WTC; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int enable.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ENA    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ENA_M  (RTCADC_COCPU_SARADC2_INT_ENA_V << RTCADC_COCPU_SARADC2_INT_ENA_S)
+#define RTCADC_COCPU_SARADC2_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ENA_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA : R/WTC; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int enable.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA : R/WTC; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int enable.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA : R/WTC; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int enable.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA : R/WTC; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int enable.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_S  5
+
+/** RTCADC_INT_ST_REG register
+ *  Interrupt status registers.
+ */
+#define RTCADC_INT_ST_REG (DR_REG_LP_ADC_BASE + 0x50)
+/** RTCADC_COCPU_SARADC1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int status.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ST    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ST_M  (RTCADC_COCPU_SARADC1_INT_ST_V << RTCADC_COCPU_SARADC1_INT_ST_S)
+#define RTCADC_COCPU_SARADC1_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ST_S  0
+/** RTCADC_COCPU_SARADC2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int status.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ST    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ST_M  (RTCADC_COCPU_SARADC2_INT_ST_V << RTCADC_COCPU_SARADC2_INT_ST_S)
+#define RTCADC_COCPU_SARADC2_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ST_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int status.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ST_V << RTCADC_COCPU_SARADC1_ERROR_INT_ST_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int status.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ST_V << RTCADC_COCPU_SARADC2_ERROR_INT_ST_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int status.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ST_V << RTCADC_COCPU_SARADC1_WAKE_INT_ST_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int status.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ST_V << RTCADC_COCPU_SARADC2_WAKE_INT_ST_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_S  5
+
+/** RTCADC_INT_CLR_REG register
+ *  Interrupt clear registers.
+ */
+#define RTCADC_INT_CLR_REG (DR_REG_LP_ADC_BASE + 0x54)
+/** RTCADC_COCPU_SARADC1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int clear.
+ */
+#define RTCADC_COCPU_SARADC1_INT_CLR    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_CLR_M  (RTCADC_COCPU_SARADC1_INT_CLR_V << RTCADC_COCPU_SARADC1_INT_CLR_S)
+#define RTCADC_COCPU_SARADC1_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_CLR_S  0
+/** RTCADC_COCPU_SARADC2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int clear.
+ */
+#define RTCADC_COCPU_SARADC2_INT_CLR    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_CLR_M  (RTCADC_COCPU_SARADC2_INT_CLR_V << RTCADC_COCPU_SARADC2_INT_CLR_S)
+#define RTCADC_COCPU_SARADC2_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_CLR_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int clear.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_M  (RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int clear.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_M  (RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int clear.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_M  (RTCADC_COCPU_SARADC1_WAKE_INT_CLR_V << RTCADC_COCPU_SARADC1_WAKE_INT_CLR_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int clear.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_M  (RTCADC_COCPU_SARADC2_WAKE_INT_CLR_V << RTCADC_COCPU_SARADC2_WAKE_INT_CLR_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_S  5
+
+/** RTCADC_INT_ENA_W1TS_REG register
+ *  Interrupt enable assert registers.
+ */
+#define RTCADC_INT_ENA_W1TS_REG (DR_REG_LP_ADC_BASE + 0x58)
+/** RTCADC_COCPU_SARADC1_INT_ENA_W1TS : WT; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC1_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_S  0
+/** RTCADC_COCPU_SARADC2_INT_ENA_W1TS : WT; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS : WT; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS : WT; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS : WT; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS : WT; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_S  5
+
+/** RTCADC_INT_ENA_W1TC_REG register
+ *  Interrupt enable deassert registers.
+ */
+#define RTCADC_INT_ENA_W1TC_REG (DR_REG_LP_ADC_BASE + 0x5c)
+/** RTCADC_COCPU_SARADC1_INT_ENA_W1TC : WT; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC1_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_S  0
+/** RTCADC_COCPU_SARADC2_INT_ENA_W1TC : WT; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC : WT; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC : WT; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC : WT; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC : WT; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_S  5
+
+/** RTCADC_WAKEUP1_REG register
+ *  ADC1 wakeup configuration registers.
+ */
+#define RTCADC_WAKEUP1_REG (DR_REG_LP_ADC_BASE + 0x60)
+/** RTCADC_SAR1_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0;
+ *  Lower threshold.
+ */
+#define RTCADC_SAR1_WAKEUP_TH_LOW    0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_LOW_M  (RTCADC_SAR1_WAKEUP_TH_LOW_V << RTCADC_SAR1_WAKEUP_TH_LOW_S)
+#define RTCADC_SAR1_WAKEUP_TH_LOW_V  0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_LOW_S  0
+/** RTCADC_SAR1_WAKEUP_TH_HIGH : R/W; bitpos: [25:14]; default: 4095;
+ *  Upper threshold.
+ */
+#define RTCADC_SAR1_WAKEUP_TH_HIGH    0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_HIGH_M  (RTCADC_SAR1_WAKEUP_TH_HIGH_V << RTCADC_SAR1_WAKEUP_TH_HIGH_S)
+#define RTCADC_SAR1_WAKEUP_TH_HIGH_V  0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_HIGH_S  14
+/** RTCADC_SAR1_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
+ *  Indicates that this wakeup event arose from exceeding upper threshold.
+ */
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH    (BIT(29))
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_M  (RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_V << RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_S)
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_V  0x00000001U
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_S  29
+/** RTCADC_SAR1_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
+ *  Wakeup function enable.
+ */
+#define RTCADC_SAR1_WAKEUP_EN    (BIT(30))
+#define RTCADC_SAR1_WAKEUP_EN_M  (RTCADC_SAR1_WAKEUP_EN_V << RTCADC_SAR1_WAKEUP_EN_S)
+#define RTCADC_SAR1_WAKEUP_EN_V  0x00000001U
+#define RTCADC_SAR1_WAKEUP_EN_S  30
+/** RTCADC_SAR1_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
+ *  0:absolute value comparison mode. 1: relative value comparison mode.
+ */
+#define RTCADC_SAR1_WAKEUP_MODE    (BIT(31))
+#define RTCADC_SAR1_WAKEUP_MODE_M  (RTCADC_SAR1_WAKEUP_MODE_V << RTCADC_SAR1_WAKEUP_MODE_S)
+#define RTCADC_SAR1_WAKEUP_MODE_V  0x00000001U
+#define RTCADC_SAR1_WAKEUP_MODE_S  31
+
+/** RTCADC_WAKEUP2_REG register
+ *  ADC2 wakeup configuration registers.
+ */
+#define RTCADC_WAKEUP2_REG (DR_REG_LP_ADC_BASE + 0x64)
+/** RTCADC_SAR2_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0;
+ *  Lower threshold.
+ */
+#define RTCADC_SAR2_WAKEUP_TH_LOW    0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_LOW_M  (RTCADC_SAR2_WAKEUP_TH_LOW_V << RTCADC_SAR2_WAKEUP_TH_LOW_S)
+#define RTCADC_SAR2_WAKEUP_TH_LOW_V  0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_LOW_S  0
+/** RTCADC_SAR2_WAKEUP_TH_HIGH : R/W; bitpos: [25:14]; default: 4095;
+ *  Upper threshold.
+ */
+#define RTCADC_SAR2_WAKEUP_TH_HIGH    0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_HIGH_M  (RTCADC_SAR2_WAKEUP_TH_HIGH_V << RTCADC_SAR2_WAKEUP_TH_HIGH_S)
+#define RTCADC_SAR2_WAKEUP_TH_HIGH_V  0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_HIGH_S  14
+/** RTCADC_SAR2_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
+ *  Indicates that this wakeup event arose from exceeding upper threshold.
+ */
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH    (BIT(29))
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_M  (RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_V << RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_S)
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_V  0x00000001U
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_S  29
+/** RTCADC_SAR2_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
+ *  Wakeup function enable.
+ */
+#define RTCADC_SAR2_WAKEUP_EN    (BIT(30))
+#define RTCADC_SAR2_WAKEUP_EN_M  (RTCADC_SAR2_WAKEUP_EN_V << RTCADC_SAR2_WAKEUP_EN_S)
+#define RTCADC_SAR2_WAKEUP_EN_V  0x00000001U
+#define RTCADC_SAR2_WAKEUP_EN_S  30
+/** RTCADC_SAR2_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
+ *  0:absolute value comparison mode. 1: relative value comparison mode.
+ */
+#define RTCADC_SAR2_WAKEUP_MODE    (BIT(31))
+#define RTCADC_SAR2_WAKEUP_MODE_M  (RTCADC_SAR2_WAKEUP_MODE_V << RTCADC_SAR2_WAKEUP_MODE_S)
+#define RTCADC_SAR2_WAKEUP_MODE_V  0x00000001U
+#define RTCADC_SAR2_WAKEUP_MODE_S  31
+
+/** RTCADC_WAKEUP_SEL_REG register
+ *  Wakeup source select register.
+ */
+#define RTCADC_WAKEUP_SEL_REG (DR_REG_LP_ADC_BASE + 0x68)
+/** RTCADC_SAR_WAKEUP_SEL : R/W; bitpos: [0]; default: 0;
+ *  0: ADC1. 1: ADC2.
+ */
+#define RTCADC_SAR_WAKEUP_SEL    (BIT(0))
+#define RTCADC_SAR_WAKEUP_SEL_M  (RTCADC_SAR_WAKEUP_SEL_V << RTCADC_SAR_WAKEUP_SEL_S)
+#define RTCADC_SAR_WAKEUP_SEL_V  0x00000001U
+#define RTCADC_SAR_WAKEUP_SEL_S  0
+
+/** RTCADC_SAR1_HW_WAKEUP_REG register
+ *  Hardware automatic sampling registers for wakeup function.
+ */
+#define RTCADC_SAR1_HW_WAKEUP_REG (DR_REG_LP_ADC_BASE + 0x6c)
+/** RTCADC_ADC1_HW_READ_EN_I : R/W; bitpos: [0]; default: 0;
+ *  Enable hardware automatic sampling.
+ */
+#define RTCADC_ADC1_HW_READ_EN_I    (BIT(0))
+#define RTCADC_ADC1_HW_READ_EN_I_M  (RTCADC_ADC1_HW_READ_EN_I_V << RTCADC_ADC1_HW_READ_EN_I_S)
+#define RTCADC_ADC1_HW_READ_EN_I_V  0x00000001U
+#define RTCADC_ADC1_HW_READ_EN_I_S  0
+/** RTCADC_ADC1_HW_READ_RATE_I : R/W; bitpos: [16:1]; default: 100;
+ *  Hardware automatic sampling rate.
+ */
+#define RTCADC_ADC1_HW_READ_RATE_I    0x0000FFFFU
+#define RTCADC_ADC1_HW_READ_RATE_I_M  (RTCADC_ADC1_HW_READ_RATE_I_V << RTCADC_ADC1_HW_READ_RATE_I_S)
+#define RTCADC_ADC1_HW_READ_RATE_I_V  0x0000FFFFU
+#define RTCADC_ADC1_HW_READ_RATE_I_S  1
+
+/** RTCADC_SAR2_HW_WAKEUP_REG register
+ *  Hardware automatic sampling registers for wakeup function.
+ */
+#define RTCADC_SAR2_HW_WAKEUP_REG (DR_REG_LP_ADC_BASE + 0x70)
+/** RTCADC_ADC2_HW_READ_EN_I : R/W; bitpos: [0]; default: 0;
+ *  Enable hardware automatic sampling.
+ */
+#define RTCADC_ADC2_HW_READ_EN_I    (BIT(0))
+#define RTCADC_ADC2_HW_READ_EN_I_M  (RTCADC_ADC2_HW_READ_EN_I_V << RTCADC_ADC2_HW_READ_EN_I_S)
+#define RTCADC_ADC2_HW_READ_EN_I_V  0x00000001U
+#define RTCADC_ADC2_HW_READ_EN_I_S  0
+/** RTCADC_ADC2_HW_READ_RATE_I : R/W; bitpos: [16:1]; default: 100;
+ *  Hardware automatic sampling rate.
+ */
+#define RTCADC_ADC2_HW_READ_RATE_I    0x0000FFFFU
+#define RTCADC_ADC2_HW_READ_RATE_I_M  (RTCADC_ADC2_HW_READ_RATE_I_V << RTCADC_ADC2_HW_READ_RATE_I_S)
+#define RTCADC_ADC2_HW_READ_RATE_I_V  0x0000FFFFU
+#define RTCADC_ADC2_HW_READ_RATE_I_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_adc_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_adc_struct.h
new file mode 100644
index 0000000000..e256dd83d4
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_adc_struct.h
@@ -0,0 +1,603 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: ADC1 control registers. */
+/** Type of reader1_ctrl register
+ *  Control the read operation of ADC1.
+ */
+typedef union {
+    struct {
+        /** sar1_clk_div : R/W; bitpos: [7:0]; default: 2;
+         *  Clock divider.
+         */
+        uint32_t sar1_clk_div:8;
+        uint32_t reserved_8:20;
+        /** sar1_data_inv : R/W; bitpos: [28]; default: 0;
+         *  Invert SAR ADC1 data.
+         */
+        uint32_t sar1_data_inv:1;
+        /** sar1_int_en : R/W; bitpos: [29]; default: 1;
+         *  Enable saradc1 to send out interrupt.
+         */
+        uint32_t sar1_int_en:1;
+        /** sar1_en_pad_force_enable : R/W; bitpos: [31:30]; default: 0;
+         *  Force enable adc en_pad to analog circuit 2'b11: force enable .
+         */
+        uint32_t sar1_en_pad_force_enable:2;
+    };
+    uint32_t val;
+} rtcadc_reader1_ctrl_reg_t;
+
+/** Type of meas1_ctrl2 register
+ *  ADC1 configuration registers.
+ */
+typedef union {
+    struct {
+        /** meas1_data_sar : RO; bitpos: [15:0]; default: 0;
+         *  SAR ADC1 data.
+         */
+        uint32_t meas1_data_sar:16;
+        /** meas1_done_sar : RO; bitpos: [16]; default: 0;
+         *  SAR ADC1 conversion done indication.
+         */
+        uint32_t meas1_done_sar:1;
+        /** meas1_start_sar : R/W; bitpos: [17]; default: 0;
+         *  SAR ADC1 controller (in RTC) starts conversion.
+         */
+        uint32_t meas1_start_sar:1;
+        /** meas1_start_force : R/W; bitpos: [18]; default: 0;
+         *  1: SAR ADC1 controller (in RTC) is started by SW.
+         */
+        uint32_t meas1_start_force:1;
+        /** sar1_en_pad : R/W; bitpos: [30:19]; default: 0;
+         *  SAR ADC1 pad enable bitmap.
+         */
+        uint32_t sar1_en_pad:12;
+        /** sar1_en_pad_force : R/W; bitpos: [31]; default: 0;
+         *  1: SAR ADC1 pad enable bitmap is controlled by SW.
+         */
+        uint32_t sar1_en_pad_force:1;
+    };
+    uint32_t val;
+} rtcadc_meas1_ctrl2_reg_t;
+
+/** Type of meas1_mux register
+ *  SAR ADC1 MUX register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** sar1_dig_force : R/W; bitpos: [31]; default: 0;
+         *  1: SAR ADC1 controlled by DIG ADC1 CTRL.
+         */
+        uint32_t sar1_dig_force:1;
+    };
+    uint32_t val;
+} rtcadc_meas1_mux_reg_t;
+
+/** Type of atten1 register
+ *  ADC1 attenuation registers.
+ */
+typedef union {
+    struct {
+        /** sar1_atten : R/W; bitpos: [31:0]; default: 4294967295;
+         *  2-bit attenuation for each pad.
+         */
+        uint32_t sar1_atten:32;
+    };
+    uint32_t val;
+} rtcadc_atten1_reg_t;
+
+
+/** Group: ADC2 control registers. */
+/** Type of reader2_ctrl register
+ *  Control the read operation of ADC2.
+ */
+typedef union {
+    struct {
+        /** sar2_clk_div : R/W; bitpos: [7:0]; default: 2;
+         *  Clock divider.
+         */
+        uint32_t sar2_clk_div:8;
+        uint32_t reserved_8:8;
+        /** sar2_wait_arb_cycle : R/W; bitpos: [17:16]; default: 1;
+         *  Wait arbit stable after sar_done.
+         */
+        uint32_t sar2_wait_arb_cycle:2;
+        uint32_t reserved_18:9;
+        /** sar2_en_pad_force_enable : R/W; bitpos: [28:27]; default: 0;
+         *  Force enable adc en_pad to analog circuit 2'b11: force enable .
+         */
+        uint32_t sar2_en_pad_force_enable:2;
+        /** sar2_data_inv : R/W; bitpos: [29]; default: 0;
+         *  Invert SAR ADC2 data.
+         */
+        uint32_t sar2_data_inv:1;
+        /** sar2_int_en : R/W; bitpos: [30]; default: 1;
+         *  Enable saradc2 to send out interrupt.
+         */
+        uint32_t sar2_int_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} rtcadc_reader2_ctrl_reg_t;
+
+/** Type of meas2_ctrl1 register
+ *  ADC2 configuration registers.
+ */
+typedef union {
+    struct {
+        /** sar2_cntl_state : RO; bitpos: [2:0]; default: 0;
+         *  saradc2_cntl_fsm.
+         */
+        uint32_t sar2_cntl_state:3;
+        /** sar2_pwdet_cal_en : R/W; bitpos: [3]; default: 0;
+         *  RTC control pwdet enable.
+         */
+        uint32_t sar2_pwdet_cal_en:1;
+        /** sar2_pkdet_cal_en : R/W; bitpos: [4]; default: 0;
+         *  RTC control pkdet enable.
+         */
+        uint32_t sar2_pkdet_cal_en:1;
+        /** sar2_en_test : R/W; bitpos: [5]; default: 0;
+         *  SAR2_EN_TEST.
+         */
+        uint32_t sar2_en_test:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_meas2_ctrl1_reg_t;
+
+/** Type of meas2_ctrl2 register
+ *  ADC2 configuration registers.
+ */
+typedef union {
+    struct {
+        /** meas2_data_sar : RO; bitpos: [15:0]; default: 0;
+         *  SAR ADC2 data.
+         */
+        uint32_t meas2_data_sar:16;
+        /** meas2_done_sar : RO; bitpos: [16]; default: 0;
+         *  SAR ADC2 conversion done indication.
+         */
+        uint32_t meas2_done_sar:1;
+        /** meas2_start_sar : R/W; bitpos: [17]; default: 0;
+         *  SAR ADC2 controller (in RTC) starts conversion.
+         */
+        uint32_t meas2_start_sar:1;
+        /** meas2_start_force : R/W; bitpos: [18]; default: 0;
+         *  1: SAR ADC2 controller (in RTC) is started by SW.
+         */
+        uint32_t meas2_start_force:1;
+        /** sar2_en_pad : R/W; bitpos: [30:19]; default: 0;
+         *  SAR ADC2 pad enable bitmap.
+         */
+        uint32_t sar2_en_pad:12;
+        /** sar2_en_pad_force : R/W; bitpos: [31]; default: 0;
+         *  1: SAR ADC2 pad enable bitmap is controlled by SW.
+         */
+        uint32_t sar2_en_pad_force:1;
+    };
+    uint32_t val;
+} rtcadc_meas2_ctrl2_reg_t;
+
+/** Type of meas2_mux register
+ *  SAR ADC2 MUX register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** sar2_pwdet_cct : R/W; bitpos: [30:28]; default: 0;
+         *  SAR2_PWDET_CCT.
+         */
+        uint32_t sar2_pwdet_cct:3;
+        /** sar2_rtc_force : R/W; bitpos: [31]; default: 0;
+         *  In sleep, force to use rtc to control ADC.
+         */
+        uint32_t sar2_rtc_force:1;
+    };
+    uint32_t val;
+} rtcadc_meas2_mux_reg_t;
+
+/** Type of atten2 register
+ *  ADC1 attenuation registers.
+ */
+typedef union {
+    struct {
+        /** sar2_atten : R/W; bitpos: [31:0]; default: 4294967295;
+         *  2-bit attenuation for each pad.
+         */
+        uint32_t sar2_atten:32;
+    };
+    uint32_t val;
+} rtcadc_atten2_reg_t;
+
+
+/** Group: ADC XPD control. */
+/** Type of force_wpd_sar register
+ *  In sleep, force to use rtc to control ADC
+ */
+typedef union {
+    struct {
+        /** force_xpd_sar1 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
+         *  control.
+         */
+        uint32_t force_xpd_sar1:2;
+        /** force_xpd_sar2 : R/W; bitpos: [3:2]; default: 0;
+         *  2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
+         *  control.
+         */
+        uint32_t force_xpd_sar2:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} rtcadc_force_wpd_sar_reg_t;
+
+
+/** Group: RTCADC interrupt registers. */
+/** Type of cocpu_int_raw register
+ *  Interrupt raw registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, int raw.
+         */
+        uint32_t cocpu_saradc1_int_raw:1;
+        /** cocpu_saradc2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, int raw.
+         */
+        uint32_t cocpu_saradc2_int_raw:1;
+        /** cocpu_saradc1_error_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, int raw.
+         */
+        uint32_t cocpu_saradc1_error_int_raw:1;
+        /** cocpu_saradc2_error_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, int raw.
+         */
+        uint32_t cocpu_saradc2_error_int_raw:1;
+        /** cocpu_saradc1_wake_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, int raw.
+         */
+        uint32_t cocpu_saradc1_wake_int_raw:1;
+        /** cocpu_saradc2_wake_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, int raw.
+         */
+        uint32_t cocpu_saradc2_wake_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_cocpu_int_raw_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_ena : R/WTC; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, int enable.
+         */
+        uint32_t cocpu_saradc1_int_ena:1;
+        /** cocpu_saradc2_int_ena : R/WTC; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, int enable.
+         */
+        uint32_t cocpu_saradc2_int_ena:1;
+        /** cocpu_saradc1_error_int_ena : R/WTC; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, int enable.
+         */
+        uint32_t cocpu_saradc1_error_int_ena:1;
+        /** cocpu_saradc2_error_int_ena : R/WTC; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, int enable.
+         */
+        uint32_t cocpu_saradc2_error_int_ena:1;
+        /** cocpu_saradc1_wake_int_ena : R/WTC; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, int enable.
+         */
+        uint32_t cocpu_saradc1_wake_int_ena:1;
+        /** cocpu_saradc2_wake_int_ena : R/WTC; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, int enable.
+         */
+        uint32_t cocpu_saradc2_wake_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_int_ena_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_st : RO; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, int status.
+         */
+        uint32_t cocpu_saradc1_int_st:1;
+        /** cocpu_saradc2_int_st : RO; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, int status.
+         */
+        uint32_t cocpu_saradc2_int_st:1;
+        /** cocpu_saradc1_error_int_st : RO; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, int status.
+         */
+        uint32_t cocpu_saradc1_error_int_st:1;
+        /** cocpu_saradc2_error_int_st : RO; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, int status.
+         */
+        uint32_t cocpu_saradc2_error_int_st:1;
+        /** cocpu_saradc1_wake_int_st : RO; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, int status.
+         */
+        uint32_t cocpu_saradc1_wake_int_st:1;
+        /** cocpu_saradc2_wake_int_st : RO; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, int status.
+         */
+        uint32_t cocpu_saradc2_wake_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_clr : WT; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, int clear.
+         */
+        uint32_t cocpu_saradc1_int_clr:1;
+        /** cocpu_saradc2_int_clr : WT; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, int clear.
+         */
+        uint32_t cocpu_saradc2_int_clr:1;
+        /** cocpu_saradc1_error_int_clr : WT; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, int clear.
+         */
+        uint32_t cocpu_saradc1_error_int_clr:1;
+        /** cocpu_saradc2_error_int_clr : WT; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, int clear.
+         */
+        uint32_t cocpu_saradc2_error_int_clr:1;
+        /** cocpu_saradc1_wake_int_clr : WT; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, int clear.
+         */
+        uint32_t cocpu_saradc1_wake_int_clr:1;
+        /** cocpu_saradc2_wake_int_clr : WT; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, int clear.
+         */
+        uint32_t cocpu_saradc2_wake_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_int_clr_reg_t;
+
+/** Type of int_ena_w1ts register
+ *  Interrupt enable assert registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_ena_w1ts : WT; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc1_int_ena_w1ts:1;
+        /** cocpu_saradc2_int_ena_w1ts : WT; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc2_int_ena_w1ts:1;
+        /** cocpu_saradc1_error_int_ena_w1ts : WT; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc1_error_int_ena_w1ts:1;
+        /** cocpu_saradc2_error_int_ena_w1ts : WT; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc2_error_int_ena_w1ts:1;
+        /** cocpu_saradc1_wake_int_ena_w1ts : WT; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc1_wake_int_ena_w1ts:1;
+        /** cocpu_saradc2_wake_int_ena_w1ts : WT; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc2_wake_int_ena_w1ts:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_int_ena_w1ts_reg_t;
+
+/** Type of int_ena_w1tc register
+ *  Interrupt enable deassert registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_ena_w1tc : WT; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc1_int_ena_w1tc:1;
+        /** cocpu_saradc2_int_ena_w1tc : WT; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc2_int_ena_w1tc:1;
+        /** cocpu_saradc1_error_int_ena_w1tc : WT; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc1_error_int_ena_w1tc:1;
+        /** cocpu_saradc2_error_int_ena_w1tc : WT; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc2_error_int_ena_w1tc:1;
+        /** cocpu_saradc1_wake_int_ena_w1tc : WT; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc1_wake_int_ena_w1tc:1;
+        /** cocpu_saradc2_wake_int_ena_w1tc : WT; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc2_wake_int_ena_w1tc:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_int_ena_w1tc_reg_t;
+
+
+/** Group: RTCADC wakeup control registers. */
+/** Type of wakeup1 register
+ *  ADC1 wakeup configuration registers.
+ */
+typedef union {
+    struct {
+        /** sar1_wakeup_th_low : R/W; bitpos: [11:0]; default: 0;
+         *  Lower threshold.
+         */
+        uint32_t sar1_wakeup_th_low:12;
+        uint32_t reserved_12:2;
+        /** sar1_wakeup_th_high : R/W; bitpos: [25:14]; default: 4095;
+         *  Upper threshold.
+         */
+        uint32_t sar1_wakeup_th_high:12;
+        uint32_t reserved_26:3;
+        /** sar1_wakeup_over_upper_th : RO; bitpos: [29]; default: 0;
+         *  Indicates that this wakeup event arose from exceeding upper threshold.
+         */
+        uint32_t sar1_wakeup_over_upper_th:1;
+        /** sar1_wakeup_en : R/W; bitpos: [30]; default: 0;
+         *  Wakeup function enable.
+         */
+        uint32_t sar1_wakeup_en:1;
+        /** sar1_wakeup_mode : R/W; bitpos: [31]; default: 0;
+         *  0:absolute value comparison mode. 1: relative value comparison mode.
+         */
+        uint32_t sar1_wakeup_mode:1;
+    };
+    uint32_t val;
+} rtcadc_wakeup1_reg_t;
+
+/** Type of wakeup2 register
+ *  ADC2 wakeup configuration registers.
+ */
+typedef union {
+    struct {
+        /** sar2_wakeup_th_low : R/W; bitpos: [11:0]; default: 0;
+         *  Lower threshold.
+         */
+        uint32_t sar2_wakeup_th_low:12;
+        uint32_t reserved_12:2;
+        /** sar2_wakeup_th_high : R/W; bitpos: [25:14]; default: 4095;
+         *  Upper threshold.
+         */
+        uint32_t sar2_wakeup_th_high:12;
+        uint32_t reserved_26:3;
+        /** sar2_wakeup_over_upper_th : RO; bitpos: [29]; default: 0;
+         *  Indicates that this wakeup event arose from exceeding upper threshold.
+         */
+        uint32_t sar2_wakeup_over_upper_th:1;
+        /** sar2_wakeup_en : R/W; bitpos: [30]; default: 0;
+         *  Wakeup function enable.
+         */
+        uint32_t sar2_wakeup_en:1;
+        /** sar2_wakeup_mode : R/W; bitpos: [31]; default: 0;
+         *  0:absolute value comparison mode. 1: relative value comparison mode.
+         */
+        uint32_t sar2_wakeup_mode:1;
+    };
+    uint32_t val;
+} rtcadc_wakeup2_reg_t;
+
+/** Type of wakeup_sel register
+ *  Wakeup source select register.
+ */
+typedef union {
+    struct {
+        /** sar_wakeup_sel : R/W; bitpos: [0]; default: 0;
+         *  0: ADC1. 1: ADC2.
+         */
+        uint32_t sar_wakeup_sel:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rtcadc_wakeup_sel_reg_t;
+
+/** Type of sar1_hw_wakeup register
+ *  Hardware automatic sampling registers for wakeup function.
+ */
+typedef union {
+    struct {
+        /** adc1_hw_read_en_i : R/W; bitpos: [0]; default: 0;
+         *  Enable hardware automatic sampling.
+         */
+        uint32_t adc1_hw_read_en_i:1;
+        /** adc1_hw_read_rate_i : R/W; bitpos: [16:1]; default: 100;
+         *  Hardware automatic sampling rate.
+         */
+        uint32_t adc1_hw_read_rate_i:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} rtcadc_sar1_hw_wakeup_reg_t;
+
+/** Type of sar2_hw_wakeup register
+ *  Hardware automatic sampling registers for wakeup function.
+ */
+typedef union {
+    struct {
+        /** adc2_hw_read_en_i : R/W; bitpos: [0]; default: 0;
+         *  Enable hardware automatic sampling.
+         */
+        uint32_t adc2_hw_read_en_i:1;
+        /** adc2_hw_read_rate_i : R/W; bitpos: [16:1]; default: 100;
+         *  Hardware automatic sampling rate.
+         */
+        uint32_t adc2_hw_read_rate_i:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} rtcadc_sar2_hw_wakeup_reg_t;
+
+
+typedef struct {
+    volatile rtcadc_reader1_ctrl_reg_t reader1_ctrl;
+    uint32_t reserved_004[2];
+    volatile rtcadc_meas1_ctrl2_reg_t meas1_ctrl2;
+    volatile rtcadc_meas1_mux_reg_t meas1_mux;
+    volatile rtcadc_atten1_reg_t atten1;
+    uint32_t reserved_018[3];
+    volatile rtcadc_reader2_ctrl_reg_t reader2_ctrl;
+    uint32_t reserved_028;
+    volatile rtcadc_meas2_ctrl1_reg_t meas2_ctrl1;
+    volatile rtcadc_meas2_ctrl2_reg_t meas2_ctrl2;
+    volatile rtcadc_meas2_mux_reg_t meas2_mux;
+    volatile rtcadc_atten2_reg_t atten2;
+    volatile rtcadc_force_wpd_sar_reg_t force_wpd_sar;
+    uint32_t reserved_040[2];
+    volatile rtcadc_cocpu_int_raw_reg_t cocpu_int_raw;
+    volatile rtcadc_int_ena_reg_t int_ena;
+    volatile rtcadc_int_st_reg_t int_st;
+    volatile rtcadc_int_clr_reg_t int_clr;
+    volatile rtcadc_int_ena_w1ts_reg_t int_ena_w1ts;
+    volatile rtcadc_int_ena_w1tc_reg_t int_ena_w1tc;
+    volatile rtcadc_wakeup1_reg_t wakeup1;
+    volatile rtcadc_wakeup2_reg_t wakeup2;
+    volatile rtcadc_wakeup_sel_reg_t wakeup_sel;
+    volatile rtcadc_sar1_hw_wakeup_reg_t sar1_hw_wakeup;
+    volatile rtcadc_sar2_hw_wakeup_reg_t sar2_hw_wakeup;
+} rtcadc_dev_t;
+
+extern rtcadc_dev_t LP_ADC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rtcadc_dev_t) == 0x74, "Invalid size of rtcadc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_reg.h
new file mode 100644
index 0000000000..aa2d39a1cf
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_reg.h
@@ -0,0 +1,1619 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13424
+
+/** LP_ANALOG_PERI_BOD_MODE0_CNTL_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x0)
+/** LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA    (BIT(6))
+#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_S  6
+/** LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA    (BIT(7))
+#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_V << LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_S  7
+/** LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT    0x000003FFU
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_M  (LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_V << LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_V  0x000003FFU
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_S  8
+/** LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT    0x000003FFU
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_M  (LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_V << LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_S)
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_V  0x000003FFU
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_S  18
+/** LP_ANALOG_PERI_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR    (BIT(28))
+#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_M  (LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_V << LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_S)
+#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_S  28
+/** LP_ANALOG_PERI_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA    (BIT(29))
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_V << LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_S  29
+/** LP_ANALOG_PERI_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL    (BIT(30))
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_M  (LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_V << LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_S)
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_S  30
+/** LP_ANALOG_PERI_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_V << LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_S  31
+
+/** LP_ANALOG_PERI_BOD_MODE1_CNTL_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE1_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x4)
+/** LP_ANALOG_PERI_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_M  (LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_V << LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_S  31
+
+/** LP_ANALOG_PERI_VDD_SOURCE_CNTL_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDD_SOURCE_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x8)
+/** LP_ANALOG_PERI_DETMODE_SEL : R/W; bitpos: [7:0]; default: 255;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_DETMODE_SEL    0x000000FFU
+#define LP_ANALOG_PERI_DETMODE_SEL_M  (LP_ANALOG_PERI_DETMODE_SEL_V << LP_ANALOG_PERI_DETMODE_SEL_S)
+#define LP_ANALOG_PERI_DETMODE_SEL_V  0x000000FFU
+#define LP_ANALOG_PERI_DETMODE_SEL_S  0
+/** LP_ANALOG_PERI_VGOOD_EVENT_RECORD : RO; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD    0x000000FFU
+#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD_M  (LP_ANALOG_PERI_VGOOD_EVENT_RECORD_V << LP_ANALOG_PERI_VGOOD_EVENT_RECORD_S)
+#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD_V  0x000000FFU
+#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD_S  8
+/** LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR : WT; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR    0x000000FFU
+#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_M  (LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_V << LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_S)
+#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_V  0x000000FFU
+#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_S  16
+/** LP_ANALOG_PERI_BOD_SOURCE_ENA : R/W; bitpos: [31:24]; default: 4;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_SOURCE_ENA    0x000000FFU
+#define LP_ANALOG_PERI_BOD_SOURCE_ENA_M  (LP_ANALOG_PERI_BOD_SOURCE_ENA_V << LP_ANALOG_PERI_BOD_SOURCE_ENA_S)
+#define LP_ANALOG_PERI_BOD_SOURCE_ENA_V  0x000000FFU
+#define LP_ANALOG_PERI_BOD_SOURCE_ENA_S  24
+
+/** LP_ANALOG_PERI_VDDBAT_BOD_CNTL_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_BOD_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0xc)
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG    (BIT(0))
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_S  0
+/** LP_ANALOG_PERI_VDDBAT_CHARGER : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGER    (BIT(10))
+#define LP_ANALOG_PERI_VDDBAT_CHARGER_M  (LP_ANALOG_PERI_VDDBAT_CHARGER_V << LP_ANALOG_PERI_VDDBAT_CHARGER_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGER_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGER_S  10
+/** LP_ANALOG_PERI_VDDBAT_CNT_CLR : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CNT_CLR    (BIT(11))
+#define LP_ANALOG_PERI_VDDBAT_CNT_CLR_M  (LP_ANALOG_PERI_VDDBAT_CNT_CLR_V << LP_ANALOG_PERI_VDDBAT_CNT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_CNT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CNT_CLR_S  11
+/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET    0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_M  (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_S)
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_V  0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_S  12
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET    0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_V  0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_S  22
+
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_CNTL_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x10)
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG    (BIT(0))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S  0
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER    (BIT(10))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_V << LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_S  10
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR    (BIT(11))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_V << LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_S  11
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET    0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V  0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S  12
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET    0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V  0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S  22
+
+/** LP_ANALOG_PERI_PG_GLITCH_CNTL_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_PG_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x18)
+/** LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA    (BIT(31))
+#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_M  (LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_S)
+#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_S  31
+
+/** LP_ANALOG_PERI_FIB_ENABLE_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_FIB_ENABLE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c)
+/** LP_ANALOG_PERI_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_ANA_FIB_ENA    0xFFFFFFFFU
+#define LP_ANALOG_PERI_ANA_FIB_ENA_M  (LP_ANALOG_PERI_ANA_FIB_ENA_V << LP_ANALOG_PERI_ANA_FIB_ENA_S)
+#define LP_ANALOG_PERI_ANA_FIB_ENA_V  0xFFFFFFFFU
+#define LP_ANALOG_PERI_ANA_FIB_ENA_S  0
+
+#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
+
+/** LP_ANALOG_PERI_INT_RAW_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x20)
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW    (BIT(27))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S  27
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW    (BIT(28))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S  28
+/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW    (BIT(29))
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_M  (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_S)
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_S  29
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW    (BIT(30))
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_S  30
+/** LP_ANALOG_PERI_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW_M  (LP_ANALOG_PERI_BOD_MODE0_INT_RAW_V << LP_ANALOG_PERI_BOD_MODE0_INT_RAW_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW_S  31
+
+/** LP_ANALOG_PERI_INT_ST_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x24)
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST    (BIT(27))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S  27
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST    (BIT(28))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S  28
+/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST    (BIT(29))
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_M  (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_S)
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_S  29
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST    (BIT(30))
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_S  30
+/** LP_ANALOG_PERI_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ST    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ST_M  (LP_ANALOG_PERI_BOD_MODE0_INT_ST_V << LP_ANALOG_PERI_BOD_MODE0_INT_ST_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ST_S  31
+
+/** LP_ANALOG_PERI_INT_ENA_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x28)
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA    (BIT(27))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S  27
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA    (BIT(28))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S  28
+/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA    (BIT(29))
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_M  (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_S)
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_S  29
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA    (BIT(30))
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_S  30
+/** LP_ANALOG_PERI_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_INT_ENA_V << LP_ANALOG_PERI_BOD_MODE0_INT_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA_S  31
+
+/** LP_ANALOG_PERI_INT_CLR_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x2c)
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR    (BIT(27))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S  27
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR    (BIT(28))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S  28
+/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR    (BIT(29))
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_M  (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_S  29
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR    (BIT(30))
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_S  30
+/** LP_ANALOG_PERI_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR_M  (LP_ANALOG_PERI_BOD_MODE0_INT_CLR_V << LP_ANALOG_PERI_BOD_MODE0_INT_CLR_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR_S  31
+
+/** LP_ANALOG_PERI_LP_INT_RAW_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_LP_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x30)
+/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_M  (LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_S)
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_S  31
+
+/** LP_ANALOG_PERI_LP_INT_ST_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_LP_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x34)
+/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_M  (LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_S)
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_S  31
+
+/** LP_ANALOG_PERI_LP_INT_ENA_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_LP_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x38)
+/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_S  31
+
+/** LP_ANALOG_PERI_LP_INT_CLR_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_LP_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3c)
+/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_M  (LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_S)
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_S  31
+
+/** LP_ANALOG_PERI_TOUCH_APPROACH_WORK_MEAS_NUM_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_APPROACH_WORK_MEAS_NUM_REG (DR_REG_LP_ANALOG_PERI_BASE + 0xfc)
+/** LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_M  (LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_V << LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_S  0
+/** LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1 : R/W; bitpos: [19:10]; default: 100;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_M  (LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_V << LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_S  10
+/** LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0 : R/W; bitpos: [29:20]; default: 100;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_M  (LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_V << LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_S  20
+
+/** LP_ANALOG_PERI_TOUCH_SCAN_CTRL1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SCAN_CTRL1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x100)
+/** LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN    (BIT(0))
+#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_M  (LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_V << LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_S)
+#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_S  0
+/** LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION    (BIT(1))
+#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_M  (LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_V << LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_S)
+#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_S  1
+/** LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP : R/W; bitpos: [16:2]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_M  (LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_V << LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_S)
+#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_S  2
+/** LP_ANALOG_PERI_TOUCH_XPD_WAIT : R/W; bitpos: [31:17]; default: 4;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_XPD_WAIT    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_XPD_WAIT_M  (LP_ANALOG_PERI_TOUCH_XPD_WAIT_V << LP_ANALOG_PERI_TOUCH_XPD_WAIT_S)
+#define LP_ANALOG_PERI_TOUCH_XPD_WAIT_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_XPD_WAIT_S  17
+
+/** LP_ANALOG_PERI_TOUCH_SCAN_CTRL2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SCAN_CTRL2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x104)
+/** LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:6]; default: 65535;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_M  (LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_V << LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_S)
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_S  6
+/** LP_ANALOG_PERI_TOUCH_TIMEOUT_EN : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN    (BIT(22))
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_M  (LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_V << LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_S)
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_S  22
+/** LP_ANALOG_PERI_TOUCH_OUT_RING : R/W; bitpos: [26:23]; default: 15;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_OUT_RING    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_OUT_RING_M  (LP_ANALOG_PERI_TOUCH_OUT_RING_V << LP_ANALOG_PERI_TOUCH_OUT_RING_S)
+#define LP_ANALOG_PERI_TOUCH_OUT_RING_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_OUT_RING_S  23
+/** LP_ANALOG_PERI_FREQ_SCAN_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_FREQ_SCAN_EN    (BIT(27))
+#define LP_ANALOG_PERI_FREQ_SCAN_EN_M  (LP_ANALOG_PERI_FREQ_SCAN_EN_V << LP_ANALOG_PERI_FREQ_SCAN_EN_S)
+#define LP_ANALOG_PERI_FREQ_SCAN_EN_V  0x00000001U
+#define LP_ANALOG_PERI_FREQ_SCAN_EN_S  27
+/** LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT : R/W; bitpos: [29:28]; default: 3;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT    0x00000003U
+#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_M  (LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_V << LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_S)
+#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_V  0x00000003U
+#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_S  28
+
+/** LP_ANALOG_PERI_TOUCH_WORK_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_WORK_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x108)
+/** LP_ANALOG_PERI_DIV_NUM2 : R/W; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_DIV_NUM2    0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM2_M  (LP_ANALOG_PERI_DIV_NUM2_V << LP_ANALOG_PERI_DIV_NUM2_S)
+#define LP_ANALOG_PERI_DIV_NUM2_V  0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM2_S  16
+/** LP_ANALOG_PERI_DIV_NUM1 : R/W; bitpos: [21:19]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_DIV_NUM1    0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM1_M  (LP_ANALOG_PERI_DIV_NUM1_V << LP_ANALOG_PERI_DIV_NUM1_S)
+#define LP_ANALOG_PERI_DIV_NUM1_V  0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM1_S  19
+/** LP_ANALOG_PERI_DIV_NUM0 : R/W; bitpos: [24:22]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_DIV_NUM0    0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM0_M  (LP_ANALOG_PERI_DIV_NUM0_V << LP_ANALOG_PERI_DIV_NUM0_S)
+#define LP_ANALOG_PERI_DIV_NUM0_V  0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM0_S  22
+/** LP_ANALOG_PERI_TOUCH_OUT_SEL : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_OUT_SEL    (BIT(25))
+#define LP_ANALOG_PERI_TOUCH_OUT_SEL_M  (LP_ANALOG_PERI_TOUCH_OUT_SEL_V << LP_ANALOG_PERI_TOUCH_OUT_SEL_S)
+#define LP_ANALOG_PERI_TOUCH_OUT_SEL_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_OUT_SEL_S  25
+/** LP_ANALOG_PERI_TOUCH_OUT_RESET : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_OUT_RESET    (BIT(26))
+#define LP_ANALOG_PERI_TOUCH_OUT_RESET_M  (LP_ANALOG_PERI_TOUCH_OUT_RESET_V << LP_ANALOG_PERI_TOUCH_OUT_RESET_S)
+#define LP_ANALOG_PERI_TOUCH_OUT_RESET_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_OUT_RESET_S  26
+/** LP_ANALOG_PERI_TOUCH_OUT_GATE : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_OUT_GATE    (BIT(27))
+#define LP_ANALOG_PERI_TOUCH_OUT_GATE_M  (LP_ANALOG_PERI_TOUCH_OUT_GATE_V << LP_ANALOG_PERI_TOUCH_OUT_GATE_S)
+#define LP_ANALOG_PERI_TOUCH_OUT_GATE_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_OUT_GATE_S  27
+
+/** LP_ANALOG_PERI_TOUCH_WORK_MEAS_NUM_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_WORK_MEAS_NUM_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x10c)
+/** LP_ANALOG_PERI_TOUCH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2_M  (LP_ANALOG_PERI_TOUCH_MEAS_NUM2_V << LP_ANALOG_PERI_TOUCH_MEAS_NUM2_S)
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2_S  0
+/** LP_ANALOG_PERI_TOUCH_MEAS_NUM1 : R/W; bitpos: [19:10]; default: 100;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1_M  (LP_ANALOG_PERI_TOUCH_MEAS_NUM1_V << LP_ANALOG_PERI_TOUCH_MEAS_NUM1_S)
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1_S  10
+/** LP_ANALOG_PERI_TOUCH_MEAS_NUM0 : R/W; bitpos: [29:20]; default: 100;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0_M  (LP_ANALOG_PERI_TOUCH_MEAS_NUM0_V << LP_ANALOG_PERI_TOUCH_MEAS_NUM0_S)
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0_S  20
+
+/** LP_ANALOG_PERI_TOUCH_FILTER1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FILTER1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x110)
+/** LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN    (BIT(0))
+#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_M  (LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_V << LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_S)
+#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_S  0
+/** LP_ANALOG_PERI_TOUCH_HYSTERESIS : R/W; bitpos: [2:1]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_HYSTERESIS    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_HYSTERESIS_M  (LP_ANALOG_PERI_TOUCH_HYSTERESIS_V << LP_ANALOG_PERI_TOUCH_HYSTERESIS_S)
+#define LP_ANALOG_PERI_TOUCH_HYSTERESIS_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_HYSTERESIS_S  1
+/** LP_ANALOG_PERI_TOUCH_NN_THRES : R/W; bitpos: [4:3]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_NN_THRES    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_NN_THRES_M  (LP_ANALOG_PERI_TOUCH_NN_THRES_V << LP_ANALOG_PERI_TOUCH_NN_THRES_S)
+#define LP_ANALOG_PERI_TOUCH_NN_THRES_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_NN_THRES_S  3
+/** LP_ANALOG_PERI_TOUCH_NOISE_THRES : R/W; bitpos: [6:5]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_NOISE_THRES    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_NOISE_THRES_M  (LP_ANALOG_PERI_TOUCH_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_NOISE_THRES_S)
+#define LP_ANALOG_PERI_TOUCH_NOISE_THRES_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_NOISE_THRES_S  5
+/** LP_ANALOG_PERI_TOUCH_SMOOTH_LVL : R/W; bitpos: [8:7]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_M  (LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_V << LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_S)
+#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_S  7
+/** LP_ANALOG_PERI_TOUCH_JITTER_STEP : R/W; bitpos: [12:9]; default: 1;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_JITTER_STEP    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_JITTER_STEP_M  (LP_ANALOG_PERI_TOUCH_JITTER_STEP_V << LP_ANALOG_PERI_TOUCH_JITTER_STEP_S)
+#define LP_ANALOG_PERI_TOUCH_JITTER_STEP_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_JITTER_STEP_S  9
+/** LP_ANALOG_PERI_TOUCH_FILTER_MODE : R/W; bitpos: [15:13]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FILTER_MODE    0x00000007U
+#define LP_ANALOG_PERI_TOUCH_FILTER_MODE_M  (LP_ANALOG_PERI_TOUCH_FILTER_MODE_V << LP_ANALOG_PERI_TOUCH_FILTER_MODE_S)
+#define LP_ANALOG_PERI_TOUCH_FILTER_MODE_V  0x00000007U
+#define LP_ANALOG_PERI_TOUCH_FILTER_MODE_S  13
+/** LP_ANALOG_PERI_TOUCH_FILTER_EN : R/W; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FILTER_EN    (BIT(16))
+#define LP_ANALOG_PERI_TOUCH_FILTER_EN_M  (LP_ANALOG_PERI_TOUCH_FILTER_EN_V << LP_ANALOG_PERI_TOUCH_FILTER_EN_S)
+#define LP_ANALOG_PERI_TOUCH_FILTER_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_FILTER_EN_S  16
+/** LP_ANALOG_PERI_TOUCH_NN_LIMIT : R/W; bitpos: [20:17]; default: 5;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_NN_LIMIT    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_NN_LIMIT_M  (LP_ANALOG_PERI_TOUCH_NN_LIMIT_V << LP_ANALOG_PERI_TOUCH_NN_LIMIT_S)
+#define LP_ANALOG_PERI_TOUCH_NN_LIMIT_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_NN_LIMIT_S  17
+/** LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT : R/W; bitpos: [28:21]; default: 80;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT    0x000000FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_M  (LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_V << LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_V  0x000000FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_S  21
+/** LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT : R/W; bitpos: [31:29]; default: 3;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT    0x00000007U
+#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_M  (LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_V << LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_S)
+#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_V  0x00000007U
+#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_S  29
+
+/** LP_ANALOG_PERI_TOUCH_FILTER2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FILTER2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x114)
+/** LP_ANALOG_PERI_TOUCH_OUTEN : R/W; bitpos: [29:15]; default: 16383;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_OUTEN    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_OUTEN_M  (LP_ANALOG_PERI_TOUCH_OUTEN_V << LP_ANALOG_PERI_TOUCH_OUTEN_S)
+#define LP_ANALOG_PERI_TOUCH_OUTEN_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_OUTEN_S  15
+/** LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES    (BIT(30))
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_M  (LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_S)
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_S  30
+/** LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES    (BIT(31))
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_M  (LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_V << LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_S)
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_S  31
+
+/** LP_ANALOG_PERI_TOUCH_FILTER3_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FILTER3_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x118)
+/** LP_ANALOG_PERI_TOUCH_BENCHMARK_SW : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_M  (LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_V << LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_S)
+#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_S  0
+/** LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW : WT; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW    (BIT(16))
+#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_M  (LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_V << LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_S)
+#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_S  16
+
+/** LP_ANALOG_PERI_TOUCH_SLP0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SLP0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x11c)
+/** LP_ANALOG_PERI_TOUCH_SLP_TH0 : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SLP_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH0_M  (LP_ANALOG_PERI_TOUCH_SLP_TH0_V << LP_ANALOG_PERI_TOUCH_SLP_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH0_S  0
+/** LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR : WT; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR    (BIT(16))
+#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_M  (LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_V << LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_S  16
+/** LP_ANALOG_PERI_TOUCH_SLP_PAD : R/W; bitpos: [20:17]; default: 15;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SLP_PAD    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_SLP_PAD_M  (LP_ANALOG_PERI_TOUCH_SLP_PAD_V << LP_ANALOG_PERI_TOUCH_SLP_PAD_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_PAD_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_SLP_PAD_S  17
+
+/** LP_ANALOG_PERI_TOUCH_SLP1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SLP1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x120)
+/** LP_ANALOG_PERI_TOUCH_SLP_TH2 : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SLP_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH2_M  (LP_ANALOG_PERI_TOUCH_SLP_TH2_V << LP_ANALOG_PERI_TOUCH_SLP_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH2_S  0
+/** LP_ANALOG_PERI_TOUCH_SLP_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SLP_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH1_M  (LP_ANALOG_PERI_TOUCH_SLP_TH1_V << LP_ANALOG_PERI_TOUCH_SLP_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_CLR_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x124)
+/** LP_ANALOG_PERI_TOUCH_CHANNEL_CLR : WT; bitpos: [14:0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_M  (LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_V << LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_S)
+#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_S  0
+/** LP_ANALOG_PERI_TOUCH_STATUS_CLR : WT; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_STATUS_CLR    (BIT(15))
+#define LP_ANALOG_PERI_TOUCH_STATUS_CLR_M  (LP_ANALOG_PERI_TOUCH_STATUS_CLR_V << LP_ANALOG_PERI_TOUCH_STATUS_CLR_S)
+#define LP_ANALOG_PERI_TOUCH_STATUS_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_STATUS_CLR_S  15
+
+/** LP_ANALOG_PERI_TOUCH_APPROACH_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_APPROACH_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x128)
+/** LP_ANALOG_PERI_TOUCH_APPROACH_PAD0 : R/W; bitpos: [3:0]; default: 15;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_M  (LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_V << LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_S  0
+/** LP_ANALOG_PERI_TOUCH_APPROACH_PAD1 : R/W; bitpos: [7:4]; default: 15;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_M  (LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_V << LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_S  4
+/** LP_ANALOG_PERI_TOUCH_APPROACH_PAD2 : R/W; bitpos: [11:8]; default: 15;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_M  (LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_V << LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_S  8
+/** LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN    (BIT(12))
+#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_M  (LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_V << LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_S  12
+
+/** LP_ANALOG_PERI_TOUCH_FREQ0_SCAN_PARA_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ0_SCAN_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x12c)
+/** LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF    0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_V  0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_S  0
+/** LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF : R/W; bitpos: [8:7]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_S  7
+/** LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS : R/W; bitpos: [12:9]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_M  (LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_V << LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_S  9
+/** LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS : R/W; bitpos: [17:13]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_M  (LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_V << LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_S  13
+/** LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS : R/W; bitpos: [22:18]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_M  (LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_V << LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_S  18
+
+/** LP_ANALOG_PERI_TOUCH_FREQ1_SCAN_PARA_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ1_SCAN_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x130)
+/** LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF    0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_V  0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_S  0
+/** LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF : R/W; bitpos: [8:7]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_S  7
+/** LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS : R/W; bitpos: [12:9]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_M  (LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_V << LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_S  9
+/** LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS : R/W; bitpos: [17:13]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_M  (LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_V << LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_S  13
+/** LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS : R/W; bitpos: [22:18]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_M  (LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_V << LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_S  18
+
+/** LP_ANALOG_PERI_TOUCH_FREQ2_SCAN_PARA_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ2_SCAN_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x134)
+/** LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF    0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_V  0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_S  0
+/** LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF : R/W; bitpos: [8:7]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_S  7
+/** LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS : R/W; bitpos: [12:9]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_M  (LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_V << LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_S  9
+/** LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS : R/W; bitpos: [17:13]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_M  (LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_V << LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_S  13
+/** LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS : R/W; bitpos: [22:18]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_M  (LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_V << LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_S  18
+
+/** LP_ANALOG_PERI_TOUCH_ANA_PARA_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_ANA_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x138)
+/** LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV : R/W; bitpos: [2:0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV    0x00000007U
+#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_M  (LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_V << LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_S)
+#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_V  0x00000007U
+#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_S  0
+/** LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL    (BIT(3))
+#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_M  (LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_V << LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_S)
+#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_S  3
+/** LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL : R/W; bitpos: [10:4]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL    0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_M  (LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_V << LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_S)
+#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_V  0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_S  4
+
+/** LP_ANALOG_PERI_TOUCH_MUX0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_MUX0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x13c)
+/** LP_ANALOG_PERI_TOUCH_DATA_SEL : R/W; bitpos: [9:8]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_DATA_SEL    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_DATA_SEL_M  (LP_ANALOG_PERI_TOUCH_DATA_SEL_V << LP_ANALOG_PERI_TOUCH_DATA_SEL_S)
+#define LP_ANALOG_PERI_TOUCH_DATA_SEL_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_DATA_SEL_S  8
+/** LP_ANALOG_PERI_TOUCH_FREQ_SEL : R/W; bitpos: [11:10]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FREQ_SEL    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ_SEL_M  (LP_ANALOG_PERI_TOUCH_FREQ_SEL_V << LP_ANALOG_PERI_TOUCH_FREQ_SEL_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ_SEL_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ_SEL_S  10
+/** LP_ANALOG_PERI_TOUCH_BUFSEL : R/W; bitpos: [26:12]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_BUFSEL    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_BUFSEL_M  (LP_ANALOG_PERI_TOUCH_BUFSEL_V << LP_ANALOG_PERI_TOUCH_BUFSEL_S)
+#define LP_ANALOG_PERI_TOUCH_BUFSEL_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_BUFSEL_S  12
+/** LP_ANALOG_PERI_TOUCH_DONE_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_DONE_EN    (BIT(27))
+#define LP_ANALOG_PERI_TOUCH_DONE_EN_M  (LP_ANALOG_PERI_TOUCH_DONE_EN_V << LP_ANALOG_PERI_TOUCH_DONE_EN_S)
+#define LP_ANALOG_PERI_TOUCH_DONE_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_DONE_EN_S  27
+/** LP_ANALOG_PERI_TOUCH_DONE_FORCE : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_DONE_FORCE    (BIT(28))
+#define LP_ANALOG_PERI_TOUCH_DONE_FORCE_M  (LP_ANALOG_PERI_TOUCH_DONE_FORCE_V << LP_ANALOG_PERI_TOUCH_DONE_FORCE_S)
+#define LP_ANALOG_PERI_TOUCH_DONE_FORCE_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_DONE_FORCE_S  28
+/** LP_ANALOG_PERI_TOUCH_FSM_EN : R/W; bitpos: [29]; default: 1;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_FSM_EN    (BIT(29))
+#define LP_ANALOG_PERI_TOUCH_FSM_EN_M  (LP_ANALOG_PERI_TOUCH_FSM_EN_V << LP_ANALOG_PERI_TOUCH_FSM_EN_S)
+#define LP_ANALOG_PERI_TOUCH_FSM_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_FSM_EN_S  29
+/** LP_ANALOG_PERI_TOUCH_START_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_START_EN    (BIT(30))
+#define LP_ANALOG_PERI_TOUCH_START_EN_M  (LP_ANALOG_PERI_TOUCH_START_EN_V << LP_ANALOG_PERI_TOUCH_START_EN_S)
+#define LP_ANALOG_PERI_TOUCH_START_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_START_EN_S  30
+/** LP_ANALOG_PERI_TOUCH_START_FORCE : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_START_FORCE    (BIT(31))
+#define LP_ANALOG_PERI_TOUCH_START_FORCE_M  (LP_ANALOG_PERI_TOUCH_START_FORCE_V << LP_ANALOG_PERI_TOUCH_START_FORCE_S)
+#define LP_ANALOG_PERI_TOUCH_START_FORCE_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_START_FORCE_S  31
+
+/** LP_ANALOG_PERI_TOUCH_MUX1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_MUX1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x140)
+/** LP_ANALOG_PERI_TOUCH_START : R/W; bitpos: [14:0]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_START    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_START_M  (LP_ANALOG_PERI_TOUCH_START_V << LP_ANALOG_PERI_TOUCH_START_S)
+#define LP_ANALOG_PERI_TOUCH_START_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_START_S  0
+/** LP_ANALOG_PERI_TOUCH_XPD : R/W; bitpos: [29:15]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_XPD    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_XPD_M  (LP_ANALOG_PERI_TOUCH_XPD_V << LP_ANALOG_PERI_TOUCH_XPD_S)
+#define LP_ANALOG_PERI_TOUCH_XPD_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_XPD_S  15
+
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x144)
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD0_TH0_V << LP_ANALOG_PERI_TOUCH_PAD0_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x148)
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD0_TH1_V << LP_ANALOG_PERI_TOUCH_PAD0_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14c)
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD0_TH2_V << LP_ANALOG_PERI_TOUCH_PAD0_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x150)
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD1_TH0_V << LP_ANALOG_PERI_TOUCH_PAD1_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x154)
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD1_TH1_V << LP_ANALOG_PERI_TOUCH_PAD1_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x158)
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD1_TH2_V << LP_ANALOG_PERI_TOUCH_PAD1_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x15c)
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD2_TH0_V << LP_ANALOG_PERI_TOUCH_PAD2_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x160)
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD2_TH1_V << LP_ANALOG_PERI_TOUCH_PAD2_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x164)
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD2_TH2_V << LP_ANALOG_PERI_TOUCH_PAD2_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x168)
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD3_TH0_V << LP_ANALOG_PERI_TOUCH_PAD3_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x16c)
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD3_TH1_V << LP_ANALOG_PERI_TOUCH_PAD3_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x170)
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD3_TH2_V << LP_ANALOG_PERI_TOUCH_PAD3_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x174)
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD4_TH0_V << LP_ANALOG_PERI_TOUCH_PAD4_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x178)
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD4_TH1_V << LP_ANALOG_PERI_TOUCH_PAD4_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x17c)
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD4_TH2_V << LP_ANALOG_PERI_TOUCH_PAD4_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x180)
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD5_TH0_V << LP_ANALOG_PERI_TOUCH_PAD5_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x184)
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD5_TH1_V << LP_ANALOG_PERI_TOUCH_PAD5_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x188)
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD5_TH2_V << LP_ANALOG_PERI_TOUCH_PAD5_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x18c)
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD6_TH0_V << LP_ANALOG_PERI_TOUCH_PAD6_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x190)
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD6_TH1_V << LP_ANALOG_PERI_TOUCH_PAD6_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x194)
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD6_TH2_V << LP_ANALOG_PERI_TOUCH_PAD6_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x198)
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD7_TH0_V << LP_ANALOG_PERI_TOUCH_PAD7_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x19c)
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD7_TH1_V << LP_ANALOG_PERI_TOUCH_PAD7_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1a0)
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD7_TH2_V << LP_ANALOG_PERI_TOUCH_PAD7_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1a4)
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD8_TH0_V << LP_ANALOG_PERI_TOUCH_PAD8_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1a8)
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD8_TH1_V << LP_ANALOG_PERI_TOUCH_PAD8_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1ac)
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD8_TH2_V << LP_ANALOG_PERI_TOUCH_PAD8_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1b0)
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD9_TH0_V << LP_ANALOG_PERI_TOUCH_PAD9_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1b4)
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD9_TH1_V << LP_ANALOG_PERI_TOUCH_PAD9_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1b8)
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD9_TH2_V << LP_ANALOG_PERI_TOUCH_PAD9_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1bc)
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD10_TH0_V << LP_ANALOG_PERI_TOUCH_PAD10_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c0)
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD10_TH1_V << LP_ANALOG_PERI_TOUCH_PAD10_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c4)
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD10_TH2_V << LP_ANALOG_PERI_TOUCH_PAD10_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c8)
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD11_TH0_V << LP_ANALOG_PERI_TOUCH_PAD11_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1cc)
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD11_TH1_V << LP_ANALOG_PERI_TOUCH_PAD11_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1d0)
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD11_TH2_V << LP_ANALOG_PERI_TOUCH_PAD11_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1d4)
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD12_TH0_V << LP_ANALOG_PERI_TOUCH_PAD12_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1d8)
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD12_TH1_V << LP_ANALOG_PERI_TOUCH_PAD12_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1dc)
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD12_TH2_V << LP_ANALOG_PERI_TOUCH_PAD12_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1e0)
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD13_TH0_V << LP_ANALOG_PERI_TOUCH_PAD13_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1e4)
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD13_TH1_V << LP_ANALOG_PERI_TOUCH_PAD13_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1e8)
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD13_TH2_V << LP_ANALOG_PERI_TOUCH_PAD13_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH0_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1ec)
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH0 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD14_TH0_V << LP_ANALOG_PERI_TOUCH_PAD14_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH1_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1f0)
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH1 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD14_TH1_V << LP_ANALOG_PERI_TOUCH_PAD14_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_S  16
+
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH2_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1f4)
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH2 : R/W; bitpos: [31:16]; default: 0;
+ *  Reserved
+ */
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD14_TH2_V << LP_ANALOG_PERI_TOUCH_PAD14_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_S  16
+
+/** LP_ANALOG_PERI_DATE_REG register
+ *  need_des
+ */
+#define LP_ANALOG_PERI_DATE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3fc)
+/** LP_ANALOG_PERI_LP_ANALOG_PERI_DATE : R/W; bitpos: [30:0]; default: 2294816;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE    0x7FFFFFFFU
+#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_M  (LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_V << LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_S)
+#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_V  0x7FFFFFFFU
+#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_S  0
+/** LP_ANALOG_PERI_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANALOG_PERI_CLK_EN    (BIT(31))
+#define LP_ANALOG_PERI_CLK_EN_M  (LP_ANALOG_PERI_CLK_EN_V << LP_ANALOG_PERI_CLK_EN_S)
+#define LP_ANALOG_PERI_CLK_EN_V  0x00000001U
+#define LP_ANALOG_PERI_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_struct.h
new file mode 100644
index 0000000000..919afa0f27
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_struct.h
@@ -0,0 +1,885 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13424
+
+/** Group: configure_register */
+/** Type of bod_mode0_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_close_flash_ena:1;
+        /** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_pd_rf_ena:1;
+        /** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
+         *  need_des
+         */
+        uint32_t bod_mode0_intr_wait:10;
+        /** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
+         *  need_des
+         */
+        uint32_t bod_mode0_reset_wait:10;
+        /** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_cnt_clr:1;
+        /** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_intr_ena:1;
+        /** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_reset_sel:1;
+        /** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_reset_ena:1;
+    };
+    uint32_t val;
+} lp_analog_peri_bod_mode0_cntl_reg_t;
+
+/** Type of bod_mode1_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode1_reset_ena:1;
+    };
+    uint32_t val;
+} lp_analog_peri_bod_mode1_cntl_reg_t;
+
+/** Type of vdd_source_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** detmode_sel : R/W; bitpos: [7:0]; default: 255;
+         *  need_des
+         */
+        uint32_t detmode_sel:8;
+        /** vgood_event_record : RO; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t vgood_event_record:8;
+        /** vbat_event_record_clr : WT; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t vbat_event_record_clr:8;
+        /** bod_source_ena : R/W; bitpos: [31:24]; default: 4;
+         *  need_des
+         */
+        uint32_t bod_source_ena:8;
+    };
+    uint32_t val;
+} lp_analog_peri_vdd_source_cntl_reg_t;
+
+/** Type of vddbat_bod_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** vddbat_undervoltage_flag : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_flag:1;
+        uint32_t reserved_1:9;
+        /** vddbat_charger : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charger:1;
+        /** vddbat_cnt_clr : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_cnt_clr:1;
+        /** vddbat_upvoltage_target : R/W; bitpos: [21:12]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_upvoltage_target:10;
+        /** vddbat_undervoltage_target : R/W; bitpos: [31:22]; default: 1023;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_target:10;
+    };
+    uint32_t val;
+} lp_analog_peri_vddbat_bod_cntl_reg_t;
+
+/** Type of vddbat_charge_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** vddbat_charge_undervoltage_flag : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_flag:1;
+        uint32_t reserved_1:9;
+        /** vddbat_charge_charger : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_charger:1;
+        /** vddbat_charge_cnt_clr : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_cnt_clr:1;
+        /** vddbat_charge_upvoltage_target : R/W; bitpos: [21:12]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_upvoltage_target:10;
+        /** vddbat_charge_undervoltage_target : R/W; bitpos: [31:22]; default: 1023;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_target:10;
+    };
+    uint32_t val;
+} lp_analog_peri_vddbat_charge_cntl_reg_t;
+
+/** Type of pg_glitch_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** power_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t power_glitch_reset_ena:1;
+    };
+    uint32_t val;
+} lp_analog_peri_pg_glitch_cntl_reg_t;
+
+/** Type of fib_enable register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t ana_fib_ena:32;
+    };
+    uint32_t val;
+} lp_analog_peri_fib_enable_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** vddbat_charge_upvoltage_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_upvoltage_int_raw:1;
+        /** vddbat_charge_undervoltage_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_int_raw:1;
+        /** vddbat_upvoltage_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_upvoltage_int_raw:1;
+        /** vddbat_undervoltage_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_int_raw:1;
+        /** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_int_raw:1;
+    };
+    uint32_t val;
+} lp_analog_peri_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** vddbat_charge_upvoltage_int_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_upvoltage_int_st:1;
+        /** vddbat_charge_undervoltage_int_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_int_st:1;
+        /** vddbat_upvoltage_int_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_upvoltage_int_st:1;
+        /** vddbat_undervoltage_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_int_st:1;
+        /** bod_mode0_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_int_st:1;
+    };
+    uint32_t val;
+} lp_analog_peri_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** vddbat_charge_upvoltage_int_ena : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_upvoltage_int_ena:1;
+        /** vddbat_charge_undervoltage_int_ena : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_int_ena:1;
+        /** vddbat_upvoltage_int_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_upvoltage_int_ena:1;
+        /** vddbat_undervoltage_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_int_ena:1;
+        /** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_int_ena:1;
+    };
+    uint32_t val;
+} lp_analog_peri_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** vddbat_charge_upvoltage_int_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_upvoltage_int_clr:1;
+        /** vddbat_charge_undervoltage_int_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_int_clr:1;
+        /** vddbat_upvoltage_int_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_upvoltage_int_clr:1;
+        /** vddbat_undervoltage_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_int_clr:1;
+        /** bod_mode0_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_int_clr:1;
+    };
+    uint32_t val;
+} lp_analog_peri_int_clr_reg_t;
+
+/** Type of lp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_lp_int_raw:1;
+    };
+    uint32_t val;
+} lp_analog_peri_lp_int_raw_reg_t;
+
+/** Type of lp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_lp_int_st:1;
+    };
+    uint32_t val;
+} lp_analog_peri_lp_int_st_reg_t;
+
+/** Type of lp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_lp_int_ena:1;
+    };
+    uint32_t val;
+} lp_analog_peri_lp_int_ena_reg_t;
+
+/** Type of lp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_lp_int_clr:1;
+    };
+    uint32_t val;
+} lp_analog_peri_lp_int_clr_reg_t;
+
+/** Type of touch_approach_work_meas_num register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_approach_meas_num2 : R/W; bitpos: [9:0]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_approach_meas_num2:10;
+        /** touch_approach_meas_num1 : R/W; bitpos: [19:10]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_approach_meas_num1:10;
+        /** touch_approach_meas_num0 : R/W; bitpos: [29:20]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_approach_meas_num0:10;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_approach_work_meas_num_reg_t;
+
+/** Type of touch_scan_ctrl1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_shield_pad_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_shield_pad_en:1;
+        /** touch_inactive_connection : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_inactive_connection:1;
+        /** touch_scan_pad_map : R/W; bitpos: [16:2]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_scan_pad_map:15;
+        /** touch_xpd_wait : R/W; bitpos: [31:17]; default: 4;
+         *  need_des
+         */
+        uint32_t touch_xpd_wait:15;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_scan_ctrl1_reg_t;
+
+/** Type of touch_scan_ctrl2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** touch_timeout_num : R/W; bitpos: [21:6]; default: 65535;
+         *  need_des
+         */
+        uint32_t touch_timeout_num:16;
+        /** touch_timeout_en : R/W; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_timeout_en:1;
+        /** touch_out_ring : R/W; bitpos: [26:23]; default: 15;
+         *  need_des
+         */
+        uint32_t touch_out_ring:4;
+        /** freq_scan_en : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t freq_scan_en:1;
+        /** freq_scan_cnt_limit : R/W; bitpos: [29:28]; default: 3;
+         *  need_des
+         */
+        uint32_t freq_scan_cnt_limit:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_scan_ctrl2_reg_t;
+
+/** Type of touch_work register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** div_num2 : R/W; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t div_num2:3;
+        /** div_num1 : R/W; bitpos: [21:19]; default: 0;
+         *  need_des
+         */
+        uint32_t div_num1:3;
+        /** div_num0 : R/W; bitpos: [24:22]; default: 0;
+         *  need_des
+         */
+        uint32_t div_num0:3;
+        /** touch_out_sel : R/W; bitpos: [25]; default: 0;
+         *  0: Select the output of the touch as data
+         *  1: Select the output of the touch as clock
+         */
+        uint32_t touch_out_sel:1;
+        /** touch_out_reset : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_out_reset:1;
+        /** touch_out_gate : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_out_gate:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_work_reg_t;
+
+/** Type of touch_work_meas_num register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_meas_num2 : R/W; bitpos: [9:0]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_meas_num2:10;
+        /** touch_meas_num1 : R/W; bitpos: [19:10]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_meas_num1:10;
+        /** touch_meas_num0 : R/W; bitpos: [29:20]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_meas_num0:10;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_work_meas_num_reg_t;
+
+/** Type of touch_filter1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_nn_disupdate_benchmark_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t touch_nn_disupdate_benchmark_en:1;
+        /** touch_hysteresis : R/W; bitpos: [2:1]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_hysteresis:2;
+        /** touch_nn_thres : R/W; bitpos: [4:3]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_nn_thres:2;
+        /** touch_noise_thres : R/W; bitpos: [6:5]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_noise_thres:2;
+        /** touch_smooth_lvl : R/W; bitpos: [8:7]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_smooth_lvl:2;
+        /** touch_jitter_step : R/W; bitpos: [12:9]; default: 1;
+         *  need_des
+         */
+        uint32_t touch_jitter_step:4;
+        /** touch_filter_mode : R/W; bitpos: [15:13]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_filter_mode:3;
+        /** touch_filter_en : R/W; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_filter_en:1;
+        /** touch_nn_limit : R/W; bitpos: [20:17]; default: 5;
+         *  need_des
+         */
+        uint32_t touch_nn_limit:4;
+        /** touch_approach_limit : R/W; bitpos: [28:21]; default: 80;
+         *  need_des
+         */
+        uint32_t touch_approach_limit:8;
+        /** touch_debounce_limit : R/W; bitpos: [31:29]; default: 3;
+         *  need_des
+         */
+        uint32_t touch_debounce_limit:3;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_filter1_reg_t;
+
+/** Type of touch_filter2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:15;
+        /** touch_outen : R/W; bitpos: [29:15]; default: 16383;
+         *  need_des
+         */
+        uint32_t touch_outen:15;
+        /** touch_bypass_noise_thres : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_bypass_noise_thres:1;
+        /** touch_bypass_nn_thres : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_bypass_nn_thres:1;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_filter2_reg_t;
+
+/** Type of touch_filter3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_benchmark_sw : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_benchmark_sw:16;
+        /** touch_update_benchmark_sw : WT; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_update_benchmark_sw:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_filter3_reg_t;
+
+/** Type of touch_slp0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_slp_th0 : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_slp_th0:16;
+        /** touch_slp_channel_clr : WT; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_slp_channel_clr:1;
+        /** touch_slp_pad : R/W; bitpos: [20:17]; default: 15;
+         *  need_des
+         */
+        uint32_t touch_slp_pad:4;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_slp0_reg_t;
+
+/** Type of touch_slp1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_slp_th2 : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_slp_th2:16;
+        /** touch_slp_th1 : R/W; bitpos: [31:16]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_slp_th1:16;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_slp1_reg_t;
+
+/** Type of touch_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_channel_clr : WT; bitpos: [14:0]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_channel_clr:15;
+        /** touch_status_clr : WT; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_status_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_clr_reg_t;
+
+/** Type of touch_approach register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_approach_pad0 : R/W; bitpos: [3:0]; default: 15;
+         *  need_des
+         */
+        uint32_t touch_approach_pad0:4;
+        /** touch_approach_pad1 : R/W; bitpos: [7:4]; default: 15;
+         *  need_des
+         */
+        uint32_t touch_approach_pad1:4;
+        /** touch_approach_pad2 : R/W; bitpos: [11:8]; default: 15;
+         *  need_des
+         */
+        uint32_t touch_approach_pad2:4;
+        /** touch_slp_approach_en : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_slp_approach_en:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_approach_reg_t;
+
+/** Type of touch_freq_scan_para register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_freq_dcap_lpf : R/W; bitpos: [6:0]; default: 0;
+         *  Capacity of the RC low pass filter
+         *  0 ~ 2.54 pF, step 20fF
+         */
+        uint32_t touch_freq_dcap_lpf:7;
+        /** touch_freq_dres_lpf : R/W; bitpos: [8:7]; default: 0;
+         *  Resistance of the RC low pass filter
+         *  0 ~ 4.5 K, step 1.5 K
+         */
+        uint32_t touch_freq_dres_lpf:2;
+        /** touch_freq_drv_ls : R/W; bitpos: [12:9]; default: 0;
+         *  Low speed touch driver, effective when high speed driver is disabled
+         */
+        uint32_t touch_freq_drv_ls:4;
+        /** touch_freq_drv_hs : R/W; bitpos: [17:13]; default: 0;
+         *  High speed touch driver
+         */
+        uint32_t touch_freq_drv_hs:5;
+        /** touch_bypass_shield : R/W; bitpos: [18]; default: 0;
+         *  bypass the shield channel output (only available since ECO1)
+         */
+        uint32_t touch_bypass_shield:1;
+        /** touch_freq_dbias : R/W; bitpos: [22:19]; default: 0;
+         *  Internal LDO voltage
+         */
+        uint32_t touch_freq_dbias:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_freq_scan_para_reg_t;
+
+/** Type of touch_ana_para register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_touch_buf_drv : R/W; bitpos: [2:0]; default: 0;
+         *  The driver of water proof touch buff
+         */
+        uint32_t touch_touch_buf_drv:3;
+        /** touch_touch_en_cal : R/W; bitpos: [3]; default: 0;
+         *  Enable internal loop. Need to turn off touch pad.
+         *  Tuning 'dcap_cal' to change the frequency
+         */
+        uint32_t touch_touch_en_cal:1;
+        /** touch_touch_dcap_cal : R/W; bitpos: [10:4]; default: 0;
+         *  The internal capacitor connected to the touch pad. Effective when 'en_cal' enabled
+         *  Normally set to 0
+         */
+        uint32_t touch_touch_dcap_cal:7;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_ana_para_reg_t;
+
+/** Type of touch_mux0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** touch_data_sel : R/W; bitpos: [9:8]; default: 0;
+         *  The type of the output data for debugging
+         *  0/1: raw data
+         *  2: benchmark
+         *  3: smooth data
+         */
+        uint32_t touch_data_sel:2;
+        /** touch_freq_sel : R/W; bitpos: [11:10]; default: 0;
+         *  The frequency id of the output data for debugging
+         *  0: invalid
+         *  1: Frequency 1
+         *  2: Frequency 2
+         *  3: Frequency 3
+         */
+        uint32_t touch_freq_sel:2;
+        /** touch_bufsel : R/W; bitpos: [26:12]; default: 0;
+         *  The bitmap of the shield pad
+         */
+        uint32_t touch_bufsel:15;
+        /** touch_done_en : R/W; bitpos: [27]; default: 0;
+         *  Force to terminate the touch by software
+         */
+        uint32_t touch_done_en:1;
+        /** touch_done_force : R/W; bitpos: [28]; default: 0;
+         *  0: Select touch_meas_done as the touch timer input
+         *  1: Select software termination as the touch timer input
+         */
+        uint32_t touch_done_force:1;
+        /** touch_fsm_en : R/W; bitpos: [29]; default: 1;
+         *  0: Select software configured parameters for ana
+         *  1: Select hardware calculated parameters for ana
+         */
+        uint32_t touch_fsm_en:1;
+        /** touch_start_en : R/W; bitpos: [30]; default: 0;
+         *  Force to start the touch by software
+         */
+        uint32_t touch_start_en:1;
+        /** touch_start_force : R/W; bitpos: [31]; default: 0;
+         *  0: Select the touch timer to start the touch scanning
+         *  1: Select the software to start the touch scanning
+         */
+        uint32_t touch_start_force:1;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_mux0_reg_t;
+
+/** Type of touch_mux1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_start : R/W; bitpos: [14:0]; default: 0;
+         *  The bitmap of the start touch channels
+         */
+        uint32_t touch_start:15;
+        /** touch_xpd : R/W; bitpos: [29:15]; default: 0;
+         *  The bitmap of the power on touch channels
+         */
+        uint32_t touch_xpd:15;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_mux1_reg_t;
+
+/** Type of touch_pad0_th0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** touch_pad_th : R/W; bitpos: [31:16]; default: 0;
+         *  The threshold to activate a touch channel
+         */
+        uint32_t threshold:16;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_pad_thn_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_analog_peri_date : R/W; bitpos: [30:0]; default: 2294816;
+         *  need_des
+         */
+        uint32_t lp_analog_peri_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_analog_peri_date_reg_t;
+
+
+typedef struct {
+    volatile lp_analog_peri_touch_pad_thn_reg_t thresh[3];
+} lp_analog_peri_touch_padx_thn_reg_t;
+
+typedef struct {
+    volatile lp_analog_peri_bod_mode0_cntl_reg_t bod_mode0_cntl;
+    volatile lp_analog_peri_bod_mode1_cntl_reg_t bod_mode1_cntl;
+    volatile lp_analog_peri_vdd_source_cntl_reg_t vdd_source_cntl;
+    volatile lp_analog_peri_vddbat_bod_cntl_reg_t vddbat_bod_cntl;
+    volatile lp_analog_peri_vddbat_charge_cntl_reg_t vddbat_charge_cntl;
+    uint32_t reserved_014;
+    volatile lp_analog_peri_pg_glitch_cntl_reg_t pg_glitch_cntl;
+    volatile lp_analog_peri_fib_enable_reg_t fib_enable;
+    volatile lp_analog_peri_int_raw_reg_t int_raw;
+    volatile lp_analog_peri_int_st_reg_t int_st;
+    volatile lp_analog_peri_int_ena_reg_t int_ena;
+    volatile lp_analog_peri_int_clr_reg_t int_clr;
+    volatile lp_analog_peri_lp_int_raw_reg_t lp_int_raw;
+    volatile lp_analog_peri_lp_int_st_reg_t lp_int_st;
+    volatile lp_analog_peri_lp_int_ena_reg_t lp_int_ena;
+    volatile lp_analog_peri_lp_int_clr_reg_t lp_int_clr;
+    uint32_t reserved_040[47];
+    volatile lp_analog_peri_touch_approach_work_meas_num_reg_t touch_approach_work_meas_num;
+    volatile lp_analog_peri_touch_scan_ctrl1_reg_t touch_scan_ctrl1;
+    volatile lp_analog_peri_touch_scan_ctrl2_reg_t touch_scan_ctrl2;
+    volatile lp_analog_peri_touch_work_reg_t touch_work;
+    volatile lp_analog_peri_touch_work_meas_num_reg_t touch_work_meas_num;
+    volatile lp_analog_peri_touch_filter1_reg_t touch_filter1;
+    volatile lp_analog_peri_touch_filter2_reg_t touch_filter2;
+    volatile lp_analog_peri_touch_filter3_reg_t touch_filter3;
+    volatile lp_analog_peri_touch_slp0_reg_t touch_slp0;
+    volatile lp_analog_peri_touch_slp1_reg_t touch_slp1;
+    volatile lp_analog_peri_touch_clr_reg_t touch_clr;
+    volatile lp_analog_peri_touch_approach_reg_t touch_approach;
+    volatile lp_analog_peri_touch_freq_scan_para_reg_t touch_freq_scan_para[3];
+    volatile lp_analog_peri_touch_ana_para_reg_t touch_ana_para;
+    volatile lp_analog_peri_touch_mux0_reg_t touch_mux0;
+    volatile lp_analog_peri_touch_mux1_reg_t touch_mux1;
+    volatile lp_analog_peri_touch_padx_thn_reg_t touch_padx_thn[15];
+    uint32_t reserved_1f8[129];
+    volatile lp_analog_peri_date_reg_t date;
+} lp_analog_peri_dev_t;
+
+extern lp_analog_peri_dev_t LP_ANA_PERI;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_analog_peri_dev_t) == 0x400, "Invalid size of lp_analog_peri_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_clkrst_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_clkrst_reg.h
new file mode 100644
index 0000000000..c6b37fe988
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_clkrst_reg.h
@@ -0,0 +1,1036 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_CLKRST_LP_CLK_CONF_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
+/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_SLOW_CLK_SEL    0x00000003U
+#define LP_CLKRST_SLOW_CLK_SEL_M  (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
+#define LP_CLKRST_SLOW_CLK_SEL_V  0x00000003U
+#define LP_CLKRST_SLOW_CLK_SEL_S  0
+/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_FAST_CLK_SEL    0x00000003U
+#define LP_CLKRST_FAST_CLK_SEL_M  (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
+#define LP_CLKRST_FAST_CLK_SEL_V  0x00000003U
+#define LP_CLKRST_FAST_CLK_SEL_S  2
+/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LP_PERI_DIV_NUM    0x0000003FU
+#define LP_CLKRST_LP_PERI_DIV_NUM_M  (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
+#define LP_CLKRST_LP_PERI_DIV_NUM_V  0x0000003FU
+#define LP_CLKRST_LP_PERI_DIV_NUM_S  4
+/** LP_CLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_ANA_SEL_REF_PLL8M    (BIT(10))
+#define LP_CLKRST_ANA_SEL_REF_PLL8M_M  (LP_CLKRST_ANA_SEL_REF_PLL8M_V << LP_CLKRST_ANA_SEL_REF_PLL8M_S)
+#define LP_CLKRST_ANA_SEL_REF_PLL8M_V  0x00000001U
+#define LP_CLKRST_ANA_SEL_REF_PLL8M_S  10
+
+/** LP_CLKRST_LP_CLK_PO_EN_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
+/** LP_CLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN    (BIT(0))
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN_M  (LP_CLKRST_CLK_CORE_EFUSE_OEN_V << LP_CLKRST_CLK_CORE_EFUSE_OEN_S)
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN_S  0
+/** LP_CLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_LP_BUS_OEN    (BIT(1))
+#define LP_CLKRST_CLK_LP_BUS_OEN_M  (LP_CLKRST_CLK_LP_BUS_OEN_V << LP_CLKRST_CLK_LP_BUS_OEN_S)
+#define LP_CLKRST_CLK_LP_BUS_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_LP_BUS_OEN_S  1
+/** LP_CLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_AON_SLOW_OEN    (BIT(2))
+#define LP_CLKRST_CLK_AON_SLOW_OEN_M  (LP_CLKRST_CLK_AON_SLOW_OEN_V << LP_CLKRST_CLK_AON_SLOW_OEN_S)
+#define LP_CLKRST_CLK_AON_SLOW_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_AON_SLOW_OEN_S  2
+/** LP_CLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_AON_FAST_OEN    (BIT(3))
+#define LP_CLKRST_CLK_AON_FAST_OEN_M  (LP_CLKRST_CLK_AON_FAST_OEN_V << LP_CLKRST_CLK_AON_FAST_OEN_S)
+#define LP_CLKRST_CLK_AON_FAST_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_AON_FAST_OEN_S  3
+/** LP_CLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_SLOW_OEN    (BIT(4))
+#define LP_CLKRST_CLK_SLOW_OEN_M  (LP_CLKRST_CLK_SLOW_OEN_V << LP_CLKRST_CLK_SLOW_OEN_S)
+#define LP_CLKRST_CLK_SLOW_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_SLOW_OEN_S  4
+/** LP_CLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_FAST_OEN    (BIT(5))
+#define LP_CLKRST_CLK_FAST_OEN_M  (LP_CLKRST_CLK_FAST_OEN_V << LP_CLKRST_CLK_FAST_OEN_S)
+#define LP_CLKRST_CLK_FAST_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_FAST_OEN_S  5
+/** LP_CLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_FOSC_OEN    (BIT(6))
+#define LP_CLKRST_CLK_FOSC_OEN_M  (LP_CLKRST_CLK_FOSC_OEN_V << LP_CLKRST_CLK_FOSC_OEN_S)
+#define LP_CLKRST_CLK_FOSC_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_FOSC_OEN_S  6
+/** LP_CLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_RC32K_OEN    (BIT(7))
+#define LP_CLKRST_CLK_RC32K_OEN_M  (LP_CLKRST_CLK_RC32K_OEN_V << LP_CLKRST_CLK_RC32K_OEN_S)
+#define LP_CLKRST_CLK_RC32K_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_RC32K_OEN_S  7
+/** LP_CLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_SXTAL_OEN    (BIT(8))
+#define LP_CLKRST_CLK_SXTAL_OEN_M  (LP_CLKRST_CLK_SXTAL_OEN_V << LP_CLKRST_CLK_SXTAL_OEN_S)
+#define LP_CLKRST_CLK_SXTAL_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_SXTAL_OEN_S  8
+/** LP_CLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0;
+ *  1'b1: probe sosc clk on
+ *  1'b0: probe sosc clk off
+ */
+#define LP_CLKRST_CLK_SOSC_OEN    (BIT(9))
+#define LP_CLKRST_CLK_SOSC_OEN_M  (LP_CLKRST_CLK_SOSC_OEN_V << LP_CLKRST_CLK_SOSC_OEN_S)
+#define LP_CLKRST_CLK_SOSC_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_SOSC_OEN_S  9
+
+/** LP_CLKRST_LP_CLK_EN_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
+/** LP_CLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON    (BIT(26))
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_M  (LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S)
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S  26
+/** LP_CLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_CK_EN_LP_RAM    (BIT(27))
+#define LP_CLKRST_CK_EN_LP_RAM_M  (LP_CLKRST_CK_EN_LP_RAM_V << LP_CLKRST_CK_EN_LP_RAM_S)
+#define LP_CLKRST_CK_EN_LP_RAM_V  0x00000001U
+#define LP_CLKRST_CK_EN_LP_RAM_S  27
+/** LP_CLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_ETM_EVENT_TICK_EN    (BIT(28))
+#define LP_CLKRST_ETM_EVENT_TICK_EN_M  (LP_CLKRST_ETM_EVENT_TICK_EN_V << LP_CLKRST_ETM_EVENT_TICK_EN_S)
+#define LP_CLKRST_ETM_EVENT_TICK_EN_V  0x00000001U
+#define LP_CLKRST_ETM_EVENT_TICK_EN_S  28
+/** LP_CLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON    (BIT(29))
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON_M  (LP_CLKRST_PLL8M_CLK_FORCE_ON_V << LP_CLKRST_PLL8M_CLK_FORCE_ON_S)
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON_S  29
+/** LP_CLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_XTAL_CLK_FORCE_ON    (BIT(30))
+#define LP_CLKRST_XTAL_CLK_FORCE_ON_M  (LP_CLKRST_XTAL_CLK_FORCE_ON_V << LP_CLKRST_XTAL_CLK_FORCE_ON_S)
+#define LP_CLKRST_XTAL_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_XTAL_CLK_FORCE_ON_S  30
+/** LP_CLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_FOSC_CLK_FORCE_ON    (BIT(31))
+#define LP_CLKRST_FOSC_CLK_FORCE_ON_M  (LP_CLKRST_FOSC_CLK_FORCE_ON_V << LP_CLKRST_FOSC_CLK_FORCE_ON_S)
+#define LP_CLKRST_FOSC_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_FOSC_CLK_FORCE_ON_S  31
+
+/** LP_CLKRST_LP_RST_EN_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
+/** LP_CLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_HUK    (BIT(24))
+#define LP_CLKRST_RST_EN_LP_HUK_M  (LP_CLKRST_RST_EN_LP_HUK_V << LP_CLKRST_RST_EN_LP_HUK_S)
+#define LP_CLKRST_RST_EN_LP_HUK_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_HUK_S  24
+/** LP_CLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_ANAPERI    (BIT(25))
+#define LP_CLKRST_RST_EN_LP_ANAPERI_M  (LP_CLKRST_RST_EN_LP_ANAPERI_V << LP_CLKRST_RST_EN_LP_ANAPERI_S)
+#define LP_CLKRST_RST_EN_LP_ANAPERI_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_ANAPERI_S  25
+/** LP_CLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_WDT    (BIT(26))
+#define LP_CLKRST_RST_EN_LP_WDT_M  (LP_CLKRST_RST_EN_LP_WDT_V << LP_CLKRST_RST_EN_LP_WDT_S)
+#define LP_CLKRST_RST_EN_LP_WDT_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_WDT_S  26
+/** LP_CLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_TIMER    (BIT(27))
+#define LP_CLKRST_RST_EN_LP_TIMER_M  (LP_CLKRST_RST_EN_LP_TIMER_V << LP_CLKRST_RST_EN_LP_TIMER_S)
+#define LP_CLKRST_RST_EN_LP_TIMER_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_TIMER_S  27
+/** LP_CLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_RTC    (BIT(28))
+#define LP_CLKRST_RST_EN_LP_RTC_M  (LP_CLKRST_RST_EN_LP_RTC_V << LP_CLKRST_RST_EN_LP_RTC_S)
+#define LP_CLKRST_RST_EN_LP_RTC_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_RTC_S  28
+/** LP_CLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_MAILBOX    (BIT(29))
+#define LP_CLKRST_RST_EN_LP_MAILBOX_M  (LP_CLKRST_RST_EN_LP_MAILBOX_V << LP_CLKRST_RST_EN_LP_MAILBOX_S)
+#define LP_CLKRST_RST_EN_LP_MAILBOX_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_MAILBOX_S  29
+/** LP_CLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG    (BIT(30))
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_M  (LP_CLKRST_RST_EN_LP_AONEFUSEREG_V << LP_CLKRST_RST_EN_LP_AONEFUSEREG_S)
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_S  30
+/** LP_CLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_RAM    (BIT(31))
+#define LP_CLKRST_RST_EN_LP_RAM_M  (LP_CLKRST_RST_EN_LP_RAM_V << LP_CLKRST_RST_EN_LP_RAM_S)
+#define LP_CLKRST_RST_EN_LP_RAM_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_RAM_S  31
+
+/** LP_CLKRST_RESET_CAUSE_REG register
+ *  need_des
+ */
+#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
+/** LP_CLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0;
+ *  6'h1: POR reset
+ *  6'h9: PMU LP PERI power down reset
+ *  6'ha: PMU LP CPU reset
+ *  6'hf: brown out reset
+ *  6'h10: LP watchdog chip reset
+ *  6'h12: super watch dog reset
+ *  6'h13: glitch reset
+ *  6'h14: software reset
+ */
+#define LP_CLKRST_LPCORE_RESET_CAUSE    0x0000003FU
+#define LP_CLKRST_LPCORE_RESET_CAUSE_M  (LP_CLKRST_LPCORE_RESET_CAUSE_V << LP_CLKRST_LPCORE_RESET_CAUSE_S)
+#define LP_CLKRST_LPCORE_RESET_CAUSE_V  0x0000003FU
+#define LP_CLKRST_LPCORE_RESET_CAUSE_S  0
+/** LP_CLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LPCORE_RESET_FLAG    (BIT(6))
+#define LP_CLKRST_LPCORE_RESET_FLAG_M  (LP_CLKRST_LPCORE_RESET_FLAG_V << LP_CLKRST_LPCORE_RESET_FLAG_S)
+#define LP_CLKRST_LPCORE_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_FLAG_S  6
+/** LP_CLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0;
+ *  6'h1: POR reset
+ *  6'h3: digital system software reset
+ *  6'h5: PMU HP system power down reset
+ *  6'h7: HP system reset from HP watchdog
+ *  6'h9: HP system reset from LP watchdog
+ *  6'hb: HP core reset from HP watchdog
+ *  6'hc: HP core software reset
+ *  6'hd: HP core reset from LP watchdog
+ *  6'hf: brown out reset
+ *  6'h10: LP watchdog chip reset
+ *  6'h12: super watch dog reset
+ *  6'h13: glitch reset
+ *  6'h14: efuse crc error reset
+ *  6'h16: HP usb jtag chip reset
+ *  6'h17: HP usb uart chip reset
+ *  6'h18: HP jtag reset
+ *  6'h1a: HP core lockup
+ */
+#define LP_CLKRST_HPCORE0_RESET_CAUSE    0x0000003FU
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_M  (LP_CLKRST_HPCORE0_RESET_CAUSE_V << LP_CLKRST_HPCORE0_RESET_CAUSE_S)
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_V  0x0000003FU
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_S  7
+/** LP_CLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_RESET_FLAG    (BIT(13))
+#define LP_CLKRST_HPCORE0_RESET_FLAG_M  (LP_CLKRST_HPCORE0_RESET_FLAG_V << LP_CLKRST_HPCORE0_RESET_FLAG_S)
+#define LP_CLKRST_HPCORE0_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_HPCORE0_RESET_FLAG_S  13
+/** LP_CLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0;
+ *  6'h1: POR reset
+ *  6'h3: digital system software reset
+ *  6'h5: PMU HP system power down reset
+ *  6'h7: HP system reset from HP watchdog
+ *  6'h9: HP system reset from LP watchdog
+ *  6'hb: HP core reset from HP watchdog
+ *  6'hc: HP core software reset
+ *  6'hd: HP core reset from LP watchdog
+ *  6'hf: brown out reset
+ *  6'h10: LP watchdog chip reset
+ *  6'h12: super watch dog reset
+ *  6'h13: glitch reset
+ *  6'h14: efuse crc error reset
+ *  6'h16: HP usb jtag chip reset
+ *  6'h17: HP usb uart chip reset
+ *  6'h18: HP jtag reset
+ *  6'h1a: HP core lockup
+ */
+#define LP_CLKRST_HPCORE1_RESET_CAUSE    0x0000003FU
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_M  (LP_CLKRST_HPCORE1_RESET_CAUSE_V << LP_CLKRST_HPCORE1_RESET_CAUSE_S)
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_V  0x0000003FU
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_S  14
+/** LP_CLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_RESET_FLAG    (BIT(20))
+#define LP_CLKRST_HPCORE1_RESET_FLAG_M  (LP_CLKRST_HPCORE1_RESET_FLAG_V << LP_CLKRST_HPCORE1_RESET_FLAG_S)
+#define LP_CLKRST_HPCORE1_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_HPCORE1_RESET_FLAG_S  20
+/** LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1;
+ *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
+ *  pmu_lp_cpu_reset reset_cause
+ */
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK    (BIT(25))
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M  (LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S)
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S  25
+/** LP_CLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR    (BIT(26))
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_M  (LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S  26
+/** LP_CLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR    (BIT(27))
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_M  (LP_CLKRST_LPCORE_RESET_FLAG_CLR_V << LP_CLKRST_LPCORE_RESET_FLAG_CLR_S)
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_S  27
+/** LP_CLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR    (BIT(28))
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_M  (LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S  28
+/** LP_CLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR    (BIT(29))
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_M  (LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S)
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S  29
+/** LP_CLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR    (BIT(30))
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_M  (LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S  30
+/** LP_CLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR    (BIT(31))
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_M  (LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S)
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S  31
+
+/** LP_CLKRST_HPCPU_RESET_CTRL0_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x14)
+/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0;
+ *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
+ *  reset feature
+ */
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN    (BIT(0))
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S  0
+/** LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH    0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M  (LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S)
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V  0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S  1
+/** LP_CLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0;
+ *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
+ *  hpcore0 feature
+ */
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN    (BIT(4))
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_M  (LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S)
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V  0x00000001U
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S  4
+/** LP_CLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_STALL_WAIT    0x0000007FU
+#define LP_CLKRST_HPCORE0_STALL_WAIT_M  (LP_CLKRST_HPCORE0_STALL_WAIT_V << LP_CLKRST_HPCORE0_STALL_WAIT_S)
+#define LP_CLKRST_HPCORE0_STALL_WAIT_V  0x0000007FU
+#define LP_CLKRST_HPCORE0_STALL_WAIT_S  5
+/** LP_CLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_STALL_EN    (BIT(12))
+#define LP_CLKRST_HPCORE0_STALL_EN_M  (LP_CLKRST_HPCORE0_STALL_EN_V << LP_CLKRST_HPCORE0_STALL_EN_S)
+#define LP_CLKRST_HPCORE0_STALL_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE0_STALL_EN_S  12
+/** LP_CLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_SW_RESET    (BIT(13))
+#define LP_CLKRST_HPCORE0_SW_RESET_M  (LP_CLKRST_HPCORE0_SW_RESET_V << LP_CLKRST_HPCORE0_SW_RESET_S)
+#define LP_CLKRST_HPCORE0_SW_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE0_SW_RESET_S  13
+/** LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET    (BIT(14))
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_M  (LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S)
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S  14
+/** LP_CLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1;
+ *  1'b1: boot from HP TCM ROM: 0x4FC00000
+ *  1'b0: boot from LP TCM RAM:  0x50108000
+ */
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL    (BIT(15))
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_M  (LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S)
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V  0x00000001U
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S  15
+/** LP_CLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0;
+ *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
+ *  reset feature
+ */
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN    (BIT(16))
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S)
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S  16
+/** LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH    0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M  (LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S)
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V  0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S  17
+/** LP_CLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0;
+ *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
+ *  hpcore1 feature
+ */
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN    (BIT(20))
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_M  (LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S)
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V  0x00000001U
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S  20
+/** LP_CLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_STALL_WAIT    0x0000007FU
+#define LP_CLKRST_HPCORE1_STALL_WAIT_M  (LP_CLKRST_HPCORE1_STALL_WAIT_V << LP_CLKRST_HPCORE1_STALL_WAIT_S)
+#define LP_CLKRST_HPCORE1_STALL_WAIT_V  0x0000007FU
+#define LP_CLKRST_HPCORE1_STALL_WAIT_S  21
+/** LP_CLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_STALL_EN    (BIT(28))
+#define LP_CLKRST_HPCORE1_STALL_EN_M  (LP_CLKRST_HPCORE1_STALL_EN_V << LP_CLKRST_HPCORE1_STALL_EN_S)
+#define LP_CLKRST_HPCORE1_STALL_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE1_STALL_EN_S  28
+/** LP_CLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_SW_RESET    (BIT(29))
+#define LP_CLKRST_HPCORE1_SW_RESET_M  (LP_CLKRST_HPCORE1_SW_RESET_V << LP_CLKRST_HPCORE1_SW_RESET_S)
+#define LP_CLKRST_HPCORE1_SW_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE1_SW_RESET_S  29
+/** LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET    (BIT(30))
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_M  (LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S)
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S  30
+/** LP_CLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1;
+ *  1'b1: boot from HP TCM ROM: 0x4FC00000
+ *  1'b0: boot from LP TCM RAM:  0x50108000
+ */
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL    (BIT(31))
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_M  (LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S)
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V  0x00000001U
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S  31
+
+/** LP_CLKRST_HPCPU_RESET_CTRL1_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x18)
+/** LP_CLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0;
+ *  HP core0 software stall when set to 8'h86
+ */
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE    0x000000FFU
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE_M  (LP_CLKRST_HPCORE0_SW_STALL_CODE_V << LP_CLKRST_HPCORE0_SW_STALL_CODE_S)
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE_V  0x000000FFU
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE_S  16
+/** LP_CLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0;
+ *  HP core1 software stall when set to 8'h86
+ */
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE    0x000000FFU
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE_M  (LP_CLKRST_HPCORE1_SW_STALL_CODE_V << LP_CLKRST_HPCORE1_SW_STALL_CODE_S)
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE_V  0x000000FFU
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE_S  24
+
+/** LP_CLKRST_FOSC_CNTL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
+/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400;
+ *  need_des
+ */
+#define LP_CLKRST_FOSC_DFREQ    0x000003FFU
+#define LP_CLKRST_FOSC_DFREQ_M  (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
+#define LP_CLKRST_FOSC_DFREQ_V  0x000003FFU
+#define LP_CLKRST_FOSC_DFREQ_S  22
+
+/** LP_CLKRST_RC32K_CNTL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x20)
+/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650;
+ *  need_des
+ */
+#define LP_CLKRST_RC32K_DFREQ    0xFFFFFFFFU
+#define LP_CLKRST_RC32K_DFREQ_M  (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
+#define LP_CLKRST_RC32K_DFREQ_V  0xFFFFFFFFU
+#define LP_CLKRST_RC32K_DFREQ_S  0
+
+/** LP_CLKRST_SOSC_CNTL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_SOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x24)
+/** LP_CLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
+ *  need_des
+ */
+#define LP_CLKRST_SOSC_DFREQ    0x000003FFU
+#define LP_CLKRST_SOSC_DFREQ_M  (LP_CLKRST_SOSC_DFREQ_V << LP_CLKRST_SOSC_DFREQ_S)
+#define LP_CLKRST_SOSC_DFREQ_V  0x000003FFU
+#define LP_CLKRST_SOSC_DFREQ_S  22
+
+/** LP_CLKRST_CLK_TO_HP_REG register
+ *  need_des
+ */
+#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x28)
+/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define LP_CLKRST_ICG_HP_XTAL32K    (BIT(28))
+#define LP_CLKRST_ICG_HP_XTAL32K_M  (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
+#define LP_CLKRST_ICG_HP_XTAL32K_V  0x00000001U
+#define LP_CLKRST_ICG_HP_XTAL32K_S  28
+/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define LP_CLKRST_ICG_HP_SOSC    (BIT(29))
+#define LP_CLKRST_ICG_HP_SOSC_M  (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
+#define LP_CLKRST_ICG_HP_SOSC_V  0x00000001U
+#define LP_CLKRST_ICG_HP_SOSC_S  29
+/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define LP_CLKRST_ICG_HP_OSC32K    (BIT(30))
+#define LP_CLKRST_ICG_HP_OSC32K_M  (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
+#define LP_CLKRST_ICG_HP_OSC32K_V  0x00000001U
+#define LP_CLKRST_ICG_HP_OSC32K_S  30
+/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
+ *  reserved
+ */
+#define LP_CLKRST_ICG_HP_FOSC    (BIT(31))
+#define LP_CLKRST_ICG_HP_FOSC_M  (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
+#define LP_CLKRST_ICG_HP_FOSC_V  0x00000001U
+#define LP_CLKRST_ICG_HP_FOSC_S  31
+
+/** LP_CLKRST_LPMEM_FORCE_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
+/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON    (BIT(31))
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M  (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S  31
+
+/** LP_CLKRST_XTAL32K_REG register
+ *  need_des
+ */
+#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x30)
+/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
+ *  need_des
+ */
+#define LP_CLKRST_DRES_XTAL32K    0x00000007U
+#define LP_CLKRST_DRES_XTAL32K_M  (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
+#define LP_CLKRST_DRES_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DRES_XTAL32K_S  22
+/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
+ *  need_des
+ */
+#define LP_CLKRST_DGM_XTAL32K    0x00000007U
+#define LP_CLKRST_DGM_XTAL32K_M  (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
+#define LP_CLKRST_DGM_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DGM_XTAL32K_S  25
+/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_DBUF_XTAL32K    (BIT(28))
+#define LP_CLKRST_DBUF_XTAL32K_M  (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
+#define LP_CLKRST_DBUF_XTAL32K_V  0x00000001U
+#define LP_CLKRST_DBUF_XTAL32K_S  28
+/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
+ *  need_des
+ */
+#define LP_CLKRST_DAC_XTAL32K    0x00000007U
+#define LP_CLKRST_DAC_XTAL32K_M  (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
+#define LP_CLKRST_DAC_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DAC_XTAL32K_S  29
+
+/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG register
+ *  need_des
+ */
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x34)
+/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS    0xFFFFFFFFU
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_M  (LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S)
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V  0xFFFFFFFFU
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S  0
+
+/** LP_CLKRST_HPSYS_0_RESET_BYPASS_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x38)
+/** LP_CLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS    0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_M  (LP_CLKRST_HPSYS_0_RESET_BYPASS_V << LP_CLKRST_HPSYS_0_RESET_BYPASS_S)
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_V  0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_S  0
+
+/** LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x3c)
+/** LP_CLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS    0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_M  (LP_CLKRST_HPSYS_APM_RESET_BYPASS_V << LP_CLKRST_HPSYS_APM_RESET_BYPASS_S)
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_V  0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_S  0
+
+/** LP_CLKRST_HP_CLK_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define LP_CLKRST_HP_CLK_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x40)
+/** LP_CLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
+ */
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL    0x00000003U
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_M  (LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S)
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V  0x00000003U
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S  0
+/** LP_CLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  HP SoC Root Clock Enable.
+ */
+#define LP_CLKRST_HP_ROOT_CLK_EN    (BIT(2))
+#define LP_CLKRST_HP_ROOT_CLK_EN_M  (LP_CLKRST_HP_ROOT_CLK_EN_V << LP_CLKRST_HP_ROOT_CLK_EN_S)
+#define LP_CLKRST_HP_ROOT_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_ROOT_CLK_EN_S  2
+/** LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  PARLIO TX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN    (BIT(3))
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_M  (LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S  3
+/** LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  PARLIO RX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN    (BIT(4))
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_M  (LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S  4
+/** LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  UART4 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN    (BIT(5))
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S  5
+/** LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  UART3 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN    (BIT(6))
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S  6
+/** LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  UART2 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN    (BIT(7))
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S  7
+/** LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  UART1 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN    (BIT(8))
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S  8
+/** LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  UART0 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN    (BIT(9))
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S  9
+/** LP_CLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1;
+ *  I2S2 MCLK Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN    (BIT(10))
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S)
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S  10
+/** LP_CLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1;
+ *  I2S1 MCLK Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN    (BIT(11))
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S)
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S  11
+/** LP_CLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1;
+ *  I2S0 MCLK Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN    (BIT(12))
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S)
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S  12
+/** LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1;
+ *  EMAC RX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN    (BIT(13))
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S  13
+/** LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1;
+ *  EMAC TX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN    (BIT(14))
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S  14
+/** LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  EMAC TXRX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN    (BIT(15))
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S  15
+/** LP_CLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  XTAL 32K Clock Enable.
+ */
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN    (BIT(16))
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN_M  (LP_CLKRST_HP_XTAL_32K_CLK_EN_V << LP_CLKRST_HP_XTAL_32K_CLK_EN_S)
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN_S  16
+/** LP_CLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1;
+ *  RC 32K Clock Enable.
+ */
+#define LP_CLKRST_HP_RC_32K_CLK_EN    (BIT(17))
+#define LP_CLKRST_HP_RC_32K_CLK_EN_M  (LP_CLKRST_HP_RC_32K_CLK_EN_V << LP_CLKRST_HP_RC_32K_CLK_EN_S)
+#define LP_CLKRST_HP_RC_32K_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_RC_32K_CLK_EN_S  17
+/** LP_CLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1;
+ *  SOSC 150K Clock Enable.
+ */
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN    (BIT(18))
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN_M  (LP_CLKRST_HP_SOSC_150K_CLK_EN_V << LP_CLKRST_HP_SOSC_150K_CLK_EN_S)
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN_S  18
+/** LP_CLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  PLL 8M Clock Enable.
+ */
+#define LP_CLKRST_HP_PLL_8M_CLK_EN    (BIT(19))
+#define LP_CLKRST_HP_PLL_8M_CLK_EN_M  (LP_CLKRST_HP_PLL_8M_CLK_EN_V << LP_CLKRST_HP_PLL_8M_CLK_EN_S)
+#define LP_CLKRST_HP_PLL_8M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PLL_8M_CLK_EN_S  19
+/** LP_CLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  AUDIO PLL Clock Enable.
+ */
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN    (BIT(20))
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_M  (LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S)
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S  20
+/** LP_CLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1;
+ *  SDIO PLL2 Clock Enable.
+ */
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN    (BIT(21))
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S)
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S  21
+/** LP_CLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  SDIO PLL1 Clock Enable.
+ */
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN    (BIT(22))
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S)
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S  22
+/** LP_CLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  SDIO PLL0 Clock Enable.
+ */
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN    (BIT(23))
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S)
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S  23
+/** LP_CLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1;
+ *  FOSC 20M Clock Enable.
+ */
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN    (BIT(24))
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN_M  (LP_CLKRST_HP_FOSC_20M_CLK_EN_V << LP_CLKRST_HP_FOSC_20M_CLK_EN_S)
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN_S  24
+/** LP_CLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1;
+ *  XTAL 40M Clock Enable.
+ */
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN    (BIT(25))
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN_M  (LP_CLKRST_HP_XTAL_40M_CLK_EN_V << LP_CLKRST_HP_XTAL_40M_CLK_EN_S)
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN_S  25
+/** LP_CLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  CPLL 400M Clock Enable.
+ */
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN    (BIT(26))
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN_M  (LP_CLKRST_HP_CPLL_400M_CLK_EN_V << LP_CLKRST_HP_CPLL_400M_CLK_EN_S)
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN_S  26
+/** LP_CLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  SPLL 480M Clock Enable.
+ */
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN    (BIT(27))
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN_M  (LP_CLKRST_HP_SPLL_480M_CLK_EN_V << LP_CLKRST_HP_SPLL_480M_CLK_EN_S)
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN_S  27
+/** LP_CLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  MPLL 500M Clock Enable.
+ */
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN    (BIT(28))
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN_M  (LP_CLKRST_HP_MPLL_500M_CLK_EN_V << LP_CLKRST_HP_MPLL_500M_CLK_EN_S)
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN_S  28
+
+/** LP_CLKRST_HP_USB_CLKRST_CTRL0_REG register
+ *  HP USB Clock Reset Control Register.
+ */
+#define LP_CLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x44)
+/** LP_CLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE    (BIT(0))
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE_M  (LP_CLKRST_USB_OTG20_SLEEP_MODE_V << LP_CLKRST_USB_OTG20_SLEEP_MODE_S)
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE_S  0
+/** LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN    (BIT(1))
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_M  (LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S)
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S  1
+/** LP_CLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE    (BIT(2))
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE_M  (LP_CLKRST_USB_OTG11_SLEEP_MODE_V << LP_CLKRST_USB_OTG11_SLEEP_MODE_S)
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE_V  0x00000001U
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE_S  2
+/** LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN    (BIT(3))
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_M  (LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S)
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S  3
+/** LP_CLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  usb otg11 fs phy clock enable.
+ */
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN    (BIT(4))
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN_M  (LP_CLKRST_USB_OTG11_48M_CLK_EN_V << LP_CLKRST_USB_OTG11_48M_CLK_EN_S)
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN_S  4
+/** LP_CLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  usb device fs phy clock enable.
+ */
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN    (BIT(5))
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_M  (LP_CLKRST_USB_DEVICE_48M_CLK_EN_V << LP_CLKRST_USB_DEVICE_48M_CLK_EN_S)
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_S  5
+/** LP_CLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9;
+ *  usb 480m to 25m divide number.
+ */
+#define LP_CLKRST_USB_48M_DIV_NUM    0x000000FFU
+#define LP_CLKRST_USB_48M_DIV_NUM_M  (LP_CLKRST_USB_48M_DIV_NUM_V << LP_CLKRST_USB_48M_DIV_NUM_S)
+#define LP_CLKRST_USB_48M_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_USB_48M_DIV_NUM_S  6
+/** LP_CLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19;
+ *  usb 500m to 25m divide number.
+ */
+#define LP_CLKRST_USB_25M_DIV_NUM    0x000000FFU
+#define LP_CLKRST_USB_25M_DIV_NUM_M  (LP_CLKRST_USB_25M_DIV_NUM_V << LP_CLKRST_USB_25M_DIV_NUM_S)
+#define LP_CLKRST_USB_25M_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_USB_25M_DIV_NUM_S  14
+/** LP_CLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39;
+ *  usb 480m to 12m divide number.
+ */
+#define LP_CLKRST_USB_12M_DIV_NUM    0x000000FFU
+#define LP_CLKRST_USB_12M_DIV_NUM_M  (LP_CLKRST_USB_12M_DIV_NUM_V << LP_CLKRST_USB_12M_DIV_NUM_S)
+#define LP_CLKRST_USB_12M_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_USB_12M_DIV_NUM_S  22
+
+/** LP_CLKRST_HP_USB_CLKRST_CTRL1_REG register
+ *  HP USB Clock Reset Control Register.
+ */
+#define LP_CLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x48)
+/** LP_CLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0;
+ *  usb otg20 adp reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP    (BIT(0))
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP_M  (LP_CLKRST_RST_EN_USB_OTG20_ADP_V << LP_CLKRST_RST_EN_USB_OTG20_ADP_S)
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP_S  0
+/** LP_CLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0;
+ *  usb otg20 phy reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY    (BIT(1))
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY_M  (LP_CLKRST_RST_EN_USB_OTG20_PHY_V << LP_CLKRST_RST_EN_USB_OTG20_PHY_S)
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY_S  1
+/** LP_CLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0;
+ *  usb otg20 reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG20    (BIT(2))
+#define LP_CLKRST_RST_EN_USB_OTG20_M  (LP_CLKRST_RST_EN_USB_OTG20_V << LP_CLKRST_RST_EN_USB_OTG20_S)
+#define LP_CLKRST_RST_EN_USB_OTG20_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG20_S  2
+/** LP_CLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0;
+ *  usb org11 reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG11    (BIT(3))
+#define LP_CLKRST_RST_EN_USB_OTG11_M  (LP_CLKRST_RST_EN_USB_OTG11_V << LP_CLKRST_RST_EN_USB_OTG11_S)
+#define LP_CLKRST_RST_EN_USB_OTG11_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG11_S  3
+/** LP_CLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0;
+ *  usb device reset en
+ */
+#define LP_CLKRST_RST_EN_USB_DEVICE    (BIT(4))
+#define LP_CLKRST_RST_EN_USB_DEVICE_M  (LP_CLKRST_RST_EN_USB_DEVICE_V << LP_CLKRST_RST_EN_USB_DEVICE_S)
+#define LP_CLKRST_RST_EN_USB_DEVICE_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_DEVICE_S  4
+/** LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0;
+ *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
+ */
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL    0x00000003U
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M  (LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S)
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V  0x00000003U
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S  28
+/** LP_CLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  usb otg20 hs phy refclk enable.
+ */
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN    (BIT(30))
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_M  (LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S)
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S  30
+/** LP_CLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  usb otg20 ulpi clock enable.
+ */
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN    (BIT(31))
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_M  (LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S)
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S  31
+
+/** LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x4c)
+/** LP_CLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0;
+ *  hp sdmmc reset en
+ */
+#define LP_CLKRST_RST_EN_SDMMC    (BIT(28))
+#define LP_CLKRST_RST_EN_SDMMC_M  (LP_CLKRST_RST_EN_SDMMC_V << LP_CLKRST_RST_EN_SDMMC_S)
+#define LP_CLKRST_RST_EN_SDMMC_V  0x00000001U
+#define LP_CLKRST_RST_EN_SDMMC_S  28
+/** LP_CLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0;
+ *  hp sdmmc force norst
+ */
+#define LP_CLKRST_FORCE_NORST_SDMMC    (BIT(29))
+#define LP_CLKRST_FORCE_NORST_SDMMC_M  (LP_CLKRST_FORCE_NORST_SDMMC_V << LP_CLKRST_FORCE_NORST_SDMMC_S)
+#define LP_CLKRST_FORCE_NORST_SDMMC_V  0x00000001U
+#define LP_CLKRST_FORCE_NORST_SDMMC_S  29
+/** LP_CLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0;
+ *  hp emac reset en
+ */
+#define LP_CLKRST_RST_EN_EMAC    (BIT(30))
+#define LP_CLKRST_RST_EN_EMAC_M  (LP_CLKRST_RST_EN_EMAC_V << LP_CLKRST_RST_EN_EMAC_S)
+#define LP_CLKRST_RST_EN_EMAC_V  0x00000001U
+#define LP_CLKRST_RST_EN_EMAC_S  30
+/** LP_CLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0;
+ *  hp emac force norst
+ */
+#define LP_CLKRST_FORCE_NORST_EMAC    (BIT(31))
+#define LP_CLKRST_FORCE_NORST_EMAC_M  (LP_CLKRST_FORCE_NORST_EMAC_V << LP_CLKRST_FORCE_NORST_EMAC_S)
+#define LP_CLKRST_FORCE_NORST_EMAC_V  0x00000001U
+#define LP_CLKRST_FORCE_NORST_EMAC_S  31
+
+/** LP_CLKRST_DATE_REG register
+ *  need_des
+ */
+#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
+/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_EN    (BIT(31))
+#define LP_CLKRST_CLK_EN_M  (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
+#define LP_CLKRST_CLK_EN_V  0x00000001U
+#define LP_CLKRST_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_clkrst_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_clkrst_struct.h
new file mode 100644
index 0000000000..49e42b840d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_clkrst_struct.h
@@ -0,0 +1,796 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of lp_clk_conf register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t slow_clk_sel:2;
+        /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
+         *  need_des
+         */
+        uint32_t fast_clk_sel:2;
+        /** lp_peri_div_num : R/W; bitpos: [9:4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_peri_div_num:6;
+        /** ana_sel_ref_pll8m : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_sel_ref_pll8m:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_aonclkrst_lp_clk_conf_reg_t;
+
+/** Type of lp_clk_po_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** clk_core_efuse_oen : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_core_efuse_oen:1;
+        /** clk_lp_bus_oen : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_lp_bus_oen:1;
+        /** clk_aon_slow_oen : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_aon_slow_oen:1;
+        /** clk_aon_fast_oen : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_aon_fast_oen:1;
+        /** clk_slow_oen : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_slow_oen:1;
+        /** clk_fast_oen : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_fast_oen:1;
+        /** clk_fosc_oen : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_fosc_oen:1;
+        /** clk_rc32k_oen : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_rc32k_oen:1;
+        /** clk_sxtal_oen : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_sxtal_oen:1;
+        /** clk_sosc_oen : R/W; bitpos: [9]; default: 0;
+         *  1'b1: probe sosc clk on
+         *  1'b0: probe sosc clk off
+         */
+        uint32_t clk_sosc_oen:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} lp_aonclkrst_lp_clk_po_en_reg_t;
+
+/** Type of lp_clk_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** lp_rtc_xtal_force_on : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_rtc_xtal_force_on:1;
+        /** ck_en_lp_ram : R/W; bitpos: [27]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_ram:1;
+        /** etm_event_tick_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t etm_event_tick_en:1;
+        /** pll8m_clk_force_on : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t pll8m_clk_force_on:1;
+        /** xtal_clk_force_on : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t xtal_clk_force_on:1;
+        /** fosc_clk_force_on : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t fosc_clk_force_on:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_lp_clk_en_reg_t;
+
+/** Type of lp_rst_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** rst_en_lp_huk : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_huk:1;
+        /** rst_en_lp_anaperi : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_anaperi:1;
+        /** rst_en_lp_wdt : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_wdt:1;
+        /** rst_en_lp_timer : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_timer:1;
+        /** rst_en_lp_rtc : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_rtc:1;
+        /** rst_en_lp_mailbox : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_mailbox:1;
+        /** rst_en_lp_aonefusereg : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_aonefusereg:1;
+        /** rst_en_lp_ram : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_ram:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_lp_rst_en_reg_t;
+
+/** Type of reset_cause register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lpcore_reset_cause : RO; bitpos: [5:0]; default: 0;
+         *  6'h1: POR reset
+         *  6'h9: PMU LP PERI power down reset
+         *  6'ha: PMU LP CPU reset
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: software reset
+         */
+        uint32_t lpcore_reset_cause:6;
+        /** lpcore_reset_flag : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_reset_flag:1;
+        /** hpcore0_reset_cause : RO; bitpos: [12:7]; default: 0;
+         *  6'h1: POR reset
+         *  6'h3: digital system software reset
+         *  6'h5: PMU HP system power down reset
+         *  6'h7: HP system reset from HP watchdog
+         *  6'h9: HP system reset from LP watchdog
+         *  6'hb: HP core reset from HP watchdog
+         *  6'hc: HP core software reset
+         *  6'hd: HP core reset from LP watchdog
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: efuse crc error reset
+         *  6'h16: HP usb jtag chip reset
+         *  6'h17: HP usb uart chip reset
+         *  6'h18: HP jtag reset
+         *  6'h1a: HP core lockup
+         */
+        uint32_t hpcore0_reset_cause:6;
+        /** hpcore0_reset_flag : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_flag:1;
+        /** hpcore1_reset_cause : RO; bitpos: [19:14]; default: 0;
+         *  6'h1: POR reset
+         *  6'h3: digital system software reset
+         *  6'h5: PMU HP system power down reset
+         *  6'h7: HP system reset from HP watchdog
+         *  6'h9: HP system reset from LP watchdog
+         *  6'hb: HP core reset from HP watchdog
+         *  6'hc: HP core software reset
+         *  6'hd: HP core reset from LP watchdog
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: efuse crc error reset
+         *  6'h16: HP usb jtag chip reset
+         *  6'h17: HP usb uart chip reset
+         *  6'h18: HP jtag reset
+         *  6'h1a: HP core lockup
+         */
+        uint32_t hpcore1_reset_cause:6;
+        /** hpcore1_reset_flag : RO; bitpos: [20]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_flag:1;
+        uint32_t reserved_21:4;
+        /** lpcore_reset_cause_pmu_lp_cpu_mask : R/W; bitpos: [25]; default: 1;
+         *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
+         *  pmu_lp_cpu_reset reset_cause
+         */
+        uint32_t lpcore_reset_cause_pmu_lp_cpu_mask:1;
+        /** lpcore_reset_cause_clr : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_reset_cause_clr:1;
+        /** lpcore_reset_flag_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_reset_flag_clr:1;
+        /** hpcore0_reset_cause_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_cause_clr:1;
+        /** hpcore0_reset_flag_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_flag_clr:1;
+        /** hpcore1_reset_cause_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_cause_clr:1;
+        /** hpcore1_reset_flag_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_flag_clr:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_reset_cause_reg_t;
+
+/** Type of hpcpu_reset_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpcore0_lockup_reset_en : R/W; bitpos: [0]; default: 0;
+         *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
+         *  reset feature
+         */
+        uint32_t hpcore0_lockup_reset_en:1;
+        /** lp_wdt_hpcore0_reset_length : R/W; bitpos: [3:1]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_wdt_hpcore0_reset_length:3;
+        /** lp_wdt_hpcore0_reset_en : R/W; bitpos: [4]; default: 0;
+         *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
+         *  hpcore0 feature
+         */
+        uint32_t lp_wdt_hpcore0_reset_en:1;
+        /** hpcore0_stall_wait : R/W; bitpos: [11:5]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_stall_wait:7;
+        /** hpcore0_stall_en : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_stall_en:1;
+        /** hpcore0_sw_reset : WT; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_sw_reset:1;
+        /** hpcore0_ocd_halt_on_reset : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_ocd_halt_on_reset:1;
+        /** hpcore0_stat_vector_sel : R/W; bitpos: [15]; default: 1;
+         *  1'b1: boot from HP TCM ROM: 0x4FC00000
+         *  1'b0: boot from LP TCM RAM:  0x50108000
+         */
+        uint32_t hpcore0_stat_vector_sel:1;
+        /** hpcore1_lockup_reset_en : R/W; bitpos: [16]; default: 0;
+         *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
+         *  reset feature
+         */
+        uint32_t hpcore1_lockup_reset_en:1;
+        /** lp_wdt_hpcore1_reset_length : R/W; bitpos: [19:17]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_wdt_hpcore1_reset_length:3;
+        /** lp_wdt_hpcore1_reset_en : R/W; bitpos: [20]; default: 0;
+         *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
+         *  hpcore1 feature
+         */
+        uint32_t lp_wdt_hpcore1_reset_en:1;
+        /** hpcore1_stall_wait : R/W; bitpos: [27:21]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_stall_wait:7;
+        /** hpcore1_stall_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_stall_en:1;
+        /** hpcore1_sw_reset : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_sw_reset:1;
+        /** hpcore1_ocd_halt_on_reset : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_ocd_halt_on_reset:1;
+        /** hpcore1_stat_vector_sel : R/W; bitpos: [31]; default: 1;
+         *  1'b1: boot from HP TCM ROM: 0x4FC00000
+         *  1'b0: boot from LP TCM RAM:  0x50108000
+         */
+        uint32_t hpcore1_stat_vector_sel:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_hpcpu_reset_ctrl0_reg_t;
+
+/** Type of hpcpu_reset_ctrl1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** hpcore0_sw_stall_code : R/W; bitpos: [23:16]; default: 0;
+         *  HP core0 software stall when set to 8'h86
+         */
+        uint32_t hpcore0_sw_stall_code:8;
+        /** hpcore1_sw_stall_code : R/W; bitpos: [31:24]; default: 0;
+         *  HP core1 software stall when set to 8'h86
+         */
+        uint32_t hpcore1_sw_stall_code:8;
+    };
+    uint32_t val;
+} lp_aonclkrst_hpcpu_reset_ctrl1_reg_t;
+
+/** Type of fosc_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 400;
+         *  need_des
+         */
+        uint32_t fosc_dfreq:10;
+    };
+    uint32_t val;
+} lp_aonclkrst_fosc_cntl_reg_t;
+
+/** Type of rc32k_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** rc32k_dfreq : R/W; bitpos: [31:0]; default: 650;
+         *  need_des
+         */
+        uint32_t rc32k_dfreq:32;
+    };
+    uint32_t val;
+} lp_aonclkrst_rc32k_cntl_reg_t;
+
+/** Type of sosc_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** sosc_dfreq : R/W; bitpos: [31:22]; default: 172;
+         *  need_des
+         */
+        uint32_t sosc_dfreq:10;
+    };
+    uint32_t val;
+} lp_aonclkrst_sosc_cntl_reg_t;
+
+/** Type of clk_to_hp register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_xtal32k:1;
+        /** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_sosc:1;
+        /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_osc32k:1;
+        /** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_fosc:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_clk_to_hp_reg_t;
+
+/** Type of lpmem_force register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t lpmem_clk_force_on:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_lpmem_force_reg_t;
+
+/** Type of xtal32k register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
+         *  need_des
+         */
+        uint32_t dres_xtal32k:3;
+        /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
+         *  need_des
+         */
+        uint32_t dgm_xtal32k:3;
+        /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t dbuf_xtal32k:1;
+        /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
+         *  need_des
+         */
+        uint32_t dac_xtal32k:3;
+    };
+    uint32_t val;
+} lp_aonclkrst_xtal32k_reg_t;
+
+/** Type of mux_hpsys_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** mux_hpsys_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t mux_hpsys_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_aonclkrst_mux_hpsys_reset_bypass_reg_t;
+
+/** Type of hpsys_0_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpsys_0_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t hpsys_0_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_aonclkrst_hpsys_0_reset_bypass_reg_t;
+
+/** Type of hpsys_apm_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpsys_apm_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t hpsys_apm_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_aonclkrst_hpsys_apm_reset_bypass_reg_t;
+
+/** Type of hp_clk_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        /** hp_root_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
+         */
+        uint32_t hp_root_clk_src_sel:2;
+        /** hp_root_clk_en : R/W; bitpos: [2]; default: 1;
+         *  HP SoC Root Clock Enable.
+         */
+        uint32_t hp_root_clk_en:1;
+        /** hp_pad_parlio_tx_clk_en : R/W; bitpos: [3]; default: 1;
+         *  PARLIO TX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_parlio_tx_clk_en:1;
+        /** hp_pad_parlio_rx_clk_en : R/W; bitpos: [4]; default: 1;
+         *  PARLIO RX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_parlio_rx_clk_en:1;
+        /** hp_pad_uart4_slp_clk_en : R/W; bitpos: [5]; default: 1;
+         *  UART4 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart4_slp_clk_en:1;
+        /** hp_pad_uart3_slp_clk_en : R/W; bitpos: [6]; default: 1;
+         *  UART3 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart3_slp_clk_en:1;
+        /** hp_pad_uart2_slp_clk_en : R/W; bitpos: [7]; default: 1;
+         *  UART2 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart2_slp_clk_en:1;
+        /** hp_pad_uart1_slp_clk_en : R/W; bitpos: [8]; default: 1;
+         *  UART1 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart1_slp_clk_en:1;
+        /** hp_pad_uart0_slp_clk_en : R/W; bitpos: [9]; default: 1;
+         *  UART0 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart0_slp_clk_en:1;
+        /** hp_pad_i2s2_mclk_en : R/W; bitpos: [10]; default: 1;
+         *  I2S2 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s2_mclk_en:1;
+        /** hp_pad_i2s1_mclk_en : R/W; bitpos: [11]; default: 1;
+         *  I2S1 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s1_mclk_en:1;
+        /** hp_pad_i2s0_mclk_en : R/W; bitpos: [12]; default: 1;
+         *  I2S0 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s0_mclk_en:1;
+        /** hp_pad_emac_tx_clk_en : R/W; bitpos: [13]; default: 1;
+         *  EMAC RX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_tx_clk_en:1;
+        /** hp_pad_emac_rx_clk_en : R/W; bitpos: [14]; default: 1;
+         *  EMAC TX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_rx_clk_en:1;
+        /** hp_pad_emac_txrx_clk_en : R/W; bitpos: [15]; default: 1;
+         *  EMAC TXRX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_txrx_clk_en:1;
+        /** hp_xtal_32k_clk_en : R/W; bitpos: [16]; default: 1;
+         *  XTAL 32K Clock Enable.
+         */
+        uint32_t hp_xtal_32k_clk_en:1;
+        /** hp_rc_32k_clk_en : R/W; bitpos: [17]; default: 1;
+         *  RC 32K Clock Enable.
+         */
+        uint32_t hp_rc_32k_clk_en:1;
+        /** hp_sosc_150k_clk_en : R/W; bitpos: [18]; default: 1;
+         *  SOSC 150K Clock Enable.
+         */
+        uint32_t hp_sosc_150k_clk_en:1;
+        /** hp_pll_8m_clk_en : R/W; bitpos: [19]; default: 1;
+         *  PLL 8M Clock Enable.
+         */
+        uint32_t hp_pll_8m_clk_en:1;
+        /** hp_audio_pll_clk_en : R/W; bitpos: [20]; default: 1;
+         *  AUDIO PLL Clock Enable.
+         */
+        uint32_t hp_audio_pll_clk_en:1;
+        /** hp_sdio_pll2_clk_en : R/W; bitpos: [21]; default: 1;
+         *  SDIO PLL2 Clock Enable.
+         */
+        uint32_t hp_sdio_pll2_clk_en:1;
+        /** hp_sdio_pll1_clk_en : R/W; bitpos: [22]; default: 1;
+         *  SDIO PLL1 Clock Enable.
+         */
+        uint32_t hp_sdio_pll1_clk_en:1;
+        /** hp_sdio_pll0_clk_en : R/W; bitpos: [23]; default: 1;
+         *  SDIO PLL0 Clock Enable.
+         */
+        uint32_t hp_sdio_pll0_clk_en:1;
+        /** hp_fosc_20m_clk_en : R/W; bitpos: [24]; default: 1;
+         *  FOSC 20M Clock Enable.
+         */
+        uint32_t hp_fosc_20m_clk_en:1;
+        /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1;
+         *  XTAL 40M Clock Enable.
+         */
+        uint32_t hp_xtal_40m_clk_en:1;
+        /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1;
+         *  CPLL 400M Clock Enable.
+         */
+        uint32_t hp_cpll_400m_clk_en:1;
+        /** hp_spll_480m_clk_en : R/W; bitpos: [27]; default: 1;
+         *  SPLL 480M Clock Enable.
+         */
+        uint32_t hp_spll_480m_clk_en:1;
+        /** hp_mpll_500m_clk_en : R/W; bitpos: [28]; default: 1;
+         *  MPLL 500M Clock Enable.
+         */
+        uint32_t hp_mpll_500m_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} lp_aonclkrst_hp_clk_ctrl_reg_t;
+
+/** Type of hp_usb_clkrst_ctrl0 register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        /** usb_otg20_sleep_mode : R/W; bitpos: [0]; default: 0;
+         *  unused.
+         */
+        uint32_t usb_otg20_sleep_mode:1;
+        /** usb_otg20_bk_sys_clk_en : R/W; bitpos: [1]; default: 1;
+         *  unused.
+         */
+        uint32_t usb_otg20_bk_sys_clk_en:1;
+        /** usb_otg11_sleep_mode : R/W; bitpos: [2]; default: 0;
+         *  unused.
+         */
+        uint32_t usb_otg11_sleep_mode:1;
+        /** usb_otg11_bk_sys_clk_en : R/W; bitpos: [3]; default: 1;
+         *  unused.
+         */
+        uint32_t usb_otg11_bk_sys_clk_en:1;
+        /** usb_otg11_48m_clk_en : R/W; bitpos: [4]; default: 1;
+         *  usb otg11 fs phy clock enable.
+         */
+        uint32_t usb_otg11_48m_clk_en:1;
+        /** usb_device_48m_clk_en : R/W; bitpos: [5]; default: 1;
+         *  usb device fs phy clock enable.
+         */
+        uint32_t usb_device_48m_clk_en:1;
+        /** usb_48m_div_num : R/W; bitpos: [13:6]; default: 9;
+         *  usb 480m to 25m divide number.
+         */
+        uint32_t usb_48m_div_num:8;
+        /** usb_25m_div_num : R/W; bitpos: [21:14]; default: 19;
+         *  usb 500m to 25m divide number.
+         */
+        uint32_t usb_25m_div_num:8;
+        /** usb_12m_div_num : R/W; bitpos: [29:22]; default: 39;
+         *  usb 480m to 12m divide number.
+         */
+        uint32_t usb_12m_div_num:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t;
+
+/** Type of hp_usb_clkrst_ctrl1 register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        /** rst_en_usb_otg20_adp : R/W; bitpos: [0]; default: 0;
+         *  usb otg20 adp reset en
+         */
+        uint32_t rst_en_usb_otg20_adp:1;
+        /** rst_en_usb_otg20_phy : R/W; bitpos: [1]; default: 0;
+         *  usb otg20 phy reset en
+         */
+        uint32_t rst_en_usb_otg20_phy:1;
+        /** rst_en_usb_otg20 : R/W; bitpos: [2]; default: 0;
+         *  usb otg20 reset en
+         */
+        uint32_t rst_en_usb_otg20:1;
+        /** rst_en_usb_otg11 : R/W; bitpos: [3]; default: 0;
+         *  usb org11 reset en
+         */
+        uint32_t rst_en_usb_otg11:1;
+        /** rst_en_usb_device : R/W; bitpos: [4]; default: 0;
+         *  usb device reset en
+         */
+        uint32_t rst_en_usb_device:1;
+        uint32_t reserved_5:23;
+        /** usb_otg20_phyref_clk_src_sel : R/W; bitpos: [29:28]; default: 0;
+         *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
+         */
+        uint32_t usb_otg20_phyref_clk_src_sel:2;
+        /** usb_otg20_phyref_clk_en : R/W; bitpos: [30]; default: 1;
+         *  usb otg20 hs phy refclk enable.
+         */
+        uint32_t usb_otg20_phyref_clk_en:1;
+        /** usb_otg20_ulpi_clk_en : R/W; bitpos: [31]; default: 1;
+         *  usb otg20 ulpi clock enable.
+         */
+        uint32_t usb_otg20_ulpi_clk_en:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t;
+
+/** Type of hp_sdmmc_emac_rst_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** rst_en_sdmmc : R/W; bitpos: [28]; default: 0;
+         *  hp sdmmc reset en
+         */
+        uint32_t rst_en_sdmmc:1;
+        /** force_norst_sdmmc : R/W; bitpos: [29]; default: 0;
+         *  hp sdmmc force norst
+         */
+        uint32_t force_norst_sdmmc:1;
+        /** rst_en_emac : R/W; bitpos: [30]; default: 0;
+         *  hp emac reset en
+         */
+        uint32_t rst_en_emac:1;
+        /** force_norst_emac : R/W; bitpos: [31]; default: 0;
+         *  hp emac force norst
+         */
+        uint32_t force_norst_emac:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_date_reg_t;
+
+
+typedef struct {
+    volatile lp_aonclkrst_lp_clk_conf_reg_t lp_clk_conf;
+    volatile lp_aonclkrst_lp_clk_po_en_reg_t lp_clk_po_en;
+    volatile lp_aonclkrst_lp_clk_en_reg_t lp_clk_en;
+    volatile lp_aonclkrst_lp_rst_en_reg_t lp_rst_en;
+    volatile lp_aonclkrst_reset_cause_reg_t reset_cause;
+    volatile lp_aonclkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0;
+    volatile lp_aonclkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1;
+    volatile lp_aonclkrst_fosc_cntl_reg_t fosc_cntl;
+    volatile lp_aonclkrst_rc32k_cntl_reg_t rc32k_cntl;
+    volatile lp_aonclkrst_sosc_cntl_reg_t sosc_cntl;
+    volatile lp_aonclkrst_clk_to_hp_reg_t clk_to_hp;
+    volatile lp_aonclkrst_lpmem_force_reg_t lpmem_force;
+    volatile lp_aonclkrst_xtal32k_reg_t xtal32k;
+    volatile lp_aonclkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass;
+    volatile lp_aonclkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass;
+    volatile lp_aonclkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass;
+    volatile lp_aonclkrst_hp_clk_ctrl_reg_t hp_clk_ctrl;
+    volatile lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0;
+    volatile lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1;
+    volatile lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl;
+    uint32_t reserved_050[235];
+    volatile lp_aonclkrst_date_reg_t date;
+} lp_aonclkrst_dev_t;
+
+extern lp_aonclkrst_dev_t LP_AON_CLKRST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_aonclkrst_dev_t) == 0x400, "Invalid size of lp_aonclkrst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_gpio_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_gpio_reg.h
new file mode 100644
index 0000000000..6e3da4f938
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_gpio_reg.h
@@ -0,0 +1,1593 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_GPIO_CLK_EN_REG register
+ *  Reserved
+ */
+#define LP_GPIO_CLK_EN_REG (DR_REG_LP_GPIO_BASE + 0x0)
+/** LP_GPIO_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define LP_GPIO_REG_CLK_EN    (BIT(0))
+#define LP_GPIO_REG_CLK_EN_M  (LP_GPIO_REG_CLK_EN_V << LP_GPIO_REG_CLK_EN_S)
+#define LP_GPIO_REG_CLK_EN_V  0x00000001U
+#define LP_GPIO_REG_CLK_EN_S  0
+
+/** LP_GPIO_VER_DATE_REG register
+ *  Reserved
+ */
+#define LP_GPIO_VER_DATE_REG (DR_REG_LP_GPIO_BASE + 0x4)
+/** LP_GPIO_REG_VER_DATE : R/W; bitpos: [27:0]; default: 2294563;
+ *  Reserved
+ */
+#define LP_GPIO_REG_VER_DATE    0x0FFFFFFFU
+#define LP_GPIO_REG_VER_DATE_M  (LP_GPIO_REG_VER_DATE_V << LP_GPIO_REG_VER_DATE_S)
+#define LP_GPIO_REG_VER_DATE_V  0x0FFFFFFFU
+#define LP_GPIO_REG_VER_DATE_S  0
+
+/** LP_GPIO_OUT_REG register
+ *  Reserved
+ */
+#define LP_GPIO_OUT_REG (DR_REG_LP_GPIO_BASE + 0x8)
+/** LP_GPIO_REG_GPIO_OUT_DATA : R/W/WTC; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_OUT_DATA    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_OUT_DATA_M  (LP_GPIO_REG_GPIO_OUT_DATA_V << LP_GPIO_REG_GPIO_OUT_DATA_S)
+#define LP_GPIO_REG_GPIO_OUT_DATA_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_OUT_DATA_S  0
+
+/** LP_GPIO_OUT_W1TS_REG register
+ *  Reserved
+ */
+#define LP_GPIO_OUT_W1TS_REG (DR_REG_LP_GPIO_BASE + 0xc)
+/** LP_GPIO_REG_GPIO_OUT_DATA_W1TS : WT; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_OUT_DATA_W1TS    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_OUT_DATA_W1TS_M  (LP_GPIO_REG_GPIO_OUT_DATA_W1TS_V << LP_GPIO_REG_GPIO_OUT_DATA_W1TS_S)
+#define LP_GPIO_REG_GPIO_OUT_DATA_W1TS_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_OUT_DATA_W1TS_S  0
+
+/** LP_GPIO_OUT_W1TC_REG register
+ *  Reserved
+ */
+#define LP_GPIO_OUT_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x10)
+/** LP_GPIO_REG_GPIO_OUT_DATA_W1TC : WT; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_OUT_DATA_W1TC    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_OUT_DATA_W1TC_M  (LP_GPIO_REG_GPIO_OUT_DATA_W1TC_V << LP_GPIO_REG_GPIO_OUT_DATA_W1TC_S)
+#define LP_GPIO_REG_GPIO_OUT_DATA_W1TC_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_OUT_DATA_W1TC_S  0
+
+/** LP_GPIO_ENABLE_REG register
+ *  Reserved
+ */
+#define LP_GPIO_ENABLE_REG (DR_REG_LP_GPIO_BASE + 0x14)
+/** LP_GPIO_REG_GPIO_ENABLE_DATA : R/W/WTC; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_ENABLE_DATA    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_M  (LP_GPIO_REG_GPIO_ENABLE_DATA_V << LP_GPIO_REG_GPIO_ENABLE_DATA_S)
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_S  0
+
+/** LP_GPIO_ENABLE_W1TS_REG register
+ *  Reserved
+ */
+#define LP_GPIO_ENABLE_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x18)
+/** LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS : WT; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS_M  (LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS_V << LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS_S)
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS_S  0
+
+/** LP_GPIO_ENABLE_W1TC_REG register
+ *  Reserved
+ */
+#define LP_GPIO_ENABLE_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x1c)
+/** LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC : WT; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC_M  (LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC_V << LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC_S)
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC_S  0
+
+/** LP_GPIO_STATUS_REG register
+ *  Reserved
+ */
+#define LP_GPIO_STATUS_REG (DR_REG_LP_GPIO_BASE + 0x20)
+/** LP_GPIO_REG_GPIO_STATUS_DATA : R/W/WTC; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_STATUS_DATA    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_STATUS_DATA_M  (LP_GPIO_REG_GPIO_STATUS_DATA_V << LP_GPIO_REG_GPIO_STATUS_DATA_S)
+#define LP_GPIO_REG_GPIO_STATUS_DATA_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_STATUS_DATA_S  0
+
+/** LP_GPIO_STATUS_W1TS_REG register
+ *  Reserved
+ */
+#define LP_GPIO_STATUS_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x24)
+/** LP_GPIO_REG_GPIO_STATUS_DATA_W1TS : WT; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TS    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TS_M  (LP_GPIO_REG_GPIO_STATUS_DATA_W1TS_V << LP_GPIO_REG_GPIO_STATUS_DATA_W1TS_S)
+#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TS_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TS_S  0
+
+/** LP_GPIO_STATUS_W1TC_REG register
+ *  Reserved
+ */
+#define LP_GPIO_STATUS_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x28)
+/** LP_GPIO_REG_GPIO_STATUS_DATA_W1TC : WT; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TC    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TC_M  (LP_GPIO_REG_GPIO_STATUS_DATA_W1TC_V << LP_GPIO_REG_GPIO_STATUS_DATA_W1TC_S)
+#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TC_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TC_S  0
+
+/** LP_GPIO_STATUS_NEXT_REG register
+ *  Reserved
+ */
+#define LP_GPIO_STATUS_NEXT_REG (DR_REG_LP_GPIO_BASE + 0x2c)
+/** LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT_M  (LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT_V << LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT_S)
+#define LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+/** LP_GPIO_IN_REG register
+ *  Reserved
+ */
+#define LP_GPIO_IN_REG (DR_REG_LP_GPIO_BASE + 0x30)
+/** LP_GPIO_REG_GPIO_IN_DATA_NEXT : RO; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_IN_DATA_NEXT    0x0000FFFFU
+#define LP_GPIO_REG_GPIO_IN_DATA_NEXT_M  (LP_GPIO_REG_GPIO_IN_DATA_NEXT_V << LP_GPIO_REG_GPIO_IN_DATA_NEXT_S)
+#define LP_GPIO_REG_GPIO_IN_DATA_NEXT_V  0x0000FFFFU
+#define LP_GPIO_REG_GPIO_IN_DATA_NEXT_S  0
+
+/** LP_GPIO_PIN0_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN0_REG (DR_REG_LP_GPIO_BASE + 0x34)
+/** LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN0_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN0_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN0_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN0_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN0_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN0_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN0_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN1_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN1_REG (DR_REG_LP_GPIO_BASE + 0x38)
+/** LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN1_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN1_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN1_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN1_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN1_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN1_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN1_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN2_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN2_REG (DR_REG_LP_GPIO_BASE + 0x3c)
+/** LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN2_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN2_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN2_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN2_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN2_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN2_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN2_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN3_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN3_REG (DR_REG_LP_GPIO_BASE + 0x40)
+/** LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN3_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN3_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN3_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN3_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN3_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN3_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN3_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN4_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN4_REG (DR_REG_LP_GPIO_BASE + 0x44)
+/** LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN4_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN4_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN4_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN4_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN4_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN4_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN4_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN5_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN5_REG (DR_REG_LP_GPIO_BASE + 0x48)
+/** LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN5_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN5_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN5_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN5_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN5_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN5_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN5_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN6_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN6_REG (DR_REG_LP_GPIO_BASE + 0x4c)
+/** LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN6_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN6_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN6_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN6_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN6_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN6_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN6_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN7_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN7_REG (DR_REG_LP_GPIO_BASE + 0x50)
+/** LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN7_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN7_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN7_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN7_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN7_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN7_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN7_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN8_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN8_REG (DR_REG_LP_GPIO_BASE + 0x54)
+/** LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN8_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN8_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN8_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN8_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN8_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN8_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN8_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN9_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN9_REG (DR_REG_LP_GPIO_BASE + 0x58)
+/** LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN9_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN9_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN9_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN9_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN9_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN9_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN9_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN10_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN10_REG (DR_REG_LP_GPIO_BASE + 0x5c)
+/** LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN10_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN10_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN10_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN10_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN10_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN10_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN10_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN11_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN11_REG (DR_REG_LP_GPIO_BASE + 0x60)
+/** LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN11_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN11_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN11_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN11_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN11_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN11_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN11_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN12_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN12_REG (DR_REG_LP_GPIO_BASE + 0x64)
+/** LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN12_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN12_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN12_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN12_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN12_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN12_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN12_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN13_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN13_REG (DR_REG_LP_GPIO_BASE + 0x68)
+/** LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN13_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN13_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN13_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN13_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN13_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN13_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN13_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN14_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN14_REG (DR_REG_LP_GPIO_BASE + 0x6c)
+/** LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN14_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN14_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN14_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN14_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN14_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN14_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN14_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_PIN15_REG register
+ *  Reserved
+ */
+#define LP_GPIO_PIN15_REG (DR_REG_LP_GPIO_BASE + 0x70)
+/** LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE    (BIT(0))
+#define LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE_M  (LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE_S)
+#define LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE_S  0
+/** LP_GPIO_REG_GPIO_PIN15_INT_TYPE : R/W; bitpos: [3:1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN15_INT_TYPE    0x00000007U
+#define LP_GPIO_REG_GPIO_PIN15_INT_TYPE_M  (LP_GPIO_REG_GPIO_PIN15_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN15_INT_TYPE_S)
+#define LP_GPIO_REG_GPIO_PIN15_INT_TYPE_V  0x00000007U
+#define LP_GPIO_REG_GPIO_PIN15_INT_TYPE_S  1
+/** LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER    (BIT(4))
+#define LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER_M  (LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER_S)
+#define LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER_V  0x00000001U
+#define LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER_S  4
+/** LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
+ *  need des
+ */
+#define LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR    (BIT(5))
+#define LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_M  (LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_S)
+#define LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_V  0x00000001U
+#define LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_S  5
+
+/** LP_GPIO_FUNC0_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x74)
+/** LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG0_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG0_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG0_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG0_IN_SEL_V << LP_GPIO_REG_GPIO_SIG0_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG0_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG0_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC0_IN_SEL : R/W; bitpos: [7:2]; default: 48;
+ *  reg_gpio_func0_in_sel[5:4]==2'b11->constant
+ *  1,reg_gpio_func0_in_sel[5:4]==2'b10->constant 0
+ */
+#define LP_GPIO_REG_GPIO_FUNC0_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC0_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC0_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC0_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC0_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC0_IN_SEL_S  2
+
+/** LP_GPIO_FUNC1_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x78)
+/** LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG1_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG1_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG1_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG1_IN_SEL_V << LP_GPIO_REG_GPIO_SIG1_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG1_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG1_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC1_IN_SEL : R/W; bitpos: [7:2]; default: 48;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC1_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC1_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC1_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC1_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC1_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC1_IN_SEL_S  2
+
+/** LP_GPIO_FUNC2_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x7c)
+/** LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG2_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG2_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG2_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG2_IN_SEL_V << LP_GPIO_REG_GPIO_SIG2_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG2_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG2_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC2_IN_SEL : R/W; bitpos: [7:2]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC2_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC2_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC2_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC2_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC2_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC2_IN_SEL_S  2
+
+/** LP_GPIO_FUNC3_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x80)
+/** LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG3_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG3_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG3_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG3_IN_SEL_V << LP_GPIO_REG_GPIO_SIG3_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG3_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG3_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC3_IN_SEL : R/W; bitpos: [7:2]; default: 48;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC3_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC3_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC3_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC3_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC3_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC3_IN_SEL_S  2
+
+/** LP_GPIO_FUNC4_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x84)
+/** LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG4_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG4_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG4_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG4_IN_SEL_V << LP_GPIO_REG_GPIO_SIG4_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG4_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG4_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC4_IN_SEL : R/W; bitpos: [7:2]; default: 48;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC4_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC4_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC4_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC4_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC4_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC4_IN_SEL_S  2
+
+/** LP_GPIO_FUNC5_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x88)
+/** LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG5_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG5_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG5_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG5_IN_SEL_V << LP_GPIO_REG_GPIO_SIG5_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG5_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG5_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC5_IN_SEL : R/W; bitpos: [7:2]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC5_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC5_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC5_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC5_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC5_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC5_IN_SEL_S  2
+
+/** LP_GPIO_FUNC6_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x8c)
+/** LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG6_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG6_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG6_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG6_IN_SEL_V << LP_GPIO_REG_GPIO_SIG6_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG6_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG6_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC6_IN_SEL : R/W; bitpos: [7:2]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC6_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC6_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC6_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC6_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC6_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC6_IN_SEL_S  2
+
+/** LP_GPIO_FUNC7_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x90)
+/** LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG7_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG7_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG7_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG7_IN_SEL_V << LP_GPIO_REG_GPIO_SIG7_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG7_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG7_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC7_IN_SEL : R/W; bitpos: [7:2]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC7_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC7_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC7_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC7_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC7_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC7_IN_SEL_S  2
+
+/** LP_GPIO_FUNC8_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x94)
+/** LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG8_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG8_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG8_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG8_IN_SEL_V << LP_GPIO_REG_GPIO_SIG8_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG8_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG8_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC8_IN_SEL : R/W; bitpos: [7:2]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC8_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC8_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC8_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC8_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC8_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC8_IN_SEL_S  2
+
+/** LP_GPIO_FUNC9_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x98)
+/** LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG9_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG9_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG9_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG9_IN_SEL_V << LP_GPIO_REG_GPIO_SIG9_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG9_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG9_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC9_IN_SEL : R/W; bitpos: [7:2]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC9_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC9_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC9_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC9_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC9_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC9_IN_SEL_S  2
+
+/** LP_GPIO_FUNC10_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x9c)
+/** LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG10_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG10_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG10_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG10_IN_SEL_V << LP_GPIO_REG_GPIO_SIG10_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG10_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG10_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC10_IN_SEL : R/W; bitpos: [7:2]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC10_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC10_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC10_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC10_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC10_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC10_IN_SEL_S  2
+
+/** LP_GPIO_FUNC11_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xa0)
+/** LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG11_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG11_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG11_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG11_IN_SEL_V << LP_GPIO_REG_GPIO_SIG11_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG11_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG11_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC11_IN_SEL : R/W; bitpos: [7:2]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC11_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC11_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC11_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC11_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC11_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC11_IN_SEL_S  2
+
+/** LP_GPIO_FUNC12_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xa4)
+/** LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG12_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG12_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG12_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG12_IN_SEL_V << LP_GPIO_REG_GPIO_SIG12_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG12_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG12_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC12_IN_SEL : R/W; bitpos: [7:2]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC12_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC12_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC12_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC12_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC12_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC12_IN_SEL_S  2
+
+/** LP_GPIO_FUNC13_IN_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xa8)
+/** LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_SIG13_IN_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_SIG13_IN_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_SIG13_IN_SEL_M  (LP_GPIO_REG_GPIO_SIG13_IN_SEL_V << LP_GPIO_REG_GPIO_SIG13_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_SIG13_IN_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_SIG13_IN_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC13_IN_SEL : R/W; bitpos: [7:2]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC13_IN_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC13_IN_SEL_M  (LP_GPIO_REG_GPIO_FUNC13_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC13_IN_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC13_IN_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC13_IN_SEL_S  2
+
+/** LP_GPIO_FUNC0_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xf4)
+/** LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC0_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC0_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC0_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC0_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC0_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC0_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC0_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC0_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  reg_gpio_func0_out_sel[5:1]==16 -> output gpio register value to pad
+ */
+#define LP_GPIO_REG_GPIO_FUNC0_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC0_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC0_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC0_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC0_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC0_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC1_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xf8)
+/** LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC1_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC1_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC1_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC1_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC1_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC1_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC1_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC1_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC1_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC1_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC1_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC1_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC1_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC1_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC2_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xfc)
+/** LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC2_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC2_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC2_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC2_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC2_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC2_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC2_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC2_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC2_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC2_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC2_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC2_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC2_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC2_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC3_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x100)
+/** LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC3_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC3_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC3_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC3_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC3_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC3_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC3_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC3_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC3_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC3_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC3_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC3_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC3_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC3_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC4_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x104)
+/** LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC4_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC4_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC4_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC4_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC4_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC4_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC4_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC4_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC4_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC4_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC4_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC4_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC4_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC4_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC5_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x108)
+/** LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC5_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC5_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC5_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC5_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC5_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC5_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC5_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC5_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC5_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC5_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC5_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC5_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC5_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC5_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC6_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x10c)
+/** LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC6_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC6_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC6_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC6_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC6_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC6_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC6_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC6_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC6_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC6_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC6_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC6_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC6_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC6_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC7_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x110)
+/** LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC7_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC7_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC7_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC7_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC7_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC7_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC7_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC7_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC7_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC7_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC7_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC7_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC7_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC7_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC8_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x114)
+/** LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC8_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC8_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC8_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC8_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC8_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC8_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC8_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC8_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC8_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC8_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC8_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC8_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC8_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC8_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC9_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x118)
+/** LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC9_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC9_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC9_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC9_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC9_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC9_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC9_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC9_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC9_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC9_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC9_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC9_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC9_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC9_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC10_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x11c)
+/** LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC10_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC10_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC10_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC10_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC10_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC10_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC10_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC10_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC10_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC10_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC10_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC10_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC10_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC10_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC11_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x120)
+/** LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC11_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC11_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC11_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC11_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC11_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC11_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC11_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC11_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC11_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC11_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC11_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC11_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC11_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC11_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC12_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x124)
+/** LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC12_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC12_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC12_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC12_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC12_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC12_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC12_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC12_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC12_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC12_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC12_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC12_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC12_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC12_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC13_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x128)
+/** LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC13_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC13_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC13_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC13_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC13_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC13_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC13_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC13_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC13_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC13_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC13_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC13_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC13_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC13_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC14_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x12c)
+/** LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC14_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC14_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC14_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC14_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC14_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC14_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC14_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC14_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC14_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC14_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC14_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC14_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC14_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC14_OUT_SEL_S  3
+
+/** LP_GPIO_FUNC15_OUT_SEL_CFG_REG register
+ *  Reserved
+ */
+#define LP_GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x130)
+/** LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL    (BIT(0))
+#define LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL_S  0
+/** LP_GPIO_REG_GPIO_FUNC15_OE_SEL : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC15_OE_SEL    (BIT(1))
+#define LP_GPIO_REG_GPIO_FUNC15_OE_SEL_M  (LP_GPIO_REG_GPIO_FUNC15_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC15_OE_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC15_OE_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC15_OE_SEL_S  1
+/** LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL    (BIT(2))
+#define LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL_M  (LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL_V  0x00000001U
+#define LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL_S  2
+/** LP_GPIO_REG_GPIO_FUNC15_OUT_SEL : R/W; bitpos: [8:3]; default: 32;
+ *  Reserved
+ */
+#define LP_GPIO_REG_GPIO_FUNC15_OUT_SEL    0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC15_OUT_SEL_M  (LP_GPIO_REG_GPIO_FUNC15_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC15_OUT_SEL_S)
+#define LP_GPIO_REG_GPIO_FUNC15_OUT_SEL_V  0x0000003FU
+#define LP_GPIO_REG_GPIO_FUNC15_OUT_SEL_S  3
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_gpio_sig_map.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_gpio_sig_map.h
new file mode 100644
index 0000000000..43e2e8043c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_gpio_sig_map.h
@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define LP_I2C_SCL_PAD_IN_IDX                   0
+#define LP_I2C_SCL_PAD_OUT_IDX                  0
+#define LP_I2C_SDA_PAD_IN_IDX                   1
+#define LP_I2C_SDA_PAD_OUT_IDX                  1
+#define LP_UART_RXD_PAD_IN_IDX                  2
+#define LP_UART_TXD_PAD_OUT_IDX                 2
+#define LP_UART_CTSN_PAD_IN_IDX                 3
+#define LP_UART_RTSN_PAD_OUT_IDX                3
+#define LP_UART_DSRN_PAD_IN_IDX                 4
+#define LP_UART_DTRN_PAD_OUT_IDX                4
+#define LP_SPI_CK_PAD_IN_IDX                    5
+#define LP_SPI_CK_PAD_OUT_IDX                   5
+#define LP_SPI_CS_PAD_IN_IDX                    6
+#define LP_SPI_CS_PAD_OUT_IDX                   6
+#define LP_SPI_D_PAD_IN_IDX                     7
+#define LP_SPI_D_PAD_OUT_IDX                    7
+#define LP_SPI_Q_PAD_IN_IDX                     8
+#define LP_SPI_Q_PAD_OUT_IDX                    8
+#define LP_I2S_I_BCK_PAD_IN_IDX                 9
+#define LP_I2S_I_BCK_PAD_OUT_IDX                9
+#define LP_I2S_I_SD_PAD_IN_IDX                  10
+#define LP_I2S_O_SD_PAD_OUT_IDX                 10
+#define LP_I2S_I_WS_PAD_IN_IDX                  11
+#define LP_I2S_I_WS_PAD_OUT_IDX                 11
+#define LP_I2S_O_BCK_PAD_IN_IDX                 12
+#define LP_I2S_O_BCK_PAD_OUT_IDX                12
+#define LP_I2S_O_WS_PAD_IN_IDX                  13
+#define LP_I2S_O_WS_PAD_OUT_IDX                 13
+#define LP_PROBE_TOP_OUT0_IDX                   14
+#define LP_PROBE_TOP_OUT1_IDX                   15
+#define LP_PROBE_TOP_OUT2_IDX                   16
+#define LP_PROBE_TOP_OUT3_IDX                   17
+#define LP_PROBE_TOP_OUT4_IDX                   18
+#define LP_PROBE_TOP_OUT5_IDX                   19
+#define LP_PROBE_TOP_OUT6_IDX                   20
+#define LP_PROBE_TOP_OUT7_IDX                   21
+#define LP_PROBE_TOP_OUT8_IDX                   22
+#define LP_PROBE_TOP_OUT9_IDX                   23
+#define LP_PROBE_TOP_OUT10_IDX                  24
+#define LP_PROBE_TOP_OUT11_IDX                  25
+#define LP_PROBE_TOP_OUT12_IDX                  26
+#define LP_PROBE_TOP_OUT13_IDX                  27
+#define LP_PROBE_TOP_OUT14_IDX                  28
+#define LP_PROBE_TOP_OUT15_IDX                  29
+#define PROBE_CHAIN_CLK_PAD_OUT_IDX             30
+// version date 230323
+#define SIG_GPIO_OUT_IDX                        128
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_gpio_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_gpio_struct.h
new file mode 100644
index 0000000000..b00dc46894
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_gpio_struct.h
@@ -0,0 +1,329 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_en */
+/** Type of clk_en register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_gpio_clk_en_reg_t;
+
+
+/** Group: ver_date */
+/** Type of ver_date register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [27:0]; default: 2294563;
+         *  Reserved
+         */
+        uint32_t reg_ver_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_gpio_ver_date_reg_t;
+
+
+/** Group: out */
+/** Type of out register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_out_data : R/W/WTC; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_out_data:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_out_reg_t;
+
+
+/** Group: out_w1ts */
+/** Type of out_w1ts register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_out_data_w1ts : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_out_data_w1ts:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_out_w1ts_reg_t;
+
+
+/** Group: out_w1tc */
+/** Type of out_w1tc register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_out_data_w1tc : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_out_data_w1tc:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_out_w1tc_reg_t;
+
+
+/** Group: enable */
+/** Type of enable register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_enable_data : R/W/WTC; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_enable_data:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_enable_reg_t;
+
+
+/** Group: enable_w1ts */
+/** Type of enable_w1ts register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_enable_data_w1ts : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_enable_data_w1ts:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_enable_w1ts_reg_t;
+
+
+/** Group: enable_w1tc */
+/** Type of enable_w1tc register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_enable_data_w1tc : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_enable_data_w1tc:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_enable_w1tc_reg_t;
+
+
+/** Group: status */
+/** Type of status register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_status_data : R/W/WTC; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_status_data:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_status_reg_t;
+
+
+/** Group: status_w1ts */
+/** Type of status_w1ts register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_status_data_w1ts : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_status_data_w1ts:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_status_w1ts_reg_t;
+
+
+/** Group: status_w1tc */
+/** Type of status_w1tc register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_status_data_w1tc : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_status_data_w1tc:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_status_w1tc_reg_t;
+
+
+/** Group: in */
+/** Type of status_next register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_status_interrupt_next : RO; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_status_interrupt_next:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_status_next_reg_t;
+
+/** Type of in register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_in_data_next : RO; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_in_data_next:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_in_reg_t;
+
+
+/** Group: pin */
+/** Type of pin register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** wakeup_enable : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t wakeup_enable:1;
+        /** int_type : R/W; bitpos: [3:1]; default: 0;
+         *  Reserved
+         */
+        uint32_t int_type:3;
+        /** pad_driver : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t pad_driver:1;
+        /** edge_wakeup_clr : WT; bitpos: [5]; default: 0;
+         *  need des
+         */
+        uint32_t edge_wakeup_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} lp_gpio_pin_reg_t;
+
+
+/** Group: func_in_sel_cfg */
+/** Type of func_in_sel_cfg register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** in_inv_sel : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t in_inv_sel:1;
+        /** sig_in_sel : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t sig_in_sel:1;
+        /** func_in_sel : R/W; bitpos: [7:2]; default: 48 (for func0/1/3/4) 32 (for the rest);
+         *  func_in_sel[5:4]==2'b11 (s=0x30) -> constant 1
+         *  func_in_sel[5:4]==2'b10 (s=0x20) -> constant 0
+         */
+        uint32_t func_in_sel:6;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_gpio_func_in_sel_cfg_reg_t;
+
+
+/** Group: func_out_sel_cfg */
+/** Type of func0_out_sel_cfg register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** oe_inv_sel : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t oe_inv_sel:1;
+        /** oe_sel : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t oe_sel:1;
+        /** out_inv_sel : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t out_inv_sel:1;
+        /** func_out_sel : R/W; bitpos: [8:3]; default: 32;
+         *  func_out_sel[5:1]==16 (s=32) -> output gpio register value to pad
+         */
+        uint32_t func_out_sel:6;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} lp_gpio_func_out_sel_cfg_reg_t;
+
+
+typedef struct lp_gpio_dev_t {
+    volatile lp_gpio_clk_en_reg_t clk_en;
+    volatile lp_gpio_ver_date_reg_t ver_date;
+    volatile lp_gpio_out_reg_t out;
+    volatile lp_gpio_out_w1ts_reg_t out_w1ts;
+    volatile lp_gpio_out_w1tc_reg_t out_w1tc;
+    volatile lp_gpio_enable_reg_t enable;
+    volatile lp_gpio_enable_w1ts_reg_t enable_w1ts;
+    volatile lp_gpio_enable_w1tc_reg_t enable_w1tc;
+    volatile lp_gpio_status_reg_t status;
+    volatile lp_gpio_status_w1ts_reg_t status_w1ts;
+    volatile lp_gpio_status_w1tc_reg_t status_w1tc;
+    volatile lp_gpio_status_next_reg_t status_next;
+    volatile lp_gpio_in_reg_t in;
+    volatile lp_gpio_pin_reg_t pin[16];
+    volatile lp_gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[14];
+    uint32_t reserved_0ac[18];
+    volatile lp_gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[16];
+} lp_gpio_dev_t;
+
+extern lp_gpio_dev_t LP_GPIO;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_gpio_dev_t) == 0x134, "Invalid size of lp_gpio_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h
new file mode 100644
index 0000000000..e7b75d50a4
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h
@@ -0,0 +1,1194 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2C_SCL_LOW_PERIOD_REG register
+ *  Configures the low level width of the SCL
+ *  Clock
+ */
+#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
+/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure for how long SCL remains low in master mode, in
+ *  I2C module clock cycles.
+ */
+#define I2C_SCL_LOW_PERIOD    0x000001FFU
+#define I2C_SCL_LOW_PERIOD_M  (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
+#define I2C_SCL_LOW_PERIOD_V  0x000001FFU
+#define I2C_SCL_LOW_PERIOD_S  0
+
+/** I2C_CTR_REG register
+ *  Transmission setting
+ */
+#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
+/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
+ *  This register is used to select the sample mode.1: sample SDA data on the SCL low
+ *  level.0: sample SDA data on the SCL high level.
+ */
+#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
+#define I2C_SAMPLE_SCL_LEVEL_V  0x00000001U
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
+ *  This register is used to configure the ACK value that need to sent by master when
+ *  the rx_fifo_cnt has reached the threshold.
+ */
+#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_M  (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
+#define I2C_RX_FULL_ACK_LEVEL_V  0x00000001U
+#define I2C_RX_FULL_ACK_LEVEL_S  3
+/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
+ *  Set this bit to start sending the data in txfifo.
+ */
+#define I2C_TRANS_START    (BIT(5))
+#define I2C_TRANS_START_M  (I2C_TRANS_START_V << I2C_TRANS_START_S)
+#define I2C_TRANS_START_V  0x00000001U
+#define I2C_TRANS_START_S  5
+/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
+ *  This bit is used to control the sending mode for data needing to be sent. 1: send
+ *  data from the least significant bit,0: send data from the most significant bit.
+ */
+#define I2C_TX_LSB_FIRST    (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
+#define I2C_TX_LSB_FIRST_V  0x00000001U
+#define I2C_TX_LSB_FIRST_S  6
+/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
+ *  This bit is used to control the storage mode for received data.1: receive data from
+ *  the least significant bit,0: receive data from the most significant bit.
+ */
+#define I2C_RX_LSB_FIRST    (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
+#define I2C_RX_LSB_FIRST_V  0x00000001U
+#define I2C_RX_LSB_FIRST_S  7
+/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define I2C_CLK_EN    (BIT(8))
+#define I2C_CLK_EN_M  (I2C_CLK_EN_V << I2C_CLK_EN_S)
+#define I2C_CLK_EN_V  0x00000001U
+#define I2C_CLK_EN_S  8
+/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
+ *  This is the enable bit for arbitration_lost.
+ */
+#define I2C_ARBITRATION_EN    (BIT(9))
+#define I2C_ARBITRATION_EN_M  (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
+#define I2C_ARBITRATION_EN_V  0x00000001U
+#define I2C_ARBITRATION_EN_S  9
+/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
+ *  This register is used to reset the scl FMS.
+ */
+#define I2C_FSM_RST    (BIT(10))
+#define I2C_FSM_RST_M  (I2C_FSM_RST_V << I2C_FSM_RST_S)
+#define I2C_FSM_RST_V  0x00000001U
+#define I2C_FSM_RST_S  10
+/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
+ *  synchronization bit
+ */
+#define I2C_CONF_UPGATE    (BIT(11))
+#define I2C_CONF_UPGATE_M  (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S)
+#define I2C_CONF_UPGATE_V  0x00000001U
+#define I2C_CONF_UPGATE_S  11
+
+/** I2C_SR_REG register
+ *  Describe I2C work status.
+ */
+#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
+/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
+ *  The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.
+ */
+#define I2C_RESP_REC    (BIT(0))
+#define I2C_RESP_REC_M  (I2C_RESP_REC_V << I2C_RESP_REC_S)
+#define I2C_RESP_REC_V  0x00000001U
+#define I2C_RESP_REC_S  0
+/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
+ *  When the I2C controller loses control of SCL line, this register changes to 1.
+ */
+#define I2C_ARB_LOST    (BIT(3))
+#define I2C_ARB_LOST_M  (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
+#define I2C_ARB_LOST_V  0x00000001U
+#define I2C_ARB_LOST_S  3
+/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
+ *  1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state.
+ */
+#define I2C_BUS_BUSY    (BIT(4))
+#define I2C_BUS_BUSY_M  (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
+#define I2C_BUS_BUSY_V  0x00000001U
+#define I2C_BUS_BUSY_S  4
+/** I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0;
+ *  This field represents the amount of data needed to be sent.
+ */
+#define I2C_RXFIFO_CNT    0x0000001FU
+#define I2C_RXFIFO_CNT_M  (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S)
+#define I2C_RXFIFO_CNT_V  0x0000001FU
+#define I2C_RXFIFO_CNT_S  8
+/** I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0;
+ *  This field stores the amount of received data in RAM.
+ */
+#define I2C_TXFIFO_CNT    0x0000001FU
+#define I2C_TXFIFO_CNT_M  (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S)
+#define I2C_TXFIFO_CNT_V  0x0000001FU
+#define I2C_TXFIFO_CNT_S  18
+/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
+ *  This field indicates the states of the I2C module state machine. 0: Idle, 1:
+ *  Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK
+ */
+#define I2C_SCL_MAIN_STATE_LAST    0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_M  (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S)
+#define I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
+ *  This field indicates the states of the state machine used to produce SCL.0: Idle,
+ *  1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop
+ */
+#define I2C_SCL_STATE_LAST    0x00000007U
+#define I2C_SCL_STATE_LAST_M  (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S)
+#define I2C_SCL_STATE_LAST_V  0x00000007U
+#define I2C_SCL_STATE_LAST_S  28
+
+/** I2C_TO_REG register
+ *  Setting time out control for receiving data.
+ */
+#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
+/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
+ *  This register is used to configure the timeout for receiving a data bit in APBclock
+ *  cycles.
+ */
+#define I2C_TIME_OUT_VALUE    0x0000001FU
+#define I2C_TIME_OUT_VALUE_M  (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
+#define I2C_TIME_OUT_VALUE_V  0x0000001FU
+#define I2C_TIME_OUT_VALUE_S  0
+/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for time out control.
+ */
+#define I2C_TIME_OUT_EN    (BIT(5))
+#define I2C_TIME_OUT_EN_M  (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
+#define I2C_TIME_OUT_EN_V  0x00000001U
+#define I2C_TIME_OUT_EN_S  5
+
+/** I2C_FIFO_ST_REG register
+ *  FIFO status register.
+ */
+#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
+/** I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0;
+ *  This is the offset address of the APB reading from rxfifo
+ */
+#define I2C_RXFIFO_RADDR    0x0000000FU
+#define I2C_RXFIFO_RADDR_M  (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S)
+#define I2C_RXFIFO_RADDR_V  0x0000000FU
+#define I2C_RXFIFO_RADDR_S  0
+/** I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0;
+ *  This is the offset address of i2c module receiving data and writing to rxfifo.
+ */
+#define I2C_RXFIFO_WADDR    0x0000000FU
+#define I2C_RXFIFO_WADDR_M  (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S)
+#define I2C_RXFIFO_WADDR_V  0x0000000FU
+#define I2C_RXFIFO_WADDR_S  5
+/** I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0;
+ *  This is the offset address of i2c module reading from txfifo.
+ */
+#define I2C_TXFIFO_RADDR    0x0000000FU
+#define I2C_TXFIFO_RADDR_M  (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S)
+#define I2C_TXFIFO_RADDR_V  0x0000000FU
+#define I2C_TXFIFO_RADDR_S  10
+/** I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0;
+ *  This is the offset address of APB bus writing to txfifo.
+ */
+#define I2C_TXFIFO_WADDR    0x0000000FU
+#define I2C_TXFIFO_WADDR_M  (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S)
+#define I2C_TXFIFO_WADDR_V  0x0000000FU
+#define I2C_TXFIFO_WADDR_S  15
+
+/** I2C_FIFO_CONF_REG register
+ *  FIFO configuration register.
+ */
+#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
+/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6;
+ *  The water mark threshold of rx FIFO in nonfifo access mode. When
+ *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
+ *  reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.
+ */
+#define I2C_RXFIFO_WM_THRHD    0x0000000FU
+#define I2C_RXFIFO_WM_THRHD_M  (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S)
+#define I2C_RXFIFO_WM_THRHD_V  0x0000000FU
+#define I2C_RXFIFO_WM_THRHD_S  0
+/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2;
+ *  The water mark threshold of tx FIFO in nonfifo access mode. When
+ *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
+ *  reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.
+ */
+#define I2C_TXFIFO_WM_THRHD    0x0000000FU
+#define I2C_TXFIFO_WM_THRHD_M  (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S)
+#define I2C_TXFIFO_WM_THRHD_V  0x0000000FU
+#define I2C_TXFIFO_WM_THRHD_S  5
+/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to enable APB nonfifo access.
+ */
+#define I2C_NONFIFO_EN    (BIT(10))
+#define I2C_NONFIFO_EN_M  (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S)
+#define I2C_NONFIFO_EN_V  0x00000001U
+#define I2C_NONFIFO_EN_S  10
+/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to reset rx-fifo.
+ */
+#define I2C_RX_FIFO_RST    (BIT(12))
+#define I2C_RX_FIFO_RST_M  (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S)
+#define I2C_RX_FIFO_RST_V  0x00000001U
+#define I2C_RX_FIFO_RST_S  12
+/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to reset tx-fifo.
+ */
+#define I2C_TX_FIFO_RST    (BIT(13))
+#define I2C_TX_FIFO_RST_M  (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S)
+#define I2C_TX_FIFO_RST_V  0x00000001U
+#define I2C_TX_FIFO_RST_S  13
+/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
+ *  The control enable bit of FIFO pointer in non-fifo access mode. This bit controls
+ *  the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
+ */
+#define I2C_FIFO_PRT_EN    (BIT(14))
+#define I2C_FIFO_PRT_EN_M  (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
+#define I2C_FIFO_PRT_EN_V  0x00000001U
+#define I2C_FIFO_PRT_EN_S  14
+
+/** I2C_DATA_REG register
+ *  Rx FIFO read data.
+ */
+#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
+/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0;
+ *  The value of rx FIFO read data.
+ */
+#define I2C_FIFO_RDATA    0x000000FFU
+#define I2C_FIFO_RDATA_M  (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S)
+#define I2C_FIFO_RDATA_V  0x000000FFU
+#define I2C_FIFO_RDATA_S  0
+
+/** I2C_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
+/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_M  (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S)
+#define I2C_RXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_RAW_S  0
+/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
+ *  The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_M  (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S)
+#define I2C_TXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_RAW_S  1
+/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S)
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_RAW    (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S)
+#define I2C_END_DETECT_INT_RAW_V  0x00000001U
+#define I2C_END_DETECT_INT_RAW_S  3
+/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S)
+#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
+/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S)
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S)
+#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
+/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
+ *  The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S)
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
+ *  The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_RAW    (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S)
+#define I2C_TIME_OUT_INT_RAW_V  0x00000001U
+#define I2C_TIME_OUT_INT_RAW_S  8
+/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
+ *  The raw interrupt bit for the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_RAW    (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S)
+#define I2C_TRANS_START_INT_RAW_V  0x00000001U
+#define I2C_TRANS_START_INT_RAW_S  9
+/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
+ *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_RAW    (BIT(10))
+#define I2C_NACK_INT_RAW_M  (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S)
+#define I2C_NACK_INT_RAW_V  0x00000001U
+#define I2C_NACK_INT_RAW_S  10
+/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
+ *  The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_M  (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S)
+#define I2C_TXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_RAW_S  11
+/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
+ *  The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_M  (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S)
+#define I2C_RXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_RAW_S  12
+/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
+ *  The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S)
+#define I2C_SCL_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
+ *  The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S)
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
+ *  The raw interrupt bit for I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_RAW    (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S)
+#define I2C_DET_START_INT_RAW_V  0x00000001U
+#define I2C_DET_START_INT_RAW_S  15
+
+/** I2C_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
+/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_M  (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S)
+#define I2C_RXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_CLR_S  0
+/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_M  (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S)
+#define I2C_TXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_CLR_S  1
+/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S)
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_CLR    (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S)
+#define I2C_END_DETECT_INT_CLR_V  0x00000001U
+#define I2C_END_DETECT_INT_CLR_S  3
+/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S)
+#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
+/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S)
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S)
+#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
+/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S)
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_CLR    (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S)
+#define I2C_TIME_OUT_INT_CLR_V  0x00000001U
+#define I2C_TIME_OUT_INT_CLR_S  8
+/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_CLR    (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S)
+#define I2C_TRANS_START_INT_CLR_V  0x00000001U
+#define I2C_TRANS_START_INT_CLR_S  9
+/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_CLR    (BIT(10))
+#define I2C_NACK_INT_CLR_M  (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S)
+#define I2C_NACK_INT_CLR_V  0x00000001U
+#define I2C_NACK_INT_CLR_S  10
+/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_M  (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S)
+#define I2C_TXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_CLR_S  11
+/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_M  (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S)
+#define I2C_RXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_CLR_S  12
+/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S)
+#define I2C_SCL_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S)
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_CLR    (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S)
+#define I2C_DET_START_INT_CLR_V  0x00000001U
+#define I2C_DET_START_INT_CLR_S  15
+
+/** I2C_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
+/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_M  (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S)
+#define I2C_RXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ENA_S  0
+/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_M  (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S)
+#define I2C_TXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ENA_S  1
+/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S)
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ENA    (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S)
+#define I2C_END_DETECT_INT_ENA_V  0x00000001U
+#define I2C_END_DETECT_INT_ENA_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S)
+#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
+/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S)
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S)
+#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
+/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S)
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ENA    (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S)
+#define I2C_TIME_OUT_INT_ENA_V  0x00000001U
+#define I2C_TIME_OUT_INT_ENA_S  8
+/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ENA    (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S)
+#define I2C_TRANS_START_INT_ENA_V  0x00000001U
+#define I2C_TRANS_START_INT_ENA_S  9
+/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ENA    (BIT(10))
+#define I2C_NACK_INT_ENA_M  (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S)
+#define I2C_NACK_INT_ENA_V  0x00000001U
+#define I2C_NACK_INT_ENA_S  10
+/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_M  (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S)
+#define I2C_TXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ENA_S  11
+/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_M  (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S)
+#define I2C_RXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ENA_S  12
+/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S)
+#define I2C_SCL_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ENA    (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S)
+#define I2C_DET_START_INT_ENA_V  0x00000001U
+#define I2C_DET_START_INT_ENA_S  15
+
+/** I2C_INT_STATUS_REG register
+ *  Status of captured I2C communication events
+ */
+#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
+/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_M  (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S)
+#define I2C_RXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ST_S  0
+/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_M  (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S)
+#define I2C_TXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ST_S  1
+/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S)
+#define I2C_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ST    (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S)
+#define I2C_END_DETECT_INT_ST_V  0x00000001U
+#define I2C_END_DETECT_INT_ST_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_M  (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S)
+#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
+/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S)
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_M  (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S)
+#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
+/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S)
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ST    (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S)
+#define I2C_TIME_OUT_INT_ST_V  0x00000001U
+#define I2C_TIME_OUT_INT_ST_S  8
+/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ST    (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S)
+#define I2C_TRANS_START_INT_ST_V  0x00000001U
+#define I2C_TRANS_START_INT_ST_S  9
+/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ST    (BIT(10))
+#define I2C_NACK_INT_ST_M  (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S)
+#define I2C_NACK_INT_ST_V  0x00000001U
+#define I2C_NACK_INT_ST_S  10
+/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_M  (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S)
+#define I2C_TXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ST_S  11
+/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_M  (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S)
+#define I2C_RXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ST_S  12
+/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S)
+#define I2C_SCL_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ST_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked interrupt status bit for I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ST    (BIT(15))
+#define I2C_DET_START_INT_ST_M  (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S)
+#define I2C_DET_START_INT_ST_V  0x00000001U
+#define I2C_DET_START_INT_ST_S  15
+
+/** I2C_SDA_HOLD_REG register
+ *  Configures the hold time after a negative SCL edge.
+ */
+#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
+/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure the time to hold the data after the negativeedge
+ *  of SCL, in I2C module clock cycles.
+ */
+#define I2C_SDA_HOLD_TIME    0x000001FFU
+#define I2C_SDA_HOLD_TIME_M  (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
+#define I2C_SDA_HOLD_TIME_V  0x000001FFU
+#define I2C_SDA_HOLD_TIME_S  0
+
+/** I2C_SDA_SAMPLE_REG register
+ *  Configures the sample time after a positive SCL edge.
+ */
+#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
+/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure for how long SDA is sampled, in I2C module clock
+ *  cycles.
+ */
+#define I2C_SDA_SAMPLE_TIME    0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_M  (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
+#define I2C_SDA_SAMPLE_TIME_V  0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+/** I2C_SCL_HIGH_PERIOD_REG register
+ *  Configures the high level width of SCL
+ */
+#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
+/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure for how long SCL setup to high level and remains
+ *  high in master mode, in I2C module clock cycles.
+ */
+#define I2C_SCL_HIGH_PERIOD    0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_M  (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
+#define I2C_SCL_HIGH_PERIOD_V  0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_S  0
+/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
+ *  This register is used to configure for the SCL_FSM's waiting period for SCL high
+ *  level in master mode, in I2C module clock cycles.
+ */
+#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_M  (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
+#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
+
+/** I2C_SCL_START_HOLD_REG register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
+/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the negative edgeof SDA and the
+ *  negative edge of SCL for a START condition, in I2C module clock cycles.
+ */
+#define I2C_SCL_START_HOLD_TIME    0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_M  (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
+#define I2C_SCL_START_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+/** I2C_SCL_RSTART_SETUP_REG register
+ *  Configures the delay between the positive
+ *  edge of SCL and the negative edge of SDA
+ */
+#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
+/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the positiveedge of SCL and the
+ *  negative edge of SDA for a RESTART condition, in I2C module clock cycles.
+ */
+#define I2C_SCL_RSTART_SETUP_TIME    0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_M  (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+/** I2C_SCL_STOP_HOLD_REG register
+ *  Configures the delay after the SCL clock
+ *  edge for a stop condition
+ */
+#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
+/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the delay after the STOP condition,in I2C module
+ *  clock cycles.
+ */
+#define I2C_SCL_STOP_HOLD_TIME    0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_M  (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
+#define I2C_SCL_STOP_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+/** I2C_SCL_STOP_SETUP_REG register
+ *  Configures the delay between the SDA and
+ *  SCL positive edge for a stop condition
+ */
+#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
+/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the positive edgeof SCL and the
+ *  positive edge of SDA, in I2C module clock cycles.
+ */
+#define I2C_SCL_STOP_SETUP_TIME    0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_M  (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S)
+#define I2C_SCL_STOP_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+/** I2C_FILTER_CFG_REG register
+ *  SCL and SDA filter configuration register
+ */
+#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
+/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
+ *  When a pulse on the SCL input has smaller width than this register valuein I2C
+ *  module clock cycles, the I2C controller will ignore that pulse.
+ */
+#define I2C_SCL_FILTER_THRES    0x0000000FU
+#define I2C_SCL_FILTER_THRES_M  (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
+#define I2C_SCL_FILTER_THRES_V  0x0000000FU
+#define I2C_SCL_FILTER_THRES_S  0
+/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
+ *  When a pulse on the SDA input has smaller width than this register valuein I2C
+ *  module clock cycles, the I2C controller will ignore that pulse.
+ */
+#define I2C_SDA_FILTER_THRES    0x0000000FU
+#define I2C_SDA_FILTER_THRES_M  (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
+#define I2C_SDA_FILTER_THRES_V  0x0000000FU
+#define I2C_SDA_FILTER_THRES_S  4
+/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
+ *  This is the filter enable bit for SCL.
+ */
+#define I2C_SCL_FILTER_EN    (BIT(8))
+#define I2C_SCL_FILTER_EN_M  (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
+#define I2C_SCL_FILTER_EN_V  0x00000001U
+#define I2C_SCL_FILTER_EN_S  8
+/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
+ *  This is the filter enable bit for SDA.
+ */
+#define I2C_SDA_FILTER_EN    (BIT(9))
+#define I2C_SDA_FILTER_EN_M  (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
+#define I2C_SDA_FILTER_EN_V  0x00000001U
+#define I2C_SDA_FILTER_EN_S  9
+
+/** I2C_CLK_CONF_REG register
+ *  I2C CLK configuration register
+ */
+#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54)
+/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  the integral part of the fractional divisor for i2c module
+ */
+#define I2C_SCLK_DIV_NUM    0x000000FFU
+#define I2C_SCLK_DIV_NUM_M  (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S)
+#define I2C_SCLK_DIV_NUM_V  0x000000FFU
+#define I2C_SCLK_DIV_NUM_S  0
+/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0;
+ *  the numerator of the fractional part of the fractional divisor for i2c module
+ */
+#define I2C_SCLK_DIV_A    0x0000003FU
+#define I2C_SCLK_DIV_A_M  (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S)
+#define I2C_SCLK_DIV_A_V  0x0000003FU
+#define I2C_SCLK_DIV_A_S  8
+/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0;
+ *  the denominator of the fractional part of the fractional divisor for i2c module
+ */
+#define I2C_SCLK_DIV_B    0x0000003FU
+#define I2C_SCLK_DIV_B_M  (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S)
+#define I2C_SCLK_DIV_B_V  0x0000003FU
+#define I2C_SCLK_DIV_B_S  14
+/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  The clock selection for i2c module:0-XTAL,1-CLK_8MHz.
+ */
+#define I2C_SCLK_SEL    (BIT(20))
+#define I2C_SCLK_SEL_M  (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S)
+#define I2C_SCLK_SEL_V  0x00000001U
+#define I2C_SCLK_SEL_S  20
+/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1;
+ *  The clock switch for i2c module
+ */
+#define I2C_SCLK_ACTIVE    (BIT(21))
+#define I2C_SCLK_ACTIVE_M  (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S)
+#define I2C_SCLK_ACTIVE_V  0x00000001U
+#define I2C_SCLK_ACTIVE_S  21
+
+/** I2C_COMD0_REG register
+ *  I2C command register 0
+ */
+#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
+/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 0. It consists of three parts: op_code is the
+ *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+ *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+ *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+ */
+#define I2C_COMMAND0    0x00003FFFU
+#define I2C_COMMAND0_M  (I2C_COMMAND0_V << I2C_COMMAND0_S)
+#define I2C_COMMAND0_V  0x00003FFFU
+#define I2C_COMMAND0_S  0
+/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 0 is done in I2C Master mode, this bit changes to highlevel.
+ */
+#define I2C_COMMAND0_DONE    (BIT(31))
+#define I2C_COMMAND0_DONE_M  (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
+#define I2C_COMMAND0_DONE_V  0x00000001U
+#define I2C_COMMAND0_DONE_S  31
+
+/** I2C_COMD1_REG register
+ *  I2C command register 1
+ */
+#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
+/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 1. It consists of three parts: op_code is the
+ *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+ *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+ *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+ */
+#define I2C_COMMAND1    0x00003FFFU
+#define I2C_COMMAND1_M  (I2C_COMMAND1_V << I2C_COMMAND1_S)
+#define I2C_COMMAND1_V  0x00003FFFU
+#define I2C_COMMAND1_S  0
+/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 1 is done in I2C Master mode, this bit changes to highlevel.
+ */
+#define I2C_COMMAND1_DONE    (BIT(31))
+#define I2C_COMMAND1_DONE_M  (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
+#define I2C_COMMAND1_DONE_V  0x00000001U
+#define I2C_COMMAND1_DONE_S  31
+
+/** I2C_COMD2_REG register
+ *  I2C command register 2
+ */
+#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
+/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 2. It consists of three parts: op_code is the
+ *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+ *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+ *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+ */
+#define I2C_COMMAND2    0x00003FFFU
+#define I2C_COMMAND2_M  (I2C_COMMAND2_V << I2C_COMMAND2_S)
+#define I2C_COMMAND2_V  0x00003FFFU
+#define I2C_COMMAND2_S  0
+/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 2 is done in I2C Master mode, this bit changes to highLevel.
+ */
+#define I2C_COMMAND2_DONE    (BIT(31))
+#define I2C_COMMAND2_DONE_M  (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
+#define I2C_COMMAND2_DONE_V  0x00000001U
+#define I2C_COMMAND2_DONE_S  31
+
+/** I2C_COMD3_REG register
+ *  I2C command register 3
+ */
+#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
+/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 3. It consists of three parts: op_code is the
+ *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+ *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+ *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+ */
+#define I2C_COMMAND3    0x00003FFFU
+#define I2C_COMMAND3_M  (I2C_COMMAND3_V << I2C_COMMAND3_S)
+#define I2C_COMMAND3_V  0x00003FFFU
+#define I2C_COMMAND3_S  0
+/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 3 is done in I2C Master mode, this bit changes to highlevel.
+ */
+#define I2C_COMMAND3_DONE    (BIT(31))
+#define I2C_COMMAND3_DONE_M  (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
+#define I2C_COMMAND3_DONE_V  0x00000001U
+#define I2C_COMMAND3_DONE_S  31
+
+/** I2C_COMD4_REG register
+ *  I2C command register 4
+ */
+#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
+/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 4. It consists of three parts: op_code is the
+ *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+ *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+ *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+ */
+#define I2C_COMMAND4    0x00003FFFU
+#define I2C_COMMAND4_M  (I2C_COMMAND4_V << I2C_COMMAND4_S)
+#define I2C_COMMAND4_V  0x00003FFFU
+#define I2C_COMMAND4_S  0
+/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 4 is done in I2C Master mode, this bit changes to highlevel.
+ */
+#define I2C_COMMAND4_DONE    (BIT(31))
+#define I2C_COMMAND4_DONE_M  (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
+#define I2C_COMMAND4_DONE_V  0x00000001U
+#define I2C_COMMAND4_DONE_S  31
+
+/** I2C_COMD5_REG register
+ *  I2C command register 5
+ */
+#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
+/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 5. It consists of three parts:op_code is the
+ *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+ *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+ *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+ */
+#define I2C_COMMAND5    0x00003FFFU
+#define I2C_COMMAND5_M  (I2C_COMMAND5_V << I2C_COMMAND5_S)
+#define I2C_COMMAND5_V  0x00003FFFU
+#define I2C_COMMAND5_S  0
+/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 5 is done in I2C Master mode, this bit changes to high level.
+ */
+#define I2C_COMMAND5_DONE    (BIT(31))
+#define I2C_COMMAND5_DONE_M  (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
+#define I2C_COMMAND5_DONE_V  0x00000001U
+#define I2C_COMMAND5_DONE_S  31
+
+/** I2C_COMD6_REG register
+ *  I2C command register 6
+ */
+#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
+/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 6. It consists of three parts: op_code is the
+ *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+ *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+ *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+ */
+#define I2C_COMMAND6    0x00003FFFU
+#define I2C_COMMAND6_M  (I2C_COMMAND6_V << I2C_COMMAND6_S)
+#define I2C_COMMAND6_V  0x00003FFFU
+#define I2C_COMMAND6_S  0
+/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 6 is done in I2C Master mode, this bit changes to high level.
+ */
+#define I2C_COMMAND6_DONE    (BIT(31))
+#define I2C_COMMAND6_DONE_M  (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
+#define I2C_COMMAND6_DONE_V  0x00000001U
+#define I2C_COMMAND6_DONE_S  31
+
+/** I2C_COMD7_REG register
+ *  I2C command register 7
+ */
+#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
+/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 7. It consists of three parts: op_code is the
+ *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+ *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+ *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+ */
+#define I2C_COMMAND7    0x00003FFFU
+#define I2C_COMMAND7_M  (I2C_COMMAND7_V << I2C_COMMAND7_S)
+#define I2C_COMMAND7_V  0x00003FFFU
+#define I2C_COMMAND7_S  0
+/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 7 is done in I2C Master mode, this bit changes to high level.
+ */
+#define I2C_COMMAND7_DONE    (BIT(31))
+#define I2C_COMMAND7_DONE_M  (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
+#define I2C_COMMAND7_DONE_V  0x00000001U
+#define I2C_COMMAND7_DONE_S  31
+
+/** I2C_SCL_ST_TIME_OUT_REG register
+ *  SCL status time out register
+ */
+#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
+/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  The threshold value of SCL_FSM state unchanged period. It should be o more than 23
+ */
+#define I2C_SCL_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_ST_TO_I2C_M  (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
+#define I2C_SCL_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_ST_TO_I2C_S  0
+
+/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
+ *  SCL main status time out register
+ */
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
+/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more
+ *  than 23
+ */
+#define I2C_SCL_MAIN_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_M  (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
+#define I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_S  0
+
+/** I2C_SCL_SP_CONF_REG register
+ *  Power configuration register
+ */
+#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
+/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
+ *  When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
+ *  equals to reg_scl_rst_slv_num[4:0].
+ */
+#define I2C_SCL_RST_SLV_EN    (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S)
+#define I2C_SCL_RST_SLV_EN_V  0x00000001U
+#define I2C_SCL_RST_SLV_EN_S  0
+/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
+ *  Configure the pulses of SCL generated in I2C master mode. Valid when
+ *  reg_scl_rst_slv_en is 1.
+ */
+#define I2C_SCL_RST_SLV_NUM    0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_M  (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
+#define I2C_SCL_RST_SLV_NUM_V  0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_S  1
+/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
+ *  The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power
+ *  down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
+ */
+#define I2C_SCL_PD_EN    (BIT(6))
+#define I2C_SCL_PD_EN_M  (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S)
+#define I2C_SCL_PD_EN_V  0x00000001U
+#define I2C_SCL_PD_EN_S  6
+/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
+ *  The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power
+ *  down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.
+ */
+#define I2C_SDA_PD_EN    (BIT(7))
+#define I2C_SDA_PD_EN_M  (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S)
+#define I2C_SDA_PD_EN_V  0x00000001U
+#define I2C_SDA_PD_EN_S  7
+
+/** I2C_DATE_REG register
+ *  Version register
+ */
+#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
+/** I2C_DATE : R/W; bitpos: [31:0]; default: 37765408;
+ *  This is the the version register.
+ */
+#define I2C_DATE    0xFFFFFFFFU
+#define I2C_DATE_M  (I2C_DATE_V << I2C_DATE_S)
+#define I2C_DATE_V  0xFFFFFFFFU
+#define I2C_DATE_S  0
+
+/** I2C_TXFIFO_START_ADDR_REG register
+ *  I2C TXFIFO base address register
+ */
+#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
+/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  This is the I2C txfifo first address.
+ */
+#define I2C_TXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_M  (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S)
+#define I2C_TXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_S  0
+
+/** I2C_RXFIFO_START_ADDR_REG register
+ *  I2C RXFIFO base address register
+ */
+#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
+/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  This is the I2C rxfifo first address.
+ */
+#define I2C_RXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_M  (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S)
+#define I2C_RXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_struct.h
new file mode 100644
index 0000000000..3ccb12bd73
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_struct.h
@@ -0,0 +1,1027 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Timing registers */
+/** Type of scl_low_period register
+ *  Configures the low level width of the SCL
+ *  Clock
+ */
+typedef union {
+    struct {
+        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure for how long SCL remains low in master mode, in
+         *  I2C module clock cycles.
+         */
+        uint32_t scl_low_period:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_low_period_reg_t;
+
+/** Type of sda_hold register
+ *  Configures the hold time after a negative SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure the time to hold the data after the negativeedge
+         *  of SCL, in I2C module clock cycles.
+         */
+        uint32_t sda_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_hold_reg_t;
+
+/** Type of sda_sample register
+ *  Configures the sample time after a positive SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure for how long SDA is sampled, in I2C module clock
+         *  cycles.
+         */
+        uint32_t sda_sample_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_sample_reg_t;
+
+/** Type of scl_high_period register
+ *  Configures the high level width of SCL
+ */
+typedef union {
+    struct {
+        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure for how long SCL setup to high level and remains
+         *  high in master mode, in I2C module clock cycles.
+         */
+        uint32_t scl_high_period:9;
+        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
+         *  This register is used to configure for the SCL_FSM's waiting period for SCL high
+         *  level in master mode, in I2C module clock cycles.
+         */
+        uint32_t scl_wait_high_period:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_scl_high_period_reg_t;
+
+/** Type of scl_start_hold register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+typedef union {
+    struct {
+        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the negative edgeof SDA and the
+         *  negative edge of SCL for a START condition, in I2C module clock cycles.
+         */
+        uint32_t scl_start_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_start_hold_reg_t;
+
+/** Type of scl_rstart_setup register
+ *  Configures the delay between the positive
+ *  edge of SCL and the negative edge of SDA
+ */
+typedef union {
+    struct {
+        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the positiveedge of SCL and the
+         *  negative edge of SDA for a RESTART condition, in I2C module clock cycles.
+         */
+        uint32_t scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_rstart_setup_reg_t;
+
+/** Type of scl_stop_hold register
+ *  Configures the delay after the SCL clock
+ *  edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the delay after the STOP condition,in I2C module
+         *  clock cycles.
+         */
+        uint32_t scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_hold_reg_t;
+
+/** Type of scl_stop_setup register
+ *  Configures the delay between the SDA and
+ *  SCL positive edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the positive edgeof SCL and the
+         *  positive edge of SDA, in I2C module clock cycles.
+         */
+        uint32_t scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_setup_reg_t;
+
+/** Type of scl_st_time_out register
+ *  SCL status time out register
+ */
+typedef union {
+    struct {
+        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  The threshold value of SCL_FSM state unchanged period. It should be o more than 23
+         */
+        uint32_t scl_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_st_time_out_reg_t;
+
+/** Type of scl_main_st_time_out register
+ *  SCL main status time out register
+ */
+typedef union {
+    struct {
+        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more
+         *  than 23
+         */
+        uint32_t scl_main_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_main_st_time_out_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of ctr register
+ *  Transmission setting
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
+         *  This register is used to select the sample mode.1: sample SDA data on the SCL low
+         *  level.0: sample SDA data on the SCL high level.
+         */
+        uint32_t sample_scl_level:1;
+        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
+         *  This register is used to configure the ACK value that need to sent by master when
+         *  the rx_fifo_cnt has reached the threshold.
+         */
+        uint32_t rx_full_ack_level:1;
+        uint32_t reserved_4:1;
+        /** trans_start : WT; bitpos: [5]; default: 0;
+         *  Set this bit to start sending the data in txfifo.
+         */
+        uint32_t trans_start:1;
+        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
+         *  This bit is used to control the sending mode for data needing to be sent. 1: send
+         *  data from the least significant bit,0: send data from the most significant bit.
+         */
+        uint32_t tx_lsb_first:1;
+        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
+         *  This bit is used to control the storage mode for received data.1: receive data from
+         *  the least significant bit,0: receive data from the most significant bit.
+         */
+        uint32_t rx_lsb_first:1;
+        /** clk_en : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t clk_en:1;
+        /** arbitration_en : R/W; bitpos: [9]; default: 1;
+         *  This is the enable bit for arbitration_lost.
+         */
+        uint32_t arbitration_en:1;
+        /** fsm_rst : WT; bitpos: [10]; default: 0;
+         *  This register is used to reset the scl FMS.
+         */
+        uint32_t fsm_rst:1;
+        /** conf_upgate : WT; bitpos: [11]; default: 0;
+         *  synchronization bit
+         */
+        uint32_t conf_upgate:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2c_ctr_reg_t;
+
+/** Type of to register
+ *  Setting time out control for receiving data.
+ */
+typedef union {
+    struct {
+        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
+         *  This register is used to configure the timeout for receiving a data bit in APBclock
+         *  cycles.
+         */
+        uint32_t time_out_value:5;
+        /** time_out_en : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for time out control.
+         */
+        uint32_t time_out_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i2c_to_reg_t;
+
+/** Type of fifo_conf register
+ *  FIFO configuration register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_thrhd : R/W; bitpos: [3:0]; default: 6;
+         *  The water mark threshold of rx FIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
+         *  reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t rxfifo_wm_thrhd:4;
+        uint32_t reserved_4:1;
+        /** txfifo_wm_thrhd : R/W; bitpos: [8:5]; default: 2;
+         *  The water mark threshold of tx FIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
+         *  reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t txfifo_wm_thrhd:4;
+        uint32_t reserved_9:1;
+        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to enable APB nonfifo access.
+         */
+        uint32_t nonfifo_en:1;
+        uint32_t reserved_11:1;
+        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to reset rx-fifo.
+         */
+        uint32_t rx_fifo_rst:1;
+        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to reset tx-fifo.
+         */
+        uint32_t tx_fifo_rst:1;
+        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
+         *  The control enable bit of FIFO pointer in non-fifo access mode. This bit controls
+         *  the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
+         */
+        uint32_t fifo_prt_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_fifo_conf_reg_t;
+
+/** Type of filter_cfg register
+ *  SCL and SDA filter configuration register
+ */
+typedef union {
+    struct {
+        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
+         *  When a pulse on the SCL input has smaller width than this register valuein I2C
+         *  module clock cycles, the I2C controller will ignore that pulse.
+         */
+        uint32_t scl_filter_thres:4;
+        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
+         *  When a pulse on the SDA input has smaller width than this register valuein I2C
+         *  module clock cycles, the I2C controller will ignore that pulse.
+         */
+        uint32_t sda_filter_thres:4;
+        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
+         *  This is the filter enable bit for SCL.
+         */
+        uint32_t scl_filter_en:1;
+        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
+         *  This is the filter enable bit for SDA.
+         */
+        uint32_t sda_filter_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} i2c_filter_cfg_reg_t;
+
+/** Type of clk_conf register
+ *  I2C CLK configuration register
+ */
+typedef union {
+    struct {
+        /** sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  the integral part of the fractional divisor for i2c module
+         */
+        uint32_t sclk_div_num:8;
+        /** sclk_div_a : R/W; bitpos: [13:8]; default: 0;
+         *  the numerator of the fractional part of the fractional divisor for i2c module
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_b : R/W; bitpos: [19:14]; default: 0;
+         *  the denominator of the fractional part of the fractional divisor for i2c module
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_sel : R/W; bitpos: [20]; default: 0;
+         *  The clock selection for i2c module:0-XTAL,1-CLK_8MHz.
+         */
+        uint32_t sclk_sel:1;
+        /** sclk_active : R/W; bitpos: [21]; default: 1;
+         *  The clock switch for i2c module
+         */
+        uint32_t sclk_active:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} i2c_clk_conf_reg_t;
+
+/** Type of scl_sp_conf register
+ *  Power configuration register
+ */
+typedef union {
+    struct {
+        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
+         *  When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
+         *  equals to reg_scl_rst_slv_num[4:0].
+         */
+        uint32_t scl_rst_slv_en:1;
+        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
+         *  Configure the pulses of SCL generated in I2C master mode. Valid when
+         *  reg_scl_rst_slv_en is 1.
+         */
+        uint32_t scl_rst_slv_num:5;
+        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
+         *  The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power
+         *  down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
+         */
+        uint32_t scl_pd_en:1;
+        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
+         *  The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power
+         *  down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.
+         */
+        uint32_t sda_pd_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_scl_sp_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of sr register
+ *  Describe I2C work status.
+ */
+typedef union {
+    struct {
+        /** resp_rec : RO; bitpos: [0]; default: 0;
+         *  The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.
+         */
+        uint32_t resp_rec:1;
+        uint32_t reserved_1:2;
+        /** arb_lost : RO; bitpos: [3]; default: 0;
+         *  When the I2C controller loses control of SCL line, this register changes to 1.
+         */
+        uint32_t arb_lost:1;
+        /** bus_busy : RO; bitpos: [4]; default: 0;
+         *  1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state.
+         */
+        uint32_t bus_busy:1;
+        uint32_t reserved_5:3;
+        /** rxfifo_cnt : RO; bitpos: [12:8]; default: 0;
+         *  This field represents the amount of data needed to be sent.
+         */
+        uint32_t rxfifo_cnt:5;
+        uint32_t reserved_13:5;
+        /** txfifo_cnt : RO; bitpos: [22:18]; default: 0;
+         *  This field stores the amount of received data in RAM.
+         */
+        uint32_t txfifo_cnt:5;
+        uint32_t reserved_23:1;
+        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
+         *  This field indicates the states of the I2C module state machine. 0: Idle, 1:
+         *  Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK
+         */
+        uint32_t scl_main_state_last:3;
+        uint32_t reserved_27:1;
+        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
+         *  This field indicates the states of the state machine used to produce SCL.0: Idle,
+         *  1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop
+         */
+        uint32_t scl_state_last:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2c_sr_reg_t;
+
+/** Type of fifo_st register
+ *  FIFO status register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_raddr : RO; bitpos: [3:0]; default: 0;
+         *  This is the offset address of the APB reading from rxfifo
+         */
+        uint32_t rxfifo_raddr:4;
+        uint32_t reserved_4:1;
+        /** rxfifo_waddr : RO; bitpos: [8:5]; default: 0;
+         *  This is the offset address of i2c module receiving data and writing to rxfifo.
+         */
+        uint32_t rxfifo_waddr:4;
+        uint32_t reserved_9:1;
+        /** txfifo_raddr : RO; bitpos: [13:10]; default: 0;
+         *  This is the offset address of i2c module reading from txfifo.
+         */
+        uint32_t txfifo_raddr:4;
+        uint32_t reserved_14:1;
+        /** txfifo_waddr : RO; bitpos: [18:15]; default: 0;
+         *  This is the offset address of APB bus writing to txfifo.
+         */
+        uint32_t txfifo_waddr:4;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_fifo_st_reg_t;
+
+/** Type of data register
+ *  Rx FIFO read data.
+ */
+typedef union {
+    struct {
+        /** fifo_rdata : RO; bitpos: [7:0]; default: 0;
+         *  The value of rx FIFO read data.
+         */
+        uint32_t fifo_rdata:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_data_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_raw:1;
+        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
+         *  The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_raw:1;
+        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_raw:1;
+        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_raw:1;
+        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_raw:1;
+        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_raw:1;
+        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_raw:1;
+        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  The raw interrupt bit for the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_raw:1;
+        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_raw:1;
+        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_raw:1;
+        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_raw:1;
+        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_raw:1;
+        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_raw:1;
+        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  The raw interrupt bit for I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_clr:1;
+        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_clr:1;
+        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_clr:1;
+        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_clr:1;
+        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_clr:1;
+        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_clr:1;
+        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_clr:1;
+        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_clr:1;
+        /** nack_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_clr:1;
+        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_clr:1;
+        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_clr:1;
+        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_clr:1;
+        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_clr:1;
+        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_ena:1;
+        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_ena:1;
+        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_ena:1;
+        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_ena:1;
+        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_ena:1;
+        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_ena:1;
+        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_ena:1;
+        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_ena:1;
+        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_ena:1;
+        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_ena:1;
+        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_ena:1;
+        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The interrupt enable bit for I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_int_ena_reg_t;
+
+/** Type of int_status register
+ *  Status of captured I2C communication events
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_st:1;
+        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_st:1;
+        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_st:1;
+        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_st:1;
+        /** time_out_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_st:1;
+        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_st:1;
+        /** nack_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_st:1;
+        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_st:1;
+        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_st:1;
+        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_st:1;
+        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_st:1;
+        /** det_start_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status bit for I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_int_status_reg_t;
+
+
+/** Group: Command registers */
+/** Type of comd0 register
+ *  I2C command register 0
+ */
+typedef union {
+    struct {
+        /** command0 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 0. It consists of three parts: op_code is the
+         *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+         *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+         *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+         */
+        uint32_t command0:14;
+        uint32_t reserved_14:17;
+        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 0 is done in I2C Master mode, this bit changes to highlevel.
+         */
+        uint32_t command0_done:1;
+    };
+    uint32_t val;
+} i2c_comd0_reg_t;
+
+/** Type of comd1 register
+ *  I2C command register 1
+ */
+typedef union {
+    struct {
+        /** command1 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 1. It consists of three parts: op_code is the
+         *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+         *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+         *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+         */
+        uint32_t command1:14;
+        uint32_t reserved_14:17;
+        /** command1_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 1 is done in I2C Master mode, this bit changes to highlevel.
+         */
+        uint32_t command1_done:1;
+    };
+    uint32_t val;
+} i2c_comd1_reg_t;
+
+/** Type of comd2 register
+ *  I2C command register 2
+ */
+typedef union {
+    struct {
+        /** command2 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 2. It consists of three parts: op_code is the
+         *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+         *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+         *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+         */
+        uint32_t command2:14;
+        uint32_t reserved_14:17;
+        /** command2_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 2 is done in I2C Master mode, this bit changes to highLevel.
+         */
+        uint32_t command2_done:1;
+    };
+    uint32_t val;
+} i2c_comd2_reg_t;
+
+/** Type of comd3 register
+ *  I2C command register 3
+ */
+typedef union {
+    struct {
+        /** command3 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 3. It consists of three parts: op_code is the
+         *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+         *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+         *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+         */
+        uint32_t command3:14;
+        uint32_t reserved_14:17;
+        /** command3_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 3 is done in I2C Master mode, this bit changes to highlevel.
+         */
+        uint32_t command3_done:1;
+    };
+    uint32_t val;
+} i2c_comd3_reg_t;
+
+/** Type of comd4 register
+ *  I2C command register 4
+ */
+typedef union {
+    struct {
+        /** command4 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 4. It consists of three parts: op_code is the
+         *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+         *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+         *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+         */
+        uint32_t command4:14;
+        uint32_t reserved_14:17;
+        /** command4_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 4 is done in I2C Master mode, this bit changes to highlevel.
+         */
+        uint32_t command4_done:1;
+    };
+    uint32_t val;
+} i2c_comd4_reg_t;
+
+/** Type of comd5 register
+ *  I2C command register 5
+ */
+typedef union {
+    struct {
+        /** command5 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 5. It consists of three parts:op_code is the
+         *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+         *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+         *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+         */
+        uint32_t command5:14;
+        uint32_t reserved_14:17;
+        /** command5_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 5 is done in I2C Master mode, this bit changes to high level.
+         */
+        uint32_t command5_done:1;
+    };
+    uint32_t val;
+} i2c_comd5_reg_t;
+
+/** Type of comd6 register
+ *  I2C command register 6
+ */
+typedef union {
+    struct {
+        /** command6 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 6. It consists of three parts: op_code is the
+         *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+         *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+         *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+         */
+        uint32_t command6:14;
+        uint32_t reserved_14:17;
+        /** command6_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 6 is done in I2C Master mode, this bit changes to high level.
+         */
+        uint32_t command6_done:1;
+    };
+    uint32_t val;
+} i2c_comd6_reg_t;
+
+/** Type of comd7 register
+ *  I2C command register 7
+ */
+typedef union {
+    struct {
+        /** command7 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 7. It consists of three parts: op_code is the
+         *  command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the
+         *  number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are
+         *  used to control the ACK bit. See I2C cmd structure for moreInformation.
+         */
+        uint32_t command7:14;
+        uint32_t reserved_14:17;
+        /** command7_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 7 is done in I2C Master mode, this bit changes to high level.
+         */
+        uint32_t command7_done:1;
+    };
+    uint32_t val;
+} i2c_comd7_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 37765408;
+         *  This is the the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} i2c_date_reg_t;
+
+
+/** Group: Address register */
+/** Type of txfifo_start_addr register
+ *  I2C TXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  This is the I2C txfifo first address.
+         */
+        uint32_t txfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_txfifo_start_addr_reg_t;
+
+/** Type of rxfifo_start_addr register
+ *  I2C RXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  This is the I2C rxfifo first address.
+         */
+        uint32_t rxfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_rxfifo_start_addr_reg_t;
+
+
+typedef struct {
+    volatile i2c_scl_low_period_reg_t scl_low_period;
+    volatile i2c_ctr_reg_t ctr;
+    volatile i2c_sr_reg_t sr;
+    volatile i2c_to_reg_t to;
+    uint32_t reserved_010;
+    volatile i2c_fifo_st_reg_t fifo_st;
+    volatile i2c_fifo_conf_reg_t fifo_conf;
+    volatile i2c_data_reg_t data;
+    volatile i2c_int_raw_reg_t int_raw;
+    volatile i2c_int_clr_reg_t int_clr;
+    volatile i2c_int_ena_reg_t int_ena;
+    volatile i2c_int_status_reg_t int_status;
+    volatile i2c_sda_hold_reg_t sda_hold;
+    volatile i2c_sda_sample_reg_t sda_sample;
+    volatile i2c_scl_high_period_reg_t scl_high_period;
+    uint32_t reserved_03c;
+    volatile i2c_scl_start_hold_reg_t scl_start_hold;
+    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
+    volatile i2c_filter_cfg_reg_t filter_cfg;
+    volatile i2c_clk_conf_reg_t clk_conf;
+    volatile i2c_comd0_reg_t comd0;
+    volatile i2c_comd1_reg_t comd1;
+    volatile i2c_comd2_reg_t comd2;
+    volatile i2c_comd3_reg_t comd3;
+    volatile i2c_comd4_reg_t comd4;
+    volatile i2c_comd5_reg_t comd5;
+    volatile i2c_comd6_reg_t comd6;
+    volatile i2c_comd7_reg_t comd7;
+    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
+    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
+    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
+    uint32_t reserved_084[29];
+    volatile i2c_date_reg_t date;
+    uint32_t reserved_0fc;
+    volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
+    uint32_t reserved_104[31];
+    volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
+} i2c_dev_t;
+
+extern i2c_dev_t LP_I2C;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2s_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2s_reg.h
new file mode 100644
index 0000000000..2eeb0b8dbf
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2s_reg.h
@@ -0,0 +1,1057 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_I2S_VAD_CONF_REG register
+ *  I2S VAD Configure register
+ */
+#define LP_I2S_VAD_CONF_REG (DR_REG_LP_I2S_BASE + 0x0)
+/** LP_I2S_VAD_EN : R/W; bitpos: [0]; default: 0;
+ *  VAD enable register
+ */
+#define LP_I2S_VAD_EN    (BIT(0))
+#define LP_I2S_VAD_EN_M  (LP_I2S_VAD_EN_V << LP_I2S_VAD_EN_S)
+#define LP_I2S_VAD_EN_V  0x00000001U
+#define LP_I2S_VAD_EN_S  0
+/** LP_I2S_VAD_RESET : WT; bitpos: [1]; default: 0;
+ *  VAD reset register
+ */
+#define LP_I2S_VAD_RESET    (BIT(1))
+#define LP_I2S_VAD_RESET_M  (LP_I2S_VAD_RESET_V << LP_I2S_VAD_RESET_S)
+#define LP_I2S_VAD_RESET_V  0x00000001U
+#define LP_I2S_VAD_RESET_S  1
+/** LP_I2S_VAD_FORCE_START : WT; bitpos: [2]; default: 0;
+ *  VAD force start register.
+ */
+#define LP_I2S_VAD_FORCE_START    (BIT(2))
+#define LP_I2S_VAD_FORCE_START_M  (LP_I2S_VAD_FORCE_START_V << LP_I2S_VAD_FORCE_START_S)
+#define LP_I2S_VAD_FORCE_START_V  0x00000001U
+#define LP_I2S_VAD_FORCE_START_S  2
+
+/** LP_I2S_VAD_RESULT_REG register
+ *  I2S VAD Result register
+ */
+#define LP_I2S_VAD_RESULT_REG (DR_REG_LP_I2S_BASE + 0x4)
+/** LP_I2S_VAD_FLAG : RO; bitpos: [0]; default: 0;
+ *  Reg vad flag observe signal
+ */
+#define LP_I2S_VAD_FLAG    (BIT(0))
+#define LP_I2S_VAD_FLAG_M  (LP_I2S_VAD_FLAG_V << LP_I2S_VAD_FLAG_S)
+#define LP_I2S_VAD_FLAG_V  0x00000001U
+#define LP_I2S_VAD_FLAG_S  0
+/** LP_I2S_ENERGY_ENOUGH : RO; bitpos: [1]; default: 0;
+ *  Reg energy enough observe signal
+ */
+#define LP_I2S_ENERGY_ENOUGH    (BIT(1))
+#define LP_I2S_ENERGY_ENOUGH_M  (LP_I2S_ENERGY_ENOUGH_V << LP_I2S_ENERGY_ENOUGH_S)
+#define LP_I2S_ENERGY_ENOUGH_V  0x00000001U
+#define LP_I2S_ENERGY_ENOUGH_S  1
+
+/** LP_I2S_RX_MEM_CONF_REG register
+ *  I2S VAD Observe register
+ */
+#define LP_I2S_RX_MEM_CONF_REG (DR_REG_LP_I2S_BASE + 0x8)
+/** LP_I2S_RX_MEM_FIFO_CNT : RO; bitpos: [8:0]; default: 0;
+ *  The number of data in the rx mem
+ */
+#define LP_I2S_RX_MEM_FIFO_CNT    0x000001FFU
+#define LP_I2S_RX_MEM_FIFO_CNT_M  (LP_I2S_RX_MEM_FIFO_CNT_V << LP_I2S_RX_MEM_FIFO_CNT_S)
+#define LP_I2S_RX_MEM_FIFO_CNT_V  0x000001FFU
+#define LP_I2S_RX_MEM_FIFO_CNT_S  0
+/** LP_I2S_RX_MEM_THRESHOLD : R/W; bitpos: [16:9]; default: 63;
+ *  I2S rx mem will trigger an interrupt when the data in the mem is over(not including
+ *  equal) reg_rx_mem_threshold
+ */
+#define LP_I2S_RX_MEM_THRESHOLD    0x000000FFU
+#define LP_I2S_RX_MEM_THRESHOLD_M  (LP_I2S_RX_MEM_THRESHOLD_V << LP_I2S_RX_MEM_THRESHOLD_S)
+#define LP_I2S_RX_MEM_THRESHOLD_V  0x000000FFU
+#define LP_I2S_RX_MEM_THRESHOLD_S  9
+
+/** LP_I2S_INT_RAW_REG register
+ *  I2S interrupt raw register, valid in level.
+ */
+#define LP_I2S_INT_RAW_REG (DR_REG_LP_I2S_BASE + 0xc)
+/** LP_I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define LP_I2S_RX_DONE_INT_RAW    (BIT(0))
+#define LP_I2S_RX_DONE_INT_RAW_M  (LP_I2S_RX_DONE_INT_RAW_V << LP_I2S_RX_DONE_INT_RAW_S)
+#define LP_I2S_RX_DONE_INT_RAW_V  0x00000001U
+#define LP_I2S_RX_DONE_INT_RAW_S  0
+/** LP_I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define LP_I2S_RX_HUNG_INT_RAW    (BIT(1))
+#define LP_I2S_RX_HUNG_INT_RAW_M  (LP_I2S_RX_HUNG_INT_RAW_V << LP_I2S_RX_HUNG_INT_RAW_S)
+#define LP_I2S_RX_HUNG_INT_RAW_V  0x00000001U
+#define LP_I2S_RX_HUNG_INT_RAW_S  1
+/** LP_I2S_RX_FIFOMEM_UDF_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_fifomem_udf_int interrupt
+ */
+#define LP_I2S_RX_FIFOMEM_UDF_INT_RAW    (BIT(2))
+#define LP_I2S_RX_FIFOMEM_UDF_INT_RAW_M  (LP_I2S_RX_FIFOMEM_UDF_INT_RAW_V << LP_I2S_RX_FIFOMEM_UDF_INT_RAW_S)
+#define LP_I2S_RX_FIFOMEM_UDF_INT_RAW_V  0x00000001U
+#define LP_I2S_RX_FIFOMEM_UDF_INT_RAW_S  2
+/** LP_I2S_VAD_DONE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the vad_done_int interrupt
+ */
+#define LP_I2S_VAD_DONE_INT_RAW    (BIT(3))
+#define LP_I2S_VAD_DONE_INT_RAW_M  (LP_I2S_VAD_DONE_INT_RAW_V << LP_I2S_VAD_DONE_INT_RAW_S)
+#define LP_I2S_VAD_DONE_INT_RAW_V  0x00000001U
+#define LP_I2S_VAD_DONE_INT_RAW_S  3
+/** LP_I2S_VAD_RESET_DONE_INT_RAW : RO/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit  for the vad_reset_done_int interrupt
+ */
+#define LP_I2S_VAD_RESET_DONE_INT_RAW    (BIT(4))
+#define LP_I2S_VAD_RESET_DONE_INT_RAW_M  (LP_I2S_VAD_RESET_DONE_INT_RAW_V << LP_I2S_VAD_RESET_DONE_INT_RAW_S)
+#define LP_I2S_VAD_RESET_DONE_INT_RAW_V  0x00000001U
+#define LP_I2S_VAD_RESET_DONE_INT_RAW_S  4
+/** LP_I2S_RX_MEM_THRESHOLD_INT_RAW : RO/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit  for the rx_mem_threshold_int interrupt
+ */
+#define LP_I2S_RX_MEM_THRESHOLD_INT_RAW    (BIT(5))
+#define LP_I2S_RX_MEM_THRESHOLD_INT_RAW_M  (LP_I2S_RX_MEM_THRESHOLD_INT_RAW_V << LP_I2S_RX_MEM_THRESHOLD_INT_RAW_S)
+#define LP_I2S_RX_MEM_THRESHOLD_INT_RAW_V  0x00000001U
+#define LP_I2S_RX_MEM_THRESHOLD_INT_RAW_S  5
+
+/** LP_I2S_INT_ST_REG register
+ *  I2S interrupt status register.
+ */
+#define LP_I2S_INT_ST_REG (DR_REG_LP_I2S_BASE + 0x10)
+/** LP_I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define LP_I2S_RX_DONE_INT_ST    (BIT(0))
+#define LP_I2S_RX_DONE_INT_ST_M  (LP_I2S_RX_DONE_INT_ST_V << LP_I2S_RX_DONE_INT_ST_S)
+#define LP_I2S_RX_DONE_INT_ST_V  0x00000001U
+#define LP_I2S_RX_DONE_INT_ST_S  0
+/** LP_I2S_RX_HUNG_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define LP_I2S_RX_HUNG_INT_ST    (BIT(1))
+#define LP_I2S_RX_HUNG_INT_ST_M  (LP_I2S_RX_HUNG_INT_ST_V << LP_I2S_RX_HUNG_INT_ST_S)
+#define LP_I2S_RX_HUNG_INT_ST_V  0x00000001U
+#define LP_I2S_RX_HUNG_INT_ST_S  1
+/** LP_I2S_RX_FIFOMEM_UDF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_fifomem_udf_int interrupt
+ */
+#define LP_I2S_RX_FIFOMEM_UDF_INT_ST    (BIT(2))
+#define LP_I2S_RX_FIFOMEM_UDF_INT_ST_M  (LP_I2S_RX_FIFOMEM_UDF_INT_ST_V << LP_I2S_RX_FIFOMEM_UDF_INT_ST_S)
+#define LP_I2S_RX_FIFOMEM_UDF_INT_ST_V  0x00000001U
+#define LP_I2S_RX_FIFOMEM_UDF_INT_ST_S  2
+/** LP_I2S_VAD_DONE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the vad_done_int interrupt
+ */
+#define LP_I2S_VAD_DONE_INT_ST    (BIT(3))
+#define LP_I2S_VAD_DONE_INT_ST_M  (LP_I2S_VAD_DONE_INT_ST_V << LP_I2S_VAD_DONE_INT_ST_S)
+#define LP_I2S_VAD_DONE_INT_ST_V  0x00000001U
+#define LP_I2S_VAD_DONE_INT_ST_S  3
+/** LP_I2S_VAD_RESET_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status bit  for the vad_reset_done_int interrupt
+ */
+#define LP_I2S_VAD_RESET_DONE_INT_ST    (BIT(4))
+#define LP_I2S_VAD_RESET_DONE_INT_ST_M  (LP_I2S_VAD_RESET_DONE_INT_ST_V << LP_I2S_VAD_RESET_DONE_INT_ST_S)
+#define LP_I2S_VAD_RESET_DONE_INT_ST_V  0x00000001U
+#define LP_I2S_VAD_RESET_DONE_INT_ST_S  4
+/** LP_I2S_RX_MEM_THRESHOLD_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status bit  for the rx_mem_threshold_int interrupt
+ */
+#define LP_I2S_RX_MEM_THRESHOLD_INT_ST    (BIT(5))
+#define LP_I2S_RX_MEM_THRESHOLD_INT_ST_M  (LP_I2S_RX_MEM_THRESHOLD_INT_ST_V << LP_I2S_RX_MEM_THRESHOLD_INT_ST_S)
+#define LP_I2S_RX_MEM_THRESHOLD_INT_ST_V  0x00000001U
+#define LP_I2S_RX_MEM_THRESHOLD_INT_ST_S  5
+
+/** LP_I2S_INT_ENA_REG register
+ *  I2S interrupt enable register.
+ */
+#define LP_I2S_INT_ENA_REG (DR_REG_LP_I2S_BASE + 0x14)
+/** LP_I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+ */
+#define LP_I2S_RX_DONE_INT_ENA    (BIT(0))
+#define LP_I2S_RX_DONE_INT_ENA_M  (LP_I2S_RX_DONE_INT_ENA_V << LP_I2S_RX_DONE_INT_ENA_S)
+#define LP_I2S_RX_DONE_INT_ENA_V  0x00000001U
+#define LP_I2S_RX_DONE_INT_ENA_S  0
+/** LP_I2S_RX_HUNG_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+ */
+#define LP_I2S_RX_HUNG_INT_ENA    (BIT(1))
+#define LP_I2S_RX_HUNG_INT_ENA_M  (LP_I2S_RX_HUNG_INT_ENA_V << LP_I2S_RX_HUNG_INT_ENA_S)
+#define LP_I2S_RX_HUNG_INT_ENA_V  0x00000001U
+#define LP_I2S_RX_HUNG_INT_ENA_S  1
+/** LP_I2S_RX_FIFOMEM_UDF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_fifomem_udf_int interrupt
+ */
+#define LP_I2S_RX_FIFOMEM_UDF_INT_ENA    (BIT(2))
+#define LP_I2S_RX_FIFOMEM_UDF_INT_ENA_M  (LP_I2S_RX_FIFOMEM_UDF_INT_ENA_V << LP_I2S_RX_FIFOMEM_UDF_INT_ENA_S)
+#define LP_I2S_RX_FIFOMEM_UDF_INT_ENA_V  0x00000001U
+#define LP_I2S_RX_FIFOMEM_UDF_INT_ENA_S  2
+/** LP_I2S_VAD_DONE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the vad_done_int interrupt
+ */
+#define LP_I2S_VAD_DONE_INT_ENA    (BIT(3))
+#define LP_I2S_VAD_DONE_INT_ENA_M  (LP_I2S_VAD_DONE_INT_ENA_V << LP_I2S_VAD_DONE_INT_ENA_S)
+#define LP_I2S_VAD_DONE_INT_ENA_V  0x00000001U
+#define LP_I2S_VAD_DONE_INT_ENA_S  3
+/** LP_I2S_VAD_RESET_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit  for the vad_reset_done_int interrupt
+ */
+#define LP_I2S_VAD_RESET_DONE_INT_ENA    (BIT(4))
+#define LP_I2S_VAD_RESET_DONE_INT_ENA_M  (LP_I2S_VAD_RESET_DONE_INT_ENA_V << LP_I2S_VAD_RESET_DONE_INT_ENA_S)
+#define LP_I2S_VAD_RESET_DONE_INT_ENA_V  0x00000001U
+#define LP_I2S_VAD_RESET_DONE_INT_ENA_S  4
+/** LP_I2S_RX_MEM_THRESHOLD_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit  for the rx_mem_threshold_int interrupt
+ */
+#define LP_I2S_RX_MEM_THRESHOLD_INT_ENA    (BIT(5))
+#define LP_I2S_RX_MEM_THRESHOLD_INT_ENA_M  (LP_I2S_RX_MEM_THRESHOLD_INT_ENA_V << LP_I2S_RX_MEM_THRESHOLD_INT_ENA_S)
+#define LP_I2S_RX_MEM_THRESHOLD_INT_ENA_V  0x00000001U
+#define LP_I2S_RX_MEM_THRESHOLD_INT_ENA_S  5
+
+/** LP_I2S_INT_CLR_REG register
+ *  I2S interrupt clear register.
+ */
+#define LP_I2S_INT_CLR_REG (DR_REG_LP_I2S_BASE + 0x18)
+/** LP_I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the i2s_rx_done_int interrupt
+ */
+#define LP_I2S_RX_DONE_INT_CLR    (BIT(0))
+#define LP_I2S_RX_DONE_INT_CLR_M  (LP_I2S_RX_DONE_INT_CLR_V << LP_I2S_RX_DONE_INT_CLR_S)
+#define LP_I2S_RX_DONE_INT_CLR_V  0x00000001U
+#define LP_I2S_RX_DONE_INT_CLR_S  0
+/** LP_I2S_RX_HUNG_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the i2s_rx_hung_int interrupt
+ */
+#define LP_I2S_RX_HUNG_INT_CLR    (BIT(1))
+#define LP_I2S_RX_HUNG_INT_CLR_M  (LP_I2S_RX_HUNG_INT_CLR_V << LP_I2S_RX_HUNG_INT_CLR_S)
+#define LP_I2S_RX_HUNG_INT_CLR_V  0x00000001U
+#define LP_I2S_RX_HUNG_INT_CLR_S  1
+/** LP_I2S_RX_FIFOMEM_UDF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the i2s_rx_fifomem_udf_int interrupt
+ */
+#define LP_I2S_RX_FIFOMEM_UDF_INT_CLR    (BIT(2))
+#define LP_I2S_RX_FIFOMEM_UDF_INT_CLR_M  (LP_I2S_RX_FIFOMEM_UDF_INT_CLR_V << LP_I2S_RX_FIFOMEM_UDF_INT_CLR_S)
+#define LP_I2S_RX_FIFOMEM_UDF_INT_CLR_V  0x00000001U
+#define LP_I2S_RX_FIFOMEM_UDF_INT_CLR_S  2
+/** LP_I2S_VAD_DONE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the vad_done_int interrupt
+ */
+#define LP_I2S_VAD_DONE_INT_CLR    (BIT(3))
+#define LP_I2S_VAD_DONE_INT_CLR_M  (LP_I2S_VAD_DONE_INT_CLR_V << LP_I2S_VAD_DONE_INT_CLR_S)
+#define LP_I2S_VAD_DONE_INT_CLR_V  0x00000001U
+#define LP_I2S_VAD_DONE_INT_CLR_S  3
+/** LP_I2S_VAD_RESET_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the vad_reset_done_int interrupt
+ */
+#define LP_I2S_VAD_RESET_DONE_INT_CLR    (BIT(4))
+#define LP_I2S_VAD_RESET_DONE_INT_CLR_M  (LP_I2S_VAD_RESET_DONE_INT_CLR_V << LP_I2S_VAD_RESET_DONE_INT_CLR_S)
+#define LP_I2S_VAD_RESET_DONE_INT_CLR_V  0x00000001U
+#define LP_I2S_VAD_RESET_DONE_INT_CLR_S  4
+/** LP_I2S_RX_MEM_THRESHOLD_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the rx_mem_threshold_int interrupt
+ */
+#define LP_I2S_RX_MEM_THRESHOLD_INT_CLR    (BIT(5))
+#define LP_I2S_RX_MEM_THRESHOLD_INT_CLR_M  (LP_I2S_RX_MEM_THRESHOLD_INT_CLR_V << LP_I2S_RX_MEM_THRESHOLD_INT_CLR_S)
+#define LP_I2S_RX_MEM_THRESHOLD_INT_CLR_V  0x00000001U
+#define LP_I2S_RX_MEM_THRESHOLD_INT_CLR_S  5
+
+/** LP_I2S_RX_CONF_REG register
+ *  I2S RX configure register
+ */
+#define LP_I2S_RX_CONF_REG (DR_REG_LP_I2S_BASE + 0x20)
+/** LP_I2S_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset receiver
+ */
+#define LP_I2S_RX_RESET    (BIT(0))
+#define LP_I2S_RX_RESET_M  (LP_I2S_RX_RESET_V << LP_I2S_RX_RESET_S)
+#define LP_I2S_RX_RESET_V  0x00000001U
+#define LP_I2S_RX_RESET_S  0
+/** LP_I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Rx AFIFO
+ */
+#define LP_I2S_RX_FIFO_RESET    (BIT(1))
+#define LP_I2S_RX_FIFO_RESET_M  (LP_I2S_RX_FIFO_RESET_V << LP_I2S_RX_FIFO_RESET_S)
+#define LP_I2S_RX_FIFO_RESET_V  0x00000001U
+#define LP_I2S_RX_FIFO_RESET_S  1
+/** LP_I2S_RX_START : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to start receiving data
+ */
+#define LP_I2S_RX_START    (BIT(2))
+#define LP_I2S_RX_START_M  (LP_I2S_RX_START_V << LP_I2S_RX_START_S)
+#define LP_I2S_RX_START_V  0x00000001U
+#define LP_I2S_RX_START_S  2
+/** LP_I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave receiver mode
+ */
+#define LP_I2S_RX_SLAVE_MOD    (BIT(3))
+#define LP_I2S_RX_SLAVE_MOD_M  (LP_I2S_RX_SLAVE_MOD_V << LP_I2S_RX_SLAVE_MOD_S)
+#define LP_I2S_RX_SLAVE_MOD_V  0x00000001U
+#define LP_I2S_RX_SLAVE_MOD_S  3
+/** LP_I2S_RX_FIFOMEM_RESET : WT; bitpos: [4]; default: 0;
+ *  Set this bit to reset Rx Syncfifomem
+ */
+#define LP_I2S_RX_FIFOMEM_RESET    (BIT(4))
+#define LP_I2S_RX_FIFOMEM_RESET_M  (LP_I2S_RX_FIFOMEM_RESET_V << LP_I2S_RX_FIFOMEM_RESET_S)
+#define LP_I2S_RX_FIFOMEM_RESET_V  0x00000001U
+#define LP_I2S_RX_FIFOMEM_RESET_S  4
+/** LP_I2S_RX_MONO : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to enable receiver  in mono mode
+ */
+#define LP_I2S_RX_MONO    (BIT(5))
+#define LP_I2S_RX_MONO_M  (LP_I2S_RX_MONO_V << LP_I2S_RX_MONO_S)
+#define LP_I2S_RX_MONO_V  0x00000001U
+#define LP_I2S_RX_MONO_S  5
+/** LP_I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+ */
+#define LP_I2S_RX_BIG_ENDIAN    (BIT(7))
+#define LP_I2S_RX_BIG_ENDIAN_M  (LP_I2S_RX_BIG_ENDIAN_V << LP_I2S_RX_BIG_ENDIAN_S)
+#define LP_I2S_RX_BIG_ENDIAN_V  0x00000001U
+#define LP_I2S_RX_BIG_ENDIAN_S  7
+/** LP_I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define LP_I2S_RX_UPDATE    (BIT(8))
+#define LP_I2S_RX_UPDATE_M  (LP_I2S_RX_UPDATE_V << LP_I2S_RX_UPDATE_S)
+#define LP_I2S_RX_UPDATE_V  0x00000001U
+#define LP_I2S_RX_UPDATE_S  8
+/** LP_I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+ *  channel data value is valid in I2S RX mono mode.
+ */
+#define LP_I2S_RX_MONO_FST_VLD    (BIT(9))
+#define LP_I2S_RX_MONO_FST_VLD_M  (LP_I2S_RX_MONO_FST_VLD_V << LP_I2S_RX_MONO_FST_VLD_S)
+#define LP_I2S_RX_MONO_FST_VLD_V  0x00000001U
+#define LP_I2S_RX_MONO_FST_VLD_S  9
+/** LP_I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
+ *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define LP_I2S_RX_PCM_CONF    0x00000003U
+#define LP_I2S_RX_PCM_CONF_M  (LP_I2S_RX_PCM_CONF_V << LP_I2S_RX_PCM_CONF_S)
+#define LP_I2S_RX_PCM_CONF_V  0x00000003U
+#define LP_I2S_RX_PCM_CONF_S  10
+/** LP_I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass Compress/Decompress module for received data.
+ */
+#define LP_I2S_RX_PCM_BYPASS    (BIT(12))
+#define LP_I2S_RX_PCM_BYPASS_M  (LP_I2S_RX_PCM_BYPASS_V << LP_I2S_RX_PCM_BYPASS_S)
+#define LP_I2S_RX_PCM_BYPASS_V  0x00000001U
+#define LP_I2S_RX_PCM_BYPASS_S  12
+/** LP_I2S_RX_STOP_MODE : R/W; bitpos: [14:13]; default: 0;
+ *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+ *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+ */
+#define LP_I2S_RX_STOP_MODE    0x00000003U
+#define LP_I2S_RX_STOP_MODE_M  (LP_I2S_RX_STOP_MODE_V << LP_I2S_RX_STOP_MODE_S)
+#define LP_I2S_RX_STOP_MODE_V  0x00000003U
+#define LP_I2S_RX_STOP_MODE_S  13
+/** LP_I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+ */
+#define LP_I2S_RX_LEFT_ALIGN    (BIT(15))
+#define LP_I2S_RX_LEFT_ALIGN_M  (LP_I2S_RX_LEFT_ALIGN_V << LP_I2S_RX_LEFT_ALIGN_S)
+#define LP_I2S_RX_LEFT_ALIGN_V  0x00000001U
+#define LP_I2S_RX_LEFT_ALIGN_S  15
+/** LP_I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+ */
+#define LP_I2S_RX_24_FILL_EN    (BIT(16))
+#define LP_I2S_RX_24_FILL_EN_M  (LP_I2S_RX_24_FILL_EN_V << LP_I2S_RX_24_FILL_EN_S)
+#define LP_I2S_RX_24_FILL_EN_V  0x00000001U
+#define LP_I2S_RX_24_FILL_EN_S  16
+/** LP_I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+ *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+ */
+#define LP_I2S_RX_WS_IDLE_POL    (BIT(17))
+#define LP_I2S_RX_WS_IDLE_POL_M  (LP_I2S_RX_WS_IDLE_POL_V << LP_I2S_RX_WS_IDLE_POL_S)
+#define LP_I2S_RX_WS_IDLE_POL_V  0x00000001U
+#define LP_I2S_RX_WS_IDLE_POL_S  17
+/** LP_I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+ *  is received first.
+ */
+#define LP_I2S_RX_BIT_ORDER    (BIT(18))
+#define LP_I2S_RX_BIT_ORDER_M  (LP_I2S_RX_BIT_ORDER_V << LP_I2S_RX_BIT_ORDER_S)
+#define LP_I2S_RX_BIT_ORDER_V  0x00000001U
+#define LP_I2S_RX_BIT_ORDER_S  18
+/** LP_I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Rx mode . 0: Disable.
+ */
+#define LP_I2S_RX_TDM_EN    (BIT(19))
+#define LP_I2S_RX_TDM_EN_M  (LP_I2S_RX_TDM_EN_V << LP_I2S_RX_TDM_EN_S)
+#define LP_I2S_RX_TDM_EN_V  0x00000001U
+#define LP_I2S_RX_TDM_EN_S  19
+/** LP_I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Rx mode . 0: Disable.
+ */
+#define LP_I2S_RX_PDM_EN    (BIT(20))
+#define LP_I2S_RX_PDM_EN_M  (LP_I2S_RX_PDM_EN_V << LP_I2S_RX_PDM_EN_S)
+#define LP_I2S_RX_PDM_EN_V  0x00000001U
+#define LP_I2S_RX_PDM_EN_S  20
+
+/** LP_I2S_RX_CONF1_REG register
+ *  I2S RX configure register 1
+ */
+#define LP_I2S_RX_CONF1_REG (DR_REG_LP_I2S_BASE + 0x28)
+/** LP_I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [6:0]; default: 0;
+ *  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+ */
+#define LP_I2S_RX_TDM_WS_WIDTH    0x0000007FU
+#define LP_I2S_RX_TDM_WS_WIDTH_M  (LP_I2S_RX_TDM_WS_WIDTH_V << LP_I2S_RX_TDM_WS_WIDTH_S)
+#define LP_I2S_RX_TDM_WS_WIDTH_V  0x0000007FU
+#define LP_I2S_RX_TDM_WS_WIDTH_S  0
+/** LP_I2S_RX_BCK_DIV_NUM : R/W; bitpos: [12:7]; default: 6;
+ *  Bit clock configuration bits in receiver mode.
+ */
+#define LP_I2S_RX_BCK_DIV_NUM    0x0000003FU
+#define LP_I2S_RX_BCK_DIV_NUM_M  (LP_I2S_RX_BCK_DIV_NUM_V << LP_I2S_RX_BCK_DIV_NUM_S)
+#define LP_I2S_RX_BCK_DIV_NUM_V  0x0000003FU
+#define LP_I2S_RX_BCK_DIV_NUM_S  7
+/** LP_I2S_RX_BITS_MOD : R/W; bitpos: [17:13]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+ *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define LP_I2S_RX_BITS_MOD    0x0000001FU
+#define LP_I2S_RX_BITS_MOD_M  (LP_I2S_RX_BITS_MOD_V << LP_I2S_RX_BITS_MOD_S)
+#define LP_I2S_RX_BITS_MOD_V  0x0000001FU
+#define LP_I2S_RX_BITS_MOD_S  13
+/** LP_I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [23:18]; default: 15;
+ *  I2S Rx half sample bits -1.
+ */
+#define LP_I2S_RX_HALF_SAMPLE_BITS    0x0000003FU
+#define LP_I2S_RX_HALF_SAMPLE_BITS_M  (LP_I2S_RX_HALF_SAMPLE_BITS_V << LP_I2S_RX_HALF_SAMPLE_BITS_S)
+#define LP_I2S_RX_HALF_SAMPLE_BITS_V  0x0000003FU
+#define LP_I2S_RX_HALF_SAMPLE_BITS_S  18
+/** LP_I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [28:24]; default: 15;
+ *  The Rx bit number for each channel minus 1in TDM mode.
+ */
+#define LP_I2S_RX_TDM_CHAN_BITS    0x0000001FU
+#define LP_I2S_RX_TDM_CHAN_BITS_M  (LP_I2S_RX_TDM_CHAN_BITS_V << LP_I2S_RX_TDM_CHAN_BITS_S)
+#define LP_I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
+#define LP_I2S_RX_TDM_CHAN_BITS_S  24
+/** LP_I2S_RX_MSB_SHIFT : R/W; bitpos: [29]; default: 1;
+ *  Set this bit to enable receiver in Phillips standard mode
+ */
+#define LP_I2S_RX_MSB_SHIFT    (BIT(29))
+#define LP_I2S_RX_MSB_SHIFT_M  (LP_I2S_RX_MSB_SHIFT_V << LP_I2S_RX_MSB_SHIFT_S)
+#define LP_I2S_RX_MSB_SHIFT_V  0x00000001U
+#define LP_I2S_RX_MSB_SHIFT_S  29
+
+/** LP_I2S_RX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define LP_I2S_RX_TDM_CTRL_REG (DR_REG_LP_I2S_BASE + 0x50)
+/** LP_I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define LP_I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
+#define LP_I2S_RX_TDM_PDM_CHAN0_EN_M  (LP_I2S_RX_TDM_PDM_CHAN0_EN_V << LP_I2S_RX_TDM_PDM_CHAN0_EN_S)
+#define LP_I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
+#define LP_I2S_RX_TDM_PDM_CHAN0_EN_S  0
+/** LP_I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define LP_I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
+#define LP_I2S_RX_TDM_PDM_CHAN1_EN_M  (LP_I2S_RX_TDM_PDM_CHAN1_EN_V << LP_I2S_RX_TDM_PDM_CHAN1_EN_S)
+#define LP_I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
+#define LP_I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/** LP_I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define LP_I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define LP_I2S_RX_TDM_TOT_CHAN_NUM_M  (LP_I2S_RX_TDM_TOT_CHAN_NUM_V << LP_I2S_RX_TDM_TOT_CHAN_NUM_S)
+#define LP_I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define LP_I2S_RX_TDM_TOT_CHAN_NUM_S  16
+
+/** LP_I2S_RX_TIMING_REG register
+ *  I2S RX timing control register
+ */
+#define LP_I2S_RX_TIMING_REG (DR_REG_LP_I2S_BASE + 0x58)
+/** LP_I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define LP_I2S_RX_SD_IN_DM    0x00000003U
+#define LP_I2S_RX_SD_IN_DM_M  (LP_I2S_RX_SD_IN_DM_V << LP_I2S_RX_SD_IN_DM_S)
+#define LP_I2S_RX_SD_IN_DM_V  0x00000003U
+#define LP_I2S_RX_SD_IN_DM_S  0
+/** LP_I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define LP_I2S_RX_WS_OUT_DM    0x00000003U
+#define LP_I2S_RX_WS_OUT_DM_M  (LP_I2S_RX_WS_OUT_DM_V << LP_I2S_RX_WS_OUT_DM_S)
+#define LP_I2S_RX_WS_OUT_DM_V  0x00000003U
+#define LP_I2S_RX_WS_OUT_DM_S  16
+/** LP_I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define LP_I2S_RX_BCK_OUT_DM    0x00000003U
+#define LP_I2S_RX_BCK_OUT_DM_M  (LP_I2S_RX_BCK_OUT_DM_V << LP_I2S_RX_BCK_OUT_DM_S)
+#define LP_I2S_RX_BCK_OUT_DM_V  0x00000003U
+#define LP_I2S_RX_BCK_OUT_DM_S  20
+/** LP_I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define LP_I2S_RX_WS_IN_DM    0x00000003U
+#define LP_I2S_RX_WS_IN_DM_M  (LP_I2S_RX_WS_IN_DM_V << LP_I2S_RX_WS_IN_DM_S)
+#define LP_I2S_RX_WS_IN_DM_V  0x00000003U
+#define LP_I2S_RX_WS_IN_DM_S  24
+/** LP_I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define LP_I2S_RX_BCK_IN_DM    0x00000003U
+#define LP_I2S_RX_BCK_IN_DM_M  (LP_I2S_RX_BCK_IN_DM_V << LP_I2S_RX_BCK_IN_DM_S)
+#define LP_I2S_RX_BCK_IN_DM_V  0x00000003U
+#define LP_I2S_RX_BCK_IN_DM_S  28
+
+/** LP_I2S_LC_HUNG_CONF_REG register
+ *  I2S HUNG configure register.
+ */
+#define LP_I2S_LC_HUNG_CONF_REG (DR_REG_LP_I2S_BASE + 0x60)
+/** LP_I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+ *  when fifo hung counter is equal to this value
+ */
+#define LP_I2S_LC_FIFO_TIMEOUT    0x000000FFU
+#define LP_I2S_LC_FIFO_TIMEOUT_M  (LP_I2S_LC_FIFO_TIMEOUT_V << LP_I2S_LC_FIFO_TIMEOUT_S)
+#define LP_I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
+#define LP_I2S_LC_FIFO_TIMEOUT_S  0
+/** LP_I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  The bits are used to scale tick counter threshold. The tick counter is reset when
+ *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+ */
+#define LP_I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
+#define LP_I2S_LC_FIFO_TIMEOUT_SHIFT_M  (LP_I2S_LC_FIFO_TIMEOUT_SHIFT_V << LP_I2S_LC_FIFO_TIMEOUT_SHIFT_S)
+#define LP_I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define LP_I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/** LP_I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  The enable bit for FIFO timeout
+ */
+#define LP_I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
+#define LP_I2S_LC_FIFO_TIMEOUT_ENA_M  (LP_I2S_LC_FIFO_TIMEOUT_ENA_V << LP_I2S_LC_FIFO_TIMEOUT_ENA_S)
+#define LP_I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
+#define LP_I2S_LC_FIFO_TIMEOUT_ENA_S  11
+
+/** LP_I2S_RXEOF_NUM_REG register
+ *  I2S RX data number control register.
+ */
+#define LP_I2S_RXEOF_NUM_REG (DR_REG_LP_I2S_BASE + 0x64)
+/** LP_I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
+ *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+ *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+ */
+#define LP_I2S_RX_EOF_NUM    0x00000FFFU
+#define LP_I2S_RX_EOF_NUM_M  (LP_I2S_RX_EOF_NUM_V << LP_I2S_RX_EOF_NUM_S)
+#define LP_I2S_RX_EOF_NUM_V  0x00000FFFU
+#define LP_I2S_RX_EOF_NUM_S  0
+
+/** LP_I2S_CONF_SIGLE_DATA_REG register
+ *  I2S signal data register
+ */
+#define LP_I2S_CONF_SIGLE_DATA_REG (DR_REG_LP_I2S_BASE + 0x68)
+/** LP_I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The configured constant channel data to be sent out.
+ */
+#define LP_I2S_SINGLE_DATA    0xFFFFFFFFU
+#define LP_I2S_SINGLE_DATA_M  (LP_I2S_SINGLE_DATA_V << LP_I2S_SINGLE_DATA_S)
+#define LP_I2S_SINGLE_DATA_V  0xFFFFFFFFU
+#define LP_I2S_SINGLE_DATA_S  0
+
+/** LP_I2S_RX_PDM_CONF_REG register
+ *  I2S RX configure register
+ */
+#define LP_I2S_RX_PDM_CONF_REG (DR_REG_LP_I2S_BASE + 0x70)
+/** LP_I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable PDM2PCM RX mode. 0: DIsable.
+ */
+#define LP_I2S_RX_PDM2PCM_EN    (BIT(19))
+#define LP_I2S_RX_PDM2PCM_EN_M  (LP_I2S_RX_PDM2PCM_EN_V << LP_I2S_RX_PDM2PCM_EN_S)
+#define LP_I2S_RX_PDM2PCM_EN_V  0x00000001U
+#define LP_I2S_RX_PDM2PCM_EN_S  19
+/** LP_I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
+ *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+ *  sampling rate is 128. 0: down sampling rate is 64.
+ */
+#define LP_I2S_RX_PDM_SINC_DSR_16_EN    (BIT(20))
+#define LP_I2S_RX_PDM_SINC_DSR_16_EN_M  (LP_I2S_RX_PDM_SINC_DSR_16_EN_V << LP_I2S_RX_PDM_SINC_DSR_16_EN_S)
+#define LP_I2S_RX_PDM_SINC_DSR_16_EN_V  0x00000001U
+#define LP_I2S_RX_PDM_SINC_DSR_16_EN_S  20
+/** LP_I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
+ *  Configure PDM RX amplify number.
+ */
+#define LP_I2S_RX_PDM2PCM_AMPLIFY_NUM    0x0000000FU
+#define LP_I2S_RX_PDM2PCM_AMPLIFY_NUM_M  (LP_I2S_RX_PDM2PCM_AMPLIFY_NUM_V << LP_I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
+#define LP_I2S_RX_PDM2PCM_AMPLIFY_NUM_V  0x0000000FU
+#define LP_I2S_RX_PDM2PCM_AMPLIFY_NUM_S  21
+/** LP_I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
+ *  I2S PDM RX bypass hp filter or not.
+ */
+#define LP_I2S_RX_PDM_HP_BYPASS    (BIT(25))
+#define LP_I2S_RX_PDM_HP_BYPASS_M  (LP_I2S_RX_PDM_HP_BYPASS_V << LP_I2S_RX_PDM_HP_BYPASS_S)
+#define LP_I2S_RX_PDM_HP_BYPASS_V  0x00000001U
+#define LP_I2S_RX_PDM_HP_BYPASS_S  25
+/** LP_I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
+ *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+ *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+ */
+#define LP_I2S_RX_IIR_HP_MULT12_5    0x00000007U
+#define LP_I2S_RX_IIR_HP_MULT12_5_M  (LP_I2S_RX_IIR_HP_MULT12_5_V << LP_I2S_RX_IIR_HP_MULT12_5_S)
+#define LP_I2S_RX_IIR_HP_MULT12_5_V  0x00000007U
+#define LP_I2S_RX_IIR_HP_MULT12_5_S  26
+/** LP_I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
+ *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+ *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+ */
+#define LP_I2S_RX_IIR_HP_MULT12_0    0x00000007U
+#define LP_I2S_RX_IIR_HP_MULT12_0_M  (LP_I2S_RX_IIR_HP_MULT12_0_V << LP_I2S_RX_IIR_HP_MULT12_0_S)
+#define LP_I2S_RX_IIR_HP_MULT12_0_V  0x00000007U
+#define LP_I2S_RX_IIR_HP_MULT12_0_S  29
+
+/** LP_I2S_ECO_LOW_REG register
+ *  I2S ECO register
+ */
+#define LP_I2S_ECO_LOW_REG (DR_REG_LP_I2S_BASE + 0x74)
+/** LP_I2S_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  logic low eco registers
+ */
+#define LP_I2S_RDN_ECO_LOW    0xFFFFFFFFU
+#define LP_I2S_RDN_ECO_LOW_M  (LP_I2S_RDN_ECO_LOW_V << LP_I2S_RDN_ECO_LOW_S)
+#define LP_I2S_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define LP_I2S_RDN_ECO_LOW_S  0
+
+/** LP_I2S_ECO_HIGH_REG register
+ *  I2S ECO register
+ */
+#define LP_I2S_ECO_HIGH_REG (DR_REG_LP_I2S_BASE + 0x78)
+/** LP_I2S_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  logic high eco registers
+ */
+#define LP_I2S_RDN_ECO_HIGH    0xFFFFFFFFU
+#define LP_I2S_RDN_ECO_HIGH_M  (LP_I2S_RDN_ECO_HIGH_V << LP_I2S_RDN_ECO_HIGH_S)
+#define LP_I2S_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_I2S_RDN_ECO_HIGH_S  0
+
+/** LP_I2S_ECO_CONF_REG register
+ *  I2S ECO register
+ */
+#define LP_I2S_ECO_CONF_REG (DR_REG_LP_I2S_BASE + 0x7c)
+/** LP_I2S_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  enable rdn counter bit
+ */
+#define LP_I2S_RDN_ENA    (BIT(0))
+#define LP_I2S_RDN_ENA_M  (LP_I2S_RDN_ENA_V << LP_I2S_RDN_ENA_S)
+#define LP_I2S_RDN_ENA_V  0x00000001U
+#define LP_I2S_RDN_ENA_S  0
+/** LP_I2S_RDN_RESULT : RO; bitpos: [1]; default: 0;
+ *  rdn result
+ */
+#define LP_I2S_RDN_RESULT    (BIT(1))
+#define LP_I2S_RDN_RESULT_M  (LP_I2S_RDN_RESULT_V << LP_I2S_RDN_RESULT_S)
+#define LP_I2S_RDN_RESULT_V  0x00000001U
+#define LP_I2S_RDN_RESULT_S  1
+
+/** LP_I2S_VAD_PARAM0_REG register
+ *  I2S VAD Parameter register
+ */
+#define LP_I2S_VAD_PARAM0_REG (DR_REG_LP_I2S_BASE + 0x80)
+/** LP_I2S_PARAM_MIN_ENERGY : R/W; bitpos: [15:0]; default: 5000;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_MIN_ENERGY    0x0000FFFFU
+#define LP_I2S_PARAM_MIN_ENERGY_M  (LP_I2S_PARAM_MIN_ENERGY_V << LP_I2S_PARAM_MIN_ENERGY_S)
+#define LP_I2S_PARAM_MIN_ENERGY_V  0x0000FFFFU
+#define LP_I2S_PARAM_MIN_ENERGY_S  0
+/** LP_I2S_PARAM_INIT_FRAME_NUM : R/W; bitpos: [24:16]; default: 200;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_INIT_FRAME_NUM    0x000001FFU
+#define LP_I2S_PARAM_INIT_FRAME_NUM_M  (LP_I2S_PARAM_INIT_FRAME_NUM_V << LP_I2S_PARAM_INIT_FRAME_NUM_S)
+#define LP_I2S_PARAM_INIT_FRAME_NUM_V  0x000001FFU
+#define LP_I2S_PARAM_INIT_FRAME_NUM_S  16
+
+/** LP_I2S_VAD_PARAM1_REG register
+ *  I2S VAD Parameter register
+ */
+#define LP_I2S_VAD_PARAM1_REG (DR_REG_LP_I2S_BASE + 0x84)
+/** LP_I2S_PARAM_MIN_SPEECH_COUNT : R/W; bitpos: [3:0]; default: 3;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_MIN_SPEECH_COUNT    0x0000000FU
+#define LP_I2S_PARAM_MIN_SPEECH_COUNT_M  (LP_I2S_PARAM_MIN_SPEECH_COUNT_V << LP_I2S_PARAM_MIN_SPEECH_COUNT_S)
+#define LP_I2S_PARAM_MIN_SPEECH_COUNT_V  0x0000000FU
+#define LP_I2S_PARAM_MIN_SPEECH_COUNT_S  0
+/** LP_I2S_PARAM_MAX_SPEECH_COUNT : R/W; bitpos: [10:4]; default: 100;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_MAX_SPEECH_COUNT    0x0000007FU
+#define LP_I2S_PARAM_MAX_SPEECH_COUNT_M  (LP_I2S_PARAM_MAX_SPEECH_COUNT_V << LP_I2S_PARAM_MAX_SPEECH_COUNT_S)
+#define LP_I2S_PARAM_MAX_SPEECH_COUNT_V  0x0000007FU
+#define LP_I2S_PARAM_MAX_SPEECH_COUNT_S  4
+/** LP_I2S_PARAM_HANGOVER_SPEECH : R/W; bitpos: [15:11]; default: 3;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_HANGOVER_SPEECH    0x0000001FU
+#define LP_I2S_PARAM_HANGOVER_SPEECH_M  (LP_I2S_PARAM_HANGOVER_SPEECH_V << LP_I2S_PARAM_HANGOVER_SPEECH_S)
+#define LP_I2S_PARAM_HANGOVER_SPEECH_V  0x0000001FU
+#define LP_I2S_PARAM_HANGOVER_SPEECH_S  11
+/** LP_I2S_PARAM_HANGOVER_SILENT : R/W; bitpos: [23:16]; default: 30;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_HANGOVER_SILENT    0x000000FFU
+#define LP_I2S_PARAM_HANGOVER_SILENT_M  (LP_I2S_PARAM_HANGOVER_SILENT_V << LP_I2S_PARAM_HANGOVER_SILENT_S)
+#define LP_I2S_PARAM_HANGOVER_SILENT_V  0x000000FFU
+#define LP_I2S_PARAM_HANGOVER_SILENT_S  16
+/** LP_I2S_PARAM_MAX_OFFSET : R/W; bitpos: [30:24]; default: 40;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_MAX_OFFSET    0x0000007FU
+#define LP_I2S_PARAM_MAX_OFFSET_M  (LP_I2S_PARAM_MAX_OFFSET_V << LP_I2S_PARAM_MAX_OFFSET_S)
+#define LP_I2S_PARAM_MAX_OFFSET_V  0x0000007FU
+#define LP_I2S_PARAM_MAX_OFFSET_S  24
+/** LP_I2S_PARAM_SKIP_BAND_ENERGY : R/W; bitpos: [31]; default: 0;
+ *  Set 1 to skip band energy check.
+ */
+#define LP_I2S_PARAM_SKIP_BAND_ENERGY    (BIT(31))
+#define LP_I2S_PARAM_SKIP_BAND_ENERGY_M  (LP_I2S_PARAM_SKIP_BAND_ENERGY_V << LP_I2S_PARAM_SKIP_BAND_ENERGY_S)
+#define LP_I2S_PARAM_SKIP_BAND_ENERGY_V  0x00000001U
+#define LP_I2S_PARAM_SKIP_BAND_ENERGY_S  31
+
+/** LP_I2S_VAD_PARAM2_REG register
+ *  I2S VAD Parameter register
+ */
+#define LP_I2S_VAD_PARAM2_REG (DR_REG_LP_I2S_BASE + 0x88)
+/** LP_I2S_PARAM_NOISE_AMP_DOWN : R/W; bitpos: [15:0]; default: 26214;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_NOISE_AMP_DOWN    0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_AMP_DOWN_M  (LP_I2S_PARAM_NOISE_AMP_DOWN_V << LP_I2S_PARAM_NOISE_AMP_DOWN_S)
+#define LP_I2S_PARAM_NOISE_AMP_DOWN_V  0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_AMP_DOWN_S  0
+/** LP_I2S_PARAM_NOISE_AMP_UP : R/W; bitpos: [31:16]; default: 32440;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_NOISE_AMP_UP    0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_AMP_UP_M  (LP_I2S_PARAM_NOISE_AMP_UP_V << LP_I2S_PARAM_NOISE_AMP_UP_S)
+#define LP_I2S_PARAM_NOISE_AMP_UP_V  0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_AMP_UP_S  16
+
+/** LP_I2S_VAD_PARAM3_REG register
+ *  I2S VAD Parameter register
+ */
+#define LP_I2S_VAD_PARAM3_REG (DR_REG_LP_I2S_BASE + 0x8c)
+/** LP_I2S_PARAM_NOISE_SPE_UP0 : R/W; bitpos: [15:0]; default: 32735;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_NOISE_SPE_UP0    0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_SPE_UP0_M  (LP_I2S_PARAM_NOISE_SPE_UP0_V << LP_I2S_PARAM_NOISE_SPE_UP0_S)
+#define LP_I2S_PARAM_NOISE_SPE_UP0_V  0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_SPE_UP0_S  0
+/** LP_I2S_PARAM_NOISE_SPE_UP1 : R/W; bitpos: [31:16]; default: 32113;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_NOISE_SPE_UP1    0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_SPE_UP1_M  (LP_I2S_PARAM_NOISE_SPE_UP1_V << LP_I2S_PARAM_NOISE_SPE_UP1_S)
+#define LP_I2S_PARAM_NOISE_SPE_UP1_V  0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_SPE_UP1_S  16
+
+/** LP_I2S_VAD_PARAM4_REG register
+ *  I2S VAD Parameter register
+ */
+#define LP_I2S_VAD_PARAM4_REG (DR_REG_LP_I2S_BASE + 0x90)
+/** LP_I2S_PARAM_NOISE_SPE_DOWN : R/W; bitpos: [15:0]; default: 26214;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_NOISE_SPE_DOWN    0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_SPE_DOWN_M  (LP_I2S_PARAM_NOISE_SPE_DOWN_V << LP_I2S_PARAM_NOISE_SPE_DOWN_S)
+#define LP_I2S_PARAM_NOISE_SPE_DOWN_V  0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_SPE_DOWN_S  0
+/** LP_I2S_PARAM_NOISE_MEAN_DOWN : R/W; bitpos: [31:16]; default: 31130;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_NOISE_MEAN_DOWN    0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_MEAN_DOWN_M  (LP_I2S_PARAM_NOISE_MEAN_DOWN_V << LP_I2S_PARAM_NOISE_MEAN_DOWN_S)
+#define LP_I2S_PARAM_NOISE_MEAN_DOWN_V  0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_MEAN_DOWN_S  16
+
+/** LP_I2S_VAD_PARAM5_REG register
+ *  I2S VAD Parameter register
+ */
+#define LP_I2S_VAD_PARAM5_REG (DR_REG_LP_I2S_BASE + 0x94)
+/** LP_I2S_PARAM_NOISE_MEAN_UP0 : R/W; bitpos: [15:0]; default: 32113;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_NOISE_MEAN_UP0    0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_MEAN_UP0_M  (LP_I2S_PARAM_NOISE_MEAN_UP0_V << LP_I2S_PARAM_NOISE_MEAN_UP0_S)
+#define LP_I2S_PARAM_NOISE_MEAN_UP0_V  0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_MEAN_UP0_S  0
+/** LP_I2S_PARAM_NOISE_MEAN_UP1 : R/W; bitpos: [31:16]; default: 31784;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_NOISE_MEAN_UP1    0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_MEAN_UP1_M  (LP_I2S_PARAM_NOISE_MEAN_UP1_V << LP_I2S_PARAM_NOISE_MEAN_UP1_S)
+#define LP_I2S_PARAM_NOISE_MEAN_UP1_V  0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_MEAN_UP1_S  16
+
+/** LP_I2S_VAD_PARAM6_REG register
+ *  I2S VAD Parameter register
+ */
+#define LP_I2S_VAD_PARAM6_REG (DR_REG_LP_I2S_BASE + 0x98)
+/** LP_I2S_PARAM_NOISE_STD_FS_THSL : R/W; bitpos: [15:0]; default: 32000;
+ *  Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to
+ *  ((noise_std_max)>>11)^2*5
+ */
+#define LP_I2S_PARAM_NOISE_STD_FS_THSL    0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_STD_FS_THSL_M  (LP_I2S_PARAM_NOISE_STD_FS_THSL_V << LP_I2S_PARAM_NOISE_STD_FS_THSL_S)
+#define LP_I2S_PARAM_NOISE_STD_FS_THSL_V  0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_STD_FS_THSL_S  0
+/** LP_I2S_PARAM_NOISE_STD_FS_THSH : R/W; bitpos: [31:16]; default: 46080;
+ *  Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to
+ *  ((noise_std_max)>>11)^2*5
+ */
+#define LP_I2S_PARAM_NOISE_STD_FS_THSH    0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_STD_FS_THSH_M  (LP_I2S_PARAM_NOISE_STD_FS_THSH_V << LP_I2S_PARAM_NOISE_STD_FS_THSH_S)
+#define LP_I2S_PARAM_NOISE_STD_FS_THSH_V  0x0000FFFFU
+#define LP_I2S_PARAM_NOISE_STD_FS_THSH_S  16
+
+/** LP_I2S_VAD_PARAM7_REG register
+ *  I2S VAD Parameter register
+ */
+#define LP_I2S_VAD_PARAM7_REG (DR_REG_LP_I2S_BASE + 0x9c)
+/** LP_I2S_PARAM_THRES_UPD_BASE : R/W; bitpos: [15:0]; default: 32440;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_THRES_UPD_BASE    0x0000FFFFU
+#define LP_I2S_PARAM_THRES_UPD_BASE_M  (LP_I2S_PARAM_THRES_UPD_BASE_V << LP_I2S_PARAM_THRES_UPD_BASE_S)
+#define LP_I2S_PARAM_THRES_UPD_BASE_V  0x0000FFFFU
+#define LP_I2S_PARAM_THRES_UPD_BASE_S  0
+/** LP_I2S_PARAM_THRES_UPD_VARY : R/W; bitpos: [31:16]; default: 328;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_THRES_UPD_VARY    0x0000FFFFU
+#define LP_I2S_PARAM_THRES_UPD_VARY_M  (LP_I2S_PARAM_THRES_UPD_VARY_V << LP_I2S_PARAM_THRES_UPD_VARY_S)
+#define LP_I2S_PARAM_THRES_UPD_VARY_V  0x0000FFFFU
+#define LP_I2S_PARAM_THRES_UPD_VARY_S  16
+
+/** LP_I2S_VAD_PARAM8_REG register
+ *  I2S VAD Parameter register
+ */
+#define LP_I2S_VAD_PARAM8_REG (DR_REG_LP_I2S_BASE + 0xa0)
+/** LP_I2S_PARAM_THRES_UPD_BDL : R/W; bitpos: [7:0]; default: 64;
+ *  Noise_std boundary low when updating threshold.
+ */
+#define LP_I2S_PARAM_THRES_UPD_BDL    0x000000FFU
+#define LP_I2S_PARAM_THRES_UPD_BDL_M  (LP_I2S_PARAM_THRES_UPD_BDL_V << LP_I2S_PARAM_THRES_UPD_BDL_S)
+#define LP_I2S_PARAM_THRES_UPD_BDL_V  0x000000FFU
+#define LP_I2S_PARAM_THRES_UPD_BDL_S  0
+/** LP_I2S_PARAM_THRES_UPD_BDH : R/W; bitpos: [15:8]; default: 80;
+ *  Noise_std boundary high when updating threshold.
+ */
+#define LP_I2S_PARAM_THRES_UPD_BDH    0x000000FFU
+#define LP_I2S_PARAM_THRES_UPD_BDH_M  (LP_I2S_PARAM_THRES_UPD_BDH_V << LP_I2S_PARAM_THRES_UPD_BDH_S)
+#define LP_I2S_PARAM_THRES_UPD_BDH_V  0x000000FFU
+#define LP_I2S_PARAM_THRES_UPD_BDH_S  8
+/** LP_I2S_PARAM_FEATURE_BURST : R/W; bitpos: [31:16]; default: 8192;
+ *  VAD parameter
+ */
+#define LP_I2S_PARAM_FEATURE_BURST    0x0000FFFFU
+#define LP_I2S_PARAM_FEATURE_BURST_M  (LP_I2S_PARAM_FEATURE_BURST_V << LP_I2S_PARAM_FEATURE_BURST_S)
+#define LP_I2S_PARAM_FEATURE_BURST_V  0x0000FFFFU
+#define LP_I2S_PARAM_FEATURE_BURST_S  16
+
+/** LP_I2S_VAD_OB0_REG register
+ *  I2S VAD Observe register
+ */
+#define LP_I2S_VAD_OB0_REG (DR_REG_LP_I2S_BASE + 0xb0)
+/** LP_I2S_SPEECH_COUNT_OB : RO; bitpos: [7:0]; default: 0;
+ *  Reg silent count observe
+ */
+#define LP_I2S_SPEECH_COUNT_OB    0x000000FFU
+#define LP_I2S_SPEECH_COUNT_OB_M  (LP_I2S_SPEECH_COUNT_OB_V << LP_I2S_SPEECH_COUNT_OB_S)
+#define LP_I2S_SPEECH_COUNT_OB_V  0x000000FFU
+#define LP_I2S_SPEECH_COUNT_OB_S  0
+/** LP_I2S_SILENT_COUNT_OB : RO; bitpos: [15:8]; default: 0;
+ *  Reg speech count observe
+ */
+#define LP_I2S_SILENT_COUNT_OB    0x000000FFU
+#define LP_I2S_SILENT_COUNT_OB_M  (LP_I2S_SILENT_COUNT_OB_V << LP_I2S_SILENT_COUNT_OB_S)
+#define LP_I2S_SILENT_COUNT_OB_V  0x000000FFU
+#define LP_I2S_SILENT_COUNT_OB_S  8
+/** LP_I2S_MAX_SIGNAL0_OB : RO; bitpos: [31:16]; default: 0;
+ *  Reg max signal0 observe
+ */
+#define LP_I2S_MAX_SIGNAL0_OB    0x0000FFFFU
+#define LP_I2S_MAX_SIGNAL0_OB_M  (LP_I2S_MAX_SIGNAL0_OB_V << LP_I2S_MAX_SIGNAL0_OB_S)
+#define LP_I2S_MAX_SIGNAL0_OB_V  0x0000FFFFU
+#define LP_I2S_MAX_SIGNAL0_OB_S  16
+
+/** LP_I2S_VAD_OB1_REG register
+ *  I2S VAD Observe register
+ */
+#define LP_I2S_VAD_OB1_REG (DR_REG_LP_I2S_BASE + 0xb4)
+/** LP_I2S_MAX_SIGNAL1_OB : RO; bitpos: [15:0]; default: 0;
+ *  Reg max signal1 observe
+ */
+#define LP_I2S_MAX_SIGNAL1_OB    0x0000FFFFU
+#define LP_I2S_MAX_SIGNAL1_OB_M  (LP_I2S_MAX_SIGNAL1_OB_V << LP_I2S_MAX_SIGNAL1_OB_S)
+#define LP_I2S_MAX_SIGNAL1_OB_V  0x0000FFFFU
+#define LP_I2S_MAX_SIGNAL1_OB_S  0
+/** LP_I2S_MAX_SIGNAL2_OB : RO; bitpos: [31:16]; default: 0;
+ *  Reg max signal2 observe
+ */
+#define LP_I2S_MAX_SIGNAL2_OB    0x0000FFFFU
+#define LP_I2S_MAX_SIGNAL2_OB_M  (LP_I2S_MAX_SIGNAL2_OB_V << LP_I2S_MAX_SIGNAL2_OB_S)
+#define LP_I2S_MAX_SIGNAL2_OB_V  0x0000FFFFU
+#define LP_I2S_MAX_SIGNAL2_OB_S  16
+
+/** LP_I2S_VAD_OB2_REG register
+ *  I2S VAD Observe register
+ */
+#define LP_I2S_VAD_OB2_REG (DR_REG_LP_I2S_BASE + 0xb8)
+/** LP_I2S_NOISE_AMP_OB : RO; bitpos: [31:0]; default: 0;
+ *  Reg noise_amp observe signal
+ */
+#define LP_I2S_NOISE_AMP_OB    0xFFFFFFFFU
+#define LP_I2S_NOISE_AMP_OB_M  (LP_I2S_NOISE_AMP_OB_V << LP_I2S_NOISE_AMP_OB_S)
+#define LP_I2S_NOISE_AMP_OB_V  0xFFFFFFFFU
+#define LP_I2S_NOISE_AMP_OB_S  0
+
+/** LP_I2S_VAD_OB3_REG register
+ *  I2S VAD Observe register
+ */
+#define LP_I2S_VAD_OB3_REG (DR_REG_LP_I2S_BASE + 0xbc)
+/** LP_I2S_NOISE_MEAN_OB : RO; bitpos: [31:0]; default: 0;
+ *  Reg noise_mean observe signal
+ */
+#define LP_I2S_NOISE_MEAN_OB    0xFFFFFFFFU
+#define LP_I2S_NOISE_MEAN_OB_M  (LP_I2S_NOISE_MEAN_OB_V << LP_I2S_NOISE_MEAN_OB_S)
+#define LP_I2S_NOISE_MEAN_OB_V  0xFFFFFFFFU
+#define LP_I2S_NOISE_MEAN_OB_S  0
+
+/** LP_I2S_VAD_OB4_REG register
+ *  I2S VAD Observe register
+ */
+#define LP_I2S_VAD_OB4_REG (DR_REG_LP_I2S_BASE + 0xc0)
+/** LP_I2S_NOISE_STD_OB : RO; bitpos: [31:0]; default: 0;
+ *  Reg noise_std observe signal
+ */
+#define LP_I2S_NOISE_STD_OB    0xFFFFFFFFU
+#define LP_I2S_NOISE_STD_OB_M  (LP_I2S_NOISE_STD_OB_V << LP_I2S_NOISE_STD_OB_S)
+#define LP_I2S_NOISE_STD_OB_V  0xFFFFFFFFU
+#define LP_I2S_NOISE_STD_OB_S  0
+
+/** LP_I2S_VAD_OB5_REG register
+ *  I2S VAD Observe register
+ */
+#define LP_I2S_VAD_OB5_REG (DR_REG_LP_I2S_BASE + 0xc4)
+/** LP_I2S_OFFSET_OB : RO; bitpos: [31:0]; default: 0;
+ *  Reg offset observe signal
+ */
+#define LP_I2S_OFFSET_OB    0xFFFFFFFFU
+#define LP_I2S_OFFSET_OB_M  (LP_I2S_OFFSET_OB_V << LP_I2S_OFFSET_OB_S)
+#define LP_I2S_OFFSET_OB_V  0xFFFFFFFFU
+#define LP_I2S_OFFSET_OB_S  0
+
+/** LP_I2S_VAD_OB6_REG register
+ *  I2S VAD Observe register
+ */
+#define LP_I2S_VAD_OB6_REG (DR_REG_LP_I2S_BASE + 0xc8)
+/** LP_I2S_THRESHOLD_OB : RO; bitpos: [31:0]; default: 0;
+ *  Reg threshold observe signal
+ */
+#define LP_I2S_THRESHOLD_OB    0xFFFFFFFFU
+#define LP_I2S_THRESHOLD_OB_M  (LP_I2S_THRESHOLD_OB_V << LP_I2S_THRESHOLD_OB_S)
+#define LP_I2S_THRESHOLD_OB_V  0xFFFFFFFFU
+#define LP_I2S_THRESHOLD_OB_S  0
+
+/** LP_I2S_VAD_OB7_REG register
+ *  I2S VAD Observe register
+ */
+#define LP_I2S_VAD_OB7_REG (DR_REG_LP_I2S_BASE + 0xcc)
+/** LP_I2S_ENERGY_LOW_OB : RO; bitpos: [31:0]; default: 0;
+ *  Reg energy bit 31~0 observe signal
+ */
+#define LP_I2S_ENERGY_LOW_OB    0xFFFFFFFFU
+#define LP_I2S_ENERGY_LOW_OB_M  (LP_I2S_ENERGY_LOW_OB_V << LP_I2S_ENERGY_LOW_OB_S)
+#define LP_I2S_ENERGY_LOW_OB_V  0xFFFFFFFFU
+#define LP_I2S_ENERGY_LOW_OB_S  0
+
+/** LP_I2S_VAD_OB8_REG register
+ *  I2S VAD Observe register
+ */
+#define LP_I2S_VAD_OB8_REG (DR_REG_LP_I2S_BASE + 0xd0)
+/** LP_I2S_ENERGY_HIGH_OB : RO; bitpos: [31:0]; default: 0;
+ *  Reg energy bit 63~32 observe signal
+ */
+#define LP_I2S_ENERGY_HIGH_OB    0xFFFFFFFFU
+#define LP_I2S_ENERGY_HIGH_OB_M  (LP_I2S_ENERGY_HIGH_OB_V << LP_I2S_ENERGY_HIGH_OB_S)
+#define LP_I2S_ENERGY_HIGH_OB_V  0xFFFFFFFFU
+#define LP_I2S_ENERGY_HIGH_OB_S  0
+
+/** LP_I2S_CLK_GATE_REG register
+ *  Clock gate register
+ */
+#define LP_I2S_CLK_GATE_REG (DR_REG_LP_I2S_BASE + 0xf8)
+/** LP_I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  set this bit to enable clock gate
+ */
+#define LP_I2S_CLK_EN    (BIT(0))
+#define LP_I2S_CLK_EN_M  (LP_I2S_CLK_EN_V << LP_I2S_CLK_EN_S)
+#define LP_I2S_CLK_EN_V  0x00000001U
+#define LP_I2S_CLK_EN_S  0
+/** LP_I2S_VAD_CG_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  VAD clock gate force on register
+ */
+#define LP_I2S_VAD_CG_FORCE_ON    (BIT(1))
+#define LP_I2S_VAD_CG_FORCE_ON_M  (LP_I2S_VAD_CG_FORCE_ON_V << LP_I2S_VAD_CG_FORCE_ON_S)
+#define LP_I2S_VAD_CG_FORCE_ON_V  0x00000001U
+#define LP_I2S_VAD_CG_FORCE_ON_S  1
+/** LP_I2S_RX_MEM_CG_FORCE_ON : R/W; bitpos: [2]; default: 0;
+ *  I2S rx mem clock gate force on register
+ */
+#define LP_I2S_RX_MEM_CG_FORCE_ON    (BIT(2))
+#define LP_I2S_RX_MEM_CG_FORCE_ON_M  (LP_I2S_RX_MEM_CG_FORCE_ON_V << LP_I2S_RX_MEM_CG_FORCE_ON_S)
+#define LP_I2S_RX_MEM_CG_FORCE_ON_V  0x00000001U
+#define LP_I2S_RX_MEM_CG_FORCE_ON_S  2
+/** LP_I2S_RX_REG_CG_FORCE_ON : R/W; bitpos: [3]; default: 1;
+ *  I2S rx reg clock gate force on register
+ */
+#define LP_I2S_RX_REG_CG_FORCE_ON    (BIT(3))
+#define LP_I2S_RX_REG_CG_FORCE_ON_M  (LP_I2S_RX_REG_CG_FORCE_ON_V << LP_I2S_RX_REG_CG_FORCE_ON_S)
+#define LP_I2S_RX_REG_CG_FORCE_ON_V  0x00000001U
+#define LP_I2S_RX_REG_CG_FORCE_ON_S  3
+
+/** LP_I2S_DATE_REG register
+ *  Version control register
+ */
+#define LP_I2S_DATE_REG (DR_REG_LP_I2S_BASE + 0xfc)
+/** LP_I2S_DATE : R/W; bitpos: [27:0]; default: 36720704;
+ *  I2S version control register
+ */
+#define LP_I2S_DATE    0x0FFFFFFFU
+#define LP_I2S_DATE_M  (LP_I2S_DATE_V << LP_I2S_DATE_S)
+#define LP_I2S_DATE_V  0x0FFFFFFFU
+#define LP_I2S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2s_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2s_struct.h
new file mode 100644
index 0000000000..bfc118ffeb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2s_struct.h
@@ -0,0 +1,949 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: VAD registers */
+/** Type of vad_conf register
+ *  I2S VAD Configure register
+ */
+typedef union {
+    struct {
+        /** vad_en : R/W; bitpos: [0]; default: 0;
+         *  VAD enable register
+         */
+        uint32_t vad_en:1;
+        /** vad_reset : WT; bitpos: [1]; default: 0;
+         *  VAD reset register
+         */
+        uint32_t vad_reset:1;
+        /** vad_force_start : WT; bitpos: [2]; default: 0;
+         *  VAD force start register.
+         */
+        uint32_t vad_force_start:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} lp_i2s_vad_conf_reg_t;
+
+/** Type of vad_result register
+ *  I2S VAD Result register
+ */
+typedef union {
+    struct {
+        /** vad_flag : RO; bitpos: [0]; default: 0;
+         *  Reg vad flag observe signal
+         */
+        uint32_t vad_flag:1;
+        /** energy_enough : RO; bitpos: [1]; default: 0;
+         *  Reg energy enough observe signal
+         */
+        uint32_t energy_enough:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_i2s_vad_result_reg_t;
+
+/** Type of vad_param0 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_min_energy : R/W; bitpos: [15:0]; default: 5000;
+         *  VAD parameter
+         */
+        uint32_t param_min_energy:16;
+        /** param_init_frame_num : R/W; bitpos: [24:16]; default: 200;
+         *  VAD parameter
+         */
+        uint32_t param_init_frame_num:9;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} lp_i2s_vad_param0_reg_t;
+
+/** Type of vad_param1 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_min_speech_count : R/W; bitpos: [3:0]; default: 3;
+         *  VAD parameter
+         */
+        uint32_t param_min_speech_count:4;
+        /** param_max_speech_count : R/W; bitpos: [10:4]; default: 100;
+         *  VAD parameter
+         */
+        uint32_t param_max_speech_count:7;
+        /** param_hangover_speech : R/W; bitpos: [15:11]; default: 3;
+         *  VAD parameter
+         */
+        uint32_t param_hangover_speech:5;
+        /** param_hangover_silent : R/W; bitpos: [23:16]; default: 30;
+         *  VAD parameter
+         */
+        uint32_t param_hangover_silent:8;
+        /** param_max_offset : R/W; bitpos: [30:24]; default: 40;
+         *  VAD parameter
+         */
+        uint32_t param_max_offset:7;
+        /** param_skip_band_energy : R/W; bitpos: [31]; default: 0;
+         *  Set 1 to skip band energy check.
+         */
+        uint32_t param_skip_band_energy:1;
+    };
+    uint32_t val;
+} lp_i2s_vad_param1_reg_t;
+
+/** Type of vad_param2 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_noise_amp_down : R/W; bitpos: [15:0]; default: 26214;
+         *  VAD parameter
+         */
+        uint32_t param_noise_amp_down:16;
+        /** param_noise_amp_up : R/W; bitpos: [31:16]; default: 32440;
+         *  VAD parameter
+         */
+        uint32_t param_noise_amp_up:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param2_reg_t;
+
+/** Type of vad_param3 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_noise_spe_up0 : R/W; bitpos: [15:0]; default: 32735;
+         *  VAD parameter
+         */
+        uint32_t param_noise_spe_up0:16;
+        /** param_noise_spe_up1 : R/W; bitpos: [31:16]; default: 32113;
+         *  VAD parameter
+         */
+        uint32_t param_noise_spe_up1:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param3_reg_t;
+
+/** Type of vad_param4 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_noise_spe_down : R/W; bitpos: [15:0]; default: 26214;
+         *  VAD parameter
+         */
+        uint32_t param_noise_spe_down:16;
+        /** param_noise_mean_down : R/W; bitpos: [31:16]; default: 31130;
+         *  VAD parameter
+         */
+        uint32_t param_noise_mean_down:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param4_reg_t;
+
+/** Type of vad_param5 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_noise_mean_up0 : R/W; bitpos: [15:0]; default: 32113;
+         *  VAD parameter
+         */
+        uint32_t param_noise_mean_up0:16;
+        /** param_noise_mean_up1 : R/W; bitpos: [31:16]; default: 31784;
+         *  VAD parameter
+         */
+        uint32_t param_noise_mean_up1:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param5_reg_t;
+
+/** Type of vad_param6 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_noise_std_fs_thsl : R/W; bitpos: [15:0]; default: 32000;
+         *  Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to
+         *  ((noise_std_max)>>11)^2*5
+         */
+        uint32_t param_noise_std_fs_thsl:16;
+        /** param_noise_std_fs_thsh : R/W; bitpos: [31:16]; default: 46080;
+         *  Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to
+         *  ((noise_std_max)>>11)^2*5
+         */
+        uint32_t param_noise_std_fs_thsh:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param6_reg_t;
+
+/** Type of vad_param7 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_thres_upd_base : R/W; bitpos: [15:0]; default: 32440;
+         *  VAD parameter
+         */
+        uint32_t param_thres_upd_base:16;
+        /** param_thres_upd_vary : R/W; bitpos: [31:16]; default: 328;
+         *  VAD parameter
+         */
+        uint32_t param_thres_upd_vary:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param7_reg_t;
+
+/** Type of vad_param8 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_thres_upd_bdl : R/W; bitpos: [7:0]; default: 64;
+         *  Noise_std boundary low when updating threshold.
+         */
+        uint32_t param_thres_upd_bdl:8;
+        /** param_thres_upd_bdh : R/W; bitpos: [15:8]; default: 80;
+         *  Noise_std boundary high when updating threshold.
+         */
+        uint32_t param_thres_upd_bdh:8;
+        /** param_feature_burst : R/W; bitpos: [31:16]; default: 8192;
+         *  VAD parameter
+         */
+        uint32_t param_feature_burst:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param8_reg_t;
+
+/** Type of vad_ob0 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** speech_count_ob : RO; bitpos: [7:0]; default: 0;
+         *  Reg silent count observe
+         */
+        uint32_t speech_count_ob:8;
+        /** silent_count_ob : RO; bitpos: [15:8]; default: 0;
+         *  Reg speech count observe
+         */
+        uint32_t silent_count_ob:8;
+        /** max_signal0_ob : RO; bitpos: [31:16]; default: 0;
+         *  Reg max signal0 observe
+         */
+        uint32_t max_signal0_ob:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob0_reg_t;
+
+/** Type of vad_ob1 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** max_signal1_ob : RO; bitpos: [15:0]; default: 0;
+         *  Reg max signal1 observe
+         */
+        uint32_t max_signal1_ob:16;
+        /** max_signal2_ob : RO; bitpos: [31:16]; default: 0;
+         *  Reg max signal2 observe
+         */
+        uint32_t max_signal2_ob:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob1_reg_t;
+
+/** Type of vad_ob2 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** noise_amp_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg noise_amp observe signal
+         */
+        uint32_t noise_amp_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob2_reg_t;
+
+/** Type of vad_ob3 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** noise_mean_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg noise_mean observe signal
+         */
+        uint32_t noise_mean_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob3_reg_t;
+
+/** Type of vad_ob4 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** noise_std_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg noise_std observe signal
+         */
+        uint32_t noise_std_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob4_reg_t;
+
+/** Type of vad_ob5 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** offset_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg offset observe signal
+         */
+        uint32_t offset_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob5_reg_t;
+
+/** Type of vad_ob6 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** threshold_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg threshold observe signal
+         */
+        uint32_t threshold_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob6_reg_t;
+
+/** Type of vad_ob7 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** energy_low_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg energy bit 31~0 observe signal
+         */
+        uint32_t energy_low_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob7_reg_t;
+
+/** Type of vad_ob8 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** energy_high_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg energy bit 63~32 observe signal
+         */
+        uint32_t energy_high_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob8_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_mem_conf register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** rx_mem_fifo_cnt : RO; bitpos: [8:0]; default: 0;
+         *  The number of data in the rx mem
+         */
+        uint32_t rx_mem_fifo_cnt:9;
+        /** rx_mem_threshold : R/W; bitpos: [16:9]; default: 63;
+         *  I2S rx mem will trigger an interrupt when the data in the mem is over(not including
+         *  equal) reg_rx_mem_threshold
+         */
+        uint32_t rx_mem_threshold:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_i2s_rx_mem_conf_reg_t;
+
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        /** rx_fifomem_reset : WT; bitpos: [4]; default: 0;
+         *  Set this bit to reset Rx Syncfifomem
+         */
+        uint32_t rx_fifomem_reset:1;
+        /** rx_mono : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        uint32_t reserved_6:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_stop_mode : R/W; bitpos: [14:13]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} lp_i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [6:0]; default: 0;
+         *  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+         */
+        uint32_t rx_tdm_ws_width:7;
+        /** rx_bck_div_num : R/W; bitpos: [12:7]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        /** rx_bits_mod : R/W; bitpos: [17:13]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [23:18]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:6;
+        /** rx_tdm_chan_bits : R/W; bitpos: [28:24]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+        /** rx_msb_shift : R/W; bitpos: [29]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_i2s_rx_conf1_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        uint32_t reserved_2:14;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rxeof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_i2s_rxeof_num_reg_t;
+
+/** Type of rx_pdm_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:19;
+        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable PDM2PCM RX mode. 0: DIsable.
+         */
+        uint32_t rx_pdm2pcm_en:1;
+        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
+         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+         *  sampling rate is 128. 0: down sampling rate is 64.
+         */
+        uint32_t rx_pdm_sinc_dsr_16_en:1;
+        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
+         *  Configure PDM RX amplify number.
+         */
+        uint32_t rx_pdm2pcm_amplify_num:4;
+        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
+         *  I2S PDM RX bypass hp filter or not.
+         */
+        uint32_t rx_pdm_hp_bypass:1;
+        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_5:3;
+        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_0:3;
+    };
+    uint32_t val;
+} lp_i2s_rx_pdm_conf_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** rx_fifomem_udf_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_fifomem_udf_int interrupt
+         */
+        uint32_t rx_fifomem_udf_int_raw:1;
+        /** vad_done_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the vad_done_int interrupt
+         */
+        uint32_t vad_done_int_raw:1;
+        /** vad_reset_done_int_raw : RO/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit  for the vad_reset_done_int interrupt
+         */
+        uint32_t vad_reset_done_int_raw:1;
+        /** rx_mem_threshold_int_raw : RO/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit  for the rx_mem_threshold_int interrupt
+         */
+        uint32_t rx_mem_threshold_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} lp_i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** rx_fifomem_udf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_fifomem_udf_int interrupt
+         */
+        uint32_t rx_fifomem_udf_int_st:1;
+        /** vad_done_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the vad_done_int interrupt
+         */
+        uint32_t vad_done_int_st:1;
+        /** vad_reset_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status bit  for the vad_reset_done_int interrupt
+         */
+        uint32_t vad_reset_done_int_st:1;
+        /** rx_mem_threshold_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status bit  for the rx_mem_threshold_int interrupt
+         */
+        uint32_t rx_mem_threshold_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} lp_i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** rx_fifomem_udf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_fifomem_udf_int interrupt
+         */
+        uint32_t rx_fifomem_udf_int_ena:1;
+        /** vad_done_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the vad_done_int interrupt
+         */
+        uint32_t vad_done_int_ena:1;
+        /** vad_reset_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit  for the vad_reset_done_int interrupt
+         */
+        uint32_t vad_reset_done_int_ena:1;
+        /** rx_mem_threshold_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit  for the rx_mem_threshold_int interrupt
+         */
+        uint32_t rx_mem_threshold_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} lp_i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** rx_fifomem_udf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_fifomem_udf_int interrupt
+         */
+        uint32_t rx_fifomem_udf_int_clr:1;
+        /** vad_done_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the vad_done_int interrupt
+         */
+        uint32_t vad_done_int_clr:1;
+        /** vad_reset_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the vad_reset_done_int interrupt
+         */
+        uint32_t vad_reset_done_int_clr:1;
+        /** rx_mem_threshold_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the rx_mem_threshold_int interrupt
+         */
+        uint32_t rx_mem_threshold_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} lp_i2s_int_clr_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:14;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_i2s_rx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_sigle_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} lp_i2s_conf_sigle_data_reg_t;
+
+
+/** Group: ECO registers */
+/** Type of eco_low register
+ *  I2S ECO register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  logic low eco registers
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} lp_i2s_eco_low_reg_t;
+
+/** Type of eco_high register
+ *  I2S ECO register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  logic high eco registers
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} lp_i2s_eco_high_reg_t;
+
+/** Type of eco_conf register
+ *  I2S ECO register
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  enable rdn counter bit
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  rdn result
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_i2s_eco_conf_reg_t;
+
+
+/** Group: Clock registers */
+/** Type of clk_gate register
+ *  Clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit to enable clock gate
+         */
+        uint32_t clk_en:1;
+        /** vad_cg_force_on : R/W; bitpos: [1]; default: 1;
+         *  VAD clock gate force on register
+         */
+        uint32_t vad_cg_force_on:1;
+        /** rx_mem_cg_force_on : R/W; bitpos: [2]; default: 0;
+         *  I2S rx mem clock gate force on register
+         */
+        uint32_t rx_mem_cg_force_on:1;
+        /** rx_reg_cg_force_on : R/W; bitpos: [3]; default: 1;
+         *  I2S rx reg clock gate force on register
+         */
+        uint32_t rx_reg_cg_force_on:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lp_i2s_clk_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36720704;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_i2s_date_reg_t;
+
+
+typedef struct lp_i2s_dev_t {
+    volatile lp_i2s_vad_conf_reg_t vad_conf;
+    volatile lp_i2s_vad_result_reg_t vad_result;
+    volatile lp_i2s_rx_mem_conf_reg_t rx_mem_conf;
+    volatile lp_i2s_int_raw_reg_t int_raw;
+    volatile lp_i2s_int_st_reg_t int_st;
+    volatile lp_i2s_int_ena_reg_t int_ena;
+    volatile lp_i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile lp_i2s_rx_conf_reg_t rx_conf;
+    uint32_t reserved_024;
+    volatile lp_i2s_rx_conf1_reg_t rx_conf1;
+    uint32_t reserved_02c[9];
+    volatile lp_i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    uint32_t reserved_054;
+    volatile lp_i2s_rx_timing_reg_t rx_timing;
+    uint32_t reserved_05c;
+    volatile lp_i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile lp_i2s_rxeof_num_reg_t rxeof_num;
+    volatile lp_i2s_conf_sigle_data_reg_t conf_sigle_data;
+    uint32_t reserved_06c;
+    volatile lp_i2s_rx_pdm_conf_reg_t rx_pdm_conf;
+    volatile lp_i2s_eco_low_reg_t eco_low;
+    volatile lp_i2s_eco_high_reg_t eco_high;
+    volatile lp_i2s_eco_conf_reg_t eco_conf;
+    volatile lp_i2s_vad_param0_reg_t vad_param0;
+    volatile lp_i2s_vad_param1_reg_t vad_param1;
+    volatile lp_i2s_vad_param2_reg_t vad_param2;
+    volatile lp_i2s_vad_param3_reg_t vad_param3;
+    volatile lp_i2s_vad_param4_reg_t vad_param4;
+    volatile lp_i2s_vad_param5_reg_t vad_param5;
+    volatile lp_i2s_vad_param6_reg_t vad_param6;
+    volatile lp_i2s_vad_param7_reg_t vad_param7;
+    volatile lp_i2s_vad_param8_reg_t vad_param8;
+    uint32_t reserved_0a4[3];
+    volatile lp_i2s_vad_ob0_reg_t vad_ob0;
+    volatile lp_i2s_vad_ob1_reg_t vad_ob1;
+    volatile lp_i2s_vad_ob2_reg_t vad_ob2;
+    volatile lp_i2s_vad_ob3_reg_t vad_ob3;
+    volatile lp_i2s_vad_ob4_reg_t vad_ob4;
+    volatile lp_i2s_vad_ob5_reg_t vad_ob5;
+    volatile lp_i2s_vad_ob6_reg_t vad_ob6;
+    volatile lp_i2s_vad_ob7_reg_t vad_ob7;
+    volatile lp_i2s_vad_ob8_reg_t vad_ob8;
+    uint32_t reserved_0d4[9];
+    volatile lp_i2s_clk_gate_reg_t clk_gate;
+    volatile lp_i2s_date_reg_t date;
+} lp_i2s_dev_t;
+
+extern lp_i2s_dev_t LP_I2S;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_i2s_dev_t) == 0x100, "Invalid size of lp_i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_intr_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_intr_reg.h
new file mode 100644
index 0000000000..f4a0e4f7c2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_intr_reg.h
@@ -0,0 +1,235 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LPINTR_SW_INT_RAW_REG register
+ *  need_des
+ */
+#define LPINTR_SW_INT_RAW_REG (DR_REG_LPINTR_BASE + 0x0)
+/** LPINTR_LP_SW_INT_RAW : R/W/WTC; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SW_INT_RAW    (BIT(31))
+#define LPINTR_LP_SW_INT_RAW_M  (LPINTR_LP_SW_INT_RAW_V << LPINTR_LP_SW_INT_RAW_S)
+#define LPINTR_LP_SW_INT_RAW_V  0x00000001U
+#define LPINTR_LP_SW_INT_RAW_S  31
+
+/** LPINTR_SW_INT_ST_REG register
+ *  need_des
+ */
+#define LPINTR_SW_INT_ST_REG (DR_REG_LPINTR_BASE + 0x4)
+/** LPINTR_LP_SW_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SW_INT_ST    (BIT(31))
+#define LPINTR_LP_SW_INT_ST_M  (LPINTR_LP_SW_INT_ST_V << LPINTR_LP_SW_INT_ST_S)
+#define LPINTR_LP_SW_INT_ST_V  0x00000001U
+#define LPINTR_LP_SW_INT_ST_S  31
+
+/** LPINTR_SW_INT_ENA_REG register
+ *  need_des
+ */
+#define LPINTR_SW_INT_ENA_REG (DR_REG_LPINTR_BASE + 0x8)
+/** LPINTR_LP_SW_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SW_INT_ENA    (BIT(31))
+#define LPINTR_LP_SW_INT_ENA_M  (LPINTR_LP_SW_INT_ENA_V << LPINTR_LP_SW_INT_ENA_S)
+#define LPINTR_LP_SW_INT_ENA_V  0x00000001U
+#define LPINTR_LP_SW_INT_ENA_S  31
+
+/** LPINTR_SW_INT_CLR_REG register
+ *  need_des
+ */
+#define LPINTR_SW_INT_CLR_REG (DR_REG_LPINTR_BASE + 0xc)
+/** LPINTR_LP_SW_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SW_INT_CLR    (BIT(31))
+#define LPINTR_LP_SW_INT_CLR_M  (LPINTR_LP_SW_INT_CLR_V << LPINTR_LP_SW_INT_CLR_S)
+#define LPINTR_LP_SW_INT_CLR_V  0x00000001U
+#define LPINTR_LP_SW_INT_CLR_S  31
+
+/** LPINTR_STATUS_REG register
+ *  need_des
+ */
+#define LPINTR_STATUS_REG (DR_REG_LPINTR_BASE + 0x10)
+/** LPINTR_LP_HUK_INTR_ST : RO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_HUK_INTR_ST    (BIT(10))
+#define LPINTR_LP_HUK_INTR_ST_M  (LPINTR_LP_HUK_INTR_ST_V << LPINTR_LP_HUK_INTR_ST_S)
+#define LPINTR_LP_HUK_INTR_ST_V  0x00000001U
+#define LPINTR_LP_HUK_INTR_ST_S  10
+/** LPINTR_SYSREG_INTR_ST : RO; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define LPINTR_SYSREG_INTR_ST    (BIT(11))
+#define LPINTR_SYSREG_INTR_ST_M  (LPINTR_SYSREG_INTR_ST_V << LPINTR_SYSREG_INTR_ST_S)
+#define LPINTR_SYSREG_INTR_ST_V  0x00000001U
+#define LPINTR_SYSREG_INTR_ST_S  11
+/** LPINTR_LP_SW_INTR_ST : RO; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SW_INTR_ST    (BIT(12))
+#define LPINTR_LP_SW_INTR_ST_M  (LPINTR_LP_SW_INTR_ST_V << LPINTR_LP_SW_INTR_ST_S)
+#define LPINTR_LP_SW_INTR_ST_V  0x00000001U
+#define LPINTR_LP_SW_INTR_ST_S  12
+/** LPINTR_LP_EFUSE_INTR_ST : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_EFUSE_INTR_ST    (BIT(13))
+#define LPINTR_LP_EFUSE_INTR_ST_M  (LPINTR_LP_EFUSE_INTR_ST_V << LPINTR_LP_EFUSE_INTR_ST_S)
+#define LPINTR_LP_EFUSE_INTR_ST_V  0x00000001U
+#define LPINTR_LP_EFUSE_INTR_ST_S  13
+/** LPINTR_LP_UART_INTR_ST : RO; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_UART_INTR_ST    (BIT(14))
+#define LPINTR_LP_UART_INTR_ST_M  (LPINTR_LP_UART_INTR_ST_V << LPINTR_LP_UART_INTR_ST_S)
+#define LPINTR_LP_UART_INTR_ST_V  0x00000001U
+#define LPINTR_LP_UART_INTR_ST_S  14
+/** LPINTR_LP_TSENS_INTR_ST : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_TSENS_INTR_ST    (BIT(15))
+#define LPINTR_LP_TSENS_INTR_ST_M  (LPINTR_LP_TSENS_INTR_ST_V << LPINTR_LP_TSENS_INTR_ST_S)
+#define LPINTR_LP_TSENS_INTR_ST_V  0x00000001U
+#define LPINTR_LP_TSENS_INTR_ST_S  15
+/** LPINTR_LP_TOUCH_INTR_ST : RO; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_TOUCH_INTR_ST    (BIT(16))
+#define LPINTR_LP_TOUCH_INTR_ST_M  (LPINTR_LP_TOUCH_INTR_ST_V << LPINTR_LP_TOUCH_INTR_ST_S)
+#define LPINTR_LP_TOUCH_INTR_ST_V  0x00000001U
+#define LPINTR_LP_TOUCH_INTR_ST_S  16
+/** LPINTR_LP_SPI_INTR_ST : RO; bitpos: [17]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SPI_INTR_ST    (BIT(17))
+#define LPINTR_LP_SPI_INTR_ST_M  (LPINTR_LP_SPI_INTR_ST_V << LPINTR_LP_SPI_INTR_ST_S)
+#define LPINTR_LP_SPI_INTR_ST_V  0x00000001U
+#define LPINTR_LP_SPI_INTR_ST_S  17
+/** LPINTR_LP_I2S_INTR_ST : RO; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_I2S_INTR_ST    (BIT(18))
+#define LPINTR_LP_I2S_INTR_ST_M  (LPINTR_LP_I2S_INTR_ST_V << LPINTR_LP_I2S_INTR_ST_S)
+#define LPINTR_LP_I2S_INTR_ST_V  0x00000001U
+#define LPINTR_LP_I2S_INTR_ST_S  18
+/** LPINTR_LP_I2C_INTR_ST : RO; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_I2C_INTR_ST    (BIT(19))
+#define LPINTR_LP_I2C_INTR_ST_M  (LPINTR_LP_I2C_INTR_ST_V << LPINTR_LP_I2C_INTR_ST_S)
+#define LPINTR_LP_I2C_INTR_ST_V  0x00000001U
+#define LPINTR_LP_I2C_INTR_ST_S  19
+/** LPINTR_LP_GPIO_INTR_ST : RO; bitpos: [20]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_GPIO_INTR_ST    (BIT(20))
+#define LPINTR_LP_GPIO_INTR_ST_M  (LPINTR_LP_GPIO_INTR_ST_V << LPINTR_LP_GPIO_INTR_ST_S)
+#define LPINTR_LP_GPIO_INTR_ST_V  0x00000001U
+#define LPINTR_LP_GPIO_INTR_ST_S  20
+/** LPINTR_LP_ADC_INTR_ST : RO; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_ADC_INTR_ST    (BIT(21))
+#define LPINTR_LP_ADC_INTR_ST_M  (LPINTR_LP_ADC_INTR_ST_V << LPINTR_LP_ADC_INTR_ST_S)
+#define LPINTR_LP_ADC_INTR_ST_V  0x00000001U
+#define LPINTR_LP_ADC_INTR_ST_S  21
+/** LPINTR_ANAPERI_INTR_ST : RO; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define LPINTR_ANAPERI_INTR_ST    (BIT(22))
+#define LPINTR_ANAPERI_INTR_ST_M  (LPINTR_ANAPERI_INTR_ST_V << LPINTR_ANAPERI_INTR_ST_S)
+#define LPINTR_ANAPERI_INTR_ST_V  0x00000001U
+#define LPINTR_ANAPERI_INTR_ST_S  22
+/** LPINTR_PMU_REG_1_INTR_ST : RO; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define LPINTR_PMU_REG_1_INTR_ST    (BIT(23))
+#define LPINTR_PMU_REG_1_INTR_ST_M  (LPINTR_PMU_REG_1_INTR_ST_V << LPINTR_PMU_REG_1_INTR_ST_S)
+#define LPINTR_PMU_REG_1_INTR_ST_V  0x00000001U
+#define LPINTR_PMU_REG_1_INTR_ST_S  23
+/** LPINTR_PMU_REG_0_INTR_ST : RO; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define LPINTR_PMU_REG_0_INTR_ST    (BIT(24))
+#define LPINTR_PMU_REG_0_INTR_ST_M  (LPINTR_PMU_REG_0_INTR_ST_V << LPINTR_PMU_REG_0_INTR_ST_S)
+#define LPINTR_PMU_REG_0_INTR_ST_V  0x00000001U
+#define LPINTR_PMU_REG_0_INTR_ST_S  24
+/** LPINTR_MB_LP_INTR_ST : RO; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define LPINTR_MB_LP_INTR_ST    (BIT(25))
+#define LPINTR_MB_LP_INTR_ST_M  (LPINTR_MB_LP_INTR_ST_V << LPINTR_MB_LP_INTR_ST_S)
+#define LPINTR_MB_LP_INTR_ST_V  0x00000001U
+#define LPINTR_MB_LP_INTR_ST_S  25
+/** LPINTR_MB_HP_INTR_ST : RO; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LPINTR_MB_HP_INTR_ST    (BIT(26))
+#define LPINTR_MB_HP_INTR_ST_M  (LPINTR_MB_HP_INTR_ST_V << LPINTR_MB_HP_INTR_ST_S)
+#define LPINTR_MB_HP_INTR_ST_V  0x00000001U
+#define LPINTR_MB_HP_INTR_ST_S  26
+/** LPINTR_LP_TIMER_REG_1_INTR_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_TIMER_REG_1_INTR_ST    (BIT(27))
+#define LPINTR_LP_TIMER_REG_1_INTR_ST_M  (LPINTR_LP_TIMER_REG_1_INTR_ST_V << LPINTR_LP_TIMER_REG_1_INTR_ST_S)
+#define LPINTR_LP_TIMER_REG_1_INTR_ST_V  0x00000001U
+#define LPINTR_LP_TIMER_REG_1_INTR_ST_S  27
+/** LPINTR_LP_TIMER_REG_0_INTR_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_TIMER_REG_0_INTR_ST    (BIT(28))
+#define LPINTR_LP_TIMER_REG_0_INTR_ST_M  (LPINTR_LP_TIMER_REG_0_INTR_ST_V << LPINTR_LP_TIMER_REG_0_INTR_ST_S)
+#define LPINTR_LP_TIMER_REG_0_INTR_ST_V  0x00000001U
+#define LPINTR_LP_TIMER_REG_0_INTR_ST_S  28
+/** LPINTR_LP_WDT_INTR_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_WDT_INTR_ST    (BIT(29))
+#define LPINTR_LP_WDT_INTR_ST_M  (LPINTR_LP_WDT_INTR_ST_V << LPINTR_LP_WDT_INTR_ST_S)
+#define LPINTR_LP_WDT_INTR_ST_V  0x00000001U
+#define LPINTR_LP_WDT_INTR_ST_S  29
+/** LPINTR_LP_RTC_INTR_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_RTC_INTR_ST    (BIT(30))
+#define LPINTR_LP_RTC_INTR_ST_M  (LPINTR_LP_RTC_INTR_ST_V << LPINTR_LP_RTC_INTR_ST_S)
+#define LPINTR_LP_RTC_INTR_ST_V  0x00000001U
+#define LPINTR_LP_RTC_INTR_ST_S  30
+/** LPINTR_HP_INTR_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_HP_INTR_ST    (BIT(31))
+#define LPINTR_HP_INTR_ST_M  (LPINTR_HP_INTR_ST_V << LPINTR_HP_INTR_ST_S)
+#define LPINTR_HP_INTR_ST_V  0x00000001U
+#define LPINTR_HP_INTR_ST_S  31
+
+/** LPINTR_DATE_REG register
+ *  need_des
+ */
+#define LPINTR_DATE_REG (DR_REG_LPINTR_BASE + 0x3fc)
+/** LPINTR_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_CLK_EN    (BIT(31))
+#define LPINTR_CLK_EN_M  (LPINTR_CLK_EN_V << LPINTR_CLK_EN_S)
+#define LPINTR_CLK_EN_V  0x00000001U
+#define LPINTR_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_intr_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_intr_struct.h
new file mode 100644
index 0000000000..7afbf69953
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_intr_struct.h
@@ -0,0 +1,205 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt Registers */
+/** Type of sw_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_sw_int_raw : R/W/WTC; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sw_int_raw:1;
+    };
+    uint32_t val;
+} lpintr_sw_int_raw_reg_t;
+
+/** Type of sw_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_sw_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sw_int_st:1;
+    };
+    uint32_t val;
+} lpintr_sw_int_st_reg_t;
+
+/** Type of sw_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_sw_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sw_int_ena:1;
+    };
+    uint32_t val;
+} lpintr_sw_int_ena_reg_t;
+
+/** Type of sw_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_sw_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sw_int_clr:1;
+    };
+    uint32_t val;
+} lpintr_sw_int_clr_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of status register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** lp_huk_intr_st : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_huk_intr_st:1;
+        /** sysreg_intr_st : RO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t sysreg_intr_st:1;
+        /** lp_sw_intr_st : RO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sw_intr_st:1;
+        /** lp_efuse_intr_st : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_efuse_intr_st:1;
+        /** lp_uart_intr_st : RO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_intr_st:1;
+        /** lp_tsens_intr_st : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tsens_intr_st:1;
+        /** lp_touch_intr_st : RO; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_touch_intr_st:1;
+        /** lp_spi_intr_st : RO; bitpos: [17]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_spi_intr_st:1;
+        /** lp_i2s_intr_st : RO; bitpos: [18]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_intr_st:1;
+        /** lp_i2c_intr_st : RO; bitpos: [19]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2c_intr_st:1;
+        /** lp_gpio_intr_st : RO; bitpos: [20]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_gpio_intr_st:1;
+        /** lp_adc_intr_st : RO; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_adc_intr_st:1;
+        /** anaperi_intr_st : RO; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t anaperi_intr_st:1;
+        /** pmu_reg_1_intr_st : RO; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_reg_1_intr_st:1;
+        /** pmu_reg_0_intr_st : RO; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_reg_0_intr_st:1;
+        /** mb_lp_intr_st : RO; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t mb_lp_intr_st:1;
+        /** mb_hp_intr_st : RO; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t mb_hp_intr_st:1;
+        /** lp_timer_reg_1_intr_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_timer_reg_1_intr_st:1;
+        /** lp_timer_reg_0_intr_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_timer_reg_0_intr_st:1;
+        /** lp_wdt_intr_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_intr_st:1;
+        /** lp_rtc_intr_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_rtc_intr_st:1;
+        /** hp_intr_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_intr_st:1;
+    };
+    uint32_t val;
+} lpintr_status_reg_t;
+
+
+/** Group: configure_register */
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lpintr_date_reg_t;
+
+
+typedef struct {
+    volatile lpintr_sw_int_raw_reg_t sw_int_raw;
+    volatile lpintr_sw_int_st_reg_t sw_int_st;
+    volatile lpintr_sw_int_ena_reg_t sw_int_ena;
+    volatile lpintr_sw_int_clr_reg_t sw_int_clr;
+    volatile lpintr_status_reg_t status;
+    uint32_t reserved_014[250];
+    volatile lpintr_date_reg_t date;
+} lpintr_dev_t;
+
+extern lpintr_dev_t LP_INTR;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lpintr_dev_t) == 0x400, "Invalid size of lpintr_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_reg.h
new file mode 100644
index 0000000000..de9f270b78
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_reg.h
@@ -0,0 +1,1283 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_IOMUX_CLK_EN_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_CLK_EN_REG (DR_REG_LP_IOMUX_BASE + 0x0)
+/** LP_IOMUX_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_CLK_EN    (BIT(0))
+#define LP_IOMUX_REG_CLK_EN_M  (LP_IOMUX_REG_CLK_EN_V << LP_IOMUX_REG_CLK_EN_S)
+#define LP_IOMUX_REG_CLK_EN_V  0x00000001U
+#define LP_IOMUX_REG_CLK_EN_S  0
+
+/** LP_IOMUX_VER_DATE_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_VER_DATE_REG (DR_REG_LP_IOMUX_BASE + 0x4)
+/** LP_IOMUX_REG_VER_DATE : R/W; bitpos: [27:0]; default: 2294547;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_VER_DATE    0x0FFFFFFFU
+#define LP_IOMUX_REG_VER_DATE_M  (LP_IOMUX_REG_VER_DATE_V << LP_IOMUX_REG_VER_DATE_S)
+#define LP_IOMUX_REG_VER_DATE_V  0x0FFFFFFFU
+#define LP_IOMUX_REG_VER_DATE_S  0
+
+/** LP_IOMUX_PAD0_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD0_REG (DR_REG_LP_IOMUX_BASE + 0x8)
+/** LP_IOMUX_REG_PAD0_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD0_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD0_DRV_M  (LP_IOMUX_REG_PAD0_DRV_V << LP_IOMUX_REG_PAD0_DRV_S)
+#define LP_IOMUX_REG_PAD0_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD0_DRV_S  0
+/** LP_IOMUX_REG_PAD0_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD0_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD0_RDE_M  (LP_IOMUX_REG_PAD0_RDE_V << LP_IOMUX_REG_PAD0_RDE_S)
+#define LP_IOMUX_REG_PAD0_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD0_RDE_S  2
+/** LP_IOMUX_REG_PAD0_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD0_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD0_RUE_M  (LP_IOMUX_REG_PAD0_RUE_V << LP_IOMUX_REG_PAD0_RUE_S)
+#define LP_IOMUX_REG_PAD0_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD0_RUE_S  3
+/** LP_IOMUX_REG_PAD0_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD0_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD0_MUX_SEL_M  (LP_IOMUX_REG_PAD0_MUX_SEL_V << LP_IOMUX_REG_PAD0_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD0_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD0_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD0_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD0_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD0_FUN_SEL_M  (LP_IOMUX_REG_PAD0_FUN_SEL_V << LP_IOMUX_REG_PAD0_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD0_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD0_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD0_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD0_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD0_SLP_SEL_M  (LP_IOMUX_REG_PAD0_SLP_SEL_V << LP_IOMUX_REG_PAD0_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD0_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD0_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD0_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD0_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD0_SLP_IE_M  (LP_IOMUX_REG_PAD0_SLP_IE_V << LP_IOMUX_REG_PAD0_SLP_IE_S)
+#define LP_IOMUX_REG_PAD0_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD0_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD0_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD0_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD0_SLP_OE_M  (LP_IOMUX_REG_PAD0_SLP_OE_V << LP_IOMUX_REG_PAD0_SLP_OE_S)
+#define LP_IOMUX_REG_PAD0_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD0_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD0_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD0_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD0_FUN_IE_M  (LP_IOMUX_REG_PAD0_FUN_IE_V << LP_IOMUX_REG_PAD0_FUN_IE_S)
+#define LP_IOMUX_REG_PAD0_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD0_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD0_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD0_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD0_FILTER_EN_M  (LP_IOMUX_REG_PAD0_FILTER_EN_V << LP_IOMUX_REG_PAD0_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD0_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD0_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD1_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD1_REG (DR_REG_LP_IOMUX_BASE + 0xc)
+/** LP_IOMUX_REG_PAD1_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD1_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD1_DRV_M  (LP_IOMUX_REG_PAD1_DRV_V << LP_IOMUX_REG_PAD1_DRV_S)
+#define LP_IOMUX_REG_PAD1_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD1_DRV_S  0
+/** LP_IOMUX_REG_PAD1_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD1_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD1_RDE_M  (LP_IOMUX_REG_PAD1_RDE_V << LP_IOMUX_REG_PAD1_RDE_S)
+#define LP_IOMUX_REG_PAD1_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD1_RDE_S  2
+/** LP_IOMUX_REG_PAD1_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD1_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD1_RUE_M  (LP_IOMUX_REG_PAD1_RUE_V << LP_IOMUX_REG_PAD1_RUE_S)
+#define LP_IOMUX_REG_PAD1_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD1_RUE_S  3
+/** LP_IOMUX_REG_PAD1_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD1_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD1_MUX_SEL_M  (LP_IOMUX_REG_PAD1_MUX_SEL_V << LP_IOMUX_REG_PAD1_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD1_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD1_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD1_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD1_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD1_FUN_SEL_M  (LP_IOMUX_REG_PAD1_FUN_SEL_V << LP_IOMUX_REG_PAD1_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD1_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD1_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD1_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD1_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD1_SLP_SEL_M  (LP_IOMUX_REG_PAD1_SLP_SEL_V << LP_IOMUX_REG_PAD1_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD1_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD1_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD1_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD1_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD1_SLP_IE_M  (LP_IOMUX_REG_PAD1_SLP_IE_V << LP_IOMUX_REG_PAD1_SLP_IE_S)
+#define LP_IOMUX_REG_PAD1_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD1_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD1_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD1_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD1_SLP_OE_M  (LP_IOMUX_REG_PAD1_SLP_OE_V << LP_IOMUX_REG_PAD1_SLP_OE_S)
+#define LP_IOMUX_REG_PAD1_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD1_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD1_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD1_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD1_FUN_IE_M  (LP_IOMUX_REG_PAD1_FUN_IE_V << LP_IOMUX_REG_PAD1_FUN_IE_S)
+#define LP_IOMUX_REG_PAD1_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD1_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD1_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD1_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD1_FILTER_EN_M  (LP_IOMUX_REG_PAD1_FILTER_EN_V << LP_IOMUX_REG_PAD1_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD1_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD1_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD2_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD2_REG (DR_REG_LP_IOMUX_BASE + 0x10)
+/** LP_IOMUX_REG_PAD2_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD2_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD2_DRV_M  (LP_IOMUX_REG_PAD2_DRV_V << LP_IOMUX_REG_PAD2_DRV_S)
+#define LP_IOMUX_REG_PAD2_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD2_DRV_S  0
+/** LP_IOMUX_REG_PAD2_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD2_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD2_RDE_M  (LP_IOMUX_REG_PAD2_RDE_V << LP_IOMUX_REG_PAD2_RDE_S)
+#define LP_IOMUX_REG_PAD2_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD2_RDE_S  2
+/** LP_IOMUX_REG_PAD2_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD2_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD2_RUE_M  (LP_IOMUX_REG_PAD2_RUE_V << LP_IOMUX_REG_PAD2_RUE_S)
+#define LP_IOMUX_REG_PAD2_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD2_RUE_S  3
+/** LP_IOMUX_REG_PAD2_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD2_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD2_MUX_SEL_M  (LP_IOMUX_REG_PAD2_MUX_SEL_V << LP_IOMUX_REG_PAD2_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD2_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD2_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD2_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD2_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD2_FUN_SEL_M  (LP_IOMUX_REG_PAD2_FUN_SEL_V << LP_IOMUX_REG_PAD2_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD2_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD2_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD2_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD2_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD2_SLP_SEL_M  (LP_IOMUX_REG_PAD2_SLP_SEL_V << LP_IOMUX_REG_PAD2_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD2_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD2_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD2_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD2_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD2_SLP_IE_M  (LP_IOMUX_REG_PAD2_SLP_IE_V << LP_IOMUX_REG_PAD2_SLP_IE_S)
+#define LP_IOMUX_REG_PAD2_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD2_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD2_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD2_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD2_SLP_OE_M  (LP_IOMUX_REG_PAD2_SLP_OE_V << LP_IOMUX_REG_PAD2_SLP_OE_S)
+#define LP_IOMUX_REG_PAD2_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD2_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD2_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD2_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD2_FUN_IE_M  (LP_IOMUX_REG_PAD2_FUN_IE_V << LP_IOMUX_REG_PAD2_FUN_IE_S)
+#define LP_IOMUX_REG_PAD2_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD2_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD2_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD2_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD2_FILTER_EN_M  (LP_IOMUX_REG_PAD2_FILTER_EN_V << LP_IOMUX_REG_PAD2_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD2_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD2_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD3_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD3_REG (DR_REG_LP_IOMUX_BASE + 0x14)
+/** LP_IOMUX_REG_PAD3_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD3_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD3_DRV_M  (LP_IOMUX_REG_PAD3_DRV_V << LP_IOMUX_REG_PAD3_DRV_S)
+#define LP_IOMUX_REG_PAD3_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD3_DRV_S  0
+/** LP_IOMUX_REG_PAD3_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD3_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD3_RDE_M  (LP_IOMUX_REG_PAD3_RDE_V << LP_IOMUX_REG_PAD3_RDE_S)
+#define LP_IOMUX_REG_PAD3_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD3_RDE_S  2
+/** LP_IOMUX_REG_PAD3_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD3_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD3_RUE_M  (LP_IOMUX_REG_PAD3_RUE_V << LP_IOMUX_REG_PAD3_RUE_S)
+#define LP_IOMUX_REG_PAD3_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD3_RUE_S  3
+/** LP_IOMUX_REG_PAD3_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD3_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD3_MUX_SEL_M  (LP_IOMUX_REG_PAD3_MUX_SEL_V << LP_IOMUX_REG_PAD3_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD3_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD3_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD3_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD3_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD3_FUN_SEL_M  (LP_IOMUX_REG_PAD3_FUN_SEL_V << LP_IOMUX_REG_PAD3_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD3_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD3_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD3_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD3_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD3_SLP_SEL_M  (LP_IOMUX_REG_PAD3_SLP_SEL_V << LP_IOMUX_REG_PAD3_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD3_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD3_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD3_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD3_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD3_SLP_IE_M  (LP_IOMUX_REG_PAD3_SLP_IE_V << LP_IOMUX_REG_PAD3_SLP_IE_S)
+#define LP_IOMUX_REG_PAD3_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD3_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD3_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD3_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD3_SLP_OE_M  (LP_IOMUX_REG_PAD3_SLP_OE_V << LP_IOMUX_REG_PAD3_SLP_OE_S)
+#define LP_IOMUX_REG_PAD3_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD3_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD3_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD3_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD3_FUN_IE_M  (LP_IOMUX_REG_PAD3_FUN_IE_V << LP_IOMUX_REG_PAD3_FUN_IE_S)
+#define LP_IOMUX_REG_PAD3_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD3_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD3_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD3_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD3_FILTER_EN_M  (LP_IOMUX_REG_PAD3_FILTER_EN_V << LP_IOMUX_REG_PAD3_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD3_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD3_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD4_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD4_REG (DR_REG_LP_IOMUX_BASE + 0x18)
+/** LP_IOMUX_REG_PAD4_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD4_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD4_DRV_M  (LP_IOMUX_REG_PAD4_DRV_V << LP_IOMUX_REG_PAD4_DRV_S)
+#define LP_IOMUX_REG_PAD4_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD4_DRV_S  0
+/** LP_IOMUX_REG_PAD4_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD4_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD4_RDE_M  (LP_IOMUX_REG_PAD4_RDE_V << LP_IOMUX_REG_PAD4_RDE_S)
+#define LP_IOMUX_REG_PAD4_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD4_RDE_S  2
+/** LP_IOMUX_REG_PAD4_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD4_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD4_RUE_M  (LP_IOMUX_REG_PAD4_RUE_V << LP_IOMUX_REG_PAD4_RUE_S)
+#define LP_IOMUX_REG_PAD4_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD4_RUE_S  3
+/** LP_IOMUX_REG_PAD4_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD4_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD4_MUX_SEL_M  (LP_IOMUX_REG_PAD4_MUX_SEL_V << LP_IOMUX_REG_PAD4_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD4_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD4_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD4_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD4_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD4_FUN_SEL_M  (LP_IOMUX_REG_PAD4_FUN_SEL_V << LP_IOMUX_REG_PAD4_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD4_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD4_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD4_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD4_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD4_SLP_SEL_M  (LP_IOMUX_REG_PAD4_SLP_SEL_V << LP_IOMUX_REG_PAD4_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD4_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD4_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD4_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD4_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD4_SLP_IE_M  (LP_IOMUX_REG_PAD4_SLP_IE_V << LP_IOMUX_REG_PAD4_SLP_IE_S)
+#define LP_IOMUX_REG_PAD4_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD4_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD4_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD4_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD4_SLP_OE_M  (LP_IOMUX_REG_PAD4_SLP_OE_V << LP_IOMUX_REG_PAD4_SLP_OE_S)
+#define LP_IOMUX_REG_PAD4_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD4_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD4_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD4_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD4_FUN_IE_M  (LP_IOMUX_REG_PAD4_FUN_IE_V << LP_IOMUX_REG_PAD4_FUN_IE_S)
+#define LP_IOMUX_REG_PAD4_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD4_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD4_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD4_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD4_FILTER_EN_M  (LP_IOMUX_REG_PAD4_FILTER_EN_V << LP_IOMUX_REG_PAD4_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD4_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD4_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD5_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD5_REG (DR_REG_LP_IOMUX_BASE + 0x1c)
+/** LP_IOMUX_REG_PAD5_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD5_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD5_DRV_M  (LP_IOMUX_REG_PAD5_DRV_V << LP_IOMUX_REG_PAD5_DRV_S)
+#define LP_IOMUX_REG_PAD5_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD5_DRV_S  0
+/** LP_IOMUX_REG_PAD5_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD5_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD5_RDE_M  (LP_IOMUX_REG_PAD5_RDE_V << LP_IOMUX_REG_PAD5_RDE_S)
+#define LP_IOMUX_REG_PAD5_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD5_RDE_S  2
+/** LP_IOMUX_REG_PAD5_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD5_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD5_RUE_M  (LP_IOMUX_REG_PAD5_RUE_V << LP_IOMUX_REG_PAD5_RUE_S)
+#define LP_IOMUX_REG_PAD5_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD5_RUE_S  3
+/** LP_IOMUX_REG_PAD5_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD5_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD5_MUX_SEL_M  (LP_IOMUX_REG_PAD5_MUX_SEL_V << LP_IOMUX_REG_PAD5_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD5_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD5_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD5_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD5_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD5_FUN_SEL_M  (LP_IOMUX_REG_PAD5_FUN_SEL_V << LP_IOMUX_REG_PAD5_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD5_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD5_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD5_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD5_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD5_SLP_SEL_M  (LP_IOMUX_REG_PAD5_SLP_SEL_V << LP_IOMUX_REG_PAD5_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD5_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD5_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD5_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD5_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD5_SLP_IE_M  (LP_IOMUX_REG_PAD5_SLP_IE_V << LP_IOMUX_REG_PAD5_SLP_IE_S)
+#define LP_IOMUX_REG_PAD5_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD5_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD5_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD5_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD5_SLP_OE_M  (LP_IOMUX_REG_PAD5_SLP_OE_V << LP_IOMUX_REG_PAD5_SLP_OE_S)
+#define LP_IOMUX_REG_PAD5_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD5_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD5_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD5_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD5_FUN_IE_M  (LP_IOMUX_REG_PAD5_FUN_IE_V << LP_IOMUX_REG_PAD5_FUN_IE_S)
+#define LP_IOMUX_REG_PAD5_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD5_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD5_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD5_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD5_FILTER_EN_M  (LP_IOMUX_REG_PAD5_FILTER_EN_V << LP_IOMUX_REG_PAD5_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD5_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD5_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD6_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD6_REG (DR_REG_LP_IOMUX_BASE + 0x20)
+/** LP_IOMUX_REG_PAD6_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD6_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD6_DRV_M  (LP_IOMUX_REG_PAD6_DRV_V << LP_IOMUX_REG_PAD6_DRV_S)
+#define LP_IOMUX_REG_PAD6_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD6_DRV_S  0
+/** LP_IOMUX_REG_PAD6_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD6_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD6_RDE_M  (LP_IOMUX_REG_PAD6_RDE_V << LP_IOMUX_REG_PAD6_RDE_S)
+#define LP_IOMUX_REG_PAD6_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD6_RDE_S  2
+/** LP_IOMUX_REG_PAD6_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD6_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD6_RUE_M  (LP_IOMUX_REG_PAD6_RUE_V << LP_IOMUX_REG_PAD6_RUE_S)
+#define LP_IOMUX_REG_PAD6_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD6_RUE_S  3
+/** LP_IOMUX_REG_PAD6_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD6_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD6_MUX_SEL_M  (LP_IOMUX_REG_PAD6_MUX_SEL_V << LP_IOMUX_REG_PAD6_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD6_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD6_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD6_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD6_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD6_FUN_SEL_M  (LP_IOMUX_REG_PAD6_FUN_SEL_V << LP_IOMUX_REG_PAD6_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD6_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD6_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD6_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD6_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD6_SLP_SEL_M  (LP_IOMUX_REG_PAD6_SLP_SEL_V << LP_IOMUX_REG_PAD6_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD6_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD6_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD6_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD6_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD6_SLP_IE_M  (LP_IOMUX_REG_PAD6_SLP_IE_V << LP_IOMUX_REG_PAD6_SLP_IE_S)
+#define LP_IOMUX_REG_PAD6_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD6_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD6_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD6_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD6_SLP_OE_M  (LP_IOMUX_REG_PAD6_SLP_OE_V << LP_IOMUX_REG_PAD6_SLP_OE_S)
+#define LP_IOMUX_REG_PAD6_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD6_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD6_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD6_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD6_FUN_IE_M  (LP_IOMUX_REG_PAD6_FUN_IE_V << LP_IOMUX_REG_PAD6_FUN_IE_S)
+#define LP_IOMUX_REG_PAD6_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD6_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD6_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD6_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD6_FILTER_EN_M  (LP_IOMUX_REG_PAD6_FILTER_EN_V << LP_IOMUX_REG_PAD6_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD6_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD6_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD7_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD7_REG (DR_REG_LP_IOMUX_BASE + 0x24)
+/** LP_IOMUX_REG_PAD7_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD7_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD7_DRV_M  (LP_IOMUX_REG_PAD7_DRV_V << LP_IOMUX_REG_PAD7_DRV_S)
+#define LP_IOMUX_REG_PAD7_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD7_DRV_S  0
+/** LP_IOMUX_REG_PAD7_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD7_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD7_RDE_M  (LP_IOMUX_REG_PAD7_RDE_V << LP_IOMUX_REG_PAD7_RDE_S)
+#define LP_IOMUX_REG_PAD7_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD7_RDE_S  2
+/** LP_IOMUX_REG_PAD7_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD7_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD7_RUE_M  (LP_IOMUX_REG_PAD7_RUE_V << LP_IOMUX_REG_PAD7_RUE_S)
+#define LP_IOMUX_REG_PAD7_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD7_RUE_S  3
+/** LP_IOMUX_REG_PAD7_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD7_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD7_MUX_SEL_M  (LP_IOMUX_REG_PAD7_MUX_SEL_V << LP_IOMUX_REG_PAD7_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD7_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD7_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD7_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD7_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD7_FUN_SEL_M  (LP_IOMUX_REG_PAD7_FUN_SEL_V << LP_IOMUX_REG_PAD7_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD7_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD7_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD7_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD7_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD7_SLP_SEL_M  (LP_IOMUX_REG_PAD7_SLP_SEL_V << LP_IOMUX_REG_PAD7_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD7_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD7_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD7_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD7_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD7_SLP_IE_M  (LP_IOMUX_REG_PAD7_SLP_IE_V << LP_IOMUX_REG_PAD7_SLP_IE_S)
+#define LP_IOMUX_REG_PAD7_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD7_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD7_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD7_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD7_SLP_OE_M  (LP_IOMUX_REG_PAD7_SLP_OE_V << LP_IOMUX_REG_PAD7_SLP_OE_S)
+#define LP_IOMUX_REG_PAD7_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD7_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD7_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD7_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD7_FUN_IE_M  (LP_IOMUX_REG_PAD7_FUN_IE_V << LP_IOMUX_REG_PAD7_FUN_IE_S)
+#define LP_IOMUX_REG_PAD7_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD7_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD7_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD7_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD7_FILTER_EN_M  (LP_IOMUX_REG_PAD7_FILTER_EN_V << LP_IOMUX_REG_PAD7_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD7_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD7_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD8_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD8_REG (DR_REG_LP_IOMUX_BASE + 0x28)
+/** LP_IOMUX_REG_PAD8_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD8_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD8_DRV_M  (LP_IOMUX_REG_PAD8_DRV_V << LP_IOMUX_REG_PAD8_DRV_S)
+#define LP_IOMUX_REG_PAD8_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD8_DRV_S  0
+/** LP_IOMUX_REG_PAD8_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD8_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD8_RDE_M  (LP_IOMUX_REG_PAD8_RDE_V << LP_IOMUX_REG_PAD8_RDE_S)
+#define LP_IOMUX_REG_PAD8_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD8_RDE_S  2
+/** LP_IOMUX_REG_PAD8_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD8_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD8_RUE_M  (LP_IOMUX_REG_PAD8_RUE_V << LP_IOMUX_REG_PAD8_RUE_S)
+#define LP_IOMUX_REG_PAD8_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD8_RUE_S  3
+/** LP_IOMUX_REG_PAD8_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD8_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD8_MUX_SEL_M  (LP_IOMUX_REG_PAD8_MUX_SEL_V << LP_IOMUX_REG_PAD8_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD8_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD8_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD8_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD8_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD8_FUN_SEL_M  (LP_IOMUX_REG_PAD8_FUN_SEL_V << LP_IOMUX_REG_PAD8_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD8_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD8_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD8_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD8_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD8_SLP_SEL_M  (LP_IOMUX_REG_PAD8_SLP_SEL_V << LP_IOMUX_REG_PAD8_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD8_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD8_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD8_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD8_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD8_SLP_IE_M  (LP_IOMUX_REG_PAD8_SLP_IE_V << LP_IOMUX_REG_PAD8_SLP_IE_S)
+#define LP_IOMUX_REG_PAD8_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD8_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD8_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD8_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD8_SLP_OE_M  (LP_IOMUX_REG_PAD8_SLP_OE_V << LP_IOMUX_REG_PAD8_SLP_OE_S)
+#define LP_IOMUX_REG_PAD8_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD8_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD8_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD8_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD8_FUN_IE_M  (LP_IOMUX_REG_PAD8_FUN_IE_V << LP_IOMUX_REG_PAD8_FUN_IE_S)
+#define LP_IOMUX_REG_PAD8_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD8_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD8_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD8_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD8_FILTER_EN_M  (LP_IOMUX_REG_PAD8_FILTER_EN_V << LP_IOMUX_REG_PAD8_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD8_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD8_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD9_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD9_REG (DR_REG_LP_IOMUX_BASE + 0x2c)
+/** LP_IOMUX_REG_PAD9_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD9_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD9_DRV_M  (LP_IOMUX_REG_PAD9_DRV_V << LP_IOMUX_REG_PAD9_DRV_S)
+#define LP_IOMUX_REG_PAD9_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD9_DRV_S  0
+/** LP_IOMUX_REG_PAD9_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD9_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD9_RDE_M  (LP_IOMUX_REG_PAD9_RDE_V << LP_IOMUX_REG_PAD9_RDE_S)
+#define LP_IOMUX_REG_PAD9_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD9_RDE_S  2
+/** LP_IOMUX_REG_PAD9_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD9_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD9_RUE_M  (LP_IOMUX_REG_PAD9_RUE_V << LP_IOMUX_REG_PAD9_RUE_S)
+#define LP_IOMUX_REG_PAD9_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD9_RUE_S  3
+/** LP_IOMUX_REG_PAD9_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD9_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD9_MUX_SEL_M  (LP_IOMUX_REG_PAD9_MUX_SEL_V << LP_IOMUX_REG_PAD9_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD9_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD9_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD9_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD9_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD9_FUN_SEL_M  (LP_IOMUX_REG_PAD9_FUN_SEL_V << LP_IOMUX_REG_PAD9_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD9_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD9_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD9_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD9_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD9_SLP_SEL_M  (LP_IOMUX_REG_PAD9_SLP_SEL_V << LP_IOMUX_REG_PAD9_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD9_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD9_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD9_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD9_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD9_SLP_IE_M  (LP_IOMUX_REG_PAD9_SLP_IE_V << LP_IOMUX_REG_PAD9_SLP_IE_S)
+#define LP_IOMUX_REG_PAD9_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD9_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD9_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD9_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD9_SLP_OE_M  (LP_IOMUX_REG_PAD9_SLP_OE_V << LP_IOMUX_REG_PAD9_SLP_OE_S)
+#define LP_IOMUX_REG_PAD9_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD9_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD9_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD9_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD9_FUN_IE_M  (LP_IOMUX_REG_PAD9_FUN_IE_V << LP_IOMUX_REG_PAD9_FUN_IE_S)
+#define LP_IOMUX_REG_PAD9_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD9_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD9_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD9_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD9_FILTER_EN_M  (LP_IOMUX_REG_PAD9_FILTER_EN_V << LP_IOMUX_REG_PAD9_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD9_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD9_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD10_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD10_REG (DR_REG_LP_IOMUX_BASE + 0x30)
+/** LP_IOMUX_REG_PAD10_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD10_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD10_DRV_M  (LP_IOMUX_REG_PAD10_DRV_V << LP_IOMUX_REG_PAD10_DRV_S)
+#define LP_IOMUX_REG_PAD10_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD10_DRV_S  0
+/** LP_IOMUX_REG_PAD10_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD10_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD10_RDE_M  (LP_IOMUX_REG_PAD10_RDE_V << LP_IOMUX_REG_PAD10_RDE_S)
+#define LP_IOMUX_REG_PAD10_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD10_RDE_S  2
+/** LP_IOMUX_REG_PAD10_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD10_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD10_RUE_M  (LP_IOMUX_REG_PAD10_RUE_V << LP_IOMUX_REG_PAD10_RUE_S)
+#define LP_IOMUX_REG_PAD10_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD10_RUE_S  3
+/** LP_IOMUX_REG_PAD10_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD10_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD10_MUX_SEL_M  (LP_IOMUX_REG_PAD10_MUX_SEL_V << LP_IOMUX_REG_PAD10_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD10_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD10_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD10_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD10_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD10_FUN_SEL_M  (LP_IOMUX_REG_PAD10_FUN_SEL_V << LP_IOMUX_REG_PAD10_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD10_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD10_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD10_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD10_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD10_SLP_SEL_M  (LP_IOMUX_REG_PAD10_SLP_SEL_V << LP_IOMUX_REG_PAD10_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD10_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD10_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD10_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD10_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD10_SLP_IE_M  (LP_IOMUX_REG_PAD10_SLP_IE_V << LP_IOMUX_REG_PAD10_SLP_IE_S)
+#define LP_IOMUX_REG_PAD10_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD10_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD10_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD10_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD10_SLP_OE_M  (LP_IOMUX_REG_PAD10_SLP_OE_V << LP_IOMUX_REG_PAD10_SLP_OE_S)
+#define LP_IOMUX_REG_PAD10_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD10_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD10_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD10_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD10_FUN_IE_M  (LP_IOMUX_REG_PAD10_FUN_IE_V << LP_IOMUX_REG_PAD10_FUN_IE_S)
+#define LP_IOMUX_REG_PAD10_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD10_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD10_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD10_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD10_FILTER_EN_M  (LP_IOMUX_REG_PAD10_FILTER_EN_V << LP_IOMUX_REG_PAD10_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD10_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD10_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD11_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD11_REG (DR_REG_LP_IOMUX_BASE + 0x34)
+/** LP_IOMUX_REG_PAD11_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD11_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD11_DRV_M  (LP_IOMUX_REG_PAD11_DRV_V << LP_IOMUX_REG_PAD11_DRV_S)
+#define LP_IOMUX_REG_PAD11_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD11_DRV_S  0
+/** LP_IOMUX_REG_PAD11_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD11_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD11_RDE_M  (LP_IOMUX_REG_PAD11_RDE_V << LP_IOMUX_REG_PAD11_RDE_S)
+#define LP_IOMUX_REG_PAD11_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD11_RDE_S  2
+/** LP_IOMUX_REG_PAD11_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD11_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD11_RUE_M  (LP_IOMUX_REG_PAD11_RUE_V << LP_IOMUX_REG_PAD11_RUE_S)
+#define LP_IOMUX_REG_PAD11_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD11_RUE_S  3
+/** LP_IOMUX_REG_PAD11_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD11_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD11_MUX_SEL_M  (LP_IOMUX_REG_PAD11_MUX_SEL_V << LP_IOMUX_REG_PAD11_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD11_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD11_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD11_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD11_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD11_FUN_SEL_M  (LP_IOMUX_REG_PAD11_FUN_SEL_V << LP_IOMUX_REG_PAD11_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD11_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD11_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD11_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD11_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD11_SLP_SEL_M  (LP_IOMUX_REG_PAD11_SLP_SEL_V << LP_IOMUX_REG_PAD11_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD11_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD11_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD11_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD11_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD11_SLP_IE_M  (LP_IOMUX_REG_PAD11_SLP_IE_V << LP_IOMUX_REG_PAD11_SLP_IE_S)
+#define LP_IOMUX_REG_PAD11_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD11_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD11_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD11_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD11_SLP_OE_M  (LP_IOMUX_REG_PAD11_SLP_OE_V << LP_IOMUX_REG_PAD11_SLP_OE_S)
+#define LP_IOMUX_REG_PAD11_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD11_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD11_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD11_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD11_FUN_IE_M  (LP_IOMUX_REG_PAD11_FUN_IE_V << LP_IOMUX_REG_PAD11_FUN_IE_S)
+#define LP_IOMUX_REG_PAD11_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD11_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD11_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD11_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD11_FILTER_EN_M  (LP_IOMUX_REG_PAD11_FILTER_EN_V << LP_IOMUX_REG_PAD11_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD11_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD11_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD120_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD120_REG (DR_REG_LP_IOMUX_BASE + 0x38)
+/** LP_IOMUX_REG_PAD12_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD12_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD12_DRV_M  (LP_IOMUX_REG_PAD12_DRV_V << LP_IOMUX_REG_PAD12_DRV_S)
+#define LP_IOMUX_REG_PAD12_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD12_DRV_S  0
+/** LP_IOMUX_REG_PAD12_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD12_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD12_RDE_M  (LP_IOMUX_REG_PAD12_RDE_V << LP_IOMUX_REG_PAD12_RDE_S)
+#define LP_IOMUX_REG_PAD12_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD12_RDE_S  2
+/** LP_IOMUX_REG_PAD12_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD12_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD12_RUE_M  (LP_IOMUX_REG_PAD12_RUE_V << LP_IOMUX_REG_PAD12_RUE_S)
+#define LP_IOMUX_REG_PAD12_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD12_RUE_S  3
+/** LP_IOMUX_REG_PAD12_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD12_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD12_MUX_SEL_M  (LP_IOMUX_REG_PAD12_MUX_SEL_V << LP_IOMUX_REG_PAD12_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD12_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD12_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD12_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD12_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD12_FUN_SEL_M  (LP_IOMUX_REG_PAD12_FUN_SEL_V << LP_IOMUX_REG_PAD12_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD12_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD12_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD12_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD12_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD12_SLP_SEL_M  (LP_IOMUX_REG_PAD12_SLP_SEL_V << LP_IOMUX_REG_PAD12_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD12_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD12_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD12_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD12_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD12_SLP_IE_M  (LP_IOMUX_REG_PAD12_SLP_IE_V << LP_IOMUX_REG_PAD12_SLP_IE_S)
+#define LP_IOMUX_REG_PAD12_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD12_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD12_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD12_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD12_SLP_OE_M  (LP_IOMUX_REG_PAD12_SLP_OE_V << LP_IOMUX_REG_PAD12_SLP_OE_S)
+#define LP_IOMUX_REG_PAD12_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD12_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD12_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD12_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD12_FUN_IE_M  (LP_IOMUX_REG_PAD12_FUN_IE_V << LP_IOMUX_REG_PAD12_FUN_IE_S)
+#define LP_IOMUX_REG_PAD12_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD12_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD12_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD12_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD12_FILTER_EN_M  (LP_IOMUX_REG_PAD12_FILTER_EN_V << LP_IOMUX_REG_PAD12_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD12_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD12_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD13_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD13_REG (DR_REG_LP_IOMUX_BASE + 0x3c)
+/** LP_IOMUX_REG_PAD13_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD13_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD13_DRV_M  (LP_IOMUX_REG_PAD13_DRV_V << LP_IOMUX_REG_PAD13_DRV_S)
+#define LP_IOMUX_REG_PAD13_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD13_DRV_S  0
+/** LP_IOMUX_REG_PAD13_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD13_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD13_RDE_M  (LP_IOMUX_REG_PAD13_RDE_V << LP_IOMUX_REG_PAD13_RDE_S)
+#define LP_IOMUX_REG_PAD13_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD13_RDE_S  2
+/** LP_IOMUX_REG_PAD13_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD13_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD13_RUE_M  (LP_IOMUX_REG_PAD13_RUE_V << LP_IOMUX_REG_PAD13_RUE_S)
+#define LP_IOMUX_REG_PAD13_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD13_RUE_S  3
+/** LP_IOMUX_REG_PAD13_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD13_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD13_MUX_SEL_M  (LP_IOMUX_REG_PAD13_MUX_SEL_V << LP_IOMUX_REG_PAD13_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD13_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD13_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD13_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD13_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD13_FUN_SEL_M  (LP_IOMUX_REG_PAD13_FUN_SEL_V << LP_IOMUX_REG_PAD13_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD13_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD13_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD13_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD13_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD13_SLP_SEL_M  (LP_IOMUX_REG_PAD13_SLP_SEL_V << LP_IOMUX_REG_PAD13_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD13_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD13_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD13_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD13_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD13_SLP_IE_M  (LP_IOMUX_REG_PAD13_SLP_IE_V << LP_IOMUX_REG_PAD13_SLP_IE_S)
+#define LP_IOMUX_REG_PAD13_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD13_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD13_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD13_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD13_SLP_OE_M  (LP_IOMUX_REG_PAD13_SLP_OE_V << LP_IOMUX_REG_PAD13_SLP_OE_S)
+#define LP_IOMUX_REG_PAD13_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD13_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD13_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD13_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD13_FUN_IE_M  (LP_IOMUX_REG_PAD13_FUN_IE_V << LP_IOMUX_REG_PAD13_FUN_IE_S)
+#define LP_IOMUX_REG_PAD13_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD13_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD13_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD13_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD13_FILTER_EN_M  (LP_IOMUX_REG_PAD13_FILTER_EN_V << LP_IOMUX_REG_PAD13_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD13_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD13_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD14_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD14_REG (DR_REG_LP_IOMUX_BASE + 0x40)
+/** LP_IOMUX_REG_PAD14_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD14_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD14_DRV_M  (LP_IOMUX_REG_PAD14_DRV_V << LP_IOMUX_REG_PAD14_DRV_S)
+#define LP_IOMUX_REG_PAD14_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD14_DRV_S  0
+/** LP_IOMUX_REG_PAD14_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD14_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD14_RDE_M  (LP_IOMUX_REG_PAD14_RDE_V << LP_IOMUX_REG_PAD14_RDE_S)
+#define LP_IOMUX_REG_PAD14_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD14_RDE_S  2
+/** LP_IOMUX_REG_PAD14_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD14_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD14_RUE_M  (LP_IOMUX_REG_PAD14_RUE_V << LP_IOMUX_REG_PAD14_RUE_S)
+#define LP_IOMUX_REG_PAD14_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD14_RUE_S  3
+/** LP_IOMUX_REG_PAD14_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD14_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD14_MUX_SEL_M  (LP_IOMUX_REG_PAD14_MUX_SEL_V << LP_IOMUX_REG_PAD14_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD14_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD14_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD14_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD14_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD14_FUN_SEL_M  (LP_IOMUX_REG_PAD14_FUN_SEL_V << LP_IOMUX_REG_PAD14_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD14_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD14_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD14_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD14_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD14_SLP_SEL_M  (LP_IOMUX_REG_PAD14_SLP_SEL_V << LP_IOMUX_REG_PAD14_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD14_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD14_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD14_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD14_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD14_SLP_IE_M  (LP_IOMUX_REG_PAD14_SLP_IE_V << LP_IOMUX_REG_PAD14_SLP_IE_S)
+#define LP_IOMUX_REG_PAD14_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD14_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD14_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD14_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD14_SLP_OE_M  (LP_IOMUX_REG_PAD14_SLP_OE_V << LP_IOMUX_REG_PAD14_SLP_OE_S)
+#define LP_IOMUX_REG_PAD14_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD14_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD14_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD14_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD14_FUN_IE_M  (LP_IOMUX_REG_PAD14_FUN_IE_V << LP_IOMUX_REG_PAD14_FUN_IE_S)
+#define LP_IOMUX_REG_PAD14_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD14_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD14_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD14_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD14_FILTER_EN_M  (LP_IOMUX_REG_PAD14_FILTER_EN_V << LP_IOMUX_REG_PAD14_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD14_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD14_FILTER_EN_S  11
+
+/** LP_IOMUX_PAD15_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_PAD15_REG (DR_REG_LP_IOMUX_BASE + 0x44)
+/** LP_IOMUX_REG_PAD15_DRV : R/W; bitpos: [1:0]; default: 2;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD15_DRV    0x00000003U
+#define LP_IOMUX_REG_PAD15_DRV_M  (LP_IOMUX_REG_PAD15_DRV_V << LP_IOMUX_REG_PAD15_DRV_S)
+#define LP_IOMUX_REG_PAD15_DRV_V  0x00000003U
+#define LP_IOMUX_REG_PAD15_DRV_S  0
+/** LP_IOMUX_REG_PAD15_RDE : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD15_RDE    (BIT(2))
+#define LP_IOMUX_REG_PAD15_RDE_M  (LP_IOMUX_REG_PAD15_RDE_V << LP_IOMUX_REG_PAD15_RDE_S)
+#define LP_IOMUX_REG_PAD15_RDE_V  0x00000001U
+#define LP_IOMUX_REG_PAD15_RDE_S  2
+/** LP_IOMUX_REG_PAD15_RUE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_PAD15_RUE    (BIT(3))
+#define LP_IOMUX_REG_PAD15_RUE_M  (LP_IOMUX_REG_PAD15_RUE_V << LP_IOMUX_REG_PAD15_RUE_S)
+#define LP_IOMUX_REG_PAD15_RUE_V  0x00000001U
+#define LP_IOMUX_REG_PAD15_RUE_S  3
+/** LP_IOMUX_REG_PAD15_MUX_SEL : R/W; bitpos: [4]; default: 0;
+ *  1:use LP GPIO,0: use digital GPIO
+ */
+#define LP_IOMUX_REG_PAD15_MUX_SEL    (BIT(4))
+#define LP_IOMUX_REG_PAD15_MUX_SEL_M  (LP_IOMUX_REG_PAD15_MUX_SEL_V << LP_IOMUX_REG_PAD15_MUX_SEL_S)
+#define LP_IOMUX_REG_PAD15_MUX_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD15_MUX_SEL_S  4
+/** LP_IOMUX_REG_PAD15_FUN_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  function sel
+ */
+#define LP_IOMUX_REG_PAD15_FUN_SEL    0x00000003U
+#define LP_IOMUX_REG_PAD15_FUN_SEL_M  (LP_IOMUX_REG_PAD15_FUN_SEL_V << LP_IOMUX_REG_PAD15_FUN_SEL_S)
+#define LP_IOMUX_REG_PAD15_FUN_SEL_V  0x00000003U
+#define LP_IOMUX_REG_PAD15_FUN_SEL_S  5
+/** LP_IOMUX_REG_PAD15_SLP_SEL : R/W; bitpos: [7]; default: 0;
+ *  1: enable sleep mode during sleep,0: no sleep mode
+ */
+#define LP_IOMUX_REG_PAD15_SLP_SEL    (BIT(7))
+#define LP_IOMUX_REG_PAD15_SLP_SEL_M  (LP_IOMUX_REG_PAD15_SLP_SEL_V << LP_IOMUX_REG_PAD15_SLP_SEL_S)
+#define LP_IOMUX_REG_PAD15_SLP_SEL_V  0x00000001U
+#define LP_IOMUX_REG_PAD15_SLP_SEL_S  7
+/** LP_IOMUX_REG_PAD15_SLP_IE : R/W; bitpos: [8]; default: 0;
+ *  input enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD15_SLP_IE    (BIT(8))
+#define LP_IOMUX_REG_PAD15_SLP_IE_M  (LP_IOMUX_REG_PAD15_SLP_IE_V << LP_IOMUX_REG_PAD15_SLP_IE_S)
+#define LP_IOMUX_REG_PAD15_SLP_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD15_SLP_IE_S  8
+/** LP_IOMUX_REG_PAD15_SLP_OE : R/W; bitpos: [9]; default: 0;
+ *  output enable in sleep mode
+ */
+#define LP_IOMUX_REG_PAD15_SLP_OE    (BIT(9))
+#define LP_IOMUX_REG_PAD15_SLP_OE_M  (LP_IOMUX_REG_PAD15_SLP_OE_V << LP_IOMUX_REG_PAD15_SLP_OE_S)
+#define LP_IOMUX_REG_PAD15_SLP_OE_V  0x00000001U
+#define LP_IOMUX_REG_PAD15_SLP_OE_S  9
+/** LP_IOMUX_REG_PAD15_FUN_IE : R/W; bitpos: [10]; default: 0;
+ *  input enable in work mode
+ */
+#define LP_IOMUX_REG_PAD15_FUN_IE    (BIT(10))
+#define LP_IOMUX_REG_PAD15_FUN_IE_M  (LP_IOMUX_REG_PAD15_FUN_IE_V << LP_IOMUX_REG_PAD15_FUN_IE_S)
+#define LP_IOMUX_REG_PAD15_FUN_IE_V  0x00000001U
+#define LP_IOMUX_REG_PAD15_FUN_IE_S  10
+/** LP_IOMUX_REG_PAD15_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define LP_IOMUX_REG_PAD15_FILTER_EN    (BIT(11))
+#define LP_IOMUX_REG_PAD15_FILTER_EN_M  (LP_IOMUX_REG_PAD15_FILTER_EN_V << LP_IOMUX_REG_PAD15_FILTER_EN_S)
+#define LP_IOMUX_REG_PAD15_FILTER_EN_V  0x00000001U
+#define LP_IOMUX_REG_PAD15_FILTER_EN_S  11
+
+/** LP_IOMUX_EXT_WAKEUP0_SEL_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_EXT_WAKEUP0_SEL_REG (DR_REG_LP_IOMUX_BASE + 0x48)
+/** LP_IOMUX_REG_XTL_EXT_CTR_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  select LP GPIO 0 ~ 15 to control XTAL
+ */
+#define LP_IOMUX_REG_XTL_EXT_CTR_SEL    0x0000001FU
+#define LP_IOMUX_REG_XTL_EXT_CTR_SEL_M  (LP_IOMUX_REG_XTL_EXT_CTR_SEL_V << LP_IOMUX_REG_XTL_EXT_CTR_SEL_S)
+#define LP_IOMUX_REG_XTL_EXT_CTR_SEL_V  0x0000001FU
+#define LP_IOMUX_REG_XTL_EXT_CTR_SEL_S  0
+/** LP_IOMUX_REG_EXT_WAKEUP0_SEL : R/W; bitpos: [9:5]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_EXT_WAKEUP0_SEL    0x0000001FU
+#define LP_IOMUX_REG_EXT_WAKEUP0_SEL_M  (LP_IOMUX_REG_EXT_WAKEUP0_SEL_V << LP_IOMUX_REG_EXT_WAKEUP0_SEL_S)
+#define LP_IOMUX_REG_EXT_WAKEUP0_SEL_V  0x0000001FU
+#define LP_IOMUX_REG_EXT_WAKEUP0_SEL_S  5
+
+/** LP_IOMUX_LP_PAD_HOLD_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_LP_PAD_HOLD_REG (DR_REG_LP_IOMUX_BASE + 0x4c)
+/** LP_IOMUX_REG_LP_GPIO_HOLD : R/W; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_LP_GPIO_HOLD    0x0000FFFFU
+#define LP_IOMUX_REG_LP_GPIO_HOLD_M  (LP_IOMUX_REG_LP_GPIO_HOLD_V << LP_IOMUX_REG_LP_GPIO_HOLD_S)
+#define LP_IOMUX_REG_LP_GPIO_HOLD_V  0x0000FFFFU
+#define LP_IOMUX_REG_LP_GPIO_HOLD_S  0
+
+/** LP_IOMUX_LP_PAD_HYS_REG register
+ *  Reserved
+ */
+#define LP_IOMUX_LP_PAD_HYS_REG (DR_REG_LP_IOMUX_BASE + 0x50)
+/** LP_IOMUX_REG_LP_GPIO_HYS : R/W; bitpos: [15:0]; default: 0;
+ *  Reserved
+ */
+#define LP_IOMUX_REG_LP_GPIO_HYS    0x0000FFFFU
+#define LP_IOMUX_REG_LP_GPIO_HYS_M  (LP_IOMUX_REG_LP_GPIO_HYS_V << LP_IOMUX_REG_LP_GPIO_HYS_S)
+#define LP_IOMUX_REG_LP_GPIO_HYS_V  0x0000FFFFU
+#define LP_IOMUX_REG_LP_GPIO_HYS_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h
new file mode 100644
index 0000000000..740839aecd
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h
@@ -0,0 +1,166 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_en */
+/** Type of clk_en register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_iomux_clk_en_reg_t;
+
+
+/** Group: ver_date */
+/** Type of ver_date register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [27:0]; default: 2294547;
+         *  Reserved
+         */
+        uint32_t reg_ver_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_iomux_ver_date_reg_t;
+
+
+/** Group: pad */
+/** Type of pad register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** drv : R/W; bitpos: [1:0]; default: 2;
+         *  Reserved
+         */
+        uint32_t drv:2;
+        /** rde : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t rde:1;
+        /** rue : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t rue:1;
+        /** mux_sel : R/W; bitpos: [4]; default: 0;
+         *  1:use LP GPIO,0: use digital GPIO
+         */
+        uint32_t mux_sel:1;
+        /** fun_sel : R/W; bitpos: [6:5]; default: 0;
+         *  function sel
+         */
+        uint32_t fun_sel:2;
+        /** slp_sel : R/W; bitpos: [7]; default: 0;
+         *  1: enable sleep mode during sleep,0: no sleep mode
+         */
+        uint32_t slp_sel:1;
+        /** slp_ie : R/W; bitpos: [8]; default: 0;
+         *  input enable in sleep mode
+         */
+        uint32_t slp_ie:1;
+        /** slp_oe : R/W; bitpos: [9]; default: 0;
+         *  output enable in sleep mode
+         */
+        uint32_t slp_oe:1;
+        /** fun_ie : R/W; bitpos: [10]; default: 0;
+         *  input enable in work mode
+        */
+        uint32_t fun_ie:1;
+        /** filter_en : R/W; bitpos: [11]; default: 0;
+         *  need des
+         */
+        uint32_t filter_en:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_iomux_pad_reg_t;
+
+
+/** Group: ext_wakeup0_sel */
+/** Type of ext_wakeup0_sel register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_xtl_ext_ctr_sel : R/W; bitpos: [4:0]; default: 0;
+         *  select LP GPIO 0 ~ 15 to control XTAL
+         */
+        uint32_t reg_xtl_ext_ctr_sel:5;
+        /** reg_ext_wakeup0_sel : R/W; bitpos: [9:5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_ext_wakeup0_sel:5;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} lp_iomux_ext_wakeup0_sel_reg_t;
+
+
+/** Group: lp_pad_hold */
+/** Type of lp_pad_hold register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_lp_gpio_hold : R/W; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lp_gpio_hold:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_iomux_lp_pad_hold_reg_t;
+
+
+/** Group: lp_pad_hys */
+/** Type of lp_pad_hys register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_lp_gpio_hys : R/W; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lp_gpio_hys:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_iomux_lp_pad_hys_reg_t;
+
+
+typedef struct lp_iomux_dev_t {
+    volatile lp_iomux_clk_en_reg_t clk_en;
+    volatile lp_iomux_ver_date_reg_t ver_date;
+    volatile lp_iomux_pad_reg_t pad[16];
+    volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel;
+    volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold;
+    volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys;
+} lp_iomux_dev_t;
+
+extern lp_iomux_dev_t LP_IOMUX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_iomux_dev_t) == 0x54, "Invalid size of lp_iomux_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_mailbox_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_mailbox_reg.h
new file mode 100644
index 0000000000..07ebf89847
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_mailbox_reg.h
@@ -0,0 +1,1156 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MB_MASSEGE_0_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_0_REG (DR_REG_MB_BASE + 0x0)
+/** MB_MASSEGE_0 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_0    0xFFFFFFFFU
+#define MB_MASSEGE_0_M  (MB_MASSEGE_0_V << MB_MASSEGE_0_S)
+#define MB_MASSEGE_0_V  0xFFFFFFFFU
+#define MB_MASSEGE_0_S  0
+
+/** MB_MASSEGE_1_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_1_REG (DR_REG_MB_BASE + 0x4)
+/** MB_MASSEGE_1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_1    0xFFFFFFFFU
+#define MB_MASSEGE_1_M  (MB_MASSEGE_1_V << MB_MASSEGE_1_S)
+#define MB_MASSEGE_1_V  0xFFFFFFFFU
+#define MB_MASSEGE_1_S  0
+
+/** MB_MASSEGE_2_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_2_REG (DR_REG_MB_BASE + 0x8)
+/** MB_MASSEGE_2 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_2    0xFFFFFFFFU
+#define MB_MASSEGE_2_M  (MB_MASSEGE_2_V << MB_MASSEGE_2_S)
+#define MB_MASSEGE_2_V  0xFFFFFFFFU
+#define MB_MASSEGE_2_S  0
+
+/** MB_MASSEGE_3_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_3_REG (DR_REG_MB_BASE + 0xc)
+/** MB_MASSEGE_3 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_3    0xFFFFFFFFU
+#define MB_MASSEGE_3_M  (MB_MASSEGE_3_V << MB_MASSEGE_3_S)
+#define MB_MASSEGE_3_V  0xFFFFFFFFU
+#define MB_MASSEGE_3_S  0
+
+/** MB_MASSEGE_4_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_4_REG (DR_REG_MB_BASE + 0x10)
+/** MB_MASSEGE_4 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_4    0xFFFFFFFFU
+#define MB_MASSEGE_4_M  (MB_MASSEGE_4_V << MB_MASSEGE_4_S)
+#define MB_MASSEGE_4_V  0xFFFFFFFFU
+#define MB_MASSEGE_4_S  0
+
+/** MB_MASSEGE_5_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_5_REG (DR_REG_MB_BASE + 0x14)
+/** MB_MASSEGE_5 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_5    0xFFFFFFFFU
+#define MB_MASSEGE_5_M  (MB_MASSEGE_5_V << MB_MASSEGE_5_S)
+#define MB_MASSEGE_5_V  0xFFFFFFFFU
+#define MB_MASSEGE_5_S  0
+
+/** MB_MASSEGE_6_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_6_REG (DR_REG_MB_BASE + 0x18)
+/** MB_MASSEGE_6 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_6    0xFFFFFFFFU
+#define MB_MASSEGE_6_M  (MB_MASSEGE_6_V << MB_MASSEGE_6_S)
+#define MB_MASSEGE_6_V  0xFFFFFFFFU
+#define MB_MASSEGE_6_S  0
+
+/** MB_MASSEGE_7_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_7_REG (DR_REG_MB_BASE + 0x1c)
+/** MB_MASSEGE_7 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_7    0xFFFFFFFFU
+#define MB_MASSEGE_7_M  (MB_MASSEGE_7_V << MB_MASSEGE_7_S)
+#define MB_MASSEGE_7_V  0xFFFFFFFFU
+#define MB_MASSEGE_7_S  0
+
+/** MB_MASSEGE_8_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_8_REG (DR_REG_MB_BASE + 0x20)
+/** MB_MASSEGE_8 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_8    0xFFFFFFFFU
+#define MB_MASSEGE_8_M  (MB_MASSEGE_8_V << MB_MASSEGE_8_S)
+#define MB_MASSEGE_8_V  0xFFFFFFFFU
+#define MB_MASSEGE_8_S  0
+
+/** MB_MASSEGE_9_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_9_REG (DR_REG_MB_BASE + 0x24)
+/** MB_MASSEGE_9 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_9    0xFFFFFFFFU
+#define MB_MASSEGE_9_M  (MB_MASSEGE_9_V << MB_MASSEGE_9_S)
+#define MB_MASSEGE_9_V  0xFFFFFFFFU
+#define MB_MASSEGE_9_S  0
+
+/** MB_MASSEGE_10_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_10_REG (DR_REG_MB_BASE + 0x28)
+/** MB_MASSEGE_10 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_10    0xFFFFFFFFU
+#define MB_MASSEGE_10_M  (MB_MASSEGE_10_V << MB_MASSEGE_10_S)
+#define MB_MASSEGE_10_V  0xFFFFFFFFU
+#define MB_MASSEGE_10_S  0
+
+/** MB_MASSEGE_11_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_11_REG (DR_REG_MB_BASE + 0x2c)
+/** MB_MASSEGE_11 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_11    0xFFFFFFFFU
+#define MB_MASSEGE_11_M  (MB_MASSEGE_11_V << MB_MASSEGE_11_S)
+#define MB_MASSEGE_11_V  0xFFFFFFFFU
+#define MB_MASSEGE_11_S  0
+
+/** MB_MASSEGE_12_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_12_REG (DR_REG_MB_BASE + 0x30)
+/** MB_MASSEGE_12 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_12    0xFFFFFFFFU
+#define MB_MASSEGE_12_M  (MB_MASSEGE_12_V << MB_MASSEGE_12_S)
+#define MB_MASSEGE_12_V  0xFFFFFFFFU
+#define MB_MASSEGE_12_S  0
+
+/** MB_MASSEGE_13_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_13_REG (DR_REG_MB_BASE + 0x34)
+/** MB_MASSEGE_13 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_13    0xFFFFFFFFU
+#define MB_MASSEGE_13_M  (MB_MASSEGE_13_V << MB_MASSEGE_13_S)
+#define MB_MASSEGE_13_V  0xFFFFFFFFU
+#define MB_MASSEGE_13_S  0
+
+/** MB_MASSEGE_14_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_14_REG (DR_REG_MB_BASE + 0x38)
+/** MB_MASSEGE_14 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_14    0xFFFFFFFFU
+#define MB_MASSEGE_14_M  (MB_MASSEGE_14_V << MB_MASSEGE_14_S)
+#define MB_MASSEGE_14_V  0xFFFFFFFFU
+#define MB_MASSEGE_14_S  0
+
+/** MB_MASSEGE_15_REG register
+ *  need_des
+ */
+#define MB_MASSEGE_15_REG (DR_REG_MB_BASE + 0x3c)
+/** MB_MASSEGE_15 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define MB_MASSEGE_15    0xFFFFFFFFU
+#define MB_MASSEGE_15_M  (MB_MASSEGE_15_V << MB_MASSEGE_15_S)
+#define MB_MASSEGE_15_V  0xFFFFFFFFU
+#define MB_MASSEGE_15_S  0
+
+/** MB_LP_INT_RAW_REG register
+ *  need_des
+ */
+#define MB_LP_INT_RAW_REG (DR_REG_MB_BASE + 0x40)
+/** MB_LP_0_INT_RAW : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define MB_LP_0_INT_RAW    (BIT(0))
+#define MB_LP_0_INT_RAW_M  (MB_LP_0_INT_RAW_V << MB_LP_0_INT_RAW_S)
+#define MB_LP_0_INT_RAW_V  0x00000001U
+#define MB_LP_0_INT_RAW_S  0
+/** MB_LP_1_INT_RAW : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define MB_LP_1_INT_RAW    (BIT(1))
+#define MB_LP_1_INT_RAW_M  (MB_LP_1_INT_RAW_V << MB_LP_1_INT_RAW_S)
+#define MB_LP_1_INT_RAW_V  0x00000001U
+#define MB_LP_1_INT_RAW_S  1
+/** MB_LP_2_INT_RAW : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define MB_LP_2_INT_RAW    (BIT(2))
+#define MB_LP_2_INT_RAW_M  (MB_LP_2_INT_RAW_V << MB_LP_2_INT_RAW_S)
+#define MB_LP_2_INT_RAW_V  0x00000001U
+#define MB_LP_2_INT_RAW_S  2
+/** MB_LP_3_INT_RAW : RO; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define MB_LP_3_INT_RAW    (BIT(3))
+#define MB_LP_3_INT_RAW_M  (MB_LP_3_INT_RAW_V << MB_LP_3_INT_RAW_S)
+#define MB_LP_3_INT_RAW_V  0x00000001U
+#define MB_LP_3_INT_RAW_S  3
+/** MB_LP_4_INT_RAW : RO; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define MB_LP_4_INT_RAW    (BIT(4))
+#define MB_LP_4_INT_RAW_M  (MB_LP_4_INT_RAW_V << MB_LP_4_INT_RAW_S)
+#define MB_LP_4_INT_RAW_V  0x00000001U
+#define MB_LP_4_INT_RAW_S  4
+/** MB_LP_5_INT_RAW : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define MB_LP_5_INT_RAW    (BIT(5))
+#define MB_LP_5_INT_RAW_M  (MB_LP_5_INT_RAW_V << MB_LP_5_INT_RAW_S)
+#define MB_LP_5_INT_RAW_V  0x00000001U
+#define MB_LP_5_INT_RAW_S  5
+/** MB_LP_6_INT_RAW : RO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define MB_LP_6_INT_RAW    (BIT(6))
+#define MB_LP_6_INT_RAW_M  (MB_LP_6_INT_RAW_V << MB_LP_6_INT_RAW_S)
+#define MB_LP_6_INT_RAW_V  0x00000001U
+#define MB_LP_6_INT_RAW_S  6
+/** MB_LP_7_INT_RAW : RO; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define MB_LP_7_INT_RAW    (BIT(7))
+#define MB_LP_7_INT_RAW_M  (MB_LP_7_INT_RAW_V << MB_LP_7_INT_RAW_S)
+#define MB_LP_7_INT_RAW_V  0x00000001U
+#define MB_LP_7_INT_RAW_S  7
+/** MB_LP_8_INT_RAW : RO; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define MB_LP_8_INT_RAW    (BIT(8))
+#define MB_LP_8_INT_RAW_M  (MB_LP_8_INT_RAW_V << MB_LP_8_INT_RAW_S)
+#define MB_LP_8_INT_RAW_V  0x00000001U
+#define MB_LP_8_INT_RAW_S  8
+/** MB_LP_9_INT_RAW : RO; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define MB_LP_9_INT_RAW    (BIT(9))
+#define MB_LP_9_INT_RAW_M  (MB_LP_9_INT_RAW_V << MB_LP_9_INT_RAW_S)
+#define MB_LP_9_INT_RAW_V  0x00000001U
+#define MB_LP_9_INT_RAW_S  9
+/** MB_LP_10_INT_RAW : RO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define MB_LP_10_INT_RAW    (BIT(10))
+#define MB_LP_10_INT_RAW_M  (MB_LP_10_INT_RAW_V << MB_LP_10_INT_RAW_S)
+#define MB_LP_10_INT_RAW_V  0x00000001U
+#define MB_LP_10_INT_RAW_S  10
+/** MB_LP_11_INT_RAW : RO; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define MB_LP_11_INT_RAW    (BIT(11))
+#define MB_LP_11_INT_RAW_M  (MB_LP_11_INT_RAW_V << MB_LP_11_INT_RAW_S)
+#define MB_LP_11_INT_RAW_V  0x00000001U
+#define MB_LP_11_INT_RAW_S  11
+/** MB_LP_12_INT_RAW : RO; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define MB_LP_12_INT_RAW    (BIT(12))
+#define MB_LP_12_INT_RAW_M  (MB_LP_12_INT_RAW_V << MB_LP_12_INT_RAW_S)
+#define MB_LP_12_INT_RAW_V  0x00000001U
+#define MB_LP_12_INT_RAW_S  12
+/** MB_LP_13_INT_RAW : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define MB_LP_13_INT_RAW    (BIT(13))
+#define MB_LP_13_INT_RAW_M  (MB_LP_13_INT_RAW_V << MB_LP_13_INT_RAW_S)
+#define MB_LP_13_INT_RAW_V  0x00000001U
+#define MB_LP_13_INT_RAW_S  13
+/** MB_LP_14_INT_RAW : RO; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define MB_LP_14_INT_RAW    (BIT(14))
+#define MB_LP_14_INT_RAW_M  (MB_LP_14_INT_RAW_V << MB_LP_14_INT_RAW_S)
+#define MB_LP_14_INT_RAW_V  0x00000001U
+#define MB_LP_14_INT_RAW_S  14
+/** MB_LP_15_INT_RAW : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define MB_LP_15_INT_RAW    (BIT(15))
+#define MB_LP_15_INT_RAW_M  (MB_LP_15_INT_RAW_V << MB_LP_15_INT_RAW_S)
+#define MB_LP_15_INT_RAW_V  0x00000001U
+#define MB_LP_15_INT_RAW_S  15
+
+/** MB_LP_INT_ST_REG register
+ *  need_des
+ */
+#define MB_LP_INT_ST_REG (DR_REG_MB_BASE + 0x44)
+/** MB_LP_0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define MB_LP_0_INT_ST    (BIT(0))
+#define MB_LP_0_INT_ST_M  (MB_LP_0_INT_ST_V << MB_LP_0_INT_ST_S)
+#define MB_LP_0_INT_ST_V  0x00000001U
+#define MB_LP_0_INT_ST_S  0
+/** MB_LP_1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define MB_LP_1_INT_ST    (BIT(1))
+#define MB_LP_1_INT_ST_M  (MB_LP_1_INT_ST_V << MB_LP_1_INT_ST_S)
+#define MB_LP_1_INT_ST_V  0x00000001U
+#define MB_LP_1_INT_ST_S  1
+/** MB_LP_2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define MB_LP_2_INT_ST    (BIT(2))
+#define MB_LP_2_INT_ST_M  (MB_LP_2_INT_ST_V << MB_LP_2_INT_ST_S)
+#define MB_LP_2_INT_ST_V  0x00000001U
+#define MB_LP_2_INT_ST_S  2
+/** MB_LP_3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define MB_LP_3_INT_ST    (BIT(3))
+#define MB_LP_3_INT_ST_M  (MB_LP_3_INT_ST_V << MB_LP_3_INT_ST_S)
+#define MB_LP_3_INT_ST_V  0x00000001U
+#define MB_LP_3_INT_ST_S  3
+/** MB_LP_4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define MB_LP_4_INT_ST    (BIT(4))
+#define MB_LP_4_INT_ST_M  (MB_LP_4_INT_ST_V << MB_LP_4_INT_ST_S)
+#define MB_LP_4_INT_ST_V  0x00000001U
+#define MB_LP_4_INT_ST_S  4
+/** MB_LP_5_INT_ST : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define MB_LP_5_INT_ST    (BIT(5))
+#define MB_LP_5_INT_ST_M  (MB_LP_5_INT_ST_V << MB_LP_5_INT_ST_S)
+#define MB_LP_5_INT_ST_V  0x00000001U
+#define MB_LP_5_INT_ST_S  5
+/** MB_LP_6_INT_ST : RO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define MB_LP_6_INT_ST    (BIT(6))
+#define MB_LP_6_INT_ST_M  (MB_LP_6_INT_ST_V << MB_LP_6_INT_ST_S)
+#define MB_LP_6_INT_ST_V  0x00000001U
+#define MB_LP_6_INT_ST_S  6
+/** MB_LP_7_INT_ST : RO; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define MB_LP_7_INT_ST    (BIT(7))
+#define MB_LP_7_INT_ST_M  (MB_LP_7_INT_ST_V << MB_LP_7_INT_ST_S)
+#define MB_LP_7_INT_ST_V  0x00000001U
+#define MB_LP_7_INT_ST_S  7
+/** MB_LP_8_INT_ST : RO; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define MB_LP_8_INT_ST    (BIT(8))
+#define MB_LP_8_INT_ST_M  (MB_LP_8_INT_ST_V << MB_LP_8_INT_ST_S)
+#define MB_LP_8_INT_ST_V  0x00000001U
+#define MB_LP_8_INT_ST_S  8
+/** MB_LP_9_INT_ST : RO; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define MB_LP_9_INT_ST    (BIT(9))
+#define MB_LP_9_INT_ST_M  (MB_LP_9_INT_ST_V << MB_LP_9_INT_ST_S)
+#define MB_LP_9_INT_ST_V  0x00000001U
+#define MB_LP_9_INT_ST_S  9
+/** MB_LP_10_INT_ST : RO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define MB_LP_10_INT_ST    (BIT(10))
+#define MB_LP_10_INT_ST_M  (MB_LP_10_INT_ST_V << MB_LP_10_INT_ST_S)
+#define MB_LP_10_INT_ST_V  0x00000001U
+#define MB_LP_10_INT_ST_S  10
+/** MB_LP_11_INT_ST : RO; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define MB_LP_11_INT_ST    (BIT(11))
+#define MB_LP_11_INT_ST_M  (MB_LP_11_INT_ST_V << MB_LP_11_INT_ST_S)
+#define MB_LP_11_INT_ST_V  0x00000001U
+#define MB_LP_11_INT_ST_S  11
+/** MB_LP_12_INT_ST : RO; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define MB_LP_12_INT_ST    (BIT(12))
+#define MB_LP_12_INT_ST_M  (MB_LP_12_INT_ST_V << MB_LP_12_INT_ST_S)
+#define MB_LP_12_INT_ST_V  0x00000001U
+#define MB_LP_12_INT_ST_S  12
+/** MB_LP_13_INT_ST : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define MB_LP_13_INT_ST    (BIT(13))
+#define MB_LP_13_INT_ST_M  (MB_LP_13_INT_ST_V << MB_LP_13_INT_ST_S)
+#define MB_LP_13_INT_ST_V  0x00000001U
+#define MB_LP_13_INT_ST_S  13
+/** MB_LP_14_INT_ST : RO; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define MB_LP_14_INT_ST    (BIT(14))
+#define MB_LP_14_INT_ST_M  (MB_LP_14_INT_ST_V << MB_LP_14_INT_ST_S)
+#define MB_LP_14_INT_ST_V  0x00000001U
+#define MB_LP_14_INT_ST_S  14
+/** MB_LP_15_INT_ST : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define MB_LP_15_INT_ST    (BIT(15))
+#define MB_LP_15_INT_ST_M  (MB_LP_15_INT_ST_V << MB_LP_15_INT_ST_S)
+#define MB_LP_15_INT_ST_V  0x00000001U
+#define MB_LP_15_INT_ST_S  15
+
+/** MB_LP_INT_ENA_REG register
+ *  need_des
+ */
+#define MB_LP_INT_ENA_REG (DR_REG_MB_BASE + 0x48)
+/** MB_LP_0_INT_ENA : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define MB_LP_0_INT_ENA    (BIT(0))
+#define MB_LP_0_INT_ENA_M  (MB_LP_0_INT_ENA_V << MB_LP_0_INT_ENA_S)
+#define MB_LP_0_INT_ENA_V  0x00000001U
+#define MB_LP_0_INT_ENA_S  0
+/** MB_LP_1_INT_ENA : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define MB_LP_1_INT_ENA    (BIT(1))
+#define MB_LP_1_INT_ENA_M  (MB_LP_1_INT_ENA_V << MB_LP_1_INT_ENA_S)
+#define MB_LP_1_INT_ENA_V  0x00000001U
+#define MB_LP_1_INT_ENA_S  1
+/** MB_LP_2_INT_ENA : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define MB_LP_2_INT_ENA    (BIT(2))
+#define MB_LP_2_INT_ENA_M  (MB_LP_2_INT_ENA_V << MB_LP_2_INT_ENA_S)
+#define MB_LP_2_INT_ENA_V  0x00000001U
+#define MB_LP_2_INT_ENA_S  2
+/** MB_LP_3_INT_ENA : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define MB_LP_3_INT_ENA    (BIT(3))
+#define MB_LP_3_INT_ENA_M  (MB_LP_3_INT_ENA_V << MB_LP_3_INT_ENA_S)
+#define MB_LP_3_INT_ENA_V  0x00000001U
+#define MB_LP_3_INT_ENA_S  3
+/** MB_LP_4_INT_ENA : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define MB_LP_4_INT_ENA    (BIT(4))
+#define MB_LP_4_INT_ENA_M  (MB_LP_4_INT_ENA_V << MB_LP_4_INT_ENA_S)
+#define MB_LP_4_INT_ENA_V  0x00000001U
+#define MB_LP_4_INT_ENA_S  4
+/** MB_LP_5_INT_ENA : R/W; bitpos: [5]; default: 1;
+ *  need_des
+ */
+#define MB_LP_5_INT_ENA    (BIT(5))
+#define MB_LP_5_INT_ENA_M  (MB_LP_5_INT_ENA_V << MB_LP_5_INT_ENA_S)
+#define MB_LP_5_INT_ENA_V  0x00000001U
+#define MB_LP_5_INT_ENA_S  5
+/** MB_LP_6_INT_ENA : R/W; bitpos: [6]; default: 1;
+ *  need_des
+ */
+#define MB_LP_6_INT_ENA    (BIT(6))
+#define MB_LP_6_INT_ENA_M  (MB_LP_6_INT_ENA_V << MB_LP_6_INT_ENA_S)
+#define MB_LP_6_INT_ENA_V  0x00000001U
+#define MB_LP_6_INT_ENA_S  6
+/** MB_LP_7_INT_ENA : R/W; bitpos: [7]; default: 1;
+ *  need_des
+ */
+#define MB_LP_7_INT_ENA    (BIT(7))
+#define MB_LP_7_INT_ENA_M  (MB_LP_7_INT_ENA_V << MB_LP_7_INT_ENA_S)
+#define MB_LP_7_INT_ENA_V  0x00000001U
+#define MB_LP_7_INT_ENA_S  7
+/** MB_LP_8_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define MB_LP_8_INT_ENA    (BIT(8))
+#define MB_LP_8_INT_ENA_M  (MB_LP_8_INT_ENA_V << MB_LP_8_INT_ENA_S)
+#define MB_LP_8_INT_ENA_V  0x00000001U
+#define MB_LP_8_INT_ENA_S  8
+/** MB_LP_9_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define MB_LP_9_INT_ENA    (BIT(9))
+#define MB_LP_9_INT_ENA_M  (MB_LP_9_INT_ENA_V << MB_LP_9_INT_ENA_S)
+#define MB_LP_9_INT_ENA_V  0x00000001U
+#define MB_LP_9_INT_ENA_S  9
+/** MB_LP_10_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define MB_LP_10_INT_ENA    (BIT(10))
+#define MB_LP_10_INT_ENA_M  (MB_LP_10_INT_ENA_V << MB_LP_10_INT_ENA_S)
+#define MB_LP_10_INT_ENA_V  0x00000001U
+#define MB_LP_10_INT_ENA_S  10
+/** MB_LP_11_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define MB_LP_11_INT_ENA    (BIT(11))
+#define MB_LP_11_INT_ENA_M  (MB_LP_11_INT_ENA_V << MB_LP_11_INT_ENA_S)
+#define MB_LP_11_INT_ENA_V  0x00000001U
+#define MB_LP_11_INT_ENA_S  11
+/** MB_LP_12_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define MB_LP_12_INT_ENA    (BIT(12))
+#define MB_LP_12_INT_ENA_M  (MB_LP_12_INT_ENA_V << MB_LP_12_INT_ENA_S)
+#define MB_LP_12_INT_ENA_V  0x00000001U
+#define MB_LP_12_INT_ENA_S  12
+/** MB_LP_13_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define MB_LP_13_INT_ENA    (BIT(13))
+#define MB_LP_13_INT_ENA_M  (MB_LP_13_INT_ENA_V << MB_LP_13_INT_ENA_S)
+#define MB_LP_13_INT_ENA_V  0x00000001U
+#define MB_LP_13_INT_ENA_S  13
+/** MB_LP_14_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define MB_LP_14_INT_ENA    (BIT(14))
+#define MB_LP_14_INT_ENA_M  (MB_LP_14_INT_ENA_V << MB_LP_14_INT_ENA_S)
+#define MB_LP_14_INT_ENA_V  0x00000001U
+#define MB_LP_14_INT_ENA_S  14
+/** MB_LP_15_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define MB_LP_15_INT_ENA    (BIT(15))
+#define MB_LP_15_INT_ENA_M  (MB_LP_15_INT_ENA_V << MB_LP_15_INT_ENA_S)
+#define MB_LP_15_INT_ENA_V  0x00000001U
+#define MB_LP_15_INT_ENA_S  15
+
+/** MB_LP_INT_CLR_REG register
+ *  need_des
+ */
+#define MB_LP_INT_CLR_REG (DR_REG_MB_BASE + 0x4c)
+/** MB_LP_0_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define MB_LP_0_INT_CLR    (BIT(0))
+#define MB_LP_0_INT_CLR_M  (MB_LP_0_INT_CLR_V << MB_LP_0_INT_CLR_S)
+#define MB_LP_0_INT_CLR_V  0x00000001U
+#define MB_LP_0_INT_CLR_S  0
+/** MB_LP_1_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define MB_LP_1_INT_CLR    (BIT(1))
+#define MB_LP_1_INT_CLR_M  (MB_LP_1_INT_CLR_V << MB_LP_1_INT_CLR_S)
+#define MB_LP_1_INT_CLR_V  0x00000001U
+#define MB_LP_1_INT_CLR_S  1
+/** MB_LP_2_INT_CLR : WO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define MB_LP_2_INT_CLR    (BIT(2))
+#define MB_LP_2_INT_CLR_M  (MB_LP_2_INT_CLR_V << MB_LP_2_INT_CLR_S)
+#define MB_LP_2_INT_CLR_V  0x00000001U
+#define MB_LP_2_INT_CLR_S  2
+/** MB_LP_3_INT_CLR : WO; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define MB_LP_3_INT_CLR    (BIT(3))
+#define MB_LP_3_INT_CLR_M  (MB_LP_3_INT_CLR_V << MB_LP_3_INT_CLR_S)
+#define MB_LP_3_INT_CLR_V  0x00000001U
+#define MB_LP_3_INT_CLR_S  3
+/** MB_LP_4_INT_CLR : WO; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define MB_LP_4_INT_CLR    (BIT(4))
+#define MB_LP_4_INT_CLR_M  (MB_LP_4_INT_CLR_V << MB_LP_4_INT_CLR_S)
+#define MB_LP_4_INT_CLR_V  0x00000001U
+#define MB_LP_4_INT_CLR_S  4
+/** MB_LP_5_INT_CLR : WO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define MB_LP_5_INT_CLR    (BIT(5))
+#define MB_LP_5_INT_CLR_M  (MB_LP_5_INT_CLR_V << MB_LP_5_INT_CLR_S)
+#define MB_LP_5_INT_CLR_V  0x00000001U
+#define MB_LP_5_INT_CLR_S  5
+/** MB_LP_6_INT_CLR : WO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define MB_LP_6_INT_CLR    (BIT(6))
+#define MB_LP_6_INT_CLR_M  (MB_LP_6_INT_CLR_V << MB_LP_6_INT_CLR_S)
+#define MB_LP_6_INT_CLR_V  0x00000001U
+#define MB_LP_6_INT_CLR_S  6
+/** MB_LP_7_INT_CLR : WO; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define MB_LP_7_INT_CLR    (BIT(7))
+#define MB_LP_7_INT_CLR_M  (MB_LP_7_INT_CLR_V << MB_LP_7_INT_CLR_S)
+#define MB_LP_7_INT_CLR_V  0x00000001U
+#define MB_LP_7_INT_CLR_S  7
+/** MB_LP_8_INT_CLR : WO; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define MB_LP_8_INT_CLR    (BIT(8))
+#define MB_LP_8_INT_CLR_M  (MB_LP_8_INT_CLR_V << MB_LP_8_INT_CLR_S)
+#define MB_LP_8_INT_CLR_V  0x00000001U
+#define MB_LP_8_INT_CLR_S  8
+/** MB_LP_9_INT_CLR : WO; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define MB_LP_9_INT_CLR    (BIT(9))
+#define MB_LP_9_INT_CLR_M  (MB_LP_9_INT_CLR_V << MB_LP_9_INT_CLR_S)
+#define MB_LP_9_INT_CLR_V  0x00000001U
+#define MB_LP_9_INT_CLR_S  9
+/** MB_LP_10_INT_CLR : WO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define MB_LP_10_INT_CLR    (BIT(10))
+#define MB_LP_10_INT_CLR_M  (MB_LP_10_INT_CLR_V << MB_LP_10_INT_CLR_S)
+#define MB_LP_10_INT_CLR_V  0x00000001U
+#define MB_LP_10_INT_CLR_S  10
+/** MB_LP_11_INT_CLR : WO; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define MB_LP_11_INT_CLR    (BIT(11))
+#define MB_LP_11_INT_CLR_M  (MB_LP_11_INT_CLR_V << MB_LP_11_INT_CLR_S)
+#define MB_LP_11_INT_CLR_V  0x00000001U
+#define MB_LP_11_INT_CLR_S  11
+/** MB_LP_12_INT_CLR : WO; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define MB_LP_12_INT_CLR    (BIT(12))
+#define MB_LP_12_INT_CLR_M  (MB_LP_12_INT_CLR_V << MB_LP_12_INT_CLR_S)
+#define MB_LP_12_INT_CLR_V  0x00000001U
+#define MB_LP_12_INT_CLR_S  12
+/** MB_LP_13_INT_CLR : WO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define MB_LP_13_INT_CLR    (BIT(13))
+#define MB_LP_13_INT_CLR_M  (MB_LP_13_INT_CLR_V << MB_LP_13_INT_CLR_S)
+#define MB_LP_13_INT_CLR_V  0x00000001U
+#define MB_LP_13_INT_CLR_S  13
+/** MB_LP_14_INT_CLR : WO; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define MB_LP_14_INT_CLR    (BIT(14))
+#define MB_LP_14_INT_CLR_M  (MB_LP_14_INT_CLR_V << MB_LP_14_INT_CLR_S)
+#define MB_LP_14_INT_CLR_V  0x00000001U
+#define MB_LP_14_INT_CLR_S  14
+/** MB_LP_15_INT_CLR : WO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define MB_LP_15_INT_CLR    (BIT(15))
+#define MB_LP_15_INT_CLR_M  (MB_LP_15_INT_CLR_V << MB_LP_15_INT_CLR_S)
+#define MB_LP_15_INT_CLR_V  0x00000001U
+#define MB_LP_15_INT_CLR_S  15
+
+/** MB_HP_INT_RAW_REG register
+ *  need_des
+ */
+#define MB_HP_INT_RAW_REG (DR_REG_MB_BASE + 0x50)
+/** MB_HP_0_INT_RAW : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define MB_HP_0_INT_RAW    (BIT(0))
+#define MB_HP_0_INT_RAW_M  (MB_HP_0_INT_RAW_V << MB_HP_0_INT_RAW_S)
+#define MB_HP_0_INT_RAW_V  0x00000001U
+#define MB_HP_0_INT_RAW_S  0
+/** MB_HP_1_INT_RAW : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define MB_HP_1_INT_RAW    (BIT(1))
+#define MB_HP_1_INT_RAW_M  (MB_HP_1_INT_RAW_V << MB_HP_1_INT_RAW_S)
+#define MB_HP_1_INT_RAW_V  0x00000001U
+#define MB_HP_1_INT_RAW_S  1
+/** MB_HP_2_INT_RAW : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define MB_HP_2_INT_RAW    (BIT(2))
+#define MB_HP_2_INT_RAW_M  (MB_HP_2_INT_RAW_V << MB_HP_2_INT_RAW_S)
+#define MB_HP_2_INT_RAW_V  0x00000001U
+#define MB_HP_2_INT_RAW_S  2
+/** MB_HP_3_INT_RAW : RO; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define MB_HP_3_INT_RAW    (BIT(3))
+#define MB_HP_3_INT_RAW_M  (MB_HP_3_INT_RAW_V << MB_HP_3_INT_RAW_S)
+#define MB_HP_3_INT_RAW_V  0x00000001U
+#define MB_HP_3_INT_RAW_S  3
+/** MB_HP_4_INT_RAW : RO; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define MB_HP_4_INT_RAW    (BIT(4))
+#define MB_HP_4_INT_RAW_M  (MB_HP_4_INT_RAW_V << MB_HP_4_INT_RAW_S)
+#define MB_HP_4_INT_RAW_V  0x00000001U
+#define MB_HP_4_INT_RAW_S  4
+/** MB_HP_5_INT_RAW : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define MB_HP_5_INT_RAW    (BIT(5))
+#define MB_HP_5_INT_RAW_M  (MB_HP_5_INT_RAW_V << MB_HP_5_INT_RAW_S)
+#define MB_HP_5_INT_RAW_V  0x00000001U
+#define MB_HP_5_INT_RAW_S  5
+/** MB_HP_6_INT_RAW : RO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define MB_HP_6_INT_RAW    (BIT(6))
+#define MB_HP_6_INT_RAW_M  (MB_HP_6_INT_RAW_V << MB_HP_6_INT_RAW_S)
+#define MB_HP_6_INT_RAW_V  0x00000001U
+#define MB_HP_6_INT_RAW_S  6
+/** MB_HP_7_INT_RAW : RO; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define MB_HP_7_INT_RAW    (BIT(7))
+#define MB_HP_7_INT_RAW_M  (MB_HP_7_INT_RAW_V << MB_HP_7_INT_RAW_S)
+#define MB_HP_7_INT_RAW_V  0x00000001U
+#define MB_HP_7_INT_RAW_S  7
+/** MB_HP_8_INT_RAW : RO; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define MB_HP_8_INT_RAW    (BIT(8))
+#define MB_HP_8_INT_RAW_M  (MB_HP_8_INT_RAW_V << MB_HP_8_INT_RAW_S)
+#define MB_HP_8_INT_RAW_V  0x00000001U
+#define MB_HP_8_INT_RAW_S  8
+/** MB_HP_9_INT_RAW : RO; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define MB_HP_9_INT_RAW    (BIT(9))
+#define MB_HP_9_INT_RAW_M  (MB_HP_9_INT_RAW_V << MB_HP_9_INT_RAW_S)
+#define MB_HP_9_INT_RAW_V  0x00000001U
+#define MB_HP_9_INT_RAW_S  9
+/** MB_HP_10_INT_RAW : RO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define MB_HP_10_INT_RAW    (BIT(10))
+#define MB_HP_10_INT_RAW_M  (MB_HP_10_INT_RAW_V << MB_HP_10_INT_RAW_S)
+#define MB_HP_10_INT_RAW_V  0x00000001U
+#define MB_HP_10_INT_RAW_S  10
+/** MB_HP_11_INT_RAW : RO; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define MB_HP_11_INT_RAW    (BIT(11))
+#define MB_HP_11_INT_RAW_M  (MB_HP_11_INT_RAW_V << MB_HP_11_INT_RAW_S)
+#define MB_HP_11_INT_RAW_V  0x00000001U
+#define MB_HP_11_INT_RAW_S  11
+/** MB_HP_12_INT_RAW : RO; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define MB_HP_12_INT_RAW    (BIT(12))
+#define MB_HP_12_INT_RAW_M  (MB_HP_12_INT_RAW_V << MB_HP_12_INT_RAW_S)
+#define MB_HP_12_INT_RAW_V  0x00000001U
+#define MB_HP_12_INT_RAW_S  12
+/** MB_HP_13_INT_RAW : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define MB_HP_13_INT_RAW    (BIT(13))
+#define MB_HP_13_INT_RAW_M  (MB_HP_13_INT_RAW_V << MB_HP_13_INT_RAW_S)
+#define MB_HP_13_INT_RAW_V  0x00000001U
+#define MB_HP_13_INT_RAW_S  13
+/** MB_HP_14_INT_RAW : RO; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define MB_HP_14_INT_RAW    (BIT(14))
+#define MB_HP_14_INT_RAW_M  (MB_HP_14_INT_RAW_V << MB_HP_14_INT_RAW_S)
+#define MB_HP_14_INT_RAW_V  0x00000001U
+#define MB_HP_14_INT_RAW_S  14
+/** MB_HP_15_INT_RAW : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define MB_HP_15_INT_RAW    (BIT(15))
+#define MB_HP_15_INT_RAW_M  (MB_HP_15_INT_RAW_V << MB_HP_15_INT_RAW_S)
+#define MB_HP_15_INT_RAW_V  0x00000001U
+#define MB_HP_15_INT_RAW_S  15
+
+/** MB_HP_INT_ST_REG register
+ *  need_des
+ */
+#define MB_HP_INT_ST_REG (DR_REG_MB_BASE + 0x54)
+/** MB_HP_0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define MB_HP_0_INT_ST    (BIT(0))
+#define MB_HP_0_INT_ST_M  (MB_HP_0_INT_ST_V << MB_HP_0_INT_ST_S)
+#define MB_HP_0_INT_ST_V  0x00000001U
+#define MB_HP_0_INT_ST_S  0
+/** MB_HP_1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define MB_HP_1_INT_ST    (BIT(1))
+#define MB_HP_1_INT_ST_M  (MB_HP_1_INT_ST_V << MB_HP_1_INT_ST_S)
+#define MB_HP_1_INT_ST_V  0x00000001U
+#define MB_HP_1_INT_ST_S  1
+/** MB_HP_2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define MB_HP_2_INT_ST    (BIT(2))
+#define MB_HP_2_INT_ST_M  (MB_HP_2_INT_ST_V << MB_HP_2_INT_ST_S)
+#define MB_HP_2_INT_ST_V  0x00000001U
+#define MB_HP_2_INT_ST_S  2
+/** MB_HP_3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define MB_HP_3_INT_ST    (BIT(3))
+#define MB_HP_3_INT_ST_M  (MB_HP_3_INT_ST_V << MB_HP_3_INT_ST_S)
+#define MB_HP_3_INT_ST_V  0x00000001U
+#define MB_HP_3_INT_ST_S  3
+/** MB_HP_4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define MB_HP_4_INT_ST    (BIT(4))
+#define MB_HP_4_INT_ST_M  (MB_HP_4_INT_ST_V << MB_HP_4_INT_ST_S)
+#define MB_HP_4_INT_ST_V  0x00000001U
+#define MB_HP_4_INT_ST_S  4
+/** MB_HP_5_INT_ST : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define MB_HP_5_INT_ST    (BIT(5))
+#define MB_HP_5_INT_ST_M  (MB_HP_5_INT_ST_V << MB_HP_5_INT_ST_S)
+#define MB_HP_5_INT_ST_V  0x00000001U
+#define MB_HP_5_INT_ST_S  5
+/** MB_HP_6_INT_ST : RO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define MB_HP_6_INT_ST    (BIT(6))
+#define MB_HP_6_INT_ST_M  (MB_HP_6_INT_ST_V << MB_HP_6_INT_ST_S)
+#define MB_HP_6_INT_ST_V  0x00000001U
+#define MB_HP_6_INT_ST_S  6
+/** MB_HP_7_INT_ST : RO; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define MB_HP_7_INT_ST    (BIT(7))
+#define MB_HP_7_INT_ST_M  (MB_HP_7_INT_ST_V << MB_HP_7_INT_ST_S)
+#define MB_HP_7_INT_ST_V  0x00000001U
+#define MB_HP_7_INT_ST_S  7
+/** MB_HP_8_INT_ST : RO; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define MB_HP_8_INT_ST    (BIT(8))
+#define MB_HP_8_INT_ST_M  (MB_HP_8_INT_ST_V << MB_HP_8_INT_ST_S)
+#define MB_HP_8_INT_ST_V  0x00000001U
+#define MB_HP_8_INT_ST_S  8
+/** MB_HP_9_INT_ST : RO; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define MB_HP_9_INT_ST    (BIT(9))
+#define MB_HP_9_INT_ST_M  (MB_HP_9_INT_ST_V << MB_HP_9_INT_ST_S)
+#define MB_HP_9_INT_ST_V  0x00000001U
+#define MB_HP_9_INT_ST_S  9
+/** MB_HP_10_INT_ST : RO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define MB_HP_10_INT_ST    (BIT(10))
+#define MB_HP_10_INT_ST_M  (MB_HP_10_INT_ST_V << MB_HP_10_INT_ST_S)
+#define MB_HP_10_INT_ST_V  0x00000001U
+#define MB_HP_10_INT_ST_S  10
+/** MB_HP_11_INT_ST : RO; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define MB_HP_11_INT_ST    (BIT(11))
+#define MB_HP_11_INT_ST_M  (MB_HP_11_INT_ST_V << MB_HP_11_INT_ST_S)
+#define MB_HP_11_INT_ST_V  0x00000001U
+#define MB_HP_11_INT_ST_S  11
+/** MB_HP_12_INT_ST : RO; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define MB_HP_12_INT_ST    (BIT(12))
+#define MB_HP_12_INT_ST_M  (MB_HP_12_INT_ST_V << MB_HP_12_INT_ST_S)
+#define MB_HP_12_INT_ST_V  0x00000001U
+#define MB_HP_12_INT_ST_S  12
+/** MB_HP_13_INT_ST : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define MB_HP_13_INT_ST    (BIT(13))
+#define MB_HP_13_INT_ST_M  (MB_HP_13_INT_ST_V << MB_HP_13_INT_ST_S)
+#define MB_HP_13_INT_ST_V  0x00000001U
+#define MB_HP_13_INT_ST_S  13
+/** MB_HP_14_INT_ST : RO; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define MB_HP_14_INT_ST    (BIT(14))
+#define MB_HP_14_INT_ST_M  (MB_HP_14_INT_ST_V << MB_HP_14_INT_ST_S)
+#define MB_HP_14_INT_ST_V  0x00000001U
+#define MB_HP_14_INT_ST_S  14
+/** MB_HP_15_INT_ST : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define MB_HP_15_INT_ST    (BIT(15))
+#define MB_HP_15_INT_ST_M  (MB_HP_15_INT_ST_V << MB_HP_15_INT_ST_S)
+#define MB_HP_15_INT_ST_V  0x00000001U
+#define MB_HP_15_INT_ST_S  15
+
+/** MB_HP_INT_ENA_REG register
+ *  need_des
+ */
+#define MB_HP_INT_ENA_REG (DR_REG_MB_BASE + 0x58)
+/** MB_HP_0_INT_ENA : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define MB_HP_0_INT_ENA    (BIT(0))
+#define MB_HP_0_INT_ENA_M  (MB_HP_0_INT_ENA_V << MB_HP_0_INT_ENA_S)
+#define MB_HP_0_INT_ENA_V  0x00000001U
+#define MB_HP_0_INT_ENA_S  0
+/** MB_HP_1_INT_ENA : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define MB_HP_1_INT_ENA    (BIT(1))
+#define MB_HP_1_INT_ENA_M  (MB_HP_1_INT_ENA_V << MB_HP_1_INT_ENA_S)
+#define MB_HP_1_INT_ENA_V  0x00000001U
+#define MB_HP_1_INT_ENA_S  1
+/** MB_HP_2_INT_ENA : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define MB_HP_2_INT_ENA    (BIT(2))
+#define MB_HP_2_INT_ENA_M  (MB_HP_2_INT_ENA_V << MB_HP_2_INT_ENA_S)
+#define MB_HP_2_INT_ENA_V  0x00000001U
+#define MB_HP_2_INT_ENA_S  2
+/** MB_HP_3_INT_ENA : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define MB_HP_3_INT_ENA    (BIT(3))
+#define MB_HP_3_INT_ENA_M  (MB_HP_3_INT_ENA_V << MB_HP_3_INT_ENA_S)
+#define MB_HP_3_INT_ENA_V  0x00000001U
+#define MB_HP_3_INT_ENA_S  3
+/** MB_HP_4_INT_ENA : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define MB_HP_4_INT_ENA    (BIT(4))
+#define MB_HP_4_INT_ENA_M  (MB_HP_4_INT_ENA_V << MB_HP_4_INT_ENA_S)
+#define MB_HP_4_INT_ENA_V  0x00000001U
+#define MB_HP_4_INT_ENA_S  4
+/** MB_HP_5_INT_ENA : R/W; bitpos: [5]; default: 1;
+ *  need_des
+ */
+#define MB_HP_5_INT_ENA    (BIT(5))
+#define MB_HP_5_INT_ENA_M  (MB_HP_5_INT_ENA_V << MB_HP_5_INT_ENA_S)
+#define MB_HP_5_INT_ENA_V  0x00000001U
+#define MB_HP_5_INT_ENA_S  5
+/** MB_HP_6_INT_ENA : R/W; bitpos: [6]; default: 1;
+ *  need_des
+ */
+#define MB_HP_6_INT_ENA    (BIT(6))
+#define MB_HP_6_INT_ENA_M  (MB_HP_6_INT_ENA_V << MB_HP_6_INT_ENA_S)
+#define MB_HP_6_INT_ENA_V  0x00000001U
+#define MB_HP_6_INT_ENA_S  6
+/** MB_HP_7_INT_ENA : R/W; bitpos: [7]; default: 1;
+ *  need_des
+ */
+#define MB_HP_7_INT_ENA    (BIT(7))
+#define MB_HP_7_INT_ENA_M  (MB_HP_7_INT_ENA_V << MB_HP_7_INT_ENA_S)
+#define MB_HP_7_INT_ENA_V  0x00000001U
+#define MB_HP_7_INT_ENA_S  7
+/** MB_HP_8_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define MB_HP_8_INT_ENA    (BIT(8))
+#define MB_HP_8_INT_ENA_M  (MB_HP_8_INT_ENA_V << MB_HP_8_INT_ENA_S)
+#define MB_HP_8_INT_ENA_V  0x00000001U
+#define MB_HP_8_INT_ENA_S  8
+/** MB_HP_9_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define MB_HP_9_INT_ENA    (BIT(9))
+#define MB_HP_9_INT_ENA_M  (MB_HP_9_INT_ENA_V << MB_HP_9_INT_ENA_S)
+#define MB_HP_9_INT_ENA_V  0x00000001U
+#define MB_HP_9_INT_ENA_S  9
+/** MB_HP_10_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define MB_HP_10_INT_ENA    (BIT(10))
+#define MB_HP_10_INT_ENA_M  (MB_HP_10_INT_ENA_V << MB_HP_10_INT_ENA_S)
+#define MB_HP_10_INT_ENA_V  0x00000001U
+#define MB_HP_10_INT_ENA_S  10
+/** MB_HP_11_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define MB_HP_11_INT_ENA    (BIT(11))
+#define MB_HP_11_INT_ENA_M  (MB_HP_11_INT_ENA_V << MB_HP_11_INT_ENA_S)
+#define MB_HP_11_INT_ENA_V  0x00000001U
+#define MB_HP_11_INT_ENA_S  11
+/** MB_HP_12_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define MB_HP_12_INT_ENA    (BIT(12))
+#define MB_HP_12_INT_ENA_M  (MB_HP_12_INT_ENA_V << MB_HP_12_INT_ENA_S)
+#define MB_HP_12_INT_ENA_V  0x00000001U
+#define MB_HP_12_INT_ENA_S  12
+/** MB_HP_13_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define MB_HP_13_INT_ENA    (BIT(13))
+#define MB_HP_13_INT_ENA_M  (MB_HP_13_INT_ENA_V << MB_HP_13_INT_ENA_S)
+#define MB_HP_13_INT_ENA_V  0x00000001U
+#define MB_HP_13_INT_ENA_S  13
+/** MB_HP_14_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define MB_HP_14_INT_ENA    (BIT(14))
+#define MB_HP_14_INT_ENA_M  (MB_HP_14_INT_ENA_V << MB_HP_14_INT_ENA_S)
+#define MB_HP_14_INT_ENA_V  0x00000001U
+#define MB_HP_14_INT_ENA_S  14
+/** MB_HP_15_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define MB_HP_15_INT_ENA    (BIT(15))
+#define MB_HP_15_INT_ENA_M  (MB_HP_15_INT_ENA_V << MB_HP_15_INT_ENA_S)
+#define MB_HP_15_INT_ENA_V  0x00000001U
+#define MB_HP_15_INT_ENA_S  15
+
+/** MB_HP_INT_CLR_REG register
+ *  need_des
+ */
+#define MB_HP_INT_CLR_REG (DR_REG_MB_BASE + 0x5c)
+/** MB_HP_0_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define MB_HP_0_INT_CLR    (BIT(0))
+#define MB_HP_0_INT_CLR_M  (MB_HP_0_INT_CLR_V << MB_HP_0_INT_CLR_S)
+#define MB_HP_0_INT_CLR_V  0x00000001U
+#define MB_HP_0_INT_CLR_S  0
+/** MB_HP_1_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define MB_HP_1_INT_CLR    (BIT(1))
+#define MB_HP_1_INT_CLR_M  (MB_HP_1_INT_CLR_V << MB_HP_1_INT_CLR_S)
+#define MB_HP_1_INT_CLR_V  0x00000001U
+#define MB_HP_1_INT_CLR_S  1
+/** MB_HP_2_INT_CLR : WO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define MB_HP_2_INT_CLR    (BIT(2))
+#define MB_HP_2_INT_CLR_M  (MB_HP_2_INT_CLR_V << MB_HP_2_INT_CLR_S)
+#define MB_HP_2_INT_CLR_V  0x00000001U
+#define MB_HP_2_INT_CLR_S  2
+/** MB_HP_3_INT_CLR : WO; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define MB_HP_3_INT_CLR    (BIT(3))
+#define MB_HP_3_INT_CLR_M  (MB_HP_3_INT_CLR_V << MB_HP_3_INT_CLR_S)
+#define MB_HP_3_INT_CLR_V  0x00000001U
+#define MB_HP_3_INT_CLR_S  3
+/** MB_HP_4_INT_CLR : WO; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define MB_HP_4_INT_CLR    (BIT(4))
+#define MB_HP_4_INT_CLR_M  (MB_HP_4_INT_CLR_V << MB_HP_4_INT_CLR_S)
+#define MB_HP_4_INT_CLR_V  0x00000001U
+#define MB_HP_4_INT_CLR_S  4
+/** MB_HP_5_INT_CLR : WO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define MB_HP_5_INT_CLR    (BIT(5))
+#define MB_HP_5_INT_CLR_M  (MB_HP_5_INT_CLR_V << MB_HP_5_INT_CLR_S)
+#define MB_HP_5_INT_CLR_V  0x00000001U
+#define MB_HP_5_INT_CLR_S  5
+/** MB_HP_6_INT_CLR : WO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define MB_HP_6_INT_CLR    (BIT(6))
+#define MB_HP_6_INT_CLR_M  (MB_HP_6_INT_CLR_V << MB_HP_6_INT_CLR_S)
+#define MB_HP_6_INT_CLR_V  0x00000001U
+#define MB_HP_6_INT_CLR_S  6
+/** MB_HP_7_INT_CLR : WO; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define MB_HP_7_INT_CLR    (BIT(7))
+#define MB_HP_7_INT_CLR_M  (MB_HP_7_INT_CLR_V << MB_HP_7_INT_CLR_S)
+#define MB_HP_7_INT_CLR_V  0x00000001U
+#define MB_HP_7_INT_CLR_S  7
+/** MB_HP_8_INT_CLR : WO; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define MB_HP_8_INT_CLR    (BIT(8))
+#define MB_HP_8_INT_CLR_M  (MB_HP_8_INT_CLR_V << MB_HP_8_INT_CLR_S)
+#define MB_HP_8_INT_CLR_V  0x00000001U
+#define MB_HP_8_INT_CLR_S  8
+/** MB_HP_9_INT_CLR : WO; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define MB_HP_9_INT_CLR    (BIT(9))
+#define MB_HP_9_INT_CLR_M  (MB_HP_9_INT_CLR_V << MB_HP_9_INT_CLR_S)
+#define MB_HP_9_INT_CLR_V  0x00000001U
+#define MB_HP_9_INT_CLR_S  9
+/** MB_HP_10_INT_CLR : WO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define MB_HP_10_INT_CLR    (BIT(10))
+#define MB_HP_10_INT_CLR_M  (MB_HP_10_INT_CLR_V << MB_HP_10_INT_CLR_S)
+#define MB_HP_10_INT_CLR_V  0x00000001U
+#define MB_HP_10_INT_CLR_S  10
+/** MB_HP_11_INT_CLR : WO; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define MB_HP_11_INT_CLR    (BIT(11))
+#define MB_HP_11_INT_CLR_M  (MB_HP_11_INT_CLR_V << MB_HP_11_INT_CLR_S)
+#define MB_HP_11_INT_CLR_V  0x00000001U
+#define MB_HP_11_INT_CLR_S  11
+/** MB_HP_12_INT_CLR : WO; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define MB_HP_12_INT_CLR    (BIT(12))
+#define MB_HP_12_INT_CLR_M  (MB_HP_12_INT_CLR_V << MB_HP_12_INT_CLR_S)
+#define MB_HP_12_INT_CLR_V  0x00000001U
+#define MB_HP_12_INT_CLR_S  12
+/** MB_HP_13_INT_CLR : WO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define MB_HP_13_INT_CLR    (BIT(13))
+#define MB_HP_13_INT_CLR_M  (MB_HP_13_INT_CLR_V << MB_HP_13_INT_CLR_S)
+#define MB_HP_13_INT_CLR_V  0x00000001U
+#define MB_HP_13_INT_CLR_S  13
+/** MB_HP_14_INT_CLR : WO; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define MB_HP_14_INT_CLR    (BIT(14))
+#define MB_HP_14_INT_CLR_M  (MB_HP_14_INT_CLR_V << MB_HP_14_INT_CLR_S)
+#define MB_HP_14_INT_CLR_V  0x00000001U
+#define MB_HP_14_INT_CLR_S  14
+/** MB_HP_15_INT_CLR : WO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define MB_HP_15_INT_CLR    (BIT(15))
+#define MB_HP_15_INT_CLR_M  (MB_HP_15_INT_CLR_V << MB_HP_15_INT_CLR_S)
+#define MB_HP_15_INT_CLR_V  0x00000001U
+#define MB_HP_15_INT_CLR_S  15
+
+/** MB_REG_CLK_EN_REG register
+ *  need_des
+ */
+#define MB_REG_CLK_EN_REG (DR_REG_MB_BASE + 0x60)
+/** MB_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define MB_REG_CLK_EN    (BIT(0))
+#define MB_REG_CLK_EN_M  (MB_REG_CLK_EN_V << MB_REG_CLK_EN_S)
+#define MB_REG_CLK_EN_V  0x00000001U
+#define MB_REG_CLK_EN_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_mailbox_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_mailbox_struct.h
new file mode 100644
index 0000000000..16e0a721e2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_mailbox_struct.h
@@ -0,0 +1,867 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of massege_0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_0 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_0:32;
+    };
+    uint32_t val;
+} mb_massege_0_reg_t;
+
+/** Type of massege_1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_1 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_1:32;
+    };
+    uint32_t val;
+} mb_massege_1_reg_t;
+
+/** Type of massege_2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_2 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_2:32;
+    };
+    uint32_t val;
+} mb_massege_2_reg_t;
+
+/** Type of massege_3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_3 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_3:32;
+    };
+    uint32_t val;
+} mb_massege_3_reg_t;
+
+/** Type of massege_4 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_4 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_4:32;
+    };
+    uint32_t val;
+} mb_massege_4_reg_t;
+
+/** Type of massege_5 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_5 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_5:32;
+    };
+    uint32_t val;
+} mb_massege_5_reg_t;
+
+/** Type of massege_6 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_6 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_6:32;
+    };
+    uint32_t val;
+} mb_massege_6_reg_t;
+
+/** Type of massege_7 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_7 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_7:32;
+    };
+    uint32_t val;
+} mb_massege_7_reg_t;
+
+/** Type of massege_8 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_8 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_8:32;
+    };
+    uint32_t val;
+} mb_massege_8_reg_t;
+
+/** Type of massege_9 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_9 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_9:32;
+    };
+    uint32_t val;
+} mb_massege_9_reg_t;
+
+/** Type of massege_10 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_10 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_10:32;
+    };
+    uint32_t val;
+} mb_massege_10_reg_t;
+
+/** Type of massege_11 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_11 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_11:32;
+    };
+    uint32_t val;
+} mb_massege_11_reg_t;
+
+/** Type of massege_12 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_12 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_12:32;
+    };
+    uint32_t val;
+} mb_massege_12_reg_t;
+
+/** Type of massege_13 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_13 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_13:32;
+    };
+    uint32_t val;
+} mb_massege_13_reg_t;
+
+/** Type of massege_14 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_14 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_14:32;
+    };
+    uint32_t val;
+} mb_massege_14_reg_t;
+
+/** Type of massege_15 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_15 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_15:32;
+    };
+    uint32_t val;
+} mb_massege_15_reg_t;
+
+/** Type of reg_clk_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mb_reg_clk_en_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of lp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_0_int_raw : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_0_int_raw:1;
+        /** lp_1_int_raw : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_1_int_raw:1;
+        /** lp_2_int_raw : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_2_int_raw:1;
+        /** lp_3_int_raw : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_3_int_raw:1;
+        /** lp_4_int_raw : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_4_int_raw:1;
+        /** lp_5_int_raw : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_5_int_raw:1;
+        /** lp_6_int_raw : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_6_int_raw:1;
+        /** lp_7_int_raw : RO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_7_int_raw:1;
+        /** lp_8_int_raw : RO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_8_int_raw:1;
+        /** lp_9_int_raw : RO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_9_int_raw:1;
+        /** lp_10_int_raw : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_10_int_raw:1;
+        /** lp_11_int_raw : RO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_11_int_raw:1;
+        /** lp_12_int_raw : RO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_12_int_raw:1;
+        /** lp_13_int_raw : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_13_int_raw:1;
+        /** lp_14_int_raw : RO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_14_int_raw:1;
+        /** lp_15_int_raw : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_15_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_lp_int_raw_reg_t;
+
+/** Type of lp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_0_int_st : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_0_int_st:1;
+        /** lp_1_int_st : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_1_int_st:1;
+        /** lp_2_int_st : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_2_int_st:1;
+        /** lp_3_int_st : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_3_int_st:1;
+        /** lp_4_int_st : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_4_int_st:1;
+        /** lp_5_int_st : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_5_int_st:1;
+        /** lp_6_int_st : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_6_int_st:1;
+        /** lp_7_int_st : RO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_7_int_st:1;
+        /** lp_8_int_st : RO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_8_int_st:1;
+        /** lp_9_int_st : RO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_9_int_st:1;
+        /** lp_10_int_st : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_10_int_st:1;
+        /** lp_11_int_st : RO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_11_int_st:1;
+        /** lp_12_int_st : RO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_12_int_st:1;
+        /** lp_13_int_st : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_13_int_st:1;
+        /** lp_14_int_st : RO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_14_int_st:1;
+        /** lp_15_int_st : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_15_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_lp_int_st_reg_t;
+
+/** Type of lp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_0_int_ena : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_0_int_ena:1;
+        /** lp_1_int_ena : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_1_int_ena:1;
+        /** lp_2_int_ena : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_2_int_ena:1;
+        /** lp_3_int_ena : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_3_int_ena:1;
+        /** lp_4_int_ena : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_4_int_ena:1;
+        /** lp_5_int_ena : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_5_int_ena:1;
+        /** lp_6_int_ena : R/W; bitpos: [6]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_6_int_ena:1;
+        /** lp_7_int_ena : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_7_int_ena:1;
+        /** lp_8_int_ena : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_8_int_ena:1;
+        /** lp_9_int_ena : R/W; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_9_int_ena:1;
+        /** lp_10_int_ena : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_10_int_ena:1;
+        /** lp_11_int_ena : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_11_int_ena:1;
+        /** lp_12_int_ena : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_12_int_ena:1;
+        /** lp_13_int_ena : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_13_int_ena:1;
+        /** lp_14_int_ena : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_14_int_ena:1;
+        /** lp_15_int_ena : R/W; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_15_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_lp_int_ena_reg_t;
+
+/** Type of lp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_0_int_clr : WO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_0_int_clr:1;
+        /** lp_1_int_clr : WO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_1_int_clr:1;
+        /** lp_2_int_clr : WO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_2_int_clr:1;
+        /** lp_3_int_clr : WO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_3_int_clr:1;
+        /** lp_4_int_clr : WO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_4_int_clr:1;
+        /** lp_5_int_clr : WO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_5_int_clr:1;
+        /** lp_6_int_clr : WO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_6_int_clr:1;
+        /** lp_7_int_clr : WO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_7_int_clr:1;
+        /** lp_8_int_clr : WO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_8_int_clr:1;
+        /** lp_9_int_clr : WO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_9_int_clr:1;
+        /** lp_10_int_clr : WO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_10_int_clr:1;
+        /** lp_11_int_clr : WO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_11_int_clr:1;
+        /** lp_12_int_clr : WO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_12_int_clr:1;
+        /** lp_13_int_clr : WO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_13_int_clr:1;
+        /** lp_14_int_clr : WO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_14_int_clr:1;
+        /** lp_15_int_clr : WO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_15_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_lp_int_clr_reg_t;
+
+/** Type of hp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_0_int_raw : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_0_int_raw:1;
+        /** hp_1_int_raw : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_1_int_raw:1;
+        /** hp_2_int_raw : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_2_int_raw:1;
+        /** hp_3_int_raw : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_3_int_raw:1;
+        /** hp_4_int_raw : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_4_int_raw:1;
+        /** hp_5_int_raw : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_5_int_raw:1;
+        /** hp_6_int_raw : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_6_int_raw:1;
+        /** hp_7_int_raw : RO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_7_int_raw:1;
+        /** hp_8_int_raw : RO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_8_int_raw:1;
+        /** hp_9_int_raw : RO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_9_int_raw:1;
+        /** hp_10_int_raw : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_10_int_raw:1;
+        /** hp_11_int_raw : RO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_11_int_raw:1;
+        /** hp_12_int_raw : RO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_12_int_raw:1;
+        /** hp_13_int_raw : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_13_int_raw:1;
+        /** hp_14_int_raw : RO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_14_int_raw:1;
+        /** hp_15_int_raw : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_15_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_hp_int_raw_reg_t;
+
+/** Type of hp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_0_int_st : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_0_int_st:1;
+        /** hp_1_int_st : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_1_int_st:1;
+        /** hp_2_int_st : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_2_int_st:1;
+        /** hp_3_int_st : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_3_int_st:1;
+        /** hp_4_int_st : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_4_int_st:1;
+        /** hp_5_int_st : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_5_int_st:1;
+        /** hp_6_int_st : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_6_int_st:1;
+        /** hp_7_int_st : RO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_7_int_st:1;
+        /** hp_8_int_st : RO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_8_int_st:1;
+        /** hp_9_int_st : RO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_9_int_st:1;
+        /** hp_10_int_st : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_10_int_st:1;
+        /** hp_11_int_st : RO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_11_int_st:1;
+        /** hp_12_int_st : RO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_12_int_st:1;
+        /** hp_13_int_st : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_13_int_st:1;
+        /** hp_14_int_st : RO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_14_int_st:1;
+        /** hp_15_int_st : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_15_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_hp_int_st_reg_t;
+
+/** Type of hp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_0_int_ena : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_0_int_ena:1;
+        /** hp_1_int_ena : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_1_int_ena:1;
+        /** hp_2_int_ena : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_2_int_ena:1;
+        /** hp_3_int_ena : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_3_int_ena:1;
+        /** hp_4_int_ena : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_4_int_ena:1;
+        /** hp_5_int_ena : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_5_int_ena:1;
+        /** hp_6_int_ena : R/W; bitpos: [6]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_6_int_ena:1;
+        /** hp_7_int_ena : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_7_int_ena:1;
+        /** hp_8_int_ena : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_8_int_ena:1;
+        /** hp_9_int_ena : R/W; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_9_int_ena:1;
+        /** hp_10_int_ena : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_10_int_ena:1;
+        /** hp_11_int_ena : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_11_int_ena:1;
+        /** hp_12_int_ena : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_12_int_ena:1;
+        /** hp_13_int_ena : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_13_int_ena:1;
+        /** hp_14_int_ena : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_14_int_ena:1;
+        /** hp_15_int_ena : R/W; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_15_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_hp_int_ena_reg_t;
+
+/** Type of hp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_0_int_clr : WO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_0_int_clr:1;
+        /** hp_1_int_clr : WO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_1_int_clr:1;
+        /** hp_2_int_clr : WO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_2_int_clr:1;
+        /** hp_3_int_clr : WO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_3_int_clr:1;
+        /** hp_4_int_clr : WO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_4_int_clr:1;
+        /** hp_5_int_clr : WO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_5_int_clr:1;
+        /** hp_6_int_clr : WO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_6_int_clr:1;
+        /** hp_7_int_clr : WO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_7_int_clr:1;
+        /** hp_8_int_clr : WO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_8_int_clr:1;
+        /** hp_9_int_clr : WO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_9_int_clr:1;
+        /** hp_10_int_clr : WO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_10_int_clr:1;
+        /** hp_11_int_clr : WO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_11_int_clr:1;
+        /** hp_12_int_clr : WO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_12_int_clr:1;
+        /** hp_13_int_clr : WO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_13_int_clr:1;
+        /** hp_14_int_clr : WO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_14_int_clr:1;
+        /** hp_15_int_clr : WO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_15_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_hp_int_clr_reg_t;
+
+
+typedef struct {
+    volatile mb_massege_0_reg_t massege_0;
+    volatile mb_massege_1_reg_t massege_1;
+    volatile mb_massege_2_reg_t massege_2;
+    volatile mb_massege_3_reg_t massege_3;
+    volatile mb_massege_4_reg_t massege_4;
+    volatile mb_massege_5_reg_t massege_5;
+    volatile mb_massege_6_reg_t massege_6;
+    volatile mb_massege_7_reg_t massege_7;
+    volatile mb_massege_8_reg_t massege_8;
+    volatile mb_massege_9_reg_t massege_9;
+    volatile mb_massege_10_reg_t massege_10;
+    volatile mb_massege_11_reg_t massege_11;
+    volatile mb_massege_12_reg_t massege_12;
+    volatile mb_massege_13_reg_t massege_13;
+    volatile mb_massege_14_reg_t massege_14;
+    volatile mb_massege_15_reg_t massege_15;
+    volatile mb_lp_int_raw_reg_t lp_int_raw;
+    volatile mb_lp_int_st_reg_t lp_int_st;
+    volatile mb_lp_int_ena_reg_t lp_int_ena;
+    volatile mb_lp_int_clr_reg_t lp_int_clr;
+    volatile mb_hp_int_raw_reg_t hp_int_raw;
+    volatile mb_hp_int_st_reg_t hp_int_st;
+    volatile mb_hp_int_ena_reg_t hp_int_ena;
+    volatile mb_hp_int_clr_reg_t hp_int_clr;
+    volatile mb_reg_clk_en_reg_t reg_clk_en;
+} mb_dev_t;
+
+extern mb_dev_t LP_MAILBOX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mb_dev_t) == 0x64, "Invalid size of mb_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_eco5_reg.h
new file mode 100644
index 0000000000..833e384012
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_eco5_reg.h
@@ -0,0 +1,492 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_PMS_DATE_REG register
+ *  NA
+ */
+#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
+/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
+ *  NA
+ */
+#define TEE_TEE_DATE    0xFFFFFFFFU
+#define TEE_TEE_DATE_M  (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
+#define TEE_TEE_DATE_V  0xFFFFFFFFU
+#define TEE_TEE_DATE_S  0
+
+/** TEE_PMS_CLK_EN_REG register
+ *  NA
+ */
+#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
+/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CLK_EN    (BIT(0))
+#define TEE_REG_CLK_EN_M  (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
+#define TEE_REG_CLK_EN_V  0x00000001U
+#define TEE_REG_CLK_EN_S  0
+
+/** TEE_LP_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
+/** TEE_REG_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_M  (TEE_REG_LP_MM_LP_SYSREG_ALLOW_V << TEE_REG_LP_MM_LP_SYSREG_ALLOW_S)
+#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_S  0
+/** TEE_REG_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_M  (TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S)
+#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S  1
+/** TEE_REG_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_TIMER_ALLOW    (BIT(2))
+#define TEE_REG_LP_MM_LP_TIMER_ALLOW_M  (TEE_REG_LP_MM_LP_TIMER_ALLOW_V << TEE_REG_LP_MM_LP_TIMER_ALLOW_S)
+#define TEE_REG_LP_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_TIMER_ALLOW_S  2
+/** TEE_REG_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_M  (TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V << TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S)
+#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S  3
+/** TEE_REG_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_PMU_ALLOW    (BIT(4))
+#define TEE_REG_LP_MM_LP_PMU_ALLOW_M  (TEE_REG_LP_MM_LP_PMU_ALLOW_V << TEE_REG_LP_MM_LP_PMU_ALLOW_S)
+#define TEE_REG_LP_MM_LP_PMU_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_PMU_ALLOW_S  4
+/** TEE_REG_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_WDT_ALLOW    (BIT(5))
+#define TEE_REG_LP_MM_LP_WDT_ALLOW_M  (TEE_REG_LP_MM_LP_WDT_ALLOW_V << TEE_REG_LP_MM_LP_WDT_ALLOW_S)
+#define TEE_REG_LP_MM_LP_WDT_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_WDT_ALLOW_S  5
+/** TEE_REG_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_M  (TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V << TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S)
+#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S  6
+/** TEE_REG_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_RTC_ALLOW    (BIT(7))
+#define TEE_REG_LP_MM_LP_RTC_ALLOW_M  (TEE_REG_LP_MM_LP_RTC_ALLOW_V << TEE_REG_LP_MM_LP_RTC_ALLOW_S)
+#define TEE_REG_LP_MM_LP_RTC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_RTC_ALLOW_S  7
+/** TEE_REG_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_M  (TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S)
+#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S  8
+/** TEE_REG_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_UART_ALLOW    (BIT(9))
+#define TEE_REG_LP_MM_LP_UART_ALLOW_M  (TEE_REG_LP_MM_LP_UART_ALLOW_V << TEE_REG_LP_MM_LP_UART_ALLOW_S)
+#define TEE_REG_LP_MM_LP_UART_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_UART_ALLOW_S  9
+/** TEE_REG_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_I2C_ALLOW    (BIT(10))
+#define TEE_REG_LP_MM_LP_I2C_ALLOW_M  (TEE_REG_LP_MM_LP_I2C_ALLOW_V << TEE_REG_LP_MM_LP_I2C_ALLOW_S)
+#define TEE_REG_LP_MM_LP_I2C_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_I2C_ALLOW_S  10
+/** TEE_REG_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_SPI_ALLOW    (BIT(11))
+#define TEE_REG_LP_MM_LP_SPI_ALLOW_M  (TEE_REG_LP_MM_LP_SPI_ALLOW_V << TEE_REG_LP_MM_LP_SPI_ALLOW_S)
+#define TEE_REG_LP_MM_LP_SPI_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_SPI_ALLOW_S  11
+/** TEE_REG_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_M  (TEE_REG_LP_MM_LP_I2CMST_ALLOW_V << TEE_REG_LP_MM_LP_I2CMST_ALLOW_S)
+#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_S  12
+/** TEE_REG_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_I2S_ALLOW    (BIT(13))
+#define TEE_REG_LP_MM_LP_I2S_ALLOW_M  (TEE_REG_LP_MM_LP_I2S_ALLOW_V << TEE_REG_LP_MM_LP_I2S_ALLOW_S)
+#define TEE_REG_LP_MM_LP_I2S_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_I2S_ALLOW_S  13
+/** TEE_REG_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_ADC_ALLOW    (BIT(14))
+#define TEE_REG_LP_MM_LP_ADC_ALLOW_M  (TEE_REG_LP_MM_LP_ADC_ALLOW_V << TEE_REG_LP_MM_LP_ADC_ALLOW_S)
+#define TEE_REG_LP_MM_LP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_ADC_ALLOW_S  14
+/** TEE_REG_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_M  (TEE_REG_LP_MM_LP_TOUCH_ALLOW_V << TEE_REG_LP_MM_LP_TOUCH_ALLOW_S)
+#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_S  15
+/** TEE_REG_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_M  (TEE_REG_LP_MM_LP_IOMUX_ALLOW_V << TEE_REG_LP_MM_LP_IOMUX_ALLOW_S)
+#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_S  16
+/** TEE_REG_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_INTR_ALLOW    (BIT(17))
+#define TEE_REG_LP_MM_LP_INTR_ALLOW_M  (TEE_REG_LP_MM_LP_INTR_ALLOW_V << TEE_REG_LP_MM_LP_INTR_ALLOW_S)
+#define TEE_REG_LP_MM_LP_INTR_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_INTR_ALLOW_S  17
+/** TEE_REG_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_M  (TEE_REG_LP_MM_LP_EFUSE_ALLOW_V << TEE_REG_LP_MM_LP_EFUSE_ALLOW_S)
+#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_S  18
+/** TEE_REG_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_PMS_ALLOW    (BIT(19))
+#define TEE_REG_LP_MM_LP_PMS_ALLOW_M  (TEE_REG_LP_MM_LP_PMS_ALLOW_V << TEE_REG_LP_MM_LP_PMS_ALLOW_S)
+#define TEE_REG_LP_MM_LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_PMS_ALLOW_S  19
+/** TEE_REG_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_M  (TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V << TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S)
+#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S  20
+/** TEE_REG_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_TSENS_ALLOW    (BIT(21))
+#define TEE_REG_LP_MM_LP_TSENS_ALLOW_M  (TEE_REG_LP_MM_LP_TSENS_ALLOW_V << TEE_REG_LP_MM_LP_TSENS_ALLOW_S)
+#define TEE_REG_LP_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_TSENS_ALLOW_S  21
+/** TEE_REG_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_HUK_ALLOW    (BIT(22))
+#define TEE_REG_LP_MM_LP_HUK_ALLOW_M  (TEE_REG_LP_MM_LP_HUK_ALLOW_V << TEE_REG_LP_MM_LP_HUK_ALLOW_S)
+#define TEE_REG_LP_MM_LP_HUK_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_HUK_ALLOW_S  22
+/** TEE_REG_LP_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW    (BIT(23))
+#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_M  (TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S)
+#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S  23
+/** TEE_REG_LP_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_TRNG_ALLOW    (BIT(24))
+#define TEE_REG_LP_MM_LP_TRNG_ALLOW_M  (TEE_REG_LP_MM_LP_TRNG_ALLOW_V << TEE_REG_LP_MM_LP_TRNG_ALLOW_S)
+#define TEE_REG_LP_MM_LP_TRNG_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_TRNG_ALLOW_S  24
+
+/** TEE_PERI_REGION0_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION0_LOW_REG (DR_REG_TEE_BASE + 0xc)
+/** TEE_REG_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION0_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION0_LOW_M  (TEE_REG_PERI_REGION0_LOW_V << TEE_REG_PERI_REGION0_LOW_S)
+#define TEE_REG_PERI_REGION0_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION0_LOW_S  2
+
+/** TEE_PERI_REGION0_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION0_HIGH_REG (DR_REG_TEE_BASE + 0x10)
+/** TEE_REG_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION0_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION0_HIGH_M  (TEE_REG_PERI_REGION0_HIGH_V << TEE_REG_PERI_REGION0_HIGH_S)
+#define TEE_REG_PERI_REGION0_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION0_HIGH_S  2
+
+/** TEE_PERI_REGION1_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION1_LOW_REG (DR_REG_TEE_BASE + 0x14)
+/** TEE_REG_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION1_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION1_LOW_M  (TEE_REG_PERI_REGION1_LOW_V << TEE_REG_PERI_REGION1_LOW_S)
+#define TEE_REG_PERI_REGION1_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION1_LOW_S  2
+
+/** TEE_PERI_REGION1_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION1_HIGH_REG (DR_REG_TEE_BASE + 0x18)
+/** TEE_REG_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION1_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION1_HIGH_M  (TEE_REG_PERI_REGION1_HIGH_V << TEE_REG_PERI_REGION1_HIGH_S)
+#define TEE_REG_PERI_REGION1_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION1_HIGH_S  2
+
+/** TEE_PERI_REGION_PMS_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION_PMS_REG (DR_REG_TEE_BASE + 0x1c)
+/** TEE_REG_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
+ *  NA
+ */
+#define TEE_REG_LP_CORE_REGION_PMS    0x00000003U
+#define TEE_REG_LP_CORE_REGION_PMS_M  (TEE_REG_LP_CORE_REGION_PMS_V << TEE_REG_LP_CORE_REGION_PMS_S)
+#define TEE_REG_LP_CORE_REGION_PMS_V  0x00000003U
+#define TEE_REG_LP_CORE_REGION_PMS_S  0
+/** TEE_REG_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_REGION_PMS    0x00000003U
+#define TEE_REG_HP_CORE0_UM_REGION_PMS_M  (TEE_REG_HP_CORE0_UM_REGION_PMS_V << TEE_REG_HP_CORE0_UM_REGION_PMS_S)
+#define TEE_REG_HP_CORE0_UM_REGION_PMS_V  0x00000003U
+#define TEE_REG_HP_CORE0_UM_REGION_PMS_S  2
+/** TEE_REG_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_REGION_PMS    0x00000003U
+#define TEE_REG_HP_CORE0_MM_REGION_PMS_M  (TEE_REG_HP_CORE0_MM_REGION_PMS_V << TEE_REG_HP_CORE0_MM_REGION_PMS_S)
+#define TEE_REG_HP_CORE0_MM_REGION_PMS_V  0x00000003U
+#define TEE_REG_HP_CORE0_MM_REGION_PMS_S  4
+/** TEE_REG_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_REGION_PMS    0x00000003U
+#define TEE_REG_HP_CORE1_UM_REGION_PMS_M  (TEE_REG_HP_CORE1_UM_REGION_PMS_V << TEE_REG_HP_CORE1_UM_REGION_PMS_S)
+#define TEE_REG_HP_CORE1_UM_REGION_PMS_V  0x00000003U
+#define TEE_REG_HP_CORE1_UM_REGION_PMS_S  6
+/** TEE_REG_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_REGION_PMS    0x00000003U
+#define TEE_REG_HP_CORE1_MM_REGION_PMS_M  (TEE_REG_HP_CORE1_MM_REGION_PMS_V << TEE_REG_HP_CORE1_MM_REGION_PMS_S)
+#define TEE_REG_HP_CORE1_MM_REGION_PMS_V  0x00000003U
+#define TEE_REG_HP_CORE1_MM_REGION_PMS_S  8
+
+/** TEE_PERI_REGION_2_TO_7_PMS_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION_2_TO_7_PMS_REG (DR_REG_TEE_BASE + 0x20)
+/** TEE_REG_LP_CORE_REGION_2_TO_7_PMS : R/W; bitpos: [5:0]; default: 63;
+ *  NA
+ */
+#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS    0x0000003FU
+#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_M  (TEE_REG_LP_CORE_REGION_2_TO_7_PMS_V << TEE_REG_LP_CORE_REGION_2_TO_7_PMS_S)
+#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_V  0x0000003FU
+#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_S  0
+/** TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS : R/W; bitpos: [11:6]; default: 63;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS    0x0000003FU
+#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_M  (TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_S)
+#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_V  0x0000003FU
+#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_S  6
+/** TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS : R/W; bitpos: [17:12]; default: 63;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS    0x0000003FU
+#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_M  (TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_S)
+#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_V  0x0000003FU
+#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_S  12
+/** TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS : R/W; bitpos: [23:18]; default: 63;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS    0x0000003FU
+#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_M  (TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_S)
+#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_V  0x0000003FU
+#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_S  18
+/** TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS : R/W; bitpos: [29:24]; default: 63;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS    0x0000003FU
+#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_M  (TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_S)
+#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_V  0x0000003FU
+#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_S  24
+
+/** TEE_PERI_REGION2_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION2_LOW_REG (DR_REG_TEE_BASE + 0x24)
+/** TEE_REG_PERI_REGION2_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION2_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION2_LOW_M  (TEE_REG_PERI_REGION2_LOW_V << TEE_REG_PERI_REGION2_LOW_S)
+#define TEE_REG_PERI_REGION2_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION2_LOW_S  2
+
+/** TEE_PERI_REGION2_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION2_HIGH_REG (DR_REG_TEE_BASE + 0x28)
+/** TEE_REG_PERI_REGION2_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION2_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION2_HIGH_M  (TEE_REG_PERI_REGION2_HIGH_V << TEE_REG_PERI_REGION2_HIGH_S)
+#define TEE_REG_PERI_REGION2_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION2_HIGH_S  2
+
+/** TEE_PERI_REGION3_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION3_LOW_REG (DR_REG_TEE_BASE + 0x2c)
+/** TEE_REG_PERI_REGION3_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION3_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION3_LOW_M  (TEE_REG_PERI_REGION3_LOW_V << TEE_REG_PERI_REGION3_LOW_S)
+#define TEE_REG_PERI_REGION3_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION3_LOW_S  2
+
+/** TEE_PERI_REGION3_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION3_HIGH_REG (DR_REG_TEE_BASE + 0x30)
+/** TEE_REG_PERI_REGION3_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION3_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION3_HIGH_M  (TEE_REG_PERI_REGION3_HIGH_V << TEE_REG_PERI_REGION3_HIGH_S)
+#define TEE_REG_PERI_REGION3_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION3_HIGH_S  2
+
+/** TEE_PERI_REGION4_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION4_LOW_REG (DR_REG_TEE_BASE + 0x34)
+/** TEE_REG_PERI_REGION4_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION4_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION4_LOW_M  (TEE_REG_PERI_REGION4_LOW_V << TEE_REG_PERI_REGION4_LOW_S)
+#define TEE_REG_PERI_REGION4_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION4_LOW_S  2
+
+/** TEE_PERI_REGION4_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION4_HIGH_REG (DR_REG_TEE_BASE + 0x38)
+/** TEE_REG_PERI_REGION4_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION4_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION4_HIGH_M  (TEE_REG_PERI_REGION4_HIGH_V << TEE_REG_PERI_REGION4_HIGH_S)
+#define TEE_REG_PERI_REGION4_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION4_HIGH_S  2
+
+/** TEE_PERI_REGION5_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION5_LOW_REG (DR_REG_TEE_BASE + 0x3c)
+/** TEE_REG_PERI_REGION5_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION5_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION5_LOW_M  (TEE_REG_PERI_REGION5_LOW_V << TEE_REG_PERI_REGION5_LOW_S)
+#define TEE_REG_PERI_REGION5_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION5_LOW_S  2
+
+/** TEE_PERI_REGION5_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION5_HIGH_REG (DR_REG_TEE_BASE + 0x40)
+/** TEE_REG_PERI_REGION5_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION5_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION5_HIGH_M  (TEE_REG_PERI_REGION5_HIGH_V << TEE_REG_PERI_REGION5_HIGH_S)
+#define TEE_REG_PERI_REGION5_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION5_HIGH_S  2
+
+/** TEE_PERI_REGION6_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION6_LOW_REG (DR_REG_TEE_BASE + 0x44)
+/** TEE_REG_PERI_REGION6_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION6_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION6_LOW_M  (TEE_REG_PERI_REGION6_LOW_V << TEE_REG_PERI_REGION6_LOW_S)
+#define TEE_REG_PERI_REGION6_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION6_LOW_S  2
+
+/** TEE_PERI_REGION6_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION6_HIGH_REG (DR_REG_TEE_BASE + 0x48)
+/** TEE_REG_PERI_REGION6_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION6_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION6_HIGH_M  (TEE_REG_PERI_REGION6_HIGH_V << TEE_REG_PERI_REGION6_HIGH_S)
+#define TEE_REG_PERI_REGION6_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION6_HIGH_S  2
+
+/** TEE_PERI_REGION7_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION7_LOW_REG (DR_REG_TEE_BASE + 0x4c)
+/** TEE_REG_PERI_REGION7_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION7_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION7_LOW_M  (TEE_REG_PERI_REGION7_LOW_V << TEE_REG_PERI_REGION7_LOW_S)
+#define TEE_REG_PERI_REGION7_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION7_LOW_S  2
+
+/** TEE_PERI_REGION7_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION7_HIGH_REG (DR_REG_TEE_BASE + 0x50)
+/** TEE_REG_PERI_REGION7_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION7_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION7_HIGH_M  (TEE_REG_PERI_REGION7_HIGH_V << TEE_REG_PERI_REGION7_HIGH_S)
+#define TEE_REG_PERI_REGION7_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION7_HIGH_S  2
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_reg.h
new file mode 100644
index 0000000000..11055cc05b
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_reg.h
@@ -0,0 +1,377 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMS_LP_PERI_PMS_DATE_REG register
+ *  Version control register
+ */
+#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_LP_PERI_PMS_BASE + 0x0)
+/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
+ *  Version control register
+ */
+#define PMS_LP_PERI_PMS_DATE    0xFFFFFFFFU
+#define PMS_LP_PERI_PMS_DATE_M  (PMS_LP_PERI_PMS_DATE_V << PMS_LP_PERI_PMS_DATE_S)
+#define PMS_LP_PERI_PMS_DATE_V  0xFFFFFFFFU
+#define PMS_LP_PERI_PMS_DATE_S  0
+
+/** PMS_LP_PERI_PMS_CLK_EN_REG register
+ *  Clock gating register
+ */
+#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_LP_PERI_PMS_BASE + 0x4)
+/** PMS_LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating
+ *  1: Keep the clock always on
+ */
+#define PMS_LP_PERI_PMS_CLK_EN    (BIT(0))
+#define PMS_LP_PERI_PMS_CLK_EN_M  (PMS_LP_PERI_PMS_CLK_EN_V << PMS_LP_PERI_PMS_CLK_EN_S)
+#define PMS_LP_PERI_PMS_CLK_EN_V  0x00000001U
+#define PMS_LP_PERI_PMS_CLK_EN_S  0
+
+/** PMS_LP_MM_LP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for LP CPU in machine mode
+ */
+#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_LP_PERI_PMS_BASE + 0x8)
+/** PMS_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP system
+ *  registers.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_LP_MM_LP_SYSREG_ALLOW_M  (PMS_LP_MM_LP_SYSREG_ALLOW_V << PMS_LP_MM_LP_SYSREG_ALLOW_S)
+#define PMS_LP_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_SYSREG_ALLOW_S  0
+/** PMS_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP
+ *  always-on clock and reset).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW_M  (PMS_LP_MM_LP_AONCLKRST_ALLOW_V << PMS_LP_MM_LP_AONCLKRST_ALLOW_S)
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_LP_MM_LP_TIMER_ALLOW_M  (PMS_LP_MM_LP_TIMER_ALLOW_V << PMS_LP_MM_LP_TIMER_ALLOW_S)
+#define PMS_LP_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_TIMER_ALLOW_S  2
+/** PMS_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP ANAPERI
+ *  (analog peripherals).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_LP_MM_LP_ANAPERI_ALLOW_M  (PMS_LP_MM_LP_ANAPERI_ALLOW_V << PMS_LP_MM_LP_ANAPERI_ALLOW_S)
+#define PMS_LP_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_ANAPERI_ALLOW_S  3
+/** PMS_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP PMU (Power
+ *  Management Unit).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_LP_MM_LP_PMU_ALLOW_M  (PMS_LP_MM_LP_PMU_ALLOW_V << PMS_LP_MM_LP_PMU_ALLOW_S)
+#define PMS_LP_MM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_PMU_ALLOW_S  4
+/** PMS_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog
+ *  timer).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_LP_MM_LP_WDT_ALLOW_M  (PMS_LP_MM_LP_WDT_ALLOW_V << PMS_LP_MM_LP_WDT_ALLOW_S)
+#define PMS_LP_MM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_WDT_ALLOW_S  5
+/** PMS_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_LP_MM_LP_MAILBOX_ALLOW_M  (PMS_LP_MM_LP_MAILBOX_ALLOW_V << PMS_LP_MM_LP_MAILBOX_ALLOW_S)
+#define PMS_LP_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_MAILBOX_ALLOW_S  6
+/** PMS_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_LP_MM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_LP_MM_LP_RTC_ALLOW_M  (PMS_LP_MM_LP_RTC_ALLOW_V << PMS_LP_MM_LP_RTC_ALLOW_S)
+#define PMS_LP_MM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_RTC_ALLOW_S  7
+/** PMS_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access  LP PREICLKRST
+ *  (peripheral clock and reset).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW_M  (PMS_LP_MM_LP_PERICLKRST_ALLOW_V << PMS_LP_MM_LP_PERICLKRST_ALLOW_S)
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access  LP UART.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_UART_ALLOW    (BIT(9))
+#define PMS_LP_MM_LP_UART_ALLOW_M  (PMS_LP_MM_LP_UART_ALLOW_V << PMS_LP_MM_LP_UART_ALLOW_S)
+#define PMS_LP_MM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_UART_ALLOW_S  9
+/** PMS_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_LP_MM_LP_I2C_ALLOW_M  (PMS_LP_MM_LP_I2C_ALLOW_V << PMS_LP_MM_LP_I2C_ALLOW_S)
+#define PMS_LP_MM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_I2C_ALLOW_S  10
+/** PMS_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_LP_MM_LP_SPI_ALLOW_M  (PMS_LP_MM_LP_SPI_ALLOW_V << PMS_LP_MM_LP_SPI_ALLOW_S)
+#define PMS_LP_MM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_SPI_ALLOW_S  11
+/** PMS_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_LP_MM_LP_I2CMST_ALLOW_M  (PMS_LP_MM_LP_I2CMST_ALLOW_V << PMS_LP_MM_LP_I2CMST_ALLOW_S)
+#define PMS_LP_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_I2CMST_ALLOW_S  12
+/** PMS_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_LP_MM_LP_I2S_ALLOW_M  (PMS_LP_MM_LP_I2S_ALLOW_V << PMS_LP_MM_LP_I2S_ALLOW_S)
+#define PMS_LP_MM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_I2S_ALLOW_S  13
+/** PMS_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_LP_MM_LP_ADC_ALLOW_M  (PMS_LP_MM_LP_ADC_ALLOW_V << PMS_LP_MM_LP_ADC_ALLOW_S)
+#define PMS_LP_MM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_ADC_ALLOW_S  14
+/** PMS_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP touch sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_LP_MM_LP_TOUCH_ALLOW_M  (PMS_LP_MM_LP_TOUCH_ALLOW_V << PMS_LP_MM_LP_TOUCH_ALLOW_S)
+#define PMS_LP_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_TOUCH_ALLOW_S  15
+/** PMS_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_LP_MM_LP_IOMUX_ALLOW_M  (PMS_LP_MM_LP_IOMUX_ALLOW_V << PMS_LP_MM_LP_IOMUX_ALLOW_S)
+#define PMS_LP_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_IOMUX_ALLOW_S  16
+/** PMS_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP INTR
+ *  (interrupt).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_LP_MM_LP_INTR_ALLOW_M  (PMS_LP_MM_LP_INTR_ALLOW_V << PMS_LP_MM_LP_INTR_ALLOW_S)
+#define PMS_LP_MM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_INTR_ALLOW_S  17
+/** PMS_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_LP_MM_LP_EFUSE_ALLOW_M  (PMS_LP_MM_LP_EFUSE_ALLOW_V << PMS_LP_MM_LP_EFUSE_ALLOW_S)
+#define PMS_LP_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_EFUSE_ALLOW_S  18
+/** PMS_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_LP_MM_LP_PMS_ALLOW_M  (PMS_LP_MM_LP_PMS_ALLOW_V << PMS_LP_MM_LP_PMS_ALLOW_S)
+#define PMS_LP_MM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_PMS_ALLOW_S  19
+/** PMS_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_LP_MM_HP2LP_PMS_ALLOW_M  (PMS_LP_MM_HP2LP_PMS_ALLOW_V << PMS_LP_MM_HP2LP_PMS_ALLOW_S)
+#define PMS_LP_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP2LP_PMS_ALLOW_S  20
+/** PMS_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_LP_MM_LP_TSENS_ALLOW_M  (PMS_LP_MM_LP_TSENS_ALLOW_V << PMS_LP_MM_LP_TSENS_ALLOW_S)
+#define PMS_LP_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_TSENS_ALLOW_S  21
+/** PMS_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware
+ *  Unique Key).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_LP_MM_LP_HUK_ALLOW_M  (PMS_LP_MM_LP_HUK_ALLOW_V << PMS_LP_MM_LP_HUK_ALLOW_S)
+#define PMS_LP_MM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_HUK_ALLOW_S  22
+/** PMS_LP_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_LP_MM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_LP_MM_LP_SRAM_ALLOW_M  (PMS_LP_MM_LP_SRAM_ALLOW_V << PMS_LP_MM_LP_SRAM_ALLOW_S)
+#define PMS_LP_MM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_SRAM_ALLOW_S  23
+
+/** PMS_PERI_REGION0_LOW_REG register
+ *  Region0 start address configuration register
+ */
+#define PMS_PERI_REGION0_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0xc)
+/** PMS_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  Configures the high 30 bits of the start address of peripheral register's region0.
+ */
+#define PMS_PERI_REGION0_LOW    0x3FFFFFFFU
+#define PMS_PERI_REGION0_LOW_M  (PMS_PERI_REGION0_LOW_V << PMS_PERI_REGION0_LOW_S)
+#define PMS_PERI_REGION0_LOW_V  0x3FFFFFFFU
+#define PMS_PERI_REGION0_LOW_S  2
+
+/** PMS_PERI_REGION0_HIGH_REG register
+ *  Region0 end address configuration register
+ */
+#define PMS_PERI_REGION0_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x10)
+/** PMS_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  Configures the high 30 bits of the end address of peripheral register's region0.
+ */
+#define PMS_PERI_REGION0_HIGH    0x3FFFFFFFU
+#define PMS_PERI_REGION0_HIGH_M  (PMS_PERI_REGION0_HIGH_V << PMS_PERI_REGION0_HIGH_S)
+#define PMS_PERI_REGION0_HIGH_V  0x3FFFFFFFU
+#define PMS_PERI_REGION0_HIGH_S  2
+
+/** PMS_PERI_REGION1_LOW_REG register
+ *  Region1 start address configuration register
+ */
+#define PMS_PERI_REGION1_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x14)
+/** PMS_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  Configures the high 30 bits of the start address of peripheral register's region1.
+ */
+#define PMS_PERI_REGION1_LOW    0x3FFFFFFFU
+#define PMS_PERI_REGION1_LOW_M  (PMS_PERI_REGION1_LOW_V << PMS_PERI_REGION1_LOW_S)
+#define PMS_PERI_REGION1_LOW_V  0x3FFFFFFFU
+#define PMS_PERI_REGION1_LOW_S  2
+
+/** PMS_PERI_REGION1_HIGH_REG register
+ *  Region1 end address configuration register
+ */
+#define PMS_PERI_REGION1_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x18)
+/** PMS_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  Configures the high 30 bits of the end address of peripheral register's region1.
+ */
+#define PMS_PERI_REGION1_HIGH    0x3FFFFFFFU
+#define PMS_PERI_REGION1_HIGH_M  (PMS_PERI_REGION1_HIGH_V << PMS_PERI_REGION1_HIGH_S)
+#define PMS_PERI_REGION1_HIGH_V  0x3FFFFFFFU
+#define PMS_PERI_REGION1_HIGH_S  2
+
+/** PMS_PERI_REGION_PMS_REG register
+ *  Permission register of  region
+ */
+#define PMS_PERI_REGION_PMS_REG (DR_REG_LP_PERI_PMS_BASE + 0x1c)
+/** PMS_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
+ *  Configures whether LP core in machine mode has permission to access address region0
+ *  and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_LP_CORE_REGION_PMS    0x00000003U
+#define PMS_LP_CORE_REGION_PMS_M  (PMS_LP_CORE_REGION_PMS_V << PMS_LP_CORE_REGION_PMS_S)
+#define PMS_LP_CORE_REGION_PMS_V  0x00000003U
+#define PMS_LP_CORE_REGION_PMS_S  0
+/** PMS_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
+ *  Configures whether HP CPU0 in user mode has permission to access address region0
+ *  and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE0_UM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE0_UM_REGION_PMS_M  (PMS_HP_CORE0_UM_REGION_PMS_V << PMS_HP_CORE0_UM_REGION_PMS_S)
+#define PMS_HP_CORE0_UM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE0_UM_REGION_PMS_S  2
+/** PMS_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
+ *  Configures whether HP CPU0 in machine mode has permission to access address region0
+ *  and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE0_MM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE0_MM_REGION_PMS_M  (PMS_HP_CORE0_MM_REGION_PMS_V << PMS_HP_CORE0_MM_REGION_PMS_S)
+#define PMS_HP_CORE0_MM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE0_MM_REGION_PMS_S  4
+/** PMS_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
+ *  Configures whether HP CPU1 in user mode has permission to access address region0
+ *  and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE1_UM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE1_UM_REGION_PMS_M  (PMS_HP_CORE1_UM_REGION_PMS_V << PMS_HP_CORE1_UM_REGION_PMS_S)
+#define PMS_HP_CORE1_UM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE1_UM_REGION_PMS_S  6
+/** PMS_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
+ *  Configures whether HP CPU1 in machine mode has permission to access address region0
+ *  and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE1_MM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE1_MM_REGION_PMS_M  (PMS_HP_CORE1_MM_REGION_PMS_V << PMS_HP_CORE1_MM_REGION_PMS_S)
+#define PMS_HP_CORE1_MM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE1_MM_REGION_PMS_S  8
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_struct.h
new file mode 100644
index 0000000000..691228182d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_struct.h
@@ -0,0 +1,508 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: TEE PMS DATE REG */
+/** Type of pms_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tee_date : R/W; bitpos: [31:0]; default: 2363943;
+         *  NA
+         */
+        uint32_t tee_date:32;
+    };
+    uint32_t val;
+} tee_pms_date_reg_t;
+
+
+/** Group: TEE PMS CLK EN REG */
+/** Type of pms_clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_pms_clk_en_reg_t;
+
+
+/** Group: TEE LP MM PMS REG0 REG */
+/** Type of lp_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_sysreg_allow:1;
+        /** reg_lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_aonclkrst_allow:1;
+        /** reg_lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_timer_allow:1;
+        /** reg_lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_anaperi_allow:1;
+        /** reg_lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_pmu_allow:1;
+        /** reg_lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_wdt_allow:1;
+        /** reg_lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_mailbox_allow:1;
+        /** reg_lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_rtc_allow:1;
+        /** reg_lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_periclkrst_allow:1;
+        /** reg_lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_uart_allow:1;
+        /** reg_lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_i2c_allow:1;
+        /** reg_lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_spi_allow:1;
+        /** reg_lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_i2cmst_allow:1;
+        /** reg_lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_i2s_allow:1;
+        /** reg_lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_adc_allow:1;
+        /** reg_lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_touch_allow:1;
+        /** reg_lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_iomux_allow:1;
+        /** reg_lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_intr_allow:1;
+        /** reg_lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_efuse_allow:1;
+        /** reg_lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_pms_allow:1;
+        /** reg_lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp2lp_pms_allow:1;
+        /** reg_lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_tsens_allow:1;
+        /** reg_lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_huk_allow:1;
+        /** reg_lp_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_tcm_ram_allow:1;
+        /** reg_lp_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_trng_allow:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} tee_lp_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE PERI REGION0 LOW REG */
+/** Type of peri_region0_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region0_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region0_low:30;
+    };
+    uint32_t val;
+} tee_peri_region0_low_reg_t;
+
+
+/** Group: TEE PERI REGION0 HIGH REG */
+/** Type of peri_region0_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region0_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region0_high:30;
+    };
+    uint32_t val;
+} tee_peri_region0_high_reg_t;
+
+
+/** Group: TEE PERI REGION1 LOW REG */
+/** Type of peri_region1_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region1_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region1_low:30;
+    };
+    uint32_t val;
+} tee_peri_region1_low_reg_t;
+
+
+/** Group: TEE PERI REGION1 HIGH REG */
+/** Type of peri_region1_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region1_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region1_high:30;
+    };
+    uint32_t val;
+} tee_peri_region1_high_reg_t;
+
+
+/** Group: TEE PERI REGION PMS REG */
+/** Type of peri_region_pms register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_core_region_pms : R/W; bitpos: [1:0]; default: 3;
+         *  NA
+         */
+        uint32_t reg_lp_core_region_pms:2;
+        /** reg_hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_region_pms:2;
+        /** reg_hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_region_pms:2;
+        /** reg_hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_region_pms:2;
+        /** reg_hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_region_pms:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} tee_peri_region_pms_reg_t;
+
+
+/** Group: TEE PERI REGION 2 TO 7 PMS REG */
+/** Type of peri_region_2_to_7_pms register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_core_region_2_to_7_pms : R/W; bitpos: [5:0]; default: 63;
+         *  NA
+         */
+        uint32_t reg_lp_core_region_2_to_7_pms:6;
+        /** reg_hp_core0_um_region_2_to_7_pms : R/W; bitpos: [11:6]; default: 63;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_region_2_to_7_pms:6;
+        /** reg_hp_core0_mm_region_2_to_7_pms : R/W; bitpos: [17:12]; default: 63;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_region_2_to_7_pms:6;
+        /** reg_hp_core1_um_region_2_to_7_pms : R/W; bitpos: [23:18]; default: 63;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_region_2_to_7_pms:6;
+        /** reg_hp_core1_mm_region_2_to_7_pms : R/W; bitpos: [29:24]; default: 63;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_region_2_to_7_pms:6;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_peri_region_2_to_7_pms_reg_t;
+
+
+/** Group: TEE PERI REGION2 LOW REG */
+/** Type of peri_region2_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region2_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region2_low:30;
+    };
+    uint32_t val;
+} tee_peri_region2_low_reg_t;
+
+
+/** Group: TEE PERI REGION2 HIGH REG */
+/** Type of peri_region2_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region2_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region2_high:30;
+    };
+    uint32_t val;
+} tee_peri_region2_high_reg_t;
+
+
+/** Group: TEE PERI REGION3 LOW REG */
+/** Type of peri_region3_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region3_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region3_low:30;
+    };
+    uint32_t val;
+} tee_peri_region3_low_reg_t;
+
+
+/** Group: TEE PERI REGION3 HIGH REG */
+/** Type of peri_region3_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region3_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region3_high:30;
+    };
+    uint32_t val;
+} tee_peri_region3_high_reg_t;
+
+
+/** Group: TEE PERI REGION4 LOW REG */
+/** Type of peri_region4_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region4_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region4_low:30;
+    };
+    uint32_t val;
+} tee_peri_region4_low_reg_t;
+
+
+/** Group: TEE PERI REGION4 HIGH REG */
+/** Type of peri_region4_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region4_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region4_high:30;
+    };
+    uint32_t val;
+} tee_peri_region4_high_reg_t;
+
+
+/** Group: TEE PERI REGION5 LOW REG */
+/** Type of peri_region5_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region5_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region5_low:30;
+    };
+    uint32_t val;
+} tee_peri_region5_low_reg_t;
+
+
+/** Group: TEE PERI REGION5 HIGH REG */
+/** Type of peri_region5_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region5_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region5_high:30;
+    };
+    uint32_t val;
+} tee_peri_region5_high_reg_t;
+
+
+/** Group: TEE PERI REGION6 LOW REG */
+/** Type of peri_region6_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region6_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region6_low:30;
+    };
+    uint32_t val;
+} tee_peri_region6_low_reg_t;
+
+
+/** Group: TEE PERI REGION6 HIGH REG */
+/** Type of peri_region6_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region6_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region6_high:30;
+    };
+    uint32_t val;
+} tee_peri_region6_high_reg_t;
+
+
+/** Group: TEE PERI REGION7 LOW REG */
+/** Type of peri_region7_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region7_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region7_low:30;
+    };
+    uint32_t val;
+} tee_peri_region7_low_reg_t;
+
+
+/** Group: TEE PERI REGION7 HIGH REG */
+/** Type of peri_region7_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region7_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region7_high:30;
+    };
+    uint32_t val;
+} tee_peri_region7_high_reg_t;
+
+
+typedef struct {
+    volatile tee_pms_date_reg_t pms_date;
+    volatile tee_pms_clk_en_reg_t pms_clk_en;
+    volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
+    volatile tee_peri_region0_low_reg_t peri_region0_low;
+    volatile tee_peri_region0_high_reg_t peri_region0_high;
+    volatile tee_peri_region1_low_reg_t peri_region1_low;
+    volatile tee_peri_region1_high_reg_t peri_region1_high;
+    volatile tee_peri_region_pms_reg_t peri_region_pms;
+    volatile tee_peri_region_2_to_7_pms_reg_t peri_region_2_to_7_pms;
+    volatile tee_peri_region2_low_reg_t peri_region2_low;
+    volatile tee_peri_region2_high_reg_t peri_region2_high;
+    volatile tee_peri_region3_low_reg_t peri_region3_low;
+    volatile tee_peri_region3_high_reg_t peri_region3_high;
+    volatile tee_peri_region4_low_reg_t peri_region4_low;
+    volatile tee_peri_region4_high_reg_t peri_region4_high;
+    volatile tee_peri_region5_low_reg_t peri_region5_low;
+    volatile tee_peri_region5_high_reg_t peri_region5_high;
+    volatile tee_peri_region6_low_reg_t peri_region6_low;
+    volatile tee_peri_region6_high_reg_t peri_region6_high;
+    volatile tee_peri_region7_low_reg_t peri_region7_low;
+    volatile tee_peri_region7_high_reg_t peri_region7_high;
+} tee_dev_t;
+
+extern tee_dev_t LP_PERI_PMS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dev_t) == 0x54, "Invalid size of tee_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_reg.h
new file mode 100644
index 0000000000..3d6bb0371a
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_reg.h
@@ -0,0 +1,1375 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_SPI_CMD_REG register
+ *  Command control register
+ */
+#define LP_SPI_CMD_REG (DR_REG_LP_BASE + 0x0)
+/** LP_REG_UPDATE : WT; bitpos: [23]; default: 0;
+ *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+ *  clock domain, which is only used in SPI master mode.
+ */
+#define LP_REG_UPDATE    (BIT(23))
+#define LP_REG_UPDATE_M  (LP_REG_UPDATE_V << LP_REG_UPDATE_S)
+#define LP_REG_UPDATE_V  0x00000001U
+#define LP_REG_UPDATE_S  23
+/** LP_REG_USR : R/W/SC; bitpos: [24]; default: 0;
+ *  User define command enable.  An operation will be triggered when the bit is set.
+ *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+ *  changed by CONF_buf.
+ */
+#define LP_REG_USR    (BIT(24))
+#define LP_REG_USR_M  (LP_REG_USR_V << LP_REG_USR_S)
+#define LP_REG_USR_V  0x00000001U
+#define LP_REG_USR_S  24
+
+/** LP_SPI_ADDR_REG register
+ *  Address value register
+ */
+#define LP_SPI_ADDR_REG (DR_REG_LP_BASE + 0x4)
+/** LP_REG_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  Address to slave. Can be configured in CONF state.
+ */
+#define LP_REG_USR_ADDR_VALUE    0xFFFFFFFFU
+#define LP_REG_USR_ADDR_VALUE_M  (LP_REG_USR_ADDR_VALUE_V << LP_REG_USR_ADDR_VALUE_S)
+#define LP_REG_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define LP_REG_USR_ADDR_VALUE_S  0
+
+/** LP_SPI_CTRL_REG register
+ *  SPI control register
+ */
+#define LP_SPI_CTRL_REG (DR_REG_LP_BASE + 0x8)
+/** LP_REG_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
+ *  In the dummy phase the signal level of spi is output by the spi controller. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_DUMMY_OUT    (BIT(3))
+#define LP_REG_DUMMY_OUT_M  (LP_REG_DUMMY_OUT_V << LP_REG_DUMMY_OUT_S)
+#define LP_REG_DUMMY_OUT_V  0x00000001U
+#define LP_REG_DUMMY_OUT_S  3
+/** LP_REG_Q_POL : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+ *  CONF state.
+ */
+#define LP_REG_Q_POL    (BIT(18))
+#define LP_REG_Q_POL_M  (LP_REG_Q_POL_V << LP_REG_Q_POL_S)
+#define LP_REG_Q_POL_V  0x00000001U
+#define LP_REG_Q_POL_S  18
+/** LP_REG_D_POL : R/W; bitpos: [19]; default: 1;
+ *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+ *  CONF state.
+ */
+#define LP_REG_D_POL    (BIT(19))
+#define LP_REG_D_POL_M  (LP_REG_D_POL_V << LP_REG_D_POL_S)
+#define LP_REG_D_POL_V  0x00000001U
+#define LP_REG_D_POL_S  19
+/** LP_REG_RD_BIT_ORDER : R/W; bitpos: [25]; default: 0;
+ *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+ *  state.
+ */
+#define LP_REG_RD_BIT_ORDER    (BIT(25))
+#define LP_REG_RD_BIT_ORDER_M  (LP_REG_RD_BIT_ORDER_V << LP_REG_RD_BIT_ORDER_S)
+#define LP_REG_RD_BIT_ORDER_V  0x00000001U
+#define LP_REG_RD_BIT_ORDER_S  25
+/** LP_REG_WR_BIT_ORDER : R/W; bitpos: [26]; default: 0;
+ *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_WR_BIT_ORDER    (BIT(26))
+#define LP_REG_WR_BIT_ORDER_M  (LP_REG_WR_BIT_ORDER_V << LP_REG_WR_BIT_ORDER_S)
+#define LP_REG_WR_BIT_ORDER_V  0x00000001U
+#define LP_REG_WR_BIT_ORDER_S  26
+
+/** LP_SPI_CLOCK_REG register
+ *  SPI clock control register
+ */
+#define LP_SPI_CLOCK_REG (DR_REG_LP_BASE + 0xc)
+/** LP_REG_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
+ *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+ *  0. Can be configured in CONF state.
+ */
+#define LP_REG_CLKCNT_L    0x0000003FU
+#define LP_REG_CLKCNT_L_M  (LP_REG_CLKCNT_L_V << LP_REG_CLKCNT_L_S)
+#define LP_REG_CLKCNT_L_V  0x0000003FU
+#define LP_REG_CLKCNT_L_S  0
+/** LP_REG_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
+ *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+ *  must be 0. Can be configured in CONF state.
+ */
+#define LP_REG_CLKCNT_H    0x0000003FU
+#define LP_REG_CLKCNT_H_M  (LP_REG_CLKCNT_H_V << LP_REG_CLKCNT_H_S)
+#define LP_REG_CLKCNT_H_V  0x0000003FU
+#define LP_REG_CLKCNT_H_S  6
+/** LP_REG_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
+ *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+ *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+ */
+#define LP_REG_CLKCNT_N    0x0000003FU
+#define LP_REG_CLKCNT_N_M  (LP_REG_CLKCNT_N_V << LP_REG_CLKCNT_N_S)
+#define LP_REG_CLKCNT_N_V  0x0000003FU
+#define LP_REG_CLKCNT_N_S  12
+/** LP_REG_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
+ *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+ */
+#define LP_REG_CLKDIV_PRE    0x0000000FU
+#define LP_REG_CLKDIV_PRE_M  (LP_REG_CLKDIV_PRE_V << LP_REG_CLKDIV_PRE_S)
+#define LP_REG_CLKDIV_PRE_V  0x0000000FU
+#define LP_REG_CLKDIV_PRE_S  18
+/** LP_REG_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
+ *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+ *  clock. Can be configured in CONF state.
+ */
+#define LP_REG_CLK_EQU_SYSCLK    (BIT(31))
+#define LP_REG_CLK_EQU_SYSCLK_M  (LP_REG_CLK_EQU_SYSCLK_V << LP_REG_CLK_EQU_SYSCLK_S)
+#define LP_REG_CLK_EQU_SYSCLK_V  0x00000001U
+#define LP_REG_CLK_EQU_SYSCLK_S  31
+
+/** LP_SPI_USER_REG register
+ *  SPI USER control register
+ */
+#define LP_SPI_USER_REG (DR_REG_LP_BASE + 0x10)
+/** LP_REG_DOUTDIN : R/W; bitpos: [0]; default: 0;
+ *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_DOUTDIN    (BIT(0))
+#define LP_REG_DOUTDIN_M  (LP_REG_DOUTDIN_V << LP_REG_DOUTDIN_S)
+#define LP_REG_DOUTDIN_V  0x00000001U
+#define LP_REG_DOUTDIN_S  0
+/** LP_REG_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
+ *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+ *  spi_ck_i. 1:tsck = !spi_ck_i.
+ */
+#define LP_REG_TSCK_I_EDGE    (BIT(5))
+#define LP_REG_TSCK_I_EDGE_M  (LP_REG_TSCK_I_EDGE_V << LP_REG_TSCK_I_EDGE_S)
+#define LP_REG_TSCK_I_EDGE_V  0x00000001U
+#define LP_REG_TSCK_I_EDGE_S  5
+/** LP_REG_CS_HOLD : R/W; bitpos: [6]; default: 1;
+ *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_CS_HOLD    (BIT(6))
+#define LP_REG_CS_HOLD_M  (LP_REG_CS_HOLD_V << LP_REG_CS_HOLD_S)
+#define LP_REG_CS_HOLD_V  0x00000001U
+#define LP_REG_CS_HOLD_S  6
+/** LP_REG_CS_SETUP : R/W; bitpos: [7]; default: 1;
+ *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_CS_SETUP    (BIT(7))
+#define LP_REG_CS_SETUP_M  (LP_REG_CS_SETUP_V << LP_REG_CS_SETUP_S)
+#define LP_REG_CS_SETUP_V  0x00000001U
+#define LP_REG_CS_SETUP_S  7
+/** LP_REG_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
+ *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+ *  !spi_ck_i. 1:rsck = spi_ck_i.
+ */
+#define LP_REG_RSCK_I_EDGE    (BIT(8))
+#define LP_REG_RSCK_I_EDGE_M  (LP_REG_RSCK_I_EDGE_V << LP_REG_RSCK_I_EDGE_S)
+#define LP_REG_RSCK_I_EDGE_V  0x00000001U
+#define LP_REG_RSCK_I_EDGE_S  8
+/** LP_REG_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+ *  be configured in CONF state.
+ */
+#define LP_REG_CK_OUT_EDGE    (BIT(9))
+#define LP_REG_CK_OUT_EDGE_M  (LP_REG_CK_OUT_EDGE_V << LP_REG_CK_OUT_EDGE_S)
+#define LP_REG_CK_OUT_EDGE_V  0x00000001U
+#define LP_REG_CK_OUT_EDGE_S  9
+/** LP_REG_SIO : R/W; bitpos: [17]; default: 0;
+ *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+ *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+ */
+#define LP_REG_SIO    (BIT(17))
+#define LP_REG_SIO_M  (LP_REG_SIO_V << LP_REG_SIO_S)
+#define LP_REG_SIO_V  0x00000001U
+#define LP_REG_SIO_S  17
+/** LP_REG_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+ *  disable. Can be configured in CONF state.
+ */
+#define LP_REG_USR_MISO_HIGHPART    (BIT(24))
+#define LP_REG_USR_MISO_HIGHPART_M  (LP_REG_USR_MISO_HIGHPART_V << LP_REG_USR_MISO_HIGHPART_S)
+#define LP_REG_USR_MISO_HIGHPART_V  0x00000001U
+#define LP_REG_USR_MISO_HIGHPART_S  24
+/** LP_REG_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+ *  0: disable.  Can be configured in CONF state.
+ */
+#define LP_REG_USR_MOSI_HIGHPART    (BIT(25))
+#define LP_REG_USR_MOSI_HIGHPART_M  (LP_REG_USR_MOSI_HIGHPART_V << LP_REG_USR_MOSI_HIGHPART_S)
+#define LP_REG_USR_MOSI_HIGHPART_V  0x00000001U
+#define LP_REG_USR_MOSI_HIGHPART_S  25
+/** LP_REG_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+ *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+ *  CONF state.
+ */
+#define LP_REG_USR_DUMMY_IDLE    (BIT(26))
+#define LP_REG_USR_DUMMY_IDLE_M  (LP_REG_USR_DUMMY_IDLE_V << LP_REG_USR_DUMMY_IDLE_S)
+#define LP_REG_USR_DUMMY_IDLE_V  0x00000001U
+#define LP_REG_USR_DUMMY_IDLE_S  26
+/** LP_REG_USR_MOSI : R/W; bitpos: [27]; default: 0;
+ *  This bit enable the write-data phase of an operation. Can be configured in CONF
+ *  state.
+ */
+#define LP_REG_USR_MOSI    (BIT(27))
+#define LP_REG_USR_MOSI_M  (LP_REG_USR_MOSI_V << LP_REG_USR_MOSI_S)
+#define LP_REG_USR_MOSI_V  0x00000001U
+#define LP_REG_USR_MOSI_S  27
+/** LP_REG_USR_MISO : R/W; bitpos: [28]; default: 0;
+ *  This bit enable the read-data phase of an operation. Can be configured in CONF
+ *  state.
+ */
+#define LP_REG_USR_MISO    (BIT(28))
+#define LP_REG_USR_MISO_M  (LP_REG_USR_MISO_V << LP_REG_USR_MISO_S)
+#define LP_REG_USR_MISO_V  0x00000001U
+#define LP_REG_USR_MISO_S  28
+/** LP_REG_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+ *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+ */
+#define LP_REG_USR_DUMMY    (BIT(29))
+#define LP_REG_USR_DUMMY_M  (LP_REG_USR_DUMMY_V << LP_REG_USR_DUMMY_S)
+#define LP_REG_USR_DUMMY_V  0x00000001U
+#define LP_REG_USR_DUMMY_S  29
+/** LP_REG_USR_ADDR : R/W; bitpos: [30]; default: 0;
+ *  This bit enable the address phase of an operation. Can be configured in CONF state.
+ */
+#define LP_REG_USR_ADDR    (BIT(30))
+#define LP_REG_USR_ADDR_M  (LP_REG_USR_ADDR_V << LP_REG_USR_ADDR_S)
+#define LP_REG_USR_ADDR_V  0x00000001U
+#define LP_REG_USR_ADDR_S  30
+/** LP_REG_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+ *  This bit enable the command phase of an operation. Can be configured in CONF state.
+ */
+#define LP_REG_USR_COMMAND    (BIT(31))
+#define LP_REG_USR_COMMAND_M  (LP_REG_USR_COMMAND_V << LP_REG_USR_COMMAND_S)
+#define LP_REG_USR_COMMAND_V  0x00000001U
+#define LP_REG_USR_COMMAND_S  31
+
+/** LP_SPI_USER1_REG register
+ *  SPI USER control register 1
+ */
+#define LP_SPI_USER1_REG (DR_REG_LP_BASE + 0x14)
+/** LP_REG_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
+ *  The length in spi_clk cycles of dummy phase. The register value shall be
+ *  (cycle_num-1). Can be configured in CONF state.
+ */
+#define LP_REG_USR_DUMMY_CYCLELEN    0x000000FFU
+#define LP_REG_USR_DUMMY_CYCLELEN_M  (LP_REG_USR_DUMMY_CYCLELEN_V << LP_REG_USR_DUMMY_CYCLELEN_S)
+#define LP_REG_USR_DUMMY_CYCLELEN_V  0x000000FFU
+#define LP_REG_USR_DUMMY_CYCLELEN_S  0
+/** LP_REG_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
+ *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+ *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+ *  GP-SPI master FD/HD-mode.
+ */
+#define LP_REG_MST_WFULL_ERR_END_EN    (BIT(16))
+#define LP_REG_MST_WFULL_ERR_END_EN_M  (LP_REG_MST_WFULL_ERR_END_EN_V << LP_REG_MST_WFULL_ERR_END_EN_S)
+#define LP_REG_MST_WFULL_ERR_END_EN_V  0x00000001U
+#define LP_REG_MST_WFULL_ERR_END_EN_S  16
+/** LP_REG_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
+ *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+ *  bit. Can be configured in CONF state.
+ */
+#define LP_REG_CS_SETUP_TIME    0x0000001FU
+#define LP_REG_CS_SETUP_TIME_M  (LP_REG_CS_SETUP_TIME_V << LP_REG_CS_SETUP_TIME_S)
+#define LP_REG_CS_SETUP_TIME_V  0x0000001FU
+#define LP_REG_CS_SETUP_TIME_S  17
+/** LP_REG_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
+ *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+ *  Can be configured in CONF state.
+ */
+#define LP_REG_CS_HOLD_TIME    0x0000001FU
+#define LP_REG_CS_HOLD_TIME_M  (LP_REG_CS_HOLD_TIME_V << LP_REG_CS_HOLD_TIME_S)
+#define LP_REG_CS_HOLD_TIME_V  0x0000001FU
+#define LP_REG_CS_HOLD_TIME_S  22
+/** LP_REG_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
+ *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+ *  be configured in CONF state.
+ */
+#define LP_REG_USR_ADDR_BITLEN    0x0000001FU
+#define LP_REG_USR_ADDR_BITLEN_M  (LP_REG_USR_ADDR_BITLEN_V << LP_REG_USR_ADDR_BITLEN_S)
+#define LP_REG_USR_ADDR_BITLEN_V  0x0000001FU
+#define LP_REG_USR_ADDR_BITLEN_S  27
+
+/** LP_SPI_USER2_REG register
+ *  SPI USER control register 2
+ */
+#define LP_SPI_USER2_REG (DR_REG_LP_BASE + 0x18)
+/** LP_REG_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  The value of  command. Can be configured in CONF state.
+ */
+#define LP_REG_USR_COMMAND_VALUE    0x0000FFFFU
+#define LP_REG_USR_COMMAND_VALUE_M  (LP_REG_USR_COMMAND_VALUE_V << LP_REG_USR_COMMAND_VALUE_S)
+#define LP_REG_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define LP_REG_USR_COMMAND_VALUE_S  0
+/** LP_REG_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
+ *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+ *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+ *  is valid in GP-SPI master FD/HD-mode.
+ */
+#define LP_REG_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define LP_REG_MST_REMPTY_ERR_END_EN_M  (LP_REG_MST_REMPTY_ERR_END_EN_V << LP_REG_MST_REMPTY_ERR_END_EN_S)
+#define LP_REG_MST_REMPTY_ERR_END_EN_V  0x00000001U
+#define LP_REG_MST_REMPTY_ERR_END_EN_S  27
+/** LP_REG_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+ *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+ *  be configured in CONF state.
+ */
+#define LP_REG_USR_COMMAND_BITLEN    0x0000000FU
+#define LP_REG_USR_COMMAND_BITLEN_M  (LP_REG_USR_COMMAND_BITLEN_V << LP_REG_USR_COMMAND_BITLEN_S)
+#define LP_REG_USR_COMMAND_BITLEN_V  0x0000000FU
+#define LP_REG_USR_COMMAND_BITLEN_S  28
+
+/** LP_SPI_MS_DLEN_REG register
+ *  SPI data bit length control register
+ */
+#define LP_SPI_MS_DLEN_REG (DR_REG_LP_BASE + 0x1c)
+/** LP_REG_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  The value of these bits is the configured SPI transmission data bit length in
+ *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+ *  the configured bit length in slave mode DMA RX controlled transfer. The register
+ *  value shall be (bit_num-1). Can be configured in CONF state.
+ */
+#define LP_REG_MS_DATA_BITLEN    0x0003FFFFU
+#define LP_REG_MS_DATA_BITLEN_M  (LP_REG_MS_DATA_BITLEN_V << LP_REG_MS_DATA_BITLEN_S)
+#define LP_REG_MS_DATA_BITLEN_V  0x0003FFFFU
+#define LP_REG_MS_DATA_BITLEN_S  0
+
+/** LP_SPI_MISC_REG register
+ *  SPI misc register
+ */
+#define LP_SPI_MISC_REG (DR_REG_LP_BASE + 0x20)
+/** LP_REG_CS0_DIS : R/W; bitpos: [0]; default: 0;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define LP_REG_CS0_DIS    (BIT(0))
+#define LP_REG_CS0_DIS_M  (LP_REG_CS0_DIS_V << LP_REG_CS0_DIS_S)
+#define LP_REG_CS0_DIS_V  0x00000001U
+#define LP_REG_CS0_DIS_S  0
+/** LP_REG_CK_DIS : R/W; bitpos: [6]; default: 0;
+ *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+ */
+#define LP_REG_CK_DIS    (BIT(6))
+#define LP_REG_CK_DIS_M  (LP_REG_CK_DIS_V << LP_REG_CK_DIS_S)
+#define LP_REG_CK_DIS_V  0x00000001U
+#define LP_REG_CK_DIS_S  6
+/** LP_REG_MASTER_CS_POL : R/W; bitpos: [9:7]; default: 0;
+ *  In the master mode the bits are the polarity of spi cs line, the value is
+ *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+ */
+#define LP_REG_MASTER_CS_POL    0x00000007U
+#define LP_REG_MASTER_CS_POL_M  (LP_REG_MASTER_CS_POL_V << LP_REG_MASTER_CS_POL_S)
+#define LP_REG_MASTER_CS_POL_V  0x00000007U
+#define LP_REG_MASTER_CS_POL_S  7
+/** LP_REG_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
+ *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+ *  CONF state.
+ */
+#define LP_REG_SLAVE_CS_POL    (BIT(23))
+#define LP_REG_SLAVE_CS_POL_M  (LP_REG_SLAVE_CS_POL_V << LP_REG_SLAVE_CS_POL_S)
+#define LP_REG_SLAVE_CS_POL_V  0x00000001U
+#define LP_REG_SLAVE_CS_POL_S  23
+/** LP_REG_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
+ *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_CK_IDLE_EDGE    (BIT(29))
+#define LP_REG_CK_IDLE_EDGE_M  (LP_REG_CK_IDLE_EDGE_V << LP_REG_CK_IDLE_EDGE_S)
+#define LP_REG_CK_IDLE_EDGE_V  0x00000001U
+#define LP_REG_CK_IDLE_EDGE_S  29
+/** LP_REG_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
+ *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+ */
+#define LP_REG_CS_KEEP_ACTIVE    (BIT(30))
+#define LP_REG_CS_KEEP_ACTIVE_M  (LP_REG_CS_KEEP_ACTIVE_V << LP_REG_CS_KEEP_ACTIVE_S)
+#define LP_REG_CS_KEEP_ACTIVE_V  0x00000001U
+#define LP_REG_CS_KEEP_ACTIVE_S  30
+
+/** LP_SPI_DIN_MODE_REG register
+ *  SPI input delay mode configuration
+ */
+#define LP_SPI_DIN_MODE_REG (DR_REG_LP_BASE + 0x24)
+/** LP_REG_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define LP_REG_DIN0_MODE    0x00000003U
+#define LP_REG_DIN0_MODE_M  (LP_REG_DIN0_MODE_V << LP_REG_DIN0_MODE_S)
+#define LP_REG_DIN0_MODE_V  0x00000003U
+#define LP_REG_DIN0_MODE_S  0
+/** LP_REG_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define LP_REG_DIN1_MODE    0x00000003U
+#define LP_REG_DIN1_MODE_M  (LP_REG_DIN1_MODE_V << LP_REG_DIN1_MODE_S)
+#define LP_REG_DIN1_MODE_V  0x00000003U
+#define LP_REG_DIN1_MODE_S  2
+/** LP_REG_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define LP_REG_DIN2_MODE    0x00000003U
+#define LP_REG_DIN2_MODE_M  (LP_REG_DIN2_MODE_V << LP_REG_DIN2_MODE_S)
+#define LP_REG_DIN2_MODE_V  0x00000003U
+#define LP_REG_DIN2_MODE_S  4
+/** LP_REG_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define LP_REG_DIN3_MODE    0x00000003U
+#define LP_REG_DIN3_MODE_M  (LP_REG_DIN3_MODE_V << LP_REG_DIN3_MODE_S)
+#define LP_REG_DIN3_MODE_V  0x00000003U
+#define LP_REG_DIN3_MODE_S  6
+/** LP_REG_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
+ *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+ *  state.
+ */
+#define LP_REG_TIMING_HCLK_ACTIVE    (BIT(16))
+#define LP_REG_TIMING_HCLK_ACTIVE_M  (LP_REG_TIMING_HCLK_ACTIVE_V << LP_REG_TIMING_HCLK_ACTIVE_S)
+#define LP_REG_TIMING_HCLK_ACTIVE_V  0x00000001U
+#define LP_REG_TIMING_HCLK_ACTIVE_S  16
+
+/** LP_SPI_DIN_NUM_REG register
+ *  SPI input delay number configuration
+ */
+#define LP_SPI_DIN_NUM_REG (DR_REG_LP_BASE + 0x28)
+/** LP_REG_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define LP_REG_DIN0_NUM    0x00000003U
+#define LP_REG_DIN0_NUM_M  (LP_REG_DIN0_NUM_V << LP_REG_DIN0_NUM_S)
+#define LP_REG_DIN0_NUM_V  0x00000003U
+#define LP_REG_DIN0_NUM_S  0
+/** LP_REG_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define LP_REG_DIN1_NUM    0x00000003U
+#define LP_REG_DIN1_NUM_M  (LP_REG_DIN1_NUM_V << LP_REG_DIN1_NUM_S)
+#define LP_REG_DIN1_NUM_V  0x00000003U
+#define LP_REG_DIN1_NUM_S  2
+/** LP_REG_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define LP_REG_DIN2_NUM    0x00000003U
+#define LP_REG_DIN2_NUM_M  (LP_REG_DIN2_NUM_V << LP_REG_DIN2_NUM_S)
+#define LP_REG_DIN2_NUM_V  0x00000003U
+#define LP_REG_DIN2_NUM_S  4
+/** LP_REG_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define LP_REG_DIN3_NUM    0x00000003U
+#define LP_REG_DIN3_NUM_M  (LP_REG_DIN3_NUM_V << LP_REG_DIN3_NUM_S)
+#define LP_REG_DIN3_NUM_V  0x00000003U
+#define LP_REG_DIN3_NUM_S  6
+
+/** LP_SPI_DOUT_MODE_REG register
+ *  SPI output delay mode configuration
+ */
+#define LP_SPI_DOUT_MODE_REG (DR_REG_LP_BASE + 0x2c)
+/** LP_REG_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_DOUT0_MODE    (BIT(0))
+#define LP_REG_DOUT0_MODE_M  (LP_REG_DOUT0_MODE_V << LP_REG_DOUT0_MODE_S)
+#define LP_REG_DOUT0_MODE_V  0x00000001U
+#define LP_REG_DOUT0_MODE_S  0
+/** LP_REG_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_DOUT1_MODE    (BIT(1))
+#define LP_REG_DOUT1_MODE_M  (LP_REG_DOUT1_MODE_V << LP_REG_DOUT1_MODE_S)
+#define LP_REG_DOUT1_MODE_V  0x00000001U
+#define LP_REG_DOUT1_MODE_S  1
+/** LP_REG_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_DOUT2_MODE    (BIT(2))
+#define LP_REG_DOUT2_MODE_M  (LP_REG_DOUT2_MODE_V << LP_REG_DOUT2_MODE_S)
+#define LP_REG_DOUT2_MODE_V  0x00000001U
+#define LP_REG_DOUT2_MODE_S  2
+/** LP_REG_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_DOUT3_MODE    (BIT(3))
+#define LP_REG_DOUT3_MODE_M  (LP_REG_DOUT3_MODE_V << LP_REG_DOUT3_MODE_S)
+#define LP_REG_DOUT3_MODE_V  0x00000001U
+#define LP_REG_DOUT3_MODE_S  3
+
+/** LP_SPI_DMA_CONF_REG register
+ *  SPI DMA control register
+ */
+#define LP_SPI_DMA_CONF_REG (DR_REG_LP_BASE + 0x30)
+/** LP_REG_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
+ *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+ *  slave mode transfer.
+ */
+#define LP_REG_RX_AFIFO_RST    (BIT(29))
+#define LP_REG_RX_AFIFO_RST_M  (LP_REG_RX_AFIFO_RST_V << LP_REG_RX_AFIFO_RST_S)
+#define LP_REG_RX_AFIFO_RST_V  0x00000001U
+#define LP_REG_RX_AFIFO_RST_S  29
+/** LP_REG_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
+ *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+ *  controlled mode transfer and master mode transfer.
+ */
+#define LP_REG_BUF_AFIFO_RST    (BIT(30))
+#define LP_REG_BUF_AFIFO_RST_M  (LP_REG_BUF_AFIFO_RST_V << LP_REG_BUF_AFIFO_RST_S)
+#define LP_REG_BUF_AFIFO_RST_V  0x00000001U
+#define LP_REG_BUF_AFIFO_RST_S  30
+
+/** LP_SPI_DMA_INT_ENA_REG register
+ *  SPI DMA interrupt enable register
+ */
+#define LP_SPI_DMA_INT_ENA_REG (DR_REG_LP_BASE + 0x34)
+/** LP_REG_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define LP_REG_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define LP_REG_SLV_RD_BUF_DONE_INT_ENA_M  (LP_REG_SLV_RD_BUF_DONE_INT_ENA_V << LP_REG_SLV_RD_BUF_DONE_INT_ENA_S)
+#define LP_REG_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
+#define LP_REG_SLV_RD_BUF_DONE_INT_ENA_S  10
+/** LP_REG_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define LP_REG_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define LP_REG_SLV_WR_BUF_DONE_INT_ENA_M  (LP_REG_SLV_WR_BUF_DONE_INT_ENA_V << LP_REG_SLV_WR_BUF_DONE_INT_ENA_S)
+#define LP_REG_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
+#define LP_REG_SLV_WR_BUF_DONE_INT_ENA_S  11
+/** LP_REG_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The enable bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define LP_REG_TRANS_DONE_INT_ENA    (BIT(12))
+#define LP_REG_TRANS_DONE_INT_ENA_M  (LP_REG_TRANS_DONE_INT_ENA_V << LP_REG_TRANS_DONE_INT_ENA_S)
+#define LP_REG_TRANS_DONE_INT_ENA_V  0x00000001U
+#define LP_REG_TRANS_DONE_INT_ENA_S  12
+/** LP_REG_SPI_WAKEUP_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The enable bit for SPI_WAKEUP_INT interrupt
+ */
+#define LP_REG_SPI_WAKEUP_INT_ENA    (BIT(14))
+#define LP_REG_SPI_WAKEUP_INT_ENA_M  (LP_REG_SPI_WAKEUP_INT_ENA_V << LP_REG_SPI_WAKEUP_INT_ENA_S)
+#define LP_REG_SPI_WAKEUP_INT_ENA_V  0x00000001U
+#define LP_REG_SPI_WAKEUP_INT_ENA_S  14
+/** LP_REG_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_ENA_M  (LP_REG_SLV_BUF_ADDR_ERR_INT_ENA_V << LP_REG_SLV_BUF_ADDR_ERR_INT_ENA_S)
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/** LP_REG_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define LP_REG_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define LP_REG_SLV_CMD_ERR_INT_ENA_M  (LP_REG_SLV_CMD_ERR_INT_ENA_V << LP_REG_SLV_CMD_ERR_INT_ENA_S)
+#define LP_REG_SLV_CMD_ERR_INT_ENA_V  0x00000001U
+#define LP_REG_SLV_CMD_ERR_INT_ENA_S  16
+/** LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/** LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/** LP_REG_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  The enable bit for SPI_APP2_INT interrupt.
+ */
+#define LP_REG_APP2_INT_ENA    (BIT(19))
+#define LP_REG_APP2_INT_ENA_M  (LP_REG_APP2_INT_ENA_V << LP_REG_APP2_INT_ENA_S)
+#define LP_REG_APP2_INT_ENA_V  0x00000001U
+#define LP_REG_APP2_INT_ENA_S  19
+/** LP_REG_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  The enable bit for SPI_APP1_INT interrupt.
+ */
+#define LP_REG_APP1_INT_ENA    (BIT(20))
+#define LP_REG_APP1_INT_ENA_M  (LP_REG_APP1_INT_ENA_V << LP_REG_APP1_INT_ENA_S)
+#define LP_REG_APP1_INT_ENA_V  0x00000001U
+#define LP_REG_APP1_INT_ENA_S  20
+
+/** LP_SPI_DMA_INT_CLR_REG register
+ *  SPI DMA interrupt clear register
+ */
+#define LP_SPI_DMA_INT_CLR_REG (DR_REG_LP_BASE + 0x38)
+/** LP_REG_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define LP_REG_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define LP_REG_SLV_RD_BUF_DONE_INT_CLR_M  (LP_REG_SLV_RD_BUF_DONE_INT_CLR_V << LP_REG_SLV_RD_BUF_DONE_INT_CLR_S)
+#define LP_REG_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
+#define LP_REG_SLV_RD_BUF_DONE_INT_CLR_S  10
+/** LP_REG_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define LP_REG_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define LP_REG_SLV_WR_BUF_DONE_INT_CLR_M  (LP_REG_SLV_WR_BUF_DONE_INT_CLR_V << LP_REG_SLV_WR_BUF_DONE_INT_CLR_S)
+#define LP_REG_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
+#define LP_REG_SLV_WR_BUF_DONE_INT_CLR_S  11
+/** LP_REG_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The clear bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define LP_REG_TRANS_DONE_INT_CLR    (BIT(12))
+#define LP_REG_TRANS_DONE_INT_CLR_M  (LP_REG_TRANS_DONE_INT_CLR_V << LP_REG_TRANS_DONE_INT_CLR_S)
+#define LP_REG_TRANS_DONE_INT_CLR_V  0x00000001U
+#define LP_REG_TRANS_DONE_INT_CLR_S  12
+/** LP_REG_SPI_WAKEUP_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  The clear bit for SPI_WAKEUP_INT interrupt
+ */
+#define LP_REG_SPI_WAKEUP_INT_CLR    (BIT(14))
+#define LP_REG_SPI_WAKEUP_INT_CLR_M  (LP_REG_SPI_WAKEUP_INT_CLR_V << LP_REG_SPI_WAKEUP_INT_CLR_S)
+#define LP_REG_SPI_WAKEUP_INT_CLR_V  0x00000001U
+#define LP_REG_SPI_WAKEUP_INT_CLR_S  14
+/** LP_REG_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_CLR_M  (LP_REG_SLV_BUF_ADDR_ERR_INT_CLR_V << LP_REG_SLV_BUF_ADDR_ERR_INT_CLR_S)
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/** LP_REG_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define LP_REG_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define LP_REG_SLV_CMD_ERR_INT_CLR_M  (LP_REG_SLV_CMD_ERR_INT_CLR_V << LP_REG_SLV_CMD_ERR_INT_CLR_S)
+#define LP_REG_SLV_CMD_ERR_INT_CLR_V  0x00000001U
+#define LP_REG_SLV_CMD_ERR_INT_CLR_S  16
+/** LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/** LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/** LP_REG_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  The clear bit for SPI_APP2_INT interrupt.
+ */
+#define LP_REG_APP2_INT_CLR    (BIT(19))
+#define LP_REG_APP2_INT_CLR_M  (LP_REG_APP2_INT_CLR_V << LP_REG_APP2_INT_CLR_S)
+#define LP_REG_APP2_INT_CLR_V  0x00000001U
+#define LP_REG_APP2_INT_CLR_S  19
+/** LP_REG_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  The clear bit for SPI_APP1_INT interrupt.
+ */
+#define LP_REG_APP1_INT_CLR    (BIT(20))
+#define LP_REG_APP1_INT_CLR_M  (LP_REG_APP1_INT_CLR_V << LP_REG_APP1_INT_CLR_S)
+#define LP_REG_APP1_INT_CLR_V  0x00000001U
+#define LP_REG_APP1_INT_CLR_S  20
+
+/** LP_SPI_DMA_INT_RAW_REG register
+ *  SPI DMA interrupt raw register
+ */
+#define LP_SPI_DMA_INT_RAW_REG (DR_REG_LP_BASE + 0x3c)
+/** LP_REG_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+ *  transmission is ended. 0: Others.
+ */
+#define LP_REG_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define LP_REG_SLV_RD_BUF_DONE_INT_RAW_M  (LP_REG_SLV_RD_BUF_DONE_INT_RAW_V << LP_REG_SLV_RD_BUF_DONE_INT_RAW_S)
+#define LP_REG_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
+#define LP_REG_SLV_RD_BUF_DONE_INT_RAW_S  10
+/** LP_REG_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+ *  transmission is ended. 0: Others.
+ */
+#define LP_REG_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define LP_REG_SLV_WR_BUF_DONE_INT_RAW_M  (LP_REG_SLV_WR_BUF_DONE_INT_RAW_V << LP_REG_SLV_WR_BUF_DONE_INT_RAW_S)
+#define LP_REG_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
+#define LP_REG_SLV_WR_BUF_DONE_INT_RAW_S  11
+/** LP_REG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+ *  ended. 0: others.
+ */
+#define LP_REG_TRANS_DONE_INT_RAW    (BIT(12))
+#define LP_REG_TRANS_DONE_INT_RAW_M  (LP_REG_TRANS_DONE_INT_RAW_V << LP_REG_TRANS_DONE_INT_RAW_S)
+#define LP_REG_TRANS_DONE_INT_RAW_V  0x00000001U
+#define LP_REG_TRANS_DONE_INT_RAW_S  12
+/** LP_REG_SPI_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit for SPI_SPI_WAKEUP_INT interrupt. 1: There is a  wake up signal when
+ *  low power mode. 0: Others.
+ */
+#define LP_REG_SPI_WAKEUP_INT_RAW    (BIT(14))
+#define LP_REG_SPI_WAKEUP_INT_RAW_M  (LP_REG_SPI_WAKEUP_INT_RAW_V << LP_REG_SPI_WAKEUP_INT_RAW_S)
+#define LP_REG_SPI_WAKEUP_INT_RAW_V  0x00000001U
+#define LP_REG_SPI_WAKEUP_INT_RAW_S  14
+/** LP_REG_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+ *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+ *  bigger than 63. 0: Others.
+ */
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_RAW_M  (LP_REG_SLV_BUF_ADDR_ERR_INT_RAW_V << LP_REG_SLV_BUF_ADDR_ERR_INT_RAW_S)
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/** LP_REG_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+ *  current SPI slave HD mode transmission is not supported. 0: Others.
+ */
+#define LP_REG_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define LP_REG_SLV_CMD_ERR_INT_RAW_M  (LP_REG_SLV_CMD_ERR_INT_RAW_V << LP_REG_SLV_CMD_ERR_INT_RAW_S)
+#define LP_REG_SLV_CMD_ERR_INT_RAW_V  0x00000001U
+#define LP_REG_SLV_CMD_ERR_INT_RAW_S  16
+/** LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+ *  write-full error when SPI inputs data in master mode. 0: Others.
+ */
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/** LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+ *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+ */
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/** LP_REG_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.
+ */
+#define LP_REG_APP2_INT_RAW    (BIT(19))
+#define LP_REG_APP2_INT_RAW_M  (LP_REG_APP2_INT_RAW_V << LP_REG_APP2_INT_RAW_S)
+#define LP_REG_APP2_INT_RAW_V  0x00000001U
+#define LP_REG_APP2_INT_RAW_S  19
+/** LP_REG_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.
+ */
+#define LP_REG_APP1_INT_RAW    (BIT(20))
+#define LP_REG_APP1_INT_RAW_M  (LP_REG_APP1_INT_RAW_V << LP_REG_APP1_INT_RAW_S)
+#define LP_REG_APP1_INT_RAW_V  0x00000001U
+#define LP_REG_APP1_INT_RAW_S  20
+
+/** LP_SPI_DMA_INT_ST_REG register
+ *  SPI DMA interrupt status register
+ */
+#define LP_SPI_DMA_INT_ST_REG (DR_REG_LP_BASE + 0x40)
+/** LP_REG_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define LP_REG_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define LP_REG_SLV_RD_BUF_DONE_INT_ST_M  (LP_REG_SLV_RD_BUF_DONE_INT_ST_V << LP_REG_SLV_RD_BUF_DONE_INT_ST_S)
+#define LP_REG_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
+#define LP_REG_SLV_RD_BUF_DONE_INT_ST_S  10
+/** LP_REG_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define LP_REG_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define LP_REG_SLV_WR_BUF_DONE_INT_ST_M  (LP_REG_SLV_WR_BUF_DONE_INT_ST_V << LP_REG_SLV_WR_BUF_DONE_INT_ST_S)
+#define LP_REG_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
+#define LP_REG_SLV_WR_BUF_DONE_INT_ST_S  11
+/** LP_REG_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The status bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define LP_REG_TRANS_DONE_INT_ST    (BIT(12))
+#define LP_REG_TRANS_DONE_INT_ST_M  (LP_REG_TRANS_DONE_INT_ST_V << LP_REG_TRANS_DONE_INT_ST_S)
+#define LP_REG_TRANS_DONE_INT_ST_V  0x00000001U
+#define LP_REG_TRANS_DONE_INT_ST_S  12
+/** LP_REG_SPI_WAKEUP_INT_ST : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define LP_REG_SPI_WAKEUP_INT_ST    (BIT(14))
+#define LP_REG_SPI_WAKEUP_INT_ST_M  (LP_REG_SPI_WAKEUP_INT_ST_V << LP_REG_SPI_WAKEUP_INT_ST_S)
+#define LP_REG_SPI_WAKEUP_INT_ST_V  0x00000001U
+#define LP_REG_SPI_WAKEUP_INT_ST_S  14
+/** LP_REG_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_ST_M  (LP_REG_SLV_BUF_ADDR_ERR_INT_ST_V << LP_REG_SLV_BUF_ADDR_ERR_INT_ST_S)
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
+#define LP_REG_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/** LP_REG_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define LP_REG_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define LP_REG_SLV_CMD_ERR_INT_ST_M  (LP_REG_SLV_CMD_ERR_INT_ST_V << LP_REG_SLV_CMD_ERR_INT_ST_S)
+#define LP_REG_SLV_CMD_ERR_INT_ST_V  0x00000001U
+#define LP_REG_SLV_CMD_ERR_INT_ST_S  16
+/** LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
+#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/** LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
+#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/** LP_REG_APP2_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The status bit for SPI_APP2_INT interrupt.
+ */
+#define LP_REG_APP2_INT_ST    (BIT(19))
+#define LP_REG_APP2_INT_ST_M  (LP_REG_APP2_INT_ST_V << LP_REG_APP2_INT_ST_S)
+#define LP_REG_APP2_INT_ST_V  0x00000001U
+#define LP_REG_APP2_INT_ST_S  19
+/** LP_REG_APP1_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The status bit for SPI_APP1_INT interrupt.
+ */
+#define LP_REG_APP1_INT_ST    (BIT(20))
+#define LP_REG_APP1_INT_ST_M  (LP_REG_APP1_INT_ST_V << LP_REG_APP1_INT_ST_S)
+#define LP_REG_APP1_INT_ST_V  0x00000001U
+#define LP_REG_APP1_INT_ST_S  20
+
+/** LP_SPI_SLEEP_CONF0_REG register
+ *  NA
+ */
+#define LP_SPI_SLEEP_CONF0_REG (DR_REG_LP_BASE + 0x44)
+/** LP_REG_SLV_WK_CHAR0 : R/W; bitpos: [7:0]; default: 10;
+ *  NA
+ */
+#define LP_REG_SLV_WK_CHAR0    0x000000FFU
+#define LP_REG_SLV_WK_CHAR0_M  (LP_REG_SLV_WK_CHAR0_V << LP_REG_SLV_WK_CHAR0_S)
+#define LP_REG_SLV_WK_CHAR0_V  0x000000FFU
+#define LP_REG_SLV_WK_CHAR0_S  0
+/** LP_REG_SLV_WK_CHAR_NUM : R/W; bitpos: [10:8]; default: 0;
+ *  NA
+ */
+#define LP_REG_SLV_WK_CHAR_NUM    0x00000007U
+#define LP_REG_SLV_WK_CHAR_NUM_M  (LP_REG_SLV_WK_CHAR_NUM_V << LP_REG_SLV_WK_CHAR_NUM_S)
+#define LP_REG_SLV_WK_CHAR_NUM_V  0x00000007U
+#define LP_REG_SLV_WK_CHAR_NUM_S  8
+/** LP_REG_SLV_WK_CHAR_MASK : R/W; bitpos: [15:11]; default: 0;
+ *  NA
+ */
+#define LP_REG_SLV_WK_CHAR_MASK    0x0000001FU
+#define LP_REG_SLV_WK_CHAR_MASK_M  (LP_REG_SLV_WK_CHAR_MASK_V << LP_REG_SLV_WK_CHAR_MASK_S)
+#define LP_REG_SLV_WK_CHAR_MASK_V  0x0000001FU
+#define LP_REG_SLV_WK_CHAR_MASK_S  11
+/** LP_REG_SLV_WK_MODE_SEL : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define LP_REG_SLV_WK_MODE_SEL    (BIT(16))
+#define LP_REG_SLV_WK_MODE_SEL_M  (LP_REG_SLV_WK_MODE_SEL_V << LP_REG_SLV_WK_MODE_SEL_S)
+#define LP_REG_SLV_WK_MODE_SEL_V  0x00000001U
+#define LP_REG_SLV_WK_MODE_SEL_S  16
+/** LP_REG_SLEEP_EN : R/W; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define LP_REG_SLEEP_EN    (BIT(17))
+#define LP_REG_SLEEP_EN_M  (LP_REG_SLEEP_EN_V << LP_REG_SLEEP_EN_S)
+#define LP_REG_SLEEP_EN_V  0x00000001U
+#define LP_REG_SLEEP_EN_S  17
+/** LP_REG_SLEEP_DIS_RXFIFO_WR_EN : R/W; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define LP_REG_SLEEP_DIS_RXFIFO_WR_EN    (BIT(18))
+#define LP_REG_SLEEP_DIS_RXFIFO_WR_EN_M  (LP_REG_SLEEP_DIS_RXFIFO_WR_EN_V << LP_REG_SLEEP_DIS_RXFIFO_WR_EN_S)
+#define LP_REG_SLEEP_DIS_RXFIFO_WR_EN_V  0x00000001U
+#define LP_REG_SLEEP_DIS_RXFIFO_WR_EN_S  18
+/** LP_REG_SLEEP_WK_DATA_SEL : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define LP_REG_SLEEP_WK_DATA_SEL    (BIT(19))
+#define LP_REG_SLEEP_WK_DATA_SEL_M  (LP_REG_SLEEP_WK_DATA_SEL_V << LP_REG_SLEEP_WK_DATA_SEL_S)
+#define LP_REG_SLEEP_WK_DATA_SEL_V  0x00000001U
+#define LP_REG_SLEEP_WK_DATA_SEL_S  19
+
+/** LP_SPI_SLEEP_CONF1_REG register
+ *  NA
+ */
+#define LP_SPI_SLEEP_CONF1_REG (DR_REG_LP_BASE + 0x48)
+/** LP_REG_SLV_WK_CHAR1 : R/W; bitpos: [7:0]; default: 11;
+ *  NA
+ */
+#define LP_REG_SLV_WK_CHAR1    0x000000FFU
+#define LP_REG_SLV_WK_CHAR1_M  (LP_REG_SLV_WK_CHAR1_V << LP_REG_SLV_WK_CHAR1_S)
+#define LP_REG_SLV_WK_CHAR1_V  0x000000FFU
+#define LP_REG_SLV_WK_CHAR1_S  0
+/** LP_REG_SLV_WK_CHAR2 : R/W; bitpos: [15:8]; default: 12;
+ *  NA
+ */
+#define LP_REG_SLV_WK_CHAR2    0x000000FFU
+#define LP_REG_SLV_WK_CHAR2_M  (LP_REG_SLV_WK_CHAR2_V << LP_REG_SLV_WK_CHAR2_S)
+#define LP_REG_SLV_WK_CHAR2_V  0x000000FFU
+#define LP_REG_SLV_WK_CHAR2_S  8
+/** LP_REG_SLV_WK_CHAR3 : R/W; bitpos: [23:16]; default: 13;
+ *  NA
+ */
+#define LP_REG_SLV_WK_CHAR3    0x000000FFU
+#define LP_REG_SLV_WK_CHAR3_M  (LP_REG_SLV_WK_CHAR3_V << LP_REG_SLV_WK_CHAR3_S)
+#define LP_REG_SLV_WK_CHAR3_V  0x000000FFU
+#define LP_REG_SLV_WK_CHAR3_S  16
+/** LP_REG_SLV_WK_CHAR4 : R/W; bitpos: [31:24]; default: 14;
+ *  NA
+ */
+#define LP_REG_SLV_WK_CHAR4    0x000000FFU
+#define LP_REG_SLV_WK_CHAR4_M  (LP_REG_SLV_WK_CHAR4_V << LP_REG_SLV_WK_CHAR4_S)
+#define LP_REG_SLV_WK_CHAR4_V  0x000000FFU
+#define LP_REG_SLV_WK_CHAR4_S  24
+
+/** LP_SPI_DMA_INT_SET_REG register
+ *  SPI interrupt software set register
+ */
+#define LP_SPI_DMA_INT_SET_REG (DR_REG_LP_BASE + 0x4c)
+/** LP_SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
+ *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define LP_SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
+#define LP_SPI_SLV_RD_BUF_DONE_INT_SET_M  (LP_SPI_SLV_RD_BUF_DONE_INT_SET_V << LP_SPI_SLV_RD_BUF_DONE_INT_SET_S)
+#define LP_SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
+#define LP_SPI_SLV_RD_BUF_DONE_INT_SET_S  10
+/** LP_SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
+ *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define LP_SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
+#define LP_SPI_SLV_WR_BUF_DONE_INT_SET_M  (LP_SPI_SLV_WR_BUF_DONE_INT_SET_V << LP_SPI_SLV_WR_BUF_DONE_INT_SET_S)
+#define LP_SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
+#define LP_SPI_SLV_WR_BUF_DONE_INT_SET_S  11
+/** LP_SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
+ *  The software set bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define LP_SPI_TRANS_DONE_INT_SET    (BIT(12))
+#define LP_SPI_TRANS_DONE_INT_SET_M  (LP_SPI_TRANS_DONE_INT_SET_V << LP_SPI_TRANS_DONE_INT_SET_S)
+#define LP_SPI_TRANS_DONE_INT_SET_V  0x00000001U
+#define LP_SPI_TRANS_DONE_INT_SET_S  12
+/** LP_SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
+ *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define LP_SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
+#define LP_SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (LP_SPI_SLV_BUF_ADDR_ERR_INT_SET_V << LP_SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
+#define LP_SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
+#define LP_SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
+/** LP_SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
+ *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define LP_SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
+#define LP_SPI_SLV_CMD_ERR_INT_SET_M  (LP_SPI_SLV_CMD_ERR_INT_SET_V << LP_SPI_SLV_CMD_ERR_INT_SET_S)
+#define LP_SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
+#define LP_SPI_SLV_CMD_ERR_INT_SET_S  16
+/** LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
+ *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
+#define LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
+#define LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
+#define LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
+/** LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
+ *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
+#define LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
+#define LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
+#define LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
+/** LP_SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
+ *  The software set bit for SPI_APP2_INT interrupt.
+ */
+#define LP_SPI_APP2_INT_SET    (BIT(19))
+#define LP_SPI_APP2_INT_SET_M  (LP_SPI_APP2_INT_SET_V << LP_SPI_APP2_INT_SET_S)
+#define LP_SPI_APP2_INT_SET_V  0x00000001U
+#define LP_SPI_APP2_INT_SET_S  19
+/** LP_SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
+ *  The software set bit for SPI_APP1_INT interrupt.
+ */
+#define LP_SPI_APP1_INT_SET    (BIT(20))
+#define LP_SPI_APP1_INT_SET_M  (LP_SPI_APP1_INT_SET_V << LP_SPI_APP1_INT_SET_S)
+#define LP_SPI_APP1_INT_SET_V  0x00000001U
+#define LP_SPI_APP1_INT_SET_S  20
+
+/** LP_SPI_W0_REG register
+ *  SPI CPU-controlled buffer0
+ */
+#define LP_SPI_W0_REG (DR_REG_LP_BASE + 0x98)
+/** LP_REG_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF0    0xFFFFFFFFU
+#define LP_REG_BUF0_M  (LP_REG_BUF0_V << LP_REG_BUF0_S)
+#define LP_REG_BUF0_V  0xFFFFFFFFU
+#define LP_REG_BUF0_S  0
+
+/** LP_SPI_W1_REG register
+ *  SPI CPU-controlled buffer1
+ */
+#define LP_SPI_W1_REG (DR_REG_LP_BASE + 0x9c)
+/** LP_REG_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF1    0xFFFFFFFFU
+#define LP_REG_BUF1_M  (LP_REG_BUF1_V << LP_REG_BUF1_S)
+#define LP_REG_BUF1_V  0xFFFFFFFFU
+#define LP_REG_BUF1_S  0
+
+/** LP_SPI_W2_REG register
+ *  SPI CPU-controlled buffer2
+ */
+#define LP_SPI_W2_REG (DR_REG_LP_BASE + 0xa0)
+/** LP_REG_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF2    0xFFFFFFFFU
+#define LP_REG_BUF2_M  (LP_REG_BUF2_V << LP_REG_BUF2_S)
+#define LP_REG_BUF2_V  0xFFFFFFFFU
+#define LP_REG_BUF2_S  0
+
+/** LP_SPI_W3_REG register
+ *  SPI CPU-controlled buffer3
+ */
+#define LP_SPI_W3_REG (DR_REG_LP_BASE + 0xa4)
+/** LP_REG_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF3    0xFFFFFFFFU
+#define LP_REG_BUF3_M  (LP_REG_BUF3_V << LP_REG_BUF3_S)
+#define LP_REG_BUF3_V  0xFFFFFFFFU
+#define LP_REG_BUF3_S  0
+
+/** LP_SPI_W4_REG register
+ *  SPI CPU-controlled buffer4
+ */
+#define LP_SPI_W4_REG (DR_REG_LP_BASE + 0xa8)
+/** LP_REG_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF4    0xFFFFFFFFU
+#define LP_REG_BUF4_M  (LP_REG_BUF4_V << LP_REG_BUF4_S)
+#define LP_REG_BUF4_V  0xFFFFFFFFU
+#define LP_REG_BUF4_S  0
+
+/** LP_SPI_W5_REG register
+ *  SPI CPU-controlled buffer5
+ */
+#define LP_SPI_W5_REG (DR_REG_LP_BASE + 0xac)
+/** LP_REG_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF5    0xFFFFFFFFU
+#define LP_REG_BUF5_M  (LP_REG_BUF5_V << LP_REG_BUF5_S)
+#define LP_REG_BUF5_V  0xFFFFFFFFU
+#define LP_REG_BUF5_S  0
+
+/** LP_SPI_W6_REG register
+ *  SPI CPU-controlled buffer6
+ */
+#define LP_SPI_W6_REG (DR_REG_LP_BASE + 0xb0)
+/** LP_REG_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF6    0xFFFFFFFFU
+#define LP_REG_BUF6_M  (LP_REG_BUF6_V << LP_REG_BUF6_S)
+#define LP_REG_BUF6_V  0xFFFFFFFFU
+#define LP_REG_BUF6_S  0
+
+/** LP_SPI_W7_REG register
+ *  SPI CPU-controlled buffer7
+ */
+#define LP_SPI_W7_REG (DR_REG_LP_BASE + 0xb4)
+/** LP_REG_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF7    0xFFFFFFFFU
+#define LP_REG_BUF7_M  (LP_REG_BUF7_V << LP_REG_BUF7_S)
+#define LP_REG_BUF7_V  0xFFFFFFFFU
+#define LP_REG_BUF7_S  0
+
+/** LP_SPI_W8_REG register
+ *  SPI CPU-controlled buffer8
+ */
+#define LP_SPI_W8_REG (DR_REG_LP_BASE + 0xb8)
+/** LP_REG_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF8    0xFFFFFFFFU
+#define LP_REG_BUF8_M  (LP_REG_BUF8_V << LP_REG_BUF8_S)
+#define LP_REG_BUF8_V  0xFFFFFFFFU
+#define LP_REG_BUF8_S  0
+
+/** LP_SPI_W9_REG register
+ *  SPI CPU-controlled buffer9
+ */
+#define LP_SPI_W9_REG (DR_REG_LP_BASE + 0xbc)
+/** LP_REG_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF9    0xFFFFFFFFU
+#define LP_REG_BUF9_M  (LP_REG_BUF9_V << LP_REG_BUF9_S)
+#define LP_REG_BUF9_V  0xFFFFFFFFU
+#define LP_REG_BUF9_S  0
+
+/** LP_SPI_W10_REG register
+ *  SPI CPU-controlled buffer10
+ */
+#define LP_SPI_W10_REG (DR_REG_LP_BASE + 0xc0)
+/** LP_REG_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF10    0xFFFFFFFFU
+#define LP_REG_BUF10_M  (LP_REG_BUF10_V << LP_REG_BUF10_S)
+#define LP_REG_BUF10_V  0xFFFFFFFFU
+#define LP_REG_BUF10_S  0
+
+/** LP_SPI_W11_REG register
+ *  SPI CPU-controlled buffer11
+ */
+#define LP_SPI_W11_REG (DR_REG_LP_BASE + 0xc4)
+/** LP_REG_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF11    0xFFFFFFFFU
+#define LP_REG_BUF11_M  (LP_REG_BUF11_V << LP_REG_BUF11_S)
+#define LP_REG_BUF11_V  0xFFFFFFFFU
+#define LP_REG_BUF11_S  0
+
+/** LP_SPI_W12_REG register
+ *  SPI CPU-controlled buffer12
+ */
+#define LP_SPI_W12_REG (DR_REG_LP_BASE + 0xc8)
+/** LP_REG_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF12    0xFFFFFFFFU
+#define LP_REG_BUF12_M  (LP_REG_BUF12_V << LP_REG_BUF12_S)
+#define LP_REG_BUF12_V  0xFFFFFFFFU
+#define LP_REG_BUF12_S  0
+
+/** LP_SPI_W13_REG register
+ *  SPI CPU-controlled buffer13
+ */
+#define LP_SPI_W13_REG (DR_REG_LP_BASE + 0xcc)
+/** LP_REG_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF13    0xFFFFFFFFU
+#define LP_REG_BUF13_M  (LP_REG_BUF13_V << LP_REG_BUF13_S)
+#define LP_REG_BUF13_V  0xFFFFFFFFU
+#define LP_REG_BUF13_S  0
+
+/** LP_SPI_W14_REG register
+ *  SPI CPU-controlled buffer14
+ */
+#define LP_SPI_W14_REG (DR_REG_LP_BASE + 0xd0)
+/** LP_REG_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF14    0xFFFFFFFFU
+#define LP_REG_BUF14_M  (LP_REG_BUF14_V << LP_REG_BUF14_S)
+#define LP_REG_BUF14_V  0xFFFFFFFFU
+#define LP_REG_BUF14_S  0
+
+/** LP_SPI_W15_REG register
+ *  SPI CPU-controlled buffer15
+ */
+#define LP_SPI_W15_REG (DR_REG_LP_BASE + 0xd4)
+/** LP_REG_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define LP_REG_BUF15    0xFFFFFFFFU
+#define LP_REG_BUF15_M  (LP_REG_BUF15_V << LP_REG_BUF15_S)
+#define LP_REG_BUF15_V  0xFFFFFFFFU
+#define LP_REG_BUF15_S  0
+
+/** LP_SPI_SLAVE_REG register
+ *  SPI slave control register
+ */
+#define LP_SPI_SLAVE_REG (DR_REG_LP_BASE + 0xe0)
+/** LP_REG_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+ *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+ *  SPI clock is always on. Can be configured in CONF state.
+ */
+#define LP_REG_CLK_MODE    0x00000003U
+#define LP_REG_CLK_MODE_M  (LP_REG_CLK_MODE_V << LP_REG_CLK_MODE_S)
+#define LP_REG_CLK_MODE_V  0x00000003U
+#define LP_REG_CLK_MODE_S  0
+/** LP_REG_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
+ *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+ *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+ */
+#define LP_REG_CLK_MODE_13    (BIT(2))
+#define LP_REG_CLK_MODE_13_M  (LP_REG_CLK_MODE_13_V << LP_REG_CLK_MODE_13_S)
+#define LP_REG_CLK_MODE_13_V  0x00000001U
+#define LP_REG_CLK_MODE_13_S  2
+/** LP_REG_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
+ *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+ *  0: output data at tsck posedge
+ */
+#define LP_REG_RSCK_DATA_OUT    (BIT(3))
+#define LP_REG_RSCK_DATA_OUT_M  (LP_REG_RSCK_DATA_OUT_V << LP_REG_RSCK_DATA_OUT_S)
+#define LP_REG_RSCK_DATA_OUT_V  0x00000001U
+#define LP_REG_RSCK_DATA_OUT_S  3
+/** LP_REG_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+ *  CPU controlled mode(Rd_BUF). 0: others
+ */
+#define LP_REG_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define LP_REG_SLV_RDBUF_BITLEN_EN_M  (LP_REG_SLV_RDBUF_BITLEN_EN_V << LP_REG_SLV_RDBUF_BITLEN_EN_S)
+#define LP_REG_SLV_RDBUF_BITLEN_EN_V  0x00000001U
+#define LP_REG_SLV_RDBUF_BITLEN_EN_S  10
+/** LP_REG_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+ *  in CPU controlled mode(Wr_BUF). 0: others
+ */
+#define LP_REG_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define LP_REG_SLV_WRBUF_BITLEN_EN_M  (LP_REG_SLV_WRBUF_BITLEN_EN_V << LP_REG_SLV_WRBUF_BITLEN_EN_S)
+#define LP_REG_SLV_WRBUF_BITLEN_EN_V  0x00000001U
+#define LP_REG_SLV_WRBUF_BITLEN_EN_S  11
+/** LP_REG_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
+ *  Set SPI work mode. 1: slave mode 0: master mode.
+ */
+#define LP_REG_SLAVE_MODE    (BIT(26))
+#define LP_REG_SLAVE_MODE_M  (LP_REG_SLAVE_MODE_V << LP_REG_SLAVE_MODE_S)
+#define LP_REG_SLAVE_MODE_V  0x00000001U
+#define LP_REG_SLAVE_MODE_S  26
+/** LP_REG_SOFT_RESET : WT; bitpos: [27]; default: 0;
+ *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+ *  configured in CONF state.
+ */
+#define LP_REG_SOFT_RESET    (BIT(27))
+#define LP_REG_SOFT_RESET_M  (LP_REG_SOFT_RESET_V << LP_REG_SOFT_RESET_S)
+#define LP_REG_SOFT_RESET_V  0x00000001U
+#define LP_REG_SOFT_RESET_S  27
+
+/** LP_SPI_SLAVE1_REG register
+ *  SPI slave control register 1
+ */
+#define LP_SPI_SLAVE1_REG (DR_REG_LP_BASE + 0xe4)
+/** LP_REG_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
+ *  The transferred data bit length in SPI slave FD and HD mode.
+ */
+#define LP_REG_SLV_DATA_BITLEN    0x0003FFFFU
+#define LP_REG_SLV_DATA_BITLEN_M  (LP_REG_SLV_DATA_BITLEN_V << LP_REG_SLV_DATA_BITLEN_S)
+#define LP_REG_SLV_DATA_BITLEN_V  0x0003FFFFU
+#define LP_REG_SLV_DATA_BITLEN_S  0
+/** LP_REG_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
+ *  In the slave mode it is the value of command.
+ */
+#define LP_REG_SLV_LAST_COMMAND    0x000000FFU
+#define LP_REG_SLV_LAST_COMMAND_M  (LP_REG_SLV_LAST_COMMAND_V << LP_REG_SLV_LAST_COMMAND_S)
+#define LP_REG_SLV_LAST_COMMAND_V  0x000000FFU
+#define LP_REG_SLV_LAST_COMMAND_S  18
+/** LP_REG_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
+ *  In the slave mode it is the value of address.
+ */
+#define LP_REG_SLV_LAST_ADDR    0x0000003FU
+#define LP_REG_SLV_LAST_ADDR_M  (LP_REG_SLV_LAST_ADDR_V << LP_REG_SLV_LAST_ADDR_S)
+#define LP_REG_SLV_LAST_ADDR_V  0x0000003FU
+#define LP_REG_SLV_LAST_ADDR_S  26
+
+/** LP_SPI_CLK_GATE_REG register
+ *  SPI module clock and register clock control
+ */
+#define LP_SPI_CLK_GATE_REG (DR_REG_LP_BASE + 0xe8)
+/** LP_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable clk gate
+ */
+#define LP_REG_CLK_EN    (BIT(0))
+#define LP_REG_CLK_EN_M  (LP_REG_CLK_EN_V << LP_REG_CLK_EN_S)
+#define LP_REG_CLK_EN_V  0x00000001U
+#define LP_REG_CLK_EN_S  0
+/** LP_REG_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to power on the SPI module clock.
+ */
+#define LP_REG_MST_CLK_ACTIVE    (BIT(1))
+#define LP_REG_MST_CLK_ACTIVE_M  (LP_REG_MST_CLK_ACTIVE_V << LP_REG_MST_CLK_ACTIVE_S)
+#define LP_REG_MST_CLK_ACTIVE_V  0x00000001U
+#define LP_REG_MST_CLK_ACTIVE_S  1
+/** LP_REG_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
+ *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+ *  0: XTAL CLK.
+ */
+#define LP_REG_MST_CLK_SEL    (BIT(2))
+#define LP_REG_MST_CLK_SEL_M  (LP_REG_MST_CLK_SEL_V << LP_REG_MST_CLK_SEL_S)
+#define LP_REG_MST_CLK_SEL_V  0x00000001U
+#define LP_REG_MST_CLK_SEL_S  2
+
+/** LP_SPI_DATE_REG register
+ *  Version control
+ */
+#define LP_SPI_DATE_REG (DR_REG_LP_BASE + 0xf0)
+/** LP_REG_DATE : R/W; bitpos: [27:0]; default: 33591360;
+ *  SPI register version.
+ */
+#define LP_REG_DATE    0x0FFFFFFFU
+#define LP_REG_DATE_M  (LP_REG_DATE_V << LP_REG_DATE_S)
+#define LP_REG_DATE_V  0x0FFFFFFFU
+#define LP_REG_DATE_S  0
+
+/** LP_RND_ECO_CS_REG register
+ *  NA
+ */
+#define LP_RND_ECO_CS_REG (DR_REG_LP_BASE + 0xf4)
+/** LP_REG_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define LP_REG_RND_ECO_EN    (BIT(0))
+#define LP_REG_RND_ECO_EN_M  (LP_REG_RND_ECO_EN_V << LP_REG_RND_ECO_EN_S)
+#define LP_REG_RND_ECO_EN_V  0x00000001U
+#define LP_REG_RND_ECO_EN_S  0
+/** LP_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define LP_RND_ECO_RESULT    (BIT(1))
+#define LP_RND_ECO_RESULT_M  (LP_RND_ECO_RESULT_V << LP_RND_ECO_RESULT_S)
+#define LP_RND_ECO_RESULT_V  0x00000001U
+#define LP_RND_ECO_RESULT_S  1
+
+/** LP_RND_ECO_LOW_REG register
+ *  NA
+ */
+#define LP_RND_ECO_LOW_REG (DR_REG_LP_BASE + 0xf8)
+/** LP_REG_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define LP_REG_RND_ECO_LOW    0xFFFFFFFFU
+#define LP_REG_RND_ECO_LOW_M  (LP_REG_RND_ECO_LOW_V << LP_REG_RND_ECO_LOW_S)
+#define LP_REG_RND_ECO_LOW_V  0xFFFFFFFFU
+#define LP_REG_RND_ECO_LOW_S  0
+
+/** LP_RND_ECO_HIGH_REG register
+ *  NA
+ */
+#define LP_RND_ECO_HIGH_REG (DR_REG_LP_BASE + 0xfc)
+/** LP_REG_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 65535;
+ *  NA
+ */
+#define LP_REG_RND_ECO_HIGH    0xFFFFFFFFU
+#define LP_REG_RND_ECO_HIGH_M  (LP_REG_RND_ECO_HIGH_V << LP_REG_RND_ECO_HIGH_S)
+#define LP_REG_RND_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_REG_RND_ECO_HIGH_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h
new file mode 100644
index 0000000000..0735efd6be
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h
@@ -0,0 +1,1276 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: LP SPI CMD REG */
+/** Type of spi_cmd register
+ *  Command control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** reg_update : WT; bitpos: [23]; default: 0;
+         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+         *  clock domain, which is only used in SPI master mode.
+         */
+        uint32_t reg_update:1;
+        /** reg_usr : R/W/SC; bitpos: [24]; default: 0;
+         *  User define command enable.  An operation will be triggered when the bit is set.
+         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+         *  changed by CONF_buf.
+         */
+        uint32_t reg_usr:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} lp_spi_cmd_reg_t;
+
+
+/** Group: LP SPI ADDR REG */
+/** Type of spi_addr register
+ *  Address value register
+ */
+typedef union {
+    struct {
+        /** reg_usr_addr_value : R/W; bitpos: [31:0]; default: 0;
+         *  Address to slave. Can be configured in CONF state.
+         */
+        uint32_t reg_usr_addr_value:32;
+    };
+    uint32_t val;
+} lp_spi_addr_reg_t;
+
+
+/** Group: LP SPI CTRL REG */
+/** Type of spi_ctrl register
+ *  SPI control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** reg_dummy_out : R/W; bitpos: [3]; default: 0;
+         *  In the dummy phase the signal level of spi is output by the spi controller. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_dummy_out:1;
+        uint32_t reserved_4:14;
+        /** reg_q_pol : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t reg_q_pol:1;
+        /** reg_d_pol : R/W; bitpos: [19]; default: 1;
+         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t reg_d_pol:1;
+        uint32_t reserved_20:5;
+        /** reg_rd_bit_order : R/W; bitpos: [25]; default: 0;
+         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+         *  state.
+         */
+        uint32_t reg_rd_bit_order:1;
+        /** reg_wr_bit_order : R/W; bitpos: [26]; default: 0;
+         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_wr_bit_order:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} lp_spi_ctrl_reg_t;
+
+
+/** Group: LP SPI CLOCK REG */
+/** Type of spi_clock register
+ *  SPI clock control register
+ */
+typedef union {
+    struct {
+        /** reg_clkcnt_l : R/W; bitpos: [5:0]; default: 3;
+         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+         *  0. Can be configured in CONF state.
+         */
+        uint32_t reg_clkcnt_l:6;
+        /** reg_clkcnt_h : R/W; bitpos: [11:6]; default: 1;
+         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+         *  must be 0. Can be configured in CONF state.
+         */
+        uint32_t reg_clkcnt_h:6;
+        /** reg_clkcnt_n : R/W; bitpos: [17:12]; default: 3;
+         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+         */
+        uint32_t reg_clkcnt_n:6;
+        /** reg_clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
+         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+         */
+        uint32_t reg_clkdiv_pre:4;
+        uint32_t reserved_22:9;
+        /** reg_clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
+         *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+         *  clock. Can be configured in CONF state.
+         */
+        uint32_t reg_clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} lp_spi_clock_reg_t;
+
+
+/** Group: LP SPI USER REG */
+/** Type of spi_user register
+ *  SPI USER control register
+ */
+typedef union {
+    struct {
+        /** reg_doutdin : R/W; bitpos: [0]; default: 0;
+         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_doutdin:1;
+        uint32_t reserved_1:4;
+        /** reg_tsck_i_edge : R/W; bitpos: [5]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+         *  spi_ck_i. 1:tsck = !spi_ck_i.
+         */
+        uint32_t reg_tsck_i_edge:1;
+        /** reg_cs_hold : R/W; bitpos: [6]; default: 1;
+         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_cs_hold:1;
+        /** reg_cs_setup : R/W; bitpos: [7]; default: 1;
+         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_cs_setup:1;
+        /** reg_rsck_i_edge : R/W; bitpos: [8]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+         *  !spi_ck_i. 1:rsck = spi_ck_i.
+         */
+        uint32_t reg_rsck_i_edge:1;
+        /** reg_ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+         *  be configured in CONF state.
+         */
+        uint32_t reg_ck_out_edge:1;
+        uint32_t reserved_10:7;
+        /** reg_sio : R/W; bitpos: [17]; default: 0;
+         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+         */
+        uint32_t reg_sio:1;
+        uint32_t reserved_18:6;
+        /** reg_usr_miso_highpart : R/W; bitpos: [24]; default: 0;
+         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+         *  disable. Can be configured in CONF state.
+         */
+        uint32_t reg_usr_miso_highpart:1;
+        /** reg_usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
+         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+         *  0: disable.  Can be configured in CONF state.
+         */
+        uint32_t reg_usr_mosi_highpart:1;
+        /** reg_usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+         *  CONF state.
+         */
+        uint32_t reg_usr_dummy_idle:1;
+        /** reg_usr_mosi : R/W; bitpos: [27]; default: 0;
+         *  This bit enable the write-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t reg_usr_mosi:1;
+        /** reg_usr_miso : R/W; bitpos: [28]; default: 0;
+         *  This bit enable the read-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t reg_usr_miso:1;
+        /** reg_usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t reg_usr_dummy:1;
+        /** reg_usr_addr : R/W; bitpos: [30]; default: 0;
+         *  This bit enable the address phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t reg_usr_addr:1;
+        /** reg_usr_command : R/W; bitpos: [31]; default: 1;
+         *  This bit enable the command phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t reg_usr_command:1;
+    };
+    uint32_t val;
+} lp_spi_user_reg_t;
+
+
+/** Group: LP SPI USER1 REG */
+/** Type of spi_user1 register
+ *  SPI USER control register 1
+ */
+typedef union {
+    struct {
+        /** reg_usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
+         *  The length in spi_clk cycles of dummy phase. The register value shall be
+         *  (cycle_num-1). Can be configured in CONF state.
+         */
+        uint32_t reg_usr_dummy_cyclelen:8;
+        uint32_t reserved_8:8;
+        /** reg_mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
+         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+         *  GP-SPI master FD/HD-mode.
+         */
+        uint32_t reg_mst_wfull_err_end_en:1;
+        /** reg_cs_setup_time : R/W; bitpos: [21:17]; default: 0;
+         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+         *  bit. Can be configured in CONF state.
+         */
+        uint32_t reg_cs_setup_time:5;
+        /** reg_cs_hold_time : R/W; bitpos: [26:22]; default: 1;
+         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+         *  Can be configured in CONF state.
+         */
+        uint32_t reg_cs_hold_time:5;
+        /** reg_usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
+         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t reg_usr_addr_bitlen:5;
+    };
+    uint32_t val;
+} lp_spi_user1_reg_t;
+
+
+/** Group: LP SPI USER2 REG */
+/** Type of spi_user2 register
+ *  SPI USER control register 2
+ */
+typedef union {
+    struct {
+        /** reg_usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  The value of  command. Can be configured in CONF state.
+         */
+        uint32_t reg_usr_command_value:16;
+        uint32_t reserved_16:11;
+        /** reg_mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
+         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+         *  is valid in GP-SPI master FD/HD-mode.
+         */
+        uint32_t reg_mst_rempty_err_end_en:1;
+        /** reg_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t reg_usr_command_bitlen:4;
+    };
+    uint32_t val;
+} lp_spi_user2_reg_t;
+
+
+/** Group: LP SPI MS DLEN REG */
+/** Type of spi_ms_dlen register
+ *  SPI data bit length control register
+ */
+typedef union {
+    struct {
+        /** reg_ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  The value of these bits is the configured SPI transmission data bit length in
+         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+         *  the configured bit length in slave mode DMA RX controlled transfer. The register
+         *  value shall be (bit_num-1). Can be configured in CONF state.
+         */
+        uint32_t reg_ms_data_bitlen:18;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} lp_spi_ms_dlen_reg_t;
+
+
+/** Group: LP SPI MISC REG */
+/** Type of spi_misc register
+ *  SPI misc register
+ */
+typedef union {
+    struct {
+        /** reg_cs0_dis : R/W; bitpos: [0]; default: 0;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t reg_cs0_dis:1;
+        uint32_t reserved_1:5;
+        /** reg_ck_dis : R/W; bitpos: [6]; default: 0;
+         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+         */
+        uint32_t reg_ck_dis:1;
+        /** reg_master_cs_pol : R/W; bitpos: [9:7]; default: 0;
+         *  In the master mode the bits are the polarity of spi cs line, the value is
+         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+         */
+        uint32_t reg_master_cs_pol:3;
+        uint32_t reserved_10:13;
+        /** reg_slave_cs_pol : R/W; bitpos: [23]; default: 0;
+         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+         *  CONF state.
+         */
+        uint32_t reg_slave_cs_pol:1;
+        uint32_t reserved_24:5;
+        /** reg_ck_idle_edge : R/W; bitpos: [29]; default: 0;
+         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_ck_idle_edge:1;
+        /** reg_cs_keep_active : R/W; bitpos: [30]; default: 0;
+         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+         */
+        uint32_t reg_cs_keep_active:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} lp_spi_misc_reg_t;
+
+
+/** Group: LP SPI DIN MODE REG */
+/** Type of spi_din_mode register
+ *  SPI input delay mode configuration
+ */
+typedef union {
+    struct {
+        /** reg_din0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t reg_din0_mode:2;
+        /** reg_din1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t reg_din1_mode:2;
+        /** reg_din2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t reg_din2_mode:2;
+        /** reg_din3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t reg_din3_mode:2;
+        uint32_t reserved_8:8;
+        /** reg_timing_hclk_active : R/W; bitpos: [16]; default: 0;
+         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+         *  state.
+         */
+        uint32_t reg_timing_hclk_active:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_spi_din_mode_reg_t;
+
+
+/** Group: LP SPI DIN NUM REG */
+/** Type of spi_din_num register
+ *  SPI input delay number configuration
+ */
+typedef union {
+    struct {
+        /** reg_din0_num : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t reg_din0_num:2;
+        /** reg_din1_num : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t reg_din1_num:2;
+        /** reg_din2_num : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t reg_din2_num:2;
+        /** reg_din3_num : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t reg_din3_num:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_spi_din_num_reg_t;
+
+
+/** Group: LP SPI DOUT MODE REG */
+/** Type of spi_dout_mode register
+ *  SPI output delay mode configuration
+ */
+typedef union {
+    struct {
+        /** reg_dout0_mode : R/W; bitpos: [0]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_dout0_mode:1;
+        /** reg_dout1_mode : R/W; bitpos: [1]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_dout1_mode:1;
+        /** reg_dout2_mode : R/W; bitpos: [2]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_dout2_mode:1;
+        /** reg_dout3_mode : R/W; bitpos: [3]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_dout3_mode:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lp_spi_dout_mode_reg_t;
+
+
+/** Group: LP SPI DMA CONF REG */
+/** Type of spi_dma_conf register
+ *  SPI DMA control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** reg_rx_afifo_rst : WT; bitpos: [29]; default: 0;
+         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+         *  slave mode transfer.
+         */
+        uint32_t reg_rx_afifo_rst:1;
+        /** reg_buf_afifo_rst : WT; bitpos: [30]; default: 0;
+         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+         *  controlled mode transfer and master mode transfer.
+         */
+        uint32_t reg_buf_afifo_rst:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} lp_spi_dma_conf_reg_t;
+
+
+/** Group: LP SPI DMA INT ENA REG */
+/** Type of spi_dma_int_ena register
+ *  SPI DMA interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** reg_slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t reg_slv_rd_buf_done_int_ena:1;
+        /** reg_slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t reg_slv_wr_buf_done_int_ena:1;
+        /** reg_trans_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The enable bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t reg_trans_done_int_ena:1;
+        uint32_t reserved_13:1;
+        /** reg_spi_wakeup_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The enable bit for SPI_WAKEUP_INT interrupt
+         */
+        uint32_t reg_spi_wakeup_int_ena:1;
+        /** reg_slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t reg_slv_buf_addr_err_int_ena:1;
+        /** reg_slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t reg_slv_cmd_err_int_ena:1;
+        /** reg_mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t reg_mst_rx_afifo_wfull_err_int_ena:1;
+        /** reg_mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0;
+         *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t reg_mst_tx_afifo_rempty_err_int_ena:1;
+        /** reg_app2_int_ena : R/W; bitpos: [19]; default: 0;
+         *  The enable bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t reg_app2_int_ena:1;
+        /** reg_app1_int_ena : R/W; bitpos: [20]; default: 0;
+         *  The enable bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t reg_app1_int_ena:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} lp_spi_dma_int_ena_reg_t;
+
+
+/** Group: LP SPI DMA INT CLR REG */
+/** Type of spi_dma_int_clr register
+ *  SPI DMA interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** reg_slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0;
+         *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t reg_slv_rd_buf_done_int_clr:1;
+        /** reg_slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0;
+         *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t reg_slv_wr_buf_done_int_clr:1;
+        /** reg_trans_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  The clear bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t reg_trans_done_int_clr:1;
+        uint32_t reserved_13:1;
+        /** reg_spi_wakeup_int_clr : WT; bitpos: [14]; default: 0;
+         *  The clear bit for SPI_WAKEUP_INT interrupt
+         */
+        uint32_t reg_spi_wakeup_int_clr:1;
+        /** reg_slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t reg_slv_buf_addr_err_int_clr:1;
+        /** reg_slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t reg_slv_cmd_err_int_clr:1;
+        /** reg_mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0;
+         *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t reg_mst_rx_afifo_wfull_err_int_clr:1;
+        /** reg_mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0;
+         *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t reg_mst_tx_afifo_rempty_err_int_clr:1;
+        /** reg_app2_int_clr : WT; bitpos: [19]; default: 0;
+         *  The clear bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t reg_app2_int_clr:1;
+        /** reg_app1_int_clr : WT; bitpos: [20]; default: 0;
+         *  The clear bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t reg_app1_int_clr:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} lp_spi_dma_int_clr_reg_t;
+
+
+/** Group: LP SPI DMA INT RAW REG */
+/** Type of spi_dma_int_raw register
+ *  SPI DMA interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** reg_slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t reg_slv_rd_buf_done_int_raw:1;
+        /** reg_slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t reg_slv_wr_buf_done_int_raw:1;
+        /** reg_trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+         *  ended. 0: others.
+         */
+        uint32_t reg_trans_done_int_raw:1;
+        uint32_t reserved_13:1;
+        /** reg_spi_wakeup_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit for SPI_SPI_WAKEUP_INT interrupt. 1: There is a  wake up signal when
+         *  low power mode. 0: Others.
+         */
+        uint32_t reg_spi_wakeup_int_raw:1;
+        /** reg_slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+         *  bigger than 63. 0: Others.
+         */
+        uint32_t reg_slv_buf_addr_err_int_raw:1;
+        /** reg_slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+         *  current SPI slave HD mode transmission is not supported. 0: Others.
+         */
+        uint32_t reg_slv_cmd_err_int_raw:1;
+        /** reg_mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+         *  write-full error when SPI inputs data in master mode. 0: Others.
+         */
+        uint32_t reg_mst_rx_afifo_wfull_err_int_raw:1;
+        /** reg_mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+         */
+        uint32_t reg_mst_tx_afifo_rempty_err_int_raw:1;
+        /** reg_app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.
+         */
+        uint32_t reg_app2_int_raw:1;
+        /** reg_app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.
+         */
+        uint32_t reg_app1_int_raw:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} lp_spi_dma_int_raw_reg_t;
+
+
+/** Group: LP SPI DMA INT ST REG */
+/** Type of spi_dma_int_st register
+ *  SPI DMA interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** reg_slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0;
+         *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t reg_slv_rd_buf_done_int_st:1;
+        /** reg_slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0;
+         *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t reg_slv_wr_buf_done_int_st:1;
+        /** reg_trans_done_int_st : RO; bitpos: [12]; default: 0;
+         *  The status bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t reg_trans_done_int_st:1;
+        uint32_t reserved_13:1;
+        /** reg_spi_wakeup_int_st : RO; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t reg_spi_wakeup_int_st:1;
+        /** reg_slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0;
+         *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t reg_slv_buf_addr_err_int_st:1;
+        /** reg_slv_cmd_err_int_st : RO; bitpos: [16]; default: 0;
+         *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t reg_slv_cmd_err_int_st:1;
+        /** reg_mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0;
+         *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t reg_mst_rx_afifo_wfull_err_int_st:1;
+        /** reg_mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0;
+         *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t reg_mst_tx_afifo_rempty_err_int_st:1;
+        /** reg_app2_int_st : RO; bitpos: [19]; default: 0;
+         *  The status bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t reg_app2_int_st:1;
+        /** reg_app1_int_st : RO; bitpos: [20]; default: 0;
+         *  The status bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t reg_app1_int_st:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} lp_spi_dma_int_st_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of spi_dma_int_set register
+ *  SPI interrupt software set register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** spi_slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0;
+         *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t spi_slv_rd_buf_done_int_set:1;
+        /** spi_slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0;
+         *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t spi_slv_wr_buf_done_int_set:1;
+        /** spi_trans_done_int_set : WT; bitpos: [12]; default: 0;
+         *  The software set bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t spi_trans_done_int_set:1;
+        uint32_t reserved_13:2;
+        /** spi_slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
+         *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t spi_slv_buf_addr_err_int_set:1;
+        /** spi_slv_cmd_err_int_set : WT; bitpos: [16]; default: 0;
+         *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t spi_slv_cmd_err_int_set:1;
+        /** spi_mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0;
+         *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t spi_mst_rx_afifo_wfull_err_int_set:1;
+        /** spi_mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0;
+         *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t spi_mst_tx_afifo_rempty_err_int_set:1;
+        /** spi_app2_int_set : WT; bitpos: [19]; default: 0;
+         *  The software set bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t spi_app2_int_set:1;
+        /** spi_app1_int_set : WT; bitpos: [20]; default: 0;
+         *  The software set bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t spi_app1_int_set:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} lp_spi_dma_int_set_reg_t;
+
+
+/** Group: LP SPI SLEEP CONF0 REG */
+/** Type of spi_sleep_conf0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_slv_wk_char0 : R/W; bitpos: [7:0]; default: 10;
+         *  NA
+         */
+        uint32_t reg_slv_wk_char0:8;
+        /** reg_slv_wk_char_num : R/W; bitpos: [10:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_slv_wk_char_num:3;
+        /** reg_slv_wk_char_mask : R/W; bitpos: [15:11]; default: 0;
+         *  NA
+         */
+        uint32_t reg_slv_wk_char_mask:5;
+        /** reg_slv_wk_mode_sel : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_slv_wk_mode_sel:1;
+        /** reg_sleep_en : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sleep_en:1;
+        /** reg_sleep_dis_rxfifo_wr_en : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sleep_dis_rxfifo_wr_en:1;
+        /** reg_sleep_wk_data_sel : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sleep_wk_data_sel:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_spi_sleep_conf0_reg_t;
+
+
+/** Group: LP SPI SLEEP CONF1 REG */
+/** Type of spi_sleep_conf1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_slv_wk_char1 : R/W; bitpos: [7:0]; default: 11;
+         *  NA
+         */
+        uint32_t reg_slv_wk_char1:8;
+        /** reg_slv_wk_char2 : R/W; bitpos: [15:8]; default: 12;
+         *  NA
+         */
+        uint32_t reg_slv_wk_char2:8;
+        /** reg_slv_wk_char3 : R/W; bitpos: [23:16]; default: 13;
+         *  NA
+         */
+        uint32_t reg_slv_wk_char3:8;
+        /** reg_slv_wk_char4 : R/W; bitpos: [31:24]; default: 14;
+         *  NA
+         */
+        uint32_t reg_slv_wk_char4:8;
+    };
+    uint32_t val;
+} lp_spi_sleep_conf1_reg_t;
+
+
+/** Group: LP SPI W0 REG */
+/** Type of spi_w0 register
+ *  SPI CPU-controlled buffer0
+ */
+typedef union {
+    struct {
+        /** reg_buf0 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf0:32;
+    };
+    uint32_t val;
+} lp_spi_w0_reg_t;
+
+
+/** Group: LP SPI W1 REG */
+/** Type of spi_w1 register
+ *  SPI CPU-controlled buffer1
+ */
+typedef union {
+    struct {
+        /** reg_buf1 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf1:32;
+    };
+    uint32_t val;
+} lp_spi_w1_reg_t;
+
+
+/** Group: LP SPI W2 REG */
+/** Type of spi_w2 register
+ *  SPI CPU-controlled buffer2
+ */
+typedef union {
+    struct {
+        /** reg_buf2 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf2:32;
+    };
+    uint32_t val;
+} lp_spi_w2_reg_t;
+
+
+/** Group: LP SPI W3 REG */
+/** Type of spi_w3 register
+ *  SPI CPU-controlled buffer3
+ */
+typedef union {
+    struct {
+        /** reg_buf3 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf3:32;
+    };
+    uint32_t val;
+} lp_spi_w3_reg_t;
+
+
+/** Group: LP SPI W4 REG */
+/** Type of spi_w4 register
+ *  SPI CPU-controlled buffer4
+ */
+typedef union {
+    struct {
+        /** reg_buf4 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf4:32;
+    };
+    uint32_t val;
+} lp_spi_w4_reg_t;
+
+
+/** Group: LP SPI W5 REG */
+/** Type of spi_w5 register
+ *  SPI CPU-controlled buffer5
+ */
+typedef union {
+    struct {
+        /** reg_buf5 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf5:32;
+    };
+    uint32_t val;
+} lp_spi_w5_reg_t;
+
+
+/** Group: LP SPI W6 REG */
+/** Type of spi_w6 register
+ *  SPI CPU-controlled buffer6
+ */
+typedef union {
+    struct {
+        /** reg_buf6 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf6:32;
+    };
+    uint32_t val;
+} lp_spi_w6_reg_t;
+
+
+/** Group: LP SPI W7 REG */
+/** Type of spi_w7 register
+ *  SPI CPU-controlled buffer7
+ */
+typedef union {
+    struct {
+        /** reg_buf7 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf7:32;
+    };
+    uint32_t val;
+} lp_spi_w7_reg_t;
+
+
+/** Group: LP SPI W8 REG */
+/** Type of spi_w8 register
+ *  SPI CPU-controlled buffer8
+ */
+typedef union {
+    struct {
+        /** reg_buf8 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf8:32;
+    };
+    uint32_t val;
+} lp_spi_w8_reg_t;
+
+
+/** Group: LP SPI W9 REG */
+/** Type of spi_w9 register
+ *  SPI CPU-controlled buffer9
+ */
+typedef union {
+    struct {
+        /** reg_buf9 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf9:32;
+    };
+    uint32_t val;
+} lp_spi_w9_reg_t;
+
+
+/** Group: LP SPI W10 REG */
+/** Type of spi_w10 register
+ *  SPI CPU-controlled buffer10
+ */
+typedef union {
+    struct {
+        /** reg_buf10 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf10:32;
+    };
+    uint32_t val;
+} lp_spi_w10_reg_t;
+
+
+/** Group: LP SPI W11 REG */
+/** Type of spi_w11 register
+ *  SPI CPU-controlled buffer11
+ */
+typedef union {
+    struct {
+        /** reg_buf11 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf11:32;
+    };
+    uint32_t val;
+} lp_spi_w11_reg_t;
+
+
+/** Group: LP SPI W12 REG */
+/** Type of spi_w12 register
+ *  SPI CPU-controlled buffer12
+ */
+typedef union {
+    struct {
+        /** reg_buf12 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf12:32;
+    };
+    uint32_t val;
+} lp_spi_w12_reg_t;
+
+
+/** Group: LP SPI W13 REG */
+/** Type of spi_w13 register
+ *  SPI CPU-controlled buffer13
+ */
+typedef union {
+    struct {
+        /** reg_buf13 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf13:32;
+    };
+    uint32_t val;
+} lp_spi_w13_reg_t;
+
+
+/** Group: LP SPI W14 REG */
+/** Type of spi_w14 register
+ *  SPI CPU-controlled buffer14
+ */
+typedef union {
+    struct {
+        /** reg_buf14 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf14:32;
+    };
+    uint32_t val;
+} lp_spi_w14_reg_t;
+
+
+/** Group: LP SPI W15 REG */
+/** Type of spi_w15 register
+ *  SPI CPU-controlled buffer15
+ */
+typedef union {
+    struct {
+        /** reg_buf15 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t reg_buf15:32;
+    };
+    uint32_t val;
+} lp_spi_w15_reg_t;
+
+
+/** Group: LP SPI SLAVE REG */
+/** Type of spi_slave register
+ *  SPI slave control register
+ */
+typedef union {
+    struct {
+        /** reg_clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on. Can be configured in CONF state.
+         */
+        uint32_t reg_clk_mode:2;
+        /** reg_clk_mode_13 : R/W; bitpos: [2]; default: 0;
+         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+         */
+        uint32_t reg_clk_mode_13:1;
+        /** reg_rsck_data_out : R/W; bitpos: [3]; default: 0;
+         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+         *  0: output data at tsck posedge
+         */
+        uint32_t reg_rsck_data_out:1;
+        uint32_t reserved_4:6;
+        /** reg_slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  CPU controlled mode(Rd_BUF). 0: others
+         */
+        uint32_t reg_slv_rdbuf_bitlen_en:1;
+        /** reg_slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in CPU controlled mode(Wr_BUF). 0: others
+         */
+        uint32_t reg_slv_wrbuf_bitlen_en:1;
+        uint32_t reserved_12:14;
+        /** reg_slave_mode : R/W; bitpos: [26]; default: 0;
+         *  Set SPI work mode. 1: slave mode 0: master mode.
+         */
+        uint32_t reg_slave_mode:1;
+        /** reg_soft_reset : WT; bitpos: [27]; default: 0;
+         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+         *  configured in CONF state.
+         */
+        uint32_t reg_soft_reset:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_spi_slave_reg_t;
+
+
+/** Group: LP SPI SLAVE1 REG */
+/** Type of spi_slave1 register
+ *  SPI slave control register 1
+ */
+typedef union {
+    struct {
+        /** reg_slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
+         *  The transferred data bit length in SPI slave FD and HD mode.
+         */
+        uint32_t reg_slv_data_bitlen:18;
+        /** reg_slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
+         *  In the slave mode it is the value of command.
+         */
+        uint32_t reg_slv_last_command:8;
+        /** reg_slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
+         *  In the slave mode it is the value of address.
+         */
+        uint32_t reg_slv_last_addr:6;
+    };
+    uint32_t val;
+} lp_spi_slave1_reg_t;
+
+
+/** Group: LP SPI CLK GATE REG */
+/** Type of spi_clk_gate register
+ *  SPI module clock and register clock control
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t reg_clk_en:1;
+        /** reg_mst_clk_active : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to power on the SPI module clock.
+         */
+        uint32_t reg_mst_clk_active:1;
+        /** reg_mst_clk_sel : R/W; bitpos: [2]; default: 0;
+         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+         *  0: XTAL CLK.
+         */
+        uint32_t reg_mst_clk_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} lp_spi_clk_gate_reg_t;
+
+
+/** Group: LP SPI DATE REG */
+/** Type of spi_date register
+ *  Version control
+ */
+typedef union {
+    struct {
+        /** reg_date : R/W; bitpos: [27:0]; default: 33591360;
+         *  SPI register version.
+         */
+        uint32_t reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_spi_date_reg_t;
+
+
+/** Group: LP RND ECO CS REG */
+/** Type of rnd_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rnd_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rnd_eco_en:1;
+        /** rnd_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t rnd_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_rnd_eco_cs_reg_t;
+
+
+/** Group: LP RND ECO LOW REG */
+/** Type of rnd_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rnd_eco_low:32;
+    };
+    uint32_t val;
+} lp_rnd_eco_low_reg_t;
+
+
+/** Group: LP RND ECO HIGH REG */
+/** Type of rnd_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rnd_eco_high : R/W; bitpos: [31:0]; default: 65535;
+         *  NA
+         */
+        uint32_t reg_rnd_eco_high:32;
+    };
+    uint32_t val;
+} lp_rnd_eco_high_reg_t;
+
+
+typedef struct {
+    volatile lp_spi_cmd_reg_t spi_cmd;
+    volatile lp_spi_addr_reg_t spi_addr;
+    volatile lp_spi_ctrl_reg_t spi_ctrl;
+    volatile lp_spi_clock_reg_t spi_clock;
+    volatile lp_spi_user_reg_t spi_user;
+    volatile lp_spi_user1_reg_t spi_user1;
+    volatile lp_spi_user2_reg_t spi_user2;
+    volatile lp_spi_ms_dlen_reg_t spi_ms_dlen;
+    volatile lp_spi_misc_reg_t spi_misc;
+    volatile lp_spi_din_mode_reg_t spi_din_mode;
+    volatile lp_spi_din_num_reg_t spi_din_num;
+    volatile lp_spi_dout_mode_reg_t spi_dout_mode;
+    volatile lp_spi_dma_conf_reg_t spi_dma_conf;
+    volatile lp_spi_dma_int_ena_reg_t spi_dma_int_ena;
+    volatile lp_spi_dma_int_clr_reg_t spi_dma_int_clr;
+    volatile lp_spi_dma_int_raw_reg_t spi_dma_int_raw;
+    volatile lp_spi_dma_int_st_reg_t spi_dma_int_st;
+    volatile lp_spi_sleep_conf0_reg_t spi_sleep_conf0;
+    volatile lp_spi_sleep_conf1_reg_t spi_sleep_conf1;
+    volatile lp_spi_dma_int_set_reg_t spi_dma_int_set;
+    uint32_t reserved_050[18];
+    volatile lp_spi_w0_reg_t spi_w0;
+    volatile lp_spi_w1_reg_t spi_w1;
+    volatile lp_spi_w2_reg_t spi_w2;
+    volatile lp_spi_w3_reg_t spi_w3;
+    volatile lp_spi_w4_reg_t spi_w4;
+    volatile lp_spi_w5_reg_t spi_w5;
+    volatile lp_spi_w6_reg_t spi_w6;
+    volatile lp_spi_w7_reg_t spi_w7;
+    volatile lp_spi_w8_reg_t spi_w8;
+    volatile lp_spi_w9_reg_t spi_w9;
+    volatile lp_spi_w10_reg_t spi_w10;
+    volatile lp_spi_w11_reg_t spi_w11;
+    volatile lp_spi_w12_reg_t spi_w12;
+    volatile lp_spi_w13_reg_t spi_w13;
+    volatile lp_spi_w14_reg_t spi_w14;
+    volatile lp_spi_w15_reg_t spi_w15;
+    uint32_t reserved_0d8[2];
+    volatile lp_spi_slave_reg_t spi_slave;
+    volatile lp_spi_slave1_reg_t spi_slave1;
+    volatile lp_spi_clk_gate_reg_t spi_clk_gate;
+    uint32_t reserved_0ec;
+    volatile lp_spi_date_reg_t spi_date;
+    volatile lp_rnd_eco_cs_reg_t rnd_eco_cs;
+    volatile lp_rnd_eco_low_reg_t rnd_eco_low;
+    volatile lp_rnd_eco_high_reg_t rnd_eco_high;
+} lp_dev_t;
+
+extern lp_dev_t LP_SPI;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_dev_t) == 0x100, "Invalid size of lp_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_system_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_system_reg.h
new file mode 100644
index 0000000000..3719697ee9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_system_reg.h
@@ -0,0 +1,1465 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_SYSTEM_REG_LP_SYSTEM_VER_DATE_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SYSTEM_VER_DATE_REG (DR_REG_LP_SYS_BASE + 0x0)
+/** LP_SYSTEM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539296276;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_VER_DATE    0xFFFFFFFFU
+#define LP_SYSTEM_REG_VER_DATE_M  (LP_SYSTEM_REG_VER_DATE_V << LP_SYSTEM_REG_VER_DATE_S)
+#define LP_SYSTEM_REG_VER_DATE_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_VER_DATE_S  0
+
+/** LP_SYSTEM_REG_CLK_SEL_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_CLK_SEL_CTRL_REG (DR_REG_LP_SYS_BASE + 0x4)
+/** LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK    (BIT(16))
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_M  (LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V << LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S)
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V  0x00000001U
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S  16
+/** LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL : R/W; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL    (BIT(17))
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_M  (LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V << LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S)
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S  17
+
+/** LP_SYSTEM_REG_SYS_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_SYS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x8)
+/** LP_SYSTEM_REG_LP_CORE_DISABLE : R/W; bitpos: [0]; default: 0;
+ *  lp cpu disable
+ */
+#define LP_SYSTEM_REG_LP_CORE_DISABLE    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_DISABLE_M  (LP_SYSTEM_REG_LP_CORE_DISABLE_V << LP_SYSTEM_REG_LP_CORE_DISABLE_S)
+#define LP_SYSTEM_REG_LP_CORE_DISABLE_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DISABLE_S  0
+/** LP_SYSTEM_REG_SYS_SW_RST : WT; bitpos: [1]; default: 0;
+ *  digital system software reset bit
+ */
+#define LP_SYSTEM_REG_SYS_SW_RST    (BIT(1))
+#define LP_SYSTEM_REG_SYS_SW_RST_M  (LP_SYSTEM_REG_SYS_SW_RST_V << LP_SYSTEM_REG_SYS_SW_RST_S)
+#define LP_SYSTEM_REG_SYS_SW_RST_V  0x00000001U
+#define LP_SYSTEM_REG_SYS_SW_RST_S  1
+/** LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT    (BIT(2))
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_M  (LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V << LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S)
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V  0x00000001U
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S  2
+/** LP_SYSTEM_REG_DIG_FIB : R/W; bitpos: [10:3]; default: 255;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_DIG_FIB    0x000000FFU
+#define LP_SYSTEM_REG_DIG_FIB_M  (LP_SYSTEM_REG_DIG_FIB_V << LP_SYSTEM_REG_DIG_FIB_S)
+#define LP_SYSTEM_REG_DIG_FIB_V  0x000000FFU
+#define LP_SYSTEM_REG_DIG_FIB_S  3
+/** LP_SYSTEM_REG_IO_MUX_RESET_DISABLE : R/W; bitpos: [11]; default: 0;
+ *  reset disable bit for LP IOMUX
+ */
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE    (BIT(11))
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_M  (LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V << LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S)
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V  0x00000001U
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S  11
+/** LP_SYSTEM_REG_ANA_FIB : RO; bitpos: [20:14]; default: 127;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_ANA_FIB    0x0000007FU
+#define LP_SYSTEM_REG_ANA_FIB_M  (LP_SYSTEM_REG_ANA_FIB_V << LP_SYSTEM_REG_ANA_FIB_S)
+#define LP_SYSTEM_REG_ANA_FIB_V  0x0000007FU
+#define LP_SYSTEM_REG_ANA_FIB_S  14
+/** LP_SYSTEM_REG_LP_FIB_SEL : R/W; bitpos: [28:21]; default: 255;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_FIB_SEL    0x000000FFU
+#define LP_SYSTEM_REG_LP_FIB_SEL_M  (LP_SYSTEM_REG_LP_FIB_SEL_V << LP_SYSTEM_REG_LP_FIB_SEL_S)
+#define LP_SYSTEM_REG_LP_FIB_SEL_V  0x000000FFU
+#define LP_SYSTEM_REG_LP_FIB_SEL_S  21
+/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR    (BIT(29))
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_M  (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S  29
+/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG    (BIT(30))
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_M  (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S)
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S  30
+/** LP_SYSTEM_REG_SYSTIMER_STALL_SEL : R/W; bitpos: [31]; default: 0;
+ *  0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from
+ *  hp_core1
+ */
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL    (BIT(31))
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_M  (LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V << LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S)
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S  31
+
+/** LP_SYSTEM_REG_LP_CLK_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0xc)
+/** LP_SYSTEM_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_CLK_EN    (BIT(0))
+#define LP_SYSTEM_REG_CLK_EN_M  (LP_SYSTEM_REG_CLK_EN_V << LP_SYSTEM_REG_CLK_EN_S)
+#define LP_SYSTEM_REG_CLK_EN_V  0x00000001U
+#define LP_SYSTEM_REG_CLK_EN_S  0
+/** LP_SYSTEM_REG_LP_FOSC_HP_CKEN : R/W; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN    (BIT(14))
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_M  (LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V << LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S)
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S  14
+
+/** LP_SYSTEM_REG_LP_RST_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_RST_CTRL_REG (DR_REG_LP_SYS_BASE + 0x10)
+/** LP_SYSTEM_REG_ANA_RST_BYPASS : R/W; bitpos: [0]; default: 1;
+ *  analog source reset bypass : wdt,brown out,super wdt,glitch
+ */
+#define LP_SYSTEM_REG_ANA_RST_BYPASS    (BIT(0))
+#define LP_SYSTEM_REG_ANA_RST_BYPASS_M  (LP_SYSTEM_REG_ANA_RST_BYPASS_V << LP_SYSTEM_REG_ANA_RST_BYPASS_S)
+#define LP_SYSTEM_REG_ANA_RST_BYPASS_V  0x00000001U
+#define LP_SYSTEM_REG_ANA_RST_BYPASS_S  0
+/** LP_SYSTEM_REG_SYS_RST_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  system source reset bypass : software reset,hp wdt,lp wdt,efuse
+ */
+#define LP_SYSTEM_REG_SYS_RST_BYPASS    (BIT(1))
+#define LP_SYSTEM_REG_SYS_RST_BYPASS_M  (LP_SYSTEM_REG_SYS_RST_BYPASS_V << LP_SYSTEM_REG_SYS_RST_BYPASS_S)
+#define LP_SYSTEM_REG_SYS_RST_BYPASS_V  0x00000001U
+#define LP_SYSTEM_REG_SYS_RST_BYPASS_S  1
+/** LP_SYSTEM_REG_EFUSE_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  efuse force no reset control
+ */
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST    (BIT(2))
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_M  (LP_SYSTEM_REG_EFUSE_FORCE_NORST_V << LP_SYSTEM_REG_EFUSE_FORCE_NORST_S)
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_V  0x00000001U
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_S  2
+
+/** LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG (DR_REG_LP_SYS_BASE + 0x18)
+/** LP_SYSTEM_REG_LP_CPU_BOOT_ADDR : R/W; bitpos: [31:0]; default: 1343225856;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_M  (LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V << LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S)
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S  0
+
+/** LP_SYSTEM_REG_EXT_WAKEUP1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_REG (DR_REG_LP_SYS_BASE + 0x1c)
+/** LP_SYSTEM_REG_EXT_WAKEUP1_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  Bitmap to select RTC pads for ext wakeup1
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL    0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_M  (LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V << LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S)
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V  0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S  0
+/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR : WT; bitpos: [16]; default: 0;
+ *  clear ext wakeup1 status
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR    (BIT(16))
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_M  (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S)
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S  16
+
+/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG (DR_REG_LP_SYS_BASE + 0x20)
+/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS : RO; bitpos: [15:0]; default: 0;
+ *  ext wakeup1 status
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS    0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_M  (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S)
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V  0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG (DR_REG_LP_SYS_BASE + 0x24)
+/** LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON    (BIT(5))
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_M  (LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S  5
+/** LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON    (BIT(7))
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_M  (LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S  7
+
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG (DR_REG_LP_SYS_BASE + 0x28)
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP    0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_M  (LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V << LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S)
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S  0
+
+/** LP_SYSTEM_REG_LP_STORE0_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE0_REG (DR_REG_LP_SYS_BASE + 0x2c)
+/** LP_SYSTEM_REG_LP_SCRATCH0 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH0    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH0_M  (LP_SYSTEM_REG_LP_SCRATCH0_V << LP_SYSTEM_REG_LP_SCRATCH0_S)
+#define LP_SYSTEM_REG_LP_SCRATCH0_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH0_S  0
+
+/** LP_SYSTEM_REG_LP_STORE1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE1_REG (DR_REG_LP_SYS_BASE + 0x30)
+/** LP_SYSTEM_REG_LP_SCRATCH1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH1    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH1_M  (LP_SYSTEM_REG_LP_SCRATCH1_V << LP_SYSTEM_REG_LP_SCRATCH1_S)
+#define LP_SYSTEM_REG_LP_SCRATCH1_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH1_S  0
+
+/** LP_SYSTEM_REG_LP_STORE2_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE2_REG (DR_REG_LP_SYS_BASE + 0x34)
+/** LP_SYSTEM_REG_LP_SCRATCH2 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH2    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH2_M  (LP_SYSTEM_REG_LP_SCRATCH2_V << LP_SYSTEM_REG_LP_SCRATCH2_S)
+#define LP_SYSTEM_REG_LP_SCRATCH2_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH2_S  0
+
+/** LP_SYSTEM_REG_LP_STORE3_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE3_REG (DR_REG_LP_SYS_BASE + 0x38)
+/** LP_SYSTEM_REG_LP_SCRATCH3 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH3    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH3_M  (LP_SYSTEM_REG_LP_SCRATCH3_V << LP_SYSTEM_REG_LP_SCRATCH3_S)
+#define LP_SYSTEM_REG_LP_SCRATCH3_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH3_S  0
+
+/** LP_SYSTEM_REG_LP_STORE4_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE4_REG (DR_REG_LP_SYS_BASE + 0x3c)
+/** LP_SYSTEM_REG_LP_SCRATCH4 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH4    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH4_M  (LP_SYSTEM_REG_LP_SCRATCH4_V << LP_SYSTEM_REG_LP_SCRATCH4_S)
+#define LP_SYSTEM_REG_LP_SCRATCH4_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH4_S  0
+
+/** LP_SYSTEM_REG_LP_STORE5_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE5_REG (DR_REG_LP_SYS_BASE + 0x40)
+/** LP_SYSTEM_REG_LP_SCRATCH5 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH5    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH5_M  (LP_SYSTEM_REG_LP_SCRATCH5_V << LP_SYSTEM_REG_LP_SCRATCH5_S)
+#define LP_SYSTEM_REG_LP_SCRATCH5_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH5_S  0
+
+/** LP_SYSTEM_REG_LP_STORE6_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE6_REG (DR_REG_LP_SYS_BASE + 0x44)
+/** LP_SYSTEM_REG_LP_SCRATCH6 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH6    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH6_M  (LP_SYSTEM_REG_LP_SCRATCH6_V << LP_SYSTEM_REG_LP_SCRATCH6_S)
+#define LP_SYSTEM_REG_LP_SCRATCH6_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH6_S  0
+
+/** LP_SYSTEM_REG_LP_STORE7_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE7_REG (DR_REG_LP_SYS_BASE + 0x48)
+/** LP_SYSTEM_REG_LP_SCRATCH7 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH7    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH7_M  (LP_SYSTEM_REG_LP_SCRATCH7_V << LP_SYSTEM_REG_LP_SCRATCH7_S)
+#define LP_SYSTEM_REG_LP_SCRATCH7_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH7_S  0
+
+/** LP_SYSTEM_REG_LP_STORE8_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE8_REG (DR_REG_LP_SYS_BASE + 0x4c)
+/** LP_SYSTEM_REG_LP_SCRATCH8 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH8    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH8_M  (LP_SYSTEM_REG_LP_SCRATCH8_V << LP_SYSTEM_REG_LP_SCRATCH8_S)
+#define LP_SYSTEM_REG_LP_SCRATCH8_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH8_S  0
+
+/** LP_SYSTEM_REG_LP_STORE9_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE9_REG (DR_REG_LP_SYS_BASE + 0x50)
+/** LP_SYSTEM_REG_LP_SCRATCH9 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH9    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH9_M  (LP_SYSTEM_REG_LP_SCRATCH9_V << LP_SYSTEM_REG_LP_SCRATCH9_S)
+#define LP_SYSTEM_REG_LP_SCRATCH9_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH9_S  0
+
+/** LP_SYSTEM_REG_LP_STORE10_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE10_REG (DR_REG_LP_SYS_BASE + 0x54)
+/** LP_SYSTEM_REG_LP_SCRATCH10 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH10    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH10_M  (LP_SYSTEM_REG_LP_SCRATCH10_V << LP_SYSTEM_REG_LP_SCRATCH10_S)
+#define LP_SYSTEM_REG_LP_SCRATCH10_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH10_S  0
+
+/** LP_SYSTEM_REG_LP_STORE11_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE11_REG (DR_REG_LP_SYS_BASE + 0x58)
+/** LP_SYSTEM_REG_LP_SCRATCH11 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH11    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH11_M  (LP_SYSTEM_REG_LP_SCRATCH11_V << LP_SYSTEM_REG_LP_SCRATCH11_S)
+#define LP_SYSTEM_REG_LP_SCRATCH11_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH11_S  0
+
+/** LP_SYSTEM_REG_LP_STORE12_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE12_REG (DR_REG_LP_SYS_BASE + 0x5c)
+/** LP_SYSTEM_REG_LP_SCRATCH12 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH12    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH12_M  (LP_SYSTEM_REG_LP_SCRATCH12_V << LP_SYSTEM_REG_LP_SCRATCH12_S)
+#define LP_SYSTEM_REG_LP_SCRATCH12_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH12_S  0
+
+/** LP_SYSTEM_REG_LP_STORE13_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE13_REG (DR_REG_LP_SYS_BASE + 0x60)
+/** LP_SYSTEM_REG_LP_SCRATCH13 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH13    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH13_M  (LP_SYSTEM_REG_LP_SCRATCH13_V << LP_SYSTEM_REG_LP_SCRATCH13_S)
+#define LP_SYSTEM_REG_LP_SCRATCH13_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH13_S  0
+
+/** LP_SYSTEM_REG_LP_STORE14_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE14_REG (DR_REG_LP_SYS_BASE + 0x64)
+/** LP_SYSTEM_REG_LP_SCRATCH14 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH14    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH14_M  (LP_SYSTEM_REG_LP_SCRATCH14_V << LP_SYSTEM_REG_LP_SCRATCH14_S)
+#define LP_SYSTEM_REG_LP_SCRATCH14_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH14_S  0
+
+/** LP_SYSTEM_REG_LP_STORE15_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE15_REG (DR_REG_LP_SYS_BASE + 0x68)
+/** LP_SYSTEM_REG_LP_SCRATCH15 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH15    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH15_M  (LP_SYSTEM_REG_LP_SCRATCH15_V << LP_SYSTEM_REG_LP_SCRATCH15_S)
+#define LP_SYSTEM_REG_LP_SCRATCH15_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH15_S  0
+
+/** LP_SYSTEM_REG_LP_PROBEA_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PROBEA_CTRL_REG (DR_REG_LP_SYS_BASE + 0x6c)
+/** LP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_M  (LP_SYSTEM_REG_PROBE_A_MOD_SEL_V << LP_SYSTEM_REG_PROBE_A_MOD_SEL_S)
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
+/** LP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (LP_SYSTEM_REG_PROBE_A_TOP_SEL_V << LP_SYSTEM_REG_PROBE_A_TOP_SEL_S)
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
+/** LP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
+#define LP_SYSTEM_REG_PROBE_L_SEL_M  (LP_SYSTEM_REG_PROBE_L_SEL_V << LP_SYSTEM_REG_PROBE_L_SEL_S)
+#define LP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
+#define LP_SYSTEM_REG_PROBE_L_SEL_S  24
+/** LP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
+#define LP_SYSTEM_REG_PROBE_H_SEL_M  (LP_SYSTEM_REG_PROBE_H_SEL_V << LP_SYSTEM_REG_PROBE_H_SEL_S)
+#define LP_SYSTEM_REG_PROBE_H_SEL_V  0x00000003U
+#define LP_SYSTEM_REG_PROBE_H_SEL_S  26
+/** LP_SYSTEM_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN    (BIT(28))
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_M  (LP_SYSTEM_REG_PROBE_GLOBAL_EN_V << LP_SYSTEM_REG_PROBE_GLOBAL_EN_S)
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_V  0x00000001U
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_S  28
+
+/** LP_SYSTEM_REG_LP_PROBEB_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PROBEB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x70)
+/** LP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_M  (LP_SYSTEM_REG_PROBE_B_MOD_SEL_V << LP_SYSTEM_REG_PROBE_B_MOD_SEL_S)
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
+/** LP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (LP_SYSTEM_REG_PROBE_B_TOP_SEL_V << LP_SYSTEM_REG_PROBE_B_TOP_SEL_S)
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_V  0x000000FFU
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_S  16
+/** LP_SYSTEM_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_B_EN    (BIT(24))
+#define LP_SYSTEM_REG_PROBE_B_EN_M  (LP_SYSTEM_REG_PROBE_B_EN_V << LP_SYSTEM_REG_PROBE_B_EN_S)
+#define LP_SYSTEM_REG_PROBE_B_EN_V  0x00000001U
+#define LP_SYSTEM_REG_PROBE_B_EN_S  24
+
+/** LP_SYSTEM_REG_LP_PROBE_OUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PROBE_OUT_REG (DR_REG_LP_SYS_BASE + 0x74)
+/** LP_SYSTEM_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_TOP_OUT    0xFFFFFFFFU
+#define LP_SYSTEM_REG_PROBE_TOP_OUT_M  (LP_SYSTEM_REG_PROBE_TOP_OUT_V << LP_SYSTEM_REG_PROBE_TOP_OUT_S)
+#define LP_SYSTEM_REG_PROBE_TOP_OUT_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_PROBE_TOP_OUT_S  0
+
+/** LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG (DR_REG_LP_SYS_BASE + 0x9c)
+/** LP_SYSTEM_REG_F2S_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN    (BIT(0))
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_M  (LP_SYSTEM_REG_F2S_APB_POSTW_EN_V << LP_SYSTEM_REG_F2S_APB_POSTW_EN_S)
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_V  0x00000001U
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_S  0
+
+/** LP_SYSTEM_REG_USB_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_USB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x100)
+/** LP_SYSTEM_REG_SW_HW_USB_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL    (BIT(0))
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_M  (LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S)
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S  0
+/** LP_SYSTEM_REG_SW_USB_PHY_SEL : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL    (BIT(1))
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL_M  (LP_SYSTEM_REG_SW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_USB_PHY_SEL_S)
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL_S  1
+/** LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR : WT; bitpos: [2]; default: 0;
+ *  clear usb wakeup to PMU.
+ */
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR    (BIT(2))
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_M  (LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V << LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S)
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S  2
+/** LP_SYSTEM_REG_USBOTG20_IN_SUSPEND : R/W; bitpos: [3]; default: 0;
+ *  indicate usb otg2.0 is in suspend state.
+ */
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND    (BIT(3))
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_M  (LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V << LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S)
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V  0x00000001U
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S  3
+/** LP_SYSTEM_REG_USBOTG20_LS_MODE : R/W; bitpos: [4]; default: 0;
+ *  indicate current mode of usb otg2.0.
+ */
+#define LP_SYSTEM_REG_USBOTG20_LS_MODE    (BIT(4))
+#define LP_SYSTEM_REG_USBOTG20_LS_MODE_M  (LP_SYSTEM_REG_USBOTG20_LS_MODE_V << LP_SYSTEM_REG_USBOTG20_LS_MODE_S)
+#define LP_SYSTEM_REG_USBOTG20_LS_MODE_V  0x00000001U
+#define LP_SYSTEM_REG_USBOTG20_LS_MODE_S  4
+
+/** LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG (DR_REG_LP_SYS_BASE + 0x10c)
+/** LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP : R/W; bitpos: [7:0]; default: 255;
+ *  Set 1 to power up pad group
+ */
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP    0x000000FFU
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_M  (LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V << LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S)
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V  0x000000FFU
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x110)
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S  0
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT    (BIT(1))
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S  1
+
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x114)
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x118)
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x11c)
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S  0
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT    (BIT(1))
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S  1
+
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x120)
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x124)
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S  0
+
+/** LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0x130)
+/** LP_SYSTEM_REG_CPU_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  clock gate enable for hp cpu root 400M clk
+ */
+#define LP_SYSTEM_REG_CPU_CLK_EN    (BIT(0))
+#define LP_SYSTEM_REG_CPU_CLK_EN_M  (LP_SYSTEM_REG_CPU_CLK_EN_V << LP_SYSTEM_REG_CPU_CLK_EN_S)
+#define LP_SYSTEM_REG_CPU_CLK_EN_V  0x00000001U
+#define LP_SYSTEM_REG_CPU_CLK_EN_S  0
+/** LP_SYSTEM_REG_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  clock gate enable for hp sys root 480M clk
+ */
+#define LP_SYSTEM_REG_SYS_CLK_EN    (BIT(1))
+#define LP_SYSTEM_REG_SYS_CLK_EN_M  (LP_SYSTEM_REG_SYS_CLK_EN_V << LP_SYSTEM_REG_SYS_CLK_EN_S)
+#define LP_SYSTEM_REG_SYS_CLK_EN_V  0x00000001U
+#define LP_SYSTEM_REG_SYS_CLK_EN_S  1
+
+/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x138)
+/** LP_SYSTEM_REG_PMU_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW    0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_M  (LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V << LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S)
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S  0
+
+/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x13c)
+/** LP_SYSTEM_REG_PMU_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH    0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V << LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S)
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S  0
+
+/** LP_SYSTEM_REG_PAD_COMP0_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PAD_COMP0_REG (DR_REG_LP_SYS_BASE + 0x148)
+/** LP_SYSTEM_REG_DREF_COMP0 : R/W; bitpos: [2:0]; default: 0;
+ *  pad comp dref
+ */
+#define LP_SYSTEM_REG_DREF_COMP0    0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP0_M  (LP_SYSTEM_REG_DREF_COMP0_V << LP_SYSTEM_REG_DREF_COMP0_S)
+#define LP_SYSTEM_REG_DREF_COMP0_V  0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP0_S  0
+/** LP_SYSTEM_REG_MODE_COMP0 : R/W; bitpos: [3]; default: 0;
+ *  pad comp mode
+ */
+#define LP_SYSTEM_REG_MODE_COMP0    (BIT(3))
+#define LP_SYSTEM_REG_MODE_COMP0_M  (LP_SYSTEM_REG_MODE_COMP0_V << LP_SYSTEM_REG_MODE_COMP0_S)
+#define LP_SYSTEM_REG_MODE_COMP0_V  0x00000001U
+#define LP_SYSTEM_REG_MODE_COMP0_S  3
+/** LP_SYSTEM_REG_XPD_COMP0 : R/W; bitpos: [4]; default: 0;
+ *  pad comp xpd
+ */
+#define LP_SYSTEM_REG_XPD_COMP0    (BIT(4))
+#define LP_SYSTEM_REG_XPD_COMP0_M  (LP_SYSTEM_REG_XPD_COMP0_V << LP_SYSTEM_REG_XPD_COMP0_S)
+#define LP_SYSTEM_REG_XPD_COMP0_V  0x00000001U
+#define LP_SYSTEM_REG_XPD_COMP0_S  4
+
+/** LP_SYSTEM_REG_PAD_COMP1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PAD_COMP1_REG (DR_REG_LP_SYS_BASE + 0x14c)
+/** LP_SYSTEM_REG_DREF_COMP1 : R/W; bitpos: [2:0]; default: 0;
+ *  pad comp dref
+ */
+#define LP_SYSTEM_REG_DREF_COMP1    0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP1_M  (LP_SYSTEM_REG_DREF_COMP1_V << LP_SYSTEM_REG_DREF_COMP1_S)
+#define LP_SYSTEM_REG_DREF_COMP1_V  0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP1_S  0
+/** LP_SYSTEM_REG_MODE_COMP1 : R/W; bitpos: [3]; default: 0;
+ *  pad comp mode
+ */
+#define LP_SYSTEM_REG_MODE_COMP1    (BIT(3))
+#define LP_SYSTEM_REG_MODE_COMP1_M  (LP_SYSTEM_REG_MODE_COMP1_V << LP_SYSTEM_REG_MODE_COMP1_S)
+#define LP_SYSTEM_REG_MODE_COMP1_V  0x00000001U
+#define LP_SYSTEM_REG_MODE_COMP1_S  3
+/** LP_SYSTEM_REG_XPD_COMP1 : R/W; bitpos: [4]; default: 0;
+ *  pad comp xpd
+ */
+#define LP_SYSTEM_REG_XPD_COMP1    (BIT(4))
+#define LP_SYSTEM_REG_XPD_COMP1_M  (LP_SYSTEM_REG_XPD_COMP1_V << LP_SYSTEM_REG_XPD_COMP1_S)
+#define LP_SYSTEM_REG_XPD_COMP1_V  0x00000001U
+#define LP_SYSTEM_REG_XPD_COMP1_S  4
+
+/** LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG (DR_REG_LP_SYS_BASE + 0x154)
+/** LP_SYSTEM_REG_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BURST_LIMIT_AON    0x0000001FU
+#define LP_SYSTEM_REG_BURST_LIMIT_AON_M  (LP_SYSTEM_REG_BURST_LIMIT_AON_V << LP_SYSTEM_REG_BURST_LIMIT_AON_S)
+#define LP_SYSTEM_REG_BURST_LIMIT_AON_V  0x0000001FU
+#define LP_SYSTEM_REG_BURST_LIMIT_AON_S  0
+/** LP_SYSTEM_REG_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_READ_INTERVAL_AON    0x0000007FU
+#define LP_SYSTEM_REG_READ_INTERVAL_AON_M  (LP_SYSTEM_REG_READ_INTERVAL_AON_V << LP_SYSTEM_REG_READ_INTERVAL_AON_S)
+#define LP_SYSTEM_REG_READ_INTERVAL_AON_V  0x0000007FU
+#define LP_SYSTEM_REG_READ_INTERVAL_AON_S  5
+/** LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [21:12]; default: 100;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON    0x000003FFU
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_M  (LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S)
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V  0x000003FFU
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S  12
+/** LP_SYSTEM_REG_LINK_TOUT_THRES_AON : R/W; bitpos: [31:22]; default: 100;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON    0x000003FFU
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_M  (LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S)
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V  0x000003FFU
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S  22
+
+/** LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG (DR_REG_LP_SYS_BASE + 0x158)
+/** LP_SYSTEM_REG_AON_BYPASS : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_AON_BYPASS    (BIT(31))
+#define LP_SYSTEM_REG_AON_BYPASS_M  (LP_SYSTEM_REG_AON_BYPASS_V << LP_SYSTEM_REG_AON_BYPASS_S)
+#define LP_SYSTEM_REG_AON_BYPASS_V  0x00000001U
+#define LP_SYSTEM_REG_AON_BYPASS_S  31
+
+/** LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG (DR_REG_LP_SYS_BASE + 0x15c)
+/** LP_SYSTEM_REG_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LINK_ADDR_AON    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LINK_ADDR_AON_M  (LP_SYSTEM_REG_LINK_ADDR_AON_V << LP_SYSTEM_REG_LINK_ADDR_AON_S)
+#define LP_SYSTEM_REG_LINK_ADDR_AON_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LINK_ADDR_AON_S  0
+
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG (DR_REG_LP_SYS_BASE + 0x164)
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1    0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_M  (LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V << LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S)
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S  0
+
+/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x168)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S  0
+
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x16c)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
+ *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
+ *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
+ *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID    0x0000001FU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_M  (LP_SYSTEM_REG_LP_ADDRHOLE_ID_V << LP_SYSTEM_REG_LP_ADDRHOLE_ID_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_V  0x0000001FU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_S  0
+/** LP_SYSTEM_REG_LP_ADDRHOLE_WR : RO; bitpos: [5]; default: 0;
+ *  1:write trans, 0: read trans.
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR    (BIT(5))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_WR_V << LP_SYSTEM_REG_LP_ADDRHOLE_WR_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_S  5
+/** LP_SYSTEM_REG_LP_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0;
+ *  1: illegal address access, 0: access without permission
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE    (BIT(6))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_M  (LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S  6
+
+/** LP_SYSTEM_REG_INT_RAW_REG register
+ *  raw interrupt register
+ */
+#define LP_SYSTEM_REG_INT_RAW_REG (DR_REG_LP_SYS_BASE + 0x170)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  the raw interrupt status of lp addrhole(for lp peri  and lp ram tee apm, and lp
+ *  matrix default slave)
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  the raw interrupt status of lp core ahb bus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  the raw interrupt status of lp core  ibus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  the raw interrupt status of lp core  dbus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  the raw interrupt status of etm task ulp
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  the raw interrupt status of slow_clk_tick
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S  6
+
+/** LP_SYSTEM_REG_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define LP_SYSTEM_REG_INT_ST_REG (DR_REG_LP_SYS_BASE + 0x174)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of lp addrhole (for lp peri  and lp ram tee apm, and lp
+ *  matrix default slave)
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  the masked interrupt status of lp core ahb bus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  the masked interrupt status of lp core  ibus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  the masked interrupt status of lp core  dbus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST : RO; bitpos: [5]; default: 0;
+ *  the masked interrupt status of etm task ulp
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST : RO; bitpos: [6]; default: 0;
+ *  the masked interrupt status of slow_clk_tick
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S  6
+
+/** LP_SYSTEM_REG_INT_ENA_REG register
+ *  masked interrupt register
+ */
+#define LP_SYSTEM_REG_INT_ENA_REG (DR_REG_LP_SYS_BASE + 0x178)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable lp addrhole int
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable idbus addrhole int
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable lp_core_ahb_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable lp_core_ibus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable lp_core_dbus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable etm task ulp int
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable slow_clk_tick int
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S  6
+
+/** LP_SYSTEM_REG_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define LP_SYSTEM_REG_INT_CLR_REG (DR_REG_LP_SYS_BASE + 0x17c)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  write 1 to clear lp addrhole int
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  write 1 to clear idbus addrhole int
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear lp_core_ahb_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear lp_core_ibus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear lp_core_dbus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear etm tasl ulp int
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear slow_clk_tick int
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S  6
+
+/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x180)
+/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_M  (LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x184)
+/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_M  (LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x188)
+/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_M  (LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x18c)
+/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_M  (LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_LP_CPU_DBG_PC_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_REG (DR_REG_LP_SYS_BASE + 0x190)
+/** LP_SYSTEM_REG_LP_CPU_DBG_PC : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_M  (LP_SYSTEM_REG_LP_CPU_DBG_PC_V << LP_SYSTEM_REG_LP_CPU_DBG_PC_S)
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_S  0
+
+/** LP_SYSTEM_REG_LP_CPU_EXC_PC_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_REG (DR_REG_LP_SYS_BASE + 0x194)
+/** LP_SYSTEM_REG_LP_CPU_EXC_PC : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_M  (LP_SYSTEM_REG_LP_CPU_EXC_PC_V << LP_SYSTEM_REG_LP_CPU_EXC_PC_S)
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_S  0
+
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x198)
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR    0xFFFFFFFFU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S  0
+
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x19c)
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID    0x0000001FU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V  0x0000001FU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR    (BIT(5))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S  5
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE    (BIT(6))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S  6
+
+/** LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x1a0)
+/** LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL : R/W; bitpos: [15:8]; default: 255;
+ *  [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn
+ *  [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn
+ *  [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn
+ *  [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn
+ *  [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst
+ *  [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst
+ *  [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn
+ *  [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn
+ */
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL    0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_M  (LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S)
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V  0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S  8
+/** LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL : R/W; bitpos: [31:24]; default: 255;
+ *  [31] 1'b1: po_rstn bypass sys_sw_rstn
+ *  [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn
+ *  [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn
+ *  [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn
+ *  [27] 1'b1: po_rstn bypass usb_jtag_chip_rst
+ *  [26] 1'b1: po_rstn bypass usb_uart_chip_rst
+ *  [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn
+ *  [24] 1'b1: po_rstn bypass efuse_err_rstn
+ */
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL    0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_M  (LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S)
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V  0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S  24
+
+/** LP_SYSTEM_REG_RNG_DATA_REG register
+ *  rng data register
+ */
+#define LP_SYSTEM_REG_RNG_DATA_REG (DR_REG_LP_SYS_BASE + 0x1a4)
+/** LP_SYSTEM_REG_RND_DATA : RO; bitpos: [31:0]; default: 0;
+ *  result of rng output
+ */
+#define LP_SYSTEM_REG_RND_DATA    0xFFFFFFFFU
+#define LP_SYSTEM_REG_RND_DATA_M  (LP_SYSTEM_REG_RND_DATA_V << LP_SYSTEM_REG_RND_DATA_S)
+#define LP_SYSTEM_REG_RND_DATA_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_RND_DATA_S  0
+
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b0)
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable lp core ahb timeout handle
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S  0
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set lp core ahb bus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES    0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V  0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S  1
+/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN : R/W; bitpos: [17]; default: 1;
+ *  set this field to 1 to enable lp2hp ahb timeout handle
+ */
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN    (BIT(17))
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S  17
+/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES : R/W; bitpos: [22:18]; default: 31;
+ *  This field used to set lp2hp ahb bus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES    0x0000001FU
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V  0x0000001FU
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S  18
+
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b4)
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable lp core ibus timeout handle
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S  0
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set lp core ibus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S  1
+
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b8)
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable lp core dbus timeout handle
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S  0
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set lp core dbus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S  1
+
+/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG (DR_REG_LP_SYS_BASE + 0x1bc)
+/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
+ *  Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to
+ *  disable ahb err resp.
+ */
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS    0x00000007U
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_M  (LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V << LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S)
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V  0x00000007U
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S  0
+
+/** LP_SYSTEM_REG_RNG_CFG_REG register
+ *  rng cfg register
+ */
+#define LP_SYSTEM_REG_RNG_CFG_REG (DR_REG_LP_SYS_BASE + 0x1c0)
+/** LP_SYSTEM_REG_RNG_TIMER_EN : R/W; bitpos: [0]; default: 1;
+ *  enable rng timer
+ */
+#define LP_SYSTEM_REG_RNG_TIMER_EN    (BIT(0))
+#define LP_SYSTEM_REG_RNG_TIMER_EN_M  (LP_SYSTEM_REG_RNG_TIMER_EN_V << LP_SYSTEM_REG_RNG_TIMER_EN_S)
+#define LP_SYSTEM_REG_RNG_TIMER_EN_V  0x00000001U
+#define LP_SYSTEM_REG_RNG_TIMER_EN_S  0
+/** LP_SYSTEM_REG_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 1;
+ *  configure ng timer pscale
+ */
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE    0x000000FFU
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_M  (LP_SYSTEM_REG_RNG_TIMER_PSCALE_V << LP_SYSTEM_REG_RNG_TIMER_PSCALE_S)
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_V  0x000000FFU
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_S  1
+/** LP_SYSTEM_REG_RNG_SAR_ENABLE : R/W; bitpos: [9]; default: 0;
+ *  enable rng_saradc
+ */
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE    (BIT(9))
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE_M  (LP_SYSTEM_REG_RNG_SAR_ENABLE_V << LP_SYSTEM_REG_RNG_SAR_ENABLE_S)
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE_V  0x00000001U
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE_S  9
+/** LP_SYSTEM_REG_RNG_SAR_DATA : RO; bitpos: [28:16]; default: 0;
+ *  debug rng sar sample cnt
+ */
+#define LP_SYSTEM_REG_RNG_SAR_DATA    0x00001FFFU
+#define LP_SYSTEM_REG_RNG_SAR_DATA_M  (LP_SYSTEM_REG_RNG_SAR_DATA_V << LP_SYSTEM_REG_RNG_SAR_DATA_S)
+#define LP_SYSTEM_REG_RNG_SAR_DATA_V  0x00001FFFU
+#define LP_SYSTEM_REG_RNG_SAR_DATA_S  16
+
+/** LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_REG register
+ *  enable pad hold ctrl
+ */
+#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_REG (DR_REG_LP_SYS_BASE + 0x1c4)
+/** LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0 : R/W; bitpos: [31:0]; default: 0;
+ *  Set 1 to hold pad 0-31 status
+ */
+#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0    0xFFFFFFFFU
+#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_M  (LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_V << LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_S)
+#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_S  0
+
+/** LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_REG register
+ *  enable pad hold ctrl
+ */
+#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_REG (DR_REG_LP_SYS_BASE + 0x1c8)
+/** LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1 : R/W; bitpos: [24:0]; default: 0;
+ *  Set 1 to hold pad 32-56 status
+ */
+#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1    0x01FFFFFFU
+#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_M  (LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_V << LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_S)
+#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_V  0x01FFFFFFU
+#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_S  0
+
+/** LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_REG register
+ *  enable pad hold ctrl
+ */
+#define LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_REG (DR_REG_LP_SYS_BASE + 0x1cc)
+/** LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL : R/W; bitpos: [25:0]; default: 0;
+ *  Set bit0-5 to hold flash pad status. Set bit6-25 to hold psram pad status.
+ */
+#define LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL    0x03FFFFFFU
+#define LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_M  (LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_V << LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_S)
+#define LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_V  0x03FFFFFFU
+#define LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_S  0
+
+/** LP_SYSTEM_REG_DISCHARGE_REG register
+ *  pufmem / ldo flash power discharge control
+ */
+#define LP_SYSTEM_REG_DISCHARGE_REG (DR_REG_LP_SYS_BASE + 0x200)
+/** LP_SYSTEM_REG_LDO_FLASH_DISCHARGE : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to discharge ldo flash.
+ */
+#define LP_SYSTEM_REG_LDO_FLASH_DISCHARGE    (BIT(0))
+#define LP_SYSTEM_REG_LDO_FLASH_DISCHARGE_M  (LP_SYSTEM_REG_LDO_FLASH_DISCHARGE_V << LP_SYSTEM_REG_LDO_FLASH_DISCHARGE_S)
+#define LP_SYSTEM_REG_LDO_FLASH_DISCHARGE_V  0x00000001U
+#define LP_SYSTEM_REG_LDO_FLASH_DISCHARGE_S  0
+/** LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to discharge lp puf mem.
+ */
+#define LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN    (BIT(1))
+#define LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN_M  (LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN_V << LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN_S)
+#define LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN_S  1
+/** LP_SYSTEM_REG_LP_PUF_MEM_XPD : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to discharge lp puf mem.
+ */
+#define LP_SYSTEM_REG_LP_PUF_MEM_XPD    (BIT(2))
+#define LP_SYSTEM_REG_LP_PUF_MEM_XPD_M  (LP_SYSTEM_REG_LP_PUF_MEM_XPD_V << LP_SYSTEM_REG_LP_PUF_MEM_XPD_S)
+#define LP_SYSTEM_REG_LP_PUF_MEM_XPD_V  0x00000001U
+#define LP_SYSTEM_REG_LP_PUF_MEM_XPD_S  2
+/** LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to discharge lp puf mem.
+ */
+#define LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE    (BIT(3))
+#define LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE_M  (LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE_V << LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE_S)
+#define LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE_V  0x00000001U
+#define LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE_S  3
+
+/** LP_SYSTEM_REG_HP_USB_OTGHS_PHY_CTRL_REG register
+ *  Usb otg2.0 PHY control register
+ */
+#define LP_SYSTEM_REG_HP_USB_OTGHS_PHY_CTRL_REG (DR_REG_LP_SYS_BASE + 0x204)
+/** LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to pull up USB OTG2.0 PHY id
+ */
+#define LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP    (BIT(0))
+#define LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP_M  (LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP_V << LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP_S)
+#define LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP_V  0x00000001U
+#define LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP_S  0
+/** LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to pull down USB OTG2.0 PHY dp
+ */
+#define LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN    (BIT(1))
+#define LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN_M  (LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN_V << LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN_S)
+#define LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN_V  0x00000001U
+#define LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN_S  1
+/** LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to pull down USB OTG2.0 PHY dm
+ */
+#define LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN    (BIT(2))
+#define LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN_M  (LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN_V << LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN_S)
+#define LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN_V  0x00000001U
+#define LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN_S  2
+/** LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to charge USB OTG2.0 PHY vbus
+ */
+#define LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS    (BIT(3))
+#define LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS_M  (LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS_V << LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS_S)
+#define LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS_V  0x00000001U
+#define LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS_S  3
+/** LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to discharge USB OTG2.0 PHY vbus
+ */
+#define LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS    (BIT(4))
+#define LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS_M  (LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS_V << LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS_S)
+#define LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS_V  0x00000001U
+#define LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS_S  4
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_system_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_system_struct.h
new file mode 100644
index 0000000000..1b63f5af86
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_system_struct.h
@@ -0,0 +1,1418 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of lp_sys_ver_date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ver_date : R/W; bitpos: [31:0]; default: 539296276;
+         *  need_des
+         */
+        uint32_t ver_date:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_sys_ver_date_reg_t;
+
+/** Type of clk_sel_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** ena_sw_sel_sys_clk : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t ena_sw_sel_sys_clk:1;
+        /** sw_sys_clk_src_sel : R/W; bitpos: [17]; default: 0;
+         *  reserved
+         */
+        uint32_t sw_sys_clk_src_sel:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} lp_system_reg_clk_sel_ctrl_reg_t;
+
+/** Type of sys_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_core_disable : R/W; bitpos: [0]; default: 0;
+         *  lp cpu disable
+         */
+        uint32_t lp_core_disable:1;
+        /** sys_sw_rst : WT; bitpos: [1]; default: 0;
+         *  digital system software reset bit
+         */
+        uint32_t sys_sw_rst:1;
+        /** force_download_boot : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t force_download_boot:1;
+        /** dig_fib : R/W; bitpos: [10:3]; default: 255;
+         *  need_des
+         */
+        uint32_t dig_fib:8;
+        /** io_mux_reset_disable : R/W; bitpos: [11]; default: 0;
+         *  reset disable bit for LP IOMUX
+         */
+        uint32_t io_mux_reset_disable:1;
+        uint32_t reserved_12:2;
+        /** ana_fib : RO; bitpos: [20:14]; default: 127;
+         *  need_des
+         */
+        uint32_t ana_fib:7;
+        /** lp_fib_sel : R/W; bitpos: [28:21]; default: 255;
+         *  need_des
+         */
+        uint32_t lp_fib_sel:8;
+        /** lp_core_etm_wakeup_flag_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_core_etm_wakeup_flag_clr:1;
+        /** lp_core_etm_wakeup_flag : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_core_etm_wakeup_flag:1;
+        /** systimer_stall_sel : R/W; bitpos: [31]; default: 0;
+         *  0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from
+         *  hp_core1
+         */
+        uint32_t systimer_stall_sel:1;
+    };
+    uint32_t val;
+} lp_system_reg_sys_ctrl_reg_t;
+
+/** Type of lp_clk_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:13;
+        /** lp_fosc_hp_cken : R/W; bitpos: [14]; default: 1;
+         *  reserved
+         */
+        uint32_t lp_fosc_hp_cken:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} lp_system_reg_lp_clk_ctrl_reg_t;
+
+/** Type of lp_rst_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ana_rst_bypass : R/W; bitpos: [0]; default: 1;
+         *  analog source reset bypass : wdt,brown out,super wdt,glitch
+         */
+        uint32_t ana_rst_bypass:1;
+        /** sys_rst_bypass : R/W; bitpos: [1]; default: 1;
+         *  system source reset bypass : software reset,hp wdt,lp wdt,efuse
+         */
+        uint32_t sys_rst_bypass:1;
+        /** efuse_force_norst : R/W; bitpos: [2]; default: 0;
+         *  efuse force no reset control
+         */
+        uint32_t efuse_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} lp_system_reg_lp_rst_ctrl_reg_t;
+
+/** Type of lp_core_boot_addr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_boot_addr : R/W; bitpos: [31:0]; default: 1343225856;
+         *  need_des
+         */
+        uint32_t lp_cpu_boot_addr:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_core_boot_addr_reg_t;
+
+/** Type of ext_wakeup1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ext_wakeup1_sel : R/W; bitpos: [15:0]; default: 0;
+         *  Bitmap to select RTC pads for ext wakeup1
+         */
+        uint32_t ext_wakeup1_sel:16;
+        /** ext_wakeup1_status_clr : WT; bitpos: [16]; default: 0;
+         *  clear ext wakeup1 status
+         */
+        uint32_t ext_wakeup1_status_clr:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_system_reg_ext_wakeup1_reg_t;
+
+/** Type of ext_wakeup1_status register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ext_wakeup1_status : RO; bitpos: [15:0]; default: 0;
+         *  ext wakeup1 status
+         */
+        uint32_t ext_wakeup1_status:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_system_reg_ext_wakeup1_status_reg_t;
+
+/** Type of lp_tcm_pwr_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** lp_tcm_rom_clk_force_on : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_rom_clk_force_on:1;
+        uint32_t reserved_6:1;
+        /** lp_tcm_ram_clk_force_on : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_ram_clk_force_on:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_pwr_ctrl_reg_t;
+
+/** Type of boot_addr_hp_lp_reg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** boot_addr_hp_lp : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t boot_addr_hp_lp:32;
+    };
+    uint32_t val;
+} lp_system_reg_boot_addr_hp_lp_reg_reg_t;
+
+/** Type of lp_store0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch0 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch0:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store0_reg_t;
+
+/** Type of lp_store1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch1 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch1:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store1_reg_t;
+
+/** Type of lp_store2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch2 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch2:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store2_reg_t;
+
+/** Type of lp_store3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch3 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch3:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store3_reg_t;
+
+/** Type of lp_store4 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch4 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch4:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store4_reg_t;
+
+/** Type of lp_store5 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch5 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch5:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store5_reg_t;
+
+/** Type of lp_store6 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch6 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch6:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store6_reg_t;
+
+/** Type of lp_store7 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch7 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch7:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store7_reg_t;
+
+/** Type of lp_store8 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch8 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch8:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store8_reg_t;
+
+/** Type of lp_store9 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch9 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch9:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store9_reg_t;
+
+/** Type of lp_store10 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch10 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch10:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store10_reg_t;
+
+/** Type of lp_store11 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch11 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch11:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store11_reg_t;
+
+/** Type of lp_store12 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch12 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch12:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store12_reg_t;
+
+/** Type of lp_store13 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch13 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch13:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store13_reg_t;
+
+/** Type of lp_store14 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch14 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch14:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store14_reg_t;
+
+/** Type of lp_store15 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_scratch15 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_scratch15:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_store15_reg_t;
+
+/** Type of lp_probea_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_a_mod_sel:16;
+        /** probe_a_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_a_top_sel:8;
+        /** probe_l_sel : R/W; bitpos: [25:24]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_l_sel:2;
+        /** probe_h_sel : R/W; bitpos: [27:26]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_h_sel:2;
+        /** probe_global_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_global_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} lp_system_reg_lp_probea_ctrl_reg_t;
+
+/** Type of lp_probeb_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_b_mod_sel:16;
+        /** probe_b_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_b_top_sel:8;
+        /** probe_b_en : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_b_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} lp_system_reg_lp_probeb_ctrl_reg_t;
+
+/** Type of lp_probe_out register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** probe_top_out : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t probe_top_out:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_probe_out_reg_t;
+
+/** Type of f2s_apb_brg_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** f2s_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t f2s_apb_postw_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_system_reg_f2s_apb_brg_cntl_reg_t;
+
+/** Type of usb_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sw_hw_usb_phy_sel : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t sw_hw_usb_phy_sel:1;
+        /** sw_usb_phy_sel : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t sw_usb_phy_sel:1;
+        /** usbotg20_wakeup_clr : WT; bitpos: [2]; default: 0;
+         *  clear usb wakeup to PMU.
+         */
+        uint32_t usbotg20_wakeup_clr:1;
+        /** usbotg20_in_suspend : R/W; bitpos: [3]; default: 0;
+         *  indicate usb otg2.0 is in suspend state.
+         */
+        uint32_t usbotg20_in_suspend:1;
+        /** usbotg20_ls_mode : R/W; bitpos: [4]; default: 0;
+         *  indicate current mode of usb otg2.0.
+         */
+        uint32_t usbotg20_ls_mode:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lp_system_reg_usb_ctrl_reg_t;
+
+/** Type of ana_xpd_pad_group register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ana_reg_xpd_pad_group : R/W; bitpos: [7:0]; default: 255;
+         *  Set 1 to power up pad group
+         */
+        uint32_t ana_reg_xpd_pad_group:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_system_reg_ana_xpd_pad_group_reg_t;
+
+/** Type of lp_tcm_ram_rdn_eco_cs register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_ram_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_ram_rdn_eco_en:1;
+        /** lp_tcm_ram_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_ram_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t;
+
+/** Type of lp_tcm_ram_rdn_eco_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_ram_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_ram_rdn_eco_low:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t;
+
+/** Type of lp_tcm_ram_rdn_eco_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_ram_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t lp_tcm_ram_rdn_eco_high:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t;
+
+/** Type of lp_tcm_rom_rdn_eco_cs register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_rom_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_rom_rdn_eco_en:1;
+        /** lp_tcm_rom_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_rom_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t;
+
+/** Type of lp_tcm_rom_rdn_eco_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_rom_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tcm_rom_rdn_eco_low:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t;
+
+/** Type of lp_tcm_rom_rdn_eco_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_tcm_rom_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t lp_tcm_rom_rdn_eco_high:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t;
+
+/** Type of hp_root_clk_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** cpu_clk_en : R/W; bitpos: [0]; default: 1;
+         *  clock gate enable for hp cpu root 400M clk
+         */
+        uint32_t cpu_clk_en:1;
+        /** sys_clk_en : R/W; bitpos: [1]; default: 1;
+         *  clock gate enable for hp sys root 480M clk
+         */
+        uint32_t sys_clk_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_system_reg_hp_root_clk_ctrl_reg_t;
+
+/** Type of lp_pmu_rdn_eco_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pmu_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_rdn_eco_low:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_pmu_rdn_eco_low_reg_t;
+
+/** Type of lp_pmu_rdn_eco_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pmu_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t pmu_rdn_eco_high:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_pmu_rdn_eco_high_reg_t;
+
+/** Type of pad_comp0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dref_comp0 : R/W; bitpos: [2:0]; default: 0;
+         *  pad comp dref
+         */
+        uint32_t dref_comp:3;
+        /** mode_comp0 : R/W; bitpos: [3]; default: 0;
+         *  pad comp mode
+         */
+        uint32_t mode_comp:1;
+        /** xpd_comp0 : R/W; bitpos: [4]; default: 0;
+         *  pad comp xpd
+         */
+        uint32_t xpd_comp:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lp_system_reg_pad_comp_reg_t;
+
+/** Type of backup_dma_cfg0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** burst_limit_aon : R/W; bitpos: [4:0]; default: 10;
+         *  need_des
+         */
+        uint32_t burst_limit_aon:5;
+        /** read_interval_aon : R/W; bitpos: [11:5]; default: 10;
+         *  need_des
+         */
+        uint32_t read_interval_aon:7;
+        /** link_backup_tout_thres_aon : R/W; bitpos: [21:12]; default: 100;
+         *  need_des
+         */
+        uint32_t link_backup_tout_thres_aon:10;
+        /** link_tout_thres_aon : R/W; bitpos: [31:22]; default: 100;
+         *  need_des
+         */
+        uint32_t link_tout_thres_aon:10;
+    };
+    uint32_t val;
+} lp_system_reg_backup_dma_cfg0_reg_t;
+
+/** Type of backup_dma_cfg1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** aon_bypass : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t aon_bypass:1;
+    };
+    uint32_t val;
+} lp_system_reg_backup_dma_cfg1_reg_t;
+
+/** Type of backup_dma_cfg2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** link_addr_aon : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t link_addr_aon:32;
+    };
+    uint32_t val;
+} lp_system_reg_backup_dma_cfg2_reg_t;
+
+/** Type of boot_addr_hp_core1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** boot_addr_hp_core1 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t boot_addr_hp_core1:32;
+    };
+    uint32_t val;
+} lp_system_reg_boot_addr_hp_core1_reg_t;
+
+/** Type of hp_mem_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  need_des
+         */
+        uint32_t hp_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} lp_system_reg_hp_mem_aux_ctrl_reg_t;
+
+/** Type of lp_mem_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  need_des
+         */
+        uint32_t lp_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_mem_aux_ctrl_reg_t;
+
+/** Type of hp_rom_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_rom_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
+         *  need_des
+         */
+        uint32_t hp_rom_aux_ctrl:32;
+    };
+    uint32_t val;
+} lp_system_reg_hp_rom_aux_ctrl_reg_t;
+
+/** Type of lp_rom_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_rom_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
+         *  need_des
+         */
+        uint32_t lp_rom_aux_ctrl:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_rom_aux_ctrl_reg_t;
+
+/** Type of hp_por_rst_bypass_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** hp_po_cnnt_rstn_bypass_ctrl : R/W; bitpos: [15:8]; default: 255;
+         *  [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn
+         *  [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn
+         *  [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn
+         *  [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn
+         *  [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst
+         *  [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst
+         *  [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn
+         *  [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn
+         */
+        uint32_t hp_po_cnnt_rstn_bypass_ctrl:8;
+        uint32_t reserved_16:8;
+        /** hp_po_rstn_bypass_ctrl : R/W; bitpos: [31:24]; default: 255;
+         *  [31] 1'b1: po_rstn bypass sys_sw_rstn
+         *  [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn
+         *  [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn
+         *  [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn
+         *  [27] 1'b1: po_rstn bypass usb_jtag_chip_rst
+         *  [26] 1'b1: po_rstn bypass usb_uart_chip_rst
+         *  [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn
+         *  [24] 1'b1: po_rstn bypass efuse_err_rstn
+         */
+        uint32_t hp_po_rstn_bypass_ctrl:8;
+    };
+    uint32_t val;
+} lp_system_reg_hp_por_rst_bypass_ctrl_reg_t;
+
+/** Type of lp_core_ahb_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_core_ahb_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable lp core ahb timeout handle
+         */
+        uint32_t lp_core_ahb_timeout_en:1;
+        /** lp_core_ahb_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set lp core ahb bus timeout  threshold
+         */
+        uint32_t lp_core_ahb_timeout_thres:16;
+        /** lp2hp_ahb_timeout_en : R/W; bitpos: [17]; default: 1;
+         *  set this field to 1 to enable lp2hp ahb timeout handle
+         */
+        uint32_t lp2hp_ahb_timeout_en:1;
+        /** lp2hp_ahb_timeout_thres : R/W; bitpos: [22:18]; default: 31;
+         *  This field used to set lp2hp ahb bus timeout  threshold
+         */
+        uint32_t lp2hp_ahb_timeout_thres:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} lp_system_reg_lp_core_ahb_timeout_reg_t;
+
+/** Type of lp_core_ibus_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_core_ibus_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable lp core ibus timeout handle
+         */
+        uint32_t lp_core_ibus_timeout_en:1;
+        /** lp_core_ibus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set lp core ibus timeout  threshold
+         */
+        uint32_t lp_core_ibus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_system_reg_lp_core_ibus_timeout_reg_t;
+
+/** Type of lp_core_dbus_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_core_dbus_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable lp core dbus timeout handle
+         */
+        uint32_t lp_core_dbus_timeout_en:1;
+        /** lp_core_dbus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set lp core dbus timeout  threshold
+         */
+        uint32_t lp_core_dbus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_system_reg_lp_core_dbus_timeout_reg_t;
+
+
+/** Group: status_register */
+/** Type of lp_addrhole_addr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_addr : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_addrhole_addr:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_addrhole_addr_reg_t;
+
+/** Type of lp_addrhole_info register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_id : RO; bitpos: [4:0]; default: 0;
+         *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
+         *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
+         *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
+         */
+        uint32_t lp_addrhole_id:5;
+        /** lp_addrhole_wr : RO; bitpos: [5]; default: 0;
+         *  1:write trans, 0: read trans.
+         */
+        uint32_t lp_addrhole_wr:1;
+        /** lp_addrhole_secure : RO; bitpos: [6]; default: 0;
+         *  1: illegal address access, 0: access without permission
+         */
+        uint32_t lp_addrhole_secure:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_lp_addrhole_info_reg_t;
+
+/** Type of lp_cpu_dbg_pc register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_dbg_pc : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_dbg_pc:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_cpu_dbg_pc_reg_t;
+
+/** Type of lp_cpu_exc_pc register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_exc_pc : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_exc_pc:32;
+    };
+    uint32_t val;
+} lp_system_reg_lp_cpu_exc_pc_reg_t;
+
+/** Type of idbus_addrhole_addr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** idbus_addrhole_addr : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t idbus_addrhole_addr:32;
+    };
+    uint32_t val;
+} lp_system_reg_idbus_addrhole_addr_reg_t;
+
+/** Type of idbus_addrhole_info register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** idbus_addrhole_id : RO; bitpos: [4:0]; default: 0;
+         *  need_des
+         */
+        uint32_t idbus_addrhole_id:5;
+        /** idbus_addrhole_wr : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t idbus_addrhole_wr:1;
+        /** idbus_addrhole_secure : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t idbus_addrhole_secure:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_idbus_addrhole_info_reg_t;
+
+/** Type of rng_data register
+ *  rng data register
+ */
+typedef union {
+    struct {
+        /** rnd_data : RO; bitpos: [31:0]; default: 0;
+         *  result of rng output
+         */
+        uint32_t rnd_data:32;
+    };
+    uint32_t val;
+} lp_system_reg_rng_data_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  raw interrupt register
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  the raw interrupt status of lp addrhole(for lp peri  and lp ram tee apm, and lp
+         *  matrix default slave)
+         */
+        uint32_t lp_addrhole_int_raw:1;
+        /** idbus_addrhole_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
+         */
+        uint32_t idbus_addrhole_int_raw:1;
+        /** lp_core_ahb_timeout_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  the raw interrupt status of lp core ahb bus timeout
+         */
+        uint32_t lp_core_ahb_timeout_int_raw:1;
+        /** lp_core_ibus_timeout_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  the raw interrupt status of lp core  ibus timeout
+         */
+        uint32_t lp_core_ibus_timeout_int_raw:1;
+        /** lp_core_dbus_timeout_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  the raw interrupt status of lp core  dbus timeout
+         */
+        uint32_t lp_core_dbus_timeout_int_raw:1;
+        /** etm_task_ulp_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  the raw interrupt status of etm task ulp
+         */
+        uint32_t etm_task_ulp_int_raw:1;
+        /** slow_clk_tick_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  the raw interrupt status of slow_clk_tick
+         */
+        uint32_t slow_clk_tick_int_raw:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_int_raw_reg_t;
+
+/** Type of int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of lp addrhole (for lp peri  and lp ram tee apm, and lp
+         *  matrix default slave)
+         */
+        uint32_t lp_addrhole_int_st:1;
+        /** idbus_addrhole_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
+         */
+        uint32_t idbus_addrhole_int_st:1;
+        /** lp_core_ahb_timeout_int_st : RO; bitpos: [2]; default: 0;
+         *  the masked interrupt status of lp core ahb bus timeout
+         */
+        uint32_t lp_core_ahb_timeout_int_st:1;
+        /** lp_core_ibus_timeout_int_st : RO; bitpos: [3]; default: 0;
+         *  the masked interrupt status of lp core  ibus timeout
+         */
+        uint32_t lp_core_ibus_timeout_int_st:1;
+        /** lp_core_dbus_timeout_int_st : RO; bitpos: [4]; default: 0;
+         *  the masked interrupt status of lp core  dbus timeout
+         */
+        uint32_t lp_core_dbus_timeout_int_st:1;
+        /** etm_task_ulp_int_st : RO; bitpos: [5]; default: 0;
+         *  the masked interrupt status of etm task ulp
+         */
+        uint32_t etm_task_ulp_int_st:1;
+        /** slow_clk_tick_int_st : RO; bitpos: [6]; default: 0;
+         *  the masked interrupt status of slow_clk_tick
+         */
+        uint32_t slow_clk_tick_int_st:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_int_st_reg_t;
+
+/** Type of int_ena register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable lp addrhole int
+         */
+        uint32_t lp_addrhole_int_ena:1;
+        /** idbus_addrhole_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable idbus addrhole int
+         */
+        uint32_t idbus_addrhole_int_ena:1;
+        /** lp_core_ahb_timeout_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable lp_core_ahb_timeout int
+         */
+        uint32_t lp_core_ahb_timeout_int_ena:1;
+        /** lp_core_ibus_timeout_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable lp_core_ibus_timeout int
+         */
+        uint32_t lp_core_ibus_timeout_int_ena:1;
+        /** lp_core_dbus_timeout_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable lp_core_dbus_timeout int
+         */
+        uint32_t lp_core_dbus_timeout_int_ena:1;
+        /** etm_task_ulp_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable etm task ulp int
+         */
+        uint32_t etm_task_ulp_int_ena:1;
+        /** slow_clk_tick_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable slow_clk_tick int
+         */
+        uint32_t slow_clk_tick_int_ena:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** lp_addrhole_int_clr : WT; bitpos: [0]; default: 0;
+         *  write 1 to clear lp addrhole int
+         */
+        uint32_t lp_addrhole_int_clr:1;
+        /** idbus_addrhole_int_clr : WT; bitpos: [1]; default: 0;
+         *  write 1 to clear idbus addrhole int
+         */
+        uint32_t idbus_addrhole_int_clr:1;
+        /** lp_core_ahb_timeout_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear lp_core_ahb_timeout int
+         */
+        uint32_t lp_core_ahb_timeout_int_clr:1;
+        /** lp_core_ibus_timeout_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear lp_core_ibus_timeout int
+         */
+        uint32_t lp_core_ibus_timeout_int_clr:1;
+        /** lp_core_dbus_timeout_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear lp_core_dbus_timeout int
+         */
+        uint32_t lp_core_dbus_timeout_int_clr:1;
+        /** etm_task_ulp_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear etm tasl ulp int
+         */
+        uint32_t etm_task_ulp_int_clr:1;
+        /** slow_clk_tick_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear slow_clk_tick int
+         */
+        uint32_t slow_clk_tick_int_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} lp_system_reg_int_clr_reg_t;
+
+
+/** Group: control registers */
+/** Type of lp_core_err_resp_dis register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_core_err_resp_dis : R/W; bitpos: [2:0]; default: 0;
+         *  Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to
+         *  disable ahb err resp.
+         */
+        uint32_t lp_core_err_resp_dis:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} lp_system_reg_lp_core_err_resp_dis_reg_t;
+
+/** Type of rng_cfg register
+ *  rng cfg register
+ */
+typedef union {
+    struct {
+        /** rng_timer_en : R/W; bitpos: [0]; default: 1;
+         *  enable rng timer
+         */
+        uint32_t rng_timer_en:1;
+        /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 1;
+         *  configure ng timer pscale
+         */
+        uint32_t rng_timer_pscale:8;
+        /** rng_sar_enable : R/W; bitpos: [9]; default: 0;
+         *  enable rng_saradc
+         */
+        uint32_t rng_sar_enable:1;
+        uint32_t reserved_10:6;
+        /** rng_sar_data : RO; bitpos: [28:16]; default: 0;
+         *  debug rng sar sample cnt
+         */
+        uint32_t rng_sar_data:13;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} lp_system_reg_rng_cfg_reg_t;
+
+/** Type of pad_rtc_hold_ctrl0 register
+ *  enable pad hold ctrl
+ */
+typedef union {
+    struct {
+        /** pad_rtc_hold_ctrl0 : R/W; bitpos: [31:0]; default: 0;
+         *  Set 1 to hold pad 0-31 status
+         */
+        uint32_t pad_rtc_hold_ctrl0:32;
+    };
+    uint32_t val;
+} lp_system_reg_pad_rtc_hold_ctrl0_reg_t;
+
+/** Type of pad_rtc_hold_ctrl1 register
+ *  enable pad hold ctrl
+ */
+typedef union {
+    struct {
+        /** pad_rtc_hold_ctrl1 : R/W; bitpos: [24:0]; default: 0;
+         *  Set 1 to hold pad 32-56 status
+         */
+        uint32_t pad_rtc_hold_ctrl1:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} lp_system_reg_pad_rtc_hold_ctrl1_reg_t;
+
+/** Type of ded_pad_rtc_hold_ctrl register
+ *  enable pad hold ctrl
+ */
+typedef union {
+    struct {
+        /** ded_pad_rtc_hold_ctrl : R/W; bitpos: [25:0]; default: 0;
+         *  Set bit0-5 to hold flash pad status. Set bit6-25 to hold psram pad status.
+         */
+        uint32_t ded_pad_rtc_hold_ctrl:26;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} lp_system_reg_ded_pad_rtc_hold_ctrl_reg_t;
+
+/** Type of discharge register
+ *  pufmem / ldo flash power discharge control
+ */
+typedef union {
+    struct {
+        /** ldo_flash_discharge : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to discharge ldo flash.
+         */
+        uint32_t ldo_flash_discharge:1;
+        /** lp_puf_mem_iso_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to discharge lp puf mem.
+         */
+        uint32_t lp_puf_mem_iso_en:1;
+        /** lp_puf_mem_xpd : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to discharge lp puf mem.
+         */
+        uint32_t lp_puf_mem_xpd:1;
+        /** lp_puf_mem_discharge : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to discharge lp puf mem.
+         */
+        uint32_t lp_puf_mem_discharge:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lp_system_reg_discharge_reg_t;
+
+/** Type of hp_usb_otghs_phy_ctrl register
+ *  Usb otg2.0 PHY control register
+ */
+typedef union {
+    struct {
+        /** hp_utmiotg_idpullup : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to pull up USB OTG2.0 PHY id
+         */
+        uint32_t hp_utmiotg_idpullup:1;
+        /** hp_utmiotg_dppulldown : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to pull down USB OTG2.0 PHY dp
+         */
+        uint32_t hp_utmiotg_dppulldown:1;
+        /** hp_utmiotg_dmpulldown : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to pull down USB OTG2.0 PHY dm
+         */
+        uint32_t hp_utmiotg_dmpulldown:1;
+        /** hp_utmisrp_chrgvbus : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to charge USB OTG2.0 PHY vbus
+         */
+        uint32_t hp_utmisrp_chrgvbus:1;
+        /** hp_utmisrp_dischrgvbus : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to discharge USB OTG2.0 PHY vbus
+         */
+        uint32_t hp_utmisrp_dischrgvbus:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lp_system_reg_hp_usb_otghs_phy_ctrl_reg_t;
+
+
+typedef struct {
+    volatile lp_system_reg_lp_sys_ver_date_reg_t lp_sys_ver_date;
+    volatile lp_system_reg_clk_sel_ctrl_reg_t clk_sel_ctrl;
+    volatile lp_system_reg_sys_ctrl_reg_t sys_ctrl;
+    volatile lp_system_reg_lp_clk_ctrl_reg_t lp_clk_ctrl;
+    volatile lp_system_reg_lp_rst_ctrl_reg_t lp_rst_ctrl;
+    uint32_t reserved_014;
+    volatile lp_system_reg_lp_core_boot_addr_reg_t lp_core_boot_addr;
+    volatile lp_system_reg_ext_wakeup1_reg_t ext_wakeup1;
+    volatile lp_system_reg_ext_wakeup1_status_reg_t ext_wakeup1_status;
+    volatile lp_system_reg_lp_tcm_pwr_ctrl_reg_t lp_tcm_pwr_ctrl;
+    volatile lp_system_reg_boot_addr_hp_lp_reg_reg_t boot_addr_hp_lp_reg;
+    volatile lp_system_reg_lp_store0_reg_t lp_store0;
+    volatile lp_system_reg_lp_store1_reg_t lp_store1;
+    volatile lp_system_reg_lp_store2_reg_t lp_store2;
+    volatile lp_system_reg_lp_store3_reg_t lp_store3;
+    volatile lp_system_reg_lp_store4_reg_t lp_store4;
+    volatile lp_system_reg_lp_store5_reg_t lp_store5;
+    volatile lp_system_reg_lp_store6_reg_t lp_store6;
+    volatile lp_system_reg_lp_store7_reg_t lp_store7;
+    volatile lp_system_reg_lp_store8_reg_t lp_store8;
+    volatile lp_system_reg_lp_store9_reg_t lp_store9;
+    volatile lp_system_reg_lp_store10_reg_t lp_store10;
+    volatile lp_system_reg_lp_store11_reg_t lp_store11;
+    volatile lp_system_reg_lp_store12_reg_t lp_store12;
+    volatile lp_system_reg_lp_store13_reg_t lp_store13;
+    volatile lp_system_reg_lp_store14_reg_t lp_store14;
+    volatile lp_system_reg_lp_store15_reg_t lp_store15;
+    volatile lp_system_reg_lp_probea_ctrl_reg_t lp_probea_ctrl;
+    volatile lp_system_reg_lp_probeb_ctrl_reg_t lp_probeb_ctrl;
+    volatile lp_system_reg_lp_probe_out_reg_t lp_probe_out;
+    uint32_t reserved_078[9];
+    volatile lp_system_reg_f2s_apb_brg_cntl_reg_t f2s_apb_brg_cntl;
+    uint32_t reserved_0a0[24];
+    volatile lp_system_reg_usb_ctrl_reg_t usb_ctrl;
+    uint32_t reserved_104[2];
+    volatile lp_system_reg_ana_xpd_pad_group_reg_t ana_xpd_pad_group;
+    volatile lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t lp_tcm_ram_rdn_eco_cs;
+    volatile lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t lp_tcm_ram_rdn_eco_low;
+    volatile lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t lp_tcm_ram_rdn_eco_high;
+    volatile lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t lp_tcm_rom_rdn_eco_cs;
+    volatile lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t lp_tcm_rom_rdn_eco_low;
+    volatile lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t lp_tcm_rom_rdn_eco_high;
+    uint32_t reserved_128[2];
+    volatile lp_system_reg_hp_root_clk_ctrl_reg_t hp_root_clk_ctrl;
+    uint32_t reserved_134;
+    volatile lp_system_reg_lp_pmu_rdn_eco_low_reg_t lp_pmu_rdn_eco_low;
+    volatile lp_system_reg_lp_pmu_rdn_eco_high_reg_t lp_pmu_rdn_eco_high;
+    uint32_t reserved_140[2];
+    volatile lp_system_reg_pad_comp_reg_t pad_comp[2];
+    uint32_t reserved_150;
+    volatile lp_system_reg_backup_dma_cfg0_reg_t backup_dma_cfg0;
+    volatile lp_system_reg_backup_dma_cfg1_reg_t backup_dma_cfg1;
+    volatile lp_system_reg_backup_dma_cfg2_reg_t backup_dma_cfg2;
+    uint32_t reserved_160;
+    volatile lp_system_reg_boot_addr_hp_core1_reg_t boot_addr_hp_core1;
+    volatile lp_system_reg_lp_addrhole_addr_reg_t lp_addrhole_addr;
+    volatile lp_system_reg_lp_addrhole_info_reg_t lp_addrhole_info;
+    volatile lp_system_reg_int_raw_reg_t int_raw;
+    volatile lp_system_reg_int_st_reg_t int_st;
+    volatile lp_system_reg_int_ena_reg_t int_ena;
+    volatile lp_system_reg_int_clr_reg_t int_clr;
+    volatile lp_system_reg_hp_mem_aux_ctrl_reg_t hp_mem_aux_ctrl;
+    volatile lp_system_reg_lp_mem_aux_ctrl_reg_t lp_mem_aux_ctrl;
+    volatile lp_system_reg_hp_rom_aux_ctrl_reg_t hp_rom_aux_ctrl;
+    volatile lp_system_reg_lp_rom_aux_ctrl_reg_t lp_rom_aux_ctrl;
+    volatile lp_system_reg_lp_cpu_dbg_pc_reg_t lp_cpu_dbg_pc;
+    volatile lp_system_reg_lp_cpu_exc_pc_reg_t lp_cpu_exc_pc;
+    volatile lp_system_reg_idbus_addrhole_addr_reg_t idbus_addrhole_addr;
+    volatile lp_system_reg_idbus_addrhole_info_reg_t idbus_addrhole_info;
+    volatile lp_system_reg_hp_por_rst_bypass_ctrl_reg_t hp_por_rst_bypass_ctrl;
+    volatile lp_system_reg_rng_data_reg_t rng_data;
+    uint32_t reserved_1a8[2];
+    volatile lp_system_reg_lp_core_ahb_timeout_reg_t lp_core_ahb_timeout;
+    volatile lp_system_reg_lp_core_ibus_timeout_reg_t lp_core_ibus_timeout;
+    volatile lp_system_reg_lp_core_dbus_timeout_reg_t lp_core_dbus_timeout;
+    volatile lp_system_reg_lp_core_err_resp_dis_reg_t lp_core_err_resp_dis;
+    volatile lp_system_reg_rng_cfg_reg_t rng_cfg;
+    volatile lp_system_reg_pad_rtc_hold_ctrl0_reg_t pad_rtc_hold_ctrl0;
+    volatile lp_system_reg_pad_rtc_hold_ctrl1_reg_t pad_rtc_hold_ctrl1;
+    volatile lp_system_reg_ded_pad_rtc_hold_ctrl_reg_t ded_pad_rtc_hold_ctrl;
+    uint32_t reserved_1d0[12];
+    volatile lp_system_reg_discharge_reg_t discharge;
+    volatile lp_system_reg_hp_usb_otghs_phy_ctrl_reg_t hp_usb_otghs_phy_ctrl;
+} lp_system_reg_dev_t;
+
+extern lp_system_reg_dev_t LP_SYS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_system_reg_dev_t) == 0x208, "Invalid size of lp_system_reg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_eco5_struct.h
new file mode 100644
index 0000000000..ad41a52b3f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_eco5_struct.h
@@ -0,0 +1,363 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of tar0_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_low0:32;
+    };
+    uint32_t val;
+} lp_timer_tar0_low_reg_t;
+
+/** Type of tar0_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_high0:16;
+        uint32_t reserved_16:15;
+        /** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_en0:1;
+    };
+    uint32_t val;
+} lp_timer_tar0_high_reg_t;
+
+/** Type of tar1_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_low1:32;
+    };
+    uint32_t val;
+} lp_timer_tar1_low_reg_t;
+
+/** Type of tar1_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_high1:16;
+        uint32_t reserved_16:15;
+        /** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_en1:1;
+    };
+    uint32_t val;
+} lp_timer_tar1_high_reg_t;
+
+/** Type of update register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** main_timer_update : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_update:1;
+        /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_xtal_off:1;
+        /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_sys_stall:1;
+        /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_sys_rst:1;
+    };
+    uint32_t val;
+} lp_timer_update_reg_t;
+
+/** Type of main_buf0_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf0_low:32;
+    };
+    uint32_t val;
+} lp_timer_main_buf0_low_reg_t;
+
+/** Type of main_buf0_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf0_high:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_timer_main_buf0_high_reg_t;
+
+/** Type of main_buf1_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf1_low:32;
+    };
+    uint32_t val;
+} lp_timer_main_buf1_low_reg_t;
+
+/** Type of main_buf1_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf1_high:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_timer_main_buf1_high_reg_t;
+
+/** Type of main_overflow register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_alarm_load:1;
+    };
+    uint32_t val;
+} lp_timer_main_overflow_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_raw:1;
+        /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_raw:1;
+    };
+    uint32_t val;
+} lp_timer_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_st:1;
+        /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_st:1;
+    };
+    uint32_t val;
+} lp_timer_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_ena:1;
+        /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_ena:1;
+    };
+    uint32_t val;
+} lp_timer_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_clr:1;
+        /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_clr:1;
+    };
+    uint32_t val;
+} lp_timer_int_clr_reg_t;
+
+/** Type of lp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_raw:1;
+        /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_raw:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_raw_reg_t;
+
+/** Type of lp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_st:1;
+        /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_st:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_st_reg_t;
+
+/** Type of lp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_ena:1;
+        /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_ena:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_ena_reg_t;
+
+/** Type of lp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_clr:1;
+        /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_clr:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_clr_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [30:0]; default: 34672976;
+         *  need_des
+         */
+        uint32_t date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_timer_date_reg_t;
+
+
+typedef struct {
+    volatile lp_timer_tar0_low_reg_t tar0_low;
+    volatile lp_timer_tar0_high_reg_t tar0_high;
+    volatile lp_timer_tar1_low_reg_t tar1_low;
+    volatile lp_timer_tar1_high_reg_t tar1_high;
+    volatile lp_timer_update_reg_t update;
+    volatile lp_timer_main_buf0_low_reg_t main_buf0_low;
+    volatile lp_timer_main_buf0_high_reg_t main_buf0_high;
+    volatile lp_timer_main_buf1_low_reg_t main_buf1_low;
+    volatile lp_timer_main_buf1_high_reg_t main_buf1_high;
+    volatile lp_timer_main_overflow_reg_t main_overflow;
+    volatile lp_timer_int_raw_reg_t int_raw;
+    volatile lp_timer_int_st_reg_t int_st;
+    volatile lp_timer_int_ena_reg_t int_ena;
+    volatile lp_timer_int_clr_reg_t int_clr;
+    volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
+    volatile lp_timer_lp_int_st_reg_t lp_int_st;
+    volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
+    volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
+    uint32_t reserved_048[237];
+    volatile lp_timer_date_reg_t date;
+} lp_timer_dev_t;
+
+extern lp_timer_dev_t LP_TIMER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h
new file mode 100644
index 0000000000..683e3596ac
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h
@@ -0,0 +1,342 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RTC_TIMER_TAR0_LOW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_TAR0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x0)
+/** RTC_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW0    0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_M  (RTC_TIMER_MAIN_TIMER_TAR_LOW0_V << RTC_TIMER_MAIN_TIMER_TAR_LOW0_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_V  0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_S  0
+
+/** RTC_TIMER_TAR0_HIGH_REG register
+ *  need_des
+ */
+#define RTC_TIMER_TAR0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x4)
+/** RTC_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0    0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_M  (RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V  0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S  0
+/** RTC_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_EN0    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_TAR_EN0_M  (RTC_TIMER_MAIN_TIMER_TAR_EN0_V << RTC_TIMER_MAIN_TIMER_TAR_EN0_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_EN0_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_TAR_EN0_S  31
+
+/** RTC_TIMER_TAR1_LOW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_TAR1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x8)
+/** RTC_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW1    0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_M  (RTC_TIMER_MAIN_TIMER_TAR_LOW1_V << RTC_TIMER_MAIN_TIMER_TAR_LOW1_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_V  0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_S  0
+
+/** RTC_TIMER_TAR1_HIGH_REG register
+ *  need_des
+ */
+#define RTC_TIMER_TAR1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0xc)
+/** RTC_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1    0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_M  (RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V  0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S  0
+/** RTC_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_EN1    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_TAR_EN1_M  (RTC_TIMER_MAIN_TIMER_TAR_EN1_V << RTC_TIMER_MAIN_TIMER_TAR_EN1_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_EN1_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_TAR_EN1_S  31
+
+/** RTC_TIMER_UPDATE_REG register
+ *  need_des
+ */
+#define RTC_TIMER_UPDATE_REG (DR_REG_RTC_TIMER_BASE + 0x10)
+/** RTC_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_UPDATE    (BIT(28))
+#define RTC_TIMER_MAIN_TIMER_UPDATE_M  (RTC_TIMER_MAIN_TIMER_UPDATE_V << RTC_TIMER_MAIN_TIMER_UPDATE_S)
+#define RTC_TIMER_MAIN_TIMER_UPDATE_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_UPDATE_S  28
+/** RTC_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_XTAL_OFF    (BIT(29))
+#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_M  (RTC_TIMER_MAIN_TIMER_XTAL_OFF_V << RTC_TIMER_MAIN_TIMER_XTAL_OFF_S)
+#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_S  29
+/** RTC_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_SYS_STALL    (BIT(30))
+#define RTC_TIMER_MAIN_TIMER_SYS_STALL_M  (RTC_TIMER_MAIN_TIMER_SYS_STALL_V << RTC_TIMER_MAIN_TIMER_SYS_STALL_S)
+#define RTC_TIMER_MAIN_TIMER_SYS_STALL_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_SYS_STALL_S  30
+/** RTC_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_SYS_RST    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_SYS_RST_M  (RTC_TIMER_MAIN_TIMER_SYS_RST_V << RTC_TIMER_MAIN_TIMER_SYS_RST_S)
+#define RTC_TIMER_MAIN_TIMER_SYS_RST_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_SYS_RST_S  31
+
+/** RTC_TIMER_MAIN_BUF0_LOW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_BUF0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x14)
+/** RTC_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_BUF0_LOW    0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_M  (RTC_TIMER_MAIN_TIMER_BUF0_LOW_V << RTC_TIMER_MAIN_TIMER_BUF0_LOW_S)
+#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_V  0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_S  0
+
+/** RTC_TIMER_MAIN_BUF0_HIGH_REG register
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x18)
+/** RTC_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH    0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_M  (RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S)
+#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V  0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S  0
+
+/** RTC_TIMER_MAIN_BUF1_LOW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_BUF1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x1c)
+/** RTC_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_BUF1_LOW    0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_M  (RTC_TIMER_MAIN_TIMER_BUF1_LOW_V << RTC_TIMER_MAIN_TIMER_BUF1_LOW_S)
+#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_V  0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_S  0
+
+/** RTC_TIMER_MAIN_BUF1_HIGH_REG register
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x20)
+/** RTC_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH    0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_M  (RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S)
+#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V  0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S  0
+
+/** RTC_TIMER_MAIN_OVERFLOW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_OVERFLOW_REG (DR_REG_RTC_TIMER_BASE + 0x24)
+/** RTC_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_M  (RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V << RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S)
+#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S  31
+
+/** RTC_TIMER_INT_RAW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x28)
+/** RTC_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_OVERFLOW_RAW    (BIT(30))
+#define RTC_TIMER_OVERFLOW_RAW_M  (RTC_TIMER_OVERFLOW_RAW_V << RTC_TIMER_OVERFLOW_RAW_S)
+#define RTC_TIMER_OVERFLOW_RAW_V  0x00000001U
+#define RTC_TIMER_OVERFLOW_RAW_S  30
+/** RTC_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_SOC_WAKEUP_INT_RAW    (BIT(31))
+#define RTC_TIMER_SOC_WAKEUP_INT_RAW_M  (RTC_TIMER_SOC_WAKEUP_INT_RAW_V << RTC_TIMER_SOC_WAKEUP_INT_RAW_S)
+#define RTC_TIMER_SOC_WAKEUP_INT_RAW_V  0x00000001U
+#define RTC_TIMER_SOC_WAKEUP_INT_RAW_S  31
+
+/** RTC_TIMER_INT_ST_REG register
+ *  need_des
+ */
+#define RTC_TIMER_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x2c)
+/** RTC_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_OVERFLOW_ST    (BIT(30))
+#define RTC_TIMER_OVERFLOW_ST_M  (RTC_TIMER_OVERFLOW_ST_V << RTC_TIMER_OVERFLOW_ST_S)
+#define RTC_TIMER_OVERFLOW_ST_V  0x00000001U
+#define RTC_TIMER_OVERFLOW_ST_S  30
+/** RTC_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_SOC_WAKEUP_INT_ST    (BIT(31))
+#define RTC_TIMER_SOC_WAKEUP_INT_ST_M  (RTC_TIMER_SOC_WAKEUP_INT_ST_V << RTC_TIMER_SOC_WAKEUP_INT_ST_S)
+#define RTC_TIMER_SOC_WAKEUP_INT_ST_V  0x00000001U
+#define RTC_TIMER_SOC_WAKEUP_INT_ST_S  31
+
+/** RTC_TIMER_INT_ENA_REG register
+ *  need_des
+ */
+#define RTC_TIMER_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x30)
+/** RTC_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_OVERFLOW_ENA    (BIT(30))
+#define RTC_TIMER_OVERFLOW_ENA_M  (RTC_TIMER_OVERFLOW_ENA_V << RTC_TIMER_OVERFLOW_ENA_S)
+#define RTC_TIMER_OVERFLOW_ENA_V  0x00000001U
+#define RTC_TIMER_OVERFLOW_ENA_S  30
+/** RTC_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_SOC_WAKEUP_INT_ENA    (BIT(31))
+#define RTC_TIMER_SOC_WAKEUP_INT_ENA_M  (RTC_TIMER_SOC_WAKEUP_INT_ENA_V << RTC_TIMER_SOC_WAKEUP_INT_ENA_S)
+#define RTC_TIMER_SOC_WAKEUP_INT_ENA_V  0x00000001U
+#define RTC_TIMER_SOC_WAKEUP_INT_ENA_S  31
+
+/** RTC_TIMER_INT_CLR_REG register
+ *  need_des
+ */
+#define RTC_TIMER_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x34)
+/** RTC_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_OVERFLOW_CLR    (BIT(30))
+#define RTC_TIMER_OVERFLOW_CLR_M  (RTC_TIMER_OVERFLOW_CLR_V << RTC_TIMER_OVERFLOW_CLR_S)
+#define RTC_TIMER_OVERFLOW_CLR_V  0x00000001U
+#define RTC_TIMER_OVERFLOW_CLR_S  30
+/** RTC_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_SOC_WAKEUP_INT_CLR    (BIT(31))
+#define RTC_TIMER_SOC_WAKEUP_INT_CLR_M  (RTC_TIMER_SOC_WAKEUP_INT_CLR_V << RTC_TIMER_SOC_WAKEUP_INT_CLR_S)
+#define RTC_TIMER_SOC_WAKEUP_INT_CLR_V  0x00000001U
+#define RTC_TIMER_SOC_WAKEUP_INT_CLR_S  31
+
+/** RTC_TIMER_LP_INT_RAW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_LP_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x38)
+/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW    (BIT(30))
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S  30
+/** RTC_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_M  (RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S)
+#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S  31
+
+/** RTC_TIMER_LP_INT_ST_REG register
+ *  need_des
+ */
+#define RTC_TIMER_LP_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x3c)
+/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST    (BIT(30))
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S  30
+/** RTC_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ST    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_M  (RTC_TIMER_MAIN_TIMER_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_LP_INT_ST_S)
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_S  31
+
+/** RTC_TIMER_LP_INT_ENA_REG register
+ *  need_des
+ */
+#define RTC_TIMER_LP_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x40)
+/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA    (BIT(30))
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S  30
+/** RTC_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_M  (RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S)
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S  31
+
+/** RTC_TIMER_LP_INT_CLR_REG register
+ *  need_des
+ */
+#define RTC_TIMER_LP_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x44)
+/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR    (BIT(30))
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S  30
+/** RTC_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_M  (RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S)
+#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S  31
+
+/** RTC_TIMER_DATE_REG register
+ *  need_des
+ */
+#define RTC_TIMER_DATE_REG (DR_REG_RTC_TIMER_BASE + 0x3fc)
+/** RTC_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
+ *  need_des
+ */
+#define RTC_TIMER_DATE    0x7FFFFFFFU
+#define RTC_TIMER_DATE_M  (RTC_TIMER_DATE_V << RTC_TIMER_DATE_S)
+#define RTC_TIMER_DATE_V  0x7FFFFFFFU
+#define RTC_TIMER_DATE_S  0
+/** RTC_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_CLK_EN    (BIT(31))
+#define RTC_TIMER_CLK_EN_M  (RTC_TIMER_CLK_EN_V << RTC_TIMER_CLK_EN_S)
+#define RTC_TIMER_CLK_EN_V  0x00000001U
+#define RTC_TIMER_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_struct.h
new file mode 100644
index 0000000000..09dd169f13
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_struct.h
@@ -0,0 +1,274 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    union {
+        struct {
+            uint32_t target_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+    union {
+        struct {
+            uint32_t target_hi: 16;
+            uint32_t reserved0: 15;
+            uint32_t enable   : 1;
+        };
+        uint32_t val;
+    } hi;
+} lp_timer_target_reg_t;
+
+/** Type of update register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** main_timer_update : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_update:1;
+        /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_xtal_off:1;
+        /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_sys_stall:1;
+        /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_sys_rst:1;
+    };
+    uint32_t val;
+} lp_timer_update_reg_t;
+
+typedef struct {
+    union {
+        struct {
+            uint32_t counter_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+    union {
+        struct {
+            uint32_t counter_hi: 16;
+            uint32_t reserved0 : 16;
+        };
+        uint32_t val;
+    } hi;
+} lp_timer_counter_reg_t;
+
+
+/** Type of main_overflow register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_alarm_load:1;
+    };
+    uint32_t val;
+} lp_timer_main_overflow_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_raw:1;
+        /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_raw:1;
+    };
+    uint32_t val;
+} lp_timer_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_st:1;
+        /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_st:1;
+    };
+    uint32_t val;
+} lp_timer_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_ena:1;
+        /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_ena:1;
+    };
+    uint32_t val;
+} lp_timer_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_clr:1;
+        /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_clr:1;
+    };
+    uint32_t val;
+} lp_timer_int_clr_reg_t;
+
+/** Type of lp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_raw:1;
+        /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_raw:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_raw_reg_t;
+
+/** Type of lp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_st:1;
+        /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_st:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_st_reg_t;
+
+/** Type of lp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_ena:1;
+        /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_ena:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_ena_reg_t;
+
+/** Type of lp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_clr:1;
+        /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_clr:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_clr_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [30:0]; default: 34672976;
+         *  need_des
+         */
+        uint32_t date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_timer_date_reg_t;
+
+
+typedef struct {
+    volatile lp_timer_target_reg_t          target[2];
+    volatile lp_timer_update_reg_t          update;
+    volatile lp_timer_counter_reg_t         counter[2];
+    volatile lp_timer_main_overflow_reg_t main_overflow;
+    volatile lp_timer_int_raw_reg_t int_raw;
+    volatile lp_timer_int_st_reg_t int_st;
+    volatile lp_timer_int_ena_reg_t int_ena;
+    volatile lp_timer_int_clr_reg_t int_clr;
+    volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
+    volatile lp_timer_lp_int_st_reg_t lp_int_st;
+    volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
+    volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
+    uint32_t reserved_048[237];
+    volatile lp_timer_date_reg_t date;
+} lp_timer_dev_t;
+
+extern lp_timer_dev_t LP_TIMER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_uart_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_uart_reg.h
new file mode 100644
index 0000000000..2a494b5d0c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_uart_reg.h
@@ -0,0 +1,1339 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_UART_FIFO_REG register
+ *  FIFO data register
+ */
+#define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0)
+/** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART $n accesses FIFO via this register.
+ */
+#define LP_UART_RXFIFO_RD_BYTE    0x000000FFU
+#define LP_UART_RXFIFO_RD_BYTE_M  (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S)
+#define LP_UART_RXFIFO_RD_BYTE_V  0x000000FFU
+#define LP_UART_RXFIFO_RD_BYTE_S  0
+
+/** LP_UART_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4)
+/** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
+#define LP_UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_RAW_M  (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S)
+#define LP_UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_RAW_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_RAW_M  (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S)
+#define LP_UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define LP_UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_RAW_M  (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S)
+#define LP_UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_RAW_S  2
+/** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define LP_UART_FRM_ERR_INT_RAW    (BIT(3))
+#define LP_UART_FRM_ERR_INT_RAW_M  (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S)
+#define LP_UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_RAW_S  3
+/** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define LP_UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_RAW_M  (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S)
+#define LP_UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_RAW_S  4
+/** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define LP_UART_DSR_CHG_INT_RAW    (BIT(5))
+#define LP_UART_DSR_CHG_INT_RAW_M  (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S)
+#define LP_UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_RAW_S  5
+/** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define LP_UART_CTS_CHG_INT_RAW    (BIT(6))
+#define LP_UART_CTS_CHG_INT_RAW_M  (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S)
+#define LP_UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_RAW_S  6
+/** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define LP_UART_BRK_DET_INT_RAW    (BIT(7))
+#define LP_UART_BRK_DET_INT_RAW_M  (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S)
+#define LP_UART_BRK_DET_INT_RAW_V  0x00000001U
+#define LP_UART_BRK_DET_INT_RAW_S  7
+/** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_RAW_M  (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S)
+#define LP_UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_RAW_S  8
+/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define LP_UART_SW_XON_INT_RAW    (BIT(9))
+#define LP_UART_SW_XON_INT_RAW_M  (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S)
+#define LP_UART_SW_XON_INT_RAW_V  0x00000001U
+#define LP_UART_SW_XON_INT_RAW_S  9
+/** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define LP_UART_SW_XOFF_INT_RAW    (BIT(10))
+#define LP_UART_SW_XOFF_INT_RAW_M  (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S)
+#define LP_UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_RAW_S  10
+/** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define LP_UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_RAW_M  (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S)
+#define LP_UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_RAW_S  11
+/** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters after all data in Tx-FIFO are sent.
+ */
+#define LP_UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_RAW_M  (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S)
+#define LP_UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_RAW_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M  (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define LP_UART_TX_DONE_INT_RAW    (BIT(14))
+#define LP_UART_TX_DONE_INT_RAW_M  (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S)
+#define LP_UART_TX_DONE_INT_RAW_V  0x00000001U
+#define LP_UART_TX_DONE_INT_RAW_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M  (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define LP_UART_WAKEUP_INT_RAW    (BIT(19))
+#define LP_UART_WAKEUP_INT_RAW_M  (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S)
+#define LP_UART_WAKEUP_INT_RAW_V  0x00000001U
+#define LP_UART_WAKEUP_INT_RAW_S  19
+
+/** LP_UART_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8)
+/** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
+#define LP_UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_ST_M  (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S)
+#define LP_UART_RXFIFO_FULL_INT_ST_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_ST_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_ST_M  (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S)
+#define LP_UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_ST_S  1
+/** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define LP_UART_PARITY_ERR_INT_ST    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_ST_M  (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S)
+#define LP_UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_ST_S  2
+/** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define LP_UART_FRM_ERR_INT_ST    (BIT(3))
+#define LP_UART_FRM_ERR_INT_ST_M  (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S)
+#define LP_UART_FRM_ERR_INT_ST_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_ST_S  3
+/** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define LP_UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_ST_M  (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S)
+#define LP_UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_ST_S  4
+/** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define LP_UART_DSR_CHG_INT_ST    (BIT(5))
+#define LP_UART_DSR_CHG_INT_ST_M  (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S)
+#define LP_UART_DSR_CHG_INT_ST_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_ST_S  5
+/** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define LP_UART_CTS_CHG_INT_ST    (BIT(6))
+#define LP_UART_CTS_CHG_INT_ST_M  (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S)
+#define LP_UART_CTS_CHG_INT_ST_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_ST_S  6
+/** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define LP_UART_BRK_DET_INT_ST    (BIT(7))
+#define LP_UART_BRK_DET_INT_ST_M  (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S)
+#define LP_UART_BRK_DET_INT_ST_V  0x00000001U
+#define LP_UART_BRK_DET_INT_ST_S  7
+/** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_ST_M  (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S)
+#define LP_UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_ST_S  8
+/** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define LP_UART_SW_XON_INT_ST    (BIT(9))
+#define LP_UART_SW_XON_INT_ST_M  (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S)
+#define LP_UART_SW_XON_INT_ST_V  0x00000001U
+#define LP_UART_SW_XON_INT_ST_S  9
+/** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define LP_UART_SW_XOFF_INT_ST    (BIT(10))
+#define LP_UART_SW_XOFF_INT_ST_M  (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S)
+#define LP_UART_SW_XOFF_INT_ST_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_ST_S  10
+/** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define LP_UART_GLITCH_DET_INT_ST    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_ST_M  (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S)
+#define LP_UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_ST_S  11
+/** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define LP_UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_ST_M  (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S)
+#define LP_UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_ST_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define LP_UART_TX_DONE_INT_ST    (BIT(14))
+#define LP_UART_TX_DONE_INT_ST_M  (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S)
+#define LP_UART_TX_DONE_INT_ST_V  0x00000001U
+#define LP_UART_TX_DONE_INT_ST_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST_M  (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define LP_UART_WAKEUP_INT_ST    (BIT(19))
+#define LP_UART_WAKEUP_INT_ST_M  (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S)
+#define LP_UART_WAKEUP_INT_ST_V  0x00000001U
+#define LP_UART_WAKEUP_INT_ST_S  19
+
+/** LP_UART_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc)
+/** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
+#define LP_UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_ENA_M  (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S)
+#define LP_UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_ENA_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_ENA_M  (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S)
+#define LP_UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define LP_UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_ENA_M  (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S)
+#define LP_UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_ENA_S  2
+/** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define LP_UART_FRM_ERR_INT_ENA    (BIT(3))
+#define LP_UART_FRM_ERR_INT_ENA_M  (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S)
+#define LP_UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_ENA_S  3
+/** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define LP_UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_ENA_M  (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S)
+#define LP_UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_ENA_S  4
+/** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define LP_UART_DSR_CHG_INT_ENA    (BIT(5))
+#define LP_UART_DSR_CHG_INT_ENA_M  (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S)
+#define LP_UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_ENA_S  5
+/** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define LP_UART_CTS_CHG_INT_ENA    (BIT(6))
+#define LP_UART_CTS_CHG_INT_ENA_M  (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S)
+#define LP_UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_ENA_S  6
+/** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define LP_UART_BRK_DET_INT_ENA    (BIT(7))
+#define LP_UART_BRK_DET_INT_ENA_M  (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S)
+#define LP_UART_BRK_DET_INT_ENA_V  0x00000001U
+#define LP_UART_BRK_DET_INT_ENA_S  7
+/** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_ENA_M  (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S)
+#define LP_UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_ENA_S  8
+/** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define LP_UART_SW_XON_INT_ENA    (BIT(9))
+#define LP_UART_SW_XON_INT_ENA_M  (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S)
+#define LP_UART_SW_XON_INT_ENA_V  0x00000001U
+#define LP_UART_SW_XON_INT_ENA_S  9
+/** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define LP_UART_SW_XOFF_INT_ENA    (BIT(10))
+#define LP_UART_SW_XOFF_INT_ENA_M  (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S)
+#define LP_UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_ENA_S  10
+/** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define LP_UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_ENA_M  (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S)
+#define LP_UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_ENA_S  11
+/** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define LP_UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_ENA_M  (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S)
+#define LP_UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_ENA_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define LP_UART_TX_DONE_INT_ENA    (BIT(14))
+#define LP_UART_TX_DONE_INT_ENA_M  (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S)
+#define LP_UART_TX_DONE_INT_ENA_V  0x00000001U
+#define LP_UART_TX_DONE_INT_ENA_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M  (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define LP_UART_WAKEUP_INT_ENA    (BIT(19))
+#define LP_UART_WAKEUP_INT_ENA_M  (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S)
+#define LP_UART_WAKEUP_INT_ENA_V  0x00000001U
+#define LP_UART_WAKEUP_INT_ENA_S  19
+
+/** LP_UART_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10)
+/** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
+#define LP_UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_CLR_M  (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S)
+#define LP_UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_CLR_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_CLR_M  (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S)
+#define LP_UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define LP_UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_CLR_M  (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S)
+#define LP_UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_CLR_S  2
+/** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define LP_UART_FRM_ERR_INT_CLR    (BIT(3))
+#define LP_UART_FRM_ERR_INT_CLR_M  (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S)
+#define LP_UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_CLR_S  3
+/** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define LP_UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_CLR_M  (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S)
+#define LP_UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_CLR_S  4
+/** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define LP_UART_DSR_CHG_INT_CLR    (BIT(5))
+#define LP_UART_DSR_CHG_INT_CLR_M  (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S)
+#define LP_UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_CLR_S  5
+/** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define LP_UART_CTS_CHG_INT_CLR    (BIT(6))
+#define LP_UART_CTS_CHG_INT_CLR_M  (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S)
+#define LP_UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_CLR_S  6
+/** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define LP_UART_BRK_DET_INT_CLR    (BIT(7))
+#define LP_UART_BRK_DET_INT_CLR_M  (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S)
+#define LP_UART_BRK_DET_INT_CLR_V  0x00000001U
+#define LP_UART_BRK_DET_INT_CLR_S  7
+/** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_CLR_M  (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S)
+#define LP_UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_CLR_S  8
+/** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define LP_UART_SW_XON_INT_CLR    (BIT(9))
+#define LP_UART_SW_XON_INT_CLR_M  (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S)
+#define LP_UART_SW_XON_INT_CLR_V  0x00000001U
+#define LP_UART_SW_XON_INT_CLR_S  9
+/** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define LP_UART_SW_XOFF_INT_CLR    (BIT(10))
+#define LP_UART_SW_XOFF_INT_CLR_M  (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S)
+#define LP_UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_CLR_S  10
+/** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define LP_UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_CLR_M  (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S)
+#define LP_UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_CLR_S  11
+/** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define LP_UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_CLR_M  (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S)
+#define LP_UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_CLR_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M  (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define LP_UART_TX_DONE_INT_CLR    (BIT(14))
+#define LP_UART_TX_DONE_INT_CLR_M  (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S)
+#define LP_UART_TX_DONE_INT_CLR_V  0x00000001U
+#define LP_UART_TX_DONE_INT_CLR_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M  (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define LP_UART_WAKEUP_INT_CLR    (BIT(19))
+#define LP_UART_WAKEUP_INT_CLR_M  (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S)
+#define LP_UART_WAKEUP_INT_CLR_V  0x00000001U
+#define LP_UART_WAKEUP_INT_CLR_S  19
+
+/** LP_UART_CLKDIV_SYNC_REG register
+ *  Clock divider configuration
+ */
+#define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14)
+/** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define LP_UART_CLKDIV    0x00000FFFU
+#define LP_UART_CLKDIV_M  (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S)
+#define LP_UART_CLKDIV_V  0x00000FFFU
+#define LP_UART_CLKDIV_S  0
+/** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define LP_UART_CLKDIV_FRAG    0x0000000FU
+#define LP_UART_CLKDIV_FRAG_M  (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S)
+#define LP_UART_CLKDIV_FRAG_V  0x0000000FU
+#define LP_UART_CLKDIV_FRAG_S  20
+
+/** LP_UART_RX_FILT_REG register
+ *  Rx Filter configuration
+ */
+#define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18)
+/** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value the pulse is ignored.
+ */
+#define LP_UART_GLITCH_FILT    0x000000FFU
+#define LP_UART_GLITCH_FILT_M  (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S)
+#define LP_UART_GLITCH_FILT_V  0x000000FFU
+#define LP_UART_GLITCH_FILT_S  0
+/** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
+#define LP_UART_GLITCH_FILT_EN    (BIT(8))
+#define LP_UART_GLITCH_FILT_EN_M  (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S)
+#define LP_UART_GLITCH_FILT_EN_V  0x00000001U
+#define LP_UART_GLITCH_FILT_EN_S  8
+
+/** LP_UART_STATUS_REG register
+ *  UART status register
+ */
+#define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c)
+/** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define LP_UART_RXFIFO_CNT    0x0000001FU
+#define LP_UART_RXFIFO_CNT_M  (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S)
+#define LP_UART_RXFIFO_CNT_V  0x0000001FU
+#define LP_UART_RXFIFO_CNT_S  3
+/** LP_UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
+#define LP_UART_DSRN    (BIT(13))
+#define LP_UART_DSRN_M  (LP_UART_DSRN_V << LP_UART_DSRN_S)
+#define LP_UART_DSRN_V  0x00000001U
+#define LP_UART_DSRN_S  13
+/** LP_UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define LP_UART_CTSN    (BIT(14))
+#define LP_UART_CTSN_M  (LP_UART_CTSN_V << LP_UART_CTSN_S)
+#define LP_UART_CTSN_V  0x00000001U
+#define LP_UART_CTSN_S  14
+/** LP_UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define LP_UART_RXD    (BIT(15))
+#define LP_UART_RXD_M  (LP_UART_RXD_V << LP_UART_RXD_S)
+#define LP_UART_RXD_V  0x00000001U
+#define LP_UART_RXD_S  15
+/** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define LP_UART_TXFIFO_CNT    0x0000001FU
+#define LP_UART_TXFIFO_CNT_M  (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S)
+#define LP_UART_TXFIFO_CNT_V  0x0000001FU
+#define LP_UART_TXFIFO_CNT_S  19
+/** LP_UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define LP_UART_DTRN    (BIT(29))
+#define LP_UART_DTRN_M  (LP_UART_DTRN_V << LP_UART_DTRN_S)
+#define LP_UART_DTRN_V  0x00000001U
+#define LP_UART_DTRN_S  29
+/** LP_UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define LP_UART_RTSN    (BIT(30))
+#define LP_UART_RTSN_M  (LP_UART_RTSN_V << LP_UART_RTSN_S)
+#define LP_UART_RTSN_V  0x00000001U
+#define LP_UART_RTSN_S  30
+/** LP_UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define LP_UART_TXD    (BIT(31))
+#define LP_UART_TXD_M  (LP_UART_TXD_V << LP_UART_TXD_S)
+#define LP_UART_TXD_V  0x00000001U
+#define LP_UART_TXD_S  31
+
+/** LP_UART_CONF0_SYNC_REG register
+ *  Configuration register 0
+ */
+#define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20)
+/** LP_UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
+#define LP_UART_PARITY    (BIT(0))
+#define LP_UART_PARITY_M  (LP_UART_PARITY_V << LP_UART_PARITY_S)
+#define LP_UART_PARITY_V  0x00000001U
+#define LP_UART_PARITY_S  0
+/** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define LP_UART_PARITY_EN    (BIT(1))
+#define LP_UART_PARITY_EN_M  (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S)
+#define LP_UART_PARITY_EN_V  0x00000001U
+#define LP_UART_PARITY_EN_S  1
+/** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define LP_UART_BIT_NUM    0x00000003U
+#define LP_UART_BIT_NUM_M  (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S)
+#define LP_UART_BIT_NUM_V  0x00000003U
+#define LP_UART_BIT_NUM_S  2
+/** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define LP_UART_STOP_BIT_NUM    0x00000003U
+#define LP_UART_STOP_BIT_NUM_M  (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S)
+#define LP_UART_STOP_BIT_NUM_V  0x00000003U
+#define LP_UART_STOP_BIT_NUM_S  4
+/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define LP_UART_TXD_BRK    (BIT(6))
+#define LP_UART_TXD_BRK_M  (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S)
+#define LP_UART_TXD_BRK_V  0x00000001U
+#define LP_UART_TXD_BRK_S  6
+/** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define LP_UART_LOOPBACK    (BIT(12))
+#define LP_UART_LOOPBACK_M  (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S)
+#define LP_UART_LOOPBACK_V  0x00000001U
+#define LP_UART_LOOPBACK_S  12
+/** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define LP_UART_TX_FLOW_EN    (BIT(13))
+#define LP_UART_TX_FLOW_EN_M  (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S)
+#define LP_UART_TX_FLOW_EN_V  0x00000001U
+#define LP_UART_TX_FLOW_EN_S  13
+/** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define LP_UART_RXD_INV    (BIT(15))
+#define LP_UART_RXD_INV_M  (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S)
+#define LP_UART_RXD_INV_V  0x00000001U
+#define LP_UART_RXD_INV_S  15
+/** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define LP_UART_TXD_INV    (BIT(16))
+#define LP_UART_TXD_INV_M  (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S)
+#define LP_UART_TXD_INV_V  0x00000001U
+#define LP_UART_TXD_INV_S  16
+/** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
+#define LP_UART_DIS_RX_DAT_OVF    (BIT(17))
+#define LP_UART_DIS_RX_DAT_OVF_M  (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S)
+#define LP_UART_DIS_RX_DAT_OVF_V  0x00000001U
+#define LP_UART_DIS_RX_DAT_OVF_S  17
+/** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define LP_UART_ERR_WR_MASK    (BIT(18))
+#define LP_UART_ERR_WR_MASK_M  (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S)
+#define LP_UART_ERR_WR_MASK_V  0x00000001U
+#define LP_UART_ERR_WR_MASK_S  18
+/** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  UART memory clock gate enable signal.
+ */
+#define LP_UART_MEM_CLK_EN    (BIT(20))
+#define LP_UART_MEM_CLK_EN_M  (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S)
+#define LP_UART_MEM_CLK_EN_V  0x00000001U
+#define LP_UART_MEM_CLK_EN_S  20
+/** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define LP_UART_SW_RTS    (BIT(21))
+#define LP_UART_SW_RTS_M  (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S)
+#define LP_UART_SW_RTS_V  0x00000001U
+#define LP_UART_SW_RTS_S  21
+/** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define LP_UART_RXFIFO_RST    (BIT(22))
+#define LP_UART_RXFIFO_RST_M  (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S)
+#define LP_UART_RXFIFO_RST_V  0x00000001U
+#define LP_UART_RXFIFO_RST_S  22
+/** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define LP_UART_TXFIFO_RST    (BIT(23))
+#define LP_UART_TXFIFO_RST_M  (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S)
+#define LP_UART_TXFIFO_RST_V  0x00000001U
+#define LP_UART_TXFIFO_RST_S  23
+
+/** LP_UART_CONF1_REG register
+ *  Configuration register 1
+ */
+#define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24)
+/** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define LP_UART_RXFIFO_FULL_THRHD    0x0000001FU
+#define LP_UART_RXFIFO_FULL_THRHD_M  (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S)
+#define LP_UART_RXFIFO_FULL_THRHD_V  0x0000001FU
+#define LP_UART_RXFIFO_FULL_THRHD_S  3
+/** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define LP_UART_TXFIFO_EMPTY_THRHD    0x0000001FU
+#define LP_UART_TXFIFO_EMPTY_THRHD_M  (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S)
+#define LP_UART_TXFIFO_EMPTY_THRHD_V  0x0000001FU
+#define LP_UART_TXFIFO_EMPTY_THRHD_S  11
+/** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define LP_UART_CTS_INV    (BIT(16))
+#define LP_UART_CTS_INV_M  (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S)
+#define LP_UART_CTS_INV_V  0x00000001U
+#define LP_UART_CTS_INV_S  16
+/** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define LP_UART_DSR_INV    (BIT(17))
+#define LP_UART_DSR_INV_M  (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S)
+#define LP_UART_DSR_INV_V  0x00000001U
+#define LP_UART_DSR_INV_S  17
+/** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define LP_UART_RTS_INV    (BIT(18))
+#define LP_UART_RTS_INV_M  (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S)
+#define LP_UART_RTS_INV_V  0x00000001U
+#define LP_UART_RTS_INV_S  18
+/** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define LP_UART_DTR_INV    (BIT(19))
+#define LP_UART_DTR_INV_M  (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S)
+#define LP_UART_DTR_INV_V  0x00000001U
+#define LP_UART_DTR_INV_S  19
+/** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define LP_UART_SW_DTR    (BIT(20))
+#define LP_UART_SW_DTR_M  (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S)
+#define LP_UART_SW_DTR_V  0x00000001U
+#define LP_UART_SW_DTR_S  20
+/** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define LP_UART_CLK_EN    (BIT(21))
+#define LP_UART_CLK_EN_M  (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S)
+#define LP_UART_CLK_EN_V  0x00000001U
+#define LP_UART_CLK_EN_S  21
+
+/** LP_UART_HWFC_CONF_SYNC_REG register
+ *  Hardware flow-control configuration
+ */
+#define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c)
+/** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define LP_UART_RX_FLOW_THRHD    0x0000001FU
+#define LP_UART_RX_FLOW_THRHD_M  (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S)
+#define LP_UART_RX_FLOW_THRHD_V  0x0000001FU
+#define LP_UART_RX_FLOW_THRHD_S  3
+/** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define LP_UART_RX_FLOW_EN    (BIT(8))
+#define LP_UART_RX_FLOW_EN_M  (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S)
+#define LP_UART_RX_FLOW_EN_V  0x00000001U
+#define LP_UART_RX_FLOW_EN_S  8
+
+/** LP_UART_SLEEP_CONF0_REG register
+ *  UART sleep configure register 0
+ */
+#define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30)
+/** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified wake up char1 to wake up
+ */
+#define LP_UART_WK_CHAR1    0x000000FFU
+#define LP_UART_WK_CHAR1_M  (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S)
+#define LP_UART_WK_CHAR1_V  0x000000FFU
+#define LP_UART_WK_CHAR1_S  0
+/** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
+ *  This register restores the specified wake up char2 to wake up
+ */
+#define LP_UART_WK_CHAR2    0x000000FFU
+#define LP_UART_WK_CHAR2_M  (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S)
+#define LP_UART_WK_CHAR2_V  0x000000FFU
+#define LP_UART_WK_CHAR2_S  8
+/** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
+ *  This register restores the specified wake up char3 to wake up
+ */
+#define LP_UART_WK_CHAR3    0x000000FFU
+#define LP_UART_WK_CHAR3_M  (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S)
+#define LP_UART_WK_CHAR3_V  0x000000FFU
+#define LP_UART_WK_CHAR3_S  16
+/** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
+ *  This register restores the specified wake up char4 to wake up
+ */
+#define LP_UART_WK_CHAR4    0x000000FFU
+#define LP_UART_WK_CHAR4_M  (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S)
+#define LP_UART_WK_CHAR4_V  0x000000FFU
+#define LP_UART_WK_CHAR4_S  24
+
+/** LP_UART_SLEEP_CONF1_REG register
+ *  UART sleep configure register 1
+ */
+#define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34)
+/** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified char0 to wake up
+ */
+#define LP_UART_WK_CHAR0    0x000000FFU
+#define LP_UART_WK_CHAR0_M  (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S)
+#define LP_UART_WK_CHAR0_V  0x000000FFU
+#define LP_UART_WK_CHAR0_S  0
+
+/** LP_UART_SLEEP_CONF2_REG register
+ *  UART sleep configure register 2
+ */
+#define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38)
+/** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define LP_UART_ACTIVE_THRESHOLD    0x000003FFU
+#define LP_UART_ACTIVE_THRESHOLD_M  (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S)
+#define LP_UART_ACTIVE_THRESHOLD_V  0x000003FFU
+#define LP_UART_ACTIVE_THRESHOLD_S  0
+/** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1;
+ *  In wake up mode 1 this field is used to set the received data number threshold to
+ *  wake up chip.
+ */
+#define LP_UART_RX_WAKE_UP_THRHD    0x0000001FU
+#define LP_UART_RX_WAKE_UP_THRHD_M  (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S)
+#define LP_UART_RX_WAKE_UP_THRHD_V  0x0000001FU
+#define LP_UART_RX_WAKE_UP_THRHD_S  13
+/** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
+ *  This register is used to select number of wake up char.
+ */
+#define LP_UART_WK_CHAR_NUM    0x00000007U
+#define LP_UART_WK_CHAR_NUM_M  (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S)
+#define LP_UART_WK_CHAR_NUM_V  0x00000007U
+#define LP_UART_WK_CHAR_NUM_S  18
+/** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
+ *  This register is used to mask  wake up char.
+ */
+#define LP_UART_WK_CHAR_MASK    0x0000001FU
+#define LP_UART_WK_CHAR_MASK_M  (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S)
+#define LP_UART_WK_CHAR_MASK_V  0x0000001FU
+#define LP_UART_WK_CHAR_MASK_S  21
+/** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+ *  received data number larger than
+ */
+#define LP_UART_WK_MODE_SEL    0x00000003U
+#define LP_UART_WK_MODE_SEL_M  (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S)
+#define LP_UART_WK_MODE_SEL_V  0x00000003U
+#define LP_UART_WK_MODE_SEL_S  26
+
+/** LP_UART_SWFC_CONF0_SYNC_REG register
+ *  Software flow-control character configuration
+ */
+#define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c)
+/** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define LP_UART_XON_CHAR    0x000000FFU
+#define LP_UART_XON_CHAR_M  (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S)
+#define LP_UART_XON_CHAR_V  0x000000FFU
+#define LP_UART_XON_CHAR_S  0
+/** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define LP_UART_XOFF_CHAR    0x000000FFU
+#define LP_UART_XOFF_CHAR_M  (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S)
+#define LP_UART_XOFF_CHAR_V  0x000000FFU
+#define LP_UART_XOFF_CHAR_S  8
+/** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
+ *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+ *  this status, UART Tx can not transmit XOFF even the received data number is larger
+ *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+ *  UART Tx is disabled.
+ */
+#define LP_UART_XON_XOFF_STILL_SEND    (BIT(16))
+#define LP_UART_XON_XOFF_STILL_SEND_M  (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S)
+#define LP_UART_XON_XOFF_STILL_SEND_V  0x00000001U
+#define LP_UART_XON_XOFF_STILL_SEND_S  16
+/** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
+#define LP_UART_SW_FLOW_CON_EN    (BIT(17))
+#define LP_UART_SW_FLOW_CON_EN_M  (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S)
+#define LP_UART_SW_FLOW_CON_EN_V  0x00000001U
+#define LP_UART_SW_FLOW_CON_EN_S  17
+/** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define LP_UART_XONOFF_DEL    (BIT(18))
+#define LP_UART_XONOFF_DEL_M  (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S)
+#define LP_UART_XONOFF_DEL_V  0x00000001U
+#define LP_UART_XONOFF_DEL_S  18
+/** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define LP_UART_FORCE_XON    (BIT(19))
+#define LP_UART_FORCE_XON_M  (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S)
+#define LP_UART_FORCE_XON_V  0x00000001U
+#define LP_UART_FORCE_XON_S  19
+/** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define LP_UART_FORCE_XOFF    (BIT(20))
+#define LP_UART_FORCE_XOFF_M  (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S)
+#define LP_UART_FORCE_XOFF_V  0x00000001U
+#define LP_UART_FORCE_XOFF_S  20
+/** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define LP_UART_SEND_XON    (BIT(21))
+#define LP_UART_SEND_XON_M  (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S)
+#define LP_UART_SEND_XON_V  0x00000001U
+#define LP_UART_SEND_XON_S  21
+/** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define LP_UART_SEND_XOFF    (BIT(22))
+#define LP_UART_SEND_XOFF_M  (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S)
+#define LP_UART_SEND_XOFF_V  0x00000001U
+#define LP_UART_SEND_XOFF_S  22
+
+/** LP_UART_SWFC_CONF1_REG register
+ *  Software flow-control character configuration
+ */
+#define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40)
+/** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+ */
+#define LP_UART_XON_THRESHOLD    0x0000001FU
+#define LP_UART_XON_THRESHOLD_M  (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S)
+#define LP_UART_XON_THRESHOLD_V  0x0000001FU
+#define LP_UART_XON_THRESHOLD_S  3
+/** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+ */
+#define LP_UART_XOFF_THRESHOLD    0x0000001FU
+#define LP_UART_XOFF_THRESHOLD_M  (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S)
+#define LP_UART_XOFF_THRESHOLD_V  0x0000001FU
+#define LP_UART_XOFF_THRESHOLD_S  11
+
+/** LP_UART_TXBRK_CONF_SYNC_REG register
+ *  Tx Break character configuration
+ */
+#define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44)
+/** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define LP_UART_TX_BRK_NUM    0x000000FFU
+#define LP_UART_TX_BRK_NUM_M  (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S)
+#define LP_UART_TX_BRK_NUM_V  0x000000FFU
+#define LP_UART_TX_BRK_NUM_S  0
+
+/** LP_UART_IDLE_CONF_SYNC_REG register
+ *  Frame-end idle configuration
+ */
+#define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48)
+/** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define LP_UART_RX_IDLE_THRHD    0x000003FFU
+#define LP_UART_RX_IDLE_THRHD_M  (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S)
+#define LP_UART_RX_IDLE_THRHD_V  0x000003FFU
+#define LP_UART_RX_IDLE_THRHD_S  0
+/** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define LP_UART_TX_IDLE_NUM    0x000003FFU
+#define LP_UART_TX_IDLE_NUM_M  (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S)
+#define LP_UART_TX_IDLE_NUM_V  0x000003FFU
+#define LP_UART_TX_IDLE_NUM_S  10
+
+/** LP_UART_RS485_CONF_SYNC_REG register
+ *  RS485 mode configuration
+ */
+#define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c)
+/** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define LP_UART_DL0_EN    (BIT(1))
+#define LP_UART_DL0_EN_M  (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S)
+#define LP_UART_DL0_EN_V  0x00000001U
+#define LP_UART_DL0_EN_S  1
+/** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define LP_UART_DL1_EN    (BIT(2))
+#define LP_UART_DL1_EN_M  (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S)
+#define LP_UART_DL1_EN_V  0x00000001U
+#define LP_UART_DL1_EN_S  2
+
+/** LP_UART_AT_CMD_PRECNT_SYNC_REG register
+ *  Pre-sequence timing configuration
+ */
+#define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50)
+/** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define LP_UART_PRE_IDLE_NUM    0x0000FFFFU
+#define LP_UART_PRE_IDLE_NUM_M  (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S)
+#define LP_UART_PRE_IDLE_NUM_V  0x0000FFFFU
+#define LP_UART_PRE_IDLE_NUM_S  0
+
+/** LP_UART_AT_CMD_POSTCNT_SYNC_REG register
+ *  Post-sequence timing configuration
+ */
+#define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54)
+/** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define LP_UART_POST_IDLE_NUM    0x0000FFFFU
+#define LP_UART_POST_IDLE_NUM_M  (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S)
+#define LP_UART_POST_IDLE_NUM_V  0x0000FFFFU
+#define LP_UART_POST_IDLE_NUM_S  0
+
+/** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register
+ *  Timeout configuration
+ */
+#define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58)
+/** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define LP_UART_RX_GAP_TOUT    0x0000FFFFU
+#define LP_UART_RX_GAP_TOUT_M  (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S)
+#define LP_UART_RX_GAP_TOUT_V  0x0000FFFFU
+#define LP_UART_RX_GAP_TOUT_S  0
+
+/** LP_UART_AT_CMD_CHAR_SYNC_REG register
+ *  AT escape sequence detection configuration
+ */
+#define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c)
+/** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define LP_UART_AT_CMD_CHAR    0x000000FFU
+#define LP_UART_AT_CMD_CHAR_M  (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S)
+#define LP_UART_AT_CMD_CHAR_V  0x000000FFU
+#define LP_UART_AT_CMD_CHAR_S  0
+/** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define LP_UART_CHAR_NUM    0x000000FFU
+#define LP_UART_CHAR_NUM_M  (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S)
+#define LP_UART_CHAR_NUM_V  0x000000FFU
+#define LP_UART_CHAR_NUM_S  8
+
+/** LP_UART_MEM_CONF_REG register
+ *  UART memory power configuration
+ */
+#define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60)
+/** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
+#define LP_UART_MEM_FORCE_PD    (BIT(25))
+#define LP_UART_MEM_FORCE_PD_M  (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S)
+#define LP_UART_MEM_FORCE_PD_V  0x00000001U
+#define LP_UART_MEM_FORCE_PD_S  25
+/** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define LP_UART_MEM_FORCE_PU    (BIT(26))
+#define LP_UART_MEM_FORCE_PU_M  (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S)
+#define LP_UART_MEM_FORCE_PU_V  0x00000001U
+#define LP_UART_MEM_FORCE_PU_S  26
+
+/** LP_UART_TOUT_CONF_SYNC_REG register
+ *  UART threshold and allocation configuration
+ */
+#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64)
+/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for uart receiver's timeout function.
+ */
+#define LP_UART_RX_TOUT_EN    (BIT(0))
+#define LP_UART_RX_TOUT_EN_M  (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S)
+#define LP_UART_RX_TOUT_EN_V  0x00000001U
+#define LP_UART_RX_TOUT_EN_S  0
+/** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define LP_UART_RX_TOUT_FLOW_DIS    (BIT(1))
+#define LP_UART_RX_TOUT_FLOW_DIS_M  (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S)
+#define LP_UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define LP_UART_RX_TOUT_FLOW_DIS_S  1
+/** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define LP_UART_RX_TOUT_THRHD    0x000003FFU
+#define LP_UART_RX_TOUT_THRHD_M  (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S)
+#define LP_UART_RX_TOUT_THRHD_V  0x000003FFU
+#define LP_UART_RX_TOUT_THRHD_S  2
+
+/** LP_UART_MEM_TX_STATUS_REG register
+ *  Tx-SRAM write and read offset address.
+ */
+#define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68)
+/** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0;
+ *  This register stores the offset write address in Tx-SRAM.
+ */
+#define LP_UART_TX_SRAM_WADDR    0x0000001FU
+#define LP_UART_TX_SRAM_WADDR_M  (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S)
+#define LP_UART_TX_SRAM_WADDR_V  0x0000001FU
+#define LP_UART_TX_SRAM_WADDR_S  3
+/** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0;
+ *  This register stores the offset read address in Tx-SRAM.
+ */
+#define LP_UART_TX_SRAM_RADDR    0x0000001FU
+#define LP_UART_TX_SRAM_RADDR_M  (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S)
+#define LP_UART_TX_SRAM_RADDR_V  0x0000001FU
+#define LP_UART_TX_SRAM_RADDR_S  12
+
+/** LP_UART_MEM_RX_STATUS_REG register
+ *  Rx-SRAM write and read offset address.
+ */
+#define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c)
+/** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16;
+ *  This register stores the offset read address in RX-SRAM.
+ */
+#define LP_UART_RX_SRAM_RADDR    0x0000001FU
+#define LP_UART_RX_SRAM_RADDR_M  (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S)
+#define LP_UART_RX_SRAM_RADDR_V  0x0000001FU
+#define LP_UART_RX_SRAM_RADDR_S  3
+/** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16;
+ *  This register stores the offset write address in Rx-SRAM.
+ */
+#define LP_UART_RX_SRAM_WADDR    0x0000001FU
+#define LP_UART_RX_SRAM_WADDR_M  (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S)
+#define LP_UART_RX_SRAM_WADDR_V  0x0000001FU
+#define LP_UART_RX_SRAM_WADDR_S  12
+
+/** LP_UART_FSM_STATUS_REG register
+ *  UART transmit and receive status.
+ */
+#define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70)
+/** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define LP_UART_ST_URX_OUT    0x0000000FU
+#define LP_UART_ST_URX_OUT_M  (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S)
+#define LP_UART_ST_URX_OUT_V  0x0000000FU
+#define LP_UART_ST_URX_OUT_S  0
+/** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define LP_UART_ST_UTX_OUT    0x0000000FU
+#define LP_UART_ST_UTX_OUT_M  (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S)
+#define LP_UART_ST_UTX_OUT_V  0x0000000FU
+#define LP_UART_ST_UTX_OUT_S  4
+
+/** LP_UART_CLK_CONF_REG register
+ *  UART core clock configuration
+ */
+#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88)
+/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable UART Tx clock.
+ */
+#define LP_UART_TX_SCLK_EN    (BIT(24))
+#define LP_UART_TX_SCLK_EN_M  (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S)
+#define LP_UART_TX_SCLK_EN_V  0x00000001U
+#define LP_UART_TX_SCLK_EN_S  24
+/** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Set this bit to enable UART Rx clock.
+ */
+#define LP_UART_RX_SCLK_EN    (BIT(25))
+#define LP_UART_RX_SCLK_EN_M  (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S)
+#define LP_UART_RX_SCLK_EN_V  0x00000001U
+#define LP_UART_RX_SCLK_EN_S  25
+/** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Tx.
+ */
+#define LP_UART_TX_RST_CORE    (BIT(26))
+#define LP_UART_TX_RST_CORE_M  (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S)
+#define LP_UART_TX_RST_CORE_V  0x00000001U
+#define LP_UART_TX_RST_CORE_S  26
+/** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Rx.
+ */
+#define LP_UART_RX_RST_CORE    (BIT(27))
+#define LP_UART_RX_RST_CORE_M  (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S)
+#define LP_UART_RX_RST_CORE_V  0x00000001U
+#define LP_UART_RX_RST_CORE_S  27
+
+/** LP_UART_DATE_REG register
+ *  UART Version register
+ */
+#define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c)
+/** LP_UART_DATE : R/W; bitpos: [31:0]; default: 36720720;
+ *  This is the version register.
+ */
+#define LP_UART_DATE    0xFFFFFFFFU
+#define LP_UART_DATE_M  (LP_UART_DATE_V << LP_UART_DATE_S)
+#define LP_UART_DATE_V  0xFFFFFFFFU
+#define LP_UART_DATE_S  0
+
+/** LP_UART_AFIFO_STATUS_REG register
+ *  UART AFIFO Status
+ */
+#define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90)
+/** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
+ *  Full signal of APB TX AFIFO.
+ */
+#define LP_UART_TX_AFIFO_FULL    (BIT(0))
+#define LP_UART_TX_AFIFO_FULL_M  (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S)
+#define LP_UART_TX_AFIFO_FULL_V  0x00000001U
+#define LP_UART_TX_AFIFO_FULL_S  0
+/** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
+ *  Empty signal of APB TX AFIFO.
+ */
+#define LP_UART_TX_AFIFO_EMPTY    (BIT(1))
+#define LP_UART_TX_AFIFO_EMPTY_M  (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S)
+#define LP_UART_TX_AFIFO_EMPTY_V  0x00000001U
+#define LP_UART_TX_AFIFO_EMPTY_S  1
+/** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
+ *  Full signal of APB RX AFIFO.
+ */
+#define LP_UART_RX_AFIFO_FULL    (BIT(2))
+#define LP_UART_RX_AFIFO_FULL_M  (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S)
+#define LP_UART_RX_AFIFO_FULL_V  0x00000001U
+#define LP_UART_RX_AFIFO_FULL_S  2
+/** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
+ *  Empty signal of APB RX AFIFO.
+ */
+#define LP_UART_RX_AFIFO_EMPTY    (BIT(3))
+#define LP_UART_RX_AFIFO_EMPTY_M  (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S)
+#define LP_UART_RX_AFIFO_EMPTY_V  0x00000001U
+#define LP_UART_RX_AFIFO_EMPTY_S  3
+
+/** LP_UART_REG_UPDATE_REG register
+ *  UART Registers Configuration Update register
+ */
+#define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98)
+/** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define LP_UART_REG_UPDATE    (BIT(0))
+#define LP_UART_REG_UPDATE_M  (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S)
+#define LP_UART_REG_UPDATE_V  0x00000001U
+#define LP_UART_REG_UPDATE_S  0
+
+/** LP_UART_ID_REG register
+ *  UART ID register
+ */
+#define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c)
+/** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define LP_UART_ID    0xFFFFFFFFU
+#define LP_UART_ID_M  (LP_UART_ID_V << LP_UART_ID_S)
+#define LP_UART_ID_V  0xFFFFFFFFU
+#define LP_UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_uart_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_uart_struct.h
new file mode 100644
index 0000000000..d7043fc5ed
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_uart_struct.h
@@ -0,0 +1,1102 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         */
+        uint32_t rxfifo_rd_byte:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} lp_uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full_int_raw:1;
+        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty_int_raw:1;
+        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err_int_raw:1;
+        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg_int_raw:1;
+        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg_int_raw:1;
+        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det_int_raw:1;
+        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout_int_raw:1;
+        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon_int_raw:1;
+        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff_int_raw:1;
+        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det_int_raw:1;
+        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done_int_raw:1;
+        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done_int_raw:1;
+        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done_int_raw:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det_int_raw:1;
+        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full_int_st:1;
+        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty_int_st:1;
+        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err_int_st:1;
+        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg_int_st:1;
+        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg_int_st:1;
+        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det_int_st:1;
+        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout_int_st:1;
+        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon_int_st:1;
+        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff_int_st:1;
+        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det_int_st:1;
+        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done_int_st:1;
+        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done_int_st:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det_int_st:1;
+        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full_int_ena:1;
+        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty_int_ena:1;
+        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err_int_ena:1;
+        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg_int_ena:1;
+        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg_int_ena:1;
+        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det_int_ena:1;
+        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout_int_ena:1;
+        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon_int_ena:1;
+        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff_int_ena:1;
+        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det_int_ena:1;
+        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done_int_ena:1;
+        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done_int_ena:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det_int_ena:1;
+        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full_int_clr:1;
+        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty_int_clr:1;
+        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err_int_clr:1;
+        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg_int_clr:1;
+        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg_int_clr:1;
+        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det_int_clr:1;
+        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout_int_clr:1;
+        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon_int_clr:1;
+        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff_int_clr:1;
+        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det_int_clr:1;
+        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done_int_clr:1;
+        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done_int_clr:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det_int_clr:1;
+        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lp_uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} lp_uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  Configuration register 0
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        uint32_t reserved_7:5;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        uint32_t reserved_14:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        uint32_t reserved_19:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lp_uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:5;
+        uint32_t reserved_8:3;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:5;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} lp_uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow-control configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:5;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} lp_uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configure register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified wake up char1 to wake up
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  This register restores the specified wake up char2 to wake up
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  This register restores the specified wake up char3 to wake up
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  This register restores the specified wake up char4 to wake up
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} lp_uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configure register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified char0 to wake up
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configure register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        uint32_t reserved_10:3;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1;
+         *  In wake up mode 1 this field is used to set the received data number threshold to
+         *  wake up chip.
+         */
+        uint32_t rx_wake_up_thrhd:5;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  This register is used to select number of wake up char.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  This register is used to mask  wake up char.
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+         *  received data number larger than
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_char : R/W; bitpos: [7:0]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_char:8;
+        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_char:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+         *  this status, UART Tx can not transmit XOFF even the received data number is larger
+         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+         *  UART Tx is disabled.
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} lp_uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** xon_threshold : R/W; bitpos: [7:3]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+         */
+        uint32_t xon_threshold:5;
+        uint32_t reserved_8:3;
+        /** xoff_threshold : R/W; bitpos: [15:11]; default: 12;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:5;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} lp_uart_rs485_conf_sync_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable UART Tx clock.
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Set this bit to enable UART Rx clock.
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Tx.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Rx.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:5;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        uint32_t reserved_16:3;
+        /** txfifo_cnt : RO; bitpos: [23:19]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:5;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} lp_uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0;
+         *  This register stores the offset write address in Tx-SRAM.
+         */
+        uint32_t tx_sram_waddr:5;
+        uint32_t reserved_8:4;
+        /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0;
+         *  This register stores the offset read address in Tx-SRAM.
+         */
+        uint32_t tx_sram_raddr:5;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16;
+         *  This register stores the offset read address in RX-SRAM.
+         */
+        uint32_t rx_sram_raddr:5;
+        uint32_t reserved_8:4;
+        /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16;
+         *  This register stores the offset write address in Rx-SRAM.
+         */
+        uint32_t rx_sram_waddr:5;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART AFIFO Status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Full signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Empty signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Full signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Empty signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lp_uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t at_cmd_char:8;
+        /** char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36720720;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} lp_uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART Registers Configuration Update register
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} lp_uart_id_reg_t;
+
+
+typedef struct {
+    volatile lp_uart_fifo_reg_t fifo;
+    volatile lp_uart_int_raw_reg_t int_raw;
+    volatile lp_uart_int_st_reg_t int_st;
+    volatile lp_uart_int_ena_reg_t int_ena;
+    volatile lp_uart_int_clr_reg_t int_clr;
+    volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile lp_uart_rx_filt_reg_t rx_filt;
+    volatile lp_uart_status_reg_t status;
+    volatile lp_uart_conf0_sync_reg_t conf0_sync;
+    volatile lp_uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile lp_uart_sleep_conf0_reg_t sleep_conf0;
+    volatile lp_uart_sleep_conf1_reg_t sleep_conf1;
+    volatile lp_uart_sleep_conf2_reg_t sleep_conf2;
+    volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile lp_uart_swfc_conf1_reg_t swfc_conf1;
+    volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile lp_uart_mem_conf_reg_t mem_conf;
+    volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile lp_uart_mem_tx_status_reg_t mem_tx_status;
+    volatile lp_uart_mem_rx_status_reg_t mem_rx_status;
+    volatile lp_uart_fsm_status_reg_t fsm_status;
+    uint32_t reserved_074[5];
+    volatile lp_uart_clk_conf_reg_t clk_conf;
+    volatile lp_uart_date_reg_t date;
+    volatile lp_uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile lp_uart_reg_update_reg_t reg_update;
+    volatile lp_uart_id_reg_t id;
+} lp_uart_dev_t;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_wdt_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_wdt_reg.h
new file mode 100644
index 0000000000..1c215bdfa3
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_wdt_reg.h
@@ -0,0 +1,324 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_WDT_CONFIG0_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
+/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_PAUSE_IN_SLP    (BIT(9))
+#define LP_WDT_WDT_PAUSE_IN_SLP_M  (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
+#define LP_WDT_WDT_PAUSE_IN_SLP_V  0x00000001U
+#define LP_WDT_WDT_PAUSE_IN_SLP_S  9
+/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_APPCPU_RESET_EN    (BIT(10))
+#define LP_WDT_WDT_APPCPU_RESET_EN_M  (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
+#define LP_WDT_WDT_APPCPU_RESET_EN_V  0x00000001U
+#define LP_WDT_WDT_APPCPU_RESET_EN_S  10
+/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_PROCPU_RESET_EN    (BIT(11))
+#define LP_WDT_WDT_PROCPU_RESET_EN_M  (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
+#define LP_WDT_WDT_PROCPU_RESET_EN_V  0x00000001U
+#define LP_WDT_WDT_PROCPU_RESET_EN_S  11
+/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN    (BIT(12))
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M  (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S  12
+/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_SYS_RESET_LENGTH    0x00000007U
+#define LP_WDT_WDT_SYS_RESET_LENGTH_M  (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
+#define LP_WDT_WDT_SYS_RESET_LENGTH_V  0x00000007U
+#define LP_WDT_WDT_SYS_RESET_LENGTH_S  13
+/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_CPU_RESET_LENGTH    0x00000007U
+#define LP_WDT_WDT_CPU_RESET_LENGTH_M  (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
+#define LP_WDT_WDT_CPU_RESET_LENGTH_V  0x00000007U
+#define LP_WDT_WDT_CPU_RESET_LENGTH_S  16
+/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG3    0x00000007U
+#define LP_WDT_WDT_STG3_M  (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
+#define LP_WDT_WDT_STG3_V  0x00000007U
+#define LP_WDT_WDT_STG3_S  19
+/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG2    0x00000007U
+#define LP_WDT_WDT_STG2_M  (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
+#define LP_WDT_WDT_STG2_V  0x00000007U
+#define LP_WDT_WDT_STG2_S  22
+/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG1    0x00000007U
+#define LP_WDT_WDT_STG1_M  (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
+#define LP_WDT_WDT_STG1_V  0x00000007U
+#define LP_WDT_WDT_STG1_S  25
+/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG0    0x00000007U
+#define LP_WDT_WDT_STG0_M  (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
+#define LP_WDT_WDT_STG0_V  0x00000007U
+#define LP_WDT_WDT_STG0_S  28
+/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_EN    (BIT(31))
+#define LP_WDT_WDT_EN_M  (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
+#define LP_WDT_WDT_EN_V  0x00000001U
+#define LP_WDT_WDT_EN_S  31
+
+/** LP_WDT_CONFIG1_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
+/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG0_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG0_HOLD_M  (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
+#define LP_WDT_WDT_STG0_HOLD_V  0xFFFFFFFFU
+#define LP_WDT_WDT_STG0_HOLD_S  0
+
+/** LP_WDT_CONFIG2_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
+/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG1_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG1_HOLD_M  (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
+#define LP_WDT_WDT_STG1_HOLD_V  0xFFFFFFFFU
+#define LP_WDT_WDT_STG1_HOLD_S  0
+
+/** LP_WDT_CONFIG3_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
+/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG2_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG2_HOLD_M  (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
+#define LP_WDT_WDT_STG2_HOLD_V  0xFFFFFFFFU
+#define LP_WDT_WDT_STG2_HOLD_S  0
+
+/** LP_WDT_CONFIG4_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
+/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG3_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG3_HOLD_M  (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
+#define LP_WDT_WDT_STG3_HOLD_V  0xFFFFFFFFU
+#define LP_WDT_WDT_STG3_HOLD_S  0
+
+/** LP_WDT_FEED_REG register
+ *  need_des
+ */
+#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
+/** LP_WDT_FEED : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_FEED    (BIT(31))
+#define LP_WDT_FEED_M  (LP_WDT_FEED_V << LP_WDT_FEED_S)
+#define LP_WDT_FEED_V  0x00000001U
+#define LP_WDT_FEED_S  31
+
+/** LP_WDT_WPROTECT_REG register
+ *  need_des
+ */
+#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
+/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_WKEY    0xFFFFFFFFU
+#define LP_WDT_WDT_WKEY_M  (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
+#define LP_WDT_WDT_WKEY_V  0xFFFFFFFFU
+#define LP_WDT_WDT_WKEY_S  0
+
+/** LP_WDT_SWD_CONFIG_REG register
+ *  need_des
+ */
+#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
+/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_RESET_FLAG    (BIT(0))
+#define LP_WDT_SWD_RESET_FLAG_M  (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
+#define LP_WDT_SWD_RESET_FLAG_V  0x00000001U
+#define LP_WDT_SWD_RESET_FLAG_S  0
+/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_AUTO_FEED_EN    (BIT(18))
+#define LP_WDT_SWD_AUTO_FEED_EN_M  (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
+#define LP_WDT_SWD_AUTO_FEED_EN_V  0x00000001U
+#define LP_WDT_SWD_AUTO_FEED_EN_S  18
+/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_RST_FLAG_CLR    (BIT(19))
+#define LP_WDT_SWD_RST_FLAG_CLR_M  (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
+#define LP_WDT_SWD_RST_FLAG_CLR_V  0x00000001U
+#define LP_WDT_SWD_RST_FLAG_CLR_S  19
+/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
+ *  need_des
+ */
+#define LP_WDT_SWD_SIGNAL_WIDTH    0x000003FFU
+#define LP_WDT_SWD_SIGNAL_WIDTH_M  (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
+#define LP_WDT_SWD_SIGNAL_WIDTH_V  0x000003FFU
+#define LP_WDT_SWD_SIGNAL_WIDTH_S  20
+/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_DISABLE    (BIT(30))
+#define LP_WDT_SWD_DISABLE_M  (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
+#define LP_WDT_SWD_DISABLE_V  0x00000001U
+#define LP_WDT_SWD_DISABLE_S  30
+/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_FEED    (BIT(31))
+#define LP_WDT_SWD_FEED_M  (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
+#define LP_WDT_SWD_FEED_V  0x00000001U
+#define LP_WDT_SWD_FEED_S  31
+
+/** LP_WDT_SWD_WPROTECT_REG register
+ *  need_des
+ */
+#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
+/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_WKEY    0xFFFFFFFFU
+#define LP_WDT_SWD_WKEY_M  (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
+#define LP_WDT_SWD_WKEY_V  0xFFFFFFFFU
+#define LP_WDT_SWD_WKEY_S  0
+
+/** LP_WDT_INT_RAW_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
+/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_RAW    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_RAW_M  (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
+#define LP_WDT_SUPER_WDT_INT_RAW_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_RAW_S  30
+/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_RAW    (BIT(31))
+#define LP_WDT_LP_WDT_INT_RAW_M  (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
+#define LP_WDT_LP_WDT_INT_RAW_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_RAW_S  31
+
+/** LP_WDT_INT_ST_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
+/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_ST    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_ST_M  (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
+#define LP_WDT_SUPER_WDT_INT_ST_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_ST_S  30
+/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_ST    (BIT(31))
+#define LP_WDT_LP_WDT_INT_ST_M  (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
+#define LP_WDT_LP_WDT_INT_ST_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_ST_S  31
+
+/** LP_WDT_INT_ENA_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
+/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_ENA    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_ENA_M  (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
+#define LP_WDT_SUPER_WDT_INT_ENA_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_ENA_S  30
+/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_ENA    (BIT(31))
+#define LP_WDT_LP_WDT_INT_ENA_M  (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
+#define LP_WDT_LP_WDT_INT_ENA_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_ENA_S  31
+
+/** LP_WDT_INT_CLR_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
+/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_CLR    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_CLR_M  (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
+#define LP_WDT_SUPER_WDT_INT_CLR_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_CLR_S  30
+/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_CLR    (BIT(31))
+#define LP_WDT_LP_WDT_INT_CLR_M  (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
+#define LP_WDT_LP_WDT_INT_CLR_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_CLR_S  31
+
+/** LP_WDT_DATE_REG register
+ *  need_des
+ */
+#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
+/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 35725408;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_DATE    0x7FFFFFFFU
+#define LP_WDT_LP_WDT_DATE_M  (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
+#define LP_WDT_LP_WDT_DATE_V  0x7FFFFFFFU
+#define LP_WDT_LP_WDT_DATE_S  0
+/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_CLK_EN    (BIT(31))
+#define LP_WDT_CLK_EN_M  (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)
+#define LP_WDT_CLK_EN_V  0x00000001U
+#define LP_WDT_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_wdt_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_wdt_struct.h
new file mode 100644
index 0000000000..10cfad4386
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_wdt_struct.h
@@ -0,0 +1,310 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of config0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_pause_in_slp:1;
+        /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_appcpu_reset_en:1;
+        /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_procpu_reset_en:1;
+        /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_flashboot_mod_en:1;
+        /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_sys_reset_length:3;
+        /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_cpu_reset_length:3;
+        /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg3:3;
+        /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg2:3;
+        /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg1:3;
+        /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg0:3;
+        /** wdt_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_en:1;
+    };
+    uint32_t val;
+} rtc_wdt_config0_reg_t;
+
+/** Type of config1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
+         *  need_des
+         */
+        uint32_t wdt_stg0_hold:32;
+    };
+    uint32_t val;
+} rtc_wdt_config1_reg_t;
+
+/** Type of config2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
+         *  need_des
+         */
+        uint32_t wdt_stg1_hold:32;
+    };
+    uint32_t val;
+} rtc_wdt_config2_reg_t;
+
+/** Type of config3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
+         *  need_des
+         */
+        uint32_t wdt_stg2_hold:32;
+    };
+    uint32_t val;
+} rtc_wdt_config3_reg_t;
+
+/** Type of config4 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
+         *  need_des
+         */
+        uint32_t wdt_stg3_hold:32;
+    };
+    uint32_t val;
+} rtc_wdt_config4_reg_t;
+
+/** Type of feed register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** feed : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t feed:1;
+    };
+    uint32_t val;
+} rtc_wdt_feed_reg_t;
+
+/** Type of wprotect register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_wkey:32;
+    };
+    uint32_t val;
+} rtc_wdt_wprotect_reg_t;
+
+/** Type of swd_config register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** swd_reset_flag : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_reset_flag:1;
+        uint32_t reserved_1:17;
+        /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_auto_feed_en:1;
+        /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_rst_flag_clr:1;
+        /** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
+         *  need_des
+         */
+        uint32_t swd_signal_width:10;
+        /** swd_disable : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_disable:1;
+        /** swd_feed : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_feed:1;
+    };
+    uint32_t val;
+} rtc_wdt_swd_config_reg_t;
+
+/** Type of swd_wprotect register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** swd_wkey : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_wkey:32;
+    };
+    uint32_t val;
+} rtc_wdt_swd_wprotect_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_raw:1;
+        /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_raw:1;
+    };
+    uint32_t val;
+} rtc_wdt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_st:1;
+        /** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_st:1;
+    };
+    uint32_t val;
+} rtc_wdt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_ena:1;
+        /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_ena:1;
+    };
+    uint32_t val;
+} rtc_wdt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_clr:1;
+        /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_clr:1;
+    };
+    uint32_t val;
+} rtc_wdt_int_clr_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_wdt_date : R/W; bitpos: [30:0]; default: 35725408;
+         *  need_des
+         */
+        uint32_t lp_wdt_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} rtc_wdt_date_reg_t;
+
+
+typedef struct {
+    volatile rtc_wdt_config0_reg_t config0;
+    volatile rtc_wdt_config1_reg_t config1;
+    volatile rtc_wdt_config2_reg_t config2;
+    volatile rtc_wdt_config3_reg_t config3;
+    volatile rtc_wdt_config4_reg_t config4;
+    volatile rtc_wdt_feed_reg_t feed;
+    volatile rtc_wdt_wprotect_reg_t wprotect;
+    volatile rtc_wdt_swd_config_reg_t swd_config;
+    volatile rtc_wdt_swd_wprotect_reg_t swd_wprotect;
+    volatile rtc_wdt_int_raw_reg_t int_raw;
+    volatile rtc_wdt_int_st_reg_t int_st;
+    volatile rtc_wdt_int_ena_reg_t int_ena;
+    volatile rtc_wdt_int_clr_reg_t int_clr;
+    uint32_t reserved_034[242];
+    volatile rtc_wdt_date_reg_t date;
+} lp_wdt_dev_t;
+
+extern lp_wdt_dev_t LP_WDT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lpperi_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lpperi_reg.h
new file mode 100644
index 0000000000..338134fe92
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lpperi_reg.h
@@ -0,0 +1,470 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LPPERI_CLK_EN_REG register
+ *  need_des
+ */
+#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
+/** LPPERI_CK_EN_RNG : R/W; bitpos: [16]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_RNG    (BIT(16))
+#define LPPERI_CK_EN_RNG_M  (LPPERI_CK_EN_RNG_V << LPPERI_CK_EN_RNG_S)
+#define LPPERI_CK_EN_RNG_V  0x00000001U
+#define LPPERI_CK_EN_RNG_S  16
+/** LPPERI_CK_EN_LP_TSENS : R/W; bitpos: [17]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_TSENS    (BIT(17))
+#define LPPERI_CK_EN_LP_TSENS_M  (LPPERI_CK_EN_LP_TSENS_V << LPPERI_CK_EN_LP_TSENS_S)
+#define LPPERI_CK_EN_LP_TSENS_V  0x00000001U
+#define LPPERI_CK_EN_LP_TSENS_S  17
+/** LPPERI_CK_EN_LP_PMS : R/W; bitpos: [18]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_PMS    (BIT(18))
+#define LPPERI_CK_EN_LP_PMS_M  (LPPERI_CK_EN_LP_PMS_V << LPPERI_CK_EN_LP_PMS_S)
+#define LPPERI_CK_EN_LP_PMS_V  0x00000001U
+#define LPPERI_CK_EN_LP_PMS_S  18
+/** LPPERI_CK_EN_LP_EFUSE : R/W; bitpos: [19]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_EFUSE    (BIT(19))
+#define LPPERI_CK_EN_LP_EFUSE_M  (LPPERI_CK_EN_LP_EFUSE_V << LPPERI_CK_EN_LP_EFUSE_S)
+#define LPPERI_CK_EN_LP_EFUSE_V  0x00000001U
+#define LPPERI_CK_EN_LP_EFUSE_S  19
+/** LPPERI_CK_EN_LP_IOMUX : R/W; bitpos: [20]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_IOMUX    (BIT(20))
+#define LPPERI_CK_EN_LP_IOMUX_M  (LPPERI_CK_EN_LP_IOMUX_V << LPPERI_CK_EN_LP_IOMUX_S)
+#define LPPERI_CK_EN_LP_IOMUX_V  0x00000001U
+#define LPPERI_CK_EN_LP_IOMUX_S  20
+/** LPPERI_CK_EN_LP_TOUCH : R/W; bitpos: [21]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_TOUCH    (BIT(21))
+#define LPPERI_CK_EN_LP_TOUCH_M  (LPPERI_CK_EN_LP_TOUCH_V << LPPERI_CK_EN_LP_TOUCH_S)
+#define LPPERI_CK_EN_LP_TOUCH_V  0x00000001U
+#define LPPERI_CK_EN_LP_TOUCH_S  21
+/** LPPERI_CK_EN_LP_SPI : R/W; bitpos: [22]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_SPI    (BIT(22))
+#define LPPERI_CK_EN_LP_SPI_M  (LPPERI_CK_EN_LP_SPI_V << LPPERI_CK_EN_LP_SPI_S)
+#define LPPERI_CK_EN_LP_SPI_V  0x00000001U
+#define LPPERI_CK_EN_LP_SPI_S  22
+/** LPPERI_CK_EN_LP_ADC : R/W; bitpos: [23]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_ADC    (BIT(23))
+#define LPPERI_CK_EN_LP_ADC_M  (LPPERI_CK_EN_LP_ADC_V << LPPERI_CK_EN_LP_ADC_S)
+#define LPPERI_CK_EN_LP_ADC_V  0x00000001U
+#define LPPERI_CK_EN_LP_ADC_S  23
+/** LPPERI_CK_EN_LP_I2S_TX : R/W; bitpos: [24]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_I2S_TX    (BIT(24))
+#define LPPERI_CK_EN_LP_I2S_TX_M  (LPPERI_CK_EN_LP_I2S_TX_V << LPPERI_CK_EN_LP_I2S_TX_S)
+#define LPPERI_CK_EN_LP_I2S_TX_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2S_TX_S  24
+/** LPPERI_CK_EN_LP_I2S_RX : R/W; bitpos: [25]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_I2S_RX    (BIT(25))
+#define LPPERI_CK_EN_LP_I2S_RX_M  (LPPERI_CK_EN_LP_I2S_RX_V << LPPERI_CK_EN_LP_I2S_RX_S)
+#define LPPERI_CK_EN_LP_I2S_RX_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2S_RX_S  25
+/** LPPERI_CK_EN_LP_I2S : R/W; bitpos: [26]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_I2S    (BIT(26))
+#define LPPERI_CK_EN_LP_I2S_M  (LPPERI_CK_EN_LP_I2S_V << LPPERI_CK_EN_LP_I2S_S)
+#define LPPERI_CK_EN_LP_I2S_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2S_S  26
+/** LPPERI_CK_EN_LP_I2CMST : R/W; bitpos: [27]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_I2CMST    (BIT(27))
+#define LPPERI_CK_EN_LP_I2CMST_M  (LPPERI_CK_EN_LP_I2CMST_V << LPPERI_CK_EN_LP_I2CMST_S)
+#define LPPERI_CK_EN_LP_I2CMST_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2CMST_S  27
+/** LPPERI_CK_EN_LP_I2C : R/W; bitpos: [28]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_I2C    (BIT(28))
+#define LPPERI_CK_EN_LP_I2C_M  (LPPERI_CK_EN_LP_I2C_V << LPPERI_CK_EN_LP_I2C_S)
+#define LPPERI_CK_EN_LP_I2C_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2C_S  28
+/** LPPERI_CK_EN_LP_UART : R/W; bitpos: [29]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_UART    (BIT(29))
+#define LPPERI_CK_EN_LP_UART_M  (LPPERI_CK_EN_LP_UART_V << LPPERI_CK_EN_LP_UART_S)
+#define LPPERI_CK_EN_LP_UART_V  0x00000001U
+#define LPPERI_CK_EN_LP_UART_S  29
+/** LPPERI_CK_EN_LP_INTR : R/W; bitpos: [30]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_INTR    (BIT(30))
+#define LPPERI_CK_EN_LP_INTR_M  (LPPERI_CK_EN_LP_INTR_V << LPPERI_CK_EN_LP_INTR_S)
+#define LPPERI_CK_EN_LP_INTR_V  0x00000001U
+#define LPPERI_CK_EN_LP_INTR_S  30
+/** LPPERI_CK_EN_LP_CORE : R/W; bitpos: [31]; default: 0;
+ *  write 1 to force on lp_core clk
+ */
+#define LPPERI_CK_EN_LP_CORE    (BIT(31))
+#define LPPERI_CK_EN_LP_CORE_M  (LPPERI_CK_EN_LP_CORE_V << LPPERI_CK_EN_LP_CORE_S)
+#define LPPERI_CK_EN_LP_CORE_V  0x00000001U
+#define LPPERI_CK_EN_LP_CORE_S  31
+
+/** LPPERI_CORE_CLK_SEL_REG register
+ *  need_des
+ */
+#define LPPERI_CORE_CLK_SEL_REG (DR_REG_LPPERI_BASE + 0x4)
+/** LPPERI_LP_I2S_TX_CLK_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLK_SEL    0x00000003U
+#define LPPERI_LP_I2S_TX_CLK_SEL_M  (LPPERI_LP_I2S_TX_CLK_SEL_V << LPPERI_LP_I2S_TX_CLK_SEL_S)
+#define LPPERI_LP_I2S_TX_CLK_SEL_V  0x00000003U
+#define LPPERI_LP_I2S_TX_CLK_SEL_S  24
+/** LPPERI_LP_I2S_RX_CLK_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLK_SEL    0x00000003U
+#define LPPERI_LP_I2S_RX_CLK_SEL_M  (LPPERI_LP_I2S_RX_CLK_SEL_V << LPPERI_LP_I2S_RX_CLK_SEL_S)
+#define LPPERI_LP_I2S_RX_CLK_SEL_V  0x00000003U
+#define LPPERI_LP_I2S_RX_CLK_SEL_S  26
+/** LPPERI_LP_I2C_CLK_SEL : R/W; bitpos: [29:28]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2C_CLK_SEL    0x00000003U
+#define LPPERI_LP_I2C_CLK_SEL_M  (LPPERI_LP_I2C_CLK_SEL_V << LPPERI_LP_I2C_CLK_SEL_S)
+#define LPPERI_LP_I2C_CLK_SEL_V  0x00000003U
+#define LPPERI_LP_I2C_CLK_SEL_S  28
+/** LPPERI_LP_UART_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_UART_CLK_SEL    0x00000003U
+#define LPPERI_LP_UART_CLK_SEL_M  (LPPERI_LP_UART_CLK_SEL_V << LPPERI_LP_UART_CLK_SEL_S)
+#define LPPERI_LP_UART_CLK_SEL_V  0x00000003U
+#define LPPERI_LP_UART_CLK_SEL_S  30
+
+/** LPPERI_RESET_EN_REG register
+ *  need_des
+ */
+#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x8)
+/** LPPERI_RST_EN_LP_RNG : R/W; bitpos: [17]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_RNG    (BIT(17))
+#define LPPERI_RST_EN_LP_RNG_M  (LPPERI_RST_EN_LP_RNG_V << LPPERI_RST_EN_LP_RNG_S)
+#define LPPERI_RST_EN_LP_RNG_V  0x00000001U
+#define LPPERI_RST_EN_LP_RNG_S  17
+/** LPPERI_RST_EN_LP_TSENS : R/W; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_TSENS    (BIT(18))
+#define LPPERI_RST_EN_LP_TSENS_M  (LPPERI_RST_EN_LP_TSENS_V << LPPERI_RST_EN_LP_TSENS_S)
+#define LPPERI_RST_EN_LP_TSENS_V  0x00000001U
+#define LPPERI_RST_EN_LP_TSENS_S  18
+/** LPPERI_RST_EN_LP_PMS : R/W; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_PMS    (BIT(19))
+#define LPPERI_RST_EN_LP_PMS_M  (LPPERI_RST_EN_LP_PMS_V << LPPERI_RST_EN_LP_PMS_S)
+#define LPPERI_RST_EN_LP_PMS_V  0x00000001U
+#define LPPERI_RST_EN_LP_PMS_S  19
+/** LPPERI_RST_EN_LP_EFUSE : R/W; bitpos: [20]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_EFUSE    (BIT(20))
+#define LPPERI_RST_EN_LP_EFUSE_M  (LPPERI_RST_EN_LP_EFUSE_V << LPPERI_RST_EN_LP_EFUSE_S)
+#define LPPERI_RST_EN_LP_EFUSE_V  0x00000001U
+#define LPPERI_RST_EN_LP_EFUSE_S  20
+/** LPPERI_RST_EN_LP_IOMUX : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_IOMUX    (BIT(21))
+#define LPPERI_RST_EN_LP_IOMUX_M  (LPPERI_RST_EN_LP_IOMUX_V << LPPERI_RST_EN_LP_IOMUX_S)
+#define LPPERI_RST_EN_LP_IOMUX_V  0x00000001U
+#define LPPERI_RST_EN_LP_IOMUX_S  21
+/** LPPERI_RST_EN_LP_TOUCH : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_TOUCH    (BIT(22))
+#define LPPERI_RST_EN_LP_TOUCH_M  (LPPERI_RST_EN_LP_TOUCH_V << LPPERI_RST_EN_LP_TOUCH_S)
+#define LPPERI_RST_EN_LP_TOUCH_V  0x00000001U
+#define LPPERI_RST_EN_LP_TOUCH_S  22
+/** LPPERI_RST_EN_LP_SPI : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_SPI    (BIT(23))
+#define LPPERI_RST_EN_LP_SPI_M  (LPPERI_RST_EN_LP_SPI_V << LPPERI_RST_EN_LP_SPI_S)
+#define LPPERI_RST_EN_LP_SPI_V  0x00000001U
+#define LPPERI_RST_EN_LP_SPI_S  23
+/** LPPERI_RST_EN_LP_ADC : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_ADC    (BIT(24))
+#define LPPERI_RST_EN_LP_ADC_M  (LPPERI_RST_EN_LP_ADC_V << LPPERI_RST_EN_LP_ADC_S)
+#define LPPERI_RST_EN_LP_ADC_V  0x00000001U
+#define LPPERI_RST_EN_LP_ADC_S  24
+/** LPPERI_RST_EN_LP_I2S : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_I2S    (BIT(25))
+#define LPPERI_RST_EN_LP_I2S_M  (LPPERI_RST_EN_LP_I2S_V << LPPERI_RST_EN_LP_I2S_S)
+#define LPPERI_RST_EN_LP_I2S_V  0x00000001U
+#define LPPERI_RST_EN_LP_I2S_S  25
+/** LPPERI_RST_EN_LP_I2CMST : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_I2CMST    (BIT(26))
+#define LPPERI_RST_EN_LP_I2CMST_M  (LPPERI_RST_EN_LP_I2CMST_V << LPPERI_RST_EN_LP_I2CMST_S)
+#define LPPERI_RST_EN_LP_I2CMST_V  0x00000001U
+#define LPPERI_RST_EN_LP_I2CMST_S  26
+/** LPPERI_RST_EN_LP_I2C : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_I2C    (BIT(27))
+#define LPPERI_RST_EN_LP_I2C_M  (LPPERI_RST_EN_LP_I2C_V << LPPERI_RST_EN_LP_I2C_S)
+#define LPPERI_RST_EN_LP_I2C_V  0x00000001U
+#define LPPERI_RST_EN_LP_I2C_S  27
+/** LPPERI_RST_EN_LP_UART : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_UART    (BIT(28))
+#define LPPERI_RST_EN_LP_UART_M  (LPPERI_RST_EN_LP_UART_V << LPPERI_RST_EN_LP_UART_S)
+#define LPPERI_RST_EN_LP_UART_V  0x00000001U
+#define LPPERI_RST_EN_LP_UART_S  28
+/** LPPERI_RST_EN_LP_INTR : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_INTR    (BIT(29))
+#define LPPERI_RST_EN_LP_INTR_M  (LPPERI_RST_EN_LP_INTR_V << LPPERI_RST_EN_LP_INTR_S)
+#define LPPERI_RST_EN_LP_INTR_V  0x00000001U
+#define LPPERI_RST_EN_LP_INTR_S  29
+/** LPPERI_RST_EN_LP_ROM : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_ROM    (BIT(30))
+#define LPPERI_RST_EN_LP_ROM_M  (LPPERI_RST_EN_LP_ROM_V << LPPERI_RST_EN_LP_ROM_S)
+#define LPPERI_RST_EN_LP_ROM_V  0x00000001U
+#define LPPERI_RST_EN_LP_ROM_S  30
+/** LPPERI_RST_EN_LP_CORE : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_CORE    (BIT(31))
+#define LPPERI_RST_EN_LP_CORE_M  (LPPERI_RST_EN_LP_CORE_V << LPPERI_RST_EN_LP_CORE_S)
+#define LPPERI_RST_EN_LP_CORE_V  0x00000001U
+#define LPPERI_RST_EN_LP_CORE_S  31
+
+/** LPPERI_CPU_REG register
+ *  need_des
+ */
+#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
+/** LPPERI_LPCORE_DBGM_UNAVAILABLE : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define LPPERI_LPCORE_DBGM_UNAVAILABLE    (BIT(31))
+#define LPPERI_LPCORE_DBGM_UNAVAILABLE_M  (LPPERI_LPCORE_DBGM_UNAVAILABLE_V << LPPERI_LPCORE_DBGM_UNAVAILABLE_S)
+#define LPPERI_LPCORE_DBGM_UNAVAILABLE_V  0x00000001U
+#define LPPERI_LPCORE_DBGM_UNAVAILABLE_S  31
+
+/** LPPERI_MEM_CTRL_REG register
+ *  need_des
+ */
+#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x28)
+/** LPPERI_LP_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_UART_WAKEUP_FLAG_CLR    (BIT(0))
+#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_M  (LPPERI_LP_UART_WAKEUP_FLAG_CLR_V << LPPERI_LP_UART_WAKEUP_FLAG_CLR_S)
+#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_V  0x00000001U
+#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_S  0
+/** LPPERI_LP_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_UART_WAKEUP_FLAG    (BIT(1))
+#define LPPERI_LP_UART_WAKEUP_FLAG_M  (LPPERI_LP_UART_WAKEUP_FLAG_V << LPPERI_LP_UART_WAKEUP_FLAG_S)
+#define LPPERI_LP_UART_WAKEUP_FLAG_V  0x00000001U
+#define LPPERI_LP_UART_WAKEUP_FLAG_S  1
+/** LPPERI_LP_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_UART_WAKEUP_EN    (BIT(29))
+#define LPPERI_LP_UART_WAKEUP_EN_M  (LPPERI_LP_UART_WAKEUP_EN_V << LPPERI_LP_UART_WAKEUP_EN_S)
+#define LPPERI_LP_UART_WAKEUP_EN_V  0x00000001U
+#define LPPERI_LP_UART_WAKEUP_EN_S  29
+/** LPPERI_LP_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_UART_MEM_FORCE_PD    (BIT(30))
+#define LPPERI_LP_UART_MEM_FORCE_PD_M  (LPPERI_LP_UART_MEM_FORCE_PD_V << LPPERI_LP_UART_MEM_FORCE_PD_S)
+#define LPPERI_LP_UART_MEM_FORCE_PD_V  0x00000001U
+#define LPPERI_LP_UART_MEM_FORCE_PD_S  30
+/** LPPERI_LP_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define LPPERI_LP_UART_MEM_FORCE_PU    (BIT(31))
+#define LPPERI_LP_UART_MEM_FORCE_PU_M  (LPPERI_LP_UART_MEM_FORCE_PU_V << LPPERI_LP_UART_MEM_FORCE_PU_S)
+#define LPPERI_LP_UART_MEM_FORCE_PU_V  0x00000001U
+#define LPPERI_LP_UART_MEM_FORCE_PU_S  31
+
+/** LPPERI_ADC_CTRL_REG register
+ *  need_des
+ */
+#define LPPERI_ADC_CTRL_REG (DR_REG_LPPERI_BASE + 0x2c)
+/** LPPERI_SAR2_CLK_FORCE_ON : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LPPERI_SAR2_CLK_FORCE_ON    (BIT(6))
+#define LPPERI_SAR2_CLK_FORCE_ON_M  (LPPERI_SAR2_CLK_FORCE_ON_V << LPPERI_SAR2_CLK_FORCE_ON_S)
+#define LPPERI_SAR2_CLK_FORCE_ON_V  0x00000001U
+#define LPPERI_SAR2_CLK_FORCE_ON_S  6
+/** LPPERI_SAR1_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define LPPERI_SAR1_CLK_FORCE_ON    (BIT(7))
+#define LPPERI_SAR1_CLK_FORCE_ON_M  (LPPERI_SAR1_CLK_FORCE_ON_V << LPPERI_SAR1_CLK_FORCE_ON_S)
+#define LPPERI_SAR1_CLK_FORCE_ON_V  0x00000001U
+#define LPPERI_SAR1_CLK_FORCE_ON_S  7
+/** LPPERI_LPADC_FUNC_DIV_NUM : R/W; bitpos: [15:8]; default: 4;
+ *  need_des
+ */
+#define LPPERI_LPADC_FUNC_DIV_NUM    0x000000FFU
+#define LPPERI_LPADC_FUNC_DIV_NUM_M  (LPPERI_LPADC_FUNC_DIV_NUM_V << LPPERI_LPADC_FUNC_DIV_NUM_S)
+#define LPPERI_LPADC_FUNC_DIV_NUM_V  0x000000FFU
+#define LPPERI_LPADC_FUNC_DIV_NUM_S  8
+/** LPPERI_LPADC_SAR2_DIV_NUM : R/W; bitpos: [23:16]; default: 4;
+ *  need_des
+ */
+#define LPPERI_LPADC_SAR2_DIV_NUM    0x000000FFU
+#define LPPERI_LPADC_SAR2_DIV_NUM_M  (LPPERI_LPADC_SAR2_DIV_NUM_V << LPPERI_LPADC_SAR2_DIV_NUM_S)
+#define LPPERI_LPADC_SAR2_DIV_NUM_V  0x000000FFU
+#define LPPERI_LPADC_SAR2_DIV_NUM_S  16
+/** LPPERI_LPADC_SAR1_DIV_NUM : R/W; bitpos: [31:24]; default: 4;
+ *  need_des
+ */
+#define LPPERI_LPADC_SAR1_DIV_NUM    0x000000FFU
+#define LPPERI_LPADC_SAR1_DIV_NUM_M  (LPPERI_LPADC_SAR1_DIV_NUM_V << LPPERI_LPADC_SAR1_DIV_NUM_S)
+#define LPPERI_LPADC_SAR1_DIV_NUM_V  0x000000FFU
+#define LPPERI_LPADC_SAR1_DIV_NUM_S  24
+
+/** LPPERI_LP_I2S_RXCLK_DIV_NUM_REG register
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RXCLK_DIV_NUM_REG (DR_REG_LPPERI_BASE + 0x30)
+/** LPPERI_LP_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [31:24]; default: 2;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM    0x000000FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_M  (LPPERI_LP_I2S_RX_CLKM_DIV_NUM_V << LPPERI_LP_I2S_RX_CLKM_DIV_NUM_S)
+#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_S  24
+
+/** LPPERI_LP_I2S_RXCLK_DIV_XYZ_REG register
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RXCLK_DIV_XYZ_REG (DR_REG_LPPERI_BASE + 0x34)
+/** LPPERI_LP_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1    (BIT(4))
+#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_M  (LPPERI_LP_I2S_RX_CLKM_DIV_YN1_V << LPPERI_LP_I2S_RX_CLKM_DIV_YN1_S)
+#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_V  0x00000001U
+#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_S  4
+/** LPPERI_LP_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [13:5]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Z    0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_M  (LPPERI_LP_I2S_RX_CLKM_DIV_Z_V << LPPERI_LP_I2S_RX_CLKM_DIV_Z_S)
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_V  0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_S  5
+/** LPPERI_LP_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [22:14]; default: 1;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Y    0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_M  (LPPERI_LP_I2S_RX_CLKM_DIV_Y_V << LPPERI_LP_I2S_RX_CLKM_DIV_Y_S)
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_V  0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_S  14
+/** LPPERI_LP_I2S_RX_CLKM_DIV_X : R/W; bitpos: [31:23]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLKM_DIV_X    0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_X_M  (LPPERI_LP_I2S_RX_CLKM_DIV_X_V << LPPERI_LP_I2S_RX_CLKM_DIV_X_S)
+#define LPPERI_LP_I2S_RX_CLKM_DIV_X_V  0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_X_S  23
+
+/** LPPERI_LP_I2S_TXCLK_DIV_NUM_REG register
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TXCLK_DIV_NUM_REG (DR_REG_LPPERI_BASE + 0x38)
+/** LPPERI_LP_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [31:24]; default: 2;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM    0x000000FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_M  (LPPERI_LP_I2S_TX_CLKM_DIV_NUM_V << LPPERI_LP_I2S_TX_CLKM_DIV_NUM_S)
+#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_S  24
+
+/** LPPERI_LP_I2S_TXCLK_DIV_XYZ_REG register
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TXCLK_DIV_XYZ_REG (DR_REG_LPPERI_BASE + 0x3c)
+/** LPPERI_LP_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1    (BIT(4))
+#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_M  (LPPERI_LP_I2S_TX_CLKM_DIV_YN1_V << LPPERI_LP_I2S_TX_CLKM_DIV_YN1_S)
+#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_V  0x00000001U
+#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_S  4
+/** LPPERI_LP_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [13:5]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Z    0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_M  (LPPERI_LP_I2S_TX_CLKM_DIV_Z_V << LPPERI_LP_I2S_TX_CLKM_DIV_Z_S)
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_V  0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_S  5
+/** LPPERI_LP_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [22:14]; default: 1;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Y    0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_M  (LPPERI_LP_I2S_TX_CLKM_DIV_Y_V << LPPERI_LP_I2S_TX_CLKM_DIV_Y_S)
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_V  0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_S  14
+/** LPPERI_LP_I2S_TX_CLKM_DIV_X : R/W; bitpos: [31:23]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLKM_DIV_X    0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_X_M  (LPPERI_LP_I2S_TX_CLKM_DIV_X_V << LPPERI_LP_I2S_TX_CLKM_DIV_X_S)
+#define LPPERI_LP_I2S_TX_CLKM_DIV_X_V  0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_X_S  23
+
+/** LPPERI_DATE_REG register
+ *  need_des
+ */
+#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
+/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPPERI_CLK_EN    (BIT(31))
+#define LPPERI_CLK_EN_M  (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
+#define LPPERI_CLK_EN_V  0x00000001U
+#define LPPERI_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lpperi_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lpperi_struct.h
new file mode 100644
index 0000000000..98148b4e55
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lpperi_struct.h
@@ -0,0 +1,379 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of clk_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** ck_en_rng : R/W; bitpos: [16]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_rng:1;
+        /** ck_en_lp_tsens : R/W; bitpos: [17]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_tsens:1;
+        /** ck_en_lp_pms : R/W; bitpos: [18]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_pms:1;
+        /** ck_en_lp_efuse : R/W; bitpos: [19]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_efuse:1;
+        /** ck_en_lp_iomux : R/W; bitpos: [20]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_iomux:1;
+        /** ck_en_lp_touch : R/W; bitpos: [21]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_touch:1;
+        /** ck_en_lp_spi : R/W; bitpos: [22]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_spi:1;
+        /** ck_en_lp_adc : R/W; bitpos: [23]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_adc:1;
+        /** ck_en_lp_i2s_tx : R/W; bitpos: [24]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_i2s_tx:1;
+        /** ck_en_lp_i2s_rx : R/W; bitpos: [25]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_i2s_rx:1;
+        /** ck_en_lp_i2s : R/W; bitpos: [26]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_i2s:1;
+        /** ck_en_lp_i2cmst : R/W; bitpos: [27]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_i2cmst:1;
+        /** ck_en_lp_i2c : R/W; bitpos: [28]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_i2c:1;
+        /** ck_en_lp_uart : R/W; bitpos: [29]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_uart:1;
+        /** ck_en_lp_intr : R/W; bitpos: [30]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_intr:1;
+        /** ck_en_lp_core : R/W; bitpos: [31]; default: 0;
+         *  write 1 to force on lp_core clk
+         */
+        uint32_t ck_en_lp_core:1;
+    };
+    uint32_t val;
+} lpperi_clk_en_reg_t;
+
+/** Type of core_clk_sel register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** lp_i2s_tx_clk_sel : R/W; bitpos: [25:24]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clk_sel:2;
+        /** lp_i2s_rx_clk_sel : R/W; bitpos: [27:26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clk_sel:2;
+        /** lp_i2c_clk_sel : R/W; bitpos: [29:28]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2c_clk_sel:2;
+        /** lp_uart_clk_sel : R/W; bitpos: [31:30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_clk_sel:2;
+    };
+    uint32_t val;
+} lpperi_core_clk_sel_reg_t;
+
+/** Type of reset_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:17;
+        /** rst_en_lp_rng : R/W; bitpos: [17]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_rng:1;
+        /** rst_en_lp_tsens : R/W; bitpos: [18]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_tsens:1;
+        /** rst_en_lp_pms : R/W; bitpos: [19]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_pms:1;
+        /** rst_en_lp_efuse : R/W; bitpos: [20]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_efuse:1;
+        /** rst_en_lp_iomux : R/W; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_iomux:1;
+        /** rst_en_lp_touch : R/W; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_touch:1;
+        /** rst_en_lp_spi : R/W; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_spi:1;
+        /** rst_en_lp_adc : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_adc:1;
+        /** rst_en_lp_i2s : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_i2s:1;
+        /** rst_en_lp_i2cmst : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_i2cmst:1;
+        /** rst_en_lp_i2c : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_i2c:1;
+        /** rst_en_lp_uart : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_uart:1;
+        /** rst_en_lp_intr : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_intr:1;
+        /** rst_en_lp_rom : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_rom:1;
+        /** rst_en_lp_core : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_core:1;
+    };
+    uint32_t val;
+} lpperi_reset_en_reg_t;
+
+/** Type of cpu register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lpcore_dbgm_unavailable : R/W; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t lpcore_dbgm_unavailable:1;
+    };
+    uint32_t val;
+} lpperi_cpu_reg_t;
+
+/** Type of mem_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_wakeup_flag_clr:1;
+        /** lp_uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_wakeup_flag:1;
+        uint32_t reserved_2:27;
+        /** lp_uart_wakeup_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_wakeup_en:1;
+        /** lp_uart_mem_force_pd : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_mem_force_pd:1;
+        /** lp_uart_mem_force_pu : R/W; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_uart_mem_force_pu:1;
+    };
+    uint32_t val;
+} lpperi_mem_ctrl_reg_t;
+
+/** Type of adc_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** sar2_clk_force_on : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_clk_force_on:1;
+        /** sar1_clk_force_on : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_clk_force_on:1;
+        /** lpadc_func_div_num : R/W; bitpos: [15:8]; default: 4;
+         *  need_des
+         */
+        uint32_t lpadc_func_div_num:8;
+        /** lpadc_sar2_div_num : R/W; bitpos: [23:16]; default: 4;
+         *  need_des
+         */
+        uint32_t lpadc_sar2_div_num:8;
+        /** lpadc_sar1_div_num : R/W; bitpos: [31:24]; default: 4;
+         *  need_des
+         */
+        uint32_t lpadc_sar1_div_num:8;
+    };
+    uint32_t val;
+} lpperi_adc_ctrl_reg_t;
+
+/** Type of lp_i2s_rxclk_div_num register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** lp_i2s_rx_clkm_div_num : R/W; bitpos: [31:24]; default: 2;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clkm_div_num:8;
+    };
+    uint32_t val;
+} lpperi_lp_i2s_rxclk_div_num_reg_t;
+
+/** Type of lp_i2s_rxclk_div_xyz register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** lp_i2s_rx_clkm_div_yn1 : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clkm_div_yn1:1;
+        /** lp_i2s_rx_clkm_div_z : R/W; bitpos: [13:5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clkm_div_z:9;
+        /** lp_i2s_rx_clkm_div_y : R/W; bitpos: [22:14]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clkm_div_y:9;
+        /** lp_i2s_rx_clkm_div_x : R/W; bitpos: [31:23]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clkm_div_x:9;
+    };
+    uint32_t val;
+} lpperi_lp_i2s_rxclk_div_xyz_reg_t;
+
+/** Type of lp_i2s_txclk_div_num register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** lp_i2s_tx_clkm_div_num : R/W; bitpos: [31:24]; default: 2;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clkm_div_num:8;
+    };
+    uint32_t val;
+} lpperi_lp_i2s_txclk_div_num_reg_t;
+
+/** Type of lp_i2s_txclk_div_xyz register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** lp_i2s_tx_clkm_div_yn1 : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clkm_div_yn1:1;
+        /** lp_i2s_tx_clkm_div_z : R/W; bitpos: [13:5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clkm_div_z:9;
+        /** lp_i2s_tx_clkm_div_y : R/W; bitpos: [22:14]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clkm_div_y:9;
+        /** lp_i2s_tx_clkm_div_x : R/W; bitpos: [31:23]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clkm_div_x:9;
+    };
+    uint32_t val;
+} lpperi_lp_i2s_txclk_div_xyz_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lpperi_date_reg_t;
+
+
+typedef struct {
+    volatile lpperi_clk_en_reg_t clk_en;
+    volatile lpperi_core_clk_sel_reg_t core_clk_sel;
+    volatile lpperi_reset_en_reg_t reset_en;
+    volatile lpperi_cpu_reg_t cpu;
+    uint32_t reserved_010[6];
+    volatile lpperi_mem_ctrl_reg_t mem_ctrl;
+    volatile lpperi_adc_ctrl_reg_t adc_ctrl;
+    volatile lpperi_lp_i2s_rxclk_div_num_reg_t lp_i2s_rxclk_div_num;
+    volatile lpperi_lp_i2s_rxclk_div_xyz_reg_t lp_i2s_rxclk_div_xyz;
+    volatile lpperi_lp_i2s_txclk_div_num_reg_t lp_i2s_txclk_div_num;
+    volatile lpperi_lp_i2s_txclk_div_xyz_reg_t lp_i2s_txclk_div_xyz;
+    uint32_t reserved_040[239];
+    volatile lpperi_date_reg_t date;
+} lpperi_dev_t;
+
+extern lpperi_dev_t LPPERI;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_eco5_struct.h
new file mode 100644
index 0000000000..2ee5ebb57c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_eco5_struct.h
@@ -0,0 +1,2347 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration register */
+/** Type of clk_cfg register
+ *  PWM clock prescaler register.
+ */
+typedef union {
+    struct {
+        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
+         *  (PWM_CLK_PRESCALE + 1).
+         */
+        uint32_t clk_prescale:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_clk_cfg_reg_t;
+
+/** Type of timern_cfg0 register
+ *  PWM timern period and update method configuration register.
+ */
+typedef union {
+    struct {
+        /** timern_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the prescaler value of timern, so that the period of PT0_clk = Period of
+         *  PWM_clk * (PWM_TIMERn_PRESCALE + 1)
+         */
+        uint32_t timern_prescale:8;
+        /** timern_period : R/W; bitpos: [23:8]; default: 255;
+         *  Configures the period shadow of PWM timern
+         */
+        uint32_t timern_period:16;
+        /** timern_period_upmethod : R/W; bitpos: [25:24]; default: 0;
+         *  Configures the update method for active register of PWM timern period.
+         *  0: Immediate
+         *  1: TEZ
+         *  2: Sync
+         *  3: TEZ or sync
+         *  TEZ here and below means timer equal zero event
+         */
+        uint32_t timern_period_upmethod:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} mcpwm_timern_cfg0_reg_t;
+
+/** Type of timern_cfg1 register
+ *  PWM timern working mode and start/stop control register.
+ */
+typedef union {
+    struct {
+        /** timern_start : R/W/SC; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to start/stop PWM timern.
+         *  0: If PWM timern starts, then stops at TEZ
+         *  1: If timern starts, then stops at TEP
+         *  2: PWM timern starts and runs on
+         *  3: Timern starts and stops at the next TEZ
+         *  4: Timer0 starts and stops at the next TEP.
+         *  TEP here and below means the event that happens when the timer equals to period
+         */
+        uint32_t timern_start:3;
+        /** timern_mod : R/W; bitpos: [4:3]; default: 0;
+         *  Configures the working mode of PWM timern.
+         *  0: Freeze
+         *  1: Increase mode
+         *  2: Decrease mode
+         *  3: Up-down mode
+         */
+        uint32_t timern_mod:2;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_timern_cfg1_reg_t;
+
+/** Type of timern_sync register
+ *  PWM timern sync function configuration register.
+ */
+typedef union {
+    struct {
+        /** timern_synci_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable timern reloading with phase on sync input event
+         *  is enabled.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t timern_synci_en:1;
+        /** timern_sync_sw : R/W; bitpos: [1]; default: 0;
+         *  Configures the generation of software sync. Toggling this bit will trigger a
+         *  software sync.
+         */
+        uint32_t timern_sync_sw:1;
+        /** timern_synco_sel : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the selection of PWM timern sync_out.
+         *  0: Sync_in
+         *  1: TEZ
+         *  2: TEP
+         *  3: Invalid, sync_out selects noting
+         */
+        uint32_t timern_synco_sel:2;
+        /** timern_phase : R/W; bitpos: [19:4]; default: 0;
+         *  Configures the phase for timern reload on sync event.
+         */
+        uint32_t timern_phase:16;
+        /** timern_phase_direction : R/W; bitpos: [20]; default: 0;
+         *  Configures the PWM timern's direction when timern mode is up-down mode.
+         *  0: Increase
+         *  1: Decrease
+         */
+        uint32_t timern_phase_direction:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} mcpwm_timern_sync_reg_t;
+
+/** Type of timer_synci_cfg register
+ *  Synchronization input selection register for PWM timers.
+ */
+typedef union {
+    struct {
+        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the selection of sync input for PWM timer0.
+         *  1: PWM timer0 sync_out
+         *  2: PWM timer1 sync_out
+         *  3: PWM timer2 sync_out
+         *  4: SYNC0 from GPIO matrix
+         *  5: SYNC1 from GPIO matrix
+         *  6: SYNC2 from GPIO matrix
+         *  Other values: No sync input selected
+         */
+        uint32_t timer0_syncisel:3;
+        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
+         *  Configures the selection of sync input for PWM timer1.
+         *  1: PWM timer0 sync_out
+         *  2: PWM timer1 sync_out
+         *  3: PWM timer2 sync_out
+         *  4: SYNC0 from GPIO matrix
+         *  5: SYNC1 from GPIO matrix
+         *  6: SYNC2 from GPIO matrix
+         *  Other values: No sync input selected
+         */
+        uint32_t timer1_syncisel:3;
+        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures the selection of sync input for PWM timer2.
+         *  1: PWM timer0 sync_out
+         *  2: PWM timer1 sync_out
+         *  3: PWM timer2 sync_out
+         *  4: SYNC0 from GPIO matrix
+         *  5: SYNC1 from GPIO matrix
+         *  6: SYNC2 from GPIO matrix
+         *  Other values: No sync input selected
+         */
+        uint32_t timer2_syncisel:3;
+        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to invert SYNC0 from GPIO matrix.
+         *  0: Not invert
+         *  1: Invert
+         */
+        uint32_t external_synci0_invert:1;
+        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to invert SYNC1 from GPIO matrix.
+         *  0: Not invert
+         *  1: Invert
+         */
+        uint32_t external_synci1_invert:1;
+        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert SYNC2 from GPIO matrix.
+         *  0: Not invert
+         *  1: Invert
+         */
+        uint32_t external_synci2_invert:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} mcpwm_timer_synci_cfg_reg_t;
+
+/** Type of operator_timersel register
+ *  PWM operator's timer select register
+ */
+typedef union {
+    struct {
+        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator0.
+         *  0: Timer0
+         *  1: Timer1
+         *  2: Timer2
+         *  3: Invalid, will select timer2
+         */
+        uint32_t operator0_timersel:2;
+        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator1.
+         *  0: Timer0
+         *  1: Timer1
+         *  2: Timer2
+         *  3: Invalid, will select timer2
+         */
+        uint32_t operator1_timersel:2;
+        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator2.
+         *  0: Timer0
+         *  1: Timer1
+         *  2: Timer2
+         *  3: Invalid, will select timer2
+         */
+        uint32_t operator2_timersel:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_operator_timersel_reg_t;
+
+/** Type of genn_stmp_cfg register
+ *  Generatorn time stamp registers A and B transfer status and update method register
+ */
+typedef union {
+    struct {
+        /** cmprn_a_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the update method for PWM generator n time stamp A's active register.
+         *  0: Immediately
+         *  Bit0 is set to 1: TEZ
+         *  Bit1 is set to 1: TEP
+         *  Bit2 is set to 1: Sync
+         *  Bit3 is set to 1: Disable the update
+         */
+        uint32_t cmprn_a_upmethod:4;
+        /** cmprn_b_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Configures the update method for PWM generator n time stamp B's active register.
+         *  0: Immediately
+         *  Bit0 is set to 1: TEZ
+         *  Bit1 is set to 1: TEP
+         *  Bit2 is set to 1: Sync
+         *  Bit3 is set to 1: Disable the update
+         */
+        uint32_t cmprn_b_upmethod:4;
+        /** cmprn_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
+         *  Represents whether or not generatorn time stamp A's shadow reg is transferred.
+         *  0: A's active reg has been updated with shadow register latest value.
+         *  1: A's shadow reg is filled and waiting to be transferred to A's active reg
+         */
+        uint32_t cmprn_a_shdw_full:1;
+        /** cmprn_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
+         *  Represents whether or not generatorn time stamp B's shadow reg is transferred.
+         *  0: B's active reg has been updated with shadow register latest value.
+         *  1: B's shadow reg is filled and waiting to be transferred to B's active reg
+         */
+        uint32_t cmprn_b_shdw_full:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_genn_stmp_cfg_reg_t;
+
+/** Type of genn_tstmp_a register
+ *  Generatorn time stamp A's shadow register
+ */
+typedef union {
+    struct {
+        /** cmprn_a : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the value of PWM generator n time stamp A's shadow register.
+         */
+        uint32_t cmprn_a:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_genn_tstmp_a_reg_t;
+
+/** Type of genn_tstmp_b register
+ *  Generatorn time stamp B's shadow register
+ */
+typedef union {
+    struct {
+        /** cmprn_b : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the value of PWM generator n time stamp B's shadow register.
+         */
+        uint32_t cmprn_b:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_genn_tstmp_b_reg_t;
+
+/** Type of genn_cfg0 register
+ *  Generatorn fault event T0 and T1 configuration register
+ */
+typedef union {
+    struct {
+        /** genn_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures update method for PWM generator n's active register.
+         *  0: Immediately
+         *  Bit0 is set to 1: TEZ
+         *  Bit1 is set to 1: TEP
+         *  Bit2 is set to 1: Sync
+         *  Bit3 is set to 1: Disable the update
+         */
+        uint32_t genn_cfg_upmethod:4;
+        /** genn_t0_sel : R/W; bitpos: [6:4]; default: 0;
+         *  Configures source selection for PWM generator n event_t0, take effect immediately.
+         *  0: fault_event0
+         *  1: fault_event1
+         *  2: fault_event2
+         *  3: sync_taken
+         *  4: Invalid, Select nothing
+         */
+        uint32_t genn_t0_sel:3;
+        /** genn_t1_sel : R/W; bitpos: [9:7]; default: 0;
+         *  Configures source selection for PWM generator n event_t1, take effect immediately.
+         *  0: fault_event0
+         *  1: fault_event1
+         *  2: fault_event2
+         *  3: sync_taken
+         *  4: Invalid, Select nothing
+         */
+        uint32_t genn_t1_sel:3;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_genn_cfg0_reg_t;
+
+/** Type of genn_force register
+ *  Generatorn output signal force mode register.
+ */
+typedef union {
+    struct {
+        /** genn_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
+         *  Configures update method for continuous software force of PWM generatorn.
+         *  0: Immediately
+         *  Bit0 is set to 1: TEZ
+         *  Bit1 is set to 1: TEP
+         *  Bit2 is set to 1: TEA
+         *  Bit3 is set to 1: TEB
+         *  Bit4 is set to 1: Sync
+         *  Bit5 is set to 1: Disable update. TEA/B here and below means an event generated
+         *  when the timer's value equals to that of register A/B.
+         */
+        uint32_t genn_cntuforce_upmethod:6;
+        /** genn_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
+         *  Configures continuous software force mode for PWMn A.
+         *  0: Disabled
+         *  1: Low
+         *  2: High
+         *  3: Disabled
+         */
+        uint32_t genn_a_cntuforce_mode:2;
+        /** genn_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
+         *  Configures continuous software force mode for PWMn B.
+         *  0: Disabled
+         *  1: Low
+         *  2: High
+         *  3: Disabled
+         */
+        uint32_t genn_b_cntuforce_mode:2;
+        /** genn_a_nciforce : R/W; bitpos: [10]; default: 0;
+         *  Configures the generation of non-continuous immediate software-force event for PWMn
+         *  A, a toggle will trigger a force event.
+         */
+        uint32_t genn_a_nciforce:1;
+        /** genn_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
+         *  Configures non-continuous immediate software force mode for PWMn A.
+         *  0: Disabled
+         *  1: Low
+         *  2: High
+         *  3: Disabled
+         */
+        uint32_t genn_a_nciforce_mode:2;
+        /** genn_b_nciforce : R/W; bitpos: [13]; default: 0;
+         *  Configures the generation of non-continuous immediate software-force event for PWMn
+         *  B, a toggle will trigger a force event.
+         */
+        uint32_t genn_b_nciforce:1;
+        /** genn_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
+         *  Configures non-continuous immediate software force mode for PWMn B.
+         *  0: Disabled
+         *  1: Low
+         *  2: High
+         *  3: Disabled
+         */
+        uint32_t genn_b_nciforce_mode:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_genn_force_reg_t;
+
+/** Type of genn_a register
+ *  PWMn output signal A actions configuration register
+ */
+typedef union {
+    struct {
+        /** genn_a_utez : R/W; bitpos: [1:0]; default: 0;
+         *  Configures action on PWMn A triggered by event TEZ when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_utez:2;
+        /** genn_a_utep : R/W; bitpos: [3:2]; default: 0;
+         *  Configures action on PWMn A triggered by event TEP when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_utep:2;
+        /** genn_a_utea : R/W; bitpos: [5:4]; default: 0;
+         *  Configures action on PWMn A triggered by event TEA when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_utea:2;
+        /** genn_a_uteb : R/W; bitpos: [7:6]; default: 0;
+         *  Configures action on PWMn A triggered by event TEB when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_uteb:2;
+        /** genn_a_ut0 : R/W; bitpos: [9:8]; default: 0;
+         *  Configures action on PWMn A triggered by event_t0 when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_ut0:2;
+        /** genn_a_ut1 : R/W; bitpos: [11:10]; default: 0;
+         *  Configures action on PWMn A triggered by event_t1 when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_ut1:2;
+        /** genn_a_dtez : R/W; bitpos: [13:12]; default: 0;
+         *  Configures action on PWMn A triggered by event TEZ when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_dtez:2;
+        /** genn_a_dtep : R/W; bitpos: [15:14]; default: 0;
+         *  Configures action on PWMn A triggered by event TEP when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_dtep:2;
+        /** genn_a_dtea : R/W; bitpos: [17:16]; default: 0;
+         *  Configures action on PWMn A triggered by event TEA when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_dtea:2;
+        /** genn_a_dteb : R/W; bitpos: [19:18]; default: 0;
+         *  Configures action on PWMn A triggered by event TEB when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_dteb:2;
+        /** genn_a_dt0 : R/W; bitpos: [21:20]; default: 0;
+         *  Configures action on PWMn A triggered by event_t0 when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_dt0:2;
+        /** genn_a_dt1 : R/W; bitpos: [23:22]; default: 0;
+         *  Configures action on PWMn A triggered by event_t1 when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_a_dt1:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_genn_a_reg_t;
+
+/** Type of genn_b register
+ *  PWMn output signal B actions configuration register
+ */
+typedef union {
+    struct {
+        /** genn_b_utez : R/W; bitpos: [1:0]; default: 0;
+         *  Configures action on PWMn B triggered by event TEZ when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_utez:2;
+        /** genn_b_utep : R/W; bitpos: [3:2]; default: 0;
+         *  Configures action on PWMn B triggered by event TEP when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_utep:2;
+        /** genn_b_utea : R/W; bitpos: [5:4]; default: 0;
+         *  Configures action on PWMn B triggered by event TEA when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_utea:2;
+        /** genn_b_uteb : R/W; bitpos: [7:6]; default: 0;
+         *  Configures action on PWMn B triggered by event TEB when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_uteb:2;
+        /** genn_b_ut0 : R/W; bitpos: [9:8]; default: 0;
+         *  Configures action on PWMn B triggered by event_t0 when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_ut0:2;
+        /** genn_b_ut1 : R/W; bitpos: [11:10]; default: 0;
+         *  Configures action on PWMn B triggered by event_t1 when timer increasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_ut1:2;
+        /** genn_b_dtez : R/W; bitpos: [13:12]; default: 0;
+         *  Configures action on PWMn B triggered by event TEZ when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_dtez:2;
+        /** genn_b_dtep : R/W; bitpos: [15:14]; default: 0;
+         *  Configures action on PWMn B triggered by event TEP when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_dtep:2;
+        /** genn_b_dtea : R/W; bitpos: [17:16]; default: 0;
+         *  Configures action on PWMn B triggered by event TEA when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_dtea:2;
+        /** genn_b_dteb : R/W; bitpos: [19:18]; default: 0;
+         *  Configures action on PWMn B triggered by event TEB when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_dteb:2;
+        /** genn_b_dt0 : R/W; bitpos: [21:20]; default: 0;
+         *  Configures action on PWMn B triggered by event_t0 when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_dt0:2;
+        /** genn_b_dt1 : R/W; bitpos: [23:22]; default: 0;
+         *  Configures action on PWMn B triggered by event_t1 when timer decreasing.
+         *  0: No change
+         *  1: Low
+         *  2: High
+         *  3: Toggle
+         */
+        uint32_t genn_b_dt1:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_genn_b_reg_t;
+
+/** Type of dtn_cfg register
+ *  Dead time configuration register
+ */
+typedef union {
+    struct {
+        /** dbn_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures update method for FED (Falling edge delay) active register.
+         *  0: Immediate
+         *  Bit0 is set to 1: TEZ
+         *  Bit1 is set to 1: TEP
+         *  Bit2 is set to 1: Sync
+         *  Bit3 is set to 1: Disable the update
+         */
+        uint32_t dbn_fed_upmethod:4;
+        /** dbn_red_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Configures update method for RED (rising edge delay) active register.
+         *  0: Immediate
+         *  Bit0 is set to 1: TEZ
+         *  Bit1 is set to 1: TEP
+         *  Bit2 is set to 1: Sync
+         *  Bit3 is set to 1: Disable the update
+         */
+        uint32_t dbn_red_upmethod:4;
+        /** dbn_deb_mode : R/W; bitpos: [8]; default: 0;
+         *  Configures S8 in table, dual-edge B mode.
+         *  0: fed/red take effect on different path separately
+         *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+         */
+        uint32_t dbn_deb_mode:1;
+        /** dbn_a_outswap : R/W; bitpos: [9]; default: 0;
+         *  Configures S6 in table.
+         */
+        uint32_t dbn_a_outswap:1;
+        /** dbn_b_outswap : R/W; bitpos: [10]; default: 0;
+         *  Configures S7 in table.
+         */
+        uint32_t dbn_b_outswap:1;
+        /** dbn_red_insel : R/W; bitpos: [11]; default: 0;
+         *  Configures S4 in table.
+         */
+        uint32_t dbn_red_insel:1;
+        /** dbn_fed_insel : R/W; bitpos: [12]; default: 0;
+         *  Configures S5 in table.
+         */
+        uint32_t dbn_fed_insel:1;
+        /** dbn_red_outinvert : R/W; bitpos: [13]; default: 0;
+         *  Configures S2 in table.
+         */
+        uint32_t dbn_red_outinvert:1;
+        /** dbn_fed_outinvert : R/W; bitpos: [14]; default: 0;
+         *  Configures S3 in table.
+         */
+        uint32_t dbn_fed_outinvert:1;
+        /** dbn_a_outbypass : R/W; bitpos: [15]; default: 1;
+         *  Configures S1 in table.
+         */
+        uint32_t dbn_a_outbypass:1;
+        /** dbn_b_outbypass : R/W; bitpos: [16]; default: 1;
+         *  Configures S0 in table.
+         */
+        uint32_t dbn_b_outbypass:1;
+        /** dbn_clk_sel : R/W; bitpos: [17]; default: 0;
+         *  Configures dead time generator n clock selection.
+         *  0: PWM_clk
+         *  1: PT_clk
+         */
+        uint32_t dbn_clk_sel:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} mcpwm_dtn_cfg_reg_t;
+
+/** Type of dtn_fed_cfg register
+ *  Falling edge delay (FED) shadow register
+ */
+typedef union {
+    struct {
+        /** dbn_fed : R/W; bitpos: [15:0]; default: 0;
+         *  Configures shadow register for FED.
+         */
+        uint32_t dbn_fed:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dtn_fed_cfg_reg_t;
+
+/** Type of dtn_red_cfg register
+ *  Rising edge delay (RED) shadow register
+ */
+typedef union {
+    struct {
+        /** dbn_red : R/W; bitpos: [15:0]; default: 0;
+         *  Configures shadow register for RED.
+         */
+        uint32_t dbn_red:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dtn_red_cfg_reg_t;
+
+/** Type of carriern_cfg register
+ *  Carriern configuration register
+ */
+typedef union {
+    struct {
+        /** choppern_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable carriern.
+         *  0: Bypassed
+         *  1: Enabled
+         */
+        uint32_t choppern_en:1;
+        /** choppern_prescale : R/W; bitpos: [4:1]; default: 0;
+         *  Configures the prescale value of PWM carriern clock (PC_clk), so that period of
+         *  PC_clk = period of PWM_clk * (PWM_CARRIERn_PRESCALE + 1)
+         */
+        uint32_t choppern_prescale:4;
+        /** choppern_duty : R/W; bitpos: [7:5]; default: 0;
+         *  Configures carrier duty. Duty = PWM_CARRIERn_DUTY / 8
+         */
+        uint32_t choppern_duty:3;
+        /** choppern_oshtwth : R/W; bitpos: [11:8]; default: 0;
+         *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+         */
+        uint32_t choppern_oshtwth:4;
+        /** choppern_out_invert : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to invert the output of PWMn A and PWMn B for this
+         *  submodule.
+         *  0: Normal
+         *  1: Invert
+         */
+        uint32_t choppern_out_invert:1;
+        /** choppern_in_invert : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to invert the input of PWMn A and PWMn B for this
+         *  submodule.
+         *  0: Normal
+         *  1: Invert
+         */
+        uint32_t choppern_in_invert:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} mcpwm_carriern_cfg_reg_t;
+
+/** Type of fhn_cfg0 register
+ *  PWMn A and PWMn B trip events actions configuration register
+ */
+typedef union {
+    struct {
+        /** tzn_sw_cbc : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable software force cycle-by-cycle mode action.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t tzn_sw_cbc:1;
+        /** tzn_f2_cbc : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t tzn_f2_cbc:1;
+        /** tzn_f1_cbc : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t tzn_f1_cbc:1;
+        /** tzn_f0_cbc : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t tzn_f0_cbc:1;
+        /** tzn_sw_ost : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable software force one-shot mode action.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t tzn_sw_ost:1;
+        /** tzn_f2_ost : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not event_f2 will trigger one-shot mode action.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t tzn_f2_ost:1;
+        /** tzn_f1_ost : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not event_f1 will trigger one-shot mode action.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t tzn_f1_ost:1;
+        /** tzn_f0_ost : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not event_f0 will trigger one-shot mode action.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t tzn_f0_ost:1;
+        /** tzn_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer
+         *  is decreasing.
+         *  0: Do nothing
+         *  1: Force low
+         *  2: Force high
+         *  3: Toggle
+         */
+        uint32_t tzn_a_cbc_d:2;
+        /** tzn_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer
+         *  is increasing.
+         *  0: Do nothing
+         *  1: Force low
+         *  2: Force high
+         *  3: Toggle
+         */
+        uint32_t tzn_a_cbc_u:2;
+        /** tzn_a_ost_d : R/W; bitpos: [13:12]; default: 0;
+         *  Configures one-shot mode action on PWMn A when fault event occurs and timer is
+         *  decreasing.
+         *  0: Do nothing
+         *  1: Force low
+         *  2: Force high
+         *  3: Toggle
+         */
+        uint32_t tzn_a_ost_d:2;
+        /** tzn_a_ost_u : R/W; bitpos: [15:14]; default: 0;
+         *  Configures one-shot mode action on PWMn A when fault event occurs and timer is
+         *  increasing.
+         *  0: Do nothing
+         *  1: Force low
+         *  2: Force high
+         *  3: Toggle
+         */
+        uint32_t tzn_a_ost_u:2;
+        /** tzn_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer
+         *  is decreasing.
+         *  0: Do nothing
+         *  1: Force low
+         *  2: Force high
+         *  3: Toggle
+         */
+        uint32_t tzn_b_cbc_d:2;
+        /** tzn_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer
+         *  is increasing.
+         *  0: Do nothing
+         *  1: Force low
+         *  2: Force high
+         *  3: Toggle
+         */
+        uint32_t tzn_b_cbc_u:2;
+        /** tzn_b_ost_d : R/W; bitpos: [21:20]; default: 0;
+         *  Configures one-shot mode action on PWMn B when fault event occurs and timer is
+         *  decreasing.
+         *  0: Do nothing
+         *  1: Force low
+         *  2: Force high
+         *  3: Toggle
+         */
+        uint32_t tzn_b_ost_d:2;
+        /** tzn_b_ost_u : R/W; bitpos: [23:22]; default: 0;
+         *  Configures one-shot mode action on PWMn B when fault event occurs and timer is
+         *  increasing.
+         *  0: Do nothing
+         *  1: Force low
+         *  2: Force high
+         *  3: Toggle
+         */
+        uint32_t tzn_b_ost_u:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_fhn_cfg0_reg_t;
+
+/** Type of fhn_cfg1 register
+ *  Software triggers for fault handler actions configuration register
+ */
+typedef union {
+    struct {
+        /** tzn_clr_ost : R/W; bitpos: [0]; default: 0;
+         *  Configures the generation of software one-shot mode action clear. A toggle
+         *  (software negate its value) triggers a clear for on going one-shot mode action.
+         */
+        uint32_t tzn_clr_ost:1;
+        /** tzn_cbcpulse : R/W; bitpos: [2:1]; default: 0;
+         *  Configures the refresh moment selection of cycle-by-cycle mode action.
+         *  0: Select nothing, will not refresh
+         *  Bit0 is set to 1: TEZ
+         *  Bit1 is set to 1: TEP
+         */
+        uint32_t tzn_cbcpulse:2;
+        /** tzn_force_cbc : R/W; bitpos: [3]; default: 0;
+         *  Configures the generation of software cycle-by-cycle mode action. A toggle
+         *  (software negate its value) triggers a cycle-by-cycle mode action.
+         */
+        uint32_t tzn_force_cbc:1;
+        /** tzn_force_ost : R/W; bitpos: [4]; default: 0;
+         *  Configures the generation of software one-shot mode action. A toggle (software
+         *  negate its value) triggers a one-shot mode action.
+         */
+        uint32_t tzn_force_ost:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_fhn_cfg1_reg_t;
+
+/** Type of fault_detect register
+ *  Fault detection configuration and status register
+ */
+typedef union {
+    struct {
+        /** f0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable event_f0 generation.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t f0_en:1;
+        /** f1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable event_f1 generation.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t f1_en:1;
+        /** f2_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable event_f2 generation.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t f2_en:1;
+        /** f0_pole : R/W; bitpos: [3]; default: 0;
+         *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.
+         *  0: Level low
+         *  1: Level high
+         */
+        uint32_t f0_pole:1;
+        /** f1_pole : R/W; bitpos: [4]; default: 0;
+         *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.
+         *  0: Level low
+         *  1: Level high
+         */
+        uint32_t f1_pole:1;
+        /** f2_pole : R/W; bitpos: [5]; default: 0;
+         *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.
+         *  0: Level low
+         *  1: Level high
+         */
+        uint32_t f2_pole:1;
+        /** event_f0 : RO; bitpos: [6]; default: 0;
+         *  Represents whether or not an event_f0 is on going.
+         *  0: No action
+         *  1: On going
+         */
+        uint32_t event_f0:1;
+        /** event_f1 : RO; bitpos: [7]; default: 0;
+         *  Represents whether or not an event_f1 is on going.
+         *  0: No action
+         *  1: On going
+         */
+        uint32_t event_f1:1;
+        /** event_f2 : RO; bitpos: [8]; default: 0;
+         *  Represents whether or not an event_f2 is on going.
+         *  0: No action
+         *  1: On going
+         */
+        uint32_t event_f2:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} mcpwm_fault_detect_reg_t;
+
+/** Type of cap_timer_cfg register
+ *  Capture timer configuration register
+ */
+typedef union {
+    struct {
+        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable capture timer increment.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t cap_timer_en:1;
+        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable capture timer sync.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t cap_synci_en:1;
+        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
+         *  Configures the selection of capture module sync input.
+         *  0: None
+         *  1: Timer0 sync_out
+         *  2: Timer1 sync_out
+         *  3: Timer2 sync_out
+         *  4: SYNC0 from GPIO matrix
+         *  5: SYNC1 from GPIO matrix
+         *  6: SYNC2 from GPIO matrix
+         *  7: None
+         */
+        uint32_t cap_synci_sel:3;
+        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
+         *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.
+         *  0: Invalid, No effect
+         *  1: Trigger a capture timer sync, capture timer is loaded with value in phase
+         *  register
+         */
+        uint32_t cap_sync_sw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_cfg_reg_t;
+
+/** Type of cap_timer_phase register
+ *  Capture timer sync phase register
+ */
+typedef union {
+    struct {
+        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
+         *  Configures phase value for capture timer sync operation.
+         */
+        uint32_t cap_phase:32;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_phase_reg_t;
+
+/** Type of cap_chn_cfg register
+ *  Capture channel n configuration register
+ */
+typedef union {
+    struct {
+        /** capn_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable capture on channel n.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t capn_en:1;
+        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
+         *  Configures which edge of capture on channel n after prescaling is used.
+         *  0: None
+         *  Bit0 is set to 1: Rnable capture on the negative edge
+         *  Bit1 is set to 1: Enable capture on the positive edge
+         */
+        uint32_t capn_mode:2;
+        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
+         *  Configures prescale value on positive edge of CAPn. Prescale value =
+         *  PWM_CAPn_PRESCALE + 1
+         */
+        uint32_t capn_prescale:8;
+        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert CAPn from GPIO matrix before prescale.
+         *  0: Normal
+         *  1: Invert
+         */
+        uint32_t capn_in_invert:1;
+        /** capn_sw : WT; bitpos: [12]; default: 0;
+         *  Configures the generation of software capture.
+         *  0: Invalid, No effect
+         *  1: Trigger a software forced capture on channel n
+         */
+        uint32_t capn_sw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_cfg_reg_t;
+
+/** Type of update_cfg register
+ *  Generator Update configuration register
+ */
+typedef union {
+    struct {
+        /** global_up_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether or not to enable global update for all active registers in MCPWM
+         *  module.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t global_up_en:1;
+        /** global_force_up : R/W; bitpos: [1]; default: 0;
+         *  Configures the generation of global forced update for all active registers in MCPWM
+         *  module. A toggle (software invert its value) will trigger a global forced update.
+         *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
+         */
+        uint32_t global_force_up:1;
+        /** op0_up_en : R/W; bitpos: [2]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator0.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t op0_up_en:1;
+        /** op0_force_up : R/W; bitpos: [3]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator0. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
+         */
+        uint32_t op0_force_up:1;
+        /** op1_up_en : R/W; bitpos: [4]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator1.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t op1_up_en:1;
+        /** op1_force_up : R/W; bitpos: [5]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator1. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
+         */
+        uint32_t op1_force_up:1;
+        /** op2_up_en : R/W; bitpos: [6]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator2.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t op2_up_en:1;
+        /** op2_force_up : R/W; bitpos: [7]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator2. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
+         */
+        uint32_t op2_force_up:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_update_cfg_reg_t;
+
+/** Type of evt_en register
+ *  Event enable register
+ */
+typedef union {
+    struct {
+        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable timer0 stop event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_timer0_stop_en:1;
+        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable timer1 stop event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_timer1_stop_en:1;
+        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable timer2 stop event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_timer2_stop_en:1;
+        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable timer0 equal zero event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_timer0_tez_en:1;
+        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable timer1 equal zero event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_timer1_tez_en:1;
+        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable timer2 equal zero event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_timer2_tez_en:1;
+        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable timer0 equal period event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_timer0_tep_en:1;
+        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable timer1 equal period event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_timer1_tep_en:1;
+        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable timer2 equal period event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_timer2_tep_en:1;
+        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal a event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op0_tea_en:1;
+        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal a event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op1_tea_en:1;
+        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal a event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op2_tea_en:1;
+        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal b event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op0_teb_en:1;
+        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal b event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op1_teb_en:1;
+        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal b event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op2_teb_en:1;
+        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable fault0 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_f0_en:1;
+        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable fault1 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_f1_en:1;
+        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable fault2 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_f2_en:1;
+        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable fault0 clear event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_f0_clr_en:1;
+        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable fault1 clear event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_f1_clr_en:1;
+        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable fault2 clear event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_f2_clr_en:1;
+        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip0 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_tz0_cbc_en:1;
+        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip1 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_tz1_cbc_en:1;
+        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip2 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_tz2_cbc_en:1;
+        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable one-shot trip0 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_tz0_ost_en:1;
+        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to enable one-shot trip1 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_tz1_ost_en:1;
+        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to enable one-shot trip2 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_tz2_ost_en:1;
+        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable capture0 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_cap0_en:1;
+        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable capture1 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_cap1_en:1;
+        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable capture2 event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_cap2_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_evt_en_reg_t;
+
+/** Type of task_en register
+ *  Task enable register
+ */
+typedef union {
+    struct {
+        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
+         *  update task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_cmpr0_a_up_en:1;
+        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
+         *  update task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_cmpr1_a_up_en:1;
+        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
+         *  update task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_cmpr2_a_up_en:1;
+        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
+         *  update task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_cmpr0_b_up_en:1;
+        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
+         *  update task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_cmpr1_b_up_en:1;
+        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
+         *  update task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_cmpr2_b_up_en:1;
+        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable all PWM generate stop task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_gen_stop_en:1;
+        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable timer0 sync task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer0_sync_en:1;
+        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable timer1 sync task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer1_sync_en:1;
+        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable timer2 sync task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer2_sync_en:1;
+        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable timer0 period update task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer0_period_up_en:1;
+        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable timer1 period update task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer1_period_up_en:1;
+        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable timer2 period update task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_timer2_period_up_en:1;
+        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable one shot trip0 task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_tz0_ost_en:1;
+        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable one shot trip1 task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_tz1_ost_en:1;
+        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable one shot trip2 task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_tz2_ost_en:1;
+        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable one shot trip0 clear task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_clr0_ost_en:1;
+        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable one shot trip1 clear task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_clr1_ost_en:1;
+        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable one shot trip2 clear task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_clr2_ost_en:1;
+        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable capture0 task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_cap0_en:1;
+        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable capture1 task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_cap1_en:1;
+        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable capture2 task receive.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t task_cap2_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} mcpwm_task_en_reg_t;
+
+/** Type of evt_en2 register
+ *  Event enable register2
+ */
+typedef union {
+    struct {
+        /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
+         *  event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op0_tee1_en:1;
+        /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
+         *  event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op1_tee1_en:1;
+        /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
+         *  event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op2_tee1_en:1;
+        /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
+         *  event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op0_tee2_en:1;
+        /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
+         *  event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op1_tee2_en:1;
+        /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
+         *  event generate.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t evt_op2_tee2_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_evt_en2_reg_t;
+
+/** Type of opn_tstmp_e1 register
+ *  Generatorn timer stamp E1 value register
+ */
+typedef union {
+    struct {
+        /** opn_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures generatorn timer stamp E1 value register
+         */
+        uint32_t opn_tstmp_e1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_opn_tstmp_e1_reg_t;
+
+/** Type of opn_tstmp_e2 register
+ *  Generatorn timer stamp E2 value register
+ */
+typedef union {
+    struct {
+        /** opn_tstmp_e2 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures generatorn timer stamp E2 value register
+         */
+        uint32_t opn_tstmp_e2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_opn_tstmp_e2_reg_t;
+
+/** Type of clk register
+ *  Global configuration register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to open register clock gate.
+         *  0: Open the clock gate only when application writes registers
+         *  1: Force open the clock gate for register
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mcpwm_clk_reg_t;
+
+
+/** Group: Status register */
+/** Type of timern_status register
+ *  PWM timern status register.
+ */
+typedef union {
+    struct {
+        /** timern_value : RO; bitpos: [15:0]; default: 0;
+         *  Represents current PWM timern counter value.
+         */
+        uint32_t timern_value:16;
+        /** timern_direction : RO; bitpos: [16]; default: 0;
+         *  Represents current PWM timern counter direction.
+         *  0: Increment
+         *  1: Decrement
+         */
+        uint32_t timern_direction:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} mcpwm_timern_status_reg_t;
+
+/** Type of fhn_status register
+ *  Fault events status register
+ */
+typedef union {
+    struct {
+        /** tzn_cbc_on : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not an cycle-by-cycle mode action is on going.
+         *  0:No action
+         *  1: On going
+         */
+        uint32_t tzn_cbc_on:1;
+        /** tzn_ost_on : RO; bitpos: [1]; default: 0;
+         *  Represents whether or not an one-shot mode action is on going.
+         *  0:No action
+         *  1: On going
+         */
+        uint32_t tzn_ost_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} mcpwm_fhn_status_reg_t;
+
+/** Type of cap_chn register
+ *  CAPn capture value register
+ */
+typedef union {
+    struct {
+        /** capn_value : RO; bitpos: [31:0]; default: 0;
+         *  Represents value of last capture on CAPn
+         */
+        uint32_t capn_value:32;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_reg_t;
+
+/** Type of cap_status register
+ *  Last capture trigger edge information register
+ */
+typedef union {
+    struct {
+        /** cap0_edge : RO; bitpos: [0]; default: 0;
+         *  Represents edge of last capture trigger on channel0.
+         *  0: Posedge
+         *  1: Negedge
+         */
+        uint32_t cap0_edge:1;
+        /** cap1_edge : RO; bitpos: [1]; default: 0;
+         *  Represents edge of last capture trigger on channel1.
+         *  0: Posedge
+         *  1: Negedge
+         */
+        uint32_t cap1_edge:1;
+        /** cap2_edge : RO; bitpos: [2]; default: 0;
+         *  Represents edge of last capture trigger on channel2.
+         *  0: Posedge
+         *  1: Negedge
+         */
+        uint32_t cap2_edge:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} mcpwm_cap_status_reg_t;
+
+
+/** Group: Interrupt register */
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_ena:1;
+        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_ena:1;
+        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_ena:1;
+        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_ena:1;
+        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_ena:1;
+        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_ena:1;
+        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_ena:1;
+        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_ena:1;
+        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_ena:1;
+        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_ena:1;
+        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_ena:1;
+        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_ena:1;
+        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
+         */
+        uint32_t fault0_clr_int_ena:1;
+        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
+         */
+        uint32_t fault1_clr_int_ena:1;
+        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
+         */
+        uint32_t fault2_clr_int_ena:1;
+        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
+         */
+        uint32_t cmpr0_tea_int_ena:1;
+        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
+         */
+        uint32_t cmpr1_tea_int_ena:1;
+        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
+         */
+        uint32_t cmpr2_tea_int_ena:1;
+        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
+         */
+        uint32_t cmpr0_teb_int_ena:1;
+        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
+         */
+        uint32_t cmpr1_teb_int_ena:1;
+        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
+         */
+        uint32_t cmpr2_teb_int_ena:1;
+        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM0.
+         */
+        uint32_t tz0_cbc_int_ena:1;
+        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM1.
+         */
+        uint32_t tz1_cbc_int_ena:1;
+        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM2.
+         */
+        uint32_t tz2_cbc_int_ena:1;
+        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_ost_int_ena:1;
+        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_ost_int_ena:1;
+        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_ost_int_ena:1;
+        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
+         */
+        uint32_t cap0_int_ena:1;
+        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
+         */
+        uint32_t cap1_int_ena:1;
+        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
+         */
+        uint32_t cap2_int_ena:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  0 stops.
+         */
+        uint32_t timer0_stop_int_raw:1;
+        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  1 stops.
+         */
+        uint32_t timer1_stop_int_raw:1;
+        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  2 stops.
+         */
+        uint32_t timer2_stop_int_raw:1;
+        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  0 TEZ event.
+         */
+        uint32_t timer0_tez_int_raw:1;
+        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  1 TEZ event.
+         */
+        uint32_t timer1_tez_int_raw:1;
+        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  2 TEZ event.
+         */
+        uint32_t timer2_tez_int_raw:1;
+        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  0 TEP event.
+         */
+        uint32_t timer0_tep_int_raw:1;
+        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  1 TEP event.
+         */
+        uint32_t timer1_tep_int_raw:1;
+        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  2 TEP event.
+         */
+        uint32_t timer2_tep_int_raw:1;
+        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+         *  starts.
+         */
+        uint32_t fault0_int_raw:1;
+        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+         *  starts.
+         */
+        uint32_t fault1_int_raw:1;
+        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+         *  starts.
+         */
+        uint32_t fault2_int_raw:1;
+        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+         *  clears.
+         */
+        uint32_t fault0_clr_int_raw:1;
+        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+         *  clears.
+         */
+        uint32_t fault1_clr_int_raw:1;
+        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+         *  clears.
+         */
+        uint32_t fault2_clr_int_raw:1;
+        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_raw:1;
+        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_raw:1;
+        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_raw:1;
+        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_raw:1;
+        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_raw:1;
+        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_raw:1;
+        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t tz0_cbc_int_raw:1;
+        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t tz1_cbc_int_raw:1;
+        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t tz2_cbc_int_raw:1;
+        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_raw:1;
+        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_raw:1;
+        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_raw:1;
+        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP0.
+         */
+        uint32_t cap0_int_raw:1;
+        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP1.
+         */
+        uint32_t cap1_int_raw:1;
+        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP2.
+         */
+        uint32_t cap2_int_raw:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt masked status register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 0 stops.
+         */
+        uint32_t timer0_stop_int_st:1;
+        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 1 stops.
+         */
+        uint32_t timer1_stop_int_st:1;
+        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 2 stops.
+         */
+        uint32_t timer2_stop_int_st:1;
+        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_st:1;
+        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_st:1;
+        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_st:1;
+        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_st:1;
+        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_st:1;
+        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_st:1;
+        /** fault0_int_st : RO; bitpos: [9]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f0 starts.
+         */
+        uint32_t fault0_int_st:1;
+        /** fault1_int_st : RO; bitpos: [10]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f1 starts.
+         */
+        uint32_t fault1_int_st:1;
+        /** fault2_int_st : RO; bitpos: [11]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f2 starts.
+         */
+        uint32_t fault2_int_st:1;
+        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f0 clears.
+         */
+        uint32_t fault0_clr_int_st:1;
+        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f1 clears.
+         */
+        uint32_t fault1_clr_int_st:1;
+        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f2 clears.
+         */
+        uint32_t fault2_clr_int_st:1;
+        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_st:1;
+        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_st:1;
+        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_st:1;
+        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_st:1;
+        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_st:1;
+        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_st:1;
+        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t tz0_cbc_int_st:1;
+        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t tz1_cbc_int_st:1;
+        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t tz2_cbc_int_st:1;
+        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_st:1;
+        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_st:1;
+        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_st:1;
+        /** cap0_int_st : RO; bitpos: [27]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP0.
+         */
+        uint32_t cap0_int_st:1;
+        /** cap1_int_st : RO; bitpos: [28]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP1.
+         */
+        uint32_t cap1_int_st:1;
+        /** cap2_int_st : RO; bitpos: [29]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP2.
+         */
+        uint32_t cap2_int_st:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_clr:1;
+        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_clr:1;
+        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_clr:1;
+        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_clr:1;
+        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_clr:1;
+        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_clr:1;
+        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_clr:1;
+        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_clr:1;
+        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_clr:1;
+        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_clr:1;
+        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_clr:1;
+        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_clr:1;
+        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
+         */
+        uint32_t fault0_clr_int_clr:1;
+        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
+         */
+        uint32_t fault1_clr_int_clr:1;
+        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
+         */
+        uint32_t fault2_clr_int_clr:1;
+        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_clr:1;
+        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_clr:1;
+        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_clr:1;
+        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_clr:1;
+        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_clr:1;
+        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_clr:1;
+        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM0.
+         */
+        uint32_t tz0_cbc_int_clr:1;
+        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM1.
+         */
+        uint32_t tz1_cbc_int_clr:1;
+        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM2.
+         */
+        uint32_t tz2_cbc_int_clr:1;
+        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_ost_int_clr:1;
+        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_ost_int_clr:1;
+        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_ost_int_clr:1;
+        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
+         */
+        uint32_t cap0_int_clr:1;
+        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
+         */
+        uint32_t cap1_int_clr:1;
+        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
+         */
+        uint32_t cap2_int_clr:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_clr_reg_t;
+
+
+/** Group: Version register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35725968;
+         *  Configures the version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} mcpwm_version_reg_t;
+
+
+typedef struct {
+    volatile mcpwm_clk_cfg_reg_t clk_cfg;
+    volatile mcpwm_timern_cfg0_reg_t timer0_cfg0;
+    volatile mcpwm_timern_cfg1_reg_t timer0_cfg1;
+    volatile mcpwm_timern_sync_reg_t timer0_sync;
+    volatile mcpwm_timern_status_reg_t timer0_status;
+    volatile mcpwm_timern_cfg0_reg_t timer1_cfg0;
+    volatile mcpwm_timern_cfg1_reg_t timer1_cfg1;
+    volatile mcpwm_timern_sync_reg_t timer1_sync;
+    volatile mcpwm_timern_status_reg_t timer1_status;
+    volatile mcpwm_timern_cfg0_reg_t timer2_cfg0;
+    volatile mcpwm_timern_cfg1_reg_t timer2_cfg1;
+    volatile mcpwm_timern_sync_reg_t timer2_sync;
+    volatile mcpwm_timern_status_reg_t timer2_status;
+    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
+    volatile mcpwm_operator_timersel_reg_t operator_timersel;
+    volatile mcpwm_genn_stmp_cfg_reg_t gen0_stmp_cfg;
+    volatile mcpwm_genn_tstmp_a_reg_t gen0_tstmp_a;
+    volatile mcpwm_genn_tstmp_b_reg_t gen0_tstmp_b;
+    volatile mcpwm_genn_cfg0_reg_t gen0_cfg0;
+    volatile mcpwm_genn_force_reg_t gen0_force;
+    volatile mcpwm_genn_a_reg_t gen0_a;
+    volatile mcpwm_genn_b_reg_t gen0_b;
+    volatile mcpwm_dtn_cfg_reg_t dt0_cfg;
+    volatile mcpwm_dtn_fed_cfg_reg_t dt0_fed_cfg;
+    volatile mcpwm_dtn_red_cfg_reg_t dt0_red_cfg;
+    volatile mcpwm_carriern_cfg_reg_t carrier0_cfg;
+    volatile mcpwm_fhn_cfg0_reg_t fh0_cfg0;
+    volatile mcpwm_fhn_cfg1_reg_t fh0_cfg1;
+    volatile mcpwm_fhn_status_reg_t fh0_status;
+    volatile mcpwm_genn_stmp_cfg_reg_t gen1_stmp_cfg;
+    volatile mcpwm_genn_tstmp_a_reg_t gen1_tstmp_a;
+    volatile mcpwm_genn_tstmp_b_reg_t gen1_tstmp_b;
+    volatile mcpwm_genn_cfg0_reg_t gen1_cfg0;
+    volatile mcpwm_genn_force_reg_t gen1_force;
+    volatile mcpwm_genn_a_reg_t gen1_a;
+    volatile mcpwm_genn_b_reg_t gen1_b;
+    volatile mcpwm_dtn_cfg_reg_t dt1_cfg;
+    volatile mcpwm_dtn_fed_cfg_reg_t dt1_fed_cfg;
+    volatile mcpwm_dtn_red_cfg_reg_t dt1_red_cfg;
+    volatile mcpwm_carriern_cfg_reg_t carrier1_cfg;
+    volatile mcpwm_fhn_cfg0_reg_t fh1_cfg0;
+    volatile mcpwm_fhn_cfg1_reg_t fh1_cfg1;
+    volatile mcpwm_fhn_status_reg_t fh1_status;
+    volatile mcpwm_genn_stmp_cfg_reg_t gen2_stmp_cfg;
+    volatile mcpwm_genn_tstmp_a_reg_t gen2_tstmp_a;
+    volatile mcpwm_genn_tstmp_b_reg_t gen2_tstmp_b;
+    volatile mcpwm_genn_cfg0_reg_t gen2_cfg0;
+    volatile mcpwm_genn_force_reg_t gen2_force;
+    volatile mcpwm_genn_a_reg_t gen2_a;
+    volatile mcpwm_genn_b_reg_t gen2_b;
+    volatile mcpwm_dtn_cfg_reg_t dt2_cfg;
+    volatile mcpwm_dtn_fed_cfg_reg_t dt2_fed_cfg;
+    volatile mcpwm_dtn_red_cfg_reg_t dt2_red_cfg;
+    volatile mcpwm_carriern_cfg_reg_t carrier2_cfg;
+    volatile mcpwm_fhn_cfg0_reg_t fh2_cfg0;
+    volatile mcpwm_fhn_cfg1_reg_t fh2_cfg1;
+    volatile mcpwm_fhn_status_reg_t fh2_status;
+    volatile mcpwm_fault_detect_reg_t fault_detect;
+    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
+    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
+    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
+    volatile mcpwm_cap_chn_reg_t cap_chn[3];
+    volatile mcpwm_cap_status_reg_t cap_status;
+    volatile mcpwm_update_cfg_reg_t update_cfg;
+    volatile mcpwm_int_ena_reg_t int_ena;
+    volatile mcpwm_int_raw_reg_t int_raw;
+    volatile mcpwm_int_st_reg_t int_st;
+    volatile mcpwm_int_clr_reg_t int_clr;
+    volatile mcpwm_evt_en_reg_t evt_en;
+    volatile mcpwm_task_en_reg_t task_en;
+    volatile mcpwm_evt_en2_reg_t evt_en2;
+    volatile mcpwm_opn_tstmp_e1_reg_t op0_tstmp_e1;
+    volatile mcpwm_opn_tstmp_e2_reg_t op0_tstmp_e2;
+    volatile mcpwm_opn_tstmp_e1_reg_t op1_tstmp_e1;
+    volatile mcpwm_opn_tstmp_e2_reg_t op1_tstmp_e2;
+    volatile mcpwm_opn_tstmp_e1_reg_t op2_tstmp_e1;
+    volatile mcpwm_opn_tstmp_e2_reg_t op2_tstmp_e2;
+    volatile mcpwm_clk_reg_t clk;
+    volatile mcpwm_version_reg_t version;
+} mcpwm_dev_t;
+
+extern mcpwm_dev_t MCPWM0;
+extern mcpwm_dev_t MCPWM1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_reg.h
new file mode 100644
index 0000000000..c1e2197dbf
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_reg.h
@@ -0,0 +1,5213 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MCPWM_CLK_CFG_REG register
+ *  PWM clock prescaler register.
+ */
+#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0)
+/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
+ *  (PWM_CLK_PRESCALE + 1).
+ */
+#define MCPWM_CLK_PRESCALE    0x000000FFU
+#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
+#define MCPWM_CLK_PRESCALE_V  0x000000FFU
+#define MCPWM_CLK_PRESCALE_S  0
+
+/** MCPWM_TIMER0_CFG0_REG register
+ *  PWM timer0 period and update method configuration register.
+ */
+#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x4)
+/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of timer0, so that the period of PT0_clk = Period of
+ *  PWM_clk * (PWM_TIMER0_PRESCALE + 1)
+ */
+#define MCPWM_TIMER0_PRESCALE    0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
+#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_S  0
+/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  Configures the period shadow of PWM timer0
+ */
+#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
+#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_S  8
+/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Configures the update method for active register of PWM timer0 period.
+ *  0: Immediate
+ *  1: TEZ
+ *  2: Sync
+ *  3: TEZ or sync
+ *  TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER0_CFG1_REG register
+ *  PWM timer0 working mode and start/stop control register.
+ */
+#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x8)
+/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to start/stop PWM timer0.
+ *  0: If PWM timer0 starts, then stops at TEZ
+ *  1: If timer0 starts, then stops at TEP
+ *  2: PWM timer0 starts and runs on
+ *  3: Timer0 starts and stops at the next TEZ
+ *  4: Timer0 starts and stops at the next TEP.
+ *  TEP here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER0_START    0x00000007U
+#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
+#define MCPWM_TIMER0_START_V  0x00000007U
+#define MCPWM_TIMER0_START_S  0
+/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the working mode of PWM timer0.
+ *  0: Freeze
+ *  1: Increase mode
+ *  2: Decrease mode
+ *  3: Up-down mode
+ */
+#define MCPWM_TIMER0_MOD    0x00000003U
+#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
+#define MCPWM_TIMER0_MOD_V  0x00000003U
+#define MCPWM_TIMER0_MOD_S  3
+
+/** MCPWM_TIMER0_SYNC_REG register
+ *  PWM timer0 sync function configuration register.
+ */
+#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0xc)
+/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer0 reloading with phase on sync input event
+ *  is enabled.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
+#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER0_SYNCI_EN_S  0
+/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of software sync. Toggling this bit will trigger a
+ *  software sync.
+ */
+#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
+#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER0_SYNC_SW_S  1
+/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the selection of PWM timer0 sync_out.
+ *  0: Sync_in
+ *  1: TEZ
+ *  2: TEP
+ *  3: Invalid, sync_out selects noting
+ */
+#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
+#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_S  2
+/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  Configures the phase for timer0 reload on sync event.
+ */
+#define MCPWM_TIMER0_PHASE    0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
+#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_S  4
+/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configures the PWM timer0's direction when timer0 mode is up-down mode.
+ *  0: Increase
+ *  1: Decrease
+ */
+#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
+#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER0_STATUS_REG register
+ *  PWM timer0 status register.
+ */
+#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x10)
+/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  Represents current PWM timer0 counter value.
+ */
+#define MCPWM_TIMER0_VALUE    0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
+#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_S  0
+/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  Represents current PWM timer0 counter direction.
+ *  0: Increment
+ *  1: Decrement
+ */
+#define MCPWM_TIMER0_DIRECTION    (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
+#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_DIRECTION_S  16
+
+/** MCPWM_TIMER1_CFG0_REG register
+ *  PWM timer1 period and update method configuration register.
+ */
+#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x14)
+/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of timer1, so that the period of PT0_clk = Period of
+ *  PWM_clk * (PWM_TIMER1_PRESCALE + 1)
+ */
+#define MCPWM_TIMER1_PRESCALE    0x000000FFU
+#define MCPWM_TIMER1_PRESCALE_M  (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S)
+#define MCPWM_TIMER1_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER1_PRESCALE_S  0
+/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  Configures the period shadow of PWM timer1
+ */
+#define MCPWM_TIMER1_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER1_PERIOD_M  (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S)
+#define MCPWM_TIMER1_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER1_PERIOD_S  8
+/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Configures the update method for active register of PWM timer1 period.
+ *  0: Immediate
+ *  1: TEZ
+ *  2: Sync
+ *  3: TEZ or sync
+ *  TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER1_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER1_CFG1_REG register
+ *  PWM timer1 working mode and start/stop control register.
+ */
+#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x18)
+/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to start/stop PWM timer1.
+ *  0: If PWM timer1 starts, then stops at TEZ
+ *  1: If timer1 starts, then stops at TEP
+ *  2: PWM timer1 starts and runs on
+ *  3: Timer1 starts and stops at the next TEZ
+ *  4: Timer0 starts and stops at the next TEP.
+ *  TEP here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER1_START    0x00000007U
+#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
+#define MCPWM_TIMER1_START_V  0x00000007U
+#define MCPWM_TIMER1_START_S  0
+/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the working mode of PWM timer1.
+ *  0: Freeze
+ *  1: Increase mode
+ *  2: Decrease mode
+ *  3: Up-down mode
+ */
+#define MCPWM_TIMER1_MOD    0x00000003U
+#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
+#define MCPWM_TIMER1_MOD_V  0x00000003U
+#define MCPWM_TIMER1_MOD_S  3
+
+/** MCPWM_TIMER1_SYNC_REG register
+ *  PWM timer1 sync function configuration register.
+ */
+#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x1c)
+/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer1 reloading with phase on sync input event
+ *  is enabled.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
+#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER1_SYNCI_EN_S  0
+/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of software sync. Toggling this bit will trigger a
+ *  software sync.
+ */
+#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
+#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER1_SYNC_SW_S  1
+/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the selection of PWM timer1 sync_out.
+ *  0: Sync_in
+ *  1: TEZ
+ *  2: TEP
+ *  3: Invalid, sync_out selects noting
+ */
+#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
+#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_S  2
+/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  Configures the phase for timer1 reload on sync event.
+ */
+#define MCPWM_TIMER1_PHASE    0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
+#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_S  4
+/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configures the PWM timer1's direction when timer1 mode is up-down mode.
+ *  0: Increase
+ *  1: Decrease
+ */
+#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
+#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER1_STATUS_REG register
+ *  PWM timer1 status register.
+ */
+#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x20)
+/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  Represents current PWM timer1 counter value.
+ */
+#define MCPWM_TIMER1_VALUE    0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
+#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_S  0
+/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  Represents current PWM timer1 counter direction.
+ *  0: Increment
+ *  1: Decrement
+ */
+#define MCPWM_TIMER1_DIRECTION    (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
+#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_DIRECTION_S  16
+
+/** MCPWM_TIMER2_CFG0_REG register
+ *  PWM timer2 period and update method configuration register.
+ */
+#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x24)
+/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of timer2, so that the period of PT0_clk = Period of
+ *  PWM_clk * (PWM_TIMER2_PRESCALE + 1)
+ */
+#define MCPWM_TIMER2_PRESCALE    0x000000FFU
+#define MCPWM_TIMER2_PRESCALE_M  (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S)
+#define MCPWM_TIMER2_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER2_PRESCALE_S  0
+/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  Configures the period shadow of PWM timer2
+ */
+#define MCPWM_TIMER2_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER2_PERIOD_M  (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S)
+#define MCPWM_TIMER2_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER2_PERIOD_S  8
+/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Configures the update method for active register of PWM timer2 period.
+ *  0: Immediate
+ *  1: TEZ
+ *  2: Sync
+ *  3: TEZ or sync
+ *  TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER2_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER2_CFG1_REG register
+ *  PWM timer2 working mode and start/stop control register.
+ */
+#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x28)
+/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to start/stop PWM timer2.
+ *  0: If PWM timer2 starts, then stops at TEZ
+ *  1: If timer2 starts, then stops at TEP
+ *  2: PWM timer2 starts and runs on
+ *  3: Timer2 starts and stops at the next TEZ
+ *  4: Timer0 starts and stops at the next TEP.
+ *  TEP here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER2_START    0x00000007U
+#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
+#define MCPWM_TIMER2_START_V  0x00000007U
+#define MCPWM_TIMER2_START_S  0
+/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the working mode of PWM timer2.
+ *  0: Freeze
+ *  1: Increase mode
+ *  2: Decrease mode
+ *  3: Up-down mode
+ */
+#define MCPWM_TIMER2_MOD    0x00000003U
+#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
+#define MCPWM_TIMER2_MOD_V  0x00000003U
+#define MCPWM_TIMER2_MOD_S  3
+
+/** MCPWM_TIMER2_SYNC_REG register
+ *  PWM timer2 sync function configuration register.
+ */
+#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x2c)
+/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer2 reloading with phase on sync input event
+ *  is enabled.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
+#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER2_SYNCI_EN_S  0
+/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of software sync. Toggling this bit will trigger a
+ *  software sync.
+ */
+#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
+#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER2_SYNC_SW_S  1
+/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the selection of PWM timer2 sync_out.
+ *  0: Sync_in
+ *  1: TEZ
+ *  2: TEP
+ *  3: Invalid, sync_out selects noting
+ */
+#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
+#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_S  2
+/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  Configures the phase for timer2 reload on sync event.
+ */
+#define MCPWM_TIMER2_PHASE    0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
+#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_S  4
+/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configures the PWM timer2's direction when timer2 mode is up-down mode.
+ *  0: Increase
+ *  1: Decrease
+ */
+#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
+#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER2_STATUS_REG register
+ *  PWM timer2 status register.
+ */
+#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x30)
+/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  Represents current PWM timer2 counter value.
+ */
+#define MCPWM_TIMER2_VALUE    0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
+#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_S  0
+/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  Represents current PWM timer2 counter direction.
+ *  0: Increment
+ *  1: Decrement
+ */
+#define MCPWM_TIMER2_DIRECTION    (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
+#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_DIRECTION_S  16
+
+/** MCPWM_TIMER_SYNCI_CFG_REG register
+ *  Synchronization input selection register for PWM timers.
+ */
+#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x34)
+/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the selection of sync input for PWM timer0.
+ *  1: PWM timer0 sync_out
+ *  2: PWM timer1 sync_out
+ *  3: PWM timer2 sync_out
+ *  4: SYNC0 from GPIO matrix
+ *  5: SYNC1 from GPIO matrix
+ *  6: SYNC2 from GPIO matrix
+ *  Other values: No sync input selected
+ */
+#define MCPWM_TIMER0_SYNCISEL    0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
+#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_S  0
+/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
+ *  Configures the selection of sync input for PWM timer1.
+ *  1: PWM timer0 sync_out
+ *  2: PWM timer1 sync_out
+ *  3: PWM timer2 sync_out
+ *  4: SYNC0 from GPIO matrix
+ *  5: SYNC1 from GPIO matrix
+ *  6: SYNC2 from GPIO matrix
+ *  Other values: No sync input selected
+ */
+#define MCPWM_TIMER1_SYNCISEL    0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
+#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_S  3
+/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures the selection of sync input for PWM timer2.
+ *  1: PWM timer0 sync_out
+ *  2: PWM timer1 sync_out
+ *  3: PWM timer2 sync_out
+ *  4: SYNC0 from GPIO matrix
+ *  5: SYNC1 from GPIO matrix
+ *  6: SYNC2 from GPIO matrix
+ *  Other values: No sync input selected
+ */
+#define MCPWM_TIMER2_SYNCISEL    0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
+#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_S  6
+/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert SYNC0 from GPIO matrix.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
+/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to invert SYNC1 from GPIO matrix.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
+/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert SYNC2 from GPIO matrix.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
+
+/** MCPWM_OPERATOR_TIMERSEL_REG register
+ *  PWM operator's timer select register
+ */
+#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x38)
+/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which PWM timer will be the timing reference for PWM operator0.
+ *  0: Timer0
+ *  1: Timer1
+ *  2: Timer2
+ *  3: Invalid, will select timer2
+ */
+#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
+#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_S  0
+/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures which PWM timer will be the timing reference for PWM operator1.
+ *  0: Timer0
+ *  1: Timer1
+ *  2: Timer2
+ *  3: Invalid, will select timer2
+ */
+#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
+#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_S  2
+/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
+ *  Configures which PWM timer will be the timing reference for PWM operator2.
+ *  0: Timer0
+ *  1: Timer1
+ *  2: Timer2
+ *  3: Invalid, will select timer2
+ */
+#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
+#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_S  4
+
+/** MCPWM_GEN0_STMP_CFG_REG register
+ *  Generator0 time stamp registers A and B transfer status and update method register
+ */
+#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x3c)
+/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the update method for PWM generator 0 time stamp A's active register.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
+#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_S  0
+/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the update method for PWM generator 0 time stamp B's active register.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
+#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_S  4
+/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Represents whether or not generator0 time stamp A's shadow reg is transferred.
+ *  0: A's active reg has been updated with shadow register latest value.
+ *  1: A's shadow reg is filled and waiting to be transferred to A's active reg
+ */
+#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
+#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_A_SHDW_FULL_S  8
+/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Represents whether or not generator0 time stamp B's shadow reg is transferred.
+ *  0: B's active reg has been updated with shadow register latest value.
+ *  1: B's shadow reg is filled and waiting to be transferred to B's active reg
+ */
+#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
+#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN0_TSTMP_A_REG register
+ *  Generator0 time stamp A's shadow register
+ */
+#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x40)
+/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator 0 time stamp A's shadow register.
+ */
+#define MCPWM_CMPR0_A    0x0000FFFFU
+#define MCPWM_CMPR0_A_M  (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S)
+#define MCPWM_CMPR0_A_V  0x0000FFFFU
+#define MCPWM_CMPR0_A_S  0
+
+/** MCPWM_GEN0_TSTMP_B_REG register
+ *  Generator0 time stamp B's shadow register
+ */
+#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x44)
+/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator 0 time stamp B's shadow register.
+ */
+#define MCPWM_CMPR0_B    0x0000FFFFU
+#define MCPWM_CMPR0_B_M  (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S)
+#define MCPWM_CMPR0_B_V  0x0000FFFFU
+#define MCPWM_CMPR0_B_S  0
+
+/** MCPWM_GEN0_CFG0_REG register
+ *  Generator0 fault event T0 and T1 configuration register
+ */
+#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x48)
+/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for PWM generator 0's active register.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
+#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_S  0
+/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Configures source selection for PWM generator 0 event_t0, take effect immediately.
+ *  0: fault_event0
+ *  1: fault_event1
+ *  2: fault_event2
+ *  3: sync_taken
+ *  4: Invalid, Select nothing
+ */
+#define MCPWM_GEN0_T0_SEL    0x00000007U
+#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
+#define MCPWM_GEN0_T0_SEL_V  0x00000007U
+#define MCPWM_GEN0_T0_SEL_S  4
+/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Configures source selection for PWM generator 0 event_t1, take effect immediately.
+ *  0: fault_event0
+ *  1: fault_event1
+ *  2: fault_event2
+ *  3: sync_taken
+ *  4: Invalid, Select nothing
+ */
+#define MCPWM_GEN0_T1_SEL    0x00000007U
+#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
+#define MCPWM_GEN0_T1_SEL_V  0x00000007U
+#define MCPWM_GEN0_T1_SEL_S  7
+
+/** MCPWM_GEN0_FORCE_REG register
+ *  Generator0 output signal force mode register.
+ */
+#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x4c)
+/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Configures update method for continuous software force of PWM generator0.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: TEA
+ *  Bit3 is set to 1: TEB
+ *  Bit4 is set to 1: Sync
+ *  Bit5 is set to 1: Disable update. TEA/B here and below means an event generated
+ *  when the timer's value equals to that of register A/B.
+ */
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Configures continuous software force mode for PWM0 A.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Configures continuous software force mode for PWM0 B.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for PWM0
+ *  A, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
+#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_A_NCIFORCE_S  10
+/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM0 A.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for PWM0
+ *  B, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
+#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_B_NCIFORCE_S  13
+/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM0 B.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN0_A_REG register
+ *  PWM0 output signal A actions configuration register
+ */
+#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x50)
+/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM0 A triggered by event TEZ when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEZ    0x00000003U
+#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
+#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_UTEZ_S  0
+/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM0 A triggered by event TEP when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEP    0x00000003U
+#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
+#define MCPWM_GEN0_A_UTEP_V  0x00000003U
+#define MCPWM_GEN0_A_UTEP_S  2
+/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM0 A triggered by event TEA when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEA    0x00000003U
+#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
+#define MCPWM_GEN0_A_UTEA_V  0x00000003U
+#define MCPWM_GEN0_A_UTEA_S  4
+/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM0 A triggered by event TEB when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEB    0x00000003U
+#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
+#define MCPWM_GEN0_A_UTEB_V  0x00000003U
+#define MCPWM_GEN0_A_UTEB_S  6
+/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM0 A triggered by event_t0 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_UT0    0x00000003U
+#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
+#define MCPWM_GEN0_A_UT0_V  0x00000003U
+#define MCPWM_GEN0_A_UT0_S  8
+/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM0 A triggered by event_t1 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_UT1    0x00000003U
+#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
+#define MCPWM_GEN0_A_UT1_V  0x00000003U
+#define MCPWM_GEN0_A_UT1_S  10
+/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM0 A triggered by event TEZ when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEZ    0x00000003U
+#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
+#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_DTEZ_S  12
+/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM0 A triggered by event TEP when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEP    0x00000003U
+#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
+#define MCPWM_GEN0_A_DTEP_V  0x00000003U
+#define MCPWM_GEN0_A_DTEP_S  14
+/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM0 A triggered by event TEA when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEA    0x00000003U
+#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
+#define MCPWM_GEN0_A_DTEA_V  0x00000003U
+#define MCPWM_GEN0_A_DTEA_S  16
+/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM0 A triggered by event TEB when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEB    0x00000003U
+#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
+#define MCPWM_GEN0_A_DTEB_V  0x00000003U
+#define MCPWM_GEN0_A_DTEB_S  18
+/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM0 A triggered by event_t0 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_DT0    0x00000003U
+#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
+#define MCPWM_GEN0_A_DT0_V  0x00000003U
+#define MCPWM_GEN0_A_DT0_S  20
+/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM0 A triggered by event_t1 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_A_DT1    0x00000003U
+#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
+#define MCPWM_GEN0_A_DT1_V  0x00000003U
+#define MCPWM_GEN0_A_DT1_S  22
+
+/** MCPWM_GEN0_B_REG register
+ *  PWM0 output signal B actions configuration register
+ */
+#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x54)
+/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM0 B triggered by event TEZ when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEZ    0x00000003U
+#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
+#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_UTEZ_S  0
+/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM0 B triggered by event TEP when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEP    0x00000003U
+#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
+#define MCPWM_GEN0_B_UTEP_V  0x00000003U
+#define MCPWM_GEN0_B_UTEP_S  2
+/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM0 B triggered by event TEA when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEA    0x00000003U
+#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
+#define MCPWM_GEN0_B_UTEA_V  0x00000003U
+#define MCPWM_GEN0_B_UTEA_S  4
+/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM0 B triggered by event TEB when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEB    0x00000003U
+#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
+#define MCPWM_GEN0_B_UTEB_V  0x00000003U
+#define MCPWM_GEN0_B_UTEB_S  6
+/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM0 B triggered by event_t0 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_UT0    0x00000003U
+#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
+#define MCPWM_GEN0_B_UT0_V  0x00000003U
+#define MCPWM_GEN0_B_UT0_S  8
+/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM0 B triggered by event_t1 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_UT1    0x00000003U
+#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
+#define MCPWM_GEN0_B_UT1_V  0x00000003U
+#define MCPWM_GEN0_B_UT1_S  10
+/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM0 B triggered by event TEZ when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEZ    0x00000003U
+#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
+#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_DTEZ_S  12
+/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM0 B triggered by event TEP when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEP    0x00000003U
+#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
+#define MCPWM_GEN0_B_DTEP_V  0x00000003U
+#define MCPWM_GEN0_B_DTEP_S  14
+/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM0 B triggered by event TEA when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEA    0x00000003U
+#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
+#define MCPWM_GEN0_B_DTEA_V  0x00000003U
+#define MCPWM_GEN0_B_DTEA_S  16
+/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM0 B triggered by event TEB when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEB    0x00000003U
+#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
+#define MCPWM_GEN0_B_DTEB_V  0x00000003U
+#define MCPWM_GEN0_B_DTEB_S  18
+/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM0 B triggered by event_t0 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_DT0    0x00000003U
+#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
+#define MCPWM_GEN0_B_DT0_V  0x00000003U
+#define MCPWM_GEN0_B_DT0_S  20
+/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM0 B triggered by event_t1 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN0_B_DT1    0x00000003U
+#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
+#define MCPWM_GEN0_B_DT1_V  0x00000003U
+#define MCPWM_GEN0_B_DT1_S  22
+
+/** MCPWM_DT0_CFG_REG register
+ *  Dead time configuration register
+ */
+#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58)
+/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for FED (Falling edge delay) active register.
+ *  0: Immediate
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB0_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB0_FED_UPMETHOD_M  (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S)
+#define MCPWM_DB0_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB0_FED_UPMETHOD_S  0
+/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures update method for RED (rising edge delay) active register.
+ *  0: Immediate
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB0_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB0_RED_UPMETHOD_M  (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S)
+#define MCPWM_DB0_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB0_RED_UPMETHOD_S  4
+/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  Configures S8 in table, dual-edge B mode.
+ *  0: fed/red take effect on different path separately
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB0_DEB_MODE    (BIT(8))
+#define MCPWM_DB0_DEB_MODE_M  (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S)
+#define MCPWM_DB0_DEB_MODE_V  0x00000001U
+#define MCPWM_DB0_DEB_MODE_S  8
+/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  Configures S6 in table.
+ */
+#define MCPWM_DB0_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB0_A_OUTSWAP_M  (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S)
+#define MCPWM_DB0_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB0_A_OUTSWAP_S  9
+/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  Configures S7 in table.
+ */
+#define MCPWM_DB0_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB0_B_OUTSWAP_M  (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S)
+#define MCPWM_DB0_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB0_B_OUTSWAP_S  10
+/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  Configures S4 in table.
+ */
+#define MCPWM_DB0_RED_INSEL    (BIT(11))
+#define MCPWM_DB0_RED_INSEL_M  (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S)
+#define MCPWM_DB0_RED_INSEL_V  0x00000001U
+#define MCPWM_DB0_RED_INSEL_S  11
+/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  Configures S5 in table.
+ */
+#define MCPWM_DB0_FED_INSEL    (BIT(12))
+#define MCPWM_DB0_FED_INSEL_M  (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S)
+#define MCPWM_DB0_FED_INSEL_V  0x00000001U
+#define MCPWM_DB0_FED_INSEL_S  12
+/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures S2 in table.
+ */
+#define MCPWM_DB0_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB0_RED_OUTINVERT_M  (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S)
+#define MCPWM_DB0_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB0_RED_OUTINVERT_S  13
+/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  Configures S3 in table.
+ */
+#define MCPWM_DB0_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB0_FED_OUTINVERT_M  (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S)
+#define MCPWM_DB0_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB0_FED_OUTINVERT_S  14
+/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  Configures S1 in table.
+ */
+#define MCPWM_DB0_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB0_A_OUTBYPASS_M  (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S)
+#define MCPWM_DB0_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB0_A_OUTBYPASS_S  15
+/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  Configures S0 in table.
+ */
+#define MCPWM_DB0_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB0_B_OUTBYPASS_M  (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S)
+#define MCPWM_DB0_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB0_B_OUTBYPASS_S  16
+/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Configures dead time generator 0 clock selection.
+ *  0: PWM_clk
+ *  1: PT_clk
+ */
+#define MCPWM_DB0_CLK_SEL    (BIT(17))
+#define MCPWM_DB0_CLK_SEL_M  (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S)
+#define MCPWM_DB0_CLK_SEL_V  0x00000001U
+#define MCPWM_DB0_CLK_SEL_S  17
+
+/** MCPWM_DT0_FED_CFG_REG register
+ *  Falling edge delay (FED) shadow register
+ */
+#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5c)
+/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for FED.
+ */
+#define MCPWM_DB0_FED    0x0000FFFFU
+#define MCPWM_DB0_FED_M  (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S)
+#define MCPWM_DB0_FED_V  0x0000FFFFU
+#define MCPWM_DB0_FED_S  0
+
+/** MCPWM_DT0_RED_CFG_REG register
+ *  Rising edge delay (RED) shadow register
+ */
+#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60)
+/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for RED.
+ */
+#define MCPWM_DB0_RED    0x0000FFFFU
+#define MCPWM_DB0_RED_M  (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S)
+#define MCPWM_DB0_RED_V  0x0000FFFFU
+#define MCPWM_DB0_RED_S  0
+
+/** MCPWM_CARRIER0_CFG_REG register
+ *  Carrier0 configuration register
+ */
+#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64)
+/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable carrier0.
+ *  0: Bypassed
+ *  1: Enabled
+ */
+#define MCPWM_CHOPPER0_EN    (BIT(0))
+#define MCPWM_CHOPPER0_EN_M  (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S)
+#define MCPWM_CHOPPER0_EN_V  0x00000001U
+#define MCPWM_CHOPPER0_EN_S  0
+/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  Configures the prescale value of PWM carrier0 clock (PC_clk), so that period of
+ *  PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER0_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER0_PRESCALE_M  (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S)
+#define MCPWM_CHOPPER0_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER0_PRESCALE_S  1
+/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  Configures carrier duty. Duty = PWM_CARRIER0_DUTY / 8
+ */
+#define MCPWM_CHOPPER0_DUTY    0x00000007U
+#define MCPWM_CHOPPER0_DUTY_M  (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S)
+#define MCPWM_CHOPPER0_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER0_DUTY_S  5
+/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+ */
+#define MCPWM_CHOPPER0_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER0_OSHTWTH_M  (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S)
+#define MCPWM_CHOPPER0_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER0_OSHTWTH_S  8
+/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to invert the output of PWM0 A and PWM0 B for this
+ *  submodule.
+ *  0: Normal
+ *  1: Invert
+ */
+#define MCPWM_CHOPPER0_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER0_OUT_INVERT_M  (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S)
+#define MCPWM_CHOPPER0_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER0_OUT_INVERT_S  12
+/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to invert the input of PWM0 A and PWM0 B for this
+ *  submodule.
+ *  0: Normal
+ *  1: Invert
+ */
+#define MCPWM_CHOPPER0_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER0_IN_INVERT_M  (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S)
+#define MCPWM_CHOPPER0_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER0_IN_INVERT_S  13
+
+/** MCPWM_FH0_CFG0_REG register
+ *  PWM0 A and PWM0 B trip events actions configuration register
+ */
+#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x68)
+/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable software force cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ0_SW_CBC    (BIT(0))
+#define MCPWM_TZ0_SW_CBC_M  (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S)
+#define MCPWM_TZ0_SW_CBC_V  0x00000001U
+#define MCPWM_TZ0_SW_CBC_S  0
+/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ0_F2_CBC    (BIT(1))
+#define MCPWM_TZ0_F2_CBC_M  (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S)
+#define MCPWM_TZ0_F2_CBC_V  0x00000001U
+#define MCPWM_TZ0_F2_CBC_S  1
+/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ0_F1_CBC    (BIT(2))
+#define MCPWM_TZ0_F1_CBC_M  (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S)
+#define MCPWM_TZ0_F1_CBC_V  0x00000001U
+#define MCPWM_TZ0_F1_CBC_S  2
+/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ0_F0_CBC    (BIT(3))
+#define MCPWM_TZ0_F0_CBC_M  (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S)
+#define MCPWM_TZ0_F0_CBC_V  0x00000001U
+#define MCPWM_TZ0_F0_CBC_S  3
+/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable software force one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ0_SW_OST    (BIT(4))
+#define MCPWM_TZ0_SW_OST_M  (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S)
+#define MCPWM_TZ0_SW_OST_V  0x00000001U
+#define MCPWM_TZ0_SW_OST_S  4
+/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not event_f2 will trigger one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ0_F2_OST    (BIT(5))
+#define MCPWM_TZ0_F2_OST_M  (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S)
+#define MCPWM_TZ0_F2_OST_V  0x00000001U
+#define MCPWM_TZ0_F2_OST_S  5
+/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not event_f1 will trigger one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ0_F1_OST    (BIT(6))
+#define MCPWM_TZ0_F1_OST_M  (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S)
+#define MCPWM_TZ0_F1_OST_V  0x00000001U
+#define MCPWM_TZ0_F1_OST_S  6
+/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not event_f0 will trigger one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ0_F0_OST    (BIT(7))
+#define MCPWM_TZ0_F0_OST_M  (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S)
+#define MCPWM_TZ0_F0_OST_V  0x00000001U
+#define MCPWM_TZ0_F0_OST_S  7
+/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM0 A when fault event occurs and timer
+ *  is decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ0_A_CBC_D    0x00000003U
+#define MCPWM_TZ0_A_CBC_D_M  (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S)
+#define MCPWM_TZ0_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ0_A_CBC_D_S  8
+/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM0 A when fault event occurs and timer
+ *  is increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ0_A_CBC_U    0x00000003U
+#define MCPWM_TZ0_A_CBC_U_M  (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S)
+#define MCPWM_TZ0_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ0_A_CBC_U_S  10
+/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  Configures one-shot mode action on PWM0 A when fault event occurs and timer is
+ *  decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ0_A_OST_D    0x00000003U
+#define MCPWM_TZ0_A_OST_D_M  (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S)
+#define MCPWM_TZ0_A_OST_D_V  0x00000003U
+#define MCPWM_TZ0_A_OST_D_S  12
+/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  Configures one-shot mode action on PWM0 A when fault event occurs and timer is
+ *  increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ0_A_OST_U    0x00000003U
+#define MCPWM_TZ0_A_OST_U_M  (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S)
+#define MCPWM_TZ0_A_OST_U_V  0x00000003U
+#define MCPWM_TZ0_A_OST_U_S  14
+/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM0 B when fault event occurs and timer
+ *  is decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ0_B_CBC_D    0x00000003U
+#define MCPWM_TZ0_B_CBC_D_M  (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S)
+#define MCPWM_TZ0_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ0_B_CBC_D_S  16
+/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM0 B when fault event occurs and timer
+ *  is increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ0_B_CBC_U    0x00000003U
+#define MCPWM_TZ0_B_CBC_U_M  (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S)
+#define MCPWM_TZ0_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ0_B_CBC_U_S  18
+/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  Configures one-shot mode action on PWM0 B when fault event occurs and timer is
+ *  decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ0_B_OST_D    0x00000003U
+#define MCPWM_TZ0_B_OST_D_M  (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S)
+#define MCPWM_TZ0_B_OST_D_V  0x00000003U
+#define MCPWM_TZ0_B_OST_D_S  20
+/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  Configures one-shot mode action on PWM0 B when fault event occurs and timer is
+ *  increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ0_B_OST_U    0x00000003U
+#define MCPWM_TZ0_B_OST_U_M  (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S)
+#define MCPWM_TZ0_B_OST_U_V  0x00000003U
+#define MCPWM_TZ0_B_OST_U_S  22
+
+/** MCPWM_FH0_CFG1_REG register
+ *  Software triggers for fault handler actions configuration register
+ */
+#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x6c)
+/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  Configures the generation of software one-shot mode action clear. A toggle
+ *  (software negate its value) triggers a clear for on going one-shot mode action.
+ */
+#define MCPWM_TZ0_CLR_OST    (BIT(0))
+#define MCPWM_TZ0_CLR_OST_M  (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S)
+#define MCPWM_TZ0_CLR_OST_V  0x00000001U
+#define MCPWM_TZ0_CLR_OST_S  0
+/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures the refresh moment selection of cycle-by-cycle mode action.
+ *  0: Select nothing, will not refresh
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ */
+#define MCPWM_TZ0_CBCPULSE    0x00000003U
+#define MCPWM_TZ0_CBCPULSE_M  (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S)
+#define MCPWM_TZ0_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ0_CBCPULSE_S  1
+/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of software cycle-by-cycle mode action. A toggle
+ *  (software negate its value) triggers a cycle-by-cycle mode action.
+ */
+#define MCPWM_TZ0_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ0_FORCE_CBC_M  (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S)
+#define MCPWM_TZ0_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ0_FORCE_CBC_S  3
+/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures the generation of software one-shot mode action. A toggle (software
+ *  negate its value) triggers a one-shot mode action.
+ */
+#define MCPWM_TZ0_FORCE_OST    (BIT(4))
+#define MCPWM_TZ0_FORCE_OST_M  (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S)
+#define MCPWM_TZ0_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ0_FORCE_OST_S  4
+
+/** MCPWM_FH0_STATUS_REG register
+ *  Fault events status register
+ */
+#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x70)
+/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an cycle-by-cycle mode action is on going.
+ *  0:No action
+ *  1: On going
+ */
+#define MCPWM_TZ0_CBC_ON    (BIT(0))
+#define MCPWM_TZ0_CBC_ON_M  (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S)
+#define MCPWM_TZ0_CBC_ON_V  0x00000001U
+#define MCPWM_TZ0_CBC_ON_S  0
+/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not an one-shot mode action is on going.
+ *  0:No action
+ *  1: On going
+ */
+#define MCPWM_TZ0_OST_ON    (BIT(1))
+#define MCPWM_TZ0_OST_ON_M  (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S)
+#define MCPWM_TZ0_OST_ON_V  0x00000001U
+#define MCPWM_TZ0_OST_ON_S  1
+
+/** MCPWM_GEN1_STMP_CFG_REG register
+ *  Generator1 time stamp registers A and B transfer status and update method register
+ */
+#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x74)
+/** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the update method for PWM generator 1 time stamp A's active register.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR1_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR1_A_UPMETHOD_M  (MCPWM_CMPR1_A_UPMETHOD_V << MCPWM_CMPR1_A_UPMETHOD_S)
+#define MCPWM_CMPR1_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR1_A_UPMETHOD_S  0
+/** MCPWM_CMPR1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the update method for PWM generator 1 time stamp B's active register.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR1_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR1_B_UPMETHOD_M  (MCPWM_CMPR1_B_UPMETHOD_V << MCPWM_CMPR1_B_UPMETHOD_S)
+#define MCPWM_CMPR1_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR1_B_UPMETHOD_S  4
+/** MCPWM_CMPR1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Represents whether or not generator1 time stamp A's shadow reg is transferred.
+ *  0: A's active reg has been updated with shadow register latest value.
+ *  1: A's shadow reg is filled and waiting to be transferred to A's active reg
+ */
+#define MCPWM_CMPR1_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR1_A_SHDW_FULL_M  (MCPWM_CMPR1_A_SHDW_FULL_V << MCPWM_CMPR1_A_SHDW_FULL_S)
+#define MCPWM_CMPR1_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR1_A_SHDW_FULL_S  8
+/** MCPWM_CMPR1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Represents whether or not generator1 time stamp B's shadow reg is transferred.
+ *  0: B's active reg has been updated with shadow register latest value.
+ *  1: B's shadow reg is filled and waiting to be transferred to B's active reg
+ */
+#define MCPWM_CMPR1_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR1_B_SHDW_FULL_M  (MCPWM_CMPR1_B_SHDW_FULL_V << MCPWM_CMPR1_B_SHDW_FULL_S)
+#define MCPWM_CMPR1_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR1_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN1_TSTMP_A_REG register
+ *  Generator1 time stamp A's shadow register
+ */
+#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x78)
+/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator 1 time stamp A's shadow register.
+ */
+#define MCPWM_CMPR1_A    0x0000FFFFU
+#define MCPWM_CMPR1_A_M  (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S)
+#define MCPWM_CMPR1_A_V  0x0000FFFFU
+#define MCPWM_CMPR1_A_S  0
+
+/** MCPWM_GEN1_TSTMP_B_REG register
+ *  Generator1 time stamp B's shadow register
+ */
+#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x7c)
+/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator 1 time stamp B's shadow register.
+ */
+#define MCPWM_CMPR1_B    0x0000FFFFU
+#define MCPWM_CMPR1_B_M  (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S)
+#define MCPWM_CMPR1_B_V  0x0000FFFFU
+#define MCPWM_CMPR1_B_S  0
+
+/** MCPWM_GEN1_CFG0_REG register
+ *  Generator1 fault event T0 and T1 configuration register
+ */
+#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x80)
+/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for PWM generator 1's active register.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
+#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_S  0
+/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Configures source selection for PWM generator 1 event_t0, take effect immediately.
+ *  0: fault_event0
+ *  1: fault_event1
+ *  2: fault_event2
+ *  3: sync_taken
+ *  4: Invalid, Select nothing
+ */
+#define MCPWM_GEN1_T0_SEL    0x00000007U
+#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
+#define MCPWM_GEN1_T0_SEL_V  0x00000007U
+#define MCPWM_GEN1_T0_SEL_S  4
+/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Configures source selection for PWM generator 1 event_t1, take effect immediately.
+ *  0: fault_event0
+ *  1: fault_event1
+ *  2: fault_event2
+ *  3: sync_taken
+ *  4: Invalid, Select nothing
+ */
+#define MCPWM_GEN1_T1_SEL    0x00000007U
+#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
+#define MCPWM_GEN1_T1_SEL_V  0x00000007U
+#define MCPWM_GEN1_T1_SEL_S  7
+
+/** MCPWM_GEN1_FORCE_REG register
+ *  Generator1 output signal force mode register.
+ */
+#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x84)
+/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Configures update method for continuous software force of PWM generator1.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: TEA
+ *  Bit3 is set to 1: TEB
+ *  Bit4 is set to 1: Sync
+ *  Bit5 is set to 1: Disable update. TEA/B here and below means an event generated
+ *  when the timer's value equals to that of register A/B.
+ */
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Configures continuous software force mode for PWM1 A.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Configures continuous software force mode for PWM1 B.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for PWM1
+ *  A, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
+#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_A_NCIFORCE_S  10
+/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM1 A.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for PWM1
+ *  B, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
+#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_B_NCIFORCE_S  13
+/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM1 B.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN1_A_REG register
+ *  PWM1 output signal A actions configuration register
+ */
+#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x88)
+/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM1 A triggered by event TEZ when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEZ    0x00000003U
+#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
+#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_UTEZ_S  0
+/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM1 A triggered by event TEP when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEP    0x00000003U
+#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
+#define MCPWM_GEN1_A_UTEP_V  0x00000003U
+#define MCPWM_GEN1_A_UTEP_S  2
+/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM1 A triggered by event TEA when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEA    0x00000003U
+#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
+#define MCPWM_GEN1_A_UTEA_V  0x00000003U
+#define MCPWM_GEN1_A_UTEA_S  4
+/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM1 A triggered by event TEB when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEB    0x00000003U
+#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
+#define MCPWM_GEN1_A_UTEB_V  0x00000003U
+#define MCPWM_GEN1_A_UTEB_S  6
+/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM1 A triggered by event_t0 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_UT0    0x00000003U
+#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
+#define MCPWM_GEN1_A_UT0_V  0x00000003U
+#define MCPWM_GEN1_A_UT0_S  8
+/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM1 A triggered by event_t1 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_UT1    0x00000003U
+#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
+#define MCPWM_GEN1_A_UT1_V  0x00000003U
+#define MCPWM_GEN1_A_UT1_S  10
+/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM1 A triggered by event TEZ when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEZ    0x00000003U
+#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
+#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_DTEZ_S  12
+/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM1 A triggered by event TEP when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEP    0x00000003U
+#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
+#define MCPWM_GEN1_A_DTEP_V  0x00000003U
+#define MCPWM_GEN1_A_DTEP_S  14
+/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM1 A triggered by event TEA when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEA    0x00000003U
+#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
+#define MCPWM_GEN1_A_DTEA_V  0x00000003U
+#define MCPWM_GEN1_A_DTEA_S  16
+/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM1 A triggered by event TEB when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEB    0x00000003U
+#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
+#define MCPWM_GEN1_A_DTEB_V  0x00000003U
+#define MCPWM_GEN1_A_DTEB_S  18
+/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM1 A triggered by event_t0 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_DT0    0x00000003U
+#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
+#define MCPWM_GEN1_A_DT0_V  0x00000003U
+#define MCPWM_GEN1_A_DT0_S  20
+/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM1 A triggered by event_t1 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_A_DT1    0x00000003U
+#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
+#define MCPWM_GEN1_A_DT1_V  0x00000003U
+#define MCPWM_GEN1_A_DT1_S  22
+
+/** MCPWM_GEN1_B_REG register
+ *  PWM1 output signal B actions configuration register
+ */
+#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x8c)
+/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM1 B triggered by event TEZ when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEZ    0x00000003U
+#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
+#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_UTEZ_S  0
+/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM1 B triggered by event TEP when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEP    0x00000003U
+#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
+#define MCPWM_GEN1_B_UTEP_V  0x00000003U
+#define MCPWM_GEN1_B_UTEP_S  2
+/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM1 B triggered by event TEA when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEA    0x00000003U
+#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
+#define MCPWM_GEN1_B_UTEA_V  0x00000003U
+#define MCPWM_GEN1_B_UTEA_S  4
+/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM1 B triggered by event TEB when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEB    0x00000003U
+#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
+#define MCPWM_GEN1_B_UTEB_V  0x00000003U
+#define MCPWM_GEN1_B_UTEB_S  6
+/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM1 B triggered by event_t0 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_UT0    0x00000003U
+#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
+#define MCPWM_GEN1_B_UT0_V  0x00000003U
+#define MCPWM_GEN1_B_UT0_S  8
+/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM1 B triggered by event_t1 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_UT1    0x00000003U
+#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
+#define MCPWM_GEN1_B_UT1_V  0x00000003U
+#define MCPWM_GEN1_B_UT1_S  10
+/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM1 B triggered by event TEZ when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEZ    0x00000003U
+#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
+#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_DTEZ_S  12
+/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM1 B triggered by event TEP when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEP    0x00000003U
+#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
+#define MCPWM_GEN1_B_DTEP_V  0x00000003U
+#define MCPWM_GEN1_B_DTEP_S  14
+/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM1 B triggered by event TEA when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEA    0x00000003U
+#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
+#define MCPWM_GEN1_B_DTEA_V  0x00000003U
+#define MCPWM_GEN1_B_DTEA_S  16
+/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM1 B triggered by event TEB when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEB    0x00000003U
+#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
+#define MCPWM_GEN1_B_DTEB_V  0x00000003U
+#define MCPWM_GEN1_B_DTEB_S  18
+/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM1 B triggered by event_t0 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_DT0    0x00000003U
+#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
+#define MCPWM_GEN1_B_DT0_V  0x00000003U
+#define MCPWM_GEN1_B_DT0_S  20
+/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM1 B triggered by event_t1 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN1_B_DT1    0x00000003U
+#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
+#define MCPWM_GEN1_B_DT1_V  0x00000003U
+#define MCPWM_GEN1_B_DT1_S  22
+
+/** MCPWM_DT1_CFG_REG register
+ *  Dead time configuration register
+ */
+#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90)
+/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for FED (Falling edge delay) active register.
+ *  0: Immediate
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB1_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB1_FED_UPMETHOD_M  (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S)
+#define MCPWM_DB1_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB1_FED_UPMETHOD_S  0
+/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures update method for RED (rising edge delay) active register.
+ *  0: Immediate
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB1_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB1_RED_UPMETHOD_M  (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S)
+#define MCPWM_DB1_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB1_RED_UPMETHOD_S  4
+/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  Configures S8 in table, dual-edge B mode.
+ *  0: fed/red take effect on different path separately
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB1_DEB_MODE    (BIT(8))
+#define MCPWM_DB1_DEB_MODE_M  (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S)
+#define MCPWM_DB1_DEB_MODE_V  0x00000001U
+#define MCPWM_DB1_DEB_MODE_S  8
+/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  Configures S6 in table.
+ */
+#define MCPWM_DB1_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB1_A_OUTSWAP_M  (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S)
+#define MCPWM_DB1_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB1_A_OUTSWAP_S  9
+/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  Configures S7 in table.
+ */
+#define MCPWM_DB1_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB1_B_OUTSWAP_M  (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S)
+#define MCPWM_DB1_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB1_B_OUTSWAP_S  10
+/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  Configures S4 in table.
+ */
+#define MCPWM_DB1_RED_INSEL    (BIT(11))
+#define MCPWM_DB1_RED_INSEL_M  (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S)
+#define MCPWM_DB1_RED_INSEL_V  0x00000001U
+#define MCPWM_DB1_RED_INSEL_S  11
+/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  Configures S5 in table.
+ */
+#define MCPWM_DB1_FED_INSEL    (BIT(12))
+#define MCPWM_DB1_FED_INSEL_M  (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S)
+#define MCPWM_DB1_FED_INSEL_V  0x00000001U
+#define MCPWM_DB1_FED_INSEL_S  12
+/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures S2 in table.
+ */
+#define MCPWM_DB1_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB1_RED_OUTINVERT_M  (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S)
+#define MCPWM_DB1_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB1_RED_OUTINVERT_S  13
+/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  Configures S3 in table.
+ */
+#define MCPWM_DB1_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB1_FED_OUTINVERT_M  (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S)
+#define MCPWM_DB1_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB1_FED_OUTINVERT_S  14
+/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  Configures S1 in table.
+ */
+#define MCPWM_DB1_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB1_A_OUTBYPASS_M  (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S)
+#define MCPWM_DB1_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB1_A_OUTBYPASS_S  15
+/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  Configures S0 in table.
+ */
+#define MCPWM_DB1_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB1_B_OUTBYPASS_M  (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S)
+#define MCPWM_DB1_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB1_B_OUTBYPASS_S  16
+/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Configures dead time generator 1 clock selection.
+ *  0: PWM_clk
+ *  1: PT_clk
+ */
+#define MCPWM_DB1_CLK_SEL    (BIT(17))
+#define MCPWM_DB1_CLK_SEL_M  (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S)
+#define MCPWM_DB1_CLK_SEL_V  0x00000001U
+#define MCPWM_DB1_CLK_SEL_S  17
+
+/** MCPWM_DT1_FED_CFG_REG register
+ *  Falling edge delay (FED) shadow register
+ */
+#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94)
+/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for FED.
+ */
+#define MCPWM_DB1_FED    0x0000FFFFU
+#define MCPWM_DB1_FED_M  (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S)
+#define MCPWM_DB1_FED_V  0x0000FFFFU
+#define MCPWM_DB1_FED_S  0
+
+/** MCPWM_DT1_RED_CFG_REG register
+ *  Rising edge delay (RED) shadow register
+ */
+#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98)
+/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for RED.
+ */
+#define MCPWM_DB1_RED    0x0000FFFFU
+#define MCPWM_DB1_RED_M  (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S)
+#define MCPWM_DB1_RED_V  0x0000FFFFU
+#define MCPWM_DB1_RED_S  0
+
+/** MCPWM_CARRIER1_CFG_REG register
+ *  Carrier1 configuration register
+ */
+#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9c)
+/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable carrier1.
+ *  0: Bypassed
+ *  1: Enabled
+ */
+#define MCPWM_CHOPPER1_EN    (BIT(0))
+#define MCPWM_CHOPPER1_EN_M  (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S)
+#define MCPWM_CHOPPER1_EN_V  0x00000001U
+#define MCPWM_CHOPPER1_EN_S  0
+/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  Configures the prescale value of PWM carrier1 clock (PC_clk), so that period of
+ *  PC_clk = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER1_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER1_PRESCALE_M  (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S)
+#define MCPWM_CHOPPER1_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER1_PRESCALE_S  1
+/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  Configures carrier duty. Duty = PWM_CARRIER1_DUTY / 8
+ */
+#define MCPWM_CHOPPER1_DUTY    0x00000007U
+#define MCPWM_CHOPPER1_DUTY_M  (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S)
+#define MCPWM_CHOPPER1_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER1_DUTY_S  5
+/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+ */
+#define MCPWM_CHOPPER1_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER1_OSHTWTH_M  (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S)
+#define MCPWM_CHOPPER1_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER1_OSHTWTH_S  8
+/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to invert the output of PWM1 A and PWM1 B for this
+ *  submodule.
+ *  0: Normal
+ *  1: Invert
+ */
+#define MCPWM_CHOPPER1_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER1_OUT_INVERT_M  (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S)
+#define MCPWM_CHOPPER1_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER1_OUT_INVERT_S  12
+/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to invert the input of PWM1 A and PWM1 B for this
+ *  submodule.
+ *  0: Normal
+ *  1: Invert
+ */
+#define MCPWM_CHOPPER1_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER1_IN_INVERT_M  (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S)
+#define MCPWM_CHOPPER1_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER1_IN_INVERT_S  13
+
+/** MCPWM_FH1_CFG0_REG register
+ *  PWM1 A and PWM1 B trip events actions configuration register
+ */
+#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xa0)
+/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable software force cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ1_SW_CBC    (BIT(0))
+#define MCPWM_TZ1_SW_CBC_M  (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S)
+#define MCPWM_TZ1_SW_CBC_V  0x00000001U
+#define MCPWM_TZ1_SW_CBC_S  0
+/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ1_F2_CBC    (BIT(1))
+#define MCPWM_TZ1_F2_CBC_M  (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S)
+#define MCPWM_TZ1_F2_CBC_V  0x00000001U
+#define MCPWM_TZ1_F2_CBC_S  1
+/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ1_F1_CBC    (BIT(2))
+#define MCPWM_TZ1_F1_CBC_M  (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S)
+#define MCPWM_TZ1_F1_CBC_V  0x00000001U
+#define MCPWM_TZ1_F1_CBC_S  2
+/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ1_F0_CBC    (BIT(3))
+#define MCPWM_TZ1_F0_CBC_M  (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S)
+#define MCPWM_TZ1_F0_CBC_V  0x00000001U
+#define MCPWM_TZ1_F0_CBC_S  3
+/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable software force one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ1_SW_OST    (BIT(4))
+#define MCPWM_TZ1_SW_OST_M  (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S)
+#define MCPWM_TZ1_SW_OST_V  0x00000001U
+#define MCPWM_TZ1_SW_OST_S  4
+/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not event_f2 will trigger one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ1_F2_OST    (BIT(5))
+#define MCPWM_TZ1_F2_OST_M  (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S)
+#define MCPWM_TZ1_F2_OST_V  0x00000001U
+#define MCPWM_TZ1_F2_OST_S  5
+/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not event_f1 will trigger one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ1_F1_OST    (BIT(6))
+#define MCPWM_TZ1_F1_OST_M  (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S)
+#define MCPWM_TZ1_F1_OST_V  0x00000001U
+#define MCPWM_TZ1_F1_OST_S  6
+/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not event_f0 will trigger one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ1_F0_OST    (BIT(7))
+#define MCPWM_TZ1_F0_OST_M  (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S)
+#define MCPWM_TZ1_F0_OST_V  0x00000001U
+#define MCPWM_TZ1_F0_OST_S  7
+/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM1 A when fault event occurs and timer
+ *  is decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ1_A_CBC_D    0x00000003U
+#define MCPWM_TZ1_A_CBC_D_M  (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S)
+#define MCPWM_TZ1_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ1_A_CBC_D_S  8
+/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM1 A when fault event occurs and timer
+ *  is increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ1_A_CBC_U    0x00000003U
+#define MCPWM_TZ1_A_CBC_U_M  (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S)
+#define MCPWM_TZ1_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ1_A_CBC_U_S  10
+/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  Configures one-shot mode action on PWM1 A when fault event occurs and timer is
+ *  decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ1_A_OST_D    0x00000003U
+#define MCPWM_TZ1_A_OST_D_M  (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S)
+#define MCPWM_TZ1_A_OST_D_V  0x00000003U
+#define MCPWM_TZ1_A_OST_D_S  12
+/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  Configures one-shot mode action on PWM1 A when fault event occurs and timer is
+ *  increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ1_A_OST_U    0x00000003U
+#define MCPWM_TZ1_A_OST_U_M  (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S)
+#define MCPWM_TZ1_A_OST_U_V  0x00000003U
+#define MCPWM_TZ1_A_OST_U_S  14
+/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM1 B when fault event occurs and timer
+ *  is decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ1_B_CBC_D    0x00000003U
+#define MCPWM_TZ1_B_CBC_D_M  (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S)
+#define MCPWM_TZ1_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ1_B_CBC_D_S  16
+/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM1 B when fault event occurs and timer
+ *  is increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ1_B_CBC_U    0x00000003U
+#define MCPWM_TZ1_B_CBC_U_M  (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S)
+#define MCPWM_TZ1_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ1_B_CBC_U_S  18
+/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  Configures one-shot mode action on PWM1 B when fault event occurs and timer is
+ *  decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ1_B_OST_D    0x00000003U
+#define MCPWM_TZ1_B_OST_D_M  (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S)
+#define MCPWM_TZ1_B_OST_D_V  0x00000003U
+#define MCPWM_TZ1_B_OST_D_S  20
+/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  Configures one-shot mode action on PWM1 B when fault event occurs and timer is
+ *  increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ1_B_OST_U    0x00000003U
+#define MCPWM_TZ1_B_OST_U_M  (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S)
+#define MCPWM_TZ1_B_OST_U_V  0x00000003U
+#define MCPWM_TZ1_B_OST_U_S  22
+
+/** MCPWM_FH1_CFG1_REG register
+ *  Software triggers for fault handler actions configuration register
+ */
+#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xa4)
+/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  Configures the generation of software one-shot mode action clear. A toggle
+ *  (software negate its value) triggers a clear for on going one-shot mode action.
+ */
+#define MCPWM_TZ1_CLR_OST    (BIT(0))
+#define MCPWM_TZ1_CLR_OST_M  (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S)
+#define MCPWM_TZ1_CLR_OST_V  0x00000001U
+#define MCPWM_TZ1_CLR_OST_S  0
+/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures the refresh moment selection of cycle-by-cycle mode action.
+ *  0: Select nothing, will not refresh
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ */
+#define MCPWM_TZ1_CBCPULSE    0x00000003U
+#define MCPWM_TZ1_CBCPULSE_M  (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S)
+#define MCPWM_TZ1_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ1_CBCPULSE_S  1
+/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of software cycle-by-cycle mode action. A toggle
+ *  (software negate its value) triggers a cycle-by-cycle mode action.
+ */
+#define MCPWM_TZ1_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ1_FORCE_CBC_M  (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S)
+#define MCPWM_TZ1_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ1_FORCE_CBC_S  3
+/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures the generation of software one-shot mode action. A toggle (software
+ *  negate its value) triggers a one-shot mode action.
+ */
+#define MCPWM_TZ1_FORCE_OST    (BIT(4))
+#define MCPWM_TZ1_FORCE_OST_M  (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S)
+#define MCPWM_TZ1_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ1_FORCE_OST_S  4
+
+/** MCPWM_FH1_STATUS_REG register
+ *  Fault events status register
+ */
+#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xa8)
+/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an cycle-by-cycle mode action is on going.
+ *  0:No action
+ *  1: On going
+ */
+#define MCPWM_TZ1_CBC_ON    (BIT(0))
+#define MCPWM_TZ1_CBC_ON_M  (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S)
+#define MCPWM_TZ1_CBC_ON_V  0x00000001U
+#define MCPWM_TZ1_CBC_ON_S  0
+/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not an one-shot mode action is on going.
+ *  0:No action
+ *  1: On going
+ */
+#define MCPWM_TZ1_OST_ON    (BIT(1))
+#define MCPWM_TZ1_OST_ON_M  (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S)
+#define MCPWM_TZ1_OST_ON_V  0x00000001U
+#define MCPWM_TZ1_OST_ON_S  1
+
+/** MCPWM_GEN2_STMP_CFG_REG register
+ *  Generator2 time stamp registers A and B transfer status and update method register
+ */
+#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xac)
+/** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the update method for PWM generator 2 time stamp A's active register.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR2_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR2_A_UPMETHOD_M  (MCPWM_CMPR2_A_UPMETHOD_V << MCPWM_CMPR2_A_UPMETHOD_S)
+#define MCPWM_CMPR2_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR2_A_UPMETHOD_S  0
+/** MCPWM_CMPR2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the update method for PWM generator 2 time stamp B's active register.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR2_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR2_B_UPMETHOD_M  (MCPWM_CMPR2_B_UPMETHOD_V << MCPWM_CMPR2_B_UPMETHOD_S)
+#define MCPWM_CMPR2_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR2_B_UPMETHOD_S  4
+/** MCPWM_CMPR2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Represents whether or not generator2 time stamp A's shadow reg is transferred.
+ *  0: A's active reg has been updated with shadow register latest value.
+ *  1: A's shadow reg is filled and waiting to be transferred to A's active reg
+ */
+#define MCPWM_CMPR2_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR2_A_SHDW_FULL_M  (MCPWM_CMPR2_A_SHDW_FULL_V << MCPWM_CMPR2_A_SHDW_FULL_S)
+#define MCPWM_CMPR2_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR2_A_SHDW_FULL_S  8
+/** MCPWM_CMPR2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Represents whether or not generator2 time stamp B's shadow reg is transferred.
+ *  0: B's active reg has been updated with shadow register latest value.
+ *  1: B's shadow reg is filled and waiting to be transferred to B's active reg
+ */
+#define MCPWM_CMPR2_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR2_B_SHDW_FULL_M  (MCPWM_CMPR2_B_SHDW_FULL_V << MCPWM_CMPR2_B_SHDW_FULL_S)
+#define MCPWM_CMPR2_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR2_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN2_TSTMP_A_REG register
+ *  Generator2 time stamp A's shadow register
+ */
+#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0xb0)
+/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator 2 time stamp A's shadow register.
+ */
+#define MCPWM_CMPR2_A    0x0000FFFFU
+#define MCPWM_CMPR2_A_M  (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S)
+#define MCPWM_CMPR2_A_V  0x0000FFFFU
+#define MCPWM_CMPR2_A_S  0
+
+/** MCPWM_GEN2_TSTMP_B_REG register
+ *  Generator2 time stamp B's shadow register
+ */
+#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0xb4)
+/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator 2 time stamp B's shadow register.
+ */
+#define MCPWM_CMPR2_B    0x0000FFFFU
+#define MCPWM_CMPR2_B_M  (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S)
+#define MCPWM_CMPR2_B_V  0x0000FFFFU
+#define MCPWM_CMPR2_B_S  0
+
+/** MCPWM_GEN2_CFG0_REG register
+ *  Generator2 fault event T0 and T1 configuration register
+ */
+#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xb8)
+/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for PWM generator 2's active register.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
+#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_S  0
+/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Configures source selection for PWM generator 2 event_t0, take effect immediately.
+ *  0: fault_event0
+ *  1: fault_event1
+ *  2: fault_event2
+ *  3: sync_taken
+ *  4: Invalid, Select nothing
+ */
+#define MCPWM_GEN2_T0_SEL    0x00000007U
+#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
+#define MCPWM_GEN2_T0_SEL_V  0x00000007U
+#define MCPWM_GEN2_T0_SEL_S  4
+/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Configures source selection for PWM generator 2 event_t1, take effect immediately.
+ *  0: fault_event0
+ *  1: fault_event1
+ *  2: fault_event2
+ *  3: sync_taken
+ *  4: Invalid, Select nothing
+ */
+#define MCPWM_GEN2_T1_SEL    0x00000007U
+#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
+#define MCPWM_GEN2_T1_SEL_V  0x00000007U
+#define MCPWM_GEN2_T1_SEL_S  7
+
+/** MCPWM_GEN2_FORCE_REG register
+ *  Generator2 output signal force mode register.
+ */
+#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xbc)
+/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Configures update method for continuous software force of PWM generator2.
+ *  0: Immediately
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: TEA
+ *  Bit3 is set to 1: TEB
+ *  Bit4 is set to 1: Sync
+ *  Bit5 is set to 1: Disable update. TEA/B here and below means an event generated
+ *  when the timer's value equals to that of register A/B.
+ */
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Configures continuous software force mode for PWM2 A.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Configures continuous software force mode for PWM2 B.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for PWM2
+ *  A, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
+#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_A_NCIFORCE_S  10
+/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM2 A.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for PWM2
+ *  B, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
+#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_B_NCIFORCE_S  13
+/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM2 B.
+ *  0: Disabled
+ *  1: Low
+ *  2: High
+ *  3: Disabled
+ */
+#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN2_A_REG register
+ *  PWM2 output signal A actions configuration register
+ */
+#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xc0)
+/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM2 A triggered by event TEZ when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEZ    0x00000003U
+#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
+#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_UTEZ_S  0
+/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM2 A triggered by event TEP when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEP    0x00000003U
+#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
+#define MCPWM_GEN2_A_UTEP_V  0x00000003U
+#define MCPWM_GEN2_A_UTEP_S  2
+/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM2 A triggered by event TEA when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEA    0x00000003U
+#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
+#define MCPWM_GEN2_A_UTEA_V  0x00000003U
+#define MCPWM_GEN2_A_UTEA_S  4
+/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM2 A triggered by event TEB when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEB    0x00000003U
+#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
+#define MCPWM_GEN2_A_UTEB_V  0x00000003U
+#define MCPWM_GEN2_A_UTEB_S  6
+/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM2 A triggered by event_t0 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_UT0    0x00000003U
+#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
+#define MCPWM_GEN2_A_UT0_V  0x00000003U
+#define MCPWM_GEN2_A_UT0_S  8
+/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM2 A triggered by event_t1 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_UT1    0x00000003U
+#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
+#define MCPWM_GEN2_A_UT1_V  0x00000003U
+#define MCPWM_GEN2_A_UT1_S  10
+/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM2 A triggered by event TEZ when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEZ    0x00000003U
+#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
+#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_DTEZ_S  12
+/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM2 A triggered by event TEP when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEP    0x00000003U
+#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
+#define MCPWM_GEN2_A_DTEP_V  0x00000003U
+#define MCPWM_GEN2_A_DTEP_S  14
+/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM2 A triggered by event TEA when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEA    0x00000003U
+#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
+#define MCPWM_GEN2_A_DTEA_V  0x00000003U
+#define MCPWM_GEN2_A_DTEA_S  16
+/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM2 A triggered by event TEB when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEB    0x00000003U
+#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
+#define MCPWM_GEN2_A_DTEB_V  0x00000003U
+#define MCPWM_GEN2_A_DTEB_S  18
+/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM2 A triggered by event_t0 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_DT0    0x00000003U
+#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
+#define MCPWM_GEN2_A_DT0_V  0x00000003U
+#define MCPWM_GEN2_A_DT0_S  20
+/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM2 A triggered by event_t1 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_A_DT1    0x00000003U
+#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
+#define MCPWM_GEN2_A_DT1_V  0x00000003U
+#define MCPWM_GEN2_A_DT1_S  22
+
+/** MCPWM_GEN2_B_REG register
+ *  PWM2 output signal B actions configuration register
+ */
+#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xc4)
+/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM2 B triggered by event TEZ when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEZ    0x00000003U
+#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
+#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_UTEZ_S  0
+/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM2 B triggered by event TEP when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEP    0x00000003U
+#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
+#define MCPWM_GEN2_B_UTEP_V  0x00000003U
+#define MCPWM_GEN2_B_UTEP_S  2
+/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM2 B triggered by event TEA when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEA    0x00000003U
+#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
+#define MCPWM_GEN2_B_UTEA_V  0x00000003U
+#define MCPWM_GEN2_B_UTEA_S  4
+/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM2 B triggered by event TEB when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEB    0x00000003U
+#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
+#define MCPWM_GEN2_B_UTEB_V  0x00000003U
+#define MCPWM_GEN2_B_UTEB_S  6
+/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM2 B triggered by event_t0 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_UT0    0x00000003U
+#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
+#define MCPWM_GEN2_B_UT0_V  0x00000003U
+#define MCPWM_GEN2_B_UT0_S  8
+/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM2 B triggered by event_t1 when timer increasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_UT1    0x00000003U
+#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
+#define MCPWM_GEN2_B_UT1_V  0x00000003U
+#define MCPWM_GEN2_B_UT1_S  10
+/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM2 B triggered by event TEZ when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEZ    0x00000003U
+#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
+#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_DTEZ_S  12
+/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM2 B triggered by event TEP when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEP    0x00000003U
+#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
+#define MCPWM_GEN2_B_DTEP_V  0x00000003U
+#define MCPWM_GEN2_B_DTEP_S  14
+/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM2 B triggered by event TEA when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEA    0x00000003U
+#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
+#define MCPWM_GEN2_B_DTEA_V  0x00000003U
+#define MCPWM_GEN2_B_DTEA_S  16
+/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM2 B triggered by event TEB when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEB    0x00000003U
+#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
+#define MCPWM_GEN2_B_DTEB_V  0x00000003U
+#define MCPWM_GEN2_B_DTEB_S  18
+/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM2 B triggered by event_t0 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_DT0    0x00000003U
+#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
+#define MCPWM_GEN2_B_DT0_V  0x00000003U
+#define MCPWM_GEN2_B_DT0_S  20
+/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM2 B triggered by event_t1 when timer decreasing.
+ *  0: No change
+ *  1: Low
+ *  2: High
+ *  3: Toggle
+ */
+#define MCPWM_GEN2_B_DT1    0x00000003U
+#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
+#define MCPWM_GEN2_B_DT1_V  0x00000003U
+#define MCPWM_GEN2_B_DT1_S  22
+
+/** MCPWM_DT2_CFG_REG register
+ *  Dead time configuration register
+ */
+#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc8)
+/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for FED (Falling edge delay) active register.
+ *  0: Immediate
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB2_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB2_FED_UPMETHOD_M  (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S)
+#define MCPWM_DB2_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB2_FED_UPMETHOD_S  0
+/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures update method for RED (rising edge delay) active register.
+ *  0: Immediate
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ *  Bit2 is set to 1: Sync
+ *  Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB2_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB2_RED_UPMETHOD_M  (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S)
+#define MCPWM_DB2_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB2_RED_UPMETHOD_S  4
+/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  Configures S8 in table, dual-edge B mode.
+ *  0: fed/red take effect on different path separately
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB2_DEB_MODE    (BIT(8))
+#define MCPWM_DB2_DEB_MODE_M  (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S)
+#define MCPWM_DB2_DEB_MODE_V  0x00000001U
+#define MCPWM_DB2_DEB_MODE_S  8
+/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  Configures S6 in table.
+ */
+#define MCPWM_DB2_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB2_A_OUTSWAP_M  (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S)
+#define MCPWM_DB2_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB2_A_OUTSWAP_S  9
+/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  Configures S7 in table.
+ */
+#define MCPWM_DB2_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB2_B_OUTSWAP_M  (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S)
+#define MCPWM_DB2_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB2_B_OUTSWAP_S  10
+/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  Configures S4 in table.
+ */
+#define MCPWM_DB2_RED_INSEL    (BIT(11))
+#define MCPWM_DB2_RED_INSEL_M  (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S)
+#define MCPWM_DB2_RED_INSEL_V  0x00000001U
+#define MCPWM_DB2_RED_INSEL_S  11
+/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  Configures S5 in table.
+ */
+#define MCPWM_DB2_FED_INSEL    (BIT(12))
+#define MCPWM_DB2_FED_INSEL_M  (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S)
+#define MCPWM_DB2_FED_INSEL_V  0x00000001U
+#define MCPWM_DB2_FED_INSEL_S  12
+/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures S2 in table.
+ */
+#define MCPWM_DB2_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB2_RED_OUTINVERT_M  (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S)
+#define MCPWM_DB2_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB2_RED_OUTINVERT_S  13
+/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  Configures S3 in table.
+ */
+#define MCPWM_DB2_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB2_FED_OUTINVERT_M  (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S)
+#define MCPWM_DB2_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB2_FED_OUTINVERT_S  14
+/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  Configures S1 in table.
+ */
+#define MCPWM_DB2_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB2_A_OUTBYPASS_M  (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S)
+#define MCPWM_DB2_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB2_A_OUTBYPASS_S  15
+/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  Configures S0 in table.
+ */
+#define MCPWM_DB2_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB2_B_OUTBYPASS_M  (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S)
+#define MCPWM_DB2_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB2_B_OUTBYPASS_S  16
+/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Configures dead time generator 2 clock selection.
+ *  0: PWM_clk
+ *  1: PT_clk
+ */
+#define MCPWM_DB2_CLK_SEL    (BIT(17))
+#define MCPWM_DB2_CLK_SEL_M  (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S)
+#define MCPWM_DB2_CLK_SEL_V  0x00000001U
+#define MCPWM_DB2_CLK_SEL_S  17
+
+/** MCPWM_DT2_FED_CFG_REG register
+ *  Falling edge delay (FED) shadow register
+ */
+#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xcc)
+/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for FED.
+ */
+#define MCPWM_DB2_FED    0x0000FFFFU
+#define MCPWM_DB2_FED_M  (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S)
+#define MCPWM_DB2_FED_V  0x0000FFFFU
+#define MCPWM_DB2_FED_S  0
+
+/** MCPWM_DT2_RED_CFG_REG register
+ *  Rising edge delay (RED) shadow register
+ */
+#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd0)
+/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for RED.
+ */
+#define MCPWM_DB2_RED    0x0000FFFFU
+#define MCPWM_DB2_RED_M  (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S)
+#define MCPWM_DB2_RED_V  0x0000FFFFU
+#define MCPWM_DB2_RED_S  0
+
+/** MCPWM_CARRIER2_CFG_REG register
+ *  Carrier2 configuration register
+ */
+#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd4)
+/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable carrier2.
+ *  0: Bypassed
+ *  1: Enabled
+ */
+#define MCPWM_CHOPPER2_EN    (BIT(0))
+#define MCPWM_CHOPPER2_EN_M  (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S)
+#define MCPWM_CHOPPER2_EN_V  0x00000001U
+#define MCPWM_CHOPPER2_EN_S  0
+/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  Configures the prescale value of PWM carrier2 clock (PC_clk), so that period of
+ *  PC_clk = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER2_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER2_PRESCALE_M  (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S)
+#define MCPWM_CHOPPER2_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER2_PRESCALE_S  1
+/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  Configures carrier duty. Duty = PWM_CARRIER2_DUTY / 8
+ */
+#define MCPWM_CHOPPER2_DUTY    0x00000007U
+#define MCPWM_CHOPPER2_DUTY_M  (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S)
+#define MCPWM_CHOPPER2_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER2_DUTY_S  5
+/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+ */
+#define MCPWM_CHOPPER2_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER2_OSHTWTH_M  (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S)
+#define MCPWM_CHOPPER2_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER2_OSHTWTH_S  8
+/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to invert the output of PWM2 A and PWM2 B for this
+ *  submodule.
+ *  0: Normal
+ *  1: Invert
+ */
+#define MCPWM_CHOPPER2_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER2_OUT_INVERT_M  (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S)
+#define MCPWM_CHOPPER2_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER2_OUT_INVERT_S  12
+/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to invert the input of PWM2 A and PWM2 B for this
+ *  submodule.
+ *  0: Normal
+ *  1: Invert
+ */
+#define MCPWM_CHOPPER2_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER2_IN_INVERT_M  (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S)
+#define MCPWM_CHOPPER2_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER2_IN_INVERT_S  13
+
+/** MCPWM_FH2_CFG0_REG register
+ *  PWM2 A and PWM2 B trip events actions configuration register
+ */
+#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xd8)
+/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable software force cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ2_SW_CBC    (BIT(0))
+#define MCPWM_TZ2_SW_CBC_M  (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S)
+#define MCPWM_TZ2_SW_CBC_V  0x00000001U
+#define MCPWM_TZ2_SW_CBC_S  0
+/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ2_F2_CBC    (BIT(1))
+#define MCPWM_TZ2_F2_CBC_M  (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S)
+#define MCPWM_TZ2_F2_CBC_V  0x00000001U
+#define MCPWM_TZ2_F2_CBC_S  1
+/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ2_F1_CBC    (BIT(2))
+#define MCPWM_TZ2_F1_CBC_M  (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S)
+#define MCPWM_TZ2_F1_CBC_V  0x00000001U
+#define MCPWM_TZ2_F1_CBC_S  2
+/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ2_F0_CBC    (BIT(3))
+#define MCPWM_TZ2_F0_CBC_M  (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S)
+#define MCPWM_TZ2_F0_CBC_V  0x00000001U
+#define MCPWM_TZ2_F0_CBC_S  3
+/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable software force one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ2_SW_OST    (BIT(4))
+#define MCPWM_TZ2_SW_OST_M  (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S)
+#define MCPWM_TZ2_SW_OST_V  0x00000001U
+#define MCPWM_TZ2_SW_OST_S  4
+/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not event_f2 will trigger one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ2_F2_OST    (BIT(5))
+#define MCPWM_TZ2_F2_OST_M  (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S)
+#define MCPWM_TZ2_F2_OST_V  0x00000001U
+#define MCPWM_TZ2_F2_OST_S  5
+/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not event_f1 will trigger one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ2_F1_OST    (BIT(6))
+#define MCPWM_TZ2_F1_OST_M  (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S)
+#define MCPWM_TZ2_F1_OST_V  0x00000001U
+#define MCPWM_TZ2_F1_OST_S  6
+/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not event_f0 will trigger one-shot mode action.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TZ2_F0_OST    (BIT(7))
+#define MCPWM_TZ2_F0_OST_M  (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S)
+#define MCPWM_TZ2_F0_OST_V  0x00000001U
+#define MCPWM_TZ2_F0_OST_S  7
+/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM2 A when fault event occurs and timer
+ *  is decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ2_A_CBC_D    0x00000003U
+#define MCPWM_TZ2_A_CBC_D_M  (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S)
+#define MCPWM_TZ2_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ2_A_CBC_D_S  8
+/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM2 A when fault event occurs and timer
+ *  is increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ2_A_CBC_U    0x00000003U
+#define MCPWM_TZ2_A_CBC_U_M  (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S)
+#define MCPWM_TZ2_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ2_A_CBC_U_S  10
+/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  Configures one-shot mode action on PWM2 A when fault event occurs and timer is
+ *  decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ2_A_OST_D    0x00000003U
+#define MCPWM_TZ2_A_OST_D_M  (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S)
+#define MCPWM_TZ2_A_OST_D_V  0x00000003U
+#define MCPWM_TZ2_A_OST_D_S  12
+/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  Configures one-shot mode action on PWM2 A when fault event occurs and timer is
+ *  increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ2_A_OST_U    0x00000003U
+#define MCPWM_TZ2_A_OST_U_M  (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S)
+#define MCPWM_TZ2_A_OST_U_V  0x00000003U
+#define MCPWM_TZ2_A_OST_U_S  14
+/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM2 B when fault event occurs and timer
+ *  is decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ2_B_CBC_D    0x00000003U
+#define MCPWM_TZ2_B_CBC_D_M  (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S)
+#define MCPWM_TZ2_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ2_B_CBC_D_S  16
+/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM2 B when fault event occurs and timer
+ *  is increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ2_B_CBC_U    0x00000003U
+#define MCPWM_TZ2_B_CBC_U_M  (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S)
+#define MCPWM_TZ2_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ2_B_CBC_U_S  18
+/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  Configures one-shot mode action on PWM2 B when fault event occurs and timer is
+ *  decreasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ2_B_OST_D    0x00000003U
+#define MCPWM_TZ2_B_OST_D_M  (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S)
+#define MCPWM_TZ2_B_OST_D_V  0x00000003U
+#define MCPWM_TZ2_B_OST_D_S  20
+/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  Configures one-shot mode action on PWM2 B when fault event occurs and timer is
+ *  increasing.
+ *  0: Do nothing
+ *  1: Force low
+ *  2: Force high
+ *  3: Toggle
+ */
+#define MCPWM_TZ2_B_OST_U    0x00000003U
+#define MCPWM_TZ2_B_OST_U_M  (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S)
+#define MCPWM_TZ2_B_OST_U_V  0x00000003U
+#define MCPWM_TZ2_B_OST_U_S  22
+
+/** MCPWM_FH2_CFG1_REG register
+ *  Software triggers for fault handler actions configuration register
+ */
+#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xdc)
+/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  Configures the generation of software one-shot mode action clear. A toggle
+ *  (software negate its value) triggers a clear for on going one-shot mode action.
+ */
+#define MCPWM_TZ2_CLR_OST    (BIT(0))
+#define MCPWM_TZ2_CLR_OST_M  (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S)
+#define MCPWM_TZ2_CLR_OST_V  0x00000001U
+#define MCPWM_TZ2_CLR_OST_S  0
+/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures the refresh moment selection of cycle-by-cycle mode action.
+ *  0: Select nothing, will not refresh
+ *  Bit0 is set to 1: TEZ
+ *  Bit1 is set to 1: TEP
+ */
+#define MCPWM_TZ2_CBCPULSE    0x00000003U
+#define MCPWM_TZ2_CBCPULSE_M  (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S)
+#define MCPWM_TZ2_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ2_CBCPULSE_S  1
+/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of software cycle-by-cycle mode action. A toggle
+ *  (software negate its value) triggers a cycle-by-cycle mode action.
+ */
+#define MCPWM_TZ2_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ2_FORCE_CBC_M  (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S)
+#define MCPWM_TZ2_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ2_FORCE_CBC_S  3
+/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures the generation of software one-shot mode action. A toggle (software
+ *  negate its value) triggers a one-shot mode action.
+ */
+#define MCPWM_TZ2_FORCE_OST    (BIT(4))
+#define MCPWM_TZ2_FORCE_OST_M  (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S)
+#define MCPWM_TZ2_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ2_FORCE_OST_S  4
+
+/** MCPWM_FH2_STATUS_REG register
+ *  Fault events status register
+ */
+#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xe0)
+/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an cycle-by-cycle mode action is on going.
+ *  0:No action
+ *  1: On going
+ */
+#define MCPWM_TZ2_CBC_ON    (BIT(0))
+#define MCPWM_TZ2_CBC_ON_M  (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S)
+#define MCPWM_TZ2_CBC_ON_V  0x00000001U
+#define MCPWM_TZ2_CBC_ON_S  0
+/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not an one-shot mode action is on going.
+ *  0:No action
+ *  1: On going
+ */
+#define MCPWM_TZ2_OST_ON    (BIT(1))
+#define MCPWM_TZ2_OST_ON_M  (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S)
+#define MCPWM_TZ2_OST_ON_V  0x00000001U
+#define MCPWM_TZ2_OST_ON_S  1
+
+/** MCPWM_FAULT_DETECT_REG register
+ *  Fault detection configuration and status register
+ */
+#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xe4)
+/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable event_f0 generation.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_F0_EN    (BIT(0))
+#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
+#define MCPWM_F0_EN_V  0x00000001U
+#define MCPWM_F0_EN_S  0
+/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable event_f1 generation.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_F1_EN    (BIT(1))
+#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
+#define MCPWM_F1_EN_V  0x00000001U
+#define MCPWM_F1_EN_S  1
+/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable event_f2 generation.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_F2_EN    (BIT(2))
+#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
+#define MCPWM_F2_EN_V  0x00000001U
+#define MCPWM_F2_EN_S  2
+/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
+ *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.
+ *  0: Level low
+ *  1: Level high
+ */
+#define MCPWM_F0_POLE    (BIT(3))
+#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
+#define MCPWM_F0_POLE_V  0x00000001U
+#define MCPWM_F0_POLE_S  3
+/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
+ *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.
+ *  0: Level low
+ *  1: Level high
+ */
+#define MCPWM_F1_POLE    (BIT(4))
+#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
+#define MCPWM_F1_POLE_V  0x00000001U
+#define MCPWM_F1_POLE_S  4
+/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
+ *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.
+ *  0: Level low
+ *  1: Level high
+ */
+#define MCPWM_F2_POLE    (BIT(5))
+#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
+#define MCPWM_F2_POLE_V  0x00000001U
+#define MCPWM_F2_POLE_S  5
+/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
+ *  Represents whether or not an event_f0 is on going.
+ *  0: No action
+ *  1: On going
+ */
+#define MCPWM_EVENT_F0    (BIT(6))
+#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
+#define MCPWM_EVENT_F0_V  0x00000001U
+#define MCPWM_EVENT_F0_S  6
+/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
+ *  Represents whether or not an event_f1 is on going.
+ *  0: No action
+ *  1: On going
+ */
+#define MCPWM_EVENT_F1    (BIT(7))
+#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
+#define MCPWM_EVENT_F1_V  0x00000001U
+#define MCPWM_EVENT_F1_S  7
+/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
+ *  Represents whether or not an event_f2 is on going.
+ *  0: No action
+ *  1: On going
+ */
+#define MCPWM_EVENT_F2    (BIT(8))
+#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
+#define MCPWM_EVENT_F2_V  0x00000001U
+#define MCPWM_EVENT_F2_S  8
+
+/** MCPWM_CAP_TIMER_CFG_REG register
+ *  Capture timer configuration register
+ */
+#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xe8)
+/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture timer increment.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_CAP_TIMER_EN    (BIT(0))
+#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
+#define MCPWM_CAP_TIMER_EN_V  0x00000001U
+#define MCPWM_CAP_TIMER_EN_S  0
+/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable capture timer sync.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_CAP_SYNCI_EN    (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
+#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
+#define MCPWM_CAP_SYNCI_EN_S  1
+/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  Configures the selection of capture module sync input.
+ *  0: None
+ *  1: Timer0 sync_out
+ *  2: Timer1 sync_out
+ *  3: Timer2 sync_out
+ *  4: SYNC0 from GPIO matrix
+ *  5: SYNC1 from GPIO matrix
+ *  6: SYNC2 from GPIO matrix
+ *  7: None
+ */
+#define MCPWM_CAP_SYNCI_SEL    0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
+#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_S  2
+/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
+ *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.
+ *  0: Invalid, No effect
+ *  1: Trigger a capture timer sync, capture timer is loaded with value in phase
+ *  register
+ */
+#define MCPWM_CAP_SYNC_SW    (BIT(5))
+#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
+#define MCPWM_CAP_SYNC_SW_V  0x00000001U
+#define MCPWM_CAP_SYNC_SW_S  5
+
+/** MCPWM_CAP_TIMER_PHASE_REG register
+ *  Capture timer sync phase register
+ */
+#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xec)
+/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
+ *  Configures phase value for capture timer sync operation.
+ */
+#define MCPWM_CAP_PHASE    0xFFFFFFFFU
+#define MCPWM_CAP_PHASE_M  (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S)
+#define MCPWM_CAP_PHASE_V  0xFFFFFFFFU
+#define MCPWM_CAP_PHASE_S  0
+
+/** MCPWM_CAP_CH0_CFG_REG register
+ *  Capture channel 0 configuration register
+ */
+#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf0)
+/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture on channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_CAP0_EN    (BIT(0))
+#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
+#define MCPWM_CAP0_EN_V  0x00000001U
+#define MCPWM_CAP0_EN_S  0
+/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures which edge of capture on channel 0 after prescaling is used.
+ *  0: None
+ *  Bit0 is set to 1: Rnable capture on the negative edge
+ *  Bit1 is set to 1: Enable capture on the positive edge
+ */
+#define MCPWM_CAP0_MODE    0x00000003U
+#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
+#define MCPWM_CAP0_MODE_V  0x00000003U
+#define MCPWM_CAP0_MODE_S  1
+/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Configures prescale value on positive edge of CAP0. Prescale value =
+ *  PWM_CAP0_PRESCALE + 1
+ */
+#define MCPWM_CAP0_PRESCALE    0x000000FFU
+#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
+#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP0_PRESCALE_S  3
+/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert CAP0 from GPIO matrix before prescale.
+ *  0: Normal
+ *  1: Invert
+ */
+#define MCPWM_CAP0_IN_INVERT    (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
+#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP0_IN_INVERT_S  11
+/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
+ *  Configures the generation of software capture.
+ *  0: Invalid, No effect
+ *  1: Trigger a software forced capture on channel 0
+ */
+#define MCPWM_CAP0_SW    (BIT(12))
+#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
+#define MCPWM_CAP0_SW_V  0x00000001U
+#define MCPWM_CAP0_SW_S  12
+
+/** MCPWM_CAP_CH1_CFG_REG register
+ *  Capture channel 1 configuration register
+ */
+#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf4)
+/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture on channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_CAP1_EN    (BIT(0))
+#define MCPWM_CAP1_EN_M  (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S)
+#define MCPWM_CAP1_EN_V  0x00000001U
+#define MCPWM_CAP1_EN_S  0
+/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures which edge of capture on channel 1 after prescaling is used.
+ *  0: None
+ *  Bit0 is set to 1: Rnable capture on the negative edge
+ *  Bit1 is set to 1: Enable capture on the positive edge
+ */
+#define MCPWM_CAP1_MODE    0x00000003U
+#define MCPWM_CAP1_MODE_M  (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S)
+#define MCPWM_CAP1_MODE_V  0x00000003U
+#define MCPWM_CAP1_MODE_S  1
+/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Configures prescale value on positive edge of CAP1. Prescale value =
+ *  PWM_CAP1_PRESCALE + 1
+ */
+#define MCPWM_CAP1_PRESCALE    0x000000FFU
+#define MCPWM_CAP1_PRESCALE_M  (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S)
+#define MCPWM_CAP1_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP1_PRESCALE_S  3
+/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert CAP1 from GPIO matrix before prescale.
+ *  0: Normal
+ *  1: Invert
+ */
+#define MCPWM_CAP1_IN_INVERT    (BIT(11))
+#define MCPWM_CAP1_IN_INVERT_M  (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S)
+#define MCPWM_CAP1_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP1_IN_INVERT_S  11
+/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0;
+ *  Configures the generation of software capture.
+ *  0: Invalid, No effect
+ *  1: Trigger a software forced capture on channel 1
+ */
+#define MCPWM_CAP1_SW    (BIT(12))
+#define MCPWM_CAP1_SW_M  (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S)
+#define MCPWM_CAP1_SW_V  0x00000001U
+#define MCPWM_CAP1_SW_S  12
+
+/** MCPWM_CAP_CH2_CFG_REG register
+ *  Capture channel 2 configuration register
+ */
+#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf8)
+/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture on channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_CAP2_EN    (BIT(0))
+#define MCPWM_CAP2_EN_M  (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S)
+#define MCPWM_CAP2_EN_V  0x00000001U
+#define MCPWM_CAP2_EN_S  0
+/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures which edge of capture on channel 2 after prescaling is used.
+ *  0: None
+ *  Bit0 is set to 1: Rnable capture on the negative edge
+ *  Bit1 is set to 1: Enable capture on the positive edge
+ */
+#define MCPWM_CAP2_MODE    0x00000003U
+#define MCPWM_CAP2_MODE_M  (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S)
+#define MCPWM_CAP2_MODE_V  0x00000003U
+#define MCPWM_CAP2_MODE_S  1
+/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Configures prescale value on positive edge of CAP2. Prescale value =
+ *  PWM_CAP2_PRESCALE + 1
+ */
+#define MCPWM_CAP2_PRESCALE    0x000000FFU
+#define MCPWM_CAP2_PRESCALE_M  (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S)
+#define MCPWM_CAP2_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP2_PRESCALE_S  3
+/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert CAP2 from GPIO matrix before prescale.
+ *  0: Normal
+ *  1: Invert
+ */
+#define MCPWM_CAP2_IN_INVERT    (BIT(11))
+#define MCPWM_CAP2_IN_INVERT_M  (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S)
+#define MCPWM_CAP2_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP2_IN_INVERT_S  11
+/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0;
+ *  Configures the generation of software capture.
+ *  0: Invalid, No effect
+ *  1: Trigger a software forced capture on channel 2
+ */
+#define MCPWM_CAP2_SW    (BIT(12))
+#define MCPWM_CAP2_SW_M  (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S)
+#define MCPWM_CAP2_SW_V  0x00000001U
+#define MCPWM_CAP2_SW_S  12
+
+/** MCPWM_CAP_CH0_REG register
+ *  CAP0 capture value register
+ */
+#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xfc)
+/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Represents value of last capture on CAP0
+ */
+#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_S  0
+
+/** MCPWM_CAP_CH1_REG register
+ *  CAP1 capture value register
+ */
+#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x100)
+/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Represents value of last capture on CAP1
+ */
+#define MCPWM_CAP1_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP1_VALUE_M  (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S)
+#define MCPWM_CAP1_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP1_VALUE_S  0
+
+/** MCPWM_CAP_CH2_REG register
+ *  CAP2 capture value register
+ */
+#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x104)
+/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Represents value of last capture on CAP2
+ */
+#define MCPWM_CAP2_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP2_VALUE_M  (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S)
+#define MCPWM_CAP2_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP2_VALUE_S  0
+
+/** MCPWM_CAP_STATUS_REG register
+ *  Last capture trigger edge information register
+ */
+#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x108)
+/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
+ *  Represents edge of last capture trigger on channel0.
+ *  0: Posedge
+ *  1: Negedge
+ */
+#define MCPWM_CAP0_EDGE    (BIT(0))
+#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
+#define MCPWM_CAP0_EDGE_V  0x00000001U
+#define MCPWM_CAP0_EDGE_S  0
+/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
+ *  Represents edge of last capture trigger on channel1.
+ *  0: Posedge
+ *  1: Negedge
+ */
+#define MCPWM_CAP1_EDGE    (BIT(1))
+#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
+#define MCPWM_CAP1_EDGE_V  0x00000001U
+#define MCPWM_CAP1_EDGE_S  1
+/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
+ *  Represents edge of last capture trigger on channel2.
+ *  0: Posedge
+ *  1: Negedge
+ */
+#define MCPWM_CAP2_EDGE    (BIT(2))
+#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
+#define MCPWM_CAP2_EDGE_V  0x00000001U
+#define MCPWM_CAP2_EDGE_S  2
+
+/** MCPWM_UPDATE_CFG_REG register
+ *  Generator Update configuration register
+ */
+#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x10c)
+/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether or not to enable global update for all active registers in MCPWM
+ *  module.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_GLOBAL_UP_EN    (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
+#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
+#define MCPWM_GLOBAL_UP_EN_S  0
+/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of global forced update for all active registers in MCPWM
+ *  module. A toggle (software invert its value) will trigger a global forced update.
+ *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
+ */
+#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
+#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
+#define MCPWM_GLOBAL_FORCE_UP_S  1
+/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
+ *  Configures whether or not to enable update of active registers in PWM operator0.
+ *  Valid only when PWM_GLOBAL_UP_EN is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_OP0_UP_EN    (BIT(2))
+#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
+#define MCPWM_OP0_UP_EN_V  0x00000001U
+#define MCPWM_OP0_UP_EN_S  2
+/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of forced update for active registers in PWM operator0. A
+ *  toggle (software invert its value) will trigger a forced update. Valid only when
+ *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
+ */
+#define MCPWM_OP0_FORCE_UP    (BIT(3))
+#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
+#define MCPWM_OP0_FORCE_UP_V  0x00000001U
+#define MCPWM_OP0_FORCE_UP_S  3
+/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
+ *  Configures whether or not to enable update of active registers in PWM operator1.
+ *  Valid only when PWM_GLOBAL_UP_EN is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_OP1_UP_EN    (BIT(4))
+#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
+#define MCPWM_OP1_UP_EN_V  0x00000001U
+#define MCPWM_OP1_UP_EN_S  4
+/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
+ *  Configures the generation of forced update for active registers in PWM operator1. A
+ *  toggle (software invert its value) will trigger a forced update. Valid only when
+ *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
+ */
+#define MCPWM_OP1_FORCE_UP    (BIT(5))
+#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
+#define MCPWM_OP1_FORCE_UP_V  0x00000001U
+#define MCPWM_OP1_FORCE_UP_S  5
+/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
+ *  Configures whether or not to enable update of active registers in PWM operator2.
+ *  Valid only when PWM_GLOBAL_UP_EN is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_OP2_UP_EN    (BIT(6))
+#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
+#define MCPWM_OP2_UP_EN_V  0x00000001U
+#define MCPWM_OP2_UP_EN_S  6
+/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
+ *  Configures the generation of forced update for active registers in PWM operator2. A
+ *  toggle (software invert its value) will trigger a forced update. Valid only when
+ *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
+ */
+#define MCPWM_OP2_FORCE_UP    (BIT(7))
+#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
+#define MCPWM_OP2_FORCE_UP_V  0x00000001U
+#define MCPWM_OP2_FORCE_UP_S  7
+
+/** MCPWM_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define MCPWM_INT_ENA_REG(i) (REG_MCPWM_BASE(i) + 0x110)
+/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
+#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ENA_S  0
+/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
+#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ENA_S  1
+/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
+#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ENA_S  2
+/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
+#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
+/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
+#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
+/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
+#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
+/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
+#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ENA_S  6
+/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
+#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ENA_S  7
+/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
+#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ENA_S  8
+/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_ENA    (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
+#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_INT_ENA_S  9
+/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_ENA    (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
+#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_INT_ENA_S  10
+/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_ENA    (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
+#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_INT_ENA_S  11
+/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
+#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ENA_S  12
+/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
+#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ENA_S  13
+/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
+#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ENA_S  14
+/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
+ */
+#define MCPWM_CMPR0_TEA_INT_ENA    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_ENA_M  (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S)
+#define MCPWM_CMPR0_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_ENA_S  15
+/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
+ */
+#define MCPWM_CMPR1_TEA_INT_ENA    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_ENA_M  (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S)
+#define MCPWM_CMPR1_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_ENA_S  16
+/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
+ */
+#define MCPWM_CMPR2_TEA_INT_ENA    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_ENA_M  (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S)
+#define MCPWM_CMPR2_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_ENA_S  17
+/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
+ */
+#define MCPWM_CMPR0_TEB_INT_ENA    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_ENA_M  (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S)
+#define MCPWM_CMPR0_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_ENA_S  18
+/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
+ */
+#define MCPWM_CMPR1_TEB_INT_ENA    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_ENA_M  (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S)
+#define MCPWM_CMPR1_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_ENA_S  19
+/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
+ */
+#define MCPWM_CMPR2_TEB_INT_ENA    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_ENA_M  (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S)
+#define MCPWM_CMPR2_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_ENA_S  20
+/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+ *  action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_ENA    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_ENA_M  (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S)
+#define MCPWM_TZ0_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_ENA_S  21
+/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+ *  action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_ENA    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_ENA_M  (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S)
+#define MCPWM_TZ1_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_ENA_S  22
+/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+ *  action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_ENA    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_ENA_M  (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S)
+#define MCPWM_TZ2_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_ENA_S  23
+/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+ *  PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_ENA    (BIT(24))
+#define MCPWM_TZ0_OST_INT_ENA_M  (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S)
+#define MCPWM_TZ0_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_ENA_S  24
+/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+ *  PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_ENA    (BIT(25))
+#define MCPWM_TZ1_OST_INT_ENA_M  (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S)
+#define MCPWM_TZ1_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_ENA_S  25
+/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+ *  PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_ENA    (BIT(26))
+#define MCPWM_TZ2_OST_INT_ENA_M  (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S)
+#define MCPWM_TZ2_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_ENA_S  26
+/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
+ */
+#define MCPWM_CAP0_INT_ENA    (BIT(27))
+#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
+#define MCPWM_CAP0_INT_ENA_V  0x00000001U
+#define MCPWM_CAP0_INT_ENA_S  27
+/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
+ */
+#define MCPWM_CAP1_INT_ENA    (BIT(28))
+#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
+#define MCPWM_CAP1_INT_ENA_V  0x00000001U
+#define MCPWM_CAP1_INT_ENA_S  28
+/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
+ */
+#define MCPWM_CAP2_INT_ENA    (BIT(29))
+#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
+#define MCPWM_CAP2_INT_ENA_V  0x00000001U
+#define MCPWM_CAP2_INT_ENA_S  29
+
+/** MCPWM_INT_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define MCPWM_INT_RAW_REG(i) (REG_MCPWM_BASE(i) + 0x114)
+/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+ *  0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
+#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_RAW_S  0
+/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+ *  1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
+#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_RAW_S  1
+/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+ *  2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
+#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_RAW_S  2
+/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
+#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
+/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
+#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
+/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
+#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
+/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
+#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_RAW_S  6
+/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
+#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_RAW_S  7
+/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
+#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_RAW_S  8
+/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+ *  starts.
+ */
+#define MCPWM_FAULT0_INT_RAW    (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
+#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_INT_RAW_S  9
+/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+ *  starts.
+ */
+#define MCPWM_FAULT1_INT_RAW    (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
+#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_INT_RAW_S  10
+/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+ *  starts.
+ */
+#define MCPWM_FAULT2_INT_RAW    (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
+#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_INT_RAW_S  11
+/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+ *  clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
+#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_RAW_S  12
+/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+ *  clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
+#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_RAW_S  13
+/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+ *  clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
+#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_RAW_S  14
+/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_RAW    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_RAW_M  (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S)
+#define MCPWM_CMPR0_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_RAW_S  15
+/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_RAW    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_RAW_M  (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S)
+#define MCPWM_CMPR1_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_RAW_S  16
+/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_RAW    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_RAW_M  (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S)
+#define MCPWM_CMPR2_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_RAW_S  17
+/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_RAW    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_RAW_M  (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S)
+#define MCPWM_CMPR0_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_RAW_S  18
+/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_RAW    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_RAW_M  (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S)
+#define MCPWM_CMPR1_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_RAW_S  19
+/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_RAW    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_RAW_M  (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S)
+#define MCPWM_CMPR2_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_RAW_S  20
+/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_RAW    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_RAW_M  (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S)
+#define MCPWM_TZ0_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_RAW_S  21
+/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_RAW    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_RAW_M  (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S)
+#define MCPWM_TZ1_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_RAW_S  22
+/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_RAW    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_RAW_M  (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S)
+#define MCPWM_TZ2_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_RAW_S  23
+/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+ *  mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_RAW    (BIT(24))
+#define MCPWM_TZ0_OST_INT_RAW_M  (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S)
+#define MCPWM_TZ0_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_RAW_S  24
+/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+ *  mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_RAW    (BIT(25))
+#define MCPWM_TZ1_OST_INT_RAW_M  (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S)
+#define MCPWM_TZ1_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_RAW_S  25
+/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+ *  mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_RAW    (BIT(26))
+#define MCPWM_TZ2_OST_INT_RAW_M  (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S)
+#define MCPWM_TZ2_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_RAW_S  26
+/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+ *  CAP0.
+ */
+#define MCPWM_CAP0_INT_RAW    (BIT(27))
+#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
+#define MCPWM_CAP0_INT_RAW_V  0x00000001U
+#define MCPWM_CAP0_INT_RAW_S  27
+/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+ *  CAP1.
+ */
+#define MCPWM_CAP1_INT_RAW    (BIT(28))
+#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
+#define MCPWM_CAP1_INT_RAW_V  0x00000001U
+#define MCPWM_CAP1_INT_RAW_S  28
+/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+ *  CAP2.
+ */
+#define MCPWM_CAP2_INT_RAW    (BIT(29))
+#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
+#define MCPWM_CAP2_INT_RAW_V  0x00000001U
+#define MCPWM_CAP2_INT_RAW_S  29
+
+/** MCPWM_INT_ST_REG register
+ *  Interrupt masked status register
+ */
+#define MCPWM_INT_ST_REG(i) (REG_MCPWM_BASE(i) + 0x118)
+/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+ *  timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
+#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ST_S  0
+/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+ *  timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
+#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ST_S  1
+/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+ *  timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
+#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ST_S  2
+/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
+#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ST_S  3
+/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
+#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ST_S  4
+/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
+#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ST_S  5
+/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
+#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ST_S  6
+/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
+#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ST_S  7
+/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
+#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ST_S  8
+/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_ST    (BIT(9))
+#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
+#define MCPWM_FAULT0_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_INT_ST_S  9
+/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_ST    (BIT(10))
+#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
+#define MCPWM_FAULT1_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_INT_ST_S  10
+/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_ST    (BIT(11))
+#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
+#define MCPWM_FAULT2_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_INT_ST_S  11
+/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f0 clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
+#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ST_S  12
+/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f1 clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
+#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ST_S  13
+/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f2 clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
+#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ST_S  14
+/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_ST    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_ST_M  (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S)
+#define MCPWM_CMPR0_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_ST_S  15
+/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_ST    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_ST_M  (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S)
+#define MCPWM_CMPR1_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_ST_S  16
+/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_ST    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_ST_M  (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S)
+#define MCPWM_CMPR2_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_ST_S  17
+/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_ST    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_ST_M  (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S)
+#define MCPWM_CMPR0_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_ST_S  18
+/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_ST    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_ST_M  (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S)
+#define MCPWM_CMPR1_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_ST_S  19
+/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_ST    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_ST_M  (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S)
+#define MCPWM_CMPR2_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_ST_S  20
+/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_ST    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_ST_M  (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S)
+#define MCPWM_TZ0_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_ST_S  21
+/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_ST    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_ST_M  (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S)
+#define MCPWM_TZ1_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_ST_S  22
+/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_ST    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_ST_M  (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S)
+#define MCPWM_TZ2_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_ST_S  23
+/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_ST    (BIT(24))
+#define MCPWM_TZ0_OST_INT_ST_M  (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S)
+#define MCPWM_TZ0_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_ST_S  24
+/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_ST    (BIT(25))
+#define MCPWM_TZ1_OST_INT_ST_M  (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S)
+#define MCPWM_TZ1_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_ST_S  25
+/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_ST    (BIT(26))
+#define MCPWM_TZ2_OST_INT_ST_M  (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S)
+#define MCPWM_TZ2_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_ST_S  26
+/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by
+ *  capture on CAP0.
+ */
+#define MCPWM_CAP0_INT_ST    (BIT(27))
+#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
+#define MCPWM_CAP0_INT_ST_V  0x00000001U
+#define MCPWM_CAP0_INT_ST_S  27
+/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by
+ *  capture on CAP1.
+ */
+#define MCPWM_CAP1_INT_ST    (BIT(28))
+#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
+#define MCPWM_CAP1_INT_ST_V  0x00000001U
+#define MCPWM_CAP1_INT_ST_S  28
+/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by
+ *  capture on CAP2.
+ */
+#define MCPWM_CAP2_INT_ST    (BIT(29))
+#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
+#define MCPWM_CAP2_INT_ST_V  0x00000001U
+#define MCPWM_CAP2_INT_ST_S  29
+
+/** MCPWM_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define MCPWM_INT_CLR_REG(i) (REG_MCPWM_BASE(i) + 0x11c)
+/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
+#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_CLR_S  0
+/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
+#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_CLR_S  1
+/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
+#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_CLR_S  2
+/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
+#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
+/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
+#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
+/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
+#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
+/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
+#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_CLR_S  6
+/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
+#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_CLR_S  7
+/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
+#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_CLR_S  8
+/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_CLR    (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
+#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_INT_CLR_S  9
+/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_CLR    (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
+#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_INT_CLR_S  10
+/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_CLR    (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
+#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_INT_CLR_S  11
+/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
+#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_CLR_S  12
+/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
+#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_CLR_S  13
+/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
+#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_CLR_S  14
+/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_CLR    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_CLR_M  (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S)
+#define MCPWM_CMPR0_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_CLR_S  15
+/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_CLR    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_CLR_M  (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S)
+#define MCPWM_CMPR1_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_CLR_S  16
+/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_CLR    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_CLR_M  (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S)
+#define MCPWM_CMPR2_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_CLR_S  17
+/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_CLR    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_CLR_M  (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S)
+#define MCPWM_CMPR0_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_CLR_S  18
+/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_CLR    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_CLR_M  (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S)
+#define MCPWM_CMPR1_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_CLR_S  19
+/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_CLR    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_CLR_M  (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S)
+#define MCPWM_CMPR2_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_CLR_S  20
+/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_CLR    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_CLR_M  (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S)
+#define MCPWM_TZ0_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_CLR_S  21
+/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_CLR    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_CLR_M  (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S)
+#define MCPWM_TZ1_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_CLR_S  22
+/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_CLR    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_CLR_M  (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S)
+#define MCPWM_TZ2_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_CLR_S  23
+/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+ *  PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_CLR    (BIT(24))
+#define MCPWM_TZ0_OST_INT_CLR_M  (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S)
+#define MCPWM_TZ0_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_CLR_S  24
+/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+ *  PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_CLR    (BIT(25))
+#define MCPWM_TZ1_OST_INT_CLR_M  (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S)
+#define MCPWM_TZ1_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_CLR_S  25
+/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+ *  PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_CLR    (BIT(26))
+#define MCPWM_TZ2_OST_INT_CLR_M  (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S)
+#define MCPWM_TZ2_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_CLR_S  26
+/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
+ */
+#define MCPWM_CAP0_INT_CLR    (BIT(27))
+#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
+#define MCPWM_CAP0_INT_CLR_V  0x00000001U
+#define MCPWM_CAP0_INT_CLR_S  27
+/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
+ */
+#define MCPWM_CAP1_INT_CLR    (BIT(28))
+#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
+#define MCPWM_CAP1_INT_CLR_V  0x00000001U
+#define MCPWM_CAP1_INT_CLR_S  28
+/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
+ */
+#define MCPWM_CAP2_INT_CLR    (BIT(29))
+#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
+#define MCPWM_CAP2_INT_CLR_V  0x00000001U
+#define MCPWM_CAP2_INT_CLR_S  29
+
+/** MCPWM_EVT_EN_REG register
+ *  Event enable register
+ */
+#define MCPWM_EVT_EN_REG(i) (REG_MCPWM_BASE(i) + 0x120)
+/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer0 stop event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TIMER0_STOP_EN    (BIT(0))
+#define MCPWM_EVT_TIMER0_STOP_EN_M  (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S)
+#define MCPWM_EVT_TIMER0_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_STOP_EN_S  0
+/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable timer1 stop event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TIMER1_STOP_EN    (BIT(1))
+#define MCPWM_EVT_TIMER1_STOP_EN_M  (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S)
+#define MCPWM_EVT_TIMER1_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_STOP_EN_S  1
+/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable timer2 stop event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TIMER2_STOP_EN    (BIT(2))
+#define MCPWM_EVT_TIMER2_STOP_EN_M  (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S)
+#define MCPWM_EVT_TIMER2_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_STOP_EN_S  2
+/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable timer0 equal zero event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TIMER0_TEZ_EN    (BIT(3))
+#define MCPWM_EVT_TIMER0_TEZ_EN_M  (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S)
+#define MCPWM_EVT_TIMER0_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_TEZ_EN_S  3
+/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable timer1 equal zero event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TIMER1_TEZ_EN    (BIT(4))
+#define MCPWM_EVT_TIMER1_TEZ_EN_M  (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S)
+#define MCPWM_EVT_TIMER1_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_TEZ_EN_S  4
+/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable timer2 equal zero event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TIMER2_TEZ_EN    (BIT(5))
+#define MCPWM_EVT_TIMER2_TEZ_EN_M  (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S)
+#define MCPWM_EVT_TIMER2_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_TEZ_EN_S  5
+/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable timer0 equal period event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TIMER0_TEP_EN    (BIT(6))
+#define MCPWM_EVT_TIMER0_TEP_EN_M  (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S)
+#define MCPWM_EVT_TIMER0_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_TEP_EN_S  6
+/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable timer1 equal period event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TIMER1_TEP_EN    (BIT(7))
+#define MCPWM_EVT_TIMER1_TEP_EN_M  (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S)
+#define MCPWM_EVT_TIMER1_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_TEP_EN_S  7
+/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable timer2 equal period event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TIMER2_TEP_EN    (BIT(8))
+#define MCPWM_EVT_TIMER2_TEP_EN_M  (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S)
+#define MCPWM_EVT_TIMER2_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_TEP_EN_S  8
+/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal a event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP0_TEA_EN    (BIT(9))
+#define MCPWM_EVT_OP0_TEA_EN_M  (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S)
+#define MCPWM_EVT_OP0_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEA_EN_S  9
+/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal a event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP1_TEA_EN    (BIT(10))
+#define MCPWM_EVT_OP1_TEA_EN_M  (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S)
+#define MCPWM_EVT_OP1_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEA_EN_S  10
+/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal a event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP2_TEA_EN    (BIT(11))
+#define MCPWM_EVT_OP2_TEA_EN_M  (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S)
+#define MCPWM_EVT_OP2_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEA_EN_S  11
+/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal b event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP0_TEB_EN    (BIT(12))
+#define MCPWM_EVT_OP0_TEB_EN_M  (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S)
+#define MCPWM_EVT_OP0_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEB_EN_S  12
+/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal b event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP1_TEB_EN    (BIT(13))
+#define MCPWM_EVT_OP1_TEB_EN_M  (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S)
+#define MCPWM_EVT_OP1_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEB_EN_S  13
+/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal b event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP2_TEB_EN    (BIT(14))
+#define MCPWM_EVT_OP2_TEB_EN_M  (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S)
+#define MCPWM_EVT_OP2_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEB_EN_S  14
+/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable fault0 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_F0_EN    (BIT(15))
+#define MCPWM_EVT_F0_EN_M  (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S)
+#define MCPWM_EVT_F0_EN_V  0x00000001U
+#define MCPWM_EVT_F0_EN_S  15
+/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable fault1 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_F1_EN    (BIT(16))
+#define MCPWM_EVT_F1_EN_M  (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S)
+#define MCPWM_EVT_F1_EN_V  0x00000001U
+#define MCPWM_EVT_F1_EN_S  16
+/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable fault2 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_F2_EN    (BIT(17))
+#define MCPWM_EVT_F2_EN_M  (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S)
+#define MCPWM_EVT_F2_EN_V  0x00000001U
+#define MCPWM_EVT_F2_EN_S  17
+/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable fault0 clear event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_F0_CLR_EN    (BIT(18))
+#define MCPWM_EVT_F0_CLR_EN_M  (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S)
+#define MCPWM_EVT_F0_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F0_CLR_EN_S  18
+/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable fault1 clear event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_F1_CLR_EN    (BIT(19))
+#define MCPWM_EVT_F1_CLR_EN_M  (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S)
+#define MCPWM_EVT_F1_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F1_CLR_EN_S  19
+/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable fault2 clear event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_F2_CLR_EN    (BIT(20))
+#define MCPWM_EVT_F2_CLR_EN_M  (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S)
+#define MCPWM_EVT_F2_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F2_CLR_EN_S  20
+/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable cycle-by-cycle trip0 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TZ0_CBC_EN    (BIT(21))
+#define MCPWM_EVT_TZ0_CBC_EN_M  (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S)
+#define MCPWM_EVT_TZ0_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ0_CBC_EN_S  21
+/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable cycle-by-cycle trip1 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TZ1_CBC_EN    (BIT(22))
+#define MCPWM_EVT_TZ1_CBC_EN_M  (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S)
+#define MCPWM_EVT_TZ1_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ1_CBC_EN_S  22
+/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable cycle-by-cycle trip2 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TZ2_CBC_EN    (BIT(23))
+#define MCPWM_EVT_TZ2_CBC_EN_M  (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S)
+#define MCPWM_EVT_TZ2_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ2_CBC_EN_S  23
+/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0;
+ *  Configures whether or not to enable one-shot trip0 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TZ0_OST_EN    (BIT(24))
+#define MCPWM_EVT_TZ0_OST_EN_M  (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S)
+#define MCPWM_EVT_TZ0_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ0_OST_EN_S  24
+/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not to enable one-shot trip1 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TZ1_OST_EN    (BIT(25))
+#define MCPWM_EVT_TZ1_OST_EN_M  (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S)
+#define MCPWM_EVT_TZ1_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ1_OST_EN_S  25
+/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0;
+ *  Configures whether or not to enable one-shot trip2 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_TZ2_OST_EN    (BIT(26))
+#define MCPWM_EVT_TZ2_OST_EN_M  (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S)
+#define MCPWM_EVT_TZ2_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ2_OST_EN_S  26
+/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to enable capture0 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_CAP0_EN    (BIT(27))
+#define MCPWM_EVT_CAP0_EN_M  (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S)
+#define MCPWM_EVT_CAP0_EN_V  0x00000001U
+#define MCPWM_EVT_CAP0_EN_S  27
+/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable capture1 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_CAP1_EN    (BIT(28))
+#define MCPWM_EVT_CAP1_EN_M  (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S)
+#define MCPWM_EVT_CAP1_EN_V  0x00000001U
+#define MCPWM_EVT_CAP1_EN_S  28
+/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable capture2 event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_CAP2_EN    (BIT(29))
+#define MCPWM_EVT_CAP2_EN_M  (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S)
+#define MCPWM_EVT_CAP2_EN_V  0x00000001U
+#define MCPWM_EVT_CAP2_EN_S  29
+
+/** MCPWM_TASK_EN_REG register
+ *  Task enable register
+ */
+#define MCPWM_TASK_EN_REG(i) (REG_MCPWM_BASE(i) + 0x124)
+/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
+ *  update task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CMPR0_A_UP_EN    (BIT(0))
+#define MCPWM_TASK_CMPR0_A_UP_EN_M  (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S)
+#define MCPWM_TASK_CMPR0_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR0_A_UP_EN_S  0
+/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
+ *  update task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CMPR1_A_UP_EN    (BIT(1))
+#define MCPWM_TASK_CMPR1_A_UP_EN_M  (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S)
+#define MCPWM_TASK_CMPR1_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR1_A_UP_EN_S  1
+/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
+ *  update task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CMPR2_A_UP_EN    (BIT(2))
+#define MCPWM_TASK_CMPR2_A_UP_EN_M  (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S)
+#define MCPWM_TASK_CMPR2_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR2_A_UP_EN_S  2
+/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
+ *  update task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CMPR0_B_UP_EN    (BIT(3))
+#define MCPWM_TASK_CMPR0_B_UP_EN_M  (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S)
+#define MCPWM_TASK_CMPR0_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR0_B_UP_EN_S  3
+/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
+ *  update task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CMPR1_B_UP_EN    (BIT(4))
+#define MCPWM_TASK_CMPR1_B_UP_EN_M  (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S)
+#define MCPWM_TASK_CMPR1_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR1_B_UP_EN_S  4
+/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
+ *  update task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CMPR2_B_UP_EN    (BIT(5))
+#define MCPWM_TASK_CMPR2_B_UP_EN_M  (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S)
+#define MCPWM_TASK_CMPR2_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR2_B_UP_EN_S  5
+/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable all PWM generate stop task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_GEN_STOP_EN    (BIT(6))
+#define MCPWM_TASK_GEN_STOP_EN_M  (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S)
+#define MCPWM_TASK_GEN_STOP_EN_V  0x00000001U
+#define MCPWM_TASK_GEN_STOP_EN_S  6
+/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable timer0 sync task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_TIMER0_SYNC_EN    (BIT(7))
+#define MCPWM_TASK_TIMER0_SYNC_EN_M  (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S)
+#define MCPWM_TASK_TIMER0_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER0_SYNC_EN_S  7
+/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable timer1 sync task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_TIMER1_SYNC_EN    (BIT(8))
+#define MCPWM_TASK_TIMER1_SYNC_EN_M  (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S)
+#define MCPWM_TASK_TIMER1_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER1_SYNC_EN_S  8
+/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable timer2 sync task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_TIMER2_SYNC_EN    (BIT(9))
+#define MCPWM_TASK_TIMER2_SYNC_EN_M  (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S)
+#define MCPWM_TASK_TIMER2_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER2_SYNC_EN_S  9
+/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable timer0 period update task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN    (BIT(10))
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S  10
+/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable timer1 period update task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN    (BIT(11))
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S  11
+/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable timer2 period update task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN    (BIT(12))
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S  12
+/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable one shot trip0 task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_TZ0_OST_EN    (BIT(13))
+#define MCPWM_TASK_TZ0_OST_EN_M  (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S)
+#define MCPWM_TASK_TZ0_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ0_OST_EN_S  13
+/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable one shot trip1 task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_TZ1_OST_EN    (BIT(14))
+#define MCPWM_TASK_TZ1_OST_EN_M  (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S)
+#define MCPWM_TASK_TZ1_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ1_OST_EN_S  14
+/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable one shot trip2 task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_TZ2_OST_EN    (BIT(15))
+#define MCPWM_TASK_TZ2_OST_EN_M  (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S)
+#define MCPWM_TASK_TZ2_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ2_OST_EN_S  15
+/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable one shot trip0 clear task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CLR0_OST_EN    (BIT(16))
+#define MCPWM_TASK_CLR0_OST_EN_M  (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S)
+#define MCPWM_TASK_CLR0_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR0_OST_EN_S  16
+/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable one shot trip1 clear task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CLR1_OST_EN    (BIT(17))
+#define MCPWM_TASK_CLR1_OST_EN_M  (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S)
+#define MCPWM_TASK_CLR1_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR1_OST_EN_S  17
+/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable one shot trip2 clear task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CLR2_OST_EN    (BIT(18))
+#define MCPWM_TASK_CLR2_OST_EN_M  (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S)
+#define MCPWM_TASK_CLR2_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR2_OST_EN_S  18
+/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable capture0 task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CAP0_EN    (BIT(19))
+#define MCPWM_TASK_CAP0_EN_M  (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S)
+#define MCPWM_TASK_CAP0_EN_V  0x00000001U
+#define MCPWM_TASK_CAP0_EN_S  19
+/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable capture1 task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CAP1_EN    (BIT(20))
+#define MCPWM_TASK_CAP1_EN_M  (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S)
+#define MCPWM_TASK_CAP1_EN_V  0x00000001U
+#define MCPWM_TASK_CAP1_EN_S  20
+/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable capture2 task receive.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_TASK_CAP2_EN    (BIT(21))
+#define MCPWM_TASK_CAP2_EN_M  (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S)
+#define MCPWM_TASK_CAP2_EN_V  0x00000001U
+#define MCPWM_TASK_CAP2_EN_S  21
+
+/** MCPWM_EVT_EN2_REG register
+ *  Event enable register2
+ */
+#define MCPWM_EVT_EN2_REG(i) (REG_MCPWM_BASE(i) + 0x128)
+/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
+ *  event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP0_TEE1_EN    (BIT(0))
+#define MCPWM_EVT_OP0_TEE1_EN_M  (MCPWM_EVT_OP0_TEE1_EN_V << MCPWM_EVT_OP0_TEE1_EN_S)
+#define MCPWM_EVT_OP0_TEE1_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEE1_EN_S  0
+/** MCPWM_EVT_OP1_TEE1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
+ *  event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP1_TEE1_EN    (BIT(1))
+#define MCPWM_EVT_OP1_TEE1_EN_M  (MCPWM_EVT_OP1_TEE1_EN_V << MCPWM_EVT_OP1_TEE1_EN_S)
+#define MCPWM_EVT_OP1_TEE1_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEE1_EN_S  1
+/** MCPWM_EVT_OP2_TEE1_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
+ *  event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP2_TEE1_EN    (BIT(2))
+#define MCPWM_EVT_OP2_TEE1_EN_M  (MCPWM_EVT_OP2_TEE1_EN_V << MCPWM_EVT_OP2_TEE1_EN_S)
+#define MCPWM_EVT_OP2_TEE1_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEE1_EN_S  2
+/** MCPWM_EVT_OP0_TEE2_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
+ *  event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP0_TEE2_EN    (BIT(3))
+#define MCPWM_EVT_OP0_TEE2_EN_M  (MCPWM_EVT_OP0_TEE2_EN_V << MCPWM_EVT_OP0_TEE2_EN_S)
+#define MCPWM_EVT_OP0_TEE2_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEE2_EN_S  3
+/** MCPWM_EVT_OP1_TEE2_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
+ *  event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP1_TEE2_EN    (BIT(4))
+#define MCPWM_EVT_OP1_TEE2_EN_M  (MCPWM_EVT_OP1_TEE2_EN_V << MCPWM_EVT_OP1_TEE2_EN_S)
+#define MCPWM_EVT_OP1_TEE2_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEE2_EN_S  4
+/** MCPWM_EVT_OP2_TEE2_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
+ *  event generate.
+ *  0: Disable
+ *  1: Enable
+ */
+#define MCPWM_EVT_OP2_TEE2_EN    (BIT(5))
+#define MCPWM_EVT_OP2_TEE2_EN_M  (MCPWM_EVT_OP2_TEE2_EN_V << MCPWM_EVT_OP2_TEE2_EN_S)
+#define MCPWM_EVT_OP2_TEE2_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEE2_EN_S  5
+
+/** MCPWM_OP0_TSTMP_E1_REG register
+ *  Generator0 timer stamp E1 value register
+ */
+#define MCPWM_OP0_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x12c)
+/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator0 timer stamp E1 value register
+ */
+#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
+#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_S  0
+
+/** MCPWM_OP0_TSTMP_E2_REG register
+ *  Generator0 timer stamp E2 value register
+ */
+#define MCPWM_OP0_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x130)
+/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator0 timer stamp E2 value register
+ */
+#define MCPWM_OP0_TSTMP_E2    0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E2_M  (MCPWM_OP0_TSTMP_E2_V << MCPWM_OP0_TSTMP_E2_S)
+#define MCPWM_OP0_TSTMP_E2_V  0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E2_S  0
+
+/** MCPWM_OP1_TSTMP_E1_REG register
+ *  Generator1 timer stamp E1 value register
+ */
+#define MCPWM_OP1_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x134)
+/** MCPWM_OP1_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator1 timer stamp E1 value register
+ */
+#define MCPWM_OP1_TSTMP_E1    0x0000FFFFU
+#define MCPWM_OP1_TSTMP_E1_M  (MCPWM_OP1_TSTMP_E1_V << MCPWM_OP1_TSTMP_E1_S)
+#define MCPWM_OP1_TSTMP_E1_V  0x0000FFFFU
+#define MCPWM_OP1_TSTMP_E1_S  0
+
+/** MCPWM_OP1_TSTMP_E2_REG register
+ *  Generator1 timer stamp E2 value register
+ */
+#define MCPWM_OP1_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x138)
+/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator1 timer stamp E2 value register
+ */
+#define MCPWM_OP1_TSTMP_E2    0x0000FFFFU
+#define MCPWM_OP1_TSTMP_E2_M  (MCPWM_OP1_TSTMP_E2_V << MCPWM_OP1_TSTMP_E2_S)
+#define MCPWM_OP1_TSTMP_E2_V  0x0000FFFFU
+#define MCPWM_OP1_TSTMP_E2_S  0
+
+/** MCPWM_OP2_TSTMP_E1_REG register
+ *  Generator2 timer stamp E1 value register
+ */
+#define MCPWM_OP2_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x13c)
+/** MCPWM_OP2_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator2 timer stamp E1 value register
+ */
+#define MCPWM_OP2_TSTMP_E1    0x0000FFFFU
+#define MCPWM_OP2_TSTMP_E1_M  (MCPWM_OP2_TSTMP_E1_V << MCPWM_OP2_TSTMP_E1_S)
+#define MCPWM_OP2_TSTMP_E1_V  0x0000FFFFU
+#define MCPWM_OP2_TSTMP_E1_S  0
+
+/** MCPWM_OP2_TSTMP_E2_REG register
+ *  Generator2 timer stamp E2 value register
+ */
+#define MCPWM_OP2_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x140)
+/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator2 timer stamp E2 value register
+ */
+#define MCPWM_OP2_TSTMP_E2    0x0000FFFFU
+#define MCPWM_OP2_TSTMP_E2_M  (MCPWM_OP2_TSTMP_E2_V << MCPWM_OP2_TSTMP_E2_S)
+#define MCPWM_OP2_TSTMP_E2_V  0x0000FFFFU
+#define MCPWM_OP2_TSTMP_E2_S  0
+
+/** MCPWM_CLK_REG register
+ *  Global configuration register
+ */
+#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x144)
+/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to open register clock gate.
+ *  0: Open the clock gate only when application writes registers
+ *  1: Force open the clock gate for register
+ */
+#define MCPWM_CLK_EN    (BIT(0))
+#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
+#define MCPWM_CLK_EN_V  0x00000001U
+#define MCPWM_CLK_EN_S  0
+
+/** MCPWM_VERSION_REG register
+ *  Version register.
+ */
+#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x148)
+/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35725968;
+ *  Configures the version.
+ */
+#define MCPWM_DATE    0x0FFFFFFFU
+#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
+#define MCPWM_DATE_V  0x0FFFFFFFU
+#define MCPWM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_struct.h
new file mode 100644
index 0000000000..e917dc7b3c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_struct.h
@@ -0,0 +1,1918 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_cfg */
+/** Type of clk_cfg register
+ *  PWM clock prescaler register.
+ */
+typedef union {
+    struct {
+        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
+         *  (PWM_CLK_PRESCALE + 1).
+         */
+        uint32_t clk_prescale:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_clk_cfg_reg_t;
+
+
+/** Group: timer */
+/** Type of timern_cfg0 register
+ *  PWM timern period and update method configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the prescaler value of timern, so that the period of PT0_clk = Period of
+         *  PWM_clk * (PWM_TIMERn_PRESCALE + 1)
+         */
+        uint32_t timer_prescale:8;
+        /** timer_period : R/W; bitpos: [23:8]; default: 255;
+         *  Configures the period shadow of PWM timern
+         */
+        uint32_t timer_period:16;
+        /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0;
+         *  Configures the update method for active register of PWM timern period.\\0:
+         *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
+         *  zero event
+         */
+        uint32_t timer_period_upmethod:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg0_reg_t;
+
+/** Type of timer0_cfg1 register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+typedef union {
+    struct {
+        /** timer_start : R/W/SC; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+         *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+         *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+         *  stops at the next TEP.\\TEP here and below means the event that happens when the
+         *  timer equals to period
+         */
+        uint32_t timer_start:3;
+        /** timer_mod : R/W; bitpos: [4:3]; default: 0;
+         *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+         *  Decrease mode\\3: Up-down mode
+         */
+        uint32_t timer_mod:2;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg1_reg_t;
+
+/** Type of timer0_sync register
+ *  PWM timer$n sync function configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_synci_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable timer$n reloading with phase on sync input
+         *  event is enabled.\\0: Disable\\1: Enable
+         */
+        uint32_t timer_synci_en:1;
+        /** timer_sync_sw : R/W; bitpos: [1]; default: 0;
+         *  Configures the generation of software sync. Toggling this bit will trigger a
+         *  software sync.
+         */
+        uint32_t timer_sync_sw:1;
+        /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+         *  Invalid, sync_out selects noting
+         */
+        uint32_t timer_synco_sel:2;
+        /** timer_phase : R/W; bitpos: [19:4]; default: 0;
+         *  Configures the phase for timer$n reload on sync event.
+         */
+        uint32_t timer_phase:16;
+        /** timer_phase_direction : R/W; bitpos: [20]; default: 0;
+         *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+         *  Increase\\1: Decrease
+         */
+        uint32_t timer_phase_direction:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} mcpwm_timer_sync_reg_t;
+
+/** Type of timer_status register
+ *  PWM timer$n status register.
+ */
+typedef union {
+    struct {
+        /** timer_value : RO; bitpos: [15:0]; default: 0;
+         *  Represents current PWM timer$n counter value.
+         */
+        uint32_t timer_value:16;
+        /** timer_direction : RO; bitpos: [16]; default: 0;
+         *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+         */
+        uint32_t timer_direction:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} mcpwm_timer_status_reg_t;
+
+
+/** Group: timer_synci_cfg */
+/** Type of timer_synci_cfg register
+ *  Synchronization input selection register for PWM timers.
+ */
+typedef union {
+    struct {
+        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
+         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+         */
+        uint32_t timer0_syncisel:3;
+        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
+         *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
+         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+         */
+        uint32_t timer1_syncisel:3;
+        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
+         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+         */
+        uint32_t timer2_syncisel:3;
+        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
+         *  Invert
+         */
+        uint32_t external_synci0_invert:1;
+        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
+         *  Invert
+         */
+        uint32_t external_synci1_invert:1;
+        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
+         *  Invert
+         */
+        uint32_t external_synci2_invert:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} mcpwm_timer_synci_cfg_reg_t;
+
+
+/** Group: operator_timersel */
+/** Type of operator_timersel register
+ *  PWM operator's timer select register
+ */
+typedef union {
+    struct {
+        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
+         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+         */
+        uint32_t operator0_timersel:2;
+        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
+         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+         */
+        uint32_t operator1_timersel:2;
+        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
+         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+         */
+        uint32_t operator2_timersel:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_operator_timersel_reg_t;
+
+
+/** Group: operators */
+/** Type of genn_stmp_cfg register
+ *  Generatorn time stamp registers A and B transfer status and update method register
+ */
+typedef union {
+    struct {
+        /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the update method for PWM generator n time stamp A's active
+         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t cmpr_a_upmethod:4;
+        /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Configures the update method for PWM generator n time stamp B's active
+         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t cmpr_b_upmethod:4;
+        /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
+         *  Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0:
+         *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
+         *  reg is filled and waiting to be transferred to A's active reg
+         */
+        uint32_t cmpr_a_shdw_full:1;
+        /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
+         *  Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0:
+         *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
+         *  reg is filled and waiting to be transferred to B's active reg
+         */
+        uint32_t cmpr_b_shdw_full:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_gen_stmp_cfg_reg_t;
+
+/** Type of gen_tstmp_a register
+ *  Generator$n time stamp A's shadow register
+ */
+typedef union {
+    struct {
+        /** cmpr : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the value of PWM generator $n time stamp 's shadow register.
+         */
+        uint32_t cmpr:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_tstmp_reg_t;
+
+
+/** Type of gen_cfg0 register
+ *  Generator$n fault event T0 and T1 configuration register
+ */
+typedef union {
+    struct {
+        /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures update method for PWM generator $n's active register.\\0:
+         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t gen_cfg_upmethod:4;
+        /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0;
+         *  Configures source selection for PWM generator $n event_t0, take effect
+         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+         *  Invalid, Select nothing
+         */
+        uint32_t gen_t0_sel:3;
+        /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0;
+         *  Configures source selection for PWM generator $n event_t1, take effect
+         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+         *  Invalid, Select nothing
+         */
+        uint32_t gen_t1_sel:3;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_gen_cfg0_reg_t;
+
+/** Type of gen_force register
+ *  Generator$n output signal force mode register.
+ */
+typedef union {
+    struct {
+        /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
+         *  Configures update method for continuous software force of PWM generator$n.\\0:
+         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
+         *  update. TEA/B here and below means an event generated when the timer's value equals
+         *  to that of register A/B.
+         */
+        uint32_t gen_cntuforce_upmethod:6;
+        /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
+         *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
+         *  High\\3: Disabled
+         */
+        uint32_t gen_a_cntuforce_mode:2;
+        /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
+         *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
+         *  High\\3: Disabled
+         */
+        uint32_t gen_b_cntuforce_mode:2;
+        /** gen_a_nciforce : R/W; bitpos: [10]; default: 0;
+         *  Configures the generation of non-continuous immediate software-force event for
+         *  PWM$n A, a toggle will trigger a force event.
+         */
+        uint32_t gen_a_nciforce:1;
+        /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
+         *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
+         *  Disabled\\1: Low\\2: High\\3: Disabled
+         */
+        uint32_t gen_a_nciforce_mode:2;
+        /** gen_b_nciforce : R/W; bitpos: [13]; default: 0;
+         *  Configures the generation of non-continuous immediate software-force event for
+         *  PWM$n B, a toggle will trigger a force event.
+         */
+        uint32_t gen_b_nciforce:1;
+        /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
+         *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
+         *  Disabled\\1: Low\\2: High\\3: Disabled
+         */
+        uint32_t gen_b_nciforce_mode:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_force_reg_t;
+
+/** Type of gen register
+ *  PWM$n output signal A actions configuration register
+ */
+typedef union {
+    struct {
+        /** gen_a_utez : R/W; bitpos: [1:0]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_utez:2;
+        /** gen_a_utep : R/W; bitpos: [3:2]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_utep:2;
+        /** gen_a_utea : R/W; bitpos: [5:4]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_utea:2;
+        /** gen_a_uteb : R/W; bitpos: [7:6]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_uteb:2;
+        /** gen_a_ut0 : R/W; bitpos: [9:8]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_ut0:2;
+        /** gen_a_ut1 : R/W; bitpos: [11:10]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_ut1:2;
+        /** gen_a_dtez : R/W; bitpos: [13:12]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dtez:2;
+        /** gen_a_dtep : R/W; bitpos: [15:14]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dtep:2;
+        /** gen_a_dtea : R/W; bitpos: [17:16]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dtea:2;
+        /** gen_a_dteb : R/W; bitpos: [19:18]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dteb:2;
+        /** gen_a_dt0 : R/W; bitpos: [21:20]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dt0:2;
+        /** gen_a_dt1 : R/W; bitpos: [23:22]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dt1:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_gen_reg_t;
+
+/** Type of dt0_cfg register
+ *  Dead time configuration register
+ */
+typedef union {
+    struct {
+        /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures update method for FED (Falling edge delay) active register.\\0:
+         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t db_fed_upmethod:4;
+        /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Configures update method for RED (rising edge delay) active register.\\0:
+         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t db_red_upmethod:4;
+        /** db_deb_mode : R/W; bitpos: [8]; default: 0;
+         *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
+         *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
+         */
+        uint32_t db_deb_mode:1;
+        /** db_a_outswap : R/W; bitpos: [9]; default: 0;
+         *  Configures S6 in table.
+         */
+        uint32_t db_a_outswap:1;
+        /** db_b_outswap : R/W; bitpos: [10]; default: 0;
+         *  Configures S7 in table.
+         */
+        uint32_t db_b_outswap:1;
+        /** db_red_insel : R/W; bitpos: [11]; default: 0;
+         *  Configures S4 in table.
+         */
+        uint32_t db_red_insel:1;
+        /** db_fed_insel : R/W; bitpos: [12]; default: 0;
+         *  Configures S5 in table.
+         */
+        uint32_t db_fed_insel:1;
+        /** db_red_outinvert : R/W; bitpos: [13]; default: 0;
+         *  Configures S2 in table.
+         */
+        uint32_t db_red_outinvert:1;
+        /** db_fed_outinvert : R/W; bitpos: [14]; default: 0;
+         *  Configures S3 in table.
+         */
+        uint32_t db_fed_outinvert:1;
+        /** db_a_outbypass : R/W; bitpos: [15]; default: 1;
+         *  Configures S1 in table.
+         */
+        uint32_t db_a_outbypass:1;
+        /** db_b_outbypass : R/W; bitpos: [16]; default: 1;
+         *  Configures S0 in table.
+         */
+        uint32_t db_b_outbypass:1;
+        /** db_clk_sel : R/W; bitpos: [17]; default: 0;
+         *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
+         */
+        uint32_t db_clk_sel:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} mcpwm_dt_cfg_reg_t;
+
+/** Type of dt0_fed_cfg register
+ *  Falling edge delay (FED) shadow register
+ */
+typedef union {
+    struct {
+        /** db_fed : R/W; bitpos: [15:0]; default: 0;
+         *  Configures shadow register for FED.
+         */
+        uint32_t db_fed:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dt_fed_cfg_reg_t;
+
+/** Type of dt0_red_cfg register
+ *  Rising edge delay (RED) shadow register
+ */
+typedef union {
+    struct {
+        /** db_red : R/W; bitpos: [15:0]; default: 0;
+         *  Configures shadow register for RED.
+         */
+        uint32_t db_red:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dt_red_cfg_reg_t;
+
+/** Type of carrier0_cfg register
+ *  Carrier$n configuration register
+ */
+typedef union {
+    struct {
+        /** chopper_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
+         */
+        uint32_t chopper_en:1;
+        /** chopper_prescale : R/W; bitpos: [4:1]; default: 0;
+         *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
+         *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
+         */
+        uint32_t chopper_prescale:4;
+        /** chopper_duty : R/W; bitpos: [7:5]; default: 0;
+         *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
+         */
+        uint32_t chopper_duty:3;
+        /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0;
+         *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+         */
+        uint32_t chopper_oshtwth:4;
+        /** chopper_out_invert : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
+         *  submodule.\\0: Normal\\1: Invert
+         */
+        uint32_t chopper_out_invert:1;
+        /** chopper_in_invert : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
+         *  submodule.\\0: Normal\\1: Invert
+         */
+        uint32_t chopper_in_invert:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} mcpwm_carrier_cfg_reg_t;
+
+/** Type of fh0_cfg0 register
+ *  PWM$n A and PWM$n B trip events actions configuration register
+ */
+typedef union {
+    struct {
+        /** tz_sw_cbc : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_sw_cbc:1;
+        /** tz_f2_cbc : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f2_cbc:1;
+        /** tz_f1_cbc : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f1_cbc:1;
+        /** tz_f0_cbc : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f0_cbc:1;
+        /** tz_sw_ost : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable software force one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_sw_ost:1;
+        /** tz_f2_ost : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f2_ost:1;
+        /** tz_f1_ost : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f1_ost:1;
+        /** tz_f0_ost : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f0_ost:1;
+        /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_a_cbc_d:2;
+        /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_a_cbc_u:2;
+        /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0;
+         *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_a_ost_d:2;
+        /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0;
+         *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_a_ost_u:2;
+        /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_b_cbc_d:2;
+        /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_b_cbc_u:2;
+        /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0;
+         *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_b_ost_d:2;
+        /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0;
+         *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_b_ost_u:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg0_reg_t;
+
+/** Type of fh0_cfg1 register
+ *  Software triggers for fault handler actions configuration register
+ */
+typedef union {
+    struct {
+        /** tz_clr_ost : R/W; bitpos: [0]; default: 0;
+         *  Configures the generation of software one-shot mode action clear. A toggle
+         *  (software negate its value) triggers a clear for on going one-shot mode action.
+         */
+        uint32_t tz_clr_ost:1;
+        /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0;
+         *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
+         *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
+         */
+        uint32_t tz_cbcpulse:2;
+        /** tz_force_cbc : R/W; bitpos: [3]; default: 0;
+         *  Configures the generation of software cycle-by-cycle mode action. A toggle
+         *  (software negate its value) triggers a cycle-by-cycle mode action.
+         */
+        uint32_t tz_force_cbc:1;
+        /** tz_force_ost : R/W; bitpos: [4]; default: 0;
+         *  Configures the generation of software one-shot mode action. A toggle (software
+         *  negate its value) triggers a one-shot mode action.
+         */
+        uint32_t tz_force_ost:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg1_reg_t;
+
+/** Type of fh0_status register
+ *  Fault events status register
+ */
+typedef union {
+    struct {
+        /** tz_cbc_on : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
+         *  action\\1: On going
+         */
+        uint32_t tz_cbc_on:1;
+        /** tz_ost_on : RO; bitpos: [1]; default: 0;
+         *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
+         *  going
+         */
+        uint32_t tz_ost_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} mcpwm_fh_status_reg_t;
+
+/** Group: fault_detect */
+/** Type of fault_detect register
+ *  Fault detection configuration and status register
+ */
+typedef union {
+    struct {
+        /** f0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
+         */
+        uint32_t f0_en:1;
+        /** f1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
+         */
+        uint32_t f1_en:1;
+        /** f2_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
+         */
+        uint32_t f2_en:1;
+        /** f0_pole : R/W; bitpos: [3]; default: 0;
+         *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
+         *  low\\1: Level high
+         */
+        uint32_t f0_pole:1;
+        /** f1_pole : R/W; bitpos: [4]; default: 0;
+         *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
+         *  low\\1: Level high
+         */
+        uint32_t f1_pole:1;
+        /** f2_pole : R/W; bitpos: [5]; default: 0;
+         *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
+         *  low\\1: Level high
+         */
+        uint32_t f2_pole:1;
+        /** event_f0 : RO; bitpos: [6]; default: 0;
+         *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
+         */
+        uint32_t event_f0:1;
+        /** event_f1 : RO; bitpos: [7]; default: 0;
+         *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
+         */
+        uint32_t event_f1:1;
+        /** event_f2 : RO; bitpos: [8]; default: 0;
+         *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
+         */
+        uint32_t event_f2:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} mcpwm_fault_detect_reg_t;
+
+
+/** Group: cap_timer_cfg */
+/** Type of cap_timer_cfg register
+ *  Capture timer configuration register
+ */
+typedef union {
+    struct {
+        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
+         */
+        uint32_t cap_timer_en:1;
+        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
+         */
+        uint32_t cap_synci_en:1;
+        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
+         *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
+         *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
+         *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
+         */
+        uint32_t cap_synci_sel:3;
+        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
+         *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
+         *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
+         *  value in phase register
+         */
+        uint32_t cap_sync_sw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_cfg_reg_t;
+
+
+/** Group: cap_timer_phase */
+/** Type of cap_timer_phase register
+ *  Capture timer sync phase register
+ */
+typedef union {
+    struct {
+        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
+         *  Configures phase value for capture timer sync operation.
+         */
+        uint32_t cap_phase:32;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_phase_reg_t;
+
+
+/** Group: cap_chn_cfg */
+/** Type of cap_chn_cfg register
+ *  Capture channel n configuration register
+ */
+typedef union {
+    struct {
+        /** capn_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable
+         */
+        uint32_t capn_en:1;
+        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
+         *  Configures which edge of capture on channel n after prescaling is used.\\0:
+         *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
+         *  Enable capture on the positive edge
+         */
+        uint32_t capn_mode:2;
+        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
+         *  Configures prescale value on positive edge of CAPn. Prescale value =
+         *  PWM_CAPn_PRESCALE + 1
+         */
+        uint32_t capn_prescale:8;
+        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0:
+         *  Normal\\1: Invert
+         */
+        uint32_t capn_in_invert:1;
+        /** capn_sw : WT; bitpos: [12]; default: 0;
+         *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
+         *  software forced capture on channel n
+         */
+        uint32_t capn_sw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_cfg_reg_t;
+
+
+/** Group: cap_chn */
+/** Type of cap_chn register
+ *  CAPn capture value register
+ */
+typedef union {
+    struct {
+        /** capn_value : RO; bitpos: [31:0]; default: 0;
+         *  Represents value of last capture on CAPn
+         */
+        uint32_t capn_value:32;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_reg_t;
+
+
+/** Group: cap_status */
+/** Type of cap_status register
+ *  Last capture trigger edge information register
+ */
+typedef union {
+    struct {
+        /** cap0_edge : RO; bitpos: [0]; default: 0;
+         *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
+         */
+        uint32_t cap0_edge:1;
+        /** cap1_edge : RO; bitpos: [1]; default: 0;
+         *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
+         */
+        uint32_t cap1_edge:1;
+        /** cap2_edge : RO; bitpos: [2]; default: 0;
+         *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
+         */
+        uint32_t cap2_edge:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} mcpwm_cap_status_reg_t;
+
+
+/** Group: update_cfg */
+/** Type of update_cfg register
+ *  Generator Update configuration register
+ */
+typedef union {
+    struct {
+        /** global_up_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether or not to enable global update for all active registers in MCPWM
+         *  module.\\0: Disable\\1: Enable
+         */
+        uint32_t global_up_en:1;
+        /** global_force_up : R/W; bitpos: [1]; default: 0;
+         *  Configures the generation of global forced update for all active registers in MCPWM
+         *  module. A toggle (software invert its value) will trigger a global forced update.
+         *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
+         */
+        uint32_t global_force_up:1;
+        /** op0_up_en : R/W; bitpos: [2]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator$n.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+         */
+        uint32_t op0_up_en:1;
+        /** op0_force_up : R/W; bitpos: [3]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator0. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
+         */
+        uint32_t op0_force_up:1;
+        /** op1_up_en : R/W; bitpos: [4]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator$n.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+         */
+        uint32_t op1_up_en:1;
+        /** op1_force_up : R/W; bitpos: [5]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator1. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
+         */
+        uint32_t op1_force_up:1;
+        /** op2_up_en : R/W; bitpos: [6]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator$n.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+         */
+        uint32_t op2_up_en:1;
+        /** op2_force_up : R/W; bitpos: [7]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator2. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
+         */
+        uint32_t op2_force_up:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_update_cfg_reg_t;
+
+
+/** Group: int_ena */
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_ena:1;
+        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_ena:1;
+        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_ena:1;
+        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_ena:1;
+        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_ena:1;
+        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_ena:1;
+        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_ena:1;
+        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_ena:1;
+        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_ena:1;
+        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_ena:1;
+        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_ena:1;
+        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_ena:1;
+        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
+         */
+        uint32_t fault0_clr_int_ena:1;
+        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
+         */
+        uint32_t fault1_clr_int_ena:1;
+        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
+         */
+        uint32_t fault2_clr_int_ena:1;
+        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
+         */
+        uint32_t cmpr0_tea_int_ena:1;
+        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
+         */
+        uint32_t cmpr1_tea_int_ena:1;
+        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
+         */
+        uint32_t cmpr2_tea_int_ena:1;
+        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
+         */
+        uint32_t cmpr0_teb_int_ena:1;
+        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
+         */
+        uint32_t cmpr1_teb_int_ena:1;
+        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
+         */
+        uint32_t cmpr2_teb_int_ena:1;
+        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM0.
+         */
+        uint32_t tz0_cbc_int_ena:1;
+        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM1.
+         */
+        uint32_t tz1_cbc_int_ena:1;
+        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM2.
+         */
+        uint32_t tz2_cbc_int_ena:1;
+        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_ost_int_ena:1;
+        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_ost_int_ena:1;
+        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_ost_int_ena:1;
+        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
+         */
+        uint32_t cap0_int_ena:1;
+        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
+         */
+        uint32_t cap1_int_ena:1;
+        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
+         */
+        uint32_t cap2_int_ena:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_ena_reg_t;
+
+
+/** Group: int_raw */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  0 stops.
+         */
+        uint32_t timer0_stop_int_raw:1;
+        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  1 stops.
+         */
+        uint32_t timer1_stop_int_raw:1;
+        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  2 stops.
+         */
+        uint32_t timer2_stop_int_raw:1;
+        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  0 TEZ event.
+         */
+        uint32_t timer0_tez_int_raw:1;
+        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  1 TEZ event.
+         */
+        uint32_t timer1_tez_int_raw:1;
+        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  2 TEZ event.
+         */
+        uint32_t timer2_tez_int_raw:1;
+        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  0 TEP event.
+         */
+        uint32_t timer0_tep_int_raw:1;
+        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  1 TEP event.
+         */
+        uint32_t timer1_tep_int_raw:1;
+        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  2 TEP event.
+         */
+        uint32_t timer2_tep_int_raw:1;
+        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+         *  starts.
+         */
+        uint32_t fault0_int_raw:1;
+        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+         *  starts.
+         */
+        uint32_t fault1_int_raw:1;
+        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+         *  starts.
+         */
+        uint32_t fault2_int_raw:1;
+        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+         *  clears.
+         */
+        uint32_t fault0_clr_int_raw:1;
+        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+         *  clears.
+         */
+        uint32_t fault1_clr_int_raw:1;
+        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+         *  clears.
+         */
+        uint32_t fault2_clr_int_raw:1;
+        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_raw:1;
+        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_raw:1;
+        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_raw:1;
+        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_raw:1;
+        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_raw:1;
+        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_raw:1;
+        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t tz0_cbc_int_raw:1;
+        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t tz1_cbc_int_raw:1;
+        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t tz2_cbc_int_raw:1;
+        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_raw:1;
+        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_raw:1;
+        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_raw:1;
+        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP0.
+         */
+        uint32_t cap0_int_raw:1;
+        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP1.
+         */
+        uint32_t cap1_int_raw:1;
+        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP2.
+         */
+        uint32_t cap2_int_raw:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_raw_reg_t;
+
+
+/** Group: int_st */
+/** Type of int_st register
+ *  Interrupt masked status register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 0 stops.
+         */
+        uint32_t timer0_stop_int_st:1;
+        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 1 stops.
+         */
+        uint32_t timer1_stop_int_st:1;
+        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 2 stops.
+         */
+        uint32_t timer2_stop_int_st:1;
+        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_st:1;
+        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_st:1;
+        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_st:1;
+        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_st:1;
+        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_st:1;
+        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_st:1;
+        /** fault0_int_st : RO; bitpos: [9]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f0 starts.
+         */
+        uint32_t fault0_int_st:1;
+        /** fault1_int_st : RO; bitpos: [10]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f1 starts.
+         */
+        uint32_t fault1_int_st:1;
+        /** fault2_int_st : RO; bitpos: [11]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f2 starts.
+         */
+        uint32_t fault2_int_st:1;
+        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f0 clears.
+         */
+        uint32_t fault0_clr_int_st:1;
+        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f1 clears.
+         */
+        uint32_t fault1_clr_int_st:1;
+        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f2 clears.
+         */
+        uint32_t fault2_clr_int_st:1;
+        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_st:1;
+        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_st:1;
+        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_st:1;
+        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_st:1;
+        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_st:1;
+        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_st:1;
+        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t tz0_cbc_int_st:1;
+        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t tz1_cbc_int_st:1;
+        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t tz2_cbc_int_st:1;
+        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_st:1;
+        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_st:1;
+        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_st:1;
+        /** cap0_int_st : RO; bitpos: [27]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP0.
+         */
+        uint32_t cap0_int_st:1;
+        /** cap1_int_st : RO; bitpos: [28]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP1.
+         */
+        uint32_t cap1_int_st:1;
+        /** cap2_int_st : RO; bitpos: [29]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP2.
+         */
+        uint32_t cap2_int_st:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_st_reg_t;
+
+
+/** Group: int_clr */
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_clr:1;
+        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_clr:1;
+        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_clr:1;
+        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_clr:1;
+        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_clr:1;
+        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_clr:1;
+        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_clr:1;
+        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_clr:1;
+        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_clr:1;
+        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_clr:1;
+        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_clr:1;
+        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_clr:1;
+        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
+         */
+        uint32_t fault0_clr_int_clr:1;
+        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
+         */
+        uint32_t fault1_clr_int_clr:1;
+        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
+         */
+        uint32_t fault2_clr_int_clr:1;
+        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_clr:1;
+        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_clr:1;
+        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_clr:1;
+        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_clr:1;
+        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_clr:1;
+        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_clr:1;
+        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM0.
+         */
+        uint32_t tz0_cbc_int_clr:1;
+        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM1.
+         */
+        uint32_t tz1_cbc_int_clr:1;
+        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM2.
+         */
+        uint32_t tz2_cbc_int_clr:1;
+        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_ost_int_clr:1;
+        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_ost_int_clr:1;
+        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_ost_int_clr:1;
+        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
+         */
+        uint32_t cap0_int_clr:1;
+        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
+         */
+        uint32_t cap1_int_clr:1;
+        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
+         */
+        uint32_t cap2_int_clr:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_clr_reg_t;
+
+
+/** Group: evt_en */
+/** Type of evt_en register
+ *  Event enable register
+ */
+typedef union {
+    struct {
+        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer0_stop_en:1;
+        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer1_stop_en:1;
+        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer2_stop_en:1;
+        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable timer0 equal zero event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer0_tez_en:1;
+        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable timer1 equal zero event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer1_tez_en:1;
+        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable timer2 equal zero event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer2_tez_en:1;
+        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable timer0 equal period event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer0_tep_en:1;
+        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable timer1 equal period event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer1_tep_en:1;
+        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable timer2 equal period event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer2_tep_en:1;
+        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal a event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_tea_en:1;
+        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal a event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_tea_en:1;
+        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal a event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_tea_en:1;
+        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal b event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_teb_en:1;
+        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal b event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_teb_en:1;
+        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal b event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_teb_en:1;
+        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_f0_en:1;
+        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_f1_en:1;
+        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_f2_en:1;
+        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_f0_clr_en:1;
+        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_f1_clr_en:1;
+        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_f2_clr_en:1;
+        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_tz0_cbc_en:1;
+        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_tz1_cbc_en:1;
+        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_tz2_cbc_en:1;
+        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_tz0_ost_en:1;
+        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_tz1_ost_en:1;
+        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_tz2_ost_en:1;
+        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_cap0_en:1;
+        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_cap1_en:1;
+        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_cap2_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_evt_en_reg_t;
+
+
+/** Group: task_en */
+/** Type of task_en register
+ *  Task enable register
+ */
+typedef union {
+    struct {
+        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr0_a_up_en:1;
+        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr1_a_up_en:1;
+        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr2_a_up_en:1;
+        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr0_b_up_en:1;
+        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr1_b_up_en:1;
+        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr2_b_up_en:1;
+        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable all PWM generate stop task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_gen_stop_en:1;
+        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer0_sync_en:1;
+        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer1_sync_en:1;
+        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer2_sync_en:1;
+        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable timer0 period update task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_timer0_period_up_en:1;
+        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable timer1 period update task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_timer1_period_up_en:1;
+        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable timer2 period update task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_timer2_period_up_en:1;
+        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_tz0_ost_en:1;
+        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_tz1_ost_en:1;
+        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_tz2_ost_en:1;
+        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_clr0_ost_en:1;
+        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_clr1_ost_en:1;
+        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_clr2_ost_en:1;
+        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cap0_en:1;
+        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cap1_en:1;
+        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cap2_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} mcpwm_task_en_reg_t;
+
+
+/** Group: evt_en2 */
+/** Type of evt_en2 register
+ *  Event enable register2
+ */
+typedef union {
+    struct {
+        /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_tee1_en:1;
+        /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_tee1_en:1;
+        /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_tee1_en:1;
+        /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_tee2_en:1;
+        /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_tee2_en:1;
+        /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_tee2_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_evt_en2_reg_t;
+
+
+/** Group: Configuration register */
+/** Type of opn_tstmp_e1 register
+ *  Generatorn timer stamp E1 value register
+ */
+typedef union {
+    struct {
+        /** op_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures generatorn timer stamp E1 value register
+         */
+        uint32_t op_tstmp_e:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_op_tstmp_reg_t;
+
+/** Type of clk register
+ *  Global configuration register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
+         *  when application writes registers\\1: Force open the clock gate for register
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mcpwm_clk_reg_t;
+
+
+/** Group: Version register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35725968;
+         *  Configures the version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} mcpwm_version_reg_t;
+
+typedef struct {
+    volatile mcpwm_timer_cfg0_reg_t timer_cfg0;
+    volatile mcpwm_timer_cfg1_reg_t timer_cfg1;
+    volatile mcpwm_timer_sync_reg_t timer_sync;
+    volatile mcpwm_timer_status_reg_t timer_status;
+} mcpwm_timer_regs_t;
+
+typedef struct {
+    volatile mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
+    volatile mcpwm_gen_tstmp_reg_t timestamp[2];
+    volatile mcpwm_gen_cfg0_reg_t gen_cfg0;
+    volatile mcpwm_gen_force_reg_t gen_force;
+    volatile mcpwm_gen_reg_t generator[2];
+    volatile mcpwm_dt_cfg_reg_t dt_cfg;
+    volatile mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
+    volatile mcpwm_dt_red_cfg_reg_t dt_red_cfg;
+    volatile mcpwm_carrier_cfg_reg_t carrier_cfg;
+    volatile mcpwm_fh_cfg0_reg_t fh_cfg0;
+    volatile mcpwm_fh_cfg1_reg_t fh_cfg1;
+    volatile mcpwm_fh_status_reg_t fh_status;
+} mcpwm_operator_reg_t;
+
+typedef struct {
+    volatile mcpwm_op_tstmp_reg_t timestamp[2];
+} mcpwm_operator_tstmp_reg_t;
+
+typedef struct mcpwm_dev_t {
+    volatile mcpwm_clk_cfg_reg_t clk_cfg;
+    volatile mcpwm_timer_regs_t timer[3];
+    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
+    volatile mcpwm_operator_timersel_reg_t operator_timersel;
+    volatile mcpwm_operator_reg_t operators[3];
+    volatile mcpwm_fault_detect_reg_t fault_detect;
+    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
+    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
+    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
+    volatile mcpwm_cap_chn_reg_t cap_chn[3];
+    volatile mcpwm_cap_status_reg_t cap_status;
+    volatile mcpwm_update_cfg_reg_t update_cfg;
+    volatile mcpwm_int_ena_reg_t int_ena;
+    volatile mcpwm_int_raw_reg_t int_raw;
+    volatile mcpwm_int_st_reg_t int_st;
+    volatile mcpwm_int_clr_reg_t int_clr;
+    volatile mcpwm_evt_en_reg_t evt_en;
+    volatile mcpwm_task_en_reg_t task_en;
+    volatile mcpwm_evt_en2_reg_t evt_en2;
+    volatile mcpwm_operator_tstmp_reg_t operators_timestamp[3];
+    volatile mcpwm_clk_reg_t clk;
+    volatile mcpwm_version_reg_t version;
+} mcpwm_dev_t;
+
+extern mcpwm_dev_t MCPWM0;
+extern mcpwm_dev_t MCPWM1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mem_monitor_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/mem_monitor_reg.h
new file mode 100644
index 0000000000..104e4c06f1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mem_monitor_reg.h
@@ -0,0 +1,217 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MEM_MONITOR_LOG_SETTING_REG register
+ *  log config register
+ */
+#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
+/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
+ *  Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE
+ *  monitor
+ */
+#define MEM_MONITOR_LOG_MODE    0x0000000FU
+#define MEM_MONITOR_LOG_MODE_M  (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
+#define MEM_MONITOR_LOG_MODE_V  0x0000000FU
+#define MEM_MONITOR_LOG_MODE_S  0
+/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1;
+ *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
+ */
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE    (BIT(4))
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M  (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  4
+/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0;
+ *  enable core log
+ */
+#define MEM_MONITOR_LOG_CORE_ENA    0x000000FFU
+#define MEM_MONITOR_LOG_CORE_ENA_M  (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S)
+#define MEM_MONITOR_LOG_CORE_ENA_V  0x000000FFU
+#define MEM_MONITOR_LOG_CORE_ENA_S  8
+/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0;
+ *  enable dma_0 log
+ */
+#define MEM_MONITOR_LOG_DMA_0_ENA    0x000000FFU
+#define MEM_MONITOR_LOG_DMA_0_ENA_M  (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S)
+#define MEM_MONITOR_LOG_DMA_0_ENA_V  0x000000FFU
+#define MEM_MONITOR_LOG_DMA_0_ENA_S  16
+/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0;
+ *  enable dma_1 log
+ */
+#define MEM_MONITOR_LOG_DMA_1_ENA    0x000000FFU
+#define MEM_MONITOR_LOG_DMA_1_ENA_M  (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S)
+#define MEM_MONITOR_LOG_DMA_1_ENA_V  0x000000FFU
+#define MEM_MONITOR_LOG_DMA_1_ENA_S  24
+
+/** MEM_MONITOR_LOG_SETTING1_REG register
+ *  log config register
+ */
+#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
+/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
+ *  enable dma_2 log
+ */
+#define MEM_MONITOR_LOG_DMA_2_ENA    0x000000FFU
+#define MEM_MONITOR_LOG_DMA_2_ENA_M  (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S)
+#define MEM_MONITOR_LOG_DMA_2_ENA_V  0x000000FFU
+#define MEM_MONITOR_LOG_DMA_2_ENA_S  0
+/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0;
+ *  enable dma_3 log
+ */
+#define MEM_MONITOR_LOG_DMA_3_ENA    0x000000FFU
+#define MEM_MONITOR_LOG_DMA_3_ENA_M  (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S)
+#define MEM_MONITOR_LOG_DMA_3_ENA_V  0x000000FFU
+#define MEM_MONITOR_LOG_DMA_3_ENA_S  8
+
+/** MEM_MONITOR_LOG_CHECK_DATA_REG register
+ *  check data register
+ */
+#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
+/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The special check data, when write this special data, it will trigger logging.
+ */
+#define MEM_MONITOR_LOG_CHECK_DATA    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_CHECK_DATA_M  (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
+#define MEM_MONITOR_LOG_CHECK_DATA_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_CHECK_DATA_S  0
+
+/** MEM_MONITOR_LOG_DATA_MASK_REG register
+ *  check data mask register
+ */
+#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
+/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
+ *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
+ *  mask second byte, and so on.
+ */
+#define MEM_MONITOR_LOG_DATA_MASK    0x0000000FU
+#define MEM_MONITOR_LOG_DATA_MASK_M  (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
+#define MEM_MONITOR_LOG_DATA_MASK_V  0x0000000FU
+#define MEM_MONITOR_LOG_DATA_MASK_S  0
+
+/** MEM_MONITOR_LOG_MIN_REG register
+ *  log boundary register
+ */
+#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
+/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  the min address of log range
+ */
+#define MEM_MONITOR_LOG_MIN    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MIN_M  (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
+#define MEM_MONITOR_LOG_MIN_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MIN_S  0
+
+/** MEM_MONITOR_LOG_MAX_REG register
+ *  log boundary register
+ */
+#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
+/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  the max address of log range
+ */
+#define MEM_MONITOR_LOG_MAX    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MAX_M  (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
+#define MEM_MONITOR_LOG_MAX_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MAX_S  0
+
+/** MEM_MONITOR_LOG_MEM_START_REG register
+ *  log message store range register
+ */
+#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
+/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
+ *  the start address of writing logging message
+ */
+#define MEM_MONITOR_LOG_MEM_START    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_START_M  (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
+#define MEM_MONITOR_LOG_MEM_START_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_START_S  0
+
+/** MEM_MONITOR_LOG_MEM_END_REG register
+ *  log message store range register
+ */
+#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
+/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
+ *  the end address of writing logging message
+ */
+#define MEM_MONITOR_LOG_MEM_END    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_END_M  (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
+#define MEM_MONITOR_LOG_MEM_END_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_END_S  0
+
+/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
+ *  current writing address.
+ */
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
+/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  means next writing address
+ */
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M  (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S  0
+
+/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
+ *  writing address update
+ */
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
+/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
+ *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
+ */
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE    (BIT(0))
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M  (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S  0
+
+/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
+ *  full flag status register
+ */
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
+/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
+ *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
+ */
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG    (BIT(0))
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S  0
+/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
+ *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
+ */
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V  0x00000001U
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S  1
+
+/** MEM_MONITOR_CLOCK_GATE_REG register
+ *  clock gate force on register
+ */
+#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c)
+/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to force on the clk of mem_monitor register
+ */
+#define MEM_MONITOR_CLK_EN    (BIT(0))
+#define MEM_MONITOR_CLK_EN_M  (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
+#define MEM_MONITOR_CLK_EN_V  0x00000001U
+#define MEM_MONITOR_CLK_EN_S  0
+
+/** MEM_MONITOR_DATE_REG register
+ *  version register
+ */
+#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
+/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 36708896;
+ *  version register
+ */
+#define MEM_MONITOR_DATE    0x0FFFFFFFU
+#define MEM_MONITOR_DATE_M  (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
+#define MEM_MONITOR_DATE_V  0x0FFFFFFFU
+#define MEM_MONITOR_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mem_monitor_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mem_monitor_struct.h
new file mode 100644
index 0000000000..18fe8db503
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mem_monitor_struct.h
@@ -0,0 +1,247 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration registers */
+/** Type of log_setting register
+ *  log config register
+ */
+typedef union {
+    struct {
+        /** log_mode : R/W; bitpos: [3:0]; default: 0;
+         *  Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE
+         *  monitor
+         */
+        uint32_t log_mode:4;
+        /** log_mem_loop_enable : R/W; bitpos: [4]; default: 1;
+         *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
+         */
+        uint32_t log_mem_loop_enable:1;
+        uint32_t reserved_5:3;
+        /** log_core_ena : R/W; bitpos: [15:8]; default: 0;
+         *  enable core log
+         */
+        uint32_t log_core_ena:8;
+        /** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0;
+         *  enable dma_0 log
+         */
+        uint32_t log_dma_0_ena:8;
+        /** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0;
+         *  enable dma_1 log
+         */
+        uint32_t log_dma_1_ena:8;
+    };
+    uint32_t val;
+} mem_monitor_log_setting_reg_t;
+
+/** Type of log_setting1 register
+ *  log config register
+ */
+typedef union {
+    struct {
+        /** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0;
+         *  enable dma_2 log
+         */
+        uint32_t log_dma_2_ena:8;
+        /** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0;
+         *  enable dma_3 log
+         */
+        uint32_t log_dma_3_ena:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mem_monitor_log_setting1_reg_t;
+
+/** Type of log_check_data register
+ *  check data register
+ */
+typedef union {
+    struct {
+        /** log_check_data : R/W; bitpos: [31:0]; default: 0;
+         *  The special check data, when write this special data, it will trigger logging.
+         */
+        uint32_t log_check_data:32;
+    };
+    uint32_t val;
+} mem_monitor_log_check_data_reg_t;
+
+/** Type of log_data_mask register
+ *  check data mask register
+ */
+typedef union {
+    struct {
+        /** log_data_mask : R/W; bitpos: [3:0]; default: 0;
+         *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
+         *  mask second byte, and so on.
+         */
+        uint32_t log_data_mask:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} mem_monitor_log_data_mask_reg_t;
+
+/** Type of log_min register
+ *  log boundary register
+ */
+typedef union {
+    struct {
+        /** log_min : R/W; bitpos: [31:0]; default: 0;
+         *  the min address of log range
+         */
+        uint32_t log_min:32;
+    };
+    uint32_t val;
+} mem_monitor_log_min_reg_t;
+
+/** Type of log_max register
+ *  log boundary register
+ */
+typedef union {
+    struct {
+        /** log_max : R/W; bitpos: [31:0]; default: 0;
+         *  the max address of log range
+         */
+        uint32_t log_max:32;
+    };
+    uint32_t val;
+} mem_monitor_log_max_reg_t;
+
+/** Type of log_mem_start register
+ *  log message store range register
+ */
+typedef union {
+    struct {
+        /** log_mem_start : R/W; bitpos: [31:0]; default: 0;
+         *  the start address of writing logging message
+         */
+        uint32_t log_mem_start:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_start_reg_t;
+
+/** Type of log_mem_end register
+ *  log message store range register
+ */
+typedef union {
+    struct {
+        /** log_mem_end : R/W; bitpos: [31:0]; default: 0;
+         *  the end address of writing logging message
+         */
+        uint32_t log_mem_end:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_end_reg_t;
+
+/** Type of log_mem_current_addr register
+ *  current writing address.
+ */
+typedef union {
+    struct {
+        /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
+         *  means next writing address
+         */
+        uint32_t log_mem_current_addr:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_current_addr_reg_t;
+
+/** Type of log_mem_addr_update register
+ *  writing address update
+ */
+typedef union {
+    struct {
+        /** log_mem_addr_update : WT; bitpos: [0]; default: 0;
+         *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
+         *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
+         */
+        uint32_t log_mem_addr_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_addr_update_reg_t;
+
+/** Type of log_mem_full_flag register
+ *  full flag status register
+ */
+typedef union {
+    struct {
+        /** log_mem_full_flag : RO; bitpos: [0]; default: 0;
+         *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
+         */
+        uint32_t log_mem_full_flag:1;
+        /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
+         *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
+         */
+        uint32_t clr_log_mem_full_flag:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_full_flag_reg_t;
+
+
+/** Group: clk register */
+/** Type of clock_gate register
+ *  clock gate force on register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to force on the clk of mem_monitor register
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mem_monitor_clock_gate_reg_t;
+
+
+/** Group: version register */
+/** Type of date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36708896;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} mem_monitor_date_reg_t;
+
+
+typedef struct {
+    volatile mem_monitor_log_setting_reg_t log_setting;
+    volatile mem_monitor_log_setting1_reg_t log_setting1;
+    volatile mem_monitor_log_check_data_reg_t log_check_data;
+    volatile mem_monitor_log_data_mask_reg_t log_data_mask;
+    volatile mem_monitor_log_min_reg_t log_min;
+    volatile mem_monitor_log_max_reg_t log_max;
+    volatile mem_monitor_log_mem_start_reg_t log_mem_start;
+    volatile mem_monitor_log_mem_end_reg_t log_mem_end;
+    volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
+    volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
+    volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
+    volatile mem_monitor_clock_gate_reg_t clock_gate;
+    uint32_t reserved_030[243];
+    volatile mem_monitor_date_reg_t date;
+} mem_monitor_dev_t;
+
+extern mem_monitor_dev_t MEM_MONITOR;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_eco5_struct.h
new file mode 100644
index 0000000000..c94e6559ab
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_eco5_struct.h
@@ -0,0 +1,452 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: csi bridge regbank clock gating control register. */
+/** Type of clk_en register
+ *  csi bridge register mapping unit clock gating.
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  0: enable clock gating. 1: disable clock gating, clock always on.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_brg_clk_en_reg_t;
+
+
+/** Group: csi bridge control registers. */
+/** Type of csi_en register
+ *  csi bridge enable.
+ */
+typedef union {
+    struct {
+        /** csi_brg_en : R/W; bitpos: [0]; default: 0;
+         *  0: disable csi bridge. 1: enable csi bridge.
+         */
+        uint32_t csi_brg_en:1;
+        /** csi_brg_rst : R/W; bitpos: [1]; default: 0;
+         *  0: release csi bridge reset. 1: enable csi bridge reset.
+         */
+        uint32_t csi_brg_rst:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_brg_csi_en_reg_t;
+
+/** Type of buf_flow_ctl register
+ *  csi bridge buffer control.
+ */
+typedef union {
+    struct {
+        /** csi_buf_afull_thrd : R/W; bitpos: [13:0]; default: 2040;
+         *  buffer almost full threshold.
+         */
+        uint32_t csi_buf_afull_thrd:14;
+        uint32_t reserved_14:2;
+        /** csi_buf_depth : RO; bitpos: [29:16]; default: 0;
+         *  buffer data count.
+         */
+        uint32_t csi_buf_depth:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} csi_brg_buf_flow_ctl_reg_t;
+
+
+/** Group: csi bridge dma control registers. */
+/** Type of dma_req_cfg register
+ *  dma request configuration.
+ */
+typedef union {
+    struct {
+        /** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
+         *  DMA burst length.
+         */
+        uint32_t dma_burst_len:12;
+        /** dma_cfg_upd_by_blk : R/W; bitpos: [12]; default: 0;
+         *  1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0:
+         *  updated by frame.
+         */
+        uint32_t dma_cfg_upd_by_blk:1;
+        uint32_t reserved_13:3;
+        /** dma_force_rd_status : R/W; bitpos: [16]; default: 0;
+         *  1: mask dma request when reading frame info. 0: disable mask.
+         */
+        uint32_t dma_force_rd_status:1;
+        /** csi_dma_flow_controller : R/W; bitpos: [17]; default: 1;
+         *  0: dma as flow controller. 1: csi_bridge as flow controller
+         */
+        uint32_t csi_dma_flow_controller:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} csi_brg_dma_req_cfg_reg_t;
+
+/** Type of dma_req_interval register
+ *  DMA interval configuration.
+ */
+typedef union {
+    struct {
+        /** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
+         *  16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle.
+         */
+        uint32_t dma_req_interval:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_brg_dma_req_interval_reg_t;
+
+/** Type of dmablk_size register
+ *  DMA block size configuration.
+ */
+typedef union {
+    struct {
+        /** dmablk_size : R/W; bitpos: [12:0]; default: 8191;
+         *  the number of reg_dma_burst_len in a block
+         */
+        uint32_t dmablk_size:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} csi_brg_dmablk_size_reg_t;
+
+
+/** Group: csi bridge frame format configuration registers. */
+/** Type of data_type_cfg register
+ *  pixel data type configuration.
+ */
+typedef union {
+    struct {
+        /** data_type_min : R/W; bitpos: [5:0]; default: 24;
+         *  the min value of data type used for pixel filter.
+         */
+        uint32_t data_type_min:6;
+        uint32_t reserved_6:2;
+        /** data_type_max : R/W; bitpos: [13:8]; default: 47;
+         *  the max value of data type used for pixel filter.
+         */
+        uint32_t data_type_max:6;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} csi_brg_data_type_cfg_reg_t;
+
+/** Type of frame_cfg register
+ *  frame configuration.
+ */
+typedef union {
+    struct {
+        /** vadr_num : R/W; bitpos: [11:0]; default: 480;
+         *  vadr of frame data.
+         */
+        uint32_t vadr_num:12;
+        /** hadr_num : R/W; bitpos: [23:12]; default: 480;
+         *  hadr of frame data.
+         */
+        uint32_t hadr_num:12;
+        /** has_hsync_e : R/W; bitpos: [24]; default: 1;
+         *  0: frame data doesn't contain hsync. 1: frame data contains hsync.
+         */
+        uint32_t has_hsync_e:1;
+        /** vadr_num_check : R/W; bitpos: [25]; default: 0;
+         *  0: disable vadr check. 1: enable vadr check.
+         */
+        uint32_t vadr_num_check:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} csi_brg_frame_cfg_reg_t;
+
+/** Type of endian_mode register
+ *  data endianness order configuration.
+ */
+typedef union {
+    struct {
+        /** byte_endian_order : R/W; bitpos: [0]; default: 0;
+         *  endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy)
+         *  when isp is bapassed.
+         */
+        uint32_t byte_endian_order:1;
+        /** bit_endian_order : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t bit_endian_order:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_brg_endian_mode_reg_t;
+
+
+/** Group: csi bridge interrupt registers. */
+/** Type of int_raw register
+ *  csi bridge interrupt raw.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt raw.
+         */
+        uint32_t vadr_num_gt_int_raw:1;
+        /** vadr_num_lt_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt raw.
+         */
+        uint32_t vadr_num_lt_int_raw:1;
+        /** discard_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt raw.
+         */
+        uint32_t discard_int_raw:1;
+        /** csi_buf_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt raw.
+         */
+        uint32_t csi_buf_overrun_int_raw:1;
+        /** csi_async_fifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt raw.
+         */
+        uint32_t csi_async_fifo_ovf_int_raw:1;
+        /** dma_cfg_has_updated_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt raw.
+         */
+        uint32_t dma_cfg_has_updated_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  csi bridge interrupt clr.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_real_int_clr : WT; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt clr.
+         */
+        uint32_t vadr_num_gt_real_int_clr:1;
+        /** vadr_num_lt_real_int_clr : WT; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt clr.
+         */
+        uint32_t vadr_num_lt_real_int_clr:1;
+        /** discard_int_clr : WT; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt clr.
+         */
+        uint32_t discard_int_clr:1;
+        /** csi_buf_overrun_int_clr : WT; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt clr.
+         */
+        uint32_t csi_buf_overrun_int_clr:1;
+        /** csi_async_fifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt clr.
+         */
+        uint32_t csi_async_fifo_ovf_int_clr:1;
+        /** dma_cfg_has_updated_int_clr : WT; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt clr.
+         */
+        uint32_t dma_cfg_has_updated_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_clr_reg_t;
+
+/** Type of int_st register
+ *  csi bridge interrupt st.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_st : RO; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt st.
+         */
+        uint32_t vadr_num_gt_int_st:1;
+        /** vadr_num_lt_int_st : RO; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt st.
+         */
+        uint32_t vadr_num_lt_int_st:1;
+        /** discard_int_st : RO; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt st.
+         */
+        uint32_t discard_int_st:1;
+        /** csi_buf_overrun_int_st : RO; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt st.
+         */
+        uint32_t csi_buf_overrun_int_st:1;
+        /** csi_async_fifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt st.
+         */
+        uint32_t csi_async_fifo_ovf_int_st:1;
+        /** dma_cfg_has_updated_int_st : RO; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt st.
+         */
+        uint32_t dma_cfg_has_updated_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_st_reg_t;
+
+/** Type of int_ena register
+ *  csi bridge interrupt enable.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_ena : R/W; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt enable.
+         */
+        uint32_t vadr_num_gt_int_ena:1;
+        /** vadr_num_lt_int_ena : R/W; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt enable.
+         */
+        uint32_t vadr_num_lt_int_ena:1;
+        /** discard_int_ena : R/W; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt enable.
+         */
+        uint32_t discard_int_ena:1;
+        /** csi_buf_overrun_int_ena : R/W; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt enable.
+         */
+        uint32_t csi_buf_overrun_int_ena:1;
+        /** csi_async_fifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt enable.
+         */
+        uint32_t csi_async_fifo_ovf_int_ena:1;
+        /** dma_cfg_has_updated_int_ena : R/W; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt enable.
+         */
+        uint32_t dma_cfg_has_updated_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_ena_reg_t;
+
+
+/** Group: csi-host control registers from csi bridge regbank. */
+/** Type of host_ctrl register
+ *  csi host control by csi bridge.
+ */
+typedef union {
+    struct {
+        /** csi_enableclk : R/W; bitpos: [0]; default: 1;
+         *  enable clock lane module of csi phy.
+         */
+        uint32_t csi_enableclk:1;
+        /** csi_cfg_clk_en : R/W; bitpos: [1]; default: 1;
+         *  enable cfg_clk of csi host module.
+         */
+        uint32_t csi_cfg_clk_en:1;
+        /** loopbk_test_en : R/W; bitpos: [2]; default: 0;
+         *  for phy test by loopback dsi phy to csi phy.
+         */
+        uint32_t loopbk_test_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} csi_brg_host_ctrl_reg_t;
+
+
+/** Group: csi host color mode control registers. */
+/** Type of host_cm_ctrl register
+ *  CSI HOST color mode convert configuration.
+ */
+typedef union {
+    struct {
+        /** csi_host_cm_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to enable cm output
+         */
+        uint32_t csi_host_cm_en:1;
+        /** csi_host_cm_bypass : R/W; bitpos: [1]; default: 1;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_bypass:1;
+        /** csi_host_cm_rx : R/W; bitpos: [3:2]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_rx:2;
+        /** csi_host_cm_rx_rgb_format : R/W; bitpos: [6:4]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_rx_rgb_format:3;
+        /** csi_host_cm_rx_yuv422_format : R/W; bitpos: [8:7]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_rx_yuv422_format:2;
+        /** csi_host_cm_tx : R/W; bitpos: [10:9]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_tx:2;
+        /** csi_host_cm_lane_num : R/W; bitpos: [11]; default: 1;
+         *  Configures lane number that csi used, valid only rgb888 to rgb888. 0: 1-lane, 1:
+         *  2-lane
+         */
+        uint32_t csi_host_cm_lane_num:1;
+        /** csi_host_cm_16bit_swap : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to swap idi32 high and low 16-bit
+         */
+        uint32_t csi_host_cm_16bit_swap:1;
+        /** csi_host_cm_8bit_swap : R/W; bitpos: [13]; default: 0;
+         *  Configures whether to swap idi32 high and low 8-bit
+         */
+        uint32_t csi_host_cm_8bit_swap:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} csi_brg_host_cm_ctrl_reg_t;
+
+/** Type of host_size_ctrl register
+ *  CSI HOST color mode convert configuration.
+ */
+typedef union {
+    struct {
+        /** csi_host_cm_vnum : R/W; bitpos: [11:0]; default: 0;
+         *  Configures idi32 image size in y-direction, row_num - 1, valid only when
+         *  yuv422_to_yuv420_en = 1
+         */
+        uint32_t csi_host_cm_vnum:12;
+        /** csi_host_cm_hnum : R/W; bitpos: [23:12]; default: 0;
+         *  Configures idi32 image size in x-direction, line_pix_num*bits_per_pix/32 - 1, valid
+         *  only when yuv422_to_yuv420_en = 1
+         */
+        uint32_t csi_host_cm_hnum:12;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} csi_brg_host_size_ctrl_reg_t;
+
+
+typedef struct {
+    volatile csi_brg_clk_en_reg_t clk_en;
+    volatile csi_brg_csi_en_reg_t csi_en;
+    volatile csi_brg_dma_req_cfg_reg_t dma_req_cfg;
+    volatile csi_brg_buf_flow_ctl_reg_t buf_flow_ctl;
+    volatile csi_brg_data_type_cfg_reg_t data_type_cfg;
+    volatile csi_brg_frame_cfg_reg_t frame_cfg;
+    volatile csi_brg_endian_mode_reg_t endian_mode;
+    volatile csi_brg_int_raw_reg_t int_raw;
+    volatile csi_brg_int_clr_reg_t int_clr;
+    volatile csi_brg_int_st_reg_t int_st;
+    volatile csi_brg_int_ena_reg_t int_ena;
+    volatile csi_brg_dma_req_interval_reg_t dma_req_interval;
+    volatile csi_brg_dmablk_size_reg_t dmablk_size;
+    uint32_t reserved_034[3];
+    volatile csi_brg_host_ctrl_reg_t host_ctrl;
+    uint32_t reserved_044;
+    volatile csi_brg_host_cm_ctrl_reg_t host_cm_ctrl;
+    volatile csi_brg_host_size_ctrl_reg_t host_size_ctrl;
+} csi_brg_dev_t;
+
+extern csi_brg_dev_t MIPI_CSI_BRIDGE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(csi_brg_dev_t) == 0x50, "Invalid size of csi_brg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_reg.h
new file mode 100644
index 0000000000..370f31c723
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_reg.h
@@ -0,0 +1,500 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CSI_BRIG_CLK_EN_REG register
+ *  csi bridge register mapping unit clock gating.
+ */
+#define CSI_BRIG_CLK_EN_REG (DR_REG_CSI_BRIG_BASE + 0x0)
+/** CSI_BRIG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  0: enable clock gating. 1: disable clock gating, clock always on.
+ */
+#define CSI_BRIG_CLK_EN    (BIT(0))
+#define CSI_BRIG_CLK_EN_M  (CSI_BRIG_CLK_EN_V << CSI_BRIG_CLK_EN_S)
+#define CSI_BRIG_CLK_EN_V  0x00000001U
+#define CSI_BRIG_CLK_EN_S  0
+
+/** CSI_BRIG_CSI_EN_REG register
+ *  csi bridge enable.
+ */
+#define CSI_BRIG_CSI_EN_REG (DR_REG_CSI_BRIG_BASE + 0x4)
+/** CSI_BRIG_CSI_BRIG_EN : R/W; bitpos: [0]; default: 0;
+ *  0: disable csi bridge. 1: enable csi bridge.
+ */
+#define CSI_BRIG_CSI_BRIG_EN    (BIT(0))
+#define CSI_BRIG_CSI_BRIG_EN_M  (CSI_BRIG_CSI_BRIG_EN_V << CSI_BRIG_CSI_BRIG_EN_S)
+#define CSI_BRIG_CSI_BRIG_EN_V  0x00000001U
+#define CSI_BRIG_CSI_BRIG_EN_S  0
+/** CSI_BRIG_CSI_BRIG_RST : R/W; bitpos: [1]; default: 0;
+ *  0: release csi bridge reset. 1: enable csi bridge reset.
+ */
+#define CSI_BRIG_CSI_BRIG_RST    (BIT(1))
+#define CSI_BRIG_CSI_BRIG_RST_M  (CSI_BRIG_CSI_BRIG_RST_V << CSI_BRIG_CSI_BRIG_RST_S)
+#define CSI_BRIG_CSI_BRIG_RST_V  0x00000001U
+#define CSI_BRIG_CSI_BRIG_RST_S  1
+
+/** CSI_BRIG_DMA_REQ_CFG_REG register
+ *  dma request configuration.
+ */
+#define CSI_BRIG_DMA_REQ_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x8)
+/** CSI_BRIG_DMA_BURST_LEN : R/W; bitpos: [11:0]; default: 128;
+ *  DMA burst length.
+ */
+#define CSI_BRIG_DMA_BURST_LEN    0x00000FFFU
+#define CSI_BRIG_DMA_BURST_LEN_M  (CSI_BRIG_DMA_BURST_LEN_V << CSI_BRIG_DMA_BURST_LEN_S)
+#define CSI_BRIG_DMA_BURST_LEN_V  0x00000FFFU
+#define CSI_BRIG_DMA_BURST_LEN_S  0
+/** CSI_BRIG_DMA_CFG_UPD_BY_BLK : R/W; bitpos: [12]; default: 0;
+ *  1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0:
+ *  updated by frame.
+ */
+#define CSI_BRIG_DMA_CFG_UPD_BY_BLK    (BIT(12))
+#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_M  (CSI_BRIG_DMA_CFG_UPD_BY_BLK_V << CSI_BRIG_DMA_CFG_UPD_BY_BLK_S)
+#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_V  0x00000001U
+#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_S  12
+/** CSI_BRIG_DMA_FORCE_RD_STATUS : R/W; bitpos: [16]; default: 0;
+ *  1: mask dma request when reading frame info. 0: disable mask.
+ */
+#define CSI_BRIG_DMA_FORCE_RD_STATUS    (BIT(16))
+#define CSI_BRIG_DMA_FORCE_RD_STATUS_M  (CSI_BRIG_DMA_FORCE_RD_STATUS_V << CSI_BRIG_DMA_FORCE_RD_STATUS_S)
+#define CSI_BRIG_DMA_FORCE_RD_STATUS_V  0x00000001U
+#define CSI_BRIG_DMA_FORCE_RD_STATUS_S  16
+/** CSI_BRIG_CSI_DMA_FLOW_CONTROLLER : R/W; bitpos: [17]; default: 1;
+ *  0: dma as flow controller. 1: csi_bridge as flow controller
+ */
+#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER    (BIT(17))
+#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_M  (CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_V << CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_S)
+#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_V  0x00000001U
+#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_S  17
+
+/** CSI_BRIG_BUF_FLOW_CTL_REG register
+ *  csi bridge buffer control.
+ */
+#define CSI_BRIG_BUF_FLOW_CTL_REG (DR_REG_CSI_BRIG_BASE + 0xc)
+/** CSI_BRIG_CSI_BUF_AFULL_THRD : R/W; bitpos: [13:0]; default: 2040;
+ *  buffer almost full threshold.
+ */
+#define CSI_BRIG_CSI_BUF_AFULL_THRD    0x00003FFFU
+#define CSI_BRIG_CSI_BUF_AFULL_THRD_M  (CSI_BRIG_CSI_BUF_AFULL_THRD_V << CSI_BRIG_CSI_BUF_AFULL_THRD_S)
+#define CSI_BRIG_CSI_BUF_AFULL_THRD_V  0x00003FFFU
+#define CSI_BRIG_CSI_BUF_AFULL_THRD_S  0
+/** CSI_BRIG_CSI_BUF_DEPTH : RO; bitpos: [29:16]; default: 0;
+ *  buffer data count.
+ */
+#define CSI_BRIG_CSI_BUF_DEPTH    0x00003FFFU
+#define CSI_BRIG_CSI_BUF_DEPTH_M  (CSI_BRIG_CSI_BUF_DEPTH_V << CSI_BRIG_CSI_BUF_DEPTH_S)
+#define CSI_BRIG_CSI_BUF_DEPTH_V  0x00003FFFU
+#define CSI_BRIG_CSI_BUF_DEPTH_S  16
+
+/** CSI_BRIG_DATA_TYPE_CFG_REG register
+ *  pixel data type configuration.
+ */
+#define CSI_BRIG_DATA_TYPE_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x10)
+/** CSI_BRIG_DATA_TYPE_MIN : R/W; bitpos: [5:0]; default: 24;
+ *  the min value of data type used for pixel filter.
+ */
+#define CSI_BRIG_DATA_TYPE_MIN    0x0000003FU
+#define CSI_BRIG_DATA_TYPE_MIN_M  (CSI_BRIG_DATA_TYPE_MIN_V << CSI_BRIG_DATA_TYPE_MIN_S)
+#define CSI_BRIG_DATA_TYPE_MIN_V  0x0000003FU
+#define CSI_BRIG_DATA_TYPE_MIN_S  0
+/** CSI_BRIG_DATA_TYPE_MAX : R/W; bitpos: [13:8]; default: 47;
+ *  the max value of data type used for pixel filter.
+ */
+#define CSI_BRIG_DATA_TYPE_MAX    0x0000003FU
+#define CSI_BRIG_DATA_TYPE_MAX_M  (CSI_BRIG_DATA_TYPE_MAX_V << CSI_BRIG_DATA_TYPE_MAX_S)
+#define CSI_BRIG_DATA_TYPE_MAX_V  0x0000003FU
+#define CSI_BRIG_DATA_TYPE_MAX_S  8
+
+/** CSI_BRIG_FRAME_CFG_REG register
+ *  frame configuration.
+ */
+#define CSI_BRIG_FRAME_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x14)
+/** CSI_BRIG_VADR_NUM : R/W; bitpos: [11:0]; default: 480;
+ *  vadr of frame data.
+ */
+#define CSI_BRIG_VADR_NUM    0x00000FFFU
+#define CSI_BRIG_VADR_NUM_M  (CSI_BRIG_VADR_NUM_V << CSI_BRIG_VADR_NUM_S)
+#define CSI_BRIG_VADR_NUM_V  0x00000FFFU
+#define CSI_BRIG_VADR_NUM_S  0
+/** CSI_BRIG_HADR_NUM : R/W; bitpos: [23:12]; default: 480;
+ *  hadr of frame data.
+ */
+#define CSI_BRIG_HADR_NUM    0x00000FFFU
+#define CSI_BRIG_HADR_NUM_M  (CSI_BRIG_HADR_NUM_V << CSI_BRIG_HADR_NUM_S)
+#define CSI_BRIG_HADR_NUM_V  0x00000FFFU
+#define CSI_BRIG_HADR_NUM_S  12
+/** CSI_BRIG_HAS_HSYNC_E : R/W; bitpos: [24]; default: 1;
+ *  0: frame data doesn't contain hsync. 1: frame data contains hsync.
+ */
+#define CSI_BRIG_HAS_HSYNC_E    (BIT(24))
+#define CSI_BRIG_HAS_HSYNC_E_M  (CSI_BRIG_HAS_HSYNC_E_V << CSI_BRIG_HAS_HSYNC_E_S)
+#define CSI_BRIG_HAS_HSYNC_E_V  0x00000001U
+#define CSI_BRIG_HAS_HSYNC_E_S  24
+/** CSI_BRIG_VADR_NUM_CHECK : R/W; bitpos: [25]; default: 0;
+ *  0: disable vadr check. 1: enable vadr check.
+ */
+#define CSI_BRIG_VADR_NUM_CHECK    (BIT(25))
+#define CSI_BRIG_VADR_NUM_CHECK_M  (CSI_BRIG_VADR_NUM_CHECK_V << CSI_BRIG_VADR_NUM_CHECK_S)
+#define CSI_BRIG_VADR_NUM_CHECK_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_CHECK_S  25
+
+/** CSI_BRIG_ENDIAN_MODE_REG register
+ *  data endianness order configuration.
+ */
+#define CSI_BRIG_ENDIAN_MODE_REG (DR_REG_CSI_BRIG_BASE + 0x18)
+/** CSI_BRIG_BYTE_ENDIAN_ORDER : R/W; bitpos: [0]; default: 0;
+ *  endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy)
+ *  when isp is bapassed.
+ */
+#define CSI_BRIG_BYTE_ENDIAN_ORDER    (BIT(0))
+#define CSI_BRIG_BYTE_ENDIAN_ORDER_M  (CSI_BRIG_BYTE_ENDIAN_ORDER_V << CSI_BRIG_BYTE_ENDIAN_ORDER_S)
+#define CSI_BRIG_BYTE_ENDIAN_ORDER_V  0x00000001U
+#define CSI_BRIG_BYTE_ENDIAN_ORDER_S  0
+/** CSI_BRIG_BIT_ENDIAN_ORDER : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define CSI_BRIG_BIT_ENDIAN_ORDER    (BIT(1))
+#define CSI_BRIG_BIT_ENDIAN_ORDER_M  (CSI_BRIG_BIT_ENDIAN_ORDER_V << CSI_BRIG_BIT_ENDIAN_ORDER_S)
+#define CSI_BRIG_BIT_ENDIAN_ORDER_V  0x00000001U
+#define CSI_BRIG_BIT_ENDIAN_ORDER_S  1
+
+/** CSI_BRIG_INT_RAW_REG register
+ *  csi bridge interrupt raw.
+ */
+#define CSI_BRIG_INT_RAW_REG (DR_REG_CSI_BRIG_BASE + 0x1c)
+/** CSI_BRIG_VADR_NUM_GT_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  reg_vadr_num is greater than real interrupt raw.
+ */
+#define CSI_BRIG_VADR_NUM_GT_INT_RAW    (BIT(0))
+#define CSI_BRIG_VADR_NUM_GT_INT_RAW_M  (CSI_BRIG_VADR_NUM_GT_INT_RAW_V << CSI_BRIG_VADR_NUM_GT_INT_RAW_S)
+#define CSI_BRIG_VADR_NUM_GT_INT_RAW_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_GT_INT_RAW_S  0
+/** CSI_BRIG_VADR_NUM_LT_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  reg_vadr_num is less than real interrupt raw.
+ */
+#define CSI_BRIG_VADR_NUM_LT_INT_RAW    (BIT(1))
+#define CSI_BRIG_VADR_NUM_LT_INT_RAW_M  (CSI_BRIG_VADR_NUM_LT_INT_RAW_V << CSI_BRIG_VADR_NUM_LT_INT_RAW_S)
+#define CSI_BRIG_VADR_NUM_LT_INT_RAW_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_LT_INT_RAW_S  1
+/** CSI_BRIG_DISCARD_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  an incomplete frame of data was sent interrupt raw.
+ */
+#define CSI_BRIG_DISCARD_INT_RAW    (BIT(2))
+#define CSI_BRIG_DISCARD_INT_RAW_M  (CSI_BRIG_DISCARD_INT_RAW_V << CSI_BRIG_DISCARD_INT_RAW_S)
+#define CSI_BRIG_DISCARD_INT_RAW_V  0x00000001U
+#define CSI_BRIG_DISCARD_INT_RAW_S  2
+/** CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  buffer overrun interrupt raw.
+ */
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW    (BIT(3))
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_M  (CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_S)
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_V  0x00000001U
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_S  3
+/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  buffer overflow interrupt raw.
+ */
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW    (BIT(4))
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_M  (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_S)
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_V  0x00000001U
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_S  4
+/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  dma configuration update complete interrupt raw.
+ */
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW    (BIT(5))
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_M  (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_S)
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_V  0x00000001U
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_S  5
+
+/** CSI_BRIG_INT_CLR_REG register
+ *  csi bridge interrupt clr.
+ */
+#define CSI_BRIG_INT_CLR_REG (DR_REG_CSI_BRIG_BASE + 0x20)
+/** CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  reg_vadr_num is greater than real interrupt clr.
+ */
+#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR    (BIT(0))
+#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_M  (CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_V << CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_S)
+#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_S  0
+/** CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  reg_vadr_num is less than real interrupt clr.
+ */
+#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR    (BIT(1))
+#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_M  (CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_V << CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_S)
+#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_S  1
+/** CSI_BRIG_DISCARD_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  an incomplete frame of data was sent interrupt clr.
+ */
+#define CSI_BRIG_DISCARD_INT_CLR    (BIT(2))
+#define CSI_BRIG_DISCARD_INT_CLR_M  (CSI_BRIG_DISCARD_INT_CLR_V << CSI_BRIG_DISCARD_INT_CLR_S)
+#define CSI_BRIG_DISCARD_INT_CLR_V  0x00000001U
+#define CSI_BRIG_DISCARD_INT_CLR_S  2
+/** CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  buffer overrun interrupt clr.
+ */
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR    (BIT(3))
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_M  (CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_S)
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_V  0x00000001U
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_S  3
+/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  buffer overflow interrupt clr.
+ */
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR    (BIT(4))
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_M  (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_S)
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_V  0x00000001U
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_S  4
+/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  dma configuration update complete interrupt clr.
+ */
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR    (BIT(5))
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_M  (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_S)
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_V  0x00000001U
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_S  5
+
+/** CSI_BRIG_INT_ST_REG register
+ *  csi bridge interrupt st.
+ */
+#define CSI_BRIG_INT_ST_REG (DR_REG_CSI_BRIG_BASE + 0x24)
+/** CSI_BRIG_VADR_NUM_GT_INT_ST : RO; bitpos: [0]; default: 0;
+ *  reg_vadr_num is greater than real interrupt st.
+ */
+#define CSI_BRIG_VADR_NUM_GT_INT_ST    (BIT(0))
+#define CSI_BRIG_VADR_NUM_GT_INT_ST_M  (CSI_BRIG_VADR_NUM_GT_INT_ST_V << CSI_BRIG_VADR_NUM_GT_INT_ST_S)
+#define CSI_BRIG_VADR_NUM_GT_INT_ST_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_GT_INT_ST_S  0
+/** CSI_BRIG_VADR_NUM_LT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  reg_vadr_num is less than real interrupt st.
+ */
+#define CSI_BRIG_VADR_NUM_LT_INT_ST    (BIT(1))
+#define CSI_BRIG_VADR_NUM_LT_INT_ST_M  (CSI_BRIG_VADR_NUM_LT_INT_ST_V << CSI_BRIG_VADR_NUM_LT_INT_ST_S)
+#define CSI_BRIG_VADR_NUM_LT_INT_ST_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_LT_INT_ST_S  1
+/** CSI_BRIG_DISCARD_INT_ST : RO; bitpos: [2]; default: 0;
+ *  an incomplete frame of data was sent interrupt st.
+ */
+#define CSI_BRIG_DISCARD_INT_ST    (BIT(2))
+#define CSI_BRIG_DISCARD_INT_ST_M  (CSI_BRIG_DISCARD_INT_ST_V << CSI_BRIG_DISCARD_INT_ST_S)
+#define CSI_BRIG_DISCARD_INT_ST_V  0x00000001U
+#define CSI_BRIG_DISCARD_INT_ST_S  2
+/** CSI_BRIG_CSI_BUF_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
+ *  buffer overrun interrupt st.
+ */
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST    (BIT(3))
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_M  (CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_S)
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_V  0x00000001U
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_S  3
+/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  buffer overflow interrupt st.
+ */
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST    (BIT(4))
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_M  (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_S)
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_V  0x00000001U
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_S  4
+/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST : RO; bitpos: [5]; default: 0;
+ *  dma configuration update complete interrupt st.
+ */
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST    (BIT(5))
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_M  (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_S)
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_V  0x00000001U
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_S  5
+
+/** CSI_BRIG_INT_ENA_REG register
+ *  csi bridge interrupt enable.
+ */
+#define CSI_BRIG_INT_ENA_REG (DR_REG_CSI_BRIG_BASE + 0x28)
+/** CSI_BRIG_VADR_NUM_GT_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  reg_vadr_num is greater than real interrupt enable.
+ */
+#define CSI_BRIG_VADR_NUM_GT_INT_ENA    (BIT(0))
+#define CSI_BRIG_VADR_NUM_GT_INT_ENA_M  (CSI_BRIG_VADR_NUM_GT_INT_ENA_V << CSI_BRIG_VADR_NUM_GT_INT_ENA_S)
+#define CSI_BRIG_VADR_NUM_GT_INT_ENA_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_GT_INT_ENA_S  0
+/** CSI_BRIG_VADR_NUM_LT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  reg_vadr_num is less than real interrupt enable.
+ */
+#define CSI_BRIG_VADR_NUM_LT_INT_ENA    (BIT(1))
+#define CSI_BRIG_VADR_NUM_LT_INT_ENA_M  (CSI_BRIG_VADR_NUM_LT_INT_ENA_V << CSI_BRIG_VADR_NUM_LT_INT_ENA_S)
+#define CSI_BRIG_VADR_NUM_LT_INT_ENA_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_LT_INT_ENA_S  1
+/** CSI_BRIG_DISCARD_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  an incomplete frame of data was sent interrupt enable.
+ */
+#define CSI_BRIG_DISCARD_INT_ENA    (BIT(2))
+#define CSI_BRIG_DISCARD_INT_ENA_M  (CSI_BRIG_DISCARD_INT_ENA_V << CSI_BRIG_DISCARD_INT_ENA_S)
+#define CSI_BRIG_DISCARD_INT_ENA_V  0x00000001U
+#define CSI_BRIG_DISCARD_INT_ENA_S  2
+/** CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  buffer overrun interrupt enable.
+ */
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA    (BIT(3))
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_M  (CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_S)
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_V  0x00000001U
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_S  3
+/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  buffer overflow interrupt enable.
+ */
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA    (BIT(4))
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_M  (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_S)
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_V  0x00000001U
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_S  4
+/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  dma configuration update complete interrupt enable.
+ */
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA    (BIT(5))
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_M  (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_S)
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_V  0x00000001U
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_S  5
+
+/** CSI_BRIG_DMA_REQ_INTERVAL_REG register
+ *  DMA interval configuration.
+ */
+#define CSI_BRIG_DMA_REQ_INTERVAL_REG (DR_REG_CSI_BRIG_BASE + 0x2c)
+/** CSI_BRIG_DMA_REQ_INTERVAL : R/W; bitpos: [15:0]; default: 1;
+ *  16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle.
+ */
+#define CSI_BRIG_DMA_REQ_INTERVAL    0x0000FFFFU
+#define CSI_BRIG_DMA_REQ_INTERVAL_M  (CSI_BRIG_DMA_REQ_INTERVAL_V << CSI_BRIG_DMA_REQ_INTERVAL_S)
+#define CSI_BRIG_DMA_REQ_INTERVAL_V  0x0000FFFFU
+#define CSI_BRIG_DMA_REQ_INTERVAL_S  0
+
+/** CSI_BRIG_DMABLK_SIZE_REG register
+ *  DMA block size configuration.
+ */
+#define CSI_BRIG_DMABLK_SIZE_REG (DR_REG_CSI_BRIG_BASE + 0x30)
+/** CSI_BRIG_DMABLK_SIZE : R/W; bitpos: [12:0]; default: 8191;
+ *  the number of reg_dma_burst_len in a block
+ */
+#define CSI_BRIG_DMABLK_SIZE    0x00001FFFU
+#define CSI_BRIG_DMABLK_SIZE_M  (CSI_BRIG_DMABLK_SIZE_V << CSI_BRIG_DMABLK_SIZE_S)
+#define CSI_BRIG_DMABLK_SIZE_V  0x00001FFFU
+#define CSI_BRIG_DMABLK_SIZE_S  0
+
+/** CSI_BRIG_HOST_CTRL_REG register
+ *  csi host control by csi bridge.
+ */
+#define CSI_BRIG_HOST_CTRL_REG (DR_REG_CSI_BRIG_BASE + 0x40)
+/** CSI_BRIG_CSI_ENABLECLK : R/W; bitpos: [0]; default: 1;
+ *  enable clock lane module of csi phy.
+ */
+#define CSI_BRIG_CSI_ENABLECLK    (BIT(0))
+#define CSI_BRIG_CSI_ENABLECLK_M  (CSI_BRIG_CSI_ENABLECLK_V << CSI_BRIG_CSI_ENABLECLK_S)
+#define CSI_BRIG_CSI_ENABLECLK_V  0x00000001U
+#define CSI_BRIG_CSI_ENABLECLK_S  0
+/** CSI_BRIG_CSI_CFG_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  enable cfg_clk of csi host module.
+ */
+#define CSI_BRIG_CSI_CFG_CLK_EN    (BIT(1))
+#define CSI_BRIG_CSI_CFG_CLK_EN_M  (CSI_BRIG_CSI_CFG_CLK_EN_V << CSI_BRIG_CSI_CFG_CLK_EN_S)
+#define CSI_BRIG_CSI_CFG_CLK_EN_V  0x00000001U
+#define CSI_BRIG_CSI_CFG_CLK_EN_S  1
+/** CSI_BRIG_LOOPBK_TEST_EN : R/W; bitpos: [2]; default: 0;
+ *  for phy test by loopback dsi phy to csi phy.
+ */
+#define CSI_BRIG_LOOPBK_TEST_EN    (BIT(2))
+#define CSI_BRIG_LOOPBK_TEST_EN_M  (CSI_BRIG_LOOPBK_TEST_EN_V << CSI_BRIG_LOOPBK_TEST_EN_S)
+#define CSI_BRIG_LOOPBK_TEST_EN_V  0x00000001U
+#define CSI_BRIG_LOOPBK_TEST_EN_S  2
+
+/** CSI_BRIG_HOST_CM_CTRL_REG register
+ *  CSI HOST color mode convert configuration.
+ */
+#define CSI_BRIG_HOST_CM_CTRL_REG (DR_REG_CSI_BRIG_BASE + 0x48)
+/** CSI_BRIG_CSI_HOST_CM_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to enable cm output
+ */
+#define CSI_BRIG_CSI_HOST_CM_EN    (BIT(0))
+#define CSI_BRIG_CSI_HOST_CM_EN_M  (CSI_BRIG_CSI_HOST_CM_EN_V << CSI_BRIG_CSI_HOST_CM_EN_S)
+#define CSI_BRIG_CSI_HOST_CM_EN_V  0x00000001U
+#define CSI_BRIG_CSI_HOST_CM_EN_S  0
+/** CSI_BRIG_CSI_HOST_CM_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  Configures whether to bypass cm
+ */
+#define CSI_BRIG_CSI_HOST_CM_BYPASS    (BIT(1))
+#define CSI_BRIG_CSI_HOST_CM_BYPASS_M  (CSI_BRIG_CSI_HOST_CM_BYPASS_V << CSI_BRIG_CSI_HOST_CM_BYPASS_S)
+#define CSI_BRIG_CSI_HOST_CM_BYPASS_V  0x00000001U
+#define CSI_BRIG_CSI_HOST_CM_BYPASS_S  1
+/** CSI_BRIG_CSI_HOST_CM_RX : R/W; bitpos: [3:2]; default: 0;
+ *  Configures whether to bypass cm
+ */
+#define CSI_BRIG_CSI_HOST_CM_RX    0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_RX_M  (CSI_BRIG_CSI_HOST_CM_RX_V << CSI_BRIG_CSI_HOST_CM_RX_S)
+#define CSI_BRIG_CSI_HOST_CM_RX_V  0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_RX_S  2
+/** CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT : R/W; bitpos: [6:4]; default: 0;
+ *  Configures whether to bypass cm
+ */
+#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT    0x00000007U
+#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_M  (CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_V << CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_S)
+#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_V  0x00000007U
+#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_S  4
+/** CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT : R/W; bitpos: [8:7]; default: 0;
+ *  Configures whether to bypass cm
+ */
+#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT    0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_M  (CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_V << CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_S)
+#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_V  0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_S  7
+/** CSI_BRIG_CSI_HOST_CM_TX : R/W; bitpos: [10:9]; default: 0;
+ *  Configures whether to bypass cm
+ */
+#define CSI_BRIG_CSI_HOST_CM_TX    0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_TX_M  (CSI_BRIG_CSI_HOST_CM_TX_V << CSI_BRIG_CSI_HOST_CM_TX_S)
+#define CSI_BRIG_CSI_HOST_CM_TX_V  0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_TX_S  9
+/** CSI_BRIG_CSI_HOST_CM_LANE_NUM : R/W; bitpos: [11]; default: 1;
+ *  Configures lane number that csi used, valid only rgb888 to rgb888. 0: 1-lane, 1:
+ *  2-lane
+ */
+#define CSI_BRIG_CSI_HOST_CM_LANE_NUM    (BIT(11))
+#define CSI_BRIG_CSI_HOST_CM_LANE_NUM_M  (CSI_BRIG_CSI_HOST_CM_LANE_NUM_V << CSI_BRIG_CSI_HOST_CM_LANE_NUM_S)
+#define CSI_BRIG_CSI_HOST_CM_LANE_NUM_V  0x00000001U
+#define CSI_BRIG_CSI_HOST_CM_LANE_NUM_S  11
+/** CSI_BRIG_CSI_HOST_CM_16BIT_SWAP : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to swap idi32 high and low 16-bit
+ */
+#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP    (BIT(12))
+#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_M  (CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_V << CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_S)
+#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_V  0x00000001U
+#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_S  12
+/** CSI_BRIG_CSI_HOST_CM_8BIT_SWAP : R/W; bitpos: [13]; default: 0;
+ *  Configures whether to swap idi32 high and low 8-bit
+ */
+#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP    (BIT(13))
+#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_M  (CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_V << CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_S)
+#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_V  0x00000001U
+#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_S  13
+
+/** CSI_BRIG_HOST_SIZE_CTRL_REG register
+ *  CSI HOST color mode convert configuration.
+ */
+#define CSI_BRIG_HOST_SIZE_CTRL_REG (DR_REG_CSI_BRIG_BASE + 0x4c)
+/** CSI_BRIG_CSI_HOST_CM_VNUM : R/W; bitpos: [11:0]; default: 0;
+ *  Configures idi32 image size in y-direction, row_num - 1, valid only when
+ *  yuv422_to_yuv420_en = 1
+ */
+#define CSI_BRIG_CSI_HOST_CM_VNUM    0x00000FFFU
+#define CSI_BRIG_CSI_HOST_CM_VNUM_M  (CSI_BRIG_CSI_HOST_CM_VNUM_V << CSI_BRIG_CSI_HOST_CM_VNUM_S)
+#define CSI_BRIG_CSI_HOST_CM_VNUM_V  0x00000FFFU
+#define CSI_BRIG_CSI_HOST_CM_VNUM_S  0
+/** CSI_BRIG_CSI_HOST_CM_HNUM : R/W; bitpos: [23:12]; default: 0;
+ *  Configures idi32 image size in x-direction, line_pix_num*bits_per_pix/32 - 1, valid
+ *  only when yuv422_to_yuv420_en = 1
+ */
+#define CSI_BRIG_CSI_HOST_CM_HNUM    0x00000FFFU
+#define CSI_BRIG_CSI_HOST_CM_HNUM_M  (CSI_BRIG_CSI_HOST_CM_HNUM_V << CSI_BRIG_CSI_HOST_CM_HNUM_S)
+#define CSI_BRIG_CSI_HOST_CM_HNUM_V  0x00000FFFU
+#define CSI_BRIG_CSI_HOST_CM_HNUM_S  12
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h
new file mode 100644
index 0000000000..20b393afdb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h
@@ -0,0 +1,372 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: csi bridge regbank clock gating control register. */
+/** Type of clk_en register
+ *  csi bridge register mapping unit clock gating.
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  0: enable clock gating. 1: disable clock gating, clock always on.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_brg_clk_en_reg_t;
+
+
+/** Group: csi bridge control registers. */
+/** Type of csi_en register
+ *  csi bridge enable.
+ */
+typedef union {
+    struct {
+        /** csi_brg_en : R/W; bitpos: [0]; default: 0;
+         *  0: disable csi bridge. 1: enable csi bridge.
+         */
+        uint32_t csi_brg_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_brg_csi_en_reg_t;
+
+/** Type of buf_flow_ctl register
+ *  csi bridge buffer control.
+ */
+typedef union {
+    struct {
+        /** csi_buf_afull_thrd : R/W; bitpos: [13:0]; default: 2040;
+         *  buffer almost full threshold.
+         */
+        uint32_t csi_buf_afull_thrd:14;
+        uint32_t reserved_14:2;
+        /** csi_buf_depth : RO; bitpos: [29:16]; default: 0;
+         *  buffer data count.
+         */
+        uint32_t csi_buf_depth:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} csi_brg_buf_flow_ctl_reg_t;
+
+
+/** Group: csi bridge dma control registers. */
+/** Type of dma_req_cfg register
+ *  dma request configuration.
+ */
+typedef union {
+    struct {
+        /** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
+         *  DMA burst length.
+         */
+        uint32_t dma_burst_len:12;
+        /** dma_cfg_upd_by_blk : R/W; bitpos: [12]; default: 0;
+         *  1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0:
+         *  updated by frame.
+         */
+        uint32_t dma_cfg_upd_by_blk:1;
+        uint32_t reserved_13:3;
+        /** dma_force_rd_status : R/W; bitpos: [16]; default: 0;
+         *  1: mask dma request when reading frame info. 0: disable mask.
+         */
+        uint32_t dma_force_rd_status:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} csi_brg_dma_req_cfg_reg_t;
+
+/** Type of dma_req_interval register
+ *  DMA interval configuration.
+ */
+typedef union {
+    struct {
+        /** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
+         *  16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle.
+         */
+        uint32_t dma_req_interval:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_brg_dma_req_interval_reg_t;
+
+/** Type of dmablk_size register
+ *  DMA block size configuration.
+ */
+typedef union {
+    struct {
+        /** dmablk_size : R/W; bitpos: [12:0]; default: 8191;
+         *  the number of reg_dma_burst_len in a block
+         */
+        uint32_t dmablk_size:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} csi_brg_dmablk_size_reg_t;
+
+
+/** Group: csi bridge frame format configuration registers. */
+/** Type of data_type_cfg register
+ *  pixel data type configuration.
+ */
+typedef union {
+    struct {
+        /** data_type_min : R/W; bitpos: [5:0]; default: 24;
+         *  the min value of data type used for pixel filter.
+         */
+        uint32_t data_type_min:6;
+        uint32_t reserved_6:2;
+        /** data_type_max : R/W; bitpos: [13:8]; default: 47;
+         *  the max value of data type used for pixel filter.
+         */
+        uint32_t data_type_max:6;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} csi_brg_data_type_cfg_reg_t;
+
+/** Type of frame_cfg register
+ *  frame configuration.
+ */
+typedef union {
+    struct {
+        /** vadr_num : R/W; bitpos: [11:0]; default: 480;
+         *  vadr of frame data.
+         */
+        uint32_t vadr_num:12;
+        /** hadr_num : R/W; bitpos: [23:12]; default: 480;
+         *  hadr of frame data.
+         */
+        uint32_t hadr_num:12;
+        /** has_hsync_e : R/W; bitpos: [24]; default: 1;
+         *  0: frame data doesn't contain hsync. 1: frame data contains hsync.
+         */
+        uint32_t has_hsync_e:1;
+        /** vadr_num_check : R/W; bitpos: [25]; default: 0;
+         *  0: disable vadr check. 1: enable vadr check.
+         */
+        uint32_t vadr_num_check:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} csi_brg_frame_cfg_reg_t;
+
+/** Type of endian_mode register
+ *  data endianness order configuration.
+ */
+typedef union {
+    struct {
+        /** byte_endian_order : R/W; bitpos: [0]; default: 0;
+         *  endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy)
+         *  when isp is bapassed.
+         */
+        uint32_t byte_endian_order:1;    //byte_swap_en
+        /** bit_endian_order : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t bit_endian_order:1;     //reserved
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_brg_endian_mode_reg_t;
+
+
+/** Group: csi bridge interrupt registers. */
+/** Type of int_raw register
+ *  csi bridge interrupt raw.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt raw.
+         */
+        uint32_t vadr_num_gt_int_raw:1;
+        /** vadr_num_lt_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt raw.
+         */
+        uint32_t vadr_num_lt_int_raw:1;
+        /** discard_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt raw.
+         */
+        uint32_t discard_int_raw:1;
+        /** csi_buf_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt raw.
+         */
+        uint32_t csi_buf_overrun_int_raw:1;
+        /** csi_async_fifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt raw.
+         */
+        uint32_t csi_async_fifo_ovf_int_raw:1;
+        /** dma_cfg_has_updated_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt raw.
+         */
+        uint32_t dma_cfg_has_updated_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  csi bridge interrupt clr.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_real_int_clr : WT; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt clr.
+         */
+        uint32_t vadr_num_gt_real_int_clr:1;
+        /** vadr_num_lt_real_int_clr : WT; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt clr.
+         */
+        uint32_t vadr_num_lt_real_int_clr:1;
+        /** discard_int_clr : WT; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt clr.
+         */
+        uint32_t discard_int_clr:1;
+        /** csi_buf_overrun_int_clr : WT; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt clr.
+         */
+        uint32_t csi_buf_overrun_int_clr:1;
+        /** csi_async_fifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt clr.
+         */
+        uint32_t csi_async_fifo_ovf_int_clr:1;
+        /** dma_cfg_has_updated_int_clr : WT; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt clr.
+         */
+        uint32_t dma_cfg_has_updated_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_clr_reg_t;
+
+/** Type of int_st register
+ *  csi bridge interrupt st.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_st : RO; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt st.
+         */
+        uint32_t vadr_num_gt_int_st:1;
+        /** vadr_num_lt_int_st : RO; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt st.
+         */
+        uint32_t vadr_num_lt_int_st:1;
+        /** discard_int_st : RO; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt st.
+         */
+        uint32_t discard_int_st:1;
+        /** csi_buf_overrun_int_st : RO; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt st.
+         */
+        uint32_t csi_buf_overrun_int_st:1;
+        /** csi_async_fifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt st.
+         */
+        uint32_t csi_async_fifo_ovf_int_st:1;
+        /** dma_cfg_has_updated_int_st : RO; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt st.
+         */
+        uint32_t dma_cfg_has_updated_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_st_reg_t;
+
+/** Type of int_ena register
+ *  csi bridge interrupt enable.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_ena : R/W; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt enable.
+         */
+        uint32_t vadr_num_gt_int_ena:1;
+        /** vadr_num_lt_int_ena : R/W; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt enable.
+         */
+        uint32_t vadr_num_lt_int_ena:1;
+        /** discard_int_ena : R/W; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt enable.
+         */
+        uint32_t discard_int_ena:1;
+        /** csi_buf_overrun_int_ena : R/W; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt enable.
+         */
+        uint32_t csi_buf_overrun_int_ena:1;
+        /** csi_async_fifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt enable.
+         */
+        uint32_t csi_async_fifo_ovf_int_ena:1;
+        /** dma_cfg_has_updated_int_ena : R/W; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt enable.
+         */
+        uint32_t dma_cfg_has_updated_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_ena_reg_t;
+
+
+/** Group: csi-host control registers from csi bridge regbank. */
+/** Type of host_ctrl register
+ *  csi host control by csi bridge.
+ */
+typedef union {
+    struct {
+        /** csi_enableclk : R/W; bitpos: [0]; default: 1;
+         *  enable clock lane module of csi phy.
+         */
+        uint32_t csi_enableclk:1;
+        /** csi_cfg_clk_en : R/W; bitpos: [1]; default: 1;
+         *  enable cfg_clk of csi host module.
+         */
+        uint32_t csi_cfg_clk_en:1;
+        /** loopbk_test_en : R/W; bitpos: [2]; default: 0;
+         *  for phy test by loopback dsi phy to csi phy.
+         */
+        uint32_t loopbk_test_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} csi_brg_host_ctrl_reg_t;
+
+
+typedef struct csi_brg_dev_t {
+    volatile csi_brg_clk_en_reg_t clk_en;
+    volatile csi_brg_csi_en_reg_t csi_en;
+    volatile csi_brg_dma_req_cfg_reg_t dma_req_cfg;
+    volatile csi_brg_buf_flow_ctl_reg_t buf_flow_ctl;
+    volatile csi_brg_data_type_cfg_reg_t data_type_cfg;
+    volatile csi_brg_frame_cfg_reg_t frame_cfg;
+    volatile csi_brg_endian_mode_reg_t endian_mode;
+    volatile csi_brg_int_raw_reg_t int_raw;
+    volatile csi_brg_int_clr_reg_t int_clr;
+    volatile csi_brg_int_st_reg_t int_st;
+    volatile csi_brg_int_ena_reg_t int_ena;
+    volatile csi_brg_dma_req_interval_reg_t dma_req_interval;
+    volatile csi_brg_dmablk_size_reg_t dmablk_size;
+    uint32_t reserved_034[3];
+    volatile csi_brg_host_ctrl_reg_t host_ctrl;
+} csi_brg_dev_t;
+
+extern csi_brg_dev_t MIPI_CSI_BRIDGE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(csi_brg_dev_t) == 0x44, "Invalid size of csi_brg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_eco5_struct.h
new file mode 100644
index 0000000000..1c4ade584f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_eco5_struct.h
@@ -0,0 +1,1883 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Version Register */
+/** Type of version register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** version : RO; bitpos: [31:0]; default: 825569322;
+         *  NA
+         */
+        uint32_t version:32;
+    };
+    uint32_t val;
+} csi_host_version_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of n_lanes register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** n_lanes : R/W; bitpos: [2:0]; default: 1;
+         *  NA
+         */
+        uint32_t n_lanes:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} csi_host_n_lanes_reg_t;
+
+/** Type of csi2_resetn register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** csi2_resetn : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t csi2_resetn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_csi2_resetn_reg_t;
+
+/** Type of phy_shutdownz register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_shutdownz : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_shutdownz:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_phy_shutdownz_reg_t;
+
+/** Type of dphy_rstz register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dphy_rstz : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_rstz:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_dphy_rstz_reg_t;
+
+/** Type of phy_rx register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_rxulpsesc_0 : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_rxulpsesc_0:1;
+        /** phy_rxulpsesc_1 : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_rxulpsesc_1:1;
+        uint32_t reserved_2:14;
+        /** phy_rxulpsclknot : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t phy_rxulpsclknot:1;
+        /** phy_rxclkactivehs : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t phy_rxclkactivehs:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} csi_host_phy_rx_reg_t;
+
+/** Type of phy_test_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_testclr : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t phy_testclr:1;
+        /** phy_testclk : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testclk:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_phy_test_ctrl0_reg_t;
+
+/** Type of phy_test_ctrl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_testdin : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testdin:8;
+        /** phy_testdout : RO; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testdout:8;
+        /** phy_testen : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testen:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} csi_host_phy_test_ctrl1_reg_t;
+
+/** Type of vc_extension register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vcx : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t vcx:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_vc_extension_reg_t;
+
+/** Type of phy_cal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** rxskewcalhs : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t rxskewcalhs:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_phy_cal_reg_t;
+
+/** Type of scrambling register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** scramble_enable : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t scramble_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_scrambling_reg_t;
+
+/** Type of scrambling_seed1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** scramble_seed_lane1 : R/W; bitpos: [15:0]; default: 4104;
+         *  NA
+         */
+        uint32_t scramble_seed_lane1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_scrambling_seed1_reg_t;
+
+/** Type of scrambling_seed2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** scramble_seed_lane2 : R/W; bitpos: [15:0]; default: 4488;
+         *  NA
+         */
+        uint32_t scramble_seed_lane2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_scrambling_seed2_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_st_main register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_status_int_phy_fatal : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_phy_fatal:1;
+        /** st_status_int_pkt_fatal : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_pkt_fatal:1;
+        /** st_status_int_bndry_frame_fatal : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_bndry_frame_fatal:1;
+        /** st_status_int_seq_frame_fatal : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_seq_frame_fatal:1;
+        /** st_status_int_crc_frame_fatal : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_crc_frame_fatal:1;
+        /** st_status_int_pld_crc_fatal : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_pld_crc_fatal:1;
+        /** st_status_int_data_id : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_data_id:1;
+        /** st_status_int_ecc_corrected : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_ecc_corrected:1;
+        uint32_t reserved_8:8;
+        /** st_status_int_phy : RC; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_phy:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} csi_host_int_st_main_reg_t;
+
+/** Type of int_st_phy_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_phy_errsotsynchs_0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_errsotsynchs_0:1;
+        /** st_phy_errsotsynchs_1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_errsotsynchs_1:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_st_phy_fatal_reg_t;
+
+/** Type of int_msk_phy_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_errsotsynchs_0:1;
+        /** mask_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_errsotsynchs_1:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_msk_phy_fatal_reg_t;
+
+/** Type of int_force_phy_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_errsotsynchs_0:1;
+        /** force_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_errsotsynchs_1:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_force_phy_fatal_reg_t;
+
+/** Type of int_st_pkt_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_ecc_double : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_double:1;
+        /** st_shorter_payload : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_shorter_payload:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_st_pkt_fatal_reg_t;
+
+/** Type of int_msk_pkt_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_ecc_double : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_double:1;
+        /** mask_shorter_payload : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_shorter_payload:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_msk_pkt_fatal_reg_t;
+
+/** Type of int_force_pkt_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_ecc_double : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_double:1;
+        /** force_shorter_payload : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_shorter_payload:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_force_pkt_fatal_reg_t;
+
+/** Type of int_st_phy register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_phy_errsoths_0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_errsoths_0:1;
+        /** st_phy_errsoths_1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_errsoths_1:1;
+        uint32_t reserved_2:14;
+        /** st_phy_erresc_0 : RC; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_erresc_0:1;
+        /** st_phy_erresc_1 : RC; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_erresc_1:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} csi_host_int_st_phy_reg_t;
+
+/** Type of int_msk_phy register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_phy_errsoths_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_errsoths_0:1;
+        /** mask_phy_errsoths_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_errsoths_1:1;
+        uint32_t reserved_2:14;
+        /** mask_phy_erresc_0 : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_erresc_0:1;
+        /** mask_phy_erresc_1 : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_erresc_1:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} csi_host_int_msk_phy_reg_t;
+
+/** Type of int_force_phy register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_phy_errsoths_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_errsoths_0:1;
+        /** force_phy_errsoths_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_errsoths_1:1;
+        uint32_t reserved_2:14;
+        /** force_phy_erresc_0 : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_erresc_0:1;
+        /** force_phy_erresc_1 : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_erresc_1:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} csi_host_int_force_phy_reg_t;
+
+/** Type of int_st_bndry_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_f_bndry_match_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc0:1;
+        /** st_err_f_bndry_match_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc1:1;
+        /** st_err_f_bndry_match_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc2:1;
+        /** st_err_f_bndry_match_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc3:1;
+        /** st_err_f_bndry_match_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc4:1;
+        /** st_err_f_bndry_match_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc5:1;
+        /** st_err_f_bndry_match_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc6:1;
+        /** st_err_f_bndry_match_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc7:1;
+        /** st_err_f_bndry_match_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc8:1;
+        /** st_err_f_bndry_match_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc9:1;
+        /** st_err_f_bndry_match_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc10:1;
+        /** st_err_f_bndry_match_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc11:1;
+        /** st_err_f_bndry_match_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc12:1;
+        /** st_err_f_bndry_match_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc13:1;
+        /** st_err_f_bndry_match_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc14:1;
+        /** st_err_f_bndry_match_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_bndry_frame_fatal_reg_t;
+
+/** Type of int_msk_bndry_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc0:1;
+        /** mask_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc1:1;
+        /** mask_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc2:1;
+        /** mask_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc3:1;
+        /** mask_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc4:1;
+        /** mask_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc5:1;
+        /** mask_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc6:1;
+        /** mask_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc7:1;
+        /** mask_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc8:1;
+        /** mask_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc9:1;
+        /** mask_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc10:1;
+        /** mask_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc11:1;
+        /** mask_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc12:1;
+        /** mask_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc13:1;
+        /** mask_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc14:1;
+        /** mask_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_bndry_frame_fatal_reg_t;
+
+/** Type of int_force_bndry_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc0:1;
+        /** force_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc1:1;
+        /** force_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc2:1;
+        /** force_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc3:1;
+        /** force_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc4:1;
+        /** force_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc5:1;
+        /** force_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc6:1;
+        /** force_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc7:1;
+        /** force_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc8:1;
+        /** force_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc9:1;
+        /** force_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc10:1;
+        /** force_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc11:1;
+        /** force_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc12:1;
+        /** force_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc13:1;
+        /** force_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc14:1;
+        /** force_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_bndry_frame_fatal_reg_t;
+
+/** Type of int_st_seq_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_f_seq_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc0:1;
+        /** st_err_f_seq_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc1:1;
+        /** st_err_f_seq_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc2:1;
+        /** st_err_f_seq_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc3:1;
+        /** st_err_f_seq_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc4:1;
+        /** st_err_f_seq_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc5:1;
+        /** st_err_f_seq_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc6:1;
+        /** st_err_f_seq_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc7:1;
+        /** st_err_f_seq_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc8:1;
+        /** st_err_f_seq_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc9:1;
+        /** st_err_f_seq_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc10:1;
+        /** st_err_f_seq_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc11:1;
+        /** st_err_f_seq_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc12:1;
+        /** st_err_f_seq_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc13:1;
+        /** st_err_f_seq_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc14:1;
+        /** st_err_f_seq_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_seq_frame_fatal_reg_t;
+
+/** Type of int_msk_seq_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc0:1;
+        /** mask_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc1:1;
+        /** mask_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc2:1;
+        /** mask_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc3:1;
+        /** mask_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc4:1;
+        /** mask_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc5:1;
+        /** mask_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc6:1;
+        /** mask_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc7:1;
+        /** mask_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc8:1;
+        /** mask_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc9:1;
+        /** mask_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc10:1;
+        /** mask_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc11:1;
+        /** mask_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc12:1;
+        /** mask_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc13:1;
+        /** mask_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc14:1;
+        /** mask_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_seq_frame_fatal_reg_t;
+
+/** Type of int_force_seq_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc0:1;
+        /** force_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc1:1;
+        /** force_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc2:1;
+        /** force_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc3:1;
+        /** force_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc4:1;
+        /** force_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc5:1;
+        /** force_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc6:1;
+        /** force_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc7:1;
+        /** force_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc8:1;
+        /** force_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc9:1;
+        /** force_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc10:1;
+        /** force_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc11:1;
+        /** force_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc12:1;
+        /** force_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc13:1;
+        /** force_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc14:1;
+        /** force_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_seq_frame_fatal_reg_t;
+
+/** Type of int_st_crc_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_frame_data_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc0:1;
+        /** st_err_frame_data_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc1:1;
+        /** st_err_frame_data_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc2:1;
+        /** st_err_frame_data_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc3:1;
+        /** st_err_frame_data_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc4:1;
+        /** st_err_frame_data_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc5:1;
+        /** st_err_frame_data_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc6:1;
+        /** st_err_frame_data_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc7:1;
+        /** st_err_frame_data_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc8:1;
+        /** st_err_frame_data_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc9:1;
+        /** st_err_frame_data_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc10:1;
+        /** st_err_frame_data_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc11:1;
+        /** st_err_frame_data_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc12:1;
+        /** st_err_frame_data_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc13:1;
+        /** st_err_frame_data_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc14:1;
+        /** st_err_frame_data_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_crc_frame_fatal_reg_t;
+
+/** Type of int_msk_crc_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc0:1;
+        /** mask_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc1:1;
+        /** mask_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc2:1;
+        /** mask_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc3:1;
+        /** mask_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc4:1;
+        /** mask_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc5:1;
+        /** mask_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc6:1;
+        /** mask_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc7:1;
+        /** mask_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc8:1;
+        /** mask_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc9:1;
+        /** mask_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc10:1;
+        /** mask_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc11:1;
+        /** mask_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc12:1;
+        /** mask_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc13:1;
+        /** mask_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc14:1;
+        /** mask_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_crc_frame_fatal_reg_t;
+
+/** Type of int_force_crc_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc0:1;
+        /** force_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc1:1;
+        /** force_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc2:1;
+        /** force_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc3:1;
+        /** force_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc4:1;
+        /** force_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc5:1;
+        /** force_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc6:1;
+        /** force_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc7:1;
+        /** force_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc8:1;
+        /** force_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc9:1;
+        /** force_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc10:1;
+        /** force_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc11:1;
+        /** force_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc12:1;
+        /** force_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc13:1;
+        /** force_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc14:1;
+        /** force_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_crc_frame_fatal_reg_t;
+
+/** Type of int_st_pld_crc_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_crc_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc0:1;
+        /** st_err_crc_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc1:1;
+        /** st_err_crc_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc2:1;
+        /** st_err_crc_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc3:1;
+        /** st_err_crc_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc4:1;
+        /** st_err_crc_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc5:1;
+        /** st_err_crc_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc6:1;
+        /** st_err_crc_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc7:1;
+        /** st_err_crc_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc8:1;
+        /** st_err_crc_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc9:1;
+        /** st_err_crc_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc10:1;
+        /** st_err_crc_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc11:1;
+        /** st_err_crc_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc12:1;
+        /** st_err_crc_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc13:1;
+        /** st_err_crc_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc14:1;
+        /** st_err_crc_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_pld_crc_fatal_reg_t;
+
+/** Type of int_msk_pld_crc_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_crc_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc0:1;
+        /** mask_err_crc_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc1:1;
+        /** mask_err_crc_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc2:1;
+        /** mask_err_crc_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc3:1;
+        /** mask_err_crc_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc4:1;
+        /** mask_err_crc_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc5:1;
+        /** mask_err_crc_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc6:1;
+        /** mask_err_crc_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc7:1;
+        /** mask_err_crc_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc8:1;
+        /** mask_err_crc_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc9:1;
+        /** mask_err_crc_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc10:1;
+        /** mask_err_crc_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc11:1;
+        /** mask_err_crc_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc12:1;
+        /** mask_err_crc_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc13:1;
+        /** mask_err_crc_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc14:1;
+        /** mask_err_crc_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_pld_crc_fatal_reg_t;
+
+/** Type of int_force_pld_crc_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_crc_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc0:1;
+        /** force_err_crc_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc1:1;
+        /** force_err_crc_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc2:1;
+        /** force_err_crc_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc3:1;
+        /** force_err_crc_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc4:1;
+        /** force_err_crc_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc5:1;
+        /** force_err_crc_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc6:1;
+        /** force_err_crc_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc7:1;
+        /** force_err_crc_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc8:1;
+        /** force_err_crc_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc9:1;
+        /** force_err_crc_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc10:1;
+        /** force_err_crc_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc11:1;
+        /** force_err_crc_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc12:1;
+        /** force_err_crc_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc13:1;
+        /** force_err_crc_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc14:1;
+        /** force_err_crc_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_pld_crc_fatal_reg_t;
+
+/** Type of int_st_data_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_id_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc0:1;
+        /** st_err_id_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc1:1;
+        /** st_err_id_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc2:1;
+        /** st_err_id_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc3:1;
+        /** st_err_id_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc4:1;
+        /** st_err_id_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc5:1;
+        /** st_err_id_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc6:1;
+        /** st_err_id_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc7:1;
+        /** st_err_id_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc8:1;
+        /** st_err_id_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc9:1;
+        /** st_err_id_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc10:1;
+        /** st_err_id_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc11:1;
+        /** st_err_id_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc12:1;
+        /** st_err_id_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc13:1;
+        /** st_err_id_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc14:1;
+        /** st_err_id_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_data_id_reg_t;
+
+/** Type of int_msk_data_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_id_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc0:1;
+        /** mask_err_id_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc1:1;
+        /** mask_err_id_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc2:1;
+        /** mask_err_id_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc3:1;
+        /** mask_err_id_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc4:1;
+        /** mask_err_id_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc5:1;
+        /** mask_err_id_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc6:1;
+        /** mask_err_id_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc7:1;
+        /** mask_err_id_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc8:1;
+        /** mask_err_id_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc9:1;
+        /** mask_err_id_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc10:1;
+        /** mask_err_id_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc11:1;
+        /** mask_err_id_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc12:1;
+        /** mask_err_id_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc13:1;
+        /** mask_err_id_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc14:1;
+        /** mask_err_id_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_data_id_reg_t;
+
+/** Type of int_force_data_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_id_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc0:1;
+        /** force_err_id_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc1:1;
+        /** force_err_id_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc2:1;
+        /** force_err_id_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc3:1;
+        /** force_err_id_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc4:1;
+        /** force_err_id_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc5:1;
+        /** force_err_id_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc6:1;
+        /** force_err_id_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc7:1;
+        /** force_err_id_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc8:1;
+        /** force_err_id_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc9:1;
+        /** force_err_id_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc10:1;
+        /** force_err_id_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc11:1;
+        /** force_err_id_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc12:1;
+        /** force_err_id_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc13:1;
+        /** force_err_id_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc14:1;
+        /** force_err_id_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_data_id_reg_t;
+
+/** Type of int_st_ecc_corrected register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_ecc_corrected_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc0:1;
+        /** st_err_ecc_corrected_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc1:1;
+        /** st_err_ecc_corrected_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc2:1;
+        /** st_err_ecc_corrected_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc3:1;
+        /** st_err_ecc_corrected_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc4:1;
+        /** st_err_ecc_corrected_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc5:1;
+        /** st_err_ecc_corrected_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc6:1;
+        /** st_err_ecc_corrected_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc7:1;
+        /** st_err_ecc_corrected_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc8:1;
+        /** st_err_ecc_corrected_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc9:1;
+        /** st_err_ecc_corrected_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc10:1;
+        /** st_err_ecc_corrected_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc11:1;
+        /** st_err_ecc_corrected_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc12:1;
+        /** st_err_ecc_corrected_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc13:1;
+        /** st_err_ecc_corrected_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc14:1;
+        /** st_err_ecc_corrected_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_ecc_corrected_reg_t;
+
+/** Type of int_msk_ecc_corrected register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc0:1;
+        /** mask_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc1:1;
+        /** mask_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc2:1;
+        /** mask_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc3:1;
+        /** mask_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc4:1;
+        /** mask_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc5:1;
+        /** mask_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc6:1;
+        /** mask_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc7:1;
+        /** mask_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc8:1;
+        /** mask_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc9:1;
+        /** mask_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc10:1;
+        /** mask_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc11:1;
+        /** mask_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc12:1;
+        /** mask_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc13:1;
+        /** mask_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc14:1;
+        /** mask_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_ecc_corrected_reg_t;
+
+/** Type of int_force_ecc_corrected register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc0:1;
+        /** force_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc1:1;
+        /** force_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc2:1;
+        /** force_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc3:1;
+        /** force_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc4:1;
+        /** force_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc5:1;
+        /** force_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc6:1;
+        /** force_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc7:1;
+        /** force_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc8:1;
+        /** force_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc9:1;
+        /** force_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc10:1;
+        /** force_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc11:1;
+        /** force_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc12:1;
+        /** force_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc13:1;
+        /** force_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc14:1;
+        /** force_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_ecc_corrected_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of phy_stopstate register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_stopstatedata_0 : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstatedata_0:1;
+        /** phy_stopstatedata_1 : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstatedata_1:1;
+        uint32_t reserved_2:14;
+        /** phy_stopstateclk : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstateclk:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} csi_host_phy_stopstate_reg_t;
+
+
+typedef struct {
+    volatile csi_host_version_reg_t version;
+    volatile csi_host_n_lanes_reg_t n_lanes;
+    volatile csi_host_csi2_resetn_reg_t csi2_resetn;
+    volatile csi_host_int_st_main_reg_t int_st_main;
+    uint32_t reserved_010[12];
+    volatile csi_host_phy_shutdownz_reg_t phy_shutdownz;
+    volatile csi_host_dphy_rstz_reg_t dphy_rstz;
+    volatile csi_host_phy_rx_reg_t phy_rx;
+    volatile csi_host_phy_stopstate_reg_t phy_stopstate;
+    volatile csi_host_phy_test_ctrl0_reg_t phy_test_ctrl0;
+    volatile csi_host_phy_test_ctrl1_reg_t phy_test_ctrl1;
+    uint32_t reserved_058[28];
+    volatile csi_host_vc_extension_reg_t vc_extension;
+    volatile csi_host_phy_cal_reg_t phy_cal;
+    uint32_t reserved_0d0[4];
+    volatile csi_host_int_st_phy_fatal_reg_t int_st_phy_fatal;
+    volatile csi_host_int_msk_phy_fatal_reg_t int_msk_phy_fatal;
+    volatile csi_host_int_force_phy_fatal_reg_t int_force_phy_fatal;
+    uint32_t reserved_0ec;
+    volatile csi_host_int_st_pkt_fatal_reg_t int_st_pkt_fatal;
+    volatile csi_host_int_msk_pkt_fatal_reg_t int_msk_pkt_fatal;
+    volatile csi_host_int_force_pkt_fatal_reg_t int_force_pkt_fatal;
+    uint32_t reserved_0fc[5];
+    volatile csi_host_int_st_phy_reg_t int_st_phy;
+    volatile csi_host_int_msk_phy_reg_t int_msk_phy;
+    volatile csi_host_int_force_phy_reg_t int_force_phy;
+    uint32_t reserved_11c[89];
+    volatile csi_host_int_st_bndry_frame_fatal_reg_t int_st_bndry_frame_fatal;
+    volatile csi_host_int_msk_bndry_frame_fatal_reg_t int_msk_bndry_frame_fatal;
+    volatile csi_host_int_force_bndry_frame_fatal_reg_t int_force_bndry_frame_fatal;
+    uint32_t reserved_28c;
+    volatile csi_host_int_st_seq_frame_fatal_reg_t int_st_seq_frame_fatal;
+    volatile csi_host_int_msk_seq_frame_fatal_reg_t int_msk_seq_frame_fatal;
+    volatile csi_host_int_force_seq_frame_fatal_reg_t int_force_seq_frame_fatal;
+    uint32_t reserved_29c;
+    volatile csi_host_int_st_crc_frame_fatal_reg_t int_st_crc_frame_fatal;
+    volatile csi_host_int_msk_crc_frame_fatal_reg_t int_msk_crc_frame_fatal;
+    volatile csi_host_int_force_crc_frame_fatal_reg_t int_force_crc_frame_fatal;
+    uint32_t reserved_2ac;
+    volatile csi_host_int_st_pld_crc_fatal_reg_t int_st_pld_crc_fatal;
+    volatile csi_host_int_msk_pld_crc_fatal_reg_t int_msk_pld_crc_fatal;
+    volatile csi_host_int_force_pld_crc_fatal_reg_t int_force_pld_crc_fatal;
+    uint32_t reserved_2bc;
+    volatile csi_host_int_st_data_id_reg_t int_st_data_id;
+    volatile csi_host_int_msk_data_id_reg_t int_msk_data_id;
+    volatile csi_host_int_force_data_id_reg_t int_force_data_id;
+    uint32_t reserved_2cc;
+    volatile csi_host_int_st_ecc_corrected_reg_t int_st_ecc_corrected;
+    volatile csi_host_int_msk_ecc_corrected_reg_t int_msk_ecc_corrected;
+    volatile csi_host_int_force_ecc_corrected_reg_t int_force_ecc_corrected;
+    uint32_t reserved_2dc[9];
+    volatile csi_host_scrambling_reg_t scrambling;
+    volatile csi_host_scrambling_seed1_reg_t scrambling_seed1;
+    volatile csi_host_scrambling_seed2_reg_t scrambling_seed2;
+} csi_host_dev_t;
+
+extern csi_host_dev_t MIPI_CSI_HOST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(csi_host_dev_t) == 0x30c, "Invalid size of csi_host_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_reg.h
new file mode 100644
index 0000000000..2527e2c67e
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_reg.h
@@ -0,0 +1,2627 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CSI_HOST_VERSION_REG register
+ *  NA
+ */
+#define CSI_HOST_VERSION_REG (DR_REG_CSI_HOST_BASE + 0x0)
+/** CSI_HOST_VERSION : RO; bitpos: [31:0]; default: 825569322;
+ *  NA
+ */
+#define CSI_HOST_VERSION    0xFFFFFFFFU
+#define CSI_HOST_VERSION_M  (CSI_HOST_VERSION_V << CSI_HOST_VERSION_S)
+#define CSI_HOST_VERSION_V  0xFFFFFFFFU
+#define CSI_HOST_VERSION_S  0
+
+/** CSI_HOST_N_LANES_REG register
+ *  NA
+ */
+#define CSI_HOST_N_LANES_REG (DR_REG_CSI_HOST_BASE + 0x4)
+/** CSI_HOST_N_LANES : R/W; bitpos: [2:0]; default: 1;
+ *  NA
+ */
+#define CSI_HOST_N_LANES    0x00000007U
+#define CSI_HOST_N_LANES_M  (CSI_HOST_N_LANES_V << CSI_HOST_N_LANES_S)
+#define CSI_HOST_N_LANES_V  0x00000007U
+#define CSI_HOST_N_LANES_S  0
+
+/** CSI_HOST_CSI2_RESETN_REG register
+ *  NA
+ */
+#define CSI_HOST_CSI2_RESETN_REG (DR_REG_CSI_HOST_BASE + 0x8)
+/** CSI_HOST_CSI2_RESETN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_CSI2_RESETN    (BIT(0))
+#define CSI_HOST_CSI2_RESETN_M  (CSI_HOST_CSI2_RESETN_V << CSI_HOST_CSI2_RESETN_S)
+#define CSI_HOST_CSI2_RESETN_V  0x00000001U
+#define CSI_HOST_CSI2_RESETN_S  0
+
+/** CSI_HOST_INT_ST_MAIN_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_ST_MAIN_REG (DR_REG_CSI_HOST_BASE + 0xc)
+/** CSI_HOST_ST_STATUS_INT_PHY_FATAL : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_STATUS_INT_PHY_FATAL    (BIT(0))
+#define CSI_HOST_ST_STATUS_INT_PHY_FATAL_M  (CSI_HOST_ST_STATUS_INT_PHY_FATAL_V << CSI_HOST_ST_STATUS_INT_PHY_FATAL_S)
+#define CSI_HOST_ST_STATUS_INT_PHY_FATAL_V  0x00000001U
+#define CSI_HOST_ST_STATUS_INT_PHY_FATAL_S  0
+/** CSI_HOST_ST_STATUS_INT_PKT_FATAL : RC; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_STATUS_INT_PKT_FATAL    (BIT(1))
+#define CSI_HOST_ST_STATUS_INT_PKT_FATAL_M  (CSI_HOST_ST_STATUS_INT_PKT_FATAL_V << CSI_HOST_ST_STATUS_INT_PKT_FATAL_S)
+#define CSI_HOST_ST_STATUS_INT_PKT_FATAL_V  0x00000001U
+#define CSI_HOST_ST_STATUS_INT_PKT_FATAL_S  1
+/** CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL : RC; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL    (BIT(2))
+#define CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL_M  (CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL_V << CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL_S)
+#define CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL_V  0x00000001U
+#define CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL_S  2
+/** CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL : RC; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL    (BIT(3))
+#define CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL_M  (CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL_V << CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL_S)
+#define CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL_V  0x00000001U
+#define CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL_S  3
+/** CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL : RC; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL    (BIT(4))
+#define CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL_M  (CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL_V << CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL_S)
+#define CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL_V  0x00000001U
+#define CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL_S  4
+/** CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL : RC; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL    (BIT(5))
+#define CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL_M  (CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL_V << CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL_S)
+#define CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL_V  0x00000001U
+#define CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL_S  5
+/** CSI_HOST_ST_STATUS_INT_DATA_ID : RC; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_STATUS_INT_DATA_ID    (BIT(6))
+#define CSI_HOST_ST_STATUS_INT_DATA_ID_M  (CSI_HOST_ST_STATUS_INT_DATA_ID_V << CSI_HOST_ST_STATUS_INT_DATA_ID_S)
+#define CSI_HOST_ST_STATUS_INT_DATA_ID_V  0x00000001U
+#define CSI_HOST_ST_STATUS_INT_DATA_ID_S  6
+/** CSI_HOST_ST_STATUS_INT_ECC_CORRECTED : RC; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_STATUS_INT_ECC_CORRECTED    (BIT(7))
+#define CSI_HOST_ST_STATUS_INT_ECC_CORRECTED_M  (CSI_HOST_ST_STATUS_INT_ECC_CORRECTED_V << CSI_HOST_ST_STATUS_INT_ECC_CORRECTED_S)
+#define CSI_HOST_ST_STATUS_INT_ECC_CORRECTED_V  0x00000001U
+#define CSI_HOST_ST_STATUS_INT_ECC_CORRECTED_S  7
+/** CSI_HOST_ST_STATUS_INT_PHY : RC; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_STATUS_INT_PHY    (BIT(16))
+#define CSI_HOST_ST_STATUS_INT_PHY_M  (CSI_HOST_ST_STATUS_INT_PHY_V << CSI_HOST_ST_STATUS_INT_PHY_S)
+#define CSI_HOST_ST_STATUS_INT_PHY_V  0x00000001U
+#define CSI_HOST_ST_STATUS_INT_PHY_S  16
+
+/** CSI_HOST_PHY_SHUTDOWNZ_REG register
+ *  NA
+ */
+#define CSI_HOST_PHY_SHUTDOWNZ_REG (DR_REG_CSI_HOST_BASE + 0x40)
+/** CSI_HOST_PHY_SHUTDOWNZ : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_SHUTDOWNZ    (BIT(0))
+#define CSI_HOST_PHY_SHUTDOWNZ_M  (CSI_HOST_PHY_SHUTDOWNZ_V << CSI_HOST_PHY_SHUTDOWNZ_S)
+#define CSI_HOST_PHY_SHUTDOWNZ_V  0x00000001U
+#define CSI_HOST_PHY_SHUTDOWNZ_S  0
+
+/** CSI_HOST_DPHY_RSTZ_REG register
+ *  NA
+ */
+#define CSI_HOST_DPHY_RSTZ_REG (DR_REG_CSI_HOST_BASE + 0x44)
+/** CSI_HOST_DPHY_RSTZ : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_DPHY_RSTZ    (BIT(0))
+#define CSI_HOST_DPHY_RSTZ_M  (CSI_HOST_DPHY_RSTZ_V << CSI_HOST_DPHY_RSTZ_S)
+#define CSI_HOST_DPHY_RSTZ_V  0x00000001U
+#define CSI_HOST_DPHY_RSTZ_S  0
+
+/** CSI_HOST_PHY_RX_REG register
+ *  NA
+ */
+#define CSI_HOST_PHY_RX_REG (DR_REG_CSI_HOST_BASE + 0x48)
+/** CSI_HOST_PHY_RXULPSESC_0 : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_RXULPSESC_0    (BIT(0))
+#define CSI_HOST_PHY_RXULPSESC_0_M  (CSI_HOST_PHY_RXULPSESC_0_V << CSI_HOST_PHY_RXULPSESC_0_S)
+#define CSI_HOST_PHY_RXULPSESC_0_V  0x00000001U
+#define CSI_HOST_PHY_RXULPSESC_0_S  0
+/** CSI_HOST_PHY_RXULPSESC_1 : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_RXULPSESC_1    (BIT(1))
+#define CSI_HOST_PHY_RXULPSESC_1_M  (CSI_HOST_PHY_RXULPSESC_1_V << CSI_HOST_PHY_RXULPSESC_1_S)
+#define CSI_HOST_PHY_RXULPSESC_1_V  0x00000001U
+#define CSI_HOST_PHY_RXULPSESC_1_S  1
+/** CSI_HOST_PHY_RXULPSCLKNOT : RO; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define CSI_HOST_PHY_RXULPSCLKNOT    (BIT(16))
+#define CSI_HOST_PHY_RXULPSCLKNOT_M  (CSI_HOST_PHY_RXULPSCLKNOT_V << CSI_HOST_PHY_RXULPSCLKNOT_S)
+#define CSI_HOST_PHY_RXULPSCLKNOT_V  0x00000001U
+#define CSI_HOST_PHY_RXULPSCLKNOT_S  16
+/** CSI_HOST_PHY_RXCLKACTIVEHS : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_RXCLKACTIVEHS    (BIT(17))
+#define CSI_HOST_PHY_RXCLKACTIVEHS_M  (CSI_HOST_PHY_RXCLKACTIVEHS_V << CSI_HOST_PHY_RXCLKACTIVEHS_S)
+#define CSI_HOST_PHY_RXCLKACTIVEHS_V  0x00000001U
+#define CSI_HOST_PHY_RXCLKACTIVEHS_S  17
+
+/** CSI_HOST_PHY_STOPSTATE_REG register
+ *  NA
+ */
+#define CSI_HOST_PHY_STOPSTATE_REG (DR_REG_CSI_HOST_BASE + 0x4c)
+/** CSI_HOST_PHY_STOPSTATEDATA_0 : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_STOPSTATEDATA_0    (BIT(0))
+#define CSI_HOST_PHY_STOPSTATEDATA_0_M  (CSI_HOST_PHY_STOPSTATEDATA_0_V << CSI_HOST_PHY_STOPSTATEDATA_0_S)
+#define CSI_HOST_PHY_STOPSTATEDATA_0_V  0x00000001U
+#define CSI_HOST_PHY_STOPSTATEDATA_0_S  0
+/** CSI_HOST_PHY_STOPSTATEDATA_1 : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_STOPSTATEDATA_1    (BIT(1))
+#define CSI_HOST_PHY_STOPSTATEDATA_1_M  (CSI_HOST_PHY_STOPSTATEDATA_1_V << CSI_HOST_PHY_STOPSTATEDATA_1_S)
+#define CSI_HOST_PHY_STOPSTATEDATA_1_V  0x00000001U
+#define CSI_HOST_PHY_STOPSTATEDATA_1_S  1
+/** CSI_HOST_PHY_STOPSTATECLK : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_STOPSTATECLK    (BIT(16))
+#define CSI_HOST_PHY_STOPSTATECLK_M  (CSI_HOST_PHY_STOPSTATECLK_V << CSI_HOST_PHY_STOPSTATECLK_S)
+#define CSI_HOST_PHY_STOPSTATECLK_V  0x00000001U
+#define CSI_HOST_PHY_STOPSTATECLK_S  16
+
+/** CSI_HOST_PHY_TEST_CTRL0_REG register
+ *  NA
+ */
+#define CSI_HOST_PHY_TEST_CTRL0_REG (DR_REG_CSI_HOST_BASE + 0x50)
+/** CSI_HOST_PHY_TESTCLR : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define CSI_HOST_PHY_TESTCLR    (BIT(0))
+#define CSI_HOST_PHY_TESTCLR_M  (CSI_HOST_PHY_TESTCLR_V << CSI_HOST_PHY_TESTCLR_S)
+#define CSI_HOST_PHY_TESTCLR_V  0x00000001U
+#define CSI_HOST_PHY_TESTCLR_S  0
+/** CSI_HOST_PHY_TESTCLK : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_TESTCLK    (BIT(1))
+#define CSI_HOST_PHY_TESTCLK_M  (CSI_HOST_PHY_TESTCLK_V << CSI_HOST_PHY_TESTCLK_S)
+#define CSI_HOST_PHY_TESTCLK_V  0x00000001U
+#define CSI_HOST_PHY_TESTCLK_S  1
+
+/** CSI_HOST_PHY_TEST_CTRL1_REG register
+ *  NA
+ */
+#define CSI_HOST_PHY_TEST_CTRL1_REG (DR_REG_CSI_HOST_BASE + 0x54)
+/** CSI_HOST_PHY_TESTDIN : R/W; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_TESTDIN    0x000000FFU
+#define CSI_HOST_PHY_TESTDIN_M  (CSI_HOST_PHY_TESTDIN_V << CSI_HOST_PHY_TESTDIN_S)
+#define CSI_HOST_PHY_TESTDIN_V  0x000000FFU
+#define CSI_HOST_PHY_TESTDIN_S  0
+/** CSI_HOST_PHY_TESTDOUT : RO; bitpos: [15:8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_TESTDOUT    0x000000FFU
+#define CSI_HOST_PHY_TESTDOUT_M  (CSI_HOST_PHY_TESTDOUT_V << CSI_HOST_PHY_TESTDOUT_S)
+#define CSI_HOST_PHY_TESTDOUT_V  0x000000FFU
+#define CSI_HOST_PHY_TESTDOUT_S  8
+/** CSI_HOST_PHY_TESTEN : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_PHY_TESTEN    (BIT(16))
+#define CSI_HOST_PHY_TESTEN_M  (CSI_HOST_PHY_TESTEN_V << CSI_HOST_PHY_TESTEN_S)
+#define CSI_HOST_PHY_TESTEN_V  0x00000001U
+#define CSI_HOST_PHY_TESTEN_S  16
+
+/** CSI_HOST_VC_EXTENSION_REG register
+ *  NA
+ */
+#define CSI_HOST_VC_EXTENSION_REG (DR_REG_CSI_HOST_BASE + 0xc8)
+/** CSI_HOST_VCX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_VCX    (BIT(0))
+#define CSI_HOST_VCX_M  (CSI_HOST_VCX_V << CSI_HOST_VCX_S)
+#define CSI_HOST_VCX_V  0x00000001U
+#define CSI_HOST_VCX_S  0
+
+/** CSI_HOST_PHY_CAL_REG register
+ *  NA
+ */
+#define CSI_HOST_PHY_CAL_REG (DR_REG_CSI_HOST_BASE + 0xcc)
+/** CSI_HOST_RXSKEWCALHS : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_RXSKEWCALHS    (BIT(0))
+#define CSI_HOST_RXSKEWCALHS_M  (CSI_HOST_RXSKEWCALHS_V << CSI_HOST_RXSKEWCALHS_S)
+#define CSI_HOST_RXSKEWCALHS_V  0x00000001U
+#define CSI_HOST_RXSKEWCALHS_S  0
+
+/** CSI_HOST_INT_ST_PHY_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_ST_PHY_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xe0)
+/** CSI_HOST_ST_PHY_ERRSOTSYNCHS_0 : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_0    (BIT(0))
+#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_0_M  (CSI_HOST_ST_PHY_ERRSOTSYNCHS_0_V << CSI_HOST_ST_PHY_ERRSOTSYNCHS_0_S)
+#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_0_V  0x00000001U
+#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_0_S  0
+/** CSI_HOST_ST_PHY_ERRSOTSYNCHS_1 : RC; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_1    (BIT(1))
+#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_1_M  (CSI_HOST_ST_PHY_ERRSOTSYNCHS_1_V << CSI_HOST_ST_PHY_ERRSOTSYNCHS_1_S)
+#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_1_V  0x00000001U
+#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_1_S  1
+
+/** CSI_HOST_INT_MSK_PHY_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_MSK_PHY_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xe4)
+/** CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0    (BIT(0))
+#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0_M  (CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0_V << CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0_S)
+#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0_V  0x00000001U
+#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0_S  0
+/** CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1    (BIT(1))
+#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1_M  (CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1_V << CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1_S)
+#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1_V  0x00000001U
+#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1_S  1
+
+/** CSI_HOST_INT_FORCE_PHY_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_FORCE_PHY_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xe8)
+/** CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0    (BIT(0))
+#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0_M  (CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0_V << CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0_S)
+#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0_V  0x00000001U
+#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0_S  0
+/** CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1    (BIT(1))
+#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1_M  (CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1_V << CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1_S)
+#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1_V  0x00000001U
+#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1_S  1
+
+/** CSI_HOST_INT_ST_PKT_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_ST_PKT_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xf0)
+/** CSI_HOST_ST_ERR_ECC_DOUBLE : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_DOUBLE    (BIT(0))
+#define CSI_HOST_ST_ERR_ECC_DOUBLE_M  (CSI_HOST_ST_ERR_ECC_DOUBLE_V << CSI_HOST_ST_ERR_ECC_DOUBLE_S)
+#define CSI_HOST_ST_ERR_ECC_DOUBLE_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_DOUBLE_S  0
+/** CSI_HOST_ST_SHORTER_PAYLOAD : RC; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_SHORTER_PAYLOAD    (BIT(1))
+#define CSI_HOST_ST_SHORTER_PAYLOAD_M  (CSI_HOST_ST_SHORTER_PAYLOAD_V << CSI_HOST_ST_SHORTER_PAYLOAD_S)
+#define CSI_HOST_ST_SHORTER_PAYLOAD_V  0x00000001U
+#define CSI_HOST_ST_SHORTER_PAYLOAD_S  1
+
+/** CSI_HOST_INT_MSK_PKT_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_MSK_PKT_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xf4)
+/** CSI_HOST_MASK_ERR_ECC_DOUBLE : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_DOUBLE    (BIT(0))
+#define CSI_HOST_MASK_ERR_ECC_DOUBLE_M  (CSI_HOST_MASK_ERR_ECC_DOUBLE_V << CSI_HOST_MASK_ERR_ECC_DOUBLE_S)
+#define CSI_HOST_MASK_ERR_ECC_DOUBLE_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_DOUBLE_S  0
+/** CSI_HOST_MASK_SHORTER_PAYLOAD : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_SHORTER_PAYLOAD    (BIT(1))
+#define CSI_HOST_MASK_SHORTER_PAYLOAD_M  (CSI_HOST_MASK_SHORTER_PAYLOAD_V << CSI_HOST_MASK_SHORTER_PAYLOAD_S)
+#define CSI_HOST_MASK_SHORTER_PAYLOAD_V  0x00000001U
+#define CSI_HOST_MASK_SHORTER_PAYLOAD_S  1
+
+/** CSI_HOST_INT_FORCE_PKT_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_FORCE_PKT_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xf8)
+/** CSI_HOST_FORCE_ERR_ECC_DOUBLE : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_DOUBLE    (BIT(0))
+#define CSI_HOST_FORCE_ERR_ECC_DOUBLE_M  (CSI_HOST_FORCE_ERR_ECC_DOUBLE_V << CSI_HOST_FORCE_ERR_ECC_DOUBLE_S)
+#define CSI_HOST_FORCE_ERR_ECC_DOUBLE_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_DOUBLE_S  0
+/** CSI_HOST_FORCE_SHORTER_PAYLOAD : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_SHORTER_PAYLOAD    (BIT(1))
+#define CSI_HOST_FORCE_SHORTER_PAYLOAD_M  (CSI_HOST_FORCE_SHORTER_PAYLOAD_V << CSI_HOST_FORCE_SHORTER_PAYLOAD_S)
+#define CSI_HOST_FORCE_SHORTER_PAYLOAD_V  0x00000001U
+#define CSI_HOST_FORCE_SHORTER_PAYLOAD_S  1
+
+/** CSI_HOST_INT_ST_PHY_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_ST_PHY_REG (DR_REG_CSI_HOST_BASE + 0x110)
+/** CSI_HOST_ST_PHY_ERRSOTHS_0 : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_PHY_ERRSOTHS_0    (BIT(0))
+#define CSI_HOST_ST_PHY_ERRSOTHS_0_M  (CSI_HOST_ST_PHY_ERRSOTHS_0_V << CSI_HOST_ST_PHY_ERRSOTHS_0_S)
+#define CSI_HOST_ST_PHY_ERRSOTHS_0_V  0x00000001U
+#define CSI_HOST_ST_PHY_ERRSOTHS_0_S  0
+/** CSI_HOST_ST_PHY_ERRSOTHS_1 : RC; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_PHY_ERRSOTHS_1    (BIT(1))
+#define CSI_HOST_ST_PHY_ERRSOTHS_1_M  (CSI_HOST_ST_PHY_ERRSOTHS_1_V << CSI_HOST_ST_PHY_ERRSOTHS_1_S)
+#define CSI_HOST_ST_PHY_ERRSOTHS_1_V  0x00000001U
+#define CSI_HOST_ST_PHY_ERRSOTHS_1_S  1
+/** CSI_HOST_ST_PHY_ERRESC_0 : RC; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_PHY_ERRESC_0    (BIT(16))
+#define CSI_HOST_ST_PHY_ERRESC_0_M  (CSI_HOST_ST_PHY_ERRESC_0_V << CSI_HOST_ST_PHY_ERRESC_0_S)
+#define CSI_HOST_ST_PHY_ERRESC_0_V  0x00000001U
+#define CSI_HOST_ST_PHY_ERRESC_0_S  16
+/** CSI_HOST_ST_PHY_ERRESC_1 : RC; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_PHY_ERRESC_1    (BIT(17))
+#define CSI_HOST_ST_PHY_ERRESC_1_M  (CSI_HOST_ST_PHY_ERRESC_1_V << CSI_HOST_ST_PHY_ERRESC_1_S)
+#define CSI_HOST_ST_PHY_ERRESC_1_V  0x00000001U
+#define CSI_HOST_ST_PHY_ERRESC_1_S  17
+
+/** CSI_HOST_INT_MSK_PHY_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_MSK_PHY_REG (DR_REG_CSI_HOST_BASE + 0x114)
+/** CSI_HOST_MASK_PHY_ERRSOTHS_0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_PHY_ERRSOTHS_0    (BIT(0))
+#define CSI_HOST_MASK_PHY_ERRSOTHS_0_M  (CSI_HOST_MASK_PHY_ERRSOTHS_0_V << CSI_HOST_MASK_PHY_ERRSOTHS_0_S)
+#define CSI_HOST_MASK_PHY_ERRSOTHS_0_V  0x00000001U
+#define CSI_HOST_MASK_PHY_ERRSOTHS_0_S  0
+/** CSI_HOST_MASK_PHY_ERRSOTHS_1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_PHY_ERRSOTHS_1    (BIT(1))
+#define CSI_HOST_MASK_PHY_ERRSOTHS_1_M  (CSI_HOST_MASK_PHY_ERRSOTHS_1_V << CSI_HOST_MASK_PHY_ERRSOTHS_1_S)
+#define CSI_HOST_MASK_PHY_ERRSOTHS_1_V  0x00000001U
+#define CSI_HOST_MASK_PHY_ERRSOTHS_1_S  1
+/** CSI_HOST_MASK_PHY_ERRESC_0 : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_PHY_ERRESC_0    (BIT(16))
+#define CSI_HOST_MASK_PHY_ERRESC_0_M  (CSI_HOST_MASK_PHY_ERRESC_0_V << CSI_HOST_MASK_PHY_ERRESC_0_S)
+#define CSI_HOST_MASK_PHY_ERRESC_0_V  0x00000001U
+#define CSI_HOST_MASK_PHY_ERRESC_0_S  16
+/** CSI_HOST_MASK_PHY_ERRESC_1 : R/W; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_PHY_ERRESC_1    (BIT(17))
+#define CSI_HOST_MASK_PHY_ERRESC_1_M  (CSI_HOST_MASK_PHY_ERRESC_1_V << CSI_HOST_MASK_PHY_ERRESC_1_S)
+#define CSI_HOST_MASK_PHY_ERRESC_1_V  0x00000001U
+#define CSI_HOST_MASK_PHY_ERRESC_1_S  17
+
+/** CSI_HOST_INT_FORCE_PHY_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_FORCE_PHY_REG (DR_REG_CSI_HOST_BASE + 0x118)
+/** CSI_HOST_FORCE_PHY_ERRSOTHS_0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_PHY_ERRSOTHS_0    (BIT(0))
+#define CSI_HOST_FORCE_PHY_ERRSOTHS_0_M  (CSI_HOST_FORCE_PHY_ERRSOTHS_0_V << CSI_HOST_FORCE_PHY_ERRSOTHS_0_S)
+#define CSI_HOST_FORCE_PHY_ERRSOTHS_0_V  0x00000001U
+#define CSI_HOST_FORCE_PHY_ERRSOTHS_0_S  0
+/** CSI_HOST_FORCE_PHY_ERRSOTHS_1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_PHY_ERRSOTHS_1    (BIT(1))
+#define CSI_HOST_FORCE_PHY_ERRSOTHS_1_M  (CSI_HOST_FORCE_PHY_ERRSOTHS_1_V << CSI_HOST_FORCE_PHY_ERRSOTHS_1_S)
+#define CSI_HOST_FORCE_PHY_ERRSOTHS_1_V  0x00000001U
+#define CSI_HOST_FORCE_PHY_ERRSOTHS_1_S  1
+/** CSI_HOST_FORCE_PHY_ERRESC_0 : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_PHY_ERRESC_0    (BIT(16))
+#define CSI_HOST_FORCE_PHY_ERRESC_0_M  (CSI_HOST_FORCE_PHY_ERRESC_0_V << CSI_HOST_FORCE_PHY_ERRESC_0_S)
+#define CSI_HOST_FORCE_PHY_ERRESC_0_V  0x00000001U
+#define CSI_HOST_FORCE_PHY_ERRESC_0_S  16
+/** CSI_HOST_FORCE_PHY_ERRESC_1 : R/W; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_PHY_ERRESC_1    (BIT(17))
+#define CSI_HOST_FORCE_PHY_ERRESC_1_M  (CSI_HOST_FORCE_PHY_ERRESC_1_V << CSI_HOST_FORCE_PHY_ERRESC_1_S)
+#define CSI_HOST_FORCE_PHY_ERRESC_1_V  0x00000001U
+#define CSI_HOST_FORCE_PHY_ERRESC_1_S  17
+
+/** CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x280)
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0 : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0    (BIT(0))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0_S  0
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1 : RC; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1    (BIT(1))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1_S  1
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2 : RC; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2    (BIT(2))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2_S  2
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3 : RC; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3    (BIT(3))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3_S  3
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4 : RC; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4    (BIT(4))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4_S  4
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5 : RC; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5    (BIT(5))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5_S  5
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6 : RC; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6    (BIT(6))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6_S  6
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7 : RC; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7    (BIT(7))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7_S  7
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8 : RC; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8    (BIT(8))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8_S  8
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9 : RC; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9    (BIT(9))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9_S  9
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10 : RC; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10    (BIT(10))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10_S  10
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11 : RC; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11    (BIT(11))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11_S  11
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12 : RC; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12    (BIT(12))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12_S  12
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13 : RC; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13    (BIT(13))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13_S  13
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14 : RC; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14    (BIT(14))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14_S  14
+/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15 : RC; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15    (BIT(15))
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15_M  (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15_S)
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15_S  15
+
+/** CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x284)
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0    (BIT(0))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0_S  0
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1    (BIT(1))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1_S  1
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2    (BIT(2))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2_S  2
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3    (BIT(3))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3_S  3
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4    (BIT(4))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4_S  4
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5    (BIT(5))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5_S  5
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6    (BIT(6))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6_S  6
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7    (BIT(7))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7_S  7
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8    (BIT(8))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8_S  8
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9    (BIT(9))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9_S  9
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10    (BIT(10))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10_S  10
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11    (BIT(11))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11_S  11
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12    (BIT(12))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12_S  12
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13    (BIT(13))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13_S  13
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14    (BIT(14))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14_S  14
+/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15    (BIT(15))
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15_M  (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15_S)
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15_S  15
+
+/** CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x288)
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0    (BIT(0))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0_S  0
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1    (BIT(1))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1_S  1
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2    (BIT(2))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2_S  2
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3    (BIT(3))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3_S  3
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4    (BIT(4))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4_S  4
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5    (BIT(5))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5_S  5
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6    (BIT(6))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6_S  6
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7    (BIT(7))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7_S  7
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8    (BIT(8))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8_S  8
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9    (BIT(9))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9_S  9
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10    (BIT(10))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10_S  10
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11    (BIT(11))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11_S  11
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12    (BIT(12))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12_S  12
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13    (BIT(13))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13_S  13
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14    (BIT(14))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14_S  14
+/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15    (BIT(15))
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15_M  (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15_S)
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15_S  15
+
+/** CSI_HOST_INT_ST_SEQ_FRAME_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_ST_SEQ_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x290)
+/** CSI_HOST_ST_ERR_F_SEQ_VC0 : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC0    (BIT(0))
+#define CSI_HOST_ST_ERR_F_SEQ_VC0_M  (CSI_HOST_ST_ERR_F_SEQ_VC0_V << CSI_HOST_ST_ERR_F_SEQ_VC0_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC0_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC0_S  0
+/** CSI_HOST_ST_ERR_F_SEQ_VC1 : RC; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC1    (BIT(1))
+#define CSI_HOST_ST_ERR_F_SEQ_VC1_M  (CSI_HOST_ST_ERR_F_SEQ_VC1_V << CSI_HOST_ST_ERR_F_SEQ_VC1_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC1_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC1_S  1
+/** CSI_HOST_ST_ERR_F_SEQ_VC2 : RC; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC2    (BIT(2))
+#define CSI_HOST_ST_ERR_F_SEQ_VC2_M  (CSI_HOST_ST_ERR_F_SEQ_VC2_V << CSI_HOST_ST_ERR_F_SEQ_VC2_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC2_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC2_S  2
+/** CSI_HOST_ST_ERR_F_SEQ_VC3 : RC; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC3    (BIT(3))
+#define CSI_HOST_ST_ERR_F_SEQ_VC3_M  (CSI_HOST_ST_ERR_F_SEQ_VC3_V << CSI_HOST_ST_ERR_F_SEQ_VC3_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC3_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC3_S  3
+/** CSI_HOST_ST_ERR_F_SEQ_VC4 : RC; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC4    (BIT(4))
+#define CSI_HOST_ST_ERR_F_SEQ_VC4_M  (CSI_HOST_ST_ERR_F_SEQ_VC4_V << CSI_HOST_ST_ERR_F_SEQ_VC4_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC4_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC4_S  4
+/** CSI_HOST_ST_ERR_F_SEQ_VC5 : RC; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC5    (BIT(5))
+#define CSI_HOST_ST_ERR_F_SEQ_VC5_M  (CSI_HOST_ST_ERR_F_SEQ_VC5_V << CSI_HOST_ST_ERR_F_SEQ_VC5_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC5_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC5_S  5
+/** CSI_HOST_ST_ERR_F_SEQ_VC6 : RC; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC6    (BIT(6))
+#define CSI_HOST_ST_ERR_F_SEQ_VC6_M  (CSI_HOST_ST_ERR_F_SEQ_VC6_V << CSI_HOST_ST_ERR_F_SEQ_VC6_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC6_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC6_S  6
+/** CSI_HOST_ST_ERR_F_SEQ_VC7 : RC; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC7    (BIT(7))
+#define CSI_HOST_ST_ERR_F_SEQ_VC7_M  (CSI_HOST_ST_ERR_F_SEQ_VC7_V << CSI_HOST_ST_ERR_F_SEQ_VC7_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC7_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC7_S  7
+/** CSI_HOST_ST_ERR_F_SEQ_VC8 : RC; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC8    (BIT(8))
+#define CSI_HOST_ST_ERR_F_SEQ_VC8_M  (CSI_HOST_ST_ERR_F_SEQ_VC8_V << CSI_HOST_ST_ERR_F_SEQ_VC8_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC8_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC8_S  8
+/** CSI_HOST_ST_ERR_F_SEQ_VC9 : RC; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC9    (BIT(9))
+#define CSI_HOST_ST_ERR_F_SEQ_VC9_M  (CSI_HOST_ST_ERR_F_SEQ_VC9_V << CSI_HOST_ST_ERR_F_SEQ_VC9_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC9_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC9_S  9
+/** CSI_HOST_ST_ERR_F_SEQ_VC10 : RC; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC10    (BIT(10))
+#define CSI_HOST_ST_ERR_F_SEQ_VC10_M  (CSI_HOST_ST_ERR_F_SEQ_VC10_V << CSI_HOST_ST_ERR_F_SEQ_VC10_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC10_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC10_S  10
+/** CSI_HOST_ST_ERR_F_SEQ_VC11 : RC; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC11    (BIT(11))
+#define CSI_HOST_ST_ERR_F_SEQ_VC11_M  (CSI_HOST_ST_ERR_F_SEQ_VC11_V << CSI_HOST_ST_ERR_F_SEQ_VC11_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC11_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC11_S  11
+/** CSI_HOST_ST_ERR_F_SEQ_VC12 : RC; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC12    (BIT(12))
+#define CSI_HOST_ST_ERR_F_SEQ_VC12_M  (CSI_HOST_ST_ERR_F_SEQ_VC12_V << CSI_HOST_ST_ERR_F_SEQ_VC12_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC12_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC12_S  12
+/** CSI_HOST_ST_ERR_F_SEQ_VC13 : RC; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC13    (BIT(13))
+#define CSI_HOST_ST_ERR_F_SEQ_VC13_M  (CSI_HOST_ST_ERR_F_SEQ_VC13_V << CSI_HOST_ST_ERR_F_SEQ_VC13_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC13_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC13_S  13
+/** CSI_HOST_ST_ERR_F_SEQ_VC14 : RC; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC14    (BIT(14))
+#define CSI_HOST_ST_ERR_F_SEQ_VC14_M  (CSI_HOST_ST_ERR_F_SEQ_VC14_V << CSI_HOST_ST_ERR_F_SEQ_VC14_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC14_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC14_S  14
+/** CSI_HOST_ST_ERR_F_SEQ_VC15 : RC; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_F_SEQ_VC15    (BIT(15))
+#define CSI_HOST_ST_ERR_F_SEQ_VC15_M  (CSI_HOST_ST_ERR_F_SEQ_VC15_V << CSI_HOST_ST_ERR_F_SEQ_VC15_S)
+#define CSI_HOST_ST_ERR_F_SEQ_VC15_V  0x00000001U
+#define CSI_HOST_ST_ERR_F_SEQ_VC15_S  15
+
+/** CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x294)
+/** CSI_HOST_MASK_ERR_F_SEQ_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC0    (BIT(0))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC0_M  (CSI_HOST_MASK_ERR_F_SEQ_VC0_V << CSI_HOST_MASK_ERR_F_SEQ_VC0_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC0_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC0_S  0
+/** CSI_HOST_MASK_ERR_F_SEQ_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC1    (BIT(1))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC1_M  (CSI_HOST_MASK_ERR_F_SEQ_VC1_V << CSI_HOST_MASK_ERR_F_SEQ_VC1_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC1_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC1_S  1
+/** CSI_HOST_MASK_ERR_F_SEQ_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC2    (BIT(2))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC2_M  (CSI_HOST_MASK_ERR_F_SEQ_VC2_V << CSI_HOST_MASK_ERR_F_SEQ_VC2_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC2_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC2_S  2
+/** CSI_HOST_MASK_ERR_F_SEQ_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC3    (BIT(3))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC3_M  (CSI_HOST_MASK_ERR_F_SEQ_VC3_V << CSI_HOST_MASK_ERR_F_SEQ_VC3_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC3_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC3_S  3
+/** CSI_HOST_MASK_ERR_F_SEQ_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC4    (BIT(4))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC4_M  (CSI_HOST_MASK_ERR_F_SEQ_VC4_V << CSI_HOST_MASK_ERR_F_SEQ_VC4_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC4_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC4_S  4
+/** CSI_HOST_MASK_ERR_F_SEQ_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC5    (BIT(5))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC5_M  (CSI_HOST_MASK_ERR_F_SEQ_VC5_V << CSI_HOST_MASK_ERR_F_SEQ_VC5_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC5_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC5_S  5
+/** CSI_HOST_MASK_ERR_F_SEQ_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC6    (BIT(6))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC6_M  (CSI_HOST_MASK_ERR_F_SEQ_VC6_V << CSI_HOST_MASK_ERR_F_SEQ_VC6_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC6_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC6_S  6
+/** CSI_HOST_MASK_ERR_F_SEQ_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC7    (BIT(7))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC7_M  (CSI_HOST_MASK_ERR_F_SEQ_VC7_V << CSI_HOST_MASK_ERR_F_SEQ_VC7_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC7_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC7_S  7
+/** CSI_HOST_MASK_ERR_F_SEQ_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC8    (BIT(8))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC8_M  (CSI_HOST_MASK_ERR_F_SEQ_VC8_V << CSI_HOST_MASK_ERR_F_SEQ_VC8_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC8_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC8_S  8
+/** CSI_HOST_MASK_ERR_F_SEQ_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC9    (BIT(9))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC9_M  (CSI_HOST_MASK_ERR_F_SEQ_VC9_V << CSI_HOST_MASK_ERR_F_SEQ_VC9_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC9_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC9_S  9
+/** CSI_HOST_MASK_ERR_F_SEQ_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC10    (BIT(10))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC10_M  (CSI_HOST_MASK_ERR_F_SEQ_VC10_V << CSI_HOST_MASK_ERR_F_SEQ_VC10_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC10_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC10_S  10
+/** CSI_HOST_MASK_ERR_F_SEQ_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC11    (BIT(11))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC11_M  (CSI_HOST_MASK_ERR_F_SEQ_VC11_V << CSI_HOST_MASK_ERR_F_SEQ_VC11_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC11_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC11_S  11
+/** CSI_HOST_MASK_ERR_F_SEQ_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC12    (BIT(12))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC12_M  (CSI_HOST_MASK_ERR_F_SEQ_VC12_V << CSI_HOST_MASK_ERR_F_SEQ_VC12_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC12_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC12_S  12
+/** CSI_HOST_MASK_ERR_F_SEQ_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC13    (BIT(13))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC13_M  (CSI_HOST_MASK_ERR_F_SEQ_VC13_V << CSI_HOST_MASK_ERR_F_SEQ_VC13_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC13_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC13_S  13
+/** CSI_HOST_MASK_ERR_F_SEQ_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC14    (BIT(14))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC14_M  (CSI_HOST_MASK_ERR_F_SEQ_VC14_V << CSI_HOST_MASK_ERR_F_SEQ_VC14_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC14_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC14_S  14
+/** CSI_HOST_MASK_ERR_F_SEQ_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_F_SEQ_VC15    (BIT(15))
+#define CSI_HOST_MASK_ERR_F_SEQ_VC15_M  (CSI_HOST_MASK_ERR_F_SEQ_VC15_V << CSI_HOST_MASK_ERR_F_SEQ_VC15_S)
+#define CSI_HOST_MASK_ERR_F_SEQ_VC15_V  0x00000001U
+#define CSI_HOST_MASK_ERR_F_SEQ_VC15_S  15
+
+/** CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x298)
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC0    (BIT(0))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC0_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC0_V << CSI_HOST_FORCE_ERR_F_SEQ_VC0_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC0_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC0_S  0
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC1    (BIT(1))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC1_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC1_V << CSI_HOST_FORCE_ERR_F_SEQ_VC1_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC1_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC1_S  1
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC2    (BIT(2))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC2_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC2_V << CSI_HOST_FORCE_ERR_F_SEQ_VC2_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC2_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC2_S  2
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC3    (BIT(3))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC3_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC3_V << CSI_HOST_FORCE_ERR_F_SEQ_VC3_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC3_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC3_S  3
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC4    (BIT(4))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC4_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC4_V << CSI_HOST_FORCE_ERR_F_SEQ_VC4_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC4_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC4_S  4
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC5    (BIT(5))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC5_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC5_V << CSI_HOST_FORCE_ERR_F_SEQ_VC5_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC5_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC5_S  5
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC6    (BIT(6))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC6_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC6_V << CSI_HOST_FORCE_ERR_F_SEQ_VC6_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC6_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC6_S  6
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC7    (BIT(7))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC7_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC7_V << CSI_HOST_FORCE_ERR_F_SEQ_VC7_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC7_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC7_S  7
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC8    (BIT(8))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC8_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC8_V << CSI_HOST_FORCE_ERR_F_SEQ_VC8_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC8_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC8_S  8
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC9    (BIT(9))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC9_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC9_V << CSI_HOST_FORCE_ERR_F_SEQ_VC9_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC9_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC9_S  9
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC10    (BIT(10))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC10_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC10_V << CSI_HOST_FORCE_ERR_F_SEQ_VC10_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC10_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC10_S  10
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC11    (BIT(11))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC11_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC11_V << CSI_HOST_FORCE_ERR_F_SEQ_VC11_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC11_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC11_S  11
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC12    (BIT(12))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC12_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC12_V << CSI_HOST_FORCE_ERR_F_SEQ_VC12_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC12_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC12_S  12
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC13    (BIT(13))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC13_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC13_V << CSI_HOST_FORCE_ERR_F_SEQ_VC13_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC13_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC13_S  13
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC14    (BIT(14))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC14_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC14_V << CSI_HOST_FORCE_ERR_F_SEQ_VC14_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC14_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC14_S  14
+/** CSI_HOST_FORCE_ERR_F_SEQ_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC15    (BIT(15))
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC15_M  (CSI_HOST_FORCE_ERR_F_SEQ_VC15_V << CSI_HOST_FORCE_ERR_F_SEQ_VC15_S)
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC15_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_F_SEQ_VC15_S  15
+
+/** CSI_HOST_INT_ST_CRC_FRAME_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_ST_CRC_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2a0)
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC0 : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC0    (BIT(0))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC0_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC0_V << CSI_HOST_ST_ERR_FRAME_DATA_VC0_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC0_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC0_S  0
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC1 : RC; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC1    (BIT(1))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC1_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC1_V << CSI_HOST_ST_ERR_FRAME_DATA_VC1_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC1_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC1_S  1
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC2 : RC; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC2    (BIT(2))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC2_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC2_V << CSI_HOST_ST_ERR_FRAME_DATA_VC2_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC2_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC2_S  2
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC3 : RC; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC3    (BIT(3))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC3_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC3_V << CSI_HOST_ST_ERR_FRAME_DATA_VC3_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC3_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC3_S  3
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC4 : RC; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC4    (BIT(4))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC4_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC4_V << CSI_HOST_ST_ERR_FRAME_DATA_VC4_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC4_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC4_S  4
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC5 : RC; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC5    (BIT(5))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC5_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC5_V << CSI_HOST_ST_ERR_FRAME_DATA_VC5_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC5_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC5_S  5
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC6 : RC; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC6    (BIT(6))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC6_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC6_V << CSI_HOST_ST_ERR_FRAME_DATA_VC6_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC6_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC6_S  6
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC7 : RC; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC7    (BIT(7))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC7_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC7_V << CSI_HOST_ST_ERR_FRAME_DATA_VC7_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC7_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC7_S  7
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC8 : RC; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC8    (BIT(8))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC8_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC8_V << CSI_HOST_ST_ERR_FRAME_DATA_VC8_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC8_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC8_S  8
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC9 : RC; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC9    (BIT(9))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC9_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC9_V << CSI_HOST_ST_ERR_FRAME_DATA_VC9_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC9_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC9_S  9
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC10 : RC; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC10    (BIT(10))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC10_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC10_V << CSI_HOST_ST_ERR_FRAME_DATA_VC10_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC10_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC10_S  10
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC11 : RC; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC11    (BIT(11))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC11_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC11_V << CSI_HOST_ST_ERR_FRAME_DATA_VC11_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC11_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC11_S  11
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC12 : RC; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC12    (BIT(12))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC12_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC12_V << CSI_HOST_ST_ERR_FRAME_DATA_VC12_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC12_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC12_S  12
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC13 : RC; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC13    (BIT(13))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC13_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC13_V << CSI_HOST_ST_ERR_FRAME_DATA_VC13_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC13_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC13_S  13
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC14 : RC; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC14    (BIT(14))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC14_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC14_V << CSI_HOST_ST_ERR_FRAME_DATA_VC14_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC14_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC14_S  14
+/** CSI_HOST_ST_ERR_FRAME_DATA_VC15 : RC; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC15    (BIT(15))
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC15_M  (CSI_HOST_ST_ERR_FRAME_DATA_VC15_V << CSI_HOST_ST_ERR_FRAME_DATA_VC15_S)
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC15_V  0x00000001U
+#define CSI_HOST_ST_ERR_FRAME_DATA_VC15_S  15
+
+/** CSI_HOST_INT_MSK_CRC_FRAME_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_MSK_CRC_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2a4)
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC0    (BIT(0))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC0_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC0_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC0_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC0_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC0_S  0
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC1    (BIT(1))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC1_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC1_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC1_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC1_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC1_S  1
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC2    (BIT(2))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC2_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC2_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC2_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC2_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC2_S  2
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC3    (BIT(3))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC3_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC3_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC3_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC3_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC3_S  3
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC4    (BIT(4))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC4_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC4_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC4_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC4_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC4_S  4
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC5    (BIT(5))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC5_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC5_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC5_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC5_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC5_S  5
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC6    (BIT(6))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC6_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC6_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC6_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC6_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC6_S  6
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC7    (BIT(7))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC7_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC7_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC7_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC7_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC7_S  7
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC8    (BIT(8))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC8_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC8_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC8_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC8_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC8_S  8
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC9    (BIT(9))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC9_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC9_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC9_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC9_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC9_S  9
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC10    (BIT(10))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC10_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC10_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC10_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC10_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC10_S  10
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC11    (BIT(11))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC11_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC11_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC11_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC11_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC11_S  11
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC12    (BIT(12))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC12_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC12_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC12_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC12_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC12_S  12
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC13    (BIT(13))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC13_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC13_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC13_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC13_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC13_S  13
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC14    (BIT(14))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC14_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC14_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC14_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC14_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC14_S  14
+/** CSI_HOST_MASK_ERR_FRAME_DATA_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC15    (BIT(15))
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC15_M  (CSI_HOST_MASK_ERR_FRAME_DATA_VC15_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC15_S)
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC15_V  0x00000001U
+#define CSI_HOST_MASK_ERR_FRAME_DATA_VC15_S  15
+
+/** CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2a8)
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC0    (BIT(0))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC0_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC0_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC0_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC0_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC0_S  0
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC1    (BIT(1))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC1_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC1_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC1_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC1_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC1_S  1
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC2    (BIT(2))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC2_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC2_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC2_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC2_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC2_S  2
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC3    (BIT(3))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC3_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC3_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC3_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC3_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC3_S  3
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC4    (BIT(4))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC4_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC4_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC4_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC4_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC4_S  4
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC5    (BIT(5))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC5_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC5_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC5_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC5_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC5_S  5
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC6    (BIT(6))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC6_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC6_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC6_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC6_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC6_S  6
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC7    (BIT(7))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC7_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC7_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC7_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC7_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC7_S  7
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC8    (BIT(8))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC8_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC8_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC8_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC8_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC8_S  8
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC9    (BIT(9))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC9_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC9_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC9_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC9_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC9_S  9
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC10    (BIT(10))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC10_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC10_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC10_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC10_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC10_S  10
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC11    (BIT(11))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC11_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC11_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC11_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC11_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC11_S  11
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC12    (BIT(12))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC12_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC12_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC12_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC12_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC12_S  12
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC13    (BIT(13))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC13_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC13_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC13_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC13_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC13_S  13
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC14    (BIT(14))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC14_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC14_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC14_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC14_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC14_S  14
+/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC15    (BIT(15))
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC15_M  (CSI_HOST_FORCE_ERR_FRAME_DATA_VC15_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC15_S)
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC15_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC15_S  15
+
+/** CSI_HOST_INT_ST_PLD_CRC_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_ST_PLD_CRC_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2b0)
+/** CSI_HOST_ST_ERR_CRC_VC0 : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC0    (BIT(0))
+#define CSI_HOST_ST_ERR_CRC_VC0_M  (CSI_HOST_ST_ERR_CRC_VC0_V << CSI_HOST_ST_ERR_CRC_VC0_S)
+#define CSI_HOST_ST_ERR_CRC_VC0_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC0_S  0
+/** CSI_HOST_ST_ERR_CRC_VC1 : RC; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC1    (BIT(1))
+#define CSI_HOST_ST_ERR_CRC_VC1_M  (CSI_HOST_ST_ERR_CRC_VC1_V << CSI_HOST_ST_ERR_CRC_VC1_S)
+#define CSI_HOST_ST_ERR_CRC_VC1_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC1_S  1
+/** CSI_HOST_ST_ERR_CRC_VC2 : RC; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC2    (BIT(2))
+#define CSI_HOST_ST_ERR_CRC_VC2_M  (CSI_HOST_ST_ERR_CRC_VC2_V << CSI_HOST_ST_ERR_CRC_VC2_S)
+#define CSI_HOST_ST_ERR_CRC_VC2_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC2_S  2
+/** CSI_HOST_ST_ERR_CRC_VC3 : RC; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC3    (BIT(3))
+#define CSI_HOST_ST_ERR_CRC_VC3_M  (CSI_HOST_ST_ERR_CRC_VC3_V << CSI_HOST_ST_ERR_CRC_VC3_S)
+#define CSI_HOST_ST_ERR_CRC_VC3_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC3_S  3
+/** CSI_HOST_ST_ERR_CRC_VC4 : RC; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC4    (BIT(4))
+#define CSI_HOST_ST_ERR_CRC_VC4_M  (CSI_HOST_ST_ERR_CRC_VC4_V << CSI_HOST_ST_ERR_CRC_VC4_S)
+#define CSI_HOST_ST_ERR_CRC_VC4_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC4_S  4
+/** CSI_HOST_ST_ERR_CRC_VC5 : RC; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC5    (BIT(5))
+#define CSI_HOST_ST_ERR_CRC_VC5_M  (CSI_HOST_ST_ERR_CRC_VC5_V << CSI_HOST_ST_ERR_CRC_VC5_S)
+#define CSI_HOST_ST_ERR_CRC_VC5_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC5_S  5
+/** CSI_HOST_ST_ERR_CRC_VC6 : RC; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC6    (BIT(6))
+#define CSI_HOST_ST_ERR_CRC_VC6_M  (CSI_HOST_ST_ERR_CRC_VC6_V << CSI_HOST_ST_ERR_CRC_VC6_S)
+#define CSI_HOST_ST_ERR_CRC_VC6_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC6_S  6
+/** CSI_HOST_ST_ERR_CRC_VC7 : RC; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC7    (BIT(7))
+#define CSI_HOST_ST_ERR_CRC_VC7_M  (CSI_HOST_ST_ERR_CRC_VC7_V << CSI_HOST_ST_ERR_CRC_VC7_S)
+#define CSI_HOST_ST_ERR_CRC_VC7_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC7_S  7
+/** CSI_HOST_ST_ERR_CRC_VC8 : RC; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC8    (BIT(8))
+#define CSI_HOST_ST_ERR_CRC_VC8_M  (CSI_HOST_ST_ERR_CRC_VC8_V << CSI_HOST_ST_ERR_CRC_VC8_S)
+#define CSI_HOST_ST_ERR_CRC_VC8_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC8_S  8
+/** CSI_HOST_ST_ERR_CRC_VC9 : RC; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC9    (BIT(9))
+#define CSI_HOST_ST_ERR_CRC_VC9_M  (CSI_HOST_ST_ERR_CRC_VC9_V << CSI_HOST_ST_ERR_CRC_VC9_S)
+#define CSI_HOST_ST_ERR_CRC_VC9_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC9_S  9
+/** CSI_HOST_ST_ERR_CRC_VC10 : RC; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC10    (BIT(10))
+#define CSI_HOST_ST_ERR_CRC_VC10_M  (CSI_HOST_ST_ERR_CRC_VC10_V << CSI_HOST_ST_ERR_CRC_VC10_S)
+#define CSI_HOST_ST_ERR_CRC_VC10_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC10_S  10
+/** CSI_HOST_ST_ERR_CRC_VC11 : RC; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC11    (BIT(11))
+#define CSI_HOST_ST_ERR_CRC_VC11_M  (CSI_HOST_ST_ERR_CRC_VC11_V << CSI_HOST_ST_ERR_CRC_VC11_S)
+#define CSI_HOST_ST_ERR_CRC_VC11_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC11_S  11
+/** CSI_HOST_ST_ERR_CRC_VC12 : RC; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC12    (BIT(12))
+#define CSI_HOST_ST_ERR_CRC_VC12_M  (CSI_HOST_ST_ERR_CRC_VC12_V << CSI_HOST_ST_ERR_CRC_VC12_S)
+#define CSI_HOST_ST_ERR_CRC_VC12_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC12_S  12
+/** CSI_HOST_ST_ERR_CRC_VC13 : RC; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC13    (BIT(13))
+#define CSI_HOST_ST_ERR_CRC_VC13_M  (CSI_HOST_ST_ERR_CRC_VC13_V << CSI_HOST_ST_ERR_CRC_VC13_S)
+#define CSI_HOST_ST_ERR_CRC_VC13_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC13_S  13
+/** CSI_HOST_ST_ERR_CRC_VC14 : RC; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC14    (BIT(14))
+#define CSI_HOST_ST_ERR_CRC_VC14_M  (CSI_HOST_ST_ERR_CRC_VC14_V << CSI_HOST_ST_ERR_CRC_VC14_S)
+#define CSI_HOST_ST_ERR_CRC_VC14_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC14_S  14
+/** CSI_HOST_ST_ERR_CRC_VC15 : RC; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_CRC_VC15    (BIT(15))
+#define CSI_HOST_ST_ERR_CRC_VC15_M  (CSI_HOST_ST_ERR_CRC_VC15_V << CSI_HOST_ST_ERR_CRC_VC15_S)
+#define CSI_HOST_ST_ERR_CRC_VC15_V  0x00000001U
+#define CSI_HOST_ST_ERR_CRC_VC15_S  15
+
+/** CSI_HOST_INT_MSK_PLD_CRC_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_MSK_PLD_CRC_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2b4)
+/** CSI_HOST_MASK_ERR_CRC_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC0    (BIT(0))
+#define CSI_HOST_MASK_ERR_CRC_VC0_M  (CSI_HOST_MASK_ERR_CRC_VC0_V << CSI_HOST_MASK_ERR_CRC_VC0_S)
+#define CSI_HOST_MASK_ERR_CRC_VC0_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC0_S  0
+/** CSI_HOST_MASK_ERR_CRC_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC1    (BIT(1))
+#define CSI_HOST_MASK_ERR_CRC_VC1_M  (CSI_HOST_MASK_ERR_CRC_VC1_V << CSI_HOST_MASK_ERR_CRC_VC1_S)
+#define CSI_HOST_MASK_ERR_CRC_VC1_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC1_S  1
+/** CSI_HOST_MASK_ERR_CRC_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC2    (BIT(2))
+#define CSI_HOST_MASK_ERR_CRC_VC2_M  (CSI_HOST_MASK_ERR_CRC_VC2_V << CSI_HOST_MASK_ERR_CRC_VC2_S)
+#define CSI_HOST_MASK_ERR_CRC_VC2_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC2_S  2
+/** CSI_HOST_MASK_ERR_CRC_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC3    (BIT(3))
+#define CSI_HOST_MASK_ERR_CRC_VC3_M  (CSI_HOST_MASK_ERR_CRC_VC3_V << CSI_HOST_MASK_ERR_CRC_VC3_S)
+#define CSI_HOST_MASK_ERR_CRC_VC3_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC3_S  3
+/** CSI_HOST_MASK_ERR_CRC_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC4    (BIT(4))
+#define CSI_HOST_MASK_ERR_CRC_VC4_M  (CSI_HOST_MASK_ERR_CRC_VC4_V << CSI_HOST_MASK_ERR_CRC_VC4_S)
+#define CSI_HOST_MASK_ERR_CRC_VC4_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC4_S  4
+/** CSI_HOST_MASK_ERR_CRC_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC5    (BIT(5))
+#define CSI_HOST_MASK_ERR_CRC_VC5_M  (CSI_HOST_MASK_ERR_CRC_VC5_V << CSI_HOST_MASK_ERR_CRC_VC5_S)
+#define CSI_HOST_MASK_ERR_CRC_VC5_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC5_S  5
+/** CSI_HOST_MASK_ERR_CRC_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC6    (BIT(6))
+#define CSI_HOST_MASK_ERR_CRC_VC6_M  (CSI_HOST_MASK_ERR_CRC_VC6_V << CSI_HOST_MASK_ERR_CRC_VC6_S)
+#define CSI_HOST_MASK_ERR_CRC_VC6_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC6_S  6
+/** CSI_HOST_MASK_ERR_CRC_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC7    (BIT(7))
+#define CSI_HOST_MASK_ERR_CRC_VC7_M  (CSI_HOST_MASK_ERR_CRC_VC7_V << CSI_HOST_MASK_ERR_CRC_VC7_S)
+#define CSI_HOST_MASK_ERR_CRC_VC7_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC7_S  7
+/** CSI_HOST_MASK_ERR_CRC_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC8    (BIT(8))
+#define CSI_HOST_MASK_ERR_CRC_VC8_M  (CSI_HOST_MASK_ERR_CRC_VC8_V << CSI_HOST_MASK_ERR_CRC_VC8_S)
+#define CSI_HOST_MASK_ERR_CRC_VC8_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC8_S  8
+/** CSI_HOST_MASK_ERR_CRC_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC9    (BIT(9))
+#define CSI_HOST_MASK_ERR_CRC_VC9_M  (CSI_HOST_MASK_ERR_CRC_VC9_V << CSI_HOST_MASK_ERR_CRC_VC9_S)
+#define CSI_HOST_MASK_ERR_CRC_VC9_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC9_S  9
+/** CSI_HOST_MASK_ERR_CRC_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC10    (BIT(10))
+#define CSI_HOST_MASK_ERR_CRC_VC10_M  (CSI_HOST_MASK_ERR_CRC_VC10_V << CSI_HOST_MASK_ERR_CRC_VC10_S)
+#define CSI_HOST_MASK_ERR_CRC_VC10_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC10_S  10
+/** CSI_HOST_MASK_ERR_CRC_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC11    (BIT(11))
+#define CSI_HOST_MASK_ERR_CRC_VC11_M  (CSI_HOST_MASK_ERR_CRC_VC11_V << CSI_HOST_MASK_ERR_CRC_VC11_S)
+#define CSI_HOST_MASK_ERR_CRC_VC11_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC11_S  11
+/** CSI_HOST_MASK_ERR_CRC_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC12    (BIT(12))
+#define CSI_HOST_MASK_ERR_CRC_VC12_M  (CSI_HOST_MASK_ERR_CRC_VC12_V << CSI_HOST_MASK_ERR_CRC_VC12_S)
+#define CSI_HOST_MASK_ERR_CRC_VC12_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC12_S  12
+/** CSI_HOST_MASK_ERR_CRC_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC13    (BIT(13))
+#define CSI_HOST_MASK_ERR_CRC_VC13_M  (CSI_HOST_MASK_ERR_CRC_VC13_V << CSI_HOST_MASK_ERR_CRC_VC13_S)
+#define CSI_HOST_MASK_ERR_CRC_VC13_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC13_S  13
+/** CSI_HOST_MASK_ERR_CRC_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC14    (BIT(14))
+#define CSI_HOST_MASK_ERR_CRC_VC14_M  (CSI_HOST_MASK_ERR_CRC_VC14_V << CSI_HOST_MASK_ERR_CRC_VC14_S)
+#define CSI_HOST_MASK_ERR_CRC_VC14_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC14_S  14
+/** CSI_HOST_MASK_ERR_CRC_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_CRC_VC15    (BIT(15))
+#define CSI_HOST_MASK_ERR_CRC_VC15_M  (CSI_HOST_MASK_ERR_CRC_VC15_V << CSI_HOST_MASK_ERR_CRC_VC15_S)
+#define CSI_HOST_MASK_ERR_CRC_VC15_V  0x00000001U
+#define CSI_HOST_MASK_ERR_CRC_VC15_S  15
+
+/** CSI_HOST_INT_FORCE_PLD_CRC_FATAL_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_FORCE_PLD_CRC_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2b8)
+/** CSI_HOST_FORCE_ERR_CRC_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC0    (BIT(0))
+#define CSI_HOST_FORCE_ERR_CRC_VC0_M  (CSI_HOST_FORCE_ERR_CRC_VC0_V << CSI_HOST_FORCE_ERR_CRC_VC0_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC0_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC0_S  0
+/** CSI_HOST_FORCE_ERR_CRC_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC1    (BIT(1))
+#define CSI_HOST_FORCE_ERR_CRC_VC1_M  (CSI_HOST_FORCE_ERR_CRC_VC1_V << CSI_HOST_FORCE_ERR_CRC_VC1_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC1_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC1_S  1
+/** CSI_HOST_FORCE_ERR_CRC_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC2    (BIT(2))
+#define CSI_HOST_FORCE_ERR_CRC_VC2_M  (CSI_HOST_FORCE_ERR_CRC_VC2_V << CSI_HOST_FORCE_ERR_CRC_VC2_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC2_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC2_S  2
+/** CSI_HOST_FORCE_ERR_CRC_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC3    (BIT(3))
+#define CSI_HOST_FORCE_ERR_CRC_VC3_M  (CSI_HOST_FORCE_ERR_CRC_VC3_V << CSI_HOST_FORCE_ERR_CRC_VC3_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC3_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC3_S  3
+/** CSI_HOST_FORCE_ERR_CRC_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC4    (BIT(4))
+#define CSI_HOST_FORCE_ERR_CRC_VC4_M  (CSI_HOST_FORCE_ERR_CRC_VC4_V << CSI_HOST_FORCE_ERR_CRC_VC4_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC4_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC4_S  4
+/** CSI_HOST_FORCE_ERR_CRC_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC5    (BIT(5))
+#define CSI_HOST_FORCE_ERR_CRC_VC5_M  (CSI_HOST_FORCE_ERR_CRC_VC5_V << CSI_HOST_FORCE_ERR_CRC_VC5_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC5_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC5_S  5
+/** CSI_HOST_FORCE_ERR_CRC_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC6    (BIT(6))
+#define CSI_HOST_FORCE_ERR_CRC_VC6_M  (CSI_HOST_FORCE_ERR_CRC_VC6_V << CSI_HOST_FORCE_ERR_CRC_VC6_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC6_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC6_S  6
+/** CSI_HOST_FORCE_ERR_CRC_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC7    (BIT(7))
+#define CSI_HOST_FORCE_ERR_CRC_VC7_M  (CSI_HOST_FORCE_ERR_CRC_VC7_V << CSI_HOST_FORCE_ERR_CRC_VC7_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC7_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC7_S  7
+/** CSI_HOST_FORCE_ERR_CRC_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC8    (BIT(8))
+#define CSI_HOST_FORCE_ERR_CRC_VC8_M  (CSI_HOST_FORCE_ERR_CRC_VC8_V << CSI_HOST_FORCE_ERR_CRC_VC8_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC8_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC8_S  8
+/** CSI_HOST_FORCE_ERR_CRC_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC9    (BIT(9))
+#define CSI_HOST_FORCE_ERR_CRC_VC9_M  (CSI_HOST_FORCE_ERR_CRC_VC9_V << CSI_HOST_FORCE_ERR_CRC_VC9_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC9_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC9_S  9
+/** CSI_HOST_FORCE_ERR_CRC_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC10    (BIT(10))
+#define CSI_HOST_FORCE_ERR_CRC_VC10_M  (CSI_HOST_FORCE_ERR_CRC_VC10_V << CSI_HOST_FORCE_ERR_CRC_VC10_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC10_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC10_S  10
+/** CSI_HOST_FORCE_ERR_CRC_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC11    (BIT(11))
+#define CSI_HOST_FORCE_ERR_CRC_VC11_M  (CSI_HOST_FORCE_ERR_CRC_VC11_V << CSI_HOST_FORCE_ERR_CRC_VC11_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC11_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC11_S  11
+/** CSI_HOST_FORCE_ERR_CRC_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC12    (BIT(12))
+#define CSI_HOST_FORCE_ERR_CRC_VC12_M  (CSI_HOST_FORCE_ERR_CRC_VC12_V << CSI_HOST_FORCE_ERR_CRC_VC12_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC12_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC12_S  12
+/** CSI_HOST_FORCE_ERR_CRC_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC13    (BIT(13))
+#define CSI_HOST_FORCE_ERR_CRC_VC13_M  (CSI_HOST_FORCE_ERR_CRC_VC13_V << CSI_HOST_FORCE_ERR_CRC_VC13_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC13_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC13_S  13
+/** CSI_HOST_FORCE_ERR_CRC_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC14    (BIT(14))
+#define CSI_HOST_FORCE_ERR_CRC_VC14_M  (CSI_HOST_FORCE_ERR_CRC_VC14_V << CSI_HOST_FORCE_ERR_CRC_VC14_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC14_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC14_S  14
+/** CSI_HOST_FORCE_ERR_CRC_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_CRC_VC15    (BIT(15))
+#define CSI_HOST_FORCE_ERR_CRC_VC15_M  (CSI_HOST_FORCE_ERR_CRC_VC15_V << CSI_HOST_FORCE_ERR_CRC_VC15_S)
+#define CSI_HOST_FORCE_ERR_CRC_VC15_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_CRC_VC15_S  15
+
+/** CSI_HOST_INT_ST_DATA_ID_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_ST_DATA_ID_REG (DR_REG_CSI_HOST_BASE + 0x2c0)
+/** CSI_HOST_ST_ERR_ID_VC0 : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC0    (BIT(0))
+#define CSI_HOST_ST_ERR_ID_VC0_M  (CSI_HOST_ST_ERR_ID_VC0_V << CSI_HOST_ST_ERR_ID_VC0_S)
+#define CSI_HOST_ST_ERR_ID_VC0_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC0_S  0
+/** CSI_HOST_ST_ERR_ID_VC1 : RC; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC1    (BIT(1))
+#define CSI_HOST_ST_ERR_ID_VC1_M  (CSI_HOST_ST_ERR_ID_VC1_V << CSI_HOST_ST_ERR_ID_VC1_S)
+#define CSI_HOST_ST_ERR_ID_VC1_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC1_S  1
+/** CSI_HOST_ST_ERR_ID_VC2 : RC; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC2    (BIT(2))
+#define CSI_HOST_ST_ERR_ID_VC2_M  (CSI_HOST_ST_ERR_ID_VC2_V << CSI_HOST_ST_ERR_ID_VC2_S)
+#define CSI_HOST_ST_ERR_ID_VC2_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC2_S  2
+/** CSI_HOST_ST_ERR_ID_VC3 : RC; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC3    (BIT(3))
+#define CSI_HOST_ST_ERR_ID_VC3_M  (CSI_HOST_ST_ERR_ID_VC3_V << CSI_HOST_ST_ERR_ID_VC3_S)
+#define CSI_HOST_ST_ERR_ID_VC3_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC3_S  3
+/** CSI_HOST_ST_ERR_ID_VC4 : RC; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC4    (BIT(4))
+#define CSI_HOST_ST_ERR_ID_VC4_M  (CSI_HOST_ST_ERR_ID_VC4_V << CSI_HOST_ST_ERR_ID_VC4_S)
+#define CSI_HOST_ST_ERR_ID_VC4_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC4_S  4
+/** CSI_HOST_ST_ERR_ID_VC5 : RC; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC5    (BIT(5))
+#define CSI_HOST_ST_ERR_ID_VC5_M  (CSI_HOST_ST_ERR_ID_VC5_V << CSI_HOST_ST_ERR_ID_VC5_S)
+#define CSI_HOST_ST_ERR_ID_VC5_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC5_S  5
+/** CSI_HOST_ST_ERR_ID_VC6 : RC; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC6    (BIT(6))
+#define CSI_HOST_ST_ERR_ID_VC6_M  (CSI_HOST_ST_ERR_ID_VC6_V << CSI_HOST_ST_ERR_ID_VC6_S)
+#define CSI_HOST_ST_ERR_ID_VC6_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC6_S  6
+/** CSI_HOST_ST_ERR_ID_VC7 : RC; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC7    (BIT(7))
+#define CSI_HOST_ST_ERR_ID_VC7_M  (CSI_HOST_ST_ERR_ID_VC7_V << CSI_HOST_ST_ERR_ID_VC7_S)
+#define CSI_HOST_ST_ERR_ID_VC7_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC7_S  7
+/** CSI_HOST_ST_ERR_ID_VC8 : RC; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC8    (BIT(8))
+#define CSI_HOST_ST_ERR_ID_VC8_M  (CSI_HOST_ST_ERR_ID_VC8_V << CSI_HOST_ST_ERR_ID_VC8_S)
+#define CSI_HOST_ST_ERR_ID_VC8_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC8_S  8
+/** CSI_HOST_ST_ERR_ID_VC9 : RC; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC9    (BIT(9))
+#define CSI_HOST_ST_ERR_ID_VC9_M  (CSI_HOST_ST_ERR_ID_VC9_V << CSI_HOST_ST_ERR_ID_VC9_S)
+#define CSI_HOST_ST_ERR_ID_VC9_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC9_S  9
+/** CSI_HOST_ST_ERR_ID_VC10 : RC; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC10    (BIT(10))
+#define CSI_HOST_ST_ERR_ID_VC10_M  (CSI_HOST_ST_ERR_ID_VC10_V << CSI_HOST_ST_ERR_ID_VC10_S)
+#define CSI_HOST_ST_ERR_ID_VC10_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC10_S  10
+/** CSI_HOST_ST_ERR_ID_VC11 : RC; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC11    (BIT(11))
+#define CSI_HOST_ST_ERR_ID_VC11_M  (CSI_HOST_ST_ERR_ID_VC11_V << CSI_HOST_ST_ERR_ID_VC11_S)
+#define CSI_HOST_ST_ERR_ID_VC11_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC11_S  11
+/** CSI_HOST_ST_ERR_ID_VC12 : RC; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC12    (BIT(12))
+#define CSI_HOST_ST_ERR_ID_VC12_M  (CSI_HOST_ST_ERR_ID_VC12_V << CSI_HOST_ST_ERR_ID_VC12_S)
+#define CSI_HOST_ST_ERR_ID_VC12_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC12_S  12
+/** CSI_HOST_ST_ERR_ID_VC13 : RC; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC13    (BIT(13))
+#define CSI_HOST_ST_ERR_ID_VC13_M  (CSI_HOST_ST_ERR_ID_VC13_V << CSI_HOST_ST_ERR_ID_VC13_S)
+#define CSI_HOST_ST_ERR_ID_VC13_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC13_S  13
+/** CSI_HOST_ST_ERR_ID_VC14 : RC; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC14    (BIT(14))
+#define CSI_HOST_ST_ERR_ID_VC14_M  (CSI_HOST_ST_ERR_ID_VC14_V << CSI_HOST_ST_ERR_ID_VC14_S)
+#define CSI_HOST_ST_ERR_ID_VC14_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC14_S  14
+/** CSI_HOST_ST_ERR_ID_VC15 : RC; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ID_VC15    (BIT(15))
+#define CSI_HOST_ST_ERR_ID_VC15_M  (CSI_HOST_ST_ERR_ID_VC15_V << CSI_HOST_ST_ERR_ID_VC15_S)
+#define CSI_HOST_ST_ERR_ID_VC15_V  0x00000001U
+#define CSI_HOST_ST_ERR_ID_VC15_S  15
+
+/** CSI_HOST_INT_MSK_DATA_ID_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_MSK_DATA_ID_REG (DR_REG_CSI_HOST_BASE + 0x2c4)
+/** CSI_HOST_MASK_ERR_ID_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC0    (BIT(0))
+#define CSI_HOST_MASK_ERR_ID_VC0_M  (CSI_HOST_MASK_ERR_ID_VC0_V << CSI_HOST_MASK_ERR_ID_VC0_S)
+#define CSI_HOST_MASK_ERR_ID_VC0_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC0_S  0
+/** CSI_HOST_MASK_ERR_ID_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC1    (BIT(1))
+#define CSI_HOST_MASK_ERR_ID_VC1_M  (CSI_HOST_MASK_ERR_ID_VC1_V << CSI_HOST_MASK_ERR_ID_VC1_S)
+#define CSI_HOST_MASK_ERR_ID_VC1_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC1_S  1
+/** CSI_HOST_MASK_ERR_ID_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC2    (BIT(2))
+#define CSI_HOST_MASK_ERR_ID_VC2_M  (CSI_HOST_MASK_ERR_ID_VC2_V << CSI_HOST_MASK_ERR_ID_VC2_S)
+#define CSI_HOST_MASK_ERR_ID_VC2_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC2_S  2
+/** CSI_HOST_MASK_ERR_ID_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC3    (BIT(3))
+#define CSI_HOST_MASK_ERR_ID_VC3_M  (CSI_HOST_MASK_ERR_ID_VC3_V << CSI_HOST_MASK_ERR_ID_VC3_S)
+#define CSI_HOST_MASK_ERR_ID_VC3_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC3_S  3
+/** CSI_HOST_MASK_ERR_ID_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC4    (BIT(4))
+#define CSI_HOST_MASK_ERR_ID_VC4_M  (CSI_HOST_MASK_ERR_ID_VC4_V << CSI_HOST_MASK_ERR_ID_VC4_S)
+#define CSI_HOST_MASK_ERR_ID_VC4_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC4_S  4
+/** CSI_HOST_MASK_ERR_ID_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC5    (BIT(5))
+#define CSI_HOST_MASK_ERR_ID_VC5_M  (CSI_HOST_MASK_ERR_ID_VC5_V << CSI_HOST_MASK_ERR_ID_VC5_S)
+#define CSI_HOST_MASK_ERR_ID_VC5_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC5_S  5
+/** CSI_HOST_MASK_ERR_ID_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC6    (BIT(6))
+#define CSI_HOST_MASK_ERR_ID_VC6_M  (CSI_HOST_MASK_ERR_ID_VC6_V << CSI_HOST_MASK_ERR_ID_VC6_S)
+#define CSI_HOST_MASK_ERR_ID_VC6_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC6_S  6
+/** CSI_HOST_MASK_ERR_ID_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC7    (BIT(7))
+#define CSI_HOST_MASK_ERR_ID_VC7_M  (CSI_HOST_MASK_ERR_ID_VC7_V << CSI_HOST_MASK_ERR_ID_VC7_S)
+#define CSI_HOST_MASK_ERR_ID_VC7_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC7_S  7
+/** CSI_HOST_MASK_ERR_ID_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC8    (BIT(8))
+#define CSI_HOST_MASK_ERR_ID_VC8_M  (CSI_HOST_MASK_ERR_ID_VC8_V << CSI_HOST_MASK_ERR_ID_VC8_S)
+#define CSI_HOST_MASK_ERR_ID_VC8_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC8_S  8
+/** CSI_HOST_MASK_ERR_ID_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC9    (BIT(9))
+#define CSI_HOST_MASK_ERR_ID_VC9_M  (CSI_HOST_MASK_ERR_ID_VC9_V << CSI_HOST_MASK_ERR_ID_VC9_S)
+#define CSI_HOST_MASK_ERR_ID_VC9_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC9_S  9
+/** CSI_HOST_MASK_ERR_ID_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC10    (BIT(10))
+#define CSI_HOST_MASK_ERR_ID_VC10_M  (CSI_HOST_MASK_ERR_ID_VC10_V << CSI_HOST_MASK_ERR_ID_VC10_S)
+#define CSI_HOST_MASK_ERR_ID_VC10_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC10_S  10
+/** CSI_HOST_MASK_ERR_ID_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC11    (BIT(11))
+#define CSI_HOST_MASK_ERR_ID_VC11_M  (CSI_HOST_MASK_ERR_ID_VC11_V << CSI_HOST_MASK_ERR_ID_VC11_S)
+#define CSI_HOST_MASK_ERR_ID_VC11_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC11_S  11
+/** CSI_HOST_MASK_ERR_ID_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC12    (BIT(12))
+#define CSI_HOST_MASK_ERR_ID_VC12_M  (CSI_HOST_MASK_ERR_ID_VC12_V << CSI_HOST_MASK_ERR_ID_VC12_S)
+#define CSI_HOST_MASK_ERR_ID_VC12_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC12_S  12
+/** CSI_HOST_MASK_ERR_ID_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC13    (BIT(13))
+#define CSI_HOST_MASK_ERR_ID_VC13_M  (CSI_HOST_MASK_ERR_ID_VC13_V << CSI_HOST_MASK_ERR_ID_VC13_S)
+#define CSI_HOST_MASK_ERR_ID_VC13_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC13_S  13
+/** CSI_HOST_MASK_ERR_ID_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC14    (BIT(14))
+#define CSI_HOST_MASK_ERR_ID_VC14_M  (CSI_HOST_MASK_ERR_ID_VC14_V << CSI_HOST_MASK_ERR_ID_VC14_S)
+#define CSI_HOST_MASK_ERR_ID_VC14_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC14_S  14
+/** CSI_HOST_MASK_ERR_ID_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ID_VC15    (BIT(15))
+#define CSI_HOST_MASK_ERR_ID_VC15_M  (CSI_HOST_MASK_ERR_ID_VC15_V << CSI_HOST_MASK_ERR_ID_VC15_S)
+#define CSI_HOST_MASK_ERR_ID_VC15_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ID_VC15_S  15
+
+/** CSI_HOST_INT_FORCE_DATA_ID_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_FORCE_DATA_ID_REG (DR_REG_CSI_HOST_BASE + 0x2c8)
+/** CSI_HOST_FORCE_ERR_ID_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC0    (BIT(0))
+#define CSI_HOST_FORCE_ERR_ID_VC0_M  (CSI_HOST_FORCE_ERR_ID_VC0_V << CSI_HOST_FORCE_ERR_ID_VC0_S)
+#define CSI_HOST_FORCE_ERR_ID_VC0_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC0_S  0
+/** CSI_HOST_FORCE_ERR_ID_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC1    (BIT(1))
+#define CSI_HOST_FORCE_ERR_ID_VC1_M  (CSI_HOST_FORCE_ERR_ID_VC1_V << CSI_HOST_FORCE_ERR_ID_VC1_S)
+#define CSI_HOST_FORCE_ERR_ID_VC1_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC1_S  1
+/** CSI_HOST_FORCE_ERR_ID_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC2    (BIT(2))
+#define CSI_HOST_FORCE_ERR_ID_VC2_M  (CSI_HOST_FORCE_ERR_ID_VC2_V << CSI_HOST_FORCE_ERR_ID_VC2_S)
+#define CSI_HOST_FORCE_ERR_ID_VC2_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC2_S  2
+/** CSI_HOST_FORCE_ERR_ID_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC3    (BIT(3))
+#define CSI_HOST_FORCE_ERR_ID_VC3_M  (CSI_HOST_FORCE_ERR_ID_VC3_V << CSI_HOST_FORCE_ERR_ID_VC3_S)
+#define CSI_HOST_FORCE_ERR_ID_VC3_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC3_S  3
+/** CSI_HOST_FORCE_ERR_ID_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC4    (BIT(4))
+#define CSI_HOST_FORCE_ERR_ID_VC4_M  (CSI_HOST_FORCE_ERR_ID_VC4_V << CSI_HOST_FORCE_ERR_ID_VC4_S)
+#define CSI_HOST_FORCE_ERR_ID_VC4_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC4_S  4
+/** CSI_HOST_FORCE_ERR_ID_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC5    (BIT(5))
+#define CSI_HOST_FORCE_ERR_ID_VC5_M  (CSI_HOST_FORCE_ERR_ID_VC5_V << CSI_HOST_FORCE_ERR_ID_VC5_S)
+#define CSI_HOST_FORCE_ERR_ID_VC5_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC5_S  5
+/** CSI_HOST_FORCE_ERR_ID_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC6    (BIT(6))
+#define CSI_HOST_FORCE_ERR_ID_VC6_M  (CSI_HOST_FORCE_ERR_ID_VC6_V << CSI_HOST_FORCE_ERR_ID_VC6_S)
+#define CSI_HOST_FORCE_ERR_ID_VC6_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC6_S  6
+/** CSI_HOST_FORCE_ERR_ID_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC7    (BIT(7))
+#define CSI_HOST_FORCE_ERR_ID_VC7_M  (CSI_HOST_FORCE_ERR_ID_VC7_V << CSI_HOST_FORCE_ERR_ID_VC7_S)
+#define CSI_HOST_FORCE_ERR_ID_VC7_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC7_S  7
+/** CSI_HOST_FORCE_ERR_ID_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC8    (BIT(8))
+#define CSI_HOST_FORCE_ERR_ID_VC8_M  (CSI_HOST_FORCE_ERR_ID_VC8_V << CSI_HOST_FORCE_ERR_ID_VC8_S)
+#define CSI_HOST_FORCE_ERR_ID_VC8_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC8_S  8
+/** CSI_HOST_FORCE_ERR_ID_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC9    (BIT(9))
+#define CSI_HOST_FORCE_ERR_ID_VC9_M  (CSI_HOST_FORCE_ERR_ID_VC9_V << CSI_HOST_FORCE_ERR_ID_VC9_S)
+#define CSI_HOST_FORCE_ERR_ID_VC9_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC9_S  9
+/** CSI_HOST_FORCE_ERR_ID_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC10    (BIT(10))
+#define CSI_HOST_FORCE_ERR_ID_VC10_M  (CSI_HOST_FORCE_ERR_ID_VC10_V << CSI_HOST_FORCE_ERR_ID_VC10_S)
+#define CSI_HOST_FORCE_ERR_ID_VC10_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC10_S  10
+/** CSI_HOST_FORCE_ERR_ID_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC11    (BIT(11))
+#define CSI_HOST_FORCE_ERR_ID_VC11_M  (CSI_HOST_FORCE_ERR_ID_VC11_V << CSI_HOST_FORCE_ERR_ID_VC11_S)
+#define CSI_HOST_FORCE_ERR_ID_VC11_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC11_S  11
+/** CSI_HOST_FORCE_ERR_ID_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC12    (BIT(12))
+#define CSI_HOST_FORCE_ERR_ID_VC12_M  (CSI_HOST_FORCE_ERR_ID_VC12_V << CSI_HOST_FORCE_ERR_ID_VC12_S)
+#define CSI_HOST_FORCE_ERR_ID_VC12_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC12_S  12
+/** CSI_HOST_FORCE_ERR_ID_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC13    (BIT(13))
+#define CSI_HOST_FORCE_ERR_ID_VC13_M  (CSI_HOST_FORCE_ERR_ID_VC13_V << CSI_HOST_FORCE_ERR_ID_VC13_S)
+#define CSI_HOST_FORCE_ERR_ID_VC13_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC13_S  13
+/** CSI_HOST_FORCE_ERR_ID_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC14    (BIT(14))
+#define CSI_HOST_FORCE_ERR_ID_VC14_M  (CSI_HOST_FORCE_ERR_ID_VC14_V << CSI_HOST_FORCE_ERR_ID_VC14_S)
+#define CSI_HOST_FORCE_ERR_ID_VC14_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC14_S  14
+/** CSI_HOST_FORCE_ERR_ID_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ID_VC15    (BIT(15))
+#define CSI_HOST_FORCE_ERR_ID_VC15_M  (CSI_HOST_FORCE_ERR_ID_VC15_V << CSI_HOST_FORCE_ERR_ID_VC15_S)
+#define CSI_HOST_FORCE_ERR_ID_VC15_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ID_VC15_S  15
+
+/** CSI_HOST_INT_ST_ECC_CORRECTED_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_ST_ECC_CORRECTED_REG (DR_REG_CSI_HOST_BASE + 0x2d0)
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC0 : RC; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC0    (BIT(0))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC0_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC0_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC0_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC0_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC0_S  0
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC1 : RC; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC1    (BIT(1))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC1_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC1_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC1_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC1_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC1_S  1
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC2 : RC; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC2    (BIT(2))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC2_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC2_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC2_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC2_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC2_S  2
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC3 : RC; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC3    (BIT(3))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC3_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC3_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC3_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC3_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC3_S  3
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC4 : RC; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC4    (BIT(4))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC4_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC4_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC4_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC4_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC4_S  4
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC5 : RC; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC5    (BIT(5))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC5_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC5_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC5_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC5_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC5_S  5
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC6 : RC; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC6    (BIT(6))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC6_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC6_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC6_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC6_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC6_S  6
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC7 : RC; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC7    (BIT(7))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC7_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC7_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC7_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC7_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC7_S  7
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC8 : RC; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC8    (BIT(8))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC8_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC8_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC8_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC8_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC8_S  8
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC9 : RC; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC9    (BIT(9))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC9_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC9_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC9_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC9_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC9_S  9
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC10 : RC; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC10    (BIT(10))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC10_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC10_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC10_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC10_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC10_S  10
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC11 : RC; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC11    (BIT(11))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC11_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC11_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC11_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC11_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC11_S  11
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC12 : RC; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC12    (BIT(12))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC12_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC12_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC12_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC12_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC12_S  12
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC13 : RC; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC13    (BIT(13))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC13_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC13_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC13_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC13_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC13_S  13
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC14 : RC; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC14    (BIT(14))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC14_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC14_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC14_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC14_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC14_S  14
+/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC15 : RC; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC15    (BIT(15))
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC15_M  (CSI_HOST_ST_ERR_ECC_CORRECTED_VC15_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC15_S)
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC15_V  0x00000001U
+#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC15_S  15
+
+/** CSI_HOST_INT_MSK_ECC_CORRECTED_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_MSK_ECC_CORRECTED_REG (DR_REG_CSI_HOST_BASE + 0x2d4)
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0    (BIT(0))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0_S  0
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1    (BIT(1))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1_S  1
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2    (BIT(2))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2_S  2
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3    (BIT(3))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3_S  3
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4    (BIT(4))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4_S  4
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5    (BIT(5))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5_S  5
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6    (BIT(6))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6_S  6
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7    (BIT(7))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7_S  7
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8    (BIT(8))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8_S  8
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9    (BIT(9))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9_S  9
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10    (BIT(10))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10_S  10
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11    (BIT(11))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11_S  11
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12    (BIT(12))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12_S  12
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13    (BIT(13))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13_S  13
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14    (BIT(14))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14_S  14
+/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15    (BIT(15))
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15_M  (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15_S)
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15_V  0x00000001U
+#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15_S  15
+
+/** CSI_HOST_INT_FORCE_ECC_CORRECTED_REG register
+ *  NA
+ */
+#define CSI_HOST_INT_FORCE_ECC_CORRECTED_REG (DR_REG_CSI_HOST_BASE + 0x2d8)
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0    (BIT(0))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0_S  0
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1    (BIT(1))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1_S  1
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2    (BIT(2))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2_S  2
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3    (BIT(3))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3_S  3
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4    (BIT(4))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4_S  4
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5    (BIT(5))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5_S  5
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6    (BIT(6))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6_S  6
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7    (BIT(7))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7_S  7
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8    (BIT(8))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8_S  8
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9    (BIT(9))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9_S  9
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10    (BIT(10))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10_S  10
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11    (BIT(11))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11_S  11
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12    (BIT(12))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12_S  12
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13    (BIT(13))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13_S  13
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14    (BIT(14))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14_S  14
+/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15    (BIT(15))
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15_M  (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15_S)
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15_V  0x00000001U
+#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15_S  15
+
+/** CSI_HOST_SCRAMBLING_REG register
+ *  NA
+ */
+#define CSI_HOST_SCRAMBLING_REG (DR_REG_CSI_HOST_BASE + 0x300)
+/** CSI_HOST_SCRAMBLE_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define CSI_HOST_SCRAMBLE_ENABLE    (BIT(0))
+#define CSI_HOST_SCRAMBLE_ENABLE_M  (CSI_HOST_SCRAMBLE_ENABLE_V << CSI_HOST_SCRAMBLE_ENABLE_S)
+#define CSI_HOST_SCRAMBLE_ENABLE_V  0x00000001U
+#define CSI_HOST_SCRAMBLE_ENABLE_S  0
+
+/** CSI_HOST_SCRAMBLING_SEED1_REG register
+ *  NA
+ */
+#define CSI_HOST_SCRAMBLING_SEED1_REG (DR_REG_CSI_HOST_BASE + 0x304)
+/** CSI_HOST_SCRAMBLE_SEED_LANE1 : R/W; bitpos: [15:0]; default: 4104;
+ *  NA
+ */
+#define CSI_HOST_SCRAMBLE_SEED_LANE1    0x0000FFFFU
+#define CSI_HOST_SCRAMBLE_SEED_LANE1_M  (CSI_HOST_SCRAMBLE_SEED_LANE1_V << CSI_HOST_SCRAMBLE_SEED_LANE1_S)
+#define CSI_HOST_SCRAMBLE_SEED_LANE1_V  0x0000FFFFU
+#define CSI_HOST_SCRAMBLE_SEED_LANE1_S  0
+
+/** CSI_HOST_SCRAMBLING_SEED2_REG register
+ *  NA
+ */
+#define CSI_HOST_SCRAMBLING_SEED2_REG (DR_REG_CSI_HOST_BASE + 0x308)
+/** CSI_HOST_SCRAMBLE_SEED_LANE2 : R/W; bitpos: [15:0]; default: 4488;
+ *  NA
+ */
+#define CSI_HOST_SCRAMBLE_SEED_LANE2    0x0000FFFFU
+#define CSI_HOST_SCRAMBLE_SEED_LANE2_M  (CSI_HOST_SCRAMBLE_SEED_LANE2_V << CSI_HOST_SCRAMBLE_SEED_LANE2_S)
+#define CSI_HOST_SCRAMBLE_SEED_LANE2_V  0x0000FFFFU
+#define CSI_HOST_SCRAMBLE_SEED_LANE2_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_struct.h
new file mode 100644
index 0000000000..bf5bfc43d9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_struct.h
@@ -0,0 +1,1883 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Version Register */
+/** Type of version register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** version : RO; bitpos: [31:0]; default: 825569322;
+         *  NA
+         */
+        uint32_t version:32;
+    };
+    uint32_t val;
+} csi_host_version_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of n_lanes register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** n_lanes : R/W; bitpos: [2:0]; default: 1;
+         *  NA
+         */
+        uint32_t n_lanes:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} csi_host_n_lanes_reg_t;
+
+/** Type of csi2_resetn register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** csi2_resetn : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t csi2_resetn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_csi2_resetn_reg_t;
+
+/** Type of phy_shutdownz register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_shutdownz : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_shutdownz:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_phy_shutdownz_reg_t;
+
+/** Type of dphy_rstz register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dphy_rstz : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_rstz:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_dphy_rstz_reg_t;
+
+/** Type of phy_rx register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_rxulpsesc_0 : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_rxulpsesc_0:1;
+        /** phy_rxulpsesc_1 : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_rxulpsesc_1:1;
+        uint32_t reserved_2:14;
+        /** phy_rxulpsclknot : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t phy_rxulpsclknot:1;
+        /** phy_rxclkactivehs : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t phy_rxclkactivehs:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} csi_host_phy_rx_reg_t;
+
+/** Type of phy_test_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_testclr : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t phy_testclr:1;
+        /** phy_testclk : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testclk:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_phy_test_ctrl0_reg_t;
+
+/** Type of phy_test_ctrl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_testdin : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testdin:8;
+        /** phy_testdout : RO; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testdout:8;
+        /** phy_testen : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testen:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} csi_host_phy_test_ctrl1_reg_t;
+
+/** Type of vc_extension register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vcx : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t vcx:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_vc_extension_reg_t;
+
+/** Type of phy_cal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** rxskewcalhs : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t rxskewcalhs:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_phy_cal_reg_t;
+
+/** Type of scrambling register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** scramble_enable : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t scramble_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_host_scrambling_reg_t;
+
+/** Type of scrambling_seed1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** scramble_seed_lane1 : R/W; bitpos: [15:0]; default: 4104;
+         *  NA
+         */
+        uint32_t scramble_seed_lane1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_scrambling_seed1_reg_t;
+
+/** Type of scrambling_seed2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** scramble_seed_lane2 : R/W; bitpos: [15:0]; default: 4488;
+         *  NA
+         */
+        uint32_t scramble_seed_lane2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_scrambling_seed2_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_st_main register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_status_int_phy_fatal : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_phy_fatal:1;
+        /** st_status_int_pkt_fatal : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_pkt_fatal:1;
+        /** st_status_int_bndry_frame_fatal : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_bndry_frame_fatal:1;
+        /** st_status_int_seq_frame_fatal : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_seq_frame_fatal:1;
+        /** st_status_int_crc_frame_fatal : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_crc_frame_fatal:1;
+        /** st_status_int_pld_crc_fatal : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_pld_crc_fatal:1;
+        /** st_status_int_data_id : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_data_id:1;
+        /** st_status_int_ecc_corrected : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_ecc_corrected:1;
+        uint32_t reserved_8:8;
+        /** st_status_int_phy : RC; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t st_status_int_phy:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} csi_host_int_st_main_reg_t;
+
+/** Type of int_st_phy_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_phy_errsotsynchs_0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_errsotsynchs_0:1;
+        /** st_phy_errsotsynchs_1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_errsotsynchs_1:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_st_phy_fatal_reg_t;
+
+/** Type of int_msk_phy_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_errsotsynchs_0:1;
+        /** mask_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_errsotsynchs_1:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_msk_phy_fatal_reg_t;
+
+/** Type of int_force_phy_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_errsotsynchs_0:1;
+        /** force_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_errsotsynchs_1:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_force_phy_fatal_reg_t;
+
+/** Type of int_st_pkt_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_ecc_double : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_double:1;
+        /** st_shorter_payload : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_shorter_payload:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_st_pkt_fatal_reg_t;
+
+/** Type of int_msk_pkt_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_ecc_double : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_double:1;
+        /** mask_shorter_payload : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_shorter_payload:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_msk_pkt_fatal_reg_t;
+
+/** Type of int_force_pkt_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_ecc_double : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_double:1;
+        /** force_shorter_payload : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_shorter_payload:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_host_int_force_pkt_fatal_reg_t;
+
+/** Type of int_st_phy register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_phy_errsoths_0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_errsoths_0:1;
+        /** st_phy_errsoths_1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_errsoths_1:1;
+        uint32_t reserved_2:14;
+        /** st_phy_erresc_0 : RC; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_erresc_0:1;
+        /** st_phy_erresc_1 : RC; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t st_phy_erresc_1:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} csi_host_int_st_phy_reg_t;
+
+/** Type of int_msk_phy register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_phy_errsoths_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_errsoths_0:1;
+        /** mask_phy_errsoths_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_errsoths_1:1;
+        uint32_t reserved_2:14;
+        /** mask_phy_erresc_0 : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_erresc_0:1;
+        /** mask_phy_erresc_1 : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t mask_phy_erresc_1:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} csi_host_int_msk_phy_reg_t;
+
+/** Type of int_force_phy register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_phy_errsoths_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_errsoths_0:1;
+        /** force_phy_errsoths_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_errsoths_1:1;
+        uint32_t reserved_2:14;
+        /** force_phy_erresc_0 : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_erresc_0:1;
+        /** force_phy_erresc_1 : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t force_phy_erresc_1:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} csi_host_int_force_phy_reg_t;
+
+/** Type of int_st_bndry_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_f_bndry_match_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc0:1;
+        /** st_err_f_bndry_match_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc1:1;
+        /** st_err_f_bndry_match_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc2:1;
+        /** st_err_f_bndry_match_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc3:1;
+        /** st_err_f_bndry_match_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc4:1;
+        /** st_err_f_bndry_match_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc5:1;
+        /** st_err_f_bndry_match_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc6:1;
+        /** st_err_f_bndry_match_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc7:1;
+        /** st_err_f_bndry_match_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc8:1;
+        /** st_err_f_bndry_match_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc9:1;
+        /** st_err_f_bndry_match_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc10:1;
+        /** st_err_f_bndry_match_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc11:1;
+        /** st_err_f_bndry_match_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc12:1;
+        /** st_err_f_bndry_match_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc13:1;
+        /** st_err_f_bndry_match_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc14:1;
+        /** st_err_f_bndry_match_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_bndry_match_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_bndry_frame_fatal_reg_t;
+
+/** Type of int_msk_bndry_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc0:1;
+        /** mask_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc1:1;
+        /** mask_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc2:1;
+        /** mask_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc3:1;
+        /** mask_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc4:1;
+        /** mask_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc5:1;
+        /** mask_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc6:1;
+        /** mask_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc7:1;
+        /** mask_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc8:1;
+        /** mask_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc9:1;
+        /** mask_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc10:1;
+        /** mask_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc11:1;
+        /** mask_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc12:1;
+        /** mask_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc13:1;
+        /** mask_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc14:1;
+        /** mask_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_bndry_match_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_bndry_frame_fatal_reg_t;
+
+/** Type of int_force_bndry_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc0:1;
+        /** force_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc1:1;
+        /** force_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc2:1;
+        /** force_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc3:1;
+        /** force_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc4:1;
+        /** force_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc5:1;
+        /** force_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc6:1;
+        /** force_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc7:1;
+        /** force_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc8:1;
+        /** force_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc9:1;
+        /** force_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc10:1;
+        /** force_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc11:1;
+        /** force_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc12:1;
+        /** force_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc13:1;
+        /** force_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc14:1;
+        /** force_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_bndry_match_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_bndry_frame_fatal_reg_t;
+
+/** Type of int_st_seq_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_f_seq_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc0:1;
+        /** st_err_f_seq_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc1:1;
+        /** st_err_f_seq_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc2:1;
+        /** st_err_f_seq_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc3:1;
+        /** st_err_f_seq_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc4:1;
+        /** st_err_f_seq_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc5:1;
+        /** st_err_f_seq_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc6:1;
+        /** st_err_f_seq_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc7:1;
+        /** st_err_f_seq_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc8:1;
+        /** st_err_f_seq_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc9:1;
+        /** st_err_f_seq_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc10:1;
+        /** st_err_f_seq_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc11:1;
+        /** st_err_f_seq_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc12:1;
+        /** st_err_f_seq_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc13:1;
+        /** st_err_f_seq_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc14:1;
+        /** st_err_f_seq_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_f_seq_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_seq_frame_fatal_reg_t;
+
+/** Type of int_msk_seq_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc0:1;
+        /** mask_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc1:1;
+        /** mask_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc2:1;
+        /** mask_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc3:1;
+        /** mask_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc4:1;
+        /** mask_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc5:1;
+        /** mask_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc6:1;
+        /** mask_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc7:1;
+        /** mask_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc8:1;
+        /** mask_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc9:1;
+        /** mask_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc10:1;
+        /** mask_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc11:1;
+        /** mask_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc12:1;
+        /** mask_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc13:1;
+        /** mask_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc14:1;
+        /** mask_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_f_seq_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_seq_frame_fatal_reg_t;
+
+/** Type of int_force_seq_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc0:1;
+        /** force_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc1:1;
+        /** force_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc2:1;
+        /** force_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc3:1;
+        /** force_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc4:1;
+        /** force_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc5:1;
+        /** force_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc6:1;
+        /** force_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc7:1;
+        /** force_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc8:1;
+        /** force_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc9:1;
+        /** force_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc10:1;
+        /** force_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc11:1;
+        /** force_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc12:1;
+        /** force_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc13:1;
+        /** force_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc14:1;
+        /** force_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_f_seq_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_seq_frame_fatal_reg_t;
+
+/** Type of int_st_crc_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_frame_data_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc0:1;
+        /** st_err_frame_data_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc1:1;
+        /** st_err_frame_data_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc2:1;
+        /** st_err_frame_data_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc3:1;
+        /** st_err_frame_data_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc4:1;
+        /** st_err_frame_data_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc5:1;
+        /** st_err_frame_data_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc6:1;
+        /** st_err_frame_data_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc7:1;
+        /** st_err_frame_data_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc8:1;
+        /** st_err_frame_data_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc9:1;
+        /** st_err_frame_data_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc10:1;
+        /** st_err_frame_data_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc11:1;
+        /** st_err_frame_data_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc12:1;
+        /** st_err_frame_data_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc13:1;
+        /** st_err_frame_data_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc14:1;
+        /** st_err_frame_data_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_frame_data_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_crc_frame_fatal_reg_t;
+
+/** Type of int_msk_crc_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc0:1;
+        /** mask_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc1:1;
+        /** mask_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc2:1;
+        /** mask_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc3:1;
+        /** mask_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc4:1;
+        /** mask_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc5:1;
+        /** mask_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc6:1;
+        /** mask_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc7:1;
+        /** mask_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc8:1;
+        /** mask_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc9:1;
+        /** mask_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc10:1;
+        /** mask_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc11:1;
+        /** mask_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc12:1;
+        /** mask_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc13:1;
+        /** mask_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc14:1;
+        /** mask_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_frame_data_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_crc_frame_fatal_reg_t;
+
+/** Type of int_force_crc_frame_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc0:1;
+        /** force_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc1:1;
+        /** force_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc2:1;
+        /** force_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc3:1;
+        /** force_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc4:1;
+        /** force_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc5:1;
+        /** force_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc6:1;
+        /** force_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc7:1;
+        /** force_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc8:1;
+        /** force_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc9:1;
+        /** force_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc10:1;
+        /** force_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc11:1;
+        /** force_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc12:1;
+        /** force_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc13:1;
+        /** force_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc14:1;
+        /** force_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_frame_data_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_crc_frame_fatal_reg_t;
+
+/** Type of int_st_pld_crc_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_crc_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc0:1;
+        /** st_err_crc_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc1:1;
+        /** st_err_crc_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc2:1;
+        /** st_err_crc_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc3:1;
+        /** st_err_crc_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc4:1;
+        /** st_err_crc_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc5:1;
+        /** st_err_crc_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc6:1;
+        /** st_err_crc_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc7:1;
+        /** st_err_crc_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc8:1;
+        /** st_err_crc_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc9:1;
+        /** st_err_crc_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc10:1;
+        /** st_err_crc_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc11:1;
+        /** st_err_crc_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc12:1;
+        /** st_err_crc_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc13:1;
+        /** st_err_crc_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc14:1;
+        /** st_err_crc_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_crc_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_pld_crc_fatal_reg_t;
+
+/** Type of int_msk_pld_crc_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_crc_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc0:1;
+        /** mask_err_crc_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc1:1;
+        /** mask_err_crc_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc2:1;
+        /** mask_err_crc_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc3:1;
+        /** mask_err_crc_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc4:1;
+        /** mask_err_crc_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc5:1;
+        /** mask_err_crc_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc6:1;
+        /** mask_err_crc_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc7:1;
+        /** mask_err_crc_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc8:1;
+        /** mask_err_crc_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc9:1;
+        /** mask_err_crc_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc10:1;
+        /** mask_err_crc_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc11:1;
+        /** mask_err_crc_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc12:1;
+        /** mask_err_crc_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc13:1;
+        /** mask_err_crc_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc14:1;
+        /** mask_err_crc_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_crc_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_pld_crc_fatal_reg_t;
+
+/** Type of int_force_pld_crc_fatal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_crc_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc0:1;
+        /** force_err_crc_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc1:1;
+        /** force_err_crc_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc2:1;
+        /** force_err_crc_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc3:1;
+        /** force_err_crc_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc4:1;
+        /** force_err_crc_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc5:1;
+        /** force_err_crc_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc6:1;
+        /** force_err_crc_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc7:1;
+        /** force_err_crc_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc8:1;
+        /** force_err_crc_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc9:1;
+        /** force_err_crc_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc10:1;
+        /** force_err_crc_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc11:1;
+        /** force_err_crc_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc12:1;
+        /** force_err_crc_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc13:1;
+        /** force_err_crc_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc14:1;
+        /** force_err_crc_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_crc_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_pld_crc_fatal_reg_t;
+
+/** Type of int_st_data_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_id_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc0:1;
+        /** st_err_id_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc1:1;
+        /** st_err_id_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc2:1;
+        /** st_err_id_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc3:1;
+        /** st_err_id_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc4:1;
+        /** st_err_id_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc5:1;
+        /** st_err_id_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc6:1;
+        /** st_err_id_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc7:1;
+        /** st_err_id_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc8:1;
+        /** st_err_id_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc9:1;
+        /** st_err_id_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc10:1;
+        /** st_err_id_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc11:1;
+        /** st_err_id_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc12:1;
+        /** st_err_id_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc13:1;
+        /** st_err_id_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc14:1;
+        /** st_err_id_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_id_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_data_id_reg_t;
+
+/** Type of int_msk_data_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_id_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc0:1;
+        /** mask_err_id_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc1:1;
+        /** mask_err_id_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc2:1;
+        /** mask_err_id_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc3:1;
+        /** mask_err_id_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc4:1;
+        /** mask_err_id_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc5:1;
+        /** mask_err_id_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc6:1;
+        /** mask_err_id_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc7:1;
+        /** mask_err_id_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc8:1;
+        /** mask_err_id_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc9:1;
+        /** mask_err_id_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc10:1;
+        /** mask_err_id_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc11:1;
+        /** mask_err_id_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc12:1;
+        /** mask_err_id_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc13:1;
+        /** mask_err_id_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc14:1;
+        /** mask_err_id_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_id_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_data_id_reg_t;
+
+/** Type of int_force_data_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_id_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc0:1;
+        /** force_err_id_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc1:1;
+        /** force_err_id_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc2:1;
+        /** force_err_id_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc3:1;
+        /** force_err_id_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc4:1;
+        /** force_err_id_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc5:1;
+        /** force_err_id_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc6:1;
+        /** force_err_id_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc7:1;
+        /** force_err_id_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc8:1;
+        /** force_err_id_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc9:1;
+        /** force_err_id_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc10:1;
+        /** force_err_id_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc11:1;
+        /** force_err_id_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc12:1;
+        /** force_err_id_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc13:1;
+        /** force_err_id_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc14:1;
+        /** force_err_id_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_id_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_data_id_reg_t;
+
+/** Type of int_st_ecc_corrected register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** st_err_ecc_corrected_vc0 : RC; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc0:1;
+        /** st_err_ecc_corrected_vc1 : RC; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc1:1;
+        /** st_err_ecc_corrected_vc2 : RC; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc2:1;
+        /** st_err_ecc_corrected_vc3 : RC; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc3:1;
+        /** st_err_ecc_corrected_vc4 : RC; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc4:1;
+        /** st_err_ecc_corrected_vc5 : RC; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc5:1;
+        /** st_err_ecc_corrected_vc6 : RC; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc6:1;
+        /** st_err_ecc_corrected_vc7 : RC; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc7:1;
+        /** st_err_ecc_corrected_vc8 : RC; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc8:1;
+        /** st_err_ecc_corrected_vc9 : RC; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc9:1;
+        /** st_err_ecc_corrected_vc10 : RC; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc10:1;
+        /** st_err_ecc_corrected_vc11 : RC; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc11:1;
+        /** st_err_ecc_corrected_vc12 : RC; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc12:1;
+        /** st_err_ecc_corrected_vc13 : RC; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc13:1;
+        /** st_err_ecc_corrected_vc14 : RC; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc14:1;
+        /** st_err_ecc_corrected_vc15 : RC; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t st_err_ecc_corrected_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_st_ecc_corrected_reg_t;
+
+/** Type of int_msk_ecc_corrected register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc0:1;
+        /** mask_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc1:1;
+        /** mask_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc2:1;
+        /** mask_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc3:1;
+        /** mask_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc4:1;
+        /** mask_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc5:1;
+        /** mask_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc6:1;
+        /** mask_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc7:1;
+        /** mask_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc8:1;
+        /** mask_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc9:1;
+        /** mask_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc10:1;
+        /** mask_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc11:1;
+        /** mask_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc12:1;
+        /** mask_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc13:1;
+        /** mask_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc14:1;
+        /** mask_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_err_ecc_corrected_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_msk_ecc_corrected_reg_t;
+
+/** Type of int_force_ecc_corrected register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc0:1;
+        /** force_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc1:1;
+        /** force_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc2:1;
+        /** force_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc3:1;
+        /** force_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc4:1;
+        /** force_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc5:1;
+        /** force_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc6:1;
+        /** force_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc7:1;
+        /** force_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc8:1;
+        /** force_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc9:1;
+        /** force_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc10:1;
+        /** force_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc11:1;
+        /** force_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc12:1;
+        /** force_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc13:1;
+        /** force_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc14:1;
+        /** force_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_err_ecc_corrected_vc15:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_host_int_force_ecc_corrected_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of phy_stopstate register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_stopstatedata_0 : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstatedata_0:1;
+        /** phy_stopstatedata_1 : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstatedata_1:1;
+        uint32_t reserved_2:14;
+        /** phy_stopstateclk : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstateclk:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} csi_host_phy_stopstate_reg_t;
+
+
+typedef struct csi_host_dev_t {
+    volatile csi_host_version_reg_t version;
+    volatile csi_host_n_lanes_reg_t n_lanes;
+    volatile csi_host_csi2_resetn_reg_t csi2_resetn;
+    volatile csi_host_int_st_main_reg_t int_st_main;
+    uint32_t reserved_010[12];
+    volatile csi_host_phy_shutdownz_reg_t phy_shutdownz;
+    volatile csi_host_dphy_rstz_reg_t dphy_rstz;
+    volatile csi_host_phy_rx_reg_t phy_rx;
+    volatile csi_host_phy_stopstate_reg_t phy_stopstate;
+    volatile csi_host_phy_test_ctrl0_reg_t phy_test_ctrl0;
+    volatile csi_host_phy_test_ctrl1_reg_t phy_test_ctrl1;
+    uint32_t reserved_058[28];
+    volatile csi_host_vc_extension_reg_t vc_extension;
+    volatile csi_host_phy_cal_reg_t phy_cal;
+    uint32_t reserved_0d0[4];
+    volatile csi_host_int_st_phy_fatal_reg_t int_st_phy_fatal;
+    volatile csi_host_int_msk_phy_fatal_reg_t int_msk_phy_fatal;
+    volatile csi_host_int_force_phy_fatal_reg_t int_force_phy_fatal;
+    uint32_t reserved_0ec;
+    volatile csi_host_int_st_pkt_fatal_reg_t int_st_pkt_fatal;
+    volatile csi_host_int_msk_pkt_fatal_reg_t int_msk_pkt_fatal;
+    volatile csi_host_int_force_pkt_fatal_reg_t int_force_pkt_fatal;
+    uint32_t reserved_0fc[5];
+    volatile csi_host_int_st_phy_reg_t int_st_phy;
+    volatile csi_host_int_msk_phy_reg_t int_msk_phy;
+    volatile csi_host_int_force_phy_reg_t int_force_phy;
+    uint32_t reserved_11c[89];
+    volatile csi_host_int_st_bndry_frame_fatal_reg_t int_st_bndry_frame_fatal;
+    volatile csi_host_int_msk_bndry_frame_fatal_reg_t int_msk_bndry_frame_fatal;
+    volatile csi_host_int_force_bndry_frame_fatal_reg_t int_force_bndry_frame_fatal;
+    uint32_t reserved_28c;
+    volatile csi_host_int_st_seq_frame_fatal_reg_t int_st_seq_frame_fatal;
+    volatile csi_host_int_msk_seq_frame_fatal_reg_t int_msk_seq_frame_fatal;
+    volatile csi_host_int_force_seq_frame_fatal_reg_t int_force_seq_frame_fatal;
+    uint32_t reserved_29c;
+    volatile csi_host_int_st_crc_frame_fatal_reg_t int_st_crc_frame_fatal;
+    volatile csi_host_int_msk_crc_frame_fatal_reg_t int_msk_crc_frame_fatal;
+    volatile csi_host_int_force_crc_frame_fatal_reg_t int_force_crc_frame_fatal;
+    uint32_t reserved_2ac;
+    volatile csi_host_int_st_pld_crc_fatal_reg_t int_st_pld_crc_fatal;
+    volatile csi_host_int_msk_pld_crc_fatal_reg_t int_msk_pld_crc_fatal;
+    volatile csi_host_int_force_pld_crc_fatal_reg_t int_force_pld_crc_fatal;
+    uint32_t reserved_2bc;
+    volatile csi_host_int_st_data_id_reg_t int_st_data_id;
+    volatile csi_host_int_msk_data_id_reg_t int_msk_data_id;
+    volatile csi_host_int_force_data_id_reg_t int_force_data_id;
+    uint32_t reserved_2cc;
+    volatile csi_host_int_st_ecc_corrected_reg_t int_st_ecc_corrected;
+    volatile csi_host_int_msk_ecc_corrected_reg_t int_msk_ecc_corrected;
+    volatile csi_host_int_force_ecc_corrected_reg_t int_force_ecc_corrected;
+    uint32_t reserved_2dc[9];
+    volatile csi_host_scrambling_reg_t scrambling;
+    volatile csi_host_scrambling_seed1_reg_t scrambling_seed1;
+    volatile csi_host_scrambling_seed2_reg_t scrambling_seed2;
+} csi_host_dev_t;
+
+extern csi_host_dev_t MIPI_CSI_HOST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(csi_host_dev_t) == 0x30c, "Invalid size of csi_host_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_eco5_struct.h
new file mode 100644
index 0000000000..f2f78f4ec9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_eco5_struct.h
@@ -0,0 +1,868 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of clk_en register
+ *  dsi bridge clk control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures force_on of dsi_bridge register clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_clk_en_reg_t;
+
+/** Type of en register
+ *  dsi bridge en register
+ */
+typedef union {
+    struct {
+        /** dsi_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures module enable of dsi_bridge. 0: disable, 1: enable
+         */
+        uint32_t dsi_en:1;
+        /** dsi_brig_rst : R/W; bitpos: [1]; default: 0;
+         *  Configures software reset of dsi_bridge. 0: release reset, 1: reset
+         */
+        uint32_t dsi_brig_rst:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_en_reg_t;
+
+/** Type of dma_req_cfg register
+ *  dsi bridge dma burst len register
+ */
+typedef union {
+    struct {
+        /** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures the num of 64-bit in one dma burst transfer, valid only when
+         *  dsi_bridge as flow controller
+         */
+        uint32_t dma_burst_len:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_brg_dma_req_cfg_reg_t;
+
+/** Type of raw_num_cfg register
+ *  dsi bridge raw number control register
+ */
+typedef union {
+    struct {
+        /** raw_num_total : R/W; bitpos: [21:0]; default: 230400;
+         *  this field configures number of total pix bits/64
+         */
+        uint32_t raw_num_total:22;
+        /** unalign_64bit_en : R/W; bitpos: [22]; default: 0;
+         *  this field configures whether the total pix bits is a multiple of 64bits. 0: align
+         *  to 64-bit, 1: unalign to 64-bit
+         */
+        uint32_t unalign_64bit_en:1;
+        uint32_t reserved_23:8;
+        /** raw_num_total_set : WT; bitpos: [31]; default: 0;
+         *  this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable,
+         *  1: enable. valid only when dsi_bridge as flow controller
+         */
+        uint32_t raw_num_total_set:1;
+    };
+    uint32_t val;
+} dsi_brg_raw_num_cfg_reg_t;
+
+/** Type of raw_buf_credit_ctl register
+ *  dsi bridge credit register
+ */
+typedef union {
+    struct {
+        /** credit_thrd : R/W; bitpos: [14:0]; default: 1024;
+         *  this field configures the threshold whether dsi_bridge fifo can receive one more
+         *  64-bit, valid only when dsi_bridge as flow controller
+         */
+        uint32_t credit_thrd:15;
+        uint32_t reserved_15:1;
+        /** credit_burst_thrd : R/W; bitpos: [30:16]; default: 800;
+         *  this field configures the threshold whether dsi_bridge fifo can receive one more
+         *  dma burst, valid only when dsi_bridge as flow controller
+         */
+        uint32_t credit_burst_thrd:15;
+        /** credit_reset : R/W; bitpos: [31]; default: 0;
+         *  this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when
+         *  dsi_bridge as flow controller
+         */
+        uint32_t credit_reset:1;
+    };
+    uint32_t val;
+} dsi_brg_raw_buf_credit_ctl_reg_t;
+
+/** Type of pixel_type register
+ *  dsi bridge dpi type control register
+ */
+typedef union {
+    struct {
+        /** raw_type : R/W; bitpos: [3:0]; default: 0;
+         *  this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444,
+         *  9:yuv422, 10:yuv420, 12:gray
+         */
+        uint32_t raw_type:4;
+        /** dpi_config : R/W; bitpos: [5:4]; default: 0;
+         *  this field configures the pixel arrange type of dpi interface
+         */
+        uint32_t dpi_config:2;
+        /** data_in_type : R/W; bitpos: [6]; default: 0;
+         *  input data type, 0: not yuv, 1: yuv
+         */
+        uint32_t data_in_type:1;
+        /** dpi_type : R/W; bitpos: [10:7]; default: 0;
+         *  this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565
+         */
+        uint32_t dpi_type:4;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dsi_brg_pixel_type_reg_t;
+
+/** Type of dma_block_interval register
+ *  dsi bridge dma block interval control register
+ */
+typedef union {
+    struct {
+        /** dma_block_slot : R/W; bitpos: [9:0]; default: 9;
+         *  this field configures the max block_slot_cnt
+         */
+        uint32_t dma_block_slot:10;
+        /** dma_block_interval : R/W; bitpos: [27:10]; default: 9;
+         *  this field configures the max block_interval_cnt, block_interval_cnt increased by 1
+         *  when block_slot_cnt if full
+         */
+        uint32_t dma_block_interval:18;
+        /** raw_num_total_auto_reload : R/W; bitpos: [28]; default: 1;
+         *  this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable
+         */
+        uint32_t raw_num_total_auto_reload:1;
+        /** dma_block_interval_en : R/W; bitpos: [29]; default: 1;
+         *  this bit configures enable of interval between dma block transfer, 0: disable, 1:
+         *  enable
+         */
+        uint32_t dma_block_interval_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} dsi_brg_dma_block_interval_reg_t;
+
+/** Type of dma_req_interval register
+ *  dsi bridge dma req interval control register
+ */
+typedef union {
+    struct {
+        /** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
+         *  this field configures the interval between dma req events
+         */
+        uint32_t dma_req_interval:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_brg_dma_req_interval_reg_t;
+
+/** Type of dpi_lcd_ctl register
+ *  dsi bridge dpi signal control register
+ */
+typedef union {
+    struct {
+        /** dpishutdn : R/W; bitpos: [0]; default: 0;
+         *  this bit configures dpishutdn signal in dpi interface
+         */
+        uint32_t dpishutdn:1;
+        /** dpicolorm : R/W; bitpos: [1]; default: 0;
+         *  this bit configures dpicolorm signal in dpi interface
+         */
+        uint32_t dpicolorm:1;
+        /** dpiupdatecfg : R/W; bitpos: [2]; default: 0;
+         *  this bit configures dpiupdatecfg signal in dpi interface
+         */
+        uint32_t dpiupdatecfg:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dsi_brg_dpi_lcd_ctl_reg_t;
+
+/** Type of dpi_rsv_dpi_data register
+ *  dsi bridge dpi reserved data register
+ */
+typedef union {
+    struct {
+        /** dpi_rsv_data : R/W; bitpos: [29:0]; default: 16383;
+         *  this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
+         */
+        uint32_t dpi_rsv_data:30;
+        /** dpi_dbg_en : R/W; bitpos: [30]; default: 0;
+         *  Configures data debug feature enable. 0: disable, 1: enable
+         */
+        uint32_t dpi_dbg_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dsi_brg_dpi_rsv_dpi_data_reg_t;
+
+/** Type of dpi_v_cfg0 register
+ *  dsi bridge dpi v config register 0
+ */
+typedef union {
+    struct {
+        /** vtotal : R/W; bitpos: [11:0]; default: 525;
+         *  this field configures the total length of one frame (by line) for dpi output, must
+         *  meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank
+         */
+        uint32_t vtotal:12;
+        uint32_t reserved_12:4;
+        /** vdisp : R/W; bitpos: [27:16]; default: 480;
+         *  this field configures the length of valid line (by line) for dpi output
+         */
+        uint32_t vdisp:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_v_cfg0_reg_t;
+
+/** Type of dpi_v_cfg1 register
+ *  dsi bridge dpi v config register 1
+ */
+typedef union {
+    struct {
+        /** vbank : R/W; bitpos: [11:0]; default: 33;
+         *  this field configures the length between vsync and valid line (by line) for dpi
+         *  output
+         */
+        uint32_t vbank:12;
+        uint32_t reserved_12:4;
+        /** vsync : R/W; bitpos: [27:16]; default: 2;
+         *  this field configures the length of vsync (by line) for dpi output
+         */
+        uint32_t vsync:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_v_cfg1_reg_t;
+
+/** Type of dpi_h_cfg0 register
+ *  dsi bridge dpi h config register 0
+ */
+typedef union {
+    struct {
+        /** htotal : R/W; bitpos: [11:0]; default: 800;
+         *  this field configures the total length of one line (by pixel num) for dpi output,
+         *  must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank
+         */
+        uint32_t htotal:12;
+        uint32_t reserved_12:4;
+        /** hdisp : R/W; bitpos: [27:16]; default: 640;
+         *  this field configures the length of valid pixel data (by pixel num) for dpi output
+         */
+        uint32_t hdisp:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_h_cfg0_reg_t;
+
+/** Type of dpi_h_cfg1 register
+ *  dsi bridge dpi h config register 1
+ */
+typedef union {
+    struct {
+        /** hbank : R/W; bitpos: [11:0]; default: 48;
+         *  this field configures the length between hsync and pixel data valid (by pixel num)
+         *  for dpi output
+         */
+        uint32_t hbank:12;
+        uint32_t reserved_12:4;
+        /** hsync : R/W; bitpos: [27:16]; default: 96;
+         *  this field configures the length of hsync (by pixel num) for dpi output
+         */
+        uint32_t hsync:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_h_cfg1_reg_t;
+
+/** Type of dpi_misc_config register
+ *  dsi_bridge dpi misc config register
+ */
+typedef union {
+    struct {
+        /** dpi_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures enable of dpi output, 0: disable, 1: enable
+         */
+        uint32_t dpi_en:1;
+        uint32_t reserved_1:3;
+        /** fifo_underrun_discard_vcnt : R/W; bitpos: [15:4]; default: 413;
+         *  this field configures the underrun interrupt musk, when underrun occurs and line
+         *  cnt is less then this field
+         */
+        uint32_t fifo_underrun_discard_vcnt:12;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_brg_dpi_misc_config_reg_t;
+
+/** Type of dpi_config_update register
+ *  dsi_bridge dpi config update register
+ */
+typedef union {
+    struct {
+        /** dpi_config_update : WT; bitpos: [0]; default: 0;
+         *  write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*
+         */
+        uint32_t dpi_config_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_dpi_config_update_reg_t;
+
+/** Type of host_trigger_rev register
+ *  dsi_bridge host trigger reverse control register
+ */
+typedef union {
+    struct {
+        /** tx_trigger_rev_en : R/W; bitpos: [0]; default: 0;
+         *  tx_trigger reverse. 0: disable, 1: enable
+         */
+        uint32_t tx_trigger_rev_en:1;
+        /** rx_trigger_rev_en : R/W; bitpos: [1]; default: 0;
+         *  rx_trigger reverse. 0: disable, 1: enable
+         */
+        uint32_t rx_trigger_rev_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_host_trigger_rev_reg_t;
+
+/** Type of blk_raw_num_cfg register
+ *  dsi_bridge block raw number control register
+ */
+typedef union {
+    struct {
+        /** blk_raw_num_total : R/W; bitpos: [21:0]; default: 230400;
+         *  this field configures number of total block pix bits/64
+         */
+        uint32_t blk_raw_num_total:22;
+        uint32_t reserved_22:9;
+        /** blk_raw_num_total_set : WT; bitpos: [31]; default: 0;
+         *  write 1 to reload reg_blk_raw_num_total to internal cnt
+         */
+        uint32_t blk_raw_num_total_set:1;
+    };
+    uint32_t val;
+} dsi_brg_blk_raw_num_cfg_reg_t;
+
+/** Type of dma_frame_interval register
+ *  dsi_bridge dam frame interval control register
+ */
+typedef union {
+    struct {
+        /** dma_frame_slot : R/W; bitpos: [9:0]; default: 9;
+         *  this field configures the max frame_slot_cnt
+         */
+        uint32_t dma_frame_slot:10;
+        /** dma_frame_interval : R/W; bitpos: [27:10]; default: 9;
+         *  this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1
+         *  when frame_slot_cnt if full
+         */
+        uint32_t dma_frame_interval:18;
+        /** dma_multiblk_en : R/W; bitpos: [28]; default: 0;
+         *  this bit configures enable multi-blk transfer, 0: disable, 1: enable
+         */
+        uint32_t dma_multiblk_en:1;
+        /** dma_frame_interval_en : R/W; bitpos: [29]; default: 1;
+         *  this bit configures enable interval between frame transfer, 0: disable, 1: enable
+         */
+        uint32_t dma_frame_interval_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} dsi_brg_dma_frame_interval_reg_t;
+
+/** Type of mem_aux_ctrl register
+ *  dsi_bridge mem aux control register
+ */
+typedef union {
+    struct {
+        /** dsi_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures dsi_bridge fifo memory aux ctrl
+         */
+        uint32_t dsi_mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_brg_mem_aux_ctrl_reg_t;
+
+/** Type of rdn_eco_low register
+ *  dsi_bridge rdn eco all low register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rdn_eco_low
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_low_reg_t;
+
+/** Type of rdn_eco_high register
+ *  dsi_bridge rdn eco all high register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rdn_eco_high
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_high_reg_t;
+
+/** Type of host_ctrl register
+ *  dsi_bridge host control register
+ */
+typedef union {
+    struct {
+        /** dsi_cfg_ref_clk_en : R/W; bitpos: [0]; default: 1;
+         *  this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1:
+         *  enable
+         */
+        uint32_t dsi_cfg_ref_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_host_ctrl_reg_t;
+
+/** Type of mem_clk_ctrl register
+ *  dsi_bridge mem force on control register
+ */
+typedef union {
+    struct {
+        /** dsi_bridge_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1:
+         *  force on
+         */
+        uint32_t dsi_bridge_mem_clk_force_on:1;
+        /** dsi_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on
+         */
+        uint32_t dsi_mem_clk_force_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_mem_clk_ctrl_reg_t;
+
+/** Type of dma_flow_ctrl register
+ *  dsi_bridge dma flow controller register
+ */
+typedef union {
+    struct {
+        /** dsi_dma_flow_controller : R/W; bitpos: [0]; default: 1;
+         *  this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge
+         *  as flow controller
+         */
+        uint32_t dsi_dma_flow_controller:1;
+        uint32_t reserved_1:3;
+        /** dma_flow_multiblk_num : R/W; bitpos: [7:4]; default: 1;
+         *  this field configures the num of blocks when multi-blk is enable and dmac as flow
+         *  controller
+         */
+        uint32_t dma_flow_multiblk_num:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dsi_brg_dma_flow_ctrl_reg_t;
+
+/** Type of raw_buf_almost_empty_thrd register
+ *  dsi_bridge buffer empty threshold register
+ */
+typedef union {
+    struct {
+        /** dsi_raw_buf_almost_empty_thrd : R/W; bitpos: [10:0]; default: 512;
+         *  this field configures the fifo almost empty threshold, is valid only when dmac as
+         *  flow controller
+         */
+        uint32_t dsi_raw_buf_almost_empty_thrd:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dsi_brg_raw_buf_almost_empty_thrd_reg_t;
+
+/** Type of yuv_cfg register
+ *  dsi_bridge yuv format config register
+ */
+typedef union {
+    struct {
+        /** protocol : R/W; bitpos: [0]; default: 0;
+         *  this bit configures yuv protoocl, 0: bt.601, 1: bt.709
+         */
+        uint32_t protocol:1;
+        /** yuv_pix_endian : R/W; bitpos: [1]; default: 0;
+         *  this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0
+         */
+        uint32_t yuv_pix_endian:1;
+        /** yuv422_format : R/W; bitpos: [3:2]; default: 0;
+         *  this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
+         */
+        uint32_t yuv422_format:2;
+        /** yuv_range : R/W; bitpos: [4]; default: 0;
+         *  Configures yuv pixel range, 0: limit range, 1: full range
+         */
+        uint32_t yuv_range:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} dsi_brg_yuv_cfg_reg_t;
+
+/** Type of phy_lp_loopback_ctrl register
+ *  dsi phy lp_loopback test ctrl
+ */
+typedef union {
+    struct {
+        /** phy_lp_txdataesc_1 : R/W; bitpos: [7:0]; default: 0;
+         *  txdataesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txdataesc_1:8;
+        /** phy_lp_txrequestesc_1 : R/W; bitpos: [8]; default: 0;
+         *  txrequestesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txrequestesc_1:1;
+        /** phy_lp_txvalidesc_1 : R/W; bitpos: [9]; default: 0;
+         *  txvalidesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txvalidesc_1:1;
+        /** phy_lp_txlpdtesc_1 : R/W; bitpos: [10]; default: 0;
+         *  txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txlpdtesc_1:1;
+        /** phy_lp_basedir_1 : R/W; bitpos: [11]; default: 0;
+         *  basedir_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_basedir_1:1;
+        uint32_t reserved_12:4;
+        /** phy_lp_txdataesc_0 : R/W; bitpos: [23:16]; default: 0;
+         *  txdataesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txdataesc_0:8;
+        /** phy_lp_txrequestesc_0 : R/W; bitpos: [24]; default: 0;
+         *  txrequestesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txrequestesc_0:1;
+        /** phy_lp_txvalidesc_0 : R/W; bitpos: [25]; default: 0;
+         *  txvalidesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txvalidesc_0:1;
+        /** phy_lp_txlpdtesc_0 : R/W; bitpos: [26]; default: 0;
+         *  txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txlpdtesc_0:1;
+        /** phy_lp_basedir_0 : R/W; bitpos: [27]; default: 0;
+         *  basedir_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_basedir_0:1;
+        /** phy_lp_loopback_check : WT; bitpos: [28]; default: 0;
+         *  dsi phy lp_loopback test start check
+         */
+        uint32_t phy_lp_loopback_check:1;
+        /** phy_lp_loopback_check_done : RO; bitpos: [29]; default: 0;
+         *  dsi phy lp_loopback test check done
+         */
+        uint32_t phy_lp_loopback_check_done:1;
+        /** phy_lp_loopback_en : R/W; bitpos: [30]; default: 0;
+         *  dsi phy lp_loopback ctrl en
+         */
+        uint32_t phy_lp_loopback_en:1;
+        /** phy_lp_loopback_ok : RO; bitpos: [31]; default: 0;
+         *  result of dsi phy lp_loopback test
+         */
+        uint32_t phy_lp_loopback_ok:1;
+    };
+    uint32_t val;
+} dsi_brg_phy_lp_loopback_ctrl_reg_t;
+
+/** Type of phy_hs_loopback_ctrl register
+ *  dsi phy hp_loopback test ctrl
+ */
+typedef union {
+    struct {
+        /** phy_hs_txdatahs_1 : R/W; bitpos: [7:0]; default: 0;
+         *  txdatahs_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txdatahs_1:8;
+        /** phy_hs_txrequestdatahs_1 : R/W; bitpos: [8]; default: 0;
+         *  txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequestdatahs_1:1;
+        /** phy_hs_basedir_1 : R/W; bitpos: [9]; default: 1;
+         *  basedir_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_basedir_1:1;
+        uint32_t reserved_10:6;
+        /** phy_hs_txdatahs_0 : R/W; bitpos: [23:16]; default: 0;
+         *  txdatahs_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txdatahs_0:8;
+        /** phy_hs_txrequestdatahs_0 : R/W; bitpos: [24]; default: 0;
+         *  txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequestdatahs_0:1;
+        /** phy_hs_basedir_0 : R/W; bitpos: [25]; default: 0;
+         *  basedir_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_basedir_0:1;
+        uint32_t reserved_26:1;
+        /** phy_hs_txrequesthsclk : R/W; bitpos: [27]; default: 0;
+         *  txrequesthsclk when  enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequesthsclk:1;
+        /** phy_hs_loopback_check : WT; bitpos: [28]; default: 0;
+         *  dsi phy hs_loopback test start check
+         */
+        uint32_t phy_hs_loopback_check:1;
+        /** phy_hs_loopback_check_done : RO; bitpos: [29]; default: 0;
+         *  dsi phy hs_loopback test check done
+         */
+        uint32_t phy_hs_loopback_check_done:1;
+        /** phy_hs_loopback_en : R/W; bitpos: [30]; default: 0;
+         *  dsi phy hs_loopback ctrl en
+         */
+        uint32_t phy_hs_loopback_en:1;
+        /** phy_hs_loopback_ok : RO; bitpos: [31]; default: 0;
+         *  result of dsi phy hs_loopback test
+         */
+        uint32_t phy_hs_loopback_ok:1;
+    };
+    uint32_t val;
+} dsi_brg_phy_hs_loopback_ctrl_reg_t;
+
+/** Type of phy_loopback_cnt register
+ *  loopback test cnt
+ */
+typedef union {
+    struct {
+        /** phy_hs_check_cnt_th : R/W; bitpos: [7:0]; default: 64;
+         *  hs_loopback test check cnt
+         */
+        uint32_t phy_hs_check_cnt_th:8;
+        uint32_t reserved_8:8;
+        /** phy_lp_check_cnt_th : R/W; bitpos: [23:16]; default: 64;
+         *  lp_loopback test check cnt
+         */
+        uint32_t phy_lp_check_cnt_th:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dsi_brg_phy_loopback_cnt_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of fifo_flow_status register
+ *  dsi bridge raw buffer depth register
+ */
+typedef union {
+    struct {
+        /** raw_buf_depth : RO; bitpos: [13:0]; default: 0;
+         *  this field configures the depth of dsi_bridge fifo depth
+         */
+        uint32_t raw_buf_depth:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_brg_fifo_flow_status_reg_t;
+
+/** Type of host_bist_ctl register
+ *  dsi_bridge host bist control register
+ */
+typedef union {
+    struct {
+        /** bistok : RO; bitpos: [0]; default: 0;
+         *  bistok
+         */
+        uint32_t bistok:1;
+        /** biston : R/W; bitpos: [1]; default: 0;
+         *  biston
+         */
+        uint32_t biston:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_host_bist_ctl_reg_t;
+
+/** Type of rdn_eco_cs register
+ *  dsi_bridge rdn eco cs register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  rdn_eco_en
+         */
+        uint32_t rdn_eco_en:1;
+        /** rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  rdn_eco_result
+         */
+        uint32_t rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_cs_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_ena register
+ *  dsi_bridge interrupt enable register
+ */
+typedef union {
+    struct {
+        /** underrun_int_ena : R/W; bitpos: [0]; default: 0;
+         *  write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled
+         *  by dpi_underrun  interrupt signal
+         */
+        uint32_t underrun_int_ena:1;
+        /** vsync_int_ena : R/W; bitpos: [1]; default: 0;
+         *  write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by
+         *  dpi_vsync  interrupt signal
+         */
+        uint32_t vsync_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  dsi_bridge interrupt clear register
+ */
+typedef union {
+    struct {
+        /** underrun_int_clr : WT; bitpos: [0]; default: 0;
+         *  write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+         */
+        uint32_t underrun_int_clr:1;
+        /** vsync_int_clr : WT; bitpos: [1]; default: 0;
+         *  write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+         */
+        uint32_t vsync_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_int_clr_reg_t;
+
+/** Type of int_raw register
+ *  dsi_bridge raw interrupt register
+ */
+typedef union {
+    struct {
+        /** underrun_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  the raw interrupt status of dpi_underrun
+         */
+        uint32_t underrun_int_raw:1;
+        /** vsync_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  the raw interrupt status of dpi_vsync
+         */
+        uint32_t vsync_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_int_raw_reg_t;
+
+/** Type of int_st register
+ *  dsi_bridge masked interrupt register
+ */
+typedef union {
+    struct {
+        /** underrun_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of dpi_underrun
+         */
+        uint32_t underrun_int_st:1;
+        /** vsync_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of dpi_vsync
+         */
+        uint32_t vsync_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_int_st_reg_t;
+
+
+/** Group: Version Register */
+/** Type of ver_date register
+ *  version control register
+ */
+typedef union {
+    struct {
+        /** ver_data : R/W; bitpos: [31:0]; default: 539296009;
+         *  Represents csv version
+         */
+        uint32_t ver_data:32;
+    };
+    uint32_t val;
+} dsi_brg_ver_date_reg_t;
+
+
+typedef struct {
+    volatile dsi_brg_clk_en_reg_t clk_en;
+    volatile dsi_brg_en_reg_t en;
+    volatile dsi_brg_dma_req_cfg_reg_t dma_req_cfg;
+    volatile dsi_brg_raw_num_cfg_reg_t raw_num_cfg;
+    volatile dsi_brg_raw_buf_credit_ctl_reg_t raw_buf_credit_ctl;
+    volatile dsi_brg_fifo_flow_status_reg_t fifo_flow_status;
+    volatile dsi_brg_pixel_type_reg_t pixel_type;
+    volatile dsi_brg_dma_block_interval_reg_t dma_block_interval;
+    volatile dsi_brg_dma_req_interval_reg_t dma_req_interval;
+    volatile dsi_brg_dpi_lcd_ctl_reg_t dpi_lcd_ctl;
+    volatile dsi_brg_dpi_rsv_dpi_data_reg_t dpi_rsv_dpi_data;
+    uint32_t reserved_02c;
+    volatile dsi_brg_dpi_v_cfg0_reg_t dpi_v_cfg0;
+    volatile dsi_brg_dpi_v_cfg1_reg_t dpi_v_cfg1;
+    volatile dsi_brg_dpi_h_cfg0_reg_t dpi_h_cfg0;
+    volatile dsi_brg_dpi_h_cfg1_reg_t dpi_h_cfg1;
+    volatile dsi_brg_dpi_misc_config_reg_t dpi_misc_config;
+    volatile dsi_brg_dpi_config_update_reg_t dpi_config_update;
+    uint32_t reserved_048[2];
+    volatile dsi_brg_int_ena_reg_t int_ena;
+    volatile dsi_brg_int_clr_reg_t int_clr;
+    volatile dsi_brg_int_raw_reg_t int_raw;
+    volatile dsi_brg_int_st_reg_t int_st;
+    volatile dsi_brg_host_bist_ctl_reg_t host_bist_ctl;
+    volatile dsi_brg_host_trigger_rev_reg_t host_trigger_rev;
+    volatile dsi_brg_blk_raw_num_cfg_reg_t blk_raw_num_cfg;
+    volatile dsi_brg_dma_frame_interval_reg_t dma_frame_interval;
+    volatile dsi_brg_mem_aux_ctrl_reg_t mem_aux_ctrl;
+    volatile dsi_brg_rdn_eco_cs_reg_t rdn_eco_cs;
+    volatile dsi_brg_rdn_eco_low_reg_t rdn_eco_low;
+    volatile dsi_brg_rdn_eco_high_reg_t rdn_eco_high;
+    volatile dsi_brg_host_ctrl_reg_t host_ctrl;
+    volatile dsi_brg_mem_clk_ctrl_reg_t mem_clk_ctrl;
+    volatile dsi_brg_dma_flow_ctrl_reg_t dma_flow_ctrl;
+    volatile dsi_brg_raw_buf_almost_empty_thrd_reg_t raw_buf_almost_empty_thrd;
+    volatile dsi_brg_yuv_cfg_reg_t yuv_cfg;
+    volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl;
+    volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl;
+    volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt;
+    uint32_t reserved_0a0[24];
+    volatile dsi_brg_ver_date_reg_t ver_date;
+} dsi_brg_dev_t;
+
+extern dsi_brg_dev_t MIPI_DSI_BRIDGE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dsi_brg_dev_t) == 0x104, "Invalid size of dsi_brg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_reg.h
new file mode 100644
index 0000000000..b63d11181d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_reg.h
@@ -0,0 +1,907 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DSI_BRG_CLK_EN_REG register
+ *  dsi bridge clk control register
+ */
+#define DSI_BRG_CLK_EN_REG (DR_REG_DSI_BRG_BASE + 0x0)
+/** DSI_BRG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures force_on of dsi_bridge register clock gate
+ */
+#define DSI_BRG_CLK_EN    (BIT(0))
+#define DSI_BRG_CLK_EN_M  (DSI_BRG_CLK_EN_V << DSI_BRG_CLK_EN_S)
+#define DSI_BRG_CLK_EN_V  0x00000001U
+#define DSI_BRG_CLK_EN_S  0
+
+/** DSI_BRG_EN_REG register
+ *  dsi bridge en register
+ */
+#define DSI_BRG_EN_REG (DR_REG_DSI_BRG_BASE + 0x4)
+/** DSI_BRG_DSI_EN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures module enable of dsi_bridge. 0: disable, 1: enable
+ */
+#define DSI_BRG_DSI_EN    (BIT(0))
+#define DSI_BRG_DSI_EN_M  (DSI_BRG_DSI_EN_V << DSI_BRG_DSI_EN_S)
+#define DSI_BRG_DSI_EN_V  0x00000001U
+#define DSI_BRG_DSI_EN_S  0
+/** DSI_BRG_DSI_BRIG_RST : R/W; bitpos: [1]; default: 0;
+ *  Configures software reset of dsi_bridge. 0: release reset, 1: reset
+ */
+#define DSI_BRG_DSI_BRIG_RST    (BIT(1))
+#define DSI_BRG_DSI_BRIG_RST_M  (DSI_BRG_DSI_BRIG_RST_V << DSI_BRG_DSI_BRIG_RST_S)
+#define DSI_BRG_DSI_BRIG_RST_V  0x00000001U
+#define DSI_BRG_DSI_BRIG_RST_S  1
+
+/** DSI_BRG_DMA_REQ_CFG_REG register
+ *  dsi bridge dma burst len register
+ */
+#define DSI_BRG_DMA_REQ_CFG_REG (DR_REG_DSI_BRG_BASE + 0x8)
+/** DSI_BRG_DMA_BURST_LEN : R/W; bitpos: [11:0]; default: 128;
+ *  this field configures the num of 64-bit in one dma burst transfer, valid only when
+ *  dsi_bridge as flow controller
+ */
+#define DSI_BRG_DMA_BURST_LEN    0x00000FFFU
+#define DSI_BRG_DMA_BURST_LEN_M  (DSI_BRG_DMA_BURST_LEN_V << DSI_BRG_DMA_BURST_LEN_S)
+#define DSI_BRG_DMA_BURST_LEN_V  0x00000FFFU
+#define DSI_BRG_DMA_BURST_LEN_S  0
+
+/** DSI_BRG_RAW_NUM_CFG_REG register
+ *  dsi bridge raw number control register
+ */
+#define DSI_BRG_RAW_NUM_CFG_REG (DR_REG_DSI_BRG_BASE + 0xc)
+/** DSI_BRG_RAW_NUM_TOTAL : R/W; bitpos: [21:0]; default: 230400;
+ *  this field configures number of total pix bits/64
+ */
+#define DSI_BRG_RAW_NUM_TOTAL    0x003FFFFFU
+#define DSI_BRG_RAW_NUM_TOTAL_M  (DSI_BRG_RAW_NUM_TOTAL_V << DSI_BRG_RAW_NUM_TOTAL_S)
+#define DSI_BRG_RAW_NUM_TOTAL_V  0x003FFFFFU
+#define DSI_BRG_RAW_NUM_TOTAL_S  0
+/** DSI_BRG_UNALIGN_64BIT_EN : R/W; bitpos: [22]; default: 0;
+ *  this field configures whether the total pix bits is a multiple of 64bits. 0: align
+ *  to 64-bit, 1: unalign to 64-bit
+ */
+#define DSI_BRG_UNALIGN_64BIT_EN    (BIT(22))
+#define DSI_BRG_UNALIGN_64BIT_EN_M  (DSI_BRG_UNALIGN_64BIT_EN_V << DSI_BRG_UNALIGN_64BIT_EN_S)
+#define DSI_BRG_UNALIGN_64BIT_EN_V  0x00000001U
+#define DSI_BRG_UNALIGN_64BIT_EN_S  22
+/** DSI_BRG_RAW_NUM_TOTAL_SET : WT; bitpos: [31]; default: 0;
+ *  this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable,
+ *  1: enable. valid only when dsi_bridge as flow controller
+ */
+#define DSI_BRG_RAW_NUM_TOTAL_SET    (BIT(31))
+#define DSI_BRG_RAW_NUM_TOTAL_SET_M  (DSI_BRG_RAW_NUM_TOTAL_SET_V << DSI_BRG_RAW_NUM_TOTAL_SET_S)
+#define DSI_BRG_RAW_NUM_TOTAL_SET_V  0x00000001U
+#define DSI_BRG_RAW_NUM_TOTAL_SET_S  31
+
+/** DSI_BRG_RAW_BUF_CREDIT_CTL_REG register
+ *  dsi bridge credit register
+ */
+#define DSI_BRG_RAW_BUF_CREDIT_CTL_REG (DR_REG_DSI_BRG_BASE + 0x10)
+/** DSI_BRG_CREDIT_THRD : R/W; bitpos: [14:0]; default: 1024;
+ *  this field configures the threshold whether dsi_bridge fifo can receive one more
+ *  64-bit, valid only when dsi_bridge as flow controller
+ */
+#define DSI_BRG_CREDIT_THRD    0x00007FFFU
+#define DSI_BRG_CREDIT_THRD_M  (DSI_BRG_CREDIT_THRD_V << DSI_BRG_CREDIT_THRD_S)
+#define DSI_BRG_CREDIT_THRD_V  0x00007FFFU
+#define DSI_BRG_CREDIT_THRD_S  0
+/** DSI_BRG_CREDIT_BURST_THRD : R/W; bitpos: [30:16]; default: 800;
+ *  this field configures the threshold whether dsi_bridge fifo can receive one more
+ *  dma burst, valid only when dsi_bridge as flow controller
+ */
+#define DSI_BRG_CREDIT_BURST_THRD    0x00007FFFU
+#define DSI_BRG_CREDIT_BURST_THRD_M  (DSI_BRG_CREDIT_BURST_THRD_V << DSI_BRG_CREDIT_BURST_THRD_S)
+#define DSI_BRG_CREDIT_BURST_THRD_V  0x00007FFFU
+#define DSI_BRG_CREDIT_BURST_THRD_S  16
+/** DSI_BRG_CREDIT_RESET : R/W; bitpos: [31]; default: 0;
+ *  this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when
+ *  dsi_bridge as flow controller
+ */
+#define DSI_BRG_CREDIT_RESET    (BIT(31))
+#define DSI_BRG_CREDIT_RESET_M  (DSI_BRG_CREDIT_RESET_V << DSI_BRG_CREDIT_RESET_S)
+#define DSI_BRG_CREDIT_RESET_V  0x00000001U
+#define DSI_BRG_CREDIT_RESET_S  31
+
+/** DSI_BRG_FIFO_FLOW_STATUS_REG register
+ *  dsi bridge raw buffer depth register
+ */
+#define DSI_BRG_FIFO_FLOW_STATUS_REG (DR_REG_DSI_BRG_BASE + 0x14)
+/** DSI_BRG_RAW_BUF_DEPTH : RO; bitpos: [13:0]; default: 0;
+ *  this field configures the depth of dsi_bridge fifo depth
+ */
+#define DSI_BRG_RAW_BUF_DEPTH    0x00003FFFU
+#define DSI_BRG_RAW_BUF_DEPTH_M  (DSI_BRG_RAW_BUF_DEPTH_V << DSI_BRG_RAW_BUF_DEPTH_S)
+#define DSI_BRG_RAW_BUF_DEPTH_V  0x00003FFFU
+#define DSI_BRG_RAW_BUF_DEPTH_S  0
+
+/** DSI_BRG_PIXEL_TYPE_REG register
+ *  dsi bridge dpi type control register
+ */
+#define DSI_BRG_PIXEL_TYPE_REG (DR_REG_DSI_BRG_BASE + 0x18)
+/** DSI_BRG_RAW_TYPE : R/W; bitpos: [3:0]; default: 0;
+ *  this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444,
+ *  9:yuv422, 10:yuv420, 12:gray
+ */
+#define DSI_BRG_RAW_TYPE    0x0000000FU
+#define DSI_BRG_RAW_TYPE_M  (DSI_BRG_RAW_TYPE_V << DSI_BRG_RAW_TYPE_S)
+#define DSI_BRG_RAW_TYPE_V  0x0000000FU
+#define DSI_BRG_RAW_TYPE_S  0
+/** DSI_BRG_DPI_CONFIG : R/W; bitpos: [5:4]; default: 0;
+ *  this field configures the pixel arrange type of dpi interface
+ */
+#define DSI_BRG_DPI_CONFIG    0x00000003U
+#define DSI_BRG_DPI_CONFIG_M  (DSI_BRG_DPI_CONFIG_V << DSI_BRG_DPI_CONFIG_S)
+#define DSI_BRG_DPI_CONFIG_V  0x00000003U
+#define DSI_BRG_DPI_CONFIG_S  4
+/** DSI_BRG_DATA_IN_TYPE : R/W; bitpos: [6]; default: 0;
+ *  input data type, 0: not yuv, 1: yuv
+ */
+#define DSI_BRG_DATA_IN_TYPE    (BIT(6))
+#define DSI_BRG_DATA_IN_TYPE_M  (DSI_BRG_DATA_IN_TYPE_V << DSI_BRG_DATA_IN_TYPE_S)
+#define DSI_BRG_DATA_IN_TYPE_V  0x00000001U
+#define DSI_BRG_DATA_IN_TYPE_S  6
+/** DSI_BRG_DPI_TYPE : R/W; bitpos: [10:7]; default: 0;
+ *  this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565
+ */
+#define DSI_BRG_DPI_TYPE    0x0000000FU
+#define DSI_BRG_DPI_TYPE_M  (DSI_BRG_DPI_TYPE_V << DSI_BRG_DPI_TYPE_S)
+#define DSI_BRG_DPI_TYPE_V  0x0000000FU
+#define DSI_BRG_DPI_TYPE_S  7
+
+/** DSI_BRG_DMA_BLOCK_INTERVAL_REG register
+ *  dsi bridge dma block interval control register
+ */
+#define DSI_BRG_DMA_BLOCK_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x1c)
+/** DSI_BRG_DMA_BLOCK_SLOT : R/W; bitpos: [9:0]; default: 9;
+ *  this field configures the max block_slot_cnt
+ */
+#define DSI_BRG_DMA_BLOCK_SLOT    0x000003FFU
+#define DSI_BRG_DMA_BLOCK_SLOT_M  (DSI_BRG_DMA_BLOCK_SLOT_V << DSI_BRG_DMA_BLOCK_SLOT_S)
+#define DSI_BRG_DMA_BLOCK_SLOT_V  0x000003FFU
+#define DSI_BRG_DMA_BLOCK_SLOT_S  0
+/** DSI_BRG_DMA_BLOCK_INTERVAL : R/W; bitpos: [27:10]; default: 9;
+ *  this field configures the max block_interval_cnt, block_interval_cnt increased by 1
+ *  when block_slot_cnt if full
+ */
+#define DSI_BRG_DMA_BLOCK_INTERVAL    0x0003FFFFU
+#define DSI_BRG_DMA_BLOCK_INTERVAL_M  (DSI_BRG_DMA_BLOCK_INTERVAL_V << DSI_BRG_DMA_BLOCK_INTERVAL_S)
+#define DSI_BRG_DMA_BLOCK_INTERVAL_V  0x0003FFFFU
+#define DSI_BRG_DMA_BLOCK_INTERVAL_S  10
+/** DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD : R/W; bitpos: [28]; default: 1;
+ *  this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable
+ */
+#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD    (BIT(28))
+#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_M  (DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_V << DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_S)
+#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_V  0x00000001U
+#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_S  28
+/** DSI_BRG_DMA_BLOCK_INTERVAL_EN : R/W; bitpos: [29]; default: 1;
+ *  this bit configures enable of interval between dma block transfer, 0: disable, 1:
+ *  enable
+ */
+#define DSI_BRG_DMA_BLOCK_INTERVAL_EN    (BIT(29))
+#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_M  (DSI_BRG_DMA_BLOCK_INTERVAL_EN_V << DSI_BRG_DMA_BLOCK_INTERVAL_EN_S)
+#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_V  0x00000001U
+#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_S  29
+
+/** DSI_BRG_DMA_REQ_INTERVAL_REG register
+ *  dsi bridge dma req interval control register
+ */
+#define DSI_BRG_DMA_REQ_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x20)
+/** DSI_BRG_DMA_REQ_INTERVAL : R/W; bitpos: [15:0]; default: 1;
+ *  this field configures the interval between dma req events
+ */
+#define DSI_BRG_DMA_REQ_INTERVAL    0x0000FFFFU
+#define DSI_BRG_DMA_REQ_INTERVAL_M  (DSI_BRG_DMA_REQ_INTERVAL_V << DSI_BRG_DMA_REQ_INTERVAL_S)
+#define DSI_BRG_DMA_REQ_INTERVAL_V  0x0000FFFFU
+#define DSI_BRG_DMA_REQ_INTERVAL_S  0
+
+/** DSI_BRG_DPI_LCD_CTL_REG register
+ *  dsi bridge dpi signal control register
+ */
+#define DSI_BRG_DPI_LCD_CTL_REG (DR_REG_DSI_BRG_BASE + 0x24)
+/** DSI_BRG_DPISHUTDN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures dpishutdn signal in dpi interface
+ */
+#define DSI_BRG_DPISHUTDN    (BIT(0))
+#define DSI_BRG_DPISHUTDN_M  (DSI_BRG_DPISHUTDN_V << DSI_BRG_DPISHUTDN_S)
+#define DSI_BRG_DPISHUTDN_V  0x00000001U
+#define DSI_BRG_DPISHUTDN_S  0
+/** DSI_BRG_DPICOLORM : R/W; bitpos: [1]; default: 0;
+ *  this bit configures dpicolorm signal in dpi interface
+ */
+#define DSI_BRG_DPICOLORM    (BIT(1))
+#define DSI_BRG_DPICOLORM_M  (DSI_BRG_DPICOLORM_V << DSI_BRG_DPICOLORM_S)
+#define DSI_BRG_DPICOLORM_V  0x00000001U
+#define DSI_BRG_DPICOLORM_S  1
+/** DSI_BRG_DPIUPDATECFG : R/W; bitpos: [2]; default: 0;
+ *  this bit configures dpiupdatecfg signal in dpi interface
+ */
+#define DSI_BRG_DPIUPDATECFG    (BIT(2))
+#define DSI_BRG_DPIUPDATECFG_M  (DSI_BRG_DPIUPDATECFG_V << DSI_BRG_DPIUPDATECFG_S)
+#define DSI_BRG_DPIUPDATECFG_V  0x00000001U
+#define DSI_BRG_DPIUPDATECFG_S  2
+
+/** DSI_BRG_DPI_RSV_DPI_DATA_REG register
+ *  dsi bridge dpi reserved data register
+ */
+#define DSI_BRG_DPI_RSV_DPI_DATA_REG (DR_REG_DSI_BRG_BASE + 0x28)
+/** DSI_BRG_DPI_RSV_DATA : R/W; bitpos: [29:0]; default: 16383;
+ *  this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
+ */
+#define DSI_BRG_DPI_RSV_DATA    0x3FFFFFFFU
+#define DSI_BRG_DPI_RSV_DATA_M  (DSI_BRG_DPI_RSV_DATA_V << DSI_BRG_DPI_RSV_DATA_S)
+#define DSI_BRG_DPI_RSV_DATA_V  0x3FFFFFFFU
+#define DSI_BRG_DPI_RSV_DATA_S  0
+/** DSI_BRG_DPI_DBG_EN : R/W; bitpos: [30]; default: 0;
+ *  Configures data debug feature enable. 0: disable, 1: enable
+ */
+#define DSI_BRG_DPI_DBG_EN    (BIT(30))
+#define DSI_BRG_DPI_DBG_EN_M  (DSI_BRG_DPI_DBG_EN_V << DSI_BRG_DPI_DBG_EN_S)
+#define DSI_BRG_DPI_DBG_EN_V  0x00000001U
+#define DSI_BRG_DPI_DBG_EN_S  30
+
+/** DSI_BRG_DPI_V_CFG0_REG register
+ *  dsi bridge dpi v config register 0
+ */
+#define DSI_BRG_DPI_V_CFG0_REG (DR_REG_DSI_BRG_BASE + 0x30)
+/** DSI_BRG_VTOTAL : R/W; bitpos: [11:0]; default: 525;
+ *  this field configures the total length of one frame (by line) for dpi output, must
+ *  meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank
+ */
+#define DSI_BRG_VTOTAL    0x00000FFFU
+#define DSI_BRG_VTOTAL_M  (DSI_BRG_VTOTAL_V << DSI_BRG_VTOTAL_S)
+#define DSI_BRG_VTOTAL_V  0x00000FFFU
+#define DSI_BRG_VTOTAL_S  0
+/** DSI_BRG_VDISP : R/W; bitpos: [27:16]; default: 480;
+ *  this field configures the length of valid line (by line) for dpi output
+ */
+#define DSI_BRG_VDISP    0x00000FFFU
+#define DSI_BRG_VDISP_M  (DSI_BRG_VDISP_V << DSI_BRG_VDISP_S)
+#define DSI_BRG_VDISP_V  0x00000FFFU
+#define DSI_BRG_VDISP_S  16
+
+/** DSI_BRG_DPI_V_CFG1_REG register
+ *  dsi bridge dpi v config register 1
+ */
+#define DSI_BRG_DPI_V_CFG1_REG (DR_REG_DSI_BRG_BASE + 0x34)
+/** DSI_BRG_VBANK : R/W; bitpos: [11:0]; default: 33;
+ *  this field configures the length between vsync and valid line (by line) for dpi
+ *  output
+ */
+#define DSI_BRG_VBANK    0x00000FFFU
+#define DSI_BRG_VBANK_M  (DSI_BRG_VBANK_V << DSI_BRG_VBANK_S)
+#define DSI_BRG_VBANK_V  0x00000FFFU
+#define DSI_BRG_VBANK_S  0
+/** DSI_BRG_VSYNC : R/W; bitpos: [27:16]; default: 2;
+ *  this field configures the length of vsync (by line) for dpi output
+ */
+#define DSI_BRG_VSYNC    0x00000FFFU
+#define DSI_BRG_VSYNC_M  (DSI_BRG_VSYNC_V << DSI_BRG_VSYNC_S)
+#define DSI_BRG_VSYNC_V  0x00000FFFU
+#define DSI_BRG_VSYNC_S  16
+
+/** DSI_BRG_DPI_H_CFG0_REG register
+ *  dsi bridge dpi h config register 0
+ */
+#define DSI_BRG_DPI_H_CFG0_REG (DR_REG_DSI_BRG_BASE + 0x38)
+/** DSI_BRG_HTOTAL : R/W; bitpos: [11:0]; default: 800;
+ *  this field configures the total length of one line (by pixel num) for dpi output,
+ *  must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank
+ */
+#define DSI_BRG_HTOTAL    0x00000FFFU
+#define DSI_BRG_HTOTAL_M  (DSI_BRG_HTOTAL_V << DSI_BRG_HTOTAL_S)
+#define DSI_BRG_HTOTAL_V  0x00000FFFU
+#define DSI_BRG_HTOTAL_S  0
+/** DSI_BRG_HDISP : R/W; bitpos: [27:16]; default: 640;
+ *  this field configures the length of valid pixel data (by pixel num) for dpi output
+ */
+#define DSI_BRG_HDISP    0x00000FFFU
+#define DSI_BRG_HDISP_M  (DSI_BRG_HDISP_V << DSI_BRG_HDISP_S)
+#define DSI_BRG_HDISP_V  0x00000FFFU
+#define DSI_BRG_HDISP_S  16
+
+/** DSI_BRG_DPI_H_CFG1_REG register
+ *  dsi bridge dpi h config register 1
+ */
+#define DSI_BRG_DPI_H_CFG1_REG (DR_REG_DSI_BRG_BASE + 0x3c)
+/** DSI_BRG_HBANK : R/W; bitpos: [11:0]; default: 48;
+ *  this field configures the length between hsync and pixel data valid (by pixel num)
+ *  for dpi output
+ */
+#define DSI_BRG_HBANK    0x00000FFFU
+#define DSI_BRG_HBANK_M  (DSI_BRG_HBANK_V << DSI_BRG_HBANK_S)
+#define DSI_BRG_HBANK_V  0x00000FFFU
+#define DSI_BRG_HBANK_S  0
+/** DSI_BRG_HSYNC : R/W; bitpos: [27:16]; default: 96;
+ *  this field configures the length of hsync (by pixel num) for dpi output
+ */
+#define DSI_BRG_HSYNC    0x00000FFFU
+#define DSI_BRG_HSYNC_M  (DSI_BRG_HSYNC_V << DSI_BRG_HSYNC_S)
+#define DSI_BRG_HSYNC_V  0x00000FFFU
+#define DSI_BRG_HSYNC_S  16
+
+/** DSI_BRG_DPI_MISC_CONFIG_REG register
+ *  dsi_bridge dpi misc config register
+ */
+#define DSI_BRG_DPI_MISC_CONFIG_REG (DR_REG_DSI_BRG_BASE + 0x40)
+/** DSI_BRG_DPI_EN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures enable of dpi output, 0: disable, 1: enable
+ */
+#define DSI_BRG_DPI_EN    (BIT(0))
+#define DSI_BRG_DPI_EN_M  (DSI_BRG_DPI_EN_V << DSI_BRG_DPI_EN_S)
+#define DSI_BRG_DPI_EN_V  0x00000001U
+#define DSI_BRG_DPI_EN_S  0
+/** DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT : R/W; bitpos: [15:4]; default: 413;
+ *  this field configures the underrun interrupt musk, when underrun occurs and line
+ *  cnt is less then this field
+ */
+#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT    0x00000FFFU
+#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_M  (DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_V << DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_S)
+#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_V  0x00000FFFU
+#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_S  4
+
+/** DSI_BRG_DPI_CONFIG_UPDATE_REG register
+ *  dsi_bridge dpi config update register
+ */
+#define DSI_BRG_DPI_CONFIG_UPDATE_REG (DR_REG_DSI_BRG_BASE + 0x44)
+/** DSI_BRG_DPI_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*
+ */
+#define DSI_BRG_DPI_CONFIG_UPDATE    (BIT(0))
+#define DSI_BRG_DPI_CONFIG_UPDATE_M  (DSI_BRG_DPI_CONFIG_UPDATE_V << DSI_BRG_DPI_CONFIG_UPDATE_S)
+#define DSI_BRG_DPI_CONFIG_UPDATE_V  0x00000001U
+#define DSI_BRG_DPI_CONFIG_UPDATE_S  0
+
+/** DSI_BRG_INT_ENA_REG register
+ *  dsi_bridge interrupt enable register
+ */
+#define DSI_BRG_INT_ENA_REG (DR_REG_DSI_BRG_BASE + 0x50)
+/** DSI_BRG_UNDERRUN_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled
+ *  by dpi_underrun  interrupt signal
+ */
+#define DSI_BRG_UNDERRUN_INT_ENA    (BIT(0))
+#define DSI_BRG_UNDERRUN_INT_ENA_M  (DSI_BRG_UNDERRUN_INT_ENA_V << DSI_BRG_UNDERRUN_INT_ENA_S)
+#define DSI_BRG_UNDERRUN_INT_ENA_V  0x00000001U
+#define DSI_BRG_UNDERRUN_INT_ENA_S  0
+/** DSI_BRG_VSYNC_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by
+ *  dpi_vsync  interrupt signal
+ */
+#define DSI_BRG_VSYNC_INT_ENA    (BIT(1))
+#define DSI_BRG_VSYNC_INT_ENA_M  (DSI_BRG_VSYNC_INT_ENA_V << DSI_BRG_VSYNC_INT_ENA_S)
+#define DSI_BRG_VSYNC_INT_ENA_V  0x00000001U
+#define DSI_BRG_VSYNC_INT_ENA_S  1
+
+/** DSI_BRG_INT_CLR_REG register
+ *  dsi_bridge interrupt clear register
+ */
+#define DSI_BRG_INT_CLR_REG (DR_REG_DSI_BRG_BASE + 0x54)
+/** DSI_BRG_UNDERRUN_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+ */
+#define DSI_BRG_UNDERRUN_INT_CLR    (BIT(0))
+#define DSI_BRG_UNDERRUN_INT_CLR_M  (DSI_BRG_UNDERRUN_INT_CLR_V << DSI_BRG_UNDERRUN_INT_CLR_S)
+#define DSI_BRG_UNDERRUN_INT_CLR_V  0x00000001U
+#define DSI_BRG_UNDERRUN_INT_CLR_S  0
+/** DSI_BRG_VSYNC_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+ */
+#define DSI_BRG_VSYNC_INT_CLR    (BIT(1))
+#define DSI_BRG_VSYNC_INT_CLR_M  (DSI_BRG_VSYNC_INT_CLR_V << DSI_BRG_VSYNC_INT_CLR_S)
+#define DSI_BRG_VSYNC_INT_CLR_V  0x00000001U
+#define DSI_BRG_VSYNC_INT_CLR_S  1
+
+/** DSI_BRG_INT_RAW_REG register
+ *  dsi_bridge raw interrupt register
+ */
+#define DSI_BRG_INT_RAW_REG (DR_REG_DSI_BRG_BASE + 0x58)
+/** DSI_BRG_UNDERRUN_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  the raw interrupt status of dpi_underrun
+ */
+#define DSI_BRG_UNDERRUN_INT_RAW    (BIT(0))
+#define DSI_BRG_UNDERRUN_INT_RAW_M  (DSI_BRG_UNDERRUN_INT_RAW_V << DSI_BRG_UNDERRUN_INT_RAW_S)
+#define DSI_BRG_UNDERRUN_INT_RAW_V  0x00000001U
+#define DSI_BRG_UNDERRUN_INT_RAW_S  0
+/** DSI_BRG_VSYNC_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  the raw interrupt status of dpi_vsync
+ */
+#define DSI_BRG_VSYNC_INT_RAW    (BIT(1))
+#define DSI_BRG_VSYNC_INT_RAW_M  (DSI_BRG_VSYNC_INT_RAW_V << DSI_BRG_VSYNC_INT_RAW_S)
+#define DSI_BRG_VSYNC_INT_RAW_V  0x00000001U
+#define DSI_BRG_VSYNC_INT_RAW_S  1
+
+/** DSI_BRG_INT_ST_REG register
+ *  dsi_bridge masked interrupt register
+ */
+#define DSI_BRG_INT_ST_REG (DR_REG_DSI_BRG_BASE + 0x5c)
+/** DSI_BRG_UNDERRUN_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of dpi_underrun
+ */
+#define DSI_BRG_UNDERRUN_INT_ST    (BIT(0))
+#define DSI_BRG_UNDERRUN_INT_ST_M  (DSI_BRG_UNDERRUN_INT_ST_V << DSI_BRG_UNDERRUN_INT_ST_S)
+#define DSI_BRG_UNDERRUN_INT_ST_V  0x00000001U
+#define DSI_BRG_UNDERRUN_INT_ST_S  0
+/** DSI_BRG_VSYNC_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of dpi_vsync
+ */
+#define DSI_BRG_VSYNC_INT_ST    (BIT(1))
+#define DSI_BRG_VSYNC_INT_ST_M  (DSI_BRG_VSYNC_INT_ST_V << DSI_BRG_VSYNC_INT_ST_S)
+#define DSI_BRG_VSYNC_INT_ST_V  0x00000001U
+#define DSI_BRG_VSYNC_INT_ST_S  1
+
+/** DSI_BRG_HOST_BIST_CTL_REG register
+ *  dsi_bridge host bist control register
+ */
+#define DSI_BRG_HOST_BIST_CTL_REG (DR_REG_DSI_BRG_BASE + 0x60)
+/** DSI_BRG_BISTOK : RO; bitpos: [0]; default: 0;
+ *  bistok
+ */
+#define DSI_BRG_BISTOK    (BIT(0))
+#define DSI_BRG_BISTOK_M  (DSI_BRG_BISTOK_V << DSI_BRG_BISTOK_S)
+#define DSI_BRG_BISTOK_V  0x00000001U
+#define DSI_BRG_BISTOK_S  0
+/** DSI_BRG_BISTON : R/W; bitpos: [1]; default: 0;
+ *  biston
+ */
+#define DSI_BRG_BISTON    (BIT(1))
+#define DSI_BRG_BISTON_M  (DSI_BRG_BISTON_V << DSI_BRG_BISTON_S)
+#define DSI_BRG_BISTON_V  0x00000001U
+#define DSI_BRG_BISTON_S  1
+
+/** DSI_BRG_HOST_TRIGGER_REV_REG register
+ *  dsi_bridge host trigger reverse control register
+ */
+#define DSI_BRG_HOST_TRIGGER_REV_REG (DR_REG_DSI_BRG_BASE + 0x64)
+/** DSI_BRG_TX_TRIGGER_REV_EN : R/W; bitpos: [0]; default: 0;
+ *  tx_trigger reverse. 0: disable, 1: enable
+ */
+#define DSI_BRG_TX_TRIGGER_REV_EN    (BIT(0))
+#define DSI_BRG_TX_TRIGGER_REV_EN_M  (DSI_BRG_TX_TRIGGER_REV_EN_V << DSI_BRG_TX_TRIGGER_REV_EN_S)
+#define DSI_BRG_TX_TRIGGER_REV_EN_V  0x00000001U
+#define DSI_BRG_TX_TRIGGER_REV_EN_S  0
+/** DSI_BRG_RX_TRIGGER_REV_EN : R/W; bitpos: [1]; default: 0;
+ *  rx_trigger reverse. 0: disable, 1: enable
+ */
+#define DSI_BRG_RX_TRIGGER_REV_EN    (BIT(1))
+#define DSI_BRG_RX_TRIGGER_REV_EN_M  (DSI_BRG_RX_TRIGGER_REV_EN_V << DSI_BRG_RX_TRIGGER_REV_EN_S)
+#define DSI_BRG_RX_TRIGGER_REV_EN_V  0x00000001U
+#define DSI_BRG_RX_TRIGGER_REV_EN_S  1
+
+/** DSI_BRG_BLK_RAW_NUM_CFG_REG register
+ *  dsi_bridge block raw number control register
+ */
+#define DSI_BRG_BLK_RAW_NUM_CFG_REG (DR_REG_DSI_BRG_BASE + 0x68)
+/** DSI_BRG_BLK_RAW_NUM_TOTAL : R/W; bitpos: [21:0]; default: 230400;
+ *  this field configures number of total block pix bits/64
+ */
+#define DSI_BRG_BLK_RAW_NUM_TOTAL    0x003FFFFFU
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_M  (DSI_BRG_BLK_RAW_NUM_TOTAL_V << DSI_BRG_BLK_RAW_NUM_TOTAL_S)
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_V  0x003FFFFFU
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_S  0
+/** DSI_BRG_BLK_RAW_NUM_TOTAL_SET : WT; bitpos: [31]; default: 0;
+ *  write 1 to reload reg_blk_raw_num_total to internal cnt
+ */
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET    (BIT(31))
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_M  (DSI_BRG_BLK_RAW_NUM_TOTAL_SET_V << DSI_BRG_BLK_RAW_NUM_TOTAL_SET_S)
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_V  0x00000001U
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_S  31
+
+/** DSI_BRG_DMA_FRAME_INTERVAL_REG register
+ *  dsi_bridge dam frame interval control register
+ */
+#define DSI_BRG_DMA_FRAME_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x6c)
+/** DSI_BRG_DMA_FRAME_SLOT : R/W; bitpos: [9:0]; default: 9;
+ *  this field configures the max frame_slot_cnt
+ */
+#define DSI_BRG_DMA_FRAME_SLOT    0x000003FFU
+#define DSI_BRG_DMA_FRAME_SLOT_M  (DSI_BRG_DMA_FRAME_SLOT_V << DSI_BRG_DMA_FRAME_SLOT_S)
+#define DSI_BRG_DMA_FRAME_SLOT_V  0x000003FFU
+#define DSI_BRG_DMA_FRAME_SLOT_S  0
+/** DSI_BRG_DMA_FRAME_INTERVAL : R/W; bitpos: [27:10]; default: 9;
+ *  this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1
+ *  when frame_slot_cnt if full
+ */
+#define DSI_BRG_DMA_FRAME_INTERVAL    0x0003FFFFU
+#define DSI_BRG_DMA_FRAME_INTERVAL_M  (DSI_BRG_DMA_FRAME_INTERVAL_V << DSI_BRG_DMA_FRAME_INTERVAL_S)
+#define DSI_BRG_DMA_FRAME_INTERVAL_V  0x0003FFFFU
+#define DSI_BRG_DMA_FRAME_INTERVAL_S  10
+/** DSI_BRG_DMA_MULTIBLK_EN : R/W; bitpos: [28]; default: 0;
+ *  this bit configures enable multi-blk transfer, 0: disable, 1: enable
+ */
+#define DSI_BRG_DMA_MULTIBLK_EN    (BIT(28))
+#define DSI_BRG_DMA_MULTIBLK_EN_M  (DSI_BRG_DMA_MULTIBLK_EN_V << DSI_BRG_DMA_MULTIBLK_EN_S)
+#define DSI_BRG_DMA_MULTIBLK_EN_V  0x00000001U
+#define DSI_BRG_DMA_MULTIBLK_EN_S  28
+/** DSI_BRG_DMA_FRAME_INTERVAL_EN : R/W; bitpos: [29]; default: 1;
+ *  this bit configures enable interval between frame transfer, 0: disable, 1: enable
+ */
+#define DSI_BRG_DMA_FRAME_INTERVAL_EN    (BIT(29))
+#define DSI_BRG_DMA_FRAME_INTERVAL_EN_M  (DSI_BRG_DMA_FRAME_INTERVAL_EN_V << DSI_BRG_DMA_FRAME_INTERVAL_EN_S)
+#define DSI_BRG_DMA_FRAME_INTERVAL_EN_V  0x00000001U
+#define DSI_BRG_DMA_FRAME_INTERVAL_EN_S  29
+
+/** DSI_BRG_MEM_AUX_CTRL_REG register
+ *  dsi_bridge mem aux control register
+ */
+#define DSI_BRG_MEM_AUX_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x70)
+/** DSI_BRG_DSI_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  this field configures dsi_bridge fifo memory aux ctrl
+ */
+#define DSI_BRG_DSI_MEM_AUX_CTRL    0x00003FFFU
+#define DSI_BRG_DSI_MEM_AUX_CTRL_M  (DSI_BRG_DSI_MEM_AUX_CTRL_V << DSI_BRG_DSI_MEM_AUX_CTRL_S)
+#define DSI_BRG_DSI_MEM_AUX_CTRL_V  0x00003FFFU
+#define DSI_BRG_DSI_MEM_AUX_CTRL_S  0
+
+/** DSI_BRG_RDN_ECO_CS_REG register
+ *  dsi_bridge rdn eco cs register
+ */
+#define DSI_BRG_RDN_ECO_CS_REG (DR_REG_DSI_BRG_BASE + 0x74)
+/** DSI_BRG_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  rdn_eco_en
+ */
+#define DSI_BRG_RDN_ECO_EN    (BIT(0))
+#define DSI_BRG_RDN_ECO_EN_M  (DSI_BRG_RDN_ECO_EN_V << DSI_BRG_RDN_ECO_EN_S)
+#define DSI_BRG_RDN_ECO_EN_V  0x00000001U
+#define DSI_BRG_RDN_ECO_EN_S  0
+/** DSI_BRG_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  rdn_eco_result
+ */
+#define DSI_BRG_RDN_ECO_RESULT    (BIT(1))
+#define DSI_BRG_RDN_ECO_RESULT_M  (DSI_BRG_RDN_ECO_RESULT_V << DSI_BRG_RDN_ECO_RESULT_S)
+#define DSI_BRG_RDN_ECO_RESULT_V  0x00000001U
+#define DSI_BRG_RDN_ECO_RESULT_S  1
+
+/** DSI_BRG_RDN_ECO_LOW_REG register
+ *  dsi_bridge rdn eco all low register
+ */
+#define DSI_BRG_RDN_ECO_LOW_REG (DR_REG_DSI_BRG_BASE + 0x78)
+/** DSI_BRG_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  rdn_eco_low
+ */
+#define DSI_BRG_RDN_ECO_LOW    0xFFFFFFFFU
+#define DSI_BRG_RDN_ECO_LOW_M  (DSI_BRG_RDN_ECO_LOW_V << DSI_BRG_RDN_ECO_LOW_S)
+#define DSI_BRG_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define DSI_BRG_RDN_ECO_LOW_S  0
+
+/** DSI_BRG_RDN_ECO_HIGH_REG register
+ *  dsi_bridge rdn eco all high register
+ */
+#define DSI_BRG_RDN_ECO_HIGH_REG (DR_REG_DSI_BRG_BASE + 0x7c)
+/** DSI_BRG_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  rdn_eco_high
+ */
+#define DSI_BRG_RDN_ECO_HIGH    0xFFFFFFFFU
+#define DSI_BRG_RDN_ECO_HIGH_M  (DSI_BRG_RDN_ECO_HIGH_V << DSI_BRG_RDN_ECO_HIGH_S)
+#define DSI_BRG_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define DSI_BRG_RDN_ECO_HIGH_S  0
+
+/** DSI_BRG_HOST_CTRL_REG register
+ *  dsi_bridge host control register
+ */
+#define DSI_BRG_HOST_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x80)
+/** DSI_BRG_DSI_CFG_REF_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1:
+ *  enable
+ */
+#define DSI_BRG_DSI_CFG_REF_CLK_EN    (BIT(0))
+#define DSI_BRG_DSI_CFG_REF_CLK_EN_M  (DSI_BRG_DSI_CFG_REF_CLK_EN_V << DSI_BRG_DSI_CFG_REF_CLK_EN_S)
+#define DSI_BRG_DSI_CFG_REF_CLK_EN_V  0x00000001U
+#define DSI_BRG_DSI_CFG_REF_CLK_EN_S  0
+
+/** DSI_BRG_MEM_CLK_CTRL_REG register
+ *  dsi_bridge mem force on control register
+ */
+#define DSI_BRG_MEM_CLK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x84)
+/** DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1:
+ *  force on
+ */
+#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON    (BIT(0))
+#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_M  (DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_V << DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_S)
+#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_S  0
+/** DSI_BRG_DSI_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on
+ */
+#define DSI_BRG_DSI_MEM_CLK_FORCE_ON    (BIT(1))
+#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_M  (DSI_BRG_DSI_MEM_CLK_FORCE_ON_V << DSI_BRG_DSI_MEM_CLK_FORCE_ON_S)
+#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_V  0x00000001U
+#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_S  1
+
+/** DSI_BRG_DMA_FLOW_CTRL_REG register
+ *  dsi_bridge dma flow controller register
+ */
+#define DSI_BRG_DMA_FLOW_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x88)
+/** DSI_BRG_DSI_DMA_FLOW_CONTROLLER : R/W; bitpos: [0]; default: 1;
+ *  this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge
+ *  as flow controller
+ */
+#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER    (BIT(0))
+#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_M  (DSI_BRG_DSI_DMA_FLOW_CONTROLLER_V << DSI_BRG_DSI_DMA_FLOW_CONTROLLER_S)
+#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_V  0x00000001U
+#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_S  0
+/** DSI_BRG_DMA_FLOW_MULTIBLK_NUM : R/W; bitpos: [7:4]; default: 1;
+ *  this field configures the num of blocks when multi-blk is enable and dmac as flow
+ *  controller
+ */
+#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM    0x0000000FU
+#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_M  (DSI_BRG_DMA_FLOW_MULTIBLK_NUM_V << DSI_BRG_DMA_FLOW_MULTIBLK_NUM_S)
+#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_V  0x0000000FU
+#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_S  4
+
+/** DSI_BRG_RAW_BUF_ALMOST_EMPTY_THRD_REG register
+ *  dsi_bridge buffer empty threshold register
+ */
+#define DSI_BRG_RAW_BUF_ALMOST_EMPTY_THRD_REG (DR_REG_DSI_BRG_BASE + 0x8c)
+/** DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD : R/W; bitpos: [10:0]; default: 512;
+ *  this field configures the fifo almost empty threshold, is valid only when dmac as
+ *  flow controller
+ */
+#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD    0x000007FFU
+#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_M  (DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_V << DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_S)
+#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_V  0x000007FFU
+#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_S  0
+
+/** DSI_BRG_YUV_CFG_REG register
+ *  dsi_bridge yuv format config register
+ */
+#define DSI_BRG_YUV_CFG_REG (DR_REG_DSI_BRG_BASE + 0x90)
+/** DSI_BRG_PROTOCAL : R/W; bitpos: [0]; default: 0;
+ *  this bit configures yuv protoocl, 0: bt.601, 1: bt.709
+ */
+#define DSI_BRG_PROTOCAL    (BIT(0))
+#define DSI_BRG_PROTOCAL_M  (DSI_BRG_PROTOCAL_V << DSI_BRG_PROTOCAL_S)
+#define DSI_BRG_PROTOCAL_V  0x00000001U
+#define DSI_BRG_PROTOCAL_S  0
+/** DSI_BRG_YUV_PIX_ENDIAN : R/W; bitpos: [1]; default: 0;
+ *  this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0
+ */
+#define DSI_BRG_YUV_PIX_ENDIAN    (BIT(1))
+#define DSI_BRG_YUV_PIX_ENDIAN_M  (DSI_BRG_YUV_PIX_ENDIAN_V << DSI_BRG_YUV_PIX_ENDIAN_S)
+#define DSI_BRG_YUV_PIX_ENDIAN_V  0x00000001U
+#define DSI_BRG_YUV_PIX_ENDIAN_S  1
+/** DSI_BRG_YUV422_FORMAT : R/W; bitpos: [3:2]; default: 0;
+ *  this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
+ */
+#define DSI_BRG_YUV422_FORMAT    0x00000003U
+#define DSI_BRG_YUV422_FORMAT_M  (DSI_BRG_YUV422_FORMAT_V << DSI_BRG_YUV422_FORMAT_S)
+#define DSI_BRG_YUV422_FORMAT_V  0x00000003U
+#define DSI_BRG_YUV422_FORMAT_S  2
+/** DSI_BRG_YUV_RANGE : R/W; bitpos: [4]; default: 0;
+ *  Configures yuv pixel range, 0: limit range, 1: full range
+ */
+#define DSI_BRG_YUV_RANGE    (BIT(4))
+#define DSI_BRG_YUV_RANGE_M  (DSI_BRG_YUV_RANGE_V << DSI_BRG_YUV_RANGE_S)
+#define DSI_BRG_YUV_RANGE_V  0x00000001U
+#define DSI_BRG_YUV_RANGE_S  4
+
+/** DSI_BRG_PHY_LP_LOOPBACK_CTRL_REG register
+ *  dsi phy lp_loopback test ctrl
+ */
+#define DSI_BRG_PHY_LP_LOOPBACK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x94)
+/** DSI_BRG_PHY_LP_TXDATAESC_1 : R/W; bitpos: [7:0]; default: 0;
+ *  txdataesc_1 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXDATAESC_1    0x000000FFU
+#define DSI_BRG_PHY_LP_TXDATAESC_1_M  (DSI_BRG_PHY_LP_TXDATAESC_1_V << DSI_BRG_PHY_LP_TXDATAESC_1_S)
+#define DSI_BRG_PHY_LP_TXDATAESC_1_V  0x000000FFU
+#define DSI_BRG_PHY_LP_TXDATAESC_1_S  0
+/** DSI_BRG_PHY_LP_TXREQUESTESC_1 : R/W; bitpos: [8]; default: 0;
+ *  txrequestesc_1 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXREQUESTESC_1    (BIT(8))
+#define DSI_BRG_PHY_LP_TXREQUESTESC_1_M  (DSI_BRG_PHY_LP_TXREQUESTESC_1_V << DSI_BRG_PHY_LP_TXREQUESTESC_1_S)
+#define DSI_BRG_PHY_LP_TXREQUESTESC_1_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXREQUESTESC_1_S  8
+/** DSI_BRG_PHY_LP_TXVALIDESC_1 : R/W; bitpos: [9]; default: 0;
+ *  txvalidesc_1 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXVALIDESC_1    (BIT(9))
+#define DSI_BRG_PHY_LP_TXVALIDESC_1_M  (DSI_BRG_PHY_LP_TXVALIDESC_1_V << DSI_BRG_PHY_LP_TXVALIDESC_1_S)
+#define DSI_BRG_PHY_LP_TXVALIDESC_1_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXVALIDESC_1_S  9
+/** DSI_BRG_PHY_LP_TXLPDTESC_1 : R/W; bitpos: [10]; default: 0;
+ *  txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXLPDTESC_1    (BIT(10))
+#define DSI_BRG_PHY_LP_TXLPDTESC_1_M  (DSI_BRG_PHY_LP_TXLPDTESC_1_V << DSI_BRG_PHY_LP_TXLPDTESC_1_S)
+#define DSI_BRG_PHY_LP_TXLPDTESC_1_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXLPDTESC_1_S  10
+/** DSI_BRG_PHY_LP_BASEDIR_1 : R/W; bitpos: [11]; default: 0;
+ *  basedir_1 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_BASEDIR_1    (BIT(11))
+#define DSI_BRG_PHY_LP_BASEDIR_1_M  (DSI_BRG_PHY_LP_BASEDIR_1_V << DSI_BRG_PHY_LP_BASEDIR_1_S)
+#define DSI_BRG_PHY_LP_BASEDIR_1_V  0x00000001U
+#define DSI_BRG_PHY_LP_BASEDIR_1_S  11
+/** DSI_BRG_PHY_LP_TXDATAESC_0 : R/W; bitpos: [23:16]; default: 0;
+ *  txdataesc_0 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXDATAESC_0    0x000000FFU
+#define DSI_BRG_PHY_LP_TXDATAESC_0_M  (DSI_BRG_PHY_LP_TXDATAESC_0_V << DSI_BRG_PHY_LP_TXDATAESC_0_S)
+#define DSI_BRG_PHY_LP_TXDATAESC_0_V  0x000000FFU
+#define DSI_BRG_PHY_LP_TXDATAESC_0_S  16
+/** DSI_BRG_PHY_LP_TXREQUESTESC_0 : R/W; bitpos: [24]; default: 0;
+ *  txrequestesc_0 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXREQUESTESC_0    (BIT(24))
+#define DSI_BRG_PHY_LP_TXREQUESTESC_0_M  (DSI_BRG_PHY_LP_TXREQUESTESC_0_V << DSI_BRG_PHY_LP_TXREQUESTESC_0_S)
+#define DSI_BRG_PHY_LP_TXREQUESTESC_0_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXREQUESTESC_0_S  24
+/** DSI_BRG_PHY_LP_TXVALIDESC_0 : R/W; bitpos: [25]; default: 0;
+ *  txvalidesc_0 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXVALIDESC_0    (BIT(25))
+#define DSI_BRG_PHY_LP_TXVALIDESC_0_M  (DSI_BRG_PHY_LP_TXVALIDESC_0_V << DSI_BRG_PHY_LP_TXVALIDESC_0_S)
+#define DSI_BRG_PHY_LP_TXVALIDESC_0_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXVALIDESC_0_S  25
+/** DSI_BRG_PHY_LP_TXLPDTESC_0 : R/W; bitpos: [26]; default: 0;
+ *  txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXLPDTESC_0    (BIT(26))
+#define DSI_BRG_PHY_LP_TXLPDTESC_0_M  (DSI_BRG_PHY_LP_TXLPDTESC_0_V << DSI_BRG_PHY_LP_TXLPDTESC_0_S)
+#define DSI_BRG_PHY_LP_TXLPDTESC_0_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXLPDTESC_0_S  26
+/** DSI_BRG_PHY_LP_BASEDIR_0 : R/W; bitpos: [27]; default: 0;
+ *  basedir_0 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_BASEDIR_0    (BIT(27))
+#define DSI_BRG_PHY_LP_BASEDIR_0_M  (DSI_BRG_PHY_LP_BASEDIR_0_V << DSI_BRG_PHY_LP_BASEDIR_0_S)
+#define DSI_BRG_PHY_LP_BASEDIR_0_V  0x00000001U
+#define DSI_BRG_PHY_LP_BASEDIR_0_S  27
+/** DSI_BRG_PHY_LP_LOOPBACK_CHECK : WT; bitpos: [28]; default: 0;
+ *  dsi phy lp_loopback test start check
+ */
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK    (BIT(28))
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_M  (DSI_BRG_PHY_LP_LOOPBACK_CHECK_V << DSI_BRG_PHY_LP_LOOPBACK_CHECK_S)
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_V  0x00000001U
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_S  28
+/** DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE : RO; bitpos: [29]; default: 0;
+ *  dsi phy lp_loopback test check done
+ */
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE    (BIT(29))
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_M  (DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_V << DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_S)
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_V  0x00000001U
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_S  29
+/** DSI_BRG_PHY_LP_LOOPBACK_EN : R/W; bitpos: [30]; default: 0;
+ *  dsi phy lp_loopback ctrl en
+ */
+#define DSI_BRG_PHY_LP_LOOPBACK_EN    (BIT(30))
+#define DSI_BRG_PHY_LP_LOOPBACK_EN_M  (DSI_BRG_PHY_LP_LOOPBACK_EN_V << DSI_BRG_PHY_LP_LOOPBACK_EN_S)
+#define DSI_BRG_PHY_LP_LOOPBACK_EN_V  0x00000001U
+#define DSI_BRG_PHY_LP_LOOPBACK_EN_S  30
+/** DSI_BRG_PHY_LP_LOOPBACK_OK : RO; bitpos: [31]; default: 0;
+ *  result of dsi phy lp_loopback test
+ */
+#define DSI_BRG_PHY_LP_LOOPBACK_OK    (BIT(31))
+#define DSI_BRG_PHY_LP_LOOPBACK_OK_M  (DSI_BRG_PHY_LP_LOOPBACK_OK_V << DSI_BRG_PHY_LP_LOOPBACK_OK_S)
+#define DSI_BRG_PHY_LP_LOOPBACK_OK_V  0x00000001U
+#define DSI_BRG_PHY_LP_LOOPBACK_OK_S  31
+
+/** DSI_BRG_PHY_HS_LOOPBACK_CTRL_REG register
+ *  dsi phy hp_loopback test ctrl
+ */
+#define DSI_BRG_PHY_HS_LOOPBACK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x98)
+/** DSI_BRG_PHY_HS_TXDATAHS_1 : R/W; bitpos: [7:0]; default: 0;
+ *  txdatahs_1 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_TXDATAHS_1    0x000000FFU
+#define DSI_BRG_PHY_HS_TXDATAHS_1_M  (DSI_BRG_PHY_HS_TXDATAHS_1_V << DSI_BRG_PHY_HS_TXDATAHS_1_S)
+#define DSI_BRG_PHY_HS_TXDATAHS_1_V  0x000000FFU
+#define DSI_BRG_PHY_HS_TXDATAHS_1_S  0
+/** DSI_BRG_PHY_HS_TXREQUESTDATAHS_1 : R/W; bitpos: [8]; default: 0;
+ *  txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1    (BIT(8))
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_M  (DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_V << DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_S)
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_V  0x00000001U
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_S  8
+/** DSI_BRG_PHY_HS_BASEDIR_1 : R/W; bitpos: [9]; default: 1;
+ *  basedir_1 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_BASEDIR_1    (BIT(9))
+#define DSI_BRG_PHY_HS_BASEDIR_1_M  (DSI_BRG_PHY_HS_BASEDIR_1_V << DSI_BRG_PHY_HS_BASEDIR_1_S)
+#define DSI_BRG_PHY_HS_BASEDIR_1_V  0x00000001U
+#define DSI_BRG_PHY_HS_BASEDIR_1_S  9
+/** DSI_BRG_PHY_HS_TXDATAHS_0 : R/W; bitpos: [23:16]; default: 0;
+ *  txdatahs_0 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_TXDATAHS_0    0x000000FFU
+#define DSI_BRG_PHY_HS_TXDATAHS_0_M  (DSI_BRG_PHY_HS_TXDATAHS_0_V << DSI_BRG_PHY_HS_TXDATAHS_0_S)
+#define DSI_BRG_PHY_HS_TXDATAHS_0_V  0x000000FFU
+#define DSI_BRG_PHY_HS_TXDATAHS_0_S  16
+/** DSI_BRG_PHY_HS_TXREQUESTDATAHS_0 : R/W; bitpos: [24]; default: 0;
+ *  txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0    (BIT(24))
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_M  (DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_V << DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_S)
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_V  0x00000001U
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_S  24
+/** DSI_BRG_PHY_HS_BASEDIR_0 : R/W; bitpos: [25]; default: 0;
+ *  basedir_0 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_BASEDIR_0    (BIT(25))
+#define DSI_BRG_PHY_HS_BASEDIR_0_M  (DSI_BRG_PHY_HS_BASEDIR_0_V << DSI_BRG_PHY_HS_BASEDIR_0_S)
+#define DSI_BRG_PHY_HS_BASEDIR_0_V  0x00000001U
+#define DSI_BRG_PHY_HS_BASEDIR_0_S  25
+/** DSI_BRG_PHY_HS_TXREQUESTHSCLK : R/W; bitpos: [27]; default: 0;
+ *  txrequesthsclk when  enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_TXREQUESTHSCLK    (BIT(27))
+#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_M  (DSI_BRG_PHY_HS_TXREQUESTHSCLK_V << DSI_BRG_PHY_HS_TXREQUESTHSCLK_S)
+#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_V  0x00000001U
+#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_S  27
+/** DSI_BRG_PHY_HS_LOOPBACK_CHECK : WT; bitpos: [28]; default: 0;
+ *  dsi phy hs_loopback test start check
+ */
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK    (BIT(28))
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_M  (DSI_BRG_PHY_HS_LOOPBACK_CHECK_V << DSI_BRG_PHY_HS_LOOPBACK_CHECK_S)
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_V  0x00000001U
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_S  28
+/** DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE : RO; bitpos: [29]; default: 0;
+ *  dsi phy hs_loopback test check done
+ */
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE    (BIT(29))
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_M  (DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_V << DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_S)
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_V  0x00000001U
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_S  29
+/** DSI_BRG_PHY_HS_LOOPBACK_EN : R/W; bitpos: [30]; default: 0;
+ *  dsi phy hs_loopback ctrl en
+ */
+#define DSI_BRG_PHY_HS_LOOPBACK_EN    (BIT(30))
+#define DSI_BRG_PHY_HS_LOOPBACK_EN_M  (DSI_BRG_PHY_HS_LOOPBACK_EN_V << DSI_BRG_PHY_HS_LOOPBACK_EN_S)
+#define DSI_BRG_PHY_HS_LOOPBACK_EN_V  0x00000001U
+#define DSI_BRG_PHY_HS_LOOPBACK_EN_S  30
+/** DSI_BRG_PHY_HS_LOOPBACK_OK : RO; bitpos: [31]; default: 0;
+ *  result of dsi phy hs_loopback test
+ */
+#define DSI_BRG_PHY_HS_LOOPBACK_OK    (BIT(31))
+#define DSI_BRG_PHY_HS_LOOPBACK_OK_M  (DSI_BRG_PHY_HS_LOOPBACK_OK_V << DSI_BRG_PHY_HS_LOOPBACK_OK_S)
+#define DSI_BRG_PHY_HS_LOOPBACK_OK_V  0x00000001U
+#define DSI_BRG_PHY_HS_LOOPBACK_OK_S  31
+
+/** DSI_BRG_PHY_LOOPBACK_CNT_REG register
+ *  loopback test cnt
+ */
+#define DSI_BRG_PHY_LOOPBACK_CNT_REG (DR_REG_DSI_BRG_BASE + 0x9c)
+/** DSI_BRG_PHY_HS_CHECK_CNT_TH : R/W; bitpos: [7:0]; default: 64;
+ *  hs_loopback test check cnt
+ */
+#define DSI_BRG_PHY_HS_CHECK_CNT_TH    0x000000FFU
+#define DSI_BRG_PHY_HS_CHECK_CNT_TH_M  (DSI_BRG_PHY_HS_CHECK_CNT_TH_V << DSI_BRG_PHY_HS_CHECK_CNT_TH_S)
+#define DSI_BRG_PHY_HS_CHECK_CNT_TH_V  0x000000FFU
+#define DSI_BRG_PHY_HS_CHECK_CNT_TH_S  0
+/** DSI_BRG_PHY_LP_CHECK_CNT_TH : R/W; bitpos: [23:16]; default: 64;
+ *  lp_loopback test check cnt
+ */
+#define DSI_BRG_PHY_LP_CHECK_CNT_TH    0x000000FFU
+#define DSI_BRG_PHY_LP_CHECK_CNT_TH_M  (DSI_BRG_PHY_LP_CHECK_CNT_TH_V << DSI_BRG_PHY_LP_CHECK_CNT_TH_S)
+#define DSI_BRG_PHY_LP_CHECK_CNT_TH_V  0x000000FFU
+#define DSI_BRG_PHY_LP_CHECK_CNT_TH_S  16
+
+/** DSI_BRG_VER_DATE_REG register
+ *  version control register
+ */
+#define DSI_BRG_VER_DATE_REG (DR_REG_DSI_BRG_BASE + 0x100)
+/** DSI_BRG_VER_DATA : R/W; bitpos: [31:0]; default: 539296009;
+ *  Represents csv version
+ */
+#define DSI_BRG_VER_DATA    0xFFFFFFFFU
+#define DSI_BRG_VER_DATA_M  (DSI_BRG_VER_DATA_V << DSI_BRG_VER_DATA_S)
+#define DSI_BRG_VER_DATA_V  0xFFFFFFFFU
+#define DSI_BRG_VER_DATA_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_struct.h
new file mode 100644
index 0000000000..3da6f91b24
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_struct.h
@@ -0,0 +1,818 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of clk_en register
+ *  dsi bridge clk control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures force_on of dsi_bridge register clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_clk_en_reg_t;
+
+/** Type of en register
+ *  dsi bridge en register
+ */
+typedef union {
+    struct {
+        /** dsi_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures module enable of dsi_bridge. 0: disable, 1: enable
+         */
+        uint32_t dsi_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_en_reg_t;
+
+/** Type of dma_req_cfg register
+ *  dsi bridge dma burst len register
+ */
+typedef union {
+    struct {
+        /** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures the num of 64-bit in one dma burst transfer, valid only when
+         *  dsi_bridge as flow controller
+         */
+        uint32_t dma_burst_len:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_brg_dma_req_cfg_reg_t;
+
+/** Type of raw_num_cfg register
+ *  dsi bridge raw number control register
+ */
+typedef union {
+    struct {
+        /** raw_num_total : R/W; bitpos: [21:0]; default: 230400;
+         *  this field configures number of total pix bits/64
+         */
+        uint32_t raw_num_total:22;
+        /** unalign_64bit_en : R/W; bitpos: [22]; default: 0;
+         *  this field configures whether the total pix bits is a multiple of 64bits. 0: align
+         *  to 64-bit, 1: unalign to 64-bit
+         */
+        uint32_t unalign_64bit_en:1;
+        uint32_t reserved_23:8;
+        /** raw_num_total_set : WT; bitpos: [31]; default: 0;
+         *  this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable,
+         *  1: enable. valid only when dsi_bridge as flow controller
+         */
+        uint32_t raw_num_total_set:1;
+    };
+    uint32_t val;
+} dsi_brg_raw_num_cfg_reg_t;
+
+/** Type of raw_buf_credit_ctl register
+ *  dsi bridge credit register
+ */
+typedef union {
+    struct {
+        /** credit_thrd : R/W; bitpos: [14:0]; default: 1024;
+         *  this field configures the threshold whether dsi_bridge fifo can receive one more
+         *  64-bit, valid only when dsi_bridge as flow controller
+         */
+        uint32_t credit_thrd:15;
+        uint32_t reserved_15:1;
+        /** credit_burst_thrd : R/W; bitpos: [30:16]; default: 800;
+         *  this field configures the threshold whether dsi_bridge fifo can receive one more
+         *  dma burst, valid only when dsi_bridge as flow controller
+         */
+        uint32_t credit_burst_thrd:15;
+        /** credit_reset : R/W; bitpos: [31]; default: 0;
+         *  this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when
+         *  dsi_bridge as flow controller
+         */
+        uint32_t credit_reset:1;
+    };
+    uint32_t val;
+} dsi_brg_raw_buf_credit_ctl_reg_t;
+
+/** Type of pixel_type register
+ *  dsi bridge dpi type control register
+ */
+typedef union {
+    struct {
+        /** raw_type : R/W; bitpos: [3:0]; default: 0;
+         *  this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565
+         */
+        uint32_t raw_type:4;
+        /** dpi_config : R/W; bitpos: [5:4]; default: 0;
+         *  this field configures the pixel arrange type of dpi interface
+         */
+        uint32_t dpi_config:2;
+        /** data_in_type : R/W; bitpos: [6]; default: 0;
+         *  input data type, 0: rgb, 1: yuv
+         */
+        uint32_t data_in_type:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dsi_brg_pixel_type_reg_t;
+
+/** Type of dma_block_interval register
+ *  dsi bridge dma block interval control register
+ */
+typedef union {
+    struct {
+        /** dma_block_slot : R/W; bitpos: [9:0]; default: 9;
+         *  this field configures the max block_slot_cnt
+         */
+        uint32_t dma_block_slot:10;
+        /** dma_block_interval : R/W; bitpos: [27:10]; default: 9;
+         *  this field configures the max block_interval_cnt, block_interval_cnt increased by 1
+         *  when block_slot_cnt if full
+         */
+        uint32_t dma_block_interval:18;
+        /** raw_num_total_auto_reload : R/W; bitpos: [28]; default: 1;
+         *  this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable
+         */
+        uint32_t raw_num_total_auto_reload:1;
+        /** dma_block_interval_en : R/W; bitpos: [29]; default: 1;
+         *  this bit configures enable of interval between dma block transfer, 0: disable, 1:
+         *  enable
+         */
+        uint32_t dma_block_interval_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} dsi_brg_dma_block_interval_reg_t;
+
+/** Type of dma_req_interval register
+ *  dsi bridge dma req interval control register
+ */
+typedef union {
+    struct {
+        /** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
+         *  this field configures the interval between dma req events
+         */
+        uint32_t dma_req_interval:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_brg_dma_req_interval_reg_t;
+
+/** Type of dpi_lcd_ctl register
+ *  dsi bridge dpi signal control register
+ */
+typedef union {
+    struct {
+        /** dpishutdn : R/W; bitpos: [0]; default: 0;
+         *  this bit configures dpishutdn signal in dpi interface
+         */
+        uint32_t dpishutdn:1;
+        /** dpicolorm : R/W; bitpos: [1]; default: 0;
+         *  this bit configures dpicolorm signal in dpi interface
+         */
+        uint32_t dpicolorm:1;
+        /** dpiupdatecfg : R/W; bitpos: [2]; default: 0;
+         *  this bit configures dpiupdatecfg signal in dpi interface
+         */
+        uint32_t dpiupdatecfg:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dsi_brg_dpi_lcd_ctl_reg_t;
+
+/** Type of dpi_rsv_dpi_data register
+ *  dsi bridge dpi reserved data register
+ */
+typedef union {
+    struct {
+        /** dpi_rsv_data : R/W; bitpos: [29:0]; default: 16383;
+         *  this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
+         */
+        uint32_t dpi_rsv_data:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} dsi_brg_dpi_rsv_dpi_data_reg_t;
+
+/** Type of dpi_v_cfg0 register
+ *  dsi bridge dpi v config register 0
+ */
+typedef union {
+    struct {
+        /** vtotal : R/W; bitpos: [11:0]; default: 525;
+         *  this field configures the total length of one frame (by line) for dpi output, must
+         *  meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank
+         */
+        uint32_t vtotal:12;
+        uint32_t reserved_12:4;
+        /** vdisp : R/W; bitpos: [27:16]; default: 480;
+         *  this field configures the length of valid line (by line) for dpi output
+         */
+        uint32_t vdisp:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_v_cfg0_reg_t;
+
+/** Type of dpi_v_cfg1 register
+ *  dsi bridge dpi v config register 1
+ */
+typedef union {
+    struct {
+        /** vbank : R/W; bitpos: [11:0]; default: 33;
+         *  this field configures the length between vsync and valid line (by line) for dpi
+         *  output
+         */
+        uint32_t vbank:12;
+        uint32_t reserved_12:4;
+        /** vsync : R/W; bitpos: [27:16]; default: 2;
+         *  this field configures the length of vsync (by line) for dpi output
+         */
+        uint32_t vsync:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_v_cfg1_reg_t;
+
+/** Type of dpi_h_cfg0 register
+ *  dsi bridge dpi h config register 0
+ */
+typedef union {
+    struct {
+        /** htotal : R/W; bitpos: [11:0]; default: 800;
+         *  this field configures the total length of one line (by pixel num) for dpi output,
+         *  must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank
+         */
+        uint32_t htotal:12;
+        uint32_t reserved_12:4;
+        /** hdisp : R/W; bitpos: [27:16]; default: 640;
+         *  this field configures the length of valid pixel data (by pixel num) for dpi output
+         */
+        uint32_t hdisp:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_h_cfg0_reg_t;
+
+/** Type of dpi_h_cfg1 register
+ *  dsi bridge dpi h config register 1
+ */
+typedef union {
+    struct {
+        /** hbank : R/W; bitpos: [11:0]; default: 48;
+         *  this field configures the length between hsync and pixel data valid (by pixel num)
+         *  for dpi output
+         */
+        uint32_t hbank:12;
+        uint32_t reserved_12:4;
+        /** hsync : R/W; bitpos: [27:16]; default: 96;
+         *  this field configures the length of hsync (by pixel num) for dpi output
+         */
+        uint32_t hsync:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_h_cfg1_reg_t;
+
+/** Type of dpi_misc_config register
+ *  dsi_bridge dpi misc config register
+ */
+typedef union {
+    struct {
+        /** dpi_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures enable of dpi output, 0: disable, 1: enable
+         */
+        uint32_t dpi_en:1;
+        uint32_t reserved_1:3;
+        /** fifo_underrun_discard_vcnt : R/W; bitpos: [15:4]; default: 413;
+         *  this field configures the underrun interrupt musk, when underrun occurs and line
+         *  cnt is less then this field
+         */
+        uint32_t fifo_underrun_discard_vcnt:12;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_brg_dpi_misc_config_reg_t;
+
+/** Type of dpi_config_update register
+ *  dsi_bridge dpi config update register
+ */
+typedef union {
+    struct {
+        /** dpi_config_update : WT; bitpos: [0]; default: 0;
+         *  write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*
+         */
+        uint32_t dpi_config_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_dpi_config_update_reg_t;
+
+/** Type of host_trigger_rev register
+ *  dsi_bridge host trigger reverse control register
+ */
+typedef union {
+    struct {
+        /** tx_trigger_rev_en : R/W; bitpos: [0]; default: 0;
+         *  tx_trigger reverse. 0: disable, 1: enable
+         */
+        uint32_t tx_trigger_rev_en:1;
+        /** rx_trigger_rev_en : R/W; bitpos: [1]; default: 0;
+         *  rx_trigger reverse. 0: disable, 1: enable
+         */
+        uint32_t rx_trigger_rev_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_host_trigger_rev_reg_t;
+
+/** Type of blk_raw_num_cfg register
+ *  dsi_bridge block raw number control register
+ */
+typedef union {
+    struct {
+        /** blk_raw_num_total : R/W; bitpos: [21:0]; default: 230400;
+         *  this field configures number of total block pix bits/64
+         */
+        uint32_t blk_raw_num_total:22;
+        uint32_t reserved_22:9;
+        /** blk_raw_num_total_set : WT; bitpos: [31]; default: 0;
+         *  write 1 to reload reg_blk_raw_num_total to internal cnt
+         */
+        uint32_t blk_raw_num_total_set:1;
+    };
+    uint32_t val;
+} dsi_brg_blk_raw_num_cfg_reg_t;
+
+/** Type of dma_frame_interval register
+ *  dsi_bridge dam frame interval control register
+ */
+typedef union {
+    struct {
+        /** dma_frame_slot : R/W; bitpos: [9:0]; default: 9;
+         *  this field configures the max frame_slot_cnt
+         */
+        uint32_t dma_frame_slot:10;
+        /** dma_frame_interval : R/W; bitpos: [27:10]; default: 9;
+         *  this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1
+         *  when frame_slot_cnt if full
+         */
+        uint32_t dma_frame_interval:18;
+        /** dma_multiblk_en : R/W; bitpos: [28]; default: 0;
+         *  this bit configures enable multi-blk transfer, 0: disable, 1: enable
+         */
+        uint32_t dma_multiblk_en:1;
+        /** dma_frame_interval_en : R/W; bitpos: [29]; default: 1;
+         *  this bit configures enable interval between frame transfer, 0: disable, 1: enable
+         */
+        uint32_t dma_frame_interval_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} dsi_brg_dma_frame_interval_reg_t;
+
+/** Type of mem_aux_ctrl register
+ *  dsi_bridge mem aux control register
+ */
+typedef union {
+    struct {
+        /** dsi_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures dsi_bridge fifo memory aux ctrl
+         */
+        uint32_t dsi_mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_brg_mem_aux_ctrl_reg_t;
+
+/** Type of rdn_eco_low register
+ *  dsi_bridge rdn eco all low register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rdn_eco_low
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_low_reg_t;
+
+/** Type of rdn_eco_high register
+ *  dsi_bridge rdn eco all high register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rdn_eco_high
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_high_reg_t;
+
+/** Type of host_ctrl register
+ *  dsi_bridge host control register
+ */
+typedef union {
+    struct {
+        /** dsi_cfg_ref_clk_en : R/W; bitpos: [0]; default: 1;
+         *  this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1:
+         *  enable
+         */
+        uint32_t dsi_cfg_ref_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_host_ctrl_reg_t;
+
+/** Type of mem_clk_ctrl register
+ *  dsi_bridge mem force on control register
+ */
+typedef union {
+    struct {
+        /** dsi_bridge_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1:
+         *  force on
+         */
+        uint32_t dsi_bridge_mem_clk_force_on:1;
+        /** dsi_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on
+         */
+        uint32_t dsi_mem_clk_force_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_mem_clk_ctrl_reg_t;
+
+/** Type of dma_flow_ctrl register
+ *  dsi_bridge dma flow controller register
+ */
+typedef union {
+    struct {
+        /** dsi_dma_flow_controller : R/W; bitpos: [0]; default: 1;
+         *  this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge
+         *  as flow controller
+         */
+        uint32_t dsi_dma_flow_controller:1;
+        uint32_t reserved_1:3;
+        /** dma_flow_multiblk_num : R/W; bitpos: [7:4]; default: 1;
+         *  this field configures the num of blocks when multi-blk is enable and dmac as flow
+         *  controller
+         */
+        uint32_t dma_flow_multiblk_num:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dsi_brg_dma_flow_ctrl_reg_t;
+
+/** Type of raw_buf_almost_empty_thrd register
+ *  dsi_bridge buffer empty threshold register
+ */
+typedef union {
+    struct {
+        /** dsi_raw_buf_almost_empty_thrd : R/W; bitpos: [10:0]; default: 512;
+         *  this field configures the fifo almost empty threshold, is valid only when dmac as
+         *  flow controller
+         */
+        uint32_t dsi_raw_buf_almost_empty_thrd:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dsi_brg_raw_buf_almost_empty_thrd_reg_t;
+
+/** Type of yuv_cfg register
+ *  dsi_bridge yuv format config register
+ */
+typedef union {
+    struct {
+        /** protocol : R/W; bitpos: [0]; default: 0;
+         *  this bit configures yuv protocol, 0: bt.601, 1: bt.709
+         */
+        uint32_t protocol:1;
+        /** yuv_pix_endian : R/W; bitpos: [1]; default: 0;
+         *  this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0
+         */
+        uint32_t yuv_pix_endian:1;
+        /** yuv422_format : R/W; bitpos: [3:2]; default: 0;
+         *  this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
+         */
+        uint32_t yuv422_format:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dsi_brg_yuv_cfg_reg_t;
+
+/** Type of phy_lp_loopback_ctrl register
+ *  dsi phy lp_loopback test ctrl
+ */
+typedef union {
+    struct {
+        /** phy_lp_txdataesc_1 : R/W; bitpos: [7:0]; default: 0;
+         *  txdataesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txdataesc_1:8;
+        /** phy_lp_txrequestesc_1 : R/W; bitpos: [8]; default: 0;
+         *  txrequestesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txrequestesc_1:1;
+        /** phy_lp_txvalidesc_1 : R/W; bitpos: [9]; default: 0;
+         *  txvalidesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txvalidesc_1:1;
+        /** phy_lp_txlpdtesc_1 : R/W; bitpos: [10]; default: 0;
+         *  txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txlpdtesc_1:1;
+        /** phy_lp_basedir_1 : R/W; bitpos: [11]; default: 0;
+         *  basedir_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_basedir_1:1;
+        uint32_t reserved_12:4;
+        /** phy_lp_txdataesc_0 : R/W; bitpos: [23:16]; default: 0;
+         *  txdataesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txdataesc_0:8;
+        /** phy_lp_txrequestesc_0 : R/W; bitpos: [24]; default: 0;
+         *  txrequestesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txrequestesc_0:1;
+        /** phy_lp_txvalidesc_0 : R/W; bitpos: [25]; default: 0;
+         *  txvalidesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txvalidesc_0:1;
+        /** phy_lp_txlpdtesc_0 : R/W; bitpos: [26]; default: 0;
+         *  txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txlpdtesc_0:1;
+        /** phy_lp_basedir_0 : R/W; bitpos: [27]; default: 0;
+         *  basedir_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_basedir_0:1;
+        /** phy_lp_loopback_check : WT; bitpos: [28]; default: 0;
+         *  dsi phy lp_loopback test start check
+         */
+        uint32_t phy_lp_loopback_check:1;
+        /** phy_lp_loopback_check_done : RO; bitpos: [29]; default: 0;
+         *  dsi phy lp_loopback test check done
+         */
+        uint32_t phy_lp_loopback_check_done:1;
+        /** phy_lp_loopback_en : R/W; bitpos: [30]; default: 0;
+         *  dsi phy lp_loopback ctrl en
+         */
+        uint32_t phy_lp_loopback_en:1;
+        /** phy_lp_loopback_ok : RO; bitpos: [31]; default: 0;
+         *  result of dsi phy lp_loopback test
+         */
+        uint32_t phy_lp_loopback_ok:1;
+    };
+    uint32_t val;
+} dsi_brg_phy_lp_loopback_ctrl_reg_t;
+
+/** Type of phy_hs_loopback_ctrl register
+ *  dsi phy hp_loopback test ctrl
+ */
+typedef union {
+    struct {
+        /** phy_hs_txdatahs_1 : R/W; bitpos: [7:0]; default: 0;
+         *  txdatahs_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txdatahs_1:8;
+        /** phy_hs_txrequestdatahs_1 : R/W; bitpos: [8]; default: 0;
+         *  txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequestdatahs_1:1;
+        /** phy_hs_basedir_1 : R/W; bitpos: [9]; default: 1;
+         *  basedir_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_basedir_1:1;
+        uint32_t reserved_10:6;
+        /** phy_hs_txdatahs_0 : R/W; bitpos: [23:16]; default: 0;
+         *  txdatahs_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txdatahs_0:8;
+        /** phy_hs_txrequestdatahs_0 : R/W; bitpos: [24]; default: 0;
+         *  txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequestdatahs_0:1;
+        /** phy_hs_basedir_0 : R/W; bitpos: [25]; default: 0;
+         *  basedir_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_basedir_0:1;
+        uint32_t reserved_26:1;
+        /** phy_hs_txrequesthsclk : R/W; bitpos: [27]; default: 0;
+         *  txrequesthsclk when  enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequesthsclk:1;
+        /** phy_hs_loopback_check : WT; bitpos: [28]; default: 0;
+         *  dsi phy hs_loopback test start check
+         */
+        uint32_t phy_hs_loopback_check:1;
+        /** phy_hs_loopback_check_done : RO; bitpos: [29]; default: 0;
+         *  dsi phy hs_loopback test check done
+         */
+        uint32_t phy_hs_loopback_check_done:1;
+        /** phy_hs_loopback_en : R/W; bitpos: [30]; default: 0;
+         *  dsi phy hs_loopback ctrl en
+         */
+        uint32_t phy_hs_loopback_en:1;
+        /** phy_hs_loopback_ok : RO; bitpos: [31]; default: 0;
+         *  result of dsi phy hs_loopback test
+         */
+        uint32_t phy_hs_loopback_ok:1;
+    };
+    uint32_t val;
+} dsi_brg_phy_hs_loopback_ctrl_reg_t;
+
+/** Type of phy_loopback_cnt register
+ *  loopback test cnt
+ */
+typedef union {
+    struct {
+        /** phy_hs_check_cnt_th : R/W; bitpos: [7:0]; default: 64;
+         *  hs_loopback test check cnt
+         */
+        uint32_t phy_hs_check_cnt_th:8;
+        uint32_t reserved_8:8;
+        /** phy_lp_check_cnt_th : R/W; bitpos: [23:16]; default: 64;
+         *  lp_loopback test check cnt
+         */
+        uint32_t phy_lp_check_cnt_th:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dsi_brg_phy_loopback_cnt_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of fifo_flow_status register
+ *  dsi bridge raw buffer depth register
+ */
+typedef union {
+    struct {
+        /** raw_buf_depth : RO; bitpos: [13:0]; default: 0;
+         *  this field configures the depth of dsi_bridge fifo depth
+         */
+        uint32_t raw_buf_depth:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_brg_fifo_flow_status_reg_t;
+
+/** Type of host_bist_ctl register
+ *  dsi_bridge host bist control register
+ */
+typedef union {
+    struct {
+        /** bistok : RO; bitpos: [0]; default: 0;
+         *  bistok
+         */
+        uint32_t bistok:1;
+        /** biston : R/W; bitpos: [1]; default: 0;
+         *  biston
+         */
+        uint32_t biston:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_host_bist_ctl_reg_t;
+
+/** Type of rdn_eco_cs register
+ *  dsi_bridge rdn eco cs register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  rdn_eco_en
+         */
+        uint32_t rdn_eco_en:1;
+        /** rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  rdn_eco_result
+         */
+        uint32_t rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_cs_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_ena register
+ *  dsi_bridge interrupt enable register
+ */
+typedef union {
+    struct {
+        /** underrun_int_ena : R/W; bitpos: [0]; default: 0;
+         *  write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled
+         *  by dpi_underrun  interrupt signal
+         */
+        uint32_t underrun_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  dsi_bridge interrupt clear register
+ */
+typedef union {
+    struct {
+        /** underrun_int_clr : WT; bitpos: [0]; default: 0;
+         *  write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+         */
+        uint32_t underrun_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_int_clr_reg_t;
+
+/** Type of int_raw register
+ *  dsi_bridge raw interrupt register
+ */
+typedef union {
+    struct {
+        /** underrun_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  the raw interrupt status of dpi_underrun
+         */
+        uint32_t underrun_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_int_raw_reg_t;
+
+/** Type of int_st register
+ *  dsi_bridge masked interrupt register
+ */
+typedef union {
+    struct {
+        /** underrun_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of dpi_underrun
+         */
+        uint32_t underrun_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_int_st_reg_t;
+
+
+typedef struct dsi_brg_dev_t {
+    volatile dsi_brg_clk_en_reg_t clk_en;
+    volatile dsi_brg_en_reg_t en;
+    volatile dsi_brg_dma_req_cfg_reg_t dma_req_cfg;
+    volatile dsi_brg_raw_num_cfg_reg_t raw_num_cfg;
+    volatile dsi_brg_raw_buf_credit_ctl_reg_t raw_buf_credit_ctl;
+    volatile dsi_brg_fifo_flow_status_reg_t fifo_flow_status;
+    volatile dsi_brg_pixel_type_reg_t pixel_type;
+    volatile dsi_brg_dma_block_interval_reg_t dma_block_interval;
+    volatile dsi_brg_dma_req_interval_reg_t dma_req_interval;
+    volatile dsi_brg_dpi_lcd_ctl_reg_t dpi_lcd_ctl;
+    volatile dsi_brg_dpi_rsv_dpi_data_reg_t dpi_rsv_dpi_data;
+    uint32_t reserved_02c;
+    volatile dsi_brg_dpi_v_cfg0_reg_t dpi_v_cfg0;
+    volatile dsi_brg_dpi_v_cfg1_reg_t dpi_v_cfg1;
+    volatile dsi_brg_dpi_h_cfg0_reg_t dpi_h_cfg0;
+    volatile dsi_brg_dpi_h_cfg1_reg_t dpi_h_cfg1;
+    volatile dsi_brg_dpi_misc_config_reg_t dpi_misc_config;
+    volatile dsi_brg_dpi_config_update_reg_t dpi_config_update;
+    uint32_t reserved_048[2];
+    volatile dsi_brg_int_ena_reg_t int_ena;
+    volatile dsi_brg_int_clr_reg_t int_clr;
+    volatile dsi_brg_int_raw_reg_t int_raw;
+    volatile dsi_brg_int_st_reg_t int_st;
+    volatile dsi_brg_host_bist_ctl_reg_t host_bist_ctl;
+    volatile dsi_brg_host_trigger_rev_reg_t host_trigger_rev;
+    volatile dsi_brg_blk_raw_num_cfg_reg_t blk_raw_num_cfg;
+    volatile dsi_brg_dma_frame_interval_reg_t dma_frame_interval;
+    volatile dsi_brg_mem_aux_ctrl_reg_t mem_aux_ctrl;
+    volatile dsi_brg_rdn_eco_cs_reg_t rdn_eco_cs;
+    volatile dsi_brg_rdn_eco_low_reg_t rdn_eco_low;
+    volatile dsi_brg_rdn_eco_high_reg_t rdn_eco_high;
+    volatile dsi_brg_host_ctrl_reg_t host_ctrl;
+    volatile dsi_brg_mem_clk_ctrl_reg_t mem_clk_ctrl;
+    volatile dsi_brg_dma_flow_ctrl_reg_t dma_flow_ctrl;
+    volatile dsi_brg_raw_buf_almost_empty_thrd_reg_t raw_buf_almost_empty_thrd;
+    volatile dsi_brg_yuv_cfg_reg_t yuv_cfg;
+    volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl;
+    volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl;
+    volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt;
+} dsi_brg_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dsi_brg_dev_t) == 0xa0, "Invalid size of dsi_brg_dev_t structure");
+#endif
+
+extern dsi_brg_dev_t MIPI_DSI_BRIDGE;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_eco5_struct.h
new file mode 100644
index 0000000000..496ea0095f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_eco5_struct.h
@@ -0,0 +1,2007 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Version Register */
+/** Type of version register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** version : RO; bitpos: [31:0]; default: 825504042;
+         *  NA
+         */
+        uint32_t version:32;
+    };
+    uint32_t val;
+} dsi_host_version_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of pwr_up register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** shutdownz : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t shutdownz:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_host_pwr_up_reg_t;
+
+/** Type of clkmgr_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tx_esc_clk_division : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t tx_esc_clk_division:8;
+        /** to_clk_division : R/W; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t to_clk_division:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_clkmgr_cfg_reg_t;
+
+/** Type of dpi_vcid register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dpi_vcid : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_vcid:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_host_dpi_vcid_reg_t;
+
+/** Type of dpi_color_coding register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dpi_color_coding : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_color_coding:4;
+        uint32_t reserved_4:4;
+        /** loosely18_en : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t loosely18_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} dsi_host_dpi_color_coding_reg_t;
+
+/** Type of dpi_cfg_pol register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dataen_active_low : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dataen_active_low:1;
+        /** vsync_active_low : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t vsync_active_low:1;
+        /** hsync_active_low : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t hsync_active_low:1;
+        /** shutd_active_low : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t shutd_active_low:1;
+        /** colorm_active_low : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t colorm_active_low:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} dsi_host_dpi_cfg_pol_reg_t;
+
+/** Type of dpi_lp_cmd_tim register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** invact_lpcmd_time : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t invact_lpcmd_time:8;
+        uint32_t reserved_8:8;
+        /** outvact_lpcmd_time : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t outvact_lpcmd_time:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dsi_host_dpi_lp_cmd_tim_reg_t;
+
+/** Type of dbi_vcid register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dbi_vcid : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t dbi_vcid:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_host_dbi_vcid_reg_t;
+
+/** Type of dbi_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** in_dbi_conf : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t in_dbi_conf:4;
+        uint32_t reserved_4:4;
+        /** out_dbi_conf : R/W; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t out_dbi_conf:4;
+        uint32_t reserved_12:4;
+        /** lut_size_conf : R/W; bitpos: [17:16]; default: 0;
+         *  NA
+         */
+        uint32_t lut_size_conf:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dsi_host_dbi_cfg_reg_t;
+
+/** Type of dbi_partitioning_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** partitioning_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t partitioning_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_host_dbi_partitioning_en_reg_t;
+
+/** Type of dbi_cmdsize register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** wr_cmd_size : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t wr_cmd_size:16;
+        /** allowed_cmd_size : R/W; bitpos: [31:16]; default: 0;
+         *  NA
+         */
+        uint32_t allowed_cmd_size:16;
+    };
+    uint32_t val;
+} dsi_host_dbi_cmdsize_reg_t;
+
+/** Type of pckhdl_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** eotp_tx_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t eotp_tx_en:1;
+        /** eotp_rx_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t eotp_rx_en:1;
+        /** bta_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t bta_en:1;
+        /** ecc_rx_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_rx_en:1;
+        /** crc_rx_en : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t crc_rx_en:1;
+        /** eotp_tx_lp_en : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t eotp_tx_lp_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dsi_host_pckhdl_cfg_reg_t;
+
+/** Type of gen_vcid register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gen_vcid_rx : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t gen_vcid_rx:2;
+        uint32_t reserved_2:6;
+        /** gen_vcid_tear_auto : R/W; bitpos: [9:8]; default: 0;
+         *  NA
+         */
+        uint32_t gen_vcid_tear_auto:2;
+        uint32_t reserved_10:6;
+        /** gen_vcid_tx_auto : R/W; bitpos: [17:16]; default: 0;
+         *  NA
+         */
+        uint32_t gen_vcid_tx_auto:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dsi_host_gen_vcid_reg_t;
+
+/** Type of mode_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cmd_video_mode : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t cmd_video_mode:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_host_mode_cfg_reg_t;
+
+/** Type of vid_mode_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_mode_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_mode_type:2;
+        uint32_t reserved_2:6;
+        /** lp_vsa_en : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vsa_en:1;
+        /** lp_vbp_en : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vbp_en:1;
+        /** lp_vfp_en : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vfp_en:1;
+        /** lp_vact_en : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vact_en:1;
+        /** lp_hbp_en : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t lp_hbp_en:1;
+        /** lp_hfp_en : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t lp_hfp_en:1;
+        /** frame_bta_ack_en : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t frame_bta_ack_en:1;
+        /** lp_cmd_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t lp_cmd_en:1;
+        /** vpg_en : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t vpg_en:1;
+        uint32_t reserved_17:3;
+        /** vpg_mode : R/W; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t vpg_mode:1;
+        uint32_t reserved_21:3;
+        /** vpg_orientation : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t vpg_orientation:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dsi_host_vid_mode_cfg_reg_t;
+
+/** Type of vid_pkt_size register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_pkt_size : R/W; bitpos: [13:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_pkt_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_host_vid_pkt_size_reg_t;
+
+/** Type of vid_num_chunks register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_num_chunks : R/W; bitpos: [12:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_num_chunks:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dsi_host_vid_num_chunks_reg_t;
+
+/** Type of vid_null_size register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_null_size : R/W; bitpos: [12:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_null_size:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dsi_host_vid_null_size_reg_t;
+
+/** Type of vid_hsa_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hsa_time : R/W; bitpos: [11:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hsa_time:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_host_vid_hsa_time_reg_t;
+
+/** Type of vid_hbp_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hbp_time : R/W; bitpos: [11:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hbp_time:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_host_vid_hbp_time_reg_t;
+
+/** Type of vid_hline_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hline_time : R/W; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hline_time:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dsi_host_vid_hline_time_reg_t;
+
+/** Type of vid_vsa_lines register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vsa_lines : R/W; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vsa_lines:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vsa_lines_reg_t;
+
+/** Type of vid_vbp_lines register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vbp_lines : R/W; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vbp_lines:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vbp_lines_reg_t;
+
+/** Type of vid_vfp_lines register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vfp_lines : R/W; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vfp_lines:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vfp_lines_reg_t;
+
+/** Type of vid_vactive_lines register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** v_active_lines : R/W; bitpos: [13:0]; default: 0;
+         *  NA
+         */
+        uint32_t v_active_lines:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_host_vid_vactive_lines_reg_t;
+
+/** Type of edpi_cmd_size register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** edpi_allowed_cmd_size : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t edpi_allowed_cmd_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_edpi_cmd_size_reg_t;
+
+/** Type of cmd_mode_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tear_fx_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t tear_fx_en:1;
+        /** ack_rqst_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ack_rqst_en:1;
+        uint32_t reserved_2:6;
+        /** gen_sw_0p_tx : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sw_0p_tx:1;
+        /** gen_sw_1p_tx : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sw_1p_tx:1;
+        /** gen_sw_2p_tx : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sw_2p_tx:1;
+        /** gen_sr_0p_tx : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sr_0p_tx:1;
+        /** gen_sr_1p_tx : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sr_1p_tx:1;
+        /** gen_sr_2p_tx : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sr_2p_tx:1;
+        /** gen_lw_tx : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t gen_lw_tx:1;
+        uint32_t reserved_15:1;
+        /** dcs_sw_0p_tx : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t dcs_sw_0p_tx:1;
+        /** dcs_sw_1p_tx : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t dcs_sw_1p_tx:1;
+        /** dcs_sr_0p_tx : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t dcs_sr_0p_tx:1;
+        /** dcs_lw_tx : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t dcs_lw_tx:1;
+        uint32_t reserved_20:4;
+        /** max_rd_pkt_size : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t max_rd_pkt_size:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dsi_host_cmd_mode_cfg_reg_t;
+
+/** Type of gen_hdr register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gen_dt : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t gen_dt:6;
+        /** gen_vc : R/W; bitpos: [7:6]; default: 0;
+         *  NA
+         */
+        uint32_t gen_vc:2;
+        /** gen_wc_lsbyte : R/W; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t gen_wc_lsbyte:8;
+        /** gen_wc_msbyte : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t gen_wc_msbyte:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dsi_host_gen_hdr_reg_t;
+
+/** Type of gen_pld_data register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gen_pld_b1 : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_b1:8;
+        /** gen_pld_b2 : R/W; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_b2:8;
+        /** gen_pld_b3 : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_b3:8;
+        /** gen_pld_b4 : R/W; bitpos: [31:24]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_b4:8;
+    };
+    uint32_t val;
+} dsi_host_gen_pld_data_reg_t;
+
+/** Type of to_cnt_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** lprx_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t lprx_to_cnt:16;
+        /** hstx_to_cnt : R/W; bitpos: [31:16]; default: 0;
+         *  NA
+         */
+        uint32_t hstx_to_cnt:16;
+    };
+    uint32_t val;
+} dsi_host_to_cnt_cfg_reg_t;
+
+/** Type of hs_rd_to_cnt register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** hs_rd_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t hs_rd_to_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_hs_rd_to_cnt_reg_t;
+
+/** Type of lp_rd_to_cnt register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** lp_rd_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t lp_rd_to_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_lp_rd_to_cnt_reg_t;
+
+/** Type of hs_wr_to_cnt register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** hs_wr_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t hs_wr_to_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_hs_wr_to_cnt_reg_t;
+
+/** Type of lp_wr_to_cnt register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** lp_wr_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t lp_wr_to_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_lp_wr_to_cnt_reg_t;
+
+/** Type of bta_to_cnt register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** bta_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t bta_to_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_bta_to_cnt_reg_t;
+
+/** Type of sdf_3d register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mode_3d : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t mode_3d:2;
+        /** format_3d : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t format_3d:2;
+        /** second_vsync : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t second_vsync:1;
+        /** right_first : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t right_first:1;
+        uint32_t reserved_6:10;
+        /** send_3d_cfg : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t send_3d_cfg:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dsi_host_sdf_3d_reg_t;
+
+/** Type of lpclk_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_txrequestclkhs : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_txrequestclkhs:1;
+        /** auto_clklane_ctrl : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t auto_clklane_ctrl:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_host_lpclk_ctrl_reg_t;
+
+/** Type of phy_tmr_lpclk_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_clklp2hs_time : R/W; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_clklp2hs_time:10;
+        uint32_t reserved_10:6;
+        /** phy_clkhs2lp_time : R/W; bitpos: [25:16]; default: 0;
+         *  NA
+         */
+        uint32_t phy_clkhs2lp_time:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} dsi_host_phy_tmr_lpclk_cfg_reg_t;
+
+/** Type of phy_tmr_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_lp2hs_time : R/W; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_lp2hs_time:10;
+        uint32_t reserved_10:6;
+        /** phy_hs2lp_time : R/W; bitpos: [25:16]; default: 0;
+         *  NA
+         */
+        uint32_t phy_hs2lp_time:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} dsi_host_phy_tmr_cfg_reg_t;
+
+/** Type of phy_rstz register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_shutdownz : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_shutdownz:1;
+        /** phy_rstz : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_rstz:1;
+        /** phy_enableclk : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t phy_enableclk:1;
+        /** phy_forcepll : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t phy_forcepll:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dsi_host_phy_rstz_reg_t;
+
+/** Type of phy_if_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** n_lanes : R/W; bitpos: [1:0]; default: 1;
+         *  NA
+         */
+        uint32_t n_lanes:2;
+        uint32_t reserved_2:6;
+        /** phy_stop_wait_time : R/W; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stop_wait_time:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_phy_if_cfg_reg_t;
+
+/** Type of phy_ulps_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_txrequlpsclk : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_txrequlpsclk:1;
+        /** phy_txexitulpsclk : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_txexitulpsclk:1;
+        /** phy_txrequlpslan : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t phy_txrequlpslan:1;
+        /** phy_txexitulpslan : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t phy_txexitulpslan:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dsi_host_phy_ulps_ctrl_reg_t;
+
+/** Type of phy_tx_triggers register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_tx_triggers : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_tx_triggers:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dsi_host_phy_tx_triggers_reg_t;
+
+/** Type of phy_tst_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_testclr : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t phy_testclr:1;
+        /** phy_testclk : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testclk:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_host_phy_tst_ctrl0_reg_t;
+
+/** Type of phy_tst_ctrl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_testdin : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testdin:8;
+        /** pht_testdout : RO; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t pht_testdout:8;
+        /** phy_testen : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testen:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dsi_host_phy_tst_ctrl1_reg_t;
+
+/** Type of phy_cal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** txskewcalhs : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t txskewcalhs:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_host_phy_cal_reg_t;
+
+/** Type of dsc_parameter register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** compression_mode : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t compression_mode:1;
+        uint32_t reserved_1:7;
+        /** compress_algo : R/W; bitpos: [9:8]; default: 0;
+         *  NA
+         */
+        uint32_t compress_algo:2;
+        uint32_t reserved_10:6;
+        /** pps_sel : R/W; bitpos: [17:16]; default: 0;
+         *  NA
+         */
+        uint32_t pps_sel:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dsi_host_dsc_parameter_reg_t;
+
+/** Type of phy_tmr_rd_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** max_rd_time : R/W; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t max_rd_time:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dsi_host_phy_tmr_rd_cfg_reg_t;
+
+/** Type of vid_shadow_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_shadow_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_shadow_en:1;
+        uint32_t reserved_1:7;
+        /** vid_shadow_req : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t vid_shadow_req:1;
+        uint32_t reserved_9:7;
+        /** vid_shadow_pin_req : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t vid_shadow_pin_req:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dsi_host_vid_shadow_ctrl_reg_t;
+
+/** Type of edpi_te_hw_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** hw_tear_effect_on : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t hw_tear_effect_on:1;
+        /** hw_tear_effect_gen : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t hw_tear_effect_gen:1;
+        uint32_t reserved_2:2;
+        /** hw_set_scan_line : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t hw_set_scan_line:1;
+        uint32_t reserved_5:11;
+        /** scan_line_parameter : R/W; bitpos: [31:16]; default: 0;
+         *  NA
+         */
+        uint32_t scan_line_parameter:16;
+    };
+    uint32_t val;
+} dsi_host_edpi_te_hw_cfg_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of cmd_pkt_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gen_cmd_empty : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t gen_cmd_empty:1;
+        /** gen_cmd_full : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t gen_cmd_full:1;
+        /** gen_pld_w_empty : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t gen_pld_w_empty:1;
+        /** gen_pld_w_full : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_w_full:1;
+        /** gen_pld_r_empty : RO; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t gen_pld_r_empty:1;
+        /** gen_pld_r_full : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_r_full:1;
+        /** gen_rd_cmd_busy : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t gen_rd_cmd_busy:1;
+        uint32_t reserved_7:9;
+        /** gen_buff_cmd_empty : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t gen_buff_cmd_empty:1;
+        /** gen_buff_cmd_full : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t gen_buff_cmd_full:1;
+        /** gen_buff_pld_empty : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t gen_buff_pld_empty:1;
+        /** gen_buff_pld_full : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t gen_buff_pld_full:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} dsi_host_cmd_pkt_status_reg_t;
+
+/** Type of phy_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_lock : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_lock:1;
+        /** phy_direction : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_direction:1;
+        /** phy_stopstateclklane : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstateclklane:1;
+        /** phy_ulpsactivenotclk : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t phy_ulpsactivenotclk:1;
+        /** phy_stopstate0lane : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstate0lane:1;
+        /** phy_ulpsactivenot0lane : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t phy_ulpsactivenot0lane:1;
+        /** phy_rxulpsesc0lane : RO; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t phy_rxulpsesc0lane:1;
+        /** phy_stopstate1lane : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstate1lane:1;
+        /** phy_ulpsactivenot1lane : RO; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t phy_ulpsactivenot1lane:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} dsi_host_phy_status_reg_t;
+
+/** Type of dpi_vcid_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dpi_vcid_act : RO; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_vcid_act:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_host_dpi_vcid_act_reg_t;
+
+/** Type of dpi_color_coding_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dpi_color_coding_act : RO; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_color_coding_act:4;
+        uint32_t reserved_4:4;
+        /** loosely18_en_act : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t loosely18_en_act:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} dsi_host_dpi_color_coding_act_reg_t;
+
+/** Type of dpi_lp_cmd_tim_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** invact_lpcmd_time_act : RO; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t invact_lpcmd_time_act:8;
+        uint32_t reserved_8:8;
+        /** outvact_lpcmd_time_act : RO; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t outvact_lpcmd_time_act:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dsi_host_dpi_lp_cmd_tim_act_reg_t;
+
+/** Type of vid_mode_cfg_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_mode_type_act : RO; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_mode_type_act:2;
+        /** lp_vsa_en_act : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vsa_en_act:1;
+        /** lp_vbp_en_act : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vbp_en_act:1;
+        /** lp_vfp_en_act : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vfp_en_act:1;
+        /** lp_vact_en_act : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vact_en_act:1;
+        /** lp_hbp_en_act : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t lp_hbp_en_act:1;
+        /** lp_hfp_en_act : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t lp_hfp_en_act:1;
+        /** frame_bta_ack_en_act : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t frame_bta_ack_en_act:1;
+        /** lp_cmd_en_act : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t lp_cmd_en_act:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_mode_cfg_act_reg_t;
+
+/** Type of vid_pkt_size_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_pkt_size_act : RO; bitpos: [13:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_pkt_size_act:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_host_vid_pkt_size_act_reg_t;
+
+/** Type of vid_num_chunks_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_num_chunks_act : RO; bitpos: [12:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_num_chunks_act:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dsi_host_vid_num_chunks_act_reg_t;
+
+/** Type of vid_null_size_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_null_size_act : RO; bitpos: [12:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_null_size_act:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dsi_host_vid_null_size_act_reg_t;
+
+/** Type of vid_hsa_time_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hsa_time_act : RO; bitpos: [11:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hsa_time_act:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_host_vid_hsa_time_act_reg_t;
+
+/** Type of vid_hbp_time_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hbp_time_act : RO; bitpos: [11:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hbp_time_act:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_host_vid_hbp_time_act_reg_t;
+
+/** Type of vid_hline_time_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hline_time_act : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hline_time_act:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dsi_host_vid_hline_time_act_reg_t;
+
+/** Type of vid_vsa_lines_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vsa_lines_act : RO; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vsa_lines_act:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vsa_lines_act_reg_t;
+
+/** Type of vid_vbp_lines_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vbp_lines_act : RO; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vbp_lines_act:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vbp_lines_act_reg_t;
+
+/** Type of vid_vfp_lines_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vfp_lines_act : RO; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vfp_lines_act:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vfp_lines_act_reg_t;
+
+/** Type of vid_vactive_lines_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** v_active_lines_act : RO; bitpos: [13:0]; default: 0;
+         *  NA
+         */
+        uint32_t v_active_lines_act:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_host_vid_vactive_lines_act_reg_t;
+
+/** Type of vid_pkt_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dpi_cmd_w_empty : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t dpi_cmd_w_empty:1;
+        /** dpi_cmd_w_full : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_cmd_w_full:1;
+        /** dpi_pld_w_empty : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t dpi_pld_w_empty:1;
+        /** dpi_pld_w_full : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_pld_w_full:1;
+        uint32_t reserved_4:12;
+        /** dpi_buff_pld_empty : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t dpi_buff_pld_empty:1;
+        /** dpi_buff_pld_full : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_buff_pld_full:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dsi_host_vid_pkt_status_reg_t;
+
+/** Type of sdf_3d_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mode_3d_act : RO; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t mode_3d_act:2;
+        /** format_3d_act : RO; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t format_3d_act:2;
+        /** second_vsync_act : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t second_vsync_act:1;
+        /** right_first_act : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t right_first_act:1;
+        uint32_t reserved_6:10;
+        /** send_3d_cfg_act : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t send_3d_cfg_act:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dsi_host_sdf_3d_act_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_st0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ack_with_err_0 : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_0:1;
+        /** ack_with_err_1 : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_1:1;
+        /** ack_with_err_2 : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_2:1;
+        /** ack_with_err_3 : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_3:1;
+        /** ack_with_err_4 : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_4:1;
+        /** ack_with_err_5 : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_5:1;
+        /** ack_with_err_6 : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_6:1;
+        /** ack_with_err_7 : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_7:1;
+        /** ack_with_err_8 : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_8:1;
+        /** ack_with_err_9 : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_9:1;
+        /** ack_with_err_10 : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_10:1;
+        /** ack_with_err_11 : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_11:1;
+        /** ack_with_err_12 : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_12:1;
+        /** ack_with_err_13 : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_13:1;
+        /** ack_with_err_14 : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_14:1;
+        /** ack_with_err_15 : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_15:1;
+        /** dphy_errors_0 : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_errors_0:1;
+        /** dphy_errors_1 : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_errors_1:1;
+        /** dphy_errors_2 : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_errors_2:1;
+        /** dphy_errors_3 : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_errors_3:1;
+        /** dphy_errors_4 : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_errors_4:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dsi_host_int_st0_reg_t;
+
+/** Type of int_st1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** to_hs_tx : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t to_hs_tx:1;
+        /** to_lp_rx : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t to_lp_rx:1;
+        /** ecc_single_err : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_single_err:1;
+        /** ecc_milti_err : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_milti_err:1;
+        /** crc_err : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t crc_err:1;
+        /** pkt_size_err : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t pkt_size_err:1;
+        /** eopt_err : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t eopt_err:1;
+        /** dpi_pld_wr_err : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_pld_wr_err:1;
+        /** gen_cmd_wr_err : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t gen_cmd_wr_err:1;
+        /** gen_pld_wr_err : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_wr_err:1;
+        /** gen_pld_send_err : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_send_err:1;
+        /** gen_pld_rd_err : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_rd_err:1;
+        /** gen_pld_recev_err : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_recev_err:1;
+        uint32_t reserved_13:6;
+        /** dpi_buff_pld_under : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_buff_pld_under:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} dsi_host_int_st1_reg_t;
+
+/** Type of int_msk0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_ack_with_err_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_0:1;
+        /** mask_ack_with_err_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_1:1;
+        /** mask_ack_with_err_2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_2:1;
+        /** mask_ack_with_err_3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_3:1;
+        /** mask_ack_with_err_4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_4:1;
+        /** mask_ack_with_err_5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_5:1;
+        /** mask_ack_with_err_6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_6:1;
+        /** mask_ack_with_err_7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_7:1;
+        /** mask_ack_with_err_8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_8:1;
+        /** mask_ack_with_err_9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_9:1;
+        /** mask_ack_with_err_10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_10:1;
+        /** mask_ack_with_err_11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_11:1;
+        /** mask_ack_with_err_12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_12:1;
+        /** mask_ack_with_err_13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_13:1;
+        /** mask_ack_with_err_14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_14:1;
+        /** mask_ack_with_err_15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_15:1;
+        /** mask_dphy_errors_0 : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dphy_errors_0:1;
+        /** mask_dphy_errors_1 : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dphy_errors_1:1;
+        /** mask_dphy_errors_2 : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dphy_errors_2:1;
+        /** mask_dphy_errors_3 : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dphy_errors_3:1;
+        /** mask_dphy_errors_4 : R/W; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dphy_errors_4:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dsi_host_int_msk0_reg_t;
+
+/** Type of int_msk1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_to_hs_tx : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_to_hs_tx:1;
+        /** mask_to_lp_rx : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_to_lp_rx:1;
+        /** mask_ecc_single_err : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ecc_single_err:1;
+        /** mask_ecc_milti_err : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ecc_milti_err:1;
+        /** mask_crc_err : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_crc_err:1;
+        /** mask_pkt_size_err : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_pkt_size_err:1;
+        /** mask_eopt_err : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_eopt_err:1;
+        /** mask_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dpi_pld_wr_err:1;
+        /** mask_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_gen_cmd_wr_err:1;
+        /** mask_gen_pld_wr_err : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_gen_pld_wr_err:1;
+        /** mask_gen_pld_send_err : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_gen_pld_send_err:1;
+        /** mask_gen_pld_rd_err : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_gen_pld_rd_err:1;
+        /** mask_gen_pld_recev_err : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_gen_pld_recev_err:1;
+        uint32_t reserved_13:6;
+        /** mask_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dpi_buff_pld_under:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} dsi_host_int_msk1_reg_t;
+
+/** Type of int_force0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_ack_with_err_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_0:1;
+        /** force_ack_with_err_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_1:1;
+        /** force_ack_with_err_2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_2:1;
+        /** force_ack_with_err_3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_3:1;
+        /** force_ack_with_err_4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_4:1;
+        /** force_ack_with_err_5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_5:1;
+        /** force_ack_with_err_6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_6:1;
+        /** force_ack_with_err_7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_7:1;
+        /** force_ack_with_err_8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_8:1;
+        /** force_ack_with_err_9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_9:1;
+        /** force_ack_with_err_10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_10:1;
+        /** force_ack_with_err_11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_11:1;
+        /** force_ack_with_err_12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_12:1;
+        /** force_ack_with_err_13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_13:1;
+        /** force_ack_with_err_14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_14:1;
+        /** force_ack_with_err_15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_15:1;
+        /** force_dphy_errors_0 : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t force_dphy_errors_0:1;
+        /** force_dphy_errors_1 : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t force_dphy_errors_1:1;
+        /** force_dphy_errors_2 : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t force_dphy_errors_2:1;
+        /** force_dphy_errors_3 : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t force_dphy_errors_3:1;
+        /** force_dphy_errors_4 : R/W; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t force_dphy_errors_4:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dsi_host_int_force0_reg_t;
+
+/** Type of int_force1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_to_hs_tx : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_to_hs_tx:1;
+        /** force_to_lp_rx : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_to_lp_rx:1;
+        /** force_ecc_single_err : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_ecc_single_err:1;
+        /** force_ecc_milti_err : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_ecc_milti_err:1;
+        /** force_crc_err : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_crc_err:1;
+        /** force_pkt_size_err : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_pkt_size_err:1;
+        /** force_eopt_err : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_eopt_err:1;
+        /** force_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_dpi_pld_wr_err:1;
+        /** force_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_gen_cmd_wr_err:1;
+        /** force_gen_pld_wr_err : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_gen_pld_wr_err:1;
+        /** force_gen_pld_send_err : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_gen_pld_send_err:1;
+        /** force_gen_pld_rd_err : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_gen_pld_rd_err:1;
+        /** force_gen_pld_recev_err : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_gen_pld_recev_err:1;
+        uint32_t reserved_13:6;
+        /** force_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t force_dpi_buff_pld_under:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} dsi_host_int_force1_reg_t;
+
+
+typedef struct {
+    volatile dsi_host_version_reg_t version;
+    volatile dsi_host_pwr_up_reg_t pwr_up;
+    volatile dsi_host_clkmgr_cfg_reg_t clkmgr_cfg;
+    volatile dsi_host_dpi_vcid_reg_t dpi_vcid;
+    volatile dsi_host_dpi_color_coding_reg_t dpi_color_coding;
+    volatile dsi_host_dpi_cfg_pol_reg_t dpi_cfg_pol;
+    volatile dsi_host_dpi_lp_cmd_tim_reg_t dpi_lp_cmd_tim;
+    volatile dsi_host_dbi_vcid_reg_t dbi_vcid;
+    volatile dsi_host_dbi_cfg_reg_t dbi_cfg;
+    volatile dsi_host_dbi_partitioning_en_reg_t dbi_partitioning_en;
+    volatile dsi_host_dbi_cmdsize_reg_t dbi_cmdsize;
+    volatile dsi_host_pckhdl_cfg_reg_t pckhdl_cfg;
+    volatile dsi_host_gen_vcid_reg_t gen_vcid;
+    volatile dsi_host_mode_cfg_reg_t mode_cfg;
+    volatile dsi_host_vid_mode_cfg_reg_t vid_mode_cfg;
+    volatile dsi_host_vid_pkt_size_reg_t vid_pkt_size;
+    volatile dsi_host_vid_num_chunks_reg_t vid_num_chunks;
+    volatile dsi_host_vid_null_size_reg_t vid_null_size;
+    volatile dsi_host_vid_hsa_time_reg_t vid_hsa_time;
+    volatile dsi_host_vid_hbp_time_reg_t vid_hbp_time;
+    volatile dsi_host_vid_hline_time_reg_t vid_hline_time;
+    volatile dsi_host_vid_vsa_lines_reg_t vid_vsa_lines;
+    volatile dsi_host_vid_vbp_lines_reg_t vid_vbp_lines;
+    volatile dsi_host_vid_vfp_lines_reg_t vid_vfp_lines;
+    volatile dsi_host_vid_vactive_lines_reg_t vid_vactive_lines;
+    volatile dsi_host_edpi_cmd_size_reg_t edpi_cmd_size;
+    volatile dsi_host_cmd_mode_cfg_reg_t cmd_mode_cfg;
+    volatile dsi_host_gen_hdr_reg_t gen_hdr;
+    volatile dsi_host_gen_pld_data_reg_t gen_pld_data;
+    volatile dsi_host_cmd_pkt_status_reg_t cmd_pkt_status;
+    volatile dsi_host_to_cnt_cfg_reg_t to_cnt_cfg;
+    volatile dsi_host_hs_rd_to_cnt_reg_t hs_rd_to_cnt;
+    volatile dsi_host_lp_rd_to_cnt_reg_t lp_rd_to_cnt;
+    volatile dsi_host_hs_wr_to_cnt_reg_t hs_wr_to_cnt;
+    volatile dsi_host_lp_wr_to_cnt_reg_t lp_wr_to_cnt;
+    volatile dsi_host_bta_to_cnt_reg_t bta_to_cnt;
+    volatile dsi_host_sdf_3d_reg_t sdf_3d;
+    volatile dsi_host_lpclk_ctrl_reg_t lpclk_ctrl;
+    volatile dsi_host_phy_tmr_lpclk_cfg_reg_t phy_tmr_lpclk_cfg;
+    volatile dsi_host_phy_tmr_cfg_reg_t phy_tmr_cfg;
+    volatile dsi_host_phy_rstz_reg_t phy_rstz;
+    volatile dsi_host_phy_if_cfg_reg_t phy_if_cfg;
+    volatile dsi_host_phy_ulps_ctrl_reg_t phy_ulps_ctrl;
+    volatile dsi_host_phy_tx_triggers_reg_t phy_tx_triggers;
+    volatile dsi_host_phy_status_reg_t phy_status;
+    volatile dsi_host_phy_tst_ctrl0_reg_t phy_tst_ctrl0;
+    volatile dsi_host_phy_tst_ctrl1_reg_t phy_tst_ctrl1;
+    volatile dsi_host_int_st0_reg_t int_st0;
+    volatile dsi_host_int_st1_reg_t int_st1;
+    volatile dsi_host_int_msk0_reg_t int_msk0;
+    volatile dsi_host_int_msk1_reg_t int_msk1;
+    volatile dsi_host_phy_cal_reg_t phy_cal;
+    uint32_t reserved_0d0[2];
+    volatile dsi_host_int_force0_reg_t int_force0;
+    volatile dsi_host_int_force1_reg_t int_force1;
+    uint32_t reserved_0e0[4];
+    volatile dsi_host_dsc_parameter_reg_t dsc_parameter;
+    volatile dsi_host_phy_tmr_rd_cfg_reg_t phy_tmr_rd_cfg;
+    uint32_t reserved_0f8[2];
+    volatile dsi_host_vid_shadow_ctrl_reg_t vid_shadow_ctrl;
+    uint32_t reserved_104[2];
+    volatile dsi_host_dpi_vcid_act_reg_t dpi_vcid_act;
+    volatile dsi_host_dpi_color_coding_act_reg_t dpi_color_coding_act;
+    uint32_t reserved_114;
+    volatile dsi_host_dpi_lp_cmd_tim_act_reg_t dpi_lp_cmd_tim_act;
+    volatile dsi_host_edpi_te_hw_cfg_reg_t edpi_te_hw_cfg;
+    uint32_t reserved_120[6];
+    volatile dsi_host_vid_mode_cfg_act_reg_t vid_mode_cfg_act;
+    volatile dsi_host_vid_pkt_size_act_reg_t vid_pkt_size_act;
+    volatile dsi_host_vid_num_chunks_act_reg_t vid_num_chunks_act;
+    volatile dsi_host_vid_null_size_act_reg_t vid_null_size_act;
+    volatile dsi_host_vid_hsa_time_act_reg_t vid_hsa_time_act;
+    volatile dsi_host_vid_hbp_time_act_reg_t vid_hbp_time_act;
+    volatile dsi_host_vid_hline_time_act_reg_t vid_hline_time_act;
+    volatile dsi_host_vid_vsa_lines_act_reg_t vid_vsa_lines_act;
+    volatile dsi_host_vid_vbp_lines_act_reg_t vid_vbp_lines_act;
+    volatile dsi_host_vid_vfp_lines_act_reg_t vid_vfp_lines_act;
+    volatile dsi_host_vid_vactive_lines_act_reg_t vid_vactive_lines_act;
+    uint32_t reserved_164;
+    volatile dsi_host_vid_pkt_status_reg_t vid_pkt_status;
+    uint32_t reserved_16c[9];
+    volatile dsi_host_sdf_3d_act_reg_t sdf_3d_act;
+} dsi_host_dev_t;
+
+extern dsi_host_dev_t MIPI_DSI_HOST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dsi_host_dev_t) == 0x194, "Invalid size of dsi_host_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_reg.h
new file mode 100644
index 0000000000..424140762b
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_reg.h
@@ -0,0 +1,2360 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DSI_HOST_VERSION_REG register
+ *  NA
+ */
+#define DSI_HOST_VERSION_REG (DR_REG_DSI_HOST_BASE + 0x0)
+/** DSI_HOST_VERSION : RO; bitpos: [31:0]; default: 825504042;
+ *  NA
+ */
+#define DSI_HOST_VERSION    0xFFFFFFFFU
+#define DSI_HOST_VERSION_M  (DSI_HOST_VERSION_V << DSI_HOST_VERSION_S)
+#define DSI_HOST_VERSION_V  0xFFFFFFFFU
+#define DSI_HOST_VERSION_S  0
+
+/** DSI_HOST_PWR_UP_REG register
+ *  NA
+ */
+#define DSI_HOST_PWR_UP_REG (DR_REG_DSI_HOST_BASE + 0x4)
+/** DSI_HOST_SHUTDOWNZ : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_SHUTDOWNZ    (BIT(0))
+#define DSI_HOST_SHUTDOWNZ_M  (DSI_HOST_SHUTDOWNZ_V << DSI_HOST_SHUTDOWNZ_S)
+#define DSI_HOST_SHUTDOWNZ_V  0x00000001U
+#define DSI_HOST_SHUTDOWNZ_S  0
+
+/** DSI_HOST_CLKMGR_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_CLKMGR_CFG_REG (DR_REG_DSI_HOST_BASE + 0x8)
+/** DSI_HOST_TX_ESC_CLK_DIVISION : R/W; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_TX_ESC_CLK_DIVISION    0x000000FFU
+#define DSI_HOST_TX_ESC_CLK_DIVISION_M  (DSI_HOST_TX_ESC_CLK_DIVISION_V << DSI_HOST_TX_ESC_CLK_DIVISION_S)
+#define DSI_HOST_TX_ESC_CLK_DIVISION_V  0x000000FFU
+#define DSI_HOST_TX_ESC_CLK_DIVISION_S  0
+/** DSI_HOST_TO_CLK_DIVISION : R/W; bitpos: [15:8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_TO_CLK_DIVISION    0x000000FFU
+#define DSI_HOST_TO_CLK_DIVISION_M  (DSI_HOST_TO_CLK_DIVISION_V << DSI_HOST_TO_CLK_DIVISION_S)
+#define DSI_HOST_TO_CLK_DIVISION_V  0x000000FFU
+#define DSI_HOST_TO_CLK_DIVISION_S  8
+
+/** DSI_HOST_DPI_VCID_REG register
+ *  NA
+ */
+#define DSI_HOST_DPI_VCID_REG (DR_REG_DSI_HOST_BASE + 0xc)
+/** DSI_HOST_DPI_VCID : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPI_VCID    0x00000003U
+#define DSI_HOST_DPI_VCID_M  (DSI_HOST_DPI_VCID_V << DSI_HOST_DPI_VCID_S)
+#define DSI_HOST_DPI_VCID_V  0x00000003U
+#define DSI_HOST_DPI_VCID_S  0
+
+/** DSI_HOST_DPI_COLOR_CODING_REG register
+ *  NA
+ */
+#define DSI_HOST_DPI_COLOR_CODING_REG (DR_REG_DSI_HOST_BASE + 0x10)
+/** DSI_HOST_DPI_COLOR_CODING : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPI_COLOR_CODING    0x0000000FU
+#define DSI_HOST_DPI_COLOR_CODING_M  (DSI_HOST_DPI_COLOR_CODING_V << DSI_HOST_DPI_COLOR_CODING_S)
+#define DSI_HOST_DPI_COLOR_CODING_V  0x0000000FU
+#define DSI_HOST_DPI_COLOR_CODING_S  0
+/** DSI_HOST_LOOSELY18_EN : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LOOSELY18_EN    (BIT(8))
+#define DSI_HOST_LOOSELY18_EN_M  (DSI_HOST_LOOSELY18_EN_V << DSI_HOST_LOOSELY18_EN_S)
+#define DSI_HOST_LOOSELY18_EN_V  0x00000001U
+#define DSI_HOST_LOOSELY18_EN_S  8
+
+/** DSI_HOST_DPI_CFG_POL_REG register
+ *  NA
+ */
+#define DSI_HOST_DPI_CFG_POL_REG (DR_REG_DSI_HOST_BASE + 0x14)
+/** DSI_HOST_DATAEN_ACTIVE_LOW : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DATAEN_ACTIVE_LOW    (BIT(0))
+#define DSI_HOST_DATAEN_ACTIVE_LOW_M  (DSI_HOST_DATAEN_ACTIVE_LOW_V << DSI_HOST_DATAEN_ACTIVE_LOW_S)
+#define DSI_HOST_DATAEN_ACTIVE_LOW_V  0x00000001U
+#define DSI_HOST_DATAEN_ACTIVE_LOW_S  0
+/** DSI_HOST_VSYNC_ACTIVE_LOW : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VSYNC_ACTIVE_LOW    (BIT(1))
+#define DSI_HOST_VSYNC_ACTIVE_LOW_M  (DSI_HOST_VSYNC_ACTIVE_LOW_V << DSI_HOST_VSYNC_ACTIVE_LOW_S)
+#define DSI_HOST_VSYNC_ACTIVE_LOW_V  0x00000001U
+#define DSI_HOST_VSYNC_ACTIVE_LOW_S  1
+/** DSI_HOST_HSYNC_ACTIVE_LOW : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_HSYNC_ACTIVE_LOW    (BIT(2))
+#define DSI_HOST_HSYNC_ACTIVE_LOW_M  (DSI_HOST_HSYNC_ACTIVE_LOW_V << DSI_HOST_HSYNC_ACTIVE_LOW_S)
+#define DSI_HOST_HSYNC_ACTIVE_LOW_V  0x00000001U
+#define DSI_HOST_HSYNC_ACTIVE_LOW_S  2
+/** DSI_HOST_SHUTD_ACTIVE_LOW : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_SHUTD_ACTIVE_LOW    (BIT(3))
+#define DSI_HOST_SHUTD_ACTIVE_LOW_M  (DSI_HOST_SHUTD_ACTIVE_LOW_V << DSI_HOST_SHUTD_ACTIVE_LOW_S)
+#define DSI_HOST_SHUTD_ACTIVE_LOW_V  0x00000001U
+#define DSI_HOST_SHUTD_ACTIVE_LOW_S  3
+/** DSI_HOST_COLORM_ACTIVE_LOW : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_COLORM_ACTIVE_LOW    (BIT(4))
+#define DSI_HOST_COLORM_ACTIVE_LOW_M  (DSI_HOST_COLORM_ACTIVE_LOW_V << DSI_HOST_COLORM_ACTIVE_LOW_S)
+#define DSI_HOST_COLORM_ACTIVE_LOW_V  0x00000001U
+#define DSI_HOST_COLORM_ACTIVE_LOW_S  4
+
+/** DSI_HOST_DPI_LP_CMD_TIM_REG register
+ *  NA
+ */
+#define DSI_HOST_DPI_LP_CMD_TIM_REG (DR_REG_DSI_HOST_BASE + 0x18)
+/** DSI_HOST_INVACT_LPCMD_TIME : R/W; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_INVACT_LPCMD_TIME    0x000000FFU
+#define DSI_HOST_INVACT_LPCMD_TIME_M  (DSI_HOST_INVACT_LPCMD_TIME_V << DSI_HOST_INVACT_LPCMD_TIME_S)
+#define DSI_HOST_INVACT_LPCMD_TIME_V  0x000000FFU
+#define DSI_HOST_INVACT_LPCMD_TIME_S  0
+/** DSI_HOST_OUTVACT_LPCMD_TIME : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_OUTVACT_LPCMD_TIME    0x000000FFU
+#define DSI_HOST_OUTVACT_LPCMD_TIME_M  (DSI_HOST_OUTVACT_LPCMD_TIME_V << DSI_HOST_OUTVACT_LPCMD_TIME_S)
+#define DSI_HOST_OUTVACT_LPCMD_TIME_V  0x000000FFU
+#define DSI_HOST_OUTVACT_LPCMD_TIME_S  16
+
+/** DSI_HOST_DBI_VCID_REG register
+ *  NA
+ */
+#define DSI_HOST_DBI_VCID_REG (DR_REG_DSI_HOST_BASE + 0x1c)
+/** DSI_HOST_DBI_VCID : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DBI_VCID    0x00000003U
+#define DSI_HOST_DBI_VCID_M  (DSI_HOST_DBI_VCID_V << DSI_HOST_DBI_VCID_S)
+#define DSI_HOST_DBI_VCID_V  0x00000003U
+#define DSI_HOST_DBI_VCID_S  0
+
+/** DSI_HOST_DBI_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_DBI_CFG_REG (DR_REG_DSI_HOST_BASE + 0x20)
+/** DSI_HOST_IN_DBI_CONF : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_IN_DBI_CONF    0x0000000FU
+#define DSI_HOST_IN_DBI_CONF_M  (DSI_HOST_IN_DBI_CONF_V << DSI_HOST_IN_DBI_CONF_S)
+#define DSI_HOST_IN_DBI_CONF_V  0x0000000FU
+#define DSI_HOST_IN_DBI_CONF_S  0
+/** DSI_HOST_OUT_DBI_CONF : R/W; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_OUT_DBI_CONF    0x0000000FU
+#define DSI_HOST_OUT_DBI_CONF_M  (DSI_HOST_OUT_DBI_CONF_V << DSI_HOST_OUT_DBI_CONF_S)
+#define DSI_HOST_OUT_DBI_CONF_V  0x0000000FU
+#define DSI_HOST_OUT_DBI_CONF_S  8
+/** DSI_HOST_LUT_SIZE_CONF : R/W; bitpos: [17:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LUT_SIZE_CONF    0x00000003U
+#define DSI_HOST_LUT_SIZE_CONF_M  (DSI_HOST_LUT_SIZE_CONF_V << DSI_HOST_LUT_SIZE_CONF_S)
+#define DSI_HOST_LUT_SIZE_CONF_V  0x00000003U
+#define DSI_HOST_LUT_SIZE_CONF_S  16
+
+/** DSI_HOST_DBI_PARTITIONING_EN_REG register
+ *  NA
+ */
+#define DSI_HOST_DBI_PARTITIONING_EN_REG (DR_REG_DSI_HOST_BASE + 0x24)
+/** DSI_HOST_PARTITIONING_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PARTITIONING_EN    (BIT(0))
+#define DSI_HOST_PARTITIONING_EN_M  (DSI_HOST_PARTITIONING_EN_V << DSI_HOST_PARTITIONING_EN_S)
+#define DSI_HOST_PARTITIONING_EN_V  0x00000001U
+#define DSI_HOST_PARTITIONING_EN_S  0
+
+/** DSI_HOST_DBI_CMDSIZE_REG register
+ *  NA
+ */
+#define DSI_HOST_DBI_CMDSIZE_REG (DR_REG_DSI_HOST_BASE + 0x28)
+/** DSI_HOST_WR_CMD_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_WR_CMD_SIZE    0x0000FFFFU
+#define DSI_HOST_WR_CMD_SIZE_M  (DSI_HOST_WR_CMD_SIZE_V << DSI_HOST_WR_CMD_SIZE_S)
+#define DSI_HOST_WR_CMD_SIZE_V  0x0000FFFFU
+#define DSI_HOST_WR_CMD_SIZE_S  0
+/** DSI_HOST_ALLOWED_CMD_SIZE : R/W; bitpos: [31:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ALLOWED_CMD_SIZE    0x0000FFFFU
+#define DSI_HOST_ALLOWED_CMD_SIZE_M  (DSI_HOST_ALLOWED_CMD_SIZE_V << DSI_HOST_ALLOWED_CMD_SIZE_S)
+#define DSI_HOST_ALLOWED_CMD_SIZE_V  0x0000FFFFU
+#define DSI_HOST_ALLOWED_CMD_SIZE_S  16
+
+/** DSI_HOST_PCKHDL_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_PCKHDL_CFG_REG (DR_REG_DSI_HOST_BASE + 0x2c)
+/** DSI_HOST_EOTP_TX_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_EOTP_TX_EN    (BIT(0))
+#define DSI_HOST_EOTP_TX_EN_M  (DSI_HOST_EOTP_TX_EN_V << DSI_HOST_EOTP_TX_EN_S)
+#define DSI_HOST_EOTP_TX_EN_V  0x00000001U
+#define DSI_HOST_EOTP_TX_EN_S  0
+/** DSI_HOST_EOTP_RX_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_EOTP_RX_EN    (BIT(1))
+#define DSI_HOST_EOTP_RX_EN_M  (DSI_HOST_EOTP_RX_EN_V << DSI_HOST_EOTP_RX_EN_S)
+#define DSI_HOST_EOTP_RX_EN_V  0x00000001U
+#define DSI_HOST_EOTP_RX_EN_S  1
+/** DSI_HOST_BTA_EN : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_BTA_EN    (BIT(2))
+#define DSI_HOST_BTA_EN_M  (DSI_HOST_BTA_EN_V << DSI_HOST_BTA_EN_S)
+#define DSI_HOST_BTA_EN_V  0x00000001U
+#define DSI_HOST_BTA_EN_S  2
+/** DSI_HOST_ECC_RX_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ECC_RX_EN    (BIT(3))
+#define DSI_HOST_ECC_RX_EN_M  (DSI_HOST_ECC_RX_EN_V << DSI_HOST_ECC_RX_EN_S)
+#define DSI_HOST_ECC_RX_EN_V  0x00000001U
+#define DSI_HOST_ECC_RX_EN_S  3
+/** DSI_HOST_CRC_RX_EN : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_CRC_RX_EN    (BIT(4))
+#define DSI_HOST_CRC_RX_EN_M  (DSI_HOST_CRC_RX_EN_V << DSI_HOST_CRC_RX_EN_S)
+#define DSI_HOST_CRC_RX_EN_V  0x00000001U
+#define DSI_HOST_CRC_RX_EN_S  4
+/** DSI_HOST_EOTP_TX_LP_EN : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_EOTP_TX_LP_EN    (BIT(5))
+#define DSI_HOST_EOTP_TX_LP_EN_M  (DSI_HOST_EOTP_TX_LP_EN_V << DSI_HOST_EOTP_TX_LP_EN_S)
+#define DSI_HOST_EOTP_TX_LP_EN_V  0x00000001U
+#define DSI_HOST_EOTP_TX_LP_EN_S  5
+
+/** DSI_HOST_GEN_VCID_REG register
+ *  NA
+ */
+#define DSI_HOST_GEN_VCID_REG (DR_REG_DSI_HOST_BASE + 0x30)
+/** DSI_HOST_GEN_VCID_RX : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_VCID_RX    0x00000003U
+#define DSI_HOST_GEN_VCID_RX_M  (DSI_HOST_GEN_VCID_RX_V << DSI_HOST_GEN_VCID_RX_S)
+#define DSI_HOST_GEN_VCID_RX_V  0x00000003U
+#define DSI_HOST_GEN_VCID_RX_S  0
+/** DSI_HOST_GEN_VCID_TEAR_AUTO : R/W; bitpos: [9:8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_VCID_TEAR_AUTO    0x00000003U
+#define DSI_HOST_GEN_VCID_TEAR_AUTO_M  (DSI_HOST_GEN_VCID_TEAR_AUTO_V << DSI_HOST_GEN_VCID_TEAR_AUTO_S)
+#define DSI_HOST_GEN_VCID_TEAR_AUTO_V  0x00000003U
+#define DSI_HOST_GEN_VCID_TEAR_AUTO_S  8
+/** DSI_HOST_GEN_VCID_TX_AUTO : R/W; bitpos: [17:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_VCID_TX_AUTO    0x00000003U
+#define DSI_HOST_GEN_VCID_TX_AUTO_M  (DSI_HOST_GEN_VCID_TX_AUTO_V << DSI_HOST_GEN_VCID_TX_AUTO_S)
+#define DSI_HOST_GEN_VCID_TX_AUTO_V  0x00000003U
+#define DSI_HOST_GEN_VCID_TX_AUTO_S  16
+
+/** DSI_HOST_MODE_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_MODE_CFG_REG (DR_REG_DSI_HOST_BASE + 0x34)
+/** DSI_HOST_CMD_VIDEO_MODE : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_CMD_VIDEO_MODE    (BIT(0))
+#define DSI_HOST_CMD_VIDEO_MODE_M  (DSI_HOST_CMD_VIDEO_MODE_V << DSI_HOST_CMD_VIDEO_MODE_S)
+#define DSI_HOST_CMD_VIDEO_MODE_V  0x00000001U
+#define DSI_HOST_CMD_VIDEO_MODE_S  0
+
+/** DSI_HOST_VID_MODE_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_MODE_CFG_REG (DR_REG_DSI_HOST_BASE + 0x38)
+/** DSI_HOST_VID_MODE_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_MODE_TYPE    0x00000003U
+#define DSI_HOST_VID_MODE_TYPE_M  (DSI_HOST_VID_MODE_TYPE_V << DSI_HOST_VID_MODE_TYPE_S)
+#define DSI_HOST_VID_MODE_TYPE_V  0x00000003U
+#define DSI_HOST_VID_MODE_TYPE_S  0
+/** DSI_HOST_LP_VSA_EN : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_VSA_EN    (BIT(8))
+#define DSI_HOST_LP_VSA_EN_M  (DSI_HOST_LP_VSA_EN_V << DSI_HOST_LP_VSA_EN_S)
+#define DSI_HOST_LP_VSA_EN_V  0x00000001U
+#define DSI_HOST_LP_VSA_EN_S  8
+/** DSI_HOST_LP_VBP_EN : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_VBP_EN    (BIT(9))
+#define DSI_HOST_LP_VBP_EN_M  (DSI_HOST_LP_VBP_EN_V << DSI_HOST_LP_VBP_EN_S)
+#define DSI_HOST_LP_VBP_EN_V  0x00000001U
+#define DSI_HOST_LP_VBP_EN_S  9
+/** DSI_HOST_LP_VFP_EN : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_VFP_EN    (BIT(10))
+#define DSI_HOST_LP_VFP_EN_M  (DSI_HOST_LP_VFP_EN_V << DSI_HOST_LP_VFP_EN_S)
+#define DSI_HOST_LP_VFP_EN_V  0x00000001U
+#define DSI_HOST_LP_VFP_EN_S  10
+/** DSI_HOST_LP_VACT_EN : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_VACT_EN    (BIT(11))
+#define DSI_HOST_LP_VACT_EN_M  (DSI_HOST_LP_VACT_EN_V << DSI_HOST_LP_VACT_EN_S)
+#define DSI_HOST_LP_VACT_EN_V  0x00000001U
+#define DSI_HOST_LP_VACT_EN_S  11
+/** DSI_HOST_LP_HBP_EN : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_HBP_EN    (BIT(12))
+#define DSI_HOST_LP_HBP_EN_M  (DSI_HOST_LP_HBP_EN_V << DSI_HOST_LP_HBP_EN_S)
+#define DSI_HOST_LP_HBP_EN_V  0x00000001U
+#define DSI_HOST_LP_HBP_EN_S  12
+/** DSI_HOST_LP_HFP_EN : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_HFP_EN    (BIT(13))
+#define DSI_HOST_LP_HFP_EN_M  (DSI_HOST_LP_HFP_EN_V << DSI_HOST_LP_HFP_EN_S)
+#define DSI_HOST_LP_HFP_EN_V  0x00000001U
+#define DSI_HOST_LP_HFP_EN_S  13
+/** DSI_HOST_FRAME_BTA_ACK_EN : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FRAME_BTA_ACK_EN    (BIT(14))
+#define DSI_HOST_FRAME_BTA_ACK_EN_M  (DSI_HOST_FRAME_BTA_ACK_EN_V << DSI_HOST_FRAME_BTA_ACK_EN_S)
+#define DSI_HOST_FRAME_BTA_ACK_EN_V  0x00000001U
+#define DSI_HOST_FRAME_BTA_ACK_EN_S  14
+/** DSI_HOST_LP_CMD_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_CMD_EN    (BIT(15))
+#define DSI_HOST_LP_CMD_EN_M  (DSI_HOST_LP_CMD_EN_V << DSI_HOST_LP_CMD_EN_S)
+#define DSI_HOST_LP_CMD_EN_V  0x00000001U
+#define DSI_HOST_LP_CMD_EN_S  15
+/** DSI_HOST_VPG_EN : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VPG_EN    (BIT(16))
+#define DSI_HOST_VPG_EN_M  (DSI_HOST_VPG_EN_V << DSI_HOST_VPG_EN_S)
+#define DSI_HOST_VPG_EN_V  0x00000001U
+#define DSI_HOST_VPG_EN_S  16
+/** DSI_HOST_VPG_MODE : R/W; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VPG_MODE    (BIT(20))
+#define DSI_HOST_VPG_MODE_M  (DSI_HOST_VPG_MODE_V << DSI_HOST_VPG_MODE_S)
+#define DSI_HOST_VPG_MODE_V  0x00000001U
+#define DSI_HOST_VPG_MODE_S  20
+/** DSI_HOST_VPG_ORIENTATION : R/W; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VPG_ORIENTATION    (BIT(24))
+#define DSI_HOST_VPG_ORIENTATION_M  (DSI_HOST_VPG_ORIENTATION_V << DSI_HOST_VPG_ORIENTATION_S)
+#define DSI_HOST_VPG_ORIENTATION_V  0x00000001U
+#define DSI_HOST_VPG_ORIENTATION_S  24
+
+/** DSI_HOST_VID_PKT_SIZE_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_PKT_SIZE_REG (DR_REG_DSI_HOST_BASE + 0x3c)
+/** DSI_HOST_VID_PKT_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_PKT_SIZE    0x00003FFFU
+#define DSI_HOST_VID_PKT_SIZE_M  (DSI_HOST_VID_PKT_SIZE_V << DSI_HOST_VID_PKT_SIZE_S)
+#define DSI_HOST_VID_PKT_SIZE_V  0x00003FFFU
+#define DSI_HOST_VID_PKT_SIZE_S  0
+
+/** DSI_HOST_VID_NUM_CHUNKS_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_NUM_CHUNKS_REG (DR_REG_DSI_HOST_BASE + 0x40)
+/** DSI_HOST_VID_NUM_CHUNKS : R/W; bitpos: [12:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_NUM_CHUNKS    0x00001FFFU
+#define DSI_HOST_VID_NUM_CHUNKS_M  (DSI_HOST_VID_NUM_CHUNKS_V << DSI_HOST_VID_NUM_CHUNKS_S)
+#define DSI_HOST_VID_NUM_CHUNKS_V  0x00001FFFU
+#define DSI_HOST_VID_NUM_CHUNKS_S  0
+
+/** DSI_HOST_VID_NULL_SIZE_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_NULL_SIZE_REG (DR_REG_DSI_HOST_BASE + 0x44)
+/** DSI_HOST_VID_NULL_SIZE : R/W; bitpos: [12:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_NULL_SIZE    0x00001FFFU
+#define DSI_HOST_VID_NULL_SIZE_M  (DSI_HOST_VID_NULL_SIZE_V << DSI_HOST_VID_NULL_SIZE_S)
+#define DSI_HOST_VID_NULL_SIZE_V  0x00001FFFU
+#define DSI_HOST_VID_NULL_SIZE_S  0
+
+/** DSI_HOST_VID_HSA_TIME_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_HSA_TIME_REG (DR_REG_DSI_HOST_BASE + 0x48)
+/** DSI_HOST_VID_HSA_TIME : R/W; bitpos: [11:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_HSA_TIME    0x00000FFFU
+#define DSI_HOST_VID_HSA_TIME_M  (DSI_HOST_VID_HSA_TIME_V << DSI_HOST_VID_HSA_TIME_S)
+#define DSI_HOST_VID_HSA_TIME_V  0x00000FFFU
+#define DSI_HOST_VID_HSA_TIME_S  0
+
+/** DSI_HOST_VID_HBP_TIME_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_HBP_TIME_REG (DR_REG_DSI_HOST_BASE + 0x4c)
+/** DSI_HOST_VID_HBP_TIME : R/W; bitpos: [11:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_HBP_TIME    0x00000FFFU
+#define DSI_HOST_VID_HBP_TIME_M  (DSI_HOST_VID_HBP_TIME_V << DSI_HOST_VID_HBP_TIME_S)
+#define DSI_HOST_VID_HBP_TIME_V  0x00000FFFU
+#define DSI_HOST_VID_HBP_TIME_S  0
+
+/** DSI_HOST_VID_HLINE_TIME_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_HLINE_TIME_REG (DR_REG_DSI_HOST_BASE + 0x50)
+/** DSI_HOST_VID_HLINE_TIME : R/W; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_HLINE_TIME    0x00007FFFU
+#define DSI_HOST_VID_HLINE_TIME_M  (DSI_HOST_VID_HLINE_TIME_V << DSI_HOST_VID_HLINE_TIME_S)
+#define DSI_HOST_VID_HLINE_TIME_V  0x00007FFFU
+#define DSI_HOST_VID_HLINE_TIME_S  0
+
+/** DSI_HOST_VID_VSA_LINES_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_VSA_LINES_REG (DR_REG_DSI_HOST_BASE + 0x54)
+/** DSI_HOST_VSA_LINES : R/W; bitpos: [9:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VSA_LINES    0x000003FFU
+#define DSI_HOST_VSA_LINES_M  (DSI_HOST_VSA_LINES_V << DSI_HOST_VSA_LINES_S)
+#define DSI_HOST_VSA_LINES_V  0x000003FFU
+#define DSI_HOST_VSA_LINES_S  0
+
+/** DSI_HOST_VID_VBP_LINES_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_VBP_LINES_REG (DR_REG_DSI_HOST_BASE + 0x58)
+/** DSI_HOST_VBP_LINES : R/W; bitpos: [9:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VBP_LINES    0x000003FFU
+#define DSI_HOST_VBP_LINES_M  (DSI_HOST_VBP_LINES_V << DSI_HOST_VBP_LINES_S)
+#define DSI_HOST_VBP_LINES_V  0x000003FFU
+#define DSI_HOST_VBP_LINES_S  0
+
+/** DSI_HOST_VID_VFP_LINES_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_VFP_LINES_REG (DR_REG_DSI_HOST_BASE + 0x5c)
+/** DSI_HOST_VFP_LINES : R/W; bitpos: [9:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VFP_LINES    0x000003FFU
+#define DSI_HOST_VFP_LINES_M  (DSI_HOST_VFP_LINES_V << DSI_HOST_VFP_LINES_S)
+#define DSI_HOST_VFP_LINES_V  0x000003FFU
+#define DSI_HOST_VFP_LINES_S  0
+
+/** DSI_HOST_VID_VACTIVE_LINES_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_VACTIVE_LINES_REG (DR_REG_DSI_HOST_BASE + 0x60)
+/** DSI_HOST_V_ACTIVE_LINES : R/W; bitpos: [13:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_V_ACTIVE_LINES    0x00003FFFU
+#define DSI_HOST_V_ACTIVE_LINES_M  (DSI_HOST_V_ACTIVE_LINES_V << DSI_HOST_V_ACTIVE_LINES_S)
+#define DSI_HOST_V_ACTIVE_LINES_V  0x00003FFFU
+#define DSI_HOST_V_ACTIVE_LINES_S  0
+
+/** DSI_HOST_EDPI_CMD_SIZE_REG register
+ *  NA
+ */
+#define DSI_HOST_EDPI_CMD_SIZE_REG (DR_REG_DSI_HOST_BASE + 0x64)
+/** DSI_HOST_EDPI_ALLOWED_CMD_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_EDPI_ALLOWED_CMD_SIZE    0x0000FFFFU
+#define DSI_HOST_EDPI_ALLOWED_CMD_SIZE_M  (DSI_HOST_EDPI_ALLOWED_CMD_SIZE_V << DSI_HOST_EDPI_ALLOWED_CMD_SIZE_S)
+#define DSI_HOST_EDPI_ALLOWED_CMD_SIZE_V  0x0000FFFFU
+#define DSI_HOST_EDPI_ALLOWED_CMD_SIZE_S  0
+
+/** DSI_HOST_CMD_MODE_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_CMD_MODE_CFG_REG (DR_REG_DSI_HOST_BASE + 0x68)
+/** DSI_HOST_TEAR_FX_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_TEAR_FX_EN    (BIT(0))
+#define DSI_HOST_TEAR_FX_EN_M  (DSI_HOST_TEAR_FX_EN_V << DSI_HOST_TEAR_FX_EN_S)
+#define DSI_HOST_TEAR_FX_EN_V  0x00000001U
+#define DSI_HOST_TEAR_FX_EN_S  0
+/** DSI_HOST_ACK_RQST_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_RQST_EN    (BIT(1))
+#define DSI_HOST_ACK_RQST_EN_M  (DSI_HOST_ACK_RQST_EN_V << DSI_HOST_ACK_RQST_EN_S)
+#define DSI_HOST_ACK_RQST_EN_V  0x00000001U
+#define DSI_HOST_ACK_RQST_EN_S  1
+/** DSI_HOST_GEN_SW_0P_TX : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_SW_0P_TX    (BIT(8))
+#define DSI_HOST_GEN_SW_0P_TX_M  (DSI_HOST_GEN_SW_0P_TX_V << DSI_HOST_GEN_SW_0P_TX_S)
+#define DSI_HOST_GEN_SW_0P_TX_V  0x00000001U
+#define DSI_HOST_GEN_SW_0P_TX_S  8
+/** DSI_HOST_GEN_SW_1P_TX : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_SW_1P_TX    (BIT(9))
+#define DSI_HOST_GEN_SW_1P_TX_M  (DSI_HOST_GEN_SW_1P_TX_V << DSI_HOST_GEN_SW_1P_TX_S)
+#define DSI_HOST_GEN_SW_1P_TX_V  0x00000001U
+#define DSI_HOST_GEN_SW_1P_TX_S  9
+/** DSI_HOST_GEN_SW_2P_TX : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_SW_2P_TX    (BIT(10))
+#define DSI_HOST_GEN_SW_2P_TX_M  (DSI_HOST_GEN_SW_2P_TX_V << DSI_HOST_GEN_SW_2P_TX_S)
+#define DSI_HOST_GEN_SW_2P_TX_V  0x00000001U
+#define DSI_HOST_GEN_SW_2P_TX_S  10
+/** DSI_HOST_GEN_SR_0P_TX : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_SR_0P_TX    (BIT(11))
+#define DSI_HOST_GEN_SR_0P_TX_M  (DSI_HOST_GEN_SR_0P_TX_V << DSI_HOST_GEN_SR_0P_TX_S)
+#define DSI_HOST_GEN_SR_0P_TX_V  0x00000001U
+#define DSI_HOST_GEN_SR_0P_TX_S  11
+/** DSI_HOST_GEN_SR_1P_TX : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_SR_1P_TX    (BIT(12))
+#define DSI_HOST_GEN_SR_1P_TX_M  (DSI_HOST_GEN_SR_1P_TX_V << DSI_HOST_GEN_SR_1P_TX_S)
+#define DSI_HOST_GEN_SR_1P_TX_V  0x00000001U
+#define DSI_HOST_GEN_SR_1P_TX_S  12
+/** DSI_HOST_GEN_SR_2P_TX : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_SR_2P_TX    (BIT(13))
+#define DSI_HOST_GEN_SR_2P_TX_M  (DSI_HOST_GEN_SR_2P_TX_V << DSI_HOST_GEN_SR_2P_TX_S)
+#define DSI_HOST_GEN_SR_2P_TX_V  0x00000001U
+#define DSI_HOST_GEN_SR_2P_TX_S  13
+/** DSI_HOST_GEN_LW_TX : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_LW_TX    (BIT(14))
+#define DSI_HOST_GEN_LW_TX_M  (DSI_HOST_GEN_LW_TX_V << DSI_HOST_GEN_LW_TX_S)
+#define DSI_HOST_GEN_LW_TX_V  0x00000001U
+#define DSI_HOST_GEN_LW_TX_S  14
+/** DSI_HOST_DCS_SW_0P_TX : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DCS_SW_0P_TX    (BIT(16))
+#define DSI_HOST_DCS_SW_0P_TX_M  (DSI_HOST_DCS_SW_0P_TX_V << DSI_HOST_DCS_SW_0P_TX_S)
+#define DSI_HOST_DCS_SW_0P_TX_V  0x00000001U
+#define DSI_HOST_DCS_SW_0P_TX_S  16
+/** DSI_HOST_DCS_SW_1P_TX : R/W; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DCS_SW_1P_TX    (BIT(17))
+#define DSI_HOST_DCS_SW_1P_TX_M  (DSI_HOST_DCS_SW_1P_TX_V << DSI_HOST_DCS_SW_1P_TX_S)
+#define DSI_HOST_DCS_SW_1P_TX_V  0x00000001U
+#define DSI_HOST_DCS_SW_1P_TX_S  17
+/** DSI_HOST_DCS_SR_0P_TX : R/W; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DCS_SR_0P_TX    (BIT(18))
+#define DSI_HOST_DCS_SR_0P_TX_M  (DSI_HOST_DCS_SR_0P_TX_V << DSI_HOST_DCS_SR_0P_TX_S)
+#define DSI_HOST_DCS_SR_0P_TX_V  0x00000001U
+#define DSI_HOST_DCS_SR_0P_TX_S  18
+/** DSI_HOST_DCS_LW_TX : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DCS_LW_TX    (BIT(19))
+#define DSI_HOST_DCS_LW_TX_M  (DSI_HOST_DCS_LW_TX_V << DSI_HOST_DCS_LW_TX_S)
+#define DSI_HOST_DCS_LW_TX_V  0x00000001U
+#define DSI_HOST_DCS_LW_TX_S  19
+/** DSI_HOST_MAX_RD_PKT_SIZE : R/W; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MAX_RD_PKT_SIZE    (BIT(24))
+#define DSI_HOST_MAX_RD_PKT_SIZE_M  (DSI_HOST_MAX_RD_PKT_SIZE_V << DSI_HOST_MAX_RD_PKT_SIZE_S)
+#define DSI_HOST_MAX_RD_PKT_SIZE_V  0x00000001U
+#define DSI_HOST_MAX_RD_PKT_SIZE_S  24
+
+/** DSI_HOST_GEN_HDR_REG register
+ *  NA
+ */
+#define DSI_HOST_GEN_HDR_REG (DR_REG_DSI_HOST_BASE + 0x6c)
+/** DSI_HOST_GEN_DT : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_DT    0x0000003FU
+#define DSI_HOST_GEN_DT_M  (DSI_HOST_GEN_DT_V << DSI_HOST_GEN_DT_S)
+#define DSI_HOST_GEN_DT_V  0x0000003FU
+#define DSI_HOST_GEN_DT_S  0
+/** DSI_HOST_GEN_VC : R/W; bitpos: [7:6]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_VC    0x00000003U
+#define DSI_HOST_GEN_VC_M  (DSI_HOST_GEN_VC_V << DSI_HOST_GEN_VC_S)
+#define DSI_HOST_GEN_VC_V  0x00000003U
+#define DSI_HOST_GEN_VC_S  6
+/** DSI_HOST_GEN_WC_LSBYTE : R/W; bitpos: [15:8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_WC_LSBYTE    0x000000FFU
+#define DSI_HOST_GEN_WC_LSBYTE_M  (DSI_HOST_GEN_WC_LSBYTE_V << DSI_HOST_GEN_WC_LSBYTE_S)
+#define DSI_HOST_GEN_WC_LSBYTE_V  0x000000FFU
+#define DSI_HOST_GEN_WC_LSBYTE_S  8
+/** DSI_HOST_GEN_WC_MSBYTE : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_WC_MSBYTE    0x000000FFU
+#define DSI_HOST_GEN_WC_MSBYTE_M  (DSI_HOST_GEN_WC_MSBYTE_V << DSI_HOST_GEN_WC_MSBYTE_S)
+#define DSI_HOST_GEN_WC_MSBYTE_V  0x000000FFU
+#define DSI_HOST_GEN_WC_MSBYTE_S  16
+
+/** DSI_HOST_GEN_PLD_DATA_REG register
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_DATA_REG (DR_REG_DSI_HOST_BASE + 0x70)
+/** DSI_HOST_GEN_PLD_B1 : R/W; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_B1    0x000000FFU
+#define DSI_HOST_GEN_PLD_B1_M  (DSI_HOST_GEN_PLD_B1_V << DSI_HOST_GEN_PLD_B1_S)
+#define DSI_HOST_GEN_PLD_B1_V  0x000000FFU
+#define DSI_HOST_GEN_PLD_B1_S  0
+/** DSI_HOST_GEN_PLD_B2 : R/W; bitpos: [15:8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_B2    0x000000FFU
+#define DSI_HOST_GEN_PLD_B2_M  (DSI_HOST_GEN_PLD_B2_V << DSI_HOST_GEN_PLD_B2_S)
+#define DSI_HOST_GEN_PLD_B2_V  0x000000FFU
+#define DSI_HOST_GEN_PLD_B2_S  8
+/** DSI_HOST_GEN_PLD_B3 : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_B3    0x000000FFU
+#define DSI_HOST_GEN_PLD_B3_M  (DSI_HOST_GEN_PLD_B3_V << DSI_HOST_GEN_PLD_B3_S)
+#define DSI_HOST_GEN_PLD_B3_V  0x000000FFU
+#define DSI_HOST_GEN_PLD_B3_S  16
+/** DSI_HOST_GEN_PLD_B4 : R/W; bitpos: [31:24]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_B4    0x000000FFU
+#define DSI_HOST_GEN_PLD_B4_M  (DSI_HOST_GEN_PLD_B4_V << DSI_HOST_GEN_PLD_B4_S)
+#define DSI_HOST_GEN_PLD_B4_V  0x000000FFU
+#define DSI_HOST_GEN_PLD_B4_S  24
+
+/** DSI_HOST_CMD_PKT_STATUS_REG register
+ *  NA
+ */
+#define DSI_HOST_CMD_PKT_STATUS_REG (DR_REG_DSI_HOST_BASE + 0x74)
+/** DSI_HOST_GEN_CMD_EMPTY : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_GEN_CMD_EMPTY    (BIT(0))
+#define DSI_HOST_GEN_CMD_EMPTY_M  (DSI_HOST_GEN_CMD_EMPTY_V << DSI_HOST_GEN_CMD_EMPTY_S)
+#define DSI_HOST_GEN_CMD_EMPTY_V  0x00000001U
+#define DSI_HOST_GEN_CMD_EMPTY_S  0
+/** DSI_HOST_GEN_CMD_FULL : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_CMD_FULL    (BIT(1))
+#define DSI_HOST_GEN_CMD_FULL_M  (DSI_HOST_GEN_CMD_FULL_V << DSI_HOST_GEN_CMD_FULL_S)
+#define DSI_HOST_GEN_CMD_FULL_V  0x00000001U
+#define DSI_HOST_GEN_CMD_FULL_S  1
+/** DSI_HOST_GEN_PLD_W_EMPTY : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_W_EMPTY    (BIT(2))
+#define DSI_HOST_GEN_PLD_W_EMPTY_M  (DSI_HOST_GEN_PLD_W_EMPTY_V << DSI_HOST_GEN_PLD_W_EMPTY_S)
+#define DSI_HOST_GEN_PLD_W_EMPTY_V  0x00000001U
+#define DSI_HOST_GEN_PLD_W_EMPTY_S  2
+/** DSI_HOST_GEN_PLD_W_FULL : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_W_FULL    (BIT(3))
+#define DSI_HOST_GEN_PLD_W_FULL_M  (DSI_HOST_GEN_PLD_W_FULL_V << DSI_HOST_GEN_PLD_W_FULL_S)
+#define DSI_HOST_GEN_PLD_W_FULL_V  0x00000001U
+#define DSI_HOST_GEN_PLD_W_FULL_S  3
+/** DSI_HOST_GEN_PLD_R_EMPTY : RO; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_R_EMPTY    (BIT(4))
+#define DSI_HOST_GEN_PLD_R_EMPTY_M  (DSI_HOST_GEN_PLD_R_EMPTY_V << DSI_HOST_GEN_PLD_R_EMPTY_S)
+#define DSI_HOST_GEN_PLD_R_EMPTY_V  0x00000001U
+#define DSI_HOST_GEN_PLD_R_EMPTY_S  4
+/** DSI_HOST_GEN_PLD_R_FULL : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_R_FULL    (BIT(5))
+#define DSI_HOST_GEN_PLD_R_FULL_M  (DSI_HOST_GEN_PLD_R_FULL_V << DSI_HOST_GEN_PLD_R_FULL_S)
+#define DSI_HOST_GEN_PLD_R_FULL_V  0x00000001U
+#define DSI_HOST_GEN_PLD_R_FULL_S  5
+/** DSI_HOST_GEN_RD_CMD_BUSY : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_RD_CMD_BUSY    (BIT(6))
+#define DSI_HOST_GEN_RD_CMD_BUSY_M  (DSI_HOST_GEN_RD_CMD_BUSY_V << DSI_HOST_GEN_RD_CMD_BUSY_S)
+#define DSI_HOST_GEN_RD_CMD_BUSY_V  0x00000001U
+#define DSI_HOST_GEN_RD_CMD_BUSY_S  6
+/** DSI_HOST_GEN_BUFF_CMD_EMPTY : RO; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_GEN_BUFF_CMD_EMPTY    (BIT(16))
+#define DSI_HOST_GEN_BUFF_CMD_EMPTY_M  (DSI_HOST_GEN_BUFF_CMD_EMPTY_V << DSI_HOST_GEN_BUFF_CMD_EMPTY_S)
+#define DSI_HOST_GEN_BUFF_CMD_EMPTY_V  0x00000001U
+#define DSI_HOST_GEN_BUFF_CMD_EMPTY_S  16
+/** DSI_HOST_GEN_BUFF_CMD_FULL : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_BUFF_CMD_FULL    (BIT(17))
+#define DSI_HOST_GEN_BUFF_CMD_FULL_M  (DSI_HOST_GEN_BUFF_CMD_FULL_V << DSI_HOST_GEN_BUFF_CMD_FULL_S)
+#define DSI_HOST_GEN_BUFF_CMD_FULL_V  0x00000001U
+#define DSI_HOST_GEN_BUFF_CMD_FULL_S  17
+/** DSI_HOST_GEN_BUFF_PLD_EMPTY : RO; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_GEN_BUFF_PLD_EMPTY    (BIT(18))
+#define DSI_HOST_GEN_BUFF_PLD_EMPTY_M  (DSI_HOST_GEN_BUFF_PLD_EMPTY_V << DSI_HOST_GEN_BUFF_PLD_EMPTY_S)
+#define DSI_HOST_GEN_BUFF_PLD_EMPTY_V  0x00000001U
+#define DSI_HOST_GEN_BUFF_PLD_EMPTY_S  18
+/** DSI_HOST_GEN_BUFF_PLD_FULL : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_BUFF_PLD_FULL    (BIT(19))
+#define DSI_HOST_GEN_BUFF_PLD_FULL_M  (DSI_HOST_GEN_BUFF_PLD_FULL_V << DSI_HOST_GEN_BUFF_PLD_FULL_S)
+#define DSI_HOST_GEN_BUFF_PLD_FULL_V  0x00000001U
+#define DSI_HOST_GEN_BUFF_PLD_FULL_S  19
+
+/** DSI_HOST_TO_CNT_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_TO_CNT_CFG_REG (DR_REG_DSI_HOST_BASE + 0x78)
+/** DSI_HOST_LPRX_TO_CNT : R/W; bitpos: [15:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LPRX_TO_CNT    0x0000FFFFU
+#define DSI_HOST_LPRX_TO_CNT_M  (DSI_HOST_LPRX_TO_CNT_V << DSI_HOST_LPRX_TO_CNT_S)
+#define DSI_HOST_LPRX_TO_CNT_V  0x0000FFFFU
+#define DSI_HOST_LPRX_TO_CNT_S  0
+/** DSI_HOST_HSTX_TO_CNT : R/W; bitpos: [31:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_HSTX_TO_CNT    0x0000FFFFU
+#define DSI_HOST_HSTX_TO_CNT_M  (DSI_HOST_HSTX_TO_CNT_V << DSI_HOST_HSTX_TO_CNT_S)
+#define DSI_HOST_HSTX_TO_CNT_V  0x0000FFFFU
+#define DSI_HOST_HSTX_TO_CNT_S  16
+
+/** DSI_HOST_HS_RD_TO_CNT_REG register
+ *  NA
+ */
+#define DSI_HOST_HS_RD_TO_CNT_REG (DR_REG_DSI_HOST_BASE + 0x7c)
+/** DSI_HOST_HS_RD_TO_CNT : R/W; bitpos: [15:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_HS_RD_TO_CNT    0x0000FFFFU
+#define DSI_HOST_HS_RD_TO_CNT_M  (DSI_HOST_HS_RD_TO_CNT_V << DSI_HOST_HS_RD_TO_CNT_S)
+#define DSI_HOST_HS_RD_TO_CNT_V  0x0000FFFFU
+#define DSI_HOST_HS_RD_TO_CNT_S  0
+
+/** DSI_HOST_LP_RD_TO_CNT_REG register
+ *  NA
+ */
+#define DSI_HOST_LP_RD_TO_CNT_REG (DR_REG_DSI_HOST_BASE + 0x80)
+/** DSI_HOST_LP_RD_TO_CNT : R/W; bitpos: [15:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_RD_TO_CNT    0x0000FFFFU
+#define DSI_HOST_LP_RD_TO_CNT_M  (DSI_HOST_LP_RD_TO_CNT_V << DSI_HOST_LP_RD_TO_CNT_S)
+#define DSI_HOST_LP_RD_TO_CNT_V  0x0000FFFFU
+#define DSI_HOST_LP_RD_TO_CNT_S  0
+
+/** DSI_HOST_HS_WR_TO_CNT_REG register
+ *  NA
+ */
+#define DSI_HOST_HS_WR_TO_CNT_REG (DR_REG_DSI_HOST_BASE + 0x84)
+/** DSI_HOST_HS_WR_TO_CNT : R/W; bitpos: [15:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_HS_WR_TO_CNT    0x0000FFFFU
+#define DSI_HOST_HS_WR_TO_CNT_M  (DSI_HOST_HS_WR_TO_CNT_V << DSI_HOST_HS_WR_TO_CNT_S)
+#define DSI_HOST_HS_WR_TO_CNT_V  0x0000FFFFU
+#define DSI_HOST_HS_WR_TO_CNT_S  0
+
+/** DSI_HOST_LP_WR_TO_CNT_REG register
+ *  NA
+ */
+#define DSI_HOST_LP_WR_TO_CNT_REG (DR_REG_DSI_HOST_BASE + 0x88)
+/** DSI_HOST_LP_WR_TO_CNT : R/W; bitpos: [15:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_WR_TO_CNT    0x0000FFFFU
+#define DSI_HOST_LP_WR_TO_CNT_M  (DSI_HOST_LP_WR_TO_CNT_V << DSI_HOST_LP_WR_TO_CNT_S)
+#define DSI_HOST_LP_WR_TO_CNT_V  0x0000FFFFU
+#define DSI_HOST_LP_WR_TO_CNT_S  0
+
+/** DSI_HOST_BTA_TO_CNT_REG register
+ *  NA
+ */
+#define DSI_HOST_BTA_TO_CNT_REG (DR_REG_DSI_HOST_BASE + 0x8c)
+/** DSI_HOST_BTA_TO_CNT : R/W; bitpos: [15:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_BTA_TO_CNT    0x0000FFFFU
+#define DSI_HOST_BTA_TO_CNT_M  (DSI_HOST_BTA_TO_CNT_V << DSI_HOST_BTA_TO_CNT_S)
+#define DSI_HOST_BTA_TO_CNT_V  0x0000FFFFU
+#define DSI_HOST_BTA_TO_CNT_S  0
+
+/** DSI_HOST_SDF_3D_REG register
+ *  NA
+ */
+#define DSI_HOST_SDF_3D_REG (DR_REG_DSI_HOST_BASE + 0x90)
+/** DSI_HOST_MODE_3D : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MODE_3D    0x00000003U
+#define DSI_HOST_MODE_3D_M  (DSI_HOST_MODE_3D_V << DSI_HOST_MODE_3D_S)
+#define DSI_HOST_MODE_3D_V  0x00000003U
+#define DSI_HOST_MODE_3D_S  0
+/** DSI_HOST_FORMAT_3D : R/W; bitpos: [3:2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORMAT_3D    0x00000003U
+#define DSI_HOST_FORMAT_3D_M  (DSI_HOST_FORMAT_3D_V << DSI_HOST_FORMAT_3D_S)
+#define DSI_HOST_FORMAT_3D_V  0x00000003U
+#define DSI_HOST_FORMAT_3D_S  2
+/** DSI_HOST_SECOND_VSYNC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_SECOND_VSYNC    (BIT(4))
+#define DSI_HOST_SECOND_VSYNC_M  (DSI_HOST_SECOND_VSYNC_V << DSI_HOST_SECOND_VSYNC_S)
+#define DSI_HOST_SECOND_VSYNC_V  0x00000001U
+#define DSI_HOST_SECOND_VSYNC_S  4
+/** DSI_HOST_RIGHT_FIRST : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_RIGHT_FIRST    (BIT(5))
+#define DSI_HOST_RIGHT_FIRST_M  (DSI_HOST_RIGHT_FIRST_V << DSI_HOST_RIGHT_FIRST_S)
+#define DSI_HOST_RIGHT_FIRST_V  0x00000001U
+#define DSI_HOST_RIGHT_FIRST_S  5
+/** DSI_HOST_SEND_3D_CFG : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_SEND_3D_CFG    (BIT(16))
+#define DSI_HOST_SEND_3D_CFG_M  (DSI_HOST_SEND_3D_CFG_V << DSI_HOST_SEND_3D_CFG_S)
+#define DSI_HOST_SEND_3D_CFG_V  0x00000001U
+#define DSI_HOST_SEND_3D_CFG_S  16
+
+/** DSI_HOST_LPCLK_CTRL_REG register
+ *  NA
+ */
+#define DSI_HOST_LPCLK_CTRL_REG (DR_REG_DSI_HOST_BASE + 0x94)
+/** DSI_HOST_PHY_TXREQUESTCLKHS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_TXREQUESTCLKHS    (BIT(0))
+#define DSI_HOST_PHY_TXREQUESTCLKHS_M  (DSI_HOST_PHY_TXREQUESTCLKHS_V << DSI_HOST_PHY_TXREQUESTCLKHS_S)
+#define DSI_HOST_PHY_TXREQUESTCLKHS_V  0x00000001U
+#define DSI_HOST_PHY_TXREQUESTCLKHS_S  0
+/** DSI_HOST_AUTO_CLKLANE_CTRL : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_AUTO_CLKLANE_CTRL    (BIT(1))
+#define DSI_HOST_AUTO_CLKLANE_CTRL_M  (DSI_HOST_AUTO_CLKLANE_CTRL_V << DSI_HOST_AUTO_CLKLANE_CTRL_S)
+#define DSI_HOST_AUTO_CLKLANE_CTRL_V  0x00000001U
+#define DSI_HOST_AUTO_CLKLANE_CTRL_S  1
+
+/** DSI_HOST_PHY_TMR_LPCLK_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_TMR_LPCLK_CFG_REG (DR_REG_DSI_HOST_BASE + 0x98)
+/** DSI_HOST_PHY_CLKLP2HS_TIME : R/W; bitpos: [9:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_CLKLP2HS_TIME    0x000003FFU
+#define DSI_HOST_PHY_CLKLP2HS_TIME_M  (DSI_HOST_PHY_CLKLP2HS_TIME_V << DSI_HOST_PHY_CLKLP2HS_TIME_S)
+#define DSI_HOST_PHY_CLKLP2HS_TIME_V  0x000003FFU
+#define DSI_HOST_PHY_CLKLP2HS_TIME_S  0
+/** DSI_HOST_PHY_CLKHS2LP_TIME : R/W; bitpos: [25:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_CLKHS2LP_TIME    0x000003FFU
+#define DSI_HOST_PHY_CLKHS2LP_TIME_M  (DSI_HOST_PHY_CLKHS2LP_TIME_V << DSI_HOST_PHY_CLKHS2LP_TIME_S)
+#define DSI_HOST_PHY_CLKHS2LP_TIME_V  0x000003FFU
+#define DSI_HOST_PHY_CLKHS2LP_TIME_S  16
+
+/** DSI_HOST_PHY_TMR_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_TMR_CFG_REG (DR_REG_DSI_HOST_BASE + 0x9c)
+/** DSI_HOST_PHY_LP2HS_TIME : R/W; bitpos: [9:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_LP2HS_TIME    0x000003FFU
+#define DSI_HOST_PHY_LP2HS_TIME_M  (DSI_HOST_PHY_LP2HS_TIME_V << DSI_HOST_PHY_LP2HS_TIME_S)
+#define DSI_HOST_PHY_LP2HS_TIME_V  0x000003FFU
+#define DSI_HOST_PHY_LP2HS_TIME_S  0
+/** DSI_HOST_PHY_HS2LP_TIME : R/W; bitpos: [25:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_HS2LP_TIME    0x000003FFU
+#define DSI_HOST_PHY_HS2LP_TIME_M  (DSI_HOST_PHY_HS2LP_TIME_V << DSI_HOST_PHY_HS2LP_TIME_S)
+#define DSI_HOST_PHY_HS2LP_TIME_V  0x000003FFU
+#define DSI_HOST_PHY_HS2LP_TIME_S  16
+
+/** DSI_HOST_PHY_RSTZ_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_RSTZ_REG (DR_REG_DSI_HOST_BASE + 0xa0)
+/** DSI_HOST_PHY_SHUTDOWNZ : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_SHUTDOWNZ    (BIT(0))
+#define DSI_HOST_PHY_SHUTDOWNZ_M  (DSI_HOST_PHY_SHUTDOWNZ_V << DSI_HOST_PHY_SHUTDOWNZ_S)
+#define DSI_HOST_PHY_SHUTDOWNZ_V  0x00000001U
+#define DSI_HOST_PHY_SHUTDOWNZ_S  0
+/** DSI_HOST_PHY_RSTZ : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_RSTZ    (BIT(1))
+#define DSI_HOST_PHY_RSTZ_M  (DSI_HOST_PHY_RSTZ_V << DSI_HOST_PHY_RSTZ_S)
+#define DSI_HOST_PHY_RSTZ_V  0x00000001U
+#define DSI_HOST_PHY_RSTZ_S  1
+/** DSI_HOST_PHY_ENABLECLK : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_ENABLECLK    (BIT(2))
+#define DSI_HOST_PHY_ENABLECLK_M  (DSI_HOST_PHY_ENABLECLK_V << DSI_HOST_PHY_ENABLECLK_S)
+#define DSI_HOST_PHY_ENABLECLK_V  0x00000001U
+#define DSI_HOST_PHY_ENABLECLK_S  2
+/** DSI_HOST_PHY_FORCEPLL : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_FORCEPLL    (BIT(3))
+#define DSI_HOST_PHY_FORCEPLL_M  (DSI_HOST_PHY_FORCEPLL_V << DSI_HOST_PHY_FORCEPLL_S)
+#define DSI_HOST_PHY_FORCEPLL_V  0x00000001U
+#define DSI_HOST_PHY_FORCEPLL_S  3
+
+/** DSI_HOST_PHY_IF_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_IF_CFG_REG (DR_REG_DSI_HOST_BASE + 0xa4)
+/** DSI_HOST_N_LANES : R/W; bitpos: [1:0]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_N_LANES    0x00000003U
+#define DSI_HOST_N_LANES_M  (DSI_HOST_N_LANES_V << DSI_HOST_N_LANES_S)
+#define DSI_HOST_N_LANES_V  0x00000003U
+#define DSI_HOST_N_LANES_S  0
+/** DSI_HOST_PHY_STOP_WAIT_TIME : R/W; bitpos: [15:8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_STOP_WAIT_TIME    0x000000FFU
+#define DSI_HOST_PHY_STOP_WAIT_TIME_M  (DSI_HOST_PHY_STOP_WAIT_TIME_V << DSI_HOST_PHY_STOP_WAIT_TIME_S)
+#define DSI_HOST_PHY_STOP_WAIT_TIME_V  0x000000FFU
+#define DSI_HOST_PHY_STOP_WAIT_TIME_S  8
+
+/** DSI_HOST_PHY_ULPS_CTRL_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_ULPS_CTRL_REG (DR_REG_DSI_HOST_BASE + 0xa8)
+/** DSI_HOST_PHY_TXREQULPSCLK : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_TXREQULPSCLK    (BIT(0))
+#define DSI_HOST_PHY_TXREQULPSCLK_M  (DSI_HOST_PHY_TXREQULPSCLK_V << DSI_HOST_PHY_TXREQULPSCLK_S)
+#define DSI_HOST_PHY_TXREQULPSCLK_V  0x00000001U
+#define DSI_HOST_PHY_TXREQULPSCLK_S  0
+/** DSI_HOST_PHY_TXEXITULPSCLK : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_TXEXITULPSCLK    (BIT(1))
+#define DSI_HOST_PHY_TXEXITULPSCLK_M  (DSI_HOST_PHY_TXEXITULPSCLK_V << DSI_HOST_PHY_TXEXITULPSCLK_S)
+#define DSI_HOST_PHY_TXEXITULPSCLK_V  0x00000001U
+#define DSI_HOST_PHY_TXEXITULPSCLK_S  1
+/** DSI_HOST_PHY_TXREQULPSLAN : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_TXREQULPSLAN    (BIT(2))
+#define DSI_HOST_PHY_TXREQULPSLAN_M  (DSI_HOST_PHY_TXREQULPSLAN_V << DSI_HOST_PHY_TXREQULPSLAN_S)
+#define DSI_HOST_PHY_TXREQULPSLAN_V  0x00000001U
+#define DSI_HOST_PHY_TXREQULPSLAN_S  2
+/** DSI_HOST_PHY_TXEXITULPSLAN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_TXEXITULPSLAN    (BIT(3))
+#define DSI_HOST_PHY_TXEXITULPSLAN_M  (DSI_HOST_PHY_TXEXITULPSLAN_V << DSI_HOST_PHY_TXEXITULPSLAN_S)
+#define DSI_HOST_PHY_TXEXITULPSLAN_V  0x00000001U
+#define DSI_HOST_PHY_TXEXITULPSLAN_S  3
+
+/** DSI_HOST_PHY_TX_TRIGGERS_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_TX_TRIGGERS_REG (DR_REG_DSI_HOST_BASE + 0xac)
+/** DSI_HOST_PHY_TX_TRIGGERS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_TX_TRIGGERS    0x0000000FU
+#define DSI_HOST_PHY_TX_TRIGGERS_M  (DSI_HOST_PHY_TX_TRIGGERS_V << DSI_HOST_PHY_TX_TRIGGERS_S)
+#define DSI_HOST_PHY_TX_TRIGGERS_V  0x0000000FU
+#define DSI_HOST_PHY_TX_TRIGGERS_S  0
+
+/** DSI_HOST_PHY_STATUS_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_STATUS_REG (DR_REG_DSI_HOST_BASE + 0xb0)
+/** DSI_HOST_PHY_LOCK : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_LOCK    (BIT(0))
+#define DSI_HOST_PHY_LOCK_M  (DSI_HOST_PHY_LOCK_V << DSI_HOST_PHY_LOCK_S)
+#define DSI_HOST_PHY_LOCK_V  0x00000001U
+#define DSI_HOST_PHY_LOCK_S  0
+/** DSI_HOST_PHY_DIRECTION : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_DIRECTION    (BIT(1))
+#define DSI_HOST_PHY_DIRECTION_M  (DSI_HOST_PHY_DIRECTION_V << DSI_HOST_PHY_DIRECTION_S)
+#define DSI_HOST_PHY_DIRECTION_V  0x00000001U
+#define DSI_HOST_PHY_DIRECTION_S  1
+/** DSI_HOST_PHY_STOPSTATECLKLANE : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_STOPSTATECLKLANE    (BIT(2))
+#define DSI_HOST_PHY_STOPSTATECLKLANE_M  (DSI_HOST_PHY_STOPSTATECLKLANE_V << DSI_HOST_PHY_STOPSTATECLKLANE_S)
+#define DSI_HOST_PHY_STOPSTATECLKLANE_V  0x00000001U
+#define DSI_HOST_PHY_STOPSTATECLKLANE_S  2
+/** DSI_HOST_PHY_ULPSACTIVENOTCLK : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_ULPSACTIVENOTCLK    (BIT(3))
+#define DSI_HOST_PHY_ULPSACTIVENOTCLK_M  (DSI_HOST_PHY_ULPSACTIVENOTCLK_V << DSI_HOST_PHY_ULPSACTIVENOTCLK_S)
+#define DSI_HOST_PHY_ULPSACTIVENOTCLK_V  0x00000001U
+#define DSI_HOST_PHY_ULPSACTIVENOTCLK_S  3
+/** DSI_HOST_PHY_STOPSTATE0LANE : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_STOPSTATE0LANE    (BIT(4))
+#define DSI_HOST_PHY_STOPSTATE0LANE_M  (DSI_HOST_PHY_STOPSTATE0LANE_V << DSI_HOST_PHY_STOPSTATE0LANE_S)
+#define DSI_HOST_PHY_STOPSTATE0LANE_V  0x00000001U
+#define DSI_HOST_PHY_STOPSTATE0LANE_S  4
+/** DSI_HOST_PHY_ULPSACTIVENOT0LANE : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_ULPSACTIVENOT0LANE    (BIT(5))
+#define DSI_HOST_PHY_ULPSACTIVENOT0LANE_M  (DSI_HOST_PHY_ULPSACTIVENOT0LANE_V << DSI_HOST_PHY_ULPSACTIVENOT0LANE_S)
+#define DSI_HOST_PHY_ULPSACTIVENOT0LANE_V  0x00000001U
+#define DSI_HOST_PHY_ULPSACTIVENOT0LANE_S  5
+/** DSI_HOST_PHY_RXULPSESC0LANE : RO; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_PHY_RXULPSESC0LANE    (BIT(6))
+#define DSI_HOST_PHY_RXULPSESC0LANE_M  (DSI_HOST_PHY_RXULPSESC0LANE_V << DSI_HOST_PHY_RXULPSESC0LANE_S)
+#define DSI_HOST_PHY_RXULPSESC0LANE_V  0x00000001U
+#define DSI_HOST_PHY_RXULPSESC0LANE_S  6
+/** DSI_HOST_PHY_STOPSTATE1LANE : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_STOPSTATE1LANE    (BIT(7))
+#define DSI_HOST_PHY_STOPSTATE1LANE_M  (DSI_HOST_PHY_STOPSTATE1LANE_V << DSI_HOST_PHY_STOPSTATE1LANE_S)
+#define DSI_HOST_PHY_STOPSTATE1LANE_V  0x00000001U
+#define DSI_HOST_PHY_STOPSTATE1LANE_S  7
+/** DSI_HOST_PHY_ULPSACTIVENOT1LANE : RO; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_PHY_ULPSACTIVENOT1LANE    (BIT(8))
+#define DSI_HOST_PHY_ULPSACTIVENOT1LANE_M  (DSI_HOST_PHY_ULPSACTIVENOT1LANE_V << DSI_HOST_PHY_ULPSACTIVENOT1LANE_S)
+#define DSI_HOST_PHY_ULPSACTIVENOT1LANE_V  0x00000001U
+#define DSI_HOST_PHY_ULPSACTIVENOT1LANE_S  8
+
+/** DSI_HOST_PHY_TST_CTRL0_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_TST_CTRL0_REG (DR_REG_DSI_HOST_BASE + 0xb4)
+/** DSI_HOST_PHY_TESTCLR : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_PHY_TESTCLR    (BIT(0))
+#define DSI_HOST_PHY_TESTCLR_M  (DSI_HOST_PHY_TESTCLR_V << DSI_HOST_PHY_TESTCLR_S)
+#define DSI_HOST_PHY_TESTCLR_V  0x00000001U
+#define DSI_HOST_PHY_TESTCLR_S  0
+/** DSI_HOST_PHY_TESTCLK : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_TESTCLK    (BIT(1))
+#define DSI_HOST_PHY_TESTCLK_M  (DSI_HOST_PHY_TESTCLK_V << DSI_HOST_PHY_TESTCLK_S)
+#define DSI_HOST_PHY_TESTCLK_V  0x00000001U
+#define DSI_HOST_PHY_TESTCLK_S  1
+
+/** DSI_HOST_PHY_TST_CTRL1_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_TST_CTRL1_REG (DR_REG_DSI_HOST_BASE + 0xb8)
+/** DSI_HOST_PHY_TESTDIN : R/W; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_TESTDIN    0x000000FFU
+#define DSI_HOST_PHY_TESTDIN_M  (DSI_HOST_PHY_TESTDIN_V << DSI_HOST_PHY_TESTDIN_S)
+#define DSI_HOST_PHY_TESTDIN_V  0x000000FFU
+#define DSI_HOST_PHY_TESTDIN_S  0
+/** DSI_HOST_PHT_TESTDOUT : RO; bitpos: [15:8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHT_TESTDOUT    0x000000FFU
+#define DSI_HOST_PHT_TESTDOUT_M  (DSI_HOST_PHT_TESTDOUT_V << DSI_HOST_PHT_TESTDOUT_S)
+#define DSI_HOST_PHT_TESTDOUT_V  0x000000FFU
+#define DSI_HOST_PHT_TESTDOUT_S  8
+/** DSI_HOST_PHY_TESTEN : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PHY_TESTEN    (BIT(16))
+#define DSI_HOST_PHY_TESTEN_M  (DSI_HOST_PHY_TESTEN_V << DSI_HOST_PHY_TESTEN_S)
+#define DSI_HOST_PHY_TESTEN_V  0x00000001U
+#define DSI_HOST_PHY_TESTEN_S  16
+
+/** DSI_HOST_INT_ST0_REG register
+ *  NA
+ */
+#define DSI_HOST_INT_ST0_REG (DR_REG_DSI_HOST_BASE + 0xbc)
+/** DSI_HOST_ACK_WITH_ERR_0 : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_0    (BIT(0))
+#define DSI_HOST_ACK_WITH_ERR_0_M  (DSI_HOST_ACK_WITH_ERR_0_V << DSI_HOST_ACK_WITH_ERR_0_S)
+#define DSI_HOST_ACK_WITH_ERR_0_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_0_S  0
+/** DSI_HOST_ACK_WITH_ERR_1 : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_1    (BIT(1))
+#define DSI_HOST_ACK_WITH_ERR_1_M  (DSI_HOST_ACK_WITH_ERR_1_V << DSI_HOST_ACK_WITH_ERR_1_S)
+#define DSI_HOST_ACK_WITH_ERR_1_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_1_S  1
+/** DSI_HOST_ACK_WITH_ERR_2 : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_2    (BIT(2))
+#define DSI_HOST_ACK_WITH_ERR_2_M  (DSI_HOST_ACK_WITH_ERR_2_V << DSI_HOST_ACK_WITH_ERR_2_S)
+#define DSI_HOST_ACK_WITH_ERR_2_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_2_S  2
+/** DSI_HOST_ACK_WITH_ERR_3 : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_3    (BIT(3))
+#define DSI_HOST_ACK_WITH_ERR_3_M  (DSI_HOST_ACK_WITH_ERR_3_V << DSI_HOST_ACK_WITH_ERR_3_S)
+#define DSI_HOST_ACK_WITH_ERR_3_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_3_S  3
+/** DSI_HOST_ACK_WITH_ERR_4 : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_4    (BIT(4))
+#define DSI_HOST_ACK_WITH_ERR_4_M  (DSI_HOST_ACK_WITH_ERR_4_V << DSI_HOST_ACK_WITH_ERR_4_S)
+#define DSI_HOST_ACK_WITH_ERR_4_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_4_S  4
+/** DSI_HOST_ACK_WITH_ERR_5 : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_5    (BIT(5))
+#define DSI_HOST_ACK_WITH_ERR_5_M  (DSI_HOST_ACK_WITH_ERR_5_V << DSI_HOST_ACK_WITH_ERR_5_S)
+#define DSI_HOST_ACK_WITH_ERR_5_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_5_S  5
+/** DSI_HOST_ACK_WITH_ERR_6 : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_6    (BIT(6))
+#define DSI_HOST_ACK_WITH_ERR_6_M  (DSI_HOST_ACK_WITH_ERR_6_V << DSI_HOST_ACK_WITH_ERR_6_S)
+#define DSI_HOST_ACK_WITH_ERR_6_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_6_S  6
+/** DSI_HOST_ACK_WITH_ERR_7 : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_7    (BIT(7))
+#define DSI_HOST_ACK_WITH_ERR_7_M  (DSI_HOST_ACK_WITH_ERR_7_V << DSI_HOST_ACK_WITH_ERR_7_S)
+#define DSI_HOST_ACK_WITH_ERR_7_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_7_S  7
+/** DSI_HOST_ACK_WITH_ERR_8 : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_8    (BIT(8))
+#define DSI_HOST_ACK_WITH_ERR_8_M  (DSI_HOST_ACK_WITH_ERR_8_V << DSI_HOST_ACK_WITH_ERR_8_S)
+#define DSI_HOST_ACK_WITH_ERR_8_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_8_S  8
+/** DSI_HOST_ACK_WITH_ERR_9 : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_9    (BIT(9))
+#define DSI_HOST_ACK_WITH_ERR_9_M  (DSI_HOST_ACK_WITH_ERR_9_V << DSI_HOST_ACK_WITH_ERR_9_S)
+#define DSI_HOST_ACK_WITH_ERR_9_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_9_S  9
+/** DSI_HOST_ACK_WITH_ERR_10 : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_10    (BIT(10))
+#define DSI_HOST_ACK_WITH_ERR_10_M  (DSI_HOST_ACK_WITH_ERR_10_V << DSI_HOST_ACK_WITH_ERR_10_S)
+#define DSI_HOST_ACK_WITH_ERR_10_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_10_S  10
+/** DSI_HOST_ACK_WITH_ERR_11 : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_11    (BIT(11))
+#define DSI_HOST_ACK_WITH_ERR_11_M  (DSI_HOST_ACK_WITH_ERR_11_V << DSI_HOST_ACK_WITH_ERR_11_S)
+#define DSI_HOST_ACK_WITH_ERR_11_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_11_S  11
+/** DSI_HOST_ACK_WITH_ERR_12 : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_12    (BIT(12))
+#define DSI_HOST_ACK_WITH_ERR_12_M  (DSI_HOST_ACK_WITH_ERR_12_V << DSI_HOST_ACK_WITH_ERR_12_S)
+#define DSI_HOST_ACK_WITH_ERR_12_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_12_S  12
+/** DSI_HOST_ACK_WITH_ERR_13 : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_13    (BIT(13))
+#define DSI_HOST_ACK_WITH_ERR_13_M  (DSI_HOST_ACK_WITH_ERR_13_V << DSI_HOST_ACK_WITH_ERR_13_S)
+#define DSI_HOST_ACK_WITH_ERR_13_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_13_S  13
+/** DSI_HOST_ACK_WITH_ERR_14 : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_14    (BIT(14))
+#define DSI_HOST_ACK_WITH_ERR_14_M  (DSI_HOST_ACK_WITH_ERR_14_V << DSI_HOST_ACK_WITH_ERR_14_S)
+#define DSI_HOST_ACK_WITH_ERR_14_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_14_S  14
+/** DSI_HOST_ACK_WITH_ERR_15 : RO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ACK_WITH_ERR_15    (BIT(15))
+#define DSI_HOST_ACK_WITH_ERR_15_M  (DSI_HOST_ACK_WITH_ERR_15_V << DSI_HOST_ACK_WITH_ERR_15_S)
+#define DSI_HOST_ACK_WITH_ERR_15_V  0x00000001U
+#define DSI_HOST_ACK_WITH_ERR_15_S  15
+/** DSI_HOST_DPHY_ERRORS_0 : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPHY_ERRORS_0    (BIT(16))
+#define DSI_HOST_DPHY_ERRORS_0_M  (DSI_HOST_DPHY_ERRORS_0_V << DSI_HOST_DPHY_ERRORS_0_S)
+#define DSI_HOST_DPHY_ERRORS_0_V  0x00000001U
+#define DSI_HOST_DPHY_ERRORS_0_S  16
+/** DSI_HOST_DPHY_ERRORS_1 : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPHY_ERRORS_1    (BIT(17))
+#define DSI_HOST_DPHY_ERRORS_1_M  (DSI_HOST_DPHY_ERRORS_1_V << DSI_HOST_DPHY_ERRORS_1_S)
+#define DSI_HOST_DPHY_ERRORS_1_V  0x00000001U
+#define DSI_HOST_DPHY_ERRORS_1_S  17
+/** DSI_HOST_DPHY_ERRORS_2 : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPHY_ERRORS_2    (BIT(18))
+#define DSI_HOST_DPHY_ERRORS_2_M  (DSI_HOST_DPHY_ERRORS_2_V << DSI_HOST_DPHY_ERRORS_2_S)
+#define DSI_HOST_DPHY_ERRORS_2_V  0x00000001U
+#define DSI_HOST_DPHY_ERRORS_2_S  18
+/** DSI_HOST_DPHY_ERRORS_3 : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPHY_ERRORS_3    (BIT(19))
+#define DSI_HOST_DPHY_ERRORS_3_M  (DSI_HOST_DPHY_ERRORS_3_V << DSI_HOST_DPHY_ERRORS_3_S)
+#define DSI_HOST_DPHY_ERRORS_3_V  0x00000001U
+#define DSI_HOST_DPHY_ERRORS_3_S  19
+/** DSI_HOST_DPHY_ERRORS_4 : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPHY_ERRORS_4    (BIT(20))
+#define DSI_HOST_DPHY_ERRORS_4_M  (DSI_HOST_DPHY_ERRORS_4_V << DSI_HOST_DPHY_ERRORS_4_S)
+#define DSI_HOST_DPHY_ERRORS_4_V  0x00000001U
+#define DSI_HOST_DPHY_ERRORS_4_S  20
+
+/** DSI_HOST_INT_ST1_REG register
+ *  NA
+ */
+#define DSI_HOST_INT_ST1_REG (DR_REG_DSI_HOST_BASE + 0xc0)
+/** DSI_HOST_TO_HS_TX : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_TO_HS_TX    (BIT(0))
+#define DSI_HOST_TO_HS_TX_M  (DSI_HOST_TO_HS_TX_V << DSI_HOST_TO_HS_TX_S)
+#define DSI_HOST_TO_HS_TX_V  0x00000001U
+#define DSI_HOST_TO_HS_TX_S  0
+/** DSI_HOST_TO_LP_RX : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_TO_LP_RX    (BIT(1))
+#define DSI_HOST_TO_LP_RX_M  (DSI_HOST_TO_LP_RX_V << DSI_HOST_TO_LP_RX_S)
+#define DSI_HOST_TO_LP_RX_V  0x00000001U
+#define DSI_HOST_TO_LP_RX_S  1
+/** DSI_HOST_ECC_SINGLE_ERR : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ECC_SINGLE_ERR    (BIT(2))
+#define DSI_HOST_ECC_SINGLE_ERR_M  (DSI_HOST_ECC_SINGLE_ERR_V << DSI_HOST_ECC_SINGLE_ERR_S)
+#define DSI_HOST_ECC_SINGLE_ERR_V  0x00000001U
+#define DSI_HOST_ECC_SINGLE_ERR_S  2
+/** DSI_HOST_ECC_MILTI_ERR : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_ECC_MILTI_ERR    (BIT(3))
+#define DSI_HOST_ECC_MILTI_ERR_M  (DSI_HOST_ECC_MILTI_ERR_V << DSI_HOST_ECC_MILTI_ERR_S)
+#define DSI_HOST_ECC_MILTI_ERR_V  0x00000001U
+#define DSI_HOST_ECC_MILTI_ERR_S  3
+/** DSI_HOST_CRC_ERR : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_CRC_ERR    (BIT(4))
+#define DSI_HOST_CRC_ERR_M  (DSI_HOST_CRC_ERR_V << DSI_HOST_CRC_ERR_S)
+#define DSI_HOST_CRC_ERR_V  0x00000001U
+#define DSI_HOST_CRC_ERR_S  4
+/** DSI_HOST_PKT_SIZE_ERR : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PKT_SIZE_ERR    (BIT(5))
+#define DSI_HOST_PKT_SIZE_ERR_M  (DSI_HOST_PKT_SIZE_ERR_V << DSI_HOST_PKT_SIZE_ERR_S)
+#define DSI_HOST_PKT_SIZE_ERR_V  0x00000001U
+#define DSI_HOST_PKT_SIZE_ERR_S  5
+/** DSI_HOST_EOPT_ERR : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_EOPT_ERR    (BIT(6))
+#define DSI_HOST_EOPT_ERR_M  (DSI_HOST_EOPT_ERR_V << DSI_HOST_EOPT_ERR_S)
+#define DSI_HOST_EOPT_ERR_V  0x00000001U
+#define DSI_HOST_EOPT_ERR_S  6
+/** DSI_HOST_DPI_PLD_WR_ERR : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPI_PLD_WR_ERR    (BIT(7))
+#define DSI_HOST_DPI_PLD_WR_ERR_M  (DSI_HOST_DPI_PLD_WR_ERR_V << DSI_HOST_DPI_PLD_WR_ERR_S)
+#define DSI_HOST_DPI_PLD_WR_ERR_V  0x00000001U
+#define DSI_HOST_DPI_PLD_WR_ERR_S  7
+/** DSI_HOST_GEN_CMD_WR_ERR : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_CMD_WR_ERR    (BIT(8))
+#define DSI_HOST_GEN_CMD_WR_ERR_M  (DSI_HOST_GEN_CMD_WR_ERR_V << DSI_HOST_GEN_CMD_WR_ERR_S)
+#define DSI_HOST_GEN_CMD_WR_ERR_V  0x00000001U
+#define DSI_HOST_GEN_CMD_WR_ERR_S  8
+/** DSI_HOST_GEN_PLD_WR_ERR : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_WR_ERR    (BIT(9))
+#define DSI_HOST_GEN_PLD_WR_ERR_M  (DSI_HOST_GEN_PLD_WR_ERR_V << DSI_HOST_GEN_PLD_WR_ERR_S)
+#define DSI_HOST_GEN_PLD_WR_ERR_V  0x00000001U
+#define DSI_HOST_GEN_PLD_WR_ERR_S  9
+/** DSI_HOST_GEN_PLD_SEND_ERR : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_SEND_ERR    (BIT(10))
+#define DSI_HOST_GEN_PLD_SEND_ERR_M  (DSI_HOST_GEN_PLD_SEND_ERR_V << DSI_HOST_GEN_PLD_SEND_ERR_S)
+#define DSI_HOST_GEN_PLD_SEND_ERR_V  0x00000001U
+#define DSI_HOST_GEN_PLD_SEND_ERR_S  10
+/** DSI_HOST_GEN_PLD_RD_ERR : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_RD_ERR    (BIT(11))
+#define DSI_HOST_GEN_PLD_RD_ERR_M  (DSI_HOST_GEN_PLD_RD_ERR_V << DSI_HOST_GEN_PLD_RD_ERR_S)
+#define DSI_HOST_GEN_PLD_RD_ERR_V  0x00000001U
+#define DSI_HOST_GEN_PLD_RD_ERR_S  11
+/** DSI_HOST_GEN_PLD_RECEV_ERR : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_GEN_PLD_RECEV_ERR    (BIT(12))
+#define DSI_HOST_GEN_PLD_RECEV_ERR_M  (DSI_HOST_GEN_PLD_RECEV_ERR_V << DSI_HOST_GEN_PLD_RECEV_ERR_S)
+#define DSI_HOST_GEN_PLD_RECEV_ERR_V  0x00000001U
+#define DSI_HOST_GEN_PLD_RECEV_ERR_S  12
+/** DSI_HOST_DPI_BUFF_PLD_UNDER : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPI_BUFF_PLD_UNDER    (BIT(19))
+#define DSI_HOST_DPI_BUFF_PLD_UNDER_M  (DSI_HOST_DPI_BUFF_PLD_UNDER_V << DSI_HOST_DPI_BUFF_PLD_UNDER_S)
+#define DSI_HOST_DPI_BUFF_PLD_UNDER_V  0x00000001U
+#define DSI_HOST_DPI_BUFF_PLD_UNDER_S  19
+
+/** DSI_HOST_INT_MSK0_REG register
+ *  NA
+ */
+#define DSI_HOST_INT_MSK0_REG (DR_REG_DSI_HOST_BASE + 0xc4)
+/** DSI_HOST_MASK_ACK_WITH_ERR_0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_0    (BIT(0))
+#define DSI_HOST_MASK_ACK_WITH_ERR_0_M  (DSI_HOST_MASK_ACK_WITH_ERR_0_V << DSI_HOST_MASK_ACK_WITH_ERR_0_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_0_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_0_S  0
+/** DSI_HOST_MASK_ACK_WITH_ERR_1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_1    (BIT(1))
+#define DSI_HOST_MASK_ACK_WITH_ERR_1_M  (DSI_HOST_MASK_ACK_WITH_ERR_1_V << DSI_HOST_MASK_ACK_WITH_ERR_1_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_1_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_1_S  1
+/** DSI_HOST_MASK_ACK_WITH_ERR_2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_2    (BIT(2))
+#define DSI_HOST_MASK_ACK_WITH_ERR_2_M  (DSI_HOST_MASK_ACK_WITH_ERR_2_V << DSI_HOST_MASK_ACK_WITH_ERR_2_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_2_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_2_S  2
+/** DSI_HOST_MASK_ACK_WITH_ERR_3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_3    (BIT(3))
+#define DSI_HOST_MASK_ACK_WITH_ERR_3_M  (DSI_HOST_MASK_ACK_WITH_ERR_3_V << DSI_HOST_MASK_ACK_WITH_ERR_3_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_3_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_3_S  3
+/** DSI_HOST_MASK_ACK_WITH_ERR_4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_4    (BIT(4))
+#define DSI_HOST_MASK_ACK_WITH_ERR_4_M  (DSI_HOST_MASK_ACK_WITH_ERR_4_V << DSI_HOST_MASK_ACK_WITH_ERR_4_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_4_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_4_S  4
+/** DSI_HOST_MASK_ACK_WITH_ERR_5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_5    (BIT(5))
+#define DSI_HOST_MASK_ACK_WITH_ERR_5_M  (DSI_HOST_MASK_ACK_WITH_ERR_5_V << DSI_HOST_MASK_ACK_WITH_ERR_5_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_5_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_5_S  5
+/** DSI_HOST_MASK_ACK_WITH_ERR_6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_6    (BIT(6))
+#define DSI_HOST_MASK_ACK_WITH_ERR_6_M  (DSI_HOST_MASK_ACK_WITH_ERR_6_V << DSI_HOST_MASK_ACK_WITH_ERR_6_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_6_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_6_S  6
+/** DSI_HOST_MASK_ACK_WITH_ERR_7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_7    (BIT(7))
+#define DSI_HOST_MASK_ACK_WITH_ERR_7_M  (DSI_HOST_MASK_ACK_WITH_ERR_7_V << DSI_HOST_MASK_ACK_WITH_ERR_7_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_7_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_7_S  7
+/** DSI_HOST_MASK_ACK_WITH_ERR_8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_8    (BIT(8))
+#define DSI_HOST_MASK_ACK_WITH_ERR_8_M  (DSI_HOST_MASK_ACK_WITH_ERR_8_V << DSI_HOST_MASK_ACK_WITH_ERR_8_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_8_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_8_S  8
+/** DSI_HOST_MASK_ACK_WITH_ERR_9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_9    (BIT(9))
+#define DSI_HOST_MASK_ACK_WITH_ERR_9_M  (DSI_HOST_MASK_ACK_WITH_ERR_9_V << DSI_HOST_MASK_ACK_WITH_ERR_9_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_9_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_9_S  9
+/** DSI_HOST_MASK_ACK_WITH_ERR_10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_10    (BIT(10))
+#define DSI_HOST_MASK_ACK_WITH_ERR_10_M  (DSI_HOST_MASK_ACK_WITH_ERR_10_V << DSI_HOST_MASK_ACK_WITH_ERR_10_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_10_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_10_S  10
+/** DSI_HOST_MASK_ACK_WITH_ERR_11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_11    (BIT(11))
+#define DSI_HOST_MASK_ACK_WITH_ERR_11_M  (DSI_HOST_MASK_ACK_WITH_ERR_11_V << DSI_HOST_MASK_ACK_WITH_ERR_11_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_11_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_11_S  11
+/** DSI_HOST_MASK_ACK_WITH_ERR_12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_12    (BIT(12))
+#define DSI_HOST_MASK_ACK_WITH_ERR_12_M  (DSI_HOST_MASK_ACK_WITH_ERR_12_V << DSI_HOST_MASK_ACK_WITH_ERR_12_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_12_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_12_S  12
+/** DSI_HOST_MASK_ACK_WITH_ERR_13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_13    (BIT(13))
+#define DSI_HOST_MASK_ACK_WITH_ERR_13_M  (DSI_HOST_MASK_ACK_WITH_ERR_13_V << DSI_HOST_MASK_ACK_WITH_ERR_13_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_13_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_13_S  13
+/** DSI_HOST_MASK_ACK_WITH_ERR_14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_14    (BIT(14))
+#define DSI_HOST_MASK_ACK_WITH_ERR_14_M  (DSI_HOST_MASK_ACK_WITH_ERR_14_V << DSI_HOST_MASK_ACK_WITH_ERR_14_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_14_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_14_S  14
+/** DSI_HOST_MASK_ACK_WITH_ERR_15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ACK_WITH_ERR_15    (BIT(15))
+#define DSI_HOST_MASK_ACK_WITH_ERR_15_M  (DSI_HOST_MASK_ACK_WITH_ERR_15_V << DSI_HOST_MASK_ACK_WITH_ERR_15_S)
+#define DSI_HOST_MASK_ACK_WITH_ERR_15_V  0x00000001U
+#define DSI_HOST_MASK_ACK_WITH_ERR_15_S  15
+/** DSI_HOST_MASK_DPHY_ERRORS_0 : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_DPHY_ERRORS_0    (BIT(16))
+#define DSI_HOST_MASK_DPHY_ERRORS_0_M  (DSI_HOST_MASK_DPHY_ERRORS_0_V << DSI_HOST_MASK_DPHY_ERRORS_0_S)
+#define DSI_HOST_MASK_DPHY_ERRORS_0_V  0x00000001U
+#define DSI_HOST_MASK_DPHY_ERRORS_0_S  16
+/** DSI_HOST_MASK_DPHY_ERRORS_1 : R/W; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_DPHY_ERRORS_1    (BIT(17))
+#define DSI_HOST_MASK_DPHY_ERRORS_1_M  (DSI_HOST_MASK_DPHY_ERRORS_1_V << DSI_HOST_MASK_DPHY_ERRORS_1_S)
+#define DSI_HOST_MASK_DPHY_ERRORS_1_V  0x00000001U
+#define DSI_HOST_MASK_DPHY_ERRORS_1_S  17
+/** DSI_HOST_MASK_DPHY_ERRORS_2 : R/W; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_DPHY_ERRORS_2    (BIT(18))
+#define DSI_HOST_MASK_DPHY_ERRORS_2_M  (DSI_HOST_MASK_DPHY_ERRORS_2_V << DSI_HOST_MASK_DPHY_ERRORS_2_S)
+#define DSI_HOST_MASK_DPHY_ERRORS_2_V  0x00000001U
+#define DSI_HOST_MASK_DPHY_ERRORS_2_S  18
+/** DSI_HOST_MASK_DPHY_ERRORS_3 : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_DPHY_ERRORS_3    (BIT(19))
+#define DSI_HOST_MASK_DPHY_ERRORS_3_M  (DSI_HOST_MASK_DPHY_ERRORS_3_V << DSI_HOST_MASK_DPHY_ERRORS_3_S)
+#define DSI_HOST_MASK_DPHY_ERRORS_3_V  0x00000001U
+#define DSI_HOST_MASK_DPHY_ERRORS_3_S  19
+/** DSI_HOST_MASK_DPHY_ERRORS_4 : R/W; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_DPHY_ERRORS_4    (BIT(20))
+#define DSI_HOST_MASK_DPHY_ERRORS_4_M  (DSI_HOST_MASK_DPHY_ERRORS_4_V << DSI_HOST_MASK_DPHY_ERRORS_4_S)
+#define DSI_HOST_MASK_DPHY_ERRORS_4_V  0x00000001U
+#define DSI_HOST_MASK_DPHY_ERRORS_4_S  20
+
+/** DSI_HOST_INT_MSK1_REG register
+ *  NA
+ */
+#define DSI_HOST_INT_MSK1_REG (DR_REG_DSI_HOST_BASE + 0xc8)
+/** DSI_HOST_MASK_TO_HS_TX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_TO_HS_TX    (BIT(0))
+#define DSI_HOST_MASK_TO_HS_TX_M  (DSI_HOST_MASK_TO_HS_TX_V << DSI_HOST_MASK_TO_HS_TX_S)
+#define DSI_HOST_MASK_TO_HS_TX_V  0x00000001U
+#define DSI_HOST_MASK_TO_HS_TX_S  0
+/** DSI_HOST_MASK_TO_LP_RX : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_TO_LP_RX    (BIT(1))
+#define DSI_HOST_MASK_TO_LP_RX_M  (DSI_HOST_MASK_TO_LP_RX_V << DSI_HOST_MASK_TO_LP_RX_S)
+#define DSI_HOST_MASK_TO_LP_RX_V  0x00000001U
+#define DSI_HOST_MASK_TO_LP_RX_S  1
+/** DSI_HOST_MASK_ECC_SINGLE_ERR : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ECC_SINGLE_ERR    (BIT(2))
+#define DSI_HOST_MASK_ECC_SINGLE_ERR_M  (DSI_HOST_MASK_ECC_SINGLE_ERR_V << DSI_HOST_MASK_ECC_SINGLE_ERR_S)
+#define DSI_HOST_MASK_ECC_SINGLE_ERR_V  0x00000001U
+#define DSI_HOST_MASK_ECC_SINGLE_ERR_S  2
+/** DSI_HOST_MASK_ECC_MILTI_ERR : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_ECC_MILTI_ERR    (BIT(3))
+#define DSI_HOST_MASK_ECC_MILTI_ERR_M  (DSI_HOST_MASK_ECC_MILTI_ERR_V << DSI_HOST_MASK_ECC_MILTI_ERR_S)
+#define DSI_HOST_MASK_ECC_MILTI_ERR_V  0x00000001U
+#define DSI_HOST_MASK_ECC_MILTI_ERR_S  3
+/** DSI_HOST_MASK_CRC_ERR : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_CRC_ERR    (BIT(4))
+#define DSI_HOST_MASK_CRC_ERR_M  (DSI_HOST_MASK_CRC_ERR_V << DSI_HOST_MASK_CRC_ERR_S)
+#define DSI_HOST_MASK_CRC_ERR_V  0x00000001U
+#define DSI_HOST_MASK_CRC_ERR_S  4
+/** DSI_HOST_MASK_PKT_SIZE_ERR : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_PKT_SIZE_ERR    (BIT(5))
+#define DSI_HOST_MASK_PKT_SIZE_ERR_M  (DSI_HOST_MASK_PKT_SIZE_ERR_V << DSI_HOST_MASK_PKT_SIZE_ERR_S)
+#define DSI_HOST_MASK_PKT_SIZE_ERR_V  0x00000001U
+#define DSI_HOST_MASK_PKT_SIZE_ERR_S  5
+/** DSI_HOST_MASK_EOPT_ERR : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_EOPT_ERR    (BIT(6))
+#define DSI_HOST_MASK_EOPT_ERR_M  (DSI_HOST_MASK_EOPT_ERR_V << DSI_HOST_MASK_EOPT_ERR_S)
+#define DSI_HOST_MASK_EOPT_ERR_V  0x00000001U
+#define DSI_HOST_MASK_EOPT_ERR_S  6
+/** DSI_HOST_MASK_DPI_PLD_WR_ERR : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_DPI_PLD_WR_ERR    (BIT(7))
+#define DSI_HOST_MASK_DPI_PLD_WR_ERR_M  (DSI_HOST_MASK_DPI_PLD_WR_ERR_V << DSI_HOST_MASK_DPI_PLD_WR_ERR_S)
+#define DSI_HOST_MASK_DPI_PLD_WR_ERR_V  0x00000001U
+#define DSI_HOST_MASK_DPI_PLD_WR_ERR_S  7
+/** DSI_HOST_MASK_GEN_CMD_WR_ERR : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_GEN_CMD_WR_ERR    (BIT(8))
+#define DSI_HOST_MASK_GEN_CMD_WR_ERR_M  (DSI_HOST_MASK_GEN_CMD_WR_ERR_V << DSI_HOST_MASK_GEN_CMD_WR_ERR_S)
+#define DSI_HOST_MASK_GEN_CMD_WR_ERR_V  0x00000001U
+#define DSI_HOST_MASK_GEN_CMD_WR_ERR_S  8
+/** DSI_HOST_MASK_GEN_PLD_WR_ERR : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_GEN_PLD_WR_ERR    (BIT(9))
+#define DSI_HOST_MASK_GEN_PLD_WR_ERR_M  (DSI_HOST_MASK_GEN_PLD_WR_ERR_V << DSI_HOST_MASK_GEN_PLD_WR_ERR_S)
+#define DSI_HOST_MASK_GEN_PLD_WR_ERR_V  0x00000001U
+#define DSI_HOST_MASK_GEN_PLD_WR_ERR_S  9
+/** DSI_HOST_MASK_GEN_PLD_SEND_ERR : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_GEN_PLD_SEND_ERR    (BIT(10))
+#define DSI_HOST_MASK_GEN_PLD_SEND_ERR_M  (DSI_HOST_MASK_GEN_PLD_SEND_ERR_V << DSI_HOST_MASK_GEN_PLD_SEND_ERR_S)
+#define DSI_HOST_MASK_GEN_PLD_SEND_ERR_V  0x00000001U
+#define DSI_HOST_MASK_GEN_PLD_SEND_ERR_S  10
+/** DSI_HOST_MASK_GEN_PLD_RD_ERR : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_GEN_PLD_RD_ERR    (BIT(11))
+#define DSI_HOST_MASK_GEN_PLD_RD_ERR_M  (DSI_HOST_MASK_GEN_PLD_RD_ERR_V << DSI_HOST_MASK_GEN_PLD_RD_ERR_S)
+#define DSI_HOST_MASK_GEN_PLD_RD_ERR_V  0x00000001U
+#define DSI_HOST_MASK_GEN_PLD_RD_ERR_S  11
+/** DSI_HOST_MASK_GEN_PLD_RECEV_ERR : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_GEN_PLD_RECEV_ERR    (BIT(12))
+#define DSI_HOST_MASK_GEN_PLD_RECEV_ERR_M  (DSI_HOST_MASK_GEN_PLD_RECEV_ERR_V << DSI_HOST_MASK_GEN_PLD_RECEV_ERR_S)
+#define DSI_HOST_MASK_GEN_PLD_RECEV_ERR_V  0x00000001U
+#define DSI_HOST_MASK_GEN_PLD_RECEV_ERR_S  12
+/** DSI_HOST_MASK_DPI_BUFF_PLD_UNDER : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MASK_DPI_BUFF_PLD_UNDER    (BIT(19))
+#define DSI_HOST_MASK_DPI_BUFF_PLD_UNDER_M  (DSI_HOST_MASK_DPI_BUFF_PLD_UNDER_V << DSI_HOST_MASK_DPI_BUFF_PLD_UNDER_S)
+#define DSI_HOST_MASK_DPI_BUFF_PLD_UNDER_V  0x00000001U
+#define DSI_HOST_MASK_DPI_BUFF_PLD_UNDER_S  19
+
+/** DSI_HOST_PHY_CAL_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_CAL_REG (DR_REG_DSI_HOST_BASE + 0xcc)
+/** DSI_HOST_TXSKEWCALHS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_TXSKEWCALHS    (BIT(0))
+#define DSI_HOST_TXSKEWCALHS_M  (DSI_HOST_TXSKEWCALHS_V << DSI_HOST_TXSKEWCALHS_S)
+#define DSI_HOST_TXSKEWCALHS_V  0x00000001U
+#define DSI_HOST_TXSKEWCALHS_S  0
+
+/** DSI_HOST_INT_FORCE0_REG register
+ *  NA
+ */
+#define DSI_HOST_INT_FORCE0_REG (DR_REG_DSI_HOST_BASE + 0xd8)
+/** DSI_HOST_FORCE_ACK_WITH_ERR_0 : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_0    (BIT(0))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_0_M  (DSI_HOST_FORCE_ACK_WITH_ERR_0_V << DSI_HOST_FORCE_ACK_WITH_ERR_0_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_0_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_0_S  0
+/** DSI_HOST_FORCE_ACK_WITH_ERR_1 : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_1    (BIT(1))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_1_M  (DSI_HOST_FORCE_ACK_WITH_ERR_1_V << DSI_HOST_FORCE_ACK_WITH_ERR_1_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_1_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_1_S  1
+/** DSI_HOST_FORCE_ACK_WITH_ERR_2 : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_2    (BIT(2))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_2_M  (DSI_HOST_FORCE_ACK_WITH_ERR_2_V << DSI_HOST_FORCE_ACK_WITH_ERR_2_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_2_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_2_S  2
+/** DSI_HOST_FORCE_ACK_WITH_ERR_3 : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_3    (BIT(3))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_3_M  (DSI_HOST_FORCE_ACK_WITH_ERR_3_V << DSI_HOST_FORCE_ACK_WITH_ERR_3_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_3_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_3_S  3
+/** DSI_HOST_FORCE_ACK_WITH_ERR_4 : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_4    (BIT(4))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_4_M  (DSI_HOST_FORCE_ACK_WITH_ERR_4_V << DSI_HOST_FORCE_ACK_WITH_ERR_4_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_4_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_4_S  4
+/** DSI_HOST_FORCE_ACK_WITH_ERR_5 : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_5    (BIT(5))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_5_M  (DSI_HOST_FORCE_ACK_WITH_ERR_5_V << DSI_HOST_FORCE_ACK_WITH_ERR_5_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_5_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_5_S  5
+/** DSI_HOST_FORCE_ACK_WITH_ERR_6 : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_6    (BIT(6))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_6_M  (DSI_HOST_FORCE_ACK_WITH_ERR_6_V << DSI_HOST_FORCE_ACK_WITH_ERR_6_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_6_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_6_S  6
+/** DSI_HOST_FORCE_ACK_WITH_ERR_7 : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_7    (BIT(7))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_7_M  (DSI_HOST_FORCE_ACK_WITH_ERR_7_V << DSI_HOST_FORCE_ACK_WITH_ERR_7_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_7_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_7_S  7
+/** DSI_HOST_FORCE_ACK_WITH_ERR_8 : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_8    (BIT(8))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_8_M  (DSI_HOST_FORCE_ACK_WITH_ERR_8_V << DSI_HOST_FORCE_ACK_WITH_ERR_8_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_8_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_8_S  8
+/** DSI_HOST_FORCE_ACK_WITH_ERR_9 : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_9    (BIT(9))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_9_M  (DSI_HOST_FORCE_ACK_WITH_ERR_9_V << DSI_HOST_FORCE_ACK_WITH_ERR_9_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_9_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_9_S  9
+/** DSI_HOST_FORCE_ACK_WITH_ERR_10 : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_10    (BIT(10))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_10_M  (DSI_HOST_FORCE_ACK_WITH_ERR_10_V << DSI_HOST_FORCE_ACK_WITH_ERR_10_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_10_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_10_S  10
+/** DSI_HOST_FORCE_ACK_WITH_ERR_11 : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_11    (BIT(11))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_11_M  (DSI_HOST_FORCE_ACK_WITH_ERR_11_V << DSI_HOST_FORCE_ACK_WITH_ERR_11_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_11_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_11_S  11
+/** DSI_HOST_FORCE_ACK_WITH_ERR_12 : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_12    (BIT(12))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_12_M  (DSI_HOST_FORCE_ACK_WITH_ERR_12_V << DSI_HOST_FORCE_ACK_WITH_ERR_12_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_12_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_12_S  12
+/** DSI_HOST_FORCE_ACK_WITH_ERR_13 : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_13    (BIT(13))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_13_M  (DSI_HOST_FORCE_ACK_WITH_ERR_13_V << DSI_HOST_FORCE_ACK_WITH_ERR_13_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_13_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_13_S  13
+/** DSI_HOST_FORCE_ACK_WITH_ERR_14 : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_14    (BIT(14))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_14_M  (DSI_HOST_FORCE_ACK_WITH_ERR_14_V << DSI_HOST_FORCE_ACK_WITH_ERR_14_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_14_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_14_S  14
+/** DSI_HOST_FORCE_ACK_WITH_ERR_15 : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ACK_WITH_ERR_15    (BIT(15))
+#define DSI_HOST_FORCE_ACK_WITH_ERR_15_M  (DSI_HOST_FORCE_ACK_WITH_ERR_15_V << DSI_HOST_FORCE_ACK_WITH_ERR_15_S)
+#define DSI_HOST_FORCE_ACK_WITH_ERR_15_V  0x00000001U
+#define DSI_HOST_FORCE_ACK_WITH_ERR_15_S  15
+/** DSI_HOST_FORCE_DPHY_ERRORS_0 : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_DPHY_ERRORS_0    (BIT(16))
+#define DSI_HOST_FORCE_DPHY_ERRORS_0_M  (DSI_HOST_FORCE_DPHY_ERRORS_0_V << DSI_HOST_FORCE_DPHY_ERRORS_0_S)
+#define DSI_HOST_FORCE_DPHY_ERRORS_0_V  0x00000001U
+#define DSI_HOST_FORCE_DPHY_ERRORS_0_S  16
+/** DSI_HOST_FORCE_DPHY_ERRORS_1 : R/W; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_DPHY_ERRORS_1    (BIT(17))
+#define DSI_HOST_FORCE_DPHY_ERRORS_1_M  (DSI_HOST_FORCE_DPHY_ERRORS_1_V << DSI_HOST_FORCE_DPHY_ERRORS_1_S)
+#define DSI_HOST_FORCE_DPHY_ERRORS_1_V  0x00000001U
+#define DSI_HOST_FORCE_DPHY_ERRORS_1_S  17
+/** DSI_HOST_FORCE_DPHY_ERRORS_2 : R/W; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_DPHY_ERRORS_2    (BIT(18))
+#define DSI_HOST_FORCE_DPHY_ERRORS_2_M  (DSI_HOST_FORCE_DPHY_ERRORS_2_V << DSI_HOST_FORCE_DPHY_ERRORS_2_S)
+#define DSI_HOST_FORCE_DPHY_ERRORS_2_V  0x00000001U
+#define DSI_HOST_FORCE_DPHY_ERRORS_2_S  18
+/** DSI_HOST_FORCE_DPHY_ERRORS_3 : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_DPHY_ERRORS_3    (BIT(19))
+#define DSI_HOST_FORCE_DPHY_ERRORS_3_M  (DSI_HOST_FORCE_DPHY_ERRORS_3_V << DSI_HOST_FORCE_DPHY_ERRORS_3_S)
+#define DSI_HOST_FORCE_DPHY_ERRORS_3_V  0x00000001U
+#define DSI_HOST_FORCE_DPHY_ERRORS_3_S  19
+/** DSI_HOST_FORCE_DPHY_ERRORS_4 : R/W; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_DPHY_ERRORS_4    (BIT(20))
+#define DSI_HOST_FORCE_DPHY_ERRORS_4_M  (DSI_HOST_FORCE_DPHY_ERRORS_4_V << DSI_HOST_FORCE_DPHY_ERRORS_4_S)
+#define DSI_HOST_FORCE_DPHY_ERRORS_4_V  0x00000001U
+#define DSI_HOST_FORCE_DPHY_ERRORS_4_S  20
+
+/** DSI_HOST_INT_FORCE1_REG register
+ *  NA
+ */
+#define DSI_HOST_INT_FORCE1_REG (DR_REG_DSI_HOST_BASE + 0xdc)
+/** DSI_HOST_FORCE_TO_HS_TX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_TO_HS_TX    (BIT(0))
+#define DSI_HOST_FORCE_TO_HS_TX_M  (DSI_HOST_FORCE_TO_HS_TX_V << DSI_HOST_FORCE_TO_HS_TX_S)
+#define DSI_HOST_FORCE_TO_HS_TX_V  0x00000001U
+#define DSI_HOST_FORCE_TO_HS_TX_S  0
+/** DSI_HOST_FORCE_TO_LP_RX : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_TO_LP_RX    (BIT(1))
+#define DSI_HOST_FORCE_TO_LP_RX_M  (DSI_HOST_FORCE_TO_LP_RX_V << DSI_HOST_FORCE_TO_LP_RX_S)
+#define DSI_HOST_FORCE_TO_LP_RX_V  0x00000001U
+#define DSI_HOST_FORCE_TO_LP_RX_S  1
+/** DSI_HOST_FORCE_ECC_SINGLE_ERR : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ECC_SINGLE_ERR    (BIT(2))
+#define DSI_HOST_FORCE_ECC_SINGLE_ERR_M  (DSI_HOST_FORCE_ECC_SINGLE_ERR_V << DSI_HOST_FORCE_ECC_SINGLE_ERR_S)
+#define DSI_HOST_FORCE_ECC_SINGLE_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_ECC_SINGLE_ERR_S  2
+/** DSI_HOST_FORCE_ECC_MILTI_ERR : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_ECC_MILTI_ERR    (BIT(3))
+#define DSI_HOST_FORCE_ECC_MILTI_ERR_M  (DSI_HOST_FORCE_ECC_MILTI_ERR_V << DSI_HOST_FORCE_ECC_MILTI_ERR_S)
+#define DSI_HOST_FORCE_ECC_MILTI_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_ECC_MILTI_ERR_S  3
+/** DSI_HOST_FORCE_CRC_ERR : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_CRC_ERR    (BIT(4))
+#define DSI_HOST_FORCE_CRC_ERR_M  (DSI_HOST_FORCE_CRC_ERR_V << DSI_HOST_FORCE_CRC_ERR_S)
+#define DSI_HOST_FORCE_CRC_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_CRC_ERR_S  4
+/** DSI_HOST_FORCE_PKT_SIZE_ERR : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_PKT_SIZE_ERR    (BIT(5))
+#define DSI_HOST_FORCE_PKT_SIZE_ERR_M  (DSI_HOST_FORCE_PKT_SIZE_ERR_V << DSI_HOST_FORCE_PKT_SIZE_ERR_S)
+#define DSI_HOST_FORCE_PKT_SIZE_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_PKT_SIZE_ERR_S  5
+/** DSI_HOST_FORCE_EOPT_ERR : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_EOPT_ERR    (BIT(6))
+#define DSI_HOST_FORCE_EOPT_ERR_M  (DSI_HOST_FORCE_EOPT_ERR_V << DSI_HOST_FORCE_EOPT_ERR_S)
+#define DSI_HOST_FORCE_EOPT_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_EOPT_ERR_S  6
+/** DSI_HOST_FORCE_DPI_PLD_WR_ERR : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_DPI_PLD_WR_ERR    (BIT(7))
+#define DSI_HOST_FORCE_DPI_PLD_WR_ERR_M  (DSI_HOST_FORCE_DPI_PLD_WR_ERR_V << DSI_HOST_FORCE_DPI_PLD_WR_ERR_S)
+#define DSI_HOST_FORCE_DPI_PLD_WR_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_DPI_PLD_WR_ERR_S  7
+/** DSI_HOST_FORCE_GEN_CMD_WR_ERR : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_GEN_CMD_WR_ERR    (BIT(8))
+#define DSI_HOST_FORCE_GEN_CMD_WR_ERR_M  (DSI_HOST_FORCE_GEN_CMD_WR_ERR_V << DSI_HOST_FORCE_GEN_CMD_WR_ERR_S)
+#define DSI_HOST_FORCE_GEN_CMD_WR_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_GEN_CMD_WR_ERR_S  8
+/** DSI_HOST_FORCE_GEN_PLD_WR_ERR : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_GEN_PLD_WR_ERR    (BIT(9))
+#define DSI_HOST_FORCE_GEN_PLD_WR_ERR_M  (DSI_HOST_FORCE_GEN_PLD_WR_ERR_V << DSI_HOST_FORCE_GEN_PLD_WR_ERR_S)
+#define DSI_HOST_FORCE_GEN_PLD_WR_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_GEN_PLD_WR_ERR_S  9
+/** DSI_HOST_FORCE_GEN_PLD_SEND_ERR : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_GEN_PLD_SEND_ERR    (BIT(10))
+#define DSI_HOST_FORCE_GEN_PLD_SEND_ERR_M  (DSI_HOST_FORCE_GEN_PLD_SEND_ERR_V << DSI_HOST_FORCE_GEN_PLD_SEND_ERR_S)
+#define DSI_HOST_FORCE_GEN_PLD_SEND_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_GEN_PLD_SEND_ERR_S  10
+/** DSI_HOST_FORCE_GEN_PLD_RD_ERR : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_GEN_PLD_RD_ERR    (BIT(11))
+#define DSI_HOST_FORCE_GEN_PLD_RD_ERR_M  (DSI_HOST_FORCE_GEN_PLD_RD_ERR_V << DSI_HOST_FORCE_GEN_PLD_RD_ERR_S)
+#define DSI_HOST_FORCE_GEN_PLD_RD_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_GEN_PLD_RD_ERR_S  11
+/** DSI_HOST_FORCE_GEN_PLD_RECEV_ERR : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_GEN_PLD_RECEV_ERR    (BIT(12))
+#define DSI_HOST_FORCE_GEN_PLD_RECEV_ERR_M  (DSI_HOST_FORCE_GEN_PLD_RECEV_ERR_V << DSI_HOST_FORCE_GEN_PLD_RECEV_ERR_S)
+#define DSI_HOST_FORCE_GEN_PLD_RECEV_ERR_V  0x00000001U
+#define DSI_HOST_FORCE_GEN_PLD_RECEV_ERR_S  12
+/** DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER    (BIT(19))
+#define DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER_M  (DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER_V << DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER_S)
+#define DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER_V  0x00000001U
+#define DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER_S  19
+
+/** DSI_HOST_DSC_PARAMETER_REG register
+ *  NA
+ */
+#define DSI_HOST_DSC_PARAMETER_REG (DR_REG_DSI_HOST_BASE + 0xf0)
+/** DSI_HOST_COMPRESSION_MODE : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_COMPRESSION_MODE    (BIT(0))
+#define DSI_HOST_COMPRESSION_MODE_M  (DSI_HOST_COMPRESSION_MODE_V << DSI_HOST_COMPRESSION_MODE_S)
+#define DSI_HOST_COMPRESSION_MODE_V  0x00000001U
+#define DSI_HOST_COMPRESSION_MODE_S  0
+/** DSI_HOST_COMPRESS_ALGO : R/W; bitpos: [9:8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_COMPRESS_ALGO    0x00000003U
+#define DSI_HOST_COMPRESS_ALGO_M  (DSI_HOST_COMPRESS_ALGO_V << DSI_HOST_COMPRESS_ALGO_S)
+#define DSI_HOST_COMPRESS_ALGO_V  0x00000003U
+#define DSI_HOST_COMPRESS_ALGO_S  8
+/** DSI_HOST_PPS_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_PPS_SEL    0x00000003U
+#define DSI_HOST_PPS_SEL_M  (DSI_HOST_PPS_SEL_V << DSI_HOST_PPS_SEL_S)
+#define DSI_HOST_PPS_SEL_V  0x00000003U
+#define DSI_HOST_PPS_SEL_S  16
+
+/** DSI_HOST_PHY_TMR_RD_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_PHY_TMR_RD_CFG_REG (DR_REG_DSI_HOST_BASE + 0xf4)
+/** DSI_HOST_MAX_RD_TIME : R/W; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MAX_RD_TIME    0x00007FFFU
+#define DSI_HOST_MAX_RD_TIME_M  (DSI_HOST_MAX_RD_TIME_V << DSI_HOST_MAX_RD_TIME_S)
+#define DSI_HOST_MAX_RD_TIME_V  0x00007FFFU
+#define DSI_HOST_MAX_RD_TIME_S  0
+
+/** DSI_HOST_VID_SHADOW_CTRL_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_SHADOW_CTRL_REG (DR_REG_DSI_HOST_BASE + 0x100)
+/** DSI_HOST_VID_SHADOW_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_SHADOW_EN    (BIT(0))
+#define DSI_HOST_VID_SHADOW_EN_M  (DSI_HOST_VID_SHADOW_EN_V << DSI_HOST_VID_SHADOW_EN_S)
+#define DSI_HOST_VID_SHADOW_EN_V  0x00000001U
+#define DSI_HOST_VID_SHADOW_EN_S  0
+/** DSI_HOST_VID_SHADOW_REQ : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_SHADOW_REQ    (BIT(8))
+#define DSI_HOST_VID_SHADOW_REQ_M  (DSI_HOST_VID_SHADOW_REQ_V << DSI_HOST_VID_SHADOW_REQ_S)
+#define DSI_HOST_VID_SHADOW_REQ_V  0x00000001U
+#define DSI_HOST_VID_SHADOW_REQ_S  8
+/** DSI_HOST_VID_SHADOW_PIN_REQ : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_SHADOW_PIN_REQ    (BIT(16))
+#define DSI_HOST_VID_SHADOW_PIN_REQ_M  (DSI_HOST_VID_SHADOW_PIN_REQ_V << DSI_HOST_VID_SHADOW_PIN_REQ_S)
+#define DSI_HOST_VID_SHADOW_PIN_REQ_V  0x00000001U
+#define DSI_HOST_VID_SHADOW_PIN_REQ_S  16
+
+/** DSI_HOST_DPI_VCID_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_DPI_VCID_ACT_REG (DR_REG_DSI_HOST_BASE + 0x10c)
+/** DSI_HOST_DPI_VCID_ACT : RO; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPI_VCID_ACT    0x00000003U
+#define DSI_HOST_DPI_VCID_ACT_M  (DSI_HOST_DPI_VCID_ACT_V << DSI_HOST_DPI_VCID_ACT_S)
+#define DSI_HOST_DPI_VCID_ACT_V  0x00000003U
+#define DSI_HOST_DPI_VCID_ACT_S  0
+
+/** DSI_HOST_DPI_COLOR_CODING_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_DPI_COLOR_CODING_ACT_REG (DR_REG_DSI_HOST_BASE + 0x110)
+/** DSI_HOST_DPI_COLOR_CODING_ACT : RO; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPI_COLOR_CODING_ACT    0x0000000FU
+#define DSI_HOST_DPI_COLOR_CODING_ACT_M  (DSI_HOST_DPI_COLOR_CODING_ACT_V << DSI_HOST_DPI_COLOR_CODING_ACT_S)
+#define DSI_HOST_DPI_COLOR_CODING_ACT_V  0x0000000FU
+#define DSI_HOST_DPI_COLOR_CODING_ACT_S  0
+/** DSI_HOST_LOOSELY18_EN_ACT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LOOSELY18_EN_ACT    (BIT(8))
+#define DSI_HOST_LOOSELY18_EN_ACT_M  (DSI_HOST_LOOSELY18_EN_ACT_V << DSI_HOST_LOOSELY18_EN_ACT_S)
+#define DSI_HOST_LOOSELY18_EN_ACT_V  0x00000001U
+#define DSI_HOST_LOOSELY18_EN_ACT_S  8
+
+/** DSI_HOST_DPI_LP_CMD_TIM_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_DPI_LP_CMD_TIM_ACT_REG (DR_REG_DSI_HOST_BASE + 0x118)
+/** DSI_HOST_INVACT_LPCMD_TIME_ACT : RO; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_INVACT_LPCMD_TIME_ACT    0x000000FFU
+#define DSI_HOST_INVACT_LPCMD_TIME_ACT_M  (DSI_HOST_INVACT_LPCMD_TIME_ACT_V << DSI_HOST_INVACT_LPCMD_TIME_ACT_S)
+#define DSI_HOST_INVACT_LPCMD_TIME_ACT_V  0x000000FFU
+#define DSI_HOST_INVACT_LPCMD_TIME_ACT_S  0
+/** DSI_HOST_OUTVACT_LPCMD_TIME_ACT : RO; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_OUTVACT_LPCMD_TIME_ACT    0x000000FFU
+#define DSI_HOST_OUTVACT_LPCMD_TIME_ACT_M  (DSI_HOST_OUTVACT_LPCMD_TIME_ACT_V << DSI_HOST_OUTVACT_LPCMD_TIME_ACT_S)
+#define DSI_HOST_OUTVACT_LPCMD_TIME_ACT_V  0x000000FFU
+#define DSI_HOST_OUTVACT_LPCMD_TIME_ACT_S  16
+
+/** DSI_HOST_EDPI_TE_HW_CFG_REG register
+ *  NA
+ */
+#define DSI_HOST_EDPI_TE_HW_CFG_REG (DR_REG_DSI_HOST_BASE + 0x11c)
+/** DSI_HOST_HW_TEAR_EFFECT_ON : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_HW_TEAR_EFFECT_ON    (BIT(0))
+#define DSI_HOST_HW_TEAR_EFFECT_ON_M  (DSI_HOST_HW_TEAR_EFFECT_ON_V << DSI_HOST_HW_TEAR_EFFECT_ON_S)
+#define DSI_HOST_HW_TEAR_EFFECT_ON_V  0x00000001U
+#define DSI_HOST_HW_TEAR_EFFECT_ON_S  0
+/** DSI_HOST_HW_TEAR_EFFECT_GEN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_HW_TEAR_EFFECT_GEN    (BIT(1))
+#define DSI_HOST_HW_TEAR_EFFECT_GEN_M  (DSI_HOST_HW_TEAR_EFFECT_GEN_V << DSI_HOST_HW_TEAR_EFFECT_GEN_S)
+#define DSI_HOST_HW_TEAR_EFFECT_GEN_V  0x00000001U
+#define DSI_HOST_HW_TEAR_EFFECT_GEN_S  1
+/** DSI_HOST_HW_SET_SCAN_LINE : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_HW_SET_SCAN_LINE    (BIT(4))
+#define DSI_HOST_HW_SET_SCAN_LINE_M  (DSI_HOST_HW_SET_SCAN_LINE_V << DSI_HOST_HW_SET_SCAN_LINE_S)
+#define DSI_HOST_HW_SET_SCAN_LINE_V  0x00000001U
+#define DSI_HOST_HW_SET_SCAN_LINE_S  4
+/** DSI_HOST_SCAN_LINE_PARAMETER : R/W; bitpos: [31:16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_SCAN_LINE_PARAMETER    0x0000FFFFU
+#define DSI_HOST_SCAN_LINE_PARAMETER_M  (DSI_HOST_SCAN_LINE_PARAMETER_V << DSI_HOST_SCAN_LINE_PARAMETER_S)
+#define DSI_HOST_SCAN_LINE_PARAMETER_V  0x0000FFFFU
+#define DSI_HOST_SCAN_LINE_PARAMETER_S  16
+
+/** DSI_HOST_VID_MODE_CFG_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_MODE_CFG_ACT_REG (DR_REG_DSI_HOST_BASE + 0x138)
+/** DSI_HOST_VID_MODE_TYPE_ACT : RO; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_MODE_TYPE_ACT    0x00000003U
+#define DSI_HOST_VID_MODE_TYPE_ACT_M  (DSI_HOST_VID_MODE_TYPE_ACT_V << DSI_HOST_VID_MODE_TYPE_ACT_S)
+#define DSI_HOST_VID_MODE_TYPE_ACT_V  0x00000003U
+#define DSI_HOST_VID_MODE_TYPE_ACT_S  0
+/** DSI_HOST_LP_VSA_EN_ACT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_VSA_EN_ACT    (BIT(2))
+#define DSI_HOST_LP_VSA_EN_ACT_M  (DSI_HOST_LP_VSA_EN_ACT_V << DSI_HOST_LP_VSA_EN_ACT_S)
+#define DSI_HOST_LP_VSA_EN_ACT_V  0x00000001U
+#define DSI_HOST_LP_VSA_EN_ACT_S  2
+/** DSI_HOST_LP_VBP_EN_ACT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_VBP_EN_ACT    (BIT(3))
+#define DSI_HOST_LP_VBP_EN_ACT_M  (DSI_HOST_LP_VBP_EN_ACT_V << DSI_HOST_LP_VBP_EN_ACT_S)
+#define DSI_HOST_LP_VBP_EN_ACT_V  0x00000001U
+#define DSI_HOST_LP_VBP_EN_ACT_S  3
+/** DSI_HOST_LP_VFP_EN_ACT : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_VFP_EN_ACT    (BIT(4))
+#define DSI_HOST_LP_VFP_EN_ACT_M  (DSI_HOST_LP_VFP_EN_ACT_V << DSI_HOST_LP_VFP_EN_ACT_S)
+#define DSI_HOST_LP_VFP_EN_ACT_V  0x00000001U
+#define DSI_HOST_LP_VFP_EN_ACT_S  4
+/** DSI_HOST_LP_VACT_EN_ACT : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_VACT_EN_ACT    (BIT(5))
+#define DSI_HOST_LP_VACT_EN_ACT_M  (DSI_HOST_LP_VACT_EN_ACT_V << DSI_HOST_LP_VACT_EN_ACT_S)
+#define DSI_HOST_LP_VACT_EN_ACT_V  0x00000001U
+#define DSI_HOST_LP_VACT_EN_ACT_S  5
+/** DSI_HOST_LP_HBP_EN_ACT : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_HBP_EN_ACT    (BIT(6))
+#define DSI_HOST_LP_HBP_EN_ACT_M  (DSI_HOST_LP_HBP_EN_ACT_V << DSI_HOST_LP_HBP_EN_ACT_S)
+#define DSI_HOST_LP_HBP_EN_ACT_V  0x00000001U
+#define DSI_HOST_LP_HBP_EN_ACT_S  6
+/** DSI_HOST_LP_HFP_EN_ACT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_HFP_EN_ACT    (BIT(7))
+#define DSI_HOST_LP_HFP_EN_ACT_M  (DSI_HOST_LP_HFP_EN_ACT_V << DSI_HOST_LP_HFP_EN_ACT_S)
+#define DSI_HOST_LP_HFP_EN_ACT_V  0x00000001U
+#define DSI_HOST_LP_HFP_EN_ACT_S  7
+/** DSI_HOST_FRAME_BTA_ACK_EN_ACT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FRAME_BTA_ACK_EN_ACT    (BIT(8))
+#define DSI_HOST_FRAME_BTA_ACK_EN_ACT_M  (DSI_HOST_FRAME_BTA_ACK_EN_ACT_V << DSI_HOST_FRAME_BTA_ACK_EN_ACT_S)
+#define DSI_HOST_FRAME_BTA_ACK_EN_ACT_V  0x00000001U
+#define DSI_HOST_FRAME_BTA_ACK_EN_ACT_S  8
+/** DSI_HOST_LP_CMD_EN_ACT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_LP_CMD_EN_ACT    (BIT(9))
+#define DSI_HOST_LP_CMD_EN_ACT_M  (DSI_HOST_LP_CMD_EN_ACT_V << DSI_HOST_LP_CMD_EN_ACT_S)
+#define DSI_HOST_LP_CMD_EN_ACT_V  0x00000001U
+#define DSI_HOST_LP_CMD_EN_ACT_S  9
+
+/** DSI_HOST_VID_PKT_SIZE_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_PKT_SIZE_ACT_REG (DR_REG_DSI_HOST_BASE + 0x13c)
+/** DSI_HOST_VID_PKT_SIZE_ACT : RO; bitpos: [13:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_PKT_SIZE_ACT    0x00003FFFU
+#define DSI_HOST_VID_PKT_SIZE_ACT_M  (DSI_HOST_VID_PKT_SIZE_ACT_V << DSI_HOST_VID_PKT_SIZE_ACT_S)
+#define DSI_HOST_VID_PKT_SIZE_ACT_V  0x00003FFFU
+#define DSI_HOST_VID_PKT_SIZE_ACT_S  0
+
+/** DSI_HOST_VID_NUM_CHUNKS_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_NUM_CHUNKS_ACT_REG (DR_REG_DSI_HOST_BASE + 0x140)
+/** DSI_HOST_VID_NUM_CHUNKS_ACT : RO; bitpos: [12:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_NUM_CHUNKS_ACT    0x00001FFFU
+#define DSI_HOST_VID_NUM_CHUNKS_ACT_M  (DSI_HOST_VID_NUM_CHUNKS_ACT_V << DSI_HOST_VID_NUM_CHUNKS_ACT_S)
+#define DSI_HOST_VID_NUM_CHUNKS_ACT_V  0x00001FFFU
+#define DSI_HOST_VID_NUM_CHUNKS_ACT_S  0
+
+/** DSI_HOST_VID_NULL_SIZE_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_NULL_SIZE_ACT_REG (DR_REG_DSI_HOST_BASE + 0x144)
+/** DSI_HOST_VID_NULL_SIZE_ACT : RO; bitpos: [12:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_NULL_SIZE_ACT    0x00001FFFU
+#define DSI_HOST_VID_NULL_SIZE_ACT_M  (DSI_HOST_VID_NULL_SIZE_ACT_V << DSI_HOST_VID_NULL_SIZE_ACT_S)
+#define DSI_HOST_VID_NULL_SIZE_ACT_V  0x00001FFFU
+#define DSI_HOST_VID_NULL_SIZE_ACT_S  0
+
+/** DSI_HOST_VID_HSA_TIME_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_HSA_TIME_ACT_REG (DR_REG_DSI_HOST_BASE + 0x148)
+/** DSI_HOST_VID_HSA_TIME_ACT : RO; bitpos: [11:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_HSA_TIME_ACT    0x00000FFFU
+#define DSI_HOST_VID_HSA_TIME_ACT_M  (DSI_HOST_VID_HSA_TIME_ACT_V << DSI_HOST_VID_HSA_TIME_ACT_S)
+#define DSI_HOST_VID_HSA_TIME_ACT_V  0x00000FFFU
+#define DSI_HOST_VID_HSA_TIME_ACT_S  0
+
+/** DSI_HOST_VID_HBP_TIME_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_HBP_TIME_ACT_REG (DR_REG_DSI_HOST_BASE + 0x14c)
+/** DSI_HOST_VID_HBP_TIME_ACT : RO; bitpos: [11:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_HBP_TIME_ACT    0x00000FFFU
+#define DSI_HOST_VID_HBP_TIME_ACT_M  (DSI_HOST_VID_HBP_TIME_ACT_V << DSI_HOST_VID_HBP_TIME_ACT_S)
+#define DSI_HOST_VID_HBP_TIME_ACT_V  0x00000FFFU
+#define DSI_HOST_VID_HBP_TIME_ACT_S  0
+
+/** DSI_HOST_VID_HLINE_TIME_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_HLINE_TIME_ACT_REG (DR_REG_DSI_HOST_BASE + 0x150)
+/** DSI_HOST_VID_HLINE_TIME_ACT : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VID_HLINE_TIME_ACT    0x00007FFFU
+#define DSI_HOST_VID_HLINE_TIME_ACT_M  (DSI_HOST_VID_HLINE_TIME_ACT_V << DSI_HOST_VID_HLINE_TIME_ACT_S)
+#define DSI_HOST_VID_HLINE_TIME_ACT_V  0x00007FFFU
+#define DSI_HOST_VID_HLINE_TIME_ACT_S  0
+
+/** DSI_HOST_VID_VSA_LINES_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_VSA_LINES_ACT_REG (DR_REG_DSI_HOST_BASE + 0x154)
+/** DSI_HOST_VSA_LINES_ACT : RO; bitpos: [9:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VSA_LINES_ACT    0x000003FFU
+#define DSI_HOST_VSA_LINES_ACT_M  (DSI_HOST_VSA_LINES_ACT_V << DSI_HOST_VSA_LINES_ACT_S)
+#define DSI_HOST_VSA_LINES_ACT_V  0x000003FFU
+#define DSI_HOST_VSA_LINES_ACT_S  0
+
+/** DSI_HOST_VID_VBP_LINES_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_VBP_LINES_ACT_REG (DR_REG_DSI_HOST_BASE + 0x158)
+/** DSI_HOST_VBP_LINES_ACT : RO; bitpos: [9:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VBP_LINES_ACT    0x000003FFU
+#define DSI_HOST_VBP_LINES_ACT_M  (DSI_HOST_VBP_LINES_ACT_V << DSI_HOST_VBP_LINES_ACT_S)
+#define DSI_HOST_VBP_LINES_ACT_V  0x000003FFU
+#define DSI_HOST_VBP_LINES_ACT_S  0
+
+/** DSI_HOST_VID_VFP_LINES_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_VFP_LINES_ACT_REG (DR_REG_DSI_HOST_BASE + 0x15c)
+/** DSI_HOST_VFP_LINES_ACT : RO; bitpos: [9:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_VFP_LINES_ACT    0x000003FFU
+#define DSI_HOST_VFP_LINES_ACT_M  (DSI_HOST_VFP_LINES_ACT_V << DSI_HOST_VFP_LINES_ACT_S)
+#define DSI_HOST_VFP_LINES_ACT_V  0x000003FFU
+#define DSI_HOST_VFP_LINES_ACT_S  0
+
+/** DSI_HOST_VID_VACTIVE_LINES_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_VACTIVE_LINES_ACT_REG (DR_REG_DSI_HOST_BASE + 0x160)
+/** DSI_HOST_V_ACTIVE_LINES_ACT : RO; bitpos: [13:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_V_ACTIVE_LINES_ACT    0x00003FFFU
+#define DSI_HOST_V_ACTIVE_LINES_ACT_M  (DSI_HOST_V_ACTIVE_LINES_ACT_V << DSI_HOST_V_ACTIVE_LINES_ACT_S)
+#define DSI_HOST_V_ACTIVE_LINES_ACT_V  0x00003FFFU
+#define DSI_HOST_V_ACTIVE_LINES_ACT_S  0
+
+/** DSI_HOST_VID_PKT_STATUS_REG register
+ *  NA
+ */
+#define DSI_HOST_VID_PKT_STATUS_REG (DR_REG_DSI_HOST_BASE + 0x168)
+/** DSI_HOST_DPI_CMD_W_EMPTY : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_DPI_CMD_W_EMPTY    (BIT(0))
+#define DSI_HOST_DPI_CMD_W_EMPTY_M  (DSI_HOST_DPI_CMD_W_EMPTY_V << DSI_HOST_DPI_CMD_W_EMPTY_S)
+#define DSI_HOST_DPI_CMD_W_EMPTY_V  0x00000001U
+#define DSI_HOST_DPI_CMD_W_EMPTY_S  0
+/** DSI_HOST_DPI_CMD_W_FULL : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPI_CMD_W_FULL    (BIT(1))
+#define DSI_HOST_DPI_CMD_W_FULL_M  (DSI_HOST_DPI_CMD_W_FULL_V << DSI_HOST_DPI_CMD_W_FULL_S)
+#define DSI_HOST_DPI_CMD_W_FULL_V  0x00000001U
+#define DSI_HOST_DPI_CMD_W_FULL_S  1
+/** DSI_HOST_DPI_PLD_W_EMPTY : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_DPI_PLD_W_EMPTY    (BIT(2))
+#define DSI_HOST_DPI_PLD_W_EMPTY_M  (DSI_HOST_DPI_PLD_W_EMPTY_V << DSI_HOST_DPI_PLD_W_EMPTY_S)
+#define DSI_HOST_DPI_PLD_W_EMPTY_V  0x00000001U
+#define DSI_HOST_DPI_PLD_W_EMPTY_S  2
+/** DSI_HOST_DPI_PLD_W_FULL : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPI_PLD_W_FULL    (BIT(3))
+#define DSI_HOST_DPI_PLD_W_FULL_M  (DSI_HOST_DPI_PLD_W_FULL_V << DSI_HOST_DPI_PLD_W_FULL_S)
+#define DSI_HOST_DPI_PLD_W_FULL_V  0x00000001U
+#define DSI_HOST_DPI_PLD_W_FULL_S  3
+/** DSI_HOST_DPI_BUFF_PLD_EMPTY : RO; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DSI_HOST_DPI_BUFF_PLD_EMPTY    (BIT(16))
+#define DSI_HOST_DPI_BUFF_PLD_EMPTY_M  (DSI_HOST_DPI_BUFF_PLD_EMPTY_V << DSI_HOST_DPI_BUFF_PLD_EMPTY_S)
+#define DSI_HOST_DPI_BUFF_PLD_EMPTY_V  0x00000001U
+#define DSI_HOST_DPI_BUFF_PLD_EMPTY_S  16
+/** DSI_HOST_DPI_BUFF_PLD_FULL : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_DPI_BUFF_PLD_FULL    (BIT(17))
+#define DSI_HOST_DPI_BUFF_PLD_FULL_M  (DSI_HOST_DPI_BUFF_PLD_FULL_V << DSI_HOST_DPI_BUFF_PLD_FULL_S)
+#define DSI_HOST_DPI_BUFF_PLD_FULL_V  0x00000001U
+#define DSI_HOST_DPI_BUFF_PLD_FULL_S  17
+
+/** DSI_HOST_SDF_3D_ACT_REG register
+ *  NA
+ */
+#define DSI_HOST_SDF_3D_ACT_REG (DR_REG_DSI_HOST_BASE + 0x190)
+/** DSI_HOST_MODE_3D_ACT : RO; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_MODE_3D_ACT    0x00000003U
+#define DSI_HOST_MODE_3D_ACT_M  (DSI_HOST_MODE_3D_ACT_V << DSI_HOST_MODE_3D_ACT_S)
+#define DSI_HOST_MODE_3D_ACT_V  0x00000003U
+#define DSI_HOST_MODE_3D_ACT_S  0
+/** DSI_HOST_FORMAT_3D_ACT : RO; bitpos: [3:2]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_FORMAT_3D_ACT    0x00000003U
+#define DSI_HOST_FORMAT_3D_ACT_M  (DSI_HOST_FORMAT_3D_ACT_V << DSI_HOST_FORMAT_3D_ACT_S)
+#define DSI_HOST_FORMAT_3D_ACT_V  0x00000003U
+#define DSI_HOST_FORMAT_3D_ACT_S  2
+/** DSI_HOST_SECOND_VSYNC_ACT : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_SECOND_VSYNC_ACT    (BIT(4))
+#define DSI_HOST_SECOND_VSYNC_ACT_M  (DSI_HOST_SECOND_VSYNC_ACT_V << DSI_HOST_SECOND_VSYNC_ACT_S)
+#define DSI_HOST_SECOND_VSYNC_ACT_V  0x00000001U
+#define DSI_HOST_SECOND_VSYNC_ACT_S  4
+/** DSI_HOST_RIGHT_FIRST_ACT : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_RIGHT_FIRST_ACT    (BIT(5))
+#define DSI_HOST_RIGHT_FIRST_ACT_M  (DSI_HOST_RIGHT_FIRST_ACT_V << DSI_HOST_RIGHT_FIRST_ACT_S)
+#define DSI_HOST_RIGHT_FIRST_ACT_V  0x00000001U
+#define DSI_HOST_RIGHT_FIRST_ACT_S  5
+/** DSI_HOST_SEND_3D_CFG_ACT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DSI_HOST_SEND_3D_CFG_ACT    (BIT(16))
+#define DSI_HOST_SEND_3D_CFG_ACT_M  (DSI_HOST_SEND_3D_CFG_ACT_V << DSI_HOST_SEND_3D_CFG_ACT_S)
+#define DSI_HOST_SEND_3D_CFG_ACT_V  0x00000001U
+#define DSI_HOST_SEND_3D_CFG_ACT_S  16
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_struct.h
new file mode 100644
index 0000000000..15e17eba71
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_struct.h
@@ -0,0 +1,2008 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Version Register */
+/** Type of version register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** version : RO; bitpos: [31:0]; default: 825504042;
+         *  NA
+         */
+        uint32_t version:32;
+    };
+    uint32_t val;
+} dsi_host_version_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of pwr_up register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** shutdownz : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t shutdownz:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_host_pwr_up_reg_t;
+
+/** Type of clkmgr_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tx_esc_clk_division : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t tx_esc_clk_division:8;
+        /** to_clk_division : R/W; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t to_clk_division:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_clkmgr_cfg_reg_t;
+
+/** Type of dpi_vcid register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dpi_vcid : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_vcid:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_host_dpi_vcid_reg_t;
+
+/** Type of dpi_color_coding register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dpi_color_coding : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_color_coding:4;
+        uint32_t reserved_4:4;
+        /** loosely18_en : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t loosely18_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} dsi_host_dpi_color_coding_reg_t;
+
+/** Type of dpi_cfg_pol register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dataen_active_low : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dataen_active_low:1;
+        /** vsync_active_low : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t vsync_active_low:1;
+        /** hsync_active_low : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t hsync_active_low:1;
+        /** shutd_active_low : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t shutd_active_low:1;
+        /** colorm_active_low : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t colorm_active_low:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} dsi_host_dpi_cfg_pol_reg_t;
+
+/** Type of dpi_lp_cmd_tim register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** invact_lpcmd_time : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t invact_lpcmd_time:8;
+        uint32_t reserved_8:8;
+        /** outvact_lpcmd_time : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t outvact_lpcmd_time:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dsi_host_dpi_lp_cmd_tim_reg_t;
+
+/** Type of dbi_vcid register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dbi_vcid : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t dbi_vcid:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_host_dbi_vcid_reg_t;
+
+/** Type of dbi_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** in_dbi_conf : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t in_dbi_conf:4;
+        uint32_t reserved_4:4;
+        /** out_dbi_conf : R/W; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t out_dbi_conf:4;
+        uint32_t reserved_12:4;
+        /** lut_size_conf : R/W; bitpos: [17:16]; default: 0;
+         *  NA
+         */
+        uint32_t lut_size_conf:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dsi_host_dbi_cfg_reg_t;
+
+/** Type of dbi_partitioning_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** partitioning_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t partitioning_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_host_dbi_partitioning_en_reg_t;
+
+/** Type of dbi_cmdsize register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** wr_cmd_size : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t wr_cmd_size:16;
+        /** allowed_cmd_size : R/W; bitpos: [31:16]; default: 0;
+         *  NA
+         */
+        uint32_t allowed_cmd_size:16;
+    };
+    uint32_t val;
+} dsi_host_dbi_cmdsize_reg_t;
+
+/** Type of pckhdl_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** eotp_tx_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t eotp_tx_en:1;
+        /** eotp_rx_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t eotp_rx_en:1;
+        /** bta_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t bta_en:1;
+        /** ecc_rx_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_rx_en:1;
+        /** crc_rx_en : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t crc_rx_en:1;
+        /** eotp_tx_lp_en : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t eotp_tx_lp_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dsi_host_pckhdl_cfg_reg_t;
+
+/** Type of gen_vcid register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gen_vcid_rx : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t gen_vcid_rx:2;
+        uint32_t reserved_2:6;
+        /** gen_vcid_tear_auto : R/W; bitpos: [9:8]; default: 0;
+         *  NA
+         */
+        uint32_t gen_vcid_tear_auto:2;
+        uint32_t reserved_10:6;
+        /** gen_vcid_tx_auto : R/W; bitpos: [17:16]; default: 0;
+         *  NA
+         */
+        uint32_t gen_vcid_tx_auto:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dsi_host_gen_vcid_reg_t;
+
+/** Type of mode_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cmd_video_mode : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t cmd_video_mode:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_host_mode_cfg_reg_t;
+
+/** Type of vid_mode_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_mode_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_mode_type:2;
+        uint32_t reserved_2:6;
+        /** lp_vsa_en : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vsa_en:1;
+        /** lp_vbp_en : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vbp_en:1;
+        /** lp_vfp_en : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vfp_en:1;
+        /** lp_vact_en : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vact_en:1;
+        /** lp_hbp_en : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t lp_hbp_en:1;
+        /** lp_hfp_en : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t lp_hfp_en:1;
+        /** frame_bta_ack_en : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t frame_bta_ack_en:1;
+        /** lp_cmd_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t lp_cmd_en:1;
+        /** vpg_en : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t vpg_en:1;
+        uint32_t reserved_17:3;
+        /** vpg_mode : R/W; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t vpg_mode:1;
+        uint32_t reserved_21:3;
+        /** vpg_orientation : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t vpg_orientation:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dsi_host_vid_mode_cfg_reg_t;
+
+/** Type of vid_pkt_size register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_pkt_size : R/W; bitpos: [13:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_pkt_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_host_vid_pkt_size_reg_t;
+
+/** Type of vid_num_chunks register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_num_chunks : R/W; bitpos: [12:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_num_chunks:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dsi_host_vid_num_chunks_reg_t;
+
+/** Type of vid_null_size register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_null_size : R/W; bitpos: [12:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_null_size:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dsi_host_vid_null_size_reg_t;
+
+/** Type of vid_hsa_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hsa_time : R/W; bitpos: [11:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hsa_time:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_host_vid_hsa_time_reg_t;
+
+/** Type of vid_hbp_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hbp_time : R/W; bitpos: [11:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hbp_time:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_host_vid_hbp_time_reg_t;
+
+/** Type of vid_hline_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hline_time : R/W; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hline_time:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dsi_host_vid_hline_time_reg_t;
+
+/** Type of vid_vsa_lines register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vsa_lines : R/W; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vsa_lines:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vsa_lines_reg_t;
+
+/** Type of vid_vbp_lines register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vbp_lines : R/W; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vbp_lines:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vbp_lines_reg_t;
+
+/** Type of vid_vfp_lines register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vfp_lines : R/W; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vfp_lines:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vfp_lines_reg_t;
+
+/** Type of vid_vactive_lines register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** v_active_lines : R/W; bitpos: [13:0]; default: 0;
+         *  NA
+         */
+        uint32_t v_active_lines:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_host_vid_vactive_lines_reg_t;
+
+/** Type of edpi_cmd_size register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** edpi_allowed_cmd_size : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t edpi_allowed_cmd_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_edpi_cmd_size_reg_t;
+
+/** Type of cmd_mode_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tear_fx_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t tear_fx_en:1;
+        /** ack_rqst_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ack_rqst_en:1;
+        uint32_t reserved_2:6;
+        /** gen_sw_0p_tx : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sw_0p_tx:1;
+        /** gen_sw_1p_tx : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sw_1p_tx:1;
+        /** gen_sw_2p_tx : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sw_2p_tx:1;
+        /** gen_sr_0p_tx : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sr_0p_tx:1;
+        /** gen_sr_1p_tx : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sr_1p_tx:1;
+        /** gen_sr_2p_tx : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t gen_sr_2p_tx:1;
+        /** gen_lw_tx : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t gen_lw_tx:1;
+        uint32_t reserved_15:1;
+        /** dcs_sw_0p_tx : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t dcs_sw_0p_tx:1;
+        /** dcs_sw_1p_tx : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t dcs_sw_1p_tx:1;
+        /** dcs_sr_0p_tx : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t dcs_sr_0p_tx:1;
+        /** dcs_lw_tx : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t dcs_lw_tx:1;
+        uint32_t reserved_20:4;
+        /** max_rd_pkt_size : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t max_rd_pkt_size:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dsi_host_cmd_mode_cfg_reg_t;
+
+/** Type of gen_hdr register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gen_dt : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t gen_dt:6;
+        /** gen_vc : R/W; bitpos: [7:6]; default: 0;
+         *  NA
+         */
+        uint32_t gen_vc:2;
+        /** gen_wc_lsbyte : R/W; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t gen_wc_lsbyte:8;
+        /** gen_wc_msbyte : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t gen_wc_msbyte:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dsi_host_gen_hdr_reg_t;
+
+/** Type of gen_pld_data register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gen_pld_b1 : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_b1:8;
+        /** gen_pld_b2 : R/W; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_b2:8;
+        /** gen_pld_b3 : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_b3:8;
+        /** gen_pld_b4 : R/W; bitpos: [31:24]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_b4:8;
+    };
+    uint32_t val;
+} dsi_host_gen_pld_data_reg_t;
+
+/** Type of to_cnt_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** lprx_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t lprx_to_cnt:16;
+        /** hstx_to_cnt : R/W; bitpos: [31:16]; default: 0;
+         *  NA
+         */
+        uint32_t hstx_to_cnt:16;
+    };
+    uint32_t val;
+} dsi_host_to_cnt_cfg_reg_t;
+
+/** Type of hs_rd_to_cnt register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** hs_rd_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t hs_rd_to_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_hs_rd_to_cnt_reg_t;
+
+/** Type of lp_rd_to_cnt register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** lp_rd_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t lp_rd_to_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_lp_rd_to_cnt_reg_t;
+
+/** Type of hs_wr_to_cnt register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** hs_wr_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t hs_wr_to_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_hs_wr_to_cnt_reg_t;
+
+/** Type of lp_wr_to_cnt register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** lp_wr_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t lp_wr_to_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_lp_wr_to_cnt_reg_t;
+
+/** Type of bta_to_cnt register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** bta_to_cnt : R/W; bitpos: [15:0]; default: 0;
+         *  NA
+         */
+        uint32_t bta_to_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_bta_to_cnt_reg_t;
+
+/** Type of sdf_3d register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mode_3d : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t mode_3d:2;
+        /** format_3d : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t format_3d:2;
+        /** second_vsync : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t second_vsync:1;
+        /** right_first : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t right_first:1;
+        uint32_t reserved_6:10;
+        /** send_3d_cfg : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t send_3d_cfg:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dsi_host_sdf_3d_reg_t;
+
+/** Type of lpclk_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_txrequestclkhs : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_txrequestclkhs:1;
+        /** auto_clklane_ctrl : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t auto_clklane_ctrl:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_host_lpclk_ctrl_reg_t;
+
+/** Type of phy_tmr_lpclk_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_clklp2hs_time : R/W; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_clklp2hs_time:10;
+        uint32_t reserved_10:6;
+        /** phy_clkhs2lp_time : R/W; bitpos: [25:16]; default: 0;
+         *  NA
+         */
+        uint32_t phy_clkhs2lp_time:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} dsi_host_phy_tmr_lpclk_cfg_reg_t;
+
+/** Type of phy_tmr_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_lp2hs_time : R/W; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_lp2hs_time:10;
+        uint32_t reserved_10:6;
+        /** phy_hs2lp_time : R/W; bitpos: [25:16]; default: 0;
+         *  NA
+         */
+        uint32_t phy_hs2lp_time:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} dsi_host_phy_tmr_cfg_reg_t;
+
+/** Type of phy_rstz register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_shutdownz : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_shutdownz:1;
+        /** phy_rstz : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_rstz:1;
+        /** phy_enableclk : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t phy_enableclk:1;
+        /** phy_forcepll : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t phy_forcepll:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dsi_host_phy_rstz_reg_t;
+
+/** Type of phy_if_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** n_lanes : R/W; bitpos: [1:0]; default: 1;
+         *  NA
+         */
+        uint32_t n_lanes:2;
+        uint32_t reserved_2:6;
+        /** phy_stop_wait_time : R/W; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stop_wait_time:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_host_phy_if_cfg_reg_t;
+
+/** Type of phy_ulps_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_txrequlpsclk : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_txrequlpsclk:1;
+        /** phy_txexitulpsclk : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_txexitulpsclk:1;
+        /** phy_txrequlpslan : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t phy_txrequlpslan:1;
+        /** phy_txexitulpslan : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t phy_txexitulpslan:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dsi_host_phy_ulps_ctrl_reg_t;
+
+/** Type of phy_tx_triggers register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_tx_triggers : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_tx_triggers:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dsi_host_phy_tx_triggers_reg_t;
+
+/** Type of phy_tst_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_testclr : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t phy_testclr:1;
+        /** phy_testclk : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testclk:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_host_phy_tst_ctrl0_reg_t;
+
+/** Type of phy_tst_ctrl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_testdin : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testdin:8;
+        /** pht_testdout : RO; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t pht_testdout:8;
+        /** phy_testen : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t phy_testen:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dsi_host_phy_tst_ctrl1_reg_t;
+
+/** Type of phy_cal register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** txskewcalhs : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t txskewcalhs:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_host_phy_cal_reg_t;
+
+/** Type of dsc_parameter register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** compression_mode : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t compression_mode:1;
+        uint32_t reserved_1:7;
+        /** compress_algo : R/W; bitpos: [9:8]; default: 0;
+         *  NA
+         */
+        uint32_t compress_algo:2;
+        uint32_t reserved_10:6;
+        /** pps_sel : R/W; bitpos: [17:16]; default: 0;
+         *  NA
+         */
+        uint32_t pps_sel:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dsi_host_dsc_parameter_reg_t;
+
+/** Type of phy_tmr_rd_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** max_rd_time : R/W; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t max_rd_time:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dsi_host_phy_tmr_rd_cfg_reg_t;
+
+/** Type of vid_shadow_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_shadow_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_shadow_en:1;
+        uint32_t reserved_1:7;
+        /** vid_shadow_req : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t vid_shadow_req:1;
+        uint32_t reserved_9:7;
+        /** vid_shadow_pin_req : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t vid_shadow_pin_req:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dsi_host_vid_shadow_ctrl_reg_t;
+
+/** Type of edpi_te_hw_cfg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** hw_tear_effect_on : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t hw_tear_effect_on:1;
+        /** hw_tear_effect_gen : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t hw_tear_effect_gen:1;
+        uint32_t reserved_2:2;
+        /** hw_set_scan_line : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t hw_set_scan_line:1;
+        uint32_t reserved_5:11;
+        /** scan_line_parameter : R/W; bitpos: [31:16]; default: 0;
+         *  NA
+         */
+        uint32_t scan_line_parameter:16;
+    };
+    uint32_t val;
+} dsi_host_edpi_te_hw_cfg_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of cmd_pkt_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gen_cmd_empty : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t gen_cmd_empty:1;
+        /** gen_cmd_full : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t gen_cmd_full:1;
+        /** gen_pld_w_empty : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t gen_pld_w_empty:1;
+        /** gen_pld_w_full : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_w_full:1;
+        /** gen_pld_r_empty : RO; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t gen_pld_r_empty:1;
+        /** gen_pld_r_full : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_r_full:1;
+        /** gen_rd_cmd_busy : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t gen_rd_cmd_busy:1;
+        uint32_t reserved_7:9;
+        /** gen_buff_cmd_empty : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t gen_buff_cmd_empty:1;
+        /** gen_buff_cmd_full : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t gen_buff_cmd_full:1;
+        /** gen_buff_pld_empty : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t gen_buff_pld_empty:1;
+        /** gen_buff_pld_full : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t gen_buff_pld_full:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} dsi_host_cmd_pkt_status_reg_t;
+
+/** Type of phy_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** phy_lock : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t phy_lock:1;
+        /** phy_direction : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t phy_direction:1;
+        /** phy_stopstateclklane : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstateclklane:1;
+        /** phy_ulpsactivenotclk : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t phy_ulpsactivenotclk:1;
+        /** phy_stopstate0lane : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstate0lane:1;
+        /** phy_ulpsactivenot0lane : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t phy_ulpsactivenot0lane:1;
+        /** phy_rxulpsesc0lane : RO; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t phy_rxulpsesc0lane:1;
+        /** phy_stopstate1lane : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t phy_stopstate1lane:1;
+        /** phy_ulpsactivenot1lane : RO; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t phy_ulpsactivenot1lane:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} dsi_host_phy_status_reg_t;
+
+/** Type of dpi_vcid_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dpi_vcid_act : RO; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_vcid_act:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_host_dpi_vcid_act_reg_t;
+
+/** Type of dpi_color_coding_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dpi_color_coding_act : RO; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_color_coding_act:4;
+        uint32_t reserved_4:4;
+        /** loosely18_en_act : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t loosely18_en_act:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} dsi_host_dpi_color_coding_act_reg_t;
+
+/** Type of dpi_lp_cmd_tim_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** invact_lpcmd_time_act : RO; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t invact_lpcmd_time_act:8;
+        uint32_t reserved_8:8;
+        /** outvact_lpcmd_time_act : RO; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t outvact_lpcmd_time_act:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dsi_host_dpi_lp_cmd_tim_act_reg_t;
+
+/** Type of vid_mode_cfg_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_mode_type_act : RO; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_mode_type_act:2;
+        /** lp_vsa_en_act : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vsa_en_act:1;
+        /** lp_vbp_en_act : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vbp_en_act:1;
+        /** lp_vfp_en_act : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vfp_en_act:1;
+        /** lp_vact_en_act : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t lp_vact_en_act:1;
+        /** lp_hbp_en_act : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t lp_hbp_en_act:1;
+        /** lp_hfp_en_act : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t lp_hfp_en_act:1;
+        /** frame_bta_ack_en_act : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t frame_bta_ack_en_act:1;
+        /** lp_cmd_en_act : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t lp_cmd_en_act:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_mode_cfg_act_reg_t;
+
+/** Type of vid_pkt_size_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_pkt_size_act : RO; bitpos: [13:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_pkt_size_act:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_host_vid_pkt_size_act_reg_t;
+
+/** Type of vid_num_chunks_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_num_chunks_act : RO; bitpos: [12:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_num_chunks_act:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dsi_host_vid_num_chunks_act_reg_t;
+
+/** Type of vid_null_size_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_null_size_act : RO; bitpos: [12:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_null_size_act:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dsi_host_vid_null_size_act_reg_t;
+
+/** Type of vid_hsa_time_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hsa_time_act : RO; bitpos: [11:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hsa_time_act:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_host_vid_hsa_time_act_reg_t;
+
+/** Type of vid_hbp_time_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hbp_time_act : RO; bitpos: [11:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hbp_time_act:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_host_vid_hbp_time_act_reg_t;
+
+/** Type of vid_hline_time_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid_hline_time_act : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t vid_hline_time_act:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dsi_host_vid_hline_time_act_reg_t;
+
+/** Type of vid_vsa_lines_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vsa_lines_act : RO; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vsa_lines_act:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vsa_lines_act_reg_t;
+
+/** Type of vid_vbp_lines_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vbp_lines_act : RO; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vbp_lines_act:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vbp_lines_act_reg_t;
+
+/** Type of vid_vfp_lines_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vfp_lines_act : RO; bitpos: [9:0]; default: 0;
+         *  NA
+         */
+        uint32_t vfp_lines_act:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} dsi_host_vid_vfp_lines_act_reg_t;
+
+/** Type of vid_vactive_lines_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** v_active_lines_act : RO; bitpos: [13:0]; default: 0;
+         *  NA
+         */
+        uint32_t v_active_lines_act:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_host_vid_vactive_lines_act_reg_t;
+
+/** Type of vid_pkt_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dpi_cmd_w_empty : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t dpi_cmd_w_empty:1;
+        /** dpi_cmd_w_full : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_cmd_w_full:1;
+        /** dpi_pld_w_empty : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t dpi_pld_w_empty:1;
+        /** dpi_pld_w_full : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_pld_w_full:1;
+        uint32_t reserved_4:12;
+        /** dpi_buff_pld_empty : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t dpi_buff_pld_empty:1;
+        /** dpi_buff_pld_full : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_buff_pld_full:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dsi_host_vid_pkt_status_reg_t;
+
+/** Type of sdf_3d_act register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mode_3d_act : RO; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t mode_3d_act:2;
+        /** format_3d_act : RO; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t format_3d_act:2;
+        /** second_vsync_act : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t second_vsync_act:1;
+        /** right_first_act : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t right_first_act:1;
+        uint32_t reserved_6:10;
+        /** send_3d_cfg_act : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t send_3d_cfg_act:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dsi_host_sdf_3d_act_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_st0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ack_with_err_0 : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_0:1;
+        /** ack_with_err_1 : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_1:1;
+        /** ack_with_err_2 : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_2:1;
+        /** ack_with_err_3 : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_3:1;
+        /** ack_with_err_4 : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_4:1;
+        /** ack_with_err_5 : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_5:1;
+        /** ack_with_err_6 : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_6:1;
+        /** ack_with_err_7 : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_7:1;
+        /** ack_with_err_8 : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_8:1;
+        /** ack_with_err_9 : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_9:1;
+        /** ack_with_err_10 : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_10:1;
+        /** ack_with_err_11 : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_11:1;
+        /** ack_with_err_12 : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_12:1;
+        /** ack_with_err_13 : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_13:1;
+        /** ack_with_err_14 : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_14:1;
+        /** ack_with_err_15 : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t ack_with_err_15:1;
+        /** dphy_errors_0 : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_errors_0:1;
+        /** dphy_errors_1 : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_errors_1:1;
+        /** dphy_errors_2 : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_errors_2:1;
+        /** dphy_errors_3 : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_errors_3:1;
+        /** dphy_errors_4 : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t dphy_errors_4:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dsi_host_int_st0_reg_t;
+
+/** Type of int_st1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** to_hs_tx : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t to_hs_tx:1;
+        /** to_lp_rx : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t to_lp_rx:1;
+        /** ecc_single_err : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_single_err:1;
+        /** ecc_milti_err : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_milti_err:1;
+        /** crc_err : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t crc_err:1;
+        /** pkt_size_err : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t pkt_size_err:1;
+        /** eopt_err : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t eopt_err:1;
+        /** dpi_pld_wr_err : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_pld_wr_err:1;
+        /** gen_cmd_wr_err : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t gen_cmd_wr_err:1;
+        /** gen_pld_wr_err : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_wr_err:1;
+        /** gen_pld_send_err : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_send_err:1;
+        /** gen_pld_rd_err : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_rd_err:1;
+        /** gen_pld_recev_err : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t gen_pld_recev_err:1;
+        uint32_t reserved_13:6;
+        /** dpi_buff_pld_under : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t dpi_buff_pld_under:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} dsi_host_int_st1_reg_t;
+
+/** Type of int_msk0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_ack_with_err_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_0:1;
+        /** mask_ack_with_err_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_1:1;
+        /** mask_ack_with_err_2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_2:1;
+        /** mask_ack_with_err_3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_3:1;
+        /** mask_ack_with_err_4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_4:1;
+        /** mask_ack_with_err_5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_5:1;
+        /** mask_ack_with_err_6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_6:1;
+        /** mask_ack_with_err_7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_7:1;
+        /** mask_ack_with_err_8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_8:1;
+        /** mask_ack_with_err_9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_9:1;
+        /** mask_ack_with_err_10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_10:1;
+        /** mask_ack_with_err_11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_11:1;
+        /** mask_ack_with_err_12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_12:1;
+        /** mask_ack_with_err_13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_13:1;
+        /** mask_ack_with_err_14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_14:1;
+        /** mask_ack_with_err_15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ack_with_err_15:1;
+        /** mask_dphy_errors_0 : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dphy_errors_0:1;
+        /** mask_dphy_errors_1 : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dphy_errors_1:1;
+        /** mask_dphy_errors_2 : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dphy_errors_2:1;
+        /** mask_dphy_errors_3 : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dphy_errors_3:1;
+        /** mask_dphy_errors_4 : R/W; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dphy_errors_4:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dsi_host_int_msk0_reg_t;
+
+/** Type of int_msk1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** mask_to_hs_tx : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t mask_to_hs_tx:1;
+        /** mask_to_lp_rx : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t mask_to_lp_rx:1;
+        /** mask_ecc_single_err : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ecc_single_err:1;
+        /** mask_ecc_milti_err : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t mask_ecc_milti_err:1;
+        /** mask_crc_err : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t mask_crc_err:1;
+        /** mask_pkt_size_err : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t mask_pkt_size_err:1;
+        /** mask_eopt_err : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t mask_eopt_err:1;
+        /** mask_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dpi_pld_wr_err:1;
+        /** mask_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t mask_gen_cmd_wr_err:1;
+        /** mask_gen_pld_wr_err : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mask_gen_pld_wr_err:1;
+        /** mask_gen_pld_send_err : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mask_gen_pld_send_err:1;
+        /** mask_gen_pld_rd_err : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mask_gen_pld_rd_err:1;
+        /** mask_gen_pld_recev_err : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mask_gen_pld_recev_err:1;
+        uint32_t reserved_13:6;
+        /** mask_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t mask_dpi_buff_pld_under:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} dsi_host_int_msk1_reg_t;
+
+/** Type of int_force0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_ack_with_err_0 : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_0:1;
+        /** force_ack_with_err_1 : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_1:1;
+        /** force_ack_with_err_2 : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_2:1;
+        /** force_ack_with_err_3 : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_3:1;
+        /** force_ack_with_err_4 : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_4:1;
+        /** force_ack_with_err_5 : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_5:1;
+        /** force_ack_with_err_6 : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_6:1;
+        /** force_ack_with_err_7 : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_7:1;
+        /** force_ack_with_err_8 : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_8:1;
+        /** force_ack_with_err_9 : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_9:1;
+        /** force_ack_with_err_10 : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_10:1;
+        /** force_ack_with_err_11 : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_11:1;
+        /** force_ack_with_err_12 : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_12:1;
+        /** force_ack_with_err_13 : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_13:1;
+        /** force_ack_with_err_14 : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_14:1;
+        /** force_ack_with_err_15 : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t force_ack_with_err_15:1;
+        /** force_dphy_errors_0 : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t force_dphy_errors_0:1;
+        /** force_dphy_errors_1 : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t force_dphy_errors_1:1;
+        /** force_dphy_errors_2 : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t force_dphy_errors_2:1;
+        /** force_dphy_errors_3 : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t force_dphy_errors_3:1;
+        /** force_dphy_errors_4 : R/W; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t force_dphy_errors_4:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dsi_host_int_force0_reg_t;
+
+/** Type of int_force1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** force_to_hs_tx : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t force_to_hs_tx:1;
+        /** force_to_lp_rx : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t force_to_lp_rx:1;
+        /** force_ecc_single_err : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t force_ecc_single_err:1;
+        /** force_ecc_milti_err : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t force_ecc_milti_err:1;
+        /** force_crc_err : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t force_crc_err:1;
+        /** force_pkt_size_err : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t force_pkt_size_err:1;
+        /** force_eopt_err : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t force_eopt_err:1;
+        /** force_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t force_dpi_pld_wr_err:1;
+        /** force_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t force_gen_cmd_wr_err:1;
+        /** force_gen_pld_wr_err : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t force_gen_pld_wr_err:1;
+        /** force_gen_pld_send_err : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t force_gen_pld_send_err:1;
+        /** force_gen_pld_rd_err : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t force_gen_pld_rd_err:1;
+        /** force_gen_pld_recev_err : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t force_gen_pld_recev_err:1;
+        uint32_t reserved_13:6;
+        /** force_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t force_dpi_buff_pld_under:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} dsi_host_int_force1_reg_t;
+
+
+typedef struct dsi_host_dev_t {
+    volatile dsi_host_version_reg_t version;
+    volatile dsi_host_pwr_up_reg_t pwr_up;
+    volatile dsi_host_clkmgr_cfg_reg_t clkmgr_cfg;
+    volatile dsi_host_dpi_vcid_reg_t dpi_vcid;
+    volatile dsi_host_dpi_color_coding_reg_t dpi_color_coding;
+    volatile dsi_host_dpi_cfg_pol_reg_t dpi_cfg_pol;
+    volatile dsi_host_dpi_lp_cmd_tim_reg_t dpi_lp_cmd_tim;
+    volatile dsi_host_dbi_vcid_reg_t dbi_vcid;
+    volatile dsi_host_dbi_cfg_reg_t dbi_cfg;
+    volatile dsi_host_dbi_partitioning_en_reg_t dbi_partitioning_en;
+    volatile dsi_host_dbi_cmdsize_reg_t dbi_cmdsize;
+    volatile dsi_host_pckhdl_cfg_reg_t pckhdl_cfg;
+    volatile dsi_host_gen_vcid_reg_t gen_vcid;
+    volatile dsi_host_mode_cfg_reg_t mode_cfg;
+    volatile dsi_host_vid_mode_cfg_reg_t vid_mode_cfg;
+    volatile dsi_host_vid_pkt_size_reg_t vid_pkt_size;
+    volatile dsi_host_vid_num_chunks_reg_t vid_num_chunks;
+    volatile dsi_host_vid_null_size_reg_t vid_null_size;
+    volatile dsi_host_vid_hsa_time_reg_t vid_hsa_time;
+    volatile dsi_host_vid_hbp_time_reg_t vid_hbp_time;
+    volatile dsi_host_vid_hline_time_reg_t vid_hline_time;
+    volatile dsi_host_vid_vsa_lines_reg_t vid_vsa_lines;
+    volatile dsi_host_vid_vbp_lines_reg_t vid_vbp_lines;
+    volatile dsi_host_vid_vfp_lines_reg_t vid_vfp_lines;
+    volatile dsi_host_vid_vactive_lines_reg_t vid_vactive_lines;
+    volatile dsi_host_edpi_cmd_size_reg_t edpi_cmd_size;
+    volatile dsi_host_cmd_mode_cfg_reg_t cmd_mode_cfg;
+    volatile dsi_host_gen_hdr_reg_t gen_hdr;
+    volatile dsi_host_gen_pld_data_reg_t gen_pld_data;
+    volatile dsi_host_cmd_pkt_status_reg_t cmd_pkt_status;
+    volatile dsi_host_to_cnt_cfg_reg_t to_cnt_cfg;
+    volatile dsi_host_hs_rd_to_cnt_reg_t hs_rd_timeout_cnt;
+    volatile dsi_host_lp_rd_to_cnt_reg_t lp_rd_timeout_cnt;
+    volatile dsi_host_hs_wr_to_cnt_reg_t hs_wr_timeout_cnt;
+    volatile dsi_host_lp_wr_to_cnt_reg_t lp_wr_timeout_cnt;
+    volatile dsi_host_bta_to_cnt_reg_t bta_timeout_cnt;
+    volatile dsi_host_sdf_3d_reg_t sdf_3d;
+    volatile dsi_host_lpclk_ctrl_reg_t lpclk_ctrl;
+    volatile dsi_host_phy_tmr_lpclk_cfg_reg_t phy_tmr_lpclk_cfg;
+    volatile dsi_host_phy_tmr_cfg_reg_t phy_tmr_cfg;
+    volatile dsi_host_phy_rstz_reg_t phy_rstz;
+    volatile dsi_host_phy_if_cfg_reg_t phy_if_cfg;
+    volatile dsi_host_phy_ulps_ctrl_reg_t phy_ulps_ctrl;
+    volatile dsi_host_phy_tx_triggers_reg_t phy_tx_triggers;
+    volatile dsi_host_phy_status_reg_t phy_status;
+    volatile dsi_host_phy_tst_ctrl0_reg_t phy_tst_ctrl0;
+    volatile dsi_host_phy_tst_ctrl1_reg_t phy_tst_ctrl1;
+    volatile dsi_host_int_st0_reg_t int_st0;
+    volatile dsi_host_int_st1_reg_t int_st1;
+    volatile dsi_host_int_msk0_reg_t int_msk0;
+    volatile dsi_host_int_msk1_reg_t int_msk1;
+    volatile dsi_host_phy_cal_reg_t phy_cal;
+    uint32_t reserved_0d0[2];
+    volatile dsi_host_int_force0_reg_t int_force0;
+    volatile dsi_host_int_force1_reg_t int_force1;
+    uint32_t reserved_0e0[4];
+    volatile dsi_host_dsc_parameter_reg_t dsc_parameter;
+    volatile dsi_host_phy_tmr_rd_cfg_reg_t phy_tmr_rd_cfg;
+    uint32_t reserved_0f8[2];
+    volatile dsi_host_vid_shadow_ctrl_reg_t vid_shadow_ctrl;
+    uint32_t reserved_104[2];
+    volatile dsi_host_dpi_vcid_act_reg_t dpi_vcid_act;
+    volatile dsi_host_dpi_color_coding_act_reg_t dpi_color_coding_act;
+    uint32_t reserved_114;
+    volatile dsi_host_dpi_lp_cmd_tim_act_reg_t dpi_lp_cmd_tim_act;
+    volatile dsi_host_edpi_te_hw_cfg_reg_t edpi_te_hw_cfg;
+    uint32_t reserved_120[6];
+    volatile dsi_host_vid_mode_cfg_act_reg_t vid_mode_cfg_act;
+    volatile dsi_host_vid_pkt_size_act_reg_t vid_pkt_size_act;
+    volatile dsi_host_vid_num_chunks_act_reg_t vid_num_chunks_act;
+    volatile dsi_host_vid_null_size_act_reg_t vid_null_size_act;
+    volatile dsi_host_vid_hsa_time_act_reg_t vid_hsa_time_act;
+    volatile dsi_host_vid_hbp_time_act_reg_t vid_hbp_time_act;
+    volatile dsi_host_vid_hline_time_act_reg_t vid_hline_time_act;
+    volatile dsi_host_vid_vsa_lines_act_reg_t vid_vsa_lines_act;
+    volatile dsi_host_vid_vbp_lines_act_reg_t vid_vbp_lines_act;
+    volatile dsi_host_vid_vfp_lines_act_reg_t vid_vfp_lines_act;
+    volatile dsi_host_vid_vactive_lines_act_reg_t vid_vactive_lines_act;
+    uint32_t reserved_164;
+    volatile dsi_host_vid_pkt_status_reg_t vid_pkt_status;
+    uint32_t reserved_16c[9];
+    volatile dsi_host_sdf_3d_act_reg_t sdf_3d_act;
+} dsi_host_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dsi_host_dev_t) == 0x194, "Invalid size of dsi_host_dev_t structure");
+#endif
+
+extern dsi_host_dev_t MIPI_DSI_HOST;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/parl_io_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/parl_io_reg.h
new file mode 100644
index 0000000000..eafecf99ee
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/parl_io_reg.h
@@ -0,0 +1,495 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PARL_IO_RX_MODE_CFG_REG register
+ *  Parallel RX Sampling mode configuration register.
+ */
+#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
+/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
+ *  Configures rx external enable signal selection from IO PAD.
+ */
+#define PARL_IO_RX_EXT_EN_SEL    0x0000000FU
+#define PARL_IO_RX_EXT_EN_SEL_M  (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
+#define PARL_IO_RX_EXT_EN_SEL_V  0x0000000FU
+#define PARL_IO_RX_EXT_EN_SEL_S  21
+/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
+ *  Write 1 to enable data sampling by software.
+ */
+#define PARL_IO_RX_SW_EN    (BIT(25))
+#define PARL_IO_RX_SW_EN_M  (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
+#define PARL_IO_RX_SW_EN_V  0x00000001U
+#define PARL_IO_RX_SW_EN_S  25
+/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
+ *  Write 1 to invert the external enable signal.
+ */
+#define PARL_IO_RX_EXT_EN_INV    (BIT(26))
+#define PARL_IO_RX_EXT_EN_INV_M  (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
+#define PARL_IO_RX_EXT_EN_INV_V  0x00000001U
+#define PARL_IO_RX_EXT_EN_INV_S  26
+/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
+ *  Configures the rxd pulse sampling submode.
+ *  0: positive pulse start(data bit included) &&  positive pulse end(data bit included)
+ *  1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
+ *  2: positive pulse start(data bit excluded) && positive pulse end (data bit included)
+ *  3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)
+ *  4: positive pulse start(data bit included) && length end
+ *  5: positive pulse start(data bit excluded) && length end
+ */
+#define PARL_IO_RX_PULSE_SUBMODE_SEL    0x00000007U
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_M  (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_V  0x00000007U
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_S  27
+/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  Configures the rxd sampling mode.
+ *  0: external level enable mode
+ *  1: external pulse enable mode
+ *  2: internal software enable mode
+ */
+#define PARL_IO_RX_SMP_MODE_SEL    0x00000003U
+#define PARL_IO_RX_SMP_MODE_SEL_M  (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
+#define PARL_IO_RX_SMP_MODE_SEL_V  0x00000003U
+#define PARL_IO_RX_SMP_MODE_SEL_S  30
+
+/** PARL_IO_RX_DATA_CFG_REG register
+ *  Parallel RX data configuration register.
+ */
+#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
+/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
+ *  Configures expected byte number of received data.
+ */
+#define PARL_IO_RX_BITLEN    0x0007FFFFU
+#define PARL_IO_RX_BITLEN_M  (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
+#define PARL_IO_RX_BITLEN_V  0x0007FFFFU
+#define PARL_IO_RX_BITLEN_S  9
+/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
+ *  Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
+ */
+#define PARL_IO_RX_DATA_ORDER_INV    (BIT(28))
+#define PARL_IO_RX_DATA_ORDER_INV_M  (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
+#define PARL_IO_RX_DATA_ORDER_INV_V  0x00000001U
+#define PARL_IO_RX_DATA_ORDER_INV_S  28
+/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
+ *  Configures the rxd bus width.
+ *  0: bus width is 1.
+ *  1: bus width is 2.
+ *  2: bus width is 4.
+ *  3: bus width is 8.
+ */
+#define PARL_IO_RX_BUS_WID_SEL    0x00000007U
+#define PARL_IO_RX_BUS_WID_SEL_M  (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
+#define PARL_IO_RX_BUS_WID_SEL_V  0x00000007U
+#define PARL_IO_RX_BUS_WID_SEL_S  29
+
+/** PARL_IO_RX_GENRL_CFG_REG register
+ *  Parallel RX general configuration register.
+ */
+#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
+/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
+ *  Write 1 to enable the clock gating of output rx clock.
+ */
+#define PARL_IO_RX_GATING_EN    (BIT(12))
+#define PARL_IO_RX_GATING_EN_M  (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
+#define PARL_IO_RX_GATING_EN_V  0x00000001U
+#define PARL_IO_RX_GATING_EN_S  12
+/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
+ *  Configures threshold of timeout counter.
+ */
+#define PARL_IO_RX_TIMEOUT_THRES    0x0000FFFFU
+#define PARL_IO_RX_TIMEOUT_THRES_M  (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
+#define PARL_IO_RX_TIMEOUT_THRES_V  0x0000FFFFU
+#define PARL_IO_RX_TIMEOUT_THRES_S  13
+/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
+ *  Write 1 to enable timeout function to generate error eof.
+ */
+#define PARL_IO_RX_TIMEOUT_EN    (BIT(29))
+#define PARL_IO_RX_TIMEOUT_EN_M  (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
+#define PARL_IO_RX_TIMEOUT_EN_V  0x00000001U
+#define PARL_IO_RX_TIMEOUT_EN_S  29
+/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
+ *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
+ *  1'b1: eof generated by external enable signal.
+ */
+#define PARL_IO_RX_EOF_GEN_SEL    (BIT(30))
+#define PARL_IO_RX_EOF_GEN_SEL_M  (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
+#define PARL_IO_RX_EOF_GEN_SEL_V  0x00000001U
+#define PARL_IO_RX_EOF_GEN_SEL_S  30
+
+/** PARL_IO_RX_START_CFG_REG register
+ *  Parallel RX Start configuration register.
+ */
+#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
+/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to start rx data sampling.
+ */
+#define PARL_IO_RX_START    (BIT(31))
+#define PARL_IO_RX_START_M  (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
+#define PARL_IO_RX_START_V  0x00000001U
+#define PARL_IO_RX_START_S  31
+
+/** PARL_IO_TX_DATA_CFG_REG register
+ *  Parallel TX data configuration register.
+ */
+#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
+/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
+ *  Configures expected byte number of sent data.
+ */
+#define PARL_IO_TX_BITLEN    0x0007FFFFU
+#define PARL_IO_TX_BITLEN_M  (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
+#define PARL_IO_TX_BITLEN_V  0x0007FFFFU
+#define PARL_IO_TX_BITLEN_S  9
+/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
+ *  Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
+ */
+#define PARL_IO_TX_DATA_ORDER_INV    (BIT(28))
+#define PARL_IO_TX_DATA_ORDER_INV_M  (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
+#define PARL_IO_TX_DATA_ORDER_INV_V  0x00000001U
+#define PARL_IO_TX_DATA_ORDER_INV_S  28
+/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
+ *  Configures the txd bus width.
+ *  0: bus width is 1.
+ *  1: bus width is 2.
+ *  2: bus width is 4.
+ *  3: bus width is 8.
+ */
+#define PARL_IO_TX_BUS_WID_SEL    0x00000007U
+#define PARL_IO_TX_BUS_WID_SEL_M  (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
+#define PARL_IO_TX_BUS_WID_SEL_V  0x00000007U
+#define PARL_IO_TX_BUS_WID_SEL_S  29
+
+/** PARL_IO_TX_START_CFG_REG register
+ *  Parallel TX Start configuration register.
+ */
+#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
+/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to start tx data transmit.
+ */
+#define PARL_IO_TX_START    (BIT(31))
+#define PARL_IO_TX_START_M  (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
+#define PARL_IO_TX_START_V  0x00000001U
+#define PARL_IO_TX_START_S  31
+
+/** PARL_IO_TX_GENRL_CFG_REG register
+ *  Parallel TX general configuration register.
+ */
+#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
+/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
+ *  Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
+ *  1'b1: eof generated by DMA eof.
+ */
+#define PARL_IO_TX_EOF_GEN_SEL    (BIT(13))
+#define PARL_IO_TX_EOF_GEN_SEL_M  (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S)
+#define PARL_IO_TX_EOF_GEN_SEL_V  0x00000001U
+#define PARL_IO_TX_EOF_GEN_SEL_S  13
+/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
+ *  Configures bus value of transmitter in IDLE state.
+ */
+#define PARL_IO_TX_IDLE_VALUE    0x0000FFFFU
+#define PARL_IO_TX_IDLE_VALUE_M  (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
+#define PARL_IO_TX_IDLE_VALUE_V  0x0000FFFFU
+#define PARL_IO_TX_IDLE_VALUE_S  14
+/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to enable the clock gating of output tx clock.
+ */
+#define PARL_IO_TX_GATING_EN    (BIT(30))
+#define PARL_IO_TX_GATING_EN_M  (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
+#define PARL_IO_TX_GATING_EN_V  0x00000001U
+#define PARL_IO_TX_GATING_EN_S  30
+/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to enable the output of tx data valid signal.
+ */
+#define PARL_IO_TX_VALID_OUTPUT_EN    (BIT(31))
+#define PARL_IO_TX_VALID_OUTPUT_EN_M  (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
+#define PARL_IO_TX_VALID_OUTPUT_EN_V  0x00000001U
+#define PARL_IO_TX_VALID_OUTPUT_EN_S  31
+
+/** PARL_IO_FIFO_CFG_REG register
+ *  Parallel IO FIFO configuration register.
+ */
+#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
+/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to reset async fifo in tx module.
+ */
+#define PARL_IO_TX_FIFO_SRST    (BIT(30))
+#define PARL_IO_TX_FIFO_SRST_M  (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
+#define PARL_IO_TX_FIFO_SRST_V  0x00000001U
+#define PARL_IO_TX_FIFO_SRST_S  30
+/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to reset async fifo in rx module.
+ */
+#define PARL_IO_RX_FIFO_SRST    (BIT(31))
+#define PARL_IO_RX_FIFO_SRST_M  (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
+#define PARL_IO_RX_FIFO_SRST_V  0x00000001U
+#define PARL_IO_RX_FIFO_SRST_S  31
+
+/** PARL_IO_REG_UPDATE_REG register
+ *  Parallel IO FIFO configuration register.
+ */
+#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
+/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
+ *  Write 1 to update rx register configuration.
+ */
+#define PARL_IO_RX_REG_UPDATE    (BIT(31))
+#define PARL_IO_RX_REG_UPDATE_M  (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
+#define PARL_IO_RX_REG_UPDATE_V  0x00000001U
+#define PARL_IO_RX_REG_UPDATE_S  31
+
+/** PARL_IO_ST_REG register
+ *  Parallel IO module status register0.
+ */
+#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
+/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
+ *  Represents the status that tx is ready to transmit.
+ */
+#define PARL_IO_TX_READY    (BIT(31))
+#define PARL_IO_TX_READY_M  (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
+#define PARL_IO_TX_READY_V  0x00000001U
+#define PARL_IO_TX_READY_S  31
+
+/** PARL_IO_INT_ENA_REG register
+ *  Parallel IO interrupt enable signal configuration register.
+ */
+#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
+/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M  (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M  (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S  1
+/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_ENA    (BIT(2))
+#define PARL_IO_TX_EOF_INT_ENA_M  (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
+#define PARL_IO_TX_EOF_INT_ENA_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_ENA_S  2
+
+/** PARL_IO_INT_RAW_REG register
+ *  Parallel IO interrupt raw signal status register.
+ */
+#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
+/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status of TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M  (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw interrupt status of RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M  (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S  1
+/** PARL_IO_TX_EOF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status of TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_RAW    (BIT(2))
+#define PARL_IO_TX_EOF_INT_RAW_M  (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
+#define PARL_IO_TX_EOF_INT_RAW_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_RAW_S  2
+
+/** PARL_IO_INT_ST_REG register
+ *  Parallel IO interrupt signal status register.
+ */
+#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
+/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M  (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_ST    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_M  (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_S  1
+/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_ST    (BIT(2))
+#define PARL_IO_TX_EOF_INT_ST_M  (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
+#define PARL_IO_TX_EOF_INT_ST_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_ST_S  2
+
+/** PARL_IO_INT_CLR_REG register
+ *  Parallel IO interrupt  clear signal configuration register.
+ */
+#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
+/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M  (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M  (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S  1
+/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_CLR    (BIT(2))
+#define PARL_IO_TX_EOF_INT_CLR_M  (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
+#define PARL_IO_TX_EOF_INT_CLR_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_CLR_S  2
+
+/** PARL_IO_RX_ST0_REG register
+ *  Parallel IO RX status register0
+ */
+#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
+/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
+ *  Indicates the cycle number of reading Rx FIFO.
+ */
+#define PARL_IO_RX_CNT    0x0000001FU
+#define PARL_IO_RX_CNT_M  (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
+#define PARL_IO_RX_CNT_V  0x0000001FU
+#define PARL_IO_RX_CNT_S  8
+/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current written bit number into Rx FIFO.
+ */
+#define PARL_IO_RX_FIFO_WR_BIT_CNT    0x0007FFFFU
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_M  (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_S  13
+
+/** PARL_IO_RX_ST1_REG register
+ *  Parallel IO RX status register1
+ */
+#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
+/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current read bit number from Rx FIFO.
+ */
+#define PARL_IO_RX_FIFO_RD_BIT_CNT    0x0007FFFFU
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_M  (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_S  13
+
+/** PARL_IO_TX_ST0_REG register
+ *  Parallel IO TX status register0
+ */
+#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
+/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
+ *  Indicates the cycle number of reading Tx FIFO.
+ */
+#define PARL_IO_TX_CNT    0x0000007FU
+#define PARL_IO_TX_CNT_M  (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
+#define PARL_IO_TX_CNT_V  0x0000007FU
+#define PARL_IO_TX_CNT_S  6
+/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current read bit number from Tx FIFO.
+ */
+#define PARL_IO_TX_FIFO_RD_BIT_CNT    0x0007FFFFU
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_M  (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_S  13
+
+/** PARL_IO_RX_CLK_CFG_REG register
+ *  Parallel IO RX clk configuration register
+ */
+#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
+/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to invert the input Rx core clock.
+ */
+#define PARL_IO_RX_CLK_I_INV    (BIT(30))
+#define PARL_IO_RX_CLK_I_INV_M  (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
+#define PARL_IO_RX_CLK_I_INV_V  0x00000001U
+#define PARL_IO_RX_CLK_I_INV_S  30
+/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to invert the output Rx core clock.
+ */
+#define PARL_IO_RX_CLK_O_INV    (BIT(31))
+#define PARL_IO_RX_CLK_O_INV_M  (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
+#define PARL_IO_RX_CLK_O_INV_V  0x00000001U
+#define PARL_IO_RX_CLK_O_INV_S  31
+
+/** PARL_IO_TX_CLK_CFG_REG register
+ *  Parallel IO TX clk configuration register
+ */
+#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
+/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to invert the input Tx core clock.
+ */
+#define PARL_IO_TX_CLK_I_INV    (BIT(30))
+#define PARL_IO_TX_CLK_I_INV_M  (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
+#define PARL_IO_TX_CLK_I_INV_V  0x00000001U
+#define PARL_IO_TX_CLK_I_INV_S  30
+/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to invert the output Tx core clock.
+ */
+#define PARL_IO_TX_CLK_O_INV    (BIT(31))
+#define PARL_IO_TX_CLK_O_INV_M  (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
+#define PARL_IO_TX_CLK_O_INV_V  0x00000001U
+#define PARL_IO_TX_CLK_O_INV_S  31
+
+/** PARL_IO_TX_CS_CFG_REG register
+ *  Parallel IO tx_cs_o generate configuration
+ */
+#define PARL_IO_TX_CS_CFG_REG (DR_REG_PARL_IO_BASE + 0x4c)
+/** PARL_IO_TX_CS_STOP_DELAY : R/W; bitpos: [15:0]; default: 0;
+ *  configure the delay between data tx end and tx_cs_o posedge
+ */
+#define PARL_IO_TX_CS_STOP_DELAY    0x0000FFFFU
+#define PARL_IO_TX_CS_STOP_DELAY_M  (PARL_IO_TX_CS_STOP_DELAY_V << PARL_IO_TX_CS_STOP_DELAY_S)
+#define PARL_IO_TX_CS_STOP_DELAY_V  0x0000FFFFU
+#define PARL_IO_TX_CS_STOP_DELAY_S  0
+/** PARL_IO_TX_CS_START_DELAY : R/W; bitpos: [31:16]; default: 0;
+ *  configure the delay between tx_cs_o negedge and data tx start
+ */
+#define PARL_IO_TX_CS_START_DELAY    0x0000FFFFU
+#define PARL_IO_TX_CS_START_DELAY_M  (PARL_IO_TX_CS_START_DELAY_V << PARL_IO_TX_CS_START_DELAY_S)
+#define PARL_IO_TX_CS_START_DELAY_V  0x0000FFFFU
+#define PARL_IO_TX_CS_START_DELAY_S  16
+
+/** PARL_IO_CLK_REG register
+ *  Parallel IO clk configuration register
+ */
+#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
+/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Force clock on for this register file
+ */
+#define PARL_IO_CLK_EN    (BIT(31))
+#define PARL_IO_CLK_EN_M  (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
+#define PARL_IO_CLK_EN_V  0x00000001U
+#define PARL_IO_CLK_EN_S  31
+
+/** PARL_IO_VERSION_REG register
+ *  Version register.
+ */
+#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
+/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 37786160;
+ *  Version of this register file
+ */
+#define PARL_IO_DATE    0x0FFFFFFFU
+#define PARL_IO_DATE_M  (PARL_IO_DATE_V << PARL_IO_DATE_S)
+#define PARL_IO_DATE_V  0x0FFFFFFFU
+#define PARL_IO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/parl_io_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/parl_io_struct.h
new file mode 100644
index 0000000000..e58956022c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/parl_io_struct.h
@@ -0,0 +1,525 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PARL_IO RX  Mode Configuration */
+/** Type of rx_mode_cfg register
+ *  Parallel RX Sampling mode configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
+         *  Configures rx external enable signal selection from IO PAD.
+         */
+        uint32_t rx_ext_en_sel:4;
+        /** rx_sw_en : R/W; bitpos: [25]; default: 0;
+         *  Write 1 to enable data sampling by software.
+         */
+        uint32_t rx_sw_en:1;
+        /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
+         *  Write 1 to invert the external enable signal.
+         */
+        uint32_t rx_ext_en_inv:1;
+        /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
+         *  Configures the rxd pulse sampling submode.
+         *  0: positive pulse start(data bit included) &&  positive pulse end(data bit included)
+         *  1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
+         *  2: positive pulse start(data bit excluded) && positive pulse end (data bit included)
+         *  3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)
+         *  4: positive pulse start(data bit included) && length end
+         *  5: positive pulse start(data bit excluded) && length end
+         */
+        uint32_t rx_pulse_submode_sel:3;
+        /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
+         *  Configures the rxd sampling mode.
+         *  0: external level enable mode
+         *  1: external pulse enable mode
+         *  2: internal software enable mode
+         */
+        uint32_t rx_smp_mode_sel:2;
+    };
+    uint32_t val;
+} parl_io_rx_mode_cfg_reg_t;
+
+
+/** Group: PARL_IO RX Data Configuration */
+/** Type of rx_data_cfg register
+ *  Parallel RX data configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
+         *  Configures expected byte number of received data.
+         */
+        uint32_t rx_bitlen:19;
+        /** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
+         *  Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
+         */
+        uint32_t rx_data_order_inv:1;
+        /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
+         *  Configures the rxd bus width.
+         *  0: bus width is 1.
+         *  1: bus width is 2.
+         *  2: bus width is 4.
+         *  3: bus width is 8.
+         */
+        uint32_t rx_bus_wid_sel:3;
+    };
+    uint32_t val;
+} parl_io_rx_data_cfg_reg_t;
+
+
+/** Group: PARL_IO RX General Configuration */
+/** Type of rx_genrl_cfg register
+ *  Parallel RX general configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** rx_gating_en : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable the clock gating of output rx clock.
+         */
+        uint32_t rx_gating_en:1;
+        /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
+         *  Configures threshold of timeout counter.
+         */
+        uint32_t rx_timeout_thres:16;
+        /** rx_timeout_en : R/W; bitpos: [29]; default: 1;
+         *  Write 1 to enable timeout function to generate error eof.
+         */
+        uint32_t rx_timeout_en:1;
+        /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
+         *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
+         *  1'b1: eof generated by external enable signal.
+         */
+        uint32_t rx_eof_gen_sel:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} parl_io_rx_genrl_cfg_reg_t;
+
+
+/** Group: PARL_IO RX Start Configuration */
+/** Type of rx_start_cfg register
+ *  Parallel RX Start configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** rx_start : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to start rx data sampling.
+         */
+        uint32_t rx_start:1;
+    };
+    uint32_t val;
+} parl_io_rx_start_cfg_reg_t;
+
+
+/** Group: PARL_IO TX Data Configuration */
+/** Type of tx_data_cfg register
+ *  Parallel TX data configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
+         *  Configures expected byte number of sent data.
+         */
+        uint32_t tx_bitlen:19;
+        /** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
+         *  Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
+         */
+        uint32_t tx_data_order_inv:1;
+        /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
+         *  Configures the txd bus width.
+         *  0: bus width is 1.
+         *  1: bus width is 2.
+         *  2: bus width is 4.
+         *  3: bus width is 8.
+         */
+        uint32_t tx_bus_wid_sel:3;
+    };
+    uint32_t val;
+} parl_io_tx_data_cfg_reg_t;
+
+
+/** Group: PARL_IO TX Start Configuration */
+/** Type of tx_start_cfg register
+ *  Parallel TX Start configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_start : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to start tx data transmit.
+         */
+        uint32_t tx_start:1;
+    };
+    uint32_t val;
+} parl_io_tx_start_cfg_reg_t;
+
+
+/** Group: PARL_IO TX General Configuration */
+/** Type of tx_genrl_cfg register
+ *  Parallel TX general configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
+         *  Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
+         *  1'b1: eof generated by DMA eof.
+         */
+        uint32_t tx_eof_gen_sel:1;
+        /** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
+         *  Configures bus value of transmitter in IDLE state.
+         */
+        uint32_t tx_idle_value:16;
+        /** tx_gating_en : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to enable the clock gating of output tx clock.
+         */
+        uint32_t tx_gating_en:1;
+        /** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to enable the output of tx data valid signal.
+         */
+        uint32_t tx_valid_output_en:1;
+    };
+    uint32_t val;
+} parl_io_tx_genrl_cfg_reg_t;
+
+
+/** Group: PARL_IO FIFO Configuration */
+/** Type of fifo_cfg register
+ *  Parallel IO FIFO configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to reset async fifo in tx module.
+         */
+        uint32_t tx_fifo_srst:1;
+        /** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to reset async fifo in rx module.
+         */
+        uint32_t rx_fifo_srst:1;
+    };
+    uint32_t val;
+} parl_io_fifo_cfg_reg_t;
+
+
+/** Group: PARL_IO Register Update Configuration */
+/** Type of reg_update register
+ *  Parallel IO FIFO configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** rx_reg_update : WT; bitpos: [31]; default: 0;
+         *  Write 1 to update rx register configuration.
+         */
+        uint32_t rx_reg_update:1;
+    };
+    uint32_t val;
+} parl_io_reg_update_reg_t;
+
+
+/** Group: PARL_IO Status */
+/** Type of st register
+ *  Parallel IO module status register0.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_ready : RO; bitpos: [31]; default: 0;
+         *  Represents the status that tx is ready to transmit.
+         */
+        uint32_t tx_ready:1;
+    };
+    uint32_t val;
+} parl_io_st_reg_t;
+
+
+/** Group: PARL_IO Interrupt Configuration and Status */
+/** Type of int_ena register
+ *  Parallel IO interrupt enable signal configuration register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_ena:1;
+        /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_ena:1;
+        /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Parallel IO interrupt raw signal status register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status of TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_raw:1;
+        /** rx_fifo_wovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw interrupt status of RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_raw:1;
+        /** tx_eof_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status of TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Parallel IO interrupt signal status register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_st:1;
+        /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_st:1;
+        /** tx_eof_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Parallel IO interrupt  clear signal configuration register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_clr:1;
+        /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_clr:1;
+        /** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_clr_reg_t;
+
+
+/** Group: PARL_IO Rx Status0 */
+/** Type of rx_st0 register
+ *  Parallel IO RX status register0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** rx_cnt : RO; bitpos: [12:8]; default: 0;
+         *  Indicates the cycle number of reading Rx FIFO.
+         */
+        uint32_t rx_cnt:5;
+        /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current written bit number into Rx FIFO.
+         */
+        uint32_t rx_fifo_wr_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_rx_st0_reg_t;
+
+
+/** Group: PARL_IO Rx Status1 */
+/** Type of rx_st1 register
+ *  Parallel IO RX status register1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current read bit number from Rx FIFO.
+         */
+        uint32_t rx_fifo_rd_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_rx_st1_reg_t;
+
+
+/** Group: PARL_IO Tx Status0 */
+/** Type of tx_st0 register
+ *  Parallel IO TX status register0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** tx_cnt : RO; bitpos: [12:6]; default: 0;
+         *  Indicates the cycle number of reading Tx FIFO.
+         */
+        uint32_t tx_cnt:7;
+        /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current read bit number from Tx FIFO.
+         */
+        uint32_t tx_fifo_rd_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_tx_st0_reg_t;
+
+
+/** Group: PARL_IO Rx Clock Configuration */
+/** Type of rx_clk_cfg register
+ *  Parallel IO RX clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to invert the input Rx core clock.
+         */
+        uint32_t rx_clk_i_inv:1;
+        /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to invert the output Rx core clock.
+         */
+        uint32_t rx_clk_o_inv:1;
+    };
+    uint32_t val;
+} parl_io_rx_clk_cfg_reg_t;
+
+
+/** Group: PARL_IO Tx Clock Configuration */
+/** Type of tx_clk_cfg register
+ *  Parallel IO TX clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to invert the input Tx core clock.
+         */
+        uint32_t tx_clk_i_inv:1;
+        /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to invert the output Tx core clock.
+         */
+        uint32_t tx_clk_o_inv:1;
+    };
+    uint32_t val;
+} parl_io_tx_clk_cfg_reg_t;
+
+
+/** Group: PARL_TX_CS Configuration */
+/** Type of tx_cs_cfg register
+ *  Parallel IO tx_cs_o generate configuration
+ */
+typedef union {
+    struct {
+        /** tx_cs_stop_delay : R/W; bitpos: [15:0]; default: 0;
+         *  configure the delay between data tx end and tx_cs_o posedge
+         */
+        uint32_t tx_cs_stop_delay:16;
+        /** tx_cs_start_delay : R/W; bitpos: [31:16]; default: 0;
+         *  configure the delay between tx_cs_o negedge and data tx start
+         */
+        uint32_t tx_cs_start_delay:16;
+    };
+    uint32_t val;
+} parl_io_tx_cs_cfg_reg_t;
+
+
+/** Group: PARL_IO Clock Configuration */
+/** Type of clk register
+ *  Parallel IO clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Force clock on for this register file
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} parl_io_clk_reg_t;
+
+
+/** Group: PARL_IO Version Register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37786160;
+         *  Version of this register file
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} parl_io_version_reg_t;
+
+
+typedef struct parl_io_dev_t {
+    volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
+    volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
+    volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
+    volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
+    volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
+    volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
+    volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
+    volatile parl_io_fifo_cfg_reg_t fifo_cfg;
+    volatile parl_io_reg_update_reg_t reg_update;
+    volatile parl_io_st_reg_t st;
+    volatile parl_io_int_ena_reg_t int_ena;
+    volatile parl_io_int_raw_reg_t int_raw;
+    volatile parl_io_int_st_reg_t int_st;
+    volatile parl_io_int_clr_reg_t int_clr;
+    volatile parl_io_rx_st0_reg_t rx_st0;
+    volatile parl_io_rx_st1_reg_t rx_st1;
+    volatile parl_io_tx_st0_reg_t tx_st0;
+    volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
+    volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
+    volatile parl_io_tx_cs_cfg_reg_t tx_cs_cfg;
+    uint32_t reserved_050[52];
+    volatile parl_io_clk_reg_t clk;
+    uint32_t reserved_124[182];
+    volatile parl_io_version_reg_t version;
+} parl_io_dev_t;
+
+extern parl_io_dev_t PARL_IO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pau_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/pau_reg.h
new file mode 100644
index 0000000000..16ec86ea23
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pau_reg.h
@@ -0,0 +1,332 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PAU_REGDMA_CONF_REG register
+ *  Peri backup control register
+ */
+#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
+/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
+ *  backup error type
+ */
+#define PAU_FLOW_ERR    0x00000007U
+#define PAU_FLOW_ERR_M  (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
+#define PAU_FLOW_ERR_V  0x00000007U
+#define PAU_FLOW_ERR_S  0
+/** PAU_START : WT; bitpos: [3]; default: 0;
+ *  backup start signal
+ */
+#define PAU_START    (BIT(3))
+#define PAU_START_M  (PAU_START_V << PAU_START_S)
+#define PAU_START_V  0x00000001U
+#define PAU_START_S  3
+/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
+ *  backup direction(reg to mem / mem to reg)
+ */
+#define PAU_TO_MEM    (BIT(4))
+#define PAU_TO_MEM_M  (PAU_TO_MEM_V << PAU_TO_MEM_S)
+#define PAU_TO_MEM_V  0x00000001U
+#define PAU_TO_MEM_S  4
+/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  Link select
+ */
+#define PAU_LINK_SEL    0x00000003U
+#define PAU_LINK_SEL_M  (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
+#define PAU_LINK_SEL_V  0x00000003U
+#define PAU_LINK_SEL_S  5
+/** PAU_START_MAC : WT; bitpos: [7]; default: 0;
+ *  mac sw backup start signal
+ */
+#define PAU_START_MAC    (BIT(7))
+#define PAU_START_MAC_M  (PAU_START_MAC_V << PAU_START_MAC_S)
+#define PAU_START_MAC_V  0x00000001U
+#define PAU_START_MAC_S  7
+/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0;
+ *  mac sw backup direction(reg to mem / mem to reg)
+ */
+#define PAU_TO_MEM_MAC    (BIT(8))
+#define PAU_TO_MEM_MAC_M  (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
+#define PAU_TO_MEM_MAC_V  0x00000001U
+#define PAU_TO_MEM_MAC_S  8
+/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0;
+ *  mac hw/sw select
+ */
+#define PAU_SEL_MAC    (BIT(9))
+#define PAU_SEL_MAC_M  (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
+#define PAU_SEL_MAC_V  0x00000001U
+#define PAU_SEL_MAC_S  9
+
+/** PAU_REGDMA_CLK_CONF_REG register
+ *  Clock control register
+ */
+#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
+/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  clock enable
+ */
+#define PAU_CLK_EN    (BIT(0))
+#define PAU_CLK_EN_M  (PAU_CLK_EN_V << PAU_CLK_EN_S)
+#define PAU_CLK_EN_V  0x00000001U
+#define PAU_CLK_EN_S  0
+
+/** PAU_REGDMA_ETM_CTRL_REG register
+ *  ETM start ctrl reg
+ */
+#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
+/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
+ *  etm_start_0 reg
+ */
+#define PAU_ETM_START_0    (BIT(0))
+#define PAU_ETM_START_0_M  (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
+#define PAU_ETM_START_0_V  0x00000001U
+#define PAU_ETM_START_0_S  0
+/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
+ *  etm_start_1 reg
+ */
+#define PAU_ETM_START_1    (BIT(1))
+#define PAU_ETM_START_1_M  (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
+#define PAU_ETM_START_1_V  0x00000001U
+#define PAU_ETM_START_1_S  1
+/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
+ *  etm_start_2 reg
+ */
+#define PAU_ETM_START_2    (BIT(2))
+#define PAU_ETM_START_2_M  (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
+#define PAU_ETM_START_2_V  0x00000001U
+#define PAU_ETM_START_2_S  2
+/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
+ *  etm_start_3 reg
+ */
+#define PAU_ETM_START_3    (BIT(3))
+#define PAU_ETM_START_3_M  (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
+#define PAU_ETM_START_3_V  0x00000001U
+#define PAU_ETM_START_3_S  3
+
+/** PAU_REGDMA_LINK_0_ADDR_REG register
+ *  link_0_addr
+ */
+#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc)
+/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0;
+ *  link_0_addr reg
+ */
+#define PAU_LINK_ADDR_0    0xFFFFFFFFU
+#define PAU_LINK_ADDR_0_M  (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S)
+#define PAU_LINK_ADDR_0_V  0xFFFFFFFFU
+#define PAU_LINK_ADDR_0_S  0
+
+/** PAU_REGDMA_LINK_1_ADDR_REG register
+ *  Link_1_addr
+ */
+#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10)
+/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Link_1_addr reg
+ */
+#define PAU_LINK_ADDR_1    0xFFFFFFFFU
+#define PAU_LINK_ADDR_1_M  (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S)
+#define PAU_LINK_ADDR_1_V  0xFFFFFFFFU
+#define PAU_LINK_ADDR_1_S  0
+
+/** PAU_REGDMA_LINK_2_ADDR_REG register
+ *  Link_2_addr
+ */
+#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14)
+/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Link_2_addr reg
+ */
+#define PAU_LINK_ADDR_2    0xFFFFFFFFU
+#define PAU_LINK_ADDR_2_M  (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S)
+#define PAU_LINK_ADDR_2_V  0xFFFFFFFFU
+#define PAU_LINK_ADDR_2_S  0
+
+/** PAU_REGDMA_LINK_3_ADDR_REG register
+ *  Link_3_addr
+ */
+#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18)
+/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Link_3_addr reg
+ */
+#define PAU_LINK_ADDR_3    0xFFFFFFFFU
+#define PAU_LINK_ADDR_3_M  (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S)
+#define PAU_LINK_ADDR_3_V  0xFFFFFFFFU
+#define PAU_LINK_ADDR_3_S  0
+
+/** PAU_REGDMA_LINK_MAC_ADDR_REG register
+ *  Link_mac_addr
+ */
+#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c)
+/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0;
+ *  Link_mac_addr reg
+ */
+#define PAU_LINK_ADDR_MAC    0xFFFFFFFFU
+#define PAU_LINK_ADDR_MAC_M  (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S)
+#define PAU_LINK_ADDR_MAC_V  0xFFFFFFFFU
+#define PAU_LINK_ADDR_MAC_S  0
+
+/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
+ *  current link addr
+ */
+#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20)
+/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  current link addr reg
+ */
+#define PAU_CURRENT_LINK_ADDR    0xFFFFFFFFU
+#define PAU_CURRENT_LINK_ADDR_M  (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
+#define PAU_CURRENT_LINK_ADDR_V  0xFFFFFFFFU
+#define PAU_CURRENT_LINK_ADDR_S  0
+
+/** PAU_REGDMA_BACKUP_ADDR_REG register
+ *  Backup addr
+ */
+#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24)
+/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  backup addr reg
+ */
+#define PAU_BACKUP_ADDR    0xFFFFFFFFU
+#define PAU_BACKUP_ADDR_M  (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S)
+#define PAU_BACKUP_ADDR_V  0xFFFFFFFFU
+#define PAU_BACKUP_ADDR_S  0
+
+/** PAU_REGDMA_MEM_ADDR_REG register
+ *  mem addr
+ */
+#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28)
+/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  mem addr reg
+ */
+#define PAU_MEM_ADDR    0xFFFFFFFFU
+#define PAU_MEM_ADDR_M  (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
+#define PAU_MEM_ADDR_V  0xFFFFFFFFU
+#define PAU_MEM_ADDR_S  0
+
+/** PAU_REGDMA_BKP_CONF_REG register
+ *  backup config
+ */
+#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c)
+/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32;
+ *  Link read_interval
+ */
+#define PAU_READ_INTERVAL    0x0000007FU
+#define PAU_READ_INTERVAL_M  (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S)
+#define PAU_READ_INTERVAL_V  0x0000007FU
+#define PAU_READ_INTERVAL_S  0
+/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50;
+ *  link wait timeout threshold
+ */
+#define PAU_LINK_TOUT_THRES    0x000003FFU
+#define PAU_LINK_TOUT_THRES_M  (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S)
+#define PAU_LINK_TOUT_THRES_V  0x000003FFU
+#define PAU_LINK_TOUT_THRES_S  7
+/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8;
+ *  burst limit
+ */
+#define PAU_BURST_LIMIT    0x0000001FU
+#define PAU_BURST_LIMIT_M  (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S)
+#define PAU_BURST_LIMIT_V  0x0000001FU
+#define PAU_BURST_LIMIT_S  17
+/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500;
+ *  Backup timeout threshold
+ */
+#define PAU_BACKUP_TOUT_THRES    0x000003FFU
+#define PAU_BACKUP_TOUT_THRES_M  (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S)
+#define PAU_BACKUP_TOUT_THRES_V  0x000003FFU
+#define PAU_BACKUP_TOUT_THRES_S  22
+
+/** PAU_INT_ENA_REG register
+ *  Read only register for error and done
+ */
+#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30)
+/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  backup done flag
+ */
+#define PAU_DONE_INT_ENA    (BIT(0))
+#define PAU_DONE_INT_ENA_M  (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
+#define PAU_DONE_INT_ENA_V  0x00000001U
+#define PAU_DONE_INT_ENA_S  0
+/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  error flag
+ */
+#define PAU_ERROR_INT_ENA    (BIT(1))
+#define PAU_ERROR_INT_ENA_M  (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
+#define PAU_ERROR_INT_ENA_V  0x00000001U
+#define PAU_ERROR_INT_ENA_S  1
+
+/** PAU_INT_RAW_REG register
+ *  Read only register for error and done
+ */
+#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34)
+/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  backup done flag
+ */
+#define PAU_DONE_INT_RAW    (BIT(0))
+#define PAU_DONE_INT_RAW_M  (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
+#define PAU_DONE_INT_RAW_V  0x00000001U
+#define PAU_DONE_INT_RAW_S  0
+/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  error flag
+ */
+#define PAU_ERROR_INT_RAW    (BIT(1))
+#define PAU_ERROR_INT_RAW_M  (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
+#define PAU_ERROR_INT_RAW_V  0x00000001U
+#define PAU_ERROR_INT_RAW_S  1
+
+/** PAU_INT_CLR_REG register
+ *  Read only register for error and done
+ */
+#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38)
+/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  backup done flag
+ */
+#define PAU_DONE_INT_CLR    (BIT(0))
+#define PAU_DONE_INT_CLR_M  (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
+#define PAU_DONE_INT_CLR_V  0x00000001U
+#define PAU_DONE_INT_CLR_S  0
+/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  error flag
+ */
+#define PAU_ERROR_INT_CLR    (BIT(1))
+#define PAU_ERROR_INT_CLR_M  (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
+#define PAU_ERROR_INT_CLR_V  0x00000001U
+#define PAU_ERROR_INT_CLR_S  1
+
+/** PAU_INT_ST_REG register
+ *  Read only register for error and done
+ */
+#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c)
+/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  backup done flag
+ */
+#define PAU_DONE_INT_ST    (BIT(0))
+#define PAU_DONE_INT_ST_M  (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
+#define PAU_DONE_INT_ST_V  0x00000001U
+#define PAU_DONE_INT_ST_S  0
+/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  error flag
+ */
+#define PAU_ERROR_INT_ST    (BIT(1))
+#define PAU_ERROR_INT_ST_M  (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
+#define PAU_ERROR_INT_ST_V  0x00000001U
+#define PAU_ERROR_INT_ST_S  1
+
+/** PAU_DATE_REG register
+ *  Date register.
+ */
+#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
+/** PAU_DATE : R/W; bitpos: [27:0]; default: 36705040;
+ *  REGDMA date information/ REGDMA version information.
+ */
+#define PAU_DATE    0x0FFFFFFFU
+#define PAU_DATE_M  (PAU_DATE_V << PAU_DATE_S)
+#define PAU_DATE_V  0x0FFFFFFFU
+#define PAU_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pau_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pau_struct.h
new file mode 100644
index 0000000000..13b5c39a32
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pau_struct.h
@@ -0,0 +1,339 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of regdma_conf register
+ *  Peri backup control register
+ */
+typedef union {
+    struct {
+        /** flow_err : RO; bitpos: [2:0]; default: 0;
+         *  backup error type
+         */
+        uint32_t flow_err:3;
+        /** start : WT; bitpos: [3]; default: 0;
+         *  backup start signal
+         */
+        uint32_t start:1;
+        /** to_mem : R/W; bitpos: [4]; default: 0;
+         *  backup direction(reg to mem / mem to reg)
+         */
+        uint32_t to_mem:1;
+        /** link_sel : R/W; bitpos: [6:5]; default: 0;
+         *  Link select
+         */
+        uint32_t link_sel:2;
+        /** start_mac : WT; bitpos: [7]; default: 0;
+         *  mac sw backup start signal
+         */
+        uint32_t start_mac:1;
+        /** to_mem_mac : R/W; bitpos: [8]; default: 0;
+         *  mac sw backup direction(reg to mem / mem to reg)
+         */
+        uint32_t to_mem_mac:1;
+        /** sel_mac : R/W; bitpos: [9]; default: 0;
+         *  mac hw/sw select
+         */
+        uint32_t sel_mac:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} pau_regdma_conf_reg_t;
+
+/** Type of regdma_clk_conf register
+ *  Clock control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  clock enable
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} pau_regdma_clk_conf_reg_t;
+
+/** Type of regdma_etm_ctrl register
+ *  ETM start ctrl reg
+ */
+typedef union {
+    struct {
+        /** etm_start_0 : WT; bitpos: [0]; default: 0;
+         *  etm_start_0 reg
+         */
+        uint32_t etm_start_0:1;
+        /** etm_start_1 : WT; bitpos: [1]; default: 0;
+         *  etm_start_1 reg
+         */
+        uint32_t etm_start_1:1;
+        /** etm_start_2 : WT; bitpos: [2]; default: 0;
+         *  etm_start_2 reg
+         */
+        uint32_t etm_start_2:1;
+        /** etm_start_3 : WT; bitpos: [3]; default: 0;
+         *  etm_start_3 reg
+         */
+        uint32_t etm_start_3:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pau_regdma_etm_ctrl_reg_t;
+
+/** Type of regdma_link_0_addr register
+ *  link_0_addr
+ */
+typedef union {
+    struct {
+        /** link_addr_0 : R/W; bitpos: [31:0]; default: 0;
+         *  link_0_addr reg
+         */
+        uint32_t link_addr_0:32;
+    };
+    uint32_t val;
+} pau_regdma_link_0_addr_reg_t;
+
+/** Type of regdma_link_1_addr register
+ *  Link_1_addr
+ */
+typedef union {
+    struct {
+        /** link_addr_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Link_1_addr reg
+         */
+        uint32_t link_addr_1:32;
+    };
+    uint32_t val;
+} pau_regdma_link_1_addr_reg_t;
+
+/** Type of regdma_link_2_addr register
+ *  Link_2_addr
+ */
+typedef union {
+    struct {
+        /** link_addr_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Link_2_addr reg
+         */
+        uint32_t link_addr_2:32;
+    };
+    uint32_t val;
+} pau_regdma_link_2_addr_reg_t;
+
+/** Type of regdma_link_3_addr register
+ *  Link_3_addr
+ */
+typedef union {
+    struct {
+        /** link_addr_3 : R/W; bitpos: [31:0]; default: 0;
+         *  Link_3_addr reg
+         */
+        uint32_t link_addr_3:32;
+    };
+    uint32_t val;
+} pau_regdma_link_3_addr_reg_t;
+
+/** Type of regdma_link_mac_addr register
+ *  Link_mac_addr
+ */
+typedef union {
+    struct {
+        /** link_addr_mac : R/W; bitpos: [31:0]; default: 0;
+         *  Link_mac_addr reg
+         */
+        uint32_t link_addr_mac:32;
+    };
+    uint32_t val;
+} pau_regdma_link_mac_addr_reg_t;
+
+/** Type of regdma_current_link_addr register
+ *  current link addr
+ */
+typedef union {
+    struct {
+        /** current_link_addr : RO; bitpos: [31:0]; default: 0;
+         *  current link addr reg
+         */
+        uint32_t current_link_addr:32;
+    };
+    uint32_t val;
+} pau_regdma_current_link_addr_reg_t;
+
+/** Type of regdma_backup_addr register
+ *  Backup addr
+ */
+typedef union {
+    struct {
+        /** backup_addr : RO; bitpos: [31:0]; default: 0;
+         *  backup addr reg
+         */
+        uint32_t backup_addr:32;
+    };
+    uint32_t val;
+} pau_regdma_backup_addr_reg_t;
+
+/** Type of regdma_mem_addr register
+ *  mem addr
+ */
+typedef union {
+    struct {
+        /** mem_addr : RO; bitpos: [31:0]; default: 0;
+         *  mem addr reg
+         */
+        uint32_t mem_addr:32;
+    };
+    uint32_t val;
+} pau_regdma_mem_addr_reg_t;
+
+/** Type of regdma_bkp_conf register
+ *  backup config
+ */
+typedef union {
+    struct {
+        /** read_interval : R/W; bitpos: [6:0]; default: 32;
+         *  Link read_interval
+         */
+        uint32_t read_interval:7;
+        /** link_tout_thres : R/W; bitpos: [16:7]; default: 50;
+         *  link wait timeout threshold
+         */
+        uint32_t link_tout_thres:10;
+        /** burst_limit : R/W; bitpos: [21:17]; default: 8;
+         *  burst limit
+         */
+        uint32_t burst_limit:5;
+        /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500;
+         *  Backup timeout threshold
+         */
+        uint32_t backup_tout_thres:10;
+    };
+    uint32_t val;
+} pau_regdma_bkp_conf_reg_t;
+
+/** Type of int_ena register
+ *  Read only register for error and done
+ */
+typedef union {
+    struct {
+        /** done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  backup done flag
+         */
+        uint32_t done_int_ena:1;
+        /** error_int_ena : R/W; bitpos: [1]; default: 0;
+         *  error flag
+         */
+        uint32_t error_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pau_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Read only register for error and done
+ */
+typedef union {
+    struct {
+        /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  backup done flag
+         */
+        uint32_t done_int_raw:1;
+        /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  error flag
+         */
+        uint32_t error_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pau_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Read only register for error and done
+ */
+typedef union {
+    struct {
+        /** done_int_clr : WT; bitpos: [0]; default: 0;
+         *  backup done flag
+         */
+        uint32_t done_int_clr:1;
+        /** error_int_clr : WT; bitpos: [1]; default: 0;
+         *  error flag
+         */
+        uint32_t error_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pau_int_clr_reg_t;
+
+/** Type of int_st register
+ *  Read only register for error and done
+ */
+typedef union {
+    struct {
+        /** done_int_st : RO; bitpos: [0]; default: 0;
+         *  backup done flag
+         */
+        uint32_t done_int_st:1;
+        /** error_int_st : RO; bitpos: [1]; default: 0;
+         *  error flag
+         */
+        uint32_t error_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pau_int_st_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36705040;
+         *  REGDMA date information/ REGDMA version information.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} pau_date_reg_t;
+
+
+typedef struct {
+    volatile pau_regdma_conf_reg_t regdma_conf;
+    volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
+    volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;
+    volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr;
+    volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr;
+    volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr;
+    volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr;
+    volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr;
+    volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr;
+    volatile pau_regdma_backup_addr_reg_t regdma_backup_addr;
+    volatile pau_regdma_mem_addr_reg_t regdma_mem_addr;
+    volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf;
+    volatile pau_int_ena_reg_t int_ena;
+    volatile pau_int_raw_reg_t int_raw;
+    volatile pau_int_clr_reg_t int_clr;
+    volatile pau_int_st_reg_t int_st;
+    uint32_t reserved_040[239];
+    volatile pau_date_reg_t date;
+} pau_dev_t;
+
+extern pau_dev_t PAU;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pcnt_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pcnt_eco5_struct.h
new file mode 100644
index 0000000000..ada36b8ff1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pcnt_eco5_struct.h
@@ -0,0 +1,504 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of un_conf0 register
+ *  Configuration register 0 for unit n
+ */
+typedef union {
+    struct {
+        /** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
+         *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+         *
+         *  Any pulses with width less than this will be ignored when the filter is enabled.
+         */
+        uint32_t filter_thres_un:10;
+        /** filter_en_un : R/W; bitpos: [10]; default: 1;
+         *  This is the enable bit for unit n's input filter.
+         */
+        uint32_t filter_en_un:1;
+        /** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
+         *  This is the enable bit for unit n's zero comparator.
+         */
+        uint32_t thr_zero_en_un:1;
+        /** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
+         *  This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
+         *  the high limit interrupt.
+         */
+        uint32_t thr_h_lim_en_un:1;
+        /** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
+         *  This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
+         *  the low limit interrupt.
+         */
+        uint32_t thr_l_lim_en_un:1;
+        /** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for unit n's thres0 comparator.
+         */
+        uint32_t thr_thres0_en_un:1;
+        /** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for unit n's thres1 comparator.
+         */
+        uint32_t thr_thres1_en_un:1;
+        /** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  negative edge.
+         *
+         *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+         */
+        uint32_t ch0_neg_mode_un:2;
+        /** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  positive edge.
+         *
+         *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+         */
+        uint32_t ch0_pos_mode_un:2;
+        /** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_hctrl_mode_un:2;
+        /** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_lctrl_mode_un:2;
+        /** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  negative edge.
+         *
+         *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+         */
+        uint32_t ch1_neg_mode_un:2;
+        /** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  positive edge.
+         *
+         *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+         */
+        uint32_t ch1_pos_mode_un:2;
+        /** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_hctrl_mode_un:2;
+        /** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_lctrl_mode_un:2;
+    };
+    uint32_t val;
+} pcnt_un_conf0_reg_t;
+
+/** Type of un_conf1 register
+ *  Configuration register 1 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thres0 value for unit n.
+         */
+        uint32_t cnt_thres0_un:16;
+        /** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thres1 value for unit n.
+         */
+        uint32_t cnt_thres1_un:16;
+    };
+    uint32_t val;
+} pcnt_un_conf1_reg_t;
+
+/** Type of un_conf2 register
+ *  Configuration register 2 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thr_h_lim value for unit n. When pcnt
+         *  reaches this value, the counter will be cleared to 0.
+         */
+        uint32_t cnt_h_lim_un:16;
+        /** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thr_l_lim value for unit n. When pcnt
+         *  reaches this value, the counter will be cleared to 0.
+         */
+        uint32_t cnt_l_lim_un:16;
+    };
+    uint32_t val;
+} pcnt_un_conf2_reg_t;
+
+/** Type of ctrl register
+ *  Control register for all counters
+ */
+typedef union {
+    struct {
+        /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to clear unit 0's counter.
+         */
+        uint32_t pulse_cnt_rst_u0:1;
+        /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to freeze unit 0's counter.
+         */
+        uint32_t cnt_pause_u0:1;
+        /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to clear unit 1's counter.
+         */
+        uint32_t pulse_cnt_rst_u1:1;
+        /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to freeze unit 1's counter.
+         */
+        uint32_t cnt_pause_u1:1;
+        /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to clear unit 2's counter.
+         */
+        uint32_t pulse_cnt_rst_u2:1;
+        /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to freeze unit 2's counter.
+         */
+        uint32_t cnt_pause_u2:1;
+        /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
+         *  Set this bit to clear unit 3's counter.
+         */
+        uint32_t pulse_cnt_rst_u3:1;
+        /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to freeze unit 3's counter.
+         */
+        uint32_t cnt_pause_u3:1;
+        /** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0;
+         *  Configures this bit to enable unit 0's step comparator.
+         */
+        uint32_t dalta_change_en_u0:1;
+        /** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0;
+         *  Configures this bit to enable unit 1's step comparator.
+         */
+        uint32_t dalta_change_en_u1:1;
+        /** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0;
+         *  Configures this bit to enable unit 2's step comparator.
+         */
+        uint32_t dalta_change_en_u2:1;
+        /** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0;
+         *  Configures this bit to enable unit 3's step comparator.
+         */
+        uint32_t dalta_change_en_u3:1;
+        uint32_t reserved_12:4;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
+         *  and written by application. 0: the registers can not be read or written by
+         *  application
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pcnt_ctrl_reg_t;
+
+/** Type of u3_change_conf register
+ *  Configuration register for unit $n's step value.
+ */
+typedef union {
+    struct {
+        /** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the step value for unit 3.
+         */
+        uint32_t cnt_step_u3:16;
+        /** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0;
+         *  Configures the step limit value for unit 3.
+         */
+        uint32_t cnt_step_lim_u3:16;
+    };
+    uint32_t val;
+} pcnt_u3_change_conf_reg_t;
+
+/** Type of u2_change_conf register
+ *  Configuration register for unit $n's step value.
+ */
+typedef union {
+    struct {
+        /** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the step value for unit 2.
+         */
+        uint32_t cnt_step_u2:16;
+        /** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0;
+         *  Configures the step limit value for unit 2.
+         */
+        uint32_t cnt_step_lim_u2:16;
+    };
+    uint32_t val;
+} pcnt_u2_change_conf_reg_t;
+
+/** Type of u1_change_conf register
+ *  Configuration register for unit $n's step value.
+ */
+typedef union {
+    struct {
+        /** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the step value for unit 1.
+         */
+        uint32_t cnt_step_u1:16;
+        /** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0;
+         *  Configures the step limit value for unit 1.
+         */
+        uint32_t cnt_step_lim_u1:16;
+    };
+    uint32_t val;
+} pcnt_u1_change_conf_reg_t;
+
+/** Type of u0_change_conf register
+ *  Configuration register for unit $n's step value.
+ */
+typedef union {
+    struct {
+        /** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the step value for unit 0.
+         */
+        uint32_t cnt_step_u0:16;
+        /** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0;
+         *  Configures the step limit value for unit 0.
+         */
+        uint32_t cnt_step_lim_u0:16;
+    };
+    uint32_t val;
+} pcnt_u0_change_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of un_cnt register
+ *  Counter value for unit n
+ */
+typedef union {
+    struct {
+        /** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
+         *  This register stores the current pulse count value for unit n.
+         */
+        uint32_t pulse_cnt_un:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} pcnt_un_cnt_reg_t;
+
+/** Type of un_status register
+ *  PNCT UNITn status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
+         *  The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases
+         *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+         *  is negative. 3: pulse counter is positive.
+         */
+        uint32_t cnt_thr_zero_mode_un:2;
+        /** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
+         *  The latched value of thres1 event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres1_lat_un:1;
+        /** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
+         *  The latched value of thres0 event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres0_lat_un:1;
+        /** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
+         *  The latched value of low limit event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_l_lim_lat_un:1;
+        /** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
+         *  The latched value of high limit event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_h_lim_lat_un:1;
+        /** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
+         *  The latched value of zero threshold event of PCNT_Un when threshold event interrupt
+         *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_zero_lat_un:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} pcnt_un_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_raw:1;
+        /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_raw:1;
+        /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_raw:1;
+        /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_st:1;
+        /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_st:1;
+        /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_st:1;
+        /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_ena:1;
+        /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_ena:1;
+        /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_ena:1;
+        /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_clr:1;
+        /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_clr:1;
+        /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_clr:1;
+        /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  PCNT version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35721985;
+         *  This is the PCNT version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} pcnt_date_reg_t;
+
+
+typedef struct {
+    volatile pcnt_un_conf0_reg_t u0_conf0;
+    volatile pcnt_un_conf1_reg_t u0_conf1;
+    volatile pcnt_un_conf2_reg_t u0_conf2;
+    volatile pcnt_un_conf0_reg_t u1_conf0;
+    volatile pcnt_un_conf1_reg_t u1_conf1;
+    volatile pcnt_un_conf2_reg_t u1_conf2;
+    volatile pcnt_un_conf0_reg_t u2_conf0;
+    volatile pcnt_un_conf1_reg_t u2_conf1;
+    volatile pcnt_un_conf2_reg_t u2_conf2;
+    volatile pcnt_un_conf0_reg_t u3_conf0;
+    volatile pcnt_un_conf1_reg_t u3_conf1;
+    volatile pcnt_un_conf2_reg_t u3_conf2;
+    volatile pcnt_un_cnt_reg_t un_cnt[4];
+    volatile pcnt_int_raw_reg_t int_raw;
+    volatile pcnt_int_st_reg_t int_st;
+    volatile pcnt_int_ena_reg_t int_ena;
+    volatile pcnt_int_clr_reg_t int_clr;
+    volatile pcnt_un_status_reg_t un_status[4];
+    volatile pcnt_ctrl_reg_t ctrl;
+    volatile pcnt_u3_change_conf_reg_t u3_change_conf;
+    volatile pcnt_u2_change_conf_reg_t u2_change_conf;
+    volatile pcnt_u1_change_conf_reg_t u1_change_conf;
+    volatile pcnt_u0_change_conf_reg_t u0_change_conf;
+    uint32_t reserved_074[34];
+    volatile pcnt_date_reg_t date;
+} pcnt_dev_t;
+
+extern pcnt_dev_t PCNT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pcnt_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/pcnt_reg.h
new file mode 100644
index 0000000000..a15eac4f18
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pcnt_reg.h
@@ -0,0 +1,1346 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PCNT_U0_CONF0_REG register
+ *  Configuration register 0 for unit 0
+ */
+#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0)
+/** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U0    0x000003FFU
+#define PCNT_FILTER_THRES_U0_M  (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S)
+#define PCNT_FILTER_THRES_U0_V  0x000003FFU
+#define PCNT_FILTER_THRES_U0_S  0
+/** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 0's input filter.
+ */
+#define PCNT_FILTER_EN_U0    (BIT(10))
+#define PCNT_FILTER_EN_U0_M  (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S)
+#define PCNT_FILTER_EN_U0_V  0x00000001U
+#define PCNT_FILTER_EN_U0_S  10
+/** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 0's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U0    (BIT(11))
+#define PCNT_THR_ZERO_EN_U0_M  (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S)
+#define PCNT_THR_ZERO_EN_U0_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U0_S  11
+/** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 0's thr_h_lim comparator. Configures it to enable
+ *  the high limit interrupt.
+ */
+#define PCNT_THR_H_LIM_EN_U0    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U0_M  (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S)
+#define PCNT_THR_H_LIM_EN_U0_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U0_S  12
+/** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 0's thr_l_lim comparator. Configures it to enable
+ *  the low limit interrupt.
+ */
+#define PCNT_THR_L_LIM_EN_U0    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U0_M  (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S)
+#define PCNT_THR_L_LIM_EN_U0_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U0_S  13
+/** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 0's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U0    (BIT(14))
+#define PCNT_THR_THRES0_EN_U0_M  (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S)
+#define PCNT_THR_THRES0_EN_U0_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U0_S  14
+/** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 0's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U0    (BIT(15))
+#define PCNT_THR_THRES1_EN_U0_M  (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S)
+#define PCNT_THR_THRES1_EN_U0_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U0_S  15
+/** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U0    0x00000003U
+#define PCNT_CH0_NEG_MODE_U0_M  (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S)
+#define PCNT_CH0_NEG_MODE_U0_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U0_S  16
+/** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U0    0x00000003U
+#define PCNT_CH0_POS_MODE_U0_M  (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S)
+#define PCNT_CH0_POS_MODE_U0_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U0_S  18
+/** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U0    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U0_M  (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S)
+#define PCNT_CH0_HCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U0_S  20
+/** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U0    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U0_M  (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S)
+#define PCNT_CH0_LCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U0_S  22
+/** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U0    0x00000003U
+#define PCNT_CH1_NEG_MODE_U0_M  (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S)
+#define PCNT_CH1_NEG_MODE_U0_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U0_S  24
+/** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U0    0x00000003U
+#define PCNT_CH1_POS_MODE_U0_M  (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S)
+#define PCNT_CH1_POS_MODE_U0_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U0_S  26
+/** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U0    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U0_M  (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S)
+#define PCNT_CH1_HCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U0_S  28
+/** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U0    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U0_M  (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S)
+#define PCNT_CH1_LCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U0_S  30
+
+/** PCNT_U0_CONF1_REG register
+ *  Configuration register 1 for unit 0
+ */
+#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4)
+/** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 0.
+ */
+#define PCNT_CNT_THRES0_U0    0x0000FFFFU
+#define PCNT_CNT_THRES0_U0_M  (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S)
+#define PCNT_CNT_THRES0_U0_V  0x0000FFFFU
+#define PCNT_CNT_THRES0_U0_S  0
+/** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 0.
+ */
+#define PCNT_CNT_THRES1_U0    0x0000FFFFU
+#define PCNT_CNT_THRES1_U0_M  (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S)
+#define PCNT_CNT_THRES1_U0_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U0_S  16
+
+/** PCNT_U0_CONF2_REG register
+ *  Configuration register 2 for unit 0
+ */
+#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8)
+/** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 0. When pcnt
+ *  reaches this value, the counter will be cleared to 0.
+ */
+#define PCNT_CNT_H_LIM_U0    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U0_M  (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S)
+#define PCNT_CNT_H_LIM_U0_V  0x0000FFFFU
+#define PCNT_CNT_H_LIM_U0_S  0
+/** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 0. When pcnt
+ *  reaches this value, the counter will be cleared to 0.
+ */
+#define PCNT_CNT_L_LIM_U0    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U0_M  (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S)
+#define PCNT_CNT_L_LIM_U0_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U0_S  16
+
+/** PCNT_U1_CONF0_REG register
+ *  Configuration register 0 for unit 1
+ */
+#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xc)
+/** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U1    0x000003FFU
+#define PCNT_FILTER_THRES_U1_M  (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S)
+#define PCNT_FILTER_THRES_U1_V  0x000003FFU
+#define PCNT_FILTER_THRES_U1_S  0
+/** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 1's input filter.
+ */
+#define PCNT_FILTER_EN_U1    (BIT(10))
+#define PCNT_FILTER_EN_U1_M  (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S)
+#define PCNT_FILTER_EN_U1_V  0x00000001U
+#define PCNT_FILTER_EN_U1_S  10
+/** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 1's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U1    (BIT(11))
+#define PCNT_THR_ZERO_EN_U1_M  (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S)
+#define PCNT_THR_ZERO_EN_U1_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U1_S  11
+/** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 1's thr_h_lim comparator. Configures it to enable
+ *  the high limit interrupt.
+ */
+#define PCNT_THR_H_LIM_EN_U1    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U1_M  (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S)
+#define PCNT_THR_H_LIM_EN_U1_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U1_S  12
+/** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 1's thr_l_lim comparator. Configures it to enable
+ *  the low limit interrupt.
+ */
+#define PCNT_THR_L_LIM_EN_U1    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U1_M  (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S)
+#define PCNT_THR_L_LIM_EN_U1_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U1_S  13
+/** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 1's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U1    (BIT(14))
+#define PCNT_THR_THRES0_EN_U1_M  (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S)
+#define PCNT_THR_THRES0_EN_U1_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U1_S  14
+/** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 1's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U1    (BIT(15))
+#define PCNT_THR_THRES1_EN_U1_M  (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S)
+#define PCNT_THR_THRES1_EN_U1_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U1_S  15
+/** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U1    0x00000003U
+#define PCNT_CH0_NEG_MODE_U1_M  (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S)
+#define PCNT_CH0_NEG_MODE_U1_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U1_S  16
+/** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U1    0x00000003U
+#define PCNT_CH0_POS_MODE_U1_M  (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S)
+#define PCNT_CH0_POS_MODE_U1_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U1_S  18
+/** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U1    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U1_M  (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S)
+#define PCNT_CH0_HCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U1_S  20
+/** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U1    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U1_M  (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S)
+#define PCNT_CH0_LCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U1_S  22
+/** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U1    0x00000003U
+#define PCNT_CH1_NEG_MODE_U1_M  (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S)
+#define PCNT_CH1_NEG_MODE_U1_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U1_S  24
+/** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U1    0x00000003U
+#define PCNT_CH1_POS_MODE_U1_M  (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S)
+#define PCNT_CH1_POS_MODE_U1_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U1_S  26
+/** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U1    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U1_M  (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S)
+#define PCNT_CH1_HCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U1_S  28
+/** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U1    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U1_M  (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S)
+#define PCNT_CH1_LCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U1_S  30
+
+/** PCNT_U1_CONF1_REG register
+ *  Configuration register 1 for unit 1
+ */
+#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10)
+/** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 1.
+ */
+#define PCNT_CNT_THRES0_U1    0x0000FFFFU
+#define PCNT_CNT_THRES0_U1_M  (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S)
+#define PCNT_CNT_THRES0_U1_V  0x0000FFFFU
+#define PCNT_CNT_THRES0_U1_S  0
+/** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 1.
+ */
+#define PCNT_CNT_THRES1_U1    0x0000FFFFU
+#define PCNT_CNT_THRES1_U1_M  (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S)
+#define PCNT_CNT_THRES1_U1_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U1_S  16
+
+/** PCNT_U1_CONF2_REG register
+ *  Configuration register 2 for unit 1
+ */
+#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14)
+/** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 1. When pcnt
+ *  reaches this value, the counter will be cleared to 0.
+ */
+#define PCNT_CNT_H_LIM_U1    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U1_M  (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S)
+#define PCNT_CNT_H_LIM_U1_V  0x0000FFFFU
+#define PCNT_CNT_H_LIM_U1_S  0
+/** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 1. When pcnt
+ *  reaches this value, the counter will be cleared to 0.
+ */
+#define PCNT_CNT_L_LIM_U1    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U1_M  (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S)
+#define PCNT_CNT_L_LIM_U1_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U1_S  16
+
+/** PCNT_U2_CONF0_REG register
+ *  Configuration register 0 for unit 2
+ */
+#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18)
+/** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U2    0x000003FFU
+#define PCNT_FILTER_THRES_U2_M  (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S)
+#define PCNT_FILTER_THRES_U2_V  0x000003FFU
+#define PCNT_FILTER_THRES_U2_S  0
+/** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 2's input filter.
+ */
+#define PCNT_FILTER_EN_U2    (BIT(10))
+#define PCNT_FILTER_EN_U2_M  (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S)
+#define PCNT_FILTER_EN_U2_V  0x00000001U
+#define PCNT_FILTER_EN_U2_S  10
+/** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 2's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U2    (BIT(11))
+#define PCNT_THR_ZERO_EN_U2_M  (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S)
+#define PCNT_THR_ZERO_EN_U2_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U2_S  11
+/** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 2's thr_h_lim comparator. Configures it to enable
+ *  the high limit interrupt.
+ */
+#define PCNT_THR_H_LIM_EN_U2    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U2_M  (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S)
+#define PCNT_THR_H_LIM_EN_U2_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U2_S  12
+/** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 2's thr_l_lim comparator. Configures it to enable
+ *  the low limit interrupt.
+ */
+#define PCNT_THR_L_LIM_EN_U2    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U2_M  (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S)
+#define PCNT_THR_L_LIM_EN_U2_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U2_S  13
+/** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 2's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U2    (BIT(14))
+#define PCNT_THR_THRES0_EN_U2_M  (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S)
+#define PCNT_THR_THRES0_EN_U2_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U2_S  14
+/** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 2's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U2    (BIT(15))
+#define PCNT_THR_THRES1_EN_U2_M  (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S)
+#define PCNT_THR_THRES1_EN_U2_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U2_S  15
+/** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U2    0x00000003U
+#define PCNT_CH0_NEG_MODE_U2_M  (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S)
+#define PCNT_CH0_NEG_MODE_U2_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U2_S  16
+/** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U2    0x00000003U
+#define PCNT_CH0_POS_MODE_U2_M  (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S)
+#define PCNT_CH0_POS_MODE_U2_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U2_S  18
+/** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U2    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U2_M  (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S)
+#define PCNT_CH0_HCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U2_S  20
+/** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U2    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U2_M  (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S)
+#define PCNT_CH0_LCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U2_S  22
+/** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U2    0x00000003U
+#define PCNT_CH1_NEG_MODE_U2_M  (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S)
+#define PCNT_CH1_NEG_MODE_U2_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U2_S  24
+/** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U2    0x00000003U
+#define PCNT_CH1_POS_MODE_U2_M  (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S)
+#define PCNT_CH1_POS_MODE_U2_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U2_S  26
+/** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U2    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U2_M  (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S)
+#define PCNT_CH1_HCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U2_S  28
+/** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U2    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U2_M  (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S)
+#define PCNT_CH1_LCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U2_S  30
+
+/** PCNT_U2_CONF1_REG register
+ *  Configuration register 1 for unit 2
+ */
+#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1c)
+/** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 2.
+ */
+#define PCNT_CNT_THRES0_U2    0x0000FFFFU
+#define PCNT_CNT_THRES0_U2_M  (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S)
+#define PCNT_CNT_THRES0_U2_V  0x0000FFFFU
+#define PCNT_CNT_THRES0_U2_S  0
+/** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 2.
+ */
+#define PCNT_CNT_THRES1_U2    0x0000FFFFU
+#define PCNT_CNT_THRES1_U2_M  (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S)
+#define PCNT_CNT_THRES1_U2_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U2_S  16
+
+/** PCNT_U2_CONF2_REG register
+ *  Configuration register 2 for unit 2
+ */
+#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20)
+/** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 2. When pcnt
+ *  reaches this value, the counter will be cleared to 0.
+ */
+#define PCNT_CNT_H_LIM_U2    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U2_M  (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S)
+#define PCNT_CNT_H_LIM_U2_V  0x0000FFFFU
+#define PCNT_CNT_H_LIM_U2_S  0
+/** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 2. When pcnt
+ *  reaches this value, the counter will be cleared to 0.
+ */
+#define PCNT_CNT_L_LIM_U2    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U2_M  (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S)
+#define PCNT_CNT_L_LIM_U2_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U2_S  16
+
+/** PCNT_U3_CONF0_REG register
+ *  Configuration register 0 for unit 3
+ */
+#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24)
+/** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U3    0x000003FFU
+#define PCNT_FILTER_THRES_U3_M  (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S)
+#define PCNT_FILTER_THRES_U3_V  0x000003FFU
+#define PCNT_FILTER_THRES_U3_S  0
+/** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 3's input filter.
+ */
+#define PCNT_FILTER_EN_U3    (BIT(10))
+#define PCNT_FILTER_EN_U3_M  (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S)
+#define PCNT_FILTER_EN_U3_V  0x00000001U
+#define PCNT_FILTER_EN_U3_S  10
+/** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 3's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U3    (BIT(11))
+#define PCNT_THR_ZERO_EN_U3_M  (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S)
+#define PCNT_THR_ZERO_EN_U3_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U3_S  11
+/** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 3's thr_h_lim comparator. Configures it to enable
+ *  the high limit interrupt.
+ */
+#define PCNT_THR_H_LIM_EN_U3    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U3_M  (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S)
+#define PCNT_THR_H_LIM_EN_U3_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U3_S  12
+/** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 3's thr_l_lim comparator. Configures it to enable
+ *  the low limit interrupt.
+ */
+#define PCNT_THR_L_LIM_EN_U3    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U3_M  (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S)
+#define PCNT_THR_L_LIM_EN_U3_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U3_S  13
+/** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 3's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U3    (BIT(14))
+#define PCNT_THR_THRES0_EN_U3_M  (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S)
+#define PCNT_THR_THRES0_EN_U3_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U3_S  14
+/** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 3's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U3    (BIT(15))
+#define PCNT_THR_THRES1_EN_U3_M  (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S)
+#define PCNT_THR_THRES1_EN_U3_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U3_S  15
+/** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U3    0x00000003U
+#define PCNT_CH0_NEG_MODE_U3_M  (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S)
+#define PCNT_CH0_NEG_MODE_U3_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U3_S  16
+/** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U3    0x00000003U
+#define PCNT_CH0_POS_MODE_U3_M  (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S)
+#define PCNT_CH0_POS_MODE_U3_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U3_S  18
+/** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U3    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U3_M  (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S)
+#define PCNT_CH0_HCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U3_S  20
+/** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U3    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U3_M  (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S)
+#define PCNT_CH0_LCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U3_S  22
+/** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U3    0x00000003U
+#define PCNT_CH1_NEG_MODE_U3_M  (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S)
+#define PCNT_CH1_NEG_MODE_U3_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U3_S  24
+/** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U3    0x00000003U
+#define PCNT_CH1_POS_MODE_U3_M  (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S)
+#define PCNT_CH1_POS_MODE_U3_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U3_S  26
+/** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U3    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U3_M  (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S)
+#define PCNT_CH1_HCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U3_S  28
+/** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+ *  increase).2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U3    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U3_M  (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S)
+#define PCNT_CH1_LCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U3_S  30
+
+/** PCNT_U3_CONF1_REG register
+ *  Configuration register 1 for unit 3
+ */
+#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28)
+/** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 3.
+ */
+#define PCNT_CNT_THRES0_U3    0x0000FFFFU
+#define PCNT_CNT_THRES0_U3_M  (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S)
+#define PCNT_CNT_THRES0_U3_V  0x0000FFFFU
+#define PCNT_CNT_THRES0_U3_S  0
+/** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 3.
+ */
+#define PCNT_CNT_THRES1_U3    0x0000FFFFU
+#define PCNT_CNT_THRES1_U3_M  (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S)
+#define PCNT_CNT_THRES1_U3_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U3_S  16
+
+/** PCNT_U3_CONF2_REG register
+ *  Configuration register 2 for unit 3
+ */
+#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2c)
+/** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 3. When pcnt
+ *  reaches this value, the counter will be cleared to 0.
+ */
+#define PCNT_CNT_H_LIM_U3    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U3_M  (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S)
+#define PCNT_CNT_H_LIM_U3_V  0x0000FFFFU
+#define PCNT_CNT_H_LIM_U3_S  0
+/** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 3. When pcnt
+ *  reaches this value, the counter will be cleared to 0.
+ */
+#define PCNT_CNT_L_LIM_U3    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U3_M  (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S)
+#define PCNT_CNT_L_LIM_U3_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U3_S  16
+
+/** PCNT_U0_CNT_REG register
+ *  Counter value for unit 0
+ */
+#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30)
+/** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 0.
+ */
+#define PCNT_PULSE_CNT_U0    0x0000FFFFU
+#define PCNT_PULSE_CNT_U0_M  (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S)
+#define PCNT_PULSE_CNT_U0_V  0x0000FFFFU
+#define PCNT_PULSE_CNT_U0_S  0
+
+/** PCNT_U1_CNT_REG register
+ *  Counter value for unit 1
+ */
+#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34)
+/** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 1.
+ */
+#define PCNT_PULSE_CNT_U1    0x0000FFFFU
+#define PCNT_PULSE_CNT_U1_M  (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S)
+#define PCNT_PULSE_CNT_U1_V  0x0000FFFFU
+#define PCNT_PULSE_CNT_U1_S  0
+
+/** PCNT_U2_CNT_REG register
+ *  Counter value for unit 2
+ */
+#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38)
+/** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 2.
+ */
+#define PCNT_PULSE_CNT_U2    0x0000FFFFU
+#define PCNT_PULSE_CNT_U2_M  (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S)
+#define PCNT_PULSE_CNT_U2_V  0x0000FFFFU
+#define PCNT_PULSE_CNT_U2_S  0
+
+/** PCNT_U3_CNT_REG register
+ *  Counter value for unit 3
+ */
+#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3c)
+/** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 3.
+ */
+#define PCNT_PULSE_CNT_U3    0x0000FFFFU
+#define PCNT_PULSE_CNT_U3_M  (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S)
+#define PCNT_PULSE_CNT_U3_V  0x0000FFFFU
+#define PCNT_PULSE_CNT_U3_S  0
+
+/** PCNT_INT_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40)
+/** PCNT_CNT_THR_EVENT_U0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW    (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M  (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M  (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M  (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M  (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S  3
+
+/** PCNT_INT_ST_REG register
+ *  Interrupt status register
+ */
+#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44)
+/** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U0_INT_ST    (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_M  (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_ST    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_M  (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_ST    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_M  (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_ST    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_M  (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_S  3
+
+/** PCNT_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48)
+/** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA    (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M  (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M  (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M  (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M  (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S  3
+
+/** PCNT_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4c)
+/** PCNT_CNT_THR_EVENT_U0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR    (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M  (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M  (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M  (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M  (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S  3
+
+/** PCNT_U0_STATUS_REG register
+ *  PNCT UNIT0 status register
+ */
+#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50)
+/** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U0 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U0    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U0_M  (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S)
+#define PCNT_CNT_THR_ZERO_MODE_U0_V  0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U0_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES1_LAT_U0    (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U0_M  (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S)
+#define PCNT_CNT_THR_THRES1_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_THRES1_LAT_U0_S  2
+/** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U0    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U0_M  (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S)
+#define PCNT_CNT_THR_THRES0_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U0_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U0    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U0_M  (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U0_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U0    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U0_M  (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U0_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U0 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U0    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U0_M  (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S)
+#define PCNT_CNT_THR_ZERO_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U0_S  6
+
+/** PCNT_U1_STATUS_REG register
+ *  PNCT UNIT1 status register
+ */
+#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54)
+/** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U1 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U1    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U1_M  (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S)
+#define PCNT_CNT_THR_ZERO_MODE_U1_V  0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U1_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES1_LAT_U1    (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U1_M  (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S)
+#define PCNT_CNT_THR_THRES1_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_THRES1_LAT_U1_S  2
+/** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U1    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U1_M  (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S)
+#define PCNT_CNT_THR_THRES0_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U1_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U1    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U1_M  (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U1_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U1    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U1_M  (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U1_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U1 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U1    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U1_M  (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S)
+#define PCNT_CNT_THR_ZERO_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U1_S  6
+
+/** PCNT_U2_STATUS_REG register
+ *  PNCT UNIT2 status register
+ */
+#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58)
+/** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U2 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U2    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U2_M  (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S)
+#define PCNT_CNT_THR_ZERO_MODE_U2_V  0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U2_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES1_LAT_U2    (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U2_M  (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S)
+#define PCNT_CNT_THR_THRES1_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_THRES1_LAT_U2_S  2
+/** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U2    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U2_M  (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S)
+#define PCNT_CNT_THR_THRES0_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U2_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U2    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U2_M  (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U2_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U2    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U2_M  (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U2_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U2 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U2    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U2_M  (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S)
+#define PCNT_CNT_THR_ZERO_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U2_S  6
+
+/** PCNT_U3_STATUS_REG register
+ *  PNCT UNIT3 status register
+ */
+#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5c)
+/** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U3 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U3    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U3_M  (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S)
+#define PCNT_CNT_THR_ZERO_MODE_U3_V  0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U3_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES1_LAT_U3    (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U3_M  (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S)
+#define PCNT_CNT_THR_THRES1_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_THRES1_LAT_U3_S  2
+/** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U3    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U3_M  (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S)
+#define PCNT_CNT_THR_THRES0_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U3_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U3    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U3_M  (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U3_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U3    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U3_M  (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U3_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U3 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U3    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U3_M  (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S)
+#define PCNT_CNT_THR_ZERO_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U3_S  6
+
+/** PCNT_CTRL_REG register
+ *  Control register for all counters
+ */
+#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60)
+/** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to clear unit 0's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U0    (BIT(0))
+#define PCNT_PULSE_CNT_RST_U0_M  (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S)
+#define PCNT_PULSE_CNT_RST_U0_V  0x00000001U
+#define PCNT_PULSE_CNT_RST_U0_S  0
+/** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to freeze unit 0's counter.
+ */
+#define PCNT_CNT_PAUSE_U0    (BIT(1))
+#define PCNT_CNT_PAUSE_U0_M  (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S)
+#define PCNT_CNT_PAUSE_U0_V  0x00000001U
+#define PCNT_CNT_PAUSE_U0_S  1
+/** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to clear unit 1's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U1    (BIT(2))
+#define PCNT_PULSE_CNT_RST_U1_M  (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S)
+#define PCNT_PULSE_CNT_RST_U1_V  0x00000001U
+#define PCNT_PULSE_CNT_RST_U1_S  2
+/** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to freeze unit 1's counter.
+ */
+#define PCNT_CNT_PAUSE_U1    (BIT(3))
+#define PCNT_CNT_PAUSE_U1_M  (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S)
+#define PCNT_CNT_PAUSE_U1_V  0x00000001U
+#define PCNT_CNT_PAUSE_U1_S  3
+/** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to clear unit 2's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U2    (BIT(4))
+#define PCNT_PULSE_CNT_RST_U2_M  (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S)
+#define PCNT_PULSE_CNT_RST_U2_V  0x00000001U
+#define PCNT_PULSE_CNT_RST_U2_S  4
+/** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to freeze unit 2's counter.
+ */
+#define PCNT_CNT_PAUSE_U2    (BIT(5))
+#define PCNT_CNT_PAUSE_U2_M  (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S)
+#define PCNT_CNT_PAUSE_U2_V  0x00000001U
+#define PCNT_CNT_PAUSE_U2_S  5
+/** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1;
+ *  Set this bit to clear unit 3's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U3    (BIT(6))
+#define PCNT_PULSE_CNT_RST_U3_M  (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S)
+#define PCNT_PULSE_CNT_RST_U3_V  0x00000001U
+#define PCNT_PULSE_CNT_RST_U3_S  6
+/** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to freeze unit 3's counter.
+ */
+#define PCNT_CNT_PAUSE_U3    (BIT(7))
+#define PCNT_CNT_PAUSE_U3_M  (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S)
+#define PCNT_CNT_PAUSE_U3_V  0x00000001U
+#define PCNT_CNT_PAUSE_U3_S  7
+/** PCNT_DALTA_CHANGE_EN_U0 : R/W; bitpos: [8]; default: 0;
+ *  Configures this bit to enable unit 0's step comparator.
+ */
+#define PCNT_DALTA_CHANGE_EN_U0    (BIT(8))
+#define PCNT_DALTA_CHANGE_EN_U0_M  (PCNT_DALTA_CHANGE_EN_U0_V << PCNT_DALTA_CHANGE_EN_U0_S)
+#define PCNT_DALTA_CHANGE_EN_U0_V  0x00000001U
+#define PCNT_DALTA_CHANGE_EN_U0_S  8
+/** PCNT_DALTA_CHANGE_EN_U1 : R/W; bitpos: [9]; default: 0;
+ *  Configures this bit to enable unit 1's step comparator.
+ */
+#define PCNT_DALTA_CHANGE_EN_U1    (BIT(9))
+#define PCNT_DALTA_CHANGE_EN_U1_M  (PCNT_DALTA_CHANGE_EN_U1_V << PCNT_DALTA_CHANGE_EN_U1_S)
+#define PCNT_DALTA_CHANGE_EN_U1_V  0x00000001U
+#define PCNT_DALTA_CHANGE_EN_U1_S  9
+/** PCNT_DALTA_CHANGE_EN_U2 : R/W; bitpos: [10]; default: 0;
+ *  Configures this bit to enable unit 2's step comparator.
+ */
+#define PCNT_DALTA_CHANGE_EN_U2    (BIT(10))
+#define PCNT_DALTA_CHANGE_EN_U2_M  (PCNT_DALTA_CHANGE_EN_U2_V << PCNT_DALTA_CHANGE_EN_U2_S)
+#define PCNT_DALTA_CHANGE_EN_U2_V  0x00000001U
+#define PCNT_DALTA_CHANGE_EN_U2_S  10
+/** PCNT_DALTA_CHANGE_EN_U3 : R/W; bitpos: [11]; default: 0;
+ *  Configures this bit to enable unit 3's step comparator.
+ */
+#define PCNT_DALTA_CHANGE_EN_U3    (BIT(11))
+#define PCNT_DALTA_CHANGE_EN_U3_M  (PCNT_DALTA_CHANGE_EN_U3_V << PCNT_DALTA_CHANGE_EN_U3_S)
+#define PCNT_DALTA_CHANGE_EN_U3_V  0x00000001U
+#define PCNT_DALTA_CHANGE_EN_U3_S  11
+/** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
+ *  and written by application. 0: the registers can not be read or written by
+ *  application
+ */
+#define PCNT_CLK_EN    (BIT(16))
+#define PCNT_CLK_EN_M  (PCNT_CLK_EN_V << PCNT_CLK_EN_S)
+#define PCNT_CLK_EN_V  0x00000001U
+#define PCNT_CLK_EN_S  16
+
+/** PCNT_U3_CHANGE_CONF_REG register
+ *  Configuration register for unit $n's step value.
+ */
+#define PCNT_U3_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x64)
+/** PCNT_CNT_STEP_U3 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the step value for unit 3.
+ */
+#define PCNT_CNT_STEP_U3    0x0000FFFFU
+#define PCNT_CNT_STEP_U3_M  (PCNT_CNT_STEP_U3_V << PCNT_CNT_STEP_U3_S)
+#define PCNT_CNT_STEP_U3_V  0x0000FFFFU
+#define PCNT_CNT_STEP_U3_S  0
+/** PCNT_CNT_STEP_LIM_U3 : R/W; bitpos: [31:16]; default: 0;
+ *  Configures the step limit value for unit 3.
+ */
+#define PCNT_CNT_STEP_LIM_U3    0x0000FFFFU
+#define PCNT_CNT_STEP_LIM_U3_M  (PCNT_CNT_STEP_LIM_U3_V << PCNT_CNT_STEP_LIM_U3_S)
+#define PCNT_CNT_STEP_LIM_U3_V  0x0000FFFFU
+#define PCNT_CNT_STEP_LIM_U3_S  16
+
+/** PCNT_U2_CHANGE_CONF_REG register
+ *  Configuration register for unit $n's step value.
+ */
+#define PCNT_U2_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x68)
+/** PCNT_CNT_STEP_U2 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the step value for unit 2.
+ */
+#define PCNT_CNT_STEP_U2    0x0000FFFFU
+#define PCNT_CNT_STEP_U2_M  (PCNT_CNT_STEP_U2_V << PCNT_CNT_STEP_U2_S)
+#define PCNT_CNT_STEP_U2_V  0x0000FFFFU
+#define PCNT_CNT_STEP_U2_S  0
+/** PCNT_CNT_STEP_LIM_U2 : R/W; bitpos: [31:16]; default: 0;
+ *  Configures the step limit value for unit 2.
+ */
+#define PCNT_CNT_STEP_LIM_U2    0x0000FFFFU
+#define PCNT_CNT_STEP_LIM_U2_M  (PCNT_CNT_STEP_LIM_U2_V << PCNT_CNT_STEP_LIM_U2_S)
+#define PCNT_CNT_STEP_LIM_U2_V  0x0000FFFFU
+#define PCNT_CNT_STEP_LIM_U2_S  16
+
+/** PCNT_U1_CHANGE_CONF_REG register
+ *  Configuration register for unit $n's step value.
+ */
+#define PCNT_U1_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x6c)
+/** PCNT_CNT_STEP_U1 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the step value for unit 1.
+ */
+#define PCNT_CNT_STEP_U1    0x0000FFFFU
+#define PCNT_CNT_STEP_U1_M  (PCNT_CNT_STEP_U1_V << PCNT_CNT_STEP_U1_S)
+#define PCNT_CNT_STEP_U1_V  0x0000FFFFU
+#define PCNT_CNT_STEP_U1_S  0
+/** PCNT_CNT_STEP_LIM_U1 : R/W; bitpos: [31:16]; default: 0;
+ *  Configures the step limit value for unit 1.
+ */
+#define PCNT_CNT_STEP_LIM_U1    0x0000FFFFU
+#define PCNT_CNT_STEP_LIM_U1_M  (PCNT_CNT_STEP_LIM_U1_V << PCNT_CNT_STEP_LIM_U1_S)
+#define PCNT_CNT_STEP_LIM_U1_V  0x0000FFFFU
+#define PCNT_CNT_STEP_LIM_U1_S  16
+
+/** PCNT_U0_CHANGE_CONF_REG register
+ *  Configuration register for unit $n's step value.
+ */
+#define PCNT_U0_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x70)
+/** PCNT_CNT_STEP_U0 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the step value for unit 0.
+ */
+#define PCNT_CNT_STEP_U0    0x0000FFFFU
+#define PCNT_CNT_STEP_U0_M  (PCNT_CNT_STEP_U0_V << PCNT_CNT_STEP_U0_S)
+#define PCNT_CNT_STEP_U0_V  0x0000FFFFU
+#define PCNT_CNT_STEP_U0_S  0
+/** PCNT_CNT_STEP_LIM_U0 : R/W; bitpos: [31:16]; default: 0;
+ *  Configures the step limit value for unit 0.
+ */
+#define PCNT_CNT_STEP_LIM_U0    0x0000FFFFU
+#define PCNT_CNT_STEP_LIM_U0_M  (PCNT_CNT_STEP_LIM_U0_V << PCNT_CNT_STEP_LIM_U0_S)
+#define PCNT_CNT_STEP_LIM_U0_V  0x0000FFFFU
+#define PCNT_CNT_STEP_LIM_U0_S  16
+
+/** PCNT_DATE_REG register
+ *  PCNT version control register
+ */
+#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc)
+/** PCNT_DATE : R/W; bitpos: [31:0]; default: 35721985;
+ *  This is the PCNT version control register.
+ */
+#define PCNT_DATE    0xFFFFFFFFU
+#define PCNT_DATE_M  (PCNT_DATE_V << PCNT_DATE_S)
+#define PCNT_DATE_V  0xFFFFFFFFU
+#define PCNT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pcnt_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pcnt_struct.h
new file mode 100644
index 0000000000..03b63407cf
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pcnt_struct.h
@@ -0,0 +1,442 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of un_conf0 register
+ *  Configuration register 0 for unit n
+ */
+typedef union {
+    struct {
+        /** filter_thres : R/W; bitpos: [9:0]; default: 16;
+         *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+         *
+         *  Any pulses with width less than this will be ignored when the filter is enabled.
+         */
+        uint32_t filter_thres:10;
+        /** filter_en : R/W; bitpos: [10]; default: 1;
+         *  This is the enable bit for unit n's input filter.
+         */
+        uint32_t filter_en:1;
+        /** thr_zero_en : R/W; bitpos: [11]; default: 1;
+         *  This is the enable bit for unit n's zero comparator.
+         */
+        uint32_t thr_zero_en:1;
+        /** thr_h_lim_en : R/W; bitpos: [12]; default: 1;
+         *  This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
+         *  the high limit interrupt.
+         */
+        uint32_t thr_h_lim_en:1;
+        /** thr_l_lim_en : R/W; bitpos: [13]; default: 1;
+         *  This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
+         *  the low limit interrupt.
+         */
+        uint32_t thr_l_lim_en:1;
+        /** thr_thres0_en : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for unit n's thres0 comparator.
+         */
+        uint32_t thr_thres0_en:1;
+        /** thr_thres1_en : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for unit n's thres1 comparator.
+         */
+        uint32_t thr_thres1_en:1;
+        /** ch0_neg_mode : R/W; bitpos: [17:16]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  negative edge.
+         *
+         *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+         */
+        uint32_t ch0_neg_mode:2;
+        /** ch0_pos_mode : R/W; bitpos: [19:18]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  positive edge.
+         *
+         *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+         */
+        uint32_t ch0_pos_mode:2;
+        /** ch0_hctrl_mode : R/W; bitpos: [21:20]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_hctrl_mode:2;
+        /** ch0_lctrl_mode : R/W; bitpos: [23:22]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_lctrl_mode:2;
+        /** ch1_neg_mode : R/W; bitpos: [25:24]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  negative edge.
+         *
+         *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+         */
+        uint32_t ch1_neg_mode:2;
+        /** ch1_pos_mode : R/W; bitpos: [27:26]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  positive edge.
+         *
+         *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+         */
+        uint32_t ch1_pos_mode:2;
+        /** ch1_hctrl_mode : R/W; bitpos: [29:28]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_hctrl_mode:2;
+        /** ch1_lctrl_mode : R/W; bitpos: [31:30]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_lctrl_mode:2;
+    };
+    uint32_t val;
+} pcnt_un_conf0_reg_t;
+
+/** Type of un_conf1 register
+ *  Configuration register 1 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_thres0 : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thres0 value for unit n.
+         */
+        uint32_t cnt_thres0:16;
+        /** cnt_thres1 : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thres1 value for unit n.
+         */
+        uint32_t cnt_thres1:16;
+    };
+    uint32_t val;
+} pcnt_un_conf1_reg_t;
+
+/** Type of un_conf2 register
+ *  Configuration register 2 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_h_lim : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thr_h_lim value for unit n. When pcnt
+         *  reaches this value, the counter will be cleared to 0.
+         */
+        uint32_t cnt_h_lim:16;
+        /** cnt_l_lim : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thr_l_lim value for unit n. When pcnt
+         *  reaches this value, the counter will be cleared to 0.
+         */
+        uint32_t cnt_l_lim:16;
+    };
+    uint32_t val;
+} pcnt_un_conf2_reg_t;
+
+/** Type of ctrl register
+ *  Control register for all counters
+ */
+typedef union {
+    struct {
+        /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to clear unit 0's counter.
+         */
+        uint32_t pulse_cnt_rst_u0:1;
+        /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to freeze unit 0's counter.
+         */
+        uint32_t cnt_pause_u0:1;
+        /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to clear unit 1's counter.
+         */
+        uint32_t pulse_cnt_rst_u1:1;
+        /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to freeze unit 1's counter.
+         */
+        uint32_t cnt_pause_u1:1;
+        /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to clear unit 2's counter.
+         */
+        uint32_t pulse_cnt_rst_u2:1;
+        /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to freeze unit 2's counter.
+         */
+        uint32_t cnt_pause_u2:1;
+        /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
+         *  Set this bit to clear unit 3's counter.
+         */
+        uint32_t pulse_cnt_rst_u3:1;
+        /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to freeze unit 3's counter.
+         */
+        uint32_t cnt_pause_u3:1;
+        /** delta_change_en_u0 : R/W; bitpos: [8]; default: 0;
+         *  Configures this bit to enable unit 0's step comparator.
+         */
+        uint32_t delta_change_en_u0:1;
+        /** delta_change_en_u1 : R/W; bitpos: [9]; default: 0;
+         *  Configures this bit to enable unit 1's step comparator.
+         */
+        uint32_t delta_change_en_u1:1;
+        /** delta_change_en_u2 : R/W; bitpos: [10]; default: 0;
+         *  Configures this bit to enable unit 2's step comparator.
+         */
+        uint32_t delta_change_en_u2:1;
+        /** delta_change_en_u3 : R/W; bitpos: [11]; default: 0;
+         *  Configures this bit to enable unit 3's step comparator.
+         */
+        uint32_t delta_change_en_u3:1;
+        uint32_t reserved_12:4;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
+         *  and written by application. 0: the registers can not be read or written by
+         *  application
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pcnt_ctrl_reg_t;
+
+/** Type of change_conf register
+ *  Configuration register for unit $n's step value.
+ */
+typedef union {
+    struct {
+        /** cnt_step : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the step value for unit n.
+         */
+        uint32_t cnt_step:16;
+        /** cnt_step_lim : R/W; bitpos: [31:16]; default: 0;
+         *  Configures the step limit value for unit n.
+         */
+        uint32_t cnt_step_lim:16;
+    };
+    uint32_t val;
+} pcnt_un_change_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of un_cnt register
+ *  Counter value for unit n
+ */
+typedef union {
+    struct {
+        /** pulse_cnt : RO; bitpos: [15:0]; default: 0;
+         *  This register stores the current pulse count value for unit n.
+         */
+        uint32_t pulse_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} pcnt_un_cnt_reg_t;
+
+/** Type of un_status register
+ *  PNCT UNITn status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_zero_mode : RO; bitpos: [1:0]; default: 0;
+         *  The pulse counter status of PCNT corresponding to 0. 0: pulse counter decreases
+         *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+         *  is negative. 3: pulse counter is positive.
+         */
+        uint32_t cnt_thr_zero_mode:2;
+        /** cnt_thr_thres1_lat : RO; bitpos: [2]; default: 0;
+         *  The latched value of thres1 event of PCNT when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres1_lat:1;
+        /** cnt_thr_thres0_lat : RO; bitpos: [3]; default: 0;
+         *  The latched value of thres0 event of PCNT when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres0_lat:1;
+        /** cnt_thr_l_lim_lat : RO; bitpos: [4]; default: 0;
+         *  The latched value of low limit event of PCNT when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_l_lim_lat:1;
+        /** cnt_thr_h_lim_lat : RO; bitpos: [5]; default: 0;
+         *  The latched value of high limit event of PCNT when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_h_lim_lat:1;
+        /** cnt_thr_zero_lat : RO; bitpos: [6]; default: 0;
+         *  The latched value of zero threshold event of PCNT when threshold event interrupt
+         *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_zero_lat:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} pcnt_un_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_raw:1;
+        /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_raw:1;
+        /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_raw:1;
+        /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_st:1;
+        /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_st:1;
+        /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_st:1;
+        /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_ena:1;
+        /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_ena:1;
+        /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_ena:1;
+        /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_clr:1;
+        /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_clr:1;
+        /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_clr:1;
+        /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  PCNT version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 571021568;
+         *  This is the PCNT version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} pcnt_date_reg_t;
+
+typedef struct pcnt_dev_t {
+    volatile struct {
+        pcnt_un_conf0_reg_t conf0;
+        pcnt_un_conf1_reg_t conf1;
+        pcnt_un_conf2_reg_t conf2;
+    } conf_unit[4];
+    volatile pcnt_un_cnt_reg_t cnt_unit[4];
+    volatile pcnt_int_raw_reg_t int_raw;
+    volatile pcnt_int_st_reg_t int_st;
+    volatile pcnt_int_ena_reg_t int_ena;
+    volatile pcnt_int_clr_reg_t int_clr;
+    volatile pcnt_un_status_reg_t status_unit[4];
+    volatile pcnt_ctrl_reg_t ctrl;
+    volatile pcnt_un_change_conf_reg_t change_conf_unit[4]; // Note the unit order is 3210
+    uint32_t reserved_074[34];
+    volatile pcnt_date_reg_t date;
+} pcnt_dev_t;
+
+extern pcnt_dev_t PCNT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pmu_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/pmu_eco5_reg.h
new file mode 100644
index 0000000000..3d574d64cf
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pmu_eco5_reg.h
@@ -0,0 +1,4968 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMU_HP_ACTIVE_DIG_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0)
+/** PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN    (BIT(21))
+#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_M  (PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_V << PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_S)
+#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_S  21
+/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_MEM_DSLP    (BIT(22))
+#define PMU_HP_ACTIVE_HP_MEM_DSLP_M  (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S)
+#define PMU_HP_ACTIVE_HP_MEM_DSLP_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_MEM_DSLP_S  22
+/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN    (BIT(23))
+#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S)
+#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S  23
+/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN    (BIT(29))
+#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S)
+#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S  29
+/** PMU_HP_ACTIVE_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_PD_CNNT_PD_EN    (BIT(30))
+#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_M  (PMU_HP_ACTIVE_PD_CNNT_PD_EN_V << PMU_HP_ACTIVE_PD_CNNT_PD_EN_S)
+#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_S  30
+/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_PD_TOP_PD_EN    (BIT(31))
+#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M  (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S)
+#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S  31
+
+/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4)
+/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M  (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S)
+#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S  0
+
+/** PMU_HP_ACTIVE_ICG_HP_APB_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8)
+/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_ICG_APB_EN    0xFFFFFFFFU
+#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M  (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S)
+#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V  0xFFFFFFFFU
+#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S  0
+
+/** PMU_HP_ACTIVE_ICG_MODEM_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc)
+/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE    0x00000003U
+#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M  (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S)
+#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V  0x00000003U
+#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S  30
+
+/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10)
+/** PMU_HP_ACTIVE_HP_POWER_DET_BYPASS : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS    (BIT(23))
+#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M  (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S)
+#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S  23
+/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_UART_WAKEUP_EN    (BIT(24))
+#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M  (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S)
+#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S  24
+/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL    (BIT(25))
+#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M  (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S)
+#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S  25
+/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL    (BIT(26))
+#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M  (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S)
+#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S  26
+/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL    (BIT(27))
+#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M  (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S)
+#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V  0x00000001U
+#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S  27
+/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_PAUSE_WDT    (BIT(28))
+#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M  (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S)
+#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V  0x00000001U
+#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S  28
+/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_CPU_STALL    (BIT(29))
+#define PMU_HP_ACTIVE_DIG_CPU_STALL_M  (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S)
+#define PMU_HP_ACTIVE_DIG_CPU_STALL_V  0x00000001U
+#define PMU_HP_ACTIVE_DIG_CPU_STALL_S  29
+
+/** PMU_HP_ACTIVE_HP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14)
+/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_I2C_ISO_EN    (BIT(21))
+#define PMU_HP_ACTIVE_I2C_ISO_EN_M  (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S)
+#define PMU_HP_ACTIVE_I2C_ISO_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_I2C_ISO_EN_S  21
+/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_I2C_RETENTION    (BIT(22))
+#define PMU_HP_ACTIVE_I2C_RETENTION_M  (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S)
+#define PMU_HP_ACTIVE_I2C_RETENTION_V  0x00000001U
+#define PMU_HP_ACTIVE_I2C_RETENTION_S  22
+/** PMU_HP_ACTIVE_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_XPD_PLL_I2C    0x0000000FU
+#define PMU_HP_ACTIVE_XPD_PLL_I2C_M  (PMU_HP_ACTIVE_XPD_PLL_I2C_V << PMU_HP_ACTIVE_XPD_PLL_I2C_S)
+#define PMU_HP_ACTIVE_XPD_PLL_I2C_V  0x0000000FU
+#define PMU_HP_ACTIVE_XPD_PLL_I2C_S  23
+/** PMU_HP_ACTIVE_XPD_PLL : R/W; bitpos: [30:27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_XPD_PLL    0x0000000FU
+#define PMU_HP_ACTIVE_XPD_PLL_M  (PMU_HP_ACTIVE_XPD_PLL_V << PMU_HP_ACTIVE_XPD_PLL_S)
+#define PMU_HP_ACTIVE_XPD_PLL_V  0x0000000FU
+#define PMU_HP_ACTIVE_XPD_PLL_S  27
+
+/** PMU_HP_ACTIVE_BIAS_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18)
+/** PMU_HP_ACTIVE_DCM_VSET : R/W; bitpos: [22:18]; default: 20;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DCM_VSET    0x0000001FU
+#define PMU_HP_ACTIVE_DCM_VSET_M  (PMU_HP_ACTIVE_DCM_VSET_V << PMU_HP_ACTIVE_DCM_VSET_S)
+#define PMU_HP_ACTIVE_DCM_VSET_V  0x0000001FU
+#define PMU_HP_ACTIVE_DCM_VSET_S  18
+/** PMU_HP_ACTIVE_DCM_MODE : R/W; bitpos: [24:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DCM_MODE    0x00000003U
+#define PMU_HP_ACTIVE_DCM_MODE_M  (PMU_HP_ACTIVE_DCM_MODE_V << PMU_HP_ACTIVE_DCM_MODE_S)
+#define PMU_HP_ACTIVE_DCM_MODE_V  0x00000003U
+#define PMU_HP_ACTIVE_DCM_MODE_S  23
+/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_XPD_BIAS    (BIT(25))
+#define PMU_HP_ACTIVE_XPD_BIAS_M  (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S)
+#define PMU_HP_ACTIVE_XPD_BIAS_V  0x00000001U
+#define PMU_HP_ACTIVE_XPD_BIAS_S  25
+/** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DBG_ATTEN    0x0000000FU
+#define PMU_HP_ACTIVE_DBG_ATTEN_M  (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S)
+#define PMU_HP_ACTIVE_DBG_ATTEN_V  0x0000000FU
+#define PMU_HP_ACTIVE_DBG_ATTEN_S  26
+/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_PD_CUR    (BIT(30))
+#define PMU_HP_ACTIVE_PD_CUR_M  (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S)
+#define PMU_HP_ACTIVE_PD_CUR_V  0x00000001U
+#define PMU_HP_ACTIVE_PD_CUR_S  30
+/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_BIAS_SLEEP    (BIT(31))
+#define PMU_HP_ACTIVE_BIAS_SLEEP_M  (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S)
+#define PMU_HP_ACTIVE_BIAS_SLEEP_V  0x00000001U
+#define PMU_HP_ACTIVE_BIAS_SLEEP_S  31
+
+/** PMU_HP_ACTIVE_BACKUP_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c)
+/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE    0x00000003U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S)
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V  0x00000003U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S  4
+/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE    0x00000003U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S)
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V  0x00000003U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S  6
+/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_RETENTION_MODE    (BIT(10))
+#define PMU_HP_ACTIVE_RETENTION_MODE_M  (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S)
+#define PMU_HP_ACTIVE_RETENTION_MODE_V  0x00000001U
+#define PMU_HP_ACTIVE_RETENTION_MODE_S  10
+/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN    (BIT(11))
+#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M  (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S)
+#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V  0x00000001U
+#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S  11
+/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2ACTIVE_RETENTION_EN    (BIT(12))
+#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M  (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S)
+#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V  0x00000001U
+#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S  12
+/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL    0x00000003U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S)
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V  0x00000003U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S  14
+/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL    0x00000003U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M  (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S)
+#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V  0x00000003U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S  16
+/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE    0x00000007U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S)
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V  0x00000007U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S  20
+/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE    0x00000007U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M  (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S)
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V  0x00000007U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S  23
+/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN    (BIT(29))
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S)
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V  0x00000001U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S  29
+/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2ACTIVE_BACKUP_EN    (BIT(30))
+#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M  (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S)
+#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V  0x00000001U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S  30
+
+/** PMU_HP_ACTIVE_BACKUP_CLK_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20)
+/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M  (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S)
+#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S  0
+
+/** PMU_HP_ACTIVE_SYSCLK_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24)
+/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV    (BIT(26))
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S)
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V  0x00000001U
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S  26
+/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN    (BIT(27))
+#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M  (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S)
+#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S  27
+/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL    (BIT(28))
+#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M  (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S)
+#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V  0x00000001U
+#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S  28
+/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_ICG_SLP_SEL    (BIT(29))
+#define PMU_HP_ACTIVE_ICG_SLP_SEL_M  (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S)
+#define PMU_HP_ACTIVE_ICG_SLP_SEL_V  0x00000001U
+#define PMU_HP_ACTIVE_ICG_SLP_SEL_S  29
+/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL    0x00000003U
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M  (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S)
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V  0x00000003U
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S  30
+
+/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28)
+/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24;
+ *  need_des
+ */
+#define PMU_LP_DBIAS_VOL    0x0000001FU
+#define PMU_LP_DBIAS_VOL_M  (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S)
+#define PMU_LP_DBIAS_VOL_V  0x0000001FU
+#define PMU_LP_DBIAS_VOL_S  4
+/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24;
+ *  need_des
+ */
+#define PMU_HP_DBIAS_VOL    0x0000001FU
+#define PMU_HP_DBIAS_VOL_M  (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S)
+#define PMU_HP_DBIAS_VOL_V  0x0000001FU
+#define PMU_HP_DBIAS_VOL_S  9
+/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1;
+ *  need_des
+ */
+#define PMU_DIG_REGULATOR0_DBIAS_SEL    (BIT(14))
+#define PMU_DIG_REGULATOR0_DBIAS_SEL_M  (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S)
+#define PMU_DIG_REGULATOR0_DBIAS_SEL_V  0x00000001U
+#define PMU_DIG_REGULATOR0_DBIAS_SEL_S  14
+/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define PMU_DIG_DBIAS_INIT    (BIT(15))
+#define PMU_DIG_DBIAS_INIT_M  (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S)
+#define PMU_DIG_DBIAS_INIT_V  0x00000001U
+#define PMU_DIG_DBIAS_INIT_S  15
+/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S  16
+/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S  17
+/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_XPD    (BIT(18))
+#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S  18
+/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S  19
+/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
+/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS    0x0000001FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V  0x0000001FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S  27
+
+/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c)
+/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B    0x0000003FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M  (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V  0x0000003FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S  26
+
+/** PMU_HP_ACTIVE_XTAL_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30)
+/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_XPD_XTAL    (BIT(31))
+#define PMU_HP_ACTIVE_XPD_XTAL_M  (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S)
+#define PMU_HP_ACTIVE_XPD_XTAL_V  0x00000001U
+#define PMU_HP_ACTIVE_XPD_XTAL_S  31
+
+/** PMU_HP_MODEM_DIG_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34)
+/** PMU_HP_MODEM_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN    (BIT(21))
+#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_M  (PMU_HP_MODEM_DCDC_SWITCH_PD_EN_V << PMU_HP_MODEM_DCDC_SWITCH_PD_EN_S)
+#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_V  0x00000001U
+#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_S  21
+/** PMU_HP_MODEM_HP_MEM_DSLP : WT; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_MEM_DSLP    (BIT(22))
+#define PMU_HP_MODEM_HP_MEM_DSLP_M  (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S)
+#define PMU_HP_MODEM_HP_MEM_DSLP_V  0x00000001U
+#define PMU_HP_MODEM_HP_MEM_DSLP_S  22
+/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : WT; bitpos: [26:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_HP_MEM_PD_EN    0x0000000FU
+#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M  (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S)
+#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V  0x0000000FU
+#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S  23
+/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN    (BIT(27))
+#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M  (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S)
+#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V  0x00000001U
+#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S  27
+/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_HP_CPU_PD_EN    (BIT(29))
+#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M  (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S)
+#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V  0x00000001U
+#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S  29
+/** PMU_HP_MODEM_PD_CNNT_PD_EN : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_CNNT_PD_EN    (BIT(30))
+#define PMU_HP_MODEM_PD_CNNT_PD_EN_M  (PMU_HP_MODEM_PD_CNNT_PD_EN_V << PMU_HP_MODEM_PD_CNNT_PD_EN_S)
+#define PMU_HP_MODEM_PD_CNNT_PD_EN_V  0x00000001U
+#define PMU_HP_MODEM_PD_CNNT_PD_EN_S  30
+/** PMU_HP_MODEM_PD_TOP_PD_EN : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_TOP_PD_EN    (BIT(31))
+#define PMU_HP_MODEM_PD_TOP_PD_EN_M  (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S)
+#define PMU_HP_MODEM_PD_TOP_PD_EN_V  0x00000001U
+#define PMU_HP_MODEM_PD_TOP_PD_EN_S  31
+
+/** PMU_HP_MODEM_ICG_HP_FUNC_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38)
+/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M  (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S)
+#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S  0
+
+/** PMU_HP_MODEM_ICG_HP_APB_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c)
+/** PMU_HP_MODEM_DIG_ICG_APB_EN : WT; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_ICG_APB_EN    0xFFFFFFFFU
+#define PMU_HP_MODEM_DIG_ICG_APB_EN_M  (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S)
+#define PMU_HP_MODEM_DIG_ICG_APB_EN_V  0xFFFFFFFFU
+#define PMU_HP_MODEM_DIG_ICG_APB_EN_S  0
+
+/** PMU_HP_MODEM_ICG_MODEM_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40)
+/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : WT; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE    0x00000003U
+#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M  (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S)
+#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V  0x00000003U
+#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S  30
+
+/** PMU_HP_MODEM_HP_SYS_CNTL_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44)
+/** PMU_HP_MODEM_HP_POWER_DET_BYPASS : WT; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_POWER_DET_BYPASS    (BIT(23))
+#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M  (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S)
+#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_V  0x00000001U
+#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S  23
+/** PMU_HP_MODEM_UART_WAKEUP_EN : WT; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_UART_WAKEUP_EN    (BIT(24))
+#define PMU_HP_MODEM_UART_WAKEUP_EN_M  (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S)
+#define PMU_HP_MODEM_UART_WAKEUP_EN_V  0x00000001U
+#define PMU_HP_MODEM_UART_WAKEUP_EN_S  24
+/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : WT; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_LP_PAD_HOLD_ALL    (BIT(25))
+#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M  (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S)
+#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S  25
+/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_PAD_HOLD_ALL    (BIT(26))
+#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M  (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S)
+#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S  26
+/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_PAD_SLP_SEL    (BIT(27))
+#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M  (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S)
+#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V  0x00000001U
+#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S  27
+/** PMU_HP_MODEM_DIG_PAUSE_WDT : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_PAUSE_WDT    (BIT(28))
+#define PMU_HP_MODEM_DIG_PAUSE_WDT_M  (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S)
+#define PMU_HP_MODEM_DIG_PAUSE_WDT_V  0x00000001U
+#define PMU_HP_MODEM_DIG_PAUSE_WDT_S  28
+/** PMU_HP_MODEM_DIG_CPU_STALL : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_CPU_STALL    (BIT(29))
+#define PMU_HP_MODEM_DIG_CPU_STALL_M  (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S)
+#define PMU_HP_MODEM_DIG_CPU_STALL_V  0x00000001U
+#define PMU_HP_MODEM_DIG_CPU_STALL_S  29
+
+/** PMU_HP_MODEM_HP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48)
+/** PMU_HP_MODEM_I2C_ISO_EN : WT; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_I2C_ISO_EN    (BIT(21))
+#define PMU_HP_MODEM_I2C_ISO_EN_M  (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S)
+#define PMU_HP_MODEM_I2C_ISO_EN_V  0x00000001U
+#define PMU_HP_MODEM_I2C_ISO_EN_S  21
+/** PMU_HP_MODEM_I2C_RETENTION : WT; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_I2C_RETENTION    (BIT(22))
+#define PMU_HP_MODEM_I2C_RETENTION_M  (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S)
+#define PMU_HP_MODEM_I2C_RETENTION_V  0x00000001U
+#define PMU_HP_MODEM_I2C_RETENTION_S  22
+/** PMU_HP_MODEM_XPD_PLL_I2C : WT; bitpos: [26:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_XPD_PLL_I2C    0x0000000FU
+#define PMU_HP_MODEM_XPD_PLL_I2C_M  (PMU_HP_MODEM_XPD_PLL_I2C_V << PMU_HP_MODEM_XPD_PLL_I2C_S)
+#define PMU_HP_MODEM_XPD_PLL_I2C_V  0x0000000FU
+#define PMU_HP_MODEM_XPD_PLL_I2C_S  23
+/** PMU_HP_MODEM_XPD_PLL : WT; bitpos: [30:27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_XPD_PLL    0x0000000FU
+#define PMU_HP_MODEM_XPD_PLL_M  (PMU_HP_MODEM_XPD_PLL_V << PMU_HP_MODEM_XPD_PLL_S)
+#define PMU_HP_MODEM_XPD_PLL_V  0x0000000FU
+#define PMU_HP_MODEM_XPD_PLL_S  27
+
+/** PMU_HP_MODEM_BIAS_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c)
+/** PMU_HP_MODEM_DCM_VSET : WT; bitpos: [22:18]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DCM_VSET    0x0000001FU
+#define PMU_HP_MODEM_DCM_VSET_M  (PMU_HP_MODEM_DCM_VSET_V << PMU_HP_MODEM_DCM_VSET_S)
+#define PMU_HP_MODEM_DCM_VSET_V  0x0000001FU
+#define PMU_HP_MODEM_DCM_VSET_S  18
+/** PMU_HP_MODEM_DCM_MODE : WT; bitpos: [24:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DCM_MODE    0x00000003U
+#define PMU_HP_MODEM_DCM_MODE_M  (PMU_HP_MODEM_DCM_MODE_V << PMU_HP_MODEM_DCM_MODE_S)
+#define PMU_HP_MODEM_DCM_MODE_V  0x00000003U
+#define PMU_HP_MODEM_DCM_MODE_S  23
+/** PMU_HP_MODEM_XPD_BIAS : WT; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_XPD_BIAS    (BIT(25))
+#define PMU_HP_MODEM_XPD_BIAS_M  (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S)
+#define PMU_HP_MODEM_XPD_BIAS_V  0x00000001U
+#define PMU_HP_MODEM_XPD_BIAS_S  25
+/** PMU_HP_MODEM_DBG_ATTEN : WT; bitpos: [29:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DBG_ATTEN    0x0000000FU
+#define PMU_HP_MODEM_DBG_ATTEN_M  (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S)
+#define PMU_HP_MODEM_DBG_ATTEN_V  0x0000000FU
+#define PMU_HP_MODEM_DBG_ATTEN_S  26
+/** PMU_HP_MODEM_PD_CUR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_CUR    (BIT(30))
+#define PMU_HP_MODEM_PD_CUR_M  (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S)
+#define PMU_HP_MODEM_PD_CUR_V  0x00000001U
+#define PMU_HP_MODEM_PD_CUR_S  30
+/** PMU_HP_MODEM_BIAS_SLEEP : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_BIAS_SLEEP    (BIT(31))
+#define PMU_HP_MODEM_BIAS_SLEEP_M  (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S)
+#define PMU_HP_MODEM_BIAS_SLEEP_V  0x00000001U
+#define PMU_HP_MODEM_BIAS_SLEEP_S  31
+
+/** PMU_HP_MODEM_BACKUP_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50)
+/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : WT; bitpos: [5:4]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE    0x00000003U
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S)
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V  0x00000003U
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S  4
+/** PMU_HP_MODEM_RETENTION_MODE : WT; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_RETENTION_MODE    (BIT(10))
+#define PMU_HP_MODEM_RETENTION_MODE_M  (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S)
+#define PMU_HP_MODEM_RETENTION_MODE_V  0x00000001U
+#define PMU_HP_MODEM_RETENTION_MODE_S  10
+/** PMU_HP_SLEEP2MODEM_RETENTION_EN : WT; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2MODEM_RETENTION_EN    (BIT(11))
+#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M  (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S)
+#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V  0x00000001U
+#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S  11
+/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : WT; bitpos: [15:14]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL    0x00000003U
+#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M  (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S)
+#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V  0x00000003U
+#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S  14
+/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : WT; bitpos: [22:20]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODE    0x00000007U
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M  (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S)
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V  0x00000007U
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S  20
+/** PMU_HP_SLEEP2MODEM_BACKUP_EN : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2MODEM_BACKUP_EN    (BIT(29))
+#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M  (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S)
+#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V  0x00000001U
+#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S  29
+
+/** PMU_HP_MODEM_BACKUP_CLK_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54)
+/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M  (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S)
+#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S  0
+
+/** PMU_HP_MODEM_SYSCLK_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58)
+/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV    (BIT(26))
+#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S)
+#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V  0x00000001U
+#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S  26
+/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN    (BIT(27))
+#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M  (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S)
+#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V  0x00000001U
+#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S  27
+/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_SYS_CLK_SLP_SEL    (BIT(28))
+#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M  (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S)
+#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V  0x00000001U
+#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S  28
+/** PMU_HP_MODEM_ICG_SLP_SEL : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_ICG_SLP_SEL    (BIT(29))
+#define PMU_HP_MODEM_ICG_SLP_SEL_M  (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S)
+#define PMU_HP_MODEM_ICG_SLP_SEL_V  0x00000001U
+#define PMU_HP_MODEM_ICG_SLP_SEL_S  29
+/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : WT; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_SYS_CLK_SEL    0x00000003U
+#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M  (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S)
+#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V  0x00000003U
+#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S  30
+
+/** PMU_HP_MODEM_HP_REGULATOR0_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c)
+/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : WT; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S)
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S  16
+/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : WT; bitpos: [17]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S)
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S  17
+/** PMU_HP_MODEM_HP_REGULATOR_XPD : WT; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_XPD    (BIT(18))
+#define PMU_HP_MODEM_HP_REGULATOR_XPD_M  (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S)
+#define PMU_HP_MODEM_HP_REGULATOR_XPD_V  0x00000001U
+#define PMU_HP_MODEM_HP_REGULATOR_XPD_S  18
+/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : WT; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S)
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S  19
+/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : WT; bitpos: [26:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
+/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : WT; bitpos: [31:27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_DBIAS    0x0000001FU
+#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M  (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S)
+#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V  0x0000001FU
+#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S  27
+
+/** PMU_HP_MODEM_HP_REGULATOR1_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60)
+/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : WT; bitpos: [31:8]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_DRV_B    0x00FFFFFFU
+#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M  (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S)
+#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V  0x00FFFFFFU
+#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S  8
+
+/** PMU_HP_MODEM_XTAL_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64)
+/** PMU_HP_MODEM_XPD_XTAL : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_XPD_XTAL    (BIT(31))
+#define PMU_HP_MODEM_XPD_XTAL_M  (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S)
+#define PMU_HP_MODEM_XPD_XTAL_V  0x00000001U
+#define PMU_HP_MODEM_XPD_XTAL_S  31
+
+/** PMU_HP_SLEEP_DIG_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68)
+/** PMU_HP_SLEEP_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN    (BIT(21))
+#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_M  (PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_V << PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_S)
+#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_S  21
+/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_MEM_DSLP    (BIT(22))
+#define PMU_HP_SLEEP_HP_MEM_DSLP_M  (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S)
+#define PMU_HP_SLEEP_HP_MEM_DSLP_V  0x00000001U
+#define PMU_HP_SLEEP_HP_MEM_DSLP_S  22
+/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN    (BIT(23))
+#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M  (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S)
+#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S  23
+/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN    (BIT(29))
+#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M  (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S)
+#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S  29
+/** PMU_HP_SLEEP_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_CNNT_PD_EN    (BIT(30))
+#define PMU_HP_SLEEP_PD_CNNT_PD_EN_M  (PMU_HP_SLEEP_PD_CNNT_PD_EN_V << PMU_HP_SLEEP_PD_CNNT_PD_EN_S)
+#define PMU_HP_SLEEP_PD_CNNT_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_PD_CNNT_PD_EN_S  30
+/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_TOP_PD_EN    (BIT(31))
+#define PMU_HP_SLEEP_PD_TOP_PD_EN_M  (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S)
+#define PMU_HP_SLEEP_PD_TOP_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_PD_TOP_PD_EN_S  31
+
+/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c)
+/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M  (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S)
+#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S  0
+
+/** PMU_HP_SLEEP_ICG_HP_APB_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70)
+/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_ICG_APB_EN    0xFFFFFFFFU
+#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M  (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S)
+#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V  0xFFFFFFFFU
+#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S  0
+
+/** PMU_HP_SLEEP_ICG_MODEM_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74)
+/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE    0x00000003U
+#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M  (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S)
+#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V  0x00000003U
+#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S  30
+
+/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78)
+/** PMU_HP_SLEEP_HP_POWER_DET_BYPASS : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS    (BIT(23))
+#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_M  (PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V << PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S)
+#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V  0x00000001U
+#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S  23
+/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_UART_WAKEUP_EN    (BIT(24))
+#define PMU_HP_SLEEP_UART_WAKEUP_EN_M  (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S)
+#define PMU_HP_SLEEP_UART_WAKEUP_EN_V  0x00000001U
+#define PMU_HP_SLEEP_UART_WAKEUP_EN_S  24
+/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL    (BIT(25))
+#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M  (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S)
+#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S  25
+/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL    (BIT(26))
+#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M  (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S)
+#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S  26
+/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL    (BIT(27))
+#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M  (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S)
+#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V  0x00000001U
+#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S  27
+/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_PAUSE_WDT    (BIT(28))
+#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M  (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S)
+#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V  0x00000001U
+#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S  28
+/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_CPU_STALL    (BIT(29))
+#define PMU_HP_SLEEP_DIG_CPU_STALL_M  (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S)
+#define PMU_HP_SLEEP_DIG_CPU_STALL_V  0x00000001U
+#define PMU_HP_SLEEP_DIG_CPU_STALL_S  29
+
+/** PMU_HP_SLEEP_HP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c)
+/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_I2C_ISO_EN    (BIT(21))
+#define PMU_HP_SLEEP_I2C_ISO_EN_M  (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S)
+#define PMU_HP_SLEEP_I2C_ISO_EN_V  0x00000001U
+#define PMU_HP_SLEEP_I2C_ISO_EN_S  21
+/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_I2C_RETENTION    (BIT(22))
+#define PMU_HP_SLEEP_I2C_RETENTION_M  (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S)
+#define PMU_HP_SLEEP_I2C_RETENTION_V  0x00000001U
+#define PMU_HP_SLEEP_I2C_RETENTION_S  22
+/** PMU_HP_SLEEP_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_PLL_I2C    0x0000000FU
+#define PMU_HP_SLEEP_XPD_PLL_I2C_M  (PMU_HP_SLEEP_XPD_PLL_I2C_V << PMU_HP_SLEEP_XPD_PLL_I2C_S)
+#define PMU_HP_SLEEP_XPD_PLL_I2C_V  0x0000000FU
+#define PMU_HP_SLEEP_XPD_PLL_I2C_S  23
+/** PMU_HP_SLEEP_XPD_PLL : R/W; bitpos: [30:27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_PLL    0x0000000FU
+#define PMU_HP_SLEEP_XPD_PLL_M  (PMU_HP_SLEEP_XPD_PLL_V << PMU_HP_SLEEP_XPD_PLL_S)
+#define PMU_HP_SLEEP_XPD_PLL_V  0x0000000FU
+#define PMU_HP_SLEEP_XPD_PLL_S  27
+
+/** PMU_HP_SLEEP_BIAS_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80)
+/** PMU_HP_SLEEP_DCM_VSET : R/W; bitpos: [22:18]; default: 20;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DCM_VSET    0x0000001FU
+#define PMU_HP_SLEEP_DCM_VSET_M  (PMU_HP_SLEEP_DCM_VSET_V << PMU_HP_SLEEP_DCM_VSET_S)
+#define PMU_HP_SLEEP_DCM_VSET_V  0x0000001FU
+#define PMU_HP_SLEEP_DCM_VSET_S  18
+/** PMU_HP_SLEEP_DCM_MODE : R/W; bitpos: [24:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DCM_MODE    0x00000003U
+#define PMU_HP_SLEEP_DCM_MODE_M  (PMU_HP_SLEEP_DCM_MODE_V << PMU_HP_SLEEP_DCM_MODE_S)
+#define PMU_HP_SLEEP_DCM_MODE_V  0x00000003U
+#define PMU_HP_SLEEP_DCM_MODE_S  23
+/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_BIAS    (BIT(25))
+#define PMU_HP_SLEEP_XPD_BIAS_M  (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S)
+#define PMU_HP_SLEEP_XPD_BIAS_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_BIAS_S  25
+/** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DBG_ATTEN    0x0000000FU
+#define PMU_HP_SLEEP_DBG_ATTEN_M  (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S)
+#define PMU_HP_SLEEP_DBG_ATTEN_V  0x0000000FU
+#define PMU_HP_SLEEP_DBG_ATTEN_S  26
+/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_CUR    (BIT(30))
+#define PMU_HP_SLEEP_PD_CUR_M  (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S)
+#define PMU_HP_SLEEP_PD_CUR_V  0x00000001U
+#define PMU_HP_SLEEP_PD_CUR_S  30
+/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BIAS_SLEEP    (BIT(31))
+#define PMU_HP_SLEEP_BIAS_SLEEP_M  (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S)
+#define PMU_HP_SLEEP_BIAS_SLEEP_V  0x00000001U
+#define PMU_HP_SLEEP_BIAS_SLEEP_S  31
+
+/** PMU_HP_SLEEP_BACKUP_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84)
+/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE    0x00000003U
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S)
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V  0x00000003U
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S  6
+/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE    0x00000003U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S)
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V  0x00000003U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S  8
+/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_RETENTION_MODE    (BIT(10))
+#define PMU_HP_SLEEP_RETENTION_MODE_M  (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S)
+#define PMU_HP_SLEEP_RETENTION_MODE_V  0x00000001U
+#define PMU_HP_SLEEP_RETENTION_MODE_S  10
+/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2SLEEP_RETENTION_EN    (BIT(12))
+#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M  (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S)
+#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V  0x00000001U
+#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S  12
+/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN    (BIT(13))
+#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M  (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S)
+#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V  0x00000001U
+#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S  13
+/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL    0x00000003U
+#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M  (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S)
+#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V  0x00000003U
+#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S  16
+/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL    0x00000003U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S)
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V  0x00000003U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S  18
+/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODE    0x00000007U
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M  (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S)
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V  0x00000007U
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S  23
+/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE    0x00000007U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S)
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V  0x00000007U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S  26
+/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2SLEEP_BACKUP_EN    (BIT(30))
+#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M  (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S)
+#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V  0x00000001U
+#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S  30
+/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN    (BIT(31))
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S)
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V  0x00000001U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S  31
+
+/** PMU_HP_SLEEP_BACKUP_CLK_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88)
+/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M  (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S)
+#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S  0
+
+/** PMU_HP_SLEEP_SYSCLK_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c)
+/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV    (BIT(26))
+#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S)
+#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V  0x00000001U
+#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S  26
+/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN    (BIT(27))
+#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M  (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S)
+#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V  0x00000001U
+#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S  27
+/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL    (BIT(28))
+#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M  (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S)
+#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V  0x00000001U
+#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S  28
+/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_ICG_SLP_SEL    (BIT(29))
+#define PMU_HP_SLEEP_ICG_SLP_SEL_M  (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S)
+#define PMU_HP_SLEEP_ICG_SLP_SEL_V  0x00000001U
+#define PMU_HP_SLEEP_ICG_SLP_SEL_S  29
+/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL    0x00000003U
+#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M  (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S)
+#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V  0x00000003U
+#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S  30
+
+/** PMU_HP_SLEEP_HP_REGULATOR0_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90)
+/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S  16
+/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S  17
+/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_XPD    (BIT(18))
+#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V  0x00000001U
+#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S  18
+/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S  19
+/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
+/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS    0x0000001FU
+#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V  0x0000001FU
+#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S  27
+
+/** PMU_HP_SLEEP_HP_REGULATOR1_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94)
+/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B    0x0000003FU
+#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M  (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V  0x0000003FU
+#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S  26
+
+/** PMU_HP_SLEEP_XTAL_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98)
+/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_XTAL    (BIT(31))
+#define PMU_HP_SLEEP_XPD_XTAL_M  (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S)
+#define PMU_HP_SLEEP_XPD_XTAL_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_XTAL_S  31
+
+/** PMU_HP_SLEEP_LP_REGULATOR0_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c)
+/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD    (BIT(21))
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M  (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S)
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V  0x00000001U
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S  21
+/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR_XPD    (BIT(22))
+#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M  (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S)
+#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V  0x00000001U
+#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S  22
+/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS    0x0000000FU
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M  (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S)
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V  0x0000000FU
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S  23
+/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS    0x0000001FU
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M  (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S)
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V  0x0000001FU
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S  27
+
+/** PMU_HP_SLEEP_LP_REGULATOR1_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0)
+/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B    0x0000003FU
+#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M  (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S)
+#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V  0x0000003FU
+#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S  26
+
+/** PMU_HP_SLEEP_LP_DIG_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8)
+/** PMU_HP_SLEEP_LP_PAD_SLP_SEL : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_PAD_SLP_SEL    (BIT(26))
+#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_M  (PMU_HP_SLEEP_LP_PAD_SLP_SEL_V << PMU_HP_SLEEP_LP_PAD_SLP_SEL_S)
+#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_V  0x00000001U
+#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_S  26
+/** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BOD_SOURCE_SEL    (BIT(27))
+#define PMU_HP_SLEEP_BOD_SOURCE_SEL_M  (PMU_HP_SLEEP_BOD_SOURCE_SEL_V << PMU_HP_SLEEP_BOD_SOURCE_SEL_S)
+#define PMU_HP_SLEEP_BOD_SOURCE_SEL_V  0x00000001U
+#define PMU_HP_SLEEP_BOD_SOURCE_SEL_S  27
+/** PMU_HP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_VDDBAT_MODE    0x00000003U
+#define PMU_HP_SLEEP_VDDBAT_MODE_M  (PMU_HP_SLEEP_VDDBAT_MODE_V << PMU_HP_SLEEP_VDDBAT_MODE_S)
+#define PMU_HP_SLEEP_VDDBAT_MODE_V  0x00000003U
+#define PMU_HP_SLEEP_VDDBAT_MODE_S  28
+/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_MEM_DSLP    (BIT(30))
+#define PMU_HP_SLEEP_LP_MEM_DSLP_M  (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S)
+#define PMU_HP_SLEEP_LP_MEM_DSLP_V  0x00000001U
+#define PMU_HP_SLEEP_LP_MEM_DSLP_S  30
+/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN    (BIT(31))
+#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M  (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S)
+#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S  31
+
+/** PMU_HP_SLEEP_LP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac)
+/** PMU_HP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_LPPLL    (BIT(27))
+#define PMU_HP_SLEEP_XPD_LPPLL_M  (PMU_HP_SLEEP_XPD_LPPLL_V << PMU_HP_SLEEP_XPD_LPPLL_S)
+#define PMU_HP_SLEEP_XPD_LPPLL_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_LPPLL_S  27
+/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_XTAL32K    (BIT(28))
+#define PMU_HP_SLEEP_XPD_XTAL32K_M  (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S)
+#define PMU_HP_SLEEP_XPD_XTAL32K_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_XTAL32K_S  28
+/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_RC32K    (BIT(29))
+#define PMU_HP_SLEEP_XPD_RC32K_M  (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S)
+#define PMU_HP_SLEEP_XPD_RC32K_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_RC32K_S  29
+/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_FOSC_CLK    (BIT(30))
+#define PMU_HP_SLEEP_XPD_FOSC_CLK_M  (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S)
+#define PMU_HP_SLEEP_XPD_FOSC_CLK_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_FOSC_CLK_S  30
+/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_OSC_CLK    (BIT(31))
+#define PMU_HP_SLEEP_PD_OSC_CLK_M  (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S)
+#define PMU_HP_SLEEP_PD_OSC_CLK_V  0x00000001U
+#define PMU_HP_SLEEP_PD_OSC_CLK_S  31
+
+/** PMU_LP_SLEEP_LP_REGULATOR0_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4)
+/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD    (BIT(21))
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M  (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S)
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V  0x00000001U
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S  21
+/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR_XPD    (BIT(22))
+#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M  (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S)
+#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V  0x00000001U
+#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S  22
+/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS    0x0000000FU
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M  (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S)
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V  0x0000000FU
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S  23
+/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS    0x0000001FU
+#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M  (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S)
+#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V  0x0000001FU
+#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S  27
+
+/** PMU_LP_SLEEP_LP_REGULATOR1_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8)
+/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B    0x0000003FU
+#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M  (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S)
+#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V  0x0000003FU
+#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S  26
+
+/** PMU_LP_SLEEP_XTAL_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc)
+/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_XTAL    (BIT(31))
+#define PMU_LP_SLEEP_XPD_XTAL_M  (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S)
+#define PMU_LP_SLEEP_XPD_XTAL_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_XTAL_S  31
+
+/** PMU_LP_SLEEP_LP_DIG_POWER_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0)
+/** PMU_LP_SLEEP_LP_PAD_SLP_SEL : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_PAD_SLP_SEL    (BIT(26))
+#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_M  (PMU_LP_SLEEP_LP_PAD_SLP_SEL_V << PMU_LP_SLEEP_LP_PAD_SLP_SEL_S)
+#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_V  0x00000001U
+#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_S  26
+/** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_BOD_SOURCE_SEL    (BIT(27))
+#define PMU_LP_SLEEP_BOD_SOURCE_SEL_M  (PMU_LP_SLEEP_BOD_SOURCE_SEL_V << PMU_LP_SLEEP_BOD_SOURCE_SEL_S)
+#define PMU_LP_SLEEP_BOD_SOURCE_SEL_V  0x00000001U
+#define PMU_LP_SLEEP_BOD_SOURCE_SEL_S  27
+/** PMU_LP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_VDDBAT_MODE    0x00000003U
+#define PMU_LP_SLEEP_VDDBAT_MODE_M  (PMU_LP_SLEEP_VDDBAT_MODE_V << PMU_LP_SLEEP_VDDBAT_MODE_S)
+#define PMU_LP_SLEEP_VDDBAT_MODE_V  0x00000003U
+#define PMU_LP_SLEEP_VDDBAT_MODE_S  28
+/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_MEM_DSLP    (BIT(30))
+#define PMU_LP_SLEEP_LP_MEM_DSLP_M  (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S)
+#define PMU_LP_SLEEP_LP_MEM_DSLP_V  0x00000001U
+#define PMU_LP_SLEEP_LP_MEM_DSLP_S  30
+/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN    (BIT(31))
+#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M  (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S)
+#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V  0x00000001U
+#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S  31
+
+/** PMU_LP_SLEEP_LP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4)
+/** PMU_LP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_LPPLL    (BIT(27))
+#define PMU_LP_SLEEP_XPD_LPPLL_M  (PMU_LP_SLEEP_XPD_LPPLL_V << PMU_LP_SLEEP_XPD_LPPLL_S)
+#define PMU_LP_SLEEP_XPD_LPPLL_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_LPPLL_S  27
+/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_XTAL32K    (BIT(28))
+#define PMU_LP_SLEEP_XPD_XTAL32K_M  (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S)
+#define PMU_LP_SLEEP_XPD_XTAL32K_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_XTAL32K_S  28
+/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_RC32K    (BIT(29))
+#define PMU_LP_SLEEP_XPD_RC32K_M  (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S)
+#define PMU_LP_SLEEP_XPD_RC32K_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_RC32K_S  29
+/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_FOSC_CLK    (BIT(30))
+#define PMU_LP_SLEEP_XPD_FOSC_CLK_M  (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S)
+#define PMU_LP_SLEEP_XPD_FOSC_CLK_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_FOSC_CLK_S  30
+/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_PD_OSC_CLK    (BIT(31))
+#define PMU_LP_SLEEP_PD_OSC_CLK_M  (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S)
+#define PMU_LP_SLEEP_PD_OSC_CLK_V  0x00000001U
+#define PMU_LP_SLEEP_PD_OSC_CLK_S  31
+
+/** PMU_LP_SLEEP_BIAS_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8)
+/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_BIAS    (BIT(25))
+#define PMU_LP_SLEEP_XPD_BIAS_M  (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S)
+#define PMU_LP_SLEEP_XPD_BIAS_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_BIAS_S  25
+/** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_DBG_ATTEN    0x0000000FU
+#define PMU_LP_SLEEP_DBG_ATTEN_M  (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S)
+#define PMU_LP_SLEEP_DBG_ATTEN_V  0x0000000FU
+#define PMU_LP_SLEEP_DBG_ATTEN_S  26
+/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_PD_CUR    (BIT(30))
+#define PMU_LP_SLEEP_PD_CUR_M  (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S)
+#define PMU_LP_SLEEP_PD_CUR_V  0x00000001U
+#define PMU_LP_SLEEP_PD_CUR_S  30
+/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_BIAS_SLEEP    (BIT(31))
+#define PMU_LP_SLEEP_BIAS_SLEEP_M  (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S)
+#define PMU_LP_SLEEP_BIAS_SLEEP_V  0x00000001U
+#define PMU_LP_SLEEP_BIAS_SLEEP_S  31
+
+/** PMU_IMM_HP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc)
+/** PMU_TIE_LOW_CALI_XTAL_ICG : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_CALI_XTAL_ICG    (BIT(0))
+#define PMU_TIE_LOW_CALI_XTAL_ICG_M  (PMU_TIE_LOW_CALI_XTAL_ICG_V << PMU_TIE_LOW_CALI_XTAL_ICG_S)
+#define PMU_TIE_LOW_CALI_XTAL_ICG_V  0x00000001U
+#define PMU_TIE_LOW_CALI_XTAL_ICG_S  0
+/** PMU_TIE_LOW_GLOBAL_PLL_ICG : WT; bitpos: [4:1]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_GLOBAL_PLL_ICG    0x0000000FU
+#define PMU_TIE_LOW_GLOBAL_PLL_ICG_M  (PMU_TIE_LOW_GLOBAL_PLL_ICG_V << PMU_TIE_LOW_GLOBAL_PLL_ICG_S)
+#define PMU_TIE_LOW_GLOBAL_PLL_ICG_V  0x0000000FU
+#define PMU_TIE_LOW_GLOBAL_PLL_ICG_S  1
+/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_GLOBAL_XTAL_ICG    (BIT(5))
+#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M  (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S)
+#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V  0x00000001U
+#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S  5
+/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_I2C_RETENTION    (BIT(6))
+#define PMU_TIE_LOW_I2C_RETENTION_M  (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S)
+#define PMU_TIE_LOW_I2C_RETENTION_V  0x00000001U
+#define PMU_TIE_LOW_I2C_RETENTION_S  6
+/** PMU_TIE_LOW_XPD_PLL_I2C : WT; bitpos: [10:7]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_PLL_I2C    0x0000000FU
+#define PMU_TIE_LOW_XPD_PLL_I2C_M  (PMU_TIE_LOW_XPD_PLL_I2C_V << PMU_TIE_LOW_XPD_PLL_I2C_S)
+#define PMU_TIE_LOW_XPD_PLL_I2C_V  0x0000000FU
+#define PMU_TIE_LOW_XPD_PLL_I2C_S  7
+/** PMU_TIE_LOW_XPD_PLL : WT; bitpos: [14:11]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_PLL    0x0000000FU
+#define PMU_TIE_LOW_XPD_PLL_M  (PMU_TIE_LOW_XPD_PLL_V << PMU_TIE_LOW_XPD_PLL_S)
+#define PMU_TIE_LOW_XPD_PLL_V  0x0000000FU
+#define PMU_TIE_LOW_XPD_PLL_S  11
+/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_XTAL    (BIT(15))
+#define PMU_TIE_LOW_XPD_XTAL_M  (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S)
+#define PMU_TIE_LOW_XPD_XTAL_V  0x00000001U
+#define PMU_TIE_LOW_XPD_XTAL_S  15
+/** PMU_TIE_HIGH_CALI_XTAL_ICG : R/W; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_CALI_XTAL_ICG    (BIT(16))
+#define PMU_TIE_HIGH_CALI_XTAL_ICG_M  (PMU_TIE_HIGH_CALI_XTAL_ICG_V << PMU_TIE_HIGH_CALI_XTAL_ICG_S)
+#define PMU_TIE_HIGH_CALI_XTAL_ICG_V  0x00000001U
+#define PMU_TIE_HIGH_CALI_XTAL_ICG_S  16
+/** PMU_TIE_HIGH_GLOBAL_PLL_ICG : WT; bitpos: [20:17]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_GLOBAL_PLL_ICG    0x0000000FU
+#define PMU_TIE_HIGH_GLOBAL_PLL_ICG_M  (PMU_TIE_HIGH_GLOBAL_PLL_ICG_V << PMU_TIE_HIGH_GLOBAL_PLL_ICG_S)
+#define PMU_TIE_HIGH_GLOBAL_PLL_ICG_V  0x0000000FU
+#define PMU_TIE_HIGH_GLOBAL_PLL_ICG_S  17
+/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG    (BIT(21))
+#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M  (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S)
+#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V  0x00000001U
+#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S  21
+/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_I2C_RETENTION    (BIT(22))
+#define PMU_TIE_HIGH_I2C_RETENTION_M  (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S)
+#define PMU_TIE_HIGH_I2C_RETENTION_V  0x00000001U
+#define PMU_TIE_HIGH_I2C_RETENTION_S  22
+/** PMU_TIE_HIGH_XPD_PLL_I2C : WT; bitpos: [26:23]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_PLL_I2C    0x0000000FU
+#define PMU_TIE_HIGH_XPD_PLL_I2C_M  (PMU_TIE_HIGH_XPD_PLL_I2C_V << PMU_TIE_HIGH_XPD_PLL_I2C_S)
+#define PMU_TIE_HIGH_XPD_PLL_I2C_V  0x0000000FU
+#define PMU_TIE_HIGH_XPD_PLL_I2C_S  23
+/** PMU_TIE_HIGH_XPD_PLL : WT; bitpos: [30:27]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_PLL    0x0000000FU
+#define PMU_TIE_HIGH_XPD_PLL_M  (PMU_TIE_HIGH_XPD_PLL_V << PMU_TIE_HIGH_XPD_PLL_S)
+#define PMU_TIE_HIGH_XPD_PLL_V  0x0000000FU
+#define PMU_TIE_HIGH_XPD_PLL_S  27
+/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_XTAL    (BIT(31))
+#define PMU_TIE_HIGH_XPD_XTAL_M  (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S)
+#define PMU_TIE_HIGH_XPD_XTAL_V  0x00000001U
+#define PMU_TIE_HIGH_XPD_XTAL_S  31
+
+/** PMU_IMM_SLEEP_SYSCLK_REG register
+ *  need_des
+ */
+#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0)
+/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_UPDATE_DIG_ICG_SWITCH    (BIT(28))
+#define PMU_UPDATE_DIG_ICG_SWITCH_M  (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S)
+#define PMU_UPDATE_DIG_ICG_SWITCH_V  0x00000001U
+#define PMU_UPDATE_DIG_ICG_SWITCH_S  28
+/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_ICG_SLP_SEL    (BIT(29))
+#define PMU_TIE_LOW_ICG_SLP_SEL_M  (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S)
+#define PMU_TIE_LOW_ICG_SLP_SEL_V  0x00000001U
+#define PMU_TIE_LOW_ICG_SLP_SEL_S  29
+/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_ICG_SLP_SEL    (BIT(30))
+#define PMU_TIE_HIGH_ICG_SLP_SEL_M  (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S)
+#define PMU_TIE_HIGH_ICG_SLP_SEL_V  0x00000001U
+#define PMU_TIE_HIGH_ICG_SLP_SEL_S  30
+/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_UPDATE_DIG_SYS_CLK_SEL    (BIT(31))
+#define PMU_UPDATE_DIG_SYS_CLK_SEL_M  (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S)
+#define PMU_UPDATE_DIG_SYS_CLK_SEL_V  0x00000001U
+#define PMU_UPDATE_DIG_SYS_CLK_SEL_S  31
+
+/** PMU_IMM_HP_FUNC_ICG_REG register
+ *  need_des
+ */
+#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4)
+/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_UPDATE_DIG_ICG_FUNC_EN    (BIT(31))
+#define PMU_UPDATE_DIG_ICG_FUNC_EN_M  (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S)
+#define PMU_UPDATE_DIG_ICG_FUNC_EN_V  0x00000001U
+#define PMU_UPDATE_DIG_ICG_FUNC_EN_S  31
+
+/** PMU_IMM_HP_APB_ICG_REG register
+ *  need_des
+ */
+#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8)
+/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_UPDATE_DIG_ICG_APB_EN    (BIT(31))
+#define PMU_UPDATE_DIG_ICG_APB_EN_M  (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S)
+#define PMU_UPDATE_DIG_ICG_APB_EN_V  0x00000001U
+#define PMU_UPDATE_DIG_ICG_APB_EN_S  31
+
+/** PMU_IMM_MODEM_ICG_REG register
+ *  need_des
+ */
+#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc)
+/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_UPDATE_DIG_ICG_MODEM_EN    (BIT(31))
+#define PMU_UPDATE_DIG_ICG_MODEM_EN_M  (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S)
+#define PMU_UPDATE_DIG_ICG_MODEM_EN_V  0x00000001U
+#define PMU_UPDATE_DIG_ICG_MODEM_EN_S  31
+
+/** PMU_IMM_LP_ICG_REG register
+ *  need_des
+ */
+#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0)
+/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_LP_ROOTCLK_SEL    (BIT(30))
+#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M  (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S)
+#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V  0x00000001U
+#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S  30
+/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_LP_ROOTCLK_SEL    (BIT(31))
+#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M  (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S)
+#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V  0x00000001U
+#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S  31
+
+/** PMU_IMM_PAD_HOLD_ALL_REG register
+ *  need_des
+ */
+#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4)
+/** PMU_PAD_SLP_SEL : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_PAD_SLP_SEL    (BIT(0))
+#define PMU_PAD_SLP_SEL_M  (PMU_PAD_SLP_SEL_V << PMU_PAD_SLP_SEL_S)
+#define PMU_PAD_SLP_SEL_V  0x00000001U
+#define PMU_PAD_SLP_SEL_S  0
+/** PMU_LP_PAD_HOLD_ALL : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_PAD_HOLD_ALL    (BIT(1))
+#define PMU_LP_PAD_HOLD_ALL_M  (PMU_LP_PAD_HOLD_ALL_V << PMU_LP_PAD_HOLD_ALL_S)
+#define PMU_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_LP_PAD_HOLD_ALL_S  1
+/** PMU_HP_PAD_HOLD_ALL : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_PAD_HOLD_ALL    (BIT(2))
+#define PMU_HP_PAD_HOLD_ALL_M  (PMU_HP_PAD_HOLD_ALL_V << PMU_HP_PAD_HOLD_ALL_S)
+#define PMU_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_PAD_HOLD_ALL_S  2
+/** PMU_TIE_HIGH_PAD_SLP_SEL : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_PAD_SLP_SEL    (BIT(26))
+#define PMU_TIE_HIGH_PAD_SLP_SEL_M  (PMU_TIE_HIGH_PAD_SLP_SEL_V << PMU_TIE_HIGH_PAD_SLP_SEL_S)
+#define PMU_TIE_HIGH_PAD_SLP_SEL_V  0x00000001U
+#define PMU_TIE_HIGH_PAD_SLP_SEL_S  26
+/** PMU_TIE_LOW_PAD_SLP_SEL : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_PAD_SLP_SEL    (BIT(27))
+#define PMU_TIE_LOW_PAD_SLP_SEL_M  (PMU_TIE_LOW_PAD_SLP_SEL_V << PMU_TIE_LOW_PAD_SLP_SEL_S)
+#define PMU_TIE_LOW_PAD_SLP_SEL_V  0x00000001U
+#define PMU_TIE_LOW_PAD_SLP_SEL_S  27
+/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL    (BIT(28))
+#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M  (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S)
+#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S  28
+/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_LP_PAD_HOLD_ALL    (BIT(29))
+#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M  (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S)
+#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S  29
+/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL    (BIT(30))
+#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M  (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S)
+#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S  30
+/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_HP_PAD_HOLD_ALL    (BIT(31))
+#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M  (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S)
+#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S  31
+
+/** PMU_IMM_I2C_ISO_REG register
+ *  need_des
+ */
+#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8)
+/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_I2C_ISO_EN    (BIT(30))
+#define PMU_TIE_HIGH_I2C_ISO_EN_M  (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S)
+#define PMU_TIE_HIGH_I2C_ISO_EN_V  0x00000001U
+#define PMU_TIE_HIGH_I2C_ISO_EN_S  30
+/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_I2C_ISO_EN    (BIT(31))
+#define PMU_TIE_LOW_I2C_ISO_EN_M  (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S)
+#define PMU_TIE_LOW_I2C_ISO_EN_V  0x00000001U
+#define PMU_TIE_LOW_I2C_ISO_EN_S  31
+
+/** PMU_POWER_WAIT_TIMER0_REG register
+ *  need_des
+ */
+#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec)
+/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_HP_POWERDOWN_TIMER    0x000001FFU
+#define PMU_DG_HP_POWERDOWN_TIMER_M  (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S)
+#define PMU_DG_HP_POWERDOWN_TIMER_V  0x000001FFU
+#define PMU_DG_HP_POWERDOWN_TIMER_S  5
+/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_HP_POWERUP_TIMER    0x000001FFU
+#define PMU_DG_HP_POWERUP_TIMER_M  (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S)
+#define PMU_DG_HP_POWERUP_TIMER_V  0x000001FFU
+#define PMU_DG_HP_POWERUP_TIMER_S  14
+/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_HP_WAIT_TIMER    0x000001FFU
+#define PMU_DG_HP_WAIT_TIMER_M  (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S)
+#define PMU_DG_HP_WAIT_TIMER_V  0x000001FFU
+#define PMU_DG_HP_WAIT_TIMER_S  23
+
+/** PMU_POWER_WAIT_TIMER1_REG register
+ *  need_des
+ */
+#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0)
+/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_LP_POWERDOWN_TIMER    0x000001FFU
+#define PMU_DG_LP_POWERDOWN_TIMER_M  (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S)
+#define PMU_DG_LP_POWERDOWN_TIMER_V  0x000001FFU
+#define PMU_DG_LP_POWERDOWN_TIMER_S  5
+/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_LP_POWERUP_TIMER    0x000001FFU
+#define PMU_DG_LP_POWERUP_TIMER_M  (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S)
+#define PMU_DG_LP_POWERUP_TIMER_V  0x000001FFU
+#define PMU_DG_LP_POWERUP_TIMER_S  14
+/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_LP_WAIT_TIMER    0x000001FFU
+#define PMU_DG_LP_WAIT_TIMER_M  (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S)
+#define PMU_DG_LP_WAIT_TIMER_V  0x000001FFU
+#define PMU_DG_LP_WAIT_TIMER_S  23
+
+/** PMU_POWER_PD_TOP_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4)
+/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_RESET    (BIT(0))
+#define PMU_FORCE_TOP_RESET_M  (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S)
+#define PMU_FORCE_TOP_RESET_V  0x00000001U
+#define PMU_FORCE_TOP_RESET_S  0
+/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_ISO    (BIT(1))
+#define PMU_FORCE_TOP_ISO_M  (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S)
+#define PMU_FORCE_TOP_ISO_V  0x00000001U
+#define PMU_FORCE_TOP_ISO_S  1
+/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_PU    (BIT(2))
+#define PMU_FORCE_TOP_PU_M  (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S)
+#define PMU_FORCE_TOP_PU_V  0x00000001U
+#define PMU_FORCE_TOP_PU_S  2
+/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_NO_RESET    (BIT(3))
+#define PMU_FORCE_TOP_NO_RESET_M  (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S)
+#define PMU_FORCE_TOP_NO_RESET_V  0x00000001U
+#define PMU_FORCE_TOP_NO_RESET_S  3
+/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_NO_ISO    (BIT(4))
+#define PMU_FORCE_TOP_NO_ISO_M  (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S)
+#define PMU_FORCE_TOP_NO_ISO_V  0x00000001U
+#define PMU_FORCE_TOP_NO_ISO_S  4
+/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_PD    (BIT(5))
+#define PMU_FORCE_TOP_PD_M  (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S)
+#define PMU_FORCE_TOP_PD_V  0x00000001U
+#define PMU_FORCE_TOP_PD_S  5
+
+/** PMU_POWER_PD_CNNT_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_CNNT_CNTL_REG (DR_REG_PMU_BASE + 0xf8)
+/** PMU_FORCE_CNNT_RESET : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_RESET    (BIT(0))
+#define PMU_FORCE_CNNT_RESET_M  (PMU_FORCE_CNNT_RESET_V << PMU_FORCE_CNNT_RESET_S)
+#define PMU_FORCE_CNNT_RESET_V  0x00000001U
+#define PMU_FORCE_CNNT_RESET_S  0
+/** PMU_FORCE_CNNT_ISO : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_ISO    (BIT(1))
+#define PMU_FORCE_CNNT_ISO_M  (PMU_FORCE_CNNT_ISO_V << PMU_FORCE_CNNT_ISO_S)
+#define PMU_FORCE_CNNT_ISO_V  0x00000001U
+#define PMU_FORCE_CNNT_ISO_S  1
+/** PMU_FORCE_CNNT_PU : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_PU    (BIT(2))
+#define PMU_FORCE_CNNT_PU_M  (PMU_FORCE_CNNT_PU_V << PMU_FORCE_CNNT_PU_S)
+#define PMU_FORCE_CNNT_PU_V  0x00000001U
+#define PMU_FORCE_CNNT_PU_S  2
+/** PMU_FORCE_CNNT_NO_RESET : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_NO_RESET    (BIT(3))
+#define PMU_FORCE_CNNT_NO_RESET_M  (PMU_FORCE_CNNT_NO_RESET_V << PMU_FORCE_CNNT_NO_RESET_S)
+#define PMU_FORCE_CNNT_NO_RESET_V  0x00000001U
+#define PMU_FORCE_CNNT_NO_RESET_S  3
+/** PMU_FORCE_CNNT_NO_ISO : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_NO_ISO    (BIT(4))
+#define PMU_FORCE_CNNT_NO_ISO_M  (PMU_FORCE_CNNT_NO_ISO_V << PMU_FORCE_CNNT_NO_ISO_S)
+#define PMU_FORCE_CNNT_NO_ISO_V  0x00000001U
+#define PMU_FORCE_CNNT_NO_ISO_S  4
+/** PMU_FORCE_CNNT_PD : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_PD    (BIT(5))
+#define PMU_FORCE_CNNT_PD_M  (PMU_FORCE_CNNT_PD_V << PMU_FORCE_CNNT_PD_S)
+#define PMU_FORCE_CNNT_PD_V  0x00000001U
+#define PMU_FORCE_CNNT_PD_S  5
+
+/** PMU_POWER_PD_HPMEM_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_HPMEM_CNTL_REG (DR_REG_PMU_BASE + 0xfc)
+/** PMU_FORCE_HP_MEM_RESET : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_RESET    (BIT(0))
+#define PMU_FORCE_HP_MEM_RESET_M  (PMU_FORCE_HP_MEM_RESET_V << PMU_FORCE_HP_MEM_RESET_S)
+#define PMU_FORCE_HP_MEM_RESET_V  0x00000001U
+#define PMU_FORCE_HP_MEM_RESET_S  0
+/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_ISO    (BIT(1))
+#define PMU_FORCE_HP_MEM_ISO_M  (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S)
+#define PMU_FORCE_HP_MEM_ISO_V  0x00000001U
+#define PMU_FORCE_HP_MEM_ISO_S  1
+/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_PU    (BIT(2))
+#define PMU_FORCE_HP_MEM_PU_M  (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S)
+#define PMU_FORCE_HP_MEM_PU_V  0x00000001U
+#define PMU_FORCE_HP_MEM_PU_S  2
+/** PMU_FORCE_HP_MEM_NO_RESET : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_NO_RESET    (BIT(3))
+#define PMU_FORCE_HP_MEM_NO_RESET_M  (PMU_FORCE_HP_MEM_NO_RESET_V << PMU_FORCE_HP_MEM_NO_RESET_S)
+#define PMU_FORCE_HP_MEM_NO_RESET_V  0x00000001U
+#define PMU_FORCE_HP_MEM_NO_RESET_S  3
+/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_NO_ISO    (BIT(4))
+#define PMU_FORCE_HP_MEM_NO_ISO_M  (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S)
+#define PMU_FORCE_HP_MEM_NO_ISO_V  0x00000001U
+#define PMU_FORCE_HP_MEM_NO_ISO_S  4
+/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_PD    (BIT(5))
+#define PMU_FORCE_HP_MEM_PD_M  (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S)
+#define PMU_FORCE_HP_MEM_PD_V  0x00000001U
+#define PMU_FORCE_HP_MEM_PD_S  5
+
+/** PMU_POWER_PD_TOP_MASK_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_TOP_MASK_REG (DR_REG_PMU_BASE + 0x100)
+/** PMU_XPD_TOP_MASK : R/W; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_TOP_MASK    0x0000001FU
+#define PMU_XPD_TOP_MASK_M  (PMU_XPD_TOP_MASK_V << PMU_XPD_TOP_MASK_S)
+#define PMU_XPD_TOP_MASK_V  0x0000001FU
+#define PMU_XPD_TOP_MASK_S  0
+/** PMU_PD_TOP_MASK : R/W; bitpos: [31:27]; default: 0;
+ *  need_des
+ */
+#define PMU_PD_TOP_MASK    0x0000001FU
+#define PMU_PD_TOP_MASK_M  (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S)
+#define PMU_PD_TOP_MASK_V  0x0000001FU
+#define PMU_PD_TOP_MASK_S  27
+
+/** PMU_POWER_PD_CNNT_MASK_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_CNNT_MASK_REG (DR_REG_PMU_BASE + 0x104)
+/** PMU_XPD_CNNT_MASK : R/W; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_CNNT_MASK    0x0000001FU
+#define PMU_XPD_CNNT_MASK_M  (PMU_XPD_CNNT_MASK_V << PMU_XPD_CNNT_MASK_S)
+#define PMU_XPD_CNNT_MASK_V  0x0000001FU
+#define PMU_XPD_CNNT_MASK_S  0
+/** PMU_PD_CNNT_MASK : R/W; bitpos: [31:27]; default: 0;
+ *  need_des
+ */
+#define PMU_PD_CNNT_MASK    0x0000001FU
+#define PMU_PD_CNNT_MASK_M  (PMU_PD_CNNT_MASK_V << PMU_PD_CNNT_MASK_S)
+#define PMU_PD_CNNT_MASK_V  0x0000001FU
+#define PMU_PD_CNNT_MASK_S  27
+
+/** PMU_POWER_PD_HPMEM_MASK_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_HPMEM_MASK_REG (DR_REG_PMU_BASE + 0x108)
+/** PMU_XPD_HP_MEM_MASK : R/W; bitpos: [5:0]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_HP_MEM_MASK    0x0000003FU
+#define PMU_XPD_HP_MEM_MASK_M  (PMU_XPD_HP_MEM_MASK_V << PMU_XPD_HP_MEM_MASK_S)
+#define PMU_XPD_HP_MEM_MASK_V  0x0000003FU
+#define PMU_XPD_HP_MEM_MASK_S  0
+/** PMU_PD_HP_MEM_MASK : R/W; bitpos: [31:26]; default: 0;
+ *  need_des
+ */
+#define PMU_PD_HP_MEM_MASK    0x0000003FU
+#define PMU_PD_HP_MEM_MASK_M  (PMU_PD_HP_MEM_MASK_V << PMU_PD_HP_MEM_MASK_S)
+#define PMU_PD_HP_MEM_MASK_V  0x0000003FU
+#define PMU_PD_HP_MEM_MASK_S  26
+
+/** PMU_POWER_DCDC_SWITCH_REG register
+ *  need_des
+ */
+#define PMU_POWER_DCDC_SWITCH_REG (DR_REG_PMU_BASE + 0x10c)
+/** PMU_FORCE_DCDC_SWITCH_PU : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_DCDC_SWITCH_PU    (BIT(0))
+#define PMU_FORCE_DCDC_SWITCH_PU_M  (PMU_FORCE_DCDC_SWITCH_PU_V << PMU_FORCE_DCDC_SWITCH_PU_S)
+#define PMU_FORCE_DCDC_SWITCH_PU_V  0x00000001U
+#define PMU_FORCE_DCDC_SWITCH_PU_S  0
+/** PMU_FORCE_DCDC_SWITCH_PD : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_DCDC_SWITCH_PD    (BIT(1))
+#define PMU_FORCE_DCDC_SWITCH_PD_M  (PMU_FORCE_DCDC_SWITCH_PD_V << PMU_FORCE_DCDC_SWITCH_PD_S)
+#define PMU_FORCE_DCDC_SWITCH_PD_V  0x00000001U
+#define PMU_FORCE_DCDC_SWITCH_PD_S  1
+
+/** PMU_POWER_PD_LPPERI_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x110)
+/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_RESET    (BIT(0))
+#define PMU_FORCE_LP_PERI_RESET_M  (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S)
+#define PMU_FORCE_LP_PERI_RESET_V  0x00000001U
+#define PMU_FORCE_LP_PERI_RESET_S  0
+/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_ISO    (BIT(1))
+#define PMU_FORCE_LP_PERI_ISO_M  (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S)
+#define PMU_FORCE_LP_PERI_ISO_V  0x00000001U
+#define PMU_FORCE_LP_PERI_ISO_S  1
+/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_PU    (BIT(2))
+#define PMU_FORCE_LP_PERI_PU_M  (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S)
+#define PMU_FORCE_LP_PERI_PU_V  0x00000001U
+#define PMU_FORCE_LP_PERI_PU_S  2
+/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_NO_RESET    (BIT(3))
+#define PMU_FORCE_LP_PERI_NO_RESET_M  (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S)
+#define PMU_FORCE_LP_PERI_NO_RESET_V  0x00000001U
+#define PMU_FORCE_LP_PERI_NO_RESET_S  3
+/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_NO_ISO    (BIT(4))
+#define PMU_FORCE_LP_PERI_NO_ISO_M  (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S)
+#define PMU_FORCE_LP_PERI_NO_ISO_V  0x00000001U
+#define PMU_FORCE_LP_PERI_NO_ISO_S  4
+/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_PD    (BIT(5))
+#define PMU_FORCE_LP_PERI_PD_M  (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S)
+#define PMU_FORCE_LP_PERI_PD_V  0x00000001U
+#define PMU_FORCE_LP_PERI_PD_S  5
+
+/** PMU_POWER_PD_LPPERI_MASK_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_LPPERI_MASK_REG (DR_REG_PMU_BASE + 0x114)
+/** PMU_XPD_LP_PERI_MASK : R/W; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_LP_PERI_MASK    0x0000001FU
+#define PMU_XPD_LP_PERI_MASK_M  (PMU_XPD_LP_PERI_MASK_V << PMU_XPD_LP_PERI_MASK_S)
+#define PMU_XPD_LP_PERI_MASK_V  0x0000001FU
+#define PMU_XPD_LP_PERI_MASK_S  0
+/** PMU_PD_LP_PERI_MASK : R/W; bitpos: [31:27]; default: 0;
+ *  need_des
+ */
+#define PMU_PD_LP_PERI_MASK    0x0000001FU
+#define PMU_PD_LP_PERI_MASK_M  (PMU_PD_LP_PERI_MASK_V << PMU_PD_LP_PERI_MASK_S)
+#define PMU_PD_LP_PERI_MASK_V  0x0000001FU
+#define PMU_PD_LP_PERI_MASK_S  27
+
+/** PMU_POWER_HP_PAD_REG register
+ *  need_des
+ */
+#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118)
+/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_PAD_NO_ISO_ALL    (BIT(0))
+#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M  (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S)
+#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V  0x00000001U
+#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S  0
+/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_PAD_ISO_ALL    (BIT(1))
+#define PMU_FORCE_HP_PAD_ISO_ALL_M  (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S)
+#define PMU_FORCE_HP_PAD_ISO_ALL_V  0x00000001U
+#define PMU_FORCE_HP_PAD_ISO_ALL_S  1
+
+/** PMU_POWER_CK_WAIT_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c)
+/** PMU_PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256;
+ *  need_des
+ */
+#define PMU_PMU_WAIT_XTL_STABLE    0x0000FFFFU
+#define PMU_PMU_WAIT_XTL_STABLE_M  (PMU_PMU_WAIT_XTL_STABLE_V << PMU_PMU_WAIT_XTL_STABLE_S)
+#define PMU_PMU_WAIT_XTL_STABLE_V  0x0000FFFFU
+#define PMU_PMU_WAIT_XTL_STABLE_S  0
+/** PMU_PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256;
+ *  need_des
+ */
+#define PMU_PMU_WAIT_PLL_STABLE    0x0000FFFFU
+#define PMU_PMU_WAIT_PLL_STABLE_M  (PMU_PMU_WAIT_PLL_STABLE_V << PMU_PMU_WAIT_PLL_STABLE_S)
+#define PMU_PMU_WAIT_PLL_STABLE_V  0x0000FFFFU
+#define PMU_PMU_WAIT_PLL_STABLE_S  16
+
+/** PMU_SLP_WAKEUP_CNTL0_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120)
+/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_REQ    (BIT(31))
+#define PMU_SLEEP_REQ_M  (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S)
+#define PMU_SLEEP_REQ_V  0x00000001U
+#define PMU_SLEEP_REQ_S  31
+
+/** PMU_SLP_WAKEUP_CNTL1_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124)
+/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_REJECT_ENA    0x7FFFFFFFU
+#define PMU_SLEEP_REJECT_ENA_M  (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S)
+#define PMU_SLEEP_REJECT_ENA_V  0x7FFFFFFFU
+#define PMU_SLEEP_REJECT_ENA_S  0
+/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SLP_REJECT_EN    (BIT(31))
+#define PMU_SLP_REJECT_EN_M  (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S)
+#define PMU_SLP_REJECT_EN_V  0x00000001U
+#define PMU_SLP_REJECT_EN_S  31
+
+/** PMU_SLP_WAKEUP_CNTL2_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128)
+/** PMU_WAKEUP_ENA : R/W; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_WAKEUP_ENA    0x7FFFFFFFU
+#define PMU_WAKEUP_ENA_M  (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S)
+#define PMU_WAKEUP_ENA_V  0x7FFFFFFFU
+#define PMU_WAKEUP_ENA_S  0
+
+/** PMU_SLP_WAKEUP_CNTL3_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c)
+/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_MIN_SLP_VAL    0x000000FFU
+#define PMU_LP_MIN_SLP_VAL_M  (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S)
+#define PMU_LP_MIN_SLP_VAL_V  0x000000FFU
+#define PMU_LP_MIN_SLP_VAL_S  0
+/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MIN_SLP_VAL    0x000000FFU
+#define PMU_HP_MIN_SLP_VAL_M  (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S)
+#define PMU_HP_MIN_SLP_VAL_V  0x000000FFU
+#define PMU_HP_MIN_SLP_VAL_S  8
+/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_PRT_SEL    0x00000003U
+#define PMU_SLEEP_PRT_SEL_M  (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S)
+#define PMU_SLEEP_PRT_SEL_V  0x00000003U
+#define PMU_SLEEP_PRT_SEL_S  16
+
+/** PMU_SLP_WAKEUP_CNTL4_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130)
+/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SLP_REJECT_CAUSE_CLR    (BIT(31))
+#define PMU_SLP_REJECT_CAUSE_CLR_M  (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S)
+#define PMU_SLP_REJECT_CAUSE_CLR_V  0x00000001U
+#define PMU_SLP_REJECT_CAUSE_CLR_S  31
+
+/** PMU_SLP_WAKEUP_CNTL5_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134)
+/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128;
+ *  need_des
+ */
+#define PMU_MODEM_WAIT_TARGET    0x000FFFFFU
+#define PMU_MODEM_WAIT_TARGET_M  (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S)
+#define PMU_MODEM_WAIT_TARGET_V  0x000FFFFFU
+#define PMU_MODEM_WAIT_TARGET_S  0
+/** PMU_LP_ANA_WAIT_TARGET_EXPAND : R/W; bitpos: [23:22]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_ANA_WAIT_TARGET_EXPAND    0x00000003U
+#define PMU_LP_ANA_WAIT_TARGET_EXPAND_M  (PMU_LP_ANA_WAIT_TARGET_EXPAND_V << PMU_LP_ANA_WAIT_TARGET_EXPAND_S)
+#define PMU_LP_ANA_WAIT_TARGET_EXPAND_V  0x00000003U
+#define PMU_LP_ANA_WAIT_TARGET_EXPAND_S  22
+/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_ANA_WAIT_TARGET    0x000000FFU
+#define PMU_LP_ANA_WAIT_TARGET_M  (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S)
+#define PMU_LP_ANA_WAIT_TARGET_V  0x000000FFU
+#define PMU_LP_ANA_WAIT_TARGET_S  24
+
+/** PMU_SLP_WAKEUP_CNTL6_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138)
+/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_WAIT    0x000FFFFFU
+#define PMU_SOC_WAKEUP_WAIT_M  (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S)
+#define PMU_SOC_WAKEUP_WAIT_V  0x000FFFFFU
+#define PMU_SOC_WAKEUP_WAIT_S  0
+/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_WAIT_CFG    0x00000003U
+#define PMU_SOC_WAKEUP_WAIT_CFG_M  (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S)
+#define PMU_SOC_WAKEUP_WAIT_CFG_V  0x00000003U
+#define PMU_SOC_WAKEUP_WAIT_CFG_S  30
+
+/** PMU_SLP_WAKEUP_CNTL7_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c)
+/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1;
+ *  need_des
+ */
+#define PMU_ANA_WAIT_TARGET    0x0000FFFFU
+#define PMU_ANA_WAIT_TARGET_M  (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S)
+#define PMU_ANA_WAIT_TARGET_V  0x0000FFFFU
+#define PMU_ANA_WAIT_TARGET_S  16
+
+/** PMU_SLP_WAKEUP_CNTL8_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL8_REG (DR_REG_PMU_BASE + 0x140)
+/** PMU_LP_LITE_WAKEUP_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_LITE_WAKEUP_ENA    (BIT(31))
+#define PMU_LP_LITE_WAKEUP_ENA_M  (PMU_LP_LITE_WAKEUP_ENA_V << PMU_LP_LITE_WAKEUP_ENA_S)
+#define PMU_LP_LITE_WAKEUP_ENA_V  0x00000001U
+#define PMU_LP_LITE_WAKEUP_ENA_S  31
+
+/** PMU_SLP_WAKEUP_STATUS0_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x144)
+/** PMU_WAKEUP_CAUSE : RO; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_WAKEUP_CAUSE    0x7FFFFFFFU
+#define PMU_WAKEUP_CAUSE_M  (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S)
+#define PMU_WAKEUP_CAUSE_V  0x7FFFFFFFU
+#define PMU_WAKEUP_CAUSE_S  0
+
+/** PMU_SLP_WAKEUP_STATUS1_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x148)
+/** PMU_REJECT_CAUSE : RO; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_REJECT_CAUSE    0x7FFFFFFFU
+#define PMU_REJECT_CAUSE_M  (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S)
+#define PMU_REJECT_CAUSE_V  0x7FFFFFFFU
+#define PMU_REJECT_CAUSE_S  0
+
+/** PMU_SLP_WAKEUP_STATUS2_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_STATUS2_REG (DR_REG_PMU_BASE + 0x14c)
+/** PMU_LP_LITE_WAKEUP_CAUSE : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_LITE_WAKEUP_CAUSE    (BIT(31))
+#define PMU_LP_LITE_WAKEUP_CAUSE_M  (PMU_LP_LITE_WAKEUP_CAUSE_V << PMU_LP_LITE_WAKEUP_CAUSE_S)
+#define PMU_LP_LITE_WAKEUP_CAUSE_V  0x00000001U
+#define PMU_LP_LITE_WAKEUP_CAUSE_S  31
+
+/** PMU_HP_CK_POWERON_REG register
+ *  need_des
+ */
+#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x150)
+/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50;
+ *  need_des
+ */
+#define PMU_I2C_POR_WAIT_TARGET    0x000000FFU
+#define PMU_I2C_POR_WAIT_TARGET_M  (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S)
+#define PMU_I2C_POR_WAIT_TARGET_V  0x000000FFU
+#define PMU_I2C_POR_WAIT_TARGET_S  0
+
+/** PMU_HP_CK_CNTL_REG register
+ *  need_des
+ */
+#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x154)
+/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10;
+ *  need_des
+ */
+#define PMU_MODIFY_ICG_CNTL_WAIT    0x000000FFU
+#define PMU_MODIFY_ICG_CNTL_WAIT_M  (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S)
+#define PMU_MODIFY_ICG_CNTL_WAIT_V  0x000000FFU
+#define PMU_MODIFY_ICG_CNTL_WAIT_S  0
+/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10;
+ *  need_des
+ */
+#define PMU_SWITCH_ICG_CNTL_WAIT    0x000000FFU
+#define PMU_SWITCH_ICG_CNTL_WAIT_M  (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S)
+#define PMU_SWITCH_ICG_CNTL_WAIT_V  0x000000FFU
+#define PMU_SWITCH_ICG_CNTL_WAIT_S  8
+
+/** PMU_POR_STATUS_REG register
+ *  need_des
+ */
+#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x158)
+/** PMU_POR_DONE : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_POR_DONE    (BIT(31))
+#define PMU_POR_DONE_M  (PMU_POR_DONE_V << PMU_POR_DONE_S)
+#define PMU_POR_DONE_V  0x00000001U
+#define PMU_POR_DONE_S  31
+
+/** PMU_RF_PWC_REG register
+ *  need_des
+ */
+#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x15c)
+/** PMU_MSPI_PHY_XPD : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_MSPI_PHY_XPD    (BIT(24))
+#define PMU_MSPI_PHY_XPD_M  (PMU_MSPI_PHY_XPD_V << PMU_MSPI_PHY_XPD_S)
+#define PMU_MSPI_PHY_XPD_V  0x00000001U
+#define PMU_MSPI_PHY_XPD_S  24
+/** PMU_SDIO_PLL_XPD : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_SDIO_PLL_XPD    (BIT(25))
+#define PMU_SDIO_PLL_XPD_M  (PMU_SDIO_PLL_XPD_V << PMU_SDIO_PLL_XPD_S)
+#define PMU_SDIO_PLL_XPD_V  0x00000001U
+#define PMU_SDIO_PLL_XPD_S  25
+/** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_PERIF_I2C_RSTB    (BIT(26))
+#define PMU_PERIF_I2C_RSTB_M  (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S)
+#define PMU_PERIF_I2C_RSTB_V  0x00000001U
+#define PMU_PERIF_I2C_RSTB_S  26
+/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1;
+ *  need_des
+ */
+#define PMU_XPD_PERIF_I2C    (BIT(27))
+#define PMU_XPD_PERIF_I2C_M  (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S)
+#define PMU_XPD_PERIF_I2C_V  0x00000001U
+#define PMU_XPD_PERIF_I2C_S  27
+/** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_TXRF_I2C    (BIT(28))
+#define PMU_XPD_TXRF_I2C_M  (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S)
+#define PMU_XPD_TXRF_I2C_V  0x00000001U
+#define PMU_XPD_TXRF_I2C_S  28
+/** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_RFRX_PBUS    (BIT(29))
+#define PMU_XPD_RFRX_PBUS_M  (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S)
+#define PMU_XPD_RFRX_PBUS_V  0x00000001U
+#define PMU_XPD_RFRX_PBUS_S  29
+/** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_CKGEN_I2C    (BIT(30))
+#define PMU_XPD_CKGEN_I2C_M  (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S)
+#define PMU_XPD_CKGEN_I2C_V  0x00000001U
+#define PMU_XPD_CKGEN_I2C_S  30
+
+/** PMU_BACKUP_CFG_REG register
+ *  need_des
+ */
+#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x160)
+/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_BACKUP_SYS_CLK_NO_DIV    (BIT(31))
+#define PMU_BACKUP_SYS_CLK_NO_DIV_M  (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S)
+#define PMU_BACKUP_SYS_CLK_NO_DIV_V  0x00000001U
+#define PMU_BACKUP_SYS_CLK_NO_DIV_S  31
+
+/** PMU_INT_RAW_REG register
+ *  need_des
+ */
+#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x164)
+/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_M  (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_M  (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_M  (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_M  (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_M  (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_M  (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_M  (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_M  (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_M  (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_M  (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_M  (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_M  (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_S  25
+/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_EXC_INT_RAW    (BIT(27))
+#define PMU_LP_CPU_EXC_INT_RAW_M  (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S)
+#define PMU_LP_CPU_EXC_INT_RAW_V  0x00000001U
+#define PMU_LP_CPU_EXC_INT_RAW_S  27
+/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_SDIO_IDLE_INT_RAW    (BIT(28))
+#define PMU_SDIO_IDLE_INT_RAW_M  (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S)
+#define PMU_SDIO_IDLE_INT_RAW_V  0x00000001U
+#define PMU_SDIO_IDLE_INT_RAW_S  28
+/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SW_INT_RAW    (BIT(29))
+#define PMU_SW_INT_RAW_M  (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S)
+#define PMU_SW_INT_RAW_V  0x00000001U
+#define PMU_SW_INT_RAW_S  29
+/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_SLEEP_REJECT_INT_RAW    (BIT(30))
+#define PMU_SOC_SLEEP_REJECT_INT_RAW_M  (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S)
+#define PMU_SOC_SLEEP_REJECT_INT_RAW_V  0x00000001U
+#define PMU_SOC_SLEEP_REJECT_INT_RAW_S  30
+/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_INT_RAW    (BIT(31))
+#define PMU_SOC_WAKEUP_INT_RAW_M  (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S)
+#define PMU_SOC_WAKEUP_INT_RAW_V  0x00000001U
+#define PMU_SOC_WAKEUP_INT_RAW_S  31
+
+/** PMU_HP_INT_ST_REG register
+ *  need_des
+ */
+#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x168)
+/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_M  (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_M  (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_M  (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_M  (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_M  (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_M  (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_M  (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_M  (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_M  (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_M  (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_M  (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_M  (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_S  25
+/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_EXC_INT_ST    (BIT(27))
+#define PMU_LP_CPU_EXC_INT_ST_M  (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S)
+#define PMU_LP_CPU_EXC_INT_ST_V  0x00000001U
+#define PMU_LP_CPU_EXC_INT_ST_S  27
+/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_SDIO_IDLE_INT_ST    (BIT(28))
+#define PMU_SDIO_IDLE_INT_ST_M  (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S)
+#define PMU_SDIO_IDLE_INT_ST_V  0x00000001U
+#define PMU_SDIO_IDLE_INT_ST_S  28
+/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SW_INT_ST    (BIT(29))
+#define PMU_SW_INT_ST_M  (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S)
+#define PMU_SW_INT_ST_V  0x00000001U
+#define PMU_SW_INT_ST_S  29
+/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_SLEEP_REJECT_INT_ST    (BIT(30))
+#define PMU_SOC_SLEEP_REJECT_INT_ST_M  (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S)
+#define PMU_SOC_SLEEP_REJECT_INT_ST_V  0x00000001U
+#define PMU_SOC_SLEEP_REJECT_INT_ST_S  30
+/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_INT_ST    (BIT(31))
+#define PMU_SOC_WAKEUP_INT_ST_M  (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S)
+#define PMU_SOC_WAKEUP_INT_ST_V  0x00000001U
+#define PMU_SOC_WAKEUP_INT_ST_S  31
+
+/** PMU_HP_INT_ENA_REG register
+ *  need_des
+ */
+#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x16c)
+/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_M  (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_M  (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_M  (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_M  (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_M  (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_M  (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_M  (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_M  (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_M  (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_M  (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_M  (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_M  (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_S  25
+/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_EXC_INT_ENA    (BIT(27))
+#define PMU_LP_CPU_EXC_INT_ENA_M  (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S)
+#define PMU_LP_CPU_EXC_INT_ENA_V  0x00000001U
+#define PMU_LP_CPU_EXC_INT_ENA_S  27
+/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_SDIO_IDLE_INT_ENA    (BIT(28))
+#define PMU_SDIO_IDLE_INT_ENA_M  (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S)
+#define PMU_SDIO_IDLE_INT_ENA_V  0x00000001U
+#define PMU_SDIO_IDLE_INT_ENA_S  28
+/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SW_INT_ENA    (BIT(29))
+#define PMU_SW_INT_ENA_M  (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S)
+#define PMU_SW_INT_ENA_V  0x00000001U
+#define PMU_SW_INT_ENA_S  29
+/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_SLEEP_REJECT_INT_ENA    (BIT(30))
+#define PMU_SOC_SLEEP_REJECT_INT_ENA_M  (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S)
+#define PMU_SOC_SLEEP_REJECT_INT_ENA_V  0x00000001U
+#define PMU_SOC_SLEEP_REJECT_INT_ENA_S  30
+/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_INT_ENA    (BIT(31))
+#define PMU_SOC_WAKEUP_INT_ENA_M  (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S)
+#define PMU_SOC_WAKEUP_INT_ENA_V  0x00000001U
+#define PMU_SOC_WAKEUP_INT_ENA_S  31
+
+/** PMU_HP_INT_CLR_REG register
+ *  need_des
+ */
+#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x170)
+/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_M  (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_M  (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_M  (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_M  (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_M  (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_M  (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_M  (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_M  (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_M  (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_M  (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_M  (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_M  (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_S  25
+/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_EXC_INT_CLR    (BIT(27))
+#define PMU_LP_CPU_EXC_INT_CLR_M  (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S)
+#define PMU_LP_CPU_EXC_INT_CLR_V  0x00000001U
+#define PMU_LP_CPU_EXC_INT_CLR_S  27
+/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_SDIO_IDLE_INT_CLR    (BIT(28))
+#define PMU_SDIO_IDLE_INT_CLR_M  (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S)
+#define PMU_SDIO_IDLE_INT_CLR_V  0x00000001U
+#define PMU_SDIO_IDLE_INT_CLR_S  28
+/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SW_INT_CLR    (BIT(29))
+#define PMU_SW_INT_CLR_M  (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S)
+#define PMU_SW_INT_CLR_V  0x00000001U
+#define PMU_SW_INT_CLR_S  29
+/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_SLEEP_REJECT_INT_CLR    (BIT(30))
+#define PMU_SOC_SLEEP_REJECT_INT_CLR_M  (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S)
+#define PMU_SOC_SLEEP_REJECT_INT_CLR_V  0x00000001U
+#define PMU_SOC_SLEEP_REJECT_INT_CLR_S  30
+/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_INT_CLR    (BIT(31))
+#define PMU_SOC_WAKEUP_INT_CLR_M  (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S)
+#define PMU_SOC_WAKEUP_INT_CLR_V  0x00000001U
+#define PMU_SOC_WAKEUP_INT_CLR_S  31
+
+/** PMU_LP_INT_RAW_REG register
+ *  need_des
+ */
+#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x174)
+/** PMU_LP_CPU_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW    (BIT(13))
+#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_M  (PMU_LP_CPU_SLEEP_REJECT_INT_RAW_V << PMU_LP_CPU_SLEEP_REJECT_INT_RAW_S)
+#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_V  0x00000001U
+#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_S  13
+/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_M  (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_M  (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_M  (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_M  (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_M  (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_M  (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_M  (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_M  (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_M  (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_M  (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_M  (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_M  (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_S  25
+/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_INT_RAW    (BIT(26))
+#define PMU_LP_CPU_WAKEUP_INT_RAW_M  (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S)
+#define PMU_LP_CPU_WAKEUP_INT_RAW_V  0x00000001U
+#define PMU_LP_CPU_WAKEUP_INT_RAW_S  26
+/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW    (BIT(27))
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S  27
+/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW    (BIT(28))
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S  28
+/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW    (BIT(29))
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S  29
+/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW    (BIT(30))
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S  30
+/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SW_TRIGGER_INT_RAW    (BIT(31))
+#define PMU_HP_SW_TRIGGER_INT_RAW_M  (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S)
+#define PMU_HP_SW_TRIGGER_INT_RAW_V  0x00000001U
+#define PMU_HP_SW_TRIGGER_INT_RAW_S  31
+
+/** PMU_LP_INT_ST_REG register
+ *  need_des
+ */
+#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x178)
+/** PMU_LP_CPU_SLEEP_REJECT_INT_ST : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ST    (BIT(13))
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_M  (PMU_LP_CPU_SLEEP_REJECT_INT_ST_V << PMU_LP_CPU_SLEEP_REJECT_INT_ST_S)
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_V  0x00000001U
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_S  13
+/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_M  (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_M  (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_M  (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_M  (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_M  (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_M  (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_M  (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_M  (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_M  (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_M  (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_M  (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_M  (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_S  25
+/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_INT_ST    (BIT(26))
+#define PMU_LP_CPU_WAKEUP_INT_ST_M  (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S)
+#define PMU_LP_CPU_WAKEUP_INT_ST_V  0x00000001U
+#define PMU_LP_CPU_WAKEUP_INT_ST_S  26
+/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST    (BIT(27))
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S  27
+/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST    (BIT(28))
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S  28
+/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST    (BIT(29))
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S  29
+/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST    (BIT(30))
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S  30
+/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SW_TRIGGER_INT_ST    (BIT(31))
+#define PMU_HP_SW_TRIGGER_INT_ST_M  (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S)
+#define PMU_HP_SW_TRIGGER_INT_ST_V  0x00000001U
+#define PMU_HP_SW_TRIGGER_INT_ST_S  31
+
+/** PMU_LP_INT_ENA_REG register
+ *  need_des
+ */
+#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x17c)
+/** PMU_LP_CPU_SLEEP_REJECT_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA    (BIT(13))
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_M  (PMU_LP_CPU_SLEEP_REJECT_INT_ENA_V << PMU_LP_CPU_SLEEP_REJECT_INT_ENA_S)
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_V  0x00000001U
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_S  13
+/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_M  (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_M  (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_M  (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_M  (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_M  (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_M  (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_M  (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_M  (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_M  (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_M  (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_M  (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_M  (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_S  25
+/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_INT_ENA    (BIT(26))
+#define PMU_LP_CPU_WAKEUP_INT_ENA_M  (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S)
+#define PMU_LP_CPU_WAKEUP_INT_ENA_V  0x00000001U
+#define PMU_LP_CPU_WAKEUP_INT_ENA_S  26
+/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA    (BIT(27))
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S  27
+/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA    (BIT(28))
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S  28
+/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA    (BIT(29))
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S  29
+/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA    (BIT(30))
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S  30
+/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SW_TRIGGER_INT_ENA    (BIT(31))
+#define PMU_HP_SW_TRIGGER_INT_ENA_M  (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S)
+#define PMU_HP_SW_TRIGGER_INT_ENA_V  0x00000001U
+#define PMU_HP_SW_TRIGGER_INT_ENA_S  31
+
+/** PMU_LP_INT_CLR_REG register
+ *  need_des
+ */
+#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x180)
+/** PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR    (BIT(13))
+#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_M  (PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_V << PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_S)
+#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_V  0x00000001U
+#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_S  13
+/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_M  (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_M  (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_M  (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_M  (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_M  (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_M  (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_M  (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_M  (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_M  (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_M  (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_M  (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_M  (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_S  25
+/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_INT_CLR    (BIT(26))
+#define PMU_LP_CPU_WAKEUP_INT_CLR_M  (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S)
+#define PMU_LP_CPU_WAKEUP_INT_CLR_V  0x00000001U
+#define PMU_LP_CPU_WAKEUP_INT_CLR_S  26
+/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR    (BIT(27))
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S  27
+/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR    (BIT(28))
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S  28
+/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR    (BIT(29))
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S  29
+/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR    (BIT(30))
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S  30
+/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SW_TRIGGER_INT_CLR    (BIT(31))
+#define PMU_HP_SW_TRIGGER_INT_CLR_M  (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S)
+#define PMU_HP_SW_TRIGGER_INT_CLR_V  0x00000001U
+#define PMU_HP_SW_TRIGGER_INT_CLR_S  31
+
+/** PMU_LP_CPU_PWR0_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x184)
+/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAITI_RDY    (BIT(0))
+#define PMU_LP_CPU_WAITI_RDY_M  (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S)
+#define PMU_LP_CPU_WAITI_RDY_V  0x00000001U
+#define PMU_LP_CPU_WAITI_RDY_S  0
+/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_STALL_RDY    (BIT(1))
+#define PMU_LP_CPU_STALL_RDY_M  (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S)
+#define PMU_LP_CPU_STALL_RDY_V  0x00000001U
+#define PMU_LP_CPU_STALL_RDY_S  1
+/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_FORCE_STALL    (BIT(18))
+#define PMU_LP_CPU_FORCE_STALL_M  (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S)
+#define PMU_LP_CPU_FORCE_STALL_V  0x00000001U
+#define PMU_LP_CPU_FORCE_STALL_S  18
+/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_WAITI_FLAG_EN    (BIT(19))
+#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M  (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S)
+#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V  0x00000001U
+#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S  19
+/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_STALL_FLAG_EN    (BIT(20))
+#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M  (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S)
+#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V  0x00000001U
+#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S  20
+/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_STALL_WAIT    0x000000FFU
+#define PMU_LP_CPU_SLP_STALL_WAIT_M  (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S)
+#define PMU_LP_CPU_SLP_STALL_WAIT_V  0x000000FFU
+#define PMU_LP_CPU_SLP_STALL_WAIT_S  21
+/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_STALL_EN    (BIT(29))
+#define PMU_LP_CPU_SLP_STALL_EN_M  (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S)
+#define PMU_LP_CPU_SLP_STALL_EN_V  0x00000001U
+#define PMU_LP_CPU_SLP_STALL_EN_S  29
+/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_RESET_EN    (BIT(30))
+#define PMU_LP_CPU_SLP_RESET_EN_M  (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S)
+#define PMU_LP_CPU_SLP_RESET_EN_V  0x00000001U
+#define PMU_LP_CPU_SLP_RESET_EN_S  30
+/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_BYPASS_INTR_EN    (BIT(31))
+#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M  (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S)
+#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V  0x00000001U
+#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S  31
+
+/** PMU_LP_CPU_PWR1_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x188)
+/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLEEP_REQ    (BIT(31))
+#define PMU_LP_CPU_SLEEP_REQ_M  (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S)
+#define PMU_LP_CPU_SLEEP_REQ_V  0x00000001U
+#define PMU_LP_CPU_SLEEP_REQ_S  31
+
+/** PMU_LP_CPU_PWR2_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR2_REG (DR_REG_PMU_BASE + 0x18c)
+/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_EN    0x7FFFFFFFU
+#define PMU_LP_CPU_WAKEUP_EN_M  (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S)
+#define PMU_LP_CPU_WAKEUP_EN_V  0x7FFFFFFFU
+#define PMU_LP_CPU_WAKEUP_EN_S  0
+
+/** PMU_LP_CPU_PWR3_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR3_REG (DR_REG_PMU_BASE + 0x190)
+/** PMU_LP_CPU_WAKEUP_CAUSE : RO; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_CAUSE    0x7FFFFFFFU
+#define PMU_LP_CPU_WAKEUP_CAUSE_M  (PMU_LP_CPU_WAKEUP_CAUSE_V << PMU_LP_CPU_WAKEUP_CAUSE_S)
+#define PMU_LP_CPU_WAKEUP_CAUSE_V  0x7FFFFFFFU
+#define PMU_LP_CPU_WAKEUP_CAUSE_S  0
+
+/** PMU_LP_CPU_PWR4_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR4_REG (DR_REG_PMU_BASE + 0x194)
+/** PMU_LP_CPU_REJECT_EN : R/W; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_REJECT_EN    0x7FFFFFFFU
+#define PMU_LP_CPU_REJECT_EN_M  (PMU_LP_CPU_REJECT_EN_V << PMU_LP_CPU_REJECT_EN_S)
+#define PMU_LP_CPU_REJECT_EN_V  0x7FFFFFFFU
+#define PMU_LP_CPU_REJECT_EN_S  0
+
+/** PMU_LP_CPU_PWR5_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR5_REG (DR_REG_PMU_BASE + 0x198)
+/** PMU_LP_CPU_REJECT_CAUSE : RO; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_REJECT_CAUSE    0x7FFFFFFFU
+#define PMU_LP_CPU_REJECT_CAUSE_M  (PMU_LP_CPU_REJECT_CAUSE_V << PMU_LP_CPU_REJECT_CAUSE_S)
+#define PMU_LP_CPU_REJECT_CAUSE_V  0x7FFFFFFFU
+#define PMU_LP_CPU_REJECT_CAUSE_S  0
+
+/** PMU_HP_LP_CPU_COMM_REG register
+ *  need_des
+ */
+#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x19c)
+/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_TRIGGER_HP    (BIT(30))
+#define PMU_LP_TRIGGER_HP_M  (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S)
+#define PMU_LP_TRIGGER_HP_V  0x00000001U
+#define PMU_LP_TRIGGER_HP_S  30
+/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_TRIGGER_LP    (BIT(31))
+#define PMU_HP_TRIGGER_LP_M  (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S)
+#define PMU_HP_TRIGGER_LP_V  0x00000001U
+#define PMU_HP_TRIGGER_LP_S  31
+
+/** PMU_HP_REGULATOR_CFG_REG register
+ *  need_des
+ */
+#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x1a0)
+/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_DIG_REGULATOR_EN_CAL    (BIT(31))
+#define PMU_DIG_REGULATOR_EN_CAL_M  (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S)
+#define PMU_DIG_REGULATOR_EN_CAL_V  0x00000001U
+#define PMU_DIG_REGULATOR_EN_CAL_S  31
+
+/** PMU_MAIN_STATE_REG register
+ *  need_des
+ */
+#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x1a4)
+/** PMU_ENABLE_CALI_PMU_CNTL : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define PMU_ENABLE_CALI_PMU_CNTL    (BIT(0))
+#define PMU_ENABLE_CALI_PMU_CNTL_M  (PMU_ENABLE_CALI_PMU_CNTL_V << PMU_ENABLE_CALI_PMU_CNTL_S)
+#define PMU_ENABLE_CALI_PMU_CNTL_V  0x00000001U
+#define PMU_ENABLE_CALI_PMU_CNTL_S  0
+/** PMU_PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1;
+ *  need_des
+ */
+#define PMU_PMU_MAIN_LAST_ST_STATE    0x0000007FU
+#define PMU_PMU_MAIN_LAST_ST_STATE_M  (PMU_PMU_MAIN_LAST_ST_STATE_V << PMU_PMU_MAIN_LAST_ST_STATE_S)
+#define PMU_PMU_MAIN_LAST_ST_STATE_V  0x0000007FU
+#define PMU_PMU_MAIN_LAST_ST_STATE_S  11
+/** PMU_PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4;
+ *  need_des
+ */
+#define PMU_PMU_MAIN_TAR_ST_STATE    0x0000007FU
+#define PMU_PMU_MAIN_TAR_ST_STATE_M  (PMU_PMU_MAIN_TAR_ST_STATE_V << PMU_PMU_MAIN_TAR_ST_STATE_S)
+#define PMU_PMU_MAIN_TAR_ST_STATE_V  0x0000007FU
+#define PMU_PMU_MAIN_TAR_ST_STATE_S  18
+/** PMU_PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 1;
+ *  need_des
+ */
+#define PMU_PMU_MAIN_CUR_ST_STATE    0x0000007FU
+#define PMU_PMU_MAIN_CUR_ST_STATE_M  (PMU_PMU_MAIN_CUR_ST_STATE_V << PMU_PMU_MAIN_CUR_ST_STATE_S)
+#define PMU_PMU_MAIN_CUR_ST_STATE_V  0x0000007FU
+#define PMU_PMU_MAIN_CUR_ST_STATE_S  25
+
+/** PMU_PWR_STATE_REG register
+ *  need_des
+ */
+#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x1a8)
+/** PMU_PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1;
+ *  need_des
+ */
+#define PMU_PMU_BACKUP_ST_STATE    0x0000001FU
+#define PMU_PMU_BACKUP_ST_STATE_M  (PMU_PMU_BACKUP_ST_STATE_V << PMU_PMU_BACKUP_ST_STATE_S)
+#define PMU_PMU_BACKUP_ST_STATE_V  0x0000001FU
+#define PMU_PMU_BACKUP_ST_STATE_S  13
+/** PMU_PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_LP_PWR_ST_STATE    0x0000001FU
+#define PMU_PMU_LP_PWR_ST_STATE_M  (PMU_PMU_LP_PWR_ST_STATE_V << PMU_PMU_LP_PWR_ST_STATE_S)
+#define PMU_PMU_LP_PWR_ST_STATE_V  0x0000001FU
+#define PMU_PMU_LP_PWR_ST_STATE_S  18
+/** PMU_PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1;
+ *  need_des
+ */
+#define PMU_PMU_HP_PWR_ST_STATE    0x000001FFU
+#define PMU_PMU_HP_PWR_ST_STATE_M  (PMU_PMU_HP_PWR_ST_STATE_V << PMU_PMU_HP_PWR_ST_STATE_S)
+#define PMU_PMU_HP_PWR_ST_STATE_V  0x000001FFU
+#define PMU_PMU_HP_PWR_ST_STATE_S  23
+
+/** PMU_CLK_STATE0_REG register
+ *  need_des
+ */
+#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac)
+/** PMU_STABLE_XPD_PLL_STATE : RO; bitpos: [2:0]; default: 0;
+ *  need_des
+ */
+#define PMU_STABLE_XPD_PLL_STATE    0x00000007U
+#define PMU_STABLE_XPD_PLL_STATE_M  (PMU_STABLE_XPD_PLL_STATE_V << PMU_STABLE_XPD_PLL_STATE_S)
+#define PMU_STABLE_XPD_PLL_STATE_V  0x00000007U
+#define PMU_STABLE_XPD_PLL_STATE_S  0
+/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define PMU_STABLE_XPD_XTAL_STATE    (BIT(3))
+#define PMU_STABLE_XPD_XTAL_STATE_M  (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S)
+#define PMU_STABLE_XPD_XTAL_STATE_V  0x00000001U
+#define PMU_STABLE_XPD_XTAL_STATE_S  3
+/** PMU_PMU_ANA_XPD_PLL_I2C_STATE : RO; bitpos: [6:4]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ANA_XPD_PLL_I2C_STATE    0x00000007U
+#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_M  (PMU_PMU_ANA_XPD_PLL_I2C_STATE_V << PMU_PMU_ANA_XPD_PLL_I2C_STATE_S)
+#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_V  0x00000007U
+#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_S  4
+/** PMU_PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_SYS_CLK_SLP_SEL_STATE    (BIT(10))
+#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_M  (PMU_PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_PMU_SYS_CLK_SLP_SEL_STATE_S)
+#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_V  0x00000001U
+#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_S  10
+/** PMU_PMU_SYS_CLK_SEL_STATE : RO; bitpos: [12:11]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_SYS_CLK_SEL_STATE    0x00000003U
+#define PMU_PMU_SYS_CLK_SEL_STATE_M  (PMU_PMU_SYS_CLK_SEL_STATE_V << PMU_PMU_SYS_CLK_SEL_STATE_S)
+#define PMU_PMU_SYS_CLK_SEL_STATE_V  0x00000003U
+#define PMU_PMU_SYS_CLK_SEL_STATE_S  11
+/** PMU_PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_SYS_CLK_NO_DIV_STATE    (BIT(13))
+#define PMU_PMU_SYS_CLK_NO_DIV_STATE_M  (PMU_PMU_SYS_CLK_NO_DIV_STATE_V << PMU_PMU_SYS_CLK_NO_DIV_STATE_S)
+#define PMU_PMU_SYS_CLK_NO_DIV_STATE_V  0x00000001U
+#define PMU_PMU_SYS_CLK_NO_DIV_STATE_S  13
+/** PMU_PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [14]; default: 1;
+ *  need_des
+ */
+#define PMU_PMU_ICG_SYS_CLK_EN_STATE    (BIT(14))
+#define PMU_PMU_ICG_SYS_CLK_EN_STATE_M  (PMU_PMU_ICG_SYS_CLK_EN_STATE_V << PMU_PMU_ICG_SYS_CLK_EN_STATE_S)
+#define PMU_PMU_ICG_SYS_CLK_EN_STATE_V  0x00000001U
+#define PMU_PMU_ICG_SYS_CLK_EN_STATE_S  14
+/** PMU_PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_MODEM_SWITCH_STATE    (BIT(15))
+#define PMU_PMU_ICG_MODEM_SWITCH_STATE_M  (PMU_PMU_ICG_MODEM_SWITCH_STATE_V << PMU_PMU_ICG_MODEM_SWITCH_STATE_S)
+#define PMU_PMU_ICG_MODEM_SWITCH_STATE_V  0x00000001U
+#define PMU_PMU_ICG_MODEM_SWITCH_STATE_S  15
+/** PMU_PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [17:16]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_MODEM_CODE_STATE    0x00000003U
+#define PMU_PMU_ICG_MODEM_CODE_STATE_M  (PMU_PMU_ICG_MODEM_CODE_STATE_V << PMU_PMU_ICG_MODEM_CODE_STATE_S)
+#define PMU_PMU_ICG_MODEM_CODE_STATE_V  0x00000003U
+#define PMU_PMU_ICG_MODEM_CODE_STATE_S  16
+/** PMU_PMU_ICG_SLP_SEL_STATE : RO; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_SLP_SEL_STATE    (BIT(18))
+#define PMU_PMU_ICG_SLP_SEL_STATE_M  (PMU_PMU_ICG_SLP_SEL_STATE_V << PMU_PMU_ICG_SLP_SEL_STATE_S)
+#define PMU_PMU_ICG_SLP_SEL_STATE_V  0x00000001U
+#define PMU_PMU_ICG_SLP_SEL_STATE_S  18
+/** PMU_PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_GLOBAL_XTAL_STATE    (BIT(19))
+#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_M  (PMU_PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_PMU_ICG_GLOBAL_XTAL_STATE_S)
+#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_V  0x00000001U
+#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_S  19
+/** PMU_PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [23:20]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_GLOBAL_PLL_STATE    0x0000000FU
+#define PMU_PMU_ICG_GLOBAL_PLL_STATE_M  (PMU_PMU_ICG_GLOBAL_PLL_STATE_V << PMU_PMU_ICG_GLOBAL_PLL_STATE_S)
+#define PMU_PMU_ICG_GLOBAL_PLL_STATE_V  0x0000000FU
+#define PMU_PMU_ICG_GLOBAL_PLL_STATE_S  20
+/** PMU_PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ANA_I2C_ISO_EN_STATE    (BIT(24))
+#define PMU_PMU_ANA_I2C_ISO_EN_STATE_M  (PMU_PMU_ANA_I2C_ISO_EN_STATE_V << PMU_PMU_ANA_I2C_ISO_EN_STATE_S)
+#define PMU_PMU_ANA_I2C_ISO_EN_STATE_V  0x00000001U
+#define PMU_PMU_ANA_I2C_ISO_EN_STATE_S  24
+/** PMU_PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ANA_I2C_RETENTION_STATE    (BIT(25))
+#define PMU_PMU_ANA_I2C_RETENTION_STATE_M  (PMU_PMU_ANA_I2C_RETENTION_STATE_V << PMU_PMU_ANA_I2C_RETENTION_STATE_S)
+#define PMU_PMU_ANA_I2C_RETENTION_STATE_V  0x00000001U
+#define PMU_PMU_ANA_I2C_RETENTION_STATE_S  25
+/** PMU_PMU_ANA_XPD_PLL_STATE : RO; bitpos: [30:27]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ANA_XPD_PLL_STATE    0x0000000FU
+#define PMU_PMU_ANA_XPD_PLL_STATE_M  (PMU_PMU_ANA_XPD_PLL_STATE_V << PMU_PMU_ANA_XPD_PLL_STATE_S)
+#define PMU_PMU_ANA_XPD_PLL_STATE_V  0x0000000FU
+#define PMU_PMU_ANA_XPD_PLL_STATE_S  27
+/** PMU_PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_PMU_ANA_XPD_XTAL_STATE    (BIT(31))
+#define PMU_PMU_ANA_XPD_XTAL_STATE_M  (PMU_PMU_ANA_XPD_XTAL_STATE_V << PMU_PMU_ANA_XPD_XTAL_STATE_S)
+#define PMU_PMU_ANA_XPD_XTAL_STATE_V  0x00000001U
+#define PMU_PMU_ANA_XPD_XTAL_STATE_S  31
+
+/** PMU_CLK_STATE1_REG register
+ *  need_des
+ */
+#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x1b0)
+/** PMU_PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_PMU_ICG_FUNC_EN_STATE    0xFFFFFFFFU
+#define PMU_PMU_ICG_FUNC_EN_STATE_M  (PMU_PMU_ICG_FUNC_EN_STATE_V << PMU_PMU_ICG_FUNC_EN_STATE_S)
+#define PMU_PMU_ICG_FUNC_EN_STATE_V  0xFFFFFFFFU
+#define PMU_PMU_ICG_FUNC_EN_STATE_S  0
+
+/** PMU_CLK_STATE2_REG register
+ *  need_des
+ */
+#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1b4)
+/** PMU_PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_PMU_ICG_APB_EN_STATE    0xFFFFFFFFU
+#define PMU_PMU_ICG_APB_EN_STATE_M  (PMU_PMU_ICG_APB_EN_STATE_V << PMU_PMU_ICG_APB_EN_STATE_S)
+#define PMU_PMU_ICG_APB_EN_STATE_V  0xFFFFFFFFU
+#define PMU_PMU_ICG_APB_EN_STATE_S  0
+
+/** PMU_EXT_LDO_P0_0P1A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P1A_REG (DR_REG_PMU_BASE + 0x1b8)
+/** PMU_0P1A_CNT_CLR_0 : WT; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_CNT_CLR_0    (BIT(6))
+#define PMU_0P1A_CNT_CLR_0_M  (PMU_0P1A_CNT_CLR_0_V << PMU_0P1A_CNT_CLR_0_S)
+#define PMU_0P1A_CNT_CLR_0_V  0x00000001U
+#define PMU_0P1A_CNT_CLR_0_S  6
+/** PMU_0P1A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_FORCE_TIEH_SEL_0    (BIT(7))
+#define PMU_0P1A_FORCE_TIEH_SEL_0_M  (PMU_0P1A_FORCE_TIEH_SEL_0_V << PMU_0P1A_FORCE_TIEH_SEL_0_S)
+#define PMU_0P1A_FORCE_TIEH_SEL_0_V  0x00000001U
+#define PMU_0P1A_FORCE_TIEH_SEL_0_S  7
+/** PMU_0P1A_XPD_0 : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define PMU_0P1A_XPD_0    (BIT(8))
+#define PMU_0P1A_XPD_0_M  (PMU_0P1A_XPD_0_V << PMU_0P1A_XPD_0_S)
+#define PMU_0P1A_XPD_0_V  0x00000001U
+#define PMU_0P1A_XPD_0_S  8
+/** PMU_0P1A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_SEL_0    0x00000007U
+#define PMU_0P1A_TIEH_SEL_0_M  (PMU_0P1A_TIEH_SEL_0_V << PMU_0P1A_TIEH_SEL_0_S)
+#define PMU_0P1A_TIEH_SEL_0_V  0x00000007U
+#define PMU_0P1A_TIEH_SEL_0_S  9
+/** PMU_0P1A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_POS_EN_0    (BIT(12))
+#define PMU_0P1A_TIEH_POS_EN_0_M  (PMU_0P1A_TIEH_POS_EN_0_V << PMU_0P1A_TIEH_POS_EN_0_S)
+#define PMU_0P1A_TIEH_POS_EN_0_V  0x00000001U
+#define PMU_0P1A_TIEH_POS_EN_0_S  12
+/** PMU_0P1A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_NEG_EN_0    (BIT(13))
+#define PMU_0P1A_TIEH_NEG_EN_0_M  (PMU_0P1A_TIEH_NEG_EN_0_V << PMU_0P1A_TIEH_NEG_EN_0_S)
+#define PMU_0P1A_TIEH_NEG_EN_0_V  0x00000001U
+#define PMU_0P1A_TIEH_NEG_EN_0_S  13
+/** PMU_0P1A_TIEH_0 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_0    (BIT(14))
+#define PMU_0P1A_TIEH_0_M  (PMU_0P1A_TIEH_0_V << PMU_0P1A_TIEH_0_S)
+#define PMU_0P1A_TIEH_0_V  0x00000001U
+#define PMU_0P1A_TIEH_0_S  14
+/** PMU_0P1A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P1A_TARGET1_0    0x000000FFU
+#define PMU_0P1A_TARGET1_0_M  (PMU_0P1A_TARGET1_0_V << PMU_0P1A_TARGET1_0_S)
+#define PMU_0P1A_TARGET1_0_V  0x000000FFU
+#define PMU_0P1A_TARGET1_0_S  15
+/** PMU_0P1A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P1A_TARGET0_0    0x000000FFU
+#define PMU_0P1A_TARGET0_0_M  (PMU_0P1A_TARGET0_0_V << PMU_0P1A_TARGET0_0_S)
+#define PMU_0P1A_TARGET0_0_V  0x000000FFU
+#define PMU_0P1A_TARGET0_0_S  23
+/** PMU_0P1A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0    (BIT(31))
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_M  (PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_S)
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_V  0x00000001U
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_S  31
+
+/** PMU_EXT_LDO_P0_0P1A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P1A_ANA_REG (DR_REG_PMU_BASE + 0x1bc)
+/** PMU_ANA_0P1A_MUL_0 : R/W; bitpos: [25:23]; default: 2;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_MUL_0    0x00000007U
+#define PMU_ANA_0P1A_MUL_0_M  (PMU_ANA_0P1A_MUL_0_V << PMU_ANA_0P1A_MUL_0_S)
+#define PMU_ANA_0P1A_MUL_0_V  0x00000007U
+#define PMU_ANA_0P1A_MUL_0_S  23
+/** PMU_ANA_0P1A_EN_VDET_0 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_EN_VDET_0    (BIT(26))
+#define PMU_ANA_0P1A_EN_VDET_0_M  (PMU_ANA_0P1A_EN_VDET_0_V << PMU_ANA_0P1A_EN_VDET_0_S)
+#define PMU_ANA_0P1A_EN_VDET_0_V  0x00000001U
+#define PMU_ANA_0P1A_EN_VDET_0_S  26
+/** PMU_ANA_0P1A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_EN_CUR_LIM_0    (BIT(27))
+#define PMU_ANA_0P1A_EN_CUR_LIM_0_M  (PMU_ANA_0P1A_EN_CUR_LIM_0_V << PMU_ANA_0P1A_EN_CUR_LIM_0_S)
+#define PMU_ANA_0P1A_EN_CUR_LIM_0_V  0x00000001U
+#define PMU_ANA_0P1A_EN_CUR_LIM_0_S  27
+/** PMU_ANA_0P1A_DREF_0 : R/W; bitpos: [31:28]; default: 11;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_DREF_0    0x0000000FU
+#define PMU_ANA_0P1A_DREF_0_M  (PMU_ANA_0P1A_DREF_0_V << PMU_ANA_0P1A_DREF_0_S)
+#define PMU_ANA_0P1A_DREF_0_V  0x0000000FU
+#define PMU_ANA_0P1A_DREF_0_S  28
+
+/** PMU_EXT_LDO_P0_0P2A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P2A_REG (DR_REG_PMU_BASE + 0x1c0)
+/** PMU_0P2A_CNT_CLR_0 : WT; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_CNT_CLR_0    (BIT(6))
+#define PMU_0P2A_CNT_CLR_0_M  (PMU_0P2A_CNT_CLR_0_V << PMU_0P2A_CNT_CLR_0_S)
+#define PMU_0P2A_CNT_CLR_0_V  0x00000001U
+#define PMU_0P2A_CNT_CLR_0_S  6
+/** PMU_0P2A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_FORCE_TIEH_SEL_0    (BIT(7))
+#define PMU_0P2A_FORCE_TIEH_SEL_0_M  (PMU_0P2A_FORCE_TIEH_SEL_0_V << PMU_0P2A_FORCE_TIEH_SEL_0_S)
+#define PMU_0P2A_FORCE_TIEH_SEL_0_V  0x00000001U
+#define PMU_0P2A_FORCE_TIEH_SEL_0_S  7
+/** PMU_0P2A_XPD_0 : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_XPD_0    (BIT(8))
+#define PMU_0P2A_XPD_0_M  (PMU_0P2A_XPD_0_V << PMU_0P2A_XPD_0_S)
+#define PMU_0P2A_XPD_0_V  0x00000001U
+#define PMU_0P2A_XPD_0_S  8
+/** PMU_0P2A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_SEL_0    0x00000007U
+#define PMU_0P2A_TIEH_SEL_0_M  (PMU_0P2A_TIEH_SEL_0_V << PMU_0P2A_TIEH_SEL_0_S)
+#define PMU_0P2A_TIEH_SEL_0_V  0x00000007U
+#define PMU_0P2A_TIEH_SEL_0_S  9
+/** PMU_0P2A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_POS_EN_0    (BIT(12))
+#define PMU_0P2A_TIEH_POS_EN_0_M  (PMU_0P2A_TIEH_POS_EN_0_V << PMU_0P2A_TIEH_POS_EN_0_S)
+#define PMU_0P2A_TIEH_POS_EN_0_V  0x00000001U
+#define PMU_0P2A_TIEH_POS_EN_0_S  12
+/** PMU_0P2A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_NEG_EN_0    (BIT(13))
+#define PMU_0P2A_TIEH_NEG_EN_0_M  (PMU_0P2A_TIEH_NEG_EN_0_V << PMU_0P2A_TIEH_NEG_EN_0_S)
+#define PMU_0P2A_TIEH_NEG_EN_0_V  0x00000001U
+#define PMU_0P2A_TIEH_NEG_EN_0_S  13
+/** PMU_0P2A_TIEH_0 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_0    (BIT(14))
+#define PMU_0P2A_TIEH_0_M  (PMU_0P2A_TIEH_0_V << PMU_0P2A_TIEH_0_S)
+#define PMU_0P2A_TIEH_0_V  0x00000001U
+#define PMU_0P2A_TIEH_0_S  14
+/** PMU_0P2A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P2A_TARGET1_0    0x000000FFU
+#define PMU_0P2A_TARGET1_0_M  (PMU_0P2A_TARGET1_0_V << PMU_0P2A_TARGET1_0_S)
+#define PMU_0P2A_TARGET1_0_V  0x000000FFU
+#define PMU_0P2A_TARGET1_0_S  15
+/** PMU_0P2A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P2A_TARGET0_0    0x000000FFU
+#define PMU_0P2A_TARGET0_0_M  (PMU_0P2A_TARGET0_0_V << PMU_0P2A_TARGET0_0_S)
+#define PMU_0P2A_TARGET0_0_V  0x000000FFU
+#define PMU_0P2A_TARGET0_0_S  23
+/** PMU_0P2A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0    (BIT(31))
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_M  (PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_S)
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_V  0x00000001U
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_S  31
+
+/** PMU_EXT_LDO_P0_0P2A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P2A_ANA_REG (DR_REG_PMU_BASE + 0x1c4)
+/** PMU_ANA_0P2A_MUL_0 : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_MUL_0    0x00000007U
+#define PMU_ANA_0P2A_MUL_0_M  (PMU_ANA_0P2A_MUL_0_V << PMU_ANA_0P2A_MUL_0_S)
+#define PMU_ANA_0P2A_MUL_0_V  0x00000007U
+#define PMU_ANA_0P2A_MUL_0_S  23
+/** PMU_ANA_0P2A_EN_VDET_0 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_EN_VDET_0    (BIT(26))
+#define PMU_ANA_0P2A_EN_VDET_0_M  (PMU_ANA_0P2A_EN_VDET_0_V << PMU_ANA_0P2A_EN_VDET_0_S)
+#define PMU_ANA_0P2A_EN_VDET_0_V  0x00000001U
+#define PMU_ANA_0P2A_EN_VDET_0_S  26
+/** PMU_ANA_0P2A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_EN_CUR_LIM_0    (BIT(27))
+#define PMU_ANA_0P2A_EN_CUR_LIM_0_M  (PMU_ANA_0P2A_EN_CUR_LIM_0_V << PMU_ANA_0P2A_EN_CUR_LIM_0_S)
+#define PMU_ANA_0P2A_EN_CUR_LIM_0_V  0x00000001U
+#define PMU_ANA_0P2A_EN_CUR_LIM_0_S  27
+/** PMU_ANA_0P2A_DREF_0 : R/W; bitpos: [31:28]; default: 10;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_DREF_0    0x0000000FU
+#define PMU_ANA_0P2A_DREF_0_M  (PMU_ANA_0P2A_DREF_0_V << PMU_ANA_0P2A_DREF_0_S)
+#define PMU_ANA_0P2A_DREF_0_V  0x0000000FU
+#define PMU_ANA_0P2A_DREF_0_S  28
+
+/** PMU_EXT_LDO_P0_0P3A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P3A_REG (DR_REG_PMU_BASE + 0x1c8)
+/** PMU_0P3A_CNT_CLR_0 : WT; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_CNT_CLR_0    (BIT(6))
+#define PMU_0P3A_CNT_CLR_0_M  (PMU_0P3A_CNT_CLR_0_V << PMU_0P3A_CNT_CLR_0_S)
+#define PMU_0P3A_CNT_CLR_0_V  0x00000001U
+#define PMU_0P3A_CNT_CLR_0_S  6
+/** PMU_0P3A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_FORCE_TIEH_SEL_0    (BIT(7))
+#define PMU_0P3A_FORCE_TIEH_SEL_0_M  (PMU_0P3A_FORCE_TIEH_SEL_0_V << PMU_0P3A_FORCE_TIEH_SEL_0_S)
+#define PMU_0P3A_FORCE_TIEH_SEL_0_V  0x00000001U
+#define PMU_0P3A_FORCE_TIEH_SEL_0_S  7
+/** PMU_0P3A_XPD_0 : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_XPD_0    (BIT(8))
+#define PMU_0P3A_XPD_0_M  (PMU_0P3A_XPD_0_V << PMU_0P3A_XPD_0_S)
+#define PMU_0P3A_XPD_0_V  0x00000001U
+#define PMU_0P3A_XPD_0_S  8
+/** PMU_0P3A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_SEL_0    0x00000007U
+#define PMU_0P3A_TIEH_SEL_0_M  (PMU_0P3A_TIEH_SEL_0_V << PMU_0P3A_TIEH_SEL_0_S)
+#define PMU_0P3A_TIEH_SEL_0_V  0x00000007U
+#define PMU_0P3A_TIEH_SEL_0_S  9
+/** PMU_0P3A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_POS_EN_0    (BIT(12))
+#define PMU_0P3A_TIEH_POS_EN_0_M  (PMU_0P3A_TIEH_POS_EN_0_V << PMU_0P3A_TIEH_POS_EN_0_S)
+#define PMU_0P3A_TIEH_POS_EN_0_V  0x00000001U
+#define PMU_0P3A_TIEH_POS_EN_0_S  12
+/** PMU_0P3A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_NEG_EN_0    (BIT(13))
+#define PMU_0P3A_TIEH_NEG_EN_0_M  (PMU_0P3A_TIEH_NEG_EN_0_V << PMU_0P3A_TIEH_NEG_EN_0_S)
+#define PMU_0P3A_TIEH_NEG_EN_0_V  0x00000001U
+#define PMU_0P3A_TIEH_NEG_EN_0_S  13
+/** PMU_0P3A_TIEH_0 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_0    (BIT(14))
+#define PMU_0P3A_TIEH_0_M  (PMU_0P3A_TIEH_0_V << PMU_0P3A_TIEH_0_S)
+#define PMU_0P3A_TIEH_0_V  0x00000001U
+#define PMU_0P3A_TIEH_0_S  14
+/** PMU_0P3A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P3A_TARGET1_0    0x000000FFU
+#define PMU_0P3A_TARGET1_0_M  (PMU_0P3A_TARGET1_0_V << PMU_0P3A_TARGET1_0_S)
+#define PMU_0P3A_TARGET1_0_V  0x000000FFU
+#define PMU_0P3A_TARGET1_0_S  15
+/** PMU_0P3A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P3A_TARGET0_0    0x000000FFU
+#define PMU_0P3A_TARGET0_0_M  (PMU_0P3A_TARGET0_0_V << PMU_0P3A_TARGET0_0_S)
+#define PMU_0P3A_TARGET0_0_V  0x000000FFU
+#define PMU_0P3A_TARGET0_0_S  23
+/** PMU_0P3A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0    (BIT(31))
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_M  (PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_S)
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_V  0x00000001U
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_S  31
+
+/** PMU_EXT_LDO_P0_0P3A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P3A_ANA_REG (DR_REG_PMU_BASE + 0x1cc)
+/** PMU_ANA_0P3A_MUL_0 : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_MUL_0    0x00000007U
+#define PMU_ANA_0P3A_MUL_0_M  (PMU_ANA_0P3A_MUL_0_V << PMU_ANA_0P3A_MUL_0_S)
+#define PMU_ANA_0P3A_MUL_0_V  0x00000007U
+#define PMU_ANA_0P3A_MUL_0_S  23
+/** PMU_ANA_0P3A_EN_VDET_0 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_EN_VDET_0    (BIT(26))
+#define PMU_ANA_0P3A_EN_VDET_0_M  (PMU_ANA_0P3A_EN_VDET_0_V << PMU_ANA_0P3A_EN_VDET_0_S)
+#define PMU_ANA_0P3A_EN_VDET_0_V  0x00000001U
+#define PMU_ANA_0P3A_EN_VDET_0_S  26
+/** PMU_ANA_0P3A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_EN_CUR_LIM_0    (BIT(27))
+#define PMU_ANA_0P3A_EN_CUR_LIM_0_M  (PMU_ANA_0P3A_EN_CUR_LIM_0_V << PMU_ANA_0P3A_EN_CUR_LIM_0_S)
+#define PMU_ANA_0P3A_EN_CUR_LIM_0_V  0x00000001U
+#define PMU_ANA_0P3A_EN_CUR_LIM_0_S  27
+/** PMU_ANA_0P3A_DREF_0 : R/W; bitpos: [31:28]; default: 10;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_DREF_0    0x0000000FU
+#define PMU_ANA_0P3A_DREF_0_M  (PMU_ANA_0P3A_DREF_0_V << PMU_ANA_0P3A_DREF_0_S)
+#define PMU_ANA_0P3A_DREF_0_V  0x0000000FU
+#define PMU_ANA_0P3A_DREF_0_S  28
+
+/** PMU_EXT_LDO_P1_0P1A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P1A_REG (DR_REG_PMU_BASE + 0x1d0)
+/** PMU_0P1A_CNT_CLR_1 : WT; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_CNT_CLR_1    (BIT(6))
+#define PMU_0P1A_CNT_CLR_1_M  (PMU_0P1A_CNT_CLR_1_V << PMU_0P1A_CNT_CLR_1_S)
+#define PMU_0P1A_CNT_CLR_1_V  0x00000001U
+#define PMU_0P1A_CNT_CLR_1_S  6
+/** PMU_0P1A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_FORCE_TIEH_SEL_1    (BIT(7))
+#define PMU_0P1A_FORCE_TIEH_SEL_1_M  (PMU_0P1A_FORCE_TIEH_SEL_1_V << PMU_0P1A_FORCE_TIEH_SEL_1_S)
+#define PMU_0P1A_FORCE_TIEH_SEL_1_V  0x00000001U
+#define PMU_0P1A_FORCE_TIEH_SEL_1_S  7
+/** PMU_0P1A_XPD_1 : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_XPD_1    (BIT(8))
+#define PMU_0P1A_XPD_1_M  (PMU_0P1A_XPD_1_V << PMU_0P1A_XPD_1_S)
+#define PMU_0P1A_XPD_1_V  0x00000001U
+#define PMU_0P1A_XPD_1_S  8
+/** PMU_0P1A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_SEL_1    0x00000007U
+#define PMU_0P1A_TIEH_SEL_1_M  (PMU_0P1A_TIEH_SEL_1_V << PMU_0P1A_TIEH_SEL_1_S)
+#define PMU_0P1A_TIEH_SEL_1_V  0x00000007U
+#define PMU_0P1A_TIEH_SEL_1_S  9
+/** PMU_0P1A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_POS_EN_1    (BIT(12))
+#define PMU_0P1A_TIEH_POS_EN_1_M  (PMU_0P1A_TIEH_POS_EN_1_V << PMU_0P1A_TIEH_POS_EN_1_S)
+#define PMU_0P1A_TIEH_POS_EN_1_V  0x00000001U
+#define PMU_0P1A_TIEH_POS_EN_1_S  12
+/** PMU_0P1A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_NEG_EN_1    (BIT(13))
+#define PMU_0P1A_TIEH_NEG_EN_1_M  (PMU_0P1A_TIEH_NEG_EN_1_V << PMU_0P1A_TIEH_NEG_EN_1_S)
+#define PMU_0P1A_TIEH_NEG_EN_1_V  0x00000001U
+#define PMU_0P1A_TIEH_NEG_EN_1_S  13
+/** PMU_0P1A_TIEH_1 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_1    (BIT(14))
+#define PMU_0P1A_TIEH_1_M  (PMU_0P1A_TIEH_1_V << PMU_0P1A_TIEH_1_S)
+#define PMU_0P1A_TIEH_1_V  0x00000001U
+#define PMU_0P1A_TIEH_1_S  14
+/** PMU_0P1A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P1A_TARGET1_1    0x000000FFU
+#define PMU_0P1A_TARGET1_1_M  (PMU_0P1A_TARGET1_1_V << PMU_0P1A_TARGET1_1_S)
+#define PMU_0P1A_TARGET1_1_V  0x000000FFU
+#define PMU_0P1A_TARGET1_1_S  15
+/** PMU_0P1A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P1A_TARGET0_1    0x000000FFU
+#define PMU_0P1A_TARGET0_1_M  (PMU_0P1A_TARGET0_1_V << PMU_0P1A_TARGET0_1_S)
+#define PMU_0P1A_TARGET0_1_V  0x000000FFU
+#define PMU_0P1A_TARGET0_1_S  23
+/** PMU_0P1A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1    (BIT(31))
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_M  (PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_S)
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_V  0x00000001U
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_S  31
+
+/** PMU_EXT_LDO_P1_0P1A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P1A_ANA_REG (DR_REG_PMU_BASE + 0x1d4)
+/** PMU_ANA_0P1A_MUL_1 : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_MUL_1    0x00000007U
+#define PMU_ANA_0P1A_MUL_1_M  (PMU_ANA_0P1A_MUL_1_V << PMU_ANA_0P1A_MUL_1_S)
+#define PMU_ANA_0P1A_MUL_1_V  0x00000007U
+#define PMU_ANA_0P1A_MUL_1_S  23
+/** PMU_ANA_0P1A_EN_VDET_1 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_EN_VDET_1    (BIT(26))
+#define PMU_ANA_0P1A_EN_VDET_1_M  (PMU_ANA_0P1A_EN_VDET_1_V << PMU_ANA_0P1A_EN_VDET_1_S)
+#define PMU_ANA_0P1A_EN_VDET_1_V  0x00000001U
+#define PMU_ANA_0P1A_EN_VDET_1_S  26
+/** PMU_ANA_0P1A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_EN_CUR_LIM_1    (BIT(27))
+#define PMU_ANA_0P1A_EN_CUR_LIM_1_M  (PMU_ANA_0P1A_EN_CUR_LIM_1_V << PMU_ANA_0P1A_EN_CUR_LIM_1_S)
+#define PMU_ANA_0P1A_EN_CUR_LIM_1_V  0x00000001U
+#define PMU_ANA_0P1A_EN_CUR_LIM_1_S  27
+/** PMU_ANA_0P1A_DREF_1 : R/W; bitpos: [31:28]; default: 10;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_DREF_1    0x0000000FU
+#define PMU_ANA_0P1A_DREF_1_M  (PMU_ANA_0P1A_DREF_1_V << PMU_ANA_0P1A_DREF_1_S)
+#define PMU_ANA_0P1A_DREF_1_V  0x0000000FU
+#define PMU_ANA_0P1A_DREF_1_S  28
+
+/** PMU_EXT_LDO_P1_0P2A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P2A_REG (DR_REG_PMU_BASE + 0x1d8)
+/** PMU_0P2A_CNT_CLR_1 : WT; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_CNT_CLR_1    (BIT(6))
+#define PMU_0P2A_CNT_CLR_1_M  (PMU_0P2A_CNT_CLR_1_V << PMU_0P2A_CNT_CLR_1_S)
+#define PMU_0P2A_CNT_CLR_1_V  0x00000001U
+#define PMU_0P2A_CNT_CLR_1_S  6
+/** PMU_0P2A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_FORCE_TIEH_SEL_1    (BIT(7))
+#define PMU_0P2A_FORCE_TIEH_SEL_1_M  (PMU_0P2A_FORCE_TIEH_SEL_1_V << PMU_0P2A_FORCE_TIEH_SEL_1_S)
+#define PMU_0P2A_FORCE_TIEH_SEL_1_V  0x00000001U
+#define PMU_0P2A_FORCE_TIEH_SEL_1_S  7
+/** PMU_0P2A_XPD_1 : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_XPD_1    (BIT(8))
+#define PMU_0P2A_XPD_1_M  (PMU_0P2A_XPD_1_V << PMU_0P2A_XPD_1_S)
+#define PMU_0P2A_XPD_1_V  0x00000001U
+#define PMU_0P2A_XPD_1_S  8
+/** PMU_0P2A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_SEL_1    0x00000007U
+#define PMU_0P2A_TIEH_SEL_1_M  (PMU_0P2A_TIEH_SEL_1_V << PMU_0P2A_TIEH_SEL_1_S)
+#define PMU_0P2A_TIEH_SEL_1_V  0x00000007U
+#define PMU_0P2A_TIEH_SEL_1_S  9
+/** PMU_0P2A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_POS_EN_1    (BIT(12))
+#define PMU_0P2A_TIEH_POS_EN_1_M  (PMU_0P2A_TIEH_POS_EN_1_V << PMU_0P2A_TIEH_POS_EN_1_S)
+#define PMU_0P2A_TIEH_POS_EN_1_V  0x00000001U
+#define PMU_0P2A_TIEH_POS_EN_1_S  12
+/** PMU_0P2A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_NEG_EN_1    (BIT(13))
+#define PMU_0P2A_TIEH_NEG_EN_1_M  (PMU_0P2A_TIEH_NEG_EN_1_V << PMU_0P2A_TIEH_NEG_EN_1_S)
+#define PMU_0P2A_TIEH_NEG_EN_1_V  0x00000001U
+#define PMU_0P2A_TIEH_NEG_EN_1_S  13
+/** PMU_0P2A_TIEH_1 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_1    (BIT(14))
+#define PMU_0P2A_TIEH_1_M  (PMU_0P2A_TIEH_1_V << PMU_0P2A_TIEH_1_S)
+#define PMU_0P2A_TIEH_1_V  0x00000001U
+#define PMU_0P2A_TIEH_1_S  14
+/** PMU_0P2A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P2A_TARGET1_1    0x000000FFU
+#define PMU_0P2A_TARGET1_1_M  (PMU_0P2A_TARGET1_1_V << PMU_0P2A_TARGET1_1_S)
+#define PMU_0P2A_TARGET1_1_V  0x000000FFU
+#define PMU_0P2A_TARGET1_1_S  15
+/** PMU_0P2A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P2A_TARGET0_1    0x000000FFU
+#define PMU_0P2A_TARGET0_1_M  (PMU_0P2A_TARGET0_1_V << PMU_0P2A_TARGET0_1_S)
+#define PMU_0P2A_TARGET0_1_V  0x000000FFU
+#define PMU_0P2A_TARGET0_1_S  23
+/** PMU_0P2A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1    (BIT(31))
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_M  (PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_S)
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_V  0x00000001U
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_S  31
+
+/** PMU_EXT_LDO_P1_0P2A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P2A_ANA_REG (DR_REG_PMU_BASE + 0x1dc)
+/** PMU_ANA_0P2A_MUL_1 : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_MUL_1    0x00000007U
+#define PMU_ANA_0P2A_MUL_1_M  (PMU_ANA_0P2A_MUL_1_V << PMU_ANA_0P2A_MUL_1_S)
+#define PMU_ANA_0P2A_MUL_1_V  0x00000007U
+#define PMU_ANA_0P2A_MUL_1_S  23
+/** PMU_ANA_0P2A_EN_VDET_1 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_EN_VDET_1    (BIT(26))
+#define PMU_ANA_0P2A_EN_VDET_1_M  (PMU_ANA_0P2A_EN_VDET_1_V << PMU_ANA_0P2A_EN_VDET_1_S)
+#define PMU_ANA_0P2A_EN_VDET_1_V  0x00000001U
+#define PMU_ANA_0P2A_EN_VDET_1_S  26
+/** PMU_ANA_0P2A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_EN_CUR_LIM_1    (BIT(27))
+#define PMU_ANA_0P2A_EN_CUR_LIM_1_M  (PMU_ANA_0P2A_EN_CUR_LIM_1_V << PMU_ANA_0P2A_EN_CUR_LIM_1_S)
+#define PMU_ANA_0P2A_EN_CUR_LIM_1_V  0x00000001U
+#define PMU_ANA_0P2A_EN_CUR_LIM_1_S  27
+/** PMU_ANA_0P2A_DREF_1 : R/W; bitpos: [31:28]; default: 10;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_DREF_1    0x0000000FU
+#define PMU_ANA_0P2A_DREF_1_M  (PMU_ANA_0P2A_DREF_1_V << PMU_ANA_0P2A_DREF_1_S)
+#define PMU_ANA_0P2A_DREF_1_V  0x0000000FU
+#define PMU_ANA_0P2A_DREF_1_S  28
+
+/** PMU_EXT_LDO_P1_0P3A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P3A_REG (DR_REG_PMU_BASE + 0x1e0)
+/** PMU_0P3A_CNT_CLR_1 : WT; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_CNT_CLR_1    (BIT(6))
+#define PMU_0P3A_CNT_CLR_1_M  (PMU_0P3A_CNT_CLR_1_V << PMU_0P3A_CNT_CLR_1_S)
+#define PMU_0P3A_CNT_CLR_1_V  0x00000001U
+#define PMU_0P3A_CNT_CLR_1_S  6
+/** PMU_0P3A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_FORCE_TIEH_SEL_1    (BIT(7))
+#define PMU_0P3A_FORCE_TIEH_SEL_1_M  (PMU_0P3A_FORCE_TIEH_SEL_1_V << PMU_0P3A_FORCE_TIEH_SEL_1_S)
+#define PMU_0P3A_FORCE_TIEH_SEL_1_V  0x00000001U
+#define PMU_0P3A_FORCE_TIEH_SEL_1_S  7
+/** PMU_0P3A_XPD_1 : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_XPD_1    (BIT(8))
+#define PMU_0P3A_XPD_1_M  (PMU_0P3A_XPD_1_V << PMU_0P3A_XPD_1_S)
+#define PMU_0P3A_XPD_1_V  0x00000001U
+#define PMU_0P3A_XPD_1_S  8
+/** PMU_0P3A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_SEL_1    0x00000007U
+#define PMU_0P3A_TIEH_SEL_1_M  (PMU_0P3A_TIEH_SEL_1_V << PMU_0P3A_TIEH_SEL_1_S)
+#define PMU_0P3A_TIEH_SEL_1_V  0x00000007U
+#define PMU_0P3A_TIEH_SEL_1_S  9
+/** PMU_0P3A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_POS_EN_1    (BIT(12))
+#define PMU_0P3A_TIEH_POS_EN_1_M  (PMU_0P3A_TIEH_POS_EN_1_V << PMU_0P3A_TIEH_POS_EN_1_S)
+#define PMU_0P3A_TIEH_POS_EN_1_V  0x00000001U
+#define PMU_0P3A_TIEH_POS_EN_1_S  12
+/** PMU_0P3A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_NEG_EN_1    (BIT(13))
+#define PMU_0P3A_TIEH_NEG_EN_1_M  (PMU_0P3A_TIEH_NEG_EN_1_V << PMU_0P3A_TIEH_NEG_EN_1_S)
+#define PMU_0P3A_TIEH_NEG_EN_1_V  0x00000001U
+#define PMU_0P3A_TIEH_NEG_EN_1_S  13
+/** PMU_0P3A_TIEH_1 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_1    (BIT(14))
+#define PMU_0P3A_TIEH_1_M  (PMU_0P3A_TIEH_1_V << PMU_0P3A_TIEH_1_S)
+#define PMU_0P3A_TIEH_1_V  0x00000001U
+#define PMU_0P3A_TIEH_1_S  14
+/** PMU_0P3A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P3A_TARGET1_1    0x000000FFU
+#define PMU_0P3A_TARGET1_1_M  (PMU_0P3A_TARGET1_1_V << PMU_0P3A_TARGET1_1_S)
+#define PMU_0P3A_TARGET1_1_V  0x000000FFU
+#define PMU_0P3A_TARGET1_1_S  15
+/** PMU_0P3A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P3A_TARGET0_1    0x000000FFU
+#define PMU_0P3A_TARGET0_1_M  (PMU_0P3A_TARGET0_1_V << PMU_0P3A_TARGET0_1_S)
+#define PMU_0P3A_TARGET0_1_V  0x000000FFU
+#define PMU_0P3A_TARGET0_1_S  23
+/** PMU_0P3A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1    (BIT(31))
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_M  (PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_S)
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_V  0x00000001U
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_S  31
+
+/** PMU_EXT_LDO_P1_0P3A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P3A_ANA_REG (DR_REG_PMU_BASE + 0x1e4)
+/** PMU_ANA_0P3A_MUL_1 : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_MUL_1    0x00000007U
+#define PMU_ANA_0P3A_MUL_1_M  (PMU_ANA_0P3A_MUL_1_V << PMU_ANA_0P3A_MUL_1_S)
+#define PMU_ANA_0P3A_MUL_1_V  0x00000007U
+#define PMU_ANA_0P3A_MUL_1_S  23
+/** PMU_ANA_0P3A_EN_VDET_1 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_EN_VDET_1    (BIT(26))
+#define PMU_ANA_0P3A_EN_VDET_1_M  (PMU_ANA_0P3A_EN_VDET_1_V << PMU_ANA_0P3A_EN_VDET_1_S)
+#define PMU_ANA_0P3A_EN_VDET_1_V  0x00000001U
+#define PMU_ANA_0P3A_EN_VDET_1_S  26
+/** PMU_ANA_0P3A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_EN_CUR_LIM_1    (BIT(27))
+#define PMU_ANA_0P3A_EN_CUR_LIM_1_M  (PMU_ANA_0P3A_EN_CUR_LIM_1_V << PMU_ANA_0P3A_EN_CUR_LIM_1_S)
+#define PMU_ANA_0P3A_EN_CUR_LIM_1_V  0x00000001U
+#define PMU_ANA_0P3A_EN_CUR_LIM_1_S  27
+/** PMU_ANA_0P3A_DREF_1 : R/W; bitpos: [31:28]; default: 10;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_DREF_1    0x0000000FU
+#define PMU_ANA_0P3A_DREF_1_M  (PMU_ANA_0P3A_DREF_1_V << PMU_ANA_0P3A_DREF_1_S)
+#define PMU_ANA_0P3A_DREF_1_V  0x0000000FU
+#define PMU_ANA_0P3A_DREF_1_S  28
+
+/** PMU_EXT_WAKEUP_LV_REG register
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_LV_REG (DR_REG_PMU_BASE + 0x1e8)
+/** PMU_EXT_WAKEUP_LV : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_LV    0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_LV_M  (PMU_EXT_WAKEUP_LV_V << PMU_EXT_WAKEUP_LV_S)
+#define PMU_EXT_WAKEUP_LV_V  0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_LV_S  0
+
+/** PMU_EXT_WAKEUP_SEL_REG register
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_SEL_REG (DR_REG_PMU_BASE + 0x1ec)
+/** PMU_EXT_WAKEUP_SEL : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_SEL    0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_SEL_M  (PMU_EXT_WAKEUP_SEL_V << PMU_EXT_WAKEUP_SEL_S)
+#define PMU_EXT_WAKEUP_SEL_V  0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_SEL_S  0
+
+/** PMU_EXT_WAKEUP_ST_REG register
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_ST_REG (DR_REG_PMU_BASE + 0x1f0)
+/** PMU_EXT_WAKEUP_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_STATUS    0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_STATUS_M  (PMU_EXT_WAKEUP_STATUS_V << PMU_EXT_WAKEUP_STATUS_S)
+#define PMU_EXT_WAKEUP_STATUS_V  0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_STATUS_S  0
+
+/** PMU_EXT_WAKEUP_CNTL_REG register
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_CNTL_REG (DR_REG_PMU_BASE + 0x1f4)
+/** PMU_EXT_WAKEUP_STATUS_CLR : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_STATUS_CLR    (BIT(30))
+#define PMU_EXT_WAKEUP_STATUS_CLR_M  (PMU_EXT_WAKEUP_STATUS_CLR_V << PMU_EXT_WAKEUP_STATUS_CLR_S)
+#define PMU_EXT_WAKEUP_STATUS_CLR_V  0x00000001U
+#define PMU_EXT_WAKEUP_STATUS_CLR_S  30
+/** PMU_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_FILTER    (BIT(31))
+#define PMU_EXT_WAKEUP_FILTER_M  (PMU_EXT_WAKEUP_FILTER_V << PMU_EXT_WAKEUP_FILTER_S)
+#define PMU_EXT_WAKEUP_FILTER_V  0x00000001U
+#define PMU_EXT_WAKEUP_FILTER_S  31
+
+/** PMU_SDIO_WAKEUP_CNTL_REG register
+ *  need_des
+ */
+#define PMU_SDIO_WAKEUP_CNTL_REG (DR_REG_PMU_BASE + 0x1f8)
+/** PMU_SDIO_ACT_DNUM : R/W; bitpos: [9:0]; default: 1023;
+ *  need_des
+ */
+#define PMU_SDIO_ACT_DNUM    0x000003FFU
+#define PMU_SDIO_ACT_DNUM_M  (PMU_SDIO_ACT_DNUM_V << PMU_SDIO_ACT_DNUM_S)
+#define PMU_SDIO_ACT_DNUM_V  0x000003FFU
+#define PMU_SDIO_ACT_DNUM_S  0
+
+/** PMU_XTAL_SLP_REG register
+ *  need_des
+ */
+#define PMU_XTAL_SLP_REG (DR_REG_PMU_BASE + 0x1fc)
+/** PMU_XTAL_SLP_CNT_TARGET : R/W; bitpos: [31:16]; default: 15;
+ *  need_des
+ */
+#define PMU_XTAL_SLP_CNT_TARGET    0x0000FFFFU
+#define PMU_XTAL_SLP_CNT_TARGET_M  (PMU_XTAL_SLP_CNT_TARGET_V << PMU_XTAL_SLP_CNT_TARGET_S)
+#define PMU_XTAL_SLP_CNT_TARGET_V  0x0000FFFFU
+#define PMU_XTAL_SLP_CNT_TARGET_S  16
+
+/** PMU_CPU_SW_STALL_REG register
+ *  need_des
+ */
+#define PMU_CPU_SW_STALL_REG (DR_REG_PMU_BASE + 0x200)
+/** PMU_HPCORE1_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define PMU_HPCORE1_SW_STALL_CODE    0x000000FFU
+#define PMU_HPCORE1_SW_STALL_CODE_M  (PMU_HPCORE1_SW_STALL_CODE_V << PMU_HPCORE1_SW_STALL_CODE_S)
+#define PMU_HPCORE1_SW_STALL_CODE_V  0x000000FFU
+#define PMU_HPCORE1_SW_STALL_CODE_S  16
+/** PMU_HPCORE0_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0;
+ *  need_des
+ */
+#define PMU_HPCORE0_SW_STALL_CODE    0x000000FFU
+#define PMU_HPCORE0_SW_STALL_CODE_M  (PMU_HPCORE0_SW_STALL_CODE_V << PMU_HPCORE0_SW_STALL_CODE_S)
+#define PMU_HPCORE0_SW_STALL_CODE_V  0x000000FFU
+#define PMU_HPCORE0_SW_STALL_CODE_S  24
+
+/** PMU_DCM_CTRL_REG register
+ *  need_des
+ */
+#define PMU_DCM_CTRL_REG (DR_REG_PMU_BASE + 0x204)
+/** PMU_DCDC_ON_REQ : WT; bitpos: [0]; default: 0;
+ *  SW trigger dcdc on
+ */
+#define PMU_DCDC_ON_REQ    (BIT(0))
+#define PMU_DCDC_ON_REQ_M  (PMU_DCDC_ON_REQ_V << PMU_DCDC_ON_REQ_S)
+#define PMU_DCDC_ON_REQ_V  0x00000001U
+#define PMU_DCDC_ON_REQ_S  0
+/** PMU_DCDC_OFF_REQ : WT; bitpos: [1]; default: 0;
+ *  SW trigger dcdc off
+ */
+#define PMU_DCDC_OFF_REQ    (BIT(1))
+#define PMU_DCDC_OFF_REQ_M  (PMU_DCDC_OFF_REQ_V << PMU_DCDC_OFF_REQ_S)
+#define PMU_DCDC_OFF_REQ_V  0x00000001U
+#define PMU_DCDC_OFF_REQ_S  1
+/** PMU_DCDC_LIGHTSLP_REQ : WT; bitpos: [2]; default: 0;
+ *  SW trigger dcdc enter lightsleep
+ */
+#define PMU_DCDC_LIGHTSLP_REQ    (BIT(2))
+#define PMU_DCDC_LIGHTSLP_REQ_M  (PMU_DCDC_LIGHTSLP_REQ_V << PMU_DCDC_LIGHTSLP_REQ_S)
+#define PMU_DCDC_LIGHTSLP_REQ_V  0x00000001U
+#define PMU_DCDC_LIGHTSLP_REQ_S  2
+/** PMU_DCDC_DEEPSLP_REQ : WT; bitpos: [3]; default: 0;
+ *  SW trigger dcdc enter deepsleep
+ */
+#define PMU_DCDC_DEEPSLP_REQ    (BIT(3))
+#define PMU_DCDC_DEEPSLP_REQ_M  (PMU_DCDC_DEEPSLP_REQ_V << PMU_DCDC_DEEPSLP_REQ_S)
+#define PMU_DCDC_DEEPSLP_REQ_V  0x00000001U
+#define PMU_DCDC_DEEPSLP_REQ_S  3
+/** PMU_DCDC_DONE_FORCE : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_DONE_FORCE    (BIT(7))
+#define PMU_DCDC_DONE_FORCE_M  (PMU_DCDC_DONE_FORCE_V << PMU_DCDC_DONE_FORCE_S)
+#define PMU_DCDC_DONE_FORCE_V  0x00000001U
+#define PMU_DCDC_DONE_FORCE_S  7
+/** PMU_DCDC_ON_FORCE_PU : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_ON_FORCE_PU    (BIT(8))
+#define PMU_DCDC_ON_FORCE_PU_M  (PMU_DCDC_ON_FORCE_PU_V << PMU_DCDC_ON_FORCE_PU_S)
+#define PMU_DCDC_ON_FORCE_PU_V  0x00000001U
+#define PMU_DCDC_ON_FORCE_PU_S  8
+/** PMU_DCDC_ON_FORCE_PD : R/W; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_ON_FORCE_PD    (BIT(9))
+#define PMU_DCDC_ON_FORCE_PD_M  (PMU_DCDC_ON_FORCE_PD_V << PMU_DCDC_ON_FORCE_PD_S)
+#define PMU_DCDC_ON_FORCE_PD_V  0x00000001U
+#define PMU_DCDC_ON_FORCE_PD_S  9
+/** PMU_DCDC_FB_RES_FORCE_PU : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_FB_RES_FORCE_PU    (BIT(10))
+#define PMU_DCDC_FB_RES_FORCE_PU_M  (PMU_DCDC_FB_RES_FORCE_PU_V << PMU_DCDC_FB_RES_FORCE_PU_S)
+#define PMU_DCDC_FB_RES_FORCE_PU_V  0x00000001U
+#define PMU_DCDC_FB_RES_FORCE_PU_S  10
+/** PMU_DCDC_FB_RES_FORCE_PD : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_FB_RES_FORCE_PD    (BIT(11))
+#define PMU_DCDC_FB_RES_FORCE_PD_M  (PMU_DCDC_FB_RES_FORCE_PD_V << PMU_DCDC_FB_RES_FORCE_PD_S)
+#define PMU_DCDC_FB_RES_FORCE_PD_V  0x00000001U
+#define PMU_DCDC_FB_RES_FORCE_PD_S  11
+/** PMU_DCDC_LS_FORCE_PU : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_LS_FORCE_PU    (BIT(12))
+#define PMU_DCDC_LS_FORCE_PU_M  (PMU_DCDC_LS_FORCE_PU_V << PMU_DCDC_LS_FORCE_PU_S)
+#define PMU_DCDC_LS_FORCE_PU_V  0x00000001U
+#define PMU_DCDC_LS_FORCE_PU_S  12
+/** PMU_DCDC_LS_FORCE_PD : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_LS_FORCE_PD    (BIT(13))
+#define PMU_DCDC_LS_FORCE_PD_M  (PMU_DCDC_LS_FORCE_PD_V << PMU_DCDC_LS_FORCE_PD_S)
+#define PMU_DCDC_LS_FORCE_PD_V  0x00000001U
+#define PMU_DCDC_LS_FORCE_PD_S  13
+/** PMU_DCDC_DS_FORCE_PU : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_DS_FORCE_PU    (BIT(14))
+#define PMU_DCDC_DS_FORCE_PU_M  (PMU_DCDC_DS_FORCE_PU_V << PMU_DCDC_DS_FORCE_PU_S)
+#define PMU_DCDC_DS_FORCE_PU_V  0x00000001U
+#define PMU_DCDC_DS_FORCE_PU_S  14
+/** PMU_DCDC_DS_FORCE_PD : R/W; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_DS_FORCE_PD    (BIT(15))
+#define PMU_DCDC_DS_FORCE_PD_M  (PMU_DCDC_DS_FORCE_PD_V << PMU_DCDC_DS_FORCE_PD_S)
+#define PMU_DCDC_DS_FORCE_PD_V  0x00000001U
+#define PMU_DCDC_DS_FORCE_PD_S  15
+/** PMU_DCM_CUR_ST : RO; bitpos: [23:16]; default: 1;
+ *  need_des
+ */
+#define PMU_DCM_CUR_ST    0x000000FFU
+#define PMU_DCM_CUR_ST_M  (PMU_DCM_CUR_ST_V << PMU_DCM_CUR_ST_S)
+#define PMU_DCM_CUR_ST_V  0x000000FFU
+#define PMU_DCM_CUR_ST_S  16
+/** PMU_DCDC_EN_AMUX_TEST : R/W; bitpos: [29]; default: 0;
+ *  Enable analog mux to pull PAD TEST_DCDC voltage signal
+ */
+#define PMU_DCDC_EN_AMUX_TEST    (BIT(29))
+#define PMU_DCDC_EN_AMUX_TEST_M  (PMU_DCDC_EN_AMUX_TEST_V << PMU_DCDC_EN_AMUX_TEST_S)
+#define PMU_DCDC_EN_AMUX_TEST_V  0x00000001U
+#define PMU_DCDC_EN_AMUX_TEST_S  29
+
+/** PMU_DCM_WAIT_DELAY_REG register
+ *  need_des
+ */
+#define PMU_DCM_WAIT_DELAY_REG (DR_REG_PMU_BASE + 0x208)
+/** PMU_DCDC_PRE_DELAY : R/W; bitpos: [7:0]; default: 5;
+ *  DCDC pre-on/post off delay
+ */
+#define PMU_DCDC_PRE_DELAY    0x000000FFU
+#define PMU_DCDC_PRE_DELAY_M  (PMU_DCDC_PRE_DELAY_V << PMU_DCDC_PRE_DELAY_S)
+#define PMU_DCDC_PRE_DELAY_V  0x000000FFU
+#define PMU_DCDC_PRE_DELAY_S  0
+/** PMU_DCDC_RES_OFF_DELAY : R/W; bitpos: [15:8]; default: 2;
+ *  DCDC fb res off delay
+ */
+#define PMU_DCDC_RES_OFF_DELAY    0x000000FFU
+#define PMU_DCDC_RES_OFF_DELAY_M  (PMU_DCDC_RES_OFF_DELAY_V << PMU_DCDC_RES_OFF_DELAY_S)
+#define PMU_DCDC_RES_OFF_DELAY_V  0x000000FFU
+#define PMU_DCDC_RES_OFF_DELAY_S  8
+/** PMU_DCDC_STABLE_DELAY : R/W; bitpos: [25:16]; default: 75;
+ *  DCDC stable delay
+ */
+#define PMU_DCDC_STABLE_DELAY    0x000003FFU
+#define PMU_DCDC_STABLE_DELAY_M  (PMU_DCDC_STABLE_DELAY_V << PMU_DCDC_STABLE_DELAY_S)
+#define PMU_DCDC_STABLE_DELAY_V  0x000003FFU
+#define PMU_DCDC_STABLE_DELAY_S  16
+
+/** PMU_VDDBAT_CFG_REG register
+ *  need_des
+ */
+#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x20c)
+/** PMU_ANA_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_VDDBAT_MODE    0x00000003U
+#define PMU_ANA_VDDBAT_MODE_M  (PMU_ANA_VDDBAT_MODE_V << PMU_ANA_VDDBAT_MODE_S)
+#define PMU_ANA_VDDBAT_MODE_V  0x00000003U
+#define PMU_ANA_VDDBAT_MODE_S  0
+/** PMU_VDDBAT_SW_UPDATE : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_VDDBAT_SW_UPDATE    (BIT(31))
+#define PMU_VDDBAT_SW_UPDATE_M  (PMU_VDDBAT_SW_UPDATE_V << PMU_VDDBAT_SW_UPDATE_S)
+#define PMU_VDDBAT_SW_UPDATE_V  0x00000001U
+#define PMU_VDDBAT_SW_UPDATE_S  31
+
+/** PMU_TOUCH_PWR_CNTL_REG register
+ *  need_des
+ */
+#define PMU_TOUCH_PWR_CNTL_REG (DR_REG_PMU_BASE + 0x210)
+/** PMU_TOUCH_WAIT_CYCLES : R/W; bitpos: [13:5]; default: 10;
+ *  need_des
+ */
+#define PMU_TOUCH_WAIT_CYCLES    0x000001FFU
+#define PMU_TOUCH_WAIT_CYCLES_M  (PMU_TOUCH_WAIT_CYCLES_V << PMU_TOUCH_WAIT_CYCLES_S)
+#define PMU_TOUCH_WAIT_CYCLES_V  0x000001FFU
+#define PMU_TOUCH_WAIT_CYCLES_S  5
+/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [29:14]; default: 100;
+ *  need_des
+ */
+#define PMU_TOUCH_SLEEP_CYCLES    0x0000FFFFU
+#define PMU_TOUCH_SLEEP_CYCLES_M  (PMU_TOUCH_SLEEP_CYCLES_V << PMU_TOUCH_SLEEP_CYCLES_S)
+#define PMU_TOUCH_SLEEP_CYCLES_V  0x0000FFFFU
+#define PMU_TOUCH_SLEEP_CYCLES_S  14
+/** PMU_TOUCH_FORCE_DONE : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TOUCH_FORCE_DONE    (BIT(30))
+#define PMU_TOUCH_FORCE_DONE_M  (PMU_TOUCH_FORCE_DONE_V << PMU_TOUCH_FORCE_DONE_S)
+#define PMU_TOUCH_FORCE_DONE_V  0x00000001U
+#define PMU_TOUCH_FORCE_DONE_S  30
+/** PMU_TOUCH_SLEEP_TIMER_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_TOUCH_SLEEP_TIMER_EN    (BIT(31))
+#define PMU_TOUCH_SLEEP_TIMER_EN_M  (PMU_TOUCH_SLEEP_TIMER_EN_V << PMU_TOUCH_SLEEP_TIMER_EN_S)
+#define PMU_TOUCH_SLEEP_TIMER_EN_V  0x00000001U
+#define PMU_TOUCH_SLEEP_TIMER_EN_S  31
+
+/** PMU_RDN_ECO_REG register
+ *  need_des
+ */
+#define PMU_RDN_ECO_REG (DR_REG_PMU_BASE + 0x214)
+/** PMU_PMU_RDN_ECO_RESULT : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_RDN_ECO_RESULT    (BIT(0))
+#define PMU_PMU_RDN_ECO_RESULT_M  (PMU_PMU_RDN_ECO_RESULT_V << PMU_PMU_RDN_ECO_RESULT_S)
+#define PMU_PMU_RDN_ECO_RESULT_V  0x00000001U
+#define PMU_PMU_RDN_ECO_RESULT_S  0
+/** PMU_PMU_RDN_ECO_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_RDN_ECO_EN    (BIT(31))
+#define PMU_PMU_RDN_ECO_EN_M  (PMU_PMU_RDN_ECO_EN_V << PMU_PMU_RDN_ECO_EN_S)
+#define PMU_PMU_RDN_ECO_EN_V  0x00000001U
+#define PMU_PMU_RDN_ECO_EN_S  31
+
+/** PMU_POWER_PD_HP_CPU_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_HP_CPU_CNTL_REG (DR_REG_PMU_BASE + 0x218)
+/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_CPU_RESET    (BIT(0))
+#define PMU_FORCE_HP_CPU_RESET_M  (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S)
+#define PMU_FORCE_HP_CPU_RESET_V  0x00000001U
+#define PMU_FORCE_HP_CPU_RESET_S  0
+/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_CPU_ISO    (BIT(1))
+#define PMU_FORCE_HP_CPU_ISO_M  (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S)
+#define PMU_FORCE_HP_CPU_ISO_V  0x00000001U
+#define PMU_FORCE_HP_CPU_ISO_S  1
+/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_HP_CPU_PU    (BIT(2))
+#define PMU_FORCE_HP_CPU_PU_M  (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S)
+#define PMU_FORCE_HP_CPU_PU_V  0x00000001U
+#define PMU_FORCE_HP_CPU_PU_S  2
+/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_HP_CPU_NO_RESET    (BIT(3))
+#define PMU_FORCE_HP_CPU_NO_RESET_M  (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S)
+#define PMU_FORCE_HP_CPU_NO_RESET_V  0x00000001U
+#define PMU_FORCE_HP_CPU_NO_RESET_S  3
+/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_HP_CPU_NO_ISO    (BIT(4))
+#define PMU_FORCE_HP_CPU_NO_ISO_M  (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S)
+#define PMU_FORCE_HP_CPU_NO_ISO_V  0x00000001U
+#define PMU_FORCE_HP_CPU_NO_ISO_S  4
+/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_CPU_PD    (BIT(5))
+#define PMU_FORCE_HP_CPU_PD_M  (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S)
+#define PMU_FORCE_HP_CPU_PD_V  0x00000001U
+#define PMU_FORCE_HP_CPU_PD_S  5
+
+/** PMU_POWER_PD_HP_CPU_MASK_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_HP_CPU_MASK_REG (DR_REG_PMU_BASE + 0x21c)
+/** PMU_XPD_HP_CPU_MASK : R/W; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_HP_CPU_MASK    0x0000001FU
+#define PMU_XPD_HP_CPU_MASK_M  (PMU_XPD_HP_CPU_MASK_V << PMU_XPD_HP_CPU_MASK_S)
+#define PMU_XPD_HP_CPU_MASK_V  0x0000001FU
+#define PMU_XPD_HP_CPU_MASK_S  0
+/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [31:27]; default: 0;
+ *  need_des
+ */
+#define PMU_PD_HP_CPU_MASK    0x0000001FU
+#define PMU_PD_HP_CPU_MASK_M  (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S)
+#define PMU_PD_HP_CPU_MASK_V  0x0000001FU
+#define PMU_PD_HP_CPU_MASK_S  27
+
+/** PMU_DATE_REG register
+ *  need_des
+ */
+#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc)
+/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 38801456;
+ *  need_des
+ */
+#define PMU_PMU_DATE    0x7FFFFFFFU
+#define PMU_PMU_DATE_M  (PMU_PMU_DATE_V << PMU_PMU_DATE_S)
+#define PMU_PMU_DATE_V  0x7FFFFFFFU
+#define PMU_PMU_DATE_S  0
+/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_CLK_EN    (BIT(31))
+#define PMU_CLK_EN_M  (PMU_CLK_EN_V << PMU_CLK_EN_S)
+#define PMU_CLK_EN_V  0x00000001U
+#define PMU_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pmu_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pmu_eco5_struct.h
new file mode 100644
index 0000000000..b800521b0d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pmu_eco5_struct.h
@@ -0,0 +1,3973 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of hp_active_dig_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** hp_active_dcdc_switch_pd_en : R/W; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_dcdc_switch_pd_en:1;
+        /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_hp_mem_dslp:1;
+        /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_pd_hp_mem_pd_en:1;
+        uint32_t reserved_24:5;
+        /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_pd_hp_cpu_pd_en:1;
+        /** hp_active_pd_cnnt_pd_en : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_pd_cnnt_pd_en:1;
+        /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_pd_top_pd_en:1;
+    };
+    uint32_t val;
+} pmu_hp_active_dig_power_reg_t;
+
+/** Type of hp_active_icg_hp_func register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t hp_active_dig_icg_func_en:32;
+    };
+    uint32_t val;
+} pmu_hp_active_icg_hp_func_reg_t;
+
+/** Type of hp_active_icg_hp_apb register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t hp_active_dig_icg_apb_en:32;
+    };
+    uint32_t val;
+} pmu_hp_active_icg_hp_apb_reg_t;
+
+/** Type of hp_active_icg_modem register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_dig_icg_modem_code:2;
+    };
+    uint32_t val;
+} pmu_hp_active_icg_modem_reg_t;
+
+/** Type of hp_active_hp_sys_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** hp_active_hp_power_det_bypass : R/W; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_hp_power_det_bypass:1;
+        /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_uart_wakeup_en:1;
+        /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_lp_pad_hold_all:1;
+        /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_hp_pad_hold_all:1;
+        /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_dig_pad_slp_sel:1;
+        /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_dig_pause_wdt:1;
+        /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_dig_cpu_stall:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} pmu_hp_active_hp_sys_cntl_reg_t;
+
+/** Type of hp_active_hp_ck_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** hp_active_i2c_iso_en : R/W; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_i2c_iso_en:1;
+        /** hp_active_i2c_retention : R/W; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_i2c_retention:1;
+        /** hp_active_xpd_pll_i2c : R/W; bitpos: [26:23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_xpd_pll_i2c:4;
+        /** hp_active_xpd_pll : R/W; bitpos: [30:27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_xpd_pll:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_hp_active_hp_ck_power_reg_t;
+
+/** Type of hp_active_bias register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:18;
+        /** hp_active_dcm_vset : R/W; bitpos: [22:18]; default: 20;
+         *  need_des
+         */
+        uint32_t hp_active_dcm_vset:5;
+        /** hp_active_dcm_mode : R/W; bitpos: [24:23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_dcm_mode:2;
+        /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_xpd_bias:1;
+        /** hp_active_dbg_atten : R/W; bitpos: [29:26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_dbg_atten:4;
+        /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_pd_cur:1;
+        /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_bias_sleep:1;
+    };
+    uint32_t val;
+} pmu_hp_active_bias_reg_t;
+
+/** Type of hp_active_backup register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep2active_backup_modem_clk_code:2;
+        /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem2active_backup_modem_clk_code:2;
+        uint32_t reserved_8:2;
+        /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_retention_mode:1;
+        /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep2active_retention_en:1;
+        /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem2active_retention_en:1;
+        uint32_t reserved_13:1;
+        /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep2active_backup_clk_sel:2;
+        /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem2active_backup_clk_sel:2;
+        uint32_t reserved_18:2;
+        /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep2active_backup_mode:3;
+        /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem2active_backup_mode:3;
+        uint32_t reserved_26:3;
+        /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep2active_backup_en:1;
+        /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem2active_backup_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_hp_active_backup_reg_t;
+
+/** Type of hp_active_backup_clk register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_backup_icg_func_en:32;
+    };
+    uint32_t val;
+} pmu_hp_active_backup_clk_reg_t;
+
+/** Type of hp_active_sysclk register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_dig_sys_clk_no_div:1;
+        /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_icg_sys_clock_en:1;
+        /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_sys_clk_slp_sel:1;
+        /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_icg_slp_sel:1;
+        /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_dig_sys_clk_sel:2;
+    };
+    uint32_t val;
+} pmu_hp_active_sysclk_reg_t;
+
+/** Type of hp_active_hp_regulator0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24;
+         *  need_des
+         */
+        uint32_t lp_dbias_vol:5;
+        /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24;
+         *  need_des
+         */
+        uint32_t hp_dbias_vol:5;
+        /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1;
+         *  need_des
+         */
+        uint32_t dig_regulator0_dbias_sel:1;
+        /** dig_dbias_init : WT; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t dig_dbias_init:1;
+        /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_active_hp_regulator_slp_mem_xpd:1;
+        /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_active_hp_regulator_slp_logic_xpd:1;
+        /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_active_hp_regulator_xpd:1;
+        /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12;
+         *  need_des
+         */
+        uint32_t hp_active_hp_regulator_slp_mem_dbias:4;
+        /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12;
+         *  need_des
+         */
+        uint32_t hp_active_hp_regulator_slp_logic_dbias:4;
+        /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24;
+         *  need_des
+         */
+        uint32_t hp_active_hp_regulator_dbias:5;
+    };
+    uint32_t val;
+} pmu_hp_active_hp_regulator0_reg_t;
+
+/** Type of hp_active_hp_regulator1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active_hp_regulator_drv_b:6;
+    };
+    uint32_t val;
+} pmu_hp_active_hp_regulator1_reg_t;
+
+/** Type of hp_active_xtal register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_active_xpd_xtal:1;
+    };
+    uint32_t val;
+} pmu_hp_active_xtal_reg_t;
+
+/** Type of hp_modem_dig_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** hp_modem_dcdc_switch_pd_en : R/W; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dcdc_switch_pd_en:1;
+        /** hp_modem_hp_mem_dslp : WT; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_hp_mem_dslp:1;
+        /** hp_modem_pd_hp_mem_pd_en : WT; bitpos: [26:23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_pd_hp_mem_pd_en:4;
+        /** hp_modem_pd_hp_wifi_pd_en : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_pd_hp_wifi_pd_en:1;
+        uint32_t reserved_28:1;
+        /** hp_modem_pd_hp_cpu_pd_en : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_pd_hp_cpu_pd_en:1;
+        /** hp_modem_pd_cnnt_pd_en : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_pd_cnnt_pd_en:1;
+        /** hp_modem_pd_top_pd_en : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_pd_top_pd_en:1;
+    };
+    uint32_t val;
+} pmu_hp_modem_dig_power_reg_t;
+
+/** Type of hp_modem_icg_hp_func register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_modem_dig_icg_func_en : WT; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dig_icg_func_en:32;
+    };
+    uint32_t val;
+} pmu_hp_modem_icg_hp_func_reg_t;
+
+/** Type of hp_modem_icg_hp_apb register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_modem_dig_icg_apb_en : WT; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dig_icg_apb_en:32;
+    };
+    uint32_t val;
+} pmu_hp_modem_icg_hp_apb_reg_t;
+
+/** Type of hp_modem_icg_modem register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** hp_modem_dig_icg_modem_code : WT; bitpos: [31:30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dig_icg_modem_code:2;
+    };
+    uint32_t val;
+} pmu_hp_modem_icg_modem_reg_t;
+
+/** Type of hp_modem_hp_sys_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** hp_modem_hp_power_det_bypass : WT; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_hp_power_det_bypass:1;
+        /** hp_modem_uart_wakeup_en : WT; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_uart_wakeup_en:1;
+        /** hp_modem_lp_pad_hold_all : WT; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_lp_pad_hold_all:1;
+        /** hp_modem_hp_pad_hold_all : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_hp_pad_hold_all:1;
+        /** hp_modem_dig_pad_slp_sel : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dig_pad_slp_sel:1;
+        /** hp_modem_dig_pause_wdt : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dig_pause_wdt:1;
+        /** hp_modem_dig_cpu_stall : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dig_cpu_stall:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} pmu_hp_modem_hp_sys_cntl_reg_t;
+
+/** Type of hp_modem_hp_ck_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** hp_modem_i2c_iso_en : WT; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_i2c_iso_en:1;
+        /** hp_modem_i2c_retention : WT; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_i2c_retention:1;
+        /** hp_modem_xpd_pll_i2c : WT; bitpos: [26:23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_xpd_pll_i2c:4;
+        /** hp_modem_xpd_pll : WT; bitpos: [30:27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_xpd_pll:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_hp_modem_hp_ck_power_reg_t;
+
+/** Type of hp_modem_bias register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:18;
+        /** hp_modem_dcm_vset : WT; bitpos: [22:18]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dcm_vset:5;
+        /** hp_modem_dcm_mode : WT; bitpos: [24:23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dcm_mode:2;
+        /** hp_modem_xpd_bias : WT; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_xpd_bias:1;
+        /** hp_modem_dbg_atten : WT; bitpos: [29:26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dbg_atten:4;
+        /** hp_modem_pd_cur : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_pd_cur:1;
+        /** hp_modem_bias_sleep : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_bias_sleep:1;
+    };
+    uint32_t val;
+} pmu_hp_modem_bias_reg_t;
+
+/** Type of hp_modem_backup register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** hp_sleep2modem_backup_modem_clk_code : WT; bitpos: [5:4]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep2modem_backup_modem_clk_code:2;
+        uint32_t reserved_6:4;
+        /** hp_modem_retention_mode : WT; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_retention_mode:1;
+        /** hp_sleep2modem_retention_en : WT; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep2modem_retention_en:1;
+        uint32_t reserved_12:2;
+        /** hp_sleep2modem_backup_clk_sel : WT; bitpos: [15:14]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep2modem_backup_clk_sel:2;
+        uint32_t reserved_16:4;
+        /** hp_sleep2modem_backup_mode : WT; bitpos: [22:20]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep2modem_backup_mode:3;
+        uint32_t reserved_23:6;
+        /** hp_sleep2modem_backup_en : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep2modem_backup_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} pmu_hp_modem_backup_reg_t;
+
+/** Type of hp_modem_backup_clk register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_modem_backup_icg_func_en : WT; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_backup_icg_func_en:32;
+    };
+    uint32_t val;
+} pmu_hp_modem_backup_clk_reg_t;
+
+/** Type of hp_modem_sysclk register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** hp_modem_dig_sys_clk_no_div : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dig_sys_clk_no_div:1;
+        /** hp_modem_icg_sys_clock_en : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_icg_sys_clock_en:1;
+        /** hp_modem_sys_clk_slp_sel : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_sys_clk_slp_sel:1;
+        /** hp_modem_icg_slp_sel : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_icg_slp_sel:1;
+        /** hp_modem_dig_sys_clk_sel : WT; bitpos: [31:30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_dig_sys_clk_sel:2;
+    };
+    uint32_t val;
+} pmu_hp_modem_sysclk_reg_t;
+
+/** Type of hp_modem_hp_regulator0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** hp_modem_hp_regulator_slp_mem_xpd : WT; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_hp_regulator_slp_mem_xpd:1;
+        /** hp_modem_hp_regulator_slp_logic_xpd : WT; bitpos: [17]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_hp_regulator_slp_logic_xpd:1;
+        /** hp_modem_hp_regulator_xpd : WT; bitpos: [18]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_hp_regulator_xpd:1;
+        /** hp_modem_hp_regulator_slp_mem_dbias : WT; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_hp_regulator_slp_mem_dbias:4;
+        /** hp_modem_hp_regulator_slp_logic_dbias : WT; bitpos: [26:23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_hp_regulator_slp_logic_dbias:4;
+        /** hp_modem_hp_regulator_dbias : WT; bitpos: [31:27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_hp_regulator_dbias:5;
+    };
+    uint32_t val;
+} pmu_hp_modem_hp_regulator0_reg_t;
+
+/** Type of hp_modem_hp_regulator1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** hp_modem_hp_regulator_drv_b : WT; bitpos: [31:8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_hp_regulator_drv_b:24;
+    };
+    uint32_t val;
+} pmu_hp_modem_hp_regulator1_reg_t;
+
+/** Type of hp_modem_xtal register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** hp_modem_xpd_xtal : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem_xpd_xtal:1;
+    };
+    uint32_t val;
+} pmu_hp_modem_xtal_reg_t;
+
+/** Type of hp_sleep_dig_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** hp_sleep_dcdc_switch_pd_en : R/W; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_dcdc_switch_pd_en:1;
+        /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_hp_mem_dslp:1;
+        /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_pd_hp_mem_pd_en:1;
+        uint32_t reserved_24:5;
+        /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_pd_hp_cpu_pd_en:1;
+        /** hp_sleep_pd_cnnt_pd_en : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_pd_cnnt_pd_en:1;
+        /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_pd_top_pd_en:1;
+    };
+    uint32_t val;
+} pmu_hp_sleep_dig_power_reg_t;
+
+/** Type of hp_sleep_icg_hp_func register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t hp_sleep_dig_icg_func_en:32;
+    };
+    uint32_t val;
+} pmu_hp_sleep_icg_hp_func_reg_t;
+
+/** Type of hp_sleep_icg_hp_apb register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t hp_sleep_dig_icg_apb_en:32;
+    };
+    uint32_t val;
+} pmu_hp_sleep_icg_hp_apb_reg_t;
+
+/** Type of hp_sleep_icg_modem register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_dig_icg_modem_code:2;
+    };
+    uint32_t val;
+} pmu_hp_sleep_icg_modem_reg_t;
+
+/** Type of hp_sleep_hp_sys_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** hp_sleep_hp_power_det_bypass : R/W; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_hp_power_det_bypass:1;
+        /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_uart_wakeup_en:1;
+        /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_lp_pad_hold_all:1;
+        /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_hp_pad_hold_all:1;
+        /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_dig_pad_slp_sel:1;
+        /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_dig_pause_wdt:1;
+        /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_dig_cpu_stall:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} pmu_hp_sleep_hp_sys_cntl_reg_t;
+
+/** Type of hp_sleep_hp_ck_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** hp_sleep_i2c_iso_en : R/W; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_i2c_iso_en:1;
+        /** hp_sleep_i2c_retention : R/W; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_i2c_retention:1;
+        /** hp_sleep_xpd_pll_i2c : R/W; bitpos: [26:23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_xpd_pll_i2c:4;
+        /** hp_sleep_xpd_pll : R/W; bitpos: [30:27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_xpd_pll:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_hp_sleep_hp_ck_power_reg_t;
+
+/** Type of hp_sleep_bias register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:18;
+        /** hp_sleep_dcm_vset : R/W; bitpos: [22:18]; default: 20;
+         *  need_des
+         */
+        uint32_t hp_sleep_dcm_vset:5;
+        /** hp_sleep_dcm_mode : R/W; bitpos: [24:23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_dcm_mode:2;
+        /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_xpd_bias:1;
+        /** hp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_dbg_atten:4;
+        /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_pd_cur:1;
+        /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_bias_sleep:1;
+    };
+    uint32_t val;
+} pmu_hp_sleep_bias_reg_t;
+
+/** Type of hp_sleep_backup register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem2sleep_backup_modem_clk_code:2;
+        /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active2sleep_backup_modem_clk_code:2;
+        /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_retention_mode:1;
+        uint32_t reserved_11:1;
+        /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem2sleep_retention_en:1;
+        /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active2sleep_retention_en:1;
+        uint32_t reserved_14:2;
+        /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem2sleep_backup_clk_sel:2;
+        /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active2sleep_backup_clk_sel:2;
+        uint32_t reserved_20:3;
+        /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem2sleep_backup_mode:3;
+        /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active2sleep_backup_mode:3;
+        uint32_t reserved_29:1;
+        /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_modem2sleep_backup_en:1;
+        /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_active2sleep_backup_en:1;
+    };
+    uint32_t val;
+} pmu_hp_sleep_backup_reg_t;
+
+/** Type of hp_sleep_backup_clk register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_backup_icg_func_en:32;
+    };
+    uint32_t val;
+} pmu_hp_sleep_backup_clk_reg_t;
+
+/** Type of hp_sleep_sysclk register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_dig_sys_clk_no_div:1;
+        /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_icg_sys_clock_en:1;
+        /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_sys_clk_slp_sel:1;
+        /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_icg_slp_sel:1;
+        /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_dig_sys_clk_sel:2;
+    };
+    uint32_t val;
+} pmu_hp_sleep_sysclk_reg_t;
+
+/** Type of hp_sleep_hp_regulator0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1;
+        /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1;
+        /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_sleep_hp_regulator_xpd:1;
+        /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12;
+         *  need_des
+         */
+        uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4;
+        /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12;
+         *  need_des
+         */
+        uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4;
+        /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24;
+         *  need_des
+         */
+        uint32_t hp_sleep_hp_regulator_dbias:5;
+    };
+    uint32_t val;
+} pmu_hp_sleep_hp_regulator0_reg_t;
+
+/** Type of hp_sleep_hp_regulator1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_hp_regulator_drv_b:6;
+    };
+    uint32_t val;
+} pmu_hp_sleep_hp_regulator1_reg_t;
+
+/** Type of hp_sleep_xtal register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_sleep_xpd_xtal:1;
+    };
+    uint32_t val;
+} pmu_hp_sleep_xtal_reg_t;
+
+/** Type of hp_sleep_lp_regulator0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_sleep_lp_regulator_slp_xpd:1;
+        /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_sleep_lp_regulator_xpd:1;
+        /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12;
+         *  need_des
+         */
+        uint32_t hp_sleep_lp_regulator_slp_dbias:4;
+        /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24;
+         *  need_des
+         */
+        uint32_t hp_sleep_lp_regulator_dbias:5;
+    };
+    uint32_t val;
+} pmu_hp_sleep_lp_regulator0_reg_t;
+
+/** Type of hp_sleep_lp_regulator1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_lp_regulator_drv_b:6;
+    };
+    uint32_t val;
+} pmu_hp_sleep_lp_regulator1_reg_t;
+
+/** Type of hp_sleep_lp_dig_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** hp_sleep_lp_pad_slp_sel : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_lp_pad_slp_sel:1;
+        /** hp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_bod_source_sel:1;
+        /** hp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_vddbat_mode:2;
+        /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_lp_mem_dslp:1;
+        /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_pd_lp_peri_pd_en:1;
+    };
+    uint32_t val;
+} pmu_hp_sleep_lp_dig_power_reg_t;
+
+/** Type of hp_sleep_lp_ck_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** hp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_xpd_lppll:1;
+        /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_xpd_xtal32k:1;
+        /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_xpd_rc32k:1;
+        /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_sleep_xpd_fosc_clk:1;
+        /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sleep_pd_osc_clk:1;
+    };
+    uint32_t val;
+} pmu_hp_sleep_lp_ck_power_reg_t;
+
+/** Type of lp_sleep_lp_regulator0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_sleep_lp_regulator_slp_xpd:1;
+        /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_sleep_lp_regulator_xpd:1;
+        /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12;
+         *  need_des
+         */
+        uint32_t lp_sleep_lp_regulator_slp_dbias:4;
+        /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24;
+         *  need_des
+         */
+        uint32_t lp_sleep_lp_regulator_dbias:5;
+    };
+    uint32_t val;
+} pmu_lp_sleep_lp_regulator0_reg_t;
+
+/** Type of lp_sleep_lp_regulator1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_lp_regulator_drv_b:6;
+    };
+    uint32_t val;
+} pmu_lp_sleep_lp_regulator1_reg_t;
+
+/** Type of lp_sleep_xtal register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_sleep_xpd_xtal:1;
+    };
+    uint32_t val;
+} pmu_lp_sleep_xtal_reg_t;
+
+/** Type of lp_sleep_lp_dig_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** lp_sleep_lp_pad_slp_sel : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_lp_pad_slp_sel:1;
+        /** lp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_bod_source_sel:1;
+        /** lp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_vddbat_mode:2;
+        /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_lp_mem_dslp:1;
+        /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_pd_lp_peri_pd_en:1;
+    };
+    uint32_t val;
+} pmu_lp_sleep_lp_dig_power_reg_t;
+
+/** Type of lp_sleep_lp_ck_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** lp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_xpd_lppll:1;
+        /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_xpd_xtal32k:1;
+        /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_xpd_rc32k:1;
+        /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_sleep_xpd_fosc_clk:1;
+        /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_pd_osc_clk:1;
+    };
+    uint32_t val;
+} pmu_lp_sleep_lp_ck_power_reg_t;
+
+/** Type of lp_sleep_bias register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_xpd_bias:1;
+        /** lp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_dbg_atten:4;
+        /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_pd_cur:1;
+        /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sleep_bias_sleep:1;
+    };
+    uint32_t val;
+} pmu_lp_sleep_bias_reg_t;
+
+/** Type of imm_hp_ck_power register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tie_low_cali_xtal_icg : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_cali_xtal_icg:1;
+        /** tie_low_global_pll_icg : WT; bitpos: [4:1]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_global_pll_icg:4;
+        /** tie_low_global_xtal_icg : WT; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_global_xtal_icg:1;
+        /** tie_low_i2c_retention : WT; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_i2c_retention:1;
+        /** tie_low_xpd_pll_i2c : WT; bitpos: [10:7]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_xpd_pll_i2c:4;
+        /** tie_low_xpd_pll : WT; bitpos: [14:11]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_xpd_pll:4;
+        /** tie_low_xpd_xtal : WT; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_xpd_xtal:1;
+        /** tie_high_cali_xtal_icg : R/W; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_cali_xtal_icg:1;
+        /** tie_high_global_pll_icg : WT; bitpos: [20:17]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_global_pll_icg:4;
+        /** tie_high_global_xtal_icg : WT; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_global_xtal_icg:1;
+        /** tie_high_i2c_retention : WT; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_i2c_retention:1;
+        /** tie_high_xpd_pll_i2c : WT; bitpos: [26:23]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_xpd_pll_i2c:4;
+        /** tie_high_xpd_pll : WT; bitpos: [30:27]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_xpd_pll:4;
+        /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_xpd_xtal:1;
+    };
+    uint32_t val;
+} pmu_imm_hp_ck_power_reg_t;
+
+/** Type of imm_sleep_sysclk register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** update_dig_icg_switch : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t update_dig_icg_switch:1;
+        /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_icg_slp_sel:1;
+        /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_icg_slp_sel:1;
+        /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t update_dig_sys_clk_sel:1;
+    };
+    uint32_t val;
+} pmu_imm_sleep_sysclk_reg_t;
+
+/** Type of imm_hp_func_icg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t update_dig_icg_func_en:1;
+    };
+    uint32_t val;
+} pmu_imm_hp_func_icg_reg_t;
+
+/** Type of imm_hp_apb_icg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t update_dig_icg_apb_en:1;
+    };
+    uint32_t val;
+} pmu_imm_hp_apb_icg_reg_t;
+
+/** Type of imm_modem_icg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t update_dig_icg_modem_en:1;
+    };
+    uint32_t val;
+} pmu_imm_modem_icg_reg_t;
+
+/** Type of imm_lp_icg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_lp_rootclk_sel:1;
+        /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_lp_rootclk_sel:1;
+    };
+    uint32_t val;
+} pmu_imm_lp_icg_reg_t;
+
+/** Type of imm_pad_hold_all register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad_slp_sel : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_slp_sel:1;
+        /** lp_pad_hold_all : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_pad_hold_all:1;
+        /** hp_pad_hold_all : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_pad_hold_all:1;
+        uint32_t reserved_3:23;
+        /** tie_high_pad_slp_sel : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_pad_slp_sel:1;
+        /** tie_low_pad_slp_sel : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_pad_slp_sel:1;
+        /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_lp_pad_hold_all:1;
+        /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_lp_pad_hold_all:1;
+        /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_hp_pad_hold_all:1;
+        /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_hp_pad_hold_all:1;
+    };
+    uint32_t val;
+} pmu_imm_pad_hold_all_reg_t;
+
+/** Type of imm_i2c_iso register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_high_i2c_iso_en:1;
+        /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tie_low_i2c_iso_en:1;
+    };
+    uint32_t val;
+} pmu_imm_i2c_iso_reg_t;
+
+/** Type of power_wait_timer0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255;
+         *  need_des
+         */
+        uint32_t dg_hp_powerdown_timer:9;
+        /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255;
+         *  need_des
+         */
+        uint32_t dg_hp_powerup_timer:9;
+        /** dg_hp_wait_timer : R/W; bitpos: [31:23]; default: 255;
+         *  need_des
+         */
+        uint32_t dg_hp_wait_timer:9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer0_reg_t;
+
+/** Type of power_wait_timer1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** dg_lp_powerdown_timer : R/W; bitpos: [13:5]; default: 255;
+         *  need_des
+         */
+        uint32_t dg_lp_powerdown_timer:9;
+        /** dg_lp_powerup_timer : R/W; bitpos: [22:14]; default: 255;
+         *  need_des
+         */
+        uint32_t dg_lp_powerup_timer:9;
+        /** dg_lp_wait_timer : R/W; bitpos: [31:23]; default: 255;
+         *  need_des
+         */
+        uint32_t dg_lp_wait_timer:9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer1_reg_t;
+
+/** Type of power_pd_top_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** force_top_reset : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t force_top_reset:1;
+        /** force_top_iso : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t force_top_iso:1;
+        /** force_top_pu : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t force_top_pu:1;
+        /** force_top_no_reset : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t force_top_no_reset:1;
+        /** force_top_no_iso : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t force_top_no_iso:1;
+        /** force_top_pd : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t force_top_pd:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} pmu_power_pd_top_cntl_reg_t;
+
+/** Type of power_pd_cnnt_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** force_cnnt_reset : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t force_cnnt_reset:1;
+        /** force_cnnt_iso : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t force_cnnt_iso:1;
+        /** force_cnnt_pu : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t force_cnnt_pu:1;
+        /** force_cnnt_no_reset : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t force_cnnt_no_reset:1;
+        /** force_cnnt_no_iso : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t force_cnnt_no_iso:1;
+        /** force_cnnt_pd : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t force_cnnt_pd:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} pmu_power_pd_cnnt_cntl_reg_t;
+
+/** Type of power_pd_hpmem_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** force_hp_mem_reset : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t force_hp_mem_reset:1;
+        /** force_hp_mem_iso : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t force_hp_mem_iso:1;
+        /** force_hp_mem_pu : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t force_hp_mem_pu:1;
+        /** force_hp_mem_no_reset : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t force_hp_mem_no_reset:1;
+        /** force_hp_mem_no_iso : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t force_hp_mem_no_iso:1;
+        /** force_hp_mem_pd : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t force_hp_mem_pd:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} pmu_power_pd_hpmem_cntl_reg_t;
+
+/** Type of power_pd_top_mask register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** xpd_top_mask : R/W; bitpos: [4:0]; default: 0;
+         *  need_des
+         */
+        uint32_t xpd_top_mask:5;
+        uint32_t reserved_5:22;
+        /** pd_top_mask : R/W; bitpos: [31:27]; default: 0;
+         *  need_des
+         */
+        uint32_t pd_top_mask:5;
+    };
+    uint32_t val;
+} pmu_power_pd_top_mask_reg_t;
+
+/** Type of power_pd_cnnt_mask register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** xpd_cnnt_mask : R/W; bitpos: [4:0]; default: 0;
+         *  need_des
+         */
+        uint32_t xpd_cnnt_mask:5;
+        uint32_t reserved_5:22;
+        /** pd_cnnt_mask : R/W; bitpos: [31:27]; default: 0;
+         *  need_des
+         */
+        uint32_t pd_cnnt_mask:5;
+    };
+    uint32_t val;
+} pmu_power_pd_cnnt_mask_reg_t;
+
+/** Type of power_pd_hpmem_mask register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** xpd_hp_mem_mask : R/W; bitpos: [5:0]; default: 0;
+         *  need_des
+         */
+        uint32_t xpd_hp_mem_mask:6;
+        uint32_t reserved_6:20;
+        /** pd_hp_mem_mask : R/W; bitpos: [31:26]; default: 0;
+         *  need_des
+         */
+        uint32_t pd_hp_mem_mask:6;
+    };
+    uint32_t val;
+} pmu_power_pd_hpmem_mask_reg_t;
+
+/** Type of power_dcdc_switch register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** force_dcdc_switch_pu : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t force_dcdc_switch_pu:1;
+        /** force_dcdc_switch_pd : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t force_dcdc_switch_pd:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pmu_power_dcdc_switch_reg_t;
+
+/** Type of power_pd_lpperi_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t force_lp_peri_reset:1;
+        /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t force_lp_peri_iso:1;
+        /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t force_lp_peri_pu:1;
+        /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t force_lp_peri_no_reset:1;
+        /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t force_lp_peri_no_iso:1;
+        /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t force_lp_peri_pd:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} pmu_power_pd_lpperi_cntl_reg_t;
+
+/** Type of power_pd_lpperi_mask register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** xpd_lp_peri_mask : R/W; bitpos: [4:0]; default: 0;
+         *  need_des
+         */
+        uint32_t xpd_lp_peri_mask:5;
+        uint32_t reserved_5:22;
+        /** pd_lp_peri_mask : R/W; bitpos: [31:27]; default: 0;
+         *  need_des
+         */
+        uint32_t pd_lp_peri_mask:5;
+    };
+    uint32_t val;
+} pmu_power_pd_lpperi_mask_reg_t;
+
+/** Type of power_hp_pad register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t force_hp_pad_no_iso_all:1;
+        /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t force_hp_pad_iso_all:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pmu_power_hp_pad_reg_t;
+
+/** Type of power_ck_wait_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pmu_wait_xtl_stable : R/W; bitpos: [15:0]; default: 256;
+         *  need_des
+         */
+        uint32_t pmu_wait_xtl_stable:16;
+        /** pmu_wait_pll_stable : R/W; bitpos: [31:16]; default: 256;
+         *  need_des
+         */
+        uint32_t pmu_wait_pll_stable:16;
+    };
+    uint32_t val;
+} pmu_power_ck_wait_cntl_reg_t;
+
+/** Type of slp_wakeup_cntl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** sleep_req : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_req:1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl0_reg_t;
+
+/** Type of slp_wakeup_cntl1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_reject_ena:31;
+        /** slp_reject_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_reject_en:1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl1_reg_t;
+
+/** Type of slp_wakeup_cntl2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wakeup_ena : R/W; bitpos: [30:0]; default: 0;
+         *  need_des
+         */
+        uint32_t wakeup_ena:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl2_reg_t;
+
+/** Type of slp_wakeup_cntl3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_min_slp_val:8;
+        /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_min_slp_val:8;
+        /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_prt_sel:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl3_reg_t;
+
+/** Type of slp_wakeup_cntl4 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_reject_cause_clr:1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl4_reg_t;
+
+/** Type of slp_wakeup_cntl5 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** modem_wait_target : R/W; bitpos: [19:0]; default: 128;
+         *  need_des
+         */
+        uint32_t modem_wait_target:20;
+        uint32_t reserved_20:2;
+        /** lp_ana_wait_target_expand : R/W; bitpos: [23:22]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_ana_wait_target_expand:2;
+        /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_ana_wait_target:8;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl5_reg_t;
+
+/** Type of slp_wakeup_cntl6 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128;
+         *  need_des
+         */
+        uint32_t soc_wakeup_wait:20;
+        uint32_t reserved_20:10;
+        /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_wait_cfg:2;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl6_reg_t;
+
+/** Type of slp_wakeup_cntl7 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** ana_wait_target : R/W; bitpos: [31:16]; default: 1;
+         *  need_des
+         */
+        uint32_t ana_wait_target:16;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl7_reg_t;
+
+/** Type of slp_wakeup_cntl8 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_lite_wakeup_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_lite_wakeup_ena:1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl8_reg_t;
+
+/** Type of slp_wakeup_status0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wakeup_cause : RO; bitpos: [30:0]; default: 0;
+         *  need_des
+         */
+        uint32_t wakeup_cause:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_status0_reg_t;
+
+/** Type of slp_wakeup_status1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reject_cause : RO; bitpos: [30:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reject_cause:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_status1_reg_t;
+
+/** Type of slp_wakeup_status2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_lite_wakeup_cause : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_lite_wakeup_cause:1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_status2_reg_t;
+
+/** Type of hp_ck_poweron register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50;
+         *  need_des
+         */
+        uint32_t i2c_por_wait_target:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} pmu_hp_ck_poweron_reg_t;
+
+/** Type of hp_ck_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10;
+         *  need_des
+         */
+        uint32_t modify_icg_cntl_wait:8;
+        /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10;
+         *  need_des
+         */
+        uint32_t switch_icg_cntl_wait:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} pmu_hp_ck_cntl_reg_t;
+
+/** Type of por_status register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** por_done : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t por_done:1;
+    };
+    uint32_t val;
+} pmu_por_status_reg_t;
+
+/** Type of rf_pwc register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** mspi_phy_xpd : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t mspi_phy_xpd:1;
+        /** sdio_pll_xpd : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t sdio_pll_xpd:1;
+        /** perif_i2c_rstb : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t perif_i2c_rstb:1;
+        /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1;
+         *  need_des
+         */
+        uint32_t xpd_perif_i2c:1;
+        /** xpd_txrf_i2c : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t xpd_txrf_i2c:1;
+        /** xpd_rfrx_pbus : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t xpd_rfrx_pbus:1;
+        /** xpd_ckgen_i2c : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t xpd_ckgen_i2c:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_rf_pwc_reg_t;
+
+/** Type of backup_cfg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t backup_sys_clk_no_div:1;
+    };
+    uint32_t val;
+} pmu_backup_cfg_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** pmu_0p1a_cnt_target0_reach_0_hp_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  reg_0p1a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_raw:1;
+        /** pmu_0p1a_cnt_target1_reach_0_hp_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_raw:1;
+        /** pmu_0p1a_cnt_target0_reach_1_hp_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  reg_0p1a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_raw:1;
+        /** pmu_0p1a_cnt_target1_reach_1_hp_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_raw:1;
+        /** pmu_0p2a_cnt_target0_reach_0_hp_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_raw:1;
+        /** pmu_0p2a_cnt_target1_reach_0_hp_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_raw:1;
+        /** pmu_0p2a_cnt_target0_reach_1_hp_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_raw:1;
+        /** pmu_0p2a_cnt_target1_reach_1_hp_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_raw:1;
+        /** pmu_0p3a_cnt_target0_reach_0_hp_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  reg_0p3a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_raw:1;
+        /** pmu_0p3a_cnt_target1_reach_0_hp_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_raw:1;
+        /** pmu_0p3a_cnt_target0_reach_1_hp_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  reg_0p3a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_raw:1;
+        /** pmu_0p3a_cnt_target1_reach_1_hp_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_raw:1;
+        uint32_t reserved_26:1;
+        /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_exc_int_raw:1;
+        /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t sdio_idle_int_raw:1;
+        /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t sw_int_raw:1;
+        /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_sleep_reject_int_raw:1;
+        /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_raw:1;
+    };
+    uint32_t val;
+} pmu_int_raw_reg_t;
+
+/** Type of hp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** pmu_0p1a_cnt_target0_reach_0_hp_int_st : RO; bitpos: [14]; default: 0;
+         *  reg_0p1a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_st:1;
+        /** pmu_0p1a_cnt_target1_reach_0_hp_int_st : RO; bitpos: [15]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_st:1;
+        /** pmu_0p1a_cnt_target0_reach_1_hp_int_st : RO; bitpos: [16]; default: 0;
+         *  reg_0p1a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_st:1;
+        /** pmu_0p1a_cnt_target1_reach_1_hp_int_st : RO; bitpos: [17]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_st:1;
+        /** pmu_0p2a_cnt_target0_reach_0_hp_int_st : RO; bitpos: [18]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_st:1;
+        /** pmu_0p2a_cnt_target1_reach_0_hp_int_st : RO; bitpos: [19]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_st:1;
+        /** pmu_0p2a_cnt_target0_reach_1_hp_int_st : RO; bitpos: [20]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_st:1;
+        /** pmu_0p2a_cnt_target1_reach_1_hp_int_st : RO; bitpos: [21]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_st:1;
+        /** pmu_0p3a_cnt_target0_reach_0_hp_int_st : RO; bitpos: [22]; default: 0;
+         *  reg_0p3a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_st:1;
+        /** pmu_0p3a_cnt_target1_reach_0_hp_int_st : RO; bitpos: [23]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_st:1;
+        /** pmu_0p3a_cnt_target0_reach_1_hp_int_st : RO; bitpos: [24]; default: 0;
+         *  reg_0p3a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_st:1;
+        /** pmu_0p3a_cnt_target1_reach_1_hp_int_st : RO; bitpos: [25]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_st:1;
+        uint32_t reserved_26:1;
+        /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_exc_int_st:1;
+        /** sdio_idle_int_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t sdio_idle_int_st:1;
+        /** sw_int_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t sw_int_st:1;
+        /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_sleep_reject_int_st:1;
+        /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_st:1;
+    };
+    uint32_t val;
+} pmu_hp_int_st_reg_t;
+
+/** Type of hp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** pmu_0p1a_cnt_target0_reach_0_hp_int_ena : R/W; bitpos: [14]; default: 0;
+         *  reg_0p1a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_ena:1;
+        /** pmu_0p1a_cnt_target1_reach_0_hp_int_ena : R/W; bitpos: [15]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_ena:1;
+        /** pmu_0p1a_cnt_target0_reach_1_hp_int_ena : R/W; bitpos: [16]; default: 0;
+         *  reg_0p1a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_ena:1;
+        /** pmu_0p1a_cnt_target1_reach_1_hp_int_ena : R/W; bitpos: [17]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_ena:1;
+        /** pmu_0p2a_cnt_target0_reach_0_hp_int_ena : R/W; bitpos: [18]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_ena:1;
+        /** pmu_0p2a_cnt_target1_reach_0_hp_int_ena : R/W; bitpos: [19]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_ena:1;
+        /** pmu_0p2a_cnt_target0_reach_1_hp_int_ena : R/W; bitpos: [20]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_ena:1;
+        /** pmu_0p2a_cnt_target1_reach_1_hp_int_ena : R/W; bitpos: [21]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_ena:1;
+        /** pmu_0p3a_cnt_target0_reach_0_hp_int_ena : R/W; bitpos: [22]; default: 0;
+         *  reg_0p3a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_ena:1;
+        /** pmu_0p3a_cnt_target1_reach_0_hp_int_ena : R/W; bitpos: [23]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_ena:1;
+        /** pmu_0p3a_cnt_target0_reach_1_hp_int_ena : R/W; bitpos: [24]; default: 0;
+         *  reg_0p3a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_ena:1;
+        /** pmu_0p3a_cnt_target1_reach_1_hp_int_ena : R/W; bitpos: [25]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_ena:1;
+        uint32_t reserved_26:1;
+        /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_exc_int_ena:1;
+        /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t sdio_idle_int_ena:1;
+        /** sw_int_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t sw_int_ena:1;
+        /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_sleep_reject_int_ena:1;
+        /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_ena:1;
+    };
+    uint32_t val;
+} pmu_hp_int_ena_reg_t;
+
+/** Type of hp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** pmu_0p1a_cnt_target0_reach_0_hp_int_clr : WT; bitpos: [14]; default: 0;
+         *  reg_0p1a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_clr:1;
+        /** pmu_0p1a_cnt_target1_reach_0_hp_int_clr : WT; bitpos: [15]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_clr:1;
+        /** pmu_0p1a_cnt_target0_reach_1_hp_int_clr : WT; bitpos: [16]; default: 0;
+         *  reg_0p1a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_clr:1;
+        /** pmu_0p1a_cnt_target1_reach_1_hp_int_clr : WT; bitpos: [17]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_clr:1;
+        /** pmu_0p2a_cnt_target0_reach_0_hp_int_clr : WT; bitpos: [18]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_clr:1;
+        /** pmu_0p2a_cnt_target1_reach_0_hp_int_clr : WT; bitpos: [19]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_clr:1;
+        /** pmu_0p2a_cnt_target0_reach_1_hp_int_clr : WT; bitpos: [20]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_clr:1;
+        /** pmu_0p2a_cnt_target1_reach_1_hp_int_clr : WT; bitpos: [21]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_clr:1;
+        /** pmu_0p3a_cnt_target0_reach_0_hp_int_clr : WT; bitpos: [22]; default: 0;
+         *  reg_0p3a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_clr:1;
+        /** pmu_0p3a_cnt_target1_reach_0_hp_int_clr : WT; bitpos: [23]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_clr:1;
+        /** pmu_0p3a_cnt_target0_reach_1_hp_int_clr : WT; bitpos: [24]; default: 0;
+         *  reg_0p3a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_clr:1;
+        /** pmu_0p3a_cnt_target1_reach_1_hp_int_clr : WT; bitpos: [25]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_clr:1;
+        uint32_t reserved_26:1;
+        /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_exc_int_clr:1;
+        /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t sdio_idle_int_clr:1;
+        /** sw_int_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t sw_int_clr:1;
+        /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_sleep_reject_int_clr:1;
+        /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_clr:1;
+    };
+    uint32_t val;
+} pmu_hp_int_clr_reg_t;
+
+/** Type of lp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** lp_cpu_sleep_reject_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_sleep_reject_int_raw:1;
+        /** pmu_0p1a_cnt_target0_reach_0_lp_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  reg_0p1a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_raw:1;
+        /** pmu_0p1a_cnt_target1_reach_0_lp_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_raw:1;
+        /** pmu_0p1a_cnt_target0_reach_1_lp_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  reg_0p1a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_raw:1;
+        /** pmu_0p1a_cnt_target1_reach_1_lp_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_raw:1;
+        /** pmu_0p2a_cnt_target0_reach_0_lp_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_raw:1;
+        /** pmu_0p2a_cnt_target1_reach_0_lp_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_raw:1;
+        /** pmu_0p2a_cnt_target0_reach_1_lp_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_raw:1;
+        /** pmu_0p2a_cnt_target1_reach_1_lp_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_raw:1;
+        /** pmu_0p3a_cnt_target0_reach_0_lp_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  reg_0p3a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_raw:1;
+        /** pmu_0p3a_cnt_target1_reach_0_lp_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_raw:1;
+        /** pmu_0p3a_cnt_target0_reach_1_lp_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  reg_0p3a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_raw:1;
+        /** pmu_0p3a_cnt_target1_reach_1_lp_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_raw:1;
+        /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_wakeup_int_raw:1;
+        /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_switch_active_end_int_raw:1;
+        /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t active_switch_sleep_end_int_raw:1;
+        /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_switch_active_start_int_raw:1;
+        /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t active_switch_sleep_start_int_raw:1;
+        /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sw_trigger_int_raw:1;
+    };
+    uint32_t val;
+} pmu_lp_int_raw_reg_t;
+
+/** Type of lp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** lp_cpu_sleep_reject_int_st : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_sleep_reject_int_st:1;
+        /** pmu_0p1a_cnt_target0_reach_0_lp_int_st : RO; bitpos: [14]; default: 0;
+         *  reg_0p1a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_st:1;
+        /** pmu_0p1a_cnt_target1_reach_0_lp_int_st : RO; bitpos: [15]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_st:1;
+        /** pmu_0p1a_cnt_target0_reach_1_lp_int_st : RO; bitpos: [16]; default: 0;
+         *  reg_0p1a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_st:1;
+        /** pmu_0p1a_cnt_target1_reach_1_lp_int_st : RO; bitpos: [17]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_st:1;
+        /** pmu_0p2a_cnt_target0_reach_0_lp_int_st : RO; bitpos: [18]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_st:1;
+        /** pmu_0p2a_cnt_target1_reach_0_lp_int_st : RO; bitpos: [19]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_st:1;
+        /** pmu_0p2a_cnt_target0_reach_1_lp_int_st : RO; bitpos: [20]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_st:1;
+        /** pmu_0p2a_cnt_target1_reach_1_lp_int_st : RO; bitpos: [21]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_st:1;
+        /** pmu_0p3a_cnt_target0_reach_0_lp_int_st : RO; bitpos: [22]; default: 0;
+         *  reg_0p3a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_st:1;
+        /** pmu_0p3a_cnt_target1_reach_0_lp_int_st : RO; bitpos: [23]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_st:1;
+        /** pmu_0p3a_cnt_target0_reach_1_lp_int_st : RO; bitpos: [24]; default: 0;
+         *  reg_0p3a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_st:1;
+        /** pmu_0p3a_cnt_target1_reach_1_lp_int_st : RO; bitpos: [25]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_st:1;
+        /** lp_cpu_wakeup_int_st : RO; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_wakeup_int_st:1;
+        /** sleep_switch_active_end_int_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_switch_active_end_int_st:1;
+        /** active_switch_sleep_end_int_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t active_switch_sleep_end_int_st:1;
+        /** sleep_switch_active_start_int_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_switch_active_start_int_st:1;
+        /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t active_switch_sleep_start_int_st:1;
+        /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sw_trigger_int_st:1;
+    };
+    uint32_t val;
+} pmu_lp_int_st_reg_t;
+
+/** Type of lp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** lp_cpu_sleep_reject_int_ena : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_sleep_reject_int_ena:1;
+        /** pmu_0p1a_cnt_target0_reach_0_lp_int_ena : R/W; bitpos: [14]; default: 0;
+         *  reg_0p1a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_ena:1;
+        /** pmu_0p1a_cnt_target1_reach_0_lp_int_ena : R/W; bitpos: [15]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_ena:1;
+        /** pmu_0p1a_cnt_target0_reach_1_lp_int_ena : R/W; bitpos: [16]; default: 0;
+         *  reg_0p1a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_ena:1;
+        /** pmu_0p1a_cnt_target1_reach_1_lp_int_ena : R/W; bitpos: [17]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_ena:1;
+        /** pmu_0p2a_cnt_target0_reach_0_lp_int_ena : R/W; bitpos: [18]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_ena:1;
+        /** pmu_0p2a_cnt_target1_reach_0_lp_int_ena : R/W; bitpos: [19]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_ena:1;
+        /** pmu_0p2a_cnt_target0_reach_1_lp_int_ena : R/W; bitpos: [20]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_ena:1;
+        /** pmu_0p2a_cnt_target1_reach_1_lp_int_ena : R/W; bitpos: [21]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_ena:1;
+        /** pmu_0p3a_cnt_target0_reach_0_lp_int_ena : R/W; bitpos: [22]; default: 0;
+         *  reg_0p3a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_ena:1;
+        /** pmu_0p3a_cnt_target1_reach_0_lp_int_ena : R/W; bitpos: [23]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_ena:1;
+        /** pmu_0p3a_cnt_target0_reach_1_lp_int_ena : R/W; bitpos: [24]; default: 0;
+         *  reg_0p3a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_ena:1;
+        /** pmu_0p3a_cnt_target1_reach_1_lp_int_ena : R/W; bitpos: [25]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_ena:1;
+        /** lp_cpu_wakeup_int_ena : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_wakeup_int_ena:1;
+        /** sleep_switch_active_end_int_ena : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_switch_active_end_int_ena:1;
+        /** active_switch_sleep_end_int_ena : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t active_switch_sleep_end_int_ena:1;
+        /** sleep_switch_active_start_int_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_switch_active_start_int_ena:1;
+        /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t active_switch_sleep_start_int_ena:1;
+        /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sw_trigger_int_ena:1;
+    };
+    uint32_t val;
+} pmu_lp_int_ena_reg_t;
+
+/** Type of lp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** lp_cpu_sleep_reject_lp_int_clr : WT; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_sleep_reject_lp_int_clr:1;
+        /** pmu_0p1a_cnt_target0_reach_0_lp_int_clr : WT; bitpos: [14]; default: 0;
+         *  reg_0p1a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_clr:1;
+        /** pmu_0p1a_cnt_target1_reach_0_lp_int_clr : WT; bitpos: [15]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_clr:1;
+        /** pmu_0p1a_cnt_target0_reach_1_lp_int_clr : WT; bitpos: [16]; default: 0;
+         *  reg_0p1a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_clr:1;
+        /** pmu_0p1a_cnt_target1_reach_1_lp_int_clr : WT; bitpos: [17]; default: 0;
+         *  reg_0p1a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_clr:1;
+        /** pmu_0p2a_cnt_target0_reach_0_lp_int_clr : WT; bitpos: [18]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_clr:1;
+        /** pmu_0p2a_cnt_target1_reach_0_lp_int_clr : WT; bitpos: [19]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_clr:1;
+        /** pmu_0p2a_cnt_target0_reach_1_lp_int_clr : WT; bitpos: [20]; default: 0;
+         *  reg_0p2a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_clr:1;
+        /** pmu_0p2a_cnt_target1_reach_1_lp_int_clr : WT; bitpos: [21]; default: 0;
+         *  reg_0p2a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_clr:1;
+        /** pmu_0p3a_cnt_target0_reach_0_lp_int_clr : WT; bitpos: [22]; default: 0;
+         *  reg_0p3a_0 counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_clr:1;
+        /** pmu_0p3a_cnt_target1_reach_0_lp_int_clr : WT; bitpos: [23]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_clr:1;
+        /** pmu_0p3a_cnt_target0_reach_1_lp_int_clr : WT; bitpos: [24]; default: 0;
+         *  reg_0p3a_0_counter after xpd reach target0
+         */
+        uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_clr:1;
+        /** pmu_0p3a_cnt_target1_reach_1_lp_int_clr : WT; bitpos: [25]; default: 0;
+         *  reg_0p3a_1_counter after xpd reach target1
+         */
+        uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_clr:1;
+        /** lp_cpu_wakeup_int_clr : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_wakeup_int_clr:1;
+        /** sleep_switch_active_end_int_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_switch_active_end_int_clr:1;
+        /** active_switch_sleep_end_int_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t active_switch_sleep_end_int_clr:1;
+        /** sleep_switch_active_start_int_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t sleep_switch_active_start_int_clr:1;
+        /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t active_switch_sleep_start_int_clr:1;
+        /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_sw_trigger_int_clr:1;
+    };
+    uint32_t val;
+} pmu_lp_int_clr_reg_t;
+
+/** Type of lp_cpu_pwr0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_waiti_rdy:1;
+        /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_stall_rdy:1;
+        uint32_t reserved_2:16;
+        /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_force_stall:1;
+        /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_slp_waiti_flag_en:1;
+        /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_cpu_slp_stall_flag_en:1;
+        /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255;
+         *  need_des
+         */
+        uint32_t lp_cpu_slp_stall_wait:8;
+        /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_slp_stall_en:1;
+        /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_slp_reset_en:1;
+        /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_slp_bypass_intr_en:1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr0_reg_t;
+
+/** Type of lp_cpu_pwr1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_sleep_req:1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr1_reg_t;
+
+/** Type of lp_cpu_pwr2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_wakeup_en : R/W; bitpos: [30:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_wakeup_en:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr2_reg_t;
+
+/** Type of lp_cpu_pwr3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_wakeup_cause : RO; bitpos: [30:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_wakeup_cause:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr3_reg_t;
+
+/** Type of lp_cpu_pwr4 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_reject_en : R/W; bitpos: [30:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_reject_en:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr4_reg_t;
+
+/** Type of lp_cpu_pwr5 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_cpu_reject_cause : RO; bitpos: [30:0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_cpu_reject_cause:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr5_reg_t;
+
+/** Type of hp_lp_cpu_comm register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** lp_trigger_hp : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_trigger_hp:1;
+        /** hp_trigger_lp : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_trigger_lp:1;
+    };
+    uint32_t val;
+} pmu_hp_lp_cpu_comm_reg_t;
+
+/** Type of hp_regulator_cfg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t dig_regulator_en_cal:1;
+    };
+    uint32_t val;
+} pmu_hp_regulator_cfg_reg_t;
+
+/** Type of main_state register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** enable_cali_pmu_cntl : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t enable_cali_pmu_cntl:1;
+        uint32_t reserved_1:10;
+        /** pmu_main_last_st_state : RO; bitpos: [17:11]; default: 1;
+         *  need_des
+         */
+        uint32_t pmu_main_last_st_state:7;
+        /** pmu_main_tar_st_state : RO; bitpos: [24:18]; default: 4;
+         *  need_des
+         */
+        uint32_t pmu_main_tar_st_state:7;
+        /** pmu_main_cur_st_state : RO; bitpos: [31:25]; default: 1;
+         *  need_des
+         */
+        uint32_t pmu_main_cur_st_state:7;
+    };
+    uint32_t val;
+} pmu_main_state_reg_t;
+
+/** Type of pwr_state register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** pmu_backup_st_state : RO; bitpos: [17:13]; default: 1;
+         *  need_des
+         */
+        uint32_t pmu_backup_st_state:5;
+        /** pmu_lp_pwr_st_state : RO; bitpos: [22:18]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_lp_pwr_st_state:5;
+        /** pmu_hp_pwr_st_state : RO; bitpos: [31:23]; default: 1;
+         *  need_des
+         */
+        uint32_t pmu_hp_pwr_st_state:9;
+    };
+    uint32_t val;
+} pmu_pwr_state_reg_t;
+
+/** Type of ext_ldo_p0_0p1a register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** pmu_0p1a_cnt_clr_0 : WT; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_cnt_clr_0:1;
+        /** pmu_0p1a_force_tieh_sel_0 : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_force_tieh_sel_0:1;
+        /** pmu_0p1a_xpd_0 : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_xpd_0:1;
+        /** pmu_0p1a_tieh_sel_0 : R/W; bitpos: [11:9]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_tieh_sel_0:3;
+        /** pmu_0p1a_tieh_pos_en_0 : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_tieh_pos_en_0:1;
+        /** pmu_0p1a_tieh_neg_en_0 : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_tieh_neg_en_0:1;
+        /** pmu_0p1a_tieh_0 : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_tieh_0:1;
+        /** pmu_0p1a_target1_0 : R/W; bitpos: [22:15]; default: 64;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_target1_0:8;
+        /** pmu_0p1a_target0_0 : R/W; bitpos: [30:23]; default: 128;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_target0_0:8;
+        /** pmu_0p1a_ldo_cnt_prescaler_sel_0 : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_ldo_cnt_prescaler_sel_0:1;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p0_0p1a_reg_t;
+
+/** Type of ext_ldo_p0_0p1a_ana register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** ana_0p1a_mul_0 : R/W; bitpos: [25:23]; default: 2;
+         *  need_des
+         */
+        uint32_t ana_0p1a_mul_0:3;
+        /** ana_0p1a_en_vdet_0 : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p1a_en_vdet_0:1;
+        /** ana_0p1a_en_cur_lim_0 : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p1a_en_cur_lim_0:1;
+        /** ana_0p1a_dref_0 : R/W; bitpos: [31:28]; default: 11;
+         *  need_des
+         */
+        uint32_t ana_0p1a_dref_0:4;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p0_0p1a_ana_reg_t;
+
+/** Type of ext_ldo_p0_0p2a register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** pmu_0p2a_cnt_clr_0 : WT; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_cnt_clr_0:1;
+        /** 0p2a_force_tieh_sel_0 : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_force_tieh_sel_0:1;
+        /** pmu_0p2a_xpd_0 : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_xpd_0:1;
+        /** pmu_0p2a_tieh_sel_0 : R/W; bitpos: [11:9]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_tieh_sel_0:3;
+        /** pmu_0p2a_tieh_pos_en_0 : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_tieh_pos_en_0:1;
+        /** pmu_0p2a_tieh_neg_en_0 : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_tieh_neg_en_0:1;
+        /** pmu_0p2a_tieh_0 : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_tieh_0:1;
+        /** pmu_0p2a_target1_0 : R/W; bitpos: [22:15]; default: 64;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_target1_0:8;
+        /** pmu_0p2a_target0_0 : R/W; bitpos: [30:23]; default: 128;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_target0_0:8;
+        /** pmu_0p2a_ldo_cnt_prescaler_sel_0 : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_ldo_cnt_prescaler_sel_0:1;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p0_0p2a_reg_t;
+
+/** Type of ext_ldo_p0_0p2a_ana register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** ana_0p2a_mul_0 : R/W; bitpos: [25:23]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p2a_mul_0:3;
+        /** ana_0p2a_en_vdet_0 : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p2a_en_vdet_0:1;
+        /** ana_0p2a_en_cur_lim_0 : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p2a_en_cur_lim_0:1;
+        /** ana_0p2a_dref_0 : R/W; bitpos: [31:28]; default: 10;
+         *  need_des
+         */
+        uint32_t ana_0p2a_dref_0:4;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p0_0p2a_ana_reg_t;
+
+/** Type of ext_ldo_p0_0p3a register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** pmu_0p3a_cnt_clr_0 : WT; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_cnt_clr_0:1;
+        /** pmu_0p3a_force_tieh_sel_0 : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_force_tieh_sel_0:1;
+        /** pmu_0p3a_xpd_0 : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_xpd_0:1;
+        /** pmu_0p3a_tieh_sel_0 : R/W; bitpos: [11:9]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_tieh_sel_0:3;
+        /** pmu_0p3a_tieh_pos_en_0 : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_tieh_pos_en_0:1;
+        /** pmu_0p3a_tieh_neg_en_0 : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_tieh_neg_en_0:1;
+        /** pmu_0p3a_tieh_0 : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_tieh_0:1;
+        /** pmu_0p3a_target1_0 : R/W; bitpos: [22:15]; default: 64;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_target1_0:8;
+        /** pmu_0p3a_target0_0 : R/W; bitpos: [30:23]; default: 128;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_target0_0:8;
+        /** pmu_0p3a_ldo_cnt_prescaler_sel_0 : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_ldo_cnt_prescaler_sel_0:1;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p0_0p3a_reg_t;
+
+/** Type of ext_ldo_p0_0p3a_ana register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** ana_0p3a_mul_0 : R/W; bitpos: [25:23]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p3a_mul_0:3;
+        /** ana_0p3a_en_vdet_0 : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p3a_en_vdet_0:1;
+        /** ana_0p3a_en_cur_lim_0 : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p3a_en_cur_lim_0:1;
+        /** ana_0p3a_dref_0 : R/W; bitpos: [31:28]; default: 10;
+         *  need_des
+         */
+        uint32_t ana_0p3a_dref_0:4;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p0_0p3a_ana_reg_t;
+
+/** Type of ext_ldo_p1_0p1a register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** pmu_0p1a_cnt_clr_1 : WT; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_cnt_clr_1:1;
+        /** pmu_0p1a_force_tieh_sel_1 : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_force_tieh_sel_1:1;
+        /** pmu_0p1a_xpd_1 : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_xpd_1:1;
+        /** pmu_0p1a_tieh_sel_1 : R/W; bitpos: [11:9]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_tieh_sel_1:3;
+        /** pmu_0p1a_tieh_pos_en_1 : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_tieh_pos_en_1:1;
+        /** pmu_0p1a_tieh_neg_en_1 : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_tieh_neg_en_1:1;
+        /** pmu_0p1a_tieh_1 : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_tieh_1:1;
+        /** pmu_0p1a_target1_1 : R/W; bitpos: [22:15]; default: 64;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_target1_1:8;
+        /** pmu_0p1a_target0_1 : R/W; bitpos: [30:23]; default: 128;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_target0_1:8;
+        /** pmu_0p1a_ldo_cnt_prescaler_sel_1 : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p1a_ldo_cnt_prescaler_sel_1:1;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p1_0p1a_reg_t;
+
+/** Type of ext_ldo_p1_0p1a_ana register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** ana_0p1a_mul_1 : R/W; bitpos: [25:23]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p1a_mul_1:3;
+        /** ana_0p1a_en_vdet_1 : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p1a_en_vdet_1:1;
+        /** ana_0p1a_en_cur_lim_1 : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p1a_en_cur_lim_1:1;
+        /** ana_0p1a_dref_1 : R/W; bitpos: [31:28]; default: 10;
+         *  need_des
+         */
+        uint32_t ana_0p1a_dref_1:4;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p1_0p1a_ana_reg_t;
+
+/** Type of ext_ldo_p1_0p2a register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** pmu_0p2a_cnt_clr_1 : WT; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_cnt_clr_1:1;
+        /** pmu_0p2a_force_tieh_sel_1 : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_force_tieh_sel_1:1;
+        /** pmu_0p2a_xpd_1 : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_xpd_1:1;
+        /** pmu_0p2a_tieh_sel_1 : R/W; bitpos: [11:9]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_tieh_sel_1:3;
+        /** pmu_0p2a_tieh_pos_en_1 : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_tieh_pos_en_1:1;
+        /** pmu_0p2a_tieh_neg_en_1 : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_tieh_neg_en_1:1;
+        /** pmu_0p2a_tieh_1 : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_tieh_1:1;
+        /** pmu_0p2a_target1_1 : R/W; bitpos: [22:15]; default: 64;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_target1_1:8;
+        /** pmu_0p2a_target0_1 : R/W; bitpos: [30:23]; default: 128;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_target0_1:8;
+        /** pmu_0p2a_ldo_cnt_prescaler_sel_1 : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p2a_ldo_cnt_prescaler_sel_1:1;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p1_0p2a_reg_t;
+
+/** Type of ext_ldo_p1_0p2a_ana register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** ana_0p2a_mul_1 : R/W; bitpos: [25:23]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p2a_mul_1:3;
+        /** ana_0p2a_en_vdet_1 : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p2a_en_vdet_1:1;
+        /** ana_0p2a_en_cur_lim_1 : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p2a_en_cur_lim_1:1;
+        /** ana_0p2a_dref_1 : R/W; bitpos: [31:28]; default: 10;
+         *  need_des
+         */
+        uint32_t ana_0p2a_dref_1:4;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p1_0p2a_ana_reg_t;
+
+/** Type of ext_ldo_p1_0p3a register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** pmu_0p3a_cnt_clr_1 : WT; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_cnt_clr_1:1;
+        /** pmu_0p3a_force_tieh_sel_1 : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_force_tieh_sel_1:1;
+        /** pmu_0p3a_xpd_1 : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_xpd_1:1;
+        /** pmu_0p3a_tieh_sel_1 : R/W; bitpos: [11:9]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_tieh_sel_1:3;
+        /** pmu_0p3a_tieh_pos_en_1 : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_tieh_pos_en_1:1;
+        /** pmu_0p3a_tieh_neg_en_1 : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_tieh_neg_en_1:1;
+        /** pmu_0p3a_tieh_1 : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_tieh_1:1;
+        /** pmu_0p3a_target1_1 : R/W; bitpos: [22:15]; default: 64;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_target1_1:8;
+        /** pmu_0p3a_target0_1 : R/W; bitpos: [30:23]; default: 128;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_target0_1:8;
+        /** pmu_0p3a_ldo_cnt_prescaler_sel_1 : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_0p3a_ldo_cnt_prescaler_sel_1:1;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p1_0p3a_reg_t;
+
+/** Type of ext_ldo_p1_0p3a_ana register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** ana_0p3a_mul_1 : R/W; bitpos: [25:23]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p3a_mul_1:3;
+        /** ana_0p3a_en_vdet_1 : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p3a_en_vdet_1:1;
+        /** ana_0p3a_en_cur_lim_1 : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_0p3a_en_cur_lim_1:1;
+        /** ana_0p3a_dref_1 : R/W; bitpos: [31:28]; default: 10;
+         *  need_des
+         */
+        uint32_t ana_0p3a_dref_1:4;
+    };
+    uint32_t val;
+} pmu_ext_ldo_p1_0p3a_ana_reg_t;
+
+/** Type of ext_wakeup_lv register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ext_wakeup_lv : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t ext_wakeup_lv:32;
+    };
+    uint32_t val;
+} pmu_ext_wakeup_lv_reg_t;
+
+/** Type of ext_wakeup_sel register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ext_wakeup_sel : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t ext_wakeup_sel:32;
+    };
+    uint32_t val;
+} pmu_ext_wakeup_sel_reg_t;
+
+/** Type of ext_wakeup_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ext_wakeup_status : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t ext_wakeup_status:32;
+    };
+    uint32_t val;
+} pmu_ext_wakeup_st_reg_t;
+
+/** Type of ext_wakeup_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** ext_wakeup_status_clr : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t ext_wakeup_status_clr:1;
+        /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t ext_wakeup_filter:1;
+    };
+    uint32_t val;
+} pmu_ext_wakeup_cntl_reg_t;
+
+/** Type of sdio_wakeup_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sdio_act_dnum : R/W; bitpos: [9:0]; default: 1023;
+         *  need_des
+         */
+        uint32_t sdio_act_dnum:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} pmu_sdio_wakeup_cntl_reg_t;
+
+/** Type of cpu_sw_stall register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** hpcore1_sw_stall_code : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_sw_stall_code:8;
+        /** hpcore0_sw_stall_code : R/W; bitpos: [31:24]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_sw_stall_code:8;
+    };
+    uint32_t val;
+} pmu_cpu_sw_stall_reg_t;
+
+/** Type of dcm_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dcdc_on_req : WT; bitpos: [0]; default: 0;
+         *  SW trigger dcdc on
+         */
+        uint32_t dcdc_on_req:1;
+        /** dcdc_off_req : WT; bitpos: [1]; default: 0;
+         *  SW trigger dcdc off
+         */
+        uint32_t dcdc_off_req:1;
+        /** dcdc_lightslp_req : WT; bitpos: [2]; default: 0;
+         *  SW trigger dcdc enter lightsleep
+         */
+        uint32_t dcdc_lightslp_req:1;
+        /** dcdc_deepslp_req : WT; bitpos: [3]; default: 0;
+         *  SW trigger dcdc enter deepsleep
+         */
+        uint32_t dcdc_deepslp_req:1;
+        uint32_t reserved_4:3;
+        /** dcdc_done_force : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t dcdc_done_force:1;
+        /** dcdc_on_force_pu : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t dcdc_on_force_pu:1;
+        /** dcdc_on_force_pd : R/W; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t dcdc_on_force_pd:1;
+        /** dcdc_fb_res_force_pu : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t dcdc_fb_res_force_pu:1;
+        /** dcdc_fb_res_force_pd : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t dcdc_fb_res_force_pd:1;
+        /** dcdc_ls_force_pu : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t dcdc_ls_force_pu:1;
+        /** dcdc_ls_force_pd : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t dcdc_ls_force_pd:1;
+        /** dcdc_ds_force_pu : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t dcdc_ds_force_pu:1;
+        /** dcdc_ds_force_pd : R/W; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t dcdc_ds_force_pd:1;
+        /** dcm_cur_st : RO; bitpos: [23:16]; default: 1;
+         *  need_des
+         */
+        uint32_t dcm_cur_st:8;
+        uint32_t reserved_24:5;
+        /** dcdc_en_amux_test : R/W; bitpos: [29]; default: 0;
+         *  Enable analog mux to pull PAD TEST_DCDC voltage signal
+         */
+        uint32_t dcdc_en_amux_test:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} pmu_dcm_ctrl_reg_t;
+
+/** Type of dcm_wait_delay register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dcdc_pre_delay : R/W; bitpos: [7:0]; default: 5;
+         *  DCDC pre-on/post off delay
+         */
+        uint32_t dcdc_pre_delay:8;
+        /** dcdc_res_off_delay : R/W; bitpos: [15:8]; default: 2;
+         *  DCDC fb res off delay
+         */
+        uint32_t dcdc_res_off_delay:8;
+        /** dcdc_stable_delay : R/W; bitpos: [25:16]; default: 75;
+         *  DCDC stable delay
+         */
+        uint32_t dcdc_stable_delay:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} pmu_dcm_wait_delay_reg_t;
+
+/** Type of vddbat_cfg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ana_vddbat_mode : RO; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_vddbat_mode:2;
+        uint32_t reserved_2:29;
+        /** vddbat_sw_update : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_sw_update:1;
+    };
+    uint32_t val;
+} pmu_vddbat_cfg_reg_t;
+
+/** Type of touch_pwr_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** touch_wait_cycles : R/W; bitpos: [13:5]; default: 10;
+         *  need_des
+         */
+        uint32_t touch_wait_cycles:9;
+        /** touch_sleep_cycles : R/W; bitpos: [29:14]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_sleep_cycles:16;
+        /** touch_force_done : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_force_done:1;
+        /** touch_sleep_timer_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_sleep_timer_en:1;
+    };
+    uint32_t val;
+} pmu_touch_pwr_cntl_reg_t;
+
+/** Type of rdn_eco register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pmu_rdn_eco_result : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_rdn_eco_result:1;
+        uint32_t reserved_1:30;
+        /** pmu_rdn_eco_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_rdn_eco_en:1;
+    };
+    uint32_t val;
+} pmu_rdn_eco_reg_t;
+
+/** Type of power_pd_hp_cpu_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t force_hp_cpu_reset:1;
+        /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t force_hp_cpu_iso:1;
+        /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t force_hp_cpu_pu:1;
+        /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t force_hp_cpu_no_reset:1;
+        /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t force_hp_cpu_no_iso:1;
+        /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t force_hp_cpu_pd:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} pmu_power_pd_hp_cpu_cntl_reg_t;
+
+/** Type of power_pd_hp_cpu_mask register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** xpd_hp_cpu_mask : R/W; bitpos: [4:0]; default: 0;
+         *  need_des
+         */
+        uint32_t xpd_hp_cpu_mask:5;
+        uint32_t reserved_5:22;
+        /** pd_hp_cpu_mask : R/W; bitpos: [31:27]; default: 0;
+         *  need_des
+         */
+        uint32_t pd_hp_cpu_mask:5;
+    };
+    uint32_t val;
+} pmu_power_pd_hp_cpu_mask_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pmu_date : R/W; bitpos: [30:0]; default: 38801456;
+         *  need_des
+         */
+        uint32_t pmu_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} pmu_date_reg_t;
+
+
+/** Group: status_register */
+/** Type of clk_state0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** stable_xpd_pll_state : RO; bitpos: [2:0]; default: 0;
+         *  need_des
+         */
+        uint32_t stable_xpd_pll_state:3;
+        /** stable_xpd_xtal_state : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t stable_xpd_xtal_state:1;
+        /** pmu_ana_xpd_pll_i2c_state : RO; bitpos: [6:4]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_ana_xpd_pll_i2c_state:3;
+        uint32_t reserved_7:3;
+        /** pmu_sys_clk_slp_sel_state : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_sys_clk_slp_sel_state:1;
+        /** pmu_sys_clk_sel_state : RO; bitpos: [12:11]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_sys_clk_sel_state:2;
+        /** pmu_sys_clk_no_div_state : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_sys_clk_no_div_state:1;
+        /** pmu_icg_sys_clk_en_state : RO; bitpos: [14]; default: 1;
+         *  need_des
+         */
+        uint32_t pmu_icg_sys_clk_en_state:1;
+        /** pmu_icg_modem_switch_state : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_icg_modem_switch_state:1;
+        /** pmu_icg_modem_code_state : RO; bitpos: [17:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_icg_modem_code_state:2;
+        /** pmu_icg_slp_sel_state : RO; bitpos: [18]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_icg_slp_sel_state:1;
+        /** pmu_icg_global_xtal_state : RO; bitpos: [19]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_icg_global_xtal_state:1;
+        /** pmu_icg_global_pll_state : RO; bitpos: [23:20]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_icg_global_pll_state:4;
+        /** pmu_ana_i2c_iso_en_state : RO; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_ana_i2c_iso_en_state:1;
+        /** pmu_ana_i2c_retention_state : RO; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_ana_i2c_retention_state:1;
+        uint32_t reserved_26:1;
+        /** pmu_ana_xpd_pll_state : RO; bitpos: [30:27]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_ana_xpd_pll_state:4;
+        /** pmu_ana_xpd_xtal_state : RO; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t pmu_ana_xpd_xtal_state:1;
+    };
+    uint32_t val;
+} pmu_clk_state0_reg_t;
+
+/** Type of clk_state1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pmu_icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t pmu_icg_func_en_state:32;
+    };
+    uint32_t val;
+} pmu_clk_state1_reg_t;
+
+/** Type of clk_state2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pmu_icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t pmu_icg_apb_en_state:32;
+    };
+    uint32_t val;
+} pmu_clk_state2_reg_t;
+
+/** Type of xtal_slp register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** xtal_slp_cnt_target : R/W; bitpos: [31:16]; default: 15;
+         *  need_des
+         */
+        uint32_t xtal_slp_cnt_target:16;
+    };
+    uint32_t val;
+} pmu_xtal_slp_reg_t;
+
+
+typedef struct {
+    volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power;
+    volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func;
+    volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb;
+    volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem;
+    volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl;
+    volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power;
+    volatile pmu_hp_active_bias_reg_t hp_active_bias;
+    volatile pmu_hp_active_backup_reg_t hp_active_backup;
+    volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk;
+    volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk;
+    volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0;
+    volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1;
+    volatile pmu_hp_active_xtal_reg_t hp_active_xtal;
+    volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power;
+    volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func;
+    volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb;
+    volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem;
+    volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl;
+    volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power;
+    volatile pmu_hp_modem_bias_reg_t hp_modem_bias;
+    volatile pmu_hp_modem_backup_reg_t hp_modem_backup;
+    volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk;
+    volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk;
+    volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0;
+    volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1;
+    volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal;
+    volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power;
+    volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func;
+    volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb;
+    volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem;
+    volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl;
+    volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power;
+    volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias;
+    volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup;
+    volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk;
+    volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk;
+    volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0;
+    volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1;
+    volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal;
+    volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0;
+    volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1;
+    uint32_t reserved_0a4;
+    volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power;
+    volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power;
+    uint32_t reserved_0b0;
+    volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0;
+    volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1;
+    volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal;
+    volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power;
+    volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power;
+    volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias;
+    volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power;
+    volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk;
+    volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg;
+    volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg;
+    volatile pmu_imm_modem_icg_reg_t imm_modem_icg;
+    volatile pmu_imm_lp_icg_reg_t imm_lp_icg;
+    volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all;
+    volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso;
+    volatile pmu_power_wait_timer0_reg_t power_wait_timer0;
+    volatile pmu_power_wait_timer1_reg_t power_wait_timer1;
+    volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl;
+    volatile pmu_power_pd_cnnt_cntl_reg_t power_pd_cnnt_cntl;
+    volatile pmu_power_pd_hpmem_cntl_reg_t power_pd_hpmem_cntl;
+    volatile pmu_power_pd_top_mask_reg_t power_pd_top_mask;
+    volatile pmu_power_pd_cnnt_mask_reg_t power_pd_cnnt_mask;
+    volatile pmu_power_pd_hpmem_mask_reg_t power_pd_hpmem_mask;
+    volatile pmu_power_dcdc_switch_reg_t power_dcdc_switch;
+    volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl;
+    volatile pmu_power_pd_lpperi_mask_reg_t power_pd_lpperi_mask;
+    volatile pmu_power_hp_pad_reg_t power_hp_pad;
+    volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl;
+    volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0;
+    volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1;
+    volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2;
+    volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3;
+    volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4;
+    volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5;
+    volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6;
+    volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7;
+    volatile pmu_slp_wakeup_cntl8_reg_t slp_wakeup_cntl8;
+    volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0;
+    volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1;
+    volatile pmu_slp_wakeup_status2_reg_t slp_wakeup_status2;
+    volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron;
+    volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl;
+    volatile pmu_por_status_reg_t por_status;
+    volatile pmu_rf_pwc_reg_t rf_pwc;
+    volatile pmu_backup_cfg_reg_t backup_cfg;
+    volatile pmu_int_raw_reg_t int_raw;
+    volatile pmu_hp_int_st_reg_t hp_int_st;
+    volatile pmu_hp_int_ena_reg_t hp_int_ena;
+    volatile pmu_hp_int_clr_reg_t hp_int_clr;
+    volatile pmu_lp_int_raw_reg_t lp_int_raw;
+    volatile pmu_lp_int_st_reg_t lp_int_st;
+    volatile pmu_lp_int_ena_reg_t lp_int_ena;
+    volatile pmu_lp_int_clr_reg_t lp_int_clr;
+    volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0;
+    volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1;
+    volatile pmu_lp_cpu_pwr2_reg_t lp_cpu_pwr2;
+    volatile pmu_lp_cpu_pwr3_reg_t lp_cpu_pwr3;
+    volatile pmu_lp_cpu_pwr4_reg_t lp_cpu_pwr4;
+    volatile pmu_lp_cpu_pwr5_reg_t lp_cpu_pwr5;
+    volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm;
+    volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg;
+    volatile pmu_main_state_reg_t main_state;
+    volatile pmu_pwr_state_reg_t pwr_state;
+    volatile pmu_clk_state0_reg_t clk_state0;
+    volatile pmu_clk_state1_reg_t clk_state1;
+    volatile pmu_clk_state2_reg_t clk_state2;
+    volatile pmu_ext_ldo_p0_0p1a_reg_t ext_ldo_p0_0p1a;
+    volatile pmu_ext_ldo_p0_0p1a_ana_reg_t ext_ldo_p0_0p1a_ana;
+    volatile pmu_ext_ldo_p0_0p2a_reg_t ext_ldo_p0_0p2a;
+    volatile pmu_ext_ldo_p0_0p2a_ana_reg_t ext_ldo_p0_0p2a_ana;
+    volatile pmu_ext_ldo_p0_0p3a_reg_t ext_ldo_p0_0p3a;
+    volatile pmu_ext_ldo_p0_0p3a_ana_reg_t ext_ldo_p0_0p3a_ana;
+    volatile pmu_ext_ldo_p1_0p1a_reg_t ext_ldo_p1_0p1a;
+    volatile pmu_ext_ldo_p1_0p1a_ana_reg_t ext_ldo_p1_0p1a_ana;
+    volatile pmu_ext_ldo_p1_0p2a_reg_t ext_ldo_p1_0p2a;
+    volatile pmu_ext_ldo_p1_0p2a_ana_reg_t ext_ldo_p1_0p2a_ana;
+    volatile pmu_ext_ldo_p1_0p3a_reg_t ext_ldo_p1_0p3a;
+    volatile pmu_ext_ldo_p1_0p3a_ana_reg_t ext_ldo_p1_0p3a_ana;
+    volatile pmu_ext_wakeup_lv_reg_t ext_wakeup_lv;
+    volatile pmu_ext_wakeup_sel_reg_t ext_wakeup_sel;
+    volatile pmu_ext_wakeup_st_reg_t ext_wakeup_st;
+    volatile pmu_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
+    volatile pmu_sdio_wakeup_cntl_reg_t sdio_wakeup_cntl;
+    volatile pmu_xtal_slp_reg_t xtal_slp;
+    volatile pmu_cpu_sw_stall_reg_t cpu_sw_stall;
+    volatile pmu_dcm_ctrl_reg_t dcm_ctrl;
+    volatile pmu_dcm_wait_delay_reg_t dcm_wait_delay;
+    volatile pmu_vddbat_cfg_reg_t vddbat_cfg;
+    volatile pmu_touch_pwr_cntl_reg_t touch_pwr_cntl;
+    volatile pmu_rdn_eco_reg_t rdn_eco;
+    volatile pmu_power_pd_hp_cpu_cntl_reg_t power_pd_hp_cpu_cntl;
+    volatile pmu_power_pd_hp_cpu_mask_reg_t power_pd_hp_cpu_mask;
+    uint32_t reserved_220[119];
+    volatile pmu_date_reg_t date;
+} pmu_dev_t;
+
+extern pmu_dev_t PMU;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pmu_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/pmu_reg.h
new file mode 100644
index 0000000000..bb17970949
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pmu_reg.h
@@ -0,0 +1,4967 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13420
+
+/** PMU_HP_ACTIVE_DIG_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0)
+/** PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN    (BIT(21))
+#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_M  (PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_V << PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_S)
+#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_S  21
+/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_MEM_DSLP    (BIT(22))
+#define PMU_HP_ACTIVE_HP_MEM_DSLP_M  (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S)
+#define PMU_HP_ACTIVE_HP_MEM_DSLP_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_MEM_DSLP_S  22
+/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN    (BIT(23))
+#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S)
+#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S  23
+/** PMU_HP_ACTIVE_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_PD_CNNT_PD_EN    (BIT(30))
+#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_M  (PMU_HP_ACTIVE_PD_CNNT_PD_EN_V << PMU_HP_ACTIVE_PD_CNNT_PD_EN_S)
+#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_S  30
+/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_PD_TOP_PD_EN    (BIT(31))
+#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M  (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S)
+#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S  31
+
+/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4)
+/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M  (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S)
+#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S  0
+
+/** PMU_HP_ACTIVE_ICG_HP_APB_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8)
+/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_ICG_APB_EN    0xFFFFFFFFU
+#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M  (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S)
+#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V  0xFFFFFFFFU
+#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S  0
+
+/** PMU_HP_ACTIVE_ICG_MODEM_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc)
+/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE    0x00000003U
+#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M  (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S)
+#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V  0x00000003U
+#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S  30
+
+/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10)
+/** PMU_HP_ACTIVE_HP_POWER_DET_BYPASS : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS    (BIT(23))
+#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M  (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S)
+#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S  23
+/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_UART_WAKEUP_EN    (BIT(24))
+#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M  (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S)
+#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S  24
+/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL    (BIT(25))
+#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M  (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S)
+#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S  25
+/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL    (BIT(26))
+#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M  (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S)
+#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S  26
+/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL    (BIT(27))
+#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M  (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S)
+#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V  0x00000001U
+#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S  27
+/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_PAUSE_WDT    (BIT(28))
+#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M  (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S)
+#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V  0x00000001U
+#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S  28
+/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_CPU_STALL    (BIT(29))
+#define PMU_HP_ACTIVE_DIG_CPU_STALL_M  (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S)
+#define PMU_HP_ACTIVE_DIG_CPU_STALL_V  0x00000001U
+#define PMU_HP_ACTIVE_DIG_CPU_STALL_S  29
+
+/** PMU_HP_ACTIVE_HP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14)
+/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_I2C_ISO_EN    (BIT(21))
+#define PMU_HP_ACTIVE_I2C_ISO_EN_M  (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S)
+#define PMU_HP_ACTIVE_I2C_ISO_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_I2C_ISO_EN_S  21
+/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_I2C_RETENTION    (BIT(22))
+#define PMU_HP_ACTIVE_I2C_RETENTION_M  (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S)
+#define PMU_HP_ACTIVE_I2C_RETENTION_V  0x00000001U
+#define PMU_HP_ACTIVE_I2C_RETENTION_S  22
+/** PMU_HP_ACTIVE_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_XPD_PLL_I2C    0x0000000FU
+#define PMU_HP_ACTIVE_XPD_PLL_I2C_M  (PMU_HP_ACTIVE_XPD_PLL_I2C_V << PMU_HP_ACTIVE_XPD_PLL_I2C_S)
+#define PMU_HP_ACTIVE_XPD_PLL_I2C_V  0x0000000FU
+#define PMU_HP_ACTIVE_XPD_PLL_I2C_S  23
+/** PMU_HP_ACTIVE_XPD_PLL : R/W; bitpos: [30:27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_XPD_PLL    0x0000000FU
+#define PMU_HP_ACTIVE_XPD_PLL_M  (PMU_HP_ACTIVE_XPD_PLL_V << PMU_HP_ACTIVE_XPD_PLL_S)
+#define PMU_HP_ACTIVE_XPD_PLL_V  0x0000000FU
+#define PMU_HP_ACTIVE_XPD_PLL_S  27
+
+/** PMU_HP_ACTIVE_BIAS_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18)
+/** PMU_HP_ACTIVE_DCM_VSET : R/W; bitpos: [22:18]; default: 20;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DCM_VSET    0x0000001FU
+#define PMU_HP_ACTIVE_DCM_VSET_M  (PMU_HP_ACTIVE_DCM_VSET_V << PMU_HP_ACTIVE_DCM_VSET_S)
+#define PMU_HP_ACTIVE_DCM_VSET_V  0x0000001FU
+#define PMU_HP_ACTIVE_DCM_VSET_S  18
+/** PMU_HP_ACTIVE_DCM_MODE : R/W; bitpos: [24:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DCM_MODE    0x00000003U
+#define PMU_HP_ACTIVE_DCM_MODE_M  (PMU_HP_ACTIVE_DCM_MODE_V << PMU_HP_ACTIVE_DCM_MODE_S)
+#define PMU_HP_ACTIVE_DCM_MODE_V  0x00000003U
+#define PMU_HP_ACTIVE_DCM_MODE_S  23
+/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_XPD_BIAS    (BIT(25))
+#define PMU_HP_ACTIVE_XPD_BIAS_M  (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S)
+#define PMU_HP_ACTIVE_XPD_BIAS_V  0x00000001U
+#define PMU_HP_ACTIVE_XPD_BIAS_S  25
+/** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DBG_ATTEN    0x0000000FU
+#define PMU_HP_ACTIVE_DBG_ATTEN_M  (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S)
+#define PMU_HP_ACTIVE_DBG_ATTEN_V  0x0000000FU
+#define PMU_HP_ACTIVE_DBG_ATTEN_S  26
+/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_PD_CUR    (BIT(30))
+#define PMU_HP_ACTIVE_PD_CUR_M  (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S)
+#define PMU_HP_ACTIVE_PD_CUR_V  0x00000001U
+#define PMU_HP_ACTIVE_PD_CUR_S  30
+/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_BIAS_SLEEP    (BIT(31))
+#define PMU_HP_ACTIVE_BIAS_SLEEP_M  (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S)
+#define PMU_HP_ACTIVE_BIAS_SLEEP_V  0x00000001U
+#define PMU_HP_ACTIVE_BIAS_SLEEP_S  31
+
+/** PMU_HP_ACTIVE_BACKUP_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c)
+/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE    0x00000003U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S)
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V  0x00000003U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S  4
+/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE    0x00000003U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S)
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V  0x00000003U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S  6
+/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_RETENTION_MODE    (BIT(10))
+#define PMU_HP_ACTIVE_RETENTION_MODE_M  (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S)
+#define PMU_HP_ACTIVE_RETENTION_MODE_V  0x00000001U
+#define PMU_HP_ACTIVE_RETENTION_MODE_S  10
+/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN    (BIT(11))
+#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M  (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S)
+#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V  0x00000001U
+#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S  11
+/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2ACTIVE_RETENTION_EN    (BIT(12))
+#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M  (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S)
+#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V  0x00000001U
+#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S  12
+/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL    0x00000003U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S)
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V  0x00000003U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S  14
+/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL    0x00000003U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M  (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S)
+#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V  0x00000003U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S  16
+/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE    0x00000007U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S)
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V  0x00000007U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S  20
+/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE    0x00000007U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M  (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S)
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V  0x00000007U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S  23
+/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN    (BIT(29))
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S)
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V  0x00000001U
+#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S  29
+/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2ACTIVE_BACKUP_EN    (BIT(30))
+#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M  (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S)
+#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V  0x00000001U
+#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S  30
+
+/** PMU_HP_ACTIVE_BACKUP_CLK_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20)
+/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M  (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S)
+#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S  0
+
+/** PMU_HP_ACTIVE_SYSCLK_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24)
+/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV    (BIT(26))
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S)
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V  0x00000001U
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S  26
+/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN    (BIT(27))
+#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M  (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S)
+#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V  0x00000001U
+#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S  27
+/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL    (BIT(28))
+#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M  (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S)
+#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V  0x00000001U
+#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S  28
+/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_ICG_SLP_SEL    (BIT(29))
+#define PMU_HP_ACTIVE_ICG_SLP_SEL_M  (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S)
+#define PMU_HP_ACTIVE_ICG_SLP_SEL_V  0x00000001U
+#define PMU_HP_ACTIVE_ICG_SLP_SEL_S  29
+/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL    0x00000003U
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M  (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S)
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V  0x00000003U
+#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S  30
+
+/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28)
+/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24;
+ *  need_des
+ */
+#define PMU_LP_DBIAS_VOL    0x0000001FU
+#define PMU_LP_DBIAS_VOL_M  (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S)
+#define PMU_LP_DBIAS_VOL_V  0x0000001FU
+#define PMU_LP_DBIAS_VOL_S  4
+/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24;
+ *  need_des
+ */
+#define PMU_HP_DBIAS_VOL    0x0000001FU
+#define PMU_HP_DBIAS_VOL_M  (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S)
+#define PMU_HP_DBIAS_VOL_V  0x0000001FU
+#define PMU_HP_DBIAS_VOL_S  9
+/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1;
+ *  need_des
+ */
+#define PMU_DIG_REGULATOR0_DBIAS_SEL    (BIT(14))
+#define PMU_DIG_REGULATOR0_DBIAS_SEL_M  (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S)
+#define PMU_DIG_REGULATOR0_DBIAS_SEL_V  0x00000001U
+#define PMU_DIG_REGULATOR0_DBIAS_SEL_S  14
+/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define PMU_DIG_DBIAS_INIT    (BIT(15))
+#define PMU_DIG_DBIAS_INIT_M  (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S)
+#define PMU_DIG_DBIAS_INIT_V  0x00000001U
+#define PMU_DIG_DBIAS_INIT_S  15
+/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S  16
+/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S  17
+/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_XPD    (BIT(18))
+#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V  0x00000001U
+#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S  18
+/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S  19
+/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
+/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS    0x0000001FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V  0x0000001FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S  27
+
+/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c)
+/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B    0x0000003FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M  (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S)
+#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V  0x0000003FU
+#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S  26
+
+/** PMU_HP_ACTIVE_XTAL_REG register
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30)
+/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE_XPD_XTAL    (BIT(31))
+#define PMU_HP_ACTIVE_XPD_XTAL_M  (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S)
+#define PMU_HP_ACTIVE_XPD_XTAL_V  0x00000001U
+#define PMU_HP_ACTIVE_XPD_XTAL_S  31
+
+/** PMU_HP_MODEM_DIG_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34)
+/** PMU_HP_MODEM_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN    (BIT(21))
+#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_M  (PMU_HP_MODEM_DCDC_SWITCH_PD_EN_V << PMU_HP_MODEM_DCDC_SWITCH_PD_EN_S)
+#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_V  0x00000001U
+#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_S  21
+/** PMU_HP_MODEM_HP_MEM_DSLP : WT; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_MEM_DSLP    (BIT(22))
+#define PMU_HP_MODEM_HP_MEM_DSLP_M  (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S)
+#define PMU_HP_MODEM_HP_MEM_DSLP_V  0x00000001U
+#define PMU_HP_MODEM_HP_MEM_DSLP_S  22
+/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : WT; bitpos: [26:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_HP_MEM_PD_EN    0x0000000FU
+#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M  (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S)
+#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V  0x0000000FU
+#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S  23
+/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN    (BIT(27))
+#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M  (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S)
+#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V  0x00000001U
+#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S  27
+/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_HP_CPU_PD_EN    (BIT(29))
+#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M  (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S)
+#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V  0x00000001U
+#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S  29
+/** PMU_HP_MODEM_PD_CNNT_PD_EN : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_CNNT_PD_EN    (BIT(30))
+#define PMU_HP_MODEM_PD_CNNT_PD_EN_M  (PMU_HP_MODEM_PD_CNNT_PD_EN_V << PMU_HP_MODEM_PD_CNNT_PD_EN_S)
+#define PMU_HP_MODEM_PD_CNNT_PD_EN_V  0x00000001U
+#define PMU_HP_MODEM_PD_CNNT_PD_EN_S  30
+/** PMU_HP_MODEM_PD_TOP_PD_EN : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_TOP_PD_EN    (BIT(31))
+#define PMU_HP_MODEM_PD_TOP_PD_EN_M  (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S)
+#define PMU_HP_MODEM_PD_TOP_PD_EN_V  0x00000001U
+#define PMU_HP_MODEM_PD_TOP_PD_EN_S  31
+
+/** PMU_HP_MODEM_ICG_HP_FUNC_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38)
+/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M  (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S)
+#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S  0
+
+/** PMU_HP_MODEM_ICG_HP_APB_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c)
+/** PMU_HP_MODEM_DIG_ICG_APB_EN : WT; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_ICG_APB_EN    0xFFFFFFFFU
+#define PMU_HP_MODEM_DIG_ICG_APB_EN_M  (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S)
+#define PMU_HP_MODEM_DIG_ICG_APB_EN_V  0xFFFFFFFFU
+#define PMU_HP_MODEM_DIG_ICG_APB_EN_S  0
+
+/** PMU_HP_MODEM_ICG_MODEM_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40)
+/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : WT; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE    0x00000003U
+#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M  (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S)
+#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V  0x00000003U
+#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S  30
+
+/** PMU_HP_MODEM_HP_SYS_CNTL_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44)
+/** PMU_HP_MODEM_HP_POWER_DET_BYPASS : WT; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_POWER_DET_BYPASS    (BIT(23))
+#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M  (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S)
+#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_V  0x00000001U
+#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S  23
+/** PMU_HP_MODEM_UART_WAKEUP_EN : WT; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_UART_WAKEUP_EN    (BIT(24))
+#define PMU_HP_MODEM_UART_WAKEUP_EN_M  (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S)
+#define PMU_HP_MODEM_UART_WAKEUP_EN_V  0x00000001U
+#define PMU_HP_MODEM_UART_WAKEUP_EN_S  24
+/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : WT; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_LP_PAD_HOLD_ALL    (BIT(25))
+#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M  (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S)
+#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S  25
+/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_PAD_HOLD_ALL    (BIT(26))
+#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M  (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S)
+#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S  26
+/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_PAD_SLP_SEL    (BIT(27))
+#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M  (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S)
+#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V  0x00000001U
+#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S  27
+/** PMU_HP_MODEM_DIG_PAUSE_WDT : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_PAUSE_WDT    (BIT(28))
+#define PMU_HP_MODEM_DIG_PAUSE_WDT_M  (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S)
+#define PMU_HP_MODEM_DIG_PAUSE_WDT_V  0x00000001U
+#define PMU_HP_MODEM_DIG_PAUSE_WDT_S  28
+/** PMU_HP_MODEM_DIG_CPU_STALL : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_CPU_STALL    (BIT(29))
+#define PMU_HP_MODEM_DIG_CPU_STALL_M  (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S)
+#define PMU_HP_MODEM_DIG_CPU_STALL_V  0x00000001U
+#define PMU_HP_MODEM_DIG_CPU_STALL_S  29
+
+/** PMU_HP_MODEM_HP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48)
+/** PMU_HP_MODEM_I2C_ISO_EN : WT; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_I2C_ISO_EN    (BIT(21))
+#define PMU_HP_MODEM_I2C_ISO_EN_M  (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S)
+#define PMU_HP_MODEM_I2C_ISO_EN_V  0x00000001U
+#define PMU_HP_MODEM_I2C_ISO_EN_S  21
+/** PMU_HP_MODEM_I2C_RETENTION : WT; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_I2C_RETENTION    (BIT(22))
+#define PMU_HP_MODEM_I2C_RETENTION_M  (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S)
+#define PMU_HP_MODEM_I2C_RETENTION_V  0x00000001U
+#define PMU_HP_MODEM_I2C_RETENTION_S  22
+/** PMU_HP_MODEM_XPD_PLL_I2C : WT; bitpos: [26:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_XPD_PLL_I2C    0x0000000FU
+#define PMU_HP_MODEM_XPD_PLL_I2C_M  (PMU_HP_MODEM_XPD_PLL_I2C_V << PMU_HP_MODEM_XPD_PLL_I2C_S)
+#define PMU_HP_MODEM_XPD_PLL_I2C_V  0x0000000FU
+#define PMU_HP_MODEM_XPD_PLL_I2C_S  23
+/** PMU_HP_MODEM_XPD_PLL : WT; bitpos: [30:27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_XPD_PLL    0x0000000FU
+#define PMU_HP_MODEM_XPD_PLL_M  (PMU_HP_MODEM_XPD_PLL_V << PMU_HP_MODEM_XPD_PLL_S)
+#define PMU_HP_MODEM_XPD_PLL_V  0x0000000FU
+#define PMU_HP_MODEM_XPD_PLL_S  27
+
+/** PMU_HP_MODEM_BIAS_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c)
+/** PMU_HP_MODEM_DCM_VSET : WT; bitpos: [22:18]; default: 20;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DCM_VSET    0x0000001FU
+#define PMU_HP_MODEM_DCM_VSET_M  (PMU_HP_MODEM_DCM_VSET_V << PMU_HP_MODEM_DCM_VSET_S)
+#define PMU_HP_MODEM_DCM_VSET_V  0x0000001FU
+#define PMU_HP_MODEM_DCM_VSET_S  18
+/** PMU_HP_MODEM_DCM_MODE : WT; bitpos: [24:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DCM_MODE    0x00000003U
+#define PMU_HP_MODEM_DCM_MODE_M  (PMU_HP_MODEM_DCM_MODE_V << PMU_HP_MODEM_DCM_MODE_S)
+#define PMU_HP_MODEM_DCM_MODE_V  0x00000003U
+#define PMU_HP_MODEM_DCM_MODE_S  23
+/** PMU_HP_MODEM_XPD_BIAS : WT; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_XPD_BIAS    (BIT(25))
+#define PMU_HP_MODEM_XPD_BIAS_M  (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S)
+#define PMU_HP_MODEM_XPD_BIAS_V  0x00000001U
+#define PMU_HP_MODEM_XPD_BIAS_S  25
+/** PMU_HP_MODEM_DBG_ATTEN : WT; bitpos: [29:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DBG_ATTEN    0x0000000FU
+#define PMU_HP_MODEM_DBG_ATTEN_M  (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S)
+#define PMU_HP_MODEM_DBG_ATTEN_V  0x0000000FU
+#define PMU_HP_MODEM_DBG_ATTEN_S  26
+/** PMU_HP_MODEM_PD_CUR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_PD_CUR    (BIT(30))
+#define PMU_HP_MODEM_PD_CUR_M  (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S)
+#define PMU_HP_MODEM_PD_CUR_V  0x00000001U
+#define PMU_HP_MODEM_PD_CUR_S  30
+/** PMU_HP_MODEM_BIAS_SLEEP : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_BIAS_SLEEP    (BIT(31))
+#define PMU_HP_MODEM_BIAS_SLEEP_M  (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S)
+#define PMU_HP_MODEM_BIAS_SLEEP_V  0x00000001U
+#define PMU_HP_MODEM_BIAS_SLEEP_S  31
+
+/** PMU_HP_MODEM_BACKUP_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50)
+/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : WT; bitpos: [5:4]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE    0x00000003U
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S)
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V  0x00000003U
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S  4
+/** PMU_HP_MODEM_RETENTION_MODE : WT; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_RETENTION_MODE    (BIT(10))
+#define PMU_HP_MODEM_RETENTION_MODE_M  (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S)
+#define PMU_HP_MODEM_RETENTION_MODE_V  0x00000001U
+#define PMU_HP_MODEM_RETENTION_MODE_S  10
+/** PMU_HP_SLEEP2MODEM_RETENTION_EN : WT; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2MODEM_RETENTION_EN    (BIT(11))
+#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M  (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S)
+#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V  0x00000001U
+#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S  11
+/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : WT; bitpos: [15:14]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL    0x00000003U
+#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M  (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S)
+#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V  0x00000003U
+#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S  14
+/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : WT; bitpos: [22:20]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODE    0x00000007U
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M  (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S)
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V  0x00000007U
+#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S  20
+/** PMU_HP_SLEEP2MODEM_BACKUP_EN : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP2MODEM_BACKUP_EN    (BIT(29))
+#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M  (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S)
+#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V  0x00000001U
+#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S  29
+
+/** PMU_HP_MODEM_BACKUP_CLK_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54)
+/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M  (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S)
+#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S  0
+
+/** PMU_HP_MODEM_SYSCLK_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58)
+/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV    (BIT(26))
+#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S)
+#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V  0x00000001U
+#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S  26
+/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN    (BIT(27))
+#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M  (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S)
+#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V  0x00000001U
+#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S  27
+/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_SYS_CLK_SLP_SEL    (BIT(28))
+#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M  (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S)
+#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V  0x00000001U
+#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S  28
+/** PMU_HP_MODEM_ICG_SLP_SEL : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_ICG_SLP_SEL    (BIT(29))
+#define PMU_HP_MODEM_ICG_SLP_SEL_M  (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S)
+#define PMU_HP_MODEM_ICG_SLP_SEL_V  0x00000001U
+#define PMU_HP_MODEM_ICG_SLP_SEL_S  29
+/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : WT; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_DIG_SYS_CLK_SEL    0x00000003U
+#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M  (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S)
+#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V  0x00000003U
+#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S  30
+
+/** PMU_HP_MODEM_HP_REGULATOR0_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c)
+/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : WT; bitpos: [16]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S)
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S  16
+/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : WT; bitpos: [17]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S)
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S  17
+/** PMU_HP_MODEM_HP_REGULATOR_XPD : WT; bitpos: [18]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_XPD    (BIT(18))
+#define PMU_HP_MODEM_HP_REGULATOR_XPD_M  (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S)
+#define PMU_HP_MODEM_HP_REGULATOR_XPD_V  0x00000001U
+#define PMU_HP_MODEM_HP_REGULATOR_XPD_S  18
+/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : WT; bitpos: [22:19]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S)
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S  19
+/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : WT; bitpos: [26:23]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
+#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
+/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : WT; bitpos: [31:27]; default: 24;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_DBIAS    0x0000001FU
+#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M  (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S)
+#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V  0x0000001FU
+#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S  27
+
+/** PMU_HP_MODEM_HP_REGULATOR1_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60)
+/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : WT; bitpos: [31:8]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM_HP_REGULATOR_DRV_B    0x00FFFFFFU
+#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M  (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S)
+#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V  0x00FFFFFFU
+#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S  8
+
+/** PMU_HP_MODEM_XTAL_REG register
+ *  need_des
+ */
+#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64)
+/** PMU_HP_MODEM_XPD_XTAL : WT; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_MODEM_XPD_XTAL    (BIT(31))
+#define PMU_HP_MODEM_XPD_XTAL_M  (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S)
+#define PMU_HP_MODEM_XPD_XTAL_V  0x00000001U
+#define PMU_HP_MODEM_XPD_XTAL_S  31
+
+/** PMU_HP_SLEEP_DIG_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68)
+/** PMU_HP_SLEEP_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN    (BIT(21))
+#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_M  (PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_V << PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_S)
+#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_S  21
+/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_MEM_DSLP    (BIT(22))
+#define PMU_HP_SLEEP_HP_MEM_DSLP_M  (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S)
+#define PMU_HP_SLEEP_HP_MEM_DSLP_V  0x00000001U
+#define PMU_HP_SLEEP_HP_MEM_DSLP_S  22
+/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN    (BIT(23))
+#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M  (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S)
+#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S  23
+/** PMU_HP_SLEEP_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_CNNT_PD_EN    (BIT(30))
+#define PMU_HP_SLEEP_PD_CNNT_PD_EN_M  (PMU_HP_SLEEP_PD_CNNT_PD_EN_V << PMU_HP_SLEEP_PD_CNNT_PD_EN_S)
+#define PMU_HP_SLEEP_PD_CNNT_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_PD_CNNT_PD_EN_S  30
+/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_TOP_PD_EN    (BIT(31))
+#define PMU_HP_SLEEP_PD_TOP_PD_EN_M  (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S)
+#define PMU_HP_SLEEP_PD_TOP_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_PD_TOP_PD_EN_S  31
+
+/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c)
+/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M  (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S)
+#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S  0
+
+/** PMU_HP_SLEEP_ICG_HP_APB_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70)
+/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_ICG_APB_EN    0xFFFFFFFFU
+#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M  (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S)
+#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V  0xFFFFFFFFU
+#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S  0
+
+/** PMU_HP_SLEEP_ICG_MODEM_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74)
+/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE    0x00000003U
+#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M  (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S)
+#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V  0x00000003U
+#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S  30
+
+/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78)
+/** PMU_HP_SLEEP_HP_POWER_DET_BYPASS : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS    (BIT(23))
+#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_M  (PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V << PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S)
+#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V  0x00000001U
+#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S  23
+/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_UART_WAKEUP_EN    (BIT(24))
+#define PMU_HP_SLEEP_UART_WAKEUP_EN_M  (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S)
+#define PMU_HP_SLEEP_UART_WAKEUP_EN_V  0x00000001U
+#define PMU_HP_SLEEP_UART_WAKEUP_EN_S  24
+/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL    (BIT(25))
+#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M  (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S)
+#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S  25
+/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL    (BIT(26))
+#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M  (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S)
+#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S  26
+/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL    (BIT(27))
+#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M  (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S)
+#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V  0x00000001U
+#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S  27
+/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_PAUSE_WDT    (BIT(28))
+#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M  (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S)
+#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V  0x00000001U
+#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S  28
+/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_CPU_STALL    (BIT(29))
+#define PMU_HP_SLEEP_DIG_CPU_STALL_M  (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S)
+#define PMU_HP_SLEEP_DIG_CPU_STALL_V  0x00000001U
+#define PMU_HP_SLEEP_DIG_CPU_STALL_S  29
+
+/** PMU_HP_SLEEP_HP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c)
+/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_I2C_ISO_EN    (BIT(21))
+#define PMU_HP_SLEEP_I2C_ISO_EN_M  (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S)
+#define PMU_HP_SLEEP_I2C_ISO_EN_V  0x00000001U
+#define PMU_HP_SLEEP_I2C_ISO_EN_S  21
+/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_I2C_RETENTION    (BIT(22))
+#define PMU_HP_SLEEP_I2C_RETENTION_M  (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S)
+#define PMU_HP_SLEEP_I2C_RETENTION_V  0x00000001U
+#define PMU_HP_SLEEP_I2C_RETENTION_S  22
+/** PMU_HP_SLEEP_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_PLL_I2C    0x0000000FU
+#define PMU_HP_SLEEP_XPD_PLL_I2C_M  (PMU_HP_SLEEP_XPD_PLL_I2C_V << PMU_HP_SLEEP_XPD_PLL_I2C_S)
+#define PMU_HP_SLEEP_XPD_PLL_I2C_V  0x0000000FU
+#define PMU_HP_SLEEP_XPD_PLL_I2C_S  23
+/** PMU_HP_SLEEP_XPD_PLL : R/W; bitpos: [30:27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_PLL    0x0000000FU
+#define PMU_HP_SLEEP_XPD_PLL_M  (PMU_HP_SLEEP_XPD_PLL_V << PMU_HP_SLEEP_XPD_PLL_S)
+#define PMU_HP_SLEEP_XPD_PLL_V  0x0000000FU
+#define PMU_HP_SLEEP_XPD_PLL_S  27
+
+/** PMU_HP_SLEEP_BIAS_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80)
+/** PMU_HP_SLEEP_DCM_VSET : R/W; bitpos: [22:18]; default: 20;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DCM_VSET    0x0000001FU
+#define PMU_HP_SLEEP_DCM_VSET_M  (PMU_HP_SLEEP_DCM_VSET_V << PMU_HP_SLEEP_DCM_VSET_S)
+#define PMU_HP_SLEEP_DCM_VSET_V  0x0000001FU
+#define PMU_HP_SLEEP_DCM_VSET_S  18
+/** PMU_HP_SLEEP_DCM_MODE : R/W; bitpos: [24:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DCM_MODE    0x00000003U
+#define PMU_HP_SLEEP_DCM_MODE_M  (PMU_HP_SLEEP_DCM_MODE_V << PMU_HP_SLEEP_DCM_MODE_S)
+#define PMU_HP_SLEEP_DCM_MODE_V  0x00000003U
+#define PMU_HP_SLEEP_DCM_MODE_S  23
+/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_BIAS    (BIT(25))
+#define PMU_HP_SLEEP_XPD_BIAS_M  (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S)
+#define PMU_HP_SLEEP_XPD_BIAS_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_BIAS_S  25
+/** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DBG_ATTEN    0x0000000FU
+#define PMU_HP_SLEEP_DBG_ATTEN_M  (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S)
+#define PMU_HP_SLEEP_DBG_ATTEN_V  0x0000000FU
+#define PMU_HP_SLEEP_DBG_ATTEN_S  26
+/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_CUR    (BIT(30))
+#define PMU_HP_SLEEP_PD_CUR_M  (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S)
+#define PMU_HP_SLEEP_PD_CUR_V  0x00000001U
+#define PMU_HP_SLEEP_PD_CUR_S  30
+/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BIAS_SLEEP    (BIT(31))
+#define PMU_HP_SLEEP_BIAS_SLEEP_M  (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S)
+#define PMU_HP_SLEEP_BIAS_SLEEP_V  0x00000001U
+#define PMU_HP_SLEEP_BIAS_SLEEP_S  31
+
+/** PMU_HP_SLEEP_BACKUP_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84)
+/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE    0x00000003U
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S)
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V  0x00000003U
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S  6
+/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE    0x00000003U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S)
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V  0x00000003U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S  8
+/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_RETENTION_MODE    (BIT(10))
+#define PMU_HP_SLEEP_RETENTION_MODE_M  (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S)
+#define PMU_HP_SLEEP_RETENTION_MODE_V  0x00000001U
+#define PMU_HP_SLEEP_RETENTION_MODE_S  10
+/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2SLEEP_RETENTION_EN    (BIT(12))
+#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M  (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S)
+#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V  0x00000001U
+#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S  12
+/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN    (BIT(13))
+#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M  (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S)
+#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V  0x00000001U
+#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S  13
+/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL    0x00000003U
+#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M  (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S)
+#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V  0x00000003U
+#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S  16
+/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL    0x00000003U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S)
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V  0x00000003U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S  18
+/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODE    0x00000007U
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M  (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S)
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V  0x00000007U
+#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S  23
+/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE    0x00000007U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S)
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V  0x00000007U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S  26
+/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MODEM2SLEEP_BACKUP_EN    (BIT(30))
+#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M  (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S)
+#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V  0x00000001U
+#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S  30
+/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN    (BIT(31))
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S)
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V  0x00000001U
+#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S  31
+
+/** PMU_HP_SLEEP_BACKUP_CLK_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88)
+/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
+#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M  (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S)
+#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
+#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S  0
+
+/** PMU_HP_SLEEP_SYSCLK_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c)
+/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV    (BIT(26))
+#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S)
+#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V  0x00000001U
+#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S  26
+/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN    (BIT(27))
+#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M  (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S)
+#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V  0x00000001U
+#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S  27
+/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL    (BIT(28))
+#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M  (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S)
+#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V  0x00000001U
+#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S  28
+/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_ICG_SLP_SEL    (BIT(29))
+#define PMU_HP_SLEEP_ICG_SLP_SEL_M  (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S)
+#define PMU_HP_SLEEP_ICG_SLP_SEL_V  0x00000001U
+#define PMU_HP_SLEEP_ICG_SLP_SEL_S  29
+/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL    0x00000003U
+#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M  (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S)
+#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V  0x00000003U
+#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S  30
+
+/** PMU_HP_SLEEP_HP_REGULATOR0_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90)
+/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S  16
+/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S  17
+/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_XPD    (BIT(18))
+#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V  0x00000001U
+#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S  18
+/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S  19
+/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
+#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
+/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS    0x0000001FU
+#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V  0x0000001FU
+#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S  27
+
+/** PMU_HP_SLEEP_HP_REGULATOR1_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94)
+/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B    0x0000003FU
+#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M  (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S)
+#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V  0x0000003FU
+#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S  26
+
+/** PMU_HP_SLEEP_XTAL_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98)
+/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_XTAL    (BIT(31))
+#define PMU_HP_SLEEP_XPD_XTAL_M  (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S)
+#define PMU_HP_SLEEP_XPD_XTAL_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_XTAL_S  31
+
+/** PMU_HP_SLEEP_LP_REGULATOR0_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c)
+/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD    (BIT(21))
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M  (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S)
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V  0x00000001U
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S  21
+/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR_XPD    (BIT(22))
+#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M  (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S)
+#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V  0x00000001U
+#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S  22
+/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS    0x0000000FU
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M  (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S)
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V  0x0000000FU
+#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S  23
+/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS    0x0000001FU
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M  (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S)
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V  0x0000001FU
+#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S  27
+
+/** PMU_HP_SLEEP_LP_REGULATOR1_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0)
+/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B    0x0000003FU
+#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M  (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S)
+#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V  0x0000003FU
+#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S  26
+
+/** PMU_HP_SLEEP_LP_DIG_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8)
+/** PMU_HP_SLEEP_LP_PAD_SLP_SEL : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_PAD_SLP_SEL    (BIT(26))
+#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_M  (PMU_HP_SLEEP_LP_PAD_SLP_SEL_V << PMU_HP_SLEEP_LP_PAD_SLP_SEL_S)
+#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_V  0x00000001U
+#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_S  26
+/** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_BOD_SOURCE_SEL    (BIT(27))
+#define PMU_HP_SLEEP_BOD_SOURCE_SEL_M  (PMU_HP_SLEEP_BOD_SOURCE_SEL_V << PMU_HP_SLEEP_BOD_SOURCE_SEL_S)
+#define PMU_HP_SLEEP_BOD_SOURCE_SEL_V  0x00000001U
+#define PMU_HP_SLEEP_BOD_SOURCE_SEL_S  27
+/** PMU_HP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_VDDBAT_MODE    0x00000003U
+#define PMU_HP_SLEEP_VDDBAT_MODE_M  (PMU_HP_SLEEP_VDDBAT_MODE_V << PMU_HP_SLEEP_VDDBAT_MODE_S)
+#define PMU_HP_SLEEP_VDDBAT_MODE_V  0x00000003U
+#define PMU_HP_SLEEP_VDDBAT_MODE_S  28
+/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_MEM_DSLP    (BIT(30))
+#define PMU_HP_SLEEP_LP_MEM_DSLP_M  (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S)
+#define PMU_HP_SLEEP_LP_MEM_DSLP_V  0x00000001U
+#define PMU_HP_SLEEP_LP_MEM_DSLP_S  30
+/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN    (BIT(31))
+#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M  (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S)
+#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V  0x00000001U
+#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S  31
+
+/** PMU_HP_SLEEP_LP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac)
+/** PMU_HP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_LPPLL    (BIT(27))
+#define PMU_HP_SLEEP_XPD_LPPLL_M  (PMU_HP_SLEEP_XPD_LPPLL_V << PMU_HP_SLEEP_XPD_LPPLL_S)
+#define PMU_HP_SLEEP_XPD_LPPLL_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_LPPLL_S  27
+/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_XTAL32K    (BIT(28))
+#define PMU_HP_SLEEP_XPD_XTAL32K_M  (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S)
+#define PMU_HP_SLEEP_XPD_XTAL32K_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_XTAL32K_S  28
+/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_RC32K    (BIT(29))
+#define PMU_HP_SLEEP_XPD_RC32K_M  (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S)
+#define PMU_HP_SLEEP_XPD_RC32K_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_RC32K_S  29
+/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_XPD_FOSC_CLK    (BIT(30))
+#define PMU_HP_SLEEP_XPD_FOSC_CLK_M  (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S)
+#define PMU_HP_SLEEP_XPD_FOSC_CLK_V  0x00000001U
+#define PMU_HP_SLEEP_XPD_FOSC_CLK_S  30
+/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SLEEP_PD_OSC_CLK    (BIT(31))
+#define PMU_HP_SLEEP_PD_OSC_CLK_M  (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S)
+#define PMU_HP_SLEEP_PD_OSC_CLK_V  0x00000001U
+#define PMU_HP_SLEEP_PD_OSC_CLK_S  31
+
+/** PMU_LP_SLEEP_LP_REGULATOR0_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4)
+/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD    (BIT(21))
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M  (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S)
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V  0x00000001U
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S  21
+/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR_XPD    (BIT(22))
+#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M  (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S)
+#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V  0x00000001U
+#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S  22
+/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS    0x0000000FU
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M  (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S)
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V  0x0000000FU
+#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S  23
+/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS    0x0000001FU
+#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M  (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S)
+#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V  0x0000001FU
+#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S  27
+
+/** PMU_LP_SLEEP_LP_REGULATOR1_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8)
+/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B    0x0000003FU
+#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M  (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S)
+#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V  0x0000003FU
+#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S  26
+
+/** PMU_LP_SLEEP_XTAL_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc)
+/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_XTAL    (BIT(31))
+#define PMU_LP_SLEEP_XPD_XTAL_M  (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S)
+#define PMU_LP_SLEEP_XPD_XTAL_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_XTAL_S  31
+
+/** PMU_LP_SLEEP_LP_DIG_POWER_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0)
+/** PMU_LP_SLEEP_LP_PAD_SLP_SEL : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_PAD_SLP_SEL    (BIT(26))
+#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_M  (PMU_LP_SLEEP_LP_PAD_SLP_SEL_V << PMU_LP_SLEEP_LP_PAD_SLP_SEL_S)
+#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_V  0x00000001U
+#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_S  26
+/** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_BOD_SOURCE_SEL    (BIT(27))
+#define PMU_LP_SLEEP_BOD_SOURCE_SEL_M  (PMU_LP_SLEEP_BOD_SOURCE_SEL_V << PMU_LP_SLEEP_BOD_SOURCE_SEL_S)
+#define PMU_LP_SLEEP_BOD_SOURCE_SEL_V  0x00000001U
+#define PMU_LP_SLEEP_BOD_SOURCE_SEL_S  27
+/** PMU_LP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_VDDBAT_MODE    0x00000003U
+#define PMU_LP_SLEEP_VDDBAT_MODE_M  (PMU_LP_SLEEP_VDDBAT_MODE_V << PMU_LP_SLEEP_VDDBAT_MODE_S)
+#define PMU_LP_SLEEP_VDDBAT_MODE_V  0x00000003U
+#define PMU_LP_SLEEP_VDDBAT_MODE_S  28
+/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_MEM_DSLP    (BIT(30))
+#define PMU_LP_SLEEP_LP_MEM_DSLP_M  (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S)
+#define PMU_LP_SLEEP_LP_MEM_DSLP_V  0x00000001U
+#define PMU_LP_SLEEP_LP_MEM_DSLP_S  30
+/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN    (BIT(31))
+#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M  (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S)
+#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V  0x00000001U
+#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S  31
+
+/** PMU_LP_SLEEP_LP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4)
+/** PMU_LP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_LPPLL    (BIT(27))
+#define PMU_LP_SLEEP_XPD_LPPLL_M  (PMU_LP_SLEEP_XPD_LPPLL_V << PMU_LP_SLEEP_XPD_LPPLL_S)
+#define PMU_LP_SLEEP_XPD_LPPLL_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_LPPLL_S  27
+/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_XTAL32K    (BIT(28))
+#define PMU_LP_SLEEP_XPD_XTAL32K_M  (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S)
+#define PMU_LP_SLEEP_XPD_XTAL32K_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_XTAL32K_S  28
+/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_RC32K    (BIT(29))
+#define PMU_LP_SLEEP_XPD_RC32K_M  (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S)
+#define PMU_LP_SLEEP_XPD_RC32K_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_RC32K_S  29
+/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_FOSC_CLK    (BIT(30))
+#define PMU_LP_SLEEP_XPD_FOSC_CLK_M  (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S)
+#define PMU_LP_SLEEP_XPD_FOSC_CLK_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_FOSC_CLK_S  30
+/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_PD_OSC_CLK    (BIT(31))
+#define PMU_LP_SLEEP_PD_OSC_CLK_M  (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S)
+#define PMU_LP_SLEEP_PD_OSC_CLK_V  0x00000001U
+#define PMU_LP_SLEEP_PD_OSC_CLK_S  31
+
+/** PMU_LP_SLEEP_BIAS_REG register
+ *  need_des
+ */
+#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8)
+/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_XPD_BIAS    (BIT(25))
+#define PMU_LP_SLEEP_XPD_BIAS_M  (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S)
+#define PMU_LP_SLEEP_XPD_BIAS_V  0x00000001U
+#define PMU_LP_SLEEP_XPD_BIAS_S  25
+/** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_DBG_ATTEN    0x0000000FU
+#define PMU_LP_SLEEP_DBG_ATTEN_M  (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S)
+#define PMU_LP_SLEEP_DBG_ATTEN_V  0x0000000FU
+#define PMU_LP_SLEEP_DBG_ATTEN_S  26
+/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_PD_CUR    (BIT(30))
+#define PMU_LP_SLEEP_PD_CUR_M  (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S)
+#define PMU_LP_SLEEP_PD_CUR_V  0x00000001U
+#define PMU_LP_SLEEP_PD_CUR_S  30
+/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_SLEEP_BIAS_SLEEP    (BIT(31))
+#define PMU_LP_SLEEP_BIAS_SLEEP_M  (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S)
+#define PMU_LP_SLEEP_BIAS_SLEEP_V  0x00000001U
+#define PMU_LP_SLEEP_BIAS_SLEEP_S  31
+
+/** PMU_IMM_HP_CK_POWER_REG register
+ *  need_des
+ */
+#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc)
+/** PMU_TIE_LOW_CALI_XTAL_ICG : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_CALI_XTAL_ICG    (BIT(0))
+#define PMU_TIE_LOW_CALI_XTAL_ICG_M  (PMU_TIE_LOW_CALI_XTAL_ICG_V << PMU_TIE_LOW_CALI_XTAL_ICG_S)
+#define PMU_TIE_LOW_CALI_XTAL_ICG_V  0x00000001U
+#define PMU_TIE_LOW_CALI_XTAL_ICG_S  0
+/** PMU_TIE_LOW_GLOBAL_CPLL_ICG : WT; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_GLOBAL_CPLL_ICG    (BIT(1))
+#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_M  (PMU_TIE_LOW_GLOBAL_CPLL_ICG_V << PMU_TIE_LOW_GLOBAL_CPLL_ICG_S)
+#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_V  0x00000001U
+#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_S  1
+/** PMU_TIE_LOW_GLOBAL_SPLL_ICG : WT; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_GLOBAL_SPLL_ICG    (BIT(2))
+#define PMU_TIE_LOW_GLOBAL_SPLL_ICG_M  (PMU_TIE_LOW_GLOBAL_SPLL_ICG_V << PMU_TIE_LOW_GLOBAL_SPLL_ICG_S)
+#define PMU_TIE_LOW_GLOBAL_SPLL_ICG_V  0x00000001U
+#define PMU_TIE_LOW_GLOBAL_SPLL_ICG_S  2
+/** PMU_TIE_LOW_GLOBAL_APLL_ICG : WT; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_GLOBAL_APLL_ICG    (BIT(3))
+#define PMU_TIE_LOW_GLOBAL_APLL_ICG_M  (PMU_TIE_LOW_GLOBAL_APLL_ICG_V << PMU_TIE_LOW_GLOBAL_APLL_ICG_S)
+#define PMU_TIE_LOW_GLOBAL_APLL_ICG_V  0x00000001U
+#define PMU_TIE_LOW_GLOBAL_APLL_ICG_S  3
+/** PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG : WT; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG    (BIT(4))
+#define PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG_M  (PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG_V << PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG_S)
+#define PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG_V  0x00000001U
+#define PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG_S  4
+/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_GLOBAL_XTAL_ICG    (BIT(5))
+#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M  (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S)
+#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V  0x00000001U
+#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S  5
+/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_I2C_RETENTION    (BIT(6))
+#define PMU_TIE_LOW_I2C_RETENTION_M  (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S)
+#define PMU_TIE_LOW_I2C_RETENTION_V  0x00000001U
+#define PMU_TIE_LOW_I2C_RETENTION_S  6
+/** PMU_TIE_LOW_XPD_CPLL_I2C : WT; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_CPLL_I2C    (BIT(7))
+#define PMU_TIE_LOW_XPD_CPLL_I2C_M  (PMU_TIE_LOW_XPD_CPLL_I2C_V << PMU_TIE_LOW_XPD_CPLL_I2C_S)
+#define PMU_TIE_LOW_XPD_CPLL_I2C_V  0x00000001U
+#define PMU_TIE_LOW_XPD_CPLL_I2C_S  7
+/** PMU_TIE_LOW_XPD_SPLL_I2C : WT; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_SPLL_I2C    (BIT(8))
+#define PMU_TIE_LOW_XPD_SPLL_I2C_M  (PMU_TIE_LOW_XPD_SPLL_I2C_V << PMU_TIE_LOW_XPD_SPLL_I2C_S)
+#define PMU_TIE_LOW_XPD_SPLL_I2C_V  0x00000001U
+#define PMU_TIE_LOW_XPD_SPLL_I2C_S  8
+/** PMU_TIE_LOW_XPD_APLL_I2C : WT; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_APLL_I2C    (BIT(9))
+#define PMU_TIE_LOW_XPD_APLL_I2C_M  (PMU_TIE_LOW_XPD_APLL_I2C_V << PMU_TIE_LOW_XPD_APLL_I2C_S)
+#define PMU_TIE_LOW_XPD_APLL_I2C_V  0x00000001U
+#define PMU_TIE_LOW_XPD_APLL_I2C_S  9
+/** PMU_TIE_LOW_XPD_SDIOPLL_I2C : WT; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_SDIOPLL_I2C    (BIT(10))
+#define PMU_TIE_LOW_XPD_SDIOPLL_I2C_M  (PMU_TIE_LOW_XPD_SDIOPLL_I2C_V << PMU_TIE_LOW_XPD_SDIOPLL_I2C_S)
+#define PMU_TIE_LOW_XPD_SDIOPLL_I2C_V  0x00000001U
+#define PMU_TIE_LOW_XPD_SDIOPLL_I2C_S  10
+/** PMU_TIE_LOW_XPD_CPLL : WT; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_CPLL    (BIT(11))
+#define PMU_TIE_LOW_XPD_CPLL_M  (PMU_TIE_LOW_XPD_CPLL_V << PMU_TIE_LOW_XPD_CPLL_S)
+#define PMU_TIE_LOW_XPD_CPLL_V  0x00000001U
+#define PMU_TIE_LOW_XPD_CPLL_S  11
+/** PMU_TIE_LOW_XPD_SPLL : WT; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_SPLL    (BIT(12))
+#define PMU_TIE_LOW_XPD_SPLL_M  (PMU_TIE_LOW_XPD_SPLL_V << PMU_TIE_LOW_XPD_SPLL_S)
+#define PMU_TIE_LOW_XPD_SPLL_V  0x00000001U
+#define PMU_TIE_LOW_XPD_SPLL_S  12
+/** PMU_TIE_LOW_XPD_APLL : WT; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_APLL    (BIT(13))
+#define PMU_TIE_LOW_XPD_APLL_M  (PMU_TIE_LOW_XPD_APLL_V << PMU_TIE_LOW_XPD_APLL_S)
+#define PMU_TIE_LOW_XPD_APLL_V  0x00000001U
+#define PMU_TIE_LOW_XPD_APLL_S  13
+/** PMU_TIE_LOW_XPD_SDIOPLL : WT; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_SDIOPLL    (BIT(14))
+#define PMU_TIE_LOW_XPD_SDIOPLL_M  (PMU_TIE_LOW_XPD_SDIOPLL_V << PMU_TIE_LOW_XPD_SDIOPLL_S)
+#define PMU_TIE_LOW_XPD_SDIOPLL_V  0x00000001U
+#define PMU_TIE_LOW_XPD_SDIOPLL_S  14
+/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_XPD_XTAL    (BIT(15))
+#define PMU_TIE_LOW_XPD_XTAL_M  (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S)
+#define PMU_TIE_LOW_XPD_XTAL_V  0x00000001U
+#define PMU_TIE_LOW_XPD_XTAL_S  15
+/** PMU_TIE_HIGH_CALI_XTAL_ICG : R/W; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_CALI_XTAL_ICG    (BIT(16))
+#define PMU_TIE_HIGH_CALI_XTAL_ICG_M  (PMU_TIE_HIGH_CALI_XTAL_ICG_V << PMU_TIE_HIGH_CALI_XTAL_ICG_S)
+#define PMU_TIE_HIGH_CALI_XTAL_ICG_V  0x00000001U
+#define PMU_TIE_HIGH_CALI_XTAL_ICG_S  16
+/** PMU_TIE_HIGH_GLOBAL_CPLL_ICG : WT; bitpos: [17]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG    (BIT(17))
+#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_M  (PMU_TIE_HIGH_GLOBAL_CPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_CPLL_ICG_S)
+#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_V  0x00000001U
+#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_S  17
+/** PMU_TIE_HIGH_GLOBAL_SPLL_ICG : WT; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_GLOBAL_SPLL_ICG    (BIT(18))
+#define PMU_TIE_HIGH_GLOBAL_SPLL_ICG_M  (PMU_TIE_HIGH_GLOBAL_SPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_SPLL_ICG_S)
+#define PMU_TIE_HIGH_GLOBAL_SPLL_ICG_V  0x00000001U
+#define PMU_TIE_HIGH_GLOBAL_SPLL_ICG_S  18
+/** PMU_TIE_HIGH_GLOBAL_APLL_ICG : WT; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_GLOBAL_APLL_ICG    (BIT(19))
+#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_M  (PMU_TIE_HIGH_GLOBAL_APLL_ICG_V << PMU_TIE_HIGH_GLOBAL_APLL_ICG_S)
+#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_V  0x00000001U
+#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_S  19
+/** PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG : WT; bitpos: [20]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG    (BIT(20))
+#define PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG_M  (PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG_S)
+#define PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG_V  0x00000001U
+#define PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG_S  20
+/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG    (BIT(21))
+#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M  (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S)
+#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V  0x00000001U
+#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S  21
+/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_I2C_RETENTION    (BIT(22))
+#define PMU_TIE_HIGH_I2C_RETENTION_M  (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S)
+#define PMU_TIE_HIGH_I2C_RETENTION_V  0x00000001U
+#define PMU_TIE_HIGH_I2C_RETENTION_S  22
+/** PMU_TIE_HIGH_XPD_CPLL_I2C : WT; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_CPLL_I2C    (BIT(23))
+#define PMU_TIE_HIGH_XPD_CPLL_I2C_M  (PMU_TIE_HIGH_XPD_CPLL_I2C_V << PMU_TIE_HIGH_XPD_CPLL_I2C_S)
+#define PMU_TIE_HIGH_XPD_CPLL_I2C_V  0x00000001U
+#define PMU_TIE_HIGH_XPD_CPLL_I2C_S  23
+/** PMU_TIE_HIGH_XPD_SPLL_I2C : WT; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_SPLL_I2C    (BIT(24))
+#define PMU_TIE_HIGH_XPD_SPLL_I2C_M  (PMU_TIE_HIGH_XPD_SPLL_I2C_V << PMU_TIE_HIGH_XPD_SPLL_I2C_S)
+#define PMU_TIE_HIGH_XPD_SPLL_I2C_V  0x00000001U
+#define PMU_TIE_HIGH_XPD_SPLL_I2C_S  24
+/** PMU_TIE_HIGH_XPD_APLL_I2C : WT; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_APLL_I2C    (BIT(25))
+#define PMU_TIE_HIGH_XPD_APLL_I2C_M  (PMU_TIE_HIGH_XPD_APLL_I2C_V << PMU_TIE_HIGH_XPD_APLL_I2C_S)
+#define PMU_TIE_HIGH_XPD_APLL_I2C_V  0x00000001U
+#define PMU_TIE_HIGH_XPD_APLL_I2C_S  25
+/** PMU_TIE_HIGH_XPD_SDIOPLL_I2C : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_SDIOPLL_I2C    (BIT(26))
+#define PMU_TIE_HIGH_XPD_SDIOPLL_I2C_M  (PMU_TIE_HIGH_XPD_SDIOPLL_I2C_V << PMU_TIE_HIGH_XPD_SDIOPLL_I2C_S)
+#define PMU_TIE_HIGH_XPD_SDIOPLL_I2C_V  0x00000001U
+#define PMU_TIE_HIGH_XPD_SDIOPLL_I2C_S  26
+/** PMU_TIE_HIGH_XPD_CPLL : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_CPLL    (BIT(27))
+#define PMU_TIE_HIGH_XPD_CPLL_M  (PMU_TIE_HIGH_XPD_CPLL_V << PMU_TIE_HIGH_XPD_CPLL_S)
+#define PMU_TIE_HIGH_XPD_CPLL_V  0x00000001U
+#define PMU_TIE_HIGH_XPD_CPLL_S  27
+/** PMU_TIE_HIGH_XPD_SPLL : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_SPLL    (BIT(28))
+#define PMU_TIE_HIGH_XPD_SPLL_M  (PMU_TIE_HIGH_XPD_SPLL_V << PMU_TIE_HIGH_XPD_SPLL_S)
+#define PMU_TIE_HIGH_XPD_SPLL_V  0x00000001U
+#define PMU_TIE_HIGH_XPD_SPLL_S  28
+/** PMU_TIE_HIGH_XPD_APLL : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_APLL    (BIT(29))
+#define PMU_TIE_HIGH_XPD_APLL_M  (PMU_TIE_HIGH_XPD_APLL_V << PMU_TIE_HIGH_XPD_APLL_S)
+#define PMU_TIE_HIGH_XPD_APLL_V  0x00000001U
+#define PMU_TIE_HIGH_XPD_APLL_S  29
+/** PMU_TIE_HIGH_XPD_SDIOPLL : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_SDIOPLL    (BIT(30))
+#define PMU_TIE_HIGH_XPD_SDIOPLL_M  (PMU_TIE_HIGH_XPD_SDIOPLL_V << PMU_TIE_HIGH_XPD_SDIOPLL_S)
+#define PMU_TIE_HIGH_XPD_SDIOPLL_V  0x00000001U
+#define PMU_TIE_HIGH_XPD_SDIOPLL_S  30
+/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_XPD_XTAL    (BIT(31))
+#define PMU_TIE_HIGH_XPD_XTAL_M  (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S)
+#define PMU_TIE_HIGH_XPD_XTAL_V  0x00000001U
+#define PMU_TIE_HIGH_XPD_XTAL_S  31
+
+/** PMU_IMM_SLEEP_SYSCLK_REG register
+ *  need_des
+ */
+#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0)
+/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_UPDATE_DIG_ICG_SWITCH    (BIT(28))
+#define PMU_UPDATE_DIG_ICG_SWITCH_M  (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S)
+#define PMU_UPDATE_DIG_ICG_SWITCH_V  0x00000001U
+#define PMU_UPDATE_DIG_ICG_SWITCH_S  28
+/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_ICG_SLP_SEL    (BIT(29))
+#define PMU_TIE_LOW_ICG_SLP_SEL_M  (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S)
+#define PMU_TIE_LOW_ICG_SLP_SEL_V  0x00000001U
+#define PMU_TIE_LOW_ICG_SLP_SEL_S  29
+/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_ICG_SLP_SEL    (BIT(30))
+#define PMU_TIE_HIGH_ICG_SLP_SEL_M  (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S)
+#define PMU_TIE_HIGH_ICG_SLP_SEL_V  0x00000001U
+#define PMU_TIE_HIGH_ICG_SLP_SEL_S  30
+/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_UPDATE_DIG_SYS_CLK_SEL    (BIT(31))
+#define PMU_UPDATE_DIG_SYS_CLK_SEL_M  (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S)
+#define PMU_UPDATE_DIG_SYS_CLK_SEL_V  0x00000001U
+#define PMU_UPDATE_DIG_SYS_CLK_SEL_S  31
+
+/** PMU_IMM_HP_FUNC_ICG_REG register
+ *  need_des
+ */
+#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4)
+/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_UPDATE_DIG_ICG_FUNC_EN    (BIT(31))
+#define PMU_UPDATE_DIG_ICG_FUNC_EN_M  (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S)
+#define PMU_UPDATE_DIG_ICG_FUNC_EN_V  0x00000001U
+#define PMU_UPDATE_DIG_ICG_FUNC_EN_S  31
+
+/** PMU_IMM_HP_APB_ICG_REG register
+ *  need_des
+ */
+#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8)
+/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_UPDATE_DIG_ICG_APB_EN    (BIT(31))
+#define PMU_UPDATE_DIG_ICG_APB_EN_M  (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S)
+#define PMU_UPDATE_DIG_ICG_APB_EN_V  0x00000001U
+#define PMU_UPDATE_DIG_ICG_APB_EN_S  31
+
+/** PMU_IMM_MODEM_ICG_REG register
+ *  need_des
+ */
+#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc)
+/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_UPDATE_DIG_ICG_MODEM_EN    (BIT(31))
+#define PMU_UPDATE_DIG_ICG_MODEM_EN_M  (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S)
+#define PMU_UPDATE_DIG_ICG_MODEM_EN_V  0x00000001U
+#define PMU_UPDATE_DIG_ICG_MODEM_EN_S  31
+
+/** PMU_IMM_LP_ICG_REG register
+ *  need_des
+ */
+#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0)
+/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_LP_ROOTCLK_SEL    (BIT(30))
+#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M  (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S)
+#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V  0x00000001U
+#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S  30
+/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_LP_ROOTCLK_SEL    (BIT(31))
+#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M  (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S)
+#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V  0x00000001U
+#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S  31
+
+/** PMU_IMM_PAD_HOLD_ALL_REG register
+ *  need_des
+ */
+#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4)
+/** PMU_PAD_SLP_SEL : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_PAD_SLP_SEL    (BIT(0))
+#define PMU_PAD_SLP_SEL_M  (PMU_PAD_SLP_SEL_V << PMU_PAD_SLP_SEL_S)
+#define PMU_PAD_SLP_SEL_V  0x00000001U
+#define PMU_PAD_SLP_SEL_S  0
+/** PMU_LP_PAD_HOLD_ALL : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_PAD_HOLD_ALL    (BIT(1))
+#define PMU_LP_PAD_HOLD_ALL_M  (PMU_LP_PAD_HOLD_ALL_V << PMU_LP_PAD_HOLD_ALL_S)
+#define PMU_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_LP_PAD_HOLD_ALL_S  1
+/** PMU_HP_PAD_HOLD_ALL : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_PAD_HOLD_ALL    (BIT(2))
+#define PMU_HP_PAD_HOLD_ALL_M  (PMU_HP_PAD_HOLD_ALL_V << PMU_HP_PAD_HOLD_ALL_S)
+#define PMU_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_HP_PAD_HOLD_ALL_S  2
+/** PMU_TIE_HIGH_PAD_SLP_SEL : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_PAD_SLP_SEL    (BIT(26))
+#define PMU_TIE_HIGH_PAD_SLP_SEL_M  (PMU_TIE_HIGH_PAD_SLP_SEL_V << PMU_TIE_HIGH_PAD_SLP_SEL_S)
+#define PMU_TIE_HIGH_PAD_SLP_SEL_V  0x00000001U
+#define PMU_TIE_HIGH_PAD_SLP_SEL_S  26
+/** PMU_TIE_LOW_PAD_SLP_SEL : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_PAD_SLP_SEL    (BIT(27))
+#define PMU_TIE_LOW_PAD_SLP_SEL_M  (PMU_TIE_LOW_PAD_SLP_SEL_V << PMU_TIE_LOW_PAD_SLP_SEL_S)
+#define PMU_TIE_LOW_PAD_SLP_SEL_V  0x00000001U
+#define PMU_TIE_LOW_PAD_SLP_SEL_S  27
+/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL    (BIT(28))
+#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M  (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S)
+#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S  28
+/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_LP_PAD_HOLD_ALL    (BIT(29))
+#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M  (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S)
+#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S  29
+/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL    (BIT(30))
+#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M  (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S)
+#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S  30
+/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_HP_PAD_HOLD_ALL    (BIT(31))
+#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M  (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S)
+#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V  0x00000001U
+#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S  31
+
+/** PMU_IMM_I2C_ISO_REG register
+ *  need_des
+ */
+#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8)
+/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_HIGH_I2C_ISO_EN    (BIT(30))
+#define PMU_TIE_HIGH_I2C_ISO_EN_M  (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S)
+#define PMU_TIE_HIGH_I2C_ISO_EN_V  0x00000001U
+#define PMU_TIE_HIGH_I2C_ISO_EN_S  30
+/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_TIE_LOW_I2C_ISO_EN    (BIT(31))
+#define PMU_TIE_LOW_I2C_ISO_EN_M  (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S)
+#define PMU_TIE_LOW_I2C_ISO_EN_V  0x00000001U
+#define PMU_TIE_LOW_I2C_ISO_EN_S  31
+
+/** PMU_POWER_WAIT_TIMER0_REG register
+ *  need_des
+ */
+#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec)
+/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_HP_POWERDOWN_TIMER    0x000001FFU
+#define PMU_DG_HP_POWERDOWN_TIMER_M  (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S)
+#define PMU_DG_HP_POWERDOWN_TIMER_V  0x000001FFU
+#define PMU_DG_HP_POWERDOWN_TIMER_S  5
+/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_HP_POWERUP_TIMER    0x000001FFU
+#define PMU_DG_HP_POWERUP_TIMER_M  (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S)
+#define PMU_DG_HP_POWERUP_TIMER_V  0x000001FFU
+#define PMU_DG_HP_POWERUP_TIMER_S  14
+/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_HP_WAIT_TIMER    0x000001FFU
+#define PMU_DG_HP_WAIT_TIMER_M  (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S)
+#define PMU_DG_HP_WAIT_TIMER_V  0x000001FFU
+#define PMU_DG_HP_WAIT_TIMER_S  23
+
+/** PMU_POWER_WAIT_TIMER1_REG register
+ *  need_des
+ */
+#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0)
+/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_LP_POWERDOWN_TIMER    0x000001FFU
+#define PMU_DG_LP_POWERDOWN_TIMER_M  (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S)
+#define PMU_DG_LP_POWERDOWN_TIMER_V  0x000001FFU
+#define PMU_DG_LP_POWERDOWN_TIMER_S  5
+/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_LP_POWERUP_TIMER    0x000001FFU
+#define PMU_DG_LP_POWERUP_TIMER_M  (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S)
+#define PMU_DG_LP_POWERUP_TIMER_V  0x000001FFU
+#define PMU_DG_LP_POWERUP_TIMER_S  14
+/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255;
+ *  need_des
+ */
+#define PMU_DG_LP_WAIT_TIMER    0x000001FFU
+#define PMU_DG_LP_WAIT_TIMER_M  (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S)
+#define PMU_DG_LP_WAIT_TIMER_V  0x000001FFU
+#define PMU_DG_LP_WAIT_TIMER_S  23
+
+/** PMU_POWER_PD_TOP_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4)
+/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_RESET    (BIT(0))
+#define PMU_FORCE_TOP_RESET_M  (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S)
+#define PMU_FORCE_TOP_RESET_V  0x00000001U
+#define PMU_FORCE_TOP_RESET_S  0
+/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_ISO    (BIT(1))
+#define PMU_FORCE_TOP_ISO_M  (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S)
+#define PMU_FORCE_TOP_ISO_V  0x00000001U
+#define PMU_FORCE_TOP_ISO_S  1
+/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_PU    (BIT(2))
+#define PMU_FORCE_TOP_PU_M  (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S)
+#define PMU_FORCE_TOP_PU_V  0x00000001U
+#define PMU_FORCE_TOP_PU_S  2
+/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_NO_RESET    (BIT(3))
+#define PMU_FORCE_TOP_NO_RESET_M  (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S)
+#define PMU_FORCE_TOP_NO_RESET_V  0x00000001U
+#define PMU_FORCE_TOP_NO_RESET_S  3
+/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_NO_ISO    (BIT(4))
+#define PMU_FORCE_TOP_NO_ISO_M  (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S)
+#define PMU_FORCE_TOP_NO_ISO_V  0x00000001U
+#define PMU_FORCE_TOP_NO_ISO_S  4
+/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_TOP_PD    (BIT(5))
+#define PMU_FORCE_TOP_PD_M  (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S)
+#define PMU_FORCE_TOP_PD_V  0x00000001U
+#define PMU_FORCE_TOP_PD_S  5
+
+/** PMU_POWER_PD_CNNT_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_CNNT_CNTL_REG (DR_REG_PMU_BASE + 0xf8)
+/** PMU_FORCE_CNNT_RESET : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_RESET    (BIT(0))
+#define PMU_FORCE_CNNT_RESET_M  (PMU_FORCE_CNNT_RESET_V << PMU_FORCE_CNNT_RESET_S)
+#define PMU_FORCE_CNNT_RESET_V  0x00000001U
+#define PMU_FORCE_CNNT_RESET_S  0
+/** PMU_FORCE_CNNT_ISO : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_ISO    (BIT(1))
+#define PMU_FORCE_CNNT_ISO_M  (PMU_FORCE_CNNT_ISO_V << PMU_FORCE_CNNT_ISO_S)
+#define PMU_FORCE_CNNT_ISO_V  0x00000001U
+#define PMU_FORCE_CNNT_ISO_S  1
+/** PMU_FORCE_CNNT_PU : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_PU    (BIT(2))
+#define PMU_FORCE_CNNT_PU_M  (PMU_FORCE_CNNT_PU_V << PMU_FORCE_CNNT_PU_S)
+#define PMU_FORCE_CNNT_PU_V  0x00000001U
+#define PMU_FORCE_CNNT_PU_S  2
+/** PMU_FORCE_CNNT_NO_RESET : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_NO_RESET    (BIT(3))
+#define PMU_FORCE_CNNT_NO_RESET_M  (PMU_FORCE_CNNT_NO_RESET_V << PMU_FORCE_CNNT_NO_RESET_S)
+#define PMU_FORCE_CNNT_NO_RESET_V  0x00000001U
+#define PMU_FORCE_CNNT_NO_RESET_S  3
+/** PMU_FORCE_CNNT_NO_ISO : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_NO_ISO    (BIT(4))
+#define PMU_FORCE_CNNT_NO_ISO_M  (PMU_FORCE_CNNT_NO_ISO_V << PMU_FORCE_CNNT_NO_ISO_S)
+#define PMU_FORCE_CNNT_NO_ISO_V  0x00000001U
+#define PMU_FORCE_CNNT_NO_ISO_S  4
+/** PMU_FORCE_CNNT_PD : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_CNNT_PD    (BIT(5))
+#define PMU_FORCE_CNNT_PD_M  (PMU_FORCE_CNNT_PD_V << PMU_FORCE_CNNT_PD_S)
+#define PMU_FORCE_CNNT_PD_V  0x00000001U
+#define PMU_FORCE_CNNT_PD_S  5
+
+/** PMU_POWER_PD_HPMEM_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_HPMEM_CNTL_REG (DR_REG_PMU_BASE + 0xfc)
+/** PMU_FORCE_HP_MEM_RESET : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_RESET    (BIT(0))
+#define PMU_FORCE_HP_MEM_RESET_M  (PMU_FORCE_HP_MEM_RESET_V << PMU_FORCE_HP_MEM_RESET_S)
+#define PMU_FORCE_HP_MEM_RESET_V  0x00000001U
+#define PMU_FORCE_HP_MEM_RESET_S  0
+/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_ISO    (BIT(1))
+#define PMU_FORCE_HP_MEM_ISO_M  (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S)
+#define PMU_FORCE_HP_MEM_ISO_V  0x00000001U
+#define PMU_FORCE_HP_MEM_ISO_S  1
+/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_PU    (BIT(2))
+#define PMU_FORCE_HP_MEM_PU_M  (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S)
+#define PMU_FORCE_HP_MEM_PU_V  0x00000001U
+#define PMU_FORCE_HP_MEM_PU_S  2
+/** PMU_FORCE_HP_MEM_NO_RESET : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_NO_RESET    (BIT(3))
+#define PMU_FORCE_HP_MEM_NO_RESET_M  (PMU_FORCE_HP_MEM_NO_RESET_V << PMU_FORCE_HP_MEM_NO_RESET_S)
+#define PMU_FORCE_HP_MEM_NO_RESET_V  0x00000001U
+#define PMU_FORCE_HP_MEM_NO_RESET_S  3
+/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_NO_ISO    (BIT(4))
+#define PMU_FORCE_HP_MEM_NO_ISO_M  (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S)
+#define PMU_FORCE_HP_MEM_NO_ISO_V  0x00000001U
+#define PMU_FORCE_HP_MEM_NO_ISO_S  4
+/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_MEM_PD    (BIT(5))
+#define PMU_FORCE_HP_MEM_PD_M  (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S)
+#define PMU_FORCE_HP_MEM_PD_V  0x00000001U
+#define PMU_FORCE_HP_MEM_PD_S  5
+
+/** PMU_POWER_PD_TOP_MASK_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_TOP_MASK_REG (DR_REG_PMU_BASE + 0x100)
+/** PMU_XPD_TOP_MASK : R/W; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_TOP_MASK    0x0000001FU
+#define PMU_XPD_TOP_MASK_M  (PMU_XPD_TOP_MASK_V << PMU_XPD_TOP_MASK_S)
+#define PMU_XPD_TOP_MASK_V  0x0000001FU
+#define PMU_XPD_TOP_MASK_S  0
+/** PMU_PD_TOP_MASK : R/W; bitpos: [31:27]; default: 0;
+ *  need_des
+ */
+#define PMU_PD_TOP_MASK    0x0000001FU
+#define PMU_PD_TOP_MASK_M  (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S)
+#define PMU_PD_TOP_MASK_V  0x0000001FU
+#define PMU_PD_TOP_MASK_S  27
+
+/** PMU_POWER_PD_CNNT_MASK_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_CNNT_MASK_REG (DR_REG_PMU_BASE + 0x104)
+/** PMU_XPD_CNNT_MASK : R/W; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_CNNT_MASK    0x0000001FU
+#define PMU_XPD_CNNT_MASK_M  (PMU_XPD_CNNT_MASK_V << PMU_XPD_CNNT_MASK_S)
+#define PMU_XPD_CNNT_MASK_V  0x0000001FU
+#define PMU_XPD_CNNT_MASK_S  0
+/** PMU_PD_CNNT_MASK : R/W; bitpos: [31:27]; default: 0;
+ *  need_des
+ */
+#define PMU_PD_CNNT_MASK    0x0000001FU
+#define PMU_PD_CNNT_MASK_M  (PMU_PD_CNNT_MASK_V << PMU_PD_CNNT_MASK_S)
+#define PMU_PD_CNNT_MASK_V  0x0000001FU
+#define PMU_PD_CNNT_MASK_S  27
+
+/** PMU_POWER_PD_HPMEM_MASK_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_HPMEM_MASK_REG (DR_REG_PMU_BASE + 0x108)
+/** PMU_XPD_HP_MEM_MASK : R/W; bitpos: [5:0]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_HP_MEM_MASK    0x0000003FU
+#define PMU_XPD_HP_MEM_MASK_M  (PMU_XPD_HP_MEM_MASK_V << PMU_XPD_HP_MEM_MASK_S)
+#define PMU_XPD_HP_MEM_MASK_V  0x0000003FU
+#define PMU_XPD_HP_MEM_MASK_S  0
+/** PMU_PD_HP_MEM_MASK : R/W; bitpos: [31:26]; default: 0;
+ *  need_des
+ */
+#define PMU_PD_HP_MEM_MASK    0x0000003FU
+#define PMU_PD_HP_MEM_MASK_M  (PMU_PD_HP_MEM_MASK_V << PMU_PD_HP_MEM_MASK_S)
+#define PMU_PD_HP_MEM_MASK_V  0x0000003FU
+#define PMU_PD_HP_MEM_MASK_S  26
+
+/** PMU_POWER_DCDC_SWITCH_REG register
+ *  need_des
+ */
+#define PMU_POWER_DCDC_SWITCH_REG (DR_REG_PMU_BASE + 0x10c)
+/** PMU_FORCE_DCDC_SWITCH_PU : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_DCDC_SWITCH_PU    (BIT(0))
+#define PMU_FORCE_DCDC_SWITCH_PU_M  (PMU_FORCE_DCDC_SWITCH_PU_V << PMU_FORCE_DCDC_SWITCH_PU_S)
+#define PMU_FORCE_DCDC_SWITCH_PU_V  0x00000001U
+#define PMU_FORCE_DCDC_SWITCH_PU_S  0
+/** PMU_FORCE_DCDC_SWITCH_PD : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_DCDC_SWITCH_PD    (BIT(1))
+#define PMU_FORCE_DCDC_SWITCH_PD_M  (PMU_FORCE_DCDC_SWITCH_PD_V << PMU_FORCE_DCDC_SWITCH_PD_S)
+#define PMU_FORCE_DCDC_SWITCH_PD_V  0x00000001U
+#define PMU_FORCE_DCDC_SWITCH_PD_S  1
+
+/** PMU_POWER_PD_LPPERI_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x110)
+/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_RESET    (BIT(0))
+#define PMU_FORCE_LP_PERI_RESET_M  (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S)
+#define PMU_FORCE_LP_PERI_RESET_V  0x00000001U
+#define PMU_FORCE_LP_PERI_RESET_S  0
+/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_ISO    (BIT(1))
+#define PMU_FORCE_LP_PERI_ISO_M  (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S)
+#define PMU_FORCE_LP_PERI_ISO_V  0x00000001U
+#define PMU_FORCE_LP_PERI_ISO_S  1
+/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_PU    (BIT(2))
+#define PMU_FORCE_LP_PERI_PU_M  (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S)
+#define PMU_FORCE_LP_PERI_PU_V  0x00000001U
+#define PMU_FORCE_LP_PERI_PU_S  2
+/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_NO_RESET    (BIT(3))
+#define PMU_FORCE_LP_PERI_NO_RESET_M  (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S)
+#define PMU_FORCE_LP_PERI_NO_RESET_V  0x00000001U
+#define PMU_FORCE_LP_PERI_NO_RESET_S  3
+/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_NO_ISO    (BIT(4))
+#define PMU_FORCE_LP_PERI_NO_ISO_M  (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S)
+#define PMU_FORCE_LP_PERI_NO_ISO_V  0x00000001U
+#define PMU_FORCE_LP_PERI_NO_ISO_S  4
+/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_LP_PERI_PD    (BIT(5))
+#define PMU_FORCE_LP_PERI_PD_M  (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S)
+#define PMU_FORCE_LP_PERI_PD_V  0x00000001U
+#define PMU_FORCE_LP_PERI_PD_S  5
+
+/** PMU_POWER_PD_LPPERI_MASK_REG register
+ *  need_des
+ */
+#define PMU_POWER_PD_LPPERI_MASK_REG (DR_REG_PMU_BASE + 0x114)
+/** PMU_XPD_LP_PERI_MASK : R/W; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_LP_PERI_MASK    0x0000001FU
+#define PMU_XPD_LP_PERI_MASK_M  (PMU_XPD_LP_PERI_MASK_V << PMU_XPD_LP_PERI_MASK_S)
+#define PMU_XPD_LP_PERI_MASK_V  0x0000001FU
+#define PMU_XPD_LP_PERI_MASK_S  0
+/** PMU_PD_LP_PERI_MASK : R/W; bitpos: [31:27]; default: 0;
+ *  need_des
+ */
+#define PMU_PD_LP_PERI_MASK    0x0000001FU
+#define PMU_PD_LP_PERI_MASK_M  (PMU_PD_LP_PERI_MASK_V << PMU_PD_LP_PERI_MASK_S)
+#define PMU_PD_LP_PERI_MASK_V  0x0000001FU
+#define PMU_PD_LP_PERI_MASK_S  27
+
+/** PMU_POWER_HP_PAD_REG register
+ *  need_des
+ */
+#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118)
+/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_PAD_NO_ISO_ALL    (BIT(0))
+#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M  (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S)
+#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V  0x00000001U
+#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S  0
+/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_FORCE_HP_PAD_ISO_ALL    (BIT(1))
+#define PMU_FORCE_HP_PAD_ISO_ALL_M  (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S)
+#define PMU_FORCE_HP_PAD_ISO_ALL_V  0x00000001U
+#define PMU_FORCE_HP_PAD_ISO_ALL_S  1
+
+/** PMU_POWER_CK_WAIT_CNTL_REG register
+ *  need_des
+ */
+#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c)
+/** PMU_PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256;
+ *  need_des
+ */
+#define PMU_PMU_WAIT_XTL_STABLE    0x0000FFFFU
+#define PMU_PMU_WAIT_XTL_STABLE_M  (PMU_PMU_WAIT_XTL_STABLE_V << PMU_PMU_WAIT_XTL_STABLE_S)
+#define PMU_PMU_WAIT_XTL_STABLE_V  0x0000FFFFU
+#define PMU_PMU_WAIT_XTL_STABLE_S  0
+/** PMU_PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256;
+ *  need_des
+ */
+#define PMU_PMU_WAIT_PLL_STABLE    0x0000FFFFU
+#define PMU_PMU_WAIT_PLL_STABLE_M  (PMU_PMU_WAIT_PLL_STABLE_V << PMU_PMU_WAIT_PLL_STABLE_S)
+#define PMU_PMU_WAIT_PLL_STABLE_V  0x0000FFFFU
+#define PMU_PMU_WAIT_PLL_STABLE_S  16
+
+/** PMU_SLP_WAKEUP_CNTL0_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120)
+/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_REQ    (BIT(31))
+#define PMU_SLEEP_REQ_M  (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S)
+#define PMU_SLEEP_REQ_V  0x00000001U
+#define PMU_SLEEP_REQ_S  31
+
+/** PMU_SLP_WAKEUP_CNTL1_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124)
+/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_REJECT_ENA    0x7FFFFFFFU
+#define PMU_SLEEP_REJECT_ENA_M  (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S)
+#define PMU_SLEEP_REJECT_ENA_V  0x7FFFFFFFU
+#define PMU_SLEEP_REJECT_ENA_S  0
+/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SLP_REJECT_EN    (BIT(31))
+#define PMU_SLP_REJECT_EN_M  (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S)
+#define PMU_SLP_REJECT_EN_V  0x00000001U
+#define PMU_SLP_REJECT_EN_S  31
+
+/** PMU_SLP_WAKEUP_CNTL2_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128)
+/** PMU_WAKEUP_ENA : R/W; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_WAKEUP_ENA    0x7FFFFFFFU
+#define PMU_WAKEUP_ENA_M  (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S)
+#define PMU_WAKEUP_ENA_V  0x7FFFFFFFU
+#define PMU_WAKEUP_ENA_S  0
+
+/** PMU_SLP_WAKEUP_CNTL3_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c)
+/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_MIN_SLP_VAL    0x000000FFU
+#define PMU_LP_MIN_SLP_VAL_M  (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S)
+#define PMU_LP_MIN_SLP_VAL_V  0x000000FFU
+#define PMU_LP_MIN_SLP_VAL_S  0
+/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_MIN_SLP_VAL    0x000000FFU
+#define PMU_HP_MIN_SLP_VAL_M  (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S)
+#define PMU_HP_MIN_SLP_VAL_V  0x000000FFU
+#define PMU_HP_MIN_SLP_VAL_S  8
+/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_PRT_SEL    0x00000003U
+#define PMU_SLEEP_PRT_SEL_M  (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S)
+#define PMU_SLEEP_PRT_SEL_V  0x00000003U
+#define PMU_SLEEP_PRT_SEL_S  16
+
+/** PMU_SLP_WAKEUP_CNTL4_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130)
+/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SLP_REJECT_CAUSE_CLR    (BIT(31))
+#define PMU_SLP_REJECT_CAUSE_CLR_M  (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S)
+#define PMU_SLP_REJECT_CAUSE_CLR_V  0x00000001U
+#define PMU_SLP_REJECT_CAUSE_CLR_S  31
+
+/** PMU_SLP_WAKEUP_CNTL5_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134)
+/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128;
+ *  need_des
+ */
+#define PMU_MODEM_WAIT_TARGET    0x000FFFFFU
+#define PMU_MODEM_WAIT_TARGET_M  (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S)
+#define PMU_MODEM_WAIT_TARGET_V  0x000FFFFFU
+#define PMU_MODEM_WAIT_TARGET_S  0
+/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_ANA_WAIT_TARGET    0x000000FFU
+#define PMU_LP_ANA_WAIT_TARGET_M  (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S)
+#define PMU_LP_ANA_WAIT_TARGET_V  0x000000FFU
+#define PMU_LP_ANA_WAIT_TARGET_S  24
+
+/** PMU_SLP_WAKEUP_CNTL6_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138)
+/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_WAIT    0x000FFFFFU
+#define PMU_SOC_WAKEUP_WAIT_M  (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S)
+#define PMU_SOC_WAKEUP_WAIT_V  0x000FFFFFU
+#define PMU_SOC_WAKEUP_WAIT_S  0
+/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_WAIT_CFG    0x00000003U
+#define PMU_SOC_WAKEUP_WAIT_CFG_M  (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S)
+#define PMU_SOC_WAKEUP_WAIT_CFG_V  0x00000003U
+#define PMU_SOC_WAKEUP_WAIT_CFG_S  30
+
+/** PMU_SLP_WAKEUP_CNTL7_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c)
+/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1;
+ *  need_des
+ */
+#define PMU_ANA_WAIT_TARGET    0x0000FFFFU
+#define PMU_ANA_WAIT_TARGET_M  (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S)
+#define PMU_ANA_WAIT_TARGET_V  0x0000FFFFU
+#define PMU_ANA_WAIT_TARGET_S  16
+
+/** PMU_SLP_WAKEUP_CNTL8_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_CNTL8_REG (DR_REG_PMU_BASE + 0x140)
+/** PMU_LP_LITE_WAKEUP_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_LITE_WAKEUP_ENA    (BIT(31))
+#define PMU_LP_LITE_WAKEUP_ENA_M  (PMU_LP_LITE_WAKEUP_ENA_V << PMU_LP_LITE_WAKEUP_ENA_S)
+#define PMU_LP_LITE_WAKEUP_ENA_V  0x00000001U
+#define PMU_LP_LITE_WAKEUP_ENA_S  31
+
+/** PMU_SLP_WAKEUP_STATUS0_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x144)
+/** PMU_WAKEUP_CAUSE : RO; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_WAKEUP_CAUSE    0x7FFFFFFFU
+#define PMU_WAKEUP_CAUSE_M  (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S)
+#define PMU_WAKEUP_CAUSE_V  0x7FFFFFFFU
+#define PMU_WAKEUP_CAUSE_S  0
+
+/** PMU_SLP_WAKEUP_STATUS1_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x148)
+/** PMU_REJECT_CAUSE : RO; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_REJECT_CAUSE    0x7FFFFFFFU
+#define PMU_REJECT_CAUSE_M  (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S)
+#define PMU_REJECT_CAUSE_V  0x7FFFFFFFU
+#define PMU_REJECT_CAUSE_S  0
+
+/** PMU_SLP_WAKEUP_STATUS2_REG register
+ *  need_des
+ */
+#define PMU_SLP_WAKEUP_STATUS2_REG (DR_REG_PMU_BASE + 0x14c)
+/** PMU_LP_LITE_WAKEUP_CAUSE : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_LITE_WAKEUP_CAUSE    (BIT(31))
+#define PMU_LP_LITE_WAKEUP_CAUSE_M  (PMU_LP_LITE_WAKEUP_CAUSE_V << PMU_LP_LITE_WAKEUP_CAUSE_S)
+#define PMU_LP_LITE_WAKEUP_CAUSE_V  0x00000001U
+#define PMU_LP_LITE_WAKEUP_CAUSE_S  31
+
+/** PMU_HP_CK_POWERON_REG register
+ *  need_des
+ */
+#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x150)
+/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50;
+ *  need_des
+ */
+#define PMU_I2C_POR_WAIT_TARGET    0x000000FFU
+#define PMU_I2C_POR_WAIT_TARGET_M  (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S)
+#define PMU_I2C_POR_WAIT_TARGET_V  0x000000FFU
+#define PMU_I2C_POR_WAIT_TARGET_S  0
+
+/** PMU_HP_CK_CNTL_REG register
+ *  need_des
+ */
+#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x154)
+/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10;
+ *  need_des
+ */
+#define PMU_MODIFY_ICG_CNTL_WAIT    0x000000FFU
+#define PMU_MODIFY_ICG_CNTL_WAIT_M  (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S)
+#define PMU_MODIFY_ICG_CNTL_WAIT_V  0x000000FFU
+#define PMU_MODIFY_ICG_CNTL_WAIT_S  0
+/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10;
+ *  need_des
+ */
+#define PMU_SWITCH_ICG_CNTL_WAIT    0x000000FFU
+#define PMU_SWITCH_ICG_CNTL_WAIT_M  (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S)
+#define PMU_SWITCH_ICG_CNTL_WAIT_V  0x000000FFU
+#define PMU_SWITCH_ICG_CNTL_WAIT_S  8
+
+/** PMU_POR_STATUS_REG register
+ *  need_des
+ */
+#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x158)
+/** PMU_POR_DONE : RO; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_POR_DONE    (BIT(31))
+#define PMU_POR_DONE_M  (PMU_POR_DONE_V << PMU_POR_DONE_S)
+#define PMU_POR_DONE_V  0x00000001U
+#define PMU_POR_DONE_S  31
+
+/** PMU_RF_PWC_REG register
+ *  need_des
+ */
+#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x15c)
+/** PMU_MSPI_PHY_XPD : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_MSPI_PHY_XPD    (BIT(24))
+#define PMU_MSPI_PHY_XPD_M  (PMU_MSPI_PHY_XPD_V << PMU_MSPI_PHY_XPD_S)
+#define PMU_MSPI_PHY_XPD_V  0x00000001U
+#define PMU_MSPI_PHY_XPD_S  24
+/** PMU_SDIO_PLL_XPD : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_SDIO_PLL_XPD    (BIT(25))
+#define PMU_SDIO_PLL_XPD_M  (PMU_SDIO_PLL_XPD_V << PMU_SDIO_PLL_XPD_S)
+#define PMU_SDIO_PLL_XPD_V  0x00000001U
+#define PMU_SDIO_PLL_XPD_S  25
+/** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_PERIF_I2C_RSTB    (BIT(26))
+#define PMU_PERIF_I2C_RSTB_M  (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S)
+#define PMU_PERIF_I2C_RSTB_V  0x00000001U
+#define PMU_PERIF_I2C_RSTB_S  26
+/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1;
+ *  need_des
+ */
+#define PMU_XPD_PERIF_I2C    (BIT(27))
+#define PMU_XPD_PERIF_I2C_M  (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S)
+#define PMU_XPD_PERIF_I2C_V  0x00000001U
+#define PMU_XPD_PERIF_I2C_S  27
+/** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_TXRF_I2C    (BIT(28))
+#define PMU_XPD_TXRF_I2C_M  (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S)
+#define PMU_XPD_TXRF_I2C_V  0x00000001U
+#define PMU_XPD_TXRF_I2C_S  28
+/** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_RFRX_PBUS    (BIT(29))
+#define PMU_XPD_RFRX_PBUS_M  (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S)
+#define PMU_XPD_RFRX_PBUS_V  0x00000001U
+#define PMU_XPD_RFRX_PBUS_S  29
+/** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_XPD_CKGEN_I2C    (BIT(30))
+#define PMU_XPD_CKGEN_I2C_M  (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S)
+#define PMU_XPD_CKGEN_I2C_V  0x00000001U
+#define PMU_XPD_CKGEN_I2C_S  30
+
+/** PMU_BACKUP_CFG_REG register
+ *  need_des
+ */
+#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x160)
+/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define PMU_BACKUP_SYS_CLK_NO_DIV    (BIT(31))
+#define PMU_BACKUP_SYS_CLK_NO_DIV_M  (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S)
+#define PMU_BACKUP_SYS_CLK_NO_DIV_V  0x00000001U
+#define PMU_BACKUP_SYS_CLK_NO_DIV_S  31
+
+/** PMU_INT_RAW_REG register
+ *  need_des
+ */
+#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x164)
+/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_M  (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_M  (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_M  (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_M  (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_M  (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_M  (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_M  (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_M  (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_M  (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_M  (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_M  (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_M  (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_S  25
+/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_EXC_INT_RAW    (BIT(27))
+#define PMU_LP_CPU_EXC_INT_RAW_M  (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S)
+#define PMU_LP_CPU_EXC_INT_RAW_V  0x00000001U
+#define PMU_LP_CPU_EXC_INT_RAW_S  27
+/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_SDIO_IDLE_INT_RAW    (BIT(28))
+#define PMU_SDIO_IDLE_INT_RAW_M  (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S)
+#define PMU_SDIO_IDLE_INT_RAW_V  0x00000001U
+#define PMU_SDIO_IDLE_INT_RAW_S  28
+/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SW_INT_RAW    (BIT(29))
+#define PMU_SW_INT_RAW_M  (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S)
+#define PMU_SW_INT_RAW_V  0x00000001U
+#define PMU_SW_INT_RAW_S  29
+/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_SLEEP_REJECT_INT_RAW    (BIT(30))
+#define PMU_SOC_SLEEP_REJECT_INT_RAW_M  (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S)
+#define PMU_SOC_SLEEP_REJECT_INT_RAW_V  0x00000001U
+#define PMU_SOC_SLEEP_REJECT_INT_RAW_S  30
+/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_INT_RAW    (BIT(31))
+#define PMU_SOC_WAKEUP_INT_RAW_M  (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S)
+#define PMU_SOC_WAKEUP_INT_RAW_V  0x00000001U
+#define PMU_SOC_WAKEUP_INT_RAW_S  31
+
+/** PMU_HP_INT_ST_REG register
+ *  need_des
+ */
+#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x168)
+/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_M  (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_M  (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_M  (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_M  (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_M  (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_M  (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_M  (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_M  (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_M  (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_M  (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_M  (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_M  (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_S  25
+/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_EXC_INT_ST    (BIT(27))
+#define PMU_LP_CPU_EXC_INT_ST_M  (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S)
+#define PMU_LP_CPU_EXC_INT_ST_V  0x00000001U
+#define PMU_LP_CPU_EXC_INT_ST_S  27
+/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_SDIO_IDLE_INT_ST    (BIT(28))
+#define PMU_SDIO_IDLE_INT_ST_M  (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S)
+#define PMU_SDIO_IDLE_INT_ST_V  0x00000001U
+#define PMU_SDIO_IDLE_INT_ST_S  28
+/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SW_INT_ST    (BIT(29))
+#define PMU_SW_INT_ST_M  (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S)
+#define PMU_SW_INT_ST_V  0x00000001U
+#define PMU_SW_INT_ST_S  29
+/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_SLEEP_REJECT_INT_ST    (BIT(30))
+#define PMU_SOC_SLEEP_REJECT_INT_ST_M  (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S)
+#define PMU_SOC_SLEEP_REJECT_INT_ST_V  0x00000001U
+#define PMU_SOC_SLEEP_REJECT_INT_ST_S  30
+/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_INT_ST    (BIT(31))
+#define PMU_SOC_WAKEUP_INT_ST_M  (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S)
+#define PMU_SOC_WAKEUP_INT_ST_V  0x00000001U
+#define PMU_SOC_WAKEUP_INT_ST_S  31
+
+/** PMU_HP_INT_ENA_REG register
+ *  need_des
+ */
+#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x16c)
+/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_M  (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_M  (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_M  (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_M  (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_M  (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_M  (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_M  (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_M  (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_M  (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_M  (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_M  (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_M  (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_S  25
+/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_EXC_INT_ENA    (BIT(27))
+#define PMU_LP_CPU_EXC_INT_ENA_M  (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S)
+#define PMU_LP_CPU_EXC_INT_ENA_V  0x00000001U
+#define PMU_LP_CPU_EXC_INT_ENA_S  27
+/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_SDIO_IDLE_INT_ENA    (BIT(28))
+#define PMU_SDIO_IDLE_INT_ENA_M  (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S)
+#define PMU_SDIO_IDLE_INT_ENA_V  0x00000001U
+#define PMU_SDIO_IDLE_INT_ENA_S  28
+/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SW_INT_ENA    (BIT(29))
+#define PMU_SW_INT_ENA_M  (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S)
+#define PMU_SW_INT_ENA_V  0x00000001U
+#define PMU_SW_INT_ENA_S  29
+/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_SLEEP_REJECT_INT_ENA    (BIT(30))
+#define PMU_SOC_SLEEP_REJECT_INT_ENA_M  (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S)
+#define PMU_SOC_SLEEP_REJECT_INT_ENA_V  0x00000001U
+#define PMU_SOC_SLEEP_REJECT_INT_ENA_S  30
+/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_INT_ENA    (BIT(31))
+#define PMU_SOC_WAKEUP_INT_ENA_M  (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S)
+#define PMU_SOC_WAKEUP_INT_ENA_V  0x00000001U
+#define PMU_SOC_WAKEUP_INT_ENA_S  31
+
+/** PMU_HP_INT_CLR_REG register
+ *  need_des
+ */
+#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x170)
+/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_M  (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_M  (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_M  (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_M  (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_M  (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_M  (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_M  (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_M  (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_M  (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_M  (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_M  (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_M  (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_S  25
+/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_EXC_INT_CLR    (BIT(27))
+#define PMU_LP_CPU_EXC_INT_CLR_M  (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S)
+#define PMU_LP_CPU_EXC_INT_CLR_V  0x00000001U
+#define PMU_LP_CPU_EXC_INT_CLR_S  27
+/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_SDIO_IDLE_INT_CLR    (BIT(28))
+#define PMU_SDIO_IDLE_INT_CLR_M  (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S)
+#define PMU_SDIO_IDLE_INT_CLR_V  0x00000001U
+#define PMU_SDIO_IDLE_INT_CLR_S  28
+/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SW_INT_CLR    (BIT(29))
+#define PMU_SW_INT_CLR_M  (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S)
+#define PMU_SW_INT_CLR_V  0x00000001U
+#define PMU_SW_INT_CLR_S  29
+/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_SLEEP_REJECT_INT_CLR    (BIT(30))
+#define PMU_SOC_SLEEP_REJECT_INT_CLR_M  (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S)
+#define PMU_SOC_SLEEP_REJECT_INT_CLR_V  0x00000001U
+#define PMU_SOC_SLEEP_REJECT_INT_CLR_S  30
+/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_SOC_WAKEUP_INT_CLR    (BIT(31))
+#define PMU_SOC_WAKEUP_INT_CLR_M  (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S)
+#define PMU_SOC_WAKEUP_INT_CLR_V  0x00000001U
+#define PMU_SOC_WAKEUP_INT_CLR_S  31
+
+/** PMU_LP_INT_RAW_REG register
+ *  need_des
+ */
+#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x174)
+/** PMU_LP_CPU_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW    (BIT(13))
+#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_M  (PMU_LP_CPU_SLEEP_REJECT_INT_RAW_V << PMU_LP_CPU_SLEEP_REJECT_INT_RAW_S)
+#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_V  0x00000001U
+#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_S  13
+/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_M  (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_M  (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_M  (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_M  (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_M  (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_M  (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_M  (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_M  (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_M  (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_M  (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_M  (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_M  (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_S  25
+/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_INT_RAW    (BIT(26))
+#define PMU_LP_CPU_WAKEUP_INT_RAW_M  (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S)
+#define PMU_LP_CPU_WAKEUP_INT_RAW_V  0x00000001U
+#define PMU_LP_CPU_WAKEUP_INT_RAW_S  26
+/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW    (BIT(27))
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S  27
+/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW    (BIT(28))
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S  28
+/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW    (BIT(29))
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S  29
+/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW    (BIT(30))
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S  30
+/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SW_TRIGGER_INT_RAW    (BIT(31))
+#define PMU_HP_SW_TRIGGER_INT_RAW_M  (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S)
+#define PMU_HP_SW_TRIGGER_INT_RAW_V  0x00000001U
+#define PMU_HP_SW_TRIGGER_INT_RAW_S  31
+
+/** PMU_LP_INT_ST_REG register
+ *  need_des
+ */
+#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x178)
+/** PMU_LP_CPU_SLEEP_REJECT_INT_ST : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ST    (BIT(13))
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_M  (PMU_LP_CPU_SLEEP_REJECT_INT_ST_V << PMU_LP_CPU_SLEEP_REJECT_INT_ST_S)
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_V  0x00000001U
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_S  13
+/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_M  (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_M  (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_M  (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_M  (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_M  (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_M  (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_M  (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_M  (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_M  (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_M  (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_M  (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_M  (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_S  25
+/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_INT_ST    (BIT(26))
+#define PMU_LP_CPU_WAKEUP_INT_ST_M  (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S)
+#define PMU_LP_CPU_WAKEUP_INT_ST_V  0x00000001U
+#define PMU_LP_CPU_WAKEUP_INT_ST_S  26
+/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST    (BIT(27))
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S  27
+/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST    (BIT(28))
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S  28
+/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST    (BIT(29))
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S  29
+/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST    (BIT(30))
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S  30
+/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SW_TRIGGER_INT_ST    (BIT(31))
+#define PMU_HP_SW_TRIGGER_INT_ST_M  (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S)
+#define PMU_HP_SW_TRIGGER_INT_ST_V  0x00000001U
+#define PMU_HP_SW_TRIGGER_INT_ST_S  31
+
+/** PMU_LP_INT_ENA_REG register
+ *  need_des
+ */
+#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x17c)
+/** PMU_LP_CPU_SLEEP_REJECT_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA    (BIT(13))
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_M  (PMU_LP_CPU_SLEEP_REJECT_INT_ENA_V << PMU_LP_CPU_SLEEP_REJECT_INT_ENA_S)
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_V  0x00000001U
+#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_S  13
+/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_M  (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_M  (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_M  (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_M  (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_M  (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_M  (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_M  (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_M  (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_M  (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_M  (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_M  (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_M  (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_S  25
+/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_INT_ENA    (BIT(26))
+#define PMU_LP_CPU_WAKEUP_INT_ENA_M  (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S)
+#define PMU_LP_CPU_WAKEUP_INT_ENA_V  0x00000001U
+#define PMU_LP_CPU_WAKEUP_INT_ENA_S  26
+/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA    (BIT(27))
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S  27
+/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA    (BIT(28))
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S  28
+/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA    (BIT(29))
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S  29
+/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA    (BIT(30))
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S  30
+/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SW_TRIGGER_INT_ENA    (BIT(31))
+#define PMU_HP_SW_TRIGGER_INT_ENA_M  (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S)
+#define PMU_HP_SW_TRIGGER_INT_ENA_V  0x00000001U
+#define PMU_HP_SW_TRIGGER_INT_ENA_S  31
+
+/** PMU_LP_INT_CLR_REG register
+ *  need_des
+ */
+#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x180)
+/** PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR    (BIT(13))
+#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_M  (PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_V << PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_S)
+#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_V  0x00000001U
+#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_S  13
+/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  reg_0p1a_0_counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR    (BIT(14))
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_M  (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_S  14
+/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR    (BIT(15))
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_M  (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_S  15
+/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  reg_0p1a_0 counter after xpd reach target0
+ */
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR    (BIT(16))
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_M  (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_S  16
+/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  reg_0p1a_1_counter after xpd reach target1
+ */
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR    (BIT(17))
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_M  (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_S)
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_S  17
+/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR    (BIT(18))
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_M  (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_S  18
+/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR    (BIT(19))
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_M  (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_S  19
+/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  reg_0p2a_0 counter after xpd reach target0
+ */
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR    (BIT(20))
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_M  (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_S  20
+/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  reg_0p2a_1_counter after xpd reach target1
+ */
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR    (BIT(21))
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_M  (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_S)
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_S  21
+/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  reg_0p3a_0 counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR    (BIT(22))
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_M  (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_S  22
+/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR    (BIT(23))
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_M  (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_S  23
+/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  reg_0p3a_0_counter after xpd reach target0
+ */
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR    (BIT(24))
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_M  (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_S  24
+/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  reg_0p3a_1_counter after xpd reach target1
+ */
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR    (BIT(25))
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_M  (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_S)
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_V  0x00000001U
+#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_S  25
+/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_INT_CLR    (BIT(26))
+#define PMU_LP_CPU_WAKEUP_INT_CLR_M  (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S)
+#define PMU_LP_CPU_WAKEUP_INT_CLR_V  0x00000001U
+#define PMU_LP_CPU_WAKEUP_INT_CLR_S  26
+/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR    (BIT(27))
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S  27
+/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR    (BIT(28))
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S  28
+/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR    (BIT(29))
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S)
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V  0x00000001U
+#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S  29
+/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR    (BIT(30))
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S)
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V  0x00000001U
+#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S  30
+/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_SW_TRIGGER_INT_CLR    (BIT(31))
+#define PMU_HP_SW_TRIGGER_INT_CLR_M  (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S)
+#define PMU_HP_SW_TRIGGER_INT_CLR_V  0x00000001U
+#define PMU_HP_SW_TRIGGER_INT_CLR_S  31
+
+/** PMU_LP_CPU_PWR0_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x184)
+/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAITI_RDY    (BIT(0))
+#define PMU_LP_CPU_WAITI_RDY_M  (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S)
+#define PMU_LP_CPU_WAITI_RDY_V  0x00000001U
+#define PMU_LP_CPU_WAITI_RDY_S  0
+/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_STALL_RDY    (BIT(1))
+#define PMU_LP_CPU_STALL_RDY_M  (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S)
+#define PMU_LP_CPU_STALL_RDY_V  0x00000001U
+#define PMU_LP_CPU_STALL_RDY_S  1
+/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_FORCE_STALL    (BIT(18))
+#define PMU_LP_CPU_FORCE_STALL_M  (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S)
+#define PMU_LP_CPU_FORCE_STALL_V  0x00000001U
+#define PMU_LP_CPU_FORCE_STALL_S  18
+/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_WAITI_FLAG_EN    (BIT(19))
+#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M  (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S)
+#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V  0x00000001U
+#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S  19
+/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_STALL_FLAG_EN    (BIT(20))
+#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M  (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S)
+#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V  0x00000001U
+#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S  20
+/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_STALL_WAIT    0x000000FFU
+#define PMU_LP_CPU_SLP_STALL_WAIT_M  (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S)
+#define PMU_LP_CPU_SLP_STALL_WAIT_V  0x000000FFU
+#define PMU_LP_CPU_SLP_STALL_WAIT_S  21
+/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_STALL_EN    (BIT(29))
+#define PMU_LP_CPU_SLP_STALL_EN_M  (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S)
+#define PMU_LP_CPU_SLP_STALL_EN_V  0x00000001U
+#define PMU_LP_CPU_SLP_STALL_EN_S  29
+/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_RESET_EN    (BIT(30))
+#define PMU_LP_CPU_SLP_RESET_EN_M  (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S)
+#define PMU_LP_CPU_SLP_RESET_EN_V  0x00000001U
+#define PMU_LP_CPU_SLP_RESET_EN_S  30
+/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLP_BYPASS_INTR_EN    (BIT(31))
+#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M  (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S)
+#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V  0x00000001U
+#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S  31
+
+/** PMU_LP_CPU_PWR1_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x188)
+/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_SLEEP_REQ    (BIT(31))
+#define PMU_LP_CPU_SLEEP_REQ_M  (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S)
+#define PMU_LP_CPU_SLEEP_REQ_V  0x00000001U
+#define PMU_LP_CPU_SLEEP_REQ_S  31
+
+/** PMU_LP_CPU_PWR2_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR2_REG (DR_REG_PMU_BASE + 0x18c)
+/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_EN    0x7FFFFFFFU
+#define PMU_LP_CPU_WAKEUP_EN_M  (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S)
+#define PMU_LP_CPU_WAKEUP_EN_V  0x7FFFFFFFU
+#define PMU_LP_CPU_WAKEUP_EN_S  0
+
+/** PMU_LP_CPU_PWR3_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR3_REG (DR_REG_PMU_BASE + 0x190)
+/** PMU_LP_CPU_WAKEUP_CAUSE : RO; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_WAKEUP_CAUSE    0x7FFFFFFFU
+#define PMU_LP_CPU_WAKEUP_CAUSE_M  (PMU_LP_CPU_WAKEUP_CAUSE_V << PMU_LP_CPU_WAKEUP_CAUSE_S)
+#define PMU_LP_CPU_WAKEUP_CAUSE_V  0x7FFFFFFFU
+#define PMU_LP_CPU_WAKEUP_CAUSE_S  0
+
+/** PMU_LP_CPU_PWR4_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR4_REG (DR_REG_PMU_BASE + 0x194)
+/** PMU_LP_CPU_REJECT_EN : R/W; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_REJECT_EN    0x7FFFFFFFU
+#define PMU_LP_CPU_REJECT_EN_M  (PMU_LP_CPU_REJECT_EN_V << PMU_LP_CPU_REJECT_EN_S)
+#define PMU_LP_CPU_REJECT_EN_V  0x7FFFFFFFU
+#define PMU_LP_CPU_REJECT_EN_S  0
+
+/** PMU_LP_CPU_PWR5_REG register
+ *  need_des
+ */
+#define PMU_LP_CPU_PWR5_REG (DR_REG_PMU_BASE + 0x198)
+/** PMU_LP_CPU_REJECT_CAUSE : RO; bitpos: [30:0]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_CPU_REJECT_CAUSE    0x7FFFFFFFU
+#define PMU_LP_CPU_REJECT_CAUSE_M  (PMU_LP_CPU_REJECT_CAUSE_V << PMU_LP_CPU_REJECT_CAUSE_S)
+#define PMU_LP_CPU_REJECT_CAUSE_V  0x7FFFFFFFU
+#define PMU_LP_CPU_REJECT_CAUSE_S  0
+
+/** PMU_HP_LP_CPU_COMM_REG register
+ *  need_des
+ */
+#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x19c)
+/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_LP_TRIGGER_HP    (BIT(30))
+#define PMU_LP_TRIGGER_HP_M  (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S)
+#define PMU_LP_TRIGGER_HP_V  0x00000001U
+#define PMU_LP_TRIGGER_HP_S  30
+/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_HP_TRIGGER_LP    (BIT(31))
+#define PMU_HP_TRIGGER_LP_M  (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S)
+#define PMU_HP_TRIGGER_LP_V  0x00000001U
+#define PMU_HP_TRIGGER_LP_S  31
+
+/** PMU_HP_REGULATOR_CFG_REG register
+ *  need_des
+ */
+#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x1a0)
+/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_DIG_REGULATOR_EN_CAL    (BIT(31))
+#define PMU_DIG_REGULATOR_EN_CAL_M  (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S)
+#define PMU_DIG_REGULATOR_EN_CAL_V  0x00000001U
+#define PMU_DIG_REGULATOR_EN_CAL_S  31
+
+/** PMU_MAIN_STATE_REG register
+ *  need_des
+ */
+#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x1a4)
+/** PMU_ENABLE_CALI_PMU_CNTL : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define PMU_ENABLE_CALI_PMU_CNTL    (BIT(0))
+#define PMU_ENABLE_CALI_PMU_CNTL_M  (PMU_ENABLE_CALI_PMU_CNTL_V << PMU_ENABLE_CALI_PMU_CNTL_S)
+#define PMU_ENABLE_CALI_PMU_CNTL_V  0x00000001U
+#define PMU_ENABLE_CALI_PMU_CNTL_S  0
+/** PMU_PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1;
+ *  need_des
+ */
+#define PMU_PMU_MAIN_LAST_ST_STATE    0x0000007FU
+#define PMU_PMU_MAIN_LAST_ST_STATE_M  (PMU_PMU_MAIN_LAST_ST_STATE_V << PMU_PMU_MAIN_LAST_ST_STATE_S)
+#define PMU_PMU_MAIN_LAST_ST_STATE_V  0x0000007FU
+#define PMU_PMU_MAIN_LAST_ST_STATE_S  11
+/** PMU_PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4;
+ *  need_des
+ */
+#define PMU_PMU_MAIN_TAR_ST_STATE    0x0000007FU
+#define PMU_PMU_MAIN_TAR_ST_STATE_M  (PMU_PMU_MAIN_TAR_ST_STATE_V << PMU_PMU_MAIN_TAR_ST_STATE_S)
+#define PMU_PMU_MAIN_TAR_ST_STATE_V  0x0000007FU
+#define PMU_PMU_MAIN_TAR_ST_STATE_S  18
+/** PMU_PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4;
+ *  need_des
+ */
+#define PMU_PMU_MAIN_CUR_ST_STATE    0x0000007FU
+#define PMU_PMU_MAIN_CUR_ST_STATE_M  (PMU_PMU_MAIN_CUR_ST_STATE_V << PMU_PMU_MAIN_CUR_ST_STATE_S)
+#define PMU_PMU_MAIN_CUR_ST_STATE_V  0x0000007FU
+#define PMU_PMU_MAIN_CUR_ST_STATE_S  25
+
+/** PMU_PWR_STATE_REG register
+ *  need_des
+ */
+#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x1a8)
+/** PMU_PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1;
+ *  need_des
+ */
+#define PMU_PMU_BACKUP_ST_STATE    0x0000001FU
+#define PMU_PMU_BACKUP_ST_STATE_M  (PMU_PMU_BACKUP_ST_STATE_V << PMU_PMU_BACKUP_ST_STATE_S)
+#define PMU_PMU_BACKUP_ST_STATE_V  0x0000001FU
+#define PMU_PMU_BACKUP_ST_STATE_S  13
+/** PMU_PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_LP_PWR_ST_STATE    0x0000001FU
+#define PMU_PMU_LP_PWR_ST_STATE_M  (PMU_PMU_LP_PWR_ST_STATE_V << PMU_PMU_LP_PWR_ST_STATE_S)
+#define PMU_PMU_LP_PWR_ST_STATE_V  0x0000001FU
+#define PMU_PMU_LP_PWR_ST_STATE_S  18
+/** PMU_PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1;
+ *  need_des
+ */
+#define PMU_PMU_HP_PWR_ST_STATE    0x000001FFU
+#define PMU_PMU_HP_PWR_ST_STATE_M  (PMU_PMU_HP_PWR_ST_STATE_V << PMU_PMU_HP_PWR_ST_STATE_S)
+#define PMU_PMU_HP_PWR_ST_STATE_V  0x000001FFU
+#define PMU_PMU_HP_PWR_ST_STATE_S  23
+
+/** PMU_CLK_STATE0_REG register
+ *  need_des
+ */
+#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac)
+/** PMU_STABLE_XPD_PLL_STATE : RO; bitpos: [2:0]; default: 7;
+ *  need_des
+ */
+#define PMU_STABLE_XPD_PLL_STATE    0x00000007U
+#define PMU_STABLE_XPD_PLL_STATE_M  (PMU_STABLE_XPD_PLL_STATE_V << PMU_STABLE_XPD_PLL_STATE_S)
+#define PMU_STABLE_XPD_PLL_STATE_V  0x00000007U
+#define PMU_STABLE_XPD_PLL_STATE_S  0
+/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define PMU_STABLE_XPD_XTAL_STATE    (BIT(3))
+#define PMU_STABLE_XPD_XTAL_STATE_M  (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S)
+#define PMU_STABLE_XPD_XTAL_STATE_V  0x00000001U
+#define PMU_STABLE_XPD_XTAL_STATE_S  3
+/** PMU_PMU_ANA_XPD_PLL_I2C_STATE : RO; bitpos: [6:4]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ANA_XPD_PLL_I2C_STATE    0x00000007U
+#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_M  (PMU_PMU_ANA_XPD_PLL_I2C_STATE_V << PMU_PMU_ANA_XPD_PLL_I2C_STATE_S)
+#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_V  0x00000007U
+#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_S  4
+/** PMU_PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_SYS_CLK_SLP_SEL_STATE    (BIT(10))
+#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_M  (PMU_PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_PMU_SYS_CLK_SLP_SEL_STATE_S)
+#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_V  0x00000001U
+#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_S  10
+/** PMU_PMU_SYS_CLK_SEL_STATE : RO; bitpos: [12:11]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_SYS_CLK_SEL_STATE    0x00000003U
+#define PMU_PMU_SYS_CLK_SEL_STATE_M  (PMU_PMU_SYS_CLK_SEL_STATE_V << PMU_PMU_SYS_CLK_SEL_STATE_S)
+#define PMU_PMU_SYS_CLK_SEL_STATE_V  0x00000003U
+#define PMU_PMU_SYS_CLK_SEL_STATE_S  11
+/** PMU_PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_SYS_CLK_NO_DIV_STATE    (BIT(13))
+#define PMU_PMU_SYS_CLK_NO_DIV_STATE_M  (PMU_PMU_SYS_CLK_NO_DIV_STATE_V << PMU_PMU_SYS_CLK_NO_DIV_STATE_S)
+#define PMU_PMU_SYS_CLK_NO_DIV_STATE_V  0x00000001U
+#define PMU_PMU_SYS_CLK_NO_DIV_STATE_S  13
+/** PMU_PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_SYS_CLK_EN_STATE    (BIT(14))
+#define PMU_PMU_ICG_SYS_CLK_EN_STATE_M  (PMU_PMU_ICG_SYS_CLK_EN_STATE_V << PMU_PMU_ICG_SYS_CLK_EN_STATE_S)
+#define PMU_PMU_ICG_SYS_CLK_EN_STATE_V  0x00000001U
+#define PMU_PMU_ICG_SYS_CLK_EN_STATE_S  14
+/** PMU_PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_MODEM_SWITCH_STATE    (BIT(15))
+#define PMU_PMU_ICG_MODEM_SWITCH_STATE_M  (PMU_PMU_ICG_MODEM_SWITCH_STATE_V << PMU_PMU_ICG_MODEM_SWITCH_STATE_S)
+#define PMU_PMU_ICG_MODEM_SWITCH_STATE_V  0x00000001U
+#define PMU_PMU_ICG_MODEM_SWITCH_STATE_S  15
+/** PMU_PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [17:16]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_MODEM_CODE_STATE    0x00000003U
+#define PMU_PMU_ICG_MODEM_CODE_STATE_M  (PMU_PMU_ICG_MODEM_CODE_STATE_V << PMU_PMU_ICG_MODEM_CODE_STATE_S)
+#define PMU_PMU_ICG_MODEM_CODE_STATE_V  0x00000003U
+#define PMU_PMU_ICG_MODEM_CODE_STATE_S  16
+/** PMU_PMU_ICG_SLP_SEL_STATE : RO; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_SLP_SEL_STATE    (BIT(18))
+#define PMU_PMU_ICG_SLP_SEL_STATE_M  (PMU_PMU_ICG_SLP_SEL_STATE_V << PMU_PMU_ICG_SLP_SEL_STATE_S)
+#define PMU_PMU_ICG_SLP_SEL_STATE_V  0x00000001U
+#define PMU_PMU_ICG_SLP_SEL_STATE_S  18
+/** PMU_PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_GLOBAL_XTAL_STATE    (BIT(19))
+#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_M  (PMU_PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_PMU_ICG_GLOBAL_XTAL_STATE_S)
+#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_V  0x00000001U
+#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_S  19
+/** PMU_PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [23:20]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ICG_GLOBAL_PLL_STATE    0x0000000FU
+#define PMU_PMU_ICG_GLOBAL_PLL_STATE_M  (PMU_PMU_ICG_GLOBAL_PLL_STATE_V << PMU_PMU_ICG_GLOBAL_PLL_STATE_S)
+#define PMU_PMU_ICG_GLOBAL_PLL_STATE_V  0x0000000FU
+#define PMU_PMU_ICG_GLOBAL_PLL_STATE_S  20
+/** PMU_PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ANA_I2C_ISO_EN_STATE    (BIT(24))
+#define PMU_PMU_ANA_I2C_ISO_EN_STATE_M  (PMU_PMU_ANA_I2C_ISO_EN_STATE_V << PMU_PMU_ANA_I2C_ISO_EN_STATE_S)
+#define PMU_PMU_ANA_I2C_ISO_EN_STATE_V  0x00000001U
+#define PMU_PMU_ANA_I2C_ISO_EN_STATE_S  24
+/** PMU_PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ANA_I2C_RETENTION_STATE    (BIT(25))
+#define PMU_PMU_ANA_I2C_RETENTION_STATE_M  (PMU_PMU_ANA_I2C_RETENTION_STATE_V << PMU_PMU_ANA_I2C_RETENTION_STATE_S)
+#define PMU_PMU_ANA_I2C_RETENTION_STATE_V  0x00000001U
+#define PMU_PMU_ANA_I2C_RETENTION_STATE_S  25
+/** PMU_PMU_ANA_XPD_PLL_STATE : RO; bitpos: [30:27]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ANA_XPD_PLL_STATE    0x0000000FU
+#define PMU_PMU_ANA_XPD_PLL_STATE_M  (PMU_PMU_ANA_XPD_PLL_STATE_V << PMU_PMU_ANA_XPD_PLL_STATE_S)
+#define PMU_PMU_ANA_XPD_PLL_STATE_V  0x0000000FU
+#define PMU_PMU_ANA_XPD_PLL_STATE_S  27
+/** PMU_PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_ANA_XPD_XTAL_STATE    (BIT(31))
+#define PMU_PMU_ANA_XPD_XTAL_STATE_M  (PMU_PMU_ANA_XPD_XTAL_STATE_V << PMU_PMU_ANA_XPD_XTAL_STATE_S)
+#define PMU_PMU_ANA_XPD_XTAL_STATE_V  0x00000001U
+#define PMU_PMU_ANA_XPD_XTAL_STATE_S  31
+
+/** PMU_CLK_STATE1_REG register
+ *  need_des
+ */
+#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x1b0)
+/** PMU_PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_PMU_ICG_FUNC_EN_STATE    0xFFFFFFFFU
+#define PMU_PMU_ICG_FUNC_EN_STATE_M  (PMU_PMU_ICG_FUNC_EN_STATE_V << PMU_PMU_ICG_FUNC_EN_STATE_S)
+#define PMU_PMU_ICG_FUNC_EN_STATE_V  0xFFFFFFFFU
+#define PMU_PMU_ICG_FUNC_EN_STATE_S  0
+
+/** PMU_CLK_STATE2_REG register
+ *  need_des
+ */
+#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1b4)
+/** PMU_PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define PMU_PMU_ICG_APB_EN_STATE    0xFFFFFFFFU
+#define PMU_PMU_ICG_APB_EN_STATE_M  (PMU_PMU_ICG_APB_EN_STATE_V << PMU_PMU_ICG_APB_EN_STATE_S)
+#define PMU_PMU_ICG_APB_EN_STATE_V  0xFFFFFFFFU
+#define PMU_PMU_ICG_APB_EN_STATE_S  0
+
+/** PMU_EXT_LDO_P0_0P1A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P1A_REG (DR_REG_PMU_BASE + 0x1b8)
+/** PMU_0P1A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_FORCE_TIEH_SEL_0    (BIT(7))
+#define PMU_0P1A_FORCE_TIEH_SEL_0_M  (PMU_0P1A_FORCE_TIEH_SEL_0_V << PMU_0P1A_FORCE_TIEH_SEL_0_S)
+#define PMU_0P1A_FORCE_TIEH_SEL_0_V  0x00000001U
+#define PMU_0P1A_FORCE_TIEH_SEL_0_S  7
+/** PMU_0P1A_XPD_0 : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define PMU_0P1A_XPD_0    (BIT(8))
+#define PMU_0P1A_XPD_0_M  (PMU_0P1A_XPD_0_V << PMU_0P1A_XPD_0_S)
+#define PMU_0P1A_XPD_0_V  0x00000001U
+#define PMU_0P1A_XPD_0_S  8
+/** PMU_0P1A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_SEL_0    0x00000007U
+#define PMU_0P1A_TIEH_SEL_0_M  (PMU_0P1A_TIEH_SEL_0_V << PMU_0P1A_TIEH_SEL_0_S)
+#define PMU_0P1A_TIEH_SEL_0_V  0x00000007U
+#define PMU_0P1A_TIEH_SEL_0_S  9
+/** PMU_0P1A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_POS_EN_0    (BIT(12))
+#define PMU_0P1A_TIEH_POS_EN_0_M  (PMU_0P1A_TIEH_POS_EN_0_V << PMU_0P1A_TIEH_POS_EN_0_S)
+#define PMU_0P1A_TIEH_POS_EN_0_V  0x00000001U
+#define PMU_0P1A_TIEH_POS_EN_0_S  12
+/** PMU_0P1A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_NEG_EN_0    (BIT(13))
+#define PMU_0P1A_TIEH_NEG_EN_0_M  (PMU_0P1A_TIEH_NEG_EN_0_V << PMU_0P1A_TIEH_NEG_EN_0_S)
+#define PMU_0P1A_TIEH_NEG_EN_0_V  0x00000001U
+#define PMU_0P1A_TIEH_NEG_EN_0_S  13
+/** PMU_0P1A_TIEH_0 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_0    (BIT(14))
+#define PMU_0P1A_TIEH_0_M  (PMU_0P1A_TIEH_0_V << PMU_0P1A_TIEH_0_S)
+#define PMU_0P1A_TIEH_0_V  0x00000001U
+#define PMU_0P1A_TIEH_0_S  14
+/** PMU_0P1A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P1A_TARGET1_0    0x000000FFU
+#define PMU_0P1A_TARGET1_0_M  (PMU_0P1A_TARGET1_0_V << PMU_0P1A_TARGET1_0_S)
+#define PMU_0P1A_TARGET1_0_V  0x000000FFU
+#define PMU_0P1A_TARGET1_0_S  15
+/** PMU_0P1A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P1A_TARGET0_0    0x000000FFU
+#define PMU_0P1A_TARGET0_0_M  (PMU_0P1A_TARGET0_0_V << PMU_0P1A_TARGET0_0_S)
+#define PMU_0P1A_TARGET0_0_V  0x000000FFU
+#define PMU_0P1A_TARGET0_0_S  23
+/** PMU_0P1A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0    (BIT(31))
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_M  (PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_S)
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_V  0x00000001U
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_S  31
+
+/** PMU_EXT_LDO_P0_0P1A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P1A_ANA_REG (DR_REG_PMU_BASE + 0x1bc)
+/** PMU_ANA_0P1A_MUL_0 : R/W; bitpos: [25:23]; default: 2;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_MUL_0    0x00000007U
+#define PMU_ANA_0P1A_MUL_0_M  (PMU_ANA_0P1A_MUL_0_V << PMU_ANA_0P1A_MUL_0_S)
+#define PMU_ANA_0P1A_MUL_0_V  0x00000007U
+#define PMU_ANA_0P1A_MUL_0_S  23
+/** PMU_ANA_0P1A_EN_VDET_0 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_EN_VDET_0    (BIT(26))
+#define PMU_ANA_0P1A_EN_VDET_0_M  (PMU_ANA_0P1A_EN_VDET_0_V << PMU_ANA_0P1A_EN_VDET_0_S)
+#define PMU_ANA_0P1A_EN_VDET_0_V  0x00000001U
+#define PMU_ANA_0P1A_EN_VDET_0_S  26
+/** PMU_ANA_0P1A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_EN_CUR_LIM_0    (BIT(27))
+#define PMU_ANA_0P1A_EN_CUR_LIM_0_M  (PMU_ANA_0P1A_EN_CUR_LIM_0_V << PMU_ANA_0P1A_EN_CUR_LIM_0_S)
+#define PMU_ANA_0P1A_EN_CUR_LIM_0_V  0x00000001U
+#define PMU_ANA_0P1A_EN_CUR_LIM_0_S  27
+/** PMU_ANA_0P1A_DREF_0 : R/W; bitpos: [31:28]; default: 11;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_DREF_0    0x0000000FU
+#define PMU_ANA_0P1A_DREF_0_M  (PMU_ANA_0P1A_DREF_0_V << PMU_ANA_0P1A_DREF_0_S)
+#define PMU_ANA_0P1A_DREF_0_V  0x0000000FU
+#define PMU_ANA_0P1A_DREF_0_S  28
+
+/** PMU_EXT_LDO_P0_0P2A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P2A_REG (DR_REG_PMU_BASE + 0x1c0)
+/** PMU_0P2A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_FORCE_TIEH_SEL_0    (BIT(7))
+#define PMU_0P2A_FORCE_TIEH_SEL_0_M  (PMU_0P2A_FORCE_TIEH_SEL_0_V << PMU_0P2A_FORCE_TIEH_SEL_0_S)
+#define PMU_0P2A_FORCE_TIEH_SEL_0_V  0x00000001U
+#define PMU_0P2A_FORCE_TIEH_SEL_0_S  7
+/** PMU_0P2A_XPD_0 : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_XPD_0    (BIT(8))
+#define PMU_0P2A_XPD_0_M  (PMU_0P2A_XPD_0_V << PMU_0P2A_XPD_0_S)
+#define PMU_0P2A_XPD_0_V  0x00000001U
+#define PMU_0P2A_XPD_0_S  8
+/** PMU_0P2A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_SEL_0    0x00000007U
+#define PMU_0P2A_TIEH_SEL_0_M  (PMU_0P2A_TIEH_SEL_0_V << PMU_0P2A_TIEH_SEL_0_S)
+#define PMU_0P2A_TIEH_SEL_0_V  0x00000007U
+#define PMU_0P2A_TIEH_SEL_0_S  9
+/** PMU_0P2A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_POS_EN_0    (BIT(12))
+#define PMU_0P2A_TIEH_POS_EN_0_M  (PMU_0P2A_TIEH_POS_EN_0_V << PMU_0P2A_TIEH_POS_EN_0_S)
+#define PMU_0P2A_TIEH_POS_EN_0_V  0x00000001U
+#define PMU_0P2A_TIEH_POS_EN_0_S  12
+/** PMU_0P2A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_NEG_EN_0    (BIT(13))
+#define PMU_0P2A_TIEH_NEG_EN_0_M  (PMU_0P2A_TIEH_NEG_EN_0_V << PMU_0P2A_TIEH_NEG_EN_0_S)
+#define PMU_0P2A_TIEH_NEG_EN_0_V  0x00000001U
+#define PMU_0P2A_TIEH_NEG_EN_0_S  13
+/** PMU_0P2A_TIEH_0 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_0    (BIT(14))
+#define PMU_0P2A_TIEH_0_M  (PMU_0P2A_TIEH_0_V << PMU_0P2A_TIEH_0_S)
+#define PMU_0P2A_TIEH_0_V  0x00000001U
+#define PMU_0P2A_TIEH_0_S  14
+/** PMU_0P2A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P2A_TARGET1_0    0x000000FFU
+#define PMU_0P2A_TARGET1_0_M  (PMU_0P2A_TARGET1_0_V << PMU_0P2A_TARGET1_0_S)
+#define PMU_0P2A_TARGET1_0_V  0x000000FFU
+#define PMU_0P2A_TARGET1_0_S  15
+/** PMU_0P2A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P2A_TARGET0_0    0x000000FFU
+#define PMU_0P2A_TARGET0_0_M  (PMU_0P2A_TARGET0_0_V << PMU_0P2A_TARGET0_0_S)
+#define PMU_0P2A_TARGET0_0_V  0x000000FFU
+#define PMU_0P2A_TARGET0_0_S  23
+/** PMU_0P2A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0    (BIT(31))
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_M  (PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_S)
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_V  0x00000001U
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_S  31
+
+/** PMU_EXT_LDO_P0_0P2A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P2A_ANA_REG (DR_REG_PMU_BASE + 0x1c4)
+/** PMU_ANA_0P2A_MUL_0 : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_MUL_0    0x00000007U
+#define PMU_ANA_0P2A_MUL_0_M  (PMU_ANA_0P2A_MUL_0_V << PMU_ANA_0P2A_MUL_0_S)
+#define PMU_ANA_0P2A_MUL_0_V  0x00000007U
+#define PMU_ANA_0P2A_MUL_0_S  23
+/** PMU_ANA_0P2A_EN_VDET_0 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_EN_VDET_0    (BIT(26))
+#define PMU_ANA_0P2A_EN_VDET_0_M  (PMU_ANA_0P2A_EN_VDET_0_V << PMU_ANA_0P2A_EN_VDET_0_S)
+#define PMU_ANA_0P2A_EN_VDET_0_V  0x00000001U
+#define PMU_ANA_0P2A_EN_VDET_0_S  26
+/** PMU_ANA_0P2A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_EN_CUR_LIM_0    (BIT(27))
+#define PMU_ANA_0P2A_EN_CUR_LIM_0_M  (PMU_ANA_0P2A_EN_CUR_LIM_0_V << PMU_ANA_0P2A_EN_CUR_LIM_0_S)
+#define PMU_ANA_0P2A_EN_CUR_LIM_0_V  0x00000001U
+#define PMU_ANA_0P2A_EN_CUR_LIM_0_S  27
+/** PMU_ANA_0P2A_DREF_0 : R/W; bitpos: [31:28]; default: 10;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_DREF_0    0x0000000FU
+#define PMU_ANA_0P2A_DREF_0_M  (PMU_ANA_0P2A_DREF_0_V << PMU_ANA_0P2A_DREF_0_S)
+#define PMU_ANA_0P2A_DREF_0_V  0x0000000FU
+#define PMU_ANA_0P2A_DREF_0_S  28
+
+/** PMU_EXT_LDO_P0_0P3A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P3A_REG (DR_REG_PMU_BASE + 0x1c8)
+/** PMU_0P3A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_FORCE_TIEH_SEL_0    (BIT(7))
+#define PMU_0P3A_FORCE_TIEH_SEL_0_M  (PMU_0P3A_FORCE_TIEH_SEL_0_V << PMU_0P3A_FORCE_TIEH_SEL_0_S)
+#define PMU_0P3A_FORCE_TIEH_SEL_0_V  0x00000001U
+#define PMU_0P3A_FORCE_TIEH_SEL_0_S  7
+/** PMU_0P3A_XPD_0 : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_XPD_0    (BIT(8))
+#define PMU_0P3A_XPD_0_M  (PMU_0P3A_XPD_0_V << PMU_0P3A_XPD_0_S)
+#define PMU_0P3A_XPD_0_V  0x00000001U
+#define PMU_0P3A_XPD_0_S  8
+/** PMU_0P3A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_SEL_0    0x00000007U
+#define PMU_0P3A_TIEH_SEL_0_M  (PMU_0P3A_TIEH_SEL_0_V << PMU_0P3A_TIEH_SEL_0_S)
+#define PMU_0P3A_TIEH_SEL_0_V  0x00000007U
+#define PMU_0P3A_TIEH_SEL_0_S  9
+/** PMU_0P3A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_POS_EN_0    (BIT(12))
+#define PMU_0P3A_TIEH_POS_EN_0_M  (PMU_0P3A_TIEH_POS_EN_0_V << PMU_0P3A_TIEH_POS_EN_0_S)
+#define PMU_0P3A_TIEH_POS_EN_0_V  0x00000001U
+#define PMU_0P3A_TIEH_POS_EN_0_S  12
+/** PMU_0P3A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_NEG_EN_0    (BIT(13))
+#define PMU_0P3A_TIEH_NEG_EN_0_M  (PMU_0P3A_TIEH_NEG_EN_0_V << PMU_0P3A_TIEH_NEG_EN_0_S)
+#define PMU_0P3A_TIEH_NEG_EN_0_V  0x00000001U
+#define PMU_0P3A_TIEH_NEG_EN_0_S  13
+/** PMU_0P3A_TIEH_0 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_0    (BIT(14))
+#define PMU_0P3A_TIEH_0_M  (PMU_0P3A_TIEH_0_V << PMU_0P3A_TIEH_0_S)
+#define PMU_0P3A_TIEH_0_V  0x00000001U
+#define PMU_0P3A_TIEH_0_S  14
+/** PMU_0P3A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P3A_TARGET1_0    0x000000FFU
+#define PMU_0P3A_TARGET1_0_M  (PMU_0P3A_TARGET1_0_V << PMU_0P3A_TARGET1_0_S)
+#define PMU_0P3A_TARGET1_0_V  0x000000FFU
+#define PMU_0P3A_TARGET1_0_S  15
+/** PMU_0P3A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P3A_TARGET0_0    0x000000FFU
+#define PMU_0P3A_TARGET0_0_M  (PMU_0P3A_TARGET0_0_V << PMU_0P3A_TARGET0_0_S)
+#define PMU_0P3A_TARGET0_0_V  0x000000FFU
+#define PMU_0P3A_TARGET0_0_S  23
+/** PMU_0P3A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0    (BIT(31))
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_M  (PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_S)
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_V  0x00000001U
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_S  31
+
+/** PMU_EXT_LDO_P0_0P3A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P0_0P3A_ANA_REG (DR_REG_PMU_BASE + 0x1cc)
+/** PMU_ANA_0P3A_MUL_0 : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_MUL_0    0x00000007U
+#define PMU_ANA_0P3A_MUL_0_M  (PMU_ANA_0P3A_MUL_0_V << PMU_ANA_0P3A_MUL_0_S)
+#define PMU_ANA_0P3A_MUL_0_V  0x00000007U
+#define PMU_ANA_0P3A_MUL_0_S  23
+/** PMU_ANA_0P3A_EN_VDET_0 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_EN_VDET_0    (BIT(26))
+#define PMU_ANA_0P3A_EN_VDET_0_M  (PMU_ANA_0P3A_EN_VDET_0_V << PMU_ANA_0P3A_EN_VDET_0_S)
+#define PMU_ANA_0P3A_EN_VDET_0_V  0x00000001U
+#define PMU_ANA_0P3A_EN_VDET_0_S  26
+/** PMU_ANA_0P3A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_EN_CUR_LIM_0    (BIT(27))
+#define PMU_ANA_0P3A_EN_CUR_LIM_0_M  (PMU_ANA_0P3A_EN_CUR_LIM_0_V << PMU_ANA_0P3A_EN_CUR_LIM_0_S)
+#define PMU_ANA_0P3A_EN_CUR_LIM_0_V  0x00000001U
+#define PMU_ANA_0P3A_EN_CUR_LIM_0_S  27
+/** PMU_ANA_0P3A_DREF_0 : R/W; bitpos: [31:28]; default: 10;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_DREF_0    0x0000000FU
+#define PMU_ANA_0P3A_DREF_0_M  (PMU_ANA_0P3A_DREF_0_V << PMU_ANA_0P3A_DREF_0_S)
+#define PMU_ANA_0P3A_DREF_0_V  0x0000000FU
+#define PMU_ANA_0P3A_DREF_0_S  28
+
+/** PMU_EXT_LDO_P1_0P1A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P1A_REG (DR_REG_PMU_BASE + 0x1d0)
+/** PMU_0P1A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_FORCE_TIEH_SEL_1    (BIT(7))
+#define PMU_0P1A_FORCE_TIEH_SEL_1_M  (PMU_0P1A_FORCE_TIEH_SEL_1_V << PMU_0P1A_FORCE_TIEH_SEL_1_S)
+#define PMU_0P1A_FORCE_TIEH_SEL_1_V  0x00000001U
+#define PMU_0P1A_FORCE_TIEH_SEL_1_S  7
+/** PMU_0P1A_XPD_1 : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_XPD_1    (BIT(8))
+#define PMU_0P1A_XPD_1_M  (PMU_0P1A_XPD_1_V << PMU_0P1A_XPD_1_S)
+#define PMU_0P1A_XPD_1_V  0x00000001U
+#define PMU_0P1A_XPD_1_S  8
+/** PMU_0P1A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_SEL_1    0x00000007U
+#define PMU_0P1A_TIEH_SEL_1_M  (PMU_0P1A_TIEH_SEL_1_V << PMU_0P1A_TIEH_SEL_1_S)
+#define PMU_0P1A_TIEH_SEL_1_V  0x00000007U
+#define PMU_0P1A_TIEH_SEL_1_S  9
+/** PMU_0P1A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_POS_EN_1    (BIT(12))
+#define PMU_0P1A_TIEH_POS_EN_1_M  (PMU_0P1A_TIEH_POS_EN_1_V << PMU_0P1A_TIEH_POS_EN_1_S)
+#define PMU_0P1A_TIEH_POS_EN_1_V  0x00000001U
+#define PMU_0P1A_TIEH_POS_EN_1_S  12
+/** PMU_0P1A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_NEG_EN_1    (BIT(13))
+#define PMU_0P1A_TIEH_NEG_EN_1_M  (PMU_0P1A_TIEH_NEG_EN_1_V << PMU_0P1A_TIEH_NEG_EN_1_S)
+#define PMU_0P1A_TIEH_NEG_EN_1_V  0x00000001U
+#define PMU_0P1A_TIEH_NEG_EN_1_S  13
+/** PMU_0P1A_TIEH_1 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_TIEH_1    (BIT(14))
+#define PMU_0P1A_TIEH_1_M  (PMU_0P1A_TIEH_1_V << PMU_0P1A_TIEH_1_S)
+#define PMU_0P1A_TIEH_1_V  0x00000001U
+#define PMU_0P1A_TIEH_1_S  14
+/** PMU_0P1A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P1A_TARGET1_1    0x000000FFU
+#define PMU_0P1A_TARGET1_1_M  (PMU_0P1A_TARGET1_1_V << PMU_0P1A_TARGET1_1_S)
+#define PMU_0P1A_TARGET1_1_V  0x000000FFU
+#define PMU_0P1A_TARGET1_1_S  15
+/** PMU_0P1A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P1A_TARGET0_1    0x000000FFU
+#define PMU_0P1A_TARGET0_1_M  (PMU_0P1A_TARGET0_1_V << PMU_0P1A_TARGET0_1_S)
+#define PMU_0P1A_TARGET0_1_V  0x000000FFU
+#define PMU_0P1A_TARGET0_1_S  23
+/** PMU_0P1A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1    (BIT(31))
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_M  (PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_S)
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_V  0x00000001U
+#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_S  31
+
+/** PMU_EXT_LDO_P1_0P1A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P1A_ANA_REG (DR_REG_PMU_BASE + 0x1d4)
+/** PMU_ANA_0P1A_MUL_1 : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_MUL_1    0x00000007U
+#define PMU_ANA_0P1A_MUL_1_M  (PMU_ANA_0P1A_MUL_1_V << PMU_ANA_0P1A_MUL_1_S)
+#define PMU_ANA_0P1A_MUL_1_V  0x00000007U
+#define PMU_ANA_0P1A_MUL_1_S  23
+/** PMU_ANA_0P1A_EN_VDET_1 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_EN_VDET_1    (BIT(26))
+#define PMU_ANA_0P1A_EN_VDET_1_M  (PMU_ANA_0P1A_EN_VDET_1_V << PMU_ANA_0P1A_EN_VDET_1_S)
+#define PMU_ANA_0P1A_EN_VDET_1_V  0x00000001U
+#define PMU_ANA_0P1A_EN_VDET_1_S  26
+/** PMU_ANA_0P1A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_EN_CUR_LIM_1    (BIT(27))
+#define PMU_ANA_0P1A_EN_CUR_LIM_1_M  (PMU_ANA_0P1A_EN_CUR_LIM_1_V << PMU_ANA_0P1A_EN_CUR_LIM_1_S)
+#define PMU_ANA_0P1A_EN_CUR_LIM_1_V  0x00000001U
+#define PMU_ANA_0P1A_EN_CUR_LIM_1_S  27
+/** PMU_ANA_0P1A_DREF_1 : R/W; bitpos: [31:28]; default: 10;
+ *  need_des
+ */
+#define PMU_ANA_0P1A_DREF_1    0x0000000FU
+#define PMU_ANA_0P1A_DREF_1_M  (PMU_ANA_0P1A_DREF_1_V << PMU_ANA_0P1A_DREF_1_S)
+#define PMU_ANA_0P1A_DREF_1_V  0x0000000FU
+#define PMU_ANA_0P1A_DREF_1_S  28
+
+/** PMU_EXT_LDO_P1_0P2A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P2A_REG (DR_REG_PMU_BASE + 0x1d8)
+/** PMU_0P2A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_FORCE_TIEH_SEL_1    (BIT(7))
+#define PMU_0P2A_FORCE_TIEH_SEL_1_M  (PMU_0P2A_FORCE_TIEH_SEL_1_V << PMU_0P2A_FORCE_TIEH_SEL_1_S)
+#define PMU_0P2A_FORCE_TIEH_SEL_1_V  0x00000001U
+#define PMU_0P2A_FORCE_TIEH_SEL_1_S  7
+/** PMU_0P2A_XPD_1 : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_XPD_1    (BIT(8))
+#define PMU_0P2A_XPD_1_M  (PMU_0P2A_XPD_1_V << PMU_0P2A_XPD_1_S)
+#define PMU_0P2A_XPD_1_V  0x00000001U
+#define PMU_0P2A_XPD_1_S  8
+/** PMU_0P2A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_SEL_1    0x00000007U
+#define PMU_0P2A_TIEH_SEL_1_M  (PMU_0P2A_TIEH_SEL_1_V << PMU_0P2A_TIEH_SEL_1_S)
+#define PMU_0P2A_TIEH_SEL_1_V  0x00000007U
+#define PMU_0P2A_TIEH_SEL_1_S  9
+/** PMU_0P2A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_POS_EN_1    (BIT(12))
+#define PMU_0P2A_TIEH_POS_EN_1_M  (PMU_0P2A_TIEH_POS_EN_1_V << PMU_0P2A_TIEH_POS_EN_1_S)
+#define PMU_0P2A_TIEH_POS_EN_1_V  0x00000001U
+#define PMU_0P2A_TIEH_POS_EN_1_S  12
+/** PMU_0P2A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_NEG_EN_1    (BIT(13))
+#define PMU_0P2A_TIEH_NEG_EN_1_M  (PMU_0P2A_TIEH_NEG_EN_1_V << PMU_0P2A_TIEH_NEG_EN_1_S)
+#define PMU_0P2A_TIEH_NEG_EN_1_V  0x00000001U
+#define PMU_0P2A_TIEH_NEG_EN_1_S  13
+/** PMU_0P2A_TIEH_1 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_TIEH_1    (BIT(14))
+#define PMU_0P2A_TIEH_1_M  (PMU_0P2A_TIEH_1_V << PMU_0P2A_TIEH_1_S)
+#define PMU_0P2A_TIEH_1_V  0x00000001U
+#define PMU_0P2A_TIEH_1_S  14
+/** PMU_0P2A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P2A_TARGET1_1    0x000000FFU
+#define PMU_0P2A_TARGET1_1_M  (PMU_0P2A_TARGET1_1_V << PMU_0P2A_TARGET1_1_S)
+#define PMU_0P2A_TARGET1_1_V  0x000000FFU
+#define PMU_0P2A_TARGET1_1_S  15
+/** PMU_0P2A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P2A_TARGET0_1    0x000000FFU
+#define PMU_0P2A_TARGET0_1_M  (PMU_0P2A_TARGET0_1_V << PMU_0P2A_TARGET0_1_S)
+#define PMU_0P2A_TARGET0_1_V  0x000000FFU
+#define PMU_0P2A_TARGET0_1_S  23
+/** PMU_0P2A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1    (BIT(31))
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_M  (PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_S)
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_V  0x00000001U
+#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_S  31
+
+/** PMU_EXT_LDO_P1_0P2A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P2A_ANA_REG (DR_REG_PMU_BASE + 0x1dc)
+/** PMU_ANA_0P2A_MUL_1 : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_MUL_1    0x00000007U
+#define PMU_ANA_0P2A_MUL_1_M  (PMU_ANA_0P2A_MUL_1_V << PMU_ANA_0P2A_MUL_1_S)
+#define PMU_ANA_0P2A_MUL_1_V  0x00000007U
+#define PMU_ANA_0P2A_MUL_1_S  23
+/** PMU_ANA_0P2A_EN_VDET_1 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_EN_VDET_1    (BIT(26))
+#define PMU_ANA_0P2A_EN_VDET_1_M  (PMU_ANA_0P2A_EN_VDET_1_V << PMU_ANA_0P2A_EN_VDET_1_S)
+#define PMU_ANA_0P2A_EN_VDET_1_V  0x00000001U
+#define PMU_ANA_0P2A_EN_VDET_1_S  26
+/** PMU_ANA_0P2A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_EN_CUR_LIM_1    (BIT(27))
+#define PMU_ANA_0P2A_EN_CUR_LIM_1_M  (PMU_ANA_0P2A_EN_CUR_LIM_1_V << PMU_ANA_0P2A_EN_CUR_LIM_1_S)
+#define PMU_ANA_0P2A_EN_CUR_LIM_1_V  0x00000001U
+#define PMU_ANA_0P2A_EN_CUR_LIM_1_S  27
+/** PMU_ANA_0P2A_DREF_1 : R/W; bitpos: [31:28]; default: 10;
+ *  need_des
+ */
+#define PMU_ANA_0P2A_DREF_1    0x0000000FU
+#define PMU_ANA_0P2A_DREF_1_M  (PMU_ANA_0P2A_DREF_1_V << PMU_ANA_0P2A_DREF_1_S)
+#define PMU_ANA_0P2A_DREF_1_V  0x0000000FU
+#define PMU_ANA_0P2A_DREF_1_S  28
+
+/** PMU_EXT_LDO_P1_0P3A_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P3A_REG (DR_REG_PMU_BASE + 0x1e0)
+/** PMU_0P3A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_FORCE_TIEH_SEL_1    (BIT(7))
+#define PMU_0P3A_FORCE_TIEH_SEL_1_M  (PMU_0P3A_FORCE_TIEH_SEL_1_V << PMU_0P3A_FORCE_TIEH_SEL_1_S)
+#define PMU_0P3A_FORCE_TIEH_SEL_1_V  0x00000001U
+#define PMU_0P3A_FORCE_TIEH_SEL_1_S  7
+/** PMU_0P3A_XPD_1 : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_XPD_1    (BIT(8))
+#define PMU_0P3A_XPD_1_M  (PMU_0P3A_XPD_1_V << PMU_0P3A_XPD_1_S)
+#define PMU_0P3A_XPD_1_V  0x00000001U
+#define PMU_0P3A_XPD_1_S  8
+/** PMU_0P3A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_SEL_1    0x00000007U
+#define PMU_0P3A_TIEH_SEL_1_M  (PMU_0P3A_TIEH_SEL_1_V << PMU_0P3A_TIEH_SEL_1_S)
+#define PMU_0P3A_TIEH_SEL_1_V  0x00000007U
+#define PMU_0P3A_TIEH_SEL_1_S  9
+/** PMU_0P3A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_POS_EN_1    (BIT(12))
+#define PMU_0P3A_TIEH_POS_EN_1_M  (PMU_0P3A_TIEH_POS_EN_1_V << PMU_0P3A_TIEH_POS_EN_1_S)
+#define PMU_0P3A_TIEH_POS_EN_1_V  0x00000001U
+#define PMU_0P3A_TIEH_POS_EN_1_S  12
+/** PMU_0P3A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_NEG_EN_1    (BIT(13))
+#define PMU_0P3A_TIEH_NEG_EN_1_M  (PMU_0P3A_TIEH_NEG_EN_1_V << PMU_0P3A_TIEH_NEG_EN_1_S)
+#define PMU_0P3A_TIEH_NEG_EN_1_V  0x00000001U
+#define PMU_0P3A_TIEH_NEG_EN_1_S  13
+/** PMU_0P3A_TIEH_1 : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_TIEH_1    (BIT(14))
+#define PMU_0P3A_TIEH_1_M  (PMU_0P3A_TIEH_1_V << PMU_0P3A_TIEH_1_S)
+#define PMU_0P3A_TIEH_1_V  0x00000001U
+#define PMU_0P3A_TIEH_1_S  14
+/** PMU_0P3A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64;
+ *  need_des
+ */
+#define PMU_0P3A_TARGET1_1    0x000000FFU
+#define PMU_0P3A_TARGET1_1_M  (PMU_0P3A_TARGET1_1_V << PMU_0P3A_TARGET1_1_S)
+#define PMU_0P3A_TARGET1_1_V  0x000000FFU
+#define PMU_0P3A_TARGET1_1_S  15
+/** PMU_0P3A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128;
+ *  need_des
+ */
+#define PMU_0P3A_TARGET0_1    0x000000FFU
+#define PMU_0P3A_TARGET0_1_M  (PMU_0P3A_TARGET0_1_V << PMU_0P3A_TARGET0_1_S)
+#define PMU_0P3A_TARGET0_1_V  0x000000FFU
+#define PMU_0P3A_TARGET0_1_S  23
+/** PMU_0P3A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1    (BIT(31))
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_M  (PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_S)
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_V  0x00000001U
+#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_S  31
+
+/** PMU_EXT_LDO_P1_0P3A_ANA_REG register
+ *  need_des
+ */
+#define PMU_EXT_LDO_P1_0P3A_ANA_REG (DR_REG_PMU_BASE + 0x1e4)
+/** PMU_ANA_0P3A_MUL_1 : R/W; bitpos: [25:23]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_MUL_1    0x00000007U
+#define PMU_ANA_0P3A_MUL_1_M  (PMU_ANA_0P3A_MUL_1_V << PMU_ANA_0P3A_MUL_1_S)
+#define PMU_ANA_0P3A_MUL_1_V  0x00000007U
+#define PMU_ANA_0P3A_MUL_1_S  23
+/** PMU_ANA_0P3A_EN_VDET_1 : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_EN_VDET_1    (BIT(26))
+#define PMU_ANA_0P3A_EN_VDET_1_M  (PMU_ANA_0P3A_EN_VDET_1_V << PMU_ANA_0P3A_EN_VDET_1_S)
+#define PMU_ANA_0P3A_EN_VDET_1_V  0x00000001U
+#define PMU_ANA_0P3A_EN_VDET_1_S  26
+/** PMU_ANA_0P3A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_EN_CUR_LIM_1    (BIT(27))
+#define PMU_ANA_0P3A_EN_CUR_LIM_1_M  (PMU_ANA_0P3A_EN_CUR_LIM_1_V << PMU_ANA_0P3A_EN_CUR_LIM_1_S)
+#define PMU_ANA_0P3A_EN_CUR_LIM_1_V  0x00000001U
+#define PMU_ANA_0P3A_EN_CUR_LIM_1_S  27
+/** PMU_ANA_0P3A_DREF_1 : R/W; bitpos: [31:28]; default: 10;
+ *  need_des
+ */
+#define PMU_ANA_0P3A_DREF_1    0x0000000FU
+#define PMU_ANA_0P3A_DREF_1_M  (PMU_ANA_0P3A_DREF_1_V << PMU_ANA_0P3A_DREF_1_S)
+#define PMU_ANA_0P3A_DREF_1_V  0x0000000FU
+#define PMU_ANA_0P3A_DREF_1_S  28
+
+/** PMU_EXT_WAKEUP_LV_REG register
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_LV_REG (DR_REG_PMU_BASE + 0x1e8)
+/** PMU_EXT_WAKEUP_LV : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_LV    0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_LV_M  (PMU_EXT_WAKEUP_LV_V << PMU_EXT_WAKEUP_LV_S)
+#define PMU_EXT_WAKEUP_LV_V  0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_LV_S  0
+
+/** PMU_EXT_WAKEUP_SEL_REG register
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_SEL_REG (DR_REG_PMU_BASE + 0x1ec)
+/** PMU_EXT_WAKEUP_SEL : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_SEL    0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_SEL_M  (PMU_EXT_WAKEUP_SEL_V << PMU_EXT_WAKEUP_SEL_S)
+#define PMU_EXT_WAKEUP_SEL_V  0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_SEL_S  0
+
+/** PMU_EXT_WAKEUP_ST_REG register
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_ST_REG (DR_REG_PMU_BASE + 0x1f0)
+/** PMU_EXT_WAKEUP_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_STATUS    0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_STATUS_M  (PMU_EXT_WAKEUP_STATUS_V << PMU_EXT_WAKEUP_STATUS_S)
+#define PMU_EXT_WAKEUP_STATUS_V  0xFFFFFFFFU
+#define PMU_EXT_WAKEUP_STATUS_S  0
+
+/** PMU_EXT_WAKEUP_CNTL_REG register
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_CNTL_REG (DR_REG_PMU_BASE + 0x1f4)
+/** PMU_EXT_WAKEUP_STATUS_CLR : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_STATUS_CLR    (BIT(30))
+#define PMU_EXT_WAKEUP_STATUS_CLR_M  (PMU_EXT_WAKEUP_STATUS_CLR_V << PMU_EXT_WAKEUP_STATUS_CLR_S)
+#define PMU_EXT_WAKEUP_STATUS_CLR_V  0x00000001U
+#define PMU_EXT_WAKEUP_STATUS_CLR_S  30
+/** PMU_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_EXT_WAKEUP_FILTER    (BIT(31))
+#define PMU_EXT_WAKEUP_FILTER_M  (PMU_EXT_WAKEUP_FILTER_V << PMU_EXT_WAKEUP_FILTER_S)
+#define PMU_EXT_WAKEUP_FILTER_V  0x00000001U
+#define PMU_EXT_WAKEUP_FILTER_S  31
+
+/** PMU_SDIO_WAKEUP_CNTL_REG register
+ *  need_des
+ */
+#define PMU_SDIO_WAKEUP_CNTL_REG (DR_REG_PMU_BASE + 0x1f8)
+/** PMU_SDIO_ACT_DNUM : R/W; bitpos: [9:0]; default: 1023;
+ *  need_des
+ */
+#define PMU_SDIO_ACT_DNUM    0x000003FFU
+#define PMU_SDIO_ACT_DNUM_M  (PMU_SDIO_ACT_DNUM_V << PMU_SDIO_ACT_DNUM_S)
+#define PMU_SDIO_ACT_DNUM_V  0x000003FFU
+#define PMU_SDIO_ACT_DNUM_S  0
+
+/** PMU_XTAL_SLP_REG register
+ *  need_des
+ */
+#define PMU_XTAL_SLP_REG (DR_REG_PMU_BASE + 0x1fc)
+/** PMU_XTAL_SLP_CNT_TARGET : R/W; bitpos: [31:16]; default: 15;
+ *  need_des
+ */
+#define PMU_XTAL_SLP_CNT_TARGET    0x0000FFFFU
+#define PMU_XTAL_SLP_CNT_TARGET_M  (PMU_XTAL_SLP_CNT_TARGET_V << PMU_XTAL_SLP_CNT_TARGET_S)
+#define PMU_XTAL_SLP_CNT_TARGET_V  0x0000FFFFU
+#define PMU_XTAL_SLP_CNT_TARGET_S  16
+
+/** PMU_CPU_SW_STALL_REG register
+ *  need_des
+ */
+#define PMU_CPU_SW_STALL_REG (DR_REG_PMU_BASE + 0x200)
+/** PMU_HPCORE1_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define PMU_HPCORE1_SW_STALL_CODE    0x000000FFU
+#define PMU_HPCORE1_SW_STALL_CODE_M  (PMU_HPCORE1_SW_STALL_CODE_V << PMU_HPCORE1_SW_STALL_CODE_S)
+#define PMU_HPCORE1_SW_STALL_CODE_V  0x000000FFU
+#define PMU_HPCORE1_SW_STALL_CODE_S  16
+/** PMU_HPCORE0_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0;
+ *  need_des
+ */
+#define PMU_HPCORE0_SW_STALL_CODE    0x000000FFU
+#define PMU_HPCORE0_SW_STALL_CODE_M  (PMU_HPCORE0_SW_STALL_CODE_V << PMU_HPCORE0_SW_STALL_CODE_S)
+#define PMU_HPCORE0_SW_STALL_CODE_V  0x000000FFU
+#define PMU_HPCORE0_SW_STALL_CODE_S  24
+
+/** PMU_DCM_CTRL_REG register
+ *  need_des
+ */
+#define PMU_DCM_CTRL_REG (DR_REG_PMU_BASE + 0x204)
+/** PMU_DCDC_ON_REQ : WT; bitpos: [0]; default: 0;
+ *  SW trigger dcdc on
+ */
+#define PMU_DCDC_ON_REQ    (BIT(0))
+#define PMU_DCDC_ON_REQ_M  (PMU_DCDC_ON_REQ_V << PMU_DCDC_ON_REQ_S)
+#define PMU_DCDC_ON_REQ_V  0x00000001U
+#define PMU_DCDC_ON_REQ_S  0
+/** PMU_DCDC_OFF_REQ : WT; bitpos: [1]; default: 0;
+ *  SW trigger dcdc off
+ */
+#define PMU_DCDC_OFF_REQ    (BIT(1))
+#define PMU_DCDC_OFF_REQ_M  (PMU_DCDC_OFF_REQ_V << PMU_DCDC_OFF_REQ_S)
+#define PMU_DCDC_OFF_REQ_V  0x00000001U
+#define PMU_DCDC_OFF_REQ_S  1
+/** PMU_DCDC_LIGHTSLP_REQ : WT; bitpos: [2]; default: 0;
+ *  SW trigger dcdc enter lightsleep
+ */
+#define PMU_DCDC_LIGHTSLP_REQ    (BIT(2))
+#define PMU_DCDC_LIGHTSLP_REQ_M  (PMU_DCDC_LIGHTSLP_REQ_V << PMU_DCDC_LIGHTSLP_REQ_S)
+#define PMU_DCDC_LIGHTSLP_REQ_V  0x00000001U
+#define PMU_DCDC_LIGHTSLP_REQ_S  2
+/** PMU_DCDC_DEEPSLP_REQ : WT; bitpos: [3]; default: 0;
+ *  SW trigger dcdc enter deepsleep
+ */
+#define PMU_DCDC_DEEPSLP_REQ    (BIT(3))
+#define PMU_DCDC_DEEPSLP_REQ_M  (PMU_DCDC_DEEPSLP_REQ_V << PMU_DCDC_DEEPSLP_REQ_S)
+#define PMU_DCDC_DEEPSLP_REQ_V  0x00000001U
+#define PMU_DCDC_DEEPSLP_REQ_S  3
+/** PMU_DCDC_DONE_FORCE : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_DONE_FORCE    (BIT(7))
+#define PMU_DCDC_DONE_FORCE_M  (PMU_DCDC_DONE_FORCE_V << PMU_DCDC_DONE_FORCE_S)
+#define PMU_DCDC_DONE_FORCE_V  0x00000001U
+#define PMU_DCDC_DONE_FORCE_S  7
+/** PMU_DCDC_ON_FORCE_PU : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_ON_FORCE_PU    (BIT(8))
+#define PMU_DCDC_ON_FORCE_PU_M  (PMU_DCDC_ON_FORCE_PU_V << PMU_DCDC_ON_FORCE_PU_S)
+#define PMU_DCDC_ON_FORCE_PU_V  0x00000001U
+#define PMU_DCDC_ON_FORCE_PU_S  8
+/** PMU_DCDC_ON_FORCE_PD : R/W; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_ON_FORCE_PD    (BIT(9))
+#define PMU_DCDC_ON_FORCE_PD_M  (PMU_DCDC_ON_FORCE_PD_V << PMU_DCDC_ON_FORCE_PD_S)
+#define PMU_DCDC_ON_FORCE_PD_V  0x00000001U
+#define PMU_DCDC_ON_FORCE_PD_S  9
+/** PMU_DCDC_FB_RES_FORCE_PU : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_FB_RES_FORCE_PU    (BIT(10))
+#define PMU_DCDC_FB_RES_FORCE_PU_M  (PMU_DCDC_FB_RES_FORCE_PU_V << PMU_DCDC_FB_RES_FORCE_PU_S)
+#define PMU_DCDC_FB_RES_FORCE_PU_V  0x00000001U
+#define PMU_DCDC_FB_RES_FORCE_PU_S  10
+/** PMU_DCDC_FB_RES_FORCE_PD : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_FB_RES_FORCE_PD    (BIT(11))
+#define PMU_DCDC_FB_RES_FORCE_PD_M  (PMU_DCDC_FB_RES_FORCE_PD_V << PMU_DCDC_FB_RES_FORCE_PD_S)
+#define PMU_DCDC_FB_RES_FORCE_PD_V  0x00000001U
+#define PMU_DCDC_FB_RES_FORCE_PD_S  11
+/** PMU_DCDC_LS_FORCE_PU : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_LS_FORCE_PU    (BIT(12))
+#define PMU_DCDC_LS_FORCE_PU_M  (PMU_DCDC_LS_FORCE_PU_V << PMU_DCDC_LS_FORCE_PU_S)
+#define PMU_DCDC_LS_FORCE_PU_V  0x00000001U
+#define PMU_DCDC_LS_FORCE_PU_S  12
+/** PMU_DCDC_LS_FORCE_PD : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_LS_FORCE_PD    (BIT(13))
+#define PMU_DCDC_LS_FORCE_PD_M  (PMU_DCDC_LS_FORCE_PD_V << PMU_DCDC_LS_FORCE_PD_S)
+#define PMU_DCDC_LS_FORCE_PD_V  0x00000001U
+#define PMU_DCDC_LS_FORCE_PD_S  13
+/** PMU_DCDC_DS_FORCE_PU : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_DS_FORCE_PU    (BIT(14))
+#define PMU_DCDC_DS_FORCE_PU_M  (PMU_DCDC_DS_FORCE_PU_V << PMU_DCDC_DS_FORCE_PU_S)
+#define PMU_DCDC_DS_FORCE_PU_V  0x00000001U
+#define PMU_DCDC_DS_FORCE_PU_S  14
+/** PMU_DCDC_DS_FORCE_PD : R/W; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define PMU_DCDC_DS_FORCE_PD    (BIT(15))
+#define PMU_DCDC_DS_FORCE_PD_M  (PMU_DCDC_DS_FORCE_PD_V << PMU_DCDC_DS_FORCE_PD_S)
+#define PMU_DCDC_DS_FORCE_PD_V  0x00000001U
+#define PMU_DCDC_DS_FORCE_PD_S  15
+/** PMU_DCM_CUR_ST : RO; bitpos: [23:16]; default: 1;
+ *  need_des
+ */
+#define PMU_DCM_CUR_ST    0x000000FFU
+#define PMU_DCM_CUR_ST_M  (PMU_DCM_CUR_ST_V << PMU_DCM_CUR_ST_S)
+#define PMU_DCM_CUR_ST_V  0x000000FFU
+#define PMU_DCM_CUR_ST_S  16
+/** PMU_DCDC_EN_AMUX_TEST : R/W; bitpos: [29]; default: 0;
+ *  Enable analog mux to pull PAD TEST_DCDC voltage signal
+ */
+#define PMU_DCDC_EN_AMUX_TEST    (BIT(29))
+#define PMU_DCDC_EN_AMUX_TEST_M  (PMU_DCDC_EN_AMUX_TEST_V << PMU_DCDC_EN_AMUX_TEST_S)
+#define PMU_DCDC_EN_AMUX_TEST_V  0x00000001U
+#define PMU_DCDC_EN_AMUX_TEST_S  29
+
+/** PMU_DCM_WAIT_DELAY_REG register
+ *  need_des
+ */
+#define PMU_DCM_WAIT_DELAY_REG (DR_REG_PMU_BASE + 0x208)
+/** PMU_DCDC_PRE_DELAY : R/W; bitpos: [7:0]; default: 5;
+ *  DCDC pre-on/post off delay
+ */
+#define PMU_DCDC_PRE_DELAY    0x000000FFU
+#define PMU_DCDC_PRE_DELAY_M  (PMU_DCDC_PRE_DELAY_V << PMU_DCDC_PRE_DELAY_S)
+#define PMU_DCDC_PRE_DELAY_V  0x000000FFU
+#define PMU_DCDC_PRE_DELAY_S  0
+/** PMU_DCDC_RES_OFF_DELAY : R/W; bitpos: [15:8]; default: 2;
+ *  DCDC fb res off delay
+ */
+#define PMU_DCDC_RES_OFF_DELAY    0x000000FFU
+#define PMU_DCDC_RES_OFF_DELAY_M  (PMU_DCDC_RES_OFF_DELAY_V << PMU_DCDC_RES_OFF_DELAY_S)
+#define PMU_DCDC_RES_OFF_DELAY_V  0x000000FFU
+#define PMU_DCDC_RES_OFF_DELAY_S  8
+/** PMU_DCDC_STABLE_DELAY : R/W; bitpos: [25:16]; default: 75;
+ *  DCDC stable delay
+ */
+#define PMU_DCDC_STABLE_DELAY    0x000003FFU
+#define PMU_DCDC_STABLE_DELAY_M  (PMU_DCDC_STABLE_DELAY_V << PMU_DCDC_STABLE_DELAY_S)
+#define PMU_DCDC_STABLE_DELAY_V  0x000003FFU
+#define PMU_DCDC_STABLE_DELAY_S  16
+
+/** PMU_VDDBAT_CFG_REG register
+ *  need_des
+ */
+#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x20c)
+/** PMU_ANA_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define PMU_ANA_VDDBAT_MODE    0x00000003U
+#define PMU_ANA_VDDBAT_MODE_M  (PMU_ANA_VDDBAT_MODE_V << PMU_ANA_VDDBAT_MODE_S)
+#define PMU_ANA_VDDBAT_MODE_V  0x00000003U
+#define PMU_ANA_VDDBAT_MODE_S  0
+/** PMU_VDDBAT_SW_UPDATE : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_VDDBAT_SW_UPDATE    (BIT(31))
+#define PMU_VDDBAT_SW_UPDATE_M  (PMU_VDDBAT_SW_UPDATE_V << PMU_VDDBAT_SW_UPDATE_S)
+#define PMU_VDDBAT_SW_UPDATE_V  0x00000001U
+#define PMU_VDDBAT_SW_UPDATE_S  31
+
+/** PMU_TOUCH_PWR_CNTL_REG register
+ *  need_des
+ */
+#define PMU_TOUCH_PWR_CNTL_REG (DR_REG_PMU_BASE + 0x210)
+/** PMU_TOUCH_WAIT_CYCLES : R/W; bitpos: [13:5]; default: 10;
+ *  need_des
+ */
+#define PMU_TOUCH_WAIT_CYCLES    0x000001FFU
+#define PMU_TOUCH_WAIT_CYCLES_M  (PMU_TOUCH_WAIT_CYCLES_V << PMU_TOUCH_WAIT_CYCLES_S)
+#define PMU_TOUCH_WAIT_CYCLES_V  0x000001FFU
+#define PMU_TOUCH_WAIT_CYCLES_S  5
+/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [29:14]; default: 100;
+ *  need_des
+ */
+#define PMU_TOUCH_SLEEP_CYCLES    0x0000FFFFU
+#define PMU_TOUCH_SLEEP_CYCLES_M  (PMU_TOUCH_SLEEP_CYCLES_V << PMU_TOUCH_SLEEP_CYCLES_S)
+#define PMU_TOUCH_SLEEP_CYCLES_V  0x0000FFFFU
+#define PMU_TOUCH_SLEEP_CYCLES_S  14
+/** PMU_TOUCH_FORCE_DONE : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define PMU_TOUCH_FORCE_DONE    (BIT(30))
+#define PMU_TOUCH_FORCE_DONE_M  (PMU_TOUCH_FORCE_DONE_V << PMU_TOUCH_FORCE_DONE_S)
+#define PMU_TOUCH_FORCE_DONE_V  0x00000001U
+#define PMU_TOUCH_FORCE_DONE_S  30
+/** PMU_TOUCH_SLEEP_TIMER_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_TOUCH_SLEEP_TIMER_EN    (BIT(31))
+#define PMU_TOUCH_SLEEP_TIMER_EN_M  (PMU_TOUCH_SLEEP_TIMER_EN_V << PMU_TOUCH_SLEEP_TIMER_EN_S)
+#define PMU_TOUCH_SLEEP_TIMER_EN_V  0x00000001U
+#define PMU_TOUCH_SLEEP_TIMER_EN_S  31
+
+/** PMU_RDN_ECO_REG register
+ *  need_des
+ */
+#define PMU_RDN_ECO_REG (DR_REG_PMU_BASE + 0x214)
+/** PMU_PMU_RDN_ECO_RESULT : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_RDN_ECO_RESULT    (BIT(0))
+#define PMU_PMU_RDN_ECO_RESULT_M  (PMU_PMU_RDN_ECO_RESULT_V << PMU_PMU_RDN_ECO_RESULT_S)
+#define PMU_PMU_RDN_ECO_RESULT_V  0x00000001U
+#define PMU_PMU_RDN_ECO_RESULT_S  0
+/** PMU_PMU_RDN_ECO_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_PMU_RDN_ECO_EN    (BIT(31))
+#define PMU_PMU_RDN_ECO_EN_M  (PMU_PMU_RDN_ECO_EN_V << PMU_PMU_RDN_ECO_EN_S)
+#define PMU_PMU_RDN_ECO_EN_V  0x00000001U
+#define PMU_PMU_RDN_ECO_EN_S  31
+
+/** PMU_DATE_REG register
+ *  need_des
+ */
+#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc)
+/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 36712768;
+ *  need_des
+ */
+#define PMU_PMU_DATE    0x7FFFFFFFU
+#define PMU_PMU_DATE_M  (PMU_PMU_DATE_V << PMU_PMU_DATE_S)
+#define PMU_PMU_DATE_V  0x7FFFFFFFU
+#define PMU_PMU_DATE_S  0
+/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define PMU_CLK_EN    (BIT(31))
+#define PMU_CLK_EN_M  (PMU_CLK_EN_V << PMU_CLK_EN_S)
+#define PMU_CLK_EN_V  0x00000001U
+#define PMU_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h
new file mode 100644
index 0000000000..8d9e91538a
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h
@@ -0,0 +1,942 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/pmu_reg.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13420
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 21;
+        uint32_t dcdc_switch_pd_en :1;
+        uint32_t mem_dslp     : 1;
+        uint32_t mem_pd_en    : 1;
+        uint32_t reserved1    : 6;
+        uint32_t cnnt_pd_en   : 1;
+        uint32_t top_pd_en    : 1;
+    };
+    uint32_t val;
+} pmu_hp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 23;
+        uint32_t power_det_bypass : 1;
+        uint32_t uart_wakeup_en : 1;
+        uint32_t lp_pad_hold_all: 1;
+        uint32_t hp_pad_hold_all: 1;
+        uint32_t dig_pad_slp_sel: 1;
+        uint32_t dig_pause_wdt  : 1;
+        uint32_t dig_cpu_stall  : 1;
+        uint32_t reserved1      : 2;
+    };
+    uint32_t val;
+} pmu_hp_sys_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 21;
+        uint32_t i2c_iso_en   : 1;
+        uint32_t i2c_retention: 1;
+        uint32_t xpd_pll_i2c  : 4;
+        uint32_t xpd_pll      : 4;
+        uint32_t reserved1    : 1;
+    };
+    uint32_t val;
+} pmu_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 18;
+        uint32_t dcm_vset  : 5;
+        uint32_t dcm_mode  : 2;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_hp_bias_reg_t;
+
+typedef union {
+    struct {    /* HP: Active State */
+        uint32_t reserved0                            : 4;
+        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
+        uint32_t hp_modem2active_backup_modem_clk_code: 2;
+        uint32_t reserved1                            : 2;
+        uint32_t hp_active_retention_mode             : 1;
+        uint32_t hp_sleep2active_retention_en         : 1;
+        uint32_t hp_modem2active_retention_en         : 1;
+        uint32_t reserved2                            : 1;
+        uint32_t hp_sleep2active_backup_clk_sel       : 2;
+        uint32_t hp_modem2active_backup_clk_sel       : 2;
+        uint32_t reserved3                            : 2;
+        uint32_t hp_sleep2active_backup_mode          : 3;
+        uint32_t hp_modem2active_backup_mode          : 3;
+        uint32_t reserved4                            : 3;
+        uint32_t hp_sleep2active_backup_en            : 1;
+        uint32_t hp_modem2active_backup_en            : 1;
+        uint32_t reserved5                            : 1;
+    };
+    struct {    /* HP: Modem State */
+        uint32_t reserved6                            : 32;
+    };
+    struct {    /* HP: Sleep State */
+        uint32_t reserved12                           : 6;
+        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
+        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
+        uint32_t hp_sleep_retention_mode              : 1;
+        uint32_t reserved13                           : 1;
+        uint32_t hp_modem2sleep_retention_en          : 1;
+        uint32_t hp_active2sleep_retention_en         : 1;
+        uint32_t reserved14                           : 2;
+        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
+        uint32_t hp_active2sleep_backup_clk_sel       : 2;
+        uint32_t reserved15                           : 3;
+        uint32_t hp_modem2sleep_backup_mode           : 3;
+        uint32_t hp_active2sleep_backup_mode          : 3;
+        uint32_t reserved16                           : 1;
+        uint32_t hp_modem2sleep_backup_en             : 1;
+        uint32_t hp_active2sleep_backup_en            : 1;
+    };
+    uint32_t val;
+} pmu_hp_backup_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0       : 26;
+        uint32_t dig_sysclk_nodiv: 1;
+        uint32_t icg_sysclk_en   : 1;
+        uint32_t sysclk_slp_sel  : 1;
+        uint32_t icg_slp_sel     : 1;
+        uint32_t dig_sysclk_sel  : 2;
+    };
+    uint32_t val;
+} pmu_hp_sysclk_reg_t;
+
+typedef union {
+    // For chip_revsion < 1.0
+    struct {
+        uint32_t reserved0      : 4;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t slp_mem_xpd    : 1;
+        uint32_t slp_logic_xpd  : 1;
+        uint32_t xpd            : 1;
+        uint32_t slp_mem_dbias  : 4;    /* slp_mem_dbias is not used on chip_revision < 100 */
+        uint32_t slp_logic_dbias: 4;
+        uint32_t dbias          : 5;
+    };
+    // For chip revision >= 100
+    struct {
+        uint32_t reserved1      : 19;
+        uint32_t xpd_0p1a       : 4;    /* slp_mem_dbias[3] is used to control the volt output of VO1 on chip_revision >= 1.0 */
+        uint32_t reserved2      : 9;
+    };
+    uint32_t val;
+} pmu_hp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 26;
+        uint32_t drv_b    : 6;
+    };
+    uint32_t val;
+} pmu_hp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_hp_xtal_reg_t;
+
+typedef struct pmu_hp_hw_regmap_t {
+    pmu_hp_dig_power_reg_t     dig_power;
+    uint32_t                   icg_func;
+    uint32_t                   icg_apb;
+    uint32_t                   icg_modem;
+    pmu_hp_sys_cntl_reg_t      syscntl;
+    pmu_hp_clk_power_reg_t     clk_power;
+    pmu_hp_bias_reg_t          bias;
+    pmu_hp_backup_reg_t        backup;
+    uint32_t                   backup_clk;
+    pmu_hp_sysclk_reg_t        sysclk;
+    pmu_hp_regulator0_reg_t    regulator0;
+    pmu_hp_regulator1_reg_t    regulator1;
+    pmu_hp_xtal_reg_t          xtal;
+} pmu_hp_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 21;
+        uint32_t slp_xpd  : 1;
+        uint32_t xpd      : 1;
+        uint32_t slp_dbias: 4;
+        uint32_t dbias    : 5;
+    };
+    uint32_t val;
+} pmu_lp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 26;
+        uint32_t drv_b    : 6;
+    };
+    uint32_t val;
+} pmu_lp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_lp_xtal_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 26;
+        uint32_t lp_pad_slp_sel : 1;
+        uint32_t bod_source_sel : 1;
+        uint32_t vddbat_mode : 2;
+        uint32_t mem_dslp  : 1;
+        uint32_t peri_pd_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0  : 27;
+        uint32_t xpd_lppll  : 1;
+        uint32_t xpd_xtal32k: 1;
+        uint32_t xpd_rc32k  : 1;
+        uint32_t xpd_fosc   : 1;
+        uint32_t pd_osc     : 1;
+    };
+    uint32_t val;
+} pmu_lp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_lp_bias_reg_t;
+
+typedef struct pmu_lp_hw_regmap_t {
+    pmu_lp_regulator0_reg_t    regulator0;
+    pmu_lp_regulator1_reg_t    regulator1;
+    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
+    pmu_lp_dig_power_reg_t     dig_power;
+    pmu_lp_clk_power_reg_t     clk_power;
+    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
+} pmu_lp_hw_regmap_t;
+
+
+typedef union {
+    struct {
+        uint32_t tie_low_cali_xtal_icg      : 1;
+        uint32_t tie_low_global_pll_icg     : 4;
+        uint32_t tie_low_global_xtal_icg    : 1;
+        uint32_t tie_low_i2c_retention      : 1;
+        uint32_t tie_low_xpd_pll_i2c        : 4;
+        uint32_t tie_low_xpd_pll            : 4;
+        uint32_t tie_low_xpd_xtal           : 1;
+        uint32_t tie_high_cali_xtal_icg     : 1;
+        uint32_t tie_high_global_pll_icg    : 4;
+        uint32_t tie_high_global_xtal_icg   : 1;
+        uint32_t tie_high_i2c_retention     : 1;
+        uint32_t tie_high_xpd_pll_i2c       : 4;
+        uint32_t tie_high_xpd_pll           : 4;
+        uint32_t tie_high_xpd_xtal          : 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 28;
+        uint32_t update_dig_icg_switch: 1;
+        uint32_t tie_low_icg_slp_sel  : 1;
+        uint32_t tie_high_icg_slp_sel : 1;
+        uint32_t update_dig_sysclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_sleep_sysclk_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0             : 31;
+        uint32_t update_dig_icg_func_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_func_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 31;
+        uint32_t update_dig_icg_apb_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_apb_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 31;
+        uint32_t update_dig_icg_modem_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_modem_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 30;
+        uint32_t tie_low_lp_rootclk_sel : 1;
+        uint32_t tie_high_lp_rootclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_lp_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t pad_slp_sel             : 1;
+        uint32_t lp_pad_hold_all         : 1;
+        uint32_t hp_pad_hold_all         : 1;
+        uint32_t reserved0               : 23;
+        uint32_t tie_high_pad_slp_sel    : 1;
+        uint32_t tie_low_pad_slp_sel     : 1;
+        uint32_t tie_high_lp_pad_hold_all: 1;
+        uint32_t tie_low_lp_pad_hold_all : 1;
+        uint32_t tie_high_hp_pad_hold_all: 1;
+        uint32_t tie_low_hp_pad_hold_all : 1;
+    };
+    uint32_t val;
+} pmu_imm_pad_hold_all_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 30;
+        uint32_t tie_high_i2c_iso_en: 1;
+        uint32_t tie_low_i2c_iso_en : 1;
+    };
+    uint32_t val;
+} pmu_imm_i2c_isolate_reg_t;
+
+typedef struct pmu_imm_hw_regmap_t {
+    pmu_imm_hp_clk_power_reg_t     clk_power;
+    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
+    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
+    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
+    pmu_imm_modem_icg_reg_t        modem_icg;
+    pmu_imm_lp_icg_reg_t           lp_icg;
+    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
+    pmu_imm_i2c_isolate_reg_t      i2c_iso;
+} pmu_imm_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t powerdown_timer: 9;
+        uint32_t powerup_timer  : 9;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t powerdown_timer: 9;
+        uint32_t powerup_timer  : 9;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_reset   : 1;
+        uint32_t force_iso     : 1;
+        uint32_t force_pu      : 1;
+        uint32_t force_no_reset: 1;
+        uint32_t force_no_iso  : 1;
+        uint32_t force_pd      : 1;
+        uint32_t reserved0     : 26;    /* Invalid of lp peripherals */
+    };
+    uint32_t val;
+} pmu_power_domain_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t pd_top_mask   : 5;
+        uint32_t reserved0     : 22;    /* Invalid of lp peripherals */
+        uint32_t top_pd_mask   : 5;
+    };
+    uint32_t val;
+} pmu_power_domain_mask_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_pu      :    1;
+        uint32_t force_pd      :    1;
+        uint32_t reserved2     :    30;
+    };
+    uint32_t val;
+} pmu_power_dcdc_switch_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_hp_pad_no_iso_all: 1;
+        uint32_t force_hp_pad_iso_all   : 1;
+        uint32_t reserved0              : 30;
+    };
+    uint32_t val;
+} pmu_power_hp_pad_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wait_xtal_stable: 16;
+        uint32_t wait_pll_stable : 16;
+    };
+    uint32_t val;
+} pmu_power_clk_wait_cntl_reg_t;
+
+typedef struct pmu_power_hw_regmap_t {
+    pmu_power_wait_timer0_reg_t    wait_timer0;
+    pmu_power_wait_timer1_reg_t    wait_timer1;
+    pmu_power_domain_cntl_reg_t    hp_pd[3];
+    pmu_power_domain_mask_reg_t    hp_pd_mask[3];
+    pmu_power_dcdc_switch_reg_t    dcdc_switch;
+    pmu_power_domain_cntl_reg_t    lp_peri;
+    pmu_power_domain_mask_reg_t    lp_peri_mask;
+    pmu_power_hp_pad_reg_t         hp_pad;
+    pmu_power_clk_wait_cntl_reg_t  clk_wait;
+} pmu_power_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject_ena: 31;
+        uint32_t slp_reject_en   : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_ena: 31;
+        uint32_t reserved0 : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl2_reg_t;
+
+typedef union {
+    struct {
+        uint32_t lp_min_slp_val: 8;
+        uint32_t hp_min_slp_val: 8;
+        uint32_t sleep_prt_sel : 2;
+        uint32_t reserved0     : 14;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl3_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0           : 31;
+        uint32_t slp_reject_cause_clr: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl4_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modem_wait_target : 20;
+        uint32_t reserved0         : 4;
+        uint32_t lp_ana_wait_target: 8;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl5_reg_t;
+
+typedef union {
+    struct {
+        uint32_t soc_wakeup_wait    : 20;
+        uint32_t reserved0          : 10;
+        uint32_t soc_wakeup_wait_cfg: 2;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl6_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 16;
+        uint32_t ana_wait_target: 16;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl7_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 31;
+        uint32_t lp_lite_wakeup_ena : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl8_reg_t;
+
+typedef struct pmu_wakeup_hw_regmap_t {
+    pmu_slp_wakeup_cntl0_reg_t     cntl0;
+    pmu_slp_wakeup_cntl1_reg_t     cntl1;
+    pmu_slp_wakeup_cntl2_reg_t     cntl2;
+    pmu_slp_wakeup_cntl3_reg_t     cntl3;
+    pmu_slp_wakeup_cntl4_reg_t     cntl4;
+    pmu_slp_wakeup_cntl5_reg_t     cntl5;
+    pmu_slp_wakeup_cntl6_reg_t     cntl6;
+    pmu_slp_wakeup_cntl7_reg_t     cntl7;
+    pmu_slp_wakeup_cntl8_reg_t     cntl8;
+    uint32_t                       status0;
+    uint32_t                       status1;
+    uint32_t                       status2;
+} pmu_wakeup_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t i2c_por_wait_target: 8;
+        uint32_t reserved0          : 24;
+    };
+    uint32_t val;
+} pmu_hp_clk_poweron_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modify_icg_cntl_wait: 8;
+        uint32_t switch_icg_cntl_wait: 8;
+        uint32_t reserved0           : 16;
+    };
+    uint32_t val;
+} pmu_hp_clk_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t por_done : 1;
+    };
+    uint32_t val;
+} pmu_por_status_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0     : 24;
+        uint32_t mspi_phy_xpd  : 1;
+        uint32_t sdio_pll_xpd  : 1;
+        uint32_t perif_i2c_rstb: 1;
+        uint32_t xpd_perif_i2c : 1;
+        uint32_t xpd_txrf_i2c  : 1;
+        uint32_t xpd_rfrx_pbus : 1;
+        uint32_t xpd_ckgen_i2c : 1;
+        uint32_t reserved1     : 1;
+    };
+    uint32_t val;
+} pmu_rf_pwc_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 31;
+        uint32_t backup_sysclk_nodiv: 1;
+    };
+    uint32_t val;
+} pmu_backup_cfg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0   : 14;
+        uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;
+        uint32_t reserved1   : 1;
+        uint32_t lp_exception: 1;
+        uint32_t sdio_idle: 1;
+        uint32_t sw       : 1;
+        uint32_t reject   : 1;
+        uint32_t wakeup   : 1;
+    };
+    uint32_t val;
+} pmu_hp_intr_reg_t;
+
+typedef struct pmu_hp_ext_hw_regmap_t {
+    pmu_hp_clk_poweron_reg_t   clk_poweron;
+    pmu_hp_clk_cntl_reg_t      clk_cntl;
+    pmu_por_status_reg_t       por_status;
+    pmu_rf_pwc_reg_t           rf_pwc;
+    pmu_backup_cfg_reg_t       backup_cfg;
+    pmu_hp_intr_reg_t          int_raw;
+    pmu_hp_intr_reg_t          int_st;
+    pmu_hp_intr_reg_t          int_ena;
+    pmu_hp_intr_reg_t          int_clr;
+} pmu_hp_ext_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0                    : 13;
+        uint32_t sleep_reject                 : 1;
+        uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;
+        uint32_t lp_wakeup                    : 1;
+        uint32_t sleep_switch_active_end      : 1;
+        uint32_t active_switch_sleep_end      : 1;
+        uint32_t sleep_switch_active_start    : 1;
+        uint32_t active_switch_sleep_start    : 1;
+        uint32_t hp_sw_trigger                : 1;
+    };
+    uint32_t val;
+} pmu_lp_intr_reg_t;
+
+typedef union {
+    struct {
+        uint32_t waiti_rdy         : 1;
+        uint32_t stall_rdy         : 1;
+        uint32_t reserved0         : 16;
+        uint32_t force_stall       : 1;
+        uint32_t slp_waiti_flag_en : 1;
+        uint32_t slp_stall_flag_en : 1;
+        uint32_t slp_stall_wait    : 8;
+        uint32_t slp_stall_en      : 1;
+        uint32_t slp_reset_en      : 1;
+        uint32_t slp_bypass_intr_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_en: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr2_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_cause: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr3_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr4_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject_cause: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr5_reg_t;
+
+typedef struct pmu_lp_ext_hw_regmap_t {
+    pmu_lp_intr_reg_t          int_raw;
+    pmu_lp_intr_reg_t          int_st;
+    pmu_lp_intr_reg_t          int_ena;
+    pmu_lp_intr_reg_t          int_clr;
+    pmu_lp_cpu_pwr0_reg_t      pwr0;
+    pmu_lp_cpu_pwr1_reg_t      pwr1;
+    pmu_lp_cpu_pwr2_reg_t      pwr2;
+    pmu_lp_cpu_pwr3_reg_t      pwr3;
+    pmu_lp_cpu_pwr4_reg_t      pwr4;
+    pmu_lp_cpu_pwr5_reg_t      pwr5;
+} pmu_lp_ext_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:7;
+        uint32_t force_tieh_sel:1;
+        uint32_t xpd:1;
+        uint32_t tieh_sel:3;
+        uint32_t tieh_pos_en:1;
+        uint32_t tieh_neg_en:1;
+        uint32_t tieh:1;
+        uint32_t target1:8;
+        uint32_t target0:8;
+        uint32_t ldo_cnt_prescaler_sel:1;
+    };
+    uint32_t val;
+} pmu_ext_ldo_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        uint32_t mul:3;
+        uint32_t en_vdet:1;
+        uint32_t en_cur_lim:1;
+        uint32_t dref:4;
+    };
+    uint32_t val;
+} pmu_ext_ldo_ana_reg_t;
+
+
+typedef struct pmu_ext_ldo_info_t {
+    pmu_ext_ldo_reg_t pmu_ext_ldo;
+    pmu_ext_ldo_ana_reg_t pmu_ext_ldo_ana;
+} pmu_ext_ldo_info_t;
+
+
+typedef union {
+    struct {
+        uint32_t on_req        : 1;
+        uint32_t off_req       : 1;
+        uint32_t lightslp_req  : 1;
+        uint32_t deepslp_req   : 1;
+        uint32_t reserved0     : 3;
+        uint32_t done_force    : 1;
+        uint32_t on_force_pu   : 1;
+        uint32_t on_force_pd   : 1;
+        uint32_t fb_res_force_pu   : 1;
+        uint32_t fb_res_force_pd   : 1;
+        uint32_t ls_force_pu   : 1;
+        uint32_t ls_force_pd   : 1;
+        uint32_t ds_force_pu   : 1;
+        uint32_t ds_force_pd   : 1;
+        uint32_t dcm_cur_st    : 8;
+        uint32_t reserved1     : 5;
+        uint32_t en_amux_test  : 1;
+        uint32_t reserved2     : 2;
+    };
+    uint32_t val;
+} pmu_dcm_ctrl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t pre_delay      : 8;
+        uint32_t res_off_delay  : 8;
+        uint32_t stable_delay   : 10;
+        uint32_t reserved0      : 6;
+    };
+    uint32_t val;
+} pmu_dcm_wait_delay_t;
+
+typedef union {
+    struct {
+        uint32_t ana_vddbat_mode    : 2;
+        uint32_t reserved1          : 29;
+        uint32_t sw_update          : 1;
+    };
+    uint32_t val;
+} pmu_vddbat_cfg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t wait_cycles    : 9;
+        uint32_t sleep_cycles   : 16;
+        uint32_t force_done     : 1;
+        uint32_t sleep_timer_en : 1;
+    };
+    uint32_t val;
+} pmu_touch_sensor_pwr_cntl_t;
+
+typedef struct pmu_dev_t {
+    volatile pmu_hp_hw_regmap_t     hp_sys[3];
+    volatile pmu_lp_hw_regmap_t     lp_sys[2];
+    volatile pmu_imm_hw_regmap_t    imm;
+    volatile pmu_power_hw_regmap_t  power;
+    volatile pmu_wakeup_hw_regmap_t wakeup;
+    volatile pmu_hp_ext_hw_regmap_t hp_ext;
+    volatile pmu_lp_ext_hw_regmap_t lp_ext;
+
+    union {
+        struct {
+            volatile uint32_t reserved0    : 30;
+            volatile uint32_t lp_trigger_hp: 1;
+            volatile uint32_t hp_trigger_lp: 1;
+        };
+        volatile uint32_t val;
+    } hp_lp_cpu_comm;
+
+    union {
+        struct {
+            volatile uint32_t reserved0           : 31;
+            volatile uint32_t dig_regulator_en_cal: 1;
+        };
+        volatile uint32_t val;
+    } hp_regulator_cfg;
+
+    union {
+        struct {
+            volatile uint32_t en_cali_pmu_cntl : 1;
+            volatile uint32_t reserved0 : 10;
+            volatile uint32_t last_st   : 7;
+            volatile uint32_t target_st : 7;
+            volatile uint32_t current_st: 7;
+        };
+        volatile uint32_t val;
+    } main_state;
+
+    union {
+        struct {
+            volatile uint32_t reserved0: 13;
+            volatile uint32_t backup_st: 5;
+            volatile uint32_t lp_pwr_st: 5;
+            volatile uint32_t hp_pwr_st: 9;
+        };
+        volatile int32_t val;
+    } pwr_state;
+
+    union {
+        struct {
+            volatile uint32_t stable_xpd_bbpll : 3;
+            volatile uint32_t stable_xpd_xtal  : 1;
+            volatile uint32_t ana_xpd_pll_i2c  : 3;
+            volatile uint32_t reserved0        : 3;
+            volatile uint32_t sysclk_slp_sel   : 1;
+            volatile uint32_t sysclk_sel       : 2;
+            volatile uint32_t sysclk_nodiv     : 1;
+            volatile uint32_t icg_sysclk_en    : 1;
+            volatile uint32_t icg_modem_switch : 1;
+            volatile uint32_t icg_modem_code   : 2;
+            volatile uint32_t icg_slp_sel      : 1;
+            volatile uint32_t icg_global_xtal  : 1;
+            volatile uint32_t icg_global_pll   : 4;
+            volatile uint32_t ana_i2c_iso_en   : 1;
+            volatile uint32_t ana_i2c_retention: 1;
+            volatile uint32_t reserved1        : 1;
+            volatile uint32_t ana_xpd_pll      : 4;
+            volatile uint32_t ana_xpd_xtal     : 1;
+        };
+        volatile uint32_t val;
+    } clk_state0;
+
+    volatile uint32_t clk_state1;
+    volatile uint32_t clk_state2;
+
+    volatile pmu_ext_ldo_info_t ext_ldo[6];
+
+    volatile uint32_t ext_wakeup_lv;
+    volatile uint32_t ext_wakeup_sel;
+    volatile uint32_t ext_wakeup_st;
+    union {
+        struct {
+            volatile uint32_t reserved0      : 30;
+            volatile uint32_t status_clr     : 1;
+            volatile uint32_t filter         : 1;
+        };
+        volatile uint32_t val;
+    } ext_wakeup_cntl;
+
+    union {
+        struct {
+            volatile uint32_t act_dnum   : 10;
+            volatile uint32_t reserved0  : 22;
+        };
+        volatile uint32_t val;
+    } sdio_wakeup_cntl;
+
+    union {
+        struct {
+            volatile uint32_t reserved0  : 16;
+            volatile uint32_t cnt_target : 16;
+        };
+        volatile uint32_t val;
+    } xtal_slp;
+
+    union {
+        struct {
+            volatile uint32_t reserved0  : 16;
+            volatile uint32_t hpcore1_stall_code : 8;
+            volatile uint32_t hpcore0_stall_code : 8;
+        };
+        volatile uint32_t val;
+    } cpu_sw_stall;
+
+    volatile pmu_dcm_ctrl_reg_t dcm_ctrl;
+    volatile pmu_dcm_wait_delay_t dcm_delay;
+    volatile pmu_vddbat_cfg_t vbat_cfg;
+    volatile pmu_touch_sensor_pwr_cntl_t touch_pwr_cntl;
+
+    union {
+        struct {
+            volatile uint32_t eco_result:1;
+            volatile uint32_t reserved0  : 30;
+            volatile uint32_t eco_en: 1;
+
+        };
+        volatile uint32_t val;
+    } pmu_rdn_eco;
+
+
+    uint32_t reserved[121];
+
+    union {
+        struct {
+            volatile uint32_t pmu_date: 31;
+            volatile uint32_t clk_en  : 1;
+        };
+        volatile uint32_t val;
+    } date;
+} pmu_dev_t;
+
+extern pmu_dev_t PMU;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
+
+_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_RDN_ECO_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h
new file mode 100644
index 0000000000..4d0f664733
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h
@@ -0,0 +1,1025 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of blend0_clut_data register
+ *  CLUT sram data read/write register in background plane of blender
+ */
+typedef union {
+    struct {
+        /** rdwr_word_blend0_clut : R/W; bitpos: [31:0]; default: 0;
+         *  Write and read data to/from CLUT RAM in background plane of blender engine through
+         *  this field in fifo mode.
+         */
+        uint32_t rdwr_word_blend0_clut:32;
+    };
+    uint32_t val;
+} ppa_blend0_clut_data_reg_t;
+
+/** Type of blend1_clut_data register
+ *  CLUT sram data read/write register in foreground plane of blender
+ */
+typedef union {
+    struct {
+        /** rdwr_word_blend1_clut : R/W; bitpos: [31:0]; default: 0;
+         *  Write and read data to/from CLUT RAM in foreground plane of blender engine through
+         *  this field in fifo mode.
+         */
+        uint32_t rdwr_word_blend1_clut:32;
+    };
+    uint32_t val;
+} ppa_blend1_clut_data_reg_t;
+
+/** Type of clut_conf register
+ *  CLUT configure register
+ */
+typedef union {
+    struct {
+        /** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
+         *  1'b0: fifo mode to wr/rd clut0/clut1 RAM through register
+         *  PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1:
+         *  memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr
+         *  should be 01 to access sr clut and should be 10 to access blend0 clut and should be
+         *  11 to access blend 1 clut in memory mode.
+         */
+        uint32_t apb_fifo_mask:1;
+        /** blend0_clut_mem_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0 to this bit to reset BLEND0 CLUT.
+         */
+        uint32_t blend0_clut_mem_rst:1;
+        /** blend1_clut_mem_rst : R/W; bitpos: [2]; default: 0;
+         *  Write 1 then write 0 to this bit to reset BLEND1 CLUT.
+         */
+        uint32_t blend1_clut_mem_rst:1;
+        /** blend0_clut_mem_rdaddr_rst : R/W; bitpos: [3]; default: 0;
+         *  Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode.
+         */
+        uint32_t blend0_clut_mem_rdaddr_rst:1;
+        /** blend1_clut_mem_rdaddr_rst : R/W; bitpos: [4]; default: 0;
+         *  Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode.
+         */
+        uint32_t blend1_clut_mem_rdaddr_rst:1;
+        /** blend0_clut_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  1: force power down BLEND CLUT memory.
+         */
+        uint32_t blend0_clut_mem_force_pd:1;
+        /** blend0_clut_mem_force_pu : R/W; bitpos: [6]; default: 0;
+         *  1: force power up BLEND CLUT memory.
+         */
+        uint32_t blend0_clut_mem_force_pu:1;
+        /** blend0_clut_mem_clk_ena : R/W; bitpos: [7]; default: 0;
+         *  1: Force clock on for BLEND CLUT memory.
+         */
+        uint32_t blend0_clut_mem_clk_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ppa_clut_conf_reg_t;
+
+/** Type of sr_color_mode register
+ *  Scaling and rotating engine color mode register
+ */
+typedef union {
+    struct {
+        /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0;
+         *  The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1:
+         *  RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved.
+         */
+        uint32_t sr_rx_cm:4;
+        /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0;
+         *  The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888.
+         *  1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved.
+         */
+        uint32_t sr_tx_cm:4;
+        /** yuv_rx_range : R/W; bitpos: [8]; default: 0;
+         *  YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range
+         */
+        uint32_t yuv_rx_range:1;
+        /** yuv_tx_range : R/W; bitpos: [9]; default: 0;
+         *  YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range
+         */
+        uint32_t yuv_tx_range:1;
+        /** yuv2rgb_protocal : R/W; bitpos: [10]; default: 0;
+         *  YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709
+         */
+        uint32_t yuv2rgb_protocal:1;
+        /** rgb2yuv_protocal : R/W; bitpos: [11]; default: 0;
+         *  RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
+         */
+        uint32_t rgb2yuv_protocal:1;
+        /** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0;
+         *  YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
+         */
+        uint32_t yuv422_rx_byte_order:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} ppa_sr_color_mode_reg_t;
+
+/** Type of blend_color_mode register
+ *  blending engine color mode register
+ */
+typedef union {
+    struct {
+        /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0;
+         *  The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2:
+         *  RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY
+         */
+        uint32_t blend0_rx_cm:4;
+        /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0;
+         *  The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2:
+         *  RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4.
+         */
+        uint32_t blend1_rx_cm:4;
+        /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0;
+         *  The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2:
+         *  RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY
+         */
+        uint32_t blend_tx_cm:4;
+        /** blend0_rx_yuv_range : R/W; bitpos: [12]; default: 0;
+         *  YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range
+         */
+        uint32_t blend0_rx_yuv_range:1;
+        /** blend_tx_yuv_range : R/W; bitpos: [13]; default: 0;
+         *  YUV output range when blend tx cm is yuv. 0: limit range. 1: full range
+         */
+        uint32_t blend_tx_yuv_range:1;
+        /** blend0_rx_yuv2rgb_protocal : R/W; bitpos: [14]; default: 0;
+         *  YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709
+         */
+        uint32_t blend0_rx_yuv2rgb_protocal:1;
+        /** blend_tx_rgb2yuv_protocal : R/W; bitpos: [15]; default: 0;
+         *  RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709
+         */
+        uint32_t blend_tx_rgb2yuv_protocal:1;
+        /** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0;
+         *  YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
+         */
+        uint32_t blend0_rx_yuv422_byte_order:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} ppa_blend_color_mode_reg_t;
+
+/** Type of sr_byte_order register
+ *  Scaling and rotating engine byte order register
+ */
+typedef union {
+    struct {
+        /** sr_rx_byte_swap_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+         *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+         */
+        uint32_t sr_rx_byte_swap_en:1;
+        /** sr_rx_rgb_swap_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+         *  would be swap to bgr.
+         */
+        uint32_t sr_rx_rgb_swap_en:1;
+        /** sr_macro_bk_ro_bypass : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to bypass the macro block order function. This function is used
+         *  to improve efficient accessing external memory.
+         */
+        uint32_t sr_macro_bk_ro_bypass:1;
+        /** sr_bk_size_sel : R/W; bitpos: [3]; default: 0;
+         *  sel srm pix_blk size, 0:32x32, 1:16x16
+         */
+        uint32_t sr_bk_size_sel:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ppa_sr_byte_order_reg_t;
+
+/** Type of blend_byte_order register
+ *  Blending engine byte order register
+ */
+typedef union {
+    struct {
+        /** blend0_rx_byte_swap_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+         *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+         */
+        uint32_t blend0_rx_byte_swap_en:1;
+        /** blend1_rx_byte_swap_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+         *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+         */
+        uint32_t blend1_rx_byte_swap_en:1;
+        /** blend0_rx_rgb_swap_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+         *  would be swap to bgr.
+         */
+        uint32_t blend0_rx_rgb_swap_en:1;
+        /** blend1_rx_rgb_swap_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+         *  would be swap to bgr.
+         */
+        uint32_t blend1_rx_rgb_swap_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ppa_blend_byte_order_reg_t;
+
+/** Type of blend_trans_mode register
+ *  Blending engine mode configure register
+ */
+typedef union {
+    struct {
+        /** blend_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable alpha blending.
+         */
+        uint32_t blend_en:1;
+        /** blend_bypass : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to bypass blender. Then background date would be output.
+         */
+        uint32_t blend_bypass:1;
+        /** blend_fix_pixel_fill_en : R/W; bitpos: [2]; default: 0;
+         *  This bit is used to enable fix pixel filling. When this mode is enable  only Tx
+         *  channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL.
+         */
+        uint32_t blend_fix_pixel_fill_en:1;
+        /** blend_trans_mode_update : WT; bitpos: [3]; default: 0;
+         *  Set this bit to update the transfer mode. Only the bit is set  the transfer mode is
+         *  valid.
+         */
+        uint32_t blend_trans_mode_update:1;
+        /** blend_rst : R/W; bitpos: [4]; default: 0;
+         *  write 1 then write 0 to reset blending engine.
+         */
+        uint32_t blend_rst:1;
+        /** blend_tx_inf_sel : R/W; bitpos: [6:5]; default: 0;
+         *  unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and
+         *  ls_enc
+         */
+        uint32_t blend_tx_inf_sel:2;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ppa_blend_trans_mode_reg_t;
+
+/** Type of sr_fix_alpha register
+ *  Scaling and rotating engine alpha override register
+ */
+typedef union {
+    struct {
+        /** sr_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128;
+         *  The value would replace the alpha value in received pixel for Scaling and Rotating
+         *  engine when PPA_SR_RX_ALPHA_CONF_EN is enabled.
+         */
+        uint32_t sr_rx_fix_alpha:8;
+        /** sr_rx_alpha_mod : R/W; bitpos: [9:8]; default: 0;
+         *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
+         *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+         */
+        uint32_t sr_rx_alpha_mod:2;
+        /** sr_rx_alpha_inv : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to invert the original alpha value. When RX color mode is
+         *  RGB565/RGB88. The original alpha value is 255.
+         */
+        uint32_t sr_rx_alpha_inv:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} ppa_sr_fix_alpha_reg_t;
+
+/** Type of blend_tx_size register
+ *  Fix pixel filling mode image size register
+ */
+typedef union {
+    struct {
+        /** blend_hb : R/W; bitpos: [13:0]; default: 0;
+         *  The horizontal width of image block that would be filled in fix pixel filling mode
+         *  or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420
+         */
+        uint32_t blend_hb:14;
+        /** blend_vb : R/W; bitpos: [27:14]; default: 0;
+         *  The vertical width of image block that would be filled in fix pixel filling mode or
+         *  blend mode. The unit is pixel. Must be even num when YUV420
+         */
+        uint32_t blend_vb:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ppa_blend_tx_size_reg_t;
+
+/** Type of blend_fix_alpha register
+ *  Blending engine alpha override register
+ */
+typedef union {
+    struct {
+        /** blend0_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128;
+         *  The value would replace the alpha value in received pixel for background plane of
+         *  blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled.
+         */
+        uint32_t blend0_rx_fix_alpha:8;
+        /** blend1_rx_fix_alpha : R/W; bitpos: [15:8]; default: 128;
+         *  The value would replace the alpha value in received pixel for foreground plane of
+         *  blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled.
+         */
+        uint32_t blend1_rx_fix_alpha:8;
+        /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0;
+         *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2:
+         *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+         */
+        uint32_t blend0_rx_alpha_mod:2;
+        /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0;
+         *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2:
+         *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+         */
+        uint32_t blend1_rx_alpha_mod:2;
+        /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to invert the original alpha value. When RX color mode is
+         *  RGB565/RGB88. The original alpha value is 255.
+         */
+        uint32_t blend0_rx_alpha_inv:1;
+        /** blend1_rx_alpha_inv : R/W; bitpos: [21]; default: 0;
+         *  Set this bit to invert the original alpha value. When RX color mode is
+         *  RGB565/RGB88. The original alpha value is 255.
+         */
+        uint32_t blend1_rx_alpha_inv:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} ppa_blend_fix_alpha_reg_t;
+
+/** Type of blend_rgb register
+ *  RGB color register
+ */
+typedef union {
+    struct {
+        /** blend1_rx_b : R/W; bitpos: [7:0]; default: 128;
+         *  blue color for A4/A8 mode.
+         */
+        uint32_t blend1_rx_b:8;
+        /** blend1_rx_g : R/W; bitpos: [15:8]; default: 128;
+         *  green color for A4/A8 mode.
+         */
+        uint32_t blend1_rx_g:8;
+        /** blend1_rx_r : R/W; bitpos: [23:16]; default: 128;
+         *  red color for A4/A8 mode.
+         */
+        uint32_t blend1_rx_r:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_blend_rgb_reg_t;
+
+/** Type of blend_fix_pixel register
+ *  Blending engine fix pixel register
+ */
+typedef union {
+    struct {
+        /** blend_tx_fix_pixel : R/W; bitpos: [31:0]; default: 0;
+         *  The configure fix pixel in fix pixel filling mode for blender engine.
+         */
+        uint32_t blend_tx_fix_pixel:32;
+    };
+    uint32_t val;
+} ppa_blend_fix_pixel_reg_t;
+
+/** Type of ck_fg_low register
+ *  foreground color key lower threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_fg_b_low : R/W; bitpos: [7:0]; default: 255;
+         *  color key lower threshold of foreground b channel
+         */
+        uint32_t colorkey_fg_b_low:8;
+        /** colorkey_fg_g_low : R/W; bitpos: [15:8]; default: 255;
+         *  color key lower threshold of foreground g channel
+         */
+        uint32_t colorkey_fg_g_low:8;
+        /** colorkey_fg_r_low : R/W; bitpos: [23:16]; default: 255;
+         *  color key lower threshold of foreground r channel
+         */
+        uint32_t colorkey_fg_r_low:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_fg_low_reg_t;
+
+/** Type of ck_fg_high register
+ *  foreground color key higher threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_fg_b_high : R/W; bitpos: [7:0]; default: 0;
+         *  color key higher threshold of foreground b channel
+         */
+        uint32_t colorkey_fg_b_high:8;
+        /** colorkey_fg_g_high : R/W; bitpos: [15:8]; default: 0;
+         *  color key higher threshold of foreground g channel
+         */
+        uint32_t colorkey_fg_g_high:8;
+        /** colorkey_fg_r_high : R/W; bitpos: [23:16]; default: 0;
+         *  color key higher threshold of foreground r channel
+         */
+        uint32_t colorkey_fg_r_high:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_fg_high_reg_t;
+
+/** Type of ck_bg_low register
+ *  background color key lower threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_bg_b_low : R/W; bitpos: [7:0]; default: 255;
+         *  color key lower threshold of background b channel
+         */
+        uint32_t colorkey_bg_b_low:8;
+        /** colorkey_bg_g_low : R/W; bitpos: [15:8]; default: 255;
+         *  color key lower threshold of background g channel
+         */
+        uint32_t colorkey_bg_g_low:8;
+        /** colorkey_bg_r_low : R/W; bitpos: [23:16]; default: 255;
+         *  color key lower threshold of background r channel
+         */
+        uint32_t colorkey_bg_r_low:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_bg_low_reg_t;
+
+/** Type of ck_bg_high register
+ *  background color key higher threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_bg_b_high : R/W; bitpos: [7:0]; default: 0;
+         *  color key higher threshold of background b channel
+         */
+        uint32_t colorkey_bg_b_high:8;
+        /** colorkey_bg_g_high : R/W; bitpos: [15:8]; default: 0;
+         *  color key higher threshold of background g channel
+         */
+        uint32_t colorkey_bg_g_high:8;
+        /** colorkey_bg_r_high : R/W; bitpos: [23:16]; default: 0;
+         *  color key higher threshold of background r channel
+         */
+        uint32_t colorkey_bg_r_high:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_bg_high_reg_t;
+
+/** Type of ck_default register
+ *  default value when foreground and background both in color key range
+ */
+typedef union {
+    struct {
+        /** colorkey_default_b : R/W; bitpos: [7:0]; default: 0;
+         *  default B channel value of color key
+         */
+        uint32_t colorkey_default_b:8;
+        /** colorkey_default_g : R/W; bitpos: [15:8]; default: 0;
+         *  default G channel value of color key
+         */
+        uint32_t colorkey_default_g:8;
+        /** colorkey_default_r : R/W; bitpos: [23:16]; default: 0;
+         *  default R channel value of color key
+         */
+        uint32_t colorkey_default_r:8;
+        /** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0;
+         *  when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the
+         *  result is fg
+         */
+        uint32_t colorkey_fg_bg_reverse:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} ppa_ck_default_reg_t;
+
+/** Type of sr_scal_rotate register
+ *  Scaling and rotating coefficient register
+ */
+typedef union {
+    struct {
+        /** sr_scal_x_int : R/W; bitpos: [7:0]; default: 1;
+         *  The integrated part of scaling coefficient in X direction.
+         */
+        uint32_t sr_scal_x_int:8;
+        /** sr_scal_x_frag : R/W; bitpos: [11:8]; default: 0;
+         *  The fragment part of scaling coefficient in X direction.
+         */
+        uint32_t sr_scal_x_frag:4;
+        /** sr_scal_y_int : R/W; bitpos: [19:12]; default: 1;
+         *  The integrated part of scaling coefficient in Y direction.
+         */
+        uint32_t sr_scal_y_int:8;
+        /** sr_scal_y_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The fragment part of scaling coefficient in Y direction.
+         */
+        uint32_t sr_scal_y_frag:4;
+        /** sr_rotate_angle : R/W; bitpos: [25:24]; default: 0;
+         *  The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree.
+         */
+        uint32_t sr_rotate_angle:2;
+        /** scal_rotate_rst : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset scaling and rotating engine.
+         */
+        uint32_t scal_rotate_rst:1;
+        /** scal_rotate_start : WT; bitpos: [27]; default: 0;
+         *  Write 1 to enable scaling and rotating engine after parameter is configured.
+         */
+        uint32_t scal_rotate_start:1;
+        /** sr_mirror_x : R/W; bitpos: [28]; default: 0;
+         *  Image mirror in X direction. 0: disable, 1: enable
+         */
+        uint32_t sr_mirror_x:1;
+        /** sr_mirror_y : R/W; bitpos: [29]; default: 0;
+         *  Image mirror in Y direction. 0: disable, 1: enable
+         */
+        uint32_t sr_mirror_y:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} ppa_sr_scal_rotate_reg_t;
+
+/** Type of sr_mem_pd register
+ *  SR memory power done register
+ */
+typedef union {
+    struct {
+        /** sr_mem_clk_ena : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force clock enable of scaling and rotating engine's data memory.
+         */
+        uint32_t sr_mem_clk_ena:1;
+        /** sr_mem_force_pd : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to force power down scaling and rotating engine's data memory.
+         */
+        uint32_t sr_mem_force_pd:1;
+        /** sr_mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power up scaling and rotating engine's data memory.
+         */
+        uint32_t sr_mem_force_pu:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_sr_mem_pd_reg_t;
+
+/** Type of reg_conf register
+ *  Register clock enable register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  PPA register clock gate enable signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ppa_reg_conf_reg_t;
+
+/** Type of eco_low register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_low:32;
+    };
+    uint32_t val;
+} ppa_eco_low_reg_t;
+
+/** Type of eco_high register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_high:32;
+    };
+    uint32_t val;
+} ppa_eco_high_reg_t;
+
+/** Type of sram_ctrl register
+ *  PPA SRAM Control Register
+ */
+typedef union {
+    struct {
+        /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  Control signals
+         */
+        uint32_t mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} ppa_sram_ctrl_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  Raw status interrupt
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when scaling and rotating engine
+         *  calculate one frame image.
+         */
+        uint32_t sr_eof_int_raw:1;
+        /** blend_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when blending engine calculate one frame
+         *  image.
+         */
+        uint32_t blend_eof_int_raw:1;
+        /** sr_param_cfg_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the configured scaling and rotating
+         *  coefficient is wrong. User can check the reasons through register
+         *  PPA_SR_PARAM_ERR_ST_REG.
+         */
+        uint32_t sr_param_cfg_err_int_raw:1;
+        /** blend_param_cfg_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when the configured blending coefficient
+         *  is wrong. User can check the reasons through register PPA_BLEND_ST_REG.
+         */
+        uint32_t blend_param_cfg_err_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ppa_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the PPA_SR_EOF_INT interrupt.
+         */
+        uint32_t sr_eof_int_st:1;
+        /** blend_eof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt.
+         */
+        uint32_t blend_eof_int_st:1;
+        /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt.
+         */
+        uint32_t sr_param_cfg_err_int_st:1;
+        /** blend_param_cfg_err_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
+         */
+        uint32_t blend_param_cfg_err_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ppa_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the PPA_SR_EOF_INT interrupt.
+         */
+        uint32_t sr_eof_int_ena:1;
+        /** blend_eof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt.
+         */
+        uint32_t blend_eof_int_ena:1;
+        /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt.
+         */
+        uint32_t sr_param_cfg_err_int_ena:1;
+        /** blend_param_cfg_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
+         */
+        uint32_t blend_param_cfg_err_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ppa_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the PPA_SR_EOF_INT interrupt.
+         */
+        uint32_t sr_eof_int_clr:1;
+        /** blend_eof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the PPA_BLEND_EOF_INT interrupt.
+         */
+        uint32_t blend_eof_int_clr:1;
+        /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt.
+         */
+        uint32_t sr_param_cfg_err_int_clr:1;
+        /** blend_param_cfg_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
+         */
+        uint32_t blend_param_cfg_err_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ppa_int_clr_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of clut_cnt register
+ *  BLEND CLUT write counter register
+ */
+typedef union {
+    struct {
+        /** blend0_clut_cnt : RO; bitpos: [8:0]; default: 0;
+         *  The write data counter of BLEND0 CLUT in fifo mode.
+         */
+        uint32_t blend0_clut_cnt:9;
+        /** blend1_clut_cnt : RO; bitpos: [17:9]; default: 0;
+         *  The write data counter of BLEND1 CLUT in fifo mode.
+         */
+        uint32_t blend1_clut_cnt:9;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} ppa_clut_cnt_reg_t;
+
+/** Type of blend_st register
+ *  Blending engine status register
+ */
+typedef union {
+    struct {
+        /** blend_size_diff_st : RO; bitpos: [0]; default: 0;
+         *  1: indicate the size of two image is different.
+         */
+        uint32_t blend_size_diff_st:1;
+        /** blend_yuv_x_scale_err_st : RO; bitpos: [1]; default: 0;
+         *  Represents that x param is an odd num when enable yuv422 or yuv420
+         */
+        uint32_t blend_yuv_x_scale_err_st:1;
+        /** blend_yuv_y_scale_err_st : RO; bitpos: [2]; default: 0;
+         *  Represents that y param is an odd num when enable yuv420
+         */
+        uint32_t blend_yuv_y_scale_err_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_blend_st_reg_t;
+
+/** Type of sr_param_err_st register
+ *  Scaling and rotating coefficient error register
+ */
+typedef union {
+    struct {
+        /** tx_dscr_vb_err_st : RO; bitpos: [0]; default: 0;
+         *  The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive
+         *  descriptor is larger than VA in 2DDMA receive descriptor.
+         */
+        uint32_t tx_dscr_vb_err_st:1;
+        /** tx_dscr_hb_err_st : RO; bitpos: [1]; default: 0;
+         *  The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive
+         *  descriptor is larger than HA in 2DDMA receive descriptor.
+         */
+        uint32_t tx_dscr_hb_err_st:1;
+        /** y_rx_scal_equal_0_err_st : RO; bitpos: [2]; default: 0;
+         *  The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0.
+         */
+        uint32_t y_rx_scal_equal_0_err_st:1;
+        /** rx_dscr_vb_err_st : RO; bitpos: [3]; default: 0;
+         *  The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in
+         *  2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor
+         */
+        uint32_t rx_dscr_vb_err_st:1;
+        /** ydst_len_too_samll_err_st : RO; bitpos: [4]; default: 0;
+         *  The error is that the scaled image width is 0. For example.  when source width is
+         *  14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as
+         *  the result would be floored.
+         */
+        uint32_t ydst_len_too_samll_err_st:1;
+        /** ydst_len_too_large_err_st : RO; bitpos: [5]; default: 0;
+         *  The error is that the scaled width is larger than (2^13 - 1).
+         */
+        uint32_t ydst_len_too_large_err_st:1;
+        /** x_rx_scal_equal_0_err_st : RO; bitpos: [6]; default: 0;
+         *  The error is that the scaled image height is 0.
+         */
+        uint32_t x_rx_scal_equal_0_err_st:1;
+        /** rx_dscr_hb_err_st : RO; bitpos: [7]; default: 0;
+         *  The error is that the HB in 2DDMA transmit descriptor plus the offset of X
+         *  coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit
+         *  descriptor.
+         */
+        uint32_t rx_dscr_hb_err_st:1;
+        /** xdst_len_too_samll_err_st : RO; bitpos: [8]; default: 0;
+         *  The error is that the scaled image height is 0. For example.  when source height is
+         *  14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as
+         *  the result would be floored.
+         */
+        uint32_t xdst_len_too_samll_err_st:1;
+        /** xdst_len_too_large_err_st : RO; bitpos: [9]; default: 0;
+         *  The error is that the scaled image height is larger than (2^13 - 1).
+         */
+        uint32_t xdst_len_too_large_err_st:1;
+        /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0;
+         *  The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
+         *  yuv422 or yuv420 rx
+         */
+        uint32_t x_yuv420_rx_scale_err_st:1;
+        /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0;
+         *  The error is that the va/vb/y param in dma2d descriptor is an odd num when enable
+         *  yuv420 rx
+         */
+        uint32_t y_yuv420_rx_scale_err_st:1;
+        /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0;
+         *  The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
+         *  yuv422 or yuv420 tx
+         */
+        uint32_t x_yuv420_tx_scale_err_st:1;
+        /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0;
+         *  The error is that the va/vb/y param in dma2d descriptor is an odd num when enable
+         *  yuv420 tx
+         */
+        uint32_t y_yuv420_tx_scale_err_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} ppa_sr_param_err_st_reg_t;
+
+/** Type of sr_status register
+ *  SR FSM register
+ */
+typedef union {
+    struct {
+        /** sr_rx_dscr_sample_state : RO; bitpos: [1:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_rx_dscr_sample_state:2;
+        /** sr_rx_scan_state : RO; bitpos: [3:2]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_rx_scan_state:2;
+        /** sr_tx_dscr_sample_state : RO; bitpos: [5:4]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_tx_dscr_sample_state:2;
+        /** sr_tx_scan_state : RO; bitpos: [8:6]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_tx_scan_state:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} ppa_sr_status_reg_t;
+
+/** Type of eco_cell_ctrl register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rdn_result : RO; bitpos: [0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_result:1;
+        /** rdn_ena : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ppa_eco_cell_ctrl_reg_t;
+
+
+/** Group: Debug Register */
+/** Type of debug_ctrl0 register
+ *  debug register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx
+         *  bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6:
+         *  blend output
+         */
+        uint32_t dbg_replace_sel:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_debug_ctrl0_reg_t;
+
+/** Type of debug_ctrl1 register
+ *  debug register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_data : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the replace data
+         */
+        uint32_t dbg_replace_data:32;
+    };
+    uint32_t val;
+} ppa_debug_ctrl1_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of rgb2gray register
+ *  rgb2gray register
+ */
+typedef union {
+    struct {
+        /** rgb2gray_b : R/W; bitpos: [7:0]; default: 85;
+         *  Configures the b parameter for rgb2gray
+         */
+        uint32_t rgb2gray_b:8;
+        /** rgb2gray_g : R/W; bitpos: [15:8]; default: 86;
+         *  Configures the g parameter for rgb2gray
+         */
+        uint32_t rgb2gray_g:8;
+        /** rgb2gray_r : R/W; bitpos: [23:16]; default: 85;
+         *  Configures the r parameter for rgb2gray
+         */
+        uint32_t rgb2gray_r:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_rgb2gray_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  PPA Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 539234848;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} ppa_date_reg_t;
+
+
+typedef struct ppa_dev_t {
+    volatile ppa_blend0_clut_data_reg_t blend0_clut_data;
+    volatile ppa_blend1_clut_data_reg_t blend1_clut_data;
+    uint32_t reserved_008;
+    volatile ppa_clut_conf_reg_t clut_conf;
+    volatile ppa_int_raw_reg_t int_raw;
+    volatile ppa_int_st_reg_t int_st;
+    volatile ppa_int_ena_reg_t int_ena;
+    volatile ppa_int_clr_reg_t int_clr;
+    volatile ppa_sr_color_mode_reg_t sr_color_mode;
+    volatile ppa_blend_color_mode_reg_t blend_color_mode;
+    volatile ppa_sr_byte_order_reg_t sr_byte_order;
+    volatile ppa_blend_byte_order_reg_t blend_byte_order;
+    uint32_t reserved_030;
+    volatile ppa_blend_trans_mode_reg_t blend_trans_mode;
+    volatile ppa_sr_fix_alpha_reg_t sr_fix_alpha;
+    volatile ppa_blend_tx_size_reg_t blend_tx_size;
+    volatile ppa_blend_fix_alpha_reg_t blend_fix_alpha;
+    uint32_t reserved_044;
+    volatile ppa_blend_rgb_reg_t blend_rgb;
+    volatile ppa_blend_fix_pixel_reg_t blend_fix_pixel;
+    volatile ppa_ck_fg_low_reg_t ck_fg_low;
+    volatile ppa_ck_fg_high_reg_t ck_fg_high;
+    volatile ppa_ck_bg_low_reg_t ck_bg_low;
+    volatile ppa_ck_bg_high_reg_t ck_bg_high;
+    volatile ppa_ck_default_reg_t ck_default;
+    volatile ppa_sr_scal_rotate_reg_t sr_scal_rotate;
+    volatile ppa_sr_mem_pd_reg_t sr_mem_pd;
+    volatile ppa_reg_conf_reg_t reg_conf;
+    volatile ppa_clut_cnt_reg_t clut_cnt;
+    volatile ppa_blend_st_reg_t blend_st;
+    volatile ppa_sr_param_err_st_reg_t sr_param_err_st;
+    volatile ppa_sr_status_reg_t sr_status;
+    volatile ppa_eco_low_reg_t eco_low;
+    volatile ppa_eco_high_reg_t eco_high;
+    volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl;
+    volatile ppa_sram_ctrl_reg_t sram_ctrl;
+    volatile ppa_debug_ctrl0_reg_t debug_ctrl0;
+    volatile ppa_debug_ctrl1_reg_t debug_ctrl1;
+    volatile ppa_rgb2gray_reg_t rgb2gray;
+    uint32_t reserved_09c[25];
+    volatile ppa_date_reg_t date;
+} ppa_dev_t;
+
+extern ppa_dev_t PPA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ppa_dev_t) == 0x104, "Invalid size of ppa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h
new file mode 100644
index 0000000000..f843b5b49d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h
@@ -0,0 +1,1185 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PPA_BLEND0_CLUT_DATA_REG register
+ *  CLUT sram data read/write register in background plane of blender
+ */
+#define PPA_BLEND0_CLUT_DATA_REG (DR_REG_PPA_BASE + 0x0)
+/** PPA_RDWR_WORD_BLEND0_CLUT : R/W; bitpos: [31:0]; default: 0;
+ *  Write and read data to/from CLUT RAM in background plane of blender engine through
+ *  this field in fifo mode.
+ */
+#define PPA_RDWR_WORD_BLEND0_CLUT    0xFFFFFFFFU
+#define PPA_RDWR_WORD_BLEND0_CLUT_M  (PPA_RDWR_WORD_BLEND0_CLUT_V << PPA_RDWR_WORD_BLEND0_CLUT_S)
+#define PPA_RDWR_WORD_BLEND0_CLUT_V  0xFFFFFFFFU
+#define PPA_RDWR_WORD_BLEND0_CLUT_S  0
+
+/** PPA_BLEND1_CLUT_DATA_REG register
+ *  CLUT sram data read/write register in foreground plane of blender
+ */
+#define PPA_BLEND1_CLUT_DATA_REG (DR_REG_PPA_BASE + 0x4)
+/** PPA_RDWR_WORD_BLEND1_CLUT : R/W; bitpos: [31:0]; default: 0;
+ *  Write and read data to/from CLUT RAM in foreground plane of blender engine through
+ *  this field in fifo mode.
+ */
+#define PPA_RDWR_WORD_BLEND1_CLUT    0xFFFFFFFFU
+#define PPA_RDWR_WORD_BLEND1_CLUT_M  (PPA_RDWR_WORD_BLEND1_CLUT_V << PPA_RDWR_WORD_BLEND1_CLUT_S)
+#define PPA_RDWR_WORD_BLEND1_CLUT_V  0xFFFFFFFFU
+#define PPA_RDWR_WORD_BLEND1_CLUT_S  0
+
+/** PPA_CLUT_CONF_REG register
+ *  CLUT configure register
+ */
+#define PPA_CLUT_CONF_REG (DR_REG_PPA_BASE + 0xc)
+/** PPA_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0;
+ *  1'b0: fifo mode to wr/rd clut0/clut1 RAM through register
+ *  PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1:
+ *  memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr
+ *  should be 01 to access sr clut and should be 10 to access blend0 clut and should be
+ *  11 to access blend 1 clut in memory mode.
+ */
+#define PPA_APB_FIFO_MASK    (BIT(0))
+#define PPA_APB_FIFO_MASK_M  (PPA_APB_FIFO_MASK_V << PPA_APB_FIFO_MASK_S)
+#define PPA_APB_FIFO_MASK_V  0x00000001U
+#define PPA_APB_FIFO_MASK_S  0
+/** PPA_BLEND0_CLUT_MEM_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0 to this bit to reset BLEND0 CLUT.
+ */
+#define PPA_BLEND0_CLUT_MEM_RST    (BIT(1))
+#define PPA_BLEND0_CLUT_MEM_RST_M  (PPA_BLEND0_CLUT_MEM_RST_V << PPA_BLEND0_CLUT_MEM_RST_S)
+#define PPA_BLEND0_CLUT_MEM_RST_V  0x00000001U
+#define PPA_BLEND0_CLUT_MEM_RST_S  1
+/** PPA_BLEND1_CLUT_MEM_RST : R/W; bitpos: [2]; default: 0;
+ *  Write 1 then write 0 to this bit to reset BLEND1 CLUT.
+ */
+#define PPA_BLEND1_CLUT_MEM_RST    (BIT(2))
+#define PPA_BLEND1_CLUT_MEM_RST_M  (PPA_BLEND1_CLUT_MEM_RST_V << PPA_BLEND1_CLUT_MEM_RST_S)
+#define PPA_BLEND1_CLUT_MEM_RST_V  0x00000001U
+#define PPA_BLEND1_CLUT_MEM_RST_S  2
+/** PPA_BLEND0_CLUT_MEM_RDADDR_RST : R/W; bitpos: [3]; default: 0;
+ *  Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode.
+ */
+#define PPA_BLEND0_CLUT_MEM_RDADDR_RST    (BIT(3))
+#define PPA_BLEND0_CLUT_MEM_RDADDR_RST_M  (PPA_BLEND0_CLUT_MEM_RDADDR_RST_V << PPA_BLEND0_CLUT_MEM_RDADDR_RST_S)
+#define PPA_BLEND0_CLUT_MEM_RDADDR_RST_V  0x00000001U
+#define PPA_BLEND0_CLUT_MEM_RDADDR_RST_S  3
+/** PPA_BLEND1_CLUT_MEM_RDADDR_RST : R/W; bitpos: [4]; default: 0;
+ *  Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode.
+ */
+#define PPA_BLEND1_CLUT_MEM_RDADDR_RST    (BIT(4))
+#define PPA_BLEND1_CLUT_MEM_RDADDR_RST_M  (PPA_BLEND1_CLUT_MEM_RDADDR_RST_V << PPA_BLEND1_CLUT_MEM_RDADDR_RST_S)
+#define PPA_BLEND1_CLUT_MEM_RDADDR_RST_V  0x00000001U
+#define PPA_BLEND1_CLUT_MEM_RDADDR_RST_S  4
+/** PPA_BLEND0_CLUT_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  1: force power down BLEND CLUT memory.
+ */
+#define PPA_BLEND0_CLUT_MEM_FORCE_PD    (BIT(5))
+#define PPA_BLEND0_CLUT_MEM_FORCE_PD_M  (PPA_BLEND0_CLUT_MEM_FORCE_PD_V << PPA_BLEND0_CLUT_MEM_FORCE_PD_S)
+#define PPA_BLEND0_CLUT_MEM_FORCE_PD_V  0x00000001U
+#define PPA_BLEND0_CLUT_MEM_FORCE_PD_S  5
+/** PPA_BLEND0_CLUT_MEM_FORCE_PU : R/W; bitpos: [6]; default: 0;
+ *  1: force power up BLEND CLUT memory.
+ */
+#define PPA_BLEND0_CLUT_MEM_FORCE_PU    (BIT(6))
+#define PPA_BLEND0_CLUT_MEM_FORCE_PU_M  (PPA_BLEND0_CLUT_MEM_FORCE_PU_V << PPA_BLEND0_CLUT_MEM_FORCE_PU_S)
+#define PPA_BLEND0_CLUT_MEM_FORCE_PU_V  0x00000001U
+#define PPA_BLEND0_CLUT_MEM_FORCE_PU_S  6
+/** PPA_BLEND0_CLUT_MEM_CLK_ENA : R/W; bitpos: [7]; default: 0;
+ *  1: Force clock on for BLEND CLUT memory.
+ */
+#define PPA_BLEND0_CLUT_MEM_CLK_ENA    (BIT(7))
+#define PPA_BLEND0_CLUT_MEM_CLK_ENA_M  (PPA_BLEND0_CLUT_MEM_CLK_ENA_V << PPA_BLEND0_CLUT_MEM_CLK_ENA_S)
+#define PPA_BLEND0_CLUT_MEM_CLK_ENA_V  0x00000001U
+#define PPA_BLEND0_CLUT_MEM_CLK_ENA_S  7
+
+/** PPA_INT_RAW_REG register
+ *  Raw status interrupt
+ */
+#define PPA_INT_RAW_REG (DR_REG_PPA_BASE + 0x10)
+/** PPA_SR_EOF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when scaling and rotating engine
+ *  calculate one frame image.
+ */
+#define PPA_SR_EOF_INT_RAW    (BIT(0))
+#define PPA_SR_EOF_INT_RAW_M  (PPA_SR_EOF_INT_RAW_V << PPA_SR_EOF_INT_RAW_S)
+#define PPA_SR_EOF_INT_RAW_V  0x00000001U
+#define PPA_SR_EOF_INT_RAW_S  0
+/** PPA_BLEND_EOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when blending engine calculate one frame
+ *  image.
+ */
+#define PPA_BLEND_EOF_INT_RAW    (BIT(1))
+#define PPA_BLEND_EOF_INT_RAW_M  (PPA_BLEND_EOF_INT_RAW_V << PPA_BLEND_EOF_INT_RAW_S)
+#define PPA_BLEND_EOF_INT_RAW_V  0x00000001U
+#define PPA_BLEND_EOF_INT_RAW_S  1
+/** PPA_SR_PARAM_CFG_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the configured scaling and rotating
+ *  coefficient is wrong. User can check the reasons through register
+ *  PPA_SR_PARAM_ERR_ST_REG.
+ */
+#define PPA_SR_PARAM_CFG_ERR_INT_RAW    (BIT(2))
+#define PPA_SR_PARAM_CFG_ERR_INT_RAW_M  (PPA_SR_PARAM_CFG_ERR_INT_RAW_V << PPA_SR_PARAM_CFG_ERR_INT_RAW_S)
+#define PPA_SR_PARAM_CFG_ERR_INT_RAW_V  0x00000001U
+#define PPA_SR_PARAM_CFG_ERR_INT_RAW_S  2
+/** PPA_BLEND_PARAM_CFG_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when the configured blending coefficient
+ *  is wrong. User can check the reasons through register PPA_BLEND_ST_REG.
+ */
+#define PPA_BLEND_PARAM_CFG_ERR_INT_RAW    (BIT(3))
+#define PPA_BLEND_PARAM_CFG_ERR_INT_RAW_M  (PPA_BLEND_PARAM_CFG_ERR_INT_RAW_V << PPA_BLEND_PARAM_CFG_ERR_INT_RAW_S)
+#define PPA_BLEND_PARAM_CFG_ERR_INT_RAW_V  0x00000001U
+#define PPA_BLEND_PARAM_CFG_ERR_INT_RAW_S  3
+
+/** PPA_INT_ST_REG register
+ *  Masked interrupt
+ */
+#define PPA_INT_ST_REG (DR_REG_PPA_BASE + 0x14)
+/** PPA_SR_EOF_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the PPA_SR_EOF_INT interrupt.
+ */
+#define PPA_SR_EOF_INT_ST    (BIT(0))
+#define PPA_SR_EOF_INT_ST_M  (PPA_SR_EOF_INT_ST_V << PPA_SR_EOF_INT_ST_S)
+#define PPA_SR_EOF_INT_ST_V  0x00000001U
+#define PPA_SR_EOF_INT_ST_S  0
+/** PPA_BLEND_EOF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt.
+ */
+#define PPA_BLEND_EOF_INT_ST    (BIT(1))
+#define PPA_BLEND_EOF_INT_ST_M  (PPA_BLEND_EOF_INT_ST_V << PPA_BLEND_EOF_INT_ST_S)
+#define PPA_BLEND_EOF_INT_ST_V  0x00000001U
+#define PPA_BLEND_EOF_INT_ST_S  1
+/** PPA_SR_PARAM_CFG_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt.
+ */
+#define PPA_SR_PARAM_CFG_ERR_INT_ST    (BIT(2))
+#define PPA_SR_PARAM_CFG_ERR_INT_ST_M  (PPA_SR_PARAM_CFG_ERR_INT_ST_V << PPA_SR_PARAM_CFG_ERR_INT_ST_S)
+#define PPA_SR_PARAM_CFG_ERR_INT_ST_V  0x00000001U
+#define PPA_SR_PARAM_CFG_ERR_INT_ST_S  2
+/** PPA_BLEND_PARAM_CFG_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
+ */
+#define PPA_BLEND_PARAM_CFG_ERR_INT_ST    (BIT(3))
+#define PPA_BLEND_PARAM_CFG_ERR_INT_ST_M  (PPA_BLEND_PARAM_CFG_ERR_INT_ST_V << PPA_BLEND_PARAM_CFG_ERR_INT_ST_S)
+#define PPA_BLEND_PARAM_CFG_ERR_INT_ST_V  0x00000001U
+#define PPA_BLEND_PARAM_CFG_ERR_INT_ST_S  3
+
+/** PPA_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define PPA_INT_ENA_REG (DR_REG_PPA_BASE + 0x18)
+/** PPA_SR_EOF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the PPA_SR_EOF_INT interrupt.
+ */
+#define PPA_SR_EOF_INT_ENA    (BIT(0))
+#define PPA_SR_EOF_INT_ENA_M  (PPA_SR_EOF_INT_ENA_V << PPA_SR_EOF_INT_ENA_S)
+#define PPA_SR_EOF_INT_ENA_V  0x00000001U
+#define PPA_SR_EOF_INT_ENA_S  0
+/** PPA_BLEND_EOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt.
+ */
+#define PPA_BLEND_EOF_INT_ENA    (BIT(1))
+#define PPA_BLEND_EOF_INT_ENA_M  (PPA_BLEND_EOF_INT_ENA_V << PPA_BLEND_EOF_INT_ENA_S)
+#define PPA_BLEND_EOF_INT_ENA_V  0x00000001U
+#define PPA_BLEND_EOF_INT_ENA_S  1
+/** PPA_SR_PARAM_CFG_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt.
+ */
+#define PPA_SR_PARAM_CFG_ERR_INT_ENA    (BIT(2))
+#define PPA_SR_PARAM_CFG_ERR_INT_ENA_M  (PPA_SR_PARAM_CFG_ERR_INT_ENA_V << PPA_SR_PARAM_CFG_ERR_INT_ENA_S)
+#define PPA_SR_PARAM_CFG_ERR_INT_ENA_V  0x00000001U
+#define PPA_SR_PARAM_CFG_ERR_INT_ENA_S  2
+/** PPA_BLEND_PARAM_CFG_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
+ */
+#define PPA_BLEND_PARAM_CFG_ERR_INT_ENA    (BIT(3))
+#define PPA_BLEND_PARAM_CFG_ERR_INT_ENA_M  (PPA_BLEND_PARAM_CFG_ERR_INT_ENA_V << PPA_BLEND_PARAM_CFG_ERR_INT_ENA_S)
+#define PPA_BLEND_PARAM_CFG_ERR_INT_ENA_V  0x00000001U
+#define PPA_BLEND_PARAM_CFG_ERR_INT_ENA_S  3
+
+/** PPA_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define PPA_INT_CLR_REG (DR_REG_PPA_BASE + 0x1c)
+/** PPA_SR_EOF_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the PPA_SR_EOF_INT interrupt.
+ */
+#define PPA_SR_EOF_INT_CLR    (BIT(0))
+#define PPA_SR_EOF_INT_CLR_M  (PPA_SR_EOF_INT_CLR_V << PPA_SR_EOF_INT_CLR_S)
+#define PPA_SR_EOF_INT_CLR_V  0x00000001U
+#define PPA_SR_EOF_INT_CLR_S  0
+/** PPA_BLEND_EOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the PPA_BLEND_EOF_INT interrupt.
+ */
+#define PPA_BLEND_EOF_INT_CLR    (BIT(1))
+#define PPA_BLEND_EOF_INT_CLR_M  (PPA_BLEND_EOF_INT_CLR_V << PPA_BLEND_EOF_INT_CLR_S)
+#define PPA_BLEND_EOF_INT_CLR_V  0x00000001U
+#define PPA_BLEND_EOF_INT_CLR_S  1
+/** PPA_SR_PARAM_CFG_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt.
+ */
+#define PPA_SR_PARAM_CFG_ERR_INT_CLR    (BIT(2))
+#define PPA_SR_PARAM_CFG_ERR_INT_CLR_M  (PPA_SR_PARAM_CFG_ERR_INT_CLR_V << PPA_SR_PARAM_CFG_ERR_INT_CLR_S)
+#define PPA_SR_PARAM_CFG_ERR_INT_CLR_V  0x00000001U
+#define PPA_SR_PARAM_CFG_ERR_INT_CLR_S  2
+/** PPA_BLEND_PARAM_CFG_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
+ */
+#define PPA_BLEND_PARAM_CFG_ERR_INT_CLR    (BIT(3))
+#define PPA_BLEND_PARAM_CFG_ERR_INT_CLR_M  (PPA_BLEND_PARAM_CFG_ERR_INT_CLR_V << PPA_BLEND_PARAM_CFG_ERR_INT_CLR_S)
+#define PPA_BLEND_PARAM_CFG_ERR_INT_CLR_V  0x00000001U
+#define PPA_BLEND_PARAM_CFG_ERR_INT_CLR_S  3
+
+/** PPA_SR_COLOR_MODE_REG register
+ *  Scaling and rotating engine color mode register
+ */
+#define PPA_SR_COLOR_MODE_REG (DR_REG_PPA_BASE + 0x20)
+/** PPA_SR_RX_CM : R/W; bitpos: [3:0]; default: 0;
+ *  The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1:
+ *  RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved.
+ */
+#define PPA_SR_RX_CM    0x0000000FU
+#define PPA_SR_RX_CM_M  (PPA_SR_RX_CM_V << PPA_SR_RX_CM_S)
+#define PPA_SR_RX_CM_V  0x0000000FU
+#define PPA_SR_RX_CM_S  0
+/** PPA_SR_TX_CM : R/W; bitpos: [7:4]; default: 0;
+ *  The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888.
+ *  1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved.
+ */
+#define PPA_SR_TX_CM    0x0000000FU
+#define PPA_SR_TX_CM_M  (PPA_SR_TX_CM_V << PPA_SR_TX_CM_S)
+#define PPA_SR_TX_CM_V  0x0000000FU
+#define PPA_SR_TX_CM_S  4
+/** PPA_YUV_RX_RANGE : R/W; bitpos: [8]; default: 0;
+ *  YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range
+ */
+#define PPA_YUV_RX_RANGE    (BIT(8))
+#define PPA_YUV_RX_RANGE_M  (PPA_YUV_RX_RANGE_V << PPA_YUV_RX_RANGE_S)
+#define PPA_YUV_RX_RANGE_V  0x00000001U
+#define PPA_YUV_RX_RANGE_S  8
+/** PPA_YUV_TX_RANGE : R/W; bitpos: [9]; default: 0;
+ *  YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range
+ */
+#define PPA_YUV_TX_RANGE    (BIT(9))
+#define PPA_YUV_TX_RANGE_M  (PPA_YUV_TX_RANGE_V << PPA_YUV_TX_RANGE_S)
+#define PPA_YUV_TX_RANGE_V  0x00000001U
+#define PPA_YUV_TX_RANGE_S  9
+/** PPA_YUV2RGB_PROTOCAL : R/W; bitpos: [10]; default: 0;
+ *  YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709
+ */
+#define PPA_YUV2RGB_PROTOCAL    (BIT(10))
+#define PPA_YUV2RGB_PROTOCAL_M  (PPA_YUV2RGB_PROTOCAL_V << PPA_YUV2RGB_PROTOCAL_S)
+#define PPA_YUV2RGB_PROTOCAL_V  0x00000001U
+#define PPA_YUV2RGB_PROTOCAL_S  10
+/** PPA_RGB2YUV_PROTOCAL : R/W; bitpos: [11]; default: 0;
+ *  RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
+ */
+#define PPA_RGB2YUV_PROTOCAL    (BIT(11))
+#define PPA_RGB2YUV_PROTOCAL_M  (PPA_RGB2YUV_PROTOCAL_V << PPA_RGB2YUV_PROTOCAL_S)
+#define PPA_RGB2YUV_PROTOCAL_V  0x00000001U
+#define PPA_RGB2YUV_PROTOCAL_S  11
+/** PPA_YUV422_RX_BYTE_ORDER : R/W; bitpos: [13:12]; default: 0;
+ *  YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
+ */
+#define PPA_YUV422_RX_BYTE_ORDER    0x00000003U
+#define PPA_YUV422_RX_BYTE_ORDER_M  (PPA_YUV422_RX_BYTE_ORDER_V << PPA_YUV422_RX_BYTE_ORDER_S)
+#define PPA_YUV422_RX_BYTE_ORDER_V  0x00000003U
+#define PPA_YUV422_RX_BYTE_ORDER_S  12
+
+/** PPA_BLEND_COLOR_MODE_REG register
+ *  blending engine color mode register
+ */
+#define PPA_BLEND_COLOR_MODE_REG (DR_REG_PPA_BASE + 0x24)
+/** PPA_BLEND0_RX_CM : R/W; bitpos: [3:0]; default: 0;
+ *  The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2:
+ *  RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY
+ */
+#define PPA_BLEND0_RX_CM    0x0000000FU
+#define PPA_BLEND0_RX_CM_M  (PPA_BLEND0_RX_CM_V << PPA_BLEND0_RX_CM_S)
+#define PPA_BLEND0_RX_CM_V  0x0000000FU
+#define PPA_BLEND0_RX_CM_S  0
+/** PPA_BLEND1_RX_CM : R/W; bitpos: [7:4]; default: 0;
+ *  The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2:
+ *  RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4.
+ */
+#define PPA_BLEND1_RX_CM    0x0000000FU
+#define PPA_BLEND1_RX_CM_M  (PPA_BLEND1_RX_CM_V << PPA_BLEND1_RX_CM_S)
+#define PPA_BLEND1_RX_CM_V  0x0000000FU
+#define PPA_BLEND1_RX_CM_S  4
+/** PPA_BLEND_TX_CM : R/W; bitpos: [11:8]; default: 0;
+ *  The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2:
+ *  RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY
+ */
+#define PPA_BLEND_TX_CM    0x0000000FU
+#define PPA_BLEND_TX_CM_M  (PPA_BLEND_TX_CM_V << PPA_BLEND_TX_CM_S)
+#define PPA_BLEND_TX_CM_V  0x0000000FU
+#define PPA_BLEND_TX_CM_S  8
+/** PPA_BLEND0_RX_YUV_RANGE : R/W; bitpos: [12]; default: 0;
+ *  YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range
+ */
+#define PPA_BLEND0_RX_YUV_RANGE    (BIT(12))
+#define PPA_BLEND0_RX_YUV_RANGE_M  (PPA_BLEND0_RX_YUV_RANGE_V << PPA_BLEND0_RX_YUV_RANGE_S)
+#define PPA_BLEND0_RX_YUV_RANGE_V  0x00000001U
+#define PPA_BLEND0_RX_YUV_RANGE_S  12
+/** PPA_BLEND_TX_YUV_RANGE : R/W; bitpos: [13]; default: 0;
+ *  YUV output range when blend tx cm is yuv. 0: limit range. 1: full range
+ */
+#define PPA_BLEND_TX_YUV_RANGE    (BIT(13))
+#define PPA_BLEND_TX_YUV_RANGE_M  (PPA_BLEND_TX_YUV_RANGE_V << PPA_BLEND_TX_YUV_RANGE_S)
+#define PPA_BLEND_TX_YUV_RANGE_V  0x00000001U
+#define PPA_BLEND_TX_YUV_RANGE_S  13
+/** PPA_BLEND0_RX_YUV2RGB_PROTOCAL : R/W; bitpos: [14]; default: 0;
+ *  YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709
+ */
+#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL    (BIT(14))
+#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_M  (PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S)
+#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V  0x00000001U
+#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S  14
+/** PPA_BLEND_TX_RGB2YUV_PROTOCAL : R/W; bitpos: [15]; default: 0;
+ *  RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709
+ */
+#define PPA_BLEND_TX_RGB2YUV_PROTOCAL    (BIT(15))
+#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_M  (PPA_BLEND_TX_RGB2YUV_PROTOCAL_V << PPA_BLEND_TX_RGB2YUV_PROTOCAL_S)
+#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_V  0x00000001U
+#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_S  15
+/** PPA_BLEND0_RX_YUV422_BYTE_ORDER : R/W; bitpos: [17:16]; default: 0;
+ *  YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
+ */
+#define PPA_BLEND0_RX_YUV422_BYTE_ORDER    0x00000003U
+#define PPA_BLEND0_RX_YUV422_BYTE_ORDER_M  (PPA_BLEND0_RX_YUV422_BYTE_ORDER_V << PPA_BLEND0_RX_YUV422_BYTE_ORDER_S)
+#define PPA_BLEND0_RX_YUV422_BYTE_ORDER_V  0x00000003U
+#define PPA_BLEND0_RX_YUV422_BYTE_ORDER_S  16
+
+/** PPA_SR_BYTE_ORDER_REG register
+ *  Scaling and rotating engine byte order register
+ */
+#define PPA_SR_BYTE_ORDER_REG (DR_REG_PPA_BASE + 0x28)
+/** PPA_SR_RX_BYTE_SWAP_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+ *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+ */
+#define PPA_SR_RX_BYTE_SWAP_EN    (BIT(0))
+#define PPA_SR_RX_BYTE_SWAP_EN_M  (PPA_SR_RX_BYTE_SWAP_EN_V << PPA_SR_RX_BYTE_SWAP_EN_S)
+#define PPA_SR_RX_BYTE_SWAP_EN_V  0x00000001U
+#define PPA_SR_RX_BYTE_SWAP_EN_S  0
+/** PPA_SR_RX_RGB_SWAP_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+ *  would be swap to bgr.
+ */
+#define PPA_SR_RX_RGB_SWAP_EN    (BIT(1))
+#define PPA_SR_RX_RGB_SWAP_EN_M  (PPA_SR_RX_RGB_SWAP_EN_V << PPA_SR_RX_RGB_SWAP_EN_S)
+#define PPA_SR_RX_RGB_SWAP_EN_V  0x00000001U
+#define PPA_SR_RX_RGB_SWAP_EN_S  1
+/** PPA_SR_MACRO_BK_RO_BYPASS : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to bypass the macro block order function. This function is used
+ *  to improve efficient accessing external memory.
+ */
+#define PPA_SR_MACRO_BK_RO_BYPASS    (BIT(2))
+#define PPA_SR_MACRO_BK_RO_BYPASS_M  (PPA_SR_MACRO_BK_RO_BYPASS_V << PPA_SR_MACRO_BK_RO_BYPASS_S)
+#define PPA_SR_MACRO_BK_RO_BYPASS_V  0x00000001U
+#define PPA_SR_MACRO_BK_RO_BYPASS_S  2
+/** PPA_SR_BK_SIZE_SEL : R/W; bitpos: [3]; default: 0;
+ *  sel srm pix_blk size, 0:32x32, 1:16x16
+ */
+#define PPA_SR_BK_SIZE_SEL    (BIT(3))
+#define PPA_SR_BK_SIZE_SEL_M  (PPA_SR_BK_SIZE_SEL_V << PPA_SR_BK_SIZE_SEL_S)
+#define PPA_SR_BK_SIZE_SEL_V  0x00000001U
+#define PPA_SR_BK_SIZE_SEL_S  3
+
+/** PPA_BLEND_BYTE_ORDER_REG register
+ *  Blending engine byte order register
+ */
+#define PPA_BLEND_BYTE_ORDER_REG (DR_REG_PPA_BASE + 0x2c)
+/** PPA_BLEND0_RX_BYTE_SWAP_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+ *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+ */
+#define PPA_BLEND0_RX_BYTE_SWAP_EN    (BIT(0))
+#define PPA_BLEND0_RX_BYTE_SWAP_EN_M  (PPA_BLEND0_RX_BYTE_SWAP_EN_V << PPA_BLEND0_RX_BYTE_SWAP_EN_S)
+#define PPA_BLEND0_RX_BYTE_SWAP_EN_V  0x00000001U
+#define PPA_BLEND0_RX_BYTE_SWAP_EN_S  0
+/** PPA_BLEND1_RX_BYTE_SWAP_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+ *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+ */
+#define PPA_BLEND1_RX_BYTE_SWAP_EN    (BIT(1))
+#define PPA_BLEND1_RX_BYTE_SWAP_EN_M  (PPA_BLEND1_RX_BYTE_SWAP_EN_V << PPA_BLEND1_RX_BYTE_SWAP_EN_S)
+#define PPA_BLEND1_RX_BYTE_SWAP_EN_V  0x00000001U
+#define PPA_BLEND1_RX_BYTE_SWAP_EN_S  1
+/** PPA_BLEND0_RX_RGB_SWAP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+ *  would be swap to bgr.
+ */
+#define PPA_BLEND0_RX_RGB_SWAP_EN    (BIT(2))
+#define PPA_BLEND0_RX_RGB_SWAP_EN_M  (PPA_BLEND0_RX_RGB_SWAP_EN_V << PPA_BLEND0_RX_RGB_SWAP_EN_S)
+#define PPA_BLEND0_RX_RGB_SWAP_EN_V  0x00000001U
+#define PPA_BLEND0_RX_RGB_SWAP_EN_S  2
+/** PPA_BLEND1_RX_RGB_SWAP_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+ *  would be swap to bgr.
+ */
+#define PPA_BLEND1_RX_RGB_SWAP_EN    (BIT(3))
+#define PPA_BLEND1_RX_RGB_SWAP_EN_M  (PPA_BLEND1_RX_RGB_SWAP_EN_V << PPA_BLEND1_RX_RGB_SWAP_EN_S)
+#define PPA_BLEND1_RX_RGB_SWAP_EN_V  0x00000001U
+#define PPA_BLEND1_RX_RGB_SWAP_EN_S  3
+
+/** PPA_BLEND_TRANS_MODE_REG register
+ *  Blending engine mode configure register
+ */
+#define PPA_BLEND_TRANS_MODE_REG (DR_REG_PPA_BASE + 0x34)
+/** PPA_BLEND_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable alpha blending.
+ */
+#define PPA_BLEND_EN    (BIT(0))
+#define PPA_BLEND_EN_M  (PPA_BLEND_EN_V << PPA_BLEND_EN_S)
+#define PPA_BLEND_EN_V  0x00000001U
+#define PPA_BLEND_EN_S  0
+/** PPA_BLEND_BYPASS : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to bypass blender. Then background date would be output.
+ */
+#define PPA_BLEND_BYPASS    (BIT(1))
+#define PPA_BLEND_BYPASS_M  (PPA_BLEND_BYPASS_V << PPA_BLEND_BYPASS_S)
+#define PPA_BLEND_BYPASS_V  0x00000001U
+#define PPA_BLEND_BYPASS_S  1
+/** PPA_BLEND_FIX_PIXEL_FILL_EN : R/W; bitpos: [2]; default: 0;
+ *  This bit is used to enable fix pixel filling. When this mode is enable  only Tx
+ *  channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL.
+ */
+#define PPA_BLEND_FIX_PIXEL_FILL_EN    (BIT(2))
+#define PPA_BLEND_FIX_PIXEL_FILL_EN_M  (PPA_BLEND_FIX_PIXEL_FILL_EN_V << PPA_BLEND_FIX_PIXEL_FILL_EN_S)
+#define PPA_BLEND_FIX_PIXEL_FILL_EN_V  0x00000001U
+#define PPA_BLEND_FIX_PIXEL_FILL_EN_S  2
+/** PPA_BLEND_TRANS_MODE_UPDATE : WT; bitpos: [3]; default: 0;
+ *  Set this bit to update the transfer mode. Only the bit is set  the transfer mode is
+ *  valid.
+ */
+#define PPA_BLEND_TRANS_MODE_UPDATE    (BIT(3))
+#define PPA_BLEND_TRANS_MODE_UPDATE_M  (PPA_BLEND_TRANS_MODE_UPDATE_V << PPA_BLEND_TRANS_MODE_UPDATE_S)
+#define PPA_BLEND_TRANS_MODE_UPDATE_V  0x00000001U
+#define PPA_BLEND_TRANS_MODE_UPDATE_S  3
+/** PPA_BLEND_RST : R/W; bitpos: [4]; default: 0;
+ *  write 1 then write 0 to reset blending engine.
+ */
+#define PPA_BLEND_RST    (BIT(4))
+#define PPA_BLEND_RST_M  (PPA_BLEND_RST_V << PPA_BLEND_RST_S)
+#define PPA_BLEND_RST_V  0x00000001U
+#define PPA_BLEND_RST_S  4
+/** PPA_BLEND_TX_INF_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and
+ *  ls_enc
+ */
+#define PPA_BLEND_TX_INF_SEL    0x00000003U
+#define PPA_BLEND_TX_INF_SEL_M  (PPA_BLEND_TX_INF_SEL_V << PPA_BLEND_TX_INF_SEL_S)
+#define PPA_BLEND_TX_INF_SEL_V  0x00000003U
+#define PPA_BLEND_TX_INF_SEL_S  5
+
+/** PPA_SR_FIX_ALPHA_REG register
+ *  Scaling and rotating engine alpha override register
+ */
+#define PPA_SR_FIX_ALPHA_REG (DR_REG_PPA_BASE + 0x38)
+/** PPA_SR_RX_FIX_ALPHA : R/W; bitpos: [7:0]; default: 128;
+ *  The value would replace the alpha value in received pixel for Scaling and Rotating
+ *  engine when PPA_SR_RX_ALPHA_CONF_EN is enabled.
+ */
+#define PPA_SR_RX_FIX_ALPHA    0x000000FFU
+#define PPA_SR_RX_FIX_ALPHA_M  (PPA_SR_RX_FIX_ALPHA_V << PPA_SR_RX_FIX_ALPHA_S)
+#define PPA_SR_RX_FIX_ALPHA_V  0x000000FFU
+#define PPA_SR_RX_FIX_ALPHA_S  0
+/** PPA_SR_RX_ALPHA_MOD : R/W; bitpos: [9:8]; default: 0;
+ *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
+ *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+ */
+#define PPA_SR_RX_ALPHA_MOD    0x00000003U
+#define PPA_SR_RX_ALPHA_MOD_M  (PPA_SR_RX_ALPHA_MOD_V << PPA_SR_RX_ALPHA_MOD_S)
+#define PPA_SR_RX_ALPHA_MOD_V  0x00000003U
+#define PPA_SR_RX_ALPHA_MOD_S  8
+/** PPA_SR_RX_ALPHA_INV : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to invert the original alpha value. When RX color mode is
+ *  RGB565/RGB88. The original alpha value is 255.
+ */
+#define PPA_SR_RX_ALPHA_INV    (BIT(10))
+#define PPA_SR_RX_ALPHA_INV_M  (PPA_SR_RX_ALPHA_INV_V << PPA_SR_RX_ALPHA_INV_S)
+#define PPA_SR_RX_ALPHA_INV_V  0x00000001U
+#define PPA_SR_RX_ALPHA_INV_S  10
+
+/** PPA_BLEND_TX_SIZE_REG register
+ *  Fix pixel filling mode image size register
+ */
+#define PPA_BLEND_TX_SIZE_REG (DR_REG_PPA_BASE + 0x3c)
+/** PPA_BLEND_HB : R/W; bitpos: [13:0]; default: 0;
+ *  The horizontal width of image block that would be filled in fix pixel filling mode
+ *  or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420
+ */
+#define PPA_BLEND_HB    0x00003FFFU
+#define PPA_BLEND_HB_M  (PPA_BLEND_HB_V << PPA_BLEND_HB_S)
+#define PPA_BLEND_HB_V  0x00003FFFU
+#define PPA_BLEND_HB_S  0
+/** PPA_BLEND_VB : R/W; bitpos: [27:14]; default: 0;
+ *  The vertical width of image block that would be filled in fix pixel filling mode or
+ *  blend mode. The unit is pixel. Must be even num when YUV420
+ */
+#define PPA_BLEND_VB    0x00003FFFU
+#define PPA_BLEND_VB_M  (PPA_BLEND_VB_V << PPA_BLEND_VB_S)
+#define PPA_BLEND_VB_V  0x00003FFFU
+#define PPA_BLEND_VB_S  14
+
+/** PPA_BLEND_FIX_ALPHA_REG register
+ *  Blending engine alpha override register
+ */
+#define PPA_BLEND_FIX_ALPHA_REG (DR_REG_PPA_BASE + 0x40)
+/** PPA_BLEND0_RX_FIX_ALPHA : R/W; bitpos: [7:0]; default: 128;
+ *  The value would replace the alpha value in received pixel for background plane of
+ *  blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled.
+ */
+#define PPA_BLEND0_RX_FIX_ALPHA    0x000000FFU
+#define PPA_BLEND0_RX_FIX_ALPHA_M  (PPA_BLEND0_RX_FIX_ALPHA_V << PPA_BLEND0_RX_FIX_ALPHA_S)
+#define PPA_BLEND0_RX_FIX_ALPHA_V  0x000000FFU
+#define PPA_BLEND0_RX_FIX_ALPHA_S  0
+/** PPA_BLEND1_RX_FIX_ALPHA : R/W; bitpos: [15:8]; default: 128;
+ *  The value would replace the alpha value in received pixel for foreground plane of
+ *  blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled.
+ */
+#define PPA_BLEND1_RX_FIX_ALPHA    0x000000FFU
+#define PPA_BLEND1_RX_FIX_ALPHA_M  (PPA_BLEND1_RX_FIX_ALPHA_V << PPA_BLEND1_RX_FIX_ALPHA_S)
+#define PPA_BLEND1_RX_FIX_ALPHA_V  0x000000FFU
+#define PPA_BLEND1_RX_FIX_ALPHA_S  8
+/** PPA_BLEND0_RX_ALPHA_MOD : R/W; bitpos: [17:16]; default: 0;
+ *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2:
+ *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+ */
+#define PPA_BLEND0_RX_ALPHA_MOD    0x00000003U
+#define PPA_BLEND0_RX_ALPHA_MOD_M  (PPA_BLEND0_RX_ALPHA_MOD_V << PPA_BLEND0_RX_ALPHA_MOD_S)
+#define PPA_BLEND0_RX_ALPHA_MOD_V  0x00000003U
+#define PPA_BLEND0_RX_ALPHA_MOD_S  16
+/** PPA_BLEND1_RX_ALPHA_MOD : R/W; bitpos: [19:18]; default: 0;
+ *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2:
+ *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+ */
+#define PPA_BLEND1_RX_ALPHA_MOD    0x00000003U
+#define PPA_BLEND1_RX_ALPHA_MOD_M  (PPA_BLEND1_RX_ALPHA_MOD_V << PPA_BLEND1_RX_ALPHA_MOD_S)
+#define PPA_BLEND1_RX_ALPHA_MOD_V  0x00000003U
+#define PPA_BLEND1_RX_ALPHA_MOD_S  18
+/** PPA_BLEND0_RX_ALPHA_INV : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to invert the original alpha value. When RX color mode is
+ *  RGB565/RGB88. The original alpha value is 255.
+ */
+#define PPA_BLEND0_RX_ALPHA_INV    (BIT(20))
+#define PPA_BLEND0_RX_ALPHA_INV_M  (PPA_BLEND0_RX_ALPHA_INV_V << PPA_BLEND0_RX_ALPHA_INV_S)
+#define PPA_BLEND0_RX_ALPHA_INV_V  0x00000001U
+#define PPA_BLEND0_RX_ALPHA_INV_S  20
+/** PPA_BLEND1_RX_ALPHA_INV : R/W; bitpos: [21]; default: 0;
+ *  Set this bit to invert the original alpha value. When RX color mode is
+ *  RGB565/RGB88. The original alpha value is 255.
+ */
+#define PPA_BLEND1_RX_ALPHA_INV    (BIT(21))
+#define PPA_BLEND1_RX_ALPHA_INV_M  (PPA_BLEND1_RX_ALPHA_INV_V << PPA_BLEND1_RX_ALPHA_INV_S)
+#define PPA_BLEND1_RX_ALPHA_INV_V  0x00000001U
+#define PPA_BLEND1_RX_ALPHA_INV_S  21
+
+/** PPA_BLEND_RGB_REG register
+ *  RGB color register
+ */
+#define PPA_BLEND_RGB_REG (DR_REG_PPA_BASE + 0x48)
+/** PPA_BLEND1_RX_B : R/W; bitpos: [7:0]; default: 128;
+ *  blue color for A4/A8 mode.
+ */
+#define PPA_BLEND1_RX_B    0x000000FFU
+#define PPA_BLEND1_RX_B_M  (PPA_BLEND1_RX_B_V << PPA_BLEND1_RX_B_S)
+#define PPA_BLEND1_RX_B_V  0x000000FFU
+#define PPA_BLEND1_RX_B_S  0
+/** PPA_BLEND1_RX_G : R/W; bitpos: [15:8]; default: 128;
+ *  green color for A4/A8 mode.
+ */
+#define PPA_BLEND1_RX_G    0x000000FFU
+#define PPA_BLEND1_RX_G_M  (PPA_BLEND1_RX_G_V << PPA_BLEND1_RX_G_S)
+#define PPA_BLEND1_RX_G_V  0x000000FFU
+#define PPA_BLEND1_RX_G_S  8
+/** PPA_BLEND1_RX_R : R/W; bitpos: [23:16]; default: 128;
+ *  red color for A4/A8 mode.
+ */
+#define PPA_BLEND1_RX_R    0x000000FFU
+#define PPA_BLEND1_RX_R_M  (PPA_BLEND1_RX_R_V << PPA_BLEND1_RX_R_S)
+#define PPA_BLEND1_RX_R_V  0x000000FFU
+#define PPA_BLEND1_RX_R_S  16
+
+/** PPA_BLEND_FIX_PIXEL_REG register
+ *  Blending engine fix pixel register
+ */
+#define PPA_BLEND_FIX_PIXEL_REG (DR_REG_PPA_BASE + 0x4c)
+/** PPA_BLEND_TX_FIX_PIXEL : R/W; bitpos: [31:0]; default: 0;
+ *  The configure fix pixel in fix pixel filling mode for blender engine.
+ */
+#define PPA_BLEND_TX_FIX_PIXEL    0xFFFFFFFFU
+#define PPA_BLEND_TX_FIX_PIXEL_M  (PPA_BLEND_TX_FIX_PIXEL_V << PPA_BLEND_TX_FIX_PIXEL_S)
+#define PPA_BLEND_TX_FIX_PIXEL_V  0xFFFFFFFFU
+#define PPA_BLEND_TX_FIX_PIXEL_S  0
+
+/** PPA_CK_FG_LOW_REG register
+ *  foreground color key lower threshold
+ */
+#define PPA_CK_FG_LOW_REG (DR_REG_PPA_BASE + 0x50)
+/** PPA_COLORKEY_FG_B_LOW : R/W; bitpos: [7:0]; default: 255;
+ *  color key lower threshold of foreground b channel
+ */
+#define PPA_COLORKEY_FG_B_LOW    0x000000FFU
+#define PPA_COLORKEY_FG_B_LOW_M  (PPA_COLORKEY_FG_B_LOW_V << PPA_COLORKEY_FG_B_LOW_S)
+#define PPA_COLORKEY_FG_B_LOW_V  0x000000FFU
+#define PPA_COLORKEY_FG_B_LOW_S  0
+/** PPA_COLORKEY_FG_G_LOW : R/W; bitpos: [15:8]; default: 255;
+ *  color key lower threshold of foreground g channel
+ */
+#define PPA_COLORKEY_FG_G_LOW    0x000000FFU
+#define PPA_COLORKEY_FG_G_LOW_M  (PPA_COLORKEY_FG_G_LOW_V << PPA_COLORKEY_FG_G_LOW_S)
+#define PPA_COLORKEY_FG_G_LOW_V  0x000000FFU
+#define PPA_COLORKEY_FG_G_LOW_S  8
+/** PPA_COLORKEY_FG_R_LOW : R/W; bitpos: [23:16]; default: 255;
+ *  color key lower threshold of foreground r channel
+ */
+#define PPA_COLORKEY_FG_R_LOW    0x000000FFU
+#define PPA_COLORKEY_FG_R_LOW_M  (PPA_COLORKEY_FG_R_LOW_V << PPA_COLORKEY_FG_R_LOW_S)
+#define PPA_COLORKEY_FG_R_LOW_V  0x000000FFU
+#define PPA_COLORKEY_FG_R_LOW_S  16
+
+/** PPA_CK_FG_HIGH_REG register
+ *  foreground color key higher threshold
+ */
+#define PPA_CK_FG_HIGH_REG (DR_REG_PPA_BASE + 0x54)
+/** PPA_COLORKEY_FG_B_HIGH : R/W; bitpos: [7:0]; default: 0;
+ *  color key higher threshold of foreground b channel
+ */
+#define PPA_COLORKEY_FG_B_HIGH    0x000000FFU
+#define PPA_COLORKEY_FG_B_HIGH_M  (PPA_COLORKEY_FG_B_HIGH_V << PPA_COLORKEY_FG_B_HIGH_S)
+#define PPA_COLORKEY_FG_B_HIGH_V  0x000000FFU
+#define PPA_COLORKEY_FG_B_HIGH_S  0
+/** PPA_COLORKEY_FG_G_HIGH : R/W; bitpos: [15:8]; default: 0;
+ *  color key higher threshold of foreground g channel
+ */
+#define PPA_COLORKEY_FG_G_HIGH    0x000000FFU
+#define PPA_COLORKEY_FG_G_HIGH_M  (PPA_COLORKEY_FG_G_HIGH_V << PPA_COLORKEY_FG_G_HIGH_S)
+#define PPA_COLORKEY_FG_G_HIGH_V  0x000000FFU
+#define PPA_COLORKEY_FG_G_HIGH_S  8
+/** PPA_COLORKEY_FG_R_HIGH : R/W; bitpos: [23:16]; default: 0;
+ *  color key higher threshold of foreground r channel
+ */
+#define PPA_COLORKEY_FG_R_HIGH    0x000000FFU
+#define PPA_COLORKEY_FG_R_HIGH_M  (PPA_COLORKEY_FG_R_HIGH_V << PPA_COLORKEY_FG_R_HIGH_S)
+#define PPA_COLORKEY_FG_R_HIGH_V  0x000000FFU
+#define PPA_COLORKEY_FG_R_HIGH_S  16
+
+/** PPA_CK_BG_LOW_REG register
+ *  background color key lower threshold
+ */
+#define PPA_CK_BG_LOW_REG (DR_REG_PPA_BASE + 0x58)
+/** PPA_COLORKEY_BG_B_LOW : R/W; bitpos: [7:0]; default: 255;
+ *  color key lower threshold of background b channel
+ */
+#define PPA_COLORKEY_BG_B_LOW    0x000000FFU
+#define PPA_COLORKEY_BG_B_LOW_M  (PPA_COLORKEY_BG_B_LOW_V << PPA_COLORKEY_BG_B_LOW_S)
+#define PPA_COLORKEY_BG_B_LOW_V  0x000000FFU
+#define PPA_COLORKEY_BG_B_LOW_S  0
+/** PPA_COLORKEY_BG_G_LOW : R/W; bitpos: [15:8]; default: 255;
+ *  color key lower threshold of background g channel
+ */
+#define PPA_COLORKEY_BG_G_LOW    0x000000FFU
+#define PPA_COLORKEY_BG_G_LOW_M  (PPA_COLORKEY_BG_G_LOW_V << PPA_COLORKEY_BG_G_LOW_S)
+#define PPA_COLORKEY_BG_G_LOW_V  0x000000FFU
+#define PPA_COLORKEY_BG_G_LOW_S  8
+/** PPA_COLORKEY_BG_R_LOW : R/W; bitpos: [23:16]; default: 255;
+ *  color key lower threshold of background r channel
+ */
+#define PPA_COLORKEY_BG_R_LOW    0x000000FFU
+#define PPA_COLORKEY_BG_R_LOW_M  (PPA_COLORKEY_BG_R_LOW_V << PPA_COLORKEY_BG_R_LOW_S)
+#define PPA_COLORKEY_BG_R_LOW_V  0x000000FFU
+#define PPA_COLORKEY_BG_R_LOW_S  16
+
+/** PPA_CK_BG_HIGH_REG register
+ *  background color key higher threshold
+ */
+#define PPA_CK_BG_HIGH_REG (DR_REG_PPA_BASE + 0x5c)
+/** PPA_COLORKEY_BG_B_HIGH : R/W; bitpos: [7:0]; default: 0;
+ *  color key higher threshold of background b channel
+ */
+#define PPA_COLORKEY_BG_B_HIGH    0x000000FFU
+#define PPA_COLORKEY_BG_B_HIGH_M  (PPA_COLORKEY_BG_B_HIGH_V << PPA_COLORKEY_BG_B_HIGH_S)
+#define PPA_COLORKEY_BG_B_HIGH_V  0x000000FFU
+#define PPA_COLORKEY_BG_B_HIGH_S  0
+/** PPA_COLORKEY_BG_G_HIGH : R/W; bitpos: [15:8]; default: 0;
+ *  color key higher threshold of background g channel
+ */
+#define PPA_COLORKEY_BG_G_HIGH    0x000000FFU
+#define PPA_COLORKEY_BG_G_HIGH_M  (PPA_COLORKEY_BG_G_HIGH_V << PPA_COLORKEY_BG_G_HIGH_S)
+#define PPA_COLORKEY_BG_G_HIGH_V  0x000000FFU
+#define PPA_COLORKEY_BG_G_HIGH_S  8
+/** PPA_COLORKEY_BG_R_HIGH : R/W; bitpos: [23:16]; default: 0;
+ *  color key higher threshold of background r channel
+ */
+#define PPA_COLORKEY_BG_R_HIGH    0x000000FFU
+#define PPA_COLORKEY_BG_R_HIGH_M  (PPA_COLORKEY_BG_R_HIGH_V << PPA_COLORKEY_BG_R_HIGH_S)
+#define PPA_COLORKEY_BG_R_HIGH_V  0x000000FFU
+#define PPA_COLORKEY_BG_R_HIGH_S  16
+
+/** PPA_CK_DEFAULT_REG register
+ *  default value when foreground and background both in color key range
+ */
+#define PPA_CK_DEFAULT_REG (DR_REG_PPA_BASE + 0x60)
+/** PPA_COLORKEY_DEFAULT_B : R/W; bitpos: [7:0]; default: 0;
+ *  default B channel value of color key
+ */
+#define PPA_COLORKEY_DEFAULT_B    0x000000FFU
+#define PPA_COLORKEY_DEFAULT_B_M  (PPA_COLORKEY_DEFAULT_B_V << PPA_COLORKEY_DEFAULT_B_S)
+#define PPA_COLORKEY_DEFAULT_B_V  0x000000FFU
+#define PPA_COLORKEY_DEFAULT_B_S  0
+/** PPA_COLORKEY_DEFAULT_G : R/W; bitpos: [15:8]; default: 0;
+ *  default G channel value of color key
+ */
+#define PPA_COLORKEY_DEFAULT_G    0x000000FFU
+#define PPA_COLORKEY_DEFAULT_G_M  (PPA_COLORKEY_DEFAULT_G_V << PPA_COLORKEY_DEFAULT_G_S)
+#define PPA_COLORKEY_DEFAULT_G_V  0x000000FFU
+#define PPA_COLORKEY_DEFAULT_G_S  8
+/** PPA_COLORKEY_DEFAULT_R : R/W; bitpos: [23:16]; default: 0;
+ *  default R channel value of color key
+ */
+#define PPA_COLORKEY_DEFAULT_R    0x000000FFU
+#define PPA_COLORKEY_DEFAULT_R_M  (PPA_COLORKEY_DEFAULT_R_V << PPA_COLORKEY_DEFAULT_R_S)
+#define PPA_COLORKEY_DEFAULT_R_V  0x000000FFU
+#define PPA_COLORKEY_DEFAULT_R_S  16
+/** PPA_COLORKEY_FG_BG_REVERSE : R/W; bitpos: [24]; default: 0;
+ *  when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the
+ *  result is fg
+ */
+#define PPA_COLORKEY_FG_BG_REVERSE    (BIT(24))
+#define PPA_COLORKEY_FG_BG_REVERSE_M  (PPA_COLORKEY_FG_BG_REVERSE_V << PPA_COLORKEY_FG_BG_REVERSE_S)
+#define PPA_COLORKEY_FG_BG_REVERSE_V  0x00000001U
+#define PPA_COLORKEY_FG_BG_REVERSE_S  24
+
+/** PPA_SR_SCAL_ROTATE_REG register
+ *  Scaling and rotating coefficient register
+ */
+#define PPA_SR_SCAL_ROTATE_REG (DR_REG_PPA_BASE + 0x64)
+/** PPA_SR_SCAL_X_INT : R/W; bitpos: [7:0]; default: 1;
+ *  The integrated part of scaling coefficient in X direction.
+ */
+#define PPA_SR_SCAL_X_INT    0x000000FFU
+#define PPA_SR_SCAL_X_INT_M  (PPA_SR_SCAL_X_INT_V << PPA_SR_SCAL_X_INT_S)
+#define PPA_SR_SCAL_X_INT_V  0x000000FFU
+#define PPA_SR_SCAL_X_INT_S  0
+/** PPA_SR_SCAL_X_FRAG : R/W; bitpos: [11:8]; default: 0;
+ *  The fragment part of scaling coefficient in X direction.
+ */
+#define PPA_SR_SCAL_X_FRAG    0x0000000FU
+#define PPA_SR_SCAL_X_FRAG_M  (PPA_SR_SCAL_X_FRAG_V << PPA_SR_SCAL_X_FRAG_S)
+#define PPA_SR_SCAL_X_FRAG_V  0x0000000FU
+#define PPA_SR_SCAL_X_FRAG_S  8
+/** PPA_SR_SCAL_Y_INT : R/W; bitpos: [19:12]; default: 1;
+ *  The integrated part of scaling coefficient in Y direction.
+ */
+#define PPA_SR_SCAL_Y_INT    0x000000FFU
+#define PPA_SR_SCAL_Y_INT_M  (PPA_SR_SCAL_Y_INT_V << PPA_SR_SCAL_Y_INT_S)
+#define PPA_SR_SCAL_Y_INT_V  0x000000FFU
+#define PPA_SR_SCAL_Y_INT_S  12
+/** PPA_SR_SCAL_Y_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The fragment part of scaling coefficient in Y direction.
+ */
+#define PPA_SR_SCAL_Y_FRAG    0x0000000FU
+#define PPA_SR_SCAL_Y_FRAG_M  (PPA_SR_SCAL_Y_FRAG_V << PPA_SR_SCAL_Y_FRAG_S)
+#define PPA_SR_SCAL_Y_FRAG_V  0x0000000FU
+#define PPA_SR_SCAL_Y_FRAG_S  20
+/** PPA_SR_ROTATE_ANGLE : R/W; bitpos: [25:24]; default: 0;
+ *  The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree.
+ */
+#define PPA_SR_ROTATE_ANGLE    0x00000003U
+#define PPA_SR_ROTATE_ANGLE_M  (PPA_SR_ROTATE_ANGLE_V << PPA_SR_ROTATE_ANGLE_S)
+#define PPA_SR_ROTATE_ANGLE_V  0x00000003U
+#define PPA_SR_ROTATE_ANGLE_S  24
+/** PPA_SCAL_ROTATE_RST : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit to reset scaling and rotating engine.
+ */
+#define PPA_SCAL_ROTATE_RST    (BIT(26))
+#define PPA_SCAL_ROTATE_RST_M  (PPA_SCAL_ROTATE_RST_V << PPA_SCAL_ROTATE_RST_S)
+#define PPA_SCAL_ROTATE_RST_V  0x00000001U
+#define PPA_SCAL_ROTATE_RST_S  26
+/** PPA_SCAL_ROTATE_START : WT; bitpos: [27]; default: 0;
+ *  Write 1 to enable scaling and rotating engine after parameter is configured.
+ */
+#define PPA_SCAL_ROTATE_START    (BIT(27))
+#define PPA_SCAL_ROTATE_START_M  (PPA_SCAL_ROTATE_START_V << PPA_SCAL_ROTATE_START_S)
+#define PPA_SCAL_ROTATE_START_V  0x00000001U
+#define PPA_SCAL_ROTATE_START_S  27
+/** PPA_SR_MIRROR_X : R/W; bitpos: [28]; default: 0;
+ *  Image mirror in X direction. 0: disable, 1: enable
+ */
+#define PPA_SR_MIRROR_X    (BIT(28))
+#define PPA_SR_MIRROR_X_M  (PPA_SR_MIRROR_X_V << PPA_SR_MIRROR_X_S)
+#define PPA_SR_MIRROR_X_V  0x00000001U
+#define PPA_SR_MIRROR_X_S  28
+/** PPA_SR_MIRROR_Y : R/W; bitpos: [29]; default: 0;
+ *  Image mirror in Y direction. 0: disable, 1: enable
+ */
+#define PPA_SR_MIRROR_Y    (BIT(29))
+#define PPA_SR_MIRROR_Y_M  (PPA_SR_MIRROR_Y_V << PPA_SR_MIRROR_Y_S)
+#define PPA_SR_MIRROR_Y_V  0x00000001U
+#define PPA_SR_MIRROR_Y_S  29
+
+/** PPA_SR_MEM_PD_REG register
+ *  SR memory power done register
+ */
+#define PPA_SR_MEM_PD_REG (DR_REG_PPA_BASE + 0x68)
+/** PPA_SR_MEM_CLK_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force clock enable of scaling and rotating engine's data memory.
+ */
+#define PPA_SR_MEM_CLK_ENA    (BIT(0))
+#define PPA_SR_MEM_CLK_ENA_M  (PPA_SR_MEM_CLK_ENA_V << PPA_SR_MEM_CLK_ENA_S)
+#define PPA_SR_MEM_CLK_ENA_V  0x00000001U
+#define PPA_SR_MEM_CLK_ENA_S  0
+/** PPA_SR_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to force power down scaling and rotating engine's data memory.
+ */
+#define PPA_SR_MEM_FORCE_PD    (BIT(1))
+#define PPA_SR_MEM_FORCE_PD_M  (PPA_SR_MEM_FORCE_PD_V << PPA_SR_MEM_FORCE_PD_S)
+#define PPA_SR_MEM_FORCE_PD_V  0x00000001U
+#define PPA_SR_MEM_FORCE_PD_S  1
+/** PPA_SR_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power up scaling and rotating engine's data memory.
+ */
+#define PPA_SR_MEM_FORCE_PU    (BIT(2))
+#define PPA_SR_MEM_FORCE_PU_M  (PPA_SR_MEM_FORCE_PU_V << PPA_SR_MEM_FORCE_PU_S)
+#define PPA_SR_MEM_FORCE_PU_V  0x00000001U
+#define PPA_SR_MEM_FORCE_PU_S  2
+
+/** PPA_REG_CONF_REG register
+ *  Register clock enable register
+ */
+#define PPA_REG_CONF_REG (DR_REG_PPA_BASE + 0x6c)
+/** PPA_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  PPA register clock gate enable signal.
+ */
+#define PPA_CLK_EN    (BIT(0))
+#define PPA_CLK_EN_M  (PPA_CLK_EN_V << PPA_CLK_EN_S)
+#define PPA_CLK_EN_V  0x00000001U
+#define PPA_CLK_EN_S  0
+
+/** PPA_CLUT_CNT_REG register
+ *  BLEND CLUT write counter register
+ */
+#define PPA_CLUT_CNT_REG (DR_REG_PPA_BASE + 0x70)
+/** PPA_BLEND0_CLUT_CNT : RO; bitpos: [8:0]; default: 0;
+ *  The write data counter of BLEND0 CLUT in fifo mode.
+ */
+#define PPA_BLEND0_CLUT_CNT    0x000001FFU
+#define PPA_BLEND0_CLUT_CNT_M  (PPA_BLEND0_CLUT_CNT_V << PPA_BLEND0_CLUT_CNT_S)
+#define PPA_BLEND0_CLUT_CNT_V  0x000001FFU
+#define PPA_BLEND0_CLUT_CNT_S  0
+/** PPA_BLEND1_CLUT_CNT : RO; bitpos: [17:9]; default: 0;
+ *  The write data counter of BLEND1 CLUT in fifo mode.
+ */
+#define PPA_BLEND1_CLUT_CNT    0x000001FFU
+#define PPA_BLEND1_CLUT_CNT_M  (PPA_BLEND1_CLUT_CNT_V << PPA_BLEND1_CLUT_CNT_S)
+#define PPA_BLEND1_CLUT_CNT_V  0x000001FFU
+#define PPA_BLEND1_CLUT_CNT_S  9
+
+/** PPA_BLEND_ST_REG register
+ *  Blending engine status register
+ */
+#define PPA_BLEND_ST_REG (DR_REG_PPA_BASE + 0x74)
+/** PPA_BLEND_SIZE_DIFF_ST : RO; bitpos: [0]; default: 0;
+ *  1: indicate the size of two image is different.
+ */
+#define PPA_BLEND_SIZE_DIFF_ST    (BIT(0))
+#define PPA_BLEND_SIZE_DIFF_ST_M  (PPA_BLEND_SIZE_DIFF_ST_V << PPA_BLEND_SIZE_DIFF_ST_S)
+#define PPA_BLEND_SIZE_DIFF_ST_V  0x00000001U
+#define PPA_BLEND_SIZE_DIFF_ST_S  0
+/** PPA_BLEND_YUV_X_SCALE_ERR_ST : RO; bitpos: [1]; default: 0;
+ *  Represents that x param is an odd num when enable yuv422 or yuv420
+ */
+#define PPA_BLEND_YUV_X_SCALE_ERR_ST    (BIT(1))
+#define PPA_BLEND_YUV_X_SCALE_ERR_ST_M  (PPA_BLEND_YUV_X_SCALE_ERR_ST_V << PPA_BLEND_YUV_X_SCALE_ERR_ST_S)
+#define PPA_BLEND_YUV_X_SCALE_ERR_ST_V  0x00000001U
+#define PPA_BLEND_YUV_X_SCALE_ERR_ST_S  1
+/** PPA_BLEND_YUV_Y_SCALE_ERR_ST : RO; bitpos: [2]; default: 0;
+ *  Represents that y param is an odd num when enable yuv420
+ */
+#define PPA_BLEND_YUV_Y_SCALE_ERR_ST    (BIT(2))
+#define PPA_BLEND_YUV_Y_SCALE_ERR_ST_M  (PPA_BLEND_YUV_Y_SCALE_ERR_ST_V << PPA_BLEND_YUV_Y_SCALE_ERR_ST_S)
+#define PPA_BLEND_YUV_Y_SCALE_ERR_ST_V  0x00000001U
+#define PPA_BLEND_YUV_Y_SCALE_ERR_ST_S  2
+
+/** PPA_SR_PARAM_ERR_ST_REG register
+ *  Scaling and rotating coefficient error register
+ */
+#define PPA_SR_PARAM_ERR_ST_REG (DR_REG_PPA_BASE + 0x78)
+/** PPA_TX_DSCR_VB_ERR_ST : RO; bitpos: [0]; default: 0;
+ *  The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive
+ *  descriptor is larger than VA in 2DDMA receive descriptor.
+ */
+#define PPA_TX_DSCR_VB_ERR_ST    (BIT(0))
+#define PPA_TX_DSCR_VB_ERR_ST_M  (PPA_TX_DSCR_VB_ERR_ST_V << PPA_TX_DSCR_VB_ERR_ST_S)
+#define PPA_TX_DSCR_VB_ERR_ST_V  0x00000001U
+#define PPA_TX_DSCR_VB_ERR_ST_S  0
+/** PPA_TX_DSCR_HB_ERR_ST : RO; bitpos: [1]; default: 0;
+ *  The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive
+ *  descriptor is larger than HA in 2DDMA receive descriptor.
+ */
+#define PPA_TX_DSCR_HB_ERR_ST    (BIT(1))
+#define PPA_TX_DSCR_HB_ERR_ST_M  (PPA_TX_DSCR_HB_ERR_ST_V << PPA_TX_DSCR_HB_ERR_ST_S)
+#define PPA_TX_DSCR_HB_ERR_ST_V  0x00000001U
+#define PPA_TX_DSCR_HB_ERR_ST_S  1
+/** PPA_Y_RX_SCAL_EQUAL_0_ERR_ST : RO; bitpos: [2]; default: 0;
+ *  The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0.
+ */
+#define PPA_Y_RX_SCAL_EQUAL_0_ERR_ST    (BIT(2))
+#define PPA_Y_RX_SCAL_EQUAL_0_ERR_ST_M  (PPA_Y_RX_SCAL_EQUAL_0_ERR_ST_V << PPA_Y_RX_SCAL_EQUAL_0_ERR_ST_S)
+#define PPA_Y_RX_SCAL_EQUAL_0_ERR_ST_V  0x00000001U
+#define PPA_Y_RX_SCAL_EQUAL_0_ERR_ST_S  2
+/** PPA_RX_DSCR_VB_ERR_ST : RO; bitpos: [3]; default: 0;
+ *  The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in
+ *  2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor
+ */
+#define PPA_RX_DSCR_VB_ERR_ST    (BIT(3))
+#define PPA_RX_DSCR_VB_ERR_ST_M  (PPA_RX_DSCR_VB_ERR_ST_V << PPA_RX_DSCR_VB_ERR_ST_S)
+#define PPA_RX_DSCR_VB_ERR_ST_V  0x00000001U
+#define PPA_RX_DSCR_VB_ERR_ST_S  3
+/** PPA_YDST_LEN_TOO_SAMLL_ERR_ST : RO; bitpos: [4]; default: 0;
+ *  The error is that the scaled image width is 0. For example.  when source width is
+ *  14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as
+ *  the result would be floored.
+ */
+#define PPA_YDST_LEN_TOO_SAMLL_ERR_ST    (BIT(4))
+#define PPA_YDST_LEN_TOO_SAMLL_ERR_ST_M  (PPA_YDST_LEN_TOO_SAMLL_ERR_ST_V << PPA_YDST_LEN_TOO_SAMLL_ERR_ST_S)
+#define PPA_YDST_LEN_TOO_SAMLL_ERR_ST_V  0x00000001U
+#define PPA_YDST_LEN_TOO_SAMLL_ERR_ST_S  4
+/** PPA_YDST_LEN_TOO_LARGE_ERR_ST : RO; bitpos: [5]; default: 0;
+ *  The error is that the scaled width is larger than (2^13 - 1).
+ */
+#define PPA_YDST_LEN_TOO_LARGE_ERR_ST    (BIT(5))
+#define PPA_YDST_LEN_TOO_LARGE_ERR_ST_M  (PPA_YDST_LEN_TOO_LARGE_ERR_ST_V << PPA_YDST_LEN_TOO_LARGE_ERR_ST_S)
+#define PPA_YDST_LEN_TOO_LARGE_ERR_ST_V  0x00000001U
+#define PPA_YDST_LEN_TOO_LARGE_ERR_ST_S  5
+/** PPA_X_RX_SCAL_EQUAL_0_ERR_ST : RO; bitpos: [6]; default: 0;
+ *  The error is that the scaled image height is 0.
+ */
+#define PPA_X_RX_SCAL_EQUAL_0_ERR_ST    (BIT(6))
+#define PPA_X_RX_SCAL_EQUAL_0_ERR_ST_M  (PPA_X_RX_SCAL_EQUAL_0_ERR_ST_V << PPA_X_RX_SCAL_EQUAL_0_ERR_ST_S)
+#define PPA_X_RX_SCAL_EQUAL_0_ERR_ST_V  0x00000001U
+#define PPA_X_RX_SCAL_EQUAL_0_ERR_ST_S  6
+/** PPA_RX_DSCR_HB_ERR_ST : RO; bitpos: [7]; default: 0;
+ *  The error is that the HB in 2DDMA transmit descriptor plus the offset of X
+ *  coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit
+ *  descriptor.
+ */
+#define PPA_RX_DSCR_HB_ERR_ST    (BIT(7))
+#define PPA_RX_DSCR_HB_ERR_ST_M  (PPA_RX_DSCR_HB_ERR_ST_V << PPA_RX_DSCR_HB_ERR_ST_S)
+#define PPA_RX_DSCR_HB_ERR_ST_V  0x00000001U
+#define PPA_RX_DSCR_HB_ERR_ST_S  7
+/** PPA_XDST_LEN_TOO_SAMLL_ERR_ST : RO; bitpos: [8]; default: 0;
+ *  The error is that the scaled image height is 0. For example.  when source height is
+ *  14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as
+ *  the result would be floored.
+ */
+#define PPA_XDST_LEN_TOO_SAMLL_ERR_ST    (BIT(8))
+#define PPA_XDST_LEN_TOO_SAMLL_ERR_ST_M  (PPA_XDST_LEN_TOO_SAMLL_ERR_ST_V << PPA_XDST_LEN_TOO_SAMLL_ERR_ST_S)
+#define PPA_XDST_LEN_TOO_SAMLL_ERR_ST_V  0x00000001U
+#define PPA_XDST_LEN_TOO_SAMLL_ERR_ST_S  8
+/** PPA_XDST_LEN_TOO_LARGE_ERR_ST : RO; bitpos: [9]; default: 0;
+ *  The error is that the scaled image height is larger than (2^13 - 1).
+ */
+#define PPA_XDST_LEN_TOO_LARGE_ERR_ST    (BIT(9))
+#define PPA_XDST_LEN_TOO_LARGE_ERR_ST_M  (PPA_XDST_LEN_TOO_LARGE_ERR_ST_V << PPA_XDST_LEN_TOO_LARGE_ERR_ST_S)
+#define PPA_XDST_LEN_TOO_LARGE_ERR_ST_V  0x00000001U
+#define PPA_XDST_LEN_TOO_LARGE_ERR_ST_S  9
+/** PPA_X_YUV420_RX_SCALE_ERR_ST : RO; bitpos: [10]; default: 0;
+ *  The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
+ *  yuv422 or yuv420 rx
+ */
+#define PPA_X_YUV420_RX_SCALE_ERR_ST    (BIT(10))
+#define PPA_X_YUV420_RX_SCALE_ERR_ST_M  (PPA_X_YUV420_RX_SCALE_ERR_ST_V << PPA_X_YUV420_RX_SCALE_ERR_ST_S)
+#define PPA_X_YUV420_RX_SCALE_ERR_ST_V  0x00000001U
+#define PPA_X_YUV420_RX_SCALE_ERR_ST_S  10
+/** PPA_Y_YUV420_RX_SCALE_ERR_ST : RO; bitpos: [11]; default: 0;
+ *  The error is that the va/vb/y param in dma2d descriptor is an odd num when enable
+ *  yuv420 rx
+ */
+#define PPA_Y_YUV420_RX_SCALE_ERR_ST    (BIT(11))
+#define PPA_Y_YUV420_RX_SCALE_ERR_ST_M  (PPA_Y_YUV420_RX_SCALE_ERR_ST_V << PPA_Y_YUV420_RX_SCALE_ERR_ST_S)
+#define PPA_Y_YUV420_RX_SCALE_ERR_ST_V  0x00000001U
+#define PPA_Y_YUV420_RX_SCALE_ERR_ST_S  11
+/** PPA_X_YUV420_TX_SCALE_ERR_ST : RO; bitpos: [12]; default: 0;
+ *  The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
+ *  yuv422 or yuv420 tx
+ */
+#define PPA_X_YUV420_TX_SCALE_ERR_ST    (BIT(12))
+#define PPA_X_YUV420_TX_SCALE_ERR_ST_M  (PPA_X_YUV420_TX_SCALE_ERR_ST_V << PPA_X_YUV420_TX_SCALE_ERR_ST_S)
+#define PPA_X_YUV420_TX_SCALE_ERR_ST_V  0x00000001U
+#define PPA_X_YUV420_TX_SCALE_ERR_ST_S  12
+/** PPA_Y_YUV420_TX_SCALE_ERR_ST : RO; bitpos: [13]; default: 0;
+ *  The error is that the va/vb/y param in dma2d descriptor is an odd num when enable
+ *  yuv420 tx
+ */
+#define PPA_Y_YUV420_TX_SCALE_ERR_ST    (BIT(13))
+#define PPA_Y_YUV420_TX_SCALE_ERR_ST_M  (PPA_Y_YUV420_TX_SCALE_ERR_ST_V << PPA_Y_YUV420_TX_SCALE_ERR_ST_S)
+#define PPA_Y_YUV420_TX_SCALE_ERR_ST_V  0x00000001U
+#define PPA_Y_YUV420_TX_SCALE_ERR_ST_S  13
+
+/** PPA_SR_STATUS_REG register
+ *  SR FSM register
+ */
+#define PPA_SR_STATUS_REG (DR_REG_PPA_BASE + 0x7c)
+/** PPA_SR_RX_DSCR_SAMPLE_STATE : RO; bitpos: [1:0]; default: 0;
+ *  Reserved.
+ */
+#define PPA_SR_RX_DSCR_SAMPLE_STATE    0x00000003U
+#define PPA_SR_RX_DSCR_SAMPLE_STATE_M  (PPA_SR_RX_DSCR_SAMPLE_STATE_V << PPA_SR_RX_DSCR_SAMPLE_STATE_S)
+#define PPA_SR_RX_DSCR_SAMPLE_STATE_V  0x00000003U
+#define PPA_SR_RX_DSCR_SAMPLE_STATE_S  0
+/** PPA_SR_RX_SCAN_STATE : RO; bitpos: [3:2]; default: 0;
+ *  Reserved.
+ */
+#define PPA_SR_RX_SCAN_STATE    0x00000003U
+#define PPA_SR_RX_SCAN_STATE_M  (PPA_SR_RX_SCAN_STATE_V << PPA_SR_RX_SCAN_STATE_S)
+#define PPA_SR_RX_SCAN_STATE_V  0x00000003U
+#define PPA_SR_RX_SCAN_STATE_S  2
+/** PPA_SR_TX_DSCR_SAMPLE_STATE : RO; bitpos: [5:4]; default: 0;
+ *  Reserved.
+ */
+#define PPA_SR_TX_DSCR_SAMPLE_STATE    0x00000003U
+#define PPA_SR_TX_DSCR_SAMPLE_STATE_M  (PPA_SR_TX_DSCR_SAMPLE_STATE_V << PPA_SR_TX_DSCR_SAMPLE_STATE_S)
+#define PPA_SR_TX_DSCR_SAMPLE_STATE_V  0x00000003U
+#define PPA_SR_TX_DSCR_SAMPLE_STATE_S  4
+/** PPA_SR_TX_SCAN_STATE : RO; bitpos: [8:6]; default: 0;
+ *  Reserved.
+ */
+#define PPA_SR_TX_SCAN_STATE    0x00000007U
+#define PPA_SR_TX_SCAN_STATE_M  (PPA_SR_TX_SCAN_STATE_V << PPA_SR_TX_SCAN_STATE_S)
+#define PPA_SR_TX_SCAN_STATE_V  0x00000007U
+#define PPA_SR_TX_SCAN_STATE_S  6
+
+/** PPA_ECO_LOW_REG register
+ *  Reserved.
+ */
+#define PPA_ECO_LOW_REG (DR_REG_PPA_BASE + 0x80)
+/** PPA_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define PPA_RND_ECO_LOW    0xFFFFFFFFU
+#define PPA_RND_ECO_LOW_M  (PPA_RND_ECO_LOW_V << PPA_RND_ECO_LOW_S)
+#define PPA_RND_ECO_LOW_V  0xFFFFFFFFU
+#define PPA_RND_ECO_LOW_S  0
+
+/** PPA_ECO_HIGH_REG register
+ *  Reserved.
+ */
+#define PPA_ECO_HIGH_REG (DR_REG_PPA_BASE + 0x84)
+/** PPA_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Reserved.
+ */
+#define PPA_RND_ECO_HIGH    0xFFFFFFFFU
+#define PPA_RND_ECO_HIGH_M  (PPA_RND_ECO_HIGH_V << PPA_RND_ECO_HIGH_S)
+#define PPA_RND_ECO_HIGH_V  0xFFFFFFFFU
+#define PPA_RND_ECO_HIGH_S  0
+
+/** PPA_ECO_CELL_CTRL_REG register
+ *  Reserved.
+ */
+#define PPA_ECO_CELL_CTRL_REG (DR_REG_PPA_BASE + 0x88)
+/** PPA_RDN_RESULT : RO; bitpos: [0]; default: 0;
+ *  Reserved.
+ */
+#define PPA_RDN_RESULT    (BIT(0))
+#define PPA_RDN_RESULT_M  (PPA_RDN_RESULT_V << PPA_RDN_RESULT_S)
+#define PPA_RDN_RESULT_V  0x00000001U
+#define PPA_RDN_RESULT_S  0
+/** PPA_RDN_ENA : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define PPA_RDN_ENA    (BIT(1))
+#define PPA_RDN_ENA_M  (PPA_RDN_ENA_V << PPA_RDN_ENA_S)
+#define PPA_RDN_ENA_V  0x00000001U
+#define PPA_RDN_ENA_S  1
+
+/** PPA_SRAM_CTRL_REG register
+ *  PPA SRAM Control Register
+ */
+#define PPA_SRAM_CTRL_REG (DR_REG_PPA_BASE + 0x8c)
+/** PPA_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  Control signals
+ */
+#define PPA_MEM_AUX_CTRL    0x00003FFFU
+#define PPA_MEM_AUX_CTRL_M  (PPA_MEM_AUX_CTRL_V << PPA_MEM_AUX_CTRL_S)
+#define PPA_MEM_AUX_CTRL_V  0x00003FFFU
+#define PPA_MEM_AUX_CTRL_S  0
+
+/** PPA_DEBUG_CTRL0_REG register
+ *  debug register
+ */
+#define PPA_DEBUG_CTRL0_REG (DR_REG_PPA_BASE + 0x90)
+/** PPA_DBG_REPLACE_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx
+ *  bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6:
+ *  blend output
+ */
+#define PPA_DBG_REPLACE_SEL    0x00000007U
+#define PPA_DBG_REPLACE_SEL_M  (PPA_DBG_REPLACE_SEL_V << PPA_DBG_REPLACE_SEL_S)
+#define PPA_DBG_REPLACE_SEL_V  0x00000007U
+#define PPA_DBG_REPLACE_SEL_S  0
+
+/** PPA_DEBUG_CTRL1_REG register
+ *  debug register
+ */
+#define PPA_DEBUG_CTRL1_REG (DR_REG_PPA_BASE + 0x94)
+/** PPA_DBG_REPLACE_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the replace data
+ */
+#define PPA_DBG_REPLACE_DATA    0xFFFFFFFFU
+#define PPA_DBG_REPLACE_DATA_M  (PPA_DBG_REPLACE_DATA_V << PPA_DBG_REPLACE_DATA_S)
+#define PPA_DBG_REPLACE_DATA_V  0xFFFFFFFFU
+#define PPA_DBG_REPLACE_DATA_S  0
+
+/** PPA_RGB2GRAY_REG register
+ *  rgb2gray register
+ */
+#define PPA_RGB2GRAY_REG (DR_REG_PPA_BASE + 0x98)
+/** PPA_RGB2GRAY_B : R/W; bitpos: [7:0]; default: 85;
+ *  Configures the b parameter for rgb2gray
+ */
+#define PPA_RGB2GRAY_B    0x000000FFU
+#define PPA_RGB2GRAY_B_M  (PPA_RGB2GRAY_B_V << PPA_RGB2GRAY_B_S)
+#define PPA_RGB2GRAY_B_V  0x000000FFU
+#define PPA_RGB2GRAY_B_S  0
+/** PPA_RGB2GRAY_G : R/W; bitpos: [15:8]; default: 86;
+ *  Configures the g parameter for rgb2gray
+ */
+#define PPA_RGB2GRAY_G    0x000000FFU
+#define PPA_RGB2GRAY_G_M  (PPA_RGB2GRAY_G_V << PPA_RGB2GRAY_G_S)
+#define PPA_RGB2GRAY_G_V  0x000000FFU
+#define PPA_RGB2GRAY_G_S  8
+/** PPA_RGB2GRAY_R : R/W; bitpos: [23:16]; default: 85;
+ *  Configures the r parameter for rgb2gray
+ */
+#define PPA_RGB2GRAY_R    0x000000FFU
+#define PPA_RGB2GRAY_R_M  (PPA_RGB2GRAY_R_V << PPA_RGB2GRAY_R_S)
+#define PPA_RGB2GRAY_R_V  0x000000FFU
+#define PPA_RGB2GRAY_R_S  16
+
+/** PPA_DATE_REG register
+ *  PPA Version register
+ */
+#define PPA_DATE_REG (DR_REG_PPA_BASE + 0x100)
+/** PPA_DATE : R/W; bitpos: [31:0]; default: 539234848;
+ *  register version.
+ */
+#define PPA_DATE    0xFFFFFFFFU
+#define PPA_DATE_M  (PPA_DATE_V << PPA_DATE_S)
+#define PPA_DATE_V  0xFFFFFFFFU
+#define PPA_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h
new file mode 100644
index 0000000000..fe85942a62
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h
@@ -0,0 +1,908 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of blend0_clut_data register
+ *  CLUT sram data read/write register in background plane of blender
+ */
+typedef union {
+    struct {
+        /** rdwr_word_blend0_clut : R/W; bitpos: [31:0]; default: 0;
+         *  Write and read data to/from CLUT RAM in background plane of blender engine through
+         *  this field in fifo mode.
+         */
+        uint32_t rdwr_word_blend0_clut:32;
+    };
+    uint32_t val;
+} ppa_blend0_clut_data_reg_t;
+
+/** Type of blend1_clut_data register
+ *  CLUT sram data read/write register in foreground plane of blender
+ */
+typedef union {
+    struct {
+        /** rdwr_word_blend1_clut : R/W; bitpos: [31:0]; default: 0;
+         *  Write and read data to/from CLUT RAM in foreground plane of blender engine through
+         *  this field in fifo mode.
+         */
+        uint32_t rdwr_word_blend1_clut:32;
+    };
+    uint32_t val;
+} ppa_blend1_clut_data_reg_t;
+
+/** Type of clut_conf register
+ *  CLUT configure register
+ */
+typedef union {
+    struct {
+        /** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
+         *  1'b0: fifo mode to wr/rd clut0/clut1 RAM through register
+         *  PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1:
+         *  memory mode to wr/rd blend0/blend1 clut RAM. The bit 11 and 10 of the waddr
+         *  should be 01 to access blend0 clut and should be 10 to access blend1 clut in memory mode.
+         */
+        uint32_t apb_fifo_mask:1;
+        /** blend0_clut_mem_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0 to this bit to reset BLEND0 CLUT.
+         */
+        uint32_t blend0_clut_mem_rst:1;
+        /** blend1_clut_mem_rst : R/W; bitpos: [2]; default: 0;
+         *  Write 1 then write 0 to this bit to reset BLEND1 CLUT.
+         */
+        uint32_t blend1_clut_mem_rst:1;
+        /** blend0_clut_mem_rdaddr_rst : R/W; bitpos: [3]; default: 0;
+         *  Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode.
+         */
+        uint32_t blend0_clut_mem_rdaddr_rst:1;
+        /** blend1_clut_mem_rdaddr_rst : R/W; bitpos: [4]; default: 0;
+         *  Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode.
+         */
+        uint32_t blend1_clut_mem_rdaddr_rst:1;
+        /** blend_clut_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  1: force power down BLEND CLUT memory.
+         */
+        uint32_t blend_clut_mem_force_pd:1;
+        /** blend_clut_mem_force_pu : R/W; bitpos: [6]; default: 0;
+         *  1: force power up BLEND CLUT memory.
+         */
+        uint32_t blend_clut_mem_force_pu:1;
+        /** blend_clut_mem_clk_ena : R/W; bitpos: [7]; default: 0;
+         *  1: Force clock on for BLEND CLUT memory.
+         */
+        uint32_t blend_clut_mem_clk_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ppa_clut_conf_reg_t;
+
+/** Type of sr_color_mode register
+ *  Scaling and rotating engine color mode register
+ */
+typedef union {
+    struct {
+        /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0;
+         *  The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1:
+         *  RGB888. 2: RGB565. 8: YUV420. others: Reserved.
+         */
+        uint32_t sr_rx_cm:4;
+        /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0;
+         *  The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888.
+         *  1: RGB888. 2: RGB565. 8: YUV420. others: Reserved.
+         */
+        uint32_t sr_tx_cm:4;
+        /** yuv_rx_range : R/W; bitpos: [8]; default: 0;
+         *  YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range
+         */
+        uint32_t yuv_rx_range:1;
+        /** yuv_tx_range : R/W; bitpos: [9]; default: 0;
+         *  YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range
+         */
+        uint32_t yuv_tx_range:1;
+        /** yuv2rgb_protocol : R/W; bitpos: [10]; default: 0;
+         *  YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709
+         */
+        uint32_t yuv2rgb_protocol:1;
+        /** rgb2yuv_protocol : R/W; bitpos: [11]; default: 0;
+         *  RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
+         */
+        uint32_t rgb2yuv_protocol:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} ppa_sr_color_mode_reg_t;
+
+/** Type of blend_color_mode register
+ *  blending engine color mode register
+ */
+typedef union {
+    struct {
+        /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0;
+         *  The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2:
+         *  RGB565. 3: Reserved. 4: L8. 5: L4.
+         */
+        uint32_t blend0_rx_cm:4;
+        /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0;
+         *  The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2:
+         *  RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4.
+         */
+        uint32_t blend1_rx_cm:4;
+        /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0;
+         *  The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2:
+         *  RGB565. 3: Reserved..
+         */
+        uint32_t blend_tx_cm:4;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} ppa_blend_color_mode_reg_t;
+
+/** Type of sr_byte_order register
+ *  Scaling and rotating engine byte order register
+ */
+typedef union {
+    struct {
+        /** sr_rx_byte_swap_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+         *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+         */
+        uint32_t sr_rx_byte_swap_en:1;
+        /** sr_rx_rgb_swap_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+         *  would be swap to bgr.
+         */
+        uint32_t sr_rx_rgb_swap_en:1;
+        /** sr_macro_bk_ro_bypass : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to bypass the macro block order function. This function is used
+         *  to improve efficient accessing external memory.
+         */
+        uint32_t sr_macro_bk_ro_bypass:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_sr_byte_order_reg_t;
+
+/** Type of blend_byte_order register
+ *  Blending engine byte order register
+ */
+typedef union {
+    struct {
+        /** blend0_rx_byte_swap_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+         *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+         */
+        uint32_t blend0_rx_byte_swap_en:1;
+        /** blend1_rx_byte_swap_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+         *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+         */
+        uint32_t blend1_rx_byte_swap_en:1;
+        /** blend0_rx_rgb_swap_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+         *  would be swap to bgr.
+         */
+        uint32_t blend0_rx_rgb_swap_en:1;
+        /** blend1_rx_rgb_swap_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+         *  would be swap to bgr.
+         */
+        uint32_t blend1_rx_rgb_swap_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ppa_blend_byte_order_reg_t;
+
+/** Type of blend_trans_mode register
+ *  Blending engine mode configure register
+ */
+typedef union {
+    struct {
+        /** blend_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable alpha blending.
+         */
+        uint32_t blend_en:1;
+        /** blend_bypass : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to bypass blender. Then background date would be output.
+         */
+        uint32_t blend_bypass:1;
+        /** blend_fix_pixel_fill_en : R/W; bitpos: [2]; default: 0;
+         *  This bit is used to enable fix pixel filling. When this mode is enable  only Tx
+         *  channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL.
+         */
+        uint32_t blend_fix_pixel_fill_en:1;
+        /** blend_trans_mode_update : WT; bitpos: [3]; default: 0;
+         *  Set this bit to update the transfer mode. Only the bit is set  the transfer mode is
+         *  valid.
+         */
+        uint32_t blend_trans_mode_update:1;
+        /** blend_rst : R/W; bitpos: [4]; default: 0;
+         *  write 1 then write 0 to reset blending engine.
+         */
+        uint32_t blend_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} ppa_blend_trans_mode_reg_t;
+
+/** Type of sr_fix_alpha register
+ *  Scaling and rotating engine alpha override register
+ */
+typedef union {
+    struct {
+        /** sr_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128;
+         *  The value would replace the alpha value in received pixel for Scaling and Rotating
+         *  engine when PPA_SR_RX_ALPHA_CONF_EN is enabled.
+         */
+        uint32_t sr_rx_fix_alpha:8;
+        /** sr_rx_alpha_mod : R/W; bitpos: [9:8]; default: 0;
+         *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
+         *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+         */
+        uint32_t sr_rx_alpha_mod:2;
+        /** sr_rx_alpha_inv : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to invert the original alpha value. When RX color mode is
+         *  RGB565/RGB88. The original alpha value is 255.
+         */
+        uint32_t sr_rx_alpha_inv:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} ppa_sr_fix_alpha_reg_t;
+
+/** Type of blend_tx_size register
+ *  Fix pixel filling mode image size register
+ */
+typedef union {
+    struct {
+        /** blend_hb : R/W; bitpos: [13:0]; default: 0;
+         *  The horizontal width of image block that would be filled in fix pixel filling mode.
+         *  The unit is pixel
+         */
+        uint32_t blend_hb:14;
+        /** blend_vb : R/W; bitpos: [27:14]; default: 0;
+         *  The vertical width of image block that would be filled in fix pixel filling mode.
+         *  The unit is pixel
+         */
+        uint32_t blend_vb:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ppa_blend_tx_size_reg_t;
+
+/** Type of blend_fix_alpha register
+ *  Blending engine alpha override register
+ */
+typedef union {
+    struct {
+        /** blend0_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128;
+         *  The value would replace the alpha value in received pixel for background plane of
+         *  blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled.
+         */
+        uint32_t blend0_rx_fix_alpha:8;
+        /** blend1_rx_fix_alpha : R/W; bitpos: [15:8]; default: 128;
+         *  The value would replace the alpha value in received pixel for foreground plane of
+         *  blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled.
+         */
+        uint32_t blend1_rx_fix_alpha:8;
+        /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0;
+         *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
+         *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+         */
+        uint32_t blend0_rx_alpha_mod:2;
+        /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0;
+         *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
+         *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+         */
+        uint32_t blend1_rx_alpha_mod:2;
+        /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to invert the original alpha value. When RX color mode is
+         *  RGB565/RGB88. The original alpha value is 255.
+         */
+        uint32_t blend0_rx_alpha_inv:1;
+        /** blend1_rx_alpha_inv : R/W; bitpos: [21]; default: 0;
+         *  Set this bit to invert the original alpha value. When RX color mode is
+         *  RGB565/RGB88. The original alpha value is 255.
+         */
+        uint32_t blend1_rx_alpha_inv:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} ppa_blend_fix_alpha_reg_t;
+
+/** Type of blend_rgb register
+ *  RGB color register
+ */
+typedef union {
+    struct {
+        /** blend1_rx_b : R/W; bitpos: [7:0]; default: 128;
+         *  blue color for A4/A8 mode.
+         */
+        uint32_t blend1_rx_b:8;
+        /** blend1_rx_g : R/W; bitpos: [15:8]; default: 128;
+         *  green color for A4/A8 mode.
+         */
+        uint32_t blend1_rx_g:8;
+        /** blend1_rx_r : R/W; bitpos: [23:16]; default: 128;
+         *  red color for A4/A8 mode.
+         */
+        uint32_t blend1_rx_r:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_blend_rgb_reg_t;
+
+/** Type of blend_fix_pixel register
+ *  Blending engine fix pixel register
+ */
+typedef union {
+    struct {
+        /** blend_tx_fix_pixel : R/W; bitpos: [31:0]; default: 0;
+         *  The configure fix pixel in fix pixel filling mode for blender engine.
+         */
+        uint32_t blend_tx_fix_pixel:32;
+    };
+    uint32_t val;
+} ppa_blend_fix_pixel_reg_t;
+
+/** Type of ck_fg_low register
+ *  foreground color key lower threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_fg_b_low : R/W; bitpos: [7:0]; default: 255;
+         *  color key lower threshold of foreground b channel
+         */
+        uint32_t colorkey_fg_b_low:8;
+        /** colorkey_fg_g_low : R/W; bitpos: [15:8]; default: 255;
+         *  color key lower threshold of foreground g channel
+         */
+        uint32_t colorkey_fg_g_low:8;
+        /** colorkey_fg_r_low : R/W; bitpos: [23:16]; default: 255;
+         *  color key lower threshold of foreground r channel
+         */
+        uint32_t colorkey_fg_r_low:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_fg_low_reg_t;
+
+/** Type of ck_fg_high register
+ *  foreground color key higher threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_fg_b_high : R/W; bitpos: [7:0]; default: 0;
+         *  color key higher threshold of foreground b channel
+         */
+        uint32_t colorkey_fg_b_high:8;
+        /** colorkey_fg_g_high : R/W; bitpos: [15:8]; default: 0;
+         *  color key higher threshold of foreground g channel
+         */
+        uint32_t colorkey_fg_g_high:8;
+        /** colorkey_fg_r_high : R/W; bitpos: [23:16]; default: 0;
+         *  color key higher threshold of foreground r channel
+         */
+        uint32_t colorkey_fg_r_high:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_fg_high_reg_t;
+
+/** Type of ck_bg_low register
+ *  background color key lower threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_bg_b_low : R/W; bitpos: [7:0]; default: 255;
+         *  color key lower threshold of background b channel
+         */
+        uint32_t colorkey_bg_b_low:8;
+        /** colorkey_bg_g_low : R/W; bitpos: [15:8]; default: 255;
+         *  color key lower threshold of background g channel
+         */
+        uint32_t colorkey_bg_g_low:8;
+        /** colorkey_bg_r_low : R/W; bitpos: [23:16]; default: 255;
+         *  color key lower threshold of background r channel
+         */
+        uint32_t colorkey_bg_r_low:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_bg_low_reg_t;
+
+/** Type of ck_bg_high register
+ *  background color key higher threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_bg_b_high : R/W; bitpos: [7:0]; default: 0;
+         *  color key higher threshold of background b channel
+         */
+        uint32_t colorkey_bg_b_high:8;
+        /** colorkey_bg_g_high : R/W; bitpos: [15:8]; default: 0;
+         *  color key higher threshold of background g channel
+         */
+        uint32_t colorkey_bg_g_high:8;
+        /** colorkey_bg_r_high : R/W; bitpos: [23:16]; default: 0;
+         *  color key higher threshold of background r channel
+         */
+        uint32_t colorkey_bg_r_high:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_bg_high_reg_t;
+
+/** Type of ck_default register
+ *  default value when foreground and background both in color key range
+ */
+typedef union {
+    struct {
+        /** colorkey_default_b : R/W; bitpos: [7:0]; default: 0;
+         *  default B channel value of color key
+         */
+        uint32_t colorkey_default_b:8;
+        /** colorkey_default_g : R/W; bitpos: [15:8]; default: 0;
+         *  default G channel value of color key
+         */
+        uint32_t colorkey_default_g:8;
+        /** colorkey_default_r : R/W; bitpos: [23:16]; default: 0;
+         *  default R channel value of color key
+         */
+        uint32_t colorkey_default_r:8;
+        /** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0;
+         *  when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the
+         *  result is fg
+         */
+        uint32_t colorkey_fg_bg_reverse:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} ppa_ck_default_reg_t;
+
+/** Type of sr_scal_rotate register
+ *  Scaling and rotating coefficient register
+ */
+typedef union {
+    struct {
+        /** sr_scal_x_int : R/W; bitpos: [7:0]; default: 1;
+         *  The integrated part of scaling coefficient in X direction.
+         */
+        uint32_t sr_scal_x_int:8;
+        /** sr_scal_x_frag : R/W; bitpos: [11:8]; default: 0;
+         *  The fragment part of scaling coefficient in X direction.
+         */
+        uint32_t sr_scal_x_frag:4;
+        /** sr_scal_y_int : R/W; bitpos: [19:12]; default: 1;
+         *  The integrated part of scaling coefficient in Y direction.
+         */
+        uint32_t sr_scal_y_int:8;
+        /** sr_scal_y_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The fragment part of scaling coefficient in Y direction.
+         */
+        uint32_t sr_scal_y_frag:4;
+        /** sr_rotate_angle : R/W; bitpos: [25:24]; default: 0;
+         *  The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree.
+         */
+        uint32_t sr_rotate_angle:2;
+        /** scal_rotate_rst : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset scaling and rotating engine.
+         */
+        uint32_t scal_rotate_rst:1;
+        /** scal_rotate_start : WT; bitpos: [27]; default: 0;
+         *  Write 1 to enable scaling and rotating engine after parameter is configured.
+         */
+        uint32_t scal_rotate_start:1;
+        /** sr_mirror_x : R/W; bitpos: [28]; default: 0;
+         *  Image mirror in X direction. 0: disable, 1: enable
+         */
+        uint32_t sr_mirror_x:1;
+        /** sr_mirror_y : R/W; bitpos: [29]; default: 0;
+         *  Image mirror in Y direction. 0: disable, 1: enable
+         */
+        uint32_t sr_mirror_y:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} ppa_sr_scal_rotate_reg_t;
+
+/** Type of sr_mem_pd register
+ *  SR memory power done register
+ */
+typedef union {
+    struct {
+        /** sr_mem_clk_ena : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force clock enable of scaling and rotating engine's data memory.
+         */
+        uint32_t sr_mem_clk_ena:1;
+        /** sr_mem_force_pd : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to force power down scaling and rotating engine's data memory.
+         */
+        uint32_t sr_mem_force_pd:1;
+        /** sr_mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power up scaling and rotating engine's data memory.
+         */
+        uint32_t sr_mem_force_pu:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_sr_mem_pd_reg_t;
+
+/** Type of reg_conf register
+ *  Register clock enable register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  PPA register clock gate enable signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ppa_reg_conf_reg_t;
+
+/** Type of eco_low register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_low:32;
+    };
+    uint32_t val;
+} ppa_eco_low_reg_t;
+
+/** Type of eco_high register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_high:32;
+    };
+    uint32_t val;
+} ppa_eco_high_reg_t;
+
+/** Type of sram_ctrl register
+ *  PPA SRAM Control Register
+ */
+typedef union {
+    struct {
+        /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  Control signals
+         */
+        uint32_t mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} ppa_sram_ctrl_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  Raw status interrupt
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when scaling and rotating engine
+         *  calculate one frame image.
+         */
+        uint32_t sr_eof_int_raw:1;
+        /** blend_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when blending engine calculate one frame
+         *  image.
+         */
+        uint32_t blend_eof_int_raw:1;
+        /** sr_param_cfg_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the configured scaling and rotating
+         *  coefficient is wrong. User can check the reasons through register
+         *  PPA_SR_PARAM_ERR_ST_REG.
+         */
+        uint32_t sr_param_cfg_err_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the PPA_SR_EOF_INT interrupt.
+         */
+        uint32_t sr_eof_int_st:1;
+        /** blend_eof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt.
+         */
+        uint32_t blend_eof_int_st:1;
+        /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt.
+         */
+        uint32_t sr_param_cfg_err_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the PPA_SR_EOF_INT interrupt.
+         */
+        uint32_t sr_eof_int_ena:1;
+        /** blend_eof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt.
+         */
+        uint32_t blend_eof_int_ena:1;
+        /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt.
+         */
+        uint32_t sr_param_cfg_err_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the PPA_SR_EOF_INT interrupt.
+         */
+        uint32_t sr_eof_int_clr:1;
+        /** blend_eof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the PPA_BLEND_EOF_INT interrupt.
+         */
+        uint32_t blend_eof_int_clr:1;
+        /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt.
+         */
+        uint32_t sr_param_cfg_err_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_int_clr_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of clut_cnt register
+ *  BLEND CLUT write counter register
+ */
+typedef union {
+    struct {
+        /** blend0_clut_cnt : RO; bitpos: [8:0]; default: 0;
+         *  The write data counter of BLEND0 CLUT in fifo mode.
+         */
+        uint32_t blend0_clut_cnt:9;
+        /** blend1_clut_cnt : RO; bitpos: [17:9]; default: 0;
+         *  The write data counter of BLEND1 CLUT in fifo mode.
+         */
+        uint32_t blend1_clut_cnt:9;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} ppa_clut_cnt_reg_t;
+
+/** Type of blend_st register
+ *  Blending engine status register
+ */
+typedef union {
+    struct {
+        /** blend_size_diff_st : RO; bitpos: [0]; default: 0;
+         *  1: indicate the size of two image is different.
+         */
+        uint32_t blend_size_diff_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ppa_blend_st_reg_t;
+
+/** Type of sr_param_err_st register
+ *  Scaling and rotating coefficient error register
+ */
+typedef union {
+    struct {
+        /** tx_dscr_vb_err_st : RO; bitpos: [0]; default: 0;
+         *  The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive
+         *  descriptor is larger than VA in 2DDMA receive descriptor.
+         */
+        uint32_t tx_dscr_vb_err_st:1;
+        /** tx_dscr_hb_err_st : RO; bitpos: [1]; default: 0;
+         *  The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive
+         *  descriptor is larger than HA in 2DDMA receive descriptor.
+         */
+        uint32_t tx_dscr_hb_err_st:1;
+        /** y_rx_scal_equal_0_err_st : RO; bitpos: [2]; default: 0;
+         *  The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0.
+         */
+        uint32_t y_rx_scal_equal_0_err_st:1;
+        /** rx_dscr_vb_err_st : RO; bitpos: [3]; default: 0;
+         *  The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in
+         *  2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor
+         */
+        uint32_t rx_dscr_vb_err_st:1;
+        /** ydst_len_too_samll_err_st : RO; bitpos: [4]; default: 0;
+         *  The error is that the scaled image width is 0. For example.  when source width is
+         *  14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as
+         *  the result would be floored.
+         */
+        uint32_t ydst_len_too_samll_err_st:1;
+        /** ydst_len_too_large_err_st : RO; bitpos: [5]; default: 0;
+         *  The error is that the scaled width is larger than (2^13 - 1).
+         */
+        uint32_t ydst_len_too_large_err_st:1;
+        /** x_rx_scal_equal_0_err_st : RO; bitpos: [6]; default: 0;
+         *  The error is that the scaled image height is 0.
+         */
+        uint32_t x_rx_scal_equal_0_err_st:1;
+        /** rx_dscr_hb_err_st : RO; bitpos: [7]; default: 0;
+         *  The error is that the HB in 2DDMA transmit descriptor plus the offset of X
+         *  coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit
+         *  descriptor.
+         */
+        uint32_t rx_dscr_hb_err_st:1;
+        /** xdst_len_too_samll_err_st : RO; bitpos: [8]; default: 0;
+         *  The error is that the scaled image height is 0. For example.  when source height is
+         *  14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as
+         *  the result would be floored.
+         */
+        uint32_t xdst_len_too_samll_err_st:1;
+        /** xdst_len_too_large_err_st : RO; bitpos: [9]; default: 0;
+         *  The error is that the scaled image height is larger than (2^13 - 1).
+         */
+        uint32_t xdst_len_too_large_err_st:1;
+        /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0;
+         *  The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
+         *  yuv420 rx
+         */
+        uint32_t x_yuv420_rx_scale_err_st:1;
+        /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0;
+         *  The error is that the va/vb/y param in dma2d descriptor is an odd num when enable
+         *  yuv420 rx
+         */
+        uint32_t y_yuv420_rx_scale_err_st:1;
+        /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0;
+         *  The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
+         *  yuv420 tx
+         */
+        uint32_t x_yuv420_tx_scale_err_st:1;
+        /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0;
+         *  The error is that the va/vb/y param in dma2d descriptor is an odd num when enable
+         *  yuv420 tx
+         */
+        uint32_t y_yuv420_tx_scale_err_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} ppa_sr_param_err_st_reg_t;
+
+/** Type of sr_status register
+ *  SR FSM register
+ */
+typedef union {
+    struct {
+        /** sr_rx_dscr_sample_state : RO; bitpos: [1:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_rx_dscr_sample_state:2;
+        /** sr_rx_scan_state : RO; bitpos: [3:2]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_rx_scan_state:2;
+        /** sr_tx_dscr_sample_state : RO; bitpos: [5:4]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_tx_dscr_sample_state:2;
+        /** sr_tx_scan_state : RO; bitpos: [8:6]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_tx_scan_state:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} ppa_sr_status_reg_t;
+
+/** Type of eco_cell_ctrl register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rdn_result : RO; bitpos: [0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_result:1;
+        /** rdn_ena : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ppa_eco_cell_ctrl_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  PPA Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36716609;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} ppa_date_reg_t;
+
+
+typedef struct ppa_dev_t {
+    volatile ppa_blend0_clut_data_reg_t blend0_clut_data;
+    volatile ppa_blend1_clut_data_reg_t blend1_clut_data;
+    uint32_t reserved_008;
+    volatile ppa_clut_conf_reg_t clut_conf;
+    volatile ppa_int_raw_reg_t int_raw;
+    volatile ppa_int_st_reg_t int_st;
+    volatile ppa_int_ena_reg_t int_ena;
+    volatile ppa_int_clr_reg_t int_clr;
+    volatile ppa_sr_color_mode_reg_t sr_color_mode;
+    volatile ppa_blend_color_mode_reg_t blend_color_mode;
+    volatile ppa_sr_byte_order_reg_t sr_byte_order;
+    volatile ppa_blend_byte_order_reg_t blend_byte_order;
+    uint32_t reserved_030;
+    volatile ppa_blend_trans_mode_reg_t blend_trans_mode;
+    volatile ppa_sr_fix_alpha_reg_t sr_fix_alpha;
+    volatile ppa_blend_tx_size_reg_t blend_tx_size;
+    volatile ppa_blend_fix_alpha_reg_t blend_fix_alpha;
+    uint32_t reserved_044;
+    volatile ppa_blend_rgb_reg_t blend_rgb;
+    volatile ppa_blend_fix_pixel_reg_t blend_fix_pixel;
+    volatile ppa_ck_fg_low_reg_t ck_fg_low;
+    volatile ppa_ck_fg_high_reg_t ck_fg_high;
+    volatile ppa_ck_bg_low_reg_t ck_bg_low;
+    volatile ppa_ck_bg_high_reg_t ck_bg_high;
+    volatile ppa_ck_default_reg_t ck_default;
+    volatile ppa_sr_scal_rotate_reg_t sr_scal_rotate;
+    volatile ppa_sr_mem_pd_reg_t sr_mem_pd;
+    volatile ppa_reg_conf_reg_t reg_conf;
+    volatile ppa_clut_cnt_reg_t clut_cnt;
+    volatile ppa_blend_st_reg_t blend_st;
+    volatile ppa_sr_param_err_st_reg_t sr_param_err_st;
+    volatile ppa_sr_status_reg_t sr_status;
+    volatile ppa_eco_low_reg_t eco_low;
+    volatile ppa_eco_high_reg_t eco_high;
+    volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl;
+    volatile ppa_sram_ctrl_reg_t sram_ctrl;
+    uint32_t reserved_090[28];
+    volatile ppa_date_reg_t date;
+} ppa_dev_t;
+
+extern ppa_dev_t PPA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ppa_dev_t) == 0x104, "Invalid size of ppa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pvt_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/pvt_reg.h
new file mode 100644
index 0000000000..cae14a798b
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pvt_reg.h
@@ -0,0 +1,3955 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PVT_PMUP_BITMAP_HIGH0_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_HIGH0_REG (DR_REG_PVT_BASE + 0x0)
+/** PVT_PUMP_BITMAP_HIGH0 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid high channel0
+ */
+#define PVT_PUMP_BITMAP_HIGH0    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH0_M  (PVT_PUMP_BITMAP_HIGH0_V << PVT_PUMP_BITMAP_HIGH0_S)
+#define PVT_PUMP_BITMAP_HIGH0_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH0_S  0
+
+/** PVT_PMUP_BITMAP_HIGH1_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_HIGH1_REG (DR_REG_PVT_BASE + 0x4)
+/** PVT_PUMP_BITMAP_HIGH1 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid high channel1
+ */
+#define PVT_PUMP_BITMAP_HIGH1    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH1_M  (PVT_PUMP_BITMAP_HIGH1_V << PVT_PUMP_BITMAP_HIGH1_S)
+#define PVT_PUMP_BITMAP_HIGH1_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH1_S  0
+
+/** PVT_PMUP_BITMAP_HIGH2_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_HIGH2_REG (DR_REG_PVT_BASE + 0x8)
+/** PVT_PUMP_BITMAP_HIGH2 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid high channel2
+ */
+#define PVT_PUMP_BITMAP_HIGH2    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH2_M  (PVT_PUMP_BITMAP_HIGH2_V << PVT_PUMP_BITMAP_HIGH2_S)
+#define PVT_PUMP_BITMAP_HIGH2_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH2_S  0
+
+/** PVT_PMUP_BITMAP_HIGH3_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_HIGH3_REG (DR_REG_PVT_BASE + 0xc)
+/** PVT_PUMP_BITMAP_HIGH3 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid high channel3
+ */
+#define PVT_PUMP_BITMAP_HIGH3    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH3_M  (PVT_PUMP_BITMAP_HIGH3_V << PVT_PUMP_BITMAP_HIGH3_S)
+#define PVT_PUMP_BITMAP_HIGH3_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH3_S  0
+
+/** PVT_PMUP_BITMAP_HIGH4_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_HIGH4_REG (DR_REG_PVT_BASE + 0x10)
+/** PVT_PUMP_BITMAP_HIGH4 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid high channel4
+ */
+#define PVT_PUMP_BITMAP_HIGH4    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH4_M  (PVT_PUMP_BITMAP_HIGH4_V << PVT_PUMP_BITMAP_HIGH4_S)
+#define PVT_PUMP_BITMAP_HIGH4_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH4_S  0
+
+/** PVT_PMUP_BITMAP_LOW0_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_LOW0_REG (DR_REG_PVT_BASE + 0x14)
+/** PVT_PUMP_BITMAP_LOW0 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid low channel0
+ */
+#define PVT_PUMP_BITMAP_LOW0    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW0_M  (PVT_PUMP_BITMAP_LOW0_V << PVT_PUMP_BITMAP_LOW0_S)
+#define PVT_PUMP_BITMAP_LOW0_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW0_S  0
+
+/** PVT_PMUP_BITMAP_LOW1_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_LOW1_REG (DR_REG_PVT_BASE + 0x18)
+/** PVT_PUMP_BITMAP_LOW1 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid low channel1
+ */
+#define PVT_PUMP_BITMAP_LOW1    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW1_M  (PVT_PUMP_BITMAP_LOW1_V << PVT_PUMP_BITMAP_LOW1_S)
+#define PVT_PUMP_BITMAP_LOW1_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW1_S  0
+
+/** PVT_PMUP_BITMAP_LOW2_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_LOW2_REG (DR_REG_PVT_BASE + 0x1c)
+/** PVT_PUMP_BITMAP_LOW2 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid low channel2
+ */
+#define PVT_PUMP_BITMAP_LOW2    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW2_M  (PVT_PUMP_BITMAP_LOW2_V << PVT_PUMP_BITMAP_LOW2_S)
+#define PVT_PUMP_BITMAP_LOW2_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW2_S  0
+
+/** PVT_PMUP_BITMAP_LOW3_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_LOW3_REG (DR_REG_PVT_BASE + 0x20)
+/** PVT_PUMP_BITMAP_LOW3 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid low channel3
+ */
+#define PVT_PUMP_BITMAP_LOW3    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW3_M  (PVT_PUMP_BITMAP_LOW3_V << PVT_PUMP_BITMAP_LOW3_S)
+#define PVT_PUMP_BITMAP_LOW3_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW3_S  0
+
+/** PVT_PMUP_BITMAP_LOW4_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_LOW4_REG (DR_REG_PVT_BASE + 0x24)
+/** PVT_PUMP_BITMAP_LOW4 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid low channel4
+ */
+#define PVT_PUMP_BITMAP_LOW4    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW4_M  (PVT_PUMP_BITMAP_LOW4_V << PVT_PUMP_BITMAP_LOW4_S)
+#define PVT_PUMP_BITMAP_LOW4_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW4_S  0
+
+/** PVT_PMUP_DRV_CFG_REG register
+ *  configure pump drv
+ */
+#define PVT_PMUP_DRV_CFG_REG (DR_REG_PVT_BASE + 0x28)
+/** PVT_BYPASS_EFUSE_CTRL : R/W; bitpos: [8]; default: 1;
+ *  needs desc
+ */
+#define PVT_BYPASS_EFUSE_CTRL    (BIT(8))
+#define PVT_BYPASS_EFUSE_CTRL_M  (PVT_BYPASS_EFUSE_CTRL_V << PVT_BYPASS_EFUSE_CTRL_S)
+#define PVT_BYPASS_EFUSE_CTRL_V  0x00000001U
+#define PVT_BYPASS_EFUSE_CTRL_S  8
+/** PVT_PUMP_EN : R/W; bitpos: [9]; default: 0;
+ *  configure pvt charge xpd
+ */
+#define PVT_PUMP_EN    (BIT(9))
+#define PVT_PUMP_EN_M  (PVT_PUMP_EN_V << PVT_PUMP_EN_S)
+#define PVT_PUMP_EN_V  0x00000001U
+#define PVT_PUMP_EN_S  9
+/** PVT_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  force register clken
+ */
+#define PVT_CLK_EN    (BIT(10))
+#define PVT_CLK_EN_M  (PVT_CLK_EN_V << PVT_CLK_EN_S)
+#define PVT_CLK_EN_V  0x00000001U
+#define PVT_CLK_EN_S  10
+/** PVT_PUMP_DRV4 : R/W; bitpos: [14:11]; default: 0;
+ *  configure cmd4 drv
+ */
+#define PVT_PUMP_DRV4    0x0000000FU
+#define PVT_PUMP_DRV4_M  (PVT_PUMP_DRV4_V << PVT_PUMP_DRV4_S)
+#define PVT_PUMP_DRV4_V  0x0000000FU
+#define PVT_PUMP_DRV4_S  11
+/** PVT_PUMP_DRV3 : R/W; bitpos: [18:15]; default: 0;
+ *  configure cmd3 drv
+ */
+#define PVT_PUMP_DRV3    0x0000000FU
+#define PVT_PUMP_DRV3_M  (PVT_PUMP_DRV3_V << PVT_PUMP_DRV3_S)
+#define PVT_PUMP_DRV3_V  0x0000000FU
+#define PVT_PUMP_DRV3_S  15
+/** PVT_PUMP_DRV2 : R/W; bitpos: [22:19]; default: 0;
+ *  configure cmd2 drv
+ */
+#define PVT_PUMP_DRV2    0x0000000FU
+#define PVT_PUMP_DRV2_M  (PVT_PUMP_DRV2_V << PVT_PUMP_DRV2_S)
+#define PVT_PUMP_DRV2_V  0x0000000FU
+#define PVT_PUMP_DRV2_S  19
+/** PVT_PUMP_DRV1 : R/W; bitpos: [26:23]; default: 0;
+ *  configure cmd1 drv
+ */
+#define PVT_PUMP_DRV1    0x0000000FU
+#define PVT_PUMP_DRV1_M  (PVT_PUMP_DRV1_V << PVT_PUMP_DRV1_S)
+#define PVT_PUMP_DRV1_V  0x0000000FU
+#define PVT_PUMP_DRV1_S  23
+/** PVT_PUMP_DRV0 : R/W; bitpos: [30:27]; default: 0;
+ *  configure cmd0 drv
+ */
+#define PVT_PUMP_DRV0    0x0000000FU
+#define PVT_PUMP_DRV0_M  (PVT_PUMP_DRV0_V << PVT_PUMP_DRV0_S)
+#define PVT_PUMP_DRV0_V  0x0000000FU
+#define PVT_PUMP_DRV0_S  27
+
+/** PVT_PMUP_CHANNEL_CFG_REG register
+ *  configure the code of valid pump channel code
+ */
+#define PVT_PMUP_CHANNEL_CFG_REG (DR_REG_PVT_BASE + 0x2c)
+/** PVT_PUMP_CHANNEL_CODE4 : R/W; bitpos: [11:7]; default: 0;
+ *  configure cmd4 code
+ */
+#define PVT_PUMP_CHANNEL_CODE4    0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE4_M  (PVT_PUMP_CHANNEL_CODE4_V << PVT_PUMP_CHANNEL_CODE4_S)
+#define PVT_PUMP_CHANNEL_CODE4_V  0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE4_S  7
+/** PVT_PUMP_CHANNEL_CODE3 : R/W; bitpos: [16:12]; default: 0;
+ *  configure cmd3 code
+ */
+#define PVT_PUMP_CHANNEL_CODE3    0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE3_M  (PVT_PUMP_CHANNEL_CODE3_V << PVT_PUMP_CHANNEL_CODE3_S)
+#define PVT_PUMP_CHANNEL_CODE3_V  0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE3_S  12
+/** PVT_PUMP_CHANNEL_CODE2 : R/W; bitpos: [21:17]; default: 0;
+ *  configure cmd2 code
+ */
+#define PVT_PUMP_CHANNEL_CODE2    0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE2_M  (PVT_PUMP_CHANNEL_CODE2_V << PVT_PUMP_CHANNEL_CODE2_S)
+#define PVT_PUMP_CHANNEL_CODE2_V  0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE2_S  17
+/** PVT_PUMP_CHANNEL_CODE1 : R/W; bitpos: [26:22]; default: 0;
+ *  configure cmd1 code
+ */
+#define PVT_PUMP_CHANNEL_CODE1    0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE1_M  (PVT_PUMP_CHANNEL_CODE1_V << PVT_PUMP_CHANNEL_CODE1_S)
+#define PVT_PUMP_CHANNEL_CODE1_V  0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE1_S  22
+/** PVT_PUMP_CHANNEL_CODE0 : R/W; bitpos: [31:27]; default: 0;
+ *  configure cmd0 code
+ */
+#define PVT_PUMP_CHANNEL_CODE0    0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE0_M  (PVT_PUMP_CHANNEL_CODE0_V << PVT_PUMP_CHANNEL_CODE0_S)
+#define PVT_PUMP_CHANNEL_CODE0_V  0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE0_S  27
+
+/** PVT_CLK_CFG_REG register
+ *  configure pvt clk
+ */
+#define PVT_CLK_CFG_REG (DR_REG_PVT_BASE + 0x30)
+/** PVT_PUMP_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_PUMP_CLK_DIV_NUM    0x000000FFU
+#define PVT_PUMP_CLK_DIV_NUM_M  (PVT_PUMP_CLK_DIV_NUM_V << PVT_PUMP_CLK_DIV_NUM_S)
+#define PVT_PUMP_CLK_DIV_NUM_V  0x000000FFU
+#define PVT_PUMP_CLK_DIV_NUM_S  0
+/** PVT_MONITOR_CLK_PVT_EN : R/W; bitpos: [8]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_CLK_PVT_EN    (BIT(8))
+#define PVT_MONITOR_CLK_PVT_EN_M  (PVT_MONITOR_CLK_PVT_EN_V << PVT_MONITOR_CLK_PVT_EN_S)
+#define PVT_MONITOR_CLK_PVT_EN_V  0x00000001U
+#define PVT_MONITOR_CLK_PVT_EN_S  8
+/** PVT_CLK_SEL : R/W; bitpos: [31]; default: 0;
+ *  select pvt clk
+ */
+#define PVT_CLK_SEL    (BIT(31))
+#define PVT_CLK_SEL_M  (PVT_CLK_SEL_V << PVT_CLK_SEL_S)
+#define PVT_CLK_SEL_V  0x00000001U
+#define PVT_CLK_SEL_S  31
+
+/** PVT_DBIAS_CHANNEL_SEL0_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL_SEL0_REG (DR_REG_PVT_BASE + 0x34)
+/** PVT_DBIAS_CHANNEL3_SEL : R/W; bitpos: [10:4]; default: 64;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL3_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL3_SEL_M  (PVT_DBIAS_CHANNEL3_SEL_V << PVT_DBIAS_CHANNEL3_SEL_S)
+#define PVT_DBIAS_CHANNEL3_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL3_SEL_S  4
+/** PVT_DBIAS_CHANNEL2_SEL : R/W; bitpos: [17:11]; default: 64;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL2_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL2_SEL_M  (PVT_DBIAS_CHANNEL2_SEL_V << PVT_DBIAS_CHANNEL2_SEL_S)
+#define PVT_DBIAS_CHANNEL2_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL2_SEL_S  11
+/** PVT_DBIAS_CHANNEL1_SEL : R/W; bitpos: [24:18]; default: 64;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL1_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL1_SEL_M  (PVT_DBIAS_CHANNEL1_SEL_V << PVT_DBIAS_CHANNEL1_SEL_S)
+#define PVT_DBIAS_CHANNEL1_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL1_SEL_S  18
+/** PVT_DBIAS_CHANNEL0_SEL : R/W; bitpos: [31:25]; default: 64;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL0_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL0_SEL_M  (PVT_DBIAS_CHANNEL0_SEL_V << PVT_DBIAS_CHANNEL0_SEL_S)
+#define PVT_DBIAS_CHANNEL0_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL0_SEL_S  25
+
+/** PVT_DBIAS_CHANNEL_SEL1_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL_SEL1_REG (DR_REG_PVT_BASE + 0x38)
+/** PVT_DBIAS_CHANNEL4_SEL : R/W; bitpos: [31:25]; default: 64;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL4_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL4_SEL_M  (PVT_DBIAS_CHANNEL4_SEL_V << PVT_DBIAS_CHANNEL4_SEL_S)
+#define PVT_DBIAS_CHANNEL4_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL4_SEL_S  25
+
+/** PVT_DBIAS_CHANNEL0_SEL_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL0_SEL_REG (DR_REG_PVT_BASE + 0x3c)
+/** PVT_DBIAS_CHANNEL0_CFG : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL0_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL0_CFG_M  (PVT_DBIAS_CHANNEL0_CFG_V << PVT_DBIAS_CHANNEL0_CFG_S)
+#define PVT_DBIAS_CHANNEL0_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL0_CFG_S  0
+
+/** PVT_DBIAS_CHANNEL1_SEL_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL1_SEL_REG (DR_REG_PVT_BASE + 0x40)
+/** PVT_DBIAS_CHANNEL1_CFG : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL1_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL1_CFG_M  (PVT_DBIAS_CHANNEL1_CFG_V << PVT_DBIAS_CHANNEL1_CFG_S)
+#define PVT_DBIAS_CHANNEL1_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL1_CFG_S  0
+
+/** PVT_DBIAS_CHANNEL2_SEL_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL2_SEL_REG (DR_REG_PVT_BASE + 0x44)
+/** PVT_DBIAS_CHANNEL2_CFG : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL2_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL2_CFG_M  (PVT_DBIAS_CHANNEL2_CFG_V << PVT_DBIAS_CHANNEL2_CFG_S)
+#define PVT_DBIAS_CHANNEL2_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL2_CFG_S  0
+
+/** PVT_DBIAS_CHANNEL3_SEL_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL3_SEL_REG (DR_REG_PVT_BASE + 0x48)
+/** PVT_DBIAS_CHANNEL3_CFG : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL3_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL3_CFG_M  (PVT_DBIAS_CHANNEL3_CFG_V << PVT_DBIAS_CHANNEL3_CFG_S)
+#define PVT_DBIAS_CHANNEL3_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL3_CFG_S  0
+
+/** PVT_DBIAS_CHANNEL4_SEL_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL4_SEL_REG (DR_REG_PVT_BASE + 0x4c)
+/** PVT_DBIAS_CHANNEL4_CFG : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL4_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL4_CFG_M  (PVT_DBIAS_CHANNEL4_CFG_V << PVT_DBIAS_CHANNEL4_CFG_S)
+#define PVT_DBIAS_CHANNEL4_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL4_CFG_S  0
+
+/** PVT_DBIAS_CMD0_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CMD0_REG (DR_REG_PVT_BASE + 0x50)
+/** PVT_DBIAS_CMD0 : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CMD0    0x0001FFFFU
+#define PVT_DBIAS_CMD0_M  (PVT_DBIAS_CMD0_V << PVT_DBIAS_CMD0_S)
+#define PVT_DBIAS_CMD0_V  0x0001FFFFU
+#define PVT_DBIAS_CMD0_S  0
+
+#define PVT_DBIAS_CMD0_OFFSET_FLAG 1
+#define PVT_DBIAS_CMD0_OFFSET_FLAG_S 16
+#define PVT_DBIAS_CMD0_OFFSET_VALUE 0x1F
+#define PVT_DBIAS_CMD0_OFFSET_VALUE_S 11
+#define PVT_DBIAS_CMD0_PVT 0x7FF
+#define PVT_DBIAS_CMD0_PVT_S 0
+
+/** PVT_DBIAS_CMD1_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CMD1_REG (DR_REG_PVT_BASE + 0x54)
+/** PVT_DBIAS_CMD1 : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CMD1    0x0001FFFFU
+#define PVT_DBIAS_CMD1_M  (PVT_DBIAS_CMD1_V << PVT_DBIAS_CMD1_S)
+#define PVT_DBIAS_CMD1_V  0x0001FFFFU
+#define PVT_DBIAS_CMD1_S  0
+
+#define PVT_DBIAS_CMD1_OFFSET_FLAG 1
+#define PVT_DBIAS_CMD1_OFFSET_FLAG_S 16
+#define PVT_DBIAS_CMD1_OFFSET_VALUE 0x1F
+#define PVT_DBIAS_CMD1_OFFSET_VALUE_S 11
+#define PVT_DBIAS_CMD1_PVT 0x7FF
+#define PVT_DBIAS_CMD1_PVT_S 0
+
+/** PVT_DBIAS_CMD2_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CMD2_REG (DR_REG_PVT_BASE + 0x58)
+/** PVT_DBIAS_CMD2 : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CMD2    0x0001FFFFU
+#define PVT_DBIAS_CMD2_M  (PVT_DBIAS_CMD2_V << PVT_DBIAS_CMD2_S)
+#define PVT_DBIAS_CMD2_V  0x0001FFFFU
+#define PVT_DBIAS_CMD2_S  0
+
+#define PVT_DBIAS_CMD2_OFFSET_FLAG 1
+#define PVT_DBIAS_CMD2_OFFSET_FLAG_S 16
+#define PVT_DBIAS_CMD2_OFFSET_VALUE 0x1F
+#define PVT_DBIAS_CMD2_OFFSET_VALUE_S 11
+#define PVT_DBIAS_CMD2_PVT 0x7FF
+#define PVT_DBIAS_CMD2_PVT_S 0
+
+/** PVT_DBIAS_CMD3_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CMD3_REG (DR_REG_PVT_BASE + 0x5c)
+/** PVT_DBIAS_CMD3 : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CMD3    0x0001FFFFU
+#define PVT_DBIAS_CMD3_M  (PVT_DBIAS_CMD3_V << PVT_DBIAS_CMD3_S)
+#define PVT_DBIAS_CMD3_V  0x0001FFFFU
+#define PVT_DBIAS_CMD3_S  0
+
+/** PVT_DBIAS_CMD4_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CMD4_REG (DR_REG_PVT_BASE + 0x60)
+/** PVT_DBIAS_CMD4 : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CMD4    0x0001FFFFU
+#define PVT_DBIAS_CMD4_M  (PVT_DBIAS_CMD4_V << PVT_DBIAS_CMD4_S)
+#define PVT_DBIAS_CMD4_V  0x0001FFFFU
+#define PVT_DBIAS_CMD4_S  0
+
+/** PVT_DBIAS_TIMER_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_TIMER_REG (DR_REG_PVT_BASE + 0x64)
+/** PVT_TIMER_TARGET : R/W; bitpos: [30:15]; default: 65535;
+ *  needs field desc
+ */
+#define PVT_TIMER_TARGET    0x0000FFFFU
+#define PVT_TIMER_TARGET_M  (PVT_TIMER_TARGET_V << PVT_TIMER_TARGET_S)
+#define PVT_TIMER_TARGET_V  0x0000FFFFU
+#define PVT_TIMER_TARGET_S  15
+/** PVT_TIMER_EN : R/W; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMER_EN    (BIT(31))
+#define PVT_TIMER_EN_M  (PVT_TIMER_EN_V << PVT_TIMER_EN_S)
+#define PVT_TIMER_EN_V  0x00000001U
+#define PVT_TIMER_EN_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x68)
+/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_M  (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_M  (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_M  (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x6c)
+/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_M  (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_M  (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_M  (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x70)
+/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_M  (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_M  (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_M  (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x74)
+/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_M  (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_M  (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_M  (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x78)
+/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_M  (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_M  (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_M  (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x7c)
+/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_M  (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_M  (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_M  (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x80)
+/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_M  (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_M  (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_M  (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x84)
+/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_M  (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_M  (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_M  (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x88)
+/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_M  (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_M  (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_M  (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x8c)
+/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_M  (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_M  (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_M  (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x90)
+/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_M  (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_M  (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_M  (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x94)
+/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_M  (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_M  (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_M  (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x98)
+/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_M  (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_M  (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_M  (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x9c)
+/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_M  (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_M  (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_M  (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xa0)
+/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_M  (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_M  (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_M  (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xa4)
+/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_M  (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_M  (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_M  (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xa8)
+/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_M  (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_M  (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_M  (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xac)
+/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_M  (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_M  (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_M  (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xb0)
+/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_M  (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_M  (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_M  (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xb4)
+/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_M  (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_M  (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_M  (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xb8)
+/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_M  (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_M  (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_M  (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xbc)
+/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_M  (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_M  (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_M  (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xc0)
+/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_M  (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_M  (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_M  (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xc4)
+/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_M  (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_M  (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_M  (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xc8)
+/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_M  (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_M  (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_M  (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xcc)
+/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_M  (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_M  (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_M  (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xd0)
+/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_M  (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_M  (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_M  (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xd4)
+/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_M  (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_M  (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_M  (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xd8)
+/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_M  (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_M  (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_M  (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xdc)
+/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_M  (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_M  (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_M  (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xe0)
+/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_M  (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_M  (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_M  (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xe4)
+/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_M  (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_M  (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_M  (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xe8)
+/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_M  (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_M  (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_M  (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xec)
+/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_M  (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_M  (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_M  (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xf0)
+/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_M  (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_M  (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_M  (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xf4)
+/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_M  (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_M  (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_M  (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xf8)
+/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_M  (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_M  (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_M  (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_M  (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xfc)
+/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_M  (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_M  (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_M  (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_M  (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x100)
+/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_M  (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_M  (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_M  (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_M  (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x104)
+/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_M  (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_M  (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_M  (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_M  (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x108)
+/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_M  (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_M  (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_M  (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_M  (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x10c)
+/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_M  (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_M  (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_M  (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_M  (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x110)
+/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_M  (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_M  (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_M  (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_M  (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x114)
+/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_M  (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_M  (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_M  (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_M  (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x118)
+/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_M  (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_M  (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_M  (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_M  (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x11c)
+/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_M  (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_M  (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_M  (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_M  (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x120)
+/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_M  (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_M  (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_M  (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_M  (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x124)
+/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_M  (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_M  (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_M  (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_M  (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x128)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_M  (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x12c)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_M  (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x130)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_M  (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x134)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_M  (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x138)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_M  (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x13c)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_M  (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x140)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_M  (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x144)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_M  (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x148)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_M  (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x14c)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_M  (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x150)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_M  (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x154)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_M  (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x158)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_M  (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x15c)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_M  (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x160)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_M  (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x164)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_M  (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x168)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_M  (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x16c)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_M  (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x170)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_M  (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x174)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_M  (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x178)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_M  (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x17c)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_M  (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x180)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_M  (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x184)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_M  (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x188)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_M  (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x18c)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_M  (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x190)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_M  (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x194)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_M  (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x198)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_M  (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x19c)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_M  (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1a0)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_M  (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1a4)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_M  (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1a8)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_M  (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1ac)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_M  (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1b0)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_M  (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1b4)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_M  (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1b8)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_M  (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1bc)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_M  (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1c0)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_M  (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1c4)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_M  (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1c8)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_M  (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1cc)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_M  (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1d0)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_M  (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1d4)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_M  (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1d8)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_M  (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1dc)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_M  (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1e0)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_M  (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1e4)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_M  (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_S  16
+
+/** PVT_VALUE_UPDATE_REG register
+ *  needs field desc
+ */
+#define PVT_VALUE_UPDATE_REG (DR_REG_PVT_BASE + 0x1e8)
+/** PVT_VALUE_UPDATE : WT; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_VALUE_UPDATE    (BIT(0))
+#define PVT_VALUE_UPDATE_M  (PVT_VALUE_UPDATE_V << PVT_VALUE_UPDATE_S)
+#define PVT_VALUE_UPDATE_V  0x00000001U
+#define PVT_VALUE_UPDATE_S  0
+/** PVT_VALUE_UPDATE_BYPASS : R/W; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_VALUE_UPDATE_BYPASS    (BIT(1))
+#define PVT_VALUE_UPDATE_BYPASS_M  (PVT_VALUE_UPDATE_BYPASS_V << PVT_VALUE_UPDATE_BYPASS_S)
+#define PVT_VALUE_UPDATE_BYPASS_V  0x00000001U
+#define PVT_VALUE_UPDATE_BYPASS_S  1
+
+/** PVT_BYPASS_CHAIN_REG register
+ *  needs field desc
+ */
+#define PVT_BYPASS_CHAIN_REG (DR_REG_PVT_BASE + 0x1ec)
+/** PVT_CLK_CHAIN_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  needs field desc
+ */
+#define PVT_CLK_CHAIN_EN    0xFFFFFFFFU
+#define PVT_CLK_CHAIN_EN_M  (PVT_CLK_CHAIN_EN_V << PVT_CLK_CHAIN_EN_S)
+#define PVT_CLK_CHAIN_EN_V  0xFFFFFFFFU
+#define PVT_CLK_CHAIN_EN_S  0
+
+/** PVT_DLY_NUM_REC0_REG register
+ *  needs field desc
+ */
+#define PVT_DLY_NUM_REC0_REG (DR_REG_PVT_BASE + 0x1f0)
+/** PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD : RO; bitpos: [7:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD    0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD_M  (PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD_V << PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD_S)
+#define PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD_S  0
+/** PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD : RO; bitpos: [15:8]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD    0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD_M  (PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD_V << PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD_S)
+#define PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD_S  8
+/** PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD : RO; bitpos: [23:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD    0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD_M  (PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD_V << PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD_S)
+#define PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD_S  16
+/** PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD : RO; bitpos: [31:24]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD    0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD_M  (PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD_V << PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD_S)
+#define PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD_S  24
+
+/** PVT_DLY_NUM_REC1_REG register
+ *  needs field desc
+ */
+#define PVT_DLY_NUM_REC1_REG (DR_REG_PVT_BASE + 0x1f4)
+/** PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD : RO; bitpos: [7:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD    0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD_M  (PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD_V << PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD_S)
+#define PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD_S  0
+/** PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD : RO; bitpos: [15:8]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD    0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD_M  (PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD_V << PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD_S)
+#define PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD_S  8
+/** PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD : RO; bitpos: [23:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD    0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD_M  (PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD_V << PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD_S)
+#define PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD_S  16
+/** PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD : RO; bitpos: [31:24]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD    0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD_M  (PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD_V << PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD_S)
+#define PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD_S  24
+
+/** PVT_DLY_NUM_REC2_REG register
+ *  needs field desc
+ */
+#define PVT_DLY_NUM_REC2_REG (DR_REG_PVT_BASE + 0x1f8)
+/** PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD : RO; bitpos: [7:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD    0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD_M  (PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD_V << PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD_S)
+#define PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD_S  0
+/** PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD : RO; bitpos: [15:8]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD    0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD_M  (PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD_V << PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD_S)
+#define PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD_S  8
+/** PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD : RO; bitpos: [23:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD    0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD_M  (PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD_V << PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD_S)
+#define PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD_S  16
+/** PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD : RO; bitpos: [31:24]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD    0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD_M  (PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD_V << PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD_S)
+#define PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD_S  24
+
+/** PVT_DLY_NUM_REC3_REG register
+ *  needs field desc
+ */
+#define PVT_DLY_NUM_REC3_REG (DR_REG_PVT_BASE + 0x1fc)
+/** PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD : RO; bitpos: [7:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD    0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD_M  (PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD_V << PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD_S)
+#define PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD_S  0
+/** PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD : RO; bitpos: [15:8]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD    0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD_M  (PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD_V << PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD_S)
+#define PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD_S  8
+/** PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD : RO; bitpos: [23:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD    0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD_M  (PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD_V << PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD_S)
+#define PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD_S  16
+/** PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD : RO; bitpos: [31:24]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD    0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD_M  (PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD_V << PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD_S)
+#define PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD_V  0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD_S  24
+
+/** PVT_DLY_NUM_REC4_REG register
+ *  needs field desc
+ */
+#define PVT_DLY_NUM_REC4_REG (DR_REG_PVT_BASE + 0x200)
+/** PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD : RO; bitpos: [7:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD    0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD_M  (PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD_V << PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD_S)
+#define PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD_S  0
+/** PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD : RO; bitpos: [15:8]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD    0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD_M  (PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD_V << PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD_S)
+#define PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD_S  8
+/** PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD : RO; bitpos: [23:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD    0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD_M  (PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD_V << PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD_S)
+#define PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD_S  16
+/** PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD : RO; bitpos: [31:24]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD    0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD_M  (PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD_V << PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD_S)
+#define PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD_S  24
+
+/** PVT_DLY_NUM_REC5_REG register
+ *  needs field desc
+ */
+#define PVT_DLY_NUM_REC5_REG (DR_REG_PVT_BASE + 0x204)
+/** PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD : RO; bitpos: [7:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD    0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD_M  (PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD_V << PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD_S)
+#define PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD_S  0
+/** PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD : RO; bitpos: [15:8]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD    0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD_M  (PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD_V << PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD_S)
+#define PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD_S  8
+/** PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD : RO; bitpos: [23:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD    0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD_M  (PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD_V << PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD_S)
+#define PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD_S  16
+/** PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD : RO; bitpos: [31:24]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD    0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD_M  (PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD_V << PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD_S)
+#define PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD_S  24
+
+/** PVT_DLY_NUM_REC6_REG register
+ *  needs field desc
+ */
+#define PVT_DLY_NUM_REC6_REG (DR_REG_PVT_BASE + 0x208)
+/** PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD : RO; bitpos: [7:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD    0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD_M  (PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD_V << PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD_S)
+#define PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD_S  0
+/** PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD : RO; bitpos: [15:8]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD    0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD_M  (PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD_V << PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD_S)
+#define PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD_S  8
+/** PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD : RO; bitpos: [23:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD    0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD_M  (PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD_V << PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD_S)
+#define PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD_S  16
+/** PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD : RO; bitpos: [31:24]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD    0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD_M  (PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD_V << PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD_S)
+#define PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD_S  24
+
+/** PVT_DLY_NUM_REC7_REG register
+ *  needs field desc
+ */
+#define PVT_DLY_NUM_REC7_REG (DR_REG_PVT_BASE + 0x20c)
+/** PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD : RO; bitpos: [7:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD    0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD_M  (PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD_V << PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD_S)
+#define PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD_S  0
+/** PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD : RO; bitpos: [15:8]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD    0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD_M  (PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD_V << PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD_S)
+#define PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD_S  8
+/** PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD : RO; bitpos: [23:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD    0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD_M  (PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD_V << PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD_S)
+#define PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD_S  16
+/** PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD : RO; bitpos: [31:24]; default: 0;
+ *  needs field desc
+ */
+#define PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD    0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD_M  (PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD_V << PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD_S)
+#define PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD_V  0x000000FFU
+#define PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD_S  24
+
+/** PVT_DLY_NUM_REC_CLR_REG register
+ *  needs field desc
+ */
+#define PVT_DLY_NUM_REC_CLR_REG (DR_REG_PVT_BASE + 0x210)
+/** PVT_DELAY_NUM_REC_CLR : WT; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_REC_CLR    (BIT(0))
+#define PVT_DELAY_NUM_REC_CLR_M  (PVT_DELAY_NUM_REC_CLR_V << PVT_DELAY_NUM_REC_CLR_S)
+#define PVT_DELAY_NUM_REC_CLR_V  0x00000001U
+#define PVT_DELAY_NUM_REC_CLR_S  0
+
+/** PVT_DATE_REG register
+ *  version register
+ */
+#define PVT_DATE_REG (DR_REG_PVT_BASE + 0xffc)
+/** PVT_DATE : R/W; bitpos: [31:0]; default: 34677040;
+ *  version register
+ */
+#define PVT_DATE    0xFFFFFFFFU
+#define PVT_DATE_M  (PVT_DATE_V << PVT_DATE_S)
+#define PVT_DATE_V  0xFFFFFFFFU
+#define PVT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pvt_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pvt_struct.h
new file mode 100644
index 0000000000..ffeeb40341
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/pvt_struct.h
@@ -0,0 +1,3340 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure register */
+/** Type of pmup_bitmap_high0 register
+ *  select valid pvt channel
+ */
+typedef union {
+    struct {
+        /** pump_bitmap_high0 : R/W; bitpos: [31:0]; default: 0;
+         *  select valid high channel0
+         */
+        uint32_t pump_bitmap_high0:32;
+    };
+    uint32_t val;
+} pvt_pmup_bitmap_high0_reg_t;
+
+/** Type of pmup_bitmap_high1 register
+ *  select valid pvt channel
+ */
+typedef union {
+    struct {
+        /** pump_bitmap_high1 : R/W; bitpos: [31:0]; default: 0;
+         *  select valid high channel1
+         */
+        uint32_t pump_bitmap_high1:32;
+    };
+    uint32_t val;
+} pvt_pmup_bitmap_high1_reg_t;
+
+/** Type of pmup_bitmap_high2 register
+ *  select valid pvt channel
+ */
+typedef union {
+    struct {
+        /** pump_bitmap_high2 : R/W; bitpos: [31:0]; default: 0;
+         *  select valid high channel2
+         */
+        uint32_t pump_bitmap_high2:32;
+    };
+    uint32_t val;
+} pvt_pmup_bitmap_high2_reg_t;
+
+/** Type of pmup_bitmap_high3 register
+ *  select valid pvt channel
+ */
+typedef union {
+    struct {
+        /** pump_bitmap_high3 : R/W; bitpos: [31:0]; default: 0;
+         *  select valid high channel3
+         */
+        uint32_t pump_bitmap_high3:32;
+    };
+    uint32_t val;
+} pvt_pmup_bitmap_high3_reg_t;
+
+/** Type of pmup_bitmap_high4 register
+ *  select valid pvt channel
+ */
+typedef union {
+    struct {
+        /** pump_bitmap_high4 : R/W; bitpos: [31:0]; default: 0;
+         *  select valid high channel4
+         */
+        uint32_t pump_bitmap_high4:32;
+    };
+    uint32_t val;
+} pvt_pmup_bitmap_high4_reg_t;
+
+/** Type of pmup_bitmap_low0 register
+ *  select valid pvt channel
+ */
+typedef union {
+    struct {
+        /** pump_bitmap_low0 : R/W; bitpos: [31:0]; default: 0;
+         *  select valid low channel0
+         */
+        uint32_t pump_bitmap_low0:32;
+    };
+    uint32_t val;
+} pvt_pmup_bitmap_low0_reg_t;
+
+/** Type of pmup_bitmap_low1 register
+ *  select valid pvt channel
+ */
+typedef union {
+    struct {
+        /** pump_bitmap_low1 : R/W; bitpos: [31:0]; default: 0;
+         *  select valid low channel1
+         */
+        uint32_t pump_bitmap_low1:32;
+    };
+    uint32_t val;
+} pvt_pmup_bitmap_low1_reg_t;
+
+/** Type of pmup_bitmap_low2 register
+ *  select valid pvt channel
+ */
+typedef union {
+    struct {
+        /** pump_bitmap_low2 : R/W; bitpos: [31:0]; default: 0;
+         *  select valid low channel2
+         */
+        uint32_t pump_bitmap_low2:32;
+    };
+    uint32_t val;
+} pvt_pmup_bitmap_low2_reg_t;
+
+/** Type of pmup_bitmap_low3 register
+ *  select valid pvt channel
+ */
+typedef union {
+    struct {
+        /** pump_bitmap_low3 : R/W; bitpos: [31:0]; default: 0;
+         *  select valid low channel3
+         */
+        uint32_t pump_bitmap_low3:32;
+    };
+    uint32_t val;
+} pvt_pmup_bitmap_low3_reg_t;
+
+/** Type of pmup_bitmap_low4 register
+ *  select valid pvt channel
+ */
+typedef union {
+    struct {
+        /** pump_bitmap_low4 : R/W; bitpos: [31:0]; default: 0;
+         *  select valid low channel4
+         */
+        uint32_t pump_bitmap_low4:32;
+    };
+    uint32_t val;
+} pvt_pmup_bitmap_low4_reg_t;
+
+/** Type of pmup_drv_cfg register
+ *  configure pump drv
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** bypass_efuse_ctrl : R/W; bitpos: [8]; default: 1;
+         *  needs desc
+         */
+        uint32_t bypass_efuse_ctrl:1;
+        /** pump_en : R/W; bitpos: [9]; default: 0;
+         *  configure pvt charge xpd
+         */
+        uint32_t pump_en:1;
+        /** clk_en : R/W; bitpos: [10]; default: 0;
+         *  force register clken
+         */
+        uint32_t clk_en:1;
+        /** pump_drv4 : R/W; bitpos: [14:11]; default: 0;
+         *  configure cmd4 drv
+         */
+        uint32_t pump_drv4:4;
+        /** pump_drv3 : R/W; bitpos: [18:15]; default: 0;
+         *  configure cmd3 drv
+         */
+        uint32_t pump_drv3:4;
+        /** pump_drv2 : R/W; bitpos: [22:19]; default: 0;
+         *  configure cmd2 drv
+         */
+        uint32_t pump_drv2:4;
+        /** pump_drv1 : R/W; bitpos: [26:23]; default: 0;
+         *  configure cmd1 drv
+         */
+        uint32_t pump_drv1:4;
+        /** pump_drv0 : R/W; bitpos: [30:27]; default: 0;
+         *  configure cmd0 drv
+         */
+        uint32_t pump_drv0:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pvt_pmup_drv_cfg_reg_t;
+
+/** Type of pmup_channel_cfg register
+ *  configure the code of valid pump channel code
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:7;
+        /** pump_channel_code4 : R/W; bitpos: [11:7]; default: 0;
+         *  configure cmd4 code
+         */
+        uint32_t pump_channel_code4:5;
+        /** pump_channel_code3 : R/W; bitpos: [16:12]; default: 0;
+         *  configure cmd3 code
+         */
+        uint32_t pump_channel_code3:5;
+        /** pump_channel_code2 : R/W; bitpos: [21:17]; default: 0;
+         *  configure cmd2 code
+         */
+        uint32_t pump_channel_code2:5;
+        /** pump_channel_code1 : R/W; bitpos: [26:22]; default: 0;
+         *  configure cmd1 code
+         */
+        uint32_t pump_channel_code1:5;
+        /** pump_channel_code0 : R/W; bitpos: [31:27]; default: 0;
+         *  configure cmd0 code
+         */
+        uint32_t pump_channel_code0:5;
+    };
+    uint32_t val;
+} pvt_pmup_channel_cfg_reg_t;
+
+/** Type of clk_cfg register
+ *  configure pvt clk
+ */
+typedef union {
+    struct {
+        /** pump_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t pump_clk_div_num:8;
+        /** monitor_clk_pvt_en : R/W; bitpos: [8]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_clk_pvt_en:1;
+        uint32_t reserved_9:22;
+        /** clk_sel : R/W; bitpos: [31]; default: 0;
+         *  select pvt clk
+         */
+        uint32_t clk_sel:1;
+    };
+    uint32_t val;
+} pvt_clk_cfg_reg_t;
+
+/** Type of dbias_channel_sel0 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** dbias_channel3_sel : R/W; bitpos: [10:4]; default: 64;
+         *  needs field desc
+         */
+        uint32_t dbias_channel3_sel:7;
+        /** dbias_channel2_sel : R/W; bitpos: [17:11]; default: 64;
+         *  needs field desc
+         */
+        uint32_t dbias_channel2_sel:7;
+        /** dbias_channel1_sel : R/W; bitpos: [24:18]; default: 64;
+         *  needs field desc
+         */
+        uint32_t dbias_channel1_sel:7;
+        /** dbias_channel0_sel : R/W; bitpos: [31:25]; default: 64;
+         *  needs field desc
+         */
+        uint32_t dbias_channel0_sel:7;
+    };
+    uint32_t val;
+} pvt_dbias_channel_sel0_reg_t;
+
+/** Type of dbias_channel_sel1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** dbias_channel4_sel : R/W; bitpos: [31:25]; default: 64;
+         *  needs field desc
+         */
+        uint32_t dbias_channel4_sel:7;
+    };
+    uint32_t val;
+} pvt_dbias_channel_sel1_reg_t;
+
+/** Type of dbias_channel0_sel register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** dbias_channel0_cfg : R/W; bitpos: [16:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t dbias_channel0_cfg:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pvt_dbias_channel0_sel_reg_t;
+
+/** Type of dbias_channel1_sel register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** dbias_channel1_cfg : R/W; bitpos: [16:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t dbias_channel1_cfg:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pvt_dbias_channel1_sel_reg_t;
+
+/** Type of dbias_channel2_sel register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** dbias_channel2_cfg : R/W; bitpos: [16:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t dbias_channel2_cfg:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pvt_dbias_channel2_sel_reg_t;
+
+/** Type of dbias_channel3_sel register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** dbias_channel3_cfg : R/W; bitpos: [16:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t dbias_channel3_cfg:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pvt_dbias_channel3_sel_reg_t;
+
+/** Type of dbias_channel4_sel register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** dbias_channel4_cfg : R/W; bitpos: [16:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t dbias_channel4_cfg:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pvt_dbias_channel4_sel_reg_t;
+
+/** Type of dbias_cmd0 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** dbias_cmd0 : R/W; bitpos: [16:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t dbias_cmd0:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pvt_dbias_cmd0_reg_t;
+
+/** Type of dbias_cmd1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** dbias_cmd1 : R/W; bitpos: [16:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t dbias_cmd1:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pvt_dbias_cmd1_reg_t;
+
+/** Type of dbias_cmd2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** dbias_cmd2 : R/W; bitpos: [16:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t dbias_cmd2:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pvt_dbias_cmd2_reg_t;
+
+/** Type of dbias_cmd3 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** dbias_cmd3 : R/W; bitpos: [16:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t dbias_cmd3:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pvt_dbias_cmd3_reg_t;
+
+/** Type of dbias_cmd4 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** dbias_cmd4 : R/W; bitpos: [16:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t dbias_cmd4:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pvt_dbias_cmd4_reg_t;
+
+/** Type of dbias_timer register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:15;
+        /** timer_target : R/W; bitpos: [30:15]; default: 65535;
+         *  needs field desc
+         */
+        uint32_t timer_target:16;
+        /** timer_en : R/W; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timer_en:1;
+    };
+    uint32_t val;
+} pvt_dbias_timer_reg_t;
+
+/** Type of comb_pd_site0_unit0_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site0_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site0_unit0:1;
+        /** timing_err_cnt_clr_vt0_pd_site0_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site0_unit0:1;
+        /** delay_limit_vt0_pd_site0_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site0_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site0_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site0_unit0:8;
+        /** timing_err_vt0_pd_site0_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site0_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit0_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit1_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site0_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site0_unit1:1;
+        /** timing_err_cnt_clr_vt0_pd_site0_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site0_unit1:1;
+        /** delay_limit_vt0_pd_site0_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site0_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site0_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site0_unit1:8;
+        /** timing_err_vt0_pd_site0_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site0_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit1_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit2_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site0_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site0_unit2:1;
+        /** timing_err_cnt_clr_vt0_pd_site0_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site0_unit2:1;
+        /** delay_limit_vt0_pd_site0_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site0_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site0_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site0_unit2:8;
+        /** timing_err_vt0_pd_site0_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site0_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit2_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit3_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site0_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site0_unit3:1;
+        /** timing_err_cnt_clr_vt0_pd_site0_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site0_unit3:1;
+        /** delay_limit_vt0_pd_site0_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site0_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site0_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site0_unit3:8;
+        /** timing_err_vt0_pd_site0_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site0_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit3_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit0_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site0_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site0_unit0:1;
+        /** timing_err_cnt_clr_vt1_pd_site0_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site0_unit0:1;
+        /** delay_limit_vt1_pd_site0_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site0_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site0_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site0_unit0:8;
+        /** timing_err_vt1_pd_site0_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site0_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit0_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit1_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site0_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site0_unit1:1;
+        /** timing_err_cnt_clr_vt1_pd_site0_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site0_unit1:1;
+        /** delay_limit_vt1_pd_site0_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site0_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site0_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site0_unit1:8;
+        /** timing_err_vt1_pd_site0_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site0_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit1_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit2_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site0_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site0_unit2:1;
+        /** timing_err_cnt_clr_vt1_pd_site0_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site0_unit2:1;
+        /** delay_limit_vt1_pd_site0_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site0_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site0_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site0_unit2:8;
+        /** timing_err_vt1_pd_site0_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site0_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit2_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit3_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site0_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site0_unit3:1;
+        /** timing_err_cnt_clr_vt1_pd_site0_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site0_unit3:1;
+        /** delay_limit_vt1_pd_site0_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site0_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site0_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site0_unit3:8;
+        /** timing_err_vt1_pd_site0_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site0_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit3_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit0_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site0_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site0_unit0:1;
+        /** timing_err_cnt_clr_vt2_pd_site0_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site0_unit0:1;
+        /** delay_limit_vt2_pd_site0_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site0_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site0_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site0_unit0:8;
+        /** timing_err_vt2_pd_site0_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site0_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit0_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit1_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site0_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site0_unit1:1;
+        /** timing_err_cnt_clr_vt2_pd_site0_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site0_unit1:1;
+        /** delay_limit_vt2_pd_site0_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site0_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site0_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site0_unit1:8;
+        /** timing_err_vt2_pd_site0_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site0_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit1_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit2_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site0_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site0_unit2:1;
+        /** timing_err_cnt_clr_vt2_pd_site0_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site0_unit2:1;
+        /** delay_limit_vt2_pd_site0_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site0_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site0_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site0_unit2:8;
+        /** timing_err_vt2_pd_site0_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site0_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit2_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit3_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site0_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site0_unit3:1;
+        /** timing_err_cnt_clr_vt2_pd_site0_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site0_unit3:1;
+        /** delay_limit_vt2_pd_site0_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site0_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site0_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site0_unit3:8;
+        /** timing_err_vt2_pd_site0_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site0_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit3_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit0_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site1_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site1_unit0:1;
+        /** timing_err_cnt_clr_vt0_pd_site1_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site1_unit0:1;
+        /** delay_limit_vt0_pd_site1_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site1_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site1_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site1_unit0:8;
+        /** timing_err_vt0_pd_site1_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site1_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit0_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit1_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site1_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site1_unit1:1;
+        /** timing_err_cnt_clr_vt0_pd_site1_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site1_unit1:1;
+        /** delay_limit_vt0_pd_site1_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site1_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site1_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site1_unit1:8;
+        /** timing_err_vt0_pd_site1_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site1_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit1_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit2_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site1_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site1_unit2:1;
+        /** timing_err_cnt_clr_vt0_pd_site1_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site1_unit2:1;
+        /** delay_limit_vt0_pd_site1_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site1_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site1_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site1_unit2:8;
+        /** timing_err_vt0_pd_site1_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site1_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit2_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit3_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site1_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site1_unit3:1;
+        /** timing_err_cnt_clr_vt0_pd_site1_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site1_unit3:1;
+        /** delay_limit_vt0_pd_site1_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site1_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site1_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site1_unit3:8;
+        /** timing_err_vt0_pd_site1_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site1_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit3_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit0_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site1_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site1_unit0:1;
+        /** timing_err_cnt_clr_vt1_pd_site1_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site1_unit0:1;
+        /** delay_limit_vt1_pd_site1_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site1_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site1_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site1_unit0:8;
+        /** timing_err_vt1_pd_site1_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site1_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit0_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit1_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site1_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site1_unit1:1;
+        /** timing_err_cnt_clr_vt1_pd_site1_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site1_unit1:1;
+        /** delay_limit_vt1_pd_site1_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site1_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site1_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site1_unit1:8;
+        /** timing_err_vt1_pd_site1_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site1_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit1_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit2_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site1_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site1_unit2:1;
+        /** timing_err_cnt_clr_vt1_pd_site1_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site1_unit2:1;
+        /** delay_limit_vt1_pd_site1_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site1_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site1_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site1_unit2:8;
+        /** timing_err_vt1_pd_site1_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site1_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit2_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit3_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site1_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site1_unit3:1;
+        /** timing_err_cnt_clr_vt1_pd_site1_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site1_unit3:1;
+        /** delay_limit_vt1_pd_site1_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site1_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site1_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site1_unit3:8;
+        /** timing_err_vt1_pd_site1_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site1_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit3_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit0_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site1_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site1_unit0:1;
+        /** timing_err_cnt_clr_vt2_pd_site1_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site1_unit0:1;
+        /** delay_limit_vt2_pd_site1_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site1_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site1_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site1_unit0:8;
+        /** timing_err_vt2_pd_site1_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site1_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit0_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit1_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site1_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site1_unit1:1;
+        /** timing_err_cnt_clr_vt2_pd_site1_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site1_unit1:1;
+        /** delay_limit_vt2_pd_site1_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site1_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site1_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site1_unit1:8;
+        /** timing_err_vt2_pd_site1_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site1_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit1_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit2_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site1_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site1_unit2:1;
+        /** timing_err_cnt_clr_vt2_pd_site1_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site1_unit2:1;
+        /** delay_limit_vt2_pd_site1_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site1_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site1_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site1_unit2:8;
+        /** timing_err_vt2_pd_site1_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site1_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit2_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site1_unit3_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site1_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site1_unit3:1;
+        /** timing_err_cnt_clr_vt2_pd_site1_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site1_unit3:1;
+        /** delay_limit_vt2_pd_site1_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site1_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site1_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site1_unit3:8;
+        /** timing_err_vt2_pd_site1_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site1_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit3_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit0_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site2_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site2_unit0:1;
+        /** timing_err_cnt_clr_vt0_pd_site2_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site2_unit0:1;
+        /** delay_limit_vt0_pd_site2_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site2_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site2_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site2_unit0:8;
+        /** timing_err_vt0_pd_site2_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site2_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit0_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit1_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site2_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site2_unit1:1;
+        /** timing_err_cnt_clr_vt0_pd_site2_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site2_unit1:1;
+        /** delay_limit_vt0_pd_site2_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site2_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site2_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site2_unit1:8;
+        /** timing_err_vt0_pd_site2_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site2_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit1_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit2_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site2_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site2_unit2:1;
+        /** timing_err_cnt_clr_vt0_pd_site2_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site2_unit2:1;
+        /** delay_limit_vt0_pd_site2_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site2_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site2_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site2_unit2:8;
+        /** timing_err_vt0_pd_site2_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site2_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit2_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit3_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site2_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site2_unit3:1;
+        /** timing_err_cnt_clr_vt0_pd_site2_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site2_unit3:1;
+        /** delay_limit_vt0_pd_site2_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site2_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site2_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site2_unit3:8;
+        /** timing_err_vt0_pd_site2_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site2_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit3_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit0_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site2_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site2_unit0:1;
+        /** timing_err_cnt_clr_vt1_pd_site2_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site2_unit0:1;
+        /** delay_limit_vt1_pd_site2_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site2_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site2_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site2_unit0:8;
+        /** timing_err_vt1_pd_site2_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site2_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit0_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit1_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site2_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site2_unit1:1;
+        /** timing_err_cnt_clr_vt1_pd_site2_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site2_unit1:1;
+        /** delay_limit_vt1_pd_site2_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site2_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site2_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site2_unit1:8;
+        /** timing_err_vt1_pd_site2_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site2_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit1_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit2_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site2_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site2_unit2:1;
+        /** timing_err_cnt_clr_vt1_pd_site2_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site2_unit2:1;
+        /** delay_limit_vt1_pd_site2_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site2_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site2_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site2_unit2:8;
+        /** timing_err_vt1_pd_site2_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site2_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit2_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit3_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site2_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site2_unit3:1;
+        /** timing_err_cnt_clr_vt1_pd_site2_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site2_unit3:1;
+        /** delay_limit_vt1_pd_site2_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site2_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site2_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site2_unit3:8;
+        /** timing_err_vt1_pd_site2_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site2_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit3_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit0_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site2_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site2_unit0:1;
+        /** timing_err_cnt_clr_vt2_pd_site2_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site2_unit0:1;
+        /** delay_limit_vt2_pd_site2_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site2_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site2_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site2_unit0:8;
+        /** timing_err_vt2_pd_site2_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site2_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit0_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit1_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site2_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site2_unit1:1;
+        /** timing_err_cnt_clr_vt2_pd_site2_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site2_unit1:1;
+        /** delay_limit_vt2_pd_site2_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site2_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site2_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site2_unit1:8;
+        /** timing_err_vt2_pd_site2_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site2_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit1_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit2_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site2_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site2_unit2:1;
+        /** timing_err_cnt_clr_vt2_pd_site2_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site2_unit2:1;
+        /** delay_limit_vt2_pd_site2_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site2_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site2_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site2_unit2:8;
+        /** timing_err_vt2_pd_site2_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site2_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit2_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site2_unit3_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site2_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site2_unit3:1;
+        /** timing_err_cnt_clr_vt2_pd_site2_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site2_unit3:1;
+        /** delay_limit_vt2_pd_site2_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site2_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site2_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site2_unit3:8;
+        /** timing_err_vt2_pd_site2_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site2_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit3_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit0_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site3_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site3_unit0:1;
+        /** timing_err_cnt_clr_vt0_pd_site3_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site3_unit0:1;
+        /** delay_limit_vt0_pd_site3_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site3_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site3_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site3_unit0:8;
+        /** timing_err_vt0_pd_site3_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site3_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit0_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit1_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site3_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site3_unit1:1;
+        /** timing_err_cnt_clr_vt0_pd_site3_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site3_unit1:1;
+        /** delay_limit_vt0_pd_site3_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site3_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site3_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site3_unit1:8;
+        /** timing_err_vt0_pd_site3_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site3_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit1_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit2_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site3_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site3_unit2:1;
+        /** timing_err_cnt_clr_vt0_pd_site3_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site3_unit2:1;
+        /** delay_limit_vt0_pd_site3_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site3_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site3_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site3_unit2:8;
+        /** timing_err_vt0_pd_site3_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site3_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit2_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit3_vt0_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt0_pd_site3_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt0_pd_site3_unit3:1;
+        /** timing_err_cnt_clr_vt0_pd_site3_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt0_pd_site3_unit3:1;
+        /** delay_limit_vt0_pd_site3_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt0_pd_site3_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt0_pd_site3_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt0_pd_site3_unit3:8;
+        /** timing_err_vt0_pd_site3_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt0_pd_site3_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit3_vt0_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit0_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site3_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site3_unit0:1;
+        /** timing_err_cnt_clr_vt1_pd_site3_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site3_unit0:1;
+        /** delay_limit_vt1_pd_site3_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site3_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site3_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site3_unit0:8;
+        /** timing_err_vt1_pd_site3_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site3_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit0_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit1_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site3_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site3_unit1:1;
+        /** timing_err_cnt_clr_vt1_pd_site3_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site3_unit1:1;
+        /** delay_limit_vt1_pd_site3_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site3_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site3_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site3_unit1:8;
+        /** timing_err_vt1_pd_site3_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site3_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit1_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit2_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site3_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site3_unit2:1;
+        /** timing_err_cnt_clr_vt1_pd_site3_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site3_unit2:1;
+        /** delay_limit_vt1_pd_site3_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site3_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site3_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site3_unit2:8;
+        /** timing_err_vt1_pd_site3_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site3_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit2_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit3_vt1_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt1_pd_site3_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt1_pd_site3_unit3:1;
+        /** timing_err_cnt_clr_vt1_pd_site3_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt1_pd_site3_unit3:1;
+        /** delay_limit_vt1_pd_site3_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt1_pd_site3_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt1_pd_site3_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt1_pd_site3_unit3:8;
+        /** timing_err_vt1_pd_site3_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt1_pd_site3_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit3_vt1_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit0_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site3_unit0 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site3_unit0:1;
+        /** timing_err_cnt_clr_vt2_pd_site3_unit0 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site3_unit0:1;
+        /** delay_limit_vt2_pd_site3_unit0 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site3_unit0:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site3_unit0 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site3_unit0:8;
+        /** timing_err_vt2_pd_site3_unit0 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site3_unit0:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit0_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit1_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site3_unit1 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site3_unit1:1;
+        /** timing_err_cnt_clr_vt2_pd_site3_unit1 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site3_unit1:1;
+        /** delay_limit_vt2_pd_site3_unit1 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site3_unit1:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site3_unit1 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site3_unit1:8;
+        /** timing_err_vt2_pd_site3_unit1 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site3_unit1:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit1_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit2_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site3_unit2 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site3_unit2:1;
+        /** timing_err_cnt_clr_vt2_pd_site3_unit2 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site3_unit2:1;
+        /** delay_limit_vt2_pd_site3_unit2 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site3_unit2:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site3_unit2 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site3_unit2:8;
+        /** timing_err_vt2_pd_site3_unit2 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site3_unit2:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit2_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site3_unit3_vt2_conf1 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_en_vt2_pd_site3_unit3 : R/W; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_en_vt2_pd_site3_unit3:1;
+        /** timing_err_cnt_clr_vt2_pd_site3_unit3 : WT; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_clr_vt2_pd_site3_unit3:1;
+        /** delay_limit_vt2_pd_site3_unit3 : R/W; bitpos: [9:2]; default: 20;
+         *  needs field desc
+         */
+        uint32_t delay_limit_vt2_pd_site3_unit3:8;
+        uint32_t reserved_10:13;
+        /** delay_num_o_vt2_pd_site3_unit3 : RO; bitpos: [30:23]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_o_vt2_pd_site3_unit3:8;
+        /** timing_err_vt2_pd_site3_unit3 : RO; bitpos: [31]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_vt2_pd_site3_unit3:1;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit3_vt2_conf1_reg_t;
+
+/** Type of comb_pd_site0_unit0_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site0_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site0_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site0_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site0_unit0:1;
+        /** timing_err_cnt_o_vt0_pd_site0_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site0_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit0_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit1_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site0_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site0_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site0_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site0_unit1:1;
+        /** timing_err_cnt_o_vt0_pd_site0_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site0_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit1_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit2_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site0_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site0_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site0_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site0_unit2:1;
+        /** timing_err_cnt_o_vt0_pd_site0_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site0_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit2_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit3_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site0_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site0_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site0_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site0_unit3:1;
+        /** timing_err_cnt_o_vt0_pd_site0_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site0_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit3_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit0_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site0_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site0_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site0_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site0_unit0:1;
+        /** timing_err_cnt_o_vt1_pd_site0_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site0_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit0_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit1_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site0_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site0_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site0_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site0_unit1:1;
+        /** timing_err_cnt_o_vt1_pd_site0_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site0_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit1_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit2_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site0_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site0_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site0_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site0_unit2:1;
+        /** timing_err_cnt_o_vt1_pd_site0_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site0_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit2_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit3_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site0_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site0_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site0_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site0_unit3:1;
+        /** timing_err_cnt_o_vt1_pd_site0_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site0_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit3_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit0_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site0_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site0_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site0_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site0_unit0:1;
+        /** timing_err_cnt_o_vt2_pd_site0_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site0_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit0_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit1_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site0_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site0_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site0_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site0_unit1:1;
+        /** timing_err_cnt_o_vt2_pd_site0_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site0_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit1_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit2_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site0_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site0_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site0_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site0_unit2:1;
+        /** timing_err_cnt_o_vt2_pd_site0_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site0_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit2_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site0_unit3_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site0_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site0_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site0_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site0_unit3:1;
+        /** timing_err_cnt_o_vt2_pd_site0_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site0_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site0_unit3_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit0_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site1_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site1_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site1_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site1_unit0:1;
+        /** timing_err_cnt_o_vt0_pd_site1_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site1_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit0_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit1_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site1_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site1_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site1_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site1_unit1:1;
+        /** timing_err_cnt_o_vt0_pd_site1_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site1_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit1_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit2_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site1_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site1_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site1_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site1_unit2:1;
+        /** timing_err_cnt_o_vt0_pd_site1_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site1_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit2_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit3_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site1_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site1_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site1_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site1_unit3:1;
+        /** timing_err_cnt_o_vt0_pd_site1_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site1_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit3_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit0_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site1_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site1_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site1_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site1_unit0:1;
+        /** timing_err_cnt_o_vt1_pd_site1_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site1_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit0_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit1_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site1_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site1_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site1_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site1_unit1:1;
+        /** timing_err_cnt_o_vt1_pd_site1_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site1_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit1_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit2_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site1_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site1_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site1_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site1_unit2:1;
+        /** timing_err_cnt_o_vt1_pd_site1_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site1_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit2_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit3_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site1_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site1_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site1_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site1_unit3:1;
+        /** timing_err_cnt_o_vt1_pd_site1_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site1_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit3_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit0_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site1_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site1_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site1_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site1_unit0:1;
+        /** timing_err_cnt_o_vt2_pd_site1_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site1_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit0_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit1_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site1_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site1_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site1_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site1_unit1:1;
+        /** timing_err_cnt_o_vt2_pd_site1_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site1_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit1_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit2_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site1_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site1_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site1_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site1_unit2:1;
+        /** timing_err_cnt_o_vt2_pd_site1_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site1_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit2_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site1_unit3_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site1_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site1_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site1_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site1_unit3:1;
+        /** timing_err_cnt_o_vt2_pd_site1_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site1_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site1_unit3_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit0_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site2_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site2_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site2_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site2_unit0:1;
+        /** timing_err_cnt_o_vt0_pd_site2_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site2_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit0_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit1_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site2_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site2_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site2_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site2_unit1:1;
+        /** timing_err_cnt_o_vt0_pd_site2_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site2_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit1_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit2_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site2_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site2_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site2_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site2_unit2:1;
+        /** timing_err_cnt_o_vt0_pd_site2_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site2_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit2_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit3_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site2_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site2_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site2_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site2_unit3:1;
+        /** timing_err_cnt_o_vt0_pd_site2_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site2_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit3_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit0_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site2_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site2_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site2_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site2_unit0:1;
+        /** timing_err_cnt_o_vt1_pd_site2_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site2_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit0_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit1_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site2_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site2_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site2_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site2_unit1:1;
+        /** timing_err_cnt_o_vt1_pd_site2_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site2_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit1_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit2_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site2_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site2_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site2_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site2_unit2:1;
+        /** timing_err_cnt_o_vt1_pd_site2_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site2_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit2_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit3_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site2_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site2_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site2_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site2_unit3:1;
+        /** timing_err_cnt_o_vt1_pd_site2_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site2_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit3_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit0_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site2_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site2_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site2_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site2_unit0:1;
+        /** timing_err_cnt_o_vt2_pd_site2_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site2_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit0_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit1_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site2_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site2_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site2_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site2_unit1:1;
+        /** timing_err_cnt_o_vt2_pd_site2_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site2_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit1_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit2_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site2_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site2_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site2_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site2_unit2:1;
+        /** timing_err_cnt_o_vt2_pd_site2_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site2_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit2_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site2_unit3_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site2_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site2_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site2_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site2_unit3:1;
+        /** timing_err_cnt_o_vt2_pd_site2_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site2_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site2_unit3_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit0_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site3_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site3_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site3_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site3_unit0:1;
+        /** timing_err_cnt_o_vt0_pd_site3_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site3_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit0_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit1_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site3_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site3_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site3_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site3_unit1:1;
+        /** timing_err_cnt_o_vt0_pd_site3_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site3_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit1_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit2_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site3_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site3_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site3_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site3_unit2:1;
+        /** timing_err_cnt_o_vt0_pd_site3_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site3_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit2_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit3_vt0_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt0_pd_site3_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt0_pd_site3_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt0_pd_site3_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt0_pd_site3_unit3:1;
+        /** timing_err_cnt_o_vt0_pd_site3_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt0_pd_site3_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit3_vt0_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit0_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site3_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site3_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site3_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site3_unit0:1;
+        /** timing_err_cnt_o_vt1_pd_site3_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site3_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit0_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit1_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site3_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site3_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site3_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site3_unit1:1;
+        /** timing_err_cnt_o_vt1_pd_site3_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site3_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit1_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit2_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site3_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site3_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site3_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site3_unit2:1;
+        /** timing_err_cnt_o_vt1_pd_site3_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site3_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit2_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit3_vt1_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt1_pd_site3_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt1_pd_site3_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt1_pd_site3_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt1_pd_site3_unit3:1;
+        /** timing_err_cnt_o_vt1_pd_site3_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt1_pd_site3_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit3_vt1_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit0_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site3_unit0 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site3_unit0:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site3_unit0 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site3_unit0:1;
+        /** timing_err_cnt_o_vt2_pd_site3_unit0 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site3_unit0:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit0_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit1_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site3_unit1 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site3_unit1:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site3_unit1 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site3_unit1:1;
+        /** timing_err_cnt_o_vt2_pd_site3_unit1 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site3_unit1:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit1_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit2_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site3_unit2 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site3_unit2:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site3_unit2 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site3_unit2:1;
+        /** timing_err_cnt_o_vt2_pd_site3_unit2 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site3_unit2:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit2_vt2_conf2_reg_t;
+
+/** Type of comb_pd_site3_unit3_vt2_conf2 register
+ *  needs desc
+ */
+typedef union {
+    struct {
+        /** monitor_edg_mod_vt2_pd_site3_unit3 : R/W; bitpos: [1:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t monitor_edg_mod_vt2_pd_site3_unit3:2;
+        uint32_t reserved_2:13;
+        /** delay_ovf_vt2_pd_site3_unit3 : RO; bitpos: [15]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_ovf_vt2_pd_site3_unit3:1;
+        /** timing_err_cnt_o_vt2_pd_site3_unit3 : RO; bitpos: [31:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t timing_err_cnt_o_vt2_pd_site3_unit3:16;
+    };
+    uint32_t val;
+} pvt_comb_pd_site3_unit3_vt2_conf2_reg_t;
+
+/** Type of value_update register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** value_update : WT; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t value_update:1;
+        /** value_update_bypass : R/W; bitpos: [1]; default: 0;
+         *  needs field desc
+         */
+        uint32_t value_update_bypass:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pvt_value_update_reg_t;
+
+/** Type of bypass_chain register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** clk_chain_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  needs field desc
+         */
+        uint32_t clk_chain_en:32;
+    };
+    uint32_t val;
+} pvt_bypass_chain_reg_t;
+
+/** Type of dly_num_rec0 register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** site0_delay_num_vt0_max_record : RO; bitpos: [7:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site0_delay_num_vt0_max_record:8;
+        /** site0_delay_num_vt1_max_record : RO; bitpos: [15:8]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site0_delay_num_vt1_max_record:8;
+        /** site0_delay_num_vt2_max_record : RO; bitpos: [23:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site0_delay_num_vt2_max_record:8;
+        /** site0_delay_num_vt3_max_record : RO; bitpos: [31:24]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site0_delay_num_vt3_max_record:8;
+    };
+    uint32_t val;
+} pvt_dly_num_rec0_reg_t;
+
+/** Type of dly_num_rec1 register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** site1_delay_num_vt0_max_record : RO; bitpos: [7:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site1_delay_num_vt0_max_record:8;
+        /** site1_delay_num_vt1_max_record : RO; bitpos: [15:8]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site1_delay_num_vt1_max_record:8;
+        /** site1_delay_num_vt2_max_record : RO; bitpos: [23:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site1_delay_num_vt2_max_record:8;
+        /** site1_delay_num_vt3_max_record : RO; bitpos: [31:24]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site1_delay_num_vt3_max_record:8;
+    };
+    uint32_t val;
+} pvt_dly_num_rec1_reg_t;
+
+/** Type of dly_num_rec2 register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** site2_delay_num_vt0_max_record : RO; bitpos: [7:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site2_delay_num_vt0_max_record:8;
+        /** site2_delay_num_vt1_max_record : RO; bitpos: [15:8]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site2_delay_num_vt1_max_record:8;
+        /** site2_delay_num_vt2_max_record : RO; bitpos: [23:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site2_delay_num_vt2_max_record:8;
+        /** site2_delay_num_vt3_max_record : RO; bitpos: [31:24]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site2_delay_num_vt3_max_record:8;
+    };
+    uint32_t val;
+} pvt_dly_num_rec2_reg_t;
+
+/** Type of dly_num_rec3 register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** site3_delay_num_vt0_max_record : RO; bitpos: [7:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site3_delay_num_vt0_max_record:8;
+        /** site3_delay_num_vt1_max_record : RO; bitpos: [15:8]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site3_delay_num_vt1_max_record:8;
+        /** site3_delay_num_vt2_max_record : RO; bitpos: [23:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site3_delay_num_vt2_max_record:8;
+        /** site3_delay_num_vt3_max_record : RO; bitpos: [31:24]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site3_delay_num_vt3_max_record:8;
+    };
+    uint32_t val;
+} pvt_dly_num_rec3_reg_t;
+
+/** Type of dly_num_rec4 register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** site0_delay_num_vt0_min_record : RO; bitpos: [7:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site0_delay_num_vt0_min_record:8;
+        /** site0_delay_num_vt1_min_record : RO; bitpos: [15:8]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site0_delay_num_vt1_min_record:8;
+        /** site0_delay_num_vt2_min_record : RO; bitpos: [23:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site0_delay_num_vt2_min_record:8;
+        /** site0_delay_num_vt3_min_record : RO; bitpos: [31:24]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site0_delay_num_vt3_min_record:8;
+    };
+    uint32_t val;
+} pvt_dly_num_rec4_reg_t;
+
+/** Type of dly_num_rec5 register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** site1_delay_num_vt0_min_record : RO; bitpos: [7:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site1_delay_num_vt0_min_record:8;
+        /** site1_delay_num_vt1_min_record : RO; bitpos: [15:8]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site1_delay_num_vt1_min_record:8;
+        /** site1_delay_num_vt2_min_record : RO; bitpos: [23:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site1_delay_num_vt2_min_record:8;
+        /** site1_delay_num_vt3_min_record : RO; bitpos: [31:24]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site1_delay_num_vt3_min_record:8;
+    };
+    uint32_t val;
+} pvt_dly_num_rec5_reg_t;
+
+/** Type of dly_num_rec6 register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** site2_delay_num_vt0_min_record : RO; bitpos: [7:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site2_delay_num_vt0_min_record:8;
+        /** site2_delay_num_vt1_min_record : RO; bitpos: [15:8]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site2_delay_num_vt1_min_record:8;
+        /** site2_delay_num_vt2_min_record : RO; bitpos: [23:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site2_delay_num_vt2_min_record:8;
+        /** site2_delay_num_vt3_min_record : RO; bitpos: [31:24]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site2_delay_num_vt3_min_record:8;
+    };
+    uint32_t val;
+} pvt_dly_num_rec6_reg_t;
+
+/** Type of dly_num_rec7 register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** site3_delay_num_vt0_min_record : RO; bitpos: [7:0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site3_delay_num_vt0_min_record:8;
+        /** site3_delay_num_vt1_min_record : RO; bitpos: [15:8]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site3_delay_num_vt1_min_record:8;
+        /** site3_delay_num_vt2_min_record : RO; bitpos: [23:16]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site3_delay_num_vt2_min_record:8;
+        /** site3_delay_num_vt3_min_record : RO; bitpos: [31:24]; default: 0;
+         *  needs field desc
+         */
+        uint32_t site3_delay_num_vt3_min_record:8;
+    };
+    uint32_t val;
+} pvt_dly_num_rec7_reg_t;
+
+/** Type of dly_num_rec_clr register
+ *  needs field desc
+ */
+typedef union {
+    struct {
+        /** delay_num_rec_clr : WT; bitpos: [0]; default: 0;
+         *  needs field desc
+         */
+        uint32_t delay_num_rec_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} pvt_dly_num_rec_clr_reg_t;
+
+
+/** Group: version register */
+/** Type of date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 34677040;
+         *  version register
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} pvt_date_reg_t;
+
+
+typedef struct {
+    volatile pvt_pmup_bitmap_high0_reg_t pmup_bitmap_high0;
+    volatile pvt_pmup_bitmap_high1_reg_t pmup_bitmap_high1;
+    volatile pvt_pmup_bitmap_high2_reg_t pmup_bitmap_high2;
+    volatile pvt_pmup_bitmap_high3_reg_t pmup_bitmap_high3;
+    volatile pvt_pmup_bitmap_high4_reg_t pmup_bitmap_high4;
+    volatile pvt_pmup_bitmap_low0_reg_t pmup_bitmap_low0;
+    volatile pvt_pmup_bitmap_low1_reg_t pmup_bitmap_low1;
+    volatile pvt_pmup_bitmap_low2_reg_t pmup_bitmap_low2;
+    volatile pvt_pmup_bitmap_low3_reg_t pmup_bitmap_low3;
+    volatile pvt_pmup_bitmap_low4_reg_t pmup_bitmap_low4;
+    volatile pvt_pmup_drv_cfg_reg_t pmup_drv_cfg;
+    volatile pvt_pmup_channel_cfg_reg_t pmup_channel_cfg;
+    volatile pvt_clk_cfg_reg_t clk_cfg;
+    volatile pvt_dbias_channel_sel0_reg_t dbias_channel_sel0;
+    volatile pvt_dbias_channel_sel1_reg_t dbias_channel_sel1;
+    volatile pvt_dbias_channel0_sel_reg_t dbias_channel0_sel;
+    volatile pvt_dbias_channel1_sel_reg_t dbias_channel1_sel;
+    volatile pvt_dbias_channel2_sel_reg_t dbias_channel2_sel;
+    volatile pvt_dbias_channel3_sel_reg_t dbias_channel3_sel;
+    volatile pvt_dbias_channel4_sel_reg_t dbias_channel4_sel;
+    volatile pvt_dbias_cmd0_reg_t dbias_cmd0;
+    volatile pvt_dbias_cmd1_reg_t dbias_cmd1;
+    volatile pvt_dbias_cmd2_reg_t dbias_cmd2;
+    volatile pvt_dbias_cmd3_reg_t dbias_cmd3;
+    volatile pvt_dbias_cmd4_reg_t dbias_cmd4;
+    volatile pvt_dbias_timer_reg_t dbias_timer;
+    volatile pvt_comb_pd_site0_unit0_vt0_conf1_reg_t comb_pd_site0_unit0_vt0_conf1;
+    volatile pvt_comb_pd_site0_unit1_vt0_conf1_reg_t comb_pd_site0_unit1_vt0_conf1;
+    volatile pvt_comb_pd_site0_unit2_vt0_conf1_reg_t comb_pd_site0_unit2_vt0_conf1;
+    volatile pvt_comb_pd_site0_unit3_vt0_conf1_reg_t comb_pd_site0_unit3_vt0_conf1;
+    volatile pvt_comb_pd_site0_unit0_vt1_conf1_reg_t comb_pd_site0_unit0_vt1_conf1;
+    volatile pvt_comb_pd_site0_unit1_vt1_conf1_reg_t comb_pd_site0_unit1_vt1_conf1;
+    volatile pvt_comb_pd_site0_unit2_vt1_conf1_reg_t comb_pd_site0_unit2_vt1_conf1;
+    volatile pvt_comb_pd_site0_unit3_vt1_conf1_reg_t comb_pd_site0_unit3_vt1_conf1;
+    volatile pvt_comb_pd_site0_unit0_vt2_conf1_reg_t comb_pd_site0_unit0_vt2_conf1;
+    volatile pvt_comb_pd_site0_unit1_vt2_conf1_reg_t comb_pd_site0_unit1_vt2_conf1;
+    volatile pvt_comb_pd_site0_unit2_vt2_conf1_reg_t comb_pd_site0_unit2_vt2_conf1;
+    volatile pvt_comb_pd_site0_unit3_vt2_conf1_reg_t comb_pd_site0_unit3_vt2_conf1;
+    volatile pvt_comb_pd_site1_unit0_vt0_conf1_reg_t comb_pd_site1_unit0_vt0_conf1;
+    volatile pvt_comb_pd_site1_unit1_vt0_conf1_reg_t comb_pd_site1_unit1_vt0_conf1;
+    volatile pvt_comb_pd_site1_unit2_vt0_conf1_reg_t comb_pd_site1_unit2_vt0_conf1;
+    volatile pvt_comb_pd_site1_unit3_vt0_conf1_reg_t comb_pd_site1_unit3_vt0_conf1;
+    volatile pvt_comb_pd_site1_unit0_vt1_conf1_reg_t comb_pd_site1_unit0_vt1_conf1;
+    volatile pvt_comb_pd_site1_unit1_vt1_conf1_reg_t comb_pd_site1_unit1_vt1_conf1;
+    volatile pvt_comb_pd_site1_unit2_vt1_conf1_reg_t comb_pd_site1_unit2_vt1_conf1;
+    volatile pvt_comb_pd_site1_unit3_vt1_conf1_reg_t comb_pd_site1_unit3_vt1_conf1;
+    volatile pvt_comb_pd_site1_unit0_vt2_conf1_reg_t comb_pd_site1_unit0_vt2_conf1;
+    volatile pvt_comb_pd_site1_unit1_vt2_conf1_reg_t comb_pd_site1_unit1_vt2_conf1;
+    volatile pvt_comb_pd_site1_unit2_vt2_conf1_reg_t comb_pd_site1_unit2_vt2_conf1;
+    volatile pvt_comb_pd_site1_unit3_vt2_conf1_reg_t comb_pd_site1_unit3_vt2_conf1;
+    volatile pvt_comb_pd_site2_unit0_vt0_conf1_reg_t comb_pd_site2_unit0_vt0_conf1;
+    volatile pvt_comb_pd_site2_unit1_vt0_conf1_reg_t comb_pd_site2_unit1_vt0_conf1;
+    volatile pvt_comb_pd_site2_unit2_vt0_conf1_reg_t comb_pd_site2_unit2_vt0_conf1;
+    volatile pvt_comb_pd_site2_unit3_vt0_conf1_reg_t comb_pd_site2_unit3_vt0_conf1;
+    volatile pvt_comb_pd_site2_unit0_vt1_conf1_reg_t comb_pd_site2_unit0_vt1_conf1;
+    volatile pvt_comb_pd_site2_unit1_vt1_conf1_reg_t comb_pd_site2_unit1_vt1_conf1;
+    volatile pvt_comb_pd_site2_unit2_vt1_conf1_reg_t comb_pd_site2_unit2_vt1_conf1;
+    volatile pvt_comb_pd_site2_unit3_vt1_conf1_reg_t comb_pd_site2_unit3_vt1_conf1;
+    volatile pvt_comb_pd_site2_unit0_vt2_conf1_reg_t comb_pd_site2_unit0_vt2_conf1;
+    volatile pvt_comb_pd_site2_unit1_vt2_conf1_reg_t comb_pd_site2_unit1_vt2_conf1;
+    volatile pvt_comb_pd_site2_unit2_vt2_conf1_reg_t comb_pd_site2_unit2_vt2_conf1;
+    volatile pvt_comb_pd_site2_unit3_vt2_conf1_reg_t comb_pd_site2_unit3_vt2_conf1;
+    volatile pvt_comb_pd_site3_unit0_vt0_conf1_reg_t comb_pd_site3_unit0_vt0_conf1;
+    volatile pvt_comb_pd_site3_unit1_vt0_conf1_reg_t comb_pd_site3_unit1_vt0_conf1;
+    volatile pvt_comb_pd_site3_unit2_vt0_conf1_reg_t comb_pd_site3_unit2_vt0_conf1;
+    volatile pvt_comb_pd_site3_unit3_vt0_conf1_reg_t comb_pd_site3_unit3_vt0_conf1;
+    volatile pvt_comb_pd_site3_unit0_vt1_conf1_reg_t comb_pd_site3_unit0_vt1_conf1;
+    volatile pvt_comb_pd_site3_unit1_vt1_conf1_reg_t comb_pd_site3_unit1_vt1_conf1;
+    volatile pvt_comb_pd_site3_unit2_vt1_conf1_reg_t comb_pd_site3_unit2_vt1_conf1;
+    volatile pvt_comb_pd_site3_unit3_vt1_conf1_reg_t comb_pd_site3_unit3_vt1_conf1;
+    volatile pvt_comb_pd_site3_unit0_vt2_conf1_reg_t comb_pd_site3_unit0_vt2_conf1;
+    volatile pvt_comb_pd_site3_unit1_vt2_conf1_reg_t comb_pd_site3_unit1_vt2_conf1;
+    volatile pvt_comb_pd_site3_unit2_vt2_conf1_reg_t comb_pd_site3_unit2_vt2_conf1;
+    volatile pvt_comb_pd_site3_unit3_vt2_conf1_reg_t comb_pd_site3_unit3_vt2_conf1;
+    volatile pvt_comb_pd_site0_unit0_vt0_conf2_reg_t comb_pd_site0_unit0_vt0_conf2;
+    volatile pvt_comb_pd_site0_unit1_vt0_conf2_reg_t comb_pd_site0_unit1_vt0_conf2;
+    volatile pvt_comb_pd_site0_unit2_vt0_conf2_reg_t comb_pd_site0_unit2_vt0_conf2;
+    volatile pvt_comb_pd_site0_unit3_vt0_conf2_reg_t comb_pd_site0_unit3_vt0_conf2;
+    volatile pvt_comb_pd_site0_unit0_vt1_conf2_reg_t comb_pd_site0_unit0_vt1_conf2;
+    volatile pvt_comb_pd_site0_unit1_vt1_conf2_reg_t comb_pd_site0_unit1_vt1_conf2;
+    volatile pvt_comb_pd_site0_unit2_vt1_conf2_reg_t comb_pd_site0_unit2_vt1_conf2;
+    volatile pvt_comb_pd_site0_unit3_vt1_conf2_reg_t comb_pd_site0_unit3_vt1_conf2;
+    volatile pvt_comb_pd_site0_unit0_vt2_conf2_reg_t comb_pd_site0_unit0_vt2_conf2;
+    volatile pvt_comb_pd_site0_unit1_vt2_conf2_reg_t comb_pd_site0_unit1_vt2_conf2;
+    volatile pvt_comb_pd_site0_unit2_vt2_conf2_reg_t comb_pd_site0_unit2_vt2_conf2;
+    volatile pvt_comb_pd_site0_unit3_vt2_conf2_reg_t comb_pd_site0_unit3_vt2_conf2;
+    volatile pvt_comb_pd_site1_unit0_vt0_conf2_reg_t comb_pd_site1_unit0_vt0_conf2;
+    volatile pvt_comb_pd_site1_unit1_vt0_conf2_reg_t comb_pd_site1_unit1_vt0_conf2;
+    volatile pvt_comb_pd_site1_unit2_vt0_conf2_reg_t comb_pd_site1_unit2_vt0_conf2;
+    volatile pvt_comb_pd_site1_unit3_vt0_conf2_reg_t comb_pd_site1_unit3_vt0_conf2;
+    volatile pvt_comb_pd_site1_unit0_vt1_conf2_reg_t comb_pd_site1_unit0_vt1_conf2;
+    volatile pvt_comb_pd_site1_unit1_vt1_conf2_reg_t comb_pd_site1_unit1_vt1_conf2;
+    volatile pvt_comb_pd_site1_unit2_vt1_conf2_reg_t comb_pd_site1_unit2_vt1_conf2;
+    volatile pvt_comb_pd_site1_unit3_vt1_conf2_reg_t comb_pd_site1_unit3_vt1_conf2;
+    volatile pvt_comb_pd_site1_unit0_vt2_conf2_reg_t comb_pd_site1_unit0_vt2_conf2;
+    volatile pvt_comb_pd_site1_unit1_vt2_conf2_reg_t comb_pd_site1_unit1_vt2_conf2;
+    volatile pvt_comb_pd_site1_unit2_vt2_conf2_reg_t comb_pd_site1_unit2_vt2_conf2;
+    volatile pvt_comb_pd_site1_unit3_vt2_conf2_reg_t comb_pd_site1_unit3_vt2_conf2;
+    volatile pvt_comb_pd_site2_unit0_vt0_conf2_reg_t comb_pd_site2_unit0_vt0_conf2;
+    volatile pvt_comb_pd_site2_unit1_vt0_conf2_reg_t comb_pd_site2_unit1_vt0_conf2;
+    volatile pvt_comb_pd_site2_unit2_vt0_conf2_reg_t comb_pd_site2_unit2_vt0_conf2;
+    volatile pvt_comb_pd_site2_unit3_vt0_conf2_reg_t comb_pd_site2_unit3_vt0_conf2;
+    volatile pvt_comb_pd_site2_unit0_vt1_conf2_reg_t comb_pd_site2_unit0_vt1_conf2;
+    volatile pvt_comb_pd_site2_unit1_vt1_conf2_reg_t comb_pd_site2_unit1_vt1_conf2;
+    volatile pvt_comb_pd_site2_unit2_vt1_conf2_reg_t comb_pd_site2_unit2_vt1_conf2;
+    volatile pvt_comb_pd_site2_unit3_vt1_conf2_reg_t comb_pd_site2_unit3_vt1_conf2;
+    volatile pvt_comb_pd_site2_unit0_vt2_conf2_reg_t comb_pd_site2_unit0_vt2_conf2;
+    volatile pvt_comb_pd_site2_unit1_vt2_conf2_reg_t comb_pd_site2_unit1_vt2_conf2;
+    volatile pvt_comb_pd_site2_unit2_vt2_conf2_reg_t comb_pd_site2_unit2_vt2_conf2;
+    volatile pvt_comb_pd_site2_unit3_vt2_conf2_reg_t comb_pd_site2_unit3_vt2_conf2;
+    volatile pvt_comb_pd_site3_unit0_vt0_conf2_reg_t comb_pd_site3_unit0_vt0_conf2;
+    volatile pvt_comb_pd_site3_unit1_vt0_conf2_reg_t comb_pd_site3_unit1_vt0_conf2;
+    volatile pvt_comb_pd_site3_unit2_vt0_conf2_reg_t comb_pd_site3_unit2_vt0_conf2;
+    volatile pvt_comb_pd_site3_unit3_vt0_conf2_reg_t comb_pd_site3_unit3_vt0_conf2;
+    volatile pvt_comb_pd_site3_unit0_vt1_conf2_reg_t comb_pd_site3_unit0_vt1_conf2;
+    volatile pvt_comb_pd_site3_unit1_vt1_conf2_reg_t comb_pd_site3_unit1_vt1_conf2;
+    volatile pvt_comb_pd_site3_unit2_vt1_conf2_reg_t comb_pd_site3_unit2_vt1_conf2;
+    volatile pvt_comb_pd_site3_unit3_vt1_conf2_reg_t comb_pd_site3_unit3_vt1_conf2;
+    volatile pvt_comb_pd_site3_unit0_vt2_conf2_reg_t comb_pd_site3_unit0_vt2_conf2;
+    volatile pvt_comb_pd_site3_unit1_vt2_conf2_reg_t comb_pd_site3_unit1_vt2_conf2;
+    volatile pvt_comb_pd_site3_unit2_vt2_conf2_reg_t comb_pd_site3_unit2_vt2_conf2;
+    volatile pvt_comb_pd_site3_unit3_vt2_conf2_reg_t comb_pd_site3_unit3_vt2_conf2;
+    volatile pvt_value_update_reg_t value_update;
+    volatile pvt_bypass_chain_reg_t bypass_chain;
+    volatile pvt_dly_num_rec0_reg_t dly_num_rec0;
+    volatile pvt_dly_num_rec1_reg_t dly_num_rec1;
+    volatile pvt_dly_num_rec2_reg_t dly_num_rec2;
+    volatile pvt_dly_num_rec3_reg_t dly_num_rec3;
+    volatile pvt_dly_num_rec4_reg_t dly_num_rec4;
+    volatile pvt_dly_num_rec5_reg_t dly_num_rec5;
+    volatile pvt_dly_num_rec6_reg_t dly_num_rec6;
+    volatile pvt_dly_num_rec7_reg_t dly_num_rec7;
+    volatile pvt_dly_num_rec_clr_reg_t dly_num_rec_clr;
+    uint32_t reserved_214[890];
+    volatile pvt_date_reg_t date;
+} pvt_dev_t;
+
+extern pvt_dev_t PVT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pvt_dev_t) == 0x1000, "Invalid size of pvt_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h b/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h
new file mode 100644
index 0000000000..12e537ee3a
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h
@@ -0,0 +1,205 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Basic address */
+#define DR_REG_HPCPUTCP_BASE          0x3FF00000
+#define DR_REG_HPPERIPH0_BASE         0x50000000
+#define DR_REG_HPPERIPH1_BASE         0x500C0000
+#define DR_REG_LPAON_BASE             0x50110000
+#define DR_REG_LPPERIPH_BASE          0x50120000
+
+/* This is raw module base from digital team
+ * some of them may not be used in rom
+ * just keep them for a reference
+ */
+/*
+ * @module: CPU-PERIPHERAL
+ *
+ * @base: 0x3FF00000
+ *
+ * @size: 128KB
+ */
+#define DR_REG_TRACE0_BASE            (DR_REG_HPCPUTCP_BASE + 0x4000)
+#define DR_REG_TRACE1_BASE            (DR_REG_HPCPUTCP_BASE + 0x5000)
+#define DR_REG_CPU_BUS_MON_BASE       (DR_REG_HPCPUTCP_BASE + 0x6000)
+#define DR_REG_L2MEM_MON_BASE         (DR_REG_HPCPUTCP_BASE + 0xE000)
+#define DR_REG_TCM_MON_BASE           (DR_REG_HPCPUTCP_BASE + 0xF000)
+#define DR_REG_CACHE_BASE             (DR_REG_HPCPUTCP_BASE + 0x10000)
+
+/*
+ * @module: PERIPHERAL0
+ *
+ * @base: 0x50000000
+ *
+ * @size: 768KB
+ */
+#define DR_REG_USB2_BASE              (DR_REG_HPPERIPH0_BASE + 0x0)
+#define DR_REG_USB11_BASE             (DR_REG_HPPERIPH0_BASE + 0x40000)
+#define DR_REG_USB_WRAP_BASE          (DR_REG_HPPERIPH0_BASE + 0x80000)
+#define DR_REG_GDMA_BASE              (DR_REG_HPPERIPH0_BASE + 0x81000)
+#define DR_REG_REGDMA_BASE            (DR_REG_HPPERIPH0_BASE + 0x82000)
+#define DR_REG_SDMMC_BASE             (DR_REG_HPPERIPH0_BASE + 0x83000)
+#define DR_REG_H264_CORE_BASE         (DR_REG_HPPERIPH0_BASE + 0x84000)
+#define DR_REG_AHB_DMA_BASE           (DR_REG_HPPERIPH0_BASE + 0x85000)
+#define DR_REG_JPEG_BASE              (DR_REG_HPPERIPH0_BASE + 0x86000)
+#define DR_REG_PPA_BASE               (DR_REG_HPPERIPH0_BASE + 0x87000)
+#define DR_REG_DMA2D_BASE             (DR_REG_HPPERIPH0_BASE + 0x88000)
+#define DR_REG_KEYMNG_BASE            (DR_REG_HPPERIPH0_BASE + 0x89000)
+#define DR_REG_AXI_DMA_BASE           (DR_REG_HPPERIPH0_BASE + 0x8A000)
+#define DR_REG_FLASH_SPI0_BASE        (DR_REG_HPPERIPH0_BASE + 0x8C000)
+#define DR_REG_FLASH_SPI1_BASE        (DR_REG_HPPERIPH0_BASE + 0x8D000)
+#define DR_REG_PSRAM_MSPI0_BASE       (DR_REG_HPPERIPH0_BASE + 0x8E000)
+#define DR_REG_PSRAM_MSPI1_BASE       (DR_REG_HPPERIPH0_BASE + 0x8F000)
+#define DR_REG_CRYPTO_BASE            (DR_REG_HPPERIPH0_BASE + 0x90000)
+#define DR_REG_EMAC_BASE              (DR_REG_HPPERIPH0_BASE + 0x98000)
+#define DR_REG_USBPHY_BASE            (DR_REG_HPPERIPH0_BASE + 0x9C000)
+#define DR_REG_DDRPHY_BASE            (DR_REG_HPPERIPH0_BASE + 0x9D000)
+#define DR_REG_PVT_BASE               (DR_REG_HPPERIPH0_BASE + 0x9E000)
+#define DR_REG_CSI_HOST_BASE          (DR_REG_HPPERIPH0_BASE + 0x9F000)
+#define DR_REG_CSI_BRG_BASE           (DR_REG_HPPERIPH0_BASE + 0x9F800)
+#define DR_REG_DSI_HOST_BASE          (DR_REG_HPPERIPH0_BASE + 0xA0000)
+#define DR_REG_DSI_BRG_BASE           (DR_REG_HPPERIPH0_BASE + 0xA0800)
+#define DR_REG_ISP_BASE               (DR_REG_HPPERIPH0_BASE + 0xA1000)
+#define DR_REG_RMT_BASE               (DR_REG_HPPERIPH0_BASE + 0xA2000)
+#define DR_REG_BITSCRAMBLER_BASE      (DR_REG_HPPERIPH0_BASE + 0xA3000)
+#define DR_REG_AXI_ICM_BASE           (DR_REG_HPPERIPH0_BASE + 0xA4000)
+#define DR_REG_AXI_ICM_QOS_BASE       (DR_REG_AXI_ICM_BASE   + 0x400)
+#define DR_REG_HP_PERI_PMS_BASE       (DR_REG_HPPERIPH0_BASE + 0xA5000)
+#define DR_REG_LP2HP_PERI_PMS_BASE    (DR_REG_HPPERIPH0_BASE + 0xA5800)
+#define DR_REG_DMA_PMS_BASE           (DR_REG_HPPERIPH0_BASE + 0xA6000)
+#define DR_REG_H264_DMA_2D_BASE       (DR_REG_HPPERIPH0_BASE + 0xA7000)
+/*
+ * @module: PERIPHERAL1
+ *
+ * @base: 0x500C0000
+ *
+ * @size: 256KB
+ */
+#define DR_REG_MCPWM0_BASE            (DR_REG_HPPERIPH1_BASE + 0x0)
+#define DR_REG_MCPWM1_BASE            (DR_REG_HPPERIPH1_BASE + 0x1000)
+#define DR_REG_TIMG0_BASE             (DR_REG_HPPERIPH1_BASE + 0x2000)
+#define DR_REG_TIMG1_BASE             (DR_REG_HPPERIPH1_BASE + 0x3000)
+#define DR_REG_I2C0_BASE              (DR_REG_HPPERIPH1_BASE + 0x4000)
+#define DR_REG_I2C1_BASE              (DR_REG_HPPERIPH1_BASE + 0x5000)
+#define DR_REG_I2S0_BASE              (DR_REG_HPPERIPH1_BASE + 0x6000)
+#define DR_REG_I2S1_BASE              (DR_REG_HPPERIPH1_BASE + 0x7000)
+#define DR_REG_I2S2_BASE              (DR_REG_HPPERIPH1_BASE + 0x8000)
+#define DR_REG_PCNT_BASE              (DR_REG_HPPERIPH1_BASE + 0x9000)
+#define DR_REG_UART0_BASE             (DR_REG_HPPERIPH1_BASE + 0xA000)
+#define DR_REG_UART1_BASE             (DR_REG_HPPERIPH1_BASE + 0xB000)
+#define DR_REG_UART2_BASE             (DR_REG_HPPERIPH1_BASE + 0xC000)
+#define DR_REG_UART3_BASE             (DR_REG_HPPERIPH1_BASE + 0xD000)
+#define DR_REG_UART4_BASE             (DR_REG_HPPERIPH1_BASE + 0xE000)
+#define DR_REG_PARIO_BASE             (DR_REG_HPPERIPH1_BASE + 0xF000)
+#define DR_REG_SPI2_BASE              (DR_REG_HPPERIPH1_BASE + 0x10000)
+#define DR_REG_SPI3_BASE              (DR_REG_HPPERIPH1_BASE + 0x11000)
+#define DR_REG_USB2JTAG_BASE          (DR_REG_HPPERIPH1_BASE + 0x12000)
+#define DR_REG_LEDC_BASE              (DR_REG_HPPERIPH1_BASE + 0x13000)
+#define DR_REG_ETM_BASE               (DR_REG_HPPERIPH1_BASE + 0x15000)
+#define DR_REG_INTR_BASE              (DR_REG_HPPERIPH1_BASE + 0x16000)
+#define DR_REG_TWAI0_BASE             (DR_REG_HPPERIPH1_BASE + 0x17000)
+#define DR_REG_TWAI1_BASE             (DR_REG_HPPERIPH1_BASE + 0x18000)
+#define DR_REG_TWAI2_BASE             (DR_REG_HPPERIPH1_BASE + 0x19000)
+#define DR_REG_I3C_MST_BASE           (DR_REG_HPPERIPH1_BASE + 0x1A000)
+#define DR_REG_I3C_MST_MEM_BASE       (DR_REG_I3C_MST_BASE)
+#define DR_REG_I3C_SLV_BASE           (DR_REG_HPPERIPH1_BASE + 0x1B000)
+#define DR_REG_LCDCAM_BASE            (DR_REG_HPPERIPH1_BASE + 0x1C000)
+#define DR_REG_ADC_BASE               (DR_REG_HPPERIPH1_BASE + 0x1E000)
+#define DR_REG_UHCI_BASE              (DR_REG_HPPERIPH1_BASE + 0x1F000)
+#define DR_REG_GPIO_BASE              (DR_REG_HPPERIPH1_BASE + 0x20000)
+#define DR_REG_GPIO_EXT_BASE          (DR_REG_HPPERIPH1_BASE + 0x20F00)
+#define DR_REG_IO_MUX_BASE            (DR_REG_HPPERIPH1_BASE + 0x21000)
+#define DR_REG_IOMUX_MSPI_PIN_BASE    (DR_REG_HPPERIPH1_BASE + 0x21200)
+#define DR_REG_SYSTIMER_BASE          (DR_REG_HPPERIPH1_BASE + 0x22000)
+#define DR_REG_MEM_MON_BASE           (DR_REG_HPPERIPH1_BASE + 0x23000)
+#define DR_REG_AUDIO_ADDC_BASE        (DR_REG_HPPERIPH1_BASE + 0x24000)
+#define DR_REG_HP_SYS_BASE            (DR_REG_HPPERIPH1_BASE + 0x25000)
+#define DR_REG_HP_SYS_CLKRST_BASE     (DR_REG_HPPERIPH1_BASE + 0x26000)
+
+/*
+ * @module: LP AON
+ *
+ * @base: 0x50110000
+ *
+ * @size: 64KB
+ */
+#define DR_REG_LP_SYS_BASE            (DR_REG_LPAON_BASE + 0x0)
+#define DR_REG_LP_CLKRST_BASE         (DR_REG_LPAON_BASE + 0x1000)
+#define DR_REG_LP_TIMER_BASE          (DR_REG_LPAON_BASE + 0x2000)
+#define DR_REG_LP_ANALOG_PERI_BASE    (DR_REG_LPAON_BASE + 0x3000)
+#define DR_REG_LP_HUK_BASE            (DR_REG_LPAON_BASE + 0x4000)
+#define DR_REG_HUK_BASE               (DR_REG_LP_HUK_BASE)
+#define DR_REG_PMU_BASE               (DR_REG_LPAON_BASE + 0x5000)
+#define DR_REG_LP_WDT_BASE            (DR_REG_LPAON_BASE + 0x6000)
+#define DR_REG_LP_MB_BASE             (DR_REG_LPAON_BASE + 0x8000)
+#define DR_REG_RTC_BASE               (DR_REG_LPAON_BASE + 0x9000)
+
+/*
+ * @module: LP PERI
+ *
+ * @base: 0x50120000
+ *
+ * @size: 64KB
+ */
+#define DR_REG_LP_PERI_CLKRST_BASE    (DR_REG_LPPERIPH_BASE + 0x0)
+#define DR_REG_LP_PERI_BASE           (DR_REG_LPPERIPH_BASE + 0x0)
+#define DR_REG_LP_UART_BASE           (DR_REG_LPPERIPH_BASE + 0x1000)
+#define DR_REG_LP_I2C_BASE            (DR_REG_LPPERIPH_BASE + 0x2000)
+#define DR_REG_LP_SPI_BASE            (DR_REG_LPPERIPH_BASE + 0x3000)
+#define DR_REG_I2C_ANA_MST_BASE       (DR_REG_LPPERIPH_BASE + 0x4000)
+#define DR_REG_LP_I2S_BASE            (DR_REG_LPPERIPH_BASE + 0x5000)
+#define DR_REG_LP_ADC_BASE            (DR_REG_LPPERIPH_BASE + 0x7000)
+#define DR_REG_LP_TOUCH_BASE          (DR_REG_LPPERIPH_BASE + 0x8000)
+#define DR_REG_LP_GPIO_BASE           (DR_REG_LPPERIPH_BASE + 0xA000)
+#define DR_REG_LP_IOMUX_BASE          (DR_REG_LPPERIPH_BASE + 0xB000)
+#define DR_REG_LP_INTR_BASE           (DR_REG_LPPERIPH_BASE + 0xC000)
+#define DR_REG_EFUSE_BASE             (DR_REG_LPPERIPH_BASE + 0xD000)
+#define DR_REG_LP_PERI_PMS_BASE       (DR_REG_LPPERIPH_BASE + 0xE000)
+#define DR_REG_HP2LP_PERI_PMS_BASE    (DR_REG_LPPERIPH_BASE + 0xE800)
+#define DR_REG_LP_TSENSOR_BASE        (DR_REG_LPPERIPH_BASE + 0xF000)
+
+/**
+ * @brief: Special memory address
+ */
+#define LP_I2S_RAM_BASE               0x50125c00
+#define MIPI_CSI_BRG_MEM_BASE         0x50104000
+#define MIPI_DSI_BRG_MEM_BASE         0x50105000
+
+
+/**
+ * This are module helper MACROs for quick module reference
+ * including some module(renamed) address
+ */
+#define DR_REG_UART_BASE                        DR_REG_UART0_BASE
+#define DR_REG_UHCI0_BASE                       DR_REG_UHCI_BASE
+#define DR_REG_TIMERGROUP0_BASE                 DR_REG_TIMG0_BASE
+#define DR_REG_TIMERGROUP1_BASE                 DR_REG_TIMG1_BASE
+#define DR_REG_I2S_BASE                         DR_REG_I2S0_BASE
+#define DR_REG_USB_SERIAL_JTAG_BASE             DR_REG_USB2JTAG_BASE
+#define DR_REG_INTMTX_BASE                      DR_REG_INTR_BASE
+#define DR_REG_SOC_ETM_BASE                     DR_REG_ETM_BASE
+#define DR_REG_MCPWM_BASE                       DR_REG_MCPWM0_BASE
+#define DR_REG_PARL_IO_BASE                     DR_REG_PARIO_BASE
+#define DR_REG_PVT_MONITOR_BASE                 DR_REG_PVT_BASE
+#define DR_REG_AES_BASE                         (DR_REG_CRYPTO_BASE + 0x0)
+#define DR_REG_SHA_BASE                         (DR_REG_CRYPTO_BASE + 0x1000)
+#define DR_REG_RSA_BASE                         (DR_REG_CRYPTO_BASE + 0x2000)
+#define DR_REG_ECC_MULT_BASE                    (DR_REG_CRYPTO_BASE + 0x3000)
+#define DR_REG_DS_BASE                          (DR_REG_CRYPTO_BASE + 0x4000)
+#define DR_REG_DIGITAL_SIGNATURE_BASE           DR_REG_DS_BASE
+#define DR_REG_HMAC_BASE                        (DR_REG_CRYPTO_BASE + 0x5000)
+#define DR_REG_ECDSA_BASE                       (DR_REG_CRYPTO_BASE + 0x6000)
+#define DR_REG_MEM_MONITOR_BASE                 DR_REG_L2MEM_MON_BASE
+#define DR_REG_HP_CLKRST_BASE                   DR_REG_HP_SYS_CLKRST_BASE
+#define DR_REG_DSPI_MEM_BASE                    DR_REG_PSRAM_MSPI0_BASE
+#define DR_REG_INTERRUPT_CORE0_BASE             DR_REG_INTR_BASE
+#define DR_REG_INTERRUPT_CORE1_BASE             (DR_REG_INTR_BASE + 0x800)
+#define DR_REG_LPPERI_BASE                      DR_REG_LP_PERI_CLKRST_BASE
+#define DR_REG_CPU_BUS_MONITOR_BASE             DR_REG_CPU_BUS_MON_BASE
+#define DR_REG_ASSIST_DEBUG_BASE                DR_REG_CPU_BUS_MON_BASE
+#define DR_REG_PAU_BASE                         DR_REG_REGDMA_BASE
+#define DR_REG_SDHOST_BASE                      DR_REG_SDMMC_BASE
+#define DR_REG_TRACE_BASE                       DR_REG_TRACE0_BASE
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/rmt_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/rmt_eco5_struct.h
new file mode 100644
index 0000000000..bd665b84be
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/rmt_eco5_struct.h
@@ -0,0 +1,1077 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO R/W registers */
+/** Type of chndata register
+ *  The read and write  data register for CHANNELn by apb fifo access.
+ */
+typedef union {
+    struct {
+        /** chndata : HRO; bitpos: [31:0]; default: 0;
+         *  Read and write data for channel n via APB FIFO.
+         */
+        uint32_t chndata:32;
+    };
+    uint32_t val;
+} rmt_chndata_reg_t;
+
+/** Type of chmdata register
+ *  The read and write  data register for CHANNEL$n by apb fifo access.
+ */
+typedef union {
+    struct {
+        /** chmdata : HRO; bitpos: [31:0]; default: 0;
+         *  Read and write data for channel $n via APB FIFO.
+         */
+        uint32_t chmdata:32;
+    };
+    uint32_t val;
+} rmt_chmdata_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of chnconf0 register
+ *  Channel n configure register 0
+ */
+typedef union {
+    struct {
+        /** tx_start_chn : WT; bitpos: [0]; default: 0;
+         *  Set this bit to start sending data on CHANNELn.
+         */
+        uint32_t tx_start_chn:1;
+        /** mem_rd_rst_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset read ram address for CHANNELn by accessing transmitter.
+         */
+        uint32_t mem_rd_rst_chn:1;
+        /** apb_mem_rst_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo.
+         */
+        uint32_t apb_mem_rst_chn:1;
+        /** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to restart transmission  from the first data to the last data in
+         *  CHANNELn.
+         */
+        uint32_t tx_conti_mode_chn:1;
+        /** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0;
+         *  This is the channel n enable bit for wraparound mode: it will resume sending at the
+         *  start when the data to be sent is more than its memory size.
+         */
+        uint32_t mem_tx_wrap_en_chn:1;
+        /** idle_out_lv_chn : R/W; bitpos: [5]; default: 0;
+         *  This bit configures the level of output signal in CHANNELn when the latter is in
+         *  IDLE state.
+         */
+        uint32_t idle_out_lv_chn:1;
+        /** idle_out_en_chn : R/W; bitpos: [6]; default: 0;
+         *  This is the output enable-control bit for CHANNELn in IDLE state.
+         */
+        uint32_t idle_out_en_chn:1;
+        /** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0;
+         *  Set this bit to stop the transmitter of CHANNELn sending data out.
+         */
+        uint32_t tx_stop_chn:1;
+        /** div_cnt_chn : R/W; bitpos: [15:8]; default: 2;
+         *  This register is used to configure the divider for clock of CHANNELn.
+         */
+        uint32_t div_cnt_chn:8;
+        /** mem_size_chn : R/W; bitpos: [19:16]; default: 1;
+         *  This register is used to configure the maximum size of memory allocated to CHANNELn.
+         */
+        uint32_t mem_size_chn:4;
+        /** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1;
+         *  1: Add carrier modulation on the output signal only at the send data state for
+         *  CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn.
+         *  Only valid when RMT_CARRIER_EN_CHn is 1.
+         */
+        uint32_t carrier_eff_en_chn:1;
+        /** carrier_en_chn : R/W; bitpos: [21]; default: 1;
+         *  This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier
+         *  modulation in the output signal. 0: No carrier modulation in sig_out.
+         */
+        uint32_t carrier_en_chn:1;
+        /** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1;
+         *  This bit is used to configure the position of carrier wave for CHANNELn.1'h0: add
+         *  carrier wave on low level.1'h1: add carrier wave on high level.
+         */
+        uint32_t carrier_out_lv_chn:1;
+        uint32_t reserved_23:1;
+        /** conf_update_chn : WT; bitpos: [24]; default: 0;
+         *  synchronization bit for CHANNELn
+         */
+        uint32_t conf_update_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} rmt_chnconf0_reg_t;
+
+/** Type of chmconf0 register
+ *  Channel m configure register 0
+ */
+typedef union {
+    struct {
+        /** div_cnt_chm : R/W; bitpos: [7:0]; default: 2;
+         *  This register is used to configure the divider for clock of CHANNELm.
+         */
+        uint32_t div_cnt_chm:8;
+        /** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767;
+         *  When no edge is detected on the input signal and continuous clock cycles is longer
+         *  than this register value, received process is finished.
+         */
+        uint32_t idle_thres_chm:15;
+        uint32_t reserved_23:1;
+        /** mem_size_chm : R/W; bitpos: [27:24]; default: 1;
+         *  This register is used to configure the maximum size of memory allocated to CHANNELm.
+         */
+        uint32_t mem_size_chm:4;
+        /** carrier_en_chm : R/W; bitpos: [28]; default: 1;
+         *  This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier
+         *  modulation in the output signal. 0: No carrier modulation in sig_out.
+         */
+        uint32_t carrier_en_chm:1;
+        /** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1;
+         *  This bit is used to configure the position of carrier wave for CHANNELm.1'h0: add
+         *  carrier wave on low level.1'h1: add carrier wave on high level.
+         */
+        uint32_t carrier_out_lv_chm:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} rmt_chmconf0_reg_t;
+
+/** Type of chmconf1 register
+ *  Channel m configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_en_chm : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable receiver to receive data on CHANNELm.
+         */
+        uint32_t rx_en_chm:1;
+        /** mem_wr_rst_chm : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset write ram address for CHANNELm by accessing receiver.
+         */
+        uint32_t mem_wr_rst_chm:1;
+        /** apb_mem_rst_chm : WT; bitpos: [2]; default: 0;
+         *  Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo.
+         */
+        uint32_t apb_mem_rst_chm:1;
+        /** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1;
+         *  This register marks the ownership of CHANNELm's ram block.1'h1: Receiver is using
+         *  the ram. 1'h0: APB bus is using the ram.
+         */
+        uint32_t mem_owner_chm:1;
+        /** rx_filter_en_chm : R/W; bitpos: [4]; default: 0;
+         *  This is the receive filter's enable bit for CHANNELm.
+         */
+        uint32_t rx_filter_en_chm:1;
+        /** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15;
+         *  Ignores the input pulse when its width is smaller than this register value in APB
+         *  clock periods (in receive mode).
+         */
+        uint32_t rx_filter_thres_chm:8;
+        /** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0;
+         *  This is the channel m enable bit for wraparound mode: it will resume receiving at
+         *  the start when the data to be received is more than its memory size.
+         */
+        uint32_t mem_rx_wrap_en_chm:1;
+        uint32_t reserved_14:1;
+        /** conf_update_chm : WT; bitpos: [15]; default: 0;
+         *  synchronization bit for CHANNELm
+         */
+        uint32_t conf_update_chm:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} rmt_chmconf1_reg_t;
+
+/** Type of chm_rx_carrier_rm register
+ *  Channel m carrier remove register
+ */
+typedef union {
+    struct {
+        /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0;
+         *  The low level period in a carrier modulation mode is
+         *  (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m.
+         */
+        uint32_t carrier_low_thres_chm:16;
+        /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0;
+         *  The high level period in a carrier modulation mode is
+         *  (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m.
+         */
+        uint32_t carrier_high_thres_chm:16;
+    };
+    uint32_t val;
+} rmt_chm_rx_carrier_rm_reg_t;
+
+/** Type of sys_conf register
+ *  RMT apb configuration register
+ */
+typedef union {
+    struct {
+        /** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
+         *  1'h1: access memory directly.   1'h0: access memory by FIFO.
+         */
+        uint32_t apb_fifo_mask:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable the clock for RMT memory.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down RMT memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [3]; default: 0;
+         *  1: Disable RMT memory light sleep power down function. 0: Power down RMT memory
+         *  when RMT is in light sleep mode.
+         */
+        uint32_t mem_force_pu:1;
+        /** sclk_div_num : R/W; bitpos: [11:4]; default: 1;
+         *  the integral part of the fractional divisor
+         */
+        uint32_t sclk_div_num:8;
+        /** sclk_div_a : R/W; bitpos: [17:12]; default: 0;
+         *  the numerator of the fractional part of the fractional divisor
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_b : R/W; bitpos: [23:18]; default: 0;
+         *  the denominator of the fractional part of the fractional divisor
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_sel : R/W; bitpos: [25:24]; default: 1;
+         *  choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL
+         */
+        uint32_t sclk_sel:2;
+        /** sclk_active : R/W; bitpos: [26]; default: 1;
+         *  rmt_sclk switch
+         */
+        uint32_t sclk_active:1;
+        uint32_t reserved_27:4;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0:
+         *  Power down the drive clock of registers
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} rmt_sys_conf_reg_t;
+
+/** Type of ref_cnt_rst register
+ *  RMT clock divider reset register
+ */
+typedef union {
+    struct {
+        /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL0.
+         */
+        uint32_t ref_cnt_rst_ch0:1;
+        /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL1.
+         */
+        uint32_t ref_cnt_rst_ch1:1;
+        /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL2.
+         */
+        uint32_t ref_cnt_rst_ch2:1;
+        /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL3.
+         */
+        uint32_t ref_cnt_rst_ch3:1;
+        /** ref_cnt_rst_ch4 : WT; bitpos: [4]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL4.
+         */
+        uint32_t ref_cnt_rst_ch4:1;
+        /** ref_cnt_rst_ch5 : WT; bitpos: [5]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL5.
+         */
+        uint32_t ref_cnt_rst_ch5:1;
+        /** ref_cnt_rst_ch6 : WT; bitpos: [6]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL6.
+         */
+        uint32_t ref_cnt_rst_ch6:1;
+        /** ref_cnt_rst_ch7 : WT; bitpos: [7]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL7.
+         */
+        uint32_t ref_cnt_rst_ch7:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} rmt_ref_cnt_rst_reg_t;
+
+
+/** Group: Status registers */
+/** Type of chnstatus register
+ *  Channel n status register
+ */
+typedef union {
+    struct {
+        /** mem_raddr_ex_chn : RO; bitpos: [9:0]; default: 0;
+         *  This register records the memory address offset when transmitter of CHANNELn is
+         *  using the RAM.
+         */
+        uint32_t mem_raddr_ex_chn:10;
+        uint32_t reserved_10:1;
+        /** apb_mem_waddr_chn : RO; bitpos: [20:11]; default: 0;
+         *  This register records the memory address offset when writes RAM over APB bus.
+         */
+        uint32_t apb_mem_waddr_chn:10;
+        uint32_t reserved_21:1;
+        /** state_chn : RO; bitpos: [24:22]; default: 0;
+         *  This register records the FSM status of CHANNELn.
+         */
+        uint32_t state_chn:3;
+        /** mem_empty_chn : RO; bitpos: [25]; default: 0;
+         *  This status bit will be set when the data to be set is more than memory size and
+         *  the wraparound mode is disabled.
+         */
+        uint32_t mem_empty_chn:1;
+        /** apb_mem_wr_err_chn : RO; bitpos: [26]; default: 0;
+         *  This status bit will be set if the offset address out of memory size when writes
+         *  via APB bus.
+         */
+        uint32_t apb_mem_wr_err_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} rmt_chnstatus_reg_t;
+
+/** Type of chmstatus register
+ *  Channel m status register
+ */
+typedef union {
+    struct {
+        /** mem_waddr_ex_chm : RO; bitpos: [9:0]; default: 192;
+         *  This register records the memory address offset when receiver of CHANNELm is using
+         *  the RAM.
+         */
+        uint32_t mem_waddr_ex_chm:10;
+        uint32_t reserved_10:1;
+        /** apb_mem_raddr_chm : RO; bitpos: [20:11]; default: 192;
+         *  This register records the memory address offset when reads RAM over APB bus.
+         */
+        uint32_t apb_mem_raddr_chm:10;
+        uint32_t reserved_21:1;
+        /** state_chm : RO; bitpos: [24:22]; default: 0;
+         *  This register records the FSM status of CHANNELm.
+         */
+        uint32_t state_chm:3;
+        /** mem_owner_err_chm : RO; bitpos: [25]; default: 0;
+         *  This status bit will be set when the ownership of memory block is wrong.
+         */
+        uint32_t mem_owner_err_chm:1;
+        /** mem_full_chm : RO; bitpos: [26]; default: 0;
+         *  This status bit will be set if the receiver receives more data than the memory size.
+         */
+        uint32_t mem_full_chm:1;
+        /** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0;
+         *  This status bit will be set if the offset address out of memory size when reads via
+         *  APB bus.
+         */
+        uint32_t apb_mem_rd_err_chm:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} rmt_chmstatus_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The interrupt raw bit for CHANNEL0. Triggered when transmission done.
+         */
+        uint32_t ch0_tx_end_int_raw:1;
+        /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The interrupt raw bit for CHANNEL1. Triggered when transmission done.
+         */
+        uint32_t ch1_tx_end_int_raw:1;
+        /** ch2_tx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The interrupt raw bit for CHANNEL2. Triggered when transmission done.
+         */
+        uint32_t ch2_tx_end_int_raw:1;
+        /** ch3_tx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The interrupt raw bit for CHANNEL3. Triggered when transmission done.
+         */
+        uint32_t ch3_tx_end_int_raw:1;
+        /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The interrupt raw bit for CHANNEL0. Triggered when error occurs.
+         */
+        uint32_t ch0_err_int_raw:1;
+        /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The interrupt raw bit for CHANNEL1. Triggered when error occurs.
+         */
+        uint32_t ch1_err_int_raw:1;
+        /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The interrupt raw bit for CHANNEL2. Triggered when error occurs.
+         */
+        uint32_t ch2_err_int_raw:1;
+        /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The interrupt raw bit for CHANNEL3. Triggered when error occurs.
+         */
+        uint32_t ch3_err_int_raw:1;
+        /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than
+         *  configured value.
+         */
+        uint32_t ch0_tx_thr_event_int_raw:1;
+        /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than
+         *  configured value.
+         */
+        uint32_t ch1_tx_thr_event_int_raw:1;
+        /** ch2_tx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than
+         *  configured value.
+         */
+        uint32_t ch2_tx_thr_event_int_raw:1;
+        /** ch3_tx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than
+         *  configured value.
+         */
+        uint32_t ch3_tx_thr_event_int_raw:1;
+        /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the
+         *  configured threshold value.
+         */
+        uint32_t ch0_tx_loop_int_raw:1;
+        /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the
+         *  configured threshold value.
+         */
+        uint32_t ch1_tx_loop_int_raw:1;
+        /** ch2_tx_loop_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the
+         *  configured threshold value.
+         */
+        uint32_t ch2_tx_loop_int_raw:1;
+        /** ch3_tx_loop_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the
+         *  configured threshold value.
+         */
+        uint32_t ch3_tx_loop_int_raw:1;
+        /** ch4_rx_end_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The interrupt raw bit for CHANNEL4. Triggered when reception done.
+         */
+        uint32_t ch4_rx_end_int_raw:1;
+        /** ch5_rx_end_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The interrupt raw bit for CHANNEL5. Triggered when reception done.
+         */
+        uint32_t ch5_rx_end_int_raw:1;
+        /** ch6_rx_end_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The interrupt raw bit for CHANNEL6. Triggered when reception done.
+         */
+        uint32_t ch6_rx_end_int_raw:1;
+        /** ch7_rx_end_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The interrupt raw bit for CHANNEL7. Triggered when reception done.
+         */
+        uint32_t ch7_rx_end_int_raw:1;
+        /** ch4_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The interrupt raw bit for CHANNEL4. Triggered when error occurs.
+         */
+        uint32_t ch4_err_int_raw:1;
+        /** ch5_err_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  The interrupt raw bit for CHANNEL5. Triggered when error occurs.
+         */
+        uint32_t ch5_err_int_raw:1;
+        /** ch6_err_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  The interrupt raw bit for CHANNEL6. Triggered when error occurs.
+         */
+        uint32_t ch6_err_int_raw:1;
+        /** ch7_err_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  The interrupt raw bit for CHANNEL7. Triggered when error occurs.
+         */
+        uint32_t ch7_err_int_raw:1;
+        /** ch4_rx_thr_event_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than
+         *  configured value.
+         */
+        uint32_t ch4_rx_thr_event_int_raw:1;
+        /** ch5_rx_thr_event_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than
+         *  configured value.
+         */
+        uint32_t ch5_rx_thr_event_int_raw:1;
+        /** ch6_rx_thr_event_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than
+         *  configured value.
+         */
+        uint32_t ch6_rx_thr_event_int_raw:1;
+        /** ch7_rx_thr_event_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than
+         *  configured value.
+         */
+        uint32_t ch7_rx_thr_event_int_raw:1;
+        /** ch3_dma_access_fail_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails.
+         */
+        uint32_t ch3_dma_access_fail_int_raw:1;
+        /** ch7_dma_access_fail_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails.
+         */
+        uint32_t ch7_dma_access_fail_int_raw:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} rmt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for CH0_TX_END_INT.
+         */
+        uint32_t ch0_tx_end_int_st:1;
+        /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for CH1_TX_END_INT.
+         */
+        uint32_t ch1_tx_end_int_st:1;
+        /** ch2_tx_end_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for CH2_TX_END_INT.
+         */
+        uint32_t ch2_tx_end_int_st:1;
+        /** ch3_tx_end_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for CH3_TX_END_INT.
+         */
+        uint32_t ch3_tx_end_int_st:1;
+        /** ch0_err_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status bit for CH0_ERR_INT.
+         */
+        uint32_t ch0_err_int_st:1;
+        /** ch1_err_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status bit for CH1_ERR_INT.
+         */
+        uint32_t ch1_err_int_st:1;
+        /** ch2_err_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status bit for CH2_ERR_INT.
+         */
+        uint32_t ch2_err_int_st:1;
+        /** ch3_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status bit for CH3_ERR_INT.
+         */
+        uint32_t ch3_err_int_st:1;
+        /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
+         */
+        uint32_t ch0_tx_thr_event_int_st:1;
+        /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
+         */
+        uint32_t ch1_tx_thr_event_int_st:1;
+        /** ch2_tx_thr_event_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status bit for CH2_TX_THR_EVENT_INT.
+         */
+        uint32_t ch2_tx_thr_event_int_st:1;
+        /** ch3_tx_thr_event_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status bit for CH3_TX_THR_EVENT_INT.
+         */
+        uint32_t ch3_tx_thr_event_int_st:1;
+        /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status bit for CH0_TX_LOOP_INT.
+         */
+        uint32_t ch0_tx_loop_int_st:1;
+        /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status bit for CH1_TX_LOOP_INT.
+         */
+        uint32_t ch1_tx_loop_int_st:1;
+        /** ch2_tx_loop_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status bit for CH2_TX_LOOP_INT.
+         */
+        uint32_t ch2_tx_loop_int_st:1;
+        /** ch3_tx_loop_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status bit for CH3_TX_LOOP_INT.
+         */
+        uint32_t ch3_tx_loop_int_st:1;
+        /** ch4_rx_end_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status bit for CH4_RX_END_INT.
+         */
+        uint32_t ch4_rx_end_int_st:1;
+        /** ch5_rx_end_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status bit for CH5_RX_END_INT.
+         */
+        uint32_t ch5_rx_end_int_st:1;
+        /** ch6_rx_end_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked interrupt status bit for CH6_RX_END_INT.
+         */
+        uint32_t ch6_rx_end_int_st:1;
+        /** ch7_rx_end_int_st : RO; bitpos: [19]; default: 0;
+         *  The masked interrupt status bit for CH7_RX_END_INT.
+         */
+        uint32_t ch7_rx_end_int_st:1;
+        /** ch4_err_int_st : RO; bitpos: [20]; default: 0;
+         *  The masked interrupt status bit for CH4_ERR_INT.
+         */
+        uint32_t ch4_err_int_st:1;
+        /** ch5_err_int_st : RO; bitpos: [21]; default: 0;
+         *  The masked interrupt status bit for CH5_ERR_INT.
+         */
+        uint32_t ch5_err_int_st:1;
+        /** ch6_err_int_st : RO; bitpos: [22]; default: 0;
+         *  The masked interrupt status bit for CH6_ERR_INT.
+         */
+        uint32_t ch6_err_int_st:1;
+        /** ch7_err_int_st : RO; bitpos: [23]; default: 0;
+         *  The masked interrupt status bit for CH7_ERR_INT.
+         */
+        uint32_t ch7_err_int_st:1;
+        /** ch4_rx_thr_event_int_st : RO; bitpos: [24]; default: 0;
+         *  The masked interrupt status bit for CH4_RX_THR_EVENT_INT.
+         */
+        uint32_t ch4_rx_thr_event_int_st:1;
+        /** ch5_rx_thr_event_int_st : RO; bitpos: [25]; default: 0;
+         *  The masked interrupt status bit for CH5_RX_THR_EVENT_INT.
+         */
+        uint32_t ch5_rx_thr_event_int_st:1;
+        /** ch6_rx_thr_event_int_st : RO; bitpos: [26]; default: 0;
+         *  The masked interrupt status bit for CH6_RX_THR_EVENT_INT.
+         */
+        uint32_t ch6_rx_thr_event_int_st:1;
+        /** ch7_rx_thr_event_int_st : RO; bitpos: [27]; default: 0;
+         *  The masked interrupt status bit for CH7_RX_THR_EVENT_INT.
+         */
+        uint32_t ch7_rx_thr_event_int_st:1;
+        /** ch3_dma_access_fail_int_st : RO; bitpos: [28]; default: 0;
+         *  The masked interrupt status bit for  CH3_DMA_ACCESS_FAIL_INT.
+         */
+        uint32_t ch3_dma_access_fail_int_st:1;
+        /** ch7_dma_access_fail_int_st : RO; bitpos: [29]; default: 0;
+         *  The masked interrupt status bit for  CH7_DMA_ACCESS_FAIL_INT.
+         */
+        uint32_t ch7_dma_access_fail_int_st:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} rmt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for CH0_TX_END_INT.
+         */
+        uint32_t ch0_tx_end_int_ena:1;
+        /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for CH1_TX_END_INT.
+         */
+        uint32_t ch1_tx_end_int_ena:1;
+        /** ch2_tx_end_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for CH2_TX_END_INT.
+         */
+        uint32_t ch2_tx_end_int_ena:1;
+        /** ch3_tx_end_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for CH3_TX_END_INT.
+         */
+        uint32_t ch3_tx_end_int_ena:1;
+        /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for CH0_ERR_INT.
+         */
+        uint32_t ch0_err_int_ena:1;
+        /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for CH1_ERR_INT.
+         */
+        uint32_t ch1_err_int_ena:1;
+        /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for CH2_ERR_INT.
+         */
+        uint32_t ch2_err_int_ena:1;
+        /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for CH3_ERR_INT.
+         */
+        uint32_t ch3_err_int_ena:1;
+        /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for CH0_TX_THR_EVENT_INT.
+         */
+        uint32_t ch0_tx_thr_event_int_ena:1;
+        /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for CH1_TX_THR_EVENT_INT.
+         */
+        uint32_t ch1_tx_thr_event_int_ena:1;
+        /** ch2_tx_thr_event_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for CH2_TX_THR_EVENT_INT.
+         */
+        uint32_t ch2_tx_thr_event_int_ena:1;
+        /** ch3_tx_thr_event_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for CH3_TX_THR_EVENT_INT.
+         */
+        uint32_t ch3_tx_thr_event_int_ena:1;
+        /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for CH0_TX_LOOP_INT.
+         */
+        uint32_t ch0_tx_loop_int_ena:1;
+        /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for CH1_TX_LOOP_INT.
+         */
+        uint32_t ch1_tx_loop_int_ena:1;
+        /** ch2_tx_loop_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The interrupt enable bit for CH2_TX_LOOP_INT.
+         */
+        uint32_t ch2_tx_loop_int_ena:1;
+        /** ch3_tx_loop_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The interrupt enable bit for CH3_TX_LOOP_INT.
+         */
+        uint32_t ch3_tx_loop_int_ena:1;
+        /** ch4_rx_end_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The interrupt enable bit for CH4_RX_END_INT.
+         */
+        uint32_t ch4_rx_end_int_ena:1;
+        /** ch5_rx_end_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The interrupt enable bit for CH5_RX_END_INT.
+         */
+        uint32_t ch5_rx_end_int_ena:1;
+        /** ch6_rx_end_int_ena : R/W; bitpos: [18]; default: 0;
+         *  The interrupt enable bit for CH6_RX_END_INT.
+         */
+        uint32_t ch6_rx_end_int_ena:1;
+        /** ch7_rx_end_int_ena : R/W; bitpos: [19]; default: 0;
+         *  The interrupt enable bit for CH7_RX_END_INT.
+         */
+        uint32_t ch7_rx_end_int_ena:1;
+        /** ch4_err_int_ena : R/W; bitpos: [20]; default: 0;
+         *  The interrupt enable bit for CH4_ERR_INT.
+         */
+        uint32_t ch4_err_int_ena:1;
+        /** ch5_err_int_ena : R/W; bitpos: [21]; default: 0;
+         *  The interrupt enable bit for CH5_ERR_INT.
+         */
+        uint32_t ch5_err_int_ena:1;
+        /** ch6_err_int_ena : R/W; bitpos: [22]; default: 0;
+         *  The interrupt enable bit for CH6_ERR_INT.
+         */
+        uint32_t ch6_err_int_ena:1;
+        /** ch7_err_int_ena : R/W; bitpos: [23]; default: 0;
+         *  The interrupt enable bit for CH7_ERR_INT.
+         */
+        uint32_t ch7_err_int_ena:1;
+        /** ch4_rx_thr_event_int_ena : R/W; bitpos: [24]; default: 0;
+         *  The interrupt enable bit for CH4_RX_THR_EVENT_INT.
+         */
+        uint32_t ch4_rx_thr_event_int_ena:1;
+        /** ch5_rx_thr_event_int_ena : R/W; bitpos: [25]; default: 0;
+         *  The interrupt enable bit for CH5_RX_THR_EVENT_INT.
+         */
+        uint32_t ch5_rx_thr_event_int_ena:1;
+        /** ch6_rx_thr_event_int_ena : R/W; bitpos: [26]; default: 0;
+         *  The interrupt enable bit for CH6_RX_THR_EVENT_INT.
+         */
+        uint32_t ch6_rx_thr_event_int_ena:1;
+        /** ch7_rx_thr_event_int_ena : R/W; bitpos: [27]; default: 0;
+         *  The interrupt enable bit for CH7_RX_THR_EVENT_INT.
+         */
+        uint32_t ch7_rx_thr_event_int_ena:1;
+        /** ch3_dma_access_fail_int_ena : R/W; bitpos: [28]; default: 0;
+         *  The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT.
+         */
+        uint32_t ch3_dma_access_fail_int_ena:1;
+        /** ch7_dma_access_fail_int_ena : R/W; bitpos: [29]; default: 0;
+         *  The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT.
+         */
+        uint32_t ch7_dma_access_fail_int_ena:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} rmt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear theCH0_TX_END_INT interrupt.
+         */
+        uint32_t ch0_tx_end_int_clr:1;
+        /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear theCH1_TX_END_INT interrupt.
+         */
+        uint32_t ch1_tx_end_int_clr:1;
+        /** ch2_tx_end_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear theCH2_TX_END_INT interrupt.
+         */
+        uint32_t ch2_tx_end_int_clr:1;
+        /** ch3_tx_end_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear theCH3_TX_END_INT interrupt.
+         */
+        uint32_t ch3_tx_end_int_clr:1;
+        /** ch0_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear theCH0_ERR_INT interrupt.
+         */
+        uint32_t ch0_err_int_clr:1;
+        /** ch1_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear theCH1_ERR_INT interrupt.
+         */
+        uint32_t ch1_err_int_clr:1;
+        /** ch2_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear theCH2_ERR_INT interrupt.
+         */
+        uint32_t ch2_err_int_clr:1;
+        /** ch3_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear theCH3_ERR_INT interrupt.
+         */
+        uint32_t ch3_err_int_clr:1;
+        /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch0_tx_thr_event_int_clr:1;
+        /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch1_tx_thr_event_int_clr:1;
+        /** ch2_tx_thr_event_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch2_tx_thr_event_int_clr:1;
+        /** ch3_tx_thr_event_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch3_tx_thr_event_int_clr:1;
+        /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear theCH0_TX_LOOP_INT interrupt.
+         */
+        uint32_t ch0_tx_loop_int_clr:1;
+        /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear theCH1_TX_LOOP_INT interrupt.
+         */
+        uint32_t ch1_tx_loop_int_clr:1;
+        /** ch2_tx_loop_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear theCH2_TX_LOOP_INT interrupt.
+         */
+        uint32_t ch2_tx_loop_int_clr:1;
+        /** ch3_tx_loop_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear theCH3_TX_LOOP_INT interrupt.
+         */
+        uint32_t ch3_tx_loop_int_clr:1;
+        /** ch4_rx_end_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear theCH4_RX_END_INT interrupt.
+         */
+        uint32_t ch4_rx_end_int_clr:1;
+        /** ch5_rx_end_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear theCH5_RX_END_INT interrupt.
+         */
+        uint32_t ch5_rx_end_int_clr:1;
+        /** ch6_rx_end_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear theCH6_RX_END_INT interrupt.
+         */
+        uint32_t ch6_rx_end_int_clr:1;
+        /** ch7_rx_end_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear theCH7_RX_END_INT interrupt.
+         */
+        uint32_t ch7_rx_end_int_clr:1;
+        /** ch4_err_int_clr : WT; bitpos: [20]; default: 0;
+         *  Set this bit to clear theCH4_ERR_INT interrupt.
+         */
+        uint32_t ch4_err_int_clr:1;
+        /** ch5_err_int_clr : WT; bitpos: [21]; default: 0;
+         *  Set this bit to clear theCH5_ERR_INT interrupt.
+         */
+        uint32_t ch5_err_int_clr:1;
+        /** ch6_err_int_clr : WT; bitpos: [22]; default: 0;
+         *  Set this bit to clear theCH6_ERR_INT interrupt.
+         */
+        uint32_t ch6_err_int_clr:1;
+        /** ch7_err_int_clr : WT; bitpos: [23]; default: 0;
+         *  Set this bit to clear theCH7_ERR_INT interrupt.
+         */
+        uint32_t ch7_err_int_clr:1;
+        /** ch4_rx_thr_event_int_clr : WT; bitpos: [24]; default: 0;
+         *  Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch4_rx_thr_event_int_clr:1;
+        /** ch5_rx_thr_event_int_clr : WT; bitpos: [25]; default: 0;
+         *  Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch5_rx_thr_event_int_clr:1;
+        /** ch6_rx_thr_event_int_clr : WT; bitpos: [26]; default: 0;
+         *  Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch6_rx_thr_event_int_clr:1;
+        /** ch7_rx_thr_event_int_clr : WT; bitpos: [27]; default: 0;
+         *  Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch7_rx_thr_event_int_clr:1;
+        /** ch3_dma_access_fail_int_clr : WT; bitpos: [28]; default: 0;
+         *  Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt.
+         */
+        uint32_t ch3_dma_access_fail_int_clr:1;
+        /** ch7_dma_access_fail_int_clr : WT; bitpos: [29]; default: 0;
+         *  Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt.
+         */
+        uint32_t ch7_dma_access_fail_int_clr:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} rmt_int_clr_reg_t;
+
+
+/** Group: Carrier wave duty cycle registers */
+/** Type of chncarrier_duty register
+ *  Channel n duty cycle configuration register
+ */
+typedef union {
+    struct {
+        /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64;
+         *  This register is used to configure carrier wave 's low level clock period for
+         *  CHANNELn.
+         */
+        uint32_t carrier_low_chn:16;
+        /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64;
+         *  This register is used to configure carrier wave 's high level clock period for
+         *  CHANNELn.
+         */
+        uint32_t carrier_high_chn:16;
+    };
+    uint32_t val;
+} rmt_chncarrier_duty_reg_t;
+
+
+/** Group: Tx event configuration registers */
+/** Type of chn_tx_lim register
+ *  Channel n Tx event configuration register
+ */
+typedef union {
+    struct {
+        /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128;
+         *  This register is used to configure the maximum entries that CHANNELn can send out.
+         */
+        uint32_t tx_lim_chn:9;
+        /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0;
+         *  This register is used to configure the maximum loop count when tx_conti_mode is
+         *  valid.
+         */
+        uint32_t tx_loop_num_chn:10;
+        /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0;
+         *  This register is the enabled bit for loop count.
+         */
+        uint32_t tx_loop_cnt_en_chn:1;
+        /** loop_count_reset_chn : WT; bitpos: [20]; default: 0;
+         *  This register is used to reset the loop count when tx_conti_mode is valid.
+         */
+        uint32_t loop_count_reset_chn:1;
+        /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0;
+         *  This bit is used to enable the loop send stop function after the loop counter
+         *  counts to  loop number for CHANNELn.
+         */
+        uint32_t loop_stop_en_chn:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} rmt_chn_tx_lim_reg_t;
+
+/** Type of tx_sim register
+ *  RMT TX synchronous register
+ */
+typedef union {
+    struct {
+        /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable CHANNEL0 to start sending data synchronously with other
+         *  enabled channels.
+         */
+        uint32_t tx_sim_ch0:1;
+        /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable CHANNEL1 to start sending data synchronously with other
+         *  enabled channels.
+         */
+        uint32_t tx_sim_ch1:1;
+        /** tx_sim_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable CHANNEL2 to start sending data synchronously with other
+         *  enabled channels.
+         */
+        uint32_t tx_sim_ch2:1;
+        /** tx_sim_ch3 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable CHANNEL3 to start sending data synchronously with other
+         *  enabled channels.
+         */
+        uint32_t tx_sim_ch3:1;
+        /** tx_sim_en : R/W; bitpos: [4]; default: 0;
+         *  This register is used to enable multiple of channels to start sending data
+         *  synchronously.
+         */
+        uint32_t tx_sim_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} rmt_tx_sim_reg_t;
+
+
+/** Group: Rx event configuration registers */
+/** Type of chm_rx_lim register
+ *  Channel m Rx event configuration register
+ */
+typedef union {
+    struct {
+        /** chm_rx_lim_reg : R/W; bitpos: [8:0]; default: 128;
+         *  This register is used to configure the maximum entries that CHANNELm can receive.
+         */
+        uint32_t chm_rx_lim_reg:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} rmt_chm_rx_lim_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  RMT version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35655953;
+         *  This is the version register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} rmt_date_reg_t;
+
+
+typedef struct {
+    volatile rmt_chndata_reg_t chndata[4];
+    volatile rmt_chmdata_reg_t chmdata[4];
+    volatile rmt_chnconf0_reg_t chnconf0[4];
+    volatile rmt_chmconf0_reg_t ch4conf0;
+    volatile rmt_chmconf1_reg_t ch4conf1;
+    volatile rmt_chmconf0_reg_t ch5conf0;
+    volatile rmt_chmconf1_reg_t ch5conf1;
+    volatile rmt_chmconf0_reg_t ch6conf0;
+    volatile rmt_chmconf1_reg_t ch6conf1;
+    volatile rmt_chmconf0_reg_t ch7conf0;
+    volatile rmt_chmconf1_reg_t ch7conf1;
+    volatile rmt_chnstatus_reg_t chnstatus[4];
+    volatile rmt_chmstatus_reg_t chmstatus[4];
+    volatile rmt_int_raw_reg_t int_raw;
+    volatile rmt_int_st_reg_t int_st;
+    volatile rmt_int_ena_reg_t int_ena;
+    volatile rmt_int_clr_reg_t int_clr;
+    volatile rmt_chncarrier_duty_reg_t chncarrier_duty[4];
+    volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[4];
+    volatile rmt_chn_tx_lim_reg_t chn_tx_lim[4];
+    volatile rmt_chm_rx_lim_reg_t chm_rx_lim[4];
+    volatile rmt_sys_conf_reg_t sys_conf;
+    volatile rmt_tx_sim_reg_t tx_sim;
+    volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst;
+    volatile rmt_date_reg_t date;
+} rmt_dev_t;
+
+extern rmt_dev_t RMT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/rmt_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/rmt_reg.h
new file mode 100644
index 0000000000..772e8dd316
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/rmt_reg.h
@@ -0,0 +1,2799 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RMT_CH0DATA_REG register
+ *  The read and write  data register for CHANNEL0 by apb fifo access.
+ */
+#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0)
+/** RMT_CH0DATA : HRO; bitpos: [31:0]; default: 0;
+ *  Read and write data for channel 0 via APB FIFO.
+ */
+#define RMT_CH0DATA    0xFFFFFFFFU
+#define RMT_CH0DATA_M  (RMT_CH0DATA_V << RMT_CH0DATA_S)
+#define RMT_CH0DATA_V  0xFFFFFFFFU
+#define RMT_CH0DATA_S  0
+
+/** RMT_CH1DATA_REG register
+ *  The read and write  data register for CHANNEL1 by apb fifo access.
+ */
+#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4)
+/** RMT_CH1DATA : HRO; bitpos: [31:0]; default: 0;
+ *  Read and write data for channel 1 via APB FIFO.
+ */
+#define RMT_CH1DATA    0xFFFFFFFFU
+#define RMT_CH1DATA_M  (RMT_CH1DATA_V << RMT_CH1DATA_S)
+#define RMT_CH1DATA_V  0xFFFFFFFFU
+#define RMT_CH1DATA_S  0
+
+/** RMT_CH2DATA_REG register
+ *  The read and write  data register for CHANNEL2 by apb fifo access.
+ */
+#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8)
+/** RMT_CH2DATA : HRO; bitpos: [31:0]; default: 0;
+ *  Read and write data for channel 2 via APB FIFO.
+ */
+#define RMT_CH2DATA    0xFFFFFFFFU
+#define RMT_CH2DATA_M  (RMT_CH2DATA_V << RMT_CH2DATA_S)
+#define RMT_CH2DATA_V  0xFFFFFFFFU
+#define RMT_CH2DATA_S  0
+
+/** RMT_CH3DATA_REG register
+ *  The read and write  data register for CHANNEL3 by apb fifo access.
+ */
+#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc)
+/** RMT_CH3DATA : HRO; bitpos: [31:0]; default: 0;
+ *  Read and write data for channel 3 via APB FIFO.
+ */
+#define RMT_CH3DATA    0xFFFFFFFFU
+#define RMT_CH3DATA_M  (RMT_CH3DATA_V << RMT_CH3DATA_S)
+#define RMT_CH3DATA_V  0xFFFFFFFFU
+#define RMT_CH3DATA_S  0
+
+/** RMT_CH4DATA_REG register
+ *  The read and write  data register for CHANNEL$n by apb fifo access.
+ */
+#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x10)
+/** RMT_CH4DATA : HRO; bitpos: [31:0]; default: 0;
+ *  Read and write data for channel $n via APB FIFO.
+ */
+#define RMT_CH4DATA    0xFFFFFFFFU
+#define RMT_CH4DATA_M  (RMT_CH4DATA_V << RMT_CH4DATA_S)
+#define RMT_CH4DATA_V  0xFFFFFFFFU
+#define RMT_CH4DATA_S  0
+
+/** RMT_CH5DATA_REG register
+ *  The read and write  data register for CHANNEL$n by apb fifo access.
+ */
+#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x14)
+/** RMT_CH5DATA : HRO; bitpos: [31:0]; default: 0;
+ *  Read and write data for channel $n via APB FIFO.
+ */
+#define RMT_CH5DATA    0xFFFFFFFFU
+#define RMT_CH5DATA_M  (RMT_CH5DATA_V << RMT_CH5DATA_S)
+#define RMT_CH5DATA_V  0xFFFFFFFFU
+#define RMT_CH5DATA_S  0
+
+/** RMT_CH6DATA_REG register
+ *  The read and write  data register for CHANNEL$n by apb fifo access.
+ */
+#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x18)
+/** RMT_CH6DATA : HRO; bitpos: [31:0]; default: 0;
+ *  Read and write data for channel $n via APB FIFO.
+ */
+#define RMT_CH6DATA    0xFFFFFFFFU
+#define RMT_CH6DATA_M  (RMT_CH6DATA_V << RMT_CH6DATA_S)
+#define RMT_CH6DATA_V  0xFFFFFFFFU
+#define RMT_CH6DATA_S  0
+
+/** RMT_CH7DATA_REG register
+ *  The read and write  data register for CHANNEL$n by apb fifo access.
+ */
+#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x1c)
+/** RMT_CH7DATA : HRO; bitpos: [31:0]; default: 0;
+ *  Read and write data for channel $n via APB FIFO.
+ */
+#define RMT_CH7DATA    0xFFFFFFFFU
+#define RMT_CH7DATA_M  (RMT_CH7DATA_V << RMT_CH7DATA_S)
+#define RMT_CH7DATA_V  0xFFFFFFFFU
+#define RMT_CH7DATA_S  0
+
+/** RMT_CH0CONF0_REG register
+ *  Channel 0 configure register 0
+ */
+#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x20)
+/** RMT_TX_START_CH0 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to start sending data on CHANNEL0.
+ */
+#define RMT_TX_START_CH0    (BIT(0))
+#define RMT_TX_START_CH0_M  (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S)
+#define RMT_TX_START_CH0_V  0x00000001U
+#define RMT_TX_START_CH0_S  0
+/** RMT_MEM_RD_RST_CH0 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset read ram address for CHANNEL0 by accessing transmitter.
+ */
+#define RMT_MEM_RD_RST_CH0    (BIT(1))
+#define RMT_MEM_RD_RST_CH0_M  (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S)
+#define RMT_MEM_RD_RST_CH0_V  0x00000001U
+#define RMT_MEM_RD_RST_CH0_S  1
+/** RMT_APB_MEM_RST_CH0 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to reset W/R ram address for CHANNEL0 by accessing apb fifo.
+ */
+#define RMT_APB_MEM_RST_CH0    (BIT(2))
+#define RMT_APB_MEM_RST_CH0_M  (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S)
+#define RMT_APB_MEM_RST_CH0_V  0x00000001U
+#define RMT_APB_MEM_RST_CH0_S  2
+/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to restart transmission  from the first data to the last data in
+ *  CHANNEL0.
+ */
+#define RMT_TX_CONTI_MODE_CH0    (BIT(3))
+#define RMT_TX_CONTI_MODE_CH0_M  (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S)
+#define RMT_TX_CONTI_MODE_CH0_V  0x00000001U
+#define RMT_TX_CONTI_MODE_CH0_S  3
+/** RMT_MEM_TX_WRAP_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  This is the channel 0 enable bit for wraparound mode: it will resume sending at the
+ *  start when the data to be sent is more than its memory size.
+ */
+#define RMT_MEM_TX_WRAP_EN_CH0    (BIT(4))
+#define RMT_MEM_TX_WRAP_EN_CH0_M  (RMT_MEM_TX_WRAP_EN_CH0_V << RMT_MEM_TX_WRAP_EN_CH0_S)
+#define RMT_MEM_TX_WRAP_EN_CH0_V  0x00000001U
+#define RMT_MEM_TX_WRAP_EN_CH0_S  4
+/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [5]; default: 0;
+ *  This bit configures the level of output signal in CHANNEL0 when the latter is in
+ *  IDLE state.
+ */
+#define RMT_IDLE_OUT_LV_CH0    (BIT(5))
+#define RMT_IDLE_OUT_LV_CH0_M  (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S)
+#define RMT_IDLE_OUT_LV_CH0_V  0x00000001U
+#define RMT_IDLE_OUT_LV_CH0_S  5
+/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [6]; default: 0;
+ *  This is the output enable-control bit for CHANNEL0 in IDLE state.
+ */
+#define RMT_IDLE_OUT_EN_CH0    (BIT(6))
+#define RMT_IDLE_OUT_EN_CH0_M  (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S)
+#define RMT_IDLE_OUT_EN_CH0_V  0x00000001U
+#define RMT_IDLE_OUT_EN_CH0_S  6
+/** RMT_TX_STOP_CH0 : R/W/SC; bitpos: [7]; default: 0;
+ *  Set this bit to stop the transmitter of CHANNEL0 sending data out.
+ */
+#define RMT_TX_STOP_CH0    (BIT(7))
+#define RMT_TX_STOP_CH0_M  (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S)
+#define RMT_TX_STOP_CH0_V  0x00000001U
+#define RMT_TX_STOP_CH0_S  7
+/** RMT_DIV_CNT_CH0 : R/W; bitpos: [15:8]; default: 2;
+ *  This register is used to configure the divider for clock of CHANNEL0.
+ */
+#define RMT_DIV_CNT_CH0    0x000000FFU
+#define RMT_DIV_CNT_CH0_M  (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S)
+#define RMT_DIV_CNT_CH0_V  0x000000FFU
+#define RMT_DIV_CNT_CH0_S  8
+/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [19:16]; default: 1;
+ *  This register is used to configure the maximum size of memory allocated to CHANNEL0.
+ */
+#define RMT_MEM_SIZE_CH0    0x0000000FU
+#define RMT_MEM_SIZE_CH0_M  (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S)
+#define RMT_MEM_SIZE_CH0_V  0x0000000FU
+#define RMT_MEM_SIZE_CH0_S  16
+/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [20]; default: 1;
+ *  1: Add carrier modulation on the output signal only at the send data state for
+ *  CHANNEL0. 0: Add carrier modulation on the output signal at all state for CHANNEL0.
+ *  Only valid when RMT_CARRIER_EN_CH0 is 1.
+ */
+#define RMT_CARRIER_EFF_EN_CH0    (BIT(20))
+#define RMT_CARRIER_EFF_EN_CH0_M  (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S)
+#define RMT_CARRIER_EFF_EN_CH0_V  0x00000001U
+#define RMT_CARRIER_EFF_EN_CH0_S  20
+/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [21]; default: 1;
+ *  This is the carrier modulation enable-control bit for CHANNEL0. 1: Add carrier
+ *  modulation in the output signal. 0: No carrier modulation in sig_out.
+ */
+#define RMT_CARRIER_EN_CH0    (BIT(21))
+#define RMT_CARRIER_EN_CH0_M  (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S)
+#define RMT_CARRIER_EN_CH0_V  0x00000001U
+#define RMT_CARRIER_EN_CH0_S  21
+/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [22]; default: 1;
+ *  This bit is used to configure the position of carrier wave for CHANNEL0.1'h0: add
+ *  carrier wave on low level.1'h1: add carrier wave on high level.
+ */
+#define RMT_CARRIER_OUT_LV_CH0    (BIT(22))
+#define RMT_CARRIER_OUT_LV_CH0_M  (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S)
+#define RMT_CARRIER_OUT_LV_CH0_V  0x00000001U
+#define RMT_CARRIER_OUT_LV_CH0_S  22
+/** RMT_CONF_UPDATE_CH0 : WT; bitpos: [24]; default: 0;
+ *  synchronization bit for CHANNEL0
+ */
+#define RMT_CONF_UPDATE_CH0    (BIT(24))
+#define RMT_CONF_UPDATE_CH0_M  (RMT_CONF_UPDATE_CH0_V << RMT_CONF_UPDATE_CH0_S)
+#define RMT_CONF_UPDATE_CH0_V  0x00000001U
+#define RMT_CONF_UPDATE_CH0_S  24
+
+/** RMT_CH1CONF0_REG register
+ *  Channel 1 configure register 0
+ */
+#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x24)
+/** RMT_TX_START_CH1 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to start sending data on CHANNEL1.
+ */
+#define RMT_TX_START_CH1    (BIT(0))
+#define RMT_TX_START_CH1_M  (RMT_TX_START_CH1_V << RMT_TX_START_CH1_S)
+#define RMT_TX_START_CH1_V  0x00000001U
+#define RMT_TX_START_CH1_S  0
+/** RMT_MEM_RD_RST_CH1 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset read ram address for CHANNEL1 by accessing transmitter.
+ */
+#define RMT_MEM_RD_RST_CH1    (BIT(1))
+#define RMT_MEM_RD_RST_CH1_M  (RMT_MEM_RD_RST_CH1_V << RMT_MEM_RD_RST_CH1_S)
+#define RMT_MEM_RD_RST_CH1_V  0x00000001U
+#define RMT_MEM_RD_RST_CH1_S  1
+/** RMT_APB_MEM_RST_CH1 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to reset W/R ram address for CHANNEL1 by accessing apb fifo.
+ */
+#define RMT_APB_MEM_RST_CH1    (BIT(2))
+#define RMT_APB_MEM_RST_CH1_M  (RMT_APB_MEM_RST_CH1_V << RMT_APB_MEM_RST_CH1_S)
+#define RMT_APB_MEM_RST_CH1_V  0x00000001U
+#define RMT_APB_MEM_RST_CH1_S  2
+/** RMT_TX_CONTI_MODE_CH1 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to restart transmission  from the first data to the last data in
+ *  CHANNEL1.
+ */
+#define RMT_TX_CONTI_MODE_CH1    (BIT(3))
+#define RMT_TX_CONTI_MODE_CH1_M  (RMT_TX_CONTI_MODE_CH1_V << RMT_TX_CONTI_MODE_CH1_S)
+#define RMT_TX_CONTI_MODE_CH1_V  0x00000001U
+#define RMT_TX_CONTI_MODE_CH1_S  3
+/** RMT_MEM_TX_WRAP_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ *  This is the channel 1 enable bit for wraparound mode: it will resume sending at the
+ *  start when the data to be sent is more than its memory size.
+ */
+#define RMT_MEM_TX_WRAP_EN_CH1    (BIT(4))
+#define RMT_MEM_TX_WRAP_EN_CH1_M  (RMT_MEM_TX_WRAP_EN_CH1_V << RMT_MEM_TX_WRAP_EN_CH1_S)
+#define RMT_MEM_TX_WRAP_EN_CH1_V  0x00000001U
+#define RMT_MEM_TX_WRAP_EN_CH1_S  4
+/** RMT_IDLE_OUT_LV_CH1 : R/W; bitpos: [5]; default: 0;
+ *  This bit configures the level of output signal in CHANNEL1 when the latter is in
+ *  IDLE state.
+ */
+#define RMT_IDLE_OUT_LV_CH1    (BIT(5))
+#define RMT_IDLE_OUT_LV_CH1_M  (RMT_IDLE_OUT_LV_CH1_V << RMT_IDLE_OUT_LV_CH1_S)
+#define RMT_IDLE_OUT_LV_CH1_V  0x00000001U
+#define RMT_IDLE_OUT_LV_CH1_S  5
+/** RMT_IDLE_OUT_EN_CH1 : R/W; bitpos: [6]; default: 0;
+ *  This is the output enable-control bit for CHANNEL1 in IDLE state.
+ */
+#define RMT_IDLE_OUT_EN_CH1    (BIT(6))
+#define RMT_IDLE_OUT_EN_CH1_M  (RMT_IDLE_OUT_EN_CH1_V << RMT_IDLE_OUT_EN_CH1_S)
+#define RMT_IDLE_OUT_EN_CH1_V  0x00000001U
+#define RMT_IDLE_OUT_EN_CH1_S  6
+/** RMT_TX_STOP_CH1 : R/W/SC; bitpos: [7]; default: 0;
+ *  Set this bit to stop the transmitter of CHANNEL1 sending data out.
+ */
+#define RMT_TX_STOP_CH1    (BIT(7))
+#define RMT_TX_STOP_CH1_M  (RMT_TX_STOP_CH1_V << RMT_TX_STOP_CH1_S)
+#define RMT_TX_STOP_CH1_V  0x00000001U
+#define RMT_TX_STOP_CH1_S  7
+/** RMT_DIV_CNT_CH1 : R/W; bitpos: [15:8]; default: 2;
+ *  This register is used to configure the divider for clock of CHANNEL1.
+ */
+#define RMT_DIV_CNT_CH1    0x000000FFU
+#define RMT_DIV_CNT_CH1_M  (RMT_DIV_CNT_CH1_V << RMT_DIV_CNT_CH1_S)
+#define RMT_DIV_CNT_CH1_V  0x000000FFU
+#define RMT_DIV_CNT_CH1_S  8
+/** RMT_MEM_SIZE_CH1 : R/W; bitpos: [19:16]; default: 1;
+ *  This register is used to configure the maximum size of memory allocated to CHANNEL1.
+ */
+#define RMT_MEM_SIZE_CH1    0x0000000FU
+#define RMT_MEM_SIZE_CH1_M  (RMT_MEM_SIZE_CH1_V << RMT_MEM_SIZE_CH1_S)
+#define RMT_MEM_SIZE_CH1_V  0x0000000FU
+#define RMT_MEM_SIZE_CH1_S  16
+/** RMT_CARRIER_EFF_EN_CH1 : R/W; bitpos: [20]; default: 1;
+ *  1: Add carrier modulation on the output signal only at the send data state for
+ *  CHANNEL1. 0: Add carrier modulation on the output signal at all state for CHANNEL1.
+ *  Only valid when RMT_CARRIER_EN_CH1 is 1.
+ */
+#define RMT_CARRIER_EFF_EN_CH1    (BIT(20))
+#define RMT_CARRIER_EFF_EN_CH1_M  (RMT_CARRIER_EFF_EN_CH1_V << RMT_CARRIER_EFF_EN_CH1_S)
+#define RMT_CARRIER_EFF_EN_CH1_V  0x00000001U
+#define RMT_CARRIER_EFF_EN_CH1_S  20
+/** RMT_CARRIER_EN_CH1 : R/W; bitpos: [21]; default: 1;
+ *  This is the carrier modulation enable-control bit for CHANNEL1. 1: Add carrier
+ *  modulation in the output signal. 0: No carrier modulation in sig_out.
+ */
+#define RMT_CARRIER_EN_CH1    (BIT(21))
+#define RMT_CARRIER_EN_CH1_M  (RMT_CARRIER_EN_CH1_V << RMT_CARRIER_EN_CH1_S)
+#define RMT_CARRIER_EN_CH1_V  0x00000001U
+#define RMT_CARRIER_EN_CH1_S  21
+/** RMT_CARRIER_OUT_LV_CH1 : R/W; bitpos: [22]; default: 1;
+ *  This bit is used to configure the position of carrier wave for CHANNEL1.1'h0: add
+ *  carrier wave on low level.1'h1: add carrier wave on high level.
+ */
+#define RMT_CARRIER_OUT_LV_CH1    (BIT(22))
+#define RMT_CARRIER_OUT_LV_CH1_M  (RMT_CARRIER_OUT_LV_CH1_V << RMT_CARRIER_OUT_LV_CH1_S)
+#define RMT_CARRIER_OUT_LV_CH1_V  0x00000001U
+#define RMT_CARRIER_OUT_LV_CH1_S  22
+/** RMT_CONF_UPDATE_CH1 : WT; bitpos: [24]; default: 0;
+ *  synchronization bit for CHANNEL1
+ */
+#define RMT_CONF_UPDATE_CH1    (BIT(24))
+#define RMT_CONF_UPDATE_CH1_M  (RMT_CONF_UPDATE_CH1_V << RMT_CONF_UPDATE_CH1_S)
+#define RMT_CONF_UPDATE_CH1_V  0x00000001U
+#define RMT_CONF_UPDATE_CH1_S  24
+
+/** RMT_CH2CONF0_REG register
+ *  Channel 2 configure register 0
+ */
+#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x28)
+/** RMT_TX_START_CH2 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to start sending data on CHANNEL2.
+ */
+#define RMT_TX_START_CH2    (BIT(0))
+#define RMT_TX_START_CH2_M  (RMT_TX_START_CH2_V << RMT_TX_START_CH2_S)
+#define RMT_TX_START_CH2_V  0x00000001U
+#define RMT_TX_START_CH2_S  0
+/** RMT_MEM_RD_RST_CH2 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset read ram address for CHANNEL2 by accessing transmitter.
+ */
+#define RMT_MEM_RD_RST_CH2    (BIT(1))
+#define RMT_MEM_RD_RST_CH2_M  (RMT_MEM_RD_RST_CH2_V << RMT_MEM_RD_RST_CH2_S)
+#define RMT_MEM_RD_RST_CH2_V  0x00000001U
+#define RMT_MEM_RD_RST_CH2_S  1
+/** RMT_APB_MEM_RST_CH2 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to reset W/R ram address for CHANNEL2 by accessing apb fifo.
+ */
+#define RMT_APB_MEM_RST_CH2    (BIT(2))
+#define RMT_APB_MEM_RST_CH2_M  (RMT_APB_MEM_RST_CH2_V << RMT_APB_MEM_RST_CH2_S)
+#define RMT_APB_MEM_RST_CH2_V  0x00000001U
+#define RMT_APB_MEM_RST_CH2_S  2
+/** RMT_TX_CONTI_MODE_CH2 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to restart transmission  from the first data to the last data in
+ *  CHANNEL2.
+ */
+#define RMT_TX_CONTI_MODE_CH2    (BIT(3))
+#define RMT_TX_CONTI_MODE_CH2_M  (RMT_TX_CONTI_MODE_CH2_V << RMT_TX_CONTI_MODE_CH2_S)
+#define RMT_TX_CONTI_MODE_CH2_V  0x00000001U
+#define RMT_TX_CONTI_MODE_CH2_S  3
+/** RMT_MEM_TX_WRAP_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  This is the channel 2 enable bit for wraparound mode: it will resume sending at the
+ *  start when the data to be sent is more than its memory size.
+ */
+#define RMT_MEM_TX_WRAP_EN_CH2    (BIT(4))
+#define RMT_MEM_TX_WRAP_EN_CH2_M  (RMT_MEM_TX_WRAP_EN_CH2_V << RMT_MEM_TX_WRAP_EN_CH2_S)
+#define RMT_MEM_TX_WRAP_EN_CH2_V  0x00000001U
+#define RMT_MEM_TX_WRAP_EN_CH2_S  4
+/** RMT_IDLE_OUT_LV_CH2 : R/W; bitpos: [5]; default: 0;
+ *  This bit configures the level of output signal in CHANNEL2 when the latter is in
+ *  IDLE state.
+ */
+#define RMT_IDLE_OUT_LV_CH2    (BIT(5))
+#define RMT_IDLE_OUT_LV_CH2_M  (RMT_IDLE_OUT_LV_CH2_V << RMT_IDLE_OUT_LV_CH2_S)
+#define RMT_IDLE_OUT_LV_CH2_V  0x00000001U
+#define RMT_IDLE_OUT_LV_CH2_S  5
+/** RMT_IDLE_OUT_EN_CH2 : R/W; bitpos: [6]; default: 0;
+ *  This is the output enable-control bit for CHANNEL2 in IDLE state.
+ */
+#define RMT_IDLE_OUT_EN_CH2    (BIT(6))
+#define RMT_IDLE_OUT_EN_CH2_M  (RMT_IDLE_OUT_EN_CH2_V << RMT_IDLE_OUT_EN_CH2_S)
+#define RMT_IDLE_OUT_EN_CH2_V  0x00000001U
+#define RMT_IDLE_OUT_EN_CH2_S  6
+/** RMT_TX_STOP_CH2 : R/W/SC; bitpos: [7]; default: 0;
+ *  Set this bit to stop the transmitter of CHANNEL2 sending data out.
+ */
+#define RMT_TX_STOP_CH2    (BIT(7))
+#define RMT_TX_STOP_CH2_M  (RMT_TX_STOP_CH2_V << RMT_TX_STOP_CH2_S)
+#define RMT_TX_STOP_CH2_V  0x00000001U
+#define RMT_TX_STOP_CH2_S  7
+/** RMT_DIV_CNT_CH2 : R/W; bitpos: [15:8]; default: 2;
+ *  This register is used to configure the divider for clock of CHANNEL2.
+ */
+#define RMT_DIV_CNT_CH2    0x000000FFU
+#define RMT_DIV_CNT_CH2_M  (RMT_DIV_CNT_CH2_V << RMT_DIV_CNT_CH2_S)
+#define RMT_DIV_CNT_CH2_V  0x000000FFU
+#define RMT_DIV_CNT_CH2_S  8
+/** RMT_MEM_SIZE_CH2 : R/W; bitpos: [19:16]; default: 1;
+ *  This register is used to configure the maximum size of memory allocated to CHANNEL2.
+ */
+#define RMT_MEM_SIZE_CH2    0x0000000FU
+#define RMT_MEM_SIZE_CH2_M  (RMT_MEM_SIZE_CH2_V << RMT_MEM_SIZE_CH2_S)
+#define RMT_MEM_SIZE_CH2_V  0x0000000FU
+#define RMT_MEM_SIZE_CH2_S  16
+/** RMT_CARRIER_EFF_EN_CH2 : R/W; bitpos: [20]; default: 1;
+ *  1: Add carrier modulation on the output signal only at the send data state for
+ *  CHANNEL2. 0: Add carrier modulation on the output signal at all state for CHANNEL2.
+ *  Only valid when RMT_CARRIER_EN_CH2 is 1.
+ */
+#define RMT_CARRIER_EFF_EN_CH2    (BIT(20))
+#define RMT_CARRIER_EFF_EN_CH2_M  (RMT_CARRIER_EFF_EN_CH2_V << RMT_CARRIER_EFF_EN_CH2_S)
+#define RMT_CARRIER_EFF_EN_CH2_V  0x00000001U
+#define RMT_CARRIER_EFF_EN_CH2_S  20
+/** RMT_CARRIER_EN_CH2 : R/W; bitpos: [21]; default: 1;
+ *  This is the carrier modulation enable-control bit for CHANNEL2. 1: Add carrier
+ *  modulation in the output signal. 0: No carrier modulation in sig_out.
+ */
+#define RMT_CARRIER_EN_CH2    (BIT(21))
+#define RMT_CARRIER_EN_CH2_M  (RMT_CARRIER_EN_CH2_V << RMT_CARRIER_EN_CH2_S)
+#define RMT_CARRIER_EN_CH2_V  0x00000001U
+#define RMT_CARRIER_EN_CH2_S  21
+/** RMT_CARRIER_OUT_LV_CH2 : R/W; bitpos: [22]; default: 1;
+ *  This bit is used to configure the position of carrier wave for CHANNEL2.1'h0: add
+ *  carrier wave on low level.1'h1: add carrier wave on high level.
+ */
+#define RMT_CARRIER_OUT_LV_CH2    (BIT(22))
+#define RMT_CARRIER_OUT_LV_CH2_M  (RMT_CARRIER_OUT_LV_CH2_V << RMT_CARRIER_OUT_LV_CH2_S)
+#define RMT_CARRIER_OUT_LV_CH2_V  0x00000001U
+#define RMT_CARRIER_OUT_LV_CH2_S  22
+/** RMT_CONF_UPDATE_CH2 : WT; bitpos: [24]; default: 0;
+ *  synchronization bit for CHANNEL2
+ */
+#define RMT_CONF_UPDATE_CH2    (BIT(24))
+#define RMT_CONF_UPDATE_CH2_M  (RMT_CONF_UPDATE_CH2_V << RMT_CONF_UPDATE_CH2_S)
+#define RMT_CONF_UPDATE_CH2_V  0x00000001U
+#define RMT_CONF_UPDATE_CH2_S  24
+
+/** RMT_CH3CONF0_REG register
+ *  Channel 3 configure register 0
+ */
+#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x2c)
+/** RMT_TX_START_CH3 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to start sending data on CHANNEL3.
+ */
+#define RMT_TX_START_CH3    (BIT(0))
+#define RMT_TX_START_CH3_M  (RMT_TX_START_CH3_V << RMT_TX_START_CH3_S)
+#define RMT_TX_START_CH3_V  0x00000001U
+#define RMT_TX_START_CH3_S  0
+/** RMT_MEM_RD_RST_CH3 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset read ram address for CHANNEL3 by accessing transmitter.
+ */
+#define RMT_MEM_RD_RST_CH3    (BIT(1))
+#define RMT_MEM_RD_RST_CH3_M  (RMT_MEM_RD_RST_CH3_V << RMT_MEM_RD_RST_CH3_S)
+#define RMT_MEM_RD_RST_CH3_V  0x00000001U
+#define RMT_MEM_RD_RST_CH3_S  1
+/** RMT_APB_MEM_RST_CH3 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to reset W/R ram address for CHANNEL3 by accessing apb fifo.
+ */
+#define RMT_APB_MEM_RST_CH3    (BIT(2))
+#define RMT_APB_MEM_RST_CH3_M  (RMT_APB_MEM_RST_CH3_V << RMT_APB_MEM_RST_CH3_S)
+#define RMT_APB_MEM_RST_CH3_V  0x00000001U
+#define RMT_APB_MEM_RST_CH3_S  2
+/** RMT_TX_CONTI_MODE_CH3 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to restart transmission  from the first data to the last data in
+ *  CHANNEL3.
+ */
+#define RMT_TX_CONTI_MODE_CH3    (BIT(3))
+#define RMT_TX_CONTI_MODE_CH3_M  (RMT_TX_CONTI_MODE_CH3_V << RMT_TX_CONTI_MODE_CH3_S)
+#define RMT_TX_CONTI_MODE_CH3_V  0x00000001U
+#define RMT_TX_CONTI_MODE_CH3_S  3
+/** RMT_MEM_TX_WRAP_EN_CH3 : R/W; bitpos: [4]; default: 0;
+ *  This is the channel 3 enable bit for wraparound mode: it will resume sending at the
+ *  start when the data to be sent is more than its memory size.
+ */
+#define RMT_MEM_TX_WRAP_EN_CH3    (BIT(4))
+#define RMT_MEM_TX_WRAP_EN_CH3_M  (RMT_MEM_TX_WRAP_EN_CH3_V << RMT_MEM_TX_WRAP_EN_CH3_S)
+#define RMT_MEM_TX_WRAP_EN_CH3_V  0x00000001U
+#define RMT_MEM_TX_WRAP_EN_CH3_S  4
+/** RMT_IDLE_OUT_LV_CH3 : R/W; bitpos: [5]; default: 0;
+ *  This bit configures the level of output signal in CHANNEL3 when the latter is in
+ *  IDLE state.
+ */
+#define RMT_IDLE_OUT_LV_CH3    (BIT(5))
+#define RMT_IDLE_OUT_LV_CH3_M  (RMT_IDLE_OUT_LV_CH3_V << RMT_IDLE_OUT_LV_CH3_S)
+#define RMT_IDLE_OUT_LV_CH3_V  0x00000001U
+#define RMT_IDLE_OUT_LV_CH3_S  5
+/** RMT_IDLE_OUT_EN_CH3 : R/W; bitpos: [6]; default: 0;
+ *  This is the output enable-control bit for CHANNEL3 in IDLE state.
+ */
+#define RMT_IDLE_OUT_EN_CH3    (BIT(6))
+#define RMT_IDLE_OUT_EN_CH3_M  (RMT_IDLE_OUT_EN_CH3_V << RMT_IDLE_OUT_EN_CH3_S)
+#define RMT_IDLE_OUT_EN_CH3_V  0x00000001U
+#define RMT_IDLE_OUT_EN_CH3_S  6
+/** RMT_TX_STOP_CH3 : R/W/SC; bitpos: [7]; default: 0;
+ *  Set this bit to stop the transmitter of CHANNEL3 sending data out.
+ */
+#define RMT_TX_STOP_CH3    (BIT(7))
+#define RMT_TX_STOP_CH3_M  (RMT_TX_STOP_CH3_V << RMT_TX_STOP_CH3_S)
+#define RMT_TX_STOP_CH3_V  0x00000001U
+#define RMT_TX_STOP_CH3_S  7
+/** RMT_DIV_CNT_CH3 : R/W; bitpos: [15:8]; default: 2;
+ *  This register is used to configure the divider for clock of CHANNEL3.
+ */
+#define RMT_DIV_CNT_CH3    0x000000FFU
+#define RMT_DIV_CNT_CH3_M  (RMT_DIV_CNT_CH3_V << RMT_DIV_CNT_CH3_S)
+#define RMT_DIV_CNT_CH3_V  0x000000FFU
+#define RMT_DIV_CNT_CH3_S  8
+/** RMT_MEM_SIZE_CH3 : R/W; bitpos: [19:16]; default: 1;
+ *  This register is used to configure the maximum size of memory allocated to CHANNEL3.
+ */
+#define RMT_MEM_SIZE_CH3    0x0000000FU
+#define RMT_MEM_SIZE_CH3_M  (RMT_MEM_SIZE_CH3_V << RMT_MEM_SIZE_CH3_S)
+#define RMT_MEM_SIZE_CH3_V  0x0000000FU
+#define RMT_MEM_SIZE_CH3_S  16
+/** RMT_CARRIER_EFF_EN_CH3 : R/W; bitpos: [20]; default: 1;
+ *  1: Add carrier modulation on the output signal only at the send data state for
+ *  CHANNEL3. 0: Add carrier modulation on the output signal at all state for CHANNEL3.
+ *  Only valid when RMT_CARRIER_EN_CH3 is 1.
+ */
+#define RMT_CARRIER_EFF_EN_CH3    (BIT(20))
+#define RMT_CARRIER_EFF_EN_CH3_M  (RMT_CARRIER_EFF_EN_CH3_V << RMT_CARRIER_EFF_EN_CH3_S)
+#define RMT_CARRIER_EFF_EN_CH3_V  0x00000001U
+#define RMT_CARRIER_EFF_EN_CH3_S  20
+/** RMT_CARRIER_EN_CH3 : R/W; bitpos: [21]; default: 1;
+ *  This is the carrier modulation enable-control bit for CHANNEL3. 1: Add carrier
+ *  modulation in the output signal. 0: No carrier modulation in sig_out.
+ */
+#define RMT_CARRIER_EN_CH3    (BIT(21))
+#define RMT_CARRIER_EN_CH3_M  (RMT_CARRIER_EN_CH3_V << RMT_CARRIER_EN_CH3_S)
+#define RMT_CARRIER_EN_CH3_V  0x00000001U
+#define RMT_CARRIER_EN_CH3_S  21
+/** RMT_CARRIER_OUT_LV_CH3 : R/W; bitpos: [22]; default: 1;
+ *  This bit is used to configure the position of carrier wave for CHANNEL3.1'h0: add
+ *  carrier wave on low level.1'h1: add carrier wave on high level.
+ */
+#define RMT_CARRIER_OUT_LV_CH3    (BIT(22))
+#define RMT_CARRIER_OUT_LV_CH3_M  (RMT_CARRIER_OUT_LV_CH3_V << RMT_CARRIER_OUT_LV_CH3_S)
+#define RMT_CARRIER_OUT_LV_CH3_V  0x00000001U
+#define RMT_CARRIER_OUT_LV_CH3_S  22
+/** RMT_CONF_UPDATE_CH3 : WT; bitpos: [24]; default: 0;
+ *  synchronization bit for CHANNEL3
+ */
+#define RMT_CONF_UPDATE_CH3    (BIT(24))
+#define RMT_CONF_UPDATE_CH3_M  (RMT_CONF_UPDATE_CH3_V << RMT_CONF_UPDATE_CH3_S)
+#define RMT_CONF_UPDATE_CH3_V  0x00000001U
+#define RMT_CONF_UPDATE_CH3_S  24
+
+/** RMT_CH4CONF0_REG register
+ *  Channel 4 configure register 0
+ */
+#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x30)
+/** RMT_DIV_CNT_CH4 : R/W; bitpos: [7:0]; default: 2;
+ *  This register is used to configure the divider for clock of CHANNEL4.
+ */
+#define RMT_DIV_CNT_CH4    0x000000FFU
+#define RMT_DIV_CNT_CH4_M  (RMT_DIV_CNT_CH4_V << RMT_DIV_CNT_CH4_S)
+#define RMT_DIV_CNT_CH4_V  0x000000FFU
+#define RMT_DIV_CNT_CH4_S  0
+/** RMT_IDLE_THRES_CH4 : R/W; bitpos: [22:8]; default: 32767;
+ *  When no edge is detected on the input signal and continuous clock cycles is longer
+ *  than this register value, received process is finished.
+ */
+#define RMT_IDLE_THRES_CH4    0x00007FFFU
+#define RMT_IDLE_THRES_CH4_M  (RMT_IDLE_THRES_CH4_V << RMT_IDLE_THRES_CH4_S)
+#define RMT_IDLE_THRES_CH4_V  0x00007FFFU
+#define RMT_IDLE_THRES_CH4_S  8
+/** RMT_MEM_SIZE_CH4 : R/W; bitpos: [27:24]; default: 1;
+ *  This register is used to configure the maximum size of memory allocated to CHANNEL4.
+ */
+#define RMT_MEM_SIZE_CH4    0x0000000FU
+#define RMT_MEM_SIZE_CH4_M  (RMT_MEM_SIZE_CH4_V << RMT_MEM_SIZE_CH4_S)
+#define RMT_MEM_SIZE_CH4_V  0x0000000FU
+#define RMT_MEM_SIZE_CH4_S  24
+/** RMT_CARRIER_EN_CH4 : R/W; bitpos: [28]; default: 1;
+ *  This is the carrier modulation enable-control bit for CHANNEL4. 1: Add carrier
+ *  modulation in the output signal. 0: No carrier modulation in sig_out.
+ */
+#define RMT_CARRIER_EN_CH4    (BIT(28))
+#define RMT_CARRIER_EN_CH4_M  (RMT_CARRIER_EN_CH4_V << RMT_CARRIER_EN_CH4_S)
+#define RMT_CARRIER_EN_CH4_V  0x00000001U
+#define RMT_CARRIER_EN_CH4_S  28
+/** RMT_CARRIER_OUT_LV_CH4 : R/W; bitpos: [29]; default: 1;
+ *  This bit is used to configure the position of carrier wave for CHANNEL4.1'h0: add
+ *  carrier wave on low level.1'h1: add carrier wave on high level.
+ */
+#define RMT_CARRIER_OUT_LV_CH4    (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH4_M  (RMT_CARRIER_OUT_LV_CH4_V << RMT_CARRIER_OUT_LV_CH4_S)
+#define RMT_CARRIER_OUT_LV_CH4_V  0x00000001U
+#define RMT_CARRIER_OUT_LV_CH4_S  29
+
+/** RMT_CH4CONF1_REG register
+ *  Channel 4 configure register 1
+ */
+#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x34)
+/** RMT_RX_EN_CH4 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable receiver to receive data on CHANNEL4.
+ */
+#define RMT_RX_EN_CH4    (BIT(0))
+#define RMT_RX_EN_CH4_M  (RMT_RX_EN_CH4_V << RMT_RX_EN_CH4_S)
+#define RMT_RX_EN_CH4_V  0x00000001U
+#define RMT_RX_EN_CH4_S  0
+/** RMT_MEM_WR_RST_CH4 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset write ram address for CHANNEL4 by accessing receiver.
+ */
+#define RMT_MEM_WR_RST_CH4    (BIT(1))
+#define RMT_MEM_WR_RST_CH4_M  (RMT_MEM_WR_RST_CH4_V << RMT_MEM_WR_RST_CH4_S)
+#define RMT_MEM_WR_RST_CH4_V  0x00000001U
+#define RMT_MEM_WR_RST_CH4_S  1
+/** RMT_APB_MEM_RST_CH4 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to reset W/R ram address for CHANNEL4 by accessing apb fifo.
+ */
+#define RMT_APB_MEM_RST_CH4    (BIT(2))
+#define RMT_APB_MEM_RST_CH4_M  (RMT_APB_MEM_RST_CH4_V << RMT_APB_MEM_RST_CH4_S)
+#define RMT_APB_MEM_RST_CH4_V  0x00000001U
+#define RMT_APB_MEM_RST_CH4_S  2
+/** RMT_MEM_OWNER_CH4 : R/W/SC; bitpos: [3]; default: 1;
+ *  This register marks the ownership of CHANNEL4's ram block.1'h1: Receiver is using
+ *  the ram. 1'h0: APB bus is using the ram.
+ */
+#define RMT_MEM_OWNER_CH4    (BIT(3))
+#define RMT_MEM_OWNER_CH4_M  (RMT_MEM_OWNER_CH4_V << RMT_MEM_OWNER_CH4_S)
+#define RMT_MEM_OWNER_CH4_V  0x00000001U
+#define RMT_MEM_OWNER_CH4_S  3
+/** RMT_RX_FILTER_EN_CH4 : R/W; bitpos: [4]; default: 0;
+ *  This is the receive filter's enable bit for CHANNEL4.
+ */
+#define RMT_RX_FILTER_EN_CH4    (BIT(4))
+#define RMT_RX_FILTER_EN_CH4_M  (RMT_RX_FILTER_EN_CH4_V << RMT_RX_FILTER_EN_CH4_S)
+#define RMT_RX_FILTER_EN_CH4_V  0x00000001U
+#define RMT_RX_FILTER_EN_CH4_S  4
+/** RMT_RX_FILTER_THRES_CH4 : R/W; bitpos: [12:5]; default: 15;
+ *  Ignores the input pulse when its width is smaller than this register value in APB
+ *  clock periods (in receive mode).
+ */
+#define RMT_RX_FILTER_THRES_CH4    0x000000FFU
+#define RMT_RX_FILTER_THRES_CH4_M  (RMT_RX_FILTER_THRES_CH4_V << RMT_RX_FILTER_THRES_CH4_S)
+#define RMT_RX_FILTER_THRES_CH4_V  0x000000FFU
+#define RMT_RX_FILTER_THRES_CH4_S  5
+/** RMT_MEM_RX_WRAP_EN_CH4 : R/W; bitpos: [13]; default: 0;
+ *  This is the channel 4 enable bit for wraparound mode: it will resume receiving at
+ *  the start when the data to be received is more than its memory size.
+ */
+#define RMT_MEM_RX_WRAP_EN_CH4    (BIT(13))
+#define RMT_MEM_RX_WRAP_EN_CH4_M  (RMT_MEM_RX_WRAP_EN_CH4_V << RMT_MEM_RX_WRAP_EN_CH4_S)
+#define RMT_MEM_RX_WRAP_EN_CH4_V  0x00000001U
+#define RMT_MEM_RX_WRAP_EN_CH4_S  13
+/** RMT_CONF_UPDATE_CH4 : WT; bitpos: [15]; default: 0;
+ *  synchronization bit for CHANNEL4
+ */
+#define RMT_CONF_UPDATE_CH4    (BIT(15))
+#define RMT_CONF_UPDATE_CH4_M  (RMT_CONF_UPDATE_CH4_V << RMT_CONF_UPDATE_CH4_S)
+#define RMT_CONF_UPDATE_CH4_V  0x00000001U
+#define RMT_CONF_UPDATE_CH4_S  15
+
+/** RMT_CH5CONF0_REG register
+ *  Channel 5 configure register 0
+ */
+#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x38)
+/** RMT_DIV_CNT_CH5 : R/W; bitpos: [7:0]; default: 2;
+ *  This register is used to configure the divider for clock of CHANNEL5.
+ */
+#define RMT_DIV_CNT_CH5    0x000000FFU
+#define RMT_DIV_CNT_CH5_M  (RMT_DIV_CNT_CH5_V << RMT_DIV_CNT_CH5_S)
+#define RMT_DIV_CNT_CH5_V  0x000000FFU
+#define RMT_DIV_CNT_CH5_S  0
+/** RMT_IDLE_THRES_CH5 : R/W; bitpos: [22:8]; default: 32767;
+ *  When no edge is detected on the input signal and continuous clock cycles is longer
+ *  than this register value, received process is finished.
+ */
+#define RMT_IDLE_THRES_CH5    0x00007FFFU
+#define RMT_IDLE_THRES_CH5_M  (RMT_IDLE_THRES_CH5_V << RMT_IDLE_THRES_CH5_S)
+#define RMT_IDLE_THRES_CH5_V  0x00007FFFU
+#define RMT_IDLE_THRES_CH5_S  8
+/** RMT_MEM_SIZE_CH5 : R/W; bitpos: [27:24]; default: 1;
+ *  This register is used to configure the maximum size of memory allocated to CHANNEL5.
+ */
+#define RMT_MEM_SIZE_CH5    0x0000000FU
+#define RMT_MEM_SIZE_CH5_M  (RMT_MEM_SIZE_CH5_V << RMT_MEM_SIZE_CH5_S)
+#define RMT_MEM_SIZE_CH5_V  0x0000000FU
+#define RMT_MEM_SIZE_CH5_S  24
+/** RMT_CARRIER_EN_CH5 : R/W; bitpos: [28]; default: 1;
+ *  This is the carrier modulation enable-control bit for CHANNEL5. 1: Add carrier
+ *  modulation in the output signal. 0: No carrier modulation in sig_out.
+ */
+#define RMT_CARRIER_EN_CH5    (BIT(28))
+#define RMT_CARRIER_EN_CH5_M  (RMT_CARRIER_EN_CH5_V << RMT_CARRIER_EN_CH5_S)
+#define RMT_CARRIER_EN_CH5_V  0x00000001U
+#define RMT_CARRIER_EN_CH5_S  28
+/** RMT_CARRIER_OUT_LV_CH5 : R/W; bitpos: [29]; default: 1;
+ *  This bit is used to configure the position of carrier wave for CHANNEL5.1'h0: add
+ *  carrier wave on low level.1'h1: add carrier wave on high level.
+ */
+#define RMT_CARRIER_OUT_LV_CH5    (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH5_M  (RMT_CARRIER_OUT_LV_CH5_V << RMT_CARRIER_OUT_LV_CH5_S)
+#define RMT_CARRIER_OUT_LV_CH5_V  0x00000001U
+#define RMT_CARRIER_OUT_LV_CH5_S  29
+
+/** RMT_CH5CONF1_REG register
+ *  Channel 5 configure register 1
+ */
+#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x3c)
+/** RMT_RX_EN_CH5 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable receiver to receive data on CHANNEL5.
+ */
+#define RMT_RX_EN_CH5    (BIT(0))
+#define RMT_RX_EN_CH5_M  (RMT_RX_EN_CH5_V << RMT_RX_EN_CH5_S)
+#define RMT_RX_EN_CH5_V  0x00000001U
+#define RMT_RX_EN_CH5_S  0
+/** RMT_MEM_WR_RST_CH5 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset write ram address for CHANNEL5 by accessing receiver.
+ */
+#define RMT_MEM_WR_RST_CH5    (BIT(1))
+#define RMT_MEM_WR_RST_CH5_M  (RMT_MEM_WR_RST_CH5_V << RMT_MEM_WR_RST_CH5_S)
+#define RMT_MEM_WR_RST_CH5_V  0x00000001U
+#define RMT_MEM_WR_RST_CH5_S  1
+/** RMT_APB_MEM_RST_CH5 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to reset W/R ram address for CHANNEL5 by accessing apb fifo.
+ */
+#define RMT_APB_MEM_RST_CH5    (BIT(2))
+#define RMT_APB_MEM_RST_CH5_M  (RMT_APB_MEM_RST_CH5_V << RMT_APB_MEM_RST_CH5_S)
+#define RMT_APB_MEM_RST_CH5_V  0x00000001U
+#define RMT_APB_MEM_RST_CH5_S  2
+/** RMT_MEM_OWNER_CH5 : R/W/SC; bitpos: [3]; default: 1;
+ *  This register marks the ownership of CHANNEL5's ram block.1'h1: Receiver is using
+ *  the ram. 1'h0: APB bus is using the ram.
+ */
+#define RMT_MEM_OWNER_CH5    (BIT(3))
+#define RMT_MEM_OWNER_CH5_M  (RMT_MEM_OWNER_CH5_V << RMT_MEM_OWNER_CH5_S)
+#define RMT_MEM_OWNER_CH5_V  0x00000001U
+#define RMT_MEM_OWNER_CH5_S  3
+/** RMT_RX_FILTER_EN_CH5 : R/W; bitpos: [4]; default: 0;
+ *  This is the receive filter's enable bit for CHANNEL5.
+ */
+#define RMT_RX_FILTER_EN_CH5    (BIT(4))
+#define RMT_RX_FILTER_EN_CH5_M  (RMT_RX_FILTER_EN_CH5_V << RMT_RX_FILTER_EN_CH5_S)
+#define RMT_RX_FILTER_EN_CH5_V  0x00000001U
+#define RMT_RX_FILTER_EN_CH5_S  4
+/** RMT_RX_FILTER_THRES_CH5 : R/W; bitpos: [12:5]; default: 15;
+ *  Ignores the input pulse when its width is smaller than this register value in APB
+ *  clock periods (in receive mode).
+ */
+#define RMT_RX_FILTER_THRES_CH5    0x000000FFU
+#define RMT_RX_FILTER_THRES_CH5_M  (RMT_RX_FILTER_THRES_CH5_V << RMT_RX_FILTER_THRES_CH5_S)
+#define RMT_RX_FILTER_THRES_CH5_V  0x000000FFU
+#define RMT_RX_FILTER_THRES_CH5_S  5
+/** RMT_MEM_RX_WRAP_EN_CH5 : R/W; bitpos: [13]; default: 0;
+ *  This is the channel 5 enable bit for wraparound mode: it will resume receiving at
+ *  the start when the data to be received is more than its memory size.
+ */
+#define RMT_MEM_RX_WRAP_EN_CH5    (BIT(13))
+#define RMT_MEM_RX_WRAP_EN_CH5_M  (RMT_MEM_RX_WRAP_EN_CH5_V << RMT_MEM_RX_WRAP_EN_CH5_S)
+#define RMT_MEM_RX_WRAP_EN_CH5_V  0x00000001U
+#define RMT_MEM_RX_WRAP_EN_CH5_S  13
+/** RMT_CONF_UPDATE_CH5 : WT; bitpos: [15]; default: 0;
+ *  synchronization bit for CHANNEL5
+ */
+#define RMT_CONF_UPDATE_CH5    (BIT(15))
+#define RMT_CONF_UPDATE_CH5_M  (RMT_CONF_UPDATE_CH5_V << RMT_CONF_UPDATE_CH5_S)
+#define RMT_CONF_UPDATE_CH5_V  0x00000001U
+#define RMT_CONF_UPDATE_CH5_S  15
+
+/** RMT_CH6CONF0_REG register
+ *  Channel 6 configure register 0
+ */
+#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x40)
+/** RMT_DIV_CNT_CH6 : R/W; bitpos: [7:0]; default: 2;
+ *  This register is used to configure the divider for clock of CHANNEL6.
+ */
+#define RMT_DIV_CNT_CH6    0x000000FFU
+#define RMT_DIV_CNT_CH6_M  (RMT_DIV_CNT_CH6_V << RMT_DIV_CNT_CH6_S)
+#define RMT_DIV_CNT_CH6_V  0x000000FFU
+#define RMT_DIV_CNT_CH6_S  0
+/** RMT_IDLE_THRES_CH6 : R/W; bitpos: [22:8]; default: 32767;
+ *  When no edge is detected on the input signal and continuous clock cycles is longer
+ *  than this register value, received process is finished.
+ */
+#define RMT_IDLE_THRES_CH6    0x00007FFFU
+#define RMT_IDLE_THRES_CH6_M  (RMT_IDLE_THRES_CH6_V << RMT_IDLE_THRES_CH6_S)
+#define RMT_IDLE_THRES_CH6_V  0x00007FFFU
+#define RMT_IDLE_THRES_CH6_S  8
+/** RMT_MEM_SIZE_CH6 : R/W; bitpos: [27:24]; default: 1;
+ *  This register is used to configure the maximum size of memory allocated to CHANNEL6.
+ */
+#define RMT_MEM_SIZE_CH6    0x0000000FU
+#define RMT_MEM_SIZE_CH6_M  (RMT_MEM_SIZE_CH6_V << RMT_MEM_SIZE_CH6_S)
+#define RMT_MEM_SIZE_CH6_V  0x0000000FU
+#define RMT_MEM_SIZE_CH6_S  24
+/** RMT_CARRIER_EN_CH6 : R/W; bitpos: [28]; default: 1;
+ *  This is the carrier modulation enable-control bit for CHANNEL6. 1: Add carrier
+ *  modulation in the output signal. 0: No carrier modulation in sig_out.
+ */
+#define RMT_CARRIER_EN_CH6    (BIT(28))
+#define RMT_CARRIER_EN_CH6_M  (RMT_CARRIER_EN_CH6_V << RMT_CARRIER_EN_CH6_S)
+#define RMT_CARRIER_EN_CH6_V  0x00000001U
+#define RMT_CARRIER_EN_CH6_S  28
+/** RMT_CARRIER_OUT_LV_CH6 : R/W; bitpos: [29]; default: 1;
+ *  This bit is used to configure the position of carrier wave for CHANNEL6.1'h0: add
+ *  carrier wave on low level.1'h1: add carrier wave on high level.
+ */
+#define RMT_CARRIER_OUT_LV_CH6    (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH6_M  (RMT_CARRIER_OUT_LV_CH6_V << RMT_CARRIER_OUT_LV_CH6_S)
+#define RMT_CARRIER_OUT_LV_CH6_V  0x00000001U
+#define RMT_CARRIER_OUT_LV_CH6_S  29
+
+/** RMT_CH6CONF1_REG register
+ *  Channel 6 configure register 1
+ */
+#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x44)
+/** RMT_RX_EN_CH6 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable receiver to receive data on CHANNEL6.
+ */
+#define RMT_RX_EN_CH6    (BIT(0))
+#define RMT_RX_EN_CH6_M  (RMT_RX_EN_CH6_V << RMT_RX_EN_CH6_S)
+#define RMT_RX_EN_CH6_V  0x00000001U
+#define RMT_RX_EN_CH6_S  0
+/** RMT_MEM_WR_RST_CH6 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset write ram address for CHANNEL6 by accessing receiver.
+ */
+#define RMT_MEM_WR_RST_CH6    (BIT(1))
+#define RMT_MEM_WR_RST_CH6_M  (RMT_MEM_WR_RST_CH6_V << RMT_MEM_WR_RST_CH6_S)
+#define RMT_MEM_WR_RST_CH6_V  0x00000001U
+#define RMT_MEM_WR_RST_CH6_S  1
+/** RMT_APB_MEM_RST_CH6 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to reset W/R ram address for CHANNEL6 by accessing apb fifo.
+ */
+#define RMT_APB_MEM_RST_CH6    (BIT(2))
+#define RMT_APB_MEM_RST_CH6_M  (RMT_APB_MEM_RST_CH6_V << RMT_APB_MEM_RST_CH6_S)
+#define RMT_APB_MEM_RST_CH6_V  0x00000001U
+#define RMT_APB_MEM_RST_CH6_S  2
+/** RMT_MEM_OWNER_CH6 : R/W/SC; bitpos: [3]; default: 1;
+ *  This register marks the ownership of CHANNEL6's ram block.1'h1: Receiver is using
+ *  the ram. 1'h0: APB bus is using the ram.
+ */
+#define RMT_MEM_OWNER_CH6    (BIT(3))
+#define RMT_MEM_OWNER_CH6_M  (RMT_MEM_OWNER_CH6_V << RMT_MEM_OWNER_CH6_S)
+#define RMT_MEM_OWNER_CH6_V  0x00000001U
+#define RMT_MEM_OWNER_CH6_S  3
+/** RMT_RX_FILTER_EN_CH6 : R/W; bitpos: [4]; default: 0;
+ *  This is the receive filter's enable bit for CHANNEL6.
+ */
+#define RMT_RX_FILTER_EN_CH6    (BIT(4))
+#define RMT_RX_FILTER_EN_CH6_M  (RMT_RX_FILTER_EN_CH6_V << RMT_RX_FILTER_EN_CH6_S)
+#define RMT_RX_FILTER_EN_CH6_V  0x00000001U
+#define RMT_RX_FILTER_EN_CH6_S  4
+/** RMT_RX_FILTER_THRES_CH6 : R/W; bitpos: [12:5]; default: 15;
+ *  Ignores the input pulse when its width is smaller than this register value in APB
+ *  clock periods (in receive mode).
+ */
+#define RMT_RX_FILTER_THRES_CH6    0x000000FFU
+#define RMT_RX_FILTER_THRES_CH6_M  (RMT_RX_FILTER_THRES_CH6_V << RMT_RX_FILTER_THRES_CH6_S)
+#define RMT_RX_FILTER_THRES_CH6_V  0x000000FFU
+#define RMT_RX_FILTER_THRES_CH6_S  5
+/** RMT_MEM_RX_WRAP_EN_CH6 : R/W; bitpos: [13]; default: 0;
+ *  This is the channel 6 enable bit for wraparound mode: it will resume receiving at
+ *  the start when the data to be received is more than its memory size.
+ */
+#define RMT_MEM_RX_WRAP_EN_CH6    (BIT(13))
+#define RMT_MEM_RX_WRAP_EN_CH6_M  (RMT_MEM_RX_WRAP_EN_CH6_V << RMT_MEM_RX_WRAP_EN_CH6_S)
+#define RMT_MEM_RX_WRAP_EN_CH6_V  0x00000001U
+#define RMT_MEM_RX_WRAP_EN_CH6_S  13
+/** RMT_CONF_UPDATE_CH6 : WT; bitpos: [15]; default: 0;
+ *  synchronization bit for CHANNEL6
+ */
+#define RMT_CONF_UPDATE_CH6    (BIT(15))
+#define RMT_CONF_UPDATE_CH6_M  (RMT_CONF_UPDATE_CH6_V << RMT_CONF_UPDATE_CH6_S)
+#define RMT_CONF_UPDATE_CH6_V  0x00000001U
+#define RMT_CONF_UPDATE_CH6_S  15
+
+/** RMT_CH7CONF0_REG register
+ *  Channel 7 configure register 0
+ */
+#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x48)
+/** RMT_DIV_CNT_CH7 : R/W; bitpos: [7:0]; default: 2;
+ *  This register is used to configure the divider for clock of CHANNEL7.
+ */
+#define RMT_DIV_CNT_CH7    0x000000FFU
+#define RMT_DIV_CNT_CH7_M  (RMT_DIV_CNT_CH7_V << RMT_DIV_CNT_CH7_S)
+#define RMT_DIV_CNT_CH7_V  0x000000FFU
+#define RMT_DIV_CNT_CH7_S  0
+/** RMT_IDLE_THRES_CH7 : R/W; bitpos: [22:8]; default: 32767;
+ *  When no edge is detected on the input signal and continuous clock cycles is longer
+ *  than this register value, received process is finished.
+ */
+#define RMT_IDLE_THRES_CH7    0x00007FFFU
+#define RMT_IDLE_THRES_CH7_M  (RMT_IDLE_THRES_CH7_V << RMT_IDLE_THRES_CH7_S)
+#define RMT_IDLE_THRES_CH7_V  0x00007FFFU
+#define RMT_IDLE_THRES_CH7_S  8
+/** RMT_MEM_SIZE_CH7 : R/W; bitpos: [27:24]; default: 1;
+ *  This register is used to configure the maximum size of memory allocated to CHANNEL7.
+ */
+#define RMT_MEM_SIZE_CH7    0x0000000FU
+#define RMT_MEM_SIZE_CH7_M  (RMT_MEM_SIZE_CH7_V << RMT_MEM_SIZE_CH7_S)
+#define RMT_MEM_SIZE_CH7_V  0x0000000FU
+#define RMT_MEM_SIZE_CH7_S  24
+/** RMT_CARRIER_EN_CH7 : R/W; bitpos: [28]; default: 1;
+ *  This is the carrier modulation enable-control bit for CHANNEL7. 1: Add carrier
+ *  modulation in the output signal. 0: No carrier modulation in sig_out.
+ */
+#define RMT_CARRIER_EN_CH7    (BIT(28))
+#define RMT_CARRIER_EN_CH7_M  (RMT_CARRIER_EN_CH7_V << RMT_CARRIER_EN_CH7_S)
+#define RMT_CARRIER_EN_CH7_V  0x00000001U
+#define RMT_CARRIER_EN_CH7_S  28
+/** RMT_CARRIER_OUT_LV_CH7 : R/W; bitpos: [29]; default: 1;
+ *  This bit is used to configure the position of carrier wave for CHANNEL7.1'h0: add
+ *  carrier wave on low level.1'h1: add carrier wave on high level.
+ */
+#define RMT_CARRIER_OUT_LV_CH7    (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH7_M  (RMT_CARRIER_OUT_LV_CH7_V << RMT_CARRIER_OUT_LV_CH7_S)
+#define RMT_CARRIER_OUT_LV_CH7_V  0x00000001U
+#define RMT_CARRIER_OUT_LV_CH7_S  29
+
+/** RMT_CH7CONF1_REG register
+ *  Channel 7 configure register 1
+ */
+#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x4c)
+/** RMT_RX_EN_CH7 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable receiver to receive data on CHANNEL7.
+ */
+#define RMT_RX_EN_CH7    (BIT(0))
+#define RMT_RX_EN_CH7_M  (RMT_RX_EN_CH7_V << RMT_RX_EN_CH7_S)
+#define RMT_RX_EN_CH7_V  0x00000001U
+#define RMT_RX_EN_CH7_S  0
+/** RMT_MEM_WR_RST_CH7 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset write ram address for CHANNEL7 by accessing receiver.
+ */
+#define RMT_MEM_WR_RST_CH7    (BIT(1))
+#define RMT_MEM_WR_RST_CH7_M  (RMT_MEM_WR_RST_CH7_V << RMT_MEM_WR_RST_CH7_S)
+#define RMT_MEM_WR_RST_CH7_V  0x00000001U
+#define RMT_MEM_WR_RST_CH7_S  1
+/** RMT_APB_MEM_RST_CH7 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to reset W/R ram address for CHANNEL7 by accessing apb fifo.
+ */
+#define RMT_APB_MEM_RST_CH7    (BIT(2))
+#define RMT_APB_MEM_RST_CH7_M  (RMT_APB_MEM_RST_CH7_V << RMT_APB_MEM_RST_CH7_S)
+#define RMT_APB_MEM_RST_CH7_V  0x00000001U
+#define RMT_APB_MEM_RST_CH7_S  2
+/** RMT_MEM_OWNER_CH7 : R/W/SC; bitpos: [3]; default: 1;
+ *  This register marks the ownership of CHANNEL7's ram block.1'h1: Receiver is using
+ *  the ram. 1'h0: APB bus is using the ram.
+ */
+#define RMT_MEM_OWNER_CH7    (BIT(3))
+#define RMT_MEM_OWNER_CH7_M  (RMT_MEM_OWNER_CH7_V << RMT_MEM_OWNER_CH7_S)
+#define RMT_MEM_OWNER_CH7_V  0x00000001U
+#define RMT_MEM_OWNER_CH7_S  3
+/** RMT_RX_FILTER_EN_CH7 : R/W; bitpos: [4]; default: 0;
+ *  This is the receive filter's enable bit for CHANNEL7.
+ */
+#define RMT_RX_FILTER_EN_CH7    (BIT(4))
+#define RMT_RX_FILTER_EN_CH7_M  (RMT_RX_FILTER_EN_CH7_V << RMT_RX_FILTER_EN_CH7_S)
+#define RMT_RX_FILTER_EN_CH7_V  0x00000001U
+#define RMT_RX_FILTER_EN_CH7_S  4
+/** RMT_RX_FILTER_THRES_CH7 : R/W; bitpos: [12:5]; default: 15;
+ *  Ignores the input pulse when its width is smaller than this register value in APB
+ *  clock periods (in receive mode).
+ */
+#define RMT_RX_FILTER_THRES_CH7    0x000000FFU
+#define RMT_RX_FILTER_THRES_CH7_M  (RMT_RX_FILTER_THRES_CH7_V << RMT_RX_FILTER_THRES_CH7_S)
+#define RMT_RX_FILTER_THRES_CH7_V  0x000000FFU
+#define RMT_RX_FILTER_THRES_CH7_S  5
+/** RMT_MEM_RX_WRAP_EN_CH7 : R/W; bitpos: [13]; default: 0;
+ *  This is the channel 7 enable bit for wraparound mode: it will resume receiving at
+ *  the start when the data to be received is more than its memory size.
+ */
+#define RMT_MEM_RX_WRAP_EN_CH7    (BIT(13))
+#define RMT_MEM_RX_WRAP_EN_CH7_M  (RMT_MEM_RX_WRAP_EN_CH7_V << RMT_MEM_RX_WRAP_EN_CH7_S)
+#define RMT_MEM_RX_WRAP_EN_CH7_V  0x00000001U
+#define RMT_MEM_RX_WRAP_EN_CH7_S  13
+/** RMT_CONF_UPDATE_CH7 : WT; bitpos: [15]; default: 0;
+ *  synchronization bit for CHANNEL7
+ */
+#define RMT_CONF_UPDATE_CH7    (BIT(15))
+#define RMT_CONF_UPDATE_CH7_M  (RMT_CONF_UPDATE_CH7_V << RMT_CONF_UPDATE_CH7_S)
+#define RMT_CONF_UPDATE_CH7_V  0x00000001U
+#define RMT_CONF_UPDATE_CH7_S  15
+
+/** RMT_CH0STATUS_REG register
+ *  Channel 0 status register
+ */
+#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x50)
+/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [9:0]; default: 0;
+ *  This register records the memory address offset when transmitter of CHANNEL0 is
+ *  using the RAM.
+ */
+#define RMT_MEM_RADDR_EX_CH0    0x000003FFU
+#define RMT_MEM_RADDR_EX_CH0_M  (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S)
+#define RMT_MEM_RADDR_EX_CH0_V  0x000003FFU
+#define RMT_MEM_RADDR_EX_CH0_S  0
+/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [20:11]; default: 0;
+ *  This register records the memory address offset when writes RAM over APB bus.
+ */
+#define RMT_APB_MEM_WADDR_CH0    0x000003FFU
+#define RMT_APB_MEM_WADDR_CH0_M  (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S)
+#define RMT_APB_MEM_WADDR_CH0_V  0x000003FFU
+#define RMT_APB_MEM_WADDR_CH0_S  11
+/** RMT_STATE_CH0 : RO; bitpos: [24:22]; default: 0;
+ *  This register records the FSM status of CHANNEL0.
+ */
+#define RMT_STATE_CH0    0x00000007U
+#define RMT_STATE_CH0_M  (RMT_STATE_CH0_V << RMT_STATE_CH0_S)
+#define RMT_STATE_CH0_V  0x00000007U
+#define RMT_STATE_CH0_S  22
+/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [25]; default: 0;
+ *  This status bit will be set when the data to be set is more than memory size and
+ *  the wraparound mode is disabled.
+ */
+#define RMT_MEM_EMPTY_CH0    (BIT(25))
+#define RMT_MEM_EMPTY_CH0_M  (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S)
+#define RMT_MEM_EMPTY_CH0_V  0x00000001U
+#define RMT_MEM_EMPTY_CH0_S  25
+/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [26]; default: 0;
+ *  This status bit will be set if the offset address out of memory size when writes
+ *  via APB bus.
+ */
+#define RMT_APB_MEM_WR_ERR_CH0    (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH0_M  (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S)
+#define RMT_APB_MEM_WR_ERR_CH0_V  0x00000001U
+#define RMT_APB_MEM_WR_ERR_CH0_S  26
+
+/** RMT_CH1STATUS_REG register
+ *  Channel 1 status register
+ */
+#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x54)
+/** RMT_MEM_RADDR_EX_CH1 : RO; bitpos: [9:0]; default: 0;
+ *  This register records the memory address offset when transmitter of CHANNEL1 is
+ *  using the RAM.
+ */
+#define RMT_MEM_RADDR_EX_CH1    0x000003FFU
+#define RMT_MEM_RADDR_EX_CH1_M  (RMT_MEM_RADDR_EX_CH1_V << RMT_MEM_RADDR_EX_CH1_S)
+#define RMT_MEM_RADDR_EX_CH1_V  0x000003FFU
+#define RMT_MEM_RADDR_EX_CH1_S  0
+/** RMT_APB_MEM_WADDR_CH1 : RO; bitpos: [20:11]; default: 0;
+ *  This register records the memory address offset when writes RAM over APB bus.
+ */
+#define RMT_APB_MEM_WADDR_CH1    0x000003FFU
+#define RMT_APB_MEM_WADDR_CH1_M  (RMT_APB_MEM_WADDR_CH1_V << RMT_APB_MEM_WADDR_CH1_S)
+#define RMT_APB_MEM_WADDR_CH1_V  0x000003FFU
+#define RMT_APB_MEM_WADDR_CH1_S  11
+/** RMT_STATE_CH1 : RO; bitpos: [24:22]; default: 0;
+ *  This register records the FSM status of CHANNEL1.
+ */
+#define RMT_STATE_CH1    0x00000007U
+#define RMT_STATE_CH1_M  (RMT_STATE_CH1_V << RMT_STATE_CH1_S)
+#define RMT_STATE_CH1_V  0x00000007U
+#define RMT_STATE_CH1_S  22
+/** RMT_MEM_EMPTY_CH1 : RO; bitpos: [25]; default: 0;
+ *  This status bit will be set when the data to be set is more than memory size and
+ *  the wraparound mode is disabled.
+ */
+#define RMT_MEM_EMPTY_CH1    (BIT(25))
+#define RMT_MEM_EMPTY_CH1_M  (RMT_MEM_EMPTY_CH1_V << RMT_MEM_EMPTY_CH1_S)
+#define RMT_MEM_EMPTY_CH1_V  0x00000001U
+#define RMT_MEM_EMPTY_CH1_S  25
+/** RMT_APB_MEM_WR_ERR_CH1 : RO; bitpos: [26]; default: 0;
+ *  This status bit will be set if the offset address out of memory size when writes
+ *  via APB bus.
+ */
+#define RMT_APB_MEM_WR_ERR_CH1    (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH1_M  (RMT_APB_MEM_WR_ERR_CH1_V << RMT_APB_MEM_WR_ERR_CH1_S)
+#define RMT_APB_MEM_WR_ERR_CH1_V  0x00000001U
+#define RMT_APB_MEM_WR_ERR_CH1_S  26
+
+/** RMT_CH2STATUS_REG register
+ *  Channel 2 status register
+ */
+#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x58)
+/** RMT_MEM_RADDR_EX_CH2 : RO; bitpos: [9:0]; default: 0;
+ *  This register records the memory address offset when transmitter of CHANNEL2 is
+ *  using the RAM.
+ */
+#define RMT_MEM_RADDR_EX_CH2    0x000003FFU
+#define RMT_MEM_RADDR_EX_CH2_M  (RMT_MEM_RADDR_EX_CH2_V << RMT_MEM_RADDR_EX_CH2_S)
+#define RMT_MEM_RADDR_EX_CH2_V  0x000003FFU
+#define RMT_MEM_RADDR_EX_CH2_S  0
+/** RMT_APB_MEM_WADDR_CH2 : RO; bitpos: [20:11]; default: 0;
+ *  This register records the memory address offset when writes RAM over APB bus.
+ */
+#define RMT_APB_MEM_WADDR_CH2    0x000003FFU
+#define RMT_APB_MEM_WADDR_CH2_M  (RMT_APB_MEM_WADDR_CH2_V << RMT_APB_MEM_WADDR_CH2_S)
+#define RMT_APB_MEM_WADDR_CH2_V  0x000003FFU
+#define RMT_APB_MEM_WADDR_CH2_S  11
+/** RMT_STATE_CH2 : RO; bitpos: [24:22]; default: 0;
+ *  This register records the FSM status of CHANNEL2.
+ */
+#define RMT_STATE_CH2    0x00000007U
+#define RMT_STATE_CH2_M  (RMT_STATE_CH2_V << RMT_STATE_CH2_S)
+#define RMT_STATE_CH2_V  0x00000007U
+#define RMT_STATE_CH2_S  22
+/** RMT_MEM_EMPTY_CH2 : RO; bitpos: [25]; default: 0;
+ *  This status bit will be set when the data to be set is more than memory size and
+ *  the wraparound mode is disabled.
+ */
+#define RMT_MEM_EMPTY_CH2    (BIT(25))
+#define RMT_MEM_EMPTY_CH2_M  (RMT_MEM_EMPTY_CH2_V << RMT_MEM_EMPTY_CH2_S)
+#define RMT_MEM_EMPTY_CH2_V  0x00000001U
+#define RMT_MEM_EMPTY_CH2_S  25
+/** RMT_APB_MEM_WR_ERR_CH2 : RO; bitpos: [26]; default: 0;
+ *  This status bit will be set if the offset address out of memory size when writes
+ *  via APB bus.
+ */
+#define RMT_APB_MEM_WR_ERR_CH2    (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH2_M  (RMT_APB_MEM_WR_ERR_CH2_V << RMT_APB_MEM_WR_ERR_CH2_S)
+#define RMT_APB_MEM_WR_ERR_CH2_V  0x00000001U
+#define RMT_APB_MEM_WR_ERR_CH2_S  26
+
+/** RMT_CH3STATUS_REG register
+ *  Channel 3 status register
+ */
+#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x5c)
+/** RMT_MEM_RADDR_EX_CH3 : RO; bitpos: [9:0]; default: 0;
+ *  This register records the memory address offset when transmitter of CHANNEL3 is
+ *  using the RAM.
+ */
+#define RMT_MEM_RADDR_EX_CH3    0x000003FFU
+#define RMT_MEM_RADDR_EX_CH3_M  (RMT_MEM_RADDR_EX_CH3_V << RMT_MEM_RADDR_EX_CH3_S)
+#define RMT_MEM_RADDR_EX_CH3_V  0x000003FFU
+#define RMT_MEM_RADDR_EX_CH3_S  0
+/** RMT_APB_MEM_WADDR_CH3 : RO; bitpos: [20:11]; default: 0;
+ *  This register records the memory address offset when writes RAM over APB bus.
+ */
+#define RMT_APB_MEM_WADDR_CH3    0x000003FFU
+#define RMT_APB_MEM_WADDR_CH3_M  (RMT_APB_MEM_WADDR_CH3_V << RMT_APB_MEM_WADDR_CH3_S)
+#define RMT_APB_MEM_WADDR_CH3_V  0x000003FFU
+#define RMT_APB_MEM_WADDR_CH3_S  11
+/** RMT_STATE_CH3 : RO; bitpos: [24:22]; default: 0;
+ *  This register records the FSM status of CHANNEL3.
+ */
+#define RMT_STATE_CH3    0x00000007U
+#define RMT_STATE_CH3_M  (RMT_STATE_CH3_V << RMT_STATE_CH3_S)
+#define RMT_STATE_CH3_V  0x00000007U
+#define RMT_STATE_CH3_S  22
+/** RMT_MEM_EMPTY_CH3 : RO; bitpos: [25]; default: 0;
+ *  This status bit will be set when the data to be set is more than memory size and
+ *  the wraparound mode is disabled.
+ */
+#define RMT_MEM_EMPTY_CH3    (BIT(25))
+#define RMT_MEM_EMPTY_CH3_M  (RMT_MEM_EMPTY_CH3_V << RMT_MEM_EMPTY_CH3_S)
+#define RMT_MEM_EMPTY_CH3_V  0x00000001U
+#define RMT_MEM_EMPTY_CH3_S  25
+/** RMT_APB_MEM_WR_ERR_CH3 : RO; bitpos: [26]; default: 0;
+ *  This status bit will be set if the offset address out of memory size when writes
+ *  via APB bus.
+ */
+#define RMT_APB_MEM_WR_ERR_CH3    (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH3_M  (RMT_APB_MEM_WR_ERR_CH3_V << RMT_APB_MEM_WR_ERR_CH3_S)
+#define RMT_APB_MEM_WR_ERR_CH3_V  0x00000001U
+#define RMT_APB_MEM_WR_ERR_CH3_S  26
+
+/** RMT_CH4STATUS_REG register
+ *  Channel 4 status register
+ */
+#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x60)
+/** RMT_MEM_WADDR_EX_CH4 : RO; bitpos: [9:0]; default: 192;
+ *  This register records the memory address offset when receiver of CHANNEL4 is using
+ *  the RAM.
+ */
+#define RMT_MEM_WADDR_EX_CH4    0x000003FFU
+#define RMT_MEM_WADDR_EX_CH4_M  (RMT_MEM_WADDR_EX_CH4_V << RMT_MEM_WADDR_EX_CH4_S)
+#define RMT_MEM_WADDR_EX_CH4_V  0x000003FFU
+#define RMT_MEM_WADDR_EX_CH4_S  0
+/** RMT_APB_MEM_RADDR_CH4 : RO; bitpos: [20:11]; default: 192;
+ *  This register records the memory address offset when reads RAM over APB bus.
+ */
+#define RMT_APB_MEM_RADDR_CH4    0x000003FFU
+#define RMT_APB_MEM_RADDR_CH4_M  (RMT_APB_MEM_RADDR_CH4_V << RMT_APB_MEM_RADDR_CH4_S)
+#define RMT_APB_MEM_RADDR_CH4_V  0x000003FFU
+#define RMT_APB_MEM_RADDR_CH4_S  11
+/** RMT_STATE_CH4 : RO; bitpos: [24:22]; default: 0;
+ *  This register records the FSM status of CHANNEL4.
+ */
+#define RMT_STATE_CH4    0x00000007U
+#define RMT_STATE_CH4_M  (RMT_STATE_CH4_V << RMT_STATE_CH4_S)
+#define RMT_STATE_CH4_V  0x00000007U
+#define RMT_STATE_CH4_S  22
+/** RMT_MEM_OWNER_ERR_CH4 : RO; bitpos: [25]; default: 0;
+ *  This status bit will be set when the ownership of memory block is wrong.
+ */
+#define RMT_MEM_OWNER_ERR_CH4    (BIT(25))
+#define RMT_MEM_OWNER_ERR_CH4_M  (RMT_MEM_OWNER_ERR_CH4_V << RMT_MEM_OWNER_ERR_CH4_S)
+#define RMT_MEM_OWNER_ERR_CH4_V  0x00000001U
+#define RMT_MEM_OWNER_ERR_CH4_S  25
+/** RMT_MEM_FULL_CH4 : RO; bitpos: [26]; default: 0;
+ *  This status bit will be set if the receiver receives more data than the memory size.
+ */
+#define RMT_MEM_FULL_CH4    (BIT(26))
+#define RMT_MEM_FULL_CH4_M  (RMT_MEM_FULL_CH4_V << RMT_MEM_FULL_CH4_S)
+#define RMT_MEM_FULL_CH4_V  0x00000001U
+#define RMT_MEM_FULL_CH4_S  26
+/** RMT_APB_MEM_RD_ERR_CH4 : RO; bitpos: [27]; default: 0;
+ *  This status bit will be set if the offset address out of memory size when reads via
+ *  APB bus.
+ */
+#define RMT_APB_MEM_RD_ERR_CH4    (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH4_M  (RMT_APB_MEM_RD_ERR_CH4_V << RMT_APB_MEM_RD_ERR_CH4_S)
+#define RMT_APB_MEM_RD_ERR_CH4_V  0x00000001U
+#define RMT_APB_MEM_RD_ERR_CH4_S  27
+
+/** RMT_CH5STATUS_REG register
+ *  Channel 5 status register
+ */
+#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x64)
+/** RMT_MEM_WADDR_EX_CH5 : RO; bitpos: [9:0]; default: 192;
+ *  This register records the memory address offset when receiver of CHANNEL5 is using
+ *  the RAM.
+ */
+#define RMT_MEM_WADDR_EX_CH5    0x000003FFU
+#define RMT_MEM_WADDR_EX_CH5_M  (RMT_MEM_WADDR_EX_CH5_V << RMT_MEM_WADDR_EX_CH5_S)
+#define RMT_MEM_WADDR_EX_CH5_V  0x000003FFU
+#define RMT_MEM_WADDR_EX_CH5_S  0
+/** RMT_APB_MEM_RADDR_CH5 : RO; bitpos: [20:11]; default: 192;
+ *  This register records the memory address offset when reads RAM over APB bus.
+ */
+#define RMT_APB_MEM_RADDR_CH5    0x000003FFU
+#define RMT_APB_MEM_RADDR_CH5_M  (RMT_APB_MEM_RADDR_CH5_V << RMT_APB_MEM_RADDR_CH5_S)
+#define RMT_APB_MEM_RADDR_CH5_V  0x000003FFU
+#define RMT_APB_MEM_RADDR_CH5_S  11
+/** RMT_STATE_CH5 : RO; bitpos: [24:22]; default: 0;
+ *  This register records the FSM status of CHANNEL5.
+ */
+#define RMT_STATE_CH5    0x00000007U
+#define RMT_STATE_CH5_M  (RMT_STATE_CH5_V << RMT_STATE_CH5_S)
+#define RMT_STATE_CH5_V  0x00000007U
+#define RMT_STATE_CH5_S  22
+/** RMT_MEM_OWNER_ERR_CH5 : RO; bitpos: [25]; default: 0;
+ *  This status bit will be set when the ownership of memory block is wrong.
+ */
+#define RMT_MEM_OWNER_ERR_CH5    (BIT(25))
+#define RMT_MEM_OWNER_ERR_CH5_M  (RMT_MEM_OWNER_ERR_CH5_V << RMT_MEM_OWNER_ERR_CH5_S)
+#define RMT_MEM_OWNER_ERR_CH5_V  0x00000001U
+#define RMT_MEM_OWNER_ERR_CH5_S  25
+/** RMT_MEM_FULL_CH5 : RO; bitpos: [26]; default: 0;
+ *  This status bit will be set if the receiver receives more data than the memory size.
+ */
+#define RMT_MEM_FULL_CH5    (BIT(26))
+#define RMT_MEM_FULL_CH5_M  (RMT_MEM_FULL_CH5_V << RMT_MEM_FULL_CH5_S)
+#define RMT_MEM_FULL_CH5_V  0x00000001U
+#define RMT_MEM_FULL_CH5_S  26
+/** RMT_APB_MEM_RD_ERR_CH5 : RO; bitpos: [27]; default: 0;
+ *  This status bit will be set if the offset address out of memory size when reads via
+ *  APB bus.
+ */
+#define RMT_APB_MEM_RD_ERR_CH5    (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH5_M  (RMT_APB_MEM_RD_ERR_CH5_V << RMT_APB_MEM_RD_ERR_CH5_S)
+#define RMT_APB_MEM_RD_ERR_CH5_V  0x00000001U
+#define RMT_APB_MEM_RD_ERR_CH5_S  27
+
+/** RMT_CH6STATUS_REG register
+ *  Channel 6 status register
+ */
+#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x68)
+/** RMT_MEM_WADDR_EX_CH6 : RO; bitpos: [9:0]; default: 192;
+ *  This register records the memory address offset when receiver of CHANNEL6 is using
+ *  the RAM.
+ */
+#define RMT_MEM_WADDR_EX_CH6    0x000003FFU
+#define RMT_MEM_WADDR_EX_CH6_M  (RMT_MEM_WADDR_EX_CH6_V << RMT_MEM_WADDR_EX_CH6_S)
+#define RMT_MEM_WADDR_EX_CH6_V  0x000003FFU
+#define RMT_MEM_WADDR_EX_CH6_S  0
+/** RMT_APB_MEM_RADDR_CH6 : RO; bitpos: [20:11]; default: 192;
+ *  This register records the memory address offset when reads RAM over APB bus.
+ */
+#define RMT_APB_MEM_RADDR_CH6    0x000003FFU
+#define RMT_APB_MEM_RADDR_CH6_M  (RMT_APB_MEM_RADDR_CH6_V << RMT_APB_MEM_RADDR_CH6_S)
+#define RMT_APB_MEM_RADDR_CH6_V  0x000003FFU
+#define RMT_APB_MEM_RADDR_CH6_S  11
+/** RMT_STATE_CH6 : RO; bitpos: [24:22]; default: 0;
+ *  This register records the FSM status of CHANNEL6.
+ */
+#define RMT_STATE_CH6    0x00000007U
+#define RMT_STATE_CH6_M  (RMT_STATE_CH6_V << RMT_STATE_CH6_S)
+#define RMT_STATE_CH6_V  0x00000007U
+#define RMT_STATE_CH6_S  22
+/** RMT_MEM_OWNER_ERR_CH6 : RO; bitpos: [25]; default: 0;
+ *  This status bit will be set when the ownership of memory block is wrong.
+ */
+#define RMT_MEM_OWNER_ERR_CH6    (BIT(25))
+#define RMT_MEM_OWNER_ERR_CH6_M  (RMT_MEM_OWNER_ERR_CH6_V << RMT_MEM_OWNER_ERR_CH6_S)
+#define RMT_MEM_OWNER_ERR_CH6_V  0x00000001U
+#define RMT_MEM_OWNER_ERR_CH6_S  25
+/** RMT_MEM_FULL_CH6 : RO; bitpos: [26]; default: 0;
+ *  This status bit will be set if the receiver receives more data than the memory size.
+ */
+#define RMT_MEM_FULL_CH6    (BIT(26))
+#define RMT_MEM_FULL_CH6_M  (RMT_MEM_FULL_CH6_V << RMT_MEM_FULL_CH6_S)
+#define RMT_MEM_FULL_CH6_V  0x00000001U
+#define RMT_MEM_FULL_CH6_S  26
+/** RMT_APB_MEM_RD_ERR_CH6 : RO; bitpos: [27]; default: 0;
+ *  This status bit will be set if the offset address out of memory size when reads via
+ *  APB bus.
+ */
+#define RMT_APB_MEM_RD_ERR_CH6    (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH6_M  (RMT_APB_MEM_RD_ERR_CH6_V << RMT_APB_MEM_RD_ERR_CH6_S)
+#define RMT_APB_MEM_RD_ERR_CH6_V  0x00000001U
+#define RMT_APB_MEM_RD_ERR_CH6_S  27
+
+/** RMT_CH7STATUS_REG register
+ *  Channel 7 status register
+ */
+#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x6c)
+/** RMT_MEM_WADDR_EX_CH7 : RO; bitpos: [9:0]; default: 192;
+ *  This register records the memory address offset when receiver of CHANNEL7 is using
+ *  the RAM.
+ */
+#define RMT_MEM_WADDR_EX_CH7    0x000003FFU
+#define RMT_MEM_WADDR_EX_CH7_M  (RMT_MEM_WADDR_EX_CH7_V << RMT_MEM_WADDR_EX_CH7_S)
+#define RMT_MEM_WADDR_EX_CH7_V  0x000003FFU
+#define RMT_MEM_WADDR_EX_CH7_S  0
+/** RMT_APB_MEM_RADDR_CH7 : RO; bitpos: [20:11]; default: 192;
+ *  This register records the memory address offset when reads RAM over APB bus.
+ */
+#define RMT_APB_MEM_RADDR_CH7    0x000003FFU
+#define RMT_APB_MEM_RADDR_CH7_M  (RMT_APB_MEM_RADDR_CH7_V << RMT_APB_MEM_RADDR_CH7_S)
+#define RMT_APB_MEM_RADDR_CH7_V  0x000003FFU
+#define RMT_APB_MEM_RADDR_CH7_S  11
+/** RMT_STATE_CH7 : RO; bitpos: [24:22]; default: 0;
+ *  This register records the FSM status of CHANNEL7.
+ */
+#define RMT_STATE_CH7    0x00000007U
+#define RMT_STATE_CH7_M  (RMT_STATE_CH7_V << RMT_STATE_CH7_S)
+#define RMT_STATE_CH7_V  0x00000007U
+#define RMT_STATE_CH7_S  22
+/** RMT_MEM_OWNER_ERR_CH7 : RO; bitpos: [25]; default: 0;
+ *  This status bit will be set when the ownership of memory block is wrong.
+ */
+#define RMT_MEM_OWNER_ERR_CH7    (BIT(25))
+#define RMT_MEM_OWNER_ERR_CH7_M  (RMT_MEM_OWNER_ERR_CH7_V << RMT_MEM_OWNER_ERR_CH7_S)
+#define RMT_MEM_OWNER_ERR_CH7_V  0x00000001U
+#define RMT_MEM_OWNER_ERR_CH7_S  25
+/** RMT_MEM_FULL_CH7 : RO; bitpos: [26]; default: 0;
+ *  This status bit will be set if the receiver receives more data than the memory size.
+ */
+#define RMT_MEM_FULL_CH7    (BIT(26))
+#define RMT_MEM_FULL_CH7_M  (RMT_MEM_FULL_CH7_V << RMT_MEM_FULL_CH7_S)
+#define RMT_MEM_FULL_CH7_V  0x00000001U
+#define RMT_MEM_FULL_CH7_S  26
+/** RMT_APB_MEM_RD_ERR_CH7 : RO; bitpos: [27]; default: 0;
+ *  This status bit will be set if the offset address out of memory size when reads via
+ *  APB bus.
+ */
+#define RMT_APB_MEM_RD_ERR_CH7    (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH7_M  (RMT_APB_MEM_RD_ERR_CH7_V << RMT_APB_MEM_RD_ERR_CH7_S)
+#define RMT_APB_MEM_RD_ERR_CH7_V  0x00000001U
+#define RMT_APB_MEM_RD_ERR_CH7_S  27
+
+/** RMT_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x70)
+/** RMT_CH0_TX_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The interrupt raw bit for CHANNEL0. Triggered when transmission done.
+ */
+#define RMT_CH0_TX_END_INT_RAW    (BIT(0))
+#define RMT_CH0_TX_END_INT_RAW_M  (RMT_CH0_TX_END_INT_RAW_V << RMT_CH0_TX_END_INT_RAW_S)
+#define RMT_CH0_TX_END_INT_RAW_V  0x00000001U
+#define RMT_CH0_TX_END_INT_RAW_S  0
+/** RMT_CH1_TX_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The interrupt raw bit for CHANNEL1. Triggered when transmission done.
+ */
+#define RMT_CH1_TX_END_INT_RAW    (BIT(1))
+#define RMT_CH1_TX_END_INT_RAW_M  (RMT_CH1_TX_END_INT_RAW_V << RMT_CH1_TX_END_INT_RAW_S)
+#define RMT_CH1_TX_END_INT_RAW_V  0x00000001U
+#define RMT_CH1_TX_END_INT_RAW_S  1
+/** RMT_CH2_TX_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The interrupt raw bit for CHANNEL2. Triggered when transmission done.
+ */
+#define RMT_CH2_TX_END_INT_RAW    (BIT(2))
+#define RMT_CH2_TX_END_INT_RAW_M  (RMT_CH2_TX_END_INT_RAW_V << RMT_CH2_TX_END_INT_RAW_S)
+#define RMT_CH2_TX_END_INT_RAW_V  0x00000001U
+#define RMT_CH2_TX_END_INT_RAW_S  2
+/** RMT_CH3_TX_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The interrupt raw bit for CHANNEL3. Triggered when transmission done.
+ */
+#define RMT_CH3_TX_END_INT_RAW    (BIT(3))
+#define RMT_CH3_TX_END_INT_RAW_M  (RMT_CH3_TX_END_INT_RAW_V << RMT_CH3_TX_END_INT_RAW_S)
+#define RMT_CH3_TX_END_INT_RAW_V  0x00000001U
+#define RMT_CH3_TX_END_INT_RAW_S  3
+/** RMT_CH0_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The interrupt raw bit for CHANNEL0. Triggered when error occurs.
+ */
+#define RMT_CH0_ERR_INT_RAW    (BIT(4))
+#define RMT_CH0_ERR_INT_RAW_M  (RMT_CH0_ERR_INT_RAW_V << RMT_CH0_ERR_INT_RAW_S)
+#define RMT_CH0_ERR_INT_RAW_V  0x00000001U
+#define RMT_CH0_ERR_INT_RAW_S  4
+/** RMT_CH1_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The interrupt raw bit for CHANNEL1. Triggered when error occurs.
+ */
+#define RMT_CH1_ERR_INT_RAW    (BIT(5))
+#define RMT_CH1_ERR_INT_RAW_M  (RMT_CH1_ERR_INT_RAW_V << RMT_CH1_ERR_INT_RAW_S)
+#define RMT_CH1_ERR_INT_RAW_V  0x00000001U
+#define RMT_CH1_ERR_INT_RAW_S  5
+/** RMT_CH2_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The interrupt raw bit for CHANNEL2. Triggered when error occurs.
+ */
+#define RMT_CH2_ERR_INT_RAW    (BIT(6))
+#define RMT_CH2_ERR_INT_RAW_M  (RMT_CH2_ERR_INT_RAW_V << RMT_CH2_ERR_INT_RAW_S)
+#define RMT_CH2_ERR_INT_RAW_V  0x00000001U
+#define RMT_CH2_ERR_INT_RAW_S  6
+/** RMT_CH3_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The interrupt raw bit for CHANNEL3. Triggered when error occurs.
+ */
+#define RMT_CH3_ERR_INT_RAW    (BIT(7))
+#define RMT_CH3_ERR_INT_RAW_M  (RMT_CH3_ERR_INT_RAW_V << RMT_CH3_ERR_INT_RAW_S)
+#define RMT_CH3_ERR_INT_RAW_V  0x00000001U
+#define RMT_CH3_ERR_INT_RAW_S  7
+/** RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than
+ *  configured value.
+ */
+#define RMT_CH0_TX_THR_EVENT_INT_RAW    (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_M  (RMT_CH0_TX_THR_EVENT_INT_RAW_V << RMT_CH0_TX_THR_EVENT_INT_RAW_S)
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_V  0x00000001U
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_S  8
+/** RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than
+ *  configured value.
+ */
+#define RMT_CH1_TX_THR_EVENT_INT_RAW    (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_M  (RMT_CH1_TX_THR_EVENT_INT_RAW_V << RMT_CH1_TX_THR_EVENT_INT_RAW_S)
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_V  0x00000001U
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_S  9
+/** RMT_CH2_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than
+ *  configured value.
+ */
+#define RMT_CH2_TX_THR_EVENT_INT_RAW    (BIT(10))
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_M  (RMT_CH2_TX_THR_EVENT_INT_RAW_V << RMT_CH2_TX_THR_EVENT_INT_RAW_S)
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_V  0x00000001U
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_S  10
+/** RMT_CH3_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than
+ *  configured value.
+ */
+#define RMT_CH3_TX_THR_EVENT_INT_RAW    (BIT(11))
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_M  (RMT_CH3_TX_THR_EVENT_INT_RAW_V << RMT_CH3_TX_THR_EVENT_INT_RAW_S)
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_V  0x00000001U
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_S  11
+/** RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the
+ *  configured threshold value.
+ */
+#define RMT_CH0_TX_LOOP_INT_RAW    (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_RAW_M  (RMT_CH0_TX_LOOP_INT_RAW_V << RMT_CH0_TX_LOOP_INT_RAW_S)
+#define RMT_CH0_TX_LOOP_INT_RAW_V  0x00000001U
+#define RMT_CH0_TX_LOOP_INT_RAW_S  12
+/** RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the
+ *  configured threshold value.
+ */
+#define RMT_CH1_TX_LOOP_INT_RAW    (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_RAW_M  (RMT_CH1_TX_LOOP_INT_RAW_V << RMT_CH1_TX_LOOP_INT_RAW_S)
+#define RMT_CH1_TX_LOOP_INT_RAW_V  0x00000001U
+#define RMT_CH1_TX_LOOP_INT_RAW_S  13
+/** RMT_CH2_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the
+ *  configured threshold value.
+ */
+#define RMT_CH2_TX_LOOP_INT_RAW    (BIT(14))
+#define RMT_CH2_TX_LOOP_INT_RAW_M  (RMT_CH2_TX_LOOP_INT_RAW_V << RMT_CH2_TX_LOOP_INT_RAW_S)
+#define RMT_CH2_TX_LOOP_INT_RAW_V  0x00000001U
+#define RMT_CH2_TX_LOOP_INT_RAW_S  14
+/** RMT_CH3_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the
+ *  configured threshold value.
+ */
+#define RMT_CH3_TX_LOOP_INT_RAW    (BIT(15))
+#define RMT_CH3_TX_LOOP_INT_RAW_M  (RMT_CH3_TX_LOOP_INT_RAW_V << RMT_CH3_TX_LOOP_INT_RAW_S)
+#define RMT_CH3_TX_LOOP_INT_RAW_V  0x00000001U
+#define RMT_CH3_TX_LOOP_INT_RAW_S  15
+/** RMT_CH4_RX_END_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The interrupt raw bit for CHANNEL4. Triggered when reception done.
+ */
+#define RMT_CH4_RX_END_INT_RAW    (BIT(16))
+#define RMT_CH4_RX_END_INT_RAW_M  (RMT_CH4_RX_END_INT_RAW_V << RMT_CH4_RX_END_INT_RAW_S)
+#define RMT_CH4_RX_END_INT_RAW_V  0x00000001U
+#define RMT_CH4_RX_END_INT_RAW_S  16
+/** RMT_CH5_RX_END_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The interrupt raw bit for CHANNEL5. Triggered when reception done.
+ */
+#define RMT_CH5_RX_END_INT_RAW    (BIT(17))
+#define RMT_CH5_RX_END_INT_RAW_M  (RMT_CH5_RX_END_INT_RAW_V << RMT_CH5_RX_END_INT_RAW_S)
+#define RMT_CH5_RX_END_INT_RAW_V  0x00000001U
+#define RMT_CH5_RX_END_INT_RAW_S  17
+/** RMT_CH6_RX_END_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The interrupt raw bit for CHANNEL6. Triggered when reception done.
+ */
+#define RMT_CH6_RX_END_INT_RAW    (BIT(18))
+#define RMT_CH6_RX_END_INT_RAW_M  (RMT_CH6_RX_END_INT_RAW_V << RMT_CH6_RX_END_INT_RAW_S)
+#define RMT_CH6_RX_END_INT_RAW_V  0x00000001U
+#define RMT_CH6_RX_END_INT_RAW_S  18
+/** RMT_CH7_RX_END_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The interrupt raw bit for CHANNEL7. Triggered when reception done.
+ */
+#define RMT_CH7_RX_END_INT_RAW    (BIT(19))
+#define RMT_CH7_RX_END_INT_RAW_M  (RMT_CH7_RX_END_INT_RAW_V << RMT_CH7_RX_END_INT_RAW_S)
+#define RMT_CH7_RX_END_INT_RAW_V  0x00000001U
+#define RMT_CH7_RX_END_INT_RAW_S  19
+/** RMT_CH4_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The interrupt raw bit for CHANNEL4. Triggered when error occurs.
+ */
+#define RMT_CH4_ERR_INT_RAW    (BIT(20))
+#define RMT_CH4_ERR_INT_RAW_M  (RMT_CH4_ERR_INT_RAW_V << RMT_CH4_ERR_INT_RAW_S)
+#define RMT_CH4_ERR_INT_RAW_V  0x00000001U
+#define RMT_CH4_ERR_INT_RAW_S  20
+/** RMT_CH5_ERR_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  The interrupt raw bit for CHANNEL5. Triggered when error occurs.
+ */
+#define RMT_CH5_ERR_INT_RAW    (BIT(21))
+#define RMT_CH5_ERR_INT_RAW_M  (RMT_CH5_ERR_INT_RAW_V << RMT_CH5_ERR_INT_RAW_S)
+#define RMT_CH5_ERR_INT_RAW_V  0x00000001U
+#define RMT_CH5_ERR_INT_RAW_S  21
+/** RMT_CH6_ERR_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  The interrupt raw bit for CHANNEL6. Triggered when error occurs.
+ */
+#define RMT_CH6_ERR_INT_RAW    (BIT(22))
+#define RMT_CH6_ERR_INT_RAW_M  (RMT_CH6_ERR_INT_RAW_V << RMT_CH6_ERR_INT_RAW_S)
+#define RMT_CH6_ERR_INT_RAW_V  0x00000001U
+#define RMT_CH6_ERR_INT_RAW_S  22
+/** RMT_CH7_ERR_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  The interrupt raw bit for CHANNEL7. Triggered when error occurs.
+ */
+#define RMT_CH7_ERR_INT_RAW    (BIT(23))
+#define RMT_CH7_ERR_INT_RAW_M  (RMT_CH7_ERR_INT_RAW_V << RMT_CH7_ERR_INT_RAW_S)
+#define RMT_CH7_ERR_INT_RAW_V  0x00000001U
+#define RMT_CH7_ERR_INT_RAW_S  23
+/** RMT_CH4_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than
+ *  configured value.
+ */
+#define RMT_CH4_RX_THR_EVENT_INT_RAW    (BIT(24))
+#define RMT_CH4_RX_THR_EVENT_INT_RAW_M  (RMT_CH4_RX_THR_EVENT_INT_RAW_V << RMT_CH4_RX_THR_EVENT_INT_RAW_S)
+#define RMT_CH4_RX_THR_EVENT_INT_RAW_V  0x00000001U
+#define RMT_CH4_RX_THR_EVENT_INT_RAW_S  24
+/** RMT_CH5_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than
+ *  configured value.
+ */
+#define RMT_CH5_RX_THR_EVENT_INT_RAW    (BIT(25))
+#define RMT_CH5_RX_THR_EVENT_INT_RAW_M  (RMT_CH5_RX_THR_EVENT_INT_RAW_V << RMT_CH5_RX_THR_EVENT_INT_RAW_S)
+#define RMT_CH5_RX_THR_EVENT_INT_RAW_V  0x00000001U
+#define RMT_CH5_RX_THR_EVENT_INT_RAW_S  25
+/** RMT_CH6_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than
+ *  configured value.
+ */
+#define RMT_CH6_RX_THR_EVENT_INT_RAW    (BIT(26))
+#define RMT_CH6_RX_THR_EVENT_INT_RAW_M  (RMT_CH6_RX_THR_EVENT_INT_RAW_V << RMT_CH6_RX_THR_EVENT_INT_RAW_S)
+#define RMT_CH6_RX_THR_EVENT_INT_RAW_V  0x00000001U
+#define RMT_CH6_RX_THR_EVENT_INT_RAW_S  26
+/** RMT_CH7_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than
+ *  configured value.
+ */
+#define RMT_CH7_RX_THR_EVENT_INT_RAW    (BIT(27))
+#define RMT_CH7_RX_THR_EVENT_INT_RAW_M  (RMT_CH7_RX_THR_EVENT_INT_RAW_V << RMT_CH7_RX_THR_EVENT_INT_RAW_S)
+#define RMT_CH7_RX_THR_EVENT_INT_RAW_V  0x00000001U
+#define RMT_CH7_RX_THR_EVENT_INT_RAW_S  27
+/** RMT_CH3_DMA_ACCESS_FAIL_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails.
+ */
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW    (BIT(28))
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_M  (RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_V << RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_S)
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_V  0x00000001U
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_S  28
+/** RMT_CH7_DMA_ACCESS_FAIL_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails.
+ */
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW    (BIT(29))
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_M  (RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_V << RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_S)
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_V  0x00000001U
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_S  29
+
+/** RMT_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x74)
+/** RMT_CH0_TX_END_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for CH0_TX_END_INT.
+ */
+#define RMT_CH0_TX_END_INT_ST    (BIT(0))
+#define RMT_CH0_TX_END_INT_ST_M  (RMT_CH0_TX_END_INT_ST_V << RMT_CH0_TX_END_INT_ST_S)
+#define RMT_CH0_TX_END_INT_ST_V  0x00000001U
+#define RMT_CH0_TX_END_INT_ST_S  0
+/** RMT_CH1_TX_END_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for CH1_TX_END_INT.
+ */
+#define RMT_CH1_TX_END_INT_ST    (BIT(1))
+#define RMT_CH1_TX_END_INT_ST_M  (RMT_CH1_TX_END_INT_ST_V << RMT_CH1_TX_END_INT_ST_S)
+#define RMT_CH1_TX_END_INT_ST_V  0x00000001U
+#define RMT_CH1_TX_END_INT_ST_S  1
+/** RMT_CH2_TX_END_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for CH2_TX_END_INT.
+ */
+#define RMT_CH2_TX_END_INT_ST    (BIT(2))
+#define RMT_CH2_TX_END_INT_ST_M  (RMT_CH2_TX_END_INT_ST_V << RMT_CH2_TX_END_INT_ST_S)
+#define RMT_CH2_TX_END_INT_ST_V  0x00000001U
+#define RMT_CH2_TX_END_INT_ST_S  2
+/** RMT_CH3_TX_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit for CH3_TX_END_INT.
+ */
+#define RMT_CH3_TX_END_INT_ST    (BIT(3))
+#define RMT_CH3_TX_END_INT_ST_M  (RMT_CH3_TX_END_INT_ST_V << RMT_CH3_TX_END_INT_ST_S)
+#define RMT_CH3_TX_END_INT_ST_V  0x00000001U
+#define RMT_CH3_TX_END_INT_ST_S  3
+/** RMT_CH0_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status bit for CH0_ERR_INT.
+ */
+#define RMT_CH0_ERR_INT_ST    (BIT(4))
+#define RMT_CH0_ERR_INT_ST_M  (RMT_CH0_ERR_INT_ST_V << RMT_CH0_ERR_INT_ST_S)
+#define RMT_CH0_ERR_INT_ST_V  0x00000001U
+#define RMT_CH0_ERR_INT_ST_S  4
+/** RMT_CH1_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status bit for CH1_ERR_INT.
+ */
+#define RMT_CH1_ERR_INT_ST    (BIT(5))
+#define RMT_CH1_ERR_INT_ST_M  (RMT_CH1_ERR_INT_ST_V << RMT_CH1_ERR_INT_ST_S)
+#define RMT_CH1_ERR_INT_ST_V  0x00000001U
+#define RMT_CH1_ERR_INT_ST_S  5
+/** RMT_CH2_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status bit for CH2_ERR_INT.
+ */
+#define RMT_CH2_ERR_INT_ST    (BIT(6))
+#define RMT_CH2_ERR_INT_ST_M  (RMT_CH2_ERR_INT_ST_V << RMT_CH2_ERR_INT_ST_S)
+#define RMT_CH2_ERR_INT_ST_V  0x00000001U
+#define RMT_CH2_ERR_INT_ST_S  6
+/** RMT_CH3_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status bit for CH3_ERR_INT.
+ */
+#define RMT_CH3_ERR_INT_ST    (BIT(7))
+#define RMT_CH3_ERR_INT_ST_M  (RMT_CH3_ERR_INT_ST_V << RMT_CH3_ERR_INT_ST_S)
+#define RMT_CH3_ERR_INT_ST_V  0x00000001U
+#define RMT_CH3_ERR_INT_ST_S  7
+/** RMT_CH0_TX_THR_EVENT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
+ */
+#define RMT_CH0_TX_THR_EVENT_INT_ST    (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_ST_M  (RMT_CH0_TX_THR_EVENT_INT_ST_V << RMT_CH0_TX_THR_EVENT_INT_ST_S)
+#define RMT_CH0_TX_THR_EVENT_INT_ST_V  0x00000001U
+#define RMT_CH0_TX_THR_EVENT_INT_ST_S  8
+/** RMT_CH1_TX_THR_EVENT_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
+ */
+#define RMT_CH1_TX_THR_EVENT_INT_ST    (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_ST_M  (RMT_CH1_TX_THR_EVENT_INT_ST_V << RMT_CH1_TX_THR_EVENT_INT_ST_S)
+#define RMT_CH1_TX_THR_EVENT_INT_ST_V  0x00000001U
+#define RMT_CH1_TX_THR_EVENT_INT_ST_S  9
+/** RMT_CH2_TX_THR_EVENT_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked interrupt status bit for CH2_TX_THR_EVENT_INT.
+ */
+#define RMT_CH2_TX_THR_EVENT_INT_ST    (BIT(10))
+#define RMT_CH2_TX_THR_EVENT_INT_ST_M  (RMT_CH2_TX_THR_EVENT_INT_ST_V << RMT_CH2_TX_THR_EVENT_INT_ST_S)
+#define RMT_CH2_TX_THR_EVENT_INT_ST_V  0x00000001U
+#define RMT_CH2_TX_THR_EVENT_INT_ST_S  10
+/** RMT_CH3_TX_THR_EVENT_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked interrupt status bit for CH3_TX_THR_EVENT_INT.
+ */
+#define RMT_CH3_TX_THR_EVENT_INT_ST    (BIT(11))
+#define RMT_CH3_TX_THR_EVENT_INT_ST_M  (RMT_CH3_TX_THR_EVENT_INT_ST_V << RMT_CH3_TX_THR_EVENT_INT_ST_S)
+#define RMT_CH3_TX_THR_EVENT_INT_ST_V  0x00000001U
+#define RMT_CH3_TX_THR_EVENT_INT_ST_S  11
+/** RMT_CH0_TX_LOOP_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked interrupt status bit for CH0_TX_LOOP_INT.
+ */
+#define RMT_CH0_TX_LOOP_INT_ST    (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_ST_M  (RMT_CH0_TX_LOOP_INT_ST_V << RMT_CH0_TX_LOOP_INT_ST_S)
+#define RMT_CH0_TX_LOOP_INT_ST_V  0x00000001U
+#define RMT_CH0_TX_LOOP_INT_ST_S  12
+/** RMT_CH1_TX_LOOP_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked interrupt status bit for CH1_TX_LOOP_INT.
+ */
+#define RMT_CH1_TX_LOOP_INT_ST    (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_ST_M  (RMT_CH1_TX_LOOP_INT_ST_V << RMT_CH1_TX_LOOP_INT_ST_S)
+#define RMT_CH1_TX_LOOP_INT_ST_V  0x00000001U
+#define RMT_CH1_TX_LOOP_INT_ST_S  13
+/** RMT_CH2_TX_LOOP_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked interrupt status bit for CH2_TX_LOOP_INT.
+ */
+#define RMT_CH2_TX_LOOP_INT_ST    (BIT(14))
+#define RMT_CH2_TX_LOOP_INT_ST_M  (RMT_CH2_TX_LOOP_INT_ST_V << RMT_CH2_TX_LOOP_INT_ST_S)
+#define RMT_CH2_TX_LOOP_INT_ST_V  0x00000001U
+#define RMT_CH2_TX_LOOP_INT_ST_S  14
+/** RMT_CH3_TX_LOOP_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked interrupt status bit for CH3_TX_LOOP_INT.
+ */
+#define RMT_CH3_TX_LOOP_INT_ST    (BIT(15))
+#define RMT_CH3_TX_LOOP_INT_ST_M  (RMT_CH3_TX_LOOP_INT_ST_V << RMT_CH3_TX_LOOP_INT_ST_S)
+#define RMT_CH3_TX_LOOP_INT_ST_V  0x00000001U
+#define RMT_CH3_TX_LOOP_INT_ST_S  15
+/** RMT_CH4_RX_END_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The masked interrupt status bit for CH4_RX_END_INT.
+ */
+#define RMT_CH4_RX_END_INT_ST    (BIT(16))
+#define RMT_CH4_RX_END_INT_ST_M  (RMT_CH4_RX_END_INT_ST_V << RMT_CH4_RX_END_INT_ST_S)
+#define RMT_CH4_RX_END_INT_ST_V  0x00000001U
+#define RMT_CH4_RX_END_INT_ST_S  16
+/** RMT_CH5_RX_END_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The masked interrupt status bit for CH5_RX_END_INT.
+ */
+#define RMT_CH5_RX_END_INT_ST    (BIT(17))
+#define RMT_CH5_RX_END_INT_ST_M  (RMT_CH5_RX_END_INT_ST_V << RMT_CH5_RX_END_INT_ST_S)
+#define RMT_CH5_RX_END_INT_ST_V  0x00000001U
+#define RMT_CH5_RX_END_INT_ST_S  17
+/** RMT_CH6_RX_END_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The masked interrupt status bit for CH6_RX_END_INT.
+ */
+#define RMT_CH6_RX_END_INT_ST    (BIT(18))
+#define RMT_CH6_RX_END_INT_ST_M  (RMT_CH6_RX_END_INT_ST_V << RMT_CH6_RX_END_INT_ST_S)
+#define RMT_CH6_RX_END_INT_ST_V  0x00000001U
+#define RMT_CH6_RX_END_INT_ST_S  18
+/** RMT_CH7_RX_END_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The masked interrupt status bit for CH7_RX_END_INT.
+ */
+#define RMT_CH7_RX_END_INT_ST    (BIT(19))
+#define RMT_CH7_RX_END_INT_ST_M  (RMT_CH7_RX_END_INT_ST_V << RMT_CH7_RX_END_INT_ST_S)
+#define RMT_CH7_RX_END_INT_ST_V  0x00000001U
+#define RMT_CH7_RX_END_INT_ST_S  19
+/** RMT_CH4_ERR_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The masked interrupt status bit for CH4_ERR_INT.
+ */
+#define RMT_CH4_ERR_INT_ST    (BIT(20))
+#define RMT_CH4_ERR_INT_ST_M  (RMT_CH4_ERR_INT_ST_V << RMT_CH4_ERR_INT_ST_S)
+#define RMT_CH4_ERR_INT_ST_V  0x00000001U
+#define RMT_CH4_ERR_INT_ST_S  20
+/** RMT_CH5_ERR_INT_ST : RO; bitpos: [21]; default: 0;
+ *  The masked interrupt status bit for CH5_ERR_INT.
+ */
+#define RMT_CH5_ERR_INT_ST    (BIT(21))
+#define RMT_CH5_ERR_INT_ST_M  (RMT_CH5_ERR_INT_ST_V << RMT_CH5_ERR_INT_ST_S)
+#define RMT_CH5_ERR_INT_ST_V  0x00000001U
+#define RMT_CH5_ERR_INT_ST_S  21
+/** RMT_CH6_ERR_INT_ST : RO; bitpos: [22]; default: 0;
+ *  The masked interrupt status bit for CH6_ERR_INT.
+ */
+#define RMT_CH6_ERR_INT_ST    (BIT(22))
+#define RMT_CH6_ERR_INT_ST_M  (RMT_CH6_ERR_INT_ST_V << RMT_CH6_ERR_INT_ST_S)
+#define RMT_CH6_ERR_INT_ST_V  0x00000001U
+#define RMT_CH6_ERR_INT_ST_S  22
+/** RMT_CH7_ERR_INT_ST : RO; bitpos: [23]; default: 0;
+ *  The masked interrupt status bit for CH7_ERR_INT.
+ */
+#define RMT_CH7_ERR_INT_ST    (BIT(23))
+#define RMT_CH7_ERR_INT_ST_M  (RMT_CH7_ERR_INT_ST_V << RMT_CH7_ERR_INT_ST_S)
+#define RMT_CH7_ERR_INT_ST_V  0x00000001U
+#define RMT_CH7_ERR_INT_ST_S  23
+/** RMT_CH4_RX_THR_EVENT_INT_ST : RO; bitpos: [24]; default: 0;
+ *  The masked interrupt status bit for CH4_RX_THR_EVENT_INT.
+ */
+#define RMT_CH4_RX_THR_EVENT_INT_ST    (BIT(24))
+#define RMT_CH4_RX_THR_EVENT_INT_ST_M  (RMT_CH4_RX_THR_EVENT_INT_ST_V << RMT_CH4_RX_THR_EVENT_INT_ST_S)
+#define RMT_CH4_RX_THR_EVENT_INT_ST_V  0x00000001U
+#define RMT_CH4_RX_THR_EVENT_INT_ST_S  24
+/** RMT_CH5_RX_THR_EVENT_INT_ST : RO; bitpos: [25]; default: 0;
+ *  The masked interrupt status bit for CH5_RX_THR_EVENT_INT.
+ */
+#define RMT_CH5_RX_THR_EVENT_INT_ST    (BIT(25))
+#define RMT_CH5_RX_THR_EVENT_INT_ST_M  (RMT_CH5_RX_THR_EVENT_INT_ST_V << RMT_CH5_RX_THR_EVENT_INT_ST_S)
+#define RMT_CH5_RX_THR_EVENT_INT_ST_V  0x00000001U
+#define RMT_CH5_RX_THR_EVENT_INT_ST_S  25
+/** RMT_CH6_RX_THR_EVENT_INT_ST : RO; bitpos: [26]; default: 0;
+ *  The masked interrupt status bit for CH6_RX_THR_EVENT_INT.
+ */
+#define RMT_CH6_RX_THR_EVENT_INT_ST    (BIT(26))
+#define RMT_CH6_RX_THR_EVENT_INT_ST_M  (RMT_CH6_RX_THR_EVENT_INT_ST_V << RMT_CH6_RX_THR_EVENT_INT_ST_S)
+#define RMT_CH6_RX_THR_EVENT_INT_ST_V  0x00000001U
+#define RMT_CH6_RX_THR_EVENT_INT_ST_S  26
+/** RMT_CH7_RX_THR_EVENT_INT_ST : RO; bitpos: [27]; default: 0;
+ *  The masked interrupt status bit for CH7_RX_THR_EVENT_INT.
+ */
+#define RMT_CH7_RX_THR_EVENT_INT_ST    (BIT(27))
+#define RMT_CH7_RX_THR_EVENT_INT_ST_M  (RMT_CH7_RX_THR_EVENT_INT_ST_V << RMT_CH7_RX_THR_EVENT_INT_ST_S)
+#define RMT_CH7_RX_THR_EVENT_INT_ST_V  0x00000001U
+#define RMT_CH7_RX_THR_EVENT_INT_ST_S  27
+/** RMT_CH3_DMA_ACCESS_FAIL_INT_ST : RO; bitpos: [28]; default: 0;
+ *  The masked interrupt status bit for  CH3_DMA_ACCESS_FAIL_INT.
+ */
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST    (BIT(28))
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_M  (RMT_CH3_DMA_ACCESS_FAIL_INT_ST_V << RMT_CH3_DMA_ACCESS_FAIL_INT_ST_S)
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_V  0x00000001U
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_S  28
+/** RMT_CH7_DMA_ACCESS_FAIL_INT_ST : RO; bitpos: [29]; default: 0;
+ *  The masked interrupt status bit for  CH7_DMA_ACCESS_FAIL_INT.
+ */
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST    (BIT(29))
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_M  (RMT_CH7_DMA_ACCESS_FAIL_INT_ST_V << RMT_CH7_DMA_ACCESS_FAIL_INT_ST_S)
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_V  0x00000001U
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_S  29
+
+/** RMT_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x78)
+/** RMT_CH0_TX_END_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for CH0_TX_END_INT.
+ */
+#define RMT_CH0_TX_END_INT_ENA    (BIT(0))
+#define RMT_CH0_TX_END_INT_ENA_M  (RMT_CH0_TX_END_INT_ENA_V << RMT_CH0_TX_END_INT_ENA_S)
+#define RMT_CH0_TX_END_INT_ENA_V  0x00000001U
+#define RMT_CH0_TX_END_INT_ENA_S  0
+/** RMT_CH1_TX_END_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for CH1_TX_END_INT.
+ */
+#define RMT_CH1_TX_END_INT_ENA    (BIT(1))
+#define RMT_CH1_TX_END_INT_ENA_M  (RMT_CH1_TX_END_INT_ENA_V << RMT_CH1_TX_END_INT_ENA_S)
+#define RMT_CH1_TX_END_INT_ENA_V  0x00000001U
+#define RMT_CH1_TX_END_INT_ENA_S  1
+/** RMT_CH2_TX_END_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for CH2_TX_END_INT.
+ */
+#define RMT_CH2_TX_END_INT_ENA    (BIT(2))
+#define RMT_CH2_TX_END_INT_ENA_M  (RMT_CH2_TX_END_INT_ENA_V << RMT_CH2_TX_END_INT_ENA_S)
+#define RMT_CH2_TX_END_INT_ENA_V  0x00000001U
+#define RMT_CH2_TX_END_INT_ENA_S  2
+/** RMT_CH3_TX_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for CH3_TX_END_INT.
+ */
+#define RMT_CH3_TX_END_INT_ENA    (BIT(3))
+#define RMT_CH3_TX_END_INT_ENA_M  (RMT_CH3_TX_END_INT_ENA_V << RMT_CH3_TX_END_INT_ENA_S)
+#define RMT_CH3_TX_END_INT_ENA_V  0x00000001U
+#define RMT_CH3_TX_END_INT_ENA_S  3
+/** RMT_CH0_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for CH0_ERR_INT.
+ */
+#define RMT_CH0_ERR_INT_ENA    (BIT(4))
+#define RMT_CH0_ERR_INT_ENA_M  (RMT_CH0_ERR_INT_ENA_V << RMT_CH0_ERR_INT_ENA_S)
+#define RMT_CH0_ERR_INT_ENA_V  0x00000001U
+#define RMT_CH0_ERR_INT_ENA_S  4
+/** RMT_CH1_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for CH1_ERR_INT.
+ */
+#define RMT_CH1_ERR_INT_ENA    (BIT(5))
+#define RMT_CH1_ERR_INT_ENA_M  (RMT_CH1_ERR_INT_ENA_V << RMT_CH1_ERR_INT_ENA_S)
+#define RMT_CH1_ERR_INT_ENA_V  0x00000001U
+#define RMT_CH1_ERR_INT_ENA_S  5
+/** RMT_CH2_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for CH2_ERR_INT.
+ */
+#define RMT_CH2_ERR_INT_ENA    (BIT(6))
+#define RMT_CH2_ERR_INT_ENA_M  (RMT_CH2_ERR_INT_ENA_V << RMT_CH2_ERR_INT_ENA_S)
+#define RMT_CH2_ERR_INT_ENA_V  0x00000001U
+#define RMT_CH2_ERR_INT_ENA_S  6
+/** RMT_CH3_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for CH3_ERR_INT.
+ */
+#define RMT_CH3_ERR_INT_ENA    (BIT(7))
+#define RMT_CH3_ERR_INT_ENA_M  (RMT_CH3_ERR_INT_ENA_V << RMT_CH3_ERR_INT_ENA_S)
+#define RMT_CH3_ERR_INT_ENA_V  0x00000001U
+#define RMT_CH3_ERR_INT_ENA_S  7
+/** RMT_CH0_TX_THR_EVENT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for CH0_TX_THR_EVENT_INT.
+ */
+#define RMT_CH0_TX_THR_EVENT_INT_ENA    (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_M  (RMT_CH0_TX_THR_EVENT_INT_ENA_V << RMT_CH0_TX_THR_EVENT_INT_ENA_S)
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_V  0x00000001U
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_S  8
+/** RMT_CH1_TX_THR_EVENT_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for CH1_TX_THR_EVENT_INT.
+ */
+#define RMT_CH1_TX_THR_EVENT_INT_ENA    (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_M  (RMT_CH1_TX_THR_EVENT_INT_ENA_V << RMT_CH1_TX_THR_EVENT_INT_ENA_S)
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_V  0x00000001U
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_S  9
+/** RMT_CH2_TX_THR_EVENT_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for CH2_TX_THR_EVENT_INT.
+ */
+#define RMT_CH2_TX_THR_EVENT_INT_ENA    (BIT(10))
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_M  (RMT_CH2_TX_THR_EVENT_INT_ENA_V << RMT_CH2_TX_THR_EVENT_INT_ENA_S)
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_V  0x00000001U
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_S  10
+/** RMT_CH3_TX_THR_EVENT_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for CH3_TX_THR_EVENT_INT.
+ */
+#define RMT_CH3_TX_THR_EVENT_INT_ENA    (BIT(11))
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_M  (RMT_CH3_TX_THR_EVENT_INT_ENA_V << RMT_CH3_TX_THR_EVENT_INT_ENA_S)
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_V  0x00000001U
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_S  11
+/** RMT_CH0_TX_LOOP_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for CH0_TX_LOOP_INT.
+ */
+#define RMT_CH0_TX_LOOP_INT_ENA    (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_ENA_M  (RMT_CH0_TX_LOOP_INT_ENA_V << RMT_CH0_TX_LOOP_INT_ENA_S)
+#define RMT_CH0_TX_LOOP_INT_ENA_V  0x00000001U
+#define RMT_CH0_TX_LOOP_INT_ENA_S  12
+/** RMT_CH1_TX_LOOP_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for CH1_TX_LOOP_INT.
+ */
+#define RMT_CH1_TX_LOOP_INT_ENA    (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_ENA_M  (RMT_CH1_TX_LOOP_INT_ENA_V << RMT_CH1_TX_LOOP_INT_ENA_S)
+#define RMT_CH1_TX_LOOP_INT_ENA_V  0x00000001U
+#define RMT_CH1_TX_LOOP_INT_ENA_S  13
+/** RMT_CH2_TX_LOOP_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for CH2_TX_LOOP_INT.
+ */
+#define RMT_CH2_TX_LOOP_INT_ENA    (BIT(14))
+#define RMT_CH2_TX_LOOP_INT_ENA_M  (RMT_CH2_TX_LOOP_INT_ENA_V << RMT_CH2_TX_LOOP_INT_ENA_S)
+#define RMT_CH2_TX_LOOP_INT_ENA_V  0x00000001U
+#define RMT_CH2_TX_LOOP_INT_ENA_S  14
+/** RMT_CH3_TX_LOOP_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for CH3_TX_LOOP_INT.
+ */
+#define RMT_CH3_TX_LOOP_INT_ENA    (BIT(15))
+#define RMT_CH3_TX_LOOP_INT_ENA_M  (RMT_CH3_TX_LOOP_INT_ENA_V << RMT_CH3_TX_LOOP_INT_ENA_S)
+#define RMT_CH3_TX_LOOP_INT_ENA_V  0x00000001U
+#define RMT_CH3_TX_LOOP_INT_ENA_S  15
+/** RMT_CH4_RX_END_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The interrupt enable bit for CH4_RX_END_INT.
+ */
+#define RMT_CH4_RX_END_INT_ENA    (BIT(16))
+#define RMT_CH4_RX_END_INT_ENA_M  (RMT_CH4_RX_END_INT_ENA_V << RMT_CH4_RX_END_INT_ENA_S)
+#define RMT_CH4_RX_END_INT_ENA_V  0x00000001U
+#define RMT_CH4_RX_END_INT_ENA_S  16
+/** RMT_CH5_RX_END_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The interrupt enable bit for CH5_RX_END_INT.
+ */
+#define RMT_CH5_RX_END_INT_ENA    (BIT(17))
+#define RMT_CH5_RX_END_INT_ENA_M  (RMT_CH5_RX_END_INT_ENA_V << RMT_CH5_RX_END_INT_ENA_S)
+#define RMT_CH5_RX_END_INT_ENA_V  0x00000001U
+#define RMT_CH5_RX_END_INT_ENA_S  17
+/** RMT_CH6_RX_END_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  The interrupt enable bit for CH6_RX_END_INT.
+ */
+#define RMT_CH6_RX_END_INT_ENA    (BIT(18))
+#define RMT_CH6_RX_END_INT_ENA_M  (RMT_CH6_RX_END_INT_ENA_V << RMT_CH6_RX_END_INT_ENA_S)
+#define RMT_CH6_RX_END_INT_ENA_V  0x00000001U
+#define RMT_CH6_RX_END_INT_ENA_S  18
+/** RMT_CH7_RX_END_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  The interrupt enable bit for CH7_RX_END_INT.
+ */
+#define RMT_CH7_RX_END_INT_ENA    (BIT(19))
+#define RMT_CH7_RX_END_INT_ENA_M  (RMT_CH7_RX_END_INT_ENA_V << RMT_CH7_RX_END_INT_ENA_S)
+#define RMT_CH7_RX_END_INT_ENA_V  0x00000001U
+#define RMT_CH7_RX_END_INT_ENA_S  19
+/** RMT_CH4_ERR_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  The interrupt enable bit for CH4_ERR_INT.
+ */
+#define RMT_CH4_ERR_INT_ENA    (BIT(20))
+#define RMT_CH4_ERR_INT_ENA_M  (RMT_CH4_ERR_INT_ENA_V << RMT_CH4_ERR_INT_ENA_S)
+#define RMT_CH4_ERR_INT_ENA_V  0x00000001U
+#define RMT_CH4_ERR_INT_ENA_S  20
+/** RMT_CH5_ERR_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  The interrupt enable bit for CH5_ERR_INT.
+ */
+#define RMT_CH5_ERR_INT_ENA    (BIT(21))
+#define RMT_CH5_ERR_INT_ENA_M  (RMT_CH5_ERR_INT_ENA_V << RMT_CH5_ERR_INT_ENA_S)
+#define RMT_CH5_ERR_INT_ENA_V  0x00000001U
+#define RMT_CH5_ERR_INT_ENA_S  21
+/** RMT_CH6_ERR_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  The interrupt enable bit for CH6_ERR_INT.
+ */
+#define RMT_CH6_ERR_INT_ENA    (BIT(22))
+#define RMT_CH6_ERR_INT_ENA_M  (RMT_CH6_ERR_INT_ENA_V << RMT_CH6_ERR_INT_ENA_S)
+#define RMT_CH6_ERR_INT_ENA_V  0x00000001U
+#define RMT_CH6_ERR_INT_ENA_S  22
+/** RMT_CH7_ERR_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  The interrupt enable bit for CH7_ERR_INT.
+ */
+#define RMT_CH7_ERR_INT_ENA    (BIT(23))
+#define RMT_CH7_ERR_INT_ENA_M  (RMT_CH7_ERR_INT_ENA_V << RMT_CH7_ERR_INT_ENA_S)
+#define RMT_CH7_ERR_INT_ENA_V  0x00000001U
+#define RMT_CH7_ERR_INT_ENA_S  23
+/** RMT_CH4_RX_THR_EVENT_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  The interrupt enable bit for CH4_RX_THR_EVENT_INT.
+ */
+#define RMT_CH4_RX_THR_EVENT_INT_ENA    (BIT(24))
+#define RMT_CH4_RX_THR_EVENT_INT_ENA_M  (RMT_CH4_RX_THR_EVENT_INT_ENA_V << RMT_CH4_RX_THR_EVENT_INT_ENA_S)
+#define RMT_CH4_RX_THR_EVENT_INT_ENA_V  0x00000001U
+#define RMT_CH4_RX_THR_EVENT_INT_ENA_S  24
+/** RMT_CH5_RX_THR_EVENT_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  The interrupt enable bit for CH5_RX_THR_EVENT_INT.
+ */
+#define RMT_CH5_RX_THR_EVENT_INT_ENA    (BIT(25))
+#define RMT_CH5_RX_THR_EVENT_INT_ENA_M  (RMT_CH5_RX_THR_EVENT_INT_ENA_V << RMT_CH5_RX_THR_EVENT_INT_ENA_S)
+#define RMT_CH5_RX_THR_EVENT_INT_ENA_V  0x00000001U
+#define RMT_CH5_RX_THR_EVENT_INT_ENA_S  25
+/** RMT_CH6_RX_THR_EVENT_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  The interrupt enable bit for CH6_RX_THR_EVENT_INT.
+ */
+#define RMT_CH6_RX_THR_EVENT_INT_ENA    (BIT(26))
+#define RMT_CH6_RX_THR_EVENT_INT_ENA_M  (RMT_CH6_RX_THR_EVENT_INT_ENA_V << RMT_CH6_RX_THR_EVENT_INT_ENA_S)
+#define RMT_CH6_RX_THR_EVENT_INT_ENA_V  0x00000001U
+#define RMT_CH6_RX_THR_EVENT_INT_ENA_S  26
+/** RMT_CH7_RX_THR_EVENT_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  The interrupt enable bit for CH7_RX_THR_EVENT_INT.
+ */
+#define RMT_CH7_RX_THR_EVENT_INT_ENA    (BIT(27))
+#define RMT_CH7_RX_THR_EVENT_INT_ENA_M  (RMT_CH7_RX_THR_EVENT_INT_ENA_V << RMT_CH7_RX_THR_EVENT_INT_ENA_S)
+#define RMT_CH7_RX_THR_EVENT_INT_ENA_V  0x00000001U
+#define RMT_CH7_RX_THR_EVENT_INT_ENA_S  27
+/** RMT_CH3_DMA_ACCESS_FAIL_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT.
+ */
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA    (BIT(28))
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_M  (RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_V << RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_S)
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_V  0x00000001U
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_S  28
+/** RMT_CH7_DMA_ACCESS_FAIL_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT.
+ */
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA    (BIT(29))
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_M  (RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_V << RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_S)
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_V  0x00000001U
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_S  29
+
+/** RMT_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x7c)
+/** RMT_CH0_TX_END_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear theCH0_TX_END_INT interrupt.
+ */
+#define RMT_CH0_TX_END_INT_CLR    (BIT(0))
+#define RMT_CH0_TX_END_INT_CLR_M  (RMT_CH0_TX_END_INT_CLR_V << RMT_CH0_TX_END_INT_CLR_S)
+#define RMT_CH0_TX_END_INT_CLR_V  0x00000001U
+#define RMT_CH0_TX_END_INT_CLR_S  0
+/** RMT_CH1_TX_END_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear theCH1_TX_END_INT interrupt.
+ */
+#define RMT_CH1_TX_END_INT_CLR    (BIT(1))
+#define RMT_CH1_TX_END_INT_CLR_M  (RMT_CH1_TX_END_INT_CLR_V << RMT_CH1_TX_END_INT_CLR_S)
+#define RMT_CH1_TX_END_INT_CLR_V  0x00000001U
+#define RMT_CH1_TX_END_INT_CLR_S  1
+/** RMT_CH2_TX_END_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear theCH2_TX_END_INT interrupt.
+ */
+#define RMT_CH2_TX_END_INT_CLR    (BIT(2))
+#define RMT_CH2_TX_END_INT_CLR_M  (RMT_CH2_TX_END_INT_CLR_V << RMT_CH2_TX_END_INT_CLR_S)
+#define RMT_CH2_TX_END_INT_CLR_V  0x00000001U
+#define RMT_CH2_TX_END_INT_CLR_S  2
+/** RMT_CH3_TX_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear theCH3_TX_END_INT interrupt.
+ */
+#define RMT_CH3_TX_END_INT_CLR    (BIT(3))
+#define RMT_CH3_TX_END_INT_CLR_M  (RMT_CH3_TX_END_INT_CLR_V << RMT_CH3_TX_END_INT_CLR_S)
+#define RMT_CH3_TX_END_INT_CLR_V  0x00000001U
+#define RMT_CH3_TX_END_INT_CLR_S  3
+/** RMT_CH0_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear theCH0_ERR_INT interrupt.
+ */
+#define RMT_CH0_ERR_INT_CLR    (BIT(4))
+#define RMT_CH0_ERR_INT_CLR_M  (RMT_CH0_ERR_INT_CLR_V << RMT_CH0_ERR_INT_CLR_S)
+#define RMT_CH0_ERR_INT_CLR_V  0x00000001U
+#define RMT_CH0_ERR_INT_CLR_S  4
+/** RMT_CH1_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear theCH1_ERR_INT interrupt.
+ */
+#define RMT_CH1_ERR_INT_CLR    (BIT(5))
+#define RMT_CH1_ERR_INT_CLR_M  (RMT_CH1_ERR_INT_CLR_V << RMT_CH1_ERR_INT_CLR_S)
+#define RMT_CH1_ERR_INT_CLR_V  0x00000001U
+#define RMT_CH1_ERR_INT_CLR_S  5
+/** RMT_CH2_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear theCH2_ERR_INT interrupt.
+ */
+#define RMT_CH2_ERR_INT_CLR    (BIT(6))
+#define RMT_CH2_ERR_INT_CLR_M  (RMT_CH2_ERR_INT_CLR_V << RMT_CH2_ERR_INT_CLR_S)
+#define RMT_CH2_ERR_INT_CLR_V  0x00000001U
+#define RMT_CH2_ERR_INT_CLR_S  6
+/** RMT_CH3_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear theCH3_ERR_INT interrupt.
+ */
+#define RMT_CH3_ERR_INT_CLR    (BIT(7))
+#define RMT_CH3_ERR_INT_CLR_M  (RMT_CH3_ERR_INT_CLR_V << RMT_CH3_ERR_INT_CLR_S)
+#define RMT_CH3_ERR_INT_CLR_V  0x00000001U
+#define RMT_CH3_ERR_INT_CLR_S  7
+/** RMT_CH0_TX_THR_EVENT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
+ */
+#define RMT_CH0_TX_THR_EVENT_INT_CLR    (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_M  (RMT_CH0_TX_THR_EVENT_INT_CLR_V << RMT_CH0_TX_THR_EVENT_INT_CLR_S)
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_V  0x00000001U
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_S  8
+/** RMT_CH1_TX_THR_EVENT_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
+ */
+#define RMT_CH1_TX_THR_EVENT_INT_CLR    (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_M  (RMT_CH1_TX_THR_EVENT_INT_CLR_V << RMT_CH1_TX_THR_EVENT_INT_CLR_S)
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_V  0x00000001U
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_S  9
+/** RMT_CH2_TX_THR_EVENT_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt.
+ */
+#define RMT_CH2_TX_THR_EVENT_INT_CLR    (BIT(10))
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_M  (RMT_CH2_TX_THR_EVENT_INT_CLR_V << RMT_CH2_TX_THR_EVENT_INT_CLR_S)
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_V  0x00000001U
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_S  10
+/** RMT_CH3_TX_THR_EVENT_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt.
+ */
+#define RMT_CH3_TX_THR_EVENT_INT_CLR    (BIT(11))
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_M  (RMT_CH3_TX_THR_EVENT_INT_CLR_V << RMT_CH3_TX_THR_EVENT_INT_CLR_S)
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_V  0x00000001U
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_S  11
+/** RMT_CH0_TX_LOOP_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear theCH0_TX_LOOP_INT interrupt.
+ */
+#define RMT_CH0_TX_LOOP_INT_CLR    (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_CLR_M  (RMT_CH0_TX_LOOP_INT_CLR_V << RMT_CH0_TX_LOOP_INT_CLR_S)
+#define RMT_CH0_TX_LOOP_INT_CLR_V  0x00000001U
+#define RMT_CH0_TX_LOOP_INT_CLR_S  12
+/** RMT_CH1_TX_LOOP_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear theCH1_TX_LOOP_INT interrupt.
+ */
+#define RMT_CH1_TX_LOOP_INT_CLR    (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_CLR_M  (RMT_CH1_TX_LOOP_INT_CLR_V << RMT_CH1_TX_LOOP_INT_CLR_S)
+#define RMT_CH1_TX_LOOP_INT_CLR_V  0x00000001U
+#define RMT_CH1_TX_LOOP_INT_CLR_S  13
+/** RMT_CH2_TX_LOOP_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear theCH2_TX_LOOP_INT interrupt.
+ */
+#define RMT_CH2_TX_LOOP_INT_CLR    (BIT(14))
+#define RMT_CH2_TX_LOOP_INT_CLR_M  (RMT_CH2_TX_LOOP_INT_CLR_V << RMT_CH2_TX_LOOP_INT_CLR_S)
+#define RMT_CH2_TX_LOOP_INT_CLR_V  0x00000001U
+#define RMT_CH2_TX_LOOP_INT_CLR_S  14
+/** RMT_CH3_TX_LOOP_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear theCH3_TX_LOOP_INT interrupt.
+ */
+#define RMT_CH3_TX_LOOP_INT_CLR    (BIT(15))
+#define RMT_CH3_TX_LOOP_INT_CLR_M  (RMT_CH3_TX_LOOP_INT_CLR_V << RMT_CH3_TX_LOOP_INT_CLR_S)
+#define RMT_CH3_TX_LOOP_INT_CLR_V  0x00000001U
+#define RMT_CH3_TX_LOOP_INT_CLR_S  15
+/** RMT_CH4_RX_END_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear theCH4_RX_END_INT interrupt.
+ */
+#define RMT_CH4_RX_END_INT_CLR    (BIT(16))
+#define RMT_CH4_RX_END_INT_CLR_M  (RMT_CH4_RX_END_INT_CLR_V << RMT_CH4_RX_END_INT_CLR_S)
+#define RMT_CH4_RX_END_INT_CLR_V  0x00000001U
+#define RMT_CH4_RX_END_INT_CLR_S  16
+/** RMT_CH5_RX_END_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear theCH5_RX_END_INT interrupt.
+ */
+#define RMT_CH5_RX_END_INT_CLR    (BIT(17))
+#define RMT_CH5_RX_END_INT_CLR_M  (RMT_CH5_RX_END_INT_CLR_V << RMT_CH5_RX_END_INT_CLR_S)
+#define RMT_CH5_RX_END_INT_CLR_V  0x00000001U
+#define RMT_CH5_RX_END_INT_CLR_S  17
+/** RMT_CH6_RX_END_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear theCH6_RX_END_INT interrupt.
+ */
+#define RMT_CH6_RX_END_INT_CLR    (BIT(18))
+#define RMT_CH6_RX_END_INT_CLR_M  (RMT_CH6_RX_END_INT_CLR_V << RMT_CH6_RX_END_INT_CLR_S)
+#define RMT_CH6_RX_END_INT_CLR_V  0x00000001U
+#define RMT_CH6_RX_END_INT_CLR_S  18
+/** RMT_CH7_RX_END_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear theCH7_RX_END_INT interrupt.
+ */
+#define RMT_CH7_RX_END_INT_CLR    (BIT(19))
+#define RMT_CH7_RX_END_INT_CLR_M  (RMT_CH7_RX_END_INT_CLR_V << RMT_CH7_RX_END_INT_CLR_S)
+#define RMT_CH7_RX_END_INT_CLR_V  0x00000001U
+#define RMT_CH7_RX_END_INT_CLR_S  19
+/** RMT_CH4_ERR_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  Set this bit to clear theCH4_ERR_INT interrupt.
+ */
+#define RMT_CH4_ERR_INT_CLR    (BIT(20))
+#define RMT_CH4_ERR_INT_CLR_M  (RMT_CH4_ERR_INT_CLR_V << RMT_CH4_ERR_INT_CLR_S)
+#define RMT_CH4_ERR_INT_CLR_V  0x00000001U
+#define RMT_CH4_ERR_INT_CLR_S  20
+/** RMT_CH5_ERR_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  Set this bit to clear theCH5_ERR_INT interrupt.
+ */
+#define RMT_CH5_ERR_INT_CLR    (BIT(21))
+#define RMT_CH5_ERR_INT_CLR_M  (RMT_CH5_ERR_INT_CLR_V << RMT_CH5_ERR_INT_CLR_S)
+#define RMT_CH5_ERR_INT_CLR_V  0x00000001U
+#define RMT_CH5_ERR_INT_CLR_S  21
+/** RMT_CH6_ERR_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  Set this bit to clear theCH6_ERR_INT interrupt.
+ */
+#define RMT_CH6_ERR_INT_CLR    (BIT(22))
+#define RMT_CH6_ERR_INT_CLR_M  (RMT_CH6_ERR_INT_CLR_V << RMT_CH6_ERR_INT_CLR_S)
+#define RMT_CH6_ERR_INT_CLR_V  0x00000001U
+#define RMT_CH6_ERR_INT_CLR_S  22
+/** RMT_CH7_ERR_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  Set this bit to clear theCH7_ERR_INT interrupt.
+ */
+#define RMT_CH7_ERR_INT_CLR    (BIT(23))
+#define RMT_CH7_ERR_INT_CLR_M  (RMT_CH7_ERR_INT_CLR_V << RMT_CH7_ERR_INT_CLR_S)
+#define RMT_CH7_ERR_INT_CLR_V  0x00000001U
+#define RMT_CH7_ERR_INT_CLR_S  23
+/** RMT_CH4_RX_THR_EVENT_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt.
+ */
+#define RMT_CH4_RX_THR_EVENT_INT_CLR    (BIT(24))
+#define RMT_CH4_RX_THR_EVENT_INT_CLR_M  (RMT_CH4_RX_THR_EVENT_INT_CLR_V << RMT_CH4_RX_THR_EVENT_INT_CLR_S)
+#define RMT_CH4_RX_THR_EVENT_INT_CLR_V  0x00000001U
+#define RMT_CH4_RX_THR_EVENT_INT_CLR_S  24
+/** RMT_CH5_RX_THR_EVENT_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt.
+ */
+#define RMT_CH5_RX_THR_EVENT_INT_CLR    (BIT(25))
+#define RMT_CH5_RX_THR_EVENT_INT_CLR_M  (RMT_CH5_RX_THR_EVENT_INT_CLR_V << RMT_CH5_RX_THR_EVENT_INT_CLR_S)
+#define RMT_CH5_RX_THR_EVENT_INT_CLR_V  0x00000001U
+#define RMT_CH5_RX_THR_EVENT_INT_CLR_S  25
+/** RMT_CH6_RX_THR_EVENT_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt.
+ */
+#define RMT_CH6_RX_THR_EVENT_INT_CLR    (BIT(26))
+#define RMT_CH6_RX_THR_EVENT_INT_CLR_M  (RMT_CH6_RX_THR_EVENT_INT_CLR_V << RMT_CH6_RX_THR_EVENT_INT_CLR_S)
+#define RMT_CH6_RX_THR_EVENT_INT_CLR_V  0x00000001U
+#define RMT_CH6_RX_THR_EVENT_INT_CLR_S  26
+/** RMT_CH7_RX_THR_EVENT_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt.
+ */
+#define RMT_CH7_RX_THR_EVENT_INT_CLR    (BIT(27))
+#define RMT_CH7_RX_THR_EVENT_INT_CLR_M  (RMT_CH7_RX_THR_EVENT_INT_CLR_V << RMT_CH7_RX_THR_EVENT_INT_CLR_S)
+#define RMT_CH7_RX_THR_EVENT_INT_CLR_V  0x00000001U
+#define RMT_CH7_RX_THR_EVENT_INT_CLR_S  27
+/** RMT_CH3_DMA_ACCESS_FAIL_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt.
+ */
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR    (BIT(28))
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_M  (RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_V << RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_S)
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_V  0x00000001U
+#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_S  28
+/** RMT_CH7_DMA_ACCESS_FAIL_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt.
+ */
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR    (BIT(29))
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_M  (RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_V << RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_S)
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_V  0x00000001U
+#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_S  29
+
+/** RMT_CH0CARRIER_DUTY_REG register
+ *  Channel 0 duty cycle configuration register
+ */
+#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x80)
+/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64;
+ *  This register is used to configure carrier wave 's low level clock period for
+ *  CHANNEL0.
+ */
+#define RMT_CARRIER_LOW_CH0    0x0000FFFFU
+#define RMT_CARRIER_LOW_CH0_M  (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S)
+#define RMT_CARRIER_LOW_CH0_V  0x0000FFFFU
+#define RMT_CARRIER_LOW_CH0_S  0
+/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64;
+ *  This register is used to configure carrier wave 's high level clock period for
+ *  CHANNEL0.
+ */
+#define RMT_CARRIER_HIGH_CH0    0x0000FFFFU
+#define RMT_CARRIER_HIGH_CH0_M  (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S)
+#define RMT_CARRIER_HIGH_CH0_V  0x0000FFFFU
+#define RMT_CARRIER_HIGH_CH0_S  16
+
+/** RMT_CH1CARRIER_DUTY_REG register
+ *  Channel 1 duty cycle configuration register
+ */
+#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x84)
+/** RMT_CARRIER_LOW_CH1 : R/W; bitpos: [15:0]; default: 64;
+ *  This register is used to configure carrier wave 's low level clock period for
+ *  CHANNEL1.
+ */
+#define RMT_CARRIER_LOW_CH1    0x0000FFFFU
+#define RMT_CARRIER_LOW_CH1_M  (RMT_CARRIER_LOW_CH1_V << RMT_CARRIER_LOW_CH1_S)
+#define RMT_CARRIER_LOW_CH1_V  0x0000FFFFU
+#define RMT_CARRIER_LOW_CH1_S  0
+/** RMT_CARRIER_HIGH_CH1 : R/W; bitpos: [31:16]; default: 64;
+ *  This register is used to configure carrier wave 's high level clock period for
+ *  CHANNEL1.
+ */
+#define RMT_CARRIER_HIGH_CH1    0x0000FFFFU
+#define RMT_CARRIER_HIGH_CH1_M  (RMT_CARRIER_HIGH_CH1_V << RMT_CARRIER_HIGH_CH1_S)
+#define RMT_CARRIER_HIGH_CH1_V  0x0000FFFFU
+#define RMT_CARRIER_HIGH_CH1_S  16
+
+/** RMT_CH2CARRIER_DUTY_REG register
+ *  Channel 2 duty cycle configuration register
+ */
+#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x88)
+/** RMT_CARRIER_LOW_CH2 : R/W; bitpos: [15:0]; default: 64;
+ *  This register is used to configure carrier wave 's low level clock period for
+ *  CHANNEL2.
+ */
+#define RMT_CARRIER_LOW_CH2    0x0000FFFFU
+#define RMT_CARRIER_LOW_CH2_M  (RMT_CARRIER_LOW_CH2_V << RMT_CARRIER_LOW_CH2_S)
+#define RMT_CARRIER_LOW_CH2_V  0x0000FFFFU
+#define RMT_CARRIER_LOW_CH2_S  0
+/** RMT_CARRIER_HIGH_CH2 : R/W; bitpos: [31:16]; default: 64;
+ *  This register is used to configure carrier wave 's high level clock period for
+ *  CHANNEL2.
+ */
+#define RMT_CARRIER_HIGH_CH2    0x0000FFFFU
+#define RMT_CARRIER_HIGH_CH2_M  (RMT_CARRIER_HIGH_CH2_V << RMT_CARRIER_HIGH_CH2_S)
+#define RMT_CARRIER_HIGH_CH2_V  0x0000FFFFU
+#define RMT_CARRIER_HIGH_CH2_S  16
+
+/** RMT_CH3CARRIER_DUTY_REG register
+ *  Channel 3 duty cycle configuration register
+ */
+#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x8c)
+/** RMT_CARRIER_LOW_CH3 : R/W; bitpos: [15:0]; default: 64;
+ *  This register is used to configure carrier wave 's low level clock period for
+ *  CHANNEL3.
+ */
+#define RMT_CARRIER_LOW_CH3    0x0000FFFFU
+#define RMT_CARRIER_LOW_CH3_M  (RMT_CARRIER_LOW_CH3_V << RMT_CARRIER_LOW_CH3_S)
+#define RMT_CARRIER_LOW_CH3_V  0x0000FFFFU
+#define RMT_CARRIER_LOW_CH3_S  0
+/** RMT_CARRIER_HIGH_CH3 : R/W; bitpos: [31:16]; default: 64;
+ *  This register is used to configure carrier wave 's high level clock period for
+ *  CHANNEL3.
+ */
+#define RMT_CARRIER_HIGH_CH3    0x0000FFFFU
+#define RMT_CARRIER_HIGH_CH3_M  (RMT_CARRIER_HIGH_CH3_V << RMT_CARRIER_HIGH_CH3_S)
+#define RMT_CARRIER_HIGH_CH3_V  0x0000FFFFU
+#define RMT_CARRIER_HIGH_CH3_S  16
+
+/** RMT_CH4_RX_CARRIER_RM_REG register
+ *  Channel 4 carrier remove register
+ */
+#define RMT_CH4_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x90)
+/** RMT_CARRIER_LOW_THRES_CH4 : R/W; bitpos: [15:0]; default: 0;
+ *  The low level period in a carrier modulation mode is
+ *  (REG_RMT_REG_CARRIER_LOW_THRES_CH4 + 1) for channel 4.
+ */
+#define RMT_CARRIER_LOW_THRES_CH4    0x0000FFFFU
+#define RMT_CARRIER_LOW_THRES_CH4_M  (RMT_CARRIER_LOW_THRES_CH4_V << RMT_CARRIER_LOW_THRES_CH4_S)
+#define RMT_CARRIER_LOW_THRES_CH4_V  0x0000FFFFU
+#define RMT_CARRIER_LOW_THRES_CH4_S  0
+/** RMT_CARRIER_HIGH_THRES_CH4 : R/W; bitpos: [31:16]; default: 0;
+ *  The high level period in a carrier modulation mode is
+ *  (REG_RMT_REG_CARRIER_HIGH_THRES_CH4 + 1) for channel 4.
+ */
+#define RMT_CARRIER_HIGH_THRES_CH4    0x0000FFFFU
+#define RMT_CARRIER_HIGH_THRES_CH4_M  (RMT_CARRIER_HIGH_THRES_CH4_V << RMT_CARRIER_HIGH_THRES_CH4_S)
+#define RMT_CARRIER_HIGH_THRES_CH4_V  0x0000FFFFU
+#define RMT_CARRIER_HIGH_THRES_CH4_S  16
+
+/** RMT_CH5_RX_CARRIER_RM_REG register
+ *  Channel 5 carrier remove register
+ */
+#define RMT_CH5_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x94)
+/** RMT_CARRIER_LOW_THRES_CH5 : R/W; bitpos: [15:0]; default: 0;
+ *  The low level period in a carrier modulation mode is
+ *  (REG_RMT_REG_CARRIER_LOW_THRES_CH5 + 1) for channel 5.
+ */
+#define RMT_CARRIER_LOW_THRES_CH5    0x0000FFFFU
+#define RMT_CARRIER_LOW_THRES_CH5_M  (RMT_CARRIER_LOW_THRES_CH5_V << RMT_CARRIER_LOW_THRES_CH5_S)
+#define RMT_CARRIER_LOW_THRES_CH5_V  0x0000FFFFU
+#define RMT_CARRIER_LOW_THRES_CH5_S  0
+/** RMT_CARRIER_HIGH_THRES_CH5 : R/W; bitpos: [31:16]; default: 0;
+ *  The high level period in a carrier modulation mode is
+ *  (REG_RMT_REG_CARRIER_HIGH_THRES_CH5 + 1) for channel 5.
+ */
+#define RMT_CARRIER_HIGH_THRES_CH5    0x0000FFFFU
+#define RMT_CARRIER_HIGH_THRES_CH5_M  (RMT_CARRIER_HIGH_THRES_CH5_V << RMT_CARRIER_HIGH_THRES_CH5_S)
+#define RMT_CARRIER_HIGH_THRES_CH5_V  0x0000FFFFU
+#define RMT_CARRIER_HIGH_THRES_CH5_S  16
+
+/** RMT_CH6_RX_CARRIER_RM_REG register
+ *  Channel 6 carrier remove register
+ */
+#define RMT_CH6_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x98)
+/** RMT_CARRIER_LOW_THRES_CH6 : R/W; bitpos: [15:0]; default: 0;
+ *  The low level period in a carrier modulation mode is
+ *  (REG_RMT_REG_CARRIER_LOW_THRES_CH6 + 1) for channel 6.
+ */
+#define RMT_CARRIER_LOW_THRES_CH6    0x0000FFFFU
+#define RMT_CARRIER_LOW_THRES_CH6_M  (RMT_CARRIER_LOW_THRES_CH6_V << RMT_CARRIER_LOW_THRES_CH6_S)
+#define RMT_CARRIER_LOW_THRES_CH6_V  0x0000FFFFU
+#define RMT_CARRIER_LOW_THRES_CH6_S  0
+/** RMT_CARRIER_HIGH_THRES_CH6 : R/W; bitpos: [31:16]; default: 0;
+ *  The high level period in a carrier modulation mode is
+ *  (REG_RMT_REG_CARRIER_HIGH_THRES_CH6 + 1) for channel 6.
+ */
+#define RMT_CARRIER_HIGH_THRES_CH6    0x0000FFFFU
+#define RMT_CARRIER_HIGH_THRES_CH6_M  (RMT_CARRIER_HIGH_THRES_CH6_V << RMT_CARRIER_HIGH_THRES_CH6_S)
+#define RMT_CARRIER_HIGH_THRES_CH6_V  0x0000FFFFU
+#define RMT_CARRIER_HIGH_THRES_CH6_S  16
+
+/** RMT_CH7_RX_CARRIER_RM_REG register
+ *  Channel 7 carrier remove register
+ */
+#define RMT_CH7_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x9c)
+/** RMT_CARRIER_LOW_THRES_CH7 : R/W; bitpos: [15:0]; default: 0;
+ *  The low level period in a carrier modulation mode is
+ *  (REG_RMT_REG_CARRIER_LOW_THRES_CH7 + 1) for channel 7.
+ */
+#define RMT_CARRIER_LOW_THRES_CH7    0x0000FFFFU
+#define RMT_CARRIER_LOW_THRES_CH7_M  (RMT_CARRIER_LOW_THRES_CH7_V << RMT_CARRIER_LOW_THRES_CH7_S)
+#define RMT_CARRIER_LOW_THRES_CH7_V  0x0000FFFFU
+#define RMT_CARRIER_LOW_THRES_CH7_S  0
+/** RMT_CARRIER_HIGH_THRES_CH7 : R/W; bitpos: [31:16]; default: 0;
+ *  The high level period in a carrier modulation mode is
+ *  (REG_RMT_REG_CARRIER_HIGH_THRES_CH7 + 1) for channel 7.
+ */
+#define RMT_CARRIER_HIGH_THRES_CH7    0x0000FFFFU
+#define RMT_CARRIER_HIGH_THRES_CH7_M  (RMT_CARRIER_HIGH_THRES_CH7_V << RMT_CARRIER_HIGH_THRES_CH7_S)
+#define RMT_CARRIER_HIGH_THRES_CH7_V  0x0000FFFFU
+#define RMT_CARRIER_HIGH_THRES_CH7_S  16
+
+/** RMT_CH0_TX_LIM_REG register
+ *  Channel 0 Tx event configuration register
+ */
+#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0xa0)
+/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128;
+ *  This register is used to configure the maximum entries that CHANNEL0 can send out.
+ */
+#define RMT_TX_LIM_CH0    0x000001FFU
+#define RMT_TX_LIM_CH0_M  (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S)
+#define RMT_TX_LIM_CH0_V  0x000001FFU
+#define RMT_TX_LIM_CH0_S  0
+/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0;
+ *  This register is used to configure the maximum loop count when tx_conti_mode is
+ *  valid.
+ */
+#define RMT_TX_LOOP_NUM_CH0    0x000003FFU
+#define RMT_TX_LOOP_NUM_CH0_M  (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S)
+#define RMT_TX_LOOP_NUM_CH0_V  0x000003FFU
+#define RMT_TX_LOOP_NUM_CH0_S  9
+/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0;
+ *  This register is the enabled bit for loop count.
+ */
+#define RMT_TX_LOOP_CNT_EN_CH0    (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH0_M  (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S)
+#define RMT_TX_LOOP_CNT_EN_CH0_V  0x00000001U
+#define RMT_TX_LOOP_CNT_EN_CH0_S  19
+/** RMT_LOOP_COUNT_RESET_CH0 : WT; bitpos: [20]; default: 0;
+ *  This register is used to reset the loop count when tx_conti_mode is valid.
+ */
+#define RMT_LOOP_COUNT_RESET_CH0    (BIT(20))
+#define RMT_LOOP_COUNT_RESET_CH0_M  (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S)
+#define RMT_LOOP_COUNT_RESET_CH0_V  0x00000001U
+#define RMT_LOOP_COUNT_RESET_CH0_S  20
+/** RMT_LOOP_STOP_EN_CH0 : R/W; bitpos: [21]; default: 0;
+ *  This bit is used to enable the loop send stop function after the loop counter
+ *  counts to  loop number for CHANNEL0.
+ */
+#define RMT_LOOP_STOP_EN_CH0    (BIT(21))
+#define RMT_LOOP_STOP_EN_CH0_M  (RMT_LOOP_STOP_EN_CH0_V << RMT_LOOP_STOP_EN_CH0_S)
+#define RMT_LOOP_STOP_EN_CH0_V  0x00000001U
+#define RMT_LOOP_STOP_EN_CH0_S  21
+
+/** RMT_CH1_TX_LIM_REG register
+ *  Channel 1 Tx event configuration register
+ */
+#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0xa4)
+/** RMT_TX_LIM_CH1 : R/W; bitpos: [8:0]; default: 128;
+ *  This register is used to configure the maximum entries that CHANNEL1 can send out.
+ */
+#define RMT_TX_LIM_CH1    0x000001FFU
+#define RMT_TX_LIM_CH1_M  (RMT_TX_LIM_CH1_V << RMT_TX_LIM_CH1_S)
+#define RMT_TX_LIM_CH1_V  0x000001FFU
+#define RMT_TX_LIM_CH1_S  0
+/** RMT_TX_LOOP_NUM_CH1 : R/W; bitpos: [18:9]; default: 0;
+ *  This register is used to configure the maximum loop count when tx_conti_mode is
+ *  valid.
+ */
+#define RMT_TX_LOOP_NUM_CH1    0x000003FFU
+#define RMT_TX_LOOP_NUM_CH1_M  (RMT_TX_LOOP_NUM_CH1_V << RMT_TX_LOOP_NUM_CH1_S)
+#define RMT_TX_LOOP_NUM_CH1_V  0x000003FFU
+#define RMT_TX_LOOP_NUM_CH1_S  9
+/** RMT_TX_LOOP_CNT_EN_CH1 : R/W; bitpos: [19]; default: 0;
+ *  This register is the enabled bit for loop count.
+ */
+#define RMT_TX_LOOP_CNT_EN_CH1    (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH1_M  (RMT_TX_LOOP_CNT_EN_CH1_V << RMT_TX_LOOP_CNT_EN_CH1_S)
+#define RMT_TX_LOOP_CNT_EN_CH1_V  0x00000001U
+#define RMT_TX_LOOP_CNT_EN_CH1_S  19
+/** RMT_LOOP_COUNT_RESET_CH1 : WT; bitpos: [20]; default: 0;
+ *  This register is used to reset the loop count when tx_conti_mode is valid.
+ */
+#define RMT_LOOP_COUNT_RESET_CH1    (BIT(20))
+#define RMT_LOOP_COUNT_RESET_CH1_M  (RMT_LOOP_COUNT_RESET_CH1_V << RMT_LOOP_COUNT_RESET_CH1_S)
+#define RMT_LOOP_COUNT_RESET_CH1_V  0x00000001U
+#define RMT_LOOP_COUNT_RESET_CH1_S  20
+/** RMT_LOOP_STOP_EN_CH1 : R/W; bitpos: [21]; default: 0;
+ *  This bit is used to enable the loop send stop function after the loop counter
+ *  counts to  loop number for CHANNEL1.
+ */
+#define RMT_LOOP_STOP_EN_CH1    (BIT(21))
+#define RMT_LOOP_STOP_EN_CH1_M  (RMT_LOOP_STOP_EN_CH1_V << RMT_LOOP_STOP_EN_CH1_S)
+#define RMT_LOOP_STOP_EN_CH1_V  0x00000001U
+#define RMT_LOOP_STOP_EN_CH1_S  21
+
+/** RMT_CH2_TX_LIM_REG register
+ *  Channel 2 Tx event configuration register
+ */
+#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0xa8)
+/** RMT_TX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128;
+ *  This register is used to configure the maximum entries that CHANNEL2 can send out.
+ */
+#define RMT_TX_LIM_CH2    0x000001FFU
+#define RMT_TX_LIM_CH2_M  (RMT_TX_LIM_CH2_V << RMT_TX_LIM_CH2_S)
+#define RMT_TX_LIM_CH2_V  0x000001FFU
+#define RMT_TX_LIM_CH2_S  0
+/** RMT_TX_LOOP_NUM_CH2 : R/W; bitpos: [18:9]; default: 0;
+ *  This register is used to configure the maximum loop count when tx_conti_mode is
+ *  valid.
+ */
+#define RMT_TX_LOOP_NUM_CH2    0x000003FFU
+#define RMT_TX_LOOP_NUM_CH2_M  (RMT_TX_LOOP_NUM_CH2_V << RMT_TX_LOOP_NUM_CH2_S)
+#define RMT_TX_LOOP_NUM_CH2_V  0x000003FFU
+#define RMT_TX_LOOP_NUM_CH2_S  9
+/** RMT_TX_LOOP_CNT_EN_CH2 : R/W; bitpos: [19]; default: 0;
+ *  This register is the enabled bit for loop count.
+ */
+#define RMT_TX_LOOP_CNT_EN_CH2    (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH2_M  (RMT_TX_LOOP_CNT_EN_CH2_V << RMT_TX_LOOP_CNT_EN_CH2_S)
+#define RMT_TX_LOOP_CNT_EN_CH2_V  0x00000001U
+#define RMT_TX_LOOP_CNT_EN_CH2_S  19
+/** RMT_LOOP_COUNT_RESET_CH2 : WT; bitpos: [20]; default: 0;
+ *  This register is used to reset the loop count when tx_conti_mode is valid.
+ */
+#define RMT_LOOP_COUNT_RESET_CH2    (BIT(20))
+#define RMT_LOOP_COUNT_RESET_CH2_M  (RMT_LOOP_COUNT_RESET_CH2_V << RMT_LOOP_COUNT_RESET_CH2_S)
+#define RMT_LOOP_COUNT_RESET_CH2_V  0x00000001U
+#define RMT_LOOP_COUNT_RESET_CH2_S  20
+/** RMT_LOOP_STOP_EN_CH2 : R/W; bitpos: [21]; default: 0;
+ *  This bit is used to enable the loop send stop function after the loop counter
+ *  counts to  loop number for CHANNEL2.
+ */
+#define RMT_LOOP_STOP_EN_CH2    (BIT(21))
+#define RMT_LOOP_STOP_EN_CH2_M  (RMT_LOOP_STOP_EN_CH2_V << RMT_LOOP_STOP_EN_CH2_S)
+#define RMT_LOOP_STOP_EN_CH2_V  0x00000001U
+#define RMT_LOOP_STOP_EN_CH2_S  21
+
+/** RMT_CH3_TX_LIM_REG register
+ *  Channel 3 Tx event configuration register
+ */
+#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0xac)
+/** RMT_TX_LIM_CH3 : R/W; bitpos: [8:0]; default: 128;
+ *  This register is used to configure the maximum entries that CHANNEL3 can send out.
+ */
+#define RMT_TX_LIM_CH3    0x000001FFU
+#define RMT_TX_LIM_CH3_M  (RMT_TX_LIM_CH3_V << RMT_TX_LIM_CH3_S)
+#define RMT_TX_LIM_CH3_V  0x000001FFU
+#define RMT_TX_LIM_CH3_S  0
+/** RMT_TX_LOOP_NUM_CH3 : R/W; bitpos: [18:9]; default: 0;
+ *  This register is used to configure the maximum loop count when tx_conti_mode is
+ *  valid.
+ */
+#define RMT_TX_LOOP_NUM_CH3    0x000003FFU
+#define RMT_TX_LOOP_NUM_CH3_M  (RMT_TX_LOOP_NUM_CH3_V << RMT_TX_LOOP_NUM_CH3_S)
+#define RMT_TX_LOOP_NUM_CH3_V  0x000003FFU
+#define RMT_TX_LOOP_NUM_CH3_S  9
+/** RMT_TX_LOOP_CNT_EN_CH3 : R/W; bitpos: [19]; default: 0;
+ *  This register is the enabled bit for loop count.
+ */
+#define RMT_TX_LOOP_CNT_EN_CH3    (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH3_M  (RMT_TX_LOOP_CNT_EN_CH3_V << RMT_TX_LOOP_CNT_EN_CH3_S)
+#define RMT_TX_LOOP_CNT_EN_CH3_V  0x00000001U
+#define RMT_TX_LOOP_CNT_EN_CH3_S  19
+/** RMT_LOOP_COUNT_RESET_CH3 : WT; bitpos: [20]; default: 0;
+ *  This register is used to reset the loop count when tx_conti_mode is valid.
+ */
+#define RMT_LOOP_COUNT_RESET_CH3    (BIT(20))
+#define RMT_LOOP_COUNT_RESET_CH3_M  (RMT_LOOP_COUNT_RESET_CH3_V << RMT_LOOP_COUNT_RESET_CH3_S)
+#define RMT_LOOP_COUNT_RESET_CH3_V  0x00000001U
+#define RMT_LOOP_COUNT_RESET_CH3_S  20
+/** RMT_LOOP_STOP_EN_CH3 : R/W; bitpos: [21]; default: 0;
+ *  This bit is used to enable the loop send stop function after the loop counter
+ *  counts to  loop number for CHANNEL3.
+ */
+#define RMT_LOOP_STOP_EN_CH3    (BIT(21))
+#define RMT_LOOP_STOP_EN_CH3_M  (RMT_LOOP_STOP_EN_CH3_V << RMT_LOOP_STOP_EN_CH3_S)
+#define RMT_LOOP_STOP_EN_CH3_V  0x00000001U
+#define RMT_LOOP_STOP_EN_CH3_S  21
+
+/** RMT_CH4_RX_LIM_REG register
+ *  Channel 4 Rx event configuration register
+ */
+#define RMT_CH4_RX_LIM_REG (DR_REG_RMT_BASE + 0xb0)
+/** RMT_CH4_RX_LIM : R/W; bitpos: [8:0]; default: 128;
+ *  This register is used to configure the maximum entries that CHANNEL4 can receive.
+ */
+#define RMT_CH4_RX_LIM    0x000001FFU
+#define RMT_CH4_RX_LIM_M  (RMT_CH4_RX_LIM_V << RMT_CH4_RX_LIM_S)
+#define RMT_CH4_RX_LIM_V  0x000001FFU
+#define RMT_CH4_RX_LIM_S  0
+
+/** RMT_CH5_RX_LIM_REG register
+ *  Channel 5 Rx event configuration register
+ */
+#define RMT_CH5_RX_LIM_REG (DR_REG_RMT_BASE + 0xb4)
+/** RMT_CH5_RX_LIM : R/W; bitpos: [8:0]; default: 128;
+ *  This register is used to configure the maximum entries that CHANNEL5 can receive.
+ */
+#define RMT_CH5_RX_LIM    0x000001FFU
+#define RMT_CH5_RX_LIM_M  (RMT_CH5_RX_LIM_V << RMT_CH5_RX_LIM_S)
+#define RMT_CH5_RX_LIM_V  0x000001FFU
+#define RMT_CH5_RX_LIM_S  0
+
+/** RMT_CH6_RX_LIM_REG register
+ *  Channel 6 Rx event configuration register
+ */
+#define RMT_CH6_RX_LIM_REG (DR_REG_RMT_BASE + 0xb8)
+/** RMT_CH6_RX_LIM : R/W; bitpos: [8:0]; default: 128;
+ *  This register is used to configure the maximum entries that CHANNEL6 can receive.
+ */
+#define RMT_CH6_RX_LIM    0x000001FFU
+#define RMT_CH6_RX_LIM_M  (RMT_CH6_RX_LIM_V << RMT_CH6_RX_LIM_S)
+#define RMT_CH6_RX_LIM_V  0x000001FFU
+#define RMT_CH6_RX_LIM_S  0
+
+/** RMT_CH7_RX_LIM_REG register
+ *  Channel 7 Rx event configuration register
+ */
+#define RMT_CH7_RX_LIM_REG (DR_REG_RMT_BASE + 0xbc)
+/** RMT_CH7_RX_LIM : R/W; bitpos: [8:0]; default: 128;
+ *  This register is used to configure the maximum entries that CHANNEL7 can receive.
+ */
+#define RMT_CH7_RX_LIM    0x000001FFU
+#define RMT_CH7_RX_LIM_M  (RMT_CH7_RX_LIM_V << RMT_CH7_RX_LIM_S)
+#define RMT_CH7_RX_LIM_V  0x000001FFU
+#define RMT_CH7_RX_LIM_S  0
+
+/** RMT_SYS_CONF_REG register
+ *  RMT apb configuration register
+ */
+#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0xc0)
+/** RMT_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0;
+ *  1'h1: access memory directly.   1'h0: access memory by FIFO.
+ */
+#define RMT_APB_FIFO_MASK    (BIT(0))
+#define RMT_APB_FIFO_MASK_M  (RMT_APB_FIFO_MASK_V << RMT_APB_FIFO_MASK_S)
+#define RMT_APB_FIFO_MASK_V  0x00000001U
+#define RMT_APB_FIFO_MASK_S  0
+/** RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable the clock for RMT memory.
+ */
+#define RMT_MEM_CLK_FORCE_ON    (BIT(1))
+#define RMT_MEM_CLK_FORCE_ON_M  (RMT_MEM_CLK_FORCE_ON_V << RMT_MEM_CLK_FORCE_ON_S)
+#define RMT_MEM_CLK_FORCE_ON_V  0x00000001U
+#define RMT_MEM_CLK_FORCE_ON_S  1
+/** RMT_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down RMT memory.
+ */
+#define RMT_MEM_FORCE_PD    (BIT(2))
+#define RMT_MEM_FORCE_PD_M  (RMT_MEM_FORCE_PD_V << RMT_MEM_FORCE_PD_S)
+#define RMT_MEM_FORCE_PD_V  0x00000001U
+#define RMT_MEM_FORCE_PD_S  2
+/** RMT_MEM_FORCE_PU : R/W; bitpos: [3]; default: 0;
+ *  1: Disable RMT memory light sleep power down function. 0: Power down RMT memory
+ *  when RMT is in light sleep mode.
+ */
+#define RMT_MEM_FORCE_PU    (BIT(3))
+#define RMT_MEM_FORCE_PU_M  (RMT_MEM_FORCE_PU_V << RMT_MEM_FORCE_PU_S)
+#define RMT_MEM_FORCE_PU_V  0x00000001U
+#define RMT_MEM_FORCE_PU_S  3
+/** RMT_SCLK_DIV_NUM : R/W; bitpos: [11:4]; default: 1;
+ *  the integral part of the fractional divisor
+ */
+#define RMT_SCLK_DIV_NUM    0x000000FFU
+#define RMT_SCLK_DIV_NUM_M  (RMT_SCLK_DIV_NUM_V << RMT_SCLK_DIV_NUM_S)
+#define RMT_SCLK_DIV_NUM_V  0x000000FFU
+#define RMT_SCLK_DIV_NUM_S  4
+/** RMT_SCLK_DIV_A : R/W; bitpos: [17:12]; default: 0;
+ *  the numerator of the fractional part of the fractional divisor
+ */
+#define RMT_SCLK_DIV_A    0x0000003FU
+#define RMT_SCLK_DIV_A_M  (RMT_SCLK_DIV_A_V << RMT_SCLK_DIV_A_S)
+#define RMT_SCLK_DIV_A_V  0x0000003FU
+#define RMT_SCLK_DIV_A_S  12
+/** RMT_SCLK_DIV_B : R/W; bitpos: [23:18]; default: 0;
+ *  the denominator of the fractional part of the fractional divisor
+ */
+#define RMT_SCLK_DIV_B    0x0000003FU
+#define RMT_SCLK_DIV_B_M  (RMT_SCLK_DIV_B_V << RMT_SCLK_DIV_B_S)
+#define RMT_SCLK_DIV_B_V  0x0000003FU
+#define RMT_SCLK_DIV_B_S  18
+/** RMT_SCLK_SEL : R/W; bitpos: [25:24]; default: 1;
+ *  choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL
+ */
+#define RMT_SCLK_SEL    0x00000003U
+#define RMT_SCLK_SEL_M  (RMT_SCLK_SEL_V << RMT_SCLK_SEL_S)
+#define RMT_SCLK_SEL_V  0x00000003U
+#define RMT_SCLK_SEL_S  24
+/** RMT_SCLK_ACTIVE : R/W; bitpos: [26]; default: 1;
+ *  rmt_sclk switch
+ */
+#define RMT_SCLK_ACTIVE    (BIT(26))
+#define RMT_SCLK_ACTIVE_M  (RMT_SCLK_ACTIVE_V << RMT_SCLK_ACTIVE_S)
+#define RMT_SCLK_ACTIVE_V  0x00000001U
+#define RMT_SCLK_ACTIVE_S  26
+/** RMT_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0:
+ *  Power down the drive clock of registers
+ */
+#define RMT_CLK_EN    (BIT(31))
+#define RMT_CLK_EN_M  (RMT_CLK_EN_V << RMT_CLK_EN_S)
+#define RMT_CLK_EN_V  0x00000001U
+#define RMT_CLK_EN_S  31
+
+/** RMT_TX_SIM_REG register
+ *  RMT TX synchronous register
+ */
+#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0xc4)
+/** RMT_TX_SIM_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable CHANNEL0 to start sending data synchronously with other
+ *  enabled channels.
+ */
+#define RMT_TX_SIM_CH0    (BIT(0))
+#define RMT_TX_SIM_CH0_M  (RMT_TX_SIM_CH0_V << RMT_TX_SIM_CH0_S)
+#define RMT_TX_SIM_CH0_V  0x00000001U
+#define RMT_TX_SIM_CH0_S  0
+/** RMT_TX_SIM_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable CHANNEL1 to start sending data synchronously with other
+ *  enabled channels.
+ */
+#define RMT_TX_SIM_CH1    (BIT(1))
+#define RMT_TX_SIM_CH1_M  (RMT_TX_SIM_CH1_V << RMT_TX_SIM_CH1_S)
+#define RMT_TX_SIM_CH1_V  0x00000001U
+#define RMT_TX_SIM_CH1_S  1
+/** RMT_TX_SIM_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable CHANNEL2 to start sending data synchronously with other
+ *  enabled channels.
+ */
+#define RMT_TX_SIM_CH2    (BIT(2))
+#define RMT_TX_SIM_CH2_M  (RMT_TX_SIM_CH2_V << RMT_TX_SIM_CH2_S)
+#define RMT_TX_SIM_CH2_V  0x00000001U
+#define RMT_TX_SIM_CH2_S  2
+/** RMT_TX_SIM_CH3 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable CHANNEL3 to start sending data synchronously with other
+ *  enabled channels.
+ */
+#define RMT_TX_SIM_CH3    (BIT(3))
+#define RMT_TX_SIM_CH3_M  (RMT_TX_SIM_CH3_V << RMT_TX_SIM_CH3_S)
+#define RMT_TX_SIM_CH3_V  0x00000001U
+#define RMT_TX_SIM_CH3_S  3
+/** RMT_TX_SIM_EN : R/W; bitpos: [4]; default: 0;
+ *  This register is used to enable multiple of channels to start sending data
+ *  synchronously.
+ */
+#define RMT_TX_SIM_EN    (BIT(4))
+#define RMT_TX_SIM_EN_M  (RMT_TX_SIM_EN_V << RMT_TX_SIM_EN_S)
+#define RMT_TX_SIM_EN_V  0x00000001U
+#define RMT_TX_SIM_EN_S  4
+
+/** RMT_REF_CNT_RST_REG register
+ *  RMT clock divider reset register
+ */
+#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0xc8)
+/** RMT_REF_CNT_RST_CH0 : WT; bitpos: [0]; default: 0;
+ *  This register is used to reset the clock divider of CHANNEL0.
+ */
+#define RMT_REF_CNT_RST_CH0    (BIT(0))
+#define RMT_REF_CNT_RST_CH0_M  (RMT_REF_CNT_RST_CH0_V << RMT_REF_CNT_RST_CH0_S)
+#define RMT_REF_CNT_RST_CH0_V  0x00000001U
+#define RMT_REF_CNT_RST_CH0_S  0
+/** RMT_REF_CNT_RST_CH1 : WT; bitpos: [1]; default: 0;
+ *  This register is used to reset the clock divider of CHANNEL1.
+ */
+#define RMT_REF_CNT_RST_CH1    (BIT(1))
+#define RMT_REF_CNT_RST_CH1_M  (RMT_REF_CNT_RST_CH1_V << RMT_REF_CNT_RST_CH1_S)
+#define RMT_REF_CNT_RST_CH1_V  0x00000001U
+#define RMT_REF_CNT_RST_CH1_S  1
+/** RMT_REF_CNT_RST_CH2 : WT; bitpos: [2]; default: 0;
+ *  This register is used to reset the clock divider of CHANNEL2.
+ */
+#define RMT_REF_CNT_RST_CH2    (BIT(2))
+#define RMT_REF_CNT_RST_CH2_M  (RMT_REF_CNT_RST_CH2_V << RMT_REF_CNT_RST_CH2_S)
+#define RMT_REF_CNT_RST_CH2_V  0x00000001U
+#define RMT_REF_CNT_RST_CH2_S  2
+/** RMT_REF_CNT_RST_CH3 : WT; bitpos: [3]; default: 0;
+ *  This register is used to reset the clock divider of CHANNEL3.
+ */
+#define RMT_REF_CNT_RST_CH3    (BIT(3))
+#define RMT_REF_CNT_RST_CH3_M  (RMT_REF_CNT_RST_CH3_V << RMT_REF_CNT_RST_CH3_S)
+#define RMT_REF_CNT_RST_CH3_V  0x00000001U
+#define RMT_REF_CNT_RST_CH3_S  3
+/** RMT_REF_CNT_RST_CH4 : WT; bitpos: [4]; default: 0;
+ *  This register is used to reset the clock divider of CHANNEL4.
+ */
+#define RMT_REF_CNT_RST_CH4    (BIT(4))
+#define RMT_REF_CNT_RST_CH4_M  (RMT_REF_CNT_RST_CH4_V << RMT_REF_CNT_RST_CH4_S)
+#define RMT_REF_CNT_RST_CH4_V  0x00000001U
+#define RMT_REF_CNT_RST_CH4_S  4
+/** RMT_REF_CNT_RST_CH5 : WT; bitpos: [5]; default: 0;
+ *  This register is used to reset the clock divider of CHANNEL5.
+ */
+#define RMT_REF_CNT_RST_CH5    (BIT(5))
+#define RMT_REF_CNT_RST_CH5_M  (RMT_REF_CNT_RST_CH5_V << RMT_REF_CNT_RST_CH5_S)
+#define RMT_REF_CNT_RST_CH5_V  0x00000001U
+#define RMT_REF_CNT_RST_CH5_S  5
+/** RMT_REF_CNT_RST_CH6 : WT; bitpos: [6]; default: 0;
+ *  This register is used to reset the clock divider of CHANNEL6.
+ */
+#define RMT_REF_CNT_RST_CH6    (BIT(6))
+#define RMT_REF_CNT_RST_CH6_M  (RMT_REF_CNT_RST_CH6_V << RMT_REF_CNT_RST_CH6_S)
+#define RMT_REF_CNT_RST_CH6_V  0x00000001U
+#define RMT_REF_CNT_RST_CH6_S  6
+/** RMT_REF_CNT_RST_CH7 : WT; bitpos: [7]; default: 0;
+ *  This register is used to reset the clock divider of CHANNEL7.
+ */
+#define RMT_REF_CNT_RST_CH7    (BIT(7))
+#define RMT_REF_CNT_RST_CH7_M  (RMT_REF_CNT_RST_CH7_V << RMT_REF_CNT_RST_CH7_S)
+#define RMT_REF_CNT_RST_CH7_V  0x00000001U
+#define RMT_REF_CNT_RST_CH7_S  7
+
+/** RMT_DATE_REG register
+ *  RMT version register
+ */
+#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xcc)
+/** RMT_DATE : R/W; bitpos: [27:0]; default: 35655953;
+ *  This is the version register.
+ */
+#define RMT_DATE    0x0FFFFFFFU
+#define RMT_DATE_M  (RMT_DATE_V << RMT_DATE_S)
+#define RMT_DATE_V  0x0FFFFFFFU
+#define RMT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/rmt_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/rmt_struct.h
new file mode 100644
index 0000000000..b6d21840aa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/rmt_struct.h
@@ -0,0 +1,1082 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO R/W registers */
+/** Type of chndata register
+ *  The read and write  data register for CHANNELn by apb fifo access.
+ */
+typedef union {
+    struct {
+        /** chndata : RO; bitpos: [31:0]; default: 0;
+         *  Read and write data for channel n via APB FIFO.
+         */
+        uint32_t chndata: 32;
+    };
+    uint32_t val;
+} rmt_chndata_reg_t;
+
+/** Type of chmdata register
+ *  The read and write  data register for CHANNEL$n by apb fifo access.
+ */
+typedef union {
+    struct {
+        /** chmdata : RO; bitpos: [31:0]; default: 0;
+         *  Read and write data for channel $n via APB FIFO.
+         */
+        uint32_t chmdata: 32;
+    };
+    uint32_t val;
+} rmt_chmdata_reg_t;
+
+/** Group: Configuration registers */
+/** Type of chnconf0 register
+ *  Channel n configure register 0
+ */
+typedef union {
+    struct {
+        /** tx_start_chn : WT; bitpos: [0]; default: 0;
+         *  Set this bit to start sending data on CHANNELn.
+         */
+        uint32_t tx_start_chn: 1;
+        /** mem_rd_rst_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset read ram address for CHANNELn by accessing transmitter.
+         */
+        uint32_t mem_rd_rst_chn: 1;
+        /** apb_mem_rst_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo.
+         */
+        uint32_t apb_mem_rst_chn: 1;
+        /** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to restart transmission  from the first data to the last data in
+         *  CHANNELn.
+         */
+        uint32_t tx_conti_mode_chn: 1;
+        /** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0;
+         *  This is the channel n enable bit for wraparound mode: it will resume sending at the
+         *  start when the data to be sent is more than its memory size.
+         */
+        uint32_t mem_tx_wrap_en_chn: 1;
+        /** idle_out_lv_chn : R/W; bitpos: [5]; default: 0;
+         *  This bit configures the level of output signal in CHANNELn when the latter is in
+         *  IDLE state.
+         */
+        uint32_t idle_out_lv_chn: 1;
+        /** idle_out_en_chn : R/W; bitpos: [6]; default: 0;
+         *  This is the output enable-control bit for CHANNELn in IDLE state.
+         */
+        uint32_t idle_out_en_chn: 1;
+        /** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0;
+         *  Set this bit to stop the transmitter of CHANNELn sending data out.
+         */
+        uint32_t tx_stop_chn: 1;
+        /** div_cnt_chn : R/W; bitpos: [15:8]; default: 2;
+         *  This register is used to configure the divider for clock of CHANNELn.
+         */
+        uint32_t div_cnt_chn: 8;
+        /** mem_size_chn : R/W; bitpos: [19:16]; default: 1;
+         *  This register is used to configure the maximum size of memory allocated to CHANNELn.
+         */
+        uint32_t mem_size_chn: 4;
+        /** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1;
+         *  1: Add carrier modulation on the output signal only at the send data state for
+         *  CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn.
+         *  Only valid when RMT_CARRIER_EN_CHn is 1.
+         */
+        uint32_t carrier_eff_en_chn: 1;
+        /** carrier_en_chn : R/W; bitpos: [21]; default: 1;
+         *  This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier
+         *  modulation in the output signal. 0: No carrier modulation in sig_out.
+         */
+        uint32_t carrier_en_chn: 1;
+        /** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1;
+         *  This bit is used to configure the position of carrier wave for CHANNELn.
+         *  1'h0: add carrier wave on low level.
+         *  1'h1: add carrier wave on high level.
+         */
+        uint32_t carrier_out_lv_chn: 1;
+        /** afifo_rst_chn : WT; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t afifo_rst_chn: 1;
+        /** conf_update_chn : WT; bitpos: [24]; default: 0;
+         *  synchronization bit for CHANNELn
+         */
+        uint32_t conf_update_chn: 1;
+        /** dma_access_en_chn : WT; bitpos: [25]; default: 0;
+         *  DMA access control bit for CHANNELn (only CHANNEL3 has this control bit)
+         */
+        uint32_t dma_access_en_chn: 1;
+        uint32_t reserved_26: 6;
+    };
+    uint32_t val;
+} rmt_chnconf0_reg_t;
+
+/** Type of chmconf0 register
+ *  Channel m configure register 0
+ */
+typedef union {
+    struct {
+        /** div_cnt_chm : R/W; bitpos: [7:0]; default: 2;
+         *  This register is used to configure the divider for clock of CHANNELm.
+         */
+        uint32_t div_cnt_chm: 8;
+        /** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767;
+         *  When no edge is detected on the input signal and continuous clock cycles is longer
+         *  than this register value, received process is finished.
+         */
+        uint32_t idle_thres_chm: 15;
+        /** dma_access_en_m : WT; bitpos: [23]; default: 0;
+         *  DMA access control bit for CHANNELm (only channel7 has this control bit)
+         */
+        uint32_t dma_access_en_chm: 1;
+        /** mem_size_chm : R/W; bitpos: [27:24]; default: 1;
+         *  This register is used to configure the maximum size of memory allocated to CHANNELm.
+         */
+        uint32_t mem_size_chm: 4;
+        /** carrier_en_chm : R/W; bitpos: [28]; default: 1;
+         *  This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier
+         *  modulation in the output signal. 0: No carrier modulation in sig_out.
+         */
+        uint32_t carrier_en_chm: 1;
+        /** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1;
+         *  This bit is used to configure the position of carrier wave for CHANNELm.
+         *  1'h0: add carrier wave on low level.
+         *  1'h1: add carrier wave on high level.
+         */
+        uint32_t carrier_out_lv_chm: 1;
+        uint32_t reserved_30: 2;
+    };
+    uint32_t val;
+} rmt_chmconf0_reg_t;
+
+/** Type of chmconf1 register
+ *  Channel m configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_en_chm : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable receiver to receive data on CHANNELm.
+         */
+        uint32_t rx_en_chm: 1;
+        /** mem_wr_rst_chm : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset write ram address for CHANNELm by accessing receiver.
+         */
+        uint32_t mem_wr_rst_chm: 1;
+        /** apb_mem_rst_chm : WT; bitpos: [2]; default: 0;
+         *  Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo.
+         */
+        uint32_t apb_mem_rst_chm: 1;
+        /** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1;
+         *  This register marks the ownership of CHANNELm's ram block.
+         *  1'h1: Receiver is using the ram.
+         *  1'h0: APB bus is using the ram.
+         */
+        uint32_t mem_owner_chm: 1;
+        /** rx_filter_en_chm : R/W; bitpos: [4]; default: 0;
+         *  This is the receive filter's enable bit for CHANNELm.
+         */
+        uint32_t rx_filter_en_chm: 1;
+        /** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15;
+         *  Ignores the input pulse when its width is smaller than this register value in APB
+         *  clock periods (in receive mode).
+         */
+        uint32_t rx_filter_thres_chm: 8;
+        /** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0;
+         *  This is the channel m enable bit for wraparound mode: it will resume receiving at
+         *  the start when the data to be received is more than its memory size.
+         */
+        uint32_t mem_rx_wrap_en_chm: 1;
+        /** afifo_rst_chm : WT; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t afifo_rst_chm: 1;
+        /** conf_update_chm : WT; bitpos: [15]; default: 0;
+         *  synchronization bit for CHANNELm
+         */
+        uint32_t conf_update_chm: 1;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} rmt_chmconf1_reg_t;
+
+/** Type of chm_rx_carrier_rm register
+ *  Channel m carrier remove register
+ */
+typedef union {
+    struct {
+        /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0;
+         *  The low level period in a carrier modulation mode is
+         *  (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m.
+         */
+        uint32_t carrier_low_thres_chm: 16;
+        /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0;
+         *  The high level period in a carrier modulation mode is
+         *  (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m.
+         */
+        uint32_t carrier_high_thres_chm: 16;
+    };
+    uint32_t val;
+} rmt_chm_rx_carrier_rm_reg_t;
+
+/** Type of sys_conf register
+ *  RMT apb configuration register
+ */
+typedef union {
+    struct {
+        /** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
+         *  1'h1: access memory directly.   1'h0: access memory by FIFO.
+         */
+        uint32_t apb_fifo_mask: 1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable the clock for RMT memory.
+         */
+        uint32_t mem_clk_force_on: 1;
+        /** mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down RMT memory.
+         */
+        uint32_t mem_force_pd: 1;
+        /** mem_force_pu : R/W; bitpos: [3]; default: 0;
+         *  1: Disable RMT memory light sleep power down function. 0: Power down RMT memory
+         *  when RMT is in light sleep mode.
+         */
+        uint32_t mem_force_pu: 1;
+        /** sclk_div_num : R/W; bitpos: [11:4]; default: 1;
+         *  the integral part of the fractional divisor
+         */
+        uint32_t sclk_div_num: 8;
+        /** sclk_div_a : R/W; bitpos: [17:12]; default: 0;
+         *  the numerator of the fractional part of the fractional divisor
+         */
+        uint32_t sclk_div_a: 6;
+        /** sclk_div_b : R/W; bitpos: [23:18]; default: 0;
+         *  the denominator of the fractional part of the fractional divisor
+         */
+        uint32_t sclk_div_b: 6;
+        /** sclk_sel : R/W; bitpos: [25:24]; default: 1;
+         *  choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL
+         */
+        uint32_t sclk_sel: 2;
+        /** sclk_active : R/W; bitpos: [26]; default: 1;
+         *  rmt_sclk switch
+         */
+        uint32_t sclk_active: 1;
+        uint32_t reserved_27: 4;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0:
+         *  Power down the drive clock of registers
+         */
+        uint32_t clk_en: 1;
+    };
+    uint32_t val;
+} rmt_sys_conf_reg_t;
+
+/** Type of ref_cnt_rst register
+ *  RMT clock divider reset register
+ */
+typedef union {
+    struct {
+        /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL0.
+         */
+        uint32_t ref_cnt_rst_ch0: 1;
+        /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL1.
+         */
+        uint32_t ref_cnt_rst_ch1: 1;
+        /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL2.
+         */
+        uint32_t ref_cnt_rst_ch2: 1;
+        /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL3.
+         */
+        uint32_t ref_cnt_rst_ch3: 1;
+        /** ref_cnt_rst_ch4 : WT; bitpos: [4]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL4.
+         */
+        uint32_t ref_cnt_rst_ch4: 1;
+        /** ref_cnt_rst_ch5 : WT; bitpos: [5]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL5.
+         */
+        uint32_t ref_cnt_rst_ch5: 1;
+        /** ref_cnt_rst_ch6 : WT; bitpos: [6]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL6.
+         */
+        uint32_t ref_cnt_rst_ch6: 1;
+        /** ref_cnt_rst_ch7 : WT; bitpos: [7]; default: 0;
+         *  This register is used to reset the clock divider of CHANNEL7.
+         */
+        uint32_t ref_cnt_rst_ch7: 1;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} rmt_ref_cnt_rst_reg_t;
+
+/** Group: Status registers */
+/** Type of chnstatus register
+ *  Channel n status register
+ */
+typedef union {
+    struct {
+        /** mem_raddr_ex_chn : RO; bitpos: [9:0]; default: 0;
+         *  This register records the memory address offset when transmitter of CHANNELn is
+         *  using the RAM.
+         */
+        uint32_t mem_raddr_ex_chn: 10;
+        uint32_t reserved_10: 1;
+        /** apb_mem_waddr_chn : RO; bitpos: [20:11]; default: 0;
+         *  This register records the memory address offset when writes RAM over APB bus.
+         */
+        uint32_t apb_mem_waddr_chn: 10;
+        uint32_t reserved_21: 1;
+        /** state_chn : RO; bitpos: [24:22]; default: 0;
+         *  This register records the FSM status of CHANNELn.
+         */
+        uint32_t state_chn: 3;
+        /** mem_empty_chn : RO; bitpos: [25]; default: 0;
+         *  This status bit will be set when the data to be set is more than memory size and
+         *  the wraparound mode is disabled.
+         */
+        uint32_t mem_empty_chn: 1;
+        /** apb_mem_wr_err_chn : RO; bitpos: [26]; default: 0;
+         *  This status bit will be set if the offset address out of memory size when writes
+         *  via APB bus.
+         */
+        uint32_t apb_mem_wr_err_chn: 1;
+        uint32_t reserved_27: 5;
+    };
+    uint32_t val;
+} rmt_chnstatus_reg_t;
+
+/** Type of chmstatus register
+ *  Channel m status register
+ */
+typedef union {
+    struct {
+        /** mem_waddr_ex_chm : RO; bitpos: [9:0]; default: 192;
+         *  This register records the memory address offset when receiver of CHANNELm is using
+         *  the RAM.
+         */
+        uint32_t mem_waddr_ex_chm: 10;
+        uint32_t reserved_10: 1;
+        /** apb_mem_raddr_chm : RO; bitpos: [20:11]; default: 192;
+         *  This register records the memory address offset when reads RAM over APB bus.
+         */
+        uint32_t apb_mem_raddr_chm: 10;
+        uint32_t reserved_21: 1;
+        /** state_chm : RO; bitpos: [24:22]; default: 0;
+         *  This register records the FSM status of CHANNELm.
+         */
+        uint32_t state_chm: 3;
+        /** mem_owner_err_chm : RO; bitpos: [25]; default: 0;
+         *  This status bit will be set when the ownership of memory block is wrong.
+         */
+        uint32_t mem_owner_err_chm: 1;
+        /** mem_full_chm : RO; bitpos: [26]; default: 0;
+         *  This status bit will be set if the receiver receives more data than the memory size.
+         */
+        uint32_t mem_full_chm: 1;
+        /** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0;
+         *  This status bit will be set if the offset address out of memory size when reads via
+         *  APB bus.
+         */
+        uint32_t apb_mem_rd_err_chm: 1;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} rmt_chmstatus_reg_t;
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The interrupt raw bit for CHANNEL0. Triggered when transmission done.
+         */
+        uint32_t ch0_tx_end_int_raw: 1;
+        /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The interrupt raw bit for CHANNEL1. Triggered when transmission done.
+         */
+        uint32_t ch1_tx_end_int_raw: 1;
+        /** ch2_tx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The interrupt raw bit for CHANNEL2. Triggered when transmission done.
+         */
+        uint32_t ch2_tx_end_int_raw: 1;
+        /** ch3_tx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The interrupt raw bit for CHANNEL3. Triggered when transmission done.
+         */
+        uint32_t ch3_tx_end_int_raw: 1;
+        /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The interrupt raw bit for CHANNEL0. Triggered when error occurs.
+         */
+        uint32_t ch0_err_int_raw: 1;
+        /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The interrupt raw bit for CHANNEL1. Triggered when error occurs.
+         */
+        uint32_t ch1_err_int_raw: 1;
+        /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The interrupt raw bit for CHANNEL2. Triggered when error occurs.
+         */
+        uint32_t ch2_err_int_raw: 1;
+        /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The interrupt raw bit for CHANNEL3. Triggered when error occurs.
+         */
+        uint32_t ch3_err_int_raw: 1;
+        /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than
+         *  configured value.
+         */
+        uint32_t ch0_tx_thr_event_int_raw: 1;
+        /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than
+         *  configured value.
+         */
+        uint32_t ch1_tx_thr_event_int_raw: 1;
+        /** ch2_tx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than
+         *  configured value.
+         */
+        uint32_t ch2_tx_thr_event_int_raw: 1;
+        /** ch3_tx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than
+         *  configured value.
+         */
+        uint32_t ch3_tx_thr_event_int_raw: 1;
+        /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the
+         *  configured threshold value.
+         */
+        uint32_t ch0_tx_loop_int_raw: 1;
+        /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the
+         *  configured threshold value.
+         */
+        uint32_t ch1_tx_loop_int_raw: 1;
+        /** ch2_tx_loop_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the
+         *  configured threshold value.
+         */
+        uint32_t ch2_tx_loop_int_raw: 1;
+        /** ch3_tx_loop_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the
+         *  configured threshold value.
+         */
+        uint32_t ch3_tx_loop_int_raw: 1;
+        /** ch4_rx_end_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The interrupt raw bit for CHANNEL4. Triggered when reception done.
+         */
+        uint32_t ch4_rx_end_int_raw: 1;
+        /** ch5_rx_end_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The interrupt raw bit for CHANNEL5. Triggered when reception done.
+         */
+        uint32_t ch5_rx_end_int_raw: 1;
+        /** ch6_rx_end_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The interrupt raw bit for CHANNEL6. Triggered when reception done.
+         */
+        uint32_t ch6_rx_end_int_raw: 1;
+        /** ch7_rx_end_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The interrupt raw bit for CHANNEL7. Triggered when reception done.
+         */
+        uint32_t ch7_rx_end_int_raw: 1;
+        /** ch4_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The interrupt raw bit for CHANNEL4. Triggered when error occurs.
+         */
+        uint32_t ch4_err_int_raw: 1;
+        /** ch5_err_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  The interrupt raw bit for CHANNEL5. Triggered when error occurs.
+         */
+        uint32_t ch5_err_int_raw: 1;
+        /** ch6_err_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  The interrupt raw bit for CHANNEL6. Triggered when error occurs.
+         */
+        uint32_t ch6_err_int_raw: 1;
+        /** ch7_err_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  The interrupt raw bit for CHANNEL7. Triggered when error occurs.
+         */
+        uint32_t ch7_err_int_raw: 1;
+        /** ch4_rx_thr_event_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than
+         *  configured value.
+         */
+        uint32_t ch4_rx_thr_event_int_raw: 1;
+        /** ch5_rx_thr_event_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than
+         *  configured value.
+         */
+        uint32_t ch5_rx_thr_event_int_raw: 1;
+        /** ch6_rx_thr_event_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than
+         *  configured value.
+         */
+        uint32_t ch6_rx_thr_event_int_raw: 1;
+        /** ch7_rx_thr_event_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than
+         *  configured value.
+         */
+        uint32_t ch7_rx_thr_event_int_raw: 1;
+        /** ch3_dma_access_fail_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails.
+         */
+        uint32_t ch3_dma_access_fail_int_raw: 1;
+        /** ch7_dma_access_fail_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails.
+         */
+        uint32_t ch7_dma_access_fail_int_raw: 1;
+        uint32_t reserved_30: 2;
+    };
+    uint32_t val;
+} rmt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for CH0_TX_END_INT.
+         */
+        uint32_t ch0_tx_end_int_st: 1;
+        /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for CH1_TX_END_INT.
+         */
+        uint32_t ch1_tx_end_int_st: 1;
+        /** ch2_tx_end_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for CH2_TX_END_INT.
+         */
+        uint32_t ch2_tx_end_int_st: 1;
+        /** ch3_tx_end_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for CH3_TX_END_INT.
+         */
+        uint32_t ch3_tx_end_int_st: 1;
+        /** ch0_err_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status bit for CH0_ERR_INT.
+         */
+        uint32_t ch0_err_int_st: 1;
+        /** ch1_err_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status bit for CH1_ERR_INT.
+         */
+        uint32_t ch1_err_int_st: 1;
+        /** ch2_err_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status bit for CH2_ERR_INT.
+         */
+        uint32_t ch2_err_int_st: 1;
+        /** ch3_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status bit for CH3_ERR_INT.
+         */
+        uint32_t ch3_err_int_st: 1;
+        /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
+         */
+        uint32_t ch0_tx_thr_event_int_st: 1;
+        /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
+         */
+        uint32_t ch1_tx_thr_event_int_st: 1;
+        /** ch2_tx_thr_event_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status bit for CH2_TX_THR_EVENT_INT.
+         */
+        uint32_t ch2_tx_thr_event_int_st: 1;
+        /** ch3_tx_thr_event_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status bit for CH3_TX_THR_EVENT_INT.
+         */
+        uint32_t ch3_tx_thr_event_int_st: 1;
+        /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status bit for CH0_TX_LOOP_INT.
+         */
+        uint32_t ch0_tx_loop_int_st: 1;
+        /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status bit for CH1_TX_LOOP_INT.
+         */
+        uint32_t ch1_tx_loop_int_st: 1;
+        /** ch2_tx_loop_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status bit for CH2_TX_LOOP_INT.
+         */
+        uint32_t ch2_tx_loop_int_st: 1;
+        /** ch3_tx_loop_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status bit for CH3_TX_LOOP_INT.
+         */
+        uint32_t ch3_tx_loop_int_st: 1;
+        /** ch4_rx_end_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status bit for CH4_RX_END_INT.
+         */
+        uint32_t ch4_rx_end_int_st: 1;
+        /** ch5_rx_end_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status bit for CH5_RX_END_INT.
+         */
+        uint32_t ch5_rx_end_int_st: 1;
+        /** ch6_rx_end_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked interrupt status bit for CH6_RX_END_INT.
+         */
+        uint32_t ch6_rx_end_int_st: 1;
+        /** ch7_rx_end_int_st : RO; bitpos: [19]; default: 0;
+         *  The masked interrupt status bit for CH7_RX_END_INT.
+         */
+        uint32_t ch7_rx_end_int_st: 1;
+        /** ch4_err_int_st : RO; bitpos: [20]; default: 0;
+         *  The masked interrupt status bit for CH4_ERR_INT.
+         */
+        uint32_t ch4_err_int_st: 1;
+        /** ch5_err_int_st : RO; bitpos: [21]; default: 0;
+         *  The masked interrupt status bit for CH5_ERR_INT.
+         */
+        uint32_t ch5_err_int_st: 1;
+        /** ch6_err_int_st : RO; bitpos: [22]; default: 0;
+         *  The masked interrupt status bit for CH6_ERR_INT.
+         */
+        uint32_t ch6_err_int_st: 1;
+        /** ch7_err_int_st : RO; bitpos: [23]; default: 0;
+         *  The masked interrupt status bit for CH7_ERR_INT.
+         */
+        uint32_t ch7_err_int_st: 1;
+        /** ch4_rx_thr_event_int_st : RO; bitpos: [24]; default: 0;
+         *  The masked interrupt status bit for CH4_RX_THR_EVENT_INT.
+         */
+        uint32_t ch4_rx_thr_event_int_st: 1;
+        /** ch5_rx_thr_event_int_st : RO; bitpos: [25]; default: 0;
+         *  The masked interrupt status bit for CH5_RX_THR_EVENT_INT.
+         */
+        uint32_t ch5_rx_thr_event_int_st: 1;
+        /** ch6_rx_thr_event_int_st : RO; bitpos: [26]; default: 0;
+         *  The masked interrupt status bit for CH6_RX_THR_EVENT_INT.
+         */
+        uint32_t ch6_rx_thr_event_int_st: 1;
+        /** ch7_rx_thr_event_int_st : RO; bitpos: [27]; default: 0;
+         *  The masked interrupt status bit for CH7_RX_THR_EVENT_INT.
+         */
+        uint32_t ch7_rx_thr_event_int_st: 1;
+        /** ch3_dma_access_fail_int_st : RO; bitpos: [28]; default: 0;
+         *  The masked interrupt status bit for  CH3_DMA_ACCESS_FAIL_INT.
+         */
+        uint32_t ch3_dma_access_fail_int_st: 1;
+        /** ch7_dma_access_fail_int_st : RO; bitpos: [29]; default: 0;
+         *  The masked interrupt status bit for  CH7_DMA_ACCESS_FAIL_INT.
+         */
+        uint32_t ch7_dma_access_fail_int_st: 1;
+        uint32_t reserved_30: 2;
+    };
+    uint32_t val;
+} rmt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for CH0_TX_END_INT.
+         */
+        uint32_t ch0_tx_end_int_ena: 1;
+        /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for CH1_TX_END_INT.
+         */
+        uint32_t ch1_tx_end_int_ena: 1;
+        /** ch2_tx_end_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for CH2_TX_END_INT.
+         */
+        uint32_t ch2_tx_end_int_ena: 1;
+        /** ch3_tx_end_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for CH3_TX_END_INT.
+         */
+        uint32_t ch3_tx_end_int_ena: 1;
+        /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for CH0_ERR_INT.
+         */
+        uint32_t ch0_err_int_ena: 1;
+        /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for CH1_ERR_INT.
+         */
+        uint32_t ch1_err_int_ena: 1;
+        /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for CH2_ERR_INT.
+         */
+        uint32_t ch2_err_int_ena: 1;
+        /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for CH3_ERR_INT.
+         */
+        uint32_t ch3_err_int_ena: 1;
+        /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for CH0_TX_THR_EVENT_INT.
+         */
+        uint32_t ch0_tx_thr_event_int_ena: 1;
+        /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for CH1_TX_THR_EVENT_INT.
+         */
+        uint32_t ch1_tx_thr_event_int_ena: 1;
+        /** ch2_tx_thr_event_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for CH2_TX_THR_EVENT_INT.
+         */
+        uint32_t ch2_tx_thr_event_int_ena: 1;
+        /** ch3_tx_thr_event_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for CH3_TX_THR_EVENT_INT.
+         */
+        uint32_t ch3_tx_thr_event_int_ena: 1;
+        /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for CH0_TX_LOOP_INT.
+         */
+        uint32_t ch0_tx_loop_int_ena: 1;
+        /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for CH1_TX_LOOP_INT.
+         */
+        uint32_t ch1_tx_loop_int_ena: 1;
+        /** ch2_tx_loop_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The interrupt enable bit for CH2_TX_LOOP_INT.
+         */
+        uint32_t ch2_tx_loop_int_ena: 1;
+        /** ch3_tx_loop_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The interrupt enable bit for CH3_TX_LOOP_INT.
+         */
+        uint32_t ch3_tx_loop_int_ena: 1;
+        /** ch4_rx_end_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The interrupt enable bit for CH4_RX_END_INT.
+         */
+        uint32_t ch4_rx_end_int_ena: 1;
+        /** ch5_rx_end_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The interrupt enable bit for CH5_RX_END_INT.
+         */
+        uint32_t ch5_rx_end_int_ena: 1;
+        /** ch6_rx_end_int_ena : R/W; bitpos: [18]; default: 0;
+         *  The interrupt enable bit for CH6_RX_END_INT.
+         */
+        uint32_t ch6_rx_end_int_ena: 1;
+        /** ch7_rx_end_int_ena : R/W; bitpos: [19]; default: 0;
+         *  The interrupt enable bit for CH7_RX_END_INT.
+         */
+        uint32_t ch7_rx_end_int_ena: 1;
+        /** ch4_err_int_ena : R/W; bitpos: [20]; default: 0;
+         *  The interrupt enable bit for CH4_ERR_INT.
+         */
+        uint32_t ch4_err_int_ena: 1;
+        /** ch5_err_int_ena : R/W; bitpos: [21]; default: 0;
+         *  The interrupt enable bit for CH5_ERR_INT.
+         */
+        uint32_t ch5_err_int_ena: 1;
+        /** ch6_err_int_ena : R/W; bitpos: [22]; default: 0;
+         *  The interrupt enable bit for CH6_ERR_INT.
+         */
+        uint32_t ch6_err_int_ena: 1;
+        /** ch7_err_int_ena : R/W; bitpos: [23]; default: 0;
+         *  The interrupt enable bit for CH7_ERR_INT.
+         */
+        uint32_t ch7_err_int_ena: 1;
+        /** ch4_rx_thr_event_int_ena : R/W; bitpos: [24]; default: 0;
+         *  The interrupt enable bit for CH4_RX_THR_EVENT_INT.
+         */
+        uint32_t ch4_rx_thr_event_int_ena: 1;
+        /** ch5_rx_thr_event_int_ena : R/W; bitpos: [25]; default: 0;
+         *  The interrupt enable bit for CH5_RX_THR_EVENT_INT.
+         */
+        uint32_t ch5_rx_thr_event_int_ena: 1;
+        /** ch6_rx_thr_event_int_ena : R/W; bitpos: [26]; default: 0;
+         *  The interrupt enable bit for CH6_RX_THR_EVENT_INT.
+         */
+        uint32_t ch6_rx_thr_event_int_ena: 1;
+        /** ch7_rx_thr_event_int_ena : R/W; bitpos: [27]; default: 0;
+         *  The interrupt enable bit for CH7_RX_THR_EVENT_INT.
+         */
+        uint32_t ch7_rx_thr_event_int_ena: 1;
+        /** ch3_dma_access_fail_int_ena : R/W; bitpos: [28]; default: 0;
+         *  The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT.
+         */
+        uint32_t ch3_dma_access_fail_int_ena: 1;
+        /** ch7_dma_access_fail_int_ena : R/W; bitpos: [29]; default: 0;
+         *  The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT.
+         */
+        uint32_t ch7_dma_access_fail_int_ena: 1;
+        uint32_t reserved_30: 2;
+    };
+    uint32_t val;
+} rmt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear theCH0_TX_END_INT interrupt.
+         */
+        uint32_t ch0_tx_end_int_clr: 1;
+        /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear theCH1_TX_END_INT interrupt.
+         */
+        uint32_t ch1_tx_end_int_clr: 1;
+        /** ch2_tx_end_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear theCH2_TX_END_INT interrupt.
+         */
+        uint32_t ch2_tx_end_int_clr: 1;
+        /** ch3_tx_end_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear theCH3_TX_END_INT interrupt.
+         */
+        uint32_t ch3_tx_end_int_clr: 1;
+        /** ch0_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear theCH0_ERR_INT interrupt.
+         */
+        uint32_t ch0_err_int_clr: 1;
+        /** ch1_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear theCH1_ERR_INT interrupt.
+         */
+        uint32_t ch1_err_int_clr: 1;
+        /** ch2_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear theCH2_ERR_INT interrupt.
+         */
+        uint32_t ch2_err_int_clr: 1;
+        /** ch3_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear theCH3_ERR_INT interrupt.
+         */
+        uint32_t ch3_err_int_clr: 1;
+        /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch0_tx_thr_event_int_clr: 1;
+        /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch1_tx_thr_event_int_clr: 1;
+        /** ch2_tx_thr_event_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch2_tx_thr_event_int_clr: 1;
+        /** ch3_tx_thr_event_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch3_tx_thr_event_int_clr: 1;
+        /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear theCH0_TX_LOOP_INT interrupt.
+         */
+        uint32_t ch0_tx_loop_int_clr: 1;
+        /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear theCH1_TX_LOOP_INT interrupt.
+         */
+        uint32_t ch1_tx_loop_int_clr: 1;
+        /** ch2_tx_loop_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear theCH2_TX_LOOP_INT interrupt.
+         */
+        uint32_t ch2_tx_loop_int_clr: 1;
+        /** ch3_tx_loop_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear theCH3_TX_LOOP_INT interrupt.
+         */
+        uint32_t ch3_tx_loop_int_clr: 1;
+        /** ch4_rx_end_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear theCH4_RX_END_INT interrupt.
+         */
+        uint32_t ch4_rx_end_int_clr: 1;
+        /** ch5_rx_end_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear theCH5_RX_END_INT interrupt.
+         */
+        uint32_t ch5_rx_end_int_clr: 1;
+        /** ch6_rx_end_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear theCH6_RX_END_INT interrupt.
+         */
+        uint32_t ch6_rx_end_int_clr: 1;
+        /** ch7_rx_end_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear theCH7_RX_END_INT interrupt.
+         */
+        uint32_t ch7_rx_end_int_clr: 1;
+        /** ch4_err_int_clr : WT; bitpos: [20]; default: 0;
+         *  Set this bit to clear theCH4_ERR_INT interrupt.
+         */
+        uint32_t ch4_err_int_clr: 1;
+        /** ch5_err_int_clr : WT; bitpos: [21]; default: 0;
+         *  Set this bit to clear theCH5_ERR_INT interrupt.
+         */
+        uint32_t ch5_err_int_clr: 1;
+        /** ch6_err_int_clr : WT; bitpos: [22]; default: 0;
+         *  Set this bit to clear theCH6_ERR_INT interrupt.
+         */
+        uint32_t ch6_err_int_clr: 1;
+        /** ch7_err_int_clr : WT; bitpos: [23]; default: 0;
+         *  Set this bit to clear theCH7_ERR_INT interrupt.
+         */
+        uint32_t ch7_err_int_clr: 1;
+        /** ch4_rx_thr_event_int_clr : WT; bitpos: [24]; default: 0;
+         *  Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch4_rx_thr_event_int_clr: 1;
+        /** ch5_rx_thr_event_int_clr : WT; bitpos: [25]; default: 0;
+         *  Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch5_rx_thr_event_int_clr: 1;
+        /** ch6_rx_thr_event_int_clr : WT; bitpos: [26]; default: 0;
+         *  Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch6_rx_thr_event_int_clr: 1;
+        /** ch7_rx_thr_event_int_clr : WT; bitpos: [27]; default: 0;
+         *  Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt.
+         */
+        uint32_t ch7_rx_thr_event_int_clr: 1;
+        /** ch3_dma_access_fail_int_clr : WT; bitpos: [28]; default: 0;
+         *  Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt.
+         */
+        uint32_t ch3_dma_access_fail_int_clr: 1;
+        /** ch7_dma_access_fail_int_clr : WT; bitpos: [29]; default: 0;
+         *  Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt.
+         */
+        uint32_t ch7_dma_access_fail_int_clr: 1;
+        uint32_t reserved_30: 2;
+    };
+    uint32_t val;
+} rmt_int_clr_reg_t;
+
+/** Group: Carrier wave duty cycle registers */
+/** Type of chncarrier_duty register
+ *  Channel n duty cycle configuration register
+ */
+typedef union {
+    struct {
+        /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64;
+         *  This register is used to configure carrier wave 's low level clock period for
+         *  CHANNELn.
+         */
+        uint32_t carrier_low_chn: 16;
+        /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64;
+         *  This register is used to configure carrier wave 's high level clock period for
+         *  CHANNELn.
+         */
+        uint32_t carrier_high_chn: 16;
+    };
+    uint32_t val;
+} rmt_chncarrier_duty_reg_t;
+
+/** Group: Tx event configuration registers */
+/** Type of chn_tx_lim register
+ *  Channel n Tx event configuration register
+ */
+typedef union {
+    struct {
+        /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128;
+         *  This register is used to configure the maximum entries that CHANNELn can send out.
+         */
+        uint32_t tx_lim_chn: 9;
+        /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0;
+         *  This register is used to configure the maximum loop count when tx_conti_mode is
+         *  valid.
+         */
+        uint32_t tx_loop_num_chn: 10;
+        /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0;
+         *  This register is the enabled bit for loop count.
+         */
+        uint32_t tx_loop_cnt_en_chn: 1;
+        /** loop_count_reset_chn : WT; bitpos: [20]; default: 0;
+         *  This register is used to reset the loop count when tx_conti_mode is valid.
+         */
+        uint32_t loop_count_reset_chn: 1;
+        /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0;
+         *  This bit is used to enable the loop send stop function after the loop counter
+         *  counts to  loop number for CHANNELn.
+         */
+        uint32_t loop_stop_en_chn: 1;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} rmt_chn_tx_lim_reg_t;
+
+/** Type of tx_sim register
+ *  RMT TX synchronous register
+ */
+typedef union {
+    struct {
+        /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable CHANNEL0 to start sending data synchronously with other
+         *  enabled channels.
+         */
+        uint32_t tx_sim_ch0: 1;
+        /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable CHANNEL1 to start sending data synchronously with other
+         *  enabled channels.
+         */
+        uint32_t tx_sim_ch1: 1;
+        /** tx_sim_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable CHANNEL2 to start sending data synchronously with other
+         *  enabled channels.
+         */
+        uint32_t tx_sim_ch2: 1;
+        /** tx_sim_ch3 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable CHANNEL3 to start sending data synchronously with other
+         *  enabled channels.
+         */
+        uint32_t tx_sim_ch3: 1;
+        /** tx_sim_en : R/W; bitpos: [4]; default: 0;
+         *  This register is used to enable multiple of channels to start sending data
+         *  synchronously.
+         */
+        uint32_t tx_sim_en: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} rmt_tx_sim_reg_t;
+
+/** Group: Rx event configuration registers */
+/** Type of chm_rx_lim register
+ *  Channel m Rx event configuration register
+ */
+typedef union {
+    struct {
+        /** rx_lim_chm : R/W; bitpos: [8:0]; default: 128;
+         *  This register is used to configure the maximum entries that CHANNELm can receive.
+         */
+        uint32_t rx_lim_chm: 9;
+        uint32_t reserved_9: 23;
+    };
+    uint32_t val;
+} rmt_chm_rx_lim_reg_t;
+
+/** Group: Version register */
+/** Type of date register
+ *  RMT version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35655953;
+         *  This is the version register.
+         */
+        uint32_t date: 28;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} rmt_date_reg_t;
+
+typedef struct rmt_dev_t {
+    volatile rmt_chndata_reg_t chndata[4];
+    volatile rmt_chmdata_reg_t chmdata[4];
+    volatile rmt_chnconf0_reg_t chnconf0[4];
+    volatile struct {
+        rmt_chmconf0_reg_t conf0;
+        rmt_chmconf1_reg_t conf1;
+    } chmconf[4];
+    volatile rmt_chnstatus_reg_t chnstatus[4];
+    volatile rmt_chmstatus_reg_t chmstatus[4];
+    volatile rmt_int_raw_reg_t int_raw;
+    volatile rmt_int_st_reg_t int_st;
+    volatile rmt_int_ena_reg_t int_ena;
+    volatile rmt_int_clr_reg_t int_clr;
+    volatile rmt_chncarrier_duty_reg_t chncarrier_duty[4];
+    volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[4];
+    volatile rmt_chn_tx_lim_reg_t chn_tx_lim[4];
+    volatile rmt_chm_rx_lim_reg_t chm_rx_lim[4];
+    volatile rmt_sys_conf_reg_t sys_conf;
+    volatile rmt_tx_sim_reg_t tx_sim;
+    volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst;
+    volatile rmt_date_reg_t date;
+} rmt_dev_t;
+
+extern rmt_dev_t RMT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/rsa_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/rsa_reg.h
new file mode 100644
index 0000000000..c100dbdbaa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/rsa_reg.h
@@ -0,0 +1,212 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RSA_M_MEM register
+ *  Represents M
+ */
+#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
+#define RSA_M_MEM_SIZE_BYTES 16
+
+/** RSA_Z_MEM register
+ *  Represents Z
+ */
+#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
+#define RSA_Z_MEM_SIZE_BYTES 16
+
+/** RSA_Y_MEM register
+ *  Represents Y
+ */
+#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400)
+#define RSA_Y_MEM_SIZE_BYTES 16
+
+/** RSA_X_MEM register
+ *  Represents X
+ */
+#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600)
+#define RSA_X_MEM_SIZE_BYTES 16
+
+/** RSA_M_PRIME_REG register
+ *  Represents M'
+ */
+#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800)
+/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0;
+ *  Represents M'
+ */
+#define RSA_M_PRIME    0xFFFFFFFFU
+#define RSA_M_PRIME_M  (RSA_M_PRIME_V << RSA_M_PRIME_S)
+#define RSA_M_PRIME_V  0xFFFFFFFFU
+#define RSA_M_PRIME_S  0
+
+/** RSA_MODE_REG register
+ *  Configures RSA length
+ */
+#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804)
+/** RSA_MODE : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the RSA length.
+ */
+#define RSA_MODE    0x0000007FU
+#define RSA_MODE_M  (RSA_MODE_V << RSA_MODE_S)
+#define RSA_MODE_V  0x0000007FU
+#define RSA_MODE_S  0
+
+/** RSA_QUERY_CLEAN_REG register
+ *  RSA initialization status
+ */
+#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
+/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the RSA memory completes initialization.
+ *  0: Not complete
+ *  1: Completed
+ */
+#define RSA_QUERY_CLEAN    (BIT(0))
+#define RSA_QUERY_CLEAN_M  (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S)
+#define RSA_QUERY_CLEAN_V  0x00000001U
+#define RSA_QUERY_CLEAN_S  0
+
+/** RSA_SET_START_MODEXP_REG register
+ *  Starts modular exponentiation
+ */
+#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c)
+/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to starts the modular exponentiation.
+ *  0: No effect
+ *  1: Start
+ */
+#define RSA_SET_START_MODEXP    (BIT(0))
+#define RSA_SET_START_MODEXP_M  (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S)
+#define RSA_SET_START_MODEXP_V  0x00000001U
+#define RSA_SET_START_MODEXP_S  0
+
+/** RSA_SET_START_MODMULT_REG register
+ *  Starts modular multiplication
+ */
+#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810)
+/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to start the modular multiplication.
+ *  0: No effect
+ *  1: Start
+ */
+#define RSA_SET_START_MODMULT    (BIT(0))
+#define RSA_SET_START_MODMULT_M  (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S)
+#define RSA_SET_START_MODMULT_V  0x00000001U
+#define RSA_SET_START_MODMULT_S  0
+
+/** RSA_SET_START_MULT_REG register
+ *  Starts multiplication
+ */
+#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814)
+/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to start the multiplication.
+ *  0: No effect
+ *  1: Start
+ */
+#define RSA_SET_START_MULT    (BIT(0))
+#define RSA_SET_START_MULT_M  (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S)
+#define RSA_SET_START_MULT_V  0x00000001U
+#define RSA_SET_START_MULT_S  0
+
+/** RSA_QUERY_IDLE_REG register
+ *  Represents the RSA status
+ */
+#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818)
+/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0;
+ *  Represents the RSA status.
+ *  0: Busy
+ *  1: Idle
+ */
+#define RSA_QUERY_IDLE    (BIT(0))
+#define RSA_QUERY_IDLE_M  (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S)
+#define RSA_QUERY_IDLE_V  0x00000001U
+#define RSA_QUERY_IDLE_S  0
+
+/** RSA_INT_CLR_REG register
+ *  Clears RSA interrupt
+ */
+#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c)
+/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear the RSA interrupt.
+ */
+#define RSA_CLEAR_INTERRUPT    (BIT(0))
+#define RSA_CLEAR_INTERRUPT_M  (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S)
+#define RSA_CLEAR_INTERRUPT_V  0x00000001U
+#define RSA_CLEAR_INTERRUPT_S  0
+
+/** RSA_CONSTANT_TIME_REG register
+ *  Configures the constant_time option
+ */
+#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
+/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
+ *  Configures the constant_time option.
+ *  0: Acceleration
+ *  1: No acceleration (default)
+ */
+#define RSA_CONSTANT_TIME    (BIT(0))
+#define RSA_CONSTANT_TIME_M  (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
+#define RSA_CONSTANT_TIME_V  0x00000001U
+#define RSA_CONSTANT_TIME_S  0
+
+/** RSA_SEARCH_ENABLE_REG register
+ *  Configures the search option
+ */
+#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
+/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Configures the search option.
+ *  0: No acceleration (default)
+ *  1: Acceleration
+ *  This option should be used together with RSA_SEARCH_POS_REG.
+ */
+#define RSA_SEARCH_ENABLE    (BIT(0))
+#define RSA_SEARCH_ENABLE_M  (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S)
+#define RSA_SEARCH_ENABLE_V  0x00000001U
+#define RSA_SEARCH_ENABLE_S  0
+
+/** RSA_SEARCH_POS_REG register
+ *  Configures the search position
+ */
+#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
+/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0;
+ *  Configures the starting address to start search. This field should be used together
+ *  with RSA_SEARCH_ENABLE_REG. The field is only valid when RSA_SEARCH_ENABLE is high.
+ */
+#define RSA_SEARCH_POS    0x00000FFFU
+#define RSA_SEARCH_POS_M  (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S)
+#define RSA_SEARCH_POS_V  0x00000FFFU
+#define RSA_SEARCH_POS_S  0
+
+/** RSA_INT_ENA_REG register
+ *  Enables the RSA interrupt
+ */
+#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c)
+/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable the RSA interrupt.
+ */
+#define RSA_INT_ENA    (BIT(0))
+#define RSA_INT_ENA_M  (RSA_INT_ENA_V << RSA_INT_ENA_S)
+#define RSA_INT_ENA_V  0x00000001U
+#define RSA_INT_ENA_S  0
+
+/** RSA_DATE_REG register
+ *  Version control register
+ */
+#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830)
+/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624;
+ *  Version control register.
+ */
+#define RSA_DATE    0x3FFFFFFFU
+#define RSA_DATE_M  (RSA_DATE_V << RSA_DATE_S)
+#define RSA_DATE_V  0x3FFFFFFFU
+#define RSA_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/rsa_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/rsa_struct.h
new file mode 100644
index 0000000000..44f1d9ea58
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/rsa_struct.h
@@ -0,0 +1,252 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory */
+
+/** Group: Control / Configuration Registers */
+/** Type of m_prime register
+ *  Represents M'
+ */
+typedef union {
+    struct {
+        /** m_prime : R/W; bitpos: [31:0]; default: 0;
+         *  Represents M'
+         */
+        uint32_t m_prime:32;
+    };
+    uint32_t val;
+} rsa_m_prime_reg_t;
+
+/** Type of mode register
+ *  Configures RSA length
+ */
+typedef union {
+    struct {
+        /** mode : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the RSA length.
+         */
+        uint32_t mode:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} rsa_mode_reg_t;
+
+/** Type of set_start_modexp register
+ *  Starts modular exponentiation
+ */
+typedef union {
+    struct {
+        /** set_start_modexp : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to starts the modular exponentiation.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t set_start_modexp:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_set_start_modexp_reg_t;
+
+/** Type of set_start_modmult register
+ *  Starts modular multiplication
+ */
+typedef union {
+    struct {
+        /** set_start_modmult : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to start the modular multiplication.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t set_start_modmult:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_set_start_modmult_reg_t;
+
+/** Type of set_start_mult register
+ *  Starts multiplication
+ */
+typedef union {
+    struct {
+        /** set_start_mult : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to start the multiplication.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t set_start_mult:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_set_start_mult_reg_t;
+
+/** Type of query_idle register
+ *  Represents the RSA status
+ */
+typedef union {
+    struct {
+        /** query_idle : RO; bitpos: [0]; default: 0;
+         *  Represents the RSA status.
+         *  0: Busy
+         *  1: Idle
+         */
+        uint32_t query_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_query_idle_reg_t;
+
+/** Type of constant_time register
+ *  Configures the constant_time option
+ */
+typedef union {
+    struct {
+        /** constant_time : R/W; bitpos: [0]; default: 1;
+         *  Configures the constant_time option.
+         *  0: Acceleration
+         *  1: No acceleration (default)
+         */
+        uint32_t constant_time:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_constant_time_reg_t;
+
+/** Type of search_enable register
+ *  Configures the search option
+ */
+typedef union {
+    struct {
+        /** search_enable : R/W; bitpos: [0]; default: 0;
+         *  Configures the search option.
+         *  0: No acceleration (default)
+         *  1: Acceleration
+         *  This option should be used together with RSA_SEARCH_POS_REG.
+         */
+        uint32_t search_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_search_enable_reg_t;
+
+/** Type of search_pos register
+ *  Configures the search position
+ */
+typedef union {
+    struct {
+        /** search_pos : R/W; bitpos: [11:0]; default: 0;
+         *  Configures the starting address to start search. This field should be used together
+         *  with RSA_SEARCH_ENABLE_REG. The field is only valid when RSA_SEARCH_ENABLE is high.
+         */
+        uint32_t search_pos:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} rsa_search_pos_reg_t;
+
+
+/** Group: Status Register */
+/** Type of query_clean register
+ *  RSA initialization status
+ */
+typedef union {
+    struct {
+        /** query_clean : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the RSA memory completes initialization.
+         *  0: Not complete
+         *  1: Completed
+         */
+        uint32_t query_clean:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_query_clean_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_clr register
+ *  Clears RSA interrupt
+ */
+typedef union {
+    struct {
+        /** clear_interrupt : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear the RSA interrupt.
+         */
+        uint32_t clear_interrupt:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Enables the RSA interrupt
+ */
+typedef union {
+    struct {
+        /** int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable the RSA interrupt.
+         */
+        uint32_t int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_int_ena_reg_t;
+
+
+/** Group: Version Control Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [29:0]; default: 538969624;
+         *  Version control register.
+         */
+        uint32_t date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} rsa_date_reg_t;
+
+
+typedef struct {
+    volatile uint32_t m[4];
+    uint32_t reserved_010[124];
+    volatile uint32_t z[4];
+    uint32_t reserved_210[124];
+    volatile uint32_t y[4];
+    uint32_t reserved_410[124];
+    volatile uint32_t x[4];
+    uint32_t reserved_610[124];
+    volatile rsa_m_prime_reg_t m_prime;
+    volatile rsa_mode_reg_t mode;
+    volatile rsa_query_clean_reg_t query_clean;
+    volatile rsa_set_start_modexp_reg_t set_start_modexp;
+    volatile rsa_set_start_modmult_reg_t set_start_modmult;
+    volatile rsa_set_start_mult_reg_t set_start_mult;
+    volatile rsa_query_idle_reg_t query_idle;
+    volatile rsa_int_clr_reg_t int_clr;
+    volatile rsa_constant_time_reg_t constant_time;
+    volatile rsa_search_enable_reg_t search_enable;
+    volatile rsa_search_pos_reg_t search_pos;
+    volatile rsa_int_ena_reg_t int_ena;
+    volatile rsa_date_reg_t date;
+} rsa_dev_t;
+
+extern rsa_dev_t RSA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/rtclockcali_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/rtclockcali_reg.h
new file mode 100644
index 0000000000..dbf69d31a2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/rtclockcali_reg.h
@@ -0,0 +1,578 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RTCLOCKCALI_LP_CALI_TIMER_REG register
+ *  need_des
+ */
+#define RTCLOCKCALI_LP_CALI_TIMER_REG (DR_REG_RTCLOCKCALI_BASE + 0x0)
+/** RTCLOCKCALI_TIMER_TARGET : R/W; bitpos: [29:0]; default: 4095;
+ *  need_des
+ */
+#define RTCLOCKCALI_TIMER_TARGET    0x3FFFFFFFU
+#define RTCLOCKCALI_TIMER_TARGET_M  (RTCLOCKCALI_TIMER_TARGET_V << RTCLOCKCALI_TIMER_TARGET_S)
+#define RTCLOCKCALI_TIMER_TARGET_V  0x3FFFFFFFU
+#define RTCLOCKCALI_TIMER_TARGET_S  0
+/** RTCLOCKCALI_TIMER_STOP : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_TIMER_STOP    (BIT(30))
+#define RTCLOCKCALI_TIMER_STOP_M  (RTCLOCKCALI_TIMER_STOP_V << RTCLOCKCALI_TIMER_STOP_S)
+#define RTCLOCKCALI_TIMER_STOP_V  0x00000001U
+#define RTCLOCKCALI_TIMER_STOP_S  30
+/** RTCLOCKCALI_TIMER_START : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_TIMER_START    (BIT(31))
+#define RTCLOCKCALI_TIMER_START_M  (RTCLOCKCALI_TIMER_START_V << RTCLOCKCALI_TIMER_START_S)
+#define RTCLOCKCALI_TIMER_START_V  0x00000001U
+#define RTCLOCKCALI_TIMER_START_S  31
+
+/** RTCLOCKCALI_RTCCALICFG_SLOW_REG register
+ *  RTC calibration configure register
+ */
+#define RTCLOCKCALI_RTCCALICFG_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x4)
+/** RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW : R/W; bitpos: [12]; default: 1;
+ *  0: one-shot frequency calculation,1: periodic frequency calculation,
+ */
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW    (BIT(12))
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_M  (RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_V << RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_S  12
+/** RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW : R/W; bitpos: [14:13]; default: 0;
+ *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+ */
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW    0x00000003U
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_M  (RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_V << RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_V  0x00000003U
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_S  13
+/** RTCLOCKCALI_RTC_CALI_RDY_SLOW : RO; bitpos: [15]; default: 0;
+ *  indicate one-shot frequency calculation is done.
+ */
+#define RTCLOCKCALI_RTC_CALI_RDY_SLOW    (BIT(15))
+#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_M  (RTCLOCKCALI_RTC_CALI_RDY_SLOW_V << RTCLOCKCALI_RTC_CALI_RDY_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_S  15
+/** RTCLOCKCALI_RTC_CALI_MAX_SLOW : R/W; bitpos: [30:16]; default: 1;
+ *  Configure the time to calculate RTC slow clock's frequency.
+ */
+#define RTCLOCKCALI_RTC_CALI_MAX_SLOW    0x00007FFFU
+#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_M  (RTCLOCKCALI_RTC_CALI_MAX_SLOW_V << RTCLOCKCALI_RTC_CALI_MAX_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_V  0x00007FFFU
+#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_S  16
+/** RTCLOCKCALI_RTC_CALI_START_SLOW : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start one-shot frequency calculation.
+ */
+#define RTCLOCKCALI_RTC_CALI_START_SLOW    (BIT(31))
+#define RTCLOCKCALI_RTC_CALI_START_SLOW_M  (RTCLOCKCALI_RTC_CALI_START_SLOW_V << RTCLOCKCALI_RTC_CALI_START_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_START_SLOW_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_START_SLOW_S  31
+
+/** RTCLOCKCALI_RTCCALICFG_FAST_REG register
+ *  RTC calibration configure register
+ */
+#define RTCLOCKCALI_RTCCALICFG_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x8)
+/** RTCLOCKCALI_FOSC_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
+ *  fosc clock divider number
+ */
+#define RTCLOCKCALI_FOSC_DIV_NUM    0x000000FFU
+#define RTCLOCKCALI_FOSC_DIV_NUM_M  (RTCLOCKCALI_FOSC_DIV_NUM_V << RTCLOCKCALI_FOSC_DIV_NUM_S)
+#define RTCLOCKCALI_FOSC_DIV_NUM_V  0x000000FFU
+#define RTCLOCKCALI_FOSC_DIV_NUM_S  4
+/** RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST : R/W; bitpos: [12]; default: 1;
+ *  0: one-shot frequency calculation,1: periodic frequency calculation,
+ */
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST    (BIT(12))
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_M  (RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_V << RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_S  12
+/** RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST : R/W; bitpos: [14:13]; default: 0;
+ *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+ */
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST    0x00000003U
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_M  (RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_V << RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_V  0x00000003U
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_S  13
+/** RTCLOCKCALI_RTC_CALI_RDY_FAST : RO; bitpos: [15]; default: 0;
+ *  indicate one-shot frequency calculation is done.
+ */
+#define RTCLOCKCALI_RTC_CALI_RDY_FAST    (BIT(15))
+#define RTCLOCKCALI_RTC_CALI_RDY_FAST_M  (RTCLOCKCALI_RTC_CALI_RDY_FAST_V << RTCLOCKCALI_RTC_CALI_RDY_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_RDY_FAST_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_RDY_FAST_S  15
+/** RTCLOCKCALI_RTC_CALI_MAX_FAST : R/W; bitpos: [30:16]; default: 1;
+ *  Configure the time to calculate RTC slow clock's frequency.
+ */
+#define RTCLOCKCALI_RTC_CALI_MAX_FAST    0x00007FFFU
+#define RTCLOCKCALI_RTC_CALI_MAX_FAST_M  (RTCLOCKCALI_RTC_CALI_MAX_FAST_V << RTCLOCKCALI_RTC_CALI_MAX_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_MAX_FAST_V  0x00007FFFU
+#define RTCLOCKCALI_RTC_CALI_MAX_FAST_S  16
+/** RTCLOCKCALI_RTC_CALI_START_FAST : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start one-shot frequency calculation.
+ */
+#define RTCLOCKCALI_RTC_CALI_START_FAST    (BIT(31))
+#define RTCLOCKCALI_RTC_CALI_START_FAST_M  (RTCLOCKCALI_RTC_CALI_START_FAST_V << RTCLOCKCALI_RTC_CALI_START_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_START_FAST_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_START_FAST_S  31
+
+/** RTCLOCKCALI_RTCCALICFG1_SLOW_REG register
+ *  RTC calibration configure1 register
+ */
+#define RTCLOCKCALI_RTCCALICFG1_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0xc)
+/** RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW : RO; bitpos: [0]; default: 0;
+ *  indicate periodic frequency calculation is done.
+ */
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW    (BIT(0))
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_M  (RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_V << RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_S  0
+/** RTCLOCKCALI_RTC_CALI_VALUE_SLOW : RO; bitpos: [31:7]; default: 0;
+ *  When one-shot or periodic frequency calculation is done, read this value to
+ *  calculate RTC slow clock's frequency.
+ */
+#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW    0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_M  (RTCLOCKCALI_RTC_CALI_VALUE_SLOW_V << RTCLOCKCALI_RTC_CALI_VALUE_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_V  0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_S  7
+
+/** RTCLOCKCALI_RTCCALICFG1_FAST_REG register
+ *  RTC calibration configure1 register
+ */
+#define RTCLOCKCALI_RTCCALICFG1_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x10)
+/** RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST : RO; bitpos: [0]; default: 0;
+ *  indicate periodic frequency calculation is done.
+ */
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST    (BIT(0))
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_M  (RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_V << RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_S  0
+/** RTCLOCKCALI_RTC_CALI_VALUE_FAST : RO; bitpos: [31:7]; default: 0;
+ *  When one-shot or periodic frequency calculation is done, read this value to
+ *  calculate RTC slow clock's frequency.
+ */
+#define RTCLOCKCALI_RTC_CALI_VALUE_FAST    0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_M  (RTCLOCKCALI_RTC_CALI_VALUE_FAST_V << RTCLOCKCALI_RTC_CALI_VALUE_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_V  0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_S  7
+
+/** RTCLOCKCALI_RTCCALICFG2_REG register
+ *  Timer group calibration register
+ */
+#define RTCLOCKCALI_RTCCALICFG2_REG (DR_REG_RTCLOCKCALI_BASE + 0x14)
+/** RTCLOCKCALI_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
+ *  RTC calibration timeout indicator
+ */
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT    (BIT(0))
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_M  (RTCLOCKCALI_RTC_CALI_TIMEOUT_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_S)
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_S  0
+/** RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
+ *  Cycles that release calibration timeout reset
+ */
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT    0x0000000FU
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_M  (RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_S)
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_V  0x0000000FU
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_S  3
+/** RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
+ *  Threshold value for the RTC calibration timer. If the calibration timer's value
+ *  exceeds this threshold, a timeout is triggered.
+ */
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES    0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_M  (RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_S)
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_V  0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_S  7
+
+/** RTCLOCKCALI_DFREQ_HIGH_LIMIT_SLOW_REG register
+ *  RTC slow clock dfreq high limit.
+ */
+#define RTCLOCKCALI_DFREQ_HIGH_LIMIT_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x18)
+/** RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW : R/W; bitpos: [7:0]; default: 16;
+ *  When rtc_cali_value upper/lower than reg_high/low_limit +/-
+ *  reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
+ */
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW    0x000000FFU
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_M  (RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_V << RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_S)
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_V  0x000000FFU
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_S  0
+/** RTCLOCKCALI_HIGH_LIMIT_SLOW : R/W; bitpos: [31:8]; default: 267;
+ *  when rtc_cali_value upper than reg_high_limit,frequency of osc will  increase .
+ */
+#define RTCLOCKCALI_HIGH_LIMIT_SLOW    0x00FFFFFFU
+#define RTCLOCKCALI_HIGH_LIMIT_SLOW_M  (RTCLOCKCALI_HIGH_LIMIT_SLOW_V << RTCLOCKCALI_HIGH_LIMIT_SLOW_S)
+#define RTCLOCKCALI_HIGH_LIMIT_SLOW_V  0x00FFFFFFU
+#define RTCLOCKCALI_HIGH_LIMIT_SLOW_S  8
+
+/** RTCLOCKCALI_DFREQ_LOW_LIMIT_SLOW_REG register
+ *  RTC slow clock dfreq low limit.
+ */
+#define RTCLOCKCALI_DFREQ_LOW_LIMIT_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x1c)
+/** RTCLOCKCALI_LOW_LIMIT_SLOW : R/W; bitpos: [31:8]; default: 266;
+ *  when rtc_cali_value lower than reg_low_limit,frequency of osc will  decrease .
+ */
+#define RTCLOCKCALI_LOW_LIMIT_SLOW    0x00FFFFFFU
+#define RTCLOCKCALI_LOW_LIMIT_SLOW_M  (RTCLOCKCALI_LOW_LIMIT_SLOW_V << RTCLOCKCALI_LOW_LIMIT_SLOW_S)
+#define RTCLOCKCALI_LOW_LIMIT_SLOW_V  0x00FFFFFFU
+#define RTCLOCKCALI_LOW_LIMIT_SLOW_S  8
+
+/** RTCLOCKCALI_DFREQ_HIGH_LIMIT_FAST_REG register
+ *  RTC fast clock dfreq high limit.
+ */
+#define RTCLOCKCALI_DFREQ_HIGH_LIMIT_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x20)
+/** RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST : R/W; bitpos: [7:0]; default: 16;
+ *  When rtc_cali_value upper/lower than reg_high/low_limit +/-
+ *  reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
+ */
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST    0x000000FFU
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_M  (RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_V << RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_S)
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_V  0x000000FFU
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_S  0
+/** RTCLOCKCALI_HIGH_LIMIT_FAST : R/W; bitpos: [31:8]; default: 267;
+ *  when rtc_cali_value upper than reg_high_limit,frequency of osc will  increase .
+ */
+#define RTCLOCKCALI_HIGH_LIMIT_FAST    0x00FFFFFFU
+#define RTCLOCKCALI_HIGH_LIMIT_FAST_M  (RTCLOCKCALI_HIGH_LIMIT_FAST_V << RTCLOCKCALI_HIGH_LIMIT_FAST_S)
+#define RTCLOCKCALI_HIGH_LIMIT_FAST_V  0x00FFFFFFU
+#define RTCLOCKCALI_HIGH_LIMIT_FAST_S  8
+
+/** RTCLOCKCALI_DFREQ_LOW_LIMIT_FAST_REG register
+ *  RTC fast clock dfreq low limit.
+ */
+#define RTCLOCKCALI_DFREQ_LOW_LIMIT_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x24)
+/** RTCLOCKCALI_LOW_LIMIT_FAST : R/W; bitpos: [31:8]; default: 266;
+ *  when rtc_cali_value lower than reg_low_limit,frequency of osc will  decrease .
+ */
+#define RTCLOCKCALI_LOW_LIMIT_FAST    0x00FFFFFFU
+#define RTCLOCKCALI_LOW_LIMIT_FAST_M  (RTCLOCKCALI_LOW_LIMIT_FAST_V << RTCLOCKCALI_LOW_LIMIT_FAST_S)
+#define RTCLOCKCALI_LOW_LIMIT_FAST_V  0x00FFFFFFU
+#define RTCLOCKCALI_LOW_LIMIT_FAST_S  8
+
+/** RTCLOCKCALI_DFREQ_CONF2_REG register
+ *  RTC DFREQ CONF2
+ */
+#define RTCLOCKCALI_DFREQ_CONF2_REG (DR_REG_RTCLOCKCALI_BASE + 0x28)
+/** RTCLOCKCALI_DREQ_UPDATE : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_DREQ_UPDATE    (BIT(0))
+#define RTCLOCKCALI_DREQ_UPDATE_M  (RTCLOCKCALI_DREQ_UPDATE_V << RTCLOCKCALI_DREQ_UPDATE_S)
+#define RTCLOCKCALI_DREQ_UPDATE_V  0x00000001U
+#define RTCLOCKCALI_DREQ_UPDATE_S  0
+/** RTCLOCKCALI_DREQ_INIT_32K : WT; bitpos: [2]; default: 0;
+ *  Initialize the value of 32K OSC dfreq setting.
+ */
+#define RTCLOCKCALI_DREQ_INIT_32K    (BIT(2))
+#define RTCLOCKCALI_DREQ_INIT_32K_M  (RTCLOCKCALI_DREQ_INIT_32K_V << RTCLOCKCALI_DREQ_INIT_32K_S)
+#define RTCLOCKCALI_DREQ_INIT_32K_V  0x00000001U
+#define RTCLOCKCALI_DREQ_INIT_32K_S  2
+/** RTCLOCKCALI_DREQ_INIT_FOSC : WT; bitpos: [3]; default: 0;
+ *  Initialize the value of FOSC  dfreq setting.
+ */
+#define RTCLOCKCALI_DREQ_INIT_FOSC    (BIT(3))
+#define RTCLOCKCALI_DREQ_INIT_FOSC_M  (RTCLOCKCALI_DREQ_INIT_FOSC_V << RTCLOCKCALI_DREQ_INIT_FOSC_S)
+#define RTCLOCKCALI_DREQ_INIT_FOSC_V  0x00000001U
+#define RTCLOCKCALI_DREQ_INIT_FOSC_S  3
+/** RTCLOCKCALI_DREQ_INIT_SOSC : WT; bitpos: [4]; default: 0;
+ *  Initialize the value of SOSC  dfreq setting.
+ */
+#define RTCLOCKCALI_DREQ_INIT_SOSC    (BIT(4))
+#define RTCLOCKCALI_DREQ_INIT_SOSC_M  (RTCLOCKCALI_DREQ_INIT_SOSC_V << RTCLOCKCALI_DREQ_INIT_SOSC_S)
+#define RTCLOCKCALI_DREQ_INIT_SOSC_V  0x00000001U
+#define RTCLOCKCALI_DREQ_INIT_SOSC_S  4
+/** RTCLOCKCALI_32K_DFREQ_SEL : R/W; bitpos: [5]; default: 0;
+ *  1:Frequency of 32k controlled by calibration module.0:Frequency of 32k controlled
+ *  by register from system-register bank
+ */
+#define RTCLOCKCALI_32K_DFREQ_SEL    (BIT(5))
+#define RTCLOCKCALI_32K_DFREQ_SEL_M  (RTCLOCKCALI_32K_DFREQ_SEL_V << RTCLOCKCALI_32K_DFREQ_SEL_S)
+#define RTCLOCKCALI_32K_DFREQ_SEL_V  0x00000001U
+#define RTCLOCKCALI_32K_DFREQ_SEL_S  5
+/** RTCLOCKCALI_FOSC_DFREQ_SEL : R/W; bitpos: [6]; default: 0;
+ *  1:Frequency of FOSC controlled by calibration module.0:Frequency of FOSC controlled
+ *  by register from system-register bank
+ */
+#define RTCLOCKCALI_FOSC_DFREQ_SEL    (BIT(6))
+#define RTCLOCKCALI_FOSC_DFREQ_SEL_M  (RTCLOCKCALI_FOSC_DFREQ_SEL_V << RTCLOCKCALI_FOSC_DFREQ_SEL_S)
+#define RTCLOCKCALI_FOSC_DFREQ_SEL_V  0x00000001U
+#define RTCLOCKCALI_FOSC_DFREQ_SEL_S  6
+/** RTCLOCKCALI_SOSC_DFREQ_SEL : R/W; bitpos: [7]; default: 0;
+ *  1:Frequency of SOSC controlled by calibration module.0:Frequency of SOSC controlled
+ *  by register from system-register bank
+ */
+#define RTCLOCKCALI_SOSC_DFREQ_SEL    (BIT(7))
+#define RTCLOCKCALI_SOSC_DFREQ_SEL_M  (RTCLOCKCALI_SOSC_DFREQ_SEL_V << RTCLOCKCALI_SOSC_DFREQ_SEL_S)
+#define RTCLOCKCALI_SOSC_DFREQ_SEL_V  0x00000001U
+#define RTCLOCKCALI_SOSC_DFREQ_SEL_S  7
+/** RTCLOCKCALI_FINE_STEP : R/W; bitpos: [15:8]; default: 1;
+ *  Frequency fine step.
+ */
+#define RTCLOCKCALI_FINE_STEP    0x000000FFU
+#define RTCLOCKCALI_FINE_STEP_M  (RTCLOCKCALI_FINE_STEP_V << RTCLOCKCALI_FINE_STEP_S)
+#define RTCLOCKCALI_FINE_STEP_V  0x000000FFU
+#define RTCLOCKCALI_FINE_STEP_S  8
+/** RTCLOCKCALI_COARSE_STEP_FAST : R/W; bitpos: [23:16]; default: 8;
+ *  Frequency coarse step,use to decrease calibration time.
+ */
+#define RTCLOCKCALI_COARSE_STEP_FAST    0x000000FFU
+#define RTCLOCKCALI_COARSE_STEP_FAST_M  (RTCLOCKCALI_COARSE_STEP_FAST_V << RTCLOCKCALI_COARSE_STEP_FAST_S)
+#define RTCLOCKCALI_COARSE_STEP_FAST_V  0x000000FFU
+#define RTCLOCKCALI_COARSE_STEP_FAST_S  16
+/** RTCLOCKCALI_COARSE_STEP_SLOW : R/W; bitpos: [31:24]; default: 8;
+ *  Frequency coarse step,use to decrease calibration time.
+ */
+#define RTCLOCKCALI_COARSE_STEP_SLOW    0x000000FFU
+#define RTCLOCKCALI_COARSE_STEP_SLOW_M  (RTCLOCKCALI_COARSE_STEP_SLOW_V << RTCLOCKCALI_COARSE_STEP_SLOW_S)
+#define RTCLOCKCALI_COARSE_STEP_SLOW_V  0x000000FFU
+#define RTCLOCKCALI_COARSE_STEP_SLOW_S  24
+
+/** RTCLOCKCALI_CALI_EN_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_CALI_EN_REG (DR_REG_RTCLOCKCALI_BASE + 0x2c)
+/** RTCLOCKCALI_CALI_EN_32K : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define RTCLOCKCALI_CALI_EN_32K    (BIT(0))
+#define RTCLOCKCALI_CALI_EN_32K_M  (RTCLOCKCALI_CALI_EN_32K_V << RTCLOCKCALI_CALI_EN_32K_S)
+#define RTCLOCKCALI_CALI_EN_32K_V  0x00000001U
+#define RTCLOCKCALI_CALI_EN_32K_S  0
+/** RTCLOCKCALI_CALI_EN_FOSC : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_CALI_EN_FOSC    (BIT(1))
+#define RTCLOCKCALI_CALI_EN_FOSC_M  (RTCLOCKCALI_CALI_EN_FOSC_V << RTCLOCKCALI_CALI_EN_FOSC_S)
+#define RTCLOCKCALI_CALI_EN_FOSC_V  0x00000001U
+#define RTCLOCKCALI_CALI_EN_FOSC_S  1
+/** RTCLOCKCALI_CALI_EN_SOSC : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_CALI_EN_SOSC    (BIT(2))
+#define RTCLOCKCALI_CALI_EN_SOSC_M  (RTCLOCKCALI_CALI_EN_SOSC_V << RTCLOCKCALI_CALI_EN_SOSC_S)
+#define RTCLOCKCALI_CALI_EN_SOSC_V  0x00000001U
+#define RTCLOCKCALI_CALI_EN_SOSC_S  2
+
+/** RTCLOCKCALI_DFREQ_VALUE_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_DFREQ_VALUE_REG (DR_REG_RTCLOCKCALI_BASE + 0x30)
+/** RTCLOCKCALI_DREQ_32K : RO; bitpos: [11:2]; default: 172;
+ *  The value of dfreq num of 32k.
+ */
+#define RTCLOCKCALI_DREQ_32K    0x000003FFU
+#define RTCLOCKCALI_DREQ_32K_M  (RTCLOCKCALI_DREQ_32K_V << RTCLOCKCALI_DREQ_32K_S)
+#define RTCLOCKCALI_DREQ_32K_V  0x000003FFU
+#define RTCLOCKCALI_DREQ_32K_S  2
+/** RTCLOCKCALI_DREQ_FOSC : RO; bitpos: [21:12]; default: 512;
+ *  The value of dfreq num of FOSC.
+ */
+#define RTCLOCKCALI_DREQ_FOSC    0x000003FFU
+#define RTCLOCKCALI_DREQ_FOSC_M  (RTCLOCKCALI_DREQ_FOSC_V << RTCLOCKCALI_DREQ_FOSC_S)
+#define RTCLOCKCALI_DREQ_FOSC_V  0x000003FFU
+#define RTCLOCKCALI_DREQ_FOSC_S  12
+/** RTCLOCKCALI_DREQ_SOSC : RO; bitpos: [31:22]; default: 512;
+ *  The value of dfreq num of SOSC.
+ */
+#define RTCLOCKCALI_DREQ_SOSC    0x000003FFU
+#define RTCLOCKCALI_DREQ_SOSC_M  (RTCLOCKCALI_DREQ_SOSC_V << RTCLOCKCALI_DREQ_SOSC_S)
+#define RTCLOCKCALI_DREQ_SOSC_V  0x000003FFU
+#define RTCLOCKCALI_DREQ_SOSC_S  22
+
+/** RTCLOCKCALI_BYPASS_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_BYPASS_REG (DR_REG_RTCLOCKCALI_BASE + 0x34)
+/** RTCLOCKCALI_HP_SLEEP_AUTOCALI : R/W; bitpos: [30]; default: 0;
+ *  1:Chip begin to calibrating,when into hp_sleep.0:Disable this function.
+ */
+#define RTCLOCKCALI_HP_SLEEP_AUTOCALI    (BIT(30))
+#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_M  (RTCLOCKCALI_HP_SLEEP_AUTOCALI_V << RTCLOCKCALI_HP_SLEEP_AUTOCALI_S)
+#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_V  0x00000001U
+#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_S  30
+/** RTCLOCKCALI_LP_SLEEP_AUTOCALI : R/W; bitpos: [31]; default: 0;
+ *  1:Chip begin to calibrating,when into lp_sleep.0:Disable this function.
+ */
+#define RTCLOCKCALI_LP_SLEEP_AUTOCALI    (BIT(31))
+#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_M  (RTCLOCKCALI_LP_SLEEP_AUTOCALI_V << RTCLOCKCALI_LP_SLEEP_AUTOCALI_S)
+#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_V  0x00000001U
+#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_S  31
+
+/** RTCLOCKCALI_INT_RAW_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_INT_RAW_REG (DR_REG_RTCLOCKCALI_BASE + 0x38)
+/** RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Indicate the xtal timeout  once happened .
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW    (BIT(29))
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_M  (RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S  29
+/** RTCLOCKCALI_CALI_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Indicate the calibration timeout  once happened .
+ */
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW    (BIT(30))
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_M  (RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_V << RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_S)
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_V  0x00000001U
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_S  30
+/** RTCLOCKCALI_CALI_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Indicate the finish of once calibration .
+ */
+#define RTCLOCKCALI_CALI_DONE_INT_RAW    (BIT(31))
+#define RTCLOCKCALI_CALI_DONE_INT_RAW_M  (RTCLOCKCALI_CALI_DONE_INT_RAW_V << RTCLOCKCALI_CALI_DONE_INT_RAW_S)
+#define RTCLOCKCALI_CALI_DONE_INT_RAW_V  0x00000001U
+#define RTCLOCKCALI_CALI_DONE_INT_RAW_S  31
+
+/** RTCLOCKCALI_INT_ST_REG register
+ *  Interrupt state register.
+ */
+#define RTCLOCKCALI_INT_ST_REG (DR_REG_RTCLOCKCALI_BASE + 0x3c)
+/** RTCLOCKCALI_XTAL_TIMEOUT_INT_ST : RO; bitpos: [29]; default: 0;
+ *  Interrupt state register.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST    (BIT(29))
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_M  (RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_S  29
+/** RTCLOCKCALI_CALI_TIMEOUT_INT_ST : RO; bitpos: [30]; default: 0;
+ *  Interrupt state register.
+ */
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST    (BIT(30))
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_M  (RTCLOCKCALI_CALI_TIMEOUT_INT_ST_V << RTCLOCKCALI_CALI_TIMEOUT_INT_ST_S)
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_V  0x00000001U
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_S  30
+/** RTCLOCKCALI_CALI_DONE_INT_ST : RO; bitpos: [31]; default: 0;
+ *  Interrupt state register.
+ */
+#define RTCLOCKCALI_CALI_DONE_INT_ST    (BIT(31))
+#define RTCLOCKCALI_CALI_DONE_INT_ST_M  (RTCLOCKCALI_CALI_DONE_INT_ST_V << RTCLOCKCALI_CALI_DONE_INT_ST_S)
+#define RTCLOCKCALI_CALI_DONE_INT_ST_V  0x00000001U
+#define RTCLOCKCALI_CALI_DONE_INT_ST_S  31
+
+/** RTCLOCKCALI_INT_ENA_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_INT_ENA_REG (DR_REG_RTCLOCKCALI_BASE + 0x40)
+/** RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  Interrupt enable signal.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA    (BIT(29))
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_M  (RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_S  29
+/** RTCLOCKCALI_CALI_TIMEOUT_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  Interrupt enable signal.
+ */
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA    (BIT(30))
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_M  (RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_V << RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_S)
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_V  0x00000001U
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_S  30
+/** RTCLOCKCALI_CALI_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  Interrupt enable signal.
+ */
+#define RTCLOCKCALI_CALI_DONE_INT_ENA    (BIT(31))
+#define RTCLOCKCALI_CALI_DONE_INT_ENA_M  (RTCLOCKCALI_CALI_DONE_INT_ENA_V << RTCLOCKCALI_CALI_DONE_INT_ENA_S)
+#define RTCLOCKCALI_CALI_DONE_INT_ENA_V  0x00000001U
+#define RTCLOCKCALI_CALI_DONE_INT_ENA_S  31
+
+/** RTCLOCKCALI_INT_CLR_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_INT_CLR_REG (DR_REG_RTCLOCKCALI_BASE + 0x44)
+/** RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  interrupt clear signal.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR    (BIT(29))
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_M  (RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_S  29
+/** RTCLOCKCALI_CALI_TIMEOUT_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  interrupt clear signal.
+ */
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR    (BIT(30))
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_M  (RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_V << RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_S)
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_V  0x00000001U
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_S  30
+/** RTCLOCKCALI_CALI_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  interrupt clear signal.
+ */
+#define RTCLOCKCALI_CALI_DONE_INT_CLR    (BIT(31))
+#define RTCLOCKCALI_CALI_DONE_INT_CLR_M  (RTCLOCKCALI_CALI_DONE_INT_CLR_V << RTCLOCKCALI_CALI_DONE_INT_CLR_S)
+#define RTCLOCKCALI_CALI_DONE_INT_CLR_V  0x00000001U
+#define RTCLOCKCALI_CALI_DONE_INT_CLR_S  31
+
+/** RTCLOCKCALI_TIMEOUT_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_TIMEOUT_REG (DR_REG_RTCLOCKCALI_BASE + 0x48)
+/** RTCLOCKCALI_TIMEOUT_TARGET : R/W; bitpos: [29:0]; default: 0;
+ *  use to setting max calibration time .
+ */
+#define RTCLOCKCALI_TIMEOUT_TARGET    0x3FFFFFFFU
+#define RTCLOCKCALI_TIMEOUT_TARGET_M  (RTCLOCKCALI_TIMEOUT_TARGET_V << RTCLOCKCALI_TIMEOUT_TARGET_S)
+#define RTCLOCKCALI_TIMEOUT_TARGET_V  0x3FFFFFFFU
+#define RTCLOCKCALI_TIMEOUT_TARGET_S  0
+/** RTCLOCKCALI_TIMEOUT_EN : R/W; bitpos: [31]; default: 0;
+ *  use to enable calibration time-out function ,the calibration force stopping,when
+ *  timeout.
+ */
+#define RTCLOCKCALI_TIMEOUT_EN    (BIT(31))
+#define RTCLOCKCALI_TIMEOUT_EN_M  (RTCLOCKCALI_TIMEOUT_EN_V << RTCLOCKCALI_TIMEOUT_EN_S)
+#define RTCLOCKCALI_TIMEOUT_EN_V  0x00000001U
+#define RTCLOCKCALI_TIMEOUT_EN_S  31
+
+/** RTCLOCKCALI_XTAL_TIMEOUT_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_REG (DR_REG_RTCLOCKCALI_BASE + 0x4c)
+/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET : R/W; bitpos: [29:14]; default: 65535;
+ *  use to setting max xtal monitor time .
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET    0x0000FFFFU
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_M  (RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_V  0x0000FFFFU
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_S  14
+/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP : WT; bitpos: [30]; default: 0;
+ *  use to stop XTAL time-out function ,timeout happened when xtal invalid.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP    (BIT(30))
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_M  (RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_S  30
+/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_START : WT; bitpos: [31]; default: 0;
+ *  use to start XTAL time-out function ,timeout happened when xtal invalid.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START    (BIT(31))
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_M  (RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_S  31
+
+/** RTCLOCKCALI_DATE_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_DATE_REG (DR_REG_RTCLOCKCALI_BASE + 0x3fc)
+/** RTCLOCKCALI_RTCLOCKCALI_DATE : R/W; bitpos: [30:0]; default: 36708448;
+ *  need_des
+ */
+#define RTCLOCKCALI_RTCLOCKCALI_DATE    0x7FFFFFFFU
+#define RTCLOCKCALI_RTCLOCKCALI_DATE_M  (RTCLOCKCALI_RTCLOCKCALI_DATE_V << RTCLOCKCALI_RTCLOCKCALI_DATE_S)
+#define RTCLOCKCALI_RTCLOCKCALI_DATE_V  0x7FFFFFFFU
+#define RTCLOCKCALI_RTCLOCKCALI_DATE_S  0
+/** RTCLOCKCALI_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_CLK_EN    (BIT(31))
+#define RTCLOCKCALI_CLK_EN_M  (RTCLOCKCALI_CLK_EN_V << RTCLOCKCALI_CLK_EN_S)
+#define RTCLOCKCALI_CLK_EN_V  0x00000001U
+#define RTCLOCKCALI_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/rtclockcali_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/rtclockcali_struct.h
new file mode 100644
index 0000000000..56c9c4533d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/rtclockcali_struct.h
@@ -0,0 +1,521 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of lp_cali_timer register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** timer_target : R/W; bitpos: [29:0]; default: 4095;
+         *  need_des
+         */
+        uint32_t timer_target:30;
+        /** timer_stop : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t timer_stop:1;
+        /** timer_start : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t timer_start:1;
+    };
+    uint32_t val;
+} rtclockcali_lp_cali_timer_reg_t;
+
+/** Type of dfreq_high_limit_slow register
+ *  RTC slow clock dfreq high limit.
+ */
+typedef union {
+    struct {
+        /** coarse_limit_diff_slow : R/W; bitpos: [7:0]; default: 16;
+         *  When rtc_cali_value upper/lower than reg_high/low_limit +/-
+         *  reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
+         */
+        uint32_t coarse_limit_diff_slow:8;
+        /** high_limit_slow : R/W; bitpos: [31:8]; default: 267;
+         *  when rtc_cali_value upper than reg_high_limit,frequency of osc will  increase .
+         */
+        uint32_t high_limit_slow:24;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_high_limit_slow_reg_t;
+
+/** Type of dfreq_low_limit_slow register
+ *  RTC slow clock dfreq low limit.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** low_limit_slow : R/W; bitpos: [31:8]; default: 266;
+         *  when rtc_cali_value lower than reg_low_limit,frequency of osc will  decrease .
+         */
+        uint32_t low_limit_slow:24;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_low_limit_slow_reg_t;
+
+/** Type of dfreq_high_limit_fast register
+ *  RTC fast clock dfreq high limit.
+ */
+typedef union {
+    struct {
+        /** coarse_limit_diff_fast : R/W; bitpos: [7:0]; default: 16;
+         *  When rtc_cali_value upper/lower than reg_high/low_limit +/-
+         *  reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
+         */
+        uint32_t coarse_limit_diff_fast:8;
+        /** high_limit_fast : R/W; bitpos: [31:8]; default: 267;
+         *  when rtc_cali_value upper than reg_high_limit,frequency of osc will  increase .
+         */
+        uint32_t high_limit_fast:24;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_high_limit_fast_reg_t;
+
+/** Type of dfreq_low_limit_fast register
+ *  RTC fast clock dfreq low limit.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** low_limit_fast : R/W; bitpos: [31:8]; default: 266;
+         *  when rtc_cali_value lower than reg_low_limit,frequency of osc will  decrease .
+         */
+        uint32_t low_limit_fast:24;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_low_limit_fast_reg_t;
+
+/** Type of dfreq_conf2 register
+ *  RTC DFREQ CONF2
+ */
+typedef union {
+    struct {
+        /** dreq_update : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t dreq_update:1;
+        uint32_t reserved_1:1;
+        /** dreq_init_32k : WT; bitpos: [2]; default: 0;
+         *  Initialize the value of 32K OSC dfreq setting.
+         */
+        uint32_t dreq_init_32k:1;
+        /** dreq_init_fosc : WT; bitpos: [3]; default: 0;
+         *  Initialize the value of FOSC  dfreq setting.
+         */
+        uint32_t dreq_init_fosc:1;
+        /** dreq_init_sosc : WT; bitpos: [4]; default: 0;
+         *  Initialize the value of SOSC  dfreq setting.
+         */
+        uint32_t dreq_init_sosc:1;
+        /** rc32k_dfreq_sel : R/W; bitpos: [5]; default: 0;
+         *  1:Frequency of 32k controlled by calibration module.0:Frequency of 32k controlled
+         *  by register from system-register bank
+         */
+        uint32_t rc32k_dfreq_sel:1;
+        /** fosc_dfreq_sel : R/W; bitpos: [6]; default: 0;
+         *  1:Frequency of FOSC controlled by calibration module.0:Frequency of FOSC controlled
+         *  by register from system-register bank
+         */
+        uint32_t fosc_dfreq_sel:1;
+        /** sosc_dfreq_sel : R/W; bitpos: [7]; default: 0;
+         *  1:Frequency of SOSC controlled by calibration module.0:Frequency of SOSC controlled
+         *  by register from system-register bank
+         */
+        uint32_t sosc_dfreq_sel:1;
+        /** fine_step : R/W; bitpos: [15:8]; default: 1;
+         *  Frequency fine step.
+         */
+        uint32_t fine_step:8;
+        /** coarse_step_fast : R/W; bitpos: [23:16]; default: 8;
+         *  Frequency coarse step,use to decrease calibration time.
+         */
+        uint32_t coarse_step_fast:8;
+        /** coarse_step_slow : R/W; bitpos: [31:24]; default: 8;
+         *  Frequency coarse step,use to decrease calibration time.
+         */
+        uint32_t coarse_step_slow:8;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_conf2_reg_t;
+
+/** Type of cali_en register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        /** cali_en_32k : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t cali_en_32k:1;
+        /** cali_en_fosc : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t cali_en_fosc:1;
+        /** cali_en_sosc : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t cali_en_sosc:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} rtclockcali_cali_en_reg_t;
+
+/** Type of dfreq_value register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** dreq_32k : RO; bitpos: [11:2]; default: 172;
+         *  The value of dfreq num of 32k.
+         */
+        uint32_t dreq_32k:10;
+        /** dreq_fosc : RO; bitpos: [21:12]; default: 512;
+         *  The value of dfreq num of FOSC.
+         */
+        uint32_t dreq_fosc:10;
+        /** dreq_sosc : RO; bitpos: [31:22]; default: 512;
+         *  The value of dfreq num of SOSC.
+         */
+        uint32_t dreq_sosc:10;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_value_reg_t;
+
+/** Type of bypass register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** hp_sleep_autocali : R/W; bitpos: [30]; default: 0;
+         *  1:Chip begin to calibrating,when into hp_sleep.0:Disable this function.
+         */
+        uint32_t hp_sleep_autocali:1;
+        /** lp_sleep_autocali : R/W; bitpos: [31]; default: 0;
+         *  1:Chip begin to calibrating,when into lp_sleep.0:Disable this function.
+         */
+        uint32_t lp_sleep_autocali:1;
+    };
+    uint32_t val;
+} rtclockcali_bypass_reg_t;
+
+/** Type of int_raw register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** xtal_timeout_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Indicate the xtal timeout  once happened .
+         */
+        uint32_t xtal_timeout_int_raw:1;
+        /** cali_timeout_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Indicate the calibration timeout  once happened .
+         */
+        uint32_t cali_timeout_int_raw:1;
+        /** cali_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Indicate the finish of once calibration .
+         */
+        uint32_t cali_done_int_raw:1;
+    };
+    uint32_t val;
+} rtclockcali_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt state register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** xtal_timeout_int_st : RO; bitpos: [29]; default: 0;
+         *  Interrupt state register.
+         */
+        uint32_t xtal_timeout_int_st:1;
+        /** cali_timeout_int_st : RO; bitpos: [30]; default: 0;
+         *  Interrupt state register.
+         */
+        uint32_t cali_timeout_int_st:1;
+        /** cali_done_int_st : RO; bitpos: [31]; default: 0;
+         *  Interrupt state register.
+         */
+        uint32_t cali_done_int_st:1;
+    };
+    uint32_t val;
+} rtclockcali_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** xtal_timeout_int_ena : R/W; bitpos: [29]; default: 0;
+         *  Interrupt enable signal.
+         */
+        uint32_t xtal_timeout_int_ena:1;
+        /** cali_timeout_int_ena : R/W; bitpos: [30]; default: 0;
+         *  Interrupt enable signal.
+         */
+        uint32_t cali_timeout_int_ena:1;
+        /** cali_done_int_ena : R/W; bitpos: [31]; default: 0;
+         *  Interrupt enable signal.
+         */
+        uint32_t cali_done_int_ena:1;
+    };
+    uint32_t val;
+} rtclockcali_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** xtal_timeout_int_clr : WT; bitpos: [29]; default: 0;
+         *  interrupt clear signal.
+         */
+        uint32_t xtal_timeout_int_clr:1;
+        /** cali_timeout_int_clr : WT; bitpos: [30]; default: 0;
+         *  interrupt clear signal.
+         */
+        uint32_t cali_timeout_int_clr:1;
+        /** cali_done_int_clr : WT; bitpos: [31]; default: 0;
+         *  interrupt clear signal.
+         */
+        uint32_t cali_done_int_clr:1;
+    };
+    uint32_t val;
+} rtclockcali_int_clr_reg_t;
+
+/** Type of timeout register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        /** timeout_target : R/W; bitpos: [29:0]; default: 0;
+         *  use to setting max calibration time .
+         */
+        uint32_t timeout_target:30;
+        uint32_t reserved_30:1;
+        /** timeout_en : R/W; bitpos: [31]; default: 0;
+         *  use to enable calibration time-out function ,the calibration force stopping,when
+         *  timeout.
+         */
+        uint32_t timeout_en:1;
+    };
+    uint32_t val;
+} rtclockcali_timeout_reg_t;
+
+/** Type of xtal_timeout register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** xtal_timeout_cnt_target : R/W; bitpos: [29:14]; default: 65535;
+         *  use to setting max xtal monitor time .
+         */
+        uint32_t xtal_timeout_cnt_target:16;
+        /** xtal_timeout_cnt_stop : WT; bitpos: [30]; default: 0;
+         *  use to stop XTAL time-out function ,timeout happened when xtal invalid.
+         */
+        uint32_t xtal_timeout_cnt_stop:1;
+        /** xtal_timeout_cnt_start : WT; bitpos: [31]; default: 0;
+         *  use to start XTAL time-out function ,timeout happened when xtal invalid.
+         */
+        uint32_t xtal_timeout_cnt_start:1;
+    };
+    uint32_t val;
+} rtclockcali_xtal_timeout_reg_t;
+
+/** Type of date register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        /** rtclockcali_date : R/W; bitpos: [30:0]; default: 36708448;
+         *  need_des
+         */
+        uint32_t rtclockcali_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} rtclockcali_date_reg_t;
+
+
+/** Group: RTC CALI Control and configuration registers */
+/** Type of rtccalicfg_slow register
+ *  RTC calibration configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** rtc_cali_start_cycling_slow : R/W; bitpos: [12]; default: 1;
+         *  0: one-shot frequency calculation,1: periodic frequency calculation,
+         */
+        uint32_t rtc_cali_start_cycling_slow:1;
+        /** rtc_cali_clk_sel_slow : R/W; bitpos: [14:13]; default: 0;
+         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         */
+        uint32_t rtc_cali_clk_sel_slow:2;
+        /** rtc_cali_rdy_slow : RO; bitpos: [15]; default: 0;
+         *  indicate one-shot frequency calculation is done.
+         */
+        uint32_t rtc_cali_rdy_slow:1;
+        /** rtc_cali_max_slow : R/W; bitpos: [30:16]; default: 1;
+         *  Configure the time to calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_max_slow:15;
+        /** rtc_cali_start_slow : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start one-shot frequency calculation.
+         */
+        uint32_t rtc_cali_start_slow:1;
+    };
+    uint32_t val;
+} rtclockcali_rtccalicfg_slow_reg_t;
+
+/** Type of rtccalicfg_fast register
+ *  RTC calibration configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** fosc_div_num : R/W; bitpos: [11:4]; default: 0;
+         *  fosc clock divider number
+         */
+        uint32_t fosc_div_num:8;
+        /** rtc_cali_start_cycling_fast : R/W; bitpos: [12]; default: 1;
+         *  0: one-shot frequency calculation,1: periodic frequency calculation,
+         */
+        uint32_t rtc_cali_start_cycling_fast:1;
+        /** rtc_cali_clk_sel_fast : R/W; bitpos: [14:13]; default: 0;
+         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         */
+        uint32_t rtc_cali_clk_sel_fast:2;
+        /** rtc_cali_rdy_fast : RO; bitpos: [15]; default: 0;
+         *  indicate one-shot frequency calculation is done.
+         */
+        uint32_t rtc_cali_rdy_fast:1;
+        /** rtc_cali_max_fast : R/W; bitpos: [30:16]; default: 1;
+         *  Configure the time to calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_max_fast:15;
+        /** rtc_cali_start_fast : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start one-shot frequency calculation.
+         */
+        uint32_t rtc_cali_start_fast:1;
+    };
+    uint32_t val;
+} rtclockcali_rtccalicfg_fast_reg_t;
+
+/** Type of rtccalicfg1_slow register
+ *  RTC calibration configure1 register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_cycling_data_vld_slow : RO; bitpos: [0]; default: 0;
+         *  indicate periodic frequency calculation is done.
+         */
+        uint32_t rtc_cali_cycling_data_vld_slow:1;
+        uint32_t reserved_1:6;
+        /** rtc_cali_value_slow : RO; bitpos: [31:7]; default: 0;
+         *  When one-shot or periodic frequency calculation is done, read this value to
+         *  calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_value_slow:25;
+    };
+    uint32_t val;
+} rtclockcali_rtccalicfg1_slow_reg_t;
+
+/** Type of rtccalicfg1_fast register
+ *  RTC calibration configure1 register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_cycling_data_vld_fast : RO; bitpos: [0]; default: 0;
+         *  indicate periodic frequency calculation is done.
+         */
+        uint32_t rtc_cali_cycling_data_vld_fast:1;
+        uint32_t reserved_1:6;
+        /** rtc_cali_value_fast : RO; bitpos: [31:7]; default: 0;
+         *  When one-shot or periodic frequency calculation is done, read this value to
+         *  calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_value_fast:25;
+    };
+    uint32_t val;
+} rtclockcali_rtccalicfg1_fast_reg_t;
+
+/** Type of rtccalicfg2 register
+ *  Timer group calibration register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
+         *  RTC calibration timeout indicator
+         */
+        uint32_t rtc_cali_timeout:1;
+        uint32_t reserved_1:2;
+        /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
+         *  Cycles that release calibration timeout reset
+         */
+        uint32_t rtc_cali_timeout_rst_cnt:4;
+        /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
+         *  Threshold value for the RTC calibration timer. If the calibration timer's value
+         *  exceeds this threshold, a timeout is triggered.
+         */
+        uint32_t rtc_cali_timeout_thres:25;
+    };
+    uint32_t val;
+} rtclockcali_rtccalicfg2_reg_t;
+
+
+typedef struct {
+    volatile rtclockcali_lp_cali_timer_reg_t lp_cali_timer;
+    volatile rtclockcali_rtccalicfg_slow_reg_t rtccalicfg_slow;
+    volatile rtclockcali_rtccalicfg_fast_reg_t rtccalicfg_fast;
+    volatile rtclockcali_rtccalicfg1_slow_reg_t rtccalicfg1_slow;
+    volatile rtclockcali_rtccalicfg1_fast_reg_t rtccalicfg1_fast;
+    volatile rtclockcali_rtccalicfg2_reg_t rtccalicfg2;
+    volatile rtclockcali_dfreq_high_limit_slow_reg_t dfreq_high_limit_slow;
+    volatile rtclockcali_dfreq_low_limit_slow_reg_t dfreq_low_limit_slow;
+    volatile rtclockcali_dfreq_high_limit_fast_reg_t dfreq_high_limit_fast;
+    volatile rtclockcali_dfreq_low_limit_fast_reg_t dfreq_low_limit_fast;
+    volatile rtclockcali_dfreq_conf2_reg_t dfreq_conf2;
+    volatile rtclockcali_cali_en_reg_t cali_en;
+    volatile rtclockcali_dfreq_value_reg_t dfreq_value;
+    volatile rtclockcali_bypass_reg_t bypass;
+    volatile rtclockcali_int_raw_reg_t int_raw;
+    volatile rtclockcali_int_st_reg_t int_st;
+    volatile rtclockcali_int_ena_reg_t int_ena;
+    volatile rtclockcali_int_clr_reg_t int_clr;
+    volatile rtclockcali_timeout_reg_t timeout;
+    volatile rtclockcali_xtal_timeout_reg_t xtal_timeout;
+    uint32_t reserved_050[235];
+    volatile rtclockcali_date_reg_t date;
+} rtclockcali_dev_t;
+
+extern rtclockcali_dev_t RTCLOCKCALI;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rtclockcali_dev_t) == 0x400, "Invalid size of rtclockcali_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/sdmmc_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/sdmmc_eco5_struct.h
new file mode 100644
index 0000000000..c719683228
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/sdmmc_eco5_struct.h
@@ -0,0 +1,1457 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control register */
+/** Type of ctrl register
+ *  Control register
+ */
+typedef union {
+    struct {
+        /** controller_reset : R/W; bitpos: [0]; default: 0;
+         *  To reset controller, firmware should set this bit. This bit is auto-cleared after
+         *  two AHB and two sdhost_cclk_in clock cycles.
+         */
+        uint32_t controller_reset:1;
+        /** fifo_reset : R/W; bitpos: [1]; default: 0;
+         *  To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after
+         *  completion of reset operation.
+         *  Note: FIFO pointers will be out of reset after 2 cycles of system clocks in
+         *  addition to synchronization delay (2 cycles of card clock), after the fifo_reset is
+         *  cleared.
+         */
+        uint32_t fifo_reset:1;
+        /** dma_reset : R/W; bitpos: [2]; default: 0;
+         *  To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared
+         *  after two AHB clocks.
+         */
+        uint32_t dma_reset:1;
+        uint32_t reserved_3:1;
+        /** int_enable : R/W; bitpos: [4]; default: 0;
+         *  Global interrupt enable/disable bit. 0: Disable; 1: Enable.
+         */
+        uint32_t int_enable:1;
+        uint32_t reserved_5:1;
+        /** read_wait : R/W; bitpos: [6]; default: 0;
+         *  For sending read-wait to SDIO cards.
+         */
+        uint32_t read_wait:1;
+        /** send_irq_response : R/W; bitpos: [7]; default: 0;
+         *  Bit automatically clears once response is sent. To wait for MMC card interrupts,
+         *  host issues CMD40 and waits for interrupt response from MMC card(s). In the
+         *  meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this
+         *  bit, at which time SD/MMC command state-machine sends CMD40 response on bus and
+         *  returns to idle state.
+         */
+        uint32_t send_irq_response:1;
+        /** abort_read_data : R/W; bitpos: [8]; default: 0;
+         *  After a suspend-command is issued during a read-operation, software polls the card
+         *  to find when the suspend-event occurred. Once the suspend-event has occurred,
+         *  software sets the bit which will reset the data state machine that is waiting for
+         *  the next block of data. This bit is automatically cleared once the data state
+         *  machine is reset to idle.
+         */
+        uint32_t abort_read_data:1;
+        /** send_ccsd : R/W; bitpos: [9]; default: 0;
+         *  When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if
+         *  the current command is expecting CCS (that is, RW_BLK), and if interrupts are
+         *  enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC
+         *  automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD)
+         *  bit  in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host,
+         *  in case the Command Done interrupt is not masked.
+         *  NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive
+         *  the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may
+         *  be sent to the CE-ATA device, even if the device has signalled CCS.
+         */
+        uint32_t send_ccsd:1;
+        /** send_auto_stop_ccsd : R/W; bitpos: [10]; default: 0;
+         *  Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together;
+         *  SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set,
+         *  SD/MMC automatically sends an internally-generated STOP command (CMD12) to the
+         *  CE-ATA device. After sending this internally-generated STOP command, the Auto
+         *  Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated
+         *  for the host, in case the ACD interrupt is not masked. After sending the Command
+         *  Completion Signal Disable (CCSD), SD/MMC automatically clears the
+         *  SDHOST_SEND_AUTO_STOP_CCSD bit.
+         */
+        uint32_t send_auto_stop_ccsd:1;
+        /** ceata_device_interrupt_status : R/W; bitpos: [11]; default: 0;
+         *  Software should appropriately write to this bit after the power-on reset or any
+         *  other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is
+         *  usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt,
+         *  then software should set this bit.
+         */
+        uint32_t ceata_device_interrupt_status:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} sdhost_ctrl_reg_t;
+
+
+/** Group: Clock divider configuration register */
+/** Type of clkdiv register
+ *  Clock divider configuration register
+ */
+typedef union {
+    struct {
+        /** clk_divider0 : R/W; bitpos: [7:0]; default: 0;
+         *  Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+         *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+         *  means divided by 2*255 = 510, and so on.
+         */
+        uint32_t clk_divider0:8;
+        /** clk_divider1 : R/W; bitpos: [15:8]; default: 0;
+         *  Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+         *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+         *  means divided by 2*255 = 510, and so on.
+         */
+        uint32_t clk_divider1:8;
+        /** clk_divider2 : R/W; bitpos: [23:16]; default: 0;
+         *  Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+         *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+         *  means divided by 2*255 = 510, and so on.
+         */
+        uint32_t clk_divider2:8;
+        /** clk_divider3 : R/W; bitpos: [31:24]; default: 0;
+         *  Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+         *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+         *  means divided by 2*255 = 510, and so on.
+         */
+        uint32_t clk_divider3:8;
+    };
+    uint32_t val;
+} sdhost_clkdiv_reg_t;
+
+
+/** Group: Clock source selection register */
+/** Type of clksrc register
+ *  Clock source selection register
+ */
+typedef union {
+    struct {
+        /** clksrc_reg : R/W; bitpos: [3:0]; default: 0;
+         *  Clock divider source for two SD cards is supported. Each card has two bits assigned
+         *  to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for
+         *  card 1. Card 0 maps and internally routes clock divider[0:3] outputs to
+         *  cclk_out[1:0] pins, depending on bit value.
+         *  00 : Clock divider 0;
+         *  01 : Clock divider 1;
+         *  10 : Clock divider 2;
+         *  11 : Clock divider 3.
+         */
+        uint32_t clksrc_reg:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} sdhost_clksrc_reg_t;
+
+
+/** Group: Clock enable register */
+/** Type of clkena register
+ *  Clock enable register
+ */
+typedef union {
+    struct {
+        /** cclk_enable : R/W; bitpos: [1:0]; default: 0;
+         *  Clock-enable control for two SD card clocks and one MMC card clock is supported.
+         *  One bit per card.
+         *  0: Clock disabled;
+         *  1: Clock enabled.
+         */
+        uint32_t cclk_enable:2;
+        uint32_t reserved_2:14;
+        /** lp_enable : R/W; bitpos: [17:16]; default: 0;
+         *  Disable clock when the card is in IDLE state. One bit per card.
+         *  0: clock disabled;
+         *  1: clock enabled.
+         */
+        uint32_t lp_enable:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_clkena_reg_t;
+
+
+/** Group: Data and response timeout configuration register */
+/** Type of tmout register
+ *  Data and response timeout configuration register
+ */
+typedef union {
+    struct {
+        /** response_timeout : R/W; bitpos: [7:0]; default: 64;
+         *  Response timeout value. Value is specified in terms of number of card output
+         *  clocks, i.e., sdhost_cclk_out.
+         */
+        uint32_t response_timeout:8;
+        /** data_timeout : R/W; bitpos: [31:8]; default: 16777215;
+         *  Value for card data read timeout. This value is also used for data starvation by
+         *  host timeout. The timeout counter is started only after the card clock is stopped.
+         *  This value is specified in number of card output clocks, i.e. sdhost_cclk_out of
+         *  the selected card.
+         *  NOTE: The software timer should be used if the timeout value is in the order of 100
+         *  ms. In this case, read data timeout interrupt needs to be disabled.
+         */
+        uint32_t data_timeout:24;
+    };
+    uint32_t val;
+} sdhost_tmout_reg_t;
+
+
+/** Group: Card bus width configuration register */
+/** Type of ctype register
+ *  Card bus width configuration register
+ */
+typedef union {
+    struct {
+        /** card_width4 : R/W; bitpos: [1:0]; default: 0;
+         *  One bit per card indicates if card is 1-bit or 4-bit mode.
+         *  0: 1-bit mode;
+         *  1: 4-bit mode.
+         *  Bit[1:0] correspond to card[1:0] respectively.
+         */
+        uint32_t card_width4:2;
+        uint32_t reserved_2:14;
+        /** card_width8 : R/W; bitpos: [17:16]; default: 0;
+         *  One bit per card indicates if card is in 8-bit mode.
+         *  0: Non 8-bit mode;
+         *  1: 8-bit mode.
+         *  Bit[17:16] correspond to card[1:0] respectively.
+         */
+        uint32_t card_width8:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_ctype_reg_t;
+
+
+/** Group: Card data block size configuration register */
+/** Type of blksiz register
+ *  Card data block size configuration register
+ */
+typedef union {
+    struct {
+        /** block_size : R/W; bitpos: [15:0]; default: 512;
+         *  Block size.
+         */
+        uint32_t block_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} sdhost_blksiz_reg_t;
+
+
+/** Group: Data transfer length configuration register */
+/** Type of bytcnt register
+ *  Data transfer length configuration register
+ */
+typedef union {
+    struct {
+        /** byte_count : R/W; bitpos: [31:0]; default: 512;
+         *  Number of bytes to be transferred, should be an integral multiple of Block Size for
+         *  block transfers. For data transfers of undefined byte lengths, byte count should be
+         *  set to 0. When byte count is set to 0, it is the responsibility of host to
+         *  explicitly send stop/abort command to terminate data transfer.
+         */
+        uint32_t byte_count:32;
+    };
+    uint32_t val;
+} sdhost_bytcnt_reg_t;
+
+
+/** Group: SDIO interrupt mask register */
+/** Type of intmask register
+ *  SDIO interrupt mask register
+ */
+typedef union {
+    struct {
+        /** int_mask : R/W; bitpos: [15:0]; default: 0;
+         *  These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a
+         *  value of 1 enables the interrupt.
+         *  Bit 15 (EBE): End-bit error/no CRC error;
+         *  Bit 14 (ACD): Auto command done;
+         *  Bit 13 (SBE/BCI): Rx Start Bit Error;
+         *  Bit 12 (HLE): Hardware locked write error;
+         *  Bit 11 (FRUN): FIFO underrun/overrun error;
+         *  Bit 10 (HTO): Data starvation-by-host timeout;
+         *  Bit 9 (DRTO): Data read timeout;
+         *  Bit 8 (RTO): Response timeout;
+         *  Bit 7 (DCRC): Data CRC error;
+         *  Bit 6 (RCRC): Response CRC error;
+         *  Bit 5 (RXDR): Receive FIFO data request;
+         *  Bit 4 (TXDR): Transmit FIFO data request;
+         *  Bit 3 (DTO): Data transfer over;
+         *  Bit 2 (CD): Command done;
+         *  Bit 1 (RE): Response error;
+         *  Bit 0 (CD): Card detect.
+         */
+        uint32_t int_mask:16;
+        /** sdio_int_mask : R/W; bitpos: [17:16]; default: 0;
+         *  SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0]
+         *  respectively. When masked, SDIO interrupt detection for that card is disabled. 0
+         *  masks an interrupt, and 1 enables an interrupt.
+         */
+        uint32_t sdio_int_mask:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_intmask_reg_t;
+
+
+/** Group: Command argument data register */
+/** Type of cmdarg register
+ *  Command argument data register
+ */
+typedef union {
+    struct {
+        /** cmdarg_reg : R/W; bitpos: [31:0]; default: 0;
+         *  Value indicates command argument to be passed to the card.
+         */
+        uint32_t cmdarg_reg:32;
+    };
+    uint32_t val;
+} sdhost_cmdarg_reg_t;
+
+
+/** Group: Command and boot configuration register */
+/** Type of cmd register
+ *  Command and boot configuration register
+ */
+typedef union {
+    struct {
+        /** cmd_index : R/W; bitpos: [5:0]; default: 0;
+         *  Command index.
+         */
+        uint32_t cmd_index:6;
+        /** response_expect : R/W; bitpos: [6]; default: 0;
+         *  0: No response expected from card; 1: Response expected from card.
+         */
+        uint32_t response_expect:1;
+        /** response_length : R/W; bitpos: [7]; default: 0;
+         *  0: Short response expected from card; 1: Long response expected from card.
+         */
+        uint32_t response_length:1;
+        /** check_response_crc : R/W; bitpos: [8]; default: 0;
+         *  0: Do not check; 1: Check response CRC.
+         *  Some of command responses do not return valid CRC bits. Software should disable CRC
+         *  checks for those commands in order to disable CRC checking by controller.
+         */
+        uint32_t check_response_crc:1;
+        /** data_expected : R/W; bitpos: [9]; default: 0;
+         *  0: No data transfer expected; 1: Data transfer expected.
+         */
+        uint32_t data_expected:1;
+        /** read_write : R/W; bitpos: [10]; default: 0;
+         *  0: Read from card; 1: Write to card.
+         *  Don't care if no data is expected from card.
+         */
+        uint32_t read_write:1;
+        /** transfer_mode : R/W; bitpos: [11]; default: 0;
+         *  0: Block data transfer command; 1: Stream data transfer command.
+         *  Don't care if no data expected.
+         */
+        uint32_t transfer_mode:1;
+        /** send_auto_stop : R/W; bitpos: [12]; default: 0;
+         *  0: No stop command is sent at the end of data transfer; 1: Send stop command at the
+         *  end of data transfer.
+         */
+        uint32_t send_auto_stop:1;
+        /** wait_prvdata_complete : R/W; bitpos: [13]; default: 0;
+         *  0: Send command at once, even if previous data transfer has not completed; 1: Wait
+         *  for previous data transfer to complete before sending Command.
+         *  The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of
+         *  card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr
+         *  should be same as in previous command.
+         */
+        uint32_t wait_prvdata_complete:1;
+        /** stop_abort_cmd : R/W; bitpos: [14]; default: 0;
+         *  0: Neither stop nor abort command can stop current data transfer. If abort is sent
+         *  to function-number currently selected or not in data-transfer mode, then bit should
+         *  be set to 0; 1: Stop or abort command intended to stop current data transfer in
+         *  progress.
+         *  When open-ended or predefined data transfer is in progress, and host issues stop or
+         *  abort command to stop data transfer, bit should be set so that command/data
+         *  state-machines of CIU can return correctly to idle state.
+         */
+        uint32_t stop_abort_cmd:1;
+        /** send_initialization : R/W; bitpos: [15]; default: 0;
+         *  0: Do not send initialization sequence (80 clocks of 1) before sending this
+         *  command; 1: Send initialization sequence before sending this command.
+         *  After powered on, 80 clocks must be sent to card for initialization before sending
+         *  any commands to card. Bit should be set while sending first command to card so that
+         *  controller will initialize clocks before sending command to card.
+         */
+        uint32_t send_initialization:1;
+        /** card_number : R/W; bitpos: [20:16]; default: 0;
+         *  Card number in use. Represents physical slot number of card being accessed. In
+         *  SD-only mode, up to two cards are supported.
+         */
+        uint32_t card_number:5;
+        /** update_clock_registers_only : R/W; bitpos: [21]; default: 0;
+         *  0: Normal command sequence; 1: Do not send commands, just update clock register
+         *  value into card clock domain.
+         *  Following register values are transferred into card clock domain: CLKDIV, CLRSRC,
+         *  and CLKENA.
+         *  Changes card clocks (change frequency, truncate off or on, and set low-frequency
+         *  mode). This is provided in order to change clock frequency or stop clock without
+         *  having to send command to cards. During normal command sequence, when
+         *  sdhost_update_clock_registers_only = 0, following control registers are transferred
+         *  from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new
+         *  register values for new command sequence to card(s). When bit is set, there are no
+         *  Command Done interrupts because no command is sent to SD_MMC_CEATA cards.
+         */
+        uint32_t update_clock_registers_only:1;
+        /** read_ceata_device : R/W; bitpos: [22]; default: 0;
+         *  Read access flag.
+         *  0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;
+         *  1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.
+         *  Software should set this bit to indicate that CE-ATA device is being accessed for
+         *  read transfer. This bit is used to disable read data timeout indication while
+         *  performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no
+         *  less than 10 seconds. SD/MMC should not indicate read data timeout while waiting
+         *  for data from CE-ATA device.
+         */
+        uint32_t read_ceata_device:1;
+        /** ccs_expected : R/W; bitpos: [23]; default: 0;
+         *  Expected Command Completion Signal (CCS) configuration.
+         *  0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register),
+         *  or command does not expect CCS from device;
+         *  1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects
+         *  command completion signal from CE-ATA device.
+         *  If the command expects Command Completion Signal (CCS) from the CE-ATA device, the
+         *  software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in
+         *  RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is
+         *  not masked.
+         */
+        uint32_t ccs_expected:1;
+        uint32_t reserved_24:5;
+        /** use_hole_reg : R/W; bitpos: [29]; default: 1;
+         *  Use Hold Register.
+         *  0: CMD and DATA sent to card bypassing HOLD Register;
+         *  1: CMD and DATA sent to card through the HOLD Register.
+         */
+        uint32_t use_hole_reg:1;
+        uint32_t reserved_30:1;
+        /** start_cmd : R/W; bitpos: [31]; default: 0;
+         *  Start command. Once command is served by the CIU, this bit is automatically
+         *  cleared. When this bit is set, host should not attempt to write to any command
+         *  registers. If a write is attempted, hardware lock error is set in raw interrupt
+         *  register. Once command is sent and a response is received from SD_MMC_CEATA cards,
+         *  Command Done bit is set in the raw interrupt Register.
+         */
+        uint32_t start_cmd:1;
+    };
+    uint32_t val;
+} sdhost_cmd_reg_t;
+
+
+/** Group: Response data register */
+/** Type of resp0 register
+ *  Response data register
+ */
+typedef union {
+    struct {
+        /** response0_reg : RO; bitpos: [31:0]; default: 0;
+         *  Bit[31:0] of response.
+         */
+        uint32_t response0_reg:32;
+    };
+    uint32_t val;
+} sdhost_resp0_reg_t;
+
+
+/** Group: Long response data register */
+/** Type of resp1 register
+ *  Long response data register
+ */
+typedef union {
+    struct {
+        /** response1_reg : RO; bitpos: [31:0]; default: 0;
+         *  Bit[63:32] of long response.
+         */
+        uint32_t response1_reg:32;
+    };
+    uint32_t val;
+} sdhost_resp1_reg_t;
+
+/** Type of resp2 register
+ *  Long response data register
+ */
+typedef union {
+    struct {
+        /** response2_reg : RO; bitpos: [31:0]; default: 0;
+         *  Bit[95:64] of long response.
+         */
+        uint32_t response2_reg:32;
+    };
+    uint32_t val;
+} sdhost_resp2_reg_t;
+
+/** Type of resp3 register
+ *  Long response data register
+ */
+typedef union {
+    struct {
+        /** response3_reg : RO; bitpos: [31:0]; default: 0;
+         *  Bit[127:96] of long response.
+         */
+        uint32_t response3_reg:32;
+    };
+    uint32_t val;
+} sdhost_resp3_reg_t;
+
+
+/** Group: Masked interrupt status register */
+/** Type of mintsts register
+ *  Masked interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_status_msk : RO; bitpos: [15:0]; default: 0;
+         *  Interrupt enabled only if corresponding bit in interrupt mask register is set.
+         *  Bit 15 (EBE): End-bit error/no CRC error;
+         *  Bit 14 (ACD): Auto command done;
+         *  Bit 13 (SBE/BCI): RX Start Bit Error;
+         *  Bit 12 (HLE): Hardware locked write error;
+         *  Bit 11 (FRUN): FIFO underrun/overrun error;
+         *  Bit 10 (HTO): Data starvation by host timeout (HTO);
+         *  Bit 9 (DTRO): Data read timeout;
+         *  Bit 8 (RTO): Response timeout;
+         *  Bit 7 (DCRC): Data CRC error;
+         *  Bit 6 (RCRC): Response CRC error;
+         *  Bit 5 (RXDR): Receive FIFO data request;
+         *  Bit 4 (TXDR): Transmit FIFO data request;
+         *  Bit 3 (DTO): Data transfer over;
+         *  Bit 2 (CD): Command done;
+         *  Bit 1 (RE): Response error;
+         *  Bit 0 (CD): Card detect.
+         */
+        uint32_t int_status_msk:16;
+        /** sdio_interrupt_msk : RO; bitpos: [17:16]; default: 0;
+         *  Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
+         *  card0, respectively. SDIO interrupt for card is enabled only if corresponding
+         *  sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit
+         *  enables interrupt).
+         */
+        uint32_t sdio_interrupt_msk:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_mintsts_reg_t;
+
+
+/** Group: Raw interrupt status register */
+/** Type of rintsts register
+ *  Raw interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_status_raw : R/W; bitpos: [15:0]; default: 0;
+         *  Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits
+         *  are logged regardless of interrupt mask status.
+         *  Bit 15 (EBE): End-bit error/no CRC error;
+         *  Bit 14 (ACD): Auto command done;
+         *  Bit 13 (SBE/BCI): RX Start Bit Error;
+         *  Bit 12 (HLE): Hardware locked write error;
+         *  Bit 11 (FRUN): FIFO underrun/overrun error;
+         *  Bit 10 (HTO): Data starvation by host timeout (HTO);
+         *  Bit 9 (DTRO): Data read timeout;
+         *  Bit 8 (RTO): Response timeout;
+         *  Bit 7 (DCRC): Data CRC error;
+         *  Bit 6 (RCRC): Response CRC error;
+         *  Bit 5 (RXDR): Receive FIFO data request;
+         *  Bit 4 (TXDR): Transmit FIFO data request;
+         *  Bit 3 (DTO): Data transfer over;
+         *  Bit 2 (CD): Command done;
+         *  Bit 1 (RE): Response error;
+         *  Bit 0 (CD): Card detect.
+         */
+        uint32_t int_status_raw:16;
+        /** sdio_interrupt_raw : R/W; bitpos: [17:16]; default: 0;
+         *  Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
+         *  card0, respectively. Setting a bit clears the corresponding interrupt bit and
+         *  writing 0 has no effect.
+         *  0: No SDIO interrupt from card;
+         *  1: SDIO interrupt from card.
+         */
+        uint32_t sdio_interrupt_raw:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_rintsts_reg_t;
+
+
+/** Group: SD/MMC status register */
+/** Type of status register
+ *  SD/MMC status register
+ */
+typedef union {
+    struct {
+        /** fifo_rx_watermark : RO; bitpos: [0]; default: 0;
+         *  FIFO reached Receive watermark level, not qualified with data transfer.
+         */
+        uint32_t fifo_rx_watermark:1;
+        /** fifo_tx_watermark : RO; bitpos: [1]; default: 1;
+         *  FIFO reached Transmit watermark level, not qualified with data transfer.
+         */
+        uint32_t fifo_tx_watermark:1;
+        /** fifo_empty : RO; bitpos: [2]; default: 1;
+         *  FIFO is empty status.
+         */
+        uint32_t fifo_empty:1;
+        /** fifo_full : RO; bitpos: [3]; default: 0;
+         *  FIFO is full status.
+         */
+        uint32_t fifo_full:1;
+        /** command_fsm_states : RO; bitpos: [7:4]; default: 1;
+         *  Command FSM states.
+         *  0: Idle;
+         *  1: Send init sequence;
+         *  2: Send cmd start bit;
+         *  3: Send cmd tx bit;
+         *  4: Send cmd index + arg;
+         *  5: Send cmd crc7;
+         *  6: Send cmd end bit;
+         *  7: Receive resp start bit;
+         *  8: Receive resp IRQ response;
+         *  9: Receive resp tx bit;
+         *  10: Receive resp cmd idx;
+         *  11: Receive resp data;
+         *  12: Receive resp crc7;
+         *  13: Receive resp end bit;
+         *  14: Cmd path wait NCC;
+         *  15: Wait, cmd-to-response turnaround.
+         */
+        uint32_t command_fsm_states:4;
+        /** data_3_status : RO; bitpos: [8]; default: 1;
+         *  Raw selected sdhost_card_data[3], checks whether card is present.
+         *  0: card not present;
+         *  1: card present.
+         */
+        uint32_t data_3_status:1;
+        /** data_busy : RO; bitpos: [9]; default: 1;
+         *  Inverted version of raw selected sdhost_card_data[0].
+         *  0: Card data not busy;
+         *  1: Card data busy.
+         */
+        uint32_t data_busy:1;
+        /** data_state_mc_busy : RO; bitpos: [10]; default: 1;
+         *  Data transmit or receive state-machine is busy.
+         */
+        uint32_t data_state_mc_busy:1;
+        /** response_index : RO; bitpos: [16:11]; default: 0;
+         *  Index of previous response, including any auto-stop sent by core.
+         */
+        uint32_t response_index:6;
+        /** fifo_count : RO; bitpos: [29:17]; default: 0;
+         *  FIFO count, number of filled locations in FIFO.
+         */
+        uint32_t fifo_count:13;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sdhost_status_reg_t;
+
+
+/** Group: FIFO configuration register */
+/** Type of fifoth register
+ *  FIFO configuration register
+ */
+typedef union {
+    struct {
+        /** tx_wmark : R/W; bitpos: [11:0]; default: 0;
+         *  FIFO threshold watermark level when transmitting data to card. When FIFO data count
+         *  is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is
+         *  enabled, then interrupt  occurs. During end of packet, request or interrupt is
+         *  generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO
+         *  threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA
+         *  request. During end of packet, on last interrupt, host is responsible for filling
+         *  FIFO with only required remaining bytes (not before FIFO is full or after CIU
+         *  completes data transfers, because FIFO may not be empty).  In DMA mode, at end of
+         *  packet, if last transfer is less than burst  size, DMA controller does single
+         *  cycles until required bytes are  transferred.
+         */
+        uint32_t tx_wmark:12;
+        uint32_t reserved_12:4;
+        /** rx_wmark : R/W; bitpos: [26:16]; default: 0;
+         *  FIFO threshold watermark level when receiving data to card.When FIFO data count
+         *  reaches greater than this number , DMA/FIFO request is raised. During end of
+         *  packet, request is generated regardless of threshold programming in order to
+         *  complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR)
+         *  interrupt is enabled, then interrupt is generated instead of DMA request.During end
+         *  of packet, interrupt is not generated if threshold programming is larger than any
+         *  remaining data. It is responsibility of host to read remaining bytes on seeing Data
+         *  Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are
+         *  less than threshold, DMA request does single transfers to flush out any remaining
+         *  bytes before Data Transfer Done interrupt is set.
+         */
+        uint32_t rx_wmark:11;
+        uint32_t reserved_27:1;
+        /** dma_multiple_transaction_size : R/W; bitpos: [30:28]; default: 0;
+         *  Burst size of multiple transaction, should be programmed same as DMA controller
+         *  multiple-transaction-size SDHOST_SRC/DEST_MSIZE.
+         *  000: 1-byte transfer;
+         *  001: 4-byte transfer;
+         *  010: 8-byte transfer;
+         *  011: 16-byte transfer;
+         *  100: 32-byte transfer;
+         *  101: 64-byte transfer;
+         *  110: 128-byte transfer;
+         *  111: 256-byte transfer.
+         */
+        uint32_t dma_multiple_transaction_size:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} sdhost_fifoth_reg_t;
+
+
+/** Group: Card detect register */
+/** Type of cdetect register
+ *  Card detect register
+ */
+typedef union {
+    struct {
+        /** card_detect_n : RO; bitpos: [1:0]; default: 0;
+         *  Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0
+         *  represents presence of card. Only NUM_CARDS number of bits are implemented.
+         */
+        uint32_t card_detect_n:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sdhost_cdetect_reg_t;
+
+
+/** Group: Card write protection (WP) status register */
+/** Type of wrtprt register
+ *  Card write protection (WP) status register
+ */
+typedef union {
+    struct {
+        /** write_protect : RO; bitpos: [1:0]; default: 0;
+         *  Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write
+         *  protection. Only NUM_CARDS number of bits are implemented.
+         */
+        uint32_t write_protect:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sdhost_wrtprt_reg_t;
+
+
+/** Group: Transferred byte count register */
+/** Type of tcbcnt register
+ *  Transferred byte count register
+ */
+typedef union {
+    struct {
+        /** tcbcnt_reg : RO; bitpos: [31:0]; default: 0;
+         *  Number of bytes transferred by CIU unit to card.
+         */
+        uint32_t tcbcnt_reg:32;
+    };
+    uint32_t val;
+} sdhost_tcbcnt_reg_t;
+
+/** Type of tbbcnt register
+ *  Transferred byte count register
+ */
+typedef union {
+    struct {
+        /** tbbcnt_reg : RO; bitpos: [31:0]; default: 0;
+         *  Number of bytes transferred between Host/DMA memory and BIU FIFO.
+         */
+        uint32_t tbbcnt_reg:32;
+    };
+    uint32_t val;
+} sdhost_tbbcnt_reg_t;
+
+
+/** Group: Debounce filter time configuration register */
+/** Type of debnce register
+ *  Debounce filter time configuration register
+ */
+typedef union {
+    struct {
+        /** debounce_count : R/W; bitpos: [23:0]; default: 0;
+         *  Number of host clocks (clk) used by debounce filter logic. The typical debounce
+         *  time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted
+         *  or removed.
+         */
+        uint32_t debounce_count:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} sdhost_debnce_reg_t;
+
+
+/** Group: User ID (scratchpad) register */
+/** Type of usrid register
+ *  User ID (scratchpad) register
+ */
+typedef union {
+    struct {
+        /** usrid_reg : R/W; bitpos: [31:0]; default: 0;
+         *  User identification register, value set by user. Can also be used as a scratchpad
+         *  register by user.
+         */
+        uint32_t usrid_reg:32;
+    };
+    uint32_t val;
+} sdhost_usrid_reg_t;
+
+
+/** Group: Version ID (scratchpad) register */
+/** Type of verid register
+ *  Version ID (scratchpad) register
+ */
+typedef union {
+    struct {
+        /** versionid_reg : RO; bitpos: [31:0]; default: 1412572938;
+         *  Hardware version register. Can also be read by fireware.
+         */
+        uint32_t versionid_reg:32;
+    };
+    uint32_t val;
+} sdhost_verid_reg_t;
+
+
+/** Group: Hardware feature register */
+/** Type of hcon register
+ *  Hardware feature register
+ */
+typedef union {
+    struct {
+        /** card_type_reg : RO; bitpos: [0]; default: 1;
+         *  Hardware support SDIO and MMC.
+         */
+        uint32_t card_type_reg:1;
+        /** card_num_reg : RO; bitpos: [5:1]; default: 1;
+         *  Support card number is 2.
+         */
+        uint32_t card_num_reg:5;
+        /** bus_type_reg : RO; bitpos: [6]; default: 1;
+         *  Register config is APB bus.
+         */
+        uint32_t bus_type_reg:1;
+        /** data_width_reg : RO; bitpos: [9:7]; default: 1;
+         *  Regisger data width is 32.
+         */
+        uint32_t data_width_reg:3;
+        /** addr_width_reg : RO; bitpos: [15:10]; default: 19;
+         *  Register address width is 32.
+         */
+        uint32_t addr_width_reg:6;
+        uint32_t reserved_16:2;
+        /** dma_width_reg : RO; bitpos: [20:18]; default: 1;
+         *  DMA data width is 32.
+         */
+        uint32_t dma_width_reg:3;
+        /** ram_indise_reg : RO; bitpos: [21]; default: 0;
+         *  Inside RAM in SDMMC module.
+         */
+        uint32_t ram_indise_reg:1;
+        /** hold_reg : RO; bitpos: [22]; default: 1;
+         *  Have a hold register in data path .
+         */
+        uint32_t hold_reg:1;
+        uint32_t reserved_23:1;
+        /** num_clk_div_reg : RO; bitpos: [25:24]; default: 3;
+         *  Have 4 clk divider in design .
+         */
+        uint32_t num_clk_div_reg:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} sdhost_hcon_reg_t;
+
+
+/** Group: UHS-1 register */
+/** Type of uhs register
+ *  UHS-1 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** ddr_reg : R/W; bitpos: [17:16]; default: 0;
+         *  DDR mode selection,1 bit for each card.
+         *  0-Non-DDR mode.
+         *  1-DDR mode.
+         */
+        uint32_t ddr_reg:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_uhs_reg_t;
+
+
+/** Group: Card reset register */
+/** Type of rst_n register
+ *  Card reset register
+ */
+typedef union {
+    struct {
+        /** card_reset : R/W; bitpos: [1:0]; default: 1;
+         *  Hardware reset.
+         *  1: Active mode;
+         *  0: Reset.
+         *  These bits cause the cards to enter pre-idle state, which requires them to be
+         *  re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0,
+         *  SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1.
+         */
+        uint32_t card_reset:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sdhost_rst_n_reg_t;
+
+
+/** Group: Burst mode transfer configuration register */
+/** Type of bmod register
+ *  Burst mode transfer configuration register
+ */
+typedef union {
+    struct {
+        /** bmod_swr : R/W; bitpos: [0]; default: 0;
+         *  Software Reset. When set, the DMA Controller resets all its internal registers. It
+         *  is automatically cleared after one clock cycle.
+         */
+        uint32_t bmod_swr:1;
+        /** bmod_fb : R/W; bitpos: [1]; default: 0;
+         *  Fixed Burst. Controls whether the AHB Master interface performs fixed burst
+         *  transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16
+         *  during start of normal burst transfers. When reset, the AHB will use SINGLE and
+         *  INCR burst transfer operations.
+         */
+        uint32_t bmod_fb:1;
+        uint32_t reserved_2:5;
+        /** bmod_de : R/W; bitpos: [7]; default: 0;
+         *  IDMAC Enable. When set, the IDMAC is enabled.
+         */
+        uint32_t bmod_de:1;
+        /** bmod_pbl : R/W; bitpos: [10:8]; default: 0;
+         *  Programmable Burst Length. These bits indicate the maximum number of beats to be
+         *  performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always
+         *  attempt to burst as specified in PBL each time it starts a burst transfer on the
+         *  host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value
+         *  is the mirror of MSIZE of FIFOTH register. In order to change this value, write the
+         *  required value to FIFOTH register. This is an encode value as follows:
+         *  000: 1-byte transfer;
+         *  001: 4-byte transfer;
+         *  010: 8-byte transfer;
+         *  011: 16-byte transfer;
+         *  100: 32-byte transfer;
+         *  101: 64-byte transfer;
+         *  110: 128-byte transfer;
+         *  111: 256-byte transfer.
+         *  PBL is a read-only value and is applicable only for data access, it does not apply
+         *  to descriptor access.
+         */
+        uint32_t bmod_pbl:3;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} sdhost_bmod_reg_t;
+
+
+/** Group: Poll demand configuration register */
+/** Type of pldmnd register
+ *  Poll demand configuration register
+ */
+typedef union {
+    struct {
+        /** pldmnd_pd : WO; bitpos: [31:0]; default: 0;
+         *  Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the
+         *  Suspend state. The host needs to write any value into this register for the IDMAC
+         *  FSM to resume normal descriptor fetch operation. This is a write only .
+         */
+        uint32_t pldmnd_pd:32;
+    };
+    uint32_t val;
+} sdhost_pldmnd_reg_t;
+
+
+/** Group: Descriptor base address register */
+/** Type of dbaddr register
+ *  Descriptor base address register
+ */
+typedef union {
+    struct {
+        /** dbaddr_reg : R/W; bitpos: [31:0]; default: 0;
+         *  Start of Descriptor List. Contains the base address of the First Descriptor. The
+         *  LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence
+         *  these LSB bits may be treated as read-only.
+         */
+        uint32_t dbaddr_reg:32;
+    };
+    uint32_t val;
+} sdhost_dbaddr_reg_t;
+
+
+/** Group: IDMAC status register */
+/** Type of idsts register
+ *  IDMAC status register
+ */
+typedef union {
+    struct {
+        /** idsts_ti : R/W; bitpos: [0]; default: 0;
+         *  Transmit Interrupt. Indicates that data transmission is finished for a descriptor.
+         *  Writing 1 clears this bit.
+         */
+        uint32_t idsts_ti:1;
+        /** idsts_ri : R/W; bitpos: [1]; default: 0;
+         *  Receive Interrupt. Indicates the completion of data reception for a descriptor.
+         *  Writing 1 clears this bit.
+         */
+        uint32_t idsts_ri:1;
+        /** idsts_fbe : R/W; bitpos: [2]; default: 0;
+         *  Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) .
+         *  When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this
+         *  bit.
+         */
+        uint32_t idsts_fbe:1;
+        uint32_t reserved_3:1;
+        /** idsts_du : R/W; bitpos: [4]; default: 0;
+         *  Descriptor Unavailable Interrupt. This bit is set when the descriptor is
+         *  unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit.
+         */
+        uint32_t idsts_du:1;
+        /** idsts_ces : R/W; bitpos: [5]; default: 0;
+         *  Card Error Summary. Indicates the status of the transaction to/from the card, also
+         *  present in RINTSTS. Indicates the logical OR of the following bits:
+         *  EBE : End Bit Error;
+         *  RTO : Response Timeout/Boot Ack Timeout;
+         *  RCRC : Response CRC;
+         *  SBE : Start Bit Error;
+         *  DRTO : Data Read Timeout/BDS timeout;
+         *  DCRC : Data CRC for Receive;
+         *  RE : Response Error.
+         *  Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting
+         *  of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response
+         *  error.
+         */
+        uint32_t idsts_ces:1;
+        uint32_t reserved_6:2;
+        /** idsts_nis : R/W; bitpos: [8]; default: 0;
+         *  Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit
+         *  Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This
+         *  is a sticky bit and must be cleared each time a corresponding bit that causes NIS
+         *  to be set is cleared. Writing 1 clears this bit.
+         */
+        uint32_t idsts_nis:1;
+        /** idsts_ais : R/W; bitpos: [9]; default: 0;
+         *  Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus
+         *  Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is
+         *  a sticky bit and must be cleared each time a corresponding bit that causes AIS to
+         *  be set is cleared. Writing 1 clears this bit.
+         */
+        uint32_t idsts_ais:1;
+        /** idsts_fbe_code : R/W; bitpos: [12:10]; default: 0;
+         *  Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid
+         *  only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an
+         *  interrupt.
+         *  001: Host Abort received during transmission;
+         *  010: Host Abort received during reception;
+         *  Others: Reserved.
+         */
+        uint32_t idsts_fbe_code:3;
+        /** idsts_fsm : R/W; bitpos: [16:13]; default: 0;
+         *  DMAC FSM present state.
+         *  0: DMA_IDLE (idle state);
+         *  1: DMA_SUSPEND (suspend state);
+         *  2: DESC_RD (descriptor reading state);
+         *  3: DESC_CHK (descriptor checking state);
+         *  4: DMA_RD_REQ_WAIT (read-data request waiting state);
+         *  5: DMA_WR_REQ_WAIT (write-data request waiting state);
+         *  6: DMA_RD (data-read state);
+         *  7: DMA_WR (data-write state);
+         *  8: DESC_CLOSE (descriptor close state).
+         */
+        uint32_t idsts_fsm:4;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} sdhost_idsts_reg_t;
+
+
+/** Group: IDMAC interrupt enable register */
+/** Type of idinten register
+ *  IDMAC interrupt enable register
+ */
+typedef union {
+    struct {
+        /** idinten_ti : R/W; bitpos: [0]; default: 0;
+         *  Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit
+         *  Interrupt is enabled. When reset, Transmit Interrupt is disabled.
+         */
+        uint32_t idinten_ti:1;
+        /** idinten_ri : R/W; bitpos: [1]; default: 0;
+         *  Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
+         *  Interrupt is enabled. When reset, Receive Interrupt is disabled.
+         */
+        uint32_t idinten_ri:1;
+        /** idinten_fbe : R/W; bitpos: [2]; default: 0;
+         *  Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal
+         *  Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is
+         *  disabled.
+         */
+        uint32_t idinten_fbe:1;
+        uint32_t reserved_3:1;
+        /** idinten_du : R/W; bitpos: [4]; default: 0;
+         *  Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
+         *  Enable, the DU interrupt is enabled.
+         */
+        uint32_t idinten_du:1;
+        /** idinten_ces : R/W; bitpos: [5]; default: 0;
+         *  Card Error summary Interrupt Enable. When set, it enables the Card Interrupt
+         *  summary.
+         */
+        uint32_t idinten_ces:1;
+        uint32_t reserved_6:2;
+        /** idinten_ni : R/W; bitpos: [8]; default: 0;
+         *  Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When
+         *  reset, a normal interrupt is disabled. This bit enables the following bits:
+         *  IDINTEN[0]: Transmit Interrupt;
+         *  IDINTEN[1]: Receive Interrupt.
+         */
+        uint32_t idinten_ni:1;
+        /** idinten_ai : R/W; bitpos: [9]; default: 0;
+         *  Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This
+         *  bit enables the following bits:
+         *  IDINTEN[2]: Fatal Bus Error Interrupt;
+         *  IDINTEN[4]: DU Interrupt.
+         */
+        uint32_t idinten_ai:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} sdhost_idinten_reg_t;
+
+
+/** Group: Host descriptor address pointer */
+/** Type of dscaddr register
+ *  Host descriptor address pointer
+ */
+typedef union {
+    struct {
+        /** dscaddr_reg : RO; bitpos: [31:0]; default: 0;
+         *  Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on
+         *  reset. This register points to the start address of the current descriptor read by
+         *  the IDMAC.
+         */
+        uint32_t dscaddr_reg:32;
+    };
+    uint32_t val;
+} sdhost_dscaddr_reg_t;
+
+
+/** Group: Host buffer address pointer register */
+/** Type of bufaddr register
+ *  Host buffer address pointer register
+ */
+typedef union {
+    struct {
+        /** bufaddr_reg : RO; bitpos: [31:0]; default: 0;
+         *  Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
+         *  reset. This register points to the current Data Buffer Address being accessed by
+         *  the IDMAC.
+         */
+        uint32_t bufaddr_reg:32;
+    };
+    uint32_t val;
+} sdhost_bufaddr_reg_t;
+
+
+/** Group: Card Threshold Control register */
+/** Type of cardthrctl register
+ *  Card Threshold Control register
+ */
+typedef union {
+    struct {
+        /** cardrdthren_reg : R/W; bitpos: [0]; default: 0;
+         *  Card read threshold enable.
+         *  1'b0-Card read threshold disabled.
+         *  1'b1-Card read threshold enabled.
+         */
+        uint32_t cardrdthren_reg:1;
+        /** cardclrinten_reg : R/W; bitpos: [1]; default: 0;
+         *  Busy clear interrupt generation:
+         *  1'b0-Busy clear interrypt disabled.
+         *  1'b1-Busy clear interrypt enabled.
+         */
+        uint32_t cardclrinten_reg:1;
+        /** cardwrthren_reg : R/W; bitpos: [2]; default: 0;
+         *  Applicable when HS400 mode is enabled.
+         *  1'b0-Card write Threshold disabled.
+         *  1'b1-Card write Threshold enabled.
+         */
+        uint32_t cardwrthren_reg:1;
+        uint32_t reserved_3:13;
+        /** cardthreshold_reg : R/W; bitpos: [31:16]; default: 0;
+         *  The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG
+         *  is set to 1 or SDHOST_CARDRDTHREN_REG set to 1.
+         */
+        uint32_t cardthreshold_reg:16;
+    };
+    uint32_t val;
+} sdhost_cardthrctl_reg_t;
+
+
+/** Group: eMMC DDR register */
+/** Type of emmcddr register
+ *  eMMC DDR register
+ */
+typedef union {
+    struct {
+        /** halfstartbit_reg : R/W; bitpos: [1:0]; default: 0;
+         *  Control for start bit detection mechanism duration of start bit.Each bit refers to
+         *  one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For
+         *  eMMC4.5,start bit can be:
+         *  1'b0-Full cycle.
+         *  1'b1-less than one full cycle.
+         */
+        uint32_t halfstartbit_reg:2;
+        uint32_t reserved_2:29;
+        /** hs400_mode_reg : R/W; bitpos: [31]; default: 0;
+         *  Set 1 to enable HS400 mode.
+         */
+        uint32_t hs400_mode_reg:1;
+    };
+    uint32_t val;
+} sdhost_emmcddr_reg_t;
+
+
+/** Group: Enable Phase Shift register */
+/** Type of enshift register
+ *  Enable Phase Shift register
+ */
+typedef union {
+    struct {
+        /** enable_shift_reg : R/W; bitpos: [3:0]; default: 0;
+         *  Control for the amount of phase shift provided on the default enables in the
+         *  design.Two bits assigned for each card.
+         *  2'b00-Default phase shift.
+         *  2'b01-Enables shifted to next immediate positive edge.
+         *  2'b10-Enables shifted to next immediate negative edge.
+         *  2'b11-Reserved.
+         */
+        uint32_t enable_shift_reg:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} sdhost_enshift_reg_t;
+
+
+/** Group: CPU write and read transmit data by FIFO */
+/** Type of buffifo register
+ *  CPU write and read transmit data by FIFO
+ */
+typedef union {
+    struct {
+        /** buffifo_reg : R/W; bitpos: [31:0]; default: 0;
+         *  CPU write and read transmit data by FIFO. This register points to the current Data
+         *  FIFO .
+         */
+        uint32_t buffifo_reg:32;
+    };
+    uint32_t val;
+} sdhost_buffifo_reg_t;
+
+
+/** Group: SDIO Control and configuration registers */
+/** Type of clk_edge_sel register
+ *  SDIO control register.
+ */
+typedef union {
+    struct {
+        /** cclkin_edge_drv_sel : R/W; bitpos: [2:0]; default: 0;
+         *  It's used to select the clock phase of the output signal from phase 0, phase 90,
+         *  phase 180, phase 270.
+         */
+        uint32_t cclkin_edge_drv_sel:3;
+        /** cclkin_edge_sam_sel : R/W; bitpos: [5:3]; default: 0;
+         *  It's used to select the clock phase of the input signal from phase 0, phase 90,
+         *  phase 180, phase 270.
+         */
+        uint32_t cclkin_edge_sam_sel:3;
+        /** cclkin_edge_slf_sel : R/W; bitpos: [8:6]; default: 0;
+         *  It's used to select the clock phase of the internal signal from phase 0, phase 90,
+         *  phase 180, phase 270.
+         */
+        uint32_t cclkin_edge_slf_sel:3;
+        /** ccllkin_edge_h : R/W; bitpos: [12:9]; default: 1;
+         *  The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L.
+         */
+        uint32_t ccllkin_edge_h:4;
+        /** ccllkin_edge_l : R/W; bitpos: [16:13]; default: 0;
+         *  The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H.
+         */
+        uint32_t ccllkin_edge_l:4;
+        /** ccllkin_edge_n : R/W; bitpos: [20:17]; default: 1;
+         *  The clock division of cclk_in.
+         */
+        uint32_t ccllkin_edge_n:4;
+        /** esdio_mode : R/W; bitpos: [21]; default: 0;
+         *  Enable esdio mode.
+         */
+        uint32_t esdio_mode:1;
+        /** esd_mode : R/W; bitpos: [22]; default: 0;
+         *  Enable esd mode.
+         */
+        uint32_t esd_mode:1;
+        /** cclk_en : R/W; bitpos: [23]; default: 1;
+         *  Sdio clock enable.
+         */
+        uint32_t cclk_en:1;
+        /** ultra_high_speed_mode : R/W; bitpos: [24]; default: 0;
+         *  Enable ultra high speed mode, use dll to generate clk.
+         */
+        uint32_t ultra_high_speed_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} sdhost_clk_edge_sel_reg_t;
+
+
+/** Group: SDIO raw ints registers */
+/** Type of raw_ints register
+ *  SDIO raw ints register.
+ */
+typedef union {
+    struct {
+        /** raw_ints : RO; bitpos: [31:0]; default: 0;
+         *  It indicates raw ints.
+         */
+        uint32_t raw_ints:32;
+    };
+    uint32_t val;
+} sdhost_raw_ints_reg_t;
+
+
+/** Group: SDIO dll clock control registers */
+/** Type of dll_clk_conf register
+ *  SDIO DLL clock control register.
+ */
+typedef union {
+    struct {
+        /** dll_cclk_in_slf_en : R/W; bitpos: [0]; default: 0;
+         *  Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_slf_en:1;
+        /** dll_cclk_in_drv_en : R/W; bitpos: [1]; default: 0;
+         *  Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_drv_en:1;
+        /** dll_cclk_in_sam_en : R/W; bitpos: [2]; default: 0;
+         *  Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_sam_en:1;
+        /** dll_cclk_in_slf_phase : R/W; bitpos: [8:3]; default: 0;
+         *  It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_slf_phase:6;
+        /** dll_cclk_in_drv_phase : R/W; bitpos: [14:9]; default: 0;
+         *  It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_drv_phase:6;
+        /** dll_cclk_in_sam_phase : R/W; bitpos: [20:15]; default: 0;
+         *  It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_sam_phase:6;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} sdhost_dll_clk_conf_reg_t;
+
+
+/** Group: SDIO dll configuration registers */
+/** Type of dll_conf register
+ *  SDIO DLL configuration register.
+ */
+typedef union {
+    struct {
+        /** dll_cal_stop : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to stop calibration.
+         */
+        uint32_t dll_cal_stop:1;
+        /** dll_cal_end : RO; bitpos: [1]; default: 0;
+         *  1 means calibration finished.
+         */
+        uint32_t dll_cal_end:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sdhost_dll_conf_reg_t;
+
+
+typedef struct {
+    volatile sdhost_ctrl_reg_t ctrl;
+    uint32_t reserved_004;
+    volatile sdhost_clkdiv_reg_t clkdiv;
+    volatile sdhost_clksrc_reg_t clksrc;
+    volatile sdhost_clkena_reg_t clkena;
+    volatile sdhost_tmout_reg_t tmout;
+    volatile sdhost_ctype_reg_t ctype;
+    volatile sdhost_blksiz_reg_t blksiz;
+    volatile sdhost_bytcnt_reg_t bytcnt;
+    volatile sdhost_intmask_reg_t intmask;
+    volatile sdhost_cmdarg_reg_t cmdarg;
+    volatile sdhost_cmd_reg_t cmd;
+    volatile sdhost_resp0_reg_t resp0;
+    volatile sdhost_resp1_reg_t resp1;
+    volatile sdhost_resp2_reg_t resp2;
+    volatile sdhost_resp3_reg_t resp3;
+    volatile sdhost_mintsts_reg_t mintsts;
+    volatile sdhost_rintsts_reg_t rintsts;
+    volatile sdhost_status_reg_t status;
+    volatile sdhost_fifoth_reg_t fifoth;
+    volatile sdhost_cdetect_reg_t cdetect;
+    volatile sdhost_wrtprt_reg_t wrtprt;
+    uint32_t reserved_058;
+    volatile sdhost_tcbcnt_reg_t tcbcnt;
+    volatile sdhost_tbbcnt_reg_t tbbcnt;
+    volatile sdhost_debnce_reg_t debnce;
+    volatile sdhost_usrid_reg_t usrid;
+    volatile sdhost_verid_reg_t verid;
+    volatile sdhost_hcon_reg_t hcon;
+    volatile sdhost_uhs_reg_t uhs;
+    volatile sdhost_rst_n_reg_t rst_n;
+    uint32_t reserved_07c;
+    volatile sdhost_bmod_reg_t bmod;
+    volatile sdhost_pldmnd_reg_t pldmnd;
+    volatile sdhost_dbaddr_reg_t dbaddr;
+    volatile sdhost_idsts_reg_t idsts;
+    volatile sdhost_idinten_reg_t idinten;
+    volatile sdhost_dscaddr_reg_t dscaddr;
+    volatile sdhost_bufaddr_reg_t bufaddr;
+    uint32_t reserved_09c[25];
+    volatile sdhost_cardthrctl_reg_t cardthrctl;
+    uint32_t reserved_104[2];
+    volatile sdhost_emmcddr_reg_t emmcddr;
+    volatile sdhost_enshift_reg_t enshift;
+    uint32_t reserved_114[59];
+    volatile sdhost_buffifo_reg_t buffifo;
+    uint32_t reserved_204[383];
+    volatile sdhost_clk_edge_sel_reg_t clk_edge_sel;
+    volatile sdhost_raw_ints_reg_t raw_ints;
+    volatile sdhost_dll_clk_conf_reg_t dll_clk_conf;
+    volatile sdhost_dll_conf_reg_t dll_conf;
+} sdhost_dev_t;
+
+extern sdhost_dev_t SDMMC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(sdhost_dev_t) == 0x810, "Invalid size of sdhost_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/sdmmc_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/sdmmc_reg.h
new file mode 100644
index 0000000000..9002fda91f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/sdmmc_reg.h
@@ -0,0 +1,1526 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SDHOST_CTRL_REG register
+ *  Control register
+ */
+#define SDHOST_CTRL_REG (DR_REG_SDHOST_BASE + 0x0)
+/** SDHOST_CONTROLLER_RESET : R/W; bitpos: [0]; default: 0;
+ *  To reset controller, firmware should set this bit. This bit is auto-cleared after
+ *  two AHB and two sdhost_cclk_in clock cycles.
+ */
+#define SDHOST_CONTROLLER_RESET    (BIT(0))
+#define SDHOST_CONTROLLER_RESET_M  (SDHOST_CONTROLLER_RESET_V << SDHOST_CONTROLLER_RESET_S)
+#define SDHOST_CONTROLLER_RESET_V  0x00000001U
+#define SDHOST_CONTROLLER_RESET_S  0
+/** SDHOST_FIFO_RESET : R/W; bitpos: [1]; default: 0;
+ *  To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after
+ *  completion of reset operation.
+ *  Note: FIFO pointers will be out of reset after 2 cycles of system clocks in
+ *  addition to synchronization delay (2 cycles of card clock), after the fifo_reset is
+ *  cleared.
+ */
+#define SDHOST_FIFO_RESET    (BIT(1))
+#define SDHOST_FIFO_RESET_M  (SDHOST_FIFO_RESET_V << SDHOST_FIFO_RESET_S)
+#define SDHOST_FIFO_RESET_V  0x00000001U
+#define SDHOST_FIFO_RESET_S  1
+/** SDHOST_DMA_RESET : R/W; bitpos: [2]; default: 0;
+ *  To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared
+ *  after two AHB clocks.
+ */
+#define SDHOST_DMA_RESET    (BIT(2))
+#define SDHOST_DMA_RESET_M  (SDHOST_DMA_RESET_V << SDHOST_DMA_RESET_S)
+#define SDHOST_DMA_RESET_V  0x00000001U
+#define SDHOST_DMA_RESET_S  2
+/** SDHOST_INT_ENABLE : R/W; bitpos: [4]; default: 0;
+ *  Global interrupt enable/disable bit. 0: Disable; 1: Enable.
+ */
+#define SDHOST_INT_ENABLE    (BIT(4))
+#define SDHOST_INT_ENABLE_M  (SDHOST_INT_ENABLE_V << SDHOST_INT_ENABLE_S)
+#define SDHOST_INT_ENABLE_V  0x00000001U
+#define SDHOST_INT_ENABLE_S  4
+/** SDHOST_READ_WAIT : R/W; bitpos: [6]; default: 0;
+ *  For sending read-wait to SDIO cards.
+ */
+#define SDHOST_READ_WAIT    (BIT(6))
+#define SDHOST_READ_WAIT_M  (SDHOST_READ_WAIT_V << SDHOST_READ_WAIT_S)
+#define SDHOST_READ_WAIT_V  0x00000001U
+#define SDHOST_READ_WAIT_S  6
+/** SDHOST_SEND_IRQ_RESPONSE : R/W; bitpos: [7]; default: 0;
+ *  Bit automatically clears once response is sent. To wait for MMC card interrupts,
+ *  host issues CMD40 and waits for interrupt response from MMC card(s). In the
+ *  meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this
+ *  bit, at which time SD/MMC command state-machine sends CMD40 response on bus and
+ *  returns to idle state.
+ */
+#define SDHOST_SEND_IRQ_RESPONSE    (BIT(7))
+#define SDHOST_SEND_IRQ_RESPONSE_M  (SDHOST_SEND_IRQ_RESPONSE_V << SDHOST_SEND_IRQ_RESPONSE_S)
+#define SDHOST_SEND_IRQ_RESPONSE_V  0x00000001U
+#define SDHOST_SEND_IRQ_RESPONSE_S  7
+/** SDHOST_ABORT_READ_DATA : R/W; bitpos: [8]; default: 0;
+ *  After a suspend-command is issued during a read-operation, software polls the card
+ *  to find when the suspend-event occurred. Once the suspend-event has occurred,
+ *  software sets the bit which will reset the data state machine that is waiting for
+ *  the next block of data. This bit is automatically cleared once the data state
+ *  machine is reset to idle.
+ */
+#define SDHOST_ABORT_READ_DATA    (BIT(8))
+#define SDHOST_ABORT_READ_DATA_M  (SDHOST_ABORT_READ_DATA_V << SDHOST_ABORT_READ_DATA_S)
+#define SDHOST_ABORT_READ_DATA_V  0x00000001U
+#define SDHOST_ABORT_READ_DATA_S  8
+/** SDHOST_SEND_CCSD : R/W; bitpos: [9]; default: 0;
+ *  When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if
+ *  the current command is expecting CCS (that is, RW_BLK), and if interrupts are
+ *  enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC
+ *  automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD)
+ *  bit  in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host,
+ *  in case the Command Done interrupt is not masked.
+ *  NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive
+ *  the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may
+ *  be sent to the CE-ATA device, even if the device has signalled CCS.
+ */
+#define SDHOST_SEND_CCSD    (BIT(9))
+#define SDHOST_SEND_CCSD_M  (SDHOST_SEND_CCSD_V << SDHOST_SEND_CCSD_S)
+#define SDHOST_SEND_CCSD_V  0x00000001U
+#define SDHOST_SEND_CCSD_S  9
+/** SDHOST_SEND_AUTO_STOP_CCSD : R/W; bitpos: [10]; default: 0;
+ *  Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together;
+ *  SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set,
+ *  SD/MMC automatically sends an internally-generated STOP command (CMD12) to the
+ *  CE-ATA device. After sending this internally-generated STOP command, the Auto
+ *  Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated
+ *  for the host, in case the ACD interrupt is not masked. After sending the Command
+ *  Completion Signal Disable (CCSD), SD/MMC automatically clears the
+ *  SDHOST_SEND_AUTO_STOP_CCSD bit.
+ */
+#define SDHOST_SEND_AUTO_STOP_CCSD    (BIT(10))
+#define SDHOST_SEND_AUTO_STOP_CCSD_M  (SDHOST_SEND_AUTO_STOP_CCSD_V << SDHOST_SEND_AUTO_STOP_CCSD_S)
+#define SDHOST_SEND_AUTO_STOP_CCSD_V  0x00000001U
+#define SDHOST_SEND_AUTO_STOP_CCSD_S  10
+/** SDHOST_CEATA_DEVICE_INTERRUPT_STATUS : R/W; bitpos: [11]; default: 0;
+ *  Software should appropriately write to this bit after the power-on reset or any
+ *  other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is
+ *  usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt,
+ *  then software should set this bit.
+ */
+#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS    (BIT(11))
+#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_M  (SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_V << SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_S)
+#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_V  0x00000001U
+#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_S  11
+
+/** SDHOST_CLKDIV_REG register
+ *  Clock divider configuration register
+ */
+#define SDHOST_CLKDIV_REG (DR_REG_SDHOST_BASE + 0x8)
+/** SDHOST_CLK_DIVIDER0 : R/W; bitpos: [7:0]; default: 0;
+ *  Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+ *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+ *  means divided by 2*255 = 510, and so on.
+ */
+#define SDHOST_CLK_DIVIDER0    0x000000FFU
+#define SDHOST_CLK_DIVIDER0_M  (SDHOST_CLK_DIVIDER0_V << SDHOST_CLK_DIVIDER0_S)
+#define SDHOST_CLK_DIVIDER0_V  0x000000FFU
+#define SDHOST_CLK_DIVIDER0_S  0
+/** SDHOST_CLK_DIVIDER1 : R/W; bitpos: [15:8]; default: 0;
+ *  Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+ *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+ *  means divided by 2*255 = 510, and so on.
+ */
+#define SDHOST_CLK_DIVIDER1    0x000000FFU
+#define SDHOST_CLK_DIVIDER1_M  (SDHOST_CLK_DIVIDER1_V << SDHOST_CLK_DIVIDER1_S)
+#define SDHOST_CLK_DIVIDER1_V  0x000000FFU
+#define SDHOST_CLK_DIVIDER1_S  8
+/** SDHOST_CLK_DIVIDER2 : R/W; bitpos: [23:16]; default: 0;
+ *  Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+ *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+ *  means divided by 2*255 = 510, and so on.
+ */
+#define SDHOST_CLK_DIVIDER2    0x000000FFU
+#define SDHOST_CLK_DIVIDER2_M  (SDHOST_CLK_DIVIDER2_V << SDHOST_CLK_DIVIDER2_S)
+#define SDHOST_CLK_DIVIDER2_V  0x000000FFU
+#define SDHOST_CLK_DIVIDER2_S  16
+/** SDHOST_CLK_DIVIDER3 : R/W; bitpos: [31:24]; default: 0;
+ *  Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+ *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+ *  means divided by 2*255 = 510, and so on.
+ */
+#define SDHOST_CLK_DIVIDER3    0x000000FFU
+#define SDHOST_CLK_DIVIDER3_M  (SDHOST_CLK_DIVIDER3_V << SDHOST_CLK_DIVIDER3_S)
+#define SDHOST_CLK_DIVIDER3_V  0x000000FFU
+#define SDHOST_CLK_DIVIDER3_S  24
+
+/** SDHOST_CLKSRC_REG register
+ *  Clock source selection register
+ */
+#define SDHOST_CLKSRC_REG (DR_REG_SDHOST_BASE + 0xc)
+/** SDHOST_CLKSRC : R/W; bitpos: [3:0]; default: 0;
+ *  Clock divider source for two SD cards is supported. Each card has two bits assigned
+ *  to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for
+ *  card 1. Card 0 maps and internally routes clock divider[0:3] outputs to
+ *  cclk_out[1:0] pins, depending on bit value.
+ *  00 : Clock divider 0;
+ *  01 : Clock divider 1;
+ *  10 : Clock divider 2;
+ *  11 : Clock divider 3.
+ */
+#define SDHOST_CLKSRC    0x0000000FU
+#define SDHOST_CLKSRC_M  (SDHOST_CLKSRC_V << SDHOST_CLKSRC_S)
+#define SDHOST_CLKSRC_V  0x0000000FU
+#define SDHOST_CLKSRC_S  0
+
+/** SDHOST_CLKENA_REG register
+ *  Clock enable register
+ */
+#define SDHOST_CLKENA_REG (DR_REG_SDHOST_BASE + 0x10)
+/** SDHOST_CCLK_ENABLE : R/W; bitpos: [1:0]; default: 0;
+ *  Clock-enable control for two SD card clocks and one MMC card clock is supported.
+ *  One bit per card.
+ *  0: Clock disabled;
+ *  1: Clock enabled.
+ */
+#define SDHOST_CCLK_ENABLE    0x00000003U
+#define SDHOST_CCLK_ENABLE_M  (SDHOST_CCLK_ENABLE_V << SDHOST_CCLK_ENABLE_S)
+#define SDHOST_CCLK_ENABLE_V  0x00000003U
+#define SDHOST_CCLK_ENABLE_S  0
+/** SDHOST_LP_ENABLE : R/W; bitpos: [17:16]; default: 0;
+ *  Disable clock when the card is in IDLE state. One bit per card.
+ *  0: clock disabled;
+ *  1: clock enabled.
+ */
+#define SDHOST_LP_ENABLE    0x00000003U
+#define SDHOST_LP_ENABLE_M  (SDHOST_LP_ENABLE_V << SDHOST_LP_ENABLE_S)
+#define SDHOST_LP_ENABLE_V  0x00000003U
+#define SDHOST_LP_ENABLE_S  16
+
+/** SDHOST_TMOUT_REG register
+ *  Data and response timeout configuration register
+ */
+#define SDHOST_TMOUT_REG (DR_REG_SDHOST_BASE + 0x14)
+/** SDHOST_RESPONSE_TIMEOUT : R/W; bitpos: [7:0]; default: 64;
+ *  Response timeout value. Value is specified in terms of number of card output
+ *  clocks, i.e., sdhost_cclk_out.
+ */
+#define SDHOST_RESPONSE_TIMEOUT    0x000000FFU
+#define SDHOST_RESPONSE_TIMEOUT_M  (SDHOST_RESPONSE_TIMEOUT_V << SDHOST_RESPONSE_TIMEOUT_S)
+#define SDHOST_RESPONSE_TIMEOUT_V  0x000000FFU
+#define SDHOST_RESPONSE_TIMEOUT_S  0
+/** SDHOST_DATA_TIMEOUT : R/W; bitpos: [31:8]; default: 16777215;
+ *  Value for card data read timeout. This value is also used for data starvation by
+ *  host timeout. The timeout counter is started only after the card clock is stopped.
+ *  This value is specified in number of card output clocks, i.e. sdhost_cclk_out of
+ *  the selected card.
+ *  NOTE: The software timer should be used if the timeout value is in the order of 100
+ *  ms. In this case, read data timeout interrupt needs to be disabled.
+ */
+#define SDHOST_DATA_TIMEOUT    0x00FFFFFFU
+#define SDHOST_DATA_TIMEOUT_M  (SDHOST_DATA_TIMEOUT_V << SDHOST_DATA_TIMEOUT_S)
+#define SDHOST_DATA_TIMEOUT_V  0x00FFFFFFU
+#define SDHOST_DATA_TIMEOUT_S  8
+
+/** SDHOST_CTYPE_REG register
+ *  Card bus width configuration register
+ */
+#define SDHOST_CTYPE_REG (DR_REG_SDHOST_BASE + 0x18)
+/** SDHOST_CARD_WIDTH4 : R/W; bitpos: [1:0]; default: 0;
+ *  One bit per card indicates if card is 1-bit or 4-bit mode.
+ *  0: 1-bit mode;
+ *  1: 4-bit mode.
+ *  Bit[1:0] correspond to card[1:0] respectively.
+ */
+#define SDHOST_CARD_WIDTH4    0x00000003U
+#define SDHOST_CARD_WIDTH4_M  (SDHOST_CARD_WIDTH4_V << SDHOST_CARD_WIDTH4_S)
+#define SDHOST_CARD_WIDTH4_V  0x00000003U
+#define SDHOST_CARD_WIDTH4_S  0
+/** SDHOST_CARD_WIDTH8 : R/W; bitpos: [17:16]; default: 0;
+ *  One bit per card indicates if card is in 8-bit mode.
+ *  0: Non 8-bit mode;
+ *  1: 8-bit mode.
+ *  Bit[17:16] correspond to card[1:0] respectively.
+ */
+#define SDHOST_CARD_WIDTH8    0x00000003U
+#define SDHOST_CARD_WIDTH8_M  (SDHOST_CARD_WIDTH8_V << SDHOST_CARD_WIDTH8_S)
+#define SDHOST_CARD_WIDTH8_V  0x00000003U
+#define SDHOST_CARD_WIDTH8_S  16
+
+/** SDHOST_BLKSIZ_REG register
+ *  Card data block size configuration register
+ */
+#define SDHOST_BLKSIZ_REG (DR_REG_SDHOST_BASE + 0x1c)
+/** SDHOST_BLOCK_SIZE : R/W; bitpos: [15:0]; default: 512;
+ *  Block size.
+ */
+#define SDHOST_BLOCK_SIZE    0x0000FFFFU
+#define SDHOST_BLOCK_SIZE_M  (SDHOST_BLOCK_SIZE_V << SDHOST_BLOCK_SIZE_S)
+#define SDHOST_BLOCK_SIZE_V  0x0000FFFFU
+#define SDHOST_BLOCK_SIZE_S  0
+
+/** SDHOST_BYTCNT_REG register
+ *  Data transfer length configuration register
+ */
+#define SDHOST_BYTCNT_REG (DR_REG_SDHOST_BASE + 0x20)
+/** SDHOST_BYTE_COUNT : R/W; bitpos: [31:0]; default: 512;
+ *  Number of bytes to be transferred, should be an integral multiple of Block Size for
+ *  block transfers. For data transfers of undefined byte lengths, byte count should be
+ *  set to 0. When byte count is set to 0, it is the responsibility of host to
+ *  explicitly send stop/abort command to terminate data transfer.
+ */
+#define SDHOST_BYTE_COUNT    0xFFFFFFFFU
+#define SDHOST_BYTE_COUNT_M  (SDHOST_BYTE_COUNT_V << SDHOST_BYTE_COUNT_S)
+#define SDHOST_BYTE_COUNT_V  0xFFFFFFFFU
+#define SDHOST_BYTE_COUNT_S  0
+
+/** SDHOST_INTMASK_REG register
+ *  SDIO interrupt mask register
+ */
+#define SDHOST_INTMASK_REG (DR_REG_SDHOST_BASE + 0x24)
+/** SDHOST_INT_MASK : R/W; bitpos: [15:0]; default: 0;
+ *  These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a
+ *  value of 1 enables the interrupt.
+ *  Bit 15 (EBE): End-bit error/no CRC error;
+ *  Bit 14 (ACD): Auto command done;
+ *  Bit 13 (SBE/BCI): Rx Start Bit Error;
+ *  Bit 12 (HLE): Hardware locked write error;
+ *  Bit 11 (FRUN): FIFO underrun/overrun error;
+ *  Bit 10 (HTO): Data starvation-by-host timeout;
+ *  Bit 9 (DRTO): Data read timeout;
+ *  Bit 8 (RTO): Response timeout;
+ *  Bit 7 (DCRC): Data CRC error;
+ *  Bit 6 (RCRC): Response CRC error;
+ *  Bit 5 (RXDR): Receive FIFO data request;
+ *  Bit 4 (TXDR): Transmit FIFO data request;
+ *  Bit 3 (DTO): Data transfer over;
+ *  Bit 2 (CD): Command done;
+ *  Bit 1 (RE): Response error;
+ *  Bit 0 (CD): Card detect.
+ */
+#define SDHOST_INT_MASK    0x0000FFFFU
+#define SDHOST_INT_MASK_M  (SDHOST_INT_MASK_V << SDHOST_INT_MASK_S)
+#define SDHOST_INT_MASK_V  0x0000FFFFU
+#define SDHOST_INT_MASK_S  0
+/** SDHOST_SDIO_INT_MASK : R/W; bitpos: [17:16]; default: 0;
+ *  SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0]
+ *  respectively. When masked, SDIO interrupt detection for that card is disabled. 0
+ *  masks an interrupt, and 1 enables an interrupt.
+ */
+#define SDHOST_SDIO_INT_MASK    0x00000003U
+#define SDHOST_SDIO_INT_MASK_M  (SDHOST_SDIO_INT_MASK_V << SDHOST_SDIO_INT_MASK_S)
+#define SDHOST_SDIO_INT_MASK_V  0x00000003U
+#define SDHOST_SDIO_INT_MASK_S  16
+
+/** SDHOST_CMDARG_REG register
+ *  Command argument data register
+ */
+#define SDHOST_CMDARG_REG (DR_REG_SDHOST_BASE + 0x28)
+/** SDHOST_CMDARG : R/W; bitpos: [31:0]; default: 0;
+ *  Value indicates command argument to be passed to the card.
+ */
+#define SDHOST_CMDARG    0xFFFFFFFFU
+#define SDHOST_CMDARG_M  (SDHOST_CMDARG_V << SDHOST_CMDARG_S)
+#define SDHOST_CMDARG_V  0xFFFFFFFFU
+#define SDHOST_CMDARG_S  0
+
+/** SDHOST_CMD_REG register
+ *  Command and boot configuration register
+ */
+#define SDHOST_CMD_REG (DR_REG_SDHOST_BASE + 0x2c)
+/** SDHOST_CMD_INDEX : R/W; bitpos: [5:0]; default: 0;
+ *  Command index.
+ */
+#define SDHOST_CMD_INDEX    0x0000003FU
+#define SDHOST_CMD_INDEX_M  (SDHOST_CMD_INDEX_V << SDHOST_CMD_INDEX_S)
+#define SDHOST_CMD_INDEX_V  0x0000003FU
+#define SDHOST_CMD_INDEX_S  0
+/** SDHOST_RESPONSE_EXPECT : R/W; bitpos: [6]; default: 0;
+ *  0: No response expected from card; 1: Response expected from card.
+ */
+#define SDHOST_RESPONSE_EXPECT    (BIT(6))
+#define SDHOST_RESPONSE_EXPECT_M  (SDHOST_RESPONSE_EXPECT_V << SDHOST_RESPONSE_EXPECT_S)
+#define SDHOST_RESPONSE_EXPECT_V  0x00000001U
+#define SDHOST_RESPONSE_EXPECT_S  6
+/** SDHOST_RESPONSE_LENGTH : R/W; bitpos: [7]; default: 0;
+ *  0: Short response expected from card; 1: Long response expected from card.
+ */
+#define SDHOST_RESPONSE_LENGTH    (BIT(7))
+#define SDHOST_RESPONSE_LENGTH_M  (SDHOST_RESPONSE_LENGTH_V << SDHOST_RESPONSE_LENGTH_S)
+#define SDHOST_RESPONSE_LENGTH_V  0x00000001U
+#define SDHOST_RESPONSE_LENGTH_S  7
+/** SDHOST_CHECK_RESPONSE_CRC : R/W; bitpos: [8]; default: 0;
+ *  0: Do not check; 1: Check response CRC.
+ *  Some of command responses do not return valid CRC bits. Software should disable CRC
+ *  checks for those commands in order to disable CRC checking by controller.
+ */
+#define SDHOST_CHECK_RESPONSE_CRC    (BIT(8))
+#define SDHOST_CHECK_RESPONSE_CRC_M  (SDHOST_CHECK_RESPONSE_CRC_V << SDHOST_CHECK_RESPONSE_CRC_S)
+#define SDHOST_CHECK_RESPONSE_CRC_V  0x00000001U
+#define SDHOST_CHECK_RESPONSE_CRC_S  8
+/** SDHOST_DATA_EXPECTED : R/W; bitpos: [9]; default: 0;
+ *  0: No data transfer expected; 1: Data transfer expected.
+ */
+#define SDHOST_DATA_EXPECTED    (BIT(9))
+#define SDHOST_DATA_EXPECTED_M  (SDHOST_DATA_EXPECTED_V << SDHOST_DATA_EXPECTED_S)
+#define SDHOST_DATA_EXPECTED_V  0x00000001U
+#define SDHOST_DATA_EXPECTED_S  9
+/** SDHOST_READ_WRITE : R/W; bitpos: [10]; default: 0;
+ *  0: Read from card; 1: Write to card.
+ *  Don't care if no data is expected from card.
+ */
+#define SDHOST_READ_WRITE    (BIT(10))
+#define SDHOST_READ_WRITE_M  (SDHOST_READ_WRITE_V << SDHOST_READ_WRITE_S)
+#define SDHOST_READ_WRITE_V  0x00000001U
+#define SDHOST_READ_WRITE_S  10
+/** SDHOST_TRANSFER_MODE : R/W; bitpos: [11]; default: 0;
+ *  0: Block data transfer command; 1: Stream data transfer command.
+ *  Don't care if no data expected.
+ */
+#define SDHOST_TRANSFER_MODE    (BIT(11))
+#define SDHOST_TRANSFER_MODE_M  (SDHOST_TRANSFER_MODE_V << SDHOST_TRANSFER_MODE_S)
+#define SDHOST_TRANSFER_MODE_V  0x00000001U
+#define SDHOST_TRANSFER_MODE_S  11
+/** SDHOST_SEND_AUTO_STOP : R/W; bitpos: [12]; default: 0;
+ *  0: No stop command is sent at the end of data transfer; 1: Send stop command at the
+ *  end of data transfer.
+ */
+#define SDHOST_SEND_AUTO_STOP    (BIT(12))
+#define SDHOST_SEND_AUTO_STOP_M  (SDHOST_SEND_AUTO_STOP_V << SDHOST_SEND_AUTO_STOP_S)
+#define SDHOST_SEND_AUTO_STOP_V  0x00000001U
+#define SDHOST_SEND_AUTO_STOP_S  12
+/** SDHOST_WAIT_PRVDATA_COMPLETE : R/W; bitpos: [13]; default: 0;
+ *  0: Send command at once, even if previous data transfer has not completed; 1: Wait
+ *  for previous data transfer to complete before sending Command.
+ *  The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of
+ *  card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr
+ *  should be same as in previous command.
+ */
+#define SDHOST_WAIT_PRVDATA_COMPLETE    (BIT(13))
+#define SDHOST_WAIT_PRVDATA_COMPLETE_M  (SDHOST_WAIT_PRVDATA_COMPLETE_V << SDHOST_WAIT_PRVDATA_COMPLETE_S)
+#define SDHOST_WAIT_PRVDATA_COMPLETE_V  0x00000001U
+#define SDHOST_WAIT_PRVDATA_COMPLETE_S  13
+/** SDHOST_STOP_ABORT_CMD : R/W; bitpos: [14]; default: 0;
+ *  0: Neither stop nor abort command can stop current data transfer. If abort is sent
+ *  to function-number currently selected or not in data-transfer mode, then bit should
+ *  be set to 0; 1: Stop or abort command intended to stop current data transfer in
+ *  progress.
+ *  When open-ended or predefined data transfer is in progress, and host issues stop or
+ *  abort command to stop data transfer, bit should be set so that command/data
+ *  state-machines of CIU can return correctly to idle state.
+ */
+#define SDHOST_STOP_ABORT_CMD    (BIT(14))
+#define SDHOST_STOP_ABORT_CMD_M  (SDHOST_STOP_ABORT_CMD_V << SDHOST_STOP_ABORT_CMD_S)
+#define SDHOST_STOP_ABORT_CMD_V  0x00000001U
+#define SDHOST_STOP_ABORT_CMD_S  14
+/** SDHOST_SEND_INITIALIZATION : R/W; bitpos: [15]; default: 0;
+ *  0: Do not send initialization sequence (80 clocks of 1) before sending this
+ *  command; 1: Send initialization sequence before sending this command.
+ *  After powered on, 80 clocks must be sent to card for initialization before sending
+ *  any commands to card. Bit should be set while sending first command to card so that
+ *  controller will initialize clocks before sending command to card.
+ */
+#define SDHOST_SEND_INITIALIZATION    (BIT(15))
+#define SDHOST_SEND_INITIALIZATION_M  (SDHOST_SEND_INITIALIZATION_V << SDHOST_SEND_INITIALIZATION_S)
+#define SDHOST_SEND_INITIALIZATION_V  0x00000001U
+#define SDHOST_SEND_INITIALIZATION_S  15
+/** SDHOST_CARD_NUMBER : R/W; bitpos: [20:16]; default: 0;
+ *  Card number in use. Represents physical slot number of card being accessed. In
+ *  SD-only mode, up to two cards are supported.
+ */
+#define SDHOST_CARD_NUMBER    0x0000001FU
+#define SDHOST_CARD_NUMBER_M  (SDHOST_CARD_NUMBER_V << SDHOST_CARD_NUMBER_S)
+#define SDHOST_CARD_NUMBER_V  0x0000001FU
+#define SDHOST_CARD_NUMBER_S  16
+/** SDHOST_UPDATE_CLOCK_REGISTERS_ONLY : R/W; bitpos: [21]; default: 0;
+ *  0: Normal command sequence; 1: Do not send commands, just update clock register
+ *  value into card clock domain.
+ *  Following register values are transferred into card clock domain: CLKDIV, CLRSRC,
+ *  and CLKENA.
+ *  Changes card clocks (change frequency, truncate off or on, and set low-frequency
+ *  mode). This is provided in order to change clock frequency or stop clock without
+ *  having to send command to cards. During normal command sequence, when
+ *  sdhost_update_clock_registers_only = 0, following control registers are transferred
+ *  from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new
+ *  register values for new command sequence to card(s). When bit is set, there are no
+ *  Command Done interrupts because no command is sent to SD_MMC_CEATA cards.
+ */
+#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY    (BIT(21))
+#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_M  (SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_V << SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_S)
+#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_V  0x00000001U
+#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_S  21
+/** SDHOST_READ_CEATA_DEVICE : R/W; bitpos: [22]; default: 0;
+ *  Read access flag.
+ *  0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;
+ *  1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.
+ *  Software should set this bit to indicate that CE-ATA device is being accessed for
+ *  read transfer. This bit is used to disable read data timeout indication while
+ *  performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no
+ *  less than 10 seconds. SD/MMC should not indicate read data timeout while waiting
+ *  for data from CE-ATA device.
+ */
+#define SDHOST_READ_CEATA_DEVICE    (BIT(22))
+#define SDHOST_READ_CEATA_DEVICE_M  (SDHOST_READ_CEATA_DEVICE_V << SDHOST_READ_CEATA_DEVICE_S)
+#define SDHOST_READ_CEATA_DEVICE_V  0x00000001U
+#define SDHOST_READ_CEATA_DEVICE_S  22
+/** SDHOST_CCS_EXPECTED : R/W; bitpos: [23]; default: 0;
+ *  Expected Command Completion Signal (CCS) configuration.
+ *  0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register),
+ *  or command does not expect CCS from device;
+ *  1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects
+ *  command completion signal from CE-ATA device.
+ *  If the command expects Command Completion Signal (CCS) from the CE-ATA device, the
+ *  software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in
+ *  RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is
+ *  not masked.
+ */
+#define SDHOST_CCS_EXPECTED    (BIT(23))
+#define SDHOST_CCS_EXPECTED_M  (SDHOST_CCS_EXPECTED_V << SDHOST_CCS_EXPECTED_S)
+#define SDHOST_CCS_EXPECTED_V  0x00000001U
+#define SDHOST_CCS_EXPECTED_S  23
+/** SDHOST_USE_HOLE_REG : R/W; bitpos: [29]; default: 1;
+ *  Use Hold Register.
+ *  0: CMD and DATA sent to card bypassing HOLD Register;
+ *  1: CMD and DATA sent to card through the HOLD Register.
+ */
+#define SDHOST_USE_HOLE_REG    (BIT(29))
+#define SDHOST_USE_HOLE_REG_M  (SDHOST_USE_HOLE_REG_V << SDHOST_USE_HOLE_REG_S)
+#define SDHOST_USE_HOLE_REG_V  0x00000001U
+#define SDHOST_USE_HOLE_REG_S  29
+/** SDHOST_START_CMD : R/W; bitpos: [31]; default: 0;
+ *  Start command. Once command is served by the CIU, this bit is automatically
+ *  cleared. When this bit is set, host should not attempt to write to any command
+ *  registers. If a write is attempted, hardware lock error is set in raw interrupt
+ *  register. Once command is sent and a response is received from SD_MMC_CEATA cards,
+ *  Command Done bit is set in the raw interrupt Register.
+ */
+#define SDHOST_START_CMD    (BIT(31))
+#define SDHOST_START_CMD_M  (SDHOST_START_CMD_V << SDHOST_START_CMD_S)
+#define SDHOST_START_CMD_V  0x00000001U
+#define SDHOST_START_CMD_S  31
+
+/** SDHOST_RESP0_REG register
+ *  Response data register
+ */
+#define SDHOST_RESP0_REG (DR_REG_SDHOST_BASE + 0x30)
+/** SDHOST_RESPONSE0_REG : RO; bitpos: [31:0]; default: 0;
+ *  Bit[31:0] of response.
+ */
+#define SDHOST_RESPONSE0_REG    0xFFFFFFFFU
+#define SDHOST_RESPONSE0_REG_M  (SDHOST_RESPONSE0_REG_V << SDHOST_RESPONSE0_REG_S)
+#define SDHOST_RESPONSE0_REG_V  0xFFFFFFFFU
+#define SDHOST_RESPONSE0_REG_S  0
+
+/** SDHOST_RESP1_REG register
+ *  Long response data register
+ */
+#define SDHOST_RESP1_REG (DR_REG_SDHOST_BASE + 0x34)
+/** SDHOST_RESPONSE1_REG : RO; bitpos: [31:0]; default: 0;
+ *  Bit[63:32] of long response.
+ */
+#define SDHOST_RESPONSE1_REG    0xFFFFFFFFU
+#define SDHOST_RESPONSE1_REG_M  (SDHOST_RESPONSE1_REG_V << SDHOST_RESPONSE1_REG_S)
+#define SDHOST_RESPONSE1_REG_V  0xFFFFFFFFU
+#define SDHOST_RESPONSE1_REG_S  0
+
+/** SDHOST_RESP2_REG register
+ *  Long response data register
+ */
+#define SDHOST_RESP2_REG (DR_REG_SDHOST_BASE + 0x38)
+/** SDHOST_RESPONSE2_REG : RO; bitpos: [31:0]; default: 0;
+ *  Bit[95:64] of long response.
+ */
+#define SDHOST_RESPONSE2_REG    0xFFFFFFFFU
+#define SDHOST_RESPONSE2_REG_M  (SDHOST_RESPONSE2_REG_V << SDHOST_RESPONSE2_REG_S)
+#define SDHOST_RESPONSE2_REG_V  0xFFFFFFFFU
+#define SDHOST_RESPONSE2_REG_S  0
+
+/** SDHOST_RESP3_REG register
+ *  Long response data register
+ */
+#define SDHOST_RESP3_REG (DR_REG_SDHOST_BASE + 0x3c)
+/** SDHOST_RESPONSE3_REG : RO; bitpos: [31:0]; default: 0;
+ *  Bit[127:96] of long response.
+ */
+#define SDHOST_RESPONSE3_REG    0xFFFFFFFFU
+#define SDHOST_RESPONSE3_REG_M  (SDHOST_RESPONSE3_REG_V << SDHOST_RESPONSE3_REG_S)
+#define SDHOST_RESPONSE3_REG_V  0xFFFFFFFFU
+#define SDHOST_RESPONSE3_REG_S  0
+
+/** SDHOST_MINTSTS_REG register
+ *  Masked interrupt status register
+ */
+#define SDHOST_MINTSTS_REG (DR_REG_SDHOST_BASE + 0x40)
+/** SDHOST_INT_STATUS_MSK : RO; bitpos: [15:0]; default: 0;
+ *  Interrupt enabled only if corresponding bit in interrupt mask register is set.
+ *  Bit 15 (EBE): End-bit error/no CRC error;
+ *  Bit 14 (ACD): Auto command done;
+ *  Bit 13 (SBE/BCI): RX Start Bit Error;
+ *  Bit 12 (HLE): Hardware locked write error;
+ *  Bit 11 (FRUN): FIFO underrun/overrun error;
+ *  Bit 10 (HTO): Data starvation by host timeout (HTO);
+ *  Bit 9 (DTRO): Data read timeout;
+ *  Bit 8 (RTO): Response timeout;
+ *  Bit 7 (DCRC): Data CRC error;
+ *  Bit 6 (RCRC): Response CRC error;
+ *  Bit 5 (RXDR): Receive FIFO data request;
+ *  Bit 4 (TXDR): Transmit FIFO data request;
+ *  Bit 3 (DTO): Data transfer over;
+ *  Bit 2 (CD): Command done;
+ *  Bit 1 (RE): Response error;
+ *  Bit 0 (CD): Card detect.
+ */
+#define SDHOST_INT_STATUS_MSK    0x0000FFFFU
+#define SDHOST_INT_STATUS_MSK_M  (SDHOST_INT_STATUS_MSK_V << SDHOST_INT_STATUS_MSK_S)
+#define SDHOST_INT_STATUS_MSK_V  0x0000FFFFU
+#define SDHOST_INT_STATUS_MSK_S  0
+/** SDHOST_SDIO_INTERRUPT_MSK : RO; bitpos: [17:16]; default: 0;
+ *  Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
+ *  card0, respectively. SDIO interrupt for card is enabled only if corresponding
+ *  sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit
+ *  enables interrupt).
+ */
+#define SDHOST_SDIO_INTERRUPT_MSK    0x00000003U
+#define SDHOST_SDIO_INTERRUPT_MSK_M  (SDHOST_SDIO_INTERRUPT_MSK_V << SDHOST_SDIO_INTERRUPT_MSK_S)
+#define SDHOST_SDIO_INTERRUPT_MSK_V  0x00000003U
+#define SDHOST_SDIO_INTERRUPT_MSK_S  16
+
+/** SDHOST_RINTSTS_REG register
+ *  Raw interrupt status register
+ */
+#define SDHOST_RINTSTS_REG (DR_REG_SDHOST_BASE + 0x44)
+/** SDHOST_INT_STATUS_RAW : R/W; bitpos: [15:0]; default: 0;
+ *  Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits
+ *  are logged regardless of interrupt mask status.
+ *  Bit 15 (EBE): End-bit error/no CRC error;
+ *  Bit 14 (ACD): Auto command done;
+ *  Bit 13 (SBE/BCI): RX Start Bit Error;
+ *  Bit 12 (HLE): Hardware locked write error;
+ *  Bit 11 (FRUN): FIFO underrun/overrun error;
+ *  Bit 10 (HTO): Data starvation by host timeout (HTO);
+ *  Bit 9 (DTRO): Data read timeout;
+ *  Bit 8 (RTO): Response timeout;
+ *  Bit 7 (DCRC): Data CRC error;
+ *  Bit 6 (RCRC): Response CRC error;
+ *  Bit 5 (RXDR): Receive FIFO data request;
+ *  Bit 4 (TXDR): Transmit FIFO data request;
+ *  Bit 3 (DTO): Data transfer over;
+ *  Bit 2 (CD): Command done;
+ *  Bit 1 (RE): Response error;
+ *  Bit 0 (CD): Card detect.
+ */
+#define SDHOST_INT_STATUS_RAW    0x0000FFFFU
+#define SDHOST_INT_STATUS_RAW_M  (SDHOST_INT_STATUS_RAW_V << SDHOST_INT_STATUS_RAW_S)
+#define SDHOST_INT_STATUS_RAW_V  0x0000FFFFU
+#define SDHOST_INT_STATUS_RAW_S  0
+/** SDHOST_SDIO_INTERRUPT_RAW : R/W; bitpos: [17:16]; default: 0;
+ *  Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
+ *  card0, respectively. Setting a bit clears the corresponding interrupt bit and
+ *  writing 0 has no effect.
+ *  0: No SDIO interrupt from card;
+ *  1: SDIO interrupt from card.
+ */
+#define SDHOST_SDIO_INTERRUPT_RAW    0x00000003U
+#define SDHOST_SDIO_INTERRUPT_RAW_M  (SDHOST_SDIO_INTERRUPT_RAW_V << SDHOST_SDIO_INTERRUPT_RAW_S)
+#define SDHOST_SDIO_INTERRUPT_RAW_V  0x00000003U
+#define SDHOST_SDIO_INTERRUPT_RAW_S  16
+
+/** SDHOST_STATUS_REG register
+ *  SD/MMC status register
+ */
+#define SDHOST_STATUS_REG (DR_REG_SDHOST_BASE + 0x48)
+/** SDHOST_FIFO_RX_WATERMARK : RO; bitpos: [0]; default: 0;
+ *  FIFO reached Receive watermark level, not qualified with data transfer.
+ */
+#define SDHOST_FIFO_RX_WATERMARK    (BIT(0))
+#define SDHOST_FIFO_RX_WATERMARK_M  (SDHOST_FIFO_RX_WATERMARK_V << SDHOST_FIFO_RX_WATERMARK_S)
+#define SDHOST_FIFO_RX_WATERMARK_V  0x00000001U
+#define SDHOST_FIFO_RX_WATERMARK_S  0
+/** SDHOST_FIFO_TX_WATERMARK : RO; bitpos: [1]; default: 1;
+ *  FIFO reached Transmit watermark level, not qualified with data transfer.
+ */
+#define SDHOST_FIFO_TX_WATERMARK    (BIT(1))
+#define SDHOST_FIFO_TX_WATERMARK_M  (SDHOST_FIFO_TX_WATERMARK_V << SDHOST_FIFO_TX_WATERMARK_S)
+#define SDHOST_FIFO_TX_WATERMARK_V  0x00000001U
+#define SDHOST_FIFO_TX_WATERMARK_S  1
+/** SDHOST_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  FIFO is empty status.
+ */
+#define SDHOST_FIFO_EMPTY    (BIT(2))
+#define SDHOST_FIFO_EMPTY_M  (SDHOST_FIFO_EMPTY_V << SDHOST_FIFO_EMPTY_S)
+#define SDHOST_FIFO_EMPTY_V  0x00000001U
+#define SDHOST_FIFO_EMPTY_S  2
+/** SDHOST_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  FIFO is full status.
+ */
+#define SDHOST_FIFO_FULL    (BIT(3))
+#define SDHOST_FIFO_FULL_M  (SDHOST_FIFO_FULL_V << SDHOST_FIFO_FULL_S)
+#define SDHOST_FIFO_FULL_V  0x00000001U
+#define SDHOST_FIFO_FULL_S  3
+/** SDHOST_COMMAND_FSM_STATES : RO; bitpos: [7:4]; default: 1;
+ *  Command FSM states.
+ *  0: Idle;
+ *  1: Send init sequence;
+ *  2: Send cmd start bit;
+ *  3: Send cmd tx bit;
+ *  4: Send cmd index + arg;
+ *  5: Send cmd crc7;
+ *  6: Send cmd end bit;
+ *  7: Receive resp start bit;
+ *  8: Receive resp IRQ response;
+ *  9: Receive resp tx bit;
+ *  10: Receive resp cmd idx;
+ *  11: Receive resp data;
+ *  12: Receive resp crc7;
+ *  13: Receive resp end bit;
+ *  14: Cmd path wait NCC;
+ *  15: Wait, cmd-to-response turnaround.
+ */
+#define SDHOST_COMMAND_FSM_STATES    0x0000000FU
+#define SDHOST_COMMAND_FSM_STATES_M  (SDHOST_COMMAND_FSM_STATES_V << SDHOST_COMMAND_FSM_STATES_S)
+#define SDHOST_COMMAND_FSM_STATES_V  0x0000000FU
+#define SDHOST_COMMAND_FSM_STATES_S  4
+/** SDHOST_DATA_3_STATUS : RO; bitpos: [8]; default: 1;
+ *  Raw selected sdhost_card_data[3], checks whether card is present.
+ *  0: card not present;
+ *  1: card present.
+ */
+#define SDHOST_DATA_3_STATUS    (BIT(8))
+#define SDHOST_DATA_3_STATUS_M  (SDHOST_DATA_3_STATUS_V << SDHOST_DATA_3_STATUS_S)
+#define SDHOST_DATA_3_STATUS_V  0x00000001U
+#define SDHOST_DATA_3_STATUS_S  8
+/** SDHOST_DATA_BUSY : RO; bitpos: [9]; default: 1;
+ *  Inverted version of raw selected sdhost_card_data[0].
+ *  0: Card data not busy;
+ *  1: Card data busy.
+ */
+#define SDHOST_DATA_BUSY    (BIT(9))
+#define SDHOST_DATA_BUSY_M  (SDHOST_DATA_BUSY_V << SDHOST_DATA_BUSY_S)
+#define SDHOST_DATA_BUSY_V  0x00000001U
+#define SDHOST_DATA_BUSY_S  9
+/** SDHOST_DATA_STATE_MC_BUSY : RO; bitpos: [10]; default: 1;
+ *  Data transmit or receive state-machine is busy.
+ */
+#define SDHOST_DATA_STATE_MC_BUSY    (BIT(10))
+#define SDHOST_DATA_STATE_MC_BUSY_M  (SDHOST_DATA_STATE_MC_BUSY_V << SDHOST_DATA_STATE_MC_BUSY_S)
+#define SDHOST_DATA_STATE_MC_BUSY_V  0x00000001U
+#define SDHOST_DATA_STATE_MC_BUSY_S  10
+/** SDHOST_RESPONSE_INDEX : RO; bitpos: [16:11]; default: 0;
+ *  Index of previous response, including any auto-stop sent by core.
+ */
+#define SDHOST_RESPONSE_INDEX    0x0000003FU
+#define SDHOST_RESPONSE_INDEX_M  (SDHOST_RESPONSE_INDEX_V << SDHOST_RESPONSE_INDEX_S)
+#define SDHOST_RESPONSE_INDEX_V  0x0000003FU
+#define SDHOST_RESPONSE_INDEX_S  11
+/** SDHOST_FIFO_COUNT : RO; bitpos: [29:17]; default: 0;
+ *  FIFO count, number of filled locations in FIFO.
+ */
+#define SDHOST_FIFO_COUNT    0x00001FFFU
+#define SDHOST_FIFO_COUNT_M  (SDHOST_FIFO_COUNT_V << SDHOST_FIFO_COUNT_S)
+#define SDHOST_FIFO_COUNT_V  0x00001FFFU
+#define SDHOST_FIFO_COUNT_S  17
+
+/** SDHOST_FIFOTH_REG register
+ *  FIFO configuration register
+ */
+#define SDHOST_FIFOTH_REG (DR_REG_SDHOST_BASE + 0x4c)
+/** SDHOST_TX_WMARK : R/W; bitpos: [11:0]; default: 0;
+ *  FIFO threshold watermark level when transmitting data to card. When FIFO data count
+ *  is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is
+ *  enabled, then interrupt  occurs. During end of packet, request or interrupt is
+ *  generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO
+ *  threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA
+ *  request. During end of packet, on last interrupt, host is responsible for filling
+ *  FIFO with only required remaining bytes (not before FIFO is full or after CIU
+ *  completes data transfers, because FIFO may not be empty).  In DMA mode, at end of
+ *  packet, if last transfer is less than burst  size, DMA controller does single
+ *  cycles until required bytes are  transferred.
+ */
+#define SDHOST_TX_WMARK    0x00000FFFU
+#define SDHOST_TX_WMARK_M  (SDHOST_TX_WMARK_V << SDHOST_TX_WMARK_S)
+#define SDHOST_TX_WMARK_V  0x00000FFFU
+#define SDHOST_TX_WMARK_S  0
+/** SDHOST_RX_WMARK : R/W; bitpos: [26:16]; default: 0;
+ *  FIFO threshold watermark level when receiving data to card.When FIFO data count
+ *  reaches greater than this number , DMA/FIFO request is raised. During end of
+ *  packet, request is generated regardless of threshold programming in order to
+ *  complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR)
+ *  interrupt is enabled, then interrupt is generated instead of DMA request.During end
+ *  of packet, interrupt is not generated if threshold programming is larger than any
+ *  remaining data. It is responsibility of host to read remaining bytes on seeing Data
+ *  Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are
+ *  less than threshold, DMA request does single transfers to flush out any remaining
+ *  bytes before Data Transfer Done interrupt is set.
+ */
+#define SDHOST_RX_WMARK    0x000007FFU
+#define SDHOST_RX_WMARK_M  (SDHOST_RX_WMARK_V << SDHOST_RX_WMARK_S)
+#define SDHOST_RX_WMARK_V  0x000007FFU
+#define SDHOST_RX_WMARK_S  16
+/** SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE : R/W; bitpos: [30:28]; default: 0;
+ *  Burst size of multiple transaction, should be programmed same as DMA controller
+ *  multiple-transaction-size SDHOST_SRC/DEST_MSIZE.
+ *  000: 1-byte transfer;
+ *  001: 4-byte transfer;
+ *  010: 8-byte transfer;
+ *  011: 16-byte transfer;
+ *  100: 32-byte transfer;
+ *  101: 64-byte transfer;
+ *  110: 128-byte transfer;
+ *  111: 256-byte transfer.
+ */
+#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE    0x00000007U
+#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_M  (SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_V << SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_S)
+#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_V  0x00000007U
+#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_S  28
+
+/** SDHOST_CDETECT_REG register
+ *  Card detect register
+ */
+#define SDHOST_CDETECT_REG (DR_REG_SDHOST_BASE + 0x50)
+/** SDHOST_CARD_DETECT_N : RO; bitpos: [1:0]; default: 0;
+ *  Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0
+ *  represents presence of card. Only NUM_CARDS number of bits are implemented.
+ */
+#define SDHOST_CARD_DETECT_N    0x00000003U
+#define SDHOST_CARD_DETECT_N_M  (SDHOST_CARD_DETECT_N_V << SDHOST_CARD_DETECT_N_S)
+#define SDHOST_CARD_DETECT_N_V  0x00000003U
+#define SDHOST_CARD_DETECT_N_S  0
+
+/** SDHOST_WRTPRT_REG register
+ *  Card write protection (WP) status register
+ */
+#define SDHOST_WRTPRT_REG (DR_REG_SDHOST_BASE + 0x54)
+/** SDHOST_WRITE_PROTECT : RO; bitpos: [1:0]; default: 0;
+ *  Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write
+ *  protection. Only NUM_CARDS number of bits are implemented.
+ */
+#define SDHOST_WRITE_PROTECT    0x00000003U
+#define SDHOST_WRITE_PROTECT_M  (SDHOST_WRITE_PROTECT_V << SDHOST_WRITE_PROTECT_S)
+#define SDHOST_WRITE_PROTECT_V  0x00000003U
+#define SDHOST_WRITE_PROTECT_S  0
+
+/** SDHOST_TCBCNT_REG register
+ *  Transferred byte count register
+ */
+#define SDHOST_TCBCNT_REG (DR_REG_SDHOST_BASE + 0x5c)
+/** SDHOST_TCBCNT : RO; bitpos: [31:0]; default: 0;
+ *  Number of bytes transferred by CIU unit to card.
+ */
+#define SDHOST_TCBCNT    0xFFFFFFFFU
+#define SDHOST_TCBCNT_M  (SDHOST_TCBCNT_V << SDHOST_TCBCNT_S)
+#define SDHOST_TCBCNT_V  0xFFFFFFFFU
+#define SDHOST_TCBCNT_S  0
+
+/** SDHOST_TBBCNT_REG register
+ *  Transferred byte count register
+ */
+#define SDHOST_TBBCNT_REG (DR_REG_SDHOST_BASE + 0x60)
+/** SDHOST_TBBCNT : RO; bitpos: [31:0]; default: 0;
+ *  Number of bytes transferred between Host/DMA memory and BIU FIFO.
+ */
+#define SDHOST_TBBCNT    0xFFFFFFFFU
+#define SDHOST_TBBCNT_M  (SDHOST_TBBCNT_V << SDHOST_TBBCNT_S)
+#define SDHOST_TBBCNT_V  0xFFFFFFFFU
+#define SDHOST_TBBCNT_S  0
+
+/** SDHOST_DEBNCE_REG register
+ *  Debounce filter time configuration register
+ */
+#define SDHOST_DEBNCE_REG (DR_REG_SDHOST_BASE + 0x64)
+/** SDHOST_DEBOUNCE_COUNT : R/W; bitpos: [23:0]; default: 0;
+ *  Number of host clocks (clk) used by debounce filter logic. The typical debounce
+ *  time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted
+ *  or removed.
+ */
+#define SDHOST_DEBOUNCE_COUNT    0x00FFFFFFU
+#define SDHOST_DEBOUNCE_COUNT_M  (SDHOST_DEBOUNCE_COUNT_V << SDHOST_DEBOUNCE_COUNT_S)
+#define SDHOST_DEBOUNCE_COUNT_V  0x00FFFFFFU
+#define SDHOST_DEBOUNCE_COUNT_S  0
+
+/** SDHOST_USRID_REG register
+ *  User ID (scratchpad) register
+ */
+#define SDHOST_USRID_REG (DR_REG_SDHOST_BASE + 0x68)
+/** SDHOST_USRID : R/W; bitpos: [31:0]; default: 0;
+ *  User identification register, value set by user. Can also be used as a scratchpad
+ *  register by user.
+ */
+#define SDHOST_USRID    0xFFFFFFFFU
+#define SDHOST_USRID_M  (SDHOST_USRID_V << SDHOST_USRID_S)
+#define SDHOST_USRID_V  0xFFFFFFFFU
+#define SDHOST_USRID_S  0
+
+/** SDHOST_VERID_REG register
+ *  Version ID (scratchpad) register
+ */
+#define SDHOST_VERID_REG (DR_REG_SDHOST_BASE + 0x6c)
+/** SDHOST_VERSIONID_REG : RO; bitpos: [31:0]; default: 1412572938;
+ *  Hardware version register. Can also be read by fireware.
+ */
+#define SDHOST_VERSIONID_REG    0xFFFFFFFFU
+#define SDHOST_VERSIONID_REG_M  (SDHOST_VERSIONID_REG_V << SDHOST_VERSIONID_REG_S)
+#define SDHOST_VERSIONID_REG_V  0xFFFFFFFFU
+#define SDHOST_VERSIONID_REG_S  0
+
+/** SDHOST_HCON_REG register
+ *  Hardware feature register
+ */
+#define SDHOST_HCON_REG (DR_REG_SDHOST_BASE + 0x70)
+/** SDHOST_CARD_TYPE_REG : RO; bitpos: [0]; default: 1;
+ *  Hardware support SDIO and MMC.
+ */
+#define SDHOST_CARD_TYPE_REG    (BIT(0))
+#define SDHOST_CARD_TYPE_REG_M  (SDHOST_CARD_TYPE_REG_V << SDHOST_CARD_TYPE_REG_S)
+#define SDHOST_CARD_TYPE_REG_V  0x00000001U
+#define SDHOST_CARD_TYPE_REG_S  0
+/** SDHOST_CARD_NUM_REG : RO; bitpos: [5:1]; default: 1;
+ *  Support card number is 2.
+ */
+#define SDHOST_CARD_NUM_REG    0x0000001FU
+#define SDHOST_CARD_NUM_REG_M  (SDHOST_CARD_NUM_REG_V << SDHOST_CARD_NUM_REG_S)
+#define SDHOST_CARD_NUM_REG_V  0x0000001FU
+#define SDHOST_CARD_NUM_REG_S  1
+/** SDHOST_BUS_TYPE_REG : RO; bitpos: [6]; default: 1;
+ *  Register config is APB bus.
+ */
+#define SDHOST_BUS_TYPE_REG    (BIT(6))
+#define SDHOST_BUS_TYPE_REG_M  (SDHOST_BUS_TYPE_REG_V << SDHOST_BUS_TYPE_REG_S)
+#define SDHOST_BUS_TYPE_REG_V  0x00000001U
+#define SDHOST_BUS_TYPE_REG_S  6
+/** SDHOST_DATA_WIDTH_REG : RO; bitpos: [9:7]; default: 1;
+ *  Regisger data width is 32.
+ */
+#define SDHOST_DATA_WIDTH_REG    0x00000007U
+#define SDHOST_DATA_WIDTH_REG_M  (SDHOST_DATA_WIDTH_REG_V << SDHOST_DATA_WIDTH_REG_S)
+#define SDHOST_DATA_WIDTH_REG_V  0x00000007U
+#define SDHOST_DATA_WIDTH_REG_S  7
+/** SDHOST_ADDR_WIDTH_REG : RO; bitpos: [15:10]; default: 19;
+ *  Register address width is 32.
+ */
+#define SDHOST_ADDR_WIDTH_REG    0x0000003FU
+#define SDHOST_ADDR_WIDTH_REG_M  (SDHOST_ADDR_WIDTH_REG_V << SDHOST_ADDR_WIDTH_REG_S)
+#define SDHOST_ADDR_WIDTH_REG_V  0x0000003FU
+#define SDHOST_ADDR_WIDTH_REG_S  10
+/** SDHOST_DMA_WIDTH_REG : RO; bitpos: [20:18]; default: 1;
+ *  DMA data width is 32.
+ */
+#define SDHOST_DMA_WIDTH_REG    0x00000007U
+#define SDHOST_DMA_WIDTH_REG_M  (SDHOST_DMA_WIDTH_REG_V << SDHOST_DMA_WIDTH_REG_S)
+#define SDHOST_DMA_WIDTH_REG_V  0x00000007U
+#define SDHOST_DMA_WIDTH_REG_S  18
+/** SDHOST_RAM_INDISE_REG : RO; bitpos: [21]; default: 0;
+ *  Inside RAM in SDMMC module.
+ */
+#define SDHOST_RAM_INDISE_REG    (BIT(21))
+#define SDHOST_RAM_INDISE_REG_M  (SDHOST_RAM_INDISE_REG_V << SDHOST_RAM_INDISE_REG_S)
+#define SDHOST_RAM_INDISE_REG_V  0x00000001U
+#define SDHOST_RAM_INDISE_REG_S  21
+/** SDHOST_HOLD_REG : RO; bitpos: [22]; default: 1;
+ *  Have a hold register in data path .
+ */
+#define SDHOST_HOLD_REG    (BIT(22))
+#define SDHOST_HOLD_REG_M  (SDHOST_HOLD_REG_V << SDHOST_HOLD_REG_S)
+#define SDHOST_HOLD_REG_V  0x00000001U
+#define SDHOST_HOLD_REG_S  22
+/** SDHOST_NUM_CLK_DIV_REG : RO; bitpos: [25:24]; default: 3;
+ *  Have 4 clk divider in design .
+ */
+#define SDHOST_NUM_CLK_DIV_REG    0x00000003U
+#define SDHOST_NUM_CLK_DIV_REG_M  (SDHOST_NUM_CLK_DIV_REG_V << SDHOST_NUM_CLK_DIV_REG_S)
+#define SDHOST_NUM_CLK_DIV_REG_V  0x00000003U
+#define SDHOST_NUM_CLK_DIV_REG_S  24
+
+/** SDHOST_UHS_REG register
+ *  UHS-1 register
+ */
+#define SDHOST_UHS_REG (DR_REG_SDHOST_BASE + 0x74)
+/** SDHOST_DDR_REG : R/W; bitpos: [17:16]; default: 0;
+ *  DDR mode selection,1 bit for each card.
+ *  0-Non-DDR mode.
+ *  1-DDR mode.
+ */
+#define SDHOST_DDR_REG    0x00000003U
+#define SDHOST_DDR_REG_M  (SDHOST_DDR_REG_V << SDHOST_DDR_REG_S)
+#define SDHOST_DDR_REG_V  0x00000003U
+#define SDHOST_DDR_REG_S  16
+
+/** SDHOST_RST_N_REG register
+ *  Card reset register
+ */
+#define SDHOST_RST_N_REG (DR_REG_SDHOST_BASE + 0x78)
+/** SDHOST_CARD_RESET : R/W; bitpos: [1:0]; default: 1;
+ *  Hardware reset.
+ *  1: Active mode;
+ *  0: Reset.
+ *  These bits cause the cards to enter pre-idle state, which requires them to be
+ *  re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0,
+ *  SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1.
+ */
+#define SDHOST_CARD_RESET    0x00000003U
+#define SDHOST_CARD_RESET_M  (SDHOST_CARD_RESET_V << SDHOST_CARD_RESET_S)
+#define SDHOST_CARD_RESET_V  0x00000003U
+#define SDHOST_CARD_RESET_S  0
+
+/** SDHOST_BMOD_REG register
+ *  Burst mode transfer configuration register
+ */
+#define SDHOST_BMOD_REG (DR_REG_SDHOST_BASE + 0x80)
+/** SDHOST_BMOD_SWR : R/W; bitpos: [0]; default: 0;
+ *  Software Reset. When set, the DMA Controller resets all its internal registers. It
+ *  is automatically cleared after one clock cycle.
+ */
+#define SDHOST_BMOD_SWR    (BIT(0))
+#define SDHOST_BMOD_SWR_M  (SDHOST_BMOD_SWR_V << SDHOST_BMOD_SWR_S)
+#define SDHOST_BMOD_SWR_V  0x00000001U
+#define SDHOST_BMOD_SWR_S  0
+/** SDHOST_BMOD_FB : R/W; bitpos: [1]; default: 0;
+ *  Fixed Burst. Controls whether the AHB Master interface performs fixed burst
+ *  transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16
+ *  during start of normal burst transfers. When reset, the AHB will use SINGLE and
+ *  INCR burst transfer operations.
+ */
+#define SDHOST_BMOD_FB    (BIT(1))
+#define SDHOST_BMOD_FB_M  (SDHOST_BMOD_FB_V << SDHOST_BMOD_FB_S)
+#define SDHOST_BMOD_FB_V  0x00000001U
+#define SDHOST_BMOD_FB_S  1
+/** SDHOST_BMOD_DE : R/W; bitpos: [7]; default: 0;
+ *  IDMAC Enable. When set, the IDMAC is enabled.
+ */
+#define SDHOST_BMOD_DE    (BIT(7))
+#define SDHOST_BMOD_DE_M  (SDHOST_BMOD_DE_V << SDHOST_BMOD_DE_S)
+#define SDHOST_BMOD_DE_V  0x00000001U
+#define SDHOST_BMOD_DE_S  7
+/** SDHOST_BMOD_PBL : R/W; bitpos: [10:8]; default: 0;
+ *  Programmable Burst Length. These bits indicate the maximum number of beats to be
+ *  performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always
+ *  attempt to burst as specified in PBL each time it starts a burst transfer on the
+ *  host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value
+ *  is the mirror of MSIZE of FIFOTH register. In order to change this value, write the
+ *  required value to FIFOTH register. This is an encode value as follows:
+ *  000: 1-byte transfer;
+ *  001: 4-byte transfer;
+ *  010: 8-byte transfer;
+ *  011: 16-byte transfer;
+ *  100: 32-byte transfer;
+ *  101: 64-byte transfer;
+ *  110: 128-byte transfer;
+ *  111: 256-byte transfer.
+ *  PBL is a read-only value and is applicable only for data access, it does not apply
+ *  to descriptor access.
+ */
+#define SDHOST_BMOD_PBL    0x00000007U
+#define SDHOST_BMOD_PBL_M  (SDHOST_BMOD_PBL_V << SDHOST_BMOD_PBL_S)
+#define SDHOST_BMOD_PBL_V  0x00000007U
+#define SDHOST_BMOD_PBL_S  8
+
+/** SDHOST_PLDMND_REG register
+ *  Poll demand configuration register
+ */
+#define SDHOST_PLDMND_REG (DR_REG_SDHOST_BASE + 0x84)
+/** SDHOST_PLDMND_PD : WO; bitpos: [31:0]; default: 0;
+ *  Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the
+ *  Suspend state. The host needs to write any value into this register for the IDMAC
+ *  FSM to resume normal descriptor fetch operation. This is a write only .
+ */
+#define SDHOST_PLDMND_PD    0xFFFFFFFFU
+#define SDHOST_PLDMND_PD_M  (SDHOST_PLDMND_PD_V << SDHOST_PLDMND_PD_S)
+#define SDHOST_PLDMND_PD_V  0xFFFFFFFFU
+#define SDHOST_PLDMND_PD_S  0
+
+/** SDHOST_DBADDR_REG register
+ *  Descriptor base address register
+ */
+#define SDHOST_DBADDR_REG (DR_REG_SDHOST_BASE + 0x88)
+/** SDHOST_DBADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Descriptor List. Contains the base address of the First Descriptor. The
+ *  LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence
+ *  these LSB bits may be treated as read-only.
+ */
+#define SDHOST_DBADDR    0xFFFFFFFFU
+#define SDHOST_DBADDR_M  (SDHOST_DBADDR_V << SDHOST_DBADDR_S)
+#define SDHOST_DBADDR_V  0xFFFFFFFFU
+#define SDHOST_DBADDR_S  0
+
+/** SDHOST_IDSTS_REG register
+ *  IDMAC status register
+ */
+#define SDHOST_IDSTS_REG (DR_REG_SDHOST_BASE + 0x8c)
+/** SDHOST_IDSTS_TI : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt. Indicates that data transmission is finished for a descriptor.
+ *  Writing 1 clears this bit.
+ */
+#define SDHOST_IDSTS_TI    (BIT(0))
+#define SDHOST_IDSTS_TI_M  (SDHOST_IDSTS_TI_V << SDHOST_IDSTS_TI_S)
+#define SDHOST_IDSTS_TI_V  0x00000001U
+#define SDHOST_IDSTS_TI_S  0
+/** SDHOST_IDSTS_RI : R/W; bitpos: [1]; default: 0;
+ *  Receive Interrupt. Indicates the completion of data reception for a descriptor.
+ *  Writing 1 clears this bit.
+ */
+#define SDHOST_IDSTS_RI    (BIT(1))
+#define SDHOST_IDSTS_RI_M  (SDHOST_IDSTS_RI_V << SDHOST_IDSTS_RI_S)
+#define SDHOST_IDSTS_RI_V  0x00000001U
+#define SDHOST_IDSTS_RI_S  1
+/** SDHOST_IDSTS_FBE : R/W; bitpos: [2]; default: 0;
+ *  Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) .
+ *  When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this
+ *  bit.
+ */
+#define SDHOST_IDSTS_FBE    (BIT(2))
+#define SDHOST_IDSTS_FBE_M  (SDHOST_IDSTS_FBE_V << SDHOST_IDSTS_FBE_S)
+#define SDHOST_IDSTS_FBE_V  0x00000001U
+#define SDHOST_IDSTS_FBE_S  2
+/** SDHOST_IDSTS_DU : R/W; bitpos: [4]; default: 0;
+ *  Descriptor Unavailable Interrupt. This bit is set when the descriptor is
+ *  unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit.
+ */
+#define SDHOST_IDSTS_DU    (BIT(4))
+#define SDHOST_IDSTS_DU_M  (SDHOST_IDSTS_DU_V << SDHOST_IDSTS_DU_S)
+#define SDHOST_IDSTS_DU_V  0x00000001U
+#define SDHOST_IDSTS_DU_S  4
+/** SDHOST_IDSTS_CES : R/W; bitpos: [5]; default: 0;
+ *  Card Error Summary. Indicates the status of the transaction to/from the card, also
+ *  present in RINTSTS. Indicates the logical OR of the following bits:
+ *  EBE : End Bit Error;
+ *  RTO : Response Timeout/Boot Ack Timeout;
+ *  RCRC : Response CRC;
+ *  SBE : Start Bit Error;
+ *  DRTO : Data Read Timeout/BDS timeout;
+ *  DCRC : Data CRC for Receive;
+ *  RE : Response Error.
+ *  Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting
+ *  of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response
+ *  error.
+ */
+#define SDHOST_IDSTS_CES    (BIT(5))
+#define SDHOST_IDSTS_CES_M  (SDHOST_IDSTS_CES_V << SDHOST_IDSTS_CES_S)
+#define SDHOST_IDSTS_CES_V  0x00000001U
+#define SDHOST_IDSTS_CES_S  5
+/** SDHOST_IDSTS_NIS : R/W; bitpos: [8]; default: 0;
+ *  Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit
+ *  Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This
+ *  is a sticky bit and must be cleared each time a corresponding bit that causes NIS
+ *  to be set is cleared. Writing 1 clears this bit.
+ */
+#define SDHOST_IDSTS_NIS    (BIT(8))
+#define SDHOST_IDSTS_NIS_M  (SDHOST_IDSTS_NIS_V << SDHOST_IDSTS_NIS_S)
+#define SDHOST_IDSTS_NIS_V  0x00000001U
+#define SDHOST_IDSTS_NIS_S  8
+/** SDHOST_IDSTS_AIS : R/W; bitpos: [9]; default: 0;
+ *  Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus
+ *  Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is
+ *  a sticky bit and must be cleared each time a corresponding bit that causes AIS to
+ *  be set is cleared. Writing 1 clears this bit.
+ */
+#define SDHOST_IDSTS_AIS    (BIT(9))
+#define SDHOST_IDSTS_AIS_M  (SDHOST_IDSTS_AIS_V << SDHOST_IDSTS_AIS_S)
+#define SDHOST_IDSTS_AIS_V  0x00000001U
+#define SDHOST_IDSTS_AIS_S  9
+/** SDHOST_IDSTS_FBE_CODE : R/W; bitpos: [12:10]; default: 0;
+ *  Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid
+ *  only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an
+ *  interrupt.
+ *  001: Host Abort received during transmission;
+ *  010: Host Abort received during reception;
+ *  Others: Reserved.
+ */
+#define SDHOST_IDSTS_FBE_CODE    0x00000007U
+#define SDHOST_IDSTS_FBE_CODE_M  (SDHOST_IDSTS_FBE_CODE_V << SDHOST_IDSTS_FBE_CODE_S)
+#define SDHOST_IDSTS_FBE_CODE_V  0x00000007U
+#define SDHOST_IDSTS_FBE_CODE_S  10
+/** SDHOST_IDSTS_FSM : R/W; bitpos: [16:13]; default: 0;
+ *  DMAC FSM present state.
+ *  0: DMA_IDLE (idle state);
+ *  1: DMA_SUSPEND (suspend state);
+ *  2: DESC_RD (descriptor reading state);
+ *  3: DESC_CHK (descriptor checking state);
+ *  4: DMA_RD_REQ_WAIT (read-data request waiting state);
+ *  5: DMA_WR_REQ_WAIT (write-data request waiting state);
+ *  6: DMA_RD (data-read state);
+ *  7: DMA_WR (data-write state);
+ *  8: DESC_CLOSE (descriptor close state).
+ */
+#define SDHOST_IDSTS_FSM    0x0000000FU
+#define SDHOST_IDSTS_FSM_M  (SDHOST_IDSTS_FSM_V << SDHOST_IDSTS_FSM_S)
+#define SDHOST_IDSTS_FSM_V  0x0000000FU
+#define SDHOST_IDSTS_FSM_S  13
+
+/** SDHOST_IDINTEN_REG register
+ *  IDMAC interrupt enable register
+ */
+#define SDHOST_IDINTEN_REG (DR_REG_SDHOST_BASE + 0x90)
+/** SDHOST_IDINTEN_TI : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit
+ *  Interrupt is enabled. When reset, Transmit Interrupt is disabled.
+ */
+#define SDHOST_IDINTEN_TI    (BIT(0))
+#define SDHOST_IDINTEN_TI_M  (SDHOST_IDINTEN_TI_V << SDHOST_IDINTEN_TI_S)
+#define SDHOST_IDINTEN_TI_V  0x00000001U
+#define SDHOST_IDINTEN_TI_S  0
+/** SDHOST_IDINTEN_RI : R/W; bitpos: [1]; default: 0;
+ *  Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
+ *  Interrupt is enabled. When reset, Receive Interrupt is disabled.
+ */
+#define SDHOST_IDINTEN_RI    (BIT(1))
+#define SDHOST_IDINTEN_RI_M  (SDHOST_IDINTEN_RI_V << SDHOST_IDINTEN_RI_S)
+#define SDHOST_IDINTEN_RI_V  0x00000001U
+#define SDHOST_IDINTEN_RI_S  1
+/** SDHOST_IDINTEN_FBE : R/W; bitpos: [2]; default: 0;
+ *  Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal
+ *  Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is
+ *  disabled.
+ */
+#define SDHOST_IDINTEN_FBE    (BIT(2))
+#define SDHOST_IDINTEN_FBE_M  (SDHOST_IDINTEN_FBE_V << SDHOST_IDINTEN_FBE_S)
+#define SDHOST_IDINTEN_FBE_V  0x00000001U
+#define SDHOST_IDINTEN_FBE_S  2
+/** SDHOST_IDINTEN_DU : R/W; bitpos: [4]; default: 0;
+ *  Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
+ *  Enable, the DU interrupt is enabled.
+ */
+#define SDHOST_IDINTEN_DU    (BIT(4))
+#define SDHOST_IDINTEN_DU_M  (SDHOST_IDINTEN_DU_V << SDHOST_IDINTEN_DU_S)
+#define SDHOST_IDINTEN_DU_V  0x00000001U
+#define SDHOST_IDINTEN_DU_S  4
+/** SDHOST_IDINTEN_CES : R/W; bitpos: [5]; default: 0;
+ *  Card Error summary Interrupt Enable. When set, it enables the Card Interrupt
+ *  summary.
+ */
+#define SDHOST_IDINTEN_CES    (BIT(5))
+#define SDHOST_IDINTEN_CES_M  (SDHOST_IDINTEN_CES_V << SDHOST_IDINTEN_CES_S)
+#define SDHOST_IDINTEN_CES_V  0x00000001U
+#define SDHOST_IDINTEN_CES_S  5
+/** SDHOST_IDINTEN_NI : R/W; bitpos: [8]; default: 0;
+ *  Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When
+ *  reset, a normal interrupt is disabled. This bit enables the following bits:
+ *  IDINTEN[0]: Transmit Interrupt;
+ *  IDINTEN[1]: Receive Interrupt.
+ */
+#define SDHOST_IDINTEN_NI    (BIT(8))
+#define SDHOST_IDINTEN_NI_M  (SDHOST_IDINTEN_NI_V << SDHOST_IDINTEN_NI_S)
+#define SDHOST_IDINTEN_NI_V  0x00000001U
+#define SDHOST_IDINTEN_NI_S  8
+/** SDHOST_IDINTEN_AI : R/W; bitpos: [9]; default: 0;
+ *  Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This
+ *  bit enables the following bits:
+ *  IDINTEN[2]: Fatal Bus Error Interrupt;
+ *  IDINTEN[4]: DU Interrupt.
+ */
+#define SDHOST_IDINTEN_AI    (BIT(9))
+#define SDHOST_IDINTEN_AI_M  (SDHOST_IDINTEN_AI_V << SDHOST_IDINTEN_AI_S)
+#define SDHOST_IDINTEN_AI_V  0x00000001U
+#define SDHOST_IDINTEN_AI_S  9
+
+/** SDHOST_DSCADDR_REG register
+ *  Host descriptor address pointer
+ */
+#define SDHOST_DSCADDR_REG (DR_REG_SDHOST_BASE + 0x94)
+/** SDHOST_DSCADDR : RO; bitpos: [31:0]; default: 0;
+ *  Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on
+ *  reset. This register points to the start address of the current descriptor read by
+ *  the IDMAC.
+ */
+#define SDHOST_DSCADDR    0xFFFFFFFFU
+#define SDHOST_DSCADDR_M  (SDHOST_DSCADDR_V << SDHOST_DSCADDR_S)
+#define SDHOST_DSCADDR_V  0xFFFFFFFFU
+#define SDHOST_DSCADDR_S  0
+
+/** SDHOST_BUFADDR_REG register
+ *  Host buffer address pointer register
+ */
+#define SDHOST_BUFADDR_REG (DR_REG_SDHOST_BASE + 0x98)
+/** SDHOST_BUFADDR : RO; bitpos: [31:0]; default: 0;
+ *  Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
+ *  reset. This register points to the current Data Buffer Address being accessed by
+ *  the IDMAC.
+ */
+#define SDHOST_BUFADDR    0xFFFFFFFFU
+#define SDHOST_BUFADDR_M  (SDHOST_BUFADDR_V << SDHOST_BUFADDR_S)
+#define SDHOST_BUFADDR_V  0xFFFFFFFFU
+#define SDHOST_BUFADDR_S  0
+
+/** SDHOST_CARDTHRCTL_REG register
+ *  Card Threshold Control register
+ */
+#define SDHOST_CARDTHRCTL_REG (DR_REG_SDHOST_BASE + 0x100)
+/** SDHOST_CARDRDTHREN_REG : R/W; bitpos: [0]; default: 0;
+ *  Card read threshold enable.
+ *  1'b0-Card read threshold disabled.
+ *  1'b1-Card read threshold enabled.
+ */
+#define SDHOST_CARDRDTHREN_REG    (BIT(0))
+#define SDHOST_CARDRDTHREN_REG_M  (SDHOST_CARDRDTHREN_REG_V << SDHOST_CARDRDTHREN_REG_S)
+#define SDHOST_CARDRDTHREN_REG_V  0x00000001U
+#define SDHOST_CARDRDTHREN_REG_S  0
+/** SDHOST_CARDCLRINTEN_REG : R/W; bitpos: [1]; default: 0;
+ *  Busy clear interrupt generation:
+ *  1'b0-Busy clear interrypt disabled.
+ *  1'b1-Busy clear interrypt enabled.
+ */
+#define SDHOST_CARDCLRINTEN_REG    (BIT(1))
+#define SDHOST_CARDCLRINTEN_REG_M  (SDHOST_CARDCLRINTEN_REG_V << SDHOST_CARDCLRINTEN_REG_S)
+#define SDHOST_CARDCLRINTEN_REG_V  0x00000001U
+#define SDHOST_CARDCLRINTEN_REG_S  1
+/** SDHOST_CARDWRTHREN_REG : R/W; bitpos: [2]; default: 0;
+ *  Applicable when HS400 mode is enabled.
+ *  1'b0-Card write Threshold disabled.
+ *  1'b1-Card write Threshold enabled.
+ */
+#define SDHOST_CARDWRTHREN_REG    (BIT(2))
+#define SDHOST_CARDWRTHREN_REG_M  (SDHOST_CARDWRTHREN_REG_V << SDHOST_CARDWRTHREN_REG_S)
+#define SDHOST_CARDWRTHREN_REG_V  0x00000001U
+#define SDHOST_CARDWRTHREN_REG_S  2
+/** SDHOST_CARDTHRESHOLD_REG : R/W; bitpos: [31:16]; default: 0;
+ *  The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG
+ *  is set to 1 or SDHOST_CARDRDTHREN_REG set to 1.
+ */
+#define SDHOST_CARDTHRESHOLD_REG    0x0000FFFFU
+#define SDHOST_CARDTHRESHOLD_REG_M  (SDHOST_CARDTHRESHOLD_REG_V << SDHOST_CARDTHRESHOLD_REG_S)
+#define SDHOST_CARDTHRESHOLD_REG_V  0x0000FFFFU
+#define SDHOST_CARDTHRESHOLD_REG_S  16
+
+/** SDHOST_EMMCDDR_REG register
+ *  eMMC DDR register
+ */
+#define SDHOST_EMMCDDR_REG (DR_REG_SDHOST_BASE + 0x10c)
+/** SDHOST_HALFSTARTBIT_REG : R/W; bitpos: [1:0]; default: 0;
+ *  Control for start bit detection mechanism duration of start bit.Each bit refers to
+ *  one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For
+ *  eMMC4.5,start bit can be:
+ *  1'b0-Full cycle.
+ *  1'b1-less than one full cycle.
+ */
+#define SDHOST_HALFSTARTBIT_REG    0x00000003U
+#define SDHOST_HALFSTARTBIT_REG_M  (SDHOST_HALFSTARTBIT_REG_V << SDHOST_HALFSTARTBIT_REG_S)
+#define SDHOST_HALFSTARTBIT_REG_V  0x00000003U
+#define SDHOST_HALFSTARTBIT_REG_S  0
+/** SDHOST_HS400_MODE_REG : R/W; bitpos: [31]; default: 0;
+ *  Set 1 to enable HS400 mode.
+ */
+#define SDHOST_HS400_MODE_REG    (BIT(31))
+#define SDHOST_HS400_MODE_REG_M  (SDHOST_HS400_MODE_REG_V << SDHOST_HS400_MODE_REG_S)
+#define SDHOST_HS400_MODE_REG_V  0x00000001U
+#define SDHOST_HS400_MODE_REG_S  31
+
+/** SDHOST_ENSHIFT_REG register
+ *  Enable Phase Shift register
+ */
+#define SDHOST_ENSHIFT_REG (DR_REG_SDHOST_BASE + 0x110)
+/** SDHOST_ENABLE_SHIFT_REG : R/W; bitpos: [3:0]; default: 0;
+ *  Control for the amount of phase shift provided on the default enables in the
+ *  design.Two bits assigned for each card.
+ *  2'b00-Default phase shift.
+ *  2'b01-Enables shifted to next immediate positive edge.
+ *  2'b10-Enables shifted to next immediate negative edge.
+ *  2'b11-Reserved.
+ */
+#define SDHOST_ENABLE_SHIFT_REG    0x0000000FU
+#define SDHOST_ENABLE_SHIFT_REG_M  (SDHOST_ENABLE_SHIFT_REG_V << SDHOST_ENABLE_SHIFT_REG_S)
+#define SDHOST_ENABLE_SHIFT_REG_V  0x0000000FU
+#define SDHOST_ENABLE_SHIFT_REG_S  0
+
+/** SDHOST_BUFFIFO_REG register
+ *  CPU write and read transmit data by FIFO
+ */
+#define SDHOST_BUFFIFO_REG (DR_REG_SDHOST_BASE + 0x200)
+/** SDHOST_BUFFIFO : R/W; bitpos: [31:0]; default: 0;
+ *  CPU write and read transmit data by FIFO. This register points to the current Data
+ *  FIFO .
+ */
+#define SDHOST_BUFFIFO    0xFFFFFFFFU
+#define SDHOST_BUFFIFO_M  (SDHOST_BUFFIFO_V << SDHOST_BUFFIFO_S)
+#define SDHOST_BUFFIFO_V  0xFFFFFFFFU
+#define SDHOST_BUFFIFO_S  0
+
+/** SDHOST_CLK_EDGE_SEL_REG register
+ *  SDIO control register.
+ */
+#define SDHOST_CLK_EDGE_SEL_REG (DR_REG_SDHOST_BASE + 0x800)
+/** SDHOST_CCLKIN_EDGE_DRV_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  It's used to select the clock phase of the output signal from phase 0, phase 90,
+ *  phase 180, phase 270.
+ */
+#define SDHOST_CCLKIN_EDGE_DRV_SEL    0x00000007U
+#define SDHOST_CCLKIN_EDGE_DRV_SEL_M  (SDHOST_CCLKIN_EDGE_DRV_SEL_V << SDHOST_CCLKIN_EDGE_DRV_SEL_S)
+#define SDHOST_CCLKIN_EDGE_DRV_SEL_V  0x00000007U
+#define SDHOST_CCLKIN_EDGE_DRV_SEL_S  0
+/** SDHOST_CCLKIN_EDGE_SAM_SEL : R/W; bitpos: [5:3]; default: 0;
+ *  It's used to select the clock phase of the input signal from phase 0, phase 90,
+ *  phase 180, phase 270.
+ */
+#define SDHOST_CCLKIN_EDGE_SAM_SEL    0x00000007U
+#define SDHOST_CCLKIN_EDGE_SAM_SEL_M  (SDHOST_CCLKIN_EDGE_SAM_SEL_V << SDHOST_CCLKIN_EDGE_SAM_SEL_S)
+#define SDHOST_CCLKIN_EDGE_SAM_SEL_V  0x00000007U
+#define SDHOST_CCLKIN_EDGE_SAM_SEL_S  3
+/** SDHOST_CCLKIN_EDGE_SLF_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  It's used to select the clock phase of the internal signal from phase 0, phase 90,
+ *  phase 180, phase 270.
+ */
+#define SDHOST_CCLKIN_EDGE_SLF_SEL    0x00000007U
+#define SDHOST_CCLKIN_EDGE_SLF_SEL_M  (SDHOST_CCLKIN_EDGE_SLF_SEL_V << SDHOST_CCLKIN_EDGE_SLF_SEL_S)
+#define SDHOST_CCLKIN_EDGE_SLF_SEL_V  0x00000007U
+#define SDHOST_CCLKIN_EDGE_SLF_SEL_S  6
+/** SDHOST_CCLLKIN_EDGE_H : R/W; bitpos: [12:9]; default: 1;
+ *  The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L.
+ */
+#define SDHOST_CCLLKIN_EDGE_H    0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_H_M  (SDHOST_CCLLKIN_EDGE_H_V << SDHOST_CCLLKIN_EDGE_H_S)
+#define SDHOST_CCLLKIN_EDGE_H_V  0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_H_S  9
+/** SDHOST_CCLLKIN_EDGE_L : R/W; bitpos: [16:13]; default: 0;
+ *  The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H.
+ */
+#define SDHOST_CCLLKIN_EDGE_L    0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_L_M  (SDHOST_CCLLKIN_EDGE_L_V << SDHOST_CCLLKIN_EDGE_L_S)
+#define SDHOST_CCLLKIN_EDGE_L_V  0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_L_S  13
+/** SDHOST_CCLLKIN_EDGE_N : R/W; bitpos: [20:17]; default: 1;
+ *  The clock division of cclk_in.
+ */
+#define SDHOST_CCLLKIN_EDGE_N    0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_N_M  (SDHOST_CCLLKIN_EDGE_N_V << SDHOST_CCLLKIN_EDGE_N_S)
+#define SDHOST_CCLLKIN_EDGE_N_V  0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_N_S  17
+/** SDHOST_ESDIO_MODE : R/W; bitpos: [21]; default: 0;
+ *  Enable esdio mode.
+ */
+#define SDHOST_ESDIO_MODE    (BIT(21))
+#define SDHOST_ESDIO_MODE_M  (SDHOST_ESDIO_MODE_V << SDHOST_ESDIO_MODE_S)
+#define SDHOST_ESDIO_MODE_V  0x00000001U
+#define SDHOST_ESDIO_MODE_S  21
+/** SDHOST_ESD_MODE : R/W; bitpos: [22]; default: 0;
+ *  Enable esd mode.
+ */
+#define SDHOST_ESD_MODE    (BIT(22))
+#define SDHOST_ESD_MODE_M  (SDHOST_ESD_MODE_V << SDHOST_ESD_MODE_S)
+#define SDHOST_ESD_MODE_V  0x00000001U
+#define SDHOST_ESD_MODE_S  22
+/** SDHOST_CCLK_EN : R/W; bitpos: [23]; default: 1;
+ *  Sdio clock enable.
+ */
+#define SDHOST_CCLK_EN    (BIT(23))
+#define SDHOST_CCLK_EN_M  (SDHOST_CCLK_EN_V << SDHOST_CCLK_EN_S)
+#define SDHOST_CCLK_EN_V  0x00000001U
+#define SDHOST_CCLK_EN_S  23
+/** SDHOST_ULTRA_HIGH_SPEED_MODE : R/W; bitpos: [24]; default: 0;
+ *  Enable ultra high speed mode, use dll to generate clk.
+ */
+#define SDHOST_ULTRA_HIGH_SPEED_MODE    (BIT(24))
+#define SDHOST_ULTRA_HIGH_SPEED_MODE_M  (SDHOST_ULTRA_HIGH_SPEED_MODE_V << SDHOST_ULTRA_HIGH_SPEED_MODE_S)
+#define SDHOST_ULTRA_HIGH_SPEED_MODE_V  0x00000001U
+#define SDHOST_ULTRA_HIGH_SPEED_MODE_S  24
+
+/** SDHOST_RAW_INTS_REG register
+ *  SDIO raw ints register.
+ */
+#define SDHOST_RAW_INTS_REG (DR_REG_SDHOST_BASE + 0x804)
+/** SDHOST_RAW_INTS : RO; bitpos: [31:0]; default: 0;
+ *  It indicates raw ints.
+ */
+#define SDHOST_RAW_INTS    0xFFFFFFFFU
+#define SDHOST_RAW_INTS_M  (SDHOST_RAW_INTS_V << SDHOST_RAW_INTS_S)
+#define SDHOST_RAW_INTS_V  0xFFFFFFFFU
+#define SDHOST_RAW_INTS_S  0
+
+/** SDHOST_DLL_CLK_CONF_REG register
+ *  SDIO DLL clock control register.
+ */
+#define SDHOST_DLL_CLK_CONF_REG (DR_REG_SDHOST_BASE + 0x808)
+/** SDHOST_DLL_CCLK_IN_SLF_EN : R/W; bitpos: [0]; default: 0;
+ *  Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_SLF_EN    (BIT(0))
+#define SDHOST_DLL_CCLK_IN_SLF_EN_M  (SDHOST_DLL_CCLK_IN_SLF_EN_V << SDHOST_DLL_CCLK_IN_SLF_EN_S)
+#define SDHOST_DLL_CCLK_IN_SLF_EN_V  0x00000001U
+#define SDHOST_DLL_CCLK_IN_SLF_EN_S  0
+/** SDHOST_DLL_CCLK_IN_DRV_EN : R/W; bitpos: [1]; default: 0;
+ *  Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_DRV_EN    (BIT(1))
+#define SDHOST_DLL_CCLK_IN_DRV_EN_M  (SDHOST_DLL_CCLK_IN_DRV_EN_V << SDHOST_DLL_CCLK_IN_DRV_EN_S)
+#define SDHOST_DLL_CCLK_IN_DRV_EN_V  0x00000001U
+#define SDHOST_DLL_CCLK_IN_DRV_EN_S  1
+/** SDHOST_DLL_CCLK_IN_SAM_EN : R/W; bitpos: [2]; default: 0;
+ *  Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_SAM_EN    (BIT(2))
+#define SDHOST_DLL_CCLK_IN_SAM_EN_M  (SDHOST_DLL_CCLK_IN_SAM_EN_V << SDHOST_DLL_CCLK_IN_SAM_EN_S)
+#define SDHOST_DLL_CCLK_IN_SAM_EN_V  0x00000001U
+#define SDHOST_DLL_CCLK_IN_SAM_EN_S  2
+/** SDHOST_DLL_CCLK_IN_SLF_PHASE : R/W; bitpos: [8:3]; default: 0;
+ *  It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_SLF_PHASE    0x0000003FU
+#define SDHOST_DLL_CCLK_IN_SLF_PHASE_M  (SDHOST_DLL_CCLK_IN_SLF_PHASE_V << SDHOST_DLL_CCLK_IN_SLF_PHASE_S)
+#define SDHOST_DLL_CCLK_IN_SLF_PHASE_V  0x0000003FU
+#define SDHOST_DLL_CCLK_IN_SLF_PHASE_S  3
+/** SDHOST_DLL_CCLK_IN_DRV_PHASE : R/W; bitpos: [14:9]; default: 0;
+ *  It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_DRV_PHASE    0x0000003FU
+#define SDHOST_DLL_CCLK_IN_DRV_PHASE_M  (SDHOST_DLL_CCLK_IN_DRV_PHASE_V << SDHOST_DLL_CCLK_IN_DRV_PHASE_S)
+#define SDHOST_DLL_CCLK_IN_DRV_PHASE_V  0x0000003FU
+#define SDHOST_DLL_CCLK_IN_DRV_PHASE_S  9
+/** SDHOST_DLL_CCLK_IN_SAM_PHASE : R/W; bitpos: [20:15]; default: 0;
+ *  It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_SAM_PHASE    0x0000003FU
+#define SDHOST_DLL_CCLK_IN_SAM_PHASE_M  (SDHOST_DLL_CCLK_IN_SAM_PHASE_V << SDHOST_DLL_CCLK_IN_SAM_PHASE_S)
+#define SDHOST_DLL_CCLK_IN_SAM_PHASE_V  0x0000003FU
+#define SDHOST_DLL_CCLK_IN_SAM_PHASE_S  15
+
+/** SDHOST_DLL_CONF_REG register
+ *  SDIO DLL configuration register.
+ */
+#define SDHOST_DLL_CONF_REG (DR_REG_SDHOST_BASE + 0x80c)
+/** SDHOST_DLL_CAL_STOP : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to stop calibration.
+ */
+#define SDHOST_DLL_CAL_STOP    (BIT(0))
+#define SDHOST_DLL_CAL_STOP_M  (SDHOST_DLL_CAL_STOP_V << SDHOST_DLL_CAL_STOP_S)
+#define SDHOST_DLL_CAL_STOP_V  0x00000001U
+#define SDHOST_DLL_CAL_STOP_S  0
+/** SDHOST_DLL_CAL_END : RO; bitpos: [1]; default: 0;
+ *  1 means calibration finished.
+ */
+#define SDHOST_DLL_CAL_END    (BIT(1))
+#define SDHOST_DLL_CAL_END_M  (SDHOST_DLL_CAL_END_V << SDHOST_DLL_CAL_END_S)
+#define SDHOST_DLL_CAL_END_V  0x00000001U
+#define SDHOST_DLL_CAL_END_S  1
+
+#define SDMMC_INTMASK_IO_SLOT1  BIT(17)
+#define SDMMC_INTMASK_IO_SLOT0  BIT(16)
+#define SDMMC_INTMASK_EBE       BIT(15)
+#define SDMMC_INTMASK_ACD       BIT(14)
+#define SDMMC_INTMASK_SBE       BIT(13)
+#define SDMMC_INTMASK_HLE       BIT(12)
+#define SDMMC_INTMASK_FRUN      BIT(11)
+#define SDMMC_INTMASK_HTO       BIT(10)
+#define SDMMC_INTMASK_VOLT_SW   SDMMC_INTMASK_HTO
+#define SDMMC_INTMASK_DTO       BIT(9)
+#define SDMMC_INTMASK_RTO       BIT(8)
+#define SDMMC_INTMASK_DCRC      BIT(7)
+#define SDMMC_INTMASK_RCRC      BIT(6)
+#define SDMMC_INTMASK_RXDR      BIT(5)
+#define SDMMC_INTMASK_TXDR      BIT(4)
+#define SDMMC_INTMASK_DATA_OVER BIT(3)
+#define SDMMC_INTMASK_CMD_DONE  BIT(2)
+#define SDMMC_INTMASK_RESP_ERR  BIT(1)
+#define SDMMC_INTMASK_CD        BIT(0)
+
+#define SDMMC_IDMAC_INTMASK_AI  BIT(9)
+#define SDMMC_IDMAC_INTMASK_NI  BIT(8)
+#define SDMMC_IDMAC_INTMASK_CES BIT(5)
+#define SDMMC_IDMAC_INTMASK_DU  BIT(4)
+#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
+#define SDMMC_IDMAC_INTMASK_RI  BIT(1)
+#define SDMMC_IDMAC_INTMASK_TI  BIT(0)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/sdmmc_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/sdmmc_struct.h
new file mode 100644
index 0000000000..fded1e9eb1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/sdmmc_struct.h
@@ -0,0 +1,1495 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct sdmmc_desc_s {
+    struct {
+        uint32_t reserved1: 1;
+        uint32_t disable_int_on_completion: 1;
+        uint32_t last_descriptor: 1;
+        uint32_t first_descriptor: 1;
+        uint32_t second_address_chained: 1;
+        uint32_t end_of_ring: 1;
+        uint32_t reserved2: 24;
+        uint32_t card_error_summary: 1;
+        uint32_t owned_by_idmac: 1;
+    };
+    struct {
+        uint32_t buffer1_size: 13;
+        uint32_t buffer2_size: 13;
+        uint32_t reserved3: 6;
+    };
+    void* buffer1_ptr;
+    union {
+        void* buffer2_ptr;
+        void* next_desc_ptr;
+    };
+    /**
+     * These `reserved[12]` are for cache alignment. On P4, L1 Cache alignment is 64B.
+     * For those who want to access the DMA descriptor in a non-cacheable way, you can
+     * consider remove these `reserved[12]` bytes.
+     */
+    uint32_t reserved[12];
+} sdmmc_desc_t;
+
+#define SDMMC_DMA_MAX_BUF_LEN 4096
+
+#ifndef __cplusplus
+_Static_assert(sizeof(sdmmc_desc_t) == 64, "invalid size of sdmmc_desc_t structure");
+#endif
+
+/** Group: Control register */
+/** Type of ctrl register
+ *  Control register
+ */
+typedef union {
+    struct {
+        /** controller_reset : R/W; bitpos: [0]; default: 0;
+         *  To reset controller, firmware should set this bit. This bit is auto-cleared after
+         *  two AHB and two sdhost_cclk_in clock cycles.
+         */
+        uint32_t controller_reset:1;
+        /** fifo_reset : R/W; bitpos: [1]; default: 0;
+         *  To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after
+         *  completion of reset operation.
+         *  Note: FIFO pointers will be out of reset after 2 cycles of system clocks in
+         *  addition to synchronization delay (2 cycles of card clock), after the fifo_reset is
+         *  cleared.
+         */
+        uint32_t fifo_reset:1;
+        /** dma_reset : R/W; bitpos: [2]; default: 0;
+         *  To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared
+         *  after two AHB clocks.
+         */
+        uint32_t dma_reset:1;
+        uint32_t reserved_3:1;
+        /** int_enable : R/W; bitpos: [4]; default: 0;
+         *  Global interrupt enable/disable bit. 0: Disable; 1: Enable.
+         */
+        uint32_t int_enable:1;
+        uint32_t dma_enable:1;
+        /** read_wait : R/W; bitpos: [6]; default: 0;
+         *  For sending read-wait to SDIO cards.
+         */
+        uint32_t read_wait:1;
+        /** send_irq_response : R/W; bitpos: [7]; default: 0;
+         *  Bit automatically clears once response is sent. To wait for MMC card interrupts,
+         *  host issues CMD40 and waits for interrupt response from MMC card(s). In the
+         *  meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this
+         *  bit, at which time SD/MMC command state-machine sends CMD40 response on bus and
+         *  returns to idle state.
+         */
+        uint32_t send_irq_response:1;
+        /** abort_read_data : R/W; bitpos: [8]; default: 0;
+         *  After a suspend-command is issued during a read-operation, software polls the card
+         *  to find when the suspend-event occurred. Once the suspend-event has occurred,
+         *  software sets the bit which will reset the data state machine that is waiting for
+         *  the next block of data. This bit is automatically cleared once the data state
+         *  machine is reset to idle.
+         */
+        uint32_t abort_read_data:1;
+        /** send_ccsd : R/W; bitpos: [9]; default: 0;
+         *  When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if
+         *  the current command is expecting CCS (that is, RW_BLK), and if interrupts are
+         *  enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC
+         *  automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD)
+         *  bit  in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host,
+         *  in case the Command Done interrupt is not masked.
+         *  NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive
+         *  the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may
+         *  be sent to the CE-ATA device, even if the device has signalled CCS.
+         */
+        uint32_t send_ccsd:1;
+        /** send_auto_stop_ccsd : R/W; bitpos: [10]; default: 0;
+         *  Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together;
+         *  SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set,
+         *  SD/MMC automatically sends an internally-generated STOP command (CMD12) to the
+         *  CE-ATA device. After sending this internally-generated STOP command, the Auto
+         *  Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated
+         *  for the host, in case the ACD interrupt is not masked. After sending the Command
+         *  Completion Signal Disable (CCSD), SD/MMC automatically clears the
+         *  SDHOST_SEND_AUTO_STOP_CCSD bit.
+         */
+        uint32_t send_auto_stop_ccsd:1;
+        /** ceata_device_interrupt_status : R/W; bitpos: [11]; default: 0;
+         *  Software should appropriately write to this bit after the power-on reset or any
+         *  other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is
+         *  usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt,
+         *  then software should set this bit.
+         */
+        uint32_t ceata_device_interrupt_status:1;
+        uint32_t reserved2:4;
+        uint32_t card_voltage_a:4;
+        uint32_t card_voltage_b:4;
+        uint32_t enable_od_pullup:1;
+        uint32_t use_internal_dma:1;
+        uint32_t reserved3:6;
+    };
+    uint32_t val;
+} sdhost_ctrl_reg_t;
+
+
+/** Group: Clock divider configuration register */
+/** Type of clkdiv register
+ *  Clock divider configuration register
+ */
+typedef union {
+    struct {
+        /** clk_divider0 : R/W; bitpos: [7:0]; default: 0;
+         *  Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+         *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+         *  means divided by 2*255 = 510, and so on.
+         */
+        uint32_t clk_divider0:8;
+        /** clk_divider1 : R/W; bitpos: [15:8]; default: 0;
+         *  Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+         *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+         *  means divided by 2*255 = 510, and so on.
+         */
+        uint32_t clk_divider1:8;
+        /** clk_divider2 : R/W; bitpos: [23:16]; default: 0;
+         *  Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+         *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+         *  means divided by 2*255 = 510, and so on.
+         */
+        uint32_t clk_divider2:8;
+        /** clk_divider3 : R/W; bitpos: [31:24]; default: 0;
+         *  Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+         *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+         *  means divided by 2*255 = 510, and so on.
+         */
+        uint32_t clk_divider3:8;
+    };
+    uint32_t val;
+} sdhost_clkdiv_reg_t;
+
+
+/** Group: Clock source selection register */
+/** Type of clksrc register
+ *  Clock source selection register
+ */
+typedef union {
+    struct {
+        /** clksrc_reg : R/W; bitpos: [3:0]; default: 0;
+         *  Clock divider source for two SD cards is supported. Each card has two bits assigned
+         *  to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for
+         *  card 1. Card 0 maps and internally routes clock divider[0:3] outputs to
+         *  cclk_out[1:0] pins, depending on bit value.
+         *  00 : Clock divider 0;
+         *  01 : Clock divider 1;
+         *  10 : Clock divider 2;
+         *  11 : Clock divider 3.
+         */
+        uint32_t card0:2;
+        uint32_t card1:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} sdhost_clksrc_reg_t;
+
+
+/** Group: Clock enable register */
+/** Type of clkena register
+ *  Clock enable register
+ */
+typedef union {
+    struct {
+        /** cclk_enable : R/W; bitpos: [1:0]; default: 0;
+         *  Clock-enable control for two SD card clocks and one MMC card clock is supported.
+         *  One bit per card.
+         *  0: Clock disabled;
+         *  1: Clock enabled.
+         */
+        uint32_t cclk_enable:2;
+        uint32_t reserved_2:14;
+        /** lp_enable : R/W; bitpos: [17:16]; default: 0;
+         *  Disable clock when the card is in IDLE state. One bit per card.
+         *  0: clock disabled;
+         *  1: clock enabled.
+         */
+        uint32_t lp_enable:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_clkena_reg_t;
+
+
+/** Group: Data and response timeout configuration register */
+/** Type of tmout register
+ *  Data and response timeout configuration register
+ */
+typedef union {
+    struct {
+        /** response_timeout : R/W; bitpos: [7:0]; default: 64;
+         *  Response timeout value. Value is specified in terms of number of card output
+         *  clocks, i.e., sdhost_cclk_out.
+         */
+        uint32_t response_timeout:8;
+        /** data_timeout : R/W; bitpos: [31:8]; default: 16777215;
+         *  Value for card data read timeout. This value is also used for data starvation by
+         *  host timeout. The timeout counter is started only after the card clock is stopped.
+         *  This value is specified in number of card output clocks, i.e. sdhost_cclk_out of
+         *  the selected card.
+         *  NOTE: The software timer should be used if the timeout value is in the order of 100
+         *  ms. In this case, read data timeout interrupt needs to be disabled.
+         */
+        uint32_t data_timeout:24;
+    };
+    uint32_t val;
+} sdhost_tmout_reg_t;
+
+
+/** Group: Card bus width configuration register */
+/** Type of ctype register
+ *  Card bus width configuration register
+ */
+typedef union {
+    struct {
+        /** card_width : R/W; bitpos: [1:0]; default: 0;
+         *  One bit per card indicates if card is 1-bit or 4-bit mode.
+         *  0: 1-bit mode;
+         *  1: 4-bit mode.
+         *  Bit[1:0] correspond to card[1:0] respectively.
+         */
+        uint32_t card_width:2;
+        uint32_t reserved_2:14;
+        /** card_width_8 : R/W; bitpos: [17:16]; default: 0;
+         *  One bit per card indicates if card is in 8-bit mode.
+         *  0: Non 8-bit mode;
+         *  1: 8-bit mode.
+         *  Bit[17:16] correspond to card[1:0] respectively.
+         */
+        uint32_t card_width_8:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_ctype_reg_t;
+
+
+/** Group: Card data block size configuration register */
+/** Type of blksiz register
+ *  Card data block size configuration register
+ */
+typedef union {
+    struct {
+        /** block_size : R/W; bitpos: [15:0]; default: 512;
+         *  Block size.
+         */
+        uint32_t block_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} sdhost_blksiz_reg_t;
+
+
+/** Group: Data transfer length configuration register */
+/** Type of bytcnt register
+ *  Data transfer length configuration register
+ */
+typedef union {
+    struct {
+        /** byte_count : R/W; bitpos: [31:0]; default: 512;
+         *  Number of bytes to be transferred, should be an integral multiple of Block Size for
+         *  block transfers. For data transfers of undefined byte lengths, byte count should be
+         *  set to 0. When byte count is set to 0, it is the responsibility of host to
+         *  explicitly send stop/abort command to terminate data transfer.
+         */
+        uint32_t byte_count:32;
+    };
+    uint32_t val;
+} sdhost_bytcnt_reg_t;
+
+
+/** Group: SDIO interrupt mask register */
+/** Type of intmask register
+ *  SDIO interrupt mask register
+ */
+typedef union {
+    struct {
+        /** int_mask : R/W; bitpos: [15:0]; default: 0;
+         *  These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a
+         *  value of 1 enables the interrupt.
+         *  Bit 15 (EBE): End-bit error/no CRC error;
+         *  Bit 14 (ACD): Auto command done;
+         *  Bit 13 (SBE/BCI): Rx Start Bit Error;
+         *  Bit 12 (HLE): Hardware locked write error;
+         *  Bit 11 (FRUN): FIFO underrun/overrun error;
+         *  Bit 10 (HTO): Data starvation-by-host timeout;
+         *  Bit 9 (DRTO): Data read timeout;
+         *  Bit 8 (RTO): Response timeout;
+         *  Bit 7 (DCRC): Data CRC error;
+         *  Bit 6 (RCRC): Response CRC error;
+         *  Bit 5 (RXDR): Receive FIFO data request;
+         *  Bit 4 (TXDR): Transmit FIFO data request;
+         *  Bit 3 (DTO): Data transfer over;
+         *  Bit 2 (CD): Command done;
+         *  Bit 1 (RE): Response error;
+         *  Bit 0 (CD): Card detect.
+         */
+        uint32_t int_mask:16;
+        /** sdio_int_mask : R/W; bitpos: [17:16]; default: 0;
+         *  SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0]
+         *  respectively. When masked, SDIO interrupt detection for that card is disabled. 0
+         *  masks an interrupt, and 1 enables an interrupt.
+         */
+        uint32_t sdio_int_mask:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_intmask_reg_t;
+
+
+/** Group: Command and boot configuration register */
+/** Type of cmd register
+ *  Command and boot configuration register
+ */
+typedef union {
+    struct {
+        /** cmd_index : R/W; bitpos: [5:0]; default: 0;
+         *  Command index.
+         */
+        uint32_t cmd_index:6;
+        /** response_expect : R/W; bitpos: [6]; default: 0;
+         *  0: No response expected from card; 1: Response expected from card.
+         */
+        uint32_t response_expect:1;
+        /** response_long : R/W; bitpos: [7]; default: 0;
+         *  0: Short response expected from card; 1: Long response expected from card.
+         */
+        uint32_t response_long:1;
+        /** check_response_crc : R/W; bitpos: [8]; default: 0;
+         *  0: Do not check; 1: Check response CRC.
+         *  Some of command responses do not return valid CRC bits. Software should disable CRC
+         *  checks for those commands in order to disable CRC checking by controller.
+         */
+        uint32_t check_response_crc:1;
+        /** data_expected : R/W; bitpos: [9]; default: 0;
+         *  0: No data transfer expected; 1: Data transfer expected.
+         */
+        uint32_t data_expected:1;
+        /** rw : R/W; bitpos: [10]; default: 0;
+         *  0: Read from card; 1: Write to card.
+         *  Don't care if no data is expected from card.
+         */
+        uint32_t rw:1;
+        /** transfer_mode : R/W; bitpos: [11]; default: 0;
+         *  0: Block data transfer command; 1: Stream data transfer command.
+         *  Don't care if no data expected.
+         */
+        uint32_t transfer_mode:1;
+        /** send_auto_stop : R/W; bitpos: [12]; default: 0;
+         *  0: No stop command is sent at the end of data transfer; 1: Send stop command at the
+         *  end of data transfer.
+         */
+        uint32_t send_auto_stop:1;
+        /** wait_complete : R/W; bitpos: [13]; default: 0;
+         *  0: Send command at once, even if previous data transfer has not completed; 1: Wait
+         *  for previous data transfer to complete before sending Command.
+         *  The SDHOST_WAIT_COMPLETE] = 0 option is typically used to query status of
+         *  card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr
+         *  should be same as in previous command.
+         */
+        uint32_t wait_complete:1;
+        /** stop_abort_cmd : R/W; bitpos: [14]; default: 0;
+         *  0: Neither stop nor abort command can stop current data transfer. If abort is sent
+         *  to function-number currently selected or not in data-transfer mode, then bit should
+         *  be set to 0; 1: Stop or abort command intended to stop current data transfer in
+         *  progress.
+         *  When open-ended or predefined data transfer is in progress, and host issues stop or
+         *  abort command to stop data transfer, bit should be set so that command/data
+         *  state-machines of CIU can return correctly to idle state.
+         */
+        uint32_t stop_abort_cmd:1;
+        /** send_init : R/W; bitpos: [15]; default: 0;
+         *  0: Do not send initialization sequence (80 clocks of 1) before sending this
+         *  command; 1: Send initialization sequence before sending this command.
+         *  After powered on, 80 clocks must be sent to card for initialization before sending
+         *  any commands to card. Bit should be set while sending first command to card so that
+         *  controller will initialize clocks before sending command to card.
+         */
+        uint32_t send_init:1;
+        /** card_num : R/W; bitpos: [20:16]; default: 0;
+         *  Card number in use. Represents physical slot number of card being accessed. In
+         *  SD-only mode, up to two cards are supported.
+         */
+        uint32_t card_num:5;
+        /** update_clk_reg : R/W; bitpos: [21]; default: 0;
+         *  0: Normal command sequence; 1: Do not send commands, just update clock register
+         *  value into card clock domain.
+         *  Following register values are transferred into card clock domain: CLKDIV, CLRSRC,
+         *  and CLKENA.
+         *  Changes card clocks (change frequency, truncate off or on, and set low-frequency
+         *  mode). This is provided in order to change clock frequency or stop clock without
+         *  having to send command to cards. During normal command sequence, when
+         *  sdhost_update_clock_registers_only = 0, following control registers are transferred
+         *  from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new
+         *  register values for new command sequence to card(s). When bit is set, there are no
+         *  Command Done interrupts because no command is sent to SD_MMC_CEATA cards.
+         */
+        uint32_t update_clk_reg:1;
+        /** read_ceata_device : R/W; bitpos: [22]; default: 0;
+         *  Read access flag.
+         *  0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;
+         *  1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.
+         *  Software should set this bit to indicate that CE-ATA device is being accessed for
+         *  read transfer. This bit is used to disable read data timeout indication while
+         *  performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no
+         *  less than 10 seconds. SD/MMC should not indicate read data timeout while waiting
+         *  for data from CE-ATA device.
+         */
+        uint32_t read_ceata_device:1;
+        /** ccs_expected : R/W; bitpos: [23]; default: 0;
+         *  Expected Command Completion Signal (CCS) configuration.
+         *  0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register),
+         *  or command does not expect CCS from device;
+         *  1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects
+         *  command completion signal from CE-ATA device.
+         *  If the command expects Command Completion Signal (CCS) from the CE-ATA device, the
+         *  software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in
+         *  RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is
+         *  not masked.
+         */
+        uint32_t ccs_expected:1;
+        uint32_t reserved_24:4;
+        /** volt_switch : R/W; bitpos: [28]; default: 0;
+         *  Voltage switch bit.
+         *  0: No voltage switching.
+         *  1: Voltage switching enabled; must be set for CMD11 only.
+         */
+        uint32_t volt_switch:1;
+        /** use_hole_reg : R/W; bitpos: [29]; default: 1;
+         *  Use Hold Register.
+         *  0: CMD and DATA sent to card bypassing HOLD Register;
+         *  1: CMD and DATA sent to card through the HOLD Register.
+         */
+        uint32_t use_hold_reg:1;
+        uint32_t reserved_30:1;
+        /** start_command : R/W; bitpos: [31]; default: 0;
+         *  Start command. Once command is served by the CIU, this bit is automatically
+         *  cleared. When this bit is set, host should not attempt to write to any command
+         *  registers. If a write is attempted, hardware lock error is set in raw interrupt
+         *  register. Once command is sent and a response is received from SD_MMC_CEATA cards,
+         *  Command Done bit is set in the raw interrupt Register.
+         */
+        uint32_t start_command:1;
+    };
+    uint32_t val;
+} sdhost_cmd_reg_t;
+
+
+/** Group: Response data register */
+/** Type of resp0 register
+ *  Response data register
+ */
+typedef union {
+    struct {
+        /** response0_reg : RO; bitpos: [31:0]; default: 0;
+         *  Bit[31:0] of response.
+         */
+        uint32_t response0_reg:32;
+    };
+    uint32_t val;
+} sdhost_resp0_reg_t;
+
+
+/** Group: Long response data register */
+/** Type of resp1 register
+ *  Long response data register
+ */
+typedef union {
+    struct {
+        /** response1_reg : RO; bitpos: [31:0]; default: 0;
+         *  Bit[63:32] of long response.
+         */
+        uint32_t response1_reg:32;
+    };
+    uint32_t val;
+} sdhost_resp1_reg_t;
+
+/** Type of resp2 register
+ *  Long response data register
+ */
+typedef union {
+    struct {
+        /** response2_reg : RO; bitpos: [31:0]; default: 0;
+         *  Bit[95:64] of long response.
+         */
+        uint32_t response2_reg:32;
+    };
+    uint32_t val;
+} sdhost_resp2_reg_t;
+
+/** Type of resp3 register
+ *  Long response data register
+ */
+typedef union {
+    struct {
+        /** response3_reg : RO; bitpos: [31:0]; default: 0;
+         *  Bit[127:96] of long response.
+         */
+        uint32_t response3_reg:32;
+    };
+    uint32_t val;
+} sdhost_resp3_reg_t;
+
+
+/** Group: Masked interrupt status register */
+/** Type of mintsts register
+ *  Masked interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_status_msk : RO; bitpos: [15:0]; default: 0;
+         *  Interrupt enabled only if corresponding bit in interrupt mask register is set.
+         *  Bit 15 (EBE): End-bit error/no CRC error;
+         *  Bit 14 (ACD): Auto command done;
+         *  Bit 13 (SBE/BCI): RX Start Bit Error;
+         *  Bit 12 (HLE): Hardware locked write error;
+         *  Bit 11 (FRUN): FIFO underrun/overrun error;
+         *  Bit 10 (HTO): Data starvation by host timeout (HTO);
+         *  Bit 9 (DTRO): Data read timeout;
+         *  Bit 8 (RTO): Response timeout;
+         *  Bit 7 (DCRC): Data CRC error;
+         *  Bit 6 (RCRC): Response CRC error;
+         *  Bit 5 (RXDR): Receive FIFO data request;
+         *  Bit 4 (TXDR): Transmit FIFO data request;
+         *  Bit 3 (DTO): Data transfer over;
+         *  Bit 2 (CD): Command done;
+         *  Bit 1 (RE): Response error;
+         *  Bit 0 (CD): Card detect.
+         */
+        uint32_t int_status_msk:16;
+        /** sdio_interrupt_msk : RO; bitpos: [17:16]; default: 0;
+         *  Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
+         *  card0, respectively. SDIO interrupt for card is enabled only if corresponding
+         *  sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit
+         *  enables interrupt).
+         */
+        uint32_t sdio_interrupt_msk:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_mintsts_reg_t;
+
+
+/** Group: Raw interrupt status register */
+/** Type of rintsts register
+ *  Raw interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_status_raw : R/W; bitpos: [15:0]; default: 0;
+         *  Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits
+         *  are logged regardless of interrupt mask status.
+         *  Bit 15 (EBE): End-bit error/no CRC error;
+         *  Bit 14 (ACD): Auto command done;
+         *  Bit 13 (SBE/BCI): RX Start Bit Error;
+         *  Bit 12 (HLE): Hardware locked write error;
+         *  Bit 11 (FRUN): FIFO underrun/overrun error;
+         *  Bit 10 (HTO): Data starvation by host timeout (HTO);
+         *  Bit 9 (DTRO): Data read timeout;
+         *  Bit 8 (RTO): Response timeout;
+         *  Bit 7 (DCRC): Data CRC error;
+         *  Bit 6 (RCRC): Response CRC error;
+         *  Bit 5 (RXDR): Receive FIFO data request;
+         *  Bit 4 (TXDR): Transmit FIFO data request;
+         *  Bit 3 (DTO): Data transfer over;
+         *  Bit 2 (CD): Command done;
+         *  Bit 1 (RE): Response error;
+         *  Bit 0 (CD): Card detect.
+         */
+        uint32_t cd:1;
+        uint32_t re:1;
+        uint32_t cmd_done:1;
+        uint32_t dto:1;
+        uint32_t txdr:1;
+        uint32_t rxdr:1;
+        uint32_t rcrc:1;
+        uint32_t dcrc:1;
+        uint32_t rto:1;
+        uint32_t drto:1;
+        uint32_t hto:1;
+        uint32_t frun:1;
+        uint32_t hle:1;
+        uint32_t sbi_bci:1;
+        uint32_t acd:1;
+        uint32_t ebe:1;
+        /** sdio_interrupt_raw : R/W; bitpos: [17:16]; default: 0;
+         *  Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
+         *  card0, respectively. Setting a bit clears the corresponding interrupt bit and
+         *  writing 0 has no effect.
+         *  0: No SDIO interrupt from card;
+         *  1: SDIO interrupt from card.
+         */
+        uint32_t sdio_interrupt_raw:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_rintsts_reg_t;
+
+
+/** Group: SD/MMC status register */
+/** Type of status register
+ *  SD/MMC status register
+ */
+typedef union {
+    struct {
+        /** fifo_rx_watermark : RO; bitpos: [0]; default: 0;
+         *  FIFO reached Receive watermark level, not qualified with data transfer.
+         */
+        uint32_t fifo_rx_watermark:1;
+        /** fifo_tx_watermark : RO; bitpos: [1]; default: 1;
+         *  FIFO reached Transmit watermark level, not qualified with data transfer.
+         */
+        uint32_t fifo_tx_watermark:1;
+        /** fifo_empty : RO; bitpos: [2]; default: 1;
+         *  FIFO is empty status.
+         */
+        uint32_t fifo_empty:1;
+        /** fifo_full : RO; bitpos: [3]; default: 0;
+         *  FIFO is full status.
+         */
+        uint32_t fifo_full:1;
+        /** command_fsm_states : RO; bitpos: [7:4]; default: 1;
+         *  Command FSM states.
+         *  0: Idle;
+         *  1: Send init sequence;
+         *  2: Send cmd start bit;
+         *  3: Send cmd tx bit;
+         *  4: Send cmd index + arg;
+         *  5: Send cmd crc7;
+         *  6: Send cmd end bit;
+         *  7: Receive resp start bit;
+         *  8: Receive resp IRQ response;
+         *  9: Receive resp tx bit;
+         *  10: Receive resp cmd idx;
+         *  11: Receive resp data;
+         *  12: Receive resp crc7;
+         *  13: Receive resp end bit;
+         *  14: Cmd path wait NCC;
+         *  15: Wait, cmd-to-response turnaround.
+         */
+        uint32_t command_fsm_states:4;
+        /** data_3_status : RO; bitpos: [8]; default: 1;
+         *  Raw selected sdhost_card_data[3], checks whether card is present.
+         *  0: card not present;
+         *  1: card present.
+         */
+        uint32_t data_3_status:1;
+        /** data_busy : RO; bitpos: [9]; default: 1;
+         *  Inverted version of raw selected sdhost_card_data[0].
+         *  0: Card data not busy;
+         *  1: Card data busy.
+         */
+        uint32_t data_busy:1;
+        /** data_state_mc_busy : RO; bitpos: [10]; default: 1;
+         *  Data transmit or receive state-machine is busy.
+         */
+        uint32_t data_state_mc_busy:1;
+        /** response_index : RO; bitpos: [16:11]; default: 0;
+         *  Index of previous response, including any auto-stop sent by core.
+         */
+        uint32_t response_index:6;
+        /** fifo_count : RO; bitpos: [29:17]; default: 0;
+         *  FIFO count, number of filled locations in FIFO.
+         */
+        uint32_t fifo_count:13;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sdhost_status_reg_t;
+
+
+/** Group: FIFO configuration register */
+/** Type of fifoth register
+ *  FIFO configuration register
+ */
+typedef union {
+    struct {
+        /** tx_wmark : R/W; bitpos: [11:0]; default: 0;
+         *  FIFO threshold watermark level when transmitting data to card. When FIFO data count
+         *  is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is
+         *  enabled, then interrupt  occurs. During end of packet, request or interrupt is
+         *  generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO
+         *  threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA
+         *  request. During end of packet, on last interrupt, host is responsible for filling
+         *  FIFO with only required remaining bytes (not before FIFO is full or after CIU
+         *  completes data transfers, because FIFO may not be empty).  In DMA mode, at end of
+         *  packet, if last transfer is less than burst  size, DMA controller does single
+         *  cycles until required bytes are  transferred.
+         */
+        uint32_t tx_wmark:12;
+        uint32_t reserved_12:4;
+        /** rx_wmark : R/W; bitpos: [26:16]; default: 0;
+         *  FIFO threshold watermark level when receiving data to card.When FIFO data count
+         *  reaches greater than this number , DMA/FIFO request is raised. During end of
+         *  packet, request is generated regardless of threshold programming in order to
+         *  complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR)
+         *  interrupt is enabled, then interrupt is generated instead of DMA request.During end
+         *  of packet, interrupt is not generated if threshold programming is larger than any
+         *  remaining data. It is responsibility of host to read remaining bytes on seeing Data
+         *  Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are
+         *  less than threshold, DMA request does single transfers to flush out any remaining
+         *  bytes before Data Transfer Done interrupt is set.
+         */
+        uint32_t rx_wmark:11;
+        uint32_t reserved_27:1;
+        /** dma_multiple_transaction_size : R/W; bitpos: [30:28]; default: 0;
+         *  Burst size of multiple transaction, should be programmed same as DMA controller
+         *  multiple-transaction-size SDHOST_SRC/DEST_MSIZE.
+         *  000: 1-byte transfer;
+         *  001: 4-byte transfer;
+         *  010: 8-byte transfer;
+         *  011: 16-byte transfer;
+         *  100: 32-byte transfer;
+         *  101: 64-byte transfer;
+         *  110: 128-byte transfer;
+         *  111: 256-byte transfer.
+         */
+        uint32_t dma_multiple_transaction_size:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} sdhost_fifoth_reg_t;
+
+
+/** Group: Card detect register */
+/** Type of cdetect register
+ *  Card detect register
+ */
+typedef union {
+    struct {
+        /** card_detect_n : RO; bitpos: [1:0]; default: 0;
+         *  Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0
+         *  represents presence of card. Only NUM_CARDS number of bits are implemented.
+         */
+        uint32_t card_detect_n:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sdhost_cdetect_reg_t;
+
+
+/** Group: Card write protection (WP) status register */
+/** Type of wrtprt register
+ *  Card write protection (WP) status register
+ */
+typedef union {
+    struct {
+        /** write_protect : RO; bitpos: [1:0]; default: 0;
+         *  Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write
+         *  protection. Only NUM_CARDS number of bits are implemented.
+         */
+        uint32_t write_protect:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sdhost_wrtprt_reg_t;
+
+
+/** Group: Transferred byte count register */
+/** Type of tcbcnt register
+ *  Transferred byte count register
+ */
+typedef union {
+    struct {
+        /** tcbcnt_reg : RO; bitpos: [31:0]; default: 0;
+         *  Number of bytes transferred by CIU unit to card.
+         */
+        uint32_t tcbcnt_reg:32;
+    };
+    uint32_t val;
+} sdhost_tcbcnt_reg_t;
+
+/** Type of tbbcnt register
+ *  Transferred byte count register
+ */
+typedef union {
+    struct {
+        /** tbbcnt_reg : RO; bitpos: [31:0]; default: 0;
+         *  Number of bytes transferred between Host/DMA memory and BIU FIFO.
+         */
+        uint32_t tbbcnt_reg:32;
+    };
+    uint32_t val;
+} sdhost_tbbcnt_reg_t;
+
+
+/** Group: Debounce filter time configuration register */
+/** Type of debnce register
+ *  Debounce filter time configuration register
+ */
+typedef union {
+    struct {
+        /** debounce_count : R/W; bitpos: [23:0]; default: 0;
+         *  Number of host clocks (clk) used by debounce filter logic. The typical debounce
+         *  time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted
+         *  or removed.
+         */
+        uint32_t debounce_count:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} sdhost_debnce_reg_t;
+
+
+/** Group: User ID (scratchpad) register */
+/** Type of usrid register
+ *  User ID (scratchpad) register
+ */
+typedef union {
+    struct {
+        /** usrid_reg : R/W; bitpos: [31:0]; default: 0;
+         *  User identification register, value set by user. Can also be used as a scratchpad
+         *  register by user.
+         */
+        uint32_t usrid_reg:32;
+    };
+    uint32_t val;
+} sdhost_usrid_reg_t;
+
+
+/** Group: Hardware feature register */
+/** Type of hcon register
+ *  Hardware feature register
+ */
+typedef union {
+    struct {
+        /** card_type_reg : RO; bitpos: [0]; default: 1;
+         *  Hardware support SDIO and MMC.
+         */
+        uint32_t card_type_reg:1;
+        /** card_num_reg : RO; bitpos: [5:1]; default: 1;
+         *  Support card number is 2.
+         */
+        uint32_t card_num_reg:5;
+        /** bus_type_reg : RO; bitpos: [6]; default: 1;
+         *  Register config is APB bus.
+         */
+        uint32_t bus_type_reg:1;
+        /** data_width_reg : RO; bitpos: [9:7]; default: 1;
+         *  Regisger data width is 32.
+         */
+        uint32_t data_width_reg:3;
+        /** addr_width_reg : RO; bitpos: [15:10]; default: 19;
+         *  Register address width is 32.
+         */
+        uint32_t addr_width_reg:6;
+        uint32_t reserved_16:2;
+        /** dma_width_reg : RO; bitpos: [20:18]; default: 1;
+         *  DMA data width is 32.
+         */
+        uint32_t dma_width_reg:3;
+        /** ram_indise_reg : RO; bitpos: [21]; default: 0;
+         *  Inside RAM in SDMMC module.
+         */
+        uint32_t ram_indise_reg:1;
+        /** hold_reg : RO; bitpos: [22]; default: 1;
+         *  Have a hold register in data path .
+         */
+        uint32_t hold_reg:1;
+        uint32_t reserved_23:1;
+        /** num_clk_div_reg : RO; bitpos: [25:24]; default: 3;
+         *  Have 4 clk divider in design .
+         */
+        uint32_t num_clk_div_reg:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} sdhost_hcon_reg_t;
+
+
+/** Group: UHS-1 register */
+/** Type of uhs register
+ *  UHS-1 register
+ */
+typedef union {
+    struct {
+        /** volt: R/W; bitpos: [1:0]; default: 0;
+         *  Voltage mode selection, 1 bit for each card. On the ESP32-P4, this bit doesn't do anything, I/O voltage is controlled using LDO API instead.
+         *  0: 3.3V mode.
+         *  1: 1.8V mode.
+         */
+        uint32_t volt:2;
+        uint32_t reserved_0:14;
+        /** ddr: R/W; bitpos: [17:16]; default: 0;
+         *  DDR mode selection, 1 bit for each card.
+         *  0: Non-DDR mode.
+         *  1: DDR mode.
+         */
+        uint32_t ddr:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} sdhost_uhs_reg_t;
+
+
+/** Group: Card reset register */
+/** Type of rst_n register
+ *  Card reset register
+ */
+typedef union {
+    struct {
+        /** card_reset : R/W; bitpos: [1:0]; default: 1;
+         *  Hardware reset.
+         *  1: Active mode;
+         *  0: Reset.
+         *  These bits cause the cards to enter pre-idle state, which requires them to be
+         *  re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0,
+         *  SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1.
+         */
+        uint32_t card_reset:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sdhost_rst_n_reg_t;
+
+
+/** Group: Burst mode transfer configuration register */
+/** Type of bmod register
+ *  Burst mode transfer configuration register
+ */
+typedef union {
+    struct {
+        /** sw_reset : R/W; bitpos: [0]; default: 0;
+         *  Software Reset. When set, the DMA Controller resets all its internal registers. It
+         *  is automatically cleared after one clock cycle.
+         */
+        uint32_t sw_reset:1;
+        /** fb : R/W; bitpos: [1]; default: 0;
+         *  Fixed Burst. Controls whether the AHB Master interface performs fixed burst
+         *  transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16
+         *  during start of normal burst transfers. When reset, the AHB will use SINGLE and
+         *  INCR burst transfer operations.
+         */
+        uint32_t fb:1;
+        uint32_t reserved_2:5;
+        /** enable : R/W; bitpos: [7]; default: 0;
+         *  IDMAC Enable. When set, the IDMAC is enabled.
+         */
+        uint32_t enable:1;
+        /** bmod_pbl : R/W; bitpos: [10:8]; default: 0;
+         *  Programmable Burst Length. These bits indicate the maximum number of beats to be
+         *  performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always
+         *  attempt to burst as specified in PBL each time it starts a burst transfer on the
+         *  host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value
+         *  is the mirror of MSIZE of FIFOTH register. In order to change this value, write the
+         *  required value to FIFOTH register. This is an encode value as follows:
+         *  000: 1-byte transfer;
+         *  001: 4-byte transfer;
+         *  010: 8-byte transfer;
+         *  011: 16-byte transfer;
+         *  100: 32-byte transfer;
+         *  101: 64-byte transfer;
+         *  110: 128-byte transfer;
+         *  111: 256-byte transfer.
+         *  PBL is a read-only value and is applicable only for data access, it does not apply
+         *  to descriptor access.
+         */
+        uint32_t bmod_pbl:3;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} sdhost_bmod_reg_t;
+
+
+/** Group: Poll demand configuration register */
+/** Type of pldmnd register
+ *  Poll demand configuration register
+ */
+typedef union {
+    struct {
+        /** pldmnd_pd : WO; bitpos: [31:0]; default: 0;
+         *  Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the
+         *  Suspend state. The host needs to write any value into this register for the IDMAC
+         *  FSM to resume normal descriptor fetch operation. This is a write only .
+         */
+        uint32_t pldmnd_pd:32;
+    };
+    uint32_t val;
+} sdhost_pldmnd_reg_t;
+
+
+/** Group: Descriptor base address register */
+/** Type of dbaddr register
+ *  Descriptor base address register
+ */
+typedef union {
+    struct {
+        /** dbaddr_reg : R/W; bitpos: [31:0]; default: 0;
+         *  Start of Descriptor List. Contains the base address of the First Descriptor. The
+         *  LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence
+         *  these LSB bits may be treated as read-only.
+         */
+        uint32_t dbaddr_reg:32;
+    };
+    uint32_t val;
+} sdhost_dbaddr_reg_t;
+
+
+/** Group: IDMAC status register */
+/** Type of idsts register
+ *  IDMAC status register
+ */
+typedef union {
+    struct {
+        /** idsts_ti : R/W; bitpos: [0]; default: 0;
+         *  Transmit Interrupt. Indicates that data transmission is finished for a descriptor.
+         *  Writing 1 clears this bit.
+         */
+        uint32_t idsts_ti:1;
+        /** idsts_ri : R/W; bitpos: [1]; default: 0;
+         *  Receive Interrupt. Indicates the completion of data reception for a descriptor.
+         *  Writing 1 clears this bit.
+         */
+        uint32_t idsts_ri:1;
+        /** idsts_fbe : R/W; bitpos: [2]; default: 0;
+         *  Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) .
+         *  When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this
+         *  bit.
+         */
+        uint32_t idsts_fbe:1;
+        uint32_t reserved_3:1;
+        /** idsts_du : R/W; bitpos: [4]; default: 0;
+         *  Descriptor Unavailable Interrupt. This bit is set when the descriptor is
+         *  unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit.
+         */
+        uint32_t idsts_du:1;
+        /** idsts_ces : R/W; bitpos: [5]; default: 0;
+         *  Card Error Summary. Indicates the status of the transaction to/from the card, also
+         *  present in RINTSTS. Indicates the logical OR of the following bits:
+         *  EBE : End Bit Error;
+         *  RTO : Response Timeout/Boot Ack Timeout;
+         *  RCRC : Response CRC;
+         *  SBE : Start Bit Error;
+         *  DRTO : Data Read Timeout/BDS timeout;
+         *  DCRC : Data CRC for Receive;
+         *  RE : Response Error.
+         *  Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting
+         *  of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response
+         *  error.
+         */
+        uint32_t idsts_ces:1;
+        uint32_t reserved_6:2;
+        /** idsts_nis : R/W; bitpos: [8]; default: 0;
+         *  Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit
+         *  Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This
+         *  is a sticky bit and must be cleared each time a corresponding bit that causes NIS
+         *  to be set is cleared. Writing 1 clears this bit.
+         */
+        uint32_t idsts_nis:1;
+        /** idsts_ais : R/W; bitpos: [9]; default: 0;
+         *  Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus
+         *  Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is
+         *  a sticky bit and must be cleared each time a corresponding bit that causes AIS to
+         *  be set is cleared. Writing 1 clears this bit.
+         */
+        uint32_t idsts_ais:1;
+        /** idsts_fbe_code : R/W; bitpos: [12:10]; default: 0;
+         *  Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid
+         *  only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an
+         *  interrupt.
+         *  001: Host Abort received during transmission;
+         *  010: Host Abort received during reception;
+         *  Others: Reserved.
+         */
+        uint32_t idsts_fbe_code:3;
+        /** idsts_fsm : R/W; bitpos: [16:13]; default: 0;
+         *  DMAC FSM present state.
+         *  0: DMA_IDLE (idle state);
+         *  1: DMA_SUSPEND (suspend state);
+         *  2: DESC_RD (descriptor reading state);
+         *  3: DESC_CHK (descriptor checking state);
+         *  4: DMA_RD_REQ_WAIT (read-data request waiting state);
+         *  5: DMA_WR_REQ_WAIT (write-data request waiting state);
+         *  6: DMA_RD (data-read state);
+         *  7: DMA_WR (data-write state);
+         *  8: DESC_CLOSE (descriptor close state).
+         */
+        uint32_t idsts_fsm:4;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} sdhost_idsts_reg_t;
+
+
+/** Group: IDMAC interrupt enable register */
+/** Type of idinten register
+ *  IDMAC interrupt enable register
+ */
+typedef union {
+    struct {
+        /** ti : R/W; bitpos: [0]; default: 0;
+         *  Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit
+         *  Interrupt is enabled. When reset, Transmit Interrupt is disabled.
+         */
+        uint32_t ti:1;
+        /** ri : R/W; bitpos: [1]; default: 0;
+         *  Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
+         *  Interrupt is enabled. When reset, Receive Interrupt is disabled.
+         */
+        uint32_t ri:1;
+        /** idinten_fbe : R/W; bitpos: [2]; default: 0;
+         *  Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal
+         *  Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is
+         *  disabled.
+         */
+        uint32_t idinten_fbe:1;
+        uint32_t reserved_3:1;
+        /** idinten_du : R/W; bitpos: [4]; default: 0;
+         *  Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
+         *  Enable, the DU interrupt is enabled.
+         */
+        uint32_t idinten_du:1;
+        /** idinten_ces : R/W; bitpos: [5]; default: 0;
+         *  Card Error summary Interrupt Enable. When set, it enables the Card Interrupt
+         *  summary.
+         */
+        uint32_t idinten_ces:1;
+        uint32_t reserved_6:2;
+        /** ni : R/W; bitpos: [8]; default: 0;
+         *  Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When
+         *  reset, a normal interrupt is disabled. This bit enables the following bits:
+         *  IDINTEN[0]: Transmit Interrupt;
+         *  IDINTEN[1]: Receive Interrupt.
+         */
+        uint32_t ni:1;
+        /** idinten_ai : R/W; bitpos: [9]; default: 0;
+         *  Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This
+         *  bit enables the following bits:
+         *  IDINTEN[2]: Fatal Bus Error Interrupt;
+         *  IDINTEN[4]: DU Interrupt.
+         */
+        uint32_t idinten_ai:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} sdhost_idinten_reg_t;
+
+
+/** Group: Host descriptor address pointer */
+/** Type of dscaddr register
+ *  Host descriptor address pointer
+ */
+typedef union {
+    struct {
+        /** dscaddr_reg : RO; bitpos: [31:0]; default: 0;
+         *  Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on
+         *  reset. This register points to the start address of the current descriptor read by
+         *  the IDMAC.
+         */
+        uint32_t dscaddr_reg:32;
+    };
+    uint32_t val;
+} sdhost_dscaddr_reg_t;
+
+
+/** Group: Host buffer address pointer register */
+/** Type of bufaddr register
+ *  Host buffer address pointer register
+ */
+typedef union {
+    struct {
+        /** bufaddr_reg : RO; bitpos: [31:0]; default: 0;
+         *  Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
+         *  reset. This register points to the current Data Buffer Address being accessed by
+         *  the IDMAC.
+         */
+        uint32_t bufaddr_reg:32;
+    };
+    uint32_t val;
+} sdhost_bufaddr_reg_t;
+
+
+/** Group: Card Threshold Control register */
+/** Type of cardthrctl register
+ *  Card Threshold Control register
+ */
+typedef union {
+    struct {
+        /** cardrdthren_reg : R/W; bitpos: [0]; default: 0;
+         *  Card read threshold enable.
+         *  1'b0-Card read threshold disabled.
+         *  1'b1-Card read threshold enabled.
+         */
+        uint32_t cardrdthren_reg:1;
+        /** busy_clr_int_en : R/W; bitpos: [1]; default: 0;
+         *  Busy clear interrupt generation:
+         *  1'b0-Busy clear interrypt disabled.
+         *  1'b1-Busy clear interrypt enabled.
+         */
+        uint32_t busy_clr_int_en:1;
+        /** cardwrthren_reg : R/W; bitpos: [2]; default: 0;
+         *  Applicable when HS400 mode is enabled.
+         *  1'b0-Card write Threshold disabled.
+         *  1'b1-Card write Threshold enabled.
+         */
+        uint32_t cardwrthren_reg:1;
+        uint32_t reserved_3:13;
+        /** cardthreshold_reg : R/W; bitpos: [31:16]; default: 0;
+         *  The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG
+         *  is set to 1 or SDHOST_CARDRDTHREN_REG set to 1.
+         */
+        uint32_t cardthreshold_reg:16;
+    };
+    uint32_t val;
+} sdhost_cardthrctl_reg_t;
+
+
+/** Group: eMMC DDR register */
+/** Type of emmcddr register
+ *  eMMC DDR register
+ */
+typedef union {
+    struct {
+        /** halfstartbit_reg : R/W; bitpos: [1:0]; default: 0;
+         *  Control for start bit detection mechanism duration of start bit.Each bit refers to
+         *  one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For
+         *  eMMC4.5,start bit can be:
+         *  1'b0-Full cycle.
+         *  1'b1-less than one full cycle.
+         */
+        uint32_t halfstartbit_reg:2;
+        uint32_t reserved_2:29;
+        /** hs400_mode_reg : R/W; bitpos: [31]; default: 0;
+         *  Set 1 to enable HS400 mode.
+         */
+        uint32_t hs400_mode_reg:1;
+    };
+    uint32_t val;
+} sdhost_emmcddr_reg_t;
+
+
+/** Group: Enable Phase Shift register */
+/** Type of enshift register
+ *  Enable Phase Shift register
+ */
+typedef union {
+    struct {
+        /** enable_shift_reg : R/W; bitpos: [3:0]; default: 0;
+         *  Control for the amount of phase shift provided on the default enables in the
+         *  design.Two bits assigned for each card.
+         *  2'b00-Default phase shift.
+         *  2'b01-Enables shifted to next immediate positive edge.
+         *  2'b10-Enables shifted to next immediate negative edge.
+         *  2'b11-Reserved.
+         */
+        uint32_t enable_shift_reg:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} sdhost_enshift_reg_t;
+
+
+/** Group: CPU write and read transmit data by FIFO */
+/** Type of buffifo register
+ *  CPU write and read transmit data by FIFO
+ */
+typedef union {
+    struct {
+        /** buffifo_reg : R/W; bitpos: [31:0]; default: 0;
+         *  CPU write and read transmit data by FIFO. This register points to the current Data
+         *  FIFO .
+         */
+        uint32_t buffifo_reg:32;
+    };
+    uint32_t val;
+} sdhost_buffifo_reg_t;
+
+
+/** Group: SDIO Control and configuration registers */
+/** Type of clk_edge_sel register
+ *  SDIO control register.
+ */
+typedef union {
+    struct {
+        /** cclkin_edge_drv_sel : R/W; bitpos: [2:0]; default: 0;
+         *  It's used to select the clock phase of the output signal from phase 0, phase 90,
+         *  phase 180, phase 270.
+         */
+        uint32_t cclkin_edge_drv_sel:3;
+        /** cclkin_edge_sam_sel : R/W; bitpos: [5:3]; default: 0;
+         *  It's used to select the clock phase of the input signal from phase 0, phase 90,
+         *  phase 180, phase 270.
+         */
+        uint32_t cclkin_edge_sam_sel:3;
+        /** cclkin_edge_slf_sel : R/W; bitpos: [8:6]; default: 0;
+         *  It's used to select the clock phase of the internal signal from phase 0, phase 90,
+         *  phase 180, phase 270.
+         */
+        uint32_t cclkin_edge_slf_sel:3;
+        /** ccllkin_edge_h : R/W; bitpos: [12:9]; default: 1;
+         *  The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L.
+         */
+        uint32_t ccllkin_edge_h:4;
+        /** ccllkin_edge_l : R/W; bitpos: [16:13]; default: 0;
+         *  The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H.
+         */
+        uint32_t ccllkin_edge_l:4;
+        /** ccllkin_edge_n : R/W; bitpos: [20:17]; default: 1;
+         *  The clock division of cclk_in.
+         */
+        uint32_t ccllkin_edge_n:4;
+        /** esdio_mode : R/W; bitpos: [21]; default: 0;
+         *  Enable esdio mode.
+         */
+        uint32_t esdio_mode:1;
+        /** esd_mode : R/W; bitpos: [22]; default: 0;
+         *  Enable esd mode.
+         */
+        uint32_t esd_mode:1;
+        /** cclk_en : R/W; bitpos: [23]; default: 1;
+         *  Sdio clock enable.
+         */
+        uint32_t cclk_en:1;
+        /** ultra_high_speed_mode : R/W; bitpos: [24]; default: 0;
+         *  Enable ultra high speed mode, use dll to generate clk.
+         */
+        uint32_t ultra_high_speed_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} sdhost_clk_edge_sel_reg_t;
+
+
+/** Group: SDIO raw ints registers */
+/** Type of raw_ints register
+ *  SDIO raw ints register.
+ */
+typedef union {
+    struct {
+        /** raw_ints : RO; bitpos: [31:0]; default: 0;
+         *  It indicates raw ints.
+         */
+        uint32_t raw_ints:32;
+    };
+    uint32_t val;
+} sdhost_raw_ints_reg_t;
+
+
+/** Group: SDIO dll clock control registers */
+/** Type of dll_clk_conf register
+ *  SDIO DLL clock control register.
+ */
+typedef union {
+    struct {
+        /** dll_cclk_in_slf_en : R/W; bitpos: [0]; default: 0;
+         *  Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_slf_en:1;
+        /** dll_cclk_in_drv_en : R/W; bitpos: [1]; default: 0;
+         *  Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_drv_en:1;
+        /** dll_cclk_in_sam_en : R/W; bitpos: [2]; default: 0;
+         *  Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_sam_en:1;
+        /** dll_cclk_in_slf_phase : R/W; bitpos: [8:3]; default: 0;
+         *  It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_slf_phase:6;
+        /** dll_cclk_in_drv_phase : R/W; bitpos: [14:9]; default: 0;
+         *  It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_drv_phase:6;
+        /** dll_cclk_in_sam_phase : R/W; bitpos: [20:15]; default: 0;
+         *  It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
+         */
+        uint32_t dll_cclk_in_sam_phase:6;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} sdhost_dll_clk_conf_reg_t;
+
+
+/** Group: SDIO dll configuration registers */
+/** Type of dll_conf register
+ *  SDIO DLL configuration register.
+ */
+typedef union {
+    struct {
+        /** dll_cal_stop : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to stop calibration.
+         */
+        uint32_t dll_cal_stop:1;
+        /** dll_cal_end : RO; bitpos: [1]; default: 0;
+         *  1 means calibration finished.
+         */
+        uint32_t dll_cal_end:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sdhost_dll_conf_reg_t;
+
+
+typedef struct sdmmc_dev_t {
+    volatile sdhost_ctrl_reg_t ctrl;
+    uint32_t reserved_004;
+    volatile sdhost_clkdiv_reg_t clkdiv;
+    volatile sdhost_clksrc_reg_t clksrc;
+    volatile sdhost_clkena_reg_t clkena;
+    volatile sdhost_tmout_reg_t tmout;
+    volatile sdhost_ctype_reg_t ctype;
+    volatile sdhost_blksiz_reg_t blksiz;
+    volatile sdhost_bytcnt_reg_t bytcnt;
+    volatile sdhost_intmask_reg_t intmask;
+    volatile uint32_t cmdarg;
+    volatile sdhost_cmd_reg_t cmd;
+    volatile uint32_t resp[4];           ///< Response from card
+    volatile sdhost_mintsts_reg_t mintsts;
+    volatile sdhost_rintsts_reg_t rintsts;
+    volatile sdhost_status_reg_t status;
+    volatile sdhost_fifoth_reg_t fifoth;
+    volatile sdhost_cdetect_reg_t cdetect;
+    volatile sdhost_wrtprt_reg_t wrtprt;
+    uint32_t reserved_058;
+    volatile sdhost_tcbcnt_reg_t tcbcnt;
+    volatile sdhost_tbbcnt_reg_t tbbcnt;
+    volatile sdhost_debnce_reg_t debnce;
+    volatile sdhost_usrid_reg_t usrid;
+    volatile uint32_t verid;
+    volatile sdhost_hcon_reg_t hcon;
+    volatile sdhost_uhs_reg_t uhs;
+    volatile sdhost_rst_n_reg_t rst_n;
+    uint32_t reserved_07c;
+    volatile sdhost_bmod_reg_t bmod;
+    volatile sdhost_pldmnd_reg_t pldmnd;
+    volatile sdhost_dbaddr_reg_t dbaddr;
+    volatile sdhost_idsts_reg_t idsts;
+    volatile sdhost_idinten_reg_t idinten;
+    volatile sdhost_dscaddr_reg_t dscaddr;
+    volatile sdhost_bufaddr_reg_t bufaddr;
+    uint32_t reserved_09c[25];
+    volatile sdhost_cardthrctl_reg_t cardthrctl;
+    uint32_t reserved_104[2];
+    volatile sdhost_emmcddr_reg_t emmcddr;
+    volatile sdhost_enshift_reg_t enshift;
+    uint32_t reserved_114[59];
+    volatile sdhost_buffifo_reg_t buffifo;
+    uint32_t reserved_204[383];
+    volatile sdhost_clk_edge_sel_reg_t clk_edge_sel;
+    volatile sdhost_raw_ints_reg_t raw_ints;
+    volatile sdhost_dll_clk_conf_reg_t dll_clk_conf;
+    volatile sdhost_dll_conf_reg_t dll_conf;
+} sdmmc_dev_t;
+
+extern sdmmc_dev_t SDMMC;
+
+typedef sdhost_cmd_reg_t sdmmc_hw_cmd_t;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(sdmmc_dev_t) == 0x810, "Invalid size of sdmmc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/sha_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/sha_eco5_reg.h
new file mode 100644
index 0000000000..f417aadeff
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/sha_eco5_reg.h
@@ -0,0 +1,170 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SHA_MODE_REG register
+ *  Configures SHA algorithm
+ */
+#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
+/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the SHA algorithm.
+ *  0: SHA-1
+ *  1: SHA-224
+ *  2: SHA-256
+ *  3: SHA2-384
+ *  4: SHA2-512
+ *  5: SHA2-512/224
+ *  6: SHA2-512/256
+ *  7: SHA2-512/t
+ */
+#define SHA_MODE    0x00000007U
+#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
+#define SHA_MODE_V  0x00000007U
+#define SHA_MODE_S  0
+
+/** SHA_DMA_BLOCK_NUM_REG register
+ *  Block number register (only effective for DMA-SHA)
+ */
+#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
+/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the DMA-SHA block number.
+ */
+#define SHA_DMA_BLOCK_NUM    0x0000FFFFU
+#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
+#define SHA_DMA_BLOCK_NUM_V  0x0000FFFFU
+#define SHA_DMA_BLOCK_NUM_S  0
+
+/** SHA_START_REG register
+ *  Starts the SHA accelerator for Typical SHA operation
+ */
+#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
+/** SHA_START : WO; bitpos: [0]; default: 0;
+ *  Write 1 to start Typical SHA calculation.
+ */
+#define SHA_START    (BIT(0))
+#define SHA_START_M  (SHA_START_V << SHA_START_S)
+#define SHA_START_V  0x00000001U
+#define SHA_START_S  0
+
+/** SHA_CONTINUE_REG register
+ *  Continues SHA operation (only effective in Typical SHA mode)
+ */
+#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
+/** SHA_CONTINUE : WO; bitpos: [0]; default: 0;
+ *  Write 1 to continue Typical SHA calculation.
+ */
+#define SHA_CONTINUE    (BIT(0))
+#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
+#define SHA_CONTINUE_V  0x00000001U
+#define SHA_CONTINUE_S  0
+
+/** SHA_BUSY_REG register
+ *  Represents if SHA Accelerator is busy or not
+ */
+#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
+/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Represents the states of SHA accelerator.
+ *  0: idle
+ *  1: busy
+ */
+#define SHA_BUSY_STATE    (BIT(0))
+#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
+#define SHA_BUSY_STATE_V  0x00000001U
+#define SHA_BUSY_STATE_S  0
+
+/** SHA_DMA_START_REG register
+ *  Starts the SHA accelerator for DMA-SHA operation
+ */
+#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
+/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
+ *  Write 1 to start DMA-SHA calculation.
+ */
+#define SHA_DMA_START    (BIT(0))
+#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
+#define SHA_DMA_START_V  0x00000001U
+#define SHA_DMA_START_S  0
+
+/** SHA_DMA_CONTINUE_REG register
+ *  Continues SHA operation (only effective in DMA-SHA mode)
+ */
+#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
+/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
+ *  Write 1 to continue DMA-SHA calculation.
+ */
+#define SHA_DMA_CONTINUE    (BIT(0))
+#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
+#define SHA_DMA_CONTINUE_V  0x00000001U
+#define SHA_DMA_CONTINUE_S  0
+
+/** SHA_CLEAR_IRQ_REG register
+ *  DMA-SHA interrupt clear register
+ */
+#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
+/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
+ *  Write 1 to clear DMA-SHA interrupt.
+ */
+#define SHA_CLEAR_INTERRUPT    (BIT(0))
+#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
+#define SHA_CLEAR_INTERRUPT_V  0x00000001U
+#define SHA_CLEAR_INTERRUPT_S  0
+
+/** SHA_IRQ_ENA_REG register
+ *  DMA-SHA interrupt enable register
+ */
+#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
+/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable DMA-SHA interrupt.
+ */
+#define SHA_INTERRUPT_ENA    (BIT(0))
+#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
+#define SHA_INTERRUPT_ENA_V  0x00000001U
+#define SHA_INTERRUPT_ENA_S  0
+
+/** SHA_DATE_REG register
+ *  Version control register
+ */
+#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
+/** SHA_DATE : R/W; bitpos: [29:0]; default: 539232291;
+ *  Version control register.
+ */
+#define SHA_DATE    0x3FFFFFFFU
+#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
+#define SHA_DATE_V  0x3FFFFFFFU
+#define SHA_DATE_S  0
+
+/** SHA_DMA_RX_RESET_REG register
+ *  DMA RX FIFO Reset Signal
+ */
+#define SHA_DMA_RX_RESET_REG (DR_REG_SHA_BASE + 0x30)
+/** SHA_DMA_RX_RESET : WO; bitpos: [0]; default: 0;
+ *  Write 1 to reset DMA RX FIFO
+ */
+#define SHA_DMA_RX_RESET    (BIT(0))
+#define SHA_DMA_RX_RESET_M  (SHA_DMA_RX_RESET_V << SHA_DMA_RX_RESET_S)
+#define SHA_DMA_RX_RESET_V  0x00000001U
+#define SHA_DMA_RX_RESET_S  0
+
+/** SHA_H_MEM register
+ *  Sha H memory which contains intermediate hash or final hash.
+ */
+#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
+#define SHA_H_MEM_SIZE_BYTES 64
+
+/** SHA_M_MEM register
+ *  Sha M memory which contains message.
+ */
+#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
+#define SHA_M_MEM_SIZE_BYTES 128
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/sha_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/sha_reg.h
new file mode 100644
index 0000000000..add9873601
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/sha_reg.h
@@ -0,0 +1,172 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SHA_MODE_REG register
+ *  Initial configuration register.
+ */
+#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
+/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Sha mode.
+ */
+#define SHA_MODE    0x00000007U
+#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
+#define SHA_MODE_V  0x00000007U
+#define SHA_MODE_S  0
+
+/** SHA_T_STRING_REG register
+ *  SHA 512/t configuration register 0.
+ */
+#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
+/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
+ *  Sha t_string (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_STRING    0xFFFFFFFFU
+#define SHA_T_STRING_M  (SHA_T_STRING_V << SHA_T_STRING_S)
+#define SHA_T_STRING_V  0xFFFFFFFFU
+#define SHA_T_STRING_S  0
+
+/** SHA_T_LENGTH_REG register
+ *  SHA 512/t configuration register 1.
+ */
+#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
+/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
+ *  Sha t_length (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_LENGTH    0x0000003FU
+#define SHA_T_LENGTH_M  (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
+#define SHA_T_LENGTH_V  0x0000003FU
+#define SHA_T_LENGTH_S  0
+
+/** SHA_DMA_BLOCK_NUM_REG register
+ *  DMA configuration register 0.
+ */
+#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
+/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
+ *  Dma-sha block number.
+ */
+#define SHA_DMA_BLOCK_NUM    0x0000003FU
+#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
+#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
+#define SHA_DMA_BLOCK_NUM_S  0
+
+/** SHA_START_REG register
+ *  Typical SHA configuration register 0.
+ */
+#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
+/** SHA_START : RO; bitpos: [31:1]; default: 0;
+ *  Reserved.
+ */
+#define SHA_START    0x7FFFFFFFU
+#define SHA_START_M  (SHA_START_V << SHA_START_S)
+#define SHA_START_V  0x7FFFFFFFU
+#define SHA_START_S  1
+
+/** SHA_CONTINUE_REG register
+ *  Typical SHA configuration register 1.
+ */
+#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
+/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
+ *  Reserved.
+ */
+#define SHA_CONTINUE    0x7FFFFFFFU
+#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
+#define SHA_CONTINUE_V  0x7FFFFFFFU
+#define SHA_CONTINUE_S  1
+
+/** SHA_BUSY_REG register
+ *  Busy register.
+ */
+#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
+/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Sha busy state. 1'b0: idle. 1'b1: busy.
+ */
+#define SHA_BUSY_STATE    (BIT(0))
+#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
+#define SHA_BUSY_STATE_V  0x00000001U
+#define SHA_BUSY_STATE_S  0
+
+/** SHA_DMA_START_REG register
+ *  DMA configuration register 1.
+ */
+#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
+/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
+ *  Start dma-sha.
+ */
+#define SHA_DMA_START    (BIT(0))
+#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
+#define SHA_DMA_START_V  0x00000001U
+#define SHA_DMA_START_S  0
+
+/** SHA_DMA_CONTINUE_REG register
+ *  DMA configuration register 2.
+ */
+#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
+/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
+ *  Continue dma-sha.
+ */
+#define SHA_DMA_CONTINUE    (BIT(0))
+#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
+#define SHA_DMA_CONTINUE_V  0x00000001U
+#define SHA_DMA_CONTINUE_S  0
+
+/** SHA_CLEAR_IRQ_REG register
+ *  Interrupt clear register.
+ */
+#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
+/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
+ *  Clear sha interrupt.
+ */
+#define SHA_CLEAR_INTERRUPT    (BIT(0))
+#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
+#define SHA_CLEAR_INTERRUPT_V  0x00000001U
+#define SHA_CLEAR_INTERRUPT_S  0
+
+/** SHA_IRQ_ENA_REG register
+ *  Interrupt enable register.
+ */
+#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
+/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+ */
+#define SHA_INTERRUPT_ENA    (BIT(0))
+#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
+#define SHA_INTERRUPT_ENA_V  0x00000001U
+#define SHA_INTERRUPT_ENA_S  0
+
+/** SHA_DATE_REG register
+ *  Date register.
+ */
+#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
+/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
+ *  Sha date information/ sha version information.
+ */
+#define SHA_DATE    0x3FFFFFFFU
+#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
+#define SHA_DATE_V  0x3FFFFFFFU
+#define SHA_DATE_S  0
+
+/** SHA_H_MEM register
+ *  Sha H memory which contains intermediate hash or final hash.
+ */
+#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
+#define SHA_H_MEM_SIZE_BYTES 64
+
+/** SHA_M_MEM register
+ *  Sha M memory which contains message.
+ */
+#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
+#define SHA_M_MEM_SIZE_BYTES 64
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/sha_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/sha_struct.h
new file mode 100644
index 0000000000..30193aee03
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/sha_struct.h
@@ -0,0 +1,213 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control/Configuration Registers */
+/** Type of mode register
+ *  Configures SHA algorithm
+ */
+typedef union {
+    struct {
+        /** mode : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the SHA algorithm.
+         *  0: SHA-1
+         *  1: SHA-224
+         *  2: SHA-256
+         *  3: SHA2-384
+         *  4: SHA2-512
+         *  5: SHA2-512/224
+         *  6: SHA2-512/256
+         *  7: SHA2-512/t
+         */
+        uint32_t mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} sha_mode_reg_t;
+
+/** Type of dma_block_num register
+ *  Block number register (only effective for DMA-SHA)
+ */
+typedef union {
+    struct {
+        /** dma_block_num : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the DMA-SHA block number.
+         */
+        uint32_t dma_block_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} sha_dma_block_num_reg_t;
+
+/** Type of start register
+ *  Starts the SHA accelerator for Typical SHA operation
+ */
+typedef union {
+    struct {
+        /** start : WO; bitpos: [0]; default: 0;
+         *  Write 1 to start Typical SHA calculation.
+         */
+        uint32_t start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_start_reg_t;
+
+/** Type of continue register
+ *  Continues SHA operation (only effective in Typical SHA mode)
+ */
+typedef union {
+    struct {
+        /** continue : WO; bitpos: [0]; default: 0;
+         *  Write 1 to continue Typical SHA calculation.
+         */
+        uint32_t conti:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_continue_reg_t;
+
+/** Type of dma_start register
+ *  Starts the SHA accelerator for DMA-SHA operation
+ */
+typedef union {
+    struct {
+        /** dma_start : WO; bitpos: [0]; default: 0;
+         *  Write 1 to start DMA-SHA calculation.
+         */
+        uint32_t dma_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_dma_start_reg_t;
+
+/** Type of dma_continue register
+ *  Continues SHA operation (only effective in DMA-SHA mode)
+ */
+typedef union {
+    struct {
+        /** dma_continue : WO; bitpos: [0]; default: 0;
+         *  Write 1 to continue DMA-SHA calculation.
+         */
+        uint32_t dma_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_dma_continue_reg_t;
+
+/** Type of dma_rx_reset register
+ *  DMA RX FIFO Reset Signal
+ */
+typedef union {
+    struct {
+        /** dma_rx_reset : WO; bitpos: [0]; default: 0;
+         *  Write 1 to reset DMA RX FIFO
+         */
+        uint32_t dma_rx_reset:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_dma_rx_reset_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of busy register
+ *  Represents if SHA Accelerator is busy or not
+ */
+typedef union {
+    struct {
+        /** busy_state : RO; bitpos: [0]; default: 0;
+         *  Represents the states of SHA accelerator.
+         *  0: idle
+         *  1: busy
+         */
+        uint32_t busy_state:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_busy_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of clear_irq register
+ *  DMA-SHA interrupt clear register
+ */
+typedef union {
+    struct {
+        /** clear_interrupt : WO; bitpos: [0]; default: 0;
+         *  Write 1 to clear DMA-SHA interrupt.
+         */
+        uint32_t clear_interrupt:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_clear_irq_reg_t;
+
+/** Type of irq_ena register
+ *  DMA-SHA interrupt enable register
+ */
+typedef union {
+    struct {
+        /** interrupt_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable DMA-SHA interrupt.
+         */
+        uint32_t interrupt_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_irq_ena_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [29:0]; default: 539232291;
+         *  Version control register.
+         */
+        uint32_t date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sha_date_reg_t;
+
+
+/** Group: memory type */
+
+typedef struct {
+    volatile sha_mode_reg_t mode;
+    uint32_t reserved_004[2];
+    volatile sha_dma_block_num_reg_t dma_block_num;
+    volatile sha_start_reg_t start;
+    volatile sha_continue_reg_t conti;
+    volatile sha_busy_reg_t busy;
+    volatile sha_dma_start_reg_t dma_start;
+    volatile sha_dma_continue_reg_t dma_continue;
+    volatile sha_clear_irq_reg_t clear_irq;
+    volatile sha_irq_ena_reg_t irq_ena;
+    volatile sha_date_reg_t date;
+    volatile sha_dma_rx_reset_reg_t dma_rx_reset;
+    uint32_t reserved_034[3];
+    volatile uint32_t h[16];
+    volatile uint32_t m[32];
+} sha_dev_t;
+
+extern sha_dev_t SHA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(sha_dev_t) == 0x100, "Invalid size of sha_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/soc_etm_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/soc_etm_reg.h
new file mode 100644
index 0000000000..caec8f065f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/soc_etm_reg.h
@@ -0,0 +1,10710 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SOC_ETM_CH_ENA_AD0_REG register
+ *  Channel enable status register
+ */
+#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0)
+/** SOC_ETM_CH_ENA0 : R/WTC/WTS; bitpos: [0]; default: 0;
+ *  Represents ch0 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA0    (BIT(0))
+#define SOC_ETM_CH_ENA0_M  (SOC_ETM_CH_ENA0_V << SOC_ETM_CH_ENA0_S)
+#define SOC_ETM_CH_ENA0_V  0x00000001U
+#define SOC_ETM_CH_ENA0_S  0
+/** SOC_ETM_CH_ENA1 : R/WTC/WTS; bitpos: [1]; default: 0;
+ *  Represents ch1 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA1    (BIT(1))
+#define SOC_ETM_CH_ENA1_M  (SOC_ETM_CH_ENA1_V << SOC_ETM_CH_ENA1_S)
+#define SOC_ETM_CH_ENA1_V  0x00000001U
+#define SOC_ETM_CH_ENA1_S  1
+/** SOC_ETM_CH_ENA2 : R/WTC/WTS; bitpos: [2]; default: 0;
+ *  Represents ch2 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA2    (BIT(2))
+#define SOC_ETM_CH_ENA2_M  (SOC_ETM_CH_ENA2_V << SOC_ETM_CH_ENA2_S)
+#define SOC_ETM_CH_ENA2_V  0x00000001U
+#define SOC_ETM_CH_ENA2_S  2
+/** SOC_ETM_CH_ENA3 : R/WTC/WTS; bitpos: [3]; default: 0;
+ *  Represents ch3 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA3    (BIT(3))
+#define SOC_ETM_CH_ENA3_M  (SOC_ETM_CH_ENA3_V << SOC_ETM_CH_ENA3_S)
+#define SOC_ETM_CH_ENA3_V  0x00000001U
+#define SOC_ETM_CH_ENA3_S  3
+/** SOC_ETM_CH_ENA4 : R/WTC/WTS; bitpos: [4]; default: 0;
+ *  Represents ch4 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA4    (BIT(4))
+#define SOC_ETM_CH_ENA4_M  (SOC_ETM_CH_ENA4_V << SOC_ETM_CH_ENA4_S)
+#define SOC_ETM_CH_ENA4_V  0x00000001U
+#define SOC_ETM_CH_ENA4_S  4
+/** SOC_ETM_CH_ENA5 : R/WTC/WTS; bitpos: [5]; default: 0;
+ *  Represents ch5 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA5    (BIT(5))
+#define SOC_ETM_CH_ENA5_M  (SOC_ETM_CH_ENA5_V << SOC_ETM_CH_ENA5_S)
+#define SOC_ETM_CH_ENA5_V  0x00000001U
+#define SOC_ETM_CH_ENA5_S  5
+/** SOC_ETM_CH_ENA6 : R/WTC/WTS; bitpos: [6]; default: 0;
+ *  Represents ch6 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA6    (BIT(6))
+#define SOC_ETM_CH_ENA6_M  (SOC_ETM_CH_ENA6_V << SOC_ETM_CH_ENA6_S)
+#define SOC_ETM_CH_ENA6_V  0x00000001U
+#define SOC_ETM_CH_ENA6_S  6
+/** SOC_ETM_CH_ENA7 : R/WTC/WTS; bitpos: [7]; default: 0;
+ *  Represents ch7 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA7    (BIT(7))
+#define SOC_ETM_CH_ENA7_M  (SOC_ETM_CH_ENA7_V << SOC_ETM_CH_ENA7_S)
+#define SOC_ETM_CH_ENA7_V  0x00000001U
+#define SOC_ETM_CH_ENA7_S  7
+/** SOC_ETM_CH_ENA8 : R/WTC/WTS; bitpos: [8]; default: 0;
+ *  Represents ch8 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA8    (BIT(8))
+#define SOC_ETM_CH_ENA8_M  (SOC_ETM_CH_ENA8_V << SOC_ETM_CH_ENA8_S)
+#define SOC_ETM_CH_ENA8_V  0x00000001U
+#define SOC_ETM_CH_ENA8_S  8
+/** SOC_ETM_CH_ENA9 : R/WTC/WTS; bitpos: [9]; default: 0;
+ *  Represents ch9 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA9    (BIT(9))
+#define SOC_ETM_CH_ENA9_M  (SOC_ETM_CH_ENA9_V << SOC_ETM_CH_ENA9_S)
+#define SOC_ETM_CH_ENA9_V  0x00000001U
+#define SOC_ETM_CH_ENA9_S  9
+/** SOC_ETM_CH_ENA10 : R/WTC/WTS; bitpos: [10]; default: 0;
+ *  Represents ch10 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA10    (BIT(10))
+#define SOC_ETM_CH_ENA10_M  (SOC_ETM_CH_ENA10_V << SOC_ETM_CH_ENA10_S)
+#define SOC_ETM_CH_ENA10_V  0x00000001U
+#define SOC_ETM_CH_ENA10_S  10
+/** SOC_ETM_CH_ENA11 : R/WTC/WTS; bitpos: [11]; default: 0;
+ *  Represents ch11 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA11    (BIT(11))
+#define SOC_ETM_CH_ENA11_M  (SOC_ETM_CH_ENA11_V << SOC_ETM_CH_ENA11_S)
+#define SOC_ETM_CH_ENA11_V  0x00000001U
+#define SOC_ETM_CH_ENA11_S  11
+/** SOC_ETM_CH_ENA12 : R/WTC/WTS; bitpos: [12]; default: 0;
+ *  Represents ch12 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA12    (BIT(12))
+#define SOC_ETM_CH_ENA12_M  (SOC_ETM_CH_ENA12_V << SOC_ETM_CH_ENA12_S)
+#define SOC_ETM_CH_ENA12_V  0x00000001U
+#define SOC_ETM_CH_ENA12_S  12
+/** SOC_ETM_CH_ENA13 : R/WTC/WTS; bitpos: [13]; default: 0;
+ *  Represents ch13 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA13    (BIT(13))
+#define SOC_ETM_CH_ENA13_M  (SOC_ETM_CH_ENA13_V << SOC_ETM_CH_ENA13_S)
+#define SOC_ETM_CH_ENA13_V  0x00000001U
+#define SOC_ETM_CH_ENA13_S  13
+/** SOC_ETM_CH_ENA14 : R/WTC/WTS; bitpos: [14]; default: 0;
+ *  Represents ch14 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA14    (BIT(14))
+#define SOC_ETM_CH_ENA14_M  (SOC_ETM_CH_ENA14_V << SOC_ETM_CH_ENA14_S)
+#define SOC_ETM_CH_ENA14_V  0x00000001U
+#define SOC_ETM_CH_ENA14_S  14
+/** SOC_ETM_CH_ENA15 : R/WTC/WTS; bitpos: [15]; default: 0;
+ *  Represents ch15 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA15    (BIT(15))
+#define SOC_ETM_CH_ENA15_M  (SOC_ETM_CH_ENA15_V << SOC_ETM_CH_ENA15_S)
+#define SOC_ETM_CH_ENA15_V  0x00000001U
+#define SOC_ETM_CH_ENA15_S  15
+/** SOC_ETM_CH_ENA16 : R/WTC/WTS; bitpos: [16]; default: 0;
+ *  Represents ch16 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA16    (BIT(16))
+#define SOC_ETM_CH_ENA16_M  (SOC_ETM_CH_ENA16_V << SOC_ETM_CH_ENA16_S)
+#define SOC_ETM_CH_ENA16_V  0x00000001U
+#define SOC_ETM_CH_ENA16_S  16
+/** SOC_ETM_CH_ENA17 : R/WTC/WTS; bitpos: [17]; default: 0;
+ *  Represents ch17 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA17    (BIT(17))
+#define SOC_ETM_CH_ENA17_M  (SOC_ETM_CH_ENA17_V << SOC_ETM_CH_ENA17_S)
+#define SOC_ETM_CH_ENA17_V  0x00000001U
+#define SOC_ETM_CH_ENA17_S  17
+/** SOC_ETM_CH_ENA18 : R/WTC/WTS; bitpos: [18]; default: 0;
+ *  Represents ch18 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA18    (BIT(18))
+#define SOC_ETM_CH_ENA18_M  (SOC_ETM_CH_ENA18_V << SOC_ETM_CH_ENA18_S)
+#define SOC_ETM_CH_ENA18_V  0x00000001U
+#define SOC_ETM_CH_ENA18_S  18
+/** SOC_ETM_CH_ENA19 : R/WTC/WTS; bitpos: [19]; default: 0;
+ *  Represents ch19 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA19    (BIT(19))
+#define SOC_ETM_CH_ENA19_M  (SOC_ETM_CH_ENA19_V << SOC_ETM_CH_ENA19_S)
+#define SOC_ETM_CH_ENA19_V  0x00000001U
+#define SOC_ETM_CH_ENA19_S  19
+/** SOC_ETM_CH_ENA20 : R/WTC/WTS; bitpos: [20]; default: 0;
+ *  Represents ch20 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA20    (BIT(20))
+#define SOC_ETM_CH_ENA20_M  (SOC_ETM_CH_ENA20_V << SOC_ETM_CH_ENA20_S)
+#define SOC_ETM_CH_ENA20_V  0x00000001U
+#define SOC_ETM_CH_ENA20_S  20
+/** SOC_ETM_CH_ENA21 : R/WTC/WTS; bitpos: [21]; default: 0;
+ *  Represents ch21 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA21    (BIT(21))
+#define SOC_ETM_CH_ENA21_M  (SOC_ETM_CH_ENA21_V << SOC_ETM_CH_ENA21_S)
+#define SOC_ETM_CH_ENA21_V  0x00000001U
+#define SOC_ETM_CH_ENA21_S  21
+/** SOC_ETM_CH_ENA22 : R/WTC/WTS; bitpos: [22]; default: 0;
+ *  Represents ch22 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA22    (BIT(22))
+#define SOC_ETM_CH_ENA22_M  (SOC_ETM_CH_ENA22_V << SOC_ETM_CH_ENA22_S)
+#define SOC_ETM_CH_ENA22_V  0x00000001U
+#define SOC_ETM_CH_ENA22_S  22
+/** SOC_ETM_CH_ENA23 : R/WTC/WTS; bitpos: [23]; default: 0;
+ *  Represents ch23 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA23    (BIT(23))
+#define SOC_ETM_CH_ENA23_M  (SOC_ETM_CH_ENA23_V << SOC_ETM_CH_ENA23_S)
+#define SOC_ETM_CH_ENA23_V  0x00000001U
+#define SOC_ETM_CH_ENA23_S  23
+/** SOC_ETM_CH_ENA24 : R/WTC/WTS; bitpos: [24]; default: 0;
+ *  Represents ch24 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA24    (BIT(24))
+#define SOC_ETM_CH_ENA24_M  (SOC_ETM_CH_ENA24_V << SOC_ETM_CH_ENA24_S)
+#define SOC_ETM_CH_ENA24_V  0x00000001U
+#define SOC_ETM_CH_ENA24_S  24
+/** SOC_ETM_CH_ENA25 : R/WTC/WTS; bitpos: [25]; default: 0;
+ *  Represents ch25 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA25    (BIT(25))
+#define SOC_ETM_CH_ENA25_M  (SOC_ETM_CH_ENA25_V << SOC_ETM_CH_ENA25_S)
+#define SOC_ETM_CH_ENA25_V  0x00000001U
+#define SOC_ETM_CH_ENA25_S  25
+/** SOC_ETM_CH_ENA26 : R/WTC/WTS; bitpos: [26]; default: 0;
+ *  Represents ch26 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA26    (BIT(26))
+#define SOC_ETM_CH_ENA26_M  (SOC_ETM_CH_ENA26_V << SOC_ETM_CH_ENA26_S)
+#define SOC_ETM_CH_ENA26_V  0x00000001U
+#define SOC_ETM_CH_ENA26_S  26
+/** SOC_ETM_CH_ENA27 : R/WTC/WTS; bitpos: [27]; default: 0;
+ *  Represents ch27 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA27    (BIT(27))
+#define SOC_ETM_CH_ENA27_M  (SOC_ETM_CH_ENA27_V << SOC_ETM_CH_ENA27_S)
+#define SOC_ETM_CH_ENA27_V  0x00000001U
+#define SOC_ETM_CH_ENA27_S  27
+/** SOC_ETM_CH_ENA28 : R/WTC/WTS; bitpos: [28]; default: 0;
+ *  Represents ch28 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA28    (BIT(28))
+#define SOC_ETM_CH_ENA28_M  (SOC_ETM_CH_ENA28_V << SOC_ETM_CH_ENA28_S)
+#define SOC_ETM_CH_ENA28_V  0x00000001U
+#define SOC_ETM_CH_ENA28_S  28
+/** SOC_ETM_CH_ENA29 : R/WTC/WTS; bitpos: [29]; default: 0;
+ *  Represents ch29 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA29    (BIT(29))
+#define SOC_ETM_CH_ENA29_M  (SOC_ETM_CH_ENA29_V << SOC_ETM_CH_ENA29_S)
+#define SOC_ETM_CH_ENA29_V  0x00000001U
+#define SOC_ETM_CH_ENA29_S  29
+/** SOC_ETM_CH_ENA30 : R/WTC/WTS; bitpos: [30]; default: 0;
+ *  Represents ch30 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA30    (BIT(30))
+#define SOC_ETM_CH_ENA30_M  (SOC_ETM_CH_ENA30_V << SOC_ETM_CH_ENA30_S)
+#define SOC_ETM_CH_ENA30_V  0x00000001U
+#define SOC_ETM_CH_ENA30_S  30
+/** SOC_ETM_CH_ENA31 : R/WTC/WTS; bitpos: [31]; default: 0;
+ *  Represents ch31 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA31    (BIT(31))
+#define SOC_ETM_CH_ENA31_M  (SOC_ETM_CH_ENA31_V << SOC_ETM_CH_ENA31_S)
+#define SOC_ETM_CH_ENA31_V  0x00000001U
+#define SOC_ETM_CH_ENA31_S  31
+
+/** SOC_ETM_CH_ENA_AD0_SET_REG register
+ *  Channel enable set register
+ */
+#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4)
+/** SOC_ETM_CH_SET0 : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable ch0.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET0    (BIT(0))
+#define SOC_ETM_CH_SET0_M  (SOC_ETM_CH_SET0_V << SOC_ETM_CH_SET0_S)
+#define SOC_ETM_CH_SET0_V  0x00000001U
+#define SOC_ETM_CH_SET0_S  0
+/** SOC_ETM_CH_SET1 : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable ch1.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET1    (BIT(1))
+#define SOC_ETM_CH_SET1_M  (SOC_ETM_CH_SET1_V << SOC_ETM_CH_SET1_S)
+#define SOC_ETM_CH_SET1_V  0x00000001U
+#define SOC_ETM_CH_SET1_S  1
+/** SOC_ETM_CH_SET2 : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable ch2.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET2    (BIT(2))
+#define SOC_ETM_CH_SET2_M  (SOC_ETM_CH_SET2_V << SOC_ETM_CH_SET2_S)
+#define SOC_ETM_CH_SET2_V  0x00000001U
+#define SOC_ETM_CH_SET2_S  2
+/** SOC_ETM_CH_SET3 : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable ch3.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET3    (BIT(3))
+#define SOC_ETM_CH_SET3_M  (SOC_ETM_CH_SET3_V << SOC_ETM_CH_SET3_S)
+#define SOC_ETM_CH_SET3_V  0x00000001U
+#define SOC_ETM_CH_SET3_S  3
+/** SOC_ETM_CH_SET4 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable ch4.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET4    (BIT(4))
+#define SOC_ETM_CH_SET4_M  (SOC_ETM_CH_SET4_V << SOC_ETM_CH_SET4_S)
+#define SOC_ETM_CH_SET4_V  0x00000001U
+#define SOC_ETM_CH_SET4_S  4
+/** SOC_ETM_CH_SET5 : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable ch5.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET5    (BIT(5))
+#define SOC_ETM_CH_SET5_M  (SOC_ETM_CH_SET5_V << SOC_ETM_CH_SET5_S)
+#define SOC_ETM_CH_SET5_V  0x00000001U
+#define SOC_ETM_CH_SET5_S  5
+/** SOC_ETM_CH_SET6 : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable ch6.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET6    (BIT(6))
+#define SOC_ETM_CH_SET6_M  (SOC_ETM_CH_SET6_V << SOC_ETM_CH_SET6_S)
+#define SOC_ETM_CH_SET6_V  0x00000001U
+#define SOC_ETM_CH_SET6_S  6
+/** SOC_ETM_CH_SET7 : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ch7.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET7    (BIT(7))
+#define SOC_ETM_CH_SET7_M  (SOC_ETM_CH_SET7_V << SOC_ETM_CH_SET7_S)
+#define SOC_ETM_CH_SET7_V  0x00000001U
+#define SOC_ETM_CH_SET7_S  7
+/** SOC_ETM_CH_SET8 : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable ch8.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET8    (BIT(8))
+#define SOC_ETM_CH_SET8_M  (SOC_ETM_CH_SET8_V << SOC_ETM_CH_SET8_S)
+#define SOC_ETM_CH_SET8_V  0x00000001U
+#define SOC_ETM_CH_SET8_S  8
+/** SOC_ETM_CH_SET9 : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable ch9.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET9    (BIT(9))
+#define SOC_ETM_CH_SET9_M  (SOC_ETM_CH_SET9_V << SOC_ETM_CH_SET9_S)
+#define SOC_ETM_CH_SET9_V  0x00000001U
+#define SOC_ETM_CH_SET9_S  9
+/** SOC_ETM_CH_SET10 : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable ch10.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET10    (BIT(10))
+#define SOC_ETM_CH_SET10_M  (SOC_ETM_CH_SET10_V << SOC_ETM_CH_SET10_S)
+#define SOC_ETM_CH_SET10_V  0x00000001U
+#define SOC_ETM_CH_SET10_S  10
+/** SOC_ETM_CH_SET11 : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable ch11.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET11    (BIT(11))
+#define SOC_ETM_CH_SET11_M  (SOC_ETM_CH_SET11_V << SOC_ETM_CH_SET11_S)
+#define SOC_ETM_CH_SET11_V  0x00000001U
+#define SOC_ETM_CH_SET11_S  11
+/** SOC_ETM_CH_SET12 : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable ch12.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET12    (BIT(12))
+#define SOC_ETM_CH_SET12_M  (SOC_ETM_CH_SET12_V << SOC_ETM_CH_SET12_S)
+#define SOC_ETM_CH_SET12_V  0x00000001U
+#define SOC_ETM_CH_SET12_S  12
+/** SOC_ETM_CH_SET13 : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable ch13.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET13    (BIT(13))
+#define SOC_ETM_CH_SET13_M  (SOC_ETM_CH_SET13_V << SOC_ETM_CH_SET13_S)
+#define SOC_ETM_CH_SET13_V  0x00000001U
+#define SOC_ETM_CH_SET13_S  13
+/** SOC_ETM_CH_SET14 : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable ch14.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET14    (BIT(14))
+#define SOC_ETM_CH_SET14_M  (SOC_ETM_CH_SET14_V << SOC_ETM_CH_SET14_S)
+#define SOC_ETM_CH_SET14_V  0x00000001U
+#define SOC_ETM_CH_SET14_S  14
+/** SOC_ETM_CH_SET15 : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable ch15.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET15    (BIT(15))
+#define SOC_ETM_CH_SET15_M  (SOC_ETM_CH_SET15_V << SOC_ETM_CH_SET15_S)
+#define SOC_ETM_CH_SET15_V  0x00000001U
+#define SOC_ETM_CH_SET15_S  15
+/** SOC_ETM_CH_SET16 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable ch16.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET16    (BIT(16))
+#define SOC_ETM_CH_SET16_M  (SOC_ETM_CH_SET16_V << SOC_ETM_CH_SET16_S)
+#define SOC_ETM_CH_SET16_V  0x00000001U
+#define SOC_ETM_CH_SET16_S  16
+/** SOC_ETM_CH_SET17 : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable ch17.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET17    (BIT(17))
+#define SOC_ETM_CH_SET17_M  (SOC_ETM_CH_SET17_V << SOC_ETM_CH_SET17_S)
+#define SOC_ETM_CH_SET17_V  0x00000001U
+#define SOC_ETM_CH_SET17_S  17
+/** SOC_ETM_CH_SET18 : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable ch18.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET18    (BIT(18))
+#define SOC_ETM_CH_SET18_M  (SOC_ETM_CH_SET18_V << SOC_ETM_CH_SET18_S)
+#define SOC_ETM_CH_SET18_V  0x00000001U
+#define SOC_ETM_CH_SET18_S  18
+/** SOC_ETM_CH_SET19 : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable ch19.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET19    (BIT(19))
+#define SOC_ETM_CH_SET19_M  (SOC_ETM_CH_SET19_V << SOC_ETM_CH_SET19_S)
+#define SOC_ETM_CH_SET19_V  0x00000001U
+#define SOC_ETM_CH_SET19_S  19
+/** SOC_ETM_CH_SET20 : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable ch20.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET20    (BIT(20))
+#define SOC_ETM_CH_SET20_M  (SOC_ETM_CH_SET20_V << SOC_ETM_CH_SET20_S)
+#define SOC_ETM_CH_SET20_V  0x00000001U
+#define SOC_ETM_CH_SET20_S  20
+/** SOC_ETM_CH_SET21 : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable ch21.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET21    (BIT(21))
+#define SOC_ETM_CH_SET21_M  (SOC_ETM_CH_SET21_V << SOC_ETM_CH_SET21_S)
+#define SOC_ETM_CH_SET21_V  0x00000001U
+#define SOC_ETM_CH_SET21_S  21
+/** SOC_ETM_CH_SET22 : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable ch22.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET22    (BIT(22))
+#define SOC_ETM_CH_SET22_M  (SOC_ETM_CH_SET22_V << SOC_ETM_CH_SET22_S)
+#define SOC_ETM_CH_SET22_V  0x00000001U
+#define SOC_ETM_CH_SET22_S  22
+/** SOC_ETM_CH_SET23 : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable ch23.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET23    (BIT(23))
+#define SOC_ETM_CH_SET23_M  (SOC_ETM_CH_SET23_V << SOC_ETM_CH_SET23_S)
+#define SOC_ETM_CH_SET23_V  0x00000001U
+#define SOC_ETM_CH_SET23_S  23
+/** SOC_ETM_CH_SET24 : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to enable ch24.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET24    (BIT(24))
+#define SOC_ETM_CH_SET24_M  (SOC_ETM_CH_SET24_V << SOC_ETM_CH_SET24_S)
+#define SOC_ETM_CH_SET24_V  0x00000001U
+#define SOC_ETM_CH_SET24_S  24
+/** SOC_ETM_CH_SET25 : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to enable ch25.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET25    (BIT(25))
+#define SOC_ETM_CH_SET25_M  (SOC_ETM_CH_SET25_V << SOC_ETM_CH_SET25_S)
+#define SOC_ETM_CH_SET25_V  0x00000001U
+#define SOC_ETM_CH_SET25_S  25
+/** SOC_ETM_CH_SET26 : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to enable ch26.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET26    (BIT(26))
+#define SOC_ETM_CH_SET26_M  (SOC_ETM_CH_SET26_V << SOC_ETM_CH_SET26_S)
+#define SOC_ETM_CH_SET26_V  0x00000001U
+#define SOC_ETM_CH_SET26_S  26
+/** SOC_ETM_CH_SET27 : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to enable ch27.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET27    (BIT(27))
+#define SOC_ETM_CH_SET27_M  (SOC_ETM_CH_SET27_V << SOC_ETM_CH_SET27_S)
+#define SOC_ETM_CH_SET27_V  0x00000001U
+#define SOC_ETM_CH_SET27_S  27
+/** SOC_ETM_CH_SET28 : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable ch28.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET28    (BIT(28))
+#define SOC_ETM_CH_SET28_M  (SOC_ETM_CH_SET28_V << SOC_ETM_CH_SET28_S)
+#define SOC_ETM_CH_SET28_V  0x00000001U
+#define SOC_ETM_CH_SET28_S  28
+/** SOC_ETM_CH_SET29 : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable ch29.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET29    (BIT(29))
+#define SOC_ETM_CH_SET29_M  (SOC_ETM_CH_SET29_V << SOC_ETM_CH_SET29_S)
+#define SOC_ETM_CH_SET29_V  0x00000001U
+#define SOC_ETM_CH_SET29_S  29
+/** SOC_ETM_CH_SET30 : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to enable ch30.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET30    (BIT(30))
+#define SOC_ETM_CH_SET30_M  (SOC_ETM_CH_SET30_V << SOC_ETM_CH_SET30_S)
+#define SOC_ETM_CH_SET30_V  0x00000001U
+#define SOC_ETM_CH_SET30_S  30
+/** SOC_ETM_CH_SET31 : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to enable ch31.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET31    (BIT(31))
+#define SOC_ETM_CH_SET31_M  (SOC_ETM_CH_SET31_V << SOC_ETM_CH_SET31_S)
+#define SOC_ETM_CH_SET31_V  0x00000001U
+#define SOC_ETM_CH_SET31_S  31
+
+/** SOC_ETM_CH_ENA_AD0_CLR_REG register
+ *  Channel enable clear register
+ */
+#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8)
+/** SOC_ETM_CH_CLR0 : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear ch0 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR0    (BIT(0))
+#define SOC_ETM_CH_CLR0_M  (SOC_ETM_CH_CLR0_V << SOC_ETM_CH_CLR0_S)
+#define SOC_ETM_CH_CLR0_V  0x00000001U
+#define SOC_ETM_CH_CLR0_S  0
+/** SOC_ETM_CH_CLR1 : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear ch1 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR1    (BIT(1))
+#define SOC_ETM_CH_CLR1_M  (SOC_ETM_CH_CLR1_V << SOC_ETM_CH_CLR1_S)
+#define SOC_ETM_CH_CLR1_V  0x00000001U
+#define SOC_ETM_CH_CLR1_S  1
+/** SOC_ETM_CH_CLR2 : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear ch2 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR2    (BIT(2))
+#define SOC_ETM_CH_CLR2_M  (SOC_ETM_CH_CLR2_V << SOC_ETM_CH_CLR2_S)
+#define SOC_ETM_CH_CLR2_V  0x00000001U
+#define SOC_ETM_CH_CLR2_S  2
+/** SOC_ETM_CH_CLR3 : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear ch3 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR3    (BIT(3))
+#define SOC_ETM_CH_CLR3_M  (SOC_ETM_CH_CLR3_V << SOC_ETM_CH_CLR3_S)
+#define SOC_ETM_CH_CLR3_V  0x00000001U
+#define SOC_ETM_CH_CLR3_S  3
+/** SOC_ETM_CH_CLR4 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear ch4 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR4    (BIT(4))
+#define SOC_ETM_CH_CLR4_M  (SOC_ETM_CH_CLR4_V << SOC_ETM_CH_CLR4_S)
+#define SOC_ETM_CH_CLR4_V  0x00000001U
+#define SOC_ETM_CH_CLR4_S  4
+/** SOC_ETM_CH_CLR5 : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear ch5 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR5    (BIT(5))
+#define SOC_ETM_CH_CLR5_M  (SOC_ETM_CH_CLR5_V << SOC_ETM_CH_CLR5_S)
+#define SOC_ETM_CH_CLR5_V  0x00000001U
+#define SOC_ETM_CH_CLR5_S  5
+/** SOC_ETM_CH_CLR6 : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear ch6 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR6    (BIT(6))
+#define SOC_ETM_CH_CLR6_M  (SOC_ETM_CH_CLR6_V << SOC_ETM_CH_CLR6_S)
+#define SOC_ETM_CH_CLR6_V  0x00000001U
+#define SOC_ETM_CH_CLR6_S  6
+/** SOC_ETM_CH_CLR7 : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear ch7 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR7    (BIT(7))
+#define SOC_ETM_CH_CLR7_M  (SOC_ETM_CH_CLR7_V << SOC_ETM_CH_CLR7_S)
+#define SOC_ETM_CH_CLR7_V  0x00000001U
+#define SOC_ETM_CH_CLR7_S  7
+/** SOC_ETM_CH_CLR8 : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear ch8 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR8    (BIT(8))
+#define SOC_ETM_CH_CLR8_M  (SOC_ETM_CH_CLR8_V << SOC_ETM_CH_CLR8_S)
+#define SOC_ETM_CH_CLR8_V  0x00000001U
+#define SOC_ETM_CH_CLR8_S  8
+/** SOC_ETM_CH_CLR9 : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear ch9 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR9    (BIT(9))
+#define SOC_ETM_CH_CLR9_M  (SOC_ETM_CH_CLR9_V << SOC_ETM_CH_CLR9_S)
+#define SOC_ETM_CH_CLR9_V  0x00000001U
+#define SOC_ETM_CH_CLR9_S  9
+/** SOC_ETM_CH_CLR10 : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear ch10 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR10    (BIT(10))
+#define SOC_ETM_CH_CLR10_M  (SOC_ETM_CH_CLR10_V << SOC_ETM_CH_CLR10_S)
+#define SOC_ETM_CH_CLR10_V  0x00000001U
+#define SOC_ETM_CH_CLR10_S  10
+/** SOC_ETM_CH_CLR11 : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear ch11 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR11    (BIT(11))
+#define SOC_ETM_CH_CLR11_M  (SOC_ETM_CH_CLR11_V << SOC_ETM_CH_CLR11_S)
+#define SOC_ETM_CH_CLR11_V  0x00000001U
+#define SOC_ETM_CH_CLR11_S  11
+/** SOC_ETM_CH_CLR12 : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear ch12 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR12    (BIT(12))
+#define SOC_ETM_CH_CLR12_M  (SOC_ETM_CH_CLR12_V << SOC_ETM_CH_CLR12_S)
+#define SOC_ETM_CH_CLR12_V  0x00000001U
+#define SOC_ETM_CH_CLR12_S  12
+/** SOC_ETM_CH_CLR13 : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear ch13 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR13    (BIT(13))
+#define SOC_ETM_CH_CLR13_M  (SOC_ETM_CH_CLR13_V << SOC_ETM_CH_CLR13_S)
+#define SOC_ETM_CH_CLR13_V  0x00000001U
+#define SOC_ETM_CH_CLR13_S  13
+/** SOC_ETM_CH_CLR14 : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear ch14 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR14    (BIT(14))
+#define SOC_ETM_CH_CLR14_M  (SOC_ETM_CH_CLR14_V << SOC_ETM_CH_CLR14_S)
+#define SOC_ETM_CH_CLR14_V  0x00000001U
+#define SOC_ETM_CH_CLR14_S  14
+/** SOC_ETM_CH_CLR15 : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear ch15 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR15    (BIT(15))
+#define SOC_ETM_CH_CLR15_M  (SOC_ETM_CH_CLR15_V << SOC_ETM_CH_CLR15_S)
+#define SOC_ETM_CH_CLR15_V  0x00000001U
+#define SOC_ETM_CH_CLR15_S  15
+/** SOC_ETM_CH_CLR16 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear ch16 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR16    (BIT(16))
+#define SOC_ETM_CH_CLR16_M  (SOC_ETM_CH_CLR16_V << SOC_ETM_CH_CLR16_S)
+#define SOC_ETM_CH_CLR16_V  0x00000001U
+#define SOC_ETM_CH_CLR16_S  16
+/** SOC_ETM_CH_CLR17 : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear ch17 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR17    (BIT(17))
+#define SOC_ETM_CH_CLR17_M  (SOC_ETM_CH_CLR17_V << SOC_ETM_CH_CLR17_S)
+#define SOC_ETM_CH_CLR17_V  0x00000001U
+#define SOC_ETM_CH_CLR17_S  17
+/** SOC_ETM_CH_CLR18 : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear ch18 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR18    (BIT(18))
+#define SOC_ETM_CH_CLR18_M  (SOC_ETM_CH_CLR18_V << SOC_ETM_CH_CLR18_S)
+#define SOC_ETM_CH_CLR18_V  0x00000001U
+#define SOC_ETM_CH_CLR18_S  18
+/** SOC_ETM_CH_CLR19 : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear ch19 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR19    (BIT(19))
+#define SOC_ETM_CH_CLR19_M  (SOC_ETM_CH_CLR19_V << SOC_ETM_CH_CLR19_S)
+#define SOC_ETM_CH_CLR19_V  0x00000001U
+#define SOC_ETM_CH_CLR19_S  19
+/** SOC_ETM_CH_CLR20 : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear ch20 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR20    (BIT(20))
+#define SOC_ETM_CH_CLR20_M  (SOC_ETM_CH_CLR20_V << SOC_ETM_CH_CLR20_S)
+#define SOC_ETM_CH_CLR20_V  0x00000001U
+#define SOC_ETM_CH_CLR20_S  20
+/** SOC_ETM_CH_CLR21 : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear ch21 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR21    (BIT(21))
+#define SOC_ETM_CH_CLR21_M  (SOC_ETM_CH_CLR21_V << SOC_ETM_CH_CLR21_S)
+#define SOC_ETM_CH_CLR21_V  0x00000001U
+#define SOC_ETM_CH_CLR21_S  21
+/** SOC_ETM_CH_CLR22 : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear ch22 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR22    (BIT(22))
+#define SOC_ETM_CH_CLR22_M  (SOC_ETM_CH_CLR22_V << SOC_ETM_CH_CLR22_S)
+#define SOC_ETM_CH_CLR22_V  0x00000001U
+#define SOC_ETM_CH_CLR22_S  22
+/** SOC_ETM_CH_CLR23 : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear ch23 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR23    (BIT(23))
+#define SOC_ETM_CH_CLR23_M  (SOC_ETM_CH_CLR23_V << SOC_ETM_CH_CLR23_S)
+#define SOC_ETM_CH_CLR23_V  0x00000001U
+#define SOC_ETM_CH_CLR23_S  23
+/** SOC_ETM_CH_CLR24 : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear ch24 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR24    (BIT(24))
+#define SOC_ETM_CH_CLR24_M  (SOC_ETM_CH_CLR24_V << SOC_ETM_CH_CLR24_S)
+#define SOC_ETM_CH_CLR24_V  0x00000001U
+#define SOC_ETM_CH_CLR24_S  24
+/** SOC_ETM_CH_CLR25 : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear ch25 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR25    (BIT(25))
+#define SOC_ETM_CH_CLR25_M  (SOC_ETM_CH_CLR25_V << SOC_ETM_CH_CLR25_S)
+#define SOC_ETM_CH_CLR25_V  0x00000001U
+#define SOC_ETM_CH_CLR25_S  25
+/** SOC_ETM_CH_CLR26 : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear ch26 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR26    (BIT(26))
+#define SOC_ETM_CH_CLR26_M  (SOC_ETM_CH_CLR26_V << SOC_ETM_CH_CLR26_S)
+#define SOC_ETM_CH_CLR26_V  0x00000001U
+#define SOC_ETM_CH_CLR26_S  26
+/** SOC_ETM_CH_CLR27 : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear ch27 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR27    (BIT(27))
+#define SOC_ETM_CH_CLR27_M  (SOC_ETM_CH_CLR27_V << SOC_ETM_CH_CLR27_S)
+#define SOC_ETM_CH_CLR27_V  0x00000001U
+#define SOC_ETM_CH_CLR27_S  27
+/** SOC_ETM_CH_CLR28 : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear ch28 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR28    (BIT(28))
+#define SOC_ETM_CH_CLR28_M  (SOC_ETM_CH_CLR28_V << SOC_ETM_CH_CLR28_S)
+#define SOC_ETM_CH_CLR28_V  0x00000001U
+#define SOC_ETM_CH_CLR28_S  28
+/** SOC_ETM_CH_CLR29 : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear ch29 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR29    (BIT(29))
+#define SOC_ETM_CH_CLR29_M  (SOC_ETM_CH_CLR29_V << SOC_ETM_CH_CLR29_S)
+#define SOC_ETM_CH_CLR29_V  0x00000001U
+#define SOC_ETM_CH_CLR29_S  29
+/** SOC_ETM_CH_CLR30 : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear ch30 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR30    (BIT(30))
+#define SOC_ETM_CH_CLR30_M  (SOC_ETM_CH_CLR30_V << SOC_ETM_CH_CLR30_S)
+#define SOC_ETM_CH_CLR30_V  0x00000001U
+#define SOC_ETM_CH_CLR30_S  30
+/** SOC_ETM_CH_CLR31 : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear ch31 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR31    (BIT(31))
+#define SOC_ETM_CH_CLR31_M  (SOC_ETM_CH_CLR31_V << SOC_ETM_CH_CLR31_S)
+#define SOC_ETM_CH_CLR31_V  0x00000001U
+#define SOC_ETM_CH_CLR31_S  31
+
+/** SOC_ETM_CH_ENA_AD1_REG register
+ *  Channel enable status register
+ */
+#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc)
+/** SOC_ETM_CH_ENA32 : R/WTC/WTS; bitpos: [0]; default: 0;
+ *  Represents ch32 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA32    (BIT(0))
+#define SOC_ETM_CH_ENA32_M  (SOC_ETM_CH_ENA32_V << SOC_ETM_CH_ENA32_S)
+#define SOC_ETM_CH_ENA32_V  0x00000001U
+#define SOC_ETM_CH_ENA32_S  0
+/** SOC_ETM_CH_ENA33 : R/WTC/WTS; bitpos: [1]; default: 0;
+ *  Represents ch33 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA33    (BIT(1))
+#define SOC_ETM_CH_ENA33_M  (SOC_ETM_CH_ENA33_V << SOC_ETM_CH_ENA33_S)
+#define SOC_ETM_CH_ENA33_V  0x00000001U
+#define SOC_ETM_CH_ENA33_S  1
+/** SOC_ETM_CH_ENA34 : R/WTC/WTS; bitpos: [2]; default: 0;
+ *  Represents ch34 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA34    (BIT(2))
+#define SOC_ETM_CH_ENA34_M  (SOC_ETM_CH_ENA34_V << SOC_ETM_CH_ENA34_S)
+#define SOC_ETM_CH_ENA34_V  0x00000001U
+#define SOC_ETM_CH_ENA34_S  2
+/** SOC_ETM_CH_ENA35 : R/WTC/WTS; bitpos: [3]; default: 0;
+ *  Represents ch35 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA35    (BIT(3))
+#define SOC_ETM_CH_ENA35_M  (SOC_ETM_CH_ENA35_V << SOC_ETM_CH_ENA35_S)
+#define SOC_ETM_CH_ENA35_V  0x00000001U
+#define SOC_ETM_CH_ENA35_S  3
+/** SOC_ETM_CH_ENA36 : R/WTC/WTS; bitpos: [4]; default: 0;
+ *  Represents ch36 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA36    (BIT(4))
+#define SOC_ETM_CH_ENA36_M  (SOC_ETM_CH_ENA36_V << SOC_ETM_CH_ENA36_S)
+#define SOC_ETM_CH_ENA36_V  0x00000001U
+#define SOC_ETM_CH_ENA36_S  4
+/** SOC_ETM_CH_ENA37 : R/WTC/WTS; bitpos: [5]; default: 0;
+ *  Represents ch37 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA37    (BIT(5))
+#define SOC_ETM_CH_ENA37_M  (SOC_ETM_CH_ENA37_V << SOC_ETM_CH_ENA37_S)
+#define SOC_ETM_CH_ENA37_V  0x00000001U
+#define SOC_ETM_CH_ENA37_S  5
+/** SOC_ETM_CH_ENA38 : R/WTC/WTS; bitpos: [6]; default: 0;
+ *  Represents ch38 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA38    (BIT(6))
+#define SOC_ETM_CH_ENA38_M  (SOC_ETM_CH_ENA38_V << SOC_ETM_CH_ENA38_S)
+#define SOC_ETM_CH_ENA38_V  0x00000001U
+#define SOC_ETM_CH_ENA38_S  6
+/** SOC_ETM_CH_ENA39 : R/WTC/WTS; bitpos: [7]; default: 0;
+ *  Represents ch39 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA39    (BIT(7))
+#define SOC_ETM_CH_ENA39_M  (SOC_ETM_CH_ENA39_V << SOC_ETM_CH_ENA39_S)
+#define SOC_ETM_CH_ENA39_V  0x00000001U
+#define SOC_ETM_CH_ENA39_S  7
+/** SOC_ETM_CH_ENA40 : R/WTC/WTS; bitpos: [8]; default: 0;
+ *  Represents ch40 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA40    (BIT(8))
+#define SOC_ETM_CH_ENA40_M  (SOC_ETM_CH_ENA40_V << SOC_ETM_CH_ENA40_S)
+#define SOC_ETM_CH_ENA40_V  0x00000001U
+#define SOC_ETM_CH_ENA40_S  8
+/** SOC_ETM_CH_ENA41 : R/WTC/WTS; bitpos: [9]; default: 0;
+ *  Represents ch41 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA41    (BIT(9))
+#define SOC_ETM_CH_ENA41_M  (SOC_ETM_CH_ENA41_V << SOC_ETM_CH_ENA41_S)
+#define SOC_ETM_CH_ENA41_V  0x00000001U
+#define SOC_ETM_CH_ENA41_S  9
+/** SOC_ETM_CH_ENA42 : R/WTC/WTS; bitpos: [10]; default: 0;
+ *  Represents ch42 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA42    (BIT(10))
+#define SOC_ETM_CH_ENA42_M  (SOC_ETM_CH_ENA42_V << SOC_ETM_CH_ENA42_S)
+#define SOC_ETM_CH_ENA42_V  0x00000001U
+#define SOC_ETM_CH_ENA42_S  10
+/** SOC_ETM_CH_ENA43 : R/WTC/WTS; bitpos: [11]; default: 0;
+ *  Represents ch43 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA43    (BIT(11))
+#define SOC_ETM_CH_ENA43_M  (SOC_ETM_CH_ENA43_V << SOC_ETM_CH_ENA43_S)
+#define SOC_ETM_CH_ENA43_V  0x00000001U
+#define SOC_ETM_CH_ENA43_S  11
+/** SOC_ETM_CH_ENA44 : R/WTC/WTS; bitpos: [12]; default: 0;
+ *  Represents ch44 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA44    (BIT(12))
+#define SOC_ETM_CH_ENA44_M  (SOC_ETM_CH_ENA44_V << SOC_ETM_CH_ENA44_S)
+#define SOC_ETM_CH_ENA44_V  0x00000001U
+#define SOC_ETM_CH_ENA44_S  12
+/** SOC_ETM_CH_ENA45 : R/WTC/WTS; bitpos: [13]; default: 0;
+ *  Represents ch45 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA45    (BIT(13))
+#define SOC_ETM_CH_ENA45_M  (SOC_ETM_CH_ENA45_V << SOC_ETM_CH_ENA45_S)
+#define SOC_ETM_CH_ENA45_V  0x00000001U
+#define SOC_ETM_CH_ENA45_S  13
+/** SOC_ETM_CH_ENA46 : R/WTC/WTS; bitpos: [14]; default: 0;
+ *  Represents ch46 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA46    (BIT(14))
+#define SOC_ETM_CH_ENA46_M  (SOC_ETM_CH_ENA46_V << SOC_ETM_CH_ENA46_S)
+#define SOC_ETM_CH_ENA46_V  0x00000001U
+#define SOC_ETM_CH_ENA46_S  14
+/** SOC_ETM_CH_ENA47 : R/WTC/WTS; bitpos: [15]; default: 0;
+ *  Represents ch47 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA47    (BIT(15))
+#define SOC_ETM_CH_ENA47_M  (SOC_ETM_CH_ENA47_V << SOC_ETM_CH_ENA47_S)
+#define SOC_ETM_CH_ENA47_V  0x00000001U
+#define SOC_ETM_CH_ENA47_S  15
+/** SOC_ETM_CH_ENA48 : R/WTC/WTS; bitpos: [16]; default: 0;
+ *  Represents ch48 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA48    (BIT(16))
+#define SOC_ETM_CH_ENA48_M  (SOC_ETM_CH_ENA48_V << SOC_ETM_CH_ENA48_S)
+#define SOC_ETM_CH_ENA48_V  0x00000001U
+#define SOC_ETM_CH_ENA48_S  16
+/** SOC_ETM_CH_ENA49 : R/WTC/WTS; bitpos: [17]; default: 0;
+ *  Represents ch49 enable status.
+ *  0: Disable
+ *  1: Enable
+ */
+#define SOC_ETM_CH_ENA49    (BIT(17))
+#define SOC_ETM_CH_ENA49_M  (SOC_ETM_CH_ENA49_V << SOC_ETM_CH_ENA49_S)
+#define SOC_ETM_CH_ENA49_V  0x00000001U
+#define SOC_ETM_CH_ENA49_S  17
+
+/** SOC_ETM_CH_ENA_AD1_SET_REG register
+ *  Channel enable set register
+ */
+#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10)
+/** SOC_ETM_CH_SET32 : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable ch32.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET32    (BIT(0))
+#define SOC_ETM_CH_SET32_M  (SOC_ETM_CH_SET32_V << SOC_ETM_CH_SET32_S)
+#define SOC_ETM_CH_SET32_V  0x00000001U
+#define SOC_ETM_CH_SET32_S  0
+/** SOC_ETM_CH_SET33 : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable ch33.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET33    (BIT(1))
+#define SOC_ETM_CH_SET33_M  (SOC_ETM_CH_SET33_V << SOC_ETM_CH_SET33_S)
+#define SOC_ETM_CH_SET33_V  0x00000001U
+#define SOC_ETM_CH_SET33_S  1
+/** SOC_ETM_CH_SET34 : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable ch34.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET34    (BIT(2))
+#define SOC_ETM_CH_SET34_M  (SOC_ETM_CH_SET34_V << SOC_ETM_CH_SET34_S)
+#define SOC_ETM_CH_SET34_V  0x00000001U
+#define SOC_ETM_CH_SET34_S  2
+/** SOC_ETM_CH_SET35 : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable ch35.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET35    (BIT(3))
+#define SOC_ETM_CH_SET35_M  (SOC_ETM_CH_SET35_V << SOC_ETM_CH_SET35_S)
+#define SOC_ETM_CH_SET35_V  0x00000001U
+#define SOC_ETM_CH_SET35_S  3
+/** SOC_ETM_CH_SET36 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable ch36.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET36    (BIT(4))
+#define SOC_ETM_CH_SET36_M  (SOC_ETM_CH_SET36_V << SOC_ETM_CH_SET36_S)
+#define SOC_ETM_CH_SET36_V  0x00000001U
+#define SOC_ETM_CH_SET36_S  4
+/** SOC_ETM_CH_SET37 : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable ch37.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET37    (BIT(5))
+#define SOC_ETM_CH_SET37_M  (SOC_ETM_CH_SET37_V << SOC_ETM_CH_SET37_S)
+#define SOC_ETM_CH_SET37_V  0x00000001U
+#define SOC_ETM_CH_SET37_S  5
+/** SOC_ETM_CH_SET38 : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable ch38.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET38    (BIT(6))
+#define SOC_ETM_CH_SET38_M  (SOC_ETM_CH_SET38_V << SOC_ETM_CH_SET38_S)
+#define SOC_ETM_CH_SET38_V  0x00000001U
+#define SOC_ETM_CH_SET38_S  6
+/** SOC_ETM_CH_SET39 : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ch39.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET39    (BIT(7))
+#define SOC_ETM_CH_SET39_M  (SOC_ETM_CH_SET39_V << SOC_ETM_CH_SET39_S)
+#define SOC_ETM_CH_SET39_V  0x00000001U
+#define SOC_ETM_CH_SET39_S  7
+/** SOC_ETM_CH_SET40 : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable ch40.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET40    (BIT(8))
+#define SOC_ETM_CH_SET40_M  (SOC_ETM_CH_SET40_V << SOC_ETM_CH_SET40_S)
+#define SOC_ETM_CH_SET40_V  0x00000001U
+#define SOC_ETM_CH_SET40_S  8
+/** SOC_ETM_CH_SET41 : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable ch41.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET41    (BIT(9))
+#define SOC_ETM_CH_SET41_M  (SOC_ETM_CH_SET41_V << SOC_ETM_CH_SET41_S)
+#define SOC_ETM_CH_SET41_V  0x00000001U
+#define SOC_ETM_CH_SET41_S  9
+/** SOC_ETM_CH_SET42 : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable ch42.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET42    (BIT(10))
+#define SOC_ETM_CH_SET42_M  (SOC_ETM_CH_SET42_V << SOC_ETM_CH_SET42_S)
+#define SOC_ETM_CH_SET42_V  0x00000001U
+#define SOC_ETM_CH_SET42_S  10
+/** SOC_ETM_CH_SET43 : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable ch43.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET43    (BIT(11))
+#define SOC_ETM_CH_SET43_M  (SOC_ETM_CH_SET43_V << SOC_ETM_CH_SET43_S)
+#define SOC_ETM_CH_SET43_V  0x00000001U
+#define SOC_ETM_CH_SET43_S  11
+/** SOC_ETM_CH_SET44 : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable ch44.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET44    (BIT(12))
+#define SOC_ETM_CH_SET44_M  (SOC_ETM_CH_SET44_V << SOC_ETM_CH_SET44_S)
+#define SOC_ETM_CH_SET44_V  0x00000001U
+#define SOC_ETM_CH_SET44_S  12
+/** SOC_ETM_CH_SET45 : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable ch45.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET45    (BIT(13))
+#define SOC_ETM_CH_SET45_M  (SOC_ETM_CH_SET45_V << SOC_ETM_CH_SET45_S)
+#define SOC_ETM_CH_SET45_V  0x00000001U
+#define SOC_ETM_CH_SET45_S  13
+/** SOC_ETM_CH_SET46 : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable ch46.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET46    (BIT(14))
+#define SOC_ETM_CH_SET46_M  (SOC_ETM_CH_SET46_V << SOC_ETM_CH_SET46_S)
+#define SOC_ETM_CH_SET46_V  0x00000001U
+#define SOC_ETM_CH_SET46_S  14
+/** SOC_ETM_CH_SET47 : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable ch47.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET47    (BIT(15))
+#define SOC_ETM_CH_SET47_M  (SOC_ETM_CH_SET47_V << SOC_ETM_CH_SET47_S)
+#define SOC_ETM_CH_SET47_V  0x00000001U
+#define SOC_ETM_CH_SET47_S  15
+/** SOC_ETM_CH_SET48 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable ch48.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET48    (BIT(16))
+#define SOC_ETM_CH_SET48_M  (SOC_ETM_CH_SET48_V << SOC_ETM_CH_SET48_S)
+#define SOC_ETM_CH_SET48_V  0x00000001U
+#define SOC_ETM_CH_SET48_S  16
+/** SOC_ETM_CH_SET49 : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable ch49.
+ *  0: Invalid, No effect
+ *  1: Enable
+ */
+#define SOC_ETM_CH_SET49    (BIT(17))
+#define SOC_ETM_CH_SET49_M  (SOC_ETM_CH_SET49_V << SOC_ETM_CH_SET49_S)
+#define SOC_ETM_CH_SET49_V  0x00000001U
+#define SOC_ETM_CH_SET49_S  17
+
+/** SOC_ETM_CH_ENA_AD1_CLR_REG register
+ *  Channel enable clear register
+ */
+#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14)
+/** SOC_ETM_CH_CLR32 : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear ch32 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR32    (BIT(0))
+#define SOC_ETM_CH_CLR32_M  (SOC_ETM_CH_CLR32_V << SOC_ETM_CH_CLR32_S)
+#define SOC_ETM_CH_CLR32_V  0x00000001U
+#define SOC_ETM_CH_CLR32_S  0
+/** SOC_ETM_CH_CLR33 : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear ch33 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR33    (BIT(1))
+#define SOC_ETM_CH_CLR33_M  (SOC_ETM_CH_CLR33_V << SOC_ETM_CH_CLR33_S)
+#define SOC_ETM_CH_CLR33_V  0x00000001U
+#define SOC_ETM_CH_CLR33_S  1
+/** SOC_ETM_CH_CLR34 : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear ch34 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR34    (BIT(2))
+#define SOC_ETM_CH_CLR34_M  (SOC_ETM_CH_CLR34_V << SOC_ETM_CH_CLR34_S)
+#define SOC_ETM_CH_CLR34_V  0x00000001U
+#define SOC_ETM_CH_CLR34_S  2
+/** SOC_ETM_CH_CLR35 : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear ch35 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR35    (BIT(3))
+#define SOC_ETM_CH_CLR35_M  (SOC_ETM_CH_CLR35_V << SOC_ETM_CH_CLR35_S)
+#define SOC_ETM_CH_CLR35_V  0x00000001U
+#define SOC_ETM_CH_CLR35_S  3
+/** SOC_ETM_CH_CLR36 : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear ch36 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR36    (BIT(4))
+#define SOC_ETM_CH_CLR36_M  (SOC_ETM_CH_CLR36_V << SOC_ETM_CH_CLR36_S)
+#define SOC_ETM_CH_CLR36_V  0x00000001U
+#define SOC_ETM_CH_CLR36_S  4
+/** SOC_ETM_CH_CLR37 : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear ch37 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR37    (BIT(5))
+#define SOC_ETM_CH_CLR37_M  (SOC_ETM_CH_CLR37_V << SOC_ETM_CH_CLR37_S)
+#define SOC_ETM_CH_CLR37_V  0x00000001U
+#define SOC_ETM_CH_CLR37_S  5
+/** SOC_ETM_CH_CLR38 : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear ch38 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR38    (BIT(6))
+#define SOC_ETM_CH_CLR38_M  (SOC_ETM_CH_CLR38_V << SOC_ETM_CH_CLR38_S)
+#define SOC_ETM_CH_CLR38_V  0x00000001U
+#define SOC_ETM_CH_CLR38_S  6
+/** SOC_ETM_CH_CLR39 : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear ch39 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR39    (BIT(7))
+#define SOC_ETM_CH_CLR39_M  (SOC_ETM_CH_CLR39_V << SOC_ETM_CH_CLR39_S)
+#define SOC_ETM_CH_CLR39_V  0x00000001U
+#define SOC_ETM_CH_CLR39_S  7
+/** SOC_ETM_CH_CLR40 : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear ch40 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR40    (BIT(8))
+#define SOC_ETM_CH_CLR40_M  (SOC_ETM_CH_CLR40_V << SOC_ETM_CH_CLR40_S)
+#define SOC_ETM_CH_CLR40_V  0x00000001U
+#define SOC_ETM_CH_CLR40_S  8
+/** SOC_ETM_CH_CLR41 : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear ch41 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR41    (BIT(9))
+#define SOC_ETM_CH_CLR41_M  (SOC_ETM_CH_CLR41_V << SOC_ETM_CH_CLR41_S)
+#define SOC_ETM_CH_CLR41_V  0x00000001U
+#define SOC_ETM_CH_CLR41_S  9
+/** SOC_ETM_CH_CLR42 : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear ch42 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR42    (BIT(10))
+#define SOC_ETM_CH_CLR42_M  (SOC_ETM_CH_CLR42_V << SOC_ETM_CH_CLR42_S)
+#define SOC_ETM_CH_CLR42_V  0x00000001U
+#define SOC_ETM_CH_CLR42_S  10
+/** SOC_ETM_CH_CLR43 : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear ch43 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR43    (BIT(11))
+#define SOC_ETM_CH_CLR43_M  (SOC_ETM_CH_CLR43_V << SOC_ETM_CH_CLR43_S)
+#define SOC_ETM_CH_CLR43_V  0x00000001U
+#define SOC_ETM_CH_CLR43_S  11
+/** SOC_ETM_CH_CLR44 : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear ch44 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR44    (BIT(12))
+#define SOC_ETM_CH_CLR44_M  (SOC_ETM_CH_CLR44_V << SOC_ETM_CH_CLR44_S)
+#define SOC_ETM_CH_CLR44_V  0x00000001U
+#define SOC_ETM_CH_CLR44_S  12
+/** SOC_ETM_CH_CLR45 : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear ch45 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR45    (BIT(13))
+#define SOC_ETM_CH_CLR45_M  (SOC_ETM_CH_CLR45_V << SOC_ETM_CH_CLR45_S)
+#define SOC_ETM_CH_CLR45_V  0x00000001U
+#define SOC_ETM_CH_CLR45_S  13
+/** SOC_ETM_CH_CLR46 : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear ch46 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR46    (BIT(14))
+#define SOC_ETM_CH_CLR46_M  (SOC_ETM_CH_CLR46_V << SOC_ETM_CH_CLR46_S)
+#define SOC_ETM_CH_CLR46_V  0x00000001U
+#define SOC_ETM_CH_CLR46_S  14
+/** SOC_ETM_CH_CLR47 : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear ch47 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR47    (BIT(15))
+#define SOC_ETM_CH_CLR47_M  (SOC_ETM_CH_CLR47_V << SOC_ETM_CH_CLR47_S)
+#define SOC_ETM_CH_CLR47_V  0x00000001U
+#define SOC_ETM_CH_CLR47_S  15
+/** SOC_ETM_CH_CLR48 : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear ch48 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR48    (BIT(16))
+#define SOC_ETM_CH_CLR48_M  (SOC_ETM_CH_CLR48_V << SOC_ETM_CH_CLR48_S)
+#define SOC_ETM_CH_CLR48_V  0x00000001U
+#define SOC_ETM_CH_CLR48_S  16
+/** SOC_ETM_CH_CLR49 : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear ch49 enable.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_CH_CLR49    (BIT(17))
+#define SOC_ETM_CH_CLR49_M  (SOC_ETM_CH_CLR49_V << SOC_ETM_CH_CLR49_S)
+#define SOC_ETM_CH_CLR49_V  0x00000001U
+#define SOC_ETM_CH_CLR49_S  17
+
+/** SOC_ETM_CH0_EVT_ID_REG register
+ *  Channel0 event id register
+ */
+#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18)
+/** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch0_evt_id
+ */
+#define SOC_ETM_CH0_EVT_ID    0x000000FFU
+#define SOC_ETM_CH0_EVT_ID_M  (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S)
+#define SOC_ETM_CH0_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH0_EVT_ID_S  0
+
+/** SOC_ETM_CH0_TASK_ID_REG register
+ *  Channel0 task id register
+ */
+#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c)
+/** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch0_task_id
+ */
+#define SOC_ETM_CH0_TASK_ID    0x000000FFU
+#define SOC_ETM_CH0_TASK_ID_M  (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S)
+#define SOC_ETM_CH0_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH0_TASK_ID_S  0
+
+/** SOC_ETM_CH1_EVT_ID_REG register
+ *  Channel1 event id register
+ */
+#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20)
+/** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch1_evt_id
+ */
+#define SOC_ETM_CH1_EVT_ID    0x000000FFU
+#define SOC_ETM_CH1_EVT_ID_M  (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S)
+#define SOC_ETM_CH1_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH1_EVT_ID_S  0
+
+/** SOC_ETM_CH1_TASK_ID_REG register
+ *  Channel1 task id register
+ */
+#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24)
+/** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch1_task_id
+ */
+#define SOC_ETM_CH1_TASK_ID    0x000000FFU
+#define SOC_ETM_CH1_TASK_ID_M  (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S)
+#define SOC_ETM_CH1_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH1_TASK_ID_S  0
+
+/** SOC_ETM_CH2_EVT_ID_REG register
+ *  Channel2 event id register
+ */
+#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28)
+/** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch2_evt_id
+ */
+#define SOC_ETM_CH2_EVT_ID    0x000000FFU
+#define SOC_ETM_CH2_EVT_ID_M  (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S)
+#define SOC_ETM_CH2_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH2_EVT_ID_S  0
+
+/** SOC_ETM_CH2_TASK_ID_REG register
+ *  Channel2 task id register
+ */
+#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c)
+/** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch2_task_id
+ */
+#define SOC_ETM_CH2_TASK_ID    0x000000FFU
+#define SOC_ETM_CH2_TASK_ID_M  (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S)
+#define SOC_ETM_CH2_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH2_TASK_ID_S  0
+
+/** SOC_ETM_CH3_EVT_ID_REG register
+ *  Channel3 event id register
+ */
+#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30)
+/** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch3_evt_id
+ */
+#define SOC_ETM_CH3_EVT_ID    0x000000FFU
+#define SOC_ETM_CH3_EVT_ID_M  (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S)
+#define SOC_ETM_CH3_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH3_EVT_ID_S  0
+
+/** SOC_ETM_CH3_TASK_ID_REG register
+ *  Channel3 task id register
+ */
+#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34)
+/** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch3_task_id
+ */
+#define SOC_ETM_CH3_TASK_ID    0x000000FFU
+#define SOC_ETM_CH3_TASK_ID_M  (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S)
+#define SOC_ETM_CH3_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH3_TASK_ID_S  0
+
+/** SOC_ETM_CH4_EVT_ID_REG register
+ *  Channel4 event id register
+ */
+#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38)
+/** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch4_evt_id
+ */
+#define SOC_ETM_CH4_EVT_ID    0x000000FFU
+#define SOC_ETM_CH4_EVT_ID_M  (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S)
+#define SOC_ETM_CH4_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH4_EVT_ID_S  0
+
+/** SOC_ETM_CH4_TASK_ID_REG register
+ *  Channel4 task id register
+ */
+#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c)
+/** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch4_task_id
+ */
+#define SOC_ETM_CH4_TASK_ID    0x000000FFU
+#define SOC_ETM_CH4_TASK_ID_M  (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S)
+#define SOC_ETM_CH4_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH4_TASK_ID_S  0
+
+/** SOC_ETM_CH5_EVT_ID_REG register
+ *  Channel5 event id register
+ */
+#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40)
+/** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch5_evt_id
+ */
+#define SOC_ETM_CH5_EVT_ID    0x000000FFU
+#define SOC_ETM_CH5_EVT_ID_M  (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S)
+#define SOC_ETM_CH5_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH5_EVT_ID_S  0
+
+/** SOC_ETM_CH5_TASK_ID_REG register
+ *  Channel5 task id register
+ */
+#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44)
+/** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch5_task_id
+ */
+#define SOC_ETM_CH5_TASK_ID    0x000000FFU
+#define SOC_ETM_CH5_TASK_ID_M  (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S)
+#define SOC_ETM_CH5_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH5_TASK_ID_S  0
+
+/** SOC_ETM_CH6_EVT_ID_REG register
+ *  Channel6 event id register
+ */
+#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48)
+/** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch6_evt_id
+ */
+#define SOC_ETM_CH6_EVT_ID    0x000000FFU
+#define SOC_ETM_CH6_EVT_ID_M  (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S)
+#define SOC_ETM_CH6_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH6_EVT_ID_S  0
+
+/** SOC_ETM_CH6_TASK_ID_REG register
+ *  Channel6 task id register
+ */
+#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c)
+/** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch6_task_id
+ */
+#define SOC_ETM_CH6_TASK_ID    0x000000FFU
+#define SOC_ETM_CH6_TASK_ID_M  (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S)
+#define SOC_ETM_CH6_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH6_TASK_ID_S  0
+
+/** SOC_ETM_CH7_EVT_ID_REG register
+ *  Channel7 event id register
+ */
+#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50)
+/** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch7_evt_id
+ */
+#define SOC_ETM_CH7_EVT_ID    0x000000FFU
+#define SOC_ETM_CH7_EVT_ID_M  (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S)
+#define SOC_ETM_CH7_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH7_EVT_ID_S  0
+
+/** SOC_ETM_CH7_TASK_ID_REG register
+ *  Channel7 task id register
+ */
+#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54)
+/** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch7_task_id
+ */
+#define SOC_ETM_CH7_TASK_ID    0x000000FFU
+#define SOC_ETM_CH7_TASK_ID_M  (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S)
+#define SOC_ETM_CH7_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH7_TASK_ID_S  0
+
+/** SOC_ETM_CH8_EVT_ID_REG register
+ *  Channel8 event id register
+ */
+#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58)
+/** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch8_evt_id
+ */
+#define SOC_ETM_CH8_EVT_ID    0x000000FFU
+#define SOC_ETM_CH8_EVT_ID_M  (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S)
+#define SOC_ETM_CH8_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH8_EVT_ID_S  0
+
+/** SOC_ETM_CH8_TASK_ID_REG register
+ *  Channel8 task id register
+ */
+#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c)
+/** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch8_task_id
+ */
+#define SOC_ETM_CH8_TASK_ID    0x000000FFU
+#define SOC_ETM_CH8_TASK_ID_M  (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S)
+#define SOC_ETM_CH8_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH8_TASK_ID_S  0
+
+/** SOC_ETM_CH9_EVT_ID_REG register
+ *  Channel9 event id register
+ */
+#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60)
+/** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch9_evt_id
+ */
+#define SOC_ETM_CH9_EVT_ID    0x000000FFU
+#define SOC_ETM_CH9_EVT_ID_M  (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S)
+#define SOC_ETM_CH9_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH9_EVT_ID_S  0
+
+/** SOC_ETM_CH9_TASK_ID_REG register
+ *  Channel9 task id register
+ */
+#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64)
+/** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch9_task_id
+ */
+#define SOC_ETM_CH9_TASK_ID    0x000000FFU
+#define SOC_ETM_CH9_TASK_ID_M  (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S)
+#define SOC_ETM_CH9_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH9_TASK_ID_S  0
+
+/** SOC_ETM_CH10_EVT_ID_REG register
+ *  Channel10 event id register
+ */
+#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68)
+/** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch10_evt_id
+ */
+#define SOC_ETM_CH10_EVT_ID    0x000000FFU
+#define SOC_ETM_CH10_EVT_ID_M  (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S)
+#define SOC_ETM_CH10_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH10_EVT_ID_S  0
+
+/** SOC_ETM_CH10_TASK_ID_REG register
+ *  Channel10 task id register
+ */
+#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c)
+/** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch10_task_id
+ */
+#define SOC_ETM_CH10_TASK_ID    0x000000FFU
+#define SOC_ETM_CH10_TASK_ID_M  (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S)
+#define SOC_ETM_CH10_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH10_TASK_ID_S  0
+
+/** SOC_ETM_CH11_EVT_ID_REG register
+ *  Channel11 event id register
+ */
+#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70)
+/** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch11_evt_id
+ */
+#define SOC_ETM_CH11_EVT_ID    0x000000FFU
+#define SOC_ETM_CH11_EVT_ID_M  (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S)
+#define SOC_ETM_CH11_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH11_EVT_ID_S  0
+
+/** SOC_ETM_CH11_TASK_ID_REG register
+ *  Channel11 task id register
+ */
+#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74)
+/** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch11_task_id
+ */
+#define SOC_ETM_CH11_TASK_ID    0x000000FFU
+#define SOC_ETM_CH11_TASK_ID_M  (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S)
+#define SOC_ETM_CH11_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH11_TASK_ID_S  0
+
+/** SOC_ETM_CH12_EVT_ID_REG register
+ *  Channel12 event id register
+ */
+#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78)
+/** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch12_evt_id
+ */
+#define SOC_ETM_CH12_EVT_ID    0x000000FFU
+#define SOC_ETM_CH12_EVT_ID_M  (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S)
+#define SOC_ETM_CH12_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH12_EVT_ID_S  0
+
+/** SOC_ETM_CH12_TASK_ID_REG register
+ *  Channel12 task id register
+ */
+#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c)
+/** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch12_task_id
+ */
+#define SOC_ETM_CH12_TASK_ID    0x000000FFU
+#define SOC_ETM_CH12_TASK_ID_M  (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S)
+#define SOC_ETM_CH12_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH12_TASK_ID_S  0
+
+/** SOC_ETM_CH13_EVT_ID_REG register
+ *  Channel13 event id register
+ */
+#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80)
+/** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch13_evt_id
+ */
+#define SOC_ETM_CH13_EVT_ID    0x000000FFU
+#define SOC_ETM_CH13_EVT_ID_M  (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S)
+#define SOC_ETM_CH13_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH13_EVT_ID_S  0
+
+/** SOC_ETM_CH13_TASK_ID_REG register
+ *  Channel13 task id register
+ */
+#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84)
+/** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch13_task_id
+ */
+#define SOC_ETM_CH13_TASK_ID    0x000000FFU
+#define SOC_ETM_CH13_TASK_ID_M  (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S)
+#define SOC_ETM_CH13_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH13_TASK_ID_S  0
+
+/** SOC_ETM_CH14_EVT_ID_REG register
+ *  Channel14 event id register
+ */
+#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88)
+/** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch14_evt_id
+ */
+#define SOC_ETM_CH14_EVT_ID    0x000000FFU
+#define SOC_ETM_CH14_EVT_ID_M  (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S)
+#define SOC_ETM_CH14_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH14_EVT_ID_S  0
+
+/** SOC_ETM_CH14_TASK_ID_REG register
+ *  Channel14 task id register
+ */
+#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c)
+/** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch14_task_id
+ */
+#define SOC_ETM_CH14_TASK_ID    0x000000FFU
+#define SOC_ETM_CH14_TASK_ID_M  (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S)
+#define SOC_ETM_CH14_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH14_TASK_ID_S  0
+
+/** SOC_ETM_CH15_EVT_ID_REG register
+ *  Channel15 event id register
+ */
+#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90)
+/** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch15_evt_id
+ */
+#define SOC_ETM_CH15_EVT_ID    0x000000FFU
+#define SOC_ETM_CH15_EVT_ID_M  (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S)
+#define SOC_ETM_CH15_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH15_EVT_ID_S  0
+
+/** SOC_ETM_CH15_TASK_ID_REG register
+ *  Channel15 task id register
+ */
+#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94)
+/** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch15_task_id
+ */
+#define SOC_ETM_CH15_TASK_ID    0x000000FFU
+#define SOC_ETM_CH15_TASK_ID_M  (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S)
+#define SOC_ETM_CH15_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH15_TASK_ID_S  0
+
+/** SOC_ETM_CH16_EVT_ID_REG register
+ *  Channel16 event id register
+ */
+#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98)
+/** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch16_evt_id
+ */
+#define SOC_ETM_CH16_EVT_ID    0x000000FFU
+#define SOC_ETM_CH16_EVT_ID_M  (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S)
+#define SOC_ETM_CH16_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH16_EVT_ID_S  0
+
+/** SOC_ETM_CH16_TASK_ID_REG register
+ *  Channel16 task id register
+ */
+#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c)
+/** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch16_task_id
+ */
+#define SOC_ETM_CH16_TASK_ID    0x000000FFU
+#define SOC_ETM_CH16_TASK_ID_M  (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S)
+#define SOC_ETM_CH16_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH16_TASK_ID_S  0
+
+/** SOC_ETM_CH17_EVT_ID_REG register
+ *  Channel17 event id register
+ */
+#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0)
+/** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch17_evt_id
+ */
+#define SOC_ETM_CH17_EVT_ID    0x000000FFU
+#define SOC_ETM_CH17_EVT_ID_M  (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S)
+#define SOC_ETM_CH17_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH17_EVT_ID_S  0
+
+/** SOC_ETM_CH17_TASK_ID_REG register
+ *  Channel17 task id register
+ */
+#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4)
+/** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch17_task_id
+ */
+#define SOC_ETM_CH17_TASK_ID    0x000000FFU
+#define SOC_ETM_CH17_TASK_ID_M  (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S)
+#define SOC_ETM_CH17_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH17_TASK_ID_S  0
+
+/** SOC_ETM_CH18_EVT_ID_REG register
+ *  Channel18 event id register
+ */
+#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8)
+/** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch18_evt_id
+ */
+#define SOC_ETM_CH18_EVT_ID    0x000000FFU
+#define SOC_ETM_CH18_EVT_ID_M  (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S)
+#define SOC_ETM_CH18_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH18_EVT_ID_S  0
+
+/** SOC_ETM_CH18_TASK_ID_REG register
+ *  Channel18 task id register
+ */
+#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac)
+/** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch18_task_id
+ */
+#define SOC_ETM_CH18_TASK_ID    0x000000FFU
+#define SOC_ETM_CH18_TASK_ID_M  (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S)
+#define SOC_ETM_CH18_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH18_TASK_ID_S  0
+
+/** SOC_ETM_CH19_EVT_ID_REG register
+ *  Channel19 event id register
+ */
+#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0)
+/** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch19_evt_id
+ */
+#define SOC_ETM_CH19_EVT_ID    0x000000FFU
+#define SOC_ETM_CH19_EVT_ID_M  (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S)
+#define SOC_ETM_CH19_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH19_EVT_ID_S  0
+
+/** SOC_ETM_CH19_TASK_ID_REG register
+ *  Channel19 task id register
+ */
+#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4)
+/** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch19_task_id
+ */
+#define SOC_ETM_CH19_TASK_ID    0x000000FFU
+#define SOC_ETM_CH19_TASK_ID_M  (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S)
+#define SOC_ETM_CH19_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH19_TASK_ID_S  0
+
+/** SOC_ETM_CH20_EVT_ID_REG register
+ *  Channel20 event id register
+ */
+#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8)
+/** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch20_evt_id
+ */
+#define SOC_ETM_CH20_EVT_ID    0x000000FFU
+#define SOC_ETM_CH20_EVT_ID_M  (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S)
+#define SOC_ETM_CH20_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH20_EVT_ID_S  0
+
+/** SOC_ETM_CH20_TASK_ID_REG register
+ *  Channel20 task id register
+ */
+#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc)
+/** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch20_task_id
+ */
+#define SOC_ETM_CH20_TASK_ID    0x000000FFU
+#define SOC_ETM_CH20_TASK_ID_M  (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S)
+#define SOC_ETM_CH20_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH20_TASK_ID_S  0
+
+/** SOC_ETM_CH21_EVT_ID_REG register
+ *  Channel21 event id register
+ */
+#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0)
+/** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch21_evt_id
+ */
+#define SOC_ETM_CH21_EVT_ID    0x000000FFU
+#define SOC_ETM_CH21_EVT_ID_M  (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S)
+#define SOC_ETM_CH21_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH21_EVT_ID_S  0
+
+/** SOC_ETM_CH21_TASK_ID_REG register
+ *  Channel21 task id register
+ */
+#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4)
+/** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch21_task_id
+ */
+#define SOC_ETM_CH21_TASK_ID    0x000000FFU
+#define SOC_ETM_CH21_TASK_ID_M  (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S)
+#define SOC_ETM_CH21_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH21_TASK_ID_S  0
+
+/** SOC_ETM_CH22_EVT_ID_REG register
+ *  Channel22 event id register
+ */
+#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8)
+/** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch22_evt_id
+ */
+#define SOC_ETM_CH22_EVT_ID    0x000000FFU
+#define SOC_ETM_CH22_EVT_ID_M  (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S)
+#define SOC_ETM_CH22_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH22_EVT_ID_S  0
+
+/** SOC_ETM_CH22_TASK_ID_REG register
+ *  Channel22 task id register
+ */
+#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc)
+/** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch22_task_id
+ */
+#define SOC_ETM_CH22_TASK_ID    0x000000FFU
+#define SOC_ETM_CH22_TASK_ID_M  (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S)
+#define SOC_ETM_CH22_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH22_TASK_ID_S  0
+
+/** SOC_ETM_CH23_EVT_ID_REG register
+ *  Channel23 event id register
+ */
+#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0)
+/** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch23_evt_id
+ */
+#define SOC_ETM_CH23_EVT_ID    0x000000FFU
+#define SOC_ETM_CH23_EVT_ID_M  (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S)
+#define SOC_ETM_CH23_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH23_EVT_ID_S  0
+
+/** SOC_ETM_CH23_TASK_ID_REG register
+ *  Channel23 task id register
+ */
+#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4)
+/** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch23_task_id
+ */
+#define SOC_ETM_CH23_TASK_ID    0x000000FFU
+#define SOC_ETM_CH23_TASK_ID_M  (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S)
+#define SOC_ETM_CH23_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH23_TASK_ID_S  0
+
+/** SOC_ETM_CH24_EVT_ID_REG register
+ *  Channel24 event id register
+ */
+#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8)
+/** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch24_evt_id
+ */
+#define SOC_ETM_CH24_EVT_ID    0x000000FFU
+#define SOC_ETM_CH24_EVT_ID_M  (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S)
+#define SOC_ETM_CH24_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH24_EVT_ID_S  0
+
+/** SOC_ETM_CH24_TASK_ID_REG register
+ *  Channel24 task id register
+ */
+#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc)
+/** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch24_task_id
+ */
+#define SOC_ETM_CH24_TASK_ID    0x000000FFU
+#define SOC_ETM_CH24_TASK_ID_M  (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S)
+#define SOC_ETM_CH24_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH24_TASK_ID_S  0
+
+/** SOC_ETM_CH25_EVT_ID_REG register
+ *  Channel25 event id register
+ */
+#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0)
+/** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch25_evt_id
+ */
+#define SOC_ETM_CH25_EVT_ID    0x000000FFU
+#define SOC_ETM_CH25_EVT_ID_M  (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S)
+#define SOC_ETM_CH25_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH25_EVT_ID_S  0
+
+/** SOC_ETM_CH25_TASK_ID_REG register
+ *  Channel25 task id register
+ */
+#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4)
+/** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch25_task_id
+ */
+#define SOC_ETM_CH25_TASK_ID    0x000000FFU
+#define SOC_ETM_CH25_TASK_ID_M  (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S)
+#define SOC_ETM_CH25_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH25_TASK_ID_S  0
+
+/** SOC_ETM_CH26_EVT_ID_REG register
+ *  Channel26 event id register
+ */
+#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8)
+/** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch26_evt_id
+ */
+#define SOC_ETM_CH26_EVT_ID    0x000000FFU
+#define SOC_ETM_CH26_EVT_ID_M  (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S)
+#define SOC_ETM_CH26_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH26_EVT_ID_S  0
+
+/** SOC_ETM_CH26_TASK_ID_REG register
+ *  Channel26 task id register
+ */
+#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec)
+/** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch26_task_id
+ */
+#define SOC_ETM_CH26_TASK_ID    0x000000FFU
+#define SOC_ETM_CH26_TASK_ID_M  (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S)
+#define SOC_ETM_CH26_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH26_TASK_ID_S  0
+
+/** SOC_ETM_CH27_EVT_ID_REG register
+ *  Channel27 event id register
+ */
+#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0)
+/** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch27_evt_id
+ */
+#define SOC_ETM_CH27_EVT_ID    0x000000FFU
+#define SOC_ETM_CH27_EVT_ID_M  (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S)
+#define SOC_ETM_CH27_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH27_EVT_ID_S  0
+
+/** SOC_ETM_CH27_TASK_ID_REG register
+ *  Channel27 task id register
+ */
+#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4)
+/** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch27_task_id
+ */
+#define SOC_ETM_CH27_TASK_ID    0x000000FFU
+#define SOC_ETM_CH27_TASK_ID_M  (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S)
+#define SOC_ETM_CH27_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH27_TASK_ID_S  0
+
+/** SOC_ETM_CH28_EVT_ID_REG register
+ *  Channel28 event id register
+ */
+#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8)
+/** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch28_evt_id
+ */
+#define SOC_ETM_CH28_EVT_ID    0x000000FFU
+#define SOC_ETM_CH28_EVT_ID_M  (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S)
+#define SOC_ETM_CH28_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH28_EVT_ID_S  0
+
+/** SOC_ETM_CH28_TASK_ID_REG register
+ *  Channel28 task id register
+ */
+#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc)
+/** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch28_task_id
+ */
+#define SOC_ETM_CH28_TASK_ID    0x000000FFU
+#define SOC_ETM_CH28_TASK_ID_M  (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S)
+#define SOC_ETM_CH28_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH28_TASK_ID_S  0
+
+/** SOC_ETM_CH29_EVT_ID_REG register
+ *  Channel29 event id register
+ */
+#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100)
+/** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch29_evt_id
+ */
+#define SOC_ETM_CH29_EVT_ID    0x000000FFU
+#define SOC_ETM_CH29_EVT_ID_M  (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S)
+#define SOC_ETM_CH29_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH29_EVT_ID_S  0
+
+/** SOC_ETM_CH29_TASK_ID_REG register
+ *  Channel29 task id register
+ */
+#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104)
+/** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch29_task_id
+ */
+#define SOC_ETM_CH29_TASK_ID    0x000000FFU
+#define SOC_ETM_CH29_TASK_ID_M  (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S)
+#define SOC_ETM_CH29_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH29_TASK_ID_S  0
+
+/** SOC_ETM_CH30_EVT_ID_REG register
+ *  Channel30 event id register
+ */
+#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108)
+/** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch30_evt_id
+ */
+#define SOC_ETM_CH30_EVT_ID    0x000000FFU
+#define SOC_ETM_CH30_EVT_ID_M  (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S)
+#define SOC_ETM_CH30_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH30_EVT_ID_S  0
+
+/** SOC_ETM_CH30_TASK_ID_REG register
+ *  Channel30 task id register
+ */
+#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c)
+/** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch30_task_id
+ */
+#define SOC_ETM_CH30_TASK_ID    0x000000FFU
+#define SOC_ETM_CH30_TASK_ID_M  (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S)
+#define SOC_ETM_CH30_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH30_TASK_ID_S  0
+
+/** SOC_ETM_CH31_EVT_ID_REG register
+ *  Channel31 event id register
+ */
+#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110)
+/** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch31_evt_id
+ */
+#define SOC_ETM_CH31_EVT_ID    0x000000FFU
+#define SOC_ETM_CH31_EVT_ID_M  (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S)
+#define SOC_ETM_CH31_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH31_EVT_ID_S  0
+
+/** SOC_ETM_CH31_TASK_ID_REG register
+ *  Channel31 task id register
+ */
+#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114)
+/** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch31_task_id
+ */
+#define SOC_ETM_CH31_TASK_ID    0x000000FFU
+#define SOC_ETM_CH31_TASK_ID_M  (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S)
+#define SOC_ETM_CH31_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH31_TASK_ID_S  0
+
+/** SOC_ETM_CH32_EVT_ID_REG register
+ *  Channel32 event id register
+ */
+#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118)
+/** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch32_evt_id
+ */
+#define SOC_ETM_CH32_EVT_ID    0x000000FFU
+#define SOC_ETM_CH32_EVT_ID_M  (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S)
+#define SOC_ETM_CH32_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH32_EVT_ID_S  0
+
+/** SOC_ETM_CH32_TASK_ID_REG register
+ *  Channel32 task id register
+ */
+#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c)
+/** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch32_task_id
+ */
+#define SOC_ETM_CH32_TASK_ID    0x000000FFU
+#define SOC_ETM_CH32_TASK_ID_M  (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S)
+#define SOC_ETM_CH32_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH32_TASK_ID_S  0
+
+/** SOC_ETM_CH33_EVT_ID_REG register
+ *  Channel33 event id register
+ */
+#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120)
+/** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch33_evt_id
+ */
+#define SOC_ETM_CH33_EVT_ID    0x000000FFU
+#define SOC_ETM_CH33_EVT_ID_M  (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S)
+#define SOC_ETM_CH33_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH33_EVT_ID_S  0
+
+/** SOC_ETM_CH33_TASK_ID_REG register
+ *  Channel33 task id register
+ */
+#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124)
+/** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch33_task_id
+ */
+#define SOC_ETM_CH33_TASK_ID    0x000000FFU
+#define SOC_ETM_CH33_TASK_ID_M  (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S)
+#define SOC_ETM_CH33_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH33_TASK_ID_S  0
+
+/** SOC_ETM_CH34_EVT_ID_REG register
+ *  Channel34 event id register
+ */
+#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128)
+/** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch34_evt_id
+ */
+#define SOC_ETM_CH34_EVT_ID    0x000000FFU
+#define SOC_ETM_CH34_EVT_ID_M  (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S)
+#define SOC_ETM_CH34_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH34_EVT_ID_S  0
+
+/** SOC_ETM_CH34_TASK_ID_REG register
+ *  Channel34 task id register
+ */
+#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c)
+/** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch34_task_id
+ */
+#define SOC_ETM_CH34_TASK_ID    0x000000FFU
+#define SOC_ETM_CH34_TASK_ID_M  (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S)
+#define SOC_ETM_CH34_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH34_TASK_ID_S  0
+
+/** SOC_ETM_CH35_EVT_ID_REG register
+ *  Channel35 event id register
+ */
+#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130)
+/** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch35_evt_id
+ */
+#define SOC_ETM_CH35_EVT_ID    0x000000FFU
+#define SOC_ETM_CH35_EVT_ID_M  (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S)
+#define SOC_ETM_CH35_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH35_EVT_ID_S  0
+
+/** SOC_ETM_CH35_TASK_ID_REG register
+ *  Channel35 task id register
+ */
+#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134)
+/** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch35_task_id
+ */
+#define SOC_ETM_CH35_TASK_ID    0x000000FFU
+#define SOC_ETM_CH35_TASK_ID_M  (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S)
+#define SOC_ETM_CH35_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH35_TASK_ID_S  0
+
+/** SOC_ETM_CH36_EVT_ID_REG register
+ *  Channel36 event id register
+ */
+#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138)
+/** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch36_evt_id
+ */
+#define SOC_ETM_CH36_EVT_ID    0x000000FFU
+#define SOC_ETM_CH36_EVT_ID_M  (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S)
+#define SOC_ETM_CH36_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH36_EVT_ID_S  0
+
+/** SOC_ETM_CH36_TASK_ID_REG register
+ *  Channel36 task id register
+ */
+#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c)
+/** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch36_task_id
+ */
+#define SOC_ETM_CH36_TASK_ID    0x000000FFU
+#define SOC_ETM_CH36_TASK_ID_M  (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S)
+#define SOC_ETM_CH36_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH36_TASK_ID_S  0
+
+/** SOC_ETM_CH37_EVT_ID_REG register
+ *  Channel37 event id register
+ */
+#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140)
+/** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch37_evt_id
+ */
+#define SOC_ETM_CH37_EVT_ID    0x000000FFU
+#define SOC_ETM_CH37_EVT_ID_M  (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S)
+#define SOC_ETM_CH37_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH37_EVT_ID_S  0
+
+/** SOC_ETM_CH37_TASK_ID_REG register
+ *  Channel37 task id register
+ */
+#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144)
+/** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch37_task_id
+ */
+#define SOC_ETM_CH37_TASK_ID    0x000000FFU
+#define SOC_ETM_CH37_TASK_ID_M  (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S)
+#define SOC_ETM_CH37_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH37_TASK_ID_S  0
+
+/** SOC_ETM_CH38_EVT_ID_REG register
+ *  Channel38 event id register
+ */
+#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148)
+/** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch38_evt_id
+ */
+#define SOC_ETM_CH38_EVT_ID    0x000000FFU
+#define SOC_ETM_CH38_EVT_ID_M  (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S)
+#define SOC_ETM_CH38_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH38_EVT_ID_S  0
+
+/** SOC_ETM_CH38_TASK_ID_REG register
+ *  Channel38 task id register
+ */
+#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c)
+/** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch38_task_id
+ */
+#define SOC_ETM_CH38_TASK_ID    0x000000FFU
+#define SOC_ETM_CH38_TASK_ID_M  (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S)
+#define SOC_ETM_CH38_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH38_TASK_ID_S  0
+
+/** SOC_ETM_CH39_EVT_ID_REG register
+ *  Channel39 event id register
+ */
+#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150)
+/** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch39_evt_id
+ */
+#define SOC_ETM_CH39_EVT_ID    0x000000FFU
+#define SOC_ETM_CH39_EVT_ID_M  (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S)
+#define SOC_ETM_CH39_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH39_EVT_ID_S  0
+
+/** SOC_ETM_CH39_TASK_ID_REG register
+ *  Channel39 task id register
+ */
+#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154)
+/** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch39_task_id
+ */
+#define SOC_ETM_CH39_TASK_ID    0x000000FFU
+#define SOC_ETM_CH39_TASK_ID_M  (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S)
+#define SOC_ETM_CH39_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH39_TASK_ID_S  0
+
+/** SOC_ETM_CH40_EVT_ID_REG register
+ *  Channel40 event id register
+ */
+#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158)
+/** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch40_evt_id
+ */
+#define SOC_ETM_CH40_EVT_ID    0x000000FFU
+#define SOC_ETM_CH40_EVT_ID_M  (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S)
+#define SOC_ETM_CH40_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH40_EVT_ID_S  0
+
+/** SOC_ETM_CH40_TASK_ID_REG register
+ *  Channel40 task id register
+ */
+#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c)
+/** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch40_task_id
+ */
+#define SOC_ETM_CH40_TASK_ID    0x000000FFU
+#define SOC_ETM_CH40_TASK_ID_M  (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S)
+#define SOC_ETM_CH40_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH40_TASK_ID_S  0
+
+/** SOC_ETM_CH41_EVT_ID_REG register
+ *  Channel41 event id register
+ */
+#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160)
+/** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch41_evt_id
+ */
+#define SOC_ETM_CH41_EVT_ID    0x000000FFU
+#define SOC_ETM_CH41_EVT_ID_M  (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S)
+#define SOC_ETM_CH41_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH41_EVT_ID_S  0
+
+/** SOC_ETM_CH41_TASK_ID_REG register
+ *  Channel41 task id register
+ */
+#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164)
+/** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch41_task_id
+ */
+#define SOC_ETM_CH41_TASK_ID    0x000000FFU
+#define SOC_ETM_CH41_TASK_ID_M  (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S)
+#define SOC_ETM_CH41_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH41_TASK_ID_S  0
+
+/** SOC_ETM_CH42_EVT_ID_REG register
+ *  Channel42 event id register
+ */
+#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168)
+/** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch42_evt_id
+ */
+#define SOC_ETM_CH42_EVT_ID    0x000000FFU
+#define SOC_ETM_CH42_EVT_ID_M  (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S)
+#define SOC_ETM_CH42_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH42_EVT_ID_S  0
+
+/** SOC_ETM_CH42_TASK_ID_REG register
+ *  Channel42 task id register
+ */
+#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c)
+/** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch42_task_id
+ */
+#define SOC_ETM_CH42_TASK_ID    0x000000FFU
+#define SOC_ETM_CH42_TASK_ID_M  (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S)
+#define SOC_ETM_CH42_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH42_TASK_ID_S  0
+
+/** SOC_ETM_CH43_EVT_ID_REG register
+ *  Channel43 event id register
+ */
+#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170)
+/** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch43_evt_id
+ */
+#define SOC_ETM_CH43_EVT_ID    0x000000FFU
+#define SOC_ETM_CH43_EVT_ID_M  (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S)
+#define SOC_ETM_CH43_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH43_EVT_ID_S  0
+
+/** SOC_ETM_CH43_TASK_ID_REG register
+ *  Channel43 task id register
+ */
+#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174)
+/** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch43_task_id
+ */
+#define SOC_ETM_CH43_TASK_ID    0x000000FFU
+#define SOC_ETM_CH43_TASK_ID_M  (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S)
+#define SOC_ETM_CH43_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH43_TASK_ID_S  0
+
+/** SOC_ETM_CH44_EVT_ID_REG register
+ *  Channel44 event id register
+ */
+#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178)
+/** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch44_evt_id
+ */
+#define SOC_ETM_CH44_EVT_ID    0x000000FFU
+#define SOC_ETM_CH44_EVT_ID_M  (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S)
+#define SOC_ETM_CH44_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH44_EVT_ID_S  0
+
+/** SOC_ETM_CH44_TASK_ID_REG register
+ *  Channel44 task id register
+ */
+#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c)
+/** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch44_task_id
+ */
+#define SOC_ETM_CH44_TASK_ID    0x000000FFU
+#define SOC_ETM_CH44_TASK_ID_M  (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S)
+#define SOC_ETM_CH44_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH44_TASK_ID_S  0
+
+/** SOC_ETM_CH45_EVT_ID_REG register
+ *  Channel45 event id register
+ */
+#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180)
+/** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch45_evt_id
+ */
+#define SOC_ETM_CH45_EVT_ID    0x000000FFU
+#define SOC_ETM_CH45_EVT_ID_M  (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S)
+#define SOC_ETM_CH45_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH45_EVT_ID_S  0
+
+/** SOC_ETM_CH45_TASK_ID_REG register
+ *  Channel45 task id register
+ */
+#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184)
+/** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch45_task_id
+ */
+#define SOC_ETM_CH45_TASK_ID    0x000000FFU
+#define SOC_ETM_CH45_TASK_ID_M  (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S)
+#define SOC_ETM_CH45_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH45_TASK_ID_S  0
+
+/** SOC_ETM_CH46_EVT_ID_REG register
+ *  Channel46 event id register
+ */
+#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188)
+/** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch46_evt_id
+ */
+#define SOC_ETM_CH46_EVT_ID    0x000000FFU
+#define SOC_ETM_CH46_EVT_ID_M  (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S)
+#define SOC_ETM_CH46_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH46_EVT_ID_S  0
+
+/** SOC_ETM_CH46_TASK_ID_REG register
+ *  Channel46 task id register
+ */
+#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c)
+/** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch46_task_id
+ */
+#define SOC_ETM_CH46_TASK_ID    0x000000FFU
+#define SOC_ETM_CH46_TASK_ID_M  (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S)
+#define SOC_ETM_CH46_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH46_TASK_ID_S  0
+
+/** SOC_ETM_CH47_EVT_ID_REG register
+ *  Channel47 event id register
+ */
+#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190)
+/** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch47_evt_id
+ */
+#define SOC_ETM_CH47_EVT_ID    0x000000FFU
+#define SOC_ETM_CH47_EVT_ID_M  (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S)
+#define SOC_ETM_CH47_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH47_EVT_ID_S  0
+
+/** SOC_ETM_CH47_TASK_ID_REG register
+ *  Channel47 task id register
+ */
+#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194)
+/** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch47_task_id
+ */
+#define SOC_ETM_CH47_TASK_ID    0x000000FFU
+#define SOC_ETM_CH47_TASK_ID_M  (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S)
+#define SOC_ETM_CH47_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH47_TASK_ID_S  0
+
+/** SOC_ETM_CH48_EVT_ID_REG register
+ *  Channel48 event id register
+ */
+#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198)
+/** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch48_evt_id
+ */
+#define SOC_ETM_CH48_EVT_ID    0x000000FFU
+#define SOC_ETM_CH48_EVT_ID_M  (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S)
+#define SOC_ETM_CH48_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH48_EVT_ID_S  0
+
+/** SOC_ETM_CH48_TASK_ID_REG register
+ *  Channel48 task id register
+ */
+#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c)
+/** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch48_task_id
+ */
+#define SOC_ETM_CH48_TASK_ID    0x000000FFU
+#define SOC_ETM_CH48_TASK_ID_M  (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S)
+#define SOC_ETM_CH48_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH48_TASK_ID_S  0
+
+/** SOC_ETM_CH49_EVT_ID_REG register
+ *  Channel49 event id register
+ */
+#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0)
+/** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch49_evt_id
+ */
+#define SOC_ETM_CH49_EVT_ID    0x000000FFU
+#define SOC_ETM_CH49_EVT_ID_M  (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S)
+#define SOC_ETM_CH49_EVT_ID_V  0x000000FFU
+#define SOC_ETM_CH49_EVT_ID_S  0
+
+/** SOC_ETM_CH49_TASK_ID_REG register
+ *  Channel49 task id register
+ */
+#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4)
+/** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0;
+ *  Configures ch49_task_id
+ */
+#define SOC_ETM_CH49_TASK_ID    0x000000FFU
+#define SOC_ETM_CH49_TASK_ID_M  (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S)
+#define SOC_ETM_CH49_TASK_ID_V  0x000000FFU
+#define SOC_ETM_CH49_TASK_ID_S  0
+
+/** SOC_ETM_EVT_ST0_REG register
+ *  Events trigger status register
+ */
+#define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1a8)
+/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents GPIO_evt_ch0_rise_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST    (BIT(0))
+#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S  0
+/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents GPIO_evt_ch1_rise_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST    (BIT(1))
+#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S  1
+/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents GPIO_evt_ch2_rise_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST    (BIT(2))
+#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S  2
+/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents GPIO_evt_ch3_rise_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST    (BIT(3))
+#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S  3
+/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents GPIO_evt_ch4_rise_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST    (BIT(4))
+#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S  4
+/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents GPIO_evt_ch5_rise_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST    (BIT(5))
+#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S  5
+/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents GPIO_evt_ch6_rise_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST    (BIT(6))
+#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S  6
+/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents GPIO_evt_ch7_rise_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST    (BIT(7))
+#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S  7
+/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents GPIO_evt_ch0_fall_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST    (BIT(8))
+#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S  8
+/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents GPIO_evt_ch1_fall_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST    (BIT(9))
+#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S  9
+/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents GPIO_evt_ch2_fall_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST    (BIT(10))
+#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S  10
+/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents GPIO_evt_ch3_fall_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST    (BIT(11))
+#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S  11
+/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents GPIO_evt_ch4_fall_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST    (BIT(12))
+#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S  12
+/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents GPIO_evt_ch5_fall_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST    (BIT(13))
+#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S  13
+/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents GPIO_evt_ch6_fall_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST    (BIT(14))
+#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S  14
+/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents GPIO_evt_ch7_fall_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST    (BIT(15))
+#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S  15
+/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents GPIO_evt_ch0_any_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST    (BIT(16))
+#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S  16
+/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents GPIO_evt_ch1_any_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST    (BIT(17))
+#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S  17
+/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents GPIO_evt_ch2_any_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST    (BIT(18))
+#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S  18
+/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents GPIO_evt_ch3_any_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST    (BIT(19))
+#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S  19
+/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents GPIO_evt_ch4_any_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST    (BIT(20))
+#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S  20
+/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents GPIO_evt_ch5_any_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST    (BIT(21))
+#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S  21
+/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents GPIO_evt_ch6_any_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST    (BIT(22))
+#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S  22
+/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents GPIO_evt_ch7_any_edge trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST    (BIT(23))
+#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S)
+#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S  23
+/** SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents GPIO_evt_zero_det_pos0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST    (BIT(24))
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_M  (SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_S)
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_S  24
+/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents GPIO_evt_zero_det_neg0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST    (BIT(25))
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_M  (SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_S)
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_S  25
+/** SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents GPIO_evt_zero_det_pos1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST    (BIT(26))
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_M  (SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_S)
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_S  26
+/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents GPIO_evt_zero_det_neg1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST    (BIT(27))
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_M  (SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_S)
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_S  27
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents LEDC_evt_duty_chng_end_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST    (BIT(28))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S  28
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents LEDC_evt_duty_chng_end_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST    (BIT(29))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S  29
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents LEDC_evt_duty_chng_end_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST    (BIT(30))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S  30
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents LEDC_evt_duty_chng_end_ch3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST    (BIT(31))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S  31
+
+/** SOC_ETM_EVT_ST0_CLR_REG register
+ *  Events trigger status clear register
+ */
+#define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ac)
+/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR    (BIT(0))
+#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S  0
+/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR    (BIT(1))
+#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S  1
+/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR    (BIT(2))
+#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S  2
+/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR    (BIT(3))
+#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S  3
+/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR    (BIT(4))
+#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S  4
+/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR    (BIT(5))
+#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S  5
+/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR    (BIT(6))
+#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S  6
+/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR    (BIT(7))
+#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S  7
+/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR    (BIT(8))
+#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S  8
+/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR    (BIT(9))
+#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S  9
+/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR    (BIT(10))
+#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S  10
+/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR    (BIT(11))
+#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S  11
+/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR    (BIT(12))
+#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S  12
+/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR    (BIT(13))
+#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S  13
+/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR    (BIT(14))
+#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S  14
+/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR    (BIT(15))
+#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S  15
+/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR    (BIT(16))
+#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S  16
+/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR    (BIT(17))
+#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S  17
+/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR    (BIT(18))
+#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S  18
+/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR    (BIT(19))
+#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S  19
+/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR    (BIT(20))
+#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S  20
+/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR    (BIT(21))
+#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S  21
+/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR    (BIT(22))
+#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S  22
+/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR    (BIT(23))
+#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S  23
+/** SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR    (BIT(24))
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_M  (SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_S  24
+/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR    (BIT(25))
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_M  (SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_S  25
+/** SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR    (BIT(26))
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_M  (SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_S  26
+/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR    (BIT(27))
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_M  (SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_S)
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_S  27
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR    (BIT(28))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S  28
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR    (BIT(29))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S  29
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR    (BIT(30))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S  30
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR    (BIT(31))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S  31
+
+/** SOC_ETM_EVT_ST1_REG register
+ *  Events trigger status register
+ */
+#define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1b0)
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents LEDC_evt_duty_chng_end_ch4 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST    (BIT(0))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S  0
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents LEDC_evt_duty_chng_end_ch5 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST    (BIT(1))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S  1
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents LEDC_evt_duty_chng_end_ch6 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST    (BIT(2))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_S  2
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents LEDC_evt_duty_chng_end_ch7 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST    (BIT(3))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_S  3
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST    (BIT(4))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S  4
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST    (BIT(5))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S  5
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST    (BIT(6))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S  6
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST    (BIT(7))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S  7
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST    (BIT(8))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S  8
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST    (BIT(9))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S  9
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST    (BIT(10))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_S  10
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST    (BIT(11))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_S  11
+/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents LEDC_evt_time_ovf_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST    (BIT(12))
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S)
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S  12
+/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents LEDC_evt_time_ovf_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST    (BIT(13))
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S)
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S  13
+/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents LEDC_evt_time_ovf_timer2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST    (BIT(14))
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S)
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S  14
+/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents LEDC_evt_time_ovf_timer3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST    (BIT(15))
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S)
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S  15
+/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents LEDC_evt_timer0_cmp trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST    (BIT(16))
+#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_M  (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S)
+#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S  16
+/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents LEDC_evt_timer1_cmp trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST    (BIT(17))
+#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_M  (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S)
+#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S  17
+/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents LEDC_evt_timer2_cmp trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST    (BIT(18))
+#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_M  (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S)
+#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S  18
+/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents LEDC_evt_timer3_cmp trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST    (BIT(19))
+#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_M  (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S)
+#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S  19
+/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents TG0_evt_cnt_cmp_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST    (BIT(20))
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_M  (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S)
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S  20
+/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents TG0_evt_cnt_cmp_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST    (BIT(21))
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_M  (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S)
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S  21
+/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents TG1_evt_cnt_cmp_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST    (BIT(22))
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_M  (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S)
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S  22
+/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents TG1_evt_cnt_cmp_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST    (BIT(23))
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_M  (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S)
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S  23
+/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents SYSTIMER_evt_cnt_cmp0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST    (BIT(24))
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S)
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V  0x00000001U
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S  24
+/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents SYSTIMER_evt_cnt_cmp1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST    (BIT(25))
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S)
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V  0x00000001U
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S  25
+/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents SYSTIMER_evt_cnt_cmp2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST    (BIT(26))
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S)
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V  0x00000001U
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S  26
+/** SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents MCPWM0_evt_timer0_stop trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST    (BIT(27))
+#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_S  27
+/** SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents MCPWM0_evt_timer1_stop trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST    (BIT(28))
+#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_S  28
+/** SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents MCPWM0_evt_timer2_stop trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST    (BIT(29))
+#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_S  29
+/** SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents MCPWM0_evt_timer0_tez trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST    (BIT(30))
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_S  30
+/** SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents MCPWM0_evt_timer1_tez trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST    (BIT(31))
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_S  31
+
+/** SOC_ETM_EVT_ST1_CLR_REG register
+ *  Events trigger status clear register
+ */
+#define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1b4)
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR    (BIT(0))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S  0
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR    (BIT(1))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S  1
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR    (BIT(2))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_S  2
+/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR    (BIT(3))
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_S  3
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR    (BIT(4))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S  4
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR    (BIT(5))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S  5
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR    (BIT(6))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S  6
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR    (BIT(7))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S  7
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR    (BIT(8))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S  8
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR    (BIT(9))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S  9
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR    (BIT(10))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_S  10
+/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR    (BIT(11))
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_S  11
+/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR    (BIT(12))
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S  12
+/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR    (BIT(13))
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S  13
+/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR    (BIT(14))
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S  14
+/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR    (BIT(15))
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S  15
+/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR    (BIT(16))
+#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S  16
+/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR    (BIT(17))
+#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S  17
+/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR    (BIT(18))
+#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S  18
+/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR    (BIT(19))
+#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S)
+#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S  19
+/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR    (BIT(20))
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_M  (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S  20
+/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR    (BIT(21))
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_M  (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S  21
+/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR    (BIT(22))
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_M  (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S  22
+/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR    (BIT(23))
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_M  (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S  23
+/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR    (BIT(24))
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S)
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V  0x00000001U
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S  24
+/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR    (BIT(25))
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S)
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V  0x00000001U
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S  25
+/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR    (BIT(26))
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S)
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V  0x00000001U
+#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S  26
+/** SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR    (BIT(27))
+#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_S  27
+/** SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR    (BIT(28))
+#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_S  28
+/** SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR    (BIT(29))
+#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_S  29
+/** SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR    (BIT(30))
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_S  30
+/** SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR    (BIT(31))
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_S  31
+
+/** SOC_ETM_EVT_ST2_REG register
+ *  Events trigger status register
+ */
+#define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1b8)
+/** SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents MCPWM0_evt_timer2_tez trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST    (BIT(0))
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_S  0
+/** SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents MCPWM0_evt_timer0_tep trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST    (BIT(1))
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_S  1
+/** SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents MCPWM0_evt_timer1_tep trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST    (BIT(2))
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_S  2
+/** SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents MCPWM0_evt_timer2_tep trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST    (BIT(3))
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_S  3
+/** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents MCPWM0_evt_op0_tea trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST    (BIT(4))
+#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_M  (SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_S  4
+/** SOC_ETM_MCPWM0_EVT_OP1_TEA_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents MCPWM0_evt_op1_tea trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST    (BIT(5))
+#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_M  (SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_S  5
+/** SOC_ETM_MCPWM0_EVT_OP2_TEA_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents MCPWM0_evt_op2_tea trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST    (BIT(6))
+#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_M  (SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_S  6
+/** SOC_ETM_MCPWM0_EVT_OP0_TEB_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents MCPWM0_evt_op0_teb trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST    (BIT(7))
+#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_M  (SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_S  7
+/** SOC_ETM_MCPWM0_EVT_OP1_TEB_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents MCPWM0_evt_op1_teb trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST    (BIT(8))
+#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_M  (SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_S  8
+/** SOC_ETM_MCPWM0_EVT_OP2_TEB_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents MCPWM0_evt_op2_teb trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST    (BIT(9))
+#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_M  (SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_S  9
+/** SOC_ETM_MCPWM0_EVT_F0_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents MCPWM0_evt_f0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_F0_ST    (BIT(10))
+#define SOC_ETM_MCPWM0_EVT_F0_ST_M  (SOC_ETM_MCPWM0_EVT_F0_ST_V << SOC_ETM_MCPWM0_EVT_F0_ST_S)
+#define SOC_ETM_MCPWM0_EVT_F0_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F0_ST_S  10
+/** SOC_ETM_MCPWM0_EVT_F1_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents MCPWM0_evt_f1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_F1_ST    (BIT(11))
+#define SOC_ETM_MCPWM0_EVT_F1_ST_M  (SOC_ETM_MCPWM0_EVT_F1_ST_V << SOC_ETM_MCPWM0_EVT_F1_ST_S)
+#define SOC_ETM_MCPWM0_EVT_F1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F1_ST_S  11
+/** SOC_ETM_MCPWM0_EVT_F2_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents MCPWM0_evt_f2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_F2_ST    (BIT(12))
+#define SOC_ETM_MCPWM0_EVT_F2_ST_M  (SOC_ETM_MCPWM0_EVT_F2_ST_V << SOC_ETM_MCPWM0_EVT_F2_ST_S)
+#define SOC_ETM_MCPWM0_EVT_F2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F2_ST_S  12
+/** SOC_ETM_MCPWM0_EVT_F0_CLR_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents MCPWM0_evt_f0_clr trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST    (BIT(13))
+#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_M  (SOC_ETM_MCPWM0_EVT_F0_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F0_CLR_ST_S)
+#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_S  13
+/** SOC_ETM_MCPWM0_EVT_F1_CLR_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents MCPWM0_evt_f1_clr trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST    (BIT(14))
+#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_M  (SOC_ETM_MCPWM0_EVT_F1_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F1_CLR_ST_S)
+#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_S  14
+/** SOC_ETM_MCPWM0_EVT_F2_CLR_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents MCPWM0_evt_f2_clr trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST    (BIT(15))
+#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_M  (SOC_ETM_MCPWM0_EVT_F2_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F2_CLR_ST_S)
+#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_S  15
+/** SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents MCPWM0_evt_tz0_cbc trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST    (BIT(16))
+#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_M  (SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_S  16
+/** SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents MCPWM0_evt_tz1_cbc trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST    (BIT(17))
+#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_M  (SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_S  17
+/** SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents MCPWM0_evt_tz2_cbc trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST    (BIT(18))
+#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_M  (SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_S  18
+/** SOC_ETM_MCPWM0_EVT_TZ0_OST_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents MCPWM0_evt_tz0_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST    (BIT(19))
+#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_M  (SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_S  19
+/** SOC_ETM_MCPWM0_EVT_TZ1_OST_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents MCPWM0_evt_tz1_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST    (BIT(20))
+#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_M  (SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_S  20
+/** SOC_ETM_MCPWM0_EVT_TZ2_OST_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents MCPWM0_evt_tz2_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST    (BIT(21))
+#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_M  (SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_S)
+#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_S  21
+/** SOC_ETM_MCPWM0_EVT_CAP0_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents MCPWM0_evt_cap0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_CAP0_ST    (BIT(22))
+#define SOC_ETM_MCPWM0_EVT_CAP0_ST_M  (SOC_ETM_MCPWM0_EVT_CAP0_ST_V << SOC_ETM_MCPWM0_EVT_CAP0_ST_S)
+#define SOC_ETM_MCPWM0_EVT_CAP0_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_CAP0_ST_S  22
+/** SOC_ETM_MCPWM0_EVT_CAP1_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents MCPWM0_evt_cap1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_CAP1_ST    (BIT(23))
+#define SOC_ETM_MCPWM0_EVT_CAP1_ST_M  (SOC_ETM_MCPWM0_EVT_CAP1_ST_V << SOC_ETM_MCPWM0_EVT_CAP1_ST_S)
+#define SOC_ETM_MCPWM0_EVT_CAP1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_CAP1_ST_S  23
+/** SOC_ETM_MCPWM0_EVT_CAP2_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents MCPWM0_evt_cap2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_CAP2_ST    (BIT(24))
+#define SOC_ETM_MCPWM0_EVT_CAP2_ST_M  (SOC_ETM_MCPWM0_EVT_CAP2_ST_V << SOC_ETM_MCPWM0_EVT_CAP2_ST_S)
+#define SOC_ETM_MCPWM0_EVT_CAP2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_CAP2_ST_S  24
+/** SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents MCPWM0_evt_op0_tee1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST    (BIT(25))
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_M  (SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_S  25
+/** SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents MCPWM0_evt_op1_tee1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST    (BIT(26))
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_M  (SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_S  26
+/** SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents MCPWM0_evt_op2_tee1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST    (BIT(27))
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_M  (SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_S  27
+/** SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents MCPWM0_evt_op0_tee2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST    (BIT(28))
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_M  (SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_S  28
+/** SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents MCPWM0_evt_op1_tee2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST    (BIT(29))
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_M  (SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_S  29
+/** SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents MCPWM0_evt_op2_tee2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST    (BIT(30))
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_M  (SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_S)
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_S  30
+/** SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents MCPWM1_evt_timer0_stop trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST    (BIT(31))
+#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_M  (SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_S  31
+
+/** SOC_ETM_EVT_ST2_CLR_REG register
+ *  Events trigger status clear register
+ */
+#define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1bc)
+/** SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR    (BIT(0))
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_S  0
+/** SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR    (BIT(1))
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_S  1
+/** SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR    (BIT(2))
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_S  2
+/** SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR    (BIT(3))
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_S  3
+/** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR    (BIT(4))
+#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_S  4
+/** SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR    (BIT(5))
+#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_S  5
+/** SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR    (BIT(6))
+#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_S  6
+/** SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR    (BIT(7))
+#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_S  7
+/** SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR    (BIT(8))
+#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_S  8
+/** SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR    (BIT(9))
+#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_S  9
+/** SOC_ETM_MCPWM0_EVT_F0_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_f0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR    (BIT(10))
+#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F0_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F0_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_S  10
+/** SOC_ETM_MCPWM0_EVT_F1_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_f1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR    (BIT(11))
+#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F1_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_S  11
+/** SOC_ETM_MCPWM0_EVT_F2_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_f2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR    (BIT(12))
+#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F2_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_S  12
+/** SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR    (BIT(13))
+#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_S  13
+/** SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR    (BIT(14))
+#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_S  14
+/** SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR    (BIT(15))
+#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_S  15
+/** SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR    (BIT(16))
+#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_S  16
+/** SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR    (BIT(17))
+#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_S  17
+/** SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR    (BIT(18))
+#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_S  18
+/** SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR    (BIT(19))
+#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_S  19
+/** SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR    (BIT(20))
+#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_S  20
+/** SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR    (BIT(21))
+#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_S  21
+/** SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_cap0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR    (BIT(22))
+#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_S  22
+/** SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_cap1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR    (BIT(23))
+#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_S  23
+/** SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_cap2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR    (BIT(24))
+#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_S  24
+/** SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR    (BIT(25))
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_S  25
+/** SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR    (BIT(26))
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_S  26
+/** SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR    (BIT(27))
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_S  27
+/** SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR    (BIT(28))
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_S  28
+/** SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR    (BIT(29))
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_S  29
+/** SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR    (BIT(30))
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_S)
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_S  30
+/** SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR    (BIT(31))
+#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR_S  31
+
+/** SOC_ETM_EVT_ST3_REG register
+ *  Events trigger status register
+ */
+#define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1c0)
+/** SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents MCPWM1_evt_timer1_stop trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST    (BIT(0))
+#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_M  (SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_S  0
+/** SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents MCPWM1_evt_timer2_stop trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST    (BIT(1))
+#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_M  (SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_S  1
+/** SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents MCPWM1_evt_timer0_tez trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST    (BIT(2))
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_M  (SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_V << SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_S  2
+/** SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents MCPWM1_evt_timer1_tez trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST    (BIT(3))
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_M  (SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_V << SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_S  3
+/** SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents MCPWM1_evt_timer2_tez trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST    (BIT(4))
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_M  (SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_V << SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_S  4
+/** SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents MCPWM1_evt_timer0_tep trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST    (BIT(5))
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_M  (SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_S  5
+/** SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents MCPWM1_evt_timer1_tep trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST    (BIT(6))
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_M  (SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_S  6
+/** SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents MCPWM1_evt_timer2_tep trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST    (BIT(7))
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_M  (SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_S  7
+/** SOC_ETM_MCPWM1_EVT_OP0_TEA_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents MCPWM1_evt_op0_tea trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST    (BIT(8))
+#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_M  (SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_V << SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_S  8
+/** SOC_ETM_MCPWM1_EVT_OP1_TEA_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents MCPWM1_evt_op1_tea trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST    (BIT(9))
+#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_M  (SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_V << SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_S  9
+/** SOC_ETM_MCPWM1_EVT_OP2_TEA_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents MCPWM1_evt_op2_tea trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST    (BIT(10))
+#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_M  (SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_V << SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_S  10
+/** SOC_ETM_MCPWM1_EVT_OP0_TEB_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents MCPWM1_evt_op0_teb trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST    (BIT(11))
+#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_M  (SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_V << SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_S  11
+/** SOC_ETM_MCPWM1_EVT_OP1_TEB_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents MCPWM1_evt_op1_teb trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST    (BIT(12))
+#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_M  (SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_V << SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_S  12
+/** SOC_ETM_MCPWM1_EVT_OP2_TEB_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents MCPWM1_evt_op2_teb trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST    (BIT(13))
+#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_M  (SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_V << SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_S  13
+/** SOC_ETM_MCPWM1_EVT_F0_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents MCPWM1_evt_f0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_F0_ST    (BIT(14))
+#define SOC_ETM_MCPWM1_EVT_F0_ST_M  (SOC_ETM_MCPWM1_EVT_F0_ST_V << SOC_ETM_MCPWM1_EVT_F0_ST_S)
+#define SOC_ETM_MCPWM1_EVT_F0_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F0_ST_S  14
+/** SOC_ETM_MCPWM1_EVT_F1_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents MCPWM1_evt_f1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_F1_ST    (BIT(15))
+#define SOC_ETM_MCPWM1_EVT_F1_ST_M  (SOC_ETM_MCPWM1_EVT_F1_ST_V << SOC_ETM_MCPWM1_EVT_F1_ST_S)
+#define SOC_ETM_MCPWM1_EVT_F1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F1_ST_S  15
+/** SOC_ETM_MCPWM1_EVT_F2_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents MCPWM1_evt_f2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_F2_ST    (BIT(16))
+#define SOC_ETM_MCPWM1_EVT_F2_ST_M  (SOC_ETM_MCPWM1_EVT_F2_ST_V << SOC_ETM_MCPWM1_EVT_F2_ST_S)
+#define SOC_ETM_MCPWM1_EVT_F2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F2_ST_S  16
+/** SOC_ETM_MCPWM1_EVT_F0_CLR_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents MCPWM1_evt_f0_clr trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST    (BIT(17))
+#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_M  (SOC_ETM_MCPWM1_EVT_F0_CLR_ST_V << SOC_ETM_MCPWM1_EVT_F0_CLR_ST_S)
+#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_S  17
+/** SOC_ETM_MCPWM1_EVT_F1_CLR_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents MCPWM1_evt_f1_clr trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST    (BIT(18))
+#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_M  (SOC_ETM_MCPWM1_EVT_F1_CLR_ST_V << SOC_ETM_MCPWM1_EVT_F1_CLR_ST_S)
+#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_S  18
+/** SOC_ETM_MCPWM1_EVT_F2_CLR_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents MCPWM1_evt_f2_clr trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST    (BIT(19))
+#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_M  (SOC_ETM_MCPWM1_EVT_F2_CLR_ST_V << SOC_ETM_MCPWM1_EVT_F2_CLR_ST_S)
+#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_S  19
+/** SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents MCPWM1_evt_tz0_cbc trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST    (BIT(20))
+#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_M  (SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_V << SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_S  20
+/** SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents MCPWM1_evt_tz1_cbc trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST    (BIT(21))
+#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_M  (SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_V << SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_S  21
+/** SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents MCPWM1_evt_tz2_cbc trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST    (BIT(22))
+#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_M  (SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_V << SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_S  22
+/** SOC_ETM_MCPWM1_EVT_TZ0_OST_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents MCPWM1_evt_tz0_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST    (BIT(23))
+#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_M  (SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_V << SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_S  23
+/** SOC_ETM_MCPWM1_EVT_TZ1_OST_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents MCPWM1_evt_tz1_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST    (BIT(24))
+#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_M  (SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_V << SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_S  24
+/** SOC_ETM_MCPWM1_EVT_TZ2_OST_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents MCPWM1_evt_tz2_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST    (BIT(25))
+#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_M  (SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_V << SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_S)
+#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_S  25
+/** SOC_ETM_MCPWM1_EVT_CAP0_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents MCPWM1_evt_cap0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_CAP0_ST    (BIT(26))
+#define SOC_ETM_MCPWM1_EVT_CAP0_ST_M  (SOC_ETM_MCPWM1_EVT_CAP0_ST_V << SOC_ETM_MCPWM1_EVT_CAP0_ST_S)
+#define SOC_ETM_MCPWM1_EVT_CAP0_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_CAP0_ST_S  26
+/** SOC_ETM_MCPWM1_EVT_CAP1_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents MCPWM1_evt_cap1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_CAP1_ST    (BIT(27))
+#define SOC_ETM_MCPWM1_EVT_CAP1_ST_M  (SOC_ETM_MCPWM1_EVT_CAP1_ST_V << SOC_ETM_MCPWM1_EVT_CAP1_ST_S)
+#define SOC_ETM_MCPWM1_EVT_CAP1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_CAP1_ST_S  27
+/** SOC_ETM_MCPWM1_EVT_CAP2_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents MCPWM1_evt_cap2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_CAP2_ST    (BIT(28))
+#define SOC_ETM_MCPWM1_EVT_CAP2_ST_M  (SOC_ETM_MCPWM1_EVT_CAP2_ST_V << SOC_ETM_MCPWM1_EVT_CAP2_ST_S)
+#define SOC_ETM_MCPWM1_EVT_CAP2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_CAP2_ST_S  28
+/** SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents MCPWM1_evt_op0_tee1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST    (BIT(29))
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_M  (SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_V << SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_S  29
+/** SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents MCPWM1_evt_op1_tee1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST    (BIT(30))
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_M  (SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_V << SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_S  30
+/** SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents MCPWM1_evt_op2_tee1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST    (BIT(31))
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_M  (SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_V << SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_S  31
+
+/** SOC_ETM_EVT_ST3_CLR_REG register
+ *  Events trigger status clear register
+ */
+#define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1c4)
+/** SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR    (BIT(0))
+#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR_S  0
+/** SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR    (BIT(1))
+#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR_S  1
+/** SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR    (BIT(2))
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_S  2
+/** SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR    (BIT(3))
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_S  3
+/** SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR    (BIT(4))
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_S  4
+/** SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR    (BIT(5))
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR_S  5
+/** SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR    (BIT(6))
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR_S  6
+/** SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR    (BIT(7))
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR_S  7
+/** SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR    (BIT(8))
+#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR_S  8
+/** SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR    (BIT(9))
+#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR_S  9
+/** SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR    (BIT(10))
+#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR_S  10
+/** SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR    (BIT(11))
+#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR_S  11
+/** SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR    (BIT(12))
+#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR_S  12
+/** SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR    (BIT(13))
+#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR_S  13
+/** SOC_ETM_MCPWM1_EVT_F0_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_f0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_F0_ST_CLR    (BIT(14))
+#define SOC_ETM_MCPWM1_EVT_F0_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_F0_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F0_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_F0_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F0_ST_CLR_S  14
+/** SOC_ETM_MCPWM1_EVT_F1_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_f1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_F1_ST_CLR    (BIT(15))
+#define SOC_ETM_MCPWM1_EVT_F1_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_F1_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F1_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_F1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F1_ST_CLR_S  15
+/** SOC_ETM_MCPWM1_EVT_F2_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_f2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_F2_ST_CLR    (BIT(16))
+#define SOC_ETM_MCPWM1_EVT_F2_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_F2_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F2_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_F2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F2_ST_CLR_S  16
+/** SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR    (BIT(17))
+#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR_S  17
+/** SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR    (BIT(18))
+#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR_S  18
+/** SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR    (BIT(19))
+#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR_S  19
+/** SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR    (BIT(20))
+#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR_S  20
+/** SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR    (BIT(21))
+#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR_S  21
+/** SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR    (BIT(22))
+#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR_S  22
+/** SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR    (BIT(23))
+#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR_S  23
+/** SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR    (BIT(24))
+#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR_S  24
+/** SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR    (BIT(25))
+#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR_S  25
+/** SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_cap0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR    (BIT(26))
+#define SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR_V << SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR_S  26
+/** SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_cap1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR    (BIT(27))
+#define SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR_V << SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR_S  27
+/** SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_cap2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR    (BIT(28))
+#define SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR_V << SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR_S  28
+/** SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR    (BIT(29))
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR_S  29
+/** SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR    (BIT(30))
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR_S  30
+/** SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR    (BIT(31))
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR_S  31
+
+/** SOC_ETM_EVT_ST4_REG register
+ *  Events trigger status register
+ */
+#define SOC_ETM_EVT_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1c8)
+/** SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents MCPWM1_evt_op0_tee2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST    (BIT(0))
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_M  (SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_V << SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_S  0
+/** SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents MCPWM1_evt_op1_tee2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST    (BIT(1))
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_M  (SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_V << SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_S  1
+/** SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents MCPWM1_evt_op2_tee2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST    (BIT(2))
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_M  (SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_V << SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_S)
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_S  2
+/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents ADC_evt_conv_cmplt0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST    (BIT(3))
+#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_M  (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S)
+#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V  0x00000001U
+#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S  3
+/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents ADC_evt_eq_above_thresh0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST    (BIT(4))
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_M  (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S)
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V  0x00000001U
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S  4
+/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents ADC_evt_eq_above_thresh1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST    (BIT(5))
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_M  (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S)
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V  0x00000001U
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S  5
+/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents ADC_evt_eq_below_thresh0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST    (BIT(6))
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_M  (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S)
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V  0x00000001U
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S  6
+/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents ADC_evt_eq_below_thresh1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST    (BIT(7))
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_M  (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S)
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V  0x00000001U
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S  7
+/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents ADC_evt_result_done0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST    (BIT(8))
+#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_M  (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S)
+#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V  0x00000001U
+#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S  8
+/** SOC_ETM_ADC_EVT_STOPPED0_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents ADC_evt_stopped0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_EVT_STOPPED0_ST    (BIT(9))
+#define SOC_ETM_ADC_EVT_STOPPED0_ST_M  (SOC_ETM_ADC_EVT_STOPPED0_ST_V << SOC_ETM_ADC_EVT_STOPPED0_ST_S)
+#define SOC_ETM_ADC_EVT_STOPPED0_ST_V  0x00000001U
+#define SOC_ETM_ADC_EVT_STOPPED0_ST_S  9
+/** SOC_ETM_ADC_EVT_STARTED0_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents ADC_evt_started0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_EVT_STARTED0_ST    (BIT(10))
+#define SOC_ETM_ADC_EVT_STARTED0_ST_M  (SOC_ETM_ADC_EVT_STARTED0_ST_V << SOC_ETM_ADC_EVT_STARTED0_ST_S)
+#define SOC_ETM_ADC_EVT_STARTED0_ST_V  0x00000001U
+#define SOC_ETM_ADC_EVT_STARTED0_ST_S  10
+/** SOC_ETM_REGDMA_EVT_DONE0_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents REGDMA_evt_done0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_EVT_DONE0_ST    (BIT(11))
+#define SOC_ETM_REGDMA_EVT_DONE0_ST_M  (SOC_ETM_REGDMA_EVT_DONE0_ST_V << SOC_ETM_REGDMA_EVT_DONE0_ST_S)
+#define SOC_ETM_REGDMA_EVT_DONE0_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_DONE0_ST_S  11
+/** SOC_ETM_REGDMA_EVT_DONE1_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents REGDMA_evt_done1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_EVT_DONE1_ST    (BIT(12))
+#define SOC_ETM_REGDMA_EVT_DONE1_ST_M  (SOC_ETM_REGDMA_EVT_DONE1_ST_V << SOC_ETM_REGDMA_EVT_DONE1_ST_S)
+#define SOC_ETM_REGDMA_EVT_DONE1_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_DONE1_ST_S  12
+/** SOC_ETM_REGDMA_EVT_DONE2_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents REGDMA_evt_done2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_EVT_DONE2_ST    (BIT(13))
+#define SOC_ETM_REGDMA_EVT_DONE2_ST_M  (SOC_ETM_REGDMA_EVT_DONE2_ST_V << SOC_ETM_REGDMA_EVT_DONE2_ST_S)
+#define SOC_ETM_REGDMA_EVT_DONE2_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_DONE2_ST_S  13
+/** SOC_ETM_REGDMA_EVT_DONE3_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents REGDMA_evt_done3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_EVT_DONE3_ST    (BIT(14))
+#define SOC_ETM_REGDMA_EVT_DONE3_ST_M  (SOC_ETM_REGDMA_EVT_DONE3_ST_V << SOC_ETM_REGDMA_EVT_DONE3_ST_S)
+#define SOC_ETM_REGDMA_EVT_DONE3_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_DONE3_ST_S  14
+/** SOC_ETM_REGDMA_EVT_ERR0_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents REGDMA_evt_err0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_EVT_ERR0_ST    (BIT(15))
+#define SOC_ETM_REGDMA_EVT_ERR0_ST_M  (SOC_ETM_REGDMA_EVT_ERR0_ST_V << SOC_ETM_REGDMA_EVT_ERR0_ST_S)
+#define SOC_ETM_REGDMA_EVT_ERR0_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_ERR0_ST_S  15
+/** SOC_ETM_REGDMA_EVT_ERR1_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents REGDMA_evt_err1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_EVT_ERR1_ST    (BIT(16))
+#define SOC_ETM_REGDMA_EVT_ERR1_ST_M  (SOC_ETM_REGDMA_EVT_ERR1_ST_V << SOC_ETM_REGDMA_EVT_ERR1_ST_S)
+#define SOC_ETM_REGDMA_EVT_ERR1_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_ERR1_ST_S  16
+/** SOC_ETM_REGDMA_EVT_ERR2_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents REGDMA_evt_err2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_EVT_ERR2_ST    (BIT(17))
+#define SOC_ETM_REGDMA_EVT_ERR2_ST_M  (SOC_ETM_REGDMA_EVT_ERR2_ST_V << SOC_ETM_REGDMA_EVT_ERR2_ST_S)
+#define SOC_ETM_REGDMA_EVT_ERR2_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_ERR2_ST_S  17
+/** SOC_ETM_REGDMA_EVT_ERR3_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents REGDMA_evt_err3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_EVT_ERR3_ST    (BIT(18))
+#define SOC_ETM_REGDMA_EVT_ERR3_ST_M  (SOC_ETM_REGDMA_EVT_ERR3_ST_V << SOC_ETM_REGDMA_EVT_ERR3_ST_S)
+#define SOC_ETM_REGDMA_EVT_ERR3_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_ERR3_ST_S  18
+/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents TMPSNSR_evt_over_limit trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST    (BIT(19))
+#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_M  (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S)
+#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V  0x00000001U
+#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S  19
+/** SOC_ETM_I2S0_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents I2S0_evt_rx_done trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S0_EVT_RX_DONE_ST    (BIT(20))
+#define SOC_ETM_I2S0_EVT_RX_DONE_ST_M  (SOC_ETM_I2S0_EVT_RX_DONE_ST_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_S)
+#define SOC_ETM_I2S0_EVT_RX_DONE_ST_V  0x00000001U
+#define SOC_ETM_I2S0_EVT_RX_DONE_ST_S  20
+/** SOC_ETM_I2S0_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents I2S0_evt_tx_done trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S0_EVT_TX_DONE_ST    (BIT(21))
+#define SOC_ETM_I2S0_EVT_TX_DONE_ST_M  (SOC_ETM_I2S0_EVT_TX_DONE_ST_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_S)
+#define SOC_ETM_I2S0_EVT_TX_DONE_ST_V  0x00000001U
+#define SOC_ETM_I2S0_EVT_TX_DONE_ST_S  21
+/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents I2S0_evt_x_words_received trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST    (BIT(22))
+#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_M  (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S)
+#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V  0x00000001U
+#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S  22
+/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents I2S0_evt_x_words_sent trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST    (BIT(23))
+#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_M  (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S)
+#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V  0x00000001U
+#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S  23
+/** SOC_ETM_I2S1_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents I2S1_evt_rx_done trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S1_EVT_RX_DONE_ST    (BIT(24))
+#define SOC_ETM_I2S1_EVT_RX_DONE_ST_M  (SOC_ETM_I2S1_EVT_RX_DONE_ST_V << SOC_ETM_I2S1_EVT_RX_DONE_ST_S)
+#define SOC_ETM_I2S1_EVT_RX_DONE_ST_V  0x00000001U
+#define SOC_ETM_I2S1_EVT_RX_DONE_ST_S  24
+/** SOC_ETM_I2S1_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents I2S1_evt_tx_done trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S1_EVT_TX_DONE_ST    (BIT(25))
+#define SOC_ETM_I2S1_EVT_TX_DONE_ST_M  (SOC_ETM_I2S1_EVT_TX_DONE_ST_V << SOC_ETM_I2S1_EVT_TX_DONE_ST_S)
+#define SOC_ETM_I2S1_EVT_TX_DONE_ST_V  0x00000001U
+#define SOC_ETM_I2S1_EVT_TX_DONE_ST_S  25
+/** SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents I2S1_evt_x_words_received trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST    (BIT(26))
+#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_M  (SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_S)
+#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_V  0x00000001U
+#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_S  26
+/** SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents I2S1_evt_x_words_sent trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST    (BIT(27))
+#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_M  (SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_S)
+#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_V  0x00000001U
+#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_S  27
+/** SOC_ETM_I2S2_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents I2S2_evt_rx_done trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S2_EVT_RX_DONE_ST    (BIT(28))
+#define SOC_ETM_I2S2_EVT_RX_DONE_ST_M  (SOC_ETM_I2S2_EVT_RX_DONE_ST_V << SOC_ETM_I2S2_EVT_RX_DONE_ST_S)
+#define SOC_ETM_I2S2_EVT_RX_DONE_ST_V  0x00000001U
+#define SOC_ETM_I2S2_EVT_RX_DONE_ST_S  28
+/** SOC_ETM_I2S2_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents I2S2_evt_tx_done trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S2_EVT_TX_DONE_ST    (BIT(29))
+#define SOC_ETM_I2S2_EVT_TX_DONE_ST_M  (SOC_ETM_I2S2_EVT_TX_DONE_ST_V << SOC_ETM_I2S2_EVT_TX_DONE_ST_S)
+#define SOC_ETM_I2S2_EVT_TX_DONE_ST_V  0x00000001U
+#define SOC_ETM_I2S2_EVT_TX_DONE_ST_S  29
+/** SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents I2S2_evt_x_words_received trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST    (BIT(30))
+#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_M  (SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_S)
+#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_V  0x00000001U
+#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_S  30
+/** SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents I2S2_evt_x_words_sent trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST    (BIT(31))
+#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_M  (SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_S)
+#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_V  0x00000001U
+#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_S  31
+
+/** SOC_ETM_EVT_ST4_CLR_REG register
+ *  Events trigger status clear register
+ */
+#define SOC_ETM_EVT_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1cc)
+/** SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR    (BIT(0))
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR_S  0
+/** SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR    (BIT(1))
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR_S  1
+/** SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR    (BIT(2))
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR_M  (SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR_S)
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR_S  2
+/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR    (BIT(3))
+#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_M  (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S)
+#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S  3
+/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR    (BIT(4))
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_M  (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S)
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S  4
+/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR    (BIT(5))
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_M  (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S)
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S  5
+/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR    (BIT(6))
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_M  (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S)
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S  6
+/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR    (BIT(7))
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_M  (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S)
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S  7
+/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear ADC_evt_result_done0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR    (BIT(8))
+#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_M  (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S)
+#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S  8
+/** SOC_ETM_ADC_EVT_STOPPED0_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear ADC_evt_stopped0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR    (BIT(9))
+#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_M  (SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V << SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S)
+#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S  9
+/** SOC_ETM_ADC_EVT_STARTED0_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear ADC_evt_started0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR    (BIT(10))
+#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_M  (SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V << SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S)
+#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S  10
+/** SOC_ETM_REGDMA_EVT_DONE0_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear REGDMA_evt_done0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR    (BIT(11))
+#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_M  (SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S)
+#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S  11
+/** SOC_ETM_REGDMA_EVT_DONE1_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear REGDMA_evt_done1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR    (BIT(12))
+#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_M  (SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S)
+#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S  12
+/** SOC_ETM_REGDMA_EVT_DONE2_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear REGDMA_evt_done2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR    (BIT(13))
+#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_M  (SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S)
+#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S  13
+/** SOC_ETM_REGDMA_EVT_DONE3_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear REGDMA_evt_done3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR    (BIT(14))
+#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_M  (SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S)
+#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S  14
+/** SOC_ETM_REGDMA_EVT_ERR0_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear REGDMA_evt_err0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR    (BIT(15))
+#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_M  (SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S)
+#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S  15
+/** SOC_ETM_REGDMA_EVT_ERR1_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear REGDMA_evt_err1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR    (BIT(16))
+#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_M  (SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S)
+#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S  16
+/** SOC_ETM_REGDMA_EVT_ERR2_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear REGDMA_evt_err2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR    (BIT(17))
+#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_M  (SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S)
+#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S  17
+/** SOC_ETM_REGDMA_EVT_ERR3_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear REGDMA_evt_err3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR    (BIT(18))
+#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_M  (SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S)
+#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S  18
+/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR    (BIT(19))
+#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_M  (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S)
+#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V  0x00000001U
+#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S  19
+/** SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear I2S0_evt_rx_done trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR    (BIT(20))
+#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_M  (SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S)
+#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S  20
+/** SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear I2S0_evt_tx_done trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR    (BIT(21))
+#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_M  (SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S)
+#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S  21
+/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear I2S0_evt_x_words_received trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR    (BIT(22))
+#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_M  (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S)
+#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S  22
+/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear I2S0_evt_x_words_sent trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR    (BIT(23))
+#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_M  (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S)
+#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S  23
+/** SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear I2S1_evt_rx_done trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR    (BIT(24))
+#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_M  (SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_S)
+#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_S  24
+/** SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear I2S1_evt_tx_done trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR    (BIT(25))
+#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_M  (SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_S)
+#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_S  25
+/** SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear I2S1_evt_x_words_received trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR    (BIT(26))
+#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_M  (SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_S)
+#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_S  26
+/** SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear I2S1_evt_x_words_sent trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR    (BIT(27))
+#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_M  (SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_S)
+#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_S  27
+/** SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear I2S2_evt_rx_done trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR    (BIT(28))
+#define SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR_M  (SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR_S)
+#define SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR_S  28
+/** SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear I2S2_evt_tx_done trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR    (BIT(29))
+#define SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR_M  (SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR_S)
+#define SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR_S  29
+/** SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear I2S2_evt_x_words_received trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR    (BIT(30))
+#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_M  (SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_S)
+#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_S  30
+/** SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear I2S2_evt_x_words_sent trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR    (BIT(31))
+#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR_M  (SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR_S)
+#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR_S  31
+
+/** SOC_ETM_EVT_ST5_REG register
+ *  Events trigger status register
+ */
+#define SOC_ETM_EVT_ST5_REG (DR_REG_SOC_ETM_BASE + 0x1d0)
+/** SOC_ETM_ULP_EVT_ERR_INTR_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents ULP_evt_err_intr trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ULP_EVT_ERR_INTR_ST    (BIT(0))
+#define SOC_ETM_ULP_EVT_ERR_INTR_ST_M  (SOC_ETM_ULP_EVT_ERR_INTR_ST_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_S)
+#define SOC_ETM_ULP_EVT_ERR_INTR_ST_V  0x00000001U
+#define SOC_ETM_ULP_EVT_ERR_INTR_ST_S  0
+/** SOC_ETM_ULP_EVT_HALT_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents ULP_evt_halt trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ULP_EVT_HALT_ST    (BIT(1))
+#define SOC_ETM_ULP_EVT_HALT_ST_M  (SOC_ETM_ULP_EVT_HALT_ST_V << SOC_ETM_ULP_EVT_HALT_ST_S)
+#define SOC_ETM_ULP_EVT_HALT_ST_V  0x00000001U
+#define SOC_ETM_ULP_EVT_HALT_ST_S  1
+/** SOC_ETM_ULP_EVT_START_INTR_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents ULP_evt_start_intr trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ULP_EVT_START_INTR_ST    (BIT(2))
+#define SOC_ETM_ULP_EVT_START_INTR_ST_M  (SOC_ETM_ULP_EVT_START_INTR_ST_V << SOC_ETM_ULP_EVT_START_INTR_ST_S)
+#define SOC_ETM_ULP_EVT_START_INTR_ST_V  0x00000001U
+#define SOC_ETM_ULP_EVT_START_INTR_ST_S  2
+/** SOC_ETM_RTC_EVT_TICK_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents RTC_evt_tick trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_RTC_EVT_TICK_ST    (BIT(3))
+#define SOC_ETM_RTC_EVT_TICK_ST_M  (SOC_ETM_RTC_EVT_TICK_ST_V << SOC_ETM_RTC_EVT_TICK_ST_S)
+#define SOC_ETM_RTC_EVT_TICK_ST_V  0x00000001U
+#define SOC_ETM_RTC_EVT_TICK_ST_S  3
+/** SOC_ETM_RTC_EVT_OVF_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents RTC_evt_ovf trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_RTC_EVT_OVF_ST    (BIT(4))
+#define SOC_ETM_RTC_EVT_OVF_ST_M  (SOC_ETM_RTC_EVT_OVF_ST_V << SOC_ETM_RTC_EVT_OVF_ST_S)
+#define SOC_ETM_RTC_EVT_OVF_ST_V  0x00000001U
+#define SOC_ETM_RTC_EVT_OVF_ST_S  4
+/** SOC_ETM_RTC_EVT_CMP_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents RTC_evt_cmp trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_RTC_EVT_CMP_ST    (BIT(5))
+#define SOC_ETM_RTC_EVT_CMP_ST_M  (SOC_ETM_RTC_EVT_CMP_ST_V << SOC_ETM_RTC_EVT_CMP_ST_S)
+#define SOC_ETM_RTC_EVT_CMP_ST_V  0x00000001U
+#define SOC_ETM_RTC_EVT_CMP_ST_S  5
+/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents PDMA_AHB_evt_in_done_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST    (BIT(6))
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_S  6
+/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents PDMA_AHB_evt_in_done_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST    (BIT(7))
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_S  7
+/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents PDMA_AHB_evt_in_done_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST    (BIT(8))
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_S  8
+/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST    (BIT(9))
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_S  9
+/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST    (BIT(10))
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_S  10
+/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST    (BIT(11))
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_S  11
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST    (BIT(12))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_S  12
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST    (BIT(13))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_S  13
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST    (BIT(14))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_S  14
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST    (BIT(15))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_S  15
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST    (BIT(16))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_S  16
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST    (BIT(17))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_S  17
+/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents PDMA_AHB_evt_out_done_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST    (BIT(18))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_S  18
+/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents PDMA_AHB_evt_out_done_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST    (BIT(19))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_S  19
+/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents PDMA_AHB_evt_out_done_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST    (BIT(20))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_S  20
+/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents PDMA_AHB_evt_out_eof_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST    (BIT(21))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_S  21
+/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents PDMA_AHB_evt_out_eof_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST    (BIT(22))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_S  22
+/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents PDMA_AHB_evt_out_eof_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST    (BIT(23))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_S  23
+/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST    (BIT(24))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_S  24
+/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST    (BIT(25))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_S  25
+/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST    (BIT(26))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_S  26
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST    (BIT(27))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_S  27
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST    (BIT(28))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_S  28
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST    (BIT(29))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_S  29
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST    (BIT(30))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_S  30
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST    (BIT(31))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_S  31
+
+/** SOC_ETM_EVT_ST5_CLR_REG register
+ *  Events trigger status clear register
+ */
+#define SOC_ETM_EVT_ST5_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1d4)
+/** SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear ULP_evt_err_intr trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR    (BIT(0))
+#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_M  (SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S)
+#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V  0x00000001U
+#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S  0
+/** SOC_ETM_ULP_EVT_HALT_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear ULP_evt_halt trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ULP_EVT_HALT_ST_CLR    (BIT(1))
+#define SOC_ETM_ULP_EVT_HALT_ST_CLR_M  (SOC_ETM_ULP_EVT_HALT_ST_CLR_V << SOC_ETM_ULP_EVT_HALT_ST_CLR_S)
+#define SOC_ETM_ULP_EVT_HALT_ST_CLR_V  0x00000001U
+#define SOC_ETM_ULP_EVT_HALT_ST_CLR_S  1
+/** SOC_ETM_ULP_EVT_START_INTR_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear ULP_evt_start_intr trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR    (BIT(2))
+#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_M  (SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S)
+#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V  0x00000001U
+#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S  2
+/** SOC_ETM_RTC_EVT_TICK_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear RTC_evt_tick trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_RTC_EVT_TICK_ST_CLR    (BIT(3))
+#define SOC_ETM_RTC_EVT_TICK_ST_CLR_M  (SOC_ETM_RTC_EVT_TICK_ST_CLR_V << SOC_ETM_RTC_EVT_TICK_ST_CLR_S)
+#define SOC_ETM_RTC_EVT_TICK_ST_CLR_V  0x00000001U
+#define SOC_ETM_RTC_EVT_TICK_ST_CLR_S  3
+/** SOC_ETM_RTC_EVT_OVF_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear RTC_evt_ovf trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_RTC_EVT_OVF_ST_CLR    (BIT(4))
+#define SOC_ETM_RTC_EVT_OVF_ST_CLR_M  (SOC_ETM_RTC_EVT_OVF_ST_CLR_V << SOC_ETM_RTC_EVT_OVF_ST_CLR_S)
+#define SOC_ETM_RTC_EVT_OVF_ST_CLR_V  0x00000001U
+#define SOC_ETM_RTC_EVT_OVF_ST_CLR_S  4
+/** SOC_ETM_RTC_EVT_CMP_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear RTC_evt_cmp trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_RTC_EVT_CMP_ST_CLR    (BIT(5))
+#define SOC_ETM_RTC_EVT_CMP_ST_CLR_M  (SOC_ETM_RTC_EVT_CMP_ST_CLR_V << SOC_ETM_RTC_EVT_CMP_ST_CLR_S)
+#define SOC_ETM_RTC_EVT_CMP_ST_CLR_V  0x00000001U
+#define SOC_ETM_RTC_EVT_CMP_ST_CLR_S  5
+/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR    (BIT(6))
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_S  6
+/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR    (BIT(7))
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_S  7
+/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR    (BIT(8))
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_S  8
+/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR    (BIT(9))
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_S  9
+/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR    (BIT(10))
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_S  10
+/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR    (BIT(11))
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_S  11
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR    (BIT(12))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S  12
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR    (BIT(13))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S  13
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR    (BIT(14))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S  14
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR    (BIT(15))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_S  15
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR    (BIT(16))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_S  16
+/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR    (BIT(17))
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_S  17
+/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR    (BIT(18))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_S  18
+/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR    (BIT(19))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_S  19
+/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR    (BIT(20))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_S  20
+/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR    (BIT(21))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_S  21
+/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR    (BIT(22))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_S  22
+/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR    (BIT(23))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_S  23
+/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR    (BIT(24))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S  24
+/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR    (BIT(25))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S  25
+/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR    (BIT(26))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S  26
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR    (BIT(27))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S  27
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR    (BIT(28))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S  28
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR    (BIT(29))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S  29
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR    (BIT(30))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S  30
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR    (BIT(31))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S  31
+
+/** SOC_ETM_EVT_ST6_REG register
+ *  Events trigger status register
+ */
+#define SOC_ETM_EVT_ST6_REG (DR_REG_SOC_ETM_BASE + 0x1d8)
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST    (BIT(0))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_S  0
+/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents PDMA_AXI_evt_in_done_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST    (BIT(1))
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_S  1
+/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents PDMA_AXI_evt_in_done_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST    (BIT(2))
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_S  2
+/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents PDMA_AXI_evt_in_done_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST    (BIT(3))
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_S  3
+/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST    (BIT(4))
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_S  4
+/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST    (BIT(5))
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_S  5
+/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST    (BIT(6))
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_S  6
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST    (BIT(7))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_S  7
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST    (BIT(8))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_S  8
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST    (BIT(9))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_S  9
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST    (BIT(10))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_S  10
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST    (BIT(11))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_S  11
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST    (BIT(12))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_S  12
+/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents PDMA_AXI_evt_out_done_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST    (BIT(13))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_S  13
+/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents PDMA_AXI_evt_out_done_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST    (BIT(14))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_S  14
+/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents PDMA_AXI_evt_out_done_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST    (BIT(15))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_S  15
+/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents PDMA_AXI_evt_out_eof_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST    (BIT(16))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_S  16
+/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents PDMA_AXI_evt_out_eof_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST    (BIT(17))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_S  17
+/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents PDMA_AXI_evt_out_eof_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST    (BIT(18))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_S  18
+/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST    (BIT(19))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_S  19
+/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST    (BIT(20))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_S  20
+/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST    (BIT(21))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_S  21
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST    (BIT(22))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_S  22
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST    (BIT(23))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_S  23
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST    (BIT(24))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_S  24
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST    (BIT(25))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_S  25
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST    (BIT(26))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_S  26
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST    (BIT(27))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_S  27
+/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents PMU_evt_sleep_weekup trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST    (BIT(28))
+#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_M  (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S)
+#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V  0x00000001U
+#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S  28
+/** SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents DMA2D_evt_in_done_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST    (BIT(29))
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_M  (SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_V << SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_S)
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_S  29
+/** SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents DMA2D_evt_in_done_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST    (BIT(30))
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_M  (SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_V << SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_S)
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_S  30
+/** SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents DMA2D_evt_in_suc_eof_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST    (BIT(31))
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_M  (SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_V << SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_S)
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_S  31
+
+/** SOC_ETM_EVT_ST6_CLR_REG register
+ *  Events trigger status clear register
+ */
+#define SOC_ETM_EVT_ST6_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1dc)
+/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR    (BIT(0))
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S  0
+/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR    (BIT(1))
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_S  1
+/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR    (BIT(2))
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_S  2
+/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR    (BIT(3))
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_S  3
+/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR    (BIT(4))
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_S  4
+/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR    (BIT(5))
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_S  5
+/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR    (BIT(6))
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_S  6
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR    (BIT(7))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S  7
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR    (BIT(8))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S  8
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR    (BIT(9))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S  9
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR    (BIT(10))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_S  10
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR    (BIT(11))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_S  11
+/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR    (BIT(12))
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_S  12
+/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR    (BIT(13))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_S  13
+/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR    (BIT(14))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_S  14
+/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR    (BIT(15))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_S  15
+/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR    (BIT(16))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_S  16
+/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR    (BIT(17))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_S  17
+/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR    (BIT(18))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_S  18
+/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR    (BIT(19))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S  19
+/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR    (BIT(20))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S  20
+/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR    (BIT(21))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S  21
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR    (BIT(22))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S  22
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR    (BIT(23))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S  23
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR    (BIT(24))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S  24
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR    (BIT(25))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S  25
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR    (BIT(26))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S  26
+/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR    (BIT(27))
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S  27
+/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear PMU_evt_sleep_weekup trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR    (BIT(28))
+#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_M  (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S)
+#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V  0x00000001U
+#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S  28
+/** SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR    (BIT(29))
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR_M  (SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR_V << SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR_S  29
+/** SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR    (BIT(30))
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR_M  (SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR_S  30
+/** SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR    (BIT(31))
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_M  (SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_V << SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_S  31
+
+/** SOC_ETM_EVT_ST7_REG register
+ *  Events trigger status register
+ */
+#define SOC_ETM_EVT_ST7_REG (DR_REG_SOC_ETM_BASE + 0x1e0)
+/** SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents DMA2D_evt_in_suc_eof_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST    (BIT(0))
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_M  (SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_S)
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_S  0
+/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents DMA2D_evt_out_done_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST    (BIT(1))
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_M  (SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_S)
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_S  1
+/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents DMA2D_evt_out_done_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST    (BIT(2))
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_M  (SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_S)
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_S  2
+/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents DMA2D_evt_out_done_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST    (BIT(3))
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_M  (SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_S)
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_S  3
+/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents DMA2D_evt_out_eof_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST    (BIT(4))
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_M  (SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_S)
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_S  4
+/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents DMA2D_evt_out_eof_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST    (BIT(5))
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_M  (SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_S)
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_S  5
+/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents DMA2D_evt_out_eof_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST    (BIT(6))
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_M  (SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_S)
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_S  6
+/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents DMA2D_evt_out_total_eof_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST    (BIT(7))
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_M  (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_S)
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_S  7
+/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents DMA2D_evt_out_total_eof_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST    (BIT(8))
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_M  (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_S)
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_S  8
+/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents DMA2D_evt_out_total_eof_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST    (BIT(9))
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_M  (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_S)
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_S  9
+
+/** SOC_ETM_EVT_ST7_CLR_REG register
+ *  Events trigger status clear register
+ */
+#define SOC_ETM_EVT_ST7_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1e4)
+/** SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR    (BIT(0))
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_M  (SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_S  0
+/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR    (BIT(1))
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_M  (SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_S  1
+/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR    (BIT(2))
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_M  (SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_S  2
+/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR    (BIT(3))
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_M  (SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_S  3
+/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR    (BIT(4))
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_M  (SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_S  4
+/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR    (BIT(5))
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_M  (SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_S  5
+/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR    (BIT(6))
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_M  (SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_S  6
+/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR    (BIT(7))
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_M  (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S  7
+/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR    (BIT(8))
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M  (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S  8
+/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR    (BIT(9))
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M  (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S)
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S  9
+
+/** SOC_ETM_TASK_ST0_REG register
+ *  Tasks trigger status register
+ */
+#define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1e8)
+/** SOC_ETM_GPIO_TASK_CH0_SET_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents GPIO_task_ch0_set trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH0_SET_ST    (BIT(0))
+#define SOC_ETM_GPIO_TASK_CH0_SET_ST_M  (SOC_ETM_GPIO_TASK_CH0_SET_ST_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_S)
+#define SOC_ETM_GPIO_TASK_CH0_SET_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH0_SET_ST_S  0
+/** SOC_ETM_GPIO_TASK_CH1_SET_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents GPIO_task_ch1_set trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH1_SET_ST    (BIT(1))
+#define SOC_ETM_GPIO_TASK_CH1_SET_ST_M  (SOC_ETM_GPIO_TASK_CH1_SET_ST_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_S)
+#define SOC_ETM_GPIO_TASK_CH1_SET_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH1_SET_ST_S  1
+/** SOC_ETM_GPIO_TASK_CH2_SET_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents GPIO_task_ch2_set trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH2_SET_ST    (BIT(2))
+#define SOC_ETM_GPIO_TASK_CH2_SET_ST_M  (SOC_ETM_GPIO_TASK_CH2_SET_ST_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_S)
+#define SOC_ETM_GPIO_TASK_CH2_SET_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH2_SET_ST_S  2
+/** SOC_ETM_GPIO_TASK_CH3_SET_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents GPIO_task_ch3_set trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH3_SET_ST    (BIT(3))
+#define SOC_ETM_GPIO_TASK_CH3_SET_ST_M  (SOC_ETM_GPIO_TASK_CH3_SET_ST_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_S)
+#define SOC_ETM_GPIO_TASK_CH3_SET_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH3_SET_ST_S  3
+/** SOC_ETM_GPIO_TASK_CH4_SET_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents GPIO_task_ch4_set trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH4_SET_ST    (BIT(4))
+#define SOC_ETM_GPIO_TASK_CH4_SET_ST_M  (SOC_ETM_GPIO_TASK_CH4_SET_ST_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_S)
+#define SOC_ETM_GPIO_TASK_CH4_SET_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH4_SET_ST_S  4
+/** SOC_ETM_GPIO_TASK_CH5_SET_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents GPIO_task_ch5_set trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH5_SET_ST    (BIT(5))
+#define SOC_ETM_GPIO_TASK_CH5_SET_ST_M  (SOC_ETM_GPIO_TASK_CH5_SET_ST_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_S)
+#define SOC_ETM_GPIO_TASK_CH5_SET_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH5_SET_ST_S  5
+/** SOC_ETM_GPIO_TASK_CH6_SET_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents GPIO_task_ch6_set trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH6_SET_ST    (BIT(6))
+#define SOC_ETM_GPIO_TASK_CH6_SET_ST_M  (SOC_ETM_GPIO_TASK_CH6_SET_ST_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_S)
+#define SOC_ETM_GPIO_TASK_CH6_SET_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH6_SET_ST_S  6
+/** SOC_ETM_GPIO_TASK_CH7_SET_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents GPIO_task_ch7_set trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH7_SET_ST    (BIT(7))
+#define SOC_ETM_GPIO_TASK_CH7_SET_ST_M  (SOC_ETM_GPIO_TASK_CH7_SET_ST_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_S)
+#define SOC_ETM_GPIO_TASK_CH7_SET_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH7_SET_ST_S  7
+/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents GPIO_task_ch0_clear trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST    (BIT(8))
+#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S)
+#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S  8
+/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents GPIO_task_ch1_clear trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST    (BIT(9))
+#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S)
+#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S  9
+/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents GPIO_task_ch2_clear trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST    (BIT(10))
+#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S)
+#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S  10
+/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents GPIO_task_ch3_clear trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST    (BIT(11))
+#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S)
+#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S  11
+/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents GPIO_task_ch4_clear trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST    (BIT(12))
+#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S)
+#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S  12
+/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents GPIO_task_ch5_clear trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST    (BIT(13))
+#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S)
+#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S  13
+/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents GPIO_task_ch6_clear trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST    (BIT(14))
+#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S)
+#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S  14
+/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents GPIO_task_ch7_clear trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST    (BIT(15))
+#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S)
+#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S  15
+/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents GPIO_task_ch0_toggle trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST    (BIT(16))
+#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S)
+#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S  16
+/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents GPIO_task_ch1_toggle trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST    (BIT(17))
+#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S)
+#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S  17
+/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents GPIO_task_ch2_toggle trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST    (BIT(18))
+#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S)
+#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S  18
+/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents GPIO_task_ch3_toggle trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST    (BIT(19))
+#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S)
+#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S  19
+/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents GPIO_task_ch4_toggle trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST    (BIT(20))
+#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S)
+#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S  20
+/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents GPIO_task_ch5_toggle trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST    (BIT(21))
+#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S)
+#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S  21
+/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents GPIO_task_ch6_toggle trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST    (BIT(22))
+#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S)
+#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S  22
+/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents GPIO_task_ch7_toggle trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST    (BIT(23))
+#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S)
+#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S  23
+/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents LEDC_task_timer0_res_update trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST    (BIT(24))
+#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_M  (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S  24
+/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents LEDC_task_timer1_res_update trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST    (BIT(25))
+#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_M  (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S  25
+/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents LEDC_task_timer2_res_update trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST    (BIT(26))
+#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_M  (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S  26
+/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents LEDC_task_timer3_res_update trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST    (BIT(27))
+#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_M  (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S  27
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents LEDC_task_duty_scale_update_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST    (BIT(28))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S  28
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents LEDC_task_duty_scale_update_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST    (BIT(29))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S  29
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents LEDC_task_duty_scale_update_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST    (BIT(30))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S  30
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents LEDC_task_duty_scale_update_ch3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST    (BIT(31))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S  31
+
+/** SOC_ETM_TASK_ST0_CLR_REG register
+ *  Tasks trigger status clear register
+ */
+#define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ec)
+/** SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch0_set trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR    (BIT(0))
+#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S  0
+/** SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch1_set trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR    (BIT(1))
+#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S  1
+/** SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch2_set trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR    (BIT(2))
+#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S  2
+/** SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch3_set trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR    (BIT(3))
+#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S  3
+/** SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch4_set trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR    (BIT(4))
+#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S  4
+/** SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch5_set trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR    (BIT(5))
+#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S  5
+/** SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch6_set trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR    (BIT(6))
+#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S  6
+/** SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch7_set trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR    (BIT(7))
+#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S  7
+/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch0_clear trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR    (BIT(8))
+#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S  8
+/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch1_clear trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR    (BIT(9))
+#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S  9
+/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch2_clear trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR    (BIT(10))
+#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S  10
+/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch3_clear trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR    (BIT(11))
+#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S  11
+/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch4_clear trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR    (BIT(12))
+#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S  12
+/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch5_clear trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR    (BIT(13))
+#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S  13
+/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch6_clear trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR    (BIT(14))
+#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S  14
+/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch7_clear trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR    (BIT(15))
+#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S  15
+/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch0_toggle trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR    (BIT(16))
+#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S  16
+/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch1_toggle trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR    (BIT(17))
+#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S  17
+/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch2_toggle trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR    (BIT(18))
+#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S  18
+/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch3_toggle trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR    (BIT(19))
+#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S  19
+/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch4_toggle trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR    (BIT(20))
+#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S  20
+/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch5_toggle trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR    (BIT(21))
+#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S  21
+/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch6_toggle trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR    (BIT(22))
+#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S  22
+/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear GPIO_task_ch7_toggle trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR    (BIT(23))
+#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S)
+#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V  0x00000001U
+#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S  23
+/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer0_res_update trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR    (BIT(24))
+#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S  24
+/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer1_res_update trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR    (BIT(25))
+#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S  25
+/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer2_res_update trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR    (BIT(26))
+#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S  26
+/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer3_res_update trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR    (BIT(27))
+#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S  27
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR    (BIT(28))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S  28
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR    (BIT(29))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S  29
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR    (BIT(30))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S  30
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR    (BIT(31))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S  31
+
+/** SOC_ETM_TASK_ST1_REG register
+ *  Tasks trigger status register
+ */
+#define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1f0)
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents LEDC_task_duty_scale_update_ch4 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST    (BIT(0))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S  0
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents LEDC_task_duty_scale_update_ch5 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST    (BIT(1))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S  1
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents LEDC_task_duty_scale_update_ch6 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST    (BIT(2))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_S  2
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents LEDC_task_duty_scale_update_ch7 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST    (BIT(3))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_S  3
+/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents LEDC_task_timer0_cap trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST    (BIT(4))
+#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_M  (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S  4
+/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents LEDC_task_timer1_cap trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST    (BIT(5))
+#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_M  (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S  5
+/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents LEDC_task_timer2_cap trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST    (BIT(6))
+#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_M  (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S  6
+/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents LEDC_task_timer3_cap trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST    (BIT(7))
+#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_M  (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S  7
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents LEDC_task_sig_out_dis_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST    (BIT(8))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S  8
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents LEDC_task_sig_out_dis_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST    (BIT(9))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S  9
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents LEDC_task_sig_out_dis_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST    (BIT(10))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S  10
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents LEDC_task_sig_out_dis_ch3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST    (BIT(11))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S  11
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents LEDC_task_sig_out_dis_ch4 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST    (BIT(12))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S  12
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents LEDC_task_sig_out_dis_ch5 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST    (BIT(13))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S  13
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents LEDC_task_sig_out_dis_ch6 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST    (BIT(14))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_S  14
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents LEDC_task_sig_out_dis_ch7 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST    (BIT(15))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_S  15
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST    (BIT(16))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S  16
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST    (BIT(17))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S  17
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST    (BIT(18))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S  18
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST    (BIT(19))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S  19
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST    (BIT(20))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S  20
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST    (BIT(21))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S  21
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST    (BIT(22))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_S  22
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST    (BIT(23))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_S  23
+/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents LEDC_task_timer0_rst trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST    (BIT(24))
+#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_M  (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S  24
+/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents LEDC_task_timer1_rst trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST    (BIT(25))
+#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_M  (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S  25
+/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents LEDC_task_timer2_rst trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST    (BIT(26))
+#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_M  (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S  26
+/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents LEDC_task_timer3_rst trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST    (BIT(27))
+#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_M  (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S  27
+/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents LEDC_task_timer0_resume trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST    (BIT(28))
+#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_M  (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S  28
+/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents LEDC_task_timer1_resume trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST    (BIT(29))
+#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_M  (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S  29
+/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents LEDC_task_timer2_resume trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST    (BIT(30))
+#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_M  (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S  30
+/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents LEDC_task_timer3_resume trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST    (BIT(31))
+#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_M  (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S  31
+
+/** SOC_ETM_TASK_ST1_CLR_REG register
+ *  Tasks trigger status clear register
+ */
+#define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1f4)
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR    (BIT(0))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S  0
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR    (BIT(1))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S  1
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR    (BIT(2))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_S  2
+/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR    (BIT(3))
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_S  3
+/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer0_cap trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR    (BIT(4))
+#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S  4
+/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer1_cap trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR    (BIT(5))
+#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S  5
+/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer2_cap trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR    (BIT(6))
+#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S  6
+/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer3_cap trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR    (BIT(7))
+#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S  7
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR    (BIT(8))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S  8
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR    (BIT(9))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S  9
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR    (BIT(10))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S  10
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR    (BIT(11))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S  11
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR    (BIT(12))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S  12
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR    (BIT(13))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S  13
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR    (BIT(14))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_S  14
+/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR    (BIT(15))
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_S  15
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR    (BIT(16))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S  16
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR    (BIT(17))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S  17
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR    (BIT(18))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S  18
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR    (BIT(19))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S  19
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR    (BIT(20))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S  20
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR    (BIT(21))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S  21
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR    (BIT(22))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_S  22
+/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR    (BIT(23))
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_S  23
+/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer0_rst trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR    (BIT(24))
+#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S  24
+/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer1_rst trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR    (BIT(25))
+#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S  25
+/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer2_rst trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR    (BIT(26))
+#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S  26
+/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer3_rst trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR    (BIT(27))
+#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S  27
+/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer0_resume trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR    (BIT(28))
+#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S  28
+/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer1_resume trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR    (BIT(29))
+#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S  29
+/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer2_resume trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR    (BIT(30))
+#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S  30
+/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer3_resume trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR    (BIT(31))
+#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S  31
+
+/** SOC_ETM_TASK_ST2_REG register
+ *  Tasks trigger status register
+ */
+#define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1f8)
+/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents LEDC_task_timer0_pause trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST    (BIT(0))
+#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_M  (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S  0
+/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents LEDC_task_timer1_pause trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST    (BIT(1))
+#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_M  (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S  1
+/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents LEDC_task_timer2_pause trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST    (BIT(2))
+#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_M  (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S  2
+/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents LEDC_task_timer3_pause trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST    (BIT(3))
+#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_M  (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S)
+#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S  3
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents LEDC_task_gamma_restart_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST    (BIT(4))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S  4
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents LEDC_task_gamma_restart_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST    (BIT(5))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S  5
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents LEDC_task_gamma_restart_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST    (BIT(6))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S  6
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents LEDC_task_gamma_restart_ch3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST    (BIT(7))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S  7
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents LEDC_task_gamma_restart_ch4 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST    (BIT(8))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S  8
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents LEDC_task_gamma_restart_ch5 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST    (BIT(9))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S  9
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents LEDC_task_gamma_restart_ch6 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST    (BIT(10))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_S  10
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents LEDC_task_gamma_restart_ch7 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST    (BIT(11))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_S  11
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents LEDC_task_gamma_pause_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST    (BIT(12))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S  12
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents LEDC_task_gamma_pause_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST    (BIT(13))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S  13
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents LEDC_task_gamma_pause_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST    (BIT(14))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S  14
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents LEDC_task_gamma_pause_ch3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST    (BIT(15))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S  15
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents LEDC_task_gamma_pause_ch4 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST    (BIT(16))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S  16
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents LEDC_task_gamma_pause_ch5 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST    (BIT(17))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S  17
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents LEDC_task_gamma_pause_ch6 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST    (BIT(18))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_S  18
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents LEDC_task_gamma_pause_ch7 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST    (BIT(19))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_S  19
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents LEDC_task_gamma_resume_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST    (BIT(20))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S  20
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents LEDC_task_gamma_resume_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST    (BIT(21))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S  21
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents LEDC_task_gamma_resume_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST    (BIT(22))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S  22
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents LEDC_task_gamma_resume_ch3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST    (BIT(23))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S  23
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents LEDC_task_gamma_resume_ch4 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST    (BIT(24))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S  24
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents LEDC_task_gamma_resume_ch5 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST    (BIT(25))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S  25
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents LEDC_task_gamma_resume_ch6 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST    (BIT(26))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_S  26
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents LEDC_task_gamma_resume_ch7 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST    (BIT(27))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_S  27
+/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents TG0_task_cnt_start_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST    (BIT(28))
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_M  (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S)
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S  28
+/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents TG0_task_alarm_start_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST    (BIT(29))
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_M  (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S)
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S  29
+/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents TG0_task_cnt_stop_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST    (BIT(30))
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_M  (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S)
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S  30
+/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents TG0_task_cnt_reload_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST    (BIT(31))
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_M  (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S)
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S  31
+
+/** SOC_ETM_TASK_ST2_CLR_REG register
+ *  Tasks trigger status clear register
+ */
+#define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1fc)
+/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer0_pause trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR    (BIT(0))
+#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S  0
+/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer1_pause trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR    (BIT(1))
+#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S  1
+/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer2_pause trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR    (BIT(2))
+#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S  2
+/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear LEDC_task_timer3_pause trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR    (BIT(3))
+#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S  3
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR    (BIT(4))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S  4
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR    (BIT(5))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S  5
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR    (BIT(6))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S  6
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR    (BIT(7))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S  7
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR    (BIT(8))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S  8
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR    (BIT(9))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S  9
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR    (BIT(10))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_S  10
+/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR    (BIT(11))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_S  11
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR    (BIT(12))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S  12
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR    (BIT(13))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S  13
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR    (BIT(14))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S  14
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR    (BIT(15))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S  15
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR    (BIT(16))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S  16
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR    (BIT(17))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S  17
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR    (BIT(18))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_S  18
+/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR    (BIT(19))
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_S  19
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR    (BIT(20))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S  20
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR    (BIT(21))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S  21
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR    (BIT(22))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S  22
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR    (BIT(23))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S  23
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR    (BIT(24))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S  24
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR    (BIT(25))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S  25
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR    (BIT(26))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_S  26
+/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR    (BIT(27))
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_S)
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_V  0x00000001U
+#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_S  27
+/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR    (BIT(28))
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S  28
+/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR    (BIT(29))
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_M  (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S  29
+/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR    (BIT(30))
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S  30
+/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR    (BIT(31))
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S  31
+
+/** SOC_ETM_TASK_ST3_REG register
+ *  Tasks trigger status register
+ */
+#define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_ETM_BASE + 0x200)
+/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents TG0_task_cnt_cap_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST    (BIT(0))
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_M  (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S)
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S  0
+/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents TG0_task_cnt_start_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST    (BIT(1))
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_M  (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S)
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S  1
+/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents TG0_task_alarm_start_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST    (BIT(2))
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_M  (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S)
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S  2
+/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents TG0_task_cnt_stop_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST    (BIT(3))
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_M  (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S)
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S  3
+/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents TG0_task_cnt_reload_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST    (BIT(4))
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_M  (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S)
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S  4
+/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents TG0_task_cnt_cap_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST    (BIT(5))
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_M  (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S)
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S  5
+/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents TG1_task_cnt_start_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST    (BIT(6))
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_M  (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S)
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S  6
+/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents TG1_task_alarm_start_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST    (BIT(7))
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_M  (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S)
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S  7
+/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents TG1_task_cnt_stop_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST    (BIT(8))
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_M  (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S)
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S  8
+/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents TG1_task_cnt_reload_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST    (BIT(9))
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_M  (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S)
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S  9
+/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents TG1_task_cnt_cap_timer0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST    (BIT(10))
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_M  (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S)
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S  10
+/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents TG1_task_cnt_start_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST    (BIT(11))
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_M  (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S)
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S  11
+/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents TG1_task_alarm_start_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST    (BIT(12))
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_M  (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S)
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S  12
+/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents TG1_task_cnt_stop_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST    (BIT(13))
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_M  (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S)
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S  13
+/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents TG1_task_cnt_reload_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST    (BIT(14))
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_M  (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S)
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S  14
+/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents TG1_task_cnt_cap_timer1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST    (BIT(15))
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_M  (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S)
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S  15
+/** SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents MCPWM0_task_cmpr0_a_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST    (BIT(16))
+#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_S  16
+/** SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents MCPWM0_task_cmpr1_a_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST    (BIT(17))
+#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_S  17
+/** SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents MCPWM0_task_cmpr2_a_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST    (BIT(18))
+#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_S  18
+/** SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents MCPWM0_task_cmpr0_b_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST    (BIT(19))
+#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_S  19
+/** SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents MCPWM0_task_cmpr1_b_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST    (BIT(20))
+#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_S  20
+/** SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents MCPWM0_task_cmpr2_b_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST    (BIT(21))
+#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_S  21
+/** SOC_ETM_MCPWM0_TASK_GEN_STOP_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents MCPWM0_task_gen_stop trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST    (BIT(22))
+#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_M  (SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_V << SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_S)
+#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_S  22
+/** SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents MCPWM0_task_timer0_syn trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST    (BIT(23))
+#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_S  23
+/** SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents MCPWM0_task_timer1_syn trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST    (BIT(24))
+#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_S  24
+/** SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents MCPWM0_task_timer2_syn trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST    (BIT(25))
+#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_S  25
+/** SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents MCPWM0_task_timer0_period_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST    (BIT(26))
+#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_S  26
+/** SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents MCPWM0_task_timer1_period_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST    (BIT(27))
+#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_S  27
+/** SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents MCPWM0_task_timer2_period_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST    (BIT(28))
+#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_S  28
+/** SOC_ETM_MCPWM0_TASK_TZ0_OST_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents MCPWM0_task_tz0_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST    (BIT(29))
+#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_M  (SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_S)
+#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_S  29
+/** SOC_ETM_MCPWM0_TASK_TZ1_OST_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents MCPWM0_task_tz1_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST    (BIT(30))
+#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_M  (SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_S)
+#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_S  30
+/** SOC_ETM_MCPWM0_TASK_TZ2_OST_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents MCPWM0_task_tz2_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST    (BIT(31))
+#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_M  (SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_S)
+#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_S  31
+
+/** SOC_ETM_TASK_ST3_CLR_REG register
+ *  Tasks trigger status clear register
+ */
+#define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x204)
+/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR    (BIT(0))
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S  0
+/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR    (BIT(1))
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S  1
+/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR    (BIT(2))
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_M  (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S  2
+/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR    (BIT(3))
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S  3
+/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR    (BIT(4))
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S  4
+/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR    (BIT(5))
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S  5
+/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR    (BIT(6))
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S  6
+/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR    (BIT(7))
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_M  (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S  7
+/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR    (BIT(8))
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S  8
+/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR    (BIT(9))
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S  9
+/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR    (BIT(10))
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S)
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S  10
+/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR    (BIT(11))
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S  11
+/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR    (BIT(12))
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_M  (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S  12
+/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR    (BIT(13))
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S  13
+/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR    (BIT(14))
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S  14
+/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR    (BIT(15))
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S)
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V  0x00000001U
+#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S  15
+/** SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR    (BIT(16))
+#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_S  16
+/** SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR    (BIT(17))
+#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_S  17
+/** SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR    (BIT(18))
+#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_S  18
+/** SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR    (BIT(19))
+#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_S  19
+/** SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR    (BIT(20))
+#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_S  20
+/** SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR    (BIT(21))
+#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_S  21
+/** SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_gen_stop trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR    (BIT(22))
+#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_S  22
+/** SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR    (BIT(23))
+#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_S  23
+/** SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR    (BIT(24))
+#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_S  24
+/** SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR    (BIT(25))
+#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_S  25
+/** SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR    (BIT(26))
+#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_S  26
+/** SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR    (BIT(27))
+#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_S  27
+/** SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR    (BIT(28))
+#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_S  28
+/** SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR    (BIT(29))
+#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_S  29
+/** SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR    (BIT(30))
+#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_S  30
+/** SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR    (BIT(31))
+#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_S  31
+
+/** SOC_ETM_TASK_ST4_REG register
+ *  Tasks trigger status register
+ */
+#define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_ETM_BASE + 0x208)
+/** SOC_ETM_MCPWM0_TASK_CLR0_OST_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents MCPWM0_task_clr0_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST    (BIT(0))
+#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_M  (SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_S  0
+/** SOC_ETM_MCPWM0_TASK_CLR1_OST_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents MCPWM0_task_clr1_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST    (BIT(1))
+#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_M  (SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_S  1
+/** SOC_ETM_MCPWM0_TASK_CLR2_OST_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents MCPWM0_task_clr2_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST    (BIT(2))
+#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_M  (SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_S  2
+/** SOC_ETM_MCPWM0_TASK_CAP0_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents MCPWM0_task_cap0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CAP0_ST    (BIT(3))
+#define SOC_ETM_MCPWM0_TASK_CAP0_ST_M  (SOC_ETM_MCPWM0_TASK_CAP0_ST_V << SOC_ETM_MCPWM0_TASK_CAP0_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CAP0_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CAP0_ST_S  3
+/** SOC_ETM_MCPWM0_TASK_CAP1_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents MCPWM0_task_cap1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CAP1_ST    (BIT(4))
+#define SOC_ETM_MCPWM0_TASK_CAP1_ST_M  (SOC_ETM_MCPWM0_TASK_CAP1_ST_V << SOC_ETM_MCPWM0_TASK_CAP1_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CAP1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CAP1_ST_S  4
+/** SOC_ETM_MCPWM0_TASK_CAP2_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents MCPWM0_task_cap2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM0_TASK_CAP2_ST    (BIT(5))
+#define SOC_ETM_MCPWM0_TASK_CAP2_ST_M  (SOC_ETM_MCPWM0_TASK_CAP2_ST_V << SOC_ETM_MCPWM0_TASK_CAP2_ST_S)
+#define SOC_ETM_MCPWM0_TASK_CAP2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CAP2_ST_S  5
+/** SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents MCPWM1_task_cmpr0_a_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST    (BIT(6))
+#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_M  (SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_S  6
+/** SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents MCPWM1_task_cmpr1_a_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST    (BIT(7))
+#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_M  (SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_S  7
+/** SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents MCPWM1_task_cmpr2_a_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST    (BIT(8))
+#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_M  (SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_S  8
+/** SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents MCPWM1_task_cmpr0_b_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST    (BIT(9))
+#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_M  (SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_S  9
+/** SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents MCPWM1_task_cmpr1_b_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST    (BIT(10))
+#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_M  (SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_S  10
+/** SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents MCPWM1_task_cmpr2_b_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST    (BIT(11))
+#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_M  (SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_S  11
+/** SOC_ETM_MCPWM1_TASK_GEN_STOP_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents MCPWM1_task_gen_stop trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST    (BIT(12))
+#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_M  (SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_V << SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_S)
+#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_S  12
+/** SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents MCPWM1_task_timer0_syn trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST    (BIT(13))
+#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_M  (SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_V << SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_S  13
+/** SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents MCPWM1_task_timer1_syn trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST    (BIT(14))
+#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_M  (SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_V << SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_S  14
+/** SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents MCPWM1_task_timer2_syn trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST    (BIT(15))
+#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_M  (SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_V << SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_S  15
+/** SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents MCPWM1_task_timer0_period_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST    (BIT(16))
+#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_M  (SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_V << SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_S  16
+/** SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents MCPWM1_task_timer1_period_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST    (BIT(17))
+#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_M  (SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_V << SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_S  17
+/** SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents MCPWM1_task_timer2_period_up trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST    (BIT(18))
+#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_M  (SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_V << SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_S  18
+/** SOC_ETM_MCPWM1_TASK_TZ0_OST_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents MCPWM1_task_tz0_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST    (BIT(19))
+#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_M  (SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_V << SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_S)
+#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_S  19
+/** SOC_ETM_MCPWM1_TASK_TZ1_OST_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents MCPWM1_task_tz1_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST    (BIT(20))
+#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_M  (SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_V << SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_S)
+#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_S  20
+/** SOC_ETM_MCPWM1_TASK_TZ2_OST_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents MCPWM1_task_tz2_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST    (BIT(21))
+#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_M  (SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_V << SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_S)
+#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_S  21
+/** SOC_ETM_MCPWM1_TASK_CLR0_OST_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents MCPWM1_task_clr0_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST    (BIT(22))
+#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_M  (SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_V << SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_S  22
+/** SOC_ETM_MCPWM1_TASK_CLR1_OST_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents MCPWM1_task_clr1_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST    (BIT(23))
+#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_M  (SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_V << SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_S  23
+/** SOC_ETM_MCPWM1_TASK_CLR2_OST_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents MCPWM1_task_clr2_ost trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST    (BIT(24))
+#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_M  (SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_V << SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_S  24
+/** SOC_ETM_MCPWM1_TASK_CAP0_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents MCPWM1_task_cap0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CAP0_ST    (BIT(25))
+#define SOC_ETM_MCPWM1_TASK_CAP0_ST_M  (SOC_ETM_MCPWM1_TASK_CAP0_ST_V << SOC_ETM_MCPWM1_TASK_CAP0_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CAP0_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CAP0_ST_S  25
+/** SOC_ETM_MCPWM1_TASK_CAP1_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents MCPWM1_task_cap1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CAP1_ST    (BIT(26))
+#define SOC_ETM_MCPWM1_TASK_CAP1_ST_M  (SOC_ETM_MCPWM1_TASK_CAP1_ST_V << SOC_ETM_MCPWM1_TASK_CAP1_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CAP1_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CAP1_ST_S  26
+/** SOC_ETM_MCPWM1_TASK_CAP2_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents MCPWM1_task_cap2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_MCPWM1_TASK_CAP2_ST    (BIT(27))
+#define SOC_ETM_MCPWM1_TASK_CAP2_ST_M  (SOC_ETM_MCPWM1_TASK_CAP2_ST_V << SOC_ETM_MCPWM1_TASK_CAP2_ST_S)
+#define SOC_ETM_MCPWM1_TASK_CAP2_ST_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CAP2_ST_S  27
+/** SOC_ETM_ADC_TASK_SAMPLE0_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents ADC_task_sample0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_TASK_SAMPLE0_ST    (BIT(28))
+#define SOC_ETM_ADC_TASK_SAMPLE0_ST_M  (SOC_ETM_ADC_TASK_SAMPLE0_ST_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_S)
+#define SOC_ETM_ADC_TASK_SAMPLE0_ST_V  0x00000001U
+#define SOC_ETM_ADC_TASK_SAMPLE0_ST_S  28
+/** SOC_ETM_ADC_TASK_SAMPLE1_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents ADC_task_sample1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_TASK_SAMPLE1_ST    (BIT(29))
+#define SOC_ETM_ADC_TASK_SAMPLE1_ST_M  (SOC_ETM_ADC_TASK_SAMPLE1_ST_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_S)
+#define SOC_ETM_ADC_TASK_SAMPLE1_ST_V  0x00000001U
+#define SOC_ETM_ADC_TASK_SAMPLE1_ST_S  29
+/** SOC_ETM_ADC_TASK_START0_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents ADC_task_start0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_TASK_START0_ST    (BIT(30))
+#define SOC_ETM_ADC_TASK_START0_ST_M  (SOC_ETM_ADC_TASK_START0_ST_V << SOC_ETM_ADC_TASK_START0_ST_S)
+#define SOC_ETM_ADC_TASK_START0_ST_V  0x00000001U
+#define SOC_ETM_ADC_TASK_START0_ST_S  30
+/** SOC_ETM_ADC_TASK_STOP0_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents ADC_task_stop0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ADC_TASK_STOP0_ST    (BIT(31))
+#define SOC_ETM_ADC_TASK_STOP0_ST_M  (SOC_ETM_ADC_TASK_STOP0_ST_V << SOC_ETM_ADC_TASK_STOP0_ST_S)
+#define SOC_ETM_ADC_TASK_STOP0_ST_V  0x00000001U
+#define SOC_ETM_ADC_TASK_STOP0_ST_S  31
+
+/** SOC_ETM_TASK_ST4_CLR_REG register
+ *  Tasks trigger status clear register
+ */
+#define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x20c)
+/** SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR    (BIT(0))
+#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_S  0
+/** SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR    (BIT(1))
+#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_S  1
+/** SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR    (BIT(2))
+#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_S  2
+/** SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_cap0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR    (BIT(3))
+#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_S  3
+/** SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_cap1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR    (BIT(4))
+#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_S  4
+/** SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear MCPWM0_task_cap2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR    (BIT(5))
+#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_S)
+#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_S  5
+/** SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR    (BIT(6))
+#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_S  6
+/** SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR    (BIT(7))
+#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_S  7
+/** SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR    (BIT(8))
+#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_S  8
+/** SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR    (BIT(9))
+#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_S  9
+/** SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR    (BIT(10))
+#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_S  10
+/** SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR    (BIT(11))
+#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_S  11
+/** SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_gen_stop trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR    (BIT(12))
+#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR_S  12
+/** SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR    (BIT(13))
+#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR_S  13
+/** SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR    (BIT(14))
+#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR_S  14
+/** SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR    (BIT(15))
+#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR_S  15
+/** SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR    (BIT(16))
+#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_S  16
+/** SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR    (BIT(17))
+#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_S  17
+/** SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR    (BIT(18))
+#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_S  18
+/** SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR    (BIT(19))
+#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR_S  19
+/** SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR    (BIT(20))
+#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR_S  20
+/** SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR    (BIT(21))
+#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR_S  21
+/** SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR    (BIT(22))
+#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR_S  22
+/** SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR    (BIT(23))
+#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR_S  23
+/** SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR    (BIT(24))
+#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR_S  24
+/** SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_cap0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR    (BIT(25))
+#define SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR_S  25
+/** SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_cap1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR    (BIT(26))
+#define SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR_S  26
+/** SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear MCPWM1_task_cap2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR    (BIT(27))
+#define SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR_M  (SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR_S)
+#define SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR_V  0x00000001U
+#define SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR_S  27
+/** SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear ADC_task_sample0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR    (BIT(28))
+#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_M  (SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S)
+#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S  28
+/** SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear ADC_task_sample1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR    (BIT(29))
+#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_M  (SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S)
+#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S  29
+/** SOC_ETM_ADC_TASK_START0_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear ADC_task_start0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_TASK_START0_ST_CLR    (BIT(30))
+#define SOC_ETM_ADC_TASK_START0_ST_CLR_M  (SOC_ETM_ADC_TASK_START0_ST_CLR_V << SOC_ETM_ADC_TASK_START0_ST_CLR_S)
+#define SOC_ETM_ADC_TASK_START0_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_TASK_START0_ST_CLR_S  30
+/** SOC_ETM_ADC_TASK_STOP0_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear ADC_task_stop0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ADC_TASK_STOP0_ST_CLR    (BIT(31))
+#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_M  (SOC_ETM_ADC_TASK_STOP0_ST_CLR_V << SOC_ETM_ADC_TASK_STOP0_ST_CLR_S)
+#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_V  0x00000001U
+#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_S  31
+
+/** SOC_ETM_TASK_ST5_REG register
+ *  Tasks trigger status register
+ */
+#define SOC_ETM_TASK_ST5_REG (DR_REG_SOC_ETM_BASE + 0x210)
+/** SOC_ETM_REGDMA_TASK_START0_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents REGDMA_task_start0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_TASK_START0_ST    (BIT(0))
+#define SOC_ETM_REGDMA_TASK_START0_ST_M  (SOC_ETM_REGDMA_TASK_START0_ST_V << SOC_ETM_REGDMA_TASK_START0_ST_S)
+#define SOC_ETM_REGDMA_TASK_START0_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_TASK_START0_ST_S  0
+/** SOC_ETM_REGDMA_TASK_START1_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents REGDMA_task_start1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_TASK_START1_ST    (BIT(1))
+#define SOC_ETM_REGDMA_TASK_START1_ST_M  (SOC_ETM_REGDMA_TASK_START1_ST_V << SOC_ETM_REGDMA_TASK_START1_ST_S)
+#define SOC_ETM_REGDMA_TASK_START1_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_TASK_START1_ST_S  1
+/** SOC_ETM_REGDMA_TASK_START2_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents REGDMA_task_start2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_TASK_START2_ST    (BIT(2))
+#define SOC_ETM_REGDMA_TASK_START2_ST_M  (SOC_ETM_REGDMA_TASK_START2_ST_V << SOC_ETM_REGDMA_TASK_START2_ST_S)
+#define SOC_ETM_REGDMA_TASK_START2_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_TASK_START2_ST_S  2
+/** SOC_ETM_REGDMA_TASK_START3_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents REGDMA_task_start3 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_REGDMA_TASK_START3_ST    (BIT(3))
+#define SOC_ETM_REGDMA_TASK_START3_ST_M  (SOC_ETM_REGDMA_TASK_START3_ST_V << SOC_ETM_REGDMA_TASK_START3_ST_S)
+#define SOC_ETM_REGDMA_TASK_START3_ST_V  0x00000001U
+#define SOC_ETM_REGDMA_TASK_START3_ST_S  3
+/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents TMPSNSR_task_start_sample trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST    (BIT(4))
+#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_M  (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S)
+#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V  0x00000001U
+#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S  4
+/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents TMPSNSR_task_stop_sample trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST    (BIT(5))
+#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_M  (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S)
+#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V  0x00000001U
+#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S  5
+/** SOC_ETM_I2S0_TASK_START_RX_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents I2S0_task_start_rx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S0_TASK_START_RX_ST    (BIT(6))
+#define SOC_ETM_I2S0_TASK_START_RX_ST_M  (SOC_ETM_I2S0_TASK_START_RX_ST_V << SOC_ETM_I2S0_TASK_START_RX_ST_S)
+#define SOC_ETM_I2S0_TASK_START_RX_ST_V  0x00000001U
+#define SOC_ETM_I2S0_TASK_START_RX_ST_S  6
+/** SOC_ETM_I2S0_TASK_START_TX_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents I2S0_task_start_tx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S0_TASK_START_TX_ST    (BIT(7))
+#define SOC_ETM_I2S0_TASK_START_TX_ST_M  (SOC_ETM_I2S0_TASK_START_TX_ST_V << SOC_ETM_I2S0_TASK_START_TX_ST_S)
+#define SOC_ETM_I2S0_TASK_START_TX_ST_V  0x00000001U
+#define SOC_ETM_I2S0_TASK_START_TX_ST_S  7
+/** SOC_ETM_I2S0_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents I2S0_task_stop_rx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S0_TASK_STOP_RX_ST    (BIT(8))
+#define SOC_ETM_I2S0_TASK_STOP_RX_ST_M  (SOC_ETM_I2S0_TASK_STOP_RX_ST_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_S)
+#define SOC_ETM_I2S0_TASK_STOP_RX_ST_V  0x00000001U
+#define SOC_ETM_I2S0_TASK_STOP_RX_ST_S  8
+/** SOC_ETM_I2S0_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents I2S0_task_stop_tx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S0_TASK_STOP_TX_ST    (BIT(9))
+#define SOC_ETM_I2S0_TASK_STOP_TX_ST_M  (SOC_ETM_I2S0_TASK_STOP_TX_ST_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_S)
+#define SOC_ETM_I2S0_TASK_STOP_TX_ST_V  0x00000001U
+#define SOC_ETM_I2S0_TASK_STOP_TX_ST_S  9
+/** SOC_ETM_I2S1_TASK_START_RX_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents I2S1_task_start_rx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S1_TASK_START_RX_ST    (BIT(10))
+#define SOC_ETM_I2S1_TASK_START_RX_ST_M  (SOC_ETM_I2S1_TASK_START_RX_ST_V << SOC_ETM_I2S1_TASK_START_RX_ST_S)
+#define SOC_ETM_I2S1_TASK_START_RX_ST_V  0x00000001U
+#define SOC_ETM_I2S1_TASK_START_RX_ST_S  10
+/** SOC_ETM_I2S1_TASK_START_TX_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents I2S1_task_start_tx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S1_TASK_START_TX_ST    (BIT(11))
+#define SOC_ETM_I2S1_TASK_START_TX_ST_M  (SOC_ETM_I2S1_TASK_START_TX_ST_V << SOC_ETM_I2S1_TASK_START_TX_ST_S)
+#define SOC_ETM_I2S1_TASK_START_TX_ST_V  0x00000001U
+#define SOC_ETM_I2S1_TASK_START_TX_ST_S  11
+/** SOC_ETM_I2S1_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents I2S1_task_stop_rx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S1_TASK_STOP_RX_ST    (BIT(12))
+#define SOC_ETM_I2S1_TASK_STOP_RX_ST_M  (SOC_ETM_I2S1_TASK_STOP_RX_ST_V << SOC_ETM_I2S1_TASK_STOP_RX_ST_S)
+#define SOC_ETM_I2S1_TASK_STOP_RX_ST_V  0x00000001U
+#define SOC_ETM_I2S1_TASK_STOP_RX_ST_S  12
+/** SOC_ETM_I2S1_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents I2S1_task_stop_tx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S1_TASK_STOP_TX_ST    (BIT(13))
+#define SOC_ETM_I2S1_TASK_STOP_TX_ST_M  (SOC_ETM_I2S1_TASK_STOP_TX_ST_V << SOC_ETM_I2S1_TASK_STOP_TX_ST_S)
+#define SOC_ETM_I2S1_TASK_STOP_TX_ST_V  0x00000001U
+#define SOC_ETM_I2S1_TASK_STOP_TX_ST_S  13
+/** SOC_ETM_I2S2_TASK_START_RX_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents I2S2_task_start_rx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S2_TASK_START_RX_ST    (BIT(14))
+#define SOC_ETM_I2S2_TASK_START_RX_ST_M  (SOC_ETM_I2S2_TASK_START_RX_ST_V << SOC_ETM_I2S2_TASK_START_RX_ST_S)
+#define SOC_ETM_I2S2_TASK_START_RX_ST_V  0x00000001U
+#define SOC_ETM_I2S2_TASK_START_RX_ST_S  14
+/** SOC_ETM_I2S2_TASK_START_TX_ST : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Represents I2S2_task_start_tx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S2_TASK_START_TX_ST    (BIT(15))
+#define SOC_ETM_I2S2_TASK_START_TX_ST_M  (SOC_ETM_I2S2_TASK_START_TX_ST_V << SOC_ETM_I2S2_TASK_START_TX_ST_S)
+#define SOC_ETM_I2S2_TASK_START_TX_ST_V  0x00000001U
+#define SOC_ETM_I2S2_TASK_START_TX_ST_S  15
+/** SOC_ETM_I2S2_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Represents I2S2_task_stop_rx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S2_TASK_STOP_RX_ST    (BIT(16))
+#define SOC_ETM_I2S2_TASK_STOP_RX_ST_M  (SOC_ETM_I2S2_TASK_STOP_RX_ST_V << SOC_ETM_I2S2_TASK_STOP_RX_ST_S)
+#define SOC_ETM_I2S2_TASK_STOP_RX_ST_V  0x00000001U
+#define SOC_ETM_I2S2_TASK_STOP_RX_ST_S  16
+/** SOC_ETM_I2S2_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Represents I2S2_task_stop_tx trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_I2S2_TASK_STOP_TX_ST    (BIT(17))
+#define SOC_ETM_I2S2_TASK_STOP_TX_ST_M  (SOC_ETM_I2S2_TASK_STOP_TX_ST_V << SOC_ETM_I2S2_TASK_STOP_TX_ST_S)
+#define SOC_ETM_I2S2_TASK_STOP_TX_ST_V  0x00000001U
+#define SOC_ETM_I2S2_TASK_STOP_TX_ST_S  17
+/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Represents ULP_task_wakeup_cpu trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST    (BIT(18))
+#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_M  (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S)
+#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V  0x00000001U
+#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S  18
+/** SOC_ETM_ULP_TASK_INT_CPU_ST : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Represents ULP_task_int_cpu trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_ULP_TASK_INT_CPU_ST    (BIT(19))
+#define SOC_ETM_ULP_TASK_INT_CPU_ST_M  (SOC_ETM_ULP_TASK_INT_CPU_ST_V << SOC_ETM_ULP_TASK_INT_CPU_ST_S)
+#define SOC_ETM_ULP_TASK_INT_CPU_ST_V  0x00000001U
+#define SOC_ETM_ULP_TASK_INT_CPU_ST_S  19
+/** SOC_ETM_RTC_TASK_START_ST : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Represents RTC_task_start trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_RTC_TASK_START_ST    (BIT(20))
+#define SOC_ETM_RTC_TASK_START_ST_M  (SOC_ETM_RTC_TASK_START_ST_V << SOC_ETM_RTC_TASK_START_ST_S)
+#define SOC_ETM_RTC_TASK_START_ST_V  0x00000001U
+#define SOC_ETM_RTC_TASK_START_ST_S  20
+/** SOC_ETM_RTC_TASK_STOP_ST : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Represents RTC_task_stop trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_RTC_TASK_STOP_ST    (BIT(21))
+#define SOC_ETM_RTC_TASK_STOP_ST_M  (SOC_ETM_RTC_TASK_STOP_ST_V << SOC_ETM_RTC_TASK_STOP_ST_S)
+#define SOC_ETM_RTC_TASK_STOP_ST_V  0x00000001U
+#define SOC_ETM_RTC_TASK_STOP_ST_S  21
+/** SOC_ETM_RTC_TASK_CLR_ST : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Represents RTC_task_clr trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_RTC_TASK_CLR_ST    (BIT(22))
+#define SOC_ETM_RTC_TASK_CLR_ST_M  (SOC_ETM_RTC_TASK_CLR_ST_V << SOC_ETM_RTC_TASK_CLR_ST_S)
+#define SOC_ETM_RTC_TASK_CLR_ST_V  0x00000001U
+#define SOC_ETM_RTC_TASK_CLR_ST_S  22
+/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Represents RTC_task_triggerflw trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST    (BIT(23))
+#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_M  (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S)
+#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V  0x00000001U
+#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S  23
+/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Represents PDMA_AHB_task_in_start_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST    (BIT(24))
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_M  (SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_S  24
+/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Represents PDMA_AHB_task_in_start_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST    (BIT(25))
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_M  (SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_S  25
+/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Represents PDMA_AHB_task_in_start_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST    (BIT(26))
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_M  (SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_S  26
+/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Represents PDMA_AHB_task_out_start_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST    (BIT(27))
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_M  (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_S)
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_S  27
+/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Represents PDMA_AHB_task_out_start_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST    (BIT(28))
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_M  (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_S)
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_S  28
+/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Represents PDMA_AHB_task_out_start_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST    (BIT(29))
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_M  (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_S)
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_S  29
+/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Represents PDMA_AXI_task_in_start_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST    (BIT(30))
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_M  (SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_S  30
+/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Represents PDMA_AXI_task_in_start_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST    (BIT(31))
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_M  (SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_S  31
+
+/** SOC_ETM_TASK_ST5_CLR_REG register
+ *  Tasks trigger status clear register
+ */
+#define SOC_ETM_TASK_ST5_CLR_REG (DR_REG_SOC_ETM_BASE + 0x214)
+/** SOC_ETM_REGDMA_TASK_START0_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear REGDMA_task_start0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_TASK_START0_ST_CLR    (BIT(0))
+#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_M  (SOC_ETM_REGDMA_TASK_START0_ST_CLR_V << SOC_ETM_REGDMA_TASK_START0_ST_CLR_S)
+#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_S  0
+/** SOC_ETM_REGDMA_TASK_START1_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear REGDMA_task_start1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_TASK_START1_ST_CLR    (BIT(1))
+#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_M  (SOC_ETM_REGDMA_TASK_START1_ST_CLR_V << SOC_ETM_REGDMA_TASK_START1_ST_CLR_S)
+#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_S  1
+/** SOC_ETM_REGDMA_TASK_START2_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear REGDMA_task_start2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_TASK_START2_ST_CLR    (BIT(2))
+#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_M  (SOC_ETM_REGDMA_TASK_START2_ST_CLR_V << SOC_ETM_REGDMA_TASK_START2_ST_CLR_S)
+#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_S  2
+/** SOC_ETM_REGDMA_TASK_START3_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear REGDMA_task_start3 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_REGDMA_TASK_START3_ST_CLR    (BIT(3))
+#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_M  (SOC_ETM_REGDMA_TASK_START3_ST_CLR_V << SOC_ETM_REGDMA_TASK_START3_ST_CLR_S)
+#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_V  0x00000001U
+#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_S  3
+/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear TMPSNSR_task_start_sample trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR    (BIT(4))
+#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_M  (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S)
+#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V  0x00000001U
+#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S  4
+/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR    (BIT(5))
+#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_M  (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S)
+#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V  0x00000001U
+#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S  5
+/** SOC_ETM_I2S0_TASK_START_RX_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear I2S0_task_start_rx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR    (BIT(6))
+#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_M  (SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S)
+#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S  6
+/** SOC_ETM_I2S0_TASK_START_TX_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear I2S0_task_start_tx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR    (BIT(7))
+#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_M  (SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S)
+#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S  7
+/** SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear I2S0_task_stop_rx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR    (BIT(8))
+#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_M  (SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S)
+#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S  8
+/** SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear I2S0_task_stop_tx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR    (BIT(9))
+#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_M  (SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S)
+#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S  9
+/** SOC_ETM_I2S1_TASK_START_RX_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear I2S1_task_start_rx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR    (BIT(10))
+#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_M  (SOC_ETM_I2S1_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S1_TASK_START_RX_ST_CLR_S)
+#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_S  10
+/** SOC_ETM_I2S1_TASK_START_TX_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear I2S1_task_start_tx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR    (BIT(11))
+#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_M  (SOC_ETM_I2S1_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S1_TASK_START_TX_ST_CLR_S)
+#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_S  11
+/** SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear I2S1_task_stop_rx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR    (BIT(12))
+#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_M  (SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_S)
+#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_S  12
+/** SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear I2S1_task_stop_tx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR    (BIT(13))
+#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_M  (SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_S)
+#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_S  13
+/** SOC_ETM_I2S2_TASK_START_RX_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear I2S2_task_start_rx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S2_TASK_START_RX_ST_CLR    (BIT(14))
+#define SOC_ETM_I2S2_TASK_START_RX_ST_CLR_M  (SOC_ETM_I2S2_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S2_TASK_START_RX_ST_CLR_S)
+#define SOC_ETM_I2S2_TASK_START_RX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S2_TASK_START_RX_ST_CLR_S  14
+/** SOC_ETM_I2S2_TASK_START_TX_ST_CLR : WT; bitpos: [15]; default: 0;
+ *  Configures whether or not to clear I2S2_task_start_tx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S2_TASK_START_TX_ST_CLR    (BIT(15))
+#define SOC_ETM_I2S2_TASK_START_TX_ST_CLR_M  (SOC_ETM_I2S2_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S2_TASK_START_TX_ST_CLR_S)
+#define SOC_ETM_I2S2_TASK_START_TX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S2_TASK_START_TX_ST_CLR_S  15
+/** SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether or not to clear I2S2_task_stop_rx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR    (BIT(16))
+#define SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR_M  (SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR_S)
+#define SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR_S  16
+/** SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether or not to clear I2S2_task_stop_tx trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR    (BIT(17))
+#define SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR_M  (SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR_S)
+#define SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR_V  0x00000001U
+#define SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR_S  17
+/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR : WT; bitpos: [18]; default: 0;
+ *  Configures whether or not to clear ULP_task_wakeup_cpu trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR    (BIT(18))
+#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_M  (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S)
+#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V  0x00000001U
+#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S  18
+/** SOC_ETM_ULP_TASK_INT_CPU_ST_CLR : WT; bitpos: [19]; default: 0;
+ *  Configures whether or not to clear ULP_task_int_cpu trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR    (BIT(19))
+#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_M  (SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S)
+#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V  0x00000001U
+#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S  19
+/** SOC_ETM_RTC_TASK_START_ST_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether or not to clear RTC_task_start trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_RTC_TASK_START_ST_CLR    (BIT(20))
+#define SOC_ETM_RTC_TASK_START_ST_CLR_M  (SOC_ETM_RTC_TASK_START_ST_CLR_V << SOC_ETM_RTC_TASK_START_ST_CLR_S)
+#define SOC_ETM_RTC_TASK_START_ST_CLR_V  0x00000001U
+#define SOC_ETM_RTC_TASK_START_ST_CLR_S  20
+/** SOC_ETM_RTC_TASK_STOP_ST_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether or not to clear RTC_task_stop trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_RTC_TASK_STOP_ST_CLR    (BIT(21))
+#define SOC_ETM_RTC_TASK_STOP_ST_CLR_M  (SOC_ETM_RTC_TASK_STOP_ST_CLR_V << SOC_ETM_RTC_TASK_STOP_ST_CLR_S)
+#define SOC_ETM_RTC_TASK_STOP_ST_CLR_V  0x00000001U
+#define SOC_ETM_RTC_TASK_STOP_ST_CLR_S  21
+/** SOC_ETM_RTC_TASK_CLR_ST_CLR : WT; bitpos: [22]; default: 0;
+ *  Configures whether or not to clear RTC_task_clr trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_RTC_TASK_CLR_ST_CLR    (BIT(22))
+#define SOC_ETM_RTC_TASK_CLR_ST_CLR_M  (SOC_ETM_RTC_TASK_CLR_ST_CLR_V << SOC_ETM_RTC_TASK_CLR_ST_CLR_S)
+#define SOC_ETM_RTC_TASK_CLR_ST_CLR_V  0x00000001U
+#define SOC_ETM_RTC_TASK_CLR_ST_CLR_S  22
+/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to clear RTC_task_triggerflw trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR    (BIT(23))
+#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_M  (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S)
+#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V  0x00000001U
+#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S  23
+/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [24]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR    (BIT(24))
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_S  24
+/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [25]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR    (BIT(25))
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_S  25
+/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR : WT; bitpos: [26]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR    (BIT(26))
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_S  26
+/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [27]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR    (BIT(27))
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_M  (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_S  27
+/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [28]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR    (BIT(28))
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_M  (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_S  28
+/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR    (BIT(29))
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_M  (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_S  29
+/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR    (BIT(30))
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_S  30
+/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR    (BIT(31))
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_S  31
+
+/** SOC_ETM_TASK_ST6_REG register
+ *  Tasks trigger status register
+ */
+#define SOC_ETM_TASK_ST6_REG (DR_REG_SOC_ETM_BASE + 0x218)
+/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Represents PDMA_AXI_task_in_start_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST    (BIT(0))
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_M  (SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_S  0
+/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Represents PDMA_AXI_task_out_start_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST    (BIT(1))
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_M  (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_S)
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_S  1
+/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Represents PDMA_AXI_task_out_start_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST    (BIT(2))
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_M  (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_S)
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_S  2
+/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Represents PDMA_AXI_task_out_start_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST    (BIT(3))
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_M  (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_S)
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_S  3
+/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Represents PMU_task_sleep_req trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST    (BIT(4))
+#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_M  (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S)
+#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V  0x00000001U
+#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S  4
+/** SOC_ETM_DMA2D_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Represents DMA2D_task_in_start_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST    (BIT(5))
+#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_M  (SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_V << SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_S)
+#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_S  5
+/** SOC_ETM_DMA2D_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Represents DMA2D_task_in_start_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST    (BIT(6))
+#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_M  (SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_V << SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_S)
+#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_S  6
+/** SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Represents DMA2D_task_in_dscr_ready_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST    (BIT(7))
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_M  (SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_V << SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_S)
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_S  7
+/** SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Represents DMA2D_task_in_dscr_ready_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST    (BIT(8))
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_M  (SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_V << SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_S)
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_S  8
+/** SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Represents DMA2D_task_out_start_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST    (BIT(9))
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_M  (SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_V << SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_S)
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_S  9
+/** SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Represents DMA2D_task_out_start_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST    (BIT(10))
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_M  (SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_V << SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_S)
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_S  10
+/** SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Represents DMA2D_task_out_start_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST    (BIT(11))
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_M  (SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_V << SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_S)
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_S  11
+/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Represents DMA2D_task_out_dscr_ready_ch0 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST    (BIT(12))
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_M  (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_S)
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_S  12
+/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Represents DMA2D_task_out_dscr_ready_ch1 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST    (BIT(13))
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_M  (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_S)
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_S  13
+/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Represents DMA2D_task_out_dscr_ready_ch2 trigger status.
+ *  0: Not triggered
+ *  1: Triggered
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST    (BIT(14))
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_M  (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_S)
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_S  14
+
+/** SOC_ETM_TASK_ST6_CLR_REG register
+ *  Tasks trigger status clear register
+ */
+#define SOC_ETM_TASK_ST6_CLR_REG (DR_REG_SOC_ETM_BASE + 0x21c)
+/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR    (BIT(0))
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_S  0
+/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR    (BIT(1))
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_M  (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_S  1
+/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [2]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR    (BIT(2))
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_M  (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_S  2
+/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR    (BIT(3))
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_M  (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_S)
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_S  3
+/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR : WT; bitpos: [4]; default: 0;
+ *  Configures whether or not to clear PMU_task_sleep_req trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR    (BIT(4))
+#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_M  (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S)
+#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V  0x00000001U
+#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S  4
+/** SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [5]; default: 0;
+ *  Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR    (BIT(5))
+#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR_M  (SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR_V << SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR_S)
+#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR_S  5
+/** SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [6]; default: 0;
+ *  Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR    (BIT(6))
+#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR_M  (SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR_S)
+#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR_S  6
+/** SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR : WT; bitpos: [7]; default: 0;
+ *  Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR    (BIT(7))
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_M  (SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_V << SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_S)
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_S  7
+/** SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR : WT; bitpos: [8]; default: 0;
+ *  Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR    (BIT(8))
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_M  (SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_V << SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_S)
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_S  8
+/** SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [9]; default: 0;
+ *  Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR    (BIT(9))
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR_M  (SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR_S)
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR_S  9
+/** SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [10]; default: 0;
+ *  Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR    (BIT(10))
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR_M  (SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR_S)
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR_S  10
+/** SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR    (BIT(11))
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR_M  (SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR_S)
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR_S  11
+/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR    (BIT(12))
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_M  (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_S)
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_S  12
+/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR : WT; bitpos: [13]; default: 0;
+ *  Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR    (BIT(13))
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_M  (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_S)
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_S  13
+/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR : WT; bitpos: [14]; default: 0;
+ *  Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger status.
+ *  0: Invalid, No effect
+ *  1: Clear
+ */
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR    (BIT(14))
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_M  (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_S)
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_V  0x00000001U
+#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_S  14
+
+/** SOC_ETM_CLK_EN_REG register
+ *  ETM clock enable register
+ */
+#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x220)
+/** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to open register clock gate.
+ *  0: Open the clock gate only when application writes registers
+ *  1: Force open the clock gate for register
+ */
+#define SOC_ETM_CLK_EN    (BIT(0))
+#define SOC_ETM_CLK_EN_M  (SOC_ETM_CLK_EN_V << SOC_ETM_CLK_EN_S)
+#define SOC_ETM_CLK_EN_V  0x00000001U
+#define SOC_ETM_CLK_EN_S  0
+
+/** SOC_ETM_DATE_REG register
+ *  ETM date register
+ */
+#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x224)
+/** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 36712497;
+ *  Configures the version.
+ */
+#define SOC_ETM_DATE    0x0FFFFFFFU
+#define SOC_ETM_DATE_M  (SOC_ETM_DATE_V << SOC_ETM_DATE_S)
+#define SOC_ETM_DATE_V  0x0FFFFFFFU
+#define SOC_ETM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/soc_etm_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/soc_etm_struct.h
new file mode 100644
index 0000000000..63d820d1c5
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/soc_etm_struct.h
@@ -0,0 +1,5134 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13428
+
+/** Group: Status register */
+/** Type of ch_ena_ad0 register
+ *  Channel enable status register
+ */
+typedef union {
+    struct {
+        /** ch_ena0 : R/WTC/WTS; bitpos: [0]; default: 0;
+         *  Represents ch0 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena0: 1;
+        /** ch_ena1 : R/WTC/WTS; bitpos: [1]; default: 0;
+         *  Represents ch1 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena1: 1;
+        /** ch_ena2 : R/WTC/WTS; bitpos: [2]; default: 0;
+         *  Represents ch2 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena2: 1;
+        /** ch_ena3 : R/WTC/WTS; bitpos: [3]; default: 0;
+         *  Represents ch3 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena3: 1;
+        /** ch_ena4 : R/WTC/WTS; bitpos: [4]; default: 0;
+         *  Represents ch4 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena4: 1;
+        /** ch_ena5 : R/WTC/WTS; bitpos: [5]; default: 0;
+         *  Represents ch5 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena5: 1;
+        /** ch_ena6 : R/WTC/WTS; bitpos: [6]; default: 0;
+         *  Represents ch6 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena6: 1;
+        /** ch_ena7 : R/WTC/WTS; bitpos: [7]; default: 0;
+         *  Represents ch7 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena7: 1;
+        /** ch_ena8 : R/WTC/WTS; bitpos: [8]; default: 0;
+         *  Represents ch8 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena8: 1;
+        /** ch_ena9 : R/WTC/WTS; bitpos: [9]; default: 0;
+         *  Represents ch9 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena9: 1;
+        /** ch_ena10 : R/WTC/WTS; bitpos: [10]; default: 0;
+         *  Represents ch10 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena10: 1;
+        /** ch_ena11 : R/WTC/WTS; bitpos: [11]; default: 0;
+         *  Represents ch11 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena11: 1;
+        /** ch_ena12 : R/WTC/WTS; bitpos: [12]; default: 0;
+         *  Represents ch12 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena12: 1;
+        /** ch_ena13 : R/WTC/WTS; bitpos: [13]; default: 0;
+         *  Represents ch13 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena13: 1;
+        /** ch_ena14 : R/WTC/WTS; bitpos: [14]; default: 0;
+         *  Represents ch14 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena14: 1;
+        /** ch_ena15 : R/WTC/WTS; bitpos: [15]; default: 0;
+         *  Represents ch15 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena15: 1;
+        /** ch_ena16 : R/WTC/WTS; bitpos: [16]; default: 0;
+         *  Represents ch16 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena16: 1;
+        /** ch_ena17 : R/WTC/WTS; bitpos: [17]; default: 0;
+         *  Represents ch17 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena17: 1;
+        /** ch_ena18 : R/WTC/WTS; bitpos: [18]; default: 0;
+         *  Represents ch18 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena18: 1;
+        /** ch_ena19 : R/WTC/WTS; bitpos: [19]; default: 0;
+         *  Represents ch19 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena19: 1;
+        /** ch_ena20 : R/WTC/WTS; bitpos: [20]; default: 0;
+         *  Represents ch20 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena20: 1;
+        /** ch_ena21 : R/WTC/WTS; bitpos: [21]; default: 0;
+         *  Represents ch21 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena21: 1;
+        /** ch_ena22 : R/WTC/WTS; bitpos: [22]; default: 0;
+         *  Represents ch22 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena22: 1;
+        /** ch_ena23 : R/WTC/WTS; bitpos: [23]; default: 0;
+         *  Represents ch23 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena23: 1;
+        /** ch_ena24 : R/WTC/WTS; bitpos: [24]; default: 0;
+         *  Represents ch24 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena24: 1;
+        /** ch_ena25 : R/WTC/WTS; bitpos: [25]; default: 0;
+         *  Represents ch25 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena25: 1;
+        /** ch_ena26 : R/WTC/WTS; bitpos: [26]; default: 0;
+         *  Represents ch26 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena26: 1;
+        /** ch_ena27 : R/WTC/WTS; bitpos: [27]; default: 0;
+         *  Represents ch27 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena27: 1;
+        /** ch_ena28 : R/WTC/WTS; bitpos: [28]; default: 0;
+         *  Represents ch28 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena28: 1;
+        /** ch_ena29 : R/WTC/WTS; bitpos: [29]; default: 0;
+         *  Represents ch29 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena29: 1;
+        /** ch_ena30 : R/WTC/WTS; bitpos: [30]; default: 0;
+         *  Represents ch30 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena30: 1;
+        /** ch_ena31 : R/WTC/WTS; bitpos: [31]; default: 0;
+         *  Represents ch31 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena31: 1;
+    };
+    uint32_t val;
+} soc_etm_ch_ena_ad0_reg_t;
+
+/** Type of ch_ena_ad1 register
+ *  Channel enable status register
+ */
+typedef union {
+    struct {
+        /** ch_ena32 : R/WTC/WTS; bitpos: [0]; default: 0;
+         *  Represents ch32 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena32: 1;
+        /** ch_ena33 : R/WTC/WTS; bitpos: [1]; default: 0;
+         *  Represents ch33 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena33: 1;
+        /** ch_ena34 : R/WTC/WTS; bitpos: [2]; default: 0;
+         *  Represents ch34 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena34: 1;
+        /** ch_ena35 : R/WTC/WTS; bitpos: [3]; default: 0;
+         *  Represents ch35 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena35: 1;
+        /** ch_ena36 : R/WTC/WTS; bitpos: [4]; default: 0;
+         *  Represents ch36 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena36: 1;
+        /** ch_ena37 : R/WTC/WTS; bitpos: [5]; default: 0;
+         *  Represents ch37 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena37: 1;
+        /** ch_ena38 : R/WTC/WTS; bitpos: [6]; default: 0;
+         *  Represents ch38 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena38: 1;
+        /** ch_ena39 : R/WTC/WTS; bitpos: [7]; default: 0;
+         *  Represents ch39 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena39: 1;
+        /** ch_ena40 : R/WTC/WTS; bitpos: [8]; default: 0;
+         *  Represents ch40 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena40: 1;
+        /** ch_ena41 : R/WTC/WTS; bitpos: [9]; default: 0;
+         *  Represents ch41 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena41: 1;
+        /** ch_ena42 : R/WTC/WTS; bitpos: [10]; default: 0;
+         *  Represents ch42 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena42: 1;
+        /** ch_ena43 : R/WTC/WTS; bitpos: [11]; default: 0;
+         *  Represents ch43 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena43: 1;
+        /** ch_ena44 : R/WTC/WTS; bitpos: [12]; default: 0;
+         *  Represents ch44 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena44: 1;
+        /** ch_ena45 : R/WTC/WTS; bitpos: [13]; default: 0;
+         *  Represents ch45 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena45: 1;
+        /** ch_ena46 : R/WTC/WTS; bitpos: [14]; default: 0;
+         *  Represents ch46 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena46: 1;
+        /** ch_ena47 : R/WTC/WTS; bitpos: [15]; default: 0;
+         *  Represents ch47 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena47: 1;
+        /** ch_ena48 : R/WTC/WTS; bitpos: [16]; default: 0;
+         *  Represents ch48 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena48: 1;
+        /** ch_ena49 : R/WTC/WTS; bitpos: [17]; default: 0;
+         *  Represents ch49 enable status.\\0: Disable\\1: Enable
+         */
+        uint32_t ch_ena49: 1;
+        uint32_t reserved_18: 14;
+    };
+    uint32_t val;
+} soc_etm_ch_ena_ad1_reg_t;
+
+/** Type of evt_st0 register
+ *  Events trigger status register
+ */
+typedef union {
+    struct {
+        /** gpio_evt_ch0_rise_edge_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch0_rise_edge_st: 1;
+        /** gpio_evt_ch1_rise_edge_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch1_rise_edge_st: 1;
+        /** gpio_evt_ch2_rise_edge_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch2_rise_edge_st: 1;
+        /** gpio_evt_ch3_rise_edge_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch3_rise_edge_st: 1;
+        /** gpio_evt_ch4_rise_edge_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch4_rise_edge_st: 1;
+        /** gpio_evt_ch5_rise_edge_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch5_rise_edge_st: 1;
+        /** gpio_evt_ch6_rise_edge_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch6_rise_edge_st: 1;
+        /** gpio_evt_ch7_rise_edge_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch7_rise_edge_st: 1;
+        /** gpio_evt_ch0_fall_edge_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch0_fall_edge_st: 1;
+        /** gpio_evt_ch1_fall_edge_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch1_fall_edge_st: 1;
+        /** gpio_evt_ch2_fall_edge_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch2_fall_edge_st: 1;
+        /** gpio_evt_ch3_fall_edge_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch3_fall_edge_st: 1;
+        /** gpio_evt_ch4_fall_edge_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch4_fall_edge_st: 1;
+        /** gpio_evt_ch5_fall_edge_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch5_fall_edge_st: 1;
+        /** gpio_evt_ch6_fall_edge_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch6_fall_edge_st: 1;
+        /** gpio_evt_ch7_fall_edge_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch7_fall_edge_st: 1;
+        /** gpio_evt_ch0_any_edge_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch0_any_edge_st: 1;
+        /** gpio_evt_ch1_any_edge_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch1_any_edge_st: 1;
+        /** gpio_evt_ch2_any_edge_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch2_any_edge_st: 1;
+        /** gpio_evt_ch3_any_edge_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch3_any_edge_st: 1;
+        /** gpio_evt_ch4_any_edge_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch4_any_edge_st: 1;
+        /** gpio_evt_ch5_any_edge_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch5_any_edge_st: 1;
+        /** gpio_evt_ch6_any_edge_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch6_any_edge_st: 1;
+        /** gpio_evt_ch7_any_edge_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_ch7_any_edge_st: 1;
+        /** gpio_evt_zero_det_pos0_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_zero_det_pos0_st: 1;
+        /** gpio_evt_zero_det_neg0_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_zero_det_neg0_st: 1;
+        /** gpio_evt_zero_det_pos1_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_zero_det_pos1_st: 1;
+        /** gpio_evt_zero_det_neg1_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_evt_zero_det_neg1_st: 1;
+        /** ledc_evt_duty_chng_end_ch0_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_evt_duty_chng_end_ch0_st: 1;
+        /** ledc_evt_duty_chng_end_ch1_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_evt_duty_chng_end_ch1_st: 1;
+        /** ledc_evt_duty_chng_end_ch2_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_evt_duty_chng_end_ch2_st: 1;
+        /** ledc_evt_duty_chng_end_ch3_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_evt_duty_chng_end_ch3_st: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st0_reg_t;
+
+/** Type of evt_st1 register
+ *  Events trigger status register
+ */
+typedef union {
+    struct {
+        /** ledc_evt_duty_chng_end_ch4_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_evt_duty_chng_end_ch4_st: 1;
+        /** ledc_evt_duty_chng_end_ch5_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_evt_duty_chng_end_ch5_st: 1;
+        /** ledc_evt_duty_chng_end_ch6_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_evt_duty_chng_end_ch6_st: 1;
+        /** ledc_evt_duty_chng_end_ch7_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_evt_duty_chng_end_ch7_st: 1;
+        /** ledc_evt_ovf_cnt_pls_ch0_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch0_st: 1;
+        /** ledc_evt_ovf_cnt_pls_ch1_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch1_st: 1;
+        /** ledc_evt_ovf_cnt_pls_ch2_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch2_st: 1;
+        /** ledc_evt_ovf_cnt_pls_ch3_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch3_st: 1;
+        /** ledc_evt_ovf_cnt_pls_ch4_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch4_st: 1;
+        /** ledc_evt_ovf_cnt_pls_ch5_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch5_st: 1;
+        /** ledc_evt_ovf_cnt_pls_ch6_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch6_st: 1;
+        /** ledc_evt_ovf_cnt_pls_ch7_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch7_st: 1;
+        /** ledc_evt_time_ovf_timer0_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_time_ovf_timer0_st: 1;
+        /** ledc_evt_time_ovf_timer1_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_time_ovf_timer1_st: 1;
+        /** ledc_evt_time_ovf_timer2_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_time_ovf_timer2_st: 1;
+        /** ledc_evt_time_ovf_timer3_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_time_ovf_timer3_st: 1;
+        /** ledc_evt_timer0_cmp_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_timer0_cmp_st: 1;
+        /** ledc_evt_timer1_cmp_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_timer1_cmp_st: 1;
+        /** ledc_evt_timer2_cmp_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_timer2_cmp_st: 1;
+        /** ledc_evt_timer3_cmp_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_evt_timer3_cmp_st: 1;
+        /** tg0_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg0_evt_cnt_cmp_timer0_st: 1;
+        /** tg0_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg0_evt_cnt_cmp_timer1_st: 1;
+        /** tg1_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg1_evt_cnt_cmp_timer0_st: 1;
+        /** tg1_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg1_evt_cnt_cmp_timer1_st: 1;
+        /** systimer_evt_cnt_cmp0_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t systimer_evt_cnt_cmp0_st: 1;
+        /** systimer_evt_cnt_cmp1_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t systimer_evt_cnt_cmp1_st: 1;
+        /** systimer_evt_cnt_cmp2_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t systimer_evt_cnt_cmp2_st: 1;
+        /** mcpwm0_evt_timer0_stop_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_timer0_stop_st: 1;
+        /** mcpwm0_evt_timer1_stop_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_timer1_stop_st: 1;
+        /** mcpwm0_evt_timer2_stop_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_timer2_stop_st: 1;
+        /** mcpwm0_evt_timer0_tez_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_timer0_tez_st: 1;
+        /** mcpwm0_evt_timer1_tez_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_timer1_tez_st: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st1_reg_t;
+
+/** Type of evt_st2 register
+ *  Events trigger status register
+ */
+typedef union {
+    struct {
+        /** mcpwm0_evt_timer2_tez_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_timer2_tez_st: 1;
+        /** mcpwm0_evt_timer0_tep_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_timer0_tep_st: 1;
+        /** mcpwm0_evt_timer1_tep_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_timer1_tep_st: 1;
+        /** mcpwm0_evt_timer2_tep_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_timer2_tep_st: 1;
+        /** mcpwm0_evt_op0_tea_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op0_tea_st: 1;
+        /** mcpwm0_evt_op1_tea_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op1_tea_st: 1;
+        /** mcpwm0_evt_op2_tea_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op2_tea_st: 1;
+        /** mcpwm0_evt_op0_teb_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op0_teb_st: 1;
+        /** mcpwm0_evt_op1_teb_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op1_teb_st: 1;
+        /** mcpwm0_evt_op2_teb_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op2_teb_st: 1;
+        /** mcpwm0_evt_f0_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_f0_st: 1;
+        /** mcpwm0_evt_f1_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_f1_st: 1;
+        /** mcpwm0_evt_f2_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_f2_st: 1;
+        /** mcpwm0_evt_f0_clr_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_f0_clr_st: 1;
+        /** mcpwm0_evt_f1_clr_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_f1_clr_st: 1;
+        /** mcpwm0_evt_f2_clr_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_f2_clr_st: 1;
+        /** mcpwm0_evt_tz0_cbc_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_tz0_cbc_st: 1;
+        /** mcpwm0_evt_tz1_cbc_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_tz1_cbc_st: 1;
+        /** mcpwm0_evt_tz2_cbc_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_tz2_cbc_st: 1;
+        /** mcpwm0_evt_tz0_ost_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_tz0_ost_st: 1;
+        /** mcpwm0_evt_tz1_ost_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_tz1_ost_st: 1;
+        /** mcpwm0_evt_tz2_ost_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_tz2_ost_st: 1;
+        /** mcpwm0_evt_cap0_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_cap0_st: 1;
+        /** mcpwm0_evt_cap1_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_cap1_st: 1;
+        /** mcpwm0_evt_cap2_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_cap2_st: 1;
+        /** mcpwm0_evt_op0_tee1_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op0_tee1_st: 1;
+        /** mcpwm0_evt_op1_tee1_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op1_tee1_st: 1;
+        /** mcpwm0_evt_op2_tee1_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op2_tee1_st: 1;
+        /** mcpwm0_evt_op0_tee2_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op0_tee2_st: 1;
+        /** mcpwm0_evt_op1_tee2_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op1_tee2_st: 1;
+        /** mcpwm0_evt_op2_tee2_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_evt_op2_tee2_st: 1;
+        /** mcpwm1_evt_timer0_stop_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents MCPWM1_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_timer0_stop_st: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st2_reg_t;
+
+/** Type of evt_st3 register
+ *  Events trigger status register
+ */
+typedef union {
+    struct {
+        /** mcpwm1_evt_timer1_stop_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents MCPWM1_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_timer1_stop_st: 1;
+        /** mcpwm1_evt_timer2_stop_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents MCPWM1_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_timer2_stop_st: 1;
+        /** mcpwm1_evt_timer0_tez_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents MCPWM1_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_timer0_tez_st: 1;
+        /** mcpwm1_evt_timer1_tez_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents MCPWM1_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_timer1_tez_st: 1;
+        /** mcpwm1_evt_timer2_tez_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents MCPWM1_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_timer2_tez_st: 1;
+        /** mcpwm1_evt_timer0_tep_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents MCPWM1_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_timer0_tep_st: 1;
+        /** mcpwm1_evt_timer1_tep_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents MCPWM1_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_timer1_tep_st: 1;
+        /** mcpwm1_evt_timer2_tep_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents MCPWM1_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_timer2_tep_st: 1;
+        /** mcpwm1_evt_op0_tea_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents MCPWM1_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op0_tea_st: 1;
+        /** mcpwm1_evt_op1_tea_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents MCPWM1_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op1_tea_st: 1;
+        /** mcpwm1_evt_op2_tea_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents MCPWM1_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op2_tea_st: 1;
+        /** mcpwm1_evt_op0_teb_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents MCPWM1_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op0_teb_st: 1;
+        /** mcpwm1_evt_op1_teb_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents MCPWM1_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op1_teb_st: 1;
+        /** mcpwm1_evt_op2_teb_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents MCPWM1_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op2_teb_st: 1;
+        /** mcpwm1_evt_f0_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents MCPWM1_evt_f0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_f0_st: 1;
+        /** mcpwm1_evt_f1_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents MCPWM1_evt_f1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_f1_st: 1;
+        /** mcpwm1_evt_f2_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents MCPWM1_evt_f2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_f2_st: 1;
+        /** mcpwm1_evt_f0_clr_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents MCPWM1_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_f0_clr_st: 1;
+        /** mcpwm1_evt_f1_clr_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents MCPWM1_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_f1_clr_st: 1;
+        /** mcpwm1_evt_f2_clr_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents MCPWM1_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_f2_clr_st: 1;
+        /** mcpwm1_evt_tz0_cbc_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents MCPWM1_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_tz0_cbc_st: 1;
+        /** mcpwm1_evt_tz1_cbc_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents MCPWM1_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_tz1_cbc_st: 1;
+        /** mcpwm1_evt_tz2_cbc_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents MCPWM1_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_tz2_cbc_st: 1;
+        /** mcpwm1_evt_tz0_ost_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents MCPWM1_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_tz0_ost_st: 1;
+        /** mcpwm1_evt_tz1_ost_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents MCPWM1_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_tz1_ost_st: 1;
+        /** mcpwm1_evt_tz2_ost_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents MCPWM1_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_tz2_ost_st: 1;
+        /** mcpwm1_evt_cap0_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents MCPWM1_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_cap0_st: 1;
+        /** mcpwm1_evt_cap1_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents MCPWM1_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_cap1_st: 1;
+        /** mcpwm1_evt_cap2_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents MCPWM1_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_cap2_st: 1;
+        /** mcpwm1_evt_op0_tee1_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents MCPWM1_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op0_tee1_st: 1;
+        /** mcpwm1_evt_op1_tee1_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents MCPWM1_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op1_tee1_st: 1;
+        /** mcpwm1_evt_op2_tee1_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents MCPWM1_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op2_tee1_st: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st3_reg_t;
+
+/** Type of evt_st4 register
+ *  Events trigger status register
+ */
+typedef union {
+    struct {
+        /** mcpwm1_evt_op0_tee2_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents MCPWM1_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op0_tee2_st: 1;
+        /** mcpwm1_evt_op1_tee2_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents MCPWM1_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op1_tee2_st: 1;
+        /** mcpwm1_evt_op2_tee2_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents MCPWM1_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_evt_op2_tee2_st: 1;
+        /** adc_evt_conv_cmplt0_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_evt_conv_cmplt0_st: 1;
+        /** adc_evt_eq_above_thresh0_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_evt_eq_above_thresh0_st: 1;
+        /** adc_evt_eq_above_thresh1_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_evt_eq_above_thresh1_st: 1;
+        /** adc_evt_eq_below_thresh0_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_evt_eq_below_thresh0_st: 1;
+        /** adc_evt_eq_below_thresh1_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_evt_eq_below_thresh1_st: 1;
+        /** adc_evt_result_done0_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_evt_result_done0_st: 1;
+        /** adc_evt_stopped0_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_evt_stopped0_st: 1;
+        /** adc_evt_started0_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_evt_started0_st: 1;
+        /** regdma_evt_done0_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_evt_done0_st: 1;
+        /** regdma_evt_done1_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_evt_done1_st: 1;
+        /** regdma_evt_done2_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_evt_done2_st: 1;
+        /** regdma_evt_done3_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_evt_done3_st: 1;
+        /** regdma_evt_err0_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_evt_err0_st: 1;
+        /** regdma_evt_err1_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_evt_err1_st: 1;
+        /** regdma_evt_err2_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_evt_err2_st: 1;
+        /** regdma_evt_err3_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_evt_err3_st: 1;
+        /** tmpsnsr_evt_over_limit_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tmpsnsr_evt_over_limit_st: 1;
+        /** i2s0_evt_rx_done_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s0_evt_rx_done_st: 1;
+        /** i2s0_evt_tx_done_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s0_evt_tx_done_st: 1;
+        /** i2s0_evt_x_words_received_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s0_evt_x_words_received_st: 1;
+        /** i2s0_evt_x_words_sent_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s0_evt_x_words_sent_st: 1;
+        /** i2s1_evt_rx_done_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s1_evt_rx_done_st: 1;
+        /** i2s1_evt_tx_done_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s1_evt_tx_done_st: 1;
+        /** i2s1_evt_x_words_received_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents I2S1_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s1_evt_x_words_received_st: 1;
+        /** i2s1_evt_x_words_sent_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s1_evt_x_words_sent_st: 1;
+        /** i2s2_evt_rx_done_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents I2S2_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s2_evt_rx_done_st: 1;
+        /** i2s2_evt_tx_done_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents I2S2_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s2_evt_tx_done_st: 1;
+        /** i2s2_evt_x_words_received_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents I2S2_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s2_evt_x_words_received_st: 1;
+        /** i2s2_evt_x_words_sent_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents I2S2_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s2_evt_x_words_sent_st: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st4_reg_t;
+
+/** Type of evt_st5 register
+ *  Events trigger status register
+ */
+typedef union {
+    struct {
+        /** ulp_evt_err_intr_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ulp_evt_err_intr_st: 1;
+        /** ulp_evt_halt_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ulp_evt_halt_st: 1;
+        /** ulp_evt_start_intr_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ulp_evt_start_intr_st: 1;
+        /** rtc_evt_tick_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t rtc_evt_tick_st: 1;
+        /** rtc_evt_ovf_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t rtc_evt_ovf_st: 1;
+        /** rtc_evt_cmp_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t rtc_evt_cmp_st: 1;
+        /** pdma_ahb_evt_in_done_ch0_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_ahb_evt_in_done_ch0_st: 1;
+        /** pdma_ahb_evt_in_done_ch1_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_ahb_evt_in_done_ch1_st: 1;
+        /** pdma_ahb_evt_in_done_ch2_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_ahb_evt_in_done_ch2_st: 1;
+        /** pdma_ahb_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_in_suc_eof_ch0_st: 1;
+        /** pdma_ahb_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_in_suc_eof_ch1_st: 1;
+        /** pdma_ahb_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_in_suc_eof_ch2_st: 1;
+        /** pdma_ahb_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_in_fifo_empty_ch0_st: 1;
+        /** pdma_ahb_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_in_fifo_empty_ch1_st: 1;
+        /** pdma_ahb_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_in_fifo_empty_ch2_st: 1;
+        /** pdma_ahb_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_in_fifo_full_ch0_st: 1;
+        /** pdma_ahb_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_in_fifo_full_ch1_st: 1;
+        /** pdma_ahb_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_in_fifo_full_ch2_st: 1;
+        /** pdma_ahb_evt_out_done_ch0_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_ahb_evt_out_done_ch0_st: 1;
+        /** pdma_ahb_evt_out_done_ch1_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_ahb_evt_out_done_ch1_st: 1;
+        /** pdma_ahb_evt_out_done_ch2_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_ahb_evt_out_done_ch2_st: 1;
+        /** pdma_ahb_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_ahb_evt_out_eof_ch0_st: 1;
+        /** pdma_ahb_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_ahb_evt_out_eof_ch1_st: 1;
+        /** pdma_ahb_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_ahb_evt_out_eof_ch2_st: 1;
+        /** pdma_ahb_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_out_total_eof_ch0_st: 1;
+        /** pdma_ahb_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_out_total_eof_ch1_st: 1;
+        /** pdma_ahb_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_out_total_eof_ch2_st: 1;
+        /** pdma_ahb_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_out_fifo_empty_ch0_st: 1;
+        /** pdma_ahb_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_out_fifo_empty_ch1_st: 1;
+        /** pdma_ahb_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_out_fifo_empty_ch2_st: 1;
+        /** pdma_ahb_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_out_fifo_full_ch0_st: 1;
+        /** pdma_ahb_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_out_fifo_full_ch1_st: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st5_reg_t;
+
+/** Type of evt_st6 register
+ *  Events trigger status register
+ */
+typedef union {
+    struct {
+        /** pdma_ahb_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_evt_out_fifo_full_ch2_st: 1;
+        /** pdma_axi_evt_in_done_ch0_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_axi_evt_in_done_ch0_st: 1;
+        /** pdma_axi_evt_in_done_ch1_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_axi_evt_in_done_ch1_st: 1;
+        /** pdma_axi_evt_in_done_ch2_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_axi_evt_in_done_ch2_st: 1;
+        /** pdma_axi_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_in_suc_eof_ch0_st: 1;
+        /** pdma_axi_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_in_suc_eof_ch1_st: 1;
+        /** pdma_axi_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_in_suc_eof_ch2_st: 1;
+        /** pdma_axi_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_in_fifo_empty_ch0_st: 1;
+        /** pdma_axi_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_in_fifo_empty_ch1_st: 1;
+        /** pdma_axi_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_in_fifo_empty_ch2_st: 1;
+        /** pdma_axi_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_in_fifo_full_ch0_st: 1;
+        /** pdma_axi_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_in_fifo_full_ch1_st: 1;
+        /** pdma_axi_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_in_fifo_full_ch2_st: 1;
+        /** pdma_axi_evt_out_done_ch0_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_axi_evt_out_done_ch0_st: 1;
+        /** pdma_axi_evt_out_done_ch1_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_axi_evt_out_done_ch1_st: 1;
+        /** pdma_axi_evt_out_done_ch2_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_axi_evt_out_done_ch2_st: 1;
+        /** pdma_axi_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_axi_evt_out_eof_ch0_st: 1;
+        /** pdma_axi_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_axi_evt_out_eof_ch1_st: 1;
+        /** pdma_axi_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pdma_axi_evt_out_eof_ch2_st: 1;
+        /** pdma_axi_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_out_total_eof_ch0_st: 1;
+        /** pdma_axi_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_out_total_eof_ch1_st: 1;
+        /** pdma_axi_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_out_total_eof_ch2_st: 1;
+        /** pdma_axi_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_out_fifo_empty_ch0_st: 1;
+        /** pdma_axi_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_out_fifo_empty_ch1_st: 1;
+        /** pdma_axi_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_out_fifo_empty_ch2_st: 1;
+        /** pdma_axi_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_out_fifo_full_ch0_st: 1;
+        /** pdma_axi_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_out_fifo_full_ch1_st: 1;
+        /** pdma_axi_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_evt_out_fifo_full_ch2_st: 1;
+        /** pmu_evt_sleep_weekup_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pmu_evt_sleep_weekup_st: 1;
+        /** dma2d_evt_in_done_ch0_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents DMA2D_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_evt_in_done_ch0_st: 1;
+        /** dma2d_evt_in_done_ch1_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents DMA2D_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_evt_in_done_ch1_st: 1;
+        /** dma2d_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_evt_in_suc_eof_ch0_st: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st6_reg_t;
+
+/** Type of evt_st7 register
+ *  Events trigger status register
+ */
+typedef union {
+    struct {
+        /** dma2d_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_evt_in_suc_eof_ch1_st: 1;
+        /** dma2d_evt_out_done_ch0_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents DMA2D_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_evt_out_done_ch0_st: 1;
+        /** dma2d_evt_out_done_ch1_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents DMA2D_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_evt_out_done_ch1_st: 1;
+        /** dma2d_evt_out_done_ch2_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents DMA2D_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_evt_out_done_ch2_st: 1;
+        /** dma2d_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents DMA2D_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_evt_out_eof_ch0_st: 1;
+        /** dma2d_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents DMA2D_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_evt_out_eof_ch1_st: 1;
+        /** dma2d_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents DMA2D_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_evt_out_eof_ch2_st: 1;
+        /** dma2d_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t dma2d_evt_out_total_eof_ch0_st: 1;
+        /** dma2d_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t dma2d_evt_out_total_eof_ch1_st: 1;
+        /** dma2d_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t dma2d_evt_out_total_eof_ch2_st: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} soc_etm_evt_st7_reg_t;
+
+/** Type of task_st0 register
+ *  Tasks trigger status register
+ */
+typedef union {
+    struct {
+        /** gpio_task_ch0_set_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch0_set_st: 1;
+        /** gpio_task_ch1_set_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch1_set_st: 1;
+        /** gpio_task_ch2_set_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch2_set_st: 1;
+        /** gpio_task_ch3_set_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch3_set_st: 1;
+        /** gpio_task_ch4_set_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch4_set_st: 1;
+        /** gpio_task_ch5_set_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch5_set_st: 1;
+        /** gpio_task_ch6_set_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch6_set_st: 1;
+        /** gpio_task_ch7_set_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch7_set_st: 1;
+        /** gpio_task_ch0_clear_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch0_clear_st: 1;
+        /** gpio_task_ch1_clear_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch1_clear_st: 1;
+        /** gpio_task_ch2_clear_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch2_clear_st: 1;
+        /** gpio_task_ch3_clear_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch3_clear_st: 1;
+        /** gpio_task_ch4_clear_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch4_clear_st: 1;
+        /** gpio_task_ch5_clear_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch5_clear_st: 1;
+        /** gpio_task_ch6_clear_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch6_clear_st: 1;
+        /** gpio_task_ch7_clear_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch7_clear_st: 1;
+        /** gpio_task_ch0_toggle_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch0_toggle_st: 1;
+        /** gpio_task_ch1_toggle_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch1_toggle_st: 1;
+        /** gpio_task_ch2_toggle_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch2_toggle_st: 1;
+        /** gpio_task_ch3_toggle_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch3_toggle_st: 1;
+        /** gpio_task_ch4_toggle_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch4_toggle_st: 1;
+        /** gpio_task_ch5_toggle_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch5_toggle_st: 1;
+        /** gpio_task_ch6_toggle_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch6_toggle_st: 1;
+        /** gpio_task_ch7_toggle_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t gpio_task_ch7_toggle_st: 1;
+        /** ledc_task_timer0_res_update_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_timer0_res_update_st: 1;
+        /** ledc_task_timer1_res_update_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_timer1_res_update_st: 1;
+        /** ledc_task_timer2_res_update_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_timer2_res_update_st: 1;
+        /** ledc_task_timer3_res_update_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_timer3_res_update_st: 1;
+        /** ledc_task_duty_scale_update_ch0_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_duty_scale_update_ch0_st: 1;
+        /** ledc_task_duty_scale_update_ch1_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_duty_scale_update_ch1_st: 1;
+        /** ledc_task_duty_scale_update_ch2_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_duty_scale_update_ch2_st: 1;
+        /** ledc_task_duty_scale_update_ch3_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_duty_scale_update_ch3_st: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st0_reg_t;
+
+/** Type of task_st1 register
+ *  Tasks trigger status register
+ */
+typedef union {
+    struct {
+        /** ledc_task_duty_scale_update_ch4_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_duty_scale_update_ch4_st: 1;
+        /** ledc_task_duty_scale_update_ch5_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_duty_scale_update_ch5_st: 1;
+        /** ledc_task_duty_scale_update_ch6_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents LEDC_task_duty_scale_update_ch6 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_duty_scale_update_ch6_st: 1;
+        /** ledc_task_duty_scale_update_ch7_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents LEDC_task_duty_scale_update_ch7 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_duty_scale_update_ch7_st: 1;
+        /** ledc_task_timer0_cap_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer0_cap_st: 1;
+        /** ledc_task_timer1_cap_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer1_cap_st: 1;
+        /** ledc_task_timer2_cap_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer2_cap_st: 1;
+        /** ledc_task_timer3_cap_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer3_cap_st: 1;
+        /** ledc_task_sig_out_dis_ch0_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_sig_out_dis_ch0_st: 1;
+        /** ledc_task_sig_out_dis_ch1_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_sig_out_dis_ch1_st: 1;
+        /** ledc_task_sig_out_dis_ch2_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_sig_out_dis_ch2_st: 1;
+        /** ledc_task_sig_out_dis_ch3_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_sig_out_dis_ch3_st: 1;
+        /** ledc_task_sig_out_dis_ch4_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_sig_out_dis_ch4_st: 1;
+        /** ledc_task_sig_out_dis_ch5_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_sig_out_dis_ch5_st: 1;
+        /** ledc_task_sig_out_dis_ch6_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents LEDC_task_sig_out_dis_ch6 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_sig_out_dis_ch6_st: 1;
+        /** ledc_task_sig_out_dis_ch7_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents LEDC_task_sig_out_dis_ch7 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_sig_out_dis_ch7_st: 1;
+        /** ledc_task_ovf_cnt_rst_ch0_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch0_st: 1;
+        /** ledc_task_ovf_cnt_rst_ch1_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch1_st: 1;
+        /** ledc_task_ovf_cnt_rst_ch2_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch2_st: 1;
+        /** ledc_task_ovf_cnt_rst_ch3_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch3_st: 1;
+        /** ledc_task_ovf_cnt_rst_ch4_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch4_st: 1;
+        /** ledc_task_ovf_cnt_rst_ch5_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch5_st: 1;
+        /** ledc_task_ovf_cnt_rst_ch6_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch6_st: 1;
+        /** ledc_task_ovf_cnt_rst_ch7_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch7_st: 1;
+        /** ledc_task_timer0_rst_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer0_rst_st: 1;
+        /** ledc_task_timer1_rst_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer1_rst_st: 1;
+        /** ledc_task_timer2_rst_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer2_rst_st: 1;
+        /** ledc_task_timer3_rst_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer3_rst_st: 1;
+        /** ledc_task_timer0_resume_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer0_resume_st: 1;
+        /** ledc_task_timer1_resume_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer1_resume_st: 1;
+        /** ledc_task_timer2_resume_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer2_resume_st: 1;
+        /** ledc_task_timer3_resume_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer3_resume_st: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st1_reg_t;
+
+/** Type of task_st2 register
+ *  Tasks trigger status register
+ */
+typedef union {
+    struct {
+        /** ledc_task_timer0_pause_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer0_pause_st: 1;
+        /** ledc_task_timer1_pause_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer1_pause_st: 1;
+        /** ledc_task_timer2_pause_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer2_pause_st: 1;
+        /** ledc_task_timer3_pause_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_timer3_pause_st: 1;
+        /** ledc_task_gamma_restart_ch0_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_restart_ch0_st: 1;
+        /** ledc_task_gamma_restart_ch1_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_restart_ch1_st: 1;
+        /** ledc_task_gamma_restart_ch2_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_restart_ch2_st: 1;
+        /** ledc_task_gamma_restart_ch3_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_restart_ch3_st: 1;
+        /** ledc_task_gamma_restart_ch4_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_restart_ch4_st: 1;
+        /** ledc_task_gamma_restart_ch5_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_restart_ch5_st: 1;
+        /** ledc_task_gamma_restart_ch6_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents LEDC_task_gamma_restart_ch6 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_restart_ch6_st: 1;
+        /** ledc_task_gamma_restart_ch7_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents LEDC_task_gamma_restart_ch7 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_restart_ch7_st: 1;
+        /** ledc_task_gamma_pause_ch0_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_gamma_pause_ch0_st: 1;
+        /** ledc_task_gamma_pause_ch1_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_gamma_pause_ch1_st: 1;
+        /** ledc_task_gamma_pause_ch2_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_gamma_pause_ch2_st: 1;
+        /** ledc_task_gamma_pause_ch3_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_gamma_pause_ch3_st: 1;
+        /** ledc_task_gamma_pause_ch4_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_gamma_pause_ch4_st: 1;
+        /** ledc_task_gamma_pause_ch5_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_gamma_pause_ch5_st: 1;
+        /** ledc_task_gamma_pause_ch6_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents LEDC_task_gamma_pause_ch6 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_gamma_pause_ch6_st: 1;
+        /** ledc_task_gamma_pause_ch7_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents LEDC_task_gamma_pause_ch7 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ledc_task_gamma_pause_ch7_st: 1;
+        /** ledc_task_gamma_resume_ch0_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_resume_ch0_st: 1;
+        /** ledc_task_gamma_resume_ch1_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_resume_ch1_st: 1;
+        /** ledc_task_gamma_resume_ch2_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_resume_ch2_st: 1;
+        /** ledc_task_gamma_resume_ch3_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_resume_ch3_st: 1;
+        /** ledc_task_gamma_resume_ch4_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_resume_ch4_st: 1;
+        /** ledc_task_gamma_resume_ch5_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_resume_ch5_st: 1;
+        /** ledc_task_gamma_resume_ch6_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents LEDC_task_gamma_resume_ch6 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_resume_ch6_st: 1;
+        /** ledc_task_gamma_resume_ch7_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents LEDC_task_gamma_resume_ch7 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t ledc_task_gamma_resume_ch7_st: 1;
+        /** tg0_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg0_task_cnt_start_timer0_st: 1;
+        /** tg0_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t tg0_task_alarm_start_timer0_st: 1;
+        /** tg0_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg0_task_cnt_stop_timer0_st: 1;
+        /** tg0_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t tg0_task_cnt_reload_timer0_st: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st2_reg_t;
+
+/** Type of task_st3 register
+ *  Tasks trigger status register
+ */
+typedef union {
+    struct {
+        /** tg0_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg0_task_cnt_cap_timer0_st: 1;
+        /** tg0_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg0_task_cnt_start_timer1_st: 1;
+        /** tg0_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t tg0_task_alarm_start_timer1_st: 1;
+        /** tg0_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg0_task_cnt_stop_timer1_st: 1;
+        /** tg0_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t tg0_task_cnt_reload_timer1_st: 1;
+        /** tg0_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg0_task_cnt_cap_timer1_st: 1;
+        /** tg1_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg1_task_cnt_start_timer0_st: 1;
+        /** tg1_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t tg1_task_alarm_start_timer0_st: 1;
+        /** tg1_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg1_task_cnt_stop_timer0_st: 1;
+        /** tg1_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t tg1_task_cnt_reload_timer0_st: 1;
+        /** tg1_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg1_task_cnt_cap_timer0_st: 1;
+        /** tg1_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg1_task_cnt_start_timer1_st: 1;
+        /** tg1_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t tg1_task_alarm_start_timer1_st: 1;
+        /** tg1_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg1_task_cnt_stop_timer1_st: 1;
+        /** tg1_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t tg1_task_cnt_reload_timer1_st: 1;
+        /** tg1_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tg1_task_cnt_cap_timer1_st: 1;
+        /** mcpwm0_task_cmpr0_a_up_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_cmpr0_a_up_st: 1;
+        /** mcpwm0_task_cmpr1_a_up_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_cmpr1_a_up_st: 1;
+        /** mcpwm0_task_cmpr2_a_up_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_cmpr2_a_up_st: 1;
+        /** mcpwm0_task_cmpr0_b_up_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_cmpr0_b_up_st: 1;
+        /** mcpwm0_task_cmpr1_b_up_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_cmpr1_b_up_st: 1;
+        /** mcpwm0_task_cmpr2_b_up_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_cmpr2_b_up_st: 1;
+        /** mcpwm0_task_gen_stop_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_gen_stop_st: 1;
+        /** mcpwm0_task_timer0_syn_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_timer0_syn_st: 1;
+        /** mcpwm0_task_timer1_syn_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_timer1_syn_st: 1;
+        /** mcpwm0_task_timer2_syn_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_timer2_syn_st: 1;
+        /** mcpwm0_task_timer0_period_up_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t mcpwm0_task_timer0_period_up_st: 1;
+        /** mcpwm0_task_timer1_period_up_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t mcpwm0_task_timer1_period_up_st: 1;
+        /** mcpwm0_task_timer2_period_up_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t mcpwm0_task_timer2_period_up_st: 1;
+        /** mcpwm0_task_tz0_ost_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_tz0_ost_st: 1;
+        /** mcpwm0_task_tz1_ost_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_tz1_ost_st: 1;
+        /** mcpwm0_task_tz2_ost_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_tz2_ost_st: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st3_reg_t;
+
+/** Type of task_st4 register
+ *  Tasks trigger status register
+ */
+typedef union {
+    struct {
+        /** mcpwm0_task_clr0_ost_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_clr0_ost_st: 1;
+        /** mcpwm0_task_clr1_ost_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_clr1_ost_st: 1;
+        /** mcpwm0_task_clr2_ost_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_clr2_ost_st: 1;
+        /** mcpwm0_task_cap0_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_cap0_st: 1;
+        /** mcpwm0_task_cap1_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_cap1_st: 1;
+        /** mcpwm0_task_cap2_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm0_task_cap2_st: 1;
+        /** mcpwm1_task_cmpr0_a_up_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents MCPWM1_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_cmpr0_a_up_st: 1;
+        /** mcpwm1_task_cmpr1_a_up_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents MCPWM1_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_cmpr1_a_up_st: 1;
+        /** mcpwm1_task_cmpr2_a_up_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents MCPWM1_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_cmpr2_a_up_st: 1;
+        /** mcpwm1_task_cmpr0_b_up_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents MCPWM1_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_cmpr0_b_up_st: 1;
+        /** mcpwm1_task_cmpr1_b_up_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents MCPWM1_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_cmpr1_b_up_st: 1;
+        /** mcpwm1_task_cmpr2_b_up_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents MCPWM1_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_cmpr2_b_up_st: 1;
+        /** mcpwm1_task_gen_stop_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents MCPWM1_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_gen_stop_st: 1;
+        /** mcpwm1_task_timer0_syn_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents MCPWM1_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_timer0_syn_st: 1;
+        /** mcpwm1_task_timer1_syn_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents MCPWM1_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_timer1_syn_st: 1;
+        /** mcpwm1_task_timer2_syn_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents MCPWM1_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_timer2_syn_st: 1;
+        /** mcpwm1_task_timer0_period_up_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents MCPWM1_task_timer0_period_up trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t mcpwm1_task_timer0_period_up_st: 1;
+        /** mcpwm1_task_timer1_period_up_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents MCPWM1_task_timer1_period_up trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t mcpwm1_task_timer1_period_up_st: 1;
+        /** mcpwm1_task_timer2_period_up_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents MCPWM1_task_timer2_period_up trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t mcpwm1_task_timer2_period_up_st: 1;
+        /** mcpwm1_task_tz0_ost_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents MCPWM1_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_tz0_ost_st: 1;
+        /** mcpwm1_task_tz1_ost_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents MCPWM1_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_tz1_ost_st: 1;
+        /** mcpwm1_task_tz2_ost_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents MCPWM1_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_tz2_ost_st: 1;
+        /** mcpwm1_task_clr0_ost_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents MCPWM1_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_clr0_ost_st: 1;
+        /** mcpwm1_task_clr1_ost_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents MCPWM1_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_clr1_ost_st: 1;
+        /** mcpwm1_task_clr2_ost_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents MCPWM1_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_clr2_ost_st: 1;
+        /** mcpwm1_task_cap0_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents MCPWM1_task_cap0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_cap0_st: 1;
+        /** mcpwm1_task_cap1_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents MCPWM1_task_cap1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_cap1_st: 1;
+        /** mcpwm1_task_cap2_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents MCPWM1_task_cap2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t mcpwm1_task_cap2_st: 1;
+        /** adc_task_sample0_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_task_sample0_st: 1;
+        /** adc_task_sample1_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_task_sample1_st: 1;
+        /** adc_task_start0_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_task_start0_st: 1;
+        /** adc_task_stop0_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t adc_task_stop0_st: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st4_reg_t;
+
+/** Type of task_st5 register
+ *  Tasks trigger status register
+ */
+typedef union {
+    struct {
+        /** regdma_task_start0_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_task_start0_st: 1;
+        /** regdma_task_start1_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_task_start1_st: 1;
+        /** regdma_task_start2_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_task_start2_st: 1;
+        /** regdma_task_start3_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t regdma_task_start3_st: 1;
+        /** tmpsnsr_task_start_sample_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tmpsnsr_task_start_sample_st: 1;
+        /** tmpsnsr_task_stop_sample_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t tmpsnsr_task_stop_sample_st: 1;
+        /** i2s0_task_start_rx_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s0_task_start_rx_st: 1;
+        /** i2s0_task_start_tx_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s0_task_start_tx_st: 1;
+        /** i2s0_task_stop_rx_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s0_task_stop_rx_st: 1;
+        /** i2s0_task_stop_tx_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s0_task_stop_tx_st: 1;
+        /** i2s1_task_start_rx_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s1_task_start_rx_st: 1;
+        /** i2s1_task_start_tx_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s1_task_start_tx_st: 1;
+        /** i2s1_task_stop_rx_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s1_task_stop_rx_st: 1;
+        /** i2s1_task_stop_tx_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s1_task_stop_tx_st: 1;
+        /** i2s2_task_start_rx_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents I2S2_task_start_rx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s2_task_start_rx_st: 1;
+        /** i2s2_task_start_tx_st : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Represents I2S2_task_start_tx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s2_task_start_tx_st: 1;
+        /** i2s2_task_stop_rx_st : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Represents I2S2_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s2_task_stop_rx_st: 1;
+        /** i2s2_task_stop_tx_st : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Represents I2S2_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t i2s2_task_stop_tx_st: 1;
+        /** ulp_task_wakeup_cpu_st : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ulp_task_wakeup_cpu_st: 1;
+        /** ulp_task_int_cpu_st : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t ulp_task_int_cpu_st: 1;
+        /** rtc_task_start_st : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t rtc_task_start_st: 1;
+        /** rtc_task_stop_st : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t rtc_task_stop_st: 1;
+        /** rtc_task_clr_st : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t rtc_task_clr_st: 1;
+        /** rtc_task_triggerflw_st : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t rtc_task_triggerflw_st: 1;
+        /** pdma_ahb_task_in_start_ch0_st : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Represents PDMA_AHB_task_in_start_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_task_in_start_ch0_st: 1;
+        /** pdma_ahb_task_in_start_ch1_st : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Represents PDMA_AHB_task_in_start_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_task_in_start_ch1_st: 1;
+        /** pdma_ahb_task_in_start_ch2_st : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Represents PDMA_AHB_task_in_start_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_task_in_start_ch2_st: 1;
+        /** pdma_ahb_task_out_start_ch0_st : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Represents PDMA_AHB_task_out_start_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_task_out_start_ch0_st: 1;
+        /** pdma_ahb_task_out_start_ch1_st : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Represents PDMA_AHB_task_out_start_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_task_out_start_ch1_st: 1;
+        /** pdma_ahb_task_out_start_ch2_st : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Represents PDMA_AHB_task_out_start_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_ahb_task_out_start_ch2_st: 1;
+        /** pdma_axi_task_in_start_ch0_st : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Represents PDMA_AXI_task_in_start_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_task_in_start_ch0_st: 1;
+        /** pdma_axi_task_in_start_ch1_st : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Represents PDMA_AXI_task_in_start_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_task_in_start_ch1_st: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st5_reg_t;
+
+/** Type of task_st6 register
+ *  Tasks trigger status register
+ */
+typedef union {
+    struct {
+        /** pdma_axi_task_in_start_ch2_st : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Represents PDMA_AXI_task_in_start_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_task_in_start_ch2_st: 1;
+        /** pdma_axi_task_out_start_ch0_st : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Represents PDMA_AXI_task_out_start_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_task_out_start_ch0_st: 1;
+        /** pdma_axi_task_out_start_ch1_st : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Represents PDMA_AXI_task_out_start_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_task_out_start_ch1_st: 1;
+        /** pdma_axi_task_out_start_ch2_st : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Represents PDMA_AXI_task_out_start_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t pdma_axi_task_out_start_ch2_st: 1;
+        /** pmu_task_sleep_req_st : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t pmu_task_sleep_req_st: 1;
+        /** dma2d_task_in_start_ch0_st : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Represents DMA2D_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_task_in_start_ch0_st: 1;
+        /** dma2d_task_in_start_ch1_st : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Represents DMA2D_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_task_in_start_ch1_st: 1;
+        /** dma2d_task_in_dscr_ready_ch0_st : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t dma2d_task_in_dscr_ready_ch0_st: 1;
+        /** dma2d_task_in_dscr_ready_ch1_st : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t dma2d_task_in_dscr_ready_ch1_st: 1;
+        /** dma2d_task_out_start_ch0_st : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Represents DMA2D_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_task_out_start_ch0_st: 1;
+        /** dma2d_task_out_start_ch1_st : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Represents DMA2D_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_task_out_start_ch1_st: 1;
+        /** dma2d_task_out_start_ch2_st : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Represents DMA2D_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered
+         */
+        uint32_t dma2d_task_out_start_ch2_st: 1;
+        /** dma2d_task_out_dscr_ready_ch0_st : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t dma2d_task_out_dscr_ready_ch0_st: 1;
+        /** dma2d_task_out_dscr_ready_ch1_st : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t dma2d_task_out_dscr_ready_ch1_st: 1;
+        /** dma2d_task_out_dscr_ready_ch2_st : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Not triggered\\1:
+         *  Triggered
+         */
+        uint32_t dma2d_task_out_dscr_ready_ch2_st: 1;
+        uint32_t reserved_15: 17;
+    };
+    uint32_t val;
+} soc_etm_task_st6_reg_t;
+
+/** Group: Configuration Register */
+/** Type of ch_ena_ad0_set register
+ *  Channel enable set register
+ */
+typedef union {
+    struct {
+        /** ch_set0 : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set0: 1;
+        /** ch_set1 : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set1: 1;
+        /** ch_set2 : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set2: 1;
+        /** ch_set3 : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set3: 1;
+        /** ch_set4 : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set4: 1;
+        /** ch_set5 : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set5: 1;
+        /** ch_set6 : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set6: 1;
+        /** ch_set7 : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set7: 1;
+        /** ch_set8 : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set8: 1;
+        /** ch_set9 : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set9: 1;
+        /** ch_set10 : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set10: 1;
+        /** ch_set11 : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set11: 1;
+        /** ch_set12 : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set12: 1;
+        /** ch_set13 : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set13: 1;
+        /** ch_set14 : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set14: 1;
+        /** ch_set15 : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set15: 1;
+        /** ch_set16 : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set16: 1;
+        /** ch_set17 : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set17: 1;
+        /** ch_set18 : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set18: 1;
+        /** ch_set19 : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set19: 1;
+        /** ch_set20 : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set20: 1;
+        /** ch_set21 : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set21: 1;
+        /** ch_set22 : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set22: 1;
+        /** ch_set23 : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set23: 1;
+        /** ch_set24 : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set24: 1;
+        /** ch_set25 : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set25: 1;
+        /** ch_set26 : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set26: 1;
+        /** ch_set27 : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set27: 1;
+        /** ch_set28 : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set28: 1;
+        /** ch_set29 : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set29: 1;
+        /** ch_set30 : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set30: 1;
+        /** ch_set31 : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set31: 1;
+    };
+    uint32_t val;
+} soc_etm_ch_ena_ad0_set_reg_t;
+
+/** Type of ch_ena_ad0_clr register
+ *  Channel enable clear register
+ */
+typedef union {
+    struct {
+        /** ch_clr0 : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr0: 1;
+        /** ch_clr1 : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr1: 1;
+        /** ch_clr2 : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr2: 1;
+        /** ch_clr3 : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr3: 1;
+        /** ch_clr4 : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr4: 1;
+        /** ch_clr5 : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr5: 1;
+        /** ch_clr6 : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr6: 1;
+        /** ch_clr7 : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr7: 1;
+        /** ch_clr8 : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr8: 1;
+        /** ch_clr9 : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr9: 1;
+        /** ch_clr10 : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr10: 1;
+        /** ch_clr11 : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr11: 1;
+        /** ch_clr12 : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr12: 1;
+        /** ch_clr13 : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr13: 1;
+        /** ch_clr14 : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr14: 1;
+        /** ch_clr15 : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr15: 1;
+        /** ch_clr16 : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr16: 1;
+        /** ch_clr17 : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr17: 1;
+        /** ch_clr18 : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr18: 1;
+        /** ch_clr19 : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr19: 1;
+        /** ch_clr20 : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr20: 1;
+        /** ch_clr21 : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr21: 1;
+        /** ch_clr22 : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr22: 1;
+        /** ch_clr23 : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr23: 1;
+        /** ch_clr24 : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr24: 1;
+        /** ch_clr25 : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr25: 1;
+        /** ch_clr26 : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr26: 1;
+        /** ch_clr27 : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr27: 1;
+        /** ch_clr28 : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr28: 1;
+        /** ch_clr29 : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr29: 1;
+        /** ch_clr30 : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr30: 1;
+        /** ch_clr31 : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr31: 1;
+    };
+    uint32_t val;
+} soc_etm_ch_ena_ad0_clr_reg_t;
+
+/** Type of ch_ena_ad1_set register
+ *  Channel enable set register
+ */
+typedef union {
+    struct {
+        /** ch_set32 : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set32: 1;
+        /** ch_set33 : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set33: 1;
+        /** ch_set34 : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set34: 1;
+        /** ch_set35 : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set35: 1;
+        /** ch_set36 : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set36: 1;
+        /** ch_set37 : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set37: 1;
+        /** ch_set38 : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set38: 1;
+        /** ch_set39 : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set39: 1;
+        /** ch_set40 : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set40: 1;
+        /** ch_set41 : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set41: 1;
+        /** ch_set42 : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set42: 1;
+        /** ch_set43 : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set43: 1;
+        /** ch_set44 : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set44: 1;
+        /** ch_set45 : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set45: 1;
+        /** ch_set46 : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set46: 1;
+        /** ch_set47 : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set47: 1;
+        /** ch_set48 : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set48: 1;
+        /** ch_set49 : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable
+         */
+        uint32_t ch_set49: 1;
+        uint32_t reserved_18: 14;
+    };
+    uint32_t val;
+} soc_etm_ch_ena_ad1_set_reg_t;
+
+/** Type of ch_ena_ad1_clr register
+ *  Channel enable clear register
+ */
+typedef union {
+    struct {
+        /** ch_clr32 : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr32: 1;
+        /** ch_clr33 : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr33: 1;
+        /** ch_clr34 : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr34: 1;
+        /** ch_clr35 : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr35: 1;
+        /** ch_clr36 : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr36: 1;
+        /** ch_clr37 : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr37: 1;
+        /** ch_clr38 : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr38: 1;
+        /** ch_clr39 : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr39: 1;
+        /** ch_clr40 : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr40: 1;
+        /** ch_clr41 : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr41: 1;
+        /** ch_clr42 : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr42: 1;
+        /** ch_clr43 : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr43: 1;
+        /** ch_clr44 : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr44: 1;
+        /** ch_clr45 : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr45: 1;
+        /** ch_clr46 : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr46: 1;
+        /** ch_clr47 : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr47: 1;
+        /** ch_clr48 : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr48: 1;
+        /** ch_clr49 : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ch_clr49: 1;
+        uint32_t reserved_18: 14;
+    };
+    uint32_t val;
+} soc_etm_ch_ena_ad1_clr_reg_t;
+
+/** Type of chn_evt_id register
+ *  Channeln event id register
+ */
+typedef union {
+    struct {
+        /** evt_id : R/W; bitpos: [7:0]; default: 0;
+         *  Configures chn_evt_id
+         */
+        uint32_t evt_id: 8;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} soc_etm_chn_evt_id_reg_t;
+
+/** Type of chn_task_id register
+ *  Channeln task id register
+ */
+typedef union {
+    struct {
+        /** chn_task_id : R/W; bitpos: [7:0]; default: 0;
+         *  Configures chn_task_id
+         */
+        uint32_t task_id: 8;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} soc_etm_chn_task_id_reg_t;
+
+/** Type of evt_st0_clr register
+ *  Events trigger status clear register
+ */
+typedef union {
+    struct {
+        /** gpio_evt_ch0_rise_edge_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch0_rise_edge_st_clr: 1;
+        /** gpio_evt_ch1_rise_edge_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch1_rise_edge_st_clr: 1;
+        /** gpio_evt_ch2_rise_edge_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch2_rise_edge_st_clr: 1;
+        /** gpio_evt_ch3_rise_edge_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch3_rise_edge_st_clr: 1;
+        /** gpio_evt_ch4_rise_edge_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch4_rise_edge_st_clr: 1;
+        /** gpio_evt_ch5_rise_edge_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch5_rise_edge_st_clr: 1;
+        /** gpio_evt_ch6_rise_edge_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch6_rise_edge_st_clr: 1;
+        /** gpio_evt_ch7_rise_edge_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch7_rise_edge_st_clr: 1;
+        /** gpio_evt_ch0_fall_edge_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch0_fall_edge_st_clr: 1;
+        /** gpio_evt_ch1_fall_edge_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch1_fall_edge_st_clr: 1;
+        /** gpio_evt_ch2_fall_edge_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch2_fall_edge_st_clr: 1;
+        /** gpio_evt_ch3_fall_edge_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch3_fall_edge_st_clr: 1;
+        /** gpio_evt_ch4_fall_edge_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch4_fall_edge_st_clr: 1;
+        /** gpio_evt_ch5_fall_edge_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch5_fall_edge_st_clr: 1;
+        /** gpio_evt_ch6_fall_edge_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch6_fall_edge_st_clr: 1;
+        /** gpio_evt_ch7_fall_edge_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch7_fall_edge_st_clr: 1;
+        /** gpio_evt_ch0_any_edge_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch0_any_edge_st_clr: 1;
+        /** gpio_evt_ch1_any_edge_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch1_any_edge_st_clr: 1;
+        /** gpio_evt_ch2_any_edge_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch2_any_edge_st_clr: 1;
+        /** gpio_evt_ch3_any_edge_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch3_any_edge_st_clr: 1;
+        /** gpio_evt_ch4_any_edge_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch4_any_edge_st_clr: 1;
+        /** gpio_evt_ch5_any_edge_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch5_any_edge_st_clr: 1;
+        /** gpio_evt_ch6_any_edge_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch6_any_edge_st_clr: 1;
+        /** gpio_evt_ch7_any_edge_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_ch7_any_edge_st_clr: 1;
+        /** gpio_evt_zero_det_pos0_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_zero_det_pos0_st_clr: 1;
+        /** gpio_evt_zero_det_neg0_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_zero_det_neg0_st_clr: 1;
+        /** gpio_evt_zero_det_pos1_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_zero_det_pos1_st_clr: 1;
+        /** gpio_evt_zero_det_neg1_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_evt_zero_det_neg1_st_clr: 1;
+        /** ledc_evt_duty_chng_end_ch0_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_duty_chng_end_ch0_st_clr: 1;
+        /** ledc_evt_duty_chng_end_ch1_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_duty_chng_end_ch1_st_clr: 1;
+        /** ledc_evt_duty_chng_end_ch2_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_duty_chng_end_ch2_st_clr: 1;
+        /** ledc_evt_duty_chng_end_ch3_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_duty_chng_end_ch3_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st0_clr_reg_t;
+
+/** Type of evt_st1_clr register
+ *  Events trigger status clear register
+ */
+typedef union {
+    struct {
+        /** ledc_evt_duty_chng_end_ch4_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_duty_chng_end_ch4_st_clr: 1;
+        /** ledc_evt_duty_chng_end_ch5_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_duty_chng_end_ch5_st_clr: 1;
+        /** ledc_evt_duty_chng_end_ch6_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_duty_chng_end_ch6_st_clr: 1;
+        /** ledc_evt_duty_chng_end_ch7_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_duty_chng_end_ch7_st_clr: 1;
+        /** ledc_evt_ovf_cnt_pls_ch0_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch0_st_clr: 1;
+        /** ledc_evt_ovf_cnt_pls_ch1_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch1_st_clr: 1;
+        /** ledc_evt_ovf_cnt_pls_ch2_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch2_st_clr: 1;
+        /** ledc_evt_ovf_cnt_pls_ch3_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch3_st_clr: 1;
+        /** ledc_evt_ovf_cnt_pls_ch4_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch4_st_clr: 1;
+        /** ledc_evt_ovf_cnt_pls_ch5_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch5_st_clr: 1;
+        /** ledc_evt_ovf_cnt_pls_ch6_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch6_st_clr: 1;
+        /** ledc_evt_ovf_cnt_pls_ch7_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_ovf_cnt_pls_ch7_st_clr: 1;
+        /** ledc_evt_time_ovf_timer0_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_time_ovf_timer0_st_clr: 1;
+        /** ledc_evt_time_ovf_timer1_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_time_ovf_timer1_st_clr: 1;
+        /** ledc_evt_time_ovf_timer2_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_time_ovf_timer2_st_clr: 1;
+        /** ledc_evt_time_ovf_timer3_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_evt_time_ovf_timer3_st_clr: 1;
+        /** ledc_evt_timer0_cmp_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t ledc_evt_timer0_cmp_st_clr: 1;
+        /** ledc_evt_timer1_cmp_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t ledc_evt_timer1_cmp_st_clr: 1;
+        /** ledc_evt_timer2_cmp_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t ledc_evt_timer2_cmp_st_clr: 1;
+        /** ledc_evt_timer3_cmp_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t ledc_evt_timer3_cmp_st_clr: 1;
+        /** tg0_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_evt_cnt_cmp_timer0_st_clr: 1;
+        /** tg0_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_evt_cnt_cmp_timer1_st_clr: 1;
+        /** tg1_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_evt_cnt_cmp_timer0_st_clr: 1;
+        /** tg1_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_evt_cnt_cmp_timer1_st_clr: 1;
+        /** systimer_evt_cnt_cmp0_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t systimer_evt_cnt_cmp0_st_clr: 1;
+        /** systimer_evt_cnt_cmp1_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t systimer_evt_cnt_cmp1_st_clr: 1;
+        /** systimer_evt_cnt_cmp2_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t systimer_evt_cnt_cmp2_st_clr: 1;
+        /** mcpwm0_evt_timer0_stop_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_timer0_stop_st_clr: 1;
+        /** mcpwm0_evt_timer1_stop_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_timer1_stop_st_clr: 1;
+        /** mcpwm0_evt_timer2_stop_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_timer2_stop_st_clr: 1;
+        /** mcpwm0_evt_timer0_tez_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_timer0_tez_st_clr: 1;
+        /** mcpwm0_evt_timer1_tez_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_timer1_tez_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st1_clr_reg_t;
+
+/** Type of evt_st2_clr register
+ *  Events trigger status clear register
+ */
+typedef union {
+    struct {
+        /** mcpwm0_evt_timer2_tez_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_timer2_tez_st_clr: 1;
+        /** mcpwm0_evt_timer0_tep_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_timer0_tep_st_clr: 1;
+        /** mcpwm0_evt_timer1_tep_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_timer1_tep_st_clr: 1;
+        /** mcpwm0_evt_timer2_tep_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_timer2_tep_st_clr: 1;
+        /** mcpwm0_evt_op0_tea_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op0_tea_st_clr: 1;
+        /** mcpwm0_evt_op1_tea_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op1_tea_st_clr: 1;
+        /** mcpwm0_evt_op2_tea_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op2_tea_st_clr: 1;
+        /** mcpwm0_evt_op0_teb_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op0_teb_st_clr: 1;
+        /** mcpwm0_evt_op1_teb_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op1_teb_st_clr: 1;
+        /** mcpwm0_evt_op2_teb_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op2_teb_st_clr: 1;
+        /** mcpwm0_evt_f0_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_f0_st_clr: 1;
+        /** mcpwm0_evt_f1_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_f1_st_clr: 1;
+        /** mcpwm0_evt_f2_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_f2_st_clr: 1;
+        /** mcpwm0_evt_f0_clr_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_f0_clr_st_clr: 1;
+        /** mcpwm0_evt_f1_clr_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_f1_clr_st_clr: 1;
+        /** mcpwm0_evt_f2_clr_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_f2_clr_st_clr: 1;
+        /** mcpwm0_evt_tz0_cbc_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_tz0_cbc_st_clr: 1;
+        /** mcpwm0_evt_tz1_cbc_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_tz1_cbc_st_clr: 1;
+        /** mcpwm0_evt_tz2_cbc_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_tz2_cbc_st_clr: 1;
+        /** mcpwm0_evt_tz0_ost_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_tz0_ost_st_clr: 1;
+        /** mcpwm0_evt_tz1_ost_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_tz1_ost_st_clr: 1;
+        /** mcpwm0_evt_tz2_ost_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_tz2_ost_st_clr: 1;
+        /** mcpwm0_evt_cap0_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_cap0_st_clr: 1;
+        /** mcpwm0_evt_cap1_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_cap1_st_clr: 1;
+        /** mcpwm0_evt_cap2_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_cap2_st_clr: 1;
+        /** mcpwm0_evt_op0_tee1_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op0_tee1_st_clr: 1;
+        /** mcpwm0_evt_op1_tee1_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op1_tee1_st_clr: 1;
+        /** mcpwm0_evt_op2_tee1_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op2_tee1_st_clr: 1;
+        /** mcpwm0_evt_op0_tee2_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op0_tee2_st_clr: 1;
+        /** mcpwm0_evt_op1_tee2_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op1_tee2_st_clr: 1;
+        /** mcpwm0_evt_op2_tee2_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_evt_op2_tee2_st_clr: 1;
+        /** mcpwm1_evt_timer0_stop_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_timer0_stop_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st2_clr_reg_t;
+
+/** Type of evt_st3_clr register
+ *  Events trigger status clear register
+ */
+typedef union {
+    struct {
+        /** mcpwm1_evt_timer1_stop_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_timer1_stop_st_clr: 1;
+        /** mcpwm1_evt_timer2_stop_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_timer2_stop_st_clr: 1;
+        /** mcpwm1_evt_timer0_tez_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_timer0_tez_st_clr: 1;
+        /** mcpwm1_evt_timer1_tez_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_timer1_tez_st_clr: 1;
+        /** mcpwm1_evt_timer2_tez_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_timer2_tez_st_clr: 1;
+        /** mcpwm1_evt_timer0_tep_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_timer0_tep_st_clr: 1;
+        /** mcpwm1_evt_timer1_tep_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_timer1_tep_st_clr: 1;
+        /** mcpwm1_evt_timer2_tep_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_timer2_tep_st_clr: 1;
+        /** mcpwm1_evt_op0_tea_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op0_tea_st_clr: 1;
+        /** mcpwm1_evt_op1_tea_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op1_tea_st_clr: 1;
+        /** mcpwm1_evt_op2_tea_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op2_tea_st_clr: 1;
+        /** mcpwm1_evt_op0_teb_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op0_teb_st_clr: 1;
+        /** mcpwm1_evt_op1_teb_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op1_teb_st_clr: 1;
+        /** mcpwm1_evt_op2_teb_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op2_teb_st_clr: 1;
+        /** mcpwm1_evt_f0_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_f0_st_clr: 1;
+        /** mcpwm1_evt_f1_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_f1_st_clr: 1;
+        /** mcpwm1_evt_f2_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_f2_st_clr: 1;
+        /** mcpwm1_evt_f0_clr_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_f0_clr_st_clr: 1;
+        /** mcpwm1_evt_f1_clr_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_f1_clr_st_clr: 1;
+        /** mcpwm1_evt_f2_clr_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_f2_clr_st_clr: 1;
+        /** mcpwm1_evt_tz0_cbc_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_tz0_cbc_st_clr: 1;
+        /** mcpwm1_evt_tz1_cbc_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_tz1_cbc_st_clr: 1;
+        /** mcpwm1_evt_tz2_cbc_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_tz2_cbc_st_clr: 1;
+        /** mcpwm1_evt_tz0_ost_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_tz0_ost_st_clr: 1;
+        /** mcpwm1_evt_tz1_ost_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_tz1_ost_st_clr: 1;
+        /** mcpwm1_evt_tz2_ost_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_tz2_ost_st_clr: 1;
+        /** mcpwm1_evt_cap0_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_cap0_st_clr: 1;
+        /** mcpwm1_evt_cap1_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_cap1_st_clr: 1;
+        /** mcpwm1_evt_cap2_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_cap2_st_clr: 1;
+        /** mcpwm1_evt_op0_tee1_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op0_tee1_st_clr: 1;
+        /** mcpwm1_evt_op1_tee1_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op1_tee1_st_clr: 1;
+        /** mcpwm1_evt_op2_tee1_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op2_tee1_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st3_clr_reg_t;
+
+/** Type of evt_st4_clr register
+ *  Events trigger status clear register
+ */
+typedef union {
+    struct {
+        /** mcpwm1_evt_op0_tee2_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op0_tee2_st_clr: 1;
+        /** mcpwm1_evt_op1_tee2_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op1_tee2_st_clr: 1;
+        /** mcpwm1_evt_op2_tee2_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_evt_op2_tee2_st_clr: 1;
+        /** adc_evt_conv_cmplt0_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t adc_evt_conv_cmplt0_st_clr: 1;
+        /** adc_evt_eq_above_thresh0_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t adc_evt_eq_above_thresh0_st_clr: 1;
+        /** adc_evt_eq_above_thresh1_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t adc_evt_eq_above_thresh1_st_clr: 1;
+        /** adc_evt_eq_below_thresh0_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t adc_evt_eq_below_thresh0_st_clr: 1;
+        /** adc_evt_eq_below_thresh1_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t adc_evt_eq_below_thresh1_st_clr: 1;
+        /** adc_evt_result_done0_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t adc_evt_result_done0_st_clr: 1;
+        /** adc_evt_stopped0_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t adc_evt_stopped0_st_clr: 1;
+        /** adc_evt_started0_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t adc_evt_started0_st_clr: 1;
+        /** regdma_evt_done0_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t regdma_evt_done0_st_clr: 1;
+        /** regdma_evt_done1_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t regdma_evt_done1_st_clr: 1;
+        /** regdma_evt_done2_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t regdma_evt_done2_st_clr: 1;
+        /** regdma_evt_done3_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t regdma_evt_done3_st_clr: 1;
+        /** regdma_evt_err0_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t regdma_evt_err0_st_clr: 1;
+        /** regdma_evt_err1_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t regdma_evt_err1_st_clr: 1;
+        /** regdma_evt_err2_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t regdma_evt_err2_st_clr: 1;
+        /** regdma_evt_err3_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t regdma_evt_err3_st_clr: 1;
+        /** tmpsnsr_evt_over_limit_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tmpsnsr_evt_over_limit_st_clr: 1;
+        /** i2s0_evt_rx_done_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t i2s0_evt_rx_done_st_clr: 1;
+        /** i2s0_evt_tx_done_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t i2s0_evt_tx_done_st_clr: 1;
+        /** i2s0_evt_x_words_received_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t i2s0_evt_x_words_received_st_clr: 1;
+        /** i2s0_evt_x_words_sent_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t i2s0_evt_x_words_sent_st_clr: 1;
+        /** i2s1_evt_rx_done_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear I2S1_evt_rx_done trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t i2s1_evt_rx_done_st_clr: 1;
+        /** i2s1_evt_tx_done_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear I2S1_evt_tx_done trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t i2s1_evt_tx_done_st_clr: 1;
+        /** i2s1_evt_x_words_received_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t i2s1_evt_x_words_received_st_clr: 1;
+        /** i2s1_evt_x_words_sent_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t i2s1_evt_x_words_sent_st_clr: 1;
+        /** i2s2_evt_rx_done_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear I2S2_evt_rx_done trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t i2s2_evt_rx_done_st_clr: 1;
+        /** i2s2_evt_tx_done_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear I2S2_evt_tx_done trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t i2s2_evt_tx_done_st_clr: 1;
+        /** i2s2_evt_x_words_received_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear I2S2_evt_x_words_received trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t i2s2_evt_x_words_received_st_clr: 1;
+        /** i2s2_evt_x_words_sent_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear I2S2_evt_x_words_sent trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t i2s2_evt_x_words_sent_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st4_clr_reg_t;
+
+/** Type of evt_st5_clr register
+ *  Events trigger status clear register
+ */
+typedef union {
+    struct {
+        /** ulp_evt_err_intr_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t ulp_evt_err_intr_st_clr: 1;
+        /** ulp_evt_halt_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t ulp_evt_halt_st_clr: 1;
+        /** ulp_evt_start_intr_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t ulp_evt_start_intr_st_clr: 1;
+        /** rtc_evt_tick_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t rtc_evt_tick_st_clr: 1;
+        /** rtc_evt_ovf_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t rtc_evt_ovf_st_clr: 1;
+        /** rtc_evt_cmp_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t rtc_evt_cmp_st_clr: 1;
+        /** pdma_ahb_evt_in_done_ch0_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_done_ch0_st_clr: 1;
+        /** pdma_ahb_evt_in_done_ch1_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_done_ch1_st_clr: 1;
+        /** pdma_ahb_evt_in_done_ch2_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_done_ch2_st_clr: 1;
+        /** pdma_ahb_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_suc_eof_ch0_st_clr: 1;
+        /** pdma_ahb_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_suc_eof_ch1_st_clr: 1;
+        /** pdma_ahb_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_suc_eof_ch2_st_clr: 1;
+        /** pdma_ahb_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_fifo_empty_ch0_st_clr: 1;
+        /** pdma_ahb_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_fifo_empty_ch1_st_clr: 1;
+        /** pdma_ahb_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_fifo_empty_ch2_st_clr: 1;
+        /** pdma_ahb_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_fifo_full_ch0_st_clr: 1;
+        /** pdma_ahb_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_fifo_full_ch1_st_clr: 1;
+        /** pdma_ahb_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_in_fifo_full_ch2_st_clr: 1;
+        /** pdma_ahb_evt_out_done_ch0_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_done_ch0_st_clr: 1;
+        /** pdma_ahb_evt_out_done_ch1_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_done_ch1_st_clr: 1;
+        /** pdma_ahb_evt_out_done_ch2_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_done_ch2_st_clr: 1;
+        /** pdma_ahb_evt_out_eof_ch0_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_eof_ch0_st_clr: 1;
+        /** pdma_ahb_evt_out_eof_ch1_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_eof_ch1_st_clr: 1;
+        /** pdma_ahb_evt_out_eof_ch2_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_eof_ch2_st_clr: 1;
+        /** pdma_ahb_evt_out_total_eof_ch0_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_total_eof_ch0_st_clr: 1;
+        /** pdma_ahb_evt_out_total_eof_ch1_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_total_eof_ch1_st_clr: 1;
+        /** pdma_ahb_evt_out_total_eof_ch2_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_total_eof_ch2_st_clr: 1;
+        /** pdma_ahb_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_fifo_empty_ch0_st_clr: 1;
+        /** pdma_ahb_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_fifo_empty_ch1_st_clr: 1;
+        /** pdma_ahb_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_fifo_empty_ch2_st_clr: 1;
+        /** pdma_ahb_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_fifo_full_ch0_st_clr: 1;
+        /** pdma_ahb_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_fifo_full_ch1_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st5_clr_reg_t;
+
+/** Type of evt_st6_clr register
+ *  Events trigger status clear register
+ */
+typedef union {
+    struct {
+        /** pdma_ahb_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_evt_out_fifo_full_ch2_st_clr: 1;
+        /** pdma_axi_evt_in_done_ch0_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_done_ch0_st_clr: 1;
+        /** pdma_axi_evt_in_done_ch1_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_done_ch1_st_clr: 1;
+        /** pdma_axi_evt_in_done_ch2_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_done_ch2_st_clr: 1;
+        /** pdma_axi_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_suc_eof_ch0_st_clr: 1;
+        /** pdma_axi_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_suc_eof_ch1_st_clr: 1;
+        /** pdma_axi_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_suc_eof_ch2_st_clr: 1;
+        /** pdma_axi_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_fifo_empty_ch0_st_clr: 1;
+        /** pdma_axi_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_fifo_empty_ch1_st_clr: 1;
+        /** pdma_axi_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_fifo_empty_ch2_st_clr: 1;
+        /** pdma_axi_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_fifo_full_ch0_st_clr: 1;
+        /** pdma_axi_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_fifo_full_ch1_st_clr: 1;
+        /** pdma_axi_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_in_fifo_full_ch2_st_clr: 1;
+        /** pdma_axi_evt_out_done_ch0_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_done_ch0_st_clr: 1;
+        /** pdma_axi_evt_out_done_ch1_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_done_ch1_st_clr: 1;
+        /** pdma_axi_evt_out_done_ch2_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_done_ch2_st_clr: 1;
+        /** pdma_axi_evt_out_eof_ch0_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_eof_ch0_st_clr: 1;
+        /** pdma_axi_evt_out_eof_ch1_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_eof_ch1_st_clr: 1;
+        /** pdma_axi_evt_out_eof_ch2_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_eof_ch2_st_clr: 1;
+        /** pdma_axi_evt_out_total_eof_ch0_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_total_eof_ch0_st_clr: 1;
+        /** pdma_axi_evt_out_total_eof_ch1_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_total_eof_ch1_st_clr: 1;
+        /** pdma_axi_evt_out_total_eof_ch2_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_total_eof_ch2_st_clr: 1;
+        /** pdma_axi_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_fifo_empty_ch0_st_clr: 1;
+        /** pdma_axi_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_fifo_empty_ch1_st_clr: 1;
+        /** pdma_axi_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_fifo_empty_ch2_st_clr: 1;
+        /** pdma_axi_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_fifo_full_ch0_st_clr: 1;
+        /** pdma_axi_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_fifo_full_ch1_st_clr: 1;
+        /** pdma_axi_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_evt_out_fifo_full_ch2_st_clr: 1;
+        /** pmu_evt_sleep_weekup_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pmu_evt_sleep_weekup_st_clr: 1;
+        /** dma2d_evt_in_done_ch0_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_in_done_ch0_st_clr: 1;
+        /** dma2d_evt_in_done_ch1_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_in_done_ch1_st_clr: 1;
+        /** dma2d_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_in_suc_eof_ch0_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_evt_st6_clr_reg_t;
+
+/** Type of evt_st7_clr register
+ *  Events trigger status clear register
+ */
+typedef union {
+    struct {
+        /** dma2d_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_in_suc_eof_ch1_st_clr: 1;
+        /** dma2d_evt_out_done_ch0_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_out_done_ch0_st_clr: 1;
+        /** dma2d_evt_out_done_ch1_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_out_done_ch1_st_clr: 1;
+        /** dma2d_evt_out_done_ch2_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_out_done_ch2_st_clr: 1;
+        /** dma2d_evt_out_eof_ch0_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_out_eof_ch0_st_clr: 1;
+        /** dma2d_evt_out_eof_ch1_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_out_eof_ch1_st_clr: 1;
+        /** dma2d_evt_out_eof_ch2_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_out_eof_ch2_st_clr: 1;
+        /** dma2d_evt_out_total_eof_ch0_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_out_total_eof_ch0_st_clr: 1;
+        /** dma2d_evt_out_total_eof_ch1_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_out_total_eof_ch1_st_clr: 1;
+        /** dma2d_evt_out_total_eof_ch2_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_evt_out_total_eof_ch2_st_clr: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} soc_etm_evt_st7_clr_reg_t;
+
+/** Type of task_st0_clr register
+ *  Tasks trigger status clear register
+ */
+typedef union {
+    struct {
+        /** gpio_task_ch0_set_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch0_set_st_clr: 1;
+        /** gpio_task_ch1_set_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch1_set_st_clr: 1;
+        /** gpio_task_ch2_set_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch2_set_st_clr: 1;
+        /** gpio_task_ch3_set_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch3_set_st_clr: 1;
+        /** gpio_task_ch4_set_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch4_set_st_clr: 1;
+        /** gpio_task_ch5_set_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch5_set_st_clr: 1;
+        /** gpio_task_ch6_set_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch6_set_st_clr: 1;
+        /** gpio_task_ch7_set_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch7_set_st_clr: 1;
+        /** gpio_task_ch0_clear_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch0_clear_st_clr: 1;
+        /** gpio_task_ch1_clear_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch1_clear_st_clr: 1;
+        /** gpio_task_ch2_clear_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch2_clear_st_clr: 1;
+        /** gpio_task_ch3_clear_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch3_clear_st_clr: 1;
+        /** gpio_task_ch4_clear_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch4_clear_st_clr: 1;
+        /** gpio_task_ch5_clear_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch5_clear_st_clr: 1;
+        /** gpio_task_ch6_clear_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch6_clear_st_clr: 1;
+        /** gpio_task_ch7_clear_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch7_clear_st_clr: 1;
+        /** gpio_task_ch0_toggle_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch0_toggle_st_clr: 1;
+        /** gpio_task_ch1_toggle_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch1_toggle_st_clr: 1;
+        /** gpio_task_ch2_toggle_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch2_toggle_st_clr: 1;
+        /** gpio_task_ch3_toggle_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch3_toggle_st_clr: 1;
+        /** gpio_task_ch4_toggle_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch4_toggle_st_clr: 1;
+        /** gpio_task_ch5_toggle_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch5_toggle_st_clr: 1;
+        /** gpio_task_ch6_toggle_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch6_toggle_st_clr: 1;
+        /** gpio_task_ch7_toggle_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t gpio_task_ch7_toggle_st_clr: 1;
+        /** ledc_task_timer0_res_update_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer0_res_update_st_clr: 1;
+        /** ledc_task_timer1_res_update_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer1_res_update_st_clr: 1;
+        /** ledc_task_timer2_res_update_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer2_res_update_st_clr: 1;
+        /** ledc_task_timer3_res_update_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer3_res_update_st_clr: 1;
+        /** ledc_task_duty_scale_update_ch0_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_duty_scale_update_ch0_st_clr: 1;
+        /** ledc_task_duty_scale_update_ch1_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_duty_scale_update_ch1_st_clr: 1;
+        /** ledc_task_duty_scale_update_ch2_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_duty_scale_update_ch2_st_clr: 1;
+        /** ledc_task_duty_scale_update_ch3_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_duty_scale_update_ch3_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st0_clr_reg_t;
+
+/** Type of task_st1_clr register
+ *  Tasks trigger status clear register
+ */
+typedef union {
+    struct {
+        /** ledc_task_duty_scale_update_ch4_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_duty_scale_update_ch4_st_clr: 1;
+        /** ledc_task_duty_scale_update_ch5_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_duty_scale_update_ch5_st_clr: 1;
+        /** ledc_task_duty_scale_update_ch6_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_duty_scale_update_ch6_st_clr: 1;
+        /** ledc_task_duty_scale_update_ch7_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_duty_scale_update_ch7_st_clr: 1;
+        /** ledc_task_timer0_cap_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer0_cap_st_clr: 1;
+        /** ledc_task_timer1_cap_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer1_cap_st_clr: 1;
+        /** ledc_task_timer2_cap_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer2_cap_st_clr: 1;
+        /** ledc_task_timer3_cap_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer3_cap_st_clr: 1;
+        /** ledc_task_sig_out_dis_ch0_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_sig_out_dis_ch0_st_clr: 1;
+        /** ledc_task_sig_out_dis_ch1_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_sig_out_dis_ch1_st_clr: 1;
+        /** ledc_task_sig_out_dis_ch2_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_sig_out_dis_ch2_st_clr: 1;
+        /** ledc_task_sig_out_dis_ch3_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_sig_out_dis_ch3_st_clr: 1;
+        /** ledc_task_sig_out_dis_ch4_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_sig_out_dis_ch4_st_clr: 1;
+        /** ledc_task_sig_out_dis_ch5_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_sig_out_dis_ch5_st_clr: 1;
+        /** ledc_task_sig_out_dis_ch6_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_sig_out_dis_ch6_st_clr: 1;
+        /** ledc_task_sig_out_dis_ch7_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_sig_out_dis_ch7_st_clr: 1;
+        /** ledc_task_ovf_cnt_rst_ch0_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch0_st_clr: 1;
+        /** ledc_task_ovf_cnt_rst_ch1_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch1_st_clr: 1;
+        /** ledc_task_ovf_cnt_rst_ch2_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch2_st_clr: 1;
+        /** ledc_task_ovf_cnt_rst_ch3_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch3_st_clr: 1;
+        /** ledc_task_ovf_cnt_rst_ch4_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch4_st_clr: 1;
+        /** ledc_task_ovf_cnt_rst_ch5_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch5_st_clr: 1;
+        /** ledc_task_ovf_cnt_rst_ch6_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch6_st_clr: 1;
+        /** ledc_task_ovf_cnt_rst_ch7_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_ovf_cnt_rst_ch7_st_clr: 1;
+        /** ledc_task_timer0_rst_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer0_rst_st_clr: 1;
+        /** ledc_task_timer1_rst_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer1_rst_st_clr: 1;
+        /** ledc_task_timer2_rst_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer2_rst_st_clr: 1;
+        /** ledc_task_timer3_rst_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer3_rst_st_clr: 1;
+        /** ledc_task_timer0_resume_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer0_resume_st_clr: 1;
+        /** ledc_task_timer1_resume_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer1_resume_st_clr: 1;
+        /** ledc_task_timer2_resume_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer2_resume_st_clr: 1;
+        /** ledc_task_timer3_resume_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer3_resume_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st1_clr_reg_t;
+
+/** Type of task_st2_clr register
+ *  Tasks trigger status clear register
+ */
+typedef union {
+    struct {
+        /** ledc_task_timer0_pause_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer0_pause_st_clr: 1;
+        /** ledc_task_timer1_pause_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer1_pause_st_clr: 1;
+        /** ledc_task_timer2_pause_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer2_pause_st_clr: 1;
+        /** ledc_task_timer3_pause_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_timer3_pause_st_clr: 1;
+        /** ledc_task_gamma_restart_ch0_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_restart_ch0_st_clr: 1;
+        /** ledc_task_gamma_restart_ch1_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_restart_ch1_st_clr: 1;
+        /** ledc_task_gamma_restart_ch2_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_restart_ch2_st_clr: 1;
+        /** ledc_task_gamma_restart_ch3_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_restart_ch3_st_clr: 1;
+        /** ledc_task_gamma_restart_ch4_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_restart_ch4_st_clr: 1;
+        /** ledc_task_gamma_restart_ch5_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_restart_ch5_st_clr: 1;
+        /** ledc_task_gamma_restart_ch6_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_restart_ch6_st_clr: 1;
+        /** ledc_task_gamma_restart_ch7_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_restart_ch7_st_clr: 1;
+        /** ledc_task_gamma_pause_ch0_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_pause_ch0_st_clr: 1;
+        /** ledc_task_gamma_pause_ch1_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_pause_ch1_st_clr: 1;
+        /** ledc_task_gamma_pause_ch2_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_pause_ch2_st_clr: 1;
+        /** ledc_task_gamma_pause_ch3_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_pause_ch3_st_clr: 1;
+        /** ledc_task_gamma_pause_ch4_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_pause_ch4_st_clr: 1;
+        /** ledc_task_gamma_pause_ch5_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_pause_ch5_st_clr: 1;
+        /** ledc_task_gamma_pause_ch6_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_pause_ch6_st_clr: 1;
+        /** ledc_task_gamma_pause_ch7_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_pause_ch7_st_clr: 1;
+        /** ledc_task_gamma_resume_ch0_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_resume_ch0_st_clr: 1;
+        /** ledc_task_gamma_resume_ch1_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_resume_ch1_st_clr: 1;
+        /** ledc_task_gamma_resume_ch2_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_resume_ch2_st_clr: 1;
+        /** ledc_task_gamma_resume_ch3_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_resume_ch3_st_clr: 1;
+        /** ledc_task_gamma_resume_ch4_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_resume_ch4_st_clr: 1;
+        /** ledc_task_gamma_resume_ch5_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_resume_ch5_st_clr: 1;
+        /** ledc_task_gamma_resume_ch6_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_resume_ch6_st_clr: 1;
+        /** ledc_task_gamma_resume_ch7_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t ledc_task_gamma_resume_ch7_st_clr: 1;
+        /** tg0_task_cnt_start_timer0_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_task_cnt_start_timer0_st_clr: 1;
+        /** tg0_task_alarm_start_timer0_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_task_alarm_start_timer0_st_clr: 1;
+        /** tg0_task_cnt_stop_timer0_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_task_cnt_stop_timer0_st_clr: 1;
+        /** tg0_task_cnt_reload_timer0_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_task_cnt_reload_timer0_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st2_clr_reg_t;
+
+/** Type of task_st3_clr register
+ *  Tasks trigger status clear register
+ */
+typedef union {
+    struct {
+        /** tg0_task_cnt_cap_timer0_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_task_cnt_cap_timer0_st_clr: 1;
+        /** tg0_task_cnt_start_timer1_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_task_cnt_start_timer1_st_clr: 1;
+        /** tg0_task_alarm_start_timer1_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_task_alarm_start_timer1_st_clr: 1;
+        /** tg0_task_cnt_stop_timer1_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_task_cnt_stop_timer1_st_clr: 1;
+        /** tg0_task_cnt_reload_timer1_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_task_cnt_reload_timer1_st_clr: 1;
+        /** tg0_task_cnt_cap_timer1_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg0_task_cnt_cap_timer1_st_clr: 1;
+        /** tg1_task_cnt_start_timer0_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_task_cnt_start_timer0_st_clr: 1;
+        /** tg1_task_alarm_start_timer0_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_task_alarm_start_timer0_st_clr: 1;
+        /** tg1_task_cnt_stop_timer0_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_task_cnt_stop_timer0_st_clr: 1;
+        /** tg1_task_cnt_reload_timer0_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_task_cnt_reload_timer0_st_clr: 1;
+        /** tg1_task_cnt_cap_timer0_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_task_cnt_cap_timer0_st_clr: 1;
+        /** tg1_task_cnt_start_timer1_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_task_cnt_start_timer1_st_clr: 1;
+        /** tg1_task_alarm_start_timer1_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_task_alarm_start_timer1_st_clr: 1;
+        /** tg1_task_cnt_stop_timer1_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_task_cnt_stop_timer1_st_clr: 1;
+        /** tg1_task_cnt_reload_timer1_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_task_cnt_reload_timer1_st_clr: 1;
+        /** tg1_task_cnt_cap_timer1_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tg1_task_cnt_cap_timer1_st_clr: 1;
+        /** mcpwm0_task_cmpr0_a_up_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_cmpr0_a_up_st_clr: 1;
+        /** mcpwm0_task_cmpr1_a_up_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_cmpr1_a_up_st_clr: 1;
+        /** mcpwm0_task_cmpr2_a_up_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_cmpr2_a_up_st_clr: 1;
+        /** mcpwm0_task_cmpr0_b_up_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_cmpr0_b_up_st_clr: 1;
+        /** mcpwm0_task_cmpr1_b_up_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_cmpr1_b_up_st_clr: 1;
+        /** mcpwm0_task_cmpr2_b_up_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_cmpr2_b_up_st_clr: 1;
+        /** mcpwm0_task_gen_stop_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_gen_stop_st_clr: 1;
+        /** mcpwm0_task_timer0_syn_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_timer0_syn_st_clr: 1;
+        /** mcpwm0_task_timer1_syn_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_timer1_syn_st_clr: 1;
+        /** mcpwm0_task_timer2_syn_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_timer2_syn_st_clr: 1;
+        /** mcpwm0_task_timer0_period_up_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_timer0_period_up_st_clr: 1;
+        /** mcpwm0_task_timer1_period_up_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_timer1_period_up_st_clr: 1;
+        /** mcpwm0_task_timer2_period_up_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_timer2_period_up_st_clr: 1;
+        /** mcpwm0_task_tz0_ost_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_tz0_ost_st_clr: 1;
+        /** mcpwm0_task_tz1_ost_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_tz1_ost_st_clr: 1;
+        /** mcpwm0_task_tz2_ost_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_tz2_ost_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st3_clr_reg_t;
+
+/** Type of task_st4_clr register
+ *  Tasks trigger status clear register
+ */
+typedef union {
+    struct {
+        /** mcpwm0_task_clr0_ost_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_clr0_ost_st_clr: 1;
+        /** mcpwm0_task_clr1_ost_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_clr1_ost_st_clr: 1;
+        /** mcpwm0_task_clr2_ost_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_clr2_ost_st_clr: 1;
+        /** mcpwm0_task_cap0_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_cap0_st_clr: 1;
+        /** mcpwm0_task_cap1_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_cap1_st_clr: 1;
+        /** mcpwm0_task_cap2_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm0_task_cap2_st_clr: 1;
+        /** mcpwm1_task_cmpr0_a_up_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_cmpr0_a_up_st_clr: 1;
+        /** mcpwm1_task_cmpr1_a_up_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_cmpr1_a_up_st_clr: 1;
+        /** mcpwm1_task_cmpr2_a_up_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_cmpr2_a_up_st_clr: 1;
+        /** mcpwm1_task_cmpr0_b_up_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_cmpr0_b_up_st_clr: 1;
+        /** mcpwm1_task_cmpr1_b_up_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_cmpr1_b_up_st_clr: 1;
+        /** mcpwm1_task_cmpr2_b_up_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_cmpr2_b_up_st_clr: 1;
+        /** mcpwm1_task_gen_stop_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_gen_stop trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_gen_stop_st_clr: 1;
+        /** mcpwm1_task_timer0_syn_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_timer0_syn_st_clr: 1;
+        /** mcpwm1_task_timer1_syn_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_timer1_syn_st_clr: 1;
+        /** mcpwm1_task_timer2_syn_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_timer2_syn_st_clr: 1;
+        /** mcpwm1_task_timer0_period_up_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_timer0_period_up_st_clr: 1;
+        /** mcpwm1_task_timer1_period_up_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_timer1_period_up_st_clr: 1;
+        /** mcpwm1_task_timer2_period_up_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_timer2_period_up_st_clr: 1;
+        /** mcpwm1_task_tz0_ost_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_tz0_ost_st_clr: 1;
+        /** mcpwm1_task_tz1_ost_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_tz1_ost_st_clr: 1;
+        /** mcpwm1_task_tz2_ost_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_tz2_ost_st_clr: 1;
+        /** mcpwm1_task_clr0_ost_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_clr0_ost_st_clr: 1;
+        /** mcpwm1_task_clr1_ost_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_clr1_ost_st_clr: 1;
+        /** mcpwm1_task_clr2_ost_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_clr2_ost_st_clr: 1;
+        /** mcpwm1_task_cap0_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_cap0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_cap0_st_clr: 1;
+        /** mcpwm1_task_cap1_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_cap1 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_cap1_st_clr: 1;
+        /** mcpwm1_task_cap2_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear MCPWM1_task_cap2 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t mcpwm1_task_cap2_st_clr: 1;
+        /** adc_task_sample0_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t adc_task_sample0_st_clr: 1;
+        /** adc_task_sample1_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t adc_task_sample1_st_clr: 1;
+        /** adc_task_start0_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t adc_task_start0_st_clr: 1;
+        /** adc_task_stop0_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t adc_task_stop0_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st4_clr_reg_t;
+
+/** Type of task_st5_clr register
+ *  Tasks trigger status clear register
+ */
+typedef union {
+    struct {
+        /** regdma_task_start0_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t regdma_task_start0_st_clr: 1;
+        /** regdma_task_start1_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t regdma_task_start1_st_clr: 1;
+        /** regdma_task_start2_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t regdma_task_start2_st_clr: 1;
+        /** regdma_task_start3_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t regdma_task_start3_st_clr: 1;
+        /** tmpsnsr_task_start_sample_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tmpsnsr_task_start_sample_st_clr: 1;
+        /** tmpsnsr_task_stop_sample_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t tmpsnsr_task_stop_sample_st_clr: 1;
+        /** i2s0_task_start_rx_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s0_task_start_rx_st_clr: 1;
+        /** i2s0_task_start_tx_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s0_task_start_tx_st_clr: 1;
+        /** i2s0_task_stop_rx_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s0_task_stop_rx_st_clr: 1;
+        /** i2s0_task_stop_tx_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s0_task_stop_tx_st_clr: 1;
+        /** i2s1_task_start_rx_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear I2S1_task_start_rx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s1_task_start_rx_st_clr: 1;
+        /** i2s1_task_start_tx_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear I2S1_task_start_tx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s1_task_start_tx_st_clr: 1;
+        /** i2s1_task_stop_rx_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear I2S1_task_stop_rx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s1_task_stop_rx_st_clr: 1;
+        /** i2s1_task_stop_tx_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear I2S1_task_stop_tx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s1_task_stop_tx_st_clr: 1;
+        /** i2s2_task_start_rx_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear I2S2_task_start_rx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s2_task_start_rx_st_clr: 1;
+        /** i2s2_task_start_tx_st_clr : WT; bitpos: [15]; default: 0;
+         *  Configures whether or not to clear I2S2_task_start_tx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s2_task_start_tx_st_clr: 1;
+        /** i2s2_task_stop_rx_st_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether or not to clear I2S2_task_stop_rx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s2_task_stop_rx_st_clr: 1;
+        /** i2s2_task_stop_tx_st_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether or not to clear I2S2_task_stop_tx trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t i2s2_task_stop_tx_st_clr: 1;
+        /** ulp_task_wakeup_cpu_st_clr : WT; bitpos: [18]; default: 0;
+         *  Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t ulp_task_wakeup_cpu_st_clr: 1;
+        /** ulp_task_int_cpu_st_clr : WT; bitpos: [19]; default: 0;
+         *  Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t ulp_task_int_cpu_st_clr: 1;
+        /** rtc_task_start_st_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t rtc_task_start_st_clr: 1;
+        /** rtc_task_stop_st_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t rtc_task_stop_st_clr: 1;
+        /** rtc_task_clr_st_clr : WT; bitpos: [22]; default: 0;
+         *  Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No
+         *  effect\\1: Clear
+         */
+        uint32_t rtc_task_clr_st_clr: 1;
+        /** rtc_task_triggerflw_st_clr : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t rtc_task_triggerflw_st_clr: 1;
+        /** pdma_ahb_task_in_start_ch0_st_clr : WT; bitpos: [24]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_task_in_start_ch0_st_clr: 1;
+        /** pdma_ahb_task_in_start_ch1_st_clr : WT; bitpos: [25]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_task_in_start_ch1_st_clr: 1;
+        /** pdma_ahb_task_in_start_ch2_st_clr : WT; bitpos: [26]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_task_in_start_ch2_st_clr: 1;
+        /** pdma_ahb_task_out_start_ch0_st_clr : WT; bitpos: [27]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_task_out_start_ch0_st_clr: 1;
+        /** pdma_ahb_task_out_start_ch1_st_clr : WT; bitpos: [28]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_task_out_start_ch1_st_clr: 1;
+        /** pdma_ahb_task_out_start_ch2_st_clr : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_ahb_task_out_start_ch2_st_clr: 1;
+        /** pdma_axi_task_in_start_ch0_st_clr : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_task_in_start_ch0_st_clr: 1;
+        /** pdma_axi_task_in_start_ch1_st_clr : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_task_in_start_ch1_st_clr: 1;
+    };
+    uint32_t val;
+} soc_etm_task_st5_clr_reg_t;
+
+/** Type of task_st6_clr register
+ *  Tasks trigger status clear register
+ */
+typedef union {
+    struct {
+        /** pdma_axi_task_in_start_ch2_st_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_task_in_start_ch2_st_clr: 1;
+        /** pdma_axi_task_out_start_ch0_st_clr : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_task_out_start_ch0_st_clr: 1;
+        /** pdma_axi_task_out_start_ch1_st_clr : WT; bitpos: [2]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_task_out_start_ch1_st_clr: 1;
+        /** pdma_axi_task_out_start_ch2_st_clr : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t pdma_axi_task_out_start_ch2_st_clr: 1;
+        /** pmu_task_sleep_req_st_clr : WT; bitpos: [4]; default: 0;
+         *  Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid,
+         *  No effect\\1: Clear
+         */
+        uint32_t pmu_task_sleep_req_st_clr: 1;
+        /** dma2d_task_in_start_ch0_st_clr : WT; bitpos: [5]; default: 0;
+         *  Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_task_in_start_ch0_st_clr: 1;
+        /** dma2d_task_in_start_ch1_st_clr : WT; bitpos: [6]; default: 0;
+         *  Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_task_in_start_ch1_st_clr: 1;
+        /** dma2d_task_in_dscr_ready_ch0_st_clr : WT; bitpos: [7]; default: 0;
+         *  Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_task_in_dscr_ready_ch0_st_clr: 1;
+        /** dma2d_task_in_dscr_ready_ch1_st_clr : WT; bitpos: [8]; default: 0;
+         *  Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_task_in_dscr_ready_ch1_st_clr: 1;
+        /** dma2d_task_out_start_ch0_st_clr : WT; bitpos: [9]; default: 0;
+         *  Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_task_out_start_ch0_st_clr: 1;
+        /** dma2d_task_out_start_ch1_st_clr : WT; bitpos: [10]; default: 0;
+         *  Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_task_out_start_ch1_st_clr: 1;
+        /** dma2d_task_out_start_ch2_st_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.\\0:
+         *  Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_task_out_start_ch2_st_clr: 1;
+        /** dma2d_task_out_dscr_ready_ch0_st_clr : WT; bitpos: [12]; default: 0;
+         *  Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_task_out_dscr_ready_ch0_st_clr: 1;
+        /** dma2d_task_out_dscr_ready_ch1_st_clr : WT; bitpos: [13]; default: 0;
+         *  Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_task_out_dscr_ready_ch1_st_clr: 1;
+        /** dma2d_task_out_dscr_ready_ch2_st_clr : WT; bitpos: [14]; default: 0;
+         *  Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger
+         *  status.\\0: Invalid, No effect\\1: Clear
+         */
+        uint32_t dma2d_task_out_dscr_ready_ch2_st_clr: 1;
+        uint32_t reserved_15: 17;
+    };
+    uint32_t val;
+} soc_etm_task_st6_clr_reg_t;
+
+/** Type of clk_en register
+ *  ETM clock enable register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
+         *  when application writes registers\\1: Force open the clock gate for register
+         */
+        uint32_t clk_en: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} soc_etm_clk_en_reg_t;
+
+/** Group: Version Register */
+/** Type of date register
+ *  ETM date register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36712497;
+         *  Configures the version.
+         */
+        uint32_t date: 28;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} soc_etm_date_reg_t;
+
+typedef struct soc_etm_dev_t {
+    volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0;
+    volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set;
+    volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr;
+    volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1;
+    volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
+    volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
+    volatile struct {
+        soc_etm_chn_evt_id_reg_t eid;
+        soc_etm_chn_task_id_reg_t tid;
+    } channel[50];
+    volatile soc_etm_evt_st0_reg_t evt_st0;
+    volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr;
+    volatile soc_etm_evt_st1_reg_t evt_st1;
+    volatile soc_etm_evt_st1_clr_reg_t evt_st1_clr;
+    volatile soc_etm_evt_st2_reg_t evt_st2;
+    volatile soc_etm_evt_st2_clr_reg_t evt_st2_clr;
+    volatile soc_etm_evt_st3_reg_t evt_st3;
+    volatile soc_etm_evt_st3_clr_reg_t evt_st3_clr;
+    volatile soc_etm_evt_st4_reg_t evt_st4;
+    volatile soc_etm_evt_st4_clr_reg_t evt_st4_clr;
+    volatile soc_etm_evt_st5_reg_t evt_st5;
+    volatile soc_etm_evt_st5_clr_reg_t evt_st5_clr;
+    volatile soc_etm_evt_st6_reg_t evt_st6;
+    volatile soc_etm_evt_st6_clr_reg_t evt_st6_clr;
+    volatile soc_etm_evt_st7_reg_t evt_st7;
+    volatile soc_etm_evt_st7_clr_reg_t evt_st7_clr;
+    volatile soc_etm_task_st0_reg_t task_st0;
+    volatile soc_etm_task_st0_clr_reg_t task_st0_clr;
+    volatile soc_etm_task_st1_reg_t task_st1;
+    volatile soc_etm_task_st1_clr_reg_t task_st1_clr;
+    volatile soc_etm_task_st2_reg_t task_st2;
+    volatile soc_etm_task_st2_clr_reg_t task_st2_clr;
+    volatile soc_etm_task_st3_reg_t task_st3;
+    volatile soc_etm_task_st3_clr_reg_t task_st3_clr;
+    volatile soc_etm_task_st4_reg_t task_st4;
+    volatile soc_etm_task_st4_clr_reg_t task_st4_clr;
+    volatile soc_etm_task_st5_reg_t task_st5;
+    volatile soc_etm_task_st5_clr_reg_t task_st5_clr;
+    volatile soc_etm_task_st6_reg_t task_st6;
+    volatile soc_etm_task_st6_clr_reg_t task_st6_clr;
+    volatile soc_etm_clk_en_reg_t clk_en;
+    volatile soc_etm_date_reg_t date;
+} soc_etm_dev_t;
+
+extern soc_etm_dev_t SOC_ETM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(soc_etm_dev_t) == 0x228, "Invalid size of soc_etm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h
new file mode 100644
index 0000000000..e1f54ec7bb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h
@@ -0,0 +1,1481 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI1_MEM_C_CMD_REG register
+ *  SPI1 memory command register
+ */
+#define SPI1_MEM_C_CMD_REG (DR_REG_FLASH_SPI1_BASE + 0x0)
+/** SPI1_MEM_C_MST_ST : RO; bitpos: [3:0]; default: 0;
+ *  The current status of SPI1 master FSM.
+ */
+#define SPI1_MEM_C_MST_ST    0x0000000FU
+#define SPI1_MEM_C_MST_ST_M  (SPI1_MEM_C_MST_ST_V << SPI1_MEM_C_MST_ST_S)
+#define SPI1_MEM_C_MST_ST_V  0x0000000FU
+#define SPI1_MEM_C_MST_ST_S  0
+/** SPI1_MEM_C_SLV_ST : RO; bitpos: [7:4]; default: 0;
+ *  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state,
+ *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
+ *  6:write data state, 7: done state, 8: read data end state.
+ */
+#define SPI1_MEM_C_SLV_ST    0x0000000FU
+#define SPI1_MEM_C_SLV_ST_M  (SPI1_MEM_C_SLV_ST_V << SPI1_MEM_C_SLV_ST_S)
+#define SPI1_MEM_C_SLV_ST_V  0x0000000FU
+#define SPI1_MEM_C_SLV_ST_S  4
+/** SPI1_MEM_C_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
+ *  In user mode, it is set to indicate that program/erase operation will be triggered.
+ *  The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the
+ *  operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_PE    (BIT(17))
+#define SPI1_MEM_C_FLASH_PE_M  (SPI1_MEM_C_FLASH_PE_V << SPI1_MEM_C_FLASH_PE_S)
+#define SPI1_MEM_C_FLASH_PE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PE_S  17
+/** SPI1_MEM_C_USR : R/W/SC; bitpos: [18]; default: 0;
+ *  User define command enable.  An operation will be triggered when the bit is set.
+ *  The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_C_USR    (BIT(18))
+#define SPI1_MEM_C_USR_M  (SPI1_MEM_C_USR_V << SPI1_MEM_C_USR_S)
+#define SPI1_MEM_C_USR_V  0x00000001U
+#define SPI1_MEM_C_USR_S  18
+/** SPI1_MEM_C_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
+ *  Drive Flash into high performance mode.  The bit will be cleared once the operation
+ *  done.1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_HPM    (BIT(19))
+#define SPI1_MEM_C_FLASH_HPM_M  (SPI1_MEM_C_FLASH_HPM_V << SPI1_MEM_C_FLASH_HPM_S)
+#define SPI1_MEM_C_FLASH_HPM_V  0x00000001U
+#define SPI1_MEM_C_FLASH_HPM_S  19
+/** SPI1_MEM_C_FLASH_RES : R/W/SC; bitpos: [20]; default: 0;
+ *  This bit combined with reg_resandres bit releases Flash from the power-down state
+ *  or high performance mode and obtains the devices ID. The bit will be cleared once
+ *  the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_RES    (BIT(20))
+#define SPI1_MEM_C_FLASH_RES_M  (SPI1_MEM_C_FLASH_RES_V << SPI1_MEM_C_FLASH_RES_S)
+#define SPI1_MEM_C_FLASH_RES_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RES_S  20
+/** SPI1_MEM_C_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
+ *  Drive Flash into power down.  An operation will be triggered when the bit is set.
+ *  The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_DP    (BIT(21))
+#define SPI1_MEM_C_FLASH_DP_M  (SPI1_MEM_C_FLASH_DP_V << SPI1_MEM_C_FLASH_DP_S)
+#define SPI1_MEM_C_FLASH_DP_V  0x00000001U
+#define SPI1_MEM_C_FLASH_DP_S  21
+/** SPI1_MEM_C_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
+ *  Chip erase enable. Chip erase operation will be triggered when the bit is set. The
+ *  bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_CE    (BIT(22))
+#define SPI1_MEM_C_FLASH_CE_M  (SPI1_MEM_C_FLASH_CE_V << SPI1_MEM_C_FLASH_CE_S)
+#define SPI1_MEM_C_FLASH_CE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_CE_S  22
+/** SPI1_MEM_C_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
+ *  Block erase enable(32KB) .  Block erase operation will be triggered when the bit is
+ *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_BE    (BIT(23))
+#define SPI1_MEM_C_FLASH_BE_M  (SPI1_MEM_C_FLASH_BE_V << SPI1_MEM_C_FLASH_BE_S)
+#define SPI1_MEM_C_FLASH_BE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_BE_S  23
+/** SPI1_MEM_C_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
+ *  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
+ *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_SE    (BIT(24))
+#define SPI1_MEM_C_FLASH_SE_M  (SPI1_MEM_C_FLASH_SE_V << SPI1_MEM_C_FLASH_SE_S)
+#define SPI1_MEM_C_FLASH_SE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_SE_S  24
+/** SPI1_MEM_C_FLASH_PP : R/W/SC; bitpos: [25]; default: 0;
+ *  Page program enable(1 byte ~256 bytes data to be programmed). Page program
+ *  operation  will be triggered when the bit is set. The bit will be cleared once the
+ *  operation done .1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_PP    (BIT(25))
+#define SPI1_MEM_C_FLASH_PP_M  (SPI1_MEM_C_FLASH_PP_V << SPI1_MEM_C_FLASH_PP_S)
+#define SPI1_MEM_C_FLASH_PP_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PP_S  25
+/** SPI1_MEM_C_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
+ *  Write status register enable.   Write status operation  will be triggered when the
+ *  bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_WRSR    (BIT(26))
+#define SPI1_MEM_C_FLASH_WRSR_M  (SPI1_MEM_C_FLASH_WRSR_V << SPI1_MEM_C_FLASH_WRSR_S)
+#define SPI1_MEM_C_FLASH_WRSR_V  0x00000001U
+#define SPI1_MEM_C_FLASH_WRSR_S  26
+/** SPI1_MEM_C_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
+ *  Read status register-1.  Read status operation will be triggered when the bit is
+ *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_RDSR    (BIT(27))
+#define SPI1_MEM_C_FLASH_RDSR_M  (SPI1_MEM_C_FLASH_RDSR_V << SPI1_MEM_C_FLASH_RDSR_S)
+#define SPI1_MEM_C_FLASH_RDSR_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RDSR_S  27
+/** SPI1_MEM_C_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
+ *  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
+ *  cleared once the operation done. 1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_RDID    (BIT(28))
+#define SPI1_MEM_C_FLASH_RDID_M  (SPI1_MEM_C_FLASH_RDID_V << SPI1_MEM_C_FLASH_RDID_S)
+#define SPI1_MEM_C_FLASH_RDID_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RDID_S  28
+/** SPI1_MEM_C_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
+ *  Write flash disable. Write disable command will be sent when the bit is set. The
+ *  bit will be cleared once the operation done. 1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_WRDI    (BIT(29))
+#define SPI1_MEM_C_FLASH_WRDI_M  (SPI1_MEM_C_FLASH_WRDI_V << SPI1_MEM_C_FLASH_WRDI_S)
+#define SPI1_MEM_C_FLASH_WRDI_V  0x00000001U
+#define SPI1_MEM_C_FLASH_WRDI_S  29
+/** SPI1_MEM_C_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
+ *  Write flash enable.  Write enable command will be sent when the bit is set. The bit
+ *  will be cleared once the operation done. 1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_WREN    (BIT(30))
+#define SPI1_MEM_C_FLASH_WREN_M  (SPI1_MEM_C_FLASH_WREN_V << SPI1_MEM_C_FLASH_WREN_S)
+#define SPI1_MEM_C_FLASH_WREN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_WREN_S  30
+/** SPI1_MEM_C_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
+ *  Read flash enable. Read flash operation will be triggered when the bit is set. The
+ *  bit will be cleared once the operation done. 1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FLASH_READ    (BIT(31))
+#define SPI1_MEM_C_FLASH_READ_M  (SPI1_MEM_C_FLASH_READ_V << SPI1_MEM_C_FLASH_READ_S)
+#define SPI1_MEM_C_FLASH_READ_V  0x00000001U
+#define SPI1_MEM_C_FLASH_READ_S  31
+
+/** SPI1_MEM_C_ADDR_REG register
+ *  SPI1 address register
+ */
+#define SPI1_MEM_C_ADDR_REG (DR_REG_FLASH_SPI1_BASE + 0x4)
+/** SPI1_MEM_C_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
+ *  address, the bit24-bit31 are the byte length of a transfer.
+ */
+#define SPI1_MEM_C_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI1_MEM_C_USR_ADDR_VALUE_M  (SPI1_MEM_C_USR_ADDR_VALUE_V << SPI1_MEM_C_USR_ADDR_VALUE_S)
+#define SPI1_MEM_C_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI1_MEM_C_USR_ADDR_VALUE_S  0
+
+/** SPI1_MEM_C_CTRL_REG register
+ *  SPI1 control register.
+ */
+#define SPI1_MEM_C_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x8)
+/** SPI1_MEM_C_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
+ *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
+ *  level of SPI bus is output by the MSPI controller.
+ */
+#define SPI1_MEM_C_FDUMMY_RIN    (BIT(2))
+#define SPI1_MEM_C_FDUMMY_RIN_M  (SPI1_MEM_C_FDUMMY_RIN_V << SPI1_MEM_C_FDUMMY_RIN_S)
+#define SPI1_MEM_C_FDUMMY_RIN_V  0x00000001U
+#define SPI1_MEM_C_FDUMMY_RIN_S  2
+/** SPI1_MEM_C_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
+ *  In the dummy phase of a MSPI write data transfer when accesses to flash, the signal
+ *  level of SPI bus is output by the MSPI controller.
+ */
+#define SPI1_MEM_C_FDUMMY_WOUT    (BIT(3))
+#define SPI1_MEM_C_FDUMMY_WOUT_M  (SPI1_MEM_C_FDUMMY_WOUT_V << SPI1_MEM_C_FDUMMY_WOUT_S)
+#define SPI1_MEM_C_FDUMMY_WOUT_V  0x00000001U
+#define SPI1_MEM_C_FDUMMY_WOUT_S  3
+/** SPI1_MEM_C_FDOUT_OCT : HRO; bitpos: [4]; default: 0;
+ *  Apply 8 signals during write-data phase 1:enable 0: disable
+ */
+#define SPI1_MEM_C_FDOUT_OCT    (BIT(4))
+#define SPI1_MEM_C_FDOUT_OCT_M  (SPI1_MEM_C_FDOUT_OCT_V << SPI1_MEM_C_FDOUT_OCT_S)
+#define SPI1_MEM_C_FDOUT_OCT_V  0x00000001U
+#define SPI1_MEM_C_FDOUT_OCT_S  4
+/** SPI1_MEM_C_FDIN_OCT : HRO; bitpos: [5]; default: 0;
+ *  Apply 8 signals during read-data phase 1:enable 0: disable
+ */
+#define SPI1_MEM_C_FDIN_OCT    (BIT(5))
+#define SPI1_MEM_C_FDIN_OCT_M  (SPI1_MEM_C_FDIN_OCT_V << SPI1_MEM_C_FDIN_OCT_S)
+#define SPI1_MEM_C_FDIN_OCT_V  0x00000001U
+#define SPI1_MEM_C_FDIN_OCT_S  5
+/** SPI1_MEM_C_FADDR_OCT : HRO; bitpos: [6]; default: 0;
+ *  Apply 8 signals during address phase 1:enable 0: disable
+ */
+#define SPI1_MEM_C_FADDR_OCT    (BIT(6))
+#define SPI1_MEM_C_FADDR_OCT_M  (SPI1_MEM_C_FADDR_OCT_V << SPI1_MEM_C_FADDR_OCT_S)
+#define SPI1_MEM_C_FADDR_OCT_V  0x00000001U
+#define SPI1_MEM_C_FADDR_OCT_S  6
+/** SPI1_MEM_C_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
+ *  Apply 4 signals during command phase 1:enable 0: disable
+ */
+#define SPI1_MEM_C_FCMD_QUAD    (BIT(8))
+#define SPI1_MEM_C_FCMD_QUAD_M  (SPI1_MEM_C_FCMD_QUAD_V << SPI1_MEM_C_FCMD_QUAD_S)
+#define SPI1_MEM_C_FCMD_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FCMD_QUAD_S  8
+/** SPI1_MEM_C_FCMD_OCT : HRO; bitpos: [9]; default: 0;
+ *  Apply 8 signals during command phase 1:enable 0: disable
+ */
+#define SPI1_MEM_C_FCMD_OCT    (BIT(9))
+#define SPI1_MEM_C_FCMD_OCT_M  (SPI1_MEM_C_FCMD_OCT_V << SPI1_MEM_C_FCMD_OCT_S)
+#define SPI1_MEM_C_FCMD_OCT_V  0x00000001U
+#define SPI1_MEM_C_FCMD_OCT_S  9
+/** SPI1_MEM_C_FCS_CRC_EN : HRO; bitpos: [10]; default: 0;
+ *  For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
+ *  low.
+ */
+#define SPI1_MEM_C_FCS_CRC_EN    (BIT(10))
+#define SPI1_MEM_C_FCS_CRC_EN_M  (SPI1_MEM_C_FCS_CRC_EN_V << SPI1_MEM_C_FCS_CRC_EN_S)
+#define SPI1_MEM_C_FCS_CRC_EN_V  0x00000001U
+#define SPI1_MEM_C_FCS_CRC_EN_S  10
+/** SPI1_MEM_C_TX_CRC_EN : HRO; bitpos: [11]; default: 0;
+ *  For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+ */
+#define SPI1_MEM_C_TX_CRC_EN    (BIT(11))
+#define SPI1_MEM_C_TX_CRC_EN_M  (SPI1_MEM_C_TX_CRC_EN_V << SPI1_MEM_C_TX_CRC_EN_S)
+#define SPI1_MEM_C_TX_CRC_EN_V  0x00000001U
+#define SPI1_MEM_C_TX_CRC_EN_S  11
+/** SPI1_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
+ *  This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout
+ *  and spi1_mem_c_fread_dout. 1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FASTRD_MODE    (BIT(13))
+#define SPI1_MEM_C_FASTRD_MODE_M  (SPI1_MEM_C_FASTRD_MODE_V << SPI1_MEM_C_FASTRD_MODE_S)
+#define SPI1_MEM_C_FASTRD_MODE_V  0x00000001U
+#define SPI1_MEM_C_FASTRD_MODE_S  13
+/** SPI1_MEM_C_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+ *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FREAD_DUAL    (BIT(14))
+#define SPI1_MEM_C_FREAD_DUAL_M  (SPI1_MEM_C_FREAD_DUAL_V << SPI1_MEM_C_FREAD_DUAL_S)
+#define SPI1_MEM_C_FREAD_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FREAD_DUAL_S  14
+/** SPI1_MEM_C_RESANDRES : R/W; bitpos: [15]; default: 1;
+ *  The Device ID is read out to SPI1_MEM_C_RD_STATUS register,  this bit combine with
+ *  spi1_mem_c_flash_res bit. 1: enable 0: disable.
+ */
+#define SPI1_MEM_C_RESANDRES    (BIT(15))
+#define SPI1_MEM_C_RESANDRES_M  (SPI1_MEM_C_RESANDRES_V << SPI1_MEM_C_RESANDRES_S)
+#define SPI1_MEM_C_RESANDRES_V  0x00000001U
+#define SPI1_MEM_C_RESANDRES_S  15
+/** SPI1_MEM_C_Q_POL : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to set MISO line polarity, 1: high 0, low
+ */
+#define SPI1_MEM_C_Q_POL    (BIT(18))
+#define SPI1_MEM_C_Q_POL_M  (SPI1_MEM_C_Q_POL_V << SPI1_MEM_C_Q_POL_S)
+#define SPI1_MEM_C_Q_POL_V  0x00000001U
+#define SPI1_MEM_C_Q_POL_S  18
+/** SPI1_MEM_C_D_POL : R/W; bitpos: [19]; default: 1;
+ *  The bit is used to set MOSI line polarity, 1: high 0, low
+ */
+#define SPI1_MEM_C_D_POL    (BIT(19))
+#define SPI1_MEM_C_D_POL_M  (SPI1_MEM_C_D_POL_V << SPI1_MEM_C_D_POL_S)
+#define SPI1_MEM_C_D_POL_V  0x00000001U
+#define SPI1_MEM_C_D_POL_S  19
+/** SPI1_MEM_C_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
+ *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FREAD_QUAD    (BIT(20))
+#define SPI1_MEM_C_FREAD_QUAD_M  (SPI1_MEM_C_FREAD_QUAD_V << SPI1_MEM_C_FREAD_QUAD_S)
+#define SPI1_MEM_C_FREAD_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FREAD_QUAD_S  20
+/** SPI1_MEM_C_WP_REG : R/W; bitpos: [21]; default: 1;
+ *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
+ */
+#define SPI1_MEM_C_WP_REG    (BIT(21))
+#define SPI1_MEM_C_WP_REG_M  (SPI1_MEM_C_WP_REG_V << SPI1_MEM_C_WP_REG_S)
+#define SPI1_MEM_C_WP_REG_V  0x00000001U
+#define SPI1_MEM_C_WP_REG_S  21
+/** SPI1_MEM_C_WRSR_2B : R/W; bitpos: [22]; default: 0;
+ *  two bytes data will be written to status register when it is set. 1: enable 0:
+ *  disable.
+ */
+#define SPI1_MEM_C_WRSR_2B    (BIT(22))
+#define SPI1_MEM_C_WRSR_2B_M  (SPI1_MEM_C_WRSR_2B_V << SPI1_MEM_C_WRSR_2B_S)
+#define SPI1_MEM_C_WRSR_2B_V  0x00000001U
+#define SPI1_MEM_C_WRSR_2B_S  22
+/** SPI1_MEM_C_FREAD_DIO : R/W; bitpos: [23]; default: 0;
+ *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
+ *  0: disable.
+ */
+#define SPI1_MEM_C_FREAD_DIO    (BIT(23))
+#define SPI1_MEM_C_FREAD_DIO_M  (SPI1_MEM_C_FREAD_DIO_V << SPI1_MEM_C_FREAD_DIO_S)
+#define SPI1_MEM_C_FREAD_DIO_V  0x00000001U
+#define SPI1_MEM_C_FREAD_DIO_S  23
+/** SPI1_MEM_C_FREAD_QIO : R/W; bitpos: [24]; default: 0;
+ *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
+ *  0: disable.
+ */
+#define SPI1_MEM_C_FREAD_QIO    (BIT(24))
+#define SPI1_MEM_C_FREAD_QIO_M  (SPI1_MEM_C_FREAD_QIO_V << SPI1_MEM_C_FREAD_QIO_S)
+#define SPI1_MEM_C_FREAD_QIO_V  0x00000001U
+#define SPI1_MEM_C_FREAD_QIO_S  24
+
+/** SPI1_MEM_C_CTRL1_REG register
+ *  SPI1 control1 register.
+ */
+#define SPI1_MEM_C_CTRL1_REG (DR_REG_FLASH_SPI1_BASE + 0xc)
+/** SPI1_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+ *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+ *  SPI clock is always on.
+ */
+#define SPI1_MEM_C_CLK_MODE    0x00000003U
+#define SPI1_MEM_C_CLK_MODE_M  (SPI1_MEM_C_CLK_MODE_V << SPI1_MEM_C_CLK_MODE_S)
+#define SPI1_MEM_C_CLK_MODE_V  0x00000003U
+#define SPI1_MEM_C_CLK_MODE_S  0
+/** SPI1_MEM_C_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
+ *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512)
+ *  SPI_CLK cycles.
+ */
+#define SPI1_MEM_C_CS_HOLD_DLY_RES    0x000003FFU
+#define SPI1_MEM_C_CS_HOLD_DLY_RES_M  (SPI1_MEM_C_CS_HOLD_DLY_RES_V << SPI1_MEM_C_CS_HOLD_DLY_RES_S)
+#define SPI1_MEM_C_CS_HOLD_DLY_RES_V  0x000003FFU
+#define SPI1_MEM_C_CS_HOLD_DLY_RES_S  2
+
+/** SPI1_MEM_C_CTRL2_REG register
+ *  SPI1 control2 register.
+ */
+#define SPI1_MEM_C_CTRL2_REG (DR_REG_FLASH_SPI1_BASE + 0x10)
+/** SPI1_MEM_C_SYNC_RESET : WT; bitpos: [31]; default: 0;
+ *  The FSM will be reset.
+ */
+#define SPI1_MEM_C_SYNC_RESET    (BIT(31))
+#define SPI1_MEM_C_SYNC_RESET_M  (SPI1_MEM_C_SYNC_RESET_V << SPI1_MEM_C_SYNC_RESET_S)
+#define SPI1_MEM_C_SYNC_RESET_V  0x00000001U
+#define SPI1_MEM_C_SYNC_RESET_S  31
+
+/** SPI1_MEM_C_CLOCK_REG register
+ *  SPI1 clock division control register.
+ */
+#define SPI1_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI1_BASE + 0x14)
+/** SPI1_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+ *  In the master mode it must be equal to spi1_mem_c_clkcnt_N.
+ */
+#define SPI1_MEM_C_CLKCNT_L    0x000000FFU
+#define SPI1_MEM_C_CLKCNT_L_M  (SPI1_MEM_C_CLKCNT_L_V << SPI1_MEM_C_CLKCNT_L_S)
+#define SPI1_MEM_C_CLKCNT_L_V  0x000000FFU
+#define SPI1_MEM_C_CLKCNT_L_S  0
+/** SPI1_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+ *  In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1).
+ */
+#define SPI1_MEM_C_CLKCNT_H    0x000000FFU
+#define SPI1_MEM_C_CLKCNT_H_M  (SPI1_MEM_C_CLKCNT_H_V << SPI1_MEM_C_CLKCNT_H_S)
+#define SPI1_MEM_C_CLKCNT_H_V  0x000000FFU
+#define SPI1_MEM_C_CLKCNT_H_S  8
+/** SPI1_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+ *  In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is
+ *  system/(spi1_mem_c_clkcnt_N+1)
+ */
+#define SPI1_MEM_C_CLKCNT_N    0x000000FFU
+#define SPI1_MEM_C_CLKCNT_N_M  (SPI1_MEM_C_CLKCNT_N_V << SPI1_MEM_C_CLKCNT_N_S)
+#define SPI1_MEM_C_CLKCNT_N_V  0x000000FFU
+#define SPI1_MEM_C_CLKCNT_N_S  16
+/** SPI1_MEM_C_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define SPI1_MEM_C_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI1_MEM_C_CLK_EQU_SYSCLK_M  (SPI1_MEM_C_CLK_EQU_SYSCLK_V << SPI1_MEM_C_CLK_EQU_SYSCLK_S)
+#define SPI1_MEM_C_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI1_MEM_C_CLK_EQU_SYSCLK_S  31
+
+/** SPI1_MEM_C_USER_REG register
+ *  SPI1 user register.
+ */
+#define SPI1_MEM_C_USER_REG (DR_REG_FLASH_SPI1_BASE + 0x18)
+/** SPI1_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode.
+ */
+#define SPI1_MEM_C_CK_OUT_EDGE    (BIT(9))
+#define SPI1_MEM_C_CK_OUT_EDGE_M  (SPI1_MEM_C_CK_OUT_EDGE_V << SPI1_MEM_C_CK_OUT_EDGE_S)
+#define SPI1_MEM_C_CK_OUT_EDGE_V  0x00000001U
+#define SPI1_MEM_C_CK_OUT_EDGE_S  9
+/** SPI1_MEM_C_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+ *  In the write operations read-data phase apply 2 signals
+ */
+#define SPI1_MEM_C_FWRITE_DUAL    (BIT(12))
+#define SPI1_MEM_C_FWRITE_DUAL_M  (SPI1_MEM_C_FWRITE_DUAL_V << SPI1_MEM_C_FWRITE_DUAL_S)
+#define SPI1_MEM_C_FWRITE_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_DUAL_S  12
+/** SPI1_MEM_C_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+ *  In the write operations read-data phase apply 4 signals
+ */
+#define SPI1_MEM_C_FWRITE_QUAD    (BIT(13))
+#define SPI1_MEM_C_FWRITE_QUAD_M  (SPI1_MEM_C_FWRITE_QUAD_V << SPI1_MEM_C_FWRITE_QUAD_S)
+#define SPI1_MEM_C_FWRITE_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_QUAD_S  13
+/** SPI1_MEM_C_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
+ *  In the write operations address phase and read-data phase apply 2 signals.
+ */
+#define SPI1_MEM_C_FWRITE_DIO    (BIT(14))
+#define SPI1_MEM_C_FWRITE_DIO_M  (SPI1_MEM_C_FWRITE_DIO_V << SPI1_MEM_C_FWRITE_DIO_S)
+#define SPI1_MEM_C_FWRITE_DIO_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_DIO_S  14
+/** SPI1_MEM_C_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
+ *  In the write operations address phase and read-data phase apply 4 signals.
+ */
+#define SPI1_MEM_C_FWRITE_QIO    (BIT(15))
+#define SPI1_MEM_C_FWRITE_QIO_M  (SPI1_MEM_C_FWRITE_QIO_V << SPI1_MEM_C_FWRITE_QIO_S)
+#define SPI1_MEM_C_FWRITE_QIO_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_QIO_S  15
+/** SPI1_MEM_C_USR_MISO_HIGHPART : HRO; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
+ *  enable 0: disable.
+ */
+#define SPI1_MEM_C_USR_MISO_HIGHPART    (BIT(24))
+#define SPI1_MEM_C_USR_MISO_HIGHPART_M  (SPI1_MEM_C_USR_MISO_HIGHPART_V << SPI1_MEM_C_USR_MISO_HIGHPART_S)
+#define SPI1_MEM_C_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI1_MEM_C_USR_MISO_HIGHPART_S  24
+/** SPI1_MEM_C_USR_MOSI_HIGHPART : HRO; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
+ *  enable 0: disable.
+ */
+#define SPI1_MEM_C_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI1_MEM_C_USR_MOSI_HIGHPART_M  (SPI1_MEM_C_USR_MOSI_HIGHPART_V << SPI1_MEM_C_USR_MOSI_HIGHPART_S)
+#define SPI1_MEM_C_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI1_MEM_C_USR_MOSI_HIGHPART_S  25
+/** SPI1_MEM_C_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+ *  SPI clock is disable in dummy phase when the bit is enable.
+ */
+#define SPI1_MEM_C_USR_DUMMY_IDLE    (BIT(26))
+#define SPI1_MEM_C_USR_DUMMY_IDLE_M  (SPI1_MEM_C_USR_DUMMY_IDLE_V << SPI1_MEM_C_USR_DUMMY_IDLE_S)
+#define SPI1_MEM_C_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI1_MEM_C_USR_DUMMY_IDLE_S  26
+/** SPI1_MEM_C_USR_MOSI : R/W; bitpos: [27]; default: 0;
+ *  This bit enable the write-data phase of an operation.
+ */
+#define SPI1_MEM_C_USR_MOSI    (BIT(27))
+#define SPI1_MEM_C_USR_MOSI_M  (SPI1_MEM_C_USR_MOSI_V << SPI1_MEM_C_USR_MOSI_S)
+#define SPI1_MEM_C_USR_MOSI_V  0x00000001U
+#define SPI1_MEM_C_USR_MOSI_S  27
+/** SPI1_MEM_C_USR_MISO : R/W; bitpos: [28]; default: 0;
+ *  This bit enable the read-data phase of an operation.
+ */
+#define SPI1_MEM_C_USR_MISO    (BIT(28))
+#define SPI1_MEM_C_USR_MISO_M  (SPI1_MEM_C_USR_MISO_V << SPI1_MEM_C_USR_MISO_S)
+#define SPI1_MEM_C_USR_MISO_V  0x00000001U
+#define SPI1_MEM_C_USR_MISO_S  28
+/** SPI1_MEM_C_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+ *  This bit enable the dummy phase of an operation.
+ */
+#define SPI1_MEM_C_USR_DUMMY    (BIT(29))
+#define SPI1_MEM_C_USR_DUMMY_M  (SPI1_MEM_C_USR_DUMMY_V << SPI1_MEM_C_USR_DUMMY_S)
+#define SPI1_MEM_C_USR_DUMMY_V  0x00000001U
+#define SPI1_MEM_C_USR_DUMMY_S  29
+/** SPI1_MEM_C_USR_ADDR : R/W; bitpos: [30]; default: 0;
+ *  This bit enable the address phase of an operation.
+ */
+#define SPI1_MEM_C_USR_ADDR    (BIT(30))
+#define SPI1_MEM_C_USR_ADDR_M  (SPI1_MEM_C_USR_ADDR_V << SPI1_MEM_C_USR_ADDR_S)
+#define SPI1_MEM_C_USR_ADDR_V  0x00000001U
+#define SPI1_MEM_C_USR_ADDR_S  30
+/** SPI1_MEM_C_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+ *  This bit enable the command phase of an operation.
+ */
+#define SPI1_MEM_C_USR_COMMAND    (BIT(31))
+#define SPI1_MEM_C_USR_COMMAND_M  (SPI1_MEM_C_USR_COMMAND_V << SPI1_MEM_C_USR_COMMAND_S)
+#define SPI1_MEM_C_USR_COMMAND_V  0x00000001U
+#define SPI1_MEM_C_USR_COMMAND_S  31
+
+/** SPI1_MEM_C_USER1_REG register
+ *  SPI1 user1 register.
+ */
+#define SPI1_MEM_C_USER1_REG (DR_REG_FLASH_SPI1_BASE + 0x1c)
+/** SPI1_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
+ *  The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be
+ *  (cycle_num-1).
+ */
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_M  (SPI1_MEM_C_USR_DUMMY_CYCLELEN_V << SPI1_MEM_C_USR_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_S  0
+/** SPI1_MEM_C_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
+ *  The length in bits of address phase. The register value shall be (bit_num-1).
+ */
+#define SPI1_MEM_C_USR_ADDR_BITLEN    0x0000003FU
+#define SPI1_MEM_C_USR_ADDR_BITLEN_M  (SPI1_MEM_C_USR_ADDR_BITLEN_V << SPI1_MEM_C_USR_ADDR_BITLEN_S)
+#define SPI1_MEM_C_USR_ADDR_BITLEN_V  0x0000003FU
+#define SPI1_MEM_C_USR_ADDR_BITLEN_S  26
+
+/** SPI1_MEM_C_USER2_REG register
+ *  SPI1 user2 register.
+ */
+#define SPI1_MEM_C_USER2_REG (DR_REG_FLASH_SPI1_BASE + 0x20)
+/** SPI1_MEM_C_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  The value of  command.
+ */
+#define SPI1_MEM_C_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI1_MEM_C_USR_COMMAND_VALUE_M  (SPI1_MEM_C_USR_COMMAND_VALUE_V << SPI1_MEM_C_USR_COMMAND_VALUE_S)
+#define SPI1_MEM_C_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI1_MEM_C_USR_COMMAND_VALUE_S  0
+/** SPI1_MEM_C_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+ *  The length in bits of command phase. The register value shall be (bit_num-1)
+ */
+#define SPI1_MEM_C_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI1_MEM_C_USR_COMMAND_BITLEN_M  (SPI1_MEM_C_USR_COMMAND_BITLEN_V << SPI1_MEM_C_USR_COMMAND_BITLEN_S)
+#define SPI1_MEM_C_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI1_MEM_C_USR_COMMAND_BITLEN_S  28
+
+/** SPI1_MEM_C_MOSI_DLEN_REG register
+ *  SPI1 send data bit length control register.
+ */
+#define SPI1_MEM_C_MOSI_DLEN_REG (DR_REG_FLASH_SPI1_BASE + 0x24)
+/** SPI1_MEM_C_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+ *  The length in bits of write-data. The register value shall be (bit_num-1).
+ */
+#define SPI1_MEM_C_USR_MOSI_DBITLEN    0x000003FFU
+#define SPI1_MEM_C_USR_MOSI_DBITLEN_M  (SPI1_MEM_C_USR_MOSI_DBITLEN_V << SPI1_MEM_C_USR_MOSI_DBITLEN_S)
+#define SPI1_MEM_C_USR_MOSI_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_C_USR_MOSI_DBITLEN_S  0
+
+/** SPI1_MEM_C_MISO_DLEN_REG register
+ *  SPI1 receive data bit length control register.
+ */
+#define SPI1_MEM_C_MISO_DLEN_REG (DR_REG_FLASH_SPI1_BASE + 0x28)
+/** SPI1_MEM_C_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+ *  The length in bits of  read-data. The register value shall be (bit_num-1).
+ */
+#define SPI1_MEM_C_USR_MISO_DBITLEN    0x000003FFU
+#define SPI1_MEM_C_USR_MISO_DBITLEN_M  (SPI1_MEM_C_USR_MISO_DBITLEN_V << SPI1_MEM_C_USR_MISO_DBITLEN_S)
+#define SPI1_MEM_C_USR_MISO_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_C_USR_MISO_DBITLEN_S  0
+
+/** SPI1_MEM_C_RD_STATUS_REG register
+ *  SPI1 status register.
+ */
+#define SPI1_MEM_C_RD_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0x2c)
+/** SPI1_MEM_C_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
+ *  The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit.
+ */
+#define SPI1_MEM_C_STATUS    0x0000FFFFU
+#define SPI1_MEM_C_STATUS_M  (SPI1_MEM_C_STATUS_V << SPI1_MEM_C_STATUS_S)
+#define SPI1_MEM_C_STATUS_V  0x0000FFFFU
+#define SPI1_MEM_C_STATUS_S  0
+/** SPI1_MEM_C_WB_MODE : R/W; bitpos: [23:16]; default: 0;
+ *  Mode bits in the flash fast read mode  it is combined with spi1_mem_c_fastrd_mode bit.
+ */
+#define SPI1_MEM_C_WB_MODE    0x000000FFU
+#define SPI1_MEM_C_WB_MODE_M  (SPI1_MEM_C_WB_MODE_V << SPI1_MEM_C_WB_MODE_S)
+#define SPI1_MEM_C_WB_MODE_V  0x000000FFU
+#define SPI1_MEM_C_WB_MODE_S  16
+
+/** SPI1_MEM_C_MISC_REG register
+ *  SPI1 misc register
+ */
+#define SPI1_MEM_C_MISC_REG (DR_REG_FLASH_SPI1_BASE + 0x34)
+/** SPI1_MEM_C_CS0_DIS : R/W; bitpos: [0]; default: 0;
+ *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
+ *  device, such as flash, external RAM and so on.
+ */
+#define SPI1_MEM_C_CS0_DIS    (BIT(0))
+#define SPI1_MEM_C_CS0_DIS_M  (SPI1_MEM_C_CS0_DIS_V << SPI1_MEM_C_CS0_DIS_S)
+#define SPI1_MEM_C_CS0_DIS_V  0x00000001U
+#define SPI1_MEM_C_CS0_DIS_S  0
+/** SPI1_MEM_C_CS1_DIS : R/W; bitpos: [1]; default: 1;
+ *  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
+ *  device, such as flash, external RAM and so on.
+ */
+#define SPI1_MEM_C_CS1_DIS    (BIT(1))
+#define SPI1_MEM_C_CS1_DIS_M  (SPI1_MEM_C_CS1_DIS_V << SPI1_MEM_C_CS1_DIS_S)
+#define SPI1_MEM_C_CS1_DIS_V  0x00000001U
+#define SPI1_MEM_C_CS1_DIS_S  1
+/** SPI1_MEM_C_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
+ *  1: spi clk line is high when idle     0: spi clk line is low when idle
+ */
+#define SPI1_MEM_C_CK_IDLE_EDGE    (BIT(9))
+#define SPI1_MEM_C_CK_IDLE_EDGE_M  (SPI1_MEM_C_CK_IDLE_EDGE_V << SPI1_MEM_C_CK_IDLE_EDGE_S)
+#define SPI1_MEM_C_CK_IDLE_EDGE_V  0x00000001U
+#define SPI1_MEM_C_CK_IDLE_EDGE_S  9
+/** SPI1_MEM_C_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
+ *  spi cs line keep low when the bit is set.
+ */
+#define SPI1_MEM_C_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI1_MEM_C_CS_KEEP_ACTIVE_M  (SPI1_MEM_C_CS_KEEP_ACTIVE_V << SPI1_MEM_C_CS_KEEP_ACTIVE_S)
+#define SPI1_MEM_C_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI1_MEM_C_CS_KEEP_ACTIVE_S  10
+
+/** SPI1_MEM_C_TX_CRC_REG register
+ *  SPI1 TX CRC data register.
+ */
+#define SPI1_MEM_C_TX_CRC_REG (DR_REG_FLASH_SPI1_BASE + 0x38)
+/** SPI1_MEM_C_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
+ *  For SPI1, the value of crc32.
+ */
+#define SPI1_MEM_C_TX_CRC_DATA    0xFFFFFFFFU
+#define SPI1_MEM_C_TX_CRC_DATA_M  (SPI1_MEM_C_TX_CRC_DATA_V << SPI1_MEM_C_TX_CRC_DATA_S)
+#define SPI1_MEM_C_TX_CRC_DATA_V  0xFFFFFFFFU
+#define SPI1_MEM_C_TX_CRC_DATA_S  0
+
+/** SPI1_MEM_C_CACHE_FCTRL_REG register
+ *  SPI1 bit mode control register.
+ */
+#define SPI1_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x3c)
+/** SPI1_MEM_C_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
+ *  For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
+ */
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_M  (SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S)
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V  0x00000001U
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S  1
+/** SPI1_MEM_C_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
+ *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
+ *  spi1_mem_c_fread_dio.
+ */
+#define SPI1_MEM_C_FDIN_DUAL    (BIT(3))
+#define SPI1_MEM_C_FDIN_DUAL_M  (SPI1_MEM_C_FDIN_DUAL_V << SPI1_MEM_C_FDIN_DUAL_S)
+#define SPI1_MEM_C_FDIN_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FDIN_DUAL_S  3
+/** SPI1_MEM_C_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
+ *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
+ *  with spi1_mem_c_fread_dio.
+ */
+#define SPI1_MEM_C_FDOUT_DUAL    (BIT(4))
+#define SPI1_MEM_C_FDOUT_DUAL_M  (SPI1_MEM_C_FDOUT_DUAL_V << SPI1_MEM_C_FDOUT_DUAL_S)
+#define SPI1_MEM_C_FDOUT_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FDOUT_DUAL_S  4
+/** SPI1_MEM_C_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+ *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
+ *  with spi1_mem_c_fread_dio.
+ */
+#define SPI1_MEM_C_FADDR_DUAL    (BIT(5))
+#define SPI1_MEM_C_FADDR_DUAL_M  (SPI1_MEM_C_FADDR_DUAL_V << SPI1_MEM_C_FADDR_DUAL_S)
+#define SPI1_MEM_C_FADDR_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FADDR_DUAL_S  5
+/** SPI1_MEM_C_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
+ *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+ *  with spi1_mem_c_fread_qio.
+ */
+#define SPI1_MEM_C_FDIN_QUAD    (BIT(6))
+#define SPI1_MEM_C_FDIN_QUAD_M  (SPI1_MEM_C_FDIN_QUAD_V << SPI1_MEM_C_FDIN_QUAD_S)
+#define SPI1_MEM_C_FDIN_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FDIN_QUAD_S  6
+/** SPI1_MEM_C_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
+ *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+ *  with spi1_mem_c_fread_qio.
+ */
+#define SPI1_MEM_C_FDOUT_QUAD    (BIT(7))
+#define SPI1_MEM_C_FDOUT_QUAD_M  (SPI1_MEM_C_FDOUT_QUAD_V << SPI1_MEM_C_FDOUT_QUAD_S)
+#define SPI1_MEM_C_FDOUT_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FDOUT_QUAD_S  7
+/** SPI1_MEM_C_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
+ *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+ *  with spi1_mem_c_fread_qio.
+ */
+#define SPI1_MEM_C_FADDR_QUAD    (BIT(8))
+#define SPI1_MEM_C_FADDR_QUAD_M  (SPI1_MEM_C_FADDR_QUAD_V << SPI1_MEM_C_FADDR_QUAD_S)
+#define SPI1_MEM_C_FADDR_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FADDR_QUAD_S  8
+
+/** SPI1_MEM_C_W0_REG register
+ *  SPI1 memory data buffer0
+ */
+#define SPI1_MEM_C_W0_REG (DR_REG_FLASH_SPI1_BASE + 0x58)
+/** SPI1_MEM_C_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF0    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF0_M  (SPI1_MEM_C_BUF0_V << SPI1_MEM_C_BUF0_S)
+#define SPI1_MEM_C_BUF0_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF0_S  0
+
+/** SPI1_MEM_C_W1_REG register
+ *  SPI1 memory data buffer1
+ */
+#define SPI1_MEM_C_W1_REG (DR_REG_FLASH_SPI1_BASE + 0x5c)
+/** SPI1_MEM_C_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF1    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF1_M  (SPI1_MEM_C_BUF1_V << SPI1_MEM_C_BUF1_S)
+#define SPI1_MEM_C_BUF1_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF1_S  0
+
+/** SPI1_MEM_C_W2_REG register
+ *  SPI1 memory data buffer2
+ */
+#define SPI1_MEM_C_W2_REG (DR_REG_FLASH_SPI1_BASE + 0x60)
+/** SPI1_MEM_C_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF2    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF2_M  (SPI1_MEM_C_BUF2_V << SPI1_MEM_C_BUF2_S)
+#define SPI1_MEM_C_BUF2_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF2_S  0
+
+/** SPI1_MEM_C_W3_REG register
+ *  SPI1 memory data buffer3
+ */
+#define SPI1_MEM_C_W3_REG (DR_REG_FLASH_SPI1_BASE + 0x64)
+/** SPI1_MEM_C_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF3    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF3_M  (SPI1_MEM_C_BUF3_V << SPI1_MEM_C_BUF3_S)
+#define SPI1_MEM_C_BUF3_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF3_S  0
+
+/** SPI1_MEM_C_W4_REG register
+ *  SPI1 memory data buffer4
+ */
+#define SPI1_MEM_C_W4_REG (DR_REG_FLASH_SPI1_BASE + 0x68)
+/** SPI1_MEM_C_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF4    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF4_M  (SPI1_MEM_C_BUF4_V << SPI1_MEM_C_BUF4_S)
+#define SPI1_MEM_C_BUF4_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF4_S  0
+
+/** SPI1_MEM_C_W5_REG register
+ *  SPI1 memory data buffer5
+ */
+#define SPI1_MEM_C_W5_REG (DR_REG_FLASH_SPI1_BASE + 0x6c)
+/** SPI1_MEM_C_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF5    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF5_M  (SPI1_MEM_C_BUF5_V << SPI1_MEM_C_BUF5_S)
+#define SPI1_MEM_C_BUF5_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF5_S  0
+
+/** SPI1_MEM_C_W6_REG register
+ *  SPI1 memory data buffer6
+ */
+#define SPI1_MEM_C_W6_REG (DR_REG_FLASH_SPI1_BASE + 0x70)
+/** SPI1_MEM_C_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF6    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF6_M  (SPI1_MEM_C_BUF6_V << SPI1_MEM_C_BUF6_S)
+#define SPI1_MEM_C_BUF6_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF6_S  0
+
+/** SPI1_MEM_C_W7_REG register
+ *  SPI1 memory data buffer7
+ */
+#define SPI1_MEM_C_W7_REG (DR_REG_FLASH_SPI1_BASE + 0x74)
+/** SPI1_MEM_C_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF7    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF7_M  (SPI1_MEM_C_BUF7_V << SPI1_MEM_C_BUF7_S)
+#define SPI1_MEM_C_BUF7_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF7_S  0
+
+/** SPI1_MEM_C_W8_REG register
+ *  SPI1 memory data buffer8
+ */
+#define SPI1_MEM_C_W8_REG (DR_REG_FLASH_SPI1_BASE + 0x78)
+/** SPI1_MEM_C_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF8    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF8_M  (SPI1_MEM_C_BUF8_V << SPI1_MEM_C_BUF8_S)
+#define SPI1_MEM_C_BUF8_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF8_S  0
+
+/** SPI1_MEM_C_W9_REG register
+ *  SPI1 memory data buffer9
+ */
+#define SPI1_MEM_C_W9_REG (DR_REG_FLASH_SPI1_BASE + 0x7c)
+/** SPI1_MEM_C_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF9    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF9_M  (SPI1_MEM_C_BUF9_V << SPI1_MEM_C_BUF9_S)
+#define SPI1_MEM_C_BUF9_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF9_S  0
+
+/** SPI1_MEM_C_W10_REG register
+ *  SPI1 memory data buffer10
+ */
+#define SPI1_MEM_C_W10_REG (DR_REG_FLASH_SPI1_BASE + 0x80)
+/** SPI1_MEM_C_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF10    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF10_M  (SPI1_MEM_C_BUF10_V << SPI1_MEM_C_BUF10_S)
+#define SPI1_MEM_C_BUF10_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF10_S  0
+
+/** SPI1_MEM_C_W11_REG register
+ *  SPI1 memory data buffer11
+ */
+#define SPI1_MEM_C_W11_REG (DR_REG_FLASH_SPI1_BASE + 0x84)
+/** SPI1_MEM_C_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF11    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF11_M  (SPI1_MEM_C_BUF11_V << SPI1_MEM_C_BUF11_S)
+#define SPI1_MEM_C_BUF11_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF11_S  0
+
+/** SPI1_MEM_C_W12_REG register
+ *  SPI1 memory data buffer12
+ */
+#define SPI1_MEM_C_W12_REG (DR_REG_FLASH_SPI1_BASE + 0x88)
+/** SPI1_MEM_C_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF12    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF12_M  (SPI1_MEM_C_BUF12_V << SPI1_MEM_C_BUF12_S)
+#define SPI1_MEM_C_BUF12_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF12_S  0
+
+/** SPI1_MEM_C_W13_REG register
+ *  SPI1 memory data buffer13
+ */
+#define SPI1_MEM_C_W13_REG (DR_REG_FLASH_SPI1_BASE + 0x8c)
+/** SPI1_MEM_C_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF13    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF13_M  (SPI1_MEM_C_BUF13_V << SPI1_MEM_C_BUF13_S)
+#define SPI1_MEM_C_BUF13_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF13_S  0
+
+/** SPI1_MEM_C_W14_REG register
+ *  SPI1 memory data buffer14
+ */
+#define SPI1_MEM_C_W14_REG (DR_REG_FLASH_SPI1_BASE + 0x90)
+/** SPI1_MEM_C_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF14    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF14_M  (SPI1_MEM_C_BUF14_V << SPI1_MEM_C_BUF14_S)
+#define SPI1_MEM_C_BUF14_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF14_S  0
+
+/** SPI1_MEM_C_W15_REG register
+ *  SPI1 memory data buffer15
+ */
+#define SPI1_MEM_C_W15_REG (DR_REG_FLASH_SPI1_BASE + 0x94)
+/** SPI1_MEM_C_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_C_BUF15    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF15_M  (SPI1_MEM_C_BUF15_V << SPI1_MEM_C_BUF15_S)
+#define SPI1_MEM_C_BUF15_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF15_S  0
+
+/** SPI1_MEM_C_FLASH_WAITI_CTRL_REG register
+ *  SPI1 wait idle control register
+ */
+#define SPI1_MEM_C_FLASH_WAITI_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x98)
+/** SPI1_MEM_C_WAITI_EN : R/W; bitpos: [0]; default: 1;
+ *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
+ *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
+ *  Suspend/Resume are not supported.
+ */
+#define SPI1_MEM_C_WAITI_EN    (BIT(0))
+#define SPI1_MEM_C_WAITI_EN_M  (SPI1_MEM_C_WAITI_EN_V << SPI1_MEM_C_WAITI_EN_S)
+#define SPI1_MEM_C_WAITI_EN_V  0x00000001U
+#define SPI1_MEM_C_WAITI_EN_S  0
+/** SPI1_MEM_C_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
+ *  The dummy phase enable when wait flash idle (RDSR)
+ */
+#define SPI1_MEM_C_WAITI_DUMMY    (BIT(1))
+#define SPI1_MEM_C_WAITI_DUMMY_M  (SPI1_MEM_C_WAITI_DUMMY_V << SPI1_MEM_C_WAITI_DUMMY_S)
+#define SPI1_MEM_C_WAITI_DUMMY_V  0x00000001U
+#define SPI1_MEM_C_WAITI_DUMMY_S  1
+/** SPI1_MEM_C_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
+ *  1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out
+ *  address in RDSR or read SUS command transfer.
+ */
+#define SPI1_MEM_C_WAITI_ADDR_EN    (BIT(2))
+#define SPI1_MEM_C_WAITI_ADDR_EN_M  (SPI1_MEM_C_WAITI_ADDR_EN_V << SPI1_MEM_C_WAITI_ADDR_EN_S)
+#define SPI1_MEM_C_WAITI_ADDR_EN_V  0x00000001U
+#define SPI1_MEM_C_WAITI_ADDR_EN_S  2
+/** SPI1_MEM_C_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
+ *  When SPI1_MEM_C_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+ *  (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+ *  SPI1_MEM_C_WAITI_ADDR_EN is cleared.
+ */
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN    0x00000003U
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_M  (SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S)
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V  0x00000003U
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S  3
+/** SPI1_MEM_C_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
+ *  1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
+ */
+#define SPI1_MEM_C_WAITI_CMD_2B    (BIT(9))
+#define SPI1_MEM_C_WAITI_CMD_2B_M  (SPI1_MEM_C_WAITI_CMD_2B_V << SPI1_MEM_C_WAITI_CMD_2B_S)
+#define SPI1_MEM_C_WAITI_CMD_2B_V  0x00000001U
+#define SPI1_MEM_C_WAITI_CMD_2B_S  9
+/** SPI1_MEM_C_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
+ *  The dummy cycle length when wait flash idle(RDSR).
+ */
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_M  (SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_S  10
+/** SPI1_MEM_C_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
+ *  The command value to wait flash idle(RDSR).
+ */
+#define SPI1_MEM_C_WAITI_CMD    0x0000FFFFU
+#define SPI1_MEM_C_WAITI_CMD_M  (SPI1_MEM_C_WAITI_CMD_V << SPI1_MEM_C_WAITI_CMD_S)
+#define SPI1_MEM_C_WAITI_CMD_V  0x0000FFFFU
+#define SPI1_MEM_C_WAITI_CMD_S  16
+
+/** SPI1_MEM_C_FLASH_SUS_CTRL_REG register
+ *  SPI1 flash suspend control register
+ */
+#define SPI1_MEM_C_FLASH_SUS_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x9c)
+/** SPI1_MEM_C_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
+ *  program erase resume bit, program erase suspend operation will be triggered when
+ *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
+ *  disable.
+ */
+#define SPI1_MEM_C_FLASH_PER    (BIT(0))
+#define SPI1_MEM_C_FLASH_PER_M  (SPI1_MEM_C_FLASH_PER_V << SPI1_MEM_C_FLASH_PER_S)
+#define SPI1_MEM_C_FLASH_PER_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PER_S  0
+/** SPI1_MEM_C_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
+ *  program erase suspend bit, program erase suspend operation will be triggered when
+ *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
+ *  disable.
+ */
+#define SPI1_MEM_C_FLASH_PES    (BIT(1))
+#define SPI1_MEM_C_FLASH_PES_M  (SPI1_MEM_C_FLASH_PES_V << SPI1_MEM_C_FLASH_PES_S)
+#define SPI1_MEM_C_FLASH_PES_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_S  1
+/** SPI1_MEM_C_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+ *  program erase resume command is sent. 0: SPI1 does not wait after program erase
+ *  resume command is sent.
+ */
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN_M  (SPI1_MEM_C_FLASH_PER_WAIT_EN_V << SPI1_MEM_C_FLASH_PER_WAIT_EN_S)
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN_S  2
+/** SPI1_MEM_C_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+ *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
+ *  suspend command is sent.
+ */
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN_M  (SPI1_MEM_C_FLASH_PES_WAIT_EN_V << SPI1_MEM_C_FLASH_PES_WAIT_EN_S)
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN_S  3
+/** SPI1_MEM_C_PES_PER_EN : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
+ *  application should send PER after PES is done.
+ */
+#define SPI1_MEM_C_PES_PER_EN    (BIT(4))
+#define SPI1_MEM_C_PES_PER_EN_M  (SPI1_MEM_C_PES_PER_EN_V << SPI1_MEM_C_PES_PER_EN_S)
+#define SPI1_MEM_C_PES_PER_EN_V  0x00000001U
+#define SPI1_MEM_C_PES_PER_EN_S  4
+/** SPI1_MEM_C_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to enable Auto-suspending function.
+ */
+#define SPI1_MEM_C_FLASH_PES_EN    (BIT(5))
+#define SPI1_MEM_C_FLASH_PES_EN_M  (SPI1_MEM_C_FLASH_PES_EN_V << SPI1_MEM_C_FLASH_PES_EN_S)
+#define SPI1_MEM_C_FLASH_PES_EN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_EN_S  5
+/** SPI1_MEM_C_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
+ *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+ *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+ *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
+ *  status_in[15:0]^ SPI1_MEM_C_PESR_END_MSK[15:0].
+ */
+#define SPI1_MEM_C_PESR_END_MSK    0x0000FFFFU
+#define SPI1_MEM_C_PESR_END_MSK_M  (SPI1_MEM_C_PESR_END_MSK_V << SPI1_MEM_C_PESR_END_MSK_S)
+#define SPI1_MEM_C_PESR_END_MSK_V  0x0000FFFFU
+#define SPI1_MEM_C_PESR_END_MSK_S  6
+/** SPI1_MEM_C_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
+ *  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when
+ *  check flash SUS/SUS1/SUS2 status bit
+ */
+#define SPI1_MEM_C_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI1_MEM_C_FMEM_RD_SUS_2B_M  (SPI1_MEM_C_FMEM_RD_SUS_2B_V << SPI1_MEM_C_FMEM_RD_SUS_2B_S)
+#define SPI1_MEM_C_FMEM_RD_SUS_2B_V  0x00000001U
+#define SPI1_MEM_C_FMEM_RD_SUS_2B_S  22
+/** SPI1_MEM_C_PER_END_EN : R/W; bitpos: [23]; default: 0;
+ *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
+ *  flash. 0: Only need to check WIP is 0.
+ */
+#define SPI1_MEM_C_PER_END_EN    (BIT(23))
+#define SPI1_MEM_C_PER_END_EN_M  (SPI1_MEM_C_PER_END_EN_V << SPI1_MEM_C_PER_END_EN_S)
+#define SPI1_MEM_C_PER_END_EN_V  0x00000001U
+#define SPI1_MEM_C_PER_END_EN_S  23
+/** SPI1_MEM_C_PES_END_EN : R/W; bitpos: [24]; default: 0;
+ *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status
+ *  of flash. 0: Only need to check WIP is 0.
+ */
+#define SPI1_MEM_C_PES_END_EN    (BIT(24))
+#define SPI1_MEM_C_PES_END_EN_M  (SPI1_MEM_C_PES_END_EN_V << SPI1_MEM_C_PES_END_EN_S)
+#define SPI1_MEM_C_PES_END_EN_V  0x00000001U
+#define SPI1_MEM_C_PES_END_EN_S  24
+/** SPI1_MEM_C_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
+ *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it
+ *  will be treated as check pass.
+ */
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT    0x0000007FU
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT_M  (SPI1_MEM_C_SUS_TIMEOUT_CNT_V << SPI1_MEM_C_SUS_TIMEOUT_CNT_S)
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT_V  0x0000007FU
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT_S  25
+
+/** SPI1_MEM_C_FLASH_SUS_CMD_REG register
+ *  SPI1 flash suspend command register
+ */
+#define SPI1_MEM_C_FLASH_SUS_CMD_REG (DR_REG_FLASH_SPI1_BASE + 0xa0)
+/** SPI1_MEM_C_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
+ *  Program/Erase suspend command.
+ */
+#define SPI1_MEM_C_FLASH_PES_COMMAND    0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PES_COMMAND_M  (SPI1_MEM_C_FLASH_PES_COMMAND_V << SPI1_MEM_C_FLASH_PES_COMMAND_S)
+#define SPI1_MEM_C_FLASH_PES_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PES_COMMAND_S  0
+/** SPI1_MEM_C_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
+ *  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
+ *  SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
+ */
+#define SPI1_MEM_C_WAIT_PESR_COMMAND    0x0000FFFFU
+#define SPI1_MEM_C_WAIT_PESR_COMMAND_M  (SPI1_MEM_C_WAIT_PESR_COMMAND_V << SPI1_MEM_C_WAIT_PESR_COMMAND_S)
+#define SPI1_MEM_C_WAIT_PESR_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_C_WAIT_PESR_COMMAND_S  16
+
+/** SPI1_MEM_C_SUS_STATUS_REG register
+ *  SPI1 flash suspend status register
+ */
+#define SPI1_MEM_C_SUS_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0xa4)
+/** SPI1_MEM_C_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
+ *  The status of flash suspend, only used in SPI1.
+ */
+#define SPI1_MEM_C_FLASH_SUS    (BIT(0))
+#define SPI1_MEM_C_FLASH_SUS_M  (SPI1_MEM_C_FLASH_SUS_V << SPI1_MEM_C_FLASH_SUS_S)
+#define SPI1_MEM_C_FLASH_SUS_V  0x00000001U
+#define SPI1_MEM_C_FLASH_SUS_S  0
+/** SPI1_MEM_C_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
+ *  1: SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ *  SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+ */
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B_M  (SPI1_MEM_C_WAIT_PESR_CMD_2B_V << SPI1_MEM_C_WAIT_PESR_CMD_2B_S)
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B_S  1
+/** SPI1_MEM_C_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ *  after HPM command is sent.
+ */
+#define SPI1_MEM_C_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI1_MEM_C_FLASH_HPM_DLY_128_M  (SPI1_MEM_C_FLASH_HPM_DLY_128_V << SPI1_MEM_C_FLASH_HPM_DLY_128_S)
+#define SPI1_MEM_C_FLASH_HPM_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_HPM_DLY_128_S  2
+/** SPI1_MEM_C_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ *  after RES command is sent.
+ */
+#define SPI1_MEM_C_FLASH_RES_DLY_128    (BIT(3))
+#define SPI1_MEM_C_FLASH_RES_DLY_128_M  (SPI1_MEM_C_FLASH_RES_DLY_128_V << SPI1_MEM_C_FLASH_RES_DLY_128_S)
+#define SPI1_MEM_C_FLASH_RES_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RES_DLY_128_S  3
+/** SPI1_MEM_C_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ *  after DP command is sent.
+ */
+#define SPI1_MEM_C_FLASH_DP_DLY_128    (BIT(4))
+#define SPI1_MEM_C_FLASH_DP_DLY_128_M  (SPI1_MEM_C_FLASH_DP_DLY_128_V << SPI1_MEM_C_FLASH_DP_DLY_128_S)
+#define SPI1_MEM_C_FLASH_DP_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_DP_DLY_128_S  4
+/** SPI1_MEM_C_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
+ *  Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+ *  sent.
+ */
+#define SPI1_MEM_C_FLASH_PER_DLY_128    (BIT(5))
+#define SPI1_MEM_C_FLASH_PER_DLY_128_M  (SPI1_MEM_C_FLASH_PER_DLY_128_V << SPI1_MEM_C_FLASH_PER_DLY_128_S)
+#define SPI1_MEM_C_FLASH_PER_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PER_DLY_128_S  5
+/** SPI1_MEM_C_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
+ *  Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+ *  sent.
+ */
+#define SPI1_MEM_C_FLASH_PES_DLY_128    (BIT(6))
+#define SPI1_MEM_C_FLASH_PES_DLY_128_M  (SPI1_MEM_C_FLASH_PES_DLY_128_V << SPI1_MEM_C_FLASH_PES_DLY_128_S)
+#define SPI1_MEM_C_FLASH_PES_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_DLY_128_S  6
+/** SPI1_MEM_C_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
+ *  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
+ */
+#define SPI1_MEM_C_SPI0_LOCK_EN    (BIT(7))
+#define SPI1_MEM_C_SPI0_LOCK_EN_M  (SPI1_MEM_C_SPI0_LOCK_EN_V << SPI1_MEM_C_SPI0_LOCK_EN_S)
+#define SPI1_MEM_C_SPI0_LOCK_EN_V  0x00000001U
+#define SPI1_MEM_C_SPI0_LOCK_EN_S  7
+/** SPI1_MEM_C_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
+ *  1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length
+ *  of Program/Erase Suspend/Resume command is 8.
+ */
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B    (BIT(15))
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B_M  (SPI1_MEM_C_FLASH_PESR_CMD_2B_V << SPI1_MEM_C_FLASH_PESR_CMD_2B_S)
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B_S  15
+/** SPI1_MEM_C_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
+ *  Program/Erase resume command.
+ */
+#define SPI1_MEM_C_FLASH_PER_COMMAND    0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PER_COMMAND_M  (SPI1_MEM_C_FLASH_PER_COMMAND_V << SPI1_MEM_C_FLASH_PER_COMMAND_S)
+#define SPI1_MEM_C_FLASH_PER_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PER_COMMAND_S  16
+
+/** SPI1_MEM_C_INT_ENA_REG register
+ *  SPI1 interrupt enable register
+ */
+#define SPI1_MEM_C_INT_ENA_REG (DR_REG_FLASH_SPI1_BASE + 0xc0)
+/** SPI1_MEM_C_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for SPI1_MEM_C_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PER_END_INT_ENA    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_ENA_M  (SPI1_MEM_C_PER_END_INT_ENA_V << SPI1_MEM_C_PER_END_INT_ENA_S)
+#define SPI1_MEM_C_PER_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_ENA_S  0
+/** SPI1_MEM_C_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for SPI1_MEM_C_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PES_END_INT_ENA    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_ENA_M  (SPI1_MEM_C_PES_END_INT_ENA_V << SPI1_MEM_C_PES_END_INT_ENA_S)
+#define SPI1_MEM_C_PES_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_ENA_S  1
+/** SPI1_MEM_C_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for SPI1_MEM_C_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_C_WPE_END_INT_ENA    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_ENA_M  (SPI1_MEM_C_WPE_END_INT_ENA_V << SPI1_MEM_C_WPE_END_INT_ENA_S)
+#define SPI1_MEM_C_WPE_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_ENA_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA_M  (SPI1_MEM_C_SLV_ST_END_INT_ENA_V << SPI1_MEM_C_SLV_ST_END_INT_ENA_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_ENA_M  (SPI1_MEM_C_MST_ST_END_INT_ENA_V << SPI1_MEM_C_MST_ST_END_INT_ENA_S)
+#define SPI1_MEM_C_MST_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_ENA_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA_M  (SPI1_MEM_C_BROWN_OUT_INT_ENA_V << SPI1_MEM_C_BROWN_OUT_INT_ENA_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA_S  10
+
+/** SPI1_MEM_C_INT_CLR_REG register
+ *  SPI1 interrupt clear register
+ */
+#define SPI1_MEM_C_INT_CLR_REG (DR_REG_FLASH_SPI1_BASE + 0xc4)
+/** SPI1_MEM_C_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for SPI1_MEM_C_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PER_END_INT_CLR    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_CLR_M  (SPI1_MEM_C_PER_END_INT_CLR_V << SPI1_MEM_C_PER_END_INT_CLR_S)
+#define SPI1_MEM_C_PER_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_CLR_S  0
+/** SPI1_MEM_C_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for SPI1_MEM_C_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PES_END_INT_CLR    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_CLR_M  (SPI1_MEM_C_PES_END_INT_CLR_V << SPI1_MEM_C_PES_END_INT_CLR_S)
+#define SPI1_MEM_C_PES_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_CLR_S  1
+/** SPI1_MEM_C_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for SPI1_MEM_C_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_C_WPE_END_INT_CLR    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_CLR_M  (SPI1_MEM_C_WPE_END_INT_CLR_V << SPI1_MEM_C_WPE_END_INT_CLR_S)
+#define SPI1_MEM_C_WPE_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_CLR_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR_M  (SPI1_MEM_C_SLV_ST_END_INT_CLR_V << SPI1_MEM_C_SLV_ST_END_INT_CLR_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_CLR_M  (SPI1_MEM_C_MST_ST_END_INT_CLR_V << SPI1_MEM_C_MST_ST_END_INT_CLR_S)
+#define SPI1_MEM_C_MST_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_CLR_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR_M  (SPI1_MEM_C_BROWN_OUT_INT_CLR_V << SPI1_MEM_C_BROWN_OUT_INT_CLR_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR_S  10
+
+/** SPI1_MEM_C_INT_RAW_REG register
+ *  SPI1 interrupt raw register
+ */
+#define SPI1_MEM_C_INT_RAW_REG (DR_REG_FLASH_SPI1_BASE + 0xc8)
+/** SPI1_MEM_C_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit for SPI1_MEM_C_PER_END_INT interrupt. 1: Triggered when Auto Resume
+ *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
+ */
+#define SPI1_MEM_C_PER_END_INT_RAW    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_RAW_M  (SPI1_MEM_C_PER_END_INT_RAW_V << SPI1_MEM_C_PER_END_INT_RAW_S)
+#define SPI1_MEM_C_PER_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_RAW_S  0
+/** SPI1_MEM_C_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit for SPI1_MEM_C_PES_END_INT interrupt.1: Triggered when Auto Suspend
+ *  command (0x75) is sent and flash is suspended successfully. 0: Others.
+ */
+#define SPI1_MEM_C_PES_END_INT_RAW    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_RAW_M  (SPI1_MEM_C_PES_END_INT_RAW_V << SPI1_MEM_C_PES_END_INT_RAW_S)
+#define SPI1_MEM_C_PES_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_RAW_S  1
+/** SPI1_MEM_C_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+ *  is sent and flash is already idle. 0: Others.
+ */
+#define SPI1_MEM_C_WPE_END_INT_RAW    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_RAW_M  (SPI1_MEM_C_WPE_END_INT_RAW_V << SPI1_MEM_C_WPE_END_INT_RAW_S)
+#define SPI1_MEM_C_WPE_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_RAW_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+ *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
+ *  Others
+ */
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW_M  (SPI1_MEM_C_SLV_ST_END_INT_RAW_V << SPI1_MEM_C_SLV_ST_END_INT_RAW_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+ *  changed from non idle state to idle state. 0: Others.
+ */
+#define SPI1_MEM_C_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_RAW_M  (SPI1_MEM_C_MST_ST_END_INT_RAW_V << SPI1_MEM_C_MST_ST_END_INT_RAW_S)
+#define SPI1_MEM_C_MST_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_RAW_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+ *  chip is losing power and RTC module sends out brown out close flash request to
+ *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
+ *  and MSPI returns to idle state. 0: Others.
+ */
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW_M  (SPI1_MEM_C_BROWN_OUT_INT_RAW_V << SPI1_MEM_C_BROWN_OUT_INT_RAW_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW_S  10
+
+/** SPI1_MEM_C_INT_ST_REG register
+ *  SPI1 interrupt status register
+ */
+#define SPI1_MEM_C_INT_ST_REG (DR_REG_FLASH_SPI1_BASE + 0xcc)
+/** SPI1_MEM_C_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for SPI1_MEM_C_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PER_END_INT_ST    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_ST_M  (SPI1_MEM_C_PER_END_INT_ST_V << SPI1_MEM_C_PER_END_INT_ST_S)
+#define SPI1_MEM_C_PER_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_ST_S  0
+/** SPI1_MEM_C_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for SPI1_MEM_C_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PES_END_INT_ST    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_ST_M  (SPI1_MEM_C_PES_END_INT_ST_V << SPI1_MEM_C_PES_END_INT_ST_S)
+#define SPI1_MEM_C_PES_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_ST_S  1
+/** SPI1_MEM_C_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for SPI1_MEM_C_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_C_WPE_END_INT_ST    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_ST_M  (SPI1_MEM_C_WPE_END_INT_ST_V << SPI1_MEM_C_WPE_END_INT_ST_S)
+#define SPI1_MEM_C_WPE_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_ST_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_ST_M  (SPI1_MEM_C_SLV_ST_END_INT_ST_V << SPI1_MEM_C_SLV_ST_END_INT_ST_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_ST_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_MST_ST_END_INT_ST    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_ST_M  (SPI1_MEM_C_MST_ST_END_INT_ST_V << SPI1_MEM_C_MST_ST_END_INT_ST_S)
+#define SPI1_MEM_C_MST_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_ST_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_C_BROWN_OUT_INT_ST    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_ST_M  (SPI1_MEM_C_BROWN_OUT_INT_ST_V << SPI1_MEM_C_BROWN_OUT_INT_ST_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_ST_S  10
+
+/** SPI1_MEM_C_DDR_REG register
+ *  SPI1 DDR control register
+ */
+#define SPI1_MEM_C_DDR_REG (DR_REG_FLASH_SPI1_BASE + 0xd4)
+/** SPI1_MEM_C_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
+ *  1: in ddr mode,  0 in sdr mode
+ */
+#define SPI1_MEM_C_FMEM_DDR_EN    (BIT(0))
+#define SPI1_MEM_C_FMEM_DDR_EN_M  (SPI1_MEM_C_FMEM_DDR_EN_V << SPI1_MEM_C_FMEM_DDR_EN_S)
+#define SPI1_MEM_C_FMEM_DDR_EN_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_EN_S  0
+/** SPI1_MEM_C_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
+ *  Set the bit to enable variable dummy cycle in spi ddr mode.
+ */
+#define SPI1_MEM_C_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI1_MEM_C_FMEM_VAR_DUMMY_M  (SPI1_MEM_C_FMEM_VAR_DUMMY_V << SPI1_MEM_C_FMEM_VAR_DUMMY_S)
+#define SPI1_MEM_C_FMEM_VAR_DUMMY_V  0x00000001U
+#define SPI1_MEM_C_FMEM_VAR_DUMMY_S  1
+/** SPI1_MEM_C_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
+ *  Set the bit to reorder rx data of the word in spi ddr mode.
+ */
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_M  (SPI1_MEM_C_FMEM_DDR_RDAT_SWP_V << SPI1_MEM_C_FMEM_DDR_RDAT_SWP_S)
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_S  2
+/** SPI1_MEM_C_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
+ *  Set the bit to reorder tx data of the word in spi ddr mode.
+ */
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_M  (SPI1_MEM_C_FMEM_DDR_WDAT_SWP_V << SPI1_MEM_C_FMEM_DDR_WDAT_SWP_S)
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_S  3
+/** SPI1_MEM_C_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
+ *  the bit is used to disable dual edge in command phase when ddr mode.
+ */
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_M  (SPI1_MEM_C_FMEM_DDR_CMD_DIS_V << SPI1_MEM_C_FMEM_DDR_CMD_DIS_S)
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_S  4
+/** SPI1_MEM_C_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
+ *  It is the minimum output data length in the panda device.
+ */
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_M  (SPI1_MEM_C_FMEM_OUTMINBYTELEN_V << SPI1_MEM_C_FMEM_OUTMINBYTELEN_S)
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_S  5
+/** SPI1_MEM_C_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
+ *  The delay number of data strobe which from memory based on SPI clock.
+ */
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_M  (SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_V << SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S)
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S  14
+/** SPI1_MEM_C_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
+ *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+ *  spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or
+ *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+ *  negative edge of SPI_DQS.
+ */
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_M  (SPI1_MEM_C_FMEM_DDR_DQS_LOOP_V << SPI1_MEM_C_FMEM_DDR_DQS_LOOP_S)
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_S  21
+/** SPI1_MEM_C_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
+ *  Set this bit to enable the differential SPI_CLK#.
+ */
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_M  (SPI1_MEM_C_FMEM_CLK_DIFF_EN_V << SPI1_MEM_C_FMEM_CLK_DIFF_EN_S)
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_S  24
+/** SPI1_MEM_C_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
+ *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+ */
+#define SPI1_MEM_C_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI1_MEM_C_FMEM_DQS_CA_IN_M  (SPI1_MEM_C_FMEM_DQS_CA_IN_V << SPI1_MEM_C_FMEM_DQS_CA_IN_S)
+#define SPI1_MEM_C_FMEM_DQS_CA_IN_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DQS_CA_IN_S  26
+/** SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
+ *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+ *  accesses flash or SPI1 accesses flash or sram.
+ */
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_M  (SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_V << SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI1_MEM_C_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
+ *  Set this bit to invert SPI_DIFF when accesses to flash. .
+ */
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_M  (SPI1_MEM_C_FMEM_CLK_DIFF_INV_V << SPI1_MEM_C_FMEM_CLK_DIFF_INV_S)
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_S  28
+/** SPI1_MEM_C_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
+ *  Set this bit to enable octa_ram address out when accesses to flash, which means
+ *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
+ */
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_M  (SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_V << SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_S)
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_S  29
+/** SPI1_MEM_C_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
+ *  Set this bit to enable HyperRAM address out when accesses to flash, which means
+ *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+ */
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA_M  (SPI1_MEM_C_FMEM_HYPERBUS_CA_V << SPI1_MEM_C_FMEM_HYPERBUS_CA_S)
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA_S  30
+
+/** SPI1_MEM_C_TIMING_CALI_REG register
+ *  SPI1 timing control register
+ */
+#define SPI1_MEM_C_TIMING_CALI_REG (DR_REG_FLASH_SPI1_BASE + 0x180)
+/** SPI1_MEM_C_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable timing auto-calibration for all reading operations.
+ */
+#define SPI1_MEM_C_TIMING_CALI    (BIT(1))
+#define SPI1_MEM_C_TIMING_CALI_M  (SPI1_MEM_C_TIMING_CALI_V << SPI1_MEM_C_TIMING_CALI_S)
+#define SPI1_MEM_C_TIMING_CALI_V  0x00000001U
+#define SPI1_MEM_C_TIMING_CALI_S  1
+/** SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+ *  add extra dummy spi clock cycle length for spi clock calibration.
+ */
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_M  (SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_S  2
+
+/** SPI1_MEM_C_CLOCK_GATE_REG register
+ *  SPI1 clk_gate register
+ */
+#define SPI1_MEM_C_CLOCK_GATE_REG (DR_REG_FLASH_SPI1_BASE + 0x200)
+/** SPI1_MEM_C_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Register clock gate enable signal. 1: Enable. 0: Disable.
+ */
+#define SPI1_MEM_C_CLK_EN    (BIT(0))
+#define SPI1_MEM_C_CLK_EN_M  (SPI1_MEM_C_CLK_EN_V << SPI1_MEM_C_CLK_EN_S)
+#define SPI1_MEM_C_CLK_EN_V  0x00000001U
+#define SPI1_MEM_C_CLK_EN_S  0
+
+/** SPI1_MEM_C_DATE_REG register
+ *  Version control register
+ */
+#define SPI1_MEM_C_DATE_REG (DR_REG_FLASH_SPI1_BASE + 0x3fc)
+/** SPI1_MEM_C_DATE : R/W; bitpos: [27:0]; default: 35660128;
+ *  Version control register
+ */
+#define SPI1_MEM_C_DATE    0x0FFFFFFFU
+#define SPI1_MEM_C_DATE_M  (SPI1_MEM_C_DATE_V << SPI1_MEM_C_DATE_S)
+#define SPI1_MEM_C_DATE_V  0x0FFFFFFFU
+#define SPI1_MEM_C_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h
new file mode 100644
index 0000000000..52941e2d36
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h
@@ -0,0 +1,1042 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: User-defined control registers */
+/** Type of cmd register
+ *  SPI1 memory command register
+ */
+typedef union {
+    struct {
+        /** mst_st : RO; bitpos: [3:0]; default: 0;
+         *  The current status of SPI1 master FSM.
+         */
+        uint32_t mst_st:4;
+        /** slv_st : RO; bitpos: [7:4]; default: 0;
+         *  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state,
+         *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
+         *  6:write data state, 7: done state, 8: read data end state.
+         */
+        uint32_t slv_st:4;
+        uint32_t reserved_8:9;
+        /** flash_pe : R/W/SC; bitpos: [17]; default: 0;
+         *  In user mode, it is set to indicate that program/erase operation will be triggered.
+         *  The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the
+         *  operation done.1: enable 0: disable.
+         */
+        uint32_t flash_pe:1;
+        /** usr : R/W/SC; bitpos: [18]; default: 0;
+         *  User define command enable.  An operation will be triggered when the bit is set.
+         *  The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t usr:1;
+        /** flash_hpm : R/W/SC; bitpos: [19]; default: 0;
+         *  Drive Flash into high performance mode.  The bit will be cleared once the operation
+         *  done.1: enable 0: disable.
+         */
+        uint32_t flash_hpm:1;
+        /** flash_res : R/W/SC; bitpos: [20]; default: 0;
+         *  This bit combined with reg_resandres bit releases Flash from the power-down state
+         *  or high performance mode and obtains the devices ID. The bit will be cleared once
+         *  the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_res:1;
+        /** flash_dp : R/W/SC; bitpos: [21]; default: 0;
+         *  Drive Flash into power down.  An operation will be triggered when the bit is set.
+         *  The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_dp:1;
+        /** flash_ce : R/W/SC; bitpos: [22]; default: 0;
+         *  Chip erase enable. Chip erase operation will be triggered when the bit is set. The
+         *  bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_ce:1;
+        /** flash_be : R/W/SC; bitpos: [23]; default: 0;
+         *  Block erase enable(32KB) .  Block erase operation will be triggered when the bit is
+         *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_be:1;
+        /** flash_se : R/W/SC; bitpos: [24]; default: 0;
+         *  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
+         *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_se:1;
+        /** flash_pp : R/W/SC; bitpos: [25]; default: 0;
+         *  Page program enable(1 byte ~256 bytes data to be programmed). Page program
+         *  operation  will be triggered when the bit is set. The bit will be cleared once the
+         *  operation done .1: enable 0: disable.
+         */
+        uint32_t flash_pp:1;
+        /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0;
+         *  Write status register enable.   Write status operation  will be triggered when the
+         *  bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_wrsr:1;
+        /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0;
+         *  Read status register-1.  Read status operation will be triggered when the bit is
+         *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_rdsr:1;
+        /** flash_rdid : R/W/SC; bitpos: [28]; default: 0;
+         *  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
+         *  cleared once the operation done. 1: enable 0: disable.
+         */
+        uint32_t flash_rdid:1;
+        /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0;
+         *  Write flash disable. Write disable command will be sent when the bit is set. The
+         *  bit will be cleared once the operation done. 1: enable 0: disable.
+         */
+        uint32_t flash_wrdi:1;
+        /** flash_wren : R/W/SC; bitpos: [30]; default: 0;
+         *  Write flash enable.  Write enable command will be sent when the bit is set. The bit
+         *  will be cleared once the operation done. 1: enable 0: disable.
+         */
+        uint32_t flash_wren:1;
+        /** flash_read : R/W/SC; bitpos: [31]; default: 0;
+         *  Read flash enable. Read flash operation will be triggered when the bit is set. The
+         *  bit will be cleared once the operation done. 1: enable 0: disable.
+         */
+        uint32_t flash_read:1;
+    };
+    uint32_t val;
+} spi1_mem_c_cmd_reg_t;
+
+/** Type of addr register
+ *  SPI1 address register
+ */
+typedef union {
+    struct {
+        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
+         *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
+         *  address, the bit24-bit31 are the byte length of a transfer.
+         */
+        uint32_t usr_addr_value:32;
+    };
+    uint32_t val;
+} spi1_mem_c_addr_reg_t;
+
+/** Type of user register
+ *  SPI1 user register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode.
+         */
+        uint32_t ck_out_edge:1;
+        uint32_t reserved_10:2;
+        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
+         *  In the write operations read-data phase apply 2 signals
+         */
+        uint32_t fwrite_dual:1;
+        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
+         *  In the write operations read-data phase apply 4 signals
+         */
+        uint32_t fwrite_quad:1;
+        /** fwrite_dio : R/W; bitpos: [14]; default: 0;
+         *  In the write operations address phase and read-data phase apply 2 signals.
+         */
+        uint32_t fwrite_dio:1;
+        /** fwrite_qio : R/W; bitpos: [15]; default: 0;
+         *  In the write operations address phase and read-data phase apply 4 signals.
+         */
+        uint32_t fwrite_qio:1;
+        uint32_t reserved_16:8;
+        /** usr_miso_highpart : HRO; bitpos: [24]; default: 0;
+         *  read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
+         *  enable 0: disable.
+         */
+        uint32_t usr_miso_highpart:1;
+        /** usr_mosi_highpart : HRO; bitpos: [25]; default: 0;
+         *  write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
+         *  enable 0: disable.
+         */
+        uint32_t usr_mosi_highpart:1;
+        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  SPI clock is disable in dummy phase when the bit is enable.
+         */
+        uint32_t usr_dummy_idle:1;
+        /** usr_mosi : R/W; bitpos: [27]; default: 0;
+         *  This bit enable the write-data phase of an operation.
+         */
+        uint32_t usr_mosi:1;
+        /** usr_miso : R/W; bitpos: [28]; default: 0;
+         *  This bit enable the read-data phase of an operation.
+         */
+        uint32_t usr_miso:1;
+        /** usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  This bit enable the dummy phase of an operation.
+         */
+        uint32_t usr_dummy:1;
+        /** usr_addr : R/W; bitpos: [30]; default: 0;
+         *  This bit enable the address phase of an operation.
+         */
+        uint32_t usr_addr:1;
+        /** usr_command : R/W; bitpos: [31]; default: 1;
+         *  This bit enable the command phase of an operation.
+         */
+        uint32_t usr_command:1;
+    };
+    uint32_t val;
+} spi1_mem_c_user_reg_t;
+
+/** Type of user1 register
+ *  SPI1 user1 register.
+ */
+typedef union {
+    struct {
+        /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
+         *  The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be
+         *  (cycle_num-1).
+         */
+        uint32_t usr_dummy_cyclelen:6;
+        uint32_t reserved_6:20;
+        /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23;
+         *  The length in bits of address phase. The register value shall be (bit_num-1).
+         */
+        uint32_t usr_addr_bitlen:6;
+    };
+    uint32_t val;
+} spi1_mem_c_user1_reg_t;
+
+/** Type of user2 register
+ *  SPI1 user2 register.
+ */
+typedef union {
+    struct {
+        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  The value of  command.
+         */
+        uint32_t usr_command_value:16;
+        uint32_t reserved_16:12;
+        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  The length in bits of command phase. The register value shall be (bit_num-1)
+         */
+        uint32_t usr_command_bitlen:4;
+    };
+    uint32_t val;
+} spi1_mem_c_user2_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of ctrl register
+ *  SPI1 control register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** fdummy_rin : R/W; bitpos: [2]; default: 1;
+         *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
+         *  level of SPI bus is output by the MSPI controller.
+         */
+        uint32_t fdummy_rin:1;
+        /** fdummy_wout : R/W; bitpos: [3]; default: 1;
+         *  In the dummy phase of a MSPI write data transfer when accesses to flash, the signal
+         *  level of SPI bus is output by the MSPI controller.
+         */
+        uint32_t fdummy_wout:1;
+        /** fdout_oct : HRO; bitpos: [4]; default: 0;
+         *  Apply 8 signals during write-data phase 1:enable 0: disable
+         */
+        uint32_t fdout_oct:1;
+        /** fdin_oct : HRO; bitpos: [5]; default: 0;
+         *  Apply 8 signals during read-data phase 1:enable 0: disable
+         */
+        uint32_t fdin_oct:1;
+        /** faddr_oct : HRO; bitpos: [6]; default: 0;
+         *  Apply 8 signals during address phase 1:enable 0: disable
+         */
+        uint32_t faddr_oct:1;
+        uint32_t reserved_7:1;
+        /** fcmd_quad : R/W; bitpos: [8]; default: 0;
+         *  Apply 4 signals during command phase 1:enable 0: disable
+         */
+        uint32_t fcmd_quad:1;
+        /** fcmd_oct : HRO; bitpos: [9]; default: 0;
+         *  Apply 8 signals during command phase 1:enable 0: disable
+         */
+        uint32_t fcmd_oct:1;
+        /** fcs_crc_en : HRO; bitpos: [10]; default: 0;
+         *  For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
+         *  low.
+         */
+        uint32_t fcs_crc_en:1;
+        /** tx_crc_en : HRO; bitpos: [11]; default: 0;
+         *  For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+         */
+        uint32_t tx_crc_en:1;
+        uint32_t reserved_12:1;
+        /** fastrd_mode : R/W; bitpos: [13]; default: 1;
+         *  This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout
+         *  and spi1_mem_c_fread_dout. 1: enable 0: disable.
+         */
+        uint32_t fastrd_mode:1;
+        /** fread_dual : R/W; bitpos: [14]; default: 0;
+         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+         */
+        uint32_t fread_dual:1;
+        /** resandres : R/W; bitpos: [15]; default: 1;
+         *  The Device ID is read out to SPI1_MEM_C_RD_STATUS register,  this bit combine with
+         *  spi1_mem_c_flash_res bit. 1: enable 0: disable.
+         */
+        uint32_t resandres:1;
+        uint32_t reserved_16:2;
+        /** q_pol : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to set MISO line polarity, 1: high 0, low
+         */
+        uint32_t q_pol:1;
+        /** d_pol : R/W; bitpos: [19]; default: 1;
+         *  The bit is used to set MOSI line polarity, 1: high 0, low
+         */
+        uint32_t d_pol:1;
+        /** fread_quad : R/W; bitpos: [20]; default: 0;
+         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+         */
+        uint32_t fread_quad:1;
+        /** wp_reg : R/W; bitpos: [21]; default: 1;
+         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
+         */
+        uint32_t wp_reg:1;
+        /** wrsr_2b : R/W; bitpos: [22]; default: 0;
+         *  two bytes data will be written to status register when it is set. 1: enable 0:
+         *  disable.
+         */
+        uint32_t wrsr_2b:1;
+        /** fread_dio : R/W; bitpos: [23]; default: 0;
+         *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
+         *  0: disable.
+         */
+        uint32_t fread_dio:1;
+        /** fread_qio : R/W; bitpos: [24]; default: 0;
+         *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
+         *  0: disable.
+         */
+        uint32_t fread_qio:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} spi1_mem_c_ctrl_reg_t;
+
+/** Type of ctrl1 register
+ *  SPI1 control1 register.
+ */
+typedef union {
+    struct {
+        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on.
+         */
+        uint32_t clk_mode:2;
+        /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
+         *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512)
+         *  SPI_CLK cycles.
+         */
+        uint32_t cs_hold_dly_res:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} spi1_mem_c_ctrl1_reg_t;
+
+/** Type of ctrl2 register
+ *  SPI1 control2 register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** sync_reset : WT; bitpos: [31]; default: 0;
+         *  The FSM will be reset.
+         */
+        uint32_t sync_reset:1;
+    };
+    uint32_t val;
+} spi1_mem_c_ctrl2_reg_t;
+
+/** Type of clock register
+ *  SPI1 clock division control register.
+ */
+typedef union {
+    struct {
+        /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
+         *  In the master mode it must be equal to spi1_mem_c_clkcnt_N.
+         */
+        uint32_t clkcnt_l:8;
+        /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
+         *  In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1).
+         */
+        uint32_t clkcnt_h:8;
+        /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
+         *  In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is
+         *  system/(spi1_mem_c_clkcnt_N+1)
+         */
+        uint32_t clkcnt_n:8;
+        uint32_t reserved_24:7;
+        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi1_mem_c_clock_reg_t;
+
+/** Type of mosi_dlen register
+ *  SPI1 send data bit length control register.
+ */
+typedef union {
+    struct {
+        /** usr_mosi_bit_len : R/W; bitpos: [9:0]; default: 0;
+         *  The length in bits of write-data. The register value shall be (bit_num-1).
+         */
+        uint32_t usr_mosi_bit_len:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} spi1_mem_c_mosi_dlen_reg_t;
+
+/** Type of miso_dlen register
+ *  SPI1 receive data bit length control register.
+ */
+typedef union {
+    struct {
+        /** usr_miso_bit_len : R/W; bitpos: [9:0]; default: 0;
+         *  The length in bits of  read-data. The register value shall be (bit_num-1).
+         */
+        uint32_t usr_miso_bit_len:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} spi1_mem_c_miso_dlen_reg_t;
+
+/** Type of rd_status register
+ *  SPI1 status register.
+ */
+typedef union {
+    struct {
+        /** status : R/W/SS; bitpos: [15:0]; default: 0;
+         *  The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit.
+         */
+        uint32_t status:16;
+        /** wb_mode : R/W; bitpos: [23:16]; default: 0;
+         *  Mode bits in the flash fast read mode  it is combined with spi1_mem_c_fastrd_mode bit.
+         */
+        uint32_t wb_mode:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} spi1_mem_c_rd_status_reg_t;
+
+/** Type of misc register
+ *  SPI1 misc register
+ */
+typedef union {
+    struct {
+        /** cs0_dis : R/W; bitpos: [0]; default: 0;
+         *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
+         *  device, such as flash, external RAM and so on.
+         */
+        uint32_t cs0_dis:1;
+        /** cs1_dis : R/W; bitpos: [1]; default: 1;
+         *  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
+         *  device, such as flash, external RAM and so on.
+         */
+        uint32_t cs1_dis:1;
+        uint32_t reserved_2:7;
+        /** ck_idle_edge : R/W; bitpos: [9]; default: 0;
+         *  1: spi clk line is high when idle     0: spi clk line is low when idle
+         */
+        uint32_t ck_idle_edge:1;
+        /** cs_keep_active : R/W; bitpos: [10]; default: 0;
+         *  spi cs line keep low when the bit is set.
+         */
+        uint32_t cs_keep_active:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi1_mem_c_misc_reg_t;
+
+/** Type of cache_fctrl register
+ *  SPI1 bit mode control register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0;
+         *  For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
+         */
+        uint32_t cache_usr_addr_4byte:1;
+        uint32_t reserved_2:1;
+        /** fdin_dual : R/W; bitpos: [3]; default: 0;
+         *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
+         *  spi1_mem_c_fread_dio.
+         */
+        uint32_t fdin_dual:1;
+        /** fdout_dual : R/W; bitpos: [4]; default: 0;
+         *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
+         *  with spi1_mem_c_fread_dio.
+         */
+        uint32_t fdout_dual:1;
+        /** faddr_dual : R/W; bitpos: [5]; default: 0;
+         *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
+         *  with spi1_mem_c_fread_dio.
+         */
+        uint32_t faddr_dual:1;
+        /** fdin_quad : R/W; bitpos: [6]; default: 0;
+         *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+         *  with spi1_mem_c_fread_qio.
+         */
+        uint32_t fdin_quad:1;
+        /** fdout_quad : R/W; bitpos: [7]; default: 0;
+         *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+         *  with spi1_mem_c_fread_qio.
+         */
+        uint32_t fdout_quad:1;
+        /** faddr_quad : R/W; bitpos: [8]; default: 0;
+         *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+         *  with spi1_mem_c_fread_qio.
+         */
+        uint32_t faddr_quad:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi1_mem_c_cache_fctrl_reg_t;
+
+/** Type of flash_waiti_ctrl register
+ *  SPI1 wait idle control register
+ */
+typedef union {
+    struct {
+        /** waiti_en : R/W; bitpos: [0]; default: 1;
+         *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
+         *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
+         *  Suspend/Resume are not supported.
+         */
+        uint32_t waiti_en:1;
+        /** waiti_dummy : R/W; bitpos: [1]; default: 0;
+         *  The dummy phase enable when wait flash idle (RDSR)
+         */
+        uint32_t waiti_dummy:1;
+        /** waiti_addr_en : R/W; bitpos: [2]; default: 0;
+         *  1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out
+         *  address in RDSR or read SUS command transfer.
+         */
+        uint32_t waiti_addr_en:1;
+        /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0;
+         *  When SPI1_MEM_C_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+         *  (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+         *  SPI1_MEM_C_WAITI_ADDR_EN is cleared.
+         */
+        uint32_t waiti_addr_cyclelen:2;
+        uint32_t reserved_5:4;
+        /** waiti_cmd_2b : R/W; bitpos: [9]; default: 0;
+         *  1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
+         */
+        uint32_t waiti_cmd_2b:1;
+        /** waiti_dummy_cyclelen : R/W; bitpos: [15:10]; default: 0;
+         *  The dummy cycle length when wait flash idle(RDSR).
+         */
+        uint32_t waiti_dummy_cyclelen:6;
+        /** waiti_cmd : R/W; bitpos: [31:16]; default: 5;
+         *  The command value to wait flash idle(RDSR).
+         */
+        uint32_t waiti_cmd:16;
+    };
+    uint32_t val;
+} spi1_mem_c_flash_waiti_ctrl_reg_t;
+
+/** Type of flash_sus_ctrl register
+ *  SPI1 flash suspend control register
+ */
+typedef union {
+    struct {
+        /** flash_per : R/W/SC; bitpos: [0]; default: 0;
+         *  program erase resume bit, program erase suspend operation will be triggered when
+         *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
+         *  disable.
+         */
+        uint32_t flash_per:1;
+        /** flash_pes : R/W/SC; bitpos: [1]; default: 0;
+         *  program erase suspend bit, program erase suspend operation will be triggered when
+         *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
+         *  disable.
+         */
+        uint32_t flash_pes:1;
+        /** flash_per_wait_en : R/W; bitpos: [2]; default: 0;
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  program erase resume command is sent. 0: SPI1 does not wait after program erase
+         *  resume command is sent.
+         */
+        uint32_t flash_per_wait_en:1;
+        /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0;
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
+         *  suspend command is sent.
+         */
+        uint32_t flash_pes_wait_en:1;
+        /** pes_per_en : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
+         *  application should send PER after PES is done.
+         */
+        uint32_t pes_per_en:1;
+        /** flash_pes_en : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable Auto-suspending function.
+         */
+        uint32_t flash_pes_en:1;
+        /** pesr_end_msk : R/W; bitpos: [21:6]; default: 128;
+         *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+         *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+         *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
+         *  status_in[15:0]^ SPI1_MEM_C_PESR_END_MSK[15:0].
+         */
+        uint32_t pesr_end_msk:16;
+        /** fmem_rd_sus_2b : R/W; bitpos: [22]; default: 0;
+         *  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when
+         *  check flash SUS/SUS1/SUS2 status bit
+         */
+        uint32_t fmem_rd_sus_2b:1;
+        /** per_end_en : R/W; bitpos: [23]; default: 0;
+         *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
+         *  flash. 0: Only need to check WIP is 0.
+         */
+        uint32_t per_end_en:1;
+        /** pes_end_en : R/W; bitpos: [24]; default: 0;
+         *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status
+         *  of flash. 0: Only need to check WIP is 0.
+         */
+        uint32_t pes_end_en:1;
+        /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4;
+         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it
+         *  will be treated as check pass.
+         */
+        uint32_t sus_timeout_cnt:7;
+    };
+    uint32_t val;
+} spi1_mem_c_flash_sus_ctrl_reg_t;
+
+/** Type of flash_sus_cmd register
+ *  SPI1 flash suspend command register
+ */
+typedef union {
+    struct {
+        /** flash_pes_command : R/W; bitpos: [15:0]; default: 30069;
+         *  Program/Erase suspend command.
+         */
+        uint32_t flash_pes_command:16;
+        /** wait_pesr_command : R/W; bitpos: [31:16]; default: 5;
+         *  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
+         *  SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
+         */
+        uint32_t wait_pesr_command:16;
+    };
+    uint32_t val;
+} spi1_mem_c_flash_sus_cmd_reg_t;
+
+/** Type of sus_status register
+ *  SPI1 flash suspend status register
+ */
+typedef union {
+    struct {
+        /** flash_sus : R/W/SS/SC; bitpos: [0]; default: 0;
+         *  The status of flash suspend, only used in SPI1.
+         */
+        uint32_t flash_sus:1;
+        /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0;
+         *  1: SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+         *  SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+         */
+        uint32_t wait_pesr_cmd_2b:1;
+        /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0;
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  after HPM command is sent.
+         */
+        uint32_t flash_hpm_dly_128:1;
+        /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0;
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  after RES command is sent.
+         */
+        uint32_t flash_res_dly_128:1;
+        /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0;
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  after DP command is sent.
+         */
+        uint32_t flash_dp_dly_128:1;
+        /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0;
+         *  Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+         *  sent.
+         */
+        uint32_t flash_per_dly_128:1;
+        /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0;
+         *  Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+         *  sent.
+         */
+        uint32_t flash_pes_dly_128:1;
+        /** spi0_lock_en : R/W; bitpos: [7]; default: 0;
+         *  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
+         */
+        uint32_t spi0_lock_en:1;
+        uint32_t reserved_8:7;
+        /** flash_pesr_cmd_2b : R/W; bitpos: [15]; default: 0;
+         *  1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length
+         *  of Program/Erase Suspend/Resume command is 8.
+         */
+        uint32_t flash_pesr_cmd_2b:1;
+        /** flash_per_command : R/W; bitpos: [31:16]; default: 31354;
+         *  Program/Erase resume command.
+         */
+        uint32_t flash_per_command:16;
+    };
+    uint32_t val;
+} spi1_mem_c_sus_status_reg_t;
+
+/** Type of ddr register
+ *  SPI1 DDR control register
+ */
+typedef union {
+    struct {
+        /** fmem_ddr_en : HRO; bitpos: [0]; default: 0;
+         *  1: in ddr mode,  0 in sdr mode
+         */
+        uint32_t fmem_ddr_en:1;
+        /** fmem_var_dummy : HRO; bitpos: [1]; default: 0;
+         *  Set the bit to enable variable dummy cycle in spi ddr mode.
+         */
+        uint32_t fmem_var_dummy:1;
+        /** fmem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0;
+         *  Set the bit to reorder rx data of the word in spi ddr mode.
+         */
+        uint32_t fmem_ddr_rdat_swp:1;
+        /** fmem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0;
+         *  Set the bit to reorder tx data of the word in spi ddr mode.
+         */
+        uint32_t fmem_ddr_wdat_swp:1;
+        /** fmem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0;
+         *  the bit is used to disable dual edge in command phase when ddr mode.
+         */
+        uint32_t fmem_ddr_cmd_dis:1;
+        /** fmem_outminbytelen : HRO; bitpos: [11:5]; default: 1;
+         *  It is the minimum output data length in the panda device.
+         */
+        uint32_t fmem_outminbytelen:7;
+        uint32_t reserved_12:2;
+        /** fmem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0;
+         *  The delay number of data strobe which from memory based on SPI clock.
+         */
+        uint32_t fmem_usr_ddr_dqs_thd:7;
+        /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
+         *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+         *  spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or
+         *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+         *  negative edge of SPI_DQS.
+         */
+        uint32_t fmem_ddr_dqs_loop:1;
+        uint32_t reserved_22:2;
+        /** fmem_clk_diff_en : HRO; bitpos: [24]; default: 0;
+         *  Set this bit to enable the differential SPI_CLK#.
+         */
+        uint32_t fmem_clk_diff_en:1;
+        uint32_t reserved_25:1;
+        /** fmem_dqs_ca_in : HRO; bitpos: [26]; default: 0;
+         *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+         */
+        uint32_t fmem_dqs_ca_in:1;
+        /** fmem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0;
+         *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+         *  accesses flash or SPI1 accesses flash or sram.
+         */
+        uint32_t fmem_hyperbus_dummy_2x:1;
+        /** fmem_clk_diff_inv : HRO; bitpos: [28]; default: 0;
+         *  Set this bit to invert SPI_DIFF when accesses to flash. .
+         */
+        uint32_t fmem_clk_diff_inv:1;
+        /** fmem_octa_ram_addr : HRO; bitpos: [29]; default: 0;
+         *  Set this bit to enable octa_ram address out when accesses to flash, which means
+         *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
+         */
+        uint32_t fmem_octa_ram_addr:1;
+        /** fmem_hyperbus_ca : HRO; bitpos: [30]; default: 0;
+         *  Set this bit to enable HyperRAM address out when accesses to flash, which means
+         *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+         */
+        uint32_t fmem_hyperbus_ca:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} spi1_mem_c_ddr_reg_t;
+
+/** Type of clock_gate register
+ *  SPI1 clk_gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Register clock gate enable signal. 1: Enable. 0: Disable.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi1_mem_c_clock_gate_reg_t;
+
+
+/** Group: Status register */
+/** Type of tx_crc register
+ *  SPI1 TX CRC data register.
+ */
+typedef union {
+    struct {
+        /** tx_crc_data : RO; bitpos: [31:0]; default: 4294967295;
+         *  For SPI1, the value of crc32.
+         */
+        uint32_t tx_crc_data:32;
+    };
+    uint32_t val;
+} spi1_mem_c_tx_crc_reg_t;
+
+/** Group: Interrupt registers */
+/** Type of int_ena register
+ *  SPI1 interrupt enable register
+ */
+typedef union {
+    struct {
+        /** per_end_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for SPI1_MEM_C_PER_END_INT interrupt.
+         */
+        uint32_t per_end_int_ena:1;
+        /** pes_end_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for SPI1_MEM_C_PES_END_INT interrupt.
+         */
+        uint32_t pes_end_int_ena:1;
+        /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for SPI1_MEM_C_WPE_END_INT interrupt.
+         */
+        uint32_t wpe_end_int_ena:1;
+        /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
+         */
+        uint32_t slv_st_end_int_ena:1;
+        /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
+         */
+        uint32_t mst_st_end_int_ena:1;
+        uint32_t reserved_5:5;
+        /** brown_out_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The enable bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
+         */
+        uint32_t brown_out_int_ena:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi1_mem_c_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  SPI1 interrupt clear register
+ */
+typedef union {
+    struct {
+        /** per_end_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear bit for SPI1_MEM_C_PER_END_INT interrupt.
+         */
+        uint32_t per_end_int_clr:1;
+        /** pes_end_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear bit for SPI1_MEM_C_PES_END_INT interrupt.
+         */
+        uint32_t pes_end_int_clr:1;
+        /** wpe_end_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear bit for SPI1_MEM_C_WPE_END_INT interrupt.
+         */
+        uint32_t wpe_end_int_clr:1;
+        /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
+         */
+        uint32_t slv_st_end_int_clr:1;
+        /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
+         */
+        uint32_t mst_st_end_int_clr:1;
+        uint32_t reserved_5:5;
+        /** brown_out_int_clr : WT; bitpos: [10]; default: 0;
+         *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
+         */
+        uint32_t brown_out_int_clr:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi1_mem_c_int_clr_reg_t;
+
+/** Type of int_raw register
+ *  SPI1 interrupt raw register
+ */
+typedef union {
+    struct {
+        /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit for SPI1_MEM_C_PER_END_INT interrupt. 1: Triggered when Auto Resume
+         *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
+         */
+        uint32_t per_end_int_raw:1;
+        /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit for SPI1_MEM_C_PES_END_INT interrupt.1: Triggered when Auto Suspend
+         *  command (0x75) is sent and flash is suspended successfully. 0: Others.
+         */
+        uint32_t pes_end_int_raw:1;
+        /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+         *  is sent and flash is already idle. 0: Others.
+         */
+        uint32_t wpe_end_int_raw:1;
+        /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+         *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
+         *  Others
+         */
+        uint32_t slv_st_end_int_raw:1;
+        /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+         *  changed from non idle state to idle state. 0: Others.
+         */
+        uint32_t mst_st_end_int_raw:1;
+        uint32_t reserved_5:5;
+        /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+         *  chip is losing power and RTC module sends out brown out close flash request to
+         *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
+         *  and MSPI returns to idle state. 0: Others.
+         */
+        uint32_t brown_out_int_raw:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi1_mem_c_int_raw_reg_t;
+
+/** Type of int_st register
+ *  SPI1 interrupt status register
+ */
+typedef union {
+    struct {
+        /** per_end_int_st : RO; bitpos: [0]; default: 0;
+         *  The status bit for SPI1_MEM_C_PER_END_INT interrupt.
+         */
+        uint32_t per_end_int_st:1;
+        /** pes_end_int_st : RO; bitpos: [1]; default: 0;
+         *  The status bit for SPI1_MEM_C_PES_END_INT interrupt.
+         */
+        uint32_t pes_end_int_st:1;
+        /** wpe_end_int_st : RO; bitpos: [2]; default: 0;
+         *  The status bit for SPI1_MEM_C_WPE_END_INT interrupt.
+         */
+        uint32_t wpe_end_int_st:1;
+        /** slv_st_end_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
+         */
+        uint32_t slv_st_end_int_st:1;
+        /** mst_st_end_int_st : RO; bitpos: [4]; default: 0;
+         *  The status bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
+         */
+        uint32_t mst_st_end_int_st:1;
+        uint32_t reserved_5:5;
+        /** brown_out_int_st : RO; bitpos: [10]; default: 0;
+         *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
+         */
+        uint32_t brown_out_int_st:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi1_mem_c_int_st_reg_t;
+
+
+/** Group: Timing registers */
+/** Type of timing_cali register
+ *  SPI1 timing control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** timing_cali : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable timing auto-calibration for all reading operations.
+         */
+        uint32_t timing_cali:1;
+        /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0;
+         *  add extra dummy spi clock cycle length for spi clock calibration.
+         */
+        uint32_t extra_dummy_cyclelen:3;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} spi1_mem_c_timing_cali_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35660128;
+         *  Version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi1_mem_c_date_reg_t;
+
+
+typedef struct spi1_mem_c_dev_s {
+    volatile spi1_mem_c_cmd_reg_t cmd;
+    volatile uint32_t addr;
+    volatile spi1_mem_c_ctrl_reg_t ctrl;
+    volatile spi1_mem_c_ctrl1_reg_t ctrl1;
+    volatile spi1_mem_c_ctrl2_reg_t ctrl2;
+    volatile spi1_mem_c_clock_reg_t clock;
+    volatile spi1_mem_c_user_reg_t user;
+    volatile spi1_mem_c_user1_reg_t user1;
+    volatile spi1_mem_c_user2_reg_t user2;
+    volatile spi1_mem_c_mosi_dlen_reg_t mosi_dlen;
+    volatile spi1_mem_c_miso_dlen_reg_t miso_dlen;
+    volatile spi1_mem_c_rd_status_reg_t rd_status;
+    uint32_t reserved_030;
+    volatile spi1_mem_c_misc_reg_t misc;
+    volatile spi1_mem_c_tx_crc_reg_t tx_crc;
+    volatile spi1_mem_c_cache_fctrl_reg_t cache_fctrl;
+    uint32_t reserved_040[6];
+    volatile uint32_t data_buf[16];
+    volatile spi1_mem_c_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
+    volatile spi1_mem_c_flash_sus_ctrl_reg_t flash_sus_ctrl;
+    volatile spi1_mem_c_flash_sus_cmd_reg_t flash_sus_cmd;
+    volatile spi1_mem_c_sus_status_reg_t sus_status;
+    uint32_t reserved_0a8[6];
+    volatile spi1_mem_c_int_ena_reg_t int_ena;
+    volatile spi1_mem_c_int_clr_reg_t int_clr;
+    volatile spi1_mem_c_int_raw_reg_t int_raw;
+    volatile spi1_mem_c_int_st_reg_t int_st;
+    uint32_t reserved_0d0;
+    volatile spi1_mem_c_ddr_reg_t ddr;
+    uint32_t reserved_0d8[42];
+    volatile spi1_mem_c_timing_cali_reg_t timing_cali;
+    uint32_t reserved_184[31];
+    volatile spi1_mem_c_clock_gate_reg_t clock_gate;
+    uint32_t reserved_204[126];
+    volatile spi1_mem_c_date_reg_t date;
+} spi1_mem_c_dev_t;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi1_mem_c_dev_t) == 0x400, "Invalid size of spi1_mem_c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h
new file mode 100644
index 0000000000..22df90ee72
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h
@@ -0,0 +1,1481 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI1_MEM_S_CMD_REG register
+ *  SPI1 memory command register
+ */
+#define SPI1_MEM_S_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0x0)
+/** SPI1_MEM_S_MST_ST : RO; bitpos: [3:0]; default: 0;
+ *  The current status of SPI1 master FSM.
+ */
+#define SPI1_MEM_S_MST_ST    0x0000000FU
+#define SPI1_MEM_S_MST_ST_M  (SPI1_MEM_S_MST_ST_V << SPI1_MEM_S_MST_ST_S)
+#define SPI1_MEM_S_MST_ST_V  0x0000000FU
+#define SPI1_MEM_S_MST_ST_S  0
+/** SPI1_MEM_S_SLV_ST : RO; bitpos: [7:4]; default: 0;
+ *  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state,
+ *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
+ *  6:write data state, 7: done state, 8: read data end state.
+ */
+#define SPI1_MEM_S_SLV_ST    0x0000000FU
+#define SPI1_MEM_S_SLV_ST_M  (SPI1_MEM_S_SLV_ST_V << SPI1_MEM_S_SLV_ST_S)
+#define SPI1_MEM_S_SLV_ST_V  0x0000000FU
+#define SPI1_MEM_S_SLV_ST_S  4
+/** SPI1_MEM_S_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
+ *  In user mode, it is set to indicate that program/erase operation will be triggered.
+ *  The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the
+ *  operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_PE    (BIT(17))
+#define SPI1_MEM_S_FLASH_PE_M  (SPI1_MEM_S_FLASH_PE_V << SPI1_MEM_S_FLASH_PE_S)
+#define SPI1_MEM_S_FLASH_PE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PE_S  17
+/** SPI1_MEM_S_USR : R/W/SC; bitpos: [18]; default: 0;
+ *  User define command enable.  An operation will be triggered when the bit is set.
+ *  The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_S_USR    (BIT(18))
+#define SPI1_MEM_S_USR_M  (SPI1_MEM_S_USR_V << SPI1_MEM_S_USR_S)
+#define SPI1_MEM_S_USR_V  0x00000001U
+#define SPI1_MEM_S_USR_S  18
+/** SPI1_MEM_S_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
+ *  Drive Flash into high performance mode.  The bit will be cleared once the operation
+ *  done.1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_HPM    (BIT(19))
+#define SPI1_MEM_S_FLASH_HPM_M  (SPI1_MEM_S_FLASH_HPM_V << SPI1_MEM_S_FLASH_HPM_S)
+#define SPI1_MEM_S_FLASH_HPM_V  0x00000001U
+#define SPI1_MEM_S_FLASH_HPM_S  19
+/** SPI1_MEM_S_FLASH_RES : R/W/SC; bitpos: [20]; default: 0;
+ *  This bit combined with reg_resandres bit releases Flash from the power-down state
+ *  or high performance mode and obtains the devices ID. The bit will be cleared once
+ *  the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_RES    (BIT(20))
+#define SPI1_MEM_S_FLASH_RES_M  (SPI1_MEM_S_FLASH_RES_V << SPI1_MEM_S_FLASH_RES_S)
+#define SPI1_MEM_S_FLASH_RES_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RES_S  20
+/** SPI1_MEM_S_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
+ *  Drive Flash into power down.  An operation will be triggered when the bit is set.
+ *  The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_DP    (BIT(21))
+#define SPI1_MEM_S_FLASH_DP_M  (SPI1_MEM_S_FLASH_DP_V << SPI1_MEM_S_FLASH_DP_S)
+#define SPI1_MEM_S_FLASH_DP_V  0x00000001U
+#define SPI1_MEM_S_FLASH_DP_S  21
+/** SPI1_MEM_S_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
+ *  Chip erase enable. Chip erase operation will be triggered when the bit is set. The
+ *  bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_CE    (BIT(22))
+#define SPI1_MEM_S_FLASH_CE_M  (SPI1_MEM_S_FLASH_CE_V << SPI1_MEM_S_FLASH_CE_S)
+#define SPI1_MEM_S_FLASH_CE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_CE_S  22
+/** SPI1_MEM_S_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
+ *  Block erase enable(32KB) .  Block erase operation will be triggered when the bit is
+ *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_BE    (BIT(23))
+#define SPI1_MEM_S_FLASH_BE_M  (SPI1_MEM_S_FLASH_BE_V << SPI1_MEM_S_FLASH_BE_S)
+#define SPI1_MEM_S_FLASH_BE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_BE_S  23
+/** SPI1_MEM_S_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
+ *  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
+ *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_SE    (BIT(24))
+#define SPI1_MEM_S_FLASH_SE_M  (SPI1_MEM_S_FLASH_SE_V << SPI1_MEM_S_FLASH_SE_S)
+#define SPI1_MEM_S_FLASH_SE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_SE_S  24
+/** SPI1_MEM_S_FLASH_PP : R/W/SC; bitpos: [25]; default: 0;
+ *  Page program enable(1 byte ~256 bytes data to be programmed). Page program
+ *  operation  will be triggered when the bit is set. The bit will be cleared once the
+ *  operation done .1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_PP    (BIT(25))
+#define SPI1_MEM_S_FLASH_PP_M  (SPI1_MEM_S_FLASH_PP_V << SPI1_MEM_S_FLASH_PP_S)
+#define SPI1_MEM_S_FLASH_PP_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PP_S  25
+/** SPI1_MEM_S_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
+ *  Write status register enable.   Write status operation  will be triggered when the
+ *  bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_WRSR    (BIT(26))
+#define SPI1_MEM_S_FLASH_WRSR_M  (SPI1_MEM_S_FLASH_WRSR_V << SPI1_MEM_S_FLASH_WRSR_S)
+#define SPI1_MEM_S_FLASH_WRSR_V  0x00000001U
+#define SPI1_MEM_S_FLASH_WRSR_S  26
+/** SPI1_MEM_S_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
+ *  Read status register-1.  Read status operation will be triggered when the bit is
+ *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_RDSR    (BIT(27))
+#define SPI1_MEM_S_FLASH_RDSR_M  (SPI1_MEM_S_FLASH_RDSR_V << SPI1_MEM_S_FLASH_RDSR_S)
+#define SPI1_MEM_S_FLASH_RDSR_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RDSR_S  27
+/** SPI1_MEM_S_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
+ *  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
+ *  cleared once the operation done. 1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_RDID    (BIT(28))
+#define SPI1_MEM_S_FLASH_RDID_M  (SPI1_MEM_S_FLASH_RDID_V << SPI1_MEM_S_FLASH_RDID_S)
+#define SPI1_MEM_S_FLASH_RDID_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RDID_S  28
+/** SPI1_MEM_S_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
+ *  Write flash disable. Write disable command will be sent when the bit is set. The
+ *  bit will be cleared once the operation done. 1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_WRDI    (BIT(29))
+#define SPI1_MEM_S_FLASH_WRDI_M  (SPI1_MEM_S_FLASH_WRDI_V << SPI1_MEM_S_FLASH_WRDI_S)
+#define SPI1_MEM_S_FLASH_WRDI_V  0x00000001U
+#define SPI1_MEM_S_FLASH_WRDI_S  29
+/** SPI1_MEM_S_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
+ *  Write flash enable.  Write enable command will be sent when the bit is set. The bit
+ *  will be cleared once the operation done. 1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_WREN    (BIT(30))
+#define SPI1_MEM_S_FLASH_WREN_M  (SPI1_MEM_S_FLASH_WREN_V << SPI1_MEM_S_FLASH_WREN_S)
+#define SPI1_MEM_S_FLASH_WREN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_WREN_S  30
+/** SPI1_MEM_S_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
+ *  Read flash enable. Read flash operation will be triggered when the bit is set. The
+ *  bit will be cleared once the operation done. 1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FLASH_READ    (BIT(31))
+#define SPI1_MEM_S_FLASH_READ_M  (SPI1_MEM_S_FLASH_READ_V << SPI1_MEM_S_FLASH_READ_S)
+#define SPI1_MEM_S_FLASH_READ_V  0x00000001U
+#define SPI1_MEM_S_FLASH_READ_S  31
+
+/** SPI1_MEM_S_ADDR_REG register
+ *  SPI1 address register
+ */
+#define SPI1_MEM_S_ADDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0x4)
+/** SPI1_MEM_S_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
+ *  address, the bit24-bit31 are the byte length of a transfer.
+ */
+#define SPI1_MEM_S_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI1_MEM_S_USR_ADDR_VALUE_M  (SPI1_MEM_S_USR_ADDR_VALUE_V << SPI1_MEM_S_USR_ADDR_VALUE_S)
+#define SPI1_MEM_S_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI1_MEM_S_USR_ADDR_VALUE_S  0
+
+/** SPI1_MEM_S_CTRL_REG register
+ *  SPI1 control register.
+ */
+#define SPI1_MEM_S_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8)
+/** SPI1_MEM_S_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
+ *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
+ *  level of SPI bus is output by the MSPI controller.
+ */
+#define SPI1_MEM_S_FDUMMY_RIN    (BIT(2))
+#define SPI1_MEM_S_FDUMMY_RIN_M  (SPI1_MEM_S_FDUMMY_RIN_V << SPI1_MEM_S_FDUMMY_RIN_S)
+#define SPI1_MEM_S_FDUMMY_RIN_V  0x00000001U
+#define SPI1_MEM_S_FDUMMY_RIN_S  2
+/** SPI1_MEM_S_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
+ *  In the dummy phase of a MSPI write data transfer when accesses to flash, the signal
+ *  level of SPI bus is output by the MSPI controller.
+ */
+#define SPI1_MEM_S_FDUMMY_WOUT    (BIT(3))
+#define SPI1_MEM_S_FDUMMY_WOUT_M  (SPI1_MEM_S_FDUMMY_WOUT_V << SPI1_MEM_S_FDUMMY_WOUT_S)
+#define SPI1_MEM_S_FDUMMY_WOUT_V  0x00000001U
+#define SPI1_MEM_S_FDUMMY_WOUT_S  3
+/** SPI1_MEM_S_FDOUT_OCT : R/W; bitpos: [4]; default: 0;
+ *  Apply 8 signals during write-data phase 1:enable 0: disable
+ */
+#define SPI1_MEM_S_FDOUT_OCT    (BIT(4))
+#define SPI1_MEM_S_FDOUT_OCT_M  (SPI1_MEM_S_FDOUT_OCT_V << SPI1_MEM_S_FDOUT_OCT_S)
+#define SPI1_MEM_S_FDOUT_OCT_V  0x00000001U
+#define SPI1_MEM_S_FDOUT_OCT_S  4
+/** SPI1_MEM_S_FDIN_OCT : R/W; bitpos: [5]; default: 0;
+ *  Apply 8 signals during read-data phase 1:enable 0: disable
+ */
+#define SPI1_MEM_S_FDIN_OCT    (BIT(5))
+#define SPI1_MEM_S_FDIN_OCT_M  (SPI1_MEM_S_FDIN_OCT_V << SPI1_MEM_S_FDIN_OCT_S)
+#define SPI1_MEM_S_FDIN_OCT_V  0x00000001U
+#define SPI1_MEM_S_FDIN_OCT_S  5
+/** SPI1_MEM_S_FADDR_OCT : R/W; bitpos: [6]; default: 0;
+ *  Apply 8 signals during address phase 1:enable 0: disable
+ */
+#define SPI1_MEM_S_FADDR_OCT    (BIT(6))
+#define SPI1_MEM_S_FADDR_OCT_M  (SPI1_MEM_S_FADDR_OCT_V << SPI1_MEM_S_FADDR_OCT_S)
+#define SPI1_MEM_S_FADDR_OCT_V  0x00000001U
+#define SPI1_MEM_S_FADDR_OCT_S  6
+/** SPI1_MEM_S_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
+ *  Apply 4 signals during command phase 1:enable 0: disable
+ */
+#define SPI1_MEM_S_FCMD_QUAD    (BIT(8))
+#define SPI1_MEM_S_FCMD_QUAD_M  (SPI1_MEM_S_FCMD_QUAD_V << SPI1_MEM_S_FCMD_QUAD_S)
+#define SPI1_MEM_S_FCMD_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FCMD_QUAD_S  8
+/** SPI1_MEM_S_FCMD_OCT : R/W; bitpos: [9]; default: 0;
+ *  Apply 8 signals during command phase 1:enable 0: disable
+ */
+#define SPI1_MEM_S_FCMD_OCT    (BIT(9))
+#define SPI1_MEM_S_FCMD_OCT_M  (SPI1_MEM_S_FCMD_OCT_V << SPI1_MEM_S_FCMD_OCT_S)
+#define SPI1_MEM_S_FCMD_OCT_V  0x00000001U
+#define SPI1_MEM_S_FCMD_OCT_S  9
+/** SPI1_MEM_S_FCS_CRC_EN : R/W; bitpos: [10]; default: 0;
+ *  For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
+ *  low.
+ */
+#define SPI1_MEM_S_FCS_CRC_EN    (BIT(10))
+#define SPI1_MEM_S_FCS_CRC_EN_M  (SPI1_MEM_S_FCS_CRC_EN_V << SPI1_MEM_S_FCS_CRC_EN_S)
+#define SPI1_MEM_S_FCS_CRC_EN_V  0x00000001U
+#define SPI1_MEM_S_FCS_CRC_EN_S  10
+/** SPI1_MEM_S_TX_CRC_EN : R/W; bitpos: [11]; default: 0;
+ *  For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+ */
+#define SPI1_MEM_S_TX_CRC_EN    (BIT(11))
+#define SPI1_MEM_S_TX_CRC_EN_M  (SPI1_MEM_S_TX_CRC_EN_V << SPI1_MEM_S_TX_CRC_EN_S)
+#define SPI1_MEM_S_TX_CRC_EN_V  0x00000001U
+#define SPI1_MEM_S_TX_CRC_EN_S  11
+/** SPI1_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
+ *  This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout
+ *  and spi1_mem_s_fread_dout. 1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FASTRD_MODE    (BIT(13))
+#define SPI1_MEM_S_FASTRD_MODE_M  (SPI1_MEM_S_FASTRD_MODE_V << SPI1_MEM_S_FASTRD_MODE_S)
+#define SPI1_MEM_S_FASTRD_MODE_V  0x00000001U
+#define SPI1_MEM_S_FASTRD_MODE_S  13
+/** SPI1_MEM_S_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+ *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FREAD_DUAL    (BIT(14))
+#define SPI1_MEM_S_FREAD_DUAL_M  (SPI1_MEM_S_FREAD_DUAL_V << SPI1_MEM_S_FREAD_DUAL_S)
+#define SPI1_MEM_S_FREAD_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FREAD_DUAL_S  14
+/** SPI1_MEM_S_RESANDRES : R/W; bitpos: [15]; default: 1;
+ *  The Device ID is read out to SPI1_MEM_S_RD_STATUS register,  this bit combine with
+ *  spi1_mem_s_flash_res bit. 1: enable 0: disable.
+ */
+#define SPI1_MEM_S_RESANDRES    (BIT(15))
+#define SPI1_MEM_S_RESANDRES_M  (SPI1_MEM_S_RESANDRES_V << SPI1_MEM_S_RESANDRES_S)
+#define SPI1_MEM_S_RESANDRES_V  0x00000001U
+#define SPI1_MEM_S_RESANDRES_S  15
+/** SPI1_MEM_S_Q_POL : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to set MISO line polarity, 1: high 0, low
+ */
+#define SPI1_MEM_S_Q_POL    (BIT(18))
+#define SPI1_MEM_S_Q_POL_M  (SPI1_MEM_S_Q_POL_V << SPI1_MEM_S_Q_POL_S)
+#define SPI1_MEM_S_Q_POL_V  0x00000001U
+#define SPI1_MEM_S_Q_POL_S  18
+/** SPI1_MEM_S_D_POL : R/W; bitpos: [19]; default: 1;
+ *  The bit is used to set MOSI line polarity, 1: high 0, low
+ */
+#define SPI1_MEM_S_D_POL    (BIT(19))
+#define SPI1_MEM_S_D_POL_M  (SPI1_MEM_S_D_POL_V << SPI1_MEM_S_D_POL_S)
+#define SPI1_MEM_S_D_POL_V  0x00000001U
+#define SPI1_MEM_S_D_POL_S  19
+/** SPI1_MEM_S_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
+ *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FREAD_QUAD    (BIT(20))
+#define SPI1_MEM_S_FREAD_QUAD_M  (SPI1_MEM_S_FREAD_QUAD_V << SPI1_MEM_S_FREAD_QUAD_S)
+#define SPI1_MEM_S_FREAD_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FREAD_QUAD_S  20
+/** SPI1_MEM_S_WP_REG : R/W; bitpos: [21]; default: 1;
+ *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
+ */
+#define SPI1_MEM_S_WP_REG    (BIT(21))
+#define SPI1_MEM_S_WP_REG_M  (SPI1_MEM_S_WP_REG_V << SPI1_MEM_S_WP_REG_S)
+#define SPI1_MEM_S_WP_REG_V  0x00000001U
+#define SPI1_MEM_S_WP_REG_S  21
+/** SPI1_MEM_S_WRSR_2B : R/W; bitpos: [22]; default: 0;
+ *  two bytes data will be written to status register when it is set. 1: enable 0:
+ *  disable.
+ */
+#define SPI1_MEM_S_WRSR_2B    (BIT(22))
+#define SPI1_MEM_S_WRSR_2B_M  (SPI1_MEM_S_WRSR_2B_V << SPI1_MEM_S_WRSR_2B_S)
+#define SPI1_MEM_S_WRSR_2B_V  0x00000001U
+#define SPI1_MEM_S_WRSR_2B_S  22
+/** SPI1_MEM_S_FREAD_DIO : R/W; bitpos: [23]; default: 0;
+ *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
+ *  0: disable.
+ */
+#define SPI1_MEM_S_FREAD_DIO    (BIT(23))
+#define SPI1_MEM_S_FREAD_DIO_M  (SPI1_MEM_S_FREAD_DIO_V << SPI1_MEM_S_FREAD_DIO_S)
+#define SPI1_MEM_S_FREAD_DIO_V  0x00000001U
+#define SPI1_MEM_S_FREAD_DIO_S  23
+/** SPI1_MEM_S_FREAD_QIO : R/W; bitpos: [24]; default: 0;
+ *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
+ *  0: disable.
+ */
+#define SPI1_MEM_S_FREAD_QIO    (BIT(24))
+#define SPI1_MEM_S_FREAD_QIO_M  (SPI1_MEM_S_FREAD_QIO_V << SPI1_MEM_S_FREAD_QIO_S)
+#define SPI1_MEM_S_FREAD_QIO_V  0x00000001U
+#define SPI1_MEM_S_FREAD_QIO_S  24
+
+/** SPI1_MEM_S_CTRL1_REG register
+ *  SPI1 control1 register.
+ */
+#define SPI1_MEM_S_CTRL1_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc)
+/** SPI1_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+ *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+ *  SPI clock is always on.
+ */
+#define SPI1_MEM_S_CLK_MODE    0x00000003U
+#define SPI1_MEM_S_CLK_MODE_M  (SPI1_MEM_S_CLK_MODE_V << SPI1_MEM_S_CLK_MODE_S)
+#define SPI1_MEM_S_CLK_MODE_V  0x00000003U
+#define SPI1_MEM_S_CLK_MODE_S  0
+/** SPI1_MEM_S_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
+ *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512)
+ *  SPI_CLK cycles.
+ */
+#define SPI1_MEM_S_CS_HOLD_DLY_RES    0x000003FFU
+#define SPI1_MEM_S_CS_HOLD_DLY_RES_M  (SPI1_MEM_S_CS_HOLD_DLY_RES_V << SPI1_MEM_S_CS_HOLD_DLY_RES_S)
+#define SPI1_MEM_S_CS_HOLD_DLY_RES_V  0x000003FFU
+#define SPI1_MEM_S_CS_HOLD_DLY_RES_S  2
+
+/** SPI1_MEM_S_CTRL2_REG register
+ *  SPI1 control2 register.
+ */
+#define SPI1_MEM_S_CTRL2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x10)
+/** SPI1_MEM_S_SYNC_RESET : WT; bitpos: [31]; default: 0;
+ *  The FSM will be reset.
+ */
+#define SPI1_MEM_S_SYNC_RESET    (BIT(31))
+#define SPI1_MEM_S_SYNC_RESET_M  (SPI1_MEM_S_SYNC_RESET_V << SPI1_MEM_S_SYNC_RESET_S)
+#define SPI1_MEM_S_SYNC_RESET_V  0x00000001U
+#define SPI1_MEM_S_SYNC_RESET_S  31
+
+/** SPI1_MEM_S_CLOCK_REG register
+ *  SPI1 clock division control register.
+ */
+#define SPI1_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI1_BASE + 0x14)
+/** SPI1_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+ *  In the master mode it must be equal to spi1_mem_s_clkcnt_N.
+ */
+#define SPI1_MEM_S_CLKCNT_L    0x000000FFU
+#define SPI1_MEM_S_CLKCNT_L_M  (SPI1_MEM_S_CLKCNT_L_V << SPI1_MEM_S_CLKCNT_L_S)
+#define SPI1_MEM_S_CLKCNT_L_V  0x000000FFU
+#define SPI1_MEM_S_CLKCNT_L_S  0
+/** SPI1_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+ *  In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1).
+ */
+#define SPI1_MEM_S_CLKCNT_H    0x000000FFU
+#define SPI1_MEM_S_CLKCNT_H_M  (SPI1_MEM_S_CLKCNT_H_V << SPI1_MEM_S_CLKCNT_H_S)
+#define SPI1_MEM_S_CLKCNT_H_V  0x000000FFU
+#define SPI1_MEM_S_CLKCNT_H_S  8
+/** SPI1_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+ *  In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is
+ *  system/(spi1_mem_s_clkcnt_N+1)
+ */
+#define SPI1_MEM_S_CLKCNT_N    0x000000FFU
+#define SPI1_MEM_S_CLKCNT_N_M  (SPI1_MEM_S_CLKCNT_N_V << SPI1_MEM_S_CLKCNT_N_S)
+#define SPI1_MEM_S_CLKCNT_N_V  0x000000FFU
+#define SPI1_MEM_S_CLKCNT_N_S  16
+/** SPI1_MEM_S_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define SPI1_MEM_S_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI1_MEM_S_CLK_EQU_SYSCLK_M  (SPI1_MEM_S_CLK_EQU_SYSCLK_V << SPI1_MEM_S_CLK_EQU_SYSCLK_S)
+#define SPI1_MEM_S_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI1_MEM_S_CLK_EQU_SYSCLK_S  31
+
+/** SPI1_MEM_S_USER_REG register
+ *  SPI1 user register.
+ */
+#define SPI1_MEM_S_USER_REG (DR_REG_PSRAM_MSPI1_BASE + 0x18)
+/** SPI1_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode.
+ */
+#define SPI1_MEM_S_CK_OUT_EDGE    (BIT(9))
+#define SPI1_MEM_S_CK_OUT_EDGE_M  (SPI1_MEM_S_CK_OUT_EDGE_V << SPI1_MEM_S_CK_OUT_EDGE_S)
+#define SPI1_MEM_S_CK_OUT_EDGE_V  0x00000001U
+#define SPI1_MEM_S_CK_OUT_EDGE_S  9
+/** SPI1_MEM_S_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+ *  In the write operations read-data phase apply 2 signals
+ */
+#define SPI1_MEM_S_FWRITE_DUAL    (BIT(12))
+#define SPI1_MEM_S_FWRITE_DUAL_M  (SPI1_MEM_S_FWRITE_DUAL_V << SPI1_MEM_S_FWRITE_DUAL_S)
+#define SPI1_MEM_S_FWRITE_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_DUAL_S  12
+/** SPI1_MEM_S_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+ *  In the write operations read-data phase apply 4 signals
+ */
+#define SPI1_MEM_S_FWRITE_QUAD    (BIT(13))
+#define SPI1_MEM_S_FWRITE_QUAD_M  (SPI1_MEM_S_FWRITE_QUAD_V << SPI1_MEM_S_FWRITE_QUAD_S)
+#define SPI1_MEM_S_FWRITE_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_QUAD_S  13
+/** SPI1_MEM_S_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
+ *  In the write operations address phase and read-data phase apply 2 signals.
+ */
+#define SPI1_MEM_S_FWRITE_DIO    (BIT(14))
+#define SPI1_MEM_S_FWRITE_DIO_M  (SPI1_MEM_S_FWRITE_DIO_V << SPI1_MEM_S_FWRITE_DIO_S)
+#define SPI1_MEM_S_FWRITE_DIO_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_DIO_S  14
+/** SPI1_MEM_S_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
+ *  In the write operations address phase and read-data phase apply 4 signals.
+ */
+#define SPI1_MEM_S_FWRITE_QIO    (BIT(15))
+#define SPI1_MEM_S_FWRITE_QIO_M  (SPI1_MEM_S_FWRITE_QIO_V << SPI1_MEM_S_FWRITE_QIO_S)
+#define SPI1_MEM_S_FWRITE_QIO_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_QIO_S  15
+/** SPI1_MEM_S_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
+ *  enable 0: disable.
+ */
+#define SPI1_MEM_S_USR_MISO_HIGHPART    (BIT(24))
+#define SPI1_MEM_S_USR_MISO_HIGHPART_M  (SPI1_MEM_S_USR_MISO_HIGHPART_V << SPI1_MEM_S_USR_MISO_HIGHPART_S)
+#define SPI1_MEM_S_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI1_MEM_S_USR_MISO_HIGHPART_S  24
+/** SPI1_MEM_S_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
+ *  enable 0: disable.
+ */
+#define SPI1_MEM_S_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI1_MEM_S_USR_MOSI_HIGHPART_M  (SPI1_MEM_S_USR_MOSI_HIGHPART_V << SPI1_MEM_S_USR_MOSI_HIGHPART_S)
+#define SPI1_MEM_S_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI1_MEM_S_USR_MOSI_HIGHPART_S  25
+/** SPI1_MEM_S_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+ *  SPI clock is disable in dummy phase when the bit is enable.
+ */
+#define SPI1_MEM_S_USR_DUMMY_IDLE    (BIT(26))
+#define SPI1_MEM_S_USR_DUMMY_IDLE_M  (SPI1_MEM_S_USR_DUMMY_IDLE_V << SPI1_MEM_S_USR_DUMMY_IDLE_S)
+#define SPI1_MEM_S_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI1_MEM_S_USR_DUMMY_IDLE_S  26
+/** SPI1_MEM_S_USR_MOSI : R/W; bitpos: [27]; default: 0;
+ *  This bit enable the write-data phase of an operation.
+ */
+#define SPI1_MEM_S_USR_MOSI    (BIT(27))
+#define SPI1_MEM_S_USR_MOSI_M  (SPI1_MEM_S_USR_MOSI_V << SPI1_MEM_S_USR_MOSI_S)
+#define SPI1_MEM_S_USR_MOSI_V  0x00000001U
+#define SPI1_MEM_S_USR_MOSI_S  27
+/** SPI1_MEM_S_USR_MISO : R/W; bitpos: [28]; default: 0;
+ *  This bit enable the read-data phase of an operation.
+ */
+#define SPI1_MEM_S_USR_MISO    (BIT(28))
+#define SPI1_MEM_S_USR_MISO_M  (SPI1_MEM_S_USR_MISO_V << SPI1_MEM_S_USR_MISO_S)
+#define SPI1_MEM_S_USR_MISO_V  0x00000001U
+#define SPI1_MEM_S_USR_MISO_S  28
+/** SPI1_MEM_S_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+ *  This bit enable the dummy phase of an operation.
+ */
+#define SPI1_MEM_S_USR_DUMMY    (BIT(29))
+#define SPI1_MEM_S_USR_DUMMY_M  (SPI1_MEM_S_USR_DUMMY_V << SPI1_MEM_S_USR_DUMMY_S)
+#define SPI1_MEM_S_USR_DUMMY_V  0x00000001U
+#define SPI1_MEM_S_USR_DUMMY_S  29
+/** SPI1_MEM_S_USR_ADDR : R/W; bitpos: [30]; default: 0;
+ *  This bit enable the address phase of an operation.
+ */
+#define SPI1_MEM_S_USR_ADDR    (BIT(30))
+#define SPI1_MEM_S_USR_ADDR_M  (SPI1_MEM_S_USR_ADDR_V << SPI1_MEM_S_USR_ADDR_S)
+#define SPI1_MEM_S_USR_ADDR_V  0x00000001U
+#define SPI1_MEM_S_USR_ADDR_S  30
+/** SPI1_MEM_S_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+ *  This bit enable the command phase of an operation.
+ */
+#define SPI1_MEM_S_USR_COMMAND    (BIT(31))
+#define SPI1_MEM_S_USR_COMMAND_M  (SPI1_MEM_S_USR_COMMAND_V << SPI1_MEM_S_USR_COMMAND_S)
+#define SPI1_MEM_S_USR_COMMAND_V  0x00000001U
+#define SPI1_MEM_S_USR_COMMAND_S  31
+
+/** SPI1_MEM_S_USER1_REG register
+ *  SPI1 user1 register.
+ */
+#define SPI1_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x1c)
+/** SPI1_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
+ *  The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be
+ *  (cycle_num-1).
+ */
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_M  (SPI1_MEM_S_USR_DUMMY_CYCLELEN_V << SPI1_MEM_S_USR_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_S  0
+/** SPI1_MEM_S_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
+ *  The length in bits of address phase. The register value shall be (bit_num-1).
+ */
+#define SPI1_MEM_S_USR_ADDR_BITLEN    0x0000003FU
+#define SPI1_MEM_S_USR_ADDR_BITLEN_M  (SPI1_MEM_S_USR_ADDR_BITLEN_V << SPI1_MEM_S_USR_ADDR_BITLEN_S)
+#define SPI1_MEM_S_USR_ADDR_BITLEN_V  0x0000003FU
+#define SPI1_MEM_S_USR_ADDR_BITLEN_S  26
+
+/** SPI1_MEM_S_USER2_REG register
+ *  SPI1 user2 register.
+ */
+#define SPI1_MEM_S_USER2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x20)
+/** SPI1_MEM_S_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  The value of  command.
+ */
+#define SPI1_MEM_S_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI1_MEM_S_USR_COMMAND_VALUE_M  (SPI1_MEM_S_USR_COMMAND_VALUE_V << SPI1_MEM_S_USR_COMMAND_VALUE_S)
+#define SPI1_MEM_S_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI1_MEM_S_USR_COMMAND_VALUE_S  0
+/** SPI1_MEM_S_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+ *  The length in bits of command phase. The register value shall be (bit_num-1)
+ */
+#define SPI1_MEM_S_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI1_MEM_S_USR_COMMAND_BITLEN_M  (SPI1_MEM_S_USR_COMMAND_BITLEN_V << SPI1_MEM_S_USR_COMMAND_BITLEN_S)
+#define SPI1_MEM_S_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI1_MEM_S_USR_COMMAND_BITLEN_S  28
+
+/** SPI1_MEM_S_MOSI_DLEN_REG register
+ *  SPI1 send data bit length control register.
+ */
+#define SPI1_MEM_S_MOSI_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x24)
+/** SPI1_MEM_S_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+ *  The length in bits of write-data. The register value shall be (bit_num-1).
+ */
+#define SPI1_MEM_S_USR_MOSI_DBITLEN    0x000003FFU
+#define SPI1_MEM_S_USR_MOSI_DBITLEN_M  (SPI1_MEM_S_USR_MOSI_DBITLEN_V << SPI1_MEM_S_USR_MOSI_DBITLEN_S)
+#define SPI1_MEM_S_USR_MOSI_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_S_USR_MOSI_DBITLEN_S  0
+
+/** SPI1_MEM_S_MISO_DLEN_REG register
+ *  SPI1 receive data bit length control register.
+ */
+#define SPI1_MEM_S_MISO_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x28)
+/** SPI1_MEM_S_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+ *  The length in bits of  read-data. The register value shall be (bit_num-1).
+ */
+#define SPI1_MEM_S_USR_MISO_DBITLEN    0x000003FFU
+#define SPI1_MEM_S_USR_MISO_DBITLEN_M  (SPI1_MEM_S_USR_MISO_DBITLEN_V << SPI1_MEM_S_USR_MISO_DBITLEN_S)
+#define SPI1_MEM_S_USR_MISO_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_S_USR_MISO_DBITLEN_S  0
+
+/** SPI1_MEM_S_RD_STATUS_REG register
+ *  SPI1 status register.
+ */
+#define SPI1_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0x2c)
+/** SPI1_MEM_S_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
+ *  The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit.
+ */
+#define SPI1_MEM_S_STATUS    0x0000FFFFU
+#define SPI1_MEM_S_STATUS_M  (SPI1_MEM_S_STATUS_V << SPI1_MEM_S_STATUS_S)
+#define SPI1_MEM_S_STATUS_V  0x0000FFFFU
+#define SPI1_MEM_S_STATUS_S  0
+/** SPI1_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0;
+ *  Mode bits in the flash fast read mode  it is combined with spi1_mem_s_fastrd_mode bit.
+ */
+#define SPI1_MEM_S_WB_MODE    0x000000FFU
+#define SPI1_MEM_S_WB_MODE_M  (SPI1_MEM_S_WB_MODE_V << SPI1_MEM_S_WB_MODE_S)
+#define SPI1_MEM_S_WB_MODE_V  0x000000FFU
+#define SPI1_MEM_S_WB_MODE_S  16
+
+/** SPI1_MEM_S_MISC_REG register
+ *  SPI1 misc register
+ */
+#define SPI1_MEM_S_MISC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x34)
+/** SPI1_MEM_S_CS0_DIS : R/W; bitpos: [0]; default: 0;
+ *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
+ *  device, such as flash, external RAM and so on.
+ */
+#define SPI1_MEM_S_CS0_DIS    (BIT(0))
+#define SPI1_MEM_S_CS0_DIS_M  (SPI1_MEM_S_CS0_DIS_V << SPI1_MEM_S_CS0_DIS_S)
+#define SPI1_MEM_S_CS0_DIS_V  0x00000001U
+#define SPI1_MEM_S_CS0_DIS_S  0
+/** SPI1_MEM_S_CS1_DIS : R/W; bitpos: [1]; default: 1;
+ *  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
+ *  device, such as flash, external RAM and so on.
+ */
+#define SPI1_MEM_S_CS1_DIS    (BIT(1))
+#define SPI1_MEM_S_CS1_DIS_M  (SPI1_MEM_S_CS1_DIS_V << SPI1_MEM_S_CS1_DIS_S)
+#define SPI1_MEM_S_CS1_DIS_V  0x00000001U
+#define SPI1_MEM_S_CS1_DIS_S  1
+/** SPI1_MEM_S_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
+ *  1: spi clk line is high when idle     0: spi clk line is low when idle
+ */
+#define SPI1_MEM_S_CK_IDLE_EDGE    (BIT(9))
+#define SPI1_MEM_S_CK_IDLE_EDGE_M  (SPI1_MEM_S_CK_IDLE_EDGE_V << SPI1_MEM_S_CK_IDLE_EDGE_S)
+#define SPI1_MEM_S_CK_IDLE_EDGE_V  0x00000001U
+#define SPI1_MEM_S_CK_IDLE_EDGE_S  9
+/** SPI1_MEM_S_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
+ *  spi cs line keep low when the bit is set.
+ */
+#define SPI1_MEM_S_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI1_MEM_S_CS_KEEP_ACTIVE_M  (SPI1_MEM_S_CS_KEEP_ACTIVE_V << SPI1_MEM_S_CS_KEEP_ACTIVE_S)
+#define SPI1_MEM_S_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI1_MEM_S_CS_KEEP_ACTIVE_S  10
+
+/** SPI1_MEM_S_TX_CRC_REG register
+ *  SPI1 TX CRC data register.
+ */
+#define SPI1_MEM_S_TX_CRC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x38)
+/** SPI1_MEM_S_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
+ *  For SPI1, the value of crc32.
+ */
+#define SPI1_MEM_S_TX_CRC_DATA    0xFFFFFFFFU
+#define SPI1_MEM_S_TX_CRC_DATA_M  (SPI1_MEM_S_TX_CRC_DATA_V << SPI1_MEM_S_TX_CRC_DATA_S)
+#define SPI1_MEM_S_TX_CRC_DATA_V  0xFFFFFFFFU
+#define SPI1_MEM_S_TX_CRC_DATA_S  0
+
+/** SPI1_MEM_S_CACHE_FCTRL_REG register
+ *  SPI1 bit mode control register.
+ */
+#define SPI1_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3c)
+/** SPI1_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
+ *  For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
+ */
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_M  (SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S)
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V  0x00000001U
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S  1
+/** SPI1_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
+ *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
+ *  spi1_mem_s_fread_dio.
+ */
+#define SPI1_MEM_S_FDIN_DUAL    (BIT(3))
+#define SPI1_MEM_S_FDIN_DUAL_M  (SPI1_MEM_S_FDIN_DUAL_V << SPI1_MEM_S_FDIN_DUAL_S)
+#define SPI1_MEM_S_FDIN_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FDIN_DUAL_S  3
+/** SPI1_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
+ *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
+ *  with spi1_mem_s_fread_dio.
+ */
+#define SPI1_MEM_S_FDOUT_DUAL    (BIT(4))
+#define SPI1_MEM_S_FDOUT_DUAL_M  (SPI1_MEM_S_FDOUT_DUAL_V << SPI1_MEM_S_FDOUT_DUAL_S)
+#define SPI1_MEM_S_FDOUT_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FDOUT_DUAL_S  4
+/** SPI1_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+ *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
+ *  with spi1_mem_s_fread_dio.
+ */
+#define SPI1_MEM_S_FADDR_DUAL    (BIT(5))
+#define SPI1_MEM_S_FADDR_DUAL_M  (SPI1_MEM_S_FADDR_DUAL_V << SPI1_MEM_S_FADDR_DUAL_S)
+#define SPI1_MEM_S_FADDR_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FADDR_DUAL_S  5
+/** SPI1_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
+ *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+ *  with spi1_mem_s_fread_qio.
+ */
+#define SPI1_MEM_S_FDIN_QUAD    (BIT(6))
+#define SPI1_MEM_S_FDIN_QUAD_M  (SPI1_MEM_S_FDIN_QUAD_V << SPI1_MEM_S_FDIN_QUAD_S)
+#define SPI1_MEM_S_FDIN_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FDIN_QUAD_S  6
+/** SPI1_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
+ *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+ *  with spi1_mem_s_fread_qio.
+ */
+#define SPI1_MEM_S_FDOUT_QUAD    (BIT(7))
+#define SPI1_MEM_S_FDOUT_QUAD_M  (SPI1_MEM_S_FDOUT_QUAD_V << SPI1_MEM_S_FDOUT_QUAD_S)
+#define SPI1_MEM_S_FDOUT_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FDOUT_QUAD_S  7
+/** SPI1_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
+ *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+ *  with spi1_mem_s_fread_qio.
+ */
+#define SPI1_MEM_S_FADDR_QUAD    (BIT(8))
+#define SPI1_MEM_S_FADDR_QUAD_M  (SPI1_MEM_S_FADDR_QUAD_V << SPI1_MEM_S_FADDR_QUAD_S)
+#define SPI1_MEM_S_FADDR_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FADDR_QUAD_S  8
+
+/** SPI1_MEM_S_W0_REG register
+ *  SPI1 memory data buffer0
+ */
+#define SPI1_MEM_S_W0_REG (DR_REG_PSRAM_MSPI1_BASE + 0x58)
+/** SPI1_MEM_S_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF0    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF0_M  (SPI1_MEM_S_BUF0_V << SPI1_MEM_S_BUF0_S)
+#define SPI1_MEM_S_BUF0_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF0_S  0
+
+/** SPI1_MEM_S_W1_REG register
+ *  SPI1 memory data buffer1
+ */
+#define SPI1_MEM_S_W1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x5c)
+/** SPI1_MEM_S_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF1    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF1_M  (SPI1_MEM_S_BUF1_V << SPI1_MEM_S_BUF1_S)
+#define SPI1_MEM_S_BUF1_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF1_S  0
+
+/** SPI1_MEM_S_W2_REG register
+ *  SPI1 memory data buffer2
+ */
+#define SPI1_MEM_S_W2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x60)
+/** SPI1_MEM_S_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF2    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF2_M  (SPI1_MEM_S_BUF2_V << SPI1_MEM_S_BUF2_S)
+#define SPI1_MEM_S_BUF2_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF2_S  0
+
+/** SPI1_MEM_S_W3_REG register
+ *  SPI1 memory data buffer3
+ */
+#define SPI1_MEM_S_W3_REG (DR_REG_PSRAM_MSPI1_BASE + 0x64)
+/** SPI1_MEM_S_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF3    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF3_M  (SPI1_MEM_S_BUF3_V << SPI1_MEM_S_BUF3_S)
+#define SPI1_MEM_S_BUF3_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF3_S  0
+
+/** SPI1_MEM_S_W4_REG register
+ *  SPI1 memory data buffer4
+ */
+#define SPI1_MEM_S_W4_REG (DR_REG_PSRAM_MSPI1_BASE + 0x68)
+/** SPI1_MEM_S_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF4    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF4_M  (SPI1_MEM_S_BUF4_V << SPI1_MEM_S_BUF4_S)
+#define SPI1_MEM_S_BUF4_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF4_S  0
+
+/** SPI1_MEM_S_W5_REG register
+ *  SPI1 memory data buffer5
+ */
+#define SPI1_MEM_S_W5_REG (DR_REG_PSRAM_MSPI1_BASE + 0x6c)
+/** SPI1_MEM_S_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF5    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF5_M  (SPI1_MEM_S_BUF5_V << SPI1_MEM_S_BUF5_S)
+#define SPI1_MEM_S_BUF5_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF5_S  0
+
+/** SPI1_MEM_S_W6_REG register
+ *  SPI1 memory data buffer6
+ */
+#define SPI1_MEM_S_W6_REG (DR_REG_PSRAM_MSPI1_BASE + 0x70)
+/** SPI1_MEM_S_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF6    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF6_M  (SPI1_MEM_S_BUF6_V << SPI1_MEM_S_BUF6_S)
+#define SPI1_MEM_S_BUF6_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF6_S  0
+
+/** SPI1_MEM_S_W7_REG register
+ *  SPI1 memory data buffer7
+ */
+#define SPI1_MEM_S_W7_REG (DR_REG_PSRAM_MSPI1_BASE + 0x74)
+/** SPI1_MEM_S_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF7    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF7_M  (SPI1_MEM_S_BUF7_V << SPI1_MEM_S_BUF7_S)
+#define SPI1_MEM_S_BUF7_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF7_S  0
+
+/** SPI1_MEM_S_W8_REG register
+ *  SPI1 memory data buffer8
+ */
+#define SPI1_MEM_S_W8_REG (DR_REG_PSRAM_MSPI1_BASE + 0x78)
+/** SPI1_MEM_S_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF8    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF8_M  (SPI1_MEM_S_BUF8_V << SPI1_MEM_S_BUF8_S)
+#define SPI1_MEM_S_BUF8_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF8_S  0
+
+/** SPI1_MEM_S_W9_REG register
+ *  SPI1 memory data buffer9
+ */
+#define SPI1_MEM_S_W9_REG (DR_REG_PSRAM_MSPI1_BASE + 0x7c)
+/** SPI1_MEM_S_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF9    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF9_M  (SPI1_MEM_S_BUF9_V << SPI1_MEM_S_BUF9_S)
+#define SPI1_MEM_S_BUF9_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF9_S  0
+
+/** SPI1_MEM_S_W10_REG register
+ *  SPI1 memory data buffer10
+ */
+#define SPI1_MEM_S_W10_REG (DR_REG_PSRAM_MSPI1_BASE + 0x80)
+/** SPI1_MEM_S_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF10    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF10_M  (SPI1_MEM_S_BUF10_V << SPI1_MEM_S_BUF10_S)
+#define SPI1_MEM_S_BUF10_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF10_S  0
+
+/** SPI1_MEM_S_W11_REG register
+ *  SPI1 memory data buffer11
+ */
+#define SPI1_MEM_S_W11_REG (DR_REG_PSRAM_MSPI1_BASE + 0x84)
+/** SPI1_MEM_S_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF11    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF11_M  (SPI1_MEM_S_BUF11_V << SPI1_MEM_S_BUF11_S)
+#define SPI1_MEM_S_BUF11_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF11_S  0
+
+/** SPI1_MEM_S_W12_REG register
+ *  SPI1 memory data buffer12
+ */
+#define SPI1_MEM_S_W12_REG (DR_REG_PSRAM_MSPI1_BASE + 0x88)
+/** SPI1_MEM_S_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF12    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF12_M  (SPI1_MEM_S_BUF12_V << SPI1_MEM_S_BUF12_S)
+#define SPI1_MEM_S_BUF12_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF12_S  0
+
+/** SPI1_MEM_S_W13_REG register
+ *  SPI1 memory data buffer13
+ */
+#define SPI1_MEM_S_W13_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8c)
+/** SPI1_MEM_S_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF13    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF13_M  (SPI1_MEM_S_BUF13_V << SPI1_MEM_S_BUF13_S)
+#define SPI1_MEM_S_BUF13_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF13_S  0
+
+/** SPI1_MEM_S_W14_REG register
+ *  SPI1 memory data buffer14
+ */
+#define SPI1_MEM_S_W14_REG (DR_REG_PSRAM_MSPI1_BASE + 0x90)
+/** SPI1_MEM_S_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF14    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF14_M  (SPI1_MEM_S_BUF14_V << SPI1_MEM_S_BUF14_S)
+#define SPI1_MEM_S_BUF14_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF14_S  0
+
+/** SPI1_MEM_S_W15_REG register
+ *  SPI1 memory data buffer15
+ */
+#define SPI1_MEM_S_W15_REG (DR_REG_PSRAM_MSPI1_BASE + 0x94)
+/** SPI1_MEM_S_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI1_MEM_S_BUF15    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF15_M  (SPI1_MEM_S_BUF15_V << SPI1_MEM_S_BUF15_S)
+#define SPI1_MEM_S_BUF15_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF15_S  0
+
+/** SPI1_MEM_S_FLASH_WAITI_CTRL_REG register
+ *  SPI1 wait idle control register
+ */
+#define SPI1_MEM_S_FLASH_WAITI_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x98)
+/** SPI1_MEM_S_WAITI_EN : R/W; bitpos: [0]; default: 1;
+ *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
+ *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
+ *  Suspend/Resume are not supported.
+ */
+#define SPI1_MEM_S_WAITI_EN    (BIT(0))
+#define SPI1_MEM_S_WAITI_EN_M  (SPI1_MEM_S_WAITI_EN_V << SPI1_MEM_S_WAITI_EN_S)
+#define SPI1_MEM_S_WAITI_EN_V  0x00000001U
+#define SPI1_MEM_S_WAITI_EN_S  0
+/** SPI1_MEM_S_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
+ *  The dummy phase enable when wait flash idle (RDSR)
+ */
+#define SPI1_MEM_S_WAITI_DUMMY    (BIT(1))
+#define SPI1_MEM_S_WAITI_DUMMY_M  (SPI1_MEM_S_WAITI_DUMMY_V << SPI1_MEM_S_WAITI_DUMMY_S)
+#define SPI1_MEM_S_WAITI_DUMMY_V  0x00000001U
+#define SPI1_MEM_S_WAITI_DUMMY_S  1
+/** SPI1_MEM_S_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
+ *  1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out
+ *  address in RDSR or read SUS command transfer.
+ */
+#define SPI1_MEM_S_WAITI_ADDR_EN    (BIT(2))
+#define SPI1_MEM_S_WAITI_ADDR_EN_M  (SPI1_MEM_S_WAITI_ADDR_EN_V << SPI1_MEM_S_WAITI_ADDR_EN_S)
+#define SPI1_MEM_S_WAITI_ADDR_EN_V  0x00000001U
+#define SPI1_MEM_S_WAITI_ADDR_EN_S  2
+/** SPI1_MEM_S_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
+ *  When SPI1_MEM_S_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+ *  (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+ *  SPI1_MEM_S_WAITI_ADDR_EN is cleared.
+ */
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN    0x00000003U
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_M  (SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S)
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V  0x00000003U
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S  3
+/** SPI1_MEM_S_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
+ *  1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
+ */
+#define SPI1_MEM_S_WAITI_CMD_2B    (BIT(9))
+#define SPI1_MEM_S_WAITI_CMD_2B_M  (SPI1_MEM_S_WAITI_CMD_2B_V << SPI1_MEM_S_WAITI_CMD_2B_S)
+#define SPI1_MEM_S_WAITI_CMD_2B_V  0x00000001U
+#define SPI1_MEM_S_WAITI_CMD_2B_S  9
+/** SPI1_MEM_S_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
+ *  The dummy cycle length when wait flash idle(RDSR).
+ */
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_M  (SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_S  10
+/** SPI1_MEM_S_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
+ *  The command value to wait flash idle(RDSR).
+ */
+#define SPI1_MEM_S_WAITI_CMD    0x0000FFFFU
+#define SPI1_MEM_S_WAITI_CMD_M  (SPI1_MEM_S_WAITI_CMD_V << SPI1_MEM_S_WAITI_CMD_S)
+#define SPI1_MEM_S_WAITI_CMD_V  0x0000FFFFU
+#define SPI1_MEM_S_WAITI_CMD_S  16
+
+/** SPI1_MEM_S_FLASH_SUS_CTRL_REG register
+ *  SPI1 flash suspend control register
+ */
+#define SPI1_MEM_S_FLASH_SUS_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x9c)
+/** SPI1_MEM_S_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
+ *  program erase resume bit, program erase suspend operation will be triggered when
+ *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
+ *  disable.
+ */
+#define SPI1_MEM_S_FLASH_PER    (BIT(0))
+#define SPI1_MEM_S_FLASH_PER_M  (SPI1_MEM_S_FLASH_PER_V << SPI1_MEM_S_FLASH_PER_S)
+#define SPI1_MEM_S_FLASH_PER_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PER_S  0
+/** SPI1_MEM_S_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
+ *  program erase suspend bit, program erase suspend operation will be triggered when
+ *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
+ *  disable.
+ */
+#define SPI1_MEM_S_FLASH_PES    (BIT(1))
+#define SPI1_MEM_S_FLASH_PES_M  (SPI1_MEM_S_FLASH_PES_V << SPI1_MEM_S_FLASH_PES_S)
+#define SPI1_MEM_S_FLASH_PES_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_S  1
+/** SPI1_MEM_S_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+ *  program erase resume command is sent. 0: SPI1 does not wait after program erase
+ *  resume command is sent.
+ */
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN_M  (SPI1_MEM_S_FLASH_PER_WAIT_EN_V << SPI1_MEM_S_FLASH_PER_WAIT_EN_S)
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN_S  2
+/** SPI1_MEM_S_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+ *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
+ *  suspend command is sent.
+ */
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN_M  (SPI1_MEM_S_FLASH_PES_WAIT_EN_V << SPI1_MEM_S_FLASH_PES_WAIT_EN_S)
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN_S  3
+/** SPI1_MEM_S_PES_PER_EN : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
+ *  application should send PER after PES is done.
+ */
+#define SPI1_MEM_S_PES_PER_EN    (BIT(4))
+#define SPI1_MEM_S_PES_PER_EN_M  (SPI1_MEM_S_PES_PER_EN_V << SPI1_MEM_S_PES_PER_EN_S)
+#define SPI1_MEM_S_PES_PER_EN_V  0x00000001U
+#define SPI1_MEM_S_PES_PER_EN_S  4
+/** SPI1_MEM_S_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to enable Auto-suspending function.
+ */
+#define SPI1_MEM_S_FLASH_PES_EN    (BIT(5))
+#define SPI1_MEM_S_FLASH_PES_EN_M  (SPI1_MEM_S_FLASH_PES_EN_V << SPI1_MEM_S_FLASH_PES_EN_S)
+#define SPI1_MEM_S_FLASH_PES_EN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_EN_S  5
+/** SPI1_MEM_S_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
+ *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+ *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+ *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
+ *  status_in[15:0]^ SPI1_MEM_S_PESR_END_MSK[15:0].
+ */
+#define SPI1_MEM_S_PESR_END_MSK    0x0000FFFFU
+#define SPI1_MEM_S_PESR_END_MSK_M  (SPI1_MEM_S_PESR_END_MSK_V << SPI1_MEM_S_PESR_END_MSK_S)
+#define SPI1_MEM_S_PESR_END_MSK_V  0x0000FFFFU
+#define SPI1_MEM_S_PESR_END_MSK_S  6
+/** SPI1_MEM_S_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
+ *  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when
+ *  check flash SUS/SUS1/SUS2 status bit
+ */
+#define SPI1_MEM_S_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI1_MEM_S_FMEM_RD_SUS_2B_M  (SPI1_MEM_S_FMEM_RD_SUS_2B_V << SPI1_MEM_S_FMEM_RD_SUS_2B_S)
+#define SPI1_MEM_S_FMEM_RD_SUS_2B_V  0x00000001U
+#define SPI1_MEM_S_FMEM_RD_SUS_2B_S  22
+/** SPI1_MEM_S_PER_END_EN : R/W; bitpos: [23]; default: 0;
+ *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
+ *  flash. 0: Only need to check WIP is 0.
+ */
+#define SPI1_MEM_S_PER_END_EN    (BIT(23))
+#define SPI1_MEM_S_PER_END_EN_M  (SPI1_MEM_S_PER_END_EN_V << SPI1_MEM_S_PER_END_EN_S)
+#define SPI1_MEM_S_PER_END_EN_V  0x00000001U
+#define SPI1_MEM_S_PER_END_EN_S  23
+/** SPI1_MEM_S_PES_END_EN : R/W; bitpos: [24]; default: 0;
+ *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status
+ *  of flash. 0: Only need to check WIP is 0.
+ */
+#define SPI1_MEM_S_PES_END_EN    (BIT(24))
+#define SPI1_MEM_S_PES_END_EN_M  (SPI1_MEM_S_PES_END_EN_V << SPI1_MEM_S_PES_END_EN_S)
+#define SPI1_MEM_S_PES_END_EN_V  0x00000001U
+#define SPI1_MEM_S_PES_END_EN_S  24
+/** SPI1_MEM_S_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
+ *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it
+ *  will be treated as check pass.
+ */
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT    0x0000007FU
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT_M  (SPI1_MEM_S_SUS_TIMEOUT_CNT_V << SPI1_MEM_S_SUS_TIMEOUT_CNT_S)
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT_V  0x0000007FU
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT_S  25
+
+/** SPI1_MEM_S_FLASH_SUS_CMD_REG register
+ *  SPI1 flash suspend command register
+ */
+#define SPI1_MEM_S_FLASH_SUS_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa0)
+/** SPI1_MEM_S_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
+ *  Program/Erase suspend command.
+ */
+#define SPI1_MEM_S_FLASH_PES_COMMAND    0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PES_COMMAND_M  (SPI1_MEM_S_FLASH_PES_COMMAND_V << SPI1_MEM_S_FLASH_PES_COMMAND_S)
+#define SPI1_MEM_S_FLASH_PES_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PES_COMMAND_S  0
+/** SPI1_MEM_S_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
+ *  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
+ *  SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
+ */
+#define SPI1_MEM_S_WAIT_PESR_COMMAND    0x0000FFFFU
+#define SPI1_MEM_S_WAIT_PESR_COMMAND_M  (SPI1_MEM_S_WAIT_PESR_COMMAND_V << SPI1_MEM_S_WAIT_PESR_COMMAND_S)
+#define SPI1_MEM_S_WAIT_PESR_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_S_WAIT_PESR_COMMAND_S  16
+
+/** SPI1_MEM_S_SUS_STATUS_REG register
+ *  SPI1 flash suspend status register
+ */
+#define SPI1_MEM_S_SUS_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa4)
+/** SPI1_MEM_S_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
+ *  The status of flash suspend, only used in SPI1.
+ */
+#define SPI1_MEM_S_FLASH_SUS    (BIT(0))
+#define SPI1_MEM_S_FLASH_SUS_M  (SPI1_MEM_S_FLASH_SUS_V << SPI1_MEM_S_FLASH_SUS_S)
+#define SPI1_MEM_S_FLASH_SUS_V  0x00000001U
+#define SPI1_MEM_S_FLASH_SUS_S  0
+/** SPI1_MEM_S_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
+ *  1: SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ *  SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+ */
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B_M  (SPI1_MEM_S_WAIT_PESR_CMD_2B_V << SPI1_MEM_S_WAIT_PESR_CMD_2B_S)
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B_S  1
+/** SPI1_MEM_S_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ *  after HPM command is sent.
+ */
+#define SPI1_MEM_S_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI1_MEM_S_FLASH_HPM_DLY_128_M  (SPI1_MEM_S_FLASH_HPM_DLY_128_V << SPI1_MEM_S_FLASH_HPM_DLY_128_S)
+#define SPI1_MEM_S_FLASH_HPM_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_HPM_DLY_128_S  2
+/** SPI1_MEM_S_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ *  after RES command is sent.
+ */
+#define SPI1_MEM_S_FLASH_RES_DLY_128    (BIT(3))
+#define SPI1_MEM_S_FLASH_RES_DLY_128_M  (SPI1_MEM_S_FLASH_RES_DLY_128_V << SPI1_MEM_S_FLASH_RES_DLY_128_S)
+#define SPI1_MEM_S_FLASH_RES_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RES_DLY_128_S  3
+/** SPI1_MEM_S_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ *  after DP command is sent.
+ */
+#define SPI1_MEM_S_FLASH_DP_DLY_128    (BIT(4))
+#define SPI1_MEM_S_FLASH_DP_DLY_128_M  (SPI1_MEM_S_FLASH_DP_DLY_128_V << SPI1_MEM_S_FLASH_DP_DLY_128_S)
+#define SPI1_MEM_S_FLASH_DP_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_DP_DLY_128_S  4
+/** SPI1_MEM_S_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
+ *  Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+ *  sent.
+ */
+#define SPI1_MEM_S_FLASH_PER_DLY_128    (BIT(5))
+#define SPI1_MEM_S_FLASH_PER_DLY_128_M  (SPI1_MEM_S_FLASH_PER_DLY_128_V << SPI1_MEM_S_FLASH_PER_DLY_128_S)
+#define SPI1_MEM_S_FLASH_PER_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PER_DLY_128_S  5
+/** SPI1_MEM_S_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
+ *  Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+ *  sent.
+ */
+#define SPI1_MEM_S_FLASH_PES_DLY_128    (BIT(6))
+#define SPI1_MEM_S_FLASH_PES_DLY_128_M  (SPI1_MEM_S_FLASH_PES_DLY_128_V << SPI1_MEM_S_FLASH_PES_DLY_128_S)
+#define SPI1_MEM_S_FLASH_PES_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_DLY_128_S  6
+/** SPI1_MEM_S_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
+ *  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
+ */
+#define SPI1_MEM_S_SPI0_LOCK_EN    (BIT(7))
+#define SPI1_MEM_S_SPI0_LOCK_EN_M  (SPI1_MEM_S_SPI0_LOCK_EN_V << SPI1_MEM_S_SPI0_LOCK_EN_S)
+#define SPI1_MEM_S_SPI0_LOCK_EN_V  0x00000001U
+#define SPI1_MEM_S_SPI0_LOCK_EN_S  7
+/** SPI1_MEM_S_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
+ *  1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length
+ *  of Program/Erase Suspend/Resume command is 8.
+ */
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B    (BIT(15))
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B_M  (SPI1_MEM_S_FLASH_PESR_CMD_2B_V << SPI1_MEM_S_FLASH_PESR_CMD_2B_S)
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B_S  15
+/** SPI1_MEM_S_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
+ *  Program/Erase resume command.
+ */
+#define SPI1_MEM_S_FLASH_PER_COMMAND    0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PER_COMMAND_M  (SPI1_MEM_S_FLASH_PER_COMMAND_V << SPI1_MEM_S_FLASH_PER_COMMAND_S)
+#define SPI1_MEM_S_FLASH_PER_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PER_COMMAND_S  16
+
+/** SPI1_MEM_S_INT_ENA_REG register
+ *  SPI1 interrupt enable register
+ */
+#define SPI1_MEM_S_INT_ENA_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc0)
+/** SPI1_MEM_S_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for SPI1_MEM_S_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PER_END_INT_ENA    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_ENA_M  (SPI1_MEM_S_PER_END_INT_ENA_V << SPI1_MEM_S_PER_END_INT_ENA_S)
+#define SPI1_MEM_S_PER_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_ENA_S  0
+/** SPI1_MEM_S_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for SPI1_MEM_S_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PES_END_INT_ENA    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_ENA_M  (SPI1_MEM_S_PES_END_INT_ENA_V << SPI1_MEM_S_PES_END_INT_ENA_S)
+#define SPI1_MEM_S_PES_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_ENA_S  1
+/** SPI1_MEM_S_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for SPI1_MEM_S_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_S_WPE_END_INT_ENA    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_ENA_M  (SPI1_MEM_S_WPE_END_INT_ENA_V << SPI1_MEM_S_WPE_END_INT_ENA_S)
+#define SPI1_MEM_S_WPE_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_ENA_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA_M  (SPI1_MEM_S_SLV_ST_END_INT_ENA_V << SPI1_MEM_S_SLV_ST_END_INT_ENA_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_ENA_M  (SPI1_MEM_S_MST_ST_END_INT_ENA_V << SPI1_MEM_S_MST_ST_END_INT_ENA_S)
+#define SPI1_MEM_S_MST_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_ENA_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA_M  (SPI1_MEM_S_BROWN_OUT_INT_ENA_V << SPI1_MEM_S_BROWN_OUT_INT_ENA_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA_S  10
+
+/** SPI1_MEM_S_INT_CLR_REG register
+ *  SPI1 interrupt clear register
+ */
+#define SPI1_MEM_S_INT_CLR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc4)
+/** SPI1_MEM_S_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for SPI1_MEM_S_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PER_END_INT_CLR    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_CLR_M  (SPI1_MEM_S_PER_END_INT_CLR_V << SPI1_MEM_S_PER_END_INT_CLR_S)
+#define SPI1_MEM_S_PER_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_CLR_S  0
+/** SPI1_MEM_S_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for SPI1_MEM_S_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PES_END_INT_CLR    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_CLR_M  (SPI1_MEM_S_PES_END_INT_CLR_V << SPI1_MEM_S_PES_END_INT_CLR_S)
+#define SPI1_MEM_S_PES_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_CLR_S  1
+/** SPI1_MEM_S_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for SPI1_MEM_S_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_S_WPE_END_INT_CLR    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_CLR_M  (SPI1_MEM_S_WPE_END_INT_CLR_V << SPI1_MEM_S_WPE_END_INT_CLR_S)
+#define SPI1_MEM_S_WPE_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_CLR_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR_M  (SPI1_MEM_S_SLV_ST_END_INT_CLR_V << SPI1_MEM_S_SLV_ST_END_INT_CLR_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_CLR_M  (SPI1_MEM_S_MST_ST_END_INT_CLR_V << SPI1_MEM_S_MST_ST_END_INT_CLR_S)
+#define SPI1_MEM_S_MST_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_CLR_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR_M  (SPI1_MEM_S_BROWN_OUT_INT_CLR_V << SPI1_MEM_S_BROWN_OUT_INT_CLR_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR_S  10
+
+/** SPI1_MEM_S_INT_RAW_REG register
+ *  SPI1 interrupt raw register
+ */
+#define SPI1_MEM_S_INT_RAW_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc8)
+/** SPI1_MEM_S_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit for SPI1_MEM_S_PER_END_INT interrupt. 1: Triggered when Auto Resume
+ *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
+ */
+#define SPI1_MEM_S_PER_END_INT_RAW    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_RAW_M  (SPI1_MEM_S_PER_END_INT_RAW_V << SPI1_MEM_S_PER_END_INT_RAW_S)
+#define SPI1_MEM_S_PER_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_RAW_S  0
+/** SPI1_MEM_S_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit for SPI1_MEM_S_PES_END_INT interrupt.1: Triggered when Auto Suspend
+ *  command (0x75) is sent and flash is suspended successfully. 0: Others.
+ */
+#define SPI1_MEM_S_PES_END_INT_RAW    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_RAW_M  (SPI1_MEM_S_PES_END_INT_RAW_V << SPI1_MEM_S_PES_END_INT_RAW_S)
+#define SPI1_MEM_S_PES_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_RAW_S  1
+/** SPI1_MEM_S_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+ *  is sent and flash is already idle. 0: Others.
+ */
+#define SPI1_MEM_S_WPE_END_INT_RAW    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_RAW_M  (SPI1_MEM_S_WPE_END_INT_RAW_V << SPI1_MEM_S_WPE_END_INT_RAW_S)
+#define SPI1_MEM_S_WPE_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_RAW_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+ *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
+ *  Others
+ */
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW_M  (SPI1_MEM_S_SLV_ST_END_INT_RAW_V << SPI1_MEM_S_SLV_ST_END_INT_RAW_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+ *  changed from non idle state to idle state. 0: Others.
+ */
+#define SPI1_MEM_S_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_RAW_M  (SPI1_MEM_S_MST_ST_END_INT_RAW_V << SPI1_MEM_S_MST_ST_END_INT_RAW_S)
+#define SPI1_MEM_S_MST_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_RAW_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+ *  chip is losing power and RTC module sends out brown out close flash request to
+ *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
+ *  and MSPI returns to idle state. 0: Others.
+ */
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW_M  (SPI1_MEM_S_BROWN_OUT_INT_RAW_V << SPI1_MEM_S_BROWN_OUT_INT_RAW_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW_S  10
+
+/** SPI1_MEM_S_INT_ST_REG register
+ *  SPI1 interrupt status register
+ */
+#define SPI1_MEM_S_INT_ST_REG (DR_REG_PSRAM_MSPI1_BASE + 0xcc)
+/** SPI1_MEM_S_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for SPI1_MEM_S_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PER_END_INT_ST    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_ST_M  (SPI1_MEM_S_PER_END_INT_ST_V << SPI1_MEM_S_PER_END_INT_ST_S)
+#define SPI1_MEM_S_PER_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_ST_S  0
+/** SPI1_MEM_S_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for SPI1_MEM_S_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PES_END_INT_ST    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_ST_M  (SPI1_MEM_S_PES_END_INT_ST_V << SPI1_MEM_S_PES_END_INT_ST_S)
+#define SPI1_MEM_S_PES_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_ST_S  1
+/** SPI1_MEM_S_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for SPI1_MEM_S_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_S_WPE_END_INT_ST    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_ST_M  (SPI1_MEM_S_WPE_END_INT_ST_V << SPI1_MEM_S_WPE_END_INT_ST_S)
+#define SPI1_MEM_S_WPE_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_ST_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_ST_M  (SPI1_MEM_S_SLV_ST_END_INT_ST_V << SPI1_MEM_S_SLV_ST_END_INT_ST_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_ST_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_MST_ST_END_INT_ST    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_ST_M  (SPI1_MEM_S_MST_ST_END_INT_ST_V << SPI1_MEM_S_MST_ST_END_INT_ST_S)
+#define SPI1_MEM_S_MST_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_ST_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_S_BROWN_OUT_INT_ST    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_ST_M  (SPI1_MEM_S_BROWN_OUT_INT_ST_V << SPI1_MEM_S_BROWN_OUT_INT_ST_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_ST_S  10
+
+/** SPI1_MEM_S_DDR_REG register
+ *  SPI1 DDR control register
+ */
+#define SPI1_MEM_S_DDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xd4)
+/** SPI1_MEM_S_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
+ *  1: in ddr mode,  0 in sdr mode
+ */
+#define SPI1_MEM_S_FMEM_DDR_EN    (BIT(0))
+#define SPI1_MEM_S_FMEM_DDR_EN_M  (SPI1_MEM_S_FMEM_DDR_EN_V << SPI1_MEM_S_FMEM_DDR_EN_S)
+#define SPI1_MEM_S_FMEM_DDR_EN_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_EN_S  0
+/** SPI1_MEM_S_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
+ *  Set the bit to enable variable dummy cycle in spi ddr mode.
+ */
+#define SPI1_MEM_S_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI1_MEM_S_FMEM_VAR_DUMMY_M  (SPI1_MEM_S_FMEM_VAR_DUMMY_V << SPI1_MEM_S_FMEM_VAR_DUMMY_S)
+#define SPI1_MEM_S_FMEM_VAR_DUMMY_V  0x00000001U
+#define SPI1_MEM_S_FMEM_VAR_DUMMY_S  1
+/** SPI1_MEM_S_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
+ *  Set the bit to reorder rx data of the word in spi ddr mode.
+ */
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_M  (SPI1_MEM_S_FMEM_DDR_RDAT_SWP_V << SPI1_MEM_S_FMEM_DDR_RDAT_SWP_S)
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_S  2
+/** SPI1_MEM_S_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
+ *  Set the bit to reorder tx data of the word in spi ddr mode.
+ */
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_M  (SPI1_MEM_S_FMEM_DDR_WDAT_SWP_V << SPI1_MEM_S_FMEM_DDR_WDAT_SWP_S)
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_S  3
+/** SPI1_MEM_S_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
+ *  the bit is used to disable dual edge in command phase when ddr mode.
+ */
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_M  (SPI1_MEM_S_FMEM_DDR_CMD_DIS_V << SPI1_MEM_S_FMEM_DDR_CMD_DIS_S)
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_S  4
+/** SPI1_MEM_S_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
+ *  It is the minimum output data length in the panda device.
+ */
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_M  (SPI1_MEM_S_FMEM_OUTMINBYTELEN_V << SPI1_MEM_S_FMEM_OUTMINBYTELEN_S)
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_S  5
+/** SPI1_MEM_S_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
+ *  The delay number of data strobe which from memory based on SPI clock.
+ */
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_M  (SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_V << SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S)
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S  14
+/** SPI1_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
+ *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+ *  spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
+ *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+ *  negative edge of SPI_DQS.
+ */
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_M  (SPI1_MEM_S_FMEM_DDR_DQS_LOOP_V << SPI1_MEM_S_FMEM_DDR_DQS_LOOP_S)
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_S  21
+/** SPI1_MEM_S_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
+ *  Set this bit to enable the differential SPI_CLK#.
+ */
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_M  (SPI1_MEM_S_FMEM_CLK_DIFF_EN_V << SPI1_MEM_S_FMEM_CLK_DIFF_EN_S)
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_S  24
+/** SPI1_MEM_S_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+ */
+#define SPI1_MEM_S_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI1_MEM_S_FMEM_DQS_CA_IN_M  (SPI1_MEM_S_FMEM_DQS_CA_IN_V << SPI1_MEM_S_FMEM_DQS_CA_IN_S)
+#define SPI1_MEM_S_FMEM_DQS_CA_IN_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DQS_CA_IN_S  26
+/** SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+ *  accesses flash or SPI1 accesses flash or sram.
+ */
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_M  (SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V << SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI1_MEM_S_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to invert SPI_DIFF when accesses to flash. .
+ */
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_M  (SPI1_MEM_S_FMEM_CLK_DIFF_INV_V << SPI1_MEM_S_FMEM_CLK_DIFF_INV_S)
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_S  28
+/** SPI1_MEM_S_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
+ *  Set this bit to enable octa_ram address out when accesses to flash, which means
+ *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
+ */
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_M  (SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_V << SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_S)
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_S  29
+/** SPI1_MEM_S_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to enable HyperRAM address out when accesses to flash, which means
+ *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+ */
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA_M  (SPI1_MEM_S_FMEM_HYPERBUS_CA_V << SPI1_MEM_S_FMEM_HYPERBUS_CA_S)
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA_S  30
+
+/** SPI1_MEM_S_TIMING_CALI_REG register
+ *  SPI1 timing control register
+ */
+#define SPI1_MEM_S_TIMING_CALI_REG (DR_REG_PSRAM_MSPI1_BASE + 0x180)
+/** SPI1_MEM_S_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable timing auto-calibration for all reading operations.
+ */
+#define SPI1_MEM_S_TIMING_CALI    (BIT(1))
+#define SPI1_MEM_S_TIMING_CALI_M  (SPI1_MEM_S_TIMING_CALI_V << SPI1_MEM_S_TIMING_CALI_S)
+#define SPI1_MEM_S_TIMING_CALI_V  0x00000001U
+#define SPI1_MEM_S_TIMING_CALI_S  1
+/** SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+ *  add extra dummy spi clock cycle length for spi clock calibration.
+ */
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_M  (SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_S  2
+
+/** SPI1_MEM_S_CLOCK_GATE_REG register
+ *  SPI1 clk_gate register
+ */
+#define SPI1_MEM_S_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x200)
+/** SPI1_MEM_S_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Register clock gate enable signal. 1: Enable. 0: Disable.
+ */
+#define SPI1_MEM_S_CLK_EN    (BIT(0))
+#define SPI1_MEM_S_CLK_EN_M  (SPI1_MEM_S_CLK_EN_V << SPI1_MEM_S_CLK_EN_S)
+#define SPI1_MEM_S_CLK_EN_V  0x00000001U
+#define SPI1_MEM_S_CLK_EN_S  0
+
+/** SPI1_MEM_S_DATE_REG register
+ *  Version control register
+ */
+#define SPI1_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3fc)
+/** SPI1_MEM_S_DATE : R/W; bitpos: [27:0]; default: 34673216;
+ *  Version control register
+ */
+#define SPI1_MEM_S_DATE    0x0FFFFFFFU
+#define SPI1_MEM_S_DATE_M  (SPI1_MEM_S_DATE_V << SPI1_MEM_S_DATE_S)
+#define SPI1_MEM_S_DATE_V  0x0FFFFFFFU
+#define SPI1_MEM_S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h
new file mode 100644
index 0000000000..756985a047
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h
@@ -0,0 +1,1270 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: User-defined control registers */
+/** Type of cmd register
+ *  SPI1 memory command register
+ */
+typedef union {
+    struct {
+        /** mst_st : RO; bitpos: [3:0]; default: 0;
+         *  The current status of SPI1 master FSM.
+         */
+        uint32_t mst_st:4;
+        /** slv_st : RO; bitpos: [7:4]; default: 0;
+         *  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state,
+         *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
+         *  6:write data state, 7: done state, 8: read data end state.
+         */
+        uint32_t slv_st:4;
+        uint32_t reserved_8:9;
+        /** flash_pe : R/W/SC; bitpos: [17]; default: 0;
+         *  In user mode, it is set to indicate that program/erase operation will be triggered.
+         *  The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the
+         *  operation done.1: enable 0: disable.
+         */
+        uint32_t flash_pe:1;
+        /** usr : R/W/SC; bitpos: [18]; default: 0;
+         *  User define command enable.  An operation will be triggered when the bit is set.
+         *  The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t usr:1;
+        /** flash_hpm : R/W/SC; bitpos: [19]; default: 0;
+         *  Drive Flash into high performance mode.  The bit will be cleared once the operation
+         *  done.1: enable 0: disable.
+         */
+        uint32_t flash_hpm:1;
+        /** flash_res : R/W/SC; bitpos: [20]; default: 0;
+         *  This bit combined with reg_resandres bit releases Flash from the power-down state
+         *  or high performance mode and obtains the devices ID. The bit will be cleared once
+         *  the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_res:1;
+        /** flash_dp : R/W/SC; bitpos: [21]; default: 0;
+         *  Drive Flash into power down.  An operation will be triggered when the bit is set.
+         *  The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_dp:1;
+        /** flash_ce : R/W/SC; bitpos: [22]; default: 0;
+         *  Chip erase enable. Chip erase operation will be triggered when the bit is set. The
+         *  bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_ce:1;
+        /** flash_be : R/W/SC; bitpos: [23]; default: 0;
+         *  Block erase enable(32KB) .  Block erase operation will be triggered when the bit is
+         *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_be:1;
+        /** flash_se : R/W/SC; bitpos: [24]; default: 0;
+         *  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
+         *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_se:1;
+        /** flash_pp : R/W/SC; bitpos: [25]; default: 0;
+         *  Page program enable(1 byte ~256 bytes data to be programmed). Page program
+         *  operation  will be triggered when the bit is set. The bit will be cleared once the
+         *  operation done .1: enable 0: disable.
+         */
+        uint32_t flash_pp:1;
+        /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0;
+         *  Write status register enable.   Write status operation  will be triggered when the
+         *  bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_wrsr:1;
+        /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0;
+         *  Read status register-1.  Read status operation will be triggered when the bit is
+         *  set. The bit will be cleared once the operation done.1: enable 0: disable.
+         */
+        uint32_t flash_rdsr:1;
+        /** flash_rdid : R/W/SC; bitpos: [28]; default: 0;
+         *  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
+         *  cleared once the operation done. 1: enable 0: disable.
+         */
+        uint32_t flash_rdid:1;
+        /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0;
+         *  Write flash disable. Write disable command will be sent when the bit is set. The
+         *  bit will be cleared once the operation done. 1: enable 0: disable.
+         */
+        uint32_t flash_wrdi:1;
+        /** flash_wren : R/W/SC; bitpos: [30]; default: 0;
+         *  Write flash enable.  Write enable command will be sent when the bit is set. The bit
+         *  will be cleared once the operation done. 1: enable 0: disable.
+         */
+        uint32_t flash_wren:1;
+        /** flash_read : R/W/SC; bitpos: [31]; default: 0;
+         *  Read flash enable. Read flash operation will be triggered when the bit is set. The
+         *  bit will be cleared once the operation done. 1: enable 0: disable.
+         */
+        uint32_t flash_read:1;
+    };
+    uint32_t val;
+} spi1_mem_s_cmd_reg_t;
+
+/** Type of addr register
+ *  SPI1 address register
+ */
+typedef union {
+    struct {
+        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
+         *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
+         *  address, the bit24-bit31 are the byte length of a transfer.
+         */
+        uint32_t usr_addr_value:32;
+    };
+    uint32_t val;
+} spi1_mem_s_addr_reg_t;
+
+/** Type of user register
+ *  SPI1 user register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode.
+         */
+        uint32_t ck_out_edge:1;
+        uint32_t reserved_10:2;
+        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
+         *  In the write operations read-data phase apply 2 signals
+         */
+        uint32_t fwrite_dual:1;
+        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
+         *  In the write operations read-data phase apply 4 signals
+         */
+        uint32_t fwrite_quad:1;
+        /** fwrite_dio : R/W; bitpos: [14]; default: 0;
+         *  In the write operations address phase and read-data phase apply 2 signals.
+         */
+        uint32_t fwrite_dio:1;
+        /** fwrite_qio : R/W; bitpos: [15]; default: 0;
+         *  In the write operations address phase and read-data phase apply 4 signals.
+         */
+        uint32_t fwrite_qio:1;
+        uint32_t reserved_16:8;
+        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
+         *  read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
+         *  enable 0: disable.
+         */
+        uint32_t usr_miso_highpart:1;
+        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
+         *  write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
+         *  enable 0: disable.
+         */
+        uint32_t usr_mosi_highpart:1;
+        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  SPI clock is disable in dummy phase when the bit is enable.
+         */
+        uint32_t usr_dummy_idle:1;
+        /** usr_mosi : R/W; bitpos: [27]; default: 0;
+         *  This bit enable the write-data phase of an operation.
+         */
+        uint32_t usr_mosi:1;
+        /** usr_miso : R/W; bitpos: [28]; default: 0;
+         *  This bit enable the read-data phase of an operation.
+         */
+        uint32_t usr_miso:1;
+        /** usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  This bit enable the dummy phase of an operation.
+         */
+        uint32_t usr_dummy:1;
+        /** usr_addr : R/W; bitpos: [30]; default: 0;
+         *  This bit enable the address phase of an operation.
+         */
+        uint32_t usr_addr:1;
+        /** usr_command : R/W; bitpos: [31]; default: 1;
+         *  This bit enable the command phase of an operation.
+         */
+        uint32_t usr_command:1;
+    };
+    uint32_t val;
+} spi1_mem_s_user_reg_t;
+
+/** Type of user1 register
+ *  SPI1 user1 register.
+ */
+typedef union {
+    struct {
+        /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
+         *  The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be
+         *  (cycle_num-1).
+         */
+        uint32_t usr_dummy_cyclelen:6;
+        uint32_t reserved_6:20;
+        /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23;
+         *  The length in bits of address phase. The register value shall be (bit_num-1).
+         */
+        uint32_t usr_addr_bitlen:6;
+    };
+    uint32_t val;
+} spi1_mem_s_user1_reg_t;
+
+/** Type of user2 register
+ *  SPI1 user2 register.
+ */
+typedef union {
+    struct {
+        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  The value of  command.
+         */
+        uint32_t usr_command_value:16;
+        uint32_t reserved_16:12;
+        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  The length in bits of command phase. The register value shall be (bit_num-1)
+         */
+        uint32_t usr_command_bitlen:4;
+    };
+    uint32_t val;
+} spi1_mem_s_user2_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of ctrl register
+ *  SPI1 control register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** fdummy_rin : R/W; bitpos: [2]; default: 1;
+         *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
+         *  level of SPI bus is output by the MSPI controller.
+         */
+        uint32_t fdummy_rin:1;
+        /** fdummy_wout : R/W; bitpos: [3]; default: 1;
+         *  In the dummy phase of a MSPI write data transfer when accesses to flash, the signal
+         *  level of SPI bus is output by the MSPI controller.
+         */
+        uint32_t fdummy_wout:1;
+        /** fdout_oct : R/W; bitpos: [4]; default: 0;
+         *  Apply 8 signals during write-data phase 1:enable 0: disable
+         */
+        uint32_t fdout_oct:1;
+        /** fdin_oct : R/W; bitpos: [5]; default: 0;
+         *  Apply 8 signals during read-data phase 1:enable 0: disable
+         */
+        uint32_t fdin_oct:1;
+        /** faddr_oct : R/W; bitpos: [6]; default: 0;
+         *  Apply 8 signals during address phase 1:enable 0: disable
+         */
+        uint32_t faddr_oct:1;
+        uint32_t reserved_7:1;
+        /** fcmd_quad : R/W; bitpos: [8]; default: 0;
+         *  Apply 4 signals during command phase 1:enable 0: disable
+         */
+        uint32_t fcmd_quad:1;
+        /** fcmd_oct : R/W; bitpos: [9]; default: 0;
+         *  Apply 8 signals during command phase 1:enable 0: disable
+         */
+        uint32_t fcmd_oct:1;
+        /** fcs_crc_en : R/W; bitpos: [10]; default: 0;
+         *  For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
+         *  low.
+         */
+        uint32_t fcs_crc_en:1;
+        /** tx_crc_en : R/W; bitpos: [11]; default: 0;
+         *  For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+         */
+        uint32_t tx_crc_en:1;
+        uint32_t reserved_12:1;
+        /** fastrd_mode : R/W; bitpos: [13]; default: 1;
+         *  This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout
+         *  and spi1_mem_s_fread_dout. 1: enable 0: disable.
+         */
+        uint32_t fastrd_mode:1;
+        /** fread_dual : R/W; bitpos: [14]; default: 0;
+         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+         */
+        uint32_t fread_dual:1;
+        /** resandres : R/W; bitpos: [15]; default: 1;
+         *  The Device ID is read out to SPI1_MEM_S_RD_STATUS register,  this bit combine with
+         *  spi1_mem_s_flash_res bit. 1: enable 0: disable.
+         */
+        uint32_t resandres:1;
+        uint32_t reserved_16:2;
+        /** q_pol : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to set MISO line polarity, 1: high 0, low
+         */
+        uint32_t q_pol:1;
+        /** d_pol : R/W; bitpos: [19]; default: 1;
+         *  The bit is used to set MOSI line polarity, 1: high 0, low
+         */
+        uint32_t d_pol:1;
+        /** fread_quad : R/W; bitpos: [20]; default: 0;
+         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+         */
+        uint32_t fread_quad:1;
+        /** wp_reg : R/W; bitpos: [21]; default: 1;
+         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
+         */
+        uint32_t wp_reg:1;
+        /** wrsr_2b : R/W; bitpos: [22]; default: 0;
+         *  two bytes data will be written to status register when it is set. 1: enable 0:
+         *  disable.
+         */
+        uint32_t wrsr_2b:1;
+        /** fread_dio : R/W; bitpos: [23]; default: 0;
+         *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
+         *  0: disable.
+         */
+        uint32_t fread_dio:1;
+        /** fread_qio : R/W; bitpos: [24]; default: 0;
+         *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
+         *  0: disable.
+         */
+        uint32_t fread_qio:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} spi1_mem_s_ctrl_reg_t;
+
+/** Type of ctrl1 register
+ *  SPI1 control1 register.
+ */
+typedef union {
+    struct {
+        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on.
+         */
+        uint32_t clk_mode:2;
+        /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
+         *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512)
+         *  SPI_CLK cycles.
+         */
+        uint32_t cs_hold_dly_res:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} spi1_mem_s_ctrl1_reg_t;
+
+/** Type of ctrl2 register
+ *  SPI1 control2 register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** sync_reset : WT; bitpos: [31]; default: 0;
+         *  The FSM will be reset.
+         */
+        uint32_t sync_reset:1;
+    };
+    uint32_t val;
+} spi1_mem_s_ctrl2_reg_t;
+
+/** Type of clock register
+ *  SPI1 clock division control register.
+ */
+typedef union {
+    struct {
+        /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
+         *  In the master mode it must be equal to spi1_mem_s_clkcnt_N.
+         */
+        uint32_t clkcnt_l:8;
+        /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
+         *  In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1).
+         */
+        uint32_t clkcnt_h:8;
+        /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
+         *  In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is
+         *  system/(spi1_mem_s_clkcnt_N+1)
+         */
+        uint32_t clkcnt_n:8;
+        uint32_t reserved_24:7;
+        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi1_mem_s_clock_reg_t;
+
+/** Type of mosi_dlen register
+ *  SPI1 send data bit length control register.
+ */
+typedef union {
+    struct {
+        /** usr_mosi_dbitlen : R/W; bitpos: [9:0]; default: 0;
+         *  The length in bits of write-data. The register value shall be (bit_num-1).
+         */
+        uint32_t usr_mosi_dbitlen:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} spi1_mem_s_mosi_dlen_reg_t;
+
+/** Type of miso_dlen register
+ *  SPI1 receive data bit length control register.
+ */
+typedef union {
+    struct {
+        /** usr_miso_dbitlen : R/W; bitpos: [9:0]; default: 0;
+         *  The length in bits of  read-data. The register value shall be (bit_num-1).
+         */
+        uint32_t usr_miso_dbitlen:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} spi1_mem_s_miso_dlen_reg_t;
+
+/** Type of rd_status register
+ *  SPI1 status register.
+ */
+typedef union {
+    struct {
+        /** status : R/W/SS; bitpos: [15:0]; default: 0;
+         *  The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit.
+         */
+        uint32_t status:16;
+        /** wb_mode : R/W; bitpos: [23:16]; default: 0;
+         *  Mode bits in the flash fast read mode  it is combined with spi1_mem_s_fastrd_mode bit.
+         */
+        uint32_t wb_mode:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} spi1_mem_s_rd_status_reg_t;
+
+/** Type of misc register
+ *  SPI1 misc register
+ */
+typedef union {
+    struct {
+        /** cs0_dis : R/W; bitpos: [0]; default: 0;
+         *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
+         *  device, such as flash, external RAM and so on.
+         */
+        uint32_t cs0_dis:1;
+        /** cs1_dis : R/W; bitpos: [1]; default: 1;
+         *  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
+         *  device, such as flash, external RAM and so on.
+         */
+        uint32_t cs1_dis:1;
+        uint32_t reserved_2:7;
+        /** ck_idle_edge : R/W; bitpos: [9]; default: 0;
+         *  1: spi clk line is high when idle     0: spi clk line is low when idle
+         */
+        uint32_t ck_idle_edge:1;
+        /** cs_keep_active : R/W; bitpos: [10]; default: 0;
+         *  spi cs line keep low when the bit is set.
+         */
+        uint32_t cs_keep_active:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi1_mem_s_misc_reg_t;
+
+/** Type of cache_fctrl register
+ *  SPI1 bit mode control register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0;
+         *  For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
+         */
+        uint32_t cache_usr_addr_4byte:1;
+        uint32_t reserved_2:1;
+        /** fdin_dual : R/W; bitpos: [3]; default: 0;
+         *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
+         *  spi1_mem_s_fread_dio.
+         */
+        uint32_t fdin_dual:1;
+        /** fdout_dual : R/W; bitpos: [4]; default: 0;
+         *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
+         *  with spi1_mem_s_fread_dio.
+         */
+        uint32_t fdout_dual:1;
+        /** faddr_dual : R/W; bitpos: [5]; default: 0;
+         *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
+         *  with spi1_mem_s_fread_dio.
+         */
+        uint32_t faddr_dual:1;
+        /** fdin_quad : R/W; bitpos: [6]; default: 0;
+         *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+         *  with spi1_mem_s_fread_qio.
+         */
+        uint32_t fdin_quad:1;
+        /** fdout_quad : R/W; bitpos: [7]; default: 0;
+         *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+         *  with spi1_mem_s_fread_qio.
+         */
+        uint32_t fdout_quad:1;
+        /** faddr_quad : R/W; bitpos: [8]; default: 0;
+         *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
+         *  with spi1_mem_s_fread_qio.
+         */
+        uint32_t faddr_quad:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi1_mem_s_cache_fctrl_reg_t;
+
+/** Type of flash_waiti_ctrl register
+ *  SPI1 wait idle control register
+ */
+typedef union {
+    struct {
+        /** waiti_en : R/W; bitpos: [0]; default: 1;
+         *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
+         *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
+         *  Suspend/Resume are not supported.
+         */
+        uint32_t waiti_en:1;
+        /** waiti_dummy : R/W; bitpos: [1]; default: 0;
+         *  The dummy phase enable when wait flash idle (RDSR)
+         */
+        uint32_t waiti_dummy:1;
+        /** waiti_addr_en : R/W; bitpos: [2]; default: 0;
+         *  1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out
+         *  address in RDSR or read SUS command transfer.
+         */
+        uint32_t waiti_addr_en:1;
+        /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0;
+         *  When SPI1_MEM_S_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+         *  (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+         *  SPI1_MEM_S_WAITI_ADDR_EN is cleared.
+         */
+        uint32_t waiti_addr_cyclelen:2;
+        uint32_t reserved_5:4;
+        /** waiti_cmd_2b : R/W; bitpos: [9]; default: 0;
+         *  1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
+         */
+        uint32_t waiti_cmd_2b:1;
+        /** waiti_dummy_cyclelen : R/W; bitpos: [15:10]; default: 0;
+         *  The dummy cycle length when wait flash idle(RDSR).
+         */
+        uint32_t waiti_dummy_cyclelen:6;
+        /** waiti_cmd : R/W; bitpos: [31:16]; default: 5;
+         *  The command value to wait flash idle(RDSR).
+         */
+        uint32_t waiti_cmd:16;
+    };
+    uint32_t val;
+} spi1_mem_s_flash_waiti_ctrl_reg_t;
+
+/** Type of flash_sus_ctrl register
+ *  SPI1 flash suspend control register
+ */
+typedef union {
+    struct {
+        /** flash_per : R/W/SC; bitpos: [0]; default: 0;
+         *  program erase resume bit, program erase suspend operation will be triggered when
+         *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
+         *  disable.
+         */
+        uint32_t flash_per:1;
+        /** flash_pes : R/W/SC; bitpos: [1]; default: 0;
+         *  program erase suspend bit, program erase suspend operation will be triggered when
+         *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
+         *  disable.
+         */
+        uint32_t flash_pes:1;
+        /** flash_per_wait_en : R/W; bitpos: [2]; default: 0;
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  program erase resume command is sent. 0: SPI1 does not wait after program erase
+         *  resume command is sent.
+         */
+        uint32_t flash_per_wait_en:1;
+        /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0;
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
+         *  suspend command is sent.
+         */
+        uint32_t flash_pes_wait_en:1;
+        /** pes_per_en : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
+         *  application should send PER after PES is done.
+         */
+        uint32_t pes_per_en:1;
+        /** flash_pes_en : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable Auto-suspending function.
+         */
+        uint32_t flash_pes_en:1;
+        /** pesr_end_msk : R/W; bitpos: [21:6]; default: 128;
+         *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+         *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+         *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
+         *  status_in[15:0]^ SPI1_MEM_S_PESR_END_MSK[15:0].
+         */
+        uint32_t pesr_end_msk:16;
+        /** fmem_rd_sus_2b : R/W; bitpos: [22]; default: 0;
+         *  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when
+         *  check flash SUS/SUS1/SUS2 status bit
+         */
+        uint32_t fmem_rd_sus_2b:1;
+        /** per_end_en : R/W; bitpos: [23]; default: 0;
+         *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
+         *  flash. 0: Only need to check WIP is 0.
+         */
+        uint32_t per_end_en:1;
+        /** pes_end_en : R/W; bitpos: [24]; default: 0;
+         *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status
+         *  of flash. 0: Only need to check WIP is 0.
+         */
+        uint32_t pes_end_en:1;
+        /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4;
+         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it
+         *  will be treated as check pass.
+         */
+        uint32_t sus_timeout_cnt:7;
+    };
+    uint32_t val;
+} spi1_mem_s_flash_sus_ctrl_reg_t;
+
+/** Type of flash_sus_cmd register
+ *  SPI1 flash suspend command register
+ */
+typedef union {
+    struct {
+        /** flash_pes_command : R/W; bitpos: [15:0]; default: 30069;
+         *  Program/Erase suspend command.
+         */
+        uint32_t flash_pes_command:16;
+        /** wait_pesr_command : R/W; bitpos: [31:16]; default: 5;
+         *  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
+         *  SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
+         */
+        uint32_t wait_pesr_command:16;
+    };
+    uint32_t val;
+} spi1_mem_s_flash_sus_cmd_reg_t;
+
+/** Type of sus_status register
+ *  SPI1 flash suspend status register
+ */
+typedef union {
+    struct {
+        /** flash_sus : R/W/SS/SC; bitpos: [0]; default: 0;
+         *  The status of flash suspend, only used in SPI1.
+         */
+        uint32_t flash_sus:1;
+        /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0;
+         *  1: SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+         *  SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+         */
+        uint32_t wait_pesr_cmd_2b:1;
+        /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0;
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  after HPM command is sent.
+         */
+        uint32_t flash_hpm_dly_128:1;
+        /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0;
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  after RES command is sent.
+         */
+        uint32_t flash_res_dly_128:1;
+        /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0;
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  after DP command is sent.
+         */
+        uint32_t flash_dp_dly_128:1;
+        /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0;
+         *  Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+         *  sent.
+         */
+        uint32_t flash_per_dly_128:1;
+        /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0;
+         *  Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+         *  sent.
+         */
+        uint32_t flash_pes_dly_128:1;
+        /** spi0_lock_en : R/W; bitpos: [7]; default: 0;
+         *  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
+         */
+        uint32_t spi0_lock_en:1;
+        uint32_t reserved_8:7;
+        /** flash_pesr_cmd_2b : R/W; bitpos: [15]; default: 0;
+         *  1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length
+         *  of Program/Erase Suspend/Resume command is 8.
+         */
+        uint32_t flash_pesr_cmd_2b:1;
+        /** flash_per_command : R/W; bitpos: [31:16]; default: 31354;
+         *  Program/Erase resume command.
+         */
+        uint32_t flash_per_command:16;
+    };
+    uint32_t val;
+} spi1_mem_s_sus_status_reg_t;
+
+/** Type of ddr register
+ *  SPI1 DDR control register
+ */
+typedef union {
+    struct {
+        /** fmem_ddr_en : R/W; bitpos: [0]; default: 0;
+         *  1: in ddr mode,  0 in sdr mode
+         */
+        uint32_t fmem_ddr_en:1;
+        /** fmem_var_dummy : R/W; bitpos: [1]; default: 0;
+         *  Set the bit to enable variable dummy cycle in spi ddr mode.
+         */
+        uint32_t fmem_var_dummy:1;
+        /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0;
+         *  Set the bit to reorder rx data of the word in spi ddr mode.
+         */
+        uint32_t fmem_ddr_rdat_swp:1;
+        /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0;
+         *  Set the bit to reorder tx data of the word in spi ddr mode.
+         */
+        uint32_t fmem_ddr_wdat_swp:1;
+        /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0;
+         *  the bit is used to disable dual edge in command phase when ddr mode.
+         */
+        uint32_t fmem_ddr_cmd_dis:1;
+        /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1;
+         *  It is the minimum output data length in the panda device.
+         */
+        uint32_t fmem_outminbytelen:7;
+        uint32_t reserved_12:2;
+        /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0;
+         *  The delay number of data strobe which from memory based on SPI clock.
+         */
+        uint32_t fmem_usr_ddr_dqs_thd:7;
+        /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
+         *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+         *  spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
+         *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+         *  negative edge of SPI_DQS.
+         */
+        uint32_t fmem_ddr_dqs_loop:1;
+        uint32_t reserved_22:2;
+        /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0;
+         *  Set this bit to enable the differential SPI_CLK#.
+         */
+        uint32_t fmem_clk_diff_en:1;
+        uint32_t reserved_25:1;
+        /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+         */
+        uint32_t fmem_dqs_ca_in:1;
+        /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+         *  accesses flash or SPI1 accesses flash or sram.
+         */
+        uint32_t fmem_hyperbus_dummy_2x:1;
+        /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to invert SPI_DIFF when accesses to flash. .
+         */
+        uint32_t fmem_clk_diff_inv:1;
+        /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0;
+         *  Set this bit to enable octa_ram address out when accesses to flash, which means
+         *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
+         */
+        uint32_t fmem_octa_ram_addr:1;
+        /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to enable HyperRAM address out when accesses to flash, which means
+         *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+         */
+        uint32_t fmem_hyperbus_ca:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} spi1_mem_s_ddr_reg_t;
+
+/** Type of clock_gate register
+ *  SPI1 clk_gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Register clock gate enable signal. 1: Enable. 0: Disable.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi1_mem_s_clock_gate_reg_t;
+
+
+/** Group: Status register */
+/** Type of tx_crc register
+ *  SPI1 TX CRC data register.
+ */
+typedef union {
+    struct {
+        /** tx_crc_data : RO; bitpos: [31:0]; default: 4294967295;
+         *  For SPI1, the value of crc32.
+         */
+        uint32_t tx_crc_data:32;
+    };
+    uint32_t val;
+} spi1_mem_s_tx_crc_reg_t;
+
+
+/** Group: Memory data buffer register */
+/** Type of w0 register
+ *  SPI1 memory data buffer0
+ */
+typedef union {
+    struct {
+        /** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf0:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w0_reg_t;
+
+/** Type of w1 register
+ *  SPI1 memory data buffer1
+ */
+typedef union {
+    struct {
+        /** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf1:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w1_reg_t;
+
+/** Type of w2 register
+ *  SPI1 memory data buffer2
+ */
+typedef union {
+    struct {
+        /** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf2:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w2_reg_t;
+
+/** Type of w3 register
+ *  SPI1 memory data buffer3
+ */
+typedef union {
+    struct {
+        /** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf3:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w3_reg_t;
+
+/** Type of w4 register
+ *  SPI1 memory data buffer4
+ */
+typedef union {
+    struct {
+        /** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf4:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w4_reg_t;
+
+/** Type of w5 register
+ *  SPI1 memory data buffer5
+ */
+typedef union {
+    struct {
+        /** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf5:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w5_reg_t;
+
+/** Type of w6 register
+ *  SPI1 memory data buffer6
+ */
+typedef union {
+    struct {
+        /** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf6:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w6_reg_t;
+
+/** Type of w7 register
+ *  SPI1 memory data buffer7
+ */
+typedef union {
+    struct {
+        /** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf7:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w7_reg_t;
+
+/** Type of w8 register
+ *  SPI1 memory data buffer8
+ */
+typedef union {
+    struct {
+        /** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf8:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w8_reg_t;
+
+/** Type of w9 register
+ *  SPI1 memory data buffer9
+ */
+typedef union {
+    struct {
+        /** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf9:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w9_reg_t;
+
+/** Type of w10 register
+ *  SPI1 memory data buffer10
+ */
+typedef union {
+    struct {
+        /** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf10:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w10_reg_t;
+
+/** Type of w11 register
+ *  SPI1 memory data buffer11
+ */
+typedef union {
+    struct {
+        /** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf11:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w11_reg_t;
+
+/** Type of w12 register
+ *  SPI1 memory data buffer12
+ */
+typedef union {
+    struct {
+        /** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf12:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w12_reg_t;
+
+/** Type of w13 register
+ *  SPI1 memory data buffer13
+ */
+typedef union {
+    struct {
+        /** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf13:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w13_reg_t;
+
+/** Type of w14 register
+ *  SPI1 memory data buffer14
+ */
+typedef union {
+    struct {
+        /** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf14:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w14_reg_t;
+
+/** Type of w15 register
+ *  SPI1 memory data buffer15
+ */
+typedef union {
+    struct {
+        /** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf15:32;
+    };
+    uint32_t val;
+} spi1_mem_s_w15_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_ena register
+ *  SPI1 interrupt enable register
+ */
+typedef union {
+    struct {
+        /** per_end_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for SPI1_MEM_S_PER_END_INT interrupt.
+         */
+        uint32_t per_end_int_ena:1;
+        /** pes_end_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for SPI1_MEM_S_PES_END_INT interrupt.
+         */
+        uint32_t pes_end_int_ena:1;
+        /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for SPI1_MEM_S_WPE_END_INT interrupt.
+         */
+        uint32_t wpe_end_int_ena:1;
+        /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
+         */
+        uint32_t slv_st_end_int_ena:1;
+        /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
+         */
+        uint32_t mst_st_end_int_ena:1;
+        uint32_t reserved_5:5;
+        /** brown_out_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The enable bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
+         */
+        uint32_t brown_out_int_ena:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi1_mem_s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  SPI1 interrupt clear register
+ */
+typedef union {
+    struct {
+        /** per_end_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear bit for SPI1_MEM_S_PER_END_INT interrupt.
+         */
+        uint32_t per_end_int_clr:1;
+        /** pes_end_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear bit for SPI1_MEM_S_PES_END_INT interrupt.
+         */
+        uint32_t pes_end_int_clr:1;
+        /** wpe_end_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear bit for SPI1_MEM_S_WPE_END_INT interrupt.
+         */
+        uint32_t wpe_end_int_clr:1;
+        /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
+         */
+        uint32_t slv_st_end_int_clr:1;
+        /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
+         */
+        uint32_t mst_st_end_int_clr:1;
+        uint32_t reserved_5:5;
+        /** brown_out_int_clr : WT; bitpos: [10]; default: 0;
+         *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
+         */
+        uint32_t brown_out_int_clr:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi1_mem_s_int_clr_reg_t;
+
+/** Type of int_raw register
+ *  SPI1 interrupt raw register
+ */
+typedef union {
+    struct {
+        /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit for SPI1_MEM_S_PER_END_INT interrupt. 1: Triggered when Auto Resume
+         *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
+         */
+        uint32_t per_end_int_raw:1;
+        /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit for SPI1_MEM_S_PES_END_INT interrupt.1: Triggered when Auto Suspend
+         *  command (0x75) is sent and flash is suspended successfully. 0: Others.
+         */
+        uint32_t pes_end_int_raw:1;
+        /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+         *  is sent and flash is already idle. 0: Others.
+         */
+        uint32_t wpe_end_int_raw:1;
+        /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+         *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
+         *  Others
+         */
+        uint32_t slv_st_end_int_raw:1;
+        /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+         *  changed from non idle state to idle state. 0: Others.
+         */
+        uint32_t mst_st_end_int_raw:1;
+        uint32_t reserved_5:5;
+        /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+         *  chip is losing power and RTC module sends out brown out close flash request to
+         *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
+         *  and MSPI returns to idle state. 0: Others.
+         */
+        uint32_t brown_out_int_raw:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi1_mem_s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  SPI1 interrupt status register
+ */
+typedef union {
+    struct {
+        /** per_end_int_st : RO; bitpos: [0]; default: 0;
+         *  The status bit for SPI1_MEM_S_PER_END_INT interrupt.
+         */
+        uint32_t per_end_int_st:1;
+        /** pes_end_int_st : RO; bitpos: [1]; default: 0;
+         *  The status bit for SPI1_MEM_S_PES_END_INT interrupt.
+         */
+        uint32_t pes_end_int_st:1;
+        /** wpe_end_int_st : RO; bitpos: [2]; default: 0;
+         *  The status bit for SPI1_MEM_S_WPE_END_INT interrupt.
+         */
+        uint32_t wpe_end_int_st:1;
+        /** slv_st_end_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
+         */
+        uint32_t slv_st_end_int_st:1;
+        /** mst_st_end_int_st : RO; bitpos: [4]; default: 0;
+         *  The status bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
+         */
+        uint32_t mst_st_end_int_st:1;
+        uint32_t reserved_5:5;
+        /** brown_out_int_st : RO; bitpos: [10]; default: 0;
+         *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
+         */
+        uint32_t brown_out_int_st:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi1_mem_s_int_st_reg_t;
+
+
+/** Group: Timing registers */
+/** Type of timing_cali register
+ *  SPI1 timing control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** timing_cali : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable timing auto-calibration for all reading operations.
+         */
+        uint32_t timing_cali:1;
+        /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0;
+         *  add extra dummy spi clock cycle length for spi clock calibration.
+         */
+        uint32_t extra_dummy_cyclelen:3;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} spi1_mem_s_timing_cali_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 34673216;
+         *  Version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi1_mem_s_date_reg_t;
+
+
+typedef struct spi1_mem_s_dev_s {
+    volatile spi1_mem_s_cmd_reg_t cmd;
+    volatile spi1_mem_s_addr_reg_t addr;
+    volatile spi1_mem_s_ctrl_reg_t ctrl;
+    volatile spi1_mem_s_ctrl1_reg_t ctrl1;
+    volatile spi1_mem_s_ctrl2_reg_t ctrl2;
+    volatile spi1_mem_s_clock_reg_t clock;
+    volatile spi1_mem_s_user_reg_t user;
+    volatile spi1_mem_s_user1_reg_t user1;
+    volatile spi1_mem_s_user2_reg_t user2;
+    volatile spi1_mem_s_mosi_dlen_reg_t mosi_dlen;
+    volatile spi1_mem_s_miso_dlen_reg_t miso_dlen;
+    volatile spi1_mem_s_rd_status_reg_t rd_status;
+    uint32_t reserved_030;
+    volatile spi1_mem_s_misc_reg_t misc;
+    volatile spi1_mem_s_tx_crc_reg_t tx_crc;
+    volatile spi1_mem_s_cache_fctrl_reg_t cache_fctrl;
+    uint32_t reserved_040[6];
+    volatile spi1_mem_s_w0_reg_t w0;
+    volatile spi1_mem_s_w1_reg_t w1;
+    volatile spi1_mem_s_w2_reg_t w2;
+    volatile spi1_mem_s_w3_reg_t w3;
+    volatile spi1_mem_s_w4_reg_t w4;
+    volatile spi1_mem_s_w5_reg_t w5;
+    volatile spi1_mem_s_w6_reg_t w6;
+    volatile spi1_mem_s_w7_reg_t w7;
+    volatile spi1_mem_s_w8_reg_t w8;
+    volatile spi1_mem_s_w9_reg_t w9;
+    volatile spi1_mem_s_w10_reg_t w10;
+    volatile spi1_mem_s_w11_reg_t w11;
+    volatile spi1_mem_s_w12_reg_t w12;
+    volatile spi1_mem_s_w13_reg_t w13;
+    volatile spi1_mem_s_w14_reg_t w14;
+    volatile spi1_mem_s_w15_reg_t w15;
+    volatile spi1_mem_s_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
+    volatile spi1_mem_s_flash_sus_ctrl_reg_t flash_sus_ctrl;
+    volatile spi1_mem_s_flash_sus_cmd_reg_t flash_sus_cmd;
+    volatile spi1_mem_s_sus_status_reg_t sus_status;
+    uint32_t reserved_0a8[6];
+    volatile spi1_mem_s_int_ena_reg_t int_ena;
+    volatile spi1_mem_s_int_clr_reg_t int_clr;
+    volatile spi1_mem_s_int_raw_reg_t int_raw;
+    volatile spi1_mem_s_int_st_reg_t int_st;
+    uint32_t reserved_0d0;
+    volatile spi1_mem_s_ddr_reg_t ddr;
+    uint32_t reserved_0d8[42];
+    volatile spi1_mem_s_timing_cali_reg_t timing_cali;
+    uint32_t reserved_184[31];
+    volatile spi1_mem_s_clock_gate_reg_t clock_gate;
+    uint32_t reserved_204[126];
+    volatile spi1_mem_s_date_reg_t date;
+} spi1_mem_s_dev_t;
+
+extern spi1_mem_s_dev_t SPIMEM3;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi1_mem_s_dev_t) == 0x400, "Invalid size of spi1_mem_s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_eco5_struct.h
new file mode 100644
index 0000000000..1263f22ba5
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_eco5_struct.h
@@ -0,0 +1,1623 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: User-defined control registers */
+/** Type of cmd register
+ *  Command control register
+ */
+typedef union {
+    struct {
+        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+         */
+        uint32_t conf_bitlen:18;
+        uint32_t reserved_18:5;
+        /** update : WT; bitpos: [23]; default: 0;
+         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+         *  clock domain, which is only used in SPI master mode.
+         */
+        uint32_t update:1;
+        /** usr : R/W/SC; bitpos: [24]; default: 0;
+         *  User define command enable.  An operation will be triggered when the bit is set.
+         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+         *  changed by CONF_buf.
+         */
+        uint32_t usr:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} spi_cmd_reg_t;
+
+/** Type of addr register
+ *  Address value register
+ */
+typedef union {
+    struct {
+        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
+         *  Address to slave. Can be configured in CONF state.
+         */
+        uint32_t usr_addr_value:32;
+    };
+    uint32_t val;
+} spi_addr_reg_t;
+
+/** Type of user register
+ *  SPI USER control register
+ */
+typedef union {
+    struct {
+        /** doutdin : R/W; bitpos: [0]; default: 0;
+         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t doutdin:1;
+        uint32_t reserved_1:2;
+        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
+         *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t qpi_mode:1;
+        /** opi_mode : R/W; bitpos: [4]; default: 0;
+         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t opi_mode:1;
+        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+         *  spi_ck_i. 1:tsck = !spi_ck_i.
+         */
+        uint32_t tsck_i_edge:1;
+        /** cs_hold : R/W; bitpos: [6]; default: 1;
+         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cs_hold:1;
+        /** cs_setup : R/W; bitpos: [7]; default: 1;
+         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cs_setup:1;
+        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+         *  !spi_ck_i. 1:rsck = spi_ck_i.
+         */
+        uint32_t rsck_i_edge:1;
+        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+         *  be configured in CONF state.
+         */
+        uint32_t ck_out_edge:1;
+        uint32_t reserved_10:2;
+        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
+         *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_dual:1;
+        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
+         *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_quad:1;
+        /** fwrite_oct : R/W; bitpos: [14]; default: 0;
+         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_oct:1;
+        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
+         *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+         *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
+         *  not seg-trans mode. Can be configured in CONF state.
+         */
+        uint32_t usr_conf_nxt:1;
+        uint32_t reserved_16:1;
+        /** sio : R/W; bitpos: [17]; default: 0;
+         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+         */
+        uint32_t sio:1;
+        uint32_t reserved_18:6;
+        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
+         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+         *  disable. Can be configured in CONF state.
+         */
+        uint32_t usr_miso_highpart:1;
+        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
+         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+         *  0: disable.  Can be configured in CONF state.
+         */
+        uint32_t usr_mosi_highpart:1;
+        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+         *  CONF state.
+         */
+        uint32_t usr_dummy_idle:1;
+        /** usr_mosi : R/W; bitpos: [27]; default: 0;
+         *  This bit enable the write-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t usr_mosi:1;
+        /** usr_miso : R/W; bitpos: [28]; default: 0;
+         *  This bit enable the read-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t usr_miso:1;
+        /** usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_dummy:1;
+        /** usr_addr : R/W; bitpos: [30]; default: 0;
+         *  This bit enable the address phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_addr:1;
+        /** usr_command : R/W; bitpos: [31]; default: 1;
+         *  This bit enable the command phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_command:1;
+    };
+    uint32_t val;
+} spi_user_reg_t;
+
+/** Type of user1 register
+ *  SPI USER control register 1
+ */
+typedef union {
+    struct {
+        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
+         *  The length in spi_clk cycles of dummy phase. The register value shall be
+         *  (cycle_num-1). Can be configured in CONF state.
+         */
+        uint32_t usr_dummy_cyclelen:8;
+        uint32_t reserved_8:8;
+        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
+         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+         *  GP-SPI master FD/HD-mode.
+         */
+        uint32_t mst_wfull_err_end_en:1;
+        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
+         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+         *  bit. Can be configured in CONF state.
+         */
+        uint32_t cs_setup_time:5;
+        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
+         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs_hold_time:5;
+        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
+         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t usr_addr_bitlen:5;
+    };
+    uint32_t val;
+} spi_user1_reg_t;
+
+/** Type of user2 register
+ *  SPI USER control register 2
+ */
+typedef union {
+    struct {
+        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  The value of  command. Can be configured in CONF state.
+         */
+        uint32_t usr_command_value:16;
+        uint32_t reserved_16:11;
+        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
+         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+         *  is valid in GP-SPI master FD/HD-mode.
+         */
+        uint32_t mst_rempty_err_end_en:1;
+        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t usr_command_bitlen:4;
+    };
+    uint32_t val;
+} spi_user2_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of ctrl register
+ *  SPI control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** dummy_out : R/W; bitpos: [3]; default: 0;
+         *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
+         *  the FSPI bus signals are output. Can be configured in CONF state.
+         */
+        uint32_t dummy_out:1;
+        uint32_t reserved_4:1;
+        /** faddr_dual : R/W; bitpos: [5]; default: 0;
+         *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_dual:1;
+        /** faddr_quad : R/W; bitpos: [6]; default: 0;
+         *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_quad:1;
+        /** faddr_oct : R/W; bitpos: [7]; default: 0;
+         *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_oct:1;
+        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
+         *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_dual:1;
+        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
+         *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_quad:1;
+        /** fcmd_oct : R/W; bitpos: [10]; default: 0;
+         *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_oct:1;
+        uint32_t reserved_11:3;
+        /** fread_dual : R/W; bitpos: [14]; default: 0;
+         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_dual:1;
+        /** fread_quad : R/W; bitpos: [15]; default: 0;
+         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_quad:1;
+        /** fread_oct : R/W; bitpos: [16]; default: 0;
+         *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_oct:1;
+        uint32_t reserved_17:1;
+        /** q_pol : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t q_pol:1;
+        /** d_pol : R/W; bitpos: [19]; default: 1;
+         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t d_pol:1;
+        /** hold_pol : R/W; bitpos: [20]; default: 1;
+         *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+         *  configured in CONF state.
+         */
+        uint32_t hold_pol:1;
+        /** wp_pol : R/W; bitpos: [21]; default: 1;
+         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t wp_pol:1;
+        uint32_t reserved_22:1;
+        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
+         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+         *  state.
+         */
+        uint32_t rd_bit_order:2;
+        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
+         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+         *  configured in CONF state.
+         */
+        uint32_t wr_bit_order:2;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_ctrl_reg_t;
+
+/** Type of ms_dlen register
+ *  SPI data bit length control register
+ */
+typedef union {
+    struct {
+        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  The value of these bits is the configured SPI transmission data bit length in
+         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+         *  the configured bit length in slave mode DMA RX controlled transfer. The register
+         *  value shall be (bit_num-1). Can be configured in CONF state.
+         */
+        uint32_t ms_data_bitlen:18;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_ms_dlen_reg_t;
+
+/** Type of misc register
+ *  SPI misc register
+ */
+typedef union {
+    struct {
+        /** cs0_dis : R/W; bitpos: [0]; default: 0;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs0_dis:1;
+        /** cs1_dis : R/W; bitpos: [1]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs1_dis:1;
+        /** cs2_dis : R/W; bitpos: [2]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs2_dis:1;
+        /** cs3_dis : R/W; bitpos: [3]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs3_dis:1;
+        /** cs4_dis : R/W; bitpos: [4]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs4_dis:1;
+        /** cs5_dis : R/W; bitpos: [5]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs5_dis:1;
+        /** ck_dis : R/W; bitpos: [6]; default: 0;
+         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+         */
+        uint32_t ck_dis:1;
+        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
+         *  In the master mode the bits are the polarity of spi cs line, the value is
+         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+         */
+        uint32_t master_cs_pol:6;
+        uint32_t reserved_13:3;
+        /** clk_data_dtr_en : R/W; bitpos: [16]; default: 0;
+         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+         */
+        uint32_t clk_data_dtr_en:1;
+        /** data_dtr_en : R/W; bitpos: [17]; default: 0;
+         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+         *  Can be configured in CONF state.
+         */
+        uint32_t data_dtr_en:1;
+        /** addr_dtr_en : R/W; bitpos: [18]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t addr_dtr_en:1;
+        /** cmd_dtr_en : R/W; bitpos: [19]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cmd_dtr_en:1;
+        uint32_t reserved_20:3;
+        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
+         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+         *  CONF state.
+         */
+        uint32_t slave_cs_pol:1;
+        /** dqs_idle_edge : R/W; bitpos: [24]; default: 0;
+         *  The default value of spi_dqs. Can be configured in CONF state.
+         */
+        uint32_t dqs_idle_edge:1;
+        uint32_t reserved_25:4;
+        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
+         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+         *  configured in CONF state.
+         */
+        uint32_t ck_idle_edge:1;
+        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
+         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+         */
+        uint32_t cs_keep_active:1;
+        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
+         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+         *  spi quad input swap disable. Can be configured in CONF state.
+         */
+        uint32_t quad_din_pin_swap:1;
+    };
+    uint32_t val;
+} spi_misc_reg_t;
+
+/** Type of dma_conf register
+ *  SPI DMA control register
+ */
+typedef union {
+    struct {
+        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
+         *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
+         *  DMA TX FIFO is ready for sending data.
+         */
+        uint32_t dma_outfifo_empty:1;
+        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
+         *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
+         *  0: DMA RX FIFO is ready for receiving data.
+         */
+        uint32_t dma_infifo_full:1;
+        uint32_t reserved_2:16;
+        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
+         *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+         */
+        uint32_t dma_slv_seg_trans_en:1;
+        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
+         *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+         *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
+         */
+        uint32_t slv_rx_seg_trans_clr_en:1;
+        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
+         *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+         *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+         */
+        uint32_t slv_tx_seg_trans_clr_en:1;
+        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
+         *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
+         *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
+         *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+         *  spi_dma_seg_trans_done in seg-trans.
+         */
+        uint32_t rx_eof_en:1;
+        uint32_t reserved_22:5;
+        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to enable SPI DMA controlled receive data mode.
+         */
+        uint32_t dma_rx_ena:1;
+        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to enable SPI DMA controlled send data mode.
+         */
+        uint32_t dma_tx_ena:1;
+        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
+         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+         *  slave mode transfer.
+         */
+        uint32_t rx_afifo_rst:1;
+        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
+         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+         *  controlled mode transfer and master mode transfer.
+         */
+        uint32_t buf_afifo_rst:1;
+        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
+         *  controlled mode transfer.
+         */
+        uint32_t dma_afifo_rst:1;
+    };
+    uint32_t val;
+} spi_dma_conf_reg_t;
+
+/** Type of slave register
+ *  SPI slave control register
+ */
+typedef union {
+    struct {
+        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on. Can be configured in CONF state.
+         */
+        uint32_t clk_mode:2;
+        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
+         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+         */
+        uint32_t clk_mode_13:1;
+        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
+         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+         *  0: output data at tsck posedge
+         */
+        uint32_t rsck_data_out:1;
+        uint32_t reserved_4:4;
+        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  DMA controlled mode(Rd_DMA). 0: others
+         */
+        uint32_t slv_rddma_bitlen_en:1;
+        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in DMA controlled mode(Wr_DMA). 0: others
+         */
+        uint32_t slv_wrdma_bitlen_en:1;
+        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  CPU controlled mode(Rd_BUF). 0: others
+         */
+        uint32_t slv_rdbuf_bitlen_en:1;
+        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in CPU controlled mode(Wr_BUF). 0: others
+         */
+        uint32_t slv_wrbuf_bitlen_en:1;
+        /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0;
+         *  Represents the effective bit of the last received data byte in SPI slave FD and HD
+         *  mode.
+         */
+        uint32_t slv_last_byte_strb:8;
+        uint32_t reserved_20:2;
+        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
+         *  The magic value of BM table in master DMA seg-trans.
+         */
+        uint32_t dma_seg_magic_value:4;
+        /** slave_mode : R/W; bitpos: [26]; default: 0;
+         *  Set SPI work mode. 1: slave mode 0: master mode.
+         */
+        uint32_t slave_mode:1;
+        /** soft_reset : WT; bitpos: [27]; default: 0;
+         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+         *  configured in CONF state.
+         */
+        uint32_t soft_reset:1;
+        /** usr_conf : R/W; bitpos: [28]; default: 0;
+         *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
+         *  will start. 0: This is not seg-trans mode.
+         */
+        uint32_t usr_conf:1;
+        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
+         *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
+         *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
+         *  transfer.
+         */
+        uint32_t mst_fd_wait_dma_tx_data:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_slave_reg_t;
+
+/** Type of slave1 register
+ *  SPI slave control register 1
+ */
+typedef union {
+    struct {
+        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
+         *  The transferred data bit length in SPI slave FD and HD mode.
+         */
+        uint32_t slv_data_bitlen:18;
+        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
+         *  In the slave mode it is the value of command.
+         */
+        uint32_t slv_last_command:8;
+        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
+         *  In the slave mode it is the value of address.
+         */
+        uint32_t slv_last_addr:6;
+    };
+    uint32_t val;
+} spi_slave1_reg_t;
+
+
+/** Group: Clock control registers */
+/** Type of clock register
+ *  SPI clock control register
+ */
+typedef union {
+    struct {
+        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
+         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+         *  0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_l:6;
+        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
+         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+         *  must be 0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_h:6;
+        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
+         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+         */
+        uint32_t clkcnt_n:6;
+        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
+         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+         */
+        uint32_t clkdiv_pre:4;
+        uint32_t reserved_22:8;
+        /** clk_edge_sel : R/W; bitpos: [30]; default: 0;
+         *  Configures use standard clock sampling edge or delay the sampling edge by half a
+         *  cycle in master transfer.
+         *  0: clock sampling edge is delayed by half a cycle.
+         *  1: clock sampling edge is standard.
+         *  Can be configured in CONF state.
+         */
+        uint32_t clk_edge_sel:1;
+        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
+         *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+         *  clock. Can be configured in CONF state.
+         */
+        uint32_t clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi_clock_reg_t;
+
+/** Type of clk_gate register
+ *  SPI module clock and register clock control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en:1;
+        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to power on the SPI module clock.
+         */
+        uint32_t mst_clk_active:1;
+        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
+         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+         *  0: XTAL CLK.
+         */
+        uint32_t mst_clk_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} spi_clk_gate_reg_t;
+
+
+/** Group: Timing registers */
+/** Type of din_mode register
+ *  SPI input delay mode configuration
+ */
+typedef union {
+    struct {
+        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din0_mode:2;
+        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din1_mode:2;
+        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din2_mode:2;
+        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din3_mode:2;
+        /** din4_mode : R/W; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din4_mode:2;
+        /** din5_mode : R/W; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din5_mode:2;
+        /** din6_mode : R/W; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din6_mode:2;
+        /** din7_mode : R/W; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din7_mode:2;
+        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
+         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+         *  state.
+         */
+        uint32_t timing_hclk_active:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} spi_din_mode_reg_t;
+
+/** Type of din_num register
+ *  SPI input delay number configuration
+ */
+typedef union {
+    struct {
+        /** din0_num : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din0_num:2;
+        /** din1_num : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din1_num:2;
+        /** din2_num : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din2_num:2;
+        /** din3_num : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din3_num:2;
+        /** din4_num : R/W; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din4_num:2;
+        /** din5_num : R/W; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din5_num:2;
+        /** din6_num : R/W; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din6_num:2;
+        /** din7_num : R/W; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din7_num:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} spi_din_num_reg_t;
+
+/** Type of dout_mode register
+ *  SPI output delay mode configuration
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [0]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout0_mode:1;
+        /** dout1_mode : R/W; bitpos: [1]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout1_mode:1;
+        /** dout2_mode : R/W; bitpos: [2]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout2_mode:1;
+        /** dout3_mode : R/W; bitpos: [3]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout3_mode:1;
+        /** dout4_mode : R/W; bitpos: [4]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout4_mode:1;
+        /** dout5_mode : R/W; bitpos: [5]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout5_mode:1;
+        /** dout6_mode : R/W; bitpos: [6]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout6_mode:1;
+        /** dout7_mode : R/W; bitpos: [7]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout7_mode:1;
+        /** d_dqs_mode : R/W; bitpos: [8]; default: 0;
+         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t d_dqs_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_dout_mode_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of dma_int_ena register
+ *  SPI interrupt enable register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err_int_ena:1;
+        /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err_int_ena:1;
+        /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi_int_ena:1;
+        /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi_int_ena:1;
+        /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7_int_ena:1;
+        /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The enable bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8_int_ena:1;
+        /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The enable bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9_int_ena:1;
+        /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The enable bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda_int_ena:1;
+        /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done_int_ena:1;
+        /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done_int_ena:1;
+        /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done_int_ena:1;
+        /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done_int_ena:1;
+        /** trans_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The enable bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done_int_ena:1;
+        /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done_int_ena:1;
+        /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err_int_ena:1;
+        /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err_int_ena:1;
+        /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err_int_ena:1;
+        /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_ena:1;
+        /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0;
+         *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_ena:1;
+        /** app2_int_ena : R/W; bitpos: [19]; default: 0;
+         *  The enable bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2_int_ena:1;
+        /** app1_int_ena : R/W; bitpos: [20]; default: 0;
+         *  The enable bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1_int_ena:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_ena_reg_t;
+
+/** Type of dma_int_clr register
+ *  SPI interrupt clear register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err_int_clr:1;
+        /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err_int_clr:1;
+        /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi_int_clr:1;
+        /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi_int_clr:1;
+        /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7_int_clr:1;
+        /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0;
+         *  The clear bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8_int_clr:1;
+        /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0;
+         *  The clear bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9_int_clr:1;
+        /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0;
+         *  The clear bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda_int_clr:1;
+        /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0;
+         *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done_int_clr:1;
+        /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0;
+         *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done_int_clr:1;
+        /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0;
+         *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done_int_clr:1;
+        /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0;
+         *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done_int_clr:1;
+        /** trans_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  The clear bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done_int_clr:1;
+        /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done_int_clr:1;
+        /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0;
+         *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err_int_clr:1;
+        /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err_int_clr:1;
+        /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err_int_clr:1;
+        /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0;
+         *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_clr:1;
+        /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0;
+         *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_clr:1;
+        /** app2_int_clr : WT; bitpos: [19]; default: 0;
+         *  The clear bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2_int_clr:1;
+        /** app1_int_clr : WT; bitpos: [20]; default: 0;
+         *  The clear bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1_int_clr:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_clr_reg_t;
+
+/** Type of dma_int_raw register
+ *  SPI interrupt raw register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
+         *  receive data.  0: Others.
+         */
+        uint32_t dma_infifo_full_err_int_raw:1;
+        /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+         *  master mode and send out all 0 in slave mode.  0: Others.
+         */
+        uint32_t dma_outfifo_empty_err_int_raw:1;
+        /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
+         *  is ended. 0: Others.
+         */
+        uint32_t slv_ex_qpi_int_raw:1;
+        /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
+         *  is ended. 0: Others.
+         */
+        uint32_t slv_en_qpi_int_raw:1;
+        /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd7_int_raw:1;
+        /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd8_int_raw:1;
+        /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd9_int_raw:1;
+        /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmda_int_raw:1;
+        /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_rd_dma_done_int_raw:1;
+        /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_wr_dma_done_int_raw:1;
+        /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_rd_buf_done_int_raw:1;
+        /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_wr_buf_done_int_raw:1;
+        /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+         *  ended. 0: others.
+         */
+        uint32_t trans_done_int_raw:1;
+        /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
+         *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+         *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
+         *  is not ended or not occurred.
+         */
+        uint32_t dma_seg_trans_done_int_raw:1;
+        /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
+         *  is error in the DMA seg-conf-trans. 0: others.
+         */
+        uint32_t seg_magic_err_int_raw:1;
+        /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+         *  bigger than 63. 0: Others.
+         */
+        uint32_t slv_buf_addr_err_int_raw:1;
+        /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+         *  current SPI slave HD mode transmission is not supported. 0: Others.
+         */
+        uint32_t slv_cmd_err_int_raw:1;
+        /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+         *  write-full error when SPI inputs data in master mode. 0: Others.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_raw:1;
+        /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_raw:1;
+        /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
+         */
+        uint32_t app2_int_raw:1;
+        /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
+         */
+        uint32_t app1_int_raw:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_raw_reg_t;
+
+/** Type of dma_int_st register
+ *  SPI interrupt status register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0;
+         *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err_int_st:1;
+        /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0;
+         *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err_int_st:1;
+        /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0;
+         *  The status bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi_int_st:1;
+        /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi_int_st:1;
+        /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0;
+         *  The status bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7_int_st:1;
+        /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0;
+         *  The status bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8_int_st:1;
+        /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0;
+         *  The status bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9_int_st:1;
+        /** slv_cmda_int_st : RO; bitpos: [7]; default: 0;
+         *  The status bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda_int_st:1;
+        /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0;
+         *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done_int_st:1;
+        /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0;
+         *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done_int_st:1;
+        /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0;
+         *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done_int_st:1;
+        /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0;
+         *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done_int_st:1;
+        /** trans_done_int_st : RO; bitpos: [12]; default: 0;
+         *  The status bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done_int_st:1;
+        /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0;
+         *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done_int_st:1;
+        /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0;
+         *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err_int_st:1;
+        /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0;
+         *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err_int_st:1;
+        /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0;
+         *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err_int_st:1;
+        /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0;
+         *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_st:1;
+        /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0;
+         *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_st:1;
+        /** app2_int_st : RO; bitpos: [19]; default: 0;
+         *  The status bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2_int_st:1;
+        /** app1_int_st : RO; bitpos: [20]; default: 0;
+         *  The status bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1_int_st:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_st_reg_t;
+
+/** Type of dma_int_set register
+ *  SPI interrupt software set register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0;
+         *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err_int_set:1;
+        /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0;
+         *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err_int_set:1;
+        /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0;
+         *  The software set bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi_int_set:1;
+        /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0;
+         *  The software set bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi_int_set:1;
+        /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0;
+         *  The software set bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7_int_set:1;
+        /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0;
+         *  The software set bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8_int_set:1;
+        /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0;
+         *  The software set bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9_int_set:1;
+        /** slv_cmda_int_set : WT; bitpos: [7]; default: 0;
+         *  The software set bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda_int_set:1;
+        /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0;
+         *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done_int_set:1;
+        /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0;
+         *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done_int_set:1;
+        /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0;
+         *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done_int_set:1;
+        /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0;
+         *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done_int_set:1;
+        /** trans_done_int_set : WT; bitpos: [12]; default: 0;
+         *  The software set bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done_int_set:1;
+        /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0;
+         *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done_int_set:1;
+        /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0;
+         *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err_int_set:1;
+        /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
+         *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err_int_set:1;
+        /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0;
+         *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err_int_set:1;
+        /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0;
+         *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_set:1;
+        /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0;
+         *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_set:1;
+        /** app2_int_set : WT; bitpos: [19]; default: 0;
+         *  The software set bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2_int_set:1;
+        /** app1_int_set : WT; bitpos: [20]; default: 0;
+         *  The software set bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1_int_set:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_set_reg_t;
+
+
+/** Group: CPU-controlled data buffer */
+/** Type of w0 register
+ *  SPI CPU-controlled buffer0
+ */
+typedef union {
+    struct {
+        /** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf0:32;
+    };
+    uint32_t val;
+} spi_w0_reg_t;
+
+/** Type of w1 register
+ *  SPI CPU-controlled buffer1
+ */
+typedef union {
+    struct {
+        /** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf1:32;
+    };
+    uint32_t val;
+} spi_w1_reg_t;
+
+/** Type of w2 register
+ *  SPI CPU-controlled buffer2
+ */
+typedef union {
+    struct {
+        /** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf2:32;
+    };
+    uint32_t val;
+} spi_w2_reg_t;
+
+/** Type of w3 register
+ *  SPI CPU-controlled buffer3
+ */
+typedef union {
+    struct {
+        /** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf3:32;
+    };
+    uint32_t val;
+} spi_w3_reg_t;
+
+/** Type of w4 register
+ *  SPI CPU-controlled buffer4
+ */
+typedef union {
+    struct {
+        /** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf4:32;
+    };
+    uint32_t val;
+} spi_w4_reg_t;
+
+/** Type of w5 register
+ *  SPI CPU-controlled buffer5
+ */
+typedef union {
+    struct {
+        /** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf5:32;
+    };
+    uint32_t val;
+} spi_w5_reg_t;
+
+/** Type of w6 register
+ *  SPI CPU-controlled buffer6
+ */
+typedef union {
+    struct {
+        /** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf6:32;
+    };
+    uint32_t val;
+} spi_w6_reg_t;
+
+/** Type of w7 register
+ *  SPI CPU-controlled buffer7
+ */
+typedef union {
+    struct {
+        /** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf7:32;
+    };
+    uint32_t val;
+} spi_w7_reg_t;
+
+/** Type of w8 register
+ *  SPI CPU-controlled buffer8
+ */
+typedef union {
+    struct {
+        /** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf8:32;
+    };
+    uint32_t val;
+} spi_w8_reg_t;
+
+/** Type of w9 register
+ *  SPI CPU-controlled buffer9
+ */
+typedef union {
+    struct {
+        /** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf9:32;
+    };
+    uint32_t val;
+} spi_w9_reg_t;
+
+/** Type of w10 register
+ *  SPI CPU-controlled buffer10
+ */
+typedef union {
+    struct {
+        /** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf10:32;
+    };
+    uint32_t val;
+} spi_w10_reg_t;
+
+/** Type of w11 register
+ *  SPI CPU-controlled buffer11
+ */
+typedef union {
+    struct {
+        /** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf11:32;
+    };
+    uint32_t val;
+} spi_w11_reg_t;
+
+/** Type of w12 register
+ *  SPI CPU-controlled buffer12
+ */
+typedef union {
+    struct {
+        /** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf12:32;
+    };
+    uint32_t val;
+} spi_w12_reg_t;
+
+/** Type of w13 register
+ *  SPI CPU-controlled buffer13
+ */
+typedef union {
+    struct {
+        /** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf13:32;
+    };
+    uint32_t val;
+} spi_w13_reg_t;
+
+/** Type of w14 register
+ *  SPI CPU-controlled buffer14
+ */
+typedef union {
+    struct {
+        /** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf14:32;
+    };
+    uint32_t val;
+} spi_w14_reg_t;
+
+/** Type of w15 register
+ *  SPI CPU-controlled buffer15
+ */
+typedef union {
+    struct {
+        /** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf15:32;
+    };
+    uint32_t val;
+} spi_w15_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37761424;
+         *  SPI register version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi_date_reg_t;
+
+
+typedef struct {
+    volatile spi_cmd_reg_t cmd;
+    volatile spi_addr_reg_t addr;
+    volatile spi_ctrl_reg_t ctrl;
+    volatile spi_clock_reg_t clock;
+    volatile spi_user_reg_t user;
+    volatile spi_user1_reg_t user1;
+    volatile spi_user2_reg_t user2;
+    volatile spi_ms_dlen_reg_t ms_dlen;
+    volatile spi_misc_reg_t misc;
+    volatile spi_din_mode_reg_t din_mode;
+    volatile spi_din_num_reg_t din_num;
+    volatile spi_dout_mode_reg_t dout_mode;
+    volatile spi_dma_conf_reg_t dma_conf;
+    volatile spi_dma_int_ena_reg_t dma_int_ena;
+    volatile spi_dma_int_clr_reg_t dma_int_clr;
+    volatile spi_dma_int_raw_reg_t dma_int_raw;
+    volatile spi_dma_int_st_reg_t dma_int_st;
+    volatile spi_dma_int_set_reg_t dma_int_set;
+    uint32_t reserved_048[20];
+    volatile spi_w0_reg_t w0;
+    volatile spi_w1_reg_t w1;
+    volatile spi_w2_reg_t w2;
+    volatile spi_w3_reg_t w3;
+    volatile spi_w4_reg_t w4;
+    volatile spi_w5_reg_t w5;
+    volatile spi_w6_reg_t w6;
+    volatile spi_w7_reg_t w7;
+    volatile spi_w8_reg_t w8;
+    volatile spi_w9_reg_t w9;
+    volatile spi_w10_reg_t w10;
+    volatile spi_w11_reg_t w11;
+    volatile spi_w12_reg_t w12;
+    volatile spi_w13_reg_t w13;
+    volatile spi_w14_reg_t w14;
+    volatile spi_w15_reg_t w15;
+    uint32_t reserved_0d8[2];
+    volatile spi_slave_reg_t slave;
+    volatile spi_slave1_reg_t slave1;
+    volatile spi_clk_gate_reg_t clk_gate;
+    uint32_t reserved_0ec;
+    volatile spi_date_reg_t date;
+} spi_dev_t;
+
+extern spi_dev_t GPSPI2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h
new file mode 100644
index 0000000000..d105863da3
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h
@@ -0,0 +1,2737 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI_MEM_C_CMD_REG register
+ *  SPI0 FSM status register
+ */
+#define SPI_MEM_C_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x0)
+/** SPI_MEM_C_MST_ST : RO; bitpos: [3:0]; default: 0;
+ *  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT ,
+ *  2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent
+ *  data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
+ */
+#define SPI_MEM_C_MST_ST    0x0000000FU
+#define SPI_MEM_C_MST_ST_M  (SPI_MEM_C_MST_ST_V << SPI_MEM_C_MST_ST_S)
+#define SPI_MEM_C_MST_ST_V  0x0000000FU
+#define SPI_MEM_C_MST_ST_S  0
+/** SPI_MEM_C_SLV_ST : RO; bitpos: [7:4]; default: 0;
+ *  The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state,
+ *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
+ *  6:write data state, 7: done state, 8: read data end state.
+ */
+#define SPI_MEM_C_SLV_ST    0x0000000FU
+#define SPI_MEM_C_SLV_ST_M  (SPI_MEM_C_SLV_ST_V << SPI_MEM_C_SLV_ST_S)
+#define SPI_MEM_C_SLV_ST_V  0x0000000FU
+#define SPI_MEM_C_SLV_ST_S  4
+/** SPI_MEM_C_USR : HRO; bitpos: [18]; default: 0;
+ *  SPI0 USR_CMD start bit, only used when SPI_MEM_C_AXI_REQ_EN is cleared.  An operation
+ *  will be triggered when the bit is set. The bit will be cleared once the operation
+ *  done.1: enable 0: disable.
+ */
+#define SPI_MEM_C_USR    (BIT(18))
+#define SPI_MEM_C_USR_M  (SPI_MEM_C_USR_V << SPI_MEM_C_USR_S)
+#define SPI_MEM_C_USR_V  0x00000001U
+#define SPI_MEM_C_USR_S  18
+
+/** SPI_MEM_C_CTRL_REG register
+ *  SPI0 control register.
+ */
+#define SPI_MEM_C_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x8)
+/** SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0;
+ *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
+ *  of SPI_DQS is output by the MSPI controller.
+ */
+#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
+#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_S)
+#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_S  0
+/** SPI_MEM_C_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0;
+ *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
+ *  of SPI_IO[7:0] is output by the MSPI controller.
+ */
+#define SPI_MEM_C_WDUMMY_ALWAYS_OUT    (BIT(1))
+#define SPI_MEM_C_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_C_WDUMMY_ALWAYS_OUT_V << SPI_MEM_C_WDUMMY_ALWAYS_OUT_S)
+#define SPI_MEM_C_WDUMMY_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_C_WDUMMY_ALWAYS_OUT_S  1
+/** SPI_MEM_C_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
+ *  In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is
+ *  output by the MSPI controller in the first half part of dummy phase. It is used to
+ *  mask invalid SPI_DQS in the half part of dummy phase.
+ */
+#define SPI_MEM_C_FDUMMY_RIN    (BIT(2))
+#define SPI_MEM_C_FDUMMY_RIN_M  (SPI_MEM_C_FDUMMY_RIN_V << SPI_MEM_C_FDUMMY_RIN_S)
+#define SPI_MEM_C_FDUMMY_RIN_V  0x00000001U
+#define SPI_MEM_C_FDUMMY_RIN_S  2
+/** SPI_MEM_C_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
+ *  In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is
+ *  output by the MSPI controller in the second half part of dummy phase. It is used to
+ *  pre-drive flash.
+ */
+#define SPI_MEM_C_FDUMMY_WOUT    (BIT(3))
+#define SPI_MEM_C_FDUMMY_WOUT_M  (SPI_MEM_C_FDUMMY_WOUT_V << SPI_MEM_C_FDUMMY_WOUT_S)
+#define SPI_MEM_C_FDUMMY_WOUT_V  0x00000001U
+#define SPI_MEM_C_FDUMMY_WOUT_S  3
+/** SPI_MEM_C_FDOUT_OCT : HRO; bitpos: [4]; default: 0;
+ *  Apply 8 signals during write-data phase 1:enable 0: disable
+ */
+#define SPI_MEM_C_FDOUT_OCT    (BIT(4))
+#define SPI_MEM_C_FDOUT_OCT_M  (SPI_MEM_C_FDOUT_OCT_V << SPI_MEM_C_FDOUT_OCT_S)
+#define SPI_MEM_C_FDOUT_OCT_V  0x00000001U
+#define SPI_MEM_C_FDOUT_OCT_S  4
+/** SPI_MEM_C_FDIN_OCT : HRO; bitpos: [5]; default: 0;
+ *  Apply 8 signals during read-data phase 1:enable 0: disable
+ */
+#define SPI_MEM_C_FDIN_OCT    (BIT(5))
+#define SPI_MEM_C_FDIN_OCT_M  (SPI_MEM_C_FDIN_OCT_V << SPI_MEM_C_FDIN_OCT_S)
+#define SPI_MEM_C_FDIN_OCT_V  0x00000001U
+#define SPI_MEM_C_FDIN_OCT_S  5
+/** SPI_MEM_C_FADDR_OCT : HRO; bitpos: [6]; default: 0;
+ *  Apply 8 signals during address phase 1:enable 0: disable
+ */
+#define SPI_MEM_C_FADDR_OCT    (BIT(6))
+#define SPI_MEM_C_FADDR_OCT_M  (SPI_MEM_C_FADDR_OCT_V << SPI_MEM_C_FADDR_OCT_S)
+#define SPI_MEM_C_FADDR_OCT_V  0x00000001U
+#define SPI_MEM_C_FADDR_OCT_S  6
+/** SPI_MEM_C_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
+ *  Apply 4 signals during command phase 1:enable 0: disable
+ */
+#define SPI_MEM_C_FCMD_QUAD    (BIT(8))
+#define SPI_MEM_C_FCMD_QUAD_M  (SPI_MEM_C_FCMD_QUAD_V << SPI_MEM_C_FCMD_QUAD_S)
+#define SPI_MEM_C_FCMD_QUAD_V  0x00000001U
+#define SPI_MEM_C_FCMD_QUAD_S  8
+/** SPI_MEM_C_FCMD_OCT : HRO; bitpos: [9]; default: 0;
+ *  Apply 8 signals during command phase 1:enable 0: disable
+ */
+#define SPI_MEM_C_FCMD_OCT    (BIT(9))
+#define SPI_MEM_C_FCMD_OCT_M  (SPI_MEM_C_FCMD_OCT_V << SPI_MEM_C_FCMD_OCT_S)
+#define SPI_MEM_C_FCMD_OCT_V  0x00000001U
+#define SPI_MEM_C_FCMD_OCT_S  9
+/** SPI_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
+ *  This bit enable the bits: SPI_MEM_C_FREAD_QIO, SPI_MEM_C_FREAD_DIO, SPI_MEM_C_FREAD_QOUT
+ *  and SPI_MEM_C_FREAD_DOUT. 1: enable 0: disable.
+ */
+#define SPI_MEM_C_FASTRD_MODE    (BIT(13))
+#define SPI_MEM_C_FASTRD_MODE_M  (SPI_MEM_C_FASTRD_MODE_V << SPI_MEM_C_FASTRD_MODE_S)
+#define SPI_MEM_C_FASTRD_MODE_V  0x00000001U
+#define SPI_MEM_C_FASTRD_MODE_S  13
+/** SPI_MEM_C_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+ *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+ */
+#define SPI_MEM_C_FREAD_DUAL    (BIT(14))
+#define SPI_MEM_C_FREAD_DUAL_M  (SPI_MEM_C_FREAD_DUAL_V << SPI_MEM_C_FREAD_DUAL_S)
+#define SPI_MEM_C_FREAD_DUAL_V  0x00000001U
+#define SPI_MEM_C_FREAD_DUAL_S  14
+/** SPI_MEM_C_Q_POL : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to set MISO line polarity, 1: high 0, low
+ */
+#define SPI_MEM_C_Q_POL    (BIT(18))
+#define SPI_MEM_C_Q_POL_M  (SPI_MEM_C_Q_POL_V << SPI_MEM_C_Q_POL_S)
+#define SPI_MEM_C_Q_POL_V  0x00000001U
+#define SPI_MEM_C_Q_POL_S  18
+/** SPI_MEM_C_D_POL : R/W; bitpos: [19]; default: 1;
+ *  The bit is used to set MOSI line polarity, 1: high 0, low
+ */
+#define SPI_MEM_C_D_POL    (BIT(19))
+#define SPI_MEM_C_D_POL_M  (SPI_MEM_C_D_POL_V << SPI_MEM_C_D_POL_S)
+#define SPI_MEM_C_D_POL_V  0x00000001U
+#define SPI_MEM_C_D_POL_S  19
+/** SPI_MEM_C_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
+ *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+ */
+#define SPI_MEM_C_FREAD_QUAD    (BIT(20))
+#define SPI_MEM_C_FREAD_QUAD_M  (SPI_MEM_C_FREAD_QUAD_V << SPI_MEM_C_FREAD_QUAD_S)
+#define SPI_MEM_C_FREAD_QUAD_V  0x00000001U
+#define SPI_MEM_C_FREAD_QUAD_S  20
+/** SPI_MEM_C_WP_REG : R/W; bitpos: [21]; default: 1;
+ *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
+ */
+#define SPI_MEM_C_WP_REG    (BIT(21))
+#define SPI_MEM_C_WP_REG_M  (SPI_MEM_C_WP_REG_V << SPI_MEM_C_WP_REG_S)
+#define SPI_MEM_C_WP_REG_V  0x00000001U
+#define SPI_MEM_C_WP_REG_S  21
+/** SPI_MEM_C_FREAD_DIO : R/W; bitpos: [23]; default: 0;
+ *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
+ *  0: disable.
+ */
+#define SPI_MEM_C_FREAD_DIO    (BIT(23))
+#define SPI_MEM_C_FREAD_DIO_M  (SPI_MEM_C_FREAD_DIO_V << SPI_MEM_C_FREAD_DIO_S)
+#define SPI_MEM_C_FREAD_DIO_V  0x00000001U
+#define SPI_MEM_C_FREAD_DIO_S  23
+/** SPI_MEM_C_FREAD_QIO : R/W; bitpos: [24]; default: 0;
+ *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
+ *  0: disable.
+ */
+#define SPI_MEM_C_FREAD_QIO    (BIT(24))
+#define SPI_MEM_C_FREAD_QIO_M  (SPI_MEM_C_FREAD_QIO_V << SPI_MEM_C_FREAD_QIO_S)
+#define SPI_MEM_C_FREAD_QIO_V  0x00000001U
+#define SPI_MEM_C_FREAD_QIO_S  24
+/** SPI_MEM_C_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 0;
+ *  When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
+ *  1. 0: Others.
+ */
+#define SPI_MEM_C_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_C_DQS_IE_ALWAYS_ON_M  (SPI_MEM_C_DQS_IE_ALWAYS_ON_V << SPI_MEM_C_DQS_IE_ALWAYS_ON_S)
+#define SPI_MEM_C_DQS_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_C_DQS_IE_ALWAYS_ON_S  30
+/** SPI_MEM_C_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1;
+ *  When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are
+ *  always 1. 0: Others.
+ */
+#define SPI_MEM_C_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_C_DATA_IE_ALWAYS_ON_M  (SPI_MEM_C_DATA_IE_ALWAYS_ON_V << SPI_MEM_C_DATA_IE_ALWAYS_ON_S)
+#define SPI_MEM_C_DATA_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_C_DATA_IE_ALWAYS_ON_S  31
+
+/** SPI_MEM_C_CTRL1_REG register
+ *  SPI0 control1 register.
+ */
+#define SPI_MEM_C_CTRL1_REG (DR_REG_FLASH_SPI0_BASE + 0xc)
+/** SPI_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+ *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+ *  SPI clock is always on.
+ */
+#define SPI_MEM_C_CLK_MODE    0x00000003U
+#define SPI_MEM_C_CLK_MODE_M  (SPI_MEM_C_CLK_MODE_V << SPI_MEM_C_CLK_MODE_S)
+#define SPI_MEM_C_CLK_MODE_V  0x00000003U
+#define SPI_MEM_C_CLK_MODE_S  0
+/** SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1;
+ *  1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply
+ *  the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.
+ */
+#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
+#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_M  (SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_V << SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_S)
+#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_V  0x00000001U
+#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_S  21
+/** SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1;
+ *  1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.
+ */
+#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
+#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_M  (SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_S)
+#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_V  0x00000001U
+#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_S  22
+/** SPI_MEM_C_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1;
+ *  1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0:
+ *  Reply AXI read data to AXI bus when all the read data is available.
+ */
+#define SPI_MEM_C_AXI_RDATA_BACK_FAST    (BIT(23))
+#define SPI_MEM_C_AXI_RDATA_BACK_FAST_M  (SPI_MEM_C_AXI_RDATA_BACK_FAST_V << SPI_MEM_C_AXI_RDATA_BACK_FAST_S)
+#define SPI_MEM_C_AXI_RDATA_BACK_FAST_V  0x00000001U
+#define SPI_MEM_C_AXI_RDATA_BACK_FAST_S  23
+/** SPI_MEM_C_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0;
+ *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
+ *  when there is a ECC error in AXI read data. The ECC error information is recorded
+ *  in SPI_MEM_C_ECC_ERR_ADDR_REG.
+ */
+#define SPI_MEM_C_RRESP_ECC_ERR_EN    (BIT(24))
+#define SPI_MEM_C_RRESP_ECC_ERR_EN_M  (SPI_MEM_C_RRESP_ECC_ERR_EN_V << SPI_MEM_C_RRESP_ECC_ERR_EN_S)
+#define SPI_MEM_C_RRESP_ECC_ERR_EN_V  0x00000001U
+#define SPI_MEM_C_RRESP_ECC_ERR_EN_S  24
+/** SPI_MEM_C_AR_SPLICE_EN : HRO; bitpos: [25]; default: 0;
+ *  Set this bit to enable AXI Read Splice-transfer.
+ */
+#define SPI_MEM_C_AR_SPLICE_EN    (BIT(25))
+#define SPI_MEM_C_AR_SPLICE_EN_M  (SPI_MEM_C_AR_SPLICE_EN_V << SPI_MEM_C_AR_SPLICE_EN_S)
+#define SPI_MEM_C_AR_SPLICE_EN_V  0x00000001U
+#define SPI_MEM_C_AR_SPLICE_EN_S  25
+/** SPI_MEM_C_AW_SPLICE_EN : HRO; bitpos: [26]; default: 0;
+ *  Set this bit to enable AXI Write Splice-transfer.
+ */
+#define SPI_MEM_C_AW_SPLICE_EN    (BIT(26))
+#define SPI_MEM_C_AW_SPLICE_EN_M  (SPI_MEM_C_AW_SPLICE_EN_V << SPI_MEM_C_AW_SPLICE_EN_S)
+#define SPI_MEM_C_AW_SPLICE_EN_V  0x00000001U
+#define SPI_MEM_C_AW_SPLICE_EN_S  26
+/** SPI_MEM_C_RAM0_EN : HRO; bitpos: [27]; default: 1;
+ *  When SPI_MEM_C_DUAL_RAM_EN is 0 and SPI_MEM_C_RAM0_EN is 1, only EXT_RAM0 will be
+ *  accessed. When SPI_MEM_C_DUAL_RAM_EN is 0 and SPI_MEM_C_RAM0_EN is 0, only EXT_RAM1
+ *  will be accessed. When SPI_MEM_C_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
+ *  accessed at the same time.
+ */
+#define SPI_MEM_C_RAM0_EN    (BIT(27))
+#define SPI_MEM_C_RAM0_EN_M  (SPI_MEM_C_RAM0_EN_V << SPI_MEM_C_RAM0_EN_S)
+#define SPI_MEM_C_RAM0_EN_V  0x00000001U
+#define SPI_MEM_C_RAM0_EN_S  27
+/** SPI_MEM_C_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0;
+ *  Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the
+ *  same time.
+ */
+#define SPI_MEM_C_DUAL_RAM_EN    (BIT(28))
+#define SPI_MEM_C_DUAL_RAM_EN_M  (SPI_MEM_C_DUAL_RAM_EN_V << SPI_MEM_C_DUAL_RAM_EN_S)
+#define SPI_MEM_C_DUAL_RAM_EN_V  0x00000001U
+#define SPI_MEM_C_DUAL_RAM_EN_S  28
+/** SPI_MEM_C_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1;
+ *  Set this bit to write data faster, do not wait write data has been stored in
+ *  tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
+ *  in  tx_bus_fifo_l2.
+ */
+#define SPI_MEM_C_FAST_WRITE_EN    (BIT(29))
+#define SPI_MEM_C_FAST_WRITE_EN_M  (SPI_MEM_C_FAST_WRITE_EN_V << SPI_MEM_C_FAST_WRITE_EN_S)
+#define SPI_MEM_C_FAST_WRITE_EN_V  0x00000001U
+#define SPI_MEM_C_FAST_WRITE_EN_S  29
+/** SPI_MEM_C_RXFIFO_RST : WT; bitpos: [30]; default: 0;
+ *  The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
+ *  receive signals from AXI.  Set this bit to reset these FIFO.
+ */
+#define SPI_MEM_C_RXFIFO_RST    (BIT(30))
+#define SPI_MEM_C_RXFIFO_RST_M  (SPI_MEM_C_RXFIFO_RST_V << SPI_MEM_C_RXFIFO_RST_S)
+#define SPI_MEM_C_RXFIFO_RST_V  0x00000001U
+#define SPI_MEM_C_RXFIFO_RST_S  30
+/** SPI_MEM_C_TXFIFO_RST : WT; bitpos: [31]; default: 0;
+ *  The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
+ *  send signals to AXI. Set this bit to reset these FIFO.
+ */
+#define SPI_MEM_C_TXFIFO_RST    (BIT(31))
+#define SPI_MEM_C_TXFIFO_RST_M  (SPI_MEM_C_TXFIFO_RST_V << SPI_MEM_C_TXFIFO_RST_S)
+#define SPI_MEM_C_TXFIFO_RST_V  0x00000001U
+#define SPI_MEM_C_TXFIFO_RST_S  31
+
+/** SPI_MEM_C_CTRL2_REG register
+ *  SPI0 control2 register.
+ */
+#define SPI_MEM_C_CTRL2_REG (DR_REG_FLASH_SPI0_BASE + 0x10)
+/** SPI_MEM_C_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1;
+ *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
+ *  SPI_MEM_C_CS_SETUP bit.
+ */
+#define SPI_MEM_C_CS_SETUP_TIME    0x0000001FU
+#define SPI_MEM_C_CS_SETUP_TIME_M  (SPI_MEM_C_CS_SETUP_TIME_V << SPI_MEM_C_CS_SETUP_TIME_S)
+#define SPI_MEM_C_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_MEM_C_CS_SETUP_TIME_S  0
+/** SPI_MEM_C_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1;
+ *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
+ *  SPI_MEM_C_CS_HOLD bit.
+ */
+#define SPI_MEM_C_CS_HOLD_TIME    0x0000001FU
+#define SPI_MEM_C_CS_HOLD_TIME_M  (SPI_MEM_C_CS_HOLD_TIME_V << SPI_MEM_C_CS_HOLD_TIME_S)
+#define SPI_MEM_C_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_MEM_C_CS_HOLD_TIME_S  5
+/** SPI_MEM_C_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3;
+ *  SPI_MEM_C_CS_HOLD_TIME + SPI_MEM_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+ *  mode when accessed flash.
+ */
+#define SPI_MEM_C_ECC_CS_HOLD_TIME    0x00000007U
+#define SPI_MEM_C_ECC_CS_HOLD_TIME_M  (SPI_MEM_C_ECC_CS_HOLD_TIME_V << SPI_MEM_C_ECC_CS_HOLD_TIME_S)
+#define SPI_MEM_C_ECC_CS_HOLD_TIME_V  0x00000007U
+#define SPI_MEM_C_ECC_CS_HOLD_TIME_S  10
+/** SPI_MEM_C_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [13]; default: 1;
+ *  1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when
+ *  accesses flash.
+ */
+#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER    (BIT(13))
+#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_C_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_C_ECC_SKIP_PAGE_CORNER_S)
+#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER_V  0x00000001U
+#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER_S  13
+/** SPI_MEM_C_ECC_16TO18_BYTE_EN : HRO; bitpos: [14]; default: 0;
+ *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+ *  accesses flash.
+ */
+#define SPI_MEM_C_ECC_16TO18_BYTE_EN    (BIT(14))
+#define SPI_MEM_C_ECC_16TO18_BYTE_EN_M  (SPI_MEM_C_ECC_16TO18_BYTE_EN_V << SPI_MEM_C_ECC_16TO18_BYTE_EN_S)
+#define SPI_MEM_C_ECC_16TO18_BYTE_EN_V  0x00000001U
+#define SPI_MEM_C_ECC_16TO18_BYTE_EN_S  14
+/** SPI_MEM_C_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable SPI0 split one AXI read flash transfer into two SPI
+ *  transfers when one transfer will cross flash or EXT_RAM page corner, valid no
+ *  matter whether there is an ECC region or not.
+ */
+#define SPI_MEM_C_SPLIT_TRANS_EN    (BIT(24))
+#define SPI_MEM_C_SPLIT_TRANS_EN_M  (SPI_MEM_C_SPLIT_TRANS_EN_V << SPI_MEM_C_SPLIT_TRANS_EN_S)
+#define SPI_MEM_C_SPLIT_TRANS_EN_V  0x00000001U
+#define SPI_MEM_C_SPLIT_TRANS_EN_S  24
+/** SPI_MEM_C_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0;
+ *  These bits are used to set the minimum CS high time tSHSL between SPI burst
+ *  transfer when accesses to flash. tSHSL is (SPI_MEM_C_CS_HOLD_DELAY[5:0] + 1) MSPI
+ *  core clock cycles.
+ */
+#define SPI_MEM_C_CS_HOLD_DELAY    0x0000003FU
+#define SPI_MEM_C_CS_HOLD_DELAY_M  (SPI_MEM_C_CS_HOLD_DELAY_V << SPI_MEM_C_CS_HOLD_DELAY_S)
+#define SPI_MEM_C_CS_HOLD_DELAY_V  0x0000003FU
+#define SPI_MEM_C_CS_HOLD_DELAY_S  25
+/** SPI_MEM_C_SYNC_RESET : WT; bitpos: [31]; default: 0;
+ *  The spi0_mst_st and spi0_slv_st will be reset.
+ */
+#define SPI_MEM_C_SYNC_RESET    (BIT(31))
+#define SPI_MEM_C_SYNC_RESET_M  (SPI_MEM_C_SYNC_RESET_V << SPI_MEM_C_SYNC_RESET_S)
+#define SPI_MEM_C_SYNC_RESET_V  0x00000001U
+#define SPI_MEM_C_SYNC_RESET_S  31
+
+/** SPI_MEM_C_CLOCK_REG register
+ *  SPI clock division control register.
+ */
+#define SPI_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI0_BASE + 0x14)
+/** SPI_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+ *  In the master mode it must be equal to spi_mem_clkcnt_N.
+ */
+#define SPI_MEM_C_CLKCNT_L    0x000000FFU
+#define SPI_MEM_C_CLKCNT_L_M  (SPI_MEM_C_CLKCNT_L_V << SPI_MEM_C_CLKCNT_L_S)
+#define SPI_MEM_C_CLKCNT_L_V  0x000000FFU
+#define SPI_MEM_C_CLKCNT_L_S  0
+/** SPI_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+ *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+ */
+#define SPI_MEM_C_CLKCNT_H    0x000000FFU
+#define SPI_MEM_C_CLKCNT_H_M  (SPI_MEM_C_CLKCNT_H_V << SPI_MEM_C_CLKCNT_H_S)
+#define SPI_MEM_C_CLKCNT_H_V  0x000000FFU
+#define SPI_MEM_C_CLKCNT_H_S  8
+/** SPI_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+ *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+ *  system/(spi_mem_clkcnt_N+1)
+ */
+#define SPI_MEM_C_CLKCNT_N    0x000000FFU
+#define SPI_MEM_C_CLKCNT_N_M  (SPI_MEM_C_CLKCNT_N_V << SPI_MEM_C_CLKCNT_N_S)
+#define SPI_MEM_C_CLKCNT_N_V  0x000000FFU
+#define SPI_MEM_C_CLKCNT_N_S  16
+/** SPI_MEM_C_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+ *  1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
+ *  clock.
+ */
+#define SPI_MEM_C_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_C_CLK_EQU_SYSCLK_M  (SPI_MEM_C_CLK_EQU_SYSCLK_V << SPI_MEM_C_CLK_EQU_SYSCLK_S)
+#define SPI_MEM_C_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI_MEM_C_CLK_EQU_SYSCLK_S  31
+
+/** SPI_MEM_C_USER_REG register
+ *  SPI0 user register.
+ */
+#define SPI_MEM_C_USER_REG (DR_REG_FLASH_SPI0_BASE + 0x18)
+/** SPI_MEM_C_CS_HOLD : R/W; bitpos: [6]; default: 0;
+ *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable.
+ */
+#define SPI_MEM_C_CS_HOLD    (BIT(6))
+#define SPI_MEM_C_CS_HOLD_M  (SPI_MEM_C_CS_HOLD_V << SPI_MEM_C_CS_HOLD_S)
+#define SPI_MEM_C_CS_HOLD_V  0x00000001U
+#define SPI_MEM_C_CS_HOLD_S  6
+/** SPI_MEM_C_CS_SETUP : R/W; bitpos: [7]; default: 0;
+ *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.
+ */
+#define SPI_MEM_C_CS_SETUP    (BIT(7))
+#define SPI_MEM_C_CS_SETUP_M  (SPI_MEM_C_CS_SETUP_V << SPI_MEM_C_CS_SETUP_S)
+#define SPI_MEM_C_CS_SETUP_V  0x00000001U
+#define SPI_MEM_C_CS_SETUP_S  7
+/** SPI_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  The bit combined with SPI_MEM_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
+ */
+#define SPI_MEM_C_CK_OUT_EDGE    (BIT(9))
+#define SPI_MEM_C_CK_OUT_EDGE_M  (SPI_MEM_C_CK_OUT_EDGE_V << SPI_MEM_C_CK_OUT_EDGE_S)
+#define SPI_MEM_C_CK_OUT_EDGE_V  0x00000001U
+#define SPI_MEM_C_CK_OUT_EDGE_S  9
+/** SPI_MEM_C_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+ *  spi clock is disable in dummy phase when the bit is enable.
+ */
+#define SPI_MEM_C_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_MEM_C_USR_DUMMY_IDLE_M  (SPI_MEM_C_USR_DUMMY_IDLE_V << SPI_MEM_C_USR_DUMMY_IDLE_S)
+#define SPI_MEM_C_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI_MEM_C_USR_DUMMY_IDLE_S  26
+/** SPI_MEM_C_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+ *  This bit enable the dummy phase of an operation.
+ */
+#define SPI_MEM_C_USR_DUMMY    (BIT(29))
+#define SPI_MEM_C_USR_DUMMY_M  (SPI_MEM_C_USR_DUMMY_V << SPI_MEM_C_USR_DUMMY_S)
+#define SPI_MEM_C_USR_DUMMY_V  0x00000001U
+#define SPI_MEM_C_USR_DUMMY_S  29
+
+/** SPI_MEM_C_USER1_REG register
+ *  SPI0 user1 register.
+ */
+#define SPI_MEM_C_USER1_REG (DR_REG_FLASH_SPI0_BASE + 0x1c)
+/** SPI_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
+ *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+ *  (cycle_num-1).
+ */
+#define SPI_MEM_C_USR_DUMMY_CYCLELEN    0x0000003FU
+#define SPI_MEM_C_USR_DUMMY_CYCLELEN_M  (SPI_MEM_C_USR_DUMMY_CYCLELEN_V << SPI_MEM_C_USR_DUMMY_CYCLELEN_S)
+#define SPI_MEM_C_USR_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI_MEM_C_USR_DUMMY_CYCLELEN_S  0
+/** SPI_MEM_C_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1;
+ *  SPI0 USR_CMD read or write data byte length -1
+ */
+#define SPI_MEM_C_USR_DBYTELEN    0x00000007U
+#define SPI_MEM_C_USR_DBYTELEN_M  (SPI_MEM_C_USR_DBYTELEN_V << SPI_MEM_C_USR_DBYTELEN_S)
+#define SPI_MEM_C_USR_DBYTELEN_V  0x00000007U
+#define SPI_MEM_C_USR_DBYTELEN_S  6
+/** SPI_MEM_C_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
+ *  The length in bits of address phase. The register value shall be (bit_num-1).
+ */
+#define SPI_MEM_C_USR_ADDR_BITLEN    0x0000003FU
+#define SPI_MEM_C_USR_ADDR_BITLEN_M  (SPI_MEM_C_USR_ADDR_BITLEN_V << SPI_MEM_C_USR_ADDR_BITLEN_S)
+#define SPI_MEM_C_USR_ADDR_BITLEN_V  0x0000003FU
+#define SPI_MEM_C_USR_ADDR_BITLEN_S  26
+
+/** SPI_MEM_C_USER2_REG register
+ *  SPI0 user2 register.
+ */
+#define SPI_MEM_C_USER2_REG (DR_REG_FLASH_SPI0_BASE + 0x20)
+/** SPI_MEM_C_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  The value of  command.
+ */
+#define SPI_MEM_C_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI_MEM_C_USR_COMMAND_VALUE_M  (SPI_MEM_C_USR_COMMAND_VALUE_V << SPI_MEM_C_USR_COMMAND_VALUE_S)
+#define SPI_MEM_C_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI_MEM_C_USR_COMMAND_VALUE_S  0
+/** SPI_MEM_C_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+ *  The length in bits of command phase. The register value shall be (bit_num-1)
+ */
+#define SPI_MEM_C_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI_MEM_C_USR_COMMAND_BITLEN_M  (SPI_MEM_C_USR_COMMAND_BITLEN_V << SPI_MEM_C_USR_COMMAND_BITLEN_S)
+#define SPI_MEM_C_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI_MEM_C_USR_COMMAND_BITLEN_S  28
+
+/** SPI_MEM_C_MISC_REG register
+ *  SPI0 misc register
+ */
+#define SPI_MEM_C_MISC_REG (DR_REG_FLASH_SPI0_BASE + 0x34)
+/** SPI_MEM_C_FSUB_PIN : HRO; bitpos: [7]; default: 0;
+ *  For SPI0,  flash is connected to SUBPINs.
+ */
+#define SPI_MEM_C_FSUB_PIN    (BIT(7))
+#define SPI_MEM_C_FSUB_PIN_M  (SPI_MEM_C_FSUB_PIN_V << SPI_MEM_C_FSUB_PIN_S)
+#define SPI_MEM_C_FSUB_PIN_V  0x00000001U
+#define SPI_MEM_C_FSUB_PIN_S  7
+/** SPI_MEM_C_SSUB_PIN : HRO; bitpos: [8]; default: 0;
+ *  For SPI0,  sram is connected to SUBPINs.
+ */
+#define SPI_MEM_C_SSUB_PIN    (BIT(8))
+#define SPI_MEM_C_SSUB_PIN_M  (SPI_MEM_C_SSUB_PIN_V << SPI_MEM_C_SSUB_PIN_S)
+#define SPI_MEM_C_SSUB_PIN_V  0x00000001U
+#define SPI_MEM_C_SSUB_PIN_S  8
+/** SPI_MEM_C_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
+ *  1: SPI_CLK line is high when idle     0: spi clk line is low when idle
+ */
+#define SPI_MEM_C_CK_IDLE_EDGE    (BIT(9))
+#define SPI_MEM_C_CK_IDLE_EDGE_M  (SPI_MEM_C_CK_IDLE_EDGE_V << SPI_MEM_C_CK_IDLE_EDGE_S)
+#define SPI_MEM_C_CK_IDLE_EDGE_V  0x00000001U
+#define SPI_MEM_C_CK_IDLE_EDGE_S  9
+/** SPI_MEM_C_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
+ *  SPI_CS line keep low when the bit is set.
+ */
+#define SPI_MEM_C_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI_MEM_C_CS_KEEP_ACTIVE_M  (SPI_MEM_C_CS_KEEP_ACTIVE_V << SPI_MEM_C_CS_KEEP_ACTIVE_S)
+#define SPI_MEM_C_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI_MEM_C_CS_KEEP_ACTIVE_S  10
+
+/** SPI_MEM_C_CACHE_FCTRL_REG register
+ *  SPI0 bit mode control register.
+ */
+#define SPI_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x3c)
+/** SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1;
+ *  Set this bit to check AXI read/write the same address region.
+ */
+#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
+#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_M  (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S)
+#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_V  0x00000001U
+#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_S  30
+/** SPI_MEM_C_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1;
+ *  Set this bit to close AXI read/write transfer to MSPI, which means that only
+ *  SLV_ERR will be replied to BRESP/RRESP.
+ */
+#define SPI_MEM_C_CLOSE_AXI_INF_EN    (BIT(31))
+#define SPI_MEM_C_CLOSE_AXI_INF_EN_M  (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S)
+#define SPI_MEM_C_CLOSE_AXI_INF_EN_V  0x00000001U
+#define SPI_MEM_C_CLOSE_AXI_INF_EN_S  31
+
+/** SPI_MEM_C_SRAM_CMD_REG register
+ *  SPI0 external RAM mode control register
+ */
+#define SPI_MEM_C_SRAM_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x44)
+/** SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0;
+ *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ *  the level of SPI_DQS is output by the MSPI controller.
+ */
+#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
+#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_S)
+#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
+/** SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT : HRO; bitpos: [25]; default: 0;
+ *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ *  the level of SPI_IO[7:0] is output by the MSPI controller.
+ */
+#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
+#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_S)
+#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_S  25
+/** SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 1;
+ *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are
+ *  always 1. 0: Others.
+ */
+#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_M  (SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_S)
+#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_S  30
+/** SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON : HRO; bitpos: [31]; default: 1;
+ *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0]
+ *  are always 1. 0: Others.
+ */
+#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_M  (SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_S)
+#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_S  31
+
+/** SPI_MEM_C_FSM_REG register
+ *  SPI0 FSM status register
+ */
+#define SPI_MEM_C_FSM_REG (DR_REG_FLASH_SPI0_BASE + 0x54)
+/** SPI_MEM_C_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4;
+ *  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
+ */
+#define SPI_MEM_C_LOCK_DELAY_TIME    0x0000001FU
+#define SPI_MEM_C_LOCK_DELAY_TIME_M  (SPI_MEM_C_LOCK_DELAY_TIME_V << SPI_MEM_C_LOCK_DELAY_TIME_S)
+#define SPI_MEM_C_LOCK_DELAY_TIME_V  0x0000001FU
+#define SPI_MEM_C_LOCK_DELAY_TIME_S  7
+
+/** SPI_MEM_C_INT_ENA_REG register
+ *  SPI0 interrupt enable register
+ */
+#define SPI_MEM_C_INT_ENA_REG (DR_REG_FLASH_SPI0_BASE + 0xc0)
+/** SPI_MEM_C_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI_MEM_C_SLV_ST_END_INT interrupt.
+ */
+#define SPI_MEM_C_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI_MEM_C_SLV_ST_END_INT_ENA_M  (SPI_MEM_C_SLV_ST_END_INT_ENA_V << SPI_MEM_C_SLV_ST_END_INT_ENA_S)
+#define SPI_MEM_C_SLV_ST_END_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_SLV_ST_END_INT_ENA_S  3
+/** SPI_MEM_C_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI_MEM_C_MST_ST_END_INT interrupt.
+ */
+#define SPI_MEM_C_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI_MEM_C_MST_ST_END_INT_ENA_M  (SPI_MEM_C_MST_ST_END_INT_ENA_V << SPI_MEM_C_MST_ST_END_INT_ENA_S)
+#define SPI_MEM_C_MST_ST_END_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_MST_ST_END_INT_ENA_S  4
+/** SPI_MEM_C_ECC_ERR_INT_ENA : HRO; bitpos: [5]; default: 0;
+ *  The enable bit for SPI_MEM_C_ECC_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_ECC_ERR_INT_ENA    (BIT(5))
+#define SPI_MEM_C_ECC_ERR_INT_ENA_M  (SPI_MEM_C_ECC_ERR_INT_ENA_V << SPI_MEM_C_ECC_ERR_INT_ENA_S)
+#define SPI_MEM_C_ECC_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_ECC_ERR_INT_ENA_S  5
+/** SPI_MEM_C_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for SPI_MEM_C_PMS_REJECT_INT interrupt.
+ */
+#define SPI_MEM_C_PMS_REJECT_INT_ENA    (BIT(6))
+#define SPI_MEM_C_PMS_REJECT_INT_ENA_M  (SPI_MEM_C_PMS_REJECT_INT_ENA_V << SPI_MEM_C_PMS_REJECT_INT_ENA_S)
+#define SPI_MEM_C_PMS_REJECT_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_PMS_REJECT_INT_ENA_S  6
+/** SPI_MEM_C_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA    (BIT(7))
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_M  (SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_S)
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_S  7
+/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA : HRO; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_M  (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_S)
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_S  8
+/** SPI_MEM_C_AXI_WADDR_ERR_INT__ENA : HRO; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA    (BIT(9))
+#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_M  (SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_S)
+#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_V  0x00000001U
+#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_S  9
+
+/** SPI_MEM_C_INT_CLR_REG register
+ *  SPI0 interrupt clear register
+ */
+#define SPI_MEM_C_INT_CLR_REG (DR_REG_FLASH_SPI0_BASE + 0xc4)
+/** SPI_MEM_C_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI_MEM_C_SLV_ST_END_INT interrupt.
+ */
+#define SPI_MEM_C_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI_MEM_C_SLV_ST_END_INT_CLR_M  (SPI_MEM_C_SLV_ST_END_INT_CLR_V << SPI_MEM_C_SLV_ST_END_INT_CLR_S)
+#define SPI_MEM_C_SLV_ST_END_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_SLV_ST_END_INT_CLR_S  3
+/** SPI_MEM_C_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI_MEM_C_MST_ST_END_INT interrupt.
+ */
+#define SPI_MEM_C_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI_MEM_C_MST_ST_END_INT_CLR_M  (SPI_MEM_C_MST_ST_END_INT_CLR_V << SPI_MEM_C_MST_ST_END_INT_CLR_S)
+#define SPI_MEM_C_MST_ST_END_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_MST_ST_END_INT_CLR_S  4
+/** SPI_MEM_C_ECC_ERR_INT_CLR : HRO; bitpos: [5]; default: 0;
+ *  The clear bit for SPI_MEM_C_ECC_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_ECC_ERR_INT_CLR    (BIT(5))
+#define SPI_MEM_C_ECC_ERR_INT_CLR_M  (SPI_MEM_C_ECC_ERR_INT_CLR_V << SPI_MEM_C_ECC_ERR_INT_CLR_S)
+#define SPI_MEM_C_ECC_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_ECC_ERR_INT_CLR_S  5
+/** SPI_MEM_C_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The clear bit for SPI_MEM_C_PMS_REJECT_INT interrupt.
+ */
+#define SPI_MEM_C_PMS_REJECT_INT_CLR    (BIT(6))
+#define SPI_MEM_C_PMS_REJECT_INT_CLR_M  (SPI_MEM_C_PMS_REJECT_INT_CLR_V << SPI_MEM_C_PMS_REJECT_INT_CLR_S)
+#define SPI_MEM_C_PMS_REJECT_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_PMS_REJECT_INT_CLR_S  6
+/** SPI_MEM_C_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The clear bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR    (BIT(7))
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_M  (SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_S)
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_S  7
+/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR : HRO; bitpos: [8]; default: 0;
+ *  The clear bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_M  (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_S)
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_S  8
+/** SPI_MEM_C_AXI_WADDR_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
+ *  The clear bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR    (BIT(9))
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_M  (SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_S)
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_S  9
+
+/** SPI_MEM_C_INT_RAW_REG register
+ *  SPI0 interrupt raw register
+ */
+#define SPI_MEM_C_INT_RAW_REG (DR_REG_FLASH_SPI0_BASE + 0xc8)
+/** SPI_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
+ *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
+ *  Others
+ */
+#define SPI_MEM_C_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI_MEM_C_SLV_ST_END_INT_RAW_M  (SPI_MEM_C_SLV_ST_END_INT_RAW_V << SPI_MEM_C_SLV_ST_END_INT_RAW_S)
+#define SPI_MEM_C_SLV_ST_END_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_SLV_ST_END_INT_RAW_S  3
+/** SPI_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
+ *  changed from non idle state to idle state. 0: Others.
+ */
+#define SPI_MEM_C_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI_MEM_C_MST_ST_END_INT_RAW_M  (SPI_MEM_C_MST_ST_END_INT_RAW_V << SPI_MEM_C_MST_ST_END_INT_RAW_S)
+#define SPI_MEM_C_MST_ST_END_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_MST_ST_END_INT_RAW_S  4
+/** SPI_MEM_C_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0;
+ *  The raw bit for SPI_MEM_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set
+ *  and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
+ *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_C_ECC_ERR_INT_NUM. When
+ *  SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is
+ *  triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
+ *  than SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and
+ *  SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+ *  of SPI0/1 ECC read external RAM and flash are equal or bigger than
+ *  SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN
+ *  are cleared, this bit will not be triggered.
+ */
+#define SPI_MEM_C_ECC_ERR_INT_RAW    (BIT(5))
+#define SPI_MEM_C_ECC_ERR_INT_RAW_M  (SPI_MEM_C_ECC_ERR_INT_RAW_V << SPI_MEM_C_ECC_ERR_INT_RAW_S)
+#define SPI_MEM_C_ECC_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_ECC_ERR_INT_RAW_S  5
+/** SPI_MEM_C_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit for SPI_MEM_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
+ *  rejected. 0: Others.
+ */
+#define SPI_MEM_C_PMS_REJECT_INT_RAW    (BIT(6))
+#define SPI_MEM_C_PMS_REJECT_INT_RAW_M  (SPI_MEM_C_PMS_REJECT_INT_RAW_V << SPI_MEM_C_PMS_REJECT_INT_RAW_S)
+#define SPI_MEM_C_PMS_REJECT_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_PMS_REJECT_INT_RAW_S  6
+/** SPI_MEM_C_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+ *  address is invalid by compared to MMU configuration. 0: Others.
+ */
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW    (BIT(7))
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_M  (SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_S)
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_S  7
+/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0;
+ *  The raw bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
+ *  flash request is received. 0: Others.
+ */
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_M  (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_S)
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_S  8
+/** SPI_MEM_C_AXI_WADDR_ERR_INT_RAW : HRO; bitpos: [9]; default: 0;
+ *  The raw bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+ *  address is invalid by compared to MMU configuration. 0: Others.
+ */
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW    (BIT(9))
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_M  (SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_S)
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_S  9
+
+/** SPI_MEM_C_INT_ST_REG register
+ *  SPI0 interrupt status register
+ */
+#define SPI_MEM_C_INT_ST_REG (DR_REG_FLASH_SPI0_BASE + 0xcc)
+/** SPI_MEM_C_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI_MEM_C_SLV_ST_END_INT interrupt.
+ */
+#define SPI_MEM_C_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI_MEM_C_SLV_ST_END_INT_ST_M  (SPI_MEM_C_SLV_ST_END_INT_ST_V << SPI_MEM_C_SLV_ST_END_INT_ST_S)
+#define SPI_MEM_C_SLV_ST_END_INT_ST_V  0x00000001U
+#define SPI_MEM_C_SLV_ST_END_INT_ST_S  3
+/** SPI_MEM_C_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI_MEM_C_MST_ST_END_INT interrupt.
+ */
+#define SPI_MEM_C_MST_ST_END_INT_ST    (BIT(4))
+#define SPI_MEM_C_MST_ST_END_INT_ST_M  (SPI_MEM_C_MST_ST_END_INT_ST_V << SPI_MEM_C_MST_ST_END_INT_ST_S)
+#define SPI_MEM_C_MST_ST_END_INT_ST_V  0x00000001U
+#define SPI_MEM_C_MST_ST_END_INT_ST_S  4
+/** SPI_MEM_C_ECC_ERR_INT_ST : HRO; bitpos: [5]; default: 0;
+ *  The status bit for SPI_MEM_C_ECC_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_ECC_ERR_INT_ST    (BIT(5))
+#define SPI_MEM_C_ECC_ERR_INT_ST_M  (SPI_MEM_C_ECC_ERR_INT_ST_V << SPI_MEM_C_ECC_ERR_INT_ST_S)
+#define SPI_MEM_C_ECC_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_C_ECC_ERR_INT_ST_S  5
+/** SPI_MEM_C_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The status bit for SPI_MEM_C_PMS_REJECT_INT interrupt.
+ */
+#define SPI_MEM_C_PMS_REJECT_INT_ST    (BIT(6))
+#define SPI_MEM_C_PMS_REJECT_INT_ST_M  (SPI_MEM_C_PMS_REJECT_INT_ST_V << SPI_MEM_C_PMS_REJECT_INT_ST_S)
+#define SPI_MEM_C_PMS_REJECT_INT_ST_V  0x00000001U
+#define SPI_MEM_C_PMS_REJECT_INT_ST_S  6
+/** SPI_MEM_C_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST    (BIT(7))
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST_M  (SPI_MEM_C_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_C_AXI_RADDR_ERR_INT_ST_S)
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST_S  7
+/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST : HRO; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_M  (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_S)
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_S  8
+/** SPI_MEM_C_AXI_WADDR_ERR_INT_ST : HRO; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST    (BIT(9))
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_M  (SPI_MEM_C_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_C_AXI_WADDR_ERR_INT_ST_S)
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_S  9
+
+/** SPI_MEM_C_DDR_REG register
+ *  SPI0 flash DDR mode control register
+ */
+#define SPI_MEM_C_DDR_REG (DR_REG_FLASH_SPI0_BASE + 0xd4)
+/** SPI_MEM_C_FMEM__DDR_EN : HRO; bitpos: [0]; default: 0;
+ *  1: in DDR mode,  0 in SDR mode
+ */
+#define SPI_MEM_C_FMEM__DDR_EN    (BIT(0))
+#define SPI_MEM_C_FMEM__DDR_EN_M  (SPI_MEM_C_FMEM__DDR_EN_V << SPI_MEM_C_FMEM__DDR_EN_S)
+#define SPI_MEM_C_FMEM__DDR_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__DDR_EN_S  0
+/** SPI_MEM_C_FMEM__VAR_DUMMY : HRO; bitpos: [1]; default: 0;
+ *  Set the bit to enable variable dummy cycle in spi DDR mode.
+ */
+#define SPI_MEM_C_FMEM__VAR_DUMMY    (BIT(1))
+#define SPI_MEM_C_FMEM__VAR_DUMMY_M  (SPI_MEM_C_FMEM__VAR_DUMMY_V << SPI_MEM_C_FMEM__VAR_DUMMY_S)
+#define SPI_MEM_C_FMEM__VAR_DUMMY_V  0x00000001U
+#define SPI_MEM_C_FMEM__VAR_DUMMY_S  1
+/** SPI_MEM_C_FMEM__DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
+ *  Set the bit to reorder rx data of the word in spi DDR mode.
+ */
+#define SPI_MEM_C_FMEM__DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_C_FMEM__DDR_RDAT_SWP_M  (SPI_MEM_C_FMEM__DDR_RDAT_SWP_V << SPI_MEM_C_FMEM__DDR_RDAT_SWP_S)
+#define SPI_MEM_C_FMEM__DDR_RDAT_SWP_V  0x00000001U
+#define SPI_MEM_C_FMEM__DDR_RDAT_SWP_S  2
+/** SPI_MEM_C_FMEM__DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
+ *  Set the bit to reorder tx data of the word in spi DDR mode.
+ */
+#define SPI_MEM_C_FMEM__DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_C_FMEM__DDR_WDAT_SWP_M  (SPI_MEM_C_FMEM__DDR_WDAT_SWP_V << SPI_MEM_C_FMEM__DDR_WDAT_SWP_S)
+#define SPI_MEM_C_FMEM__DDR_WDAT_SWP_V  0x00000001U
+#define SPI_MEM_C_FMEM__DDR_WDAT_SWP_S  3
+/** SPI_MEM_C_FMEM__DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
+ *  the bit is used to disable dual edge in command phase when DDR mode.
+ */
+#define SPI_MEM_C_FMEM__DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_C_FMEM__DDR_CMD_DIS_M  (SPI_MEM_C_FMEM__DDR_CMD_DIS_V << SPI_MEM_C_FMEM__DDR_CMD_DIS_S)
+#define SPI_MEM_C_FMEM__DDR_CMD_DIS_V  0x00000001U
+#define SPI_MEM_C_FMEM__DDR_CMD_DIS_S  4
+/** SPI_MEM_C_FMEM__OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
+ *  It is the minimum output data length in the panda device.
+ */
+#define SPI_MEM_C_FMEM__OUTMINBYTELEN    0x0000007FU
+#define SPI_MEM_C_FMEM__OUTMINBYTELEN_M  (SPI_MEM_C_FMEM__OUTMINBYTELEN_V << SPI_MEM_C_FMEM__OUTMINBYTELEN_S)
+#define SPI_MEM_C_FMEM__OUTMINBYTELEN_V  0x0000007FU
+#define SPI_MEM_C_FMEM__OUTMINBYTELEN_S  5
+/** SPI_MEM_C_FMEM__TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1;
+ *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ *  accesses to flash.
+ */
+#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN_M  (SPI_MEM_C_FMEM__TX_DDR_MSK_EN_V << SPI_MEM_C_FMEM__TX_DDR_MSK_EN_S)
+#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN_S  12
+/** SPI_MEM_C_FMEM__RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1;
+ *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+ *  accesses to flash.
+ */
+#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN_M  (SPI_MEM_C_FMEM__RX_DDR_MSK_EN_V << SPI_MEM_C_FMEM__RX_DDR_MSK_EN_S)
+#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN_S  13
+/** SPI_MEM_C_FMEM__USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
+ *  The delay number of data strobe which from memory based on SPI clock.
+ */
+#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD    0x0000007FU
+#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_M  (SPI_MEM_C_FMEM__USR_DDR_DQS_THD_V << SPI_MEM_C_FMEM__USR_DDR_DQS_THD_S)
+#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_S  14
+/** SPI_MEM_C_FMEM__DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
+ *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+ *  spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal or
+ *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+ *  negative edge of SPI_DQS.
+ */
+#define SPI_MEM_C_FMEM__DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_C_FMEM__DDR_DQS_LOOP_M  (SPI_MEM_C_FMEM__DDR_DQS_LOOP_V << SPI_MEM_C_FMEM__DDR_DQS_LOOP_S)
+#define SPI_MEM_C_FMEM__DDR_DQS_LOOP_V  0x00000001U
+#define SPI_MEM_C_FMEM__DDR_DQS_LOOP_S  21
+/** SPI_MEM_C_FMEM__CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
+ *  Set this bit to enable the differential SPI_CLK#.
+ */
+#define SPI_MEM_C_FMEM__CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_C_FMEM__CLK_DIFF_EN_M  (SPI_MEM_C_FMEM__CLK_DIFF_EN_V << SPI_MEM_C_FMEM__CLK_DIFF_EN_S)
+#define SPI_MEM_C_FMEM__CLK_DIFF_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__CLK_DIFF_EN_S  24
+/** SPI_MEM_C_FMEM__DQS_CA_IN : HRO; bitpos: [26]; default: 0;
+ *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+ */
+#define SPI_MEM_C_FMEM__DQS_CA_IN    (BIT(26))
+#define SPI_MEM_C_FMEM__DQS_CA_IN_M  (SPI_MEM_C_FMEM__DQS_CA_IN_V << SPI_MEM_C_FMEM__DQS_CA_IN_S)
+#define SPI_MEM_C_FMEM__DQS_CA_IN_V  0x00000001U
+#define SPI_MEM_C_FMEM__DQS_CA_IN_S  26
+/** SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
+ *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+ *  accesses flash or SPI1 accesses flash or sram.
+ */
+#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_M  (SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_V << SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_S)
+#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_S  27
+/** SPI_MEM_C_FMEM__CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
+ *  Set this bit to invert SPI_DIFF when accesses to flash. .
+ */
+#define SPI_MEM_C_FMEM__CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_C_FMEM__CLK_DIFF_INV_M  (SPI_MEM_C_FMEM__CLK_DIFF_INV_V << SPI_MEM_C_FMEM__CLK_DIFF_INV_S)
+#define SPI_MEM_C_FMEM__CLK_DIFF_INV_V  0x00000001U
+#define SPI_MEM_C_FMEM__CLK_DIFF_INV_S  28
+/** SPI_MEM_C_FMEM__OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
+ *  Set this bit to enable octa_ram address out when accesses to flash, which means
+ *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
+ */
+#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR_M  (SPI_MEM_C_FMEM__OCTA_RAM_ADDR_V << SPI_MEM_C_FMEM__OCTA_RAM_ADDR_S)
+#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR_V  0x00000001U
+#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR_S  29
+/** SPI_MEM_C_FMEM__HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
+ *  Set this bit to enable HyperRAM address out when accesses to flash, which means
+ *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+ */
+#define SPI_MEM_C_FMEM__HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_C_FMEM__HYPERBUS_CA_M  (SPI_MEM_C_FMEM__HYPERBUS_CA_V << SPI_MEM_C_FMEM__HYPERBUS_CA_S)
+#define SPI_MEM_C_FMEM__HYPERBUS_CA_V  0x00000001U
+#define SPI_MEM_C_FMEM__HYPERBUS_CA_S  30
+
+/** SPI_MEM_C_SMEM_DDR_REG register
+ *  SPI0 external RAM DDR mode control register
+ */
+#define SPI_MEM_C_SMEM_DDR_REG (DR_REG_FLASH_SPI0_BASE + 0xd8)
+/** SPI_MEM_C_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
+ *  1: in DDR mode,  0 in SDR mode
+ */
+#define SPI_MEM_C_SMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_C_SMEM_DDR_EN_M  (SPI_MEM_C_SMEM_DDR_EN_V << SPI_MEM_C_SMEM_DDR_EN_S)
+#define SPI_MEM_C_SMEM_DDR_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_DDR_EN_S  0
+/** SPI_MEM_C_SMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
+ *  Set the bit to enable variable dummy cycle in spi DDR mode.
+ */
+#define SPI_MEM_C_SMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_C_SMEM_VAR_DUMMY_M  (SPI_MEM_C_SMEM_VAR_DUMMY_V << SPI_MEM_C_SMEM_VAR_DUMMY_S)
+#define SPI_MEM_C_SMEM_VAR_DUMMY_V  0x00000001U
+#define SPI_MEM_C_SMEM_VAR_DUMMY_S  1
+/** SPI_MEM_C_SMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
+ *  Set the bit to reorder rx data of the word in spi DDR mode.
+ */
+#define SPI_MEM_C_SMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_C_SMEM_DDR_RDAT_SWP_M  (SPI_MEM_C_SMEM_DDR_RDAT_SWP_V << SPI_MEM_C_SMEM_DDR_RDAT_SWP_S)
+#define SPI_MEM_C_SMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI_MEM_C_SMEM_DDR_RDAT_SWP_S  2
+/** SPI_MEM_C_SMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
+ *  Set the bit to reorder tx data of the word in spi DDR mode.
+ */
+#define SPI_MEM_C_SMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_C_SMEM_DDR_WDAT_SWP_M  (SPI_MEM_C_SMEM_DDR_WDAT_SWP_V << SPI_MEM_C_SMEM_DDR_WDAT_SWP_S)
+#define SPI_MEM_C_SMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI_MEM_C_SMEM_DDR_WDAT_SWP_S  3
+/** SPI_MEM_C_SMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
+ *  the bit is used to disable dual edge in command phase when DDR mode.
+ */
+#define SPI_MEM_C_SMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_C_SMEM_DDR_CMD_DIS_M  (SPI_MEM_C_SMEM_DDR_CMD_DIS_V << SPI_MEM_C_SMEM_DDR_CMD_DIS_S)
+#define SPI_MEM_C_SMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI_MEM_C_SMEM_DDR_CMD_DIS_S  4
+/** SPI_MEM_C_SMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
+ *  It is the minimum output data length in the DDR psram.
+ */
+#define SPI_MEM_C_SMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI_MEM_C_SMEM_OUTMINBYTELEN_M  (SPI_MEM_C_SMEM_OUTMINBYTELEN_V << SPI_MEM_C_SMEM_OUTMINBYTELEN_S)
+#define SPI_MEM_C_SMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI_MEM_C_SMEM_OUTMINBYTELEN_S  5
+/** SPI_MEM_C_SMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1;
+ *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ *  accesses to external RAM.
+ */
+#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN_M  (SPI_MEM_C_SMEM_TX_DDR_MSK_EN_V << SPI_MEM_C_SMEM_TX_DDR_MSK_EN_S)
+#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN_S  12
+/** SPI_MEM_C_SMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1;
+ *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+ *  accesses to external RAM.
+ */
+#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN_M  (SPI_MEM_C_SMEM_RX_DDR_MSK_EN_V << SPI_MEM_C_SMEM_RX_DDR_MSK_EN_S)
+#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN_S  13
+/** SPI_MEM_C_SMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
+ *  The delay number of data strobe which from memory based on SPI clock.
+ */
+#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_M  (SPI_MEM_C_SMEM_USR_DDR_DQS_THD_V << SPI_MEM_C_SMEM_USR_DDR_DQS_THD_S)
+#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_S  14
+/** SPI_MEM_C_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
+ *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+ *  spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal or
+ *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+ *  negative edge of SPI_DQS.
+ */
+#define SPI_MEM_C_SMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_C_SMEM_DDR_DQS_LOOP_M  (SPI_MEM_C_SMEM_DDR_DQS_LOOP_V << SPI_MEM_C_SMEM_DDR_DQS_LOOP_S)
+#define SPI_MEM_C_SMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI_MEM_C_SMEM_DDR_DQS_LOOP_S  21
+/** SPI_MEM_C_SMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
+ *  Set this bit to enable the differential SPI_CLK#.
+ */
+#define SPI_MEM_C_SMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_C_SMEM_CLK_DIFF_EN_M  (SPI_MEM_C_SMEM_CLK_DIFF_EN_V << SPI_MEM_C_SMEM_CLK_DIFF_EN_S)
+#define SPI_MEM_C_SMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_CLK_DIFF_EN_S  24
+/** SPI_MEM_C_SMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
+ *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+ */
+#define SPI_MEM_C_SMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_C_SMEM_DQS_CA_IN_M  (SPI_MEM_C_SMEM_DQS_CA_IN_V << SPI_MEM_C_SMEM_DQS_CA_IN_S)
+#define SPI_MEM_C_SMEM_DQS_CA_IN_V  0x00000001U
+#define SPI_MEM_C_SMEM_DQS_CA_IN_S  26
+/** SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
+ *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+ *  accesses flash or SPI1 accesses flash or sram.
+ */
+#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_M  (SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI_MEM_C_SMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
+ *  Set this bit to invert SPI_DIFF when accesses to external RAM. .
+ */
+#define SPI_MEM_C_SMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_C_SMEM_CLK_DIFF_INV_M  (SPI_MEM_C_SMEM_CLK_DIFF_INV_V << SPI_MEM_C_SMEM_CLK_DIFF_INV_S)
+#define SPI_MEM_C_SMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI_MEM_C_SMEM_CLK_DIFF_INV_S  28
+/** SPI_MEM_C_SMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
+ *  Set this bit to enable octa_ram address out when accesses to external RAM, which
+ *  means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1],
+ *  1'b0}.
+ */
+#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR_M  (SPI_MEM_C_SMEM_OCTA_RAM_ADDR_V << SPI_MEM_C_SMEM_OCTA_RAM_ADDR_S)
+#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR_S  29
+/** SPI_MEM_C_SMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
+ *  Set this bit to enable HyperRAM address out when accesses to external RAM, which
+ *  means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+ */
+#define SPI_MEM_C_SMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_C_SMEM_HYPERBUS_CA_M  (SPI_MEM_C_SMEM_HYPERBUS_CA_V << SPI_MEM_C_SMEM_HYPERBUS_CA_S)
+#define SPI_MEM_C_SMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI_MEM_C_SMEM_HYPERBUS_CA_S  30
+
+/** SPI_MEM_C_FMEM__PMS0_ATTR_REG register
+ *  MSPI flash PMS section 0 attribute register
+ */
+#define SPI_MEM_C_FMEM__PMS0_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x100)
+/** SPI_MEM_C_FMEM__PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 flash PMS section 0 read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_FMEM__PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_FMEM__PMS0_RD_ATTR_M  (SPI_MEM_C_FMEM__PMS0_RD_ATTR_V << SPI_MEM_C_FMEM__PMS0_RD_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS0_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS0_RD_ATTR_S  0
+/** SPI_MEM_C_FMEM__PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 flash PMS section 0 write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_FMEM__PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_FMEM__PMS0_WR_ATTR_M  (SPI_MEM_C_FMEM__PMS0_WR_ATTR_V << SPI_MEM_C_FMEM__PMS0_WR_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS0_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS0_WR_ATTR_S  1
+/** SPI_MEM_C_FMEM__PMS0_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
+ *  section 0 is configured by registers SPI_MEM_C_FMEM__PMS0_ADDR_REG and
+ *  SPI_MEM_C_FMEM__PMS0_SIZE_REG.
+ */
+#define SPI_MEM_C_FMEM__PMS0_ECC    (BIT(2))
+#define SPI_MEM_C_FMEM__PMS0_ECC_M  (SPI_MEM_C_FMEM__PMS0_ECC_V << SPI_MEM_C_FMEM__PMS0_ECC_S)
+#define SPI_MEM_C_FMEM__PMS0_ECC_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS0_ECC_S  2
+
+/** SPI_MEM_C_FMEM__PMS1_ATTR_REG register
+ *  MSPI flash PMS section 1 attribute register
+ */
+#define SPI_MEM_C_FMEM__PMS1_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x104)
+/** SPI_MEM_C_FMEM__PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 flash PMS section 1 read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_FMEM__PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_FMEM__PMS1_RD_ATTR_M  (SPI_MEM_C_FMEM__PMS1_RD_ATTR_V << SPI_MEM_C_FMEM__PMS1_RD_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS1_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS1_RD_ATTR_S  0
+/** SPI_MEM_C_FMEM__PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 flash PMS section 1 write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_FMEM__PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_FMEM__PMS1_WR_ATTR_M  (SPI_MEM_C_FMEM__PMS1_WR_ATTR_V << SPI_MEM_C_FMEM__PMS1_WR_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS1_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS1_WR_ATTR_S  1
+/** SPI_MEM_C_FMEM__PMS1_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
+ *  section 1 is configured by registers SPI_MEM_C_FMEM__PMS1_ADDR_REG and
+ *  SPI_MEM_C_FMEM__PMS1_SIZE_REG.
+ */
+#define SPI_MEM_C_FMEM__PMS1_ECC    (BIT(2))
+#define SPI_MEM_C_FMEM__PMS1_ECC_M  (SPI_MEM_C_FMEM__PMS1_ECC_V << SPI_MEM_C_FMEM__PMS1_ECC_S)
+#define SPI_MEM_C_FMEM__PMS1_ECC_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS1_ECC_S  2
+
+/** SPI_MEM_C_FMEM__PMS2_ATTR_REG register
+ *  MSPI flash PMS section 2 attribute register
+ */
+#define SPI_MEM_C_FMEM__PMS2_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x108)
+/** SPI_MEM_C_FMEM__PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 flash PMS section 2 read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_FMEM__PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_FMEM__PMS2_RD_ATTR_M  (SPI_MEM_C_FMEM__PMS2_RD_ATTR_V << SPI_MEM_C_FMEM__PMS2_RD_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS2_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS2_RD_ATTR_S  0
+/** SPI_MEM_C_FMEM__PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 flash PMS section 2 write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_FMEM__PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_FMEM__PMS2_WR_ATTR_M  (SPI_MEM_C_FMEM__PMS2_WR_ATTR_V << SPI_MEM_C_FMEM__PMS2_WR_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS2_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS2_WR_ATTR_S  1
+/** SPI_MEM_C_FMEM__PMS2_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
+ *  section 2 is configured by registers SPI_MEM_C_FMEM__PMS2_ADDR_REG and
+ *  SPI_MEM_C_FMEM__PMS2_SIZE_REG.
+ */
+#define SPI_MEM_C_FMEM__PMS2_ECC    (BIT(2))
+#define SPI_MEM_C_FMEM__PMS2_ECC_M  (SPI_MEM_C_FMEM__PMS2_ECC_V << SPI_MEM_C_FMEM__PMS2_ECC_S)
+#define SPI_MEM_C_FMEM__PMS2_ECC_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS2_ECC_S  2
+
+/** SPI_MEM_C_FMEM__PMS3_ATTR_REG register
+ *  MSPI flash PMS section 3 attribute register
+ */
+#define SPI_MEM_C_FMEM__PMS3_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x10c)
+/** SPI_MEM_C_FMEM__PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 flash PMS section 3 read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_FMEM__PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_FMEM__PMS3_RD_ATTR_M  (SPI_MEM_C_FMEM__PMS3_RD_ATTR_V << SPI_MEM_C_FMEM__PMS3_RD_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS3_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS3_RD_ATTR_S  0
+/** SPI_MEM_C_FMEM__PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 flash PMS section 3 write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_FMEM__PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_FMEM__PMS3_WR_ATTR_M  (SPI_MEM_C_FMEM__PMS3_WR_ATTR_V << SPI_MEM_C_FMEM__PMS3_WR_ATTR_S)
+#define SPI_MEM_C_FMEM__PMS3_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS3_WR_ATTR_S  1
+/** SPI_MEM_C_FMEM__PMS3_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
+ *  section 3 is configured by registers SPI_MEM_C_FMEM__PMS3_ADDR_REG and
+ *  SPI_MEM_C_FMEM__PMS3_SIZE_REG.
+ */
+#define SPI_MEM_C_FMEM__PMS3_ECC    (BIT(2))
+#define SPI_MEM_C_FMEM__PMS3_ECC_M  (SPI_MEM_C_FMEM__PMS3_ECC_V << SPI_MEM_C_FMEM__PMS3_ECC_S)
+#define SPI_MEM_C_FMEM__PMS3_ECC_V  0x00000001U
+#define SPI_MEM_C_FMEM__PMS3_ECC_S  2
+
+/** SPI_MEM_C_FMEM__PMS0_ADDR_REG register
+ *  SPI1 flash PMS section 0 start address register
+ */
+#define SPI_MEM_C_FMEM__PMS0_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x110)
+/** SPI_MEM_C_FMEM__PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+ *  SPI1 flash PMS section 0 start address value
+ */
+#define SPI_MEM_C_FMEM__PMS0_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS0_ADDR_S_M  (SPI_MEM_C_FMEM__PMS0_ADDR_S_V << SPI_MEM_C_FMEM__PMS0_ADDR_S_S)
+#define SPI_MEM_C_FMEM__PMS0_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS0_ADDR_S_S  0
+
+/** SPI_MEM_C_FMEM__PMS1_ADDR_REG register
+ *  SPI1 flash PMS section 1 start address register
+ */
+#define SPI_MEM_C_FMEM__PMS1_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x114)
+/** SPI_MEM_C_FMEM__PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+ *  SPI1 flash PMS section 1 start address value
+ */
+#define SPI_MEM_C_FMEM__PMS1_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS1_ADDR_S_M  (SPI_MEM_C_FMEM__PMS1_ADDR_S_V << SPI_MEM_C_FMEM__PMS1_ADDR_S_S)
+#define SPI_MEM_C_FMEM__PMS1_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS1_ADDR_S_S  0
+
+/** SPI_MEM_C_FMEM__PMS2_ADDR_REG register
+ *  SPI1 flash PMS section 2 start address register
+ */
+#define SPI_MEM_C_FMEM__PMS2_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x118)
+/** SPI_MEM_C_FMEM__PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+ *  SPI1 flash PMS section 2 start address value
+ */
+#define SPI_MEM_C_FMEM__PMS2_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS2_ADDR_S_M  (SPI_MEM_C_FMEM__PMS2_ADDR_S_V << SPI_MEM_C_FMEM__PMS2_ADDR_S_S)
+#define SPI_MEM_C_FMEM__PMS2_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS2_ADDR_S_S  0
+
+/** SPI_MEM_C_FMEM__PMS3_ADDR_REG register
+ *  SPI1 flash PMS section 3 start address register
+ */
+#define SPI_MEM_C_FMEM__PMS3_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x11c)
+/** SPI_MEM_C_FMEM__PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+ *  SPI1 flash PMS section 3 start address value
+ */
+#define SPI_MEM_C_FMEM__PMS3_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS3_ADDR_S_M  (SPI_MEM_C_FMEM__PMS3_ADDR_S_V << SPI_MEM_C_FMEM__PMS3_ADDR_S_S)
+#define SPI_MEM_C_FMEM__PMS3_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_FMEM__PMS3_ADDR_S_S  0
+
+/** SPI_MEM_C_FMEM__PMS0_SIZE_REG register
+ *  SPI1 flash PMS section 0 start address register
+ */
+#define SPI_MEM_C_FMEM__PMS0_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x120)
+/** SPI_MEM_C_FMEM__PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 0 address region is (SPI_MEM_C_FMEM__PMS0_ADDR_S,
+ *  SPI_MEM_C_FMEM__PMS0_ADDR_S + SPI_MEM_C_FMEM__PMS0_SIZE)
+ */
+#define SPI_MEM_C_FMEM__PMS0_SIZE    0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS0_SIZE_M  (SPI_MEM_C_FMEM__PMS0_SIZE_V << SPI_MEM_C_FMEM__PMS0_SIZE_S)
+#define SPI_MEM_C_FMEM__PMS0_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS0_SIZE_S  0
+
+/** SPI_MEM_C_FMEM__PMS1_SIZE_REG register
+ *  SPI1 flash PMS section 1 start address register
+ */
+#define SPI_MEM_C_FMEM__PMS1_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x124)
+/** SPI_MEM_C_FMEM__PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 1 address region is (SPI_MEM_C_FMEM__PMS1_ADDR_S,
+ *  SPI_MEM_C_FMEM__PMS1_ADDR_S + SPI_MEM_C_FMEM__PMS1_SIZE)
+ */
+#define SPI_MEM_C_FMEM__PMS1_SIZE    0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS1_SIZE_M  (SPI_MEM_C_FMEM__PMS1_SIZE_V << SPI_MEM_C_FMEM__PMS1_SIZE_S)
+#define SPI_MEM_C_FMEM__PMS1_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS1_SIZE_S  0
+
+/** SPI_MEM_C_FMEM__PMS2_SIZE_REG register
+ *  SPI1 flash PMS section 2 start address register
+ */
+#define SPI_MEM_C_FMEM__PMS2_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x128)
+/** SPI_MEM_C_FMEM__PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 2 address region is (SPI_MEM_C_FMEM__PMS2_ADDR_S,
+ *  SPI_MEM_C_FMEM__PMS2_ADDR_S + SPI_MEM_C_FMEM__PMS2_SIZE)
+ */
+#define SPI_MEM_C_FMEM__PMS2_SIZE    0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS2_SIZE_M  (SPI_MEM_C_FMEM__PMS2_SIZE_V << SPI_MEM_C_FMEM__PMS2_SIZE_S)
+#define SPI_MEM_C_FMEM__PMS2_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS2_SIZE_S  0
+
+/** SPI_MEM_C_FMEM__PMS3_SIZE_REG register
+ *  SPI1 flash PMS section 3 start address register
+ */
+#define SPI_MEM_C_FMEM__PMS3_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x12c)
+/** SPI_MEM_C_FMEM__PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section 3 address region is (SPI_MEM_C_FMEM__PMS3_ADDR_S,
+ *  SPI_MEM_C_FMEM__PMS3_ADDR_S + SPI_MEM_C_FMEM__PMS3_SIZE)
+ */
+#define SPI_MEM_C_FMEM__PMS3_SIZE    0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS3_SIZE_M  (SPI_MEM_C_FMEM__PMS3_SIZE_V << SPI_MEM_C_FMEM__PMS3_SIZE_S)
+#define SPI_MEM_C_FMEM__PMS3_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_FMEM__PMS3_SIZE_S  0
+
+/** SPI_MEM_C_SMEM_PMS0_ATTR_REG register
+ *  SPI1 flash PMS section 0 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS0_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x130)
+/** SPI_MEM_C_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_SMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_SMEM_PMS0_RD_ATTR_M  (SPI_MEM_C_SMEM_PMS0_RD_ATTR_V << SPI_MEM_C_SMEM_PMS0_RD_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS0_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS0_RD_ATTR_S  0
+/** SPI_MEM_C_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_SMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_SMEM_PMS0_WR_ATTR_M  (SPI_MEM_C_SMEM_PMS0_WR_ATTR_V << SPI_MEM_C_SMEM_PMS0_WR_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS0_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS0_WR_ATTR_S  1
+/** SPI_MEM_C_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The
+ *  external RAM PMS section 0 is configured by registers SPI_MEM_C_SMEM_PMS0_ADDR_REG and
+ *  SPI_MEM_C_SMEM_PMS0_SIZE_REG.
+ */
+#define SPI_MEM_C_SMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_C_SMEM_PMS0_ECC_M  (SPI_MEM_C_SMEM_PMS0_ECC_V << SPI_MEM_C_SMEM_PMS0_ECC_S)
+#define SPI_MEM_C_SMEM_PMS0_ECC_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS0_ECC_S  2
+
+/** SPI_MEM_C_SMEM_PMS1_ATTR_REG register
+ *  SPI1 flash PMS section 1 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS1_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x134)
+/** SPI_MEM_C_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_SMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_SMEM_PMS1_RD_ATTR_M  (SPI_MEM_C_SMEM_PMS1_RD_ATTR_V << SPI_MEM_C_SMEM_PMS1_RD_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS1_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS1_RD_ATTR_S  0
+/** SPI_MEM_C_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_SMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_SMEM_PMS1_WR_ATTR_M  (SPI_MEM_C_SMEM_PMS1_WR_ATTR_V << SPI_MEM_C_SMEM_PMS1_WR_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS1_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS1_WR_ATTR_S  1
+/** SPI_MEM_C_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The
+ *  external RAM PMS section 1 is configured by registers SPI_MEM_C_SMEM_PMS1_ADDR_REG and
+ *  SPI_MEM_C_SMEM_PMS1_SIZE_REG.
+ */
+#define SPI_MEM_C_SMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_C_SMEM_PMS1_ECC_M  (SPI_MEM_C_SMEM_PMS1_ECC_V << SPI_MEM_C_SMEM_PMS1_ECC_S)
+#define SPI_MEM_C_SMEM_PMS1_ECC_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS1_ECC_S  2
+
+/** SPI_MEM_C_SMEM_PMS2_ATTR_REG register
+ *  SPI1 flash PMS section 2 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS2_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x138)
+/** SPI_MEM_C_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_SMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_SMEM_PMS2_RD_ATTR_M  (SPI_MEM_C_SMEM_PMS2_RD_ATTR_V << SPI_MEM_C_SMEM_PMS2_RD_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS2_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS2_RD_ATTR_S  0
+/** SPI_MEM_C_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_SMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_SMEM_PMS2_WR_ATTR_M  (SPI_MEM_C_SMEM_PMS2_WR_ATTR_V << SPI_MEM_C_SMEM_PMS2_WR_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS2_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS2_WR_ATTR_S  1
+/** SPI_MEM_C_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The
+ *  external RAM PMS section 2 is configured by registers SPI_MEM_C_SMEM_PMS2_ADDR_REG and
+ *  SPI_MEM_C_SMEM_PMS2_SIZE_REG.
+ */
+#define SPI_MEM_C_SMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_C_SMEM_PMS2_ECC_M  (SPI_MEM_C_SMEM_PMS2_ECC_V << SPI_MEM_C_SMEM_PMS2_ECC_S)
+#define SPI_MEM_C_SMEM_PMS2_ECC_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS2_ECC_S  2
+
+/** SPI_MEM_C_SMEM_PMS3_ATTR_REG register
+ *  SPI1 flash PMS section 3 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS3_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x13c)
+/** SPI_MEM_C_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_SMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_C_SMEM_PMS3_RD_ATTR_M  (SPI_MEM_C_SMEM_PMS3_RD_ATTR_V << SPI_MEM_C_SMEM_PMS3_RD_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS3_RD_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS3_RD_ATTR_S  0
+/** SPI_MEM_C_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_C_SMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_C_SMEM_PMS3_WR_ATTR_M  (SPI_MEM_C_SMEM_PMS3_WR_ATTR_V << SPI_MEM_C_SMEM_PMS3_WR_ATTR_S)
+#define SPI_MEM_C_SMEM_PMS3_WR_ATTR_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS3_WR_ATTR_S  1
+/** SPI_MEM_C_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The
+ *  external RAM PMS section 3 is configured by registers SPI_MEM_C_SMEM_PMS3_ADDR_REG and
+ *  SPI_MEM_C_SMEM_PMS3_SIZE_REG.
+ */
+#define SPI_MEM_C_SMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_C_SMEM_PMS3_ECC_M  (SPI_MEM_C_SMEM_PMS3_ECC_V << SPI_MEM_C_SMEM_PMS3_ECC_S)
+#define SPI_MEM_C_SMEM_PMS3_ECC_V  0x00000001U
+#define SPI_MEM_C_SMEM_PMS3_ECC_S  2
+
+/** SPI_MEM_C_SMEM_PMS0_ADDR_REG register
+ *  SPI1 external RAM PMS section 0 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS0_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x140)
+/** SPI_MEM_C_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+ *  SPI1 external RAM PMS section 0 start address value
+ */
+#define SPI_MEM_C_SMEM_PMS0_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS0_ADDR_S_M  (SPI_MEM_C_SMEM_PMS0_ADDR_S_V << SPI_MEM_C_SMEM_PMS0_ADDR_S_S)
+#define SPI_MEM_C_SMEM_PMS0_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS0_ADDR_S_S  0
+
+/** SPI_MEM_C_SMEM_PMS1_ADDR_REG register
+ *  SPI1 external RAM PMS section 1 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS1_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x144)
+/** SPI_MEM_C_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+ *  SPI1 external RAM PMS section 1 start address value
+ */
+#define SPI_MEM_C_SMEM_PMS1_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS1_ADDR_S_M  (SPI_MEM_C_SMEM_PMS1_ADDR_S_V << SPI_MEM_C_SMEM_PMS1_ADDR_S_S)
+#define SPI_MEM_C_SMEM_PMS1_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS1_ADDR_S_S  0
+
+/** SPI_MEM_C_SMEM_PMS2_ADDR_REG register
+ *  SPI1 external RAM PMS section 2 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS2_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x148)
+/** SPI_MEM_C_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+ *  SPI1 external RAM PMS section 2 start address value
+ */
+#define SPI_MEM_C_SMEM_PMS2_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS2_ADDR_S_M  (SPI_MEM_C_SMEM_PMS2_ADDR_S_V << SPI_MEM_C_SMEM_PMS2_ADDR_S_S)
+#define SPI_MEM_C_SMEM_PMS2_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS2_ADDR_S_S  0
+
+/** SPI_MEM_C_SMEM_PMS3_ADDR_REG register
+ *  SPI1 external RAM PMS section 3 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS3_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x14c)
+/** SPI_MEM_C_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+ *  SPI1 external RAM PMS section 3 start address value
+ */
+#define SPI_MEM_C_SMEM_PMS3_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS3_ADDR_S_M  (SPI_MEM_C_SMEM_PMS3_ADDR_S_V << SPI_MEM_C_SMEM_PMS3_ADDR_S_S)
+#define SPI_MEM_C_SMEM_PMS3_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_C_SMEM_PMS3_ADDR_S_S  0
+
+/** SPI_MEM_C_SMEM_PMS0_SIZE_REG register
+ *  SPI1 external RAM PMS section 0 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS0_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x150)
+/** SPI_MEM_C_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 0 address region is (SPI_MEM_C_SMEM_PMS0_ADDR_S,
+ *  SPI_MEM_C_SMEM_PMS0_ADDR_S + SPI_MEM_C_SMEM_PMS0_SIZE)
+ */
+#define SPI_MEM_C_SMEM_PMS0_SIZE    0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS0_SIZE_M  (SPI_MEM_C_SMEM_PMS0_SIZE_V << SPI_MEM_C_SMEM_PMS0_SIZE_S)
+#define SPI_MEM_C_SMEM_PMS0_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS0_SIZE_S  0
+
+/** SPI_MEM_C_SMEM_PMS1_SIZE_REG register
+ *  SPI1 external RAM PMS section 1 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS1_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x154)
+/** SPI_MEM_C_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 1 address region is (SPI_MEM_C_SMEM_PMS1_ADDR_S,
+ *  SPI_MEM_C_SMEM_PMS1_ADDR_S + SPI_MEM_C_SMEM_PMS1_SIZE)
+ */
+#define SPI_MEM_C_SMEM_PMS1_SIZE    0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS1_SIZE_M  (SPI_MEM_C_SMEM_PMS1_SIZE_V << SPI_MEM_C_SMEM_PMS1_SIZE_S)
+#define SPI_MEM_C_SMEM_PMS1_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS1_SIZE_S  0
+
+/** SPI_MEM_C_SMEM_PMS2_SIZE_REG register
+ *  SPI1 external RAM PMS section 2 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS2_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x158)
+/** SPI_MEM_C_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 2 address region is (SPI_MEM_C_SMEM_PMS2_ADDR_S,
+ *  SPI_MEM_C_SMEM_PMS2_ADDR_S + SPI_MEM_C_SMEM_PMS2_SIZE)
+ */
+#define SPI_MEM_C_SMEM_PMS2_SIZE    0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS2_SIZE_M  (SPI_MEM_C_SMEM_PMS2_SIZE_V << SPI_MEM_C_SMEM_PMS2_SIZE_S)
+#define SPI_MEM_C_SMEM_PMS2_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS2_SIZE_S  0
+
+/** SPI_MEM_C_SMEM_PMS3_SIZE_REG register
+ *  SPI1 external RAM PMS section 3 start address register
+ */
+#define SPI_MEM_C_SMEM_PMS3_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x15c)
+/** SPI_MEM_C_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section 3 address region is (SPI_MEM_C_SMEM_PMS3_ADDR_S,
+ *  SPI_MEM_C_SMEM_PMS3_ADDR_S + SPI_MEM_C_SMEM_PMS3_SIZE)
+ */
+#define SPI_MEM_C_SMEM_PMS3_SIZE    0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS3_SIZE_M  (SPI_MEM_C_SMEM_PMS3_SIZE_V << SPI_MEM_C_SMEM_PMS3_SIZE_S)
+#define SPI_MEM_C_SMEM_PMS3_SIZE_V  0x00007FFFU
+#define SPI_MEM_C_SMEM_PMS3_SIZE_S  0
+
+/** SPI_MEM_C_PMS_REJECT_REG register
+ *  SPI1 access reject register
+ */
+#define SPI_MEM_C_PMS_REJECT_REG (DR_REG_FLASH_SPI0_BASE + 0x164)
+/** SPI_MEM_C_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
+ *  This bits show the first SPI1 access error address. It is cleared by when
+ *  SPI_MEM_C_PMS_REJECT_INT_CLR bit is set.
+ */
+#define SPI_MEM_C_REJECT_ADDR    0x07FFFFFFU
+#define SPI_MEM_C_REJECT_ADDR_M  (SPI_MEM_C_REJECT_ADDR_V << SPI_MEM_C_REJECT_ADDR_S)
+#define SPI_MEM_C_REJECT_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_C_REJECT_ADDR_S  0
+/** SPI_MEM_C_PM_EN : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to enable SPI0/1 transfer permission control function.
+ */
+#define SPI_MEM_C_PM_EN    (BIT(27))
+#define SPI_MEM_C_PM_EN_M  (SPI_MEM_C_PM_EN_V << SPI_MEM_C_PM_EN_S)
+#define SPI_MEM_C_PM_EN_V  0x00000001U
+#define SPI_MEM_C_PM_EN_S  27
+/** SPI_MEM_C_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0;
+ *  1: SPI1 write access error. 0: No write access error. It is cleared by when
+ *  SPI_MEM_C_PMS_REJECT_INT_CLR bit is set.
+ */
+#define SPI_MEM_C_PMS_LD    (BIT(28))
+#define SPI_MEM_C_PMS_LD_M  (SPI_MEM_C_PMS_LD_V << SPI_MEM_C_PMS_LD_S)
+#define SPI_MEM_C_PMS_LD_V  0x00000001U
+#define SPI_MEM_C_PMS_LD_S  28
+/** SPI_MEM_C_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0;
+ *  1: SPI1 read access error. 0: No read access error. It is cleared by when
+ *  SPI_MEM_C_PMS_REJECT_INT_CLR bit is set.
+ */
+#define SPI_MEM_C_PMS_ST    (BIT(29))
+#define SPI_MEM_C_PMS_ST_M  (SPI_MEM_C_PMS_ST_V << SPI_MEM_C_PMS_ST_S)
+#define SPI_MEM_C_PMS_ST_V  0x00000001U
+#define SPI_MEM_C_PMS_ST_S  29
+/** SPI_MEM_C_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0;
+ *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
+ *  cleared by when  SPI_MEM_C_PMS_REJECT_INT_CLR bit is set.
+ */
+#define SPI_MEM_C_PMS_MULTI_HIT    (BIT(30))
+#define SPI_MEM_C_PMS_MULTI_HIT_M  (SPI_MEM_C_PMS_MULTI_HIT_V << SPI_MEM_C_PMS_MULTI_HIT_S)
+#define SPI_MEM_C_PMS_MULTI_HIT_V  0x00000001U
+#define SPI_MEM_C_PMS_MULTI_HIT_S  30
+/** SPI_MEM_C_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0;
+ *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
+ *  error. It is cleared by when  SPI_MEM_C_PMS_REJECT_INT_CLR bit is set.
+ */
+#define SPI_MEM_C_PMS_IVD    (BIT(31))
+#define SPI_MEM_C_PMS_IVD_M  (SPI_MEM_C_PMS_IVD_V << SPI_MEM_C_PMS_IVD_S)
+#define SPI_MEM_C_PMS_IVD_V  0x00000001U
+#define SPI_MEM_C_PMS_IVD_S  31
+
+/** SPI_MEM_C_ECC_CTRL_REG register
+ *  MSPI ECC control register
+ */
+#define SPI_MEM_C_ECC_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x168)
+/** SPI_MEM_C_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0;
+ *  This bits show the error times of MSPI ECC read. It is cleared by when
+ *  SPI_MEM_C_ECC_ERR_INT_CLR bit is set.
+ */
+#define SPI_MEM_C_ECC_ERR_CNT    0x0000003FU
+#define SPI_MEM_C_ECC_ERR_CNT_M  (SPI_MEM_C_ECC_ERR_CNT_V << SPI_MEM_C_ECC_ERR_CNT_S)
+#define SPI_MEM_C_ECC_ERR_CNT_V  0x0000003FU
+#define SPI_MEM_C_ECC_ERR_CNT_S  5
+/** SPI_MEM_C_FMEM__ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10;
+ *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_C_ECC_ERR_INT interrupt.
+ */
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM    0x0000003FU
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_M  (SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_V << SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_S)
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_V  0x0000003FU
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_S  11
+/** SPI_MEM_C_FMEM__ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0;
+ *  Set this bit to calculate the error times of MSPI ECC read when accesses to flash.
+ */
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN_M  (SPI_MEM_C_FMEM__ECC_ERR_INT_EN_V << SPI_MEM_C_FMEM__ECC_ERR_INT_EN_S)
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN_S  17
+/** SPI_MEM_C_FMEM__PAGE_SIZE : R/W; bitpos: [19:18]; default: 0;
+ *  Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
+ *  1024 bytes. 3: 2048 bytes.
+ */
+#define SPI_MEM_C_FMEM__PAGE_SIZE    0x00000003U
+#define SPI_MEM_C_FMEM__PAGE_SIZE_M  (SPI_MEM_C_FMEM__PAGE_SIZE_V << SPI_MEM_C_FMEM__PAGE_SIZE_S)
+#define SPI_MEM_C_FMEM__PAGE_SIZE_V  0x00000003U
+#define SPI_MEM_C_FMEM__PAGE_SIZE_S  18
+/** SPI_MEM_C_FMEM__ECC_ADDR_EN : HRO; bitpos: [20]; default: 0;
+ *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
+ *  ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit
+ *  should be 0. Otherwise, this bit should be 1.
+ */
+#define SPI_MEM_C_FMEM__ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_C_FMEM__ECC_ADDR_EN_M  (SPI_MEM_C_FMEM__ECC_ADDR_EN_V << SPI_MEM_C_FMEM__ECC_ADDR_EN_S)
+#define SPI_MEM_C_FMEM__ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_C_FMEM__ECC_ADDR_EN_S  20
+/** SPI_MEM_C_USR_ECC_ADDR_EN : HRO; bitpos: [21]; default: 0;
+ *  Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.
+ */
+#define SPI_MEM_C_USR_ECC_ADDR_EN    (BIT(21))
+#define SPI_MEM_C_USR_ECC_ADDR_EN_M  (SPI_MEM_C_USR_ECC_ADDR_EN_V << SPI_MEM_C_USR_ECC_ADDR_EN_S)
+#define SPI_MEM_C_USR_ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_C_USR_ECC_ADDR_EN_S  21
+/** SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN : HRO; bitpos: [24]; default: 1;
+ *  1: The error information in SPI_MEM_C_ECC_ERR_BITS and SPI_MEM_C_ECC_ERR_ADDR is
+ *  updated when there is an ECC error. 0: SPI_MEM_C_ECC_ERR_BITS and
+ *  SPI_MEM_C_ECC_ERR_ADDR record the first ECC error information.
+ */
+#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
+#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_M  (SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_S)
+#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_V  0x00000001U
+#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_S  24
+/** SPI_MEM_C_ECC_ERR_BITS : HRO; bitpos: [31:25]; default: 0;
+ *  Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to
+ *  byte 0 bit 0 to byte 15 bit 7)
+ */
+#define SPI_MEM_C_ECC_ERR_BITS    0x0000007FU
+#define SPI_MEM_C_ECC_ERR_BITS_M  (SPI_MEM_C_ECC_ERR_BITS_V << SPI_MEM_C_ECC_ERR_BITS_S)
+#define SPI_MEM_C_ECC_ERR_BITS_V  0x0000007FU
+#define SPI_MEM_C_ECC_ERR_BITS_S  25
+
+/** SPI_MEM_C_ECC_ERR_ADDR_REG register
+ *  MSPI ECC error address register
+ */
+#define SPI_MEM_C_ECC_ERR_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x16c)
+/** SPI_MEM_C_ECC_ERR_ADDR : HRO; bitpos: [26:0]; default: 0;
+ *  This bits show the first MSPI ECC error address. It is cleared by when
+ *  SPI_MEM_C_ECC_ERR_INT_CLR bit is set.
+ */
+#define SPI_MEM_C_ECC_ERR_ADDR    0x07FFFFFFU
+#define SPI_MEM_C_ECC_ERR_ADDR_M  (SPI_MEM_C_ECC_ERR_ADDR_V << SPI_MEM_C_ECC_ERR_ADDR_S)
+#define SPI_MEM_C_ECC_ERR_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_C_ECC_ERR_ADDR_S  0
+
+/** SPI_MEM_C_AXI_ERR_ADDR_REG register
+ *  SPI0 AXI request error address.
+ */
+#define SPI_MEM_C_AXI_ERR_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x170)
+/** SPI_MEM_C_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
+ *  This bits show the first AXI write/read invalid error or AXI write flash error
+ *  address. It is cleared by when SPI_MEM_C_AXI_WADDR_ERR_INT_CLR,
+ *  SPI_MEM_C_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_C_AXI_RADDR_ERR_IN_CLR bit is set.
+ */
+#define SPI_MEM_C_AXI_ERR_ADDR    0x07FFFFFFU
+#define SPI_MEM_C_AXI_ERR_ADDR_M  (SPI_MEM_C_AXI_ERR_ADDR_V << SPI_MEM_C_AXI_ERR_ADDR_S)
+#define SPI_MEM_C_AXI_ERR_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_C_AXI_ERR_ADDR_S  0
+
+/** SPI_MEM_C_SMEM_ECC_CTRL_REG register
+ *  MSPI ECC control register
+ */
+#define SPI_MEM_C_SMEM_ECC_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x174)
+/** SPI_MEM_C_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0;
+ *  Set this bit to calculate the error times of MSPI ECC read when accesses to
+ *  external RAM.
+ */
+#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN_M  (SPI_MEM_C_SMEM_ECC_ERR_INT_EN_V << SPI_MEM_C_SMEM_ECC_ERR_INT_EN_S)
+#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN_S  17
+/** SPI_MEM_C_SMEM_PAGE_SIZE : HRO; bitpos: [19:18]; default: 2;
+ *  Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes.
+ *  2: 1024 bytes. 3: 2048 bytes.
+ */
+#define SPI_MEM_C_SMEM_PAGE_SIZE    0x00000003U
+#define SPI_MEM_C_SMEM_PAGE_SIZE_M  (SPI_MEM_C_SMEM_PAGE_SIZE_V << SPI_MEM_C_SMEM_PAGE_SIZE_S)
+#define SPI_MEM_C_SMEM_PAGE_SIZE_V  0x00000003U
+#define SPI_MEM_C_SMEM_PAGE_SIZE_S  18
+/** SPI_MEM_C_SMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0;
+ *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
+ *  ECC region or non-ECC region of external RAM. If there is no ECC region in external
+ *  RAM, this bit should be 0. Otherwise, this bit should be 1.
+ */
+#define SPI_MEM_C_SMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_C_SMEM_ECC_ADDR_EN_M  (SPI_MEM_C_SMEM_ECC_ADDR_EN_V << SPI_MEM_C_SMEM_ECC_ADDR_EN_S)
+#define SPI_MEM_C_SMEM_ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_ECC_ADDR_EN_S  20
+
+/** SPI_MEM_C_SMEM_AXI_ADDR_CTRL_REG register
+ *  SPI0 AXI address control register
+ */
+#define SPI_MEM_C_SMEM_AXI_ADDR_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x178)
+/** SPI_MEM_C_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1;
+ *  The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
+ *  and SPI0 transfers are done. 0: Others.
+ */
+#define SPI_MEM_C_ALL_FIFO_EMPTY    (BIT(26))
+#define SPI_MEM_C_ALL_FIFO_EMPTY_M  (SPI_MEM_C_ALL_FIFO_EMPTY_V << SPI_MEM_C_ALL_FIFO_EMPTY_S)
+#define SPI_MEM_C_ALL_FIFO_EMPTY_V  0x00000001U
+#define SPI_MEM_C_ALL_FIFO_EMPTY_S  26
+/** SPI_MEM_C_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1;
+ *  1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.
+ */
+#define SPI_MEM_C_RDATA_AFIFO_REMPTY    (BIT(27))
+#define SPI_MEM_C_RDATA_AFIFO_REMPTY_M  (SPI_MEM_C_RDATA_AFIFO_REMPTY_V << SPI_MEM_C_RDATA_AFIFO_REMPTY_S)
+#define SPI_MEM_C_RDATA_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_C_RDATA_AFIFO_REMPTY_S  27
+/** SPI_MEM_C_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1;
+ *  1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.
+ */
+#define SPI_MEM_C_RADDR_AFIFO_REMPTY    (BIT(28))
+#define SPI_MEM_C_RADDR_AFIFO_REMPTY_M  (SPI_MEM_C_RADDR_AFIFO_REMPTY_V << SPI_MEM_C_RADDR_AFIFO_REMPTY_S)
+#define SPI_MEM_C_RADDR_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_C_RADDR_AFIFO_REMPTY_S  28
+/** SPI_MEM_C_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1;
+ *  1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.
+ */
+#define SPI_MEM_C_WDATA_AFIFO_REMPTY    (BIT(29))
+#define SPI_MEM_C_WDATA_AFIFO_REMPTY_M  (SPI_MEM_C_WDATA_AFIFO_REMPTY_V << SPI_MEM_C_WDATA_AFIFO_REMPTY_S)
+#define SPI_MEM_C_WDATA_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_C_WDATA_AFIFO_REMPTY_S  29
+/** SPI_MEM_C_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1;
+ *  1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.
+ */
+#define SPI_MEM_C_WBLEN_AFIFO_REMPTY    (BIT(30))
+#define SPI_MEM_C_WBLEN_AFIFO_REMPTY_M  (SPI_MEM_C_WBLEN_AFIFO_REMPTY_V << SPI_MEM_C_WBLEN_AFIFO_REMPTY_S)
+#define SPI_MEM_C_WBLEN_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_C_WBLEN_AFIFO_REMPTY_S  30
+/** SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1;
+ *  This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and
+ *  RDATA_AFIFO are empty and spi0_mst_st is IDLE.
+ */
+#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
+#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_M  (SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_S)
+#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x00000001U
+#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
+
+/** SPI_MEM_C_AXI_ERR_RESP_EN_REG register
+ *  SPI0 AXI error response enable register
+ */
+#define SPI_MEM_C_AXI_ERR_RESP_EN_REG (DR_REG_FLASH_SPI0_BASE + 0x17c)
+/** SPI_MEM_C_AW_RESP_EN_MMU_VLD : HRO; bitpos: [0]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu valid err in axi write trans.
+ */
+#define SPI_MEM_C_AW_RESP_EN_MMU_VLD    (BIT(0))
+#define SPI_MEM_C_AW_RESP_EN_MMU_VLD_M  (SPI_MEM_C_AW_RESP_EN_MMU_VLD_V << SPI_MEM_C_AW_RESP_EN_MMU_VLD_S)
+#define SPI_MEM_C_AW_RESP_EN_MMU_VLD_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_MMU_VLD_S  0
+/** SPI_MEM_C_AW_RESP_EN_MMU_GID : HRO; bitpos: [1]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu gid err in axi write trans.
+ */
+#define SPI_MEM_C_AW_RESP_EN_MMU_GID    (BIT(1))
+#define SPI_MEM_C_AW_RESP_EN_MMU_GID_M  (SPI_MEM_C_AW_RESP_EN_MMU_GID_V << SPI_MEM_C_AW_RESP_EN_MMU_GID_S)
+#define SPI_MEM_C_AW_RESP_EN_MMU_GID_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_MMU_GID_S  1
+/** SPI_MEM_C_AW_RESP_EN_AXI_SIZE : HRO; bitpos: [2]; default: 0;
+ *  Set this bit  to enable AXI response function for axi size err in axi write trans.
+ */
+#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE    (BIT(2))
+#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE_M  (SPI_MEM_C_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_C_AW_RESP_EN_AXI_SIZE_S)
+#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE_S  2
+/** SPI_MEM_C_AW_RESP_EN_AXI_FLASH : HRO; bitpos: [3]; default: 0;
+ *  Set this bit  to enable AXI response function for axi flash err in axi write trans.
+ */
+#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH    (BIT(3))
+#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH_M  (SPI_MEM_C_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_C_AW_RESP_EN_AXI_FLASH_S)
+#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH_S  3
+/** SPI_MEM_C_AW_RESP_EN_MMU_ECC : HRO; bitpos: [4]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu ecc err in axi write trans.
+ */
+#define SPI_MEM_C_AW_RESP_EN_MMU_ECC    (BIT(4))
+#define SPI_MEM_C_AW_RESP_EN_MMU_ECC_M  (SPI_MEM_C_AW_RESP_EN_MMU_ECC_V << SPI_MEM_C_AW_RESP_EN_MMU_ECC_S)
+#define SPI_MEM_C_AW_RESP_EN_MMU_ECC_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_MMU_ECC_S  4
+/** SPI_MEM_C_AW_RESP_EN_MMU_SENS : HRO; bitpos: [5]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu sens in err axi write trans.
+ */
+#define SPI_MEM_C_AW_RESP_EN_MMU_SENS    (BIT(5))
+#define SPI_MEM_C_AW_RESP_EN_MMU_SENS_M  (SPI_MEM_C_AW_RESP_EN_MMU_SENS_V << SPI_MEM_C_AW_RESP_EN_MMU_SENS_S)
+#define SPI_MEM_C_AW_RESP_EN_MMU_SENS_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_MMU_SENS_S  5
+/** SPI_MEM_C_AW_RESP_EN_AXI_WSTRB : HRO; bitpos: [6]; default: 0;
+ *  Set this bit  to enable AXI response function for axi wstrb err in axi write trans.
+ */
+#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB    (BIT(6))
+#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_M  (SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_S)
+#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_V  0x00000001U
+#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_S  6
+/** SPI_MEM_C_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu valid err in axi read trans.
+ */
+#define SPI_MEM_C_AR_RESP_EN_MMU_VLD    (BIT(7))
+#define SPI_MEM_C_AR_RESP_EN_MMU_VLD_M  (SPI_MEM_C_AR_RESP_EN_MMU_VLD_V << SPI_MEM_C_AR_RESP_EN_MMU_VLD_S)
+#define SPI_MEM_C_AR_RESP_EN_MMU_VLD_V  0x00000001U
+#define SPI_MEM_C_AR_RESP_EN_MMU_VLD_S  7
+/** SPI_MEM_C_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu gid err in axi read trans.
+ */
+#define SPI_MEM_C_AR_RESP_EN_MMU_GID    (BIT(8))
+#define SPI_MEM_C_AR_RESP_EN_MMU_GID_M  (SPI_MEM_C_AR_RESP_EN_MMU_GID_V << SPI_MEM_C_AR_RESP_EN_MMU_GID_S)
+#define SPI_MEM_C_AR_RESP_EN_MMU_GID_V  0x00000001U
+#define SPI_MEM_C_AR_RESP_EN_MMU_GID_S  8
+/** SPI_MEM_C_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu ecc err in axi read trans.
+ */
+#define SPI_MEM_C_AR_RESP_EN_MMU_ECC    (BIT(9))
+#define SPI_MEM_C_AR_RESP_EN_MMU_ECC_M  (SPI_MEM_C_AR_RESP_EN_MMU_ECC_V << SPI_MEM_C_AR_RESP_EN_MMU_ECC_S)
+#define SPI_MEM_C_AR_RESP_EN_MMU_ECC_V  0x00000001U
+#define SPI_MEM_C_AR_RESP_EN_MMU_ECC_S  9
+/** SPI_MEM_C_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu sensitive err in axi read
+ *  trans.
+ */
+#define SPI_MEM_C_AR_RESP_EN_MMU_SENS    (BIT(10))
+#define SPI_MEM_C_AR_RESP_EN_MMU_SENS_M  (SPI_MEM_C_AR_RESP_EN_MMU_SENS_V << SPI_MEM_C_AR_RESP_EN_MMU_SENS_S)
+#define SPI_MEM_C_AR_RESP_EN_MMU_SENS_V  0x00000001U
+#define SPI_MEM_C_AR_RESP_EN_MMU_SENS_S  10
+/** SPI_MEM_C_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0;
+ *  Set this bit  to enable AXI response function for axi size err in axi read trans.
+ */
+#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE    (BIT(11))
+#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE_M  (SPI_MEM_C_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_C_AR_RESP_EN_AXI_SIZE_S)
+#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE_V  0x00000001U
+#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE_S  11
+
+/** SPI_MEM_C_TIMING_CALI_REG register
+ *  SPI0 flash timing calibration register
+ */
+#define SPI_MEM_C_TIMING_CALI_REG (DR_REG_FLASH_SPI0_BASE + 0x180)
+/** SPI_MEM_C_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable timing adjust clock for all reading operations.
+ */
+#define SPI_MEM_C_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_C_TIMING_CLK_ENA_M  (SPI_MEM_C_TIMING_CLK_ENA_V << SPI_MEM_C_TIMING_CLK_ENA_S)
+#define SPI_MEM_C_TIMING_CLK_ENA_V  0x00000001U
+#define SPI_MEM_C_TIMING_CLK_ENA_S  0
+/** SPI_MEM_C_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable timing auto-calibration for all reading operations.
+ */
+#define SPI_MEM_C_TIMING_CALI    (BIT(1))
+#define SPI_MEM_C_TIMING_CALI_M  (SPI_MEM_C_TIMING_CALI_V << SPI_MEM_C_TIMING_CALI_S)
+#define SPI_MEM_C_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_C_TIMING_CALI_S  1
+/** SPI_MEM_C_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+ *  add extra dummy spi clock cycle length for spi clock calibration.
+ */
+#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_S  2
+/** SPI_MEM_C_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0;
+ *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
+ *  flash.
+ */
+#define SPI_MEM_C_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_C_DLL_TIMING_CALI_M  (SPI_MEM_C_DLL_TIMING_CALI_V << SPI_MEM_C_DLL_TIMING_CALI_S)
+#define SPI_MEM_C_DLL_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_C_DLL_TIMING_CALI_S  5
+/** SPI_MEM_C_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0;
+ *  Set this bit to update delay mode, delay num and extra dummy in MSPI.
+ */
+#define SPI_MEM_C_TIMING_CALI_UPDATE    (BIT(6))
+#define SPI_MEM_C_TIMING_CALI_UPDATE_M  (SPI_MEM_C_TIMING_CALI_UPDATE_V << SPI_MEM_C_TIMING_CALI_UPDATE_S)
+#define SPI_MEM_C_TIMING_CALI_UPDATE_V  0x00000001U
+#define SPI_MEM_C_TIMING_CALI_UPDATE_S  6
+
+/** SPI_MEM_C_DIN_MODE_REG register
+ *  MSPI flash input timing delay mode control register
+ */
+#define SPI_MEM_C_DIN_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x184)
+/** SPI_MEM_C_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_DIN0_MODE    0x00000007U
+#define SPI_MEM_C_DIN0_MODE_M  (SPI_MEM_C_DIN0_MODE_V << SPI_MEM_C_DIN0_MODE_S)
+#define SPI_MEM_C_DIN0_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN0_MODE_S  0
+/** SPI_MEM_C_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_DIN1_MODE    0x00000007U
+#define SPI_MEM_C_DIN1_MODE_M  (SPI_MEM_C_DIN1_MODE_V << SPI_MEM_C_DIN1_MODE_S)
+#define SPI_MEM_C_DIN1_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN1_MODE_S  3
+/** SPI_MEM_C_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_DIN2_MODE    0x00000007U
+#define SPI_MEM_C_DIN2_MODE_M  (SPI_MEM_C_DIN2_MODE_V << SPI_MEM_C_DIN2_MODE_S)
+#define SPI_MEM_C_DIN2_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN2_MODE_S  6
+/** SPI_MEM_C_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_DIN3_MODE    0x00000007U
+#define SPI_MEM_C_DIN3_MODE_M  (SPI_MEM_C_DIN3_MODE_V << SPI_MEM_C_DIN3_MODE_S)
+#define SPI_MEM_C_DIN3_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN3_MODE_S  9
+/** SPI_MEM_C_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk
+ */
+#define SPI_MEM_C_DIN4_MODE    0x00000007U
+#define SPI_MEM_C_DIN4_MODE_M  (SPI_MEM_C_DIN4_MODE_V << SPI_MEM_C_DIN4_MODE_S)
+#define SPI_MEM_C_DIN4_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN4_MODE_S  12
+/** SPI_MEM_C_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk
+ */
+#define SPI_MEM_C_DIN5_MODE    0x00000007U
+#define SPI_MEM_C_DIN5_MODE_M  (SPI_MEM_C_DIN5_MODE_V << SPI_MEM_C_DIN5_MODE_S)
+#define SPI_MEM_C_DIN5_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN5_MODE_S  15
+/** SPI_MEM_C_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk
+ */
+#define SPI_MEM_C_DIN6_MODE    0x00000007U
+#define SPI_MEM_C_DIN6_MODE_M  (SPI_MEM_C_DIN6_MODE_V << SPI_MEM_C_DIN6_MODE_S)
+#define SPI_MEM_C_DIN6_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN6_MODE_S  18
+/** SPI_MEM_C_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk
+ */
+#define SPI_MEM_C_DIN7_MODE    0x00000007U
+#define SPI_MEM_C_DIN7_MODE_M  (SPI_MEM_C_DIN7_MODE_V << SPI_MEM_C_DIN7_MODE_S)
+#define SPI_MEM_C_DIN7_MODE_V  0x00000007U
+#define SPI_MEM_C_DIN7_MODE_S  21
+/** SPI_MEM_C_DINS_MODE : R/W; bitpos: [26:24]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk
+ */
+#define SPI_MEM_C_DINS_MODE    0x00000007U
+#define SPI_MEM_C_DINS_MODE_M  (SPI_MEM_C_DINS_MODE_V << SPI_MEM_C_DINS_MODE_S)
+#define SPI_MEM_C_DINS_MODE_V  0x00000007U
+#define SPI_MEM_C_DINS_MODE_S  24
+
+/** SPI_MEM_C_DIN_NUM_REG register
+ *  MSPI flash input timing delay number control register
+ */
+#define SPI_MEM_C_DIN_NUM_REG (DR_REG_FLASH_SPI0_BASE + 0x188)
+/** SPI_MEM_C_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_DIN0_NUM    0x00000003U
+#define SPI_MEM_C_DIN0_NUM_M  (SPI_MEM_C_DIN0_NUM_V << SPI_MEM_C_DIN0_NUM_S)
+#define SPI_MEM_C_DIN0_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN0_NUM_S  0
+/** SPI_MEM_C_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_DIN1_NUM    0x00000003U
+#define SPI_MEM_C_DIN1_NUM_M  (SPI_MEM_C_DIN1_NUM_V << SPI_MEM_C_DIN1_NUM_S)
+#define SPI_MEM_C_DIN1_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN1_NUM_S  2
+/** SPI_MEM_C_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_DIN2_NUM    0x00000003U
+#define SPI_MEM_C_DIN2_NUM_M  (SPI_MEM_C_DIN2_NUM_V << SPI_MEM_C_DIN2_NUM_S)
+#define SPI_MEM_C_DIN2_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN2_NUM_S  4
+/** SPI_MEM_C_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_DIN3_NUM    0x00000003U
+#define SPI_MEM_C_DIN3_NUM_M  (SPI_MEM_C_DIN3_NUM_V << SPI_MEM_C_DIN3_NUM_S)
+#define SPI_MEM_C_DIN3_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN3_NUM_S  6
+/** SPI_MEM_C_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_DIN4_NUM    0x00000003U
+#define SPI_MEM_C_DIN4_NUM_M  (SPI_MEM_C_DIN4_NUM_V << SPI_MEM_C_DIN4_NUM_S)
+#define SPI_MEM_C_DIN4_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN4_NUM_S  8
+/** SPI_MEM_C_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_DIN5_NUM    0x00000003U
+#define SPI_MEM_C_DIN5_NUM_M  (SPI_MEM_C_DIN5_NUM_V << SPI_MEM_C_DIN5_NUM_S)
+#define SPI_MEM_C_DIN5_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN5_NUM_S  10
+/** SPI_MEM_C_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_DIN6_NUM    0x00000003U
+#define SPI_MEM_C_DIN6_NUM_M  (SPI_MEM_C_DIN6_NUM_V << SPI_MEM_C_DIN6_NUM_S)
+#define SPI_MEM_C_DIN6_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN6_NUM_S  12
+/** SPI_MEM_C_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_DIN7_NUM    0x00000003U
+#define SPI_MEM_C_DIN7_NUM_M  (SPI_MEM_C_DIN7_NUM_V << SPI_MEM_C_DIN7_NUM_S)
+#define SPI_MEM_C_DIN7_NUM_V  0x00000003U
+#define SPI_MEM_C_DIN7_NUM_S  14
+/** SPI_MEM_C_DINS_NUM : R/W; bitpos: [17:16]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_DINS_NUM    0x00000003U
+#define SPI_MEM_C_DINS_NUM_M  (SPI_MEM_C_DINS_NUM_V << SPI_MEM_C_DINS_NUM_S)
+#define SPI_MEM_C_DINS_NUM_V  0x00000003U
+#define SPI_MEM_C_DINS_NUM_S  16
+
+/** SPI_MEM_C_DOUT_MODE_REG register
+ *  MSPI flash output timing adjustment control register
+ */
+#define SPI_MEM_C_DOUT_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x18c)
+/** SPI_MEM_C_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_C_DOUT0_MODE_M  (SPI_MEM_C_DOUT0_MODE_V << SPI_MEM_C_DOUT0_MODE_S)
+#define SPI_MEM_C_DOUT0_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT0_MODE_S  0
+/** SPI_MEM_C_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_C_DOUT1_MODE_M  (SPI_MEM_C_DOUT1_MODE_V << SPI_MEM_C_DOUT1_MODE_S)
+#define SPI_MEM_C_DOUT1_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT1_MODE_S  1
+/** SPI_MEM_C_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_C_DOUT2_MODE_M  (SPI_MEM_C_DOUT2_MODE_V << SPI_MEM_C_DOUT2_MODE_S)
+#define SPI_MEM_C_DOUT2_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT2_MODE_S  2
+/** SPI_MEM_C_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_C_DOUT3_MODE_M  (SPI_MEM_C_DOUT3_MODE_V << SPI_MEM_C_DOUT3_MODE_S)
+#define SPI_MEM_C_DOUT3_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT3_MODE_S  3
+/** SPI_MEM_C_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the spi_clk
+ */
+#define SPI_MEM_C_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_C_DOUT4_MODE_M  (SPI_MEM_C_DOUT4_MODE_V << SPI_MEM_C_DOUT4_MODE_S)
+#define SPI_MEM_C_DOUT4_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT4_MODE_S  4
+/** SPI_MEM_C_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the spi_clk
+ */
+#define SPI_MEM_C_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_C_DOUT5_MODE_M  (SPI_MEM_C_DOUT5_MODE_V << SPI_MEM_C_DOUT5_MODE_S)
+#define SPI_MEM_C_DOUT5_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT5_MODE_S  5
+/** SPI_MEM_C_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the spi_clk
+ */
+#define SPI_MEM_C_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_C_DOUT6_MODE_M  (SPI_MEM_C_DOUT6_MODE_V << SPI_MEM_C_DOUT6_MODE_S)
+#define SPI_MEM_C_DOUT6_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT6_MODE_S  6
+/** SPI_MEM_C_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the spi_clk
+ */
+#define SPI_MEM_C_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_C_DOUT7_MODE_M  (SPI_MEM_C_DOUT7_MODE_V << SPI_MEM_C_DOUT7_MODE_S)
+#define SPI_MEM_C_DOUT7_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUT7_MODE_S  7
+/** SPI_MEM_C_DOUTS_MODE : R/W; bitpos: [8]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the spi_clk
+ */
+#define SPI_MEM_C_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_C_DOUTS_MODE_M  (SPI_MEM_C_DOUTS_MODE_V << SPI_MEM_C_DOUTS_MODE_S)
+#define SPI_MEM_C_DOUTS_MODE_V  0x00000001U
+#define SPI_MEM_C_DOUTS_MODE_S  8
+
+/** SPI_MEM_C_SMEM_TIMING_CALI_REG register
+ *  MSPI external RAM timing calibration register
+ */
+#define SPI_MEM_C_SMEM_TIMING_CALI_REG (DR_REG_FLASH_SPI0_BASE + 0x190)
+/** SPI_MEM_C_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1;
+ *  For sram, the bit is used to enable timing adjust clock for all reading operations.
+ */
+#define SPI_MEM_C_SMEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_C_SMEM_TIMING_CLK_ENA_M  (SPI_MEM_C_SMEM_TIMING_CLK_ENA_V << SPI_MEM_C_SMEM_TIMING_CLK_ENA_S)
+#define SPI_MEM_C_SMEM_TIMING_CLK_ENA_V  0x00000001U
+#define SPI_MEM_C_SMEM_TIMING_CLK_ENA_S  0
+/** SPI_MEM_C_SMEM_TIMING_CALI : HRO; bitpos: [1]; default: 0;
+ *  For sram, the bit is used to enable timing auto-calibration for all reading
+ *  operations.
+ */
+#define SPI_MEM_C_SMEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_C_SMEM_TIMING_CALI_M  (SPI_MEM_C_SMEM_TIMING_CALI_V << SPI_MEM_C_SMEM_TIMING_CALI_S)
+#define SPI_MEM_C_SMEM_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_C_SMEM_TIMING_CALI_S  1
+/** SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN : HRO; bitpos: [4:2]; default: 0;
+ *  For sram, add extra dummy spi clock cycle length for spi clock calibration.
+ */
+#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
+/** SPI_MEM_C_SMEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0;
+ *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
+ *  EXT_RAM.
+ */
+#define SPI_MEM_C_SMEM_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_C_SMEM_DLL_TIMING_CALI_M  (SPI_MEM_C_SMEM_DLL_TIMING_CALI_V << SPI_MEM_C_SMEM_DLL_TIMING_CALI_S)
+#define SPI_MEM_C_SMEM_DLL_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_C_SMEM_DLL_TIMING_CALI_S  5
+
+/** SPI_MEM_C_SMEM_DIN_MODE_REG register
+ *  MSPI external RAM input timing delay mode control register
+ */
+#define SPI_MEM_C_SMEM_DIN_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x194)
+/** SPI_MEM_C_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DIN0_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN0_MODE_M  (SPI_MEM_C_SMEM_DIN0_MODE_V << SPI_MEM_C_SMEM_DIN0_MODE_S)
+#define SPI_MEM_C_SMEM_DIN0_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN0_MODE_S  0
+/** SPI_MEM_C_SMEM_DIN1_MODE : HRO; bitpos: [5:3]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DIN1_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN1_MODE_M  (SPI_MEM_C_SMEM_DIN1_MODE_V << SPI_MEM_C_SMEM_DIN1_MODE_S)
+#define SPI_MEM_C_SMEM_DIN1_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN1_MODE_S  3
+/** SPI_MEM_C_SMEM_DIN2_MODE : HRO; bitpos: [8:6]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DIN2_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN2_MODE_M  (SPI_MEM_C_SMEM_DIN2_MODE_V << SPI_MEM_C_SMEM_DIN2_MODE_S)
+#define SPI_MEM_C_SMEM_DIN2_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN2_MODE_S  6
+/** SPI_MEM_C_SMEM_DIN3_MODE : HRO; bitpos: [11:9]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DIN3_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN3_MODE_M  (SPI_MEM_C_SMEM_DIN3_MODE_V << SPI_MEM_C_SMEM_DIN3_MODE_S)
+#define SPI_MEM_C_SMEM_DIN3_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN3_MODE_S  9
+/** SPI_MEM_C_SMEM_DIN4_MODE : HRO; bitpos: [14:12]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DIN4_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN4_MODE_M  (SPI_MEM_C_SMEM_DIN4_MODE_V << SPI_MEM_C_SMEM_DIN4_MODE_S)
+#define SPI_MEM_C_SMEM_DIN4_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN4_MODE_S  12
+/** SPI_MEM_C_SMEM_DIN5_MODE : HRO; bitpos: [17:15]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DIN5_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN5_MODE_M  (SPI_MEM_C_SMEM_DIN5_MODE_V << SPI_MEM_C_SMEM_DIN5_MODE_S)
+#define SPI_MEM_C_SMEM_DIN5_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN5_MODE_S  15
+/** SPI_MEM_C_SMEM_DIN6_MODE : HRO; bitpos: [20:18]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DIN6_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN6_MODE_M  (SPI_MEM_C_SMEM_DIN6_MODE_V << SPI_MEM_C_SMEM_DIN6_MODE_S)
+#define SPI_MEM_C_SMEM_DIN6_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN6_MODE_S  18
+/** SPI_MEM_C_SMEM_DIN7_MODE : HRO; bitpos: [23:21]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DIN7_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DIN7_MODE_M  (SPI_MEM_C_SMEM_DIN7_MODE_V << SPI_MEM_C_SMEM_DIN7_MODE_S)
+#define SPI_MEM_C_SMEM_DIN7_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DIN7_MODE_S  21
+/** SPI_MEM_C_SMEM_DINS_MODE : HRO; bitpos: [26:24]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DINS_MODE    0x00000007U
+#define SPI_MEM_C_SMEM_DINS_MODE_M  (SPI_MEM_C_SMEM_DINS_MODE_V << SPI_MEM_C_SMEM_DINS_MODE_S)
+#define SPI_MEM_C_SMEM_DINS_MODE_V  0x00000007U
+#define SPI_MEM_C_SMEM_DINS_MODE_S  24
+
+/** SPI_MEM_C_SMEM_DIN_NUM_REG register
+ *  MSPI external RAM input timing delay number control register
+ */
+#define SPI_MEM_C_SMEM_DIN_NUM_REG (DR_REG_FLASH_SPI0_BASE + 0x198)
+/** SPI_MEM_C_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_SMEM_DIN0_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN0_NUM_M  (SPI_MEM_C_SMEM_DIN0_NUM_V << SPI_MEM_C_SMEM_DIN0_NUM_S)
+#define SPI_MEM_C_SMEM_DIN0_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN0_NUM_S  0
+/** SPI_MEM_C_SMEM_DIN1_NUM : HRO; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_SMEM_DIN1_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN1_NUM_M  (SPI_MEM_C_SMEM_DIN1_NUM_V << SPI_MEM_C_SMEM_DIN1_NUM_S)
+#define SPI_MEM_C_SMEM_DIN1_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN1_NUM_S  2
+/** SPI_MEM_C_SMEM_DIN2_NUM : HRO; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_SMEM_DIN2_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN2_NUM_M  (SPI_MEM_C_SMEM_DIN2_NUM_V << SPI_MEM_C_SMEM_DIN2_NUM_S)
+#define SPI_MEM_C_SMEM_DIN2_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN2_NUM_S  4
+/** SPI_MEM_C_SMEM_DIN3_NUM : HRO; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_SMEM_DIN3_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN3_NUM_M  (SPI_MEM_C_SMEM_DIN3_NUM_V << SPI_MEM_C_SMEM_DIN3_NUM_S)
+#define SPI_MEM_C_SMEM_DIN3_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN3_NUM_S  6
+/** SPI_MEM_C_SMEM_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_SMEM_DIN4_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN4_NUM_M  (SPI_MEM_C_SMEM_DIN4_NUM_V << SPI_MEM_C_SMEM_DIN4_NUM_S)
+#define SPI_MEM_C_SMEM_DIN4_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN4_NUM_S  8
+/** SPI_MEM_C_SMEM_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_SMEM_DIN5_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN5_NUM_M  (SPI_MEM_C_SMEM_DIN5_NUM_V << SPI_MEM_C_SMEM_DIN5_NUM_S)
+#define SPI_MEM_C_SMEM_DIN5_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN5_NUM_S  10
+/** SPI_MEM_C_SMEM_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_SMEM_DIN6_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN6_NUM_M  (SPI_MEM_C_SMEM_DIN6_NUM_V << SPI_MEM_C_SMEM_DIN6_NUM_S)
+#define SPI_MEM_C_SMEM_DIN6_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN6_NUM_S  12
+/** SPI_MEM_C_SMEM_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_SMEM_DIN7_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DIN7_NUM_M  (SPI_MEM_C_SMEM_DIN7_NUM_V << SPI_MEM_C_SMEM_DIN7_NUM_S)
+#define SPI_MEM_C_SMEM_DIN7_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DIN7_NUM_S  14
+/** SPI_MEM_C_SMEM_DINS_NUM : HRO; bitpos: [17:16]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_C_SMEM_DINS_NUM    0x00000003U
+#define SPI_MEM_C_SMEM_DINS_NUM_M  (SPI_MEM_C_SMEM_DINS_NUM_V << SPI_MEM_C_SMEM_DINS_NUM_S)
+#define SPI_MEM_C_SMEM_DINS_NUM_V  0x00000003U
+#define SPI_MEM_C_SMEM_DINS_NUM_S  16
+
+/** SPI_MEM_C_SMEM_DOUT_MODE_REG register
+ *  MSPI external RAM output timing adjustment control register
+ */
+#define SPI_MEM_C_SMEM_DOUT_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x19c)
+/** SPI_MEM_C_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_C_SMEM_DOUT0_MODE_M  (SPI_MEM_C_SMEM_DOUT0_MODE_V << SPI_MEM_C_SMEM_DOUT0_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT0_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT0_MODE_S  0
+/** SPI_MEM_C_SMEM_DOUT1_MODE : HRO; bitpos: [1]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_C_SMEM_DOUT1_MODE_M  (SPI_MEM_C_SMEM_DOUT1_MODE_V << SPI_MEM_C_SMEM_DOUT1_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT1_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT1_MODE_S  1
+/** SPI_MEM_C_SMEM_DOUT2_MODE : HRO; bitpos: [2]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_C_SMEM_DOUT2_MODE_M  (SPI_MEM_C_SMEM_DOUT2_MODE_V << SPI_MEM_C_SMEM_DOUT2_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT2_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT2_MODE_S  2
+/** SPI_MEM_C_SMEM_DOUT3_MODE : HRO; bitpos: [3]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_C_SMEM_DOUT3_MODE_M  (SPI_MEM_C_SMEM_DOUT3_MODE_V << SPI_MEM_C_SMEM_DOUT3_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT3_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT3_MODE_S  3
+/** SPI_MEM_C_SMEM_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_C_SMEM_DOUT4_MODE_M  (SPI_MEM_C_SMEM_DOUT4_MODE_V << SPI_MEM_C_SMEM_DOUT4_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT4_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT4_MODE_S  4
+/** SPI_MEM_C_SMEM_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_C_SMEM_DOUT5_MODE_M  (SPI_MEM_C_SMEM_DOUT5_MODE_V << SPI_MEM_C_SMEM_DOUT5_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT5_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT5_MODE_S  5
+/** SPI_MEM_C_SMEM_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_C_SMEM_DOUT6_MODE_M  (SPI_MEM_C_SMEM_DOUT6_MODE_V << SPI_MEM_C_SMEM_DOUT6_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT6_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT6_MODE_S  6
+/** SPI_MEM_C_SMEM_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_C_SMEM_DOUT7_MODE_M  (SPI_MEM_C_SMEM_DOUT7_MODE_V << SPI_MEM_C_SMEM_DOUT7_MODE_S)
+#define SPI_MEM_C_SMEM_DOUT7_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUT7_MODE_S  7
+/** SPI_MEM_C_SMEM_DOUTS_MODE : HRO; bitpos: [8]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_C_SMEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_C_SMEM_DOUTS_MODE_M  (SPI_MEM_C_SMEM_DOUTS_MODE_V << SPI_MEM_C_SMEM_DOUTS_MODE_S)
+#define SPI_MEM_C_SMEM_DOUTS_MODE_V  0x00000001U
+#define SPI_MEM_C_SMEM_DOUTS_MODE_S  8
+
+/** SPI_MEM_C_SMEM_AC_REG register
+ *  MSPI external RAM ECC and SPI CS timing control register
+ */
+#define SPI_MEM_C_SMEM_AC_REG (DR_REG_FLASH_SPI0_BASE + 0x1a0)
+/** SPI_MEM_C_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0;
+ *  For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0:
+ *  disable.
+ */
+#define SPI_MEM_C_SMEM_CS_SETUP    (BIT(0))
+#define SPI_MEM_C_SMEM_CS_SETUP_M  (SPI_MEM_C_SMEM_CS_SETUP_V << SPI_MEM_C_SMEM_CS_SETUP_S)
+#define SPI_MEM_C_SMEM_CS_SETUP_V  0x00000001U
+#define SPI_MEM_C_SMEM_CS_SETUP_S  0
+/** SPI_MEM_C_SMEM_CS_HOLD : HRO; bitpos: [1]; default: 0;
+ *  For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable.
+ */
+#define SPI_MEM_C_SMEM_CS_HOLD    (BIT(1))
+#define SPI_MEM_C_SMEM_CS_HOLD_M  (SPI_MEM_C_SMEM_CS_HOLD_V << SPI_MEM_C_SMEM_CS_HOLD_S)
+#define SPI_MEM_C_SMEM_CS_HOLD_V  0x00000001U
+#define SPI_MEM_C_SMEM_CS_HOLD_S  1
+/** SPI_MEM_C_SMEM_CS_SETUP_TIME : HRO; bitpos: [6:2]; default: 1;
+ *  For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with
+ *  spi_mem_cs_setup bit.
+ */
+#define SPI_MEM_C_SMEM_CS_SETUP_TIME    0x0000001FU
+#define SPI_MEM_C_SMEM_CS_SETUP_TIME_M  (SPI_MEM_C_SMEM_CS_SETUP_TIME_V << SPI_MEM_C_SMEM_CS_SETUP_TIME_S)
+#define SPI_MEM_C_SMEM_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_MEM_C_SMEM_CS_SETUP_TIME_S  2
+/** SPI_MEM_C_SMEM_CS_HOLD_TIME : HRO; bitpos: [11:7]; default: 1;
+ *  For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are
+ *  combined with spi_mem_cs_hold bit.
+ */
+#define SPI_MEM_C_SMEM_CS_HOLD_TIME    0x0000001FU
+#define SPI_MEM_C_SMEM_CS_HOLD_TIME_M  (SPI_MEM_C_SMEM_CS_HOLD_TIME_V << SPI_MEM_C_SMEM_CS_HOLD_TIME_S)
+#define SPI_MEM_C_SMEM_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_MEM_C_SMEM_CS_HOLD_TIME_S  7
+/** SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3;
+ *  SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
+ *  cycles in ECC mode when accessed external RAM.
+ */
+#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME    0x00000007U
+#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_M  (SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_S)
+#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_V  0x00000007U
+#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_S  12
+/** SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [15]; default: 1;
+ *  1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when
+ *  accesses external RAM.
+ */
+#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
+#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_S)
+#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_V  0x00000001U
+#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_S  15
+/** SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [16]; default: 0;
+ *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+ *  accesses external RAM.
+ */
+#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
+#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_M  (SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_S)
+#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_S  16
+/** SPI_MEM_C_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0;
+ *  These bits are used to set the minimum CS high time tSHSL between SPI burst
+ *  transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1)
+ *  MSPI core clock cycles.
+ */
+#define SPI_MEM_C_SMEM_CS_HOLD_DELAY    0x0000003FU
+#define SPI_MEM_C_SMEM_CS_HOLD_DELAY_M  (SPI_MEM_C_SMEM_CS_HOLD_DELAY_V << SPI_MEM_C_SMEM_CS_HOLD_DELAY_S)
+#define SPI_MEM_C_SMEM_CS_HOLD_DELAY_V  0x0000003FU
+#define SPI_MEM_C_SMEM_CS_HOLD_DELAY_S  25
+/** SPI_MEM_C_SMEM_SPLIT_TRANS_EN : HRO; bitpos: [31]; default: 1;
+ *  Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
+ *  transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter
+ *  whether there is an ECC region or not.
+ */
+#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN    (BIT(31))
+#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN_M  (SPI_MEM_C_SMEM_SPLIT_TRANS_EN_V << SPI_MEM_C_SMEM_SPLIT_TRANS_EN_S)
+#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN_V  0x00000001U
+#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN_S  31
+
+/** SPI_MEM_C_CLOCK_GATE_REG register
+ *  SPI0 clock gate register
+ */
+#define SPI_MEM_C_CLOCK_GATE_REG (DR_REG_FLASH_SPI0_BASE + 0x200)
+/** SPI_MEM_C_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Register clock gate enable signal. 1: Enable. 0: Disable.
+ */
+#define SPI_MEM_C_CLK_EN    (BIT(0))
+#define SPI_MEM_C_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
+#define SPI_MEM_C_CLK_EN_V  0x00000001U
+#define SPI_MEM_C_CLK_EN_S  0
+
+/** SPI_MEM_C_XTS_PLAIN_BASE_REG register
+ *  The base address of the memory that stores plaintext in Manual Encryption
+ */
+#define SPI_MEM_C_XTS_PLAIN_BASE_REG (DR_REG_FLASH_SPI0_BASE + 0x300)
+/** SPI_MEM_C_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0;
+ *  This field is only used to generate include file in c case. This field is useless.
+ *  Please do not use this field.
+ */
+#define SPI_MEM_C_XTS_PLAIN    0xFFFFFFFFU
+#define SPI_MEM_C_XTS_PLAIN_M  (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S)
+#define SPI_MEM_C_XTS_PLAIN_V  0xFFFFFFFFU
+#define SPI_MEM_C_XTS_PLAIN_S  0
+
+/** SPI_MEM_C_XTS_LINESIZE_REG register
+ *  Manual Encryption Line-Size register
+ */
+#define SPI_MEM_C_XTS_LINESIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x340)
+/** SPI_MEM_C_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0;
+ *  This bits stores the line-size parameter which will be used in manual encryption
+ *  calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1:
+ *  32-bytes, 2: 64-bytes, 3:reserved.
+ */
+#define SPI_MEM_C_XTS_LINESIZE    0x00000003U
+#define SPI_MEM_C_XTS_LINESIZE_M  (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S)
+#define SPI_MEM_C_XTS_LINESIZE_V  0x00000003U
+#define SPI_MEM_C_XTS_LINESIZE_S  0
+
+/** SPI_MEM_C_XTS_DESTINATION_REG register
+ *  Manual Encryption destination register
+ */
+#define SPI_MEM_C_XTS_DESTINATION_REG (DR_REG_FLASH_SPI0_BASE + 0x344)
+/** SPI_MEM_C_XTS_DESTINATION : R/W; bitpos: [0]; default: 0;
+ *  This bit stores the destination parameter which will be used in manual encryption
+ *  calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.
+ */
+#define SPI_MEM_C_XTS_DESTINATION    (BIT(0))
+#define SPI_MEM_C_XTS_DESTINATION_M  (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S)
+#define SPI_MEM_C_XTS_DESTINATION_V  0x00000001U
+#define SPI_MEM_C_XTS_DESTINATION_S  0
+
+/** SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG register
+ *  Manual Encryption physical address register
+ */
+#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG (DR_REG_FLASH_SPI0_BASE + 0x348)
+/** SPI_MEM_C_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0;
+ *  This bits stores the physical-address parameter which will be used in manual
+ *  encryption calculation. This value should aligned with byte number decided by
+ *  line-size parameter.
+ */
+#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS    0x03FFFFFFU
+#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_M  (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S)
+#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_V  0x03FFFFFFU
+#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_S  0
+
+/** SPI_MEM_C_XTS_TRIGGER_REG register
+ *  Manual Encryption physical address register
+ */
+#define SPI_MEM_C_XTS_TRIGGER_REG (DR_REG_FLASH_SPI0_BASE + 0x34c)
+/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Set this bit to trigger the process of manual encryption calculation. This action
+ *  should only be asserted when manual encryption status is 0. After this action,
+ *  manual encryption status becomes 1. After calculation is done, manual encryption
+ *  status becomes 2.
+ */
+#define SPI_XTS_TRIGGER    (BIT(0))
+#define SPI_XTS_TRIGGER_M  (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S)
+#define SPI_XTS_TRIGGER_V  0x00000001U
+#define SPI_XTS_TRIGGER_S  0
+
+/** SPI_MEM_C_XTS_RELEASE_REG register
+ *  Manual Encryption physical address register
+ */
+#define SPI_MEM_C_XTS_RELEASE_REG (DR_REG_FLASH_SPI0_BASE + 0x350)
+/** SPI_MEM_C_XTS_RELEASE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to release encrypted result to mspi. This action should only be
+ *  asserted when manual encryption status is 2. After this action, manual encryption
+ *  status will become 3.
+ */
+#define SPI_MEM_C_XTS_RELEASE    (BIT(0))
+#define SPI_MEM_C_XTS_RELEASE_M  (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S)
+#define SPI_MEM_C_XTS_RELEASE_V  0x00000001U
+#define SPI_MEM_C_XTS_RELEASE_S  0
+
+/** SPI_MEM_C_XTS_DESTROY_REG register
+ *  Manual Encryption physical address register
+ */
+#define SPI_MEM_C_XTS_DESTROY_REG (DR_REG_FLASH_SPI0_BASE + 0x354)
+/** SPI_MEM_C_XTS_DESTROY : WT; bitpos: [0]; default: 0;
+ *  Set this bit to destroy encrypted result. This action should be asserted only when
+ *  manual encryption status is 3. After this action, manual encryption status will
+ *  become 0.
+ */
+#define SPI_MEM_C_XTS_DESTROY    (BIT(0))
+#define SPI_MEM_C_XTS_DESTROY_M  (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S)
+#define SPI_MEM_C_XTS_DESTROY_V  0x00000001U
+#define SPI_MEM_C_XTS_DESTROY_S  0
+
+/** SPI_MEM_C_XTS_STATE_REG register
+ *  Manual Encryption physical address register
+ */
+#define SPI_MEM_C_XTS_STATE_REG (DR_REG_FLASH_SPI0_BASE + 0x358)
+/** SPI_MEM_C_XTS_STATE : RO; bitpos: [1:0]; default: 0;
+ *  This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
+ *  calculation, 2: encryption calculation is done but the encrypted result is
+ *  invisible to mspi, 3: the encrypted result is visible to mspi.
+ */
+#define SPI_MEM_C_XTS_STATE    0x00000003U
+#define SPI_MEM_C_XTS_STATE_M  (SPI_XTS_STATE_V << SPI_XTS_STATE_S)
+#define SPI_MEM_C_XTS_STATE_V  0x00000003U
+#define SPI_MEM_C_XTS_STATE_S  0
+
+/** SPI_MEM_C_XTS_DATE_REG register
+ *  Manual Encryption version register
+ */
+#define SPI_MEM_C_XTS_DATE_REG (DR_REG_FLASH_SPI0_BASE + 0x35c)
+/** SPI_MEM_C_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176;
+ *  This bits stores the last modified-time of manual encryption feature.
+ */
+#define SPI_MEM_C_XTS_DATE    0x3FFFFFFFU
+#define SPI_MEM_C_XTS_DATE_M  (SPI_XTS_DATE_V << SPI_XTS_DATE_S)
+#define SPI_MEM_C_XTS_DATE_V  0x3FFFFFFFU
+#define SPI_MEM_C_XTS_DATE_S  0
+
+/** SPI_MEM_C_MMU_ITEM_CONTENT_REG register
+ *  MSPI-MMU item content register
+ */
+#define SPI_MEM_C_MMU_ITEM_CONTENT_REG (DR_REG_FLASH_SPI0_BASE + 0x37c)
+/** SPI_MEM_C_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892;
+ *  MSPI-MMU item content
+ */
+#define SPI_MEM_C_MMU_ITEM_CONTENT    0xFFFFFFFFU
+#define SPI_MEM_C_MMU_ITEM_CONTENT_M  (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S)
+#define SPI_MEM_C_MMU_ITEM_CONTENT_V  0xFFFFFFFFU
+#define SPI_MEM_C_MMU_ITEM_CONTENT_S  0
+
+/** SPI_MEM_C_MMU_ITEM_INDEX_REG register
+ *  MSPI-MMU item index register
+ */
+#define SPI_MEM_C_MMU_ITEM_INDEX_REG (DR_REG_FLASH_SPI0_BASE + 0x380)
+/** SPI_MEM_C_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0;
+ *  MSPI-MMU item index
+ */
+#define SPI_MEM_C_MMU_ITEM_INDEX    0xFFFFFFFFU
+#define SPI_MEM_C_MMU_ITEM_INDEX_M  (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S)
+#define SPI_MEM_C_MMU_ITEM_INDEX_V  0xFFFFFFFFU
+#define SPI_MEM_C_MMU_ITEM_INDEX_S  0
+
+/** SPI_MEM_C_MMU_POWER_CTRL_REG register
+ *  MSPI MMU power control register
+ */
+#define SPI_MEM_C_MMU_POWER_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x384)
+/** SPI_MEM_C_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable mmu-memory clock force on
+ */
+#define SPI_MEM_C_MMU_MEM_FORCE_ON    (BIT(0))
+#define SPI_MEM_C_MMU_MEM_FORCE_ON_M  (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S)
+#define SPI_MEM_C_MMU_MEM_FORCE_ON_V  0x00000001U
+#define SPI_MEM_C_MMU_MEM_FORCE_ON_S  0
+/** SPI_MEM_C_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to force mmu-memory powerdown
+ */
+#define SPI_MEM_C_MMU_MEM_FORCE_PD    (BIT(1))
+#define SPI_MEM_C_MMU_MEM_FORCE_PD_M  (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S)
+#define SPI_MEM_C_MMU_MEM_FORCE_PD_V  0x00000001U
+#define SPI_MEM_C_MMU_MEM_FORCE_PD_S  1
+/** SPI_MEM_C_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to force mmu-memory powerup, in this case, the power should also be
+ *  controlled by rtc.
+ */
+#define SPI_MEM_C_MMU_MEM_FORCE_PU    (BIT(2))
+#define SPI_MEM_C_MMU_MEM_FORCE_PU_M  (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S)
+#define SPI_MEM_C_MMU_MEM_FORCE_PU_V  0x00000001U
+#define SPI_MEM_C_MMU_MEM_FORCE_PU_S  2
+/** SPI_MEM_C_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0;
+ *  0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8
+ */
+#define SPI_MEM_C_MMU_PAGE_SIZE    0x00000003U
+#define SPI_MEM_C_MMU_PAGE_SIZE_M  (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S)
+#define SPI_MEM_C_MMU_PAGE_SIZE_V  0x00000003U
+#define SPI_MEM_C_MMU_PAGE_SIZE_S  3
+/** SPI_MEM_C_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896;
+ *  MMU PSRAM aux control register
+ */
+#define SPI_MEM_C_AUX_CTRL    0x00003FFFU
+#define SPI_MEM_C_AUX_CTRL_M  (SPI_MEM_C_AUX_CTRL_V << SPI_MEM_C_AUX_CTRL_S)
+#define SPI_MEM_C_AUX_CTRL_V  0x00003FFFU
+#define SPI_MEM_C_AUX_CTRL_S  16
+
+/** SPI_MEM_C_DPA_CTRL_REG register
+ *  SPI memory cryption DPA register
+ */
+#define SPI_MEM_C_DPA_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x388)
+/** SPI_MEM_C_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
+ *  Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7:
+ *  The bigger the number is, the more secure the cryption is. (Note that the
+ *  performance of cryption will decrease together with this number increasing)
+ */
+#define SPI_MEM_C_CRYPT_SECURITY_LEVEL    0x00000007U
+#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_M  (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S)
+#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_V  0x00000007U
+#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_S  0
+/** SPI_MEM_C_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1;
+ *  Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the
+ *  calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that
+ *  using key 1.
+ */
+#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN    (BIT(3))
+#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_M  (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S)
+#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_V  0x00000001U
+#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_S  3
+/** SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0;
+ *  1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and
+ *  SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.
+ */
+#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
+#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_M  (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S)
+#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_V  0x00000001U
+#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_S  4
+
+/** SPI_MEM_C_DATE_REG register
+ *  SPI0 version control register
+ */
+#define SPI_MEM_C_DATE_REG (DR_REG_FLASH_SPI0_BASE + 0x3fc)
+/** SPI_MEM_C_DATE : R/W; bitpos: [27:0]; default: 36712560;
+ *  SPI0 register version.
+ */
+#define SPI_MEM_C_DATE    0x0FFFFFFFU
+#define SPI_MEM_C_DATE_M  (SPI_MEM_C_DATE_V << SPI_MEM_C_DATE_S)
+#define SPI_MEM_C_DATE_V  0x0FFFFFFFU
+#define SPI_MEM_C_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h
new file mode 100644
index 0000000000..9ddcb3f6ce
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h
@@ -0,0 +1,2028 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Status and state control register */
+/** Type of cmd register
+ *  SPI0 FSM status register
+ */
+typedef union {
+    struct {
+        /** mst_st : RO; bitpos: [3:0]; default: 0;
+         *  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT ,
+         *  2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent
+         *  data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
+         */
+        uint32_t mst_st:4;
+        /** slv_st : RO; bitpos: [7:4]; default: 0;
+         *  The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state,
+         *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
+         *  6:write data state, 7: done state, 8: read data end state.
+         */
+        uint32_t slv_st:4;
+        uint32_t reserved_8:10;
+        /** usr : HRO; bitpos: [18]; default: 0;
+         *  SPI0 USR_CMD start bit, only used when spi_mem_c_C_AXI_REQ_EN is cleared.  An operation
+         *  will be triggered when the bit is set. The bit will be cleared once the operation
+         *  done.1: enable 0: disable.
+         */
+        uint32_t usr:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} spi_mem_c_cmd_reg_t;
+
+/** Type of axi_err_addr register
+ *  SPI0 AXI request error address.
+ */
+typedef union {
+    struct {
+        /** axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
+         *  This bits show the first AXI write/read invalid error or AXI write flash error
+         *  address. It is cleared by when spi_mem_c_C_AXI_WADDR_ERR_INT_CLR,
+         *  spi_mem_c_C_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_C_AXI_RADDR_ERR_IN_CLR bit is set.
+         */
+        uint32_t axi_err_addr:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_c_axi_err_addr_reg_t;
+
+
+/** Group: Flash Control and configuration registers */
+/** Type of ctrl register
+ *  SPI0 control register.
+ */
+typedef union {
+    struct {
+        /** wdummy_dqs_always_out : HRO; bitpos: [0]; default: 0;
+         *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
+         *  of SPI_DQS is output by the MSPI controller.
+         */
+        uint32_t wdummy_dqs_always_out:1;
+        /** wdummy_always_out : R/W; bitpos: [1]; default: 0;
+         *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
+         *  of SPI_IO[7:0] is output by the MSPI controller.
+         */
+        uint32_t wdummy_always_out:1;
+        /** fdummy_rin : R/W; bitpos: [2]; default: 1;
+         *  In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is
+         *  output by the MSPI controller in the first half part of dummy phase. It is used to
+         *  mask invalid SPI_DQS in the half part of dummy phase.
+         */
+        uint32_t fdummy_rin:1;
+        /** fdummy_wout : R/W; bitpos: [3]; default: 1;
+         *  In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is
+         *  output by the MSPI controller in the second half part of dummy phase. It is used to
+         *  pre-drive flash.
+         */
+        uint32_t fdummy_wout:1;
+        /** fdout_oct : HRO; bitpos: [4]; default: 0;
+         *  Apply 8 signals during write-data phase 1:enable 0: disable
+         */
+        uint32_t fdout_oct:1;
+        /** fdin_oct : HRO; bitpos: [5]; default: 0;
+         *  Apply 8 signals during read-data phase 1:enable 0: disable
+         */
+        uint32_t fdin_oct:1;
+        /** faddr_oct : HRO; bitpos: [6]; default: 0;
+         *  Apply 8 signals during address phase 1:enable 0: disable
+         */
+        uint32_t faddr_oct:1;
+        uint32_t reserved_7:1;
+        /** fcmd_quad : R/W; bitpos: [8]; default: 0;
+         *  Apply 4 signals during command phase 1:enable 0: disable
+         */
+        uint32_t fcmd_quad:1;
+        /** fcmd_oct : HRO; bitpos: [9]; default: 0;
+         *  Apply 8 signals during command phase 1:enable 0: disable
+         */
+        uint32_t fcmd_oct:1;
+        uint32_t reserved_10:3;
+        /** fastrd_mode : R/W; bitpos: [13]; default: 1;
+         *  This bit enable the bits: spi_mem_c_C_FREAD_QIO, spi_mem_c_C_FREAD_DIO, spi_mem_c_C_FREAD_QOUT
+         *  and spi_mem_c_C_FREAD_DOUT. 1: enable 0: disable.
+         */
+        uint32_t fastrd_mode:1;
+        /** fread_dual : R/W; bitpos: [14]; default: 0;
+         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+         */
+        uint32_t fread_dual:1;
+        uint32_t reserved_15:3;
+        /** q_pol : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to set MISO line polarity, 1: high 0, low
+         */
+        uint32_t q_pol:1;
+        /** d_pol : R/W; bitpos: [19]; default: 1;
+         *  The bit is used to set MOSI line polarity, 1: high 0, low
+         */
+        uint32_t d_pol:1;
+        /** fread_quad : R/W; bitpos: [20]; default: 0;
+         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+         */
+        uint32_t fread_quad:1;
+        /** wp_reg : R/W; bitpos: [21]; default: 1;
+         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
+         */
+        uint32_t wp_reg:1;
+        uint32_t reserved_22:1;
+        /** fread_dio : R/W; bitpos: [23]; default: 0;
+         *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
+         *  0: disable.
+         */
+        uint32_t fread_dio:1;
+        /** fread_qio : R/W; bitpos: [24]; default: 0;
+         *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
+         *  0: disable.
+         */
+        uint32_t fread_qio:1;
+        uint32_t reserved_25:5;
+        /** dqs_ie_always_on : HRO; bitpos: [30]; default: 0;
+         *  When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
+         *  1. 0: Others.
+         */
+        uint32_t dqs_ie_always_on:1;
+        /** data_ie_always_on : R/W; bitpos: [31]; default: 1;
+         *  When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are
+         *  always 1. 0: Others.
+         */
+        uint32_t data_ie_always_on:1;
+    };
+    uint32_t val;
+} spi_mem_c_ctrl_reg_t;
+
+/** Type of ctrl1 register
+ *  SPI0 control1 register.
+ */
+typedef union {
+    struct {
+        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on.
+         */
+        uint32_t clk_mode:2;
+        uint32_t reserved_2:19;
+        /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1;
+         *  1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply
+         *  the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.
+         */
+        uint32_t ar_size0_1_support_en:1;
+        /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1;
+         *  1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.
+         */
+        uint32_t aw_size0_1_support_en:1;
+        /** axi_rdata_back_fast : HRO; bitpos: [23]; default: 1;
+         *  1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0:
+         *  Reply AXI read data to AXI bus when all the read data is available.
+         */
+        uint32_t axi_rdata_back_fast:1;
+        /** rresp_ecc_err_en : R/W; bitpos: [24]; default: 0;
+         *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
+         *  when there is a ECC error in AXI read data. The ECC error information is recorded
+         *  in spi_mem_c_C_ECC_ERR_ADDR_REG.
+         */
+        uint32_t rresp_ecc_err_en:1;
+        /** ar_splice_en : HRO; bitpos: [25]; default: 0;
+         *  Set this bit to enable AXI Read Splice-transfer.
+         */
+        uint32_t ar_splice_en:1;
+        /** aw_splice_en : HRO; bitpos: [26]; default: 0;
+         *  Set this bit to enable AXI Write Splice-transfer.
+         */
+        uint32_t aw_splice_en:1;
+        /** ram0_en : HRO; bitpos: [27]; default: 1;
+         *  When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 1, only EXT_RAM0 will be
+         *  accessed. When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 0, only EXT_RAM1
+         *  will be accessed. When spi_mem_c_C_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
+         *  accessed at the same time.
+         */
+        uint32_t ram0_en:1;
+        /** dual_ram_en : HRO; bitpos: [28]; default: 0;
+         *  Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the
+         *  same time.
+         */
+        uint32_t dual_ram_en:1;
+        /** fast_write_en : R/W; bitpos: [29]; default: 1;
+         *  Set this bit to write data faster, do not wait write data has been stored in
+         *  tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
+         *  in  tx_bus_fifo_l2.
+         */
+        uint32_t fast_write_en:1;
+        /** rxfifo_rst : WT; bitpos: [30]; default: 0;
+         *  The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
+         *  receive signals from AXI.  Set this bit to reset these FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : WT; bitpos: [31]; default: 0;
+         *  The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
+         *  send signals to AXI. Set this bit to reset these FIFO.
+         */
+        uint32_t txfifo_rst:1;
+    };
+    uint32_t val;
+} spi_mem_c_ctrl1_reg_t;
+
+/** Type of ctrl2 register
+ *  SPI0 control2 register.
+ */
+typedef union {
+    struct {
+        /** cs_setup_time : R/W; bitpos: [4:0]; default: 1;
+         *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
+         *  spi_mem_c_C_CS_SETUP bit.
+         */
+        uint32_t cs_setup_time:5;
+        /** cs_hold_time : R/W; bitpos: [9:5]; default: 1;
+         *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
+         *  spi_mem_c_C_CS_HOLD bit.
+         */
+        uint32_t cs_hold_time:5;
+        /** ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3;
+         *  spi_mem_c_C_CS_HOLD_TIME + spi_mem_c_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+         *  mode when accessed flash.
+         */
+        uint32_t ecc_cs_hold_time:3;
+        /** ecc_skip_page_corner : HRO; bitpos: [13]; default: 1;
+         *  1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when
+         *  accesses flash.
+         */
+        uint32_t ecc_skip_page_corner:1;
+        /** ecc_16to18_byte_en : HRO; bitpos: [14]; default: 0;
+         *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+         *  accesses flash.
+         */
+        uint32_t ecc_16to18_byte_en:1;
+        uint32_t reserved_15:9;
+        /** split_trans_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable SPI0 split one AXI read flash transfer into two SPI
+         *  transfers when one transfer will cross flash or EXT_RAM page corner, valid no
+         *  matter whether there is an ECC region or not.
+         */
+        uint32_t split_trans_en:1;
+        /** cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
+         *  These bits are used to set the minimum CS high time tSHSL between SPI burst
+         *  transfer when accesses to flash. tSHSL is (spi_mem_c_C_CS_HOLD_DELAY[5:0] + 1) MSPI
+         *  core clock cycles.
+         */
+        uint32_t cs_hold_delay:6;
+        /** sync_reset : WT; bitpos: [31]; default: 0;
+         *  The spi0_mst_st and spi0_slv_st will be reset.
+         */
+        uint32_t sync_reset:1;
+    };
+    uint32_t val;
+} spi_mem_c_ctrl2_reg_t;
+
+/** Type of misc register
+ *  SPI0 misc register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:7;
+        /** fsub_pin : HRO; bitpos: [7]; default: 0;
+         *  For SPI0,  flash is connected to SUBPINs.
+         */
+        uint32_t fsub_pin:1;
+        /** ssub_pin : HRO; bitpos: [8]; default: 0;
+         *  For SPI0,  sram is connected to SUBPINs.
+         */
+        uint32_t ssub_pin:1;
+        /** ck_idle_edge : R/W; bitpos: [9]; default: 0;
+         *  1: SPI_CLK line is high when idle     0: spi clk line is low when idle
+         */
+        uint32_t ck_idle_edge:1;
+        /** cs_keep_active : R/W; bitpos: [10]; default: 0;
+         *  SPI_CS line keep low when the bit is set.
+         */
+        uint32_t cs_keep_active:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi_mem_c_misc_reg_t;
+
+/** Type of cache_fctrl register
+ *  SPI0 bit mode control register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** same_aw_ar_addr_chk_en : HRO; bitpos: [30]; default: 1;
+         *  Set this bit to check AXI read/write the same address region.
+         */
+        uint32_t same_aw_ar_addr_chk_en:1;
+        /** close_axi_inf_en : R/W; bitpos: [31]; default: 1;
+         *  Set this bit to close AXI read/write transfer to MSPI, which means that only
+         *  SLV_ERR will be replied to BRESP/RRESP.
+         */
+        uint32_t close_axi_inf_en:1;
+    };
+    uint32_t val;
+} spi_mem_c_cache_fctrl_reg_t;
+
+/** Type of ddr register
+ *  SPI0 flash DDR mode control register
+ */
+typedef union {
+    struct {
+        /** fmem_ddr_en : HRO; bitpos: [0]; default: 0;
+         *  1: in DDR mode,  0 in SDR mode
+         */
+        uint32_t fmem_ddr_en:1;
+        /** fmem_var_dummy : HRO; bitpos: [1]; default: 0;
+         *  Set the bit to enable variable dummy cycle in spi DDR mode.
+         */
+        uint32_t fmem_var_dummy:1;
+        /** fmem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0;
+         *  Set the bit to reorder rx data of the word in spi DDR mode.
+         */
+        uint32_t fmem_ddr_rdat_swp:1;
+        /** fmem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0;
+         *  Set the bit to reorder tx data of the word in spi DDR mode.
+         */
+        uint32_t fmem_ddr_wdat_swp:1;
+        /** fmem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0;
+         *  the bit is used to disable dual edge in command phase when DDR mode.
+         */
+        uint32_t fmem_ddr_cmd_dis:1;
+        /** fmem_outminbytelen : HRO; bitpos: [11:5]; default: 1;
+         *  It is the minimum output data length in the panda device.
+         */
+        uint32_t fmem_outminbytelen:7;
+        /** fmem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1;
+         *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+         *  accesses to flash.
+         */
+        uint32_t fmem_tx_ddr_msk_en:1;
+        /** fmem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1;
+         *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+         *  accesses to flash.
+         */
+        uint32_t fmem_rx_ddr_msk_en:1;
+        /** fmem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0;
+         *  The delay number of data strobe which from memory based on SPI clock.
+         */
+        uint32_t fmem_usr_ddr_dqs_thd:7;
+        /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
+         *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+         *  spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or
+         *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+         *  negative edge of SPI_DQS.
+         */
+        uint32_t fmem_ddr_dqs_loop:1;
+        uint32_t reserved_22:2;
+        /** fmem_clk_diff_en : HRO; bitpos: [24]; default: 0;
+         *  Set this bit to enable the differential SPI_CLK#.
+         */
+        uint32_t fmem_clk_diff_en:1;
+        uint32_t reserved_25:1;
+        /** fmem_dqs_ca_in : HRO; bitpos: [26]; default: 0;
+         *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+         */
+        uint32_t fmem_dqs_ca_in:1;
+        /** fmem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0;
+         *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+         *  accesses flash or SPI1 accesses flash or sram.
+         */
+        uint32_t fmem_hyperbus_dummy_2x:1;
+        /** fmem_clk_diff_inv : HRO; bitpos: [28]; default: 0;
+         *  Set this bit to invert SPI_DIFF when accesses to flash. .
+         */
+        uint32_t fmem_clk_diff_inv:1;
+        /** fmem_octa_ram_addr : HRO; bitpos: [29]; default: 0;
+         *  Set this bit to enable octa_ram address out when accesses to flash, which means
+         *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
+         */
+        uint32_t fmem_octa_ram_addr:1;
+        /** fmem_hyperbus_ca : HRO; bitpos: [30]; default: 0;
+         *  Set this bit to enable HyperRAM address out when accesses to flash, which means
+         *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+         */
+        uint32_t fmem_hyperbus_ca:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} spi_mem_c_ddr_reg_t;
+
+
+/** Group: Clock control and configuration registers */
+/** Type of clock register
+ *  SPI clock division control register.
+ */
+typedef union {
+    struct {
+        /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
+         *  In the master mode it must be equal to spi_mem_c_clkcnt_N.
+         */
+        uint32_t clkcnt_l:8;
+        /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
+         *  In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1).
+         */
+        uint32_t clkcnt_h:8;
+        /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
+         *  In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is
+         *  system/(spi_mem_c_clkcnt_N+1)
+         */
+        uint32_t clkcnt_n:8;
+        uint32_t reserved_24:7;
+        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0;
+         *  1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
+         *  clock.
+         */
+        uint32_t clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi_mem_c_clock_reg_t;
+
+/** Type of clock_gate register
+ *  SPI0 clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Register clock gate enable signal. 1: Enable. 0: Disable.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi_mem_c_clock_gate_reg_t;
+
+
+/** Group: Flash User-defined control registers */
+/** Type of user register
+ *  SPI0 user register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** cs_hold : R/W; bitpos: [6]; default: 0;
+         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable.
+         */
+        uint32_t cs_hold:1;
+        /** cs_setup : R/W; bitpos: [7]; default: 0;
+         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.
+         */
+        uint32_t cs_setup:1;
+        uint32_t reserved_8:1;
+        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  The bit combined with spi_mem_c_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
+         */
+        uint32_t ck_out_edge:1;
+        uint32_t reserved_10:16;
+        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  spi clock is disable in dummy phase when the bit is enable.
+         */
+        uint32_t usr_dummy_idle:1;
+        uint32_t reserved_27:2;
+        /** usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  This bit enable the dummy phase of an operation.
+         */
+        uint32_t usr_dummy:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_mem_c_user_reg_t;
+
+/** Type of user1 register
+ *  SPI0 user1 register.
+ */
+typedef union {
+    struct {
+        /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
+         *  The length in spi_mem_c_clk cycles of dummy phase. The register value shall be
+         *  (cycle_num-1).
+         */
+        uint32_t usr_dummy_cyclelen:6;
+        /** usr_dbytelen : HRO; bitpos: [8:6]; default: 1;
+         *  SPI0 USR_CMD read or write data byte length -1
+         */
+        uint32_t usr_dbytelen:3;
+        uint32_t reserved_9:17;
+        /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23;
+         *  The length in bits of address phase. The register value shall be (bit_num-1).
+         */
+        uint32_t usr_addr_bitlen:6;
+    };
+    uint32_t val;
+} spi_mem_c_user1_reg_t;
+
+/** Type of user2 register
+ *  SPI0 user2 register.
+ */
+typedef union {
+    struct {
+        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  The value of  command.
+         */
+        uint32_t usr_command_value:16;
+        uint32_t reserved_16:12;
+        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  The length in bits of command phase. The register value shall be (bit_num-1)
+         */
+        uint32_t usr_command_bitlen:4;
+    };
+    uint32_t val;
+} spi_mem_c_user2_reg_t;
+
+
+/** Group: External RAM Control and configuration registers */
+/** Type of sram_cmd register
+ *  SPI0 external RAM mode control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** smem_wdummy_dqs_always_out : HRO; bitpos: [24]; default: 0;
+         *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+         *  the level of SPI_DQS is output by the MSPI controller.
+         */
+        uint32_t smem_wdummy_dqs_always_out:1;
+        /** smem_wdummy_always_out : HRO; bitpos: [25]; default: 0;
+         *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+         *  the level of SPI_IO[7:0] is output by the MSPI controller.
+         */
+        uint32_t smem_wdummy_always_out:1;
+        uint32_t reserved_26:4;
+        /** smem_dqs_ie_always_on : HRO; bitpos: [30]; default: 1;
+         *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are
+         *  always 1. 0: Others.
+         */
+        uint32_t smem_dqs_ie_always_on:1;
+        /** smem_data_ie_always_on : HRO; bitpos: [31]; default: 1;
+         *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0]
+         *  are always 1. 0: Others.
+         */
+        uint32_t smem_data_ie_always_on:1;
+    };
+    uint32_t val;
+} spi_mem_c_sram_cmd_reg_t;
+
+/** Type of smem_ddr register
+ *  SPI0 external RAM DDR mode control register
+ */
+typedef union {
+    struct {
+        /** smem_ddr_en : HRO; bitpos: [0]; default: 0;
+         *  1: in DDR mode,  0 in SDR mode
+         */
+        uint32_t smem_ddr_en:1;
+        /** smem_var_dummy : HRO; bitpos: [1]; default: 0;
+         *  Set the bit to enable variable dummy cycle in spi DDR mode.
+         */
+        uint32_t smem_var_dummy:1;
+        /** smem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0;
+         *  Set the bit to reorder rx data of the word in spi DDR mode.
+         */
+        uint32_t smem_ddr_rdat_swp:1;
+        /** smem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0;
+         *  Set the bit to reorder tx data of the word in spi DDR mode.
+         */
+        uint32_t smem_ddr_wdat_swp:1;
+        /** smem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0;
+         *  the bit is used to disable dual edge in command phase when DDR mode.
+         */
+        uint32_t smem_ddr_cmd_dis:1;
+        /** smem_outminbytelen : HRO; bitpos: [11:5]; default: 1;
+         *  It is the minimum output data length in the DDR psram.
+         */
+        uint32_t smem_outminbytelen:7;
+        /** smem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1;
+         *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+         *  accesses to external RAM.
+         */
+        uint32_t smem_tx_ddr_msk_en:1;
+        /** smem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1;
+         *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+         *  accesses to external RAM.
+         */
+        uint32_t smem_rx_ddr_msk_en:1;
+        /** smem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0;
+         *  The delay number of data strobe which from memory based on SPI clock.
+         */
+        uint32_t smem_usr_ddr_dqs_thd:7;
+        /** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
+         *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+         *  spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or
+         *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+         *  negative edge of SPI_DQS.
+         */
+        uint32_t smem_ddr_dqs_loop:1;
+        uint32_t reserved_22:2;
+        /** smem_clk_diff_en : HRO; bitpos: [24]; default: 0;
+         *  Set this bit to enable the differential SPI_CLK#.
+         */
+        uint32_t smem_clk_diff_en:1;
+        uint32_t reserved_25:1;
+        /** smem_dqs_ca_in : HRO; bitpos: [26]; default: 0;
+         *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+         */
+        uint32_t smem_dqs_ca_in:1;
+        /** smem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0;
+         *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+         *  accesses flash or SPI1 accesses flash or sram.
+         */
+        uint32_t smem_hyperbus_dummy_2x:1;
+        /** smem_clk_diff_inv : HRO; bitpos: [28]; default: 0;
+         *  Set this bit to invert SPI_DIFF when accesses to external RAM. .
+         */
+        uint32_t smem_clk_diff_inv:1;
+        /** smem_octa_ram_addr : HRO; bitpos: [29]; default: 0;
+         *  Set this bit to enable octa_ram address out when accesses to external RAM, which
+         *  means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1],
+         *  1'b0}.
+         */
+        uint32_t smem_octa_ram_addr:1;
+        /** smem_hyperbus_ca : HRO; bitpos: [30]; default: 0;
+         *  Set this bit to enable HyperRAM address out when accesses to external RAM, which
+         *  means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+         */
+        uint32_t smem_hyperbus_ca:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} spi_mem_c_smem_ddr_reg_t;
+
+/** Type of smem_ac register
+ *  MSPI external RAM ECC and SPI CS timing control register
+ */
+typedef union {
+    struct {
+        /** smem_cs_setup : HRO; bitpos: [0]; default: 0;
+         *  For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0:
+         *  disable.
+         */
+        uint32_t smem_cs_setup:1;
+        /** smem_cs_hold : HRO; bitpos: [1]; default: 0;
+         *  For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable.
+         */
+        uint32_t smem_cs_hold:1;
+        /** smem_cs_setup_time : HRO; bitpos: [6:2]; default: 1;
+         *  For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with
+         *  spi_mem_c_cs_setup bit.
+         */
+        uint32_t smem_cs_setup_time:5;
+        /** smem_cs_hold_time : HRO; bitpos: [11:7]; default: 1;
+         *  For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are
+         *  combined with spi_mem_c_cs_hold bit.
+         */
+        uint32_t smem_cs_hold_time:5;
+        /** smem_ecc_cs_hold_time : HRO; bitpos: [14:12]; default: 3;
+         *  SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
+         *  cycles in ECC mode when accessed external RAM.
+         */
+        uint32_t smem_ecc_cs_hold_time:3;
+        /** smem_ecc_skip_page_corner : HRO; bitpos: [15]; default: 1;
+         *  1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when
+         *  accesses external RAM.
+         */
+        uint32_t smem_ecc_skip_page_corner:1;
+        /** smem_ecc_16to18_byte_en : HRO; bitpos: [16]; default: 0;
+         *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+         *  accesses external RAM.
+         */
+        uint32_t smem_ecc_16to18_byte_en:1;
+        uint32_t reserved_17:8;
+        /** smem_cs_hold_delay : HRO; bitpos: [30:25]; default: 0;
+         *  These bits are used to set the minimum CS high time tSHSL between SPI burst
+         *  transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1)
+         *  MSPI core clock cycles.
+         */
+        uint32_t smem_cs_hold_delay:6;
+        /** smem_split_trans_en : HRO; bitpos: [31]; default: 1;
+         *  Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
+         *  transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter
+         *  whether there is an ECC region or not.
+         */
+        uint32_t smem_split_trans_en:1;
+    };
+    uint32_t val;
+} spi_mem_c_smem_ac_reg_t;
+
+
+/** Group: State control register */
+/** Type of fsm register
+ *  SPI0 FSM status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:7;
+        /** lock_delay_time : R/W; bitpos: [11:7]; default: 4;
+         *  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
+         */
+        uint32_t lock_delay_time:5;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} spi_mem_c_fsm_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_ena register
+ *  SPI0 interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
+         */
+        uint32_t slv_st_end_int_ena:1;
+        /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for spi_mem_c_C_MST_ST_END_INT interrupt.
+         */
+        uint32_t mst_st_end_int_ena:1;
+        /** ecc_err_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The enable bit for spi_mem_c_C_ECC_ERR_INT interrupt.
+         */
+        uint32_t ecc_err_int_ena:1;
+        /** pms_reject_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The enable bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
+         */
+        uint32_t pms_reject_int_ena:1;
+        /** axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
+         */
+        uint32_t axi_raddr_err_int_ena:1;
+        /** axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
+         */
+        uint32_t axi_wr_flash_err_int_ena:1;
+        /** axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0;
+         *  The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
+         */
+        uint32_t axi_waddr_err_int__ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} spi_mem_c_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  SPI0 interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
+         */
+        uint32_t slv_st_end_int_clr:1;
+        /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear bit for spi_mem_c_C_MST_ST_END_INT interrupt.
+         */
+        uint32_t mst_st_end_int_clr:1;
+        /** ecc_err_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The clear bit for spi_mem_c_C_ECC_ERR_INT interrupt.
+         */
+        uint32_t ecc_err_int_clr:1;
+        /** pms_reject_int_clr : WT; bitpos: [6]; default: 0;
+         *  The clear bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
+         */
+        uint32_t pms_reject_int_clr:1;
+        /** axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  The clear bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
+         */
+        uint32_t axi_raddr_err_int_clr:1;
+        /** axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The clear bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
+         */
+        uint32_t axi_wr_flash_err_int_clr:1;
+        /** axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0;
+         *  The clear bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
+         */
+        uint32_t axi_waddr_err_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} spi_mem_c_int_clr_reg_t;
+
+/** Type of int_raw register
+ *  SPI0 interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for spi_mem_c_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
+         *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
+         *  Others
+         */
+        uint32_t slv_st_end_int_raw:1;
+        /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for spi_mem_c_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
+         *  changed from non idle state to idle state. 0: Others.
+         */
+        uint32_t mst_st_end_int_raw:1;
+        /** ecc_err_int_raw : HRO; bitpos: [5]; default: 0;
+         *  The raw bit for spi_mem_c_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set
+         *  and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
+         *  of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_C_ECC_ERR_INT_NUM. When
+         *  SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is
+         *  triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
+         *  than spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and
+         *  SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+         *  of SPI0/1 ECC read external RAM and flash are equal or bigger than
+         *  spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN
+         *  are cleared, this bit will not be triggered.
+         */
+        uint32_t ecc_err_int_raw:1;
+        /** pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit for spi_mem_c_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
+         *  rejected. 0: Others.
+         */
+        uint32_t pms_reject_int_raw:1;
+        /** axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+         *  address is invalid by compared to MMU configuration. 0: Others.
+         */
+        uint32_t axi_raddr_err_int_raw:1;
+        /** axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0;
+         *  The raw bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
+         *  flash request is received. 0: Others.
+         */
+        uint32_t axi_wr_flash_err_int_raw:1;
+        /** axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0;
+         *  The raw bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+         *  address is invalid by compared to MMU configuration. 0: Others.
+         */
+        uint32_t axi_waddr_err_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} spi_mem_c_int_raw_reg_t;
+
+/** Type of int_st register
+ *  SPI0 interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** slv_st_end_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
+         */
+        uint32_t slv_st_end_int_st:1;
+        /** mst_st_end_int_st : RO; bitpos: [4]; default: 0;
+         *  The status bit for spi_mem_c_C_MST_ST_END_INT interrupt.
+         */
+        uint32_t mst_st_end_int_st:1;
+        /** ecc_err_int_st : HRO; bitpos: [5]; default: 0;
+         *  The status bit for spi_mem_c_C_ECC_ERR_INT interrupt.
+         */
+        uint32_t ecc_err_int_st:1;
+        /** pms_reject_int_st : RO; bitpos: [6]; default: 0;
+         *  The status bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
+         */
+        uint32_t pms_reject_int_st:1;
+        /** axi_raddr_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
+         */
+        uint32_t axi_raddr_err_int_st:1;
+        /** axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0;
+         *  The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
+         */
+        uint32_t axi_wr_flash_err_int_st:1;
+        /** axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0;
+         *  The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
+         */
+        uint32_t axi_waddr_err_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} spi_mem_c_int_st_reg_t;
+
+
+/** Group: PMS control and configuration registers */
+/** Type of fmem_pmsn_attr register
+ *  MSPI flash PMS section n attribute register
+ */
+typedef union {
+    struct {
+        /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1;
+         *  1: SPI1 flash PMS section n read accessible. 0: Not allowed.
+         */
+        uint32_t fmem_pmsn_rd_attr:1;
+        /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1;
+         *  1: SPI1 flash PMS section n write accessible. 0: Not allowed.
+         */
+        uint32_t fmem_pmsn_wr_attr:1;
+        /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
+         *  SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
+         *  section n is configured by registers SPI_MEM_C_FMEM__PMSn_ADDR_REG and
+         *  SPI_MEM_C_FMEM__PMSn_SIZE_REG.
+         */
+        uint32_t fmem_pmsn_ecc:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} spi_mem_c_fmem_pmsn_attr_reg_t;
+
+/** Type of fmem_pmsn_addr register
+ *  SPI1 flash PMS section n start address register
+ */
+typedef union {
+    struct {
+        /** fmem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0;
+         *  SPI1 flash PMS section n start address value
+         */
+        uint32_t fmem_pmsn_addr_s:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_c_fmem_pmsn_addr_reg_t;
+
+/** Type of fmem_pmsn_size register
+ *  SPI1 flash PMS section n start address register
+ */
+typedef union {
+    struct {
+        /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096;
+         *  SPI1 flash PMS section n address region is (SPI_MEM_C_FMEM__PMSn_ADDR_S,
+         *  SPI_MEM_C_FMEM__PMSn_ADDR_S + SPI_MEM_C_FMEM__PMSn_SIZE)
+         */
+        uint32_t fmem_pmsn_size:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} spi_mem_c_fmem_pmsn_size_reg_t;
+
+/** Type of smem_pmsn_attr register
+ *  SPI1 flash PMS section n start address register
+ */
+typedef union {
+    struct {
+        /** smem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1;
+         *  1: SPI1 external RAM PMS section n read accessible. 0: Not allowed.
+         */
+        uint32_t smem_pmsn_rd_attr:1;
+        /** smem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1;
+         *  1: SPI1 external RAM PMS section n write accessible. 0: Not allowed.
+         */
+        uint32_t smem_pmsn_wr_attr:1;
+        /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
+         *  SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The
+         *  external RAM PMS section n is configured by registers SPI_MEM_C_SMEM_PMSn_ADDR_REG and
+         *  SPI_MEM_C_SMEM_PMSn_SIZE_REG.
+         */
+        uint32_t smem_pmsn_ecc:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} spi_mem_c_smem_pmsn_attr_reg_t;
+
+/** Type of smem_pmsn_addr register
+ *  SPI1 external RAM PMS section n start address register
+ */
+typedef union {
+    struct {
+        /** smem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0;
+         *  SPI1 external RAM PMS section n start address value
+         */
+        uint32_t smem_pmsn_addr_s:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_c_smem_pmsn_addr_reg_t;
+
+/** Type of smem_pmsn_size register
+ *  SPI1 external RAM PMS section n start address register
+ */
+typedef union {
+    struct {
+        /** smem_pmsn_size : R/W; bitpos: [14:0]; default: 4096;
+         *  SPI1 external RAM PMS section n address region is (SPI_MEM_C_SMEM_PMSn_ADDR_S,
+         *  SPI_MEM_C_SMEM_PMSn_ADDR_S + SPI_MEM_C_SMEM_PMSn_SIZE)
+         */
+        uint32_t smem_pmsn_size:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} spi_mem_c_smem_pmsn_size_reg_t;
+
+/** Type of pms_reject register
+ *  SPI1 access reject register
+ */
+typedef union {
+    struct {
+        /** reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
+         *  This bits show the first SPI1 access error address. It is cleared by when
+         *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
+         */
+        uint32_t reject_addr:27;
+        /** pm_en : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to enable SPI0/1 transfer permission control function.
+         */
+        uint32_t pm_en:1;
+        /** pms_ld : R/SS/WTC; bitpos: [28]; default: 0;
+         *  1: SPI1 write access error. 0: No write access error. It is cleared by when
+         *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
+         */
+        uint32_t pms_ld:1;
+        /** pms_st : R/SS/WTC; bitpos: [29]; default: 0;
+         *  1: SPI1 read access error. 0: No read access error. It is cleared by when
+         *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
+         */
+        uint32_t pms_st:1;
+        /** pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0;
+         *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
+         *  cleared by when  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
+         */
+        uint32_t pms_multi_hit:1;
+        /** pms_ivd : R/SS/WTC; bitpos: [31]; default: 0;
+         *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
+         *  error. It is cleared by when  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
+         */
+        uint32_t pms_ivd:1;
+    };
+    uint32_t val;
+} spi_mem_c_pms_reject_reg_t;
+
+
+/** Group: MSPI ECC registers */
+/** Type of ecc_ctrl register
+ *  MSPI ECC control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** ecc_err_cnt : HRO; bitpos: [10:5]; default: 0;
+         *  This bits show the error times of MSPI ECC read. It is cleared by when
+         *  spi_mem_c_C_ECC_ERR_INT_CLR bit is set.
+         */
+        uint32_t ecc_err_cnt:6;
+        /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10;
+         *  Set the error times of MSPI ECC read to generate MSPI spi_mem_c_C_ECC_ERR_INT interrupt.
+         */
+        uint32_t fmem_ecc_err_int_num:6;
+        /** fmem_ecc_err_int_en : HRO; bitpos: [17]; default: 0;
+         *  Set this bit to calculate the error times of MSPI ECC read when accesses to flash.
+         */
+        uint32_t fmem_ecc_err_int_en:1;
+        /** fmem_page_size : R/W; bitpos: [19:18]; default: 0;
+         *  Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
+         *  1024 bytes. 3: 2048 bytes.
+         */
+        uint32_t fmem_page_size:2;
+        /** fmem_ecc_addr_en : HRO; bitpos: [20]; default: 0;
+         *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
+         *  ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit
+         *  should be 0. Otherwise, this bit should be 1.
+         */
+        uint32_t fmem_ecc_addr_en:1;
+        /** usr_ecc_addr_en : HRO; bitpos: [21]; default: 0;
+         *  Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.
+         */
+        uint32_t usr_ecc_addr_en:1;
+        uint32_t reserved_22:2;
+        /** ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1;
+         *  1: The error information in spi_mem_c_C_ECC_ERR_BITS and spi_mem_c_C_ECC_ERR_ADDR is
+         *  updated when there is an ECC error. 0: spi_mem_c_C_ECC_ERR_BITS and
+         *  spi_mem_c_C_ECC_ERR_ADDR record the first ECC error information.
+         */
+        uint32_t ecc_continue_record_err_en:1;
+        /** ecc_err_bits : HRO; bitpos: [31:25]; default: 0;
+         *  Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to
+         *  byte 0 bit 0 to byte 15 bit 7)
+         */
+        uint32_t ecc_err_bits:7;
+    };
+    uint32_t val;
+} spi_mem_c_ecc_ctrl_reg_t;
+
+/** Type of ecc_err_addr register
+ *  MSPI ECC error address register
+ */
+typedef union {
+    struct {
+        /** ecc_err_addr : HRO; bitpos: [26:0]; default: 0;
+         *  This bits show the first MSPI ECC error address. It is cleared by when
+         *  spi_mem_c_C_ECC_ERR_INT_CLR bit is set.
+         */
+        uint32_t ecc_err_addr:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_c_ecc_err_addr_reg_t;
+
+/** Type of smem_ecc_ctrl register
+ *  MSPI ECC control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:17;
+        /** smem_ecc_err_int_en : HRO; bitpos: [17]; default: 0;
+         *  Set this bit to calculate the error times of MSPI ECC read when accesses to
+         *  external RAM.
+         */
+        uint32_t smem_ecc_err_int_en:1;
+        /** smem_page_size : HRO; bitpos: [19:18]; default: 2;
+         *  Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes.
+         *  2: 1024 bytes. 3: 2048 bytes.
+         */
+        uint32_t smem_page_size:2;
+        /** smem_ecc_addr_en : HRO; bitpos: [20]; default: 0;
+         *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
+         *  ECC region or non-ECC region of external RAM. If there is no ECC region in external
+         *  RAM, this bit should be 0. Otherwise, this bit should be 1.
+         */
+        uint32_t smem_ecc_addr_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_mem_c_smem_ecc_ctrl_reg_t;
+
+
+/** Group: Status and state control registers */
+/** Type of smem_axi_addr_ctrl register
+ *  SPI0 AXI address control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** all_fifo_empty : RO; bitpos: [26]; default: 1;
+         *  The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
+         *  and SPI0 transfers are done. 0: Others.
+         */
+        uint32_t all_fifo_empty:1;
+        /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1;
+         *  1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.
+         */
+        uint32_t rdata_afifo_rempty:1;
+        /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1;
+         *  1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.
+         */
+        uint32_t raddr_afifo_rempty:1;
+        /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1;
+         *  1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.
+         */
+        uint32_t wdata_afifo_rempty:1;
+        /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1;
+         *  1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.
+         */
+        uint32_t wblen_afifo_rempty:1;
+        /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1;
+         *  This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and
+         *  RDATA_AFIFO are empty and spi0_mst_st is IDLE.
+         */
+        uint32_t all_axi_trans_afifo_empty:1;
+    };
+    uint32_t val;
+} spi_mem_c_smem_axi_addr_ctrl_reg_t;
+
+/** Type of axi_err_resp_en register
+ *  SPI0 AXI error response enable register
+ */
+typedef union {
+    struct {
+        /** aw_resp_en_mmu_vld : HRO; bitpos: [0]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu valid err in axi write trans.
+         */
+        uint32_t aw_resp_en_mmu_vld:1;
+        /** aw_resp_en_mmu_gid : HRO; bitpos: [1]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu gid err in axi write trans.
+         */
+        uint32_t aw_resp_en_mmu_gid:1;
+        /** aw_resp_en_axi_size : HRO; bitpos: [2]; default: 0;
+         *  Set this bit  to enable AXI response function for axi size err in axi write trans.
+         */
+        uint32_t aw_resp_en_axi_size:1;
+        /** aw_resp_en_axi_flash : HRO; bitpos: [3]; default: 0;
+         *  Set this bit  to enable AXI response function for axi flash err in axi write trans.
+         */
+        uint32_t aw_resp_en_axi_flash:1;
+        /** aw_resp_en_mmu_ecc : HRO; bitpos: [4]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu ecc err in axi write trans.
+         */
+        uint32_t aw_resp_en_mmu_ecc:1;
+        /** aw_resp_en_mmu_sens : HRO; bitpos: [5]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu sens in err axi write trans.
+         */
+        uint32_t aw_resp_en_mmu_sens:1;
+        /** aw_resp_en_axi_wstrb : HRO; bitpos: [6]; default: 0;
+         *  Set this bit  to enable AXI response function for axi wstrb err in axi write trans.
+         */
+        uint32_t aw_resp_en_axi_wstrb:1;
+        /** ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu valid err in axi read trans.
+         */
+        uint32_t ar_resp_en_mmu_vld:1;
+        /** ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu gid err in axi read trans.
+         */
+        uint32_t ar_resp_en_mmu_gid:1;
+        /** ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu ecc err in axi read trans.
+         */
+        uint32_t ar_resp_en_mmu_ecc:1;
+        /** ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu sensitive err in axi read
+         *  trans.
+         */
+        uint32_t ar_resp_en_mmu_sens:1;
+        /** ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0;
+         *  Set this bit  to enable AXI response function for axi size err in axi read trans.
+         */
+        uint32_t ar_resp_en_axi_size:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} spi_mem_c_axi_err_resp_en_reg_t;
+
+
+/** Group: Flash timing registers */
+/** Type of timing_cali register
+ *  SPI0 flash timing calibration register
+ */
+typedef union {
+    struct {
+        /** timing_clk_ena : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable timing adjust clock for all reading operations.
+         */
+        uint32_t timing_clk_ena:1;
+        /** timing_cali : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable timing auto-calibration for all reading operations.
+         */
+        uint32_t timing_cali:1;
+        /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0;
+         *  add extra dummy spi clock cycle length for spi clock calibration.
+         */
+        uint32_t extra_dummy_cyclelen:3;
+        /** dll_timing_cali : HRO; bitpos: [5]; default: 0;
+         *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
+         *  flash.
+         */
+        uint32_t dll_timing_cali:1;
+        /** timing_cali_update : WT; bitpos: [6]; default: 0;
+         *  Set this bit to update delay mode, delay num and extra dummy in MSPI.
+         */
+        uint32_t timing_cali_update:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} spi_mem_c_timing_cali_reg_t;
+
+/** Type of din_mode register
+ *  MSPI flash input timing delay mode control register
+ */
+typedef union {
+    struct {
+        /** din0_mode : R/W; bitpos: [2:0]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t din0_mode:3;
+        /** din1_mode : R/W; bitpos: [5:3]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t din1_mode:3;
+        /** din2_mode : R/W; bitpos: [8:6]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t din2_mode:3;
+        /** din3_mode : R/W; bitpos: [11:9]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t din3_mode:3;
+        /** din4_mode : R/W; bitpos: [14:12]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk
+         */
+        uint32_t din4_mode:3;
+        /** din5_mode : R/W; bitpos: [17:15]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk
+         */
+        uint32_t din5_mode:3;
+        /** din6_mode : R/W; bitpos: [20:18]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk
+         */
+        uint32_t din6_mode:3;
+        /** din7_mode : R/W; bitpos: [23:21]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk
+         */
+        uint32_t din7_mode:3;
+        /** dins_mode : R/W; bitpos: [26:24]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk
+         */
+        uint32_t dins_mode:3;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_c_din_mode_reg_t;
+
+/** Type of din_num register
+ *  MSPI flash input timing delay number control register
+ */
+typedef union {
+    struct {
+        /** din0_num : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t din0_num:2;
+        /** din1_num : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t din1_num:2;
+        /** din2_num : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t din2_num:2;
+        /** din3_num : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t din3_num:2;
+        /** din4_num : R/W; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t din4_num:2;
+        /** din5_num : R/W; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t din5_num:2;
+        /** din6_num : R/W; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t din6_num:2;
+        /** din7_num : R/W; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t din7_num:2;
+        /** dins_num : R/W; bitpos: [17:16]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t dins_num:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_mem_c_din_num_reg_t;
+
+/** Type of dout_mode register
+ *  MSPI flash output timing adjustment control register
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [0]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t dout0_mode:1;
+        /** dout1_mode : R/W; bitpos: [1]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t dout1_mode:1;
+        /** dout2_mode : R/W; bitpos: [2]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t dout2_mode:1;
+        /** dout3_mode : R/W; bitpos: [3]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t dout3_mode:1;
+        /** dout4_mode : R/W; bitpos: [4]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the spi_clk
+         */
+        uint32_t dout4_mode:1;
+        /** dout5_mode : R/W; bitpos: [5]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the spi_clk
+         */
+        uint32_t dout5_mode:1;
+        /** dout6_mode : R/W; bitpos: [6]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the spi_clk
+         */
+        uint32_t dout6_mode:1;
+        /** dout7_mode : R/W; bitpos: [7]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the spi_clk
+         */
+        uint32_t dout7_mode:1;
+        /** douts_mode : R/W; bitpos: [8]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the spi_clk
+         */
+        uint32_t douts_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_mem_c_dout_mode_reg_t;
+
+
+/** Group: External RAM timing registers */
+/** Type of smem_timing_cali register
+ *  MSPI external RAM timing calibration register
+ */
+typedef union {
+    struct {
+        /** smem_timing_clk_ena : HRO; bitpos: [0]; default: 1;
+         *  For sram, the bit is used to enable timing adjust clock for all reading operations.
+         */
+        uint32_t smem_timing_clk_ena:1;
+        /** smem_timing_cali : HRO; bitpos: [1]; default: 0;
+         *  For sram, the bit is used to enable timing auto-calibration for all reading
+         *  operations.
+         */
+        uint32_t smem_timing_cali:1;
+        /** smem_extra_dummy_cyclelen : HRO; bitpos: [4:2]; default: 0;
+         *  For sram, add extra dummy spi clock cycle length for spi clock calibration.
+         */
+        uint32_t smem_extra_dummy_cyclelen:3;
+        /** smem_dll_timing_cali : HRO; bitpos: [5]; default: 0;
+         *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
+         *  EXT_RAM.
+         */
+        uint32_t smem_dll_timing_cali:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} spi_mem_c_smem_timing_cali_reg_t;
+
+/** Type of smem_din_mode register
+ *  MSPI external RAM input timing delay mode control register
+ */
+typedef union {
+    struct {
+        /** smem_din0_mode : HRO; bitpos: [2:0]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din0_mode:3;
+        /** smem_din1_mode : HRO; bitpos: [5:3]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din1_mode:3;
+        /** smem_din2_mode : HRO; bitpos: [8:6]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din2_mode:3;
+        /** smem_din3_mode : HRO; bitpos: [11:9]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din3_mode:3;
+        /** smem_din4_mode : HRO; bitpos: [14:12]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din4_mode:3;
+        /** smem_din5_mode : HRO; bitpos: [17:15]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din5_mode:3;
+        /** smem_din6_mode : HRO; bitpos: [20:18]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din6_mode:3;
+        /** smem_din7_mode : HRO; bitpos: [23:21]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din7_mode:3;
+        /** smem_dins_mode : HRO; bitpos: [26:24]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_dins_mode:3;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_c_smem_din_mode_reg_t;
+
+/** Type of smem_din_num register
+ *  MSPI external RAM input timing delay number control register
+ */
+typedef union {
+    struct {
+        /** smem_din0_num : HRO; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din0_num:2;
+        /** smem_din1_num : HRO; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din1_num:2;
+        /** smem_din2_num : HRO; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din2_num:2;
+        /** smem_din3_num : HRO; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din3_num:2;
+        /** smem_din4_num : HRO; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din4_num:2;
+        /** smem_din5_num : HRO; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din5_num:2;
+        /** smem_din6_num : HRO; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din6_num:2;
+        /** smem_din7_num : HRO; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din7_num:2;
+        /** smem_dins_num : HRO; bitpos: [17:16]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_dins_num:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_mem_c_smem_din_num_reg_t;
+
+/** Type of smem_dout_mode register
+ *  MSPI external RAM output timing adjustment control register
+ */
+typedef union {
+    struct {
+        /** smem_dout0_mode : HRO; bitpos: [0]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout0_mode:1;
+        /** smem_dout1_mode : HRO; bitpos: [1]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout1_mode:1;
+        /** smem_dout2_mode : HRO; bitpos: [2]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout2_mode:1;
+        /** smem_dout3_mode : HRO; bitpos: [3]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout3_mode:1;
+        /** smem_dout4_mode : HRO; bitpos: [4]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout4_mode:1;
+        /** smem_dout5_mode : HRO; bitpos: [5]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout5_mode:1;
+        /** smem_dout6_mode : HRO; bitpos: [6]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout6_mode:1;
+        /** smem_dout7_mode : HRO; bitpos: [7]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout7_mode:1;
+        /** smem_douts_mode : HRO; bitpos: [8]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_douts_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_mem_c_smem_dout_mode_reg_t;
+
+
+/** Group: Manual Encryption plaintext Memory */
+/** Type of xts_plain_base register
+ *  The base address of the memory that stores plaintext in Manual Encryption
+ */
+typedef union {
+    struct {
+        /** xts_plain : R/W; bitpos: [31:0]; default: 0;
+         *  This field is only used to generate include file in c case. This field is useless.
+         *  Please do not use this field.
+         */
+        uint32_t xts_plain:32;
+    };
+    uint32_t val;
+} spi_mem_c_xts_plain_base_reg_t;
+
+
+/** Group: Manual Encryption configuration registers */
+/** Type of xts_linesize register
+ *  Manual Encryption Line-Size register
+ */
+typedef union {
+    struct {
+        /** xts_linesize : R/W; bitpos: [1:0]; default: 0;
+         *  This bits stores the line-size parameter which will be used in manual encryption
+         *  calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1:
+         *  32-bytes, 2: 64-bytes, 3:reserved.
+         */
+        uint32_t xts_linesize:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} spi_mem_c_xts_linesize_reg_t;
+
+/** Type of xts_destination register
+ *  Manual Encryption destination register
+ */
+typedef union {
+    struct {
+        /** xts_destination : R/W; bitpos: [0]; default: 0;
+         *  This bit stores the destination parameter which will be used in manual encryption
+         *  calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.
+         */
+        uint32_t xts_destination:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi_mem_c_xts_destination_reg_t;
+
+/** Type of xts_physical_address register
+ *  Manual Encryption physical address register
+ */
+typedef union {
+    struct {
+        /** xts_physical_address : R/W; bitpos: [25:0]; default: 0;
+         *  This bits stores the physical-address parameter which will be used in manual
+         *  encryption calculation. This value should aligned with byte number decided by
+         *  line-size parameter.
+         */
+        uint32_t xts_physical_address:26;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} spi_mem_c_xts_physical_address_reg_t;
+
+
+/** Group: Manual Encryption control and status registers */
+/** Type of xts_trigger register
+ *  Manual Encryption physical address register
+ */
+typedef union {
+    struct {
+        /** xts_trigger : WT; bitpos: [0]; default: 0;
+         *  Set this bit to trigger the process of manual encryption calculation. This action
+         *  should only be asserted when manual encryption status is 0. After this action,
+         *  manual encryption status becomes 1. After calculation is done, manual encryption
+         *  status becomes 2.
+         */
+        uint32_t xts_trigger:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi_mem_c_xts_trigger_reg_t;
+
+/** Type of xts_release register
+ *  Manual Encryption physical address register
+ */
+typedef union {
+    struct {
+        /** xts_release : WT; bitpos: [0]; default: 0;
+         *  Set this bit to release encrypted result to mspi. This action should only be
+         *  asserted when manual encryption status is 2. After this action, manual encryption
+         *  status will become 3.
+         */
+        uint32_t xts_release:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi_mem_c_xts_release_reg_t;
+
+/** Type of xts_destroy register
+ *  Manual Encryption physical address register
+ */
+typedef union {
+    struct {
+        /** xts_destroy : WT; bitpos: [0]; default: 0;
+         *  Set this bit to destroy encrypted result. This action should be asserted only when
+         *  manual encryption status is 3. After this action, manual encryption status will
+         *  become 0.
+         */
+        uint32_t xts_destroy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi_mem_c_xts_destroy_reg_t;
+
+/** Type of xts_state register
+ *  Manual Encryption physical address register
+ */
+typedef union {
+    struct {
+        /** xts_state : RO; bitpos: [1:0]; default: 0;
+         *  This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
+         *  calculation, 2: encryption calculation is done but the encrypted result is
+         *  invisible to mspi, 3: the encrypted result is visible to mspi.
+         */
+        uint32_t xts_state:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} spi_mem_c_xts_state_reg_t;
+
+
+/** Group: Manual Encryption version control register */
+/** Type of xts_date register
+ *  Manual Encryption version register
+ */
+typedef union {
+    struct {
+        /** xts_date : R/W; bitpos: [29:0]; default: 538972176;
+         *  This bits stores the last modified-time of manual encryption feature.
+         */
+        uint32_t xts_date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_mem_c_xts_date_reg_t;
+
+
+/** Group: MMU access registers */
+/** Type of mmu_item_content register
+ *  MSPI-MMU item content register
+ */
+typedef union {
+    struct {
+        /** mmu_item_content : R/W; bitpos: [31:0]; default: 892;
+         *  MSPI-MMU item content
+         */
+        uint32_t mmu_item_content:32;
+    };
+    uint32_t val;
+} spi_mem_c_mmu_item_content_reg_t;
+
+/** Type of mmu_item_index register
+ *  MSPI-MMU item index register
+ */
+typedef union {
+    struct {
+        /** mmu_item_index : R/W; bitpos: [31:0]; default: 0;
+         *  MSPI-MMU item index
+         */
+        uint32_t mmu_item_index:32;
+    };
+    uint32_t val;
+} spi_mem_c_mmu_item_index_reg_t;
+
+
+/** Group: MMU power control and configuration registers */
+/** Type of mmu_power_ctrl register
+ *  MSPI MMU power control register
+ */
+typedef union {
+    struct {
+        /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable mmu-memory clock force on
+         */
+        uint32_t mmu_mem_force_on:1;
+        /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to force mmu-memory powerdown
+         */
+        uint32_t mmu_mem_force_pd:1;
+        /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to force mmu-memory powerup, in this case, the power should also be
+         *  controlled by rtc.
+         */
+        uint32_t mmu_mem_force_pu:1;
+        /** mmu_page_size : R/W; bitpos: [4:3]; default: 0;
+         *  0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8
+         */
+        uint32_t mmu_page_size:2;
+        uint32_t reserved_5:11;
+        /** aux_ctrl : HRO; bitpos: [29:16]; default: 4896;
+         *  MMU PSRAM aux control register
+         */
+        uint32_t aux_ctrl:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_mem_c_mmu_power_ctrl_reg_t;
+
+
+/** Group: External mem cryption DPA registers */
+/** Type of dpa_ctrl register
+ *  SPI memory cryption DPA register
+ */
+typedef union {
+    struct {
+        /** crypt_security_level : R/W; bitpos: [2:0]; default: 7;
+         *  Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7:
+         *  The bigger the number is, the more secure the cryption is. (Note that the
+         *  performance of cryption will decrease together with this number increasing)
+         */
+        uint32_t crypt_security_level:3;
+        /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1;
+         *  Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the
+         *  calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that
+         *  using key 1.
+         */
+        uint32_t crypt_calc_d_dpa_en:1;
+        /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0;
+         *  1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and
+         *  SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.
+         */
+        uint32_t crypt_dpa_select_register:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} spi_mem_c_dpa_ctrl_reg_t;
+
+
+/** Group: Version control register */
+/** Type of date register
+ *  SPI0 version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36712560;
+         *  SPI0 register version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi_mem_c_date_reg_t;
+
+
+typedef struct spi_mem_c_dev_s {
+    volatile spi_mem_c_cmd_reg_t cmd;
+    uint32_t reserved_004;
+    volatile spi_mem_c_ctrl_reg_t ctrl;
+    volatile spi_mem_c_ctrl1_reg_t ctrl1;
+    volatile spi_mem_c_ctrl2_reg_t ctrl2;
+    volatile spi_mem_c_clock_reg_t clock;
+    volatile spi_mem_c_user_reg_t user;
+    volatile spi_mem_c_user1_reg_t user1;
+    volatile spi_mem_c_user2_reg_t user2;
+    uint32_t reserved_024[4];
+    volatile spi_mem_c_misc_reg_t misc;
+    uint32_t reserved_038;
+    volatile spi_mem_c_cache_fctrl_reg_t cache_fctrl;
+    uint32_t reserved_040;
+    volatile spi_mem_c_sram_cmd_reg_t sram_cmd;
+    uint32_t reserved_048[3];
+    volatile spi_mem_c_fsm_reg_t fsm;
+    uint32_t reserved_058[26];
+    volatile spi_mem_c_int_ena_reg_t int_ena;
+    volatile spi_mem_c_int_clr_reg_t int_clr;
+    volatile spi_mem_c_int_raw_reg_t int_raw;
+    volatile spi_mem_c_int_st_reg_t int_st;
+    uint32_t reserved_0d0;
+    volatile spi_mem_c_ddr_reg_t ddr;
+    volatile spi_mem_c_smem_ddr_reg_t smem_ddr;
+    uint32_t reserved_0dc[9];
+    volatile spi_mem_c_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4];
+    volatile spi_mem_c_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4];
+    volatile spi_mem_c_fmem_pmsn_size_reg_t fmem_pmsn_size[4];
+    volatile spi_mem_c_smem_pmsn_attr_reg_t smem_pmsn_attr[4];
+    volatile spi_mem_c_smem_pmsn_addr_reg_t smem_pmsn_addr[4];
+    volatile spi_mem_c_smem_pmsn_size_reg_t smem_pmsn_size[4];
+    uint32_t reserved_160;
+    volatile spi_mem_c_pms_reject_reg_t pms_reject;
+    volatile spi_mem_c_ecc_ctrl_reg_t ecc_ctrl;
+    volatile spi_mem_c_ecc_err_addr_reg_t ecc_err_addr;
+    volatile spi_mem_c_axi_err_addr_reg_t axi_err_addr;
+    volatile spi_mem_c_smem_ecc_ctrl_reg_t smem_ecc_ctrl;
+    volatile spi_mem_c_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl;
+    volatile spi_mem_c_axi_err_resp_en_reg_t axi_err_resp_en;
+    volatile spi_mem_c_timing_cali_reg_t timing_cali;
+    volatile spi_mem_c_din_mode_reg_t din_mode;
+    volatile spi_mem_c_din_num_reg_t din_num;
+    volatile spi_mem_c_dout_mode_reg_t dout_mode;
+    volatile spi_mem_c_smem_timing_cali_reg_t smem_timing_cali;
+    volatile spi_mem_c_smem_din_mode_reg_t smem_din_mode;
+    volatile spi_mem_c_smem_din_num_reg_t smem_din_num;
+    volatile spi_mem_c_smem_dout_mode_reg_t smem_dout_mode;
+    volatile spi_mem_c_smem_ac_reg_t smem_ac;
+    uint32_t reserved_1a4[23];
+    volatile spi_mem_c_clock_gate_reg_t clock_gate;
+    uint32_t reserved_204[63];
+    volatile spi_mem_c_xts_plain_base_reg_t xts_plain_base;
+    uint32_t reserved_304[15];
+    volatile spi_mem_c_xts_linesize_reg_t xts_linesize;
+    volatile spi_mem_c_xts_destination_reg_t xts_destination;
+    volatile spi_mem_c_xts_physical_address_reg_t xts_physical_address;
+    volatile spi_mem_c_xts_trigger_reg_t xts_trigger;
+    volatile spi_mem_c_xts_release_reg_t xts_release;
+    volatile spi_mem_c_xts_destroy_reg_t xts_destroy;
+    volatile spi_mem_c_xts_state_reg_t xts_state;
+    volatile spi_mem_c_xts_date_reg_t xts_date;
+    uint32_t reserved_360[7];
+    volatile spi_mem_c_mmu_item_content_reg_t mmu_item_content;
+    volatile spi_mem_c_mmu_item_index_reg_t mmu_item_index;
+    volatile spi_mem_c_mmu_power_ctrl_reg_t mmu_power_ctrl;
+    volatile spi_mem_c_dpa_ctrl_reg_t dpa_ctrl;
+    uint32_t reserved_38c[28];
+    volatile spi_mem_c_date_reg_t date;
+} spi_mem_c_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_mem_c_dev_t) == 0x400, "Invalid size of spi_mem_c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h
new file mode 100644
index 0000000000..cb15d5b07d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h
@@ -0,0 +1,3528 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI_MEM_S_CMD_REG register
+ *  SPI0 FSM status register
+ */
+#define SPI_MEM_S_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x0)
+/** SPI_MEM_S_MST_ST : RO; bitpos: [3:0]; default: 0;
+ *  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT ,
+ *  2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent
+ *  data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
+ */
+#define SPI_MEM_S_MST_ST    0x0000000FU
+#define SPI_MEM_S_MST_ST_M  (SPI_MEM_S_MST_ST_V << SPI_MEM_S_MST_ST_S)
+#define SPI_MEM_S_MST_ST_V  0x0000000FU
+#define SPI_MEM_S_MST_ST_S  0
+/** SPI_MEM_S_SLV_ST : RO; bitpos: [7:4]; default: 0;
+ *  The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state,
+ *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
+ *  6:write data state, 7: done state, 8: read data end state.
+ */
+#define SPI_MEM_S_SLV_ST    0x0000000FU
+#define SPI_MEM_S_SLV_ST_M  (SPI_MEM_S_SLV_ST_V << SPI_MEM_S_SLV_ST_S)
+#define SPI_MEM_S_SLV_ST_V  0x0000000FU
+#define SPI_MEM_S_SLV_ST_S  4
+/** SPI_MEM_S_USR : HRO; bitpos: [18]; default: 0;
+ *  SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared.  An operation
+ *  will be triggered when the bit is set. The bit will be cleared once the operation
+ *  done.1: enable 0: disable.
+ */
+#define SPI_MEM_S_USR    (BIT(18))
+#define SPI_MEM_S_USR_M  (SPI_MEM_S_USR_V << SPI_MEM_S_USR_S)
+#define SPI_MEM_S_USR_V  0x00000001U
+#define SPI_MEM_S_USR_S  18
+
+/** SPI_MEM_S_CTRL_REG register
+ *  SPI0 control register.
+ */
+#define SPI_MEM_S_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x8)
+/** SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0;
+ *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
+ *  of SPI_DQS is output by the MSPI controller.
+ */
+#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
+#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_S)
+#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_S  0
+/** SPI_MEM_S_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0;
+ *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
+ *  of SPI_IO[7:0] is output by the MSPI controller.
+ */
+#define SPI_MEM_S_WDUMMY_ALWAYS_OUT    (BIT(1))
+#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_S_WDUMMY_ALWAYS_OUT_V << SPI_MEM_S_WDUMMY_ALWAYS_OUT_S)
+#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_S  1
+/** SPI_MEM_S_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
+ *  In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is
+ *  output by the MSPI controller in the first half part of dummy phase. It is used to
+ *  mask invalid SPI_DQS in the half part of dummy phase.
+ */
+#define SPI_MEM_S_FDUMMY_RIN    (BIT(2))
+#define SPI_MEM_S_FDUMMY_RIN_M  (SPI_MEM_S_FDUMMY_RIN_V << SPI_MEM_S_FDUMMY_RIN_S)
+#define SPI_MEM_S_FDUMMY_RIN_V  0x00000001U
+#define SPI_MEM_S_FDUMMY_RIN_S  2
+/** SPI_MEM_S_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
+ *  In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is
+ *  output by the MSPI controller in the second half part of dummy phase. It is used to
+ *  pre-drive flash.
+ */
+#define SPI_MEM_S_FDUMMY_WOUT    (BIT(3))
+#define SPI_MEM_S_FDUMMY_WOUT_M  (SPI_MEM_S_FDUMMY_WOUT_V << SPI_MEM_S_FDUMMY_WOUT_S)
+#define SPI_MEM_S_FDUMMY_WOUT_V  0x00000001U
+#define SPI_MEM_S_FDUMMY_WOUT_S  3
+/** SPI_MEM_S_FDOUT_OCT : R/W; bitpos: [4]; default: 0;
+ *  Apply 8 signals during write-data phase 1:enable 0: disable
+ */
+#define SPI_MEM_S_FDOUT_OCT    (BIT(4))
+#define SPI_MEM_S_FDOUT_OCT_M  (SPI_MEM_S_FDOUT_OCT_V << SPI_MEM_S_FDOUT_OCT_S)
+#define SPI_MEM_S_FDOUT_OCT_V  0x00000001U
+#define SPI_MEM_S_FDOUT_OCT_S  4
+/** SPI_MEM_S_FDIN_OCT : R/W; bitpos: [5]; default: 0;
+ *  Apply 8 signals during read-data phase 1:enable 0: disable
+ */
+#define SPI_MEM_S_FDIN_OCT    (BIT(5))
+#define SPI_MEM_S_FDIN_OCT_M  (SPI_MEM_S_FDIN_OCT_V << SPI_MEM_S_FDIN_OCT_S)
+#define SPI_MEM_S_FDIN_OCT_V  0x00000001U
+#define SPI_MEM_S_FDIN_OCT_S  5
+/** SPI_MEM_S_FADDR_OCT : R/W; bitpos: [6]; default: 0;
+ *  Apply 8 signals during address phase 1:enable 0: disable
+ */
+#define SPI_MEM_S_FADDR_OCT    (BIT(6))
+#define SPI_MEM_S_FADDR_OCT_M  (SPI_MEM_S_FADDR_OCT_V << SPI_MEM_S_FADDR_OCT_S)
+#define SPI_MEM_S_FADDR_OCT_V  0x00000001U
+#define SPI_MEM_S_FADDR_OCT_S  6
+/** SPI_MEM_S_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
+ *  Apply 4 signals during command phase 1:enable 0: disable
+ */
+#define SPI_MEM_S_FCMD_QUAD    (BIT(8))
+#define SPI_MEM_S_FCMD_QUAD_M  (SPI_MEM_S_FCMD_QUAD_V << SPI_MEM_S_FCMD_QUAD_S)
+#define SPI_MEM_S_FCMD_QUAD_V  0x00000001U
+#define SPI_MEM_S_FCMD_QUAD_S  8
+/** SPI_MEM_S_FCMD_OCT : R/W; bitpos: [9]; default: 0;
+ *  Apply 8 signals during command phase 1:enable 0: disable
+ */
+#define SPI_MEM_S_FCMD_OCT    (BIT(9))
+#define SPI_MEM_S_FCMD_OCT_M  (SPI_MEM_S_FCMD_OCT_V << SPI_MEM_S_FCMD_OCT_S)
+#define SPI_MEM_S_FCMD_OCT_V  0x00000001U
+#define SPI_MEM_S_FCMD_OCT_S  9
+/** SPI_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
+ *  This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, SPI_MEM_S_FREAD_QOUT
+ *  and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_FASTRD_MODE    (BIT(13))
+#define SPI_MEM_S_FASTRD_MODE_M  (SPI_MEM_S_FASTRD_MODE_V << SPI_MEM_S_FASTRD_MODE_S)
+#define SPI_MEM_S_FASTRD_MODE_V  0x00000001U
+#define SPI_MEM_S_FASTRD_MODE_S  13
+/** SPI_MEM_S_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+ *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_FREAD_DUAL    (BIT(14))
+#define SPI_MEM_S_FREAD_DUAL_M  (SPI_MEM_S_FREAD_DUAL_V << SPI_MEM_S_FREAD_DUAL_S)
+#define SPI_MEM_S_FREAD_DUAL_V  0x00000001U
+#define SPI_MEM_S_FREAD_DUAL_S  14
+/** SPI_MEM_S_Q_POL : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to set MISO line polarity, 1: high 0, low
+ */
+#define SPI_MEM_S_Q_POL    (BIT(18))
+#define SPI_MEM_S_Q_POL_M  (SPI_MEM_S_Q_POL_V << SPI_MEM_S_Q_POL_S)
+#define SPI_MEM_S_Q_POL_V  0x00000001U
+#define SPI_MEM_S_Q_POL_S  18
+/** SPI_MEM_S_D_POL : R/W; bitpos: [19]; default: 1;
+ *  The bit is used to set MOSI line polarity, 1: high 0, low
+ */
+#define SPI_MEM_S_D_POL    (BIT(19))
+#define SPI_MEM_S_D_POL_M  (SPI_MEM_S_D_POL_V << SPI_MEM_S_D_POL_S)
+#define SPI_MEM_S_D_POL_V  0x00000001U
+#define SPI_MEM_S_D_POL_S  19
+/** SPI_MEM_S_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
+ *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_FREAD_QUAD    (BIT(20))
+#define SPI_MEM_S_FREAD_QUAD_M  (SPI_MEM_S_FREAD_QUAD_V << SPI_MEM_S_FREAD_QUAD_S)
+#define SPI_MEM_S_FREAD_QUAD_V  0x00000001U
+#define SPI_MEM_S_FREAD_QUAD_S  20
+/** SPI_MEM_S_WP_REG : R/W; bitpos: [21]; default: 1;
+ *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
+ */
+#define SPI_MEM_S_WP_REG    (BIT(21))
+#define SPI_MEM_S_WP_REG_M  (SPI_MEM_S_WP_REG_V << SPI_MEM_S_WP_REG_S)
+#define SPI_MEM_S_WP_REG_V  0x00000001U
+#define SPI_MEM_S_WP_REG_S  21
+/** SPI_MEM_S_FREAD_DIO : R/W; bitpos: [23]; default: 0;
+ *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
+ *  0: disable.
+ */
+#define SPI_MEM_S_FREAD_DIO    (BIT(23))
+#define SPI_MEM_S_FREAD_DIO_M  (SPI_MEM_S_FREAD_DIO_V << SPI_MEM_S_FREAD_DIO_S)
+#define SPI_MEM_S_FREAD_DIO_V  0x00000001U
+#define SPI_MEM_S_FREAD_DIO_S  23
+/** SPI_MEM_S_FREAD_QIO : R/W; bitpos: [24]; default: 0;
+ *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
+ *  0: disable.
+ */
+#define SPI_MEM_S_FREAD_QIO    (BIT(24))
+#define SPI_MEM_S_FREAD_QIO_M  (SPI_MEM_S_FREAD_QIO_V << SPI_MEM_S_FREAD_QIO_S)
+#define SPI_MEM_S_FREAD_QIO_V  0x00000001U
+#define SPI_MEM_S_FREAD_QIO_S  24
+/** SPI_MEM_S_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0;
+ *  When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
+ *  1. 0: Others.
+ */
+#define SPI_MEM_S_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_S_DQS_IE_ALWAYS_ON_M  (SPI_MEM_S_DQS_IE_ALWAYS_ON_V << SPI_MEM_S_DQS_IE_ALWAYS_ON_S)
+#define SPI_MEM_S_DQS_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_S_DQS_IE_ALWAYS_ON_S  30
+/** SPI_MEM_S_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1;
+ *  When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are
+ *  always 1. 0: Others.
+ */
+#define SPI_MEM_S_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_S_DATA_IE_ALWAYS_ON_M  (SPI_MEM_S_DATA_IE_ALWAYS_ON_V << SPI_MEM_S_DATA_IE_ALWAYS_ON_S)
+#define SPI_MEM_S_DATA_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_S_DATA_IE_ALWAYS_ON_S  31
+
+/** SPI_MEM_S_CTRL1_REG register
+ *  SPI0 control1 register.
+ */
+#define SPI_MEM_S_CTRL1_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc)
+/** SPI_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+ *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+ *  SPI clock is always on.
+ */
+#define SPI_MEM_S_CLK_MODE    0x00000003U
+#define SPI_MEM_S_CLK_MODE_M  (SPI_MEM_S_CLK_MODE_V << SPI_MEM_S_CLK_MODE_S)
+#define SPI_MEM_S_CLK_MODE_V  0x00000003U
+#define SPI_MEM_S_CLK_MODE_S  0
+/** SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1;
+ *  1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply
+ *  the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.
+ */
+#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
+#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_M  (SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_V << SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_S)
+#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_V  0x00000001U
+#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_S  21
+/** SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1;
+ *  1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.
+ */
+#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
+#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_M  (SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S)
+#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V  0x00000001U
+#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S  22
+/** SPI_MEM_S_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1;
+ *  1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0:
+ *  Reply AXI read data to AXI bus when all the read data is available.
+ */
+#define SPI_MEM_S_AXI_RDATA_BACK_FAST    (BIT(23))
+#define SPI_MEM_S_AXI_RDATA_BACK_FAST_M  (SPI_MEM_S_AXI_RDATA_BACK_FAST_V << SPI_MEM_S_AXI_RDATA_BACK_FAST_S)
+#define SPI_MEM_S_AXI_RDATA_BACK_FAST_V  0x00000001U
+#define SPI_MEM_S_AXI_RDATA_BACK_FAST_S  23
+/** SPI_MEM_S_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0;
+ *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
+ *  when there is a ECC error in AXI read data. The ECC error information is recorded
+ *  in SPI_MEM_S_ECC_ERR_ADDR_REG.
+ */
+#define SPI_MEM_S_RRESP_ECC_ERR_EN    (BIT(24))
+#define SPI_MEM_S_RRESP_ECC_ERR_EN_M  (SPI_MEM_S_RRESP_ECC_ERR_EN_V << SPI_MEM_S_RRESP_ECC_ERR_EN_S)
+#define SPI_MEM_S_RRESP_ECC_ERR_EN_V  0x00000001U
+#define SPI_MEM_S_RRESP_ECC_ERR_EN_S  24
+/** SPI_MEM_S_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to enable AXI Read Splice-transfer.
+ */
+#define SPI_MEM_S_AR_SPLICE_EN    (BIT(25))
+#define SPI_MEM_S_AR_SPLICE_EN_M  (SPI_MEM_S_AR_SPLICE_EN_V << SPI_MEM_S_AR_SPLICE_EN_S)
+#define SPI_MEM_S_AR_SPLICE_EN_V  0x00000001U
+#define SPI_MEM_S_AR_SPLICE_EN_S  25
+/** SPI_MEM_S_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to enable AXI Write Splice-transfer.
+ */
+#define SPI_MEM_S_AW_SPLICE_EN    (BIT(26))
+#define SPI_MEM_S_AW_SPLICE_EN_M  (SPI_MEM_S_AW_SPLICE_EN_V << SPI_MEM_S_AW_SPLICE_EN_S)
+#define SPI_MEM_S_AW_SPLICE_EN_V  0x00000001U
+#define SPI_MEM_S_AW_SPLICE_EN_S  26
+/** SPI_MEM_S_RAM0_EN : HRO; bitpos: [27]; default: 1;
+ *  When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be
+ *  accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1
+ *  will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
+ *  accessed at the same time.
+ */
+#define SPI_MEM_S_RAM0_EN    (BIT(27))
+#define SPI_MEM_S_RAM0_EN_M  (SPI_MEM_S_RAM0_EN_V << SPI_MEM_S_RAM0_EN_S)
+#define SPI_MEM_S_RAM0_EN_V  0x00000001U
+#define SPI_MEM_S_RAM0_EN_S  27
+/** SPI_MEM_S_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0;
+ *  Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the
+ *  same time.
+ */
+#define SPI_MEM_S_DUAL_RAM_EN    (BIT(28))
+#define SPI_MEM_S_DUAL_RAM_EN_M  (SPI_MEM_S_DUAL_RAM_EN_V << SPI_MEM_S_DUAL_RAM_EN_S)
+#define SPI_MEM_S_DUAL_RAM_EN_V  0x00000001U
+#define SPI_MEM_S_DUAL_RAM_EN_S  28
+/** SPI_MEM_S_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1;
+ *  Set this bit to write data faster, do not wait write data has been stored in
+ *  tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
+ *  in  tx_bus_fifo_l2.
+ */
+#define SPI_MEM_S_FAST_WRITE_EN    (BIT(29))
+#define SPI_MEM_S_FAST_WRITE_EN_M  (SPI_MEM_S_FAST_WRITE_EN_V << SPI_MEM_S_FAST_WRITE_EN_S)
+#define SPI_MEM_S_FAST_WRITE_EN_V  0x00000001U
+#define SPI_MEM_S_FAST_WRITE_EN_S  29
+/** SPI_MEM_S_RXFIFO_RST : WT; bitpos: [30]; default: 0;
+ *  The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
+ *  receive signals from AXI.  Set this bit to reset these FIFO.
+ */
+#define SPI_MEM_S_RXFIFO_RST    (BIT(30))
+#define SPI_MEM_S_RXFIFO_RST_M  (SPI_MEM_S_RXFIFO_RST_V << SPI_MEM_S_RXFIFO_RST_S)
+#define SPI_MEM_S_RXFIFO_RST_V  0x00000001U
+#define SPI_MEM_S_RXFIFO_RST_S  30
+/** SPI_MEM_S_TXFIFO_RST : WT; bitpos: [31]; default: 0;
+ *  The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
+ *  send signals to AXI. Set this bit to reset these FIFO.
+ */
+#define SPI_MEM_S_TXFIFO_RST    (BIT(31))
+#define SPI_MEM_S_TXFIFO_RST_M  (SPI_MEM_S_TXFIFO_RST_V << SPI_MEM_S_TXFIFO_RST_S)
+#define SPI_MEM_S_TXFIFO_RST_V  0x00000001U
+#define SPI_MEM_S_TXFIFO_RST_S  31
+
+/** SPI_MEM_S_CTRL2_REG register
+ *  SPI0 control2 register.
+ */
+#define SPI_MEM_S_CTRL2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10)
+/** SPI_MEM_S_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1;
+ *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
+ *  SPI_MEM_S_CS_SETUP bit.
+ */
+#define SPI_MEM_S_CS_SETUP_TIME    0x0000001FU
+#define SPI_MEM_S_CS_SETUP_TIME_M  (SPI_MEM_S_CS_SETUP_TIME_V << SPI_MEM_S_CS_SETUP_TIME_S)
+#define SPI_MEM_S_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_MEM_S_CS_SETUP_TIME_S  0
+/** SPI_MEM_S_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1;
+ *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
+ *  SPI_MEM_S_CS_HOLD bit.
+ */
+#define SPI_MEM_S_CS_HOLD_TIME    0x0000001FU
+#define SPI_MEM_S_CS_HOLD_TIME_M  (SPI_MEM_S_CS_HOLD_TIME_V << SPI_MEM_S_CS_HOLD_TIME_S)
+#define SPI_MEM_S_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_MEM_S_CS_HOLD_TIME_S  5
+/** SPI_MEM_S_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3;
+ *  SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+ *  mode when accessed flash.
+ */
+#define SPI_MEM_S_ECC_CS_HOLD_TIME    0x00000007U
+#define SPI_MEM_S_ECC_CS_HOLD_TIME_M  (SPI_MEM_S_ECC_CS_HOLD_TIME_V << SPI_MEM_S_ECC_CS_HOLD_TIME_S)
+#define SPI_MEM_S_ECC_CS_HOLD_TIME_V  0x00000007U
+#define SPI_MEM_S_ECC_CS_HOLD_TIME_S  10
+/** SPI_MEM_S_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1;
+ *  1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when
+ *  accesses flash.
+ */
+#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER    (BIT(13))
+#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_S_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_S_ECC_SKIP_PAGE_CORNER_S)
+#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_V  0x00000001U
+#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_S  13
+/** SPI_MEM_S_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0;
+ *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+ *  accesses flash.
+ */
+#define SPI_MEM_S_ECC_16TO18_BYTE_EN    (BIT(14))
+#define SPI_MEM_S_ECC_16TO18_BYTE_EN_M  (SPI_MEM_S_ECC_16TO18_BYTE_EN_V << SPI_MEM_S_ECC_16TO18_BYTE_EN_S)
+#define SPI_MEM_S_ECC_16TO18_BYTE_EN_V  0x00000001U
+#define SPI_MEM_S_ECC_16TO18_BYTE_EN_S  14
+/** SPI_MEM_S_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable SPI0 split one AXI read flash transfer into two SPI
+ *  transfers when one transfer will cross flash or EXT_RAM page corner, valid no
+ *  matter whether there is an ECC region or not.
+ */
+#define SPI_MEM_S_SPLIT_TRANS_EN    (BIT(24))
+#define SPI_MEM_S_SPLIT_TRANS_EN_M  (SPI_MEM_S_SPLIT_TRANS_EN_V << SPI_MEM_S_SPLIT_TRANS_EN_S)
+#define SPI_MEM_S_SPLIT_TRANS_EN_V  0x00000001U
+#define SPI_MEM_S_SPLIT_TRANS_EN_S  24
+/** SPI_MEM_S_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0;
+ *  These bits are used to set the minimum CS high time tSHSL between SPI burst
+ *  transfer when accesses to flash. tSHSL is (SPI_MEM_S_CS_HOLD_DELAY[5:0] + 1) MSPI
+ *  core clock cycles.
+ */
+#define SPI_MEM_S_CS_HOLD_DELAY    0x0000003FU
+#define SPI_MEM_S_CS_HOLD_DELAY_M  (SPI_MEM_S_CS_HOLD_DELAY_V << SPI_MEM_S_CS_HOLD_DELAY_S)
+#define SPI_MEM_S_CS_HOLD_DELAY_V  0x0000003FU
+#define SPI_MEM_S_CS_HOLD_DELAY_S  25
+/** SPI_MEM_S_SYNC_RESET : WT; bitpos: [31]; default: 0;
+ *  The spi0_mst_st and spi0_slv_st will be reset.
+ */
+#define SPI_MEM_S_SYNC_RESET    (BIT(31))
+#define SPI_MEM_S_SYNC_RESET_M  (SPI_MEM_S_SYNC_RESET_V << SPI_MEM_S_SYNC_RESET_S)
+#define SPI_MEM_S_SYNC_RESET_V  0x00000001U
+#define SPI_MEM_S_SYNC_RESET_S  31
+
+/** SPI_MEM_S_CLOCK_REG register
+ *  SPI clock division control register.
+ */
+#define SPI_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14)
+/** SPI_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+ *  In the master mode it must be equal to spi_mem_clkcnt_N.
+ */
+#define SPI_MEM_S_CLKCNT_L    0x000000FFU
+#define SPI_MEM_S_CLKCNT_L_M  (SPI_MEM_S_CLKCNT_L_V << SPI_MEM_S_CLKCNT_L_S)
+#define SPI_MEM_S_CLKCNT_L_V  0x000000FFU
+#define SPI_MEM_S_CLKCNT_L_S  0
+/** SPI_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+ *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+ */
+#define SPI_MEM_S_CLKCNT_H    0x000000FFU
+#define SPI_MEM_S_CLKCNT_H_M  (SPI_MEM_S_CLKCNT_H_V << SPI_MEM_S_CLKCNT_H_S)
+#define SPI_MEM_S_CLKCNT_H_V  0x000000FFU
+#define SPI_MEM_S_CLKCNT_H_S  8
+/** SPI_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+ *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+ *  system/(spi_mem_clkcnt_N+1)
+ */
+#define SPI_MEM_S_CLKCNT_N    0x000000FFU
+#define SPI_MEM_S_CLKCNT_N_M  (SPI_MEM_S_CLKCNT_N_V << SPI_MEM_S_CLKCNT_N_S)
+#define SPI_MEM_S_CLKCNT_N_V  0x000000FFU
+#define SPI_MEM_S_CLKCNT_N_S  16
+/** SPI_MEM_S_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+ *  1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
+ *  clock.
+ */
+#define SPI_MEM_S_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_S_CLK_EQU_SYSCLK_M  (SPI_MEM_S_CLK_EQU_SYSCLK_V << SPI_MEM_S_CLK_EQU_SYSCLK_S)
+#define SPI_MEM_S_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI_MEM_S_CLK_EQU_SYSCLK_S  31
+
+/** SPI_MEM_S_USER_REG register
+ *  SPI0 user register.
+ */
+#define SPI_MEM_S_USER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18)
+/** SPI_MEM_S_CS_HOLD : R/W; bitpos: [6]; default: 0;
+ *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_CS_HOLD    (BIT(6))
+#define SPI_MEM_S_CS_HOLD_M  (SPI_MEM_S_CS_HOLD_V << SPI_MEM_S_CS_HOLD_S)
+#define SPI_MEM_S_CS_HOLD_V  0x00000001U
+#define SPI_MEM_S_CS_HOLD_S  6
+/** SPI_MEM_S_CS_SETUP : R/W; bitpos: [7]; default: 0;
+ *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_CS_SETUP    (BIT(7))
+#define SPI_MEM_S_CS_SETUP_M  (SPI_MEM_S_CS_SETUP_V << SPI_MEM_S_CS_SETUP_S)
+#define SPI_MEM_S_CS_SETUP_V  0x00000001U
+#define SPI_MEM_S_CS_SETUP_S  7
+/** SPI_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
+ */
+#define SPI_MEM_S_CK_OUT_EDGE    (BIT(9))
+#define SPI_MEM_S_CK_OUT_EDGE_M  (SPI_MEM_S_CK_OUT_EDGE_V << SPI_MEM_S_CK_OUT_EDGE_S)
+#define SPI_MEM_S_CK_OUT_EDGE_V  0x00000001U
+#define SPI_MEM_S_CK_OUT_EDGE_S  9
+/** SPI_MEM_S_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+ *  spi clock is disable in dummy phase when the bit is enable.
+ */
+#define SPI_MEM_S_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_MEM_S_USR_DUMMY_IDLE_M  (SPI_MEM_S_USR_DUMMY_IDLE_V << SPI_MEM_S_USR_DUMMY_IDLE_S)
+#define SPI_MEM_S_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI_MEM_S_USR_DUMMY_IDLE_S  26
+/** SPI_MEM_S_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+ *  This bit enable the dummy phase of an operation.
+ */
+#define SPI_MEM_S_USR_DUMMY    (BIT(29))
+#define SPI_MEM_S_USR_DUMMY_M  (SPI_MEM_S_USR_DUMMY_V << SPI_MEM_S_USR_DUMMY_S)
+#define SPI_MEM_S_USR_DUMMY_V  0x00000001U
+#define SPI_MEM_S_USR_DUMMY_S  29
+
+/** SPI_MEM_S_USER1_REG register
+ *  SPI0 user1 register.
+ */
+#define SPI_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1c)
+/** SPI_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
+ *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+ *  (cycle_num-1).
+ */
+#define SPI_MEM_S_USR_DUMMY_CYCLELEN    0x0000003FU
+#define SPI_MEM_S_USR_DUMMY_CYCLELEN_M  (SPI_MEM_S_USR_DUMMY_CYCLELEN_V << SPI_MEM_S_USR_DUMMY_CYCLELEN_S)
+#define SPI_MEM_S_USR_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI_MEM_S_USR_DUMMY_CYCLELEN_S  0
+/** SPI_MEM_S_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1;
+ *  SPI0 USR_CMD read or write data byte length -1
+ */
+#define SPI_MEM_S_USR_DBYTELEN    0x00000007U
+#define SPI_MEM_S_USR_DBYTELEN_M  (SPI_MEM_S_USR_DBYTELEN_V << SPI_MEM_S_USR_DBYTELEN_S)
+#define SPI_MEM_S_USR_DBYTELEN_V  0x00000007U
+#define SPI_MEM_S_USR_DBYTELEN_S  6
+/** SPI_MEM_S_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
+ *  The length in bits of address phase. The register value shall be (bit_num-1).
+ */
+#define SPI_MEM_S_USR_ADDR_BITLEN    0x0000003FU
+#define SPI_MEM_S_USR_ADDR_BITLEN_M  (SPI_MEM_S_USR_ADDR_BITLEN_V << SPI_MEM_S_USR_ADDR_BITLEN_S)
+#define SPI_MEM_S_USR_ADDR_BITLEN_V  0x0000003FU
+#define SPI_MEM_S_USR_ADDR_BITLEN_S  26
+
+/** SPI_MEM_S_USER2_REG register
+ *  SPI0 user2 register.
+ */
+#define SPI_MEM_S_USER2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x20)
+/** SPI_MEM_S_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  The value of  command.
+ */
+#define SPI_MEM_S_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI_MEM_S_USR_COMMAND_VALUE_M  (SPI_MEM_S_USR_COMMAND_VALUE_V << SPI_MEM_S_USR_COMMAND_VALUE_S)
+#define SPI_MEM_S_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI_MEM_S_USR_COMMAND_VALUE_S  0
+/** SPI_MEM_S_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+ *  The length in bits of command phase. The register value shall be (bit_num-1)
+ */
+#define SPI_MEM_S_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI_MEM_S_USR_COMMAND_BITLEN_M  (SPI_MEM_S_USR_COMMAND_BITLEN_V << SPI_MEM_S_USR_COMMAND_BITLEN_S)
+#define SPI_MEM_S_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI_MEM_S_USR_COMMAND_BITLEN_S  28
+
+/** SPI_MEM_S_RD_STATUS_REG register
+ *  SPI0 read control register.
+ */
+#define SPI_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x2c)
+/** SPI_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0;
+ *  Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+ */
+#define SPI_MEM_S_WB_MODE    0x000000FFU
+#define SPI_MEM_S_WB_MODE_M  (SPI_MEM_S_WB_MODE_V << SPI_MEM_S_WB_MODE_S)
+#define SPI_MEM_S_WB_MODE_V  0x000000FFU
+#define SPI_MEM_S_WB_MODE_S  16
+
+/** SPI_MEM_S_MISC_REG register
+ *  SPI0 misc register
+ */
+#define SPI_MEM_S_MISC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34)
+/** SPI_MEM_S_FSUB_PIN : R/W; bitpos: [7]; default: 0;
+ *  For SPI0,  flash is connected to SUBPINs.
+ */
+#define SPI_MEM_S_FSUB_PIN    (BIT(7))
+#define SPI_MEM_S_FSUB_PIN_M  (SPI_MEM_S_FSUB_PIN_V << SPI_MEM_S_FSUB_PIN_S)
+#define SPI_MEM_S_FSUB_PIN_V  0x00000001U
+#define SPI_MEM_S_FSUB_PIN_S  7
+/** SPI_MEM_S_SSUB_PIN : R/W; bitpos: [8]; default: 0;
+ *  For SPI0,  sram is connected to SUBPINs.
+ */
+#define SPI_MEM_S_SSUB_PIN    (BIT(8))
+#define SPI_MEM_S_SSUB_PIN_M  (SPI_MEM_S_SSUB_PIN_V << SPI_MEM_S_SSUB_PIN_S)
+#define SPI_MEM_S_SSUB_PIN_V  0x00000001U
+#define SPI_MEM_S_SSUB_PIN_S  8
+/** SPI_MEM_S_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
+ *  1: SPI_CLK line is high when idle     0: spi clk line is low when idle
+ */
+#define SPI_MEM_S_CK_IDLE_EDGE    (BIT(9))
+#define SPI_MEM_S_CK_IDLE_EDGE_M  (SPI_MEM_S_CK_IDLE_EDGE_V << SPI_MEM_S_CK_IDLE_EDGE_S)
+#define SPI_MEM_S_CK_IDLE_EDGE_V  0x00000001U
+#define SPI_MEM_S_CK_IDLE_EDGE_S  9
+/** SPI_MEM_S_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
+ *  SPI_CS line keep low when the bit is set.
+ */
+#define SPI_MEM_S_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI_MEM_S_CS_KEEP_ACTIVE_M  (SPI_MEM_S_CS_KEEP_ACTIVE_V << SPI_MEM_S_CS_KEEP_ACTIVE_S)
+#define SPI_MEM_S_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI_MEM_S_CS_KEEP_ACTIVE_S  10
+
+/** SPI_MEM_S_CACHE_FCTRL_REG register
+ *  SPI0 bit mode control register.
+ */
+#define SPI_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3c)
+/** SPI_MEM_S_AXI_REQ_EN : R/W; bitpos: [0]; default: 0;
+ *  For SPI0, AXI master access enable, 1: enable, 0:disable.
+ */
+#define SPI_MEM_S_AXI_REQ_EN    (BIT(0))
+#define SPI_MEM_S_AXI_REQ_EN_M  (SPI_MEM_S_AXI_REQ_EN_V << SPI_MEM_S_AXI_REQ_EN_S)
+#define SPI_MEM_S_AXI_REQ_EN_V  0x00000001U
+#define SPI_MEM_S_AXI_REQ_EN_S  0
+/** SPI_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
+ *  For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
+ */
+#define SPI_MEM_S_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI_MEM_S_CACHE_USR_ADDR_4BYTE_M  (SPI_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_S_CACHE_USR_ADDR_4BYTE_S)
+#define SPI_MEM_S_CACHE_USR_ADDR_4BYTE_V  0x00000001U
+#define SPI_MEM_S_CACHE_USR_ADDR_4BYTE_S  1
+/** SPI_MEM_S_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0;
+ *  For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.
+ */
+#define SPI_MEM_S_CACHE_FLASH_USR_CMD    (BIT(2))
+#define SPI_MEM_S_CACHE_FLASH_USR_CMD_M  (SPI_MEM_S_CACHE_FLASH_USR_CMD_V << SPI_MEM_S_CACHE_FLASH_USR_CMD_S)
+#define SPI_MEM_S_CACHE_FLASH_USR_CMD_V  0x00000001U
+#define SPI_MEM_S_CACHE_FLASH_USR_CMD_S  2
+/** SPI_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
+ *  For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
+ *  same with spi_mem_fread_dio.
+ */
+#define SPI_MEM_S_FDIN_DUAL    (BIT(3))
+#define SPI_MEM_S_FDIN_DUAL_M  (SPI_MEM_S_FDIN_DUAL_V << SPI_MEM_S_FDIN_DUAL_S)
+#define SPI_MEM_S_FDIN_DUAL_V  0x00000001U
+#define SPI_MEM_S_FDIN_DUAL_S  3
+/** SPI_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
+ *  For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
+ *  same with spi_mem_fread_dio.
+ */
+#define SPI_MEM_S_FDOUT_DUAL    (BIT(4))
+#define SPI_MEM_S_FDOUT_DUAL_M  (SPI_MEM_S_FDOUT_DUAL_V << SPI_MEM_S_FDOUT_DUAL_S)
+#define SPI_MEM_S_FDOUT_DUAL_V  0x00000001U
+#define SPI_MEM_S_FDOUT_DUAL_S  4
+/** SPI_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+ *  For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
+ *  the same with spi_mem_fread_dio.
+ */
+#define SPI_MEM_S_FADDR_DUAL    (BIT(5))
+#define SPI_MEM_S_FADDR_DUAL_M  (SPI_MEM_S_FADDR_DUAL_V << SPI_MEM_S_FADDR_DUAL_S)
+#define SPI_MEM_S_FADDR_DUAL_V  0x00000001U
+#define SPI_MEM_S_FADDR_DUAL_S  5
+/** SPI_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
+ *  For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
+ *  same with spi_mem_fread_qio.
+ */
+#define SPI_MEM_S_FDIN_QUAD    (BIT(6))
+#define SPI_MEM_S_FDIN_QUAD_M  (SPI_MEM_S_FDIN_QUAD_V << SPI_MEM_S_FDIN_QUAD_S)
+#define SPI_MEM_S_FDIN_QUAD_V  0x00000001U
+#define SPI_MEM_S_FDIN_QUAD_S  6
+/** SPI_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
+ *  For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the
+ *  same with spi_mem_fread_qio.
+ */
+#define SPI_MEM_S_FDOUT_QUAD    (BIT(7))
+#define SPI_MEM_S_FDOUT_QUAD_M  (SPI_MEM_S_FDOUT_QUAD_V << SPI_MEM_S_FDOUT_QUAD_S)
+#define SPI_MEM_S_FDOUT_QUAD_V  0x00000001U
+#define SPI_MEM_S_FDOUT_QUAD_S  7
+/** SPI_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
+ *  For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
+ *  the same with spi_mem_fread_qio.
+ */
+#define SPI_MEM_S_FADDR_QUAD    (BIT(8))
+#define SPI_MEM_S_FADDR_QUAD_M  (SPI_MEM_S_FADDR_QUAD_V << SPI_MEM_S_FADDR_QUAD_S)
+#define SPI_MEM_S_FADDR_QUAD_V  0x00000001U
+#define SPI_MEM_S_FADDR_QUAD_S  8
+/** SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1;
+ *  Set this bit to check AXI read/write the same address region.
+ */
+#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
+#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_M  (SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_V << SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_S)
+#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_V  0x00000001U
+#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_S  30
+/** SPI_MEM_S_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1;
+ *  Set this bit to close AXI read/write transfer to MSPI, which means that only
+ *  SLV_ERR will be replied to BRESP/RRESP.
+ */
+#define SPI_MEM_S_CLOSE_AXI_INF_EN    (BIT(31))
+#define SPI_MEM_S_CLOSE_AXI_INF_EN_M  (SPI_MEM_S_CLOSE_AXI_INF_EN_V << SPI_MEM_S_CLOSE_AXI_INF_EN_S)
+#define SPI_MEM_S_CLOSE_AXI_INF_EN_V  0x00000001U
+#define SPI_MEM_S_CLOSE_AXI_INF_EN_S  31
+
+/** SPI_MEM_S_CACHE_SCTRL_REG register
+ *  SPI0 external RAM control register
+ */
+#define SPI_MEM_S_CACHE_SCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x40)
+/** SPI_MEM_S_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0;
+ *  For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1:
+ *  enable, 0:disable.
+ */
+#define SPI_MEM_S_CACHE_USR_SADDR_4BYTE    (BIT(0))
+#define SPI_MEM_S_CACHE_USR_SADDR_4BYTE_M  (SPI_MEM_S_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_S_CACHE_USR_SADDR_4BYTE_S)
+#define SPI_MEM_S_CACHE_USR_SADDR_4BYTE_V  0x00000001U
+#define SPI_MEM_S_CACHE_USR_SADDR_4BYTE_S  0
+/** SPI_MEM_S_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0;
+ *  For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable
+ */
+#define SPI_MEM_S_USR_SRAM_DIO    (BIT(1))
+#define SPI_MEM_S_USR_SRAM_DIO_M  (SPI_MEM_S_USR_SRAM_DIO_V << SPI_MEM_S_USR_SRAM_DIO_S)
+#define SPI_MEM_S_USR_SRAM_DIO_V  0x00000001U
+#define SPI_MEM_S_USR_SRAM_DIO_S  1
+/** SPI_MEM_S_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0;
+ *  For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable
+ */
+#define SPI_MEM_S_USR_SRAM_QIO    (BIT(2))
+#define SPI_MEM_S_USR_SRAM_QIO_M  (SPI_MEM_S_USR_SRAM_QIO_V << SPI_MEM_S_USR_SRAM_QIO_S)
+#define SPI_MEM_S_USR_SRAM_QIO_V  0x00000001U
+#define SPI_MEM_S_USR_SRAM_QIO_S  2
+/** SPI_MEM_S_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0;
+ *  For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write
+ *  operations.
+ */
+#define SPI_MEM_S_USR_WR_SRAM_DUMMY    (BIT(3))
+#define SPI_MEM_S_USR_WR_SRAM_DUMMY_M  (SPI_MEM_S_USR_WR_SRAM_DUMMY_V << SPI_MEM_S_USR_WR_SRAM_DUMMY_S)
+#define SPI_MEM_S_USR_WR_SRAM_DUMMY_V  0x00000001U
+#define SPI_MEM_S_USR_WR_SRAM_DUMMY_S  3
+/** SPI_MEM_S_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1;
+ *  For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
+ *  operations.
+ */
+#define SPI_MEM_S_USR_RD_SRAM_DUMMY    (BIT(4))
+#define SPI_MEM_S_USR_RD_SRAM_DUMMY_M  (SPI_MEM_S_USR_RD_SRAM_DUMMY_V << SPI_MEM_S_USR_RD_SRAM_DUMMY_S)
+#define SPI_MEM_S_USR_RD_SRAM_DUMMY_V  0x00000001U
+#define SPI_MEM_S_USR_RD_SRAM_DUMMY_S  4
+/** SPI_MEM_S_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1;
+ *  For SPI0, In the external RAM mode cache read external RAM for user define command.
+ */
+#define SPI_MEM_S_CACHE_SRAM_USR_RCMD    (BIT(5))
+#define SPI_MEM_S_CACHE_SRAM_USR_RCMD_M  (SPI_MEM_S_CACHE_SRAM_USR_RCMD_V << SPI_MEM_S_CACHE_SRAM_USR_RCMD_S)
+#define SPI_MEM_S_CACHE_SRAM_USR_RCMD_V  0x00000001U
+#define SPI_MEM_S_CACHE_SRAM_USR_RCMD_S  5
+/** SPI_MEM_S_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1;
+ *  For SPI0, In the external RAM mode, it is the length in bits of read dummy phase.
+ *  The register value shall be (bit_num-1).
+ */
+#define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN    0x0000003FU
+#define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_M  (SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_S)
+#define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_V  0x0000003FU
+#define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_S  6
+/** SPI_MEM_S_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23;
+ *  For SPI0, In the external RAM mode, it is the length in bits of address phase. The
+ *  register value shall be (bit_num-1).
+ */
+#define SPI_MEM_S_SRAM_ADDR_BITLEN    0x0000003FU
+#define SPI_MEM_S_SRAM_ADDR_BITLEN_M  (SPI_MEM_S_SRAM_ADDR_BITLEN_V << SPI_MEM_S_SRAM_ADDR_BITLEN_S)
+#define SPI_MEM_S_SRAM_ADDR_BITLEN_V  0x0000003FU
+#define SPI_MEM_S_SRAM_ADDR_BITLEN_S  14
+/** SPI_MEM_S_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1;
+ *  For SPI0, In the external RAM mode cache write sram for user define command
+ */
+#define SPI_MEM_S_CACHE_SRAM_USR_WCMD    (BIT(20))
+#define SPI_MEM_S_CACHE_SRAM_USR_WCMD_M  (SPI_MEM_S_CACHE_SRAM_USR_WCMD_V << SPI_MEM_S_CACHE_SRAM_USR_WCMD_S)
+#define SPI_MEM_S_CACHE_SRAM_USR_WCMD_V  0x00000001U
+#define SPI_MEM_S_CACHE_SRAM_USR_WCMD_S  20
+/** SPI_MEM_S_SRAM_OCT : R/W; bitpos: [21]; default: 0;
+ *  reserved
+ */
+#define SPI_MEM_S_SRAM_OCT    (BIT(21))
+#define SPI_MEM_S_SRAM_OCT_M  (SPI_MEM_S_SRAM_OCT_V << SPI_MEM_S_SRAM_OCT_S)
+#define SPI_MEM_S_SRAM_OCT_V  0x00000001U
+#define SPI_MEM_S_SRAM_OCT_S  21
+/** SPI_MEM_S_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1;
+ *  For SPI0, In the external RAM mode, it is the length in bits of write dummy phase.
+ *  The register value shall be (bit_num-1).
+ */
+#define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN    0x0000003FU
+#define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_M  (SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_S)
+#define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_V  0x0000003FU
+#define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_S  22
+
+/** SPI_MEM_S_SRAM_CMD_REG register
+ *  SPI0 external RAM mode control register
+ */
+#define SPI_MEM_S_SRAM_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x44)
+/** SPI_MEM_S_SCLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+ *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+ *  SPI clock is always on.
+ */
+#define SPI_MEM_S_SCLK_MODE    0x00000003U
+#define SPI_MEM_S_SCLK_MODE_M  (SPI_MEM_S_SCLK_MODE_V << SPI_MEM_S_SCLK_MODE_S)
+#define SPI_MEM_S_SCLK_MODE_V  0x00000003U
+#define SPI_MEM_S_SCLK_MODE_S  0
+/** SPI_MEM_S_SWB_MODE : R/W; bitpos: [9:2]; default: 0;
+ *  Mode bits in the external RAM fast read mode  it is combined with
+ *  spi_mem_fastrd_mode bit.
+ */
+#define SPI_MEM_S_SWB_MODE    0x000000FFU
+#define SPI_MEM_S_SWB_MODE_M  (SPI_MEM_S_SWB_MODE_V << SPI_MEM_S_SWB_MODE_S)
+#define SPI_MEM_S_SWB_MODE_V  0x000000FFU
+#define SPI_MEM_S_SWB_MODE_S  2
+/** SPI_MEM_S_SDIN_DUAL : R/W; bitpos: [10]; default: 0;
+ *  For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is
+ *  the same with spi_mem_usr_sram_dio.
+ */
+#define SPI_MEM_S_SDIN_DUAL    (BIT(10))
+#define SPI_MEM_S_SDIN_DUAL_M  (SPI_MEM_S_SDIN_DUAL_V << SPI_MEM_S_SDIN_DUAL_S)
+#define SPI_MEM_S_SDIN_DUAL_V  0x00000001U
+#define SPI_MEM_S_SDIN_DUAL_S  10
+/** SPI_MEM_S_SDOUT_DUAL : R/W; bitpos: [11]; default: 0;
+ *  For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit
+ *  is the same with spi_mem_usr_sram_dio.
+ */
+#define SPI_MEM_S_SDOUT_DUAL    (BIT(11))
+#define SPI_MEM_S_SDOUT_DUAL_M  (SPI_MEM_S_SDOUT_DUAL_V << SPI_MEM_S_SDOUT_DUAL_S)
+#define SPI_MEM_S_SDOUT_DUAL_V  0x00000001U
+#define SPI_MEM_S_SDOUT_DUAL_S  11
+/** SPI_MEM_S_SADDR_DUAL : R/W; bitpos: [12]; default: 0;
+ *  For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
+ *  bit is the same with spi_mem_usr_sram_dio.
+ */
+#define SPI_MEM_S_SADDR_DUAL    (BIT(12))
+#define SPI_MEM_S_SADDR_DUAL_M  (SPI_MEM_S_SADDR_DUAL_V << SPI_MEM_S_SADDR_DUAL_S)
+#define SPI_MEM_S_SADDR_DUAL_V  0x00000001U
+#define SPI_MEM_S_SADDR_DUAL_S  12
+/** SPI_MEM_S_SDIN_QUAD : R/W; bitpos: [14]; default: 0;
+ *  For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is
+ *  the same with spi_mem_usr_sram_qio.
+ */
+#define SPI_MEM_S_SDIN_QUAD    (BIT(14))
+#define SPI_MEM_S_SDIN_QUAD_M  (SPI_MEM_S_SDIN_QUAD_V << SPI_MEM_S_SDIN_QUAD_S)
+#define SPI_MEM_S_SDIN_QUAD_V  0x00000001U
+#define SPI_MEM_S_SDIN_QUAD_S  14
+/** SPI_MEM_S_SDOUT_QUAD : R/W; bitpos: [15]; default: 0;
+ *  For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit
+ *  is the same with spi_mem_usr_sram_qio.
+ */
+#define SPI_MEM_S_SDOUT_QUAD    (BIT(15))
+#define SPI_MEM_S_SDOUT_QUAD_M  (SPI_MEM_S_SDOUT_QUAD_V << SPI_MEM_S_SDOUT_QUAD_S)
+#define SPI_MEM_S_SDOUT_QUAD_V  0x00000001U
+#define SPI_MEM_S_SDOUT_QUAD_S  15
+/** SPI_MEM_S_SADDR_QUAD : R/W; bitpos: [16]; default: 0;
+ *  For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
+ *  bit is the same with spi_mem_usr_sram_qio.
+ */
+#define SPI_MEM_S_SADDR_QUAD    (BIT(16))
+#define SPI_MEM_S_SADDR_QUAD_M  (SPI_MEM_S_SADDR_QUAD_V << SPI_MEM_S_SADDR_QUAD_S)
+#define SPI_MEM_S_SADDR_QUAD_V  0x00000001U
+#define SPI_MEM_S_SADDR_QUAD_S  16
+/** SPI_MEM_S_SCMD_QUAD : R/W; bitpos: [17]; default: 0;
+ *  For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is
+ *  the same with spi_mem_usr_sram_qio.
+ */
+#define SPI_MEM_S_SCMD_QUAD    (BIT(17))
+#define SPI_MEM_S_SCMD_QUAD_M  (SPI_MEM_S_SCMD_QUAD_V << SPI_MEM_S_SCMD_QUAD_S)
+#define SPI_MEM_S_SCMD_QUAD_V  0x00000001U
+#define SPI_MEM_S_SCMD_QUAD_S  17
+/** SPI_MEM_S_SDIN_OCT : R/W; bitpos: [18]; default: 0;
+ *  For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_SDIN_OCT    (BIT(18))
+#define SPI_MEM_S_SDIN_OCT_M  (SPI_MEM_S_SDIN_OCT_V << SPI_MEM_S_SDIN_OCT_S)
+#define SPI_MEM_S_SDIN_OCT_V  0x00000001U
+#define SPI_MEM_S_SDIN_OCT_S  18
+/** SPI_MEM_S_SDOUT_OCT : R/W; bitpos: [19]; default: 0;
+ *  For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_SDOUT_OCT    (BIT(19))
+#define SPI_MEM_S_SDOUT_OCT_M  (SPI_MEM_S_SDOUT_OCT_V << SPI_MEM_S_SDOUT_OCT_S)
+#define SPI_MEM_S_SDOUT_OCT_V  0x00000001U
+#define SPI_MEM_S_SDOUT_OCT_S  19
+/** SPI_MEM_S_SADDR_OCT : R/W; bitpos: [20]; default: 0;
+ *  For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_SADDR_OCT    (BIT(20))
+#define SPI_MEM_S_SADDR_OCT_M  (SPI_MEM_S_SADDR_OCT_V << SPI_MEM_S_SADDR_OCT_S)
+#define SPI_MEM_S_SADDR_OCT_V  0x00000001U
+#define SPI_MEM_S_SADDR_OCT_S  20
+/** SPI_MEM_S_SCMD_OCT : R/W; bitpos: [21]; default: 0;
+ *  For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_SCMD_OCT    (BIT(21))
+#define SPI_MEM_S_SCMD_OCT_M  (SPI_MEM_S_SCMD_OCT_V << SPI_MEM_S_SCMD_OCT_S)
+#define SPI_MEM_S_SCMD_OCT_V  0x00000001U
+#define SPI_MEM_S_SCMD_OCT_S  21
+/** SPI_MEM_S_SDUMMY_RIN : R/W; bitpos: [22]; default: 1;
+ *  In the dummy phase of a MSPI read data transfer when accesses to external RAM, the
+ *  signal level of SPI bus is output by the MSPI controller.
+ */
+#define SPI_MEM_S_SDUMMY_RIN    (BIT(22))
+#define SPI_MEM_S_SDUMMY_RIN_M  (SPI_MEM_S_SDUMMY_RIN_V << SPI_MEM_S_SDUMMY_RIN_S)
+#define SPI_MEM_S_SDUMMY_RIN_V  0x00000001U
+#define SPI_MEM_S_SDUMMY_RIN_S  22
+/** SPI_MEM_S_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1;
+ *  In the dummy phase of a MSPI write data transfer when accesses to external RAM, the
+ *  signal level of SPI bus is output by the MSPI controller.
+ */
+#define SPI_MEM_S_SDUMMY_WOUT    (BIT(23))
+#define SPI_MEM_S_SDUMMY_WOUT_M  (SPI_MEM_S_SDUMMY_WOUT_V << SPI_MEM_S_SDUMMY_WOUT_S)
+#define SPI_MEM_S_SDUMMY_WOUT_V  0x00000001U
+#define SPI_MEM_S_SDUMMY_WOUT_S  23
+/** SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0;
+ *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ *  the level of SPI_MEM_S_DQS is output by the MSPI controller.
+ */
+#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
+#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S)
+#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
+/** SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0;
+ *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ *  the level of SPI_MEM_S_IO[7:0] is output by the MSPI controller.
+ */
+#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
+#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S)
+#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_V  0x00000001U
+#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S  25
+/** SPI_MEM_S_SDIN_HEX : R/W; bitpos: [26]; default: 0;
+ *  For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_SDIN_HEX    (BIT(26))
+#define SPI_MEM_S_SDIN_HEX_M  (SPI_MEM_S_SDIN_HEX_V << SPI_MEM_S_SDIN_HEX_S)
+#define SPI_MEM_S_SDIN_HEX_V  0x00000001U
+#define SPI_MEM_S_SDIN_HEX_S  26
+/** SPI_MEM_S_SDOUT_HEX : R/W; bitpos: [27]; default: 0;
+ *  For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_SDOUT_HEX    (BIT(27))
+#define SPI_MEM_S_SDOUT_HEX_M  (SPI_MEM_S_SDOUT_HEX_V << SPI_MEM_S_SDOUT_HEX_S)
+#define SPI_MEM_S_SDOUT_HEX_V  0x00000001U
+#define SPI_MEM_S_SDOUT_HEX_S  27
+/** SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0;
+ *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_MEM_S_DQS are
+ *  always 1. 0: Others.
+ */
+#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_M  (SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_S)
+#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_S  30
+/** SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1;
+ *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_MEM_S_IO[7:0]
+ *  are always 1. 0: Others.
+ */
+#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_M  (SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_S)
+#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_V  0x00000001U
+#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_S  31
+
+/** SPI_MEM_S_SRAM_DRD_CMD_REG register
+ *  SPI0 external RAM DDR read command control register
+ */
+#define SPI_MEM_S_SRAM_DRD_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x48)
+/** SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  For SPI0,When cache mode is enable it is the read command value of command phase
+ *  for sram.
+ */
+#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFFU
+#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_M  (SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_S)
+#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_V  0x0000FFFFU
+#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
+/** SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0;
+ *  For SPI0,When cache mode is enable it is the length in bits of command phase for
+ *  sram. The register value shall be (bit_num-1).
+ */
+#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000FU
+#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_M  (SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_S)
+#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0x0000000FU
+#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
+
+/** SPI_MEM_S_SRAM_DWR_CMD_REG register
+ *  SPI0 external RAM DDR write command control register
+ */
+#define SPI_MEM_S_SRAM_DWR_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x4c)
+/** SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  For SPI0,When cache mode is enable it is the write command value of command phase
+ *  for sram.
+ */
+#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFFU
+#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_M  (SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_S)
+#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_V  0x0000FFFFU
+#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
+/** SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0;
+ *  For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
+ *  The register value shall be (bit_num-1).
+ */
+#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000FU
+#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_M  (SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_S)
+#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0x0000000FU
+#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
+
+/** SPI_MEM_S_SRAM_CLK_REG register
+ *  SPI0 external RAM clock control register
+ */
+#define SPI_MEM_S_SRAM_CLK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x50)
+/** SPI_MEM_S_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+ *  For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N.
+ */
+#define SPI_MEM_S_SCLKCNT_L    0x000000FFU
+#define SPI_MEM_S_SCLKCNT_L_M  (SPI_MEM_S_SCLKCNT_L_V << SPI_MEM_S_SCLKCNT_L_S)
+#define SPI_MEM_S_SCLKCNT_L_V  0x000000FFU
+#define SPI_MEM_S_SCLKCNT_L_S  0
+/** SPI_MEM_S_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+ *  For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).
+ */
+#define SPI_MEM_S_SCLKCNT_H    0x000000FFU
+#define SPI_MEM_S_SCLKCNT_H_M  (SPI_MEM_S_SCLKCNT_H_V << SPI_MEM_S_SCLKCNT_H_S)
+#define SPI_MEM_S_SCLKCNT_H_V  0x000000FFU
+#define SPI_MEM_S_SCLKCNT_H_S  8
+/** SPI_MEM_S_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+ *  For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk
+ *  frequency is system/(spi_mem_clkcnt_N+1)
+ */
+#define SPI_MEM_S_SCLKCNT_N    0x000000FFU
+#define SPI_MEM_S_SCLKCNT_N_M  (SPI_MEM_S_SCLKCNT_N_V << SPI_MEM_S_SCLKCNT_N_S)
+#define SPI_MEM_S_SCLKCNT_N_V  0x000000FFU
+#define SPI_MEM_S_SCLKCNT_N_S  16
+/** SPI_MEM_S_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+ *  For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk
+ *  is divided from system clock.
+ */
+#define SPI_MEM_S_SCLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_S_SCLK_EQU_SYSCLK_M  (SPI_MEM_S_SCLK_EQU_SYSCLK_V << SPI_MEM_S_SCLK_EQU_SYSCLK_S)
+#define SPI_MEM_S_SCLK_EQU_SYSCLK_V  0x00000001U
+#define SPI_MEM_S_SCLK_EQU_SYSCLK_S  31
+
+/** SPI_MEM_S_FSM_REG register
+ *  SPI0 FSM status register
+ */
+#define SPI_MEM_S_FSM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x54)
+/** SPI_MEM_S_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4;
+ *  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
+ */
+#define SPI_MEM_S_LOCK_DELAY_TIME    0x0000001FU
+#define SPI_MEM_S_LOCK_DELAY_TIME_M  (SPI_MEM_S_LOCK_DELAY_TIME_V << SPI_MEM_S_LOCK_DELAY_TIME_S)
+#define SPI_MEM_S_LOCK_DELAY_TIME_V  0x0000001FU
+#define SPI_MEM_S_LOCK_DELAY_TIME_S  7
+
+/** SPI_MEM_S_INT_ENA_REG register
+ *  SPI0 interrupt enable register
+ */
+#define SPI_MEM_S_INT_ENA_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc0)
+/** SPI_MEM_S_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
+ */
+#define SPI_MEM_S_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI_MEM_S_SLV_ST_END_INT_ENA_M  (SPI_MEM_S_SLV_ST_END_INT_ENA_V << SPI_MEM_S_SLV_ST_END_INT_ENA_S)
+#define SPI_MEM_S_SLV_ST_END_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_SLV_ST_END_INT_ENA_S  3
+/** SPI_MEM_S_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI_MEM_S_MST_ST_END_INT interrupt.
+ */
+#define SPI_MEM_S_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI_MEM_S_MST_ST_END_INT_ENA_M  (SPI_MEM_S_MST_ST_END_INT_ENA_V << SPI_MEM_S_MST_ST_END_INT_ENA_S)
+#define SPI_MEM_S_MST_ST_END_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_MST_ST_END_INT_ENA_S  4
+/** SPI_MEM_S_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The enable bit for SPI_MEM_S_ECC_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_ECC_ERR_INT_ENA    (BIT(5))
+#define SPI_MEM_S_ECC_ERR_INT_ENA_M  (SPI_MEM_S_ECC_ERR_INT_ENA_V << SPI_MEM_S_ECC_ERR_INT_ENA_S)
+#define SPI_MEM_S_ECC_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_ECC_ERR_INT_ENA_S  5
+/** SPI_MEM_S_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
+ */
+#define SPI_MEM_S_PMS_REJECT_INT_ENA    (BIT(6))
+#define SPI_MEM_S_PMS_REJECT_INT_ENA_M  (SPI_MEM_S_PMS_REJECT_INT_ENA_V << SPI_MEM_S_PMS_REJECT_INT_ENA_S)
+#define SPI_MEM_S_PMS_REJECT_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_PMS_REJECT_INT_ENA_S  6
+/** SPI_MEM_S_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA    (BIT(7))
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_M  (SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_S)
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_S  7
+/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_M  (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_S)
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_S  8
+/** SPI_MEM_S_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA    (BIT(9))
+#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_M  (SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S)
+#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V  0x00000001U
+#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S  9
+/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
+ */
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA    (BIT(28))
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_M  (SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_S)
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_S  28
+/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  The enable bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
+ */
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA    (BIT(29))
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_M  (SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_S)
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_S  29
+/** SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  The enable bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
+ */
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA    (BIT(30))
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_M  (SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_S)
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_S  30
+/** SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  The enable bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
+ */
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA    (BIT(31))
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_M  (SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_S)
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_S  31
+
+/** SPI_MEM_S_INT_CLR_REG register
+ *  SPI0 interrupt clear register
+ */
+#define SPI_MEM_S_INT_CLR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc4)
+/** SPI_MEM_S_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
+ */
+#define SPI_MEM_S_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI_MEM_S_SLV_ST_END_INT_CLR_M  (SPI_MEM_S_SLV_ST_END_INT_CLR_V << SPI_MEM_S_SLV_ST_END_INT_CLR_S)
+#define SPI_MEM_S_SLV_ST_END_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_SLV_ST_END_INT_CLR_S  3
+/** SPI_MEM_S_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI_MEM_S_MST_ST_END_INT interrupt.
+ */
+#define SPI_MEM_S_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI_MEM_S_MST_ST_END_INT_CLR_M  (SPI_MEM_S_MST_ST_END_INT_CLR_V << SPI_MEM_S_MST_ST_END_INT_CLR_S)
+#define SPI_MEM_S_MST_ST_END_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_MST_ST_END_INT_CLR_S  4
+/** SPI_MEM_S_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The clear bit for SPI_MEM_S_ECC_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_ECC_ERR_INT_CLR    (BIT(5))
+#define SPI_MEM_S_ECC_ERR_INT_CLR_M  (SPI_MEM_S_ECC_ERR_INT_CLR_V << SPI_MEM_S_ECC_ERR_INT_CLR_S)
+#define SPI_MEM_S_ECC_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_ECC_ERR_INT_CLR_S  5
+/** SPI_MEM_S_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The clear bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
+ */
+#define SPI_MEM_S_PMS_REJECT_INT_CLR    (BIT(6))
+#define SPI_MEM_S_PMS_REJECT_INT_CLR_M  (SPI_MEM_S_PMS_REJECT_INT_CLR_V << SPI_MEM_S_PMS_REJECT_INT_CLR_S)
+#define SPI_MEM_S_PMS_REJECT_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_PMS_REJECT_INT_CLR_S  6
+/** SPI_MEM_S_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The clear bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR    (BIT(7))
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_M  (SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_S)
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_S  7
+/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The clear bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_M  (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_S)
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_S  8
+/** SPI_MEM_S_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR    (BIT(9))
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_M  (SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S)
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S  9
+/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
+ */
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR    (BIT(28))
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_M  (SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_S)
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_S  28
+/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  The clear bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
+ */
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR    (BIT(29))
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_M  (SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_S)
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_S  29
+/** SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  The clear bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
+ */
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR    (BIT(30))
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_M  (SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_S)
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_S  30
+/** SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  The clear bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
+ */
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR    (BIT(31))
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_M  (SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_S)
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_S  31
+
+/** SPI_MEM_S_INT_RAW_REG register
+ *  SPI0 interrupt raw register
+ */
+#define SPI_MEM_S_INT_RAW_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc8)
+/** SPI_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
+ *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
+ *  Others
+ */
+#define SPI_MEM_S_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI_MEM_S_SLV_ST_END_INT_RAW_M  (SPI_MEM_S_SLV_ST_END_INT_RAW_V << SPI_MEM_S_SLV_ST_END_INT_RAW_S)
+#define SPI_MEM_S_SLV_ST_END_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_SLV_ST_END_INT_RAW_S  3
+/** SPI_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
+ *  changed from non idle state to idle state. 0: Others.
+ */
+#define SPI_MEM_S_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI_MEM_S_MST_ST_END_INT_RAW_M  (SPI_MEM_S_MST_ST_END_INT_RAW_V << SPI_MEM_S_MST_ST_END_INT_RAW_S)
+#define SPI_MEM_S_MST_ST_END_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_MST_ST_END_INT_RAW_S  4
+/** SPI_MEM_S_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is set
+ *  and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
+ *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When
+ *  SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is
+ *  triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
+ *  than SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and
+ *  SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+ *  of SPI0/1 ECC read external RAM and flash are equal or bigger than
+ *  SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN
+ *  are cleared, this bit will not be triggered.
+ */
+#define SPI_MEM_S_ECC_ERR_INT_RAW    (BIT(5))
+#define SPI_MEM_S_ECC_ERR_INT_RAW_M  (SPI_MEM_S_ECC_ERR_INT_RAW_V << SPI_MEM_S_ECC_ERR_INT_RAW_S)
+#define SPI_MEM_S_ECC_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_ECC_ERR_INT_RAW_S  5
+/** SPI_MEM_S_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
+ *  rejected. 0: Others.
+ */
+#define SPI_MEM_S_PMS_REJECT_INT_RAW    (BIT(6))
+#define SPI_MEM_S_PMS_REJECT_INT_RAW_M  (SPI_MEM_S_PMS_REJECT_INT_RAW_V << SPI_MEM_S_PMS_REJECT_INT_RAW_S)
+#define SPI_MEM_S_PMS_REJECT_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_PMS_REJECT_INT_RAW_S  6
+/** SPI_MEM_S_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+ *  address is invalid by compared to MMU configuration. 0: Others.
+ */
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW    (BIT(7))
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_M  (SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_S)
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_S  7
+/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
+ *  flash request is received. 0: Others.
+ */
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_M  (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_S)
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_S  8
+/** SPI_MEM_S_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+ *  address is invalid by compared to MMU configuration. 0: Others.
+ */
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW    (BIT(9))
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_M  (SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S)
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S  9
+/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
+ *  connected to SPI_DQS1 is overflow.
+ */
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW    (BIT(28))
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_M  (SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_S)
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_S  28
+/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  The raw bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
+ *  connected to SPI_DQS is overflow.
+ */
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW    (BIT(29))
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_M  (SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_S)
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_S  29
+/** SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is
+ *  underflow.
+ */
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW    (BIT(30))
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_M  (SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S)
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S  30
+/** SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is
+ *  underflow.
+ */
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW    (BIT(31))
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_M  (SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_S)
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_S  31
+
+/** SPI_MEM_S_INT_ST_REG register
+ *  SPI0 interrupt status register
+ */
+#define SPI_MEM_S_INT_ST_REG (DR_REG_PSRAM_MSPI0_BASE + 0xcc)
+/** SPI_MEM_S_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
+ */
+#define SPI_MEM_S_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI_MEM_S_SLV_ST_END_INT_ST_M  (SPI_MEM_S_SLV_ST_END_INT_ST_V << SPI_MEM_S_SLV_ST_END_INT_ST_S)
+#define SPI_MEM_S_SLV_ST_END_INT_ST_V  0x00000001U
+#define SPI_MEM_S_SLV_ST_END_INT_ST_S  3
+/** SPI_MEM_S_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI_MEM_S_MST_ST_END_INT interrupt.
+ */
+#define SPI_MEM_S_MST_ST_END_INT_ST    (BIT(4))
+#define SPI_MEM_S_MST_ST_END_INT_ST_M  (SPI_MEM_S_MST_ST_END_INT_ST_V << SPI_MEM_S_MST_ST_END_INT_ST_S)
+#define SPI_MEM_S_MST_ST_END_INT_ST_V  0x00000001U
+#define SPI_MEM_S_MST_ST_END_INT_ST_S  4
+/** SPI_MEM_S_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The status bit for SPI_MEM_S_ECC_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_ECC_ERR_INT_ST    (BIT(5))
+#define SPI_MEM_S_ECC_ERR_INT_ST_M  (SPI_MEM_S_ECC_ERR_INT_ST_V << SPI_MEM_S_ECC_ERR_INT_ST_S)
+#define SPI_MEM_S_ECC_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_S_ECC_ERR_INT_ST_S  5
+/** SPI_MEM_S_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The status bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
+ */
+#define SPI_MEM_S_PMS_REJECT_INT_ST    (BIT(6))
+#define SPI_MEM_S_PMS_REJECT_INT_ST_M  (SPI_MEM_S_PMS_REJECT_INT_ST_V << SPI_MEM_S_PMS_REJECT_INT_ST_S)
+#define SPI_MEM_S_PMS_REJECT_INT_ST_V  0x00000001U
+#define SPI_MEM_S_PMS_REJECT_INT_ST_S  6
+/** SPI_MEM_S_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST    (BIT(7))
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_M  (SPI_MEM_S_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_S_AXI_RADDR_ERR_INT_ST_S)
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_S  7
+/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_M  (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_S)
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_S  8
+/** SPI_MEM_S_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST    (BIT(9))
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_M  (SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S)
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S  9
+/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0;
+ *  The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
+ */
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST    (BIT(28))
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_M  (SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_S)
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_V  0x00000001U
+#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_S  28
+/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0;
+ *  The status bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
+ */
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST    (BIT(29))
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_M  (SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_S)
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_V  0x00000001U
+#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_S  29
+/** SPI_MEM_S_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0;
+ *  The status bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
+ */
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST    (BIT(30))
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_M  (SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_S)
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_S  30
+/** SPI_MEM_S_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0;
+ *  The status bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
+ */
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST    (BIT(31))
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_M  (SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_S)
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_V  0x00000001U
+#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_S  31
+
+/** SPI_MEM_S_DDR_REG register
+ *  SPI0 flash DDR mode control register
+ */
+#define SPI_MEM_S_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd4)
+/** SPI_MEM_S_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
+ *  1: in DDR mode,  0 in SDR mode
+ */
+#define SPI_MEM_S_FMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_S_FMEM_DDR_EN_M  (SPI_MEM_S_FMEM_DDR_EN_V << SPI_MEM_S_FMEM_DDR_EN_S)
+#define SPI_MEM_S_FMEM_DDR_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_DDR_EN_S  0
+/** SPI_MEM_S_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
+ *  Set the bit to enable variable dummy cycle in spi DDR mode.
+ */
+#define SPI_MEM_S_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_S_FMEM_VAR_DUMMY_M  (SPI_MEM_S_FMEM_VAR_DUMMY_V << SPI_MEM_S_FMEM_VAR_DUMMY_S)
+#define SPI_MEM_S_FMEM_VAR_DUMMY_V  0x00000001U
+#define SPI_MEM_S_FMEM_VAR_DUMMY_S  1
+/** SPI_MEM_S_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
+ *  Set the bit to reorder rx data of the word in spi DDR mode.
+ */
+#define SPI_MEM_S_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_M  (SPI_MEM_S_FMEM_DDR_RDAT_SWP_V << SPI_MEM_S_FMEM_DDR_RDAT_SWP_S)
+#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_S  2
+/** SPI_MEM_S_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
+ *  Set the bit to reorder tx data of the word in spi DDR mode.
+ */
+#define SPI_MEM_S_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_M  (SPI_MEM_S_FMEM_DDR_WDAT_SWP_V << SPI_MEM_S_FMEM_DDR_WDAT_SWP_S)
+#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_S  3
+/** SPI_MEM_S_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
+ *  the bit is used to disable dual edge in command phase when DDR mode.
+ */
+#define SPI_MEM_S_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_S_FMEM_DDR_CMD_DIS_M  (SPI_MEM_S_FMEM_DDR_CMD_DIS_V << SPI_MEM_S_FMEM_DDR_CMD_DIS_S)
+#define SPI_MEM_S_FMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI_MEM_S_FMEM_DDR_CMD_DIS_S  4
+/** SPI_MEM_S_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
+ *  It is the minimum output data length in the panda device.
+ */
+#define SPI_MEM_S_FMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI_MEM_S_FMEM_OUTMINBYTELEN_M  (SPI_MEM_S_FMEM_OUTMINBYTELEN_V << SPI_MEM_S_FMEM_OUTMINBYTELEN_S)
+#define SPI_MEM_S_FMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI_MEM_S_FMEM_OUTMINBYTELEN_S  5
+/** SPI_MEM_S_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ *  accesses to flash.
+ */
+#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_M  (SPI_MEM_S_FMEM_TX_DDR_MSK_EN_V << SPI_MEM_S_FMEM_TX_DDR_MSK_EN_S)
+#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_S  12
+/** SPI_MEM_S_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+ *  accesses to flash.
+ */
+#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_M  (SPI_MEM_S_FMEM_RX_DDR_MSK_EN_V << SPI_MEM_S_FMEM_RX_DDR_MSK_EN_S)
+#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_S  13
+/** SPI_MEM_S_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
+ *  The delay number of data strobe which from memory based on SPI clock.
+ */
+#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_M  (SPI_MEM_S_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_S_FMEM_USR_DDR_DQS_THD_S)
+#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_S  14
+/** SPI_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
+ *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+ *  spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
+ *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+ *  negative edge of SPI_DQS.
+ */
+#define SPI_MEM_S_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_M  (SPI_MEM_S_FMEM_DDR_DQS_LOOP_V << SPI_MEM_S_FMEM_DDR_DQS_LOOP_S)
+#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_S  21
+/** SPI_MEM_S_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
+ *  Set this bit to enable the differential SPI_CLK#.
+ */
+#define SPI_MEM_S_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_S_FMEM_CLK_DIFF_EN_M  (SPI_MEM_S_FMEM_CLK_DIFF_EN_V << SPI_MEM_S_FMEM_CLK_DIFF_EN_S)
+#define SPI_MEM_S_FMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_CLK_DIFF_EN_S  24
+/** SPI_MEM_S_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+ */
+#define SPI_MEM_S_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_S_FMEM_DQS_CA_IN_M  (SPI_MEM_S_FMEM_DQS_CA_IN_V << SPI_MEM_S_FMEM_DQS_CA_IN_S)
+#define SPI_MEM_S_FMEM_DQS_CA_IN_V  0x00000001U
+#define SPI_MEM_S_FMEM_DQS_CA_IN_S  26
+/** SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+ *  accesses flash or SPI1 accesses flash or sram.
+ */
+#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_M  (SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI_MEM_S_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to invert SPI_DIFF when accesses to flash. .
+ */
+#define SPI_MEM_S_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_S_FMEM_CLK_DIFF_INV_M  (SPI_MEM_S_FMEM_CLK_DIFF_INV_V << SPI_MEM_S_FMEM_CLK_DIFF_INV_S)
+#define SPI_MEM_S_FMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI_MEM_S_FMEM_CLK_DIFF_INV_S  28
+/** SPI_MEM_S_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
+ *  Set this bit to enable octa_ram address out when accesses to flash, which means
+ *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
+ */
+#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_M  (SPI_MEM_S_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_S_FMEM_OCTA_RAM_ADDR_S)
+#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_S  29
+/** SPI_MEM_S_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to enable HyperRAM address out when accesses to flash, which means
+ *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+ */
+#define SPI_MEM_S_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_S_FMEM_HYPERBUS_CA_M  (SPI_MEM_S_FMEM_HYPERBUS_CA_V << SPI_MEM_S_FMEM_HYPERBUS_CA_S)
+#define SPI_MEM_S_FMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI_MEM_S_FMEM_HYPERBUS_CA_S  30
+
+/** SPI_MEM_S_SMEM_DDR_REG register
+ *  SPI0 external RAM DDR mode control register
+ */
+#define SPI_MEM_S_SMEM_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd8)
+/** SPI_MEM_S_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
+ *  1: in DDR mode,  0 in SDR mode
+ */
+#define SPI_MEM_S_SMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_S_SMEM_DDR_EN_M  (SPI_MEM_S_SMEM_DDR_EN_V << SPI_MEM_S_SMEM_DDR_EN_S)
+#define SPI_MEM_S_SMEM_DDR_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_DDR_EN_S  0
+/** SPI_MEM_S_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
+ *  Set the bit to enable variable dummy cycle in spi DDR mode.
+ */
+#define SPI_MEM_S_SMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_S_SMEM_VAR_DUMMY_M  (SPI_MEM_S_SMEM_VAR_DUMMY_V << SPI_MEM_S_SMEM_VAR_DUMMY_S)
+#define SPI_MEM_S_SMEM_VAR_DUMMY_V  0x00000001U
+#define SPI_MEM_S_SMEM_VAR_DUMMY_S  1
+/** SPI_MEM_S_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
+ *  Set the bit to reorder rx data of the word in spi DDR mode.
+ */
+#define SPI_MEM_S_SMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_M  (SPI_MEM_S_SMEM_DDR_RDAT_SWP_V << SPI_MEM_S_SMEM_DDR_RDAT_SWP_S)
+#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_S  2
+/** SPI_MEM_S_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
+ *  Set the bit to reorder tx data of the word in spi DDR mode.
+ */
+#define SPI_MEM_S_SMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_M  (SPI_MEM_S_SMEM_DDR_WDAT_SWP_V << SPI_MEM_S_SMEM_DDR_WDAT_SWP_S)
+#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_S  3
+/** SPI_MEM_S_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
+ *  the bit is used to disable dual edge in command phase when DDR mode.
+ */
+#define SPI_MEM_S_SMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_S_SMEM_DDR_CMD_DIS_M  (SPI_MEM_S_SMEM_DDR_CMD_DIS_V << SPI_MEM_S_SMEM_DDR_CMD_DIS_S)
+#define SPI_MEM_S_SMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI_MEM_S_SMEM_DDR_CMD_DIS_S  4
+/** SPI_MEM_S_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
+ *  It is the minimum output data length in the DDR psram.
+ */
+#define SPI_MEM_S_SMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI_MEM_S_SMEM_OUTMINBYTELEN_M  (SPI_MEM_S_SMEM_OUTMINBYTELEN_V << SPI_MEM_S_SMEM_OUTMINBYTELEN_S)
+#define SPI_MEM_S_SMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI_MEM_S_SMEM_OUTMINBYTELEN_S  5
+/** SPI_MEM_S_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ *  accesses to external RAM.
+ */
+#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_M  (SPI_MEM_S_SMEM_TX_DDR_MSK_EN_V << SPI_MEM_S_SMEM_TX_DDR_MSK_EN_S)
+#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_S  12
+/** SPI_MEM_S_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+ *  accesses to external RAM.
+ */
+#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_M  (SPI_MEM_S_SMEM_RX_DDR_MSK_EN_V << SPI_MEM_S_SMEM_RX_DDR_MSK_EN_S)
+#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_S  13
+/** SPI_MEM_S_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
+ *  The delay number of data strobe which from memory based on SPI clock.
+ */
+#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_M  (SPI_MEM_S_SMEM_USR_DDR_DQS_THD_V << SPI_MEM_S_SMEM_USR_DDR_DQS_THD_S)
+#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_S  14
+/** SPI_MEM_S_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
+ *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+ *  spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
+ *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+ *  negative edge of SPI_DQS.
+ */
+#define SPI_MEM_S_SMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_M  (SPI_MEM_S_SMEM_DDR_DQS_LOOP_V << SPI_MEM_S_SMEM_DDR_DQS_LOOP_S)
+#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_S  21
+/** SPI_MEM_S_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
+ *  Set this bit to enable the differential SPI_CLK#.
+ */
+#define SPI_MEM_S_SMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_S_SMEM_CLK_DIFF_EN_M  (SPI_MEM_S_SMEM_CLK_DIFF_EN_V << SPI_MEM_S_SMEM_CLK_DIFF_EN_S)
+#define SPI_MEM_S_SMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_CLK_DIFF_EN_S  24
+/** SPI_MEM_S_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+ */
+#define SPI_MEM_S_SMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_S_SMEM_DQS_CA_IN_M  (SPI_MEM_S_SMEM_DQS_CA_IN_V << SPI_MEM_S_SMEM_DQS_CA_IN_S)
+#define SPI_MEM_S_SMEM_DQS_CA_IN_V  0x00000001U
+#define SPI_MEM_S_SMEM_DQS_CA_IN_S  26
+/** SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+ *  accesses flash or SPI1 accesses flash or sram.
+ */
+#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_M  (SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI_MEM_S_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to invert SPI_DIFF when accesses to external RAM. .
+ */
+#define SPI_MEM_S_SMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_S_SMEM_CLK_DIFF_INV_M  (SPI_MEM_S_SMEM_CLK_DIFF_INV_V << SPI_MEM_S_SMEM_CLK_DIFF_INV_S)
+#define SPI_MEM_S_SMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI_MEM_S_SMEM_CLK_DIFF_INV_S  28
+/** SPI_MEM_S_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
+ *  Set this bit to enable octa_ram address out when accesses to external RAM, which
+ *  means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1],
+ *  1'b0}.
+ */
+#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_M  (SPI_MEM_S_SMEM_OCTA_RAM_ADDR_V << SPI_MEM_S_SMEM_OCTA_RAM_ADDR_S)
+#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_S  29
+/** SPI_MEM_S_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to enable HyperRAM address out when accesses to external RAM, which
+ *  means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+ */
+#define SPI_MEM_S_SMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_S_SMEM_HYPERBUS_CA_M  (SPI_MEM_S_SMEM_HYPERBUS_CA_V << SPI_MEM_S_SMEM_HYPERBUS_CA_S)
+#define SPI_MEM_S_SMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI_MEM_S_SMEM_HYPERBUS_CA_S  30
+
+/** SPI_MEM_S_FMEM_PMS0_ATTR_REG register
+ *  MSPI flash PMS section $n attribute register
+ */
+#define SPI_MEM_S_FMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x100)
+/** SPI_MEM_S_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 flash PMS section $n read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_FMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_M  (SPI_MEM_S_FMEM_PMS0_RD_ATTR_V << SPI_MEM_S_FMEM_PMS0_RD_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_S  0
+/** SPI_MEM_S_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 flash PMS section $n write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_FMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_M  (SPI_MEM_S_FMEM_PMS0_WR_ATTR_V << SPI_MEM_S_FMEM_PMS0_WR_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_S  1
+/** SPI_MEM_S_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ *  PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and
+ *  SPI_MEM_S_FMEM_PMS$n_SIZE_REG.
+ */
+#define SPI_MEM_S_FMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_S_FMEM_PMS0_ECC_M  (SPI_MEM_S_FMEM_PMS0_ECC_V << SPI_MEM_S_FMEM_PMS0_ECC_S)
+#define SPI_MEM_S_FMEM_PMS0_ECC_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS0_ECC_S  2
+
+/** SPI_MEM_S_FMEM_PMS1_ATTR_REG register
+ *  SPI1 flash PMS section $n attribute register
+ */
+#define SPI_MEM_S_FMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x104)
+/** SPI_MEM_S_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 flash PMS section $n read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_FMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_M  (SPI_MEM_S_FMEM_PMS1_RD_ATTR_V << SPI_MEM_S_FMEM_PMS1_RD_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_S  0
+/** SPI_MEM_S_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 flash PMS section $n write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_FMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_M  (SPI_MEM_S_FMEM_PMS1_WR_ATTR_V << SPI_MEM_S_FMEM_PMS1_WR_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_S  1
+/** SPI_MEM_S_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ *  PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and
+ *  SPI_MEM_S_FMEM_PMS$n_SIZE_REG.
+ */
+#define SPI_MEM_S_FMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_S_FMEM_PMS1_ECC_M  (SPI_MEM_S_FMEM_PMS1_ECC_V << SPI_MEM_S_FMEM_PMS1_ECC_S)
+#define SPI_MEM_S_FMEM_PMS1_ECC_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS1_ECC_S  2
+
+/** SPI_MEM_S_FMEM_PMS2_ATTR_REG register
+ *  SPI1 flash PMS section $n attribute register
+ */
+#define SPI_MEM_S_FMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x108)
+/** SPI_MEM_S_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 flash PMS section $n read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_FMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_M  (SPI_MEM_S_FMEM_PMS2_RD_ATTR_V << SPI_MEM_S_FMEM_PMS2_RD_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_S  0
+/** SPI_MEM_S_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 flash PMS section $n write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_FMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_M  (SPI_MEM_S_FMEM_PMS2_WR_ATTR_V << SPI_MEM_S_FMEM_PMS2_WR_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_S  1
+/** SPI_MEM_S_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ *  PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and
+ *  SPI_MEM_S_FMEM_PMS$n_SIZE_REG.
+ */
+#define SPI_MEM_S_FMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_S_FMEM_PMS2_ECC_M  (SPI_MEM_S_FMEM_PMS2_ECC_V << SPI_MEM_S_FMEM_PMS2_ECC_S)
+#define SPI_MEM_S_FMEM_PMS2_ECC_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS2_ECC_S  2
+
+/** SPI_MEM_S_FMEM_PMS3_ATTR_REG register
+ *  SPI1 flash PMS section $n attribute register
+ */
+#define SPI_MEM_S_FMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10c)
+/** SPI_MEM_S_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 flash PMS section $n read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_FMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_M  (SPI_MEM_S_FMEM_PMS3_RD_ATTR_V << SPI_MEM_S_FMEM_PMS3_RD_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_S  0
+/** SPI_MEM_S_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 flash PMS section $n write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_FMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_M  (SPI_MEM_S_FMEM_PMS3_WR_ATTR_V << SPI_MEM_S_FMEM_PMS3_WR_ATTR_S)
+#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_S  1
+/** SPI_MEM_S_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ *  PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and
+ *  SPI_MEM_S_FMEM_PMS$n_SIZE_REG.
+ */
+#define SPI_MEM_S_FMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_S_FMEM_PMS3_ECC_M  (SPI_MEM_S_FMEM_PMS3_ECC_V << SPI_MEM_S_FMEM_PMS3_ECC_S)
+#define SPI_MEM_S_FMEM_PMS3_ECC_V  0x00000001U
+#define SPI_MEM_S_FMEM_PMS3_ECC_S  2
+
+/** SPI_MEM_S_FMEM_PMS0_ADDR_REG register
+ *  SPI1 flash PMS section $n start address register
+ */
+#define SPI_MEM_S_FMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x110)
+/** SPI_MEM_S_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+ *  SPI1 flash PMS section $n start address value
+ */
+#define SPI_MEM_S_FMEM_PMS0_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS0_ADDR_S_M  (SPI_MEM_S_FMEM_PMS0_ADDR_S_V << SPI_MEM_S_FMEM_PMS0_ADDR_S_S)
+#define SPI_MEM_S_FMEM_PMS0_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS0_ADDR_S_S  0
+
+/** SPI_MEM_S_FMEM_PMS1_ADDR_REG register
+ *  SPI1 flash PMS section $n start address register
+ */
+#define SPI_MEM_S_FMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x114)
+/** SPI_MEM_S_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 16777215;
+ *  SPI1 flash PMS section $n start address value
+ */
+#define SPI_MEM_S_FMEM_PMS1_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS1_ADDR_S_M  (SPI_MEM_S_FMEM_PMS1_ADDR_S_V << SPI_MEM_S_FMEM_PMS1_ADDR_S_S)
+#define SPI_MEM_S_FMEM_PMS1_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS1_ADDR_S_S  0
+
+/** SPI_MEM_S_FMEM_PMS2_ADDR_REG register
+ *  SPI1 flash PMS section $n start address register
+ */
+#define SPI_MEM_S_FMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x118)
+/** SPI_MEM_S_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 33554431;
+ *  SPI1 flash PMS section $n start address value
+ */
+#define SPI_MEM_S_FMEM_PMS2_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS2_ADDR_S_M  (SPI_MEM_S_FMEM_PMS2_ADDR_S_V << SPI_MEM_S_FMEM_PMS2_ADDR_S_S)
+#define SPI_MEM_S_FMEM_PMS2_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS2_ADDR_S_S  0
+
+/** SPI_MEM_S_FMEM_PMS3_ADDR_REG register
+ *  SPI1 flash PMS section $n start address register
+ */
+#define SPI_MEM_S_FMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x11c)
+/** SPI_MEM_S_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 50331647;
+ *  SPI1 flash PMS section $n start address value
+ */
+#define SPI_MEM_S_FMEM_PMS3_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS3_ADDR_S_M  (SPI_MEM_S_FMEM_PMS3_ADDR_S_V << SPI_MEM_S_FMEM_PMS3_ADDR_S_S)
+#define SPI_MEM_S_FMEM_PMS3_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_FMEM_PMS3_ADDR_S_S  0
+
+/** SPI_MEM_S_FMEM_PMS0_SIZE_REG register
+ *  SPI1 flash PMS section $n start address register
+ */
+#define SPI_MEM_S_FMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x120)
+/** SPI_MEM_S_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S,
+ *  SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE)
+ */
+#define SPI_MEM_S_FMEM_PMS0_SIZE    0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS0_SIZE_M  (SPI_MEM_S_FMEM_PMS0_SIZE_V << SPI_MEM_S_FMEM_PMS0_SIZE_S)
+#define SPI_MEM_S_FMEM_PMS0_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS0_SIZE_S  0
+
+/** SPI_MEM_S_FMEM_PMS1_SIZE_REG register
+ *  SPI1 flash PMS section $n start address register
+ */
+#define SPI_MEM_S_FMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x124)
+/** SPI_MEM_S_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S,
+ *  SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE)
+ */
+#define SPI_MEM_S_FMEM_PMS1_SIZE    0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS1_SIZE_M  (SPI_MEM_S_FMEM_PMS1_SIZE_V << SPI_MEM_S_FMEM_PMS1_SIZE_S)
+#define SPI_MEM_S_FMEM_PMS1_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS1_SIZE_S  0
+
+/** SPI_MEM_S_FMEM_PMS2_SIZE_REG register
+ *  SPI1 flash PMS section $n start address register
+ */
+#define SPI_MEM_S_FMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x128)
+/** SPI_MEM_S_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S,
+ *  SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE)
+ */
+#define SPI_MEM_S_FMEM_PMS2_SIZE    0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS2_SIZE_M  (SPI_MEM_S_FMEM_PMS2_SIZE_V << SPI_MEM_S_FMEM_PMS2_SIZE_S)
+#define SPI_MEM_S_FMEM_PMS2_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS2_SIZE_S  0
+
+/** SPI_MEM_S_FMEM_PMS3_SIZE_REG register
+ *  SPI1 flash PMS section $n start address register
+ */
+#define SPI_MEM_S_FMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x12c)
+/** SPI_MEM_S_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S,
+ *  SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE)
+ */
+#define SPI_MEM_S_FMEM_PMS3_SIZE    0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS3_SIZE_M  (SPI_MEM_S_FMEM_PMS3_SIZE_V << SPI_MEM_S_FMEM_PMS3_SIZE_S)
+#define SPI_MEM_S_FMEM_PMS3_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_FMEM_PMS3_SIZE_S  0
+
+/** SPI_MEM_S_SMEM_PMS0_ATTR_REG register
+ *  SPI1 flash PMS section $n start address register
+ */
+#define SPI_MEM_S_SMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x130)
+/** SPI_MEM_S_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_SMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_M  (SPI_MEM_S_SMEM_PMS0_RD_ATTR_V << SPI_MEM_S_SMEM_PMS0_RD_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_S  0
+/** SPI_MEM_S_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_SMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_M  (SPI_MEM_S_SMEM_PMS0_WR_ATTR_V << SPI_MEM_S_SMEM_PMS0_WR_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_S  1
+/** SPI_MEM_S_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The
+ *  external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and
+ *  SPI_MEM_S_SMEM_PMS$n_SIZE_REG.
+ */
+#define SPI_MEM_S_SMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_S_SMEM_PMS0_ECC_M  (SPI_MEM_S_SMEM_PMS0_ECC_V << SPI_MEM_S_SMEM_PMS0_ECC_S)
+#define SPI_MEM_S_SMEM_PMS0_ECC_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS0_ECC_S  2
+
+/** SPI_MEM_S_SMEM_PMS1_ATTR_REG register
+ *  SPI1 external RAM PMS section $n attribute register
+ */
+#define SPI_MEM_S_SMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x134)
+/** SPI_MEM_S_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_SMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_M  (SPI_MEM_S_SMEM_PMS1_RD_ATTR_V << SPI_MEM_S_SMEM_PMS1_RD_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_S  0
+/** SPI_MEM_S_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_SMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_M  (SPI_MEM_S_SMEM_PMS1_WR_ATTR_V << SPI_MEM_S_SMEM_PMS1_WR_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_S  1
+/** SPI_MEM_S_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The
+ *  external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and
+ *  SPI_MEM_S_SMEM_PMS$n_SIZE_REG.
+ */
+#define SPI_MEM_S_SMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_S_SMEM_PMS1_ECC_M  (SPI_MEM_S_SMEM_PMS1_ECC_V << SPI_MEM_S_SMEM_PMS1_ECC_S)
+#define SPI_MEM_S_SMEM_PMS1_ECC_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS1_ECC_S  2
+
+/** SPI_MEM_S_SMEM_PMS2_ATTR_REG register
+ *  SPI1 external RAM PMS section $n attribute register
+ */
+#define SPI_MEM_S_SMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x138)
+/** SPI_MEM_S_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_SMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_M  (SPI_MEM_S_SMEM_PMS2_RD_ATTR_V << SPI_MEM_S_SMEM_PMS2_RD_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_S  0
+/** SPI_MEM_S_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_SMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_M  (SPI_MEM_S_SMEM_PMS2_WR_ATTR_V << SPI_MEM_S_SMEM_PMS2_WR_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_S  1
+/** SPI_MEM_S_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The
+ *  external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and
+ *  SPI_MEM_S_SMEM_PMS$n_SIZE_REG.
+ */
+#define SPI_MEM_S_SMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_S_SMEM_PMS2_ECC_M  (SPI_MEM_S_SMEM_PMS2_ECC_V << SPI_MEM_S_SMEM_PMS2_ECC_S)
+#define SPI_MEM_S_SMEM_PMS2_ECC_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS2_ECC_S  2
+
+/** SPI_MEM_S_SMEM_PMS3_ATTR_REG register
+ *  SPI1 external RAM PMS section $n attribute register
+ */
+#define SPI_MEM_S_SMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x13c)
+/** SPI_MEM_S_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
+ *  1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_SMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_M  (SPI_MEM_S_SMEM_PMS3_RD_ATTR_V << SPI_MEM_S_SMEM_PMS3_RD_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_S  0
+/** SPI_MEM_S_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
+ *  1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.
+ */
+#define SPI_MEM_S_SMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_M  (SPI_MEM_S_SMEM_PMS3_WR_ATTR_V << SPI_MEM_S_SMEM_PMS3_WR_ATTR_S)
+#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_S  1
+/** SPI_MEM_S_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
+ *  SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The
+ *  external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and
+ *  SPI_MEM_S_SMEM_PMS$n_SIZE_REG.
+ */
+#define SPI_MEM_S_SMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_S_SMEM_PMS3_ECC_M  (SPI_MEM_S_SMEM_PMS3_ECC_V << SPI_MEM_S_SMEM_PMS3_ECC_S)
+#define SPI_MEM_S_SMEM_PMS3_ECC_V  0x00000001U
+#define SPI_MEM_S_SMEM_PMS3_ECC_S  2
+
+/** SPI_MEM_S_SMEM_PMS0_ADDR_REG register
+ *  SPI1 external RAM PMS section $n start address register
+ */
+#define SPI_MEM_S_SMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x140)
+/** SPI_MEM_S_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
+ *  SPI1 external RAM PMS section $n start address value
+ */
+#define SPI_MEM_S_SMEM_PMS0_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS0_ADDR_S_M  (SPI_MEM_S_SMEM_PMS0_ADDR_S_V << SPI_MEM_S_SMEM_PMS0_ADDR_S_S)
+#define SPI_MEM_S_SMEM_PMS0_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS0_ADDR_S_S  0
+
+/** SPI_MEM_S_SMEM_PMS1_ADDR_REG register
+ *  SPI1 external RAM PMS section $n start address register
+ */
+#define SPI_MEM_S_SMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x144)
+/** SPI_MEM_S_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 16777215;
+ *  SPI1 external RAM PMS section $n start address value
+ */
+#define SPI_MEM_S_SMEM_PMS1_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS1_ADDR_S_M  (SPI_MEM_S_SMEM_PMS1_ADDR_S_V << SPI_MEM_S_SMEM_PMS1_ADDR_S_S)
+#define SPI_MEM_S_SMEM_PMS1_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS1_ADDR_S_S  0
+
+/** SPI_MEM_S_SMEM_PMS2_ADDR_REG register
+ *  SPI1 external RAM PMS section $n start address register
+ */
+#define SPI_MEM_S_SMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x148)
+/** SPI_MEM_S_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 33554431;
+ *  SPI1 external RAM PMS section $n start address value
+ */
+#define SPI_MEM_S_SMEM_PMS2_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS2_ADDR_S_M  (SPI_MEM_S_SMEM_PMS2_ADDR_S_V << SPI_MEM_S_SMEM_PMS2_ADDR_S_S)
+#define SPI_MEM_S_SMEM_PMS2_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS2_ADDR_S_S  0
+
+/** SPI_MEM_S_SMEM_PMS3_ADDR_REG register
+ *  SPI1 external RAM PMS section $n start address register
+ */
+#define SPI_MEM_S_SMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14c)
+/** SPI_MEM_S_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 50331647;
+ *  SPI1 external RAM PMS section $n start address value
+ */
+#define SPI_MEM_S_SMEM_PMS3_ADDR_S    0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS3_ADDR_S_M  (SPI_MEM_S_SMEM_PMS3_ADDR_S_V << SPI_MEM_S_SMEM_PMS3_ADDR_S_S)
+#define SPI_MEM_S_SMEM_PMS3_ADDR_S_V  0x07FFFFFFU
+#define SPI_MEM_S_SMEM_PMS3_ADDR_S_S  0
+
+/** SPI_MEM_S_SMEM_PMS0_SIZE_REG register
+ *  SPI1 external RAM PMS section $n start address register
+ */
+#define SPI_MEM_S_SMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x150)
+/** SPI_MEM_S_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S,
+ *  SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE)
+ */
+#define SPI_MEM_S_SMEM_PMS0_SIZE    0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS0_SIZE_M  (SPI_MEM_S_SMEM_PMS0_SIZE_V << SPI_MEM_S_SMEM_PMS0_SIZE_S)
+#define SPI_MEM_S_SMEM_PMS0_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS0_SIZE_S  0
+
+/** SPI_MEM_S_SMEM_PMS1_SIZE_REG register
+ *  SPI1 external RAM PMS section $n start address register
+ */
+#define SPI_MEM_S_SMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x154)
+/** SPI_MEM_S_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S,
+ *  SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE)
+ */
+#define SPI_MEM_S_SMEM_PMS1_SIZE    0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS1_SIZE_M  (SPI_MEM_S_SMEM_PMS1_SIZE_V << SPI_MEM_S_SMEM_PMS1_SIZE_S)
+#define SPI_MEM_S_SMEM_PMS1_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS1_SIZE_S  0
+
+/** SPI_MEM_S_SMEM_PMS2_SIZE_REG register
+ *  SPI1 external RAM PMS section $n start address register
+ */
+#define SPI_MEM_S_SMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x158)
+/** SPI_MEM_S_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S,
+ *  SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE)
+ */
+#define SPI_MEM_S_SMEM_PMS2_SIZE    0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS2_SIZE_M  (SPI_MEM_S_SMEM_PMS2_SIZE_V << SPI_MEM_S_SMEM_PMS2_SIZE_S)
+#define SPI_MEM_S_SMEM_PMS2_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS2_SIZE_S  0
+
+/** SPI_MEM_S_SMEM_PMS3_SIZE_REG register
+ *  SPI1 external RAM PMS section $n start address register
+ */
+#define SPI_MEM_S_SMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x15c)
+/** SPI_MEM_S_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
+ *  SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S,
+ *  SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE)
+ */
+#define SPI_MEM_S_SMEM_PMS3_SIZE    0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS3_SIZE_M  (SPI_MEM_S_SMEM_PMS3_SIZE_V << SPI_MEM_S_SMEM_PMS3_SIZE_S)
+#define SPI_MEM_S_SMEM_PMS3_SIZE_V  0x00007FFFU
+#define SPI_MEM_S_SMEM_PMS3_SIZE_S  0
+
+/** SPI_MEM_S_PMS_REJECT_REG register
+ *  SPI1 access reject register
+ */
+#define SPI_MEM_S_PMS_REJECT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x164)
+/** SPI_MEM_S_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
+ *  This bits show the first SPI1 access error address. It is cleared by when
+ *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
+ */
+#define SPI_MEM_S_REJECT_ADDR    0x07FFFFFFU
+#define SPI_MEM_S_REJECT_ADDR_M  (SPI_MEM_S_REJECT_ADDR_V << SPI_MEM_S_REJECT_ADDR_S)
+#define SPI_MEM_S_REJECT_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_S_REJECT_ADDR_S  0
+/** SPI_MEM_S_PM_EN : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to enable SPI0/1 transfer permission control function.
+ */
+#define SPI_MEM_S_PM_EN    (BIT(27))
+#define SPI_MEM_S_PM_EN_M  (SPI_MEM_S_PM_EN_V << SPI_MEM_S_PM_EN_S)
+#define SPI_MEM_S_PM_EN_V  0x00000001U
+#define SPI_MEM_S_PM_EN_S  27
+/** SPI_MEM_S_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0;
+ *  1: SPI1 write access error. 0: No write access error. It is cleared by when
+ *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
+ */
+#define SPI_MEM_S_PMS_LD    (BIT(28))
+#define SPI_MEM_S_PMS_LD_M  (SPI_MEM_S_PMS_LD_V << SPI_MEM_S_PMS_LD_S)
+#define SPI_MEM_S_PMS_LD_V  0x00000001U
+#define SPI_MEM_S_PMS_LD_S  28
+/** SPI_MEM_S_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0;
+ *  1: SPI1 read access error. 0: No read access error. It is cleared by when
+ *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
+ */
+#define SPI_MEM_S_PMS_ST    (BIT(29))
+#define SPI_MEM_S_PMS_ST_M  (SPI_MEM_S_PMS_ST_V << SPI_MEM_S_PMS_ST_S)
+#define SPI_MEM_S_PMS_ST_V  0x00000001U
+#define SPI_MEM_S_PMS_ST_S  29
+/** SPI_MEM_S_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0;
+ *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
+ *  cleared by when  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
+ */
+#define SPI_MEM_S_PMS_MULTI_HIT    (BIT(30))
+#define SPI_MEM_S_PMS_MULTI_HIT_M  (SPI_MEM_S_PMS_MULTI_HIT_V << SPI_MEM_S_PMS_MULTI_HIT_S)
+#define SPI_MEM_S_PMS_MULTI_HIT_V  0x00000001U
+#define SPI_MEM_S_PMS_MULTI_HIT_S  30
+/** SPI_MEM_S_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0;
+ *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
+ *  error. It is cleared by when  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
+ */
+#define SPI_MEM_S_PMS_IVD    (BIT(31))
+#define SPI_MEM_S_PMS_IVD_M  (SPI_MEM_S_PMS_IVD_V << SPI_MEM_S_PMS_IVD_S)
+#define SPI_MEM_S_PMS_IVD_V  0x00000001U
+#define SPI_MEM_S_PMS_IVD_S  31
+
+/** SPI_MEM_S_ECC_CTRL_REG register
+ *  MSPI ECC control register
+ */
+#define SPI_MEM_S_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x168)
+/** SPI_MEM_S_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0;
+ *  This bits show the error times of MSPI ECC read. It is cleared by when
+ *  SPI_MEM_S_ECC_ERR_INT_CLR bit is set.
+ */
+#define SPI_MEM_S_ECC_ERR_CNT    0x0000003FU
+#define SPI_MEM_S_ECC_ERR_CNT_M  (SPI_MEM_S_ECC_ERR_CNT_V << SPI_MEM_S_ECC_ERR_CNT_S)
+#define SPI_MEM_S_ECC_ERR_CNT_V  0x0000003FU
+#define SPI_MEM_S_ECC_ERR_CNT_S  5
+/** SPI_MEM_S_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10;
+ *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt.
+ */
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM    0x0000003FU
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_M  (SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_V << SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_S)
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_V  0x0000003FU
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_S  11
+/** SPI_MEM_S_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to calculate the error times of MSPI ECC read when accesses to flash.
+ */
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_M  (SPI_MEM_S_FMEM_ECC_ERR_INT_EN_V << SPI_MEM_S_FMEM_ECC_ERR_INT_EN_S)
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_S  17
+/** SPI_MEM_S_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0;
+ *  Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
+ *  1024 bytes. 3: 2048 bytes.
+ */
+#define SPI_MEM_S_FMEM_PAGE_SIZE    0x00000003U
+#define SPI_MEM_S_FMEM_PAGE_SIZE_M  (SPI_MEM_S_FMEM_PAGE_SIZE_V << SPI_MEM_S_FMEM_PAGE_SIZE_S)
+#define SPI_MEM_S_FMEM_PAGE_SIZE_V  0x00000003U
+#define SPI_MEM_S_FMEM_PAGE_SIZE_S  18
+/** SPI_MEM_S_FMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
+ *  ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit
+ *  should be 0. Otherwise, this bit should be 1.
+ */
+#define SPI_MEM_S_FMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_S_FMEM_ECC_ADDR_EN_M  (SPI_MEM_S_FMEM_ECC_ADDR_EN_V << SPI_MEM_S_FMEM_ECC_ADDR_EN_S)
+#define SPI_MEM_S_FMEM_ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_S_FMEM_ECC_ADDR_EN_S  20
+/** SPI_MEM_S_USR_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0;
+ *  Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.
+ */
+#define SPI_MEM_S_USR_ECC_ADDR_EN    (BIT(21))
+#define SPI_MEM_S_USR_ECC_ADDR_EN_M  (SPI_MEM_S_USR_ECC_ADDR_EN_V << SPI_MEM_S_USR_ECC_ADDR_EN_S)
+#define SPI_MEM_S_USR_ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_S_USR_ECC_ADDR_EN_S  21
+/** SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1;
+ *  1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is
+ *  updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and
+ *  SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information.
+ */
+#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
+#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_M  (SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_S)
+#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_V  0x00000001U
+#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_S  24
+/** SPI_MEM_S_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0;
+ *  Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to
+ *  byte 0 bit 0 to byte 15 bit 7)
+ */
+#define SPI_MEM_S_ECC_ERR_BITS    0x0000007FU
+#define SPI_MEM_S_ECC_ERR_BITS_M  (SPI_MEM_S_ECC_ERR_BITS_V << SPI_MEM_S_ECC_ERR_BITS_S)
+#define SPI_MEM_S_ECC_ERR_BITS_V  0x0000007FU
+#define SPI_MEM_S_ECC_ERR_BITS_S  25
+
+/** SPI_MEM_S_ECC_ERR_ADDR_REG register
+ *  MSPI ECC error address register
+ */
+#define SPI_MEM_S_ECC_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x16c)
+/** SPI_MEM_S_ECC_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
+ *  This bits show the first MSPI ECC error address. It is cleared by when
+ *  SPI_MEM_S_ECC_ERR_INT_CLR bit is set.
+ */
+#define SPI_MEM_S_ECC_ERR_ADDR    0x07FFFFFFU
+#define SPI_MEM_S_ECC_ERR_ADDR_M  (SPI_MEM_S_ECC_ERR_ADDR_V << SPI_MEM_S_ECC_ERR_ADDR_S)
+#define SPI_MEM_S_ECC_ERR_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_S_ECC_ERR_ADDR_S  0
+
+/** SPI_MEM_S_AXI_ERR_ADDR_REG register
+ *  SPI0 AXI request error address.
+ */
+#define SPI_MEM_S_AXI_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x170)
+/** SPI_MEM_S_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
+ *  This bits show the first AXI write/read invalid error or AXI write flash error
+ *  address. It is cleared by when SPI_MEM_S_AXI_WADDR_ERR_INT_CLR,
+ *  SPI_MEM_S_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_S_AXI_RADDR_ERR_IN_CLR bit is set.
+ */
+#define SPI_MEM_S_AXI_ERR_ADDR    0x07FFFFFFU
+#define SPI_MEM_S_AXI_ERR_ADDR_M  (SPI_MEM_S_AXI_ERR_ADDR_V << SPI_MEM_S_AXI_ERR_ADDR_S)
+#define SPI_MEM_S_AXI_ERR_ADDR_V  0x07FFFFFFU
+#define SPI_MEM_S_AXI_ERR_ADDR_S  0
+
+/** SPI_MEM_S_SMEM_ECC_CTRL_REG register
+ *  MSPI ECC control register
+ */
+#define SPI_MEM_S_SMEM_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x174)
+/** SPI_MEM_S_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to calculate the error times of MSPI ECC read when accesses to
+ *  external RAM.
+ */
+#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_M  (SPI_MEM_S_SMEM_ECC_ERR_INT_EN_V << SPI_MEM_S_SMEM_ECC_ERR_INT_EN_S)
+#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_S  17
+/** SPI_MEM_S_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2;
+ *  Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes.
+ *  2: 1024 bytes. 3: 2048 bytes.
+ */
+#define SPI_MEM_S_SMEM_PAGE_SIZE    0x00000003U
+#define SPI_MEM_S_SMEM_PAGE_SIZE_M  (SPI_MEM_S_SMEM_PAGE_SIZE_V << SPI_MEM_S_SMEM_PAGE_SIZE_S)
+#define SPI_MEM_S_SMEM_PAGE_SIZE_V  0x00000003U
+#define SPI_MEM_S_SMEM_PAGE_SIZE_S  18
+/** SPI_MEM_S_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
+ *  ECC region or non-ECC region of external RAM. If there is no ECC region in external
+ *  RAM, this bit should be 0. Otherwise, this bit should be 1.
+ */
+#define SPI_MEM_S_SMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_S_SMEM_ECC_ADDR_EN_M  (SPI_MEM_S_SMEM_ECC_ADDR_EN_V << SPI_MEM_S_SMEM_ECC_ADDR_EN_S)
+#define SPI_MEM_S_SMEM_ECC_ADDR_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_ECC_ADDR_EN_S  20
+
+/** SPI_MEM_S_SMEM_AXI_ADDR_CTRL_REG register
+ *  SPI0 AXI address control register
+ */
+#define SPI_MEM_S_SMEM_AXI_ADDR_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x178)
+/** SPI_MEM_S_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1;
+ *  The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
+ *  and SPI0 transfers are done. 0: Others.
+ */
+#define SPI_MEM_S_ALL_FIFO_EMPTY    (BIT(26))
+#define SPI_MEM_S_ALL_FIFO_EMPTY_M  (SPI_MEM_S_ALL_FIFO_EMPTY_V << SPI_MEM_S_ALL_FIFO_EMPTY_S)
+#define SPI_MEM_S_ALL_FIFO_EMPTY_V  0x00000001U
+#define SPI_MEM_S_ALL_FIFO_EMPTY_S  26
+/** SPI_MEM_S_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1;
+ *  1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.
+ */
+#define SPI_MEM_S_RDATA_AFIFO_REMPTY    (BIT(27))
+#define SPI_MEM_S_RDATA_AFIFO_REMPTY_M  (SPI_MEM_S_RDATA_AFIFO_REMPTY_V << SPI_MEM_S_RDATA_AFIFO_REMPTY_S)
+#define SPI_MEM_S_RDATA_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_S_RDATA_AFIFO_REMPTY_S  27
+/** SPI_MEM_S_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1;
+ *  1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.
+ */
+#define SPI_MEM_S_RADDR_AFIFO_REMPTY    (BIT(28))
+#define SPI_MEM_S_RADDR_AFIFO_REMPTY_M  (SPI_MEM_S_RADDR_AFIFO_REMPTY_V << SPI_MEM_S_RADDR_AFIFO_REMPTY_S)
+#define SPI_MEM_S_RADDR_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_S_RADDR_AFIFO_REMPTY_S  28
+/** SPI_MEM_S_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1;
+ *  1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.
+ */
+#define SPI_MEM_S_WDATA_AFIFO_REMPTY    (BIT(29))
+#define SPI_MEM_S_WDATA_AFIFO_REMPTY_M  (SPI_MEM_S_WDATA_AFIFO_REMPTY_V << SPI_MEM_S_WDATA_AFIFO_REMPTY_S)
+#define SPI_MEM_S_WDATA_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_S_WDATA_AFIFO_REMPTY_S  29
+/** SPI_MEM_S_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1;
+ *  1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.
+ */
+#define SPI_MEM_S_WBLEN_AFIFO_REMPTY    (BIT(30))
+#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_M  (SPI_MEM_S_WBLEN_AFIFO_REMPTY_V << SPI_MEM_S_WBLEN_AFIFO_REMPTY_S)
+#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_V  0x00000001U
+#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_S  30
+/** SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1;
+ *  This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and
+ *  RDATA_AFIFO are empty and spi0_mst_st is IDLE.
+ */
+#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
+#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_M  (SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_S)
+#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x00000001U
+#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
+
+/** SPI_MEM_S_AXI_ERR_RESP_EN_REG register
+ *  SPI0 AXI error response enable register
+ */
+#define SPI_MEM_S_AXI_ERR_RESP_EN_REG (DR_REG_PSRAM_MSPI0_BASE + 0x17c)
+/** SPI_MEM_S_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu valid err in axi write trans.
+ */
+#define SPI_MEM_S_AW_RESP_EN_MMU_VLD    (BIT(0))
+#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_M  (SPI_MEM_S_AW_RESP_EN_MMU_VLD_V << SPI_MEM_S_AW_RESP_EN_MMU_VLD_S)
+#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_S  0
+/** SPI_MEM_S_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu gid err in axi write trans.
+ */
+#define SPI_MEM_S_AW_RESP_EN_MMU_GID    (BIT(1))
+#define SPI_MEM_S_AW_RESP_EN_MMU_GID_M  (SPI_MEM_S_AW_RESP_EN_MMU_GID_V << SPI_MEM_S_AW_RESP_EN_MMU_GID_S)
+#define SPI_MEM_S_AW_RESP_EN_MMU_GID_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_MMU_GID_S  1
+/** SPI_MEM_S_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0;
+ *  Set this bit  to enable AXI response function for axi size err in axi write trans.
+ */
+#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE    (BIT(2))
+#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_M  (SPI_MEM_S_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_S_AW_RESP_EN_AXI_SIZE_S)
+#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_S  2
+/** SPI_MEM_S_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0;
+ *  Set this bit  to enable AXI response function for axi flash err in axi write trans.
+ */
+#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH    (BIT(3))
+#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_M  (SPI_MEM_S_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_S_AW_RESP_EN_AXI_FLASH_S)
+#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_S  3
+/** SPI_MEM_S_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu ecc err in axi write trans.
+ */
+#define SPI_MEM_S_AW_RESP_EN_MMU_ECC    (BIT(4))
+#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_M  (SPI_MEM_S_AW_RESP_EN_MMU_ECC_V << SPI_MEM_S_AW_RESP_EN_MMU_ECC_S)
+#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_S  4
+/** SPI_MEM_S_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu sens in err axi write trans.
+ */
+#define SPI_MEM_S_AW_RESP_EN_MMU_SENS    (BIT(5))
+#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_M  (SPI_MEM_S_AW_RESP_EN_MMU_SENS_V << SPI_MEM_S_AW_RESP_EN_MMU_SENS_S)
+#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_S  5
+/** SPI_MEM_S_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0;
+ *  Set this bit  to enable AXI response function for axi wstrb err in axi write trans.
+ */
+#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB    (BIT(6))
+#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_M  (SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_S)
+#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_V  0x00000001U
+#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_S  6
+/** SPI_MEM_S_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu valid err in axi read trans.
+ */
+#define SPI_MEM_S_AR_RESP_EN_MMU_VLD    (BIT(7))
+#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_M  (SPI_MEM_S_AR_RESP_EN_MMU_VLD_V << SPI_MEM_S_AR_RESP_EN_MMU_VLD_S)
+#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_V  0x00000001U
+#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_S  7
+/** SPI_MEM_S_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu gid err in axi read trans.
+ */
+#define SPI_MEM_S_AR_RESP_EN_MMU_GID    (BIT(8))
+#define SPI_MEM_S_AR_RESP_EN_MMU_GID_M  (SPI_MEM_S_AR_RESP_EN_MMU_GID_V << SPI_MEM_S_AR_RESP_EN_MMU_GID_S)
+#define SPI_MEM_S_AR_RESP_EN_MMU_GID_V  0x00000001U
+#define SPI_MEM_S_AR_RESP_EN_MMU_GID_S  8
+/** SPI_MEM_S_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu ecc err in axi read trans.
+ */
+#define SPI_MEM_S_AR_RESP_EN_MMU_ECC    (BIT(9))
+#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_M  (SPI_MEM_S_AR_RESP_EN_MMU_ECC_V << SPI_MEM_S_AR_RESP_EN_MMU_ECC_S)
+#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_V  0x00000001U
+#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_S  9
+/** SPI_MEM_S_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0;
+ *  Set this bit  to enable AXI response function for mmu sensitive err in axi read
+ *  trans.
+ */
+#define SPI_MEM_S_AR_RESP_EN_MMU_SENS    (BIT(10))
+#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_M  (SPI_MEM_S_AR_RESP_EN_MMU_SENS_V << SPI_MEM_S_AR_RESP_EN_MMU_SENS_S)
+#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_V  0x00000001U
+#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_S  10
+/** SPI_MEM_S_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0;
+ *  Set this bit  to enable AXI response function for axi size err in axi read trans.
+ */
+#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE    (BIT(11))
+#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_M  (SPI_MEM_S_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_S_AR_RESP_EN_AXI_SIZE_S)
+#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_V  0x00000001U
+#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_S  11
+
+/** SPI_MEM_S_TIMING_CALI_REG register
+ *  SPI0 flash timing calibration register
+ */
+#define SPI_MEM_S_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x180)
+/** SPI_MEM_S_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable timing adjust clock for all reading operations.
+ */
+#define SPI_MEM_S_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_S_TIMING_CLK_ENA_M  (SPI_MEM_S_TIMING_CLK_ENA_V << SPI_MEM_S_TIMING_CLK_ENA_S)
+#define SPI_MEM_S_TIMING_CLK_ENA_V  0x00000001U
+#define SPI_MEM_S_TIMING_CLK_ENA_S  0
+/** SPI_MEM_S_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable timing auto-calibration for all reading operations.
+ */
+#define SPI_MEM_S_TIMING_CALI    (BIT(1))
+#define SPI_MEM_S_TIMING_CALI_M  (SPI_MEM_S_TIMING_CALI_V << SPI_MEM_S_TIMING_CALI_S)
+#define SPI_MEM_S_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_S_TIMING_CALI_S  1
+/** SPI_MEM_S_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+ *  add extra dummy spi clock cycle length for spi clock calibration.
+ */
+#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_S  2
+/** SPI_MEM_S_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
+ *  flash.
+ */
+#define SPI_MEM_S_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_S_DLL_TIMING_CALI_M  (SPI_MEM_S_DLL_TIMING_CALI_V << SPI_MEM_S_DLL_TIMING_CALI_S)
+#define SPI_MEM_S_DLL_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_S_DLL_TIMING_CALI_S  5
+/** SPI_MEM_S_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0;
+ *  Set this bit to update delay mode, delay num and extra dummy in MSPI.
+ */
+#define SPI_MEM_S_TIMING_CALI_UPDATE    (BIT(6))
+#define SPI_MEM_S_TIMING_CALI_UPDATE_M  (SPI_MEM_S_TIMING_CALI_UPDATE_V << SPI_MEM_S_TIMING_CALI_UPDATE_S)
+#define SPI_MEM_S_TIMING_CALI_UPDATE_V  0x00000001U
+#define SPI_MEM_S_TIMING_CALI_UPDATE_S  6
+
+/** SPI_MEM_S_DIN_MODE_REG register
+ *  MSPI flash input timing delay mode control register
+ */
+#define SPI_MEM_S_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x184)
+/** SPI_MEM_S_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_DIN0_MODE    0x00000007U
+#define SPI_MEM_S_DIN0_MODE_M  (SPI_MEM_S_DIN0_MODE_V << SPI_MEM_S_DIN0_MODE_S)
+#define SPI_MEM_S_DIN0_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN0_MODE_S  0
+/** SPI_MEM_S_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_DIN1_MODE    0x00000007U
+#define SPI_MEM_S_DIN1_MODE_M  (SPI_MEM_S_DIN1_MODE_V << SPI_MEM_S_DIN1_MODE_S)
+#define SPI_MEM_S_DIN1_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN1_MODE_S  3
+/** SPI_MEM_S_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_DIN2_MODE    0x00000007U
+#define SPI_MEM_S_DIN2_MODE_M  (SPI_MEM_S_DIN2_MODE_V << SPI_MEM_S_DIN2_MODE_S)
+#define SPI_MEM_S_DIN2_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN2_MODE_S  6
+/** SPI_MEM_S_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_DIN3_MODE    0x00000007U
+#define SPI_MEM_S_DIN3_MODE_M  (SPI_MEM_S_DIN3_MODE_V << SPI_MEM_S_DIN3_MODE_S)
+#define SPI_MEM_S_DIN3_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN3_MODE_S  9
+/** SPI_MEM_S_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk
+ */
+#define SPI_MEM_S_DIN4_MODE    0x00000007U
+#define SPI_MEM_S_DIN4_MODE_M  (SPI_MEM_S_DIN4_MODE_V << SPI_MEM_S_DIN4_MODE_S)
+#define SPI_MEM_S_DIN4_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN4_MODE_S  12
+/** SPI_MEM_S_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk
+ */
+#define SPI_MEM_S_DIN5_MODE    0x00000007U
+#define SPI_MEM_S_DIN5_MODE_M  (SPI_MEM_S_DIN5_MODE_V << SPI_MEM_S_DIN5_MODE_S)
+#define SPI_MEM_S_DIN5_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN5_MODE_S  15
+/** SPI_MEM_S_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk
+ */
+#define SPI_MEM_S_DIN6_MODE    0x00000007U
+#define SPI_MEM_S_DIN6_MODE_M  (SPI_MEM_S_DIN6_MODE_V << SPI_MEM_S_DIN6_MODE_S)
+#define SPI_MEM_S_DIN6_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN6_MODE_S  18
+/** SPI_MEM_S_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk
+ */
+#define SPI_MEM_S_DIN7_MODE    0x00000007U
+#define SPI_MEM_S_DIN7_MODE_M  (SPI_MEM_S_DIN7_MODE_V << SPI_MEM_S_DIN7_MODE_S)
+#define SPI_MEM_S_DIN7_MODE_V  0x00000007U
+#define SPI_MEM_S_DIN7_MODE_S  21
+/** SPI_MEM_S_DINS_MODE : R/W; bitpos: [26:24]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk
+ */
+#define SPI_MEM_S_DINS_MODE    0x00000007U
+#define SPI_MEM_S_DINS_MODE_M  (SPI_MEM_S_DINS_MODE_V << SPI_MEM_S_DINS_MODE_S)
+#define SPI_MEM_S_DINS_MODE_V  0x00000007U
+#define SPI_MEM_S_DINS_MODE_S  24
+
+/** SPI_MEM_S_DIN_NUM_REG register
+ *  MSPI flash input timing delay number control register
+ */
+#define SPI_MEM_S_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x188)
+/** SPI_MEM_S_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_DIN0_NUM    0x00000003U
+#define SPI_MEM_S_DIN0_NUM_M  (SPI_MEM_S_DIN0_NUM_V << SPI_MEM_S_DIN0_NUM_S)
+#define SPI_MEM_S_DIN0_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN0_NUM_S  0
+/** SPI_MEM_S_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_DIN1_NUM    0x00000003U
+#define SPI_MEM_S_DIN1_NUM_M  (SPI_MEM_S_DIN1_NUM_V << SPI_MEM_S_DIN1_NUM_S)
+#define SPI_MEM_S_DIN1_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN1_NUM_S  2
+/** SPI_MEM_S_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_DIN2_NUM    0x00000003U
+#define SPI_MEM_S_DIN2_NUM_M  (SPI_MEM_S_DIN2_NUM_V << SPI_MEM_S_DIN2_NUM_S)
+#define SPI_MEM_S_DIN2_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN2_NUM_S  4
+/** SPI_MEM_S_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_DIN3_NUM    0x00000003U
+#define SPI_MEM_S_DIN3_NUM_M  (SPI_MEM_S_DIN3_NUM_V << SPI_MEM_S_DIN3_NUM_S)
+#define SPI_MEM_S_DIN3_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN3_NUM_S  6
+/** SPI_MEM_S_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_DIN4_NUM    0x00000003U
+#define SPI_MEM_S_DIN4_NUM_M  (SPI_MEM_S_DIN4_NUM_V << SPI_MEM_S_DIN4_NUM_S)
+#define SPI_MEM_S_DIN4_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN4_NUM_S  8
+/** SPI_MEM_S_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_DIN5_NUM    0x00000003U
+#define SPI_MEM_S_DIN5_NUM_M  (SPI_MEM_S_DIN5_NUM_V << SPI_MEM_S_DIN5_NUM_S)
+#define SPI_MEM_S_DIN5_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN5_NUM_S  10
+/** SPI_MEM_S_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_DIN6_NUM    0x00000003U
+#define SPI_MEM_S_DIN6_NUM_M  (SPI_MEM_S_DIN6_NUM_V << SPI_MEM_S_DIN6_NUM_S)
+#define SPI_MEM_S_DIN6_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN6_NUM_S  12
+/** SPI_MEM_S_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_DIN7_NUM    0x00000003U
+#define SPI_MEM_S_DIN7_NUM_M  (SPI_MEM_S_DIN7_NUM_V << SPI_MEM_S_DIN7_NUM_S)
+#define SPI_MEM_S_DIN7_NUM_V  0x00000003U
+#define SPI_MEM_S_DIN7_NUM_S  14
+/** SPI_MEM_S_DINS_NUM : R/W; bitpos: [17:16]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_DINS_NUM    0x00000003U
+#define SPI_MEM_S_DINS_NUM_M  (SPI_MEM_S_DINS_NUM_V << SPI_MEM_S_DINS_NUM_S)
+#define SPI_MEM_S_DINS_NUM_V  0x00000003U
+#define SPI_MEM_S_DINS_NUM_S  16
+
+/** SPI_MEM_S_DOUT_MODE_REG register
+ *  MSPI flash output timing adjustment control register
+ */
+#define SPI_MEM_S_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18c)
+/** SPI_MEM_S_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_S_DOUT0_MODE_M  (SPI_MEM_S_DOUT0_MODE_V << SPI_MEM_S_DOUT0_MODE_S)
+#define SPI_MEM_S_DOUT0_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT0_MODE_S  0
+/** SPI_MEM_S_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_S_DOUT1_MODE_M  (SPI_MEM_S_DOUT1_MODE_V << SPI_MEM_S_DOUT1_MODE_S)
+#define SPI_MEM_S_DOUT1_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT1_MODE_S  1
+/** SPI_MEM_S_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_S_DOUT2_MODE_M  (SPI_MEM_S_DOUT2_MODE_V << SPI_MEM_S_DOUT2_MODE_S)
+#define SPI_MEM_S_DOUT2_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT2_MODE_S  2
+/** SPI_MEM_S_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_S_DOUT3_MODE_M  (SPI_MEM_S_DOUT3_MODE_V << SPI_MEM_S_DOUT3_MODE_S)
+#define SPI_MEM_S_DOUT3_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT3_MODE_S  3
+/** SPI_MEM_S_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the spi_clk
+ */
+#define SPI_MEM_S_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_S_DOUT4_MODE_M  (SPI_MEM_S_DOUT4_MODE_V << SPI_MEM_S_DOUT4_MODE_S)
+#define SPI_MEM_S_DOUT4_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT4_MODE_S  4
+/** SPI_MEM_S_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the spi_clk
+ */
+#define SPI_MEM_S_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_S_DOUT5_MODE_M  (SPI_MEM_S_DOUT5_MODE_V << SPI_MEM_S_DOUT5_MODE_S)
+#define SPI_MEM_S_DOUT5_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT5_MODE_S  5
+/** SPI_MEM_S_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the spi_clk
+ */
+#define SPI_MEM_S_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_S_DOUT6_MODE_M  (SPI_MEM_S_DOUT6_MODE_V << SPI_MEM_S_DOUT6_MODE_S)
+#define SPI_MEM_S_DOUT6_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT6_MODE_S  6
+/** SPI_MEM_S_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the spi_clk
+ */
+#define SPI_MEM_S_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_S_DOUT7_MODE_M  (SPI_MEM_S_DOUT7_MODE_V << SPI_MEM_S_DOUT7_MODE_S)
+#define SPI_MEM_S_DOUT7_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUT7_MODE_S  7
+/** SPI_MEM_S_DOUTS_MODE : R/W; bitpos: [8]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the spi_clk
+ */
+#define SPI_MEM_S_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_S_DOUTS_MODE_M  (SPI_MEM_S_DOUTS_MODE_V << SPI_MEM_S_DOUTS_MODE_S)
+#define SPI_MEM_S_DOUTS_MODE_V  0x00000001U
+#define SPI_MEM_S_DOUTS_MODE_S  8
+
+/** SPI_MEM_S_SMEM_TIMING_CALI_REG register
+ *  MSPI external RAM timing calibration register
+ */
+#define SPI_MEM_S_SMEM_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x190)
+/** SPI_MEM_S_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
+ *  For sram, the bit is used to enable timing adjust clock for all reading operations.
+ */
+#define SPI_MEM_S_SMEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_M  (SPI_MEM_S_SMEM_TIMING_CLK_ENA_V << SPI_MEM_S_SMEM_TIMING_CLK_ENA_S)
+#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_V  0x00000001U
+#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_S  0
+/** SPI_MEM_S_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+ *  For sram, the bit is used to enable timing auto-calibration for all reading
+ *  operations.
+ */
+#define SPI_MEM_S_SMEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_S_SMEM_TIMING_CALI_M  (SPI_MEM_S_SMEM_TIMING_CALI_V << SPI_MEM_S_SMEM_TIMING_CALI_S)
+#define SPI_MEM_S_SMEM_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_S_SMEM_TIMING_CALI_S  1
+/** SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+ *  For sram, add extra dummy spi clock cycle length for spi clock calibration.
+ */
+#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
+/** SPI_MEM_S_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
+ *  EXT_RAM.
+ */
+#define SPI_MEM_S_SMEM_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_M  (SPI_MEM_S_SMEM_DLL_TIMING_CALI_V << SPI_MEM_S_SMEM_DLL_TIMING_CALI_S)
+#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_V  0x00000001U
+#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_S  5
+
+/** SPI_MEM_S_SMEM_DIN_MODE_REG register
+ *  MSPI external RAM input timing delay mode control register
+ */
+#define SPI_MEM_S_SMEM_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x194)
+/** SPI_MEM_S_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN0_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN0_MODE_M  (SPI_MEM_S_SMEM_DIN0_MODE_V << SPI_MEM_S_SMEM_DIN0_MODE_S)
+#define SPI_MEM_S_SMEM_DIN0_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN0_MODE_S  0
+/** SPI_MEM_S_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN1_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN1_MODE_M  (SPI_MEM_S_SMEM_DIN1_MODE_V << SPI_MEM_S_SMEM_DIN1_MODE_S)
+#define SPI_MEM_S_SMEM_DIN1_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN1_MODE_S  3
+/** SPI_MEM_S_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN2_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN2_MODE_M  (SPI_MEM_S_SMEM_DIN2_MODE_V << SPI_MEM_S_SMEM_DIN2_MODE_S)
+#define SPI_MEM_S_SMEM_DIN2_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN2_MODE_S  6
+/** SPI_MEM_S_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN3_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN3_MODE_M  (SPI_MEM_S_SMEM_DIN3_MODE_V << SPI_MEM_S_SMEM_DIN3_MODE_S)
+#define SPI_MEM_S_SMEM_DIN3_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN3_MODE_S  9
+/** SPI_MEM_S_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN4_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN4_MODE_M  (SPI_MEM_S_SMEM_DIN4_MODE_V << SPI_MEM_S_SMEM_DIN4_MODE_S)
+#define SPI_MEM_S_SMEM_DIN4_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN4_MODE_S  12
+/** SPI_MEM_S_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN5_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN5_MODE_M  (SPI_MEM_S_SMEM_DIN5_MODE_V << SPI_MEM_S_SMEM_DIN5_MODE_S)
+#define SPI_MEM_S_SMEM_DIN5_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN5_MODE_S  15
+/** SPI_MEM_S_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN6_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN6_MODE_M  (SPI_MEM_S_SMEM_DIN6_MODE_V << SPI_MEM_S_SMEM_DIN6_MODE_S)
+#define SPI_MEM_S_SMEM_DIN6_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN6_MODE_S  18
+/** SPI_MEM_S_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN7_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN7_MODE_M  (SPI_MEM_S_SMEM_DIN7_MODE_V << SPI_MEM_S_SMEM_DIN7_MODE_S)
+#define SPI_MEM_S_SMEM_DIN7_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN7_MODE_S  21
+/** SPI_MEM_S_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DINS_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DINS_MODE_M  (SPI_MEM_S_SMEM_DINS_MODE_V << SPI_MEM_S_SMEM_DINS_MODE_S)
+#define SPI_MEM_S_SMEM_DINS_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DINS_MODE_S  24
+
+/** SPI_MEM_S_SMEM_DIN_NUM_REG register
+ *  MSPI external RAM input timing delay number control register
+ */
+#define SPI_MEM_S_SMEM_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x198)
+/** SPI_MEM_S_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN0_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN0_NUM_M  (SPI_MEM_S_SMEM_DIN0_NUM_V << SPI_MEM_S_SMEM_DIN0_NUM_S)
+#define SPI_MEM_S_SMEM_DIN0_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN0_NUM_S  0
+/** SPI_MEM_S_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN1_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN1_NUM_M  (SPI_MEM_S_SMEM_DIN1_NUM_V << SPI_MEM_S_SMEM_DIN1_NUM_S)
+#define SPI_MEM_S_SMEM_DIN1_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN1_NUM_S  2
+/** SPI_MEM_S_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN2_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN2_NUM_M  (SPI_MEM_S_SMEM_DIN2_NUM_V << SPI_MEM_S_SMEM_DIN2_NUM_S)
+#define SPI_MEM_S_SMEM_DIN2_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN2_NUM_S  4
+/** SPI_MEM_S_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN3_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN3_NUM_M  (SPI_MEM_S_SMEM_DIN3_NUM_V << SPI_MEM_S_SMEM_DIN3_NUM_S)
+#define SPI_MEM_S_SMEM_DIN3_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN3_NUM_S  6
+/** SPI_MEM_S_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN4_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN4_NUM_M  (SPI_MEM_S_SMEM_DIN4_NUM_V << SPI_MEM_S_SMEM_DIN4_NUM_S)
+#define SPI_MEM_S_SMEM_DIN4_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN4_NUM_S  8
+/** SPI_MEM_S_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN5_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN5_NUM_M  (SPI_MEM_S_SMEM_DIN5_NUM_V << SPI_MEM_S_SMEM_DIN5_NUM_S)
+#define SPI_MEM_S_SMEM_DIN5_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN5_NUM_S  10
+/** SPI_MEM_S_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN6_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN6_NUM_M  (SPI_MEM_S_SMEM_DIN6_NUM_V << SPI_MEM_S_SMEM_DIN6_NUM_S)
+#define SPI_MEM_S_SMEM_DIN6_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN6_NUM_S  12
+/** SPI_MEM_S_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN7_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN7_NUM_M  (SPI_MEM_S_SMEM_DIN7_NUM_V << SPI_MEM_S_SMEM_DIN7_NUM_S)
+#define SPI_MEM_S_SMEM_DIN7_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN7_NUM_S  14
+/** SPI_MEM_S_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DINS_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DINS_NUM_M  (SPI_MEM_S_SMEM_DINS_NUM_V << SPI_MEM_S_SMEM_DINS_NUM_S)
+#define SPI_MEM_S_SMEM_DINS_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DINS_NUM_S  16
+
+/** SPI_MEM_S_SMEM_DOUT_MODE_REG register
+ *  MSPI external RAM output timing adjustment control register
+ */
+#define SPI_MEM_S_SMEM_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x19c)
+/** SPI_MEM_S_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_S_SMEM_DOUT0_MODE_M  (SPI_MEM_S_SMEM_DOUT0_MODE_V << SPI_MEM_S_SMEM_DOUT0_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT0_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT0_MODE_S  0
+/** SPI_MEM_S_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_S_SMEM_DOUT1_MODE_M  (SPI_MEM_S_SMEM_DOUT1_MODE_V << SPI_MEM_S_SMEM_DOUT1_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT1_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT1_MODE_S  1
+/** SPI_MEM_S_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_S_SMEM_DOUT2_MODE_M  (SPI_MEM_S_SMEM_DOUT2_MODE_V << SPI_MEM_S_SMEM_DOUT2_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT2_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT2_MODE_S  2
+/** SPI_MEM_S_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_S_SMEM_DOUT3_MODE_M  (SPI_MEM_S_SMEM_DOUT3_MODE_V << SPI_MEM_S_SMEM_DOUT3_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT3_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT3_MODE_S  3
+/** SPI_MEM_S_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_S_SMEM_DOUT4_MODE_M  (SPI_MEM_S_SMEM_DOUT4_MODE_V << SPI_MEM_S_SMEM_DOUT4_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT4_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT4_MODE_S  4
+/** SPI_MEM_S_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_S_SMEM_DOUT5_MODE_M  (SPI_MEM_S_SMEM_DOUT5_MODE_V << SPI_MEM_S_SMEM_DOUT5_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT5_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT5_MODE_S  5
+/** SPI_MEM_S_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_S_SMEM_DOUT6_MODE_M  (SPI_MEM_S_SMEM_DOUT6_MODE_V << SPI_MEM_S_SMEM_DOUT6_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT6_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT6_MODE_S  6
+/** SPI_MEM_S_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_S_SMEM_DOUT7_MODE_M  (SPI_MEM_S_SMEM_DOUT7_MODE_V << SPI_MEM_S_SMEM_DOUT7_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT7_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT7_MODE_S  7
+/** SPI_MEM_S_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_S_SMEM_DOUTS_MODE_M  (SPI_MEM_S_SMEM_DOUTS_MODE_V << SPI_MEM_S_SMEM_DOUTS_MODE_S)
+#define SPI_MEM_S_SMEM_DOUTS_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUTS_MODE_S  8
+
+/** SPI_MEM_S_SMEM_AC_REG register
+ *  MSPI external RAM ECC and SPI CS timing control register
+ */
+#define SPI_MEM_S_SMEM_AC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a0)
+/** SPI_MEM_S_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0;
+ *  For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0:
+ *  disable.
+ */
+#define SPI_MEM_S_SMEM_CS_SETUP    (BIT(0))
+#define SPI_MEM_S_SMEM_CS_SETUP_M  (SPI_MEM_S_SMEM_CS_SETUP_V << SPI_MEM_S_SMEM_CS_SETUP_S)
+#define SPI_MEM_S_SMEM_CS_SETUP_V  0x00000001U
+#define SPI_MEM_S_SMEM_CS_SETUP_S  0
+/** SPI_MEM_S_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0;
+ *  For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable.
+ */
+#define SPI_MEM_S_SMEM_CS_HOLD    (BIT(1))
+#define SPI_MEM_S_SMEM_CS_HOLD_M  (SPI_MEM_S_SMEM_CS_HOLD_V << SPI_MEM_S_SMEM_CS_HOLD_S)
+#define SPI_MEM_S_SMEM_CS_HOLD_V  0x00000001U
+#define SPI_MEM_S_SMEM_CS_HOLD_S  1
+/** SPI_MEM_S_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1;
+ *  For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with
+ *  spi_mem_cs_setup bit.
+ */
+#define SPI_MEM_S_SMEM_CS_SETUP_TIME    0x0000001FU
+#define SPI_MEM_S_SMEM_CS_SETUP_TIME_M  (SPI_MEM_S_SMEM_CS_SETUP_TIME_V << SPI_MEM_S_SMEM_CS_SETUP_TIME_S)
+#define SPI_MEM_S_SMEM_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_MEM_S_SMEM_CS_SETUP_TIME_S  2
+/** SPI_MEM_S_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1;
+ *  For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are
+ *  combined with spi_mem_cs_hold bit.
+ */
+#define SPI_MEM_S_SMEM_CS_HOLD_TIME    0x0000001FU
+#define SPI_MEM_S_SMEM_CS_HOLD_TIME_M  (SPI_MEM_S_SMEM_CS_HOLD_TIME_V << SPI_MEM_S_SMEM_CS_HOLD_TIME_S)
+#define SPI_MEM_S_SMEM_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_MEM_S_SMEM_CS_HOLD_TIME_S  7
+/** SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3;
+ *  SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
+ *  cycles in ECC mode when accessed external RAM.
+ */
+#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME    0x00000007U
+#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_M  (SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_S)
+#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_V  0x00000007U
+#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_S  12
+/** SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1;
+ *  1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when
+ *  accesses external RAM.
+ */
+#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
+#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_S)
+#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_V  0x00000001U
+#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_S  15
+/** SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+ *  accesses external RAM.
+ */
+#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
+#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_M  (SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_S)
+#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_S  16
+/** SPI_MEM_S_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0;
+ *  These bits are used to set the minimum CS high time tSHSL between SPI burst
+ *  transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1)
+ *  MSPI core clock cycles.
+ */
+#define SPI_MEM_S_SMEM_CS_HOLD_DELAY    0x0000003FU
+#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_M  (SPI_MEM_S_SMEM_CS_HOLD_DELAY_V << SPI_MEM_S_SMEM_CS_HOLD_DELAY_S)
+#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_V  0x0000003FU
+#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_S  25
+/** SPI_MEM_S_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 1;
+ *  Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
+ *  transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter
+ *  whether there is an ECC region or not.
+ */
+#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN    (BIT(31))
+#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_M  (SPI_MEM_S_SMEM_SPLIT_TRANS_EN_V << SPI_MEM_S_SMEM_SPLIT_TRANS_EN_S)
+#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_V  0x00000001U
+#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_S  31
+
+/** SPI_MEM_S_SMEM_DIN_HEX_MODE_REG register
+ *  MSPI 16x external RAM input timing delay mode control register
+ */
+#define SPI_MEM_S_SMEM_DIN_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a4)
+/** SPI_MEM_S_SMEM_DIN08_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN08_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN08_MODE_M  (SPI_MEM_S_SMEM_DIN08_MODE_V << SPI_MEM_S_SMEM_DIN08_MODE_S)
+#define SPI_MEM_S_SMEM_DIN08_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN08_MODE_S  0
+/** SPI_MEM_S_SMEM_DIN09_MODE : R/W; bitpos: [5:3]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN09_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN09_MODE_M  (SPI_MEM_S_SMEM_DIN09_MODE_V << SPI_MEM_S_SMEM_DIN09_MODE_S)
+#define SPI_MEM_S_SMEM_DIN09_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN09_MODE_S  3
+/** SPI_MEM_S_SMEM_DIN10_MODE : R/W; bitpos: [8:6]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN10_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN10_MODE_M  (SPI_MEM_S_SMEM_DIN10_MODE_V << SPI_MEM_S_SMEM_DIN10_MODE_S)
+#define SPI_MEM_S_SMEM_DIN10_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN10_MODE_S  6
+/** SPI_MEM_S_SMEM_DIN11_MODE : R/W; bitpos: [11:9]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN11_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN11_MODE_M  (SPI_MEM_S_SMEM_DIN11_MODE_V << SPI_MEM_S_SMEM_DIN11_MODE_S)
+#define SPI_MEM_S_SMEM_DIN11_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN11_MODE_S  9
+/** SPI_MEM_S_SMEM_DIN12_MODE : R/W; bitpos: [14:12]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN12_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN12_MODE_M  (SPI_MEM_S_SMEM_DIN12_MODE_V << SPI_MEM_S_SMEM_DIN12_MODE_S)
+#define SPI_MEM_S_SMEM_DIN12_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN12_MODE_S  12
+/** SPI_MEM_S_SMEM_DIN13_MODE : R/W; bitpos: [17:15]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN13_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN13_MODE_M  (SPI_MEM_S_SMEM_DIN13_MODE_V << SPI_MEM_S_SMEM_DIN13_MODE_S)
+#define SPI_MEM_S_SMEM_DIN13_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN13_MODE_S  15
+/** SPI_MEM_S_SMEM_DIN14_MODE : R/W; bitpos: [20:18]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN14_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN14_MODE_M  (SPI_MEM_S_SMEM_DIN14_MODE_V << SPI_MEM_S_SMEM_DIN14_MODE_S)
+#define SPI_MEM_S_SMEM_DIN14_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN14_MODE_S  18
+/** SPI_MEM_S_SMEM_DIN15_MODE : R/W; bitpos: [23:21]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DIN15_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DIN15_MODE_M  (SPI_MEM_S_SMEM_DIN15_MODE_V << SPI_MEM_S_SMEM_DIN15_MODE_S)
+#define SPI_MEM_S_SMEM_DIN15_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DIN15_MODE_S  21
+/** SPI_MEM_S_SMEM_DINS_HEX_MODE : R/W; bitpos: [26:24]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+ *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+ *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+ *  spi_clk high edge,  6: input with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DINS_HEX_MODE    0x00000007U
+#define SPI_MEM_S_SMEM_DINS_HEX_MODE_M  (SPI_MEM_S_SMEM_DINS_HEX_MODE_V << SPI_MEM_S_SMEM_DINS_HEX_MODE_S)
+#define SPI_MEM_S_SMEM_DINS_HEX_MODE_V  0x00000007U
+#define SPI_MEM_S_SMEM_DINS_HEX_MODE_S  24
+
+/** SPI_MEM_S_SMEM_DIN_HEX_NUM_REG register
+ *  MSPI 16x external RAM input timing delay number control register
+ */
+#define SPI_MEM_S_SMEM_DIN_HEX_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a8)
+/** SPI_MEM_S_SMEM_DIN08_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN08_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN08_NUM_M  (SPI_MEM_S_SMEM_DIN08_NUM_V << SPI_MEM_S_SMEM_DIN08_NUM_S)
+#define SPI_MEM_S_SMEM_DIN08_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN08_NUM_S  0
+/** SPI_MEM_S_SMEM_DIN09_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN09_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN09_NUM_M  (SPI_MEM_S_SMEM_DIN09_NUM_V << SPI_MEM_S_SMEM_DIN09_NUM_S)
+#define SPI_MEM_S_SMEM_DIN09_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN09_NUM_S  2
+/** SPI_MEM_S_SMEM_DIN10_NUM : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN10_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN10_NUM_M  (SPI_MEM_S_SMEM_DIN10_NUM_V << SPI_MEM_S_SMEM_DIN10_NUM_S)
+#define SPI_MEM_S_SMEM_DIN10_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN10_NUM_S  4
+/** SPI_MEM_S_SMEM_DIN11_NUM : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN11_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN11_NUM_M  (SPI_MEM_S_SMEM_DIN11_NUM_V << SPI_MEM_S_SMEM_DIN11_NUM_S)
+#define SPI_MEM_S_SMEM_DIN11_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN11_NUM_S  6
+/** SPI_MEM_S_SMEM_DIN12_NUM : R/W; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN12_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN12_NUM_M  (SPI_MEM_S_SMEM_DIN12_NUM_V << SPI_MEM_S_SMEM_DIN12_NUM_S)
+#define SPI_MEM_S_SMEM_DIN12_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN12_NUM_S  8
+/** SPI_MEM_S_SMEM_DIN13_NUM : R/W; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN13_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN13_NUM_M  (SPI_MEM_S_SMEM_DIN13_NUM_V << SPI_MEM_S_SMEM_DIN13_NUM_S)
+#define SPI_MEM_S_SMEM_DIN13_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN13_NUM_S  10
+/** SPI_MEM_S_SMEM_DIN14_NUM : R/W; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN14_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN14_NUM_M  (SPI_MEM_S_SMEM_DIN14_NUM_V << SPI_MEM_S_SMEM_DIN14_NUM_S)
+#define SPI_MEM_S_SMEM_DIN14_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN14_NUM_S  12
+/** SPI_MEM_S_SMEM_DIN15_NUM : R/W; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DIN15_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DIN15_NUM_M  (SPI_MEM_S_SMEM_DIN15_NUM_V << SPI_MEM_S_SMEM_DIN15_NUM_S)
+#define SPI_MEM_S_SMEM_DIN15_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DIN15_NUM_S  14
+/** SPI_MEM_S_SMEM_DINS_HEX_NUM : R/W; bitpos: [17:16]; default: 0;
+ *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...
+ */
+#define SPI_MEM_S_SMEM_DINS_HEX_NUM    0x00000003U
+#define SPI_MEM_S_SMEM_DINS_HEX_NUM_M  (SPI_MEM_S_SMEM_DINS_HEX_NUM_V << SPI_MEM_S_SMEM_DINS_HEX_NUM_S)
+#define SPI_MEM_S_SMEM_DINS_HEX_NUM_V  0x00000003U
+#define SPI_MEM_S_SMEM_DINS_HEX_NUM_S  16
+
+/** SPI_MEM_S_SMEM_DOUT_HEX_MODE_REG register
+ *  MSPI 16x external RAM output timing adjustment control register
+ */
+#define SPI_MEM_S_SMEM_DOUT_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1ac)
+/** SPI_MEM_S_SMEM_DOUT08_MODE : R/W; bitpos: [0]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT08_MODE    (BIT(0))
+#define SPI_MEM_S_SMEM_DOUT08_MODE_M  (SPI_MEM_S_SMEM_DOUT08_MODE_V << SPI_MEM_S_SMEM_DOUT08_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT08_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT08_MODE_S  0
+/** SPI_MEM_S_SMEM_DOUT09_MODE : R/W; bitpos: [1]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT09_MODE    (BIT(1))
+#define SPI_MEM_S_SMEM_DOUT09_MODE_M  (SPI_MEM_S_SMEM_DOUT09_MODE_V << SPI_MEM_S_SMEM_DOUT09_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT09_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT09_MODE_S  1
+/** SPI_MEM_S_SMEM_DOUT10_MODE : R/W; bitpos: [2]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT10_MODE    (BIT(2))
+#define SPI_MEM_S_SMEM_DOUT10_MODE_M  (SPI_MEM_S_SMEM_DOUT10_MODE_V << SPI_MEM_S_SMEM_DOUT10_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT10_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT10_MODE_S  2
+/** SPI_MEM_S_SMEM_DOUT11_MODE : R/W; bitpos: [3]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT11_MODE    (BIT(3))
+#define SPI_MEM_S_SMEM_DOUT11_MODE_M  (SPI_MEM_S_SMEM_DOUT11_MODE_V << SPI_MEM_S_SMEM_DOUT11_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT11_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT11_MODE_S  3
+/** SPI_MEM_S_SMEM_DOUT12_MODE : R/W; bitpos: [4]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT12_MODE    (BIT(4))
+#define SPI_MEM_S_SMEM_DOUT12_MODE_M  (SPI_MEM_S_SMEM_DOUT12_MODE_V << SPI_MEM_S_SMEM_DOUT12_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT12_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT12_MODE_S  4
+/** SPI_MEM_S_SMEM_DOUT13_MODE : R/W; bitpos: [5]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT13_MODE    (BIT(5))
+#define SPI_MEM_S_SMEM_DOUT13_MODE_M  (SPI_MEM_S_SMEM_DOUT13_MODE_V << SPI_MEM_S_SMEM_DOUT13_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT13_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT13_MODE_S  5
+/** SPI_MEM_S_SMEM_DOUT14_MODE : R/W; bitpos: [6]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT14_MODE    (BIT(6))
+#define SPI_MEM_S_SMEM_DOUT14_MODE_M  (SPI_MEM_S_SMEM_DOUT14_MODE_V << SPI_MEM_S_SMEM_DOUT14_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT14_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT14_MODE_S  6
+/** SPI_MEM_S_SMEM_DOUT15_MODE : R/W; bitpos: [7]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUT15_MODE    (BIT(7))
+#define SPI_MEM_S_SMEM_DOUT15_MODE_M  (SPI_MEM_S_SMEM_DOUT15_MODE_V << SPI_MEM_S_SMEM_DOUT15_MODE_S)
+#define SPI_MEM_S_SMEM_DOUT15_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUT15_MODE_S  7
+/** SPI_MEM_S_SMEM_DOUTS_HEX_MODE : R/W; bitpos: [8]; default: 0;
+ *  the output signals are delayed by system clock cycles, 0: output without delayed,
+ *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+ *  with the spi_clk high edge ,6: output with the spi_clk low edge
+ */
+#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE    (BIT(8))
+#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_M  (SPI_MEM_S_SMEM_DOUTS_HEX_MODE_V << SPI_MEM_S_SMEM_DOUTS_HEX_MODE_S)
+#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_V  0x00000001U
+#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_S  8
+
+/** SPI_MEM_S_CLOCK_GATE_REG register
+ *  SPI0 clock gate register
+ */
+#define SPI_MEM_S_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x200)
+/** SPI_MEM_S_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Register clock gate enable signal. 1: Enable. 0: Disable.
+ */
+#define SPI_MEM_S_CLK_EN    (BIT(0))
+#define SPI_MEM_S_CLK_EN_M  (SPI_MEM_S_CLK_EN_V << SPI_MEM_S_CLK_EN_S)
+#define SPI_MEM_S_CLK_EN_V  0x00000001U
+#define SPI_MEM_S_CLK_EN_S  0
+
+/** SPI_MEM_S_XTS_PLAIN_BASE_REG register
+ *  The base address of the memory that stores plaintext in Manual Encryption
+ */
+#define SPI_MEM_S_XTS_PLAIN_BASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x300)
+/** SPI_MEM_S_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0;
+ *  This field is only used to generate include file in c case. This field is useless.
+ *  Please do not use this field.
+ */
+#define SPI_MEM_S_XTS_PLAIN    0xFFFFFFFFU
+#define SPI_MEM_S_XTS_PLAIN_M  (SPI_MEM_S_XTS_PLAIN_V << SPI_MEM_S_XTS_PLAIN_S)
+#define SPI_MEM_S_XTS_PLAIN_V  0xFFFFFFFFU
+#define SPI_MEM_S_XTS_PLAIN_S  0
+
+/** SPI_MEM_S_XTS_LINESIZE_REG register
+ *  Manual Encryption Line-Size register
+ */
+#define SPI_MEM_S_XTS_LINESIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x340)
+/** SPI_MEM_S_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0;
+ *  This bits stores the line-size parameter which will be used in manual encryption
+ *  calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1:
+ *  32-bytes, 2: 64-bytes, 3:reserved.
+ */
+#define SPI_MEM_S_XTS_LINESIZE    0x00000003U
+#define SPI_MEM_S_XTS_LINESIZE_M  (SPI_MEM_S_XTS_LINESIZE_V << SPI_MEM_S_XTS_LINESIZE_S)
+#define SPI_MEM_S_XTS_LINESIZE_V  0x00000003U
+#define SPI_MEM_S_XTS_LINESIZE_S  0
+
+/** SPI_MEM_S_XTS_DESTINATION_REG register
+ *  Manual Encryption destination register
+ */
+#define SPI_MEM_S_XTS_DESTINATION_REG (DR_REG_PSRAM_MSPI0_BASE + 0x344)
+/** SPI_MEM_S_XTS_DESTINATION : R/W; bitpos: [0]; default: 0;
+ *  This bit stores the destination parameter which will be used in manual encryption
+ *  calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.
+ */
+#define SPI_MEM_S_XTS_DESTINATION    (BIT(0))
+#define SPI_MEM_S_XTS_DESTINATION_M  (SPI_MEM_S_XTS_DESTINATION_V << SPI_MEM_S_XTS_DESTINATION_S)
+#define SPI_MEM_S_XTS_DESTINATION_V  0x00000001U
+#define SPI_MEM_S_XTS_DESTINATION_S  0
+
+/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS_REG register
+ *  Manual Encryption physical address register
+ */
+#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x348)
+/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0;
+ *  This bits stores the physical-address parameter which will be used in manual
+ *  encryption calculation. This value should aligned with byte number decided by
+ *  line-size parameter.
+ */
+#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS    0x03FFFFFFU
+#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_M  (SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V << SPI_MEM_S_XTS_PHYSICAL_ADDRESS_S)
+#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V  0x03FFFFFFU
+#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_S  0
+
+/** SPI_MEM_S_XTS_TRIGGER_REG register
+ *  Manual Encryption physical address register
+ */
+#define SPI_MEM_S_XTS_TRIGGER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34c)
+/** SPI_MEM_S_XTS_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Set this bit to trigger the process of manual encryption calculation. This action
+ *  should only be asserted when manual encryption status is 0. After this action,
+ *  manual encryption status becomes 1. After calculation is done, manual encryption
+ *  status becomes 2.
+ */
+#define SPI_MEM_S_XTS_TRIGGER    (BIT(0))
+#define SPI_MEM_S_XTS_TRIGGER_M  (SPI_MEM_S_XTS_TRIGGER_V << SPI_MEM_S_XTS_TRIGGER_S)
+#define SPI_MEM_S_XTS_TRIGGER_V  0x00000001U
+#define SPI_MEM_S_XTS_TRIGGER_S  0
+
+/** SPI_MEM_S_XTS_RELEASE_REG register
+ *  Manual Encryption physical address register
+ */
+#define SPI_MEM_S_XTS_RELEASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x350)
+/** SPI_MEM_S_XTS_RELEASE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to release encrypted result to mspi. This action should only be
+ *  asserted when manual encryption status is 2. After this action, manual encryption
+ *  status will become 3.
+ */
+#define SPI_MEM_S_XTS_RELEASE    (BIT(0))
+#define SPI_MEM_S_XTS_RELEASE_M  (SPI_MEM_S_XTS_RELEASE_V << SPI_MEM_S_XTS_RELEASE_S)
+#define SPI_MEM_S_XTS_RELEASE_V  0x00000001U
+#define SPI_MEM_S_XTS_RELEASE_S  0
+
+/** SPI_MEM_S_XTS_DESTROY_REG register
+ *  Manual Encryption physical address register
+ */
+#define SPI_MEM_S_XTS_DESTROY_REG (DR_REG_PSRAM_MSPI0_BASE + 0x354)
+/** SPI_MEM_S_XTS_DESTROY : WT; bitpos: [0]; default: 0;
+ *  Set this bit to destroy encrypted result. This action should be asserted only when
+ *  manual encryption status is 3. After this action, manual encryption status will
+ *  become 0.
+ */
+#define SPI_MEM_S_XTS_DESTROY    (BIT(0))
+#define SPI_MEM_S_XTS_DESTROY_M  (SPI_MEM_S_XTS_DESTROY_V << SPI_MEM_S_XTS_DESTROY_S)
+#define SPI_MEM_S_XTS_DESTROY_V  0x00000001U
+#define SPI_MEM_S_XTS_DESTROY_S  0
+
+/** SPI_MEM_S_XTS_STATE_REG register
+ *  Manual Encryption physical address register
+ */
+#define SPI_MEM_S_XTS_STATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x358)
+/** SPI_MEM_S_XTS_STATE : RO; bitpos: [1:0]; default: 0;
+ *  This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
+ *  calculation, 2: encryption calculation is done but the encrypted result is
+ *  invisible to mspi, 3: the encrypted result is visible to mspi.
+ */
+#define SPI_MEM_S_XTS_STATE    0x00000003U
+#define SPI_MEM_S_XTS_STATE_M  (SPI_MEM_S_XTS_STATE_V << SPI_MEM_S_XTS_STATE_S)
+#define SPI_MEM_S_XTS_STATE_V  0x00000003U
+#define SPI_MEM_S_XTS_STATE_S  0
+
+/** SPI_MEM_S_XTS_DATE_REG register
+ *  Manual Encryption version register
+ */
+#define SPI_MEM_S_XTS_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x35c)
+/** SPI_MEM_S_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176;
+ *  This bits stores the last modified-time of manual encryption feature.
+ */
+#define SPI_MEM_S_XTS_DATE    0x3FFFFFFFU
+#define SPI_MEM_S_XTS_DATE_M  (SPI_MEM_S_XTS_DATE_V << SPI_MEM_S_XTS_DATE_S)
+#define SPI_MEM_S_XTS_DATE_V  0x3FFFFFFFU
+#define SPI_MEM_S_XTS_DATE_S  0
+
+/** SPI_MEM_S_MMU_ITEM_CONTENT_REG register
+ *  MSPI-MMU item content register
+ */
+#define SPI_MEM_S_MMU_ITEM_CONTENT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x37c)
+/** SPI_MEM_S_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892;
+ *  MSPI-MMU item content
+ */
+#define SPI_MEM_S_MMU_ITEM_CONTENT    0xFFFFFFFFU
+#define SPI_MEM_S_MMU_ITEM_CONTENT_M  (SPI_MEM_S_MMU_ITEM_CONTENT_V << SPI_MEM_S_MMU_ITEM_CONTENT_S)
+#define SPI_MEM_S_MMU_ITEM_CONTENT_V  0xFFFFFFFFU
+#define SPI_MEM_S_MMU_ITEM_CONTENT_S  0
+
+/** SPI_MEM_S_MMU_ITEM_INDEX_REG register
+ *  MSPI-MMU item index register
+ */
+#define SPI_MEM_S_MMU_ITEM_INDEX_REG (DR_REG_PSRAM_MSPI0_BASE + 0x380)
+/** SPI_MEM_S_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0;
+ *  MSPI-MMU item index
+ */
+#define SPI_MEM_S_MMU_ITEM_INDEX    0xFFFFFFFFU
+#define SPI_MEM_S_MMU_ITEM_INDEX_M  (SPI_MEM_S_MMU_ITEM_INDEX_V << SPI_MEM_S_MMU_ITEM_INDEX_S)
+#define SPI_MEM_S_MMU_ITEM_INDEX_V  0xFFFFFFFFU
+#define SPI_MEM_S_MMU_ITEM_INDEX_S  0
+
+/** SPI_MEM_S_MMU_POWER_CTRL_REG register
+ *  MSPI MMU power control register
+ */
+#define SPI_MEM_S_MMU_POWER_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x384)
+/** SPI_MEM_S_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable mmu-memory clock force on
+ */
+#define SPI_MEM_S_MMU_MEM_FORCE_ON    (BIT(0))
+#define SPI_MEM_S_MMU_MEM_FORCE_ON_M  (SPI_MEM_S_MMU_MEM_FORCE_ON_V << SPI_MEM_S_MMU_MEM_FORCE_ON_S)
+#define SPI_MEM_S_MMU_MEM_FORCE_ON_V  0x00000001U
+#define SPI_MEM_S_MMU_MEM_FORCE_ON_S  0
+/** SPI_MEM_S_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to force mmu-memory powerdown
+ */
+#define SPI_MEM_S_MMU_MEM_FORCE_PD    (BIT(1))
+#define SPI_MEM_S_MMU_MEM_FORCE_PD_M  (SPI_MEM_S_MMU_MEM_FORCE_PD_V << SPI_MEM_S_MMU_MEM_FORCE_PD_S)
+#define SPI_MEM_S_MMU_MEM_FORCE_PD_V  0x00000001U
+#define SPI_MEM_S_MMU_MEM_FORCE_PD_S  1
+/** SPI_MEM_S_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to force mmu-memory powerup, in this case, the power should also be
+ *  controlled by rtc.
+ */
+#define SPI_MEM_S_MMU_MEM_FORCE_PU    (BIT(2))
+#define SPI_MEM_S_MMU_MEM_FORCE_PU_M  (SPI_MEM_S_MMU_MEM_FORCE_PU_V << SPI_MEM_S_MMU_MEM_FORCE_PU_S)
+#define SPI_MEM_S_MMU_MEM_FORCE_PU_V  0x00000001U
+#define SPI_MEM_S_MMU_MEM_FORCE_PU_S  2
+/** SPI_MEM_S_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896;
+ *  MMU PSRAM aux control register
+ */
+#define SPI_MEM_S_AUX_CTRL    0x00003FFFU
+#define SPI_MEM_S_AUX_CTRL_M  (SPI_MEM_S_AUX_CTRL_V << SPI_MEM_S_AUX_CTRL_S)
+#define SPI_MEM_S_AUX_CTRL_V  0x00003FFFU
+#define SPI_MEM_S_AUX_CTRL_S  16
+/** SPI_MEM_S_RDN_ENA : R/W; bitpos: [30]; default: 0;
+ *  ECO register enable bit
+ */
+#define SPI_MEM_S_RDN_ENA    (BIT(30))
+#define SPI_MEM_S_RDN_ENA_M  (SPI_MEM_S_RDN_ENA_V << SPI_MEM_S_RDN_ENA_S)
+#define SPI_MEM_S_RDN_ENA_V  0x00000001U
+#define SPI_MEM_S_RDN_ENA_S  30
+/** SPI_MEM_S_RDN_RESULT : RO; bitpos: [31]; default: 0;
+ *  MSPI module clock domain and AXI clock domain ECO register result register
+ */
+#define SPI_MEM_S_RDN_RESULT    (BIT(31))
+#define SPI_MEM_S_RDN_RESULT_M  (SPI_MEM_S_RDN_RESULT_V << SPI_MEM_S_RDN_RESULT_S)
+#define SPI_MEM_S_RDN_RESULT_V  0x00000001U
+#define SPI_MEM_S_RDN_RESULT_S  31
+
+/** SPI_MEM_S_DPA_CTRL_REG register
+ *  SPI memory cryption DPA register
+ */
+#define SPI_MEM_S_DPA_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x388)
+/** SPI_MEM_S_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
+ *  Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7:
+ *  The bigger the number is, the more secure the cryption is. (Note that the
+ *  performance of cryption will decrease together with this number increasing)
+ */
+#define SPI_MEM_S_CRYPT_SECURITY_LEVEL    0x00000007U
+#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_M  (SPI_MEM_S_CRYPT_SECURITY_LEVEL_V << SPI_MEM_S_CRYPT_SECURITY_LEVEL_S)
+#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_V  0x00000007U
+#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_S  0
+/** SPI_MEM_S_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1;
+ *  Only available when SPI_MEM_S_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the
+ *  calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that
+ *  using key 1.
+ */
+#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN    (BIT(3))
+#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_M  (SPI_MEM_S_CRYPT_CALC_D_DPA_EN_V << SPI_MEM_S_CRYPT_CALC_D_DPA_EN_S)
+#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_V  0x00000001U
+#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_S  3
+/** SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0;
+ *  1: MSPI XTS DPA clock gate is controlled by SPI_MEM_S_CRYPT_CALC_D_DPA_EN and
+ *  SPI_MEM_S_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.
+ */
+#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
+#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_M  (SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_V << SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_S)
+#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_V  0x00000001U
+#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_S  4
+
+/** SPI_MEM_S_REGISTERRND_ECO_HIGH_REG register
+ *  MSPI ECO high register
+ */
+#define SPI_MEM_S_REGISTERRND_ECO_HIGH_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3f0)
+/** SPI_MEM_S_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892;
+ *  ECO high register
+ */
+#define SPI_MEM_S_REGISTERRND_ECO_HIGH    0xFFFFFFFFU
+#define SPI_MEM_S_REGISTERRND_ECO_HIGH_M  (SPI_MEM_S_REGISTERRND_ECO_HIGH_V << SPI_MEM_S_REGISTERRND_ECO_HIGH_S)
+#define SPI_MEM_S_REGISTERRND_ECO_HIGH_V  0xFFFFFFFFU
+#define SPI_MEM_S_REGISTERRND_ECO_HIGH_S  0
+
+/** SPI_MEM_S_REGISTERRND_ECO_LOW_REG register
+ *  MSPI ECO low register
+ */
+#define SPI_MEM_S_REGISTERRND_ECO_LOW_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3f4)
+/** SPI_MEM_S_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892;
+ *  ECO low register
+ */
+#define SPI_MEM_S_REGISTERRND_ECO_LOW    0xFFFFFFFFU
+#define SPI_MEM_S_REGISTERRND_ECO_LOW_M  (SPI_MEM_S_REGISTERRND_ECO_LOW_V << SPI_MEM_S_REGISTERRND_ECO_LOW_S)
+#define SPI_MEM_S_REGISTERRND_ECO_LOW_V  0xFFFFFFFFU
+#define SPI_MEM_S_REGISTERRND_ECO_LOW_S  0
+
+/** SPI_MEM_S_DATE_REG register
+ *  SPI0 version control register
+ */
+#define SPI_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3fc)
+/** SPI_MEM_S_DATE : R/W; bitpos: [27:0]; default: 36712704;
+ *  SPI0 register version.
+ */
+#define SPI_MEM_S_DATE    0x0FFFFFFFU
+#define SPI_MEM_S_DATE_M  (SPI_MEM_S_DATE_V << SPI_MEM_S_DATE_S)
+#define SPI_MEM_S_DATE_V  0x0FFFFFFFU
+#define SPI_MEM_S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h
new file mode 100644
index 0000000000..05386290ac
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h
@@ -0,0 +1,2605 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Status and state control register */
+/** Type of mem_cmd register
+ *  SPI0 FSM status register
+ */
+typedef union {
+    struct {
+        /** mem_mst_st : RO; bitpos: [3:0]; default: 0;
+         *  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT ,
+         *  2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent
+         *  data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
+         */
+        uint32_t mem_mst_st:4;
+        /** mem_slv_st : RO; bitpos: [7:4]; default: 0;
+         *  The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state,
+         *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
+         *  6:write data state, 7: done state, 8: read data end state.
+         */
+        uint32_t mem_slv_st:4;
+        uint32_t reserved_8:10;
+        /** mem_usr : HRO; bitpos: [18]; default: 0;
+         *  SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared.  An operation
+         *  will be triggered when the bit is set. The bit will be cleared once the operation
+         *  done.1: enable 0: disable.
+         */
+        uint32_t mem_usr:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} spi_mem_s_cmd_reg_t;
+
+/** Type of mem_axi_err_addr register
+ *  SPI0 AXI request error address.
+ */
+typedef union {
+    struct {
+        /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
+         *  This bits show the first AXI write/read invalid error or AXI write flash error
+         *  address. It is cleared by when SPI_MEM_S_AXI_WADDR_ERR_INT_CLR,
+         *  SPI_MEM_S_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_S_AXI_RADDR_ERR_IN_CLR bit is set.
+         */
+        uint32_t mem_axi_err_addr:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_s_axi_err_addr_reg_t;
+
+
+/** Group: Flash Control and configuration registers */
+/** Type of mem_ctrl register
+ *  SPI0 control register.
+ */
+typedef union {
+    struct {
+        /** mem_wdummy_dqs_always_out : R/W; bitpos: [0]; default: 0;
+         *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
+         *  of SPI_DQS is output by the MSPI controller.
+         */
+        uint32_t mem_wdummy_dqs_always_out:1;
+        /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0;
+         *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
+         *  of SPI_IO[7:0] is output by the MSPI controller.
+         */
+        uint32_t mem_wdummy_always_out:1;
+        /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1;
+         *  In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is
+         *  output by the MSPI controller in the first half part of dummy phase. It is used to
+         *  mask invalid SPI_DQS in the half part of dummy phase.
+         */
+        uint32_t mem_fdummy_rin:1;
+        /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1;
+         *  In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is
+         *  output by the MSPI controller in the second half part of dummy phase. It is used to
+         *  pre-drive flash.
+         */
+        uint32_t mem_fdummy_wout:1;
+        /** mem_fdout_oct : R/W; bitpos: [4]; default: 0;
+         *  Apply 8 signals during write-data phase 1:enable 0: disable
+         */
+        uint32_t mem_fdout_oct:1;
+        /** mem_fdin_oct : R/W; bitpos: [5]; default: 0;
+         *  Apply 8 signals during read-data phase 1:enable 0: disable
+         */
+        uint32_t mem_fdin_oct:1;
+        /** mem_faddr_oct : R/W; bitpos: [6]; default: 0;
+         *  Apply 8 signals during address phase 1:enable 0: disable
+         */
+        uint32_t mem_faddr_oct:1;
+        uint32_t reserved_7:1;
+        /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0;
+         *  Apply 4 signals during command phase 1:enable 0: disable
+         */
+        uint32_t mem_fcmd_quad:1;
+        /** mem_fcmd_oct : R/W; bitpos: [9]; default: 0;
+         *  Apply 8 signals during command phase 1:enable 0: disable
+         */
+        uint32_t mem_fcmd_oct:1;
+        uint32_t reserved_10:3;
+        /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1;
+         *  This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, SPI_MEM_S_FREAD_QOUT
+         *  and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable.
+         */
+        uint32_t mem_fastrd_mode:1;
+        /** mem_fread_dual : R/W; bitpos: [14]; default: 0;
+         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+         */
+        uint32_t mem_fread_dual:1;
+        uint32_t reserved_15:3;
+        /** mem_q_pol : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to set MISO line polarity, 1: high 0, low
+         */
+        uint32_t mem_q_pol:1;
+        /** mem_d_pol : R/W; bitpos: [19]; default: 1;
+         *  The bit is used to set MOSI line polarity, 1: high 0, low
+         */
+        uint32_t mem_d_pol:1;
+        /** mem_fread_quad : R/W; bitpos: [20]; default: 0;
+         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+         */
+        uint32_t mem_fread_quad:1;
+        /** mem_wp_reg : R/W; bitpos: [21]; default: 1;
+         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
+         */
+        uint32_t mem_wp_reg:1;
+        uint32_t reserved_22:1;
+        /** mem_fread_dio : R/W; bitpos: [23]; default: 0;
+         *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
+         *  0: disable.
+         */
+        uint32_t mem_fread_dio:1;
+        /** mem_fread_qio : R/W; bitpos: [24]; default: 0;
+         *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
+         *  0: disable.
+         */
+        uint32_t mem_fread_qio:1;
+        uint32_t reserved_25:5;
+        /** mem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0;
+         *  When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
+         *  1. 0: Others.
+         */
+        uint32_t mem_dqs_ie_always_on:1;
+        /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1;
+         *  When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are
+         *  always 1. 0: Others.
+         */
+        uint32_t mem_data_ie_always_on:1;
+    };
+    uint32_t val;
+} spi_mem_s_ctrl_reg_t;
+
+/** Type of mem_ctrl1 register
+ *  SPI0 control1 register.
+ */
+typedef union {
+    struct {
+        /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on.
+         */
+        uint32_t mem_clk_mode:2;
+        uint32_t reserved_2:19;
+        /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1;
+         *  1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply
+         *  the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.
+         */
+        uint32_t ar_size0_1_support_en:1;
+        /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1;
+         *  1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.
+         */
+        uint32_t aw_size0_1_support_en:1;
+        /** axi_rdata_back_fast : R/W; bitpos: [23]; default: 1;
+         *  1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0:
+         *  Reply AXI read data to AXI bus when all the read data is available.
+         */
+        uint32_t axi_rdata_back_fast:1;
+        /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0;
+         *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
+         *  when there is a ECC error in AXI read data. The ECC error information is recorded
+         *  in SPI_MEM_S_ECC_ERR_ADDR_REG.
+         */
+        uint32_t mem_rresp_ecc_err_en:1;
+        /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to enable AXI Read Splice-transfer.
+         */
+        uint32_t mem_ar_splice_en:1;
+        /** mem_aw_splice_en : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to enable AXI Write Splice-transfer.
+         */
+        uint32_t mem_aw_splice_en:1;
+        /** mem_ram0_en : HRO; bitpos: [27]; default: 1;
+         *  When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be
+         *  accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1
+         *  will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
+         *  accessed at the same time.
+         */
+        uint32_t mem_ram0_en:1;
+        /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0;
+         *  Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the
+         *  same time.
+         */
+        uint32_t mem_dual_ram_en:1;
+        /** mem_fast_write_en : R/W; bitpos: [29]; default: 1;
+         *  Set this bit to write data faster, do not wait write data has been stored in
+         *  tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
+         *  in  tx_bus_fifo_l2.
+         */
+        uint32_t mem_fast_write_en:1;
+        /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0;
+         *  The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
+         *  receive signals from AXI.  Set this bit to reset these FIFO.
+         */
+        uint32_t mem_rxfifo_rst:1;
+        /** mem_txfifo_rst : WT; bitpos: [31]; default: 0;
+         *  The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
+         *  send signals to AXI. Set this bit to reset these FIFO.
+         */
+        uint32_t mem_txfifo_rst:1;
+    };
+    uint32_t val;
+} spi_mem_s_ctrl1_reg_t;
+
+/** Type of mem_ctrl2 register
+ *  SPI0 control2 register.
+ */
+typedef union {
+    struct {
+        /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1;
+         *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
+         *  SPI_MEM_S_CS_SETUP bit.
+         */
+        uint32_t mem_cs_setup_time:5;
+        /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1;
+         *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
+         *  SPI_MEM_S_CS_HOLD bit.
+         */
+        uint32_t mem_cs_hold_time:5;
+        /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3;
+         *  SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+         *  mode when accessed flash.
+         */
+        uint32_t mem_ecc_cs_hold_time:3;
+        /** mem_ecc_skip_page_corner : R/W; bitpos: [13]; default: 1;
+         *  1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when
+         *  accesses flash.
+         */
+        uint32_t mem_ecc_skip_page_corner:1;
+        /** mem_ecc_16to18_byte_en : R/W; bitpos: [14]; default: 0;
+         *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+         *  accesses flash.
+         */
+        uint32_t mem_ecc_16to18_byte_en:1;
+        uint32_t reserved_15:9;
+        /** mem_split_trans_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable SPI0 split one AXI read flash transfer into two SPI
+         *  transfers when one transfer will cross flash or EXT_RAM page corner, valid no
+         *  matter whether there is an ECC region or not.
+         */
+        uint32_t mem_split_trans_en:1;
+        /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
+         *  These bits are used to set the minimum CS high time tSHSL between SPI burst
+         *  transfer when accesses to flash. tSHSL is (SPI_MEM_S_CS_HOLD_DELAY[5:0] + 1) MSPI
+         *  core clock cycles.
+         */
+        uint32_t mem_cs_hold_delay:6;
+        /** mem_sync_reset : WT; bitpos: [31]; default: 0;
+         *  The spi0_mst_st and spi0_slv_st will be reset.
+         */
+        uint32_t mem_sync_reset:1;
+    };
+    uint32_t val;
+} spi_mem_s_ctrl2_reg_t;
+
+/** Type of mem_misc register
+ *  SPI0 misc register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:7;
+        /** mem_fsub_pin : R/W; bitpos: [7]; default: 0;
+         *  For SPI0,  flash is connected to SUBPINs.
+         */
+        uint32_t mem_fsub_pin:1;
+        /** mem_ssub_pin : R/W; bitpos: [8]; default: 0;
+         *  For SPI0,  sram is connected to SUBPINs.
+         */
+        uint32_t mem_ssub_pin:1;
+        /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0;
+         *  1: SPI_CLK line is high when idle     0: spi clk line is low when idle
+         */
+        uint32_t mem_ck_idle_edge:1;
+        /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0;
+         *  SPI_CS line keep low when the bit is set.
+         */
+        uint32_t mem_cs_keep_active:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} spi_mem_s_misc_reg_t;
+
+/** Type of mem_cache_fctrl register
+ *  SPI0 bit mode control register.
+ */
+typedef union {
+    struct {
+        /** mem_axi_req_en : R/W; bitpos: [0]; default: 0;
+         *  For SPI0, AXI master access enable, 1: enable, 0:disable.
+         */
+        uint32_t mem_axi_req_en:1;
+        /** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0;
+         *  For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
+         */
+        uint32_t mem_cache_usr_addr_4byte:1;
+        /** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0;
+         *  For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.
+         */
+        uint32_t mem_cache_flash_usr_cmd:1;
+        /** mem_fdin_dual : R/W; bitpos: [3]; default: 0;
+         *  For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
+         *  same with spi_mem_s_fread_dio.
+         */
+        uint32_t mem_fdin_dual:1;
+        /** mem_fdout_dual : R/W; bitpos: [4]; default: 0;
+         *  For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
+         *  same with spi_mem_s_fread_dio.
+         */
+        uint32_t mem_fdout_dual:1;
+        /** mem_faddr_dual : R/W; bitpos: [5]; default: 0;
+         *  For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
+         *  the same with spi_mem_s_fread_dio.
+         */
+        uint32_t mem_faddr_dual:1;
+        /** mem_fdin_quad : R/W; bitpos: [6]; default: 0;
+         *  For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
+         *  same with spi_mem_s_fread_qio.
+         */
+        uint32_t mem_fdin_quad:1;
+        /** mem_fdout_quad : R/W; bitpos: [7]; default: 0;
+         *  For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the
+         *  same with spi_mem_s_fread_qio.
+         */
+        uint32_t mem_fdout_quad:1;
+        /** mem_faddr_quad : R/W; bitpos: [8]; default: 0;
+         *  For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
+         *  the same with spi_mem_s_fread_qio.
+         */
+        uint32_t mem_faddr_quad:1;
+        uint32_t reserved_9:21;
+        /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1;
+         *  Set this bit to check AXI read/write the same address region.
+         */
+        uint32_t same_aw_ar_addr_chk_en:1;
+        /** close_axi_inf_en : R/W; bitpos: [31]; default: 1;
+         *  Set this bit to close AXI read/write transfer to MSPI, which means that only
+         *  SLV_ERR will be replied to BRESP/RRESP.
+         */
+        uint32_t close_axi_inf_en:1;
+    };
+    uint32_t val;
+} spi_mem_s_cache_fctrl_reg_t;
+
+/** Type of mem_ddr register
+ *  SPI0 flash DDR mode control register
+ */
+typedef union {
+    struct {
+        /** fmem_ddr_en : R/W; bitpos: [0]; default: 0;
+         *  1: in DDR mode,  0 in SDR mode
+         */
+        uint32_t fmem_ddr_en:1;
+        /** fmem_var_dummy : R/W; bitpos: [1]; default: 0;
+         *  Set the bit to enable variable dummy cycle in spi DDR mode.
+         */
+        uint32_t fmem_var_dummy:1;
+        /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0;
+         *  Set the bit to reorder rx data of the word in spi DDR mode.
+         */
+        uint32_t fmem_ddr_rdat_swp:1;
+        /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0;
+         *  Set the bit to reorder tx data of the word in spi DDR mode.
+         */
+        uint32_t fmem_ddr_wdat_swp:1;
+        /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0;
+         *  the bit is used to disable dual edge in command phase when DDR mode.
+         */
+        uint32_t fmem_ddr_cmd_dis:1;
+        /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1;
+         *  It is the minimum output data length in the panda device.
+         */
+        uint32_t fmem_outminbytelen:7;
+        /** fmem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+         *  accesses to flash.
+         */
+        uint32_t fmem_tx_ddr_msk_en:1;
+        /** fmem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+         *  accesses to flash.
+         */
+        uint32_t fmem_rx_ddr_msk_en:1;
+        /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0;
+         *  The delay number of data strobe which from memory based on SPI clock.
+         */
+        uint32_t fmem_usr_ddr_dqs_thd:7;
+        /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
+         *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+         *  spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
+         *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+         *  negative edge of SPI_DQS.
+         */
+        uint32_t fmem_ddr_dqs_loop:1;
+        uint32_t reserved_22:2;
+        /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0;
+         *  Set this bit to enable the differential SPI_CLK#.
+         */
+        uint32_t fmem_clk_diff_en:1;
+        uint32_t reserved_25:1;
+        /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+         */
+        uint32_t fmem_dqs_ca_in:1;
+        /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+         *  accesses flash or SPI1 accesses flash or sram.
+         */
+        uint32_t fmem_hyperbus_dummy_2x:1;
+        /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to invert SPI_DIFF when accesses to flash. .
+         */
+        uint32_t fmem_clk_diff_inv:1;
+        /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0;
+         *  Set this bit to enable octa_ram address out when accesses to flash, which means
+         *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
+         */
+        uint32_t fmem_octa_ram_addr:1;
+        /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to enable HyperRAM address out when accesses to flash, which means
+         *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+         */
+        uint32_t fmem_hyperbus_ca:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} spi_mem_s_ddr_reg_t;
+
+
+/** Group: Clock control and configuration registers */
+/** Type of mem_clock register
+ *  SPI clock division control register.
+ */
+typedef union {
+    struct {
+        /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3;
+         *  In the master mode it must be equal to spi_mem_s_clkcnt_N.
+         */
+        uint32_t mem_clkcnt_l:8;
+        /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1;
+         *  In the master mode it must be floor((spi_mem_s_clkcnt_N+1)/2-1).
+         */
+        uint32_t mem_clkcnt_h:8;
+        /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3;
+         *  In the master mode it is the divider of spi_mem_s_clk. So spi_mem_s_clk frequency is
+         *  system/(spi_mem_s_clkcnt_N+1)
+         */
+        uint32_t mem_clkcnt_n:8;
+        uint32_t reserved_24:7;
+        /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0;
+         *  1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
+         *  clock.
+         */
+        uint32_t mem_clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi_mem_s_clock_reg_t;
+
+/** Type of mem_sram_clk register
+ *  SPI0 external RAM clock control register
+ */
+typedef union {
+    struct {
+        /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3;
+         *  For SPI0 external RAM  interface, it must be equal to spi_mem_s_clkcnt_N.
+         */
+        uint32_t mem_sclkcnt_l:8;
+        /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1;
+         *  For SPI0 external RAM  interface, it must be floor((spi_mem_s_clkcnt_N+1)/2-1).
+         */
+        uint32_t mem_sclkcnt_h:8;
+        /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3;
+         *  For SPI0 external RAM  interface, it is the divider of spi_mem_s_clk. So spi_mem_s_clk
+         *  frequency is system/(spi_mem_s_clkcnt_N+1)
+         */
+        uint32_t mem_sclkcnt_n:8;
+        uint32_t reserved_24:7;
+        /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0;
+         *  For SPI0 external RAM  interface, 1: spi_mem_s_clk is equal to system 0: spi_mem_s_clk
+         *  is divided from system clock.
+         */
+        uint32_t mem_sclk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi_mem_s_sram_clk_reg_t;
+
+/** Type of mem_clock_gate register
+ *  SPI0 clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Register clock gate enable signal. 1: Enable. 0: Disable.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi_mem_s_clock_gate_reg_t;
+
+
+/** Group: Flash User-defined control registers */
+/** Type of mem_user register
+ *  SPI0 user register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** mem_cs_hold : R/W; bitpos: [6]; default: 0;
+         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable.
+         */
+        uint32_t mem_cs_hold:1;
+        /** mem_cs_setup : R/W; bitpos: [7]; default: 0;
+         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.
+         */
+        uint32_t mem_cs_setup:1;
+        uint32_t reserved_8:1;
+        /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
+         */
+        uint32_t mem_ck_out_edge:1;
+        uint32_t reserved_10:16;
+        /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  spi clock is disable in dummy phase when the bit is enable.
+         */
+        uint32_t mem_usr_dummy_idle:1;
+        uint32_t reserved_27:2;
+        /** mem_usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  This bit enable the dummy phase of an operation.
+         */
+        uint32_t mem_usr_dummy:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_mem_s_user_reg_t;
+
+/** Type of mem_user1 register
+ *  SPI0 user1 register.
+ */
+typedef union {
+    struct {
+        /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
+         *  The length in spi_mem_s_clk cycles of dummy phase. The register value shall be
+         *  (cycle_num-1).
+         */
+        uint32_t mem_usr_dummy_cyclelen:6;
+        /** mem_usr_dbytelen : HRO; bitpos: [8:6]; default: 1;
+         *  SPI0 USR_CMD read or write data byte length -1
+         */
+        uint32_t mem_usr_dbytelen:3;
+        uint32_t reserved_9:17;
+        /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23;
+         *  The length in bits of address phase. The register value shall be (bit_num-1).
+         */
+        uint32_t mem_usr_addr_bitlen:6;
+    };
+    uint32_t val;
+} spi_mem_s_user1_reg_t;
+
+/** Type of mem_user2 register
+ *  SPI0 user2 register.
+ */
+typedef union {
+    struct {
+        /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  The value of  command.
+         */
+        uint32_t mem_usr_command_value:16;
+        uint32_t reserved_16:12;
+        /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  The length in bits of command phase. The register value shall be (bit_num-1)
+         */
+        uint32_t mem_usr_command_bitlen:4;
+    };
+    uint32_t val;
+} spi_mem_s_user2_reg_t;
+
+/** Type of mem_rd_status register
+ *  SPI0 read control register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0;
+         *  Mode bits in the flash fast read mode  it is combined with spi_mem_s_fastrd_mode bit.
+         */
+        uint32_t mem_wb_mode:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} spi_mem_s_rd_status_reg_t;
+
+
+/** Group: External RAM Control and configuration registers */
+/** Type of mem_cache_sctrl register
+ *  SPI0 external RAM control register
+ */
+typedef union {
+    struct {
+        /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0;
+         *  For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1:
+         *  enable, 0:disable.
+         */
+        uint32_t mem_cache_usr_saddr_4byte:1;
+        /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0;
+         *  For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable
+         */
+        uint32_t mem_usr_sram_dio:1;
+        /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0;
+         *  For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable
+         */
+        uint32_t mem_usr_sram_qio:1;
+        /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0;
+         *  For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write
+         *  operations.
+         */
+        uint32_t mem_usr_wr_sram_dummy:1;
+        /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1;
+         *  For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
+         *  operations.
+         */
+        uint32_t mem_usr_rd_sram_dummy:1;
+        /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1;
+         *  For SPI0, In the external RAM mode cache read external RAM for user define command.
+         */
+        uint32_t mem_cache_sram_usr_rcmd:1;
+        /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1;
+         *  For SPI0, In the external RAM mode, it is the length in bits of read dummy phase.
+         *  The register value shall be (bit_num-1).
+         */
+        uint32_t mem_sram_rdummy_cyclelen:6;
+        uint32_t reserved_12:2;
+        /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23;
+         *  For SPI0, In the external RAM mode, it is the length in bits of address phase. The
+         *  register value shall be (bit_num-1).
+         */
+        uint32_t mem_sram_addr_bitlen:6;
+        /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1;
+         *  For SPI0, In the external RAM mode cache write sram for user define command
+         */
+        uint32_t mem_cache_sram_usr_wcmd:1;
+        /** mem_sram_oct : R/W; bitpos: [21]; default: 0;
+         *  reserved
+         */
+        uint32_t mem_sram_oct:1;
+        /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1;
+         *  For SPI0, In the external RAM mode, it is the length in bits of write dummy phase.
+         *  The register value shall be (bit_num-1).
+         */
+        uint32_t mem_sram_wdummy_cyclelen:6;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi_mem_s_cache_sctrl_reg_t;
+
+/** Type of mem_sram_cmd register
+ *  SPI0 external RAM mode control register
+ */
+typedef union {
+    struct {
+        /** mem_sclk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on.
+         */
+        uint32_t mem_sclk_mode:2;
+        /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0;
+         *  Mode bits in the external RAM fast read mode  it is combined with
+         *  spi_mem_s_fastrd_mode bit.
+         */
+        uint32_t mem_swb_mode:8;
+        /** mem_sdin_dual : R/W; bitpos: [10]; default: 0;
+         *  For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is
+         *  the same with spi_mem_s_usr_sram_dio.
+         */
+        uint32_t mem_sdin_dual:1;
+        /** mem_sdout_dual : R/W; bitpos: [11]; default: 0;
+         *  For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit
+         *  is the same with spi_mem_s_usr_sram_dio.
+         */
+        uint32_t mem_sdout_dual:1;
+        /** mem_saddr_dual : R/W; bitpos: [12]; default: 0;
+         *  For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
+         *  bit is the same with spi_mem_s_usr_sram_dio.
+         */
+        uint32_t mem_saddr_dual:1;
+        uint32_t reserved_13:1;
+        /** mem_sdin_quad : R/W; bitpos: [14]; default: 0;
+         *  For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is
+         *  the same with spi_mem_s_usr_sram_qio.
+         */
+        uint32_t mem_sdin_quad:1;
+        /** mem_sdout_quad : R/W; bitpos: [15]; default: 0;
+         *  For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit
+         *  is the same with spi_mem_s_usr_sram_qio.
+         */
+        uint32_t mem_sdout_quad:1;
+        /** mem_saddr_quad : R/W; bitpos: [16]; default: 0;
+         *  For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
+         *  bit is the same with spi_mem_s_usr_sram_qio.
+         */
+        uint32_t mem_saddr_quad:1;
+        /** mem_scmd_quad : R/W; bitpos: [17]; default: 0;
+         *  For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is
+         *  the same with spi_mem_s_usr_sram_qio.
+         */
+        uint32_t mem_scmd_quad:1;
+        /** mem_sdin_oct : R/W; bitpos: [18]; default: 0;
+         *  For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable.
+         */
+        uint32_t mem_sdin_oct:1;
+        /** mem_sdout_oct : R/W; bitpos: [19]; default: 0;
+         *  For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable.
+         */
+        uint32_t mem_sdout_oct:1;
+        /** mem_saddr_oct : R/W; bitpos: [20]; default: 0;
+         *  For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable.
+         */
+        uint32_t mem_saddr_oct:1;
+        /** mem_scmd_oct : R/W; bitpos: [21]; default: 0;
+         *  For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable.
+         */
+        uint32_t mem_scmd_oct:1;
+        /** mem_sdummy_rin : R/W; bitpos: [22]; default: 1;
+         *  In the dummy phase of a MSPI read data transfer when accesses to external RAM, the
+         *  signal level of SPI bus is output by the MSPI controller.
+         */
+        uint32_t mem_sdummy_rin:1;
+        /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1;
+         *  In the dummy phase of a MSPI write data transfer when accesses to external RAM, the
+         *  signal level of SPI bus is output by the MSPI controller.
+         */
+        uint32_t mem_sdummy_wout:1;
+        /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0;
+         *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+         *  the level of SPI_DQS is output by the MSPI controller.
+         */
+        uint32_t smem_wdummy_dqs_always_out:1;
+        /** smem_wdummy_always_out : R/W; bitpos: [25]; default: 0;
+         *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+         *  the level of SPI_IO[7:0] is output by the MSPI controller.
+         */
+        uint32_t smem_wdummy_always_out:1;
+        /** mem_sdin_hex : R/W; bitpos: [26]; default: 0;
+         *  For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable.
+         */
+        uint32_t mem_sdin_hex:1;
+        /** mem_sdout_hex : R/W; bitpos: [27]; default: 0;
+         *  For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable.
+         */
+        uint32_t mem_sdout_hex:1;
+        uint32_t reserved_28:2;
+        /** smem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0;
+         *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are
+         *  always 1. 0: Others.
+         */
+        uint32_t smem_dqs_ie_always_on:1;
+        /** smem_data_ie_always_on : R/W; bitpos: [31]; default: 1;
+         *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0]
+         *  are always 1. 0: Others.
+         */
+        uint32_t smem_data_ie_always_on:1;
+    };
+    uint32_t val;
+} spi_mem_s_sram_cmd_reg_t;
+
+/** Type of mem_sram_drd_cmd register
+ *  SPI0 external RAM DDR read command control register
+ */
+typedef union {
+    struct {
+        /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0;
+         *  For SPI0,When cache mode is enable it is the read command value of command phase
+         *  for sram.
+         */
+        uint32_t mem_cache_sram_usr_rd_cmd_value:16;
+        uint32_t reserved_16:12;
+        /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0;
+         *  For SPI0,When cache mode is enable it is the length in bits of command phase for
+         *  sram. The register value shall be (bit_num-1).
+         */
+        uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4;
+    };
+    uint32_t val;
+} spi_mem_s_sram_drd_cmd_reg_t;
+
+/** Type of mem_sram_dwr_cmd register
+ *  SPI0 external RAM DDR write command control register
+ */
+typedef union {
+    struct {
+        /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0;
+         *  For SPI0,When cache mode is enable it is the write command value of command phase
+         *  for sram.
+         */
+        uint32_t mem_cache_sram_usr_wr_cmd_value:16;
+        uint32_t reserved_16:12;
+        /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0;
+         *  For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
+         *  The register value shall be (bit_num-1).
+         */
+        uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4;
+    };
+    uint32_t val;
+} spi_mem_s_sram_dwr_cmd_reg_t;
+
+/** Type of smem_ddr register
+ *  SPI0 external RAM DDR mode control register
+ */
+typedef union {
+    struct {
+        /** smem_ddr_en : R/W; bitpos: [0]; default: 0;
+         *  1: in DDR mode,  0 in SDR mode
+         */
+        uint32_t smem_ddr_en:1;
+        /** smem_var_dummy : R/W; bitpos: [1]; default: 0;
+         *  Set the bit to enable variable dummy cycle in spi DDR mode.
+         */
+        uint32_t smem_var_dummy:1;
+        /** smem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0;
+         *  Set the bit to reorder rx data of the word in spi DDR mode.
+         */
+        uint32_t smem_ddr_rdat_swp:1;
+        /** smem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0;
+         *  Set the bit to reorder tx data of the word in spi DDR mode.
+         */
+        uint32_t smem_ddr_wdat_swp:1;
+        /** smem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0;
+         *  the bit is used to disable dual edge in command phase when DDR mode.
+         */
+        uint32_t smem_ddr_cmd_dis:1;
+        /** smem_outminbytelen : R/W; bitpos: [11:5]; default: 1;
+         *  It is the minimum output data length in the DDR psram.
+         */
+        uint32_t smem_outminbytelen:7;
+        /** smem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+         *  accesses to external RAM.
+         */
+        uint32_t smem_tx_ddr_msk_en:1;
+        /** smem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+         *  accesses to external RAM.
+         */
+        uint32_t smem_rx_ddr_msk_en:1;
+        /** smem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0;
+         *  The delay number of data strobe which from memory based on SPI clock.
+         */
+        uint32_t smem_usr_ddr_dqs_thd:7;
+        /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
+         *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
+         *  spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
+         *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
+         *  negative edge of SPI_DQS.
+         */
+        uint32_t smem_ddr_dqs_loop:1;
+        uint32_t reserved_22:2;
+        /** smem_clk_diff_en : R/W; bitpos: [24]; default: 0;
+         *  Set this bit to enable the differential SPI_CLK#.
+         */
+        uint32_t smem_clk_diff_en:1;
+        uint32_t reserved_25:1;
+        /** smem_dqs_ca_in : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
+         */
+        uint32_t smem_dqs_ca_in:1;
+        /** smem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
+         *  accesses flash or SPI1 accesses flash or sram.
+         */
+        uint32_t smem_hyperbus_dummy_2x:1;
+        /** smem_clk_diff_inv : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to invert SPI_DIFF when accesses to external RAM. .
+         */
+        uint32_t smem_clk_diff_inv:1;
+        /** smem_octa_ram_addr : R/W; bitpos: [29]; default: 0;
+         *  Set this bit to enable octa_ram address out when accesses to external RAM, which
+         *  means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1],
+         *  1'b0}.
+         */
+        uint32_t smem_octa_ram_addr:1;
+        /** smem_hyperbus_ca : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to enable HyperRAM address out when accesses to external RAM, which
+         *  means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
+         */
+        uint32_t smem_hyperbus_ca:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} spi_mem_s_smem_ddr_reg_t;
+
+/** Type of smem_ac register
+ *  MSPI external RAM ECC and SPI CS timing control register
+ */
+typedef union {
+    struct {
+        /** smem_cs_setup : R/W; bitpos: [0]; default: 0;
+         *  For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0:
+         *  disable.
+         */
+        uint32_t smem_cs_setup:1;
+        /** smem_cs_hold : R/W; bitpos: [1]; default: 0;
+         *  For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable.
+         */
+        uint32_t smem_cs_hold:1;
+        /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1;
+         *  For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with
+         *  spi_mem_s_cs_setup bit.
+         */
+        uint32_t smem_cs_setup_time:5;
+        /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1;
+         *  For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are
+         *  combined with spi_mem_s_cs_hold bit.
+         */
+        uint32_t smem_cs_hold_time:5;
+        /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3;
+         *  SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
+         *  cycles in ECC mode when accessed external RAM.
+         */
+        uint32_t smem_ecc_cs_hold_time:3;
+        /** smem_ecc_skip_page_corner : R/W; bitpos: [15]; default: 1;
+         *  1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when
+         *  accesses external RAM.
+         */
+        uint32_t smem_ecc_skip_page_corner:1;
+        /** smem_ecc_16to18_byte_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+         *  accesses external RAM.
+         */
+        uint32_t smem_ecc_16to18_byte_en:1;
+        uint32_t reserved_17:8;
+        /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
+         *  These bits are used to set the minimum CS high time tSHSL between SPI burst
+         *  transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1)
+         *  MSPI core clock cycles.
+         */
+        uint32_t smem_cs_hold_delay:6;
+        /** smem_split_trans_en : R/W; bitpos: [31]; default: 1;
+         *  Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
+         *  transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter
+         *  whether there is an ECC region or not.
+         */
+        uint32_t smem_split_trans_en:1;
+    };
+    uint32_t val;
+} spi_mem_s_smem_ac_reg_t;
+
+
+/** Group: State control register */
+/** Type of mem_fsm register
+ *  SPI0 FSM status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:7;
+        /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4;
+         *  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
+         */
+        uint32_t mem_lock_delay_time:5;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} spi_mem_s_fsm_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of mem_int_ena register
+ *  SPI0 interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
+         */
+        uint32_t mem_slv_st_end_int_ena:1;
+        /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for SPI_MEM_S_MST_ST_END_INT interrupt.
+         */
+        uint32_t mem_mst_st_end_int_ena:1;
+        /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The enable bit for SPI_MEM_S_ECC_ERR_INT interrupt.
+         */
+        uint32_t mem_ecc_err_int_ena:1;
+        /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The enable bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
+         */
+        uint32_t mem_pms_reject_int_ena:1;
+        /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
+         */
+        uint32_t mem_axi_raddr_err_int_ena:1;
+        /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
+         */
+        uint32_t mem_axi_wr_flash_err_int_ena:1;
+        /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0;
+         *  The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
+         */
+        uint32_t mem_axi_waddr_err_int__ena:1;
+        uint32_t reserved_10:18;
+        /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0;
+         *  The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
+         */
+        uint32_t mem_dqs0_afifo_ovf_int_ena:1;
+        /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0;
+         *  The enable bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
+         */
+        uint32_t mem_dqs1_afifo_ovf_int_ena:1;
+        /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0;
+         *  The enable bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
+         */
+        uint32_t mem_bus_fifo1_udf_int_ena:1;
+        /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0;
+         *  The enable bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
+         */
+        uint32_t mem_bus_fifo0_udf_int_ena:1;
+    };
+    uint32_t val;
+} spi_mem_s_int_ena_reg_t;
+
+/** Type of mem_int_clr register
+ *  SPI0 interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
+         */
+        uint32_t mem_slv_st_end_int_clr:1;
+        /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear bit for SPI_MEM_S_MST_ST_END_INT interrupt.
+         */
+        uint32_t mem_mst_st_end_int_clr:1;
+        /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  The clear bit for SPI_MEM_S_ECC_ERR_INT interrupt.
+         */
+        uint32_t mem_ecc_err_int_clr:1;
+        /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0;
+         *  The clear bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
+         */
+        uint32_t mem_pms_reject_int_clr:1;
+        /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  The clear bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
+         */
+        uint32_t mem_axi_raddr_err_int_clr:1;
+        /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0;
+         *  The clear bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
+         */
+        uint32_t mem_axi_wr_flash_err_int_clr:1;
+        /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0;
+         *  The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
+         */
+        uint32_t mem_axi_waddr_err_int_clr:1;
+        uint32_t reserved_10:18;
+        /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0;
+         *  The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
+         */
+        uint32_t mem_dqs0_afifo_ovf_int_clr:1;
+        /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0;
+         *  The clear bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
+         */
+        uint32_t mem_dqs1_afifo_ovf_int_clr:1;
+        /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0;
+         *  The clear bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
+         */
+        uint32_t mem_bus_fifo1_udf_int_clr:1;
+        /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0;
+         *  The clear bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
+         */
+        uint32_t mem_bus_fifo0_udf_int_clr:1;
+    };
+    uint32_t val;
+} spi_mem_s_int_clr_reg_t;
+
+/** Type of mem_int_raw register
+ *  SPI0 interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
+         *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
+         *  Others
+         */
+        uint32_t mem_slv_st_end_int_raw:1;
+        /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
+         *  changed from non idle state to idle state. 0: Others.
+         */
+        uint32_t mem_mst_st_end_int_raw:1;
+        /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is set
+         *  and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
+         *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When
+         *  SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is
+         *  triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
+         *  than SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and
+         *  SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+         *  of SPI0/1 ECC read external RAM and flash are equal or bigger than
+         *  SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and  SPI_MEM_S_SMEM_ECC_ERR_INT_EN
+         *  are cleared, this bit will not be triggered.
+         */
+        uint32_t mem_ecc_err_int_raw:1;
+        /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
+         *  rejected. 0: Others.
+         */
+        uint32_t mem_pms_reject_int_raw:1;
+        /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+         *  address is invalid by compared to MMU configuration. 0: Others.
+         */
+        uint32_t mem_axi_raddr_err_int_raw:1;
+        /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
+         *  flash request is received. 0: Others.
+         */
+        uint32_t mem_axi_wr_flash_err_int_raw:1;
+        /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+         *  address is invalid by compared to MMU configuration. 0: Others.
+         */
+        uint32_t mem_axi_waddr_err_int_raw:1;
+        uint32_t reserved_10:18;
+        /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
+         *  connected to SPI_DQS1 is overflow.
+         */
+        uint32_t mem_dqs0_afifo_ovf_int_raw:1;
+        /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  The raw bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
+         *  connected to SPI_DQS is overflow.
+         */
+        uint32_t mem_dqs1_afifo_ovf_int_raw:1;
+        /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is
+         *  underflow.
+         */
+        uint32_t mem_bus_fifo1_udf_int_raw:1;
+        /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is
+         *  underflow.
+         */
+        uint32_t mem_bus_fifo0_udf_int_raw:1;
+    };
+    uint32_t val;
+} spi_mem_s_int_raw_reg_t;
+
+/** Type of mem_int_st register
+ *  SPI0 interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for SPI_MEM_S_SLV_ST_END_INT interrupt.
+         */
+        uint32_t mem_slv_st_end_int_st:1;
+        /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0;
+         *  The status bit for SPI_MEM_S_MST_ST_END_INT interrupt.
+         */
+        uint32_t mem_mst_st_end_int_st:1;
+        /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0;
+         *  The status bit for SPI_MEM_S_ECC_ERR_INT interrupt.
+         */
+        uint32_t mem_ecc_err_int_st:1;
+        /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0;
+         *  The status bit for SPI_MEM_S_PMS_REJECT_INT interrupt.
+         */
+        uint32_t mem_pms_reject_int_st:1;
+        /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt.
+         */
+        uint32_t mem_axi_raddr_err_int_st:1;
+        /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0;
+         *  The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt.
+         */
+        uint32_t mem_axi_wr_flash_err_int_st:1;
+        /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0;
+         *  The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
+         */
+        uint32_t mem_axi_waddr_err_int_st:1;
+        uint32_t reserved_10:18;
+        /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0;
+         *  The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
+         */
+        uint32_t mem_dqs0_afifo_ovf_int_st:1;
+        /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0;
+         *  The status bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt.
+         */
+        uint32_t mem_dqs1_afifo_ovf_int_st:1;
+        /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0;
+         *  The status bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt.
+         */
+        uint32_t mem_bus_fifo1_udf_int_st:1;
+        /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0;
+         *  The status bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt.
+         */
+        uint32_t mem_bus_fifo0_udf_int_st:1;
+    };
+    uint32_t val;
+} spi_mem_s_int_st_reg_t;
+
+
+/** Group: PMS control and configuration registers */
+/** Type of fmem_pmsn_attr register
+ *  MSPI flash PMS section $n attribute register
+ */
+typedef union {
+    struct {
+        /** fmem_pms_rd_attr : R/W; bitpos: [0]; default: 1;
+         *  1: SPI1 flash PMS section $n read accessible. 0: Not allowed.
+         */
+        uint32_t fmem_pms_rd_attr:1;
+        /** fmem_pms_wr_attr : R/W; bitpos: [1]; default: 1;
+         *  1: SPI1 flash PMS section $n write accessible. 0: Not allowed.
+         */
+        uint32_t fmem_pms_wr_attr:1;
+        /** fmem_pms_ecc : R/W; bitpos: [2]; default: 0;
+         *  SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+         *  PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and
+         *  SPI_MEM_S_FMEM_PMS$n_SIZE_REG.
+         */
+        uint32_t fmem_pms_ecc:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} spi_mem_s_fmem_pmsn_attr_reg_t;
+
+/** Type of fmem_pmsn_addr register
+ *  SPI1 flash PMS section $n start address register
+ */
+typedef union {
+    struct {
+        /** fmem_pms_addr_s : R/W; bitpos: [26:0]; default: 0;
+         *  SPI1 flash PMS section $n start address value
+         */
+        uint32_t fmem_pms_addr_s:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_s_fmem_pmsn_addr_reg_t;
+
+/** Type of fmem_pmsn_size register
+ *  SPI1 flash PMS section $n start address register
+ */
+typedef union {
+    struct {
+        /** fmem_pms_size : R/W; bitpos: [14:0]; default: 4096;
+         *  SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S,
+         *  SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE)
+         */
+        uint32_t fmem_pms_size:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} spi_mem_s_fmem_pmsn_size_reg_t;
+
+/** Type of smem_pmsn_attr register
+ *  SPI1 flash PMS section $n start address register
+ */
+typedef union {
+    struct {
+        /** smem_pms_rd_attr : R/W; bitpos: [0]; default: 1;
+         *  1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.
+         */
+        uint32_t smem_pms_rd_attr:1;
+        /** smem_pms_wr_attr : R/W; bitpos: [1]; default: 1;
+         *  1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.
+         */
+        uint32_t smem_pms_wr_attr:1;
+        /** smem_pms_ecc : R/W; bitpos: [2]; default: 0;
+         *  SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The
+         *  external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and
+         *  SPI_MEM_S_SMEM_PMS$n_SIZE_REG.
+         */
+        uint32_t smem_pms_ecc:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} spi_mem_s_smem_pmsn_attr_reg_t;
+
+/** Type of smem_pmsn_addr register
+ *  SPI1 external RAM PMS section $n start address register
+ */
+typedef union {
+    struct {
+        /** smem_pms_addr_s : R/W; bitpos: [26:0]; default: 0;
+         *  SPI1 external RAM PMS section $n start address value
+         */
+        uint32_t smem_pms_addr_s:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_s_smem_pmsn_addr_reg_t;
+
+/** Type of smem_pmsn_size register
+ *  SPI1 external RAM PMS section $n start address register
+ */
+typedef union {
+    struct {
+        /** smem_pms_size : R/W; bitpos: [14:0]; default: 4096;
+         *  SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S,
+         *  SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE)
+         */
+        uint32_t smem_pms_size:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} spi_mem_s_smem_pmsn_size_reg_t;
+
+/** Type of mem_pms_reject register
+ *  SPI1 access reject register
+ */
+typedef union {
+    struct {
+        /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
+         *  This bits show the first SPI1 access error address. It is cleared by when
+         *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
+         */
+        uint32_t mem_reject_addr:27;
+        /** mem_pm_en : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to enable SPI0/1 transfer permission control function.
+         */
+        uint32_t mem_pm_en:1;
+        /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0;
+         *  1: SPI1 write access error. 0: No write access error. It is cleared by when
+         *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
+         */
+        uint32_t mem_pms_ld:1;
+        /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0;
+         *  1: SPI1 read access error. 0: No read access error. It is cleared by when
+         *  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
+         */
+        uint32_t mem_pms_st:1;
+        /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0;
+         *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
+         *  cleared by when  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
+         */
+        uint32_t mem_pms_multi_hit:1;
+        /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0;
+         *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
+         *  error. It is cleared by when  SPI_MEM_S_PMS_REJECT_INT_CLR bit is set.
+         */
+        uint32_t mem_pms_ivd:1;
+    };
+    uint32_t val;
+} spi_mem_s_pms_reject_reg_t;
+
+
+/** Group: MSPI ECC registers */
+/** Type of mem_ecc_ctrl register
+ *  MSPI ECC control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0;
+         *  This bits show the error times of MSPI ECC read. It is cleared by when
+         *  SPI_MEM_S_ECC_ERR_INT_CLR bit is set.
+         */
+        uint32_t mem_ecc_err_cnt:6;
+        /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10;
+         *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt.
+         */
+        uint32_t fmem_ecc_err_int_num:6;
+        /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to calculate the error times of MSPI ECC read when accesses to flash.
+         */
+        uint32_t fmem_ecc_err_int_en:1;
+        /** fmem_page_size : R/W; bitpos: [19:18]; default: 0;
+         *  Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
+         *  1024 bytes. 3: 2048 bytes.
+         */
+        uint32_t fmem_page_size:2;
+        /** fmem_ecc_addr_en : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
+         *  ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit
+         *  should be 0. Otherwise, this bit should be 1.
+         */
+        uint32_t fmem_ecc_addr_en:1;
+        /** mem_usr_ecc_addr_en : R/W; bitpos: [21]; default: 0;
+         *  Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.
+         */
+        uint32_t mem_usr_ecc_addr_en:1;
+        uint32_t reserved_22:2;
+        /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1;
+         *  1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is
+         *  updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and
+         *  SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information.
+         */
+        uint32_t mem_ecc_continue_record_err_en:1;
+        /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0;
+         *  Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to
+         *  byte 0 bit 0 to byte 15 bit 7)
+         */
+        uint32_t mem_ecc_err_bits:7;
+    };
+    uint32_t val;
+} spi_mem_s_ecc_ctrl_reg_t;
+
+/** Type of mem_ecc_err_addr register
+ *  MSPI ECC error address register
+ */
+typedef union {
+    struct {
+        /** mem_ecc_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
+         *  This bits show the first MSPI ECC error address. It is cleared by when
+         *  SPI_MEM_S_ECC_ERR_INT_CLR bit is set.
+         */
+        uint32_t mem_ecc_err_addr:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_s_ecc_err_addr_reg_t;
+
+/** Type of smem_ecc_ctrl register
+ *  MSPI ECC control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:17;
+        /** smem_ecc_err_int_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to calculate the error times of MSPI ECC read when accesses to
+         *  external RAM.
+         */
+        uint32_t smem_ecc_err_int_en:1;
+        /** smem_page_size : R/W; bitpos: [19:18]; default: 2;
+         *  Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes.
+         *  2: 1024 bytes. 3: 2048 bytes.
+         */
+        uint32_t smem_page_size:2;
+        /** smem_ecc_addr_en : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
+         *  ECC region or non-ECC region of external RAM. If there is no ECC region in external
+         *  RAM, this bit should be 0. Otherwise, this bit should be 1.
+         */
+        uint32_t smem_ecc_addr_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_mem_s_smem_ecc_ctrl_reg_t;
+
+
+/** Group: Status and state control registers */
+/** Type of smem_axi_addr_ctrl register
+ *  SPI0 AXI address control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1;
+         *  The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
+         *  and SPI0 transfers are done. 0: Others.
+         */
+        uint32_t mem_all_fifo_empty:1;
+        /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1;
+         *  1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.
+         */
+        uint32_t rdata_afifo_rempty:1;
+        /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1;
+         *  1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.
+         */
+        uint32_t raddr_afifo_rempty:1;
+        /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1;
+         *  1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.
+         */
+        uint32_t wdata_afifo_rempty:1;
+        /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1;
+         *  1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.
+         */
+        uint32_t wblen_afifo_rempty:1;
+        /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1;
+         *  This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and
+         *  RDATA_AFIFO are empty and spi0_mst_st is IDLE.
+         */
+        uint32_t all_axi_trans_afifo_empty:1;
+    };
+    uint32_t val;
+} spi_mem_s_smem_axi_addr_ctrl_reg_t;
+
+/** Type of mem_axi_err_resp_en register
+ *  SPI0 AXI error response enable register
+ */
+typedef union {
+    struct {
+        /** mem_aw_resp_en_mmu_vld : R/W; bitpos: [0]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu valid err in axi write trans.
+         */
+        uint32_t mem_aw_resp_en_mmu_vld:1;
+        /** mem_aw_resp_en_mmu_gid : R/W; bitpos: [1]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu gid err in axi write trans.
+         */
+        uint32_t mem_aw_resp_en_mmu_gid:1;
+        /** mem_aw_resp_en_axi_size : R/W; bitpos: [2]; default: 0;
+         *  Set this bit  to enable AXI response function for axi size err in axi write trans.
+         */
+        uint32_t mem_aw_resp_en_axi_size:1;
+        /** mem_aw_resp_en_axi_flash : R/W; bitpos: [3]; default: 0;
+         *  Set this bit  to enable AXI response function for axi flash err in axi write trans.
+         */
+        uint32_t mem_aw_resp_en_axi_flash:1;
+        /** mem_aw_resp_en_mmu_ecc : R/W; bitpos: [4]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu ecc err in axi write trans.
+         */
+        uint32_t mem_aw_resp_en_mmu_ecc:1;
+        /** mem_aw_resp_en_mmu_sens : R/W; bitpos: [5]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu sens in err axi write trans.
+         */
+        uint32_t mem_aw_resp_en_mmu_sens:1;
+        /** mem_aw_resp_en_axi_wstrb : R/W; bitpos: [6]; default: 0;
+         *  Set this bit  to enable AXI response function for axi wstrb err in axi write trans.
+         */
+        uint32_t mem_aw_resp_en_axi_wstrb:1;
+        /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu valid err in axi read trans.
+         */
+        uint32_t mem_ar_resp_en_mmu_vld:1;
+        /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu gid err in axi read trans.
+         */
+        uint32_t mem_ar_resp_en_mmu_gid:1;
+        /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu ecc err in axi read trans.
+         */
+        uint32_t mem_ar_resp_en_mmu_ecc:1;
+        /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0;
+         *  Set this bit  to enable AXI response function for mmu sensitive err in axi read
+         *  trans.
+         */
+        uint32_t mem_ar_resp_en_mmu_sens:1;
+        /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0;
+         *  Set this bit  to enable AXI response function for axi size err in axi read trans.
+         */
+        uint32_t mem_ar_resp_en_axi_size:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} spi_mem_s_axi_err_resp_en_reg_t;
+
+
+/** Group: Flash timing registers */
+/** Type of mem_timing_cali register
+ *  SPI0 flash timing calibration register
+ */
+typedef union {
+    struct {
+        /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable timing adjust clock for all reading operations.
+         */
+        uint32_t mem_timing_clk_ena:1;
+        /** mem_timing_cali : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable timing auto-calibration for all reading operations.
+         */
+        uint32_t mem_timing_cali:1;
+        /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0;
+         *  add extra dummy spi clock cycle length for spi clock calibration.
+         */
+        uint32_t mem_extra_dummy_cyclelen:3;
+        /** mem_dll_timing_cali : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
+         *  flash.
+         */
+        uint32_t mem_dll_timing_cali:1;
+        /** mem_timing_cali_update : WT; bitpos: [6]; default: 0;
+         *  Set this bit to update delay mode, delay num and extra dummy in MSPI.
+         */
+        uint32_t mem_timing_cali_update:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} spi_mem_s_timing_cali_reg_t;
+
+/** Type of mem_din_mode register
+ *  MSPI flash input timing delay mode control register
+ */
+typedef union {
+    struct {
+        /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t mem_din0_mode:3;
+        /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t mem_din1_mode:3;
+        /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t mem_din2_mode:3;
+        /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t mem_din3_mode:3;
+        /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk
+         */
+        uint32_t mem_din4_mode:3;
+        /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk
+         */
+        uint32_t mem_din5_mode:3;
+        /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk
+         */
+        uint32_t mem_din6_mode:3;
+        /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk
+         */
+        uint32_t mem_din7_mode:3;
+        /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk
+         */
+        uint32_t mem_dins_mode:3;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_s_din_mode_reg_t;
+
+/** Type of mem_din_num register
+ *  MSPI flash input timing delay number control register
+ */
+typedef union {
+    struct {
+        /** mem_din0_num : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t mem_din0_num:2;
+        /** mem_din1_num : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t mem_din1_num:2;
+        /** mem_din2_num : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t mem_din2_num:2;
+        /** mem_din3_num : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t mem_din3_num:2;
+        /** mem_din4_num : R/W; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t mem_din4_num:2;
+        /** mem_din5_num : R/W; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t mem_din5_num:2;
+        /** mem_din6_num : R/W; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t mem_din6_num:2;
+        /** mem_din7_num : R/W; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t mem_din7_num:2;
+        /** mem_dins_num : R/W; bitpos: [17:16]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t mem_dins_num:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_mem_s_din_num_reg_t;
+
+/** Type of mem_dout_mode register
+ *  MSPI flash output timing adjustment control register
+ */
+typedef union {
+    struct {
+        /** mem_dout0_mode : R/W; bitpos: [0]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t mem_dout0_mode:1;
+        /** mem_dout1_mode : R/W; bitpos: [1]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t mem_dout1_mode:1;
+        /** mem_dout2_mode : R/W; bitpos: [2]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t mem_dout2_mode:1;
+        /** mem_dout3_mode : R/W; bitpos: [3]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t mem_dout3_mode:1;
+        /** mem_dout4_mode : R/W; bitpos: [4]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the spi_clk
+         */
+        uint32_t mem_dout4_mode:1;
+        /** mem_dout5_mode : R/W; bitpos: [5]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the spi_clk
+         */
+        uint32_t mem_dout5_mode:1;
+        /** mem_dout6_mode : R/W; bitpos: [6]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the spi_clk
+         */
+        uint32_t mem_dout6_mode:1;
+        /** mem_dout7_mode : R/W; bitpos: [7]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the spi_clk
+         */
+        uint32_t mem_dout7_mode:1;
+        /** mem_douts_mode : R/W; bitpos: [8]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the spi_clk
+         */
+        uint32_t mem_douts_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_mem_s_dout_mode_reg_t;
+
+
+/** Group: External RAM timing registers */
+/** Type of smem_timing_cali register
+ *  MSPI external RAM timing calibration register
+ */
+typedef union {
+    struct {
+        /** smem_timing_clk_ena : R/W; bitpos: [0]; default: 1;
+         *  For sram, the bit is used to enable timing adjust clock for all reading operations.
+         */
+        uint32_t smem_timing_clk_ena:1;
+        /** smem_timing_cali : R/W; bitpos: [1]; default: 0;
+         *  For sram, the bit is used to enable timing auto-calibration for all reading
+         *  operations.
+         */
+        uint32_t smem_timing_cali:1;
+        /** smem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0;
+         *  For sram, add extra dummy spi clock cycle length for spi clock calibration.
+         */
+        uint32_t smem_extra_dummy_cyclelen:3;
+        /** smem_dll_timing_cali : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
+         *  EXT_RAM.
+         */
+        uint32_t smem_dll_timing_cali:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} spi_mem_s_smem_timing_cali_reg_t;
+
+/** Type of smem_din_mode register
+ *  MSPI external RAM input timing delay mode control register
+ */
+typedef union {
+    struct {
+        /** smem_din0_mode : R/W; bitpos: [2:0]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din0_mode:3;
+        /** smem_din1_mode : R/W; bitpos: [5:3]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din1_mode:3;
+        /** smem_din2_mode : R/W; bitpos: [8:6]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din2_mode:3;
+        /** smem_din3_mode : R/W; bitpos: [11:9]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din3_mode:3;
+        /** smem_din4_mode : R/W; bitpos: [14:12]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din4_mode:3;
+        /** smem_din5_mode : R/W; bitpos: [17:15]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din5_mode:3;
+        /** smem_din6_mode : R/W; bitpos: [20:18]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din6_mode:3;
+        /** smem_din7_mode : R/W; bitpos: [23:21]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din7_mode:3;
+        /** smem_dins_mode : R/W; bitpos: [26:24]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_dins_mode:3;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_s_smem_din_mode_reg_t;
+
+/** Type of smem_din_num register
+ *  MSPI external RAM input timing delay number control register
+ */
+typedef union {
+    struct {
+        /** smem_din0_num : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din0_num:2;
+        /** smem_din1_num : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din1_num:2;
+        /** smem_din2_num : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din2_num:2;
+        /** smem_din3_num : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din3_num:2;
+        /** smem_din4_num : R/W; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din4_num:2;
+        /** smem_din5_num : R/W; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din5_num:2;
+        /** smem_din6_num : R/W; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din6_num:2;
+        /** smem_din7_num : R/W; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din7_num:2;
+        /** smem_dins_num : R/W; bitpos: [17:16]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_dins_num:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_mem_s_smem_din_num_reg_t;
+
+/** Type of smem_dout_mode register
+ *  MSPI external RAM output timing adjustment control register
+ */
+typedef union {
+    struct {
+        /** smem_dout0_mode : R/W; bitpos: [0]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout0_mode:1;
+        /** smem_dout1_mode : R/W; bitpos: [1]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout1_mode:1;
+        /** smem_dout2_mode : R/W; bitpos: [2]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout2_mode:1;
+        /** smem_dout3_mode : R/W; bitpos: [3]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout3_mode:1;
+        /** smem_dout4_mode : R/W; bitpos: [4]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout4_mode:1;
+        /** smem_dout5_mode : R/W; bitpos: [5]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout5_mode:1;
+        /** smem_dout6_mode : R/W; bitpos: [6]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout6_mode:1;
+        /** smem_dout7_mode : R/W; bitpos: [7]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout7_mode:1;
+        /** smem_douts_mode : R/W; bitpos: [8]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_douts_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_mem_s_smem_dout_mode_reg_t;
+
+/** Type of smem_din_hex_mode register
+ *  MSPI 16x external RAM input timing delay mode control register
+ */
+typedef union {
+    struct {
+        /** smem_din08_mode : R/W; bitpos: [2:0]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din08_mode:3;
+        /** smem_din09_mode : R/W; bitpos: [5:3]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din09_mode:3;
+        /** smem_din10_mode : R/W; bitpos: [8:6]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din10_mode:3;
+        /** smem_din11_mode : R/W; bitpos: [11:9]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din11_mode:3;
+        /** smem_din12_mode : R/W; bitpos: [14:12]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din12_mode:3;
+        /** smem_din13_mode : R/W; bitpos: [17:15]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din13_mode:3;
+        /** smem_din14_mode : R/W; bitpos: [20:18]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din14_mode:3;
+        /** smem_din15_mode : R/W; bitpos: [23:21]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_din15_mode:3;
+        /** smem_dins_hex_mode : R/W; bitpos: [26:24]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
+         *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
+         *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
+         *  spi_clk high edge,  6: input with the spi_clk low edge
+         */
+        uint32_t smem_dins_hex_mode:3;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_mem_s_smem_din_hex_mode_reg_t;
+
+/** Type of smem_din_hex_num register
+ *  MSPI 16x external RAM input timing delay number control register
+ */
+typedef union {
+    struct {
+        /** smem_din08_num : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din08_num:2;
+        /** smem_din09_num : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din09_num:2;
+        /** smem_din10_num : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din10_num:2;
+        /** smem_din11_num : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din11_num:2;
+        /** smem_din12_num : R/W; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din12_num:2;
+        /** smem_din13_num : R/W; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din13_num:2;
+        /** smem_din14_num : R/W; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din14_num:2;
+        /** smem_din15_num : R/W; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_din15_num:2;
+        /** smem_dins_hex_num : R/W; bitpos: [17:16]; default: 0;
+         *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...
+         */
+        uint32_t smem_dins_hex_num:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_mem_s_smem_din_hex_num_reg_t;
+
+/** Type of smem_dout_hex_mode register
+ *  MSPI 16x external RAM output timing adjustment control register
+ */
+typedef union {
+    struct {
+        /** smem_dout08_mode : R/W; bitpos: [0]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout08_mode:1;
+        /** smem_dout09_mode : R/W; bitpos: [1]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout09_mode:1;
+        /** smem_dout10_mode : R/W; bitpos: [2]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout10_mode:1;
+        /** smem_dout11_mode : R/W; bitpos: [3]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout11_mode:1;
+        /** smem_dout12_mode : R/W; bitpos: [4]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout12_mode:1;
+        /** smem_dout13_mode : R/W; bitpos: [5]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout13_mode:1;
+        /** smem_dout14_mode : R/W; bitpos: [6]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout14_mode:1;
+        /** smem_dout15_mode : R/W; bitpos: [7]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_dout15_mode:1;
+        /** smem_douts_hex_mode : R/W; bitpos: [8]; default: 0;
+         *  the output signals are delayed by system clock cycles, 0: output without delayed,
+         *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+         *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
+         *  with the spi_clk high edge ,6: output with the spi_clk low edge
+         */
+        uint32_t smem_douts_hex_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_mem_s_smem_dout_hex_mode_reg_t;
+
+
+/** Group: Manual Encryption plaintext Memory */
+/** Type of mem_xts_plain_base register
+ *  The base address of the memory that stores plaintext in Manual Encryption
+ */
+typedef union {
+    struct {
+        /** xts_plain : R/W; bitpos: [31:0]; default: 0;
+         *  This field is only used to generate include file in c case. This field is useless.
+         *  Please do not use this field.
+         */
+        uint32_t xts_plain:32;
+    };
+    uint32_t val;
+} spi_mem_s_xts_plain_base_reg_t;
+
+
+/** Group: Manual Encryption configuration registers */
+/** Type of mem_xts_linesize register
+ *  Manual Encryption Line-Size register
+ */
+typedef union {
+    struct {
+        /** xts_linesize : R/W; bitpos: [1:0]; default: 0;
+         *  This bits stores the line-size parameter which will be used in manual encryption
+         *  calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1:
+         *  32-bytes, 2: 64-bytes, 3:reserved.
+         */
+        uint32_t xts_linesize:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} spi_mem_s_xts_linesize_reg_t;
+
+/** Type of mem_xts_destination register
+ *  Manual Encryption destination register
+ */
+typedef union {
+    struct {
+        /** xts_destination : R/W; bitpos: [0]; default: 0;
+         *  This bit stores the destination parameter which will be used in manual encryption
+         *  calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.
+         */
+        uint32_t xts_destination:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi_mem_s_xts_destination_reg_t;
+
+/** Type of mem_xts_physical_address register
+ *  Manual Encryption physical address register
+ */
+typedef union {
+    struct {
+        /** xts_physical_address : R/W; bitpos: [25:0]; default: 0;
+         *  This bits stores the physical-address parameter which will be used in manual
+         *  encryption calculation. This value should aligned with byte number decided by
+         *  line-size parameter.
+         */
+        uint32_t xts_physical_address:26;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} spi_mem_s_xts_physical_address_reg_t;
+
+
+/** Group: Manual Encryption control and status registers */
+/** Type of mem_xts_trigger register
+ *  Manual Encryption physical address register
+ */
+typedef union {
+    struct {
+        /** xts_trigger : WT; bitpos: [0]; default: 0;
+         *  Set this bit to trigger the process of manual encryption calculation. This action
+         *  should only be asserted when manual encryption status is 0. After this action,
+         *  manual encryption status becomes 1. After calculation is done, manual encryption
+         *  status becomes 2.
+         */
+        uint32_t xts_trigger:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi_mem_s_xts_trigger_reg_t;
+
+/** Type of mem_xts_release register
+ *  Manual Encryption physical address register
+ */
+typedef union {
+    struct {
+        /** xts_release : WT; bitpos: [0]; default: 0;
+         *  Set this bit to release encrypted result to mspi. This action should only be
+         *  asserted when manual encryption status is 2. After this action, manual encryption
+         *  status will become 3.
+         */
+        uint32_t xts_release:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi_mem_s_xts_release_reg_t;
+
+/** Type of mem_xts_destroy register
+ *  Manual Encryption physical address register
+ */
+typedef union {
+    struct {
+        /** xts_destroy : WT; bitpos: [0]; default: 0;
+         *  Set this bit to destroy encrypted result. This action should be asserted only when
+         *  manual encryption status is 3. After this action, manual encryption status will
+         *  become 0.
+         */
+        uint32_t xts_destroy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} spi_mem_s_xts_destroy_reg_t;
+
+/** Type of mem_xts_state register
+ *  Manual Encryption physical address register
+ */
+typedef union {
+    struct {
+        /** xts_state : RO; bitpos: [1:0]; default: 0;
+         *  This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
+         *  calculation, 2: encryption calculation is done but the encrypted result is
+         *  invisible to mspi, 3: the encrypted result is visible to mspi.
+         */
+        uint32_t xts_state:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} spi_mem_s_xts_state_reg_t;
+
+
+/** Group: Manual Encryption version control register */
+/** Type of mem_xts_date register
+ *  Manual Encryption version register
+ */
+typedef union {
+    struct {
+        /** xts_date : R/W; bitpos: [29:0]; default: 538972176;
+         *  This bits stores the last modified-time of manual encryption feature.
+         */
+        uint32_t xts_date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_mem_s_xts_date_reg_t;
+
+
+/** Group: MMU access registers */
+/** Type of mem_mmu_item_content register
+ *  MSPI-MMU item content register
+ */
+typedef union {
+    struct {
+        /** mmu_item_content : R/W; bitpos: [31:0]; default: 892;
+         *  MSPI-MMU item content
+         */
+        uint32_t mmu_item_content:32;
+    };
+    uint32_t val;
+} spi_mem_s_mmu_item_content_reg_t;
+
+/** Type of mem_mmu_item_index register
+ *  MSPI-MMU item index register
+ */
+typedef union {
+    struct {
+        /** mmu_item_index : R/W; bitpos: [31:0]; default: 0;
+         *  MSPI-MMU item index
+         */
+        uint32_t mmu_item_index:32;
+    };
+    uint32_t val;
+} spi_mem_s_mmu_item_index_reg_t;
+
+
+/** Group: MMU power control and configuration registers */
+/** Type of mem_mmu_power_ctrl register
+ *  MSPI MMU power control register
+ */
+typedef union {
+    struct {
+        /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable mmu-memory clock force on
+         */
+        uint32_t mmu_mem_force_on:1;
+        /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to force mmu-memory powerdown
+         */
+        uint32_t mmu_mem_force_pd:1;
+        /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to force mmu-memory powerup, in this case, the power should also be
+         *  controlled by rtc.
+         */
+        uint32_t mmu_mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896;
+         *  MMU PSRAM aux control register
+         */
+        uint32_t mem_aux_ctrl:14;
+        /** mem_rdn_ena : R/W; bitpos: [30]; default: 0;
+         *  ECO register enable bit
+         */
+        uint32_t mem_rdn_ena:1;
+        /** mem_rdn_result : RO; bitpos: [31]; default: 0;
+         *  MSPI module clock domain and AXI clock domain ECO register result register
+         */
+        uint32_t mem_rdn_result:1;
+    };
+    uint32_t val;
+} spi_mem_s_mmu_power_ctrl_reg_t;
+
+
+/** Group: External mem cryption DPA registers */
+/** Type of mem_dpa_ctrl register
+ *  SPI memory cryption DPA register
+ */
+typedef union {
+    struct {
+        /** crypt_security_level : R/W; bitpos: [2:0]; default: 7;
+         *  Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7:
+         *  The bigger the number is, the more secure the cryption is. (Note that the
+         *  performance of cryption will decrease together with this number increasing)
+         */
+        uint32_t crypt_security_level:3;
+        /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1;
+         *  Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the
+         *  calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that
+         *  using key 1.
+         */
+        uint32_t crypt_calc_d_dpa_en:1;
+        /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0;
+         *  1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and
+         *  SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.
+         */
+        uint32_t crypt_dpa_select_register:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} spi_mem_s_dpa_ctrl_reg_t;
+
+
+/** Group: ECO registers */
+/** Type of mem_registerrnd_eco_high register
+ *  MSPI ECO high register
+ */
+typedef union {
+    struct {
+        /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892;
+         *  ECO high register
+         */
+        uint32_t mem_registerrnd_eco_high:32;
+    };
+    uint32_t val;
+} spi_mem_s_registerrnd_eco_high_reg_t;
+
+/** Type of mem_registerrnd_eco_low register
+ *  MSPI ECO low register
+ */
+typedef union {
+    struct {
+        /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892;
+         *  ECO low register
+         */
+        uint32_t mem_registerrnd_eco_low:32;
+    };
+    uint32_t val;
+} spi_mem_s_registerrnd_eco_low_reg_t;
+
+
+/** Group: Version control register */
+/** Type of mem_date register
+ *  SPI0 version control register
+ */
+typedef union {
+    struct {
+        /** mem_date : R/W; bitpos: [27:0]; default: 36712704;
+         *  SPI0 register version.
+         */
+        uint32_t mem_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi_mem_s_date_reg_t;
+
+
+typedef struct spi_mem_s_dev_t {
+    volatile spi_mem_s_cmd_reg_t mem_cmd;
+    uint32_t reserved_004;
+    volatile spi_mem_s_ctrl_reg_t mem_ctrl;
+    volatile spi_mem_s_ctrl1_reg_t mem_ctrl1;
+    volatile spi_mem_s_ctrl2_reg_t mem_ctrl2;
+    volatile spi_mem_s_clock_reg_t mem_clock;
+    volatile spi_mem_s_user_reg_t mem_user;
+    volatile spi_mem_s_user1_reg_t mem_user1;
+    volatile spi_mem_s_user2_reg_t mem_user2;
+    uint32_t reserved_024[2];
+    volatile spi_mem_s_rd_status_reg_t mem_rd_status;
+    uint32_t reserved_030;
+    volatile spi_mem_s_misc_reg_t mem_misc;
+    uint32_t reserved_038;
+    volatile spi_mem_s_cache_fctrl_reg_t mem_cache_fctrl;
+    volatile spi_mem_s_cache_sctrl_reg_t mem_cache_sctrl;
+    volatile spi_mem_s_sram_cmd_reg_t mem_sram_cmd;
+    volatile spi_mem_s_sram_drd_cmd_reg_t mem_sram_drd_cmd;
+    volatile spi_mem_s_sram_dwr_cmd_reg_t mem_sram_dwr_cmd;
+    volatile spi_mem_s_sram_clk_reg_t mem_sram_clk;
+    volatile spi_mem_s_fsm_reg_t mem_fsm;
+    uint32_t reserved_058[26];
+    volatile spi_mem_s_int_ena_reg_t mem_int_ena;
+    volatile spi_mem_s_int_clr_reg_t mem_int_clr;
+    volatile spi_mem_s_int_raw_reg_t mem_int_raw;
+    volatile spi_mem_s_int_st_reg_t mem_int_st;
+    uint32_t reserved_0d0;
+    volatile spi_mem_s_ddr_reg_t mem_ddr;
+    volatile spi_mem_s_smem_ddr_reg_t smem_ddr;
+    uint32_t reserved_0dc[9];
+    volatile spi_mem_s_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4];
+    volatile spi_mem_s_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4];
+    volatile spi_mem_s_fmem_pmsn_size_reg_t fmem_pmsn_size[4];
+    volatile spi_mem_s_smem_pmsn_attr_reg_t smem_pmsn_attr[4];
+    volatile spi_mem_s_smem_pmsn_addr_reg_t smem_pmsn_addr[4];
+    volatile spi_mem_s_smem_pmsn_size_reg_t smem_pmsn_size[4];
+    uint32_t reserved_160;
+    volatile spi_mem_s_pms_reject_reg_t mem_pms_reject;
+    volatile spi_mem_s_ecc_ctrl_reg_t mem_ecc_ctrl;
+    volatile spi_mem_s_ecc_err_addr_reg_t mem_ecc_err_addr;
+    volatile spi_mem_s_axi_err_addr_reg_t mem_axi_err_addr;
+    volatile spi_mem_s_smem_ecc_ctrl_reg_t smem_ecc_ctrl;
+    volatile spi_mem_s_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl;
+    volatile spi_mem_s_axi_err_resp_en_reg_t mem_axi_err_resp_en;
+    volatile spi_mem_s_timing_cali_reg_t mem_timing_cali;
+    volatile spi_mem_s_din_mode_reg_t mem_din_mode;
+    volatile spi_mem_s_din_num_reg_t mem_din_num;
+    volatile spi_mem_s_dout_mode_reg_t mem_dout_mode;
+    volatile spi_mem_s_smem_timing_cali_reg_t smem_timing_cali;
+    volatile spi_mem_s_smem_din_mode_reg_t smem_din_mode;
+    volatile spi_mem_s_smem_din_num_reg_t smem_din_num;
+    volatile spi_mem_s_smem_dout_mode_reg_t smem_dout_mode;
+    volatile spi_mem_s_smem_ac_reg_t smem_ac;
+    volatile spi_mem_s_smem_din_hex_mode_reg_t smem_din_hex_mode;
+    volatile spi_mem_s_smem_din_hex_num_reg_t smem_din_hex_num;
+    volatile spi_mem_s_smem_dout_hex_mode_reg_t smem_dout_hex_mode;
+    uint32_t reserved_1b0[20];
+    volatile spi_mem_s_clock_gate_reg_t mem_clock_gate;
+    uint32_t reserved_204[63];
+    volatile spi_mem_s_xts_plain_base_reg_t mem_xts_plain_base;
+    uint32_t reserved_304[15];
+    volatile spi_mem_s_xts_linesize_reg_t mem_xts_linesize;
+    volatile spi_mem_s_xts_destination_reg_t mem_xts_destination;
+    volatile spi_mem_s_xts_physical_address_reg_t mem_xts_physical_address;
+    volatile spi_mem_s_xts_trigger_reg_t mem_xts_trigger;
+    volatile spi_mem_s_xts_release_reg_t mem_xts_release;
+    volatile spi_mem_s_xts_destroy_reg_t mem_xts_destroy;
+    volatile spi_mem_s_xts_state_reg_t mem_xts_state;
+    volatile spi_mem_s_xts_date_reg_t mem_xts_date;
+    uint32_t reserved_360[7];
+    volatile spi_mem_s_mmu_item_content_reg_t mem_mmu_item_content;
+    volatile spi_mem_s_mmu_item_index_reg_t mem_mmu_item_index;
+    volatile spi_mem_s_mmu_power_ctrl_reg_t mem_mmu_power_ctrl;
+    volatile spi_mem_s_dpa_ctrl_reg_t mem_dpa_ctrl;
+    uint32_t reserved_38c[25];
+    volatile spi_mem_s_registerrnd_eco_high_reg_t mem_registerrnd_eco_high;
+    volatile spi_mem_s_registerrnd_eco_low_reg_t mem_registerrnd_eco_low;
+    uint32_t reserved_3f8;
+    volatile spi_mem_s_date_reg_t mem_date;
+} spi_mem_s_dev_t;
+
+extern spi_mem_s_dev_t SPIMEM2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_mem_s_dev_t) == 0x400, "Invalid size of spi_mem_s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_reg.h
new file mode 100644
index 0000000000..f5aa935cca
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_reg.h
@@ -0,0 +1,2152 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI_CMD_REG register
+ *  Command control register
+ */
+#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
+/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_CONF_BITLEN    0x0003FFFFU
+#define SPI_CONF_BITLEN_M  (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
+#define SPI_CONF_BITLEN_V  0x0003FFFFU
+#define SPI_CONF_BITLEN_S  0
+/** SPI_UPDATE : WT; bitpos: [23]; default: 0;
+ *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+ *  clock domain, which is only used in SPI master mode.
+ */
+#define SPI_UPDATE    (BIT(23))
+#define SPI_UPDATE_M  (SPI_UPDATE_V << SPI_UPDATE_S)
+#define SPI_UPDATE_V  0x00000001U
+#define SPI_UPDATE_S  23
+/** SPI_USR : R/W/SC; bitpos: [24]; default: 0;
+ *  User define command enable.  An operation will be triggered when the bit is set.
+ *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+ *  changed by CONF_buf.
+ */
+#define SPI_USR    (BIT(24))
+#define SPI_USR_M  (SPI_USR_V << SPI_USR_S)
+#define SPI_USR_V  0x00000001U
+#define SPI_USR_S  24
+
+/** SPI_ADDR_REG register
+ *  Address value register
+ */
+#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
+/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  Address to slave. Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI_USR_ADDR_VALUE_M  (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI_USR_ADDR_VALUE_S  0
+
+/** SPI_CTRL_REG register
+ *  SPI control register
+ */
+#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
+/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
+ *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
+ *  the FSPI bus signals are output. Can be configured in CONF state.
+ */
+#define SPI_DUMMY_OUT    (BIT(3))
+#define SPI_DUMMY_OUT_M  (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
+#define SPI_DUMMY_OUT_V  0x00000001U
+#define SPI_DUMMY_OUT_S  3
+/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+ *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FADDR_DUAL    (BIT(5))
+#define SPI_FADDR_DUAL_M  (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
+#define SPI_FADDR_DUAL_V  0x00000001U
+#define SPI_FADDR_DUAL_S  5
+/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
+ *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FADDR_QUAD    (BIT(6))
+#define SPI_FADDR_QUAD_M  (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
+#define SPI_FADDR_QUAD_V  0x00000001U
+#define SPI_FADDR_QUAD_S  6
+/** SPI_FADDR_OCT : R/W; bitpos: [7]; default: 0;
+ *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+//this field is only for GPSPI2
+#define SPI_FADDR_OCT    (BIT(7))
+#define SPI_FADDR_OCT_M  (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
+#define SPI_FADDR_OCT_V  0x00000001U
+#define SPI_FADDR_OCT_S  7
+/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
+ *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FCMD_DUAL    (BIT(8))
+#define SPI_FCMD_DUAL_M  (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
+#define SPI_FCMD_DUAL_V  0x00000001U
+#define SPI_FCMD_DUAL_S  8
+/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
+ *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FCMD_QUAD    (BIT(9))
+#define SPI_FCMD_QUAD_M  (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
+#define SPI_FCMD_QUAD_V  0x00000001U
+#define SPI_FCMD_QUAD_S  9
+/** SPI_FCMD_OCT : R/W; bitpos: [10]; default: 0;
+ *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+//this field is only for GPSPI2
+#define SPI_FCMD_OCT    (BIT(10))
+#define SPI_FCMD_OCT_M  (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
+#define SPI_FCMD_OCT_V  0x00000001U
+#define SPI_FCMD_OCT_S  10
+/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+ *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
+ *  be configured in CONF state.
+ */
+#define SPI_FREAD_DUAL    (BIT(14))
+#define SPI_FREAD_DUAL_M  (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
+#define SPI_FREAD_DUAL_V  0x00000001U
+#define SPI_FREAD_DUAL_S  14
+/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
+ *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
+ *  be configured in CONF state.
+ */
+#define SPI_FREAD_QUAD    (BIT(15))
+#define SPI_FREAD_QUAD_M  (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
+#define SPI_FREAD_QUAD_V  0x00000001U
+#define SPI_FREAD_QUAD_S  15
+/** SPI_FREAD_OCT : R/W; bitpos: [16]; default: 0;
+ *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
+ *  be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_FREAD_OCT    (BIT(16))
+#define SPI_FREAD_OCT_M  (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
+#define SPI_FREAD_OCT_V  0x00000001U
+#define SPI_FREAD_OCT_S  16
+/** SPI_Q_POL : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+ *  CONF state.
+ */
+#define SPI_Q_POL    (BIT(18))
+#define SPI_Q_POL_M  (SPI_Q_POL_V << SPI_Q_POL_S)
+#define SPI_Q_POL_V  0x00000001U
+#define SPI_Q_POL_S  18
+/** SPI_D_POL : R/W; bitpos: [19]; default: 1;
+ *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+ *  CONF state.
+ */
+#define SPI_D_POL    (BIT(19))
+#define SPI_D_POL_M  (SPI_D_POL_V << SPI_D_POL_S)
+#define SPI_D_POL_V  0x00000001U
+#define SPI_D_POL_S  19
+/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1;
+ *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+ *  configured in CONF state.
+ */
+#define SPI_HOLD_POL    (BIT(20))
+#define SPI_HOLD_POL_M  (SPI_HOLD_POL_V << SPI_HOLD_POL_S)
+#define SPI_HOLD_POL_V  0x00000001U
+#define SPI_HOLD_POL_S  20
+/** SPI_WP_POL : R/W; bitpos: [21]; default: 1;
+ *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
+ *  be configured in CONF state.
+ */
+#define SPI_WP_POL    (BIT(21))
+#define SPI_WP_POL_M  (SPI_WP_POL_V << SPI_WP_POL_S)
+#define SPI_WP_POL_V  0x00000001U
+#define SPI_WP_POL_S  21
+/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0;
+ *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+ *  state.
+ */
+#define SPI_RD_BIT_ORDER    0x00000003U
+#define SPI_RD_BIT_ORDER_M  (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
+#define SPI_RD_BIT_ORDER_V  0x00000003U
+#define SPI_RD_BIT_ORDER_S  23
+/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0;
+ *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+ *  configured in CONF state.
+ */
+#define SPI_WR_BIT_ORDER    0x00000003U
+#define SPI_WR_BIT_ORDER_M  (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
+#define SPI_WR_BIT_ORDER_V  0x00000003U
+#define SPI_WR_BIT_ORDER_S  25
+
+/** SPI_CLOCK_REG register
+ *  SPI clock control register
+ */
+#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc)
+/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
+ *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+ *  0. Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_L    0x0000003FU
+#define SPI_CLKCNT_L_M  (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
+#define SPI_CLKCNT_L_V  0x0000003FU
+#define SPI_CLKCNT_L_S  0
+/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
+ *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+ *  must be 0. Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_H    0x0000003FU
+#define SPI_CLKCNT_H_M  (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
+#define SPI_CLKCNT_H_V  0x0000003FU
+#define SPI_CLKCNT_H_S  6
+/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
+ *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+ *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_N    0x0000003FU
+#define SPI_CLKCNT_N_M  (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
+#define SPI_CLKCNT_N_V  0x0000003FU
+#define SPI_CLKCNT_N_S  12
+/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
+ *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+ */
+#define SPI_CLKDIV_PRE    0x0000000FU
+#define SPI_CLKDIV_PRE_M  (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
+#define SPI_CLKDIV_PRE_V  0x0000000FU
+#define SPI_CLKDIV_PRE_S  18
+/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
+ *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+ *  clock. Can be configured in CONF state.
+ */
+#define SPI_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
+#define SPI_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI_CLK_EQU_SYSCLK_S  31
+
+/** SPI_USER_REG register
+ *  SPI USER control register
+ */
+#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
+/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
+ *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUTDIN    (BIT(0))
+#define SPI_DOUTDIN_M  (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
+#define SPI_DOUTDIN_V  0x00000001U
+#define SPI_DOUTDIN_S  0
+/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0;
+ *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
+ *  Can be configured in CONF state.
+ */
+#define SPI_QPI_MODE    (BIT(3))
+#define SPI_QPI_MODE_M  (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
+#define SPI_QPI_MODE_V  0x00000001U
+#define SPI_QPI_MODE_S  3
+/** SPI_OPI_MODE : R/W; bitpos: [4]; default: 0;
+ *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+ *  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_OPI_MODE    (BIT(4))
+#define SPI_OPI_MODE_M  (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
+#define SPI_OPI_MODE_V  0x00000001U
+#define SPI_OPI_MODE_S  4
+/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
+ *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+ *  spi_ck_i. 1:tsck = !spi_ck_i.
+ */
+#define SPI_TSCK_I_EDGE    (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
+#define SPI_TSCK_I_EDGE_V  0x00000001U
+#define SPI_TSCK_I_EDGE_S  5
+/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1;
+ *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CS_HOLD    (BIT(6))
+#define SPI_CS_HOLD_M  (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
+#define SPI_CS_HOLD_V  0x00000001U
+#define SPI_CS_HOLD_S  6
+/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1;
+ *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CS_SETUP    (BIT(7))
+#define SPI_CS_SETUP_M  (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
+#define SPI_CS_SETUP_V  0x00000001U
+#define SPI_CS_SETUP_S  7
+/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
+ *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+ *  !spi_ck_i. 1:rsck = spi_ck_i.
+ */
+#define SPI_RSCK_I_EDGE    (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
+#define SPI_RSCK_I_EDGE_V  0x00000001U
+#define SPI_RSCK_I_EDGE_S  8
+/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CK_OUT_EDGE    (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
+#define SPI_CK_OUT_EDGE_V  0x00000001U
+#define SPI_CK_OUT_EDGE_S  9
+/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+ *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_DUAL    (BIT(12))
+#define SPI_FWRITE_DUAL_M  (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
+#define SPI_FWRITE_DUAL_V  0x00000001U
+#define SPI_FWRITE_DUAL_S  12
+/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+ *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_QUAD    (BIT(13))
+#define SPI_FWRITE_QUAD_M  (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
+#define SPI_FWRITE_QUAD_V  0x00000001U
+#define SPI_FWRITE_QUAD_S  13
+/** SPI_FWRITE_OCT : R/W; bitpos: [14]; default: 0;
+ *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+ *  state.
+ */
+//this field is only for GPSPI2
+#define SPI_FWRITE_OCT    (BIT(14))
+#define SPI_FWRITE_OCT_M  (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
+#define SPI_FWRITE_OCT_V  0x00000001U
+#define SPI_FWRITE_OCT_S  14
+/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
+ *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+ *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
+ *  not seg-trans mode. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_USR_CONF_NXT    (BIT(15))
+#define SPI_USR_CONF_NXT_M  (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
+#define SPI_USR_CONF_NXT_V  0x00000001U
+#define SPI_USR_CONF_NXT_S  15
+/** SPI_SIO : R/W; bitpos: [17]; default: 0;
+ *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+ *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+ */
+#define SPI_SIO    (BIT(17))
+#define SPI_SIO_M  (SPI_SIO_V << SPI_SIO_S)
+#define SPI_SIO_V  0x00000001U
+#define SPI_SIO_S  17
+/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+ *  disable. Can be configured in CONF state.
+ */
+#define SPI_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
+#define SPI_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI_USR_MISO_HIGHPART_S  24
+/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+ *  0: disable.  Can be configured in CONF state.
+ */
+#define SPI_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
+#define SPI_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI_USR_MOSI_HIGHPART_S  25
+/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+ *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+ *  CONF state.
+ */
+#define SPI_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
+#define SPI_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI_USR_DUMMY_IDLE_S  26
+/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
+ *  This bit enable the write-data phase of an operation. Can be configured in CONF
+ *  state.
+ */
+#define SPI_USR_MOSI    (BIT(27))
+#define SPI_USR_MOSI_M  (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
+#define SPI_USR_MOSI_V  0x00000001U
+#define SPI_USR_MOSI_S  27
+/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
+ *  This bit enable the read-data phase of an operation. Can be configured in CONF
+ *  state.
+ */
+#define SPI_USR_MISO    (BIT(28))
+#define SPI_USR_MISO_M  (SPI_USR_MISO_V << SPI_USR_MISO_S)
+#define SPI_USR_MISO_V  0x00000001U
+#define SPI_USR_MISO_S  28
+/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+ *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY    (BIT(29))
+#define SPI_USR_DUMMY_M  (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
+#define SPI_USR_DUMMY_V  0x00000001U
+#define SPI_USR_DUMMY_S  29
+/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
+ *  This bit enable the address phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR    (BIT(30))
+#define SPI_USR_ADDR_M  (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
+#define SPI_USR_ADDR_V  0x00000001U
+#define SPI_USR_ADDR_S  30
+/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+ *  This bit enable the command phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND    (BIT(31))
+#define SPI_USR_COMMAND_M  (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
+#define SPI_USR_COMMAND_V  0x00000001U
+#define SPI_USR_COMMAND_S  31
+
+/** SPI_USER1_REG register
+ *  SPI USER control register 1
+ */
+#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)
+/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
+ *  The length in spi_clk cycles of dummy phase. The register value shall be
+ *  (cycle_num-1). Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY_CYCLELEN    0x000000FFU
+#define SPI_USR_DUMMY_CYCLELEN_M  (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
+#define SPI_USR_DUMMY_CYCLELEN_V  0x000000FFU
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
+ *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+ *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+ *  GP-SPI master FD/HD-mode.
+ */
+#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_M  (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S)
+#define SPI_MST_WFULL_ERR_END_EN_V  0x00000001U
+#define SPI_MST_WFULL_ERR_END_EN_S  16
+/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
+ *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+ *  bit. Can be configured in CONF state.
+ */
+#define SPI_CS_SETUP_TIME    0x0000001FU
+#define SPI_CS_SETUP_TIME_M  (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
+#define SPI_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_CS_SETUP_TIME_S  17
+/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
+ *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS_HOLD_TIME    0x0000001FU
+#define SPI_CS_HOLD_TIME_M  (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
+#define SPI_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_CS_HOLD_TIME_S  22
+/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
+ *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+ *  be configured in CONF state.
+ */
+#define SPI_USR_ADDR_BITLEN    0x0000001FU
+#define SPI_USR_ADDR_BITLEN_M  (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
+#define SPI_USR_ADDR_BITLEN_V  0x0000001FU
+#define SPI_USR_ADDR_BITLEN_S  27
+
+/** SPI_USER2_REG register
+ *  SPI USER control register 2
+ */
+#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)
+/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  The value of  command. Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI_USR_COMMAND_VALUE_M  (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
+#define SPI_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI_USR_COMMAND_VALUE_S  0
+/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
+ *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+ *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+ *  is valid in GP-SPI master FD/HD-mode.
+ */
+#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_M  (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S)
+#define SPI_MST_REMPTY_ERR_END_EN_V  0x00000001U
+#define SPI_MST_REMPTY_ERR_END_EN_S  27
+/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+ *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+ *  be configured in CONF state.
+ */
+#define SPI_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI_USR_COMMAND_BITLEN_M  (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
+#define SPI_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI_USR_COMMAND_BITLEN_S  28
+
+/** SPI_MS_DLEN_REG register
+ *  SPI data bit length control register
+ */
+#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c)
+/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  The value of these bits is the configured SPI transmission data bit length in
+ *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+ *  the configured bit length in slave mode DMA RX controlled transfer. The register
+ *  value shall be (bit_num-1). Can be configured in CONF state.
+ */
+#define SPI_MS_DATA_BITLEN    0x0003FFFFU
+#define SPI_MS_DATA_BITLEN_M  (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S)
+#define SPI_MS_DATA_BITLEN_V  0x0003FFFFU
+#define SPI_MS_DATA_BITLEN_S  0
+
+/** SPI_MISC_REG register
+ *  SPI misc register
+ */
+#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
+/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS0_DIS    (BIT(0))
+#define SPI_CS0_DIS_M  (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
+#define SPI_CS0_DIS_V  0x00000001U
+#define SPI_CS0_DIS_S  0
+/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS1_DIS    (BIT(1))
+#define SPI_CS1_DIS_M  (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
+#define SPI_CS1_DIS_V  0x00000001U
+#define SPI_CS1_DIS_S  1
+/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS2_DIS    (BIT(2))
+#define SPI_CS2_DIS_M  (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
+#define SPI_CS2_DIS_V  0x00000001U
+#define SPI_CS2_DIS_S  2
+/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_CS3_DIS    (BIT(3))
+#define SPI_CS3_DIS_M  (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
+#define SPI_CS3_DIS_V  0x00000001U
+#define SPI_CS3_DIS_S  3
+/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_CS4_DIS    (BIT(4))
+#define SPI_CS4_DIS_M  (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
+#define SPI_CS4_DIS_V  0x00000001U
+#define SPI_CS4_DIS_S  4
+/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_CS5_DIS    (BIT(5))
+#define SPI_CS5_DIS_M  (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
+#define SPI_CS5_DIS_V  0x00000001U
+#define SPI_CS5_DIS_S  5
+/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
+ *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+ */
+#define SPI_CK_DIS    (BIT(6))
+#define SPI_CK_DIS_M  (SPI_CK_DIS_V << SPI_CK_DIS_S)
+#define SPI_CK_DIS_V  0x00000001U
+#define SPI_CK_DIS_S  6
+/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
+ *  In the master mode the bits are the polarity of spi cs line, the value is
+ *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+ */
+//This field for GPSPI3 is only 3-bit-width
+#define SPI_MASTER_CS_POL    0x0000003FU
+#define SPI_MASTER_CS_POL_M  (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
+#define SPI_MASTER_CS_POL_V  0x0000003FU
+#define SPI_MASTER_CS_POL_S  7
+/** SPI_CLK_DATA_DTR_EN : R/W; bitpos: [16]; default: 0;
+ *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+ *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+ */
+//this field is only for GPSPI2
+#define SPI_CLK_DATA_DTR_EN    (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_M  (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
+#define SPI_CLK_DATA_DTR_EN_V  0x00000001U
+#define SPI_CLK_DATA_DTR_EN_S  16
+/** SPI_DATA_DTR_EN : R/W; bitpos: [17]; default: 0;
+ *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+ *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+ *  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DATA_DTR_EN    (BIT(17))
+#define SPI_DATA_DTR_EN_M  (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
+#define SPI_DATA_DTR_EN_V  0x00000001U
+#define SPI_DATA_DTR_EN_S  17
+/** SPI_ADDR_DTR_EN : R/W; bitpos: [18]; default: 0;
+ *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+ *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_ADDR_DTR_EN    (BIT(18))
+#define SPI_ADDR_DTR_EN_M  (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
+#define SPI_ADDR_DTR_EN_V  0x00000001U
+#define SPI_ADDR_DTR_EN_S  18
+/** SPI_CMD_DTR_EN : R/W; bitpos: [19]; default: 0;
+ *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+ *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_CMD_DTR_EN    (BIT(19))
+#define SPI_CMD_DTR_EN_M  (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
+#define SPI_CMD_DTR_EN_V  0x00000001U
+#define SPI_CMD_DTR_EN_S  19
+/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
+ *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+ *  CONF state.
+ */
+#define SPI_SLAVE_CS_POL    (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
+#define SPI_SLAVE_CS_POL_V  0x00000001U
+#define SPI_SLAVE_CS_POL_S  23
+/** SPI_DQS_IDLE_EDGE : R/W; bitpos: [24]; default: 0;
+ *  The default value of spi_dqs. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DQS_IDLE_EDGE    (BIT(24))
+#define SPI_DQS_IDLE_EDGE_M  (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
+#define SPI_DQS_IDLE_EDGE_V  0x00000001U
+#define SPI_DQS_IDLE_EDGE_S  24
+/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
+ *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CK_IDLE_EDGE    (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
+#define SPI_CK_IDLE_EDGE_V  0x00000001U
+#define SPI_CK_IDLE_EDGE_S  29
+/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
+ *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+ */
+#define SPI_CS_KEEP_ACTIVE    (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
+#define SPI_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI_CS_KEEP_ACTIVE_S  30
+/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
+ *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+ *  spi quad input swap disable. Can be configured in CONF state.
+ */
+#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x00000001U
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+
+/** SPI_DIN_MODE_REG register
+ *  SPI input delay mode configuration
+ */
+#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)
+/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN0_MODE    0x00000003U
+#define SPI_DIN0_MODE_M  (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
+#define SPI_DIN0_MODE_V  0x00000003U
+#define SPI_DIN0_MODE_S  0
+/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN1_MODE    0x00000003U
+#define SPI_DIN1_MODE_M  (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
+#define SPI_DIN1_MODE_V  0x00000003U
+#define SPI_DIN1_MODE_S  2
+/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN2_MODE    0x00000003U
+#define SPI_DIN2_MODE_M  (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
+#define SPI_DIN2_MODE_V  0x00000003U
+#define SPI_DIN2_MODE_S  4
+/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN3_MODE    0x00000003U
+#define SPI_DIN3_MODE_M  (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
+#define SPI_DIN3_MODE_V  0x00000003U
+#define SPI_DIN3_MODE_S  6
+/** SPI_DIN4_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN4_MODE    0x00000003U
+#define SPI_DIN4_MODE_M  (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
+#define SPI_DIN4_MODE_V  0x00000003U
+#define SPI_DIN4_MODE_S  8
+/** SPI_DIN5_MODE : R/W; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN5_MODE    0x00000003U
+#define SPI_DIN5_MODE_M  (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
+#define SPI_DIN5_MODE_V  0x00000003U
+#define SPI_DIN5_MODE_S  10
+/** SPI_DIN6_MODE : R/W; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN6_MODE    0x00000003U
+#define SPI_DIN6_MODE_M  (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
+#define SPI_DIN6_MODE_V  0x00000003U
+#define SPI_DIN6_MODE_S  12
+/** SPI_DIN7_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN7_MODE    0x00000003U
+#define SPI_DIN7_MODE_M  (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
+#define SPI_DIN7_MODE_V  0x00000003U
+#define SPI_DIN7_MODE_S  14
+/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
+ *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+ *  state.
+ */
+#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_M  (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S)
+#define SPI_TIMING_HCLK_ACTIVE_V  0x00000001U
+#define SPI_TIMING_HCLK_ACTIVE_S  16
+
+/** SPI_DIN_NUM_REG register
+ *  SPI input delay number configuration
+ */
+#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28)
+/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN0_NUM    0x00000003U
+#define SPI_DIN0_NUM_M  (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
+#define SPI_DIN0_NUM_V  0x00000003U
+#define SPI_DIN0_NUM_S  0
+/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN1_NUM    0x00000003U
+#define SPI_DIN1_NUM_M  (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
+#define SPI_DIN1_NUM_V  0x00000003U
+#define SPI_DIN1_NUM_S  2
+/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN2_NUM    0x00000003U
+#define SPI_DIN2_NUM_M  (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
+#define SPI_DIN2_NUM_V  0x00000003U
+#define SPI_DIN2_NUM_S  4
+/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN3_NUM    0x00000003U
+#define SPI_DIN3_NUM_M  (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
+#define SPI_DIN3_NUM_V  0x00000003U
+#define SPI_DIN3_NUM_S  6
+/** SPI_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN4_NUM    0x00000003U
+#define SPI_DIN4_NUM_M  (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
+#define SPI_DIN4_NUM_V  0x00000003U
+#define SPI_DIN4_NUM_S  8
+/** SPI_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN5_NUM    0x00000003U
+#define SPI_DIN5_NUM_M  (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
+#define SPI_DIN5_NUM_V  0x00000003U
+#define SPI_DIN5_NUM_S  10
+/** SPI_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN6_NUM    0x00000003U
+#define SPI_DIN6_NUM_M  (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
+#define SPI_DIN6_NUM_V  0x00000003U
+#define SPI_DIN6_NUM_S  12
+/** SPI_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN7_NUM    0x00000003U
+#define SPI_DIN7_NUM_M  (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
+#define SPI_DIN7_NUM_V  0x00000003U
+#define SPI_DIN7_NUM_S  14
+
+/** SPI_DOUT_MODE_REG register
+ *  SPI output delay mode configuration
+ */
+#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c)
+/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT0_MODE    (BIT(0))
+#define SPI_DOUT0_MODE_M  (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
+#define SPI_DOUT0_MODE_V  0x00000001U
+#define SPI_DOUT0_MODE_S  0
+/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT1_MODE    (BIT(1))
+#define SPI_DOUT1_MODE_M  (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
+#define SPI_DOUT1_MODE_V  0x00000001U
+#define SPI_DOUT1_MODE_S  1
+/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT2_MODE    (BIT(2))
+#define SPI_DOUT2_MODE_M  (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
+#define SPI_DOUT2_MODE_V  0x00000001U
+#define SPI_DOUT2_MODE_S  2
+/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT3_MODE    (BIT(3))
+#define SPI_DOUT3_MODE_M  (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
+#define SPI_DOUT3_MODE_V  0x00000001U
+#define SPI_DOUT3_MODE_S  3
+/** SPI_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DOUT4_MODE    (BIT(4))
+#define SPI_DOUT4_MODE_M  (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
+#define SPI_DOUT4_MODE_V  0x00000001U
+#define SPI_DOUT4_MODE_S  4
+/** SPI_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DOUT5_MODE    (BIT(5))
+#define SPI_DOUT5_MODE_M  (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
+#define SPI_DOUT5_MODE_V  0x00000001U
+#define SPI_DOUT5_MODE_S  5
+/** SPI_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DOUT6_MODE    (BIT(6))
+#define SPI_DOUT6_MODE_M  (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
+#define SPI_DOUT6_MODE_V  0x00000001U
+#define SPI_DOUT6_MODE_S  6
+/** SPI_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DOUT7_MODE    (BIT(7))
+#define SPI_DOUT7_MODE_M  (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
+#define SPI_DOUT7_MODE_V  0x00000001U
+#define SPI_DOUT7_MODE_S  7
+/** SPI_D_DQS_MODE : R/W; bitpos: [8]; default: 0;
+ *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+ *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_D_DQS_MODE    (BIT(8))
+#define SPI_D_DQS_MODE_M  (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
+#define SPI_D_DQS_MODE_V  0x00000001U
+#define SPI_D_DQS_MODE_S  8
+
+/** SPI_DMA_CONF_REG register
+ *  SPI DMA control register
+ */
+#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
+/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
+ *  DMA TX FIFO is ready for sending data.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_M  (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
+#define SPI_DMA_OUTFIFO_EMPTY_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_S  0
+/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1;
+ *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
+ *  0: DMA RX FIFO is ready for receiving data.
+ */
+#define SPI_DMA_INFIFO_FULL    (BIT(1))
+#define SPI_DMA_INFIFO_FULL_M  (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
+#define SPI_DMA_INFIFO_FULL_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_S  1
+/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
+ *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+ */
+#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_M  (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
+#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x00000001U
+#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
+ *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+ *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
+ */
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x00000001U
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
+/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
+ *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+ *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+ */
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x00000001U
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
+/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
+ *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
+ *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
+ *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+ *  spi_dma_seg_trans_done in seg-trans.
+ */
+#define SPI_RX_EOF_EN    (BIT(21))
+#define SPI_RX_EOF_EN_M  (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S)
+#define SPI_RX_EOF_EN_V  0x00000001U
+#define SPI_RX_EOF_EN_S  21
+/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to enable SPI DMA controlled receive data mode.
+ */
+#define SPI_DMA_RX_ENA    (BIT(27))
+#define SPI_DMA_RX_ENA_M  (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
+#define SPI_DMA_RX_ENA_V  0x00000001U
+#define SPI_DMA_RX_ENA_S  27
+/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to enable SPI DMA controlled send data mode.
+ */
+#define SPI_DMA_TX_ENA    (BIT(28))
+#define SPI_DMA_TX_ENA_M  (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
+#define SPI_DMA_TX_ENA_V  0x00000001U
+#define SPI_DMA_TX_ENA_S  28
+/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
+ *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+ *  slave mode transfer.
+ */
+#define SPI_RX_AFIFO_RST    (BIT(29))
+#define SPI_RX_AFIFO_RST_M  (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S)
+#define SPI_RX_AFIFO_RST_V  0x00000001U
+#define SPI_RX_AFIFO_RST_S  29
+/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
+ *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+ *  controlled mode transfer and master mode transfer.
+ */
+#define SPI_BUF_AFIFO_RST    (BIT(30))
+#define SPI_BUF_AFIFO_RST_M  (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S)
+#define SPI_BUF_AFIFO_RST_V  0x00000001U
+#define SPI_BUF_AFIFO_RST_S  30
+/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
+ *  controlled mode transfer.
+ */
+#define SPI_DMA_AFIFO_RST    (BIT(31))
+#define SPI_DMA_AFIFO_RST_M  (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S)
+#define SPI_DMA_AFIFO_RST_V  0x00000001U
+#define SPI_DMA_AFIFO_RST_S  31
+
+/** SPI_DMA_INT_ENA_REG register
+ *  SPI interrupt enable register
+ */
+#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
+/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_M  (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S)
+#define SPI_SLV_EX_QPI_INT_ENA_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_ENA_S  2
+/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_M  (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S)
+#define SPI_SLV_EN_QPI_INT_ENA_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_ENA_S  3
+/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_M  (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S)
+#define SPI_SLV_CMD7_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD7_INT_ENA_S  4
+/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The enable bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_M  (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S)
+#define SPI_SLV_CMD8_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD8_INT_ENA_S  5
+/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_M  (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S)
+#define SPI_SLV_CMD9_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD9_INT_ENA_S  6
+/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_M  (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S)
+#define SPI_SLV_CMDA_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMDA_INT_ENA_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S)
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S)
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S)
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S)
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
+/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The enable bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_M  (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S)
+#define SPI_TRANS_DONE_INT_ENA_V  0x00000001U
+#define SPI_TRANS_DONE_INT_ENA_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
+/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+//this field is only for GPSPI2
+#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
+#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_M  (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S)
+#define SPI_SLV_CMD_ERR_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_ENA_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  The enable bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_ENA    (BIT(19))
+#define SPI_APP2_INT_ENA_M  (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S)
+#define SPI_APP2_INT_ENA_V  0x00000001U
+#define SPI_APP2_INT_ENA_S  19
+/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  The enable bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_ENA    (BIT(20))
+#define SPI_APP1_INT_ENA_M  (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S)
+#define SPI_APP1_INT_ENA_V  0x00000001U
+#define SPI_APP1_INT_ENA_S  20
+
+/** SPI_DMA_INT_CLR_REG register
+ *  SPI interrupt clear register
+ */
+#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
+/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_M  (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S)
+#define SPI_SLV_EX_QPI_INT_CLR_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_CLR_S  2
+/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_M  (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S)
+#define SPI_SLV_EN_QPI_INT_CLR_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_CLR_S  3
+/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_M  (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S)
+#define SPI_SLV_CMD7_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD7_INT_CLR_S  4
+/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The clear bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_M  (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S)
+#define SPI_SLV_CMD8_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD8_INT_CLR_S  5
+/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The clear bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_M  (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S)
+#define SPI_SLV_CMD9_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD9_INT_CLR_S  6
+/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The clear bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_M  (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S)
+#define SPI_SLV_CMDA_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMDA_INT_CLR_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S)
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S)
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S)
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S)
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
+/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The clear bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_M  (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S)
+#define SPI_TRANS_DONE_INT_CLR_V  0x00000001U
+#define SPI_TRANS_DONE_INT_CLR_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
+/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+//this field is only for GPSPI2
+#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
+#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_M  (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S)
+#define SPI_SLV_CMD_ERR_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_CLR_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  The clear bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_CLR    (BIT(19))
+#define SPI_APP2_INT_CLR_M  (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S)
+#define SPI_APP2_INT_CLR_V  0x00000001U
+#define SPI_APP2_INT_CLR_S  19
+/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  The clear bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_CLR    (BIT(20))
+#define SPI_APP1_INT_CLR_M  (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S)
+#define SPI_APP1_INT_CLR_V  0x00000001U
+#define SPI_APP1_INT_CLR_S  20
+
+/** SPI_DMA_INT_RAW_REG register
+ *  SPI interrupt raw register
+ */
+#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
+ *  receive data.  0: Others.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+ *  master mode and send out all 0 in slave mode.  0: Others.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
+/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
+ *  is ended. 0: Others.
+ */
+#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_M  (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S)
+#define SPI_SLV_EX_QPI_INT_RAW_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_RAW_S  2
+/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
+ *  is ended. 0: Others.
+ */
+#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_M  (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S)
+#define SPI_SLV_EN_QPI_INT_RAW_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_RAW_S  3
+/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_M  (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S)
+#define SPI_SLV_CMD7_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD7_INT_RAW_S  4
+/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_M  (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S)
+#define SPI_SLV_CMD8_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD8_INT_RAW_S  5
+/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_M  (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S)
+#define SPI_SLV_CMD9_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD9_INT_RAW_S  6
+/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_M  (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S)
+#define SPI_SLV_CMDA_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMDA_INT_RAW_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S)
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S)
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S)
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S)
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
+/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+ *  ended. 0: others.
+ */
+#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_M  (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S)
+#define SPI_TRANS_DONE_INT_RAW_V  0x00000001U
+#define SPI_TRANS_DONE_INT_RAW_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
+ *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+ *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
+ *  is not ended or not occurred.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
+/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
+ *  is error in the DMA seg-conf-trans. 0: others.
+ */
+//this field is only for GPSPI2
+#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
+#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+ *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+ *  bigger than 63. 0: Others.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+ *  current SPI slave HD mode transmission is not supported. 0: Others.
+ */
+#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_M  (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S)
+#define SPI_SLV_CMD_ERR_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_RAW_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+ *  write-full error when SPI inputs data in master mode. 0: Others.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+ *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
+ */
+#define SPI_APP2_INT_RAW    (BIT(19))
+#define SPI_APP2_INT_RAW_M  (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S)
+#define SPI_APP2_INT_RAW_V  0x00000001U
+#define SPI_APP2_INT_RAW_S  19
+/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
+ */
+#define SPI_APP1_INT_RAW    (BIT(20))
+#define SPI_APP1_INT_RAW_M  (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S)
+#define SPI_APP1_INT_RAW_V  0x00000001U
+#define SPI_APP1_INT_RAW_S  20
+
+/** SPI_DMA_INT_ST_REG register
+ *  SPI interrupt status register
+ */
+#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
+/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_M  (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S)
+#define SPI_SLV_EX_QPI_INT_ST_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_ST_S  2
+/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_M  (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S)
+#define SPI_SLV_EN_QPI_INT_ST_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_ST_S  3
+/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_ST    (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_M  (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S)
+#define SPI_SLV_CMD7_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD7_INT_ST_S  4
+/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The status bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_ST    (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_M  (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S)
+#define SPI_SLV_CMD8_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD8_INT_ST_S  5
+/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The status bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_ST    (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_M  (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S)
+#define SPI_SLV_CMD9_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD9_INT_ST_S  6
+/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The status bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_ST    (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_M  (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S)
+#define SPI_SLV_CMDA_INT_ST_V  0x00000001U
+#define SPI_SLV_CMDA_INT_ST_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S)
+#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S)
+#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S)
+#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S)
+#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
+/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The status bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_ST    (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_M  (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S)
+#define SPI_TRANS_DONE_INT_ST_V  0x00000001U
+#define SPI_TRANS_DONE_INT_ST_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
+/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+//this field is only for GPSPI2
+#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_M  (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
+#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_M  (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S)
+#define SPI_SLV_CMD_ERR_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_ST_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The status bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_ST    (BIT(19))
+#define SPI_APP2_INT_ST_M  (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S)
+#define SPI_APP2_INT_ST_V  0x00000001U
+#define SPI_APP2_INT_ST_S  19
+/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The status bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_ST    (BIT(20))
+#define SPI_APP1_INT_ST_M  (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S)
+#define SPI_APP1_INT_ST_V  0x00000001U
+#define SPI_APP1_INT_ST_S  20
+
+/** SPI_DMA_INT_SET_REG register
+ *  SPI interrupt software set register
+ */
+#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
+ *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0;
+ *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
+/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0;
+ *  The software set bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_M  (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S)
+#define SPI_SLV_EX_QPI_INT_SET_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_SET_S  2
+/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0;
+ *  The software set bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_M  (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S)
+#define SPI_SLV_EN_QPI_INT_SET_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_SET_S  3
+/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0;
+ *  The software set bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_SET    (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_M  (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S)
+#define SPI_SLV_CMD7_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD7_INT_SET_S  4
+/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0;
+ *  The software set bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_SET    (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_M  (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S)
+#define SPI_SLV_CMD8_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD8_INT_SET_S  5
+/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0;
+ *  The software set bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_SET    (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_M  (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S)
+#define SPI_SLV_CMD9_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD9_INT_SET_S  6
+/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0;
+ *  The software set bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_SET    (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_M  (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S)
+#define SPI_SLV_CMDA_INT_SET_V  0x00000001U
+#define SPI_SLV_CMDA_INT_SET_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0;
+ *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S)
+#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0;
+ *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S)
+#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
+ *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S)
+#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
+ *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S)
+#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
+/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
+ *  The software set bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_SET    (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_M  (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S)
+#define SPI_TRANS_DONE_INT_SET_V  0x00000001U
+#define SPI_TRANS_DONE_INT_SET_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0;
+ *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
+/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
+ *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+//this field is only for GPSPI2
+#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_M  (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
+#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
+ *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
+/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
+ *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_M  (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S)
+#define SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_SET_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
+ *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
+ *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
+/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
+ *  The software set bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_SET    (BIT(19))
+#define SPI_APP2_INT_SET_M  (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S)
+#define SPI_APP2_INT_SET_V  0x00000001U
+#define SPI_APP2_INT_SET_S  19
+/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
+ *  The software set bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_SET    (BIT(20))
+#define SPI_APP1_INT_SET_M  (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S)
+#define SPI_APP1_INT_SET_V  0x00000001U
+#define SPI_APP1_INT_SET_S  20
+
+/** SPI_W0_REG register
+ *  SPI CPU-controlled buffer0
+ */
+#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
+/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF0    0xFFFFFFFFU
+#define SPI_BUF0_M  (SPI_BUF0_V << SPI_BUF0_S)
+#define SPI_BUF0_V  0xFFFFFFFFU
+#define SPI_BUF0_S  0
+
+/** SPI_W1_REG register
+ *  SPI CPU-controlled buffer1
+ */
+#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c)
+/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF1    0xFFFFFFFFU
+#define SPI_BUF1_M  (SPI_BUF1_V << SPI_BUF1_S)
+#define SPI_BUF1_V  0xFFFFFFFFU
+#define SPI_BUF1_S  0
+
+/** SPI_W2_REG register
+ *  SPI CPU-controlled buffer2
+ */
+#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0)
+/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF2    0xFFFFFFFFU
+#define SPI_BUF2_M  (SPI_BUF2_V << SPI_BUF2_S)
+#define SPI_BUF2_V  0xFFFFFFFFU
+#define SPI_BUF2_S  0
+
+/** SPI_W3_REG register
+ *  SPI CPU-controlled buffer3
+ */
+#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4)
+/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF3    0xFFFFFFFFU
+#define SPI_BUF3_M  (SPI_BUF3_V << SPI_BUF3_S)
+#define SPI_BUF3_V  0xFFFFFFFFU
+#define SPI_BUF3_S  0
+
+/** SPI_W4_REG register
+ *  SPI CPU-controlled buffer4
+ */
+#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8)
+/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF4    0xFFFFFFFFU
+#define SPI_BUF4_M  (SPI_BUF4_V << SPI_BUF4_S)
+#define SPI_BUF4_V  0xFFFFFFFFU
+#define SPI_BUF4_S  0
+
+/** SPI_W5_REG register
+ *  SPI CPU-controlled buffer5
+ */
+#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac)
+/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF5    0xFFFFFFFFU
+#define SPI_BUF5_M  (SPI_BUF5_V << SPI_BUF5_S)
+#define SPI_BUF5_V  0xFFFFFFFFU
+#define SPI_BUF5_S  0
+
+/** SPI_W6_REG register
+ *  SPI CPU-controlled buffer6
+ */
+#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0)
+/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF6    0xFFFFFFFFU
+#define SPI_BUF6_M  (SPI_BUF6_V << SPI_BUF6_S)
+#define SPI_BUF6_V  0xFFFFFFFFU
+#define SPI_BUF6_S  0
+
+/** SPI_W7_REG register
+ *  SPI CPU-controlled buffer7
+ */
+#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4)
+/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF7    0xFFFFFFFFU
+#define SPI_BUF7_M  (SPI_BUF7_V << SPI_BUF7_S)
+#define SPI_BUF7_V  0xFFFFFFFFU
+#define SPI_BUF7_S  0
+
+/** SPI_W8_REG register
+ *  SPI CPU-controlled buffer8
+ */
+#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8)
+/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF8    0xFFFFFFFFU
+#define SPI_BUF8_M  (SPI_BUF8_V << SPI_BUF8_S)
+#define SPI_BUF8_V  0xFFFFFFFFU
+#define SPI_BUF8_S  0
+
+/** SPI_W9_REG register
+ *  SPI CPU-controlled buffer9
+ */
+#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc)
+/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF9    0xFFFFFFFFU
+#define SPI_BUF9_M  (SPI_BUF9_V << SPI_BUF9_S)
+#define SPI_BUF9_V  0xFFFFFFFFU
+#define SPI_BUF9_S  0
+
+/** SPI_W10_REG register
+ *  SPI CPU-controlled buffer10
+ */
+#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0)
+/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF10    0xFFFFFFFFU
+#define SPI_BUF10_M  (SPI_BUF10_V << SPI_BUF10_S)
+#define SPI_BUF10_V  0xFFFFFFFFU
+#define SPI_BUF10_S  0
+
+/** SPI_W11_REG register
+ *  SPI CPU-controlled buffer11
+ */
+#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4)
+/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF11    0xFFFFFFFFU
+#define SPI_BUF11_M  (SPI_BUF11_V << SPI_BUF11_S)
+#define SPI_BUF11_V  0xFFFFFFFFU
+#define SPI_BUF11_S  0
+
+/** SPI_W12_REG register
+ *  SPI CPU-controlled buffer12
+ */
+#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8)
+/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF12    0xFFFFFFFFU
+#define SPI_BUF12_M  (SPI_BUF12_V << SPI_BUF12_S)
+#define SPI_BUF12_V  0xFFFFFFFFU
+#define SPI_BUF12_S  0
+
+/** SPI_W13_REG register
+ *  SPI CPU-controlled buffer13
+ */
+#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc)
+/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF13    0xFFFFFFFFU
+#define SPI_BUF13_M  (SPI_BUF13_V << SPI_BUF13_S)
+#define SPI_BUF13_V  0xFFFFFFFFU
+#define SPI_BUF13_S  0
+
+/** SPI_W14_REG register
+ *  SPI CPU-controlled buffer14
+ */
+#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0)
+/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF14    0xFFFFFFFFU
+#define SPI_BUF14_M  (SPI_BUF14_V << SPI_BUF14_S)
+#define SPI_BUF14_V  0xFFFFFFFFU
+#define SPI_BUF14_S  0
+
+/** SPI_W15_REG register
+ *  SPI CPU-controlled buffer15
+ */
+#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4)
+/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF15    0xFFFFFFFFU
+#define SPI_BUF15_M  (SPI_BUF15_V << SPI_BUF15_S)
+#define SPI_BUF15_V  0xFFFFFFFFU
+#define SPI_BUF15_S  0
+
+/** SPI_SLAVE_REG register
+ *  SPI slave control register
+ */
+#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0)
+/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+ *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+ *  SPI clock is always on. Can be configured in CONF state.
+ */
+#define SPI_CLK_MODE    0x00000003U
+#define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
+#define SPI_CLK_MODE_V  0x00000003U
+#define SPI_CLK_MODE_S  0
+/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
+ *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+ *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+ */
+#define SPI_CLK_MODE_13    (BIT(2))
+#define SPI_CLK_MODE_13_M  (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
+#define SPI_CLK_MODE_13_V  0x00000001U
+#define SPI_CLK_MODE_13_S  2
+/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
+ *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+ *  0: output data at tsck posedge
+ */
+#define SPI_RSCK_DATA_OUT    (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
+#define SPI_RSCK_DATA_OUT_V  0x00000001U
+#define SPI_RSCK_DATA_OUT_S  3
+/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+ *  DMA controlled mode(Rd_DMA). 0: others
+ */
+#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_M  (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S)
+#define SPI_SLV_RDDMA_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_RDDMA_BITLEN_EN_S  8
+/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+ *  in DMA controlled mode(Wr_DMA). 0: others
+ */
+#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_M  (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S)
+#define SPI_SLV_WRDMA_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_WRDMA_BITLEN_EN_S  9
+/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+ *  CPU controlled mode(Rd_BUF). 0: others
+ */
+#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_M  (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S)
+#define SPI_SLV_RDBUF_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_RDBUF_BITLEN_EN_S  10
+/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+ *  in CPU controlled mode(Wr_BUF). 0: others
+ */
+#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_M  (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S)
+#define SPI_SLV_WRBUF_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_WRBUF_BITLEN_EN_S  11
+/** SPI_SLV_LAST_BYTE_STRB : R/SS; bitpos: [19:12]; default: 0;
+ *  Represents the effective bit of the last received data byte in SPI slave FD and HD
+ *  mode.
+ */
+#define SPI_SLV_LAST_BYTE_STRB    0x000000FFU
+#define SPI_SLV_LAST_BYTE_STRB_M  (SPI_SLV_LAST_BYTE_STRB_V << SPI_SLV_LAST_BYTE_STRB_S)
+#define SPI_SLV_LAST_BYTE_STRB_V  0x000000FFU
+#define SPI_SLV_LAST_BYTE_STRB_S  12
+/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
+ *  The magic value of BM table in master DMA seg-trans.
+ */
+//this field is only for GPSPI2
+#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000FU
+#define SPI_DMA_SEG_MAGIC_VALUE_M  (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
+#define SPI_DMA_SEG_MAGIC_VALUE_V  0x0000000FU
+#define SPI_DMA_SEG_MAGIC_VALUE_S  22
+/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
+ *  Set SPI work mode. 1: slave mode 0: master mode.
+ */
+#define SPI_SLAVE_MODE    (BIT(26))
+#define SPI_SLAVE_MODE_M  (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
+#define SPI_SLAVE_MODE_V  0x00000001U
+#define SPI_SLAVE_MODE_S  26
+/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0;
+ *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+ *  configured in CONF state.
+ */
+#define SPI_SOFT_RESET    (BIT(27))
+#define SPI_SOFT_RESET_M  (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
+#define SPI_SOFT_RESET_V  0x00000001U
+#define SPI_SOFT_RESET_S  27
+/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0;
+ *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
+ *  will start. 0: This is not seg-trans mode.
+ */
+//this field is only for GPSPI2
+#define SPI_USR_CONF    (BIT(28))
+#define SPI_USR_CONF_M  (SPI_USR_CONF_V << SPI_USR_CONF_S)
+#define SPI_USR_CONF_V  0x00000001U
+#define SPI_USR_CONF_S  28
+/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0;
+ *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
+ *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
+ *  transfer.
+ */
+#define SPI_MST_FD_WAIT_DMA_TX_DATA    (BIT(29))
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_M  (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S)
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_V  0x00000001U
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_S  29
+
+/** SPI_SLAVE1_REG register
+ *  SPI slave control register 1
+ */
+#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4)
+/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
+ *  The transferred data bit length in SPI slave FD and HD mode.
+ */
+#define SPI_SLV_DATA_BITLEN    0x0003FFFFU
+#define SPI_SLV_DATA_BITLEN_M  (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S)
+#define SPI_SLV_DATA_BITLEN_V  0x0003FFFFU
+#define SPI_SLV_DATA_BITLEN_S  0
+/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
+ *  In the slave mode it is the value of command.
+ */
+#define SPI_SLV_LAST_COMMAND    0x000000FFU
+#define SPI_SLV_LAST_COMMAND_M  (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
+#define SPI_SLV_LAST_COMMAND_V  0x000000FFU
+#define SPI_SLV_LAST_COMMAND_S  18
+/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
+ *  In the slave mode it is the value of address.
+ */
+#define SPI_SLV_LAST_ADDR    0x0000003FU
+#define SPI_SLV_LAST_ADDR_M  (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
+#define SPI_SLV_LAST_ADDR_V  0x0000003FU
+#define SPI_SLV_LAST_ADDR_S  26
+
+/** SPI_CLK_GATE_REG register
+ *  SPI module clock and register clock control
+ */
+#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8)
+/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable clk gate
+ */
+#define SPI_CLK_EN    (BIT(0))
+#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
+#define SPI_CLK_EN_V  0x00000001U
+#define SPI_CLK_EN_S  0
+/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to power on the SPI module clock.
+ */
+#define SPI_MST_CLK_ACTIVE    (BIT(1))
+#define SPI_MST_CLK_ACTIVE_M  (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S)
+#define SPI_MST_CLK_ACTIVE_V  0x00000001U
+#define SPI_MST_CLK_ACTIVE_S  1
+/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
+ *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+ *  0: XTAL CLK.
+ */
+#define SPI_MST_CLK_SEL    (BIT(2))
+#define SPI_MST_CLK_SEL_M  (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S)
+#define SPI_MST_CLK_SEL_V  0x00000001U
+#define SPI_MST_CLK_SEL_S  2
+
+/** SPI_DATE_REG register
+ *  Version control
+ */
+#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0)
+/** SPI_DATE : R/W; bitpos: [27:0]; default: 35680770;
+ *  SPI register version.
+ */
+#define SPI_DATE    0x0FFFFFFFU
+#define SPI_DATE_M  (SPI_DATE_V << SPI_DATE_S)
+#define SPI_DATE_V  0x0FFFFFFFU
+#define SPI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h
new file mode 100644
index 0000000000..64da6d07f3
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h
@@ -0,0 +1,1026 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: User-defined control registers */
+/** Type of cmd register
+ *  Command control register
+ */
+typedef union {
+    struct {
+        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+         */
+        uint32_t conf_bitlen:18;  //this field is only for GPSPI2
+        uint32_t reserved_18:5;
+        /** update : WT; bitpos: [23]; default: 0;
+         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+         *  clock domain, which is only used in SPI master mode.
+         */
+        uint32_t update:1;
+        /** usr : R/W/SC; bitpos: [24]; default: 0;
+         *  User define command enable.  An operation will be triggered when the bit is set.
+         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+         *  changed by CONF_buf.
+         */
+        uint32_t usr:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} spi_cmd_reg_t;
+
+/** Type of addr register
+ *  Address value register
+ */
+typedef union {
+    struct {
+        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
+         *  Address to slave. Can be configured in CONF state.
+         */
+        uint32_t usr_addr_value:32;
+    };
+    uint32_t val;
+} spi_addr_reg_t;
+
+/** Type of user register
+ *  SPI USER control register
+ */
+typedef union {
+    struct {
+        /** doutdin : R/W; bitpos: [0]; default: 0;
+         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t doutdin:1;
+        uint32_t reserved_1:2;
+        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
+         *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t qpi_mode:1;
+        /** opi_mode : R/W; bitpos: [4]; default: 0;
+         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t opi_mode:1;  //this field is only for GPSPI2
+        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+         *  spi_ck_i. 1:tsck = !spi_ck_i.
+         */
+        uint32_t tsck_i_edge:1;
+        /** cs_hold : R/W; bitpos: [6]; default: 1;
+         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cs_hold:1;
+        /** cs_setup : R/W; bitpos: [7]; default: 1;
+         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cs_setup:1;
+        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+         *  !spi_ck_i. 1:rsck = spi_ck_i.
+         */
+        uint32_t rsck_i_edge:1;
+        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+         *  be configured in CONF state.
+         */
+        uint32_t ck_out_edge:1;
+        uint32_t reserved_10:2;
+        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
+         *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_dual:1;
+        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
+         *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_quad:1;
+        /** fwrite_oct : R/W; bitpos: [14]; default: 0;
+         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_oct:1;  //this field is only for GPSPI2
+        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
+         *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+         *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
+         *  not seg-trans mode. Can be configured in CONF state.
+         */
+        uint32_t usr_conf_nxt:1;  //this field is only for GPSPI2
+        uint32_t reserved_16:1;
+        /** sio : R/W; bitpos: [17]; default: 0;
+         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+         */
+        uint32_t sio:1;
+        uint32_t reserved_18:6;
+        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
+         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+         *  disable. Can be configured in CONF state.
+         */
+        uint32_t usr_miso_highpart:1;
+        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
+         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+         *  0: disable.  Can be configured in CONF state.
+         */
+        uint32_t usr_mosi_highpart:1;
+        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+         *  CONF state.
+         */
+        uint32_t usr_dummy_idle:1;
+        /** usr_mosi : R/W; bitpos: [27]; default: 0;
+         *  This bit enable the write-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t usr_mosi:1;
+        /** usr_miso : R/W; bitpos: [28]; default: 0;
+         *  This bit enable the read-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t usr_miso:1;
+        /** usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_dummy:1;
+        /** usr_addr : R/W; bitpos: [30]; default: 0;
+         *  This bit enable the address phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_addr:1;
+        /** usr_command : R/W; bitpos: [31]; default: 1;
+         *  This bit enable the command phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_command:1;
+    };
+    uint32_t val;
+} spi_user_reg_t;
+
+/** Type of user1 register
+ *  SPI USER control register 1
+ */
+typedef union {
+    struct {
+        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
+         *  The length in spi_clk cycles of dummy phase. The register value shall be
+         *  (cycle_num-1). Can be configured in CONF state.
+         */
+        uint32_t usr_dummy_cyclelen:8;
+        uint32_t reserved_8:8;
+        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
+         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+         *  GP-SPI master FD/HD-mode.
+         */
+        uint32_t mst_wfull_err_end_en:1;
+        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
+         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+         *  bit. Can be configured in CONF state.
+         */
+        uint32_t cs_setup_time:5;
+        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
+         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs_hold_time:5;
+        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
+         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t usr_addr_bitlen:5;
+    };
+    uint32_t val;
+} spi_user1_reg_t;
+
+/** Type of user2 register
+ *  SPI USER control register 2
+ */
+typedef union {
+    struct {
+        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  The value of  command. Can be configured in CONF state.
+         */
+        uint32_t usr_command_value:16;
+        uint32_t reserved_16:11;
+        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
+         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+         *  is valid in GP-SPI master FD/HD-mode.
+         */
+        uint32_t mst_rempty_err_end_en:1;
+        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t usr_command_bitlen:4;
+    };
+    uint32_t val;
+} spi_user2_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of ctrl register
+ *  SPI control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** dummy_out : R/W; bitpos: [3]; default: 0;
+         *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
+         *  the FSPI bus signals are output. Can be configured in CONF state.
+         */
+        uint32_t dummy_out:1;
+        uint32_t reserved_4:1;
+        /** faddr_dual : R/W; bitpos: [5]; default: 0;
+         *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_dual:1;
+        /** faddr_quad : R/W; bitpos: [6]; default: 0;
+         *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_quad:1;
+        /** faddr_oct : R/W; bitpos: [7]; default: 0;
+         *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_oct:1;  //this field is only for GPSPI2
+        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
+         *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_dual:1;
+        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
+         *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_quad:1;
+        /** fcmd_oct : R/W; bitpos: [10]; default: 0;
+         *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_oct:1;  //this field is only for GPSPI2
+        uint32_t reserved_11:3;
+        /** fread_dual : R/W; bitpos: [14]; default: 0;
+         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_dual:1;
+        /** fread_quad : R/W; bitpos: [15]; default: 0;
+         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_quad:1;
+        /** fread_oct : R/W; bitpos: [16]; default: 0;
+         *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_oct:1;  //this field is only for GPSPI2
+        uint32_t reserved_17:1;
+        /** q_pol : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t q_pol:1;
+        /** d_pol : R/W; bitpos: [19]; default: 1;
+         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t d_pol:1;
+        /** hold_pol : R/W; bitpos: [20]; default: 1;
+         *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+         *  configured in CONF state.
+         */
+        uint32_t hold_pol:1;
+        /** wp_pol : R/W; bitpos: [21]; default: 1;
+         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t wp_pol:1;
+        uint32_t reserved_22:1;
+        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
+         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+         *  state.
+         */
+        uint32_t rd_bit_order:2;
+        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
+         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+         *  configured in CONF state.
+         */
+        uint32_t wr_bit_order:2;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_ctrl_reg_t;
+
+/** Type of ms_dlen register
+ *  SPI data bit length control register
+ */
+typedef union {
+    struct {
+        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  The value of these bits is the configured SPI transmission data bit length in
+         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+         *  the configured bit length in slave mode DMA RX controlled transfer. The register
+         *  value shall be (bit_num-1). Can be configured in CONF state.
+         */
+        uint32_t ms_data_bitlen:18;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_ms_dlen_reg_t;
+
+/** Type of misc register
+ *  SPI misc register
+ */
+typedef union {
+    struct {
+        /** cs0_dis : R/W; bitpos: [0]; default: 0;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs0_dis:1;
+        /** cs1_dis : R/W; bitpos: [1]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs1_dis:1;
+        /** cs2_dis : R/W; bitpos: [2]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs2_dis:1;
+        /** cs3_dis : R/W; bitpos: [3]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs3_dis:1;  //this field is only for GPSPI2
+        /** cs4_dis : R/W; bitpos: [4]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs4_dis:1;  //this field is only for GPSPI2
+        /** cs5_dis : R/W; bitpos: [5]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs5_dis:1;  //this field is only for GPSPI2
+        /** ck_dis : R/W; bitpos: [6]; default: 0;
+         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+         */
+        uint32_t ck_dis:1;
+        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
+         *  In the master mode the bits are the polarity of spi cs line, the value is
+         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+         */
+        uint32_t master_cs_pol:6;  //This field for GPSPI3 is only 3-bit-width
+        uint32_t reserved_13:3;
+        /** clk_data_dtr_en : R/W; bitpos: [16]; default: 0;
+         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+         */
+        uint32_t clk_data_dtr_en:1;  //this field is only for GPSPI2
+        /** data_dtr_en : R/W; bitpos: [17]; default: 0;
+         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+         *  Can be configured in CONF state.
+         */
+        uint32_t data_dtr_en:1;  //this field is only for GPSPI2
+        /** addr_dtr_en : R/W; bitpos: [18]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t addr_dtr_en:1;  //this field is only for GPSPI2
+        /** cmd_dtr_en : R/W; bitpos: [19]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cmd_dtr_en:1;  //this field is only for GPSPI2
+        uint32_t reserved_20:3;
+        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
+         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+         *  CONF state.
+         */
+        uint32_t slave_cs_pol:1;
+        /** dqs_idle_edge : R/W; bitpos: [24]; default: 0;
+         *  The default value of spi_dqs. Can be configured in CONF state.
+         */
+        uint32_t dqs_idle_edge:1;  //this field is only for GPSPI2
+        uint32_t reserved_25:4;
+        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
+         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+         *  configured in CONF state.
+         */
+        uint32_t ck_idle_edge:1;
+        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
+         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+         */
+        uint32_t cs_keep_active:1;
+        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
+         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+         *  spi quad input swap disable. Can be configured in CONF state.
+         */
+        uint32_t quad_din_pin_swap:1;
+    };
+    uint32_t val;
+} spi_misc_reg_t;
+
+/** Type of dma_conf register
+ *  SPI DMA control register
+ */
+typedef union {
+    struct {
+        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
+         *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
+         *  DMA TX FIFO is ready for sending data.
+         */
+        uint32_t dma_outfifo_empty:1;
+        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
+         *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
+         *  0: DMA RX FIFO is ready for receiving data.
+         */
+        uint32_t dma_infifo_full:1;
+        uint32_t reserved_2:16;
+        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
+         *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+         */
+        uint32_t dma_slv_seg_trans_en:1;
+        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
+         *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+         *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
+         */
+        uint32_t slv_rx_seg_trans_clr_en:1;
+        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
+         *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+         *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+         */
+        uint32_t slv_tx_seg_trans_clr_en:1;
+        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
+         *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
+         *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
+         *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+         *  spi_dma_seg_trans_done in seg-trans.
+         */
+        uint32_t rx_eof_en:1;
+        uint32_t reserved_22:5;
+        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to enable SPI DMA controlled receive data mode.
+         */
+        uint32_t dma_rx_ena:1;
+        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to enable SPI DMA controlled send data mode.
+         */
+        uint32_t dma_tx_ena:1;
+        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
+         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+         *  slave mode transfer.
+         */
+        uint32_t rx_afifo_rst:1;
+        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
+         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+         *  controlled mode transfer and master mode transfer.
+         */
+        uint32_t buf_afifo_rst:1;
+        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
+         *  controlled mode transfer.
+         */
+        uint32_t dma_afifo_rst:1;
+    };
+    uint32_t val;
+} spi_dma_conf_reg_t;
+
+/** Type of slave register
+ *  SPI slave control register
+ */
+typedef union {
+    struct {
+        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on. Can be configured in CONF state.
+         */
+        uint32_t clk_mode:2;
+        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
+         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+         */
+        uint32_t clk_mode_13:1;
+        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
+         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+         *  0: output data at tsck posedge
+         */
+        uint32_t rsck_data_out:1;
+        uint32_t reserved_4:4;
+        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  DMA controlled mode(Rd_DMA). 0: others
+         */
+        uint32_t slv_rddma_bitlen_en:1;
+        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in DMA controlled mode(Wr_DMA). 0: others
+         */
+        uint32_t slv_wrdma_bitlen_en:1;
+        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  CPU controlled mode(Rd_BUF). 0: others
+         */
+        uint32_t slv_rdbuf_bitlen_en:1;
+        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in CPU controlled mode(Wr_BUF). 0: others
+         */
+        uint32_t slv_wrbuf_bitlen_en:1;
+        /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0;
+         *  Represents the effective bit of the last received data byte in SPI slave FD and HD
+         *  mode.
+         */
+        uint32_t slv_last_byte_strb:8;
+        uint32_t reserved_20:2;
+        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
+         *  The magic value of BM table in master DMA seg-trans.
+         */
+        uint32_t dma_seg_magic_value:4;  //this field is only for GPSPI2
+        /** slave_mode : R/W; bitpos: [26]; default: 0;
+         *  Set SPI work mode. 1: slave mode 0: master mode.
+         */
+        uint32_t slave_mode:1;
+        /** soft_reset : WT; bitpos: [27]; default: 0;
+         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+         *  configured in CONF state.
+         */
+        uint32_t soft_reset:1;
+        /** usr_conf : R/W; bitpos: [28]; default: 0;
+         *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
+         *  will start. 0: This is not seg-trans mode.
+         */
+        uint32_t usr_conf:1;  //this field is only for GPSPI2
+        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
+         *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
+         *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
+         *  transfer.
+         */
+        uint32_t mst_fd_wait_dma_tx_data:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_slave_reg_t;
+
+/** Type of slave1 register
+ *  SPI slave control register 1
+ */
+typedef union {
+    struct {
+        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
+         *  The transferred data bit length in SPI slave FD and HD mode.
+         */
+        uint32_t slv_data_bitlen:18;
+        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
+         *  In the slave mode it is the value of command.
+         */
+        uint32_t slv_last_command:8;
+        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
+         *  In the slave mode it is the value of address.
+         */
+        uint32_t slv_last_addr:6;
+    };
+    uint32_t val;
+} spi_slave1_reg_t;
+
+
+/** Group: Clock control registers */
+/** Type of clock register
+ *  SPI clock control register
+ */
+typedef union {
+    struct {
+        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
+         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+         *  0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_l:6;
+        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
+         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+         *  must be 0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_h:6;
+        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
+         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+         */
+        uint32_t clkcnt_n:6;
+        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
+         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+         */
+        uint32_t clkdiv_pre:4;
+        uint32_t reserved_22:9;
+        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
+         *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+         *  clock. Can be configured in CONF state.
+         */
+        uint32_t clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi_clock_reg_t;
+
+/** Type of clk_gate register
+ *  SPI module clock and register clock control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en:1;
+        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to power on the SPI module clock.
+         */
+        uint32_t mst_clk_active:1;
+        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
+         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+         *  0: XTAL CLK.
+         */
+        uint32_t mst_clk_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} spi_clk_gate_reg_t;
+
+
+/** Group: Timing registers */
+/** Type of din_mode register
+ *  SPI input delay mode configuration
+ */
+typedef union {
+    struct {
+        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din0_mode:2;
+        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din1_mode:2;
+        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din2_mode:2;
+        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din3_mode:2;
+        /** din4_mode : R/W; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din4_mode:2;  //this field is only for GPSPI2
+        /** din5_mode : R/W; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din5_mode:2;  //this field is only for GPSPI2
+        /** din6_mode : R/W; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din6_mode:2;  //this field is only for GPSPI2
+        /** din7_mode : R/W; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din7_mode:2;  //this field is only for GPSPI2
+        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
+         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+         *  state.
+         */
+        uint32_t timing_hclk_active:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} spi_din_mode_reg_t;
+
+/** Type of din_num register
+ *  SPI input delay number configuration
+ */
+typedef union {
+    struct {
+        /** din0_num : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din0_num:2;
+        /** din1_num : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din1_num:2;
+        /** din2_num : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din2_num:2;
+        /** din3_num : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din3_num:2;
+        /** din4_num : R/W; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din4_num:2;  //this field is only for GPSPI2
+        /** din5_num : R/W; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din5_num:2;  //this field is only for GPSPI2
+        /** din6_num : R/W; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din6_num:2;  //this field is only for GPSPI2
+        /** din7_num : R/W; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din7_num:2;  //this field is only for GPSPI2
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} spi_din_num_reg_t;
+
+/** Type of dout_mode register
+ *  SPI output delay mode configuration
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [0]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout0_mode:1;
+        /** dout1_mode : R/W; bitpos: [1]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout1_mode:1;
+        /** dout2_mode : R/W; bitpos: [2]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout2_mode:1;
+        /** dout3_mode : R/W; bitpos: [3]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout3_mode:1;
+        /** dout4_mode : R/W; bitpos: [4]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout4_mode:1;  //this field is only for GPSPI2
+        /** dout5_mode : R/W; bitpos: [5]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout5_mode:1;  //this field is only for GPSPI2
+        /** dout6_mode : R/W; bitpos: [6]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout6_mode:1;  //this field is only for GPSPI2
+        /** dout7_mode : R/W; bitpos: [7]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout7_mode:1;  //this field is only for GPSPI2
+        /** d_dqs_mode : R/W; bitpos: [8]; default: 0;
+         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t d_dqs_mode:1;  //this field is only for GPSPI2
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_dout_mode_reg_t;
+
+/** Type of dma_int register
+ *  SPI interrupt raw/ena/clr/sta/set register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
+         *  receive data.  0: Others.
+         */
+        uint32_t dma_infifo_full_err_int:1;
+        /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+         *  master mode and send out all 0 in slave mode.  0: Others.
+         */
+        uint32_t dma_outfifo_empty_err_int:1;
+        /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
+         *  is ended. 0: Others.
+         */
+        uint32_t slv_ex_qpi_int:1;
+        /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
+         *  is ended. 0: Others.
+         */
+        uint32_t slv_en_qpi_int:1;
+        /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd7_int:1;
+        /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd8_int:1;
+        /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd9_int:1;
+        /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmda_int:1;
+        /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_rd_dma_done_int:1;
+        /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_wr_dma_done_int:1;
+        /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_rd_buf_done_int:1;
+        /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_wr_buf_done_int:1;
+        /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+         *  ended. 0: others.
+         */
+        uint32_t trans_done_int:1;
+        /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
+         *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+         *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
+         *  is not ended or not occurred.
+         */
+        uint32_t dma_seg_trans_done_int:1;
+        /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
+         *  is error in the DMA seg-conf-trans. 0: others.
+         */
+        uint32_t seg_magic_err_int_raw:1;  //this field is only forPI2
+        /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+         *  bigger than 63. 0: Others.
+         */
+        uint32_t slv_buf_addr_err_int:1;
+        /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+         *  current SPI slave HD mode transmission is not supported. 0: Others.
+         */
+        uint32_t slv_cmd_err_int:1;
+        /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+         *  write-full error when SPI inputs data in master mode. 0: Others.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int:1;
+        /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int:1;
+        /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
+         */
+        uint32_t app2_int:1;
+        /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
+         */
+        uint32_t app1_int:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_reg_t;
+
+/** Type of wn register
+ *  SPI CPU-controlled buffer
+ */
+typedef union {
+    struct {
+        /** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf:32;
+    };
+    uint32_t val;
+} spi_wn_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35680770;
+         *  SPI register version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi_date_reg_t;
+
+
+typedef struct {
+    volatile spi_cmd_reg_t cmd;
+    volatile spi_addr_reg_t addr;
+    volatile spi_ctrl_reg_t ctrl;
+    volatile spi_clock_reg_t clock;
+    volatile spi_user_reg_t user;
+    volatile spi_user1_reg_t user1;
+    volatile spi_user2_reg_t user2;
+    volatile spi_ms_dlen_reg_t ms_dlen;
+    volatile spi_misc_reg_t misc;
+    volatile spi_din_mode_reg_t din_mode;
+    volatile spi_din_num_reg_t din_num;
+    volatile spi_dout_mode_reg_t dout_mode;
+    volatile spi_dma_conf_reg_t dma_conf;
+    volatile spi_dma_int_reg_t dma_int_ena;
+    volatile spi_dma_int_reg_t dma_int_clr;
+    volatile spi_dma_int_reg_t dma_int_raw;
+    volatile spi_dma_int_reg_t dma_int_sta;
+    volatile spi_dma_int_reg_t dma_int_set;
+    uint32_t reserved_048[20];
+    volatile spi_wn_reg_t data_buf[16];
+    uint32_t reserved_0d8[2];
+    volatile spi_slave_reg_t slave;
+    volatile spi_slave1_reg_t slave1;
+    volatile spi_clk_gate_reg_t clk_gate;
+    uint32_t reserved_0ec;
+    volatile spi_date_reg_t date;
+} spi_dev_t;
+
+extern spi_dev_t GPSPI2;
+extern spi_dev_t GPSPI3;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/systimer_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/systimer_reg.h
new file mode 100644
index 0000000000..5a8fd9e16d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/systimer_reg.h
@@ -0,0 +1,630 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SYSTIMER_CONF_REG register
+ *  Configure system timer clock
+ */
+#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
+/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
+ *  enable systimer's etm task and event
+ */
+#define SYSTIMER_ETM_EN    (BIT(1))
+#define SYSTIMER_ETM_EN_M  (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
+#define SYSTIMER_ETM_EN_V  0x00000001U
+#define SYSTIMER_ETM_EN_S  1
+/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
+ *  target2 work enable
+ */
+#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
+#define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
+#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001U
+#define SYSTIMER_TARGET2_WORK_EN_S  22
+/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
+ *  target1 work enable
+ */
+#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
+#define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
+#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001U
+#define SYSTIMER_TARGET1_WORK_EN_S  23
+/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
+ *  target0 work enable
+ */
+#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
+#define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
+#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001U
+#define SYSTIMER_TARGET0_WORK_EN_S  24
+/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
+ *  If timer unit1 is stalled when core1 stalled
+ */
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
+/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
+ *  If timer unit1 is stalled when core0 stalled
+ */
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
+/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
+ *  If timer unit0 is stalled when core1 stalled
+ */
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
+/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
+ *  If timer unit0 is stalled when core0 stalled
+ */
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
+/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
+ *  timer unit1 work enable
+ */
+#define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
+/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
+ *  timer unit0 work enable
+ */
+#define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
+/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  register file clk gating
+ */
+#define SYSTIMER_CLK_EN    (BIT(31))
+#define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
+#define SYSTIMER_CLK_EN_V  0x00000001U
+#define SYSTIMER_CLK_EN_S  31
+
+/** SYSTIMER_UNIT0_OP_REG register
+ *  system timer unit0 value update register
+ */
+#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
+/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ *  timer value is sync and valid
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
+/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
+ *  update timer_unit0
+ */
+#define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
+
+/** SYSTIMER_UNIT1_OP_REG register
+ *  system timer unit1 value update register
+ */
+#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
+/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ *  timer value is sync and valid
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
+/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
+ *  update timer unit1
+ */
+#define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
+
+/** SYSTIMER_UNIT0_LOAD_HI_REG register
+ *  system timer unit0 value high load register
+ */
+#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
+/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer unit0 load high 20 bits
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
+
+/** SYSTIMER_UNIT0_LOAD_LO_REG register
+ *  system timer unit0 value low load register
+ */
+#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
+/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer unit0 load low 32 bits
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
+
+/** SYSTIMER_UNIT1_LOAD_HI_REG register
+ *  system timer unit1 value high load register
+ */
+#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
+/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer unit1 load high 20 bits
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
+
+/** SYSTIMER_UNIT1_LOAD_LO_REG register
+ *  system timer unit1 value low load register
+ */
+#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
+/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer unit1 load low 32 bits
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
+
+/** SYSTIMER_TARGET0_HI_REG register
+ *  system timer comp0 value high register
+ */
+#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
+/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget0 high 20 bits
+ */
+#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
+#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET0_HI_S  0
+
+/** SYSTIMER_TARGET0_LO_REG register
+ *  system timer comp0 value low register
+ */
+#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
+/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget0 low 32 bits
+ */
+#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
+#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET0_LO_S  0
+
+/** SYSTIMER_TARGET1_HI_REG register
+ *  system timer comp1 value high register
+ */
+#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
+/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget1 high 20 bits
+ */
+#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
+#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET1_HI_S  0
+
+/** SYSTIMER_TARGET1_LO_REG register
+ *  system timer comp1 value low register
+ */
+#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
+/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget1 low 32 bits
+ */
+#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
+#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET1_LO_S  0
+
+/** SYSTIMER_TARGET2_HI_REG register
+ *  system timer comp2 value high register
+ */
+#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
+/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget2 high 20 bits
+ */
+#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
+#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET2_HI_S  0
+
+/** SYSTIMER_TARGET2_LO_REG register
+ *  system timer comp2 value low register
+ */
+#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
+/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget2 low 32 bits
+ */
+#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
+#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET2_LO_S  0
+
+/** SYSTIMER_TARGET0_CONF_REG register
+ *  system timer comp0 target mode register
+ */
+#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
+/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target0 period
+ */
+#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFFU
+#define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
+#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFFU
+#define SYSTIMER_TARGET0_PERIOD_S  0
+/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target0 to period mode
+ */
+#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
+#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001U
+#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001U
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_TARGET1_CONF_REG register
+ *  system timer comp1 target mode register
+ */
+#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
+/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target1 period
+ */
+#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFFU
+#define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
+#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFFU
+#define SYSTIMER_TARGET1_PERIOD_S  0
+/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target1 to period mode
+ */
+#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
+#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001U
+#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001U
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_TARGET2_CONF_REG register
+ *  system timer comp2 target mode register
+ */
+#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
+/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target2 period
+ */
+#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFFU
+#define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
+#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFFU
+#define SYSTIMER_TARGET2_PERIOD_S  0
+/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target2 to period mode
+ */
+#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
+#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001U
+#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001U
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_UNIT0_VALUE_HI_REG register
+ *  system timer unit0 value high register
+ */
+#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
+/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ *  timer read value high 20bits
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
+
+/** SYSTIMER_UNIT0_VALUE_LO_REG register
+ *  system timer unit0 value low register
+ */
+#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
+/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ *  timer read value low 32bits
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
+
+/** SYSTIMER_UNIT1_VALUE_HI_REG register
+ *  system timer unit1 value high register
+ */
+#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
+/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ *  timer read value high 20bits
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
+
+/** SYSTIMER_UNIT1_VALUE_LO_REG register
+ *  system timer unit1 value low register
+ */
+#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
+/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ *  timer read value low 32bits
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
+
+/** SYSTIMER_COMP0_LOAD_REG register
+ *  system timer comp0 conf sync register
+ */
+#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
+/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp0 sync enable signal
+ */
+#define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
+#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001U
+#define SYSTIMER_TIMER_COMP0_LOAD_S  0
+
+/** SYSTIMER_COMP1_LOAD_REG register
+ *  system timer comp1 conf sync register
+ */
+#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
+/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp1 sync enable signal
+ */
+#define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
+#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001U
+#define SYSTIMER_TIMER_COMP1_LOAD_S  0
+
+/** SYSTIMER_COMP2_LOAD_REG register
+ *  system timer comp2 conf sync register
+ */
+#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
+/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp2 sync enable signal
+ */
+#define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
+#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001U
+#define SYSTIMER_TIMER_COMP2_LOAD_S  0
+
+/** SYSTIMER_UNIT0_LOAD_REG register
+ *  system timer unit0 conf sync register
+ */
+#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
+/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer unit0 sync enable signal
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_LOAD_S  0
+
+/** SYSTIMER_UNIT1_LOAD_REG register
+ *  system timer unit1 conf sync register
+ */
+#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
+/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer unit1 sync enable signal
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_LOAD_S  0
+
+/** SYSTIMER_INT_ENA_REG register
+ *  systimer interrupt enable register
+ */
+#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
+/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  interupt0 enable
+ */
+#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
+#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001U
+#define SYSTIMER_TARGET0_INT_ENA_S  0
+/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  interupt1 enable
+ */
+#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
+#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001U
+#define SYSTIMER_TARGET1_INT_ENA_S  1
+/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  interupt2 enable
+ */
+#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
+#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001U
+#define SYSTIMER_TARGET2_INT_ENA_S  2
+
+/** SYSTIMER_INT_RAW_REG register
+ *  systimer interrupt raw register
+ */
+#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
+/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  interupt0 raw
+ */
+#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
+#define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
+#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001U
+#define SYSTIMER_TARGET0_INT_RAW_S  0
+/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  interupt1 raw
+ */
+#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
+#define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
+#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001U
+#define SYSTIMER_TARGET1_INT_RAW_S  1
+/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  interupt2 raw
+ */
+#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
+#define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
+#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001U
+#define SYSTIMER_TARGET2_INT_RAW_S  2
+
+/** SYSTIMER_INT_CLR_REG register
+ *  systimer interrupt clear register
+ */
+#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
+/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  interupt0 clear
+ */
+#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
+#define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
+#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001U
+#define SYSTIMER_TARGET0_INT_CLR_S  0
+/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  interupt1 clear
+ */
+#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
+#define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
+#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001U
+#define SYSTIMER_TARGET1_INT_CLR_S  1
+/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  interupt2 clear
+ */
+#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
+#define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
+#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001U
+#define SYSTIMER_TARGET2_INT_CLR_S  2
+
+/** SYSTIMER_INT_ST_REG register
+ *  systimer interrupt status register
+ */
+#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
+/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  interupt0 status
+ */
+#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
+#define SYSTIMER_TARGET0_INT_ST_V  0x00000001U
+#define SYSTIMER_TARGET0_INT_ST_S  0
+/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  interupt1 status
+ */
+#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
+#define SYSTIMER_TARGET1_INT_ST_V  0x00000001U
+#define SYSTIMER_TARGET1_INT_ST_S  1
+/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  interupt2 status
+ */
+#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
+#define SYSTIMER_TARGET2_INT_ST_V  0x00000001U
+#define SYSTIMER_TARGET2_INT_ST_S  2
+
+/** SYSTIMER_REAL_TARGET0_LO_REG register
+ *  system timer comp0 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
+/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET0_LO_RO    0xFFFFFFFFU
+#define SYSTIMER_TARGET0_LO_RO_M  (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
+#define SYSTIMER_TARGET0_LO_RO_V  0xFFFFFFFFU
+#define SYSTIMER_TARGET0_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET0_HI_REG register
+ *  system timer comp0 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
+/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET0_HI_RO    0x000FFFFFU
+#define SYSTIMER_TARGET0_HI_RO_M  (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
+#define SYSTIMER_TARGET0_HI_RO_V  0x000FFFFFU
+#define SYSTIMER_TARGET0_HI_RO_S  0
+
+/** SYSTIMER_REAL_TARGET1_LO_REG register
+ *  system timer comp1 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
+/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET1_LO_RO    0xFFFFFFFFU
+#define SYSTIMER_TARGET1_LO_RO_M  (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
+#define SYSTIMER_TARGET1_LO_RO_V  0xFFFFFFFFU
+#define SYSTIMER_TARGET1_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET1_HI_REG register
+ *  system timer comp1 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
+/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET1_HI_RO    0x000FFFFFU
+#define SYSTIMER_TARGET1_HI_RO_M  (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
+#define SYSTIMER_TARGET1_HI_RO_V  0x000FFFFFU
+#define SYSTIMER_TARGET1_HI_RO_S  0
+
+/** SYSTIMER_REAL_TARGET2_LO_REG register
+ *  system timer comp2 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
+/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET2_LO_RO    0xFFFFFFFFU
+#define SYSTIMER_TARGET2_LO_RO_M  (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
+#define SYSTIMER_TARGET2_LO_RO_V  0xFFFFFFFFU
+#define SYSTIMER_TARGET2_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET2_HI_REG register
+ *  system timer comp2 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
+/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET2_HI_RO    0x000FFFFFU
+#define SYSTIMER_TARGET2_HI_RO_M  (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
+#define SYSTIMER_TARGET2_HI_RO_V  0x000FFFFFU
+#define SYSTIMER_TARGET2_HI_RO_S  0
+
+/** SYSTIMER_DATE_REG register
+ *  system timer version control register
+ */
+#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
+/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795;
+ *  systimer register version
+ */
+#define SYSTIMER_DATE    0xFFFFFFFFU
+#define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
+#define SYSTIMER_DATE_V  0xFFFFFFFFU
+#define SYSTIMER_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/systimer_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/systimer_struct.h
new file mode 100644
index 0000000000..8716983ec9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/systimer_struct.h
@@ -0,0 +1,376 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
+/** Type of conf register
+ *  Configure system timer clock
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** etm_en : R/W; bitpos: [1]; default: 0;
+         *  enable systimer's etm task and event
+         */
+        uint32_t etm_en:1;
+        uint32_t reserved_2:20;
+        /** target2_work_en : R/W; bitpos: [22]; default: 0;
+         *  target2 work enable
+         */
+        uint32_t target2_work_en:1;
+        /** target1_work_en : R/W; bitpos: [23]; default: 0;
+         *  target1 work enable
+         */
+        uint32_t target1_work_en:1;
+        /** target0_work_en : R/W; bitpos: [24]; default: 0;
+         *  target0 work enable
+         */
+        uint32_t target0_work_en:1;
+        /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
+         *  If timer unit1 is stalled when core1 stalled
+         */
+        uint32_t timer_unit1_core1_stall_en:1;
+        /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
+         *  If timer unit1 is stalled when core0 stalled
+         */
+        uint32_t timer_unit1_core0_stall_en:1;
+        /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
+         *  If timer unit0 is stalled when core1 stalled
+         */
+        uint32_t timer_unit0_core1_stall_en:1;
+        /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
+         *  If timer unit0 is stalled when core0 stalled
+         */
+        uint32_t timer_unit0_core0_stall_en:1;
+        /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
+         *  timer unit1 work enable
+         */
+        uint32_t timer_unit1_work_en:1;
+        /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
+         *  timer unit0 work enable
+         */
+        uint32_t timer_unit0_work_en:1;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  register file clk gating
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} systimer_conf_reg_t;
+
+
+/** Group: SYSTEM TIMER UNIT CONTROL AND CONFIGURATION REGISTER */
+/** Type of unit_op register
+ *  system timer unit value update register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 29;
+        /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
+         *  timer value is sync and valid
+         */
+        uint32_t timer_unit_value_valid: 1;
+        /** timer_unit_update : WT; bitpos: [30]; default: 0;
+         *  update timer_unit
+         */
+        uint32_t timer_unit_update: 1;
+        uint32_t reserved31: 1;
+    };
+    uint32_t val;
+} systimer_unit_op_reg_t;
+
+/** Type of unit_load register
+ *  system timer unit value high and low load register
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer unit load high 20 bit
+             */
+            uint32_t timer_unit_load_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer unit load low 32 bit
+             */
+            uint32_t timer_unit_load_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_load_val_reg_t;
+
+/** Type of unit_value_hi register
+ *  system timer unit value high and low register
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
+             *  timer read value high 20 bit
+             */
+            uint32_t timer_unit_value_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
+             *  timer read value low 32 bit
+             */
+            uint32_t timer_unit_value_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_value_reg_t;
+
+/** Type of unit_load register
+ *  system timer unit conf sync register
+ */
+typedef union {
+    struct {
+        /** timer_unit_load : WT; bitpos: [0]; default: 0;
+         *  timer unit load value
+         */
+        uint32_t timer_unit_load: 1;
+        uint32_t reserved1: 31;
+    };
+    uint32_t val;
+} systimer_unit_load_reg_t;
+
+
+/** Group: SYSTEM TIMER COMP CONTROL AND CONFIGURATION REGISTER */
+/** Type of target register
+ *  system timer comp value high and low register
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer target high 20 bit
+             */
+            uint32_t timer_target_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer target low 32 bit
+             */
+            uint32_t timer_target_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_target_val_reg_t;
+
+/** Type of target_conf register
+ *  system timer comp target mode register
+ */
+typedef union {
+    struct {
+        /** target_period : R/W; bitpos: [25:0]; default: 0;
+         *  target period
+         */
+        uint32_t target_period: 26;
+        uint32_t reserved_26: 4;
+        /** target_period_mode : R/W; bitpos: [30]; default: 0;
+         *  Set target to period mode
+         */
+        uint32_t target_period_mode: 1;
+        /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
+         *  select which unit to compare
+         */
+        uint32_t target_timer_unit_sel: 1;
+    };
+    uint32_t val;
+} systimer_target_conf_reg_t;
+
+/** Type of comp_load register
+ *  system timer comp conf sync register
+ */
+typedef union {
+    struct {
+        /** timer_comp_load : WT; bitpos: [0]; default: 0;
+         *  timer comp sync enable signal
+         */
+        uint32_t timer_comp_load: 1;
+        uint32_t reserved1: 31;
+    };
+    uint32_t val;
+} systimer_comp_load_reg_t;
+
+
+/** Group: SYSTEM TIMER INTERRUPT REGISTER */
+/** Type of int_ena register
+ *  systimer interrupt enable register
+ */
+typedef union {
+    struct {
+        /** target0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  interupt0 enable
+         */
+        uint32_t target0_int_ena:1;
+        /** target1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  interupt1 enable
+         */
+        uint32_t target1_int_ena:1;
+        /** target2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  interupt2 enable
+         */
+        uint32_t target2_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  systimer interrupt raw register
+ */
+typedef union {
+    struct {
+        /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  interupt0 raw
+         */
+        uint32_t target0_int_raw:1;
+        /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  interupt1 raw
+         */
+        uint32_t target1_int_raw:1;
+        /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  interupt2 raw
+         */
+        uint32_t target2_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  systimer interrupt clear register
+ */
+typedef union {
+    struct {
+        /** target0_int_clr : WT; bitpos: [0]; default: 0;
+         *  interupt0 clear
+         */
+        uint32_t target0_int_clr:1;
+        /** target1_int_clr : WT; bitpos: [1]; default: 0;
+         *  interupt1 clear
+         */
+        uint32_t target1_int_clr:1;
+        /** target2_int_clr : WT; bitpos: [2]; default: 0;
+         *  interupt2 clear
+         */
+        uint32_t target2_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_clr_reg_t;
+
+/** Type of int_st register
+ *  systimer interrupt status register
+ */
+typedef union {
+    struct {
+        /** target0_int_st : RO; bitpos: [0]; default: 0;
+         *  interupt0 status
+         */
+        uint32_t target0_int_st:1;
+        /** target1_int_st : RO; bitpos: [1]; default: 0;
+         *  interupt1 status
+         */
+        uint32_t target1_int_st:1;
+        /** target2_int_st : RO; bitpos: [2]; default: 0;
+         *  interupt2 status
+         */
+        uint32_t target2_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_st_reg_t;
+
+
+/** Group: SYSTEM TIMER COMP STATUS REGISTER */
+/** Type of real_target_hi/lo register
+ *  system timer comp actual target value low register
+ */
+typedef struct {
+    union {
+        struct {
+            /** target_lo_ro : RO; bitpos: [31:0]; default: 0;
+             *  actual target value value low 32 bits
+             */
+            uint32_t target_lo_ro: 32;
+        };
+        uint32_t val;
+    } lo;
+    union {
+        struct {
+            /** target_hi_ro : RO; bitpos: [19:0]; default: 0;
+             *  actual target value value high 20 bits
+             */
+            uint32_t target_hi_ro: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+} systimer_real_target_reg_t;
+
+
+/** Group: VERSION REGISTER */
+/** Type of date register
+ *  system timer version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35655795;
+         *  systimer register version
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} systimer_date_reg_t;
+
+
+typedef struct systimer_dev_t {
+    volatile systimer_conf_reg_t conf;
+    volatile systimer_unit_op_reg_t unit_op[2];
+    volatile systimer_unit_load_val_reg_t unit_load_val[2];
+    volatile systimer_target_val_reg_t target_val[3];
+    volatile systimer_target_conf_reg_t target_conf[3];
+    volatile systimer_unit_value_reg_t unit_val[2];
+    volatile systimer_comp_load_reg_t comp_load[3];
+    volatile systimer_unit_load_reg_t unit_load[2];
+    volatile systimer_int_ena_reg_t int_ena;
+    volatile systimer_int_raw_reg_t int_raw;
+    volatile systimer_int_clr_reg_t int_clr;
+    volatile systimer_int_st_reg_t int_st;
+    volatile systimer_real_target_reg_t real_target[3];
+    uint32_t reserved_08c[28];
+    volatile systimer_date_reg_t date;
+} systimer_dev_t;
+
+extern systimer_dev_t SYSTIMER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_reg.h
new file mode 100644
index 0000000000..cb893d2353
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_reg.h
@@ -0,0 +1,716 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TIMG_T0CONFIG_REG register
+ *  Timer 0 configuration register
+ */
+#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
+/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
+ *  When set, the alarm is enabled. This bit is automatically cleared once an
+ *  alarm occurs.
+ */
+#define TIMG_T0_ALARM_EN    (BIT(10))
+#define TIMG_T0_ALARM_EN_M  (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
+#define TIMG_T0_ALARM_EN_V  0x00000001U
+#define TIMG_T0_ALARM_EN_S  10
+/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
+ *  When set, Timer 0 's clock divider counter will be reset.
+ */
+#define TIMG_T0_DIVCNT_RST    (BIT(12))
+#define TIMG_T0_DIVCNT_RST_M  (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
+#define TIMG_T0_DIVCNT_RST_V  0x00000001U
+#define TIMG_T0_DIVCNT_RST_S  12
+/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
+ *  Timer 0 clock (T0_clk) prescaler value.
+ */
+#define TIMG_T0_DIVIDER    0x0000FFFFU
+#define TIMG_T0_DIVIDER_M  (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
+#define TIMG_T0_DIVIDER_V  0x0000FFFFU
+#define TIMG_T0_DIVIDER_S  13
+/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
+ *  When set, timer 0 auto-reload at alarm is enabled.
+ */
+#define TIMG_T0_AUTORELOAD    (BIT(29))
+#define TIMG_T0_AUTORELOAD_M  (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
+#define TIMG_T0_AUTORELOAD_V  0x00000001U
+#define TIMG_T0_AUTORELOAD_S  29
+/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
+ *  When set, the timer 0 time-base counter will increment every clock tick. When
+ *  cleared, the timer 0 time-base counter will decrement.
+ */
+#define TIMG_T0_INCREASE    (BIT(30))
+#define TIMG_T0_INCREASE_M  (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
+#define TIMG_T0_INCREASE_V  0x00000001U
+#define TIMG_T0_INCREASE_S  30
+/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
+ *  When set, the timer 0 time-base counter is enabled.
+ */
+#define TIMG_T0_EN    (BIT(31))
+#define TIMG_T0_EN_M  (TIMG_T0_EN_V << TIMG_T0_EN_S)
+#define TIMG_T0_EN_V  0x00000001U
+#define TIMG_T0_EN_S  31
+
+/** TIMG_T0LO_REG register
+ *  Timer 0 current value, low 32 bits
+ */
+#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
+/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
+ *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
+ *  of timer 0 can be read here.
+ */
+#define TIMG_T0_LO    0xFFFFFFFFU
+#define TIMG_T0_LO_M  (TIMG_T0_LO_V << TIMG_T0_LO_S)
+#define TIMG_T0_LO_V  0xFFFFFFFFU
+#define TIMG_T0_LO_S  0
+
+/** TIMG_T0HI_REG register
+ *  Timer 0 current value, high 22 bits
+ */
+#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
+/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
+ *  After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
+ *  of timer 0 can be read here.
+ */
+#define TIMG_T0_HI    0x003FFFFFU
+#define TIMG_T0_HI_M  (TIMG_T0_HI_V << TIMG_T0_HI_S)
+#define TIMG_T0_HI_V  0x003FFFFFU
+#define TIMG_T0_HI_S  0
+
+/** TIMG_T0UPDATE_REG register
+ *  Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
+ */
+#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
+/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
+ */
+#define TIMG_T0_UPDATE    (BIT(31))
+#define TIMG_T0_UPDATE_M  (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
+#define TIMG_T0_UPDATE_V  0x00000001U
+#define TIMG_T0_UPDATE_S  31
+
+/** TIMG_T0ALARMLO_REG register
+ *  Timer 0 alarm value, low 32 bits
+ */
+#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
+/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Timer 0 alarm trigger time-base counter value, low 32 bits.
+ */
+#define TIMG_T0_ALARM_LO    0xFFFFFFFFU
+#define TIMG_T0_ALARM_LO_M  (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
+#define TIMG_T0_ALARM_LO_V  0xFFFFFFFFU
+#define TIMG_T0_ALARM_LO_S  0
+
+/** TIMG_T0ALARMHI_REG register
+ *  Timer 0 alarm value, high bits
+ */
+#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
+/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Timer 0 alarm trigger time-base counter value, high 22 bits.
+ */
+#define TIMG_T0_ALARM_HI    0x003FFFFFU
+#define TIMG_T0_ALARM_HI_M  (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
+#define TIMG_T0_ALARM_HI_V  0x003FFFFFU
+#define TIMG_T0_ALARM_HI_S  0
+
+/** TIMG_T0LOADLO_REG register
+ *  Timer 0 reload value, low 32 bits
+ */
+#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
+/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Low 32 bits of the value that a reload will load onto timer 0 time-base
+ *  Counter.
+ */
+#define TIMG_T0_LOAD_LO    0xFFFFFFFFU
+#define TIMG_T0_LOAD_LO_M  (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
+#define TIMG_T0_LOAD_LO_V  0xFFFFFFFFU
+#define TIMG_T0_LOAD_LO_S  0
+
+/** TIMG_T0LOADHI_REG register
+ *  Timer 0 reload value, high 22 bits
+ */
+#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
+/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
+ *  High 22 bits of the value that a reload will load onto timer 0 time-base
+ *  counter.
+ */
+#define TIMG_T0_LOAD_HI    0x003FFFFFU
+#define TIMG_T0_LOAD_HI_M  (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
+#define TIMG_T0_LOAD_HI_V  0x003FFFFFU
+#define TIMG_T0_LOAD_HI_S  0
+
+/** TIMG_T0LOAD_REG register
+ *  Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
+ */
+#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
+/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
+ *
+ *  Write any value to trigger a timer 0 time-base counter reload.
+ */
+#define TIMG_T0_LOAD    0xFFFFFFFFU
+#define TIMG_T0_LOAD_M  (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
+#define TIMG_T0_LOAD_V  0xFFFFFFFFU
+#define TIMG_T0_LOAD_S  0
+
+/** TIMG_T1CONFIG_REG register
+ *  Timer 1 configuration register
+ */
+#define TIMG_T1CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x24)
+/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
+ *  When set, the alarm is enabled. This bit is automatically cleared once an
+ *  alarm occurs.
+ */
+#define TIMG_T1_ALARM_EN    (BIT(10))
+#define TIMG_T1_ALARM_EN_M  (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
+#define TIMG_T1_ALARM_EN_V  0x00000001U
+#define TIMG_T1_ALARM_EN_S  10
+/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
+ *  When set, Timer 1 's clock divider counter will be reset.
+ */
+#define TIMG_T1_DIVCNT_RST    (BIT(12))
+#define TIMG_T1_DIVCNT_RST_M  (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
+#define TIMG_T1_DIVCNT_RST_V  0x00000001U
+#define TIMG_T1_DIVCNT_RST_S  12
+/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
+ *  Timer 1 clock (T1_clk) prescaler value.
+ */
+#define TIMG_T1_DIVIDER    0x0000FFFFU
+#define TIMG_T1_DIVIDER_M  (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
+#define TIMG_T1_DIVIDER_V  0x0000FFFFU
+#define TIMG_T1_DIVIDER_S  13
+/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
+ *  When set, timer 1 auto-reload at alarm is enabled.
+ */
+#define TIMG_T1_AUTORELOAD    (BIT(29))
+#define TIMG_T1_AUTORELOAD_M  (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
+#define TIMG_T1_AUTORELOAD_V  0x00000001U
+#define TIMG_T1_AUTORELOAD_S  29
+/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
+ *  When set, the timer 1 time-base counter will increment every clock tick. When
+ *  cleared, the timer 1 time-base counter will decrement.
+ */
+#define TIMG_T1_INCREASE    (BIT(30))
+#define TIMG_T1_INCREASE_M  (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
+#define TIMG_T1_INCREASE_V  0x00000001U
+#define TIMG_T1_INCREASE_S  30
+/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
+ *  When set, the timer 1 time-base counter is enabled.
+ */
+#define TIMG_T1_EN    (BIT(31))
+#define TIMG_T1_EN_M  (TIMG_T1_EN_V << TIMG_T1_EN_S)
+#define TIMG_T1_EN_V  0x00000001U
+#define TIMG_T1_EN_S  31
+
+/** TIMG_T1LO_REG register
+ *  Timer 1 current value, low 32 bits
+ */
+#define TIMG_T1LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x28)
+/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
+ *  After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
+ *  of timer 1 can be read here.
+ */
+#define TIMG_T1_LO    0xFFFFFFFFU
+#define TIMG_T1_LO_M  (TIMG_T1_LO_V << TIMG_T1_LO_S)
+#define TIMG_T1_LO_V  0xFFFFFFFFU
+#define TIMG_T1_LO_S  0
+
+/** TIMG_T1HI_REG register
+ *  Timer 1 current value, high 22 bits
+ */
+#define TIMG_T1HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x2c)
+/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
+ *  After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
+ *  of timer 1 can be read here.
+ */
+#define TIMG_T1_HI    0x003FFFFFU
+#define TIMG_T1_HI_M  (TIMG_T1_HI_V << TIMG_T1_HI_S)
+#define TIMG_T1_HI_V  0x003FFFFFU
+#define TIMG_T1_HI_S  0
+
+/** TIMG_T1UPDATE_REG register
+ *  Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
+ */
+#define TIMG_T1UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0x30)
+/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
+ */
+#define TIMG_T1_UPDATE    (BIT(31))
+#define TIMG_T1_UPDATE_M  (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
+#define TIMG_T1_UPDATE_V  0x00000001U
+#define TIMG_T1_UPDATE_S  31
+
+/** TIMG_T1ALARMLO_REG register
+ *  Timer 1 alarm value, low 32 bits
+ */
+#define TIMG_T1ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x34)
+/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Timer 1 alarm trigger time-base counter value, low 32 bits.
+ */
+#define TIMG_T1_ALARM_LO    0xFFFFFFFFU
+#define TIMG_T1_ALARM_LO_M  (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
+#define TIMG_T1_ALARM_LO_V  0xFFFFFFFFU
+#define TIMG_T1_ALARM_LO_S  0
+
+/** TIMG_T1ALARMHI_REG register
+ *  Timer 1 alarm value, high bits
+ */
+#define TIMG_T1ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x38)
+/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Timer 1 alarm trigger time-base counter value, high 22 bits.
+ */
+#define TIMG_T1_ALARM_HI    0x003FFFFFU
+#define TIMG_T1_ALARM_HI_M  (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
+#define TIMG_T1_ALARM_HI_V  0x003FFFFFU
+#define TIMG_T1_ALARM_HI_S  0
+
+/** TIMG_T1LOADLO_REG register
+ *  Timer 1 reload value, low 32 bits
+ */
+#define TIMG_T1LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x3c)
+/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Low 32 bits of the value that a reload will load onto timer 1 time-base
+ *  Counter.
+ */
+#define TIMG_T1_LOAD_LO    0xFFFFFFFFU
+#define TIMG_T1_LOAD_LO_M  (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
+#define TIMG_T1_LOAD_LO_V  0xFFFFFFFFU
+#define TIMG_T1_LOAD_LO_S  0
+
+/** TIMG_T1LOADHI_REG register
+ *  Timer 1 reload value, high 22 bits
+ */
+#define TIMG_T1LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x40)
+/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
+ *  High 22 bits of the value that a reload will load onto timer 1 time-base
+ *  counter.
+ */
+#define TIMG_T1_LOAD_HI    0x003FFFFFU
+#define TIMG_T1_LOAD_HI_M  (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
+#define TIMG_T1_LOAD_HI_V  0x003FFFFFU
+#define TIMG_T1_LOAD_HI_S  0
+
+/** TIMG_T1LOAD_REG register
+ *  Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
+ */
+#define TIMG_T1LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x44)
+/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
+ *
+ *  Write any value to trigger a timer 1 time-base counter reload.
+ */
+#define TIMG_T1_LOAD    0xFFFFFFFFU
+#define TIMG_T1_LOAD_M  (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
+#define TIMG_T1_LOAD_V  0xFFFFFFFFU
+#define TIMG_T1_LOAD_S  0
+
+/** TIMG_WDTCONFIG0_REG register
+ *  Watchdog timer configuration register
+ */
+#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
+/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
+ *  WDT reset CPU enable.
+ */
+#define TIMG_WDT_APPCPU_RESET_EN    (BIT(12))
+#define TIMG_WDT_APPCPU_RESET_EN_M  (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
+#define TIMG_WDT_APPCPU_RESET_EN_V  0x00000001U
+#define TIMG_WDT_APPCPU_RESET_EN_S  12
+/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
+ *  WDT reset CPU enable.
+ */
+#define TIMG_WDT_PROCPU_RESET_EN    (BIT(13))
+#define TIMG_WDT_PROCPU_RESET_EN_M  (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
+#define TIMG_WDT_PROCPU_RESET_EN_V  0x00000001U
+#define TIMG_WDT_PROCPU_RESET_EN_S  13
+/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
+ *  When set, Flash boot protection is enabled.
+ */
+#define TIMG_WDT_FLASHBOOT_MOD_EN    (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_M  (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
+#define TIMG_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
+#define TIMG_WDT_FLASHBOOT_MOD_EN_S  14
+/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
+ *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
+ *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+ */
+#define TIMG_WDT_SYS_RESET_LENGTH    0x00000007U
+#define TIMG_WDT_SYS_RESET_LENGTH_M  (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
+#define TIMG_WDT_SYS_RESET_LENGTH_V  0x00000007U
+#define TIMG_WDT_SYS_RESET_LENGTH_S  15
+/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
+ *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+ *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+ */
+#define TIMG_WDT_CPU_RESET_LENGTH    0x00000007U
+#define TIMG_WDT_CPU_RESET_LENGTH_M  (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
+#define TIMG_WDT_CPU_RESET_LENGTH_V  0x00000007U
+#define TIMG_WDT_CPU_RESET_LENGTH_S  18
+/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
+ *  update the WDT configuration registers
+ */
+#define TIMG_WDT_CONF_UPDATE_EN    (BIT(22))
+#define TIMG_WDT_CONF_UPDATE_EN_M  (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
+#define TIMG_WDT_CONF_UPDATE_EN_V  0x00000001U
+#define TIMG_WDT_CONF_UPDATE_EN_S  22
+/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
+ *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG3    0x00000003U
+#define TIMG_WDT_STG3_M  (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
+#define TIMG_WDT_STG3_V  0x00000003U
+#define TIMG_WDT_STG3_S  23
+/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
+ *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG2    0x00000003U
+#define TIMG_WDT_STG2_M  (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
+#define TIMG_WDT_STG2_V  0x00000003U
+#define TIMG_WDT_STG2_S  25
+/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
+ *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG1    0x00000003U
+#define TIMG_WDT_STG1_M  (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
+#define TIMG_WDT_STG1_V  0x00000003U
+#define TIMG_WDT_STG1_S  27
+/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
+ *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG0    0x00000003U
+#define TIMG_WDT_STG0_M  (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
+#define TIMG_WDT_STG0_V  0x00000003U
+#define TIMG_WDT_STG0_S  29
+/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
+ *  When set, MWDT is enabled.
+ */
+#define TIMG_WDT_EN    (BIT(31))
+#define TIMG_WDT_EN_M  (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
+#define TIMG_WDT_EN_V  0x00000001U
+#define TIMG_WDT_EN_S  31
+
+/** TIMG_WDTCONFIG1_REG register
+ *  Watchdog timer prescaler register
+ */
+#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
+/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
+ *  When set, WDT 's clock divider counter will be reset.
+ */
+#define TIMG_WDT_DIVCNT_RST    (BIT(0))
+#define TIMG_WDT_DIVCNT_RST_M  (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
+#define TIMG_WDT_DIVCNT_RST_V  0x00000001U
+#define TIMG_WDT_DIVCNT_RST_S  0
+/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
+ *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+ *  TIMG_WDT_CLK_PRESCALE.
+ */
+#define TIMG_WDT_CLK_PRESCALE    0x0000FFFFU
+#define TIMG_WDT_CLK_PRESCALE_M  (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
+#define TIMG_WDT_CLK_PRESCALE_V  0x0000FFFFU
+#define TIMG_WDT_CLK_PRESCALE_S  16
+
+/** TIMG_WDTCONFIG2_REG register
+ *  Watchdog timer stage 0 timeout value
+ */
+#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
+/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
+ *  Stage 0 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG0_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG0_HOLD_M  (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
+#define TIMG_WDT_STG0_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG0_HOLD_S  0
+
+/** TIMG_WDTCONFIG3_REG register
+ *  Watchdog timer stage 1 timeout value
+ */
+#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
+/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
+ *  Stage 1 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG1_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG1_HOLD_M  (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
+#define TIMG_WDT_STG1_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG1_HOLD_S  0
+
+/** TIMG_WDTCONFIG4_REG register
+ *  Watchdog timer stage 2 timeout value
+ */
+#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
+/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
+ *  Stage 2 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG2_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG2_HOLD_M  (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
+#define TIMG_WDT_STG2_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG2_HOLD_S  0
+
+/** TIMG_WDTCONFIG5_REG register
+ *  Watchdog timer stage 3 timeout value
+ */
+#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
+/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
+ *  Stage 3 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG3_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG3_HOLD_M  (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
+#define TIMG_WDT_STG3_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG3_HOLD_S  0
+
+/** TIMG_WDTFEED_REG register
+ *  Write to feed the watchdog timer
+ */
+#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
+/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
+ *  Write any value to feed the MWDT. (WO)
+ */
+#define TIMG_WDT_FEED    0xFFFFFFFFU
+#define TIMG_WDT_FEED_M  (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
+#define TIMG_WDT_FEED_V  0xFFFFFFFFU
+#define TIMG_WDT_FEED_S  0
+
+/** TIMG_WDTWPROTECT_REG register
+ *  Watchdog write protect register
+ */
+#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
+/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
+ *  If the register contains a different value than its reset value, write
+ *  protection is enabled.
+ */
+#define TIMG_WDT_WKEY    0xFFFFFFFFU
+#define TIMG_WDT_WKEY_M  (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
+#define TIMG_WDT_WKEY_V  0xFFFFFFFFU
+#define TIMG_WDT_WKEY_S  0
+
+/** TIMG_RTCCALICFG_REG register
+ *  RTC calibration configure register
+ */
+#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
+/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
+ *  0: one-shot frequency calculation,1: periodic frequency calculation,
+ */
+#define TIMG_RTC_CALI_START_CYCLING    (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_M  (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
+#define TIMG_RTC_CALI_START_CYCLING_V  0x00000001U
+#define TIMG_RTC_CALI_START_CYCLING_S  12
+/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
+ *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+ */
+#define TIMG_RTC_CALI_CLK_SEL    0x00000003U
+#define TIMG_RTC_CALI_CLK_SEL_M  (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
+#define TIMG_RTC_CALI_CLK_SEL_V  0x00000003U
+#define TIMG_RTC_CALI_CLK_SEL_S  13
+/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
+ *  indicate one-shot frequency calculation is done.
+ */
+#define TIMG_RTC_CALI_RDY    (BIT(15))
+#define TIMG_RTC_CALI_RDY_M  (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
+#define TIMG_RTC_CALI_RDY_V  0x00000001U
+#define TIMG_RTC_CALI_RDY_S  15
+/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
+ *  Configure the time to calculate RTC slow clock's frequency.
+ */
+#define TIMG_RTC_CALI_MAX    0x00007FFFU
+#define TIMG_RTC_CALI_MAX_M  (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
+#define TIMG_RTC_CALI_MAX_V  0x00007FFFU
+#define TIMG_RTC_CALI_MAX_S  16
+/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start one-shot frequency calculation.
+ */
+#define TIMG_RTC_CALI_START    (BIT(31))
+#define TIMG_RTC_CALI_START_M  (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
+#define TIMG_RTC_CALI_START_V  0x00000001U
+#define TIMG_RTC_CALI_START_S  31
+
+/** TIMG_RTCCALICFG1_REG register
+ *  RTC calibration configure1 register
+ */
+#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
+/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
+ *  indicate periodic frequency calculation is done.
+ */
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD    (BIT(0))
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M  (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V  0x00000001U
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S  0
+/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
+ *  When one-shot or periodic frequency calculation is done, read this value to
+ *  calculate RTC slow clock's frequency.
+ */
+#define TIMG_RTC_CALI_VALUE    0x01FFFFFFU
+#define TIMG_RTC_CALI_VALUE_M  (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
+#define TIMG_RTC_CALI_VALUE_V  0x01FFFFFFU
+#define TIMG_RTC_CALI_VALUE_S  7
+
+/** TIMG_INT_ENA_TIMERS_REG register
+ *  Interrupt enable bits
+ */
+#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
+/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_ENA    (BIT(0))
+#define TIMG_T0_INT_ENA_M  (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
+#define TIMG_T0_INT_ENA_V  0x00000001U
+#define TIMG_T0_INT_ENA_S  0
+/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_ENA    (BIT(1))
+#define TIMG_T1_INT_ENA_M  (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
+#define TIMG_T1_INT_ENA_V  0x00000001U
+#define TIMG_T1_INT_ENA_S  1
+/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_ENA    (BIT(2))
+#define TIMG_WDT_INT_ENA_M  (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
+#define TIMG_WDT_INT_ENA_V  0x00000001U
+#define TIMG_WDT_INT_ENA_S  2
+
+/** TIMG_INT_RAW_TIMERS_REG register
+ *  Raw interrupt status
+ */
+#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
+/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_RAW    (BIT(0))
+#define TIMG_T0_INT_RAW_M  (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
+#define TIMG_T0_INT_RAW_V  0x00000001U
+#define TIMG_T0_INT_RAW_S  0
+/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_RAW    (BIT(1))
+#define TIMG_T1_INT_RAW_M  (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
+#define TIMG_T1_INT_RAW_V  0x00000001U
+#define TIMG_T1_INT_RAW_S  1
+/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_RAW    (BIT(2))
+#define TIMG_WDT_INT_RAW_M  (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
+#define TIMG_WDT_INT_RAW_V  0x00000001U
+#define TIMG_WDT_INT_RAW_S  2
+
+/** TIMG_INT_ST_TIMERS_REG register
+ *  Masked interrupt status
+ */
+#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
+/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_ST    (BIT(0))
+#define TIMG_T0_INT_ST_M  (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
+#define TIMG_T0_INT_ST_V  0x00000001U
+#define TIMG_T0_INT_ST_S  0
+/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_ST    (BIT(1))
+#define TIMG_T1_INT_ST_M  (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
+#define TIMG_T1_INT_ST_V  0x00000001U
+#define TIMG_T1_INT_ST_S  1
+/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_ST    (BIT(2))
+#define TIMG_WDT_INT_ST_M  (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
+#define TIMG_WDT_INT_ST_V  0x00000001U
+#define TIMG_WDT_INT_ST_S  2
+
+/** TIMG_INT_CLR_TIMERS_REG register
+ *  Interrupt clear bits
+ */
+#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
+/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_CLR    (BIT(0))
+#define TIMG_T0_INT_CLR_M  (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
+#define TIMG_T0_INT_CLR_V  0x00000001U
+#define TIMG_T0_INT_CLR_S  0
+/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_CLR    (BIT(1))
+#define TIMG_T1_INT_CLR_M  (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
+#define TIMG_T1_INT_CLR_V  0x00000001U
+#define TIMG_T1_INT_CLR_S  1
+/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_CLR    (BIT(2))
+#define TIMG_WDT_INT_CLR_M  (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
+#define TIMG_WDT_INT_CLR_V  0x00000001U
+#define TIMG_WDT_INT_CLR_S  2
+
+/** TIMG_RTCCALICFG2_REG register
+ *  Timer group calibration register
+ */
+#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
+/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
+ *  RTC calibration timeout indicator
+ */
+#define TIMG_RTC_CALI_TIMEOUT    (BIT(0))
+#define TIMG_RTC_CALI_TIMEOUT_M  (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
+#define TIMG_RTC_CALI_TIMEOUT_V  0x00000001U
+#define TIMG_RTC_CALI_TIMEOUT_S  0
+/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
+ *  Cycles that release calibration timeout reset
+ */
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT    0x0000000FU
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M  (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V  0x0000000FU
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S  3
+/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
+ *  Threshold value for the RTC calibration timer. If the calibration timer's value
+ *  exceeds this threshold, a timeout is triggered.
+ */
+#define TIMG_RTC_CALI_TIMEOUT_THRES    0x01FFFFFFU
+#define TIMG_RTC_CALI_TIMEOUT_THRES_M  (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
+#define TIMG_RTC_CALI_TIMEOUT_THRES_V  0x01FFFFFFU
+#define TIMG_RTC_CALI_TIMEOUT_THRES_S  7
+
+/** TIMG_NTIMERS_DATE_REG register
+ *  Timer version control register
+ */
+#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
+/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
+ *  Timer version control register
+ */
+#define TIMG_NTIMGS_DATE    0x0FFFFFFFU
+#define TIMG_NTIMGS_DATE_M  (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
+#define TIMG_NTIMGS_DATE_V  0x0FFFFFFFU
+#define TIMG_NTIMGS_DATE_S  0
+
+/** TIMG_REGCLK_REG register
+ *  Timer group clock gate register
+ */
+#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
+/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
+ *  enable timer's etm task and event
+ */
+#define TIMG_ETM_EN    (BIT(28))
+#define TIMG_ETM_EN_M  (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
+#define TIMG_ETM_EN_V  0x00000001U
+#define TIMG_ETM_EN_S  28
+/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
+ *  Registers can not be read or written to by software.
+ */
+#define TIMG_CLK_EN    (BIT(31))
+#define TIMG_CLK_EN_M  (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
+#define TIMG_CLK_EN_V  0x00000001U
+#define TIMG_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_struct.h
new file mode 100644
index 0000000000..363dff92d1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_struct.h
@@ -0,0 +1,571 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: T0 Control and configuration registers */
+/** Type of txconfig register
+ *  Timer x configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
+         *  When set, the alarm is enabled. This bit is automatically cleared once an
+         *  alarm occurs.
+         */
+        uint32_t tx_alarm_en:1;
+        uint32_t reserved_11:1;
+        /** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
+         *  When set, Timer x 's clock divider counter will be reset.
+         */
+        uint32_t tx_divcnt_rst:1;
+        /** tx_divider : R/W; bitpos: [28:13]; default: 1;
+         *  Timer x clock (Tx_clk) prescaler value.
+         */
+        uint32_t tx_divider:16;
+        /** tx_autoreload : R/W; bitpos: [29]; default: 1;
+         *  When set, timer x auto-reload at alarm is enabled.
+         */
+        uint32_t tx_autoreload:1;
+        /** tx_increase : R/W; bitpos: [30]; default: 1;
+         *  When set, the timer x time-base counter will increment every clock tick. When
+         *  cleared, the timer x time-base counter will decrement.
+         */
+        uint32_t tx_increase:1;
+        /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
+         *  When set, the timer x time-base counter is enabled.
+         */
+        uint32_t tx_en:1;
+    };
+    uint32_t val;
+} timg_txconfig_reg_t;
+
+/** Type of txlo register
+ *  Timer x current value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_lo : RO; bitpos: [31:0]; default: 0;
+         *  After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
+         *  of timer x can be read here.
+         */
+        uint32_t tx_lo:32;
+    };
+    uint32_t val;
+} timg_txlo_reg_t;
+
+/** Type of txhi register
+ *  Timer x current value, high 22 bits
+ */
+typedef union {
+    struct {
+        /** tx_hi : RO; bitpos: [21:0]; default: 0;
+         *  After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
+         *  of timer x can be read here.
+         */
+        uint32_t tx_hi:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} timg_txhi_reg_t;
+
+/** Type of txupdate register
+ *  Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_update : R/W/SC; bitpos: [31]; default: 0;
+         *  After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
+         */
+        uint32_t tx_update:1;
+    };
+    uint32_t val;
+} timg_txupdate_reg_t;
+
+/** Type of txalarmlo register
+ *  Timer x alarm value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
+         *  Timer x alarm trigger time-base counter value, low 32 bits.
+         */
+        uint32_t tx_alarm_lo:32;
+    };
+    uint32_t val;
+} timg_txalarmlo_reg_t;
+
+/** Type of txalarmhi register
+ *  Timer x alarm value, high bits
+ */
+typedef union {
+    struct {
+        /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
+         *  Timer x alarm trigger time-base counter value, high 22 bits.
+         */
+        uint32_t tx_alarm_hi:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} timg_txalarmhi_reg_t;
+
+/** Type of txloadlo register
+ *  Timer x reload value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
+         *  Low 32 bits of the value that a reload will load onto timer x time-base
+         *  Counter.
+         */
+        uint32_t tx_load_lo:32;
+    };
+    uint32_t val;
+} timg_txloadlo_reg_t;
+
+/** Type of txloadhi register
+ *  Timer x reload value, high 22 bits
+ */
+typedef union {
+    struct {
+        /** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
+         *  High 22 bits of the value that a reload will load onto timer x time-base
+         *  counter.
+         */
+        uint32_t tx_load_hi:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} timg_txloadhi_reg_t;
+
+/** Type of txload register
+ *  Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
+ */
+typedef union {
+    struct {
+        /** tx_load : WT; bitpos: [31:0]; default: 0;
+         *
+         *  Write any value to trigger a timer x time-base counter reload.
+         */
+        uint32_t tx_load:32;
+    };
+    uint32_t val;
+} timg_txload_reg_t;
+
+/** Group: WDT Control and configuration registers */
+/** Type of wdtconfig0 register
+ *  Watchdog timer configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
+         *  WDT reset CPU enable.
+         */
+        uint32_t wdt_appcpu_reset_en:1;
+        /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
+         *  WDT reset CPU enable.
+         */
+        uint32_t wdt_procpu_reset_en:1;
+        /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
+         *  When set, Flash boot protection is enabled.
+         */
+        uint32_t wdt_flashboot_mod_en:1;
+        /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
+         *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
+         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+         */
+        uint32_t wdt_sys_reset_length:3;
+        /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
+         *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+         */
+        uint32_t wdt_cpu_reset_length:3;
+        uint32_t reserved_21:1;
+        /** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
+         *  update the WDT configuration registers
+         */
+        uint32_t wdt_conf_update_en:1;
+        /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
+         *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg3:2;
+        /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
+         *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg2:2;
+        /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
+         *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg1:2;
+        /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
+         *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg0:2;
+        /** wdt_en : R/W; bitpos: [31]; default: 0;
+         *  When set, MWDT is enabled.
+         */
+        uint32_t wdt_en:1;
+    };
+    uint32_t val;
+} timg_wdtconfig0_reg_t;
+
+/** Type of wdtconfig1 register
+ *  Watchdog timer prescaler register
+ */
+typedef union {
+    struct {
+        /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
+         *  When set, WDT 's clock divider counter will be reset.
+         */
+        uint32_t wdt_divcnt_rst:1;
+        uint32_t reserved_1:15;
+        /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
+         *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+         *  TIMG_WDT_CLK_PRESCALE.
+         */
+        uint32_t wdt_clk_prescale:16;
+    };
+    uint32_t val;
+} timg_wdtconfig1_reg_t;
+
+/** Type of wdtconfig2 register
+ *  Watchdog timer stage 0 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
+         *  Stage 0 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg0_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig2_reg_t;
+
+/** Type of wdtconfig3 register
+ *  Watchdog timer stage 1 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
+         *  Stage 1 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg1_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig3_reg_t;
+
+/** Type of wdtconfig4 register
+ *  Watchdog timer stage 2 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
+         *  Stage 2 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg2_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig4_reg_t;
+
+/** Type of wdtconfig5 register
+ *  Watchdog timer stage 3 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
+         *  Stage 3 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg3_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig5_reg_t;
+
+/** Type of wdtfeed register
+ *  Write to feed the watchdog timer
+ */
+typedef union {
+    struct {
+        /** wdt_feed : WT; bitpos: [31:0]; default: 0;
+         *  Write any value to feed the MWDT. (WO)
+         */
+        uint32_t wdt_feed:32;
+    };
+    uint32_t val;
+} timg_wdtfeed_reg_t;
+
+/** Type of wdtwprotect register
+ *  Watchdog write protect register
+ */
+typedef union {
+    struct {
+        /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
+         *  If the register contains a different value than its reset value, write
+         *  protection is enabled.
+         */
+        uint32_t wdt_wkey:32;
+    };
+    uint32_t val;
+} timg_wdtwprotect_reg_t;
+
+
+/** Group: RTC CALI Control and configuration registers */
+/** Type of rtccalicfg register
+ *  RTC calibration configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
+         *  0: one-shot frequency calculation,1: periodic frequency calculation,
+         */
+        uint32_t rtc_cali_start_cycling:1;
+        /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
+         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         */
+        uint32_t rtc_cali_clk_sel:2;
+        /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
+         *  indicate one-shot frequency calculation is done.
+         */
+        uint32_t rtc_cali_rdy:1;
+        /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
+         *  Configure the time to calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_max:15;
+        /** rtc_cali_start : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start one-shot frequency calculation.
+         */
+        uint32_t rtc_cali_start:1;
+    };
+    uint32_t val;
+} timg_rtccalicfg_reg_t;
+
+/** Type of rtccalicfg1 register
+ *  RTC calibration configure1 register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
+         *  indicate periodic frequency calculation is done.
+         */
+        uint32_t rtc_cali_cycling_data_vld:1;
+        uint32_t reserved_1:6;
+        /** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
+         *  When one-shot or periodic frequency calculation is done, read this value to
+         *  calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_value:25;
+    };
+    uint32_t val;
+} timg_rtccalicfg1_reg_t;
+
+/** Type of rtccalicfg2 register
+ *  Timer group calibration register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
+         *  RTC calibration timeout indicator
+         */
+        uint32_t rtc_cali_timeout:1;
+        uint32_t reserved_1:2;
+        /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
+         *  Cycles that release calibration timeout reset
+         */
+        uint32_t rtc_cali_timeout_rst_cnt:4;
+        /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
+         *  Threshold value for the RTC calibration timer. If the calibration timer's value
+         *  exceeds this threshold, a timeout is triggered.
+         */
+        uint32_t rtc_cali_timeout_thres:25;
+    };
+    uint32_t val;
+} timg_rtccalicfg2_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_ena_timers register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** t0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_ena:1;
+        /** t1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_ena:1;
+        /** wdt_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} timg_int_ena_timers_reg_t;
+
+/** Type of int_raw_timers register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_raw:1;
+        /** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_raw:1;
+        /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} timg_int_raw_timers_reg_t;
+
+/** Type of int_st_timers register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** t0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_st:1;
+        /** t1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_st:1;
+        /** wdt_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} timg_int_st_timers_reg_t;
+
+/** Type of int_clr_timers register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** t0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_clr:1;
+        /** t1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_clr:1;
+        /** wdt_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} timg_int_clr_timers_reg_t;
+
+
+/** Group: Version register */
+/** Type of ntimers_date register
+ *  Timer version control register
+ */
+typedef union {
+    struct {
+        /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
+         *  Timer version control register
+         */
+        uint32_t ntimgs_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} timg_ntimers_date_reg_t;
+
+
+/** Group: Clock configuration registers */
+/** Type of regclk register
+ *  Timer group clock gate register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** etm_en : R/W; bitpos: [28]; default: 1;
+         *  enable timer's etm task and event
+         */
+        uint32_t etm_en:1;
+        uint32_t reserved_29:2;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
+         *  Registers can not be read or written to by software.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} timg_regclk_reg_t;
+
+
+typedef struct {
+    volatile timg_txconfig_reg_t t0config;
+    volatile timg_txlo_reg_t t0lo;
+    volatile timg_txhi_reg_t t0hi;
+    volatile timg_txupdate_reg_t t0update;
+    volatile timg_txalarmlo_reg_t t0alarmlo;
+    volatile timg_txalarmhi_reg_t t0alarmhi;
+    volatile timg_txloadlo_reg_t t0loadlo;
+    volatile timg_txloadhi_reg_t t0loadhi;
+    volatile timg_txload_reg_t t0load;
+    volatile timg_txconfig_reg_t t1config;
+    volatile timg_txlo_reg_t t1lo;
+    volatile timg_txhi_reg_t t1hi;
+    volatile timg_txupdate_reg_t t1update;
+    volatile timg_txalarmlo_reg_t t1alarmlo;
+    volatile timg_txalarmhi_reg_t t1alarmhi;
+    volatile timg_txloadlo_reg_t t1loadlo;
+    volatile timg_txloadhi_reg_t t1loadhi;
+    volatile timg_txload_reg_t t1load;
+    volatile timg_wdtconfig0_reg_t wdtconfig0;
+    volatile timg_wdtconfig1_reg_t wdtconfig1;
+    volatile timg_wdtconfig2_reg_t wdtconfig2;
+    volatile timg_wdtconfig3_reg_t wdtconfig3;
+    volatile timg_wdtconfig4_reg_t wdtconfig4;
+    volatile timg_wdtconfig5_reg_t wdtconfig5;
+    volatile timg_wdtfeed_reg_t wdtfeed;
+    volatile timg_wdtwprotect_reg_t wdtwprotect;
+    volatile timg_rtccalicfg_reg_t rtccalicfg;
+    volatile timg_rtccalicfg1_reg_t rtccalicfg1;
+    volatile timg_int_ena_timers_reg_t int_ena_timers;
+    volatile timg_int_raw_timers_reg_t int_raw_timers;
+    volatile timg_int_st_timers_reg_t int_st_timers;
+    volatile timg_int_clr_timers_reg_t int_clr_timers;
+    volatile timg_rtccalicfg2_reg_t rtccalicfg2;
+    uint32_t reserved_084[29];
+    volatile timg_ntimers_date_reg_t ntimers_date;
+    volatile timg_regclk_reg_t regclk;
+} timg_dev_t;
+
+extern timg_dev_t TIMERG0;
+extern timg_dev_t TIMERG1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_reg.h
new file mode 100644
index 0000000000..7df8a1271f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_reg.h
@@ -0,0 +1,718 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13422
+
+/** TIMG_T0CONFIG_REG register
+ *  Timer 0 configuration register
+ */
+#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
+/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
+ *  When set, the alarm is enabled. This bit is automatically cleared once an
+ *  alarm occurs.
+ */
+#define TIMG_T0_ALARM_EN    (BIT(10))
+#define TIMG_T0_ALARM_EN_M  (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
+#define TIMG_T0_ALARM_EN_V  0x00000001U
+#define TIMG_T0_ALARM_EN_S  10
+/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
+ *  When set, Timer 0 's clock divider counter will be reset.
+ */
+#define TIMG_T0_DIVCNT_RST    (BIT(12))
+#define TIMG_T0_DIVCNT_RST_M  (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
+#define TIMG_T0_DIVCNT_RST_V  0x00000001U
+#define TIMG_T0_DIVCNT_RST_S  12
+/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
+ *  Timer 0 clock (T0_clk) prescaler value.
+ */
+#define TIMG_T0_DIVIDER    0x0000FFFFU
+#define TIMG_T0_DIVIDER_M  (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
+#define TIMG_T0_DIVIDER_V  0x0000FFFFU
+#define TIMG_T0_DIVIDER_S  13
+/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
+ *  When set, timer 0 auto-reload at alarm is enabled.
+ */
+#define TIMG_T0_AUTORELOAD    (BIT(29))
+#define TIMG_T0_AUTORELOAD_M  (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
+#define TIMG_T0_AUTORELOAD_V  0x00000001U
+#define TIMG_T0_AUTORELOAD_S  29
+/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
+ *  When set, the timer 0 time-base counter will increment every clock tick. When
+ *  cleared, the timer 0 time-base counter will decrement.
+ */
+#define TIMG_T0_INCREASE    (BIT(30))
+#define TIMG_T0_INCREASE_M  (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
+#define TIMG_T0_INCREASE_V  0x00000001U
+#define TIMG_T0_INCREASE_S  30
+/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
+ *  When set, the timer 0 time-base counter is enabled.
+ */
+#define TIMG_T0_EN    (BIT(31))
+#define TIMG_T0_EN_M  (TIMG_T0_EN_V << TIMG_T0_EN_S)
+#define TIMG_T0_EN_V  0x00000001U
+#define TIMG_T0_EN_S  31
+
+/** TIMG_T0LO_REG register
+ *  Timer 0 current value, low 32 bits
+ */
+#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
+/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
+ *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
+ *  of timer 0 can be read here.
+ */
+#define TIMG_T0_LO    0xFFFFFFFFU
+#define TIMG_T0_LO_M  (TIMG_T0_LO_V << TIMG_T0_LO_S)
+#define TIMG_T0_LO_V  0xFFFFFFFFU
+#define TIMG_T0_LO_S  0
+
+/** TIMG_T0HI_REG register
+ *  Timer 0 current value, high 22 bits
+ */
+#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
+/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
+ *  After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
+ *  of timer 0 can be read here.
+ */
+#define TIMG_T0_HI    0x003FFFFFU
+#define TIMG_T0_HI_M  (TIMG_T0_HI_V << TIMG_T0_HI_S)
+#define TIMG_T0_HI_V  0x003FFFFFU
+#define TIMG_T0_HI_S  0
+
+/** TIMG_T0UPDATE_REG register
+ *  Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
+ */
+#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
+/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
+ */
+#define TIMG_T0_UPDATE    (BIT(31))
+#define TIMG_T0_UPDATE_M  (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
+#define TIMG_T0_UPDATE_V  0x00000001U
+#define TIMG_T0_UPDATE_S  31
+
+/** TIMG_T0ALARMLO_REG register
+ *  Timer 0 alarm value, low 32 bits
+ */
+#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
+/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Timer 0 alarm trigger time-base counter value, low 32 bits.
+ */
+#define TIMG_T0_ALARM_LO    0xFFFFFFFFU
+#define TIMG_T0_ALARM_LO_M  (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
+#define TIMG_T0_ALARM_LO_V  0xFFFFFFFFU
+#define TIMG_T0_ALARM_LO_S  0
+
+/** TIMG_T0ALARMHI_REG register
+ *  Timer 0 alarm value, high bits
+ */
+#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
+/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Timer 0 alarm trigger time-base counter value, high 22 bits.
+ */
+#define TIMG_T0_ALARM_HI    0x003FFFFFU
+#define TIMG_T0_ALARM_HI_M  (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
+#define TIMG_T0_ALARM_HI_V  0x003FFFFFU
+#define TIMG_T0_ALARM_HI_S  0
+
+/** TIMG_T0LOADLO_REG register
+ *  Timer 0 reload value, low 32 bits
+ */
+#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
+/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Low 32 bits of the value that a reload will load onto timer 0 time-base
+ *  Counter.
+ */
+#define TIMG_T0_LOAD_LO    0xFFFFFFFFU
+#define TIMG_T0_LOAD_LO_M  (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
+#define TIMG_T0_LOAD_LO_V  0xFFFFFFFFU
+#define TIMG_T0_LOAD_LO_S  0
+
+/** TIMG_T0LOADHI_REG register
+ *  Timer 0 reload value, high 22 bits
+ */
+#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
+/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
+ *  High 22 bits of the value that a reload will load onto timer 0 time-base
+ *  counter.
+ */
+#define TIMG_T0_LOAD_HI    0x003FFFFFU
+#define TIMG_T0_LOAD_HI_M  (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
+#define TIMG_T0_LOAD_HI_V  0x003FFFFFU
+#define TIMG_T0_LOAD_HI_S  0
+
+/** TIMG_T0LOAD_REG register
+ *  Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
+ */
+#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
+/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
+ *
+ *  Write any value to trigger a timer 0 time-base counter reload.
+ */
+#define TIMG_T0_LOAD    0xFFFFFFFFU
+#define TIMG_T0_LOAD_M  (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
+#define TIMG_T0_LOAD_V  0xFFFFFFFFU
+#define TIMG_T0_LOAD_S  0
+
+/** TIMG_T1CONFIG_REG register
+ *  Timer 1 configuration register
+ */
+#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24)
+/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
+ *  When set, the alarm is enabled. This bit is automatically cleared once an
+ *  alarm occurs.
+ */
+#define TIMG_T1_ALARM_EN    (BIT(10))
+#define TIMG_T1_ALARM_EN_M  (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
+#define TIMG_T1_ALARM_EN_V  0x00000001U
+#define TIMG_T1_ALARM_EN_S  10
+/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
+ *  When set, Timer 1 's clock divider counter will be reset.
+ */
+#define TIMG_T1_DIVCNT_RST    (BIT(12))
+#define TIMG_T1_DIVCNT_RST_M  (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
+#define TIMG_T1_DIVCNT_RST_V  0x00000001U
+#define TIMG_T1_DIVCNT_RST_S  12
+/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
+ *  Timer 1 clock (T1_clk) prescaler value.
+ */
+#define TIMG_T1_DIVIDER    0x0000FFFFU
+#define TIMG_T1_DIVIDER_M  (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
+#define TIMG_T1_DIVIDER_V  0x0000FFFFU
+#define TIMG_T1_DIVIDER_S  13
+/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
+ *  When set, timer 1 auto-reload at alarm is enabled.
+ */
+#define TIMG_T1_AUTORELOAD    (BIT(29))
+#define TIMG_T1_AUTORELOAD_M  (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
+#define TIMG_T1_AUTORELOAD_V  0x00000001U
+#define TIMG_T1_AUTORELOAD_S  29
+/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
+ *  When set, the timer 1 time-base counter will increment every clock tick. When
+ *  cleared, the timer 1 time-base counter will decrement.
+ */
+#define TIMG_T1_INCREASE    (BIT(30))
+#define TIMG_T1_INCREASE_M  (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
+#define TIMG_T1_INCREASE_V  0x00000001U
+#define TIMG_T1_INCREASE_S  30
+/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
+ *  When set, the timer 1 time-base counter is enabled.
+ */
+#define TIMG_T1_EN    (BIT(31))
+#define TIMG_T1_EN_M  (TIMG_T1_EN_V << TIMG_T1_EN_S)
+#define TIMG_T1_EN_V  0x00000001U
+#define TIMG_T1_EN_S  31
+
+/** TIMG_T1LO_REG register
+ *  Timer 1 current value, low 32 bits
+ */
+#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x28)
+/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
+ *  After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
+ *  of timer 1 can be read here.
+ */
+#define TIMG_T1_LO    0xFFFFFFFFU
+#define TIMG_T1_LO_M  (TIMG_T1_LO_V << TIMG_T1_LO_S)
+#define TIMG_T1_LO_V  0xFFFFFFFFU
+#define TIMG_T1_LO_S  0
+
+/** TIMG_T1HI_REG register
+ *  Timer 1 current value, high 22 bits
+ */
+#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x2c)
+/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
+ *  After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
+ *  of timer 1 can be read here.
+ */
+#define TIMG_T1_HI    0x003FFFFFU
+#define TIMG_T1_HI_M  (TIMG_T1_HI_V << TIMG_T1_HI_S)
+#define TIMG_T1_HI_V  0x003FFFFFU
+#define TIMG_T1_HI_S  0
+
+/** TIMG_T1UPDATE_REG register
+ *  Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
+ */
+#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x30)
+/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
+ */
+#define TIMG_T1_UPDATE    (BIT(31))
+#define TIMG_T1_UPDATE_M  (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
+#define TIMG_T1_UPDATE_V  0x00000001U
+#define TIMG_T1_UPDATE_S  31
+
+/** TIMG_T1ALARMLO_REG register
+ *  Timer 1 alarm value, low 32 bits
+ */
+#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x34)
+/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Timer 1 alarm trigger time-base counter value, low 32 bits.
+ */
+#define TIMG_T1_ALARM_LO    0xFFFFFFFFU
+#define TIMG_T1_ALARM_LO_M  (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
+#define TIMG_T1_ALARM_LO_V  0xFFFFFFFFU
+#define TIMG_T1_ALARM_LO_S  0
+
+/** TIMG_T1ALARMHI_REG register
+ *  Timer 1 alarm value, high bits
+ */
+#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x38)
+/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Timer 1 alarm trigger time-base counter value, high 22 bits.
+ */
+#define TIMG_T1_ALARM_HI    0x003FFFFFU
+#define TIMG_T1_ALARM_HI_M  (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
+#define TIMG_T1_ALARM_HI_V  0x003FFFFFU
+#define TIMG_T1_ALARM_HI_S  0
+
+/** TIMG_T1LOADLO_REG register
+ *  Timer 1 reload value, low 32 bits
+ */
+#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x3c)
+/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Low 32 bits of the value that a reload will load onto timer 1 time-base
+ *  Counter.
+ */
+#define TIMG_T1_LOAD_LO    0xFFFFFFFFU
+#define TIMG_T1_LOAD_LO_M  (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
+#define TIMG_T1_LOAD_LO_V  0xFFFFFFFFU
+#define TIMG_T1_LOAD_LO_S  0
+
+/** TIMG_T1LOADHI_REG register
+ *  Timer 1 reload value, high 22 bits
+ */
+#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x40)
+/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
+ *  High 22 bits of the value that a reload will load onto timer 1 time-base
+ *  counter.
+ */
+#define TIMG_T1_LOAD_HI    0x003FFFFFU
+#define TIMG_T1_LOAD_HI_M  (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
+#define TIMG_T1_LOAD_HI_V  0x003FFFFFU
+#define TIMG_T1_LOAD_HI_S  0
+
+/** TIMG_T1LOAD_REG register
+ *  Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
+ */
+#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x44)
+/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
+ *
+ *  Write any value to trigger a timer 1 time-base counter reload.
+ */
+#define TIMG_T1_LOAD    0xFFFFFFFFU
+#define TIMG_T1_LOAD_M  (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
+#define TIMG_T1_LOAD_V  0xFFFFFFFFU
+#define TIMG_T1_LOAD_S  0
+
+/** TIMG_WDTCONFIG0_REG register
+ *  Watchdog timer configuration register
+ */
+#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
+/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
+ *  WDT reset CPU enable.
+ */
+#define TIMG_WDT_APPCPU_RESET_EN    (BIT(12))
+#define TIMG_WDT_APPCPU_RESET_EN_M  (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
+#define TIMG_WDT_APPCPU_RESET_EN_V  0x00000001U
+#define TIMG_WDT_APPCPU_RESET_EN_S  12
+/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
+ *  WDT reset CPU enable.
+ */
+#define TIMG_WDT_PROCPU_RESET_EN    (BIT(13))
+#define TIMG_WDT_PROCPU_RESET_EN_M  (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
+#define TIMG_WDT_PROCPU_RESET_EN_V  0x00000001U
+#define TIMG_WDT_PROCPU_RESET_EN_S  13
+/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
+ *  When set, Flash boot protection is enabled.
+ */
+#define TIMG_WDT_FLASHBOOT_MOD_EN    (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_M  (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
+#define TIMG_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
+#define TIMG_WDT_FLASHBOOT_MOD_EN_S  14
+/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
+ *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
+ *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+ */
+#define TIMG_WDT_SYS_RESET_LENGTH    0x00000007U
+#define TIMG_WDT_SYS_RESET_LENGTH_M  (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
+#define TIMG_WDT_SYS_RESET_LENGTH_V  0x00000007U
+#define TIMG_WDT_SYS_RESET_LENGTH_S  15
+/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
+ *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+ *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+ */
+#define TIMG_WDT_CPU_RESET_LENGTH    0x00000007U
+#define TIMG_WDT_CPU_RESET_LENGTH_M  (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
+#define TIMG_WDT_CPU_RESET_LENGTH_V  0x00000007U
+#define TIMG_WDT_CPU_RESET_LENGTH_S  18
+/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
+ *  update the WDT configuration registers
+ */
+#define TIMG_WDT_CONF_UPDATE_EN    (BIT(22))
+#define TIMG_WDT_CONF_UPDATE_EN_M  (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
+#define TIMG_WDT_CONF_UPDATE_EN_V  0x00000001U
+#define TIMG_WDT_CONF_UPDATE_EN_S  22
+/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
+ *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG3    0x00000003U
+#define TIMG_WDT_STG3_M  (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
+#define TIMG_WDT_STG3_V  0x00000003U
+#define TIMG_WDT_STG3_S  23
+/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
+ *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG2    0x00000003U
+#define TIMG_WDT_STG2_M  (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
+#define TIMG_WDT_STG2_V  0x00000003U
+#define TIMG_WDT_STG2_S  25
+/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
+ *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG1    0x00000003U
+#define TIMG_WDT_STG1_M  (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
+#define TIMG_WDT_STG1_V  0x00000003U
+#define TIMG_WDT_STG1_S  27
+/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
+ *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG0    0x00000003U
+#define TIMG_WDT_STG0_M  (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
+#define TIMG_WDT_STG0_V  0x00000003U
+#define TIMG_WDT_STG0_S  29
+/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
+ *  When set, MWDT is enabled.
+ */
+#define TIMG_WDT_EN    (BIT(31))
+#define TIMG_WDT_EN_M  (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
+#define TIMG_WDT_EN_V  0x00000001U
+#define TIMG_WDT_EN_S  31
+
+/** TIMG_WDTCONFIG1_REG register
+ *  Watchdog timer prescaler register
+ */
+#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c)
+/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
+ *  When set, WDT 's clock divider counter will be reset.
+ */
+#define TIMG_WDT_DIVCNT_RST    (BIT(0))
+#define TIMG_WDT_DIVCNT_RST_M  (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
+#define TIMG_WDT_DIVCNT_RST_V  0x00000001U
+#define TIMG_WDT_DIVCNT_RST_S  0
+/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
+ *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+ *  TIMG_WDT_CLK_PRESCALE.
+ */
+#define TIMG_WDT_CLK_PRESCALE    0x0000FFFFU
+#define TIMG_WDT_CLK_PRESCALE_M  (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
+#define TIMG_WDT_CLK_PRESCALE_V  0x0000FFFFU
+#define TIMG_WDT_CLK_PRESCALE_S  16
+
+/** TIMG_WDTCONFIG2_REG register
+ *  Watchdog timer stage 0 timeout value
+ */
+#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
+/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
+ *  Stage 0 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG0_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG0_HOLD_M  (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
+#define TIMG_WDT_STG0_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG0_HOLD_S  0
+
+/** TIMG_WDTCONFIG3_REG register
+ *  Watchdog timer stage 1 timeout value
+ */
+#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
+/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
+ *  Stage 1 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG1_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG1_HOLD_M  (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
+#define TIMG_WDT_STG1_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG1_HOLD_S  0
+
+/** TIMG_WDTCONFIG4_REG register
+ *  Watchdog timer stage 2 timeout value
+ */
+#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
+/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
+ *  Stage 2 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG2_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG2_HOLD_M  (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
+#define TIMG_WDT_STG2_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG2_HOLD_S  0
+
+/** TIMG_WDTCONFIG5_REG register
+ *  Watchdog timer stage 3 timeout value
+ */
+#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c)
+/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
+ *  Stage 3 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG3_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG3_HOLD_M  (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
+#define TIMG_WDT_STG3_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG3_HOLD_S  0
+
+/** TIMG_WDTFEED_REG register
+ *  Write to feed the watchdog timer
+ */
+#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60)
+/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
+ *  Write any value to feed the MWDT. (WO)
+ */
+#define TIMG_WDT_FEED    0xFFFFFFFFU
+#define TIMG_WDT_FEED_M  (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
+#define TIMG_WDT_FEED_V  0xFFFFFFFFU
+#define TIMG_WDT_FEED_S  0
+
+/** TIMG_WDTWPROTECT_REG register
+ *  Watchdog write protect register
+ */
+#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64)
+/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
+ *  If the register contains a different value than its reset value, write
+ *  protection is enabled.
+ */
+#define TIMG_WDT_WKEY    0xFFFFFFFFU
+#define TIMG_WDT_WKEY_M  (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
+#define TIMG_WDT_WKEY_V  0xFFFFFFFFU
+#define TIMG_WDT_WKEY_S  0
+
+/** TIMG_RTCCALICFG_REG register
+ *  RTC calibration configure register
+ */
+#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
+/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
+ *  0: one-shot frequency calculation,1: periodic frequency calculation,
+ */
+#define TIMG_RTC_CALI_START_CYCLING    (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_M  (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
+#define TIMG_RTC_CALI_START_CYCLING_V  0x00000001U
+#define TIMG_RTC_CALI_START_CYCLING_S  12
+/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
+ *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+ */
+#define TIMG_RTC_CALI_CLK_SEL    0x00000003U
+#define TIMG_RTC_CALI_CLK_SEL_M  (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
+#define TIMG_RTC_CALI_CLK_SEL_V  0x00000003U
+#define TIMG_RTC_CALI_CLK_SEL_S  13
+/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
+ *  indicate one-shot frequency calculation is done.
+ */
+#define TIMG_RTC_CALI_RDY    (BIT(15))
+#define TIMG_RTC_CALI_RDY_M  (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
+#define TIMG_RTC_CALI_RDY_V  0x00000001U
+#define TIMG_RTC_CALI_RDY_S  15
+/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
+ *  Configure the time to calculate RTC slow clock's frequency.
+ */
+#define TIMG_RTC_CALI_MAX    0x00007FFFU
+#define TIMG_RTC_CALI_MAX_M  (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
+#define TIMG_RTC_CALI_MAX_V  0x00007FFFU
+#define TIMG_RTC_CALI_MAX_S  16
+/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start one-shot frequency calculation.
+ */
+#define TIMG_RTC_CALI_START    (BIT(31))
+#define TIMG_RTC_CALI_START_M  (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
+#define TIMG_RTC_CALI_START_V  0x00000001U
+#define TIMG_RTC_CALI_START_S  31
+
+/** TIMG_RTCCALICFG1_REG register
+ *  RTC calibration configure1 register
+ */
+#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c)
+/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
+ *  indicate periodic frequency calculation is done.
+ */
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD    (BIT(0))
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M  (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V  0x00000001U
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S  0
+/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
+ *  When one-shot or periodic frequency calculation is done, read this value to
+ *  calculate RTC slow clock's frequency.
+ */
+#define TIMG_RTC_CALI_VALUE    0x01FFFFFFU
+#define TIMG_RTC_CALI_VALUE_M  (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
+#define TIMG_RTC_CALI_VALUE_V  0x01FFFFFFU
+#define TIMG_RTC_CALI_VALUE_S  7
+
+/** TIMG_INT_ENA_TIMERS_REG register
+ *  Interrupt enable bits
+ */
+#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70)
+/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_ENA    (BIT(0))
+#define TIMG_T0_INT_ENA_M  (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
+#define TIMG_T0_INT_ENA_V  0x00000001U
+#define TIMG_T0_INT_ENA_S  0
+/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_ENA    (BIT(1))
+#define TIMG_T1_INT_ENA_M  (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
+#define TIMG_T1_INT_ENA_V  0x00000001U
+#define TIMG_T1_INT_ENA_S  1
+/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_ENA    (BIT(2))
+#define TIMG_WDT_INT_ENA_M  (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
+#define TIMG_WDT_INT_ENA_V  0x00000001U
+#define TIMG_WDT_INT_ENA_S  2
+
+/** TIMG_INT_RAW_TIMERS_REG register
+ *  Raw interrupt status
+ */
+#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74)
+/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_RAW    (BIT(0))
+#define TIMG_T0_INT_RAW_M  (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
+#define TIMG_T0_INT_RAW_V  0x00000001U
+#define TIMG_T0_INT_RAW_S  0
+/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_RAW    (BIT(1))
+#define TIMG_T1_INT_RAW_M  (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
+#define TIMG_T1_INT_RAW_V  0x00000001U
+#define TIMG_T1_INT_RAW_S  1
+/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_RAW    (BIT(2))
+#define TIMG_WDT_INT_RAW_M  (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
+#define TIMG_WDT_INT_RAW_V  0x00000001U
+#define TIMG_WDT_INT_RAW_S  2
+
+/** TIMG_INT_ST_TIMERS_REG register
+ *  Masked interrupt status
+ */
+#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78)
+/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_ST    (BIT(0))
+#define TIMG_T0_INT_ST_M  (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
+#define TIMG_T0_INT_ST_V  0x00000001U
+#define TIMG_T0_INT_ST_S  0
+/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_ST    (BIT(1))
+#define TIMG_T1_INT_ST_M  (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
+#define TIMG_T1_INT_ST_V  0x00000001U
+#define TIMG_T1_INT_ST_S  1
+/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_ST    (BIT(2))
+#define TIMG_WDT_INT_ST_M  (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
+#define TIMG_WDT_INT_ST_V  0x00000001U
+#define TIMG_WDT_INT_ST_S  2
+
+/** TIMG_INT_CLR_TIMERS_REG register
+ *  Interrupt clear bits
+ */
+#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c)
+/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_CLR    (BIT(0))
+#define TIMG_T0_INT_CLR_M  (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
+#define TIMG_T0_INT_CLR_V  0x00000001U
+#define TIMG_T0_INT_CLR_S  0
+/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_CLR    (BIT(1))
+#define TIMG_T1_INT_CLR_M  (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
+#define TIMG_T1_INT_CLR_V  0x00000001U
+#define TIMG_T1_INT_CLR_S  1
+/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_CLR    (BIT(2))
+#define TIMG_WDT_INT_CLR_M  (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
+#define TIMG_WDT_INT_CLR_V  0x00000001U
+#define TIMG_WDT_INT_CLR_S  2
+
+/** TIMG_RTCCALICFG2_REG register
+ *  Timer group calibration register
+ */
+#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
+/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
+ *  RTC calibration timeout indicator
+ */
+#define TIMG_RTC_CALI_TIMEOUT    (BIT(0))
+#define TIMG_RTC_CALI_TIMEOUT_M  (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
+#define TIMG_RTC_CALI_TIMEOUT_V  0x00000001U
+#define TIMG_RTC_CALI_TIMEOUT_S  0
+/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
+ *  Cycles that release calibration timeout reset
+ */
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT    0x0000000FU
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M  (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V  0x0000000FU
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S  3
+/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
+ *  Threshold value for the RTC calibration timer. If the calibration timer's value
+ *  exceeds this threshold, a timeout is triggered.
+ */
+#define TIMG_RTC_CALI_TIMEOUT_THRES    0x01FFFFFFU
+#define TIMG_RTC_CALI_TIMEOUT_THRES_M  (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
+#define TIMG_RTC_CALI_TIMEOUT_THRES_V  0x01FFFFFFU
+#define TIMG_RTC_CALI_TIMEOUT_THRES_S  7
+
+/** TIMG_NTIMERS_DATE_REG register
+ *  Timer version control register
+ */
+#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8)
+/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
+ *  Timer version control register
+ */
+#define TIMG_NTIMGS_DATE    0x0FFFFFFFU
+#define TIMG_NTIMGS_DATE_M  (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
+#define TIMG_NTIMGS_DATE_V  0x0FFFFFFFU
+#define TIMG_NTIMGS_DATE_S  0
+
+/** TIMG_REGCLK_REG register
+ *  Timer group clock gate register
+ */
+#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc)
+/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
+ *  enable timer's etm task and event
+ */
+#define TIMG_ETM_EN    (BIT(28))
+#define TIMG_ETM_EN_M  (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
+#define TIMG_ETM_EN_V  0x00000001U
+#define TIMG_ETM_EN_S  28
+/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
+ *  Registers can not be read or written to by software.
+ */
+#define TIMG_CLK_EN    (BIT(31))
+#define TIMG_CLK_EN_M  (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
+#define TIMG_CLK_EN_V  0x00000001U
+#define TIMG_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_struct.h
new file mode 100644
index 0000000000..1189b1d491
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_struct.h
@@ -0,0 +1,563 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13422
+
+/** Group: T0 Control and configuration registers */
+/** Type of txconfig register
+ *  Timer x configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 10;
+        /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
+         *  When set, the alarm is enabled. This bit is automatically cleared once an
+         *  alarm occurs.
+         */
+        uint32_t tx_alarm_en: 1;
+        uint32_t reserved_11: 1;
+        /** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
+         *  When set, Timer x 's clock divider counter will be reset.
+         */
+        uint32_t tx_divcnt_rst: 1;
+        /** tx_divider : R/W; bitpos: [28:13]; default: 1;
+         *  Timer x clock (Tx_clk) prescaler value.
+         */
+        uint32_t tx_divider: 16;
+        /** tx_autoreload : R/W; bitpos: [29]; default: 1;
+         *  When set, timer x auto-reload at alarm is enabled.
+         */
+        uint32_t tx_autoreload: 1;
+        /** tx_increase : R/W; bitpos: [30]; default: 1;
+         *  When set, the timer x time-base counter will increment every clock tick. When
+         *  cleared, the timer x time-base counter will decrement.
+         */
+        uint32_t tx_increase: 1;
+        /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
+         *  When set, the timer x time-base counter is enabled.
+         */
+        uint32_t tx_en: 1;
+    };
+    uint32_t val;
+} timg_txconfig_reg_t;
+
+/** Type of txlo register
+ *  Timer x current value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_lo : RO; bitpos: [31:0]; default: 0;
+         *  After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
+         *  of timer x can be read here.
+         */
+        uint32_t tx_lo: 32;
+    };
+    uint32_t val;
+} timg_txlo_reg_t;
+
+/** Type of txhi register
+ *  Timer x current value, high 22 bits
+ */
+typedef union {
+    struct {
+        /** tx_hi : RO; bitpos: [21:0]; default: 0;
+         *  After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
+         *  of timer x can be read here.
+         */
+        uint32_t tx_hi: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} timg_txhi_reg_t;
+
+/** Type of txupdate register
+ *  Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 31;
+        /** tx_update : R/W/SC; bitpos: [31]; default: 0;
+         *  After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
+         */
+        uint32_t tx_update: 1;
+    };
+    uint32_t val;
+} timg_txupdate_reg_t;
+
+/** Type of txalarmlo register
+ *  Timer x alarm value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
+         *  Timer x alarm trigger time-base counter value, low 32 bits.
+         */
+        uint32_t tx_alarm_lo: 32;
+    };
+    uint32_t val;
+} timg_txalarmlo_reg_t;
+
+/** Type of txalarmhi register
+ *  Timer x alarm value, high bits
+ */
+typedef union {
+    struct {
+        /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
+         *  Timer x alarm trigger time-base counter value, high 22 bits.
+         */
+        uint32_t tx_alarm_hi: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} timg_txalarmhi_reg_t;
+
+/** Type of txloadlo register
+ *  Timer x reload value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
+         *  Low 32 bits of the value that a reload will load onto timer x time-base
+         *  Counter.
+         */
+        uint32_t tx_load_lo: 32;
+    };
+    uint32_t val;
+} timg_txloadlo_reg_t;
+
+/** Type of txloadhi register
+ *  Timer x reload value, high 22 bits
+ */
+typedef union {
+    struct {
+        /** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
+         *  High 22 bits of the value that a reload will load onto timer x time-base
+         *  counter.
+         */
+        uint32_t tx_load_hi: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} timg_txloadhi_reg_t;
+
+/** Type of txload register
+ *  Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
+ */
+typedef union {
+    struct {
+        /** tx_load : WT; bitpos: [31:0]; default: 0;
+         *
+         *  Write any value to trigger a timer x time-base counter reload.
+         */
+        uint32_t tx_load: 32;
+    };
+    uint32_t val;
+} timg_txload_reg_t;
+
+/** Group: WDT Control and configuration registers */
+/** Type of wdtconfig0 register
+ *  Watchdog timer configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
+         *  WDT reset CPU enable.
+         */
+        uint32_t wdt_appcpu_reset_en: 1;
+        /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
+         *  WDT reset CPU enable.
+         */
+        uint32_t wdt_procpu_reset_en: 1;
+        /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
+         *  When set, Flash boot protection is enabled.
+         */
+        uint32_t wdt_flashboot_mod_en: 1;
+        /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
+         *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
+         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+         */
+        uint32_t wdt_sys_reset_length: 3;
+        /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
+         *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+         */
+        uint32_t wdt_cpu_reset_length: 3;
+        uint32_t reserved_21: 1;
+        /** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
+         *  update the WDT configuration registers
+         */
+        uint32_t wdt_conf_update_en: 1;
+        /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
+         *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg3: 2;
+        /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
+         *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg2: 2;
+        /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
+         *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg1: 2;
+        /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
+         *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg0: 2;
+        /** wdt_en : R/W; bitpos: [31]; default: 0;
+         *  When set, MWDT is enabled.
+         */
+        uint32_t wdt_en: 1;
+    };
+    uint32_t val;
+} timg_wdtconfig0_reg_t;
+
+/** Type of wdtconfig1 register
+ *  Watchdog timer prescaler register
+ */
+typedef union {
+    struct {
+        /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
+         *  When set, WDT 's clock divider counter will be reset.
+         */
+        uint32_t wdt_divcnt_rst: 1;
+        uint32_t reserved_1: 15;
+        /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
+         *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+         *  TIMG_WDT_CLK_PRESCALE.
+         */
+        uint32_t wdt_clk_prescale: 16;
+    };
+    uint32_t val;
+} timg_wdtconfig1_reg_t;
+
+/** Type of wdtconfig2 register
+ *  Watchdog timer stage 0 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
+         *  Stage 0 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg0_hold: 32;
+    };
+    uint32_t val;
+} timg_wdtconfig2_reg_t;
+
+/** Type of wdtconfig3 register
+ *  Watchdog timer stage 1 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
+         *  Stage 1 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg1_hold: 32;
+    };
+    uint32_t val;
+} timg_wdtconfig3_reg_t;
+
+/** Type of wdtconfig4 register
+ *  Watchdog timer stage 2 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
+         *  Stage 2 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg2_hold: 32;
+    };
+    uint32_t val;
+} timg_wdtconfig4_reg_t;
+
+/** Type of wdtconfig5 register
+ *  Watchdog timer stage 3 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
+         *  Stage 3 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg3_hold: 32;
+    };
+    uint32_t val;
+} timg_wdtconfig5_reg_t;
+
+/** Type of wdtfeed register
+ *  Write to feed the watchdog timer
+ */
+typedef union {
+    struct {
+        /** wdt_feed : WT; bitpos: [31:0]; default: 0;
+         *  Write any value to feed the MWDT. (WO)
+         */
+        uint32_t wdt_feed: 32;
+    };
+    uint32_t val;
+} timg_wdtfeed_reg_t;
+
+/** Type of wdtwprotect register
+ *  Watchdog write protect register
+ */
+typedef union {
+    struct {
+        /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
+         *  If the register contains a different value than its reset value, write
+         *  protection is enabled.
+         */
+        uint32_t wdt_wkey: 32;
+    };
+    uint32_t val;
+} timg_wdtwprotect_reg_t;
+
+/** Group: RTC CALI Control and configuration registers */
+/** Type of rtccalicfg register
+ *  RTC calibration configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
+         *  0: one-shot frequency calculation,1: periodic frequency calculation,
+         */
+        uint32_t rtc_cali_start_cycling: 1;
+        /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
+         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         */
+        uint32_t rtc_cali_clk_sel: 2;
+        /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
+         *  indicate one-shot frequency calculation is done.
+         */
+        uint32_t rtc_cali_rdy: 1;
+        /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
+         *  Configure the time to calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_max: 15;
+        /** rtc_cali_start : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start one-shot frequency calculation.
+         */
+        uint32_t rtc_cali_start: 1;
+    };
+    uint32_t val;
+} timg_rtccalicfg_reg_t;
+
+/** Type of rtccalicfg1 register
+ *  RTC calibration configure1 register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
+         *  indicate periodic frequency calculation is done.
+         */
+        uint32_t rtc_cali_cycling_data_vld: 1;
+        uint32_t reserved_1: 6;
+        /** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
+         *  When one-shot or periodic frequency calculation is done, read this value to
+         *  calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_value: 25;
+    };
+    uint32_t val;
+} timg_rtccalicfg1_reg_t;
+
+/** Type of rtccalicfg2 register
+ *  Timer group calibration register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
+         *  RTC calibration timeout indicator
+         */
+        uint32_t rtc_cali_timeout: 1;
+        uint32_t reserved_1: 2;
+        /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
+         *  Cycles that release calibration timeout reset
+         */
+        uint32_t rtc_cali_timeout_rst_cnt: 4;
+        /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
+         *  Threshold value for the RTC calibration timer. If the calibration timer's value
+         *  exceeds this threshold, a timeout is triggered.
+         */
+        uint32_t rtc_cali_timeout_thres: 25;
+    };
+    uint32_t val;
+} timg_rtccalicfg2_reg_t;
+
+/** Group: Interrupt registers */
+/** Type of int_ena_timers register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** t0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_ena: 1;
+        /** t1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_ena: 1;
+        /** wdt_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_ena: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} timg_int_ena_timers_reg_t;
+
+/** Type of int_raw_timers register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_raw: 1;
+        /** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_raw: 1;
+        /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_raw: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} timg_int_raw_timers_reg_t;
+
+/** Type of int_st_timers register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** t0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_st: 1;
+        /** t1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_st: 1;
+        /** wdt_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_st: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} timg_int_st_timers_reg_t;
+
+/** Type of int_clr_timers register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** t0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_clr: 1;
+        /** t1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_clr: 1;
+        /** wdt_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_clr: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} timg_int_clr_timers_reg_t;
+
+/** Group: Version register */
+/** Type of ntimers_date register
+ *  Timer version control register
+ */
+typedef union {
+    struct {
+        /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
+         *  Timer version control register
+         */
+        uint32_t ntimgs_date: 28;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} timg_ntimers_date_reg_t;
+
+/** Group: Clock configuration registers */
+/** Type of regclk register
+ *  Timer group clock gate register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 28;
+        /** etm_en : R/W; bitpos: [28]; default: 1;
+         *  enable timer's etm task and event
+         */
+        uint32_t etm_en: 1;
+        uint32_t reserved_29: 2;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
+         *  Registers can not be read or written to by software.
+         */
+        uint32_t clk_en: 1;
+    };
+    uint32_t val;
+} timg_regclk_reg_t;
+
+typedef struct {
+    volatile timg_txconfig_reg_t config;
+    volatile timg_txlo_reg_t lo;
+    volatile timg_txhi_reg_t hi;
+    volatile timg_txupdate_reg_t update;
+    volatile timg_txalarmlo_reg_t alarmlo;
+    volatile timg_txalarmhi_reg_t alarmhi;
+    volatile timg_txloadlo_reg_t loadlo;
+    volatile timg_txloadhi_reg_t loadhi;
+    volatile timg_txload_reg_t load;
+} timg_hwtimer_reg_t;
+
+typedef struct timg_dev_t {
+    volatile timg_hwtimer_reg_t hw_timer[2];
+    volatile timg_wdtconfig0_reg_t wdtconfig0;
+    volatile timg_wdtconfig1_reg_t wdtconfig1;
+    volatile timg_wdtconfig2_reg_t wdtconfig2;
+    volatile timg_wdtconfig3_reg_t wdtconfig3;
+    volatile timg_wdtconfig4_reg_t wdtconfig4;
+    volatile timg_wdtconfig5_reg_t wdtconfig5;
+    volatile timg_wdtfeed_reg_t wdtfeed;
+    volatile timg_wdtwprotect_reg_t wdtwprotect;
+    volatile timg_rtccalicfg_reg_t rtccalicfg;
+    volatile timg_rtccalicfg1_reg_t rtccalicfg1;
+    volatile timg_int_ena_timers_reg_t int_ena_timers;
+    volatile timg_int_raw_timers_reg_t int_raw_timers;
+    volatile timg_int_st_timers_reg_t int_st_timers;
+    volatile timg_int_clr_timers_reg_t int_clr_timers;
+    volatile timg_rtccalicfg2_reg_t rtccalicfg2;
+    uint32_t reserved_084[29];
+    volatile timg_ntimers_date_reg_t ntimers_date;
+    volatile timg_regclk_reg_t regclk;
+} timg_dev_t;
+
+extern timg_dev_t TIMERG0;
+extern timg_dev_t TIMERG1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/touch_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/touch_reg.h
new file mode 100644
index 0000000000..d3173425c5
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/touch_reg.h
@@ -0,0 +1,766 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13423
+
+/** RTC_TOUCH_INT_RAW_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_RAW_REG (DR_REG_LP_TOUCH_BASE + 0x0)
+/** RTC_TOUCH_SCAN_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_RAW    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_RAW_M  (RTC_TOUCH_SCAN_DONE_INT_RAW_V << RTC_TOUCH_SCAN_DONE_INT_RAW_S)
+#define RTC_TOUCH_SCAN_DONE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_RAW_S  0
+/** RTC_TOUCH_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_RAW    (BIT(1))
+#define RTC_TOUCH_DONE_INT_RAW_M  (RTC_TOUCH_DONE_INT_RAW_V << RTC_TOUCH_DONE_INT_RAW_S)
+#define RTC_TOUCH_DONE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_RAW_S  1
+/** RTC_TOUCH_ACTIVE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_RAW    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_RAW_M  (RTC_TOUCH_ACTIVE_INT_RAW_V << RTC_TOUCH_ACTIVE_INT_RAW_S)
+#define RTC_TOUCH_ACTIVE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_RAW_S  2
+/** RTC_TOUCH_INACTIVE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_RAW    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_RAW_M  (RTC_TOUCH_INACTIVE_INT_RAW_V << RTC_TOUCH_INACTIVE_INT_RAW_S)
+#define RTC_TOUCH_INACTIVE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_RAW_S  3
+/** RTC_TOUCH_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_RAW    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_RAW_M  (RTC_TOUCH_TIMEOUT_INT_RAW_V << RTC_TOUCH_TIMEOUT_INT_RAW_S)
+#define RTC_TOUCH_TIMEOUT_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_RAW_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S  5
+
+/** RTC_TOUCH_INT_ST_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_ST_REG (DR_REG_LP_TOUCH_BASE + 0x4)
+/** RTC_TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_ST    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_ST_M  (RTC_TOUCH_SCAN_DONE_INT_ST_V << RTC_TOUCH_SCAN_DONE_INT_ST_S)
+#define RTC_TOUCH_SCAN_DONE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_ST_S  0
+/** RTC_TOUCH_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_ST    (BIT(1))
+#define RTC_TOUCH_DONE_INT_ST_M  (RTC_TOUCH_DONE_INT_ST_V << RTC_TOUCH_DONE_INT_ST_S)
+#define RTC_TOUCH_DONE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_ST_S  1
+/** RTC_TOUCH_ACTIVE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_ST    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_ST_M  (RTC_TOUCH_ACTIVE_INT_ST_V << RTC_TOUCH_ACTIVE_INT_ST_S)
+#define RTC_TOUCH_ACTIVE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_ST_S  2
+/** RTC_TOUCH_INACTIVE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_ST    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_ST_M  (RTC_TOUCH_INACTIVE_INT_ST_V << RTC_TOUCH_INACTIVE_INT_ST_S)
+#define RTC_TOUCH_INACTIVE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_ST_S  3
+/** RTC_TOUCH_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_ST    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_ST_M  (RTC_TOUCH_TIMEOUT_INT_ST_V << RTC_TOUCH_TIMEOUT_INT_ST_S)
+#define RTC_TOUCH_TIMEOUT_INT_ST_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_ST_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S  5
+
+/** RTC_TOUCH_INT_ENA_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_ENA_REG (DR_REG_LP_TOUCH_BASE + 0x8)
+/** RTC_TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_ENA    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_ENA_M  (RTC_TOUCH_SCAN_DONE_INT_ENA_V << RTC_TOUCH_SCAN_DONE_INT_ENA_S)
+#define RTC_TOUCH_SCAN_DONE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_ENA_S  0
+/** RTC_TOUCH_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_ENA    (BIT(1))
+#define RTC_TOUCH_DONE_INT_ENA_M  (RTC_TOUCH_DONE_INT_ENA_V << RTC_TOUCH_DONE_INT_ENA_S)
+#define RTC_TOUCH_DONE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_ENA_S  1
+/** RTC_TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_ENA    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_ENA_M  (RTC_TOUCH_ACTIVE_INT_ENA_V << RTC_TOUCH_ACTIVE_INT_ENA_S)
+#define RTC_TOUCH_ACTIVE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_ENA_S  2
+/** RTC_TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_ENA    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_ENA_M  (RTC_TOUCH_INACTIVE_INT_ENA_V << RTC_TOUCH_INACTIVE_INT_ENA_S)
+#define RTC_TOUCH_INACTIVE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_ENA_S  3
+/** RTC_TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_ENA    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_ENA_M  (RTC_TOUCH_TIMEOUT_INT_ENA_V << RTC_TOUCH_TIMEOUT_INT_ENA_S)
+#define RTC_TOUCH_TIMEOUT_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_ENA_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S  5
+
+/** RTC_TOUCH_INT_CLR_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_CLR_REG (DR_REG_LP_TOUCH_BASE + 0xc)
+/** RTC_TOUCH_SCAN_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_CLR    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_CLR_M  (RTC_TOUCH_SCAN_DONE_INT_CLR_V << RTC_TOUCH_SCAN_DONE_INT_CLR_S)
+#define RTC_TOUCH_SCAN_DONE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_CLR_S  0
+/** RTC_TOUCH_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_CLR    (BIT(1))
+#define RTC_TOUCH_DONE_INT_CLR_M  (RTC_TOUCH_DONE_INT_CLR_V << RTC_TOUCH_DONE_INT_CLR_S)
+#define RTC_TOUCH_DONE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_CLR_S  1
+/** RTC_TOUCH_ACTIVE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_CLR    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_CLR_M  (RTC_TOUCH_ACTIVE_INT_CLR_V << RTC_TOUCH_ACTIVE_INT_CLR_S)
+#define RTC_TOUCH_ACTIVE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_CLR_S  2
+/** RTC_TOUCH_INACTIVE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_CLR    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_CLR_M  (RTC_TOUCH_INACTIVE_INT_CLR_V << RTC_TOUCH_INACTIVE_INT_CLR_S)
+#define RTC_TOUCH_INACTIVE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_CLR_S  3
+/** RTC_TOUCH_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_CLR    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_CLR_M  (RTC_TOUCH_TIMEOUT_INT_CLR_V << RTC_TOUCH_TIMEOUT_INT_CLR_S)
+#define RTC_TOUCH_TIMEOUT_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_CLR_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S  5
+
+/** RTC_TOUCH_CHN_STATUS_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_CHN_STATUS_REG (DR_REG_LP_TOUCH_BASE + 0x10)
+/** RTC_TOUCH_PAD_ACTIVE : RO; bitpos: [14:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD_ACTIVE    0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_M  (RTC_TOUCH_PAD_ACTIVE_V << RTC_TOUCH_PAD_ACTIVE_S)
+#define RTC_TOUCH_PAD_ACTIVE_V  0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_S  0
+/** RTC_TOUCH_MEAS_DONE : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_MEAS_DONE    (BIT(15))
+#define RTC_TOUCH_MEAS_DONE_M  (RTC_TOUCH_MEAS_DONE_V << RTC_TOUCH_MEAS_DONE_S)
+#define RTC_TOUCH_MEAS_DONE_V  0x00000001U
+#define RTC_TOUCH_MEAS_DONE_S  15
+/** RTC_TOUCH_SCAN_CURR : RO; bitpos: [19:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_CURR    0x0000000FU
+#define RTC_TOUCH_SCAN_CURR_M  (RTC_TOUCH_SCAN_CURR_V << RTC_TOUCH_SCAN_CURR_S)
+#define RTC_TOUCH_SCAN_CURR_V  0x0000000FU
+#define RTC_TOUCH_SCAN_CURR_S  16
+
+/** RTC_TOUCH_STATUS_0_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_0_REG (DR_REG_LP_TOUCH_BASE + 0x14)
+/** RTC_TOUCH_PAD0_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD0_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD0_DATA_M  (RTC_TOUCH_PAD0_DATA_V << RTC_TOUCH_PAD0_DATA_S)
+#define RTC_TOUCH_PAD0_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD0_DATA_S  0
+/** RTC_TOUCH_PAD0_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD0_DEBOUNCE_CNT_V << RTC_TOUCH_PAD0_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD0_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD0_NEG_NOISE_CNT_V << RTC_TOUCH_PAD0_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_1_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_1_REG (DR_REG_LP_TOUCH_BASE + 0x18)
+/** RTC_TOUCH_PAD1_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD1_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD1_DATA_M  (RTC_TOUCH_PAD1_DATA_V << RTC_TOUCH_PAD1_DATA_S)
+#define RTC_TOUCH_PAD1_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD1_DATA_S  0
+/** RTC_TOUCH_PAD1_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD1_DEBOUNCE_CNT_V << RTC_TOUCH_PAD1_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD1_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD1_NEG_NOISE_CNT_V << RTC_TOUCH_PAD1_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_2_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_2_REG (DR_REG_LP_TOUCH_BASE + 0x1c)
+/** RTC_TOUCH_PAD2_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD2_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD2_DATA_M  (RTC_TOUCH_PAD2_DATA_V << RTC_TOUCH_PAD2_DATA_S)
+#define RTC_TOUCH_PAD2_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD2_DATA_S  0
+/** RTC_TOUCH_PAD2_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD2_DEBOUNCE_CNT_V << RTC_TOUCH_PAD2_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD2_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD2_NEG_NOISE_CNT_V << RTC_TOUCH_PAD2_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_3_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_3_REG (DR_REG_LP_TOUCH_BASE + 0x20)
+/** RTC_TOUCH_PAD3_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD3_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD3_DATA_M  (RTC_TOUCH_PAD3_DATA_V << RTC_TOUCH_PAD3_DATA_S)
+#define RTC_TOUCH_PAD3_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD3_DATA_S  0
+/** RTC_TOUCH_PAD3_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD3_DEBOUNCE_CNT_V << RTC_TOUCH_PAD3_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD3_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD3_NEG_NOISE_CNT_V << RTC_TOUCH_PAD3_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_4_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_4_REG (DR_REG_LP_TOUCH_BASE + 0x24)
+/** RTC_TOUCH_PAD4_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD4_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD4_DATA_M  (RTC_TOUCH_PAD4_DATA_V << RTC_TOUCH_PAD4_DATA_S)
+#define RTC_TOUCH_PAD4_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD4_DATA_S  0
+/** RTC_TOUCH_PAD4_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD4_DEBOUNCE_CNT_V << RTC_TOUCH_PAD4_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD4_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD4_NEG_NOISE_CNT_V << RTC_TOUCH_PAD4_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_5_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_5_REG (DR_REG_LP_TOUCH_BASE + 0x28)
+/** RTC_TOUCH_PAD5_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD5_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD5_DATA_M  (RTC_TOUCH_PAD5_DATA_V << RTC_TOUCH_PAD5_DATA_S)
+#define RTC_TOUCH_PAD5_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD5_DATA_S  0
+/** RTC_TOUCH_PAD5_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD5_DEBOUNCE_CNT_V << RTC_TOUCH_PAD5_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD5_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD5_NEG_NOISE_CNT_V << RTC_TOUCH_PAD5_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_6_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_6_REG (DR_REG_LP_TOUCH_BASE + 0x2c)
+/** RTC_TOUCH_PAD6_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD6_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD6_DATA_M  (RTC_TOUCH_PAD6_DATA_V << RTC_TOUCH_PAD6_DATA_S)
+#define RTC_TOUCH_PAD6_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD6_DATA_S  0
+/** RTC_TOUCH_PAD6_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD6_DEBOUNCE_CNT_V << RTC_TOUCH_PAD6_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD6_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD6_NEG_NOISE_CNT_V << RTC_TOUCH_PAD6_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_7_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_7_REG (DR_REG_LP_TOUCH_BASE + 0x30)
+/** RTC_TOUCH_PAD7_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD7_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD7_DATA_M  (RTC_TOUCH_PAD7_DATA_V << RTC_TOUCH_PAD7_DATA_S)
+#define RTC_TOUCH_PAD7_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD7_DATA_S  0
+/** RTC_TOUCH_PAD7_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD7_DEBOUNCE_CNT_V << RTC_TOUCH_PAD7_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD7_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD7_NEG_NOISE_CNT_V << RTC_TOUCH_PAD7_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_8_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_8_REG (DR_REG_LP_TOUCH_BASE + 0x34)
+/** RTC_TOUCH_PAD8_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD8_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD8_DATA_M  (RTC_TOUCH_PAD8_DATA_V << RTC_TOUCH_PAD8_DATA_S)
+#define RTC_TOUCH_PAD8_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD8_DATA_S  0
+/** RTC_TOUCH_PAD8_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD8_DEBOUNCE_CNT_V << RTC_TOUCH_PAD8_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD8_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD8_NEG_NOISE_CNT_V << RTC_TOUCH_PAD8_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_9_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_9_REG (DR_REG_LP_TOUCH_BASE + 0x38)
+/** RTC_TOUCH_PAD9_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD9_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD9_DATA_M  (RTC_TOUCH_PAD9_DATA_V << RTC_TOUCH_PAD9_DATA_S)
+#define RTC_TOUCH_PAD9_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD9_DATA_S  0
+/** RTC_TOUCH_PAD9_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD9_DEBOUNCE_CNT_V << RTC_TOUCH_PAD9_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD9_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD9_NEG_NOISE_CNT_V << RTC_TOUCH_PAD9_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_10_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_10_REG (DR_REG_LP_TOUCH_BASE + 0x3c)
+/** RTC_TOUCH_PAD10_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD10_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD10_DATA_M  (RTC_TOUCH_PAD10_DATA_V << RTC_TOUCH_PAD10_DATA_S)
+#define RTC_TOUCH_PAD10_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD10_DATA_S  0
+/** RTC_TOUCH_PAD10_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD10_DEBOUNCE_CNT_V << RTC_TOUCH_PAD10_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD10_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD10_NEG_NOISE_CNT_V << RTC_TOUCH_PAD10_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_11_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_11_REG (DR_REG_LP_TOUCH_BASE + 0x40)
+/** RTC_TOUCH_PAD11_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD11_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD11_DATA_M  (RTC_TOUCH_PAD11_DATA_V << RTC_TOUCH_PAD11_DATA_S)
+#define RTC_TOUCH_PAD11_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD11_DATA_S  0
+/** RTC_TOUCH_PAD11_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD11_DEBOUNCE_CNT_V << RTC_TOUCH_PAD11_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD11_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD11_NEG_NOISE_CNT_V << RTC_TOUCH_PAD11_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_12_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_12_REG (DR_REG_LP_TOUCH_BASE + 0x44)
+/** RTC_TOUCH_PAD12_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD12_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD12_DATA_M  (RTC_TOUCH_PAD12_DATA_V << RTC_TOUCH_PAD12_DATA_S)
+#define RTC_TOUCH_PAD12_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD12_DATA_S  0
+/** RTC_TOUCH_PAD12_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD12_DEBOUNCE_CNT_V << RTC_TOUCH_PAD12_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD12_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD12_NEG_NOISE_CNT_V << RTC_TOUCH_PAD12_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_13_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_13_REG (DR_REG_LP_TOUCH_BASE + 0x48)
+/** RTC_TOUCH_PAD13_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD13_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD13_DATA_M  (RTC_TOUCH_PAD13_DATA_V << RTC_TOUCH_PAD13_DATA_S)
+#define RTC_TOUCH_PAD13_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD13_DATA_S  0
+/** RTC_TOUCH_PAD13_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD13_DEBOUNCE_CNT_V << RTC_TOUCH_PAD13_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD13_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD13_NEG_NOISE_CNT_V << RTC_TOUCH_PAD13_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_14_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_14_REG (DR_REG_LP_TOUCH_BASE + 0x4c)
+/** RTC_TOUCH_PAD14_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD14_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD14_DATA_M  (RTC_TOUCH_PAD14_DATA_V << RTC_TOUCH_PAD14_DATA_S)
+#define RTC_TOUCH_PAD14_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD14_DATA_S  0
+/** RTC_TOUCH_PAD14_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD14_DEBOUNCE_CNT_V << RTC_TOUCH_PAD14_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD14_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD14_NEG_NOISE_CNT_V << RTC_TOUCH_PAD14_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_15_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_15_REG (DR_REG_LP_TOUCH_BASE + 0x50)
+/** RTC_TOUCH_SLP_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_DATA    0x0000FFFFU
+#define RTC_TOUCH_SLP_DATA_M  (RTC_TOUCH_SLP_DATA_V << RTC_TOUCH_SLP_DATA_S)
+#define RTC_TOUCH_SLP_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_SLP_DATA_S  0
+/** RTC_TOUCH_SLP_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT_M  (RTC_TOUCH_SLP_DEBOUNCE_CNT_V << RTC_TOUCH_SLP_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_SLP_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT_M  (RTC_TOUCH_SLP_NEG_NOISE_CNT_V << RTC_TOUCH_SLP_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_16_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_16_REG (DR_REG_LP_TOUCH_BASE + 0x54)
+/** RTC_TOUCH_APPROACH_PAD2_CNT : RO; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_PAD2_CNT    0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD2_CNT_M  (RTC_TOUCH_APPROACH_PAD2_CNT_V << RTC_TOUCH_APPROACH_PAD2_CNT_S)
+#define RTC_TOUCH_APPROACH_PAD2_CNT_V  0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD2_CNT_S  0
+/** RTC_TOUCH_APPROACH_PAD1_CNT : RO; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_PAD1_CNT    0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD1_CNT_M  (RTC_TOUCH_APPROACH_PAD1_CNT_V << RTC_TOUCH_APPROACH_PAD1_CNT_S)
+#define RTC_TOUCH_APPROACH_PAD1_CNT_V  0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD1_CNT_S  8
+/** RTC_TOUCH_APPROACH_PAD0_CNT : RO; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_PAD0_CNT    0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD0_CNT_M  (RTC_TOUCH_APPROACH_PAD0_CNT_V << RTC_TOUCH_APPROACH_PAD0_CNT_S)
+#define RTC_TOUCH_APPROACH_PAD0_CNT_V  0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD0_CNT_S  16
+/** RTC_TOUCH_SLP_APPROACH_CNT : RO; bitpos: [31:24]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_APPROACH_CNT    0x000000FFU
+#define RTC_TOUCH_SLP_APPROACH_CNT_M  (RTC_TOUCH_SLP_APPROACH_CNT_V << RTC_TOUCH_SLP_APPROACH_CNT_S)
+#define RTC_TOUCH_SLP_APPROACH_CNT_V  0x000000FFU
+#define RTC_TOUCH_SLP_APPROACH_CNT_S  24
+
+/** RTC_TOUCH_STATUS_17_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_17_REG (DR_REG_LP_TOUCH_BASE + 0x58)
+/** RTC_TOUCH_DCAP_LPF : RO; bitpos: [6:0]; default: 0;
+ *  Reserved
+ */
+#define RTC_TOUCH_DCAP_LPF    0x0000007FU
+#define RTC_TOUCH_DCAP_LPF_M  (RTC_TOUCH_DCAP_LPF_V << RTC_TOUCH_DCAP_LPF_S)
+#define RTC_TOUCH_DCAP_LPF_V  0x0000007FU
+#define RTC_TOUCH_DCAP_LPF_S  0
+/** RTC_TOUCH_DRES_LPF : RO; bitpos: [8:7]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DRES_LPF    0x00000003U
+#define RTC_TOUCH_DRES_LPF_M  (RTC_TOUCH_DRES_LPF_V << RTC_TOUCH_DRES_LPF_S)
+#define RTC_TOUCH_DRES_LPF_V  0x00000003U
+#define RTC_TOUCH_DRES_LPF_S  7
+/** RTC_TOUCH_DRV_LS : RO; bitpos: [12:9]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DRV_LS    0x0000000FU
+#define RTC_TOUCH_DRV_LS_M  (RTC_TOUCH_DRV_LS_V << RTC_TOUCH_DRV_LS_S)
+#define RTC_TOUCH_DRV_LS_V  0x0000000FU
+#define RTC_TOUCH_DRV_LS_S  9
+/** RTC_TOUCH_DRV_HS : RO; bitpos: [17:13]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DRV_HS    0x0000001FU
+#define RTC_TOUCH_DRV_HS_M  (RTC_TOUCH_DRV_HS_V << RTC_TOUCH_DRV_HS_S)
+#define RTC_TOUCH_DRV_HS_V  0x0000001FU
+#define RTC_TOUCH_DRV_HS_S  13
+/** RTC_TOUCH_DBIAS : RO; bitpos: [22:18]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DBIAS    0x0000001FU
+#define RTC_TOUCH_DBIAS_M  (RTC_TOUCH_DBIAS_V << RTC_TOUCH_DBIAS_S)
+#define RTC_TOUCH_DBIAS_V  0x0000001FU
+#define RTC_TOUCH_DBIAS_S  18
+/** RTC_TOUCH_FREQ_SCAN_CNT : RO; bitpos: [24:23]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_FREQ_SCAN_CNT    0x00000003U
+#define RTC_TOUCH_FREQ_SCAN_CNT_M  (RTC_TOUCH_FREQ_SCAN_CNT_V << RTC_TOUCH_FREQ_SCAN_CNT_S)
+#define RTC_TOUCH_FREQ_SCAN_CNT_V  0x00000003U
+#define RTC_TOUCH_FREQ_SCAN_CNT_S  23
+
+/** RTC_TOUCH_CHN_TMP_STATUS_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_CHN_TMP_STATUS_REG (DR_REG_LP_TOUCH_BASE + 0x5c)
+/** RTC_TOUCH_PAD_INACTIVE_STATUS : RO; bitpos: [14:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD_INACTIVE_STATUS    0x00007FFFU
+#define RTC_TOUCH_PAD_INACTIVE_STATUS_M  (RTC_TOUCH_PAD_INACTIVE_STATUS_V << RTC_TOUCH_PAD_INACTIVE_STATUS_S)
+#define RTC_TOUCH_PAD_INACTIVE_STATUS_V  0x00007FFFU
+#define RTC_TOUCH_PAD_INACTIVE_STATUS_S  0
+/** RTC_TOUCH_PAD_ACTIVE_STATUS : RO; bitpos: [29:15]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD_ACTIVE_STATUS    0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_STATUS_M  (RTC_TOUCH_PAD_ACTIVE_STATUS_V << RTC_TOUCH_PAD_ACTIVE_STATUS_S)
+#define RTC_TOUCH_PAD_ACTIVE_STATUS_V  0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_STATUS_S  15
+
+/** RTC_TOUCH_DATE_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_DATE_REG (DR_REG_LP_TOUCH_BASE + 0x100)
+/** RTC_TOUCH_DATE : R/W; bitpos: [27:0]; default: 2294548;
+ *  need_des
+ */
+#define RTC_TOUCH_DATE    0x0FFFFFFFU
+#define RTC_TOUCH_DATE_M  (RTC_TOUCH_DATE_V << RTC_TOUCH_DATE_S)
+#define RTC_TOUCH_DATE_V  0x0FFFFFFFU
+#define RTC_TOUCH_DATE_S  0
+/** RTC_TOUCH_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_CLK_EN    (BIT(31))
+#define RTC_TOUCH_CLK_EN_M  (RTC_TOUCH_CLK_EN_V << RTC_TOUCH_CLK_EN_S)
+#define RTC_TOUCH_CLK_EN_V  0x00000001U
+#define RTC_TOUCH_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/touch_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/touch_struct.h
new file mode 100644
index 0000000000..876919bf98
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/touch_struct.h
@@ -0,0 +1,339 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13423
+
+/** Group: configure_register */
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_raw:1;
+        /** done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_raw:1;
+        /** active_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_raw:1;
+        /** inactive_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_raw:1;
+        /** timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_raw:1;
+        /** approach_loop_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_st : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_st:1;
+        /** done_int_st : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_st:1;
+        /** active_int_st : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_st:1;
+        /** inactive_int_st : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_st:1;
+        /** timeout_int_st : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_st:1;
+        /** approach_loop_done_int_st : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_ena:1;
+        /** done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_ena:1;
+        /** active_int_ena : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_ena:1;
+        /** inactive_int_ena : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_ena:1;
+        /** timeout_int_ena : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_ena:1;
+        /** approach_loop_done_int_ena : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_clr:1;
+        /** done_int_clr : WT; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_clr:1;
+        /** active_int_clr : WT; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_clr:1;
+        /** inactive_int_clr : WT; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_clr:1;
+        /** timeout_int_clr : WT; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_clr:1;
+        /** approach_loop_done_int_clr : WT; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_clr_reg_t;
+
+/** Type of chn_status register
+ *  Latched channel status
+ */
+typedef union {
+    struct {
+        /** pad_active : RO; bitpos: [14:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_active:15;
+        /** meas_done : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t meas_done:1;
+        /** scan_curr : RO; bitpos: [19:16]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_curr:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} rtc_touch_chn_status_reg_t;
+
+/** Type of chn_data register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_data:16;
+        /** pad_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_debounce_cnt:3;
+        /** pad_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_chn_data_reg_t;
+
+/** Type of slp_ch_data register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** slp_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_data:16;
+        /** slp_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_debounce_cnt:3;
+        /** slp_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_slp_ch_data_reg_t;
+
+/** Type of aprch_ch_data register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** approach_pad2_cnt : RO; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_pad2_cnt:8;
+        /** approach_pad1_cnt : RO; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_pad1_cnt:8;
+        /** approach_pad0_cnt : RO; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_pad0_cnt:8;
+        /** slp_approach_cnt : RO; bitpos: [31:24]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_approach_cnt:8;
+    };
+    uint32_t val;
+} rtc_touch_aprch_ch_data_reg_t;
+
+/** Type of config register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dcap_lpf : RO; bitpos: [6:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t dcap_lpf:7;
+        /** dres_lpf : RO; bitpos: [8:7]; default: 0;
+         *  need_des
+         */
+        uint32_t dres_lpf:2;
+        /** drv_ls : RO; bitpos: [12:9]; default: 0;
+         *  need_des
+         */
+        uint32_t drv_ls:4;
+        /** drv_hs : RO; bitpos: [17:13]; default: 0;
+         *  need_des
+         */
+        uint32_t drv_hs:5;
+        /** dbias : RO; bitpos: [22:18]; default: 0;
+         *  need_des
+         */
+        uint32_t dbias:5;
+        /** freq_scan_cnt : RO; bitpos: [24:23]; default: 0;
+         *  need_des
+         */
+        uint32_t freq_scan_cnt:2;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} rtc_touch_sample_status_reg_t;
+
+/** Type of chn_tmp_status register
+ *  Realtime channel status
+ */
+typedef union {
+    struct {
+        /** pad_inactive_status : RO; bitpos: [14:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_inactive_status:15;
+        /** pad_active_status : RO; bitpos: [29:15]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_active_status:15;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} rtc_touch_chn_tmp_status_reg_t;
+
+
+/** Group: Version */
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2294548;
+         *  need_des
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:3;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} rtc_touch_date_reg_t;
+
+
+typedef struct {
+    volatile rtc_touch_int_raw_reg_t int_raw;
+    volatile rtc_touch_int_st_reg_t int_st;
+    volatile rtc_touch_int_ena_reg_t int_ena;
+    volatile rtc_touch_int_clr_reg_t int_clr;
+    volatile rtc_touch_chn_status_reg_t chn_status;
+    volatile rtc_touch_chn_data_reg_t chn_data[15];
+    volatile rtc_touch_slp_ch_data_reg_t slp_ch_data;
+    volatile rtc_touch_aprch_ch_data_reg_t aprch_ch_data;
+    volatile rtc_touch_sample_status_reg_t sample_status;
+    volatile rtc_touch_chn_tmp_status_reg_t chn_tmp_status;
+    uint32_t reserved_060[40];
+    volatile rtc_touch_date_reg_t date;
+} rtc_touch_dev_t;
+
+extern rtc_touch_dev_t LP_TOUCH;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rtc_touch_dev_t) == 0x104, "Invalid size of rtc_touch_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/trace_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/trace_reg.h
new file mode 100644
index 0000000000..2cf87ac019
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/trace_reg.h
@@ -0,0 +1,503 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TRACE_MEM_START_ADDR_REG register
+ *  mem start addr
+ */
+#define TRACE_MEM_START_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x0)
+/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of trace memory
+ */
+#define TRACE_MEM_START_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_START_ADDR_M  (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S)
+#define TRACE_MEM_START_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_START_ADDR_S  0
+
+/** TRACE_MEM_END_ADDR_REG register
+ *  mem end addr
+ */
+#define TRACE_MEM_END_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x4)
+/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The end address of trace memory
+ */
+#define TRACE_MEM_END_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_M  (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
+#define TRACE_MEM_END_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_S  0
+
+/** TRACE_MEM_CURRENT_ADDR_REG register
+ *  mem current addr
+ */
+#define TRACE_MEM_CURRENT_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x8)
+/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  current_mem_addr,indicate that next writing addr
+ */
+#define TRACE_MEM_CURRENT_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_M  (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
+#define TRACE_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_S  0
+
+/** TRACE_MEM_ADDR_UPDATE_REG register
+ *  mem addr update
+ */
+#define TRACE_MEM_ADDR_UPDATE_REG(i) (DR_REG_TRACE_BASE(i) + 0xc)
+/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
+ *  when set, the  will
+ *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to
+ *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
+ */
+#define TRACE_MEM_CURRENT_ADDR_UPDATE    (BIT(0))
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_M  (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_V  0x00000001U
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_S  0
+
+/** TRACE_FIFO_STATUS_REG register
+ *  fifo status register
+ */
+#define TRACE_FIFO_STATUS_REG(i) (DR_REG_TRACE_BASE(i) + 0x10)
+/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  Represent whether the fifo is empty.
+ *  1: empty
+ *  0: not empty
+ */
+#define TRACE_FIFO_EMPTY    (BIT(0))
+#define TRACE_FIFO_EMPTY_M  (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
+#define TRACE_FIFO_EMPTY_V  0x00000001U
+#define TRACE_FIFO_EMPTY_S  0
+/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
+ *  Represent trace work status:
+ *  0: idle state
+ *  1: working state
+ *  2: wait state due to hart halted or havereset
+ *  3: lost state
+ */
+#define TRACE_WORK_STATUS    0x00000003U
+#define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
+#define TRACE_WORK_STATUS_V  0x00000003U
+#define TRACE_WORK_STATUS_S  1
+
+/** TRACE_INTR_ENA_REG register
+ *  interrupt enable register
+ */
+#define TRACE_INTR_ENA_REG(i) (DR_REG_TRACE_BASE(i) + 0x14)
+/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set 1 enable fifo_overflow interrupt
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_ENA    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_M  (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_S  0
+/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Set 1 enable mem_full interrupt
+ */
+#define TRACE_MEM_FULL_INTR_ENA    (BIT(1))
+#define TRACE_MEM_FULL_INTR_ENA_M  (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
+#define TRACE_MEM_FULL_INTR_ENA_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_ENA_S  1
+
+/** TRACE_INTR_RAW_REG register
+ *  interrupt status register
+ */
+#define TRACE_INTR_RAW_REG(i) (DR_REG_TRACE_BASE(i) + 0x18)
+/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
+ *  fifo_overflow interrupt status
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_RAW    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_M  (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_S  0
+/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
+ *  mem_full interrupt status
+ */
+#define TRACE_MEM_FULL_INTR_RAW    (BIT(1))
+#define TRACE_MEM_FULL_INTR_RAW_M  (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
+#define TRACE_MEM_FULL_INTR_RAW_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_RAW_S  1
+
+/** TRACE_INTR_CLR_REG register
+ *  interrupt clear register
+ */
+#define TRACE_INTR_CLR_REG(i) (DR_REG_TRACE_BASE(i) + 0x1c)
+/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
+ *  Set 1 clear fifo overflow interrupt
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_CLR    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_M  (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_S  0
+/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
+ *  Set 1 clear mem full interrupt
+ */
+#define TRACE_MEM_FULL_INTR_CLR    (BIT(1))
+#define TRACE_MEM_FULL_INTR_CLR_M  (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
+#define TRACE_MEM_FULL_INTR_CLR_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_CLR_S  1
+
+/** TRACE_TRIGGER_REG register
+ *  trigger register
+ */
+#define TRACE_TRIGGER_REG(i) (DR_REG_TRACE_BASE(i) + 0x20)
+/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
+ *  Configure whether or not start trace.
+ *  1: start trace
+ *  0: invalid
+ */
+#define TRACE_TRIGGER_ON    (BIT(0))
+#define TRACE_TRIGGER_ON_M  (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
+#define TRACE_TRIGGER_ON_V  0x00000001U
+#define TRACE_TRIGGER_ON_S  0
+/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
+ *  Configure whether or not stop trace.
+ *  1: stop trace
+ *  0: invalid
+ */
+#define TRACE_TRIGGER_OFF    (BIT(1))
+#define TRACE_TRIGGER_OFF_M  (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
+#define TRACE_TRIGGER_OFF_V  0x00000001U
+#define TRACE_TRIGGER_OFF_S  1
+/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
+ *  Configure memory loop mode.
+ *  1: trace will loop write trace_mem.
+ *  0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr
+ */
+#define TRACE_MEM_LOOP    (BIT(2))
+#define TRACE_MEM_LOOP_M  (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
+#define TRACE_MEM_LOOP_V  0x00000001U
+#define TRACE_MEM_LOOP_S  2
+/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
+ *  Configure whether or not enable auto-restart.
+ *  1: enable
+ *  0: disable
+ */
+#define TRACE_RESTART_ENA    (BIT(3))
+#define TRACE_RESTART_ENA_M  (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
+#define TRACE_RESTART_ENA_V  0x00000001U
+#define TRACE_RESTART_ENA_S  3
+
+/** TRACE_CONFIG_REG register
+ *  trace configuration register
+ */
+#define TRACE_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x24)
+/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configure whether or not enable cpu trigger action.
+ *  1: enable
+ *  0:disable
+ */
+#define TRACE_DM_TRIGGER_ENA    (BIT(0))
+#define TRACE_DM_TRIGGER_ENA_M  (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S)
+#define TRACE_DM_TRIGGER_ENA_V  0x00000001U
+#define TRACE_DM_TRIGGER_ENA_S  0
+/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not enable trace cpu haverest, when enabled, if cpu have
+ *  reset, the encoder will output a packet to report the address of the last
+ *  instruction, and upon reset deassertion, the encoder start again.
+ *  1: enabled
+ *  0: disabled
+ */
+#define TRACE_RESET_ENA    (BIT(1))
+#define TRACE_RESET_ENA_M  (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S)
+#define TRACE_RESET_ENA_V  0x00000001U
+#define TRACE_RESET_ENA_S  1
+/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Configure whether or not enable trace cpu is halted, when enabled, if the cpu
+ *  halted, the encoder will output a packet to report the address of the last
+ *  instruction, and upon halted deassertion, the encoder start again.When disabled,
+ *  encoder will not report the last address before halted and first address after
+ *  halted, cpu halted information will not be tracked.
+ *  1: enabled
+ *  0: disabled
+ */
+#define TRACE_HALT_ENA    (BIT(2))
+#define TRACE_HALT_ENA_M  (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S)
+#define TRACE_HALT_ENA_V  0x00000001U
+#define TRACE_HALT_ENA_S  2
+/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0;
+ *  Configure whether or not enable stall cpu. When enabled, when the fifo almost full,
+ *  the cpu will be stalled until the packets is able to write to fifo.
+ *  1: enabled.
+ *  0: disabled
+ */
+#define TRACE_STALL_ENA    (BIT(3))
+#define TRACE_STALL_ENA_M  (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S)
+#define TRACE_STALL_ENA_V  0x00000001U
+#define TRACE_STALL_ENA_S  3
+/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0;
+ *  Configure whether or not enable full-address mode.
+ *  1: full address mode.
+ *  0: delta address mode
+ */
+#define TRACE_FULL_ADDRESS    (BIT(4))
+#define TRACE_FULL_ADDRESS_M  (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S)
+#define TRACE_FULL_ADDRESS_V  0x00000001U
+#define TRACE_FULL_ADDRESS_S  4
+/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
+ *  Configure whether or not enable implicit exception mode. When enabled,, do not sent
+ *  exception address, only exception cause in exception packets.
+ *  1: enabled
+ *  0: disabled
+ */
+#define TRACE_IMPLICIT_EXCEPT    (BIT(5))
+#define TRACE_IMPLICIT_EXCEPT_M  (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S)
+#define TRACE_IMPLICIT_EXCEPT_V  0x00000001U
+#define TRACE_IMPLICIT_EXCEPT_S  5
+
+/** TRACE_FILTER_CONTROL_REG register
+ *  filter control register
+ */
+#define TRACE_FILTER_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x28)
+/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether or not enable filter unit.
+ *  1: enable filter.
+ *  0: always match
+ */
+#define TRACE_FILTER_EN    (BIT(0))
+#define TRACE_FILTER_EN_M  (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S)
+#define TRACE_FILTER_EN_V  0x00000001U
+#define TRACE_FILTER_EN_S  0
+/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0;
+ *  when set, the comparator must be high in order for the filter to match
+ */
+#define TRACE_MATCH_COMP    (BIT(1))
+#define TRACE_MATCH_COMP_M  (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S)
+#define TRACE_MATCH_COMP_V  0x00000001U
+#define TRACE_MATCH_COMP_S  1
+/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0;
+ *  when set, match privilege levels specified by
+ *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
+ */
+#define TRACE_MATCH_PRIVILEGE    (BIT(2))
+#define TRACE_MATCH_PRIVILEGE_M  (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S)
+#define TRACE_MATCH_PRIVILEGE_V  0x00000001U
+#define TRACE_MATCH_PRIVILEGE_S  2
+/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0;
+ *  when set, start matching from exception cause codes specified by
+ *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
+ *  matching upon return from the 1st matching exception.
+ */
+#define TRACE_MATCH_ECAUSE    (BIT(3))
+#define TRACE_MATCH_ECAUSE_M  (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S)
+#define TRACE_MATCH_ECAUSE_V  0x00000001U
+#define TRACE_MATCH_ECAUSE_S  3
+/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0;
+ *  when set, start matching from a trap with the interrupt level codes specified by
+ *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
+ *  stop matching upon return from the 1st matching trap.
+ */
+#define TRACE_MATCH_INTERRUPT    (BIT(4))
+#define TRACE_MATCH_INTERRUPT_M  (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S)
+#define TRACE_MATCH_INTERRUPT_V  0x00000001U
+#define TRACE_MATCH_INTERRUPT_S  4
+
+/** TRACE_FILTER_MATCH_CONTROL_REG register
+ *  filter match control register
+ */
+#define TRACE_FILTER_MATCH_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x2c)
+/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0;
+ *  Select match which privilege level when
+ *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set.
+ *  1: machine mode.
+ *  0: user mode
+ */
+#define TRACE_MATCH_CHOICE_PRIVILEGE    (BIT(0))
+#define TRACE_MATCH_CHOICE_PRIVILEGE_M  (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S)
+#define TRACE_MATCH_CHOICE_PRIVILEGE_V  0x00000001U
+#define TRACE_MATCH_CHOICE_PRIVILEGE_S  0
+/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0;
+ *  Select which match which itype when
+ *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set.
+ *  1: match itype of 2.
+ *  0: match itype or 1.
+ */
+#define TRACE_MATCH_VALUE_INTERRUPT    (BIT(1))
+#define TRACE_MATCH_VALUE_INTERRUPT_M  (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S)
+#define TRACE_MATCH_VALUE_INTERRUPT_V  0x00000001U
+#define TRACE_MATCH_VALUE_INTERRUPT_S  1
+/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0;
+ *  specified which ecause matched.
+ */
+#define TRACE_MATCH_CHOICE_ECAUSE    0x0000003FU
+#define TRACE_MATCH_CHOICE_ECAUSE_M  (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S)
+#define TRACE_MATCH_CHOICE_ECAUSE_V  0x0000003FU
+#define TRACE_MATCH_CHOICE_ECAUSE_S  2
+
+/** TRACE_FILTER_COMPARATOR_CONTROL_REG register
+ *  filter comparator match control register
+ */
+#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x30)
+/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0;
+ *  Determines which input to compare against the primary comparator,
+ *  0: iaddr,
+ *  1: tval.
+ */
+#define TRACE_P_INPUT    (BIT(0))
+#define TRACE_P_INPUT_M  (TRACE_P_INPUT_V << TRACE_P_INPUT_S)
+#define TRACE_P_INPUT_V  0x00000001U
+#define TRACE_P_INPUT_S  0
+/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0;
+ *  Select the primary comparator function.
+ *  0: equal,
+ *  1: not equal,
+ *  2: less than,
+ *  3: less than or equal,
+ *  4: greater than,
+ *  5: greater than or equal,
+ *  other: always match
+ */
+#define TRACE_P_FUNCTION    0x00000007U
+#define TRACE_P_FUNCTION_M  (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S)
+#define TRACE_P_FUNCTION_V  0x00000007U
+#define TRACE_P_FUNCTION_S  2
+/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0;
+ *  Generate a trace packet explicitly reporting the address that cause the primary
+ *  match
+ */
+#define TRACE_P_NOTIFY    (BIT(5))
+#define TRACE_P_NOTIFY_M  (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S)
+#define TRACE_P_NOTIFY_V  0x00000001U
+#define TRACE_P_NOTIFY_S  5
+/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0;
+ *  Determines which input to compare against the secondary comparator,
+ *  0: iaddr,
+ *  1: tval.
+ */
+#define TRACE_S_INPUT    (BIT(8))
+#define TRACE_S_INPUT_M  (TRACE_S_INPUT_V << TRACE_S_INPUT_S)
+#define TRACE_S_INPUT_V  0x00000001U
+#define TRACE_S_INPUT_S  8
+/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0;
+ *  Select the secondary comparator function.
+ *  0: equal,
+ *  1: not equal,
+ *  2: less than,
+ *  3: less than or equal,
+ *  4: greater than,
+ *  5: greater than or equal,
+ *  other: always match
+ */
+#define TRACE_S_FUNCTION    0x00000007U
+#define TRACE_S_FUNCTION_M  (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S)
+#define TRACE_S_FUNCTION_V  0x00000007U
+#define TRACE_S_FUNCTION_S  10
+/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0;
+ *  Generate a trace packet explicitly reporting the address that cause the secondary
+ *  match
+ */
+#define TRACE_S_NOTIFY    (BIT(13))
+#define TRACE_S_NOTIFY_M  (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S)
+#define TRACE_S_NOTIFY_V  0x00000001U
+#define TRACE_S_NOTIFY_S  13
+/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0;
+ *  0: only primary matches,
+ *  1: primary and secondary comparator both matches(P\&\&S),
+ *  2:either primary or secondary comparator matches !(P\&\&S),
+ *  3: set when primary matches and continue to match until after secondary comparator
+ *  matches
+ */
+#define TRACE_MATCH_MODE    0x00000003U
+#define TRACE_MATCH_MODE_M  (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S)
+#define TRACE_MATCH_MODE_V  0x00000003U
+#define TRACE_MATCH_MODE_S  16
+
+/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register
+ *  primary comparator match value
+ */
+#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x34)
+/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0;
+ *  primary comparator match value
+ */
+#define TRACE_P_MATCH    0xFFFFFFFFU
+#define TRACE_P_MATCH_M  (TRACE_P_MATCH_V << TRACE_P_MATCH_S)
+#define TRACE_P_MATCH_V  0xFFFFFFFFU
+#define TRACE_P_MATCH_S  0
+
+/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register
+ *  secondary comparator match value
+ */
+#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x38)
+/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0;
+ *  secondary comparator match value
+ */
+#define TRACE_S_MATCH    0xFFFFFFFFU
+#define TRACE_S_MATCH_M  (TRACE_S_MATCH_V << TRACE_S_MATCH_S)
+#define TRACE_S_MATCH_V  0xFFFFFFFFU
+#define TRACE_S_MATCH_S  0
+
+/** TRACE_RESYNC_PROLONGED_REG register
+ *  resync configuration register
+ */
+#define TRACE_RESYNC_PROLONGED_REG(i) (DR_REG_TRACE_BASE(i) + 0x3c)
+/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
+ *  count number, when count to this value, send a sync package
+ */
+#define TRACE_RESYNC_PROLONGED    0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_M  (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
+#define TRACE_RESYNC_PROLONGED_V  0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_S  0
+/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  resyc mode sel:
+ *  0: off,
+ *  2: cycle count
+ *  3: package num count
+ */
+#define TRACE_RESYNC_MODE    0x00000003U
+#define TRACE_RESYNC_MODE_M  (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
+#define TRACE_RESYNC_MODE_V  0x00000003U
+#define TRACE_RESYNC_MODE_S  24
+
+/** TRACE_AHB_CONFIG_REG register
+ *  AHB config register
+ */
+#define TRACE_AHB_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x40)
+/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
+ *  set hburst
+ */
+#define TRACE_HBURST    0x00000007U
+#define TRACE_HBURST_M  (TRACE_HBURST_V << TRACE_HBURST_S)
+#define TRACE_HBURST_V  0x00000007U
+#define TRACE_HBURST_S  0
+/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0;
+ *  set max continuous access for incr mode
+ */
+#define TRACE_MAX_INCR    0x00000007U
+#define TRACE_MAX_INCR_M  (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S)
+#define TRACE_MAX_INCR_V  0x00000007U
+#define TRACE_MAX_INCR_S  3
+
+/** TRACE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define TRACE_CLOCK_GATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x44)
+/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable clock gate when access all registers in this module.
+ */
+#define TRACE_CLK_EN    (BIT(0))
+#define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
+#define TRACE_CLK_EN_V  0x00000001U
+#define TRACE_CLK_EN_S  0
+
+/** TRACE_DATE_REG register
+ *  Version control register
+ */
+#define TRACE_DATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x3fc)
+/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define TRACE_DATE    0x0FFFFFFFU
+#define TRACE_DATE_M  (TRACE_DATE_V << TRACE_DATE_S)
+#define TRACE_DATE_V  0x0FFFFFFFU
+#define TRACE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/trace_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/trace_struct.h
new file mode 100644
index 0000000000..dcb4fcd9aa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/trace_struct.h
@@ -0,0 +1,503 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Trace memory configuration registers */
+/** Type of mem_start_addr register
+ *  mem start addr
+ */
+typedef union {
+    struct {
+        /** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of trace memory
+         */
+        uint32_t mem_start_addr:32;
+    };
+    uint32_t val;
+} trace_mem_start_addr_reg_t;
+
+/** Type of mem_end_addr register
+ *  mem end addr
+ */
+typedef union {
+    struct {
+        /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The end address of trace memory
+         */
+        uint32_t mem_end_addr:32;
+    };
+    uint32_t val;
+} trace_mem_end_addr_reg_t;
+
+/** Type of mem_current_addr register
+ *  mem current addr
+ */
+typedef union {
+    struct {
+        /** mem_current_addr : RO; bitpos: [31:0]; default: 0;
+         *  current_mem_addr,indicate that next writing addr
+         */
+        uint32_t mem_current_addr:32;
+    };
+    uint32_t val;
+} trace_mem_current_addr_reg_t;
+
+/** Type of mem_addr_update register
+ *  mem addr update
+ */
+typedef union {
+    struct {
+        /** mem_current_addr_update : WT; bitpos: [0]; default: 0;
+         *  when set, the  will
+         *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to
+         *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
+         */
+        uint32_t mem_current_addr_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_mem_addr_update_reg_t;
+
+
+/** Group: Trace fifo status register */
+/** Type of fifo_status register
+ *  fifo status register
+ */
+typedef union {
+    struct {
+        /** fifo_empty : RO; bitpos: [0]; default: 1;
+         *  Represent whether the fifo is empty.
+         *  1: empty
+         *  0: not empty
+         */
+        uint32_t fifo_empty:1;
+        /** work_status : RO; bitpos: [2:1]; default: 0;
+         *  Represent trace work status:
+         *  0: idle state
+         *  1: working state
+         *  2: wait state due to hart halted or havereset
+         *  3: lost state
+         */
+        uint32_t work_status:2;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} trace_fifo_status_reg_t;
+
+
+/** Group: Trace interrupt configuration registers */
+/** Type of intr_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
+         *  Set 1 enable fifo_overflow interrupt
+         */
+        uint32_t fifo_overflow_intr_ena:1;
+        /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
+         *  Set 1 enable mem_full interrupt
+         */
+        uint32_t mem_full_intr_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_ena_reg_t;
+
+/** Type of intr_raw register
+ *  interrupt status register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
+         *  fifo_overflow interrupt status
+         */
+        uint32_t fifo_overflow_intr_raw:1;
+        /** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
+         *  mem_full interrupt status
+         */
+        uint32_t mem_full_intr_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_raw_reg_t;
+
+/** Type of intr_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
+         *  Set 1 clear fifo overflow interrupt
+         */
+        uint32_t fifo_overflow_intr_clr:1;
+        /** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
+         *  Set 1 clear mem full interrupt
+         */
+        uint32_t mem_full_intr_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_clr_reg_t;
+
+
+/** Group: Trace configuration register */
+/** Type of trigger register
+ *  trigger register
+ */
+typedef union {
+    struct {
+        /** trigger_on : WT; bitpos: [0]; default: 0;
+         *  Configure whether or not start trace.
+         *  1: start trace
+         *  0: invalid
+         */
+        uint32_t trigger_on:1;
+        /** trigger_off : WT; bitpos: [1]; default: 0;
+         *  Configure whether or not stop trace.
+         *  1: stop trace
+         *  0: invalid
+         */
+        uint32_t trigger_off:1;
+        /** mem_loop : R/W; bitpos: [2]; default: 1;
+         *  Configure memory loop mode.
+         *  1: trace will loop write trace_mem.
+         *  0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr
+         */
+        uint32_t mem_loop:1;
+        /** restart_ena : R/W; bitpos: [3]; default: 1;
+         *  Configure whether or not enable auto-restart.
+         *  1: enable
+         *  0: disable
+         */
+        uint32_t restart_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} trace_trigger_reg_t;
+
+/** Type of config register
+ *  trace configuration register
+ */
+typedef union {
+    struct {
+        /** dm_trigger_ena : R/W; bitpos: [0]; default: 0;
+         *  Configure whether or not enable cpu trigger action.
+         *  1: enable
+         *  0:disable
+         */
+        uint32_t dm_trigger_ena:1;
+        /** reset_ena : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not enable trace cpu haverest, when enabled, if cpu have
+         *  reset, the encoder will output a packet to report the address of the last
+         *  instruction, and upon reset deassertion, the encoder start again.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t reset_ena:1;
+        /** halt_ena : R/W; bitpos: [2]; default: 0;
+         *  Configure whether or not enable trace cpu is halted, when enabled, if the cpu
+         *  halted, the encoder will output a packet to report the address of the last
+         *  instruction, and upon halted deassertion, the encoder start again.When disabled,
+         *  encoder will not report the last address before halted and first address after
+         *  halted, cpu halted information will not be tracked.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t halt_ena:1;
+        /** stall_ena : R/W; bitpos: [3]; default: 0;
+         *  Configure whether or not enable stall cpu. When enabled, when the fifo almost full,
+         *  the cpu will be stalled until the packets is able to write to fifo.
+         *  1: enabled.
+         *  0: disabled
+         */
+        uint32_t stall_ena:1;
+        /** full_address : R/W; bitpos: [4]; default: 0;
+         *  Configure whether or not enable full-address mode.
+         *  1: full address mode.
+         *  0: delta address mode
+         */
+        uint32_t full_address:1;
+        /** implicit_except : R/W; bitpos: [5]; default: 0;
+         *  Configure whether or not enable implicit exception mode. When enabled,, do not sent
+         *  exception address, only exception cause in exception packets.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t implicit_except:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} trace_config_reg_t;
+
+/** Type of filter_control register
+ *  filter control register
+ */
+typedef union {
+    struct {
+        /** filter_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether or not enable filter unit.
+         *  1: enable filter.
+         *  0: always match
+         */
+        uint32_t filter_en:1;
+        /** match_comp : R/W; bitpos: [1]; default: 0;
+         *  when set, the comparator must be high in order for the filter to match
+         */
+        uint32_t match_comp:1;
+        /** match_privilege : R/W; bitpos: [2]; default: 0;
+         *  when set, match privilege levels specified by
+         *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
+         */
+        uint32_t match_privilege:1;
+        /** match_ecause : R/W; bitpos: [3]; default: 0;
+         *  when set, start matching from exception cause codes specified by
+         *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
+         *  matching upon return from the 1st matching exception.
+         */
+        uint32_t match_ecause:1;
+        /** match_interrupt : R/W; bitpos: [4]; default: 0;
+         *  when set, start matching from a trap with the interrupt level codes specified by
+         *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
+         *  stop matching upon return from the 1st matching trap.
+         */
+        uint32_t match_interrupt:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} trace_filter_control_reg_t;
+
+/** Type of filter_match_control register
+ *  filter match control register
+ */
+typedef union {
+    struct {
+        /** match_choice_privilege : R/W; bitpos: [0]; default: 0;
+         *  Select match which privilege level when
+         *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set.
+         *  1: machine mode.
+         *  0: user mode
+         */
+        uint32_t match_choice_privilege:1;
+        /** match_value_interrupt : R/W; bitpos: [1]; default: 0;
+         *  Select which match which itype when
+         *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set.
+         *  1: match itype of 2.
+         *  0: match itype or 1.
+         */
+        uint32_t match_value_interrupt:1;
+        /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0;
+         *  specified which ecause matched.
+         */
+        uint32_t match_choice_ecause:6;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} trace_filter_match_control_reg_t;
+
+/** Type of filter_comparator_control register
+ *  filter comparator match control register
+ */
+typedef union {
+    struct {
+        /** p_input : R/W; bitpos: [0]; default: 0;
+         *  Determines which input to compare against the primary comparator,
+         *  0: iaddr,
+         *  1: tval.
+         */
+        uint32_t p_input:1;
+        uint32_t reserved_1:1;
+        /** p_function : R/W; bitpos: [4:2]; default: 0;
+         *  Select the primary comparator function.
+         *  0: equal,
+         *  1: not equal,
+         *  2: less than,
+         *  3: less than or equal,
+         *  4: greater than,
+         *  5: greater than or equal,
+         *  other: always match
+         */
+        uint32_t p_function:3;
+        /** p_notify : R/W; bitpos: [5]; default: 0;
+         *  Generate a trace packet explicitly reporting the address that cause the primary
+         *  match
+         */
+        uint32_t p_notify:1;
+        uint32_t reserved_6:2;
+        /** s_input : R/W; bitpos: [8]; default: 0;
+         *  Determines which input to compare against the secondary comparator,
+         *  0: iaddr,
+         *  1: tval.
+         */
+        uint32_t s_input:1;
+        uint32_t reserved_9:1;
+        /** s_function : R/W; bitpos: [12:10]; default: 0;
+         *  Select the secondary comparator function.
+         *  0: equal,
+         *  1: not equal,
+         *  2: less than,
+         *  3: less than or equal,
+         *  4: greater than,
+         *  5: greater than or equal,
+         *  other: always match
+         */
+        uint32_t s_function:3;
+        /** s_notify : R/W; bitpos: [13]; default: 0;
+         *  Generate a trace packet explicitly reporting the address that cause the secondary
+         *  match
+         */
+        uint32_t s_notify:1;
+        uint32_t reserved_14:2;
+        /** match_mode : R/W; bitpos: [17:16]; default: 0;
+         *  0: only primary matches,
+         *  1: primary and secondary comparator both matches(P\&\&S),
+         *  2:either primary or secondary comparator matches !(P\&\&S),
+         *  3: set when primary matches and continue to match until after secondary comparator
+         *  matches
+         */
+        uint32_t match_mode:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} trace_filter_comparator_control_reg_t;
+
+/** Type of filter_p_comparator_match register
+ *  primary comparator match value
+ */
+typedef union {
+    struct {
+        /** p_match : R/W; bitpos: [31:0]; default: 0;
+         *  primary comparator match value
+         */
+        uint32_t p_match:32;
+    };
+    uint32_t val;
+} trace_filter_p_comparator_match_reg_t;
+
+/** Type of filter_s_comparator_match register
+ *  secondary comparator match value
+ */
+typedef union {
+    struct {
+        /** s_match : R/W; bitpos: [31:0]; default: 0;
+         *  secondary comparator match value
+         */
+        uint32_t s_match:32;
+    };
+    uint32_t val;
+} trace_filter_s_comparator_match_reg_t;
+
+/** Type of resync_prolonged register
+ *  resync configuration register
+ */
+typedef union {
+    struct {
+        /** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
+         *  count number, when count to this value, send a sync package
+         */
+        uint32_t resync_prolonged:24;
+        /** resync_mode : R/W; bitpos: [25:24]; default: 0;
+         *  resyc mode sel:
+         *  0: off,
+         *  2: cycle count
+         *  3: package num count
+         */
+        uint32_t resync_mode:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} trace_resync_prolonged_reg_t;
+
+/** Type of ahb_config register
+ *  AHB config register
+ */
+typedef union {
+    struct {
+        /** hburst : R/W; bitpos: [2:0]; default: 0;
+         *  set hburst
+         */
+        uint32_t hburst:3;
+        /** max_incr : R/W; bitpos: [5:3]; default: 0;
+         *  set max continuous access for incr mode
+         */
+        uint32_t max_incr:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} trace_ahb_config_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35721984;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} trace_date_reg_t;
+
+
+typedef struct {
+    volatile trace_mem_start_addr_reg_t mem_start_addr;
+    volatile trace_mem_end_addr_reg_t mem_end_addr;
+    volatile trace_mem_current_addr_reg_t mem_current_addr;
+    volatile trace_mem_addr_update_reg_t mem_addr_update;
+    volatile trace_fifo_status_reg_t fifo_status;
+    volatile trace_intr_ena_reg_t intr_ena;
+    volatile trace_intr_raw_reg_t intr_raw;
+    volatile trace_intr_clr_reg_t intr_clr;
+    volatile trace_trigger_reg_t trigger;
+    volatile trace_config_reg_t config;
+    volatile trace_filter_control_reg_t filter_control;
+    volatile trace_filter_match_control_reg_t filter_match_control;
+    volatile trace_filter_comparator_control_reg_t filter_comparator_control;
+    volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match;
+    volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match;
+    volatile trace_resync_prolonged_reg_t resync_prolonged;
+    volatile trace_ahb_config_reg_t ahb_config;
+    volatile trace_clock_gate_reg_t clock_gate;
+    uint32_t reserved_048[237];
+    volatile trace_date_reg_t date;
+} trace_dev_t;
+
+extern trace_dev_t TRACE0;
+extern trace_dev_t TRACE1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/trng_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/trng_reg.h
new file mode 100644
index 0000000000..cbdd7e2bd1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/trng_reg.h
@@ -0,0 +1,94 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RNG_CFG_REG register
+ *  configure rng register
+ */
+#define RNG_CFG_REG (DR_REG_RNG_BASE + 0x0)
+/** RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  enable rng RO
+ *  1: enable RO
+ *  0: disable RO
+ */
+#define RNG_SAMPLE_ENABLE    (BIT(0))
+#define RNG_SAMPLE_ENABLE_M  (RNG_SAMPLE_ENABLE_V << RNG_SAMPLE_ENABLE_S)
+#define RNG_SAMPLE_ENABLE_V  0x00000001U
+#define RNG_SAMPLE_ENABLE_S  0
+/** RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255;
+ *  configure rng timer clk div
+ */
+#define RNG_TIMER_PSCALE    0x000000FFU
+#define RNG_TIMER_PSCALE_M  (RNG_TIMER_PSCALE_V << RNG_TIMER_PSCALE_S)
+#define RNG_TIMER_PSCALE_V  0x000000FFU
+#define RNG_TIMER_PSCALE_S  1
+/** RNG_TIMER_EN : R/W; bitpos: [9]; default: 1;
+ *  enable rng xor async rng timer
+ */
+#define RNG_TIMER_EN    (BIT(9))
+#define RNG_TIMER_EN_M  (RNG_TIMER_EN_V << RNG_TIMER_EN_S)
+#define RNG_TIMER_EN_V  0x00000001U
+#define RNG_TIMER_EN_S  9
+/** RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
+ *  get rng RO sample cnt
+ */
+#define RNG_SAMPLE_CNT    0x000000FFU
+#define RNG_SAMPLE_CNT_M  (RNG_SAMPLE_CNT_V << RNG_SAMPLE_CNT_S)
+#define RNG_SAMPLE_CNT_V  0x000000FFU
+#define RNG_SAMPLE_CNT_S  24
+
+/** RNG_DATA_REG register
+ *  RNG result register
+ */
+#define RNG_DATA_REG (DR_REG_RNG_BASE + 0x4)
+/** RNG_DATA : RO; bitpos: [31:0]; default: 0;
+ *  get rng data
+ */
+#define RNG_DATA    0xFFFFFFFFU
+#define RNG_DATA_M  (RNG_DATA_V << RNG_DATA_S)
+#define RNG_DATA_V  0xFFFFFFFFU
+#define RNG_DATA_S  0
+
+/** RNG_RSTN_REG register
+ *  rng rstn register
+ */
+#define RNG_RSTN_REG (DR_REG_RNG_BASE + 0x8)
+/** RNG_RSTN : R/W; bitpos: [0]; default: 1;
+ *  enable rng system reset: 1: not reset, 0: reset
+ */
+#define RNG_RSTN    (BIT(0))
+#define RNG_RSTN_M  (RNG_RSTN_V << RNG_RSTN_S)
+#define RNG_RSTN_V  0x00000001U
+#define RNG_RSTN_S  0
+
+/** RNG_DATE_REG register
+ *  need_des
+ */
+#define RNG_DATE_REG (DR_REG_RNG_BASE + 0xc)
+/** RNG_DATE : R/W; bitpos: [30:0]; default: 2425091;
+ *  need_des
+ */
+#define RNG_DATE    0x7FFFFFFFU
+#define RNG_DATE_M  (RNG_DATE_V << RNG_DATE_S)
+#define RNG_DATE_V  0x7FFFFFFFU
+#define RNG_DATE_S  0
+/** RNG_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RNG_CLK_EN    (BIT(31))
+#define RNG_CLK_EN_M  (RNG_CLK_EN_V << RNG_CLK_EN_S)
+#define RNG_CLK_EN_V  0x00000001U
+#define RNG_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/trng_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/trng_struct.h
new file mode 100644
index 0000000000..c669247cc1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/trng_struct.h
@@ -0,0 +1,102 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of cfg register
+ *  configure rng register
+ */
+typedef union {
+    struct {
+        /** sample_enable : R/W; bitpos: [0]; default: 0;
+         *  enable rng RO
+         *  1: enable RO
+         *  0: disable RO
+         */
+        uint32_t sample_enable:1;
+        /** timer_pscale : R/W; bitpos: [8:1]; default: 255;
+         *  configure rng timer clk div
+         */
+        uint32_t timer_pscale:8;
+        /** timer_en : R/W; bitpos: [9]; default: 1;
+         *  enable rng xor async rng timer
+         */
+        uint32_t timer_en:1;
+        uint32_t reserved_10:14;
+        /** sample_cnt : RO; bitpos: [31:24]; default: 0;
+         *  get rng RO sample cnt
+         */
+        uint32_t sample_cnt:8;
+    };
+    uint32_t val;
+} rng_cfg_reg_t;
+
+/** Type of data register
+ *  RNG result register
+ */
+typedef union {
+    struct {
+        /** data : RO; bitpos: [31:0]; default: 0;
+         *  get rng data
+         */
+        uint32_t data:32;
+    };
+    uint32_t val;
+} rng_data_reg_t;
+
+/** Type of rstn register
+ *  rng rstn register
+ */
+typedef union {
+    struct {
+        /** rstn : R/W; bitpos: [0]; default: 1;
+         *  enable rng system reset: 1: not reset, 0: reset
+         */
+        uint32_t rstn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rng_rstn_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [30:0]; default: 2425091;
+         *  need_des
+         */
+        uint32_t date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} rng_date_reg_t;
+
+
+typedef struct {
+    volatile rng_cfg_reg_t cfg;
+    volatile rng_data_reg_t data;
+    volatile rng_rstn_reg_t rstn;
+    volatile rng_date_reg_t date;
+} rng_dev_t;
+
+extern rng_dev_t LP_TRNG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rng_dev_t) == 0x10, "Invalid size of rng_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/tsens_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/tsens_reg.h
new file mode 100644
index 0000000000..0662085872
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/tsens_reg.h
@@ -0,0 +1,220 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TSENS_CTRL_REG register
+ *  Tsens configuration.
+ */
+#define TSENS_CTRL_REG (DR_REG_TSENS_BASE + 0x0)
+/** TSENS_OUT : RO; bitpos: [7:0]; default: 0;
+ *  Temperature sensor data out.
+ */
+#define TSENS_OUT    0x000000FFU
+#define TSENS_OUT_M  (TSENS_OUT_V << TSENS_OUT_S)
+#define TSENS_OUT_V  0x000000FFU
+#define TSENS_OUT_S  0
+/** TSENS_READY : RO; bitpos: [8]; default: 0;
+ *  Indicate temperature sensor out ready.
+ */
+#define TSENS_READY    (BIT(8))
+#define TSENS_READY_M  (TSENS_READY_V << TSENS_READY_S)
+#define TSENS_READY_V  0x00000001U
+#define TSENS_READY_S  8
+/** TSENS_SAMPLE_EN : R/W; bitpos: [9]; default: 0;
+ *  Enable sample signal for wakeup module.
+ */
+#define TSENS_SAMPLE_EN    (BIT(9))
+#define TSENS_SAMPLE_EN_M  (TSENS_SAMPLE_EN_V << TSENS_SAMPLE_EN_S)
+#define TSENS_SAMPLE_EN_V  0x00000001U
+#define TSENS_SAMPLE_EN_S  9
+/** TSENS_WAKEUP_MASK : R/W; bitpos: [10]; default: 1;
+ *  Wake up signal  mask.
+ */
+#define TSENS_WAKEUP_MASK    (BIT(10))
+#define TSENS_WAKEUP_MASK_M  (TSENS_WAKEUP_MASK_V << TSENS_WAKEUP_MASK_S)
+#define TSENS_WAKEUP_MASK_V  0x00000001U
+#define TSENS_WAKEUP_MASK_S  10
+/** TSENS_INT_EN : R/W; bitpos: [12]; default: 1;
+ *  Enable temperature sensor to send out interrupt.
+ */
+#define TSENS_INT_EN    (BIT(12))
+#define TSENS_INT_EN_M  (TSENS_INT_EN_V << TSENS_INT_EN_S)
+#define TSENS_INT_EN_V  0x00000001U
+#define TSENS_INT_EN_S  12
+/** TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
+ *  Invert temperature sensor data.
+ */
+#define TSENS_IN_INV    (BIT(13))
+#define TSENS_IN_INV_M  (TSENS_IN_INV_V << TSENS_IN_INV_S)
+#define TSENS_IN_INV_V  0x00000001U
+#define TSENS_IN_INV_S  13
+/** TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
+ *  Temperature sensor clock divider.
+ */
+#define TSENS_CLK_DIV    0x000000FFU
+#define TSENS_CLK_DIV_M  (TSENS_CLK_DIV_V << TSENS_CLK_DIV_S)
+#define TSENS_CLK_DIV_V  0x000000FFU
+#define TSENS_CLK_DIV_S  14
+/** TSENS_POWER_UP : R/W; bitpos: [22]; default: 0;
+ *  Temperature sensor power up.
+ */
+#define TSENS_POWER_UP    (BIT(22))
+#define TSENS_POWER_UP_M  (TSENS_POWER_UP_V << TSENS_POWER_UP_S)
+#define TSENS_POWER_UP_V  0x00000001U
+#define TSENS_POWER_UP_S  22
+/** TSENS_POWER_UP_FORCE : R/W; bitpos: [23]; default: 0;
+ *  1: dump out & power up controlled by SW,  0: by FSM.
+ */
+#define TSENS_POWER_UP_FORCE    (BIT(23))
+#define TSENS_POWER_UP_FORCE_M  (TSENS_POWER_UP_FORCE_V << TSENS_POWER_UP_FORCE_S)
+#define TSENS_POWER_UP_FORCE_V  0x00000001U
+#define TSENS_POWER_UP_FORCE_S  23
+
+/** TSENS_INT_RAW_REG register
+ *  Tsens interrupt raw registers.
+ */
+#define TSENS_INT_RAW_REG (DR_REG_TSENS_BASE + 0x8)
+/** TSENS_COCPU_TSENS_WAKE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt raw.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW_M  (TSENS_COCPU_TSENS_WAKE_INT_RAW_V << TSENS_COCPU_TSENS_WAKE_INT_RAW_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW_S  0
+
+/** TSENS_INT_ST_REG register
+ *  Tsens interrupt status registers.
+ */
+#define TSENS_INT_ST_REG (DR_REG_TSENS_BASE + 0xc)
+/** TSENS_COCPU_TSENS_WAKE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt status.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ST    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ST_M  (TSENS_COCPU_TSENS_WAKE_INT_ST_V << TSENS_COCPU_TSENS_WAKE_INT_ST_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ST_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ST_S  0
+
+/** TSENS_INT_ENA_REG register
+ *  Tsens interrupt enable registers.
+ */
+#define TSENS_INT_ENA_REG (DR_REG_TSENS_BASE + 0x10)
+/** TSENS_COCPU_TSENS_WAKE_INT_ENA : R/WTC; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt enable.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_M  (TSENS_COCPU_TSENS_WAKE_INT_ENA_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_S  0
+
+/** TSENS_INT_CLR_REG register
+ *  Tsens interrupt clear registers.
+ */
+#define TSENS_INT_CLR_REG (DR_REG_TSENS_BASE + 0x14)
+/** TSENS_COCPU_TSENS_WAKE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt clear.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR_M  (TSENS_COCPU_TSENS_WAKE_INT_CLR_V << TSENS_COCPU_TSENS_WAKE_INT_CLR_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR_S  0
+
+/** TSENS_CLK_CONF_REG register
+ *  Tsens regbank configuration registers.
+ */
+#define TSENS_CLK_CONF_REG (DR_REG_TSENS_BASE + 0x18)
+/** TSENS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Tsens regbank clock gating enable.
+ */
+#define TSENS_CLK_EN    (BIT(0))
+#define TSENS_CLK_EN_M  (TSENS_CLK_EN_V << TSENS_CLK_EN_S)
+#define TSENS_CLK_EN_V  0x00000001U
+#define TSENS_CLK_EN_S  0
+
+/** TSENS_INT_ENA_W1TS_REG register
+ *  Tsens wakeup interrupt enable assert.
+ */
+#define TSENS_INT_ENA_W1TS_REG (DR_REG_TSENS_BASE + 0x1c)
+/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this field to assert interrupt enable.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_M  (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S  0
+
+/** TSENS_INT_ENA_W1TC_REG register
+ *  Tsens wakeup interrupt enable deassert.
+ */
+#define TSENS_INT_ENA_W1TC_REG (DR_REG_TSENS_BASE + 0x20)
+/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this field to deassert interrupt enable.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_M  (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S  0
+
+/** TSENS_WAKEUP_CTRL_REG register
+ *  Tsens wakeup control registers.
+ */
+#define TSENS_WAKEUP_CTRL_REG (DR_REG_TSENS_BASE + 0x24)
+/** TSENS_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
+ *  Lower threshold.
+ */
+#define TSENS_WAKEUP_TH_LOW    0x000000FFU
+#define TSENS_WAKEUP_TH_LOW_M  (TSENS_WAKEUP_TH_LOW_V << TSENS_WAKEUP_TH_LOW_S)
+#define TSENS_WAKEUP_TH_LOW_V  0x000000FFU
+#define TSENS_WAKEUP_TH_LOW_S  0
+/** TSENS_WAKEUP_TH_HIGH : R/W; bitpos: [21:14]; default: 255;
+ *  Upper threshold.
+ */
+#define TSENS_WAKEUP_TH_HIGH    0x000000FFU
+#define TSENS_WAKEUP_TH_HIGH_M  (TSENS_WAKEUP_TH_HIGH_V << TSENS_WAKEUP_TH_HIGH_S)
+#define TSENS_WAKEUP_TH_HIGH_V  0x000000FFU
+#define TSENS_WAKEUP_TH_HIGH_S  14
+/** TSENS_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
+ *  Indicates that this wakeup event arose from exceeding upper threshold.
+ */
+#define TSENS_WAKEUP_OVER_UPPER_TH    (BIT(29))
+#define TSENS_WAKEUP_OVER_UPPER_TH_M  (TSENS_WAKEUP_OVER_UPPER_TH_V << TSENS_WAKEUP_OVER_UPPER_TH_S)
+#define TSENS_WAKEUP_OVER_UPPER_TH_V  0x00000001U
+#define TSENS_WAKEUP_OVER_UPPER_TH_S  29
+/** TSENS_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
+ *  Tsens wakeup enable.
+ */
+#define TSENS_WAKEUP_EN    (BIT(30))
+#define TSENS_WAKEUP_EN_M  (TSENS_WAKEUP_EN_V << TSENS_WAKEUP_EN_S)
+#define TSENS_WAKEUP_EN_V  0x00000001U
+#define TSENS_WAKEUP_EN_S  30
+/** TSENS_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
+ *  0:absolute value comparison mode. 1: relative value comparison mode.
+ */
+#define TSENS_WAKEUP_MODE    (BIT(31))
+#define TSENS_WAKEUP_MODE_M  (TSENS_WAKEUP_MODE_V << TSENS_WAKEUP_MODE_S)
+#define TSENS_WAKEUP_MODE_V  0x00000001U
+#define TSENS_WAKEUP_MODE_S  31
+
+/** TSENS_SAMPLE_RATE_REG register
+ *  Hardware automatic sampling control registers.
+ */
+#define TSENS_SAMPLE_RATE_REG (DR_REG_TSENS_BASE + 0x28)
+/** TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
+ *  Hardware automatic sampling rate.
+ */
+#define TSENS_SAMPLE_RATE    0x0000FFFFU
+#define TSENS_SAMPLE_RATE_M  (TSENS_SAMPLE_RATE_V << TSENS_SAMPLE_RATE_S)
+#define TSENS_SAMPLE_RATE_V  0x0000FFFFU
+#define TSENS_SAMPLE_RATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/tsens_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/tsens_struct.h
new file mode 100644
index 0000000000..212214fa3f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/tsens_struct.h
@@ -0,0 +1,233 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Tsens control registers. */
+/** Type of ctrl register
+ *  Tsens configuration.
+ */
+typedef union {
+    struct {
+        /** out : RO; bitpos: [7:0]; default: 0;
+         *  Temperature sensor data out.
+         */
+        uint32_t out:8;
+        /** ready : RO; bitpos: [8]; default: 0;
+         *  Indicate temperature sensor out ready.
+         */
+        uint32_t ready:1;
+        /** sample_en : R/W; bitpos: [9]; default: 0;
+         *  Enable sample signal for wakeup module.
+         */
+        uint32_t sample_en:1;
+        /** wakeup_mask : R/W; bitpos: [10]; default: 1;
+         *  Wake up signal  mask.
+         */
+        uint32_t wakeup_mask:1;
+        uint32_t reserved_11:1;
+        /** int_en : R/W; bitpos: [12]; default: 1;
+         *  Enable temperature sensor to send out interrupt.
+         */
+        uint32_t int_en:1;
+        /** in_inv : R/W; bitpos: [13]; default: 0;
+         *  Invert temperature sensor data.
+         */
+        uint32_t in_inv:1;
+        /** clk_div : R/W; bitpos: [21:14]; default: 6;
+         *  Temperature sensor clock divider.
+         */
+        uint32_t clk_div:8;
+        /** power_up : R/W; bitpos: [22]; default: 0;
+         *  Temperature sensor power up.
+         */
+        uint32_t power_up:1;
+        /** power_up_force : R/W; bitpos: [23]; default: 0;
+         *  1: dump out & power up controlled by SW,  0: by FSM.
+         */
+        uint32_t power_up_force:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} tsens_ctrl_reg_t;
+
+
+/** Group: Tsens interrupt registers. */
+/** Type of int_raw register
+ *  Tsens interrupt raw registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt raw.
+         */
+        uint32_t cocpu_tsens_wake_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Tsens interrupt status registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_st : RO; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt status.
+         */
+        uint32_t cocpu_tsens_wake_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Tsens interrupt enable registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_ena : R/WTC; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt enable.
+         */
+        uint32_t cocpu_tsens_wake_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Tsens interrupt clear registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_clr : WT; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt clear.
+         */
+        uint32_t cocpu_tsens_wake_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_clr_reg_t;
+
+/** Type of int_ena_w1ts register
+ *  Tsens wakeup interrupt enable assert.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_ena_w1ts : WT; bitpos: [0]; default: 0;
+         *  Write 1 to this field to assert interrupt enable.
+         */
+        uint32_t cocpu_tsens_wake_int_ena_w1ts:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_ena_w1ts_reg_t;
+
+/** Type of int_ena_w1tc register
+ *  Tsens wakeup interrupt enable deassert.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_ena_w1tc : WT; bitpos: [0]; default: 0;
+         *  Write 1 to this field to deassert interrupt enable.
+         */
+        uint32_t cocpu_tsens_wake_int_ena_w1tc:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_ena_w1tc_reg_t;
+
+
+/** Group: Tsens regbank clock control registers. */
+/** Type of clk_conf register
+ *  Tsens regbank configuration registers.
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Tsens regbank clock gating enable.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_clk_conf_reg_t;
+
+
+/** Group: Tsens wakeup control registers. */
+/** Type of wakeup_ctrl register
+ *  Tsens wakeup control registers.
+ */
+typedef union {
+    struct {
+        /** wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
+         *  Lower threshold.
+         */
+        uint32_t wakeup_th_low:8;
+        uint32_t reserved_8:6;
+        /** wakeup_th_high : R/W; bitpos: [21:14]; default: 255;
+         *  Upper threshold.
+         */
+        uint32_t wakeup_th_high:8;
+        uint32_t reserved_22:7;
+        /** wakeup_over_upper_th : RO; bitpos: [29]; default: 0;
+         *  Indicates that this wakeup event arose from exceeding upper threshold.
+         */
+        uint32_t wakeup_over_upper_th:1;
+        /** wakeup_en : R/W; bitpos: [30]; default: 0;
+         *  Tsens wakeup enable.
+         */
+        uint32_t wakeup_en:1;
+        /** wakeup_mode : R/W; bitpos: [31]; default: 0;
+         *  0:absolute value comparison mode. 1: relative value comparison mode.
+         */
+        uint32_t wakeup_mode:1;
+    };
+    uint32_t val;
+} tsens_wakeup_ctrl_reg_t;
+
+/** Type of sample_rate register
+ *  Hardware automatic sampling control registers.
+ */
+typedef union {
+    struct {
+        /** sample_rate : R/W; bitpos: [15:0]; default: 20;
+         *  Hardware automatic sampling rate.
+         */
+        uint32_t sample_rate:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} tsens_sample_rate_reg_t;
+
+
+typedef struct {
+    volatile tsens_ctrl_reg_t ctrl;
+    uint32_t reserved_004;
+    volatile tsens_int_raw_reg_t int_raw;
+    volatile tsens_int_st_reg_t int_st;
+    volatile tsens_int_ena_reg_t int_ena;
+    volatile tsens_int_clr_reg_t int_clr;
+    volatile tsens_clk_conf_reg_t clk_conf;
+    volatile tsens_int_ena_w1ts_reg_t int_ena_w1ts;
+    volatile tsens_int_ena_w1tc_reg_t int_ena_w1tc;
+    volatile tsens_wakeup_ctrl_reg_t wakeup_ctrl;
+    volatile tsens_sample_rate_reg_t sample_rate;
+} tsens_dev_t;
+
+extern tsens_dev_t LP_TSENS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tsens_dev_t) == 0x2c, "Invalid size of tsens_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/twai_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/twai_eco5_struct.h
new file mode 100644
index 0000000000..429a1a7145
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/twai_eco5_struct.h
@@ -0,0 +1,799 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of mode register
+ *  TWAI mode register.
+ */
+typedef union {
+    struct {
+        /** reset_mode : R/W; bitpos: [0]; default: 1;
+         *  1: reset, detection of a set reset mode bit results in aborting the current
+         *  transmission/reception of a message and entering the reset mode. 0: normal, on the
+         *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
+         *  operating mode.
+         */
+        uint32_t reset_mode:1;
+        /** listen_only_mode : R/W; bitpos: [1]; default: 0;
+         *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
+         *  TWAI-bus, even if a message is received successfully. The error counters are
+         *  stopped at the current value. 0: normal.
+         */
+        uint32_t listen_only_mode:1;
+        /** self_test_mode : R/W; bitpos: [2]; default: 0;
+         *  1: self test, in this mode a full node test is possible without any other active
+         *  node on the bus using the self reception request command. The TWAI controller will
+         *  perform a successful transmission, even if there is no acknowledge received. 0:
+         *  normal, an acknowledge is required for successful transmission.
+         */
+        uint32_t self_test_mode:1;
+        /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0;
+         *  1:single, the single acceptance filter option is enabled (one filter with the
+         *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
+         *  (two filters, each with the length of 16 bit are active).
+         */
+        uint32_t acceptance_filter_mode:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} twai_mode_reg_t;
+
+/** Type of cmd register
+ *  TWAI command register.
+ */
+typedef union {
+    struct {
+        /** tx_request : WO; bitpos: [0]; default: 0;
+         *  1: present, a message shall be transmitted. 0: absent
+         */
+        uint32_t tx_request:1;
+        /** abort_tx : WO; bitpos: [1]; default: 0;
+         *  1: present, if not already in progress, a pending transmission request is
+         *  cancelled. 0: absent
+         */
+        uint32_t abort_tx:1;
+        /** release_buffer : WO; bitpos: [2]; default: 0;
+         *  1: released, the receive buffer, representing the message memory space in the
+         *  RXFIFO is released. 0: no action
+         */
+        uint32_t release_buffer:1;
+        /** clear_data_overrun : WO; bitpos: [3]; default: 0;
+         *  1: clear, the data overrun status bit is cleared. 0: no action.
+         */
+        uint32_t clear_data_overrun:1;
+        /** self_rx_request : WO; bitpos: [4]; default: 0;
+         *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
+         */
+        uint32_t self_rx_request:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} twai_cmd_reg_t;
+
+/** Type of bus_timing_0 register
+ *  Bit timing configuration register 0.
+ */
+typedef union {
+    struct {
+        /** baud_presc : R/W; bitpos: [13:0]; default: 0;
+         *  The period of the TWAI system clock is programmable and determines the individual
+         *  bit timing. Software has R/W permission in reset mode and RO permission in
+         *  operation mode.
+         */
+        uint32_t baud_presc:14;
+        /** sync_jump_width : R/W; bitpos: [15:14]; default: 0;
+         *  The synchronization jump width defines the maximum number of clock cycles a bit
+         *  period may be shortened or lengthened. Software has R/W permission in reset mode
+         *  and RO in operation mode.
+         */
+        uint32_t sync_jump_width:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} twai_bus_timing_0_reg_t;
+
+/** Type of bus_timing_1 register
+ *  Bit timing configuration register 1.
+ */
+typedef union {
+    struct {
+        /** time_segment1 : R/W; bitpos: [3:0]; default: 0;
+         *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
+         *  reset mode and RO in operation mode.
+         */
+        uint32_t time_segment1:4;
+        /** time_segment2 : R/W; bitpos: [6:4]; default: 0;
+         *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
+         *  reset mode and RO in operation mode.
+         */
+        uint32_t time_segment2:3;
+        /** time_sampling : R/W; bitpos: [7]; default: 0;
+         *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
+         *  Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t time_sampling:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_bus_timing_1_reg_t;
+
+/** Type of err_warning_limit register
+ *  TWAI error threshold configuration register.
+ */
+typedef union {
+    struct {
+        /** err_warning_limit : R/W; bitpos: [7:0]; default: 96;
+         *  The threshold that trigger error warning interrupt when this interrupt is enabled.
+         *  Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t err_warning_limit:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_err_warning_limit_reg_t;
+
+/** Type of clock_divider register
+ *  Clock divider register.
+ */
+typedef union {
+    struct {
+        /** cd : R/W; bitpos: [7:0]; default: 0;
+         *  These bits are used to define the frequency at the external CLKOUT pin.
+         */
+        uint32_t cd:8;
+        /** clock_off : R/W; bitpos: [8]; default: 0;
+         *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
+         *  R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t clock_off:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_clock_divider_reg_t;
+
+/** Type of sw_standby_cfg register
+ *  Software configure standby pin directly.
+ */
+typedef union {
+    struct {
+        /** sw_standby_en : R/W; bitpos: [0]; default: 0;
+         *  Enable standby pin.
+         */
+        uint32_t sw_standby_en:1;
+        /** sw_standby_clr : R/W; bitpos: [1]; default: 1;
+         *  Clear standby pin.
+         */
+        uint32_t sw_standby_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twai_sw_standby_cfg_reg_t;
+
+/** Type of hw_cfg register
+ *  Hardware configure standby pin.
+ */
+typedef union {
+    struct {
+        /** hw_standby_en : R/W; bitpos: [0]; default: 0;
+         *  Enable function that hardware control standby pin.
+         */
+        uint32_t hw_standby_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} twai_hw_cfg_reg_t;
+
+/** Type of hw_standby_cnt register
+ *  Configure standby counter.
+ */
+typedef union {
+    struct {
+        /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1;
+         *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
+         *  is enabled.
+         */
+        uint32_t standby_wait_cnt:32;
+    };
+    uint32_t val;
+} twai_hw_standby_cnt_reg_t;
+
+/** Type of idle_intr_cnt register
+ *  Configure idle interrupt counter.
+ */
+typedef union {
+    struct {
+        /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1;
+         *  Configure the number of cycles before triggering idle interrupt.
+         */
+        uint32_t idle_intr_cnt:32;
+    };
+    uint32_t val;
+} twai_idle_intr_cnt_reg_t;
+
+/** Type of eco_cfg register
+ *  ECO configuration register.
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable eco module.
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 1;
+         *  Output of eco module.
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twai_eco_cfg_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of status register
+ *  TWAI status register.
+ */
+typedef union {
+    struct {
+        /** status_receive_buffer : RO; bitpos: [0]; default: 0;
+         *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
+         *  message is available
+         */
+        uint32_t status_receive_buffer:1;
+        /** status_overrun : RO; bitpos: [1]; default: 0;
+         *  1: overrun, a message was lost because there was not enough space for that message
+         *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
+         *  overrun command was given
+         */
+        uint32_t status_overrun:1;
+        /** status_transmit_buffer : RO; bitpos: [2]; default: 0;
+         *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
+         *  CPU cannot access the transmit buffer, a message is either waiting for transmission
+         *  or is in the process of being transmitted
+         */
+        uint32_t status_transmit_buffer:1;
+        /** status_transmission_complete : RO; bitpos: [3]; default: 0;
+         *  1: complete, last requested transmission has been successfully completed. 0:
+         *  incomplete, previously requested transmission is not yet completed
+         */
+        uint32_t status_transmission_complete:1;
+        /** status_receive : RO; bitpos: [4]; default: 0;
+         *  1: receive, the TWAI controller is receiving a message. 0: idle
+         */
+        uint32_t status_receive:1;
+        /** status_transmit : RO; bitpos: [5]; default: 0;
+         *  1: transmit, the TWAI controller is transmitting a message. 0: idle
+         */
+        uint32_t status_transmit:1;
+        /** status_err : RO; bitpos: [6]; default: 0;
+         *  1: error, at least one of the error counters has reached or exceeded the CPU
+         *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
+         *  counters are below the warning limit
+         */
+        uint32_t status_err:1;
+        /** status_node_bus_off : RO; bitpos: [7]; default: 0;
+         *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
+         *  TWAI controller is involved in bus activities
+         */
+        uint32_t status_node_bus_off:1;
+        /** status_miss : RO; bitpos: [8]; default: 0;
+         *  1: current message is destroyed because of FIFO overflow.
+         */
+        uint32_t status_miss:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_status_reg_t;
+
+/** Type of arb_lost_cap register
+ *  TWAI arbiter lost capture register.
+ */
+typedef union {
+    struct {
+        /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0;
+         *  This register contains information about the bit position of losing arbitration.
+         */
+        uint32_t arbitration_lost_capture:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} twai_arb_lost_cap_reg_t;
+
+/** Type of err_code_cap register
+ *  TWAI error info capture register.
+ */
+typedef union {
+    struct {
+        /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0;
+         *  This register contains information about the location of errors on the bus.
+         */
+        uint32_t err_capture_code_segment:5;
+        /** err_capture_code_direction : RO; bitpos: [5]; default: 0;
+         *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
+         */
+        uint32_t err_capture_code_direction:1;
+        /** err_capture_code_type : RO; bitpos: [7:6]; default: 0;
+         *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
+         */
+        uint32_t err_capture_code_type:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_err_code_cap_reg_t;
+
+/** Type of rx_err_cnt register
+ *  Rx error counter register.
+ */
+typedef union {
+    struct {
+        /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0;
+         *  The RX error counter register reflects the current value of the transmit error
+         *  counter. Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t rx_err_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_rx_err_cnt_reg_t;
+
+/** Type of tx_err_cnt register
+ *  Tx error counter register.
+ */
+typedef union {
+    struct {
+        /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0;
+         *  The TX error counter register reflects the current value of the transmit error
+         *  counter. Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t tx_err_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_tx_err_cnt_reg_t;
+
+/** Type of rx_message_counter register
+ *  Received message counter register.
+ */
+typedef union {
+    struct {
+        /** rx_message_counter : RO; bitpos: [6:0]; default: 0;
+         *  Reflects the number of messages available within the RXFIFO. The value is
+         *  incremented with each receive event and decremented by the release receive buffer
+         *  command.
+         */
+        uint32_t rx_message_counter:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} twai_rx_message_counter_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of interrupt register
+ *  Interrupt signals' register.
+ */
+typedef union {
+    struct {
+        /** receive_int_st : RO; bitpos: [0]; default: 0;
+         *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
+         *  within the interrupt enable register. 0: reset
+         */
+        uint32_t receive_int_st:1;
+        /** transmit_int_st : RO; bitpos: [1]; default: 0;
+         *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
+         *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t transmit_int_st:1;
+        /** err_warning_int_st : RO; bitpos: [2]; default: 0;
+         *  1: this bit is set on every change (set and clear) of either the error status or
+         *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
+         *  reset
+         */
+        uint32_t err_warning_int_st:1;
+        /** data_overrun_int_st : RO; bitpos: [3]; default: 0;
+         *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
+         *  DOIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t data_overrun_int_st:1;
+        /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0;
+         *  1: this bit is set then the timestamp counter reaches the maximum value and
+         *  overflow.
+         */
+        uint32_t ts_counter_ovfl_int_st:1;
+        /** err_passive_int_st : RO; bitpos: [5]; default: 0;
+         *  1: this bit is set whenever the TWAI controller has reached the error passive
+         *  status (at least one error counter exceeds the protocol-defined level of 127) or if
+         *  the TWAI controller is in the error passive status and enters the error active
+         *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t err_passive_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0;
+         *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
+         *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** bus_err_int_st : RO; bitpos: [7]; default: 0;
+         *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
+         *  the BEIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t bus_err_int_st:1;
+        /** idle_int_st : RO; bitpos: [8]; default: 0;
+         *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
+         *  this interrupt enable bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t idle_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_interrupt_reg_t;
+
+/** Type of interrupt_enable register
+ *  Interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0;
+         *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
+         *  the respective interrupt. 0: disable
+         */
+        uint32_t ext_receive_int_ena:1;
+        /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0;
+         *  1: enabled, when a message has been successfully transmitted or the transmit buffer
+         *  is accessible again (e.g. after an abort transmission command), the TWAI controller
+         *  requests the respective interrupt. 0: disable
+         */
+        uint32_t ext_transmit_int_ena:1;
+        /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0;
+         *  1: enabled, if the error or bus status change (see status register. Table 14), the
+         *  TWAI controllerrequests the respective interrupt. 0: disable
+         */
+        uint32_t ext_err_warning_int_ena:1;
+        /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
+         *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
+         *  the TWAI controllerrequests the respective interrupt. 0: disable
+         */
+        uint32_t ext_data_overrun_int_ena:1;
+        /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0;
+         *  enable the timestamp counter overflow interrupt request.
+         */
+        uint32_t ts_counter_ovfl_int_ena:1;
+        /** err_passive_int_ena : R/W; bitpos: [5]; default: 0;
+         *  1: enabled, if the error status of the TWAI controller changes from error active to
+         *  error passive or vice versa, the respective interrupt is requested. 0: disable
+         */
+        uint32_t err_passive_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0;
+         *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
+         *  is requested. 0: disable
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** bus_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  1: enabled, if an bus error has been detected, the TWAI controller requests the
+         *  respective interrupt. 0: disable
+         */
+        uint32_t bus_err_int_ena:1;
+        /** idle_int_ena : RO; bitpos: [8]; default: 0;
+         *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
+         *  respective interrupt. 0: disable
+         */
+        uint32_t idle_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_interrupt_enable_reg_t;
+
+
+/** Group: Data Registers */
+/** Type of data_0 register
+ *  Data register 0.
+ */
+typedef union {
+    struct {
+        /** data_0 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 0 and when
+         *  software initiate read operation, it is rx data register 0.
+         */
+        uint32_t data_0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_0_reg_t;
+
+/** Type of data_1 register
+ *  Data register 1.
+ */
+typedef union {
+    struct {
+        /** data_1 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 1 and when
+         *  software initiate read operation, it is rx data register 1.
+         */
+        uint32_t data_1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_1_reg_t;
+
+/** Type of data_2 register
+ *  Data register 2.
+ */
+typedef union {
+    struct {
+        /** data_2 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 2 and when
+         *  software initiate read operation, it is rx data register 2.
+         */
+        uint32_t data_2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_2_reg_t;
+
+/** Type of data_3 register
+ *  Data register 3.
+ */
+typedef union {
+    struct {
+        /** data_3 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 3 and when
+         *  software initiate read operation, it is rx data register 3.
+         */
+        uint32_t data_3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_3_reg_t;
+
+/** Type of data_4 register
+ *  Data register 4.
+ */
+typedef union {
+    struct {
+        /** data_4 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 4 and when
+         *  software initiate read operation, it is rx data register 4.
+         */
+        uint32_t data_4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_4_reg_t;
+
+/** Type of data_5 register
+ *  Data register 5.
+ */
+typedef union {
+    struct {
+        /** data_5 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 5 and when
+         *  software initiate read operation, it is rx data register 5.
+         */
+        uint32_t data_5:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_5_reg_t;
+
+/** Type of data_6 register
+ *  Data register 6.
+ */
+typedef union {
+    struct {
+        /** data_6 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 6 and when
+         *  software initiate read operation, it is rx data register 6.
+         */
+        uint32_t data_6:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_6_reg_t;
+
+/** Type of data_7 register
+ *  Data register 7.
+ */
+typedef union {
+    struct {
+        /** data_7 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 7 and when
+         *  software initiate read operation, it is rx data register 7.
+         */
+        uint32_t data_7:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_7_reg_t;
+
+/** Type of data_8 register
+ *  Data register 8.
+ */
+typedef union {
+    struct {
+        /** data_8 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 8 and when software initiate read operation, it
+         *  is rx data register 8.
+         */
+        uint32_t data_8:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_8_reg_t;
+
+/** Type of data_9 register
+ *  Data register 9.
+ */
+typedef union {
+    struct {
+        /** data_9 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 9 and when software initiate read operation, it
+         *  is rx data register 9.
+         */
+        uint32_t data_9:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_9_reg_t;
+
+/** Type of data_10 register
+ *  Data register 10.
+ */
+typedef union {
+    struct {
+        /** data_10 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 10 and when software initiate read operation, it
+         *  is rx data register 10.
+         */
+        uint32_t data_10:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_10_reg_t;
+
+/** Type of data_11 register
+ *  Data register 11.
+ */
+typedef union {
+    struct {
+        /** data_11 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 11 and when software initiate read operation, it
+         *  is rx data register 11.
+         */
+        uint32_t data_11:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_11_reg_t;
+
+/** Type of data_12 register
+ *  Data register 12.
+ */
+typedef union {
+    struct {
+        /** data_12 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 12 and when software initiate read operation, it
+         *  is rx data register 12.
+         */
+        uint32_t data_12:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_12_reg_t;
+
+
+/** Group: Timestamp Register */
+/** Type of timestamp_data register
+ *  Timestamp data register
+ */
+typedef union {
+    struct {
+        /** timestamp_data : RO; bitpos: [31:0]; default: 0;
+         *  Data of timestamp of a CAN frame.
+         */
+        uint32_t timestamp_data:32;
+    };
+    uint32_t val;
+} twai_timestamp_data_reg_t;
+
+/** Type of timestamp_prescaler register
+ *  Timestamp configuration register
+ */
+typedef union {
+    struct {
+        /** ts_div_num : R/W; bitpos: [15:0]; default: 31;
+         *  Configures the clock division number of timestamp counter.
+         */
+        uint32_t ts_div_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} twai_timestamp_prescaler_reg_t;
+
+/** Type of timestamp_cfg register
+ *  Timestamp configuration register
+ */
+typedef union {
+    struct {
+        /** ts_enable : R/W; bitpos: [0]; default: 0;
+         *  enable the timestamp collection function.
+         */
+        uint32_t ts_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} twai_timestamp_cfg_reg_t;
+
+
+typedef struct {
+    volatile twai_mode_reg_t mode;
+    volatile twai_cmd_reg_t cmd;
+    volatile twai_status_reg_t status;
+    volatile twai_interrupt_reg_t interrupt;
+    volatile twai_interrupt_enable_reg_t interrupt_enable;
+    uint32_t reserved_014;
+    volatile twai_bus_timing_0_reg_t bus_timing_0;
+    volatile twai_bus_timing_1_reg_t bus_timing_1;
+    uint32_t reserved_020[3];
+    volatile twai_arb_lost_cap_reg_t arb_lost_cap;
+    volatile twai_err_code_cap_reg_t err_code_cap;
+    volatile twai_err_warning_limit_reg_t err_warning_limit;
+    volatile twai_rx_err_cnt_reg_t rx_err_cnt;
+    volatile twai_tx_err_cnt_reg_t tx_err_cnt;
+    volatile twai_data_0_reg_t data_0;
+    volatile twai_data_1_reg_t data_1;
+    volatile twai_data_2_reg_t data_2;
+    volatile twai_data_3_reg_t data_3;
+    volatile twai_data_4_reg_t data_4;
+    volatile twai_data_5_reg_t data_5;
+    volatile twai_data_6_reg_t data_6;
+    volatile twai_data_7_reg_t data_7;
+    volatile twai_data_8_reg_t data_8;
+    volatile twai_data_9_reg_t data_9;
+    volatile twai_data_10_reg_t data_10;
+    volatile twai_data_11_reg_t data_11;
+    volatile twai_data_12_reg_t data_12;
+    volatile twai_rx_message_counter_reg_t rx_message_counter;
+    uint32_t reserved_078;
+    volatile twai_clock_divider_reg_t clock_divider;
+    volatile twai_sw_standby_cfg_reg_t sw_standby_cfg;
+    volatile twai_hw_cfg_reg_t hw_cfg;
+    volatile twai_hw_standby_cnt_reg_t hw_standby_cnt;
+    volatile twai_idle_intr_cnt_reg_t idle_intr_cnt;
+    volatile twai_eco_cfg_reg_t eco_cfg;
+    volatile twai_timestamp_data_reg_t timestamp_data;
+    volatile twai_timestamp_prescaler_reg_t timestamp_prescaler;
+    volatile twai_timestamp_cfg_reg_t timestamp_cfg;
+} twai_dev_t;
+
+extern twai_dev_t TWAI0;
+extern twai_dev_t TWAI1;
+extern twai_dev_t TWAI2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/twai_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/twai_reg.h
new file mode 100644
index 0000000000..3eb5c0bb37
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/twai_reg.h
@@ -0,0 +1,791 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TWAI_MODE_REG register
+ *  TWAI mode register.
+ */
+#define TWAI_MODE_REG(i) (DR_REG_TWAI_BASE(i) + 0x0)
+/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1;
+ *  1: reset, detection of a set reset mode bit results in aborting the current
+ *  transmission/reception of a message and entering the reset mode. 0: normal, on the
+ *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
+ *  operating mode.
+ */
+#define TWAI_RESET_MODE    (BIT(0))
+#define TWAI_RESET_MODE_M  (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S)
+#define TWAI_RESET_MODE_V  0x00000001U
+#define TWAI_RESET_MODE_S  0
+/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0;
+ *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
+ *  TWAI-bus, even if a message is received successfully. The error counters are
+ *  stopped at the current value. 0: normal.
+ */
+#define TWAI_LISTEN_ONLY_MODE    (BIT(1))
+#define TWAI_LISTEN_ONLY_MODE_M  (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S)
+#define TWAI_LISTEN_ONLY_MODE_V  0x00000001U
+#define TWAI_LISTEN_ONLY_MODE_S  1
+/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0;
+ *  1: self test, in this mode a full node test is possible without any other active
+ *  node on the bus using the self reception request command. The TWAI controller will
+ *  perform a successful transmission, even if there is no acknowledge received. 0:
+ *  normal, an acknowledge is required for successful transmission.
+ */
+#define TWAI_SELF_TEST_MODE    (BIT(2))
+#define TWAI_SELF_TEST_MODE_M  (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S)
+#define TWAI_SELF_TEST_MODE_V  0x00000001U
+#define TWAI_SELF_TEST_MODE_S  2
+/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0;
+ *  1:single, the single acceptance filter option is enabled (one filter with the
+ *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
+ *  (two filters, each with the length of 16 bit are active).
+ */
+#define TWAI_ACCEPTANCE_FILTER_MODE    (BIT(3))
+#define TWAI_ACCEPTANCE_FILTER_MODE_M  (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S)
+#define TWAI_ACCEPTANCE_FILTER_MODE_V  0x00000001U
+#define TWAI_ACCEPTANCE_FILTER_MODE_S  3
+
+/** TWAI_CMD_REG register
+ *  TWAI command register.
+ */
+#define TWAI_CMD_REG(i) (DR_REG_TWAI_BASE(i) + 0x4)
+/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0;
+ *  1: present, a message shall be transmitted. 0: absent
+ */
+#define TWAI_TX_REQUEST    (BIT(0))
+#define TWAI_TX_REQUEST_M  (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S)
+#define TWAI_TX_REQUEST_V  0x00000001U
+#define TWAI_TX_REQUEST_S  0
+/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0;
+ *  1: present, if not already in progress, a pending transmission request is
+ *  cancelled. 0: absent
+ */
+#define TWAI_ABORT_TX    (BIT(1))
+#define TWAI_ABORT_TX_M  (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S)
+#define TWAI_ABORT_TX_V  0x00000001U
+#define TWAI_ABORT_TX_S  1
+/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0;
+ *  1: released, the receive buffer, representing the message memory space in the
+ *  RXFIFO is released. 0: no action
+ */
+#define TWAI_RELEASE_BUFFER    (BIT(2))
+#define TWAI_RELEASE_BUFFER_M  (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S)
+#define TWAI_RELEASE_BUFFER_V  0x00000001U
+#define TWAI_RELEASE_BUFFER_S  2
+/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0;
+ *  1: clear, the data overrun status bit is cleared. 0: no action.
+ */
+#define TWAI_CLEAR_DATA_OVERRUN    (BIT(3))
+#define TWAI_CLEAR_DATA_OVERRUN_M  (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S)
+#define TWAI_CLEAR_DATA_OVERRUN_V  0x00000001U
+#define TWAI_CLEAR_DATA_OVERRUN_S  3
+/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0;
+ *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
+ */
+#define TWAI_SELF_RX_REQUEST    (BIT(4))
+#define TWAI_SELF_RX_REQUEST_M  (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S)
+#define TWAI_SELF_RX_REQUEST_V  0x00000001U
+#define TWAI_SELF_RX_REQUEST_S  4
+
+/** TWAI_STATUS_REG register
+ *  TWAI status register.
+ */
+#define TWAI_STATUS_REG(i) (DR_REG_TWAI_BASE(i) + 0x8)
+/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0;
+ *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
+ *  message is available
+ */
+#define TWAI_STATUS_RECEIVE_BUFFER    (BIT(0))
+#define TWAI_STATUS_RECEIVE_BUFFER_M  (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S)
+#define TWAI_STATUS_RECEIVE_BUFFER_V  0x00000001U
+#define TWAI_STATUS_RECEIVE_BUFFER_S  0
+/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0;
+ *  1: overrun, a message was lost because there was not enough space for that message
+ *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
+ *  overrun command was given
+ */
+#define TWAI_STATUS_OVERRUN    (BIT(1))
+#define TWAI_STATUS_OVERRUN_M  (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S)
+#define TWAI_STATUS_OVERRUN_V  0x00000001U
+#define TWAI_STATUS_OVERRUN_S  1
+/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0;
+ *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
+ *  CPU cannot access the transmit buffer, a message is either waiting for transmission
+ *  or is in the process of being transmitted
+ */
+#define TWAI_STATUS_TRANSMIT_BUFFER    (BIT(2))
+#define TWAI_STATUS_TRANSMIT_BUFFER_M  (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S)
+#define TWAI_STATUS_TRANSMIT_BUFFER_V  0x00000001U
+#define TWAI_STATUS_TRANSMIT_BUFFER_S  2
+/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0;
+ *  1: complete, last requested transmission has been successfully completed. 0:
+ *  incomplete, previously requested transmission is not yet completed
+ */
+#define TWAI_STATUS_TRANSMISSION_COMPLETE    (BIT(3))
+#define TWAI_STATUS_TRANSMISSION_COMPLETE_M  (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S)
+#define TWAI_STATUS_TRANSMISSION_COMPLETE_V  0x00000001U
+#define TWAI_STATUS_TRANSMISSION_COMPLETE_S  3
+/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0;
+ *  1: receive, the TWAI controller is receiving a message. 0: idle
+ */
+#define TWAI_STATUS_RECEIVE    (BIT(4))
+#define TWAI_STATUS_RECEIVE_M  (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S)
+#define TWAI_STATUS_RECEIVE_V  0x00000001U
+#define TWAI_STATUS_RECEIVE_S  4
+/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0;
+ *  1: transmit, the TWAI controller is transmitting a message. 0: idle
+ */
+#define TWAI_STATUS_TRANSMIT    (BIT(5))
+#define TWAI_STATUS_TRANSMIT_M  (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S)
+#define TWAI_STATUS_TRANSMIT_V  0x00000001U
+#define TWAI_STATUS_TRANSMIT_S  5
+/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0;
+ *  1: error, at least one of the error counters has reached or exceeded the CPU
+ *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
+ *  counters are below the warning limit
+ */
+#define TWAI_STATUS_ERR    (BIT(6))
+#define TWAI_STATUS_ERR_M  (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S)
+#define TWAI_STATUS_ERR_V  0x00000001U
+#define TWAI_STATUS_ERR_S  6
+/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0;
+ *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
+ *  TWAI controller is involved in bus activities
+ */
+#define TWAI_STATUS_NODE_BUS_OFF    (BIT(7))
+#define TWAI_STATUS_NODE_BUS_OFF_M  (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S)
+#define TWAI_STATUS_NODE_BUS_OFF_V  0x00000001U
+#define TWAI_STATUS_NODE_BUS_OFF_S  7
+/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0;
+ *  1: current message is destroyed because of FIFO overflow.
+ */
+#define TWAI_STATUS_MISS    (BIT(8))
+#define TWAI_STATUS_MISS_M  (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S)
+#define TWAI_STATUS_MISS_V  0x00000001U
+#define TWAI_STATUS_MISS_S  8
+
+/** TWAI_INTERRUPT_REG register
+ *  Interrupt signals' register.
+ */
+#define TWAI_INTERRUPT_REG(i) (DR_REG_TWAI_BASE(i) + 0xc)
+/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
+ *  within the interrupt enable register. 0: reset
+ */
+#define TWAI_RECEIVE_INT_ST    (BIT(0))
+#define TWAI_RECEIVE_INT_ST_M  (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S)
+#define TWAI_RECEIVE_INT_ST_V  0x00000001U
+#define TWAI_RECEIVE_INT_ST_S  0
+/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
+ *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_TRANSMIT_INT_ST    (BIT(1))
+#define TWAI_TRANSMIT_INT_ST_M  (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S)
+#define TWAI_TRANSMIT_INT_ST_V  0x00000001U
+#define TWAI_TRANSMIT_INT_ST_S  1
+/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0;
+ *  1: this bit is set on every change (set and clear) of either the error status or
+ *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
+ *  reset
+ */
+#define TWAI_ERR_WARNING_INT_ST    (BIT(2))
+#define TWAI_ERR_WARNING_INT_ST_M  (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S)
+#define TWAI_ERR_WARNING_INT_ST_V  0x00000001U
+#define TWAI_ERR_WARNING_INT_ST_S  2
+/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
+ *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
+ *  DOIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_DATA_OVERRUN_INT_ST    (BIT(3))
+#define TWAI_DATA_OVERRUN_INT_ST_M  (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S)
+#define TWAI_DATA_OVERRUN_INT_ST_V  0x00000001U
+#define TWAI_DATA_OVERRUN_INT_ST_S  3
+/** TWAI_TS_COUNTER_OVFL_INT_ST : RO; bitpos: [4]; default: 0;
+ *  1: this bit is set then the timestamp counter reaches the maximum value and
+ *  overflow.
+ */
+#define TWAI_TS_COUNTER_OVFL_INT_ST    (BIT(4))
+#define TWAI_TS_COUNTER_OVFL_INT_ST_M  (TWAI_TS_COUNTER_OVFL_INT_ST_V << TWAI_TS_COUNTER_OVFL_INT_ST_S)
+#define TWAI_TS_COUNTER_OVFL_INT_ST_V  0x00000001U
+#define TWAI_TS_COUNTER_OVFL_INT_ST_S  4
+/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  1: this bit is set whenever the TWAI controller has reached the error passive
+ *  status (at least one error counter exceeds the protocol-defined level of 127) or if
+ *  the TWAI controller is in the error passive status and enters the error active
+ *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_ERR_PASSIVE_INT_ST    (BIT(5))
+#define TWAI_ERR_PASSIVE_INT_ST_M  (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S)
+#define TWAI_ERR_PASSIVE_INT_ST_V  0x00000001U
+#define TWAI_ERR_PASSIVE_INT_ST_S  5
+/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0;
+ *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
+ *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_ARBITRATION_LOST_INT_ST    (BIT(6))
+#define TWAI_ARBITRATION_LOST_INT_ST_M  (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S)
+#define TWAI_ARBITRATION_LOST_INT_ST_V  0x00000001U
+#define TWAI_ARBITRATION_LOST_INT_ST_S  6
+/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
+ *  the BEIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_BUS_ERR_INT_ST    (BIT(7))
+#define TWAI_BUS_ERR_INT_ST_M  (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S)
+#define TWAI_BUS_ERR_INT_ST_V  0x00000001U
+#define TWAI_BUS_ERR_INT_ST_S  7
+/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0;
+ *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
+ *  this interrupt enable bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_IDLE_INT_ST    (BIT(8))
+#define TWAI_IDLE_INT_ST_M  (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S)
+#define TWAI_IDLE_INT_ST_V  0x00000001U
+#define TWAI_IDLE_INT_ST_S  8
+
+/** TWAI_INTERRUPT_ENABLE_REG register
+ *  Interrupt enable register.
+ */
+#define TWAI_INTERRUPT_ENABLE_REG(i) (DR_REG_TWAI_BASE(i) + 0x10)
+/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
+ *  the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_RECEIVE_INT_ENA    (BIT(0))
+#define TWAI_EXT_RECEIVE_INT_ENA_M  (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S)
+#define TWAI_EXT_RECEIVE_INT_ENA_V  0x00000001U
+#define TWAI_EXT_RECEIVE_INT_ENA_S  0
+/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  1: enabled, when a message has been successfully transmitted or the transmit buffer
+ *  is accessible again (e.g. after an abort transmission command), the TWAI controller
+ *  requests the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_TRANSMIT_INT_ENA    (BIT(1))
+#define TWAI_EXT_TRANSMIT_INT_ENA_M  (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S)
+#define TWAI_EXT_TRANSMIT_INT_ENA_V  0x00000001U
+#define TWAI_EXT_TRANSMIT_INT_ENA_S  1
+/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  1: enabled, if the error or bus status change (see status register. Table 14), the
+ *  TWAI controllerrequests the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_ERR_WARNING_INT_ENA    (BIT(2))
+#define TWAI_EXT_ERR_WARNING_INT_ENA_M  (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S)
+#define TWAI_EXT_ERR_WARNING_INT_ENA_V  0x00000001U
+#define TWAI_EXT_ERR_WARNING_INT_ENA_S  2
+/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
+ *  the TWAI controllerrequests the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA    (BIT(3))
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M  (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S)
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V  0x00000001U
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S  3
+/** TWAI_TS_COUNTER_OVFL_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  enable the timestamp counter overflow interrupt request.
+ */
+#define TWAI_TS_COUNTER_OVFL_INT_ENA    (BIT(4))
+#define TWAI_TS_COUNTER_OVFL_INT_ENA_M  (TWAI_TS_COUNTER_OVFL_INT_ENA_V << TWAI_TS_COUNTER_OVFL_INT_ENA_S)
+#define TWAI_TS_COUNTER_OVFL_INT_ENA_V  0x00000001U
+#define TWAI_TS_COUNTER_OVFL_INT_ENA_S  4
+/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  1: enabled, if the error status of the TWAI controller changes from error active to
+ *  error passive or vice versa, the respective interrupt is requested. 0: disable
+ */
+#define TWAI_ERR_PASSIVE_INT_ENA    (BIT(5))
+#define TWAI_ERR_PASSIVE_INT_ENA_M  (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S)
+#define TWAI_ERR_PASSIVE_INT_ENA_V  0x00000001U
+#define TWAI_ERR_PASSIVE_INT_ENA_S  5
+/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
+ *  is requested. 0: disable
+ */
+#define TWAI_ARBITRATION_LOST_INT_ENA    (BIT(6))
+#define TWAI_ARBITRATION_LOST_INT_ENA_M  (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S)
+#define TWAI_ARBITRATION_LOST_INT_ENA_V  0x00000001U
+#define TWAI_ARBITRATION_LOST_INT_ENA_S  6
+/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  1: enabled, if an bus error has been detected, the TWAI controller requests the
+ *  respective interrupt. 0: disable
+ */
+#define TWAI_BUS_ERR_INT_ENA    (BIT(7))
+#define TWAI_BUS_ERR_INT_ENA_M  (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S)
+#define TWAI_BUS_ERR_INT_ENA_V  0x00000001U
+#define TWAI_BUS_ERR_INT_ENA_S  7
+/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0;
+ *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
+ *  respective interrupt. 0: disable
+ */
+#define TWAI_IDLE_INT_ENA    (BIT(8))
+#define TWAI_IDLE_INT_ENA_M  (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S)
+#define TWAI_IDLE_INT_ENA_V  0x00000001U
+#define TWAI_IDLE_INT_ENA_S  8
+
+/** TWAI_BUS_TIMING_0_REG register
+ *  Bit timing configuration register 0.
+ */
+#define TWAI_BUS_TIMING_0_REG(i) (DR_REG_TWAI_BASE(i) + 0x18)
+/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0;
+ *  The period of the TWAI system clock is programmable and determines the individual
+ *  bit timing. Software has R/W permission in reset mode and RO permission in
+ *  operation mode.
+ */
+#define TWAI_BAUD_PRESC    0x00003FFFU
+#define TWAI_BAUD_PRESC_M  (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S)
+#define TWAI_BAUD_PRESC_V  0x00003FFFU
+#define TWAI_BAUD_PRESC_S  0
+/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0;
+ *  The synchronization jump width defines the maximum number of clock cycles a bit
+ *  period may be shortened or lengthened. Software has R/W permission in reset mode
+ *  and RO in operation mode.
+ */
+#define TWAI_SYNC_JUMP_WIDTH    0x00000003U
+#define TWAI_SYNC_JUMP_WIDTH_M  (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S)
+#define TWAI_SYNC_JUMP_WIDTH_V  0x00000003U
+#define TWAI_SYNC_JUMP_WIDTH_S  14
+
+/** TWAI_BUS_TIMING_1_REG register
+ *  Bit timing configuration register 1.
+ */
+#define TWAI_BUS_TIMING_1_REG(i) (DR_REG_TWAI_BASE(i) + 0x1c)
+/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0;
+ *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
+ *  reset mode and RO in operation mode.
+ */
+#define TWAI_TIME_SEGMENT1    0x0000000FU
+#define TWAI_TIME_SEGMENT1_M  (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S)
+#define TWAI_TIME_SEGMENT1_V  0x0000000FU
+#define TWAI_TIME_SEGMENT1_S  0
+/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0;
+ *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
+ *  reset mode and RO in operation mode.
+ */
+#define TWAI_TIME_SEGMENT2    0x00000007U
+#define TWAI_TIME_SEGMENT2_M  (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S)
+#define TWAI_TIME_SEGMENT2_V  0x00000007U
+#define TWAI_TIME_SEGMENT2_S  4
+/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0;
+ *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
+ *  Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_TIME_SAMPLING    (BIT(7))
+#define TWAI_TIME_SAMPLING_M  (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S)
+#define TWAI_TIME_SAMPLING_V  0x00000001U
+#define TWAI_TIME_SAMPLING_S  7
+
+/** TWAI_ARB_LOST_CAP_REG register
+ *  TWAI arbiter lost capture register.
+ */
+#define TWAI_ARB_LOST_CAP_REG(i) (DR_REG_TWAI_BASE(i) + 0x2c)
+/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0;
+ *  This register contains information about the bit position of losing arbitration.
+ */
+#define TWAI_ARBITRATION_LOST_CAPTURE    0x0000001FU
+#define TWAI_ARBITRATION_LOST_CAPTURE_M  (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S)
+#define TWAI_ARBITRATION_LOST_CAPTURE_V  0x0000001FU
+#define TWAI_ARBITRATION_LOST_CAPTURE_S  0
+
+/** TWAI_ERR_CODE_CAP_REG register
+ *  TWAI error info capture register.
+ */
+#define TWAI_ERR_CODE_CAP_REG(i) (DR_REG_TWAI_BASE(i) + 0x30)
+/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0;
+ *  This register contains information about the location of errors on the bus.
+ */
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT    0x0000001FU
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M  (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S)
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V  0x0000001FU
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S  0
+/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0;
+ *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
+ */
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION    (BIT(5))
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M  (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S)
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V  0x00000001U
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S  5
+/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0;
+ *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
+ */
+#define TWAI_ERR_CAPTURE_CODE_TYPE    0x00000003U
+#define TWAI_ERR_CAPTURE_CODE_TYPE_M  (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S)
+#define TWAI_ERR_CAPTURE_CODE_TYPE_V  0x00000003U
+#define TWAI_ERR_CAPTURE_CODE_TYPE_S  6
+
+/** TWAI_ERR_WARNING_LIMIT_REG register
+ *  TWAI error threshold configuration register.
+ */
+#define TWAI_ERR_WARNING_LIMIT_REG(i) (DR_REG_TWAI_BASE(i) + 0x34)
+/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96;
+ *  The threshold that trigger error warning interrupt when this interrupt is enabled.
+ *  Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_ERR_WARNING_LIMIT    0x000000FFU
+#define TWAI_ERR_WARNING_LIMIT_M  (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S)
+#define TWAI_ERR_WARNING_LIMIT_V  0x000000FFU
+#define TWAI_ERR_WARNING_LIMIT_S  0
+
+/** TWAI_RX_ERR_CNT_REG register
+ *  Rx error counter register.
+ */
+#define TWAI_RX_ERR_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x38)
+/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
+ *  The RX error counter register reflects the current value of the transmit error
+ *  counter. Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_RX_ERR_CNT    0x000000FFU
+#define TWAI_RX_ERR_CNT_M  (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S)
+#define TWAI_RX_ERR_CNT_V  0x000000FFU
+#define TWAI_RX_ERR_CNT_S  0
+
+/** TWAI_TX_ERR_CNT_REG register
+ *  Tx error counter register.
+ */
+#define TWAI_TX_ERR_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x3c)
+/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
+ *  The TX error counter register reflects the current value of the transmit error
+ *  counter. Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_TX_ERR_CNT    0x000000FFU
+#define TWAI_TX_ERR_CNT_M  (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S)
+#define TWAI_TX_ERR_CNT_V  0x000000FFU
+#define TWAI_TX_ERR_CNT_S  0
+
+/** TWAI_DATA_0_REG register
+ *  Data register 0.
+ */
+#define TWAI_DATA_0_REG(i) (DR_REG_TWAI_BASE(i) + 0x40)
+/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 0 and when
+ *  software initiate read operation, it is rx data register 0.
+ */
+#define TWAI_DATA_0    0x000000FFU
+#define TWAI_DATA_0_M  (TWAI_DATA_0_V << TWAI_DATA_0_S)
+#define TWAI_DATA_0_V  0x000000FFU
+#define TWAI_DATA_0_S  0
+
+/** TWAI_DATA_1_REG register
+ *  Data register 1.
+ */
+#define TWAI_DATA_1_REG(i) (DR_REG_TWAI_BASE(i) + 0x44)
+/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 1 and when
+ *  software initiate read operation, it is rx data register 1.
+ */
+#define TWAI_DATA_1    0x000000FFU
+#define TWAI_DATA_1_M  (TWAI_DATA_1_V << TWAI_DATA_1_S)
+#define TWAI_DATA_1_V  0x000000FFU
+#define TWAI_DATA_1_S  0
+
+/** TWAI_DATA_2_REG register
+ *  Data register 2.
+ */
+#define TWAI_DATA_2_REG(i) (DR_REG_TWAI_BASE(i) + 0x48)
+/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 2 and when
+ *  software initiate read operation, it is rx data register 2.
+ */
+#define TWAI_DATA_2    0x000000FFU
+#define TWAI_DATA_2_M  (TWAI_DATA_2_V << TWAI_DATA_2_S)
+#define TWAI_DATA_2_V  0x000000FFU
+#define TWAI_DATA_2_S  0
+
+/** TWAI_DATA_3_REG register
+ *  Data register 3.
+ */
+#define TWAI_DATA_3_REG(i) (DR_REG_TWAI_BASE(i) + 0x4c)
+/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 3 and when
+ *  software initiate read operation, it is rx data register 3.
+ */
+#define TWAI_DATA_3    0x000000FFU
+#define TWAI_DATA_3_M  (TWAI_DATA_3_V << TWAI_DATA_3_S)
+#define TWAI_DATA_3_V  0x000000FFU
+#define TWAI_DATA_3_S  0
+
+/** TWAI_DATA_4_REG register
+ *  Data register 4.
+ */
+#define TWAI_DATA_4_REG(i) (DR_REG_TWAI_BASE(i) + 0x50)
+/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 4 and when
+ *  software initiate read operation, it is rx data register 4.
+ */
+#define TWAI_DATA_4    0x000000FFU
+#define TWAI_DATA_4_M  (TWAI_DATA_4_V << TWAI_DATA_4_S)
+#define TWAI_DATA_4_V  0x000000FFU
+#define TWAI_DATA_4_S  0
+
+/** TWAI_DATA_5_REG register
+ *  Data register 5.
+ */
+#define TWAI_DATA_5_REG(i) (DR_REG_TWAI_BASE(i) + 0x54)
+/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 5 and when
+ *  software initiate read operation, it is rx data register 5.
+ */
+#define TWAI_DATA_5    0x000000FFU
+#define TWAI_DATA_5_M  (TWAI_DATA_5_V << TWAI_DATA_5_S)
+#define TWAI_DATA_5_V  0x000000FFU
+#define TWAI_DATA_5_S  0
+
+/** TWAI_DATA_6_REG register
+ *  Data register 6.
+ */
+#define TWAI_DATA_6_REG(i) (DR_REG_TWAI_BASE(i) + 0x58)
+/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 6 and when
+ *  software initiate read operation, it is rx data register 6.
+ */
+#define TWAI_DATA_6    0x000000FFU
+#define TWAI_DATA_6_M  (TWAI_DATA_6_V << TWAI_DATA_6_S)
+#define TWAI_DATA_6_V  0x000000FFU
+#define TWAI_DATA_6_S  0
+
+/** TWAI_DATA_7_REG register
+ *  Data register 7.
+ */
+#define TWAI_DATA_7_REG(i) (DR_REG_TWAI_BASE(i) + 0x5c)
+/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 7 and when
+ *  software initiate read operation, it is rx data register 7.
+ */
+#define TWAI_DATA_7    0x000000FFU
+#define TWAI_DATA_7_M  (TWAI_DATA_7_V << TWAI_DATA_7_S)
+#define TWAI_DATA_7_V  0x000000FFU
+#define TWAI_DATA_7_S  0
+
+/** TWAI_DATA_8_REG register
+ *  Data register 8.
+ */
+#define TWAI_DATA_8_REG(i) (DR_REG_TWAI_BASE(i) + 0x60)
+/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 8 and when software initiate read operation, it
+ *  is rx data register 8.
+ */
+#define TWAI_DATA_8    0x000000FFU
+#define TWAI_DATA_8_M  (TWAI_DATA_8_V << TWAI_DATA_8_S)
+#define TWAI_DATA_8_V  0x000000FFU
+#define TWAI_DATA_8_S  0
+
+/** TWAI_DATA_9_REG register
+ *  Data register 9.
+ */
+#define TWAI_DATA_9_REG(i) (DR_REG_TWAI_BASE(i) + 0x64)
+/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 9 and when software initiate read operation, it
+ *  is rx data register 9.
+ */
+#define TWAI_DATA_9    0x000000FFU
+#define TWAI_DATA_9_M  (TWAI_DATA_9_V << TWAI_DATA_9_S)
+#define TWAI_DATA_9_V  0x000000FFU
+#define TWAI_DATA_9_S  0
+
+/** TWAI_DATA_10_REG register
+ *  Data register 10.
+ */
+#define TWAI_DATA_10_REG(i) (DR_REG_TWAI_BASE(i) + 0x68)
+/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 10 and when software initiate read operation, it
+ *  is rx data register 10.
+ */
+#define TWAI_DATA_10    0x000000FFU
+#define TWAI_DATA_10_M  (TWAI_DATA_10_V << TWAI_DATA_10_S)
+#define TWAI_DATA_10_V  0x000000FFU
+#define TWAI_DATA_10_S  0
+
+/** TWAI_DATA_11_REG register
+ *  Data register 11.
+ */
+#define TWAI_DATA_11_REG(i) (DR_REG_TWAI_BASE(i) + 0x6c)
+/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 11 and when software initiate read operation, it
+ *  is rx data register 11.
+ */
+#define TWAI_DATA_11    0x000000FFU
+#define TWAI_DATA_11_M  (TWAI_DATA_11_V << TWAI_DATA_11_S)
+#define TWAI_DATA_11_V  0x000000FFU
+#define TWAI_DATA_11_S  0
+
+/** TWAI_DATA_12_REG register
+ *  Data register 12.
+ */
+#define TWAI_DATA_12_REG(i) (DR_REG_TWAI_BASE(i) + 0x70)
+/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 12 and when software initiate read operation, it
+ *  is rx data register 12.
+ */
+#define TWAI_DATA_12    0x000000FFU
+#define TWAI_DATA_12_M  (TWAI_DATA_12_V << TWAI_DATA_12_S)
+#define TWAI_DATA_12_V  0x000000FFU
+#define TWAI_DATA_12_S  0
+
+/** TWAI_RX_MESSAGE_COUNTER_REG register
+ *  Received message counter register.
+ */
+#define TWAI_RX_MESSAGE_COUNTER_REG(i) (DR_REG_TWAI_BASE(i) + 0x74)
+/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0;
+ *  Reflects the number of messages available within the RXFIFO. The value is
+ *  incremented with each receive event and decremented by the release receive buffer
+ *  command.
+ */
+#define TWAI_RX_MESSAGE_COUNTER    0x0000007FU
+#define TWAI_RX_MESSAGE_COUNTER_M  (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S)
+#define TWAI_RX_MESSAGE_COUNTER_V  0x0000007FU
+#define TWAI_RX_MESSAGE_COUNTER_S  0
+
+/** TWAI_CLOCK_DIVIDER_REG register
+ *  Clock divider register.
+ */
+#define TWAI_CLOCK_DIVIDER_REG(i) (DR_REG_TWAI_BASE(i) + 0x7c)
+/** TWAI_CD : R/W; bitpos: [7:0]; default: 0;
+ *  These bits are used to define the frequency at the external CLKOUT pin.
+ */
+#define TWAI_CD    0x000000FFU
+#define TWAI_CD_M  (TWAI_CD_V << TWAI_CD_S)
+#define TWAI_CD_V  0x000000FFU
+#define TWAI_CD_S  0
+/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0;
+ *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
+ *  R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_CLOCK_OFF    (BIT(8))
+#define TWAI_CLOCK_OFF_M  (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S)
+#define TWAI_CLOCK_OFF_V  0x00000001U
+#define TWAI_CLOCK_OFF_S  8
+
+/** TWAI_SW_STANDBY_CFG_REG register
+ *  Software configure standby pin directly.
+ */
+#define TWAI_SW_STANDBY_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x80)
+/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable standby pin.
+ */
+#define TWAI_SW_STANDBY_EN    (BIT(0))
+#define TWAI_SW_STANDBY_EN_M  (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S)
+#define TWAI_SW_STANDBY_EN_V  0x00000001U
+#define TWAI_SW_STANDBY_EN_S  0
+/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1;
+ *  Clear standby pin.
+ */
+#define TWAI_SW_STANDBY_CLR    (BIT(1))
+#define TWAI_SW_STANDBY_CLR_M  (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S)
+#define TWAI_SW_STANDBY_CLR_V  0x00000001U
+#define TWAI_SW_STANDBY_CLR_S  1
+
+/** TWAI_HW_CFG_REG register
+ *  Hardware configure standby pin.
+ */
+#define TWAI_HW_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x84)
+/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable function that hardware control standby pin.
+ */
+#define TWAI_HW_STANDBY_EN    (BIT(0))
+#define TWAI_HW_STANDBY_EN_M  (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S)
+#define TWAI_HW_STANDBY_EN_V  0x00000001U
+#define TWAI_HW_STANDBY_EN_S  0
+
+/** TWAI_HW_STANDBY_CNT_REG register
+ *  Configure standby counter.
+ */
+#define TWAI_HW_STANDBY_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x88)
+/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1;
+ *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
+ *  is enabled.
+ */
+#define TWAI_STANDBY_WAIT_CNT    0xFFFFFFFFU
+#define TWAI_STANDBY_WAIT_CNT_M  (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S)
+#define TWAI_STANDBY_WAIT_CNT_V  0xFFFFFFFFU
+#define TWAI_STANDBY_WAIT_CNT_S  0
+
+/** TWAI_IDLE_INTR_CNT_REG register
+ *  Configure idle interrupt counter.
+ */
+#define TWAI_IDLE_INTR_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x8c)
+/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1;
+ *  Configure the number of cycles before triggering idle interrupt.
+ */
+#define TWAI_IDLE_INTR_CNT    0xFFFFFFFFU
+#define TWAI_IDLE_INTR_CNT_M  (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S)
+#define TWAI_IDLE_INTR_CNT_V  0xFFFFFFFFU
+#define TWAI_IDLE_INTR_CNT_S  0
+
+/** TWAI_ECO_CFG_REG register
+ *  ECO configuration register.
+ */
+#define TWAI_ECO_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x90)
+/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  Enable eco module.
+ */
+#define TWAI_RDN_ENA    (BIT(0))
+#define TWAI_RDN_ENA_M  (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S)
+#define TWAI_RDN_ENA_V  0x00000001U
+#define TWAI_RDN_ENA_S  0
+/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1;
+ *  Output of eco module.
+ */
+#define TWAI_RDN_RESULT    (BIT(1))
+#define TWAI_RDN_RESULT_M  (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S)
+#define TWAI_RDN_RESULT_V  0x00000001U
+#define TWAI_RDN_RESULT_S  1
+
+/** TWAI_TIMESTAMP_DATA_REG register
+ *  Timestamp data register
+ */
+#define TWAI_TIMESTAMP_DATA_REG(i) (DR_REG_TWAI_BASE(i) + 0x94)
+/** TWAI_TIMESTAMP_DATA : RO; bitpos: [31:0]; default: 0;
+ *  Data of timestamp of a CAN frame.
+ */
+#define TWAI_TIMESTAMP_DATA    0xFFFFFFFFU
+#define TWAI_TIMESTAMP_DATA_M  (TWAI_TIMESTAMP_DATA_V << TWAI_TIMESTAMP_DATA_S)
+#define TWAI_TIMESTAMP_DATA_V  0xFFFFFFFFU
+#define TWAI_TIMESTAMP_DATA_S  0
+
+/** TWAI_TIMESTAMP_PRESCALER_REG register
+ *  Timestamp configuration register
+ */
+#define TWAI_TIMESTAMP_PRESCALER_REG(i) (DR_REG_TWAI_BASE(i) + 0x98)
+/** TWAI_TS_DIV_NUM : R/W; bitpos: [15:0]; default: 31;
+ *  Configures the clock division number of timestamp counter.
+ */
+#define TWAI_TS_DIV_NUM    0x0000FFFFU
+#define TWAI_TS_DIV_NUM_M  (TWAI_TS_DIV_NUM_V << TWAI_TS_DIV_NUM_S)
+#define TWAI_TS_DIV_NUM_V  0x0000FFFFU
+#define TWAI_TS_DIV_NUM_S  0
+
+/** TWAI_TIMESTAMP_CFG_REG register
+ *  Timestamp configuration register
+ */
+#define TWAI_TIMESTAMP_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x9c)
+/** TWAI_TS_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  enable the timestamp collection function.
+ */
+#define TWAI_TS_ENABLE    (BIT(0))
+#define TWAI_TS_ENABLE_M  (TWAI_TS_ENABLE_V << TWAI_TS_ENABLE_S)
+#define TWAI_TS_ENABLE_V  0x00000001U
+#define TWAI_TS_ENABLE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/twai_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/twai_struct.h
new file mode 100644
index 0000000000..53bbc39af0
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/twai_struct.h
@@ -0,0 +1,619 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of mode register
+ *  TWAI mode register.
+ */
+typedef union {
+    struct {
+        /** reset_mode : R/W; bitpos: [0]; default: 1;
+         *  1: reset, detection of a set reset mode bit results in aborting the current
+         *  transmission/reception of a message and entering the reset mode. 0: normal, on the
+         *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
+         *  operating mode.
+         */
+        uint32_t reset_mode:1;
+        /** listen_only_mode : R/W; bitpos: [1]; default: 0;
+         *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
+         *  TWAI-bus, even if a message is received successfully. The error counters are
+         *  stopped at the current value. 0: normal.
+         */
+        uint32_t listen_only_mode:1;
+        /** self_test_mode : R/W; bitpos: [2]; default: 0;
+         *  1: self test, in this mode a full node test is possible without any other active
+         *  node on the bus using the self reception request command. The TWAI controller will
+         *  perform a successful transmission, even if there is no acknowledge received. 0:
+         *  normal, an acknowledge is required for successful transmission.
+         */
+        uint32_t self_test_mode:1;
+        /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0;
+         *  1:single, the single acceptance filter option is enabled (one filter with the
+         *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
+         *  (two filters, each with the length of 16 bit are active).
+         */
+        uint32_t acceptance_filter_mode:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} twai_mode_reg_t;
+
+/** Type of cmd register
+ *  TWAI command register.
+ */
+typedef union {
+    struct {
+        /** tx_request : WO; bitpos: [0]; default: 0;
+         *  1: present, a message shall be transmitted. 0: absent
+         */
+        uint32_t tx_request:1;
+        /** abort_tx : WO; bitpos: [1]; default: 0;
+         *  1: present, if not already in progress, a pending transmission request is
+         *  cancelled. 0: absent
+         */
+        uint32_t abort_tx:1;
+        /** release_buffer : WO; bitpos: [2]; default: 0;
+         *  1: released, the receive buffer, representing the message memory space in the
+         *  RXFIFO is released. 0: no action
+         */
+        uint32_t release_buffer:1;
+        /** clear_data_overrun : WO; bitpos: [3]; default: 0;
+         *  1: clear, the data overrun status bit is cleared. 0: no action.
+         */
+        uint32_t clear_data_overrun:1;
+        /** self_rx_request : WO; bitpos: [4]; default: 0;
+         *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
+         */
+        uint32_t self_rx_request:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} twai_cmd_reg_t;
+
+/** Type of bus_timing_0 register
+ *  Bit timing configuration register 0.
+ */
+typedef union {
+    struct {
+        /** baud_presc : R/W; bitpos: [13:0]; default: 0;
+         *  The period of the TWAI system clock is programmable and determines the individual
+         *  bit timing. Software has R/W permission in reset mode and RO permission in
+         *  operation mode.
+         */
+        uint32_t baud_presc:14;
+        /** sync_jump_width : R/W; bitpos: [15:14]; default: 0;
+         *  The synchronization jump width defines the maximum number of clock cycles a bit
+         *  period may be shortened or lengthened. Software has R/W permission in reset mode
+         *  and RO in operation mode.
+         */
+        uint32_t sync_jump_width:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} twai_bus_timing_0_reg_t;
+
+/** Type of bus_timing_1 register
+ *  Bit timing configuration register 1.
+ */
+typedef union {
+    struct {
+        /** time_segment1 : R/W; bitpos: [3:0]; default: 0;
+         *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
+         *  reset mode and RO in operation mode.
+         */
+        uint32_t time_segment1:4;
+        /** time_segment2 : R/W; bitpos: [6:4]; default: 0;
+         *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
+         *  reset mode and RO in operation mode.
+         */
+        uint32_t time_segment2:3;
+        /** time_sampling : R/W; bitpos: [7]; default: 0;
+         *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
+         *  Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t time_sampling:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_bus_timing_1_reg_t;
+
+/** Type of err_warning_limit register
+ *  TWAI error threshold configuration register.
+ */
+typedef union {
+    struct {
+        /** err_warning_limit : R/W; bitpos: [7:0]; default: 96;
+         *  The threshold that trigger error warning interrupt when this interrupt is enabled.
+         *  Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t err_warning_limit:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_err_warning_limit_reg_t;
+
+/** Type of clock_divider register
+ *  Clock divider register.
+ */
+typedef union {
+    struct {
+        /** cd : R/W; bitpos: [7:0]; default: 0;
+         *  These bits are used to define the frequency at the external CLKOUT pin.
+         */
+        uint32_t cd:8;
+        /** clock_off : R/W; bitpos: [8]; default: 0;
+         *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
+         *  R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t clock_off:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_clock_divider_reg_t;
+
+/** Type of sw_standby_cfg register
+ *  Software configure standby pin directly.
+ */
+typedef union {
+    struct {
+        /** sw_standby_en : R/W; bitpos: [0]; default: 0;
+         *  Enable standby pin.
+         */
+        uint32_t sw_standby_en:1;
+        /** sw_standby_clr : R/W; bitpos: [1]; default: 1;
+         *  Clear standby pin.
+         */
+        uint32_t sw_standby_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twai_sw_standby_cfg_reg_t;
+
+/** Type of hw_cfg register
+ *  Hardware configure standby pin.
+ */
+typedef union {
+    struct {
+        /** hw_standby_en : R/W; bitpos: [0]; default: 0;
+         *  Enable function that hardware control standby pin.
+         */
+        uint32_t hw_standby_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} twai_hw_cfg_reg_t;
+
+/** Type of hw_standby_cnt register
+ *  Configure standby counter.
+ */
+typedef union {
+    struct {
+        /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1;
+         *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
+         *  is enabled.
+         */
+        uint32_t standby_wait_cnt:32;
+    };
+    uint32_t val;
+} twai_hw_standby_cnt_reg_t;
+
+/** Type of idle_intr_cnt register
+ *  Configure idle interrupt counter.
+ */
+typedef union {
+    struct {
+        /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1;
+         *  Configure the number of cycles before triggering idle interrupt.
+         */
+        uint32_t idle_intr_cnt:32;
+    };
+    uint32_t val;
+} twai_idle_intr_cnt_reg_t;
+
+/** Type of eco_cfg register
+ *  ECO configuration register.
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable eco module.
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 1;
+         *  Output of eco module.
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twai_eco_cfg_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of status register
+ *  TWAI status register.
+ */
+typedef union {
+    struct {
+        /** status_receive_buffer : RO; bitpos: [0]; default: 0;
+         *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
+         *  message is available
+         */
+        uint32_t status_receive_buffer:1;
+        /** status_overrun : RO; bitpos: [1]; default: 0;
+         *  1: overrun, a message was lost because there was not enough space for that message
+         *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
+         *  overrun command was given
+         */
+        uint32_t status_overrun:1;
+        /** status_transmit_buffer : RO; bitpos: [2]; default: 0;
+         *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
+         *  CPU cannot access the transmit buffer, a message is either waiting for transmission
+         *  or is in the process of being transmitted
+         */
+        uint32_t status_transmit_buffer:1;
+        /** status_transmission_complete : RO; bitpos: [3]; default: 0;
+         *  1: complete, last requested transmission has been successfully completed. 0:
+         *  incomplete, previously requested transmission is not yet completed
+         */
+        uint32_t status_transmission_complete:1;
+        /** status_receive : RO; bitpos: [4]; default: 0;
+         *  1: receive, the TWAI controller is receiving a message. 0: idle
+         */
+        uint32_t status_receive:1;
+        /** status_transmit : RO; bitpos: [5]; default: 0;
+         *  1: transmit, the TWAI controller is transmitting a message. 0: idle
+         */
+        uint32_t status_transmit:1;
+        /** status_err : RO; bitpos: [6]; default: 0;
+         *  1: error, at least one of the error counters has reached or exceeded the CPU
+         *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
+         *  counters are below the warning limit
+         */
+        uint32_t status_err:1;
+        /** status_node_bus_off : RO; bitpos: [7]; default: 0;
+         *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
+         *  TWAI controller is involved in bus activities
+         */
+        uint32_t status_node_bus_off:1;
+        /** status_miss : RO; bitpos: [8]; default: 0;
+         *  1: current message is destroyed because of FIFO overflow.
+         */
+        uint32_t status_miss:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_status_reg_t;
+
+/** Type of arb_lost_cap register
+ *  TWAI arbiter lost capture register.
+ */
+typedef union {
+    struct {
+        /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0;
+         *  This register contains information about the bit position of losing arbitration.
+         */
+        uint32_t arbitration_lost_capture:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} twai_arb_lost_cap_reg_t;
+
+/** Type of err_code_cap register
+ *  TWAI error info capture register.
+ */
+typedef union {
+    struct {
+        /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0;
+         *  This register contains information about the location of errors on the bus.
+         */
+        uint32_t err_capture_code_segment:5;
+        /** err_capture_code_direction : RO; bitpos: [5]; default: 0;
+         *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
+         */
+        uint32_t err_capture_code_direction:1;
+        /** err_capture_code_type : RO; bitpos: [7:6]; default: 0;
+         *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
+         */
+        uint32_t err_capture_code_type:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_err_code_cap_reg_t;
+
+/** Type of rx_err_cnt register
+ *  Rx error counter register.
+ */
+typedef union {
+    struct {
+        /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0;
+         *  The RX error counter register reflects the current value of the transmit error
+         *  counter. Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t rx_err_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_rx_err_cnt_reg_t;
+
+/** Type of tx_err_cnt register
+ *  Tx error counter register.
+ */
+typedef union {
+    struct {
+        /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0;
+         *  The TX error counter register reflects the current value of the transmit error
+         *  counter. Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t tx_err_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_tx_err_cnt_reg_t;
+
+/** Type of rx_message_counter register
+ *  Received message counter register.
+ */
+typedef union {
+    struct {
+        /** rx_message_counter : RO; bitpos: [6:0]; default: 0;
+         *  Reflects the number of messages available within the RXFIFO. The value is
+         *  incremented with each receive event and decremented by the release receive buffer
+         *  command.
+         */
+        uint32_t rx_message_counter:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} twai_rx_message_counter_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of interrupt register
+ *  Interrupt signals' register.
+ */
+typedef union {
+    struct {
+        /** receive_int_st : RO; bitpos: [0]; default: 0;
+         *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
+         *  within the interrupt enable register. 0: reset
+         */
+        uint32_t receive_int_st:1;
+        /** transmit_int_st : RO; bitpos: [1]; default: 0;
+         *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
+         *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t transmit_int_st:1;
+        /** err_warning_int_st : RO; bitpos: [2]; default: 0;
+         *  1: this bit is set on every change (set and clear) of either the error status or
+         *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
+         *  reset
+         */
+        uint32_t err_warning_int_st:1;
+        /** data_overrun_int_st : RO; bitpos: [3]; default: 0;
+         *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
+         *  DOIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t data_overrun_int_st:1;
+        /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0;
+         *  1: this bit is set then the timestamp counter reaches the maximum value and
+         *  overflow.
+         */
+        uint32_t ts_counter_ovfl_int_st:1;
+        /** err_passive_int_st : RO; bitpos: [5]; default: 0;
+         *  1: this bit is set whenever the TWAI controller has reached the error passive
+         *  status (at least one error counter exceeds the protocol-defined level of 127) or if
+         *  the TWAI controller is in the error passive status and enters the error active
+         *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t err_passive_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0;
+         *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
+         *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** bus_err_int_st : RO; bitpos: [7]; default: 0;
+         *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
+         *  the BEIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t bus_err_int_st:1;
+        /** idle_int_st : RO; bitpos: [8]; default: 0;
+         *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
+         *  this interrupt enable bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t idle_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_interrupt_status_reg_t;
+
+/** Type of interrupt_enable register
+ *  Interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0;
+         *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
+         *  the respective interrupt. 0: disable
+         */
+        uint32_t ext_receive_int_ena:1;
+        /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0;
+         *  1: enabled, when a message has been successfully transmitted or the transmit buffer
+         *  is accessible again (e.g. after an abort transmission command), the TWAI controller
+         *  requests the respective interrupt. 0: disable
+         */
+        uint32_t ext_transmit_int_ena:1;
+        /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0;
+         *  1: enabled, if the error or bus status change (see status register. Table 14), the
+         *  TWAI controllerrequests the respective interrupt. 0: disable
+         */
+        uint32_t ext_err_warning_int_ena:1;
+        /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
+         *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
+         *  the TWAI controllerrequests the respective interrupt. 0: disable
+         */
+        uint32_t ext_data_overrun_int_ena:1;
+        /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0;
+         *  enable the timestamp counter overflow interrupt request.
+         */
+        uint32_t ts_counter_ovfl_int_ena:1;
+        /** err_passive_int_ena : R/W; bitpos: [5]; default: 0;
+         *  1: enabled, if the error status of the TWAI controller changes from error active to
+         *  error passive or vice versa, the respective interrupt is requested. 0: disable
+         */
+        uint32_t err_passive_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0;
+         *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
+         *  is requested. 0: disable
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** bus_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  1: enabled, if an bus error has been detected, the TWAI controller requests the
+         *  respective interrupt. 0: disable
+         */
+        uint32_t bus_err_int_ena:1;
+        /** idle_int_ena : RO; bitpos: [8]; default: 0;
+         *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
+         *  respective interrupt. 0: disable
+         */
+        uint32_t idle_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_interrupt_enable_reg_t;
+
+
+/** Group: Data Registers */
+/** Type of buffer register
+ *  TX RX Buffer.
+ */
+typedef union {
+    struct {
+        /** byte : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 0 and when
+         *  software initiate read operation, it is rx data register 0.
+         */
+        uint32_t byte:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_tx_rx_buffer_reg_t;
+
+typedef struct {
+    union {
+        struct {
+            uint32_t byte: 8;           /* ACRx[7:0] Acceptance Code */
+            uint32_t reserved8: 24;     /* Internal Reserved */
+        };
+        uint32_t val;
+    } acr[4];
+    union {
+        struct {
+            uint32_t byte: 8;           /* AMRx[7:0] Acceptance Mask */
+            uint32_t reserved8: 24;     /* Internal Reserved */
+        };
+        uint32_t val;
+    } amr[4];
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+} acceptance_filter_reg_t;
+
+/** Group: Timestamp Register */
+/** Type of timestamp_data register
+ *  Timestamp data register
+ */
+typedef union {
+    struct {
+        /** timestamp_data : RO; bitpos: [31:0]; default: 0;
+         *  Data of timestamp of a CAN frame.
+         */
+        uint32_t timestamp_data:32;
+    };
+    uint32_t val;
+} twai_timestamp_data_reg_t;
+
+/** Type of timestamp_prescaler register
+ *  Timestamp configuration register
+ */
+typedef union {
+    struct {
+        /** ts_div_num : R/W; bitpos: [15:0]; default: 31;
+         *  Configures the clock division number of timestamp counter.
+         */
+        uint32_t ts_div_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} twai_timestamp_prescaler_reg_t;
+
+/** Type of timestamp_cfg register
+ *  Timestamp configuration register
+ */
+typedef union {
+    struct {
+        /** ts_enable : R/W; bitpos: [0]; default: 0;
+         *  enable the timestamp collection function.
+         */
+        uint32_t ts_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} twai_timestamp_cfg_reg_t;
+
+
+typedef struct twai_dev_t {
+    volatile twai_mode_reg_t mode;
+    volatile twai_cmd_reg_t cmd;
+    volatile twai_status_reg_t status;
+    volatile twai_interrupt_status_reg_t interrupt_st;
+    volatile twai_interrupt_enable_reg_t interrupt_ena;
+    uint32_t reserved_014;
+    volatile twai_bus_timing_0_reg_t bus_timing_0;
+    volatile twai_bus_timing_1_reg_t bus_timing_1;
+    uint32_t reserved_020[3];
+    volatile twai_arb_lost_cap_reg_t arb_lost_cap;
+    volatile twai_err_code_cap_reg_t err_code_cap;
+    volatile twai_err_warning_limit_reg_t err_warning_limit;
+    volatile twai_rx_err_cnt_reg_t rx_err_cnt;
+    volatile twai_tx_err_cnt_reg_t tx_err_cnt;
+    volatile union {
+        acceptance_filter_reg_t acceptance_filter;
+        twai_tx_rx_buffer_reg_t tx_rx_buffer[13];
+    };
+    volatile twai_rx_message_counter_reg_t rx_message_counter;
+    uint32_t reserved_078;
+    volatile twai_clock_divider_reg_t clock_divider;
+    volatile twai_sw_standby_cfg_reg_t sw_standby_cfg;
+    volatile twai_hw_cfg_reg_t hw_cfg;
+    volatile twai_hw_standby_cnt_reg_t hw_standby_cnt;
+    volatile twai_idle_intr_cnt_reg_t idle_intr_cnt;
+    volatile twai_eco_cfg_reg_t eco_cfg;
+    volatile twai_timestamp_data_reg_t timestamp_data;
+    volatile twai_timestamp_prescaler_reg_t timestamp_prescaler;
+    volatile twai_timestamp_cfg_reg_t timestamp_cfg;
+} twai_dev_t;
+
+extern twai_dev_t TWAI0;
+extern twai_dev_t TWAI1;
+extern twai_dev_t TWAI2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_reg.h
new file mode 100644
index 0000000000..c782014e86
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_reg.h
@@ -0,0 +1,1579 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** UART_FIFO_REG register
+ *  FIFO data register
+ */
+#define UART_FIFO_REG(i) (DR_REG_UART_BASE(i) + 0x0)
+/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART $n accesses FIFO via this register.
+ */
+#define UART_RXFIFO_RD_BYTE    0x000000FFU
+#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
+#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
+#define UART_RXFIFO_RD_BYTE_S  0
+
+/** UART_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define UART_INT_RAW_REG(i) (DR_REG_UART_BASE(i) + 0x4)
+/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
+#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
+#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
+#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_PARITY_ERR_INT_RAW_S  2
+/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define UART_FRM_ERR_INT_RAW    (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
+#define UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_FRM_ERR_INT_RAW_S  3
+/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
+#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define UART_DSR_CHG_INT_RAW    (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
+#define UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define UART_DSR_CHG_INT_RAW_S  5
+/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define UART_CTS_CHG_INT_RAW    (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
+#define UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define UART_CTS_CHG_INT_RAW_S  6
+/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define UART_BRK_DET_INT_RAW    (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
+#define UART_BRK_DET_INT_RAW_V  0x00000001U
+#define UART_BRK_DET_INT_RAW_S  7
+/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XON_INT_RAW    (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
+#define UART_SW_XON_INT_RAW_V  0x00000001U
+#define UART_SW_XON_INT_RAW_S  9
+/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XOFF_INT_RAW    (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
+#define UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define UART_SW_XOFF_INT_RAW_S  10
+/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
+#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define UART_GLITCH_DET_INT_RAW_S  11
+/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters after all data in Tx-FIFO are sent.
+ */
+#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
+#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define UART_TX_DONE_INT_RAW    (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
+#define UART_TX_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_DONE_INT_RAW_S  14
+/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  This interrupt raw bit turns to high level when detects a clash between transmitter
+ *  and receiver in rs485 mode.
+ */
+#define UART_RS485_CLASH_INT_RAW    (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
+#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
+#define UART_RS485_CLASH_INT_RAW_S  17
+/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define UART_WAKEUP_INT_RAW    (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
+#define UART_WAKEUP_INT_RAW_V  0x00000001U
+#define UART_WAKEUP_INT_RAW_S  19
+
+/** UART_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define UART_INT_ST_REG(i) (DR_REG_UART_BASE(i) + 0x8)
+/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
+#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
+#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ST_S  0
+/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define UART_PARITY_ERR_INT_ST    (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
+#define UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_PARITY_ERR_INT_ST_S  2
+/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define UART_FRM_ERR_INT_ST    (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
+#define UART_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_FRM_ERR_INT_ST_S  3
+/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
+#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define UART_DSR_CHG_INT_ST    (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
+#define UART_DSR_CHG_INT_ST_V  0x00000001U
+#define UART_DSR_CHG_INT_ST_S  5
+/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define UART_CTS_CHG_INT_ST    (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
+#define UART_CTS_CHG_INT_ST_V  0x00000001U
+#define UART_CTS_CHG_INT_ST_S  6
+/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define UART_BRK_DET_INT_ST    (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
+#define UART_BRK_DET_INT_ST_V  0x00000001U
+#define UART_BRK_DET_INT_ST_S  7
+/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
+#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define UART_SW_XON_INT_ST    (BIT(9))
+#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
+#define UART_SW_XON_INT_ST_V  0x00000001U
+#define UART_SW_XON_INT_ST_S  9
+/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define UART_SW_XOFF_INT_ST    (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
+#define UART_SW_XOFF_INT_ST_V  0x00000001U
+#define UART_SW_XOFF_INT_ST_S  10
+/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define UART_GLITCH_DET_INT_ST    (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
+#define UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define UART_GLITCH_DET_INT_ST_S  11
+/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
+#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define UART_TX_DONE_INT_ST    (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
+#define UART_TX_DONE_INT_ST_V  0x00000001U
+#define UART_TX_DONE_INT_ST_S  14
+/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+ *  set to 1.
+ */
+#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+ *  to 1.
+ */
+#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
+#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
+ *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+ */
+#define UART_RS485_CLASH_INT_ST    (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
+#define UART_RS485_CLASH_INT_ST_V  0x00000001U
+#define UART_RS485_CLASH_INT_ST_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define UART_WAKEUP_INT_ST    (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
+#define UART_WAKEUP_INT_ST_V  0x00000001U
+#define UART_WAKEUP_INT_ST_S  19
+
+/** UART_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define UART_INT_ENA_REG(i) (DR_REG_UART_BASE(i) + 0xc)
+/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
+#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
+#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
+#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_PARITY_ERR_INT_ENA_S  2
+/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define UART_FRM_ERR_INT_ENA    (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
+#define UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_FRM_ERR_INT_ENA_S  3
+/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
+#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define UART_DSR_CHG_INT_ENA    (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
+#define UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define UART_DSR_CHG_INT_ENA_S  5
+/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define UART_CTS_CHG_INT_ENA    (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
+#define UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define UART_CTS_CHG_INT_ENA_S  6
+/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define UART_BRK_DET_INT_ENA    (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
+#define UART_BRK_DET_INT_ENA_V  0x00000001U
+#define UART_BRK_DET_INT_ENA_S  7
+/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define UART_SW_XON_INT_ENA    (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
+#define UART_SW_XON_INT_ENA_V  0x00000001U
+#define UART_SW_XON_INT_ENA_S  9
+/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define UART_SW_XOFF_INT_ENA    (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
+#define UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define UART_SW_XOFF_INT_ENA_S  10
+/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
+#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define UART_GLITCH_DET_INT_ENA_S  11
+/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
+#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define UART_TX_DONE_INT_ENA    (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
+#define UART_TX_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_DONE_INT_ENA_S  14
+/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  This is the enable bit for rs485_clash_int_st register.
+ */
+#define UART_RS485_CLASH_INT_ENA    (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
+#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
+#define UART_RS485_CLASH_INT_ENA_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define UART_WAKEUP_INT_ENA    (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
+#define UART_WAKEUP_INT_ENA_V  0x00000001U
+#define UART_WAKEUP_INT_ENA_S  19
+
+/** UART_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define UART_INT_CLR_REG(i) (DR_REG_UART_BASE(i) + 0x10)
+/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
+#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
+#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
+#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_PARITY_ERR_INT_CLR_S  2
+/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define UART_FRM_ERR_INT_CLR    (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
+#define UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_FRM_ERR_INT_CLR_S  3
+/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
+#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define UART_DSR_CHG_INT_CLR    (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
+#define UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define UART_DSR_CHG_INT_CLR_S  5
+/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define UART_CTS_CHG_INT_CLR    (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
+#define UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define UART_CTS_CHG_INT_CLR_S  6
+/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define UART_BRK_DET_INT_CLR    (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
+#define UART_BRK_DET_INT_CLR_V  0x00000001U
+#define UART_BRK_DET_INT_CLR_S  7
+/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define UART_SW_XON_INT_CLR    (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
+#define UART_SW_XON_INT_CLR_V  0x00000001U
+#define UART_SW_XON_INT_CLR_S  9
+/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define UART_SW_XOFF_INT_CLR    (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
+#define UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define UART_SW_XOFF_INT_CLR_S  10
+/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
+#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define UART_GLITCH_DET_INT_CLR_S  11
+/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
+#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define UART_TX_DONE_INT_CLR    (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
+#define UART_TX_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_DONE_INT_CLR_S  14
+/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+ */
+#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+ */
+#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the rs485_clash_int_raw interrupt.
+ */
+#define UART_RS485_CLASH_INT_CLR    (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
+#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
+#define UART_RS485_CLASH_INT_CLR_S  17
+/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define UART_WAKEUP_INT_CLR    (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
+#define UART_WAKEUP_INT_CLR_V  0x00000001U
+#define UART_WAKEUP_INT_CLR_S  19
+
+/** UART_CLKDIV_SYNC_REG register
+ *  Clock divider configuration
+ */
+#define UART_CLKDIV_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x14)
+/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define UART_CLKDIV    0x00000FFFU
+#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
+#define UART_CLKDIV_V  0x00000FFFU
+#define UART_CLKDIV_S  0
+/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define UART_CLKDIV_FRAG    0x0000000FU
+#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
+#define UART_CLKDIV_FRAG_V  0x0000000FU
+#define UART_CLKDIV_FRAG_S  20
+
+/** UART_RX_FILT_REG register
+ *  Rx Filter configuration
+ */
+#define UART_RX_FILT_REG(i) (DR_REG_UART_BASE(i) + 0x18)
+/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value the pulse is ignored.
+ */
+#define UART_GLITCH_FILT    0x000000FFU
+#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
+#define UART_GLITCH_FILT_V  0x000000FFU
+#define UART_GLITCH_FILT_S  0
+/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
+#define UART_GLITCH_FILT_EN    (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
+#define UART_GLITCH_FILT_EN_V  0x00000001U
+#define UART_GLITCH_FILT_EN_S  8
+
+/** UART_STATUS_REG register
+ *  UART status register
+ */
+#define UART_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x1c)
+/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define UART_RXFIFO_CNT    0x000000FFU
+#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
+#define UART_RXFIFO_CNT_V  0x000000FFU
+#define UART_RXFIFO_CNT_S  0
+/** UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
+#define UART_DSRN    (BIT(13))
+#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
+#define UART_DSRN_V  0x00000001U
+#define UART_DSRN_S  13
+/** UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define UART_CTSN    (BIT(14))
+#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
+#define UART_CTSN_V  0x00000001U
+#define UART_CTSN_S  14
+/** UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define UART_RXD    (BIT(15))
+#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
+#define UART_RXD_V  0x00000001U
+#define UART_RXD_S  15
+/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define UART_TXFIFO_CNT    0x000000FFU
+#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
+#define UART_TXFIFO_CNT_V  0x000000FFU
+#define UART_TXFIFO_CNT_S  16
+/** UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define UART_DTRN    (BIT(29))
+#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
+#define UART_DTRN_V  0x00000001U
+#define UART_DTRN_S  29
+/** UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define UART_RTSN    (BIT(30))
+#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
+#define UART_RTSN_V  0x00000001U
+#define UART_RTSN_S  30
+/** UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define UART_TXD    (BIT(31))
+#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
+#define UART_TXD_V  0x00000001U
+#define UART_TXD_S  31
+
+/** UART_CONF0_SYNC_REG register
+ *  a
+ */
+#define UART_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x20)
+/** UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
+#define UART_PARITY    (BIT(0))
+#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
+#define UART_PARITY_V  0x00000001U
+#define UART_PARITY_S  0
+/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define UART_PARITY_EN    (BIT(1))
+#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
+#define UART_PARITY_EN_V  0x00000001U
+#define UART_PARITY_EN_S  1
+/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define UART_BIT_NUM    0x00000003U
+#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
+#define UART_BIT_NUM_V  0x00000003U
+#define UART_BIT_NUM_S  2
+/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define UART_STOP_BIT_NUM    0x00000003U
+#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
+#define UART_STOP_BIT_NUM_V  0x00000003U
+#define UART_STOP_BIT_NUM_S  4
+/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define UART_TXD_BRK    (BIT(6))
+#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
+#define UART_TXD_BRK_V  0x00000001U
+#define UART_TXD_BRK_S  6
+/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable IrDA loopback mode.
+ */
+#define UART_IRDA_DPLX    (BIT(7))
+#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
+#define UART_IRDA_DPLX_V  0x00000001U
+#define UART_IRDA_DPLX_S  7
+/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the start enable bit for IrDA transmitter.
+ */
+#define UART_IRDA_TX_EN    (BIT(8))
+#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
+#define UART_IRDA_TX_EN_V  0x00000001U
+#define UART_IRDA_TX_EN_S  8
+/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
+ *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+ *  transmitter's 11th bit to 0.
+ */
+#define UART_IRDA_WCTL    (BIT(9))
+#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
+#define UART_IRDA_WCTL_V  0x00000001U
+#define UART_IRDA_WCTL_S  9
+/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to invert the level of  IrDA transmitter.
+ */
+#define UART_IRDA_TX_INV    (BIT(10))
+#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
+#define UART_IRDA_TX_INV_V  0x00000001U
+#define UART_IRDA_TX_INV_S  10
+/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to invert the level of IrDA receiver.
+ */
+#define UART_IRDA_RX_INV    (BIT(11))
+#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
+#define UART_IRDA_RX_INV_V  0x00000001U
+#define UART_IRDA_RX_INV_S  11
+/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define UART_LOOPBACK    (BIT(12))
+#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
+#define UART_LOOPBACK_V  0x00000001U
+#define UART_LOOPBACK_S  12
+/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define UART_TX_FLOW_EN    (BIT(13))
+#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
+#define UART_TX_FLOW_EN_V  0x00000001U
+#define UART_TX_FLOW_EN_S  13
+/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
+ *  Set this bit to enable IrDA protocol.
+ */
+#define UART_IRDA_EN    (BIT(14))
+#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
+#define UART_IRDA_EN_V  0x00000001U
+#define UART_IRDA_EN_S  14
+/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define UART_RXD_INV    (BIT(15))
+#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
+#define UART_RXD_INV_V  0x00000001U
+#define UART_RXD_INV_S  15
+/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define UART_TXD_INV    (BIT(16))
+#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
+#define UART_TXD_INV_V  0x00000001U
+#define UART_TXD_INV_S  16
+/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
+#define UART_DIS_RX_DAT_OVF    (BIT(17))
+#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
+#define UART_DIS_RX_DAT_OVF_V  0x00000001U
+#define UART_DIS_RX_DAT_OVF_S  17
+/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define UART_ERR_WR_MASK    (BIT(18))
+#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
+#define UART_ERR_WR_MASK_V  0x00000001U
+#define UART_ERR_WR_MASK_S  18
+/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for detecting baudrate.
+ */
+#define UART_AUTOBAUD_EN    (BIT(19))
+#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
+#define UART_AUTOBAUD_EN_V  0x00000001U
+#define UART_AUTOBAUD_EN_S  19
+/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  UART memory clock gate enable signal.
+ */
+#define UART_MEM_CLK_EN    (BIT(20))
+#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
+#define UART_MEM_CLK_EN_V  0x00000001U
+#define UART_MEM_CLK_EN_S  20
+/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_RTS    (BIT(21))
+#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
+#define UART_SW_RTS_V  0x00000001U
+#define UART_SW_RTS_S  21
+/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define UART_RXFIFO_RST    (BIT(22))
+#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
+#define UART_RXFIFO_RST_V  0x00000001U
+#define UART_RXFIFO_RST_S  22
+/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define UART_TXFIFO_RST    (BIT(23))
+#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
+#define UART_TXFIFO_RST_V  0x00000001U
+#define UART_TXFIFO_RST_S  23
+
+/** UART_CONF1_REG register
+ *  Configuration register 1
+ */
+#define UART_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x24)
+/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define UART_RXFIFO_FULL_THRHD    0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
+#define UART_RXFIFO_FULL_THRHD_V  0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_S  0
+/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define UART_TXFIFO_EMPTY_THRHD    0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
+#define UART_TXFIFO_EMPTY_THRHD_V  0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_S  8
+/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define UART_CTS_INV    (BIT(16))
+#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
+#define UART_CTS_INV_V  0x00000001U
+#define UART_CTS_INV_S  16
+/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define UART_DSR_INV    (BIT(17))
+#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
+#define UART_DSR_INV_V  0x00000001U
+#define UART_DSR_INV_S  17
+/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define UART_RTS_INV    (BIT(18))
+#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
+#define UART_RTS_INV_V  0x00000001U
+#define UART_RTS_INV_S  18
+/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define UART_DTR_INV    (BIT(19))
+#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
+#define UART_DTR_INV_V  0x00000001U
+#define UART_DTR_INV_S  19
+/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_DTR    (BIT(20))
+#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
+#define UART_SW_DTR_V  0x00000001U
+#define UART_SW_DTR_S  20
+/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define UART_CLK_EN    (BIT(21))
+#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
+#define UART_CLK_EN_V  0x00000001U
+#define UART_CLK_EN_S  21
+
+/** UART_HWFC_CONF_SYNC_REG register
+ *  Hardware flow-control configuration
+ */
+#define UART_HWFC_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x2c)
+/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define UART_RX_FLOW_THRHD    0x000000FFU
+#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
+#define UART_RX_FLOW_THRHD_V  0x000000FFU
+#define UART_RX_FLOW_THRHD_S  0
+/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define UART_RX_FLOW_EN    (BIT(8))
+#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
+#define UART_RX_FLOW_EN_V  0x00000001U
+#define UART_RX_FLOW_EN_S  8
+
+/** UART_SLEEP_CONF0_REG register
+ *  UART sleep configure register 0
+ */
+#define UART_SLEEP_CONF0_REG(i) (DR_REG_UART_BASE(i) + 0x30)
+/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified wake up char1 to wake up
+ */
+#define UART_WK_CHAR1    0x000000FFU
+#define UART_WK_CHAR1_M  (UART_WK_CHAR1_V << UART_WK_CHAR1_S)
+#define UART_WK_CHAR1_V  0x000000FFU
+#define UART_WK_CHAR1_S  0
+/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
+ *  This register restores the specified wake up char2 to wake up
+ */
+#define UART_WK_CHAR2    0x000000FFU
+#define UART_WK_CHAR2_M  (UART_WK_CHAR2_V << UART_WK_CHAR2_S)
+#define UART_WK_CHAR2_V  0x000000FFU
+#define UART_WK_CHAR2_S  8
+/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
+ *  This register restores the specified wake up char3 to wake up
+ */
+#define UART_WK_CHAR3    0x000000FFU
+#define UART_WK_CHAR3_M  (UART_WK_CHAR3_V << UART_WK_CHAR3_S)
+#define UART_WK_CHAR3_V  0x000000FFU
+#define UART_WK_CHAR3_S  16
+/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
+ *  This register restores the specified wake up char4 to wake up
+ */
+#define UART_WK_CHAR4    0x000000FFU
+#define UART_WK_CHAR4_M  (UART_WK_CHAR4_V << UART_WK_CHAR4_S)
+#define UART_WK_CHAR4_V  0x000000FFU
+#define UART_WK_CHAR4_S  24
+
+/** UART_SLEEP_CONF1_REG register
+ *  UART sleep configure register 1
+ */
+#define UART_SLEEP_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x34)
+/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified char0 to wake up
+ */
+#define UART_WK_CHAR0    0x000000FFU
+#define UART_WK_CHAR0_M  (UART_WK_CHAR0_V << UART_WK_CHAR0_S)
+#define UART_WK_CHAR0_V  0x000000FFU
+#define UART_WK_CHAR0_S  0
+
+/** UART_SLEEP_CONF2_REG register
+ *  UART sleep configure register 2
+ */
+#define UART_SLEEP_CONF2_REG(i) (DR_REG_UART_BASE(i) + 0x38)
+/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define UART_ACTIVE_THRESHOLD    0x000003FFU
+#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
+#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
+#define UART_ACTIVE_THRESHOLD_S  0
+/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1;
+ *  In wake up mode 1 this field is used to set the received data number threshold to
+ *  wake up chip.
+ */
+#define UART_RX_WAKE_UP_THRHD    0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_M  (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S)
+#define UART_RX_WAKE_UP_THRHD_V  0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_S  10
+/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
+ *  This register is used to select number of wake up char.
+ */
+#define UART_WK_CHAR_NUM    0x00000007U
+#define UART_WK_CHAR_NUM_M  (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S)
+#define UART_WK_CHAR_NUM_V  0x00000007U
+#define UART_WK_CHAR_NUM_S  18
+/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
+ *  This register is used to mask  wake up char.
+ */
+#define UART_WK_CHAR_MASK    0x0000001FU
+#define UART_WK_CHAR_MASK_M  (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
+#define UART_WK_CHAR_MASK_V  0x0000001FU
+#define UART_WK_CHAR_MASK_S  21
+/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+ *  received data number larger than
+ */
+#define UART_WK_MODE_SEL    0x00000003U
+#define UART_WK_MODE_SEL_M  (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
+#define UART_WK_MODE_SEL_V  0x00000003U
+#define UART_WK_MODE_SEL_S  26
+
+/** UART_SWFC_CONF0_SYNC_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x3c)
+/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define UART_XON_CHAR    0x000000FFU
+#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
+#define UART_XON_CHAR_V  0x000000FFU
+#define UART_XON_CHAR_S  0
+/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define UART_XOFF_CHAR    0x000000FFU
+#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
+#define UART_XOFF_CHAR_V  0x000000FFU
+#define UART_XOFF_CHAR_S  8
+/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
+ *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+ *  this status, UART Tx can not transmit XOFF even the received data number is larger
+ *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+ *  UART Tx is disabled.
+ */
+#define UART_XON_XOFF_STILL_SEND    (BIT(16))
+#define UART_XON_XOFF_STILL_SEND_M  (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
+#define UART_XON_XOFF_STILL_SEND_V  0x00000001U
+#define UART_XON_XOFF_STILL_SEND_S  16
+/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
+#define UART_SW_FLOW_CON_EN    (BIT(17))
+#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
+#define UART_SW_FLOW_CON_EN_V  0x00000001U
+#define UART_SW_FLOW_CON_EN_S  17
+/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define UART_XONOFF_DEL    (BIT(18))
+#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
+#define UART_XONOFF_DEL_V  0x00000001U
+#define UART_XONOFF_DEL_S  18
+/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define UART_FORCE_XON    (BIT(19))
+#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
+#define UART_FORCE_XON_V  0x00000001U
+#define UART_FORCE_XON_S  19
+/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define UART_FORCE_XOFF    (BIT(20))
+#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
+#define UART_FORCE_XOFF_V  0x00000001U
+#define UART_FORCE_XOFF_S  20
+/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XON    (BIT(21))
+#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
+#define UART_SEND_XON_V  0x00000001U
+#define UART_SEND_XON_S  21
+/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XOFF    (BIT(22))
+#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
+#define UART_SEND_XOFF_V  0x00000001U
+#define UART_SEND_XOFF_S  22
+
+/** UART_SWFC_CONF1_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x40)
+/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+ */
+#define UART_XON_THRESHOLD    0x000000FFU
+#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
+#define UART_XON_THRESHOLD_V  0x000000FFU
+#define UART_XON_THRESHOLD_S  0
+/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+ */
+#define UART_XOFF_THRESHOLD    0x000000FFU
+#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
+#define UART_XOFF_THRESHOLD_V  0x000000FFU
+#define UART_XOFF_THRESHOLD_S  8
+
+/** UART_TXBRK_CONF_SYNC_REG register
+ *  Tx Break character configuration
+ */
+#define UART_TXBRK_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x44)
+/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define UART_TX_BRK_NUM    0x000000FFU
+#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
+#define UART_TX_BRK_NUM_V  0x000000FFU
+#define UART_TX_BRK_NUM_S  0
+
+/** UART_IDLE_CONF_SYNC_REG register
+ *  Frame-end idle configuration
+ */
+#define UART_IDLE_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x48)
+/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define UART_RX_IDLE_THRHD    0x000003FFU
+#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
+#define UART_RX_IDLE_THRHD_V  0x000003FFU
+#define UART_RX_IDLE_THRHD_S  0
+/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define UART_TX_IDLE_NUM    0x000003FFU
+#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
+#define UART_TX_IDLE_NUM_V  0x000003FFU
+#define UART_TX_IDLE_NUM_S  10
+
+/** UART_RS485_CONF_SYNC_REG register
+ *  RS485 mode configuration
+ */
+#define UART_RS485_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x4c)
+/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to choose the rs485 mode.
+ */
+#define UART_RS485_EN    (BIT(0))
+#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
+#define UART_RS485_EN_V  0x00000001U
+#define UART_RS485_EN_S  0
+/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL0_EN    (BIT(1))
+#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
+#define UART_DL0_EN_V  0x00000001U
+#define UART_DL0_EN_S  1
+/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL1_EN    (BIT(2))
+#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
+#define UART_DL1_EN_V  0x00000001U
+#define UART_DL1_EN_S  2
+/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable receiver could receive data when the transmitter is
+ *  transmitting data in rs485 mode.
+ */
+#define UART_RS485TX_RX_EN    (BIT(3))
+#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
+#define UART_RS485TX_RX_EN_V  0x00000001U
+#define UART_RS485TX_RX_EN_S  3
+/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+ */
+#define UART_RS485RXBY_TX_EN    (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
+#define UART_RS485RXBY_TX_EN_V  0x00000001U
+#define UART_RS485RXBY_TX_EN_S  4
+/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
+ *  This register is used to delay the receiver's internal data signal.
+ */
+#define UART_RS485_RX_DLY_NUM    (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
+#define UART_RS485_RX_DLY_NUM_V  0x00000001U
+#define UART_RS485_RX_DLY_NUM_S  5
+/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
+ *  This register is used to delay the transmitter's internal data signal.
+ */
+#define UART_RS485_TX_DLY_NUM    0x0000000FU
+#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
+#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
+#define UART_RS485_TX_DLY_NUM_S  6
+
+/** UART_AT_CMD_PRECNT_SYNC_REG register
+ *  Pre-sequence timing configuration
+ */
+#define UART_AT_CMD_PRECNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x50)
+/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define UART_PRE_IDLE_NUM    0x0000FFFFU
+#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
+#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
+#define UART_PRE_IDLE_NUM_S  0
+
+/** UART_AT_CMD_POSTCNT_SYNC_REG register
+ *  Post-sequence timing configuration
+ */
+#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x54)
+/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define UART_POST_IDLE_NUM    0x0000FFFFU
+#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
+#define UART_POST_IDLE_NUM_V  0x0000FFFFU
+#define UART_POST_IDLE_NUM_S  0
+
+/** UART_AT_CMD_GAPTOUT_SYNC_REG register
+ *  Timeout configuration
+ */
+#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x58)
+/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define UART_RX_GAP_TOUT    0x0000FFFFU
+#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
+#define UART_RX_GAP_TOUT_V  0x0000FFFFU
+#define UART_RX_GAP_TOUT_S  0
+
+/** UART_AT_CMD_CHAR_SYNC_REG register
+ *  AT escape sequence detection configuration
+ */
+#define UART_AT_CMD_CHAR_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x5c)
+/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define UART_AT_CMD_CHAR    0x000000FFU
+#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
+#define UART_AT_CMD_CHAR_V  0x000000FFU
+#define UART_AT_CMD_CHAR_S  0
+/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define UART_CHAR_NUM    0x000000FFU
+#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
+#define UART_CHAR_NUM_V  0x000000FFU
+#define UART_CHAR_NUM_S  8
+
+/** UART_MEM_CONF_REG register
+ *  UART memory power configuration
+ */
+#define UART_MEM_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x60)
+/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
+#define UART_MEM_FORCE_PD    (BIT(25))
+#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
+#define UART_MEM_FORCE_PD_V  0x00000001U
+#define UART_MEM_FORCE_PD_S  25
+/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define UART_MEM_FORCE_PU    (BIT(26))
+#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
+#define UART_MEM_FORCE_PU_V  0x00000001U
+#define UART_MEM_FORCE_PU_S  26
+
+/** UART_TOUT_CONF_SYNC_REG register
+ *  UART threshold and allocation configuration
+ */
+#define UART_TOUT_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x64)
+/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for uart receiver's timeout function.
+ */
+#define UART_RX_TOUT_EN    (BIT(0))
+#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
+#define UART_RX_TOUT_EN_V  0x00000001U
+#define UART_RX_TOUT_EN_S  0
+/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define UART_RX_TOUT_FLOW_DIS    (BIT(1))
+#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
+#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define UART_RX_TOUT_FLOW_DIS_S  1
+/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define UART_RX_TOUT_THRHD    0x000003FFU
+#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
+#define UART_RX_TOUT_THRHD_V  0x000003FFU
+#define UART_RX_TOUT_THRHD_S  2
+
+/** UART_MEM_TX_STATUS_REG register
+ *  Tx-SRAM write and read offset address.
+ */
+#define UART_MEM_TX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x68)
+/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
+ *  This register stores the offset write address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_WADDR    0x000000FFU
+#define UART_TX_SRAM_WADDR_M  (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S)
+#define UART_TX_SRAM_WADDR_V  0x000000FFU
+#define UART_TX_SRAM_WADDR_S  0
+/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0;
+ *  This register stores the offset read address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_RADDR    0x000000FFU
+#define UART_TX_SRAM_RADDR_M  (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S)
+#define UART_TX_SRAM_RADDR_V  0x000000FFU
+#define UART_TX_SRAM_RADDR_S  9
+
+/** UART_MEM_RX_STATUS_REG register
+ *  Rx-SRAM write and read offset address.
+ */
+#define UART_MEM_RX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x6c)
+/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
+ *  This register stores the offset read address in RX-SRAM.
+ */
+#define UART_RX_SRAM_RADDR    0x000000FFU
+#define UART_RX_SRAM_RADDR_M  (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S)
+#define UART_RX_SRAM_RADDR_V  0x000000FFU
+#define UART_RX_SRAM_RADDR_S  0
+/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128;
+ *  This register stores the offset write address in Rx-SRAM.
+ */
+#define UART_RX_SRAM_WADDR    0x000000FFU
+#define UART_RX_SRAM_WADDR_M  (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S)
+#define UART_RX_SRAM_WADDR_V  0x000000FFU
+#define UART_RX_SRAM_WADDR_S  9
+
+/** UART_FSM_STATUS_REG register
+ *  UART transmit and receive status.
+ */
+#define UART_FSM_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x70)
+/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define UART_ST_URX_OUT    0x0000000FU
+#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
+#define UART_ST_URX_OUT_V  0x0000000FU
+#define UART_ST_URX_OUT_S  0
+/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define UART_ST_UTX_OUT    0x0000000FU
+#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
+#define UART_ST_UTX_OUT_V  0x0000000FU
+#define UART_ST_UTX_OUT_S  4
+
+/** UART_POSPULSE_REG register
+ *  Autobaud high pulse register
+ */
+#define UART_POSPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x74)
+/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two positive edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_POSEDGE_MIN_CNT    0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
+#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_S  0
+
+/** UART_NEGPULSE_REG register
+ *  Autobaud low pulse register
+ */
+#define UART_NEGPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x78)
+/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two negative edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
+#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+/** UART_LOWPULSE_REG register
+ *  Autobaud minimum low pulse duration register
+ */
+#define UART_LOWPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x7c)
+/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the value of the minimum duration time of the low level pulse.
+ *  It is used in baud rate-detect process.
+ */
+#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
+#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+/** UART_HIGHPULSE_REG register
+ *  Autobaud minimum high pulse duration register
+ */
+#define UART_HIGHPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x80)
+/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores  the value of the maximum duration time for the high level
+ *  pulse. It is used in baud rate-detect process.
+ */
+#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
+#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+/** UART_RXD_CNT_REG register
+ *  Autobaud edge change count register
+ */
+#define UART_RXD_CNT_REG(i) (DR_REG_UART_BASE(i) + 0x84)
+/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
+ *  This register stores the count of rxd edge change. It is used in baud rate-detect
+ *  process.
+ */
+#define UART_RXD_EDGE_CNT    0x000003FFU
+#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
+#define UART_RXD_EDGE_CNT_V  0x000003FFU
+#define UART_RXD_EDGE_CNT_S  0
+
+/** UART_CLK_CONF_REG register
+ *  UART core clock configuration
+ */
+#define UART_CLK_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x88)
+/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable UART Tx clock.
+ */
+#define UART_TX_SCLK_EN    (BIT(24))
+#define UART_TX_SCLK_EN_M  (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
+#define UART_TX_SCLK_EN_V  0x00000001U
+#define UART_TX_SCLK_EN_S  24
+/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Set this bit to enable UART Rx clock.
+ */
+#define UART_RX_SCLK_EN    (BIT(25))
+#define UART_RX_SCLK_EN_M  (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
+#define UART_RX_SCLK_EN_V  0x00000001U
+#define UART_RX_SCLK_EN_S  25
+/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Tx.
+ */
+#define UART_TX_RST_CORE    (BIT(26))
+#define UART_TX_RST_CORE_M  (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
+#define UART_TX_RST_CORE_V  0x00000001U
+#define UART_TX_RST_CORE_S  26
+/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Rx.
+ */
+#define UART_RX_RST_CORE    (BIT(27))
+#define UART_RX_RST_CORE_M  (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
+#define UART_RX_RST_CORE_V  0x00000001U
+#define UART_RX_RST_CORE_S  27
+
+/** UART_DATE_REG register
+ *  UART Version register
+ */
+#define UART_DATE_REG(i) (DR_REG_UART_BASE(i) + 0x8c)
+/** UART_DATE : R/W; bitpos: [31:0]; default: 36720720;
+ *  This is the version register.
+ */
+#define UART_DATE    0xFFFFFFFFU
+#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
+#define UART_DATE_V  0xFFFFFFFFU
+#define UART_DATE_S  0
+
+/** UART_AFIFO_STATUS_REG register
+ *  UART AFIFO Status
+ */
+#define UART_AFIFO_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x90)
+/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
+ *  Full signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_FULL    (BIT(0))
+#define UART_TX_AFIFO_FULL_M  (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
+#define UART_TX_AFIFO_FULL_V  0x00000001U
+#define UART_TX_AFIFO_FULL_S  0
+/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
+ *  Empty signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_EMPTY    (BIT(1))
+#define UART_TX_AFIFO_EMPTY_M  (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
+#define UART_TX_AFIFO_EMPTY_V  0x00000001U
+#define UART_TX_AFIFO_EMPTY_S  1
+/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
+ *  Full signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_FULL    (BIT(2))
+#define UART_RX_AFIFO_FULL_M  (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
+#define UART_RX_AFIFO_FULL_V  0x00000001U
+#define UART_RX_AFIFO_FULL_S  2
+/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
+ *  Empty signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_EMPTY    (BIT(3))
+#define UART_RX_AFIFO_EMPTY_M  (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
+#define UART_RX_AFIFO_EMPTY_V  0x00000001U
+#define UART_RX_AFIFO_EMPTY_S  3
+
+/** UART_REG_UPDATE_REG register
+ *  UART Registers Configuration Update register
+ */
+#define UART_REG_UPDATE_REG(i) (DR_REG_UART_BASE(i) + 0x98)
+/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define UART_REG_UPDATE    (BIT(0))
+#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
+#define UART_REG_UPDATE_V  0x00000001U
+#define UART_REG_UPDATE_S  0
+
+/** UART_ID_REG register
+ *  UART ID register
+ */
+#define UART_ID_REG(i) (DR_REG_UART_BASE(i) + 0x9c)
+/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define UART_ID    0xFFFFFFFFU
+#define UART_ID_M  (UART_ID_V << UART_ID_S)
+#define UART_ID_V  0xFFFFFFFFU
+#define UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_struct.h
new file mode 100644
index 0000000000..c49c9b58ba
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_struct.h
@@ -0,0 +1,1274 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         */
+        uint32_t rxfifo_rd_byte:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full_int_raw:1;
+        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty_int_raw:1;
+        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err_int_raw:1;
+        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg_int_raw:1;
+        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg_int_raw:1;
+        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det_int_raw:1;
+        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout_int_raw:1;
+        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon_int_raw:1;
+        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff_int_raw:1;
+        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det_int_raw:1;
+        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done_int_raw:1;
+        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done_int_raw:1;
+        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_parity_err_int_raw:1;
+        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_frm_err_int_raw:1;
+        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  This interrupt raw bit turns to high level when detects a clash between transmitter
+         *  and receiver in rs485 mode.
+         */
+        uint32_t rs485_clash_int_raw:1;
+        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det_int_raw:1;
+        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full_int_st:1;
+        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty_int_st:1;
+        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err_int_st:1;
+        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg_int_st:1;
+        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg_int_st:1;
+        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det_int_st:1;
+        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout_int_st:1;
+        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon_int_st:1;
+        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff_int_st:1;
+        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det_int_st:1;
+        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done_int_st:1;
+        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done_int_st:1;
+        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
+         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+         *  set to 1.
+         */
+        uint32_t rs485_parity_err_int_st:1;
+        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
+         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+         *  to 1.
+         */
+        uint32_t rs485_frm_err_int_st:1;
+        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
+         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+         */
+        uint32_t rs485_clash_int_st:1;
+        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det_int_st:1;
+        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full_int_ena:1;
+        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty_int_ena:1;
+        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err_int_ena:1;
+        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg_int_ena:1;
+        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg_int_ena:1;
+        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det_int_ena:1;
+        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout_int_ena:1;
+        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon_int_ena:1;
+        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff_int_ena:1;
+        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det_int_ena:1;
+        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done_int_ena:1;
+        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_parity_err_int_ena:1;
+        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_frm_err_int_ena:1;
+        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
+         *  This is the enable bit for rs485_clash_int_st register.
+         */
+        uint32_t rs485_clash_int_ena:1;
+        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det_int_ena:1;
+        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full_int_clr:1;
+        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty_int_clr:1;
+        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err_int_clr:1;
+        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg_int_clr:1;
+        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg_int_clr:1;
+        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det_int_clr:1;
+        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout_int_clr:1;
+        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon_int_clr:1;
+        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff_int_clr:1;
+        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det_int_clr:1;
+        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done_int_clr:1;
+        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+         */
+        uint32_t rs485_parity_err_int_clr:1;
+        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+         */
+        uint32_t rs485_frm_err_int_clr:1;
+        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the rs485_clash_int_raw interrupt.
+         */
+        uint32_t rs485_clash_int_clr:1;
+        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det_int_clr:1;
+        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  a
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        /** irda_dplx : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable IrDA loopback mode.
+         */
+        uint32_t irda_dplx:1;
+        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
+         *  This is the start enable bit for IrDA transmitter.
+         */
+        uint32_t irda_tx_en:1;
+        /** irda_wctl : R/W; bitpos: [9]; default: 0;
+         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+         *  transmitter's 11th bit to 0.
+         */
+        uint32_t irda_wctl:1;
+        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to invert the level of  IrDA transmitter.
+         */
+        uint32_t irda_tx_inv:1;
+        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to invert the level of IrDA receiver.
+         */
+        uint32_t irda_rx_inv:1;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        /** irda_en : R/W; bitpos: [14]; default: 0;
+         *  Set this bit to enable IrDA protocol.
+         */
+        uint32_t irda_en:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        /** autobaud_en : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for detecting baudrate.
+         */
+        uint32_t autobaud_en:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:8;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:8;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow-control configuration
+ */
+typedef union {
+    struct {
+        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:8;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configure register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified wake up char1 to wake up
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  This register restores the specified wake up char2 to wake up
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  This register restores the specified wake up char3 to wake up
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  This register restores the specified wake up char4 to wake up
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configure register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified char0 to wake up
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configure register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
+         *  In wake up mode 1 this field is used to set the received data number threshold to
+         *  wake up chip.
+         */
+        uint32_t rx_wake_up_thrhd:8;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  This register is used to select number of wake up char.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  This register is used to mask  wake up char.
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+         *  received data number larger than
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_char : R/W; bitpos: [7:0]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_char:8;
+        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_char:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+         *  this status, UART Tx can not transmit XOFF even the received data number is larger
+         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+         *  UART Tx is disabled.
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+         */
+        uint32_t xon_threshold:8;
+        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        /** rs485_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to choose the rs485 mode.
+         */
+        uint32_t rs485_en:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable receiver could receive data when the transmitter is
+         *  transmitting data in rs485 mode.
+         */
+        uint32_t rs485tx_rx_en:1;
+        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+         */
+        uint32_t rs485rxby_tx_en:1;
+        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
+         *  This register is used to delay the receiver's internal data signal.
+         */
+        uint32_t rs485_rx_dly_num:1;
+        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
+         *  This register is used to delay the transmitter's internal data signal.
+         */
+        uint32_t rs485_tx_dly_num:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rs485_conf_sync_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable UART Tx clock.
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Set this bit to enable UART Rx clock.
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Tx.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Rx.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:8;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:8;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
+         *  This register stores the offset write address in Tx-SRAM.
+         */
+        uint32_t tx_sram_waddr:8;
+        uint32_t reserved_8:1;
+        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
+         *  This register stores the offset read address in Tx-SRAM.
+         */
+        uint32_t tx_sram_raddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
+         *  This register stores the offset read address in RX-SRAM.
+         */
+        uint32_t rx_sram_raddr:8;
+        uint32_t reserved_8:1;
+        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
+         *  This register stores the offset write address in Rx-SRAM.
+         */
+        uint32_t rx_sram_waddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART AFIFO Status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Full signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Empty signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Full signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Empty signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t at_cmd_char:8;
+        /** char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Autobaud Register */
+/** Type of pospulse register
+ *  Autobaud high pulse register
+ */
+typedef union {
+    struct {
+        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two positive edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t posedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_pospulse_reg_t;
+
+/** Type of negpulse register
+ *  Autobaud low pulse register
+ */
+typedef union {
+    struct {
+        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two negative edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t negedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_negpulse_reg_t;
+
+/** Type of lowpulse register
+ *  Autobaud minimum low pulse duration register
+ */
+typedef union {
+    struct {
+        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the value of the minimum duration time of the low level pulse.
+         *  It is used in baud rate-detect process.
+         */
+        uint32_t lowpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_lowpulse_reg_t;
+
+/** Type of highpulse register
+ *  Autobaud minimum high pulse duration register
+ */
+typedef union {
+    struct {
+        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores  the value of the maximum duration time for the high level
+         *  pulse. It is used in baud rate-detect process.
+         */
+        uint32_t highpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_highpulse_reg_t;
+
+/** Type of rxd_cnt register
+ *  Autobaud edge change count register
+ */
+typedef union {
+    struct {
+        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
+         *  This register stores the count of rxd edge change. It is used in baud rate-detect
+         *  process.
+         */
+        uint32_t rxd_edge_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rxd_cnt_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36720720;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART Registers Configuration Update register
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} uart_id_reg_t;
+
+
+typedef struct {
+    volatile uart_fifo_reg_t fifo;
+    volatile uart_int_raw_reg_t int_raw;
+    volatile uart_int_st_reg_t int_st;
+    volatile uart_int_ena_reg_t int_ena;
+    volatile uart_int_clr_reg_t int_clr;
+    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile uart_rx_filt_reg_t rx_filt;
+    volatile uart_status_reg_t status;
+    volatile uart_conf0_sync_reg_t conf0_sync;
+    volatile uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile uart_sleep_conf0_reg_t sleep_conf0;
+    volatile uart_sleep_conf1_reg_t sleep_conf1;
+    volatile uart_sleep_conf2_reg_t sleep_conf2;
+    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile uart_swfc_conf1_reg_t swfc_conf1;
+    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile uart_mem_conf_reg_t mem_conf;
+    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile uart_mem_tx_status_reg_t mem_tx_status;
+    volatile uart_mem_rx_status_reg_t mem_rx_status;
+    volatile uart_fsm_status_reg_t fsm_status;
+    volatile uart_pospulse_reg_t pospulse;
+    volatile uart_negpulse_reg_t negpulse;
+    volatile uart_lowpulse_reg_t lowpulse;
+    volatile uart_highpulse_reg_t highpulse;
+    volatile uart_rxd_cnt_reg_t rxd_cnt;
+    volatile uart_clk_conf_reg_t clk_conf;
+    volatile uart_date_reg_t date;
+    volatile uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile uart_reg_update_reg_t reg_update;
+    volatile uart_id_reg_t id;
+} uart_dev_t;
+
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+extern uart_dev_t UART2;
+extern uart_dev_t UART3;
+extern uart_dev_t UART4;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h
new file mode 100644
index 0000000000..66c4081a96
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h
@@ -0,0 +1,1581 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13425
+
+/** UART_FIFO_REG register
+ *  FIFO data register
+ */
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
+/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART $n accesses FIFO via this register.
+ */
+#define UART_RXFIFO_RD_BYTE    0x000000FFU
+#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
+#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
+#define UART_RXFIFO_RD_BYTE_S  0
+
+/** UART_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
+/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
+#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
+#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
+#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_PARITY_ERR_INT_RAW_S  2
+/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define UART_FRM_ERR_INT_RAW    (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
+#define UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_FRM_ERR_INT_RAW_S  3
+/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
+#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define UART_DSR_CHG_INT_RAW    (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
+#define UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define UART_DSR_CHG_INT_RAW_S  5
+/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define UART_CTS_CHG_INT_RAW    (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
+#define UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define UART_CTS_CHG_INT_RAW_S  6
+/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define UART_BRK_DET_INT_RAW    (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
+#define UART_BRK_DET_INT_RAW_V  0x00000001U
+#define UART_BRK_DET_INT_RAW_S  7
+/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XON_INT_RAW    (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
+#define UART_SW_XON_INT_RAW_V  0x00000001U
+#define UART_SW_XON_INT_RAW_S  9
+/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XOFF_INT_RAW    (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
+#define UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define UART_SW_XOFF_INT_RAW_S  10
+/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
+#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define UART_GLITCH_DET_INT_RAW_S  11
+/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters after all data in Tx-FIFO are sent.
+ */
+#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
+#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define UART_TX_DONE_INT_RAW    (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
+#define UART_TX_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_DONE_INT_RAW_S  14
+/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  This interrupt raw bit turns to high level when detects a clash between transmitter
+ *  and receiver in rs485 mode.
+ */
+#define UART_RS485_CLASH_INT_RAW    (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
+#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
+#define UART_RS485_CLASH_INT_RAW_S  17
+/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define UART_WAKEUP_INT_RAW    (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
+#define UART_WAKEUP_INT_RAW_V  0x00000001U
+#define UART_WAKEUP_INT_RAW_S  19
+
+/** UART_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
+/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
+#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
+#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ST_S  0
+/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define UART_PARITY_ERR_INT_ST    (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
+#define UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_PARITY_ERR_INT_ST_S  2
+/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define UART_FRM_ERR_INT_ST    (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
+#define UART_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_FRM_ERR_INT_ST_S  3
+/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
+#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define UART_DSR_CHG_INT_ST    (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
+#define UART_DSR_CHG_INT_ST_V  0x00000001U
+#define UART_DSR_CHG_INT_ST_S  5
+/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define UART_CTS_CHG_INT_ST    (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
+#define UART_CTS_CHG_INT_ST_V  0x00000001U
+#define UART_CTS_CHG_INT_ST_S  6
+/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define UART_BRK_DET_INT_ST    (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
+#define UART_BRK_DET_INT_ST_V  0x00000001U
+#define UART_BRK_DET_INT_ST_S  7
+/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
+#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define UART_SW_XON_INT_ST    (BIT(9))
+#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
+#define UART_SW_XON_INT_ST_V  0x00000001U
+#define UART_SW_XON_INT_ST_S  9
+/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define UART_SW_XOFF_INT_ST    (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
+#define UART_SW_XOFF_INT_ST_V  0x00000001U
+#define UART_SW_XOFF_INT_ST_S  10
+/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define UART_GLITCH_DET_INT_ST    (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
+#define UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define UART_GLITCH_DET_INT_ST_S  11
+/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
+#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define UART_TX_DONE_INT_ST    (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
+#define UART_TX_DONE_INT_ST_V  0x00000001U
+#define UART_TX_DONE_INT_ST_S  14
+/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+ *  set to 1.
+ */
+#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+ *  to 1.
+ */
+#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
+#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
+ *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+ */
+#define UART_RS485_CLASH_INT_ST    (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
+#define UART_RS485_CLASH_INT_ST_V  0x00000001U
+#define UART_RS485_CLASH_INT_ST_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define UART_WAKEUP_INT_ST    (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
+#define UART_WAKEUP_INT_ST_V  0x00000001U
+#define UART_WAKEUP_INT_ST_S  19
+
+/** UART_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
+/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
+#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
+#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
+#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_PARITY_ERR_INT_ENA_S  2
+/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define UART_FRM_ERR_INT_ENA    (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
+#define UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_FRM_ERR_INT_ENA_S  3
+/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
+#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define UART_DSR_CHG_INT_ENA    (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
+#define UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define UART_DSR_CHG_INT_ENA_S  5
+/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define UART_CTS_CHG_INT_ENA    (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
+#define UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define UART_CTS_CHG_INT_ENA_S  6
+/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define UART_BRK_DET_INT_ENA    (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
+#define UART_BRK_DET_INT_ENA_V  0x00000001U
+#define UART_BRK_DET_INT_ENA_S  7
+/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define UART_SW_XON_INT_ENA    (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
+#define UART_SW_XON_INT_ENA_V  0x00000001U
+#define UART_SW_XON_INT_ENA_S  9
+/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define UART_SW_XOFF_INT_ENA    (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
+#define UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define UART_SW_XOFF_INT_ENA_S  10
+/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
+#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define UART_GLITCH_DET_INT_ENA_S  11
+/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
+#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define UART_TX_DONE_INT_ENA    (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
+#define UART_TX_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_DONE_INT_ENA_S  14
+/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  This is the enable bit for rs485_clash_int_st register.
+ */
+#define UART_RS485_CLASH_INT_ENA    (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
+#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
+#define UART_RS485_CLASH_INT_ENA_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define UART_WAKEUP_INT_ENA    (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
+#define UART_WAKEUP_INT_ENA_V  0x00000001U
+#define UART_WAKEUP_INT_ENA_S  19
+
+/** UART_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
+/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
+#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
+#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
+#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_PARITY_ERR_INT_CLR_S  2
+/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define UART_FRM_ERR_INT_CLR    (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
+#define UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_FRM_ERR_INT_CLR_S  3
+/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
+#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define UART_DSR_CHG_INT_CLR    (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
+#define UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define UART_DSR_CHG_INT_CLR_S  5
+/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define UART_CTS_CHG_INT_CLR    (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
+#define UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define UART_CTS_CHG_INT_CLR_S  6
+/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define UART_BRK_DET_INT_CLR    (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
+#define UART_BRK_DET_INT_CLR_V  0x00000001U
+#define UART_BRK_DET_INT_CLR_S  7
+/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define UART_SW_XON_INT_CLR    (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
+#define UART_SW_XON_INT_CLR_V  0x00000001U
+#define UART_SW_XON_INT_CLR_S  9
+/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define UART_SW_XOFF_INT_CLR    (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
+#define UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define UART_SW_XOFF_INT_CLR_S  10
+/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
+#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define UART_GLITCH_DET_INT_CLR_S  11
+/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
+#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define UART_TX_DONE_INT_CLR    (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
+#define UART_TX_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_DONE_INT_CLR_S  14
+/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+ */
+#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+ */
+#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the rs485_clash_int_raw interrupt.
+ */
+#define UART_RS485_CLASH_INT_CLR    (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
+#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
+#define UART_RS485_CLASH_INT_CLR_S  17
+/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define UART_WAKEUP_INT_CLR    (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
+#define UART_WAKEUP_INT_CLR_V  0x00000001U
+#define UART_WAKEUP_INT_CLR_S  19
+
+/** UART_CLKDIV_SYNC_REG register
+ *  Clock divider configuration
+ */
+#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
+/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define UART_CLKDIV    0x00000FFFU
+#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
+#define UART_CLKDIV_V  0x00000FFFU
+#define UART_CLKDIV_S  0
+/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define UART_CLKDIV_FRAG    0x0000000FU
+#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
+#define UART_CLKDIV_FRAG_V  0x0000000FU
+#define UART_CLKDIV_FRAG_S  20
+
+/** UART_RX_FILT_REG register
+ *  Rx Filter configuration
+ */
+#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
+/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value the pulse is ignored.
+ */
+#define UART_GLITCH_FILT    0x000000FFU
+#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
+#define UART_GLITCH_FILT_V  0x000000FFU
+#define UART_GLITCH_FILT_S  0
+/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
+#define UART_GLITCH_FILT_EN    (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
+#define UART_GLITCH_FILT_EN_V  0x00000001U
+#define UART_GLITCH_FILT_EN_S  8
+
+/** UART_STATUS_REG register
+ *  UART status register
+ */
+#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
+/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define UART_RXFIFO_CNT    0x000000FFU
+#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
+#define UART_RXFIFO_CNT_V  0x000000FFU
+#define UART_RXFIFO_CNT_S  0
+/** UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
+#define UART_DSRN    (BIT(13))
+#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
+#define UART_DSRN_V  0x00000001U
+#define UART_DSRN_S  13
+/** UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define UART_CTSN    (BIT(14))
+#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
+#define UART_CTSN_V  0x00000001U
+#define UART_CTSN_S  14
+/** UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define UART_RXD    (BIT(15))
+#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
+#define UART_RXD_V  0x00000001U
+#define UART_RXD_S  15
+/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define UART_TXFIFO_CNT    0x000000FFU
+#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
+#define UART_TXFIFO_CNT_V  0x000000FFU
+#define UART_TXFIFO_CNT_S  16
+/** UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define UART_DTRN    (BIT(29))
+#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
+#define UART_DTRN_V  0x00000001U
+#define UART_DTRN_S  29
+/** UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define UART_RTSN    (BIT(30))
+#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
+#define UART_RTSN_V  0x00000001U
+#define UART_RTSN_S  30
+/** UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define UART_TXD    (BIT(31))
+#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
+#define UART_TXD_V  0x00000001U
+#define UART_TXD_S  31
+
+/** UART_CONF0_SYNC_REG register
+ *  a
+ */
+#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
+/** UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
+#define UART_PARITY    (BIT(0))
+#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
+#define UART_PARITY_V  0x00000001U
+#define UART_PARITY_S  0
+/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define UART_PARITY_EN    (BIT(1))
+#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
+#define UART_PARITY_EN_V  0x00000001U
+#define UART_PARITY_EN_S  1
+/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define UART_BIT_NUM    0x00000003U
+#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
+#define UART_BIT_NUM_V  0x00000003U
+#define UART_BIT_NUM_S  2
+/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define UART_STOP_BIT_NUM    0x00000003U
+#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
+#define UART_STOP_BIT_NUM_V  0x00000003U
+#define UART_STOP_BIT_NUM_S  4
+/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define UART_TXD_BRK    (BIT(6))
+#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
+#define UART_TXD_BRK_V  0x00000001U
+#define UART_TXD_BRK_S  6
+/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable IrDA loopback mode.
+ */
+#define UART_IRDA_DPLX    (BIT(7))
+#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
+#define UART_IRDA_DPLX_V  0x00000001U
+#define UART_IRDA_DPLX_S  7
+/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the start enable bit for IrDA transmitter.
+ */
+#define UART_IRDA_TX_EN    (BIT(8))
+#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
+#define UART_IRDA_TX_EN_V  0x00000001U
+#define UART_IRDA_TX_EN_S  8
+/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
+ *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+ *  transmitter's 11th bit to 0.
+ */
+#define UART_IRDA_WCTL    (BIT(9))
+#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
+#define UART_IRDA_WCTL_V  0x00000001U
+#define UART_IRDA_WCTL_S  9
+/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to invert the level of  IrDA transmitter.
+ */
+#define UART_IRDA_TX_INV    (BIT(10))
+#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
+#define UART_IRDA_TX_INV_V  0x00000001U
+#define UART_IRDA_TX_INV_S  10
+/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to invert the level of IrDA receiver.
+ */
+#define UART_IRDA_RX_INV    (BIT(11))
+#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
+#define UART_IRDA_RX_INV_V  0x00000001U
+#define UART_IRDA_RX_INV_S  11
+/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define UART_LOOPBACK    (BIT(12))
+#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
+#define UART_LOOPBACK_V  0x00000001U
+#define UART_LOOPBACK_S  12
+/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define UART_TX_FLOW_EN    (BIT(13))
+#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
+#define UART_TX_FLOW_EN_V  0x00000001U
+#define UART_TX_FLOW_EN_S  13
+/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
+ *  Set this bit to enable IrDA protocol.
+ */
+#define UART_IRDA_EN    (BIT(14))
+#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
+#define UART_IRDA_EN_V  0x00000001U
+#define UART_IRDA_EN_S  14
+/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define UART_RXD_INV    (BIT(15))
+#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
+#define UART_RXD_INV_V  0x00000001U
+#define UART_RXD_INV_S  15
+/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define UART_TXD_INV    (BIT(16))
+#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
+#define UART_TXD_INV_V  0x00000001U
+#define UART_TXD_INV_S  16
+/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
+#define UART_DIS_RX_DAT_OVF    (BIT(17))
+#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
+#define UART_DIS_RX_DAT_OVF_V  0x00000001U
+#define UART_DIS_RX_DAT_OVF_S  17
+/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define UART_ERR_WR_MASK    (BIT(18))
+#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
+#define UART_ERR_WR_MASK_V  0x00000001U
+#define UART_ERR_WR_MASK_S  18
+/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for detecting baudrate.
+ */
+#define UART_AUTOBAUD_EN    (BIT(19))
+#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
+#define UART_AUTOBAUD_EN_V  0x00000001U
+#define UART_AUTOBAUD_EN_S  19
+/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  UART memory clock gate enable signal.
+ */
+#define UART_MEM_CLK_EN    (BIT(20))
+#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
+#define UART_MEM_CLK_EN_V  0x00000001U
+#define UART_MEM_CLK_EN_S  20
+/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_RTS    (BIT(21))
+#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
+#define UART_SW_RTS_V  0x00000001U
+#define UART_SW_RTS_S  21
+/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define UART_RXFIFO_RST    (BIT(22))
+#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
+#define UART_RXFIFO_RST_V  0x00000001U
+#define UART_RXFIFO_RST_S  22
+/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define UART_TXFIFO_RST    (BIT(23))
+#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
+#define UART_TXFIFO_RST_V  0x00000001U
+#define UART_TXFIFO_RST_S  23
+
+/** UART_CONF1_REG register
+ *  Configuration register 1
+ */
+#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
+/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define UART_RXFIFO_FULL_THRHD    0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
+#define UART_RXFIFO_FULL_THRHD_V  0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_S  0
+/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define UART_TXFIFO_EMPTY_THRHD    0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
+#define UART_TXFIFO_EMPTY_THRHD_V  0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_S  8
+/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define UART_CTS_INV    (BIT(16))
+#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
+#define UART_CTS_INV_V  0x00000001U
+#define UART_CTS_INV_S  16
+/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define UART_DSR_INV    (BIT(17))
+#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
+#define UART_DSR_INV_V  0x00000001U
+#define UART_DSR_INV_S  17
+/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define UART_RTS_INV    (BIT(18))
+#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
+#define UART_RTS_INV_V  0x00000001U
+#define UART_RTS_INV_S  18
+/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define UART_DTR_INV    (BIT(19))
+#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
+#define UART_DTR_INV_V  0x00000001U
+#define UART_DTR_INV_S  19
+/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_DTR    (BIT(20))
+#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
+#define UART_SW_DTR_V  0x00000001U
+#define UART_SW_DTR_S  20
+/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define UART_CLK_EN    (BIT(21))
+#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
+#define UART_CLK_EN_V  0x00000001U
+#define UART_CLK_EN_S  21
+
+/** UART_HWFC_CONF_SYNC_REG register
+ *  Hardware flow-control configuration
+ */
+#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
+/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define UART_RX_FLOW_THRHD    0x000000FFU
+#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
+#define UART_RX_FLOW_THRHD_V  0x000000FFU
+#define UART_RX_FLOW_THRHD_S  0
+/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define UART_RX_FLOW_EN    (BIT(8))
+#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
+#define UART_RX_FLOW_EN_V  0x00000001U
+#define UART_RX_FLOW_EN_S  8
+
+/** UART_SLEEP_CONF0_REG register
+ *  UART sleep configure register 0
+ */
+#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
+/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified wake up char1 to wake up
+ */
+#define UART_WK_CHAR1    0x000000FFU
+#define UART_WK_CHAR1_M  (UART_WK_CHAR1_V << UART_WK_CHAR1_S)
+#define UART_WK_CHAR1_V  0x000000FFU
+#define UART_WK_CHAR1_S  0
+/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
+ *  This register restores the specified wake up char2 to wake up
+ */
+#define UART_WK_CHAR2    0x000000FFU
+#define UART_WK_CHAR2_M  (UART_WK_CHAR2_V << UART_WK_CHAR2_S)
+#define UART_WK_CHAR2_V  0x000000FFU
+#define UART_WK_CHAR2_S  8
+/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
+ *  This register restores the specified wake up char3 to wake up
+ */
+#define UART_WK_CHAR3    0x000000FFU
+#define UART_WK_CHAR3_M  (UART_WK_CHAR3_V << UART_WK_CHAR3_S)
+#define UART_WK_CHAR3_V  0x000000FFU
+#define UART_WK_CHAR3_S  16
+/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
+ *  This register restores the specified wake up char4 to wake up
+ */
+#define UART_WK_CHAR4    0x000000FFU
+#define UART_WK_CHAR4_M  (UART_WK_CHAR4_V << UART_WK_CHAR4_S)
+#define UART_WK_CHAR4_V  0x000000FFU
+#define UART_WK_CHAR4_S  24
+
+/** UART_SLEEP_CONF1_REG register
+ *  UART sleep configure register 1
+ */
+#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
+/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified char0 to wake up
+ */
+#define UART_WK_CHAR0    0x000000FFU
+#define UART_WK_CHAR0_M  (UART_WK_CHAR0_V << UART_WK_CHAR0_S)
+#define UART_WK_CHAR0_V  0x000000FFU
+#define UART_WK_CHAR0_S  0
+
+/** UART_SLEEP_CONF2_REG register
+ *  UART sleep configure register 2
+ */
+#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
+/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define UART_ACTIVE_THRESHOLD    0x000003FFU
+#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
+#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
+#define UART_ACTIVE_THRESHOLD_S  0
+/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1;
+ *  In wake up mode 1 this field is used to set the received data number threshold to
+ *  wake up chip.
+ */
+#define UART_RX_WAKE_UP_THRHD    0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_M  (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S)
+#define UART_RX_WAKE_UP_THRHD_V  0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_S  10
+/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
+ *  This register is used to select number of wake up char.
+ */
+#define UART_WK_CHAR_NUM    0x00000007U
+#define UART_WK_CHAR_NUM_M  (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S)
+#define UART_WK_CHAR_NUM_V  0x00000007U
+#define UART_WK_CHAR_NUM_S  18
+/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
+ *  This register is used to mask  wake up char.
+ */
+#define UART_WK_CHAR_MASK    0x0000001FU
+#define UART_WK_CHAR_MASK_M  (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
+#define UART_WK_CHAR_MASK_V  0x0000001FU
+#define UART_WK_CHAR_MASK_S  21
+/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+ *  received data number larger than
+ */
+#define UART_WK_MODE_SEL    0x00000003U
+#define UART_WK_MODE_SEL_M  (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
+#define UART_WK_MODE_SEL_V  0x00000003U
+#define UART_WK_MODE_SEL_S  26
+
+/** UART_SWFC_CONF0_SYNC_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
+/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define UART_XON_CHAR    0x000000FFU
+#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
+#define UART_XON_CHAR_V  0x000000FFU
+#define UART_XON_CHAR_S  0
+/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define UART_XOFF_CHAR    0x000000FFU
+#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
+#define UART_XOFF_CHAR_V  0x000000FFU
+#define UART_XOFF_CHAR_S  8
+/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
+ *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+ *  this status, UART Tx can not transmit XOFF even the received data number is larger
+ *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+ *  UART Tx is disabled.
+ */
+#define UART_XON_XOFF_STILL_SEND    (BIT(16))
+#define UART_XON_XOFF_STILL_SEND_M  (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
+#define UART_XON_XOFF_STILL_SEND_V  0x00000001U
+#define UART_XON_XOFF_STILL_SEND_S  16
+/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
+#define UART_SW_FLOW_CON_EN    (BIT(17))
+#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
+#define UART_SW_FLOW_CON_EN_V  0x00000001U
+#define UART_SW_FLOW_CON_EN_S  17
+/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define UART_XONOFF_DEL    (BIT(18))
+#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
+#define UART_XONOFF_DEL_V  0x00000001U
+#define UART_XONOFF_DEL_S  18
+/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define UART_FORCE_XON    (BIT(19))
+#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
+#define UART_FORCE_XON_V  0x00000001U
+#define UART_FORCE_XON_S  19
+/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define UART_FORCE_XOFF    (BIT(20))
+#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
+#define UART_FORCE_XOFF_V  0x00000001U
+#define UART_FORCE_XOFF_S  20
+/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XON    (BIT(21))
+#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
+#define UART_SEND_XON_V  0x00000001U
+#define UART_SEND_XON_S  21
+/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XOFF    (BIT(22))
+#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
+#define UART_SEND_XOFF_V  0x00000001U
+#define UART_SEND_XOFF_S  22
+
+/** UART_SWFC_CONF1_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
+/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+ */
+#define UART_XON_THRESHOLD    0x000000FFU
+#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
+#define UART_XON_THRESHOLD_V  0x000000FFU
+#define UART_XON_THRESHOLD_S  0
+/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+ */
+#define UART_XOFF_THRESHOLD    0x000000FFU
+#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
+#define UART_XOFF_THRESHOLD_V  0x000000FFU
+#define UART_XOFF_THRESHOLD_S  8
+
+/** UART_TXBRK_CONF_SYNC_REG register
+ *  Tx Break character configuration
+ */
+#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
+/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define UART_TX_BRK_NUM    0x000000FFU
+#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
+#define UART_TX_BRK_NUM_V  0x000000FFU
+#define UART_TX_BRK_NUM_S  0
+
+/** UART_IDLE_CONF_SYNC_REG register
+ *  Frame-end idle configuration
+ */
+#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
+/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define UART_RX_IDLE_THRHD    0x000003FFU
+#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
+#define UART_RX_IDLE_THRHD_V  0x000003FFU
+#define UART_RX_IDLE_THRHD_S  0
+/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define UART_TX_IDLE_NUM    0x000003FFU
+#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
+#define UART_TX_IDLE_NUM_V  0x000003FFU
+#define UART_TX_IDLE_NUM_S  10
+
+/** UART_RS485_CONF_SYNC_REG register
+ *  RS485 mode configuration
+ */
+#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
+/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to choose the rs485 mode.
+ */
+#define UART_RS485_EN    (BIT(0))
+#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
+#define UART_RS485_EN_V  0x00000001U
+#define UART_RS485_EN_S  0
+/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL0_EN    (BIT(1))
+#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
+#define UART_DL0_EN_V  0x00000001U
+#define UART_DL0_EN_S  1
+/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL1_EN    (BIT(2))
+#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
+#define UART_DL1_EN_V  0x00000001U
+#define UART_DL1_EN_S  2
+/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable receiver could receive data when the transmitter is
+ *  transmitting data in rs485 mode.
+ */
+#define UART_RS485TX_RX_EN    (BIT(3))
+#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
+#define UART_RS485TX_RX_EN_V  0x00000001U
+#define UART_RS485TX_RX_EN_S  3
+/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+ */
+#define UART_RS485RXBY_TX_EN    (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
+#define UART_RS485RXBY_TX_EN_V  0x00000001U
+#define UART_RS485RXBY_TX_EN_S  4
+/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
+ *  This register is used to delay the receiver's internal data signal.
+ */
+#define UART_RS485_RX_DLY_NUM    (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
+#define UART_RS485_RX_DLY_NUM_V  0x00000001U
+#define UART_RS485_RX_DLY_NUM_S  5
+/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
+ *  This register is used to delay the transmitter's internal data signal.
+ */
+#define UART_RS485_TX_DLY_NUM    0x0000000FU
+#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
+#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
+#define UART_RS485_TX_DLY_NUM_S  6
+
+/** UART_AT_CMD_PRECNT_SYNC_REG register
+ *  Pre-sequence timing configuration
+ */
+#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
+/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define UART_PRE_IDLE_NUM    0x0000FFFFU
+#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
+#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
+#define UART_PRE_IDLE_NUM_S  0
+
+/** UART_AT_CMD_POSTCNT_SYNC_REG register
+ *  Post-sequence timing configuration
+ */
+#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
+/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define UART_POST_IDLE_NUM    0x0000FFFFU
+#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
+#define UART_POST_IDLE_NUM_V  0x0000FFFFU
+#define UART_POST_IDLE_NUM_S  0
+
+/** UART_AT_CMD_GAPTOUT_SYNC_REG register
+ *  Timeout configuration
+ */
+#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
+/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define UART_RX_GAP_TOUT    0x0000FFFFU
+#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
+#define UART_RX_GAP_TOUT_V  0x0000FFFFU
+#define UART_RX_GAP_TOUT_S  0
+
+/** UART_AT_CMD_CHAR_SYNC_REG register
+ *  AT escape sequence detection configuration
+ */
+#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
+/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define UART_AT_CMD_CHAR    0x000000FFU
+#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
+#define UART_AT_CMD_CHAR_V  0x000000FFU
+#define UART_AT_CMD_CHAR_S  0
+/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define UART_CHAR_NUM    0x000000FFU
+#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
+#define UART_CHAR_NUM_V  0x000000FFU
+#define UART_CHAR_NUM_S  8
+
+/** UART_MEM_CONF_REG register
+ *  UART memory power configuration
+ */
+#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
+/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
+#define UART_MEM_FORCE_PD    (BIT(25))
+#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
+#define UART_MEM_FORCE_PD_V  0x00000001U
+#define UART_MEM_FORCE_PD_S  25
+/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define UART_MEM_FORCE_PU    (BIT(26))
+#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
+#define UART_MEM_FORCE_PU_V  0x00000001U
+#define UART_MEM_FORCE_PU_S  26
+
+/** UART_TOUT_CONF_SYNC_REG register
+ *  UART threshold and allocation configuration
+ */
+#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
+/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for uart receiver's timeout function.
+ */
+#define UART_RX_TOUT_EN    (BIT(0))
+#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
+#define UART_RX_TOUT_EN_V  0x00000001U
+#define UART_RX_TOUT_EN_S  0
+/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define UART_RX_TOUT_FLOW_DIS    (BIT(1))
+#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
+#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define UART_RX_TOUT_FLOW_DIS_S  1
+/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define UART_RX_TOUT_THRHD    0x000003FFU
+#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
+#define UART_RX_TOUT_THRHD_V  0x000003FFU
+#define UART_RX_TOUT_THRHD_S  2
+
+/** UART_MEM_TX_STATUS_REG register
+ *  Tx-SRAM write and read offset address.
+ */
+#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
+/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
+ *  This register stores the offset write address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_WADDR    0x000000FFU
+#define UART_TX_SRAM_WADDR_M  (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S)
+#define UART_TX_SRAM_WADDR_V  0x000000FFU
+#define UART_TX_SRAM_WADDR_S  0
+/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0;
+ *  This register stores the offset read address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_RADDR    0x000000FFU
+#define UART_TX_SRAM_RADDR_M  (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S)
+#define UART_TX_SRAM_RADDR_V  0x000000FFU
+#define UART_TX_SRAM_RADDR_S  9
+
+/** UART_MEM_RX_STATUS_REG register
+ *  Rx-SRAM write and read offset address.
+ */
+#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
+/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
+ *  This register stores the offset read address in RX-SRAM.
+ */
+#define UART_RX_SRAM_RADDR    0x000000FFU
+#define UART_RX_SRAM_RADDR_M  (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S)
+#define UART_RX_SRAM_RADDR_V  0x000000FFU
+#define UART_RX_SRAM_RADDR_S  0
+/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128;
+ *  This register stores the offset write address in Rx-SRAM.
+ */
+#define UART_RX_SRAM_WADDR    0x000000FFU
+#define UART_RX_SRAM_WADDR_M  (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S)
+#define UART_RX_SRAM_WADDR_V  0x000000FFU
+#define UART_RX_SRAM_WADDR_S  9
+
+/** UART_FSM_STATUS_REG register
+ *  UART transmit and receive status.
+ */
+#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
+/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define UART_ST_URX_OUT    0x0000000FU
+#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
+#define UART_ST_URX_OUT_V  0x0000000FU
+#define UART_ST_URX_OUT_S  0
+/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define UART_ST_UTX_OUT    0x0000000FU
+#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
+#define UART_ST_UTX_OUT_V  0x0000000FU
+#define UART_ST_UTX_OUT_S  4
+
+/** UART_POSPULSE_REG register
+ *  Autobaud high pulse register
+ */
+#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
+/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two positive edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_POSEDGE_MIN_CNT    0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
+#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_S  0
+
+/** UART_NEGPULSE_REG register
+ *  Autobaud low pulse register
+ */
+#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
+/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two negative edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
+#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+/** UART_LOWPULSE_REG register
+ *  Autobaud minimum low pulse duration register
+ */
+#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
+/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the value of the minimum duration time of the low level pulse.
+ *  It is used in baud rate-detect process.
+ */
+#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
+#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+/** UART_HIGHPULSE_REG register
+ *  Autobaud minimum high pulse duration register
+ */
+#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
+/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores  the value of the maximum duration time for the high level
+ *  pulse. It is used in baud rate-detect process.
+ */
+#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
+#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+/** UART_RXD_CNT_REG register
+ *  Autobaud edge change count register
+ */
+#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
+/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
+ *  This register stores the count of rxd edge change. It is used in baud rate-detect
+ *  process.
+ */
+#define UART_RXD_EDGE_CNT    0x000003FFU
+#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
+#define UART_RXD_EDGE_CNT_V  0x000003FFU
+#define UART_RXD_EDGE_CNT_S  0
+
+/** UART_CLK_CONF_REG register
+ *  UART core clock configuration
+ */
+#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
+/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable UART Tx clock.
+ */
+#define UART_TX_SCLK_EN    (BIT(24))
+#define UART_TX_SCLK_EN_M  (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
+#define UART_TX_SCLK_EN_V  0x00000001U
+#define UART_TX_SCLK_EN_S  24
+/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Set this bit to enable UART Rx clock.
+ */
+#define UART_RX_SCLK_EN    (BIT(25))
+#define UART_RX_SCLK_EN_M  (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
+#define UART_RX_SCLK_EN_V  0x00000001U
+#define UART_RX_SCLK_EN_S  25
+/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Tx.
+ */
+#define UART_TX_RST_CORE    (BIT(26))
+#define UART_TX_RST_CORE_M  (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
+#define UART_TX_RST_CORE_V  0x00000001U
+#define UART_TX_RST_CORE_S  26
+/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Rx.
+ */
+#define UART_RX_RST_CORE    (BIT(27))
+#define UART_RX_RST_CORE_M  (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
+#define UART_RX_RST_CORE_V  0x00000001U
+#define UART_RX_RST_CORE_S  27
+
+/** UART_DATE_REG register
+ *  UART Version register
+ */
+#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
+/** UART_DATE : R/W; bitpos: [31:0]; default: 36720720;
+ *  This is the version register.
+ */
+#define UART_DATE    0xFFFFFFFFU
+#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
+#define UART_DATE_V  0xFFFFFFFFU
+#define UART_DATE_S  0
+
+/** UART_AFIFO_STATUS_REG register
+ *  UART AFIFO Status
+ */
+#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
+/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
+ *  Full signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_FULL    (BIT(0))
+#define UART_TX_AFIFO_FULL_M  (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
+#define UART_TX_AFIFO_FULL_V  0x00000001U
+#define UART_TX_AFIFO_FULL_S  0
+/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
+ *  Empty signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_EMPTY    (BIT(1))
+#define UART_TX_AFIFO_EMPTY_M  (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
+#define UART_TX_AFIFO_EMPTY_V  0x00000001U
+#define UART_TX_AFIFO_EMPTY_S  1
+/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
+ *  Full signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_FULL    (BIT(2))
+#define UART_RX_AFIFO_FULL_M  (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
+#define UART_RX_AFIFO_FULL_V  0x00000001U
+#define UART_RX_AFIFO_FULL_S  2
+/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
+ *  Empty signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_EMPTY    (BIT(3))
+#define UART_RX_AFIFO_EMPTY_M  (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
+#define UART_RX_AFIFO_EMPTY_V  0x00000001U
+#define UART_RX_AFIFO_EMPTY_S  3
+
+/** UART_REG_UPDATE_REG register
+ *  UART Registers Configuration Update register
+ */
+#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
+/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define UART_REG_UPDATE    (BIT(0))
+#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
+#define UART_REG_UPDATE_V  0x00000001U
+#define UART_REG_UPDATE_S  0
+
+/** UART_ID_REG register
+ *  UART ID register
+ */
+#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
+/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define UART_ID    0xFFFFFFFFU
+#define UART_ID_M  (UART_ID_V << UART_ID_S)
+#define UART_ID_V  0xFFFFFFFFU
+#define UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h
new file mode 100644
index 0000000000..5b98af7ceb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h
@@ -0,0 +1,1276 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13425
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         */
+        uint32_t rxfifo_rd_byte:32;
+    };
+    uint32_t val;
+} uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full_int_raw:1;
+        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty_int_raw:1;
+        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err_int_raw:1;
+        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg_int_raw:1;
+        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg_int_raw:1;
+        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det_int_raw:1;
+        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout_int_raw:1;
+        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon_int_raw:1;
+        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff_int_raw:1;
+        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det_int_raw:1;
+        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done_int_raw:1;
+        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done_int_raw:1;
+        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_parity_err_int_raw:1;
+        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_frm_err_int_raw:1;
+        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  This interrupt raw bit turns to high level when detects a clash between transmitter
+         *  and receiver in rs485 mode.
+         */
+        uint32_t rs485_clash_int_raw:1;
+        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det_int_raw:1;
+        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full_int_st:1;
+        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty_int_st:1;
+        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err_int_st:1;
+        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg_int_st:1;
+        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg_int_st:1;
+        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det_int_st:1;
+        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout_int_st:1;
+        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon_int_st:1;
+        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff_int_st:1;
+        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det_int_st:1;
+        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done_int_st:1;
+        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done_int_st:1;
+        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
+         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+         *  set to 1.
+         */
+        uint32_t rs485_parity_err_int_st:1;
+        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
+         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+         *  to 1.
+         */
+        uint32_t rs485_frm_err_int_st:1;
+        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
+         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+         */
+        uint32_t rs485_clash_int_st:1;
+        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det_int_st:1;
+        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full_int_ena:1;
+        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty_int_ena:1;
+        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err_int_ena:1;
+        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg_int_ena:1;
+        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg_int_ena:1;
+        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det_int_ena:1;
+        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout_int_ena:1;
+        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon_int_ena:1;
+        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff_int_ena:1;
+        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det_int_ena:1;
+        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done_int_ena:1;
+        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_parity_err_int_ena:1;
+        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_frm_err_int_ena:1;
+        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
+         *  This is the enable bit for rs485_clash_int_st register.
+         */
+        uint32_t rs485_clash_int_ena:1;
+        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det_int_ena:1;
+        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full_int_clr:1;
+        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty_int_clr:1;
+        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err_int_clr:1;
+        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg_int_clr:1;
+        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg_int_clr:1;
+        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det_int_clr:1;
+        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout_int_clr:1;
+        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon_int_clr:1;
+        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff_int_clr:1;
+        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det_int_clr:1;
+        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done_int_clr:1;
+        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+         */
+        uint32_t rs485_parity_err_int_clr:1;
+        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+         */
+        uint32_t rs485_frm_err_int_clr:1;
+        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the rs485_clash_int_raw interrupt.
+         */
+        uint32_t rs485_clash_int_clr:1;
+        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det_int_clr:1;
+        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  a
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        /** irda_dplx : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable IrDA loopback mode.
+         */
+        uint32_t irda_dplx:1;
+        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
+         *  This is the start enable bit for IrDA transmitter.
+         */
+        uint32_t irda_tx_en:1;
+        /** irda_wctl : R/W; bitpos: [9]; default: 0;
+         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+         *  transmitter's 11th bit to 0.
+         */
+        uint32_t irda_wctl:1;
+        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to invert the level of  IrDA transmitter.
+         */
+        uint32_t irda_tx_inv:1;
+        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to invert the level of IrDA receiver.
+         */
+        uint32_t irda_rx_inv:1;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        /** irda_en : R/W; bitpos: [14]; default: 0;
+         *  Set this bit to enable IrDA protocol.
+         */
+        uint32_t irda_en:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        /** autobaud_en : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for detecting baudrate.
+         */
+        uint32_t autobaud_en:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:8;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:8;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow-control configuration
+ */
+typedef union {
+    struct {
+        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:8;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configure register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified wake up char1 to wake up
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  This register restores the specified wake up char2 to wake up
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  This register restores the specified wake up char3 to wake up
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  This register restores the specified wake up char4 to wake up
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configure register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified char0 to wake up
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configure register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
+         *  In wake up mode 1 this field is used to set the received data number threshold to
+         *  wake up chip.
+         */
+        uint32_t rx_wake_up_thrhd:8;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  This register is used to select number of wake up char.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  This register is used to mask  wake up char.
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+         *  received data number larger than
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_character : R/W; bitpos: [7:0]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_character:8;
+        /** xoff_character : R/W; bitpos: [15:8]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_character:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+         *  this status, UART Tx can not transmit XOFF even the received data number is larger
+         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+         *  UART Tx is disabled.
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+         */
+        uint32_t xon_threshold:8;
+        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        /** rs485_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to choose the rs485 mode.
+         */
+        uint32_t rs485_en:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable receiver could receive data when the transmitter is
+         *  transmitting data in rs485 mode.
+         */
+        uint32_t rs485tx_rx_en:1;
+        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+         */
+        uint32_t rs485rxby_tx_en:1;
+        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
+         *  This register is used to delay the receiver's internal data signal.
+         */
+        uint32_t rs485_rx_dly_num:1;
+        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
+         *  This register is used to delay the transmitter's internal data signal.
+         */
+        uint32_t rs485_tx_dly_num:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rs485_conf_sync_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable UART Tx clock.
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Set this bit to enable UART Rx clock.
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Tx.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Rx.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:8;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:8;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
+         *  This register stores the offset write address in Tx-SRAM.
+         */
+        uint32_t tx_sram_waddr:8;
+        uint32_t reserved_8:1;
+        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
+         *  This register stores the offset read address in Tx-SRAM.
+         */
+        uint32_t tx_sram_raddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
+         *  This register stores the offset read address in RX-SRAM.
+         */
+        uint32_t rx_sram_raddr:8;
+        uint32_t reserved_8:1;
+        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
+         *  This register stores the offset write address in Rx-SRAM.
+         */
+        uint32_t rx_sram_waddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART AFIFO Status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Full signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Empty signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Full signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Empty signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t at_cmd_char:8;
+        /** at_char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t at_char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Autobaud Register */
+/** Type of pospulse register
+ *  Autobaud high pulse register
+ */
+typedef union {
+    struct {
+        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two positive edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t posedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_pospulse_reg_t;
+
+/** Type of negpulse register
+ *  Autobaud low pulse register
+ */
+typedef union {
+    struct {
+        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two negative edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t negedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_negpulse_reg_t;
+
+/** Type of lowpulse register
+ *  Autobaud minimum low pulse duration register
+ */
+typedef union {
+    struct {
+        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the value of the minimum duration time of the low level pulse.
+         *  It is used in baud rate-detect process.
+         */
+        uint32_t lowpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_lowpulse_reg_t;
+
+/** Type of highpulse register
+ *  Autobaud minimum high pulse duration register
+ */
+typedef union {
+    struct {
+        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores  the value of the maximum duration time for the high level
+         *  pulse. It is used in baud rate-detect process.
+         */
+        uint32_t highpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_highpulse_reg_t;
+
+/** Type of rxd_cnt register
+ *  Autobaud edge change count register
+ */
+typedef union {
+    struct {
+        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
+         *  This register stores the count of rxd edge change. It is used in baud rate-detect
+         *  process.
+         */
+        uint32_t rxd_edge_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rxd_cnt_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36720720;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART Registers Configuration Update register
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} uart_id_reg_t;
+
+
+typedef struct uart_dev_t{
+    volatile uart_fifo_reg_t fifo;
+    volatile uart_int_raw_reg_t int_raw;
+    volatile uart_int_st_reg_t int_st;
+    volatile uart_int_ena_reg_t int_ena;
+    volatile uart_int_clr_reg_t int_clr;
+    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile uart_rx_filt_reg_t rx_filt;
+    volatile uart_status_reg_t status;
+    volatile uart_conf0_sync_reg_t conf0_sync;
+    volatile uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile uart_sleep_conf0_reg_t sleep_conf0;
+    volatile uart_sleep_conf1_reg_t sleep_conf1;
+    volatile uart_sleep_conf2_reg_t sleep_conf2;
+    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile uart_swfc_conf1_reg_t swfc_conf1;
+    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile uart_mem_conf_reg_t mem_conf;
+    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile uart_mem_tx_status_reg_t mem_tx_status;
+    volatile uart_mem_rx_status_reg_t mem_rx_status;
+    volatile uart_fsm_status_reg_t fsm_status;
+    volatile uart_pospulse_reg_t pospulse;      /* LP_UART instance has this register reserved */
+    volatile uart_negpulse_reg_t negpulse;      /* LP_UART instance has this register reserved */
+    volatile uart_lowpulse_reg_t lowpulse;      /* LP_UART instance has this register reserved */
+    volatile uart_highpulse_reg_t highpulse;    /* LP_UART instance has this register reserved */
+    volatile uart_rxd_cnt_reg_t rxd_cnt;        /* LP_UART instance has this register reserved */
+    volatile uart_clk_conf_reg_t clk_conf;
+    volatile uart_date_reg_t date;
+    volatile uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile uart_reg_update_reg_t reg_update;
+    volatile uart_id_reg_t id;
+} uart_dev_t;
+
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+extern uart_dev_t UART2;
+extern uart_dev_t UART3;
+extern uart_dev_t UART4;
+extern uart_dev_t LP_UART;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uhci_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/uhci_reg.h
new file mode 100644
index 0000000000..74e047a248
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/uhci_reg.h
@@ -0,0 +1,966 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** UHCI_CONF0_REG register
+ *  UHCI Configuration Register0
+ */
+#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0)
+/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0 to this bit to reset decode state machine.
+ */
+#define UHCI_TX_RST    (BIT(0))
+#define UHCI_TX_RST_M  (UHCI_TX_RST_V << UHCI_TX_RST_S)
+#define UHCI_TX_RST_V  0x00000001U
+#define UHCI_TX_RST_S  0
+/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0 to this bit to reset encode state machine.
+ */
+#define UHCI_RX_RST    (BIT(1))
+#define UHCI_RX_RST_M  (UHCI_RX_RST_V << UHCI_RX_RST_S)
+#define UHCI_RX_RST_V  0x00000001U
+#define UHCI_RX_RST_S  1
+/** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 7;
+ *  Select which uart to connect with GDMA.
+ */
+#define UHCI_UART_SEL    0x00000007U
+#define UHCI_UART_SEL_M  (UHCI_UART_SEL_V << UHCI_UART_SEL_S)
+#define UHCI_UART_SEL_V  0x00000007U
+#define UHCI_UART_SEL_S  2
+/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1;
+ *  Set this bit to separate the data frame using a special char.
+ */
+#define UHCI_SEPER_EN    (BIT(5))
+#define UHCI_SEPER_EN_M  (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S)
+#define UHCI_SEPER_EN_V  0x00000001U
+#define UHCI_SEPER_EN_S  5
+/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1;
+ *  Set this bit to encode the data packet with a formatting header.
+ */
+#define UHCI_HEAD_EN    (BIT(6))
+#define UHCI_HEAD_EN_M  (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S)
+#define UHCI_HEAD_EN_V  0x00000001U
+#define UHCI_HEAD_EN_S  6
+/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1;
+ *  Set this bit to enable UHCI to receive the 16 bit CRC.
+ */
+#define UHCI_CRC_REC_EN    (BIT(7))
+#define UHCI_CRC_REC_EN_M  (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S)
+#define UHCI_CRC_REC_EN_V  0x00000001U
+#define UHCI_CRC_REC_EN_S  7
+/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0;
+ *  If this bit is set to 1 UHCI will end the payload receiving process when UART has
+ *  been in idle state.
+ */
+#define UHCI_UART_IDLE_EOF_EN    (BIT(8))
+#define UHCI_UART_IDLE_EOF_EN_M  (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S)
+#define UHCI_UART_IDLE_EOF_EN_V  0x00000001U
+#define UHCI_UART_IDLE_EOF_EN_S  8
+/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1;
+ *  If this bit is set to 1 UHCI decoder receiving payload data is end when the
+ *  receiving byte count has reached the specified value. The value is payload length
+ *  indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
+ *  configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
+ *  receiving payload data is end when 0xc0 is received.
+ */
+#define UHCI_LEN_EOF_EN    (BIT(9))
+#define UHCI_LEN_EOF_EN_M  (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S)
+#define UHCI_LEN_EOF_EN_V  0x00000001U
+#define UHCI_LEN_EOF_EN_S  9
+/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1;
+ *  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
+ *  end of the payload.
+ */
+#define UHCI_ENCODE_CRC_EN    (BIT(10))
+#define UHCI_ENCODE_CRC_EN_M  (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S)
+#define UHCI_ENCODE_CRC_EN_V  0x00000001U
+#define UHCI_ENCODE_CRC_EN_S  10
+/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
+ *  registers.
+ */
+#define UHCI_CLK_EN    (BIT(11))
+#define UHCI_CLK_EN_M  (UHCI_CLK_EN_V << UHCI_CLK_EN_S)
+#define UHCI_CLK_EN_V  0x00000001U
+#define UHCI_CLK_EN_S  11
+/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0;
+ *  If this bit is set to 1 UHCI will end payload receive process when NULL frame is
+ *  received by UART.
+ */
+#define UHCI_UART_RX_BRK_EOF_EN    (BIT(12))
+#define UHCI_UART_RX_BRK_EOF_EN_M  (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S)
+#define UHCI_UART_RX_BRK_EOF_EN_V  0x00000001U
+#define UHCI_UART_RX_BRK_EOF_EN_S  12
+
+/** UHCI_INT_RAW_REG register
+ *  UHCI Interrupt Raw Register
+ */
+#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4)
+/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when
+ *  delimiter is sent successfully.
+ */
+#define UHCI_RX_START_INT_RAW    (BIT(0))
+#define UHCI_RX_START_INT_RAW_M  (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S)
+#define UHCI_RX_START_INT_RAW_V  0x00000001U
+#define UHCI_RX_START_INT_RAW_S  0
+/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when
+ *  DMA detects delimiter.
+ */
+#define UHCI_TX_START_INT_RAW    (BIT(1))
+#define UHCI_TX_START_INT_RAW_M  (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S)
+#define UHCI_TX_START_INT_RAW_V  0x00000001U
+#define UHCI_TX_START_INT_RAW_S  1
+/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when
+ *  the required time of DMA receiving data  exceeds the configuration value.
+ */
+#define UHCI_RX_HUNG_INT_RAW    (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_M  (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S)
+#define UHCI_RX_HUNG_INT_RAW_V  0x00000001U
+#define UHCI_RX_HUNG_INT_RAW_S  2
+/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when
+ *  the required time of DMA reading RAM data  exceeds the configuration value.
+ */
+#define UHCI_TX_HUNG_INT_RAW    (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_M  (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S)
+#define UHCI_TX_HUNG_INT_RAW_V  0x00000001U
+#define UHCI_TX_HUNG_INT_RAW_S  3
+/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered
+ *  when UHCI sends short packet successfully with single_send mode.
+ */
+#define UHCI_SEND_S_REG_Q_INT_RAW    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_RAW_M  (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S)
+#define UHCI_SEND_S_REG_Q_INT_RAW_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_RAW_S  4
+/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered
+ *  when UHCI sends short packet successfully with always_send mode.
+ */
+#define UHCI_SEND_A_REG_Q_INT_RAW    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_RAW_M  (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S)
+#define UHCI_SEND_A_REG_Q_INT_RAW_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_RAW_S  5
+/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when
+ *  there are errors in EOF.
+ */
+#define UHCI_OUT_EOF_INT_RAW    (BIT(6))
+#define UHCI_OUT_EOF_INT_RAW_M  (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S)
+#define UHCI_OUT_EOF_INT_RAW_V  0x00000001U
+#define UHCI_OUT_EOF_INT_RAW_S  6
+/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0;
+ *  Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when
+ *  UHCI_APP_CTRL0_IN_SET is set to 1.
+ */
+#define UHCI_APP_CTRL0_INT_RAW    (BIT(7))
+#define UHCI_APP_CTRL0_INT_RAW_M  (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S)
+#define UHCI_APP_CTRL0_INT_RAW_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_RAW_S  7
+/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0;
+ *  Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when
+ *  UHCI_APP_CTRL1_IN_SET is set to 1.
+ */
+#define UHCI_APP_CTRL1_INT_RAW    (BIT(8))
+#define UHCI_APP_CTRL1_INT_RAW_M  (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S)
+#define UHCI_APP_CTRL1_INT_RAW_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_RAW_S  8
+
+/** UHCI_INT_ST_REG register
+ *  UHCI Interrupt Status Register
+ */
+#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8)
+/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Indicates the interrupt status of UHCI_RX_START_INT.
+ */
+#define UHCI_RX_START_INT_ST    (BIT(0))
+#define UHCI_RX_START_INT_ST_M  (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S)
+#define UHCI_RX_START_INT_ST_V  0x00000001U
+#define UHCI_RX_START_INT_ST_S  0
+/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Indicates the interrupt status of UHCI_TX_START_INT.
+ */
+#define UHCI_TX_START_INT_ST    (BIT(1))
+#define UHCI_TX_START_INT_ST_M  (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S)
+#define UHCI_TX_START_INT_ST_V  0x00000001U
+#define UHCI_TX_START_INT_ST_S  1
+/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Indicates the interrupt status of UHCI_RX_HUNG_INT.
+ */
+#define UHCI_RX_HUNG_INT_ST    (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_M  (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S)
+#define UHCI_RX_HUNG_INT_ST_V  0x00000001U
+#define UHCI_RX_HUNG_INT_ST_S  2
+/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Indicates the interrupt status of UHCI_TX_HUNG_INT.
+ */
+#define UHCI_TX_HUNG_INT_ST    (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_M  (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S)
+#define UHCI_TX_HUNG_INT_ST_V  0x00000001U
+#define UHCI_TX_HUNG_INT_ST_S  3
+/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0;
+ *  Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.
+ */
+#define UHCI_SEND_S_REG_Q_INT_ST    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_ST_M  (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S)
+#define UHCI_SEND_S_REG_Q_INT_ST_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_ST_S  4
+/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0;
+ *  Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.
+ */
+#define UHCI_SEND_A_REG_Q_INT_ST    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_ST_M  (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S)
+#define UHCI_SEND_A_REG_Q_INT_ST_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_ST_S  5
+/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  Indicates the interrupt status of UHCI_OUT_EOF_INT.
+ */
+#define UHCI_OUTLINK_EOF_ERR_INT_ST    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S)
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x00000001U
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  6
+/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  Indicates the interrupt status of UHCI_APP_CTRL0_INT.
+ */
+#define UHCI_APP_CTRL0_INT_ST    (BIT(7))
+#define UHCI_APP_CTRL0_INT_ST_M  (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S)
+#define UHCI_APP_CTRL0_INT_ST_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_ST_S  7
+/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  Indicates the interrupt status of UHCI_APP_CTRL1_INT.
+ */
+#define UHCI_APP_CTRL1_INT_ST    (BIT(8))
+#define UHCI_APP_CTRL1_INT_ST_M  (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S)
+#define UHCI_APP_CTRL1_INT_ST_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_ST_S  8
+
+/** UHCI_INT_ENA_REG register
+ *  UHCI Interrupt Enable Register
+ */
+#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc)
+/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_RX_START_INT.
+ */
+#define UHCI_RX_START_INT_ENA    (BIT(0))
+#define UHCI_RX_START_INT_ENA_M  (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S)
+#define UHCI_RX_START_INT_ENA_V  0x00000001U
+#define UHCI_RX_START_INT_ENA_S  0
+/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_TX_START_INT.
+ */
+#define UHCI_TX_START_INT_ENA    (BIT(1))
+#define UHCI_TX_START_INT_ENA_M  (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S)
+#define UHCI_TX_START_INT_ENA_V  0x00000001U
+#define UHCI_TX_START_INT_ENA_S  1
+/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.
+ */
+#define UHCI_RX_HUNG_INT_ENA    (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_M  (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S)
+#define UHCI_RX_HUNG_INT_ENA_V  0x00000001U
+#define UHCI_RX_HUNG_INT_ENA_S  2
+/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.
+ */
+#define UHCI_TX_HUNG_INT_ENA    (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_M  (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S)
+#define UHCI_TX_HUNG_INT_ENA_V  0x00000001U
+#define UHCI_TX_HUNG_INT_ENA_S  3
+/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.
+ */
+#define UHCI_SEND_S_REG_Q_INT_ENA    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_ENA_M  (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S)
+#define UHCI_SEND_S_REG_Q_INT_ENA_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_ENA_S  4
+/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.
+ */
+#define UHCI_SEND_A_REG_Q_INT_ENA    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_ENA_M  (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S)
+#define UHCI_SEND_A_REG_Q_INT_ENA_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_ENA_S  5
+/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.
+ */
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S)
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x00000001U
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  6
+/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.
+ */
+#define UHCI_APP_CTRL0_INT_ENA    (BIT(7))
+#define UHCI_APP_CTRL0_INT_ENA_M  (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S)
+#define UHCI_APP_CTRL0_INT_ENA_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_ENA_S  7
+/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.
+ */
+#define UHCI_APP_CTRL1_INT_ENA    (BIT(8))
+#define UHCI_APP_CTRL1_INT_ENA_M  (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S)
+#define UHCI_APP_CTRL1_INT_ENA_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_ENA_S  8
+
+/** UHCI_INT_CLR_REG register
+ *  UHCI Interrupt Clear Register
+ */
+#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10)
+/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_RX_START_INT.
+ */
+#define UHCI_RX_START_INT_CLR    (BIT(0))
+#define UHCI_RX_START_INT_CLR_M  (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S)
+#define UHCI_RX_START_INT_CLR_V  0x00000001U
+#define UHCI_RX_START_INT_CLR_S  0
+/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_TX_START_INT.
+ */
+#define UHCI_TX_START_INT_CLR    (BIT(1))
+#define UHCI_TX_START_INT_CLR_M  (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S)
+#define UHCI_TX_START_INT_CLR_V  0x00000001U
+#define UHCI_TX_START_INT_CLR_S  1
+/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.
+ */
+#define UHCI_RX_HUNG_INT_CLR    (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_M  (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S)
+#define UHCI_RX_HUNG_INT_CLR_V  0x00000001U
+#define UHCI_RX_HUNG_INT_CLR_S  2
+/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.
+ */
+#define UHCI_TX_HUNG_INT_CLR    (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_M  (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S)
+#define UHCI_TX_HUNG_INT_CLR_V  0x00000001U
+#define UHCI_TX_HUNG_INT_CLR_S  3
+/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.
+ */
+#define UHCI_SEND_S_REG_Q_INT_CLR    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_CLR_M  (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S)
+#define UHCI_SEND_S_REG_Q_INT_CLR_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_CLR_S  4
+/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.
+ */
+#define UHCI_SEND_A_REG_Q_INT_CLR    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_CLR_M  (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S)
+#define UHCI_SEND_A_REG_Q_INT_CLR_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_CLR_S  5
+/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.
+ */
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S)
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x00000001U
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  6
+/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.
+ */
+#define UHCI_APP_CTRL0_INT_CLR    (BIT(7))
+#define UHCI_APP_CTRL0_INT_CLR_M  (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S)
+#define UHCI_APP_CTRL0_INT_CLR_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_CLR_S  7
+/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.
+ */
+#define UHCI_APP_CTRL1_INT_CLR    (BIT(8))
+#define UHCI_APP_CTRL1_INT_CLR_M  (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S)
+#define UHCI_APP_CTRL1_INT_CLR_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_CLR_S  8
+
+/** UHCI_CONF1_REG register
+ *  UHCI Configuration Register1
+ */
+#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14)
+/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to enable head checksum check when receiving.
+ */
+#define UHCI_CHECK_SUM_EN    (BIT(0))
+#define UHCI_CHECK_SUM_EN_M  (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S)
+#define UHCI_CHECK_SUM_EN_V  0x00000001U
+#define UHCI_CHECK_SUM_EN_S  0
+/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to  enable sequence number check when receiving.
+ */
+#define UHCI_CHECK_SEQ_EN    (BIT(1))
+#define UHCI_CHECK_SEQ_EN_M  (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S)
+#define UHCI_CHECK_SEQ_EN_V  0x00000001U
+#define UHCI_CHECK_SEQ_EN_S  1
+/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to support CRC calculation, and data integrity check bit should 1.
+ */
+#define UHCI_CRC_DISABLE    (BIT(2))
+#define UHCI_CRC_DISABLE_M  (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S)
+#define UHCI_CRC_DISABLE_V  0x00000001U
+#define UHCI_CRC_DISABLE_S  2
+/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to save data packet head when UHCI receive data.
+ */
+#define UHCI_SAVE_HEAD    (BIT(3))
+#define UHCI_SAVE_HEAD_M  (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S)
+#define UHCI_SAVE_HEAD_V  0x00000001U
+#define UHCI_SAVE_HEAD_S  3
+/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to encode data packet with checksum.
+ */
+#define UHCI_TX_CHECK_SUM_RE    (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_M  (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S)
+#define UHCI_TX_CHECK_SUM_RE_V  0x00000001U
+#define UHCI_TX_CHECK_SUM_RE_S  4
+/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1;
+ *  Set this bit to encode data packet with ACK when reliable data packet is ready.
+ */
+#define UHCI_TX_ACK_NUM_RE    (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_M  (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S)
+#define UHCI_TX_ACK_NUM_RE_V  0x00000001U
+#define UHCI_TX_ACK_NUM_RE_S  5
+/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
+ */
+#define UHCI_WAIT_SW_START    (BIT(7))
+#define UHCI_WAIT_SW_START_M  (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S)
+#define UHCI_WAIT_SW_START_V  0x00000001U
+#define UHCI_WAIT_SW_START_S  7
+/** UHCI_SW_START : WT; bitpos: [8]; default: 0;
+ *  Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.
+ */
+#define UHCI_SW_START    (BIT(8))
+#define UHCI_SW_START_M  (UHCI_SW_START_V << UHCI_SW_START_S)
+#define UHCI_SW_START_V  0x00000001U
+#define UHCI_SW_START_S  8
+
+/** UHCI_STATE0_REG register
+ *  UHCI Receive Status Register
+ */
+#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18)
+/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0;
+ *  Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet
+ *  checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC
+ *  bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is
+ *  not found, but received packet is completed. 3'b110: CRC check error.
+ */
+#define UHCI_RX_ERR_CAUSE    0x00000007U
+#define UHCI_RX_ERR_CAUSE_M  (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S)
+#define UHCI_RX_ERR_CAUSE_V  0x00000007U
+#define UHCI_RX_ERR_CAUSE_S  0
+/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0;
+ *  Indicates UHCI decoder status.
+ */
+#define UHCI_DECODE_STATE    0x00000007U
+#define UHCI_DECODE_STATE_M  (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S)
+#define UHCI_DECODE_STATE_V  0x00000007U
+#define UHCI_DECODE_STATE_S  3
+
+/** UHCI_STATE1_REG register
+ *  UHCI Transmit Status Register
+ */
+#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c)
+/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0;
+ *  Indicates UHCI encoder status.
+ */
+#define UHCI_ENCODE_STATE    0x00000007U
+#define UHCI_ENCODE_STATE_M  (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S)
+#define UHCI_ENCODE_STATE_V  0x00000007U
+#define UHCI_ENCODE_STATE_S  0
+
+/** UHCI_ESCAPE_CONF_REG register
+ *  UHCI Escapes Configuration Register0
+ */
+#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20)
+/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to enable resolve char 0xC0 when DMA receiving data.
+ */
+#define UHCI_TX_C0_ESC_EN    (BIT(0))
+#define UHCI_TX_C0_ESC_EN_M  (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S)
+#define UHCI_TX_C0_ESC_EN_V  0x00000001U
+#define UHCI_TX_C0_ESC_EN_S  0
+/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to enable resolve char 0xDB when DMA receiving data.
+ */
+#define UHCI_TX_DB_ESC_EN    (BIT(1))
+#define UHCI_TX_DB_ESC_EN_M  (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S)
+#define UHCI_TX_DB_ESC_EN_V  0x00000001U
+#define UHCI_TX_DB_ESC_EN_S  1
+/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable resolve flow control char 0x11 when DMA receiving data.
+ */
+#define UHCI_TX_11_ESC_EN    (BIT(2))
+#define UHCI_TX_11_ESC_EN_M  (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S)
+#define UHCI_TX_11_ESC_EN_V  0x00000001U
+#define UHCI_TX_11_ESC_EN_S  2
+/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable resolve flow control char 0x13 when DMA receiving data.
+ */
+#define UHCI_TX_13_ESC_EN    (BIT(3))
+#define UHCI_TX_13_ESC_EN_M  (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S)
+#define UHCI_TX_13_ESC_EN_V  0x00000001U
+#define UHCI_TX_13_ESC_EN_S  3
+/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to enable replacing 0xC0 with special char when DMA receiving data.
+ */
+#define UHCI_RX_C0_ESC_EN    (BIT(4))
+#define UHCI_RX_C0_ESC_EN_M  (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S)
+#define UHCI_RX_C0_ESC_EN_V  0x00000001U
+#define UHCI_RX_C0_ESC_EN_S  4
+/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1;
+ *  Set this bit to enable replacing 0xDB with special char when DMA receiving data.
+ */
+#define UHCI_RX_DB_ESC_EN    (BIT(5))
+#define UHCI_RX_DB_ESC_EN_M  (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S)
+#define UHCI_RX_DB_ESC_EN_V  0x00000001U
+#define UHCI_RX_DB_ESC_EN_S  5
+/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable replacing 0x11 with special char when DMA receiving data.
+ */
+#define UHCI_RX_11_ESC_EN    (BIT(6))
+#define UHCI_RX_11_ESC_EN_M  (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S)
+#define UHCI_RX_11_ESC_EN_V  0x00000001U
+#define UHCI_RX_11_ESC_EN_S  6
+/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable replacing 0x13 with special char when DMA receiving data.
+ */
+#define UHCI_RX_13_ESC_EN    (BIT(7))
+#define UHCI_RX_13_ESC_EN_M  (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S)
+#define UHCI_RX_13_ESC_EN_V  0x00000001U
+#define UHCI_RX_13_ESC_EN_S  7
+
+/** UHCI_HUNG_CONF_REG register
+ *  UHCI Hung Configuration Register0
+ */
+#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24)
+/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving
+ *  data.
+ */
+#define UHCI_TXFIFO_TIMEOUT    0x000000FFU
+#define UHCI_TXFIFO_TIMEOUT_M  (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S)
+#define UHCI_TXFIFO_TIMEOUT_V  0x000000FFU
+#define UHCI_TXFIFO_TIMEOUT_S  0
+/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  Configures the maximum counter value.
+ */
+#define UHCI_TXFIFO_TIMEOUT_SHIFT    0x00000007U
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S)
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
+/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  Set this bit to enable TX FIFO timeout when receiving.
+ */
+#define UHCI_TXFIFO_TIMEOUT_ENA    (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_M  (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S)
+#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x00000001U
+#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
+/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16;
+ *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading
+ *  RAM data.
+ */
+#define UHCI_RXFIFO_TIMEOUT    0x000000FFU
+#define UHCI_RXFIFO_TIMEOUT_M  (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S)
+#define UHCI_RXFIFO_TIMEOUT_V  0x000000FFU
+#define UHCI_RXFIFO_TIMEOUT_S  12
+/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0;
+ *  Configures the maximum counter value.
+ */
+#define UHCI_RXFIFO_TIMEOUT_SHIFT    0x00000007U
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S)
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
+/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1;
+ *  Set this bit to enable TX FIFO timeout when DMA sending data.
+ */
+#define UHCI_RXFIFO_TIMEOUT_ENA    (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_M  (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S)
+#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x00000001U
+#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
+
+/** UHCI_ACK_NUM_REG register
+ *  UHCI Ack Value Configuration Register0
+ */
+#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28)
+/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0;
+ *  Indicates the ACK number during software flow control.
+ */
+#define UHCI_ACK_NUM    0x00000007U
+#define UHCI_ACK_NUM_M  (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S)
+#define UHCI_ACK_NUM_V  0x00000007U
+#define UHCI_ACK_NUM_S  0
+/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0;
+ *  Set this bit to load the ACK value of UHCI_ACK_NUM.
+ */
+#define UHCI_ACK_NUM_LOAD    (BIT(3))
+#define UHCI_ACK_NUM_LOAD_M  (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S)
+#define UHCI_ACK_NUM_LOAD_V  0x00000001U
+#define UHCI_ACK_NUM_LOAD_S  3
+
+/** UHCI_RX_HEAD_REG register
+ *  UHCI Head Register
+ */
+#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c)
+/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0;
+ *  Stores the head of received packet.
+ */
+#define UHCI_RX_HEAD    0xFFFFFFFFU
+#define UHCI_RX_HEAD_M  (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S)
+#define UHCI_RX_HEAD_V  0xFFFFFFFFU
+#define UHCI_RX_HEAD_S  0
+
+/** UHCI_QUICK_SENT_REG register
+ *  UCHI Quick send Register
+ */
+#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30)
+/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0;
+ *  Configures single_send mode.
+ */
+#define UHCI_SINGLE_SEND_NUM    0x00000007U
+#define UHCI_SINGLE_SEND_NUM_M  (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S)
+#define UHCI_SINGLE_SEND_NUM_V  0x00000007U
+#define UHCI_SINGLE_SEND_NUM_S  0
+/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0;
+ *  Set this bit to enable sending short packet with single_send mode.
+ */
+#define UHCI_SINGLE_SEND_EN    (BIT(3))
+#define UHCI_SINGLE_SEND_EN_M  (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S)
+#define UHCI_SINGLE_SEND_EN_V  0x00000001U
+#define UHCI_SINGLE_SEND_EN_S  3
+/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0;
+ *  Configures always_send mode.
+ */
+#define UHCI_ALWAYS_SEND_NUM    0x00000007U
+#define UHCI_ALWAYS_SEND_NUM_M  (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S)
+#define UHCI_ALWAYS_SEND_NUM_V  0x00000007U
+#define UHCI_ALWAYS_SEND_NUM_S  4
+/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable sending short packet with always_send mode.
+ */
+#define UHCI_ALWAYS_SEND_EN    (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_M  (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S)
+#define UHCI_ALWAYS_SEND_EN_V  0x00000001U
+#define UHCI_ALWAYS_SEND_EN_S  7
+
+/** UHCI_REG_Q0_WORD0_REG register
+ *  UHCI Q0_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34)
+/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q0_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD0_M  (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S)
+#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD0_S  0
+
+/** UHCI_REG_Q0_WORD1_REG register
+ *  UHCI Q0_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38)
+/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q0_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD1_M  (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S)
+#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD1_S  0
+
+/** UHCI_REG_Q1_WORD0_REG register
+ *  UHCI Q1_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c)
+/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q1_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD0_M  (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S)
+#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD0_S  0
+
+/** UHCI_REG_Q1_WORD1_REG register
+ *  UHCI Q1_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40)
+/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q1_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD1_M  (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S)
+#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD1_S  0
+
+/** UHCI_REG_Q2_WORD0_REG register
+ *  UHCI Q2_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44)
+/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q2_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD0_M  (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S)
+#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD0_S  0
+
+/** UHCI_REG_Q2_WORD1_REG register
+ *  UHCI Q2_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48)
+/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q2_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD1_M  (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S)
+#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD1_S  0
+
+/** UHCI_REG_Q3_WORD0_REG register
+ *  UHCI Q3_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c)
+/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q3_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD0_M  (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S)
+#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD0_S  0
+
+/** UHCI_REG_Q3_WORD1_REG register
+ *  UHCI Q3_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50)
+/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q3_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD1_M  (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S)
+#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD1_S  0
+
+/** UHCI_REG_Q4_WORD0_REG register
+ *  UHCI Q4_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54)
+/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q4_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD0_M  (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S)
+#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD0_S  0
+
+/** UHCI_REG_Q4_WORD1_REG register
+ *  UHCI Q4_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58)
+/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q4_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD1_M  (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S)
+#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD1_S  0
+
+/** UHCI_REG_Q5_WORD0_REG register
+ *  UHCI Q5_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c)
+/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q5_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD0_M  (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S)
+#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD0_S  0
+
+/** UHCI_REG_Q5_WORD1_REG register
+ *  UHCI Q5_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60)
+/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q5_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD1_M  (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S)
+#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD1_S  0
+
+/** UHCI_REG_Q6_WORD0_REG register
+ *  UHCI Q6_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64)
+/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q6_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD0_M  (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S)
+#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD0_S  0
+
+/** UHCI_REG_Q6_WORD1_REG register
+ *  UHCI Q6_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68)
+/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q6_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD1_M  (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S)
+#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD1_S  0
+
+/** UHCI_ESC_CONF0_REG register
+ *  UHCI Escapes Sequence Configuration Register0
+ */
+#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c)
+/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192;
+ *  Configures the delimiter for encoding, default value is 0xC0.
+ */
+#define UHCI_SEPER_CHAR    0x000000FFU
+#define UHCI_SEPER_CHAR_M  (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S)
+#define UHCI_SEPER_CHAR_V  0x000000FFU
+#define UHCI_SEPER_CHAR_S  0
+/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_SEPER_ESC_CHAR0    0x000000FFU
+#define UHCI_SEPER_ESC_CHAR0_M  (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S)
+#define UHCI_SEPER_ESC_CHAR0_V  0x000000FFU
+#define UHCI_SEPER_ESC_CHAR0_S  8
+/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220;
+ *  Configures the second char of SLIP escape character, default value is 0xDC.
+ */
+#define UHCI_SEPER_ESC_CHAR1    0x000000FFU
+#define UHCI_SEPER_ESC_CHAR1_M  (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S)
+#define UHCI_SEPER_ESC_CHAR1_V  0x000000FFU
+#define UHCI_SEPER_ESC_CHAR1_S  16
+
+/** UHCI_ESC_CONF1_REG register
+ *  UHCI Escapes Sequence Configuration Register1
+ */
+#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70)
+/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219;
+ *  Configures the char needing encoding, which is 0xDB as flow control char by default.
+ */
+#define UHCI_ESC_SEQ0    0x000000FFU
+#define UHCI_ESC_SEQ0_M  (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S)
+#define UHCI_ESC_SEQ0_V  0x000000FFU
+#define UHCI_ESC_SEQ0_S  0
+/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_ESC_SEQ0_CHAR0    0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR0_M  (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S)
+#define UHCI_ESC_SEQ0_CHAR0_V  0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR0_S  8
+/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221;
+ *  Configures the second char of SLIP escape character, default value is 0xDD.
+ */
+#define UHCI_ESC_SEQ0_CHAR1    0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR1_M  (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S)
+#define UHCI_ESC_SEQ0_CHAR1_V  0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR1_S  16
+
+/** UHCI_ESC_CONF2_REG register
+ *  UHCI Escapes Sequence Configuration Register2
+ */
+#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74)
+/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17;
+ *  Configures the char needing encoding, which is 0x11 as flow control char by default.
+ */
+#define UHCI_ESC_SEQ1    0x000000FFU
+#define UHCI_ESC_SEQ1_M  (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S)
+#define UHCI_ESC_SEQ1_V  0x000000FFU
+#define UHCI_ESC_SEQ1_S  0
+/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_ESC_SEQ1_CHAR0    0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR0_M  (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S)
+#define UHCI_ESC_SEQ1_CHAR0_V  0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR0_S  8
+/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222;
+ *  Configures the second char of SLIP escape character, default value is 0xDE.
+ */
+#define UHCI_ESC_SEQ1_CHAR1    0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR1_M  (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S)
+#define UHCI_ESC_SEQ1_CHAR1_V  0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR1_S  16
+
+/** UHCI_ESC_CONF3_REG register
+ *  UHCI Escapes Sequence Configuration Register3
+ */
+#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78)
+/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19;
+ *  Configures the char needing encoding, which is 0x13 as flow control char by default.
+ */
+#define UHCI_ESC_SEQ2    0x000000FFU
+#define UHCI_ESC_SEQ2_M  (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S)
+#define UHCI_ESC_SEQ2_V  0x000000FFU
+#define UHCI_ESC_SEQ2_S  0
+/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_ESC_SEQ2_CHAR0    0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR0_M  (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S)
+#define UHCI_ESC_SEQ2_CHAR0_V  0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR0_S  8
+/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223;
+ *  Configures the second char of SLIP escape character, default value is 0xDF.
+ */
+#define UHCI_ESC_SEQ2_CHAR1    0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR1_M  (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S)
+#define UHCI_ESC_SEQ2_CHAR1_V  0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR1_S  16
+
+/** UHCI_PKT_THRES_REG register
+ *  UCHI Packet Length Configuration Register
+ */
+#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c)
+/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128;
+ *  Configures the data packet's maximum length when UHCI_HEAD_EN is 0.
+ */
+#define UHCI_PKT_THRS    0x00001FFFU
+#define UHCI_PKT_THRS_M  (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S)
+#define UHCI_PKT_THRS_V  0x00001FFFU
+#define UHCI_PKT_THRS_S  0
+
+/** UHCI_DATE_REG register
+ *  UHCI Version Register
+ */
+#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80)
+/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936;
+ *  Configures version.
+ */
+#define UHCI_DATE    0xFFFFFFFFU
+#define UHCI_DATE_M  (UHCI_DATE_V << UHCI_DATE_S)
+#define UHCI_DATE_V  0xFFFFFFFFU
+#define UHCI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uhci_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/uhci_struct.h
new file mode 100644
index 0000000000..b8328eecfa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/uhci_struct.h
@@ -0,0 +1,844 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of conf0 register
+ *  UHCI Configuration Register0
+ */
+typedef union {
+    struct {
+        /** tx_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0 to this bit to reset decode state machine.
+         */
+        uint32_t tx_rst:1;
+        /** rx_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0 to this bit to reset encode state machine.
+         */
+        uint32_t rx_rst:1;
+        /** uart_sel : R/W; bitpos: [4:2]; default: 7;
+         *  Select which uart to connect with GDMA.
+         */
+        uint32_t uart_sel:3;
+        /** seper_en : R/W; bitpos: [5]; default: 1;
+         *  Set this bit to separate the data frame using a special char.
+         */
+        uint32_t seper_en:1;
+        /** head_en : R/W; bitpos: [6]; default: 1;
+         *  Set this bit to encode the data packet with a formatting header.
+         */
+        uint32_t head_en:1;
+        /** crc_rec_en : R/W; bitpos: [7]; default: 1;
+         *  Set this bit to enable UHCI to receive the 16 bit CRC.
+         */
+        uint32_t crc_rec_en:1;
+        /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0;
+         *  If this bit is set to 1 UHCI will end the payload receiving process when UART has
+         *  been in idle state.
+         */
+        uint32_t uart_idle_eof_en:1;
+        /** len_eof_en : R/W; bitpos: [9]; default: 1;
+         *  If this bit is set to 1 UHCI decoder receiving payload data is end when the
+         *  receiving byte count has reached the specified value. The value is payload length
+         *  indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
+         *  configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
+         *  receiving payload data is end when 0xc0 is received.
+         */
+        uint32_t len_eof_en:1;
+        /** encode_crc_en : R/W; bitpos: [10]; default: 1;
+         *  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
+         *  end of the payload.
+         */
+        uint32_t encode_crc_en:1;
+        /** clk_en : R/W; bitpos: [11]; default: 0;
+         *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0;
+         *  If this bit is set to 1 UHCI will end payload receive process when NULL frame is
+         *  received by UART.
+         */
+        uint32_t uart_rx_brk_eof_en:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} uhci_conf0_reg_t;
+
+/** Type of conf1 register
+ *  UHCI Configuration Register1
+ */
+typedef union {
+    struct {
+        /** check_sum_en : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to enable head checksum check when receiving.
+         */
+        uint32_t check_sum_en:1;
+        /** check_seq_en : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to  enable sequence number check when receiving.
+         */
+        uint32_t check_seq_en:1;
+        /** crc_disable : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to support CRC calculation, and data integrity check bit should 1.
+         */
+        uint32_t crc_disable:1;
+        /** save_head : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to save data packet head when UHCI receive data.
+         */
+        uint32_t save_head:1;
+        /** tx_check_sum_re : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to encode data packet with checksum.
+         */
+        uint32_t tx_check_sum_re:1;
+        /** tx_ack_num_re : R/W; bitpos: [5]; default: 1;
+         *  Set this bit to encode data packet with ACK when reliable data packet is ready.
+         */
+        uint32_t tx_ack_num_re:1;
+        uint32_t reserved_6:1;
+        /** wait_sw_start : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
+         */
+        uint32_t wait_sw_start:1;
+        /** sw_start : WT; bitpos: [8]; default: 0;
+         *  Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.
+         */
+        uint32_t sw_start:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_conf1_reg_t;
+
+/** Type of escape_conf register
+ *  UHCI Escapes Configuration Register0
+ */
+typedef union {
+    struct {
+        /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to enable resolve char 0xC0 when DMA receiving data.
+         */
+        uint32_t tx_c0_esc_en:1;
+        /** tx_db_esc_en : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to enable resolve char 0xDB when DMA receiving data.
+         */
+        uint32_t tx_db_esc_en:1;
+        /** tx_11_esc_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable resolve flow control char 0x11 when DMA receiving data.
+         */
+        uint32_t tx_11_esc_en:1;
+        /** tx_13_esc_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable resolve flow control char 0x13 when DMA receiving data.
+         */
+        uint32_t tx_13_esc_en:1;
+        /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to enable replacing 0xC0 with special char when DMA receiving data.
+         */
+        uint32_t rx_c0_esc_en:1;
+        /** rx_db_esc_en : R/W; bitpos: [5]; default: 1;
+         *  Set this bit to enable replacing 0xDB with special char when DMA receiving data.
+         */
+        uint32_t rx_db_esc_en:1;
+        /** rx_11_esc_en : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable replacing 0x11 with special char when DMA receiving data.
+         */
+        uint32_t rx_11_esc_en:1;
+        /** rx_13_esc_en : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable replacing 0x13 with special char when DMA receiving data.
+         */
+        uint32_t rx_13_esc_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uhci_escape_conf_reg_t;
+
+/** Type of hung_conf register
+ *  UHCI Hung Configuration Register0
+ */
+typedef union {
+    struct {
+        /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving
+         *  data.
+         */
+        uint32_t txfifo_timeout:8;
+        /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  Configures the maximum counter value.
+         */
+        uint32_t txfifo_timeout_shift:3;
+        /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  Set this bit to enable TX FIFO timeout when receiving.
+         */
+        uint32_t txfifo_timeout_ena:1;
+        /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16;
+         *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading
+         *  RAM data.
+         */
+        uint32_t rxfifo_timeout:8;
+        /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0;
+         *  Configures the maximum counter value.
+         */
+        uint32_t rxfifo_timeout_shift:3;
+        /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1;
+         *  Set this bit to enable TX FIFO timeout when DMA sending data.
+         */
+        uint32_t rxfifo_timeout_ena:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_hung_conf_reg_t;
+
+/** Type of ack_num register
+ *  UHCI Ack Value Configuration Register0
+ */
+typedef union {
+    struct {
+        /** ack_num : R/W; bitpos: [2:0]; default: 0;
+         *  Indicates the ACK number during software flow control.
+         */
+        uint32_t ack_num:3;
+        /** ack_num_load : WT; bitpos: [3]; default: 0;
+         *  Set this bit to load the ACK value of UHCI_ACK_NUM.
+         */
+        uint32_t ack_num_load:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uhci_ack_num_reg_t;
+
+/** Type of quick_sent register
+ *  UCHI Quick send Register
+ */
+typedef union {
+    struct {
+        /** single_send_num : R/W; bitpos: [2:0]; default: 0;
+         *  Configures single_send mode.
+         */
+        uint32_t single_send_num:3;
+        /** single_send_en : WT; bitpos: [3]; default: 0;
+         *  Set this bit to enable sending short packet with single_send mode.
+         */
+        uint32_t single_send_en:1;
+        /** always_send_num : R/W; bitpos: [6:4]; default: 0;
+         *  Configures always_send mode.
+         */
+        uint32_t always_send_num:3;
+        /** always_send_en : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable sending short packet with always_send mode.
+         */
+        uint32_t always_send_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uhci_quick_sent_reg_t;
+
+/** Type of reg_q0_word0 register
+ *  UHCI Q0_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q0_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q0_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q0_word0_reg_t;
+
+/** Type of reg_q0_word1 register
+ *  UHCI Q0_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q0_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q0_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q0_word1_reg_t;
+
+/** Type of reg_q1_word0 register
+ *  UHCI Q1_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q1_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q1_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q1_word0_reg_t;
+
+/** Type of reg_q1_word1 register
+ *  UHCI Q1_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q1_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q1_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q1_word1_reg_t;
+
+/** Type of reg_q2_word0 register
+ *  UHCI Q2_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q2_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q2_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q2_word0_reg_t;
+
+/** Type of reg_q2_word1 register
+ *  UHCI Q2_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q2_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q2_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q2_word1_reg_t;
+
+/** Type of reg_q3_word0 register
+ *  UHCI Q3_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q3_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q3_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q3_word0_reg_t;
+
+/** Type of reg_q3_word1 register
+ *  UHCI Q3_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q3_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q3_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q3_word1_reg_t;
+
+/** Type of reg_q4_word0 register
+ *  UHCI Q4_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q4_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q4_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q4_word0_reg_t;
+
+/** Type of reg_q4_word1 register
+ *  UHCI Q4_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q4_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q4_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q4_word1_reg_t;
+
+/** Type of reg_q5_word0 register
+ *  UHCI Q5_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q5_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q5_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q5_word0_reg_t;
+
+/** Type of reg_q5_word1 register
+ *  UHCI Q5_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q5_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q5_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q5_word1_reg_t;
+
+/** Type of reg_q6_word0 register
+ *  UHCI Q6_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q6_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q6_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q6_word0_reg_t;
+
+/** Type of reg_q6_word1 register
+ *  UHCI Q6_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q6_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q6_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q6_word1_reg_t;
+
+/** Type of esc_conf0 register
+ *  UHCI Escapes Sequence Configuration Register0
+ */
+typedef union {
+    struct {
+        /** seper_char : R/W; bitpos: [7:0]; default: 192;
+         *  Configures the delimiter for encoding, default value is 0xC0.
+         */
+        uint32_t seper_char:8;
+        /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t seper_esc_char0:8;
+        /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220;
+         *  Configures the second char of SLIP escape character, default value is 0xDC.
+         */
+        uint32_t seper_esc_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf0_reg_t;
+
+/** Type of esc_conf1 register
+ *  UHCI Escapes Sequence Configuration Register1
+ */
+typedef union {
+    struct {
+        /** esc_seq0 : R/W; bitpos: [7:0]; default: 219;
+         *  Configures the char needing encoding, which is 0xDB as flow control char by default.
+         */
+        uint32_t esc_seq0:8;
+        /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t esc_seq0_char0:8;
+        /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221;
+         *  Configures the second char of SLIP escape character, default value is 0xDD.
+         */
+        uint32_t esc_seq0_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf1_reg_t;
+
+/** Type of esc_conf2 register
+ *  UHCI Escapes Sequence Configuration Register2
+ */
+typedef union {
+    struct {
+        /** esc_seq1 : R/W; bitpos: [7:0]; default: 17;
+         *  Configures the char needing encoding, which is 0x11 as flow control char by default.
+         */
+        uint32_t esc_seq1:8;
+        /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t esc_seq1_char0:8;
+        /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222;
+         *  Configures the second char of SLIP escape character, default value is 0xDE.
+         */
+        uint32_t esc_seq1_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf2_reg_t;
+
+/** Type of esc_conf3 register
+ *  UHCI Escapes Sequence Configuration Register3
+ */
+typedef union {
+    struct {
+        /** esc_seq2 : R/W; bitpos: [7:0]; default: 19;
+         *  Configures the char needing encoding, which is 0x13 as flow control char by default.
+         */
+        uint32_t esc_seq2:8;
+        /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t esc_seq2_char0:8;
+        /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223;
+         *  Configures the second char of SLIP escape character, default value is 0xDF.
+         */
+        uint32_t esc_seq2_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf3_reg_t;
+
+/** Type of pkt_thres register
+ *  UCHI Packet Length Configuration Register
+ */
+typedef union {
+    struct {
+        /** pkt_thrs : R/W; bitpos: [12:0]; default: 128;
+         *  Configures the data packet's maximum length when UHCI_HEAD_EN is 0.
+         */
+        uint32_t pkt_thrs:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} uhci_pkt_thres_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  UHCI Interrupt Raw Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when
+         *  delimiter is sent successfully.
+         */
+        uint32_t rx_start_int_raw:1;
+        /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when
+         *  DMA detects delimiter.
+         */
+        uint32_t tx_start_int_raw:1;
+        /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when
+         *  the required time of DMA receiving data  exceeds the configuration value.
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when
+         *  the required time of DMA reading RAM data  exceeds the configuration value.
+         */
+        uint32_t tx_hung_int_raw:1;
+        /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered
+         *  when UHCI sends short packet successfully with single_send mode.
+         */
+        uint32_t send_s_reg_q_int_raw:1;
+        /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered
+         *  when UHCI sends short packet successfully with always_send mode.
+         */
+        uint32_t send_a_reg_q_int_raw:1;
+        /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when
+         *  there are errors in EOF.
+         */
+        uint32_t out_eof_int_raw:1;
+        /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0;
+         *  Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when
+         *  UHCI_APP_CTRL0_IN_SET is set to 1.
+         */
+        uint32_t app_ctrl0_int_raw:1;
+        /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0;
+         *  Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when
+         *  UHCI_APP_CTRL1_IN_SET is set to 1.
+         */
+        uint32_t app_ctrl1_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_raw_reg_t;
+
+/** Type of int_st register
+ *  UHCI Interrupt Status Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_st : RO; bitpos: [0]; default: 0;
+         *  Indicates the interrupt status of UHCI_RX_START_INT.
+         */
+        uint32_t rx_start_int_st:1;
+        /** tx_start_int_st : RO; bitpos: [1]; default: 0;
+         *  Indicates the interrupt status of UHCI_TX_START_INT.
+         */
+        uint32_t tx_start_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  Indicates the interrupt status of UHCI_RX_HUNG_INT.
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  Indicates the interrupt status of UHCI_TX_HUNG_INT.
+         */
+        uint32_t tx_hung_int_st:1;
+        /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0;
+         *  Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.
+         */
+        uint32_t send_s_reg_q_int_st:1;
+        /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0;
+         *  Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.
+         */
+        uint32_t send_a_reg_q_int_st:1;
+        /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0;
+         *  Indicates the interrupt status of UHCI_OUT_EOF_INT.
+         */
+        uint32_t outlink_eof_err_int_st:1;
+        /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0;
+         *  Indicates the interrupt status of UHCI_APP_CTRL0_INT.
+         */
+        uint32_t app_ctrl0_int_st:1;
+        /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0;
+         *  Indicates the interrupt status of UHCI_APP_CTRL1_INT.
+         */
+        uint32_t app_ctrl1_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_st_reg_t;
+
+/** Type of int_ena register
+ *  UHCI Interrupt Enable Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_RX_START_INT.
+         */
+        uint32_t rx_start_int_ena:1;
+        /** tx_start_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_TX_START_INT.
+         */
+        uint32_t tx_start_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.
+         */
+        uint32_t tx_hung_int_ena:1;
+        /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.
+         */
+        uint32_t send_s_reg_q_int_ena:1;
+        /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.
+         */
+        uint32_t send_a_reg_q_int_ena:1;
+        /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.
+         */
+        uint32_t outlink_eof_err_int_ena:1;
+        /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.
+         */
+        uint32_t app_ctrl0_int_ena:1;
+        /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.
+         */
+        uint32_t app_ctrl1_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  UHCI Interrupt Clear Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_RX_START_INT.
+         */
+        uint32_t rx_start_int_clr:1;
+        /** tx_start_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_TX_START_INT.
+         */
+        uint32_t tx_start_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.
+         */
+        uint32_t tx_hung_int_clr:1;
+        /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.
+         */
+        uint32_t send_s_reg_q_int_clr:1;
+        /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.
+         */
+        uint32_t send_a_reg_q_int_clr:1;
+        /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.
+         */
+        uint32_t outlink_eof_err_int_clr:1;
+        /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.
+         */
+        uint32_t app_ctrl0_int_clr:1;
+        /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.
+         */
+        uint32_t app_ctrl1_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_clr_reg_t;
+
+
+/** Group: UHCI Status Register */
+/** Type of state0 register
+ *  UHCI Receive Status Register
+ */
+typedef union {
+    struct {
+        /** rx_err_cause : RO; bitpos: [2:0]; default: 0;
+         *  Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet
+         *  checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC
+         *  bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is
+         *  not found, but received packet is completed. 3'b110: CRC check error.
+         */
+        uint32_t rx_err_cause:3;
+        /** decode_state : RO; bitpos: [5:3]; default: 0;
+         *  Indicates UHCI decoder status.
+         */
+        uint32_t decode_state:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} uhci_state0_reg_t;
+
+/** Type of state1 register
+ *  UHCI Transmit Status Register
+ */
+typedef union {
+    struct {
+        /** encode_state : RO; bitpos: [2:0]; default: 0;
+         *  Indicates UHCI encoder status.
+         */
+        uint32_t encode_state:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} uhci_state1_reg_t;
+
+/** Type of rx_head register
+ *  UHCI Head Register
+ */
+typedef union {
+    struct {
+        /** rx_head : RO; bitpos: [31:0]; default: 0;
+         *  Stores the head of received packet.
+         */
+        uint32_t rx_head:32;
+    };
+    uint32_t val;
+} uhci_rx_head_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UHCI Version Register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35655936;
+         *  Configures version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uhci_date_reg_t;
+
+
+typedef struct uhci_dev_t {
+    volatile uhci_conf0_reg_t conf0;
+    volatile uhci_int_raw_reg_t int_raw;
+    volatile uhci_int_st_reg_t int_st;
+    volatile uhci_int_ena_reg_t int_ena;
+    volatile uhci_int_clr_reg_t int_clr;
+    volatile uhci_conf1_reg_t conf1;
+    volatile uhci_state0_reg_t state0;
+    volatile uhci_state1_reg_t state1;
+    volatile uhci_escape_conf_reg_t escape_conf;
+    volatile uhci_hung_conf_reg_t hung_conf;
+    volatile uhci_ack_num_reg_t ack_num;
+    volatile uhci_rx_head_reg_t rx_head;
+    volatile uhci_quick_sent_reg_t quick_sent;
+    volatile uhci_reg_q0_word0_reg_t reg_q0_word0;
+    volatile uhci_reg_q0_word1_reg_t reg_q0_word1;
+    volatile uhci_reg_q1_word0_reg_t reg_q1_word0;
+    volatile uhci_reg_q1_word1_reg_t reg_q1_word1;
+    volatile uhci_reg_q2_word0_reg_t reg_q2_word0;
+    volatile uhci_reg_q2_word1_reg_t reg_q2_word1;
+    volatile uhci_reg_q3_word0_reg_t reg_q3_word0;
+    volatile uhci_reg_q3_word1_reg_t reg_q3_word1;
+    volatile uhci_reg_q4_word0_reg_t reg_q4_word0;
+    volatile uhci_reg_q4_word1_reg_t reg_q4_word1;
+    volatile uhci_reg_q5_word0_reg_t reg_q5_word0;
+    volatile uhci_reg_q5_word1_reg_t reg_q5_word1;
+    volatile uhci_reg_q6_word0_reg_t reg_q6_word0;
+    volatile uhci_reg_q6_word1_reg_t reg_q6_word1;
+    volatile uhci_esc_conf0_reg_t esc_conf0;
+    volatile uhci_esc_conf1_reg_t esc_conf1;
+    volatile uhci_esc_conf2_reg_t esc_conf2;
+    volatile uhci_esc_conf3_reg_t esc_conf3;
+    volatile uhci_pkt_thres_reg_t pkt_thres;
+    volatile uhci_date_reg_t date;
+} uhci_dev_t;
+
+extern uhci_dev_t UHCI0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h
new file mode 100644
index 0000000000..95ce3b2fe2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h
@@ -0,0 +1,1286 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_DEVICE_EP1_REG register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+#define USB_DEVICE_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0)
+/** USB_DEVICE_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+ *  USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
+ *  into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check
+ *  USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
+ *  received, then read data from UART Rx FIFO.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_M  (USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_V << USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_S  0
+
+/** USB_DEVICE_EP1_CONF_REG register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4)
+/** USB_DEVICE_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ */
+#define USB_DEVICE_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_WR_DONE_M  (USB_DEVICE_SERIAL_JTAG_WR_DONE_V << USB_DEVICE_SERIAL_JTAG_WR_DONE_S)
+#define USB_DEVICE_SERIAL_JTAG_WR_DONE_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_WR_DONE_S  0
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+ *  USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB
+ *  Host.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ *  1'b1: Indicate there is data in UART Rx FIFO.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+
+/** USB_DEVICE_INT_RAW_REG register
+ *  Interrupt raw status register.
+ */
+#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8)
+/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when flush cmd is received for IN
+ *  endpoint 2 of JTAG.
+ */
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+/** USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when SOF frame is received.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_S  1
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2];
+ *  default: 0;
+ *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+ *  one packet.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when pid error is detected.
+ */
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC5 error is detected.
+ */
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC16 error is detected.
+ */
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when stuff error is detected.
+ */
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8];
+ *  default: 0;
+ *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+ *  received.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when usb bus reset is detected.
+ */
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10];
+ *  default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+ *  zero palyload.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11];
+ *  default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+ *  zero palyload.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+ *  is changed.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
+/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+ *  is changed.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
+/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+ *  received.
+ */
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
+/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+ *  received.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
+
+/** USB_DEVICE_INT_ST_REG register
+ *  Interrupt status register.
+ */
+#define USB_DEVICE_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc)
+/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+/** USB_DEVICE_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_S  1
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
+/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
+/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
+/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
+
+/** USB_DEVICE_INT_ENA_REG register
+ *  Interrupt enable status register.
+ */
+#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10)
+/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+/** USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_S  1
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
+/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
+/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
+/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
+
+/** USB_DEVICE_INT_CLR_REG register
+ *  Interrupt clear status register.
+ */
+#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14)
+/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+/** USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_S  1
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
+/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
+/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
+/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
+
+/** USB_DEVICE_CONF0_REG register
+ *  PHY hardware configuration.
+ */
+#define USB_DEVICE_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18)
+/** USB_DEVICE_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  Select internal/external PHY
+ */
+#define USB_DEVICE_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_M  (USB_DEVICE_SERIAL_JTAG_PHY_SEL_V << USB_DEVICE_SERIAL_JTAG_PHY_SEL_S)
+#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_S  0
+/** USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ *  Enable software control USB D+ D- exchange
+ */
+#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/** USB_DEVICE_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ *  USB D+ D- exchange
+ */
+#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_M  (USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_V << USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_S  2
+/** USB_DEVICE_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV
+ */
+#define USB_DEVICE_SERIAL_JTAG_VREFH    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_VREFH_M  (USB_DEVICE_SERIAL_JTAG_VREFH_V << USB_DEVICE_SERIAL_JTAG_VREFH_S)
+#define USB_DEVICE_SERIAL_JTAG_VREFH_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_VREFH_S  3
+/** USB_DEVICE_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+ */
+#define USB_DEVICE_SERIAL_JTAG_VREFL    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_VREFL_M  (USB_DEVICE_SERIAL_JTAG_VREFL_V << USB_DEVICE_SERIAL_JTAG_VREFL_S)
+#define USB_DEVICE_SERIAL_JTAG_VREFL_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_VREFL_S  5
+/** USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ *  Enable software control input  threshold
+ */
+#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/** USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ *  Enable software control USB D+ D- pullup pulldown
+ */
+#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/** USB_DEVICE_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ *  Control USB D+ pull up.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_M  (USB_DEVICE_SERIAL_JTAG_DP_PULLUP_V << USB_DEVICE_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_S  9
+/** USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ *  Control USB D+ pull down.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_M  (USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_V << USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_S  10
+/** USB_DEVICE_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ *  Control USB D- pull up.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_M  (USB_DEVICE_SERIAL_JTAG_DM_PULLUP_V << USB_DEVICE_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_S  11
+/** USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ *  Control USB D- pull down.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_M  (USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_V << USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_S  12
+/** USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ *  Control pull up value.
+ */
+#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_M  (USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_V << USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_S  13
+/** USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ *  Enable USB pad function.
+ */
+#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+/** USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
+ *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+ *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+ *  through GPIO Matrix.
+ */
+#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
+#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
+#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
+
+/** USB_DEVICE_TEST_REG register
+ *  Registers used for debugging the PHY.
+ */
+#define USB_DEVICE_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c)
+/** USB_DEVICE_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Enable test of the USB pad
+ */
+#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_M  (USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_V << USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_S  0
+/** USB_DEVICE_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ *  USB pad oen in test
+ */
+#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_M  (USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_V << USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_S  1
+/** USB_DEVICE_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ *  USB D+ tx value in test
+ */
+#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_M  (USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_V << USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_S  2
+/** USB_DEVICE_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ *  USB D- tx value in test
+ */
+#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_M  (USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_V << USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_S  3
+/** USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
+ *  USB RCV value in test
+ */
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_M  (USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_S)
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_S  4
+/** USB_DEVICE_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
+ *  USB D+ rx value in test
+ */
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_M  (USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_S)
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_S  5
+/** USB_DEVICE_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
+ *  USB D- rx value in test
+ */
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_M  (USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_S)
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_S  6
+
+/** USB_DEVICE_JFIFO_ST_REG register
+ *  JTAG FIFO status and control registers.
+ */
+#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20)
+/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
+ *  JTAT in fifo counter.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_S  0
+/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  1: JTAG in fifo is empty.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  1: JTAG in fifo is full.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
+ *  JTAT out fifo counter.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ *  1: JTAG out fifo is empty.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ *  1: JTAG out fifo is full.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to reset JTAG in fifo.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to reset JTAG out fifo.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+
+/** USB_DEVICE_FRAM_NUM_REG register
+ *  Last received SOF frame index register.
+ */
+#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24)
+/** USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
+ *  Frame index of received SOF frame.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
+#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
+#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+/** USB_DEVICE_IN_EP0_ST_REG register
+ *  Control IN endpoint status information.
+ */
+#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28)
+/** USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 0.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_M  (USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_S  0
+/** USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 0.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/** USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 0.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+
+/** USB_DEVICE_IN_EP1_ST_REG register
+ *  CDC-ACM IN endpoint status information.
+ */
+#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c)
+/** USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 1.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_M  (USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_S  0
+/** USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 1.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/** USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 1.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+
+/** USB_DEVICE_IN_EP2_ST_REG register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30)
+/** USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 2.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_M  (USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_S  0
+/** USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 2.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/** USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 2.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+
+/** USB_DEVICE_IN_EP3_ST_REG register
+ *  JTAG IN endpoint status information.
+ */
+#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34)
+/** USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 3.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_M  (USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_S  0
+/** USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 3.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/** USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 3.
+ */
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+
+/** USB_DEVICE_OUT_EP0_ST_REG register
+ *  Control OUT endpoint status information.
+ */
+#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38)
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 0.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_S  0
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 0.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+
+/** USB_DEVICE_OUT_EP1_ST_REG register
+ *  CDC-ACM OUT endpoint status information.
+ */
+#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c)
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 1.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_S  0
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 1.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
+ *  Data count in OUT endpoint 1 when one packet is received.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+
+/** USB_DEVICE_OUT_EP2_ST_REG register
+ *  JTAG OUT endpoint status information.
+ */
+#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40)
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 2.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_S  0
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 2.
+ */
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
+#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+
+/** USB_DEVICE_MISC_CONF_REG register
+ *  Clock enable control
+ */
+#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44)
+/** USB_DEVICE_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define USB_DEVICE_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_CLK_EN_M  (USB_DEVICE_SERIAL_JTAG_CLK_EN_V << USB_DEVICE_SERIAL_JTAG_CLK_EN_S)
+#define USB_DEVICE_SERIAL_JTAG_CLK_EN_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_CLK_EN_S  0
+
+/** USB_DEVICE_MEM_CONF_REG register
+ *  Memory power control
+ */
+#define USB_DEVICE_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48)
+/** USB_DEVICE_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  1: power down usb memory.
+ */
+#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_M  (USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_V << USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_S  0
+/** USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Force clock on for usb memory.
+ */
+#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+
+/** USB_DEVICE_CHIP_RST_REG register
+ *  CDC-ACM chip reset control.
+ */
+#define USB_DEVICE_CHIP_RST_REG (DR_REG_USB_DEVICE_BASE + 0x4c)
+/** USB_DEVICE_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
+ *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RTS    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_RTS_M  (USB_DEVICE_SERIAL_JTAG_RTS_V << USB_DEVICE_SERIAL_JTAG_RTS_S)
+#define USB_DEVICE_SERIAL_JTAG_RTS_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_RTS_S  0
+/** USB_DEVICE_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
+ *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DTR    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_DTR_M  (USB_DEVICE_SERIAL_JTAG_DTR_V << USB_DEVICE_SERIAL_JTAG_DTR_S)
+#define USB_DEVICE_SERIAL_JTAG_DTR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_DTR_S  1
+/** USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to disable chip reset from usb serial channel to reset chip.
+ */
+#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
+#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
+#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
+
+/** USB_DEVICE_SET_LINE_CODE_W0_REG register
+ *  W0 of SET_LINE_CODING command.
+ */
+#define USB_DEVICE_SET_LINE_CODE_W0_REG (DR_REG_USB_DEVICE_BASE + 0x50)
+/** USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by host through SET_LINE_CODING command.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_M  (USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_V << USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_S)
+#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_S  0
+
+/** USB_DEVICE_SET_LINE_CODE_W1_REG register
+ *  W1 of SET_LINE_CODING command.
+ */
+#define USB_DEVICE_SET_LINE_CODE_W1_REG (DR_REG_USB_DEVICE_BASE + 0x54)
+/** USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by host through SET_LINE_CODING command.
+ */
+#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_V << USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_S)
+#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_S  0
+/** USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by host through SET_LINE_CODING command.
+ */
+#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_M  (USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_V << USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_S)
+#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_S  8
+/** USB_DEVICE_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by host through SET_LINE_CODING command.
+ */
+#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS    0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_M  (USB_DEVICE_SERIAL_JTAG_BDATA_BITS_V << USB_DEVICE_SERIAL_JTAG_BDATA_BITS_S)
+#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_S  16
+
+/** USB_DEVICE_GET_LINE_CODE_W0_REG register
+ *  W0 of GET_LINE_CODING command.
+ */
+#define USB_DEVICE_GET_LINE_CODE_W0_REG (DR_REG_USB_DEVICE_BASE + 0x58)
+/** USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_S)
+#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
+
+/** USB_DEVICE_GET_LINE_CODE_W1_REG register
+ *  W1 of GET_LINE_CODING command.
+ */
+#define USB_DEVICE_GET_LINE_CODE_W1_REG (DR_REG_USB_DEVICE_BASE + 0x5c)
+/** USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_V << USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_S)
+#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_S  0
+/** USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_S)
+#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
+/** USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
+#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
+#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
+
+/** USB_DEVICE_CONFIG_UPDATE_REG register
+ *  Configuration registers' value update
+ */
+#define USB_DEVICE_CONFIG_UPDATE_REG (DR_REG_USB_DEVICE_BASE + 0x60)
+/** USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this register would update the value of configure registers from APB
+ *  clock domain to 48MHz clock domain.
+ */
+#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_V << USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_S)
+#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_S  0
+
+/** USB_DEVICE_SER_AFIFO_CONFIG_REG register
+ *  Serial AFIFO configure register
+ */
+#define USB_DEVICE_SER_AFIFO_CONFIG_REG (DR_REG_USB_DEVICE_BASE + 0x64)
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
+ *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
+/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
+ *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+ */
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
+
+/** USB_DEVICE_BUS_RESET_ST_REG register
+ *  USB Bus reset status register
+ */
+#define USB_DEVICE_BUS_RESET_ST_REG (DR_REG_USB_DEVICE_BASE + 0x68)
+/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
+ *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+ *  reset is released.
+ */
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_S)
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
+
+/** USB_DEVICE_ECO_LOW_48_REG register
+ *  Reserved.
+ */
+#define USB_DEVICE_ECO_LOW_48_REG (DR_REG_USB_DEVICE_BASE + 0x6c)
+/** USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48    0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_M  (USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_S)
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_V  0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_S  0
+
+/** USB_DEVICE_ECO_HIGH_48_REG register
+ *  Reserved.
+ */
+#define USB_DEVICE_ECO_HIGH_48_REG (DR_REG_USB_DEVICE_BASE + 0x70)
+/** USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Reserved.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48    0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_M  (USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_S)
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_V  0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_S  0
+
+/** USB_DEVICE_ECO_CELL_CTRL_48_REG register
+ *  Reserved.
+ */
+#define USB_DEVICE_ECO_CELL_CTRL_48_REG (DR_REG_USB_DEVICE_BASE + 0x74)
+/** USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0;
+ *  Reserved.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_M  (USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_V << USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_S)
+#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_S  0
+/** USB_DEVICE_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_M  (USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_V << USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_S)
+#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_S  1
+
+/** USB_DEVICE_ECO_LOW_APB_REG register
+ *  Reserved.
+ */
+#define USB_DEVICE_ECO_LOW_APB_REG (DR_REG_USB_DEVICE_BASE + 0x78)
+/** USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB    0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_M  (USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_S)
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_V  0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_S  0
+
+/** USB_DEVICE_ECO_HIGH_APB_REG register
+ *  Reserved.
+ */
+#define USB_DEVICE_ECO_HIGH_APB_REG (DR_REG_USB_DEVICE_BASE + 0x7c)
+/** USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Reserved.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB    0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_M  (USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_S)
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_V  0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_S  0
+
+/** USB_DEVICE_ECO_CELL_CTRL_APB_REG register
+ *  Reserved.
+ */
+#define USB_DEVICE_ECO_CELL_CTRL_APB_REG (DR_REG_USB_DEVICE_BASE + 0x80)
+/** USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0;
+ *  Reserved.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB    (BIT(0))
+#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_M  (USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_V << USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_S)
+#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_S  0
+/** USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB    (BIT(1))
+#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_M  (USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_V << USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_S)
+#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_V  0x00000001U
+#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_S  1
+
+/** USB_DEVICE_SRAM_CTRL_REG register
+ *  PPA SRAM Control Register
+ */
+#define USB_DEVICE_SRAM_CTRL_REG (DR_REG_USB_DEVICE_BASE + 0x84)
+/** USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  Control signals
+ */
+#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL    0x00003FFFU
+#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_M  (USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_S)
+#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_V  0x00003FFFU
+#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_S  0
+
+/** USB_DEVICE_DATE_REG register
+ *  Date register
+ */
+#define USB_DEVICE_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x88)
+/** USB_DEVICE_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752;
+ *  register version.
+ */
+#define USB_DEVICE_SERIAL_JTAG_DATE    0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_DATE_M  (USB_DEVICE_SERIAL_JTAG_DATE_V << USB_DEVICE_SERIAL_JTAG_DATE_S)
+#define USB_DEVICE_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
+#define USB_DEVICE_SERIAL_JTAG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_struct.h
new file mode 100644
index 0000000000..ca2ea0df15
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_struct.h
@@ -0,0 +1,1045 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of ep1 register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+typedef union {
+    struct {
+        /** rdwr_byte : RO; bitpos: [7:0]; default: 0;
+         *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+         *  usb_serial_jtag_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
+         *  into UART Tx FIFO. When usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT is set, user can check
+         *  usb_serial_jtag_OUT_EP1_WR_ADDR usb_serial_jtag_OUT_EP0_RD_ADDR to know how many data is
+         *  received, then read data from UART Rx FIFO.
+         */
+        uint32_t rdwr_byte:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} usb_serial_jtag_ep1_reg_t;
+
+/** Type of ep1_conf register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+typedef union {
+    struct {
+        /** wr_done : WT; bitpos: [0]; default: 0;
+         *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+         */
+        uint32_t wr_done:1;
+        /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
+         *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+         *  usb_serial_jtag_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB
+         *  Host.
+         */
+        uint32_t serial_in_ep_data_free:1;
+        /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
+         *  1'b1: Indicate there is data in UART Rx FIFO.
+         */
+        uint32_t serial_out_ep_data_avail:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_serial_jtag_ep1_conf_reg_t;
+
+/** Type of conf0 register
+ *  PHY hardware configuration.
+ */
+typedef union {
+    struct {
+        /** phy_sel : R/W; bitpos: [0]; default: 0;
+         *  Select internal/external PHY
+         */
+        uint32_t phy_sel:1;
+        /** exchg_pins_override : R/W; bitpos: [1]; default: 0;
+         *  Enable software control USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [2]; default: 0;
+         *  USB D+ D- exchange
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [4:3]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [6:5]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [7]; default: 0;
+         *  Enable software control input  threshold
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [8]; default: 0;
+         *  Enable software control USB D+ D- pullup pulldown
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [9]; default: 1;
+         *  Control USB D+ pull up.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [10]; default: 0;
+         *  Control USB D+ pull down.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [11]; default: 0;
+         *  Control USB D- pull up.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [12]; default: 0;
+         *  Control USB D- pull down.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [13]; default: 0;
+         *  Control pull up value.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [14]; default: 1;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
+         *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+         *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+         *  through GPIO Matrix.
+         */
+        uint32_t usb_jtag_bridge_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_conf0_reg_t;
+
+/** Type of test register
+ *  Registers used for debugging the PHY.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_test_enable : R/W; bitpos: [0]; default: 0;
+         *  Enable test of the USB pad
+         */
+        uint32_t serial_jtag_test_enable:1;
+        /** serial_jtag_test_usb_oe : R/W; bitpos: [1]; default: 0;
+         *  USB pad oen in test
+         */
+        uint32_t serial_jtag_test_usb_oe:1;
+        /** serial_jtag_test_tx_dp : R/W; bitpos: [2]; default: 0;
+         *  USB D+ tx value in test
+         */
+        uint32_t serial_jtag_test_tx_dp:1;
+        /** serial_jtag_test_tx_dm : R/W; bitpos: [3]; default: 0;
+         *  USB D- tx value in test
+         */
+        uint32_t serial_jtag_test_tx_dm:1;
+        /** serial_jtag_test_rx_rcv : RO; bitpos: [4]; default: 1;
+         *  USB RCV value in test
+         */
+        uint32_t serial_jtag_test_rx_rcv:1;
+        /** serial_jtag_test_rx_dp : RO; bitpos: [5]; default: 1;
+         *  USB D+ rx value in test
+         */
+        uint32_t serial_jtag_test_rx_dp:1;
+        /** serial_jtag_test_rx_dm : RO; bitpos: [6]; default: 0;
+         *  USB D- rx value in test
+         */
+        uint32_t serial_jtag_test_rx_dm:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} usb_serial_jtag_test_reg_t;
+
+/** Type of misc_conf register
+ *  Clock enable control
+ */
+typedef union {
+    struct {
+        /** serial_jtag_clk_en : R/W; bitpos: [0]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t serial_jtag_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_misc_conf_reg_t;
+
+/** Type of mem_conf register
+ *  Memory power control
+ */
+typedef union {
+    struct {
+        /** serial_jtag_usb_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  1: power down usb memory.
+         */
+        uint32_t serial_jtag_usb_mem_pd:1;
+        /** serial_jtag_usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
+         *  1: Force clock on for usb memory.
+         */
+        uint32_t serial_jtag_usb_mem_clk_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_mem_conf_reg_t;
+
+/** Type of chip_rst register
+ *  CDC-ACM chip reset control.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_rts : RO; bitpos: [0]; default: 0;
+         *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+         */
+        uint32_t serial_jtag_rts:1;
+        /** serial_jtag_dtr : RO; bitpos: [1]; default: 0;
+         *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+         */
+        uint32_t serial_jtag_dtr:1;
+        /** serial_jtag_usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to disable chip reset from usb serial channel to reset chip.
+         */
+        uint32_t serial_jtag_usb_uart_chip_rst_dis:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_serial_jtag_chip_rst_reg_t;
+
+/** Type of get_line_code_w0 register
+ *  W0 of GET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
+         *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t serial_jtag_get_dw_dte_rate:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_get_line_code_w0_reg_t;
+
+/** Type of get_line_code_w1 register
+ *  W1 of GET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
+         *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t serial_jtag_get_bdata_bits:8;
+        /** serial_jtag_get_bparity_type : R/W; bitpos: [15:8]; default: 0;
+         *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t serial_jtag_get_bparity_type:8;
+        /** serial_jtag_get_bchar_format : R/W; bitpos: [23:16]; default: 0;
+         *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t serial_jtag_get_bchar_format:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} usb_serial_jtag_get_line_code_w1_reg_t;
+
+/** Type of config_update register
+ *  Configuration registers' value update
+ */
+typedef union {
+    struct {
+        /** serial_jtag_config_update : WT; bitpos: [0]; default: 0;
+         *  Write 1 to this register would update the value of configure registers from APB
+         *  clock domain to 48MHz clock domain.
+         */
+        uint32_t serial_jtag_config_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_config_update_reg_t;
+
+/** Type of ser_afifo_config register
+ *  Serial AFIFO configure register
+ */
+typedef union {
+    struct {
+        /** serial_jtag_serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+         */
+        uint32_t serial_jtag_serial_in_afifo_reset_wr:1;
+        /** serial_jtag_serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+         */
+        uint32_t serial_jtag_serial_in_afifo_reset_rd:1;
+        /** serial_jtag_serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+         */
+        uint32_t serial_jtag_serial_out_afifo_reset_wr:1;
+        /** serial_jtag_serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+         */
+        uint32_t serial_jtag_serial_out_afifo_reset_rd:1;
+        /** serial_jtag_serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
+         *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
+         */
+        uint32_t serial_jtag_serial_out_afifo_rempty:1;
+        /** serial_jtag_serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
+         *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+         */
+        uint32_t serial_jtag_serial_in_afifo_wfull:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} usb_serial_jtag_ser_afifo_config_reg_t;
+
+/** Type of eco_low_48 register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_rnd_eco_low_48 : R/W; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t serial_jtag_rnd_eco_low_48:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_low_48_reg_t;
+
+/** Type of eco_high_48 register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_rnd_eco_high_48 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Reserved.
+         */
+        uint32_t serial_jtag_rnd_eco_high_48:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_high_48_reg_t;
+
+/** Type of eco_low_apb register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_rnd_eco_low_apb : R/W; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t serial_jtag_rnd_eco_low_apb:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_low_apb_reg_t;
+
+/** Type of eco_high_apb register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_rnd_eco_high_apb : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Reserved.
+         */
+        uint32_t serial_jtag_rnd_eco_high_apb:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_high_apb_reg_t;
+
+/** Type of sram_ctrl register
+ *  PPA SRAM Control Register
+ */
+typedef union {
+    struct {
+        /** serial_jtag_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  Control signals
+         */
+        uint32_t serial_jtag_mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} usb_serial_jtag_sram_ctrl_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  Interrupt raw status register.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when flush cmd is received for IN
+         *  endpoint 2 of JTAG.
+         */
+        uint32_t serial_jtag_jtag_in_flush_int_raw:1;
+        /** serial_jtag_sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when SOF frame is received.
+         */
+        uint32_t serial_jtag_sof_int_raw:1;
+        /** serial_jtag_serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+         *  one packet.
+         */
+        uint32_t serial_jtag_serial_out_recv_pkt_int_raw:1;
+        /** serial_jtag_serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
+         *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+         */
+        uint32_t serial_jtag_serial_in_empty_int_raw:1;
+        /** serial_jtag_pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when pid error is detected.
+         */
+        uint32_t serial_jtag_pid_err_int_raw:1;
+        /** serial_jtag_crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when CRC5 error is detected.
+         */
+        uint32_t serial_jtag_crc5_err_int_raw:1;
+        /** serial_jtag_crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when CRC16 error is detected.
+         */
+        uint32_t serial_jtag_crc16_err_int_raw:1;
+        /** serial_jtag_stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when stuff error is detected.
+         */
+        uint32_t serial_jtag_stuff_err_int_raw:1;
+        /** serial_jtag_in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+         *  received.
+         */
+        uint32_t serial_jtag_in_token_rec_in_ep1_int_raw:1;
+        /** serial_jtag_usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when usb bus reset is detected.
+         */
+        uint32_t serial_jtag_usb_bus_reset_int_raw:1;
+        /** serial_jtag_out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+         *  zero palyload.
+         */
+        uint32_t serial_jtag_out_ep1_zero_payload_int_raw:1;
+        /** serial_jtag_out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+         *  zero palyload.
+         */
+        uint32_t serial_jtag_out_ep2_zero_payload_int_raw:1;
+        /** serial_jtag_rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+         *  is changed.
+         */
+        uint32_t serial_jtag_rts_chg_int_raw:1;
+        /** serial_jtag_dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+         *  is changed.
+         */
+        uint32_t serial_jtag_dtr_chg_int_raw:1;
+        /** serial_jtag_get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+         *  received.
+         */
+        uint32_t serial_jtag_get_line_code_int_raw:1;
+        /** serial_jtag_set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+         *  received.
+         */
+        uint32_t serial_jtag_set_line_code_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t serial_jtag_jtag_in_flush_int_st:1;
+        /** serial_jtag_sof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_SOF_INT interrupt.
+         */
+        uint32_t serial_jtag_sof_int_st:1;
+        /** serial_jtag_serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_jtag_serial_out_recv_pkt_int_st:1;
+        /** serial_jtag_serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_jtag_serial_in_empty_int_st:1;
+        /** serial_jtag_pid_err_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_PID_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_pid_err_int_st:1;
+        /** serial_jtag_crc5_err_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_CRC5_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_crc5_err_int_st:1;
+        /** serial_jtag_crc16_err_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_CRC16_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_crc16_err_int_st:1;
+        /** serial_jtag_stuff_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_STUFF_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_stuff_err_int_st:1;
+        /** serial_jtag_in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_IN_TOKEN_REC_IN_EP1_INT interrupt.
+         */
+        uint32_t serial_jtag_in_token_rec_in_ep1_int_st:1;
+        /** serial_jtag_usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t serial_jtag_usb_bus_reset_int_st:1;
+        /** serial_jtag_out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t serial_jtag_out_ep1_zero_payload_int_st:1;
+        /** serial_jtag_out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t serial_jtag_out_ep2_zero_payload_int_st:1;
+        /** serial_jtag_rts_chg_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_RTS_CHG_INT interrupt.
+         */
+        uint32_t serial_jtag_rts_chg_int_st:1;
+        /** serial_jtag_dtr_chg_int_st : RO; bitpos: [13]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_DTR_CHG_INT interrupt.
+         */
+        uint32_t serial_jtag_dtr_chg_int_st:1;
+        /** serial_jtag_get_line_code_int_st : RO; bitpos: [14]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t serial_jtag_get_line_code_int_st:1;
+        /** serial_jtag_set_line_code_int_st : RO; bitpos: [15]; default: 0;
+         *  The raw interrupt status bit for the usb_serial_jtag_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t serial_jtag_set_line_code_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable status register.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t serial_jtag_jtag_in_flush_int_ena:1;
+        /** serial_jtag_sof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_SOF_INT interrupt.
+         */
+        uint32_t serial_jtag_sof_int_ena:1;
+        /** serial_jtag_serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_jtag_serial_out_recv_pkt_int_ena:1;
+        /** serial_jtag_serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_jtag_serial_in_empty_int_ena:1;
+        /** serial_jtag_pid_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_PID_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_pid_err_int_ena:1;
+        /** serial_jtag_crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_CRC5_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_crc5_err_int_ena:1;
+        /** serial_jtag_crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_CRC16_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_crc16_err_int_ena:1;
+        /** serial_jtag_stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_STUFF_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_stuff_err_int_ena:1;
+        /** serial_jtag_in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_IN_TOKEN_REC_IN_EP1_INT interrupt.
+         */
+        uint32_t serial_jtag_in_token_rec_in_ep1_int_ena:1;
+        /** serial_jtag_usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t serial_jtag_usb_bus_reset_int_ena:1;
+        /** serial_jtag_out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t serial_jtag_out_ep1_zero_payload_int_ena:1;
+        /** serial_jtag_out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t serial_jtag_out_ep2_zero_payload_int_ena:1;
+        /** serial_jtag_rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_RTS_CHG_INT interrupt.
+         */
+        uint32_t serial_jtag_rts_chg_int_ena:1;
+        /** serial_jtag_dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_DTR_CHG_INT interrupt.
+         */
+        uint32_t serial_jtag_dtr_chg_int_ena:1;
+        /** serial_jtag_get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t serial_jtag_get_line_code_int_ena:1;
+        /** serial_jtag_set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The interrupt enable bit for the usb_serial_jtag_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t serial_jtag_set_line_code_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear status register.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t serial_jtag_jtag_in_flush_int_clr:1;
+        /** serial_jtag_sof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_JTAG_SOF_INT interrupt.
+         */
+        uint32_t serial_jtag_sof_int_clr:1;
+        /** serial_jtag_serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_jtag_serial_out_recv_pkt_int_clr:1;
+        /** serial_jtag_serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_jtag_serial_in_empty_int_clr:1;
+        /** serial_jtag_pid_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_PID_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_pid_err_int_clr:1;
+        /** serial_jtag_crc5_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_CRC5_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_crc5_err_int_clr:1;
+        /** serial_jtag_crc16_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_CRC16_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_crc16_err_int_clr:1;
+        /** serial_jtag_stuff_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_STUFF_ERR_INT interrupt.
+         */
+        uint32_t serial_jtag_stuff_err_int_clr:1;
+        /** serial_jtag_in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_IN_TOKEN_IN_EP1_INT interrupt.
+         */
+        uint32_t serial_jtag_in_token_rec_in_ep1_int_clr:1;
+        /** serial_jtag_usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t serial_jtag_usb_bus_reset_int_clr:1;
+        /** serial_jtag_out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t serial_jtag_out_ep1_zero_payload_int_clr:1;
+        /** serial_jtag_out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t serial_jtag_out_ep2_zero_payload_int_clr:1;
+        /** serial_jtag_rts_chg_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_RTS_CHG_INT interrupt.
+         */
+        uint32_t serial_jtag_rts_chg_int_clr:1;
+        /** serial_jtag_dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_DTR_CHG_INT interrupt.
+         */
+        uint32_t serial_jtag_dtr_chg_int_clr:1;
+        /** serial_jtag_get_line_code_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t serial_jtag_get_line_code_int_clr:1;
+        /** serial_jtag_set_line_code_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the usb_serial_jtag_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t serial_jtag_set_line_code_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_clr_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of jfifo_st register
+ *  JTAG FIFO status and control registers.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
+         *  JTAT in fifo counter.
+         */
+        uint32_t serial_jtag_in_fifo_cnt:2;
+        /** serial_jtag_in_fifo_empty : RO; bitpos: [2]; default: 1;
+         *  1: JTAG in fifo is empty.
+         */
+        uint32_t serial_jtag_in_fifo_empty:1;
+        /** serial_jtag_in_fifo_full : RO; bitpos: [3]; default: 0;
+         *  1: JTAG in fifo is full.
+         */
+        uint32_t serial_jtag_in_fifo_full:1;
+        /** serial_jtag_out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
+         *  JTAT out fifo counter.
+         */
+        uint32_t serial_jtag_out_fifo_cnt:2;
+        /** serial_jtag_out_fifo_empty : RO; bitpos: [6]; default: 1;
+         *  1: JTAG out fifo is empty.
+         */
+        uint32_t serial_jtag_out_fifo_empty:1;
+        /** serial_jtag_out_fifo_full : RO; bitpos: [7]; default: 0;
+         *  1: JTAG out fifo is full.
+         */
+        uint32_t serial_jtag_out_fifo_full:1;
+        /** serial_jtag_in_fifo_reset : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to reset JTAG in fifo.
+         */
+        uint32_t serial_jtag_in_fifo_reset:1;
+        /** serial_jtag_out_fifo_reset : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to reset JTAG out fifo.
+         */
+        uint32_t serial_jtag_out_fifo_reset:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} usb_serial_jtag_jfifo_st_reg_t;
+
+/** Type of fram_num register
+ *  Last received SOF frame index register.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_sof_frame_index : RO; bitpos: [10:0]; default: 0;
+         *  Frame index of received SOF frame.
+         */
+        uint32_t serial_jtag_sof_frame_index:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} usb_serial_jtag_fram_num_reg_t;
+
+/** Type of in_ep0_st register
+ *  Control IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_in_ep0_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 0.
+         */
+        uint32_t serial_jtag_in_ep0_state:2;
+        /** serial_jtag_in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 0.
+         */
+        uint32_t serial_jtag_in_ep0_wr_addr:7;
+        /** serial_jtag_in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 0.
+         */
+        uint32_t serial_jtag_in_ep0_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep0_st_reg_t;
+
+/** Type of in_ep1_st register
+ *  CDC-ACM IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_in_ep1_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 1.
+         */
+        uint32_t serial_jtag_in_ep1_state:2;
+        /** serial_jtag_in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 1.
+         */
+        uint32_t serial_jtag_in_ep1_wr_addr:7;
+        /** serial_jtag_in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 1.
+         */
+        uint32_t serial_jtag_in_ep1_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep1_st_reg_t;
+
+/** Type of in_ep2_st register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_in_ep2_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 2.
+         */
+        uint32_t serial_jtag_in_ep2_state:2;
+        /** serial_jtag_in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 2.
+         */
+        uint32_t serial_jtag_in_ep2_wr_addr:7;
+        /** serial_jtag_in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 2.
+         */
+        uint32_t serial_jtag_in_ep2_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep2_st_reg_t;
+
+/** Type of in_ep3_st register
+ *  JTAG IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_in_ep3_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 3.
+         */
+        uint32_t serial_jtag_in_ep3_state:2;
+        /** serial_jtag_in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 3.
+         */
+        uint32_t serial_jtag_in_ep3_wr_addr:7;
+        /** serial_jtag_in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 3.
+         */
+        uint32_t serial_jtag_in_ep3_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep3_st_reg_t;
+
+/** Type of out_ep0_st register
+ *  Control OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_out_ep0_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 0.
+         */
+        uint32_t serial_jtag_out_ep0_state:2;
+        /** serial_jtag_out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 0. When usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT is
+         *  detected, there are usb_serial_jtag_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+         */
+        uint32_t serial_jtag_out_ep0_wr_addr:7;
+        /** serial_jtag_out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 0.
+         */
+        uint32_t serial_jtag_out_ep0_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep0_st_reg_t;
+
+/** Type of out_ep1_st register
+ *  CDC-ACM OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_out_ep1_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 1.
+         */
+        uint32_t serial_jtag_out_ep1_state:2;
+        /** serial_jtag_out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 1. When usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT is
+         *  detected, there are usb_serial_jtag_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+         */
+        uint32_t serial_jtag_out_ep1_wr_addr:7;
+        /** serial_jtag_out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 1.
+         */
+        uint32_t serial_jtag_out_ep1_rd_addr:7;
+        /** serial_jtag_out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
+         *  Data count in OUT endpoint 1 when one packet is received.
+         */
+        uint32_t serial_jtag_out_ep1_rec_data_cnt:7;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep1_st_reg_t;
+
+/** Type of out_ep2_st register
+ *  JTAG OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_out_ep2_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 2.
+         */
+        uint32_t serial_jtag_out_ep2_state:2;
+        /** serial_jtag_out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 2. When usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT is
+         *  detected, there are usb_serial_jtag_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+         */
+        uint32_t serial_jtag_out_ep2_wr_addr:7;
+        /** serial_jtag_out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 2.
+         */
+        uint32_t serial_jtag_out_ep2_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep2_st_reg_t;
+
+/** Type of set_line_code_w0 register
+ *  W0 of SET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_dw_dte_rate : RO; bitpos: [31:0]; default: 0;
+         *  The value of dwDTERate set by host through SET_LINE_CODING command.
+         */
+        uint32_t serial_jtag_dw_dte_rate:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_set_line_code_w0_reg_t;
+
+/** Type of set_line_code_w1 register
+ *  W1 of SET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_bchar_format : RO; bitpos: [7:0]; default: 0;
+         *  The value of bCharFormat set by host through SET_LINE_CODING command.
+         */
+        uint32_t serial_jtag_bchar_format:8;
+        /** serial_jtag_bparity_type : RO; bitpos: [15:8]; default: 0;
+         *  The value of bParityTpye set by host through SET_LINE_CODING command.
+         */
+        uint32_t serial_jtag_bparity_type:8;
+        /** serial_jtag_bdata_bits : RO; bitpos: [23:16]; default: 0;
+         *  The value of bDataBits set by host through SET_LINE_CODING command.
+         */
+        uint32_t serial_jtag_bdata_bits:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} usb_serial_jtag_set_line_code_w1_reg_t;
+
+/** Type of bus_reset_st register
+ *  USB Bus reset status register
+ */
+typedef union {
+    struct {
+        /** serial_jtag_usb_bus_reset_st : RO; bitpos: [0]; default: 1;
+         *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+         *  reset is released.
+         */
+        uint32_t serial_jtag_usb_bus_reset_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_bus_reset_st_reg_t;
+
+/** Type of eco_cell_ctrl_48 register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_rdn_result_48 : RO; bitpos: [0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t serial_jtag_rdn_result_48:1;
+        /** serial_jtag_rdn_ena_48 : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t serial_jtag_rdn_ena_48:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_cell_ctrl_48_reg_t;
+
+/** Type of eco_cell_ctrl_apb register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** serial_jtag_rdn_result_apb : RO; bitpos: [0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t serial_jtag_rdn_result_apb:1;
+        /** serial_jtag_rdn_ena_apb : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t serial_jtag_rdn_ena_apb:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_eco_cell_ctrl_apb_reg_t;
+
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Date register
+ */
+typedef union {
+    struct {
+        /** serial_jtag_date : R/W; bitpos: [31:0]; default: 34676752;
+         *  register version.
+         */
+        uint32_t serial_jtag_date:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_date_reg_t;
+
+
+typedef struct usb_serial_jtag_dev_t {
+    volatile usb_serial_jtag_ep1_reg_t ep1;
+    volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
+    volatile usb_serial_jtag_int_raw_reg_t int_raw;
+    volatile usb_serial_jtag_int_st_reg_t int_st;
+    volatile usb_serial_jtag_int_ena_reg_t int_ena;
+    volatile usb_serial_jtag_int_clr_reg_t int_clr;
+    volatile usb_serial_jtag_conf0_reg_t conf0;
+    volatile usb_serial_jtag_test_reg_t test;
+    volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
+    volatile usb_serial_jtag_fram_num_reg_t fram_num;
+    volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
+    volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
+    volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
+    volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
+    volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
+    volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
+    volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
+    volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
+    volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
+    volatile usb_serial_jtag_chip_rst_reg_t chip_rst;
+    volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0;
+    volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1;
+    volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0;
+    volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1;
+    volatile usb_serial_jtag_config_update_reg_t config_update;
+    volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config;
+    volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st;
+    volatile usb_serial_jtag_eco_low_48_reg_t eco_low_48;
+    volatile usb_serial_jtag_eco_high_48_reg_t eco_high_48;
+    volatile usb_serial_jtag_eco_cell_ctrl_48_reg_t eco_cell_ctrl_48;
+    volatile usb_serial_jtag_eco_low_apb_reg_t eco_low_apb;
+    volatile usb_serial_jtag_eco_high_apb_reg_t eco_high_apb;
+    volatile usb_serial_jtag_eco_cell_ctrl_apb_reg_t eco_cell_ctrl_apb;
+    volatile usb_serial_jtag_sram_ctrl_reg_t sram_ctrl;
+    volatile usb_serial_jtag_date_reg_t date;
+} usb_serial_jtag_dev_t;
+
+extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x8c, "Invalid size of usb_serial_jtag_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_utmi_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_utmi_struct.h
new file mode 100644
index 0000000000..e891217808
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_utmi_struct.h
@@ -0,0 +1,231 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13430
+
+/**
+ * Following register description is taken from
+ * U2OPHYT40LL USB 2.0 OTG PHY specification v2.0
+ */
+
+typedef union {
+    struct {
+        /** clk_gate_rx : R/W; bitpos: [0]; default 2'b0;
+          * Clock Gating Control Signal for Rx.
+          * 2'b0 Lower power consumption
+          * 2'b1 Lowest power consumption mode
+          * 2'b2 Normal power consumption mode
+          */
+        uint32_t clk_gate_rx: 2;
+        /** clk_gate_tx : R/W; bitpos: [2]; default: 1'b0;
+          * Clock Gating Control Signal for Rx.
+          * 1'b0 Low power consumption mode
+          * 1'b1 Normal power consumption mode
+          */
+        uint32_t clk_gate_tx: 1;
+        /** adj_res_fs : Reserved; bitpos: [3]; default: 0;
+          * Fine tune the 45ohm termination resistor (FS)
+          * Reserved
+          */
+        uint32_t adj_res_fs: 2;
+        /** adj_res_hs : R/W; bitpos: [5]; default: 3'b100;
+          * Fine tune the 45ohm termination resistor (HS)
+          * 3'b000 40 Ohm
+          * 3'b100 45 Ohm
+          * 3'b110 50 Ohm
+          */
+        uint32_t adj_res_hs: 3;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} usb_utmi_fc_00_reg_t;
+
+typedef union {
+    struct {
+        /** adj_vref_sq : R/W; bitpos: [0]; default: 4'b0010;
+          * Squelch detection threshold voltage control bits
+          * 4'b0000  92 mV
+          * 4'b0010 124 mV
+          * 4'b0011 152 mV
+          */
+        uint32_t adj_vref_sq: 4;
+        /** adj_pw_hs : R/W; bitpos: [4]; default: 4'b1111;
+          * Super power saving with reduced output swing mode control bits (for HS mode only)
+          * 4'b0001 100 mV output swing
+          * 4'b0011 200 mV output swing
+          * 4'b0111 300 mV output swing
+          * 4'b1111 400 mV output swing
+          */
+        uint32_t adj_pw_hs: 4;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} usb_utmi_fc_01_reg_t;
+
+typedef union {
+    struct {
+        /** adj_iref_res : R/W; bitpos: [0]; default: 4'b0111
+          * Internal bias current adjustment control bits
+          * 4'b0000 125 uA
+          * 4'b0111 100 uA
+          * 4'b1111  78 uA
+          */
+        uint32_t adj_iref_res: 4;
+        /** adj_vsw_hs : R/W; bitpos: [4]; default: 3'b100
+          * Output eye shape adjustment control bits
+          * 3'b000 320 mV
+          * 3'b100 400 mV
+          * 3'b111 460 mV
+          */
+        uint32_t adj_vsw_hs: 3;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} usb_utmi_fc_02_reg_t;
+
+typedef union {
+    struct {
+        /** adj_pll : R/W; bitpos: [0]; default: 4'b0101
+          * PLL adjustment signal
+          */
+        uint32_t adj_pll: 4;
+        /** adj_osc : R/W; bitpos: [4]; default: 3'b000
+          * TX Clock phase adjust signal
+          */
+        uint32_t adj_txclk_phase: 3;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} usb_utmi_fc_03_reg_t;
+
+typedef union {
+    struct {
+        /** test_sel : R/W; bitpos: [0]; default: 8'b0
+          * The PHY has test_sel register here, which normally drives DTO (Digital Test Output) signal.
+          * In our implementation output of this register is left floating and DTO is driven from Probe module.
+          * Thus writing to this register has no effect and is renamed to 'reserved'
+          */
+        uint32_t reserved: 8;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} usb_utmi_fc_04_reg_t;
+
+typedef union {
+    struct {
+        /** rxgap_fix_en : R/W; bitpos: [0]; default: 1'b1
+          * RXGAP fix enable
+          */
+        uint32_t rxgap_fix_en: 1;
+        /** counter_sel : R/W; bitpos: [1]; default: 1'b0
+          * SIE_input sample enable
+          */
+        uint32_t counter_sel: 1;
+        /** clk_sel : R/W; bitpos: [2]; default: 1'b0
+          * CLK60_30 source select
+          */
+        uint32_t clk_sel: 1;
+        /** phy_mode_sel : R/W; bitpos: [3]; default: 1'b0
+          * PHY MODE select
+          */
+        uint32_t phy_mode_sel: 1;
+        /** uni_bidi_i : R/W; bitpos: [4]; default: 1'b0
+          * UNI_BIDI signal
+          */
+        uint32_t uni_bidi_i: 1;
+        /** short_5v : R/W; bitpos: [5]; default: 1'b0
+          * SHORT_5V signal
+          */
+        uint32_t short_5v: 1;
+        /** short_5v_enable : R/W; bitpos: [6]; default: 1'b1
+          * SHORT_5V_ENABLE signal
+          */
+        uint32_t short_5v_enable: 1;
+        /** usable_en : R/W; bitpos: [7]; default: 1'b1
+          * compare_begin delay time select
+          */
+        uint32_t usable_en: 1;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} usb_utmi_fc_05_reg_t;
+
+typedef union {
+    struct {
+        /** ls_par_en : R/W; bitpos: [0]; default: 1'b0
+          * LS mode with parallel enable
+          */
+        uint32_t ls_par_en: 1;
+        /** det_fseop_en : R/W; bitpos: [1]; default: 1'b0
+          * FS EOP detect enable
+          */
+        uint32_t det_fseop_en: 1;
+        /** pre_hphy_lsie : R/W; bitpos: [2]; default: 1'b0
+          * Dis_preamble enable
+          */
+        uint32_t pre_hphy_lsie: 1;
+        /** ls_kpalv_en : R/W; bitpos: [3]; default: 1'b0
+          * LS mode keep alive enable
+          */
+        uint32_t ls_kpalv_en: 1;
+        /** hs_tx2rx_dly_cnt_sel : R/W; bitpos: [4]; default: 3'b100
+          * PHY High-SPeed bus turn-around time select
+          */
+        uint32_t hs_tx2rx_dly_cnt_sel: 3;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} usb_utmi_fc_06_reg_t;
+
+typedef union {
+    struct {
+        /** cnt_num : R/W; bitpos: [1:0]; default: 2'b00
+          * 3 ms counter select
+          * 00: 392us (Default)
+          * 01: 682us
+          * 10: 1.36ms
+          * 11: 2.72ms
+          */
+        uint32_t cnt_num: 2;
+        /** clk480_sel : R/W; bitpos: [2]; default: 1'b0
+          * CLK_480 output time select
+          * 0: CLK_480 is valid after a delay time when PLL is locked
+          * 1: CLK_480 is valid immediately after PLL is locked
+          */
+        uint32_t clk480_sel: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} usb_utmi_fc_07_reg_t;
+
+typedef struct usb_utmi_dev_t {
+    volatile usb_utmi_fc_00_reg_t fc_00;
+    volatile usb_utmi_fc_01_reg_t fc_01;
+    volatile usb_utmi_fc_02_reg_t fc_02;
+    volatile usb_utmi_fc_03_reg_t fc_03;
+    volatile usb_utmi_fc_04_reg_t fc_04;
+    volatile usb_utmi_fc_05_reg_t fc_05;
+    volatile usb_utmi_fc_06_reg_t fc_06;
+    volatile usb_utmi_fc_07_reg_t fc_07;
+} usb_utmi_dev_t;
+
+extern usb_utmi_dev_t USB_UTMI;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_utmi_dev_t) == 0x20, "Invalid size of usb_utmi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_eco5_struct.h
new file mode 100644
index 0000000000..a90ba9b8d8
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_eco5_struct.h
@@ -0,0 +1,139 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: USB wrapper registers. */
+/** Type of otg_conf register
+ *  USB wrapper configuration registers.
+ */
+typedef union {
+    struct {
+        /** srp_sessend_override : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to enable the software over-ride of srp session end signal. 1'b0:
+         *  the signal is controlled by the chip input, 1'b1: the signal is controlled by the
+         *  software.
+         */
+        uint32_t srp_sessend_override:1;
+        /** srp_sessend_value : R/W; bitpos: [1]; default: 0;
+         *  Software over-ride value of srp session end signal.
+         */
+        uint32_t srp_sessend_value:1;
+        /** phy_sel : R/W; bitpos: [2]; default: 0;
+         *  Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
+         */
+        uint32_t phy_sel:1;
+        /** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
+         *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pd:1;
+        /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
+         *  Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
+         */
+        uint32_t dbnce_fltr_bypass:1;
+        /** exchg_pins_override : R/W; bitpos: [5]; default: 0;
+         *  Enable software controlle USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [6]; default: 0;
+         *  USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [8:7]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV.
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [10:9]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV.
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [11]; default: 0;
+         *  Enable software controlle input  threshold.
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [12]; default: 0;
+         *  Enable software controlle USB D+ D- pullup pulldown.
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [13]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [14]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [15]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [16]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [17]; default: 0;
+         *  Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [18]; default: 0;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
+         *  Force ahb clock always on.
+         */
+        uint32_t ahb_clk_force_on:1;
+        /** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
+         *  Force phy clock always on.
+         */
+        uint32_t phy_clk_force_on:1;
+        uint32_t reserved_21:1;
+        /** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
+         *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pu:1;
+        uint32_t reserved_23:8;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Disable auto clock gating of CSR registers.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} usb_wrap_otg_conf_reg_t;
+
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
+         *  Date register.
+         */
+        uint32_t usb_wrap_date:32;
+    };
+    uint32_t val;
+} usb_wrap_date_reg_t;
+
+
+typedef struct {
+    volatile usb_wrap_otg_conf_reg_t otg_conf;
+    uint32_t reserved_004[254];
+    volatile usb_wrap_date_reg_t date;
+} usb_wrap_dev_t;
+
+extern usb_wrap_dev_t USB_WRAP;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_reg.h
new file mode 100644
index 0000000000..31fbd239ff
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_reg.h
@@ -0,0 +1,182 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_WRAP_OTG_CONF_REG register
+ *  USB wrapper configuration registers.
+ */
+#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0)
+/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to enable the software over-ride of srp session end signal. 1'b0:
+ *  the signal is controlled by the chip input, 1'b1: the signal is controlled by the
+ *  software.
+ */
+#define USB_WRAP_SRP_SESSEND_OVERRIDE    (BIT(0))
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_M  (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S)
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_V  0x00000001U
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_S  0
+/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0;
+ *  Software over-ride value of srp session end signal.
+ */
+#define USB_WRAP_SRP_SESSEND_VALUE    (BIT(1))
+#define USB_WRAP_SRP_SESSEND_VALUE_M  (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S)
+#define USB_WRAP_SRP_SESSEND_VALUE_V  0x00000001U
+#define USB_WRAP_SRP_SESSEND_VALUE_S  1
+/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0;
+ *  Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
+ */
+#define USB_WRAP_PHY_SEL    (BIT(2))
+#define USB_WRAP_PHY_SEL_M  (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S)
+#define USB_WRAP_PHY_SEL_V  0x00000001U
+#define USB_WRAP_PHY_SEL_S  2
+/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0;
+ *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
+ */
+#define USB_WRAP_DFIFO_FORCE_PD    (BIT(3))
+#define USB_WRAP_DFIFO_FORCE_PD_M  (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S)
+#define USB_WRAP_DFIFO_FORCE_PD_V  0x00000001U
+#define USB_WRAP_DFIFO_FORCE_PD_S  3
+/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0;
+ *  Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
+ */
+#define USB_WRAP_DBNCE_FLTR_BYPASS    (BIT(4))
+#define USB_WRAP_DBNCE_FLTR_BYPASS_M  (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S)
+#define USB_WRAP_DBNCE_FLTR_BYPASS_V  0x00000001U
+#define USB_WRAP_DBNCE_FLTR_BYPASS_S  4
+/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0;
+ *  Enable software controlle USB D+ D- exchange
+ */
+#define USB_WRAP_EXCHG_PINS_OVERRIDE    (BIT(5))
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_M  (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S)
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_S  5
+/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0;
+ *  USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
+ */
+#define USB_WRAP_EXCHG_PINS    (BIT(6))
+#define USB_WRAP_EXCHG_PINS_M  (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S)
+#define USB_WRAP_EXCHG_PINS_V  0x00000001U
+#define USB_WRAP_EXCHG_PINS_S  6
+/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV.
+ */
+#define USB_WRAP_VREFH    0x00000003U
+#define USB_WRAP_VREFH_M  (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S)
+#define USB_WRAP_VREFH_V  0x00000003U
+#define USB_WRAP_VREFH_S  7
+/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV.
+ */
+#define USB_WRAP_VREFL    0x00000003U
+#define USB_WRAP_VREFL_M  (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S)
+#define USB_WRAP_VREFL_V  0x00000003U
+#define USB_WRAP_VREFL_S  9
+/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0;
+ *  Enable software controlle input  threshold.
+ */
+#define USB_WRAP_VREF_OVERRIDE    (BIT(11))
+#define USB_WRAP_VREF_OVERRIDE_M  (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S)
+#define USB_WRAP_VREF_OVERRIDE_V  0x00000001U
+#define USB_WRAP_VREF_OVERRIDE_S  11
+/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0;
+ *  Enable software controlle USB D+ D- pullup pulldown.
+ */
+#define USB_WRAP_PAD_PULL_OVERRIDE    (BIT(12))
+#define USB_WRAP_PAD_PULL_OVERRIDE_M  (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S)
+#define USB_WRAP_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_WRAP_PAD_PULL_OVERRIDE_S  12
+/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0;
+ *  Controlle USB D+ pullup.
+ */
+#define USB_WRAP_DP_PULLUP    (BIT(13))
+#define USB_WRAP_DP_PULLUP_M  (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S)
+#define USB_WRAP_DP_PULLUP_V  0x00000001U
+#define USB_WRAP_DP_PULLUP_S  13
+/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0;
+ *  Controlle USB D+ pulldown.
+ */
+#define USB_WRAP_DP_PULLDOWN    (BIT(14))
+#define USB_WRAP_DP_PULLDOWN_M  (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S)
+#define USB_WRAP_DP_PULLDOWN_V  0x00000001U
+#define USB_WRAP_DP_PULLDOWN_S  14
+/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0;
+ *  Controlle USB D+ pullup.
+ */
+#define USB_WRAP_DM_PULLUP    (BIT(15))
+#define USB_WRAP_DM_PULLUP_M  (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S)
+#define USB_WRAP_DM_PULLUP_V  0x00000001U
+#define USB_WRAP_DM_PULLUP_S  15
+/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0;
+ *  Controlle USB D+ pulldown.
+ */
+#define USB_WRAP_DM_PULLDOWN    (BIT(16))
+#define USB_WRAP_DM_PULLDOWN_M  (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S)
+#define USB_WRAP_DM_PULLDOWN_V  0x00000001U
+#define USB_WRAP_DM_PULLDOWN_S  16
+/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0;
+ *  Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
+ */
+#define USB_WRAP_PULLUP_VALUE    (BIT(17))
+#define USB_WRAP_PULLUP_VALUE_M  (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S)
+#define USB_WRAP_PULLUP_VALUE_V  0x00000001U
+#define USB_WRAP_PULLUP_VALUE_S  17
+/** USB_WRAP_USB_PAD_ENABLE : R/W; bitpos: [18]; default: 0;
+ *  Enable USB pad function.
+ */
+#define USB_WRAP_USB_PAD_ENABLE    (BIT(18))
+#define USB_WRAP_USB_PAD_ENABLE_M  (USB_WRAP_USB_PAD_ENABLE_V << USB_WRAP_USB_PAD_ENABLE_S)
+#define USB_WRAP_USB_PAD_ENABLE_V  0x00000001U
+#define USB_WRAP_USB_PAD_ENABLE_S  18
+/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 0;
+ *  Force ahb clock always on.
+ */
+#define USB_WRAP_AHB_CLK_FORCE_ON    (BIT(19))
+#define USB_WRAP_AHB_CLK_FORCE_ON_M  (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S)
+#define USB_WRAP_AHB_CLK_FORCE_ON_V  0x00000001U
+#define USB_WRAP_AHB_CLK_FORCE_ON_S  19
+/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1;
+ *  Force phy clock always on.
+ */
+#define USB_WRAP_PHY_CLK_FORCE_ON    (BIT(20))
+#define USB_WRAP_PHY_CLK_FORCE_ON_M  (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S)
+#define USB_WRAP_PHY_CLK_FORCE_ON_V  0x00000001U
+#define USB_WRAP_PHY_CLK_FORCE_ON_S  20
+/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0;
+ *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
+ */
+#define USB_WRAP_DFIFO_FORCE_PU    (BIT(22))
+#define USB_WRAP_DFIFO_FORCE_PU_M  (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S)
+#define USB_WRAP_DFIFO_FORCE_PU_V  0x00000001U
+#define USB_WRAP_DFIFO_FORCE_PU_S  22
+/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Disable auto clock gating of CSR registers.
+ */
+#define USB_WRAP_CLK_EN    (BIT(31))
+#define USB_WRAP_CLK_EN_M  (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S)
+#define USB_WRAP_CLK_EN_V  0x00000001U
+#define USB_WRAP_CLK_EN_S  31
+
+/** USB_WRAP_DATE_REG register
+ *  Date register.
+ */
+#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc)
+/** USB_WRAP_USB_WRAP_DATE : HRO; bitpos: [31:0]; default: 587400452;
+ *  Date register.
+ */
+#define USB_WRAP_USB_WRAP_DATE    0xFFFFFFFFU
+#define USB_WRAP_USB_WRAP_DATE_M  (USB_WRAP_USB_WRAP_DATE_V << USB_WRAP_USB_WRAP_DATE_S)
+#define USB_WRAP_USB_WRAP_DATE_V  0xFFFFFFFFU
+#define USB_WRAP_USB_WRAP_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_struct.h
new file mode 100644
index 0000000000..aa7f0f58e6
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_struct.h
@@ -0,0 +1,181 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: USB wrapper registers. */
+/** Type of otg_conf register
+ *  USB wrapper configuration registers.
+ */
+typedef union {
+    struct {
+        /** srp_sessend_override : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to enable the software over-ride of srp session end signal. 1'b0:
+         *  the signal is controlled by the chip input, 1'b1: the signal is controlled by the
+         *  software.
+         */
+        uint32_t srp_sessend_override:1;
+        /** srp_sessend_value : R/W; bitpos: [1]; default: 0;
+         *  Software over-ride value of srp session end signal.
+         */
+        uint32_t srp_sessend_value:1;
+        /** phy_sel : R/W; bitpos: [2]; default: 0;
+         *  Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
+         */
+        uint32_t phy_sel:1;
+        /** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
+         *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pd:1;
+        /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
+         *  Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
+         */
+        uint32_t dbnce_fltr_bypass:1;
+        /** exchg_pins_override : R/W; bitpos: [5]; default: 0;
+         *  Enable software controlle USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [6]; default: 0;
+         *  USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [8:7]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV.
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [10:9]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV.
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [11]; default: 0;
+         *  Enable software controlle input  threshold.
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [12]; default: 0;
+         *  Enable software controlle USB D+ D- pullup pulldown.
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [13]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [14]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [15]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [16]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [17]; default: 0;
+         *  Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [18]; default: 0;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
+         *  Force ahb clock always on.
+         */
+        uint32_t ahb_clk_force_on:1;
+        /** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
+         *  Force phy clock always on.
+         */
+        uint32_t phy_clk_force_on:1;
+        /** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
+         *  Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
+         */
+        uint32_t phy_tx_edge_sel:1;
+        /** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
+         *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pu:1;
+        uint32_t reserved_23:8;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Disable auto clock gating of CSR registers.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} usb_wrap_otg_conf_reg_t;
+
+/** Type of test_conf register
+ *  TEST relative configuration registers.
+ */
+typedef union {
+    struct {
+        /** test_enable : R/W; bitpos: [0]; default: 0;
+         *  Enable to test the USB pad.
+         */
+        uint32_t test_enable:1;
+        /** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
+         *  USB pad oen in test.
+         */
+        uint32_t test_usb_wrap_oe:1;
+        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
+         *  USB D+ tx value in test.
+         */
+        uint32_t test_tx_dp:1;
+        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
+         *  USB D- tx value in test.
+         */
+        uint32_t test_tx_dm:1;
+        /** test_rx_rcv : RO; bitpos: [4]; default: 0;
+         *  USB differential rx value in test.
+         */
+        uint32_t test_rx_rcv:1;
+        /** test_rx_dp : RO; bitpos: [5]; default: 0;
+         *  USB D+ rx value in test.
+         */
+        uint32_t test_rx_dp:1;
+        /** test_rx_dm : RO; bitpos: [6]; default: 0;
+         *  USB D- rx value in test.
+         */
+        uint32_t test_rx_dm:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} usb_wrap_test_conf_reg_t;
+
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
+         *  Date register.
+         */
+        uint32_t usb_wrap_date:32;
+    };
+    uint32_t val;
+} usb_wrap_date_reg_t;
+
+
+typedef struct usb_wrap_dev_t {
+    volatile usb_wrap_otg_conf_reg_t otg_conf;
+    volatile usb_wrap_test_conf_reg_t test_conf;
+    uint32_t reserved_008[253];
+    volatile usb_wrap_date_reg_t date;
+} usb_wrap_dev_t;
+
+extern usb_wrap_dev_t USB_WRAP;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tools/ci/astyle-rules.yml b/tools/ci/astyle-rules.yml
index ad50bb3fb0..8073b61e12 100644
--- a/tools/ci/astyle-rules.yml
+++ b/tools/ci/astyle-rules.yml
@@ -155,6 +155,7 @@ components_not_formatted_permanent:
     - "/components/rt/"
     # SoC header files (generated)
     - "/components/soc/*/register/soc/"
+    - "/components/soc/*/register/hw_ver*/soc/"
     # Example resource files (generated)
     - "/examples/peripherals/lcd/i80_controller/main/images/"
     - "/examples/peripherals/dac/dac_continuous/dac_audio/main/audio_example_file.h"
diff --git a/tools/ci/check_public_headers.py b/tools/ci/check_public_headers.py
index 2b21bae1e1..72b4fefdb9 100644
--- a/tools/ci/check_public_headers.py
+++ b/tools/ci/check_public_headers.py
@@ -2,7 +2,7 @@
 #
 # Checks all public headers in IDF in the ci
 #
-# SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
 #
 import argparse
@@ -24,6 +24,7 @@ from typing import Union
 
 class HeaderFailed(Exception):
     """Base header failure exception"""
+
     pass
 
 
@@ -62,7 +63,7 @@ class HeaderFailedContainsStaticAssert(HeaderFailed):
 
 #   Creates a temp file and returns both output as a string and a file name
 #
-def exec_cmd_to_temp_file(what: List, suffix: str='') -> Tuple[int, str, str, str, str]:
+def exec_cmd_to_temp_file(what: List, suffix: str = '') -> Tuple[int, str, str, str, str]:
     out_file = tempfile.NamedTemporaryFile(suffix=suffix, delete=False)
     rc, out, err, cmd = exec_cmd(what, out_file)
     with open(out_file.name, 'r', encoding='utf-8') as f:
@@ -70,7 +71,9 @@ def exec_cmd_to_temp_file(what: List, suffix: str='') -> Tuple[int, str, str, st
     return rc, out, err, out_file.name, cmd
 
 
-def exec_cmd(what: List, out_file: Union['tempfile._TemporaryFileWrapper[bytes]', int]=subprocess.PIPE) -> Tuple[int, str, str, str]:
+def exec_cmd(
+    what: List, out_file: Union['tempfile._TemporaryFileWrapper[bytes]', int] = subprocess.PIPE
+) -> Tuple[int, str, str, str]:
     p = subprocess.Popen(what, stdin=subprocess.PIPE, stdout=out_file, stderr=subprocess.PIPE)
     output_b, err_b = p.communicate()
     rc = p.returncode
@@ -80,12 +83,11 @@ def exec_cmd(what: List, out_file: Union['tempfile._TemporaryFileWrapper[bytes]'
 
 
 class PublicHeaderChecker:
-
-    def log(self, message: str, debug: bool=False) -> None:
+    def log(self, message: str, debug: bool = False) -> None:
         if self.verbose or debug:
             print(message)
 
-    def __init__(self, verbose: bool=False, jobs: int=1, prefix: Optional[str]=None) -> None:
+    def __init__(self, verbose: bool = False, jobs: int = 1, prefix: Optional[str] = None) -> None:
         self.gcc = '{}gcc'.format(prefix)
         self.gpp = '{}g++'.format(prefix)
         self.verbose = verbose
@@ -97,7 +99,9 @@ class PublicHeaderChecker:
         self.kconfig_macro = re.compile(r'\bCONFIG_[A-Z0-9_]+')
         self.static_assert = re.compile(r'(_Static_assert|static_assert)')
         self.defines_assert = re.compile(r'#define[ \t]+ESP_STATIC_ASSERT')
-        self.auto_soc_header = re.compile(r'components/soc/esp[a-z0-9_]+(?:/\w+)?/(include|register)/(soc|modem)/[a-zA-Z0-9_]+.h')
+        self.auto_soc_header = re.compile(
+            r'components/soc/esp[a-z0-9_]+(?:/\w+)?/(include|register)/(soc|modem|hw_ver\d+/soc)/[a-zA-Z0-9_]+.h'
+        )
         self.assembly_nocode = r'^\s*(\.file|\.text|\.ident|\.option|\.attribute|(\.section)?).*$'
         self.check_threads: List[Thread] = []
         self.stdc = '--std=c99'
@@ -109,7 +113,7 @@ class PublicHeaderChecker:
 
     def __enter__(self) -> 'PublicHeaderChecker':
         for i in range(self.jobs):
-            t = Thread(target=self.check_headers, args=(i, ))
+            t = Thread(target=self.check_headers, args=(i,))
             self.check_threads.append(t)
             t.start()
         return self
@@ -155,7 +159,9 @@ class PublicHeaderChecker:
 
     # Checks if the header contains some assembly code and whether it is compilable
     def compile_one_header_with(self, compiler: str, std_flags: str, header: str) -> None:
-        rc, out, err, cmd = exec_cmd([compiler, std_flags, '-S', '-o-', '-include', header, self.main_c] + self.include_dir_flags)
+        rc, out, err, cmd = exec_cmd(
+            [compiler, std_flags, '-S', '-o-', '-include', header, self.main_c] + self.include_dir_flags
+        )
         if rc == 0:
             if not re.sub(self.assembly_nocode, '', out, flags=re.M).isspace():
                 raise HeaderFailedContainsCode()
@@ -185,16 +191,25 @@ class PublicHeaderChecker:
     #                               - We still have some code? -> FAIL the test (our header needs extern "C")
     #                               - Only whitespaces -> header is OK (it contains only macros and directives)
     def preprocess_one_header(self, header: str, num: int) -> None:
-        all_compilation_flags = ['-w', '-P', '-E', '-DESP_PLATFORM', '-include', header, self.main_c] + self.include_dir_flags
+        all_compilation_flags = [
+            '-w',
+            '-P',
+            '-E',
+            '-DESP_PLATFORM',
+            '-include',
+            header,
+            self.main_c,
+        ] + self.include_dir_flags
         # just strip comments to check for CONFIG_... macros or static asserts
-        rc, out, err, _ = exec_cmd([self.gcc, '-fpreprocessed', '-dD',  '-P',  '-E', header] + self.include_dir_flags)
-        # we ignore the rc here, as the `-fpreprocessed` flag expects the file to have macros already expanded, so we might get some errors
-        # here we use it only to remove comments (even if the command returns non-zero code it produces the correct output)
+        rc, out, err, _ = exec_cmd([self.gcc, '-fpreprocessed', '-dD', '-P', '-E', header] + self.include_dir_flags)
+        # we ignore the rc here, as the `-fpreprocessed` flag expects the file to have macros already expanded,
+        # so we might get some errors here we use it only to remove comments (even if the command returns non-zero
+        # code it produces the correct output)
         if re.search(self.kconfig_macro, out):
             # enable defined #error if sdkconfig.h not included
             all_compilation_flags.append('-DIDF_CHECK_SDKCONFIG_INCLUDED')
-        # If the file contain _Static_assert or static_assert, make sure it doesn't not define ESP_STATIC_ASSERT and that it
-        # is not an automatically generated soc header file
+        # If the file contain _Static_assert or static_assert, make sure it doesn't not define ESP_STATIC_ASSERT
+        # and that it is not an automatically generated soc header file
         grp = re.search(self.static_assert, out)
         # Normalize the potential A//B, A/./B, A/../A, from the name
         normalized_path = os.path.normpath(header)
@@ -234,19 +249,22 @@ class PublicHeaderChecker:
                 if re.search(self.extern_c, out):
                     self.log('{} extern C present in the actual header, too - OK'.format(header))
                     return
-                # at this point we know that the header itself is missing extern-C, so we need to check if it contains an actual *code*
-                # we remove all preprocessor's directive to check if there's any code besides macros
+                # at this point we know that the header itself is missing extern-C, so we need to check if it
+                # contains an actual *code* we remove all preprocessor's directive to check if there's any code
+                # besides macros
                 macros = re.compile(r'(?m)^\s*#(?:.*\\\r?\n)*.*$')  # Matches multiline preprocessor directives
                 without_macros = macros.sub('', out)
                 if without_macros.isspace():
                     self.log("{} Header doesn't need extern-C, it's all just macros - OK".format(header))
                     return
-                # at this point we know that the header is not only composed of macro definitions, but could just contain some "harmless" macro calls
-                # let's remove them and check again
-                macros_calls = r'(.*?)ESP_STATIC_ASSERT[^;]+;'   # static assert macro only, we could add more if needed
+                # at this point we know that the header is not only composed of macro definitions, but could
+                # just contain some "harmless" macro calls let's remove them and check again
+                macros_calls = r'(.*?)ESP_STATIC_ASSERT[^;]+;'  # static assert macro only, we could add more if needed
                 without_macros = re.sub(macros_calls, '', without_macros, flags=re.DOTALL)
                 if without_macros.isspace():
-                    self.log("{} Header doesn't need extern-C, it's all macros definitions and calls - OK".format(header))
+                    self.log(
+                        "{} Header doesn't need extern-C, it's all macros definitions and calls - OK".format(header)
+                    )
                     return
 
             self.log('{} Different but no extern C - FAILED'.format(header), True)
@@ -259,7 +277,9 @@ class PublicHeaderChecker:
                 pass
 
     # Get compilation data from an example to list all public header files
-    def list_public_headers(self, ignore_dirs: List, ignore_files: Union[List, Set], only_dir: Optional[str]=None) -> None:
+    def list_public_headers(
+        self, ignore_dirs: List, ignore_files: Union[List, Set], only_dir: Optional[str] = None
+    ) -> None:
         idf_path = os.getenv('IDF_PATH')
         if idf_path is None:
             raise RuntimeError("Environment variable 'IDF_PATH' wasn't set.")
@@ -270,13 +290,14 @@ class PublicHeaderChecker:
             os.unlink(os.path.join(project_dir, 'sdkconfig'))
         except FileNotFoundError:
             pass
-        subprocess.check_call(['idf.py', '-B', build_dir, f'-DSDKCONFIG={sdkconfig}', '-DCOMPONENTS=', 'reconfigure'],
-                              cwd=project_dir)
+        subprocess.check_call(
+            ['idf.py', '-B', build_dir, f'-DSDKCONFIG={sdkconfig}', '-DCOMPONENTS=', 'reconfigure'], cwd=project_dir
+        )
 
         def get_std(json: List, extension: str) -> str:
             # compile commands for the files with specified extension, containing C(XX) standard flag
             command = [c for c in j if c['file'].endswith('.' + extension) and '-std=' in c['command']][0]
-            return str([s for s in command['command'].split() if 'std=' in s][0])     # grab the std flag
+            return str([s for s in command['command'].split() if 'std=' in s][0])  # grab the std flag
 
         build_commands_json = os.path.join(build_dir, 'compile_commands.json')
         with open(build_commands_json, 'r', encoding='utf-8') as f:
@@ -293,7 +314,9 @@ class PublicHeaderChecker:
                 if 'components' in item:
                     include_dirs.append(item[2:])  # Removing the leading "-I"
             if item.startswith('-D'):
-                include_dir_flags.append(item.replace('\\',''))  # removes escaped quotes, eg: -DMBEDTLS_CONFIG_FILE=\\\"mbedtls/esp_config.h\\\"
+                include_dir_flags.append(
+                    item.replace('\\', '')
+                )  # removes escaped quotes, eg: -DMBEDTLS_CONFIG_FILE=\\\"mbedtls/esp_config.h\\\"
         include_dir_flags.append('-I' + os.path.join(build_dir, 'config'))
         include_dir_flags.append('-DCI_HEADER_CHECK')
         sdkconfig_h = os.path.join(build_dir, 'config', 'sdkconfig.h')
@@ -302,14 +325,18 @@ class PublicHeaderChecker:
             f.write('#define IDF_SDKCONFIG_INCLUDED')
         main_c = os.path.join(build_dir, 'compile.c')
         with open(main_c, 'w') as f:
-            f.write('#if defined(IDF_CHECK_SDKCONFIG_INCLUDED) && ! defined(IDF_SDKCONFIG_INCLUDED)\n'
-                    '#error CONFIG_VARS_USED_WHILE_SDKCONFIG_NOT_INCLUDED\n'
-                    '#endif')
+            f.write(
+                '#if defined(IDF_CHECK_SDKCONFIG_INCLUDED) && ! defined(IDF_SDKCONFIG_INCLUDED)\n'
+                '#error CONFIG_VARS_USED_WHILE_SDKCONFIG_NOT_INCLUDED\n'
+                '#endif'
+            )
         # processes public include dirs, removing ignored files
         all_include_files = []
         files_to_check = []
         for d in include_dirs:
-            if only_dir is not None and not os.path.relpath(d, idf_path).startswith(os.path.relpath(only_dir, idf_path)):
+            if only_dir is not None and not os.path.relpath(d, idf_path).startswith(
+                os.path.relpath(only_dir, idf_path)
+            ):
                 self.log('{} - directory ignored (not in "{}")'.format(d, only_dir))
                 continue
             if os.path.relpath(d, idf_path).startswith(tuple(ignore_dirs)):
@@ -338,7 +365,10 @@ class PublicHeaderChecker:
 
 
 def check_all_headers() -> None:
-    parser = argparse.ArgumentParser('Public header checker file', formatter_class=argparse.RawDescriptionHelpFormatter, epilog='''\
+    parser = argparse.ArgumentParser(
+        'Public header checker file',
+        formatter_class=argparse.RawDescriptionHelpFormatter,
+        epilog="""\
     Tips for fixing failures reported by this script
     ------------------------------------------------
     This checker validates all public headers to detect these types of issues:
@@ -367,11 +397,14 @@ def check_all_headers() -> None:
     * Use "-v" argument to produce more verbose output
     * Copy, paste and execute the compilation commands to reproduce build errors (script prints out
       the entire compilation command line with absolute paths)
-    ''')
+    """,
+    )
     parser.add_argument('--verbose', '-v', help='enables verbose mode', action='store_true')
     parser.add_argument('--jobs', '-j', help='number of jobs to run checker', default=1, type=int)
     parser.add_argument('--prefix', '-p', help='compiler prefix', default='xtensa-esp32-elf-', type=str)
-    parser.add_argument('--exclude-file', '-e', help='exception file', default='check_public_headers_exceptions.txt', type=str)
+    parser.add_argument(
+        '--exclude-file', '-e', help='exception file', default='check_public_headers_exceptions.txt', type=str
+    )
     parser.add_argument('--only-dir', '-d', help='reduce the analysis to this directory only', default=None, type=str)
     args = parser.parse_args()